Repository: daveshah1/CSI2Rx Branch: master Commit: 582f870d3140 Files: 350 Total size: 52.1 MB Directory structure: gitextract_o_fqoapy/ ├── LICENSE ├── README.md ├── misc/ │ └── caminit/ │ ├── .gitignore │ └── picam_init.cc ├── verilog_cores/ │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── csi/ │ │ ├── header_ecc.v │ │ └── rx_packet_handler.v │ ├── csi2.core │ ├── link/ │ │ └── csi_rx_ice40.v │ ├── misc/ │ │ └── downsample.v │ ├── phy/ │ │ ├── byte_aligner.v │ │ ├── dphy_iserdes.v │ │ ├── dphy_oserdes.v │ │ └── word_combiner.v │ └── test/ │ └── icebreaker/ │ ├── .gitignore │ ├── Makefile │ ├── constraints.py │ ├── icecam.pcf │ ├── top.v │ └── uart.v └── vhdl_rx/ ├── .gitignore ├── LICENSE.notes ├── README.md ├── demo-top/ │ ├── framebuffer_top.vhd │ ├── mig_a.prj │ └── ov13850_demo.vhd ├── dvi-tx/ │ ├── dvi_tx_clk_drv.vhd │ ├── dvi_tx_tmds_enc.vhd │ ├── dvi_tx_tmds_phy.vhd │ └── dvi_tx_top.vhd ├── examples/ │ ├── .gitignore │ └── ov13850_demo/ │ ├── ov13850_demo.cache/ │ │ └── ip/ │ │ ├── 54144841a4506c29/ │ │ │ ├── 54144841a4506c29.xci │ │ │ ├── dvi_pll_sim_netlist.v │ │ │ └── dvi_pll_stub.v │ │ ├── 548aa35948ad692b/ │ │ │ ├── 548aa35948ad692b.xci │ │ │ ├── camera_pll_sim_netlist.v │ │ │ └── camera_pll_stub.v │ │ └── 75280199e9655e6a/ │ │ ├── 75280199e9655e6a.xci │ │ ├── dvi_pll_sim_netlist.v │ │ └── dvi_pll_stub.v │ ├── ov13850_demo.ip_user_files/ │ │ ├── ip/ │ │ │ ├── camera_pll/ │ │ │ │ └── camera_pll_stub.v │ │ │ ├── ddr3_if/ │ │ │ │ └── ddr3_if_stub.v │ │ │ ├── dvi_pll/ │ │ │ │ └── dvi_pll_stub.v │ │ │ ├── ila_0/ │ │ │ │ └── ila_0_stub.v │ │ │ ├── input_line_buffer/ │ │ │ │ └── input_line_buffer_stub.v │ │ │ └── output_line_buffer/ │ │ │ └── output_line_buffer_stub.v │ │ ├── ipstatic/ │ │ │ ├── hdl/ │ │ │ │ ├── fifo_generator_v13_1_rfs.v │ │ │ │ └── fifo_generator_v13_1_rfs.vhd │ │ │ └── simulation/ │ │ │ ├── blk_mem_gen_v8_3.v │ │ │ └── fifo_generator_vlog_beh.v │ │ ├── mem_init_files/ │ │ │ ├── mig_a.prj │ │ │ └── mig_b.prj │ │ └── sim_scripts/ │ │ ├── camera_pll_1/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ ├── vcs/ │ │ │ │ └── glbl.v │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── ddr3_if/ │ │ │ ├── activehdl/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_b.prj │ │ │ ├── ies/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_b.prj │ │ │ ├── modelsim/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_b.prj │ │ │ ├── questa/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_b.prj │ │ │ ├── riviera/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_b.prj │ │ │ ├── vcs/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_b.prj │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ └── vlog.prj │ │ ├── ddr3_if_1/ │ │ │ ├── activehdl/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_a.prj │ │ │ ├── ies/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_a.prj │ │ │ ├── modelsim/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_a.prj │ │ │ ├── questa/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_a.prj │ │ │ ├── riviera/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_a.prj │ │ │ ├── vcs/ │ │ │ │ ├── glbl.v │ │ │ │ └── mig_a.prj │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ ├── mig_a.prj │ │ │ └── vlog.prj │ │ ├── dvi_pll_1/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ ├── vcs/ │ │ │ │ └── glbl.v │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── framebuffer-ctrl/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ └── vcs/ │ │ │ └── glbl.v │ │ ├── ila_0/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ ├── vcs/ │ │ │ │ └── glbl.v │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── input_line_buffer/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ ├── vcs/ │ │ │ │ └── glbl.v │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── input_line_buffer_1/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ ├── vcs/ │ │ │ │ └── glbl.v │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── output_line_buffer/ │ │ │ ├── activehdl/ │ │ │ │ └── glbl.v │ │ │ ├── ies/ │ │ │ │ └── glbl.v │ │ │ ├── modelsim/ │ │ │ │ └── glbl.v │ │ │ ├── questa/ │ │ │ │ └── glbl.v │ │ │ ├── riviera/ │ │ │ │ └── glbl.v │ │ │ ├── vcs/ │ │ │ │ └── glbl.v │ │ │ └── xsim/ │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ └── output_line_buffer_1/ │ │ ├── activehdl/ │ │ │ └── glbl.v │ │ ├── ies/ │ │ │ └── glbl.v │ │ ├── modelsim/ │ │ │ └── glbl.v │ │ ├── questa/ │ │ │ └── glbl.v │ │ ├── riviera/ │ │ │ └── glbl.v │ │ ├── vcs/ │ │ │ └── glbl.v │ │ └── xsim/ │ │ ├── cmd.tcl │ │ ├── glbl.v │ │ └── vlog.prj │ ├── ov13850_demo.runs/ │ │ ├── camera_pll_synth_1/ │ │ │ ├── camera_pll.tcl │ │ │ └── dont_touch.xdc │ │ ├── ddr3_if_synth_1/ │ │ │ └── ddr3_if.tcl │ │ ├── dvi_pll_synth_1/ │ │ │ ├── dont_touch.xdc │ │ │ └── dvi_pll.tcl │ │ ├── impl_1/ │ │ │ └── ov13850_demo.tcl │ │ ├── input_line_buffer_synth_1/ │ │ │ ├── dont_touch.xdc │ │ │ ├── input_line_buffer.tcl │ │ │ ├── input_line_buffer_sim_netlist.v │ │ │ └── input_line_buffer_stub.v │ │ ├── output_line_buffer_synth_1/ │ │ │ ├── dont_touch.xdc │ │ │ ├── output_line_buffer.tcl │ │ │ ├── output_line_buffer_sim_netlist.v │ │ │ └── output_line_buffer_stub.v │ │ └── synth_1/ │ │ ├── .Xil/ │ │ │ └── ov13850_demo_propImpl.xdc │ │ └── ov13850_demo.tcl │ ├── ov13850_demo.sim/ │ │ └── sim_1/ │ │ └── synth/ │ │ └── func/ │ │ ├── genesys2_fbtest.tcl │ │ ├── genesys2_fbtest_func_synth.v │ │ └── genesys2_fbtest_vlog.prj │ ├── ov13850_demo.srcs/ │ │ ├── constrs_1/ │ │ │ └── imports/ │ │ │ ├── constraints/ │ │ │ │ └── ddr3_if.xdc │ │ │ └── new/ │ │ │ └── genesys2.xdc │ │ └── sources_1/ │ │ └── ip/ │ │ ├── camera_pll_1/ │ │ │ ├── camera_pll.v │ │ │ ├── camera_pll.xci │ │ │ ├── camera_pll.xdc │ │ │ ├── camera_pll_board.xdc │ │ │ ├── camera_pll_clk_wiz.v │ │ │ ├── camera_pll_ooc.xdc │ │ │ ├── camera_pll_sim_netlist.v │ │ │ └── camera_pll_stub.v │ │ ├── ddr3_if/ │ │ │ ├── mig_a.prj │ │ │ └── mig_b.prj │ │ ├── ddr3_if_1/ │ │ │ ├── ddr3_if/ │ │ │ │ └── user_design/ │ │ │ │ ├── constraints/ │ │ │ │ │ ├── ddr3_if.xdc │ │ │ │ │ └── ddr3_if_ooc.xdc │ │ │ │ └── rtl/ │ │ │ │ ├── axi/ │ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_addr_decode.v │ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_read.v │ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg.v │ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg_bank.v │ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_top.v │ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_write.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_ar_channel.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_aw_channel.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_b_channel.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_arbiter.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_fsm.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_translator.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_fifo.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_incr_cmd.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_r_channel.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_simple_fifo.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_w_channel.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_wr_cmd_fsm.v │ │ │ │ │ ├── mig_7series_v4_0_axi_mc_wrap_cmd.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_a_upsizer.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_axi_register_slice.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_axi_upsizer.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_axic_register_slice.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_and.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_and.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_or.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_or.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_command_fifo.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel_static.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_r_upsizer.v │ │ │ │ │ └── mig_7series_v4_0_ddr_w_upsizer.v │ │ │ │ ├── clocking/ │ │ │ │ │ ├── mig_7series_v4_0_clk_ibuf.v │ │ │ │ │ ├── mig_7series_v4_0_infrastructure.v │ │ │ │ │ ├── mig_7series_v4_0_iodelay_ctrl.v │ │ │ │ │ └── mig_7series_v4_0_tempmon.v │ │ │ │ ├── controller/ │ │ │ │ │ ├── mig_7series_v4_0_arb_mux.v │ │ │ │ │ ├── mig_7series_v4_0_arb_row_col.v │ │ │ │ │ ├── mig_7series_v4_0_arb_select.v │ │ │ │ │ ├── mig_7series_v4_0_bank_cntrl.v │ │ │ │ │ ├── mig_7series_v4_0_bank_common.v │ │ │ │ │ ├── mig_7series_v4_0_bank_compare.v │ │ │ │ │ ├── mig_7series_v4_0_bank_mach.v │ │ │ │ │ ├── mig_7series_v4_0_bank_queue.v │ │ │ │ │ ├── mig_7series_v4_0_bank_state.v │ │ │ │ │ ├── mig_7series_v4_0_col_mach.v │ │ │ │ │ ├── mig_7series_v4_0_mc.v │ │ │ │ │ ├── mig_7series_v4_0_rank_cntrl.v │ │ │ │ │ ├── mig_7series_v4_0_rank_common.v │ │ │ │ │ ├── mig_7series_v4_0_rank_mach.v │ │ │ │ │ └── mig_7series_v4_0_round_robin_arb.v │ │ │ │ ├── ddr3_if.v │ │ │ │ ├── ddr3_if_mig.v │ │ │ │ ├── ddr3_if_mig_sim.v │ │ │ │ ├── ecc/ │ │ │ │ │ ├── mig_7series_v4_0_ecc_buf.v │ │ │ │ │ ├── mig_7series_v4_0_ecc_dec_fix.v │ │ │ │ │ ├── mig_7series_v4_0_ecc_gen.v │ │ │ │ │ ├── mig_7series_v4_0_ecc_merge_enc.v │ │ │ │ │ └── mig_7series_v4_0_fi_xor.v │ │ │ │ ├── ip_top/ │ │ │ │ │ ├── mig_7series_v4_0_mem_intfc.v │ │ │ │ │ └── mig_7series_v4_0_memc_ui_top_axi.v │ │ │ │ ├── phy/ │ │ │ │ │ ├── mig_7series_v4_0_ddr_byte_group_io.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_byte_lane.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_calib_top.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_if_post_fifo.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy_wrapper.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_of_pre_fifo.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_4lanes.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_init.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_cntlr.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_data.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_edge.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_lim.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_mux.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_samp.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_oclkdelay_cal.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_prbs_rdlvl.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_rdlvl.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_tempmon.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_top.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrcal.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_0_ddr_skip_calib_tap.v │ │ │ │ │ ├── mig_7series_v4_0_poc_cc.v │ │ │ │ │ ├── mig_7series_v4_0_poc_edge_store.v │ │ │ │ │ ├── mig_7series_v4_0_poc_meta.v │ │ │ │ │ ├── mig_7series_v4_0_poc_pd.v │ │ │ │ │ ├── mig_7series_v4_0_poc_tap_base.v │ │ │ │ │ └── mig_7series_v4_0_poc_top.v │ │ │ │ └── ui/ │ │ │ │ ├── mig_7series_v4_0_ui_cmd.v │ │ │ │ ├── mig_7series_v4_0_ui_rd_data.v │ │ │ │ ├── mig_7series_v4_0_ui_top.v │ │ │ │ └── mig_7series_v4_0_ui_wr_data.v │ │ │ ├── ddr3_if.xci │ │ │ ├── ddr3_if_sim_netlist.v │ │ │ ├── ddr3_if_stub.v │ │ │ └── mig_a.prj │ │ ├── dvi_pll_1/ │ │ │ ├── dvi_pll.v │ │ │ ├── dvi_pll.xci │ │ │ ├── dvi_pll.xdc │ │ │ ├── dvi_pll_board.xdc │ │ │ ├── dvi_pll_clk_wiz.v │ │ │ ├── dvi_pll_ooc.xdc │ │ │ ├── dvi_pll_sim_netlist.v │ │ │ └── dvi_pll_stub.v │ │ ├── input_line_buffer_1/ │ │ │ ├── hdl/ │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ ├── input_line_buffer.xci │ │ │ ├── input_line_buffer_ooc.xdc │ │ │ ├── input_line_buffer_sim_netlist.v │ │ │ ├── input_line_buffer_stub.v │ │ │ ├── misc/ │ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ │ ├── sim/ │ │ │ │ └── input_line_buffer.v │ │ │ ├── simulation/ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ └── synth/ │ │ │ └── input_line_buffer.vhd │ │ └── output_line_buffer_1/ │ │ ├── hdl/ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── misc/ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ ├── output_line_buffer.xci │ │ ├── output_line_buffer_ooc.xdc │ │ ├── output_line_buffer_sim_netlist.v │ │ ├── output_line_buffer_stub.v │ │ ├── sim/ │ │ │ └── output_line_buffer.v │ │ ├── simulation/ │ │ │ └── blk_mem_gen_v8_3.v │ │ └── synth/ │ │ └── output_line_buffer.vhd │ └── ov13850_demo.xpr ├── framebuffer-ctrl/ │ ├── framebuffer_ctrl.vhd │ ├── input_line_buffer.xci │ └── output_line_buffer.xci ├── mipi-csi-rx/ │ ├── csi_rx_10bit_unpack.vhd │ ├── csi_rx_4_lane_link.vhd │ ├── csi_rx_byte_align.vhd │ ├── csi_rx_clock_det.vhd │ ├── csi_rx_hdr_ecc.vhd │ ├── csi_rx_hs_clk_phy.vhd │ ├── csi_rx_hs_lane_phy.vhd │ ├── csi_rx_idelayctrl_gen.vhd │ ├── csi_rx_line_buffer.vhd │ ├── csi_rx_packet_handler.vhd │ ├── csi_rx_top.vhd │ ├── csi_rx_video_output.vhd │ ├── csi_rx_word_align.vhd │ └── synth.ys ├── ov-cam-control/ │ ├── manual_focus.vhd │ ├── ov13850_4k_regs.vhd │ ├── ov13850_control_top.vhd │ ├── ov16825_1080p120_regs.vhd │ ├── ov_i2c_control.vhd │ └── vcm_i2c_control.vhd └── video-misc/ ├── image_gain_wb.vhd ├── simple_debayer.vhd ├── test_pattern_gen.vhd ├── video_fb_output.vhd ├── video_register.vhd └── video_timing_ctrl.vhd ================================================ FILE CONTENTS ================================================ ================================================ FILE: LICENSE ================================================ MIT License Copyright (c) 2016-2018 David Shah Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ================================================ FILE: README.md ================================================ # MIPI CSI-2 IP Cores The _vhdl\_rx_ folder contains a tried-and-tested high performance CSI-2 receiver core in VHDL. This can handle 4k video at over 30fps (most likely 60fps with a suitable camera module). This has been tested with the OV13850 camera module with a Xilinx Kintex-7 FPGA. It is currently limited to a 4-lane and 10bpp without modification, other parameters such as timing can be modified at compile time. Also in this folder are an example project and some miscellaneous VHDL support IP such as an AXI-4 framebuffer controller. The _verilog\_cores_ contains work-in-progress CSI-2 transmit and receive cores in Verilog. These are designed to be more flexible and run on a variety of platforms. The first target will be 640x480 video using a Raspberry Pi camera with an iCE40 FPGA. All cores are licensed under the MIT License, see LICENSE for details. ================================================ FILE: misc/caminit/.gitignore ================================================ /caminit ================================================ FILE: misc/caminit/picam_init.cc ================================================ // Simple I2C using MPSSE bitbang implementation (passed thru FPGA) to initialise a PiCam2 // Some code taken from iceprog #include #include #include static struct ftdi_context ftdic; static bool ftdic_open = false; static bool verbose = false; static bool ftdic_latency_set = false; static unsigned char ftdi_latency; /* MPSSE engine command definitions */ enum mpsse_cmd { /* Mode commands */ MC_SETB_LOW = 0x80, /* Set Data bits LowByte */ MC_READB_LOW = 0x81, /* Read Data bits LowByte */ MC_SETB_HIGH = 0x82, /* Set Data bits HighByte */ MC_READB_HIGH = 0x83, /* Read data bits HighByte */ MC_LOOPBACK_EN = 0x84, /* Enable loopback */ MC_LOOPBACK_DIS = 0x85, /* Disable loopback */ MC_SET_CLK_DIV = 0x86, /* Set clock divisor */ MC_FLUSH = 0x87, /* Flush buffer fifos to the PC. */ MC_WAIT_H = 0x88, /* Wait on GPIOL1 to go high. */ MC_WAIT_L = 0x89, /* Wait on GPIOL1 to go low. */ MC_TCK_X5 = 0x8A, /* Disable /5 div, enables 60MHz master clock */ MC_TCK_D5 = 0x8B, /* Enable /5 div, backward compat to FT2232D */ MC_EN_3PH_CLK = 0x8C, /* Enable 3 phase clk, DDR I2C */ MC_DIS_3PH_CLK = 0x8D, /* Disable 3 phase clk */ MC_CLK_N = 0x8E, /* Clock every bit, used for JTAG */ MC_CLK_N8 = 0x8F, /* Clock every byte, used for JTAG */ MC_CLK_TO_H = 0x94, /* Clock until GPIOL1 goes high */ MC_CLK_TO_L = 0x95, /* Clock until GPIOL1 goes low */ MC_EN_ADPT_CLK = 0x96, /* Enable adaptive clocking */ MC_DIS_ADPT_CLK = 0x97, /* Disable adaptive clocking */ MC_CLK8_TO_H = 0x9C, /* Clock until GPIOL1 goes high, count bytes */ MC_CLK8_TO_L = 0x9D, /* Clock until GPIOL1 goes low, count bytes */ MC_TRI = 0x9E, /* Set IO to only drive on 0 and tristate on 1 */ /* CPU mode commands */ MC_CPU_RS = 0x90, /* CPUMode read short address */ MC_CPU_RE = 0x91, /* CPUMode read extended address */ MC_CPU_WS = 0x92, /* CPUMode write short address */ MC_CPU_WE = 0x93, /* CPUMode write extended address */ }; static void check_rx() { while (1) { uint8_t data; int rc = ftdi_read_data(&ftdic, &data, 1); if (rc <= 0) break; fprintf(stderr, "unexpected rx byte: %02X\n", data); } } static void error(int status) { check_rx(); fprintf(stderr, "ABORT.\n"); if (ftdic_open) { if (ftdic_latency_set) ftdi_set_latency_timer(&ftdic, ftdi_latency); ftdi_usb_close(&ftdic); } ftdi_deinit(&ftdic); exit(status); } static uint8_t recv_byte() { uint8_t data; while (1) { int rc = ftdi_read_data(&ftdic, &data, 1); if (rc < 0) { fprintf(stderr, "Read error.\n"); error(2); } if (rc == 1) break; usleep(100); } return data; } static void send_byte(uint8_t data) { int rc = ftdi_write_data(&ftdic, &data, 1); if (rc != 1) { fprintf(stderr, "Write error (single byte, rc=%d, expected %d).\n", rc, 1); error(2); } } static void set_gpio(bool sda, bool scl) { uint8_t gpio = 0; if (sda) gpio |= 0x01; //BDBUS0 if (scl) gpio |= 0x02; //BDBUS1 send_byte(MC_SETB_LOW); send_byte(gpio); send_byte(0x03); //both outputs } static void i2c_start() { set_gpio(1, 1); set_gpio(0, 1); set_gpio(0, 0); } static void i2c_send(uint8_t data) { for (int i = 7; i >= 0; i--) { bool bit = (data >> i) & 0x1; set_gpio(bit, 0); set_gpio(bit, 1); set_gpio(bit, 0); } set_gpio(1, 0); set_gpio(1, 1); set_gpio(1, 0); } static void i2c_stop() { set_gpio(0, 0); set_gpio(0, 1); set_gpio(1, 1); } static void write_cmos_sensor(uint16_t addr, uint8_t value) { fprintf(stderr, "cam[0x%04X] <= 0x%02X\n", addr, value); i2c_start(); i2c_send(0x10 << 1); i2c_send((addr >> 8) & 0xFF); i2c_send(addr & 0xFF); i2c_send(value); i2c_stop(); } const int framelength = 666; const int linelength = 3448; static void cam_init() { // Based on "Preview Setting" from a Linux driver write_cmos_sensor(0x0100, 0x00); //standby mode write_cmos_sensor(0x30EB, 0x05); //mfg specific access begin write_cmos_sensor(0x30EB, 0x0C); // write_cmos_sensor(0x300A, 0xFF); // write_cmos_sensor(0x300B, 0xFF); // write_cmos_sensor(0x30EB, 0x05); // write_cmos_sensor(0x30EB, 0x09); //mfg specific access end write_cmos_sensor(0x0114, 0x01); //CSI_LANE_MODE: 2-lane write_cmos_sensor(0x0128, 0x00); //DPHY_CTRL: auto mode (?) write_cmos_sensor(0x012A, 0x18); //EXCK_FREQ[15:8] = 24MHz write_cmos_sensor(0x012B, 0x00); //EXCK_FREQ[7:0] write_cmos_sensor(0x0160, ((framelength >> 8) & 0xFF)); //framelength write_cmos_sensor(0x0161, (framelength & 0xFF)); write_cmos_sensor(0x0162, ((linelength >> 8) & 0xFF)); write_cmos_sensor(0x0163, (linelength & 0xFF)); write_cmos_sensor(0x0164, 0x00); //X_ADD_STA_A[11:8] write_cmos_sensor(0x0165, 0x00); //X_ADD_STA_A[7:0] write_cmos_sensor(0x0166, 0x0A); //X_ADD_END_A[11:8] write_cmos_sensor(0x0167, 0x00); //X_ADD_END_A[7:0] write_cmos_sensor(0x0168, 0x00); //Y_ADD_STA_A[11:8] write_cmos_sensor(0x0169, 0x00); //Y_ADD_STA_A[7:0] write_cmos_sensor(0x016A, 0x07); //Y_ADD_END_A[11:8] write_cmos_sensor(0x016B, 0x80); //Y_ADD_END_A[7:0] write_cmos_sensor(0x016C, 0x02); //x_output_size[11:8] = 640 write_cmos_sensor(0x016D, 0x80); //x_output_size[7:0] write_cmos_sensor(0x016E, 0x01); //y_output_size[11:8] = 480 write_cmos_sensor(0x016F, 0xE0); //y_output_size[7:0] write_cmos_sensor(0x0170, 0x01); //X_ODD_INC_A write_cmos_sensor(0x0171, 0x01); //Y_ODD_INC_A write_cmos_sensor(0x0174, 0x02); //BINNING_MODE_H_A = x4-binning write_cmos_sensor(0x0175, 0x02); //BINNING_MODE_V_A = x4-binning write_cmos_sensor(0x018C, 0x08); //CSI_DATA_FORMAT_A[15:8] write_cmos_sensor(0x018D, 0x08); //CSI_DATA_FORMAT_A[7:0] write_cmos_sensor(0x0301, 0x08); //VTPXCK_DIV write_cmos_sensor(0x0303, 0x01); //VTSYCK_DIV write_cmos_sensor(0x0304, 0x03); //PREPLLCK_VT_DIV write_cmos_sensor(0x0305, 0x03); //PREPLLCK_OP_DIV write_cmos_sensor(0x0306, 0x00); //PLL_VT_MPY[10:8] write_cmos_sensor(0x0307, 0x14); //PLL_VT_MPY[7:0] write_cmos_sensor(0x0309, 0x08); //OPPXCK_DIV write_cmos_sensor(0x030B, 0x02); //OPSYCK_DIV write_cmos_sensor(0x030C, 0x00); //PLL_OP_MPY[10:8] write_cmos_sensor(0x030D, 0x0A); //PLL_OP_MPY[7:0] write_cmos_sensor(0x455E, 0x00); //?? write_cmos_sensor(0x471E, 0x4B); //?? write_cmos_sensor(0x4767, 0x0F); //?? write_cmos_sensor(0x4750, 0x14); //?? write_cmos_sensor(0x4540, 0x00); //?? write_cmos_sensor(0x47B4, 0x14); //?? write_cmos_sensor(0x4713, 0x30); //?? write_cmos_sensor(0x478B, 0x10); //?? write_cmos_sensor(0x478F, 0x10); //?? write_cmos_sensor(0x4793, 0x10); //?? write_cmos_sensor(0x4797, 0x0E); //?? write_cmos_sensor(0x479B, 0x0E); //?? //write_cmos_sensor(0x0157, 232); // ANA_GAIN_GLOBAL_A //write_cmos_sensor(0x0257, 232); // ANA_GAIN_GLOBAL_B //write_cmos_sensor(0x0600, 0x00); // Test pattern: disable //write_cmos_sensor(0x0601, 0x00); // Test pattern: disable #if 0 write_cmos_sensor(0x0600, 0x00); // Test pattern: solid colour write_cmos_sensor(0x0601, 0x01); // write_cmos_sensor(0x0602, 0x02); // Test pattern: red write_cmos_sensor(0x0603, 0xAA); // write_cmos_sensor(0x0604, 0x02); // Test pattern: greenR write_cmos_sensor(0x0605, 0xAA); // write_cmos_sensor(0x0606, 0x02); // Test pattern: blue write_cmos_sensor(0x0607, 0xAA); // write_cmos_sensor(0x0608, 0x02); // Test pattern: greenB write_cmos_sensor(0x0609, 0xAA); // write_cmos_sensor(0x0624, 0x0A); // Test pattern width write_cmos_sensor(0x0625, 0x00); // write_cmos_sensor(0x0626, 0x07); // Test pattern height write_cmos_sensor(0x0627, 0x80); // #endif write_cmos_sensor(0x0100, 0x01); } int main() { enum ftdi_interface ifnum = INTERFACE_B; fprintf(stderr, "init..\n"); ftdi_init(&ftdic); ftdi_set_interface(&ftdic, ifnum); if (ftdi_usb_open(&ftdic, 0x0403, 0x6010) && ftdi_usb_open(&ftdic, 0x0403, 0x6014)) { fprintf(stderr, "Can't find FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).\n"); error(2); } if (ftdi_usb_reset(&ftdic)) { fprintf(stderr, "Failed to reset FTDI USB device.\n"); error(2); } if (ftdi_usb_purge_buffers(&ftdic)) { fprintf(stderr, "Failed to purge buffers on FTDI USB device.\n"); error(2); } if (ftdi_get_latency_timer(&ftdic, &ftdi_latency) < 0) { fprintf(stderr, "Failed to get latency timer (%s).\n", ftdi_get_error_string(&ftdic)); error(2); } /* 1 is the fastest polling, it means 1 kHz polling */ if (ftdi_set_latency_timer(&ftdic, 1) < 0) { fprintf(stderr, "Failed to set latency timer (%s).\n", ftdi_get_error_string(&ftdic)); error(2); } if (ftdi_set_bitmode(&ftdic, 0xff, BITMODE_MPSSE) < 0) { fprintf(stderr, "Failed to set BITMODE_MPSSE on iCE FTDI USB device.\n"); error(2); } // enable clock divide by 5 send_byte(MC_TCK_D5); // set 6 MHz clock send_byte(MC_SET_CLK_DIV); send_byte(0x00); send_byte(0x00); cam_init(); } ================================================ FILE: verilog_cores/.gitignore ================================================ *.o work/ *.cf *.blif *.json ================================================ FILE: verilog_cores/Makefile ================================================ SOURCES=$(wildcard phy/*.v csi/*.v link/*.v) LINT_TOP=csi_rx_ice40 # temp SYN_TOP=csi_rx_ice40 lint: $(SOURCES) verilator --top-module $(LINT_TOP) --lint-only $^ /usr/local/share/yosys/ice40/cells_sim.v syn: $(SOURCES) yosys -p "synth_ice40 -top ${SYN_TOP} -blif top.blif" $^ .PHONY: lint syn ================================================ FILE: verilog_cores/README.md ================================================ # Verilog MIPI CSI-2 Cores - WIP ================================================ FILE: verilog_cores/csi/header_ecc.v ================================================ /** * The MIT License * Copyright (c) 2016-2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /** * MIPI CSI-2 header ECC computation */ module csi_header_ecc ( input [23:0] data, output [7:0] ecc ); assign ecc[7:6] = 2'b00; assign ecc[5] = data[10] ^ data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[21] ^ data[22] ^ data[23]; assign ecc[4] = data[4] ^ data[5] ^ data[6] ^ data[7] ^ data[8] ^ data[9] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[20] ^ data[22] ^ data[23]; assign ecc[3] = data[1] ^ data[2] ^ data[3] ^ data[7] ^ data[8] ^ data[9] ^ data[13] ^ data[14] ^ data[15] ^ data[19] ^ data[20] ^ data[21] ^ data[23]; assign ecc[2] = data[0] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ data[9] ^ data[11] ^ data[12] ^ data[15] ^ data[18] ^ data[20] ^ data[21] ^ data[22]; assign ecc[1] = data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[6] ^ data[8] ^ data[10] ^ data[12] ^ data[14] ^ data[17] ^ data[20] ^ data[21] ^ data[22] ^ data[23]; assign ecc[0] = data[0] ^ data[1] ^ data[2] ^ data[4] ^ data[5] ^ data[7] ^ data[10] ^ data[11] ^ data[13] ^ data[16] ^ data[20] ^ data[21] ^ data[22] ^ data[23]; endmodule ================================================ FILE: verilog_cores/csi/rx_packet_handler.v ================================================ /** * The MIT License * Copyright (c) 2016-2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /** * MIPI CSI-2 receive packet handler * * This controls wait_for_sync and packet_done handshaking with * byte/word aligners; keeps track of whether in frame * by detecting FS/FE; and extracts video payload from long packets */ module csi_rx_packet_handler #( parameter [1:0] VC = 2'b00, // MIPI CSI-2 "virtual channel" parameter [5:0] FS_DT = 6'h00, // Frame start data type parameter [5:0] FE_DT = 6'h01, // Frame end data type parameter [5:0] VIDEO_DT = 6'h2A, // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw) parameter [15:0] MAX_LEN = 8192 // Max expected packet len, used as timeout ) ( input clock, // byte/word clock input reset, // active high sync reset input enable, // active high clock enable input [31:0] data, // data from word aligner input data_enable, // data enable for less than 4-lane links input data_frame, // data framing from word combiner input lp_detect, // D-PHY LP mode detection, forces EoP output sync_wait, // sync wait output to byte/word handlers output packet_done, // packet done output to word combiner output reg [31:0] payload, // payload output output reg payload_enable, // payload data enable output reg payload_frame, // payload framing output reg vsync, // quasi-vsync for FS signal output reg in_frame, output reg in_line ); wire [1:0] hdr_vc; wire [5:0] hdr_dt; wire [15:0] hdr_packet_len; wire [7:0] hdr_ecc, expected_ecc; wire long_packet, valid_packet; wire is_hdr; reg [15:0] packet_len; reg [2:0] state; reg [15:0] bytes_read; always @(posedge clock) begin if (reset) begin state <= 3'b000; packet_len <= 0; bytes_read <= 0; payload <= 0; payload_enable <= 0; payload_frame <= 0; vsync <= 0; in_frame <= 0; in_line <= 0; end else if (enable) begin if (lp_detect) begin state <= 3'b000; end else begin case (state) 3'b000: state <= 3'b001; // init 3'b001: begin // wait for start bytes_read <= 0; if (data_enable) begin packet_len <= hdr_packet_len; if (long_packet && valid_packet) state <= 3'b010; else state <= 3'b011; end end 3'b010: begin // rx long packet if (data_enable) begin if ((bytes_read < (packet_len - 4)) && (bytes_read < MAX_LEN)) bytes_read <= bytes_read + 4; else state <= 3'b011; end end 3'b011: state <= 3'b100; // end of packet, assert packet_done 3'b100: state <= 3'b001; // wait one cycle and reset default: state <= 3'b000; endcase end if (is_hdr && hdr_dt == FS_DT && valid_packet) in_frame <= 1'b1; else if (is_hdr && hdr_dt == FE_DT && valid_packet) in_frame <= 1'b0; if (is_hdr && hdr_dt == VIDEO_DT && valid_packet) in_line <= 1'b1; else if (state != 3'b010 && state != 3'b001) in_line <= 1'b0; vsync <= (is_hdr && hdr_dt == FS_DT && valid_packet); payload <= data; payload_frame <= (state == 3'b010); payload_enable <= (state == 3'b010) && data_enable; end end assign hdr_vc = data[7:6]; assign hdr_dt = data[5:0]; assign hdr_packet_len = data[23:8]; assign hdr_ecc = data[31:24]; csi_header_ecc ecc_i ( .data(data[23:0]), .ecc(expected_ecc) ); assign long_packet = hdr_dt > 6'h0F; assign valid_packet = (hdr_vc == VC) && (hdr_dt == FS_DT || hdr_dt == FE_DT || hdr_dt == VIDEO_DT) && (hdr_ecc == expected_ecc); assign is_hdr = data_enable && (state == 3'b001); assign sync_wait = (state == 3'b001); assign packet_done = (state == 3'b011) || lp_detect; endmodule ================================================ FILE: verilog_cores/csi2.core ================================================ CAPI=2: name : ::csi2:0 filesets: icebreaker: files: - misc/downsample.v : {file_type : verilogSource} - test/icebreaker/uart.v : {file_type : verilogSource} - test/icebreaker/top.v : {file_type : verilogSource} - test/icebreaker/icecam.pcf : {file_type : PCF} core: files: - phy/dphy_iserdes.v - phy/dphy_oserdes.v - phy/word_combiner.v - phy/byte_aligner.v - csi/header_ecc.v - csi/rx_packet_handler.v file_type : verilogSource link_ice40: files: - link/csi_rx_ice40.v : {file_type : verilogSource} depend : ["!tool_icestorm? (yosys:techlibs:ice40)"] targets: default: filesets : [core, link_ice40] icebreaker: default_tool : icestorm filesets: [core, link_ice40, icebreaker] tools: icestorm: pnr : next nextpnr_options : [--up5k] toplevel : top lint: default_tool : verilator filesets: [core, link_ice40] tools: verilator: mode : lint-only toplevel : csi_rx_ice40 ================================================ FILE: verilog_cores/link/csi_rx_ice40.v ================================================ /** * The MIT License * Copyright (c) 2016-2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /* * Example CSI-2 receiver for iCE40 */ module csi_rx_ice40 #( parameter LANES = 2, // lane count parameter PAIRSWAP = 2'b10, // lane pair swap (inverts data for given lane) parameter [1:0] VC = 2'b00, // MIPI CSI-2 "virtual channel" parameter [5:0] FS_DT = 6'h00, // Frame start data type parameter [5:0] FE_DT = 6'h01, // Frame end data type parameter [5:0] VIDEO_DT = 6'h2A, // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw) parameter [15:0] MAX_LEN = 8192 // Max expected packet len, used as timeout )( input dphy_clk_lane, input [LANES-1:0] dphy_data_lane, input dphy_lp_sense, input areset, output word_clk, output [31:0] payload_data, output payload_enable, output payload_frame, output [2*LANES-1:0] dbg_raw_ddr, output [8*LANES-1:0] dbg_raw_deser, output [8*LANES-1:0] dbg_aligned, output [LANES-1:0] dbg_aligned_valid, output dbg_wait_sync, output vsync, output in_line, output in_frame ); wire dphy_clk, dphy_clk_pre; SB_IO #( .PIN_TYPE(6'b000001), .IO_STANDARD("SB_LVDS_INPUT") ) clk_iobuf ( .PACKAGE_PIN(dphy_clk_lane), .D_IN_0(dphy_clk_pre) ); SB_GB clk_gbuf ( .USER_SIGNAL_TO_GLOBAL_BUFFER(dphy_clk_pre), .GLOBAL_BUFFER_OUTPUT(dphy_clk) ); wire dphy_lp; SB_IO #( .PIN_TYPE(6'b000001), .IO_STANDARD("SB_LVDS_INPUT") ) lp_compare ( .PACKAGE_PIN(dphy_lp_sense), .D_IN_0(dphy_lp) ); reg [1:0] div; always @(posedge dphy_clk or posedge areset) if (areset) div <= 0; else div <= div + 1'b1; assign word_clk = div[1]; wire sreset; reg [7:0] sreset_ctr; always @(posedge word_clk or posedge areset) if (areset) sreset_ctr <= 0; else if (!(&sreset_ctr)) sreset_ctr <= sreset_ctr + 1'b1; assign sreset = !(&sreset_ctr); wire byte_packet_done, wait_for_sync; wire [LANES*8-1:0] aligned_bytes; wire [LANES-1:0] aligned_bytes_valid; generate genvar ii; for (ii = 0; ii < LANES; ii++) begin wire [1:0] din_raw; SB_IO #( .PIN_TYPE(6'b000000), .IO_STANDARD("SB_LVDS_INPUT") ) data_iobuf ( .PACKAGE_PIN(dphy_data_lane[ii]), .INPUT_CLK(dphy_clk), .D_IN_0(din_raw[0]), .D_IN_1(din_raw[1]) ); assign dbg_raw_ddr[2*ii+1:2*ii] = din_raw; wire [7:0] din_deser; dphy_iserdes #( .REG_INPUT(1'b1) ) iserdes_i ( .dphy_clk(dphy_clk), .din(din_raw), .sys_clk(word_clk), .areset(areset), .dout(din_deser) ); wire [7:0] din_deser_swap = PAIRSWAP[ii] ? ~din_deser : din_deser; assign dbg_raw_deser[8*ii+7:8*ii] = din_deser_swap; dphy_rx_byte_align baligner_i ( .clock(word_clk), .reset(sreset), .enable(1'b1), .deser_byte(din_deser_swap), .wait_for_sync(wait_for_sync), .packet_done(byte_packet_done), .valid_data(aligned_bytes_valid[ii]), .data_out(aligned_bytes[8*ii+7:8*ii]) ); end endgenerate assign dbg_aligned = aligned_bytes; assign dbg_aligned_valid = aligned_bytes_valid; wire [31:0] comb_word; wire comb_word_en, comb_word_frame; wire word_packet_done; dphy_rx_word_combiner #( .LANES(LANES) ) combiner_i ( .clock(word_clk), .reset(sreset), .enable(1'b1), .bytes_in(aligned_bytes), .bytes_valid(aligned_bytes_valid), .wait_for_sync(wait_for_sync), .packet_done(word_packet_done), .byte_packet_done(byte_packet_done), .word_out(comb_word), .word_enable(comb_word_en), .word_frame(comb_word_frame) ); assign dbg_wait_sync = wait_for_sync; csi_rx_packet_handler #( .VC(VC), .FS_DT(FS_DT), .FE_DT(FE_DT), .VIDEO_DT(VIDEO_DT), .MAX_LEN(MAX_LEN) ) handler_i ( .clock(word_clk), .reset(sreset), .enable(1'b1), .data(comb_word), .data_enable(comb_word_en), .data_frame(comb_word_frame), .lp_detect(!dphy_lp), .sync_wait(wait_for_sync), .packet_done(word_packet_done), .payload(payload_data), .payload_enable(payload_enable), .payload_frame(payload_frame), .vsync(vsync), .in_frame(in_frame), .in_line(in_line) ); endmodule ================================================ FILE: verilog_cores/misc/downsample.v ================================================ /** * The MIT License * Copyright (c) 2016-2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /* * Simple downsampler and buffer 640x480 => 40x30 */ module downsample ( input pixel_clock, input in_line, input in_frame, input [31:0] pixel_data, input data_enable, input read_clock, input [5:0] read_x, input [4:0] read_y, output reg [7:0] read_q ); reg [7:0] buffer[0:2047]; reg [11:0] pixel_acc; reg [7:0] pixel_x; reg [8:0] pixel_y; reg last_in_line; wire [11:0] next_acc = pixel_acc + pixel_data[7:0] + pixel_data[15:8] + pixel_data[23:16] + pixel_data[31:24]; always @(posedge pixel_clock) begin if (!in_frame) begin pixel_acc <= 0; pixel_x <= 0; pixel_y <= 0; last_in_line <= in_line; end else begin if (in_line && data_enable) begin if (pixel_y[3:0] == 0) begin if (&(pixel_x[1:0])) begin pixel_acc <= 0; buffer[{pixel_y[8:4], pixel_x[7:2]}] <= next_acc[11:4]; end else begin pixel_acc <= next_acc; end if (pixel_x < 160) pixel_x <= pixel_x + 1; end end else if (!in_line) begin pixel_x <= 0; pixel_acc <= 0; if (last_in_line) pixel_y <= pixel_y + 1'b1; end last_in_line <= in_line; end end always @(posedge read_clock) read_q <= buffer[{read_y, read_x}]; endmodule ================================================ FILE: verilog_cores/phy/byte_aligner.v ================================================ /** * The MIT License * Copyright (c) 2016-2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /** * MIPI D-PHY byte aligner * This receives raw, unaligned bytes (which could contain part of two actual bytes) * from the SERDES and aligns them by looking for the D-PHY sync pattern * * When wait_for_sync is high the entity will wait until it sees the valid header at some alignment, * at which point the found alignment is locked until packet_done is asserted * * valid_data is asserted as soon as the sync pattern is found, so the next byte * contains the CSI packet header * * In reality to avoid false triggers we must look for a valid sync pattern on all k lanes, * if this does not occur the word aligner (a seperate entity) will assert packet_done immediately * */ `default_nettype none module dphy_rx_byte_align( input clock, // byte clock input reset, // active high sync reset input enable, // byte clock enable input [7:0] deser_byte, // raw bytes from iserdes input wait_for_sync, // when high will look for a sync pattern if sync not already found input packet_done, // assert to reset synchronisation status output reg valid_data, // goes high as soon as sync pattern is found (so data out on next cycle contains header) output reg [7:0] data_out //aligned data out, typically delayed by 2 cycles ); reg [7:0] curr_byte; reg [7:0] last_byte; reg [7:0] shifted_byte; reg found_sync; reg [2:0] sync_offs; // found offset of sync pattern reg [2:0] data_offs; // current data offset always @(posedge clock) begin if (reset) begin valid_data <= 1'b0; last_byte <= 0; curr_byte <= 0; data_out <= 0; data_offs <= 0; end else if (enable) begin last_byte <= curr_byte; curr_byte <= deser_byte; data_out <= shifted_byte; if (packet_done) begin valid_data <= found_sync; end else if (wait_for_sync && found_sync && !valid_data) begin // Waiting for sync, just found it now so use sync position as offset valid_data <= 1'b1; data_offs <= sync_offs; end end end localparam [7:0] sync_word = 8'b10111000; reg was_found; reg [2:0] offset; integer i; wire [15:0] concat_word = {curr_byte, last_byte}; always @(*) begin offset = 0; was_found = 1'b0; found_sync = 1'b0; sync_offs = 0; for (i = 0; i < 8; i = i + 1) begin if ((concat_word[(1+i) +: 8] == sync_word) && (last_byte[i:0] == 0)) begin was_found = 1'b1; offset = i; end end if (was_found) begin found_sync = 1'b1; sync_offs = offset; end end assign shifted_byte = concat_word[(1 + data_offs) +: 8]; endmodule ================================================ FILE: verilog_cores/phy/dphy_iserdes.v ================================================ /** * The MIT License * Copyright (c) 2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /** * MIPI D-PHY input SERDES * This is designed to take 2 inputs per clock from an architecture specific * DDR primitive */ module dphy_iserdes( input dphy_clk, // Fast D-PHY DDR clock (4x sys_clk) input [1:0] din, // Input from arch DDR primitive, D1 should be the bit after D0 input sys_clk, // System byte clock input areset, // Active high async reset output [7:0] dout // Output data ); parameter REG_INPUT = 1'b0; parameter NUM_OUT_SYNCFFS = 2; wire [1:0] iserdes_din; generate if (REG_INPUT) begin reg [1:0] din_reg; always @(posedge dphy_clk, posedge areset) if (areset) din_reg <= 2'b00; else din_reg <= din; assign iserdes_din = din_reg; end else begin assign iserdes_din = din; end endgenerate reg [7:0] reg_word; always @(posedge dphy_clk, posedge areset) if (areset) reg_word <= 0; else reg_word <= {iserdes_din, reg_word[7:2]}; // MIPI interface uses LSB first reg [7:0] out_sync_regs[0:NUM_OUT_SYNCFFS-1]; integer i; always @(posedge sys_clk, posedge areset) if (areset) for (i = 0; i < NUM_OUT_SYNCFFS; i = i + 1) out_sync_regs[i] <= 0; else begin for (i = 1; i < NUM_OUT_SYNCFFS; i = i + 1) out_sync_regs[i] <= out_sync_regs[i-1]; out_sync_regs[0] <= reg_word; end assign dout = out_sync_regs[NUM_OUT_SYNCFFS-1]; endmodule ================================================ FILE: verilog_cores/phy/dphy_oserdes.v ================================================ /** * The MIT License * Copyright (c) 2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /** * MIPI D-PHY output SERDES * This is designed to generate 2 outputs per clock for an architecture specific * DDR primitive */ module dphy_oserdes( input sys_clk, // System byte clock input areset, // Active high async reset input [7:0] din, // Input from CSI-2 packetiser input dphy_clk, // Fast D-PHY DDR clock (4x sys_clk) output reg [1:0] dout // Output data, bit 1 should be the second bit transmitted ); parameter NUM_SYNCFFS = 2; reg [8:0] dclk_sclk_din[0:NUM_SYNCFFS-1]; // Input integer i; always @(posedge dphy_clk, posedge areset) if (areset) begin for (i = 0; i < NUM_SYNCFFS; i = i + 1) dclk_sclk_din[i] <= 0; end else begin for (i = 1; i < NUM_SYNCFFS; i = i + 1) dclk_sclk_din[i] <= dclk_sclk_din[i-1]; dclk_sclk_din[0] <= {sys_clk, din}; end wire dclk_sclk = dclk_sclk_din[NUM_SYNCFFS-1][8]; wire [7:0] dclk_din = dclk_sclk_din[NUM_SYNCFFS-1][7:0]; reg last_sclk; reg [7:0] reg_word; always @(posedge dphy_clk, posedge areset) if (areset) begin last_sclk <= 1'b0; dout <= 2'b00; reg_word <= 0; end else begin last_sclk <= dclk_sclk; dout <= reg_word[1:0]; // LSB first if (dclk_sclk && !last_sclk) begin reg_word <= dclk_din; end else begin reg_word <= {reg_word[1:0], reg_word[7:2]}; end end endmodule ================================================ FILE: verilog_cores/phy/word_combiner.v ================================================ /** * The MIT License * Copyright (c) 2016-2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ /** * MIPI D-PHY word combiner * This receives aligned bytes from the byte aligner(s), controls the byte aligner(s) * and assembles the data stream back into 32-bit words for consistency across different * widths * */ module dphy_rx_word_combiner #( parameter LANES = 2 ) ( input clock, // byte clock input reset, // active high sync reset input enable, // active high clock enable input [8*LANES-1:0] bytes_in, // input bytes from lane byte aligners input [LANES-1:0] bytes_valid, // valid signals from lane byte aligners input wait_for_sync, // input from packet handler input packet_done, // packet done input from packet handler output byte_packet_done, // packet done output to byte aligners output reg [31:0] word_out, //fixed width 32-bit data out output reg word_enable, // word enable used when in less than 4-lane mode output reg word_frame // valid output high during valid packet even if word enable low ); wire triggered = |bytes_valid; wire all_valid = &bytes_valid; wire invalid_start = triggered && !all_valid; reg valid; reg [31:0] word_int; reg [1:0] byte_cnt; always @(posedge clock) begin if (reset) begin valid <= 0; word_int <= 0; byte_cnt <= 0; word_out <= 0; word_enable <= 0; word_frame <= 0; end else if (enable) begin if (all_valid && !valid && wait_for_sync) begin byte_cnt <= 0; word_frame <= 1'b1; valid <= 1'b1; end else if (packet_done) begin word_frame <= 1'b0; valid <= 1'b0; end if (valid) begin if (LANES == 4) begin word_out <= bytes_in; word_enable <= 1'b1; end else begin byte_cnt <= byte_cnt + LANES; word_int <= {bytes_in, word_int[31:8*LANES]}; if ((byte_cnt + LANES) % 4 == 0) begin word_out <= {bytes_in, word_int[31:8*LANES]}; word_enable <= 1'b1; end else begin word_enable <= 1'b0; end end end else begin word_enable <= 1'b0; end end end assign byte_packet_done = packet_done | invalid_start; endmodule ================================================ FILE: verilog_cores/test/icebreaker/.gitignore ================================================ *.blif *.json *.asc *.bin *.rpt *.log ================================================ FILE: verilog_cores/test/icebreaker/Makefile ================================================ SOURCES = $(wildcard ../../csi/*.v ../../phy/*.v ../../link/*.v ../../misc/*.v uart.v top.v) PROJ=camera PIN_DEF=icecam.pcf DEVICE=up5k all: $(PROJ).rpt $(PROJ).bin %.json: $(SOURCES) yosys -ql yosys.log -p 'synth_ice40 -top top -json $@' $(SOURCES) %.asc: %.json $(PIN_DEF) nextpnr-ice40 --pre-pack constraints.py --up5k --pcf $(PIN_DEF) --json $< --asc $@ --freq 40 gui: %.json $(PIN_DEF) nextpnr-ice40 --up5k --pcf $(PIN_DEF) --json $< --asc $@ --freq 40 --gui %.bin: %.asc icepack $< $@ %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< prog: $(PROJ).bin iceprog $< sudo-prog: $(PROJ).bin @echo 'Executing prog as root!!!' sudo iceprog $< clean: rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin .SECONDARY: .PHONY: all prog clean gui ================================================ FILE: verilog_cores/test/icebreaker/constraints.py ================================================ ctx.addClock("csi_rx_i.dphy_clk", 96) ctx.addClock("video_clk", 24) ctx.addClock("uart_i.sys_clk_i", 12) ================================================ FILE: verilog_cores/test/icebreaker/icecam.pcf ================================================ set_io mpsse_sda 6 #FTDI D0 set_io mpsse_scl 9 #FTDI D1 set_io cam_enable 3 #P1A7 set_io cam_sda 34 #P1B3 set_io cam_scl 28 #P1B10 set_io dphy_clk 32 #P1B9 set_io dphy_data[0] 42 #P1B7 set_io dphy_data[1] 43 #P1B1 set_io dphy_lp 48 #P1A8 set_io BTN_N 10 set_io LEDR_N 11 set_io LEDG_N 37 set_io LED2 27 set_io LED3 25 set_io LED5 21 set_io BTN2 19 set_io LED1 26 set_io LED4 23 set_io BTN1 20 set_io BTN3 18 set_io clk12 35 set_io dbg_tx 13 ================================================ FILE: verilog_cores/test/icebreaker/top.v ================================================ /** * The MIT License * Copyright (c) 2018 David Shah * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * */ module top(input clk12, input mpsse_sda, mpsse_scl, inout cam_sda, cam_scl, output cam_enable, input dphy_clk, input [1:0] dphy_data, input dphy_lp, output LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5, input BTN_N, BTN1, BTN2, BTN3, output dbg_tx); wire areset = !BTN_N; assign cam_scl = mpsse_scl ? 1'bz : 1'b0; assign cam_sda = mpsse_sda ? 1'bz : 1'b0; assign cam_enable = 1'b1; wire video_clk; wire in_line, in_frame, vsync; wire [31:0] payload_data; wire payload_valid; wire [15:0] raw_deser; wire [15:0] aligned_deser; wire [3:0] raw_ddr; wire [1:0] aligned_valid; wire wait_sync; wire payload_frame; csi_rx_ice40 #( .LANES(2), // lane count .PAIRSWAP(2'b10), // lane pair swap (inverts data for given lane) .VC(2'b00), // MIPI CSI-2 "virtual channel" .FS_DT(6'h12), // Frame start data type .FE_DT(6'h01), // Frame end data type .VIDEO_DT(6'h2A), // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw) .MAX_LEN(8192) // Max expected packet len, used as timeout ) csi_rx_i ( .dphy_clk_lane(dphy_clk), .dphy_data_lane(dphy_data), .dphy_lp_sense(dphy_lp), .areset(areset), .word_clk(video_clk), .payload_data(payload_data), .payload_enable(payload_valid), .payload_frame(payload_frame), .vsync(vsync), .in_line(in_line), .in_frame(in_frame), .dbg_aligned_valid(aligned_valid), .dbg_raw_deser(raw_deser), .dbg_raw_ddr(raw_ddr), .dbg_wait_sync(wait_sync) ); reg [22:0] sclk_div; always @(posedge video_clk) sclk_div <= sclk_div + 1'b1; reg [15:0] vsync_monostable = 0; always @(posedge video_clk) if (vsync || vsync_monostable != 0) vsync_monostable <= vsync_monostable + 1'b1; assign LEDR_N = !sclk_div[22]; assign LEDG_N = !(|vsync_monostable); assign LED1 = video_clk; assign {LED5, LED4, LED3, LED2} = (payload_frame&&payload_valid) ? payload_data[5:2] : 0; reg [5:0] read_x; reg [4:0] read_y; wire [7:0] read_data; downsample ds_i( .pixel_clock(video_clk), .in_line(in_line), .in_frame(!vsync), .pixel_data(payload_data), .data_enable(payload_frame&&payload_valid), .read_clock(clk12), .read_x(read_x), .read_y(read_y), .read_q(read_data) ); reg do_send = 1'b0; wire uart_busy; reg uart_write; reg [13:0] btn_debounce; reg btn_reg; reg [12:0] uart_holdoff; always @(posedge clk12) begin btn_reg <= BTN1; if (btn_reg) btn_debounce <= 0; else if (!&(btn_debounce)) btn_debounce <= btn_debounce + 1; uart_write <= 1'b0; if (btn_reg && &btn_debounce && !do_send) begin do_send <= 1'b1; read_x <= 0; read_y <= 0; end if (uart_busy) uart_holdoff <= 0; else if (!&(uart_holdoff)) uart_holdoff <= uart_holdoff + 1'b1; if (do_send) begin if (read_x == 0 && read_y == 30) begin do_send <= 1'b0; end else begin if (&uart_holdoff && !uart_busy && !uart_write) begin uart_write <= 1'b1; if (read_x == 39) begin read_y <= read_y + 1'b1; read_x <= 0; end else begin read_x <= read_x + 1'b1; end end end end end uart uart_i ( // Outputs .uart_busy(uart_busy), // High means UART is transmitting .uart_tx(dbg_tx), // UART transmit wire // Inputs .uart_wr_i(uart_write), // Raise to transmit byte .uart_dat_i(read_data), // 8-bit data .sys_clk_i(clk12), // System clock, 12 MHz .sys_rst_i(areset) // System reset ); endmodule ================================================ FILE: verilog_cores/test/icebreaker/uart.v ================================================ // From http://www.excamera.com/sphinx/fpga-uart.html module uart( // Outputs uart_busy, // High means UART is transmitting uart_tx, // UART transmit wire // Inputs uart_wr_i, // Raise to transmit byte uart_dat_i, // 8-bit data sys_clk_i, // System clock, 12 MHz sys_rst_i // System reset ); input uart_wr_i; input [7:0] uart_dat_i; input sys_clk_i; input sys_rst_i; output uart_busy; output uart_tx; reg [3:0] bitcount; reg [8:0] shifter; reg uart_tx; wire uart_busy = |bitcount[3:1]; wire sending = |bitcount; // sys_clk_i is 12MHz. We want a 3MHz clock reg [28:0] d; wire [28:0] dInc = d[28] ? (3000000) : (3000000 - 12000000); wire [28:0] dNxt = d + dInc; always @(posedge sys_clk_i) begin d = dNxt; end wire ser_clk = ~d[28]; // this is the 115200 Hz clock always @(posedge sys_clk_i) begin if (sys_rst_i) begin uart_tx <= 1; bitcount <= 0; shifter <= 0; end else begin // just got a new byte if (uart_wr_i & ~uart_busy) begin shifter <= { uart_dat_i[7:0], 1'h0 }; bitcount <= (1 + 8 + 2); end if (sending & ser_clk) begin { shifter, uart_tx } <= { 1'h1, shifter }; bitcount <= bitcount - 1; end end end endmodule ================================================ FILE: vhdl_rx/.gitignore ================================================ *.o work/ *.cf ================================================ FILE: vhdl_rx/LICENSE.notes ================================================ All of the source code written by me (in particular */*.vhd except the examples folder) is licensed under the MIT license,see the LICENSE file for more information. For obvious reasons this does not extend to any files in the example project generated or included by Xilinx's tools (including but not limited to Xilinx's IP cores such as the DDR3 interface). The copyright on these belongs to Xilinx and Xilinx's restrictions will apply. The register values in the `ov13850_4k_regs.vhd` file were based on open source Linux drivers, but it is my understanding that these are not copyrightable in themselves. All mentioned trademarks are property of their respective owners. ================================================ FILE: vhdl_rx/README.md ================================================ # 4k MIPI CSI-2 FPGA Camera Interface ## Overview This project is an open source (MIT license) MIPI CSI-2 receive core for Xilinx FPGAs, supporting 4k resolution at greater than 30fps. It includes a complete demo project, designed for the Genesys 2 board with a custom FMC to camera card, that writes the 4k video into a DDR3 framebuffer and outputs at 1080p (with a choice of scaled or cropped) to the HDMI and VGA ports. The demo camera module is the Omnivision OV13850 (using the Firefly camera module), which supports 4k at up to 30fps, although the demo runs at 24fps where it seems performance is better - this may partly be down to the choice of register values though. Although the OV13850 sensor/ADC does not seem to work much above 30fps; the camera also has a "test pattern" mode which bypasses this and which I have used to test my driver up to 45fps. ## Structure - The `mipi-csi-rx` folder contains all the components (except the `video_timing_ctrl` timing generator, in the `video-misc` folder) needed for the CSI-2 Rx itself. - `csi_rx_top` is the top level for the CSI-2 interface, this is what you should use in your design - `csi_rx_4_lane_link` encapsulates the link layer. In particular - `csi_rx_hs_lane_phy` is the low-level data PHY, one for each lane, containing the input buffer and input SERDES - `csi_rx_byte_align` ensures bytes are correctly aligned by looking for the sync byte that precedes packets - `csi_rx_word_align` corrects any slight alignment differences between lanes, concatenating the 4 lane byte inputs to a single 32-bit word output - `csi_rx_hs_clk_phy` handles the clock input and contains the necessary clock buffers - `csi_rx_packet_handler` processes packets, looking for video packets and seperating off the payload - `csi_rx_10bit_unpack` converts 32-bit packet payload input and outputs 4 10-bit pixels (with a `valid` output, as it does not produce pixels every clock cycle) - `csi_rx_video_output` synchronises the CSI-2 clock domain to the pixel clock domain using a line buffer and outputs standard video format - `ov-cam-control` contains a I2C interface for camera configuration, the 4k24 configuration for the OV13850, and `ov13850_control_top` which handles camera reseting and writes the register values from the configuration ROM to the I2C interface. - `framebuffer-ctrl` contains the framebuffer controller, which interfaces with external framebuffer memory (providing an AXI4 master to interface with the Xilinx DDR3 controller) to scale or crop the 4k frames from the camera to 1080p for the video output. - `video-misc` contains the video timing controller, a test pattern generator for debugging, a video register for timing purposes and the basic ISP (a simple debayering core and colour channel gain adjustment for white balance). - `dvi-tx` contains a simple DVI transmitter, for the Genesys 2 HDMI output port - `demo-top` contains the top level files for the demo project; and `examples` contains the Vivado project itself for the demo ## Test Hardware The current test platform is the Digilent Genesys 2 (Kintex-7 XC7K325T-2) with an OV13850 camera. The CSI-2 lanes connect to 2.5V LVDS inputs on the FPGA, using a custom FMC interface board. Earlier testing was done on a Virtex-6 FPGA, unfortunately I no longer have access to this platform so support cannot be guaranteed. The exact camera used was the Firefly RK3288 camera module, which is a convenient way of obtaining the OV13850 camera - search for "OV13850 Firefly RK3288" and various sites selling it can be found starting from $40 or so. In the future I'm looking into using smartphone replacement camera modules. I have ordered some IUNI U2 replacement back cameras which are P16V01A modules based on the 4k60-capable OV16825 and have a publicly available pinout. The FMC board also has a connector for the 4k 5.5" Z5 premium LCD; which I am also working on code to drive. The KiCad board designs and gerbers are in the [DSITx](https://github.com/daveshah1/DSITx/tree/master/hardware/fmc-v1.2) repo. A quick picture of my test setup is below. ![4k Camera Testing](http://ds0.me/csi_rx/csi_testing.jpg) ## Customisation See `csi_rx_top.vhd` for more information on the parameters that need to be adjusted depending on your camera and application. ## Future Work In the future the debayering block needs to be improved to reduce colour fringing at sharp edges. A driver for the focus voice coil driver inside the camera module needs to be added; along with autofocus and AEC/AGC (at the moment gain and exposure are buried deep within the camera config ROM). ================================================ FILE: vhdl_rx/demo-top/framebuffer_top.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Top Level Framebuffer and Video Output Design --Copyright (C) 2016 David Shah --Licensed under the MIT License entity framebuffer_top is port( --Video input port input_pixck : in std_logic; input_vsync : in std_logic; input_line_start : in std_logic; input_den : in std_logic; input_data_even : in std_logic_vector(23 downto 0); input_data_odd : in std_logic_vector(23 downto 0); --System/control inputs system_clock : in std_logic; system_reset : in std_logic; zoom_mode : in std_logic; freeze : in std_logic; --Video output port output_pixck : in std_logic; output_vsync : out std_logic; output_hsync : out std_logic; output_den : out std_logic; output_line_start : out std_logic; output_data : out std_logic_vector(23 downto 0); --DDR3 interface ddr3_addr : out std_logic_vector(14 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_cas_n : out std_logic; ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_ras_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_we_n : out std_logic; ddr3_dq : inout std_logic_vector(31 downto 0); ddr3_dqs_n : inout std_logic_vector(3 downto 0); ddr3_dqs_p : inout std_logic_vector(3 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(3 downto 0); ddr3_odt : out std_logic_vector(0 downto 0) ); end framebuffer_top; architecture Behavioral of framebuffer_top is signal ui_clock : std_logic; signal axi_resetn : std_logic; signal axi_awid : std_logic_vector(0 downto 0); signal axi_awaddr : std_logic_vector(29 downto 0); signal axi_awlen : std_logic_vector(7 downto 0); signal axi_awsize : std_logic_vector(2 downto 0); signal axi_awburst : std_logic_vector(1 downto 0); signal axi_awlock : std_logic_vector(0 downto 0); signal axi_awcache : std_logic_vector(3 downto 0); signal axi_awprot : std_logic_vector(2 downto 0); signal axi_awqos : std_logic_vector(3 downto 0); signal axi_awvalid : std_logic; signal axi_awready : std_logic; signal axi_wdata : std_logic_vector(255 downto 0); signal axi_wstrb : std_logic_vector(31 downto 0); signal axi_wlast : std_logic; signal axi_wvalid : std_logic; signal axi_wready : std_logic; signal axi_bid : std_logic_vector(0 downto 0); signal axi_bresp : std_logic_vector(1 downto 0); signal axi_bvalid : std_logic; signal axi_bready : std_logic; signal axi_arid : std_logic_vector(0 downto 0); signal axi_araddr : std_logic_vector(29 downto 0); signal axi_arlen : std_logic_vector(7 downto 0); signal axi_arsize : std_logic_vector(2 downto 0); signal axi_arburst : std_logic_vector(1 downto 0); signal axi_arlock : std_logic_vector(0 downto 0); signal axi_arcache : std_logic_vector(3 downto 0); signal axi_arprot : std_logic_vector(2 downto 0); signal axi_arqos : std_logic_vector(3 downto 0); signal axi_arvalid : std_logic; signal axi_arready : std_logic; signal axi_rid : std_logic_vector(0 downto 0); signal axi_rdata : std_logic_vector(255 downto 0); signal axi_rresp : std_logic_vector(1 downto 0); signal axi_rlast : std_logic; signal axi_rvalid : std_logic; signal axi_rready : std_logic; signal fbc_ovsync : std_logic; signal fbc_data : std_logic_vector(23 downto 0); signal output_line_start_int : std_logic; signal output_den_int : std_logic; component ddr3_if is port( ddr3_addr : out std_logic_vector(14 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_cas_n : out std_logic; ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_ras_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_we_n : out std_logic; ddr3_dq : inout std_logic_vector(31 downto 0); ddr3_dqs_n : inout std_logic_vector(3 downto 0); ddr3_dqs_p : inout std_logic_vector(3 downto 0); init_calib_complete : out std_logic; ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(3 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); ui_clk : out std_logic; ui_clk_sync_rst : out std_logic; mmcm_locked : out std_logic; aresetn : in std_logic; app_sr_req : in std_logic; app_ref_req : in std_logic; app_zq_req : in std_logic; app_sr_active : out std_logic; app_ref_ack : out std_logic; app_zq_ack : out std_logic; s_axi_awid : in std_logic_vector(0 downto 0); s_axi_awaddr : in std_logic_vector(29 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic_vector(0 downto 0); s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awqos : in std_logic_vector(3 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(255 downto 0); s_axi_wstrb : in std_logic_vector(31 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(0 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(0 downto 0); s_axi_araddr : in std_logic_vector(29 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic_vector(0 downto 0); s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arqos : in std_logic_vector(3 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(0 downto 0); s_axi_rdata : out std_logic_vector(255 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; sys_clk_i : in std_logic; sys_rst : in std_logic ); end component; begin axi_resetn <= not system_reset; fbctl : entity work.framebuffer_ctrl_crop_scale generic map( burst_len => 16, input_width => 3840, input_height => 2160, output_width => 1920, output_height => 1080, crop_xoffset => 1024, crop_yoffset => 540, scale_xoffset => 0, scale_yoffset => 0) port map( input_clock => input_pixck, input_vsync => input_vsync, input_line_start => input_line_start, input_den => input_den, input_data_even => input_data_even, input_data_odd => input_data_odd, output_clock => output_pixck, output_vsync => fbc_ovsync, output_line_start => output_line_start_int, output_den => output_den_int, output_data => fbc_data, axi_clock => ui_clock, axi_resetn => axi_resetn, axi_awid => axi_awid, axi_awaddr => axi_awaddr, axi_awlen => axi_awlen, axi_awsize => axi_awsize, axi_awburst => axi_awburst, axi_awlock => axi_awlock, axi_awcache => axi_awcache, axi_awprot => axi_awprot, axi_awqos => axi_awqos, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_wlast => axi_wlast, axi_wvalid => axi_wvalid, axi_wready => axi_wready, axi_bid => axi_bid, axi_bresp => axi_bresp, axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_arid => axi_arid, axi_araddr => axi_araddr, axi_arlen => axi_arlen, axi_arsize => axi_arsize, axi_arburst => axi_arburst, axi_arlock => axi_arlock, axi_arcache => axi_arcache, axi_arprot => axi_arprot, axi_arqos => axi_arqos, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_rid => axi_rid, axi_rdata => axi_rdata, axi_rresp => axi_rresp, axi_rlast => axi_rlast, axi_rvalid => axi_rvalid, axi_rready => axi_rready, zoom_mode => zoom_mode, freeze => freeze ); output : entity work.video_fb_output generic map( video_hlength => 2200, video_vlength => 1125, video_hsync_pol => true, video_hsync_len => 44, video_hbp_len => 148, video_h_visible => 1920, video_vsync_pol => true, video_vsync_len => 5, video_vbp_len => 36, video_v_visible => 1080) port map( pixel_clock => output_pixck, reset => system_reset, fbc_vsync => fbc_ovsync, fbc_data => fbc_data, video_vsync => output_vsync, video_hsync => output_hsync, video_den => output_den_int, video_line_start => output_line_start_int, video_data => output_data); output_den <= output_den_int; output_line_start <= output_line_start_int; memctl : ddr3_if port map( ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n, init_calib_complete => open, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, ui_clk => ui_clock, ui_clk_sync_rst => open, mmcm_locked => open, aresetn => axi_resetn, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => open, app_ref_ack => open, app_zq_ack => open, s_axi_awid => axi_awid, s_axi_awaddr => axi_awaddr, s_axi_awlen => axi_awlen, s_axi_awsize => axi_awsize, s_axi_awburst => axi_awburst, s_axi_awlock => axi_awlock, s_axi_awcache => axi_awcache, s_axi_awprot => axi_awprot, s_axi_awqos => axi_awqos, s_axi_awvalid => axi_awvalid, s_axi_awready => axi_awready, s_axi_wdata => axi_wdata, s_axi_wstrb => axi_wstrb, s_axi_wlast => axi_wlast, s_axi_wvalid => axi_wvalid, s_axi_wready => axi_wready, s_axi_bid => axi_bid, s_axi_bresp => axi_bresp, s_axi_bvalid => axi_bvalid, s_axi_bready => axi_bready, s_axi_arid => axi_arid, s_axi_araddr => axi_araddr, s_axi_arlen => axi_arlen, s_axi_arsize => axi_arsize, s_axi_arburst => axi_arburst, s_axi_arlock => axi_arlock, s_axi_arcache => axi_arcache, s_axi_arprot => axi_arprot, s_axi_arqos => axi_arqos, s_axi_arvalid => axi_arvalid, s_axi_arready => axi_arready, s_axi_rid => axi_rid, s_axi_rdata => axi_rdata, s_axi_rresp => axi_rresp, s_axi_rlast => axi_rlast, s_axi_rvalid => axi_rvalid, s_axi_rready => axi_rready, sys_clk_i => system_clock, sys_rst => '1'); end Behavioral; ================================================ FILE: vhdl_rx/demo-top/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1250 2.0V 4:1 200 0 800 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 11 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 8 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/demo-top/ov13850_demo.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; --OV13850 Demo Top Level Design --Copyright (C) 2016 David Shah --Licensed under the MIT License entity ov13850_demo is Port ( clock_p : in std_logic; clock_n : in std_logic; reset_n : in std_logic; hdmi_clk : out std_logic_vector(1 downto 0); hdmi_d0 : out std_logic_vector(1 downto 0); hdmi_d1 : out std_logic_vector(1 downto 0); hdmi_d2 : out std_logic_vector(1 downto 0); vga_hsync : out std_logic; vga_vsync : out std_logic; vga_r : out std_logic_vector(4 downto 0); vga_g : out std_logic_vector(5 downto 0); vga_b : out std_logic_vector(4 downto 0); zoom_mode : in std_logic; freeze : in std_logic; --Camera CSI port csi0_clk : in std_logic_vector(1 downto 0); csi0_d0 : in std_logic_vector(1 downto 0); csi0_d1 : in std_logic_vector(1 downto 0); csi0_d2 : in std_logic_vector(1 downto 0); csi0_d3 : in std_logic_vector(1 downto 0); --Camera control port cam_mclk : out std_logic; cam_rstn : out std_logic; cam_i2c_sda : inout std_logic; cam_i2c_sck : inout std_logic; --DDR3 interface ddr3_addr : out std_logic_vector(14 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_cas_n : out std_logic; ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_ras_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_we_n : out std_logic; ddr3_dq : inout std_logic_vector(31 downto 0); ddr3_dqs_n : inout std_logic_vector(3 downto 0); ddr3_dqs_p : inout std_logic_vector(3 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(3 downto 0); ddr3_odt : out std_logic_vector(0 downto 0) ); end ov13850_demo; architecture Behavioral of ov13850_demo is signal sys_clock : std_logic; signal reset : std_logic; signal dvi_pixel_clock, dvi_bit_clock : std_logic; signal dvi_data : std_logic_vector(23 downto 0); signal dvi_den, dvi_hsync, dvi_vsync : std_logic; signal i2c_clk_in, i2c_clk_div_1, i2c_clk_div : std_logic; signal cam_loading, csi_en, csi_rst : std_logic; signal camera_rstn_int : std_logic; signal input_pixel_clock : std_logic; signal camera_line_start, camera_den, camera_hsync, camera_vsync, camera_odd_line : std_logic; signal camera_data, camera_prev_line_data : std_logic_vector(19 downto 0); signal debayer_line_start, debayer_den, debayer_hsync, debayer_vsync : std_logic; signal debayer_data_even, debayer_data_odd : std_logic_vector(29 downto 0); signal fbin_line_start, fbin_den, fbin_hsync, fbin_vsync : std_logic; signal fbin_data_even, fbin_data_odd : std_logic_vector(23 downto 0); component dvi_pll is port( sysclk : in std_logic; pixel_clock : out std_logic; dvi_bit_clock : out std_logic); end component; component camera_pll is port( sysclk : in std_logic; camera_pixel_clock : out std_logic; camera_mclk : out std_logic; i2c_clkin : out std_logic); end component; begin reset <= not reset_n; clkbuf : IBUFGDS generic map( DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "DEFAULT") port map( O => sys_clock, I => clock_p, IB => clock_n); pll1 : dvi_pll port map( sysclk => sys_clock, pixel_clock => dvi_pixel_clock, dvi_bit_clock => dvi_bit_clock ); pll2 : camera_pll port map( sysclk => sys_clock, camera_pixel_clock => input_pixel_clock, camera_mclk => cam_mclk, i2c_clkin => i2c_clk_in ); --Divide 5MHz from PLL to slower I2C/reset controller input clock i2c_clkdiv : BUFR generic map( BUFR_DIVIDE => "8", SIM_DEVICE => "7SERIES") port map( O => i2c_clk_div_1, CE => '1', CLR => reset, I => i2c_clk_in); i2c_clkdiv2 : BUFR generic map( BUFR_DIVIDE => "4", SIM_DEVICE => "7SERIES") port map( O => i2c_clk_div, CE => '1', CLR => reset, I => i2c_clk_div_1); cam_ctl : entity work.ov13850_control_top port map ( reset => reset, clock => i2c_clk_div, i2c_sda => cam_i2c_sda, i2c_sck => cam_i2c_sck, rst_out => camera_rstn_int, loading_out => cam_loading); cam_rstn <= camera_rstn_int; csi_rst <= not camera_rstn_int; csi_en <= not cam_loading; csi_rx : entity work.csi_rx_4lane generic map( fpga_series => "7SERIES", dphy_term_en => true, d0_invert => false, d1_invert => false, d2_invert => false, d3_invert => false, d0_skew => 10, d1_skew => 10, d2_skew => 10, d3_skew => 10, video_hlength => 4041, video_vlength => 2992, video_hsync_pol => true, video_hsync_len => 48, video_hbp_len => 122, video_h_visible => 3840, video_vsync_pol => true, video_vsync_len => 3, video_vbp_len => 23 , video_v_visible => 2160, pixels_per_clock => 2, generate_idelayctrl => true) port map( ref_clock_in => sys_clock, pixel_clock_in => input_pixel_clock, byte_clock_out => open, enable => csi_en, reset => csi_rst, video_valid => open, dphy_clk => csi0_clk, dphy_d0 => csi0_d0, dphy_d1 => csi0_d1, dphy_d2 => csi0_d2, dphy_d3 => csi0_d3, video_hsync => camera_hsync, video_vsync => camera_vsync, video_den => camera_den, video_line_start => camera_line_start, video_odd_line => camera_odd_line, video_data => camera_data, video_prev_line_data => camera_prev_line_data); db : entity work.simple_debayer port map( clock => input_pixel_clock, input_vsync => camera_vsync, input_hsync => camera_hsync, input_den => camera_den, input_odd_line => camera_odd_line, input_line_start => camera_line_start, input_data => camera_data, input_prev_line_data => camera_prev_line_data, output_vsync => debayer_vsync, output_hsync => debayer_hsync, output_den => debayer_den, output_line_start => debayer_line_start, output_data_even => debayer_data_even, output_data_odd => debayer_data_odd); wb : entity work.image_gain_wb generic map( red_gain => 10, green_gain => 7, blue_gain => 9) port map( clock => input_pixel_clock, input_vsync => debayer_vsync, input_hsync => debayer_hsync, input_den => debayer_den, input_line_start => debayer_line_start, input_data_even => debayer_data_even, input_data_odd => debayer_data_odd, output_vsync => fbin_vsync, output_hsync => fbin_hsync, output_den => fbin_den, output_line_start => fbin_line_start, output_data_even => fbin_data_even, output_data_odd => fbin_data_odd); fbtest : entity work.framebuffer_top port map( input_pixck => input_pixel_clock, input_vsync => fbin_vsync, input_line_start => fbin_line_start, input_den => fbin_den, input_data_even => fbin_data_even, input_data_odd => fbin_data_odd, system_clock => sys_clock, system_reset => reset, zoom_mode => zoom_mode, freeze => freeze, output_pixck => dvi_pixel_clock, output_vsync => dvi_vsync, output_hsync => dvi_hsync, output_den => dvi_den, output_line_start => open, output_data => dvi_data, --DDR3 interface ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt ); dvi_tx : entity work.dvi_tx port map( pixel_clock => dvi_pixel_clock, ddr_bit_clock => dvi_bit_clock, reset => reset, den => dvi_den, hsync => dvi_hsync, vsync => dvi_vsync, pixel_data => dvi_data, tmds_clk => hdmi_clk, tmds_d0 => hdmi_d0, tmds_d1 => hdmi_d1, tmds_d2 => hdmi_d2 ); vga_hsync <= dvi_hsync; vga_vsync <= dvi_vsync; vga_r <= dvi_data(23 downto 19); vga_g <= dvi_data(15 downto 10); vga_b <= dvi_data(7 downto 3); end Behavioral; ================================================ FILE: vhdl_rx/dvi-tx/dvi_tx_clk_drv.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; --DVI Transmitter clock lane driver --Copyright (C) 2016 David Shah --Licensed under the MIT License --This drives the TMDS clock lane, taking the pixel clock as input entity dvi_tx_clk_drv is port( pixel_clock : in std_logic; tmds_clk : out std_logic_vector(1 downto 0)); end dvi_tx_clk_drv; architecture Behavioral of dvi_tx_clk_drv is signal tmds_clk_pre : std_logic; begin --Using an ODDR simplifies clock routing and avoids the need for a clock capable output clk_oddr : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0', SRTYPE => "SYNC") port map( Q => tmds_clk_pre, C => pixel_clock, CE => '1', D1 => '1', D2 => '0', R => '0', S => '0'); clk_obuf : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST") port map ( O => tmds_clk(1), OB => tmds_clk(0), I => tmds_clk_pre); end Behavioral; ================================================ FILE: vhdl_rx/dvi-tx/dvi_tx_tmds_enc.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --DVI Transmitter TMDS encoder --Copyright (C) 2016 David Shah --Licensed under the MIT License --This encodes TMDS 'characters' according to the algorithm in the DVI specification entity dvi_tx_tmds_enc is port( clock : in std_logic; --TMDS character clock reset : in std_logic; --synchronous reset input den : in std_logic; --display data enable data : in std_logic_vector(7 downto 0); --8bit display data ctrl : in std_logic_vector(1 downto 0); --2bit control (vsync+hsync for ch0) tmds : out std_logic_vector(9 downto 0) --10bit encoded TMDS to transmit ); end dvi_tx_tmds_enc; architecture Behavioral of dvi_tx_tmds_enc is signal data_lat : std_logic_vector(7 downto 0); signal den_lat : std_logic; signal ctrl_lat : std_logic_vector(1 downto 0); signal tmds_int : std_logic_vector(9 downto 0); signal cnt_q : integer range -256 to 255; signal cnt_d : integer range -256 to 255; signal q_m : std_logic_vector(8 downto 0); function count_ones(x : std_logic_vector) return integer is variable count : natural := 0; begin for i in x'range loop if x(i) = '1' then count := count + 1; end if; end loop; return count; end function; function count_zeros(x : std_logic_vector) return integer is variable count : natural := 0; begin for i in x'range loop if x(i) = '0' then count := count + 1; end if; end loop; return count; end function; begin process(clock) begin if rising_edge(clock) then if reset = '1' then data_lat <= (others => '0'); ctrl_lat <= (others => '0'); den_lat <= '0'; tmds <= (others => '0'); cnt_q <= 0; else data_lat <= data; den_lat <= den; ctrl_lat <= ctrl; tmds <= tmds_int; cnt_q <= cnt_d; end if; end if; end process; process(data_lat) variable q_m_temp : std_logic_vector(8 downto 0); begin q_m_temp(0) := data_lat(0); if count_ones(data_lat) > 4 or ((count_ones(data_lat) = 4) and data_lat(0) = '0') then for i in 1 to 7 loop q_m_temp(i) := not(q_m_temp(i-1) xor data_lat(i)); end loop; q_m_temp(8) := '0'; else for i in 1 to 7 loop q_m_temp(i) := q_m_temp(i-1) xor data_lat(i); end loop; q_m_temp(8) := '1'; end if; q_m <= q_m_temp; end process; process(cnt_q, q_m, den_lat, ctrl_lat) variable q_out : std_logic_vector(9 downto 0); begin if den_lat = '0' then cnt_d <= 0; case ctrl_lat is when "00" => q_out := "1101010100"; when "01" => q_out := "0010101011"; when "10" => q_out := "0101010100"; when "11" => q_out := "1010101011"; when others => --never occurs in synthesised system but keeps sims happy q_out := "0000000000"; end case; else if cnt_q = 0 or count_ones(q_m(7 downto 0)) = 4 then q_out(9) := not q_m(8); q_out(8) := q_m(8); if q_m(8) = '1' then q_out(7 downto 0) := q_m(7 downto 0); cnt_d <= cnt_q + 2 * (count_ones(q_m(7 downto 0)) - 4); else q_out(7 downto 0) := not q_m(7 downto 0); cnt_d <= cnt_q + 2 * (4 - count_ones(q_m(7 downto 0))); end if; else if ((cnt_q > 0) and (count_ones(q_m(7 downto 0)) > 4)) or ((cnt_q < 0) and (count_ones(q_m(7 downto 0)) < 4)) then q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not q_m(7 downto 0); if q_m(8) = '1' then cnt_d <= cnt_q + 2 + 2 * (4 - count_ones(q_m(7 downto 0))); else cnt_d <= cnt_q + 2 * (4 - count_ones(q_m(7 downto 0))); end if; else q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); if q_m(8) = '0' then cnt_d <= (cnt_q - 2) + 2 * (count_ones(q_m(7 downto 0)) - 4); else cnt_d <= cnt_q + 2 * (count_ones(q_m(7 downto 0)) - 4); end if; end if; end if; end if; tmds_int <= q_out; end process; end Behavioral; ================================================ FILE: vhdl_rx/dvi-tx/dvi_tx_tmds_phy.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; --DVI Transmitter TMDS PHY for Xilinx 7-series devices --Copyright (C) 2016 David Shah --Licensed under the MIT License --This handles the actual serialisation and transmission of 10bit encoded --TMDS data entity dvi_tx_tmds_phy is port( pixel_clock : in std_logic; --DVI pixel clock in ddr_bit_clock : in std_logic; --DDR bit clock i.e. pixel_clock*5 - must be from same MMCM/PLL as pixel_clock reset : in std_logic; --SERDES reset input data : in std_logic_vector(9 downto 0); tmds_lane : out std_logic_vector(1 downto 0) --1 is P, 0 is N ); end dvi_tx_tmds_phy; architecture Behavioral of dvi_tx_tmds_phy is signal reset_lat : std_logic; --reset latched to pixel clock signal shift_1, shift_2 : std_logic; --used to link master and slave OSERDES signal data_se : std_logic; --serialised data before output buffer begin process(pixel_clock) begin if rising_edge(pixel_clock) then reset_lat <= reset; end if; end process; master_oserdes : OSERDESE2 generic map( DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "SDR", DATA_WIDTH => 10, INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "MASTER", SRVAL_OQ => '0', SRVAL_TQ => '0', TBYTE_CTL => "FALSE", TBYTE_SRC => "FALSE", TRISTATE_WIDTH => 1) port map( CLK => ddr_bit_clock, CLKDIV => pixel_clock, D1 => data(0), D2 => data(1), D3 => data(2), D4 => data(3), D5 => data(4), D6 => data(5), D7 => data(6), D8 => data(7), OCE => '1', OFB => open, OQ => data_se, RST => reset_lat, SHIFTIN1 => shift_1, SHIFTIN2 => shift_2, SHIFTOUT1 => open, SHIFTOUT2 => open, TBYTEIN => '0', TCE => '1', TFB => open, TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0'); slave_oserdes : OSERDESE2 generic map( DATA_RATE_OQ => "DDR", DATA_RATE_TQ => "SDR", DATA_WIDTH => 10, INIT_OQ => '0', INIT_TQ => '0', SERDES_MODE => "SLAVE", SRVAL_OQ => '0', SRVAL_TQ => '0', TBYTE_CTL => "FALSE", TBYTE_SRC => "FALSE", TRISTATE_WIDTH => 1) port map( CLK => ddr_bit_clock, CLKDIV => pixel_clock, D1 => '0', D2 => '0', D3 => data(8), D4 => data(9), D5 => '0', D6 => '0', D7 => '0', D8 => '0', OCE => '1', OFB => open, OQ => open, RST => reset_lat, SHIFTIN1 => '0', SHIFTIN2 => '0', SHIFTOUT1 => shift_1, SHIFTOUT2 => shift_2, TBYTEIN => '0', TCE => '1', TFB => open, TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0'); outbuf : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST") port map ( O => tmds_lane(1), OB => tmds_lane(0), I => data_se); end Behavioral; ================================================ FILE: vhdl_rx/dvi-tx/dvi_tx_top.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; --Simple DVI Transmitter for Xilinx 7-series devices --Copyright (C) 2016 David Shah --Licensed under the MIT License --This is a minimal DVI transmitter core designed for Xilinx 7-series devices --and tested using the HDMI output the Digilent Genesys 2 board (Kintex-7 XC7K325T) entity dvi_tx is port( pixel_clock : in std_logic; --pixel clock input ddr_bit_clock : in std_logic; --DDR bit clock i.e. pixel_clock*5 - must be from same MMCM/PLL as pixel_clock reset : in std_logic; --synchronous active high reset input den : in std_logic; --video data valid input (active high) hsync : in std_logic; --video hsync input (polarity is timing dependent) vsync : in std_logic; --video vsync input (polarity is timing dependent) pixel_data : in std_logic_vector(23 downto 0); --24-bit video data tmds_clk : out std_logic_vector(1 downto 0); --TMDS clock lane; 1 is P, 0 is N tmds_d0 : out std_logic_vector(1 downto 0); --TMDS data lanes; 1 is P, 0 is N tmds_d1 : out std_logic_vector(1 downto 0); tmds_d2 : out std_logic_vector(1 downto 0)); end dvi_tx; architecture Behavioral of dvi_tx is signal ctrl : std_logic_vector(5 downto 0); --TMDS control signal states signal tmds_enc : std_logic_vector(29 downto 0); --TMDS encoded data type tmds_lanes_t is array (0 to 2) of std_logic_vector(1 downto 0); signal tmds_lanes : tmds_lanes_t; begin ctrl(0) <= hsync; ctrl(1) <= vsync; ctrl(5 downto 2) <= "0000"; gen_lane : for i in 0 to 2 generate lane_enc : entity work.dvi_tx_tmds_enc port map( clock => pixel_clock, reset => reset, den => den, data => pixel_data(((8*i) + 7) downto (8*i)), ctrl => ctrl(((2*i) + 1) downto (2*i)), tmds => tmds_enc( ((10*i) + 9) downto (10*i))); lane_phy : entity work.dvi_tx_tmds_phy port map( pixel_clock => pixel_clock, ddr_bit_clock => ddr_bit_clock, reset => reset, data => tmds_enc( ((10*i) + 9) downto (10*i)), tmds_lane => tmds_lanes(i)); end generate; clock_phy : entity work.dvi_tx_clk_drv port map( pixel_clock => pixel_clock, tmds_clk => tmds_clk); tmds_d0 <= tmds_lanes(0); tmds_d1 <= tmds_lanes(1); tmds_d2 <= tmds_lanes(2); end Behavioral; ================================================ FILE: vhdl_rx/examples/.gitignore ================================================ ######################################################################################################### ## This is an example .gitignore file for Vivado, please treat it as an example as ## it might not be complete. In addition, XAPP 1165 should be followed. ######################################################################################################### ######### #Exclude all ######### * !*/ !.gitignore ########################################################################### ## VIVADO ########################################################################### ######### #Source files: ######### #Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. !*.vhd !*.v !*.bd !*.edif ######### #IP files ######### #.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products #.xci + .dcp: implementation possible but not re-synthesis #*.xci(www.spiritconsortium.org) !*.xci *.dcp(checkpoint files) #!*.dcp *.vds *.pb #All bd comments and layout coordinates are stored within .ui !*.ui !*.ooc ######### #System Generator ######### !*.mdl !*.slx !*.bxml ######### #Simulation logic analyzer ######### !*.wcfg !*.coe ######### #MIG ######### !*.prj !*.mem ######### #Project files ######### #XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) #Do NOT ignore *.xpr files !*.xpr #Include *.xml files for 2013.4 or earlier version *.xml ######### #Constraint files ######### #Do NOT ignore *.xdc files !*.xdc ######### #TCL - files ######### !*.tcl ######### #Journal - files ######### *.jou ######### #Reports ######### *.rpt *.txt *.vdi ######### #C-files ######### !*.c !*.h !*.elf !*.bmm !*.xmp ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/54144841a4506c29.xci ================================================ xilinx.com ipcache 54144841a4506c29 0 dvi_pll MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 0.010 100.0 0.010 BUFG 136.844 false 157.836 50.000 124 0.000 1 true BUFG 105.471 false 157.836 50.000 620 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel pixel_clock false dvi_bit_clock false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto dvi_pll daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 31 0.000 false 5.0 10.0 10 0.500 0.000 false 2 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 5 None 0.010 0.010 false 2 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 sysclk PLL mmcm_adv 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false false false false false true false false false false false kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE e2451eba 54144841a4506c29 dvi_pll IP_Unknown 2 TRUE . . 2016.3 GLOBAL ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 16:22:12 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v // Design : dvi_pll // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire dvi_bit_clock; wire pixel_clock; wire sysclk; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz inst (.dvi_bit_clock(dvi_bit_clock), .pixel_clock(pixel_clock), .sysclk(sysclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire clkfbout_buf_dvi_pll; wire clkfbout_dvi_pll; wire dvi_bit_clock; wire dvi_bit_clock_dvi_pll; wire pixel_clock; wire pixel_clock_dvi_pll; wire sysclk; wire sysclk_dvi_pll; wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED; wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_dvi_pll), .O(clkfbout_buf_dvi_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_dvi_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout1_buf (.I(pixel_clock_dvi_pll), .O(pixel_clock)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout2_buf (.I(dvi_bit_clock_dvi_pll), .O(dvi_bit_clock)); (* BOX_TYPE = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(31), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(10), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(5), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_adv_inst (.CLKFBIN(clkfbout_buf_dvi_pll), .CLKFBOUT(clkfbout_dvi_pll), .CLKIN1(sysclk_dvi_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(pixel_clock_dvi_pll), .CLKOUT1(dvi_bit_clock_dvi_pll), .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED), .PWRDWN(1'b0), .RST(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 16:22:12 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v // Design : dvi_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pixel_clock, dvi_bit_clock, sysclk) /* synthesis syn_black_box black_box_pad_pin="pixel_clock,dvi_bit_clock,sysclk" */; output pixel_clock; output dvi_bit_clock; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/548aa35948ad692b.xci ================================================ xilinx.com ipcache 548aa35948ad692b 0 camera_pll MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 0.010 100.0 0.010 BUFG 280.569 false 321.802 50.000 145 0.000 1 true BUFG 391.507 false 321.802 50.000 24.4 0.000 1 true BUFG 519.540 false 321.802 50.000 5 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel camera_pixel_clock false camera_mclk false i2c_clkin false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto camera_pll daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 25.375 0.000 false 5.0 10.0 4.375 0.500 0.000 false 26 0.500 0.000 false 127 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 8 None 0.010 0.010 false 3 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 sysclk MMCM mmcm_adv 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false false false false false true false false false false false kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE e2451eba 548aa35948ad692b camera_pll IP_Unknown 2 TRUE . . 2016.3 GLOBAL ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 14:32:35 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.v // Design : camera_pll // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (camera_pixel_clock, camera_mclk, i2c_clkin, sysclk); output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; wire camera_mclk; wire camera_pixel_clock; wire i2c_clkin; wire sysclk; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_camera_pll_clk_wiz inst (.camera_mclk(camera_mclk), .camera_pixel_clock(camera_pixel_clock), .i2c_clkin(i2c_clkin), .sysclk(sysclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_camera_pll_clk_wiz (camera_pixel_clock, camera_mclk, i2c_clkin, sysclk); output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; wire camera_mclk; wire camera_mclk_camera_pll; wire camera_pixel_clock; wire camera_pixel_clock_camera_pll; wire clkfbout_buf_camera_pll; wire clkfbout_camera_pll; wire i2c_clkin; wire i2c_clkin_camera_pll; wire sysclk; wire sysclk_camera_pll; wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED; wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_camera_pll), .O(clkfbout_buf_camera_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_camera_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout1_buf (.I(camera_pixel_clock_camera_pll), .O(camera_pixel_clock)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout2_buf (.I(camera_mclk_camera_pll), .O(camera_mclk)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout3_buf (.I(i2c_clkin_camera_pll), .O(i2c_clkin)); (* BOX_TYPE = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT_F(25.375000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(4.375000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), .CLKOUT1_DIVIDE(26), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(127), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(8), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) mmcm_adv_inst (.CLKFBIN(clkfbout_buf_camera_pll), .CLKFBOUT(clkfbout_camera_pll), .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), .CLKIN1(sysclk_camera_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), .CLKOUT0(camera_pixel_clock_camera_pll), .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), .CLKOUT1(camera_mclk_camera_pll), .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), .CLKOUT2(i2c_clkin_camera_pll), .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED), .PSCLK(1'b0), .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), .PSEN(1'b0), .PSINCDEC(1'b0), .PWRDWN(1'b0), .RST(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 14:32:35 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.v // Design : camera_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(camera_pixel_clock, camera_mclk, i2c_clkin, sysclk) /* synthesis syn_black_box black_box_pad_pin="camera_pixel_clock,camera_mclk,i2c_clkin,sysclk" */; output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/75280199e9655e6a.xci ================================================ xilinx.com ipcache 75280199e9655e6a 0 dvi_pll MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 0.010 100.0 0.010 BUFG 111.449 false 139.507 50.000 148 0.000 1 true BUFG 87.091 false 139.507 50.000 740 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel pixel_clock false dvi_bit_clock false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto dvi_pll daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 37 0.000 false 5.0 10.0 10 0.500 0.000 false 2 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 5 None 0.010 0.010 false 2 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 sysclk PLL mmcm_adv 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false false false false false true false false false false false kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE e2451eba 75280199e9655e6a dvi_pll IP_Unknown 2 TRUE . . 2016.3 GLOBAL ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/dvi_pll_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 17:05:27 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v // Design : dvi_pll // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire dvi_bit_clock; wire pixel_clock; wire sysclk; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz inst (.dvi_bit_clock(dvi_bit_clock), .pixel_clock(pixel_clock), .sysclk(sysclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire clkfbout_buf_dvi_pll; wire clkfbout_dvi_pll; wire dvi_bit_clock; wire dvi_bit_clock_dvi_pll; wire pixel_clock; wire pixel_clock_dvi_pll; wire sysclk; wire sysclk_dvi_pll; wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED; wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_dvi_pll), .O(clkfbout_buf_dvi_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_dvi_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout1_buf (.I(pixel_clock_dvi_pll), .O(pixel_clock)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout2_buf (.I(dvi_bit_clock_dvi_pll), .O(dvi_bit_clock)); (* BOX_TYPE = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(37), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(10), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(5), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_adv_inst (.CLKFBIN(clkfbout_buf_dvi_pll), .CLKFBOUT(clkfbout_dvi_pll), .CLKIN1(sysclk_dvi_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(pixel_clock_dvi_pll), .CLKOUT1(dvi_bit_clock_dvi_pll), .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED), .PWRDWN(1'b0), .RST(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/dvi_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 17:05:27 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v // Design : dvi_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pixel_clock, dvi_bit_clock, sysclk) /* synthesis syn_black_box black_box_pad_pin="pixel_clock,dvi_bit_clock,sysclk" */; output pixel_clock; output dvi_bit_clock; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll/camera_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 14:32:35 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top camera_pll -prefix // camera_pll_ camera_pll_stub.v // Design : camera_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module camera_pll(camera_pixel_clock, camera_mclk, i2c_clkin, sysclk) /* synthesis syn_black_box black_box_pad_pin="camera_pixel_clock,camera_mclk,i2c_clkin,sysclk" */; output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/ddr3_if/ddr3_if_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:09:09 2016 // Host : david-xilinx-vm running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top ddr3_if -prefix // ddr3_if_ ddr3_if_stub.v // Design : ddr3_if // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module ddr3_if(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, init_calib_complete, device_temp, sys_rst) /* synthesis syn_black_box black_box_pad_pin="ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_n; inout [3:0]ddr3_dqs_p; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output ddr3_ras_n; output ddr3_cas_n; output ddr3_we_n; output ddr3_reset_n; output [0:0]ddr3_ck_p; output [0:0]ddr3_ck_n; output [0:0]ddr3_cke; output [0:0]ddr3_cs_n; output [3:0]ddr3_dm; output [0:0]ddr3_odt; input sys_clk_i; output ui_clk; output ui_clk_sync_rst; output mmcm_locked; input aresetn; input app_sr_req; input app_ref_req; input app_zq_req; output app_sr_active; output app_ref_ack; output app_zq_ack; input [0:0]s_axi_awid; input [29:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input s_axi_awvalid; output s_axi_awready; input [255:0]s_axi_wdata; input [31:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; input s_axi_bready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input [0:0]s_axi_arid; input [29:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input s_axi_arvalid; output s_axi_arready; input s_axi_rready; output [0:0]s_axi_rid; output [255:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; output init_calib_complete; output [11:0]device_temp; input sys_rst; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll/dvi_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 17:05:27 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v // Design : dvi_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module dvi_pll(pixel_clock, dvi_bit_clock, sysclk) /* synthesis syn_black_box black_box_pad_pin="pixel_clock,dvi_bit_clock,sysclk" */; output pixel_clock; output dvi_bit_clock; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/ila_0/ila_0_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Sat Nov 12 19:23:02 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ila_0/ila_0_stub.v // Design : ila_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "ila,Vivado 2016.3" *) module ila_0(clk, probe0) /* synthesis syn_black_box black_box_pad_pin="clk,probe0[8:0]" */; input clk; input [8:0]probe0; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/input_line_buffer/input_line_buffer_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:41:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v // Design : input_line_buffer // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) module input_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb) /* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[63:0],clkb,addrb[9:0],doutb[255:0]" */; input clka; input ena; input [0:0]wea; input [11:0]addra; input [63:0]dina; input clkb; input [9:0]addrb; output [255:0]doutb; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/output_line_buffer/output_line_buffer_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:42:01 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v // Design : output_line_buffer // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) module output_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb) /* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[255:0],clkb,addrb[11:0],doutb[63:0]" */; input clka; input ena; input [0:0]wea; input [9:0]addra; input [255:0]dina; input clkb; input [11:0]addrb; output [63:0]doutb; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/hdl/fifo_generator_v13_1_rfs.v ================================================ `pragma protect begin_protected `pragma protect version = 1 `pragma protect encrypt_agent = "XILINX" `pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block iCMCAmpnUKHzhjQEOGn7uHF8rzR6z6Q1KaqR86pF7GoO/ymK5vTIDTnNa9nKFdhoYtxNaHsWt5kN VFJc10LTKA== `pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block FFKI8J5LdjZtpODsN7pt+4OeAKOC8QjdxFp3gAJt8IiHZrmYepy7EgOh0P0ffApbaq0puFw9svm5 4aBPja6YuWgg7h7xNLN7wLHVUwJu+lOgLAKpk+f6Ng68Hdt4pc7b+sadbOGpLgi6XNE8X7BaPE1/ 1UBvmcWYAEvHJ5euTyA= `pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block UFtUuQ7LNNNstYC8OJZ1mZ8iEM878Hd3HgzdT2mKNF5tupw+rz5pwpvEiTElyG4e6KhcApeDVHom F+ge+iphHc+EkBINqnnEWPeyK9vbiYFxgP9RhiPBYDlGkGNxTDdYmM0kdg4/KuxlCNFqZNHWOpbR 25RTOqHyC1NGXpqnLgY= `pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `pragma protect key_block 1bvgu80gmzu2/2STP2z1dP+c59762Ntm9HVjEj1cQ5zpmEgBhYnZAWC3I1Aub88d7zlgY3jC5WfF yJfrBnrex+QQB+omjWcIgNmHSlVQEAa8B/7ZfapdLEtyPWbhR3ESAdT9ifMNXhbIKI6/6pxI69xL WQeXxSwjZUSeD3l1R5DlYnccG0/coE4cjAbDpLxadhd4XbPE5Eb/l5zjOutFozEOMJuJifhGPxpt clWZDvrK2ebtrkdJeOLIqPrryQhuh2Ul0Fe89cfqvhP4pfTSQuHM6wjgf3g4gI8CoyqLJ+7RcfBv XF4xiBcq7ly4eqDmBZ6ESOSNUR9K4pzdpVpxRw== `pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `pragma protect key_block V2wQbj5ws+RFb01e4/hVx3v2DLlfwLikAIjVjWf3BTaVlJVidhZ8Mn8kAflGhKRNAmXAG3wXOif8 fifCIiVrnszRJfRpY4Okq9RA0lc43SIZjIHWpZWN9SFT8BS5rDysaaFrV+4xQKTB4K6W38YFUiG/ PPc0osc/cnjCbXrgDV/DVsMBdtlpBq83LRpqWAIodFoHpQGf31BfsX/EoOTo5ntXFZoovFM+69rJ OUIZuCQ1otv4tQToThhbG5Gj4A/t/exgA2L2Biwt3pyTStnNwZrfRTuJqcCVtGkLNZTl3DlwxxnT vf7FZye/qhmPNSIR1DNeHWm0xYYZ/jwy6FD4EQ== `pragma protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `pragma protect key_block wwnJlZhlzdPKP+rMWc3Dx2+QDO+OuWE3mTPC5QjO9fGoMAbyT6CyUraAY0Sp+z0iQOkVvPSPGzzp x0e52CDZxf1mho3TicK7tIy7J3D+PZiccAgUujw31RoihkpPVapt35uQWL4Pu8q6yJ7s7fvQ2G1/ YwwQD6yp8SZsGJ7k0TslbLRJvfZze0XcsIIgLYwlD5gGulXXXi5yGaezKBYwqmZAru4DfBecphz9 Y87nmRqjgFW9rAU2SwckBn8xsSirT4eSKeSRHQvXV78dfm36vYul3r82HYgpAVax6qQqXR8tt/pV D1CodXioEFNGvtJqV29rJVkNa9RD1q5qLsbOpQ== `pragma protect data_method = "AES128-CBC" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 438576) `pragma protect data_block Ppwd2Ot4t2UGFpv57+IF7Bgd0fA+7s1yVCuCO3q986PbCIPay4El6J5fl1RF2/CIMAS0I7qwsewa 2QukhxV2KQgR8gtYtwzIkuE/Zkww6WVgXB/XNTz0mBN15AeyNy+axXmZy6+iDsfBytMNFV60E+bl pKvuo/bIBVc5mQdEbc0X/t4F0Fs7MhSahL4zEucnoxU2drgy6bTz9aK1O3Bjddb7xof9agt2+PxT NBCex10JBPmnfohv67nRStY07MhrH/TdJJsLzzi1XPjTWfMSy6KERthXgEsEP4iluZkIRzGyuq61 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= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block icwBRV97stUfR2Mn0wfPioI0eY3zGZJF4gSa++nlQlMi8xdqEhl343ha2TeCedqJlXwUNOMTshjg NWAZ0CnPtg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KdJiATwLz7apgDVo1m61iNvEkKe0M4UdBpI9Yd5Ge670sdg1t/Nie7/y7x7SOpFtKcG79N3mDoiw bP4Lo28OJmNglVRWiKdTRUXoQr1KC8IPt4mFyf8RW+0wysmhFnEJpQp5SwugZAg4ZiK4FJrJlEZp aSpgrgqxILRzspwvJ28= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block SEJEAo+4DoRBD70Ek1O2LvfMayFQjSsQ6O1GJG8EOchOxWL4gH+izXdYttq1qTGn/KE0kJRFDUcX A+ZQ8kqk+Eda70AyokFzsXsNSPHzlbWGhztR1gvMy+dW963rNBnhXvIDRr9xQxdB0S9wFcz7sOOD N1RSFCm4eWHHRbqFsdE= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Hw6LuFnFxQVdpUVS2z8t5Yf01nLm9evFIzBt0PsoeSy3+WLcOytdKrEuHuwtqg6ihJly/jHVrfAl TVavmgD4k59+ZTPqwkyYVYZr8LuzM7Fv3Zsc5/au2o+APxXDon/zrWg5zDCqJ+yGISpVFOGA0MAT 1rg2BXFph8wATddw8zNlEp6bqZO8wbVr8W+qZoEQF6sr6GzqUaybeo6b1Z3w1X7NKUdCSPPuX4db QRR5bHztRnOdGS2ZkX/0nKkoQdRgAGHSPbGl9d/YRB45phWabAM6E0g7GJRxyuqw+AKvG85eSMKN V6SyOVpBvhsf3QR2XAMBRIjaI2XLG0cVK3U5SA== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block f1rsayuAPFUtBwuAa6sFvNELSdf5C/KR4epVKFI5FedDC7MXninDZvVIr8Ro+3EmB5CE52O3Cses OzyWKYv6YZZKdPiFqafxQGdjnlqjoxI1gThSKKHQBU1hBfjbwsxmpQK42hqhWzSCpeRTJcjV1jcg aVPLy5PWglGMv00FiULQXmmn5GFwuKdr+Bnk+e2BuHMI4hipT8VA3cn5wgWr03pZFoefI8cpN+oG u9Ot12GyURIz66i6gWxGmq24zuJUslhyvcG/IxJB/b9eaSe9bwz573Uy7K+hKZAT043fQL8TW7Ov mXUYJTHcnse0uXeW3bie9BUo6EE7Y9TB47lk3w== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block u0nDmA3YrWcfEk4185AhUszcR/nwHQHMMcbB6zFWjm8trTpyEdJp71iK4ywXp2oQ1lMSKg28ST8Y GUH/HaXAvnJIVIf9lm4LECEiUiGW8afQ0cwQ7j8ujiLlWTcu0tDGOvezlUc2E0EMkmYd/yAwxLcX QCiYzQrF83xIvL6pPU5XdJbaD7dD4CFOpFEQRnzHYTDxHZHUu7AGIhYCSDrXQ5OQ6te9Q4sUdPJS /KiTKe33AZgktXIhotf5HgtgK/xiCoCoxnSbz6PwQCkJfuQJUXFVua3fEYo6DkxeRwgmhGEr+1Nx RBmwCvu87h7nHZQ60sX5T9NikshAxtWacHhtGQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1050704) `protect data_block y4LIg6JXGJqPWnX9Vrn3pyYNOtgNPDPGhiXH7uwtdddz/EjUHDSwkrQpWKuBvzWjUQfSUs2nfBvI arqGvWP6oLzplPIFyAnQCx/h3LkSedLqbVVe+woQduFCJW3vyNKY7nN/VtGNPMad9UaUasGS7Gui 0nDMiAjfFK1kMVPIQ+XEuYeqpHxioStuU5UrUZhopqbbo6LuDy2FbYyjsdEFGq8/cWK5kiWCrfxD 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/****************************************************************************** -- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ***************************************************************************** * * Filename: blk_mem_gen_v8_3_4.v * * Description: * This file is the Verilog behvarial model for the * Block Memory Generator Core. * ***************************************************************************** * Author: Xilinx * * History: Jan 11, 2006 Initial revision * Jun 11, 2007 Added independent register stages for * Port A and Port B (IP1_Jm/v2.5) * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) * Mar 13, 2008 Behavioral model optimizations * April 07, 2009 : Added support for Spartan-6 and Virtex-6 * features, including the following: * (i) error injection, detection and/or correction * (ii) reset priority * (iii) special reset behavior * *****************************************************************************/ `timescale 1ps/1ps module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5); parameter INIT = 64'h0000000000000000; input I0, I1, I2, I3, I4, I5; output O; reg O; reg tmp; always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; if ( tmp == 0 || tmp == 1) O = INIT[{I5, I4, I3, I2, I1, I0}]; end endmodule module beh_vlog_muxf7_v8_3 (O, I0, I1, S); output O; reg O; input I0, I1, S; always @(I0 or I1 or S) if (S) O = I1; else O = I0; endmodule module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q<= 1'b0; else Q<= #FLOP_DELAY D; endmodule module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, D, PRE; reg Q; initial Q= 1'b0; always @(posedge C ) if (PRE) Q <= 1'b1; else Q <= #FLOP_DELAY D; endmodule module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CE, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q <= 1'b0; else if (CE) Q <= #FLOP_DELAY D; endmodule module write_netlist_v8_3 #( parameter C_AXI_TYPE = 0 ) ( S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c ); input S_ACLK; input S_ARESETN; input S_AXI_AWVALID; input S_AXI_WVALID; input S_AXI_BREADY; input w_last_c; input bready_timeout_c; output aw_ready_r; output S_AXI_WREADY; output S_AXI_BVALID; output S_AXI_WR_EN; output addr_en_c; output incr_addr_c; output bvalid_c; //------------------------------------------------------------------------- //AXI LITE //------------------------------------------------------------------------- generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm wire w_ready_r_7; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSignal_bvalid_c; wire NlwRenamedSignal_incr_addr_c; wire present_state_FSM_FFd3_13; wire present_state_FSM_FFd2_14; wire present_state_FSM_FFd1_15; wire present_state_FSM_FFd4_16; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd4_In1_21; wire [0:0] Mmux_aw_ready_c ; begin assign S_AXI_WREADY = w_ready_r_7, S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, incr_addr_c = NlwRenamedSignal_incr_addr_c, bvalid_c = NlwRenamedSignal_bvalid_c; assign NlwRenamedSignal_incr_addr_c = 1'b0; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_7) ); beh_vlog_ff_pre_v8_3 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_16) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_13) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_15) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000055554440)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000088880800)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( S_AXI_WVALID), .I2 ( bready_timeout_c), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000AAAA2000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_WVALID), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( addr_en_c) ); STATE_LOGIC_v8_3 #( .INIT (64'hF5F07570F5F05500)) Mmux_w_ready_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( w_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd3_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd1_15), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_14), .I2 ( present_state_FSM_FFd3_13), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSignal_bvalid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h2F0F27072F0F2200)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( present_state_FSM_FFd4_In1_21) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_In1_21), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h7535753575305500)) Mmux_aw_ready_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_WVALID), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 ( present_state_FSM_FFd2_14), .O ( Mmux_aw_ready_c[0]) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000F8)) Mmux_aw_ready_c_0_2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( Mmux_aw_ready_c[0]), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( aw_ready_c) ); end end endgenerate //--------------------------------------------------------------------- // AXI FULL //--------------------------------------------------------------------- generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm wire w_ready_r_8; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSig_OI_bvalid_c; wire present_state_FSM_FFd1_16; wire present_state_FSM_FFd4_17; wire present_state_FSM_FFd3_18; wire present_state_FSM_FFd2_19; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd2_In1_24; wire present_state_FSM_FFd4_In1_25; wire N2; wire N4; begin assign S_AXI_WREADY = w_ready_r_8, bvalid_c = NlwRenamedSig_OI_bvalid_c, S_AXI_BVALID = 1'b0; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_8) ); beh_vlog_ff_pre_v8_3 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_17) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_18) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_19) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_16) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000005540)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd4_17), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_3 #( .INIT (64'hBF3FBB33AF0FAA00)) Mmux_aw_ready_c_0_2 ( .I0 ( S_AXI_BREADY), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd1_16), .I4 ( present_state_FSM_FFd4_17), .I5 ( NlwRenamedSig_OI_bvalid_c), .O ( aw_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'hAAAAAAAA20000000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( S_AXI_WVALID), .I4 ( w_last_c), .I5 ( present_state_FSM_FFd4_17), .O ( addr_en_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_19), .I2 ( present_state_FSM_FFd3_18), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( S_AXI_WR_EN) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000002220)) Mmux_incr_addr_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( incr_addr_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000008880)) Mmux_aw_ready_c_0_11 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSig_OI_bvalid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000000000D5C0)) present_state_FSM_FFd2_In1 ( .I0 ( w_last_c), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd4_17), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd2_In1_24) ); STATE_LOGIC_v8_3 #( .INIT (64'hFFFFAAAA08AAAAAA)) present_state_FSM_FFd2_In2 ( .I0 ( present_state_FSM_FFd2_19), .I1 ( S_AXI_AWVALID), .I2 ( bready_timeout_c), .I3 ( w_last_c), .I4 ( S_AXI_WVALID), .I5 ( present_state_FSM_FFd2_In1_24), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00C0004000C00000)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( w_last_c), .I2 ( S_AXI_WVALID), .I3 ( bready_timeout_c), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( present_state_FSM_FFd4_In1_25) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000FFFF88F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_16), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_17), .I3 ( S_AXI_AWVALID), .I4 ( present_state_FSM_FFd4_In1_25), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000007)) Mmux_w_ready_c_0_SW0 ( .I0 ( w_last_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N2) ); STATE_LOGIC_v8_3 #( .INIT (64'hFABAFABAFAAAF000)) Mmux_w_ready_c_0_Q ( .I0 ( N2), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd4_17), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( w_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000008)) Mmux_aw_ready_c_0_11_SW0 ( .I0 ( bready_timeout_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N4) ); STATE_LOGIC_v8_3 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( w_last_c), .I1 ( N4), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 ( present_state_FSM_FFd1_16), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); end end endgenerate endmodule module read_netlist_v8_3 #( parameter C_AXI_TYPE = 1, parameter C_ADDRB_WIDTH = 12 ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); input S_AXI_R_LAST_INT; input S_ACLK; input S_ARESETN; input S_AXI_ARVALID; input S_AXI_RREADY; output S_AXI_INCR_ADDR; output S_AXI_ADDR_EN; output S_AXI_SINGLE_TRANS; output S_AXI_MUX_SEL; output S_AXI_R_LAST; output S_AXI_ARREADY; output S_AXI_RLAST; output S_AXI_RVALID; output S_AXI_RD_EN; input [7:0] S_AXI_ARLEN; wire present_state_FSM_FFd1_13 ; wire present_state_FSM_FFd2_14 ; wire gaxi_full_sm_outstanding_read_r_15 ; wire gaxi_full_sm_ar_ready_r_16 ; wire gaxi_full_sm_r_last_r_17 ; wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; wire gaxi_full_sm_r_valid_c ; wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; wire gaxi_full_sm_ar_ready_c ; wire gaxi_full_sm_outstanding_read_c ; wire NlwRenamedSig_OI_S_AXI_R_LAST ; wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; wire present_state_FSM_FFd2_In ; wire present_state_FSM_FFd1_In ; wire Mmux_S_AXI_R_LAST13 ; wire N01 ; wire N2 ; wire Mmux_gaxi_full_sm_ar_ready_c11 ; wire N4 ; wire N8 ; wire N9 ; wire N10 ; wire N11 ; wire N12 ; wire N13 ; assign S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, S_AXI_RLAST = gaxi_full_sm_r_last_r_17, S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_outstanding_read_r ( .C (S_ACLK), .CLR(S_ARESETN), .D(gaxi_full_sm_outstanding_read_c), .Q(gaxi_full_sm_outstanding_read_r_15) ); beh_vlog_ff_ce_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_r_valid_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (gaxi_full_sm_r_valid_c), .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_ar_ready_r ( .C (S_ACLK), .CLR (S_ARESETN), .D (gaxi_full_sm_ar_ready_c), .Q (gaxi_full_sm_ar_ready_r_16) ); beh_vlog_ff_ce_clr_v8_3 #( .INIT(1'b0)) gaxi_full_sm_r_last_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (NlwRenamedSig_OI_S_AXI_R_LAST), .Q (gaxi_full_sm_r_last_r_17) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C (S_ACLK), .CLR (S_ARESETN), .D (present_state_FSM_FFd1_In), .Q (present_state_FSM_FFd1_13) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000000000000B)) S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( .I0 ( S_AXI_RREADY), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000008)) Mmux_S_AXI_SINGLE_TRANS11 ( .I0 (S_AXI_ARVALID), .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_SINGLE_TRANS) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000004)) Mmux_S_AXI_ADDR_EN11 ( .I0 (present_state_FSM_FFd1_13), .I1 (S_AXI_ARVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_ADDR_EN) ); STATE_LOGIC_v8_3 #( .INIT (64'hECEE2022EEEE2022)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_ARVALID), .I1 ( present_state_FSM_FFd1_13), .I2 ( S_AXI_RREADY), .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I4 ( present_state_FSM_FFd2_14), .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000044440444)) Mmux_S_AXI_R_LAST131 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_RREADY), .I5 (1'b0), .O ( Mmux_S_AXI_R_LAST13) ); STATE_LOGIC_v8_3 #( .INIT (64'h4000FFFF40004000)) Mmux_S_AXI_INCR_ADDR11 ( .I0 ( S_AXI_R_LAST_INT), .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( Mmux_S_AXI_R_LAST13), .O ( S_AXI_INCR_ADDR) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000FE)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( .I0 ( S_AXI_ARLEN[2]), .I1 ( S_AXI_ARLEN[1]), .I2 ( S_AXI_ARLEN[0]), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N01) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000001)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( .I0 ( S_AXI_ARLEN[7]), .I1 ( S_AXI_ARLEN[6]), .I2 ( S_AXI_ARLEN[5]), .I3 ( S_AXI_ARLEN[4]), .I4 ( S_AXI_ARLEN[3]), .I5 ( N01), .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000007)) Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 ( 1'b0), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N2) ); STATE_LOGIC_v8_3 #( .INIT (64'h0020000002200200)) Mmux_gaxi_full_sm_outstanding_read_c1 ( .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd1_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( gaxi_full_sm_outstanding_read_r_15), .I5 ( N2), .O ( gaxi_full_sm_outstanding_read_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000004555)) Mmux_gaxi_full_sm_ar_ready_c12 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( 1'b0), .I5 ( 1'b0), .O ( Mmux_gaxi_full_sm_ar_ready_c11) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000EF)) Mmux_S_AXI_R_LAST11_SW0 ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N4) ); STATE_LOGIC_v8_3 #( .INIT (64'hFCAAFC0A00AA000A)) Mmux_S_AXI_R_LAST11 ( .I0 ( S_AXI_ARVALID), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( N4), .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .O ( gaxi_full_sm_r_valid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000AAAAAA08)) S_AXI_MUX_SEL1 ( .I0 (present_state_FSM_FFd1_13), .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (S_AXI_RREADY), .I3 (present_state_FSM_FFd2_14), .I4 (gaxi_full_sm_outstanding_read_r_15), .I5 (1'b0), .O (S_AXI_MUX_SEL) ); STATE_LOGIC_v8_3 #( .INIT (64'hF3F3F755A2A2A200)) Mmux_S_AXI_RD_EN11 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 ( S_AXI_RREADY), .I3 ( gaxi_full_sm_outstanding_read_r_15), .I4 ( present_state_FSM_FFd2_14), .I5 ( S_AXI_ARVALID), .O ( S_AXI_RD_EN) ); beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 ( .I0 ( N8), .I1 ( N9), .S ( present_state_FSM_FFd1_13), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000005410F4F0)) present_state_FSM_FFd1_In3_F ( .I0 ( S_AXI_RREADY), .I1 ( present_state_FSM_FFd2_14), .I2 ( S_AXI_ARVALID), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( 1'b0), .O ( N8) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000072FF7272)) present_state_FSM_FFd1_In3_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N9) ); beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 ( .I0 ( N10), .I1 ( N11), .S ( present_state_FSM_FFd1_13), .O ( gaxi_full_sm_ar_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000FFFF88A8)) Mmux_gaxi_full_sm_ar_ready_c14_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), .I5 ( 1'b0), .O ( N10) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000008D008D8D)) Mmux_gaxi_full_sm_ar_ready_c14_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N11) ); beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 ( .I0 ( N12), .I1 ( N13), .S ( present_state_FSM_FFd1_13), .O ( NlwRenamedSig_OI_S_AXI_R_LAST) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000088088888)) Mmux_S_AXI_R_LAST1_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N12) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000E400E4E4)) Mmux_S_AXI_R_LAST1_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( S_AXI_R_LAST_INT), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N13) ); endmodule module blk_mem_axi_write_wrapper_beh_v8_3 # ( // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; parameter C_WRITE_DEPTH_A = 0, parameter C_AXI_AWADDR_WIDTH = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_WDATA_WIDTH = 32, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, // AXI OUTSTANDING WRITES parameter C_AXI_OS_WR = 2 ) ( // AXI Global Signals input S_ACLK, input S_ARESETN, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, input [8-1:0] S_AXI_AWLEN, input [2:0] S_AXI_AWSIZE, input [1:0] S_AXI_AWBURST, input S_AXI_AWVALID, output S_AXI_AWREADY, input S_AXI_WVALID, output S_AXI_WREADY, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, output S_AXI_BVALID, input S_AXI_BREADY, // Signals for BMG interface output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, output S_AXI_WR_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: ((C_AXI_WDATA_WIDTH==16)?1: ((C_AXI_WDATA_WIDTH==32)?2: ((C_AXI_WDATA_WIDTH==64)?3: ((C_AXI_WDATA_WIDTH==128)?4: ((C_AXI_WDATA_WIDTH==256)?5:0)))))); wire bvalid_c ; reg bready_timeout_c = 0; wire [1:0] bvalid_rd_cnt_c; reg bvalid_r = 0; reg [2:0] bvalid_count_r = 0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; reg [1:0] bvalid_wr_cnt_r = 0; reg [1:0] bvalid_rd_cnt_r = 0; wire w_last_c ; wire addr_en_c ; wire incr_addr_c ; wire aw_ready_r ; wire dec_alen_c ; reg bvalid_d1_c = 0; reg [7:0] awlen_cntr_r = 0; reg [7:0] awlen_int = 0; reg [1:0] awburst_int = 0; integer total_bytes = 0; integer wrap_boundary = 0; integer wrap_base_addr = 0; integer num_of_bytes_c = 0; integer num_of_bytes_r = 0; // Array to store BIDs reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; wire S_AXI_BVALID_axi_wr_fsm; //------------------------------------- //AXI WRITE FSM COMPONENT INSTANTIATION //------------------------------------- write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm ( .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), .S_AXI_AWVALID(S_AXI_AWVALID), .aw_ready_r(aw_ready_r), .S_AXI_WVALID(S_AXI_WVALID), .S_AXI_WREADY(S_AXI_WREADY), .S_AXI_BREADY(S_AXI_BREADY), .S_AXI_WR_EN(S_AXI_WR_EN), .w_last_c(w_last_c), .bready_timeout_c(bready_timeout_c), .addr_en_c(addr_en_c), .incr_addr_c(incr_addr_c), .bvalid_c(bvalid_c), .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) ); //Wrap Address boundary calculation always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); total_bytes = (num_of_bytes_r)*(awlen_int+1); wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); wrap_boundary = wrap_base_addr+total_bytes; end //------------------------------------------------------------------------- // BMG address generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awaddr_reg <= 0; num_of_bytes_r <= 0; awburst_int <= 0; end else begin if (addr_en_c == 1'b1) begin awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; num_of_bytes_r <= num_of_bytes_c; awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); end else if (incr_addr_c == 1'b1) begin if (awburst_int == 2'b10) begin if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin awaddr_reg <= wrap_base_addr; end else begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end end end assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); //------------------------------------------------------------------------- // AXI wlast generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awlen_cntr_r <= 0; awlen_int <= 0; end else begin if (addr_en_c == 1'b1) begin awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; end else if (dec_alen_c == 1'b1) begin awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; end end end assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; assign dec_alen_c = (incr_addr_c | w_last_c); //------------------------------------------------------------------------- // Generation of bvalid counter for outstanding transactions //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_count_r <= 0; end else begin // bvalid_count_r generation if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; end else if (bvalid_c == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; end end end //------------------------------------------------------------------------- // Generation of bvalid when BID is used //------------------------------------------------------------------------- generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; bvalid_d1_c <= 0; end else begin // Delay the generation o bvalid_r for generation for BID bvalid_d1_c <= bvalid_c; //external bvalid signal generation if (bvalid_d1_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of bvalid when BID is not used //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; end else begin //external bvalid signal generation if (bvalid_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of Bready timeout //------------------------------------------------------------------------- always @(bvalid_count_r) begin // bready_timeout_c generation if(bvalid_count_r == C_AXI_OS_WR-1) begin bready_timeout_c <= 1'b1; end else begin bready_timeout_c <= 1'b0; end end //------------------------------------------------------------------------- // Generation of BID //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_wr_cnt_r <= 0; bvalid_rd_cnt_r <= 0; end else begin // STORE AWID IN AN ARRAY if(bvalid_c == 1'b1) begin bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; end // generate BID FROM AWID ARRAY bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; end end assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; //------------------------------------------------------------------------- // Storing AWID for generation of BID //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if(S_ARESETN == 1'b1) begin axi_bid_array[0] = 0; axi_bid_array[1] = 0; axi_bid_array[2] = 0; axi_bid_array[3] = 0; end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; end end end endgenerate assign S_AXI_BVALID = bvalid_r; assign S_AXI_AWREADY = aw_ready_r; endmodule module blk_mem_axi_read_wrapper_beh_v8_3 # ( //// AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_MEMORY_TYPE = 0, parameter C_WRITE_WIDTH_A = 4, parameter C_WRITE_DEPTH_A = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_PIPELINE_STAGES = 0, parameter C_AXI_ARADDR_WIDTH = 12, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_ADDRB_WIDTH = 12 ) ( //// AXI Global Signals input S_ACLK, input S_ARESETN, //// AXI Full/Lite Slave Read (Read side) input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, input [7:0] S_AXI_ARLEN, input [2:0] S_AXI_ARSIZE, input [1:0] S_AXI_ARBURST, input S_AXI_ARVALID, output S_AXI_ARREADY, output S_AXI_RLAST, output S_AXI_RVALID, input S_AXI_RREADY, input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, //// AXI Full/Lite Read Address Signals to BRAM output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, output S_AXI_RD_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: ((C_WRITE_WIDTH_A==16)?1: ((C_WRITE_WIDTH_A==32)?2: ((C_WRITE_WIDTH_A==64)?3: ((C_WRITE_WIDTH_A==128)?4: ((C_WRITE_WIDTH_A==256)?5:0)))))); reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; wire addr_en_c; wire rd_en_c; wire incr_addr_c; wire single_trans_c; wire dec_alen_c; wire mux_sel_c; wire r_last_c; wire r_last_int_c; wire [C_ADDRB_WIDTH-1 : 0] araddr_out; reg [7:0] arlen_int_r=0; reg [7:0] arlen_cntr=8'h01; reg [1:0] arburst_int_c=0; reg [1:0] arburst_int_r=0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; integer num_of_bytes_c = 0; integer total_bytes = 0; integer num_of_bytes_r = 0; integer wrap_base_addr_r = 0; integer wrap_boundary_r = 0; reg [7:0] arlen_int_c=0; integer total_bytes_c = 0; integer wrap_base_addr_c = 0; integer wrap_boundary_c = 0; assign dec_alen_c = incr_addr_c | r_last_int_c; read_netlist_v8_3 #(.C_AXI_TYPE (1), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_read_fsm ( .S_AXI_INCR_ADDR(incr_addr_c), .S_AXI_ADDR_EN(addr_en_c), .S_AXI_SINGLE_TRANS(single_trans_c), .S_AXI_MUX_SEL(mux_sel_c), .S_AXI_R_LAST(r_last_c), .S_AXI_R_LAST_INT(r_last_int_c), //// AXI Global Signals .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), //// AXI Full/Lite Slave Read (Read side) .S_AXI_ARLEN(S_AXI_ARLEN), .S_AXI_ARVALID(S_AXI_ARVALID), .S_AXI_ARREADY(S_AXI_ARREADY), .S_AXI_RLAST(S_AXI_RLAST), .S_AXI_RVALID(S_AXI_RVALID), .S_AXI_RREADY(S_AXI_RREADY), //// AXI Full/Lite Read Address Signals to BRAM .S_AXI_RD_EN(rd_en_c) ); always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); total_bytes = (num_of_bytes_r)*(arlen_int_r+1); wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); wrap_boundary_r = wrap_base_addr_r+total_bytes; //////// combinatorial from interface arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); wrap_boundary_c = wrap_base_addr_c+total_bytes_c; arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); end ////------------------------------------------------------------------------- //// BMG address generation ////------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin araddr_reg <= 0; arburst_int_r <= 0; num_of_bytes_r <= 0; end else begin if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin arburst_int_r <= arburst_int_c; num_of_bytes_r <= num_of_bytes_c; if (arburst_int_c == 2'b10) begin if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin araddr_reg <= wrap_base_addr_c; end else begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (addr_en_c == 1'b1) begin araddr_reg <= S_AXI_ARADDR; num_of_bytes_r <= num_of_bytes_c; arburst_int_r <= arburst_int_c; end else if (incr_addr_c == 1'b1) begin if (arburst_int_r == 2'b10) begin if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin araddr_reg <= wrap_base_addr_r; end else begin araddr_reg <= araddr_reg + num_of_bytes_r; end end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin araddr_reg <= araddr_reg + num_of_bytes_r; end end end end assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); ////----------------------------------------------------------------------- //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM ////----------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin arlen_cntr <= 8'h01; arlen_int_r <= 0; end else begin if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= S_AXI_ARLEN - 1'b1; end else if (addr_en_c == 1'b1) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; end else if (dec_alen_c == 1'b1) begin arlen_cntr <= arlen_cntr - 1'b1 ; end else begin arlen_cntr <= arlen_cntr; end end end assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; ////------------------------------------------------------------------------ //// AXI FULL FSM //// Mux Selection of ARADDR //// ARADDR is driven out from the read fsm based on the mux_sel_c //// Based on mux_sel either ARADDR is given out or the latched ARADDR is //// given out to BRAM ////------------------------------------------------------------------------ assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; ////------------------------------------------------------------------------ //// Assign output signals - AXI FULL FSM ////------------------------------------------------------------------------ assign S_AXI_RD_EN = rd_en_c; generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin S_AXI_RID <= 0; ar_id_r <= 0; end else begin if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin S_AXI_RID <= S_AXI_ARID; ar_id_r <= S_AXI_ARID; end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin ar_id_r <= S_AXI_ARID; end else if (rd_en_c == 1'b1) begin S_AXI_RID <= ar_id_r; end end end end endgenerate endmodule module blk_mem_axi_regs_fwd_v8_3 #(parameter C_DATA_WIDTH = 8 )( input ACLK, input ARESET, input S_VALID, output S_READY, input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, output M_VALID, input M_READY, output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA ); reg [C_DATA_WIDTH-1:0] STORAGE_DATA; wire S_READY_I; reg M_VALID_I; reg [1:0] ARESET_D; //assign local signal to its output signal assign S_READY = S_READY_I; assign M_VALID = M_VALID_I; always @(posedge ACLK) begin ARESET_D <= {ARESET_D[0], ARESET}; end //Save payload data whenever we have a transaction on the slave side always @(posedge ACLK or ARESET) begin if (ARESET == 1'b1) begin STORAGE_DATA <= 0; end else begin if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin STORAGE_DATA <= S_PAYLOAD_DATA; end end end always @(posedge ACLK) begin M_PAYLOAD_DATA = STORAGE_DATA; end //M_Valid set to high when we have a completed transfer on slave side //Is removed on a M_READY except if we have a new transfer on the slave side always @(posedge ACLK or ARESET_D) begin if (ARESET_D != 2'b00) begin M_VALID_I <= 1'b0; end else begin if (S_VALID == 1'b1) begin //Always set M_VALID_I when slave side is valid M_VALID_I <= 1'b1; end else if (M_READY == 1'b1 ) begin //Clear (or keep) when no slave side is valid but master side is ready M_VALID_I <= 1'b0; end end end //Slave Ready is either when Master side drives M_READY or we have space in our storage data assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); endmodule //***************************************************************************** // Output Register Stage module // // This module builds the output register stages of the memory. This module is // instantiated in the main memory module (blk_mem_gen_v8_3_4) which is // declared/implemented further down in this file. //***************************************************************************** module blk_mem_gen_v8_3_4_output_stage #(parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RST = 0, parameter C_RSTRAM = 0, parameter C_RST_PRIORITY = "CE", parameter C_INIT_VAL = "0", parameter C_HAS_EN = 0, parameter C_HAS_REGCE = 0, parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_MEM_OUTPUT_REGS = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter NUM_STAGES = 1, parameter C_EN_ECC_PIPE = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input RST, input EN, input REGCE, input [C_DATA_WIDTH-1:0] DIN_I, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN_I, input DBITERR_IN_I, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, input ECCPIPECE, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RST : Determines the presence of the RST port // C_RSTRAM : Determines if special reset behavior is used // C_RST_PRIORITY : Determines the priority between CE and SR // C_INIT_VAL : Initialization value // C_HAS_EN : Determines the presence of the EN port // C_HAS_REGCE : Determines the presence of the REGCE port // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // NUM_STAGES : Determines the number of output stages // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // RST : Reset input to reset memory outputs to a user-defined // reset state // EN : Enable all read and write operations // REGCE : Register Clock Enable to control each pipeline output // register stages // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// // Fix for CR-509792 localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; // Declare the pipeline registers // (includes mem output reg, mux pipeline stages, and mux output reg) reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; reg [REG_STAGES-1:0] sbiterr_regs; reg [REG_STAGES-1:0] dbiterr_regs; reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; reg [C_DATA_WIDTH-1:0] init_val ; //********************************************* // Wire off optional inputs based on parameters //********************************************* wire en_i; wire regce_i; wire rst_i; // Internal signals reg [C_DATA_WIDTH-1:0] DIN; reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; reg SBITERR_IN; reg DBITERR_IN; // Internal enable for output registers is tied to user EN or '1' depending // on parameters assign en_i = (C_HAS_EN==0 || EN); // Internal register enable for output registers is tied to user REGCE, EN or // '1' depending on parameters // For V4 ECC, REGCE is always 1 // Virtex-4 ECC Not Yet Supported assign regce_i = ((C_HAS_REGCE==1) && REGCE) || ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); //Internal SRR is tied to user RST or '0' depending on parameters assign rst_i = (C_HAS_RST==1) && RST; //**************************************************** // Power on: load up the output registers and latches //**************************************************** initial begin if (!($sscanf(init_str, "%h", init_val))) begin init_val = 0; end DOUT = init_val; RDADDRECC = 0; SBITERR = 1'b0; DBITERR = 1'b0; DIN = {(C_DATA_WIDTH){1'b0}}; RDADDRECC_IN = 0; SBITERR_IN = 0; DBITERR_IN = 0; // This will be one wider than need, but 0 is an error out_regs = {(REG_STAGES+1){init_val}}; rdaddrecc_regs = 0; sbiterr_regs = {(REG_STAGES+1){1'b0}}; dbiterr_regs = {(REG_STAGES+1){1'b0}}; end //*********************************************** // NUM_STAGES = 0 (No output registers. RAM only) //*********************************************** generate if (NUM_STAGES == 0) begin : zero_stages always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg always @* begin DIN = DIN_I; SBITERR_IN = SBITERR_IN_I; DBITERR_IN = DBITERR_IN_I; RDADDRECC_IN = RDADDRECC_IN_I; end end endgenerate generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg always @(posedge CLK) begin if(ECCPIPECE == 1) begin DIN <= #FLOP_DELAY DIN_I; SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; end end end endgenerate //*********************************************** // NUM_STAGES = 1 // (Mem Output Reg only or Mux Output Reg only) //*********************************************** // Possible valid combinations: // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) // +-----------------------------------------+ // | C_RSTRAM_* | Reset Behavior | // +----------------+------------------------+ // | 0 | Normal Behavior | // +----------------+------------------------+ // | 1 | Special Behavior | // +----------------+------------------------+ // // Normal = REGCE gates reset, as in the case of all families except S3ADSP. // Special = EN gates reset, as in the case of S3ADSP. generate if (NUM_STAGES == 1 && (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) begin : one_stages_norm always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end //end Priority conditions end //end RST Type conditions end //end one_stages_norm generate statement endgenerate // Special Reset Behavior for S3ADSP generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) begin : one_stage_splbhv always @(posedge CLK) begin if (en_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; end else if (regce_i && !rst_i) begin DOUT <= #FLOP_DELAY DIN; end //Output signal assignments end //end CLK end //end one_stage_splbhv generate statement endgenerate //************************************************************ // NUM_STAGES > 1 // Mem Output Reg + Mux Output Reg // or // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg // or // Mux Pipeline Stages (>0) + Mux Output Reg //************************************************************* generate if (NUM_STAGES > 1) begin : multi_stage //Asynchronous Reset always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end //end Priority conditions // Shift the data through the output stages if (en_i) begin out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; end end //end CLK end //end multi_stage generate statement endgenerate endmodule module blk_mem_gen_v8_3_4_softecc_output_reg_stage #(parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_USE_SOFTECC = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input [C_DATA_WIDTH-1:0] DIN, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN, input DBITERR_IN, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// reg [C_DATA_WIDTH-1:0] dout_i = 0; reg sbiterr_i = 0; reg dbiterr_i = 0; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; //*********************************************** // NO OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate //*********************************************** // WITH OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage always @(posedge CLK) begin dout_i <= #FLOP_DELAY DIN; rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; sbiterr_i <= #FLOP_DELAY SBITERR_IN; dbiterr_i <= #FLOP_DELAY DBITERR_IN; end always @* begin DOUT = dout_i; RDADDRECC = rdaddrecc_i; SBITERR = sbiterr_i; DBITERR = dbiterr_i; end //end always end //end in_or_out_stage generate statement endgenerate endmodule //***************************************************************************** // Main Memory module // // This module is the top-level behavioral model and this implements the RAM //***************************************************************************** module blk_mem_gen_v8_3_4_mem_module #(parameter C_CORENAME = "blk_mem_gen_v8_3_4", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_USE_BRAM_BLOCK = 0, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter FLOP_DELAY = 100, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_ECC_PIPE = 0, parameter C_DISABLE_WARN_BHV_RANGE = 0 ) (input CLKA, input RSTA, input ENA, input REGCEA, input [C_WEA_WIDTH-1:0] WEA, input [C_ADDRA_WIDTH-1:0] ADDRA, input [C_WRITE_WIDTH_A-1:0] DINA, output [C_READ_WIDTH_A-1:0] DOUTA, input CLKB, input RSTB, input ENB, input REGCEB, input [C_WEB_WIDTH-1:0] WEB, input [C_ADDRB_WIDTH-1:0] ADDRB, input [C_WRITE_WIDTH_B-1:0] DINB, output [C_READ_WIDTH_B-1:0] DOUTB, input INJECTSBITERR, input INJECTDBITERR, input ECCPIPECE, input SLEEP, output SBITERR, output DBITERR, output [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// // Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_4" and it is // only used by this module to print warning messages. It is neither passed // down from blk_mem_gen_v8_3_4_xst.v nor present in the instantiation template // coregen generates //*************************************************************************** // constants for the core behavior //*************************************************************************** // file handles for logging //-------------------------------------------------- localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range localparam COLLFILE = 32'h8000_0001; //stdout for coll detection localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors // other constants //-------------------------------------------------- localparam COLL_DELAY = 100; // 100 ps // locally derived parameters to determine memory shape //----------------------------------------------------- localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? C_WRITE_WIDTH_A : C_READ_WIDTH_A; localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? C_WRITE_WIDTH_B : C_READ_WIDTH_B; localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? MIN_WIDTH_A : MIN_WIDTH_B; localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? C_WRITE_DEPTH_A : C_READ_DEPTH_A; localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? C_WRITE_DEPTH_B : C_READ_DEPTH_B; localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? MAX_DEPTH_A : MAX_DEPTH_B; // locally derived parameters to assist memory access //---------------------------------------------------- // Calculate the width ratios of each port with respect to the narrowest // port localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; // To modify the LSBs of the 'wider' data to the actual // address value //---------------------------------------------------- localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; // If byte writes aren't being used, make sure BYTE_SIZE is not // wider than the memory elements to avoid compilation warnings localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; // The memory reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1]; reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; // ECC error arrays reg sbiterr_arr [0:MAX_DEPTH-1]; reg dbiterr_arr [0:MAX_DEPTH-1]; reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; // Memory output 'latches' reg [C_READ_WIDTH_A-1:0] memory_out_a; reg [C_READ_WIDTH_B-1:0] memory_out_b; // ECC error inputs and outputs from output_stage module: reg sbiterr_in; wire sbiterr_sdp; reg dbiterr_in; wire dbiterr_sdp; wire [C_READ_WIDTH_B-1:0] dout_i; wire dbiterr_i; wire sbiterr_i; wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; // Reset values reg [C_READ_WIDTH_A-1:0] inita_val; reg [C_READ_WIDTH_B-1:0] initb_val; // Collision detect reg is_collision; reg is_collision_a, is_collision_delay_a; reg is_collision_b, is_collision_delay_b; // Temporary variables for initialization //--------------------------------------- integer status; integer initfile; integer meminitfile; // data input buffer reg [C_WRITE_WIDTH_A-1:0] mif_data; reg [C_WRITE_WIDTH_A-1:0] mem_data; // string values in hex reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; // initialization filename reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE; //Constants used to calculate the effective address widths for each of the //four ports. integer cnt = 1; integer write_addr_a_width, read_addr_a_width; integer write_addr_b_width, read_addr_b_width; localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))))))); // Internal configuration parameters //--------------------------------------------- localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); localparam HAS_A_WRITE = (!IS_ROM); localparam HAS_B_WRITE = (C_MEM_TYPE==2); localparam HAS_A_READ = (C_MEM_TYPE!=1); localparam HAS_B_READ = (!SINGLE_PORT); localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); // Calculate the mux pipeline register stages for Port A and Port B //------------------------------------------------------------------ localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? C_MUX_PIPELINE_STAGES : 0; localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? C_MUX_PIPELINE_STAGES : 0; // Calculate total number of register stages in the core // ----------------------------------------------------- localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); wire ena_i; wire enb_i; wire reseta_i; wire resetb_i; wire [C_WEA_WIDTH-1:0] wea_i; wire [C_WEB_WIDTH-1:0] web_i; wire rea_i; wire reb_i; wire rsta_outp_stage; wire rstb_outp_stage; // ECC SBITERR/DBITERR Outputs // The ECC Behavior is modeled by the behavioral models only for Virtex-6. // For Virtex-5, these outputs will be tied to 0. assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; // This effectively wires off optional inputs assign ena_i = (C_HAS_ENA==0) || ENA; assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; //assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; // To Fix CR855535 assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0; assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; assign rea_i = (HAS_A_READ) ? ena_i : 'b0; assign reb_i = (HAS_B_READ) ? enb_i : 'b0; // These signals reset the memory latches assign reseta_i = ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); assign resetb_i = ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); // Tasks to access the memory //--------------------------- //************** // write_a //************** task write_a (input reg [C_ADDRA_WIDTH-1:0] addr, input reg [C_WEA_WIDTH-1:0] byte_en, input reg [C_WRITE_WIDTH_A-1:0] data, input inj_sbiterr, input inj_dbiterr); reg [C_WRITE_WIDTH_A-1:0] current_contents; reg [C_ADDRA_WIDTH-1:0] address; integer i; begin // Shift the address by the ratio address = (addr/WRITE_ADDR_A_DIV); if (address >= C_WRITE_DEPTH_A) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for A Write", C_CORENAME, addr); end // valid address end else begin // Combine w/ byte writes if (C_USE_BYTE_WEA) begin // Get the current memory contents if (WRITE_WIDTH_RATIO_A == 1) begin // Workaround for IUS 5.5 part-select issue current_contents = memory[address]; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin current_contents[MIN_WIDTH*i+:MIN_WIDTH] = memory[address*WRITE_WIDTH_RATIO_A + i]; end end // Apply incoming bytes if (C_WEA_WIDTH == 1) begin // Workaround for IUS 5.5 part-select issue if (byte_en[0]) begin current_contents = data; end end else begin for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin if (byte_en[i]) begin current_contents[BYTE_SIZE*i+:BYTE_SIZE] = data[BYTE_SIZE*i+:BYTE_SIZE]; end end end // No byte-writes, overwrite the whole word end else begin current_contents = data; end // Insert double bit errors: if (C_USE_ECC == 1) begin if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin // Modified for Implementing CR_859399 current_contents[0] = !(current_contents[30]); current_contents[1] = !(current_contents[62]); /*current_contents[0] = !(current_contents[0]); current_contents[1] = !(current_contents[1]);*/ end end // Insert softecc double bit errors: if (C_USE_SOFTECC == 1) begin if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; end end // Write data to memory if (WRITE_WIDTH_RATIO_A == 1) begin // Workaround for IUS 5.5 part-select issue memory[address*WRITE_WIDTH_RATIO_A] = current_contents; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin memory[address*WRITE_WIDTH_RATIO_A + i] = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; end end // Store the address at which error is injected: if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) begin sbiterr_arr[addr] = 1; end else begin sbiterr_arr[addr] = 0; end if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin dbiterr_arr[addr] = 1; end else begin dbiterr_arr[addr] = 0; end end // Store the address at which softecc error is injected: if (C_USE_SOFTECC == 1) begin if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) begin softecc_sbiterr_arr[addr] = 1; end else begin softecc_sbiterr_arr[addr] = 0; end if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin softecc_dbiterr_arr[addr] = 1; end else begin softecc_dbiterr_arr[addr] = 0; end end end end endtask //************** // write_b //************** task write_b (input reg [C_ADDRB_WIDTH-1:0] addr, input reg [C_WEB_WIDTH-1:0] byte_en, input reg [C_WRITE_WIDTH_B-1:0] data); reg [C_WRITE_WIDTH_B-1:0] current_contents; reg [C_ADDRB_WIDTH-1:0] address; integer i; begin // Shift the address by the ratio address = (addr/WRITE_ADDR_B_DIV); if (address >= C_WRITE_DEPTH_B) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for B Write", C_CORENAME, addr); end // valid address end else begin // Combine w/ byte writes if (C_USE_BYTE_WEB) begin // Get the current memory contents if (WRITE_WIDTH_RATIO_B == 1) begin // Workaround for IUS 5.5 part-select issue current_contents = memory[address]; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin current_contents[MIN_WIDTH*i+:MIN_WIDTH] = memory[address*WRITE_WIDTH_RATIO_B + i]; end end // Apply incoming bytes if (C_WEB_WIDTH == 1) begin // Workaround for IUS 5.5 part-select issue if (byte_en[0]) begin current_contents = data; end end else begin for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin if (byte_en[i]) begin current_contents[BYTE_SIZE*i+:BYTE_SIZE] = data[BYTE_SIZE*i+:BYTE_SIZE]; end end end // No byte-writes, overwrite the whole word end else begin current_contents = data; end // Write data to memory if (WRITE_WIDTH_RATIO_B == 1) begin // Workaround for IUS 5.5 part-select issue memory[address*WRITE_WIDTH_RATIO_B] = current_contents; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin memory[address*WRITE_WIDTH_RATIO_B + i] = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; end end end end endtask //************** // read_a //************** task read_a (input reg [C_ADDRA_WIDTH-1:0] addr, input reg reset); reg [C_ADDRA_WIDTH-1:0] address; integer i; begin if (reset) begin memory_out_a <= #FLOP_DELAY inita_val; end else begin // Shift the address by the ratio address = (addr/READ_ADDR_A_DIV); if (address >= C_READ_DEPTH_A) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for A Read", C_CORENAME, addr); end memory_out_a <= #FLOP_DELAY 'bX; // valid address end else begin if (READ_WIDTH_RATIO_A==1) begin memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; end else begin // Increment through the 'partial' words in the memory for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; end end //end READ_WIDTH_RATIO_A==1 loop end //end valid address loop end //end reset-data assignment loops end endtask //************** // read_b //************** task read_b (input reg [C_ADDRB_WIDTH-1:0] addr, input reg reset); reg [C_ADDRB_WIDTH-1:0] address; integer i; begin if (reset) begin memory_out_b <= #FLOP_DELAY initb_val; sbiterr_in <= #FLOP_DELAY 1'b0; dbiterr_in <= #FLOP_DELAY 1'b0; rdaddrecc_in <= #FLOP_DELAY 0; end else begin // Shift the address address = (addr/READ_ADDR_B_DIV); if (address >= C_READ_DEPTH_B) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for B Read", C_CORENAME, addr); end memory_out_b <= #FLOP_DELAY 'bX; sbiterr_in <= #FLOP_DELAY 1'bX; dbiterr_in <= #FLOP_DELAY 1'bX; rdaddrecc_in <= #FLOP_DELAY 'bX; // valid address end else begin if (READ_WIDTH_RATIO_B==1) begin memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; end else begin // Increment through the 'partial' words in the memory for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; end end if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin rdaddrecc_in <= #FLOP_DELAY addr; if (sbiterr_arr[addr] == 1) begin sbiterr_in <= #FLOP_DELAY 1'b1; end else begin sbiterr_in <= #FLOP_DELAY 1'b0; end if (dbiterr_arr[addr] == 1) begin dbiterr_in <= #FLOP_DELAY 1'b1; end else begin dbiterr_in <= #FLOP_DELAY 1'b0; end end else if (C_USE_SOFTECC == 1) begin rdaddrecc_in <= #FLOP_DELAY addr; if (softecc_sbiterr_arr[addr] == 1) begin sbiterr_in <= #FLOP_DELAY 1'b1; end else begin sbiterr_in <= #FLOP_DELAY 1'b0; end if (softecc_dbiterr_arr[addr] == 1) begin dbiterr_in <= #FLOP_DELAY 1'b1; end else begin dbiterr_in <= #FLOP_DELAY 1'b0; end end else begin rdaddrecc_in <= #FLOP_DELAY 0; dbiterr_in <= #FLOP_DELAY 1'b0; sbiterr_in <= #FLOP_DELAY 1'b0; end //end SOFTECC Loop end //end Valid address loop end //end reset-data assignment loops end endtask //************** // reset_a //************** task reset_a (input reg reset); begin if (reset) memory_out_a <= #FLOP_DELAY inita_val; end endtask //************** // reset_b //************** task reset_b (input reg reset); begin if (reset) memory_out_b <= #FLOP_DELAY initb_val; end endtask //************** // init_memory //************** task init_memory; integer i, j, addr_step; integer status; reg [C_WRITE_WIDTH_A-1:0] default_data; begin default_data = 0; //Display output message indicating that the behavioral model is being //initialized if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data..."); // Convert the default to hex if (C_USE_DEFAULT_DATA) begin if (default_data_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); $finish; end else begin status = $sscanf(default_data_str, "%h", default_data); if (status == 0) begin $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", "from C_DEFAULT_DATA: %0s"}, C_CORENAME, C_DEFAULT_DATA); $finish; end end end // Step by WRITE_ADDR_A_DIV through the memory via the // Port A write interface to hit every location once addr_step = WRITE_ADDR_A_DIV; // 'write' to every location with default (or 0) for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); end // Get specialized data from the MIF file if (C_LOAD_INIT_FILE) begin if (init_file_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", C_CORENAME); $finish; end else begin initfile = $fopen(init_file_str, "r"); if (initfile == 0) begin $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", "C_INIT_FILE_NAME: %0s!"}, C_CORENAME, init_file_str); $finish; end else begin // loop through the mif file, loading in the data for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin status = $fscanf(initfile, "%b", mif_data); if (status > 0) begin write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); end end $fclose(initfile); end //initfile end //init_file_str end //C_LOAD_INIT_FILE if (C_USE_BRAM_BLOCK) begin // Get specialized data from the MIF file if (C_INIT_FILE != "NONE") begin if (mem_init_file_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!", C_CORENAME); $finish; end else begin meminitfile = $fopen(mem_init_file_str, "r"); if (meminitfile == 0) begin $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", "C_INIT_FILE: %0s!"}, C_CORENAME, mem_init_file_str); $finish; end else begin // loop through the mif file, loading in the data $readmemh(mem_init_file_str, memory ); for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin end $fclose(meminitfile); end //meminitfile end //mem_init_file_str end //C_INIT_FILE end //C_USE_BRAM_BLOCK //Display output message indicating that the behavioral model is done //initializing if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator data initialization complete."); end endtask //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //******************* // collision_check //******************* function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, input integer iswrite_a, input reg [C_ADDRB_WIDTH-1:0] addr_b, input integer iswrite_b); reg c_aw_bw, c_aw_br, c_ar_bw; integer scaled_addra_to_waddrb_width; integer scaled_addrb_to_waddrb_width; integer scaled_addra_to_waddra_width; integer scaled_addrb_to_waddra_width; integer scaled_addra_to_raddrb_width; integer scaled_addrb_to_raddrb_width; integer scaled_addra_to_raddra_width; integer scaled_addrb_to_raddra_width; begin c_aw_bw = 0; c_aw_br = 0; c_ar_bw = 0; //If write_addr_b_width is smaller, scale both addresses to that width for //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to write_addr_b_width. Once both are scaled to //write_addr_b_width, compare. scaled_addra_to_waddrb_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-write_addr_b_width)); scaled_addrb_to_waddrb_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-write_addr_b_width)); //If write_addr_a_width is smaller, scale both addresses to that width for //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to write_addr_a_width. Once both are scaled to //write_addr_a_width, compare. scaled_addra_to_waddra_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-write_addr_a_width)); scaled_addrb_to_waddra_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-write_addr_a_width)); //If read_addr_b_width is smaller, scale both addresses to that width for //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to read_addr_b_width. Once both are scaled to //read_addr_b_width, compare. scaled_addra_to_raddrb_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-read_addr_b_width)); scaled_addrb_to_raddrb_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-read_addr_b_width)); //If read_addr_a_width is smaller, scale both addresses to that width for //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to read_addr_a_width. Once both are scaled to //read_addr_a_width, compare. scaled_addra_to_raddra_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-read_addr_a_width)); scaled_addrb_to_raddra_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-read_addr_a_width)); //Look for a write-write collision. In order for a write-write //collision to exist, both ports must have a write transaction. if (iswrite_a && iswrite_b) begin if (write_addr_a_width > write_addr_b_width) begin if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin c_aw_bw = 1; end else begin c_aw_bw = 0; end end else begin if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin c_aw_bw = 1; end else begin c_aw_bw = 0; end end //width end //iswrite_a and iswrite_b //If the B port is reading (which means it is enabled - so could be //a TX_WRITE or TX_READ), then check for a write-read collision). //This could happen whether or not a write-write collision exists due //to asymmetric write/read ports. if (iswrite_a) begin if (write_addr_a_width > read_addr_b_width) begin if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin c_aw_br = 1; end else begin c_aw_br = 0; end end else begin if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin c_aw_br = 1; end else begin c_aw_br = 0; end end //width end //iswrite_a //If the A port is reading (which means it is enabled - so could be // a TX_WRITE or TX_READ), then check for a write-read collision). //This could happen whether or not a write-write collision exists due // to asymmetric write/read ports. if (iswrite_b) begin if (read_addr_a_width > write_addr_b_width) begin if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin c_ar_bw = 1; end else begin c_ar_bw = 0; end end else begin if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin c_ar_bw = 1; end else begin c_ar_bw = 0; end end //width end //iswrite_b collision_check = c_aw_bw | c_aw_br | c_ar_bw; end endfunction //******************************* // power on values //******************************* initial begin // Load up the memory init_memory; // Load up the output registers and latches if ($sscanf(inita_str, "%h", inita_val)) begin memory_out_a = inita_val; end else begin memory_out_a = 0; end if ($sscanf(initb_str, "%h", initb_val)) begin memory_out_b = initb_val; end else begin memory_out_b = 0; end sbiterr_in = 1'b0; dbiterr_in = 1'b0; rdaddrecc_in = 0; // Determine the effective address widths for each of the 4 ports write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); end //*************************************************************************** // These are the main blocks which schedule read and write operations // Note that the reset priority feature at the latch stage is only supported // for Spartan-6. For other families, the default priority at the latch stage // is "CE" //*************************************************************************** // Synchronous clocks: schedule port operations with respect to // both write operating modes generate if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_wf_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_rf_wf always @(posedge CLKA) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_wf_rf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_rf_rf always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_wf_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_rf_nc always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_nc_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_nc_rf always @(posedge CLKA) begin //Read B if (reb_i) read_b(ADDRB, resetb_i); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_nc_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK) begin: com_clk_sched_default always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end endgenerate // Asynchronous clocks: port operation is independent generate if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); end end else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); end end else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); end end endgenerate generate if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf always @(posedge CLKB) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf always @(posedge CLKB) begin //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc always @(posedge CLKB) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); end end endgenerate //*************************************************************** // Instantiate the variable depth output register stage module //*************************************************************** // Port A assign rsta_outp_stage = RSTA & (~SLEEP); blk_mem_gen_v8_3_4_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTA), .C_RSTRAM (C_RSTRAM_A), .C_RST_PRIORITY (C_RST_PRIORITY_A), .C_INIT_VAL (C_INITA_VAL), .C_HAS_EN (C_HAS_ENA), .C_HAS_REGCE (C_HAS_REGCEA), .C_DATA_WIDTH (C_READ_WIDTH_A), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_A), .C_EN_ECC_PIPE (0), .FLOP_DELAY (FLOP_DELAY)) reg_a (.CLK (CLKA), .RST (rsta_outp_stage),//(RSTA), .EN (ENA), .REGCE (REGCEA), .DIN_I (memory_out_a), .DOUT (DOUTA), .SBITERR_IN_I (1'b0), .DBITERR_IN_I (1'b0), .SBITERR (), .DBITERR (), .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), .ECCPIPECE (1'b0), .RDADDRECC () ); assign rstb_outp_stage = RSTB & (~SLEEP); // Port B blk_mem_gen_v8_3_4_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTB), .C_RSTRAM (C_RSTRAM_B), .C_RST_PRIORITY (C_RST_PRIORITY_B), .C_INIT_VAL (C_INITB_VAL), .C_HAS_EN (C_HAS_ENB), .C_HAS_REGCE (C_HAS_REGCEB), .C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_B), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .FLOP_DELAY (FLOP_DELAY)) reg_b (.CLK (CLKB), .RST (rstb_outp_stage),//(RSTB), .EN (ENB), .REGCE (REGCEB), .DIN_I (memory_out_b), .DOUT (dout_i), .SBITERR_IN_I (sbiterr_in), .DBITERR_IN_I (dbiterr_in), .SBITERR (sbiterr_i), .DBITERR (dbiterr_i), .RDADDRECC_IN_I (rdaddrecc_in), .ECCPIPECE (ECCPIPECE), .RDADDRECC (rdaddrecc_i) ); //*************************************************************** // Instantiate the Input and Output register stages //*************************************************************** blk_mem_gen_v8_3_4_softecc_output_reg_stage #(.C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .FLOP_DELAY (FLOP_DELAY)) has_softecc_output_reg_stage (.CLK (CLKB), .DIN (dout_i), .DOUT (DOUTB), .SBITERR_IN (sbiterr_i), .DBITERR_IN (dbiterr_i), .SBITERR (sbiterr_sdp), .DBITERR (dbiterr_sdp), .RDADDRECC_IN (rdaddrecc_i), .RDADDRECC (rdaddrecc_sdp) ); //**************************************************** // Synchronous collision checks //**************************************************** // CR 780544 : To make verilog model's collison warnings in consistant with // vhdl model, the non-blocking assignments are replaced with blocking // assignments. generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision = 0; end end else begin is_collision = 0; end // If the write port is in READ_FIRST mode, there is no collision if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin is_collision = 0; end if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin is_collision = 0; end // Only flag if one of the accesses is a write if (is_collision && (wea_i || web_i)) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", wea_i ? "write" : "read", ADDRA, web_i ? "write" : "read", ADDRB); end end //**************************************************** // Asynchronous collision checks //**************************************************** end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll // Delay A and B addresses in order to mimic setup/hold times wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; wire [0:0] #COLL_DELAY wea_delay = wea_i; wire #COLL_DELAY ena_delay = ena_i; wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; wire [0:0] #COLL_DELAY web_delay = web_i; wire #COLL_DELAY enb_delay = enb_i; // Do the checks w/rt A always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_a = 0; end end else begin is_collision_a = 0; end if (ena_i && enb_delay) begin if(wea_i || web_delay) begin is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, web_delay); end else begin is_collision_delay_a = 0; end end else begin is_collision_delay_a = 0; end // Only flag if B access is a write if (is_collision_a && web_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, ADDRB); end else if (is_collision_delay_a && web_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, addrb_delay); end end // Do the checks w/rt B always @(posedge CLKB) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_b = 0; end end else begin is_collision_b = 0; end if (ena_delay && enb_i) begin if (wea_delay || web_i) begin is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, web_i); end else begin is_collision_delay_b = 0; end end else begin is_collision_delay_b = 0; end // Only flag if A access is a write if (is_collision_b && wea_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", ADDRA, web_i ? "write" : "read", ADDRB); end else if (is_collision_delay_b && wea_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", addra_delay, web_i ? "write" : "read", ADDRB); end end end endgenerate endmodule //***************************************************************************** // Top module wraps Input register and Memory module // // This module is the top-level behavioral model and this implements the memory // module and the input registers //***************************************************************************** module blk_mem_gen_v8_3_4 #(parameter C_CORENAME = "blk_mem_gen_v8_3_4", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_ELABORATION_DIR = "", parameter C_INTERFACE_TYPE = 0, parameter C_USE_BRAM_BLOCK = 0, parameter C_CTRL_ECC_ALGO = "NONE", parameter C_ENABLE_32BIT_ADDRESS = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", //parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_EN_ECC_PIPE = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_SLEEP_PIN = 0, parameter C_USE_URAM = 0, parameter C_EN_RDADDRA_CHG = 0, parameter C_EN_RDADDRB_CHG = 0, parameter C_EN_DEEPSLEEP_PIN = 0, parameter C_EN_SHUTDOWN_PIN = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_COUNT_36K_BRAM = "", parameter C_COUNT_18K_BRAM = "", parameter C_EST_POWER_SUMMARY = "", parameter C_DISABLE_WARN_BHV_RANGE = 0 ) (input clka, input rsta, input ena, input regcea, input [C_WEA_WIDTH-1:0] wea, input [C_ADDRA_WIDTH-1:0] addra, input [C_WRITE_WIDTH_A-1:0] dina, output [C_READ_WIDTH_A-1:0] douta, input clkb, input rstb, input enb, input regceb, input [C_WEB_WIDTH-1:0] web, input [C_ADDRB_WIDTH-1:0] addrb, input [C_WRITE_WIDTH_B-1:0] dinb, output [C_READ_WIDTH_B-1:0] doutb, input injectsbiterr, input injectdbiterr, output sbiterr, output dbiterr, output [C_ADDRB_WIDTH-1:0] rdaddrecc, input eccpipece, input sleep, input deepsleep, input shutdown, output rsta_busy, output rstb_busy, //AXI BMG Input and Output Port Declarations //AXI Global Signals input s_aclk, input s_aresetn, //AXI Full/lite slave write (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [31:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input s_axi_awvalid, output s_axi_awready, input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, input [C_WEA_WIDTH-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, input s_axi_bready, //AXI Full/lite slave read (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [31:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, input s_axi_rready, //AXI Full/lite sideband signals input s_axi_injectsbiterr, input s_axi_injectdbiterr, output s_axi_sbiterr, output s_axi_dbiterr, output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_HAS_SOFTECC_INPUT_REGS_A : // C_HAS_SOFTECC_OUTPUT_REGS_B : // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// wire SBITERR; wire DBITERR; wire S_AXI_AWREADY; wire S_AXI_WREADY; wire S_AXI_BVALID; wire S_AXI_ARREADY; wire S_AXI_RLAST; wire S_AXI_RVALID; wire S_AXI_SBITERR; wire S_AXI_DBITERR; wire [C_WEA_WIDTH-1:0] WEA = wea; wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; wire [C_WRITE_WIDTH_A-1:0] DINA = dina; wire [C_READ_WIDTH_A-1:0] DOUTA; wire [C_WEB_WIDTH-1:0] WEB = web; wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; wire [C_READ_WIDTH_B-1:0] DOUTB; wire [C_ADDRB_WIDTH-1:0] RDADDRECC; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; wire [31:0] S_AXI_AWADDR = s_axi_awaddr; wire [7:0] S_AXI_AWLEN = s_axi_awlen; wire [2:0] S_AXI_AWSIZE = s_axi_awsize; wire [1:0] S_AXI_AWBURST = s_axi_awburst; wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [1:0] S_AXI_BRESP; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; wire [31:0] S_AXI_ARADDR = s_axi_araddr; wire [7:0] S_AXI_ARLEN = s_axi_arlen; wire [2:0] S_AXI_ARSIZE = s_axi_arsize; wire [1:0] S_AXI_ARBURST = s_axi_arburst; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; wire [1:0] S_AXI_RRESP; wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; // Added to fix the simulation warning #CR731605 wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; wire ECCPIPECE; wire SLEEP; reg RSTA_BUSY = 0; reg RSTB_BUSY = 0; // Declaration of internal signals to avoid warnings #927399 wire CLKA; wire RSTA; wire ENA; wire REGCEA; wire CLKB; wire RSTB; wire ENB; wire REGCEB; wire INJECTSBITERR; wire INJECTDBITERR; wire S_ACLK; wire S_ARESETN; wire S_AXI_AWVALID; wire S_AXI_WLAST; wire S_AXI_WVALID; wire S_AXI_BREADY; wire S_AXI_ARVALID; wire S_AXI_RREADY; wire S_AXI_INJECTSBITERR; wire S_AXI_INJECTDBITERR; assign CLKA = clka; assign RSTA = rsta; assign ENA = ena; assign REGCEA = regcea; assign CLKB = clkb; assign RSTB = rstb; assign ENB = enb; assign REGCEB = regceb; assign INJECTSBITERR = injectsbiterr; assign INJECTDBITERR = injectdbiterr; assign ECCPIPECE = eccpipece; assign SLEEP = sleep; assign sbiterr = SBITERR; assign dbiterr = DBITERR; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; assign s_axi_sbiterr = S_AXI_SBITERR; assign s_axi_dbiterr = S_AXI_DBITERR; assign rsta_busy = RSTA_BUSY; assign rstb_busy = RSTB_BUSY; assign doutb = DOUTB; assign douta = DOUTA; assign rdaddrecc = RDADDRECC; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_rdaddrecc = S_AXI_RDADDRECC; localparam FLOP_DELAY = 100; // 100 ps reg injectsbiterr_in; reg injectdbiterr_in; reg rsta_in; reg ena_in; reg regcea_in; reg [C_WEA_WIDTH-1:0] wea_in; reg [C_ADDRA_WIDTH-1:0] addra_in; reg [C_WRITE_WIDTH_A-1:0] dina_in; wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; wire s_axi_wr_en_c; wire s_axi_rd_en_c; wire s_aresetn_a_c; wire [7:0] s_axi_arlen_c ; wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; wire [1:0] s_axi_rresp_c; wire s_axi_rlast_c; wire s_axi_rvalid_c; wire s_axi_rready_c; wire regceb_c; localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; // Safety logic related signals reg [4:0] RSTA_SHFT_REG = 0; reg POR_A = 0; reg [4:0] RSTB_SHFT_REG = 0; reg POR_B = 0; reg ENA_dly = 0; reg ENA_dly_D = 0; reg ENB_dly = 0; reg ENB_dly_D = 0; wire RSTA_I_SAFE; wire RSTB_I_SAFE; wire ENA_I_SAFE; wire ENB_I_SAFE; reg ram_rstram_a_busy = 0; reg ram_rstreg_a_busy = 0; reg ram_rstram_b_busy = 0; reg ram_rstreg_b_busy = 0; reg ENA_dly_reg = 0; reg ENB_dly_reg = 0; reg ENA_dly_reg_D = 0; reg ENB_dly_reg_D = 0; //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //************** // log2int //************** function integer log2int (input integer data_value); integer width; integer cnt; begin width = 0; cnt= data_value; for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin width = width + 1; end //loop log2int = width; end //log2int endfunction //************************************************************************** // FUNCTION : divroundup // Returns the ceiling value of the division // Data_value - the quantity to be divided, dividend // Divisor - the value to divide the data_value by //************************************************************************** function integer divroundup (input integer data_value,input integer divisor); integer div; begin div = data_value/divisor; if ((data_value % divisor) != 0) begin div = div+1; end //if divroundup = div; end //if endfunction localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; //Data Width Number of LSB address bits to be discarded //1 to 16 1 //17 to 32 2 //33 to 64 3 //65 to 128 4 //129 to 256 5 //257 to 512 6 //513 to 1024 7 // The following two constants determine this. localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); localparam C_AXI_OS_WR = 2; //*********************************************** // INPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage always @* begin injectsbiterr_in = INJECTSBITERR; injectdbiterr_in = INJECTDBITERR; rsta_in = RSTA; ena_in = ENA; regcea_in = REGCEA; wea_in = WEA; addra_in = ADDRA; dina_in = DINA; end //end always end //end no_softecc_input_reg_stage endgenerate generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage always @(posedge CLKA) begin injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; rsta_in <= #FLOP_DELAY RSTA; ena_in <= #FLOP_DELAY ENA; regcea_in <= #FLOP_DELAY REGCEA; wea_in <= #FLOP_DELAY WEA; addra_in <= #FLOP_DELAY ADDRA; dina_in <= #FLOP_DELAY DINA; end //end always end //end input_reg_stages generate statement endgenerate //************************************************************************** // NO SAFETY LOGIC //************************************************************************** generate if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN assign ENA_I_SAFE = ena_in; assign ENB_I_SAFE = ENB; assign RSTA_I_SAFE = rsta_in; assign RSTB_I_SAFE = RSTB; end endgenerate //*************************************************************************** // SAFETY LOGIC // Power-ON Reset Generation //*************************************************************************** generate if (C_EN_SAFETY_CKT == 1) begin always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ; always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0]; always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ; always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; assign RSTA_I_SAFE = rsta_in | POR_A; assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B); end endgenerate //----------------------------------------------------------------------------- // -- RSTA/B_BUSY Generation //----------------------------------------------------------------------------- generate if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D; always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D; always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy; end endgenerate generate if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY always @(*) RSTB_BUSY = 1'b0; end endgenerate generate if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D; always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D; always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy; end endgenerate //----------------------------------------------------------------------------- // -- ENA/ENB Generation //----------------------------------------------------------------------------- generate if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG always @(posedge clka) begin ENA_dly <= #FLOP_DELAY RSTA_I_SAFE; ENA_dly_D <= #FLOP_DELAY ENA_dly; end assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in); end endgenerate generate if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG always @(posedge clka) begin ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE; ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg; end assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in); end endgenerate generate if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB assign ENB_I_SAFE = 1'b0; end endgenerate generate if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG always @(posedge clkb) begin : PROC_ENB_GEN ENB_dly <= #FLOP_DELAY RSTB_I_SAFE; ENB_dly_D <= #FLOP_DELAY ENB_dly; end assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG always @(posedge clkb) begin : PROC_ENB_GEN ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE; ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg; end assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB); end endgenerate generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_ALGORITHM (C_ALGORITHM), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (CLKA), .RSTA (RSTA_I_SAFE),//(rsta_in), .ENA (ENA_I_SAFE),//(ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB_I_SAFE),//(RSTB), .ENB (ENB_I_SAFE),//(ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (RDADDRECC) ); end endgenerate generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; // Data Width Number of LSB address bits to be discarded // 1 to 16 1 // 17 to 32 2 // 33 to 64 3 // 65 to 128 4 // 129 to 256 5 // 257 to 512 6 // 513 to 1024 7 // The following two constants determine this. localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; assign msb_zero_i = 0; assign lsb_zero_i = 0; assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (CLKA), .RSTA (RSTA_I_SAFE),//(rsta_in), .ENA (ENA_I_SAFE),//(ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB_I_SAFE),//(RSTB), .ENB (ENB_I_SAFE),//(ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (rdaddrecc_i) ); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RLAST = s_axi_rlast_c; assign S_AXI_RVALID = s_axi_rvalid_c; assign S_AXI_RID = s_axi_rid_c; assign S_AXI_RRESP = s_axi_rresp_c; assign s_axi_rready_c = S_AXI_RREADY; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb assign regceb_c = REGCEB; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd blk_mem_axi_regs_fwd_v8_3 #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) axi_regs_inst ( .ACLK (S_ACLK), .ARESET (s_aresetn_a_c), .S_VALID (s_axi_rvalid_c), .S_READY (s_axi_rready_c), .S_PAYLOAD_DATA (s_axi_payload_c), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY), .M_PAYLOAD_DATA (m_axi_payload_c) ); end endgenerate generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module assign s_aresetn_a_c = !S_ARESETN; assign S_AXI_BRESP = 2'b00; assign s_axi_rresp_c = 2'b00; assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; blk_mem_axi_write_wrapper_beh_v8_3 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), .C_AXI_OS_WR (C_AXI_OS_WR)) axi_wr_fsm ( // AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), // AXI Full/Lite Slave Write interface .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_AWLEN (S_AXI_AWLEN), .S_AXI_AWID (S_AXI_AWID), .S_AXI_AWSIZE (S_AXI_AWSIZE), .S_AXI_AWBURST (S_AXI_AWBURST), .S_AXI_AWVALID (S_AXI_AWVALID), .S_AXI_AWREADY (S_AXI_AWREADY), .S_AXI_WVALID (S_AXI_WVALID), .S_AXI_WREADY (S_AXI_WREADY), .S_AXI_BVALID (S_AXI_BVALID), .S_AXI_BREADY (S_AXI_BREADY), .S_AXI_BID (S_AXI_BID), // Signals for BRAM interfac( .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), .S_AXI_WR_EN (s_axi_wr_en_c) ); blk_mem_axi_read_wrapper_beh_v8_3 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_PIPELINE_STAGES (1), .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_rd_sm( //AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), //AXI Full/Lite Read Side .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_ARLEN (s_axi_arlen_c), .S_AXI_ARSIZE (S_AXI_ARSIZE), .S_AXI_ARBURST (S_AXI_ARBURST), .S_AXI_ARVALID (S_AXI_ARVALID), .S_AXI_ARREADY (S_AXI_ARREADY), .S_AXI_RLAST (s_axi_rlast_c), .S_AXI_RVALID (s_axi_rvalid_c), .S_AXI_RREADY (s_axi_rready_c), .S_AXI_ARID (S_AXI_ARID), .S_AXI_RID (s_axi_rid_c), //AXI Full/Lite Read FSM Outputs .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), .S_AXI_RD_EN (s_axi_rd_en_c) ); blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (1), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (1), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (1), .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_BYTE_WEB (1), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (0), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (0), .C_HAS_MUX_OUTPUT_REGS_B (0), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (0), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (S_ACLK), .RSTA (s_aresetn_a_c), .ENA (s_axi_wr_en_c), .REGCEA (regcea_in), .WEA (S_AXI_WSTRB), .ADDRA (s_axi_awaddr_out_c), .DINA (S_AXI_WDATA), .DOUTA (DOUTA), .CLKB (S_ACLK), .RSTB (s_aresetn_a_c), .ENB (s_axi_rd_en_c), .REGCEB (regceb_c), .WEB (WEB_parameterized), .ADDRB (s_axi_araddr_out_c), .DINB (DINB), .DOUTB (s_axi_rdata_c), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .SBITERR (SBITERR), .DBITERR (DBITERR), .ECCPIPECE (1'b0), .SLEEP (1'b0), .RDADDRECC (RDADDRECC) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v ================================================ /* ******************************************************************************* * * FIFO Generator - Verilog Behavioral Model * ******************************************************************************* * * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. * * This file contains confidential and proprietary information * of Xilinx, Inc. and is protected under U.S. and * international copyright and other intellectual property * laws. * * DISCLAIMER * This disclaimer is not a license and does not grant any * rights to the materials distributed herewith. Except as * otherwise provided in a valid license issued to you by * Xilinx, and to the maximum extent permitted by applicable * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * (2) Xilinx shall not be liable (whether in contract or tort, * including negligence, or under any other theory of * liability) for any loss or damage of any kind or nature * related to, arising under or in connection with these * materials, including for any direct, or any indirect, * special, incidental, or consequential loss or damage * (including loss of data, profits, goodwill, or any type of * loss or damage suffered as a result of any action brought * by a third party) even if such damage or loss was * reasonably foreseeable or Xilinx had been advised of the * possibility of the same. * * CRITICAL APPLICATIONS * Xilinx products are not designed or intended to be fail- * safe, or for use in any application requiring fail-safe * performance, such as life-support or safety devices or * systems, Class III medical devices, nuclear facilities, * applications related to the deployment of airbags, or any * other applications that could lead to death, personal * injury, or severe property or environmental damage * (individually and collectively, "Critical * Applications"). Customer assumes the sole risk and * liability of any use of Xilinx products in Critical * Applications, subject only to applicable laws and * regulations governing limitations on product liability. * * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * PART OF THIS FILE AT ALL TIMES. * ******************************************************************************* ******************************************************************************* * * Filename: fifo_generator_vlog_beh.v * * Author : Xilinx * ******************************************************************************* * Structure: * * fifo_generator_vlog_beh.v * | * +-fifo_generator_v13_1_2_bhv_ver_as * | * +-fifo_generator_v13_1_2_bhv_ver_ss * | * +-fifo_generator_v13_1_2_bhv_ver_preload0 * ******************************************************************************* * Description: * * The Verilog behavioral model for the FIFO Generator. * * The behavioral model has three parts: * - The behavioral model for independent clocks FIFOs (_as) * - The behavioral model for common clock FIFOs (_ss) * - The "preload logic" block which implements First-word Fall-through * ******************************************************************************* * Description: * The verilog behavioral model for the FIFO generator core. * ******************************************************************************* */ `timescale 1ps/1ps `ifndef TCQ `define TCQ 100 `endif /******************************************************************************* * Declaration of top-level module ******************************************************************************/ module fifo_generator_vlog_beh #( //----------------------------------------------------------------------- // Generic Declarations //----------------------------------------------------------------------- parameter C_COMMON_CLOCK = 0, parameter C_COUNT_TYPE = 0, parameter C_DATA_COUNT_WIDTH = 2, parameter C_DEFAULT_VALUE = "", parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_ENABLE_RLOCS = 0, parameter C_FAMILY = "", parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_BACKUP = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_INT_CLK = 0, parameter C_HAS_MEMINIT_FILE = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RD_RST = 0, parameter C_HAS_RST = 1, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_HAS_WR_RST = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_INIT_WR_PNTR_VAL = 0, parameter C_MEMORY_TYPE = 1, parameter C_MIF_FILE_NAME = "", parameter C_OPTIMIZATION_MODE = 0, parameter C_OVERFLOW_LOW = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PRIM_FIFO_TYPE = "4kx4", parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_FREQ = 1, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_USE_PIPELINE_REG = 0, parameter C_POWER_SAVING_MODE = 0, parameter C_USE_FIFO16_FLAGS = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_FREQ = 1, parameter C_WR_PNTR_WIDTH = 8, parameter C_WR_RESPONSE_LATENCY = 1, parameter C_MSGON_VAL = 1, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2, // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3 parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3 parameter C_HAS_AXI_WR_CHANNEL = 0, parameter C_HAS_AXI_RD_CHANNEL = 0, parameter C_HAS_SLAVE_CE = 0, parameter C_HAS_MASTER_CE = 0, parameter C_ADD_NGC_CONSTRAINT = 0, parameter C_USE_COMMON_UNDERFLOW = 0, parameter C_USE_COMMON_OVERFLOW = 0, parameter C_USE_DEFAULT_SETTINGS = 0, // AXI Full/Lite parameter C_AXI_ID_WIDTH = 0, parameter C_AXI_ADDR_WIDTH = 0, parameter C_AXI_DATA_WIDTH = 0, parameter C_AXI_LEN_WIDTH = 8, parameter C_AXI_LOCK_WIDTH = 2, parameter C_HAS_AXI_ID = 0, parameter C_HAS_AXI_AWUSER = 0, parameter C_HAS_AXI_WUSER = 0, parameter C_HAS_AXI_BUSER = 0, parameter C_HAS_AXI_ARUSER = 0, parameter C_HAS_AXI_RUSER = 0, parameter C_AXI_ARUSER_WIDTH = 0, parameter C_AXI_AWUSER_WIDTH = 0, parameter C_AXI_WUSER_WIDTH = 0, parameter C_AXI_BUSER_WIDTH = 0, parameter C_AXI_RUSER_WIDTH = 0, // AXI Streaming parameter C_HAS_AXIS_TDATA = 0, parameter C_HAS_AXIS_TID = 0, parameter C_HAS_AXIS_TDEST = 0, parameter C_HAS_AXIS_TUSER = 0, parameter C_HAS_AXIS_TREADY = 0, parameter C_HAS_AXIS_TLAST = 0, parameter C_HAS_AXIS_TSTRB = 0, parameter C_HAS_AXIS_TKEEP = 0, parameter C_AXIS_TDATA_WIDTH = 1, parameter C_AXIS_TID_WIDTH = 1, parameter C_AXIS_TDEST_WIDTH = 1, parameter C_AXIS_TUSER_WIDTH = 1, parameter C_AXIS_TSTRB_WIDTH = 1, parameter C_AXIS_TKEEP_WIDTH = 1, // AXI Channel Type // WACH --> Write Address Channel // WDCH --> Write Data Channel // WRCH --> Write Response Channel // RACH --> Read Address Channel // RDCH --> Read Data Channel // AXIS --> AXI Streaming parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie // AXI Implementation Type // 1 = Common Clock Block RAM FIFO // 2 = Common Clock Distributed RAM FIFO // 11 = Independent Clock Block RAM FIFO // 12 = Independent Clock Distributed RAM FIFO parameter C_IMPLEMENTATION_TYPE_WACH = 0, parameter C_IMPLEMENTATION_TYPE_WDCH = 0, parameter C_IMPLEMENTATION_TYPE_WRCH = 0, parameter C_IMPLEMENTATION_TYPE_RACH = 0, parameter C_IMPLEMENTATION_TYPE_RDCH = 0, parameter C_IMPLEMENTATION_TYPE_AXIS = 0, // AXI FIFO Type // 0 = Data FIFO // 1 = Packet FIFO // 2 = Low Latency Sync FIFO // 3 = Low Latency Async FIFO parameter C_APPLICATION_TYPE_WACH = 0, parameter C_APPLICATION_TYPE_WDCH = 0, parameter C_APPLICATION_TYPE_WRCH = 0, parameter C_APPLICATION_TYPE_RACH = 0, parameter C_APPLICATION_TYPE_RDCH = 0, parameter C_APPLICATION_TYPE_AXIS = 0, // AXI Built-in FIFO Primitive Type // 512x36, 1kx18, 2kx9, 4kx4, etc parameter C_PRIM_FIFO_TYPE_WACH = "512x36", parameter C_PRIM_FIFO_TYPE_WDCH = "512x36", parameter C_PRIM_FIFO_TYPE_WRCH = "512x36", parameter C_PRIM_FIFO_TYPE_RACH = "512x36", parameter C_PRIM_FIFO_TYPE_RDCH = "512x36", parameter C_PRIM_FIFO_TYPE_AXIS = "512x36", // Enable ECC // 0 = ECC disabled // 1 = ECC enabled parameter C_USE_ECC_WACH = 0, parameter C_USE_ECC_WDCH = 0, parameter C_USE_ECC_WRCH = 0, parameter C_USE_ECC_RACH = 0, parameter C_USE_ECC_RDCH = 0, parameter C_USE_ECC_AXIS = 0, // ECC Error Injection Type // 0 = No Error Injection // 1 = Single Bit Error Injection // 2 = Double Bit Error Injection // 3 = Single Bit and Double Bit Error Injection parameter C_ERROR_INJECTION_TYPE_WACH = 0, parameter C_ERROR_INJECTION_TYPE_WDCH = 0, parameter C_ERROR_INJECTION_TYPE_WRCH = 0, parameter C_ERROR_INJECTION_TYPE_RACH = 0, parameter C_ERROR_INJECTION_TYPE_RDCH = 0, parameter C_ERROR_INJECTION_TYPE_AXIS = 0, // Input Data Width // Accumulation of all AXI input signal's width parameter C_DIN_WIDTH_WACH = 1, parameter C_DIN_WIDTH_WDCH = 1, parameter C_DIN_WIDTH_WRCH = 1, parameter C_DIN_WIDTH_RACH = 1, parameter C_DIN_WIDTH_RDCH = 1, parameter C_DIN_WIDTH_AXIS = 1, parameter C_WR_DEPTH_WACH = 16, parameter C_WR_DEPTH_WDCH = 16, parameter C_WR_DEPTH_WRCH = 16, parameter C_WR_DEPTH_RACH = 16, parameter C_WR_DEPTH_RDCH = 16, parameter C_WR_DEPTH_AXIS = 16, parameter C_WR_PNTR_WIDTH_WACH = 4, parameter C_WR_PNTR_WIDTH_WDCH = 4, parameter C_WR_PNTR_WIDTH_WRCH = 4, parameter C_WR_PNTR_WIDTH_RACH = 4, parameter C_WR_PNTR_WIDTH_RDCH = 4, parameter C_WR_PNTR_WIDTH_AXIS = 4, parameter C_HAS_DATA_COUNTS_WACH = 0, parameter C_HAS_DATA_COUNTS_WDCH = 0, parameter C_HAS_DATA_COUNTS_WRCH = 0, parameter C_HAS_DATA_COUNTS_RACH = 0, parameter C_HAS_DATA_COUNTS_RDCH = 0, parameter C_HAS_DATA_COUNTS_AXIS = 0, parameter C_HAS_PROG_FLAGS_WACH = 0, parameter C_HAS_PROG_FLAGS_WDCH = 0, parameter C_HAS_PROG_FLAGS_WRCH = 0, parameter C_HAS_PROG_FLAGS_RACH = 0, parameter C_HAS_PROG_FLAGS_RDCH = 0, parameter C_HAS_PROG_FLAGS_AXIS = 0, parameter C_PROG_FULL_TYPE_WACH = 0, parameter C_PROG_FULL_TYPE_WDCH = 0, parameter C_PROG_FULL_TYPE_WRCH = 0, parameter C_PROG_FULL_TYPE_RACH = 0, parameter C_PROG_FULL_TYPE_RDCH = 0, parameter C_PROG_FULL_TYPE_AXIS = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0, parameter C_PROG_EMPTY_TYPE_WACH = 0, parameter C_PROG_EMPTY_TYPE_WDCH = 0, parameter C_PROG_EMPTY_TYPE_WRCH = 0, parameter C_PROG_EMPTY_TYPE_RACH = 0, parameter C_PROG_EMPTY_TYPE_RDCH = 0, parameter C_PROG_EMPTY_TYPE_AXIS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0, parameter C_REG_SLICE_MODE_WACH = 0, parameter C_REG_SLICE_MODE_WDCH = 0, parameter C_REG_SLICE_MODE_WRCH = 0, parameter C_REG_SLICE_MODE_RACH = 0, parameter C_REG_SLICE_MODE_RDCH = 0, parameter C_REG_SLICE_MODE_AXIS = 0 ) ( //------------------------------------------------------------------------------ // Input and Output Declarations //------------------------------------------------------------------------------ // Conventional FIFO Interface Signals input backup, input backup_marker, input clk, input rst, input srst, input wr_clk, input wr_rst, input rd_clk, input rd_rst, input [C_DIN_WIDTH-1:0] din, input wr_en, input rd_en, // Optional inputs input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh, input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert, input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate, input int_clk, input injectdbiterr, input injectsbiterr, input sleep, output [C_DOUT_WIDTH-1:0] dout, output full, output almost_full, output wr_ack, output overflow, output empty, output almost_empty, output valid, output underflow, output [C_DATA_COUNT_WIDTH-1:0] data_count, output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count, output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count, output prog_full, output prog_empty, output sbiterr, output dbiterr, output wr_rst_busy, output rd_rst_busy, // AXI Global Signal input m_aclk, input s_aclk, input s_aresetn, input s_aclk_en, input m_aclk_en, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen, input [3-1:0] s_axi_awsize, input [2-1:0] s_axi_awburst, input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock, input [4-1:0] s_axi_awcache, input [3-1:0] s_axi_awprot, input [4-1:0] s_axi_awqos, input [4-1:0] s_axi_awregion, input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input s_axi_awvalid, output s_axi_awready, input [C_AXI_ID_WIDTH-1:0] s_axi_wid, input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input s_axi_wlast, input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [2-1:0] s_axi_bresp, output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, output s_axi_bvalid, input s_axi_bready, // AXI Full/Lite Master Write Channel (read side) output [C_AXI_ID_WIDTH-1:0] m_axi_awid, output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen, output [3-1:0] m_axi_awsize, output [2-1:0] m_axi_awburst, output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock, output [4-1:0] m_axi_awcache, output [3-1:0] m_axi_awprot, output [4-1:0] m_axi_awqos, output [4-1:0] m_axi_awregion, output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output m_axi_awvalid, input m_axi_awready, output [C_AXI_ID_WIDTH-1:0] m_axi_wid, output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output m_axi_wlast, output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output m_axi_wvalid, input m_axi_wready, input [C_AXI_ID_WIDTH-1:0] m_axi_bid, input [2-1:0] m_axi_bresp, input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, input m_axi_bvalid, output m_axi_bready, // AXI Full/Lite Slave Read Channel (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen, input [3-1:0] s_axi_arsize, input [2-1:0] s_axi_arburst, input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock, input [4-1:0] s_axi_arcache, input [3-1:0] s_axi_arprot, input [4-1:0] s_axi_arqos, input [4-1:0] s_axi_arregion, input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output [2-1:0] s_axi_rresp, output s_axi_rlast, output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output s_axi_rvalid, input s_axi_rready, // AXI Full/Lite Master Read Channel (read side) output [C_AXI_ID_WIDTH-1:0] m_axi_arid, output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen, output [3-1:0] m_axi_arsize, output [2-1:0] m_axi_arburst, output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock, output [4-1:0] m_axi_arcache, output [3-1:0] m_axi_arprot, output [4-1:0] m_axi_arqos, output [4-1:0] m_axi_arregion, output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output m_axi_arvalid, input m_axi_arready, input [C_AXI_ID_WIDTH-1:0] m_axi_rid, input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input [2-1:0] m_axi_rresp, input m_axi_rlast, input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input m_axi_rvalid, output m_axi_rready, // AXI Streaming Slave Signals (Write side) input s_axis_tvalid, output s_axis_tready, input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb, input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep, input s_axis_tlast, input [C_AXIS_TID_WIDTH-1:0] s_axis_tid, input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, // AXI Streaming Master Signals (Read side) output m_axis_tvalid, input m_axis_tready, output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb, output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep, output m_axis_tlast, output [C_AXIS_TID_WIDTH-1:0] m_axis_tid, output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, // AXI Full/Lite Write Address Channel signals input axi_aw_injectsbiterr, input axi_aw_injectdbiterr, input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh, input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count, output axi_aw_sbiterr, output axi_aw_dbiterr, output axi_aw_overflow, output axi_aw_underflow, output axi_aw_prog_full, output axi_aw_prog_empty, // AXI Full/Lite Write Data Channel signals input axi_w_injectsbiterr, input axi_w_injectdbiterr, input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh, input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count, output axi_w_sbiterr, output axi_w_dbiterr, output axi_w_overflow, output axi_w_underflow, output axi_w_prog_full, output axi_w_prog_empty, // AXI Full/Lite Write Response Channel signals input axi_b_injectsbiterr, input axi_b_injectdbiterr, input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh, input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count, output axi_b_sbiterr, output axi_b_dbiterr, output axi_b_overflow, output axi_b_underflow, output axi_b_prog_full, output axi_b_prog_empty, // AXI Full/Lite Read Address Channel signals input axi_ar_injectsbiterr, input axi_ar_injectdbiterr, input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh, input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count, output axi_ar_sbiterr, output axi_ar_dbiterr, output axi_ar_overflow, output axi_ar_underflow, output axi_ar_prog_full, output axi_ar_prog_empty, // AXI Full/Lite Read Data Channel Signals input axi_r_injectsbiterr, input axi_r_injectdbiterr, input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh, input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count, output axi_r_sbiterr, output axi_r_dbiterr, output axi_r_overflow, output axi_r_underflow, output axi_r_prog_full, output axi_r_prog_empty, // AXI Streaming FIFO Related Signals input axis_injectsbiterr, input axis_injectdbiterr, input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh, input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh, output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count, output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count, output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count, output axis_sbiterr, output axis_dbiterr, output axis_overflow, output axis_underflow, output axis_prog_full, output axis_prog_empty ); wire BACKUP; wire BACKUP_MARKER; wire CLK; wire RST; wire SRST; wire WR_CLK; wire WR_RST; wire RD_CLK; wire RD_RST; wire [C_DIN_WIDTH-1:0] DIN; wire WR_EN; wire RD_EN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire INT_CLK; wire INJECTDBITERR; wire INJECTSBITERR; wire SLEEP; wire [C_DOUT_WIDTH-1:0] DOUT; wire FULL; wire ALMOST_FULL; wire WR_ACK; wire OVERFLOW; wire EMPTY; wire ALMOST_EMPTY; wire VALID; wire UNDERFLOW; wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; wire PROG_FULL; wire PROG_EMPTY; wire SBITERR; wire DBITERR; wire WR_RST_BUSY; wire RD_RST_BUSY; wire M_ACLK; wire S_ACLK; wire S_ARESETN; wire S_ACLK_EN; wire M_ACLK_EN; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID; wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR; wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN; wire [3-1:0] S_AXI_AWSIZE; wire [2-1:0] S_AXI_AWBURST; wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK; wire [4-1:0] S_AXI_AWCACHE; wire [3-1:0] S_AXI_AWPROT; wire [4-1:0] S_AXI_AWQOS; wire [4-1:0] S_AXI_AWREGION; wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER; wire S_AXI_AWVALID; wire S_AXI_AWREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA; wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB; wire S_AXI_WLAST; wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER; wire S_AXI_WVALID; wire S_AXI_WREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [2-1:0] S_AXI_BRESP; wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER; wire S_AXI_BVALID; wire S_AXI_BREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID; wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR; wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN; wire [3-1:0] M_AXI_AWSIZE; wire [2-1:0] M_AXI_AWBURST; wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK; wire [4-1:0] M_AXI_AWCACHE; wire [3-1:0] M_AXI_AWPROT; wire [4-1:0] M_AXI_AWQOS; wire [4-1:0] M_AXI_AWREGION; wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER; wire M_AXI_AWVALID; wire M_AXI_AWREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB; wire M_AXI_WLAST; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER; wire M_AXI_WVALID; wire M_AXI_WREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID; wire [2-1:0] M_AXI_BRESP; wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER; wire M_AXI_BVALID; wire M_AXI_BREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID; wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN; wire [3-1:0] S_AXI_ARSIZE; wire [2-1:0] S_AXI_ARBURST; wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK; wire [4-1:0] S_AXI_ARCACHE; wire [3-1:0] S_AXI_ARPROT; wire [4-1:0] S_AXI_ARQOS; wire [4-1:0] S_AXI_ARREGION; wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER; wire S_AXI_ARVALID; wire S_AXI_ARREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; wire [2-1:0] S_AXI_RRESP; wire S_AXI_RLAST; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER; wire S_AXI_RVALID; wire S_AXI_RREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN; wire [3-1:0] M_AXI_ARSIZE; wire [2-1:0] M_AXI_ARBURST; wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK; wire [4-1:0] M_AXI_ARCACHE; wire [3-1:0] M_AXI_ARPROT; wire [4-1:0] M_AXI_ARQOS; wire [4-1:0] M_AXI_ARREGION; wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER; wire M_AXI_ARVALID; wire M_AXI_ARREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; wire [2-1:0] M_AXI_RRESP; wire M_AXI_RLAST; wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER; wire M_AXI_RVALID; wire M_AXI_RREADY; wire S_AXIS_TVALID; wire S_AXIS_TREADY; wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA; wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB; wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP; wire S_AXIS_TLAST; wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID; wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST; wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER; wire M_AXIS_TVALID; wire M_AXIS_TREADY; wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA; wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB; wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP; wire M_AXIS_TLAST; wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID; wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST; wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER; wire AXI_AW_INJECTSBITERR; wire AXI_AW_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT; wire AXI_AW_SBITERR; wire AXI_AW_DBITERR; wire AXI_AW_OVERFLOW; wire AXI_AW_UNDERFLOW; wire AXI_AW_PROG_FULL; wire AXI_AW_PROG_EMPTY; wire AXI_W_INJECTSBITERR; wire AXI_W_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT; wire AXI_W_SBITERR; wire AXI_W_DBITERR; wire AXI_W_OVERFLOW; wire AXI_W_UNDERFLOW; wire AXI_W_PROG_FULL; wire AXI_W_PROG_EMPTY; wire AXI_B_INJECTSBITERR; wire AXI_B_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT; wire AXI_B_SBITERR; wire AXI_B_DBITERR; wire AXI_B_OVERFLOW; wire AXI_B_UNDERFLOW; wire AXI_B_PROG_FULL; wire AXI_B_PROG_EMPTY; wire AXI_AR_INJECTSBITERR; wire AXI_AR_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT; wire AXI_AR_SBITERR; wire AXI_AR_DBITERR; wire AXI_AR_OVERFLOW; wire AXI_AR_UNDERFLOW; wire AXI_AR_PROG_FULL; wire AXI_AR_PROG_EMPTY; wire AXI_R_INJECTSBITERR; wire AXI_R_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT; wire AXI_R_SBITERR; wire AXI_R_DBITERR; wire AXI_R_OVERFLOW; wire AXI_R_UNDERFLOW; wire AXI_R_PROG_FULL; wire AXI_R_PROG_EMPTY; wire AXIS_INJECTSBITERR; wire AXIS_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT; wire AXIS_SBITERR; wire AXIS_DBITERR; wire AXIS_OVERFLOW; wire AXIS_UNDERFLOW; wire AXIS_PROG_FULL; wire AXIS_PROG_EMPTY; wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in; wire wr_rst_int; wire rd_rst_int; wire wr_rst_busy_o; wire wr_rst_busy_ntve; wire wr_rst_busy_axis; wire wr_rst_busy_wach; wire wr_rst_busy_wdch; wire wr_rst_busy_wrch; wire wr_rst_busy_rach; wire wr_rst_busy_rdch; function integer find_log2; input integer int_val; integer i,j; begin i = 1; j = 0; for (i = 1; i < int_val; i = i*2) begin j = j + 1; end find_log2 = j; end endfunction // Conventional FIFO Interface Signals assign BACKUP = backup; assign BACKUP_MARKER = backup_marker; assign CLK = clk; assign RST = rst; assign SRST = srst; assign WR_CLK = wr_clk; assign WR_RST = wr_rst; assign RD_CLK = rd_clk; assign RD_RST = rd_rst; assign WR_EN = wr_en; assign RD_EN = rd_en; assign INT_CLK = int_clk; assign INJECTDBITERR = injectdbiterr; assign INJECTSBITERR = injectsbiterr; assign SLEEP = sleep; assign full = FULL; assign almost_full = ALMOST_FULL; assign wr_ack = WR_ACK; assign overflow = OVERFLOW; assign empty = EMPTY; assign almost_empty = ALMOST_EMPTY; assign valid = VALID; assign underflow = UNDERFLOW; assign prog_full = PROG_FULL; assign prog_empty = PROG_EMPTY; assign sbiterr = SBITERR; assign dbiterr = DBITERR; // assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o; assign wr_rst_busy = wr_rst_busy_o; assign rd_rst_busy = RD_RST_BUSY; assign M_ACLK = m_aclk; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_ACLK_EN = s_aclk_en; assign M_ACLK_EN = m_aclk_en; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign m_axi_awvalid = M_AXI_AWVALID; assign M_AXI_AWREADY = m_axi_awready; assign m_axi_wlast = M_AXI_WLAST; assign m_axi_wvalid = M_AXI_WVALID; assign M_AXI_WREADY = m_axi_wready; assign M_AXI_BVALID = m_axi_bvalid; assign m_axi_bready = M_AXI_BREADY; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign m_axi_arvalid = M_AXI_ARVALID; assign M_AXI_ARREADY = m_axi_arready; assign M_AXI_RLAST = m_axi_rlast; assign M_AXI_RVALID = m_axi_rvalid; assign m_axi_rready = M_AXI_RREADY; assign S_AXIS_TVALID = s_axis_tvalid; assign s_axis_tready = S_AXIS_TREADY; assign S_AXIS_TLAST = s_axis_tlast; assign m_axis_tvalid = M_AXIS_TVALID; assign M_AXIS_TREADY = m_axis_tready; assign m_axis_tlast = M_AXIS_TLAST; assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr; assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr; assign axi_aw_sbiterr = AXI_AW_SBITERR; assign axi_aw_dbiterr = AXI_AW_DBITERR; assign axi_aw_overflow = AXI_AW_OVERFLOW; assign axi_aw_underflow = AXI_AW_UNDERFLOW; assign axi_aw_prog_full = AXI_AW_PROG_FULL; assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY; assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr; assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr; assign axi_w_sbiterr = AXI_W_SBITERR; assign axi_w_dbiterr = AXI_W_DBITERR; assign axi_w_overflow = AXI_W_OVERFLOW; assign axi_w_underflow = AXI_W_UNDERFLOW; assign axi_w_prog_full = AXI_W_PROG_FULL; assign axi_w_prog_empty = AXI_W_PROG_EMPTY; assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr; assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr; assign axi_b_sbiterr = AXI_B_SBITERR; assign axi_b_dbiterr = AXI_B_DBITERR; assign axi_b_overflow = AXI_B_OVERFLOW; assign axi_b_underflow = AXI_B_UNDERFLOW; assign axi_b_prog_full = AXI_B_PROG_FULL; assign axi_b_prog_empty = AXI_B_PROG_EMPTY; assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr; assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr; assign axi_ar_sbiterr = AXI_AR_SBITERR; assign axi_ar_dbiterr = AXI_AR_DBITERR; assign axi_ar_overflow = AXI_AR_OVERFLOW; assign axi_ar_underflow = AXI_AR_UNDERFLOW; assign axi_ar_prog_full = AXI_AR_PROG_FULL; assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY; assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr; assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr; assign axi_r_sbiterr = AXI_R_SBITERR; assign axi_r_dbiterr = AXI_R_DBITERR; assign axi_r_overflow = AXI_R_OVERFLOW; assign axi_r_underflow = AXI_R_UNDERFLOW; assign axi_r_prog_full = AXI_R_PROG_FULL; assign axi_r_prog_empty = AXI_R_PROG_EMPTY; assign AXIS_INJECTSBITERR = axis_injectsbiterr; assign AXIS_INJECTDBITERR = axis_injectdbiterr; assign axis_sbiterr = AXIS_SBITERR; assign axis_dbiterr = AXIS_DBITERR; assign axis_overflow = AXIS_OVERFLOW; assign axis_underflow = AXIS_UNDERFLOW; assign axis_prog_full = AXIS_PROG_FULL; assign axis_prog_empty = AXIS_PROG_EMPTY; assign DIN = din; assign PROG_EMPTY_THRESH = prog_empty_thresh; assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert; assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate; assign PROG_FULL_THRESH = prog_full_thresh; assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert; assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate; assign dout = DOUT; assign data_count = DATA_COUNT; assign rd_data_count = RD_DATA_COUNT; assign wr_data_count = WR_DATA_COUNT; assign S_AXI_AWID = s_axi_awid; assign S_AXI_AWADDR = s_axi_awaddr; assign S_AXI_AWLEN = s_axi_awlen; assign S_AXI_AWSIZE = s_axi_awsize; assign S_AXI_AWBURST = s_axi_awburst; assign S_AXI_AWLOCK = s_axi_awlock; assign S_AXI_AWCACHE = s_axi_awcache; assign S_AXI_AWPROT = s_axi_awprot; assign S_AXI_AWQOS = s_axi_awqos; assign S_AXI_AWREGION = s_axi_awregion; assign S_AXI_AWUSER = s_axi_awuser; assign S_AXI_WID = s_axi_wid; assign S_AXI_WDATA = s_axi_wdata; assign S_AXI_WSTRB = s_axi_wstrb; assign S_AXI_WUSER = s_axi_wuser; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_buser = S_AXI_BUSER; assign m_axi_awid = M_AXI_AWID; assign m_axi_awaddr = M_AXI_AWADDR; assign m_axi_awlen = M_AXI_AWLEN; assign m_axi_awsize = M_AXI_AWSIZE; assign m_axi_awburst = M_AXI_AWBURST; assign m_axi_awlock = M_AXI_AWLOCK; assign m_axi_awcache = M_AXI_AWCACHE; assign m_axi_awprot = M_AXI_AWPROT; assign m_axi_awqos = M_AXI_AWQOS; assign m_axi_awregion = M_AXI_AWREGION; assign m_axi_awuser = M_AXI_AWUSER; assign m_axi_wid = M_AXI_WID; assign m_axi_wdata = M_AXI_WDATA; assign m_axi_wstrb = M_AXI_WSTRB; assign m_axi_wuser = M_AXI_WUSER; assign M_AXI_BID = m_axi_bid; assign M_AXI_BRESP = m_axi_bresp; assign M_AXI_BUSER = m_axi_buser; assign S_AXI_ARID = s_axi_arid; assign S_AXI_ARADDR = s_axi_araddr; assign S_AXI_ARLEN = s_axi_arlen; assign S_AXI_ARSIZE = s_axi_arsize; assign S_AXI_ARBURST = s_axi_arburst; assign S_AXI_ARLOCK = s_axi_arlock; assign S_AXI_ARCACHE = s_axi_arcache; assign S_AXI_ARPROT = s_axi_arprot; assign S_AXI_ARQOS = s_axi_arqos; assign S_AXI_ARREGION = s_axi_arregion; assign S_AXI_ARUSER = s_axi_aruser; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_ruser = S_AXI_RUSER; assign m_axi_arid = M_AXI_ARID; assign m_axi_araddr = M_AXI_ARADDR; assign m_axi_arlen = M_AXI_ARLEN; assign m_axi_arsize = M_AXI_ARSIZE; assign m_axi_arburst = M_AXI_ARBURST; assign m_axi_arlock = M_AXI_ARLOCK; assign m_axi_arcache = M_AXI_ARCACHE; assign m_axi_arprot = M_AXI_ARPROT; assign m_axi_arqos = M_AXI_ARQOS; assign m_axi_arregion = M_AXI_ARREGION; assign m_axi_aruser = M_AXI_ARUSER; assign M_AXI_RID = m_axi_rid; assign M_AXI_RDATA = m_axi_rdata; assign M_AXI_RRESP = m_axi_rresp; assign M_AXI_RUSER = m_axi_ruser; assign S_AXIS_TDATA = s_axis_tdata; assign S_AXIS_TSTRB = s_axis_tstrb; assign S_AXIS_TKEEP = s_axis_tkeep; assign S_AXIS_TID = s_axis_tid; assign S_AXIS_TDEST = s_axis_tdest; assign S_AXIS_TUSER = s_axis_tuser; assign m_axis_tdata = M_AXIS_TDATA; assign m_axis_tstrb = M_AXIS_TSTRB; assign m_axis_tkeep = M_AXIS_TKEEP; assign m_axis_tid = M_AXIS_TID; assign m_axis_tdest = M_AXIS_TDEST; assign m_axis_tuser = M_AXIS_TUSER; assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh; assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh; assign axi_aw_data_count = AXI_AW_DATA_COUNT; assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT; assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT; assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh; assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh; assign axi_w_data_count = AXI_W_DATA_COUNT; assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT; assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT; assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh; assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh; assign axi_b_data_count = AXI_B_DATA_COUNT; assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT; assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT; assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh; assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh; assign axi_ar_data_count = AXI_AR_DATA_COUNT; assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT; assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT; assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh; assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh; assign axi_r_data_count = AXI_R_DATA_COUNT; assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT; assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT; assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh; assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh; assign axis_data_count = AXIS_DATA_COUNT; assign axis_wr_data_count = AXIS_WR_DATA_COUNT; assign axis_rd_data_count = AXIS_RD_DATA_COUNT; generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo fifo_generator_v13_1_2_CONV_VER #( .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_FAMILY (C_FAMILY), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RD_RST (C_HAS_RD_RST), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_HAS_WR_RST (C_HAS_WR_RST), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_FREQ (C_RD_FREQ), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_ECC (C_USE_ECC), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_FREQ (C_WR_FREQ), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE) ) fifo_generator_v13_1_2_conv_dut ( .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .CLK (CLK), .RST (RST), .SRST (SRST), .WR_CLK (WR_CLK), .WR_RST (WR_RST), .RD_CLK (RD_CLK), .RD_RST (RD_RST), .DIN (DIN), .WR_EN (WR_EN), .RD_EN (RD_EN), .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), .PROG_FULL_THRESH (PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), .INT_CLK (INT_CLK), .INJECTDBITERR (INJECTDBITERR), .INJECTSBITERR (INJECTSBITERR), .DOUT (DOUT), .FULL (FULL), .ALMOST_FULL (ALMOST_FULL), .WR_ACK (WR_ACK), .OVERFLOW (OVERFLOW), .EMPTY (EMPTY), .ALMOST_EMPTY (ALMOST_EMPTY), .VALID (VALID), .UNDERFLOW (UNDERFLOW), .DATA_COUNT (DATA_COUNT), .RD_DATA_COUNT (RD_DATA_COUNT), .WR_DATA_COUNT (wr_data_count_in), .PROG_FULL (PROG_FULL), .PROG_EMPTY (PROG_EMPTY), .SBITERR (SBITERR), .DBITERR (DBITERR), .wr_rst_busy_o (wr_rst_busy_o), .wr_rst_busy (wr_rst_busy_i), .rd_rst_busy (rd_rst_busy), .wr_rst_i_out (wr_rst_int), .rd_rst_i_out (rd_rst_int) ); end endgenerate localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; localparam C_AXI_SIZE_WIDTH = 3; localparam C_AXI_BURST_WIDTH = 2; localparam C_AXI_CACHE_WIDTH = 4; localparam C_AXI_PROT_WIDTH = 3; localparam C_AXI_QOS_WIDTH = 4; localparam C_AXI_REGION_WIDTH = 4; localparam C_AXI_BRESP_WIDTH = 2; localparam C_AXI_RRESP_WIDTH = 2; localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0; localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS; localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET; localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET; localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET; localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET; localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET; localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); function [LOG_DEPTH_AXIS-1:0] bin2gray; input [LOG_DEPTH_AXIS-1:0] x; begin bin2gray = x ^ (x>>1); end endfunction function [LOG_DEPTH_AXIS-1:0] gray2bin; input [LOG_DEPTH_AXIS-1:0] x; integer i; begin gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1]; for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin gray2bin[i] = gray2bin[i+1] ^ x[i]; end end endfunction wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last; wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ; wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ; reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0; reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0; reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0; reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0; wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad; wire [LOG_WR_DEPTH : 0] r_inv_pad; wire [LOG_WR_DEPTH-1 : 0] d_cnt; reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0; reg adj_w_cnt_rd_pad_0 = 0; reg r_inv_pad_0 = 0; genvar l; generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage fifo_generator_v13_1_2_sync_stage #( .C_WIDTH (LOG_WR_DEPTH) ) rd_stg_inst ( .RST (rd_rst_int), .CLK (RD_CLK), .DIN (w_q[l-1]), .DOUT (w_q[l]) ); end endgenerate // gpkt_cnt_sync_stage generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter assign wr_eop_ad = WR_EN & !(FULL); assign rd_eop_ad = RD_EN & !(EMPTY); always @ (posedge wr_rst_int or posedge WR_CLK) begin if (wr_rst_int) w_cnt <= 1'b0; else if (wr_eop_ad) w_cnt <= w_cnt + 1; end always @ (posedge wr_rst_int or posedge WR_CLK) begin if (wr_rst_int) w_cnt_gc <= 1'b0; else w_cnt_gc <= bin2gray(w_cnt); end assign w_q[0] = w_cnt_gc; assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE]; always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) w_cnt_rd <= 1'b0; else w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last); end always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) r_cnt <= 1'b0; else if (rd_eop_ad) r_cnt <= r_cnt + 1; end // Take the difference of write and read packet count // Logic is similar to rd_pe_as assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd; assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt; assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0; assign r_inv_pad[0] = r_inv_pad_0; always @ ( rd_eop_ad ) begin if (!rd_eop_ad) begin adj_w_cnt_rd_pad_0 <= 1'b1; r_inv_pad_0 <= 1'b1; end else begin adj_w_cnt_rd_pad_0 <= 1'b0; r_inv_pad_0 <= 1'b0; end end always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) d_cnt_pad <= 1'b0; else d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ; end assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ; assign WR_DATA_COUNT = d_cnt; end endgenerate // fifo_ic_adapter generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter assign WR_DATA_COUNT = wr_data_count_in; end endgenerate // fifo_icn_adapter wire inverted_reset = ~S_ARESETN; wire axi_rs_rst; wire [C_DIN_WIDTH_AXIS-1:0] axis_din ; wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ; wire axis_full ; wire axis_almost_full ; wire axis_empty ; wire axis_s_axis_tready; wire axis_m_axis_tvalid; wire axis_wr_en ; wire axis_rd_en ; wire axis_we ; wire axis_re ; wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc; reg axis_pkt_read = 1'b0; wire axis_rd_rst; wire axis_wr_rst; generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 || C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst reg rst_d1 = 0 ; reg rst_d2 = 0 ; reg [3:0] axi_rst = 4'h0 ; always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) begin rst_d1 <= 1'b1; rst_d2 <= 1'b1; axi_rst <= 4'hf; end else begin rst_d1 <= #`TCQ 1'b0; rst_d2 <= #`TCQ rst_d1; axi_rst <= #`TCQ {axi_rst[2:0],1'b0}; end end assign axi_rs_rst = axi_rst[3];//rst_d2; end endgenerate // gaxi_rs_rst generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming // Write protection when almost full or prog_full is high assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID; // Read protection when almost empty or prog_empty is high assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY : (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY; assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we; assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re; fifo_generator_v13_1_2_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 : (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_AXIS), .C_WR_DEPTH (C_WR_DEPTH_AXIS), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), .C_DOUT_WIDTH (C_DIN_WIDTH_AXIS), .C_RD_DEPTH (C_WR_DEPTH_AXIS), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS), .C_USE_ECC (C_USE_ECC_AXIS), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_2_axis_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (axis_wr_en), .RD_EN (axis_rd_en), .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .INJECTDBITERR (AXIS_INJECTDBITERR), .INJECTSBITERR (AXIS_INJECTSBITERR), .DIN (axis_din), .DOUT (axis_dout), .FULL (axis_full), .EMPTY (axis_empty), .ALMOST_FULL (axis_almost_full), .PROG_FULL (AXIS_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXIS_PROG_EMPTY), .WR_ACK (), .OVERFLOW (AXIS_OVERFLOW), .VALID (), .UNDERFLOW (AXIS_UNDERFLOW), .DATA_COUNT (axis_dc), .RD_DATA_COUNT (AXIS_RD_DATA_COUNT), .WR_DATA_COUNT (AXIS_WR_DATA_COUNT), .SBITERR (AXIS_SBITERR), .DBITERR (AXIS_DBITERR), .wr_rst_busy (wr_rst_busy_axis), .rd_rst_busy (rd_rst_busy_axis), .wr_rst_i_out (axis_wr_rst), .rd_rst_i_out (axis_rd_rst), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full; assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read; assign S_AXIS_TREADY = axis_s_axis_tready; assign M_AXIS_TVALID = axis_m_axis_tvalid; end endgenerate // axi_streaming wire axis_wr_eop; reg axis_wr_eop_d1 = 1'b0; wire axis_rd_eop; integer axis_pkt_cnt; generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; assign axis_rd_eop = axis_rd_en & axis_dout[0]; always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_pkt_read <= 1'b0; else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1) axis_pkt_read <= 1'b0; else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty)) axis_pkt_read <= 1'b1; end always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_wr_eop_d1 <= 1'b0; else axis_wr_eop_d1 <= axis_wr_eop; end always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_pkt_cnt <= 0; else if (axis_wr_eop_d1 && ~axis_rd_eop) axis_pkt_cnt <= axis_pkt_cnt + 1; else if (axis_rd_eop && ~axis_wr_eop_d1) axis_pkt_cnt <= axis_pkt_cnt - 1; end end endgenerate // gaxis_pkt_fifo_cc reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0; wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last; wire axis_rd_has_rst; wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ; wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ; wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0; wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ; reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0; reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0; reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0; wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad; wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad; wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt; reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0; reg adj_axis_wpkt_cnt_rd_pad_0 = 0; reg rpkt_inv_pad_0 = 0; wire axis_af_rd ; generate if (C_HAS_RST == 1) begin : rst_blk_has assign axis_rd_has_rst = axis_rd_rst; end endgenerate //rst_blk_has generate if (C_HAS_RST == 0) begin :rst_blk_no assign axis_rd_has_rst = 1'b0; end endgenerate //rst_blk_no genvar i; generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage fifo_generator_v13_1_2_sync_stage #( .C_WIDTH (LOG_DEPTH_AXIS) ) rd_stg_inst ( .RST (axis_rd_has_rst), .CLK (M_ACLK), .DIN (wpkt_q[i-1]), .DOUT (wpkt_q[i]) ); fifo_generator_v13_1_2_sync_stage #( .C_WIDTH (1) ) wr_stg_inst ( .RST (axis_rd_has_rst), .CLK (M_ACLK), .DIN (axis_af_q[i-1]), .DOUT (axis_af_q[i]) ); end endgenerate // gpkt_cnt_sync_stage generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; assign axis_rd_eop = axis_rd_en & axis_dout[0]; always @ (posedge axis_rd_has_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_pkt_read <= 1'b0; else if (axis_rd_eop && (diff_pkt_cnt == 1)) axis_pkt_read <= 1'b0; else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty)) axis_pkt_read <= 1'b1; end always @ (posedge axis_wr_rst or posedge S_ACLK) begin if (axis_wr_rst) axis_wpkt_cnt <= 1'b0; else if (axis_wr_eop) axis_wpkt_cnt <= axis_wpkt_cnt + 1; end always @ (posedge axis_wr_rst or posedge S_ACLK) begin if (axis_wr_rst) axis_wpkt_cnt_gc <= 1'b0; else axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt); end assign wpkt_q[0] = axis_wpkt_cnt_gc; assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE]; assign axis_af_q[0] = axis_almost_full; //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE]; assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE]; always @ (posedge axis_rd_has_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_wpkt_cnt_rd <= 1'b0; else axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last); end always @ (posedge axis_rd_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_rpkt_cnt <= 1'b0; else if (axis_rd_eop) axis_rpkt_cnt <= axis_rpkt_cnt + 1; end // Take the difference of write and read packet count // Logic is similar to rd_pe_as assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd; assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt; assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0; assign rpkt_inv_pad[0] = rpkt_inv_pad_0; always @ ( axis_rd_eop ) begin if (!axis_rd_eop) begin adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1; rpkt_inv_pad_0 <= 1'b1; end else begin adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0; rpkt_inv_pad_0 <= 1'b0; end end always @ (posedge axis_rd_rst or posedge M_ACLK) begin if (axis_rd_has_rst) diff_pkt_cnt_pad <= 1'b0; else diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ; end assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ; end endgenerate // gaxis_pkt_fifo_ic // Generate the accurate data count for axi stream packet fifo configuration reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0; generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_dc_pkt_fifo <= 0; else if (axis_wr_en && (~axis_rd_en)) axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1; else if (~axis_wr_en && axis_rd_en) axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1; end assign AXIS_DATA_COUNT = axis_dc_pkt_fifo; end endgenerate // gdc_pkt generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt assign AXIS_DATA_COUNT = 0; end endgenerate // gndc_pkt generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc assign AXIS_DATA_COUNT = axis_dc; end endgenerate // gdc // Register Slice for Write Address Channel generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID; assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY; fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_AXIS), .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS) ) axis_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (axis_din), .S_VALID (axis_wr_en), .S_READY (S_AXIS_TREADY), // Master side .M_PAYLOAD_DATA (axis_dout), .M_VALID (M_AXIS_TVALID), .M_READY (axis_rd_en) ); end endgenerate // gaxis_reg_slice generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA; assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB; assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP; assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID; assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST; assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER; assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast assign axis_din[0] = S_AXIS_TLAST; assign M_AXIS_TLAST = axis_dout[0]; end endgenerate //########################################################################### // AXI FULL Write Channel (axi_write_channel) //########################################################################### localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0; localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0; localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0; localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0; localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0; localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0; localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0; localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH; localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH; localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET; localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET; localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET; localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET; localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET; localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH; localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH; localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET; localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET; localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH; localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH; localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8; localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET; localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH; localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH; localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET; wire [C_DIN_WIDTH_WACH-1:0] wach_din ; wire [C_DIN_WIDTH_WACH-1:0] wach_dout ; wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ; wire wach_full ; wire wach_almost_full ; wire wach_prog_full ; wire wach_empty ; wire wach_almost_empty ; wire wach_prog_empty ; wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ; wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ; wire wdch_full ; wire wdch_almost_full ; wire wdch_prog_full ; wire wdch_empty ; wire wdch_almost_empty ; wire wdch_prog_empty ; wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ; wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ; wire wrch_full ; wire wrch_almost_full ; wire wrch_prog_full ; wire wrch_empty ; wire wrch_almost_empty ; wire wrch_prog_empty ; wire axi_aw_underflow_i; wire axi_w_underflow_i ; wire axi_b_underflow_i ; wire axi_aw_overflow_i ; wire axi_w_overflow_i ; wire axi_b_overflow_i ; wire axi_wr_underflow_i; wire axi_wr_overflow_i ; wire wach_s_axi_awready; wire wach_m_axi_awvalid; wire wach_wr_en ; wire wach_rd_en ; wire wdch_s_axi_wready ; wire wdch_m_axi_wvalid ; wire wdch_wr_en ; wire wdch_rd_en ; wire wrch_s_axi_bvalid ; wire wrch_m_axi_bready ; wire wrch_wr_en ; wire wrch_rd_en ; wire txn_count_up ; wire txn_count_down ; wire awvalid_en ; wire awvalid_pkt ; wire awready_pkt ; integer wr_pkt_count ; wire wach_we ; wire wach_re ; wire wdch_we ; wire wdch_re ; wire wrch_we ; wire wrch_re ; generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel // Write protection when almost full or prog_full is high assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID; // Read protection when almost empty or prog_empty is high assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? wach_m_axi_awvalid & awready_pkt & awvalid_en : (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? M_AXI_AWREADY && wach_m_axi_awvalid : (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? awready_pkt & awvalid_en : (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? M_AXI_AWREADY : 1'b0; assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we; assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re; fifo_generator_v13_1_2_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WACH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_WR_DEPTH (C_WR_DEPTH_WACH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), .C_DOUT_WIDTH (C_DIN_WIDTH_WACH), .C_RD_DEPTH (C_WR_DEPTH_WACH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH), .C_USE_ECC (C_USE_ECC_WACH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_2_wach_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wach_wr_en), .RD_EN (wach_rd_en), .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .INJECTDBITERR (AXI_AW_INJECTDBITERR), .INJECTSBITERR (AXI_AW_INJECTSBITERR), .DIN (wach_din), .DOUT (wach_dout_pkt), .FULL (wach_full), .EMPTY (wach_empty), .ALMOST_FULL (), .PROG_FULL (AXI_AW_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXI_AW_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_aw_overflow_i), .VALID (), .UNDERFLOW (axi_aw_underflow_i), .DATA_COUNT (AXI_AW_DATA_COUNT), .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT), .SBITERR (AXI_AW_SBITERR), .DBITERR (AXI_AW_DBITERR), .wr_rst_busy (wr_rst_busy_wach), .rd_rst_busy (rd_rst_busy_wach), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full; assign wach_m_axi_awvalid = ~wach_empty; assign S_AXI_AWREADY = wach_s_axi_awready; assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0; assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0; end endgenerate // axi_write_address_channel // Register Slice for Write Address Channel generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WACH), .C_REG_CONFIG (C_REG_SLICE_MODE_WACH) ) wach_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wach_din), .S_VALID (S_AXI_AWVALID), .S_READY (S_AXI_AWREADY), // Master side .M_PAYLOAD_DATA (wach_dout), .M_VALID (M_AXI_AWVALID), .M_READY (M_AXI_AWREADY) ); end endgenerate // gwach_reg_slice generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WACH), .C_REG_CONFIG (1) ) wach_pkt_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (inverted_reset), // Slave side .S_PAYLOAD_DATA (wach_dout_pkt), .S_VALID (awvalid_pkt), .S_READY (awready_pkt), // Master side .M_PAYLOAD_DATA (wach_dout), .M_VALID (M_AXI_AWVALID), .M_READY (M_AXI_AWREADY) ); assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en; assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en; always@(posedge S_ACLK or posedge inverted_reset) begin if(inverted_reset == 1) begin wr_pkt_count <= 0; end else begin if(txn_count_up == 1 && txn_count_down == 0) begin wr_pkt_count <= wr_pkt_count + 1; end else if(txn_count_up == 0 && txn_count_down == 1) begin wr_pkt_count <= wr_pkt_count - 1; end end end //Always end assign awvalid_en = (wr_pkt_count > 0)?1:0; end endgenerate generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr assign awvalid_en = 1; assign wach_dout = wach_dout_pkt; assign M_AXI_AWVALID = wach_m_axi_awvalid; end endgenerate generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel // Write protection when almost full or prog_full is high assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID; // Read protection when almost empty or prog_empty is high assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY; assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we; assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re; fifo_generator_v13_1_2_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WDCH), .C_WR_DEPTH (C_WR_DEPTH_WDCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), .C_DOUT_WIDTH (C_DIN_WIDTH_WDCH), .C_RD_DEPTH (C_WR_DEPTH_WDCH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH), .C_USE_ECC (C_USE_ECC_WDCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_2_wdch_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wdch_wr_en), .RD_EN (wdch_rd_en), .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .INJECTDBITERR (AXI_W_INJECTDBITERR), .INJECTSBITERR (AXI_W_INJECTSBITERR), .DIN (wdch_din), .DOUT (wdch_dout), .FULL (wdch_full), .EMPTY (wdch_empty), .ALMOST_FULL (), .PROG_FULL (AXI_W_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXI_W_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_w_overflow_i), .VALID (), .UNDERFLOW (axi_w_underflow_i), .DATA_COUNT (AXI_W_DATA_COUNT), .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT), .SBITERR (AXI_W_SBITERR), .DBITERR (AXI_W_DBITERR), .wr_rst_busy (wr_rst_busy_wdch), .rd_rst_busy (rd_rst_busy_wdch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full; assign wdch_m_axi_wvalid = ~wdch_empty; assign S_AXI_WREADY = wdch_s_axi_wready; assign M_AXI_WVALID = wdch_m_axi_wvalid; assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0; assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0; end endgenerate // axi_write_data_channel // Register Slice for Write Data Channel generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WDCH), .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH) ) wdch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wdch_din), .S_VALID (S_AXI_WVALID), .S_READY (S_AXI_WREADY), // Master side .M_PAYLOAD_DATA (wdch_dout), .M_VALID (M_AXI_WVALID), .M_READY (M_AXI_WREADY) ); end endgenerate // gwdch_reg_slice generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel // Write protection when almost full or prog_full is high assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID; // Read protection when almost empty or prog_empty is high assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY; assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we; assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re; fifo_generator_v13_1_2_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WRCH), .C_WR_DEPTH (C_WR_DEPTH_WRCH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), .C_DOUT_WIDTH (C_DIN_WIDTH_WRCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_RD_DEPTH (C_WR_DEPTH_WRCH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH), .C_USE_ECC (C_USE_ECC_WRCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_2_wrch_dut ( .CLK (S_ACLK), .WR_CLK (M_ACLK), .RD_CLK (S_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wrch_wr_en), .RD_EN (wrch_rd_en), .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .INJECTDBITERR (AXI_B_INJECTDBITERR), .INJECTSBITERR (AXI_B_INJECTSBITERR), .DIN (wrch_din), .DOUT (wrch_dout), .FULL (wrch_full), .EMPTY (wrch_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_B_PROG_FULL), .PROG_EMPTY (AXI_B_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_b_overflow_i), .VALID (), .UNDERFLOW (axi_b_underflow_i), .DATA_COUNT (AXI_B_DATA_COUNT), .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT), .SBITERR (AXI_B_SBITERR), .DBITERR (AXI_B_DBITERR), .wr_rst_busy (wr_rst_busy_wrch), .rd_rst_busy (rd_rst_busy_wrch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wrch_s_axi_bvalid = ~wrch_empty; assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full; assign S_AXI_BVALID = wrch_s_axi_bvalid; assign M_AXI_BREADY = wrch_m_axi_bready; assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0; assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0; end endgenerate // axi_write_resp_channel // Register Slice for Write Response Channel generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WRCH), .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH) ) wrch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wrch_din), .S_VALID (M_AXI_BVALID), .S_READY (M_AXI_BREADY), // Master side .M_PAYLOAD_DATA (wrch_dout), .M_VALID (S_AXI_BVALID), .M_READY (S_AXI_BREADY) ); end endgenerate // gwrch_reg_slice assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0; assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0; generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR; assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN; assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE; assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST; assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK; assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE; assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT; assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS; end endgenerate // axi_wach_output generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; end endgenerate // axi_awregion generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion assign M_AXI_AWREGION = 0; end endgenerate // naxi_awregion generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; end endgenerate // axi_awuser generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser assign M_AXI_AWUSER = 0; end endgenerate // naxi_awuser generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET]; end endgenerate //axi_awid generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid assign M_AXI_AWID = 0; end endgenerate //naxi_awid generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET]; assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; assign M_AXI_WLAST = wdch_dout[0]; assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA; assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB; assign wdch_din[0] = S_AXI_WLAST; end endgenerate // axi_wdch_output generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET]; end endgenerate generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin assign M_AXI_WID = 0; end endgenerate generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; end endgenerate generate if (C_HAS_AXI_WUSER == 0) begin assign M_AXI_WUSER = 0; end endgenerate generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP; end endgenerate // axi_wrch_output generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET]; end endgenerate // axi_buser generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser assign S_AXI_BUSER = 0; end endgenerate // naxi_buser generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET]; end endgenerate // axi_bid generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid assign S_AXI_BID = 0 ; end endgenerate // naxi_bid generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1 assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT}; assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; end endgenerate // axi_wach_output1 generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1 assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB}; assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET]; assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; end endgenerate // axi_wdch_output1 generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1 assign wrch_din = M_AXI_BRESP; assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; end endgenerate // axi_wrch_output1 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1 assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER; end endgenerate // gwach_din1 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2 assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID; end endgenerate // gwach_din2 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3 assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION; end endgenerate // gwach_din3 generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1 assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER; end endgenerate // gwdch_din1 generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2 assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID; end endgenerate // gwdch_din2 generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1 assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER; end endgenerate // gwrch_din1 generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2 assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID; end endgenerate // gwrch_din2 //end of axi_write_channel //########################################################################### // AXI FULL Read Channel (axi_read_channel) //########################################################################### wire [C_DIN_WIDTH_RACH-1:0] rach_din ; wire [C_DIN_WIDTH_RACH-1:0] rach_dout ; wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ; wire rach_full ; wire rach_almost_full ; wire rach_prog_full ; wire rach_empty ; wire rach_almost_empty ; wire rach_prog_empty ; wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ; wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ; wire rdch_full ; wire rdch_almost_full ; wire rdch_prog_full ; wire rdch_empty ; wire rdch_almost_empty ; wire rdch_prog_empty ; wire axi_ar_underflow_i ; wire axi_r_underflow_i ; wire axi_ar_overflow_i ; wire axi_r_overflow_i ; wire axi_rd_underflow_i ; wire axi_rd_overflow_i ; wire rach_s_axi_arready ; wire rach_m_axi_arvalid ; wire rach_wr_en ; wire rach_rd_en ; wire rdch_m_axi_rready ; wire rdch_s_axi_rvalid ; wire rdch_wr_en ; wire rdch_rd_en ; wire arvalid_pkt ; wire arready_pkt ; wire arvalid_en ; wire rdch_rd_ok ; wire accept_next_pkt ; integer rdch_free_space ; integer rdch_commited_space ; wire rach_we ; wire rach_re ; wire rdch_we ; wire rdch_re ; localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH; localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH; localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET; localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET; localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET; localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET; localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET; localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH; localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH; localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET; localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET; localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH; localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH; localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH; localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET; generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel // Write protection when almost full or prog_full is high assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID; // Read protection when almost empty or prog_empty is high // assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en; assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? rach_m_axi_arvalid & arready_pkt & arvalid_en : (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? M_AXI_ARREADY && rach_m_axi_arvalid : (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? arready_pkt & arvalid_en : (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? M_AXI_ARREADY : 1'b0; assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we; assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re; fifo_generator_v13_1_2_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_RACH), .C_WR_DEPTH (C_WR_DEPTH_RACH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_DOUT_WIDTH (C_DIN_WIDTH_RACH), .C_RD_DEPTH (C_WR_DEPTH_RACH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH), .C_USE_ECC (C_USE_ECC_RACH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_2_rach_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (rach_wr_en), .RD_EN (rach_rd_en), .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .INJECTDBITERR (AXI_AR_INJECTDBITERR), .INJECTSBITERR (AXI_AR_INJECTSBITERR), .DIN (rach_din), .DOUT (rach_dout_pkt), .FULL (rach_full), .EMPTY (rach_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_AR_PROG_FULL), .PROG_EMPTY (AXI_AR_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_ar_overflow_i), .VALID (), .UNDERFLOW (axi_ar_underflow_i), .DATA_COUNT (AXI_AR_DATA_COUNT), .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT), .SBITERR (AXI_AR_SBITERR), .DBITERR (AXI_AR_DBITERR), .wr_rst_busy (wr_rst_busy_rach), .rd_rst_busy (rd_rst_busy_rach), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full; assign rach_m_axi_arvalid = ~rach_empty; assign S_AXI_ARREADY = rach_s_axi_arready; assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0; assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0; end endgenerate // axi_read_addr_channel // Register Slice for Read Address Channel generate if (C_RACH_TYPE == 1) begin : grach_reg_slice fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RACH), .C_REG_CONFIG (C_REG_SLICE_MODE_RACH) ) rach_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (rach_din), .S_VALID (S_AXI_ARVALID), .S_READY (S_AXI_ARREADY), // Master side .M_PAYLOAD_DATA (rach_dout), .M_VALID (M_AXI_ARVALID), .M_READY (M_AXI_ARREADY) ); end endgenerate // grach_reg_slice // Register Slice for Read Address Channel for MM Packet FIFO generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RACH), .C_REG_CONFIG (1) ) reg_slice_mm_pkt_fifo_inst ( // System Signals .ACLK (S_ACLK), .ARESET (inverted_reset), // Slave side .S_PAYLOAD_DATA (rach_dout_pkt), .S_VALID (arvalid_pkt), .S_READY (arready_pkt), // Master side .M_PAYLOAD_DATA (rach_dout), .M_VALID (M_AXI_ARVALID), .M_READY (M_AXI_ARREADY) ); end endgenerate // grach_reg_slice_mm_pkt_fifo generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid assign M_AXI_ARVALID = rach_m_axi_arvalid; assign rach_dout = rach_dout_pkt; end endgenerate // grach_m_axi_arvalid generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en; assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en; assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en; always@(posedge S_ACLK or posedge inverted_reset) begin if(inverted_reset) begin rdch_commited_space <= 0; end else begin if(rdch_rd_ok && !accept_next_pkt) begin rdch_commited_space <= rdch_commited_space-1; end else if(!rdch_rd_ok && accept_next_pkt) begin rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1); end else if(rdch_rd_ok && accept_next_pkt) begin rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]); end end end //Always end always@(*) begin rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1)); end assign arvalid_en = (rdch_free_space >= 0)?1:0; end endgenerate generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd assign arvalid_en = 1; end endgenerate generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel // Write protection when almost full or prog_full is high assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID; // Read protection when almost empty or prog_empty is high assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY; assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we; assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re; fifo_generator_v13_1_2_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_RDCH), .C_WR_DEPTH (C_WR_DEPTH_RDCH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), .C_DOUT_WIDTH (C_DIN_WIDTH_RDCH), .C_RD_DEPTH (C_WR_DEPTH_RDCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH), .C_USE_ECC (C_USE_ECC_RDCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_2_rdch_dut ( .CLK (S_ACLK), .WR_CLK (M_ACLK), .RD_CLK (S_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (rdch_wr_en), .RD_EN (rdch_rd_en), .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .INJECTDBITERR (AXI_R_INJECTDBITERR), .INJECTSBITERR (AXI_R_INJECTSBITERR), .DIN (rdch_din), .DOUT (rdch_dout), .FULL (rdch_full), .EMPTY (rdch_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_R_PROG_FULL), .PROG_EMPTY (AXI_R_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_r_overflow_i), .VALID (), .UNDERFLOW (axi_r_underflow_i), .DATA_COUNT (AXI_R_DATA_COUNT), .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT), .SBITERR (AXI_R_SBITERR), .DBITERR (AXI_R_DBITERR), .wr_rst_busy (wr_rst_busy_rdch), .rd_rst_busy (rd_rst_busy_rdch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign rdch_s_axi_rvalid = ~rdch_empty; assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full; assign S_AXI_RVALID = rdch_s_axi_rvalid; assign M_AXI_RREADY = rdch_m_axi_rready; assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0; assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0; end endgenerate //axi_read_data_channel // Register Slice for read Data Channel generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice fifo_generator_v13_1_2_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RDCH), .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH) ) rdch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (rdch_din), .S_VALID (M_AXI_RVALID), .S_READY (M_AXI_RREADY), // Master side .M_PAYLOAD_DATA (rdch_dout), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY) ); end endgenerate // grdch_reg_slice assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0; assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0; generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR; assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN; assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE; assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST; assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK; assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE; assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT; assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS; end endgenerate // axi_full_rach_output generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; end endgenerate // axi_arregion generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion assign M_AXI_ARREGION = 0; end endgenerate // naxi_arregion generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; end endgenerate // axi_aruser generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser assign M_AXI_ARUSER = 0; end endgenerate // naxi_aruser generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET]; end endgenerate // axi_arid generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid assign M_AXI_ARID = 0; end endgenerate // naxi_arid generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET]; assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; assign S_AXI_RLAST = rdch_dout[0]; assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA; assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP; assign rdch_din[0] = M_AXI_RLAST; end endgenerate // axi_full_rdch_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET]; end endgenerate // axi_full_ruser_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output assign S_AXI_RUSER = 0; end endgenerate // axi_full_nruser_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET]; end endgenerate // axi_rid generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid assign S_AXI_RID = 0; end endgenerate // naxi_rid generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1 assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT}; assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET]; assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET]; end endgenerate // axi_lite_rach_output generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1 assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP}; assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET]; assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; end endgenerate // axi_lite_rdch_output generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1 assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER; end endgenerate // grach_din1 generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2 assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID; end endgenerate // grach_din2 generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION; end endgenerate generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1 assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER; end endgenerate // grdch_din1 generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2 assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID; end endgenerate // grdch_din2 //end of axi_read_channel generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) : (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i : (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0; end endgenerate // gaxi_comm_uf generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) : (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i : (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0; end endgenerate // gaxi_comm_of //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- // Pass Through Logic or Wiring Logic //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- // Pass Through Logic for Read Channel //------------------------------------------------------------------------- // Wiring logic for Write Address Channel generate if (C_WACH_TYPE == 2) begin : gwach_pass_through assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWQOS = S_AXI_AWQOS; assign M_AXI_AWREGION = S_AXI_AWREGION; assign M_AXI_AWUSER = S_AXI_AWUSER; assign S_AXI_AWREADY = M_AXI_AWREADY; assign M_AXI_AWVALID = S_AXI_AWVALID; end endgenerate // gwach_pass_through; // Wiring logic for Write Data Channel generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through assign M_AXI_WID = S_AXI_WID; assign M_AXI_WDATA = S_AXI_WDATA; assign M_AXI_WSTRB = S_AXI_WSTRB; assign M_AXI_WLAST = S_AXI_WLAST; assign M_AXI_WUSER = S_AXI_WUSER; assign S_AXI_WREADY = M_AXI_WREADY; assign M_AXI_WVALID = S_AXI_WVALID; end endgenerate // gwdch_pass_through; // Wiring logic for Write Response Channel generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through assign S_AXI_BID = M_AXI_BID; assign S_AXI_BRESP = M_AXI_BRESP; assign S_AXI_BUSER = M_AXI_BUSER; assign M_AXI_BREADY = S_AXI_BREADY; assign S_AXI_BVALID = M_AXI_BVALID; end endgenerate // gwrch_pass_through; //------------------------------------------------------------------------- // Pass Through Logic for Read Channel //------------------------------------------------------------------------- // Wiring logic for Read Address Channel generate if (C_RACH_TYPE == 2) begin : grach_pass_through assign M_AXI_ARID = S_AXI_ARID; assign M_AXI_ARADDR = S_AXI_ARADDR; assign M_AXI_ARLEN = S_AXI_ARLEN; assign M_AXI_ARSIZE = S_AXI_ARSIZE; assign M_AXI_ARBURST = S_AXI_ARBURST; assign M_AXI_ARLOCK = S_AXI_ARLOCK; assign M_AXI_ARCACHE = S_AXI_ARCACHE; assign M_AXI_ARPROT = S_AXI_ARPROT; assign M_AXI_ARQOS = S_AXI_ARQOS; assign M_AXI_ARREGION = S_AXI_ARREGION; assign M_AXI_ARUSER = S_AXI_ARUSER; assign S_AXI_ARREADY = M_AXI_ARREADY; assign M_AXI_ARVALID = S_AXI_ARVALID; end endgenerate // grach_pass_through; // Wiring logic for Read Data Channel generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through assign S_AXI_RID = M_AXI_RID; assign S_AXI_RLAST = M_AXI_RLAST; assign S_AXI_RUSER = M_AXI_RUSER; assign S_AXI_RDATA = M_AXI_RDATA; assign S_AXI_RRESP = M_AXI_RRESP; assign S_AXI_RVALID = M_AXI_RVALID; assign M_AXI_RREADY = S_AXI_RREADY; end endgenerate // grdch_pass_through; // Wiring logic for AXI Streaming generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through assign M_AXIS_TDATA = S_AXIS_TDATA; assign M_AXIS_TSTRB = S_AXIS_TSTRB; assign M_AXIS_TKEEP = S_AXIS_TKEEP; assign M_AXIS_TID = S_AXIS_TID; assign M_AXIS_TDEST = S_AXIS_TDEST; assign M_AXIS_TUSER = S_AXIS_TUSER; assign M_AXIS_TLAST = S_AXIS_TLAST; assign S_AXIS_TREADY = M_AXIS_TREADY; assign M_AXIS_TVALID = S_AXIS_TVALID; end endgenerate // gaxis_pass_through; endmodule //fifo_generator_v13_1_2 /******************************************************************************* * Declaration of top-level module for Conventional FIFO ******************************************************************************/ module fifo_generator_v13_1_2_CONV_VER #( parameter C_COMMON_CLOCK = 0, parameter C_INTERFACE_TYPE = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_COUNT_TYPE = 0, parameter C_DATA_COUNT_WIDTH = 2, parameter C_DEFAULT_VALUE = "", parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_ENABLE_RLOCS = 0, parameter C_FAMILY = "virtex7", //Not allowed in Verilog model parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_BACKUP = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_INT_CLK = 0, parameter C_HAS_MEMINIT_FILE = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RD_RST = 0, parameter C_HAS_RST = 0, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_HAS_WR_RST = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_INIT_WR_PNTR_VAL = 0, parameter C_MEMORY_TYPE = 1, parameter C_MIF_FILE_NAME = "", parameter C_OPTIMIZATION_MODE = 0, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PRIM_FIFO_TYPE = "", parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_FREQ = 1, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_USE_FIFO16_FLAGS = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_FREQ = 1, parameter C_WR_PNTR_WIDTH = 8, parameter C_WR_RESPONSE_LATENCY = 1, parameter C_MSGON_VAL = 1, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_FIFO_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2, parameter C_AXI_TYPE = 0 ) ( input BACKUP, input BACKUP_MARKER, input CLK, input RST, input SRST, input WR_CLK, input WR_RST, input RD_CLK, input RD_RST, input [C_DIN_WIDTH-1:0] DIN, input WR_EN, input RD_EN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input INT_CLK, input INJECTDBITERR, input INJECTSBITERR, output [C_DOUT_WIDTH-1:0] DOUT, output FULL, output ALMOST_FULL, output WR_ACK, output OVERFLOW, output EMPTY, output ALMOST_EMPTY, output VALID, output UNDERFLOW, output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output PROG_FULL, output PROG_EMPTY, output SBITERR, output DBITERR, output wr_rst_busy_o, output wr_rst_busy, output rd_rst_busy, output wr_rst_i_out, output rd_rst_i_out ); /* ****************************************************************************** * Definition of Parameters ****************************************************************************** * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) * C_COUNT_TYPE : *not used * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus * C_DEFAULT_VALUE : *not used * C_DIN_WIDTH : Width of DIN bus * C_DOUT_RST_VAL : Reset value of DOUT * C_DOUT_WIDTH : Width of DOUT bus * C_ENABLE_RLOCS : *not used * C_FAMILY : not used in bhv model * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag * C_HAS_BACKUP : *not used * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus * C_HAS_INT_CLK : not used in bhv model * C_HAS_MEMINIT_FILE : *not used * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus * C_HAS_RD_RST : *not used * C_HAS_RST : 1=Core has Async Rst * C_HAS_SRST : 1=Core has Sync Rst * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag * C_HAS_VALID : 1=Core has VALID flag * C_HAS_WR_ACK : 1=Core has WR_ACK flag * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus * C_HAS_WR_RST : *not used * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram * 1=Common-Clock ShiftRam * 2=Indep. Clocks Bram/Dram * 3=Virtex-4 Built-in * 4=Virtex-5 Built-in * C_INIT_WR_PNTR_VAL : *not used * C_MEMORY_TYPE : 1=Block RAM * 2=Distributed RAM * 3=Shift RAM * 4=Built-in FIFO * C_MIF_FILE_NAME : *not used * C_OPTIMIZATION_MODE : *not used * C_OVERFLOW_LOW : 1=OVERFLOW active low * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 * C_PRELOAD_REGS : 1=Use output registers * C_PRIM_FIFO_TYPE : not used in bhv model * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold * C_PROG_EMPTY_TYPE : 0=No programmable empty * 1=Single prog empty thresh constant * 2=Multiple prog empty thresh constants * 3=Single prog empty thresh input * 4=Multiple prog empty thresh inputs * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold * C_PROG_FULL_TYPE : 0=No prog full * 1=Single prog full thresh constant * 2=Multiple prog full thresh constants * 3=Single prog full thresh input * 4=Multiple prog full thresh inputs * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus * C_RD_DEPTH : Depth of read interface (2^N) * C_RD_FREQ : not used in bhv model * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) * C_UNDERFLOW_LOW : 1=UNDERFLOW active low * C_USE_DOUT_RST : 1=Resets DOUT on RST * C_USE_ECC : Used for error injection purpose * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register * C_USE_FIFO16_FLAGS : not used in bhv model * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count * C_VALID_LOW : 1=VALID active low * C_WR_ACK_LOW : 1=WR_ACK active low * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus * C_WR_DEPTH : Depth of write interface (2^N) * C_WR_FREQ : not used in bhv model * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) * C_WR_RESPONSE_LATENCY : *not used * C_MSGON_VAL : *not used by bhv model * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST * 1 = Use RST * C_ERROR_INJECTION_TYPE : 0 = No error injection * 1 = Single bit error injection only * 2 = Double bit error injection only * 3 = Single and double bit error injection ****************************************************************************** * Definition of Ports ****************************************************************************** * BACKUP : Not used * BACKUP_MARKER: Not used * CLK : Clock * DIN : Input data bus * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag * PROG_FULL_THRESH : Threshold for Programmable Full Flag * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag * RD_CLK : Read Domain Clock * RD_EN : Read enable * RD_RST : Read Reset * RST : Asynchronous Reset * SRST : Synchronous Reset * WR_CLK : Write Domain Clock * WR_EN : Write enable * WR_RST : Write Reset * INT_CLK : Internal Clock * INJECTSBITERR: Inject Signle bit error * INJECTDBITERR: Inject Double bit error * ALMOST_EMPTY : One word remaining in FIFO * ALMOST_FULL : One empty space remaining in FIFO * DATA_COUNT : Number of data words in fifo( synchronous to CLK) * DOUT : Output data bus * EMPTY : Empty flag * FULL : Full flag * OVERFLOW : Last write rejected * PROG_EMPTY : Programmable Empty Flag * PROG_FULL : Programmable Full Flag * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) * UNDERFLOW : Last read rejected * VALID : Last read acknowledged, DOUT bus VALID * WR_ACK : Last write acknowledged * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) * SBITERR : Single Bit ECC Error Detected * DBITERR : Double Bit ECC Error Detected ****************************************************************************** */ //---------------------------------------------------------------------------- //- Internal Signals for delayed input signals //- All the input signals except Clock are delayed by 100 ps and then given to //- the models. //---------------------------------------------------------------------------- reg rst_delayed ; reg empty_fb ; reg srst_delayed ; reg wr_rst_delayed ; reg rd_rst_delayed ; reg wr_en_delayed ; reg rd_en_delayed ; reg [C_DIN_WIDTH-1:0] din_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ; reg injectdbiterr_delayed ; reg injectsbiterr_delayed ; wire empty_p0_out; always @* rst_delayed <= #`TCQ RST ; always @* empty_fb <= #`TCQ empty_p0_out ; always @* srst_delayed <= #`TCQ SRST ; always @* wr_rst_delayed <= #`TCQ WR_RST ; always @* rd_rst_delayed <= #`TCQ RD_RST ; always @* din_delayed <= #`TCQ DIN ; always @* wr_en_delayed <= #`TCQ WR_EN ; always @* rd_en_delayed <= #`TCQ RD_EN ; always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; /***************************************************************************** * Derived parameters ****************************************************************************/ //There are 2 Verilog behavioral models // 0 = Common-Clock FIFO/ShiftRam FIFO // 1 = Independent Clocks FIFO // 2 = Low Latency Synchronous FIFO // 3 = Low Latency Asynchronous FIFO localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 : (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; //Internal reset signals reg rd_rst_asreg = 0; wire rd_rst_asreg_d1; wire rd_rst_asreg_d2; reg rd_rst_asreg_d3 = 0; reg rd_rst_reg = 0; wire rd_rst_comb; reg wr_rst_d0 = 0; reg wr_rst_d1 = 0; reg wr_rst_d2 = 0; reg rd_rst_d0 = 0; reg rd_rst_d1 = 0; reg rd_rst_d2 = 0; reg rd_rst_d3 = 0; reg wrrst_done = 0; reg rdrst_done = 0; reg wr_rst_asreg = 0; wire wr_rst_asreg_d1; wire wr_rst_asreg_d2; reg wr_rst_asreg_d3 = 0; reg rd_rst_wr_d0 = 0; reg rd_rst_wr_d1 = 0; reg rd_rst_wr_d2 = 0; reg wr_rst_reg = 0; reg rst_active_i = 1'b1; reg rst_delayed_d1 = 1'b1; reg rst_delayed_d2 = 1'b1; wire wr_rst_comb; wire wr_rst_i; wire rd_rst_i; wire rst_i; //Internal reset signals reg rst_asreg = 0; reg srst_asreg = 0; wire rst_asreg_d1; wire rst_asreg_d2; reg srst_asreg_d1 = 0; reg srst_asreg_d2 = 0; reg rst_reg = 0; reg srst_reg = 0; wire rst_comb; wire srst_comb; reg rst_full_gen_i = 0; reg rst_full_ff_i = 0; reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}}; wire RD_CLK_P0_IN; wire RST_P0_IN; wire RD_EN_FIFO_IN; wire RD_EN_P0_IN; wire ALMOST_EMPTY_FIFO_OUT; wire ALMOST_FULL_FIFO_OUT; wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; wire EMPTY_FIFO_OUT; wire fifo_empty_fb; wire FULL_FIFO_OUT; wire OVERFLOW_FIFO_OUT; wire PROG_EMPTY_FIFO_OUT; wire PROG_FULL_FIFO_OUT; wire VALID_FIFO_OUT; wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; wire UNDERFLOW_FIFO_OUT; wire WR_ACK_FIFO_OUT; wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; //*************************************************************************** // Internal Signals // The core uses either the internal_ wires or the preload0_ wires depending // on whether the core uses Preload0 or not. // When using preload0, the internal signals connect the internal core to // the preload logic, and the external core's interfaces are tied to the // preload0 signals from the preload logic. //*************************************************************************** wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; wire VALID_P0_OUT; wire EMPTY_P0_OUT; wire ALMOSTEMPTY_P0_OUT; reg EMPTY_P0_OUT_Q; reg ALMOSTEMPTY_P0_OUT_Q; wire UNDERFLOW_P0_OUT; wire RDEN_P0_OUT; wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; wire EMPTY_P0_IN; reg [31:0] DATA_COUNT_FWFT; reg SS_FWFT_WR ; reg SS_FWFT_RD ; wire sbiterr_fifo_out; wire dbiterr_fifo_out; wire inject_sbit_err; wire inject_dbit_err; wire safety_ckt_wr_rst; wire safety_ckt_rd_rst; reg sckt_wr_rst_i_q = 1'b0; wire w_fab_read_data_valid_i; wire w_read_data_valid_i; wire w_ram_valid_i; // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? injectsbiterr_delayed : 0; assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? injectdbiterr_delayed : 0; assign wr_rst_i_out = wr_rst_i; assign rd_rst_i_out = rd_rst_i; assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2]; generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK; always @ (posedge clk_i) sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; end endgenerate // Choose the behavioral model to instantiate based on the C_VERILOG_IMPL // parameter (1=Independent Clocks, 0=Common Clock) localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; generate case (C_VERILOG_IMPL) 0 : begin : block1 //Common Clock Behavioral Model fifo_generator_v13_1_2_bhv_ver_ss #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), .C_FIFO_TYPE (C_FIFO_TYPE) ) gen_ss ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .CLK (CLK), .RST (rst_i), .SRST (srst_delayed), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .USER_EMPTY_FB (empty_fb), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .DATA_COUNT (DATA_COUNT_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .SBITERR (sbiterr_fifo_out), .DBITERR (dbiterr_fifo_out) ); end 1 : begin : block1 //Independent Clocks Behavioral Model fifo_generator_v13_1_2_bhv_ver_as #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) ) gen_as ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .SAFETY_CKT_RD_RST (safety_ckt_rd_rst), .WR_CLK (WR_CLK), .RD_CLK (RD_CLK), .RST (rst_i), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .USER_EMPTY_FB (EMPTY_P0_OUT), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .SBITERR (sbiterr_fifo_out), .fab_read_data_valid_i (w_fab_read_data_valid_i), .read_data_valid_i (w_read_data_valid_i), .ram_valid_i (w_ram_valid_i), .DBITERR (dbiterr_fifo_out) ); end 2 : begin : ll_afifo_inst fifo_generator_v13_1_2_beh_ver_ll_afifo #( .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_FIFO_TYPE (C_FIFO_TYPE) ) gen_ll_afifo ( .DIN (din_delayed), .RD_CLK (RD_CLK), .RD_EN (rd_en_delayed), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .WR_CLK (WR_CLK), .WR_EN (wr_en_delayed), .DOUT (DOUT), .EMPTY (EMPTY), .FULL (FULL) ); end default : begin : block1 //Independent Clocks Behavioral Model fifo_generator_v13_1_2_bhv_ver_as #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) ) gen_as ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .SAFETY_CKT_RD_RST (safety_ckt_rd_rst), .WR_CLK (WR_CLK), .RD_CLK (RD_CLK), .RST (rst_i), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .USER_EMPTY_FB (EMPTY_P0_OUT), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .SBITERR (sbiterr_fifo_out), .DBITERR (dbiterr_fifo_out) ); end endcase endgenerate //************************************************************************** // Connect Internal Signals // (Signals labeled internal_*) // In the normal case, these signals tie directly to the FIFO's inputs and // outputs. // In the case of Preload Latency 0 or 1, there are intermediate // signals between the internal FIFO and the preload logic. //************************************************************************** //*********************************************** // If First-Word Fall-Through, instantiate // the preload0 (FWFT) module //*********************************************** wire rd_en_to_fwft_fifo; wire sbiterr_fwft; wire dbiterr_fwft; wire [C_DOUT_WIDTH-1:0] dout_fwft; wire empty_fwft; wire rd_en_fifo_in; wire stage2_reg_en_i; wire [1:0] valid_stages_i; wire rst_fwft; //wire empty_p0_out; reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1; localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0; localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0; assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0; generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2 fifo_generator_v13_1_2_bhv_ver_preload0 #( .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_HAS_RST (C_HAS_RST), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_HAS_SRST (C_HAS_SRST), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_USE_ECC (C_USE_ECC), .C_USERVALID_LOW (C_VALID_LOW), .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_FIFO_TYPE (C_FIFO_TYPE) ) fgpl0 ( .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), .RD_CLK (RD_CLK_P0_IN), .RD_RST (RST_P0_IN), .SRST (srst_delayed), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .RD_EN (RD_EN_P0_IN), .FIFOEMPTY (EMPTY_P0_IN), .FIFODATA (DATA_P0_IN), .FIFOSBITERR (sbiterr_fifo_out), .FIFODBITERR (dbiterr_fifo_out), // Output .USERDATA (dout_fwft), .USERVALID (VALID_P0_OUT), .USEREMPTY (empty_fwft), .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), .USERUNDERFLOW (UNDERFLOW_P0_OUT), .RAMVALID (), .FIFORDEN (rd_en_fifo_in), .USERSBITERR (sbiterr_fwft), .USERDBITERR (dbiterr_fwft), .STAGE2_REG_EN (stage2_reg_en_i), .fab_read_data_valid_i_o (w_fab_read_data_valid_i), .read_data_valid_i_o (w_read_data_valid_i), .ram_valid_i_o (w_ram_valid_i), .VALID_STAGES (valid_stages_i) ); //*********************************************** // Connect inputs to preload (FWFT) module //*********************************************** //Connect the RD_CLK of the Preload (FWFT) module to CLK if we // have a common-clock FIFO, or RD_CLK if we have an // independent clock FIFO assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT; assign DATA_P0_IN = DOUT_FIFO_OUT; //*********************************************** // Connect outputs from preload (FWFT) module //*********************************************** assign VALID = VALID_P0_OUT ; assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; assign UNDERFLOW = UNDERFLOW_P0_OUT ; assign RD_EN_FIFO_IN = rd_en_fifo_in; //*********************************************** // Create DATA_COUNT from First-Word Fall-Through // data count //*********************************************** assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; //*********************************************** // Create DATA_COUNT from First-Word Fall-Through // data count //*********************************************** always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin if (RST_P0_IN) begin EMPTY_P0_OUT_Q <= 1; ALMOSTEMPTY_P0_OUT_Q <= 1; end else begin EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out; // EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT; ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; end end //always //*********************************************** // logic for common-clock data count when FWFT is selected //*********************************************** initial begin SS_FWFT_RD = 1'b0; DATA_COUNT_FWFT = 0 ; SS_FWFT_WR = 1'b0 ; end //initial //*********************************************** // common-clock data count is implemented as an // up-down counter. SS_FWFT_WR and SS_FWFT_RD // are the up/down enables for the counter. //*********************************************** always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin if (C_VALID_LOW == 1) begin SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ; end else begin SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ; end SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; end //*********************************************** // common-clock data count is implemented as an // up-down counter for FWFT. This always block // calculates the counter. //*********************************************** always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin if (RST_P0_IN) begin DATA_COUNT_FWFT <= 0; end else begin //if (srst_delayed && (C_HAS_SRST == 1) ) begin if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin DATA_COUNT_FWFT <= #`TCQ 0; end else begin case ( {SS_FWFT_WR, SS_FWFT_RD}) 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; endcase end //if SRST end //IF RST end //always end endgenerate // : block2 // AXI Streaming Packet FIFO reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0; reg partial_packet = 0; reg stage1_eop_d1 = 0; reg rd_en_fifo_in_d1 = 0; reg eop_at_stage2 = 0; reg ram_pkt_empty = 0; reg ram_pkt_empty_d1 = 0; wire [C_DOUT_WIDTH-1:0] dout_p0_out; wire packet_empty_wr; wire wr_rst_fwft_pkt_fifo; wire dummy_wr_eop; wire ram_wr_en_pkt_fifo; wire wr_eop; wire ram_rd_en_compare; wire stage1_eop; wire pkt_ready_to_read; wire rd_en_2_stage2; // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming) // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of // write packet count generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) partial_packet <= 1'b0; else begin if (srst_delayed | wr_rst_busy | rd_rst_busy) partial_packet <= #`TCQ 1'b0; else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0])) partial_packet <= #`TCQ 1'b1; else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo) partial_packet <= #`TCQ 1'b0; end end end endgenerate // gdummy_wr_eop generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0; assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet); assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1]; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin stage1_eop_d1 <= 1'b0; rd_en_fifo_in_d1 <= 1'b0; end else begin if (srst_delayed | wr_rst_busy | rd_rst_busy) begin stage1_eop_d1 <= #`TCQ 1'b0; rd_en_fifo_in_d1 <= #`TCQ 1'b0; end else begin stage1_eop_d1 <= #`TCQ stage1_eop; rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in; end end end assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1; assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT); assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop); assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop; fifo_generator_v13_1_2_bhv_ver_preload0 #( .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_ECC (C_USE_ECC), .C_USERVALID_LOW (C_VALID_LOW), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_FIFO_TYPE (2) // Enable low latency fwft logic ) pkt_fifo_fwft ( .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), .RD_CLK (RD_CLK_P0_IN), .RD_RST (rst_fwft), .SRST (srst_delayed), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .RD_EN (rd_en_delayed), .FIFOEMPTY (pkt_ready_to_read), .FIFODATA (dout_fwft), .FIFOSBITERR (sbiterr_fwft), .FIFODBITERR (dbiterr_fwft), // Output .USERDATA (dout_p0_out), .USERVALID (), .USEREMPTY (empty_p0_out), .USERALMOSTEMPTY (), .USERUNDERFLOW (), .RAMVALID (), .FIFORDEN (rd_en_2_stage2), .USERSBITERR (SBITERR), .USERDBITERR (DBITERR), .STAGE2_REG_EN (), .VALID_STAGES () ); assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2)); assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) eop_at_stage2 <= 1'b0; else if (stage2_reg_en_i) eop_at_stage2 <= #`TCQ stage1_eop; end //--------------------------------------------------------------------------- // Write and Read Packet Count //--------------------------------------------------------------------------- always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) wr_pkt_count <= 0; else if (srst_delayed | wr_rst_busy | rd_rst_busy) wr_pkt_count <= #`TCQ 0; else if (wr_eop) wr_pkt_count <= #`TCQ wr_pkt_count + 1; end end endgenerate // gpkt_fifo_fwft assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out; assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out; generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin rd_pkt_count <= 0; rd_pkt_count_plus1 <= 1; end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin rd_pkt_count <= #`TCQ 0; rd_pkt_count_plus1 <= #`TCQ 1; end else if (stage2_reg_en_i && stage1_eop) begin rd_pkt_count <= #`TCQ rd_pkt_count + 1; rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1; end end always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin ram_pkt_empty <= 1'b1; ram_pkt_empty_d1 <= 1'b1; end else if (SRST | wr_rst_busy | rd_rst_busy) begin ram_pkt_empty <= #`TCQ 1'b1; ram_pkt_empty_d1 <= #`TCQ 1'b1; end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin ram_pkt_empty <= #`TCQ 1'b0; ram_pkt_empty_d1 <= #`TCQ 1'b0; end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin ram_pkt_empty <= #`TCQ 1'b1; end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin ram_pkt_empty_d1 <= #`TCQ 1'b1; end end end endgenerate //grss_pkt_cnt localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH; reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0; wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd; generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) wr_pkt_count_b2g <= 0; else wr_pkt_count_b2g <= #`TCQ wr_pkt_count; end // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) wr_pkt_count_q <= 0; else wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g}; end always @* begin if (stage1_eop) rd_pkt_count <= rd_pkt_count_reg + 1; else rd_pkt_count <= rd_pkt_count_reg; end assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH]; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) rd_pkt_count_reg <= 0; else if (rd_en_fifo_in) rd_pkt_count_reg <= #`TCQ rd_pkt_count; end always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin ram_pkt_empty <= 1'b1; ram_pkt_empty_d1 <= 1'b1; end else if (rd_pkt_count != wr_pkt_count_rd) begin ram_pkt_empty <= #`TCQ 1'b0; ram_pkt_empty_d1 <= #`TCQ 1'b0; end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin ram_pkt_empty <= #`TCQ 1'b1; end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin ram_pkt_empty_d1 <= #`TCQ 1'b1; end end // Synchronize the empty in write domain always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) pkt_empty_sync <= 'b1; else pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out}; end end endgenerate //gras_pkt_cnt generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO //*********************************************** // If NOT First-Word Fall-Through, wire the outputs // of the internal _ss or _as FIFO directly to the // output, and do not instantiate the preload0 // module. //*********************************************** assign RD_CLK_P0_IN = 0; assign RST_P0_IN = 0; assign RD_EN_P0_IN = 0; assign RD_EN_FIFO_IN = rd_en_delayed; assign DOUT = DOUT_FIFO_OUT; assign DATA_P0_IN = 0; assign VALID = VALID_FIFO_OUT; assign EMPTY = EMPTY_FIFO_OUT; assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; assign EMPTY_P0_IN = 0; assign UNDERFLOW = UNDERFLOW_FIFO_OUT; assign DATA_COUNT = DATA_COUNT_FIFO_OUT; assign SBITERR = sbiterr_fifo_out; assign DBITERR = dbiterr_fifo_out; end endgenerate // STD_FIFO generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO assign empty_p0_out = empty_fwft; assign SBITERR = sbiterr_fwft; assign DBITERR = dbiterr_fwft; assign DOUT = dout_fwft; assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; end endgenerate // NO_PKT_FIFO //*********************************************** // Connect user flags to internal signals //*********************************************** //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3 if (C_COMMON_CLOCK == 0) begin : block_ic assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); end //block_ic else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block3 endgenerate //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30 if (C_COMMON_CLOCK == 0) begin : block_ic assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); end else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block30 endgenerate //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both if (C_COMMON_CLOCK == 0) begin : block_ic_both assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT)); end else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block30_both endgenerate generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both if (C_COMMON_CLOCK == 0) begin : block_ic_both assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT)); end //block_ic_both else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block3_both endgenerate //If we are not using extra logic for the FWFT data count, //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the //internal FIFO instance generate if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end endgenerate //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal //FIFO instance generate if (C_USE_FWFT_DATA_COUNT==1) begin : block4 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; end else begin : block4 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; end endgenerate //Connect other flags to the internal FIFO instance assign FULL = FULL_FIFO_OUT; assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; assign WR_ACK = WR_ACK_FIFO_OUT; assign OVERFLOW = OVERFLOW_FIFO_OUT; assign PROG_FULL = PROG_FULL_FIFO_OUT; assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; /************************************************************************** * find_log2 * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function integer find_log2; input integer int_val; integer i,j; begin i = 1; j = 0; for (i = 1; i < int_val; i = i*2) begin j = j + 1; end find_log2 = j; end endfunction // if an asynchronous FIFO has been selected, display a message that the FIFO // will not be cycle-accurate in simulation initial begin if (C_IMPLEMENTATION_TYPE == 2) begin $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); end else if (C_MEMORY_TYPE == 4) begin $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."); $finish; end if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); $finish; end if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); $finish; end if (C_USE_ECC == 1) begin if (C_DIN_WIDTH != C_DOUT_WIDTH) begin $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."); $finish; end if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."); $finish; end end end //initial /************************************************************************** * Internal reset logic **************************************************************************/ assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; assign rst_i = C_HAS_RST ? rst_reg : 0; wire rst_2_sync; wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST; wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK; localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE : (C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2; reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}}; reg [1:0] wrst_cc = {2{1'b0}}; reg [1:0] rrst_cc = {2{1'b0}}; generate if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt reg[1:0] rst_d1_safety =1; reg[1:0] rst_d2_safety =1; reg[1:0] rst_d3_safety =1; reg[1:0] rst_d4_safety =1; reg[1:0] rst_d5_safety =1; reg[1:0] rst_d6_safety =1; reg[1:0] rst_d7_safety =1; always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst if (rst_2_sync_safety == 1'b1) begin rst_d1_safety <= 1'b1; rst_d2_safety <= 1'b1; rst_d3_safety <= 1'b1; rst_d4_safety <= 1'b1; rst_d5_safety <= 1'b1; rst_d6_safety <= 1'b1; rst_d7_safety <= 1'b1; end else begin rst_d1_safety <= #`TCQ 1'b0; rst_d2_safety <= #`TCQ rst_d1_safety; rst_d3_safety <= #`TCQ rst_d2_safety; rst_d4_safety <= #`TCQ rst_d3_safety; rst_d5_safety <= #`TCQ rst_d4_safety; rst_d6_safety <= #`TCQ rst_d5_safety; rst_d7_safety <= #`TCQ rst_d6_safety; end //if end //prst always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety if(rst_d7_safety == 1 && WR_EN == 1) begin $display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled."); end //if end //always end // grst_safety_ckt endgenerate // if (C_EN_SAFET_CKT == 1) // assertion:the reset shud be atleast 3 cycles wide. generate reg safety_ckt_wr_rst_i = 1'b0; if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync always @* begin wr_rst_reg <= wr_rst_delayed; rd_rst_reg <= rd_rst_delayed; rst_reg <= 1'b0; srst_reg <= 1'b0; end assign rst_2_sync = wr_rst_delayed; assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0; // end : gnrst_sync end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst reg fifo_wrst_done = 1'b0; reg fifo_rrst_done = 1'b0; reg sckt_wrst_i = 1'b0; reg sckt_wrst_i_q = 1'b0; reg rd_rst_active = 1'b0; reg rd_rst_middle = 1'b0; reg sckt_rd_rst_d1 = 1'b0; reg [1:0] rst_delayed_ic_w = 2'h0; wire rst_delayed_ic_w_i; reg [1:0] rst_delayed_ic_r = 2'h0; wire rst_delayed_ic_r_i; wire arst_sync_rst; wire fifo_rst_done; wire fifo_rst_active; assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg; assign rst_2_sync = rst_delayed_ic_w_i; assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1]; assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0; assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done; assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1]; always @(posedge WR_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1 && C_HAS_RST) rst_delayed_ic_w <= 2'b11; else rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0}; end assign rst_delayed_ic_w_i = rst_delayed_ic_w[1]; always @(posedge RD_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1 && C_HAS_RST) rst_delayed_ic_r <= 2'b11; else rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0}; end assign rst_delayed_ic_r_i = rst_delayed_ic_r[1]; always @(posedge WR_CLK) begin sckt_wrst_i_q <= #`TCQ sckt_wrst_i; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q; if (arst_sync_rst && ~fifo_rst_active) sckt_wrst_i <= #`TCQ 1'b1; else if (sckt_wrst_i && fifo_rst_done) sckt_wrst_i <= #`TCQ 1'b0; else sckt_wrst_i <= #`TCQ sckt_wrst_i; if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1]) fifo_rrst_done <= #`TCQ 1'b1; else if (fifo_rst_done) fifo_rrst_done <= #`TCQ 1'b0; else fifo_rrst_done <= #`TCQ fifo_rrst_done; if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1]) fifo_wrst_done <= #`TCQ 1'b1; else if (fifo_rst_done) fifo_wrst_done <= #`TCQ 1'b0; else fifo_wrst_done <= #`TCQ fifo_wrst_done; end always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin if (rst_delayed_ic_w_i == 1'b1) begin wr_rst_asreg <= 1'b1; end else begin if (wr_rst_asreg_d1 == 1'b1) begin wr_rst_asreg <= #`TCQ 1'b0; end else begin wr_rst_asreg <= #`TCQ wr_rst_asreg; end end end always @(posedge WR_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1) begin wr_rst_asreg <= 1'b1; end else begin if (wr_rst_asreg_d1 == 1'b1) begin wr_rst_asreg <= #`TCQ 1'b0; end else begin wr_rst_asreg <= #`TCQ wr_rst_asreg; end end end always @(posedge WR_CLK) begin wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg}; wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i}; rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst}; arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i}; end assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2]; assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1]; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; always @(posedge WR_CLK or posedge wr_rst_comb) begin if (wr_rst_comb == 1'b1) begin wr_rst_reg <= 1'b1; end else begin wr_rst_reg <= #`TCQ 1'b0; end end always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin if (rst_delayed_ic_r_i == 1'b1) begin rd_rst_asreg <= 1'b1; end else begin if (rd_rst_asreg_d1 == 1'b1) begin rd_rst_asreg <= #`TCQ 1'b0; end else begin rd_rst_asreg <= #`TCQ rd_rst_asreg; end end end always @(posedge RD_CLK) begin rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg}; rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i}; rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2}; sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst; if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin rd_rst_active <= #`TCQ 1'b1; rd_rst_middle <= #`TCQ 1'b1; end else if (safety_ckt_rd_rst) rd_rst_active <= #`TCQ 1'b0; else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst) rd_rst_middle <= #`TCQ 1'b0; end assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2]; assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1]; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0; always @(posedge RD_CLK or posedge rd_rst_comb) begin if (rd_rst_comb == 1'b1) begin rd_rst_reg <= 1'b1; end else begin rd_rst_reg <= #`TCQ 1'b0; end end // end : g7s_ic_rst end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst reg [1:0] rst_delayed_cc = 2'h0; wire rst_delayed_cc_i; assign rst_comb = !rst_asreg_d2 && rst_asreg; assign rst_2_sync = rst_delayed_cc_i; assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0; always @(posedge CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1) rst_delayed_cc <= 2'b11; else rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0}; end assign rst_delayed_cc_i = rst_delayed_cc[1]; always @(posedge CLK or posedge rst_delayed_cc_i) begin if (rst_delayed_cc_i == 1'b1) begin rst_asreg <= 1'b1; end else begin if (rst_asreg_d1 == 1'b1) begin rst_asreg <= #`TCQ 1'b0; end else begin rst_asreg <= #`TCQ rst_asreg; end end end always @(posedge CLK) begin wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg}; wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]}; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q; arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i}; end assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2]; assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1]; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; always @(posedge CLK or posedge rst_comb) begin if (rst_comb == 1'b1) begin rst_reg <= 1'b1; end else begin rst_reg <= #`TCQ 1'b0; end end // end : g7s_cc_rst end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i; assign rd_rst_busy = rst_reg; assign rst_2_sync = srst_delayed; always @* rst_full_ff_i <= rst_reg; always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0; always @(posedge CLK) begin rst_delayed_d1 <= #`TCQ srst_delayed; rst_delayed_d2 <= #`TCQ rst_delayed_d1; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; if (rst_reg || rst_delayed_d2) begin rst_active_i <= #`TCQ 1'b1; end else begin rst_active_i <= #`TCQ rst_reg; end end always @(posedge CLK) begin if (~rst_reg && srst_delayed) begin rst_reg <= #`TCQ 1'b1; end else if (rst_reg) begin rst_reg <= #`TCQ 1'b0; end else begin rst_reg <= #`TCQ rst_reg; end end // end : g8s_cc_rst end else begin assign wr_rst_busy = 1'b0; assign rd_rst_busy = 1'b0; assign safety_ckt_wr_rst = 1'b0; assign safety_ckt_rd_rst = 1'b0; end endgenerate generate if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 // RST_FULL_GEN replaces the reset falling edge detection used to de-assert // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & // PROG_FULL reg rst_d1 = 1'b0; reg rst_d2 = 1'b0; reg rst_d3 = 1'b0; reg rst_d4 = 1'b0; reg rst_d5 = 1'b0; always @ (posedge rst_2_sync or posedge clk_2_sync) begin if (rst_2_sync) begin rst_d1 <= 1'b1; rst_d2 <= 1'b1; rst_d3 <= 1'b1; rst_d4 <= 1'b1; end else begin if (srst_delayed) begin rst_d1 <= #`TCQ 1'b1; rst_d2 <= #`TCQ 1'b1; rst_d3 <= #`TCQ 1'b1; rst_d4 <= #`TCQ 1'b1; end else begin rst_d1 <= #`TCQ wr_rst_busy; rst_d2 <= #`TCQ rst_d1; rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst; rst_d4 <= #`TCQ rst_d3; end end end always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; always @* rst_full_gen_i <= rst_d3; end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; end endgenerate // grstd1 endmodule //fifo_generator_v13_1_2_conv_ver module fifo_generator_v13_1_2_sync_stage #( parameter C_WIDTH = 10 ) ( input RST, input CLK, input [C_WIDTH-1:0] DIN, output reg [C_WIDTH-1:0] DOUT = 0 ); always @ (posedge RST or posedge CLK) begin if (RST) DOUT <= 0; else DOUT <= #`TCQ DIN; end endmodule // fifo_generator_v13_1_2_sync_stage /******************************************************************************* * Declaration of Independent-Clocks FIFO Module ******************************************************************************/ module fifo_generator_v13_1_2_bhv_ver_as /*************************************************************************** * Declare user parameters and their defaults ***************************************************************************/ #( parameter C_FAMILY = "virtex7", parameter C_DATA_COUNT_WIDTH = 2, parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_MEMORY_TYPE = 1, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_USE_ECC = 0, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2 ) /*************************************************************************** * Declare Input and Output Ports ***************************************************************************/ ( input SAFETY_CKT_WR_RST, input SAFETY_CKT_RD_RST, input [C_DIN_WIDTH-1:0] DIN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input RD_CLK, input RD_EN, input RD_EN_USER, input RST, input RST_FULL_GEN, input RST_FULL_FF, input WR_RST, input RD_RST, input WR_CLK, input WR_EN, input INJECTDBITERR, input INJECTSBITERR, input USER_EMPTY_FB, input fab_read_data_valid_i, input read_data_valid_i, input ram_valid_i, output reg ALMOST_EMPTY = 1'b1, output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, output [C_DOUT_WIDTH-1:0] DOUT, output reg EMPTY = 1'b1, output reg EMPTY_FB = 1'b1, output reg FULL = C_FULL_FLAGS_RST_VAL, output OVERFLOW, output PROG_EMPTY, output PROG_FULL, output VALID, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output UNDERFLOW, output WR_ACK, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output SBITERR, output DBITERR ); reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; /*************************************************************************** * Parameters used as constants **************************************************************************/ localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; //When RST is present, set FULL reset value to '1'. //If core has no RST, make sure FULL powers-on as '0'. localparam C_DEPTH_RATIO_WR = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; localparam C_DEPTH_RATIO_RD = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC // -----------------|------------------|-----------------|--------------- // 1 | 8 | C_RD_PNTR_WIDTH | 2 // 1 | 4 | C_RD_PNTR_WIDTH | 2 // 1 | 2 | C_RD_PNTR_WIDTH | 2 // 1 | 1 | C_WR_PNTR_WIDTH | 2 // 2 | 1 | C_WR_PNTR_WIDTH | 4 // 4 | 1 | C_WR_PNTR_WIDTH | 8 // 8 | 1 | C_WR_PNTR_WIDTH | 16 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); /************************************************************************** * FIFO Contents Tracking and Data Count Calculations *************************************************************************/ // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; // Local parameters used to determine whether to inject ECC error or not localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION; // Array that holds the error injection type (single/double bit error) on // a specific write operation, which is returned on read to corrupt the // output data. reg [1:0] ecc_err[C_WR_DEPTH-1:0]; //The amount of data stored in the FIFO at any time is given // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK // domain. //num_wr_bits is calculated by considering the total words in the FIFO, // and the state of the read pointer (which may not have yet crossed clock // domains.) //num_rd_bits is calculated by considering the total words in the FIFO, // and the state of the write pointer (which may not have yet crossed clock // domains.) reg [31:0] num_wr_bits; reg [31:0] num_rd_bits; reg [31:0] next_num_wr_bits; reg [31:0] next_num_rd_bits; //The write pointer - tracks write operations // (Works opposite to core: wr_ptr is a DOWN counter) reg [31:0] wr_ptr; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; wire wr_rst_i = WR_RST; reg wr_rst_d1 =0; //The read pointer - tracks read operations // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) reg [31:0] rd_ptr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; wire rd_rst_i = RD_RST; wire ram_rd_en; wire empty_int; wire almost_empty_int; wire ram_wr_en; wire full_int; wire almost_full_int; reg ram_rd_en_d1 = 1'b0; reg fab_rd_en_d1 = 1'b0; // Delayed ram_rd_en is needed only for STD Embedded register option generate if (C_PRELOAD_LATENCY == 2) begin : grd_d always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) ram_rd_en_d1 <= 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; end end endgenerate generate if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1 always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) ram_rd_en_d1 <= 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; end end endgenerate // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; end else begin : rdl // Read depth lesser than or equal to write depth assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate // Generate Empty and Almost Empty // ram_rd_en used to determine EMPTY should depend on the EMPTY. assign ram_rd_en = RD_EN & !EMPTY; assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); // Register Empty and Almost Empty always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin EMPTY <= 1'b1; ALMOST_EMPTY <= 1'b1; rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; end else begin rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; if (empty_int) EMPTY <= #`TCQ 1'b1; else EMPTY <= #`TCQ 1'b0; if (!EMPTY) begin if (almost_empty_int) ALMOST_EMPTY <= #`TCQ 1'b1; else ALMOST_EMPTY <= #`TCQ 1'b0; end end // rd_rst_i end // always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin EMPTY_FB <= 1'b1; end else begin if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) EMPTY_FB <= #`TCQ 1'b1; else if (empty_int) EMPTY_FB <= #`TCQ 1'b1; else EMPTY_FB <= #`TCQ 1'b0; end // rd_rst_i end // always // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; end else begin : wdl // Write depth lesser than or equal to read depth assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate // Generate FULL and ALMOST_FULL // ram_wr_en used to determine FULL should depend on the FULL. assign ram_wr_en = WR_EN & !FULL; assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); // Register FULL and ALMOST_FULL Empty always @ (posedge WR_CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) begin FULL <= C_FULL_FLAGS_RST_VAL; ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; end else begin if (full_int) begin FULL <= #`TCQ 1'b1; end else begin FULL <= #`TCQ 1'b0; end if (RST_FULL_GEN) begin ALMOST_FULL <= #`TCQ 1'b0; end else if (!FULL) begin if (almost_full_int) ALMOST_FULL <= #`TCQ 1'b1; else ALMOST_FULL <= #`TCQ 1'b0; end end // wr_rst_i end // always always @ (posedge WR_CLK or posedge wr_rst_i) begin if (wr_rst_i) begin wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}}; end else begin wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; end // wr_rst_i end // always // Determine which stage in FWFT registers are valid reg stage1_valid = 0; reg stage2_valid = 0; generate if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin stage1_valid <= 0; stage2_valid <= 0; end else begin if (!stage1_valid && !stage2_valid) begin if (!EMPTY) stage1_valid <= #`TCQ 1'b1; else stage1_valid <= #`TCQ 1'b0; end else if (stage1_valid && !stage2_valid) begin if (EMPTY) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else if (!stage1_valid && stage2_valid) begin if (EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && !RD_EN_USER) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end end else if (stage1_valid && stage2_valid) begin if (EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end end // rd_rst_i end // always end endgenerate //Pointers passed into opposite clock domain reg [31:0] wr_ptr_rdclk; reg [31:0] wr_ptr_rdclk_next; reg [31:0] rd_ptr_wrclk; reg [31:0] rd_ptr_wrclk_next; //Amount of data stored in the FIFO scaled to the narrowest (deepest) port // (Do not include data in FWFT stages) //Used to calculate PROG_EMPTY. wire [31:0] num_read_words_pe = num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); //Amount of data stored in the FIFO scaled to the narrowest (deepest) port // (Do not include data in FWFT stages) //Used to calculate PROG_FULL. wire [31:0] num_write_words_pf = num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); /************************** * Read Data Count *************************/ reg [31:0] num_read_words_dc; reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; always @(num_rd_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //If using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain, // and add two read words for FWFT stages //This value is only a temporary value and not used in the code. num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; end else begin //If not using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain. //This value is only a temporary value and not used in the code. num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************** * Write Data Count *************************/ reg [31:0] num_write_words_dc; reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; always @(num_wr_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //Calculate the Data Count value for the number of write words, // when using First-Word Fall-Through with extra logic for Data // Counts. This takes into consideration the number of words that // are expected to be stored in the FWFT register stages (it always // assumes they are filled). //This value is scaled to the Write Domain. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //When num_wr_bits==0, set the result manually to prevent // division errors. //EXTRA_WORDS_DC is the number of words added to write_words // due to FWFT. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; //Trim the write words for use with WR_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; end else begin //Calculate the Data Count value for the number of write words, when NOT // using First-Word Fall-Through with extra logic for Data Counts. This // calculates only the number of words in the internal FIFO. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //This value is scaled to the Write Domain. //When num_wr_bits==0, set the result manually to prevent // division errors. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; //Trim the read words for use with RD_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /*************************************************************************** * Internal registers and wires **************************************************************************/ //Temporary signals used for calculating the model's outputs. These //are only used in the assign statements immediately following wire, //parameter, and function declarations. wire [C_DOUT_WIDTH-1:0] ideal_dout_out; wire valid_i; wire valid_out1; wire valid_out2; wire valid_out; wire underflow_i; //Ideal FIFO signals. These are the raw output of the behavioral model, //which behaves like an ideal FIFO. reg [1:0] err_type = 0; reg [1:0] err_type_d1 = 0; reg [1:0] err_type_both = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; reg ideal_wr_ack = 0; reg ideal_valid = 0; reg ideal_overflow = C_OVERFLOW_LOW; reg ideal_underflow = C_UNDERFLOW_LOW; reg ideal_prog_full = 0; reg ideal_prog_empty = 1; reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; //Assorted reg values for delayed versions of signals reg valid_d1 = 0; reg valid_d2 = 0; //user specified value for reseting the size of the fifo reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; //temporary registers for WR_RESPONSE_LATENCY feature integer tmp_wr_listsize; integer tmp_rd_listsize; //Signal for registered version of prog full and empty //Threshold values for Programmable Flags integer prog_empty_actual_thresh_assert; integer prog_empty_actual_thresh_negate; integer prog_full_actual_thresh_assert; integer prog_full_actual_thresh_negate; /**************************************************************************** * Function Declarations ***************************************************************************/ /************************************************************************** * write_fifo * This task writes a word to the FIFO memory and updates the * write pointer. * FIFO size is relative to write domain. ***************************************************************************/ task write_fifo; begin memory[wr_ptr] <= DIN; wr_pntr <= #`TCQ wr_pntr + 1; // Store the type of error injection (double/single) on write case (C_ERROR_INJECTION_TYPE) 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; default: ecc_err[wr_ptr] <= 0; endcase // (Works opposite to core: wr_ptr is a DOWN counter) if (wr_ptr == 0) begin wr_ptr <= C_WR_DEPTH - 1; end else begin wr_ptr <= wr_ptr - 1; end end endtask // write_fifo /************************************************************************** * read_fifo * This task reads a word from the FIFO memory and updates the read * pointer. It's output is the ideal_dout bus. * FIFO size is relative to write domain. ***************************************************************************/ task read_fifo; integer i; reg [C_DOUT_WIDTH-1:0] tmp_dout; reg [C_DIN_WIDTH-1:0] memory_read; reg [31:0] tmp_rd_ptr; reg [31:0] rd_ptr_high; reg [31:0] rd_ptr_low; reg [1:0] tmp_ecc_err; begin rd_pntr <= #`TCQ rd_pntr + 1; // output is wider than input if (reads_per_write == 0) begin tmp_dout = 0; tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); for (i = writes_per_read - 1; i >= 0; i = i - 1) begin tmp_dout = tmp_dout << C_DIN_WIDTH; tmp_dout = tmp_dout | memory[tmp_rd_ptr]; // (Works opposite to core: rd_ptr is a DOWN counter) if (tmp_rd_ptr == 0) begin tmp_rd_ptr = C_WR_DEPTH - 1; end else begin tmp_rd_ptr = tmp_rd_ptr - 1; end end // output is symmetric end else if (reads_per_write == 1) begin tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; // Retreive the error injection type. Based on the error injection type // corrupt the output data. tmp_ecc_err = ecc_err[rd_ptr]; if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error if (C_DOUT_WIDTH == 1) begin $display("FAILURE : Data width must be >= 2 for double bit error injection."); $finish; end else if (C_DOUT_WIDTH == 2) tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; else tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; end else begin tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; end err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; end else begin err_type <= 0; end // input is wider than output end else begin rd_ptr_high = rd_ptr >> log2_reads_per_write; rd_ptr_low = rd_ptr & (reads_per_write - 1); memory_read = memory[rd_ptr_high]; tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); end ideal_dout <= tmp_dout; // (Works opposite to core: rd_ptr is a DOWN counter) if (rd_ptr == 0) begin rd_ptr <= C_RD_DEPTH - 1; end else begin rd_ptr <= rd_ptr - 1; end end endtask /************************************************************************** * log2_val * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function [31:0] log2_val; input [31:0] binary_val; begin if (binary_val == 8) begin log2_val = 3; end else if (binary_val == 4) begin log2_val = 2; end else begin log2_val = 1; end end endfunction /*********************************************************************** * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***********************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction /************************************************************************* * Initialize Signals for clean power-on simulation *************************************************************************/ initial begin num_wr_bits = 0; num_rd_bits = 0; next_num_wr_bits = 0; next_num_rd_bits = 0; rd_ptr = C_RD_DEPTH - 1; wr_ptr = C_WR_DEPTH - 1; wr_pntr = 0; rd_pntr = 0; rd_ptr_wrclk = rd_ptr; wr_ptr_rdclk = wr_ptr; dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); ideal_dout = dout_reset_val; err_type = 0; err_type_d1 = 0; err_type_both = 0; ideal_dout_d1 = dout_reset_val; ideal_wr_ack = 1'b0; ideal_valid = 1'b0; valid_d1 = 1'b0; valid_d2 = 1'b0; ideal_overflow = C_OVERFLOW_LOW; ideal_underflow = C_UNDERFLOW_LOW; ideal_wr_count = 0; ideal_rd_count = 0; ideal_prog_full = 1'b0; ideal_prog_empty = 1'b1; end /************************************************************************* * Connect the module inputs and outputs to the internal signals of the * behavioral model. *************************************************************************/ //Inputs /* wire [C_DIN_WIDTH-1:0] DIN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire RD_CLK; wire RD_EN; wire RST; wire WR_CLK; wire WR_EN; */ //*************************************************************************** // Dout may change behavior based on latency //*************************************************************************** assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )? ideal_dout_d1: ideal_dout; assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; //*************************************************************************** // Assign SBITERR and DBITERR based on latency //*************************************************************************** assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && (C_PRELOAD_LATENCY == 2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ? err_type_d1[0]: err_type[0]; assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[1]: err_type[1]; //*************************************************************************** // Safety-ckt logic with embedded reg/fabric reg //*************************************************************************** generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; // if (C_HAS_VALID == 1) begin // assign valid_out = valid_d1; // end always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) ram_rd_en_d1 <= #`TCQ 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; end always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1[0] <= #`TCQ err_type[0]; err_type_d1[1] <= #`TCQ err_type[1]; end end end end endgenerate //*************************************************************************** // Safety-ckt logic with embedded reg + fabric reg //*************************************************************************** generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) ram_rd_en_d1 <= #`TCQ 1'b0; else begin ram_rd_en_d1 <= #`TCQ ram_rd_en; fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; end end always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both[0] <= #`TCQ err_type[0]; err_type_both[1] <= #`TCQ err_type[1]; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1[0] <= #`TCQ err_type_both[0]; err_type_d1[1] <= #`TCQ err_type_both[1]; end end end end endgenerate //*************************************************************************** // Overflow may be active-low //*************************************************************************** generate if (C_HAS_OVERFLOW==1) begin : blockOF1 assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; end endgenerate assign PROG_EMPTY = ideal_prog_empty; assign PROG_FULL = ideal_prog_full; //*************************************************************************** // Valid may change behavior based on latency or active-low //*************************************************************************** generate if (C_HAS_VALID==1) begin : blockVL1 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; assign valid_out1 = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)? valid_d1: valid_i; assign valid_out2 = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)? valid_d2: valid_i; assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1; assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; end endgenerate //*************************************************************************** // Underflow may change behavior based on latency or active-low //*************************************************************************** generate if (C_HAS_UNDERFLOW==1) begin : blockUF1 assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; end endgenerate //*************************************************************************** // Write acknowledge may be active low //*************************************************************************** generate if (C_HAS_WR_ACK==1) begin : blockWK1 assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; end endgenerate //*************************************************************************** // Generate RD_DATA_COUNT if Use Extra Logic option is selected //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; wire [C_PNTR_WIDTH:0] diff_wr_rd; reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; always @* begin if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin adjusted_wr_pntr = wr_pntr; adjusted_rd_pntr = 0; adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin adjusted_rd_pntr = rd_pntr_wr; adjusted_wr_pntr = 0; adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; end else begin adjusted_wr_pntr = wr_pntr; adjusted_rd_pntr = rd_pntr_wr; end end // always @* assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; always @ (posedge wr_rst_i or posedge WR_CLK) begin if (wr_rst_i) wr_data_count_i <= 0; else wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; end // always @ (posedge WR_CLK or posedge WR_CLK) always @* begin if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; else wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end // always @* end // wdc_fwft_ext endgenerate //*************************************************************************** // Generate RD_DATA_COUNT if Use Extra Logic option is selected //*************************************************************************** reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; always @* begin if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin adjusted_wr_pntr_rd = 0; adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; end else begin adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end end // always @* assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) begin rdc_fwft_ext_as <= 0; end else begin if (!stage2_valid) rdc_fwft_ext_as <= #`TCQ 0; else if (!stage1_valid && stage2_valid) rdc_fwft_ext_as <= #`TCQ 1; else rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; end end // always @ (posedge WR_CLK or posedge WR_CLK) end // rdc_fwft_ext end endgenerate generate if (C_USE_EMBEDDED_REG == 3) begin if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; always @* begin if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin adjusted_wr_pntr_rd = 0; adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; end else begin adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end end // always @* assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1; // assign diff_rd_wr_1 = diff_rd_wr +2'h2; always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) begin rdc_fwft_ext_as <= #`TCQ 0; end else begin //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1))) // rdc_fwft_ext_as <= 1'b0; //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) // rdc_fwft_ext_as <= 1'b1; //else rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ; end end end end endgenerate //*************************************************************************** // Assign the read data count value only if it is selected, // otherwise output zeros. //*************************************************************************** generate if (C_HAS_RD_DATA_COUNT == 1) begin : grdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //*************************************************************************** // Assign the write data count value only if it is selected, // otherwise output zeros //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; end endgenerate /************************************************************************** * Assorted registers for delayed versions of signals **************************************************************************/ //Capture delayed version of valid generate if (C_HAS_VALID==1) begin : blockVL2 always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin valid_d1 <= 1'b0; valid_d2 <= 1'b0; end else begin valid_d1 <= #`TCQ valid_i; valid_d2 <= #`TCQ valid_d1; end // if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin // valid_d2 <= #`TCQ valid_d1; // end end end endgenerate //Capture delayed version of dout /************************************************************************** *embedded/fabric reg with no safety ckt **************************************************************************/ generate if (C_USE_EMBEDDED_REG < 3) begin always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout <= #`TCQ dout_reset_val; end // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) err_type_d1 <= #`TCQ 0; end else if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1 <= #`TCQ err_type; end end end endgenerate /************************************************************************** *embedded + fabric reg with no safety ckt **************************************************************************/ generate if (C_USE_EMBEDDED_REG == 3) begin always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout <= #`TCQ dout_reset_val; ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both <= #`TCQ err_type; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1 <= #`TCQ err_type_both; end end end end endgenerate /************************************************************************** * Overflow and Underflow Flag calculation * (handled separately because they don't support rst) **************************************************************************/ generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw always @(posedge WR_CLK) begin ideal_overflow <= #`TCQ WR_EN & FULL; end end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw always @(posedge WR_CLK) begin //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i); ideal_overflow <= #`TCQ WR_EN & (FULL ); end end endgenerate generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw always @(posedge RD_CLK) begin ideal_underflow <= #`TCQ EMPTY & RD_EN; end end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw always @(posedge RD_CLK) begin ideal_underflow <= #`TCQ (EMPTY) & RD_EN; //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN; end end endgenerate /************************************************************************** * Write/Read Pointer Synchronization **************************************************************************/ localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1; wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; genvar gss; generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst fifo_generator_v13_1_2_sync_stage #( .C_WIDTH (C_WR_PNTR_WIDTH) ) rd_stg_inst ( .RST (rd_rst_i), .CLK (RD_CLK), .DIN (wr_pntr_sync_stgs[gss-1]), .DOUT (wr_pntr_sync_stgs[gss]) ); fifo_generator_v13_1_2_sync_stage #( .C_WIDTH (C_RD_PNTR_WIDTH) ) wr_stg_inst ( .RST (wr_rst_i), .CLK (WR_CLK), .DIN (rd_pntr_sync_stgs[gss-1]), .DOUT (rd_pntr_sync_stgs[gss]) ); end endgenerate // Sync_stage_inst assign wr_pntr_sync_stgs[0] = wr_pntr_rd1; assign rd_pntr_sync_stgs[0] = rd_pntr_wr1; always@* begin wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; end /************************************************************************** * Write Domain Logic **************************************************************************/ reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0) wr_pntr <= 0; else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1) wr_pntr <= #`TCQ 0; end always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w /****** Reset fifo (case 1)***************************************/ if (wr_rst_i == 1'b1) begin num_wr_bits <= 0; next_num_wr_bits = 0; wr_ptr <= C_WR_DEPTH - 1; rd_ptr_wrclk <= C_RD_DEPTH - 1; ideal_wr_ack <= 0; ideal_wr_count <= 0; tmp_wr_listsize = 0; rd_ptr_wrclk_next <= 0; wr_pntr_rd1 <= 0; end else begin //wr_rst_i==0 wr_pntr_rd1 <= #`TCQ wr_pntr; //Determine the current number of words in the FIFO tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : num_wr_bits/C_DIN_WIDTH; rd_ptr_wrclk_next = rd_ptr; if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - rd_ptr_wrclk_next); end else begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); end //If this is a write, handle the write by adding the value // to the linked list, and updating all outputs appropriately if (WR_EN == 1'b1) begin if (FULL == 1'b1) begin //If the FIFO is full, do NOT perform the write, // update flags accordingly if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) begin //write unsuccessful - do not change contents //Do not acknowledge the write ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is one from full, but reporting full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-1) begin //No change to FIFO //Write not successful ideal_wr_ack <= #`TCQ 0; //With DEPTH-1 words in the FIFO, it is almost_full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is completely empty, but it is // reporting FULL for some reason (like reset) end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= C_FIFO_WR_DEPTH-2) begin //No change to FIFO //Write not successful ideal_wr_ack <= #`TCQ 0; //FIFO is really not close to full, so change flag status. ideal_wr_count <= #`TCQ num_write_words_sized_i; end //(tmp_wr_listsize == 0) end else begin //If the FIFO is full, do NOT perform the write, // update flags accordingly if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) begin //write unsuccessful - do not change contents //Do not acknowledge the write ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is one from full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-1) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //This write is CAUSING the FIFO to go full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is 2 from full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-2) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Still 2 from full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is not close to being full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < C_FIFO_WR_DEPTH-2) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Not even close to full. ideal_wr_count <= num_write_words_sized_i; end end end else begin //(WR_EN == 1'b1) //If user did not attempt a write, then do not // give ack or err ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ num_write_words_sized_i; end num_wr_bits <= #`TCQ next_num_wr_bits; rd_ptr_wrclk <= #`TCQ rd_ptr; end //wr_rst_i==0 end // gen_fifo_w /*************************************************************************** * Programmable FULL flags ***************************************************************************/ wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val; wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val; generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; end else begin // STD assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL; assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL; end endgenerate always @(posedge WR_CLK or posedge wr_rst_i) begin if (wr_rst_i == 1'b1) begin diff_pntr <= 0; end else begin if (ram_wr_en) diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); else if (!ram_wr_en) diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); end end always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf if (RST_FULL_FF == 1'b1) begin ideal_prog_full <= C_FULL_FLAGS_RST_VAL; end else begin if (RST_FULL_GEN) ideal_prog_full <= #`TCQ 0; //Single Programmable Full Constant Threshold else if (C_PROG_FULL_TYPE == 1) begin if (FULL == 0) begin if (diff_pntr >= pf_thr_assert_val) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end else ideal_prog_full <= #`TCQ ideal_prog_full; //Two Programmable Full Constant Thresholds end else if (C_PROG_FULL_TYPE == 2) begin if (FULL == 0) begin if (diff_pntr >= pf_thr_assert_val) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < pf_thr_negate_val) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end else ideal_prog_full <= #`TCQ ideal_prog_full; //Single Programmable Full Threshold Input end else if (C_PROG_FULL_TYPE == 3) begin if (FULL == 0) begin if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end else begin // STD if (diff_pntr >= PROG_FULL_THRESH) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end end else ideal_prog_full <= #`TCQ ideal_prog_full; //Two Programmable Full Threshold Inputs end else if (C_PROG_FULL_TYPE == 4) begin if (FULL == 0) begin if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end else begin // STD if (diff_pntr >= PROG_FULL_THRESH_ASSERT) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < PROG_FULL_THRESH_NEGATE) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end end else ideal_prog_full <= #`TCQ ideal_prog_full; end // C_PROG_FULL_TYPE end //wr_rst_i==0 end // /************************************************************************** * Read Domain Logic **************************************************************************/ /********************************************************* * Programmable EMPTY flags *********************************************************/ //Determine the Assert and Negate thresholds for Programmable Empty wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val; wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val; reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe if (rd_rst_i) begin diff_pntr_rd <= 0; ideal_prog_empty <= 1'b1; end else begin if (ram_rd_en) diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; else if (!ram_rd_en) diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); else diff_pntr_rd <= #`TCQ diff_pntr_rd; if (C_PROG_EMPTY_TYPE == 1) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else ideal_prog_empty <= #`TCQ 0; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 2) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else if (diff_pntr_rd > pe_thr_negate_val) ideal_prog_empty <= #`TCQ 0; else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 3) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else ideal_prog_empty <= #`TCQ 0; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 4) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else if (diff_pntr_rd > pe_thr_negate_val) ideal_prog_empty <= #`TCQ 0; else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end //C_PROG_EMPTY_TYPE end end // gen_pe generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH; end endgenerate // single_pe_thr_input generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT; assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE; end endgenerate // multiple_pe_thr_input generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL; assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL; end endgenerate // single_multiple_pe_thr_const always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp if (rd_rst_i && C_EN_SAFETY_CKT == 0) rd_pntr <= 0; else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1) rd_pntr <= #`TCQ 0; end always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as /****** Reset fifo (case 1)***************************************/ if (rd_rst_i) begin num_rd_bits <= 0; next_num_rd_bits = 0; rd_ptr <= C_RD_DEPTH -1; rd_pntr_wr1 <= 0; wr_ptr_rdclk <= C_WR_DEPTH -1; // DRAM resets asynchronously if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) ideal_dout <= dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= 0; err_type_d1 <= 0; err_type_both <= 0; end ideal_valid <= 1'b0; ideal_rd_count <= 0; end else begin //rd_rst_i==0 rd_pntr_wr1 <= #`TCQ rd_pntr; //Determine the current number of words in the FIFO tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : num_rd_bits/C_DOUT_WIDTH; wr_ptr_rdclk_next = wr_ptr; if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - wr_ptr_rdclk_next); end else begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); end /*****************************************************************/ // Read Operation - Read Latency 1 /*****************************************************************/ if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin ideal_valid <= #`TCQ 1'b0; if (ram_rd_en == 1'b1) begin if (EMPTY == 1'b1) begin //If the FIFO is completely empty, and is reporting empty if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) //If the FIFO is one from empty, but it is reporting empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that FIFO is no longer empty, but is almost empty (has one word left) ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 1) //If the FIFO is two from empty, and is reporting empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Fifo has two words, so is neither empty or almost empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) //If the FIFO is not close to empty, but is reporting that it is // Treat the FIFO as empty this time, but unset EMPTY flags. if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) end // else: if(ideal_empty == 1'b1) else //if (ideal_empty == 1'b0) begin //If the FIFO is completely full, and we are successfully reading from it if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) //If the FIFO is not close to being empty else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) //If the FIFO is two from empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Fifo is not yet empty. It is going almost_empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) //If the FIFO is one from empty else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Note that FIFO is GOING empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 1) //If the FIFO is completely empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) end // if (ideal_empty == 1'b0) end //(RD_EN == 1'b1) else //if (RD_EN == 1'b0) begin //If user did not attempt a read, do not give an ack or err ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // else: !if(RD_EN == 1'b1) /*****************************************************************/ // Read Operation - Read Latency 0 /*****************************************************************/ end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin ideal_valid <= #`TCQ 1'b0; if (ram_rd_en == 1'b1) begin if (EMPTY == 1'b1) begin //If the FIFO is completely empty, and is reporting empty if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is one from empty, but it is reporting empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that FIFO is no longer empty, but is almost empty (has one word left) ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is two from empty, and is reporting empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Fifo has two words, so is neither empty or almost empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is not close to empty, but is reporting that it is // Treat the FIFO as empty this time, but unset EMPTY flags. end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) end else begin //If the FIFO is completely full, and we are successfully reading from it if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is not close to being empty end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is two from empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Fifo is not yet empty. It is going almost_empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is one from empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Note that FIFO is GOING empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is completely empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) end // if (ideal_empty == 1'b0) end else begin//(RD_EN == 1'b0) //If user did not attempt a read, do not give an ack or err ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // else: !if(RD_EN == 1'b1) end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) num_rd_bits <= #`TCQ next_num_rd_bits; wr_ptr_rdclk <= #`TCQ wr_ptr; end //rd_rst_i==0 end //always gen_fifo_r_as endmodule // fifo_generator_v13_1_2_bhv_ver_as /******************************************************************************* * Declaration of Low Latency Asynchronous FIFO ******************************************************************************/ module fifo_generator_v13_1_2_beh_ver_ll_afifo /*************************************************************************** * Declare user parameters and their defaults ***************************************************************************/ #( parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_USE_DOUT_RST = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_FIFO_TYPE = 0 ) /*************************************************************************** * Declare Input and Output Ports ***************************************************************************/ ( input [C_DIN_WIDTH-1:0] DIN, input RD_CLK, input RD_EN, input WR_RST, input RD_RST, input WR_CLK, input WR_EN, output reg [C_DOUT_WIDTH-1:0] DOUT = 0, output reg EMPTY = 1'b1, output reg FULL = C_FULL_FLAGS_RST_VAL ); //----------------------------------------------------------------------------- // Low Latency Asynchronous FIFO //----------------------------------------------------------------------------- // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; integer i; initial begin for (i = 0; i < C_WR_DEPTH; i = i + 1) memory[i] = 0; end reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0; wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0; reg ll_afifo_full = 1'b0; reg ll_afifo_empty = 1'b1; wire write_allow; wire read_allow; assign write_allow = WR_EN & ~ll_afifo_full; assign read_allow = RD_EN & ~ll_afifo_empty; //----------------------------------------------------------------------------- // Write Pointer Generation //----------------------------------------------------------------------------- always @(posedge WR_CLK or posedge WR_RST) begin if (WR_RST) wr_pntr_ll_afifo <= 0; else if (write_allow) wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1; end //----------------------------------------------------------------------------- // Read Pointer Generation //----------------------------------------------------------------------------- always @(posedge RD_CLK or posedge RD_RST) begin if (RD_RST) rd_pntr_ll_afifo_q <= 0; else rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo; end assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q; //----------------------------------------------------------------------------- // Fill the Memory //----------------------------------------------------------------------------- always @(posedge WR_CLK) begin if (write_allow) memory[wr_pntr_ll_afifo] <= #`TCQ DIN; end //----------------------------------------------------------------------------- // Generate DOUT //----------------------------------------------------------------------------- always @(posedge RD_CLK) begin DOUT <= #`TCQ memory[rd_pntr_ll_afifo]; end //----------------------------------------------------------------------------- // Generate EMPTY //----------------------------------------------------------------------------- always @(posedge RD_CLK or posedge RD_RST) begin if (RD_RST) ll_afifo_empty <= 1'b1; else ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1)))); end //----------------------------------------------------------------------------- // Generate FULL //----------------------------------------------------------------------------- always @(posedge WR_CLK or posedge WR_RST) begin if (WR_RST) ll_afifo_full <= 1'b1; else ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2)))); end always @* begin FULL <= ll_afifo_full; EMPTY <= ll_afifo_empty; end endmodule // fifo_generator_v13_1_2_beh_ver_ll_afifo /******************************************************************************* * Declaration of top-level module ******************************************************************************/ module fifo_generator_v13_1_2_bhv_ver_ss /************************************************************************** * Declare user parameters and their defaults *************************************************************************/ #( parameter C_FAMILY = "virtex7", parameter C_DATA_COUNT_WIDTH = 2, parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RST = 0, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_MEMORY_TYPE = 1, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_USE_ECC = 0, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_FIFO_TYPE = 0 ) /************************************************************************** * Declare Input and Output Ports *************************************************************************/ ( //Inputs input SAFETY_CKT_WR_RST, input CLK, input [C_DIN_WIDTH-1:0] DIN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input RD_EN, input RD_EN_USER, input USER_EMPTY_FB, input RST, input RST_FULL_GEN, input RST_FULL_FF, input SRST, input WR_EN, input INJECTDBITERR, input INJECTSBITERR, input WR_RST_BUSY, input RD_RST_BUSY, //Outputs output ALMOST_EMPTY, output ALMOST_FULL, output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0, output [C_DOUT_WIDTH-1:0] DOUT, output EMPTY, output reg EMPTY_FB = 1'b1, output FULL, output OVERFLOW, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output PROG_EMPTY, output PROG_FULL, output VALID, output UNDERFLOW, output WR_ACK, output SBITERR, output DBITERR ); reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss; wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss; reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; /*************************************************************************** * Parameters used as constants **************************************************************************/ localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; localparam C_DEPTH_RATIO_WR = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; localparam C_DEPTH_RATIO_RD = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC // -----------------|------------------|-----------------|--------------- // 1 | 8 | C_RD_PNTR_WIDTH | 2 // 1 | 4 | C_RD_PNTR_WIDTH | 2 // 1 | 2 | C_RD_PNTR_WIDTH | 2 // 1 | 1 | C_WR_PNTR_WIDTH | 2 // 2 | 1 | C_WR_PNTR_WIDTH | 4 // 4 | 1 | C_WR_PNTR_WIDTH | 8 // 8 | 1 | C_WR_PNTR_WIDTH | 16 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); //When RST is present, set FULL reset value to '1'. //If core has no RST, make sure FULL powers-on as '0'. //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. // Therefore, during SRST, all the FULL flags reset to 0. localparam C_HAS_FAST_FIFO = 0; localparam C_FIFO_WR_DEPTH = C_WR_DEPTH; localparam C_FIFO_RD_DEPTH = C_RD_DEPTH; // Local parameters used to determine whether to inject ECC error or not localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH; localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1; localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; /************************************************************************** * FIFO Contents Tracking and Data Count Calculations *************************************************************************/ // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; reg [1:0] ecc_err[C_WR_DEPTH-1:0]; /************************************************************************** * Internal Registers and wires *************************************************************************/ //Temporary signals used for calculating the model's outputs. These //are only used in the assign statements immediately following wire, //parameter, and function declarations. wire underflow_i; wire valid_i; wire valid_out; reg [31:0] num_wr_bits; reg [31:0] num_rd_bits; reg [31:0] next_num_wr_bits; reg [31:0] next_num_rd_bits; //The write pointer - tracks write operations // (Works opposite to core: wr_ptr is a DOWN counter) reg [31:0] wr_ptr; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; reg wr_rst_d1 =0; //The read pointer - tracks read operations // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) reg [31:0] rd_ptr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; wire ram_rd_en; wire empty_int; wire almost_empty_int; wire ram_wr_en; wire full_int; wire almost_full_int; reg ram_rd_en_reg = 1'b0; reg ram_rd_en_d1 = 1'b0; reg fab_rd_en_d1 = 1'b0; wire srst_rrst_busy; //Ideal FIFO signals. These are the raw output of the behavioral model, //which behaves like an ideal FIFO. reg [1:0] err_type = 0; reg [1:0] err_type_d1 = 0; reg [1:0] err_type_both = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; wire [C_DOUT_WIDTH-1:0] ideal_dout_out; wire fwft_enabled; reg ideal_wr_ack = 0; reg ideal_valid = 0; reg ideal_overflow = C_OVERFLOW_LOW; reg ideal_underflow = C_UNDERFLOW_LOW; reg full_i = C_FULL_FLAGS_RST_VAL; reg full_i_temp = 0; reg empty_i = 1; reg almost_full_i = 0; reg almost_empty_i = 1; reg prog_full_i = 0; reg prog_empty_i = 1; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0; reg write_allow_q = 0; reg read_allow_q = 0; reg valid_d1 = 0; reg valid_both = 0; reg valid_d2 = 0; wire rst_i; wire srst_i; //user specified value for reseting the size of the fifo reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; reg [31:0] wr_ptr_rdclk; reg [31:0] wr_ptr_rdclk_next; reg [31:0] rd_ptr_wrclk; reg [31:0] rd_ptr_wrclk_next; /**************************************************************************** * Function Declarations ***************************************************************************/ /**************************************************************************** * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***************************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction /************************************************************************** * log2_val * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function [31:0] log2_val; input [31:0] binary_val; begin if (binary_val == 8) begin log2_val = 3; end else if (binary_val == 4) begin log2_val = 2; end else begin log2_val = 1; end end endfunction reg ideal_prog_full = 0; reg ideal_prog_empty = 1; reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; //Assorted reg values for delayed versions of signals //reg valid_d1 = 0; //user specified value for reseting the size of the fifo //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; //temporary registers for WR_RESPONSE_LATENCY feature integer tmp_wr_listsize; integer tmp_rd_listsize; //Signal for registered version of prog full and empty //Threshold values for Programmable Flags integer prog_empty_actual_thresh_assert; integer prog_empty_actual_thresh_negate; integer prog_full_actual_thresh_assert; integer prog_full_actual_thresh_negate; /************************************************************************** * write_fifo * This task writes a word to the FIFO memory and updates the * write pointer. * FIFO size is relative to write domain. ***************************************************************************/ task write_fifo; begin memory[wr_ptr] <= DIN; wr_pntr <= #`TCQ wr_pntr + 1; // Store the type of error injection (double/single) on write case (C_ERROR_INJECTION_TYPE) 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; default: ecc_err[wr_ptr] <= 0; endcase // (Works opposite to core: wr_ptr is a DOWN counter) if (wr_ptr == 0) begin wr_ptr <= C_WR_DEPTH - 1; end else begin wr_ptr <= wr_ptr - 1; end end endtask // write_fifo /************************************************************************** * read_fifo * This task reads a word from the FIFO memory and updates the read * pointer. It's output is the ideal_dout bus. * FIFO size is relative to write domain. ***************************************************************************/ task read_fifo; integer i; reg [C_DOUT_WIDTH-1:0] tmp_dout; reg [C_DIN_WIDTH-1:0] memory_read; reg [31:0] tmp_rd_ptr; reg [31:0] rd_ptr_high; reg [31:0] rd_ptr_low; reg [1:0] tmp_ecc_err; begin rd_pntr <= #`TCQ rd_pntr + 1; // output is wider than input if (reads_per_write == 0) begin tmp_dout = 0; tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); for (i = writes_per_read - 1; i >= 0; i = i - 1) begin tmp_dout = tmp_dout << C_DIN_WIDTH; tmp_dout = tmp_dout | memory[tmp_rd_ptr]; // (Works opposite to core: rd_ptr is a DOWN counter) if (tmp_rd_ptr == 0) begin tmp_rd_ptr = C_WR_DEPTH - 1; end else begin tmp_rd_ptr = tmp_rd_ptr - 1; end end // output is symmetric end else if (reads_per_write == 1) begin tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; // Retreive the error injection type. Based on the error injection type // corrupt the output data. tmp_ecc_err = ecc_err[rd_ptr]; if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error if (C_DOUT_WIDTH == 1) begin $display("FAILURE : Data width must be >= 2 for double bit error injection."); $finish; end else if (C_DOUT_WIDTH == 2) tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; else tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; end else begin tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; end err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; end else begin err_type <= 0; end // input is wider than output end else begin rd_ptr_high = rd_ptr >> log2_reads_per_write; rd_ptr_low = rd_ptr & (reads_per_write - 1); memory_read = memory[rd_ptr_high]; tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); end ideal_dout <= tmp_dout; // (Works opposite to core: rd_ptr is a DOWN counter) if (rd_ptr == 0) begin rd_ptr <= C_RD_DEPTH - 1; end else begin rd_ptr <= rd_ptr - 1; end end endtask /************************************************************************* * Initialize Signals for clean power-on simulation *************************************************************************/ initial begin num_wr_bits = 0; num_rd_bits = 0; next_num_wr_bits = 0; next_num_rd_bits = 0; rd_ptr = C_RD_DEPTH - 1; wr_ptr = C_WR_DEPTH - 1; wr_pntr = 0; rd_pntr = 0; rd_ptr_wrclk = rd_ptr; wr_ptr_rdclk = wr_ptr; dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); ideal_dout = dout_reset_val; err_type = 0; err_type_d1 = 0; err_type_both = 0; ideal_dout_d1 = dout_reset_val; ideal_dout_both = dout_reset_val; ideal_wr_ack = 1'b0; ideal_valid = 1'b0; valid_d1 = 1'b0; valid_both = 1'b0; ideal_overflow = C_OVERFLOW_LOW; ideal_underflow = C_UNDERFLOW_LOW; ideal_wr_count = 0; ideal_rd_count = 0; ideal_prog_full = 1'b0; ideal_prog_empty = 1'b1; end /************************************************************************* * Connect the module inputs and outputs to the internal signals of the * behavioral model. *************************************************************************/ //Inputs /* wire CLK; wire [C_DIN_WIDTH-1:0] DIN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire RD_EN; wire RST; wire WR_EN; */ // Assign ALMOST_EPMTY generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae assign ALMOST_EMPTY = almost_empty_i; end else begin : gnae assign ALMOST_EMPTY = 0; end endgenerate // gae // Assign ALMOST_FULL generate if (C_HAS_ALMOST_FULL==1) begin : gaf assign ALMOST_FULL = almost_full_i; end else begin : gnaf assign ALMOST_FULL = 0; end endgenerate // gaf // Dout may change behavior based on latency localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 1: 0; assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 1: 0; assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? ideal_dout_d1: ideal_dout; assign DOUT = ideal_dout_out; // Assign SBITERR and DBITERR based on latency assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[0]: err_type[0]; assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[1]: err_type[1]; assign EMPTY = empty_i; assign FULL = full_i; //saftey_ckt with one register generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge CLK) begin rst_delayed_sft1 <= #`TCQ rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; valid_d1 <= #`TCQ 1'b0; end else begin ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); valid_d1 <= #`TCQ valid_i; end end always@(posedge rst_delayed_sft2 or posedge CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (srst_rrst_busy == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1[0] <= #`TCQ err_type[0]; err_type_d1[1] <= #`TCQ err_type[1]; end end end //if endgenerate //safety ckt with both registers generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge CLK) begin rst_delayed_sft1 <= #`TCQ rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; valid_d1 <= #`TCQ 1'b0; end else begin ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; valid_both <= #`TCQ valid_i; valid_d1 <= #`TCQ valid_both; end end always@(posedge rst_delayed_sft2 or posedge CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (srst_rrst_busy == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both[0] <= #`TCQ err_type[0]; err_type_both[1] <= #`TCQ err_type[1]; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1[0] <= #`TCQ err_type_both[0]; err_type_d1[1] <= #`TCQ err_type_both[1]; end end end end //if endgenerate //Overflow may be active-low generate if (C_HAS_OVERFLOW==1) begin : gof assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; end else begin : gnof assign OVERFLOW = 0; end endgenerate // gof assign PROG_EMPTY = prog_empty_i; assign PROG_FULL = prog_full_i; //Valid may change behavior based on latency or active-low generate if (C_HAS_VALID==1) begin : gvalid assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid; assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ? valid_d1 : valid_i; assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; end else begin : gnvalid assign VALID = 0; end endgenerate // gvalid //Trim data count differently depending on set widths generate if (C_HAS_DATA_COUNT == 1) begin : gdc always @* begin diff_count <= wr_pntr - rd_pntr; if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count; DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; end else begin DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; end end // end else begin : gndc // always @* DATA_COUNT <= 0; end endgenerate // gdc //Underflow may change behavior based on latency or active-low generate if (C_HAS_UNDERFLOW==1) begin : guf assign underflow_i = ideal_underflow; assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; end else begin : gnuf assign UNDERFLOW = 0; end endgenerate // guf //Write acknowledge may be active low generate if (C_HAS_WR_ACK==1) begin : gwr_ack assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; end else begin : gnwr_ack assign WR_ACK = 0; end endgenerate // gwr_ack /***************************************************************************** * Internal reset logic ****************************************************************************/ assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0; assign rst_i = C_HAS_RST ? RST : 0; assign srst_wrst_busy = srst_i; assign srst_rrst_busy = srst_i; /************************************************************************** * Assorted registers for delayed versions of signals **************************************************************************/ //Capture delayed version of valid generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20 always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin valid_d1 <= 1'b0; end else begin if (srst_rrst_busy) begin valid_d1 <= #`TCQ 1'b0; end else begin valid_d1 <= #`TCQ valid_i; end end end // always @ (posedge CLK or posedge rst_i) end endgenerate // blockVL20 generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin valid_d1 <= 1'b0; valid_both <= 1'b0; end else begin if (srst_rrst_busy) begin valid_d1 <= #`TCQ 1'b0; valid_both <= #`TCQ 1'b0; end else begin valid_both <= #`TCQ valid_i; valid_d1 <= #`TCQ valid_both; end end end // always @ (posedge CLK or posedge rst_i) end endgenerate // blockVL20 // Determine which stage in FWFT registers are valid reg stage1_valid = 0; reg stage2_valid = 0; generate if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc always @ (posedge CLK or posedge rst_i) begin if (rst_i) begin stage1_valid <= #`TCQ 0; stage2_valid <= #`TCQ 0; end else begin if (!stage1_valid && !stage2_valid) begin if (!EMPTY) stage1_valid <= #`TCQ 1'b1; else stage1_valid <= #`TCQ 1'b0; end else if (stage1_valid && !stage2_valid) begin if (EMPTY) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else if (!stage1_valid && stage2_valid) begin if (EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && !RD_EN) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end end else if (stage1_valid && stage2_valid) begin if (EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end end // rd_rst_i end // always end endgenerate //*************************************************************************** // Assign the read data count value only if it is selected, // otherwise output zeros. //*************************************************************************** generate if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //*************************************************************************** // Assign the write data count value only if it is selected, // otherwise output zeros //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ; end endgenerate generate if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //reg ram_rd_en_d1 = 1'b0; //Capture delayed version of dout generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // DRAM and SRAM reset asynchronously if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end ram_rd_en_d1 <= #`TCQ 1'b0; if (C_USE_DOUT_RST == 1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; if (srst_rrst_busy) begin ram_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin // @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1 ) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1 <= #`TCQ err_type; end end end end // always end endgenerate //no safety ckt with both registers generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; fab_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // DRAM and SRAM reset asynchronously if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end else begin if (srst_rrst_busy) begin ram_rd_en_d1 <= #`TCQ 1'b0; fab_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1); if (ram_rd_en_d1 ) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both <= #`TCQ err_type; end if (fab_rd_en_d1 ) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1 <= #`TCQ err_type_both; end end end end // always end endgenerate /************************************************************************** * Overflow and Underflow Flag calculation * (handled separately because they don't support rst) **************************************************************************/ generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw always @(posedge CLK) begin ideal_overflow <= #`TCQ WR_EN & full_i; end end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw always @(posedge CLK) begin //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i); ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i); end end endgenerate // blockOF20 generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw always @(posedge CLK) begin ideal_underflow <= #`TCQ empty_i & RD_EN; end end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw always @(posedge CLK) begin //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN; ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN; end end endgenerate // blockUF20 /************************** * Read Data Count *************************/ reg [31:0] num_read_words_dc; reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; always @(num_rd_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //If using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain, // and add two read words for FWFT stages //This value is only a temporary value and not used in the code. num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; end else begin //If not using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain. //This value is only a temporary value and not used in the code. num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************** * Write Data Count *************************/ reg [31:0] num_write_words_dc; reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; always @(num_wr_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //Calculate the Data Count value for the number of write words, // when using First-Word Fall-Through with extra logic for Data // Counts. This takes into consideration the number of words that // are expected to be stored in the FWFT register stages (it always // assumes they are filled). //This value is scaled to the Write Domain. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //When num_wr_bits==0, set the result manually to prevent // division errors. //EXTRA_WORDS_DC is the number of words added to write_words // due to FWFT. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; //Trim the write words for use with WR_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; end else begin //Calculate the Data Count value for the number of write words, when NOT // using First-Word Fall-Through with extra logic for Data Counts. This // calculates only the number of words in the internal FIFO. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //This value is scaled to the Write Domain. //When num_wr_bits==0, set the result manually to prevent // division errors. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; //Trim the read words for use with RD_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************************************************************* * Write and Read Logic ************************************************************************/ wire write_allow; wire read_allow; wire read_allow_dc; wire write_only; wire read_only; //wire write_only_q; reg write_only_q; //wire read_only_q; reg read_only_q; reg full_reg; reg rst_full_ff_reg1; reg rst_full_ff_reg2; wire ram_full_comb; wire carry; assign write_allow = WR_EN & ~full_i; assign read_allow = RD_EN & ~empty_i; assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB; //assign write_only = write_allow & ~read_allow; //assign write_only_q = write_allow_q; //assign read_only = read_allow & ~write_allow; //assign read_only_q = read_allow_q ; wire [C_WR_PNTR_WIDTH-1:0] diff_pntr; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0; reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0; reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0; wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ; wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max; assign diff_pntr_pe_max = DIFF_MAX_RD; assign diff_pntr_max = DIFF_MAX_WR; generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym assign write_only = write_allow & ~read_allow; assign read_only = read_allow & ~write_allow; end endgenerate generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow; assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])); end endgenerate generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow; end endgenerate //----------------------------------------------------------------------------- // Write and Read pointer generation //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i && C_EN_SAFETY_CKT == 0) begin wr_pntr <= 0; rd_pntr <= 0; end else begin if (srst_i) begin wr_pntr <= #`TCQ 0; rd_pntr <= #`TCQ 0; end else begin if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1; if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1; end end end generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout always @(posedge CLK) begin if (write_allow) begin if (ENABLE_ERR_INJECTION == 1) memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN}; else memory[wr_pntr] <= #`TCQ DIN; end end reg [C_DATA_WIDTH-1:0] dout_tmp_q; reg [C_DATA_WIDTH-1:0] dout_tmp = 0; reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0; always @(posedge CLK) begin dout_tmp_q <= #`TCQ ideal_dout; end always @* begin if (read_allow) ideal_dout <= memory[rd_pntr]; else ideal_dout <= dout_tmp_q; end end endgenerate // gll_dm_dout /************************************************************************** * Write Domain Logic **************************************************************************/ assign ram_rd_en = RD_EN & !EMPTY; //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; generate if (C_FIFO_TYPE != 2) begin : gnll_din always @(posedge CLK or posedge rst_i) begin : gen_fifo_w /****** Reset fifo (case 1)***************************************/ if (rst_i == 1'b1) begin num_wr_bits <= #`TCQ 0; next_num_wr_bits = #`TCQ 0; wr_ptr <= #`TCQ C_WR_DEPTH - 1; rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ 0; tmp_wr_listsize = #`TCQ 0; rd_ptr_wrclk_next <= #`TCQ 0; wr_pntr <= #`TCQ 0; wr_pntr_rd1 <= #`TCQ 0; end else begin //rst_i==0 if (srst_wrst_busy) begin num_wr_bits <= #`TCQ 0; next_num_wr_bits = #`TCQ 0; wr_ptr <= #`TCQ C_WR_DEPTH - 1; rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ 0; tmp_wr_listsize = #`TCQ 0; rd_ptr_wrclk_next <= #`TCQ 0; wr_pntr <= #`TCQ 0; wr_pntr_rd1 <= #`TCQ 0; end else begin//srst_i=0 wr_pntr_rd1 <= #`TCQ wr_pntr; //Determine the current number of words in the FIFO tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : num_wr_bits/C_DIN_WIDTH; rd_ptr_wrclk_next = rd_ptr; if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - rd_ptr_wrclk_next); end else begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); end if (WR_EN == 1'b1) begin if (FULL == 1'b1) begin ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; end else begin write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Not even close to full. ideal_wr_count <= num_write_words_sized_i; //end end end else begin //(WR_EN == 1'b1) //If user did not attempt a write, then do not // give ack or err ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ num_write_words_sized_i; end num_wr_bits <= #`TCQ next_num_wr_bits; rd_ptr_wrclk <= #`TCQ rd_ptr; end //srst_i==0 end //wr_rst_i==0 end // gen_fifo_w end endgenerate generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout always @(posedge CLK) begin if (rst_i || srst_rrst_busy) begin if (C_USE_DOUT_RST == 1) begin ideal_dout <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end end end endgenerate generate if (C_FIFO_TYPE != 2) begin : gnll_dout always @(posedge CLK or posedge rst_i) begin : gen_fifo_r /****** Reset fifo (case 1)***************************************/ if (rst_i) begin num_rd_bits <= #`TCQ 0; next_num_rd_bits = #`TCQ 0; rd_ptr <= #`TCQ C_RD_DEPTH -1; rd_pntr <= #`TCQ 0; //rd_pntr_wr1 <= #`TCQ 0; wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; // DRAM resets asynchronously if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) ideal_dout <= #`TCQ dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= #`TCQ 0; err_type_d1 <= 0; err_type_both <= 0; end ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ 0; end else begin //rd_rst_i==0 if (srst_rrst_busy) begin num_rd_bits <= #`TCQ 0; next_num_rd_bits = #`TCQ 0; rd_ptr <= #`TCQ C_RD_DEPTH -1; rd_pntr <= #`TCQ 0; //rd_pntr_wr1 <= #`TCQ 0; wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; // DRAM resets synchronously if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) ideal_dout <= #`TCQ dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= #`TCQ 0; err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ 0; end //srst_i else begin //rd_pntr_wr1 <= #`TCQ rd_pntr; //Determine the current number of words in the FIFO tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : num_rd_bits/C_DOUT_WIDTH; wr_ptr_rdclk_next = wr_ptr; if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - wr_ptr_rdclk_next); end else begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); end if (RD_EN == 1'b1) begin if (EMPTY == 1'b1) begin ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end else begin read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) end num_rd_bits <= #`TCQ next_num_rd_bits; wr_ptr_rdclk <= #`TCQ wr_ptr; end //s_rst_i==0 end //rd_rst_i==0 end //always end endgenerate //----------------------------------------------------------------------------- // Generate diff_pntr for PROG_FULL generation // Generate diff_pntr_pe for PROG_EMPTY generation //----------------------------------------------------------------------------- generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow always @(posedge CLK ) begin if (rst_i) begin write_only_q <= 1'b0; read_only_q <= 1'b0; diff_pntr_reg1 <= 0; diff_pntr_pe_reg1 <= 0; diff_pntr_reg2 <= 0; diff_pntr_pe_reg2 <= 0; end else begin if (srst_i || srst_wrst_busy || srst_rrst_busy) begin if (srst_rrst_busy) begin read_only_q <= #`TCQ 1'b0; diff_pntr_pe_reg1 <= #`TCQ 0; diff_pntr_pe_reg2 <= #`TCQ 0; end if (srst_wrst_busy) begin write_only_q <= #`TCQ 1'b0; diff_pntr_reg1 <= #`TCQ 0; diff_pntr_reg2 <= #`TCQ 0; end end else begin write_only_q <= #`TCQ write_only; read_only_q <= #`TCQ read_only; diff_pntr_reg2 <= #`TCQ diff_pntr_reg1; diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1; // Add 1 to the difference pointer value when only write happens. if (write_only) diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1; else diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; // Add 1 to the difference pointer value when write or both write & read or no write & read happen. if (read_only) diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1; else diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr; end end end assign diff_pntr_pe = diff_pntr_pe_reg1; assign diff_pntr = diff_pntr_reg1; end endgenerate // reg_write_allow generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1}; assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1}; always @(posedge CLK ) begin if (rst_i) begin diff_pntr_pe_asym <= 0; diff_pntr_reg1 <= 0; full_reg <= 0; rst_full_ff_reg1 <= 1; rst_full_ff_reg2 <= 1; diff_pntr_pe_reg1 <= 0; end else begin if (srst_i || srst_wrst_busy || srst_rrst_busy) begin if (srst_wrst_busy) diff_pntr_reg1 <= #`TCQ 0; if (srst_rrst_busy) full_reg <= #`TCQ 0; rst_full_ff_reg1 <= #`TCQ 1; rst_full_ff_reg2 <= #`TCQ 1; diff_pntr_pe_asym <= #`TCQ 0; diff_pntr_pe_reg1 <= #`TCQ 0; end else begin diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym; full_reg <= #`TCQ full_i; rst_full_ff_reg1 <= #`TCQ RST_FULL_FF; rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1; if (~full_i) begin diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; end end end end assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1]))); assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1]; assign diff_pntr = diff_pntr_reg1; end endgenerate // reg_write_allow_asym //----------------------------------------------------------------------------- // Generate FULL flag //----------------------------------------------------------------------------- wire comp0; wire comp1; wire going_full; wire leaving_full; generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr; assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0; end endgenerate generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1)); assign comp0 = (adj_rd_pntr_wr == wr_pntr); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp assign going_full = (comp1 & write_allow & ~read_allow); assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN; end endgenerate // Write data width is bigger than read data width // Write depth is smaller than read depth // One write could be equal to 2 or 4 or 8 reads generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp assign going_full = (comp1 & write_allow & ~read_allow); assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN; end endgenerate assign ram_full_comb = going_full | (~leaving_full & full_i); always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) full_i <= C_FULL_FLAGS_RST_VAL; else if (srst_wrst_busy) full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else full_i <= #`TCQ ram_full_comb; end //----------------------------------------------------------------------------- // Generate EMPTY flag //----------------------------------------------------------------------------- wire ecomp0; wire ecomp1; wire going_empty; wire leaving_empty; wire ram_empty_comb; generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0; end endgenerate generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1)); assign ecomp0 = (adj_wr_pntr_rd == rd_pntr); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp assign going_empty = (ecomp1 & ~write_allow & read_allow); assign leaving_empty = (ecomp0 & write_allow); end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); end endgenerate generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp assign going_empty = (ecomp1 & ~write_allow & read_allow); assign leaving_empty =(ecomp0 & write_allow); end endgenerate assign ram_empty_comb = going_empty | (~leaving_empty & empty_i); always @(posedge CLK or posedge rst_i) begin if (rst_i) empty_i <= 1'b1; else if (srst_rrst_busy) empty_i <= #`TCQ 1'b1; else empty_i <= #`TCQ ram_empty_comb; end always @(posedge CLK or posedge rst_i) begin if (rst_i && C_EN_SAFETY_CKT == 0) begin EMPTY_FB <= 1'b1; end else begin if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT)) EMPTY_FB <= #`TCQ 1'b1; else EMPTY_FB <= #`TCQ ram_empty_comb; end end // always //----------------------------------------------------------------------------- // Generate Read and write data counts for asymmetic common clock //----------------------------------------------------------------------------- reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; wire [C_GRTR_PNTR_WIDTH :0] ratio; wire decr_by_one; wire incr_by_ratio; wire incr_by_one; wire decr_by_ratio; localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr assign ratio = C_DEPTH_RATIO_RD; assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow; assign incr_by_ratio = write_allow; always @(posedge CLK or posedge rst_i) begin if (rst_i) count_dc <= #`TCQ 0; else if (srst_wrst_busy) count_dc <= #`TCQ 0; else begin if (decr_by_one) begin if (!incr_by_ratio) count_dc <= #`TCQ count_dc - 1; else count_dc <= #`TCQ count_dc - 1 + ratio ; end else begin if (!incr_by_ratio) count_dc <= #`TCQ count_dc ; else count_dc <= #`TCQ count_dc + ratio ; end end end assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc; assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd assign ratio = C_DEPTH_RATIO_WR; assign incr_by_one = write_allow; assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow; always @(posedge CLK or posedge rst_i) begin if (rst_i) count_dc <= #`TCQ 0; else if (srst_wrst_busy) count_dc <= #`TCQ 0; else begin if (incr_by_one) begin if (!decr_by_ratio) count_dc <= #`TCQ count_dc + 1; else count_dc <= #`TCQ count_dc + 1 - ratio ; end else begin if (!decr_by_ratio) count_dc <= #`TCQ count_dc ; else count_dc <= #`TCQ count_dc - ratio ; end end end assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc; assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate //----------------------------------------------------------------------------- // Generate WR_ACK flag //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i) ideal_wr_ack <= 1'b0; else if (srst_wrst_busy) ideal_wr_ack <= #`TCQ 1'b0; else if (WR_EN & ~full_i) ideal_wr_ack <= #`TCQ 1'b1; else ideal_wr_ack <= #`TCQ 1'b0; end //----------------------------------------------------------------------------- // Generate VALID flag //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i) ideal_valid <= 1'b0; else if (srst_rrst_busy) ideal_valid <= #`TCQ 1'b0; else if (RD_EN & ~empty_i) ideal_valid <= #`TCQ 1'b1; else ideal_valid <= #`TCQ 1'b0; end //----------------------------------------------------------------------------- // Generate ALMOST_FULL flag //----------------------------------------------------------------------------- //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss wire fcomp2; wire going_afull; wire leaving_afull; wire ram_afull_comb; assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2)); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp assign going_afull = (fcomp2 & write_allow & ~read_allow); assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN; end endgenerate // Write data width is bigger than read data width // Write depth is smaller than read depth // One write could be equal to 2 or 4 or 8 reads generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp assign going_afull = (fcomp2 & write_allow & ~read_allow); assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN; end endgenerate assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i); always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) almost_full_i <= C_FULL_FLAGS_RST_VAL; else if (srst_wrst_busy) almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else almost_full_i <= #`TCQ ram_afull_comb; end // end endgenerate // gaf_ss //----------------------------------------------------------------------------- // Generate ALMOST_EMPTY flag //----------------------------------------------------------------------------- //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss wire ecomp2; wire going_aempty; wire leaving_aempty; wire ram_aempty_comb; assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2)); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp assign going_aempty = (ecomp2 & ~write_allow & read_allow); assign leaving_aempty = (ecomp1 & write_allow & ~read_allow); end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); end endgenerate generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp assign going_aempty = (ecomp2 & ~write_allow & read_allow); assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow); end endgenerate assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i); always @(posedge CLK or posedge rst_i) begin if (rst_i) almost_empty_i <= 1'b1; else if (srst_rrst_busy) almost_empty_i <= #`TCQ 1'b1; else almost_empty_i <= #`TCQ ram_aempty_comb; end // end endgenerate // gae_ss //----------------------------------------------------------------------------- // Generate PROG_FULL //----------------------------------------------------------------------------- localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT C_PROG_FULL_THRESH_ASSERT_VAL; // STD localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT C_PROG_FULL_THRESH_NEGATE_VAL; // STD //----------------------------------------------------------------------------- // Generate PROG_FULL for single programmable threshold constant //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~RST_FULL_GEN ) begin if (diff_pntr>= C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b1; else if ((diff_pntr) < C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ 1'b0; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate // single_pf_const //----------------------------------------------------------------------------- // Generate PROG_FULL for multiple programmable threshold constants //----------------------------------------------------------------------------- generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const always @(posedge CLK or posedge RST_FULL_FF) begin //if (RST_FULL_FF) if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~RST_FULL_GEN ) begin if (diff_pntr >= C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < C_PF_NEGATE_VAL) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate //multiple_pf_const //----------------------------------------------------------------------------- // Generate PROG_FULL for single programmable threshold input port //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT PROG_FULL_THRESH; // STD generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input always @(posedge CLK or posedge RST_FULL_FF) begin//0 //if (RST_FULL_FF) if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin //1 if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin//2 if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~almost_full_i) begin//3 if (diff_pntr > pf3_assert_val) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == pf3_assert_val) begin//4 if (read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ 1'b1; end else//4 prog_full_i <= #`TCQ 1'b0; end else//3 prog_full_i <= #`TCQ prog_full_i; end //2 else begin//5 if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~full_i ) begin//6 if (diff_pntr >= pf3_assert_val ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < pf3_assert_val) begin//7 prog_full_i <= #`TCQ 1'b0; end//7 end//6 else prog_full_i <= #`TCQ prog_full_i; end//5 end//1 end//0 end endgenerate //single_pf_input //----------------------------------------------------------------------------- // Generate PROG_FULL for multiple programmable threshold input ports //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT PROG_FULL_THRESH_ASSERT; // STD wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT PROG_FULL_THRESH_NEGATE; // STD generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~almost_full_i) begin if (diff_pntr >= pf_assert_val) prog_full_i <= #`TCQ 1'b1; else if ((diff_pntr == pf_negate_val && read_only_q) || diff_pntr < pf_negate_val) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~full_i ) begin if (diff_pntr >= pf_assert_val ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < pf_negate_val) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate //multiple_pf_inputs //----------------------------------------------------------------------------- // Generate PROG_EMPTY //----------------------------------------------------------------------------- localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD //----------------------------------------------------------------------------- // Generate PROG_EMPTY for single programmable threshold constant //----------------------------------------------------------------------------- generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (~rst_i ) begin if (diff_pntr_pe <= C_PE_ASSERT_VAL) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > C_PE_ASSERT_VAL) prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // single_pe_const //----------------------------------------------------------------------------- // Generate PROG_EMPTY for multiple programmable threshold constants //----------------------------------------------------------------------------- generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (~rst_i ) begin if (diff_pntr_pe <= C_PE_ASSERT_VAL ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > C_PE_NEGATE_VAL) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate //multiple_pe_const //----------------------------------------------------------------------------- // Generate PROG_EMPTY for single programmable threshold input port //----------------------------------------------------------------------------- wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH -2) : // FWFT PROG_EMPTY_THRESH; // STD generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (~almost_full_i) begin if (diff_pntr_pe < pe3_assert_val) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == pe3_assert_val) begin if (write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ 1'b1; end else prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (diff_pntr_pe <= pe3_assert_val ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > pe3_assert_val) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // single_pe_input //----------------------------------------------------------------------------- // Generate PROG_EMPTY for multiple programmable threshold input ports //----------------------------------------------------------------------------- wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT PROG_EMPTY_THRESH_ASSERT; // STD wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT PROG_EMPTY_THRESH_NEGATE; // STD generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (~almost_full_i) begin if (diff_pntr_pe <= pe4_assert_val) prog_empty_i <= #`TCQ 1'b1; else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || (diff_pntr_pe > pe4_negate_val)) begin prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (diff_pntr_pe <= pe4_assert_val ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > pe4_negate_val) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // multiple_pe_inputs endmodule // fifo_generator_v13_1_2_bhv_ver_ss /************************************************************************** * First-Word Fall-Through module (preload 0) **************************************************************************/ module fifo_generator_v13_1_2_bhv_ver_preload0 #( parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_HAS_RST = 0, parameter C_ENABLE_RST_SYNC = 0, parameter C_HAS_SRST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USERVALID_LOW = 0, parameter C_USERUNDERFLOW_LOW = 0, parameter C_MEMORY_TYPE = 0, parameter C_FIFO_TYPE = 0 ) ( //Inputs input SAFETY_CKT_RD_RST, input RD_CLK, input RD_RST, input SRST, input WR_RST_BUSY, input RD_RST_BUSY, input RD_EN, input FIFOEMPTY, input [C_DOUT_WIDTH-1:0] FIFODATA, input FIFOSBITERR, input FIFODBITERR, //Outputs output reg [C_DOUT_WIDTH-1:0] USERDATA, output USERVALID, output USERUNDERFLOW, output USEREMPTY, output USERALMOSTEMPTY, output RAMVALID, output FIFORDEN, output reg USERSBITERR, output reg USERDBITERR, output reg STAGE2_REG_EN, output fab_read_data_valid_i_o, output read_data_valid_i_o, output ram_valid_i_o, output [1:0] VALID_STAGES ); //Internal signals wire preloadstage1; wire preloadstage2; reg ram_valid_i; reg fab_valid; reg read_data_valid_i; reg fab_read_data_valid_i; reg fab_read_data_valid_i_1; reg ram_valid_i_d; reg read_data_valid_i_d; reg fab_read_data_valid_i_d; wire ram_regout_en; reg ram_regout_en_d1; reg ram_regout_en_d2; wire fab_regout_en; wire ram_rd_en; reg empty_i = 1'b1; reg empty_sckt = 1'b1; reg sckt_rrst_q = 1'b0; reg sckt_rrst_done = 1'b0; reg empty_q = 1'b1; reg rd_en_q = 1'b0; reg almost_empty_i = 1'b1; reg almost_empty_q = 1'b1; wire rd_rst_i; wire srst_i; reg [C_DOUT_WIDTH-1:0] userdata_both; wire uservalid_both; wire uservalid_one; reg user_sbiterr_both = 1'b0; reg user_dbiterr_both = 1'b0; assign ram_valid_i_o = ram_valid_i; assign read_data_valid_i_o = read_data_valid_i; assign fab_read_data_valid_i_o = fab_read_data_valid_i; /************************************************************************* * FUNCTIONS *************************************************************************/ /************************************************************************* * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***********************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction //************************************************************************* // Set power-on states for regs //************************************************************************* initial begin ram_valid_i = 1'b0; fab_valid = 1'b0; read_data_valid_i = 1'b0; fab_read_data_valid_i = 1'b0; fab_read_data_valid_i_1 = 1'b0; USERDATA = hexstr_conv(C_DOUT_RST_VAL); userdata_both = hexstr_conv(C_DOUT_RST_VAL); USERSBITERR = 1'b0; USERDBITERR = 1'b0; user_sbiterr_both = 1'b0; user_dbiterr_both = 1'b0; end //initial //*************************************************************************** // connect up optional reset //*************************************************************************** assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0; reg sckt_rd_rst_fwft = 1'b0; reg fwft_rst_done_i = 1'b0; wire fwft_rst_done; assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1; always @ (posedge RD_CLK) begin sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST; end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) fwft_rst_done_i <= 1'b0; else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST) fwft_rst_done_i <= #`TCQ 1'b1; end localparam INVALID = 0; localparam STAGE1_VALID = 2; localparam STAGE2_VALID = 1; localparam BOTH_STAGES_VALID = 3; reg [1:0] curr_fwft_state = INVALID; reg [1:0] next_fwft_state = INVALID; generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin always @* begin case (curr_fwft_state) INVALID: begin if (~FIFOEMPTY) next_fwft_state <= STAGE1_VALID; else next_fwft_state <= INVALID; end STAGE1_VALID: begin if (FIFOEMPTY) next_fwft_state <= STAGE2_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end STAGE2_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= INVALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= STAGE1_VALID; else if (~FIFOEMPTY && ~RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= STAGE2_VALID; end BOTH_STAGES_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= STAGE2_VALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end default: next_fwft_state <= INVALID; endcase end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) curr_fwft_state <= INVALID; else if (srst_i) curr_fwft_state <= #`TCQ INVALID; else curr_fwft_state <= #`TCQ next_fwft_state; end always @* begin case (curr_fwft_state) INVALID: STAGE2_REG_EN <= 1'b0; STAGE1_VALID: STAGE2_REG_EN <= 1'b1; STAGE2_VALID: STAGE2_REG_EN <= 1'b0; BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; default: STAGE2_REG_EN <= 1'b0; endcase end assign VALID_STAGES = curr_fwft_state; //*************************************************************************** // preloadstage2 indicates that stage2 needs to be updated. This is true // whenever read_data_valid is false, and RAM_valid is true. //*************************************************************************** assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); //*************************************************************************** // preloadstage1 indicates that stage1 needs to be updated. This is true // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is // false (indicating that Stage1 needs updating), or preloadstage2 is active // (indicating that Stage2 is going to update, so Stage1, therefore, must // also be updated to keep it valid. //*************************************************************************** assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); //*************************************************************************** // Calculate RAM_REGOUT_EN // The output registers are controlled by the ram_regout_en signal. // These registers should be updated either when the output in Stage2 is // invalid (preloadstage2), OR when the user is reading, in which case the // Stage2 value will go invalid unless it is replenished. //*************************************************************************** assign ram_regout_en = preloadstage2; //*************************************************************************** // Calculate RAM_RD_EN // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to // update the value in Stage1. // One case when this happens is when preloadstage1=true, which indicates // that the data in Stage1 or Stage2 is invalid, and needs to automatically // be updated. // The other case is when the user is reading from the FIFO, which // guarantees that Stage1 or Stage2 will be invalid on the next clock // cycle, unless it is replinished by data from the memory. So, as long // as the RAM has data in it, a read of the RAM should occur. //*************************************************************************** assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; end endgenerate // gnll_fifo reg curr_state = 0; reg next_state = 0; reg leaving_empty_fwft = 0; reg going_empty_fwft = 0; reg empty_i_q = 0; reg ram_rd_en_fwft = 0; generate if (C_FIFO_TYPE == 2) begin : gll_fifo always @* begin // FSM fo FWFT case (curr_state) 1'b0: begin if (~FIFOEMPTY) next_state <= 1'b1; else next_state <= 1'b0; end 1'b1: begin if (FIFOEMPTY && RD_EN) next_state <= 1'b0; else next_state <= 1'b1; end default: next_state <= 1'b0; endcase end always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin empty_i <= 1'b1; empty_i_q <= 1'b1; ram_valid_i <= 1'b0; end else if (srst_i) begin empty_i <= #`TCQ 1'b1; empty_i_q <= #`TCQ 1'b1; ram_valid_i <= #`TCQ 1'b0; end else begin empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i); empty_i_q <= #`TCQ FIFOEMPTY; ram_valid_i <= #`TCQ next_state; end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin curr_state <= 1'b0; end else if (srst_i) begin curr_state <= #`TCQ 1'b0; end else begin curr_state <= #`TCQ next_state; end end //always wire fe_of_empty; assign fe_of_empty = empty_i_q & ~FIFOEMPTY; always @* begin // Finding leaving empty case (curr_state) 1'b0: leaving_empty_fwft <= fe_of_empty; 1'b1: leaving_empty_fwft <= 1'b1; default: leaving_empty_fwft <= 1'b0; endcase end always @* begin // Finding going empty case (curr_state) 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN; default: going_empty_fwft <= 1'b0; endcase end always @* begin // Generating FWFT rd_en case (curr_state) 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY; 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN; default: ram_rd_en_fwft <= 1'b0; endcase end assign ram_regout_en = ram_rd_en_fwft; //assign ram_regout_en_d1 = ram_rd_en_fwft; //assign ram_regout_en_d2 = ram_rd_en_fwft; assign ram_rd_en = ram_rd_en_fwft; end endgenerate // gll_fifo //*************************************************************************** // Calculate RAMVALID_P0_OUT // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. // // If the RAM is being read from on this clock cycle (ram_rd_en=1), then // RAMVALID_P0_OUT is certainly going to be true. // If the RAM is not being read from, but the output registers are being // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, // therefore causing RAMVALID_P0_OUT to be false. // Otherwise, RAMVALID_P0_OUT will remain unchanged. //*************************************************************************** // PROCESS regout_valid generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) ram_valid_i <= #`TCQ 1'b0; end else begin if (srst_i) begin // synchronous reset (active high) ram_valid_i <= #`TCQ 1'b0; end else begin if (ram_rd_en == 1'b1) begin ram_valid_i <= #`TCQ 1'b1; end else begin if (ram_regout_en == 1'b1) ram_valid_i <= #`TCQ 1'b0; else ram_valid_i <= #`TCQ ram_valid_i; end end //srst_i end //rd_rst_i end //always end endgenerate // gnll_fifo_ram_valid //*************************************************************************** // Calculate READ_DATA_VALID // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. // Stage2 has valid data whenever Stage1 had valid data and // ram_regout_en_i=1, such that the data in Stage1 is propogated // into Stage2. //*************************************************************************** generate if(C_USE_EMBEDDED_REG < 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) read_data_valid_i <= #`TCQ 1'b0; else read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); end //always end endgenerate //************************************************************************** // Calculate EMPTY // Defined as the inverse of READ_DATA_VALID // // Description: // // If read_data_valid_i indicates that the output is not valid, // and there is no valid data on the output of the ram to preload it // with, then we will report empty. // // If there is no valid data on the output of the ram and we are // reading, then the FIFO will go empty. // //************************************************************************** generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin if (srst_i) begin // synchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin // rising clock edge empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); end end end //always end endgenerate // gnll_fifo_empty // Register RD_EN from user to calculate USERUNDERFLOW. // Register empty_i to calculate USERUNDERFLOW. always @ (posedge RD_CLK) begin rd_en_q <= #`TCQ RD_EN; empty_q <= #`TCQ empty_i; end //always //*************************************************************************** // Calculate user_almost_empty // user_almost_empty is defined such that, unless more words are written // to the FIFO, the next read will cause the FIFO to go EMPTY. // // In most cases, whenever the output registers are updated (due to a user // read or a preload condition), then user_almost_empty will update to // whatever RAM_EMPTY is. // // The exception is when the output is valid, the user is not reading, and // Stage1 is not empty. In this condition, Stage1 will be preloaded from the // memory, so we need to make sure user_almost_empty deasserts properly under // this condition. //*************************************************************************** generate if ( C_USE_EMBEDDED_REG < 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin // rising clock edge if (srst_i) begin // synchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin almost_empty_i <= #`TCQ FIFOEMPTY; end almost_empty_q <= #`TCQ empty_i; end end end //always end endgenerate // BRAM resets synchronously generate if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin always @ ( posedge rd_rst_i) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end if (C_USE_DOUT_RST == 1) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en) begin USERDATA <= #`TCQ FIFODATA; USERSBITERR <= #`TCQ FIFOSBITERR; USERDBITERR <= #`TCQ FIFODBITERR; end end end end //always end //if endgenerate //safety ckt with one register generate if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) //@(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end if (C_USE_DOUT_RST == 1) begin // @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin USERDATA <= #`TCQ FIFODATA; USERSBITERR <= #`TCQ FIFOSBITERR; USERDBITERR <= #`TCQ FIFODBITERR; end end end end //always end //if endgenerate generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin always @* begin case (curr_fwft_state) INVALID: begin if (~FIFOEMPTY) next_fwft_state <= STAGE1_VALID; else next_fwft_state <= INVALID; end STAGE1_VALID: begin if (FIFOEMPTY) next_fwft_state <= STAGE2_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end STAGE2_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= INVALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= STAGE1_VALID; else if (~FIFOEMPTY && ~RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= STAGE2_VALID; end BOTH_STAGES_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= STAGE2_VALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end default: next_fwft_state <= INVALID; endcase end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) curr_fwft_state <= INVALID; else if (srst_i) curr_fwft_state <= #`TCQ INVALID; else curr_fwft_state <= #`TCQ next_fwft_state; end always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay if (rd_rst_i == 1) begin ram_regout_en_d1 <= #`TCQ 1'b0; end else begin if (srst_i == 1'b1) ram_regout_en_d1 <= #`TCQ 1'b0; else ram_regout_en_d1 <= #`TCQ ram_regout_en; end end //always // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i)); assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0; always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1 if (rd_rst_i == 1) begin ram_regout_en_d2 <= #`TCQ 1'b0; end else begin if (srst_i == 1'b1) ram_regout_en_d2 <= #`TCQ 1'b0; else ram_regout_en_d2 <= #`TCQ ram_regout_en_d1; end end //always always @* begin case (curr_fwft_state) INVALID: STAGE2_REG_EN <= 1'b0; STAGE1_VALID: STAGE2_REG_EN <= 1'b1; STAGE2_VALID: STAGE2_REG_EN <= 1'b0; BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; default: STAGE2_REG_EN <= 1'b0; endcase end always @ (posedge RD_CLK) begin ram_valid_i_d <= #`TCQ ram_valid_i; read_data_valid_i_d <= #`TCQ read_data_valid_i; fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i; end assign VALID_STAGES = curr_fwft_state; //*************************************************************************** // preloadstage2 indicates that stage2 needs to be updated. This is true // whenever read_data_valid is false, and RAM_valid is true. //*************************************************************************** assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); //*************************************************************************** // preloadstage1 indicates that stage1 needs to be updated. This is true // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is // false (indicating that Stage1 needs updating), or preloadstage2 is active // (indicating that Stage2 is going to update, so Stage1, therefore, must // also be updated to keep it valid. //*************************************************************************** assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); //*************************************************************************** // Calculate RAM_REGOUT_EN // The output registers are controlled by the ram_regout_en signal. // These registers should be updated either when the output in Stage2 is // invalid (preloadstage2), OR when the user is reading, in which case the // Stage2 value will go invalid unless it is replenished. //*************************************************************************** assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0; //*************************************************************************** // Calculate RAM_RD_EN // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to // update the value in Stage1. // One case when this happens is when preloadstage1=true, which indicates // that the data in Stage1 or Stage2 is invalid, and needs to automatically // be updated. // The other case is when the user is reading from the FIFO, which // guarantees that Stage1 or Stage2 will be invalid on the next clock // cycle, unless it is replinished by data from the memory. So, as long // as the RAM has data in it, a read of the RAM should occur. //*************************************************************************** assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1; end endgenerate // gnll_fifo //*************************************************************************** // Calculate RAMVALID_P0_OUT // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. // // If the RAM is being read from on this clock cycle (ram_rd_en=1), then // RAMVALID_P0_OUT is certainly going to be true. // If the RAM is not being read from, but the output registers are being // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged. //*************************************************************************** // PROCESS regout_valid generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) fab_valid <= #`TCQ 1'b0; end else begin if (srst_i) begin // synchronous reset (active high) fab_valid <= #`TCQ 1'b0; end else begin if (ram_regout_en == 1'b1) begin fab_valid <= #`TCQ 1'b1; end else begin if (fab_regout_en == 1'b1) fab_valid <= #`TCQ 1'b0; else fab_valid <= #`TCQ fab_valid; end end //srst_i end //rd_rst_i end //always end endgenerate // gnll_fifo_fab_valid //*************************************************************************** // Calculate READ_DATA_VALID // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. // Stage2 has valid data whenever Stage1 had valid data and // ram_regout_en_i=1, such that the data in Stage1 is propogated // into Stage2. //*************************************************************************** generate if(C_USE_EMBEDDED_REG == 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) read_data_valid_i <= #`TCQ 1'b0; else begin if (ram_regout_en == 1'b1) begin read_data_valid_i <= #`TCQ 1'b1; end else begin if (fab_regout_en == 1'b1) read_data_valid_i <= #`TCQ 1'b0; else read_data_valid_i <= #`TCQ read_data_valid_i; end end end //always end endgenerate //generate if(C_USE_EMBEDDED_REG == 3) begin // always @ (posedge RD_CLK or posedge rd_rst_i) begin // if (rd_rst_i) // read_data_valid_i <= #`TCQ 1'b0; // else if (srst_i) // read_data_valid_i <= #`TCQ 1'b0; // // if (ram_regout_en == 1'b1) begin // fab_read_data_valid_i <= #`TCQ 1'b0; // end else begin // if (fab_regout_en == 1'b1) // fab_read_data_valid_i <= #`TCQ 1'b1; // else // fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i; // end // end //always //end //endgenerate generate if(C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid if (rd_rst_i) fab_read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) fab_read_data_valid_i <= #`TCQ 1'b0; else fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN); end //always end endgenerate always @ (posedge RD_CLK ) begin : proc_del1 begin fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i; end end //always //************************************************************************** // Calculate EMPTY // Defined as the inverse of READ_DATA_VALID // // Description: // // If read_data_valid_i indicates that the output is not valid, // and there is no valid data on the output of the ram to preload it // with, then we will report empty. // // If there is no valid data on the output of the ram and we are // reading, then the FIFO will go empty. // //************************************************************************** generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin if (srst_i) begin // synchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin // rising clock edge empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN); end end end //always end endgenerate // gnll_fifo_empty_both // Register RD_EN from user to calculate USERUNDERFLOW. // Register empty_i to calculate USERUNDERFLOW. always @ (posedge RD_CLK) begin rd_en_q <= #`TCQ RD_EN; empty_q <= #`TCQ empty_i; end //always //*************************************************************************** // Calculate user_almost_empty // user_almost_empty is defined such that, unless more words are written // to the FIFO, the next read will cause the FIFO to go EMPTY. // // In most cases, whenever the output registers are updated (due to a user // read or a preload condition), then user_almost_empty will update to // whatever RAM_EMPTY is. // // The exception is when the output is valid, the user is not reading, and // Stage1 is not empty. In this condition, Stage1 will be preloaded from the // memory, so we need to make sure user_almost_empty deasserts properly under // this condition. //*************************************************************************** reg FIFOEMPTY_1; generate if (C_USE_EMBEDDED_REG == 3 ) begin always @(posedge RD_CLK) begin FIFOEMPTY_1 <= #`TCQ FIFOEMPTY; end end endgenerate generate if (C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin // rising clock edge if (srst_i) begin // synchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin almost_empty_i <= #`TCQ (~ram_valid_i); end almost_empty_q <= #`TCQ empty_i; end end end //always end endgenerate always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin empty_sckt <= #`TCQ 1'b1; sckt_rrst_q <= #`TCQ 1'b0; sckt_rrst_done <= #`TCQ 1'b0; end else begin sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST; if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin sckt_rrst_done <= #`TCQ 1'b1; end else if (sckt_rrst_done) begin // rising clock edge empty_sckt <= #`TCQ 1'b0; end end end //always // assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i; assign USEREMPTY = empty_i; assign USERALMOSTEMPTY = almost_empty_i; assign FIFORDEN = ram_rd_en; assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i; assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0); assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0); assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one; assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //no safety ckt with both reg generate if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin if (fwft_rst_done) begin if (ram_regout_en) begin userdata_both <= #`TCQ FIFODATA; user_dbiterr_both <= #`TCQ FIFODBITERR; user_sbiterr_both <= #`TCQ FIFOSBITERR; end if (fab_regout_en) begin USERDATA <= #`TCQ userdata_both; USERDBITERR <= #`TCQ user_dbiterr_both; USERSBITERR <= #`TCQ user_sbiterr_both; end end end end end //always end //if endgenerate //safety_ckt with both registers generate if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin userdata_both <= #`TCQ FIFODATA; user_dbiterr_both <= #`TCQ FIFODBITERR; user_sbiterr_both <= #`TCQ FIFOSBITERR; end if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin USERDATA <= #`TCQ userdata_both; USERDBITERR <= #`TCQ user_dbiterr_both; USERSBITERR <= #`TCQ user_sbiterr_both; end end end end //always end //if endgenerate endmodule //fifo_generator_v13_1_2_bhv_ver_preload0 //----------------------------------------------------------------------------- // // Register Slice // Register one AXI channel on forward and/or reverse signal path // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // reg_slice // //-------------------------------------------------------------------------- module fifo_generator_v13_1_2_axic_reg_slice # ( parameter C_FAMILY = "virtex7", parameter C_DATA_WIDTH = 32, parameter C_REG_CONFIG = 32'h00000000 ) ( // System Signals input wire ACLK, input wire ARESET, // Slave side input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, input wire S_VALID, output wire S_READY, // Master side output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, output wire M_VALID, input wire M_READY ); generate //////////////////////////////////////////////////////////////////// // // Both FWD and REV mode // //////////////////////////////////////////////////////////////////// if (C_REG_CONFIG == 32'h00000000) begin reg [1:0] state; localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01; reg [C_DATA_WIDTH-1:0] storage_data1 = 0; reg [C_DATA_WIDTH-1:0] storage_data2 = 0; reg load_s1; wire load_s2; wire load_s1_from_s2; reg s_ready_i; //local signal of output wire m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg areset_d1; // Reset delay register always @(posedge ACLK) begin areset_d1 <= ARESET; end // Load storage1 with either slave side data or from storage2 always @(posedge ACLK) begin if (load_s1) if (load_s1_from_s2) storage_data1 <= storage_data2; else storage_data1 <= S_PAYLOAD_DATA; end // Load storage2 with slave side data always @(posedge ACLK) begin if (load_s2) storage_data2 <= S_PAYLOAD_DATA; end assign M_PAYLOAD_DATA = storage_data1; // Always load s2 on a valid transaction even if it's unnecessary assign load_s2 = S_VALID & s_ready_i; // Loading s1 always @ * begin if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction // Load when ONE if we both have read and write at the same time ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || // Load when TWO and we have a transaction on Master side ((state == TWO) && (M_READY == 1))) load_s1 = 1'b1; else load_s1 = 1'b0; end // always @ * assign load_s1_from_s2 = (state == TWO); // State Machine for handling output signals always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; state <= ZERO; end else if (areset_d1) begin s_ready_i <= 1'b1; end else begin case (state) // No transaction stored locally ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE // One transaction stored locally ONE: begin if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO if (~M_READY & S_VALID) begin state <= TWO; // Got another one so move to TWO s_ready_i <= 1'b0; end end // TWO transaction stored locally TWO: if (M_READY) begin state <= ONE; // Read out one so move to ONE s_ready_i <= 1'b1; end endcase // case (state) end end // always @ (posedge ACLK) assign m_valid_i = state[0]; end // if (C_REG_CONFIG == 1) //////////////////////////////////////////////////////////////////// // // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining // Operates same as 1-deep FIFO // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000001) begin reg [C_DATA_WIDTH-1:0] storage_data1 = 0; reg s_ready_i; //local signal of output reg m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg areset_d1; // Reset delay register always @(posedge ACLK) begin areset_d1 <= ARESET; end // Load storage1 with slave side data always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; m_valid_i <= 1'b0; end else if (areset_d1) begin s_ready_i <= 1'b1; end else if (m_valid_i & M_READY) begin s_ready_i <= 1'b1; m_valid_i <= 1'b0; end else if (S_VALID & s_ready_i) begin s_ready_i <= 1'b0; m_valid_i <= 1'b1; end if (~m_valid_i) begin storage_data1 <= S_PAYLOAD_DATA; end end assign M_PAYLOAD_DATA = storage_data1; end // if (C_REG_CONFIG == 7) else begin : default_case // Passthrough assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; assign M_VALID = S_VALID; assign S_READY = M_READY; end endgenerate endmodule // reg_slice ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/mem_init_files/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/mem_init_files/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1875 1.8V 4:1 200 0 1066 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 7 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 6 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_clk_wiz.v" --include "../../../ipstatic" verilog xil_defaultlib "../../../../ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.v" --include "../../../ipstatic" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/activehdl/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/ies/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/modelsim/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/questa/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/riviera/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/vcs/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_addr_decode.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg_bank.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_arbiter.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wr_cmd_fsm.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_r_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_simple_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_a_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_register_slice.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_and.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel_static.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_r_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_w_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_select.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_common.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_state.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_col_mach.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_mc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_common.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_dec_fix.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_merge_enc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_fi_xor.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_skip_calib_tap.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_meta.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ddr3_if_mig_sim.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ddr3_if.v" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/activehdl/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/ies/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/modelsim/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/questa/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/riviera/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/vcs/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_addr_decode.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg_bank.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_arbiter.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wr_cmd_fsm.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_r_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_simple_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_a_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_register_slice.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_and.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel_static.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_r_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_w_upsizer.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_select.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_common.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_state.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_col_mach.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_mc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_common.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_dec_fix.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_merge_enc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_fi_xor.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_skip_calib_tap.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_meta.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_top.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ddr3_if_mig_sim.v" verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ddr3_if.v" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_clk_wiz.v" --include "../../../ipstatic" verilog xil_defaultlib "../../../../ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.v" --include "../../../ipstatic" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/ila_0/sim/ila_0.v" --include "../../../../framebuffer_test.srcs/sources_1/ip/ila_0/hdl/verilog" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/input_line_buffer/sim/input_line_buffer.v" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/sim/input_line_buffer.v" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/output_line_buffer/sim/output_line_buffer.v" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/activehdl/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/ies/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/modelsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/questa/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/riviera/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/vcs/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/cmd.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run -all quit ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/glbl.v ================================================ // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/vlog.prj ================================================ verilog xil_defaultlib "../../../../framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/sim/output_line_buffer.v" verilog xil_defaultlib "glbl.v" nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.tcl ================================================ # # Synthesis run script generated by Vivado # set_msg_config -id {HDL 9-1061} -limit 100000 set_msg_config -id {HDL 9-1654} -limit 100000 set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k325tffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project] set_property parent.project_path /home/dave/ip/examples/ov13850_demo/ov13850_demo.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_ip -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci set_property is_locked true [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci] foreach dcp [get_files -quiet -all *.dcp] { set_property used_in_implementation false $dcp } read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1 -new_name camera_pll -ip [get_ips camera_pll]] if { $cached_ip eq {} } { synth_design -top camera_pll -part xc7k325tffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache #--------------------------------------------------------- catch { write_checkpoint -force -noxdef -rename_prefix camera_pll_ camera_pll.dcp set ipCachedFiles {} write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.v lappend ipCachedFiles camera_pll_stub.v write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.vhdl lappend ipCachedFiles camera_pll_stub.vhdl write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.v lappend ipCachedFiles camera_pll_sim_netlist.v write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.vhdl lappend ipCachedFiles camera_pll_sim_netlist.vhdl config_ip_cache -add -dcp camera_pll.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips camera_pll] } rename_ref -prefix_all camera_pll_ write_checkpoint -force -noxdef camera_pll.dcp catch { report_utilization -file camera_pll_utilization_synth.rpt -pb camera_pll_utilization_synth.pb } if { [catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { write_verilog -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_verilog -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } } else { if { [catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_sim_netlist.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_sim_netlist.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip if {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll]} { catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll } } if {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll]} { catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll } } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/dont_touch.xdc ================================================ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. # IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci # IP: The module: 'camera_pll' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc # XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint. set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc # XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci # IP: The module: 'camera_pll' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc # XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc # XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/ddr3_if_synth_1/ddr3_if.tcl ================================================ # # Synthesis run script generated by Vivado # set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k325tffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_property webtalk.parent_dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/wt [current_project] set_property parent.project_path /home/dave/ip/examples/framebuffer_test/framebuffer_test.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_ip -quiet /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.xci set_property is_locked true [get_files /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.xci] foreach dcp [get_files -quiet -all *.dcp] { set_property used_in_implementation false $dcp } set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1 -new_name ddr3_if -ip [get_ips ddr3_if]] if { $cached_ip eq {} } { synth_design -top ddr3_if -part xc7k325tffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache #--------------------------------------------------------- catch { write_checkpoint -force -noxdef -rename_prefix ddr3_if_ ddr3_if.dcp set ipCachedFiles {} write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_stub.v lappend ipCachedFiles ddr3_if_stub.v write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_stub.vhdl lappend ipCachedFiles ddr3_if_stub.vhdl write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_sim_netlist.v lappend ipCachedFiles ddr3_if_sim_netlist.v write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_sim_netlist.vhdl lappend ipCachedFiles ddr3_if_sim_netlist.vhdl config_ip_cache -add -dcp ddr3_if.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips ddr3_if] } rename_ref -prefix_all ddr3_if_ write_checkpoint -force -noxdef ddr3_if.dcp catch { report_utilization -file ddr3_if_utilization_synth.rpt -pb ddr3_if_utilization_synth.pb } if { [catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { write_verilog -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_verilog -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } } else { if { [catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_sim_netlist.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_sim_netlist.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip if {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if]} { catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if } } if {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if]} { catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if } } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dont_touch.xdc ================================================ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. # IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci # IP: The module: 'dvi_pll' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_board.xdc # XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint. set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xdc # XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci # IP: The module: 'dvi_pll' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_board.xdc # XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xdc # XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] # XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells inst] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.tcl ================================================ # # Synthesis run script generated by Vivado # set_param xicom.use_bs_reader 1 set_msg_config -id {HDL 9-1061} -limit 100000 set_msg_config -id {HDL 9-1654} -limit 100000 set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k325tffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project] set_property parent.project_path /home/dave/ip/examples/ov13850_demo/ov13850_demo.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_ip -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci set_property is_locked true [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci] foreach dcp [get_files -quiet -all *.dcp] { set_property used_in_implementation false $dcp } read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1 -new_name dvi_pll -ip [get_ips dvi_pll]] if { $cached_ip eq {} } { synth_design -top dvi_pll -part xc7k325tffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache #--------------------------------------------------------- catch { write_checkpoint -force -noxdef -rename_prefix dvi_pll_ dvi_pll.dcp set ipCachedFiles {} write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v lappend ipCachedFiles dvi_pll_stub.v write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.vhdl lappend ipCachedFiles dvi_pll_stub.vhdl write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v lappend ipCachedFiles dvi_pll_sim_netlist.v write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.vhdl lappend ipCachedFiles dvi_pll_sim_netlist.vhdl config_ip_cache -add -dcp dvi_pll.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips dvi_pll] } rename_ref -prefix_all dvi_pll_ write_checkpoint -force -noxdef dvi_pll.dcp catch { report_utilization -file dvi_pll_utilization_synth.rpt -pb dvi_pll_utilization_synth.pb } if { [catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { write_verilog -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_verilog -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } } else { if { [catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_sim_netlist.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_sim_netlist.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip if {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll]} { catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll } } if {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll]} { catch { file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll } } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/impl_1/ov13850_demo.tcl ================================================ proc start_step { step } { set stopFile ".stop.rst" if {[file isfile .stop.rst]} { puts "" puts "*** Halting run - EA reset detected ***" puts "" puts "" return -code error } set beginFile ".$step.begin.rst" set platform "$::tcl_platform(platform)" set user "$::tcl_platform(user)" set pid [pid] set host "" if { [string equal $platform unix] } { if { [info exist ::env(HOSTNAME)] } { set host $::env(HOSTNAME) } } else { if { [info exist ::env(COMPUTERNAME)] } { set host $::env(COMPUTERNAME) } } set ch [open $beginFile w] puts $ch "" puts $ch "" puts $ch " " puts $ch " " puts $ch "" close $ch } proc end_step { step } { set endFile ".$step.end.rst" set ch [open $endFile w] close $ch } proc step_failed { step } { set endFile ".$step.error.rst" set ch [open $endFile w] close $ch } set_msg_config -id {HDL 9-1061} -limit 100000 set_msg_config -id {HDL 9-1654} -limit 100000 start_step write_bitstream set ACTIVE_STEP write_bitstream set rc [catch { create_msg_db write_bitstream.pb set_param xicom.use_bs_reader 1 open_checkpoint ov13850_demo_routed.dcp set_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] catch { write_mem_info -force ov13850_demo.mmi } write_bitstream -force -no_partial_bitfile ov13850_demo.bit catch { write_sysdef -hwdef ov13850_demo.hwdef -bitfile ov13850_demo.bit -meminfo ov13850_demo.mmi -file ov13850_demo.sysdef } catch {write_debug_probes -quiet -force debug_nets} close_msg_db -file write_bitstream.pb } RESULT] if {$rc} { step_failed write_bitstream return -code error $RESULT } else { end_step write_bitstream unset ACTIVE_STEP } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/dont_touch.xdc ================================================ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. # IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci # IP: The module: 'input_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'input_line_buffer'. Do not add the DONT_TOUCH constraint. set_property DONT_TOUCH TRUE [get_cells U0] # IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci # IP: The module: 'input_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'input_line_buffer'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells U0] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer.tcl ================================================ # # Synthesis run script generated by Vivado # set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k325tffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_property webtalk.parent_dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/wt [current_project] set_property parent.project_path /home/dave/ip/examples/framebuffer_test/framebuffer_test.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_ip -quiet /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci set_property is_locked true [get_files /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci] foreach dcp [get_files -quiet -all *.dcp] { set_property used_in_implementation false $dcp } read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1 -new_name input_line_buffer -ip [get_ips input_line_buffer]] if { $cached_ip eq {} } { synth_design -top input_line_buffer -part xc7k325tffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache #--------------------------------------------------------- catch { write_checkpoint -force -noxdef -rename_prefix input_line_buffer_ input_line_buffer.dcp set ipCachedFiles {} write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_stub.v lappend ipCachedFiles input_line_buffer_stub.v write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_stub.vhdl lappend ipCachedFiles input_line_buffer_stub.vhdl write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_sim_netlist.v lappend ipCachedFiles input_line_buffer_sim_netlist.v write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_sim_netlist.vhdl lappend ipCachedFiles input_line_buffer_sim_netlist.vhdl config_ip_cache -add -dcp input_line_buffer.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips input_line_buffer] } rename_ref -prefix_all input_line_buffer_ write_checkpoint -force -noxdef input_line_buffer.dcp catch { report_utilization -file input_line_buffer_utilization_synth.rpt -pb input_line_buffer_utilization_synth.pb } if { [catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { write_verilog -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_verilog -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } } else { if { [catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip if {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer]} { catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer } } if {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer]} { catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer } } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:41:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_sim_netlist.v // Design : input_line_buffer // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "input_line_buffer,blk_mem_gen_v8_3_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (clka, ena, wea, addra, dina, clkb, addrb, doutb); (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [63:0]dina; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [9:0]addrb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [255:0]doutb; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_rsta_busy_UNCONNECTED; wire NLW_U0_rstb_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_dbiterr_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_sbiterr_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire [63:0]NLW_U0_douta_UNCONNECTED; wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED; wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; wire [255:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; (* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 36.714252 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "input_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "4096" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "64" *) (* C_READ_WIDTH_B = "256" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "4096" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "64" *) (* C_WRITE_WIDTH_B = "256" *) (* C_XDEVICEFAMILY = "kintex7" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 U0 (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .deepsleep(1'b0), .dina(dina), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(NLW_U0_douta_UNCONNECTED[63:0]), .doutb(doutb), .eccpipece(1'b0), .ena(ena), .enb(1'b0), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]), .regcea(1'b0), .regceb(1'b0), .rsta(1'b0), .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), .rstb(1'b0), .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), .s_aclk(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), .s_axi_injectdbiterr(1'b0), .s_axi_injectsbiterr(1'b0), .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[255:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb(1'b0), .s_axi_wvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .shutdown(1'b0), .sleep(1'b0), .wea(wea), .web(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [255:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [63:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[3:0]), .doutb({doutb[195:192],doutb[131:128],doutb[67:64],doutb[3:0]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[12:4]), .doutb({doutb[204:196],doutb[140:132],doutb[76:68],doutb[12:4]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[21:13]), .doutb({doutb[213:205],doutb[149:141],doutb[85:77],doutb[21:13]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[30:22]), .doutb({doutb[222:214],doutb[158:150],doutb[94:86],doutb[30:22]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[39:31]), .doutb({doutb[231:223],doutb[167:159],doutb[103:95],doutb[39:31]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[48:40]), .doutb({doutb[240:232],doutb[176:168],doutb[112:104],doutb[48:40]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[57:49]), .doutb({doutb[249:241],doutb[185:177],doutb[121:113],doutb[57:49]}), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[63:58]), .doutb({doutb[255:250],doutb[191:186],doutb[127:122],doutb[63:58]}), .ena(ena), .wea(wea)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [15:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [3:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [3:0]dina; wire [15:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [23:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [5:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [5:0]dina; wire [23:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [15:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [3:0]dina; input [0:0]wea; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 ; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [3:0]dina; wire [15:0]doutb; wire ena; wire [0:0]wea; wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(18), .READ_WIDTH_B(18), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(4), .WRITE_WIDTH_B(4)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (.ADDRARDADDR({addra,1'b0,1'b0}), .ADDRBWRADDR({addrb,1'b0,1'b0,1'b0,1'b0}), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), .DOBDO(doutb), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 }), .ENARDEN(ena), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [23:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [5:0]dina; input [0:0]wea; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [5:0]dina; wire [23:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ,doutb[23:18],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ,doutb[17:12],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,doutb[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb[5:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [255:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [63:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 36.714252 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "input_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "4096" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "64" *) (* C_READ_WIDTH_B = "256" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "4096" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "64" *) (* C_WRITE_WIDTH_B = "256" *) (* C_XDEVICEFAMILY = "kintex7" *) (* downgradeipidentifiedwarnings = "yes" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 (clka, rsta, ena, regcea, wea, addra, dina, douta, clkb, rstb, enb, regceb, web, addrb, dinb, doutb, injectsbiterr, injectdbiterr, eccpipece, sbiterr, dbiterr, rdaddrecc, sleep, deepsleep, shutdown, rsta_busy, rstb_busy, s_aclk, s_aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, s_axi_injectsbiterr, s_axi_injectdbiterr, s_axi_sbiterr, s_axi_dbiterr, s_axi_rdaddrecc); input clka; input rsta; input ena; input regcea; input [0:0]wea; input [11:0]addra; input [63:0]dina; output [63:0]douta; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [9:0]addrb; input [255:0]dinb; output [255:0]doutb; input injectsbiterr; input injectdbiterr; input eccpipece; output sbiterr; output dbiterr; output [9:0]rdaddrecc; input sleep; input deepsleep; input shutdown; output rsta_busy; output rstb_busy; input s_aclk; input s_aresetn; input [3:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input s_axi_awvalid; output s_axi_awready; input [63:0]s_axi_wdata; input [0:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; output [3:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input s_axi_bready; input [3:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input s_axi_arvalid; output s_axi_arready; output [3:0]s_axi_rid; output [255:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; input s_axi_rready; input s_axi_injectsbiterr; input s_axi_injectdbiterr; output s_axi_sbiterr; output s_axi_dbiterr; output [9:0]s_axi_rdaddrecc; wire \ ; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; assign dbiterr = \ ; assign douta[63] = \ ; assign douta[62] = \ ; assign douta[61] = \ ; assign douta[60] = \ ; assign douta[59] = \ ; assign douta[58] = \ ; assign douta[57] = \ ; assign douta[56] = \ ; assign douta[55] = \ ; assign douta[54] = \ ; assign douta[53] = \ ; assign douta[52] = \ ; assign douta[51] = \ ; assign douta[50] = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign rdaddrecc[9] = \ ; assign rdaddrecc[8] = \ ; assign rdaddrecc[7] = \ ; assign rdaddrecc[6] = \ ; assign rdaddrecc[5] = \ ; assign rdaddrecc[4] = \ ; assign rdaddrecc[3] = \ ; assign rdaddrecc[2] = \ ; assign rdaddrecc[1] = \ ; assign rdaddrecc[0] = \ ; assign rsta_busy = \ ; assign rstb_busy = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[3] = \ ; assign s_axi_bid[2] = \ ; assign s_axi_bid[1] = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_dbiterr = \ ; assign s_axi_rdaddrecc[9] = \ ; assign s_axi_rdaddrecc[8] = \ ; assign s_axi_rdaddrecc[7] = \ ; assign s_axi_rdaddrecc[6] = \ ; assign s_axi_rdaddrecc[5] = \ ; assign s_axi_rdaddrecc[4] = \ ; assign s_axi_rdaddrecc[3] = \ ; assign s_axi_rdaddrecc[2] = \ ; assign s_axi_rdaddrecc[1] = \ ; assign s_axi_rdaddrecc[0] = \ ; assign s_axi_rdata[255] = \ ; assign s_axi_rdata[254] = \ ; assign s_axi_rdata[253] = \ ; assign s_axi_rdata[252] = \ ; assign s_axi_rdata[251] = \ ; assign s_axi_rdata[250] = \ ; assign s_axi_rdata[249] = \ ; assign s_axi_rdata[248] = \ ; assign s_axi_rdata[247] = \ ; assign s_axi_rdata[246] = \ ; assign s_axi_rdata[245] = \ ; assign s_axi_rdata[244] = \ ; assign s_axi_rdata[243] = \ ; assign s_axi_rdata[242] = \ ; assign s_axi_rdata[241] = \ ; assign s_axi_rdata[240] = \ ; assign s_axi_rdata[239] = \ ; assign s_axi_rdata[238] = \ ; assign s_axi_rdata[237] = \ ; assign s_axi_rdata[236] = \ ; assign s_axi_rdata[235] = \ ; assign s_axi_rdata[234] = \ ; assign s_axi_rdata[233] = \ ; assign s_axi_rdata[232] = \ ; assign s_axi_rdata[231] = \ ; assign s_axi_rdata[230] = \ ; assign s_axi_rdata[229] = \ ; assign s_axi_rdata[228] = \ ; assign s_axi_rdata[227] = \ ; assign s_axi_rdata[226] = \ ; assign s_axi_rdata[225] = \ ; assign s_axi_rdata[224] = \ ; assign s_axi_rdata[223] = \ ; assign s_axi_rdata[222] = \ ; assign s_axi_rdata[221] = \ ; assign s_axi_rdata[220] = \ ; assign s_axi_rdata[219] = \ ; assign s_axi_rdata[218] = \ ; assign s_axi_rdata[217] = \ ; assign s_axi_rdata[216] = \ ; assign s_axi_rdata[215] = \ ; assign s_axi_rdata[214] = \ ; assign s_axi_rdata[213] = \ ; assign s_axi_rdata[212] = \ ; assign s_axi_rdata[211] = \ ; assign s_axi_rdata[210] = \ ; assign s_axi_rdata[209] = \ ; assign s_axi_rdata[208] = \ ; assign s_axi_rdata[207] = \ ; assign s_axi_rdata[206] = \ ; assign s_axi_rdata[205] = \ ; assign s_axi_rdata[204] = \ ; assign s_axi_rdata[203] = \ ; assign s_axi_rdata[202] = \ ; assign s_axi_rdata[201] = \ ; assign s_axi_rdata[200] = \ ; assign s_axi_rdata[199] = \ ; assign s_axi_rdata[198] = \ ; assign s_axi_rdata[197] = \ ; assign s_axi_rdata[196] = \ ; assign s_axi_rdata[195] = \ ; assign s_axi_rdata[194] = \ ; assign s_axi_rdata[193] = \ ; assign s_axi_rdata[192] = \ ; assign s_axi_rdata[191] = \ ; assign s_axi_rdata[190] = \ ; assign s_axi_rdata[189] = \ ; assign s_axi_rdata[188] = \ ; assign s_axi_rdata[187] = \ ; assign s_axi_rdata[186] = \ ; assign s_axi_rdata[185] = \ ; assign s_axi_rdata[184] = \ ; assign s_axi_rdata[183] = \ ; assign s_axi_rdata[182] = \ ; assign s_axi_rdata[181] = \ ; assign s_axi_rdata[180] = \ ; assign s_axi_rdata[179] = \ ; assign s_axi_rdata[178] = \ ; assign s_axi_rdata[177] = \ ; assign s_axi_rdata[176] = \ ; assign s_axi_rdata[175] = \ ; assign s_axi_rdata[174] = \ ; assign s_axi_rdata[173] = \ ; assign s_axi_rdata[172] = \ ; assign s_axi_rdata[171] = \ ; assign s_axi_rdata[170] = \ ; assign s_axi_rdata[169] = \ ; assign s_axi_rdata[168] = \ ; assign s_axi_rdata[167] = \ ; assign s_axi_rdata[166] = \ ; assign s_axi_rdata[165] = \ ; assign s_axi_rdata[164] = \ ; assign s_axi_rdata[163] = \ ; assign s_axi_rdata[162] = \ ; assign s_axi_rdata[161] = \ ; assign s_axi_rdata[160] = \ ; assign s_axi_rdata[159] = \ ; assign s_axi_rdata[158] = \ ; assign s_axi_rdata[157] = \ ; assign s_axi_rdata[156] = \ ; assign s_axi_rdata[155] = \ ; assign s_axi_rdata[154] = \ ; assign s_axi_rdata[153] = \ ; assign s_axi_rdata[152] = \ ; assign s_axi_rdata[151] = \ ; assign s_axi_rdata[150] = \ ; assign s_axi_rdata[149] = \ ; assign s_axi_rdata[148] = \ ; assign s_axi_rdata[147] = \ ; assign s_axi_rdata[146] = \ ; assign s_axi_rdata[145] = \ ; assign s_axi_rdata[144] = \ ; assign s_axi_rdata[143] = \ ; assign s_axi_rdata[142] = \ ; assign s_axi_rdata[141] = \ ; assign s_axi_rdata[140] = \ ; assign s_axi_rdata[139] = \ ; assign s_axi_rdata[138] = \ ; assign s_axi_rdata[137] = \ ; assign s_axi_rdata[136] = \ ; assign s_axi_rdata[135] = \ ; assign s_axi_rdata[134] = \ ; assign s_axi_rdata[133] = \ ; assign s_axi_rdata[132] = \ ; assign s_axi_rdata[131] = \ ; assign s_axi_rdata[130] = \ ; assign s_axi_rdata[129] = \ ; assign s_axi_rdata[128] = \ ; assign s_axi_rdata[127] = \ ; assign s_axi_rdata[126] = \ ; assign s_axi_rdata[125] = \ ; assign s_axi_rdata[124] = \ ; assign s_axi_rdata[123] = \ ; assign s_axi_rdata[122] = \ ; assign s_axi_rdata[121] = \ ; assign s_axi_rdata[120] = \ ; assign s_axi_rdata[119] = \ ; assign s_axi_rdata[118] = \ ; assign s_axi_rdata[117] = \ ; assign s_axi_rdata[116] = \ ; assign s_axi_rdata[115] = \ ; assign s_axi_rdata[114] = \ ; assign s_axi_rdata[113] = \ ; assign s_axi_rdata[112] = \ ; assign s_axi_rdata[111] = \ ; assign s_axi_rdata[110] = \ ; assign s_axi_rdata[109] = \ ; assign s_axi_rdata[108] = \ ; assign s_axi_rdata[107] = \ ; assign s_axi_rdata[106] = \ ; assign s_axi_rdata[105] = \ ; assign s_axi_rdata[104] = \ ; assign s_axi_rdata[103] = \ ; assign s_axi_rdata[102] = \ ; assign s_axi_rdata[101] = \ ; assign s_axi_rdata[100] = \ ; assign s_axi_rdata[99] = \ ; assign s_axi_rdata[98] = \ ; assign s_axi_rdata[97] = \ ; assign s_axi_rdata[96] = \ ; assign s_axi_rdata[95] = \ ; assign s_axi_rdata[94] = \ ; assign s_axi_rdata[93] = \ ; assign s_axi_rdata[92] = \ ; assign s_axi_rdata[91] = \ ; assign s_axi_rdata[90] = \ ; assign s_axi_rdata[89] = \ ; assign s_axi_rdata[88] = \ ; assign s_axi_rdata[87] = \ ; assign s_axi_rdata[86] = \ ; assign s_axi_rdata[85] = \ ; assign s_axi_rdata[84] = \ ; assign s_axi_rdata[83] = \ ; assign s_axi_rdata[82] = \ ; assign s_axi_rdata[81] = \ ; assign s_axi_rdata[80] = \ ; assign s_axi_rdata[79] = \ ; assign s_axi_rdata[78] = \ ; assign s_axi_rdata[77] = \ ; assign s_axi_rdata[76] = \ ; assign s_axi_rdata[75] = \ ; assign s_axi_rdata[74] = \ ; assign s_axi_rdata[73] = \ ; assign s_axi_rdata[72] = \ ; assign s_axi_rdata[71] = \ ; assign s_axi_rdata[70] = \ ; assign s_axi_rdata[69] = \ ; assign s_axi_rdata[68] = \ ; assign s_axi_rdata[67] = \ ; assign s_axi_rdata[66] = \ ; assign s_axi_rdata[65] = \ ; assign s_axi_rdata[64] = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[3] = \ ; assign s_axi_rid[2] = \ ; assign s_axi_rid[1] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_sbiterr = \ ; assign s_axi_wready = \ ; assign sbiterr = \ ; GND GND (.G(\ )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [255:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [63:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:41:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_stub.v // Design : input_line_buffer // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, clkb, addrb, doutb) /* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[63:0],clkb,addrb[9:0],doutb[255:0]" */; input clka; input ena; input [0:0]wea; input [11:0]addra; input [63:0]dina; input clkb; input [9:0]addrb; output [255:0]doutb; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/dont_touch.xdc ================================================ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. # IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci # IP: The module: 'output_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'output_line_buffer'. Do not add the DONT_TOUCH constraint. set_property DONT_TOUCH TRUE [get_cells U0] # IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci # IP: The module: 'output_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'output_line_buffer'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells U0] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer.tcl ================================================ # # Synthesis run script generated by Vivado # set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k325tffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info set_property webtalk.parent_dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/wt [current_project] set_property parent.project_path /home/dave/ip/examples/framebuffer_test/framebuffer_test.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_ip -quiet /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci set_property is_locked true [get_files /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci] foreach dcp [get_files -quiet -all *.dcp] { set_property used_in_implementation false $dcp } read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1 -new_name output_line_buffer -ip [get_ips output_line_buffer]] if { $cached_ip eq {} } { synth_design -top output_line_buffer -part xc7k325tffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache #--------------------------------------------------------- catch { write_checkpoint -force -noxdef -rename_prefix output_line_buffer_ output_line_buffer.dcp set ipCachedFiles {} write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_stub.v lappend ipCachedFiles output_line_buffer_stub.v write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_stub.vhdl lappend ipCachedFiles output_line_buffer_stub.vhdl write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_sim_netlist.v lappend ipCachedFiles output_line_buffer_sim_netlist.v write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_sim_netlist.vhdl lappend ipCachedFiles output_line_buffer_sim_netlist.vhdl config_ip_cache -add -dcp output_line_buffer.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips output_line_buffer] } rename_ref -prefix_all output_line_buffer_ write_checkpoint -force -noxdef output_line_buffer.dcp catch { report_utilization -file output_line_buffer_utilization_synth.rpt -pb output_line_buffer_utilization_synth.pb } if { [catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { write_verilog -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { write_verilog -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { write_vhdl -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } } else { if { [catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp } _RESULT ] } { send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } }; # end if cached_ip if {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer]} { catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer } } if {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer]} { catch { file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer } } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:42:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_sim_netlist.v // Design : output_line_buffer // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "output_line_buffer,blk_mem_gen_v8_3_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (clka, ena, wea, addra, dina, clkb, addrb, doutb); (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [255:0]dina; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [11:0]addrb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [63:0]doutb; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_rsta_busy_UNCONNECTED; wire NLW_U0_rstb_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_dbiterr_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_sbiterr_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire [255:0]NLW_U0_douta_UNCONNECTED; wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED; wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; (* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 33.580152 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "output_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "4096" *) (* C_READ_WIDTH_A = "256" *) (* C_READ_WIDTH_B = "64" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "4096" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "256" *) (* C_WRITE_WIDTH_B = "64" *) (* C_XDEVICEFAMILY = "kintex7" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 U0 (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .deepsleep(1'b0), .dina(dina), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(NLW_U0_douta_UNCONNECTED[255:0]), .doutb(doutb), .eccpipece(1'b0), .ena(ena), .enb(1'b0), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]), .regcea(1'b0), .regceb(1'b0), .rsta(1'b0), .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), .rstb(1'b0), .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), .s_aclk(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), .s_axi_injectdbiterr(1'b0), .s_axi_injectsbiterr(1'b0), .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb(1'b0), .s_axi_wvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .shutdown(1'b0), .sleep(1'b0), .wea(wea), .web(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [63:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [255:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[195:192],dina[131:128],dina[67:64],dina[3:0]}), .doutb(doutb[3:0]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[204:196],dina[140:132],dina[76:68],dina[12:4]}), .doutb(doutb[12:4]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[213:205],dina[149:141],dina[85:77],dina[21:13]}), .doutb(doutb[21:13]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[222:214],dina[158:150],dina[94:86],dina[30:22]}), .doutb(doutb[30:22]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[231:223],dina[167:159],dina[103:95],dina[39:31]}), .doutb(doutb[39:31]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[240:232],dina[176:168],dina[112:104],dina[48:40]}), .doutb(doutb[48:40]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[249:241],dina[185:177],dina[121:113],dina[57:49]}), .doutb(doutb[57:49]), .ena(ena), .wea(wea)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[255:250],dina[191:186],dina[127:122],dina[63:58]}), .doutb(doutb[63:58]), .ena(ena), .wea(wea)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [3:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [15:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [15:0]dina; wire [3:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [5:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [23:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [23:0]dina; wire [5:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [3:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [15:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [15:0]dina; wire [3:0]doutb; wire ena; wire [0:0]wea; wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(4), .READ_WIDTH_B(4), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(18)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({addrb,1'b0,1'b0}), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DIADI(dina), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],doutb}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(ena), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [5:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [23:0]dina; input [0:0]wea; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [23:0]dina; wire [5:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,dina[23:18],1'b0,1'b0,dina[17:12],1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [63:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [255:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 33.580152 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "output_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "4096" *) (* C_READ_WIDTH_A = "256" *) (* C_READ_WIDTH_B = "64" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "4096" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "256" *) (* C_WRITE_WIDTH_B = "64" *) (* C_XDEVICEFAMILY = "kintex7" *) (* downgradeipidentifiedwarnings = "yes" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 (clka, rsta, ena, regcea, wea, addra, dina, douta, clkb, rstb, enb, regceb, web, addrb, dinb, doutb, injectsbiterr, injectdbiterr, eccpipece, sbiterr, dbiterr, rdaddrecc, sleep, deepsleep, shutdown, rsta_busy, rstb_busy, s_aclk, s_aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, s_axi_injectsbiterr, s_axi_injectdbiterr, s_axi_sbiterr, s_axi_dbiterr, s_axi_rdaddrecc); input clka; input rsta; input ena; input regcea; input [0:0]wea; input [9:0]addra; input [255:0]dina; output [255:0]douta; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [11:0]addrb; input [63:0]dinb; output [63:0]doutb; input injectsbiterr; input injectdbiterr; input eccpipece; output sbiterr; output dbiterr; output [11:0]rdaddrecc; input sleep; input deepsleep; input shutdown; output rsta_busy; output rstb_busy; input s_aclk; input s_aresetn; input [3:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input s_axi_awvalid; output s_axi_awready; input [255:0]s_axi_wdata; input [0:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; output [3:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input s_axi_bready; input [3:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input s_axi_arvalid; output s_axi_arready; output [3:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; input s_axi_rready; input s_axi_injectsbiterr; input s_axi_injectdbiterr; output s_axi_sbiterr; output s_axi_dbiterr; output [11:0]s_axi_rdaddrecc; wire \ ; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; assign dbiterr = \ ; assign douta[255] = \ ; assign douta[254] = \ ; assign douta[253] = \ ; assign douta[252] = \ ; assign douta[251] = \ ; assign douta[250] = \ ; assign douta[249] = \ ; assign douta[248] = \ ; assign douta[247] = \ ; assign douta[246] = \ ; assign douta[245] = \ ; assign douta[244] = \ ; assign douta[243] = \ ; assign douta[242] = \ ; assign douta[241] = \ ; assign douta[240] = \ ; assign douta[239] = \ ; assign douta[238] = \ ; assign douta[237] = \ ; assign douta[236] = \ ; assign douta[235] = \ ; assign douta[234] = \ ; assign douta[233] = \ ; assign douta[232] = \ ; assign douta[231] = \ ; assign douta[230] = \ ; assign douta[229] = \ ; assign douta[228] = \ ; assign douta[227] = \ ; assign douta[226] = \ ; assign douta[225] = \ ; assign douta[224] = \ ; assign douta[223] = \ ; assign douta[222] = \ ; assign douta[221] = \ ; assign douta[220] = \ ; assign douta[219] = \ ; assign douta[218] = \ ; assign douta[217] = \ ; assign douta[216] = \ ; assign douta[215] = \ ; assign douta[214] = \ ; assign douta[213] = \ ; assign douta[212] = \ ; assign douta[211] = \ ; assign douta[210] = \ ; assign douta[209] = \ ; assign douta[208] = \ ; assign douta[207] = \ ; assign douta[206] = \ ; assign douta[205] = \ ; assign douta[204] = \ ; assign douta[203] = \ ; assign douta[202] = \ ; assign douta[201] = \ ; assign douta[200] = \ ; assign douta[199] = \ ; assign douta[198] = \ ; assign douta[197] = \ ; assign douta[196] = \ ; assign douta[195] = \ ; assign douta[194] = \ ; assign douta[193] = \ ; assign douta[192] = \ ; assign douta[191] = \ ; assign douta[190] = \ ; assign douta[189] = \ ; assign douta[188] = \ ; assign douta[187] = \ ; assign douta[186] = \ ; assign douta[185] = \ ; assign douta[184] = \ ; assign douta[183] = \ ; assign douta[182] = \ ; assign douta[181] = \ ; assign douta[180] = \ ; assign douta[179] = \ ; assign douta[178] = \ ; assign douta[177] = \ ; assign douta[176] = \ ; assign douta[175] = \ ; assign douta[174] = \ ; assign douta[173] = \ ; assign douta[172] = \ ; assign douta[171] = \ ; assign douta[170] = \ ; assign douta[169] = \ ; assign douta[168] = \ ; assign douta[167] = \ ; assign douta[166] = \ ; assign douta[165] = \ ; assign douta[164] = \ ; assign douta[163] = \ ; assign douta[162] = \ ; assign douta[161] = \ ; assign douta[160] = \ ; assign douta[159] = \ ; assign douta[158] = \ ; assign douta[157] = \ ; assign douta[156] = \ ; assign douta[155] = \ ; assign douta[154] = \ ; assign douta[153] = \ ; assign douta[152] = \ ; assign douta[151] = \ ; assign douta[150] = \ ; assign douta[149] = \ ; assign douta[148] = \ ; assign douta[147] = \ ; assign douta[146] = \ ; assign douta[145] = \ ; assign douta[144] = \ ; assign douta[143] = \ ; assign douta[142] = \ ; assign douta[141] = \ ; assign douta[140] = \ ; assign douta[139] = \ ; assign douta[138] = \ ; assign douta[137] = \ ; assign douta[136] = \ ; assign douta[135] = \ ; assign douta[134] = \ ; assign douta[133] = \ ; assign douta[132] = \ ; assign douta[131] = \ ; assign douta[130] = \ ; assign douta[129] = \ ; assign douta[128] = \ ; assign douta[127] = \ ; assign douta[126] = \ ; assign douta[125] = \ ; assign douta[124] = \ ; assign douta[123] = \ ; assign douta[122] = \ ; assign douta[121] = \ ; assign douta[120] = \ ; assign douta[119] = \ ; assign douta[118] = \ ; assign douta[117] = \ ; assign douta[116] = \ ; assign douta[115] = \ ; assign douta[114] = \ ; assign douta[113] = \ ; assign douta[112] = \ ; assign douta[111] = \ ; assign douta[110] = \ ; assign douta[109] = \ ; assign douta[108] = \ ; assign douta[107] = \ ; assign douta[106] = \ ; assign douta[105] = \ ; assign douta[104] = \ ; assign douta[103] = \ ; assign douta[102] = \ ; assign douta[101] = \ ; assign douta[100] = \ ; assign douta[99] = \ ; assign douta[98] = \ ; assign douta[97] = \ ; assign douta[96] = \ ; assign douta[95] = \ ; assign douta[94] = \ ; assign douta[93] = \ ; assign douta[92] = \ ; assign douta[91] = \ ; assign douta[90] = \ ; assign douta[89] = \ ; assign douta[88] = \ ; assign douta[87] = \ ; assign douta[86] = \ ; assign douta[85] = \ ; assign douta[84] = \ ; assign douta[83] = \ ; assign douta[82] = \ ; assign douta[81] = \ ; assign douta[80] = \ ; assign douta[79] = \ ; assign douta[78] = \ ; assign douta[77] = \ ; assign douta[76] = \ ; assign douta[75] = \ ; assign douta[74] = \ ; assign douta[73] = \ ; assign douta[72] = \ ; assign douta[71] = \ ; assign douta[70] = \ ; assign douta[69] = \ ; assign douta[68] = \ ; assign douta[67] = \ ; assign douta[66] = \ ; assign douta[65] = \ ; assign douta[64] = \ ; assign douta[63] = \ ; assign douta[62] = \ ; assign douta[61] = \ ; assign douta[60] = \ ; assign douta[59] = \ ; assign douta[58] = \ ; assign douta[57] = \ ; assign douta[56] = \ ; assign douta[55] = \ ; assign douta[54] = \ ; assign douta[53] = \ ; assign douta[52] = \ ; assign douta[51] = \ ; assign douta[50] = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign rdaddrecc[11] = \ ; assign rdaddrecc[10] = \ ; assign rdaddrecc[9] = \ ; assign rdaddrecc[8] = \ ; assign rdaddrecc[7] = \ ; assign rdaddrecc[6] = \ ; assign rdaddrecc[5] = \ ; assign rdaddrecc[4] = \ ; assign rdaddrecc[3] = \ ; assign rdaddrecc[2] = \ ; assign rdaddrecc[1] = \ ; assign rdaddrecc[0] = \ ; assign rsta_busy = \ ; assign rstb_busy = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[3] = \ ; assign s_axi_bid[2] = \ ; assign s_axi_bid[1] = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_dbiterr = \ ; assign s_axi_rdaddrecc[11] = \ ; assign s_axi_rdaddrecc[10] = \ ; assign s_axi_rdaddrecc[9] = \ ; assign s_axi_rdaddrecc[8] = \ ; assign s_axi_rdaddrecc[7] = \ ; assign s_axi_rdaddrecc[6] = \ ; assign s_axi_rdaddrecc[5] = \ ; assign s_axi_rdaddrecc[4] = \ ; assign s_axi_rdaddrecc[3] = \ ; assign s_axi_rdaddrecc[2] = \ ; assign s_axi_rdaddrecc[1] = \ ; assign s_axi_rdaddrecc[0] = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[3] = \ ; assign s_axi_rid[2] = \ ; assign s_axi_rid[1] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_sbiterr = \ ; assign s_axi_wready = \ ; assign sbiterr = \ ; GND GND (.G(\ )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [63:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [255:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:42:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_stub.v // Design : output_line_buffer // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, clkb, addrb, doutb) /* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[255:0],clkb,addrb[11:0],doutb[63:0]" */; input clka; input ena; input [0:0]wea; input [9:0]addra; input [255:0]dina; input clkb; input [11:0]addrb; output [63:0]doutb; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/synth_1/.Xil/ov13850_demo_propImpl.xdc ================================================ set_property SRC_FILE_INFO {cfile:/home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc rfile:../../../ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc id:1} [current_design] set_property SRC_FILE_INFO {cfile:/home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc rfile:../../../ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc id:2} [current_design] set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA20 [get_ports {hdmi_clk[1]}] set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC20 [get_ports {hdmi_d0[1]}] set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA22 [get_ports {hdmi_d1[1]}] set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AB24 [get_ports {hdmi_d2[1]}] set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN R19 [get_ports reset_n] set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD12 [get_ports clock_p] set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P27 [get_ports zoom_mode] set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P26 [get_ports freeze] set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN D26 [get_ports {csi0_clk[1]}] set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN B30 [get_ports {csi0_d1[1]}] set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN B28 [get_ports {csi0_d3[1]}] set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN D29 [get_ports {csi0_d0[1]}] set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN B27 [get_ports {csi0_d2[1]}] set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN M28 [get_ports cam_mclk] set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN L28 [get_ports cam_i2c_sck] set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN J29 [get_ports cam_i2c_sda] set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN N21 [get_ports cam_rstn] set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] set_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}] set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] set_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] -clock_fall 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}] set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH20 [get_ports {vga_b[0]}] set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG20 [get_ports {vga_b[1]}] set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF21 [get_ports {vga_b[2]}] set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK20 [get_ports {vga_b[3]}] set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG22 [get_ports {vga_b[4]}] set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ23 [get_ports {vga_g[0]}] set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ22 [get_ports {vga_g[1]}] set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH22 [get_ports {vga_g[2]}] set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK21 [get_ports {vga_g[3]}] set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ21 [get_ports {vga_g[4]}] set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK23 [get_ports {vga_g[5]}] set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF20 [get_ports vga_hsync] set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK25 [get_ports {vga_r[0]}] set_property src_info {type:XDC file:1 line:79 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG25 [get_ports {vga_r[1]}] set_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH25 [get_ports {vga_r[2]}] set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK24 [get_ports {vga_r[3]}] set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ24 [get_ports {vga_r[4]}] set_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG23 [get_ports vga_vsync] set_property src_info {type:XDC file:2 line:34 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}] set_property src_info {type:XDC file:2 line:39 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}] set_property src_info {type:XDC file:2 line:44 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}] set_property src_info {type:XDC file:2 line:49 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}] set_property src_info {type:XDC file:2 line:54 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}] set_property src_info {type:XDC file:2 line:59 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}] set_property src_info {type:XDC file:2 line:64 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}] set_property src_info {type:XDC file:2 line:69 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}] set_property src_info {type:XDC file:2 line:74 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}] set_property src_info {type:XDC file:2 line:79 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}] set_property src_info {type:XDC file:2 line:84 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}] set_property src_info {type:XDC file:2 line:89 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}] set_property src_info {type:XDC file:2 line:94 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}] set_property src_info {type:XDC file:2 line:99 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}] set_property src_info {type:XDC file:2 line:104 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}] set_property src_info {type:XDC file:2 line:109 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}] set_property src_info {type:XDC file:2 line:114 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}] set_property src_info {type:XDC file:2 line:119 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}] set_property src_info {type:XDC file:2 line:124 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}] set_property src_info {type:XDC file:2 line:129 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}] set_property src_info {type:XDC file:2 line:134 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}] set_property src_info {type:XDC file:2 line:139 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}] set_property src_info {type:XDC file:2 line:144 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}] set_property src_info {type:XDC file:2 line:149 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}] set_property src_info {type:XDC file:2 line:154 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}] set_property src_info {type:XDC file:2 line:159 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}] set_property src_info {type:XDC file:2 line:164 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}] set_property src_info {type:XDC file:2 line:169 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}] set_property src_info {type:XDC file:2 line:174 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}] set_property src_info {type:XDC file:2 line:179 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}] set_property src_info {type:XDC file:2 line:184 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}] set_property src_info {type:XDC file:2 line:189 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}] set_property src_info {type:XDC file:2 line:194 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}] set_property src_info {type:XDC file:2 line:199 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}] set_property src_info {type:XDC file:2 line:204 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}] set_property src_info {type:XDC file:2 line:209 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}] set_property src_info {type:XDC file:2 line:214 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}] set_property src_info {type:XDC file:2 line:219 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}] set_property src_info {type:XDC file:2 line:224 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}] set_property src_info {type:XDC file:2 line:229 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}] set_property src_info {type:XDC file:2 line:234 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}] set_property src_info {type:XDC file:2 line:239 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}] set_property src_info {type:XDC file:2 line:244 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}] set_property src_info {type:XDC file:2 line:249 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}] set_property src_info {type:XDC file:2 line:254 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}] set_property src_info {type:XDC file:2 line:259 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}] set_property src_info {type:XDC file:2 line:264 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}] set_property src_info {type:XDC file:2 line:269 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}] set_property src_info {type:XDC file:2 line:274 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}] set_property src_info {type:XDC file:2 line:279 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}] set_property src_info {type:XDC file:2 line:284 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AE11 [get_ports ddr3_ras_n] set_property src_info {type:XDC file:2 line:289 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF11 [get_ports ddr3_cas_n] set_property src_info {type:XDC file:2 line:294 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG13 [get_ports ddr3_we_n] set_property src_info {type:XDC file:2 line:299 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG5 [get_ports ddr3_reset_n] set_property src_info {type:XDC file:2 line:304 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}] set_property src_info {type:XDC file:2 line:309 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}] set_property src_info {type:XDC file:2 line:314 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}] set_property src_info {type:XDC file:2 line:319 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}] set_property src_info {type:XDC file:2 line:324 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}] set_property src_info {type:XDC file:2 line:329 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}] set_property src_info {type:XDC file:2 line:334 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}] set_property src_info {type:XDC file:2 line:343 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}] set_property src_info {type:XDC file:2 line:344 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}] set_property src_info {type:XDC file:2 line:353 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}] set_property src_info {type:XDC file:2 line:354 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}] set_property src_info {type:XDC file:2 line:363 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}] set_property src_info {type:XDC file:2 line:364 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}] set_property src_info {type:XDC file:2 line:373 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}] set_property src_info {type:XDC file:2 line:374 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}] set_property src_info {type:XDC file:2 line:383 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}] set_property src_info {type:XDC file:2 line:384 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}] set_property src_info {type:XDC file:2 line:388 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] set_property src_info {type:XDC file:2 line:389 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] set_property src_info {type:XDC file:2 line:390 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] set_property src_info {type:XDC file:2 line:391 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] set_property src_info {type:XDC file:2 line:392 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] set_property src_info {type:XDC file:2 line:393 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] set_property src_info {type:XDC file:2 line:394 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] set_property src_info {type:XDC file:2 line:395 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] set_property src_info {type:XDC file:2 line:401 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] set_property src_info {type:XDC file:2 line:402 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] set_property src_info {type:XDC file:2 line:403 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] set_property src_info {type:XDC file:2 line:404 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] set_property src_info {type:XDC file:2 line:408 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] set_property src_info {type:XDC file:2 line:409 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] set_property src_info {type:XDC file:2 line:410 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] set_property src_info {type:XDC file:2 line:411 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] set_property src_info {type:XDC file:2 line:412 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] set_property src_info {type:XDC file:2 line:413 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] set_property src_info {type:XDC file:2 line:414 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] set_property src_info {type:XDC file:2 line:415 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] set_property src_info {type:XDC file:2 line:417 export:INPUT save:INPUT read:READ} [current_design] set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] set_property src_info {type:XDC file:2 line:418 export:INPUT save:INPUT read:READ} [current_design] set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] set_property src_info {type:XDC file:2 line:419 export:INPUT save:INPUT read:READ} [current_design] set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] set_property src_info {type:XDC file:2 line:420 export:INPUT save:INPUT read:READ} [current_design] set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] set_property src_info {type:XDC file:2 line:422 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}] set_property src_info {type:XDC file:2 line:423 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] set_property src_info {type:XDC file:2 line:425 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}] set_property src_info {type:XDC file:2 line:426 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] set_property src_info {type:XDC file:2 line:428 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] set_property src_info {type:XDC file:2 line:429 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] set_property src_info {type:XDC file:2 line:430 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] set_property src_info {type:XDC file:2 line:431 export:INPUT save:INPUT read:READ} [current_design] set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] set_property src_info {type:XDC file:2 line:433 export:INPUT save:INPUT read:READ} [current_design] set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] set_property src_info {type:XDC file:2 line:434 export:INPUT save:INPUT read:READ} [current_design] set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] set_property src_info {type:XDC file:2 line:437 export:INPUT save:INPUT read:READ} [current_design] set_multicycle_path -setup -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 6 set_property src_info {type:XDC file:2 line:439 export:INPUT save:INPUT read:READ} [current_design] set_multicycle_path -hold -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 5 set_property src_info {type:XDC file:2 line:441 export:INPUT save:INPUT read:READ} [current_design] set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] set_property src_info {type:XDC file:2 line:443 export:INPUT save:INPUT read:READ} [current_design] set_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2 set_property src_info {type:XDC file:2 line:444 export:INPUT save:INPUT read:READ} [current_design] set_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1 set_property src_info {type:XDC file:2 line:446 export:INPUT save:INPUT read:READ} [current_design] set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000 set_property src_info {type:XDC file:2 line:447 export:INPUT save:INPUT read:READ} [current_design] set_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000 set_property src_info {type:XDC file:2 line:448 export:INPUT save:INPUT read:READ} [current_design] set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] set_property src_info {type:XDC file:2 line:450 export:INPUT save:INPUT read:READ} [current_design] set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/synth_1/ov13850_demo.tcl ================================================ # # Synthesis run script generated by Vivado # set_param xicom.use_bs_reader 1 set_msg_config -id {HDL 9-1061} -limit 100000 set_msg_config -id {HDL 9-1654} -limit 100000 create_project -in_memory -part xc7k325tffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project] set_property parent.project_path /home/dave/ip/examples/ov13850_demo/ov13850_demo.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property ip_output_repo /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] add_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp] add_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp] add_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp] add_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp] add_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp] read_vhdl -library xil_defaultlib { /home/dave/ip/mipi-csi-rx/csi_rx_line_buffer.vhd /home/dave/ip/mipi-csi-rx/csi_rx_word_align.vhd /home/dave/ip/mipi-csi-rx/csi_rx_idelayctrl_gen.vhd /home/dave/ip/mipi-csi-rx/csi_rx_hs_lane_phy.vhd /home/dave/ip/mipi-csi-rx/csi_rx_hs_clk_phy.vhd /home/dave/ip/mipi-csi-rx/csi_rx_hdr_ecc.vhd /home/dave/ip/mipi-csi-rx/csi_rx_clock_det.vhd /home/dave/ip/mipi-csi-rx/csi_rx_byte_align.vhd /home/dave/ip/video-misc/video_timing_ctrl.vhd /home/dave/ip/framebuffer-ctrl/framebuffer_ctrl.vhd /home/dave/ip/dvi-tx/dvi_tx_tmds_phy.vhd /home/dave/ip/dvi-tx/dvi_tx_tmds_enc.vhd /home/dave/ip/dvi-tx/dvi_tx_clk_drv.vhd /home/dave/ip/mipi-csi-rx/csi_rx_video_output.vhd /home/dave/ip/mipi-csi-rx/csi_rx_packet_handler.vhd /home/dave/ip/mipi-csi-rx/csi_rx_4_lane_link.vhd /home/dave/ip/mipi-csi-rx/csi_rx_10bit_unpack.vhd /home/dave/ip/video-misc/video_fb_output.vhd /home/dave/ip/ov-cam-control/ov_i2c_control.vhd /home/dave/ip/ov-cam-control/ov13850_4k_regs.vhd /home/dave/ip/dvi-tx/dvi_tx_top.vhd /home/dave/ip/mipi-csi-rx/csi_rx_top.vhd /home/dave/ip/demo-top/framebuffer_top.vhd /home/dave/ip/video-misc/image_gain_wb.vhd /home/dave/ip/video-misc/simple_debayer.vhd /home/dave/ip/ov-cam-control/ov13850_control_top.vhd /home/dave/ip/demo-top/ov13850_demo.vhd } foreach dcp [get_files -quiet -all *.dcp] { set_property used_in_implementation false $dcp } read_xdc /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc] read_xdc /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc set_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc] synth_design -top ov13850_demo -part xc7k325tffg900-2 -retiming write_checkpoint -force -noxdef ov13850_demo.dcp catch { report_utilization -file ov13850_demo_utilization_synth.rpt -pb ov13850_demo_utilization_synth.pb } ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest.tcl ================================================ set curr_wave [current_wave_config] if { [string length $curr_wave] == 0 } { if { [llength [get_objects]] > 0} { add_wave / set_property needs_save false [current_wave_config] } else { send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." } } run 1000ns ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest_func_synth.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Sat Nov 12 16:53:04 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -mode funcsim -nolib -force -file // /home/dave/ip/examples/framebuffer_test/framebuffer_test.sim/sim_1/synth/func/genesys2_fbtest_func_synth.v // Design : genesys2_fbtest // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps module camera_pll (camera_pixel_clock, sysclk); output camera_pixel_clock; input sysclk; wire camera_pixel_clock; wire sysclk; camera_pll_camera_pll_clk_wiz inst (.camera_pixel_clock(camera_pixel_clock), .sysclk(sysclk)); endmodule (* ORIG_REF_NAME = "camera_pll_clk_wiz" *) module camera_pll_camera_pll_clk_wiz (camera_pixel_clock, sysclk); output camera_pixel_clock; input sysclk; wire camera_pixel_clock; wire camera_pixel_clock_camera_pll; wire clkfbout_buf_camera_pll; wire clkfbout_camera_pll; wire sysclk; wire sysclk_camera_pll; wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED; wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* box_type = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_camera_pll), .O(clkfbout_buf_camera_pll)); (* box_type = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_camera_pll)); (* box_type = "PRIMITIVE" *) BUFG clkout1_buf (.I(camera_pixel_clock_camera_pll), .O(camera_pixel_clock)); (* box_type = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(17), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(2), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(1), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(4), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_adv_inst (.CLKFBIN(clkfbout_buf_camera_pll), .CLKFBOUT(clkfbout_camera_pll), .CLKIN1(sysclk_camera_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(camera_pixel_clock_camera_pll), .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED), .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED), .PWRDWN(1'b0), .RST(1'b0)); endmodule module ddr3_if (ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, init_calib_complete, device_temp, sys_rst); inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_n; inout [3:0]ddr3_dqs_p; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output ddr3_ras_n; output ddr3_cas_n; output ddr3_we_n; output ddr3_reset_n; output [0:0]ddr3_ck_p; output [0:0]ddr3_ck_n; output [0:0]ddr3_cke; output [0:0]ddr3_cs_n; output [3:0]ddr3_dm; output [0:0]ddr3_odt; input sys_clk_i; output ui_clk; output ui_clk_sync_rst; output mmcm_locked; input aresetn; input app_sr_req; input app_ref_req; input app_zq_req; output app_sr_active; output app_ref_ack; output app_zq_ack; input [0:0]s_axi_awid; input [29:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input s_axi_awvalid; output s_axi_awready; input [255:0]s_axi_wdata; input [31:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; input s_axi_bready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input [0:0]s_axi_arid; input [29:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input s_axi_arvalid; output s_axi_arready; input s_axi_rready; output [0:0]s_axi_rid; output [255:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; output init_calib_complete; output [11:0]device_temp; input sys_rst; wire \ ; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire aresetn; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_ck_n; wire [0:0]ddr3_ck_p; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [11:0]device_temp; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete; wire \lim_state_reg[6]_i_23_n_0 ; wire mmcm_locked; wire [29:0]s_axi_araddr; wire [1:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [1:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [255:0]s_axi_rdata; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire [1:1]\^s_axi_rresp ; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire \stg2_target_r_reg[1]_i_2_n_0 ; wire stg3_dec2init_val_r_reg_i_11_n_0; wire sys_clk_i; wire sys_rst; wire u_ddr3_if_mig_n_112; wire u_ddr3_if_mig_n_113; wire u_ddr3_if_mig_n_127; wire [49:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address ; wire [11:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank ; wire [2:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n ; wire [3:3]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ; wire [2:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n ; wire [0:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ; wire [1:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ; wire [2:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ; wire [23:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ; wire [59:2]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ; wire [77:2]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ; wire ui_clk; wire ui_clk_sync_rst; wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_rresp[1] = \^s_axi_rresp [1]; assign s_axi_rresp[0] = \ ; GND GND (.G(\ )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]), .DIB({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [1:0]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:2]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [5:4]), .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [13:12]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:14]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22]), .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [1:0]), .DIC({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [2]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [7:6]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [9:8]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [11:10]), .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}), .DIC({init_calib_complete,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [31:30]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [33:32]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:34]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [43:42]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [45:44]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [47:46]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:2]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:4]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [1:0]), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [13:12]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [15:14]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [2]}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ), .DIB({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [65:64]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33]}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:66]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [69:68]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [71:70]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [3:2]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:4]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7]}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [73:72]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:74]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:76]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); LUT1 #( .INIT(2'h1)) \lim_state_reg[6]_i_23 (.I0(u_ddr3_if_mig_n_113), .O(\lim_state_reg[6]_i_23_n_0 )); LUT1 #( .INIT(2'h1)) \stg2_target_r_reg[1]_i_2 (.I0(u_ddr3_if_mig_n_127), .O(\stg2_target_r_reg[1]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) stg3_dec2init_val_r_reg_i_11 (.I0(u_ddr3_if_mig_n_112), .O(stg3_dec2init_val_r_reg_i_11_n_0)); ddr3_ifddr3_if_mig u_ddr3_if_mig (.CLKB0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ), .CLKB0_7(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ), .CLKB0_8(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ), .CLKB0_9(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ), .D(u_ddr3_if_mig_n_127), .Q(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .aresetn(aresetn), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}), .iserdes_clk(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ), .iserdes_clk_2(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ), .iserdes_clk_3(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ), .iserdes_clk_4(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ), .mem_out({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:0]}), .\mmcm_current_reg[0] (stg3_dec2init_val_r_reg_i_11_n_0), .\mmcm_init_trail_reg[0] (\lim_state_reg[6]_i_23_n_0 ), .mmcm_locked(mmcm_locked), .out(device_temp), .phy_dout({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,init_calib_complete,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}), .rd_ptr(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ), .rd_ptr_0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ), .rd_ptr_1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ), .\rd_ptr_reg[3] ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:12],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]}), .\rd_ptr_reg[3]_0 ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:42],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:30],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]}), .\rd_ptr_timing_reg[0] ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n }), .\rd_ptr_timing_reg[0]_0 ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]}), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst[1]), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst[1]), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .s_axi_rdata(s_axi_rdata), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rresp(\^s_axi_rresp ), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .stg3_dec2init_val_r_reg(u_ddr3_if_mig_n_112), .stg3_inc2init_val_r_reg(u_ddr3_if_mig_n_113), .\stg3_r_reg[0] (\stg2_target_r_reg[1]_i_2_n_0 ), .sys_clk_i(sys_clk_i), .sys_rst(sys_rst), .ui_clk(ui_clk), .ui_clk_sync_rst(ui_clk_sync_rst), .wr_en(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ), .wr_en_5(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ), .wr_en_6(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ), .\wr_ptr_timing_reg[2] (\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ), .\wr_ptr_timing_reg[2]_0 (\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr )); endmodule (* ORIG_REF_NAME = "ddr3_if_mig" *) module ddr3_ifddr3_if_mig (ui_clk, app_ref_ack, app_zq_ack, app_sr_active, ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, rd_ptr, rd_ptr_0, rd_ptr_1, ui_clk_sync_rst, iserdes_clk, iserdes_clk_2, iserdes_clk_3, iserdes_clk_4, phy_dout, out, mmcm_locked, \rd_ptr_timing_reg[0] , \rd_ptr_timing_reg[0]_0 , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, s_axi_arready, Q, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , D, wr_en, wr_en_5, wr_en_6, ddr_ck_out, s_axi_awready, s_axi_wready, s_axi_rdata, s_axi_rresp, s_axi_rid, s_axi_bid, s_axi_bvalid, s_axi_rvalid, s_axi_rlast, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, app_ref_req, app_zq_req, app_sr_req, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, mem_out, \rd_ptr_reg[3] , \rd_ptr_reg[3]_0 , sys_rst, s_axi_arvalid, sys_clk_i, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , \stg3_r_reg[0] , s_axi_awlen, s_axi_bready, s_axi_awvalid, s_axi_awaddr, s_axi_awburst, s_axi_wvalid, s_axi_awid, s_axi_arlen, s_axi_araddr, s_axi_arburst, s_axi_rready, s_axi_wstrb, s_axi_wdata, aresetn, s_axi_arid); output ui_clk; output app_ref_ack; output app_zq_ack; output app_sr_active; output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output [3:0]rd_ptr; output [3:0]rd_ptr_0; output [3:0]rd_ptr_1; output ui_clk_sync_rst; output iserdes_clk; output iserdes_clk_2; output iserdes_clk_3; output iserdes_clk_4; output [5:0]phy_dout; output [11:0]out; output mmcm_locked; output [37:0]\rd_ptr_timing_reg[0] ; output [4:0]\rd_ptr_timing_reg[0]_0 ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output s_axi_arready; output [3:0]Q; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [0:0]D; output wr_en; output wr_en_5; output wr_en_6; output [1:0]ddr_ck_out; output s_axi_awready; output s_axi_wready; output [255:0]s_axi_rdata; output [0:0]s_axi_rresp; output [0:0]s_axi_rid; output [0:0]s_axi_bid; output s_axi_bvalid; output s_axi_rvalid; output s_axi_rlast; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input app_ref_req; input app_zq_req; input app_sr_req; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input [29:0]\rd_ptr_reg[3]_0 ; input sys_rst; input s_axi_arvalid; input sys_clk_i; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input \stg3_r_reg[0] ; input [7:0]s_axi_awlen; input s_axi_bready; input s_axi_awvalid; input [29:0]s_axi_awaddr; input [0:0]s_axi_awburst; input s_axi_wvalid; input [0:0]s_axi_awid; input [7:0]s_axi_arlen; input [29:0]s_axi_araddr; input [0:0]s_axi_arburst; input s_axi_rready; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; input aresetn; input [0:0]s_axi_arid; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [3:0]Q; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire aresetn; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire freq_refclk; wire [1:1]iodelay_ctrl_rdy; wire iserdes_clk; wire iserdes_clk_2; wire iserdes_clk_3; wire iserdes_clk_4; wire \mem_intfc0/ddr_phy_top0/phy_mc_go ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ; wire [11:0]\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ; wire \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/rtp_timer_ns1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ; wire \mem_intfc0/mc0/bank_mach0/insert_maint_r ; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [11:0]out; wire [5:0]phy_dout; wire pll_locked; wire poc_sample_pd; wire psdone; wire psen; wire [3:0]rd_ptr; wire [3:0]rd_ptr_0; wire [3:0]rd_ptr_1; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [37:0]\rd_ptr_timing_reg[0] ; wire [4:0]\rd_ptr_timing_reg[0]_0 ; (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rst_sync_r1; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [255:0]s_axi_rdata; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire [0:0]s_axi_rresp; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_clk_i; wire sys_rst; wire sys_rst_act_hi; wire u_ddr3_clk_ibuf_n_0; wire u_ddr3_infrastructure_n_10; wire u_ddr3_infrastructure_n_11; wire u_ddr3_infrastructure_n_13; wire u_ddr3_infrastructure_n_14; wire u_ddr3_infrastructure_n_15; wire u_ddr3_infrastructure_n_16; wire u_ddr3_infrastructure_n_17; wire u_ddr3_infrastructure_n_18; wire u_ddr3_infrastructure_n_19; wire u_ddr3_infrastructure_n_20; wire u_ddr3_infrastructure_n_21; wire u_ddr3_infrastructure_n_22; wire u_ddr3_infrastructure_n_23; wire u_ddr3_infrastructure_n_24; wire u_ddr3_infrastructure_n_25; wire u_ddr3_infrastructure_n_26; wire u_ddr3_infrastructure_n_27; wire u_ddr3_infrastructure_n_28; wire u_ddr3_infrastructure_n_29; wire u_ddr3_infrastructure_n_30; wire u_ddr3_infrastructure_n_31; wire u_ddr3_infrastructure_n_32; wire u_ddr3_infrastructure_n_33; wire u_ddr3_infrastructure_n_34; wire u_ddr3_infrastructure_n_35; wire u_ddr3_infrastructure_n_36; wire u_ddr3_infrastructure_n_37; wire u_ddr3_infrastructure_n_39; wire u_ddr3_infrastructure_n_40; wire u_ddr3_infrastructure_n_42; wire u_ddr3_infrastructure_n_44; wire u_ddr3_infrastructure_n_45; wire u_ddr3_infrastructure_n_46; wire u_ddr3_infrastructure_n_47; wire u_ddr3_infrastructure_n_48; wire u_ddr3_infrastructure_n_49; wire u_ddr3_infrastructure_n_50; wire u_ddr3_infrastructure_n_52; wire u_ddr3_infrastructure_n_54; wire u_ddr3_infrastructure_n_9; wire u_memc_ui_top_axi_n_108; wire u_memc_ui_top_axi_n_111; wire u_memc_ui_top_axi_n_113; wire u_memc_ui_top_axi_n_114; wire u_memc_ui_top_axi_n_116; wire u_memc_ui_top_axi_n_117; wire u_memc_ui_top_axi_n_118; wire u_memc_ui_top_axi_n_61; wire ui_clk; wire ui_clk_sync_rst; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; ddr3_ifmig_7series_v4_0_tempmon \temp_mon_enabled.u_tempmon (.CLK(ui_clk), .D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ), .in0(ui_clk_sync_rst), .mmcm_clk(u_ddr3_clk_ibuf_n_0), .out(out)); ddr3_ifmig_7series_v4_0_clk_ibuf u_ddr3_clk_ibuf (.mmcm_clk(u_ddr3_clk_ibuf_n_0), .sys_clk_i(sys_clk_i)); ddr3_ifmig_7series_v4_0_infrastructure u_ddr3_infrastructure (.AS(sys_rst_act_hi), .CLK(ui_clk), .E(psen), .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ), .SR(u_ddr3_infrastructure_n_14), .SS(u_ddr3_infrastructure_n_16), .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ), .cal2_if_reset_reg(u_ddr3_infrastructure_n_18), .cal2_prech_req_r_reg(u_ddr3_infrastructure_n_19), .\cal2_state_r_reg[0] (u_ddr3_infrastructure_n_17), .cnt_pwron_reset_done_r0(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ), .\complex_address_reg[0] (u_ddr3_infrastructure_n_24), .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (u_ddr3_infrastructure_n_23), .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_ddr3_infrastructure_n_50), .\en_cnt_div4.wrlvl_odt_reg (u_memc_ui_top_axi_n_116), .fine_adjust_reg(u_memc_ui_top_axi_n_61), .\first_fail_taps_reg[0] (u_ddr3_infrastructure_n_26), .freq_refclk(freq_refclk), .\gen_final_tap[2].final_val_reg[2][1] (u_ddr3_infrastructure_n_29), .in0(ui_clk_sync_rst), .\init_state_r_reg[6] (u_ddr3_infrastructure_n_25), .insert_maint_r(\mem_intfc0/mc0/bank_mach0/insert_maint_r ), .\last_master_r_reg[2] (u_ddr3_infrastructure_n_33), .\lim_state_reg[0] (u_memc_ui_top_axi_n_113), .mem_refclk(mem_refclk), .mmcm_clk(u_ddr3_clk_ibuf_n_0), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .\oneeighty_r_reg[0] (u_ddr3_infrastructure_n_37), .\oneeighty_r_reg[0]_0 (u_ddr3_infrastructure_n_40), .p_81_in(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ), .pass_open_bank_r(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ), .pass_open_bank_r_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ), .phy_mc_go(\mem_intfc0/ddr_phy_top0/phy_mc_go ), .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ), .\pi_rdval_cnt_reg[0] ({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}), .\pi_rst_stg1_cal_r_reg[1] (u_ddr3_infrastructure_n_47), .pll_locked(pll_locked), .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ), .poc_backup_r_reg(u_memc_ui_top_axi_n_114), .poc_sample_pd(poc_sample_pd), .prbs_found_1st_edge_r_reg(u_ddr3_infrastructure_n_21), .pre_wait_r_reg(u_ddr3_infrastructure_n_42), .psdone(psdone), .ras_timer_zero_r_reg(u_ddr3_infrastructure_n_45), .ras_timer_zero_r_reg_0(u_ddr3_infrastructure_n_46), .\read_fifo.head_r_reg[0] (u_ddr3_infrastructure_n_13), .reset_reg(u_ddr3_infrastructure_n_10), .\resume_wait_r_reg[10] (u_memc_ui_top_axi_n_108), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (u_ddr3_infrastructure_n_34), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (u_ddr3_infrastructure_n_44), .\row_cnt_victim_rotate.complex_row_cnt_reg[7] (u_memc_ui_top_axi_n_118), .rst_out_reg(u_ddr3_infrastructure_n_22), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (u_memc_ui_top_axi_n_111), .rst_sync_r1(rst_sync_r1), .rtp_timer_ns1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/rtp_timer_ns1 ), .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ), .\samp_edge_cnt0_r_reg[11] (u_ddr3_infrastructure_n_48), .\simp_stg3_final_r_reg[17] (u_ddr3_infrastructure_n_11), .sm_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ), .\stg3_r_reg[1] (u_ddr3_infrastructure_n_39), .\stg3_tap_cnt_reg[0] (u_ddr3_infrastructure_n_9), .sync_pulse(sync_pulse), .\three_dec_max_limit_reg[11] (u_ddr3_infrastructure_n_20), .\victim_sel_rotate.sel_reg[31] (u_ddr3_infrastructure_n_32), .\wait_cnt_r_reg[3] (u_ddr3_infrastructure_n_49), .\wait_cnt_reg[3] (u_ddr3_infrastructure_n_35), .\wait_cnt_reg[3]_0 (u_ddr3_infrastructure_n_54), .\wl_tap_count_r_reg[0] ({u_ddr3_infrastructure_n_30,u_ddr3_infrastructure_n_31}), .wr_victim_inc_reg(u_memc_ui_top_axi_n_117), .\wr_victim_sel_ocal_reg[2] (u_ddr3_infrastructure_n_52), .\wrcal_dqs_cnt_r_reg[2] (u_ddr3_infrastructure_n_15), .\wrcal_reads_reg[0] (u_ddr3_infrastructure_n_36)); ddr3_ifmig_7series_v4_0_iodelay_ctrl u_iodelay_ctrl (.AS(sys_rst_act_hi), .mmcm_clk(u_ddr3_clk_ibuf_n_0), .rst_sync_r1_reg(iodelay_ctrl_rdy), .sys_rst(sys_rst)); (* x_core_info = "mig_7series_v4_0_ddr3_7Series, ddr3_if, 2016.2" *) ddr3_ifmig_7series_v4_0_memc_ui_top_axi u_memc_ui_top_axi (.CLK(ui_clk), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .D(D), .E(psen), .Q(Q), .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ), .SR(u_ddr3_infrastructure_n_14), .SS(u_ddr3_infrastructure_n_16), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .aresetn(aresetn), .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_reg(u_ddr3_infrastructure_n_45), .bm_end_r1_reg_0(u_ddr3_infrastructure_n_46), .cnt_pwron_reset_done_r0(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ), .\complex_row_cnt_ocal_reg[0] (u_memc_ui_top_axi_n_117), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .\device_temp_r_reg[11] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (iserdes_clk), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (iserdes_clk_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (iserdes_clk_3), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (iserdes_clk_4), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (u_memc_ui_top_axi_n_116), .fine_adjust_reg(u_ddr3_infrastructure_n_47), .freq_refclk(freq_refclk), .\generate_maint_cmds.insert_maint_r_lcl_reg (u_ddr3_infrastructure_n_44), .in0(ui_clk_sync_rst), .insert_maint_r(\mem_intfc0/mc0/bank_mach0/insert_maint_r ), .mem_out(mem_out), .mem_refclk(mem_refclk), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .out({s_axi_rresp,s_axi_rdata}), .p_81_in(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ), .pass_open_bank_r(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ), .pass_open_bank_r_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ), .pass_open_bank_r_lcl_reg(u_ddr3_infrastructure_n_42), .phy_dout(phy_dout), .phy_mc_go(\mem_intfc0/ddr_phy_top0/phy_mc_go ), .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ), .pi_cnt_dec_reg(u_ddr3_infrastructure_n_49), .\pi_rst_stg1_cal_r_reg[0] (u_memc_ui_top_axi_n_61), .pll_locked(pll_locked), .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ), .po_cnt_dec_reg(u_ddr3_infrastructure_n_54), .poc_sample_pd(poc_sample_pd), .psdone(psdone), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[0] (\rd_ptr_timing_reg[0] ), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0]_0 ), .\rd_ptr_timing_reg[2] (rd_ptr[3]), .\rd_ptr_timing_reg[2]_0 (rd_ptr[2]), .\rd_ptr_timing_reg[2]_1 (rd_ptr[1]), .\rd_ptr_timing_reg[2]_10 (rd_ptr_1[3]), .\rd_ptr_timing_reg[2]_2 (rd_ptr[0]), .\rd_ptr_timing_reg[2]_3 (rd_ptr_0[3]), .\rd_ptr_timing_reg[2]_4 (rd_ptr_0[2]), .\rd_ptr_timing_reg[2]_5 (rd_ptr_0[1]), .\rd_ptr_timing_reg[2]_6 (rd_ptr_0[0]), .\rd_ptr_timing_reg[2]_7 (rd_ptr_1[0]), .\rd_ptr_timing_reg[2]_8 (rd_ptr_1[1]), .\rd_ptr_timing_reg[2]_9 (rd_ptr_1[2]), .\resume_wait_r_reg[5] (u_memc_ui_top_axi_n_108), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (u_memc_ui_top_axi_n_118), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (iodelay_ctrl_rdy), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(u_memc_ui_top_axi_n_111), .rstdiv0_sync_r1_reg_rep__0(u_ddr3_infrastructure_n_13), .rstdiv0_sync_r1_reg_rep__10(u_ddr3_infrastructure_n_23), .rstdiv0_sync_r1_reg_rep__11(u_ddr3_infrastructure_n_24), .rstdiv0_sync_r1_reg_rep__12(u_ddr3_infrastructure_n_25), .rstdiv0_sync_r1_reg_rep__13(u_ddr3_infrastructure_n_26), .rstdiv0_sync_r1_reg_rep__14({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}), .rstdiv0_sync_r1_reg_rep__16(u_ddr3_infrastructure_n_29), .rstdiv0_sync_r1_reg_rep__17({u_ddr3_infrastructure_n_30,u_ddr3_infrastructure_n_31}), .rstdiv0_sync_r1_reg_rep__19(u_ddr3_infrastructure_n_32), .rstdiv0_sync_r1_reg_rep__2(u_ddr3_infrastructure_n_15), .rstdiv0_sync_r1_reg_rep__20(u_ddr3_infrastructure_n_33), .rstdiv0_sync_r1_reg_rep__21(u_ddr3_infrastructure_n_34), .rstdiv0_sync_r1_reg_rep__22(u_ddr3_infrastructure_n_35), .rstdiv0_sync_r1_reg_rep__23(u_ddr3_infrastructure_n_36), .rstdiv0_sync_r1_reg_rep__23_0(u_ddr3_infrastructure_n_50), .rstdiv0_sync_r1_reg_rep__23_1(u_ddr3_infrastructure_n_52), .rstdiv0_sync_r1_reg_rep__24(u_ddr3_infrastructure_n_37), .rstdiv0_sync_r1_reg_rep__25(u_ddr3_infrastructure_n_10), .rstdiv0_sync_r1_reg_rep__25_0(u_ddr3_infrastructure_n_11), .rstdiv0_sync_r1_reg_rep__25_1(u_ddr3_infrastructure_n_9), .rstdiv0_sync_r1_reg_rep__25_2(u_ddr3_infrastructure_n_39), .rstdiv0_sync_r1_reg_rep__4(u_ddr3_infrastructure_n_17), .rstdiv0_sync_r1_reg_rep__5(u_ddr3_infrastructure_n_18), .rstdiv0_sync_r1_reg_rep__6(u_ddr3_infrastructure_n_19), .rstdiv0_sync_r1_reg_rep__7(u_ddr3_infrastructure_n_20), .rstdiv0_sync_r1_reg_rep__8(u_ddr3_infrastructure_n_21), .rstdiv0_sync_r1_reg_rep__9(u_ddr3_infrastructure_n_22), .rtp_timer_ns1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/rtp_timer_ns1 ), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ), .samp_edge_cnt0_en_r_reg(u_ddr3_infrastructure_n_48), .sm_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ), .\sm_r_reg[0] (u_memc_ui_top_axi_n_114), .\sm_r_reg[0]_0 (u_ddr3_infrastructure_n_40), .\stg2_tap_cnt_reg[0] (u_memc_ui_top_axi_n_113), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_arb_mux" *) module ddr3_ifmig_7series_v4_0_arb_mux (\cmd_pipe_plus.mc_address_reg[0] , \cmd_pipe_plus.mc_cmd_reg[0] , DIC, col_data_buf_addr, cke_r, \rnk_config_strobe_r_reg[0] , \periodic_rd_generation.periodic_rd_timer_r_reg[0] , Q, read_this_rank, D, granted_col_r_reg, \rtw_timer.rtw_cnt_r_reg[1] , mc_odt_ns, col_rd_wr, mc_data_offset_2_ns, \cmd_pipe_plus.mc_cas_n_reg[2] , \cmd_pipe_plus.mc_address_reg[0]_0 , mc_cas_n_ns, \cmd_pipe_plus.mc_cs_n_reg[0] , mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[5] , \cmd_pipe_plus.mc_address_reg[25] , granted_row_r_reg, granted_col_r_reg_0, granted_col_r_reg_1, override_demand_ns, granted_row_r_reg_0, \wtr_timer.wtr_cnt_r_reg[2] , act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , demand_priority_r_reg, demand_priority_r_reg_0, \cmd_pipe_plus.mc_address_reg[10] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[7] , \cmd_pipe_plus.mc_bank_reg[6] , \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_address_reg[43] , \cmd_pipe_plus.mc_address_reg[42] , \cmd_pipe_plus.mc_address_reg[41] , \cmd_pipe_plus.mc_address_reg[39] , \cmd_pipe_plus.mc_address_reg[38] , \cmd_pipe_plus.mc_address_reg[37] , \cmd_pipe_plus.mc_address_reg[36] , \cmd_pipe_plus.mc_address_reg[35] , \cmd_pipe_plus.mc_address_reg[34] , \cmd_pipe_plus.mc_address_reg[33] , \cmd_pipe_plus.mc_address_reg[32] , \cmd_pipe_plus.mc_address_reg[31] , \cmd_pipe_plus.mc_address_reg[30] , \cmd_pipe_plus.mc_we_n_reg[2] , \cmd_pipe_plus.mc_cas_n_reg[2]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \generate_maint_cmds.insert_maint_r_lcl_reg , CLK, granted_row_ns, rnk_config_strobe_ns, granted_col_ns, granted_pre_ns, SR, mc_cke_ns, rnk_config_valid_r_lcl_reg, read_this_rank_r, rd_this_rank_r, rd_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, col_wait_r_reg, col_wait_r_reg_0, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, \rtw_timer.rtw_cnt_r_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_2_reg[3] , col_rd_wr_r1, auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, head_r_lcl_reg, head_r_lcl_reg_0, maint_zq_r, maint_srx_r, \grant_r_reg[1] , row_cmd_wr, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , req_row_r, act_wait_r_lcl_reg, inhbt_act_faw_r, ofs_rdy_r, ofs_rdy_r_0, wr_this_rank_r, req_data_buf_addr_r, \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , act_this_rank_r, req_periodic_rd_r, req_bank_rdy_r, req_bank_rdy_r_1, \req_col_r_reg[9] , \req_col_r_reg[9]_0 , auto_pre_r_lcl_reg_1, auto_pre_r_lcl_reg_2); output \cmd_pipe_plus.mc_address_reg[0] ; output \cmd_pipe_plus.mc_cmd_reg[0] ; output [0:0]DIC; output [4:0]col_data_buf_addr; output cke_r; output \rnk_config_strobe_r_reg[0] ; output \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; output [1:0]Q; output read_this_rank; output [1:0]D; output granted_col_r_reg; output \rtw_timer.rtw_cnt_r_reg[1] ; output [0:0]mc_odt_ns; output col_rd_wr; output [0:0]mc_data_offset_2_ns; output [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ; output [1:0]\cmd_pipe_plus.mc_address_reg[0]_0 ; output [1:0]mc_cas_n_ns; output \cmd_pipe_plus.mc_cs_n_reg[0] ; output [1:0]mc_ras_n_ns; output [5:0]\cmd_pipe_plus.mc_bank_reg[5] ; output [21:0]\cmd_pipe_plus.mc_address_reg[25] ; output granted_row_r_reg; output granted_col_r_reg_0; output granted_col_r_reg_1; output override_demand_ns; output granted_row_r_reg_0; output \wtr_timer.wtr_cnt_r_reg[2] ; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output demand_priority_r_reg; output demand_priority_r_reg_0; output \cmd_pipe_plus.mc_address_reg[10] ; output \cmd_pipe_plus.mc_bank_reg[8] ; output \cmd_pipe_plus.mc_bank_reg[7] ; output \cmd_pipe_plus.mc_bank_reg[6] ; output \cmd_pipe_plus.mc_address_reg[44] ; output \cmd_pipe_plus.mc_address_reg[43] ; output \cmd_pipe_plus.mc_address_reg[42] ; output \cmd_pipe_plus.mc_address_reg[41] ; output \cmd_pipe_plus.mc_address_reg[39] ; output \cmd_pipe_plus.mc_address_reg[38] ; output \cmd_pipe_plus.mc_address_reg[37] ; output \cmd_pipe_plus.mc_address_reg[36] ; output \cmd_pipe_plus.mc_address_reg[35] ; output \cmd_pipe_plus.mc_address_reg[34] ; output \cmd_pipe_plus.mc_address_reg[33] ; output \cmd_pipe_plus.mc_address_reg[32] ; output \cmd_pipe_plus.mc_address_reg[31] ; output \cmd_pipe_plus.mc_address_reg[30] ; output \cmd_pipe_plus.mc_we_n_reg[2] ; output \cmd_pipe_plus.mc_cas_n_reg[2]_0 ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input CLK; input granted_row_ns; input rnk_config_strobe_ns; input granted_col_ns; input granted_pre_ns; input [0:0]SR; input [0:0]mc_cke_ns; input rnk_config_valid_r_lcl_reg; input read_this_rank_r; input [1:0]rd_this_rank_r; input rd_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input col_wait_r_reg; input col_wait_r_reg_0; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_2_reg[3] ; input col_rd_wr_r1; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input head_r_lcl_reg; input head_r_lcl_reg_0; input maint_zq_r; input maint_srx_r; input \grant_r_reg[1] ; input [0:0]row_cmd_wr; input [2:0]\req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [27:0]req_row_r; input act_wait_r_lcl_reg; input inhbt_act_faw_r; input ofs_rdy_r; input ofs_rdy_r_0; input [1:0]wr_this_rank_r; input [9:0]req_data_buf_addr_r; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [1:0]act_this_rank_r; input [1:0]req_periodic_rd_r; input req_bank_rdy_r; input req_bank_rdy_r_1; input [6:0]\req_col_r_reg[9] ; input [6:0]\req_col_r_reg[9]_0 ; input auto_pre_r_lcl_reg_1; input auto_pre_r_lcl_reg_2; wire CLK; wire [1:0]D; wire [0:0]DIC; wire [1:0]Q; wire [0:0]SR; wire act_this_rank; wire [1:0]act_this_rank_r; wire act_wait_r_lcl_reg; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire cke_r; wire \cmd_pipe_plus.mc_address_reg[0] ; wire [1:0]\cmd_pipe_plus.mc_address_reg[0]_0 ; wire \cmd_pipe_plus.mc_address_reg[10] ; wire [21:0]\cmd_pipe_plus.mc_address_reg[25] ; wire \cmd_pipe_plus.mc_address_reg[30] ; wire \cmd_pipe_plus.mc_address_reg[31] ; wire \cmd_pipe_plus.mc_address_reg[32] ; wire \cmd_pipe_plus.mc_address_reg[33] ; wire \cmd_pipe_plus.mc_address_reg[34] ; wire \cmd_pipe_plus.mc_address_reg[35] ; wire \cmd_pipe_plus.mc_address_reg[36] ; wire \cmd_pipe_plus.mc_address_reg[37] ; wire \cmd_pipe_plus.mc_address_reg[38] ; wire \cmd_pipe_plus.mc_address_reg[39] ; wire \cmd_pipe_plus.mc_address_reg[41] ; wire \cmd_pipe_plus.mc_address_reg[42] ; wire \cmd_pipe_plus.mc_address_reg[43] ; wire \cmd_pipe_plus.mc_address_reg[44] ; wire [5:0]\cmd_pipe_plus.mc_bank_reg[5] ; wire \cmd_pipe_plus.mc_bank_reg[6] ; wire \cmd_pipe_plus.mc_bank_reg[7] ; wire \cmd_pipe_plus.mc_bank_reg[8] ; wire [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ; wire \cmd_pipe_plus.mc_cas_n_reg[2]_0 ; wire \cmd_pipe_plus.mc_cmd_reg[0] ; wire \cmd_pipe_plus.mc_cs_n_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_2_reg[3] ; wire \cmd_pipe_plus.mc_we_n_reg[2] ; wire [4:0]col_data_buf_addr; wire [4:4]col_data_buf_addr_r; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r1; wire col_wait_r_reg; wire col_wait_r_reg_0; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[1] ; wire granted_col_ns; wire granted_col_r_reg; wire granted_col_r_reg_0; wire granted_col_r_reg_1; wire granted_pre_ns; wire granted_row_ns; wire granted_row_r_reg; wire granted_row_r_reg_0; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire maint_srx_r; wire maint_zq_r; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cke_ns; wire [0:0]mc_data_offset_2_ns; wire [0:0]mc_odt_ns; wire [1:0]mc_ras_n_ns; wire ofs_rdy_r; wire ofs_rdy_r_0; wire override_demand_ns; wire \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; wire [1:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire read_this_rank; wire read_this_rank_r; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire req_bank_rdy_r; wire req_bank_rdy_r_1; wire [6:0]\req_col_r_reg[9] ; wire [6:0]\req_col_r_reg[9]_0 ; wire [9:0]req_data_buf_addr_r; wire [1:0]req_periodic_rd_r; wire [27:0]req_row_r; wire rnk_config_strobe_ns; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [1:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[2] ; ddr3_ifmig_7series_v4_0_arb_row_col arb_row_col0 (.CLK(CLK), .D(D), .DIC(DIC), .Q(Q), .SR(SR), .act_this_rank(act_this_rank), .act_this_rank_r(act_this_rank_r), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2), .\cmd_pipe_plus.mc_address_reg[0] (\cmd_pipe_plus.mc_address_reg[0] ), .\cmd_pipe_plus.mc_address_reg[0]_0 (\cmd_pipe_plus.mc_address_reg[0]_0 ), .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ), .\cmd_pipe_plus.mc_address_reg[25] (\cmd_pipe_plus.mc_address_reg[25] ), .\cmd_pipe_plus.mc_address_reg[30] (\cmd_pipe_plus.mc_address_reg[30] ), .\cmd_pipe_plus.mc_address_reg[31] (\cmd_pipe_plus.mc_address_reg[31] ), .\cmd_pipe_plus.mc_address_reg[32] (\cmd_pipe_plus.mc_address_reg[32] ), .\cmd_pipe_plus.mc_address_reg[33] (\cmd_pipe_plus.mc_address_reg[33] ), .\cmd_pipe_plus.mc_address_reg[34] (\cmd_pipe_plus.mc_address_reg[34] ), .\cmd_pipe_plus.mc_address_reg[35] (\cmd_pipe_plus.mc_address_reg[35] ), .\cmd_pipe_plus.mc_address_reg[36] (\cmd_pipe_plus.mc_address_reg[36] ), .\cmd_pipe_plus.mc_address_reg[37] (\cmd_pipe_plus.mc_address_reg[37] ), .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ), .\cmd_pipe_plus.mc_address_reg[39] (\cmd_pipe_plus.mc_address_reg[39] ), .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ), .\cmd_pipe_plus.mc_address_reg[42] (\cmd_pipe_plus.mc_address_reg[42] ), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] ), .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[5] ), .\cmd_pipe_plus.mc_bank_reg[6] (\cmd_pipe_plus.mc_bank_reg[6] ), .\cmd_pipe_plus.mc_bank_reg[7] (\cmd_pipe_plus.mc_bank_reg[7] ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] ), .\cmd_pipe_plus.mc_cas_n_reg[2]_0 (\cmd_pipe_plus.mc_cas_n_reg[2]_0 ), .\cmd_pipe_plus.mc_cmd_reg[0] (\cmd_pipe_plus.mc_cmd_reg[0] ), .\cmd_pipe_plus.mc_cs_n_reg[0] (\cmd_pipe_plus.mc_cs_n_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg[3] ), .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ), .col_data_buf_addr(col_data_buf_addr), .col_data_buf_addr_r(col_data_buf_addr_r), .col_periodic_rd_r(col_periodic_rd_r), .col_rd_wr(col_rd_wr), .col_rd_wr_r1(col_rd_wr_r1), .col_wait_r_reg(col_wait_r_reg), .col_wait_r_reg_0(col_wait_r_reg_0), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ), .demand_priority_r_reg(demand_priority_r_reg), .demand_priority_r_reg_0(demand_priority_r_reg_0), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\grant_r_reg[1] (\grant_r_reg[1] ), .granted_col_ns(granted_col_ns), .granted_col_r_reg_0(granted_col_r_reg), .granted_col_r_reg_1(granted_col_r_reg_0), .granted_col_r_reg_2(granted_col_r_reg_1), .granted_pre_ns(granted_pre_ns), .granted_row_ns(granted_row_ns), .granted_row_r_reg_0(granted_row_r_reg), .granted_row_r_reg_1(granted_row_r_reg_0), .head_r_lcl_reg(head_r_lcl_reg), .head_r_lcl_reg_0(head_r_lcl_reg_0), .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .mc_cas_n_ns(mc_cas_n_ns), .mc_data_offset_2_ns(mc_data_offset_2_ns), .mc_odt_ns(mc_odt_ns), .mc_ras_n_ns(mc_ras_n_ns), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r_0(ofs_rdy_r_0), .override_demand_ns(override_demand_ns), .\periodic_rd_generation.periodic_rd_timer_r_reg[0] (\periodic_rd_generation.periodic_rd_timer_r_reg[0] ), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .req_bank_rdy_r(req_bank_rdy_r), .req_bank_rdy_r_1(req_bank_rdy_r_1), .\req_col_r_reg[9] (\req_col_r_reg[9] ), .\req_col_r_reg[9]_0 (\req_col_r_reg[9]_0 ), .req_data_buf_addr_r(req_data_buf_addr_r), .req_periodic_rd_r(req_periodic_rd_r), .req_row_r(req_row_r), .rnk_config_strobe_ns(rnk_config_strobe_ns), .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0] ), .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[2] (\wtr_timer.wtr_cnt_r_reg[2] )); ddr3_ifmig_7series_v4_0_arb_select arb_select0 (.CLK(CLK), .DIC(DIC), .SR(SR), .cke_r(cke_r), .col_data_buf_addr(col_data_buf_addr[4]), .col_data_buf_addr_r(col_data_buf_addr_r), .col_periodic_rd_r(col_periodic_rd_r), .mc_cke_ns(mc_cke_ns)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_arb_row_col" *) module ddr3_ifmig_7series_v4_0_arb_row_col (\cmd_pipe_plus.mc_address_reg[0] , \cmd_pipe_plus.mc_cmd_reg[0] , \rnk_config_strobe_r_reg[0]_0 , \periodic_rd_generation.periodic_rd_timer_r_reg[0] , Q, read_this_rank, D, granted_col_r_reg_0, \rtw_timer.rtw_cnt_r_reg[1] , mc_odt_ns, col_rd_wr, mc_data_offset_2_ns, \cmd_pipe_plus.mc_cas_n_reg[2] , \cmd_pipe_plus.mc_address_reg[0]_0 , mc_cas_n_ns, \cmd_pipe_plus.mc_cs_n_reg[0] , mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[5] , \cmd_pipe_plus.mc_address_reg[25] , granted_row_r_reg_0, granted_col_r_reg_1, granted_col_r_reg_2, override_demand_ns, granted_row_r_reg_1, \wtr_timer.wtr_cnt_r_reg[2] , col_data_buf_addr, act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , DIC, demand_priority_r_reg, demand_priority_r_reg_0, \cmd_pipe_plus.mc_address_reg[10] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[7] , \cmd_pipe_plus.mc_bank_reg[6] , \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_address_reg[43] , \cmd_pipe_plus.mc_address_reg[42] , \cmd_pipe_plus.mc_address_reg[41] , \cmd_pipe_plus.mc_address_reg[39] , \cmd_pipe_plus.mc_address_reg[38] , \cmd_pipe_plus.mc_address_reg[37] , \cmd_pipe_plus.mc_address_reg[36] , \cmd_pipe_plus.mc_address_reg[35] , \cmd_pipe_plus.mc_address_reg[34] , \cmd_pipe_plus.mc_address_reg[33] , \cmd_pipe_plus.mc_address_reg[32] , \cmd_pipe_plus.mc_address_reg[31] , \cmd_pipe_plus.mc_address_reg[30] , \cmd_pipe_plus.mc_we_n_reg[2] , \cmd_pipe_plus.mc_cas_n_reg[2]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \generate_maint_cmds.insert_maint_r_lcl_reg , CLK, granted_row_ns, rnk_config_strobe_ns, granted_col_ns, granted_pre_ns, SR, rnk_config_valid_r_lcl_reg_0, read_this_rank_r, rd_this_rank_r, rd_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, col_wait_r_reg, col_wait_r_reg_0, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, \rtw_timer.rtw_cnt_r_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_2_reg[3] , col_rd_wr_r1, auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, head_r_lcl_reg, head_r_lcl_reg_0, maint_zq_r, maint_srx_r, \grant_r_reg[1] , row_cmd_wr, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , req_row_r, act_wait_r_lcl_reg, inhbt_act_faw_r, ofs_rdy_r, ofs_rdy_r_0, wr_this_rank_r, req_data_buf_addr_r, col_data_buf_addr_r, \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , act_this_rank_r, req_periodic_rd_r, col_periodic_rd_r, req_bank_rdy_r, req_bank_rdy_r_1, \req_col_r_reg[9] , \req_col_r_reg[9]_0 , auto_pre_r_lcl_reg_1, auto_pre_r_lcl_reg_2); output \cmd_pipe_plus.mc_address_reg[0] ; output \cmd_pipe_plus.mc_cmd_reg[0] ; output \rnk_config_strobe_r_reg[0]_0 ; output \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; output [1:0]Q; output read_this_rank; output [1:0]D; output granted_col_r_reg_0; output \rtw_timer.rtw_cnt_r_reg[1] ; output [0:0]mc_odt_ns; output col_rd_wr; output [0:0]mc_data_offset_2_ns; output [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ; output [1:0]\cmd_pipe_plus.mc_address_reg[0]_0 ; output [1:0]mc_cas_n_ns; output \cmd_pipe_plus.mc_cs_n_reg[0] ; output [1:0]mc_ras_n_ns; output [5:0]\cmd_pipe_plus.mc_bank_reg[5] ; output [21:0]\cmd_pipe_plus.mc_address_reg[25] ; output granted_row_r_reg_0; output granted_col_r_reg_1; output granted_col_r_reg_2; output override_demand_ns; output granted_row_r_reg_1; output \wtr_timer.wtr_cnt_r_reg[2] ; output [4:0]col_data_buf_addr; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output [0:0]DIC; output demand_priority_r_reg; output demand_priority_r_reg_0; output \cmd_pipe_plus.mc_address_reg[10] ; output \cmd_pipe_plus.mc_bank_reg[8] ; output \cmd_pipe_plus.mc_bank_reg[7] ; output \cmd_pipe_plus.mc_bank_reg[6] ; output \cmd_pipe_plus.mc_address_reg[44] ; output \cmd_pipe_plus.mc_address_reg[43] ; output \cmd_pipe_plus.mc_address_reg[42] ; output \cmd_pipe_plus.mc_address_reg[41] ; output \cmd_pipe_plus.mc_address_reg[39] ; output \cmd_pipe_plus.mc_address_reg[38] ; output \cmd_pipe_plus.mc_address_reg[37] ; output \cmd_pipe_plus.mc_address_reg[36] ; output \cmd_pipe_plus.mc_address_reg[35] ; output \cmd_pipe_plus.mc_address_reg[34] ; output \cmd_pipe_plus.mc_address_reg[33] ; output \cmd_pipe_plus.mc_address_reg[32] ; output \cmd_pipe_plus.mc_address_reg[31] ; output \cmd_pipe_plus.mc_address_reg[30] ; output \cmd_pipe_plus.mc_we_n_reg[2] ; output \cmd_pipe_plus.mc_cas_n_reg[2]_0 ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input CLK; input granted_row_ns; input rnk_config_strobe_ns; input granted_col_ns; input granted_pre_ns; input [0:0]SR; input rnk_config_valid_r_lcl_reg_0; input read_this_rank_r; input [1:0]rd_this_rank_r; input rd_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input col_wait_r_reg; input col_wait_r_reg_0; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_2_reg[3] ; input col_rd_wr_r1; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input head_r_lcl_reg; input head_r_lcl_reg_0; input maint_zq_r; input maint_srx_r; input \grant_r_reg[1] ; input [0:0]row_cmd_wr; input [2:0]\req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [27:0]req_row_r; input act_wait_r_lcl_reg; input inhbt_act_faw_r; input ofs_rdy_r; input ofs_rdy_r_0; input [1:0]wr_this_rank_r; input [9:0]req_data_buf_addr_r; input [0:0]col_data_buf_addr_r; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [1:0]act_this_rank_r; input [1:0]req_periodic_rd_r; input col_periodic_rd_r; input req_bank_rdy_r; input req_bank_rdy_r_1; input [6:0]\req_col_r_reg[9] ; input [6:0]\req_col_r_reg[9]_0 ; input auto_pre_r_lcl_reg_1; input auto_pre_r_lcl_reg_2; wire CLK; wire [1:0]D; wire [0:0]DIC; wire [1:0]Q; wire [0:0]SR; wire act_this_rank; wire [1:0]act_this_rank_r; wire act_wait_r_lcl_reg; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire \cmd_pipe_plus.mc_address_reg[0] ; wire [1:0]\cmd_pipe_plus.mc_address_reg[0]_0 ; wire \cmd_pipe_plus.mc_address_reg[10] ; wire [21:0]\cmd_pipe_plus.mc_address_reg[25] ; wire \cmd_pipe_plus.mc_address_reg[30] ; wire \cmd_pipe_plus.mc_address_reg[31] ; wire \cmd_pipe_plus.mc_address_reg[32] ; wire \cmd_pipe_plus.mc_address_reg[33] ; wire \cmd_pipe_plus.mc_address_reg[34] ; wire \cmd_pipe_plus.mc_address_reg[35] ; wire \cmd_pipe_plus.mc_address_reg[36] ; wire \cmd_pipe_plus.mc_address_reg[37] ; wire \cmd_pipe_plus.mc_address_reg[38] ; wire \cmd_pipe_plus.mc_address_reg[39] ; wire \cmd_pipe_plus.mc_address_reg[41] ; wire \cmd_pipe_plus.mc_address_reg[42] ; wire \cmd_pipe_plus.mc_address_reg[43] ; wire \cmd_pipe_plus.mc_address_reg[44] ; wire [5:0]\cmd_pipe_plus.mc_bank_reg[5] ; wire \cmd_pipe_plus.mc_bank_reg[6] ; wire \cmd_pipe_plus.mc_bank_reg[7] ; wire \cmd_pipe_plus.mc_bank_reg[8] ; wire [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ; wire \cmd_pipe_plus.mc_cas_n_reg[2]_0 ; wire \cmd_pipe_plus.mc_cmd_reg[0] ; wire \cmd_pipe_plus.mc_cs_n_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_2_reg[3] ; wire \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ; wire \cmd_pipe_plus.mc_we_n_reg[2] ; wire [4:0]col_data_buf_addr; wire [0:0]col_data_buf_addr_r; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r1; wire col_wait_r_reg; wire col_wait_r_reg_0; wire cs_en2; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire \genblk3[1].rnk_config_strobe_r_reg ; wire \genblk3[2].rnk_config_strobe_r_reg ; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[1] ; wire granted_col_ns; wire granted_col_r_reg_0; wire granted_col_r_reg_1; wire granted_col_r_reg_2; wire granted_pre_ns; wire granted_row_ns; wire granted_row_r_reg_0; wire granted_row_r_reg_1; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire maint_srx_r; wire maint_zq_r; wire [1:0]mc_cas_n_ns; wire [0:0]mc_data_offset_2_ns; wire [0:0]mc_odt_ns; wire [1:0]mc_ras_n_ns; wire ofs_rdy_r; wire ofs_rdy_r_0; wire override_demand_ns; wire \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; wire [1:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire read_this_rank; wire read_this_rank_r; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire req_bank_rdy_r; wire req_bank_rdy_r_1; wire [6:0]\req_col_r_reg[9] ; wire [6:0]\req_col_r_reg[9]_0 ; wire [9:0]req_data_buf_addr_r; wire [1:0]req_periodic_rd_r; wire [27:0]req_row_r; wire rnk_config_strobe; wire rnk_config_strobe_ns; wire \rnk_config_strobe_r_reg[0]_0 ; wire rnk_config_valid_r_lcl_reg_0; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire sent_row; wire [1:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[2] ; (* SOFT_HLUTNM = "soft_lutpair1048" *) LUT2 #( .INIT(4'h1)) \cmd_pipe_plus.mc_cs_n[0]_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[0] ), .I1(sent_row), .O(\cmd_pipe_plus.mc_cs_n_reg[0] )); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_data_offset[3]_i_1 (.I0(\cmd_pipe_plus.mc_cmd_reg[0] ), .O(mc_cas_n_ns[1])); (* SOFT_HLUTNM = "soft_lutpair1048" *) LUT2 #( .INIT(4'h2)) \cmd_pipe_plus.mc_ras_n[0]_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[0] ), .I1(rstdiv0_sync_r1_reg_rep__21), .O(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_we_n[2]_i_1 (.I0(cs_en2), .O(mc_ras_n_ns[1])); ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized4 col_arb0 (.CLK(CLK), .D(D[1]), .DIC(DIC), .Q(Q), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_2), .\cmd_pipe_plus.mc_address_reg[25] (\cmd_pipe_plus.mc_address_reg[25] [21:14]), .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[5] [5:3]), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg[3] ), .col_data_buf_addr(col_data_buf_addr), .col_data_buf_addr_r(col_data_buf_addr_r), .col_periodic_rd_r(col_periodic_rd_r), .col_rd_wr(col_rd_wr), .col_rd_wr_r1(col_rd_wr_r1), .col_wait_r_reg(col_wait_r_reg), .col_wait_r_reg_0(col_wait_r_reg_0), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ), .demand_priority_r_reg(demand_priority_r_reg), .demand_priority_r_reg_0(demand_priority_r_reg_0), .\genblk3[1].rnk_config_strobe_r_reg (\genblk3[1].rnk_config_strobe_r_reg ), .\genblk3[2].rnk_config_strobe_r_reg (\genblk3[2].rnk_config_strobe_r_reg ), .granted_col_r_reg(granted_col_r_reg_0), .granted_col_r_reg_0(granted_col_r_reg_1), .granted_col_r_reg_1(granted_col_r_reg_2), .granted_col_r_reg_2(\cmd_pipe_plus.mc_cmd_reg[0] ), .mc_data_offset_2_ns(mc_data_offset_2_ns), .mc_odt_ns(mc_odt_ns), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r_0(ofs_rdy_r_0), .\periodic_rd_generation.periodic_rd_timer_r_reg[0] (\periodic_rd_generation.periodic_rd_timer_r_reg[0] ), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .req_bank_rdy_r(req_bank_rdy_r), .req_bank_rdy_r_1(req_bank_rdy_r_1), .\req_col_r_reg[9] (\req_col_r_reg[9] ), .\req_col_r_reg[9]_0 (\req_col_r_reg[9]_0 ), .req_data_buf_addr_r(req_data_buf_addr_r), .req_periodic_rd_r(req_periodic_rd_r), .rnk_config_strobe(rnk_config_strobe), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[2] (\wtr_timer.wtr_cnt_r_reg[2] )); FDRE #( .INIT(1'b0)) \genblk3[1].rnk_config_strobe_r_reg[1] (.C(CLK), .CE(1'b1), .D(rnk_config_strobe), .Q(\genblk3[1].rnk_config_strobe_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \genblk3[2].rnk_config_strobe_r_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk3[1].rnk_config_strobe_r_reg ), .Q(\genblk3[2].rnk_config_strobe_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) granted_col_r_reg (.C(CLK), .CE(1'b1), .D(granted_col_ns), .Q(\cmd_pipe_plus.mc_cmd_reg[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) granted_row_r_reg (.C(CLK), .CE(1'b1), .D(granted_row_ns), .Q(sent_row), .R(1'b0)); FDRE #( .INIT(1'b0)) insert_maint_r1_lcl_reg (.C(CLK), .CE(1'b1), .D(\generate_maint_cmds.insert_maint_r_lcl_reg ), .Q(\cmd_pipe_plus.mc_address_reg[0] ), .R(1'b0)); LUT3 #( .INIT(8'hFE)) override_demand_r_i_1 (.I0(\genblk3[1].rnk_config_strobe_r_reg ), .I1(\genblk3[2].rnk_config_strobe_r_reg ), .I2(rnk_config_strobe), .O(override_demand_ns)); FDRE #( .INIT(1'b0)) \pre_4_1_1T_arb.granted_pre_r_reg (.C(CLK), .CE(1'b1), .D(granted_pre_ns), .Q(cs_en2), .R(1'b0)); ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized1 \pre_4_1_1T_arb.pre_arb0 (.CLK(CLK), .Q(\cmd_pipe_plus.mc_cas_n_reg[2] ), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .\cmd_pipe_plus.mc_address_reg[30] (\cmd_pipe_plus.mc_address_reg[30] ), .\cmd_pipe_plus.mc_address_reg[31] (\cmd_pipe_plus.mc_address_reg[31] ), .\cmd_pipe_plus.mc_address_reg[32] (\cmd_pipe_plus.mc_address_reg[32] ), .\cmd_pipe_plus.mc_address_reg[33] (\cmd_pipe_plus.mc_address_reg[33] ), .\cmd_pipe_plus.mc_address_reg[34] (\cmd_pipe_plus.mc_address_reg[34] ), .\cmd_pipe_plus.mc_address_reg[35] (\cmd_pipe_plus.mc_address_reg[35] ), .\cmd_pipe_plus.mc_address_reg[36] (\cmd_pipe_plus.mc_address_reg[36] ), .\cmd_pipe_plus.mc_address_reg[37] (\cmd_pipe_plus.mc_address_reg[37] ), .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ), .\cmd_pipe_plus.mc_address_reg[39] (\cmd_pipe_plus.mc_address_reg[39] ), .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ), .\cmd_pipe_plus.mc_address_reg[42] (\cmd_pipe_plus.mc_address_reg[42] ), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] ), .\cmd_pipe_plus.mc_bank_reg[6] (\cmd_pipe_plus.mc_bank_reg[6] ), .\cmd_pipe_plus.mc_bank_reg[7] (\cmd_pipe_plus.mc_bank_reg[7] ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2]_0 ), .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ), .cs_en2(cs_en2), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ), .req_row_r(req_row_r), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21)); FDRE #( .INIT(1'b0)) \rnk_config_strobe_r_reg[0] (.C(CLK), .CE(1'b1), .D(rnk_config_strobe_ns), .Q(rnk_config_strobe), .R(1'b0)); FDRE #( .INIT(1'b0)) rnk_config_valid_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rnk_config_valid_r_lcl_reg_0), .Q(\rnk_config_strobe_r_reg[0]_0 ), .R(SR)); ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized2 row_arb0 (.CLK(CLK), .D(D[0]), .Q(\cmd_pipe_plus.mc_address_reg[0]_0 ), .act_this_rank(act_this_rank), .act_this_rank_r(act_this_rank_r), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ), .\cmd_pipe_plus.mc_address_reg[14] (\cmd_pipe_plus.mc_address_reg[25] [13:0]), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[5] [2:0]), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\grant_r_reg[1]_0 (\grant_r_reg[1] ), .granted_row_r_reg(granted_row_r_reg_0), .granted_row_r_reg_0(granted_row_r_reg_1), .head_r_lcl_reg(head_r_lcl_reg), .head_r_lcl_reg_0(head_r_lcl_reg_0), .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .insert_maint_r1_lcl_reg(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ), .insert_maint_r1_lcl_reg_0(\cmd_pipe_plus.mc_cs_n_reg[0] ), .insert_maint_r1_lcl_reg_1(\cmd_pipe_plus.mc_address_reg[0] ), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .mc_cas_n_ns(mc_cas_n_ns[0]), .mc_ras_n_ns(mc_ras_n_ns[0]), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .req_row_r(req_row_r), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .sent_row(sent_row)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_arb_select" *) module ddr3_ifmig_7series_v4_0_arb_select (col_periodic_rd_r, col_data_buf_addr_r, cke_r, DIC, CLK, col_data_buf_addr, SR, mc_cke_ns); output col_periodic_rd_r; output [0:0]col_data_buf_addr_r; output cke_r; input [0:0]DIC; input CLK; input [0:0]col_data_buf_addr; input [0:0]SR; input [0:0]mc_cke_ns; wire CLK; wire [0:0]DIC; wire [0:0]SR; wire cke_r; wire [0:0]col_data_buf_addr; wire [0:0]col_data_buf_addr_r; wire col_periodic_rd_r; wire [0:0]mc_cke_ns; FDSE #( .INIT(1'b1)) cke_r_reg (.C(CLK), .CE(1'b1), .D(mc_cke_ns), .Q(cke_r), .S(SR)); FDRE #( .INIT(1'b0)) \col_mux.col_data_buf_addr_r_reg[4] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr), .Q(col_data_buf_addr_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \col_mux.col_periodic_rd_r_reg (.C(CLK), .CE(1'b1), .D(DIC), .Q(col_periodic_rd_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc" *) module ddr3_ifmig_7series_v4_0_axi_mc (s_axi_arready, app_en_ns1, mc_app_cmd, E, s_axi_awready, s_axi_wready, mc_app_wdf_mask_reg, D, mc_app_wdf_data_reg, \mc_app_wdf_data_reg_reg[255] , out, s_axi_rid, s_axi_bid, s_axi_bvalid, w_cmd_rdy, \app_addr_r1_reg[27] , s_axi_rvalid, s_axi_rlast, app_wdf_mask, app_wdf_data, mc_app_wdf_wren_reg, s_axi_arvalid, app_rdy, reset_reg, app_en_r1, CLK, app_wdf_rdy, app_rd_data_valid, Q, mc_init_complete, s_axi_awlen, s_axi_bready, s_axi_awvalid, s_axi_awaddr, s_axi_awburst, s_axi_wvalid, s_axi_awid, s_axi_arlen, s_axi_araddr, s_axi_arburst, s_axi_rready, s_axi_wstrb, s_axi_wdata, aresetn, s_axi_arid); output s_axi_arready; output app_en_ns1; output [0:0]mc_app_cmd; output [0:0]E; output s_axi_awready; output s_axi_wready; output [31:0]mc_app_wdf_mask_reg; output [31:0]D; output [255:0]mc_app_wdf_data_reg; output [255:0]\mc_app_wdf_data_reg_reg[255] ; output [256:0]out; output [0:0]s_axi_rid; output [0:0]s_axi_bid; output s_axi_bvalid; output w_cmd_rdy; output [24:0]\app_addr_r1_reg[27] ; output s_axi_rvalid; output s_axi_rlast; output [31:0]app_wdf_mask; output [255:0]app_wdf_data; output mc_app_wdf_wren_reg; input s_axi_arvalid; input app_rdy; input reset_reg; input app_en_r1; input CLK; input app_wdf_rdy; input app_rd_data_valid; input [255:0]Q; input mc_init_complete; input [7:0]s_axi_awlen; input s_axi_bready; input s_axi_awvalid; input [29:0]s_axi_awaddr; input [0:0]s_axi_awburst; input s_axi_wvalid; input [0:0]s_axi_awid; input [7:0]s_axi_arlen; input [29:0]s_axi_araddr; input [0:0]s_axi_arburst; input s_axi_rready; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; input aresetn; input [0:0]s_axi_arid; wire CLK; wire [31:0]D; wire [0:0]E; wire [255:0]Q; wire [24:0]\app_addr_r1_reg[27] ; wire app_en_ns1; wire app_en_r1; wire app_rd_data_valid; wire app_rdy; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire areset_d1; wire aresetn; wire awvalid_int; wire axi_mc_ar_channel_0_n_29; wire axi_mc_aw_channel_0_n_10; wire axi_mc_aw_channel_0_n_11; wire axi_mc_aw_channel_0_n_12; wire axi_mc_aw_channel_0_n_13; wire axi_mc_aw_channel_0_n_14; wire axi_mc_aw_channel_0_n_15; wire axi_mc_aw_channel_0_n_16; wire axi_mc_aw_channel_0_n_17; wire axi_mc_aw_channel_0_n_18; wire axi_mc_aw_channel_0_n_19; wire axi_mc_aw_channel_0_n_20; wire axi_mc_aw_channel_0_n_21; wire axi_mc_aw_channel_0_n_22; wire axi_mc_aw_channel_0_n_23; wire axi_mc_aw_channel_0_n_24; wire axi_mc_aw_channel_0_n_25; wire axi_mc_aw_channel_0_n_26; wire axi_mc_aw_channel_0_n_27; wire axi_mc_aw_channel_0_n_28; wire axi_mc_aw_channel_0_n_4; wire axi_mc_aw_channel_0_n_5; wire axi_mc_aw_channel_0_n_7; wire axi_mc_aw_channel_0_n_8; wire axi_mc_aw_channel_0_n_9; wire axi_mc_cmd_arbiter_0_n_3; wire axi_mc_cmd_arbiter_0_n_4; wire axi_mc_cmd_arbiter_0_n_5; wire axi_mc_cmd_arbiter_0_n_6; wire axvalid; wire b_awid; wire b_push; wire [0:0]mc_app_cmd; wire [255:0]mc_app_wdf_data_reg; wire [255:0]\mc_app_wdf_data_reg_reg[255] ; wire [31:0]mc_app_wdf_mask_reg; wire mc_app_wdf_wren_reg; wire mc_init_complete; wire mc_init_complete_r; wire next; wire [256:0]out; wire p_0_in; wire r_arid; wire r_push; wire r_rlast; wire rd_cmd_en; wire rd_starve_cnt0; wire reset_reg; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire w_cmd_rdy; wire wr_cmd_en; wire wvalid_int; LUT2 #( .INIT(4'h7)) areset_d1_i_1 (.I0(mc_init_complete_r), .I1(aresetn), .O(p_0_in)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) areset_d1_reg (.C(CLK), .CE(1'b1), .D(p_0_in), .Q(areset_d1), .R(1'b0)); ddr3_ifmig_7series_v4_0_axi_mc_ar_channel axi_mc_ar_channel_0 (.CLK(CLK), .\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd), .\app_addr_r1_reg[27] ({\app_addr_r1_reg[27] [24:4],\app_addr_r1_reg[27] [2:0]}), .\app_addr_r1_reg[6] (axi_mc_ar_channel_0_n_29), .areset_d1(areset_d1), .\axaddr_incr_reg[10] (axi_mc_aw_channel_0_n_8), .\axaddr_incr_reg[11] (axi_mc_aw_channel_0_n_9), .\axaddr_incr_reg[12] (axi_mc_aw_channel_0_n_10), .\axaddr_incr_reg[13] (axi_mc_aw_channel_0_n_11), .\axaddr_incr_reg[14] (axi_mc_aw_channel_0_n_12), .\axaddr_incr_reg[15] (axi_mc_aw_channel_0_n_13), .\axaddr_incr_reg[16] (axi_mc_aw_channel_0_n_14), .\axaddr_incr_reg[17] (axi_mc_aw_channel_0_n_15), .\axaddr_incr_reg[18] (axi_mc_aw_channel_0_n_16), .\axaddr_incr_reg[19] (axi_mc_aw_channel_0_n_17), .\axaddr_incr_reg[20] (axi_mc_aw_channel_0_n_18), .\axaddr_incr_reg[21] (axi_mc_aw_channel_0_n_19), .\axaddr_incr_reg[22] (axi_mc_aw_channel_0_n_20), .\axaddr_incr_reg[23] (axi_mc_aw_channel_0_n_21), .\axaddr_incr_reg[24] (axi_mc_aw_channel_0_n_22), .\axaddr_incr_reg[25] (axi_mc_aw_channel_0_n_23), .\axaddr_incr_reg[26] (axi_mc_aw_channel_0_n_24), .\axaddr_incr_reg[27] (axi_mc_aw_channel_0_n_25), .\axaddr_incr_reg[28] (axi_mc_aw_channel_0_n_26), .\axaddr_incr_reg[29] (axi_mc_aw_channel_0_n_27), .\axaddr_incr_reg[5] (axi_mc_aw_channel_0_n_28), .\axaddr_incr_reg[6] (axi_mc_aw_channel_0_n_4), .\axaddr_incr_reg[7] (axi_mc_aw_channel_0_n_5), .\axaddr_incr_reg[9] (axi_mc_aw_channel_0_n_7), .axready_reg(axi_mc_cmd_arbiter_0_n_5), .axready_reg_0(axi_mc_cmd_arbiter_0_n_6), .axvalid(axvalid), .in({r_arid,r_rlast}), .next(next), .r_push(r_push), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid)); ddr3_ifmig_7series_v4_0_axi_mc_aw_channel axi_mc_aw_channel_0 (.CLK(CLK), .\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy), .\RD_PRI_REG_STARVE.rnw_i_reg_0 (mc_app_cmd), .\app_addr_r1_reg[10] (axi_mc_aw_channel_0_n_10), .\app_addr_r1_reg[11] (axi_mc_aw_channel_0_n_11), .\app_addr_r1_reg[12] (axi_mc_aw_channel_0_n_12), .\app_addr_r1_reg[13] (axi_mc_aw_channel_0_n_13), .\app_addr_r1_reg[14] (axi_mc_aw_channel_0_n_14), .\app_addr_r1_reg[15] (axi_mc_aw_channel_0_n_15), .\app_addr_r1_reg[16] (axi_mc_aw_channel_0_n_16), .\app_addr_r1_reg[17] (axi_mc_aw_channel_0_n_17), .\app_addr_r1_reg[18] (axi_mc_aw_channel_0_n_18), .\app_addr_r1_reg[19] (axi_mc_aw_channel_0_n_19), .\app_addr_r1_reg[20] (axi_mc_aw_channel_0_n_20), .\app_addr_r1_reg[21] (axi_mc_aw_channel_0_n_21), .\app_addr_r1_reg[22] (axi_mc_aw_channel_0_n_22), .\app_addr_r1_reg[23] (axi_mc_aw_channel_0_n_23), .\app_addr_r1_reg[24] (axi_mc_aw_channel_0_n_24), .\app_addr_r1_reg[25] (axi_mc_aw_channel_0_n_25), .\app_addr_r1_reg[26] (axi_mc_aw_channel_0_n_26), .\app_addr_r1_reg[27] (axi_mc_aw_channel_0_n_27), .\app_addr_r1_reg[3] (axi_mc_aw_channel_0_n_28), .\app_addr_r1_reg[4] (axi_mc_aw_channel_0_n_4), .\app_addr_r1_reg[5] (axi_mc_aw_channel_0_n_5), .\app_addr_r1_reg[6] (\app_addr_r1_reg[27] [3]), .\app_addr_r1_reg[7] (axi_mc_aw_channel_0_n_7), .\app_addr_r1_reg[8] (axi_mc_aw_channel_0_n_8), .\app_addr_r1_reg[9] (axi_mc_aw_channel_0_n_9), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .axready_reg(axi_mc_cmd_arbiter_0_n_3), .axready_reg_0(axi_mc_cmd_arbiter_0_n_4), .b_awid(b_awid), .b_push(b_push), .\int_addr_reg[3] (axi_mc_ar_channel_0_n_29), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid)); ddr3_ifmig_7series_v4_0_axi_mc_b_channel axi_mc_b_channel_0 (.CLK(CLK), .E(E), .\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd), .app_en_ns1(app_en_ns1), .app_en_r1(app_en_r1), .app_rdy(app_rdy), .app_wdf_rdy(app_wdf_rdy), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .b_awid(b_awid), .b_push(b_push), .rd_cmd_en(rd_cmd_en), .reset_reg(reset_reg), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .wr_cmd_en(wr_cmd_en), .wvalid_int(wvalid_int)); ddr3_ifmig_7series_v4_0_axi_mc_cmd_arbiter axi_mc_cmd_arbiter_0 (.CLK(CLK), .E(rd_starve_cnt0), .\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 (mc_app_cmd), .app_rdy(app_rdy), .areset_d1(areset_d1), .\axaddr_incr_reg[29] (axi_mc_cmd_arbiter_0_n_3), .\axaddr_incr_reg[29]_0 (axi_mc_cmd_arbiter_0_n_5), .\axlen_cnt_reg[1] (axi_mc_cmd_arbiter_0_n_4), .\axlen_cnt_reg[1]_0 (axi_mc_cmd_arbiter_0_n_6), .axready_reg(s_axi_arready), .mc_app_wdf_wren_reg_reg(w_cmd_rdy), .next(next), .rd_cmd_en(rd_cmd_en), .s_axi_arburst(s_axi_arburst), .s_axi_arvalid(s_axi_arvalid), .s_axi_awburst(s_axi_awburst), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .wr_cmd_en(wr_cmd_en)); ddr3_ifmig_7series_v4_0_axi_mc_r_channel axi_mc_r_channel_0 (.CLK(CLK), .E(rd_starve_cnt0), .Q(Q), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .areset_d1(areset_d1), .axvalid(axvalid), .in({r_arid,r_rlast}), .out(out), .r_push(r_push), .rd_cmd_en(rd_cmd_en), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid)); ddr3_ifmig_7series_v4_0_axi_mc_w_channel axi_mc_w_channel_0 (.CLK(CLK), .D(D), .\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .app_wdf_rdy(app_wdf_rdy), .areset_d1(areset_d1), .mc_app_wdf_data_reg(mc_app_wdf_data_reg), .\mc_app_wdf_data_reg_reg[255]_0 (\mc_app_wdf_data_reg_reg[255] ), .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg), .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .wvalid_int(wvalid_int)); FDRE #( .INIT(1'b0)) mc_init_complete_r_reg (.C(CLK), .CE(1'b1), .D(mc_init_complete), .Q(mc_init_complete_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_ar_channel" *) module ddr3_ifmig_7series_v4_0_axi_mc_ar_channel (s_axi_arready, r_push, in, axvalid, \app_addr_r1_reg[27] , \app_addr_r1_reg[6] , areset_d1, CLK, next, \axaddr_incr_reg[6] , \axaddr_incr_reg[7] , \axaddr_incr_reg[9] , \axaddr_incr_reg[10] , \axaddr_incr_reg[11] , \axaddr_incr_reg[12] , \axaddr_incr_reg[13] , \axaddr_incr_reg[14] , \axaddr_incr_reg[15] , \axaddr_incr_reg[16] , \axaddr_incr_reg[17] , \axaddr_incr_reg[18] , \axaddr_incr_reg[19] , \axaddr_incr_reg[20] , \axaddr_incr_reg[21] , \axaddr_incr_reg[22] , \axaddr_incr_reg[23] , \axaddr_incr_reg[24] , \axaddr_incr_reg[25] , \axaddr_incr_reg[26] , \axaddr_incr_reg[27] , \axaddr_incr_reg[28] , \axaddr_incr_reg[29] , \axaddr_incr_reg[5] , axready_reg, s_axi_arlen, s_axi_arvalid, s_axi_araddr, \RD_PRI_REG_STARVE.rnw_i_reg , axready_reg_0, s_axi_arburst, s_axi_arid); output s_axi_arready; output r_push; output [1:0]in; output axvalid; output [23:0]\app_addr_r1_reg[27] ; output \app_addr_r1_reg[6] ; input areset_d1; input CLK; input next; input \axaddr_incr_reg[6] ; input \axaddr_incr_reg[7] ; input \axaddr_incr_reg[9] ; input \axaddr_incr_reg[10] ; input \axaddr_incr_reg[11] ; input \axaddr_incr_reg[12] ; input \axaddr_incr_reg[13] ; input \axaddr_incr_reg[14] ; input \axaddr_incr_reg[15] ; input \axaddr_incr_reg[16] ; input \axaddr_incr_reg[17] ; input \axaddr_incr_reg[18] ; input \axaddr_incr_reg[19] ; input \axaddr_incr_reg[20] ; input \axaddr_incr_reg[21] ; input \axaddr_incr_reg[22] ; input \axaddr_incr_reg[23] ; input \axaddr_incr_reg[24] ; input \axaddr_incr_reg[25] ; input \axaddr_incr_reg[26] ; input \axaddr_incr_reg[27] ; input \axaddr_incr_reg[28] ; input \axaddr_incr_reg[29] ; input \axaddr_incr_reg[5] ; input axready_reg; input [7:0]s_axi_arlen; input s_axi_arvalid; input [29:0]s_axi_araddr; input \RD_PRI_REG_STARVE.rnw_i_reg ; input axready_reg_0; input [0:0]s_axi_arburst; input [0:0]s_axi_arid; wire CLK; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire [23:0]\app_addr_r1_reg[27] ; wire \app_addr_r1_reg[6] ; wire ar_cmd_fsm_0_n_101; wire ar_cmd_fsm_0_n_102; wire ar_cmd_fsm_0_n_103; wire ar_cmd_fsm_0_n_134; wire ar_cmd_fsm_0_n_135; wire ar_cmd_fsm_0_n_136; wire ar_cmd_fsm_0_n_137; wire ar_cmd_fsm_0_n_138; wire ar_cmd_fsm_0_n_139; wire ar_cmd_fsm_0_n_140; wire ar_cmd_fsm_0_n_141; wire ar_cmd_fsm_0_n_145; wire ar_cmd_fsm_0_n_146; wire ar_cmd_fsm_0_n_86; wire ar_cmd_fsm_0_n_87; wire ar_cmd_fsm_0_n_88; wire ar_cmd_fsm_0_n_89; wire ar_cmd_fsm_0_n_90; wire ar_cmd_fsm_0_n_91; wire ar_cmd_fsm_0_n_92; wire ar_cmd_fsm_0_n_93; wire ar_cmd_fsm_0_n_94; wire ar_cmd_fsm_0_n_95; wire areset_d1; wire arvalid_int; wire [29:0]axaddr; wire [29:0]axaddr_incr; wire \axaddr_incr_reg[10] ; wire \axaddr_incr_reg[11] ; wire \axaddr_incr_reg[12] ; wire \axaddr_incr_reg[13] ; wire \axaddr_incr_reg[14] ; wire \axaddr_incr_reg[15] ; wire \axaddr_incr_reg[16] ; wire \axaddr_incr_reg[17] ; wire \axaddr_incr_reg[18] ; wire \axaddr_incr_reg[19] ; wire \axaddr_incr_reg[20] ; wire \axaddr_incr_reg[21] ; wire \axaddr_incr_reg[22] ; wire \axaddr_incr_reg[23] ; wire \axaddr_incr_reg[24] ; wire \axaddr_incr_reg[25] ; wire \axaddr_incr_reg[26] ; wire \axaddr_incr_reg[27] ; wire \axaddr_incr_reg[28] ; wire \axaddr_incr_reg[29] ; wire \axaddr_incr_reg[5] ; wire \axaddr_incr_reg[6] ; wire \axaddr_incr_reg[7] ; wire \axaddr_incr_reg[9] ; wire [8:5]axaddr_int; wire [29:0]axaddr_int__0; wire [1:1]axburst; wire axi_mc_cmd_translator_0_n_30; wire axi_mc_cmd_translator_0_n_31; wire axi_mc_cmd_translator_0_n_32; wire axi_mc_cmd_translator_0_n_33; wire axi_mc_cmd_translator_0_n_34; wire axi_mc_cmd_translator_0_n_35; wire axi_mc_cmd_translator_0_n_36; wire axi_mc_cmd_translator_0_n_37; wire axi_mc_cmd_translator_0_n_72; wire axi_mc_cmd_translator_0_n_73; wire axi_mc_cmd_translator_0_n_74; wire axi_mc_cmd_translator_0_n_75; wire \axi_mc_incr_cmd_0/axlen_cnt ; wire [29:0]\axi_mc_incr_cmd_0/p_0_in ; wire [3:0]axi_mc_incr_cmd_byte_addr; wire [29:4]axi_mc_incr_cmd_byte_addr__0; wire \axi_mc_wrap_cmd_0/axlen_cnt ; wire [3:0]\axi_mc_wrap_cmd_0/int_addr ; wire [7:0]axlen; wire [3:0]axlen_int; wire [7:4]axlen_int__0; wire axready_reg; wire axready_reg_0; wire axvalid; wire [1:0]in; wire next; wire [29:0]p_0_in; wire r_push; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; ddr3_ifmig_7series_v4_0_axi_mc_cmd_fsm ar_cmd_fsm_0 (.CLK(CLK), .D({axlen_int__0,axlen_int}), .DI(ar_cmd_fsm_0_n_145), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .\RD_PRI_REG_STARVE.rnw_i_reg (\RD_PRI_REG_STARVE.rnw_i_reg ), .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103}), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[6] (\app_addr_r1_reg[6] ), .areset_d1(areset_d1), .arvalid_int(arvalid_int), .\axaddr_incr_reg[10] (\axaddr_incr_reg[10] ), .\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ), .\axaddr_incr_reg[12] (\axaddr_incr_reg[12] ), .\axaddr_incr_reg[13] (\axaddr_incr_reg[13] ), .\axaddr_incr_reg[14] (\axaddr_incr_reg[14] ), .\axaddr_incr_reg[15] (\axaddr_incr_reg[15] ), .\axaddr_incr_reg[16] (\axaddr_incr_reg[16] ), .\axaddr_incr_reg[17] (\axaddr_incr_reg[17] ), .\axaddr_incr_reg[18] (\axaddr_incr_reg[18] ), .\axaddr_incr_reg[19] (\axaddr_incr_reg[19] ), .\axaddr_incr_reg[20] (\axaddr_incr_reg[20] ), .\axaddr_incr_reg[21] (\axaddr_incr_reg[21] ), .\axaddr_incr_reg[22] (\axaddr_incr_reg[22] ), .\axaddr_incr_reg[23] (\axaddr_incr_reg[23] ), .\axaddr_incr_reg[24] (\axaddr_incr_reg[24] ), .\axaddr_incr_reg[25] (\axaddr_incr_reg[25] ), .\axaddr_incr_reg[26] (\axaddr_incr_reg[26] ), .\axaddr_incr_reg[27] (\axaddr_incr_reg[27] ), .\axaddr_incr_reg[28] (\axaddr_incr_reg[28] ), .\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:8],axi_mc_incr_cmd_byte_addr__0[4]}), .\axaddr_incr_reg[29]_0 (p_0_in), .\axaddr_incr_reg[29]_1 (axaddr_incr), .\axaddr_incr_reg[29]_2 (\axaddr_incr_reg[29] ), .\axaddr_incr_reg[5] (\axaddr_incr_reg[5] ), .\axaddr_incr_reg[6] (\axaddr_incr_reg[6] ), .\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ), .\axaddr_incr_reg[9] (\axaddr_incr_reg[9] ), .\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}), .\axaddr_reg[29]_0 (axaddr), .axburst(axburst), .\axburst_reg[1] (ar_cmd_fsm_0_n_95), .\axid_reg[0] (ar_cmd_fsm_0_n_146), .\axlen_cnt_reg[0] (\axi_mc_wrap_cmd_0/axlen_cnt ), .\axlen_cnt_reg[3] ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}), .\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .\axlen_cnt_reg[7] ({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}), .\axlen_reg[7] (axlen), .axready_reg_0(axready_reg), .axready_reg_1(axready_reg_0), .axvalid(axvalid), .in(in[1]), .in0(axi_mc_incr_cmd_byte_addr), .\int_addr_reg[3] ({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}), .\int_addr_reg[3]_0 (\axi_mc_wrap_cmd_0/int_addr ), .next(next), .out(\axi_mc_incr_cmd_0/p_0_in ), .r_rlast_reg(ar_cmd_fsm_0_n_94), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid)); FDRE #( .INIT(1'b0)) \axaddr_reg[0] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[0]), .Q(axaddr[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[10] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[10]), .Q(axaddr[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[11] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[11]), .Q(axaddr[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[12] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[12]), .Q(axaddr[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[13] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[13]), .Q(axaddr[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[14] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[14]), .Q(axaddr[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[15] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[15]), .Q(axaddr[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[16] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[16]), .Q(axaddr[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[17] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[17]), .Q(axaddr[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[18] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[18]), .Q(axaddr[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[19] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[19]), .Q(axaddr[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[1] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[1]), .Q(axaddr[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[20] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[20]), .Q(axaddr[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[21] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[21]), .Q(axaddr[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[22] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[22]), .Q(axaddr[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[23] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[23]), .Q(axaddr[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[24] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[24]), .Q(axaddr[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[25] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[25]), .Q(axaddr[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[26] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[26]), .Q(axaddr[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[27] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[27]), .Q(axaddr[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[28] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[28]), .Q(axaddr[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[29] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[29]), .Q(axaddr[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[2] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[2]), .Q(axaddr[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[3] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[3]), .Q(axaddr[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[4] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[4]), .Q(axaddr[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[5] (.C(CLK), .CE(1'b1), .D(axaddr_int[5]), .Q(axaddr[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[6] (.C(CLK), .CE(1'b1), .D(axaddr_int[6]), .Q(axaddr[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[7] (.C(CLK), .CE(1'b1), .D(axaddr_int[7]), .Q(axaddr[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[8] (.C(CLK), .CE(1'b1), .D(axaddr_int[8]), .Q(axaddr[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[9] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[9]), .Q(axaddr[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axburst_reg[1] (.C(CLK), .CE(1'b1), .D(ar_cmd_fsm_0_n_95), .Q(axburst), .R(1'b0)); ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator__parameterized0 axi_mc_cmd_translator_0 (.CLK(CLK), .D({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}), .DI(ar_cmd_fsm_0_n_145), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103,axi_mc_incr_cmd_byte_addr__0[4]}), .\app_addr_r1_reg[27] (axaddr_incr), .\app_addr_r1_reg[6] (\axi_mc_wrap_cmd_0/int_addr ), .areset_d1(areset_d1), .\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .\axlen_cnt_reg[3]_0 ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}), .axready_reg(axi_mc_incr_cmd_byte_addr__0[29:8]), .axready_reg_0(p_0_in), .axready_reg_1(\axi_mc_wrap_cmd_0/axlen_cnt ), .axready_reg_2({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}), .in0(axi_mc_incr_cmd_byte_addr), .out(\axi_mc_incr_cmd_0/p_0_in )); FDRE #( .INIT(1'b0)) \axid_reg[0] (.C(CLK), .CE(1'b1), .D(ar_cmd_fsm_0_n_146), .Q(in[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[0] (.C(CLK), .CE(1'b1), .D(axlen_int[0]), .Q(axlen[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[1] (.C(CLK), .CE(1'b1), .D(axlen_int[1]), .Q(axlen[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[2] (.C(CLK), .CE(1'b1), .D(axlen_int[2]), .Q(axlen[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[3] (.C(CLK), .CE(1'b1), .D(axlen_int[3]), .Q(axlen[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[4] (.C(CLK), .CE(1'b1), .D(axlen_int__0[4]), .Q(axlen[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[5] (.C(CLK), .CE(1'b1), .D(axlen_int__0[5]), .Q(axlen[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[6] (.C(CLK), .CE(1'b1), .D(axlen_int__0[6]), .Q(axlen[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[7] (.C(CLK), .CE(1'b1), .D(axlen_int__0[7]), .Q(axlen[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) axvalid_reg (.C(CLK), .CE(1'b1), .D(arvalid_int), .Q(axvalid), .R(areset_d1)); FDRE #( .INIT(1'b0)) r_push_reg (.C(CLK), .CE(1'b1), .D(next), .Q(r_push), .R(1'b0)); FDRE #( .INIT(1'b0)) r_rlast_reg (.C(CLK), .CE(1'b1), .D(ar_cmd_fsm_0_n_94), .Q(in[0]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_aw_channel" *) module ddr3_ifmig_7series_v4_0_axi_mc_aw_channel (s_axi_awready, awvalid_int, b_awid, b_push, \app_addr_r1_reg[4] , \app_addr_r1_reg[5] , \app_addr_r1_reg[6] , \app_addr_r1_reg[7] , \app_addr_r1_reg[8] , \app_addr_r1_reg[9] , \app_addr_r1_reg[10] , \app_addr_r1_reg[11] , \app_addr_r1_reg[12] , \app_addr_r1_reg[13] , \app_addr_r1_reg[14] , \app_addr_r1_reg[15] , \app_addr_r1_reg[16] , \app_addr_r1_reg[17] , \app_addr_r1_reg[18] , \app_addr_r1_reg[19] , \app_addr_r1_reg[20] , \app_addr_r1_reg[21] , \app_addr_r1_reg[22] , \app_addr_r1_reg[23] , \app_addr_r1_reg[24] , \app_addr_r1_reg[25] , \app_addr_r1_reg[26] , \app_addr_r1_reg[27] , \app_addr_r1_reg[3] , areset_d1, CLK, axready_reg, s_axi_awlen, s_axi_awvalid, \RD_PRI_REG_STARVE.rnw_i_reg , s_axi_awaddr, \int_addr_reg[3] , axready_reg_0, s_axi_awburst, \RD_PRI_REG_STARVE.rnw_i_reg_0 , s_axi_awid); output s_axi_awready; output awvalid_int; output b_awid; output b_push; output \app_addr_r1_reg[4] ; output \app_addr_r1_reg[5] ; output [0:0]\app_addr_r1_reg[6] ; output \app_addr_r1_reg[7] ; output \app_addr_r1_reg[8] ; output \app_addr_r1_reg[9] ; output \app_addr_r1_reg[10] ; output \app_addr_r1_reg[11] ; output \app_addr_r1_reg[12] ; output \app_addr_r1_reg[13] ; output \app_addr_r1_reg[14] ; output \app_addr_r1_reg[15] ; output \app_addr_r1_reg[16] ; output \app_addr_r1_reg[17] ; output \app_addr_r1_reg[18] ; output \app_addr_r1_reg[19] ; output \app_addr_r1_reg[20] ; output \app_addr_r1_reg[21] ; output \app_addr_r1_reg[22] ; output \app_addr_r1_reg[23] ; output \app_addr_r1_reg[24] ; output \app_addr_r1_reg[25] ; output \app_addr_r1_reg[26] ; output \app_addr_r1_reg[27] ; output \app_addr_r1_reg[3] ; input areset_d1; input CLK; input axready_reg; input [7:0]s_axi_awlen; input s_axi_awvalid; input \RD_PRI_REG_STARVE.rnw_i_reg ; input [29:0]s_axi_awaddr; input \int_addr_reg[3] ; input axready_reg_0; input [0:0]s_axi_awburst; input \RD_PRI_REG_STARVE.rnw_i_reg_0 ; input [0:0]s_axi_awid; wire CLK; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire \RD_PRI_REG_STARVE.rnw_i_reg_0 ; wire \app_addr_r1_reg[10] ; wire \app_addr_r1_reg[11] ; wire \app_addr_r1_reg[12] ; wire \app_addr_r1_reg[13] ; wire \app_addr_r1_reg[14] ; wire \app_addr_r1_reg[15] ; wire \app_addr_r1_reg[16] ; wire \app_addr_r1_reg[17] ; wire \app_addr_r1_reg[18] ; wire \app_addr_r1_reg[19] ; wire \app_addr_r1_reg[20] ; wire \app_addr_r1_reg[21] ; wire \app_addr_r1_reg[22] ; wire \app_addr_r1_reg[23] ; wire \app_addr_r1_reg[24] ; wire \app_addr_r1_reg[25] ; wire \app_addr_r1_reg[26] ; wire \app_addr_r1_reg[27] ; wire \app_addr_r1_reg[3] ; wire \app_addr_r1_reg[4] ; wire \app_addr_r1_reg[5] ; wire [0:0]\app_addr_r1_reg[6] ; wire \app_addr_r1_reg[7] ; wire \app_addr_r1_reg[8] ; wire \app_addr_r1_reg[9] ; wire areset_d1; wire aw_cmd_fsm_0_n_10; wire aw_cmd_fsm_0_n_102; wire aw_cmd_fsm_0_n_11; wire aw_cmd_fsm_0_n_12; wire aw_cmd_fsm_0_n_134; wire aw_cmd_fsm_0_n_135; wire aw_cmd_fsm_0_n_136; wire aw_cmd_fsm_0_n_137; wire aw_cmd_fsm_0_n_138; wire aw_cmd_fsm_0_n_139; wire aw_cmd_fsm_0_n_14; wire aw_cmd_fsm_0_n_140; wire aw_cmd_fsm_0_n_141; wire aw_cmd_fsm_0_n_146; wire aw_cmd_fsm_0_n_5; wire aw_cmd_fsm_0_n_6; wire aw_cmd_fsm_0_n_7; wire aw_cmd_fsm_0_n_8; wire aw_cmd_fsm_0_n_9; wire awvalid_int; wire [29:0]axaddr; wire [29:0]axaddr_incr; wire [8:5]axaddr_int; wire [29:0]axaddr_int__0; wire [1:1]axburst; wire axi_mc_cmd_translator_0_n_30; wire axi_mc_cmd_translator_0_n_31; wire axi_mc_cmd_translator_0_n_32; wire axi_mc_cmd_translator_0_n_33; wire axi_mc_cmd_translator_0_n_34; wire axi_mc_cmd_translator_0_n_35; wire axi_mc_cmd_translator_0_n_36; wire axi_mc_cmd_translator_0_n_37; wire axi_mc_cmd_translator_0_n_72; wire axi_mc_cmd_translator_0_n_73; wire axi_mc_cmd_translator_0_n_74; wire axi_mc_cmd_translator_0_n_75; wire \axi_mc_incr_cmd_0/axlen_cnt ; wire [29:0]\axi_mc_incr_cmd_0/p_0_in ; wire [3:0]axi_mc_incr_cmd_byte_addr; wire [29:4]axi_mc_incr_cmd_byte_addr__0; wire \axi_mc_wrap_cmd_0/axlen_cnt ; wire [3:0]\axi_mc_wrap_cmd_0/int_addr ; wire axid; wire [7:0]axlen; wire [3:0]axlen_int; wire [7:4]axlen_int__0; wire axready_reg; wire axready_reg_0; wire axvalid; wire b_awid; wire b_push; wire \int_addr_reg[3] ; wire [29:0]p_0_in; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; ddr3_ifmig_7series_v4_0_axi_mc_wr_cmd_fsm aw_cmd_fsm_0 (.CLK(CLK), .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .\RD_PRI_REG_STARVE.rnw_i_reg (\RD_PRI_REG_STARVE.rnw_i_reg ), .\RD_PRI_REG_STARVE.rnw_i_reg_0 (\RD_PRI_REG_STARVE.rnw_i_reg_0 ), .S(aw_cmd_fsm_0_n_102), .\app_addr_r1_reg[10] (\app_addr_r1_reg[10] ), .\app_addr_r1_reg[11] (\app_addr_r1_reg[11] ), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[13] (\app_addr_r1_reg[13] ), .\app_addr_r1_reg[14] (\app_addr_r1_reg[14] ), .\app_addr_r1_reg[15] (\app_addr_r1_reg[15] ), .\app_addr_r1_reg[16] (\app_addr_r1_reg[16] ), .\app_addr_r1_reg[17] (\app_addr_r1_reg[17] ), .\app_addr_r1_reg[18] (\app_addr_r1_reg[18] ), .\app_addr_r1_reg[19] (\app_addr_r1_reg[19] ), .\app_addr_r1_reg[20] (\app_addr_r1_reg[20] ), .\app_addr_r1_reg[21] (\app_addr_r1_reg[21] ), .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ), .\app_addr_r1_reg[23] (\app_addr_r1_reg[23] ), .\app_addr_r1_reg[24] (\app_addr_r1_reg[24] ), .\app_addr_r1_reg[25] (\app_addr_r1_reg[25] ), .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[3] (\app_addr_r1_reg[3] ), .\app_addr_r1_reg[4] (\app_addr_r1_reg[4] ), .\app_addr_r1_reg[5] (\app_addr_r1_reg[5] ), .\app_addr_r1_reg[6] (\app_addr_r1_reg[6] ), .\app_addr_r1_reg[7] (\app_addr_r1_reg[7] ), .\app_addr_r1_reg[8] (\app_addr_r1_reg[8] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_146), .\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}), .\axaddr_incr_reg[29]_0 (p_0_in), .\axaddr_incr_reg[29]_1 (axaddr_incr), .\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}), .\axaddr_reg[29]_0 (axaddr), .axburst(axburst), .\axburst_reg[1] (aw_cmd_fsm_0_n_14), .axid(axid), .\axlen_cnt_reg[0] (\axi_mc_wrap_cmd_0/axlen_cnt ), .\axlen_cnt_reg[3] ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}), .\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .axlen_int(axlen_int), .\axlen_reg[7] (axlen_int__0), .\axlen_reg[7]_0 (axlen), .axready_reg_0(axready_reg), .axready_reg_1(axready_reg_0), .axvalid(axvalid), .b_awid(b_awid), .b_push(b_push), .in0(axi_mc_incr_cmd_byte_addr), .\int_addr_reg[3] ({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}), .\int_addr_reg[3]_0 (\int_addr_reg[3] ), .\int_addr_reg[3]_1 (\axi_mc_wrap_cmd_0/int_addr ), .out(\axi_mc_incr_cmd_0/p_0_in ), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid)); FDRE #( .INIT(1'b0)) \axaddr_reg[0] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[0]), .Q(axaddr[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[10] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[10]), .Q(axaddr[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[11] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[11]), .Q(axaddr[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[12] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[12]), .Q(axaddr[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[13] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[13]), .Q(axaddr[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[14] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[14]), .Q(axaddr[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[15] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[15]), .Q(axaddr[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[16] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[16]), .Q(axaddr[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[17] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[17]), .Q(axaddr[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[18] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[18]), .Q(axaddr[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[19] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[19]), .Q(axaddr[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[1] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[1]), .Q(axaddr[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[20] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[20]), .Q(axaddr[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[21] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[21]), .Q(axaddr[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[22] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[22]), .Q(axaddr[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[23] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[23]), .Q(axaddr[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[24] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[24]), .Q(axaddr[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[25] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[25]), .Q(axaddr[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[26] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[26]), .Q(axaddr[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[27] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[27]), .Q(axaddr[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[28] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[28]), .Q(axaddr[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[29] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[29]), .Q(axaddr[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[2] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[2]), .Q(axaddr[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[3] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[3]), .Q(axaddr[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[4] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[4]), .Q(axaddr[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[5] (.C(CLK), .CE(1'b1), .D(axaddr_int[5]), .Q(axaddr[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[6] (.C(CLK), .CE(1'b1), .D(axaddr_int[6]), .Q(axaddr[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[7] (.C(CLK), .CE(1'b1), .D(axaddr_int[7]), .Q(axaddr[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[8] (.C(CLK), .CE(1'b1), .D(axaddr_int[8]), .Q(axaddr[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axaddr_reg[9] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[9]), .Q(axaddr[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axburst_reg[1] (.C(CLK), .CE(1'b1), .D(aw_cmd_fsm_0_n_14), .Q(axburst), .R(1'b0)); ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator axi_mc_cmd_translator_0 (.CLK(CLK), .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .S(aw_cmd_fsm_0_n_102), .\app_addr_r1_reg[27] (axaddr_incr), .areset_d1(areset_d1), .\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .\axlen_cnt_reg[3]_0 ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}), .axready_reg({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}), .axready_reg_0(aw_cmd_fsm_0_n_146), .axready_reg_1(p_0_in), .axready_reg_2(\axi_mc_wrap_cmd_0/axlen_cnt ), .axready_reg_3({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}), .in0(axi_mc_incr_cmd_byte_addr), .\int_addr_reg[3] (\axi_mc_wrap_cmd_0/int_addr ), .out(\axi_mc_incr_cmd_0/p_0_in )); FDRE #( .INIT(1'b0)) \axid_reg[0] (.C(CLK), .CE(1'b1), .D(b_awid), .Q(axid), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[0] (.C(CLK), .CE(1'b1), .D(axlen_int[0]), .Q(axlen[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[1] (.C(CLK), .CE(1'b1), .D(axlen_int[1]), .Q(axlen[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[2] (.C(CLK), .CE(1'b1), .D(axlen_int[2]), .Q(axlen[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[3] (.C(CLK), .CE(1'b1), .D(axlen_int[3]), .Q(axlen[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[4] (.C(CLK), .CE(1'b1), .D(axlen_int__0[4]), .Q(axlen[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[5] (.C(CLK), .CE(1'b1), .D(axlen_int__0[5]), .Q(axlen[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[6] (.C(CLK), .CE(1'b1), .D(axlen_int__0[6]), .Q(axlen[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \axlen_reg[7] (.C(CLK), .CE(1'b1), .D(axlen_int__0[7]), .Q(axlen[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) axvalid_reg (.C(CLK), .CE(1'b1), .D(awvalid_int), .Q(axvalid), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_b_channel" *) module ddr3_ifmig_7series_v4_0_axi_mc_b_channel (s_axi_bid, s_axi_bvalid, app_en_ns1, wr_cmd_en, E, b_push, b_awid, CLK, areset_d1, app_rdy, \RD_PRI_REG_STARVE.rnw_i_reg , rd_cmd_en, reset_reg, app_en_r1, s_axi_bready, wvalid_int, awvalid_int, app_wdf_rdy); output [0:0]s_axi_bid; output s_axi_bvalid; output app_en_ns1; output wr_cmd_en; output [0:0]E; input b_push; input b_awid; input CLK; input areset_d1; input app_rdy; input \RD_PRI_REG_STARVE.rnw_i_reg ; input rd_cmd_en; input reset_reg; input app_en_r1; input s_axi_bready; input wvalid_int; input awvalid_int; input app_wdf_rdy; wire CLK; wire [0:0]E; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire app_en_ns1; wire app_en_r1; wire app_rdy; wire app_wdf_rdy; wire areset_d1; wire awvalid_int; wire b_awid; wire b_push; wire bhandshake; wire bid_fifo_0_n_5; wire bid_i; wire rd_cmd_en; wire reset_reg; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire wr_cmd_en; wire wvalid_int; ddr3_ifmig_7series_v4_0_axi_mc_fifo bid_fifo_0 (.CLK(CLK), .E(E), .\RD_PRI_REG_STARVE.rnw_i_reg (\RD_PRI_REG_STARVE.rnw_i_reg ), .app_en_ns1(app_en_ns1), .app_en_r1(app_en_r1), .app_rdy(app_rdy), .app_wdf_rdy(app_wdf_rdy), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .b_awid(b_awid), .b_push(b_push), .bhandshake(bhandshake), .bid_i(bid_i), .bvalid_i_reg(bid_fifo_0_n_5), .bvalid_i_reg_0(s_axi_bvalid), .rd_cmd_en(rd_cmd_en), .reset_reg(reset_reg), .s_axi_bready(s_axi_bready), .wr_cmd_en(wr_cmd_en), .wvalid_int(wvalid_int)); FDRE #( .INIT(1'b0)) \bid_t_reg[0] (.C(CLK), .CE(bhandshake), .D(bid_i), .Q(s_axi_bid), .R(areset_d1)); FDRE #( .INIT(1'b0)) bvalid_i_reg (.C(CLK), .CE(1'b1), .D(bid_fifo_0_n_5), .Q(s_axi_bvalid), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_cmd_arbiter" *) module ddr3_ifmig_7series_v4_0_axi_mc_cmd_arbiter (\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 , mc_app_wdf_wren_reg_reg, next, \axaddr_incr_reg[29] , \axlen_cnt_reg[1] , \axaddr_incr_reg[29]_0 , \axlen_cnt_reg[1]_0 , areset_d1, CLK, rd_cmd_en, wr_cmd_en, app_rdy, s_axi_awburst, s_axi_awready, s_axi_awvalid, s_axi_arburst, axready_reg, s_axi_arvalid, E); output \RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ; output mc_app_wdf_wren_reg_reg; output next; output \axaddr_incr_reg[29] ; output \axlen_cnt_reg[1] ; output \axaddr_incr_reg[29]_0 ; output \axlen_cnt_reg[1]_0 ; input areset_d1; input CLK; input rd_cmd_en; input wr_cmd_en; input app_rdy; input [0:0]s_axi_awburst; input s_axi_awready; input s_axi_awvalid; input [0:0]s_axi_arburst; input axready_reg; input s_axi_arvalid; input [0:0]E; wire CLK; wire [0:0]E; wire \RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ; wire \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ; wire \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ; wire [8:8]\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ; wire \RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ; wire \RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ; wire \RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ; wire \RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ; wire \RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ; wire \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ; wire \RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ; wire [7:0]\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 ; wire app_rdy; wire areset_d1; wire \axaddr_incr_reg[29] ; wire \axaddr_incr_reg[29]_0 ; wire \axlen_cnt_reg[1] ; wire \axlen_cnt_reg[1]_0 ; wire axready_reg; wire mc_app_wdf_wren_reg_reg; wire next; wire [8:0]p_0_in__0; wire [7:0]p_0_in__1; wire rd_cmd_en; wire rd_cmd_en_d1; wire [0:0]s_axi_arburst; wire s_axi_arvalid; wire [0:0]s_axi_awburst; wire s_axi_awready; wire s_axi_awvalid; wire wr_cmd_en; wire wr_cmd_en_d1; wire wr_enable; wire wr_starve_cnt; wire wr_starve_cnt0; (* SOFT_HLUTNM = "soft_lutpair1154" *) LUT4 #( .INIT(16'h8F80)) \RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1 (.I0(rd_cmd_en), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(app_rdy), .I3(rd_cmd_en_d1), .O(\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_cmd_en_d1_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ), .Q(rd_cmd_en_d1), .R(areset_d1)); LUT1 #( .INIT(2'h1)) \RD_PRI_REG_STARVE.rd_starve_cnt[0]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair1158" *) LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.rd_starve_cnt[1]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair1158" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.rd_starve_cnt[2]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair1151" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.rd_starve_cnt[3]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair1151" *) LUT5 #( .INIT(32'h7FFF8000)) \RD_PRI_REG_STARVE.rd_starve_cnt[4]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .I4(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \RD_PRI_REG_STARVE.rd_starve_cnt[5]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I4(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .I5(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ), .O(p_0_in__0[5])); LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.rd_starve_cnt[6]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair1156" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.rd_starve_cnt[7]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ), .O(p_0_in__0[7])); LUT2 #( .INIT(4'hE)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1 (.I0(areset_d1), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .O(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1156" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_3 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ), .O(p_0_in__0[8])); LUT6 #( .INIT(64'h8000000000000000)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I4(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I5(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .O(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[0] (.C(CLK), .CE(E), .D(p_0_in__0[0]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[1] (.C(CLK), .CE(E), .D(p_0_in__0[1]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[2] (.C(CLK), .CE(E), .D(p_0_in__0[2]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[3] (.C(CLK), .CE(E), .D(p_0_in__0[3]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[4] (.C(CLK), .CE(E), .D(p_0_in__0[4]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[5] (.C(CLK), .CE(E), .D(p_0_in__0[5]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[6] (.C(CLK), .CE(E), .D(p_0_in__0[6]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[7] (.C(CLK), .CE(E), .D(p_0_in__0[7]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] (.C(CLK), .CE(E), .D(p_0_in__0[8]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); LUT5 #( .INIT(32'h55554445)) \RD_PRI_REG_STARVE.rnw_i_i_1 (.I0(wr_enable), .I1(rd_cmd_en), .I2(wr_cmd_en_d1), .I3(wr_cmd_en), .I4(rd_cmd_en_d1), .O(\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 )); FDSE #( .INIT(1'b1)) \RD_PRI_REG_STARVE.rnw_i_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .S(areset_d1)); LUT4 #( .INIT(16'h2F20)) \RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1 (.I0(wr_cmd_en), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(app_rdy), .I3(wr_cmd_en_d1), .O(\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_cmd_en_d1_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ), .Q(wr_cmd_en_d1), .R(areset_d1)); LUT5 #( .INIT(32'h0000BAAA)) \RD_PRI_REG_STARVE.wr_enable_i_1 (.I0(wr_enable), .I1(\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ), .I2(app_rdy), .I3(wr_cmd_en), .I4(wr_starve_cnt0), .O(\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \RD_PRI_REG_STARVE.wr_enable_i_2 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .I4(\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ), .O(\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1155" *) LUT4 #( .INIT(16'h7FFF)) \RD_PRI_REG_STARVE.wr_enable_i_3 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .O(\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_enable_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ), .Q(wr_enable), .R(1'b0)); LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.wr_starve_cnt[0]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair1155" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.wr_starve_cnt[1]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair1152" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.wr_starve_cnt[2]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair1152" *) LUT5 #( .INIT(32'h7FFF8000)) \RD_PRI_REG_STARVE.wr_starve_cnt[3]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I4(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .O(p_0_in__1[3])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \RD_PRI_REG_STARVE.wr_starve_cnt[4]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I4(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .I5(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .O(p_0_in__1[4])); LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.wr_starve_cnt[5]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .O(p_0_in__1[5])); (* SOFT_HLUTNM = "soft_lutpair1157" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.wr_starve_cnt[6]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .O(p_0_in__1[6])); LUT4 #( .INIT(16'hEEEF)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_1 (.I0(areset_d1), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ), .I2(wr_cmd_en_d1), .I3(wr_cmd_en), .O(wr_starve_cnt0)); LUT3 #( .INIT(8'h80)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_2 (.I0(app_rdy), .I1(\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ), .I2(wr_cmd_en), .O(wr_starve_cnt)); (* SOFT_HLUTNM = "soft_lutpair1157" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_3 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]), .O(p_0_in__1[7])); LUT6 #( .INIT(64'h8000000000000000)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I4(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I5(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .O(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[0] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[0]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[1] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[1]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[2] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[2]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[3] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[3]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[4] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[4]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[5] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[5]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[6] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[6]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .R(wr_starve_cnt0)); FDRE #( .INIT(1'b0)) \RD_PRI_REG_STARVE.wr_starve_cnt_reg[7] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[7]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]), .R(wr_starve_cnt0)); LUT4 #( .INIT(16'h1000)) \axlen_cnt[7]_i_5 (.I0(mc_app_wdf_wren_reg_reg), .I1(s_axi_awburst), .I2(s_axi_awready), .I3(s_axi_awvalid), .O(\axaddr_incr_reg[29] )); (* SOFT_HLUTNM = "soft_lutpair1153" *) LUT4 #( .INIT(16'h1000)) \axlen_cnt[7]_i_5__0 (.I0(next), .I1(s_axi_arburst), .I2(axready_reg), .I3(s_axi_arvalid), .O(\axaddr_incr_reg[29]_0 )); LUT4 #( .INIT(16'h4000)) \int_addr[3]_i_3 (.I0(mc_app_wdf_wren_reg_reg), .I1(s_axi_awburst), .I2(s_axi_awready), .I3(s_axi_awvalid), .O(\axlen_cnt_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1153" *) LUT4 #( .INIT(16'h4000)) \int_addr[3]_i_3__0 (.I0(next), .I1(s_axi_arburst), .I2(axready_reg), .I3(s_axi_arvalid), .O(\axlen_cnt_reg[1]_0 )); LUT3 #( .INIT(8'h40)) mc_app_wdf_wren_reg_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I1(app_rdy), .I2(wr_cmd_en), .O(mc_app_wdf_wren_reg_reg)); (* SOFT_HLUTNM = "soft_lutpair1154" *) LUT3 #( .INIT(8'h80)) r_push_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I1(app_rdy), .I2(rd_cmd_en), .O(next)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_cmd_fsm" *) module ddr3_ifmig_7series_v4_0_axi_mc_cmd_fsm (s_axi_arready, D, \app_addr_r1_reg[27] , \axaddr_incr_reg[29] , \axaddr_reg[29] , \axlen_cnt_reg[7] , r_rlast_reg, \axburst_reg[1] , in0, \app_addr_r1_reg[6] , S, \axaddr_incr_reg[29]_0 , \int_addr_reg[3] , \axlen_cnt_reg[3] , arvalid_int, E, \axlen_cnt_reg[0] , DI, \axid_reg[0] , areset_d1, CLK, Q, \axaddr_incr_reg[6] , \axaddr_incr_reg[7] , \axaddr_incr_reg[29]_1 , \axaddr_incr_reg[9] , \axaddr_incr_reg[10] , \axaddr_incr_reg[11] , \axaddr_incr_reg[12] , \axaddr_incr_reg[13] , \axaddr_incr_reg[14] , \axaddr_incr_reg[15] , \axaddr_incr_reg[16] , \axaddr_incr_reg[17] , \axaddr_incr_reg[18] , \axaddr_incr_reg[19] , \axaddr_incr_reg[20] , \axaddr_incr_reg[21] , \axaddr_incr_reg[22] , \axaddr_incr_reg[23] , \axaddr_incr_reg[24] , \axaddr_incr_reg[25] , \axaddr_incr_reg[26] , \axaddr_incr_reg[27] , \axaddr_incr_reg[28] , \axaddr_incr_reg[29]_2 , \axaddr_incr_reg[5] , axready_reg_0, s_axi_arlen, \axlen_reg[7] , next, axvalid, s_axi_arvalid, s_axi_araddr, \axaddr_reg[29]_0 , \int_addr_reg[3]_0 , \RD_PRI_REG_STARVE.rnw_i_reg , out, axready_reg_1, \axlen_cnt_reg[3]_0 , axburst, s_axi_arburst, s_axi_arid, in); output s_axi_arready; output [7:0]D; output [23:0]\app_addr_r1_reg[27] ; output [22:0]\axaddr_incr_reg[29] ; output [29:0]\axaddr_reg[29] ; output [7:0]\axlen_cnt_reg[7] ; output r_rlast_reg; output \axburst_reg[1] ; output [3:0]in0; output \app_addr_r1_reg[6] ; output [2:0]S; output [29:0]\axaddr_incr_reg[29]_0 ; output [3:0]\int_addr_reg[3] ; output [3:0]\axlen_cnt_reg[3] ; output arvalid_int; output [0:0]E; output [0:0]\axlen_cnt_reg[0] ; output [0:0]DI; output \axid_reg[0] ; input areset_d1; input CLK; input [7:0]Q; input \axaddr_incr_reg[6] ; input \axaddr_incr_reg[7] ; input [29:0]\axaddr_incr_reg[29]_1 ; input \axaddr_incr_reg[9] ; input \axaddr_incr_reg[10] ; input \axaddr_incr_reg[11] ; input \axaddr_incr_reg[12] ; input \axaddr_incr_reg[13] ; input \axaddr_incr_reg[14] ; input \axaddr_incr_reg[15] ; input \axaddr_incr_reg[16] ; input \axaddr_incr_reg[17] ; input \axaddr_incr_reg[18] ; input \axaddr_incr_reg[19] ; input \axaddr_incr_reg[20] ; input \axaddr_incr_reg[21] ; input \axaddr_incr_reg[22] ; input \axaddr_incr_reg[23] ; input \axaddr_incr_reg[24] ; input \axaddr_incr_reg[25] ; input \axaddr_incr_reg[26] ; input \axaddr_incr_reg[27] ; input \axaddr_incr_reg[28] ; input \axaddr_incr_reg[29]_2 ; input \axaddr_incr_reg[5] ; input axready_reg_0; input [7:0]s_axi_arlen; input [7:0]\axlen_reg[7] ; input next; input axvalid; input s_axi_arvalid; input [29:0]s_axi_araddr; input [29:0]\axaddr_reg[29]_0 ; input [3:0]\int_addr_reg[3]_0 ; input \RD_PRI_REG_STARVE.rnw_i_reg ; input [29:0]out; input axready_reg_1; input [3:0]\axlen_cnt_reg[3]_0 ; input [0:0]axburst; input [0:0]s_axi_arburst; input [0:0]s_axi_arid; input [0:0]in; wire CLK; wire [7:0]D; wire [0:0]DI; wire [0:0]E; wire [7:0]Q; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire [2:0]S; wire \app_addr_r1[27]_i_3_n_0 ; wire \app_addr_r1[27]_i_4_n_0 ; wire \app_addr_r1[6]_i_6_n_0 ; wire [23:0]\app_addr_r1_reg[27] ; wire \app_addr_r1_reg[6] ; wire areset_d1; wire arvalid_int; wire \axaddr_incr_reg[10] ; wire \axaddr_incr_reg[11] ; wire \axaddr_incr_reg[12] ; wire \axaddr_incr_reg[13] ; wire \axaddr_incr_reg[14] ; wire \axaddr_incr_reg[15] ; wire \axaddr_incr_reg[16] ; wire \axaddr_incr_reg[17] ; wire \axaddr_incr_reg[18] ; wire \axaddr_incr_reg[19] ; wire \axaddr_incr_reg[20] ; wire \axaddr_incr_reg[21] ; wire \axaddr_incr_reg[22] ; wire \axaddr_incr_reg[23] ; wire \axaddr_incr_reg[24] ; wire \axaddr_incr_reg[25] ; wire \axaddr_incr_reg[26] ; wire \axaddr_incr_reg[27] ; wire \axaddr_incr_reg[28] ; wire [22:0]\axaddr_incr_reg[29] ; wire [29:0]\axaddr_incr_reg[29]_0 ; wire [29:0]\axaddr_incr_reg[29]_1 ; wire \axaddr_incr_reg[29]_2 ; wire \axaddr_incr_reg[5] ; wire \axaddr_incr_reg[6] ; wire \axaddr_incr_reg[7] ; wire \axaddr_incr_reg[9] ; wire [29:0]\axaddr_reg[29] ; wire [29:0]\axaddr_reg[29]_0 ; wire [0:0]axburst; wire \axburst_reg[1] ; wire [3:2]\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 ; wire [8:5]\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ; wire \axi_mc_cmd_translator_0/incr_axhandshake ; wire \axi_mc_cmd_translator_0/wrap_axhandshake ; wire [7:5]axi_mc_incr_cmd_byte_addr__0; wire \axid_reg[0] ; wire \axlen_cnt[2]_i_2__1_n_0 ; wire \axlen_cnt[2]_i_2__2_n_0 ; wire \axlen_cnt[3]_i_2__1_n_0 ; wire \axlen_cnt[3]_i_2__2_n_0 ; wire \axlen_cnt[4]_i_2__0_n_0 ; wire \axlen_cnt[4]_i_3__0_n_0 ; wire \axlen_cnt[5]_i_2__0_n_0 ; wire \axlen_cnt[5]_i_3__0_n_0 ; wire \axlen_cnt[7]_i_3__0_n_0 ; wire \axlen_cnt[7]_i_4__0_n_0 ; wire [0:0]\axlen_cnt_reg[0] ; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [7:0]\axlen_cnt_reg[7] ; wire [7:0]\axlen_reg[7] ; wire axready_i_1__0_n_0; wire axready_reg_0; wire axready_reg_1; wire axvalid; wire [0:0]in; wire [3:0]in0; wire \int_addr[3]_i_5__0_n_0 ; wire [3:0]\int_addr_reg[3] ; wire [3:0]\int_addr_reg[3]_0 ; wire next; wire [29:0]out; wire r_rlast_i_4_n_0; wire r_rlast_i_5_n_0; wire r_rlast_i_6_n_0; wire r_rlast_reg; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[10]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [12]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [12]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[12] ), .O(\app_addr_r1_reg[27] [6])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[11]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [13]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [13]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[13] ), .O(\app_addr_r1_reg[27] [7])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[12]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [14]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [14]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[14] ), .O(\app_addr_r1_reg[27] [8])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[13]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [15]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [15]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[15] ), .O(\app_addr_r1_reg[27] [9])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[14]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [16]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [16]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[16] ), .O(\app_addr_r1_reg[27] [10])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[15]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [17]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [17]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[17] ), .O(\app_addr_r1_reg[27] [11])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[16]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [18]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [18]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[18] ), .O(\app_addr_r1_reg[27] [12])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[17]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [19]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [19]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[19] ), .O(\app_addr_r1_reg[27] [13])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[18]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [20]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [20]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[20] ), .O(\app_addr_r1_reg[27] [14])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[19]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [21]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [21]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[21] ), .O(\app_addr_r1_reg[27] [15])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[20]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [22]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [22]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[22] ), .O(\app_addr_r1_reg[27] [16])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[21]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [23]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [23]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[23] ), .O(\app_addr_r1_reg[27] [17])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[22]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [24]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [24]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[24] ), .O(\app_addr_r1_reg[27] [18])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[23]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [25]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [25]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[25] ), .O(\app_addr_r1_reg[27] [19])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[24]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [26]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [26]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[26] ), .O(\app_addr_r1_reg[27] [20])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[25]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [27]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [27]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[27] ), .O(\app_addr_r1_reg[27] [21])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[26]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [28]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [28]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[28] ), .O(\app_addr_r1_reg[27] [22])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[27]_i_2 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [29]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [29]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[29]_2 ), .O(\app_addr_r1_reg[27] [23])); (* SOFT_HLUTNM = "soft_lutpair1124" *) LUT4 #( .INIT(16'h02A2)) \app_addr_r1[27]_i_3 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(axburst), .I2(s_axi_arready), .I3(s_axi_arburst), .O(\app_addr_r1[27]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1124" *) LUT4 #( .INIT(16'hE200)) \app_addr_r1[27]_i_4 (.I0(axburst), .I1(s_axi_arready), .I2(s_axi_arburst), .I3(\RD_PRI_REG_STARVE.rnw_i_reg ), .O(\app_addr_r1[27]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFF888)) \app_addr_r1[3]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(axi_mc_incr_cmd_byte_addr__0[5]), .I2(\app_addr_r1[27]_i_4_n_0 ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I4(\axaddr_incr_reg[5] ), .O(\app_addr_r1_reg[27] [0])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[3]_i_2 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .O(axi_mc_incr_cmd_byte_addr__0[5])); LUT5 #( .INIT(32'hFFFFF888)) \app_addr_r1[4]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(axi_mc_incr_cmd_byte_addr__0[6]), .I2(\app_addr_r1[27]_i_4_n_0 ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]), .I4(\axaddr_incr_reg[6] ), .O(\app_addr_r1_reg[27] [1])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[4]_i_2 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .O(axi_mc_incr_cmd_byte_addr__0[6])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[4]_i_3 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [1]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6])); LUT5 #( .INIT(32'hFFFFF888)) \app_addr_r1[5]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(axi_mc_incr_cmd_byte_addr__0[7]), .I2(\app_addr_r1[27]_i_4_n_0 ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I4(\axaddr_incr_reg[7] ), .O(\app_addr_r1_reg[27] [2])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[5]_i_2 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .O(axi_mc_incr_cmd_byte_addr__0[7])); LUT6 #( .INIT(64'hCACFCAC000000000)) \app_addr_r1[6]_i_2 (.I0(\int_addr_reg[3]_0 [3]), .I1(\axaddr_reg[29] [8]), .I2(\app_addr_r1[6]_i_6_n_0 ), .I3(\axburst_reg[1] ), .I4(\axaddr_incr_reg[29]_1 [8]), .I5(\RD_PRI_REG_STARVE.rnw_i_reg ), .O(\app_addr_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair1127" *) LUT2 #( .INIT(4'h8)) \app_addr_r1[6]_i_6 (.I0(s_axi_arvalid), .I1(s_axi_arready), .O(\app_addr_r1[6]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[7]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [9]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [9]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[9] ), .O(\app_addr_r1_reg[27] [3])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[8]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [10]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [10]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[10] ), .O(\app_addr_r1_reg[27] [4])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[9]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [11]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [11]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[11] ), .O(\app_addr_r1_reg[27] [5])); (* SOFT_HLUTNM = "soft_lutpair1092" *) LUT3 #( .INIT(8'hB8)) \axaddr[0]_i_1__0 (.I0(s_axi_araddr[0]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [0]), .O(\axaddr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1104" *) LUT3 #( .INIT(8'hB8)) \axaddr[10]_i_1__0 (.I0(s_axi_araddr[10]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [10]), .O(\axaddr_reg[29] [10])); (* SOFT_HLUTNM = "soft_lutpair1105" *) LUT3 #( .INIT(8'hB8)) \axaddr[11]_i_1__0 (.I0(s_axi_araddr[11]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [11]), .O(\axaddr_reg[29] [11])); (* SOFT_HLUTNM = "soft_lutpair1106" *) LUT3 #( .INIT(8'hB8)) \axaddr[12]_i_1__0 (.I0(s_axi_araddr[12]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [12]), .O(\axaddr_reg[29] [12])); (* SOFT_HLUTNM = "soft_lutpair1112" *) LUT3 #( .INIT(8'hB8)) \axaddr[13]_i_1__0 (.I0(s_axi_araddr[13]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [13]), .O(\axaddr_reg[29] [13])); (* SOFT_HLUTNM = "soft_lutpair1107" *) LUT3 #( .INIT(8'hB8)) \axaddr[14]_i_1__0 (.I0(s_axi_araddr[14]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [14]), .O(\axaddr_reg[29] [14])); (* SOFT_HLUTNM = "soft_lutpair1109" *) LUT3 #( .INIT(8'hB8)) \axaddr[15]_i_1__0 (.I0(s_axi_araddr[15]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [15]), .O(\axaddr_reg[29] [15])); (* SOFT_HLUTNM = "soft_lutpair1110" *) LUT3 #( .INIT(8'hB8)) \axaddr[16]_i_1__0 (.I0(s_axi_araddr[16]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [16]), .O(\axaddr_reg[29] [16])); (* SOFT_HLUTNM = "soft_lutpair1116" *) LUT3 #( .INIT(8'hB8)) \axaddr[17]_i_1__0 (.I0(s_axi_araddr[17]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [17]), .O(\axaddr_reg[29] [17])); (* SOFT_HLUTNM = "soft_lutpair1111" *) LUT3 #( .INIT(8'hB8)) \axaddr[18]_i_1__0 (.I0(s_axi_araddr[18]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [18]), .O(\axaddr_reg[29] [18])); (* SOFT_HLUTNM = "soft_lutpair1113" *) LUT3 #( .INIT(8'hB8)) \axaddr[19]_i_1__0 (.I0(s_axi_araddr[19]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [19]), .O(\axaddr_reg[29] [19])); (* SOFT_HLUTNM = "soft_lutpair1093" *) LUT3 #( .INIT(8'hB8)) \axaddr[1]_i_1__0 (.I0(s_axi_araddr[1]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [1]), .O(\axaddr_reg[29] [1])); (* SOFT_HLUTNM = "soft_lutpair1114" *) LUT3 #( .INIT(8'hB8)) \axaddr[20]_i_1__0 (.I0(s_axi_araddr[20]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [20]), .O(\axaddr_reg[29] [20])); (* SOFT_HLUTNM = "soft_lutpair1120" *) LUT3 #( .INIT(8'hB8)) \axaddr[21]_i_1__0 (.I0(s_axi_araddr[21]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [21]), .O(\axaddr_reg[29] [21])); (* SOFT_HLUTNM = "soft_lutpair1115" *) LUT3 #( .INIT(8'hB8)) \axaddr[22]_i_1__0 (.I0(s_axi_araddr[22]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [22]), .O(\axaddr_reg[29] [22])); (* SOFT_HLUTNM = "soft_lutpair1117" *) LUT3 #( .INIT(8'hB8)) \axaddr[23]_i_1__0 (.I0(s_axi_araddr[23]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [23]), .O(\axaddr_reg[29] [23])); (* SOFT_HLUTNM = "soft_lutpair1118" *) LUT3 #( .INIT(8'hB8)) \axaddr[24]_i_1__0 (.I0(s_axi_araddr[24]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [24]), .O(\axaddr_reg[29] [24])); (* SOFT_HLUTNM = "soft_lutpair1100" *) LUT3 #( .INIT(8'hB8)) \axaddr[25]_i_1__0 (.I0(s_axi_araddr[25]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [25]), .O(\axaddr_reg[29] [25])); (* SOFT_HLUTNM = "soft_lutpair1119" *) LUT3 #( .INIT(8'hB8)) \axaddr[26]_i_1__0 (.I0(s_axi_araddr[26]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [26]), .O(\axaddr_reg[29] [26])); (* SOFT_HLUTNM = "soft_lutpair1121" *) LUT3 #( .INIT(8'hB8)) \axaddr[27]_i_1__0 (.I0(s_axi_araddr[27]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [27]), .O(\axaddr_reg[29] [27])); (* SOFT_HLUTNM = "soft_lutpair1122" *) LUT3 #( .INIT(8'hB8)) \axaddr[28]_i_1__0 (.I0(s_axi_araddr[28]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [28]), .O(\axaddr_reg[29] [28])); (* SOFT_HLUTNM = "soft_lutpair1123" *) LUT3 #( .INIT(8'hB8)) \axaddr[29]_i_1__0 (.I0(s_axi_araddr[29]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [29]), .O(\axaddr_reg[29] [29])); (* SOFT_HLUTNM = "soft_lutpair1094" *) LUT3 #( .INIT(8'hB8)) \axaddr[2]_i_1__0 (.I0(s_axi_araddr[2]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [2]), .O(\axaddr_reg[29] [2])); (* SOFT_HLUTNM = "soft_lutpair1095" *) LUT3 #( .INIT(8'hB8)) \axaddr[3]_i_1__0 (.I0(s_axi_araddr[3]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [3]), .O(\axaddr_reg[29] [3])); (* SOFT_HLUTNM = "soft_lutpair1098" *) LUT3 #( .INIT(8'hB8)) \axaddr[4]_i_1__0 (.I0(s_axi_araddr[4]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [4]), .O(\axaddr_reg[29] [4])); (* SOFT_HLUTNM = "soft_lutpair1097" *) LUT3 #( .INIT(8'hB8)) \axaddr[5]_i_1__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .O(\axaddr_reg[29] [5])); (* SOFT_HLUTNM = "soft_lutpair1099" *) LUT3 #( .INIT(8'hB8)) \axaddr[6]_i_1__0 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .O(\axaddr_reg[29] [6])); (* SOFT_HLUTNM = "soft_lutpair1102" *) LUT3 #( .INIT(8'hB8)) \axaddr[7]_i_1__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .O(\axaddr_reg[29] [7])); (* SOFT_HLUTNM = "soft_lutpair1103" *) LUT3 #( .INIT(8'hB8)) \axaddr[8]_i_1__0 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .O(\axaddr_reg[29] [8])); (* SOFT_HLUTNM = "soft_lutpair1108" *) LUT3 #( .INIT(8'hB8)) \axaddr[9]_i_1__0 (.I0(s_axi_araddr[9]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [9]), .O(\axaddr_reg[29] [9])); (* SOFT_HLUTNM = "soft_lutpair1092" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[0]_i_1__0 (.I0(s_axi_araddr[0]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [0]), .I3(axready_reg_0), .I4(out[0]), .O(\axaddr_incr_reg[29]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair1104" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[10]_i_1__0 (.I0(s_axi_araddr[10]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [10]), .I3(axready_reg_0), .I4(out[10]), .O(\axaddr_incr_reg[29]_0 [10])); (* SOFT_HLUTNM = "soft_lutpair1105" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[11]_i_1__0 (.I0(s_axi_araddr[11]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [11]), .I3(axready_reg_0), .I4(out[11]), .O(\axaddr_incr_reg[29]_0 [11])); (* SOFT_HLUTNM = "soft_lutpair1106" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[12]_i_1__0 (.I0(s_axi_araddr[12]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [12]), .I3(axready_reg_0), .I4(out[12]), .O(\axaddr_incr_reg[29]_0 [12])); (* SOFT_HLUTNM = "soft_lutpair1112" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[13]_i_1__0 (.I0(s_axi_araddr[13]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [13]), .I3(axready_reg_0), .I4(out[13]), .O(\axaddr_incr_reg[29]_0 [13])); (* SOFT_HLUTNM = "soft_lutpair1107" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[14]_i_1__0 (.I0(s_axi_araddr[14]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [14]), .I3(axready_reg_0), .I4(out[14]), .O(\axaddr_incr_reg[29]_0 [14])); (* SOFT_HLUTNM = "soft_lutpair1109" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[15]_i_1__0 (.I0(s_axi_araddr[15]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [15]), .I3(axready_reg_0), .I4(out[15]), .O(\axaddr_incr_reg[29]_0 [15])); (* SOFT_HLUTNM = "soft_lutpair1110" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[16]_i_1__0 (.I0(s_axi_araddr[16]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [16]), .I3(axready_reg_0), .I4(out[16]), .O(\axaddr_incr_reg[29]_0 [16])); (* SOFT_HLUTNM = "soft_lutpair1116" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[17]_i_1__0 (.I0(s_axi_araddr[17]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [17]), .I3(axready_reg_0), .I4(out[17]), .O(\axaddr_incr_reg[29]_0 [17])); (* SOFT_HLUTNM = "soft_lutpair1111" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[18]_i_1__0 (.I0(s_axi_araddr[18]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [18]), .I3(axready_reg_0), .I4(out[18]), .O(\axaddr_incr_reg[29]_0 [18])); (* SOFT_HLUTNM = "soft_lutpair1113" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[19]_i_1__0 (.I0(s_axi_araddr[19]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [19]), .I3(axready_reg_0), .I4(out[19]), .O(\axaddr_incr_reg[29]_0 [19])); (* SOFT_HLUTNM = "soft_lutpair1093" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[1]_i_1__0 (.I0(s_axi_araddr[1]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [1]), .I3(axready_reg_0), .I4(out[1]), .O(\axaddr_incr_reg[29]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair1114" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[20]_i_1__0 (.I0(s_axi_araddr[20]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [20]), .I3(axready_reg_0), .I4(out[20]), .O(\axaddr_incr_reg[29]_0 [20])); (* SOFT_HLUTNM = "soft_lutpair1120" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[21]_i_1__0 (.I0(s_axi_araddr[21]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [21]), .I3(axready_reg_0), .I4(out[21]), .O(\axaddr_incr_reg[29]_0 [21])); (* SOFT_HLUTNM = "soft_lutpair1115" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[22]_i_1__0 (.I0(s_axi_araddr[22]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [22]), .I3(axready_reg_0), .I4(out[22]), .O(\axaddr_incr_reg[29]_0 [22])); (* SOFT_HLUTNM = "soft_lutpair1117" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[23]_i_1__0 (.I0(s_axi_araddr[23]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [23]), .I3(axready_reg_0), .I4(out[23]), .O(\axaddr_incr_reg[29]_0 [23])); (* SOFT_HLUTNM = "soft_lutpair1118" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[24]_i_1__0 (.I0(s_axi_araddr[24]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [24]), .I3(axready_reg_0), .I4(out[24]), .O(\axaddr_incr_reg[29]_0 [24])); (* SOFT_HLUTNM = "soft_lutpair1100" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[25]_i_1__0 (.I0(s_axi_araddr[25]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [25]), .I3(axready_reg_0), .I4(out[25]), .O(\axaddr_incr_reg[29]_0 [25])); (* SOFT_HLUTNM = "soft_lutpair1119" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[26]_i_1__0 (.I0(s_axi_araddr[26]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [26]), .I3(axready_reg_0), .I4(out[26]), .O(\axaddr_incr_reg[29]_0 [26])); (* SOFT_HLUTNM = "soft_lutpair1121" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[27]_i_1__0 (.I0(s_axi_araddr[27]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [27]), .I3(axready_reg_0), .I4(out[27]), .O(\axaddr_incr_reg[29]_0 [27])); (* SOFT_HLUTNM = "soft_lutpair1122" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[28]_i_1__0 (.I0(s_axi_araddr[28]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [28]), .I3(axready_reg_0), .I4(out[28]), .O(\axaddr_incr_reg[29]_0 [28])); (* SOFT_HLUTNM = "soft_lutpair1123" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[29]_i_1__0 (.I0(s_axi_araddr[29]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [29]), .I3(axready_reg_0), .I4(out[29]), .O(\axaddr_incr_reg[29]_0 [29])); (* SOFT_HLUTNM = "soft_lutpair1094" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[2]_i_1__0 (.I0(s_axi_araddr[2]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [2]), .I3(axready_reg_0), .I4(out[2]), .O(\axaddr_incr_reg[29]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair1095" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[3]_i_1__0 (.I0(s_axi_araddr[3]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [3]), .I3(axready_reg_0), .I4(out[3]), .O(\axaddr_incr_reg[29]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair1098" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[4]_i_1__0 (.I0(s_axi_araddr[4]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [4]), .I3(axready_reg_0), .I4(out[4]), .O(\axaddr_incr_reg[29]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair1097" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[5]_i_1__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(axready_reg_0), .I4(out[5]), .O(\axaddr_incr_reg[29]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair1099" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[6]_i_1__0 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(axready_reg_0), .I4(out[6]), .O(\axaddr_incr_reg[29]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair1102" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[7]_i_1__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(axready_reg_0), .I4(out[7]), .O(\axaddr_incr_reg[29]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair1103" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[8]_i_1__0 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .I3(axready_reg_0), .I4(out[8]), .O(\axaddr_incr_reg[29]_0 [8])); (* SOFT_HLUTNM = "soft_lutpair1108" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[9]_i_1__0 (.I0(s_axi_araddr[9]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [9]), .I3(axready_reg_0), .I4(out[9]), .O(\axaddr_incr_reg[29]_0 [9])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_1__0 (.I0(s_axi_araddr[3]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [3]), .O(in0[3])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_2__0 (.I0(s_axi_araddr[2]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [2]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [2]), .O(in0[2])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_3__0 (.I0(s_axi_araddr[1]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [1]), .O(in0[1])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_4__0 (.I0(s_axi_araddr[0]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [0]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [0]), .O(in0[0])); LUT3 #( .INIT(8'h08)) axaddr_incr_p_inferred_i_5__0 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(s_axi_arburst), .O(\axi_mc_cmd_translator_0/incr_axhandshake )); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_1__0 (.I0(s_axi_araddr[11]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [11]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [11]), .O(\axaddr_incr_reg[29] [4])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_2__0 (.I0(s_axi_araddr[10]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [10]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [10]), .O(\axaddr_incr_reg[29] [3])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_3__0 (.I0(s_axi_araddr[9]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [9]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [9]), .O(\axaddr_incr_reg[29] [2])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_4 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [8]), .O(\axaddr_incr_reg[29] [1])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_1__0 (.I0(s_axi_araddr[15]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [15]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [15]), .O(\axaddr_incr_reg[29] [8])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_2__0 (.I0(s_axi_araddr[14]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [14]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [14]), .O(\axaddr_incr_reg[29] [7])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_3__0 (.I0(s_axi_araddr[13]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [13]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [13]), .O(\axaddr_incr_reg[29] [6])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_4__0 (.I0(s_axi_araddr[12]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [12]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [12]), .O(\axaddr_incr_reg[29] [5])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_1__0 (.I0(s_axi_araddr[19]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [19]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [19]), .O(\axaddr_incr_reg[29] [12])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_2__0 (.I0(s_axi_araddr[18]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [18]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [18]), .O(\axaddr_incr_reg[29] [11])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_3__0 (.I0(s_axi_araddr[17]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [17]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [17]), .O(\axaddr_incr_reg[29] [10])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_4__0 (.I0(s_axi_araddr[16]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [16]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [16]), .O(\axaddr_incr_reg[29] [9])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_1__0 (.I0(s_axi_araddr[23]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [23]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [23]), .O(\axaddr_incr_reg[29] [16])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_2__0 (.I0(s_axi_araddr[22]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [22]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [22]), .O(\axaddr_incr_reg[29] [15])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_3__0 (.I0(s_axi_araddr[21]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [21]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [21]), .O(\axaddr_incr_reg[29] [14])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_4__0 (.I0(s_axi_araddr[20]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [20]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [20]), .O(\axaddr_incr_reg[29] [13])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_1__0 (.I0(s_axi_araddr[27]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [27]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [27]), .O(\axaddr_incr_reg[29] [20])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_2__0 (.I0(s_axi_araddr[26]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [26]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [26]), .O(\axaddr_incr_reg[29] [19])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_3__0 (.I0(s_axi_araddr[25]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [25]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [25]), .O(\axaddr_incr_reg[29] [18])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_4__0 (.I0(s_axi_araddr[24]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [24]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [24]), .O(\axaddr_incr_reg[29] [17])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_1__0 (.I0(s_axi_araddr[29]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [29]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [29]), .O(\axaddr_incr_reg[29] [22])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_2__0 (.I0(s_axi_araddr[28]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [28]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [28]), .O(\axaddr_incr_reg[29] [21])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_1__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .O(DI)); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_2__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .O(S[2])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_3__0 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .O(S[1])); LUT5 #( .INIT(32'h111DDD1D)) axaddr_incr_p_reg0_carry_i_4__0 (.I0(\axaddr_incr_reg[29]_1 [5]), .I1(\axi_mc_cmd_translator_0/incr_axhandshake ), .I2(\axaddr_reg[29]_0 [5]), .I3(s_axi_arready), .I4(s_axi_araddr[5]), .O(S[0])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_5__0 (.I0(s_axi_araddr[4]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [4]), .O(\axaddr_incr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1126" *) LUT3 #( .INIT(8'hB8)) \axburst[1]_i_1__0 (.I0(s_axi_arburst), .I1(s_axi_arready), .I2(axburst), .O(\axburst_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1127" *) LUT3 #( .INIT(8'hB8)) \axid[0]_i_1__0 (.I0(s_axi_arid), .I1(s_axi_arready), .I2(in), .O(\axid_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1125" *) LUT3 #( .INIT(8'hB8)) \axlen[0]_i_1__0 (.I0(s_axi_arlen[0]), .I1(s_axi_arready), .I2(\axlen_reg[7] [0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair1126" *) LUT3 #( .INIT(8'hB8)) \axlen[1]_i_1__0 (.I0(s_axi_arlen[1]), .I1(s_axi_arready), .I2(\axlen_reg[7] [1]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair1101" *) LUT3 #( .INIT(8'hB8)) \axlen[2]_i_1__0 (.I0(s_axi_arlen[2]), .I1(s_axi_arready), .I2(\axlen_reg[7] [2]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair1089" *) LUT3 #( .INIT(8'hB8)) \axlen[3]_i_1__0 (.I0(s_axi_arlen[3]), .I1(s_axi_arready), .I2(\axlen_reg[7] [3]), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair1086" *) LUT3 #( .INIT(8'hB8)) \axlen[4]_i_1__0 (.I0(s_axi_arlen[4]), .I1(s_axi_arready), .I2(\axlen_reg[7] [4]), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair1088" *) LUT3 #( .INIT(8'hB8)) \axlen[5]_i_1__0 (.I0(s_axi_arlen[5]), .I1(s_axi_arready), .I2(\axlen_reg[7] [5]), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair1091" *) LUT3 #( .INIT(8'hB8)) \axlen[6]_i_1__0 (.I0(s_axi_arlen[6]), .I1(s_axi_arready), .I2(\axlen_reg[7] [6]), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair1090" *) LUT3 #( .INIT(8'hB8)) \axlen[7]_i_1__0 (.I0(s_axi_arlen[7]), .I1(s_axi_arready), .I2(\axlen_reg[7] [7]), .O(D[7])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1__1 (.I0(axready_reg_0), .I1(Q[0]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7] [0]), .I4(s_axi_arready), .I5(s_axi_arlen[0]), .O(\axlen_cnt_reg[7] [0])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1__2 (.I0(axready_reg_1), .I1(\axlen_cnt_reg[3]_0 [0]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7] [0]), .I4(s_axi_arready), .I5(s_axi_arlen[0]), .O(\axlen_cnt_reg[3] [0])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1__1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[1]), .I2(D[0]), .I3(Q[0]), .I4(axready_reg_0), .I5(D[1]), .O(\axlen_cnt_reg[7] [1])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1__2 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [1]), .I2(D[0]), .I3(\axlen_cnt_reg[3]_0 [0]), .I4(axready_reg_1), .I5(D[1]), .O(\axlen_cnt_reg[3] [1])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1__1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[2]), .I2(\axlen_cnt[2]_i_2__1_n_0 ), .I3(axready_reg_0), .I4(D[2]), .O(\axlen_cnt_reg[7] [2])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1__2 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axlen_cnt[2]_i_2__2_n_0 ), .I3(axready_reg_1), .I4(D[2]), .O(\axlen_cnt_reg[3] [2])); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2__1 (.I0(Q[0]), .I1(D[0]), .I2(Q[1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(D[1]), .O(\axlen_cnt[2]_i_2__1_n_0 )); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2__2 (.I0(\axlen_cnt_reg[3]_0 [0]), .I1(D[0]), .I2(\axlen_cnt_reg[3]_0 [1]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(D[1]), .O(\axlen_cnt[2]_i_2__2_n_0 )); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[3]_i_1__1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[3]), .I2(\axlen_cnt[3]_i_2__1_n_0 ), .I3(axready_reg_0), .I4(D[3]), .O(\axlen_cnt_reg[7] [3])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[3]_i_1__2 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [3]), .I2(\axlen_cnt[3]_i_2__2_n_0 ), .I3(axready_reg_1), .I4(D[3]), .O(\axlen_cnt_reg[3] [3])); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \axlen_cnt[3]_i_2__1 (.I0(\axlen_cnt[2]_i_2__1_n_0 ), .I1(Q[2]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7] [2]), .I4(s_axi_arready), .I5(s_axi_arlen[2]), .O(\axlen_cnt[3]_i_2__1_n_0 )); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \axlen_cnt[3]_i_2__2 (.I0(\axlen_cnt[2]_i_2__2_n_0 ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7] [2]), .I4(s_axi_arready), .I5(s_axi_arlen[2]), .O(\axlen_cnt[3]_i_2__2_n_0 )); LUT6 #( .INIT(64'hF606F6F6F6060606)) \axlen_cnt[4]_i_1__0 (.I0(\axlen_cnt[4]_i_2__0_n_0 ), .I1(\axlen_cnt[4]_i_3__0_n_0 ), .I2(axready_reg_0), .I3(s_axi_arlen[4]), .I4(s_axi_arready), .I5(\axlen_reg[7] [4]), .O(\axlen_cnt_reg[7] [4])); LUT6 #( .INIT(64'h0101015151510151)) \axlen_cnt[4]_i_2__0 (.I0(\axlen_cnt[3]_i_2__1_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7] [3]), .I4(s_axi_arready), .I5(s_axi_arlen[3]), .O(\axlen_cnt[4]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1086" *) LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[4]_i_3__0 (.I0(s_axi_arlen[4]), .I1(s_axi_arready), .I2(\axlen_reg[7] [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[4]), .O(\axlen_cnt[4]_i_3__0_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[5]_i_1__0 (.I0(\axlen_cnt[5]_i_2__0_n_0 ), .I1(\axlen_cnt[5]_i_3__0_n_0 ), .I2(axready_reg_0), .I3(s_axi_arlen[5]), .I4(s_axi_arready), .I5(\axlen_reg[7] [5]), .O(\axlen_cnt_reg[7] [5])); (* SOFT_HLUTNM = "soft_lutpair1088" *) LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[5]_i_2__0 (.I0(s_axi_arlen[5]), .I1(s_axi_arready), .I2(\axlen_reg[7] [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[5]), .O(\axlen_cnt[5]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFCFFFCAA)) \axlen_cnt[5]_i_3__0 (.I0(Q[4]), .I1(D[4]), .I2(D[3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[3]), .I5(\axlen_cnt[3]_i_2__1_n_0 ), .O(\axlen_cnt[5]_i_3__0_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[6]_i_1__0 (.I0(\axlen_cnt[7]_i_3__0_n_0 ), .I1(\axlen_cnt[7]_i_4__0_n_0 ), .I2(axready_reg_0), .I3(s_axi_arlen[6]), .I4(s_axi_arready), .I5(\axlen_reg[7] [6]), .O(\axlen_cnt_reg[7] [6])); (* SOFT_HLUTNM = "soft_lutpair1096" *) LUT5 #( .INIT(32'h0E000ECC)) \axlen_cnt[7]_i_1__0 (.I0(s_axi_arvalid), .I1(next), .I2(s_axi_arburst), .I3(s_axi_arready), .I4(axburst), .O(E)); LUT6 #( .INIT(64'hFFFFEEE10000444B)) \axlen_cnt[7]_i_2__0 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[7]), .I2(\axlen_cnt[7]_i_3__0_n_0 ), .I3(\axlen_cnt[7]_i_4__0_n_0 ), .I4(axready_reg_0), .I5(D[7]), .O(\axlen_cnt_reg[7] [7])); (* SOFT_HLUTNM = "soft_lutpair1091" *) LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[7]_i_3__0 (.I0(s_axi_arlen[6]), .I1(s_axi_arready), .I2(\axlen_reg[7] [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[6]), .O(\axlen_cnt[7]_i_3__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEAE)) \axlen_cnt[7]_i_4__0 (.I0(\axlen_cnt[3]_i_2__1_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(D[3]), .I4(\axlen_cnt[4]_i_3__0_n_0 ), .I5(\axlen_cnt[5]_i_2__0_n_0 ), .O(\axlen_cnt[7]_i_4__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1087" *) LUT5 #( .INIT(32'h888FFF8F)) axready_i_1__0 (.I0(next), .I1(r_rlast_reg), .I2(axvalid), .I3(s_axi_arready), .I4(s_axi_arvalid), .O(axready_i_1__0_n_0)); FDRE #( .INIT(1'b0)) axready_reg (.C(CLK), .CE(1'b1), .D(axready_i_1__0_n_0), .Q(s_axi_arready), .R(areset_d1)); (* SOFT_HLUTNM = "soft_lutpair1087" *) LUT3 #( .INIT(8'hB8)) axvalid_i_1__0 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(axvalid), .O(arvalid_int)); LUT6 #( .INIT(64'hF606F6F6F6060606)) \int_addr[0]_i_1__0 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I1(D[0]), .I2(axready_reg_1), .I3(s_axi_araddr[5]), .I4(s_axi_arready), .I5(\axaddr_reg[29]_0 [5]), .O(\int_addr_reg[3] [0])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[1]_i_1__0 (.I0(axready_reg_1), .I1(D[1]), .I2(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I3(\int_addr_reg[3]_0 [1]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [6]), .O(\int_addr_reg[3] [1])); LUT5 #( .INIT(32'hB8FFB800)) \int_addr[1]_i_2__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [0]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[2]_i_1__0 (.I0(axready_reg_1), .I1(D[2]), .I2(\int_addr[3]_i_5__0_n_0 ), .I3(\int_addr_reg[3]_0 [2]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [7]), .O(\int_addr_reg[3] [2])); (* SOFT_HLUTNM = "soft_lutpair1125" *) LUT3 #( .INIT(8'h80)) \int_addr[2]_i_2__0 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(s_axi_arburst), .O(\axi_mc_cmd_translator_0/wrap_axhandshake )); (* SOFT_HLUTNM = "soft_lutpair1096" *) LUT5 #( .INIT(32'hCFC08080)) \int_addr[3]_i_1__0 (.I0(s_axi_arvalid), .I1(s_axi_arburst), .I2(s_axi_arready), .I3(axburst), .I4(next), .O(\axlen_cnt_reg[0] )); LUT6 #( .INIT(64'h8BBBBBBBB8888888)) \int_addr[3]_i_2__0 (.I0(\axaddr_reg[29] [8]), .I1(axready_reg_1), .I2(D[3]), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I4(\int_addr[3]_i_5__0_n_0 ), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]), .O(\int_addr_reg[3] [3])); LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_4__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [2]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7])); LUT6 #( .INIT(64'hEEE222E200000000)) \int_addr[3]_i_5__0 (.I0(\int_addr_reg[3]_0 [1]), .I1(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I2(\axaddr_reg[29]_0 [6]), .I3(s_axi_arready), .I4(s_axi_araddr[6]), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .O(\int_addr[3]_i_5__0_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_6__0 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [3]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8])); LUT6 #( .INIT(64'h0010FFFF00100010)) r_rlast_i_1 (.I0(\axlen_cnt[2]_i_2__2_n_0 ), .I1(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2]), .I2(\axburst_reg[1] ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3]), .I4(\axlen_cnt[3]_i_2__1_n_0 ), .I5(r_rlast_i_4_n_0), .O(r_rlast_reg)); (* SOFT_HLUTNM = "soft_lutpair1101" *) LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_2 (.I0(s_axi_arlen[2]), .I1(s_axi_arready), .I2(\axlen_reg[7] [2]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\axlen_cnt_reg[3]_0 [2]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2])); LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_3 (.I0(s_axi_arlen[3]), .I1(s_axi_arready), .I2(\axlen_reg[7] [3]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\axlen_cnt_reg[3]_0 [3]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3])); LUT6 #( .INIT(64'h0000000000000001)) r_rlast_i_4 (.I0(r_rlast_i_5_n_0), .I1(\axlen_cnt[7]_i_3__0_n_0 ), .I2(\axlen_cnt[4]_i_3__0_n_0 ), .I3(\axlen_cnt[5]_i_2__0_n_0 ), .I4(\axburst_reg[1] ), .I5(r_rlast_i_6_n_0), .O(r_rlast_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair1090" *) LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_5 (.I0(s_axi_arlen[7]), .I1(s_axi_arready), .I2(\axlen_reg[7] [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[7]), .O(r_rlast_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair1089" *) LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_6 (.I0(s_axi_arlen[3]), .I1(s_axi_arready), .I2(\axlen_reg[7] [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[3]), .O(r_rlast_i_6_n_0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_cmd_translator" *) module ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator (out, Q, \app_addr_r1_reg[27] , \int_addr_reg[3] , \axlen_cnt_reg[3] , in0, axready_reg, S, axready_reg_0, areset_d1, E, D, CLK, axready_reg_1, axready_reg_2, axready_reg_3, \axlen_cnt_reg[3]_0 ); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; output [3:0]\int_addr_reg[3] ; output [3:0]\axlen_cnt_reg[3] ; input [3:0]in0; input [24:0]axready_reg; input [0:0]S; input [0:0]axready_reg_0; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_1; input [0:0]axready_reg_2; input [3:0]axready_reg_3; input [3:0]\axlen_cnt_reg[3]_0 ; wire CLK; wire [7:0]D; wire [0:0]E; wire [7:0]Q; wire [0:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire areset_d1; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [24:0]axready_reg; wire [0:0]axready_reg_0; wire [29:0]axready_reg_1; wire [0:0]axready_reg_2; wire [3:0]axready_reg_3; wire [3:0]in0; wire [3:0]\int_addr_reg[3] ; wire [29:0]out; ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd axi_mc_incr_cmd_0 (.CLK(CLK), .D(D), .E(E), .Q(Q), .S(S), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .areset_d1(areset_d1), .axready_reg(axready_reg), .axready_reg_0(axready_reg_0), .axready_reg_1(axready_reg_1), .in0(in0), .out(out)); ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd axi_mc_wrap_cmd_0 (.CLK(CLK), .areset_d1(areset_d1), .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ), .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_0 ), .axready_reg(axready_reg_2), .axready_reg_0(axready_reg_3), .\int_addr_reg[3]_0 (\int_addr_reg[3] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_cmd_translator" *) module ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator__parameterized0 (out, Q, \app_addr_r1_reg[27] , \app_addr_r1_reg[6] , \axlen_cnt_reg[3] , in0, DI, S, axready_reg, areset_d1, E, D, CLK, axready_reg_0, axready_reg_1, axready_reg_2, \axlen_cnt_reg[3]_0 ); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; output [3:0]\app_addr_r1_reg[6] ; output [3:0]\axlen_cnt_reg[3] ; input [3:0]in0; input [0:0]DI; input [3:0]S; input [21:0]axready_reg; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_0; input [0:0]axready_reg_1; input [3:0]axready_reg_2; input [3:0]\axlen_cnt_reg[3]_0 ; wire CLK; wire [7:0]D; wire [0:0]DI; wire [0:0]E; wire [7:0]Q; wire [3:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire [3:0]\app_addr_r1_reg[6] ; wire areset_d1; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [21:0]axready_reg; wire [29:0]axready_reg_0; wire [0:0]axready_reg_1; wire [3:0]axready_reg_2; wire [3:0]in0; wire [29:0]out; ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd__parameterized0 axi_mc_incr_cmd_0 (.CLK(CLK), .D(D), .DI(DI), .E(E), .Q(Q), .S(S), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .areset_d1(areset_d1), .axready_reg(axready_reg), .axready_reg_0(axready_reg_0), .in0(in0), .out(out)); ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd__parameterized0 axi_mc_wrap_cmd_0 (.CLK(CLK), .\app_addr_r1_reg[6] (\app_addr_r1_reg[6] ), .areset_d1(areset_d1), .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ), .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_0 ), .axready_reg(axready_reg_1), .axready_reg_0(axready_reg_2)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_fifo" *) module ddr3_ifmig_7series_v4_0_axi_mc_fifo (bid_i, app_en_ns1, wr_cmd_en, E, bhandshake, bvalid_i_reg, b_push, b_awid, CLK, app_rdy, \RD_PRI_REG_STARVE.rnw_i_reg , rd_cmd_en, reset_reg, app_en_r1, bvalid_i_reg_0, s_axi_bready, wvalid_int, awvalid_int, app_wdf_rdy, areset_d1); output bid_i; output app_en_ns1; output wr_cmd_en; output [0:0]E; output bhandshake; output bvalid_i_reg; input b_push; input b_awid; input CLK; input app_rdy; input \RD_PRI_REG_STARVE.rnw_i_reg ; input rd_cmd_en; input reset_reg; input app_en_r1; input bvalid_i_reg_0; input s_axi_bready; input wvalid_int; input awvalid_int; input app_wdf_rdy; input areset_d1; wire CLK; wire [0:0]E; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire app_en_ns1; wire app_en_r1; wire app_rdy; wire app_wdf_rdy; wire areset_d1; wire awvalid_int; wire b_awid; wire b_push; wire bhandshake; wire bid_i; wire bvalid_i_reg; wire bvalid_i_reg_0; wire \cnt_read[0]_i_1__1_n_0 ; wire \cnt_read[1]_i_1_n_0 ; wire \cnt_read[2]_i_1__0_n_0 ; wire \cnt_read[3]_i_1__0_n_0 ; wire \cnt_read[3]_i_2_n_0 ; wire \cnt_read[3]_i_3_n_0 ; wire [2:0]cnt_read_reg__0; wire [3:3]cnt_read_reg__0__0; wire rd_cmd_en; wire reset_reg; wire s_axi_bready; wire wr_cmd_en; wire wvalid_int; LUT6 #( .INIT(64'h8080808080008080)) \RD_PRI_REG_STARVE.rnw_i_i_2 (.I0(wvalid_int), .I1(awvalid_int), .I2(app_wdf_rdy), .I3(\cnt_read[3]_i_3_n_0 ), .I4(cnt_read_reg__0[0]), .I5(cnt_read_reg__0__0), .O(wr_cmd_en)); LUT4 #( .INIT(16'hA808)) \app_addr_r1[27]_i_1 (.I0(app_rdy), .I1(wr_cmd_en), .I2(\RD_PRI_REG_STARVE.rnw_i_reg ), .I3(rd_cmd_en), .O(E)); LUT6 #( .INIT(64'h0000FD5D0000A808)) app_en_r1_i_1 (.I0(app_rdy), .I1(wr_cmd_en), .I2(\RD_PRI_REG_STARVE.rnw_i_reg ), .I3(rd_cmd_en), .I4(reset_reg), .I5(app_en_r1), .O(app_en_ns1)); LUT2 #( .INIT(4'hB)) \bid_t[0]_i_1 (.I0(s_axi_bready), .I1(bvalid_i_reg_0), .O(bhandshake)); LUT6 #( .INIT(64'h7FFFFFFF7FFF7FFF)) bvalid_i_i_1 (.I0(cnt_read_reg__0__0), .I1(cnt_read_reg__0[1]), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[0]), .I4(s_axi_bready), .I5(bvalid_i_reg_0), .O(bvalid_i_reg)); LUT1 #( .INIT(2'h1)) \cnt_read[0]_i_1__1 (.I0(cnt_read_reg__0[0]), .O(\cnt_read[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'h52D2D2D22D2D2D2D)) \cnt_read[1]_i_1 (.I0(b_push), .I1(bhandshake), .I2(cnt_read_reg__0[0]), .I3(cnt_read_reg__0[2]), .I4(cnt_read_reg__0__0), .I5(cnt_read_reg__0[1]), .O(\cnt_read[1]_i_1_n_0 )); LUT6 #( .INIT(64'h4FFFFF30300000CF)) \cnt_read[2]_i_1__0 (.I0(cnt_read_reg__0__0), .I1(bhandshake), .I2(b_push), .I3(cnt_read_reg__0[0]), .I4(cnt_read_reg__0[1]), .I5(cnt_read_reg__0[2]), .O(\cnt_read[2]_i_1__0_n_0 )); LUT6 #( .INIT(64'h5959AA5959595959)) \cnt_read[3]_i_1__0 (.I0(b_push), .I1(bvalid_i_reg_0), .I2(s_axi_bready), .I3(cnt_read_reg__0[0]), .I4(\cnt_read[3]_i_3_n_0 ), .I5(cnt_read_reg__0__0), .O(\cnt_read[3]_i_1__0_n_0 )); LUT6 #( .INIT(64'h5FFF2000FFBA0045)) \cnt_read[3]_i_2 (.I0(cnt_read_reg__0[1]), .I1(bhandshake), .I2(b_push), .I3(cnt_read_reg__0[0]), .I4(cnt_read_reg__0__0), .I5(cnt_read_reg__0[2]), .O(\cnt_read[3]_i_2_n_0 )); LUT2 #( .INIT(4'h7)) \cnt_read[3]_i_3 (.I0(cnt_read_reg__0[1]), .I1(cnt_read_reg__0[2]), .O(\cnt_read[3]_i_3_n_0 )); FDSE #( .INIT(1'b1)) \cnt_read_reg[0] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[0]_i_1__1_n_0 ), .Q(cnt_read_reg__0[0]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[1] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[1]_i_1_n_0 ), .Q(cnt_read_reg__0[1]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[2] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[2]_i_1__0_n_0 ), .Q(cnt_read_reg__0[2]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[3] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[3]_i_2_n_0 ), .Q(cnt_read_reg__0__0), .S(areset_d1)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7][0]_srl8 " *) SRL16E #( .INIT(16'h0000)) \memory_reg[7][0]_srl8 (.A0(cnt_read_reg__0[0]), .A1(cnt_read_reg__0[1]), .A2(cnt_read_reg__0[2]), .A3(1'b0), .CE(b_push), .CLK(CLK), .D(b_awid), .Q(bid_i)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_fifo" *) module ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized0 (rd_cmd_en, E, s_axi_rvalid, p_0_in, \FSM_sequential_state_reg[1] , \FSM_sequential_state_reg[0] , \s_axi_rresp[1] , s_axi_arvalid, s_axi_arready, axvalid, \cnt_read_reg[5]_0 , app_rdy, \trans_buf_out_r_reg[0] , app_rd_data_valid, s_axi_rready, out, tr_empty, in0, Q, CLK, areset_d1); output rd_cmd_en; output [0:0]E; output s_axi_rvalid; output p_0_in; output \FSM_sequential_state_reg[1] ; output \FSM_sequential_state_reg[0] ; output [256:0]\s_axi_rresp[1] ; input s_axi_arvalid; input s_axi_arready; input axvalid; input \cnt_read_reg[5]_0 ; input app_rdy; input \trans_buf_out_r_reg[0] ; input app_rd_data_valid; input s_axi_rready; input [1:0]out; input tr_empty; input [1:0]in0; input [255:0]Q; input CLK; input areset_d1; wire CLK; wire [0:0]E; wire \FSM_sequential_state_reg[0] ; wire \FSM_sequential_state_reg[1] ; wire [255:0]Q; wire app_rd_data_valid; wire app_rdy; wire areset_d1; wire axvalid; wire \cnt_read[0]_i_1_n_0 ; wire \cnt_read[0]_rep_i_1_n_0 ; wire \cnt_read[1]_i_1__0_n_0 ; wire \cnt_read[1]_rep_i_1_n_0 ; wire \cnt_read[2]_i_1__1_n_0 ; wire \cnt_read[2]_rep_i_1_n_0 ; wire \cnt_read[3]_i_1__1_n_0 ; wire \cnt_read[3]_rep_i_1_n_0 ; wire \cnt_read[4]_i_1__0_n_0 ; wire \cnt_read[4]_rep_i_1_n_0 ; wire \cnt_read[5]_i_1_n_0 ; wire \cnt_read[5]_i_2__0_n_0 ; wire \cnt_read[5]_i_3_n_0 ; wire \cnt_read_reg[0]_rep_n_0 ; wire \cnt_read_reg[1]_rep_n_0 ; wire \cnt_read_reg[2]_rep_n_0 ; wire \cnt_read_reg[3]_rep_n_0 ; wire \cnt_read_reg[4]_rep_n_0 ; wire \cnt_read_reg[5]_0 ; wire [5:5]cnt_read_reg__0; wire [4:0]cnt_read_reg__1; wire [1:0]in0; wire [1:0]out; wire p_0_in; wire r_push_i_4_n_0; wire rd_cmd_en; wire rvalid04_in; wire s_axi_arready; wire s_axi_arvalid; wire s_axi_rready; wire [256:0]\s_axi_rresp[1] ; wire s_axi_rvalid; wire tr_empty; wire \trans_buf_out_r_reg[0] ; wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ; LUT5 #( .INIT(32'hF7FD4045)) \FSM_sequential_state[0]_i_1 (.I0(out[0]), .I1(p_0_in), .I2(out[1]), .I3(tr_empty), .I4(in0[0]), .O(\FSM_sequential_state_reg[0] )); LUT5 #( .INIT(32'hB7BA0002)) \FSM_sequential_state[1]_i_1 (.I0(out[0]), .I1(p_0_in), .I2(out[1]), .I3(tr_empty), .I4(in0[1]), .O(\FSM_sequential_state_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1161" *) LUT3 #( .INIT(8'hC8)) \FSM_sequential_state[1]_i_2 (.I0(\trans_buf_out_r_reg[0] ), .I1(rvalid04_in), .I2(s_axi_rready), .O(p_0_in)); LUT2 #( .INIT(4'h8)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_2 (.I0(rd_cmd_en), .I1(app_rdy), .O(E)); LUT1 #( .INIT(2'h1)) \cnt_read[0]_i_1 (.I0(cnt_read_reg__1[0]), .O(\cnt_read[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_read[0]_rep_i_1 (.I0(cnt_read_reg__1[0]), .O(\cnt_read[0]_rep_i_1_n_0 )); LUT6 #( .INIT(64'hAAA6666655599999)) \cnt_read[1]_i_1__0 (.I0(cnt_read_reg__1[0]), .I1(app_rd_data_valid), .I2(s_axi_rready), .I3(\trans_buf_out_r_reg[0] ), .I4(rvalid04_in), .I5(cnt_read_reg__1[1]), .O(\cnt_read[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hAAA6666655599999)) \cnt_read[1]_rep_i_1 (.I0(cnt_read_reg__1[0]), .I1(app_rd_data_valid), .I2(s_axi_rready), .I3(\trans_buf_out_r_reg[0] ), .I4(rvalid04_in), .I5(cnt_read_reg__1[1]), .O(\cnt_read[1]_rep_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1160" *) LUT3 #( .INIT(8'h69)) \cnt_read[2]_i_1__1 (.I0(\cnt_read[5]_i_3_n_0 ), .I1(cnt_read_reg__1[2]), .I2(cnt_read_reg__1[1]), .O(\cnt_read[2]_i_1__1_n_0 )); LUT3 #( .INIT(8'h69)) \cnt_read[2]_rep_i_1 (.I0(\cnt_read[5]_i_3_n_0 ), .I1(cnt_read_reg__1[2]), .I2(cnt_read_reg__1[1]), .O(\cnt_read[2]_rep_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1160" *) LUT4 #( .INIT(16'h78E1)) \cnt_read[3]_i_1__1 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[3]), .I3(cnt_read_reg__1[2]), .O(\cnt_read[3]_i_1__1_n_0 )); LUT4 #( .INIT(16'h78E1)) \cnt_read[3]_rep_i_1 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[3]), .I3(cnt_read_reg__1[2]), .O(\cnt_read[3]_rep_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1159" *) LUT5 #( .INIT(32'h7F80FE01)) \cnt_read[4]_i_1__0 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[2]), .I3(cnt_read_reg__1[4]), .I4(cnt_read_reg__1[3]), .O(\cnt_read[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7F80FE01)) \cnt_read[4]_rep_i_1 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[2]), .I3(cnt_read_reg__1[4]), .I4(cnt_read_reg__1[3]), .O(\cnt_read[4]_rep_i_1_n_0 )); LUT4 #( .INIT(16'h56AA)) \cnt_read[5]_i_1 (.I0(app_rd_data_valid), .I1(s_axi_rready), .I2(\trans_buf_out_r_reg[0] ), .I3(rvalid04_in), .O(\cnt_read[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \cnt_read[5]_i_2__0 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[2]), .I3(cnt_read_reg__1[3]), .I4(cnt_read_reg__0), .I5(cnt_read_reg__1[4]), .O(\cnt_read[5]_i_2__0_n_0 )); LUT6 #( .INIT(64'h00088888AAAEEEEE)) \cnt_read[5]_i_3 (.I0(cnt_read_reg__1[0]), .I1(app_rd_data_valid), .I2(s_axi_rready), .I3(\trans_buf_out_r_reg[0] ), .I4(rvalid04_in), .I5(cnt_read_reg__1[1]), .O(\cnt_read[5]_i_3_n_0 )); (* ORIG_CELL_NAME = "cnt_read_reg[0]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[0] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[0]_i_1_n_0 ), .Q(cnt_read_reg__1[0]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[0]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[0]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[0]_rep_i_1_n_0 ), .Q(\cnt_read_reg[0]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[1]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[1] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[1]_i_1__0_n_0 ), .Q(cnt_read_reg__1[1]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[1]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[1]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[1]_rep_i_1_n_0 ), .Q(\cnt_read_reg[1]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[2]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[2] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[2]_i_1__1_n_0 ), .Q(cnt_read_reg__1[2]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[2]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[2]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[2]_rep_i_1_n_0 ), .Q(\cnt_read_reg[2]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[3]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[3] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[3]_i_1__1_n_0 ), .Q(cnt_read_reg__1[3]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[3]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[3]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[3]_rep_i_1_n_0 ), .Q(\cnt_read_reg[3]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[4]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[4] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[4]_i_1__0_n_0 ), .Q(cnt_read_reg__1[4]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[4]" *) FDSE #( .INIT(1'b1)) \cnt_read_reg[4]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[4]_rep_i_1_n_0 ), .Q(\cnt_read_reg[4]_rep_n_0 ), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[5] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[5]_i_2__0_n_0 ), .Q(cnt_read_reg__0), .S(areset_d1)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][0]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[0]), .Q(\s_axi_rresp[1] [0]), .Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][100]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][100]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[100]), .Q(\s_axi_rresp[1] [100]), .Q31(\NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][101]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][101]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[101]), .Q(\s_axi_rresp[1] [101]), .Q31(\NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][102]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][102]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[102]), .Q(\s_axi_rresp[1] [102]), .Q31(\NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][103]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][103]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[103]), .Q(\s_axi_rresp[1] [103]), .Q31(\NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][104]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][104]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[104]), .Q(\s_axi_rresp[1] [104]), .Q31(\NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][105]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][105]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[105]), .Q(\s_axi_rresp[1] [105]), .Q31(\NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][106]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][106]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[106]), .Q(\s_axi_rresp[1] [106]), .Q31(\NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][107]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][107]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[107]), .Q(\s_axi_rresp[1] [107]), .Q31(\NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][108]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][108]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[108]), .Q(\s_axi_rresp[1] [108]), .Q31(\NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][109]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][109]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[109]), .Q(\s_axi_rresp[1] [109]), .Q31(\NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][10]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[10]), .Q(\s_axi_rresp[1] [10]), .Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][110]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][110]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[110]), .Q(\s_axi_rresp[1] [110]), .Q31(\NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][111]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][111]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[111]), .Q(\s_axi_rresp[1] [111]), .Q31(\NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][112]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][112]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[112]), .Q(\s_axi_rresp[1] [112]), .Q31(\NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][113]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][113]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[113]), .Q(\s_axi_rresp[1] [113]), .Q31(\NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][114]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][114]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[114]), .Q(\s_axi_rresp[1] [114]), .Q31(\NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][115]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][115]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[115]), .Q(\s_axi_rresp[1] [115]), .Q31(\NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][116]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][116]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[116]), .Q(\s_axi_rresp[1] [116]), .Q31(\NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][117]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][117]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[117]), .Q(\s_axi_rresp[1] [117]), .Q31(\NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][118]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][118]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[118]), .Q(\s_axi_rresp[1] [118]), .Q31(\NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][119]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][119]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[119]), .Q(\s_axi_rresp[1] [119]), .Q31(\NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][11]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[11]), .Q(\s_axi_rresp[1] [11]), .Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][120]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][120]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[120]), .Q(\s_axi_rresp[1] [120]), .Q31(\NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][121]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][121]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[121]), .Q(\s_axi_rresp[1] [121]), .Q31(\NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][122]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][122]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[122]), .Q(\s_axi_rresp[1] [122]), .Q31(\NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][123]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][123]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[123]), .Q(\s_axi_rresp[1] [123]), .Q31(\NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][124]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][124]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[124]), .Q(\s_axi_rresp[1] [124]), .Q31(\NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][125]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][125]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[125]), .Q(\s_axi_rresp[1] [125]), .Q31(\NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][126]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][126]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[126]), .Q(\s_axi_rresp[1] [126]), .Q31(\NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][127]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][127]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[127]), .Q(\s_axi_rresp[1] [127]), .Q31(\NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][128]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][128]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[128]), .Q(\s_axi_rresp[1] [128]), .Q31(\NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][129]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][129]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[129]), .Q(\s_axi_rresp[1] [129]), .Q31(\NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][12]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[12]), .Q(\s_axi_rresp[1] [12]), .Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][130]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][130]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[130]), .Q(\s_axi_rresp[1] [130]), .Q31(\NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][131]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][131]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[131]), .Q(\s_axi_rresp[1] [131]), .Q31(\NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][132]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][132]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[132]), .Q(\s_axi_rresp[1] [132]), .Q31(\NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][133]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][133]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[133]), .Q(\s_axi_rresp[1] [133]), .Q31(\NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][134]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][134]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[134]), .Q(\s_axi_rresp[1] [134]), .Q31(\NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][135]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][135]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[135]), .Q(\s_axi_rresp[1] [135]), .Q31(\NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][136]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][136]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[136]), .Q(\s_axi_rresp[1] [136]), .Q31(\NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][137]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][137]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[137]), .Q(\s_axi_rresp[1] [137]), .Q31(\NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][138]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][138]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[138]), .Q(\s_axi_rresp[1] [138]), .Q31(\NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][139]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][139]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[139]), .Q(\s_axi_rresp[1] [139]), .Q31(\NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][13]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[13]), .Q(\s_axi_rresp[1] [13]), .Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][140]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][140]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[140]), .Q(\s_axi_rresp[1] [140]), .Q31(\NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][141]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][141]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[141]), .Q(\s_axi_rresp[1] [141]), .Q31(\NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][142]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][142]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[142]), .Q(\s_axi_rresp[1] [142]), .Q31(\NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][143]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][143]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[143]), .Q(\s_axi_rresp[1] [143]), .Q31(\NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][144]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][144]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[144]), .Q(\s_axi_rresp[1] [144]), .Q31(\NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][145]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][145]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[145]), .Q(\s_axi_rresp[1] [145]), .Q31(\NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][146]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][146]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[146]), .Q(\s_axi_rresp[1] [146]), .Q31(\NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][147]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][147]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[147]), .Q(\s_axi_rresp[1] [147]), .Q31(\NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][148]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][148]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[148]), .Q(\s_axi_rresp[1] [148]), .Q31(\NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][149]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][149]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[149]), .Q(\s_axi_rresp[1] [149]), .Q31(\NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][14]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[14]), .Q(\s_axi_rresp[1] [14]), .Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][150]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][150]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[150]), .Q(\s_axi_rresp[1] [150]), .Q31(\NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][151]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][151]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[151]), .Q(\s_axi_rresp[1] [151]), .Q31(\NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][152]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][152]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[152]), .Q(\s_axi_rresp[1] [152]), .Q31(\NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][153]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][153]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[153]), .Q(\s_axi_rresp[1] [153]), .Q31(\NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][154]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][154]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[154]), .Q(\s_axi_rresp[1] [154]), .Q31(\NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][155]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][155]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[155]), .Q(\s_axi_rresp[1] [155]), .Q31(\NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][156]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][156]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[156]), .Q(\s_axi_rresp[1] [156]), .Q31(\NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][157]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][157]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[157]), .Q(\s_axi_rresp[1] [157]), .Q31(\NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][158]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][158]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[158]), .Q(\s_axi_rresp[1] [158]), .Q31(\NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][159]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][159]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[159]), .Q(\s_axi_rresp[1] [159]), .Q31(\NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][15]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[15]), .Q(\s_axi_rresp[1] [15]), .Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][160]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][160]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[160]), .Q(\s_axi_rresp[1] [160]), .Q31(\NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][161]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][161]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[161]), .Q(\s_axi_rresp[1] [161]), .Q31(\NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][162]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][162]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[162]), .Q(\s_axi_rresp[1] [162]), .Q31(\NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][163]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][163]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[163]), .Q(\s_axi_rresp[1] [163]), .Q31(\NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][164]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][164]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[164]), .Q(\s_axi_rresp[1] [164]), .Q31(\NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][165]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][165]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[165]), .Q(\s_axi_rresp[1] [165]), .Q31(\NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][166]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][166]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[166]), .Q(\s_axi_rresp[1] [166]), .Q31(\NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][167]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][167]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[167]), .Q(\s_axi_rresp[1] [167]), .Q31(\NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][168]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][168]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[168]), .Q(\s_axi_rresp[1] [168]), .Q31(\NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][169]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][169]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[169]), .Q(\s_axi_rresp[1] [169]), .Q31(\NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][16]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[16]), .Q(\s_axi_rresp[1] [16]), .Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][170]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][170]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[170]), .Q(\s_axi_rresp[1] [170]), .Q31(\NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][171]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][171]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[171]), .Q(\s_axi_rresp[1] [171]), .Q31(\NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][172]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][172]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[172]), .Q(\s_axi_rresp[1] [172]), .Q31(\NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][173]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][173]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[173]), .Q(\s_axi_rresp[1] [173]), .Q31(\NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][174]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][174]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[174]), .Q(\s_axi_rresp[1] [174]), .Q31(\NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][175]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][175]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[175]), .Q(\s_axi_rresp[1] [175]), .Q31(\NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][176]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][176]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[176]), .Q(\s_axi_rresp[1] [176]), .Q31(\NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][177]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][177]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[177]), .Q(\s_axi_rresp[1] [177]), .Q31(\NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][178]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][178]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[178]), .Q(\s_axi_rresp[1] [178]), .Q31(\NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][179]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][179]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[179]), .Q(\s_axi_rresp[1] [179]), .Q31(\NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][17]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[17]), .Q(\s_axi_rresp[1] [17]), .Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][180]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][180]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[180]), .Q(\s_axi_rresp[1] [180]), .Q31(\NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][181]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][181]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[181]), .Q(\s_axi_rresp[1] [181]), .Q31(\NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][182]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][182]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[182]), .Q(\s_axi_rresp[1] [182]), .Q31(\NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][183]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][183]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[183]), .Q(\s_axi_rresp[1] [183]), .Q31(\NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][184]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][184]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[184]), .Q(\s_axi_rresp[1] [184]), .Q31(\NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][185]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][185]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[185]), .Q(\s_axi_rresp[1] [185]), .Q31(\NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][186]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][186]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[186]), .Q(\s_axi_rresp[1] [186]), .Q31(\NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][187]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][187]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[187]), .Q(\s_axi_rresp[1] [187]), .Q31(\NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][188]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][188]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[188]), .Q(\s_axi_rresp[1] [188]), .Q31(\NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][189]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][189]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[189]), .Q(\s_axi_rresp[1] [189]), .Q31(\NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][18]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[18]), .Q(\s_axi_rresp[1] [18]), .Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][190]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][190]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[190]), .Q(\s_axi_rresp[1] [190]), .Q31(\NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][191]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][191]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[191]), .Q(\s_axi_rresp[1] [191]), .Q31(\NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][192]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][192]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[192]), .Q(\s_axi_rresp[1] [192]), .Q31(\NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][193]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][193]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[193]), .Q(\s_axi_rresp[1] [193]), .Q31(\NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][194]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][194]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[194]), .Q(\s_axi_rresp[1] [194]), .Q31(\NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][195]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][195]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[195]), .Q(\s_axi_rresp[1] [195]), .Q31(\NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][196]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][196]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[196]), .Q(\s_axi_rresp[1] [196]), .Q31(\NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][197]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][197]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[197]), .Q(\s_axi_rresp[1] [197]), .Q31(\NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][198]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][198]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[198]), .Q(\s_axi_rresp[1] [198]), .Q31(\NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][199]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][199]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[199]), .Q(\s_axi_rresp[1] [199]), .Q31(\NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][19]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[19]), .Q(\s_axi_rresp[1] [19]), .Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][1]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[1]), .Q(\s_axi_rresp[1] [1]), .Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][200]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][200]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[200]), .Q(\s_axi_rresp[1] [200]), .Q31(\NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][201]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][201]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[201]), .Q(\s_axi_rresp[1] [201]), .Q31(\NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][202]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][202]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[202]), .Q(\s_axi_rresp[1] [202]), .Q31(\NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][203]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][203]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[203]), .Q(\s_axi_rresp[1] [203]), .Q31(\NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][204]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][204]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[204]), .Q(\s_axi_rresp[1] [204]), .Q31(\NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][205]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][205]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[205]), .Q(\s_axi_rresp[1] [205]), .Q31(\NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][206]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][206]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[206]), .Q(\s_axi_rresp[1] [206]), .Q31(\NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][207]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][207]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[207]), .Q(\s_axi_rresp[1] [207]), .Q31(\NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][208]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][208]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[208]), .Q(\s_axi_rresp[1] [208]), .Q31(\NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][209]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][209]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[209]), .Q(\s_axi_rresp[1] [209]), .Q31(\NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][20]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[20]), .Q(\s_axi_rresp[1] [20]), .Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][210]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][210]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[210]), .Q(\s_axi_rresp[1] [210]), .Q31(\NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][211]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][211]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[211]), .Q(\s_axi_rresp[1] [211]), .Q31(\NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][212]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][212]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[212]), .Q(\s_axi_rresp[1] [212]), .Q31(\NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][213]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][213]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[213]), .Q(\s_axi_rresp[1] [213]), .Q31(\NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][214]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][214]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[214]), .Q(\s_axi_rresp[1] [214]), .Q31(\NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][215]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][215]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[215]), .Q(\s_axi_rresp[1] [215]), .Q31(\NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][216]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][216]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[216]), .Q(\s_axi_rresp[1] [216]), .Q31(\NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][217]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][217]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[217]), .Q(\s_axi_rresp[1] [217]), .Q31(\NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][218]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][218]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[218]), .Q(\s_axi_rresp[1] [218]), .Q31(\NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][219]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][219]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[219]), .Q(\s_axi_rresp[1] [219]), .Q31(\NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][21]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[21]), .Q(\s_axi_rresp[1] [21]), .Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][220]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][220]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[220]), .Q(\s_axi_rresp[1] [220]), .Q31(\NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][221]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][221]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[221]), .Q(\s_axi_rresp[1] [221]), .Q31(\NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][222]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][222]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[222]), .Q(\s_axi_rresp[1] [222]), .Q31(\NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][223]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][223]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[223]), .Q(\s_axi_rresp[1] [223]), .Q31(\NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][224]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][224]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[224]), .Q(\s_axi_rresp[1] [224]), .Q31(\NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][225]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][225]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[225]), .Q(\s_axi_rresp[1] [225]), .Q31(\NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][226]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][226]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[226]), .Q(\s_axi_rresp[1] [226]), .Q31(\NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][227]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][227]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[227]), .Q(\s_axi_rresp[1] [227]), .Q31(\NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][228]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][228]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[228]), .Q(\s_axi_rresp[1] [228]), .Q31(\NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][229]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][229]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[229]), .Q(\s_axi_rresp[1] [229]), .Q31(\NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][22]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[22]), .Q(\s_axi_rresp[1] [22]), .Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][230]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][230]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[230]), .Q(\s_axi_rresp[1] [230]), .Q31(\NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][231]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][231]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[231]), .Q(\s_axi_rresp[1] [231]), .Q31(\NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][232]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][232]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[232]), .Q(\s_axi_rresp[1] [232]), .Q31(\NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][233]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][233]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[233]), .Q(\s_axi_rresp[1] [233]), .Q31(\NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][234]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][234]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[234]), .Q(\s_axi_rresp[1] [234]), .Q31(\NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][235]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][235]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[235]), .Q(\s_axi_rresp[1] [235]), .Q31(\NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][236]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][236]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[236]), .Q(\s_axi_rresp[1] [236]), .Q31(\NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][237]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][237]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[237]), .Q(\s_axi_rresp[1] [237]), .Q31(\NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][238]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][238]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[238]), .Q(\s_axi_rresp[1] [238]), .Q31(\NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][239]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][239]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[239]), .Q(\s_axi_rresp[1] [239]), .Q31(\NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][23]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[23]), .Q(\s_axi_rresp[1] [23]), .Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][240]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][240]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[240]), .Q(\s_axi_rresp[1] [240]), .Q31(\NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][241]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][241]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[241]), .Q(\s_axi_rresp[1] [241]), .Q31(\NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][242]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][242]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[242]), .Q(\s_axi_rresp[1] [242]), .Q31(\NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][243]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][243]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[243]), .Q(\s_axi_rresp[1] [243]), .Q31(\NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][244]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][244]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[244]), .Q(\s_axi_rresp[1] [244]), .Q31(\NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][245]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][245]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[245]), .Q(\s_axi_rresp[1] [245]), .Q31(\NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][246]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][246]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[246]), .Q(\s_axi_rresp[1] [246]), .Q31(\NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][247]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][247]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[247]), .Q(\s_axi_rresp[1] [247]), .Q31(\NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][248]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][248]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[248]), .Q(\s_axi_rresp[1] [248]), .Q31(\NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][249]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][249]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[249]), .Q(\s_axi_rresp[1] [249]), .Q31(\NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][24]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[24]), .Q(\s_axi_rresp[1] [24]), .Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][250]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][250]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[250]), .Q(\s_axi_rresp[1] [250]), .Q31(\NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][251]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][251]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[251]), .Q(\s_axi_rresp[1] [251]), .Q31(\NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][252]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][252]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[252]), .Q(\s_axi_rresp[1] [252]), .Q31(\NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][253]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][253]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[253]), .Q(\s_axi_rresp[1] [253]), .Q31(\NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][254]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][254]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[254]), .Q(\s_axi_rresp[1] [254]), .Q31(\NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][255]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][255]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[255]), .Q(\s_axi_rresp[1] [255]), .Q31(\NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][256]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][256]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(1'b0), .Q(\s_axi_rresp[1] [256]), .Q31(\NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][25]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[25]), .Q(\s_axi_rresp[1] [25]), .Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][26]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[26]), .Q(\s_axi_rresp[1] [26]), .Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][27]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[27]), .Q(\s_axi_rresp[1] [27]), .Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][28]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[28]), .Q(\s_axi_rresp[1] [28]), .Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][29]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[29]), .Q(\s_axi_rresp[1] [29]), .Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][2]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[2]), .Q(\s_axi_rresp[1] [2]), .Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][30]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[30]), .Q(\s_axi_rresp[1] [30]), .Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][31]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[31]), .Q(\s_axi_rresp[1] [31]), .Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][32]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[32]), .Q(\s_axi_rresp[1] [32]), .Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][33]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[33]), .Q(\s_axi_rresp[1] [33]), .Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][34]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][34]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[34]), .Q(\s_axi_rresp[1] [34]), .Q31(\NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][35]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][35]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[35]), .Q(\s_axi_rresp[1] [35]), .Q31(\NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][36]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][36]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[36]), .Q(\s_axi_rresp[1] [36]), .Q31(\NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][37]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][37]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[37]), .Q(\s_axi_rresp[1] [37]), .Q31(\NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][38]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][38]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[38]), .Q(\s_axi_rresp[1] [38]), .Q31(\NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][39]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][39]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[39]), .Q(\s_axi_rresp[1] [39]), .Q31(\NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][3]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[3]), .Q(\s_axi_rresp[1] [3]), .Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][40]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][40]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[40]), .Q(\s_axi_rresp[1] [40]), .Q31(\NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][41]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][41]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[41]), .Q(\s_axi_rresp[1] [41]), .Q31(\NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][42]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][42]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[42]), .Q(\s_axi_rresp[1] [42]), .Q31(\NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][43]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][43]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[43]), .Q(\s_axi_rresp[1] [43]), .Q31(\NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][44]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][44]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[44]), .Q(\s_axi_rresp[1] [44]), .Q31(\NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][45]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][45]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[45]), .Q(\s_axi_rresp[1] [45]), .Q31(\NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][46]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][46]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[46]), .Q(\s_axi_rresp[1] [46]), .Q31(\NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][47]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][47]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[47]), .Q(\s_axi_rresp[1] [47]), .Q31(\NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][48]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][48]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[48]), .Q(\s_axi_rresp[1] [48]), .Q31(\NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][49]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][49]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[49]), .Q(\s_axi_rresp[1] [49]), .Q31(\NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][4]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[4]), .Q(\s_axi_rresp[1] [4]), .Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][50]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][50]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[50]), .Q(\s_axi_rresp[1] [50]), .Q31(\NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][51]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][51]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[51]), .Q(\s_axi_rresp[1] [51]), .Q31(\NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][52]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][52]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[52]), .Q(\s_axi_rresp[1] [52]), .Q31(\NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][53]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][53]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[53]), .Q(\s_axi_rresp[1] [53]), .Q31(\NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][54]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][54]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[54]), .Q(\s_axi_rresp[1] [54]), .Q31(\NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][55]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][55]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[55]), .Q(\s_axi_rresp[1] [55]), .Q31(\NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][56]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][56]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[56]), .Q(\s_axi_rresp[1] [56]), .Q31(\NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][57]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][57]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[57]), .Q(\s_axi_rresp[1] [57]), .Q31(\NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][58]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][58]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[58]), .Q(\s_axi_rresp[1] [58]), .Q31(\NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][59]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][59]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[59]), .Q(\s_axi_rresp[1] [59]), .Q31(\NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][5]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[5]), .Q(\s_axi_rresp[1] [5]), .Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][60]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][60]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[60]), .Q(\s_axi_rresp[1] [60]), .Q31(\NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][61]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][61]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[61]), .Q(\s_axi_rresp[1] [61]), .Q31(\NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][62]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][62]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[62]), .Q(\s_axi_rresp[1] [62]), .Q31(\NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][63]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][63]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[63]), .Q(\s_axi_rresp[1] [63]), .Q31(\NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][64]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][64]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[64]), .Q(\s_axi_rresp[1] [64]), .Q31(\NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][65]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][65]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[65]), .Q(\s_axi_rresp[1] [65]), .Q31(\NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][66]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][66]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[66]), .Q(\s_axi_rresp[1] [66]), .Q31(\NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][67]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][67]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[67]), .Q(\s_axi_rresp[1] [67]), .Q31(\NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][68]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][68]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[68]), .Q(\s_axi_rresp[1] [68]), .Q31(\NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][69]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][69]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[69]), .Q(\s_axi_rresp[1] [69]), .Q31(\NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][6]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[6]), .Q(\s_axi_rresp[1] [6]), .Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][70]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][70]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[70]), .Q(\s_axi_rresp[1] [70]), .Q31(\NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][71]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][71]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[71]), .Q(\s_axi_rresp[1] [71]), .Q31(\NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][72]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][72]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[72]), .Q(\s_axi_rresp[1] [72]), .Q31(\NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][73]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][73]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[73]), .Q(\s_axi_rresp[1] [73]), .Q31(\NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][74]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][74]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[74]), .Q(\s_axi_rresp[1] [74]), .Q31(\NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][75]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][75]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[75]), .Q(\s_axi_rresp[1] [75]), .Q31(\NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][76]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][76]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[76]), .Q(\s_axi_rresp[1] [76]), .Q31(\NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][77]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][77]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[77]), .Q(\s_axi_rresp[1] [77]), .Q31(\NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][78]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][78]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[78]), .Q(\s_axi_rresp[1] [78]), .Q31(\NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][79]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][79]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[79]), .Q(\s_axi_rresp[1] [79]), .Q31(\NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][7]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[7]), .Q(\s_axi_rresp[1] [7]), .Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][80]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][80]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[80]), .Q(\s_axi_rresp[1] [80]), .Q31(\NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][81]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][81]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[81]), .Q(\s_axi_rresp[1] [81]), .Q31(\NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][82]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][82]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[82]), .Q(\s_axi_rresp[1] [82]), .Q31(\NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][83]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][83]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[83]), .Q(\s_axi_rresp[1] [83]), .Q31(\NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][84]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][84]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[84]), .Q(\s_axi_rresp[1] [84]), .Q31(\NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][85]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[85]), .Q(\s_axi_rresp[1] [85]), .Q31(\NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][86]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][86]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[86]), .Q(\s_axi_rresp[1] [86]), .Q31(\NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][87]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][87]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[87]), .Q(\s_axi_rresp[1] [87]), .Q31(\NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][88]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][88]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[88]), .Q(\s_axi_rresp[1] [88]), .Q31(\NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][89]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][89]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[89]), .Q(\s_axi_rresp[1] [89]), .Q31(\NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][8]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[8]), .Q(\s_axi_rresp[1] [8]), .Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][90]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][90]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[90]), .Q(\s_axi_rresp[1] [90]), .Q31(\NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][91]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][91]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[91]), .Q(\s_axi_rresp[1] [91]), .Q31(\NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][92]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][92]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[92]), .Q(\s_axi_rresp[1] [92]), .Q31(\NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][93]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][93]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[93]), .Q(\s_axi_rresp[1] [93]), .Q31(\NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][94]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][94]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[94]), .Q(\s_axi_rresp[1] [94]), .Q31(\NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][95]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][95]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[95]), .Q(\s_axi_rresp[1] [95]), .Q31(\NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][96]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][96]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[96]), .Q(\s_axi_rresp[1] [96]), .Q31(\NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][97]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][97]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[97]), .Q(\s_axi_rresp[1] [97]), .Q31(\NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][98]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][98]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[98]), .Q(\s_axi_rresp[1] [98]), .Q31(\NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][99]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][99]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[99]), .Q(\s_axi_rresp[1] [99]), .Q31(\NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][9]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[9]), .Q(\s_axi_rresp[1] [9]), .Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED )); LUT6 #( .INIT(64'h00B8000000B800B8)) r_push_i_2 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(axvalid), .I3(\cnt_read_reg[5]_0 ), .I4(cnt_read_reg__0), .I5(r_push_i_4_n_0), .O(rd_cmd_en)); (* SOFT_HLUTNM = "soft_lutpair1159" *) LUT4 #( .INIT(16'h8000)) r_push_i_4 (.I0(cnt_read_reg__1[2]), .I1(cnt_read_reg__1[1]), .I2(cnt_read_reg__1[4]), .I3(cnt_read_reg__1[3]), .O(r_push_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair1161" *) LUT2 #( .INIT(4'h2)) s_axi_rvalid_INST_0 (.I0(rvalid04_in), .I1(\trans_buf_out_r_reg[0] ), .O(s_axi_rvalid)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) s_axi_rvalid_INST_0_i_1 (.I0(cnt_read_reg__1[2]), .I1(cnt_read_reg__1[1]), .I2(cnt_read_reg__1[4]), .I3(cnt_read_reg__1[3]), .I4(cnt_read_reg__0), .I5(cnt_read_reg__1[0]), .O(rvalid04_in)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_fifo" *) module ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized1 (E, tr_empty, \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] , \trans_buf_out_r_reg[0] , \trans_buf_out_r1_reg[3] , \trans_buf_out_r_reg[2] , \trans_buf_out_r_reg[3] , out, p_0_in, r_push, Q, \trans_buf_out_r_reg[0]_0 , assert_rlast, s_axi_rid, CLK, in, areset_d1); output [0:0]E; output tr_empty; output \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ; output \trans_buf_out_r_reg[0] ; output [2:0]\trans_buf_out_r1_reg[3] ; output \trans_buf_out_r_reg[2] ; output \trans_buf_out_r_reg[3] ; input [1:0]out; input p_0_in; input r_push; input [2:0]Q; input \trans_buf_out_r_reg[0]_0 ; input assert_rlast; input [0:0]s_axi_rid; input CLK; input [1:0]in; input areset_d1; wire CLK; wire [0:0]E; wire [2:0]Q; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ; wire areset_d1; wire assert_rlast; wire \cnt_read[0]_i_1__0_n_0 ; wire \cnt_read[1]_i_1__1_n_0 ; wire \cnt_read[2]_i_1_n_0 ; wire \cnt_read[3]_i_1_n_0 ; wire \cnt_read[4]_i_1_n_0 ; wire \cnt_read[5]_i_1__0_n_0 ; wire \cnt_read[5]_i_2_n_0 ; wire \cnt_read[5]_i_3__0_n_0 ; wire [4:0]cnt_read_reg__0; wire [5:5]cnt_read_reg__0__0; wire [1:0]in; wire load_stage1; wire [1:0]out; wire p_0_in; wire r_push; wire [0:0]s_axi_rid; wire tr_empty; wire [2:0]\trans_buf_out_r1_reg[3] ; wire \trans_buf_out_r_reg[0] ; wire \trans_buf_out_r_reg[0]_0 ; wire \trans_buf_out_r_reg[2] ; wire \trans_buf_out_r_reg[3] ; wire \NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED ; wire \NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED ; wire \NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED ; LUT6 #( .INIT(64'h8000000000000000)) \FSM_sequential_state[1]_i_3 (.I0(cnt_read_reg__0[0]), .I1(cnt_read_reg__0[1]), .I2(cnt_read_reg__0__0), .I3(cnt_read_reg__0[2]), .I4(cnt_read_reg__0[3]), .I5(cnt_read_reg__0[4]), .O(tr_empty)); LUT1 #( .INIT(2'h1)) \cnt_read[0]_i_1__0 (.I0(cnt_read_reg__0[0]), .O(\cnt_read[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1162" *) LUT5 #( .INIT(32'h56AAA955)) \cnt_read[1]_i_1__1 (.I0(cnt_read_reg__0[0]), .I1(tr_empty), .I2(out[1]), .I3(r_push), .I4(cnt_read_reg__0[1]), .O(\cnt_read[1]_i_1__1_n_0 )); LUT3 #( .INIT(8'h69)) \cnt_read[2]_i_1 (.I0(\cnt_read[5]_i_3__0_n_0 ), .I1(cnt_read_reg__0[2]), .I2(cnt_read_reg__0[1]), .O(\cnt_read[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1163" *) LUT4 #( .INIT(16'h78E1)) \cnt_read[3]_i_1 (.I0(cnt_read_reg__0[1]), .I1(\cnt_read[5]_i_3__0_n_0 ), .I2(cnt_read_reg__0[3]), .I3(cnt_read_reg__0[2]), .O(\cnt_read[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1163" *) LUT5 #( .INIT(32'h7F80FE01)) \cnt_read[4]_i_1 (.I0(cnt_read_reg__0[1]), .I1(\cnt_read[5]_i_3__0_n_0 ), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[4]), .I4(cnt_read_reg__0[3]), .O(\cnt_read[4]_i_1_n_0 )); LUT3 #( .INIT(8'hE1)) \cnt_read[5]_i_1__0 (.I0(tr_empty), .I1(out[1]), .I2(r_push), .O(\cnt_read[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \cnt_read[5]_i_2 (.I0(cnt_read_reg__0[1]), .I1(\cnt_read[5]_i_3__0_n_0 ), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[3]), .I4(cnt_read_reg__0__0), .I5(cnt_read_reg__0[4]), .O(\cnt_read[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1162" *) LUT5 #( .INIT(32'hA800FEAA)) \cnt_read[5]_i_3__0 (.I0(cnt_read_reg__0[0]), .I1(tr_empty), .I2(out[1]), .I3(r_push), .I4(cnt_read_reg__0[1]), .O(\cnt_read[5]_i_3__0_n_0 )); FDSE #( .INIT(1'b1)) \cnt_read_reg[0] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[0]_i_1__0_n_0 ), .Q(cnt_read_reg__0[0]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[1] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[1]_i_1__1_n_0 ), .Q(cnt_read_reg__0[1]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[2] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[2]_i_1_n_0 ), .Q(cnt_read_reg__0[2]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[3] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[3]_i_1_n_0 ), .Q(cnt_read_reg__0[3]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[4] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[4]_i_1_n_0 ), .Q(cnt_read_reg__0[4]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \cnt_read_reg[5] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[5]_i_2_n_0 ), .Q(cnt_read_reg__0__0), .S(areset_d1)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][0]_srl30 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[29][0]_srl30 (.A(cnt_read_reg__0), .CE(r_push), .CLK(CLK), .D(1'b0), .Q(\trans_buf_out_r1_reg[3] [0]), .Q31(\NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][2]_srl30 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[29][2]_srl30 (.A(cnt_read_reg__0), .CE(r_push), .CLK(CLK), .D(in[0]), .Q(\trans_buf_out_r1_reg[3] [1]), .Q31(\NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][3]_srl30 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[29][3]_srl30 (.A(cnt_read_reg__0), .CE(r_push), .CLK(CLK), .D(in[1]), .Q(\trans_buf_out_r1_reg[3] [2]), .Q31(\NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED )); LUT5 #( .INIT(32'h10000000)) r_push_i_3 (.I0(cnt_read_reg__0__0), .I1(cnt_read_reg__0[1]), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[3]), .I4(cnt_read_reg__0[4]), .O(\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair1164" *) LUT2 #( .INIT(4'h1)) \trans_buf_out_r1[3]_i_1 (.I0(out[1]), .I1(tr_empty), .O(E)); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \trans_buf_out_r[0]_i_1 (.I0(Q[0]), .I1(out[1]), .I2(out[0]), .I3(\trans_buf_out_r1_reg[3] [0]), .I4(load_stage1), .I5(\trans_buf_out_r_reg[0]_0 ), .O(\trans_buf_out_r_reg[0] )); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \trans_buf_out_r[2]_i_1 (.I0(Q[1]), .I1(out[1]), .I2(out[0]), .I3(\trans_buf_out_r1_reg[3] [1]), .I4(load_stage1), .I5(assert_rlast), .O(\trans_buf_out_r_reg[2] )); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \trans_buf_out_r[3]_i_1 (.I0(Q[2]), .I1(out[1]), .I2(out[0]), .I3(\trans_buf_out_r1_reg[3] [2]), .I4(load_stage1), .I5(s_axi_rid), .O(\trans_buf_out_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair1164" *) LUT4 #( .INIT(16'h1D01)) \trans_buf_out_r[3]_i_2 (.I0(tr_empty), .I1(out[1]), .I2(out[0]), .I3(p_0_in), .O(load_stage1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_incr_cmd" *) module ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd (out, Q, \app_addr_r1_reg[27] , in0, axready_reg, S, axready_reg_0, areset_d1, E, D, CLK, axready_reg_1); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; input [3:0]in0; input [24:0]axready_reg; input [0:0]S; input [0:0]axready_reg_0; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_1; wire CLK; wire [7:0]D; wire [0:0]E; wire [7:0]Q; wire [0:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire areset_d1; (* RTL_KEEP = "true" *) wire [29:0]axaddr_incr_p; wire axaddr_incr_p_reg0_carry__0_n_0; wire axaddr_incr_p_reg0_carry__0_n_1; wire axaddr_incr_p_reg0_carry__0_n_2; wire axaddr_incr_p_reg0_carry__0_n_3; wire axaddr_incr_p_reg0_carry__1_n_0; wire axaddr_incr_p_reg0_carry__1_n_1; wire axaddr_incr_p_reg0_carry__1_n_2; wire axaddr_incr_p_reg0_carry__1_n_3; wire axaddr_incr_p_reg0_carry__2_n_0; wire axaddr_incr_p_reg0_carry__2_n_1; wire axaddr_incr_p_reg0_carry__2_n_2; wire axaddr_incr_p_reg0_carry__2_n_3; wire axaddr_incr_p_reg0_carry__3_n_0; wire axaddr_incr_p_reg0_carry__3_n_1; wire axaddr_incr_p_reg0_carry__3_n_2; wire axaddr_incr_p_reg0_carry__3_n_3; wire axaddr_incr_p_reg0_carry__4_n_0; wire axaddr_incr_p_reg0_carry__4_n_1; wire axaddr_incr_p_reg0_carry__4_n_2; wire axaddr_incr_p_reg0_carry__4_n_3; wire axaddr_incr_p_reg0_carry__5_n_3; wire axaddr_incr_p_reg0_carry_n_0; wire axaddr_incr_p_reg0_carry_n_1; wire axaddr_incr_p_reg0_carry_n_2; wire axaddr_incr_p_reg0_carry_n_3; wire [24:0]axready_reg; wire [0:0]axready_reg_0; wire [29:0]axready_reg_1; wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED; wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED; assign axaddr_incr_p[3:0] = in0[3:0]; assign out[29:0] = axaddr_incr_p; CARRY4 axaddr_incr_p_reg0_carry (.CI(1'b0), .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,axready_reg[1],1'b0}), .O(axaddr_incr_p[7:4]), .S({axready_reg[3:2],S,axready_reg[0]})); CARRY4 axaddr_incr_p_reg0_carry__0 (.CI(axaddr_incr_p_reg0_carry_n_0), .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[11:8]), .S({axready_reg[6:4],axready_reg_0})); CARRY4 axaddr_incr_p_reg0_carry__1 (.CI(axaddr_incr_p_reg0_carry__0_n_0), .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[15:12]), .S(axready_reg[10:7])); CARRY4 axaddr_incr_p_reg0_carry__2 (.CI(axaddr_incr_p_reg0_carry__1_n_0), .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[19:16]), .S(axready_reg[14:11])); CARRY4 axaddr_incr_p_reg0_carry__3 (.CI(axaddr_incr_p_reg0_carry__2_n_0), .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[23:20]), .S(axready_reg[18:15])); CARRY4 axaddr_incr_p_reg0_carry__4 (.CI(axaddr_incr_p_reg0_carry__3_n_0), .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[27:24]), .S(axready_reg[22:19])); CARRY4 axaddr_incr_p_reg0_carry__5 (.CI(axaddr_incr_p_reg0_carry__4_n_0), .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}), .S({1'b0,1'b0,axready_reg[24:23]})); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[0] (.C(CLK), .CE(E), .D(axready_reg_1[0]), .Q(\app_addr_r1_reg[27] [0]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[10] (.C(CLK), .CE(E), .D(axready_reg_1[10]), .Q(\app_addr_r1_reg[27] [10]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[11] (.C(CLK), .CE(E), .D(axready_reg_1[11]), .Q(\app_addr_r1_reg[27] [11]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[12] (.C(CLK), .CE(E), .D(axready_reg_1[12]), .Q(\app_addr_r1_reg[27] [12]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[13] (.C(CLK), .CE(E), .D(axready_reg_1[13]), .Q(\app_addr_r1_reg[27] [13]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[14] (.C(CLK), .CE(E), .D(axready_reg_1[14]), .Q(\app_addr_r1_reg[27] [14]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[15] (.C(CLK), .CE(E), .D(axready_reg_1[15]), .Q(\app_addr_r1_reg[27] [15]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[16] (.C(CLK), .CE(E), .D(axready_reg_1[16]), .Q(\app_addr_r1_reg[27] [16]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[17] (.C(CLK), .CE(E), .D(axready_reg_1[17]), .Q(\app_addr_r1_reg[27] [17]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[18] (.C(CLK), .CE(E), .D(axready_reg_1[18]), .Q(\app_addr_r1_reg[27] [18]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[19] (.C(CLK), .CE(E), .D(axready_reg_1[19]), .Q(\app_addr_r1_reg[27] [19]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[1] (.C(CLK), .CE(E), .D(axready_reg_1[1]), .Q(\app_addr_r1_reg[27] [1]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[20] (.C(CLK), .CE(E), .D(axready_reg_1[20]), .Q(\app_addr_r1_reg[27] [20]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[21] (.C(CLK), .CE(E), .D(axready_reg_1[21]), .Q(\app_addr_r1_reg[27] [21]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[22] (.C(CLK), .CE(E), .D(axready_reg_1[22]), .Q(\app_addr_r1_reg[27] [22]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[23] (.C(CLK), .CE(E), .D(axready_reg_1[23]), .Q(\app_addr_r1_reg[27] [23]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[24] (.C(CLK), .CE(E), .D(axready_reg_1[24]), .Q(\app_addr_r1_reg[27] [24]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[25] (.C(CLK), .CE(E), .D(axready_reg_1[25]), .Q(\app_addr_r1_reg[27] [25]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[26] (.C(CLK), .CE(E), .D(axready_reg_1[26]), .Q(\app_addr_r1_reg[27] [26]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[27] (.C(CLK), .CE(E), .D(axready_reg_1[27]), .Q(\app_addr_r1_reg[27] [27]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[28] (.C(CLK), .CE(E), .D(axready_reg_1[28]), .Q(\app_addr_r1_reg[27] [28]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[29] (.C(CLK), .CE(E), .D(axready_reg_1[29]), .Q(\app_addr_r1_reg[27] [29]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[2] (.C(CLK), .CE(E), .D(axready_reg_1[2]), .Q(\app_addr_r1_reg[27] [2]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[3] (.C(CLK), .CE(E), .D(axready_reg_1[3]), .Q(\app_addr_r1_reg[27] [3]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[4] (.C(CLK), .CE(E), .D(axready_reg_1[4]), .Q(\app_addr_r1_reg[27] [4]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[5] (.C(CLK), .CE(E), .D(axready_reg_1[5]), .Q(\app_addr_r1_reg[27] [5]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[6] (.C(CLK), .CE(E), .D(axready_reg_1[6]), .Q(\app_addr_r1_reg[27] [6]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[7] (.C(CLK), .CE(E), .D(axready_reg_1[7]), .Q(\app_addr_r1_reg[27] [7]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[8] (.C(CLK), .CE(E), .D(axready_reg_1[8]), .Q(\app_addr_r1_reg[27] [8]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[9] (.C(CLK), .CE(E), .D(axready_reg_1[9]), .Q(\app_addr_r1_reg[27] [9]), .R(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[0] (.C(CLK), .CE(E), .D(D[0]), .Q(Q[0]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[1] (.C(CLK), .CE(E), .D(D[1]), .Q(Q[1]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[2] (.C(CLK), .CE(E), .D(D[2]), .Q(Q[2]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[3] (.C(CLK), .CE(E), .D(D[3]), .Q(Q[3]), .S(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[4] (.C(CLK), .CE(E), .D(D[4]), .Q(Q[4]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[5] (.C(CLK), .CE(E), .D(D[5]), .Q(Q[5]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[6] (.C(CLK), .CE(E), .D(D[6]), .Q(Q[6]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[7] (.C(CLK), .CE(E), .D(D[7]), .Q(Q[7]), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_incr_cmd" *) module ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd__parameterized0 (out, Q, \app_addr_r1_reg[27] , in0, DI, S, axready_reg, areset_d1, E, D, CLK, axready_reg_0); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; input [3:0]in0; input [0:0]DI; input [3:0]S; input [21:0]axready_reg; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_0; wire CLK; wire [7:0]D; wire [0:0]DI; wire [0:0]E; wire [7:0]Q; wire [3:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire areset_d1; (* RTL_KEEP = "true" *) wire [29:0]axaddr_incr_p; wire axaddr_incr_p_reg0_carry__0_n_0; wire axaddr_incr_p_reg0_carry__0_n_1; wire axaddr_incr_p_reg0_carry__0_n_2; wire axaddr_incr_p_reg0_carry__0_n_3; wire axaddr_incr_p_reg0_carry__1_n_0; wire axaddr_incr_p_reg0_carry__1_n_1; wire axaddr_incr_p_reg0_carry__1_n_2; wire axaddr_incr_p_reg0_carry__1_n_3; wire axaddr_incr_p_reg0_carry__2_n_0; wire axaddr_incr_p_reg0_carry__2_n_1; wire axaddr_incr_p_reg0_carry__2_n_2; wire axaddr_incr_p_reg0_carry__2_n_3; wire axaddr_incr_p_reg0_carry__3_n_0; wire axaddr_incr_p_reg0_carry__3_n_1; wire axaddr_incr_p_reg0_carry__3_n_2; wire axaddr_incr_p_reg0_carry__3_n_3; wire axaddr_incr_p_reg0_carry__4_n_0; wire axaddr_incr_p_reg0_carry__4_n_1; wire axaddr_incr_p_reg0_carry__4_n_2; wire axaddr_incr_p_reg0_carry__4_n_3; wire axaddr_incr_p_reg0_carry__5_n_3; wire axaddr_incr_p_reg0_carry_n_0; wire axaddr_incr_p_reg0_carry_n_1; wire axaddr_incr_p_reg0_carry_n_2; wire axaddr_incr_p_reg0_carry_n_3; wire [21:0]axready_reg; wire [29:0]axready_reg_0; wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED; wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED; assign axaddr_incr_p[3:0] = in0[3:0]; assign out[29:0] = axaddr_incr_p; CARRY4 axaddr_incr_p_reg0_carry (.CI(1'b0), .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,DI,1'b0}), .O(axaddr_incr_p[7:4]), .S(S)); CARRY4 axaddr_incr_p_reg0_carry__0 (.CI(axaddr_incr_p_reg0_carry_n_0), .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[11:8]), .S(axready_reg[3:0])); CARRY4 axaddr_incr_p_reg0_carry__1 (.CI(axaddr_incr_p_reg0_carry__0_n_0), .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[15:12]), .S(axready_reg[7:4])); CARRY4 axaddr_incr_p_reg0_carry__2 (.CI(axaddr_incr_p_reg0_carry__1_n_0), .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[19:16]), .S(axready_reg[11:8])); CARRY4 axaddr_incr_p_reg0_carry__3 (.CI(axaddr_incr_p_reg0_carry__2_n_0), .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[23:20]), .S(axready_reg[15:12])); CARRY4 axaddr_incr_p_reg0_carry__4 (.CI(axaddr_incr_p_reg0_carry__3_n_0), .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[27:24]), .S(axready_reg[19:16])); CARRY4 axaddr_incr_p_reg0_carry__5 (.CI(axaddr_incr_p_reg0_carry__4_n_0), .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}), .S({1'b0,1'b0,axready_reg[21:20]})); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[0] (.C(CLK), .CE(E), .D(axready_reg_0[0]), .Q(\app_addr_r1_reg[27] [0]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[10] (.C(CLK), .CE(E), .D(axready_reg_0[10]), .Q(\app_addr_r1_reg[27] [10]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[11] (.C(CLK), .CE(E), .D(axready_reg_0[11]), .Q(\app_addr_r1_reg[27] [11]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[12] (.C(CLK), .CE(E), .D(axready_reg_0[12]), .Q(\app_addr_r1_reg[27] [12]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[13] (.C(CLK), .CE(E), .D(axready_reg_0[13]), .Q(\app_addr_r1_reg[27] [13]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[14] (.C(CLK), .CE(E), .D(axready_reg_0[14]), .Q(\app_addr_r1_reg[27] [14]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[15] (.C(CLK), .CE(E), .D(axready_reg_0[15]), .Q(\app_addr_r1_reg[27] [15]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[16] (.C(CLK), .CE(E), .D(axready_reg_0[16]), .Q(\app_addr_r1_reg[27] [16]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[17] (.C(CLK), .CE(E), .D(axready_reg_0[17]), .Q(\app_addr_r1_reg[27] [17]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[18] (.C(CLK), .CE(E), .D(axready_reg_0[18]), .Q(\app_addr_r1_reg[27] [18]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[19] (.C(CLK), .CE(E), .D(axready_reg_0[19]), .Q(\app_addr_r1_reg[27] [19]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[1] (.C(CLK), .CE(E), .D(axready_reg_0[1]), .Q(\app_addr_r1_reg[27] [1]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[20] (.C(CLK), .CE(E), .D(axready_reg_0[20]), .Q(\app_addr_r1_reg[27] [20]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[21] (.C(CLK), .CE(E), .D(axready_reg_0[21]), .Q(\app_addr_r1_reg[27] [21]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[22] (.C(CLK), .CE(E), .D(axready_reg_0[22]), .Q(\app_addr_r1_reg[27] [22]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[23] (.C(CLK), .CE(E), .D(axready_reg_0[23]), .Q(\app_addr_r1_reg[27] [23]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[24] (.C(CLK), .CE(E), .D(axready_reg_0[24]), .Q(\app_addr_r1_reg[27] [24]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[25] (.C(CLK), .CE(E), .D(axready_reg_0[25]), .Q(\app_addr_r1_reg[27] [25]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[26] (.C(CLK), .CE(E), .D(axready_reg_0[26]), .Q(\app_addr_r1_reg[27] [26]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[27] (.C(CLK), .CE(E), .D(axready_reg_0[27]), .Q(\app_addr_r1_reg[27] [27]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[28] (.C(CLK), .CE(E), .D(axready_reg_0[28]), .Q(\app_addr_r1_reg[27] [28]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[29] (.C(CLK), .CE(E), .D(axready_reg_0[29]), .Q(\app_addr_r1_reg[27] [29]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[2] (.C(CLK), .CE(E), .D(axready_reg_0[2]), .Q(\app_addr_r1_reg[27] [2]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[3] (.C(CLK), .CE(E), .D(axready_reg_0[3]), .Q(\app_addr_r1_reg[27] [3]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[4] (.C(CLK), .CE(E), .D(axready_reg_0[4]), .Q(\app_addr_r1_reg[27] [4]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[5] (.C(CLK), .CE(E), .D(axready_reg_0[5]), .Q(\app_addr_r1_reg[27] [5]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[6] (.C(CLK), .CE(E), .D(axready_reg_0[6]), .Q(\app_addr_r1_reg[27] [6]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[7] (.C(CLK), .CE(E), .D(axready_reg_0[7]), .Q(\app_addr_r1_reg[27] [7]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[8] (.C(CLK), .CE(E), .D(axready_reg_0[8]), .Q(\app_addr_r1_reg[27] [8]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axaddr_incr_reg[9] (.C(CLK), .CE(E), .D(axready_reg_0[9]), .Q(\app_addr_r1_reg[27] [9]), .R(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[0] (.C(CLK), .CE(E), .D(D[0]), .Q(Q[0]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[1] (.C(CLK), .CE(E), .D(D[1]), .Q(Q[1]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[2] (.C(CLK), .CE(E), .D(D[2]), .Q(Q[2]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[3] (.C(CLK), .CE(E), .D(D[3]), .Q(Q[3]), .S(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[4] (.C(CLK), .CE(E), .D(D[4]), .Q(Q[4]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[5] (.C(CLK), .CE(E), .D(D[5]), .Q(Q[5]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[6] (.C(CLK), .CE(E), .D(D[6]), .Q(Q[6]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \axlen_cnt_reg[7] (.C(CLK), .CE(E), .D(D[7]), .Q(Q[7]), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_r_channel" *) module ddr3_ifmig_7series_v4_0_axi_mc_r_channel (rd_cmd_en, E, s_axi_rvalid, s_axi_rlast, out, s_axi_rid, s_axi_arvalid, s_axi_arready, axvalid, app_rdy, app_rd_data_valid, s_axi_rready, r_push, Q, CLK, in, areset_d1); output rd_cmd_en; output [0:0]E; output s_axi_rvalid; output s_axi_rlast; output [256:0]out; output [0:0]s_axi_rid; input s_axi_arvalid; input s_axi_arready; input axvalid; input app_rdy; input app_rd_data_valid; input s_axi_rready; input r_push; input [255:0]Q; input CLK; input [1:0]in; input areset_d1; wire CLK; wire [0:0]E; wire [255:0]Q; wire app_rd_data_valid; wire app_rdy; wire areset_d1; wire assert_rlast; wire axvalid; wire [1:0]in; wire [256:0]out; wire p_0_in; wire r_push; wire rd_cmd_en; wire rd_data_fifo_0_n_4; wire rd_data_fifo_0_n_5; wire s_axi_arready; wire s_axi_arvalid; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; (* RTL_KEEP = "yes" *) wire [1:0]state; wire tr_empty; wire [3:0]trans_buf_out_r1; wire \trans_buf_out_r_reg_n_0_[0] ; wire [3:0]trans_out; wire transaction_fifo_0_n_0; wire transaction_fifo_0_n_2; wire transaction_fifo_0_n_3; wire transaction_fifo_0_n_7; wire transaction_fifo_0_n_8; (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_state_reg[0] (.C(CLK), .CE(1'b1), .D(rd_data_fifo_0_n_5), .Q(state[0]), .R(areset_d1)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_state_reg[1] (.C(CLK), .CE(1'b1), .D(rd_data_fifo_0_n_4), .Q(state[1]), .R(areset_d1)); ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized0 rd_data_fifo_0 (.CLK(CLK), .E(E), .\FSM_sequential_state_reg[0] (rd_data_fifo_0_n_5), .\FSM_sequential_state_reg[1] (rd_data_fifo_0_n_4), .Q(Q), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .areset_d1(areset_d1), .axvalid(axvalid), .\cnt_read_reg[5]_0 (transaction_fifo_0_n_2), .in0(state), .out(state), .p_0_in(p_0_in), .rd_cmd_en(rd_cmd_en), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_rready(s_axi_rready), .\s_axi_rresp[1] (out), .s_axi_rvalid(s_axi_rvalid), .tr_empty(tr_empty), .\trans_buf_out_r_reg[0] (\trans_buf_out_r_reg_n_0_[0] )); LUT2 #( .INIT(4'h2)) s_axi_rlast_INST_0 (.I0(assert_rlast), .I1(\trans_buf_out_r_reg_n_0_[0] ), .O(s_axi_rlast)); FDRE #( .INIT(1'b0)) \trans_buf_out_r1_reg[0] (.C(CLK), .CE(transaction_fifo_0_n_0), .D(trans_out[0]), .Q(trans_buf_out_r1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \trans_buf_out_r1_reg[2] (.C(CLK), .CE(transaction_fifo_0_n_0), .D(trans_out[2]), .Q(trans_buf_out_r1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \trans_buf_out_r1_reg[3] (.C(CLK), .CE(transaction_fifo_0_n_0), .D(trans_out[3]), .Q(trans_buf_out_r1[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \trans_buf_out_r_reg[0] (.C(CLK), .CE(1'b1), .D(transaction_fifo_0_n_3), .Q(\trans_buf_out_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \trans_buf_out_r_reg[2] (.C(CLK), .CE(1'b1), .D(transaction_fifo_0_n_7), .Q(assert_rlast), .R(1'b0)); FDRE #( .INIT(1'b0)) \trans_buf_out_r_reg[3] (.C(CLK), .CE(1'b1), .D(transaction_fifo_0_n_8), .Q(s_axi_rid), .R(1'b0)); ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized1 transaction_fifo_0 (.CLK(CLK), .E(transaction_fifo_0_n_0), .Q({trans_buf_out_r1[3:2],trans_buf_out_r1[0]}), .\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] (transaction_fifo_0_n_2), .areset_d1(areset_d1), .assert_rlast(assert_rlast), .in(in), .out(state), .p_0_in(p_0_in), .r_push(r_push), .s_axi_rid(s_axi_rid), .tr_empty(tr_empty), .\trans_buf_out_r1_reg[3] ({trans_out[3:2],trans_out[0]}), .\trans_buf_out_r_reg[0] (transaction_fifo_0_n_3), .\trans_buf_out_r_reg[0]_0 (\trans_buf_out_r_reg_n_0_[0] ), .\trans_buf_out_r_reg[2] (transaction_fifo_0_n_7), .\trans_buf_out_r_reg[3] (transaction_fifo_0_n_8)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_w_channel" *) module ddr3_ifmig_7series_v4_0_axi_mc_w_channel (wvalid_int, s_axi_wready, mc_app_wdf_wren_reg, app_wdf_mask, mc_app_wdf_mask_reg, D, app_wdf_data, mc_app_wdf_data_reg, \mc_app_wdf_data_reg_reg[255]_0 , areset_d1, CLK, app_wdf_rdy, \RD_PRI_REG_STARVE.rnw_i_reg , s_axi_wvalid, s_axi_wstrb, s_axi_wdata); output wvalid_int; output s_axi_wready; output mc_app_wdf_wren_reg; output [31:0]app_wdf_mask; output [31:0]mc_app_wdf_mask_reg; output [31:0]D; output [255:0]app_wdf_data; output [255:0]mc_app_wdf_data_reg; output [255:0]\mc_app_wdf_data_reg_reg[255]_0 ; input areset_d1; input CLK; input app_wdf_rdy; input \RD_PRI_REG_STARVE.rnw_i_reg ; input s_axi_wvalid; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; wire CLK; wire [31:0]D; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire areset_d1; wire [255:0]mc_app_wdf_data_reg; wire [255:0]\mc_app_wdf_data_reg_reg[255]_0 ; wire [31:0]mc_app_wdf_mask_reg; wire mc_app_wdf_wren_reg; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire valid; wire [255:0]wdf_data; wire [31:0]wdf_mask; wire wready_i_1_n_0; wire wready_reg_rep__0_n_0; wire wready_reg_rep__1_n_0; wire wready_reg_rep__2_n_0; wire wready_reg_rep_n_0; wire wready_rep__0_i_1_n_0; wire wready_rep__1_i_1_n_0; wire wready_rep__2_i_1_n_0; wire wready_rep_i_1_n_0; wire wvalid_int; (* SOFT_HLUTNM = "soft_lutpair1452" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[0]_i_1 (.I0(s_axi_wdata[0]), .I1(s_axi_wready), .I2(wdf_data[0]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[0]), .O(app_wdf_data[0])); (* SOFT_HLUTNM = "soft_lutpair1264" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[100]_i_1 (.I0(s_axi_wdata[100]), .I1(wready_reg_rep_n_0), .I2(wdf_data[100]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[100]), .O(app_wdf_data[100])); (* SOFT_HLUTNM = "soft_lutpair1265" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[101]_i_1 (.I0(s_axi_wdata[101]), .I1(wready_reg_rep_n_0), .I2(wdf_data[101]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[101]), .O(app_wdf_data[101])); (* SOFT_HLUTNM = "soft_lutpair1266" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[102]_i_1 (.I0(s_axi_wdata[102]), .I1(wready_reg_rep_n_0), .I2(wdf_data[102]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[102]), .O(app_wdf_data[102])); (* SOFT_HLUTNM = "soft_lutpair1267" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[103]_i_1 (.I0(s_axi_wdata[103]), .I1(wready_reg_rep_n_0), .I2(wdf_data[103]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[103]), .O(app_wdf_data[103])); (* SOFT_HLUTNM = "soft_lutpair1268" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[104]_i_1 (.I0(s_axi_wdata[104]), .I1(wready_reg_rep_n_0), .I2(wdf_data[104]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[104]), .O(app_wdf_data[104])); (* SOFT_HLUTNM = "soft_lutpair1269" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[105]_i_1 (.I0(s_axi_wdata[105]), .I1(wready_reg_rep_n_0), .I2(wdf_data[105]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[105]), .O(app_wdf_data[105])); (* SOFT_HLUTNM = "soft_lutpair1270" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[106]_i_1 (.I0(s_axi_wdata[106]), .I1(wready_reg_rep_n_0), .I2(wdf_data[106]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[106]), .O(app_wdf_data[106])); (* SOFT_HLUTNM = "soft_lutpair1271" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[107]_i_1 (.I0(s_axi_wdata[107]), .I1(wready_reg_rep_n_0), .I2(wdf_data[107]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[107]), .O(app_wdf_data[107])); (* SOFT_HLUTNM = "soft_lutpair1272" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[108]_i_1 (.I0(s_axi_wdata[108]), .I1(wready_reg_rep_n_0), .I2(wdf_data[108]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[108]), .O(app_wdf_data[108])); (* SOFT_HLUTNM = "soft_lutpair1273" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[109]_i_1 (.I0(s_axi_wdata[109]), .I1(wready_reg_rep_n_0), .I2(wdf_data[109]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[109]), .O(app_wdf_data[109])); (* SOFT_HLUTNM = "soft_lutpair1174" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[10]_i_1 (.I0(s_axi_wdata[10]), .I1(s_axi_wready), .I2(wdf_data[10]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[10]), .O(app_wdf_data[10])); (* SOFT_HLUTNM = "soft_lutpair1274" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[110]_i_1 (.I0(s_axi_wdata[110]), .I1(wready_reg_rep_n_0), .I2(wdf_data[110]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[110]), .O(app_wdf_data[110])); (* SOFT_HLUTNM = "soft_lutpair1275" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[111]_i_1 (.I0(s_axi_wdata[111]), .I1(wready_reg_rep_n_0), .I2(wdf_data[111]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[111]), .O(app_wdf_data[111])); (* SOFT_HLUTNM = "soft_lutpair1276" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[112]_i_1 (.I0(s_axi_wdata[112]), .I1(wready_reg_rep_n_0), .I2(wdf_data[112]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[112]), .O(app_wdf_data[112])); (* SOFT_HLUTNM = "soft_lutpair1277" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[113]_i_1 (.I0(s_axi_wdata[113]), .I1(wready_reg_rep_n_0), .I2(wdf_data[113]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[113]), .O(app_wdf_data[113])); (* SOFT_HLUTNM = "soft_lutpair1278" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[114]_i_1 (.I0(s_axi_wdata[114]), .I1(wready_reg_rep_n_0), .I2(wdf_data[114]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[114]), .O(app_wdf_data[114])); (* SOFT_HLUTNM = "soft_lutpair1279" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[115]_i_1 (.I0(s_axi_wdata[115]), .I1(wready_reg_rep_n_0), .I2(wdf_data[115]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[115]), .O(app_wdf_data[115])); (* SOFT_HLUTNM = "soft_lutpair1280" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[116]_i_1 (.I0(s_axi_wdata[116]), .I1(wready_reg_rep_n_0), .I2(wdf_data[116]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[116]), .O(app_wdf_data[116])); (* SOFT_HLUTNM = "soft_lutpair1281" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[117]_i_1 (.I0(s_axi_wdata[117]), .I1(wready_reg_rep_n_0), .I2(wdf_data[117]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[117]), .O(app_wdf_data[117])); (* SOFT_HLUTNM = "soft_lutpair1282" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[118]_i_1 (.I0(s_axi_wdata[118]), .I1(wready_reg_rep_n_0), .I2(wdf_data[118]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[118]), .O(app_wdf_data[118])); (* SOFT_HLUTNM = "soft_lutpair1283" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[119]_i_1 (.I0(s_axi_wdata[119]), .I1(wready_reg_rep_n_0), .I2(wdf_data[119]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[119]), .O(app_wdf_data[119])); (* SOFT_HLUTNM = "soft_lutpair1175" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[11]_i_1 (.I0(s_axi_wdata[11]), .I1(s_axi_wready), .I2(wdf_data[11]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[11]), .O(app_wdf_data[11])); (* SOFT_HLUTNM = "soft_lutpair1284" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[120]_i_1 (.I0(s_axi_wdata[120]), .I1(wready_reg_rep_n_0), .I2(wdf_data[120]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[120]), .O(app_wdf_data[120])); (* SOFT_HLUTNM = "soft_lutpair1285" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[121]_i_1 (.I0(s_axi_wdata[121]), .I1(wready_reg_rep_n_0), .I2(wdf_data[121]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[121]), .O(app_wdf_data[121])); (* SOFT_HLUTNM = "soft_lutpair1286" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[122]_i_1 (.I0(s_axi_wdata[122]), .I1(wready_reg_rep_n_0), .I2(wdf_data[122]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[122]), .O(app_wdf_data[122])); (* SOFT_HLUTNM = "soft_lutpair1287" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[123]_i_1 (.I0(s_axi_wdata[123]), .I1(wready_reg_rep_n_0), .I2(wdf_data[123]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[123]), .O(app_wdf_data[123])); (* SOFT_HLUTNM = "soft_lutpair1288" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[124]_i_1 (.I0(s_axi_wdata[124]), .I1(wready_reg_rep_n_0), .I2(wdf_data[124]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[124]), .O(app_wdf_data[124])); (* SOFT_HLUTNM = "soft_lutpair1289" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[125]_i_1 (.I0(s_axi_wdata[125]), .I1(wready_reg_rep_n_0), .I2(wdf_data[125]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[125]), .O(app_wdf_data[125])); (* SOFT_HLUTNM = "soft_lutpair1290" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[126]_i_1 (.I0(s_axi_wdata[126]), .I1(wready_reg_rep_n_0), .I2(wdf_data[126]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[126]), .O(app_wdf_data[126])); (* SOFT_HLUTNM = "soft_lutpair1291" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[127]_i_1 (.I0(s_axi_wdata[127]), .I1(wready_reg_rep_n_0), .I2(wdf_data[127]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[127]), .O(app_wdf_data[127])); (* SOFT_HLUTNM = "soft_lutpair1292" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[128]_i_1 (.I0(s_axi_wdata[128]), .I1(wready_reg_rep_n_0), .I2(wdf_data[128]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[128]), .O(app_wdf_data[128])); (* SOFT_HLUTNM = "soft_lutpair1293" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[129]_i_1 (.I0(s_axi_wdata[129]), .I1(wready_reg_rep_n_0), .I2(wdf_data[129]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[129]), .O(app_wdf_data[129])); (* SOFT_HLUTNM = "soft_lutpair1176" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[12]_i_1 (.I0(s_axi_wdata[12]), .I1(s_axi_wready), .I2(wdf_data[12]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[12]), .O(app_wdf_data[12])); (* SOFT_HLUTNM = "soft_lutpair1294" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[130]_i_1 (.I0(s_axi_wdata[130]), .I1(wready_reg_rep_n_0), .I2(wdf_data[130]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[130]), .O(app_wdf_data[130])); (* SOFT_HLUTNM = "soft_lutpair1295" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[131]_i_1 (.I0(s_axi_wdata[131]), .I1(wready_reg_rep_n_0), .I2(wdf_data[131]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[131]), .O(app_wdf_data[131])); (* SOFT_HLUTNM = "soft_lutpair1296" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[132]_i_1 (.I0(s_axi_wdata[132]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[132]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[132]), .O(app_wdf_data[132])); (* SOFT_HLUTNM = "soft_lutpair1297" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[133]_i_1 (.I0(s_axi_wdata[133]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[133]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[133]), .O(app_wdf_data[133])); (* SOFT_HLUTNM = "soft_lutpair1298" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[134]_i_1 (.I0(s_axi_wdata[134]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[134]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[134]), .O(app_wdf_data[134])); (* SOFT_HLUTNM = "soft_lutpair1299" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[135]_i_1 (.I0(s_axi_wdata[135]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[135]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[135]), .O(app_wdf_data[135])); (* SOFT_HLUTNM = "soft_lutpair1300" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[136]_i_1 (.I0(s_axi_wdata[136]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[136]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[136]), .O(app_wdf_data[136])); (* SOFT_HLUTNM = "soft_lutpair1301" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[137]_i_1 (.I0(s_axi_wdata[137]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[137]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[137]), .O(app_wdf_data[137])); (* SOFT_HLUTNM = "soft_lutpair1302" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[138]_i_1 (.I0(s_axi_wdata[138]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[138]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[138]), .O(app_wdf_data[138])); (* SOFT_HLUTNM = "soft_lutpair1303" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[139]_i_1 (.I0(s_axi_wdata[139]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[139]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[139]), .O(app_wdf_data[139])); (* SOFT_HLUTNM = "soft_lutpair1177" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[13]_i_1 (.I0(s_axi_wdata[13]), .I1(s_axi_wready), .I2(wdf_data[13]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[13]), .O(app_wdf_data[13])); (* SOFT_HLUTNM = "soft_lutpair1304" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[140]_i_1 (.I0(s_axi_wdata[140]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[140]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[140]), .O(app_wdf_data[140])); (* SOFT_HLUTNM = "soft_lutpair1305" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[141]_i_1 (.I0(s_axi_wdata[141]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[141]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[141]), .O(app_wdf_data[141])); (* SOFT_HLUTNM = "soft_lutpair1306" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[142]_i_1 (.I0(s_axi_wdata[142]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[142]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[142]), .O(app_wdf_data[142])); (* SOFT_HLUTNM = "soft_lutpair1307" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[143]_i_1 (.I0(s_axi_wdata[143]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[143]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[143]), .O(app_wdf_data[143])); (* SOFT_HLUTNM = "soft_lutpair1308" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[144]_i_1 (.I0(s_axi_wdata[144]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[144]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[144]), .O(app_wdf_data[144])); (* SOFT_HLUTNM = "soft_lutpair1309" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[145]_i_1 (.I0(s_axi_wdata[145]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[145]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[145]), .O(app_wdf_data[145])); (* SOFT_HLUTNM = "soft_lutpair1310" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[146]_i_1 (.I0(s_axi_wdata[146]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[146]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[146]), .O(app_wdf_data[146])); (* SOFT_HLUTNM = "soft_lutpair1311" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[147]_i_1 (.I0(s_axi_wdata[147]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[147]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[147]), .O(app_wdf_data[147])); (* SOFT_HLUTNM = "soft_lutpair1312" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[148]_i_1 (.I0(s_axi_wdata[148]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[148]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[148]), .O(app_wdf_data[148])); (* SOFT_HLUTNM = "soft_lutpair1313" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[149]_i_1 (.I0(s_axi_wdata[149]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[149]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[149]), .O(app_wdf_data[149])); (* SOFT_HLUTNM = "soft_lutpair1178" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[14]_i_1 (.I0(s_axi_wdata[14]), .I1(s_axi_wready), .I2(wdf_data[14]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[14]), .O(app_wdf_data[14])); (* SOFT_HLUTNM = "soft_lutpair1314" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[150]_i_1 (.I0(s_axi_wdata[150]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[150]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[150]), .O(app_wdf_data[150])); (* SOFT_HLUTNM = "soft_lutpair1315" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[151]_i_1 (.I0(s_axi_wdata[151]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[151]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[151]), .O(app_wdf_data[151])); (* SOFT_HLUTNM = "soft_lutpair1316" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[152]_i_1 (.I0(s_axi_wdata[152]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[152]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[152]), .O(app_wdf_data[152])); (* SOFT_HLUTNM = "soft_lutpair1317" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[153]_i_1 (.I0(s_axi_wdata[153]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[153]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[153]), .O(app_wdf_data[153])); (* SOFT_HLUTNM = "soft_lutpair1318" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[154]_i_1 (.I0(s_axi_wdata[154]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[154]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[154]), .O(app_wdf_data[154])); (* SOFT_HLUTNM = "soft_lutpair1319" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[155]_i_1 (.I0(s_axi_wdata[155]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[155]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[155]), .O(app_wdf_data[155])); (* SOFT_HLUTNM = "soft_lutpair1320" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[156]_i_1 (.I0(s_axi_wdata[156]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[156]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[156]), .O(app_wdf_data[156])); (* SOFT_HLUTNM = "soft_lutpair1321" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[157]_i_1 (.I0(s_axi_wdata[157]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[157]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[157]), .O(app_wdf_data[157])); (* SOFT_HLUTNM = "soft_lutpair1322" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[158]_i_1 (.I0(s_axi_wdata[158]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[158]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[158]), .O(app_wdf_data[158])); (* SOFT_HLUTNM = "soft_lutpair1323" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[159]_i_1 (.I0(s_axi_wdata[159]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[159]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[159]), .O(app_wdf_data[159])); (* SOFT_HLUTNM = "soft_lutpair1179" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[15]_i_1 (.I0(s_axi_wdata[15]), .I1(s_axi_wready), .I2(wdf_data[15]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[15]), .O(app_wdf_data[15])); (* SOFT_HLUTNM = "soft_lutpair1324" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[160]_i_1 (.I0(s_axi_wdata[160]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[160]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[160]), .O(app_wdf_data[160])); (* SOFT_HLUTNM = "soft_lutpair1325" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[161]_i_1 (.I0(s_axi_wdata[161]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[161]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[161]), .O(app_wdf_data[161])); (* SOFT_HLUTNM = "soft_lutpair1326" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[162]_i_1 (.I0(s_axi_wdata[162]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[162]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[162]), .O(app_wdf_data[162])); (* SOFT_HLUTNM = "soft_lutpair1327" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[163]_i_1 (.I0(s_axi_wdata[163]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[163]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[163]), .O(app_wdf_data[163])); (* SOFT_HLUTNM = "soft_lutpair1328" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[164]_i_1 (.I0(s_axi_wdata[164]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[164]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[164]), .O(app_wdf_data[164])); (* SOFT_HLUTNM = "soft_lutpair1329" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[165]_i_1 (.I0(s_axi_wdata[165]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[165]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[165]), .O(app_wdf_data[165])); (* SOFT_HLUTNM = "soft_lutpair1330" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[166]_i_1 (.I0(s_axi_wdata[166]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[166]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[166]), .O(app_wdf_data[166])); (* SOFT_HLUTNM = "soft_lutpair1331" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[167]_i_1 (.I0(s_axi_wdata[167]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[167]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[167]), .O(app_wdf_data[167])); (* SOFT_HLUTNM = "soft_lutpair1332" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[168]_i_1 (.I0(s_axi_wdata[168]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[168]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[168]), .O(app_wdf_data[168])); (* SOFT_HLUTNM = "soft_lutpair1333" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[169]_i_1 (.I0(s_axi_wdata[169]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[169]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[169]), .O(app_wdf_data[169])); (* SOFT_HLUTNM = "soft_lutpair1180" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[16]_i_1 (.I0(s_axi_wdata[16]), .I1(s_axi_wready), .I2(wdf_data[16]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[16]), .O(app_wdf_data[16])); (* SOFT_HLUTNM = "soft_lutpair1334" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[170]_i_1 (.I0(s_axi_wdata[170]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[170]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[170]), .O(app_wdf_data[170])); (* SOFT_HLUTNM = "soft_lutpair1335" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[171]_i_1 (.I0(s_axi_wdata[171]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[171]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[171]), .O(app_wdf_data[171])); (* SOFT_HLUTNM = "soft_lutpair1336" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[172]_i_1 (.I0(s_axi_wdata[172]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[172]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[172]), .O(app_wdf_data[172])); (* SOFT_HLUTNM = "soft_lutpair1337" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[173]_i_1 (.I0(s_axi_wdata[173]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[173]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[173]), .O(app_wdf_data[173])); (* SOFT_HLUTNM = "soft_lutpair1338" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[174]_i_1 (.I0(s_axi_wdata[174]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[174]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[174]), .O(app_wdf_data[174])); (* SOFT_HLUTNM = "soft_lutpair1339" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[175]_i_1 (.I0(s_axi_wdata[175]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[175]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[175]), .O(app_wdf_data[175])); (* SOFT_HLUTNM = "soft_lutpair1340" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[176]_i_1 (.I0(s_axi_wdata[176]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[176]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[176]), .O(app_wdf_data[176])); (* SOFT_HLUTNM = "soft_lutpair1341" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[177]_i_1 (.I0(s_axi_wdata[177]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[177]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[177]), .O(app_wdf_data[177])); (* SOFT_HLUTNM = "soft_lutpair1342" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[178]_i_1 (.I0(s_axi_wdata[178]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[178]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[178]), .O(app_wdf_data[178])); (* SOFT_HLUTNM = "soft_lutpair1343" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[179]_i_1 (.I0(s_axi_wdata[179]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[179]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[179]), .O(app_wdf_data[179])); (* SOFT_HLUTNM = "soft_lutpair1181" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[17]_i_1 (.I0(s_axi_wdata[17]), .I1(s_axi_wready), .I2(wdf_data[17]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[17]), .O(app_wdf_data[17])); (* SOFT_HLUTNM = "soft_lutpair1344" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[180]_i_1 (.I0(s_axi_wdata[180]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[180]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[180]), .O(app_wdf_data[180])); (* SOFT_HLUTNM = "soft_lutpair1345" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[181]_i_1 (.I0(s_axi_wdata[181]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[181]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[181]), .O(app_wdf_data[181])); (* SOFT_HLUTNM = "soft_lutpair1346" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[182]_i_1 (.I0(s_axi_wdata[182]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[182]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[182]), .O(app_wdf_data[182])); (* SOFT_HLUTNM = "soft_lutpair1347" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[183]_i_1 (.I0(s_axi_wdata[183]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[183]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[183]), .O(app_wdf_data[183])); (* SOFT_HLUTNM = "soft_lutpair1348" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[184]_i_1 (.I0(s_axi_wdata[184]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[184]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[184]), .O(app_wdf_data[184])); (* SOFT_HLUTNM = "soft_lutpair1349" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[185]_i_1 (.I0(s_axi_wdata[185]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[185]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[185]), .O(app_wdf_data[185])); (* SOFT_HLUTNM = "soft_lutpair1350" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[186]_i_1 (.I0(s_axi_wdata[186]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[186]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[186]), .O(app_wdf_data[186])); (* SOFT_HLUTNM = "soft_lutpair1351" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[187]_i_1 (.I0(s_axi_wdata[187]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[187]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[187]), .O(app_wdf_data[187])); (* SOFT_HLUTNM = "soft_lutpair1352" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[188]_i_1 (.I0(s_axi_wdata[188]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[188]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[188]), .O(app_wdf_data[188])); (* SOFT_HLUTNM = "soft_lutpair1353" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[189]_i_1 (.I0(s_axi_wdata[189]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[189]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[189]), .O(app_wdf_data[189])); (* SOFT_HLUTNM = "soft_lutpair1182" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[18]_i_1 (.I0(s_axi_wdata[18]), .I1(s_axi_wready), .I2(wdf_data[18]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[18]), .O(app_wdf_data[18])); (* SOFT_HLUTNM = "soft_lutpair1354" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[190]_i_1 (.I0(s_axi_wdata[190]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[190]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[190]), .O(app_wdf_data[190])); (* SOFT_HLUTNM = "soft_lutpair1355" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[191]_i_1 (.I0(s_axi_wdata[191]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[191]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[191]), .O(app_wdf_data[191])); (* SOFT_HLUTNM = "soft_lutpair1356" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[192]_i_1 (.I0(s_axi_wdata[192]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[192]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[192]), .O(app_wdf_data[192])); (* SOFT_HLUTNM = "soft_lutpair1357" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[193]_i_1 (.I0(s_axi_wdata[193]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[193]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[193]), .O(app_wdf_data[193])); (* SOFT_HLUTNM = "soft_lutpair1358" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[194]_i_1 (.I0(s_axi_wdata[194]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[194]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[194]), .O(app_wdf_data[194])); (* SOFT_HLUTNM = "soft_lutpair1359" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[195]_i_1 (.I0(s_axi_wdata[195]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[195]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[195]), .O(app_wdf_data[195])); (* SOFT_HLUTNM = "soft_lutpair1360" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[196]_i_1 (.I0(s_axi_wdata[196]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[196]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[196]), .O(app_wdf_data[196])); (* SOFT_HLUTNM = "soft_lutpair1361" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[197]_i_1 (.I0(s_axi_wdata[197]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[197]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[197]), .O(app_wdf_data[197])); (* SOFT_HLUTNM = "soft_lutpair1362" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[198]_i_1 (.I0(s_axi_wdata[198]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[198]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[198]), .O(app_wdf_data[198])); (* SOFT_HLUTNM = "soft_lutpair1363" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[199]_i_1 (.I0(s_axi_wdata[199]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[199]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[199]), .O(app_wdf_data[199])); (* SOFT_HLUTNM = "soft_lutpair1183" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[19]_i_1 (.I0(s_axi_wdata[19]), .I1(s_axi_wready), .I2(wdf_data[19]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[19]), .O(app_wdf_data[19])); (* SOFT_HLUTNM = "soft_lutpair1165" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[1]_i_1 (.I0(s_axi_wdata[1]), .I1(s_axi_wready), .I2(wdf_data[1]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[1]), .O(app_wdf_data[1])); (* SOFT_HLUTNM = "soft_lutpair1364" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[200]_i_1 (.I0(s_axi_wdata[200]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[200]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[200]), .O(app_wdf_data[200])); (* SOFT_HLUTNM = "soft_lutpair1365" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[201]_i_1 (.I0(s_axi_wdata[201]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[201]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[201]), .O(app_wdf_data[201])); (* SOFT_HLUTNM = "soft_lutpair1366" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[202]_i_1 (.I0(s_axi_wdata[202]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[202]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[202]), .O(app_wdf_data[202])); (* SOFT_HLUTNM = "soft_lutpair1367" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[203]_i_1 (.I0(s_axi_wdata[203]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[203]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[203]), .O(app_wdf_data[203])); (* SOFT_HLUTNM = "soft_lutpair1368" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[204]_i_1 (.I0(s_axi_wdata[204]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[204]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[204]), .O(app_wdf_data[204])); (* SOFT_HLUTNM = "soft_lutpair1369" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[205]_i_1 (.I0(s_axi_wdata[205]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[205]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[205]), .O(app_wdf_data[205])); (* SOFT_HLUTNM = "soft_lutpair1370" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[206]_i_1 (.I0(s_axi_wdata[206]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[206]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[206]), .O(app_wdf_data[206])); (* SOFT_HLUTNM = "soft_lutpair1371" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[207]_i_1 (.I0(s_axi_wdata[207]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[207]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[207]), .O(app_wdf_data[207])); (* SOFT_HLUTNM = "soft_lutpair1372" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[208]_i_1 (.I0(s_axi_wdata[208]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[208]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[208]), .O(app_wdf_data[208])); (* SOFT_HLUTNM = "soft_lutpair1373" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[209]_i_1 (.I0(s_axi_wdata[209]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[209]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[209]), .O(app_wdf_data[209])); (* SOFT_HLUTNM = "soft_lutpair1184" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[20]_i_1 (.I0(s_axi_wdata[20]), .I1(s_axi_wready), .I2(wdf_data[20]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[20]), .O(app_wdf_data[20])); (* SOFT_HLUTNM = "soft_lutpair1374" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[210]_i_1 (.I0(s_axi_wdata[210]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[210]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[210]), .O(app_wdf_data[210])); (* SOFT_HLUTNM = "soft_lutpair1375" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[211]_i_1 (.I0(s_axi_wdata[211]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[211]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[211]), .O(app_wdf_data[211])); (* SOFT_HLUTNM = "soft_lutpair1376" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[212]_i_1 (.I0(s_axi_wdata[212]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[212]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[212]), .O(app_wdf_data[212])); (* SOFT_HLUTNM = "soft_lutpair1377" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[213]_i_1 (.I0(s_axi_wdata[213]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[213]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[213]), .O(app_wdf_data[213])); (* SOFT_HLUTNM = "soft_lutpair1378" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[214]_i_1 (.I0(s_axi_wdata[214]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[214]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[214]), .O(app_wdf_data[214])); (* SOFT_HLUTNM = "soft_lutpair1379" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[215]_i_1 (.I0(s_axi_wdata[215]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[215]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[215]), .O(app_wdf_data[215])); (* SOFT_HLUTNM = "soft_lutpair1380" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[216]_i_1 (.I0(s_axi_wdata[216]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[216]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[216]), .O(app_wdf_data[216])); (* SOFT_HLUTNM = "soft_lutpair1381" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[217]_i_1 (.I0(s_axi_wdata[217]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[217]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[217]), .O(app_wdf_data[217])); (* SOFT_HLUTNM = "soft_lutpair1382" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[218]_i_1 (.I0(s_axi_wdata[218]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[218]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[218]), .O(app_wdf_data[218])); (* SOFT_HLUTNM = "soft_lutpair1383" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[219]_i_1 (.I0(s_axi_wdata[219]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[219]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[219]), .O(app_wdf_data[219])); (* SOFT_HLUTNM = "soft_lutpair1185" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[21]_i_1 (.I0(s_axi_wdata[21]), .I1(s_axi_wready), .I2(wdf_data[21]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[21]), .O(app_wdf_data[21])); (* SOFT_HLUTNM = "soft_lutpair1384" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[220]_i_1 (.I0(s_axi_wdata[220]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[220]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[220]), .O(app_wdf_data[220])); (* SOFT_HLUTNM = "soft_lutpair1385" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[221]_i_1 (.I0(s_axi_wdata[221]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[221]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[221]), .O(app_wdf_data[221])); (* SOFT_HLUTNM = "soft_lutpair1386" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[222]_i_1 (.I0(s_axi_wdata[222]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[222]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[222]), .O(app_wdf_data[222])); (* SOFT_HLUTNM = "soft_lutpair1387" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[223]_i_1 (.I0(s_axi_wdata[223]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[223]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[223]), .O(app_wdf_data[223])); (* SOFT_HLUTNM = "soft_lutpair1388" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[224]_i_1 (.I0(s_axi_wdata[224]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[224]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[224]), .O(app_wdf_data[224])); (* SOFT_HLUTNM = "soft_lutpair1389" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[225]_i_1 (.I0(s_axi_wdata[225]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[225]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[225]), .O(app_wdf_data[225])); (* SOFT_HLUTNM = "soft_lutpair1390" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[226]_i_1 (.I0(s_axi_wdata[226]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[226]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[226]), .O(app_wdf_data[226])); (* SOFT_HLUTNM = "soft_lutpair1391" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[227]_i_1 (.I0(s_axi_wdata[227]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[227]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[227]), .O(app_wdf_data[227])); (* SOFT_HLUTNM = "soft_lutpair1392" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[228]_i_1 (.I0(s_axi_wdata[228]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[228]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[228]), .O(app_wdf_data[228])); (* SOFT_HLUTNM = "soft_lutpair1393" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[229]_i_1 (.I0(s_axi_wdata[229]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[229]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[229]), .O(app_wdf_data[229])); (* SOFT_HLUTNM = "soft_lutpair1186" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[22]_i_1 (.I0(s_axi_wdata[22]), .I1(s_axi_wready), .I2(wdf_data[22]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[22]), .O(app_wdf_data[22])); (* SOFT_HLUTNM = "soft_lutpair1394" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[230]_i_1 (.I0(s_axi_wdata[230]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[230]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[230]), .O(app_wdf_data[230])); (* SOFT_HLUTNM = "soft_lutpair1395" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[231]_i_1 (.I0(s_axi_wdata[231]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[231]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[231]), .O(app_wdf_data[231])); (* SOFT_HLUTNM = "soft_lutpair1396" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[232]_i_1 (.I0(s_axi_wdata[232]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[232]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[232]), .O(app_wdf_data[232])); (* SOFT_HLUTNM = "soft_lutpair1397" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[233]_i_1 (.I0(s_axi_wdata[233]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[233]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[233]), .O(app_wdf_data[233])); (* SOFT_HLUTNM = "soft_lutpair1398" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[234]_i_1 (.I0(s_axi_wdata[234]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[234]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[234]), .O(app_wdf_data[234])); (* SOFT_HLUTNM = "soft_lutpair1399" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[235]_i_1 (.I0(s_axi_wdata[235]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[235]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[235]), .O(app_wdf_data[235])); (* SOFT_HLUTNM = "soft_lutpair1400" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[236]_i_1 (.I0(s_axi_wdata[236]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[236]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[236]), .O(app_wdf_data[236])); (* SOFT_HLUTNM = "soft_lutpair1401" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[237]_i_1 (.I0(s_axi_wdata[237]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[237]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[237]), .O(app_wdf_data[237])); (* SOFT_HLUTNM = "soft_lutpair1402" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[238]_i_1 (.I0(s_axi_wdata[238]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[238]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[238]), .O(app_wdf_data[238])); (* SOFT_HLUTNM = "soft_lutpair1403" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[239]_i_1 (.I0(s_axi_wdata[239]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[239]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[239]), .O(app_wdf_data[239])); (* SOFT_HLUTNM = "soft_lutpair1187" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[23]_i_1 (.I0(s_axi_wdata[23]), .I1(s_axi_wready), .I2(wdf_data[23]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[23]), .O(app_wdf_data[23])); (* SOFT_HLUTNM = "soft_lutpair1404" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[240]_i_1 (.I0(s_axi_wdata[240]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[240]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[240]), .O(app_wdf_data[240])); (* SOFT_HLUTNM = "soft_lutpair1405" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[241]_i_1 (.I0(s_axi_wdata[241]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[241]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[241]), .O(app_wdf_data[241])); (* SOFT_HLUTNM = "soft_lutpair1406" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[242]_i_1 (.I0(s_axi_wdata[242]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[242]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[242]), .O(app_wdf_data[242])); (* SOFT_HLUTNM = "soft_lutpair1407" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[243]_i_1 (.I0(s_axi_wdata[243]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[243]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[243]), .O(app_wdf_data[243])); (* SOFT_HLUTNM = "soft_lutpair1408" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[244]_i_1 (.I0(s_axi_wdata[244]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[244]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[244]), .O(app_wdf_data[244])); (* SOFT_HLUTNM = "soft_lutpair1409" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[245]_i_1 (.I0(s_axi_wdata[245]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[245]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[245]), .O(app_wdf_data[245])); (* SOFT_HLUTNM = "soft_lutpair1410" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[246]_i_1 (.I0(s_axi_wdata[246]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[246]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[246]), .O(app_wdf_data[246])); (* SOFT_HLUTNM = "soft_lutpair1411" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[247]_i_1 (.I0(s_axi_wdata[247]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[247]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[247]), .O(app_wdf_data[247])); (* SOFT_HLUTNM = "soft_lutpair1412" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[248]_i_1 (.I0(s_axi_wdata[248]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[248]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[248]), .O(app_wdf_data[248])); (* SOFT_HLUTNM = "soft_lutpair1413" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[249]_i_1 (.I0(s_axi_wdata[249]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[249]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[249]), .O(app_wdf_data[249])); (* SOFT_HLUTNM = "soft_lutpair1188" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[24]_i_1 (.I0(s_axi_wdata[24]), .I1(s_axi_wready), .I2(wdf_data[24]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[24]), .O(app_wdf_data[24])); (* SOFT_HLUTNM = "soft_lutpair1414" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[250]_i_1 (.I0(s_axi_wdata[250]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[250]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[250]), .O(app_wdf_data[250])); (* SOFT_HLUTNM = "soft_lutpair1415" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[251]_i_1 (.I0(s_axi_wdata[251]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[251]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[251]), .O(app_wdf_data[251])); (* SOFT_HLUTNM = "soft_lutpair1416" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[252]_i_1 (.I0(s_axi_wdata[252]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[252]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[252]), .O(app_wdf_data[252])); (* SOFT_HLUTNM = "soft_lutpair1417" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[253]_i_1 (.I0(s_axi_wdata[253]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[253]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[253]), .O(app_wdf_data[253])); (* SOFT_HLUTNM = "soft_lutpair1418" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[254]_i_1 (.I0(s_axi_wdata[254]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[254]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[254]), .O(app_wdf_data[254])); (* SOFT_HLUTNM = "soft_lutpair1419" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[255]_i_1 (.I0(s_axi_wdata[255]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[255]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[255]), .O(app_wdf_data[255])); (* SOFT_HLUTNM = "soft_lutpair1189" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[25]_i_1 (.I0(s_axi_wdata[25]), .I1(s_axi_wready), .I2(wdf_data[25]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[25]), .O(app_wdf_data[25])); (* SOFT_HLUTNM = "soft_lutpair1190" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[26]_i_1 (.I0(s_axi_wdata[26]), .I1(s_axi_wready), .I2(wdf_data[26]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[26]), .O(app_wdf_data[26])); (* SOFT_HLUTNM = "soft_lutpair1191" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[27]_i_1 (.I0(s_axi_wdata[27]), .I1(s_axi_wready), .I2(wdf_data[27]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[27]), .O(app_wdf_data[27])); (* SOFT_HLUTNM = "soft_lutpair1192" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[28]_i_1 (.I0(s_axi_wdata[28]), .I1(s_axi_wready), .I2(wdf_data[28]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[28]), .O(app_wdf_data[28])); (* SOFT_HLUTNM = "soft_lutpair1193" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[29]_i_1 (.I0(s_axi_wdata[29]), .I1(s_axi_wready), .I2(wdf_data[29]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[29]), .O(app_wdf_data[29])); (* SOFT_HLUTNM = "soft_lutpair1166" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[2]_i_1 (.I0(s_axi_wdata[2]), .I1(s_axi_wready), .I2(wdf_data[2]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[2]), .O(app_wdf_data[2])); (* SOFT_HLUTNM = "soft_lutpair1194" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[30]_i_1 (.I0(s_axi_wdata[30]), .I1(s_axi_wready), .I2(wdf_data[30]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[30]), .O(app_wdf_data[30])); (* SOFT_HLUTNM = "soft_lutpair1195" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[31]_i_1 (.I0(s_axi_wdata[31]), .I1(s_axi_wready), .I2(wdf_data[31]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[31]), .O(app_wdf_data[31])); (* SOFT_HLUTNM = "soft_lutpair1196" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[32]_i_1 (.I0(s_axi_wdata[32]), .I1(s_axi_wready), .I2(wdf_data[32]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[32]), .O(app_wdf_data[32])); (* SOFT_HLUTNM = "soft_lutpair1197" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[33]_i_1 (.I0(s_axi_wdata[33]), .I1(s_axi_wready), .I2(wdf_data[33]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[33]), .O(app_wdf_data[33])); (* SOFT_HLUTNM = "soft_lutpair1198" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[34]_i_1 (.I0(s_axi_wdata[34]), .I1(s_axi_wready), .I2(wdf_data[34]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[34]), .O(app_wdf_data[34])); (* SOFT_HLUTNM = "soft_lutpair1199" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[35]_i_1 (.I0(s_axi_wdata[35]), .I1(s_axi_wready), .I2(wdf_data[35]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[35]), .O(app_wdf_data[35])); (* SOFT_HLUTNM = "soft_lutpair1200" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[36]_i_1 (.I0(s_axi_wdata[36]), .I1(s_axi_wready), .I2(wdf_data[36]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[36]), .O(app_wdf_data[36])); (* SOFT_HLUTNM = "soft_lutpair1201" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[37]_i_1 (.I0(s_axi_wdata[37]), .I1(s_axi_wready), .I2(wdf_data[37]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[37]), .O(app_wdf_data[37])); (* SOFT_HLUTNM = "soft_lutpair1202" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[38]_i_1 (.I0(s_axi_wdata[38]), .I1(s_axi_wready), .I2(wdf_data[38]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[38]), .O(app_wdf_data[38])); (* SOFT_HLUTNM = "soft_lutpair1203" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[39]_i_1 (.I0(s_axi_wdata[39]), .I1(s_axi_wready), .I2(wdf_data[39]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[39]), .O(app_wdf_data[39])); (* SOFT_HLUTNM = "soft_lutpair1167" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[3]_i_1 (.I0(s_axi_wdata[3]), .I1(s_axi_wready), .I2(wdf_data[3]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[3]), .O(app_wdf_data[3])); (* SOFT_HLUTNM = "soft_lutpair1204" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[40]_i_1 (.I0(s_axi_wdata[40]), .I1(s_axi_wready), .I2(wdf_data[40]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[40]), .O(app_wdf_data[40])); (* SOFT_HLUTNM = "soft_lutpair1205" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[41]_i_1 (.I0(s_axi_wdata[41]), .I1(s_axi_wready), .I2(wdf_data[41]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[41]), .O(app_wdf_data[41])); (* SOFT_HLUTNM = "soft_lutpair1206" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[42]_i_1 (.I0(s_axi_wdata[42]), .I1(s_axi_wready), .I2(wdf_data[42]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[42]), .O(app_wdf_data[42])); (* SOFT_HLUTNM = "soft_lutpair1207" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[43]_i_1 (.I0(s_axi_wdata[43]), .I1(s_axi_wready), .I2(wdf_data[43]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[43]), .O(app_wdf_data[43])); (* SOFT_HLUTNM = "soft_lutpair1208" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[44]_i_1 (.I0(s_axi_wdata[44]), .I1(s_axi_wready), .I2(wdf_data[44]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[44]), .O(app_wdf_data[44])); (* SOFT_HLUTNM = "soft_lutpair1209" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[45]_i_1 (.I0(s_axi_wdata[45]), .I1(s_axi_wready), .I2(wdf_data[45]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[45]), .O(app_wdf_data[45])); (* SOFT_HLUTNM = "soft_lutpair1210" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[46]_i_1 (.I0(s_axi_wdata[46]), .I1(s_axi_wready), .I2(wdf_data[46]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[46]), .O(app_wdf_data[46])); (* SOFT_HLUTNM = "soft_lutpair1211" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[47]_i_1 (.I0(s_axi_wdata[47]), .I1(s_axi_wready), .I2(wdf_data[47]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[47]), .O(app_wdf_data[47])); (* SOFT_HLUTNM = "soft_lutpair1212" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[48]_i_1 (.I0(s_axi_wdata[48]), .I1(s_axi_wready), .I2(wdf_data[48]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[48]), .O(app_wdf_data[48])); (* SOFT_HLUTNM = "soft_lutpair1213" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[49]_i_1 (.I0(s_axi_wdata[49]), .I1(s_axi_wready), .I2(wdf_data[49]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[49]), .O(app_wdf_data[49])); (* SOFT_HLUTNM = "soft_lutpair1168" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[4]_i_1 (.I0(s_axi_wdata[4]), .I1(s_axi_wready), .I2(wdf_data[4]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[4]), .O(app_wdf_data[4])); (* SOFT_HLUTNM = "soft_lutpair1214" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[50]_i_1 (.I0(s_axi_wdata[50]), .I1(s_axi_wready), .I2(wdf_data[50]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[50]), .O(app_wdf_data[50])); (* SOFT_HLUTNM = "soft_lutpair1215" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[51]_i_1 (.I0(s_axi_wdata[51]), .I1(s_axi_wready), .I2(wdf_data[51]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[51]), .O(app_wdf_data[51])); (* SOFT_HLUTNM = "soft_lutpair1216" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[52]_i_1 (.I0(s_axi_wdata[52]), .I1(s_axi_wready), .I2(wdf_data[52]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[52]), .O(app_wdf_data[52])); (* SOFT_HLUTNM = "soft_lutpair1217" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[53]_i_1 (.I0(s_axi_wdata[53]), .I1(s_axi_wready), .I2(wdf_data[53]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[53]), .O(app_wdf_data[53])); (* SOFT_HLUTNM = "soft_lutpair1218" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[54]_i_1 (.I0(s_axi_wdata[54]), .I1(s_axi_wready), .I2(wdf_data[54]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[54]), .O(app_wdf_data[54])); (* SOFT_HLUTNM = "soft_lutpair1219" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[55]_i_1 (.I0(s_axi_wdata[55]), .I1(s_axi_wready), .I2(wdf_data[55]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[55]), .O(app_wdf_data[55])); (* SOFT_HLUTNM = "soft_lutpair1220" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[56]_i_1 (.I0(s_axi_wdata[56]), .I1(s_axi_wready), .I2(wdf_data[56]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[56]), .O(app_wdf_data[56])); (* SOFT_HLUTNM = "soft_lutpair1221" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[57]_i_1 (.I0(s_axi_wdata[57]), .I1(s_axi_wready), .I2(wdf_data[57]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[57]), .O(app_wdf_data[57])); (* SOFT_HLUTNM = "soft_lutpair1222" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[58]_i_1 (.I0(s_axi_wdata[58]), .I1(s_axi_wready), .I2(wdf_data[58]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[58]), .O(app_wdf_data[58])); (* SOFT_HLUTNM = "soft_lutpair1223" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[59]_i_1 (.I0(s_axi_wdata[59]), .I1(s_axi_wready), .I2(wdf_data[59]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[59]), .O(app_wdf_data[59])); (* SOFT_HLUTNM = "soft_lutpair1169" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[5]_i_1 (.I0(s_axi_wdata[5]), .I1(s_axi_wready), .I2(wdf_data[5]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[5]), .O(app_wdf_data[5])); (* SOFT_HLUTNM = "soft_lutpair1224" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[60]_i_1 (.I0(s_axi_wdata[60]), .I1(s_axi_wready), .I2(wdf_data[60]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[60]), .O(app_wdf_data[60])); (* SOFT_HLUTNM = "soft_lutpair1225" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[61]_i_1 (.I0(s_axi_wdata[61]), .I1(s_axi_wready), .I2(wdf_data[61]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[61]), .O(app_wdf_data[61])); (* SOFT_HLUTNM = "soft_lutpair1226" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[62]_i_1 (.I0(s_axi_wdata[62]), .I1(s_axi_wready), .I2(wdf_data[62]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[62]), .O(app_wdf_data[62])); (* SOFT_HLUTNM = "soft_lutpair1227" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[63]_i_1 (.I0(s_axi_wdata[63]), .I1(s_axi_wready), .I2(wdf_data[63]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[63]), .O(app_wdf_data[63])); (* SOFT_HLUTNM = "soft_lutpair1228" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[64]_i_1 (.I0(s_axi_wdata[64]), .I1(s_axi_wready), .I2(wdf_data[64]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[64]), .O(app_wdf_data[64])); (* SOFT_HLUTNM = "soft_lutpair1229" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[65]_i_1 (.I0(s_axi_wdata[65]), .I1(s_axi_wready), .I2(wdf_data[65]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[65]), .O(app_wdf_data[65])); (* SOFT_HLUTNM = "soft_lutpair1230" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[66]_i_1 (.I0(s_axi_wdata[66]), .I1(wready_reg_rep_n_0), .I2(wdf_data[66]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[66]), .O(app_wdf_data[66])); (* SOFT_HLUTNM = "soft_lutpair1231" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[67]_i_1 (.I0(s_axi_wdata[67]), .I1(wready_reg_rep_n_0), .I2(wdf_data[67]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[67]), .O(app_wdf_data[67])); (* SOFT_HLUTNM = "soft_lutpair1232" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[68]_i_1 (.I0(s_axi_wdata[68]), .I1(wready_reg_rep_n_0), .I2(wdf_data[68]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[68]), .O(app_wdf_data[68])); (* SOFT_HLUTNM = "soft_lutpair1233" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[69]_i_1 (.I0(s_axi_wdata[69]), .I1(wready_reg_rep_n_0), .I2(wdf_data[69]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[69]), .O(app_wdf_data[69])); (* SOFT_HLUTNM = "soft_lutpair1170" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[6]_i_1 (.I0(s_axi_wdata[6]), .I1(s_axi_wready), .I2(wdf_data[6]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[6]), .O(app_wdf_data[6])); (* SOFT_HLUTNM = "soft_lutpair1234" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[70]_i_1 (.I0(s_axi_wdata[70]), .I1(wready_reg_rep_n_0), .I2(wdf_data[70]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[70]), .O(app_wdf_data[70])); (* SOFT_HLUTNM = "soft_lutpair1235" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[71]_i_1 (.I0(s_axi_wdata[71]), .I1(wready_reg_rep_n_0), .I2(wdf_data[71]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[71]), .O(app_wdf_data[71])); (* SOFT_HLUTNM = "soft_lutpair1236" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[72]_i_1 (.I0(s_axi_wdata[72]), .I1(wready_reg_rep_n_0), .I2(wdf_data[72]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[72]), .O(app_wdf_data[72])); (* SOFT_HLUTNM = "soft_lutpair1237" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[73]_i_1 (.I0(s_axi_wdata[73]), .I1(wready_reg_rep_n_0), .I2(wdf_data[73]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[73]), .O(app_wdf_data[73])); (* SOFT_HLUTNM = "soft_lutpair1238" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[74]_i_1 (.I0(s_axi_wdata[74]), .I1(wready_reg_rep_n_0), .I2(wdf_data[74]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[74]), .O(app_wdf_data[74])); (* SOFT_HLUTNM = "soft_lutpair1239" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[75]_i_1 (.I0(s_axi_wdata[75]), .I1(wready_reg_rep_n_0), .I2(wdf_data[75]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[75]), .O(app_wdf_data[75])); (* SOFT_HLUTNM = "soft_lutpair1240" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[76]_i_1 (.I0(s_axi_wdata[76]), .I1(wready_reg_rep_n_0), .I2(wdf_data[76]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[76]), .O(app_wdf_data[76])); (* SOFT_HLUTNM = "soft_lutpair1241" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[77]_i_1 (.I0(s_axi_wdata[77]), .I1(wready_reg_rep_n_0), .I2(wdf_data[77]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[77]), .O(app_wdf_data[77])); (* SOFT_HLUTNM = "soft_lutpair1242" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[78]_i_1 (.I0(s_axi_wdata[78]), .I1(wready_reg_rep_n_0), .I2(wdf_data[78]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[78]), .O(app_wdf_data[78])); (* SOFT_HLUTNM = "soft_lutpair1243" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[79]_i_1 (.I0(s_axi_wdata[79]), .I1(wready_reg_rep_n_0), .I2(wdf_data[79]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[79]), .O(app_wdf_data[79])); (* SOFT_HLUTNM = "soft_lutpair1171" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[7]_i_1 (.I0(s_axi_wdata[7]), .I1(s_axi_wready), .I2(wdf_data[7]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[7]), .O(app_wdf_data[7])); (* SOFT_HLUTNM = "soft_lutpair1244" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[80]_i_1 (.I0(s_axi_wdata[80]), .I1(wready_reg_rep_n_0), .I2(wdf_data[80]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[80]), .O(app_wdf_data[80])); (* SOFT_HLUTNM = "soft_lutpair1245" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[81]_i_1 (.I0(s_axi_wdata[81]), .I1(wready_reg_rep_n_0), .I2(wdf_data[81]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[81]), .O(app_wdf_data[81])); (* SOFT_HLUTNM = "soft_lutpair1246" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[82]_i_1 (.I0(s_axi_wdata[82]), .I1(wready_reg_rep_n_0), .I2(wdf_data[82]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[82]), .O(app_wdf_data[82])); (* SOFT_HLUTNM = "soft_lutpair1247" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[83]_i_1 (.I0(s_axi_wdata[83]), .I1(wready_reg_rep_n_0), .I2(wdf_data[83]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[83]), .O(app_wdf_data[83])); (* SOFT_HLUTNM = "soft_lutpair1248" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[84]_i_1 (.I0(s_axi_wdata[84]), .I1(wready_reg_rep_n_0), .I2(wdf_data[84]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[84]), .O(app_wdf_data[84])); (* SOFT_HLUTNM = "soft_lutpair1249" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[85]_i_1 (.I0(s_axi_wdata[85]), .I1(wready_reg_rep_n_0), .I2(wdf_data[85]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[85]), .O(app_wdf_data[85])); (* SOFT_HLUTNM = "soft_lutpair1250" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[86]_i_1 (.I0(s_axi_wdata[86]), .I1(wready_reg_rep_n_0), .I2(wdf_data[86]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[86]), .O(app_wdf_data[86])); (* SOFT_HLUTNM = "soft_lutpair1251" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[87]_i_1 (.I0(s_axi_wdata[87]), .I1(wready_reg_rep_n_0), .I2(wdf_data[87]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[87]), .O(app_wdf_data[87])); (* SOFT_HLUTNM = "soft_lutpair1252" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[88]_i_1 (.I0(s_axi_wdata[88]), .I1(wready_reg_rep_n_0), .I2(wdf_data[88]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[88]), .O(app_wdf_data[88])); (* SOFT_HLUTNM = "soft_lutpair1253" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[89]_i_1 (.I0(s_axi_wdata[89]), .I1(wready_reg_rep_n_0), .I2(wdf_data[89]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[89]), .O(app_wdf_data[89])); (* SOFT_HLUTNM = "soft_lutpair1172" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[8]_i_1 (.I0(s_axi_wdata[8]), .I1(s_axi_wready), .I2(wdf_data[8]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[8]), .O(app_wdf_data[8])); (* SOFT_HLUTNM = "soft_lutpair1254" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[90]_i_1 (.I0(s_axi_wdata[90]), .I1(wready_reg_rep_n_0), .I2(wdf_data[90]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[90]), .O(app_wdf_data[90])); (* SOFT_HLUTNM = "soft_lutpair1255" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[91]_i_1 (.I0(s_axi_wdata[91]), .I1(wready_reg_rep_n_0), .I2(wdf_data[91]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[91]), .O(app_wdf_data[91])); (* SOFT_HLUTNM = "soft_lutpair1256" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[92]_i_1 (.I0(s_axi_wdata[92]), .I1(wready_reg_rep_n_0), .I2(wdf_data[92]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[92]), .O(app_wdf_data[92])); (* SOFT_HLUTNM = "soft_lutpair1257" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[93]_i_1 (.I0(s_axi_wdata[93]), .I1(wready_reg_rep_n_0), .I2(wdf_data[93]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[93]), .O(app_wdf_data[93])); (* SOFT_HLUTNM = "soft_lutpair1258" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[94]_i_1 (.I0(s_axi_wdata[94]), .I1(wready_reg_rep_n_0), .I2(wdf_data[94]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[94]), .O(app_wdf_data[94])); (* SOFT_HLUTNM = "soft_lutpair1259" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[95]_i_1 (.I0(s_axi_wdata[95]), .I1(wready_reg_rep_n_0), .I2(wdf_data[95]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[95]), .O(app_wdf_data[95])); (* SOFT_HLUTNM = "soft_lutpair1260" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[96]_i_1 (.I0(s_axi_wdata[96]), .I1(wready_reg_rep_n_0), .I2(wdf_data[96]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[96]), .O(app_wdf_data[96])); (* SOFT_HLUTNM = "soft_lutpair1261" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[97]_i_1 (.I0(s_axi_wdata[97]), .I1(wready_reg_rep_n_0), .I2(wdf_data[97]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[97]), .O(app_wdf_data[97])); (* SOFT_HLUTNM = "soft_lutpair1262" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[98]_i_1 (.I0(s_axi_wdata[98]), .I1(wready_reg_rep_n_0), .I2(wdf_data[98]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[98]), .O(app_wdf_data[98])); (* SOFT_HLUTNM = "soft_lutpair1263" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[99]_i_1 (.I0(s_axi_wdata[99]), .I1(wready_reg_rep_n_0), .I2(wdf_data[99]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[99]), .O(app_wdf_data[99])); (* SOFT_HLUTNM = "soft_lutpair1173" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[9]_i_1 (.I0(s_axi_wdata[9]), .I1(s_axi_wready), .I2(wdf_data[9]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[9]), .O(app_wdf_data[9])); (* SOFT_HLUTNM = "soft_lutpair1420" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[0]_i_1 (.I0(s_axi_wstrb[0]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[0]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[0]), .O(app_wdf_mask[0])); (* SOFT_HLUTNM = "soft_lutpair1430" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[10]_i_1 (.I0(s_axi_wstrb[10]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[10]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[10]), .O(app_wdf_mask[10])); (* SOFT_HLUTNM = "soft_lutpair1431" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[11]_i_1 (.I0(s_axi_wstrb[11]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[11]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[11]), .O(app_wdf_mask[11])); (* SOFT_HLUTNM = "soft_lutpair1432" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[12]_i_1 (.I0(s_axi_wstrb[12]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[12]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[12]), .O(app_wdf_mask[12])); (* SOFT_HLUTNM = "soft_lutpair1433" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[13]_i_1 (.I0(s_axi_wstrb[13]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[13]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[13]), .O(app_wdf_mask[13])); (* SOFT_HLUTNM = "soft_lutpair1434" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[14]_i_1 (.I0(s_axi_wstrb[14]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[14]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[14]), .O(app_wdf_mask[14])); (* SOFT_HLUTNM = "soft_lutpair1435" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[15]_i_1 (.I0(s_axi_wstrb[15]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[15]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[15]), .O(app_wdf_mask[15])); (* SOFT_HLUTNM = "soft_lutpair1436" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[16]_i_1 (.I0(s_axi_wstrb[16]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[16]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[16]), .O(app_wdf_mask[16])); (* SOFT_HLUTNM = "soft_lutpair1437" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[17]_i_1 (.I0(s_axi_wstrb[17]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[17]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[17]), .O(app_wdf_mask[17])); (* SOFT_HLUTNM = "soft_lutpair1438" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[18]_i_1 (.I0(s_axi_wstrb[18]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[18]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[18]), .O(app_wdf_mask[18])); (* SOFT_HLUTNM = "soft_lutpair1439" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[19]_i_1 (.I0(s_axi_wstrb[19]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[19]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[19]), .O(app_wdf_mask[19])); (* SOFT_HLUTNM = "soft_lutpair1421" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[1]_i_1 (.I0(s_axi_wstrb[1]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[1]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[1]), .O(app_wdf_mask[1])); (* SOFT_HLUTNM = "soft_lutpair1440" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[20]_i_1 (.I0(s_axi_wstrb[20]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[20]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[20]), .O(app_wdf_mask[20])); (* SOFT_HLUTNM = "soft_lutpair1441" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[21]_i_1 (.I0(s_axi_wstrb[21]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[21]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[21]), .O(app_wdf_mask[21])); (* SOFT_HLUTNM = "soft_lutpair1442" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[22]_i_1 (.I0(s_axi_wstrb[22]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[22]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[22]), .O(app_wdf_mask[22])); (* SOFT_HLUTNM = "soft_lutpair1443" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[23]_i_1 (.I0(s_axi_wstrb[23]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[23]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[23]), .O(app_wdf_mask[23])); (* SOFT_HLUTNM = "soft_lutpair1444" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[24]_i_1 (.I0(s_axi_wstrb[24]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[24]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[24]), .O(app_wdf_mask[24])); (* SOFT_HLUTNM = "soft_lutpair1445" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[25]_i_1 (.I0(s_axi_wstrb[25]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[25]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[25]), .O(app_wdf_mask[25])); (* SOFT_HLUTNM = "soft_lutpair1446" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[26]_i_1 (.I0(s_axi_wstrb[26]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[26]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[26]), .O(app_wdf_mask[26])); (* SOFT_HLUTNM = "soft_lutpair1447" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[27]_i_1 (.I0(s_axi_wstrb[27]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[27]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[27]), .O(app_wdf_mask[27])); (* SOFT_HLUTNM = "soft_lutpair1448" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[28]_i_1 (.I0(s_axi_wstrb[28]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[28]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[28]), .O(app_wdf_mask[28])); (* SOFT_HLUTNM = "soft_lutpair1449" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[29]_i_1 (.I0(s_axi_wstrb[29]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[29]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[29]), .O(app_wdf_mask[29])); (* SOFT_HLUTNM = "soft_lutpair1422" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[2]_i_1 (.I0(s_axi_wstrb[2]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[2]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[2]), .O(app_wdf_mask[2])); (* SOFT_HLUTNM = "soft_lutpair1450" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[30]_i_1 (.I0(s_axi_wstrb[30]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[30]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[30]), .O(app_wdf_mask[30])); (* SOFT_HLUTNM = "soft_lutpair1451" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[31]_i_1 (.I0(s_axi_wstrb[31]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[31]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[31]), .O(app_wdf_mask[31])); (* SOFT_HLUTNM = "soft_lutpair1423" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[3]_i_1 (.I0(s_axi_wstrb[3]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[3]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[3]), .O(app_wdf_mask[3])); (* SOFT_HLUTNM = "soft_lutpair1424" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[4]_i_1 (.I0(s_axi_wstrb[4]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[4]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[4]), .O(app_wdf_mask[4])); (* SOFT_HLUTNM = "soft_lutpair1425" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[5]_i_1 (.I0(s_axi_wstrb[5]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[5]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[5]), .O(app_wdf_mask[5])); (* SOFT_HLUTNM = "soft_lutpair1426" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[6]_i_1 (.I0(s_axi_wstrb[6]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[6]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[6]), .O(app_wdf_mask[6])); (* SOFT_HLUTNM = "soft_lutpair1427" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[7]_i_1 (.I0(s_axi_wstrb[7]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[7]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[7]), .O(app_wdf_mask[7])); (* SOFT_HLUTNM = "soft_lutpair1428" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[8]_i_1 (.I0(s_axi_wstrb[8]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[8]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[8]), .O(app_wdf_mask[8])); (* SOFT_HLUTNM = "soft_lutpair1429" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[9]_i_1 (.I0(s_axi_wstrb[9]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[9]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[9]), .O(app_wdf_mask[9])); (* SOFT_HLUTNM = "soft_lutpair1452" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[0]_i_1 (.I0(s_axi_wdata[0]), .I1(s_axi_wready), .I2(wdf_data[0]), .O(\mc_app_wdf_data_reg_reg[255]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair1264" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[100]_i_1 (.I0(s_axi_wdata[100]), .I1(wready_reg_rep_n_0), .I2(wdf_data[100]), .O(\mc_app_wdf_data_reg_reg[255]_0 [100])); (* SOFT_HLUTNM = "soft_lutpair1265" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[101]_i_1 (.I0(s_axi_wdata[101]), .I1(wready_reg_rep_n_0), .I2(wdf_data[101]), .O(\mc_app_wdf_data_reg_reg[255]_0 [101])); (* SOFT_HLUTNM = "soft_lutpair1266" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[102]_i_1 (.I0(s_axi_wdata[102]), .I1(wready_reg_rep_n_0), .I2(wdf_data[102]), .O(\mc_app_wdf_data_reg_reg[255]_0 [102])); (* SOFT_HLUTNM = "soft_lutpair1267" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[103]_i_1 (.I0(s_axi_wdata[103]), .I1(wready_reg_rep_n_0), .I2(wdf_data[103]), .O(\mc_app_wdf_data_reg_reg[255]_0 [103])); (* SOFT_HLUTNM = "soft_lutpair1268" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[104]_i_1 (.I0(s_axi_wdata[104]), .I1(wready_reg_rep_n_0), .I2(wdf_data[104]), .O(\mc_app_wdf_data_reg_reg[255]_0 [104])); (* SOFT_HLUTNM = "soft_lutpair1269" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[105]_i_1 (.I0(s_axi_wdata[105]), .I1(wready_reg_rep_n_0), .I2(wdf_data[105]), .O(\mc_app_wdf_data_reg_reg[255]_0 [105])); (* SOFT_HLUTNM = "soft_lutpair1270" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[106]_i_1 (.I0(s_axi_wdata[106]), .I1(wready_reg_rep_n_0), .I2(wdf_data[106]), .O(\mc_app_wdf_data_reg_reg[255]_0 [106])); (* SOFT_HLUTNM = "soft_lutpair1271" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[107]_i_1 (.I0(s_axi_wdata[107]), .I1(wready_reg_rep_n_0), .I2(wdf_data[107]), .O(\mc_app_wdf_data_reg_reg[255]_0 [107])); (* SOFT_HLUTNM = "soft_lutpair1272" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[108]_i_1 (.I0(s_axi_wdata[108]), .I1(wready_reg_rep_n_0), .I2(wdf_data[108]), .O(\mc_app_wdf_data_reg_reg[255]_0 [108])); (* SOFT_HLUTNM = "soft_lutpair1273" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[109]_i_1 (.I0(s_axi_wdata[109]), .I1(wready_reg_rep_n_0), .I2(wdf_data[109]), .O(\mc_app_wdf_data_reg_reg[255]_0 [109])); (* SOFT_HLUTNM = "soft_lutpair1174" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[10]_i_1 (.I0(s_axi_wdata[10]), .I1(s_axi_wready), .I2(wdf_data[10]), .O(\mc_app_wdf_data_reg_reg[255]_0 [10])); (* SOFT_HLUTNM = "soft_lutpair1274" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[110]_i_1 (.I0(s_axi_wdata[110]), .I1(wready_reg_rep_n_0), .I2(wdf_data[110]), .O(\mc_app_wdf_data_reg_reg[255]_0 [110])); (* SOFT_HLUTNM = "soft_lutpair1275" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[111]_i_1 (.I0(s_axi_wdata[111]), .I1(wready_reg_rep_n_0), .I2(wdf_data[111]), .O(\mc_app_wdf_data_reg_reg[255]_0 [111])); (* SOFT_HLUTNM = "soft_lutpair1276" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[112]_i_1 (.I0(s_axi_wdata[112]), .I1(wready_reg_rep_n_0), .I2(wdf_data[112]), .O(\mc_app_wdf_data_reg_reg[255]_0 [112])); (* SOFT_HLUTNM = "soft_lutpair1277" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[113]_i_1 (.I0(s_axi_wdata[113]), .I1(wready_reg_rep_n_0), .I2(wdf_data[113]), .O(\mc_app_wdf_data_reg_reg[255]_0 [113])); (* SOFT_HLUTNM = "soft_lutpair1278" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[114]_i_1 (.I0(s_axi_wdata[114]), .I1(wready_reg_rep_n_0), .I2(wdf_data[114]), .O(\mc_app_wdf_data_reg_reg[255]_0 [114])); (* SOFT_HLUTNM = "soft_lutpair1279" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[115]_i_1 (.I0(s_axi_wdata[115]), .I1(wready_reg_rep_n_0), .I2(wdf_data[115]), .O(\mc_app_wdf_data_reg_reg[255]_0 [115])); (* SOFT_HLUTNM = "soft_lutpair1280" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[116]_i_1 (.I0(s_axi_wdata[116]), .I1(wready_reg_rep_n_0), .I2(wdf_data[116]), .O(\mc_app_wdf_data_reg_reg[255]_0 [116])); (* SOFT_HLUTNM = "soft_lutpair1281" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[117]_i_1 (.I0(s_axi_wdata[117]), .I1(wready_reg_rep_n_0), .I2(wdf_data[117]), .O(\mc_app_wdf_data_reg_reg[255]_0 [117])); (* SOFT_HLUTNM = "soft_lutpair1282" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[118]_i_1 (.I0(s_axi_wdata[118]), .I1(wready_reg_rep_n_0), .I2(wdf_data[118]), .O(\mc_app_wdf_data_reg_reg[255]_0 [118])); (* SOFT_HLUTNM = "soft_lutpair1283" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[119]_i_1 (.I0(s_axi_wdata[119]), .I1(wready_reg_rep_n_0), .I2(wdf_data[119]), .O(\mc_app_wdf_data_reg_reg[255]_0 [119])); (* SOFT_HLUTNM = "soft_lutpair1175" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[11]_i_1 (.I0(s_axi_wdata[11]), .I1(s_axi_wready), .I2(wdf_data[11]), .O(\mc_app_wdf_data_reg_reg[255]_0 [11])); (* SOFT_HLUTNM = "soft_lutpair1284" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[120]_i_1 (.I0(s_axi_wdata[120]), .I1(wready_reg_rep_n_0), .I2(wdf_data[120]), .O(\mc_app_wdf_data_reg_reg[255]_0 [120])); (* SOFT_HLUTNM = "soft_lutpair1285" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[121]_i_1 (.I0(s_axi_wdata[121]), .I1(wready_reg_rep_n_0), .I2(wdf_data[121]), .O(\mc_app_wdf_data_reg_reg[255]_0 [121])); (* SOFT_HLUTNM = "soft_lutpair1286" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[122]_i_1 (.I0(s_axi_wdata[122]), .I1(wready_reg_rep_n_0), .I2(wdf_data[122]), .O(\mc_app_wdf_data_reg_reg[255]_0 [122])); (* SOFT_HLUTNM = "soft_lutpair1287" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[123]_i_1 (.I0(s_axi_wdata[123]), .I1(wready_reg_rep_n_0), .I2(wdf_data[123]), .O(\mc_app_wdf_data_reg_reg[255]_0 [123])); (* SOFT_HLUTNM = "soft_lutpair1288" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[124]_i_1 (.I0(s_axi_wdata[124]), .I1(wready_reg_rep_n_0), .I2(wdf_data[124]), .O(\mc_app_wdf_data_reg_reg[255]_0 [124])); (* SOFT_HLUTNM = "soft_lutpair1289" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[125]_i_1 (.I0(s_axi_wdata[125]), .I1(wready_reg_rep_n_0), .I2(wdf_data[125]), .O(\mc_app_wdf_data_reg_reg[255]_0 [125])); (* SOFT_HLUTNM = "soft_lutpair1290" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[126]_i_1 (.I0(s_axi_wdata[126]), .I1(wready_reg_rep_n_0), .I2(wdf_data[126]), .O(\mc_app_wdf_data_reg_reg[255]_0 [126])); (* SOFT_HLUTNM = "soft_lutpair1291" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[127]_i_1 (.I0(s_axi_wdata[127]), .I1(wready_reg_rep_n_0), .I2(wdf_data[127]), .O(\mc_app_wdf_data_reg_reg[255]_0 [127])); (* SOFT_HLUTNM = "soft_lutpair1292" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[128]_i_1 (.I0(s_axi_wdata[128]), .I1(wready_reg_rep_n_0), .I2(wdf_data[128]), .O(\mc_app_wdf_data_reg_reg[255]_0 [128])); (* SOFT_HLUTNM = "soft_lutpair1293" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[129]_i_1 (.I0(s_axi_wdata[129]), .I1(wready_reg_rep_n_0), .I2(wdf_data[129]), .O(\mc_app_wdf_data_reg_reg[255]_0 [129])); (* SOFT_HLUTNM = "soft_lutpair1176" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[12]_i_1 (.I0(s_axi_wdata[12]), .I1(s_axi_wready), .I2(wdf_data[12]), .O(\mc_app_wdf_data_reg_reg[255]_0 [12])); (* SOFT_HLUTNM = "soft_lutpair1294" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[130]_i_1 (.I0(s_axi_wdata[130]), .I1(wready_reg_rep_n_0), .I2(wdf_data[130]), .O(\mc_app_wdf_data_reg_reg[255]_0 [130])); (* SOFT_HLUTNM = "soft_lutpair1295" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[131]_i_1 (.I0(s_axi_wdata[131]), .I1(wready_reg_rep_n_0), .I2(wdf_data[131]), .O(\mc_app_wdf_data_reg_reg[255]_0 [131])); (* SOFT_HLUTNM = "soft_lutpair1296" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[132]_i_1 (.I0(s_axi_wdata[132]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[132]), .O(\mc_app_wdf_data_reg_reg[255]_0 [132])); (* SOFT_HLUTNM = "soft_lutpair1297" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[133]_i_1 (.I0(s_axi_wdata[133]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[133]), .O(\mc_app_wdf_data_reg_reg[255]_0 [133])); (* SOFT_HLUTNM = "soft_lutpair1298" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[134]_i_1 (.I0(s_axi_wdata[134]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[134]), .O(\mc_app_wdf_data_reg_reg[255]_0 [134])); (* SOFT_HLUTNM = "soft_lutpair1299" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[135]_i_1 (.I0(s_axi_wdata[135]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[135]), .O(\mc_app_wdf_data_reg_reg[255]_0 [135])); (* SOFT_HLUTNM = "soft_lutpair1300" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[136]_i_1 (.I0(s_axi_wdata[136]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[136]), .O(\mc_app_wdf_data_reg_reg[255]_0 [136])); (* SOFT_HLUTNM = "soft_lutpair1301" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[137]_i_1 (.I0(s_axi_wdata[137]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[137]), .O(\mc_app_wdf_data_reg_reg[255]_0 [137])); (* SOFT_HLUTNM = "soft_lutpair1302" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[138]_i_1 (.I0(s_axi_wdata[138]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[138]), .O(\mc_app_wdf_data_reg_reg[255]_0 [138])); (* SOFT_HLUTNM = "soft_lutpair1303" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[139]_i_1 (.I0(s_axi_wdata[139]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[139]), .O(\mc_app_wdf_data_reg_reg[255]_0 [139])); (* SOFT_HLUTNM = "soft_lutpair1177" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[13]_i_1 (.I0(s_axi_wdata[13]), .I1(s_axi_wready), .I2(wdf_data[13]), .O(\mc_app_wdf_data_reg_reg[255]_0 [13])); (* SOFT_HLUTNM = "soft_lutpair1304" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[140]_i_1 (.I0(s_axi_wdata[140]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[140]), .O(\mc_app_wdf_data_reg_reg[255]_0 [140])); (* SOFT_HLUTNM = "soft_lutpair1305" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[141]_i_1 (.I0(s_axi_wdata[141]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[141]), .O(\mc_app_wdf_data_reg_reg[255]_0 [141])); (* SOFT_HLUTNM = "soft_lutpair1306" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[142]_i_1 (.I0(s_axi_wdata[142]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[142]), .O(\mc_app_wdf_data_reg_reg[255]_0 [142])); (* SOFT_HLUTNM = "soft_lutpair1307" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[143]_i_1 (.I0(s_axi_wdata[143]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[143]), .O(\mc_app_wdf_data_reg_reg[255]_0 [143])); (* SOFT_HLUTNM = "soft_lutpair1308" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[144]_i_1 (.I0(s_axi_wdata[144]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[144]), .O(\mc_app_wdf_data_reg_reg[255]_0 [144])); (* SOFT_HLUTNM = "soft_lutpair1309" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[145]_i_1 (.I0(s_axi_wdata[145]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[145]), .O(\mc_app_wdf_data_reg_reg[255]_0 [145])); (* SOFT_HLUTNM = "soft_lutpair1310" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[146]_i_1 (.I0(s_axi_wdata[146]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[146]), .O(\mc_app_wdf_data_reg_reg[255]_0 [146])); (* SOFT_HLUTNM = "soft_lutpair1311" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[147]_i_1 (.I0(s_axi_wdata[147]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[147]), .O(\mc_app_wdf_data_reg_reg[255]_0 [147])); (* SOFT_HLUTNM = "soft_lutpair1312" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[148]_i_1 (.I0(s_axi_wdata[148]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[148]), .O(\mc_app_wdf_data_reg_reg[255]_0 [148])); (* SOFT_HLUTNM = "soft_lutpair1313" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[149]_i_1 (.I0(s_axi_wdata[149]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[149]), .O(\mc_app_wdf_data_reg_reg[255]_0 [149])); (* SOFT_HLUTNM = "soft_lutpair1178" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[14]_i_1 (.I0(s_axi_wdata[14]), .I1(s_axi_wready), .I2(wdf_data[14]), .O(\mc_app_wdf_data_reg_reg[255]_0 [14])); (* SOFT_HLUTNM = "soft_lutpair1314" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[150]_i_1 (.I0(s_axi_wdata[150]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[150]), .O(\mc_app_wdf_data_reg_reg[255]_0 [150])); (* SOFT_HLUTNM = "soft_lutpair1315" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[151]_i_1 (.I0(s_axi_wdata[151]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[151]), .O(\mc_app_wdf_data_reg_reg[255]_0 [151])); (* SOFT_HLUTNM = "soft_lutpair1316" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[152]_i_1 (.I0(s_axi_wdata[152]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[152]), .O(\mc_app_wdf_data_reg_reg[255]_0 [152])); (* SOFT_HLUTNM = "soft_lutpair1317" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[153]_i_1 (.I0(s_axi_wdata[153]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[153]), .O(\mc_app_wdf_data_reg_reg[255]_0 [153])); (* SOFT_HLUTNM = "soft_lutpair1318" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[154]_i_1 (.I0(s_axi_wdata[154]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[154]), .O(\mc_app_wdf_data_reg_reg[255]_0 [154])); (* SOFT_HLUTNM = "soft_lutpair1319" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[155]_i_1 (.I0(s_axi_wdata[155]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[155]), .O(\mc_app_wdf_data_reg_reg[255]_0 [155])); (* SOFT_HLUTNM = "soft_lutpair1320" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[156]_i_1 (.I0(s_axi_wdata[156]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[156]), .O(\mc_app_wdf_data_reg_reg[255]_0 [156])); (* SOFT_HLUTNM = "soft_lutpair1321" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[157]_i_1 (.I0(s_axi_wdata[157]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[157]), .O(\mc_app_wdf_data_reg_reg[255]_0 [157])); (* SOFT_HLUTNM = "soft_lutpair1322" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[158]_i_1 (.I0(s_axi_wdata[158]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[158]), .O(\mc_app_wdf_data_reg_reg[255]_0 [158])); (* SOFT_HLUTNM = "soft_lutpair1323" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[159]_i_1 (.I0(s_axi_wdata[159]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[159]), .O(\mc_app_wdf_data_reg_reg[255]_0 [159])); (* SOFT_HLUTNM = "soft_lutpair1179" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[15]_i_1 (.I0(s_axi_wdata[15]), .I1(s_axi_wready), .I2(wdf_data[15]), .O(\mc_app_wdf_data_reg_reg[255]_0 [15])); (* SOFT_HLUTNM = "soft_lutpair1324" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[160]_i_1 (.I0(s_axi_wdata[160]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[160]), .O(\mc_app_wdf_data_reg_reg[255]_0 [160])); (* SOFT_HLUTNM = "soft_lutpair1325" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[161]_i_1 (.I0(s_axi_wdata[161]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[161]), .O(\mc_app_wdf_data_reg_reg[255]_0 [161])); (* SOFT_HLUTNM = "soft_lutpair1326" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[162]_i_1 (.I0(s_axi_wdata[162]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[162]), .O(\mc_app_wdf_data_reg_reg[255]_0 [162])); (* SOFT_HLUTNM = "soft_lutpair1327" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[163]_i_1 (.I0(s_axi_wdata[163]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[163]), .O(\mc_app_wdf_data_reg_reg[255]_0 [163])); (* SOFT_HLUTNM = "soft_lutpair1328" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[164]_i_1 (.I0(s_axi_wdata[164]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[164]), .O(\mc_app_wdf_data_reg_reg[255]_0 [164])); (* SOFT_HLUTNM = "soft_lutpair1329" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[165]_i_1 (.I0(s_axi_wdata[165]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[165]), .O(\mc_app_wdf_data_reg_reg[255]_0 [165])); (* SOFT_HLUTNM = "soft_lutpair1330" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[166]_i_1 (.I0(s_axi_wdata[166]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[166]), .O(\mc_app_wdf_data_reg_reg[255]_0 [166])); (* SOFT_HLUTNM = "soft_lutpair1331" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[167]_i_1 (.I0(s_axi_wdata[167]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[167]), .O(\mc_app_wdf_data_reg_reg[255]_0 [167])); (* SOFT_HLUTNM = "soft_lutpair1332" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[168]_i_1 (.I0(s_axi_wdata[168]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[168]), .O(\mc_app_wdf_data_reg_reg[255]_0 [168])); (* SOFT_HLUTNM = "soft_lutpair1333" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[169]_i_1 (.I0(s_axi_wdata[169]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[169]), .O(\mc_app_wdf_data_reg_reg[255]_0 [169])); (* SOFT_HLUTNM = "soft_lutpair1180" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[16]_i_1 (.I0(s_axi_wdata[16]), .I1(s_axi_wready), .I2(wdf_data[16]), .O(\mc_app_wdf_data_reg_reg[255]_0 [16])); (* SOFT_HLUTNM = "soft_lutpair1334" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[170]_i_1 (.I0(s_axi_wdata[170]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[170]), .O(\mc_app_wdf_data_reg_reg[255]_0 [170])); (* SOFT_HLUTNM = "soft_lutpair1335" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[171]_i_1 (.I0(s_axi_wdata[171]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[171]), .O(\mc_app_wdf_data_reg_reg[255]_0 [171])); (* SOFT_HLUTNM = "soft_lutpair1336" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[172]_i_1 (.I0(s_axi_wdata[172]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[172]), .O(\mc_app_wdf_data_reg_reg[255]_0 [172])); (* SOFT_HLUTNM = "soft_lutpair1337" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[173]_i_1 (.I0(s_axi_wdata[173]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[173]), .O(\mc_app_wdf_data_reg_reg[255]_0 [173])); (* SOFT_HLUTNM = "soft_lutpair1338" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[174]_i_1 (.I0(s_axi_wdata[174]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[174]), .O(\mc_app_wdf_data_reg_reg[255]_0 [174])); (* SOFT_HLUTNM = "soft_lutpair1339" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[175]_i_1 (.I0(s_axi_wdata[175]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[175]), .O(\mc_app_wdf_data_reg_reg[255]_0 [175])); (* SOFT_HLUTNM = "soft_lutpair1340" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[176]_i_1 (.I0(s_axi_wdata[176]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[176]), .O(\mc_app_wdf_data_reg_reg[255]_0 [176])); (* SOFT_HLUTNM = "soft_lutpair1341" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[177]_i_1 (.I0(s_axi_wdata[177]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[177]), .O(\mc_app_wdf_data_reg_reg[255]_0 [177])); (* SOFT_HLUTNM = "soft_lutpair1342" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[178]_i_1 (.I0(s_axi_wdata[178]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[178]), .O(\mc_app_wdf_data_reg_reg[255]_0 [178])); (* SOFT_HLUTNM = "soft_lutpair1343" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[179]_i_1 (.I0(s_axi_wdata[179]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[179]), .O(\mc_app_wdf_data_reg_reg[255]_0 [179])); (* SOFT_HLUTNM = "soft_lutpair1181" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[17]_i_1 (.I0(s_axi_wdata[17]), .I1(s_axi_wready), .I2(wdf_data[17]), .O(\mc_app_wdf_data_reg_reg[255]_0 [17])); (* SOFT_HLUTNM = "soft_lutpair1344" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[180]_i_1 (.I0(s_axi_wdata[180]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[180]), .O(\mc_app_wdf_data_reg_reg[255]_0 [180])); (* SOFT_HLUTNM = "soft_lutpair1345" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[181]_i_1 (.I0(s_axi_wdata[181]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[181]), .O(\mc_app_wdf_data_reg_reg[255]_0 [181])); (* SOFT_HLUTNM = "soft_lutpair1346" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[182]_i_1 (.I0(s_axi_wdata[182]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[182]), .O(\mc_app_wdf_data_reg_reg[255]_0 [182])); (* SOFT_HLUTNM = "soft_lutpair1347" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[183]_i_1 (.I0(s_axi_wdata[183]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[183]), .O(\mc_app_wdf_data_reg_reg[255]_0 [183])); (* SOFT_HLUTNM = "soft_lutpair1348" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[184]_i_1 (.I0(s_axi_wdata[184]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[184]), .O(\mc_app_wdf_data_reg_reg[255]_0 [184])); (* SOFT_HLUTNM = "soft_lutpair1349" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[185]_i_1 (.I0(s_axi_wdata[185]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[185]), .O(\mc_app_wdf_data_reg_reg[255]_0 [185])); (* SOFT_HLUTNM = "soft_lutpair1350" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[186]_i_1 (.I0(s_axi_wdata[186]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[186]), .O(\mc_app_wdf_data_reg_reg[255]_0 [186])); (* SOFT_HLUTNM = "soft_lutpair1351" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[187]_i_1 (.I0(s_axi_wdata[187]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[187]), .O(\mc_app_wdf_data_reg_reg[255]_0 [187])); (* SOFT_HLUTNM = "soft_lutpair1352" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[188]_i_1 (.I0(s_axi_wdata[188]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[188]), .O(\mc_app_wdf_data_reg_reg[255]_0 [188])); (* SOFT_HLUTNM = "soft_lutpair1353" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[189]_i_1 (.I0(s_axi_wdata[189]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[189]), .O(\mc_app_wdf_data_reg_reg[255]_0 [189])); (* SOFT_HLUTNM = "soft_lutpair1182" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[18]_i_1 (.I0(s_axi_wdata[18]), .I1(s_axi_wready), .I2(wdf_data[18]), .O(\mc_app_wdf_data_reg_reg[255]_0 [18])); (* SOFT_HLUTNM = "soft_lutpair1354" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[190]_i_1 (.I0(s_axi_wdata[190]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[190]), .O(\mc_app_wdf_data_reg_reg[255]_0 [190])); (* SOFT_HLUTNM = "soft_lutpair1355" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[191]_i_1 (.I0(s_axi_wdata[191]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[191]), .O(\mc_app_wdf_data_reg_reg[255]_0 [191])); (* SOFT_HLUTNM = "soft_lutpair1356" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[192]_i_1 (.I0(s_axi_wdata[192]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[192]), .O(\mc_app_wdf_data_reg_reg[255]_0 [192])); (* SOFT_HLUTNM = "soft_lutpair1357" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[193]_i_1 (.I0(s_axi_wdata[193]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[193]), .O(\mc_app_wdf_data_reg_reg[255]_0 [193])); (* SOFT_HLUTNM = "soft_lutpair1358" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[194]_i_1 (.I0(s_axi_wdata[194]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[194]), .O(\mc_app_wdf_data_reg_reg[255]_0 [194])); (* SOFT_HLUTNM = "soft_lutpair1359" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[195]_i_1 (.I0(s_axi_wdata[195]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[195]), .O(\mc_app_wdf_data_reg_reg[255]_0 [195])); (* SOFT_HLUTNM = "soft_lutpair1360" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[196]_i_1 (.I0(s_axi_wdata[196]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[196]), .O(\mc_app_wdf_data_reg_reg[255]_0 [196])); (* SOFT_HLUTNM = "soft_lutpair1361" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[197]_i_1 (.I0(s_axi_wdata[197]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[197]), .O(\mc_app_wdf_data_reg_reg[255]_0 [197])); (* SOFT_HLUTNM = "soft_lutpair1362" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[198]_i_1 (.I0(s_axi_wdata[198]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[198]), .O(\mc_app_wdf_data_reg_reg[255]_0 [198])); (* SOFT_HLUTNM = "soft_lutpair1363" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[199]_i_1 (.I0(s_axi_wdata[199]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[199]), .O(\mc_app_wdf_data_reg_reg[255]_0 [199])); (* SOFT_HLUTNM = "soft_lutpair1183" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[19]_i_1 (.I0(s_axi_wdata[19]), .I1(s_axi_wready), .I2(wdf_data[19]), .O(\mc_app_wdf_data_reg_reg[255]_0 [19])); (* SOFT_HLUTNM = "soft_lutpair1165" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[1]_i_1 (.I0(s_axi_wdata[1]), .I1(s_axi_wready), .I2(wdf_data[1]), .O(\mc_app_wdf_data_reg_reg[255]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair1364" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[200]_i_1 (.I0(s_axi_wdata[200]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[200]), .O(\mc_app_wdf_data_reg_reg[255]_0 [200])); (* SOFT_HLUTNM = "soft_lutpair1365" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[201]_i_1 (.I0(s_axi_wdata[201]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[201]), .O(\mc_app_wdf_data_reg_reg[255]_0 [201])); (* SOFT_HLUTNM = "soft_lutpair1366" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[202]_i_1 (.I0(s_axi_wdata[202]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[202]), .O(\mc_app_wdf_data_reg_reg[255]_0 [202])); (* SOFT_HLUTNM = "soft_lutpair1367" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[203]_i_1 (.I0(s_axi_wdata[203]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[203]), .O(\mc_app_wdf_data_reg_reg[255]_0 [203])); (* SOFT_HLUTNM = "soft_lutpair1368" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[204]_i_1 (.I0(s_axi_wdata[204]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[204]), .O(\mc_app_wdf_data_reg_reg[255]_0 [204])); (* SOFT_HLUTNM = "soft_lutpair1369" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[205]_i_1 (.I0(s_axi_wdata[205]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[205]), .O(\mc_app_wdf_data_reg_reg[255]_0 [205])); (* SOFT_HLUTNM = "soft_lutpair1370" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[206]_i_1 (.I0(s_axi_wdata[206]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[206]), .O(\mc_app_wdf_data_reg_reg[255]_0 [206])); (* SOFT_HLUTNM = "soft_lutpair1371" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[207]_i_1 (.I0(s_axi_wdata[207]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[207]), .O(\mc_app_wdf_data_reg_reg[255]_0 [207])); (* SOFT_HLUTNM = "soft_lutpair1372" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[208]_i_1 (.I0(s_axi_wdata[208]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[208]), .O(\mc_app_wdf_data_reg_reg[255]_0 [208])); (* SOFT_HLUTNM = "soft_lutpair1373" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[209]_i_1 (.I0(s_axi_wdata[209]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[209]), .O(\mc_app_wdf_data_reg_reg[255]_0 [209])); (* SOFT_HLUTNM = "soft_lutpair1184" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[20]_i_1 (.I0(s_axi_wdata[20]), .I1(s_axi_wready), .I2(wdf_data[20]), .O(\mc_app_wdf_data_reg_reg[255]_0 [20])); (* SOFT_HLUTNM = "soft_lutpair1374" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[210]_i_1 (.I0(s_axi_wdata[210]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[210]), .O(\mc_app_wdf_data_reg_reg[255]_0 [210])); (* SOFT_HLUTNM = "soft_lutpair1375" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[211]_i_1 (.I0(s_axi_wdata[211]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[211]), .O(\mc_app_wdf_data_reg_reg[255]_0 [211])); (* SOFT_HLUTNM = "soft_lutpair1376" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[212]_i_1 (.I0(s_axi_wdata[212]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[212]), .O(\mc_app_wdf_data_reg_reg[255]_0 [212])); (* SOFT_HLUTNM = "soft_lutpair1377" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[213]_i_1 (.I0(s_axi_wdata[213]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[213]), .O(\mc_app_wdf_data_reg_reg[255]_0 [213])); (* SOFT_HLUTNM = "soft_lutpair1378" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[214]_i_1 (.I0(s_axi_wdata[214]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[214]), .O(\mc_app_wdf_data_reg_reg[255]_0 [214])); (* SOFT_HLUTNM = "soft_lutpair1379" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[215]_i_1 (.I0(s_axi_wdata[215]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[215]), .O(\mc_app_wdf_data_reg_reg[255]_0 [215])); (* SOFT_HLUTNM = "soft_lutpair1380" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[216]_i_1 (.I0(s_axi_wdata[216]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[216]), .O(\mc_app_wdf_data_reg_reg[255]_0 [216])); (* SOFT_HLUTNM = "soft_lutpair1381" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[217]_i_1 (.I0(s_axi_wdata[217]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[217]), .O(\mc_app_wdf_data_reg_reg[255]_0 [217])); (* SOFT_HLUTNM = "soft_lutpair1382" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[218]_i_1 (.I0(s_axi_wdata[218]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[218]), .O(\mc_app_wdf_data_reg_reg[255]_0 [218])); (* SOFT_HLUTNM = "soft_lutpair1383" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[219]_i_1 (.I0(s_axi_wdata[219]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[219]), .O(\mc_app_wdf_data_reg_reg[255]_0 [219])); (* SOFT_HLUTNM = "soft_lutpair1185" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[21]_i_1 (.I0(s_axi_wdata[21]), .I1(s_axi_wready), .I2(wdf_data[21]), .O(\mc_app_wdf_data_reg_reg[255]_0 [21])); (* SOFT_HLUTNM = "soft_lutpair1384" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[220]_i_1 (.I0(s_axi_wdata[220]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[220]), .O(\mc_app_wdf_data_reg_reg[255]_0 [220])); (* SOFT_HLUTNM = "soft_lutpair1385" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[221]_i_1 (.I0(s_axi_wdata[221]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[221]), .O(\mc_app_wdf_data_reg_reg[255]_0 [221])); (* SOFT_HLUTNM = "soft_lutpair1386" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[222]_i_1 (.I0(s_axi_wdata[222]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[222]), .O(\mc_app_wdf_data_reg_reg[255]_0 [222])); (* SOFT_HLUTNM = "soft_lutpair1387" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[223]_i_1 (.I0(s_axi_wdata[223]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[223]), .O(\mc_app_wdf_data_reg_reg[255]_0 [223])); (* SOFT_HLUTNM = "soft_lutpair1388" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[224]_i_1 (.I0(s_axi_wdata[224]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[224]), .O(\mc_app_wdf_data_reg_reg[255]_0 [224])); (* SOFT_HLUTNM = "soft_lutpair1389" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[225]_i_1 (.I0(s_axi_wdata[225]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[225]), .O(\mc_app_wdf_data_reg_reg[255]_0 [225])); (* SOFT_HLUTNM = "soft_lutpair1390" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[226]_i_1 (.I0(s_axi_wdata[226]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[226]), .O(\mc_app_wdf_data_reg_reg[255]_0 [226])); (* SOFT_HLUTNM = "soft_lutpair1391" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[227]_i_1 (.I0(s_axi_wdata[227]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[227]), .O(\mc_app_wdf_data_reg_reg[255]_0 [227])); (* SOFT_HLUTNM = "soft_lutpair1392" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[228]_i_1 (.I0(s_axi_wdata[228]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[228]), .O(\mc_app_wdf_data_reg_reg[255]_0 [228])); (* SOFT_HLUTNM = "soft_lutpair1393" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[229]_i_1 (.I0(s_axi_wdata[229]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[229]), .O(\mc_app_wdf_data_reg_reg[255]_0 [229])); (* SOFT_HLUTNM = "soft_lutpair1186" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[22]_i_1 (.I0(s_axi_wdata[22]), .I1(s_axi_wready), .I2(wdf_data[22]), .O(\mc_app_wdf_data_reg_reg[255]_0 [22])); (* SOFT_HLUTNM = "soft_lutpair1394" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[230]_i_1 (.I0(s_axi_wdata[230]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[230]), .O(\mc_app_wdf_data_reg_reg[255]_0 [230])); (* SOFT_HLUTNM = "soft_lutpair1395" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[231]_i_1 (.I0(s_axi_wdata[231]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[231]), .O(\mc_app_wdf_data_reg_reg[255]_0 [231])); (* SOFT_HLUTNM = "soft_lutpair1396" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[232]_i_1 (.I0(s_axi_wdata[232]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[232]), .O(\mc_app_wdf_data_reg_reg[255]_0 [232])); (* SOFT_HLUTNM = "soft_lutpair1397" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[233]_i_1 (.I0(s_axi_wdata[233]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[233]), .O(\mc_app_wdf_data_reg_reg[255]_0 [233])); (* SOFT_HLUTNM = "soft_lutpair1398" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[234]_i_1 (.I0(s_axi_wdata[234]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[234]), .O(\mc_app_wdf_data_reg_reg[255]_0 [234])); (* SOFT_HLUTNM = "soft_lutpair1399" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[235]_i_1 (.I0(s_axi_wdata[235]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[235]), .O(\mc_app_wdf_data_reg_reg[255]_0 [235])); (* SOFT_HLUTNM = "soft_lutpair1400" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[236]_i_1 (.I0(s_axi_wdata[236]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[236]), .O(\mc_app_wdf_data_reg_reg[255]_0 [236])); (* SOFT_HLUTNM = "soft_lutpair1401" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[237]_i_1 (.I0(s_axi_wdata[237]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[237]), .O(\mc_app_wdf_data_reg_reg[255]_0 [237])); (* SOFT_HLUTNM = "soft_lutpair1402" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[238]_i_1 (.I0(s_axi_wdata[238]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[238]), .O(\mc_app_wdf_data_reg_reg[255]_0 [238])); (* SOFT_HLUTNM = "soft_lutpair1403" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[239]_i_1 (.I0(s_axi_wdata[239]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[239]), .O(\mc_app_wdf_data_reg_reg[255]_0 [239])); (* SOFT_HLUTNM = "soft_lutpair1187" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[23]_i_1 (.I0(s_axi_wdata[23]), .I1(s_axi_wready), .I2(wdf_data[23]), .O(\mc_app_wdf_data_reg_reg[255]_0 [23])); (* SOFT_HLUTNM = "soft_lutpair1404" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[240]_i_1 (.I0(s_axi_wdata[240]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[240]), .O(\mc_app_wdf_data_reg_reg[255]_0 [240])); (* SOFT_HLUTNM = "soft_lutpair1405" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[241]_i_1 (.I0(s_axi_wdata[241]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[241]), .O(\mc_app_wdf_data_reg_reg[255]_0 [241])); (* SOFT_HLUTNM = "soft_lutpair1406" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[242]_i_1 (.I0(s_axi_wdata[242]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[242]), .O(\mc_app_wdf_data_reg_reg[255]_0 [242])); (* SOFT_HLUTNM = "soft_lutpair1407" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[243]_i_1 (.I0(s_axi_wdata[243]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[243]), .O(\mc_app_wdf_data_reg_reg[255]_0 [243])); (* SOFT_HLUTNM = "soft_lutpair1408" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[244]_i_1 (.I0(s_axi_wdata[244]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[244]), .O(\mc_app_wdf_data_reg_reg[255]_0 [244])); (* SOFT_HLUTNM = "soft_lutpair1409" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[245]_i_1 (.I0(s_axi_wdata[245]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[245]), .O(\mc_app_wdf_data_reg_reg[255]_0 [245])); (* SOFT_HLUTNM = "soft_lutpair1410" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[246]_i_1 (.I0(s_axi_wdata[246]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[246]), .O(\mc_app_wdf_data_reg_reg[255]_0 [246])); (* SOFT_HLUTNM = "soft_lutpair1411" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[247]_i_1 (.I0(s_axi_wdata[247]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[247]), .O(\mc_app_wdf_data_reg_reg[255]_0 [247])); (* SOFT_HLUTNM = "soft_lutpair1412" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[248]_i_1 (.I0(s_axi_wdata[248]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[248]), .O(\mc_app_wdf_data_reg_reg[255]_0 [248])); (* SOFT_HLUTNM = "soft_lutpair1413" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[249]_i_1 (.I0(s_axi_wdata[249]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[249]), .O(\mc_app_wdf_data_reg_reg[255]_0 [249])); (* SOFT_HLUTNM = "soft_lutpair1188" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[24]_i_1 (.I0(s_axi_wdata[24]), .I1(s_axi_wready), .I2(wdf_data[24]), .O(\mc_app_wdf_data_reg_reg[255]_0 [24])); (* SOFT_HLUTNM = "soft_lutpair1414" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[250]_i_1 (.I0(s_axi_wdata[250]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[250]), .O(\mc_app_wdf_data_reg_reg[255]_0 [250])); (* SOFT_HLUTNM = "soft_lutpair1415" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[251]_i_1 (.I0(s_axi_wdata[251]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[251]), .O(\mc_app_wdf_data_reg_reg[255]_0 [251])); (* SOFT_HLUTNM = "soft_lutpair1416" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[252]_i_1 (.I0(s_axi_wdata[252]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[252]), .O(\mc_app_wdf_data_reg_reg[255]_0 [252])); (* SOFT_HLUTNM = "soft_lutpair1417" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[253]_i_1 (.I0(s_axi_wdata[253]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[253]), .O(\mc_app_wdf_data_reg_reg[255]_0 [253])); (* SOFT_HLUTNM = "soft_lutpair1418" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[254]_i_1 (.I0(s_axi_wdata[254]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[254]), .O(\mc_app_wdf_data_reg_reg[255]_0 [254])); (* SOFT_HLUTNM = "soft_lutpair1419" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[255]_i_1 (.I0(s_axi_wdata[255]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[255]), .O(\mc_app_wdf_data_reg_reg[255]_0 [255])); (* SOFT_HLUTNM = "soft_lutpair1189" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[25]_i_1 (.I0(s_axi_wdata[25]), .I1(s_axi_wready), .I2(wdf_data[25]), .O(\mc_app_wdf_data_reg_reg[255]_0 [25])); (* SOFT_HLUTNM = "soft_lutpair1190" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[26]_i_1 (.I0(s_axi_wdata[26]), .I1(s_axi_wready), .I2(wdf_data[26]), .O(\mc_app_wdf_data_reg_reg[255]_0 [26])); (* SOFT_HLUTNM = "soft_lutpair1191" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[27]_i_1 (.I0(s_axi_wdata[27]), .I1(s_axi_wready), .I2(wdf_data[27]), .O(\mc_app_wdf_data_reg_reg[255]_0 [27])); (* SOFT_HLUTNM = "soft_lutpair1192" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[28]_i_1 (.I0(s_axi_wdata[28]), .I1(s_axi_wready), .I2(wdf_data[28]), .O(\mc_app_wdf_data_reg_reg[255]_0 [28])); (* SOFT_HLUTNM = "soft_lutpair1193" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[29]_i_1 (.I0(s_axi_wdata[29]), .I1(s_axi_wready), .I2(wdf_data[29]), .O(\mc_app_wdf_data_reg_reg[255]_0 [29])); (* SOFT_HLUTNM = "soft_lutpair1166" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[2]_i_1 (.I0(s_axi_wdata[2]), .I1(s_axi_wready), .I2(wdf_data[2]), .O(\mc_app_wdf_data_reg_reg[255]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair1194" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[30]_i_1 (.I0(s_axi_wdata[30]), .I1(s_axi_wready), .I2(wdf_data[30]), .O(\mc_app_wdf_data_reg_reg[255]_0 [30])); (* SOFT_HLUTNM = "soft_lutpair1195" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[31]_i_1 (.I0(s_axi_wdata[31]), .I1(s_axi_wready), .I2(wdf_data[31]), .O(\mc_app_wdf_data_reg_reg[255]_0 [31])); (* SOFT_HLUTNM = "soft_lutpair1196" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[32]_i_1 (.I0(s_axi_wdata[32]), .I1(s_axi_wready), .I2(wdf_data[32]), .O(\mc_app_wdf_data_reg_reg[255]_0 [32])); (* SOFT_HLUTNM = "soft_lutpair1197" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[33]_i_1 (.I0(s_axi_wdata[33]), .I1(s_axi_wready), .I2(wdf_data[33]), .O(\mc_app_wdf_data_reg_reg[255]_0 [33])); (* SOFT_HLUTNM = "soft_lutpair1198" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[34]_i_1 (.I0(s_axi_wdata[34]), .I1(s_axi_wready), .I2(wdf_data[34]), .O(\mc_app_wdf_data_reg_reg[255]_0 [34])); (* SOFT_HLUTNM = "soft_lutpair1199" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[35]_i_1 (.I0(s_axi_wdata[35]), .I1(s_axi_wready), .I2(wdf_data[35]), .O(\mc_app_wdf_data_reg_reg[255]_0 [35])); (* SOFT_HLUTNM = "soft_lutpair1200" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[36]_i_1 (.I0(s_axi_wdata[36]), .I1(s_axi_wready), .I2(wdf_data[36]), .O(\mc_app_wdf_data_reg_reg[255]_0 [36])); (* SOFT_HLUTNM = "soft_lutpair1201" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[37]_i_1 (.I0(s_axi_wdata[37]), .I1(s_axi_wready), .I2(wdf_data[37]), .O(\mc_app_wdf_data_reg_reg[255]_0 [37])); (* SOFT_HLUTNM = "soft_lutpair1202" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[38]_i_1 (.I0(s_axi_wdata[38]), .I1(s_axi_wready), .I2(wdf_data[38]), .O(\mc_app_wdf_data_reg_reg[255]_0 [38])); (* SOFT_HLUTNM = "soft_lutpair1203" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[39]_i_1 (.I0(s_axi_wdata[39]), .I1(s_axi_wready), .I2(wdf_data[39]), .O(\mc_app_wdf_data_reg_reg[255]_0 [39])); (* SOFT_HLUTNM = "soft_lutpair1167" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[3]_i_1 (.I0(s_axi_wdata[3]), .I1(s_axi_wready), .I2(wdf_data[3]), .O(\mc_app_wdf_data_reg_reg[255]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair1204" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[40]_i_1 (.I0(s_axi_wdata[40]), .I1(s_axi_wready), .I2(wdf_data[40]), .O(\mc_app_wdf_data_reg_reg[255]_0 [40])); (* SOFT_HLUTNM = "soft_lutpair1205" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[41]_i_1 (.I0(s_axi_wdata[41]), .I1(s_axi_wready), .I2(wdf_data[41]), .O(\mc_app_wdf_data_reg_reg[255]_0 [41])); (* SOFT_HLUTNM = "soft_lutpair1206" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[42]_i_1 (.I0(s_axi_wdata[42]), .I1(s_axi_wready), .I2(wdf_data[42]), .O(\mc_app_wdf_data_reg_reg[255]_0 [42])); (* SOFT_HLUTNM = "soft_lutpair1207" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[43]_i_1 (.I0(s_axi_wdata[43]), .I1(s_axi_wready), .I2(wdf_data[43]), .O(\mc_app_wdf_data_reg_reg[255]_0 [43])); (* SOFT_HLUTNM = "soft_lutpair1208" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[44]_i_1 (.I0(s_axi_wdata[44]), .I1(s_axi_wready), .I2(wdf_data[44]), .O(\mc_app_wdf_data_reg_reg[255]_0 [44])); (* SOFT_HLUTNM = "soft_lutpair1209" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[45]_i_1 (.I0(s_axi_wdata[45]), .I1(s_axi_wready), .I2(wdf_data[45]), .O(\mc_app_wdf_data_reg_reg[255]_0 [45])); (* SOFT_HLUTNM = "soft_lutpair1210" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[46]_i_1 (.I0(s_axi_wdata[46]), .I1(s_axi_wready), .I2(wdf_data[46]), .O(\mc_app_wdf_data_reg_reg[255]_0 [46])); (* SOFT_HLUTNM = "soft_lutpair1211" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[47]_i_1 (.I0(s_axi_wdata[47]), .I1(s_axi_wready), .I2(wdf_data[47]), .O(\mc_app_wdf_data_reg_reg[255]_0 [47])); (* SOFT_HLUTNM = "soft_lutpair1212" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[48]_i_1 (.I0(s_axi_wdata[48]), .I1(s_axi_wready), .I2(wdf_data[48]), .O(\mc_app_wdf_data_reg_reg[255]_0 [48])); (* SOFT_HLUTNM = "soft_lutpair1213" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[49]_i_1 (.I0(s_axi_wdata[49]), .I1(s_axi_wready), .I2(wdf_data[49]), .O(\mc_app_wdf_data_reg_reg[255]_0 [49])); (* SOFT_HLUTNM = "soft_lutpair1168" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[4]_i_1 (.I0(s_axi_wdata[4]), .I1(s_axi_wready), .I2(wdf_data[4]), .O(\mc_app_wdf_data_reg_reg[255]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair1214" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[50]_i_1 (.I0(s_axi_wdata[50]), .I1(s_axi_wready), .I2(wdf_data[50]), .O(\mc_app_wdf_data_reg_reg[255]_0 [50])); (* SOFT_HLUTNM = "soft_lutpair1215" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[51]_i_1 (.I0(s_axi_wdata[51]), .I1(s_axi_wready), .I2(wdf_data[51]), .O(\mc_app_wdf_data_reg_reg[255]_0 [51])); (* SOFT_HLUTNM = "soft_lutpair1216" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[52]_i_1 (.I0(s_axi_wdata[52]), .I1(s_axi_wready), .I2(wdf_data[52]), .O(\mc_app_wdf_data_reg_reg[255]_0 [52])); (* SOFT_HLUTNM = "soft_lutpair1217" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[53]_i_1 (.I0(s_axi_wdata[53]), .I1(s_axi_wready), .I2(wdf_data[53]), .O(\mc_app_wdf_data_reg_reg[255]_0 [53])); (* SOFT_HLUTNM = "soft_lutpair1218" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[54]_i_1 (.I0(s_axi_wdata[54]), .I1(s_axi_wready), .I2(wdf_data[54]), .O(\mc_app_wdf_data_reg_reg[255]_0 [54])); (* SOFT_HLUTNM = "soft_lutpair1219" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[55]_i_1 (.I0(s_axi_wdata[55]), .I1(s_axi_wready), .I2(wdf_data[55]), .O(\mc_app_wdf_data_reg_reg[255]_0 [55])); (* SOFT_HLUTNM = "soft_lutpair1220" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[56]_i_1 (.I0(s_axi_wdata[56]), .I1(s_axi_wready), .I2(wdf_data[56]), .O(\mc_app_wdf_data_reg_reg[255]_0 [56])); (* SOFT_HLUTNM = "soft_lutpair1221" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[57]_i_1 (.I0(s_axi_wdata[57]), .I1(s_axi_wready), .I2(wdf_data[57]), .O(\mc_app_wdf_data_reg_reg[255]_0 [57])); (* SOFT_HLUTNM = "soft_lutpair1222" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[58]_i_1 (.I0(s_axi_wdata[58]), .I1(s_axi_wready), .I2(wdf_data[58]), .O(\mc_app_wdf_data_reg_reg[255]_0 [58])); (* SOFT_HLUTNM = "soft_lutpair1223" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[59]_i_1 (.I0(s_axi_wdata[59]), .I1(s_axi_wready), .I2(wdf_data[59]), .O(\mc_app_wdf_data_reg_reg[255]_0 [59])); (* SOFT_HLUTNM = "soft_lutpair1169" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[5]_i_1 (.I0(s_axi_wdata[5]), .I1(s_axi_wready), .I2(wdf_data[5]), .O(\mc_app_wdf_data_reg_reg[255]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair1224" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[60]_i_1 (.I0(s_axi_wdata[60]), .I1(s_axi_wready), .I2(wdf_data[60]), .O(\mc_app_wdf_data_reg_reg[255]_0 [60])); (* SOFT_HLUTNM = "soft_lutpair1225" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[61]_i_1 (.I0(s_axi_wdata[61]), .I1(s_axi_wready), .I2(wdf_data[61]), .O(\mc_app_wdf_data_reg_reg[255]_0 [61])); (* SOFT_HLUTNM = "soft_lutpair1226" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[62]_i_1 (.I0(s_axi_wdata[62]), .I1(s_axi_wready), .I2(wdf_data[62]), .O(\mc_app_wdf_data_reg_reg[255]_0 [62])); (* SOFT_HLUTNM = "soft_lutpair1227" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[63]_i_1 (.I0(s_axi_wdata[63]), .I1(s_axi_wready), .I2(wdf_data[63]), .O(\mc_app_wdf_data_reg_reg[255]_0 [63])); (* SOFT_HLUTNM = "soft_lutpair1228" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[64]_i_1 (.I0(s_axi_wdata[64]), .I1(s_axi_wready), .I2(wdf_data[64]), .O(\mc_app_wdf_data_reg_reg[255]_0 [64])); (* SOFT_HLUTNM = "soft_lutpair1229" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[65]_i_1 (.I0(s_axi_wdata[65]), .I1(s_axi_wready), .I2(wdf_data[65]), .O(\mc_app_wdf_data_reg_reg[255]_0 [65])); (* SOFT_HLUTNM = "soft_lutpair1230" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[66]_i_1 (.I0(s_axi_wdata[66]), .I1(wready_reg_rep_n_0), .I2(wdf_data[66]), .O(\mc_app_wdf_data_reg_reg[255]_0 [66])); (* SOFT_HLUTNM = "soft_lutpair1231" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[67]_i_1 (.I0(s_axi_wdata[67]), .I1(wready_reg_rep_n_0), .I2(wdf_data[67]), .O(\mc_app_wdf_data_reg_reg[255]_0 [67])); (* SOFT_HLUTNM = "soft_lutpair1232" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[68]_i_1 (.I0(s_axi_wdata[68]), .I1(wready_reg_rep_n_0), .I2(wdf_data[68]), .O(\mc_app_wdf_data_reg_reg[255]_0 [68])); (* SOFT_HLUTNM = "soft_lutpair1233" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[69]_i_1 (.I0(s_axi_wdata[69]), .I1(wready_reg_rep_n_0), .I2(wdf_data[69]), .O(\mc_app_wdf_data_reg_reg[255]_0 [69])); (* SOFT_HLUTNM = "soft_lutpair1170" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[6]_i_1 (.I0(s_axi_wdata[6]), .I1(s_axi_wready), .I2(wdf_data[6]), .O(\mc_app_wdf_data_reg_reg[255]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair1234" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[70]_i_1 (.I0(s_axi_wdata[70]), .I1(wready_reg_rep_n_0), .I2(wdf_data[70]), .O(\mc_app_wdf_data_reg_reg[255]_0 [70])); (* SOFT_HLUTNM = "soft_lutpair1235" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[71]_i_1 (.I0(s_axi_wdata[71]), .I1(wready_reg_rep_n_0), .I2(wdf_data[71]), .O(\mc_app_wdf_data_reg_reg[255]_0 [71])); (* SOFT_HLUTNM = "soft_lutpair1236" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[72]_i_1 (.I0(s_axi_wdata[72]), .I1(wready_reg_rep_n_0), .I2(wdf_data[72]), .O(\mc_app_wdf_data_reg_reg[255]_0 [72])); (* SOFT_HLUTNM = "soft_lutpair1237" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[73]_i_1 (.I0(s_axi_wdata[73]), .I1(wready_reg_rep_n_0), .I2(wdf_data[73]), .O(\mc_app_wdf_data_reg_reg[255]_0 [73])); (* SOFT_HLUTNM = "soft_lutpair1238" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[74]_i_1 (.I0(s_axi_wdata[74]), .I1(wready_reg_rep_n_0), .I2(wdf_data[74]), .O(\mc_app_wdf_data_reg_reg[255]_0 [74])); (* SOFT_HLUTNM = "soft_lutpair1239" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[75]_i_1 (.I0(s_axi_wdata[75]), .I1(wready_reg_rep_n_0), .I2(wdf_data[75]), .O(\mc_app_wdf_data_reg_reg[255]_0 [75])); (* SOFT_HLUTNM = "soft_lutpair1240" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[76]_i_1 (.I0(s_axi_wdata[76]), .I1(wready_reg_rep_n_0), .I2(wdf_data[76]), .O(\mc_app_wdf_data_reg_reg[255]_0 [76])); (* SOFT_HLUTNM = "soft_lutpair1241" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[77]_i_1 (.I0(s_axi_wdata[77]), .I1(wready_reg_rep_n_0), .I2(wdf_data[77]), .O(\mc_app_wdf_data_reg_reg[255]_0 [77])); (* SOFT_HLUTNM = "soft_lutpair1242" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[78]_i_1 (.I0(s_axi_wdata[78]), .I1(wready_reg_rep_n_0), .I2(wdf_data[78]), .O(\mc_app_wdf_data_reg_reg[255]_0 [78])); (* SOFT_HLUTNM = "soft_lutpair1243" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[79]_i_1 (.I0(s_axi_wdata[79]), .I1(wready_reg_rep_n_0), .I2(wdf_data[79]), .O(\mc_app_wdf_data_reg_reg[255]_0 [79])); (* SOFT_HLUTNM = "soft_lutpair1171" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[7]_i_1 (.I0(s_axi_wdata[7]), .I1(s_axi_wready), .I2(wdf_data[7]), .O(\mc_app_wdf_data_reg_reg[255]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair1244" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[80]_i_1 (.I0(s_axi_wdata[80]), .I1(wready_reg_rep_n_0), .I2(wdf_data[80]), .O(\mc_app_wdf_data_reg_reg[255]_0 [80])); (* SOFT_HLUTNM = "soft_lutpair1245" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[81]_i_1 (.I0(s_axi_wdata[81]), .I1(wready_reg_rep_n_0), .I2(wdf_data[81]), .O(\mc_app_wdf_data_reg_reg[255]_0 [81])); (* SOFT_HLUTNM = "soft_lutpair1246" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[82]_i_1 (.I0(s_axi_wdata[82]), .I1(wready_reg_rep_n_0), .I2(wdf_data[82]), .O(\mc_app_wdf_data_reg_reg[255]_0 [82])); (* SOFT_HLUTNM = "soft_lutpair1247" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[83]_i_1 (.I0(s_axi_wdata[83]), .I1(wready_reg_rep_n_0), .I2(wdf_data[83]), .O(\mc_app_wdf_data_reg_reg[255]_0 [83])); (* SOFT_HLUTNM = "soft_lutpair1248" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[84]_i_1 (.I0(s_axi_wdata[84]), .I1(wready_reg_rep_n_0), .I2(wdf_data[84]), .O(\mc_app_wdf_data_reg_reg[255]_0 [84])); (* SOFT_HLUTNM = "soft_lutpair1249" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[85]_i_1 (.I0(s_axi_wdata[85]), .I1(wready_reg_rep_n_0), .I2(wdf_data[85]), .O(\mc_app_wdf_data_reg_reg[255]_0 [85])); (* SOFT_HLUTNM = "soft_lutpair1250" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[86]_i_1 (.I0(s_axi_wdata[86]), .I1(wready_reg_rep_n_0), .I2(wdf_data[86]), .O(\mc_app_wdf_data_reg_reg[255]_0 [86])); (* SOFT_HLUTNM = "soft_lutpair1251" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[87]_i_1 (.I0(s_axi_wdata[87]), .I1(wready_reg_rep_n_0), .I2(wdf_data[87]), .O(\mc_app_wdf_data_reg_reg[255]_0 [87])); (* SOFT_HLUTNM = "soft_lutpair1252" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[88]_i_1 (.I0(s_axi_wdata[88]), .I1(wready_reg_rep_n_0), .I2(wdf_data[88]), .O(\mc_app_wdf_data_reg_reg[255]_0 [88])); (* SOFT_HLUTNM = "soft_lutpair1253" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[89]_i_1 (.I0(s_axi_wdata[89]), .I1(wready_reg_rep_n_0), .I2(wdf_data[89]), .O(\mc_app_wdf_data_reg_reg[255]_0 [89])); (* SOFT_HLUTNM = "soft_lutpair1172" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[8]_i_1 (.I0(s_axi_wdata[8]), .I1(s_axi_wready), .I2(wdf_data[8]), .O(\mc_app_wdf_data_reg_reg[255]_0 [8])); (* SOFT_HLUTNM = "soft_lutpair1254" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[90]_i_1 (.I0(s_axi_wdata[90]), .I1(wready_reg_rep_n_0), .I2(wdf_data[90]), .O(\mc_app_wdf_data_reg_reg[255]_0 [90])); (* SOFT_HLUTNM = "soft_lutpair1255" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[91]_i_1 (.I0(s_axi_wdata[91]), .I1(wready_reg_rep_n_0), .I2(wdf_data[91]), .O(\mc_app_wdf_data_reg_reg[255]_0 [91])); (* SOFT_HLUTNM = "soft_lutpair1256" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[92]_i_1 (.I0(s_axi_wdata[92]), .I1(wready_reg_rep_n_0), .I2(wdf_data[92]), .O(\mc_app_wdf_data_reg_reg[255]_0 [92])); (* SOFT_HLUTNM = "soft_lutpair1257" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[93]_i_1 (.I0(s_axi_wdata[93]), .I1(wready_reg_rep_n_0), .I2(wdf_data[93]), .O(\mc_app_wdf_data_reg_reg[255]_0 [93])); (* SOFT_HLUTNM = "soft_lutpair1258" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[94]_i_1 (.I0(s_axi_wdata[94]), .I1(wready_reg_rep_n_0), .I2(wdf_data[94]), .O(\mc_app_wdf_data_reg_reg[255]_0 [94])); (* SOFT_HLUTNM = "soft_lutpair1259" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[95]_i_1 (.I0(s_axi_wdata[95]), .I1(wready_reg_rep_n_0), .I2(wdf_data[95]), .O(\mc_app_wdf_data_reg_reg[255]_0 [95])); (* SOFT_HLUTNM = "soft_lutpair1260" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[96]_i_1 (.I0(s_axi_wdata[96]), .I1(wready_reg_rep_n_0), .I2(wdf_data[96]), .O(\mc_app_wdf_data_reg_reg[255]_0 [96])); (* SOFT_HLUTNM = "soft_lutpair1261" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[97]_i_1 (.I0(s_axi_wdata[97]), .I1(wready_reg_rep_n_0), .I2(wdf_data[97]), .O(\mc_app_wdf_data_reg_reg[255]_0 [97])); (* SOFT_HLUTNM = "soft_lutpair1262" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[98]_i_1 (.I0(s_axi_wdata[98]), .I1(wready_reg_rep_n_0), .I2(wdf_data[98]), .O(\mc_app_wdf_data_reg_reg[255]_0 [98])); (* SOFT_HLUTNM = "soft_lutpair1263" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[99]_i_1 (.I0(s_axi_wdata[99]), .I1(wready_reg_rep_n_0), .I2(wdf_data[99]), .O(\mc_app_wdf_data_reg_reg[255]_0 [99])); (* SOFT_HLUTNM = "soft_lutpair1173" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[9]_i_1 (.I0(s_axi_wdata[9]), .I1(s_axi_wready), .I2(wdf_data[9]), .O(\mc_app_wdf_data_reg_reg[255]_0 [9])); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[0] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [0]), .Q(mc_app_wdf_data_reg[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[100] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [100]), .Q(mc_app_wdf_data_reg[100]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[101] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [101]), .Q(mc_app_wdf_data_reg[101]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[102] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [102]), .Q(mc_app_wdf_data_reg[102]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[103] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [103]), .Q(mc_app_wdf_data_reg[103]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[104] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [104]), .Q(mc_app_wdf_data_reg[104]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[105] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [105]), .Q(mc_app_wdf_data_reg[105]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[106] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [106]), .Q(mc_app_wdf_data_reg[106]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[107] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [107]), .Q(mc_app_wdf_data_reg[107]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[108] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [108]), .Q(mc_app_wdf_data_reg[108]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[109] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [109]), .Q(mc_app_wdf_data_reg[109]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[10] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [10]), .Q(mc_app_wdf_data_reg[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[110] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [110]), .Q(mc_app_wdf_data_reg[110]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[111] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [111]), .Q(mc_app_wdf_data_reg[111]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[112] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [112]), .Q(mc_app_wdf_data_reg[112]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[113] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [113]), .Q(mc_app_wdf_data_reg[113]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[114] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [114]), .Q(mc_app_wdf_data_reg[114]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[115] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [115]), .Q(mc_app_wdf_data_reg[115]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[116] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [116]), .Q(mc_app_wdf_data_reg[116]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[117] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [117]), .Q(mc_app_wdf_data_reg[117]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[118] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [118]), .Q(mc_app_wdf_data_reg[118]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[119] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [119]), .Q(mc_app_wdf_data_reg[119]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[11] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [11]), .Q(mc_app_wdf_data_reg[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[120] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [120]), .Q(mc_app_wdf_data_reg[120]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[121] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [121]), .Q(mc_app_wdf_data_reg[121]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[122] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [122]), .Q(mc_app_wdf_data_reg[122]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[123] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [123]), .Q(mc_app_wdf_data_reg[123]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[124] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [124]), .Q(mc_app_wdf_data_reg[124]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[125] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [125]), .Q(mc_app_wdf_data_reg[125]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[126] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [126]), .Q(mc_app_wdf_data_reg[126]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[127] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [127]), .Q(mc_app_wdf_data_reg[127]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[128] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [128]), .Q(mc_app_wdf_data_reg[128]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[129] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [129]), .Q(mc_app_wdf_data_reg[129]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[12] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [12]), .Q(mc_app_wdf_data_reg[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[130] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [130]), .Q(mc_app_wdf_data_reg[130]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[131] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [131]), .Q(mc_app_wdf_data_reg[131]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[132] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [132]), .Q(mc_app_wdf_data_reg[132]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[133] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [133]), .Q(mc_app_wdf_data_reg[133]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[134] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [134]), .Q(mc_app_wdf_data_reg[134]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[135] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [135]), .Q(mc_app_wdf_data_reg[135]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[136] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [136]), .Q(mc_app_wdf_data_reg[136]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[137] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [137]), .Q(mc_app_wdf_data_reg[137]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[138] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [138]), .Q(mc_app_wdf_data_reg[138]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[139] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [139]), .Q(mc_app_wdf_data_reg[139]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[13] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [13]), .Q(mc_app_wdf_data_reg[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[140] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [140]), .Q(mc_app_wdf_data_reg[140]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[141] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [141]), .Q(mc_app_wdf_data_reg[141]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[142] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [142]), .Q(mc_app_wdf_data_reg[142]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[143] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [143]), .Q(mc_app_wdf_data_reg[143]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[144] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [144]), .Q(mc_app_wdf_data_reg[144]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[145] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [145]), .Q(mc_app_wdf_data_reg[145]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[146] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [146]), .Q(mc_app_wdf_data_reg[146]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[147] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [147]), .Q(mc_app_wdf_data_reg[147]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[148] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [148]), .Q(mc_app_wdf_data_reg[148]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[149] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [149]), .Q(mc_app_wdf_data_reg[149]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[14] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [14]), .Q(mc_app_wdf_data_reg[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[150] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [150]), .Q(mc_app_wdf_data_reg[150]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[151] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [151]), .Q(mc_app_wdf_data_reg[151]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[152] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [152]), .Q(mc_app_wdf_data_reg[152]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[153] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [153]), .Q(mc_app_wdf_data_reg[153]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[154] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [154]), .Q(mc_app_wdf_data_reg[154]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[155] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [155]), .Q(mc_app_wdf_data_reg[155]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[156] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [156]), .Q(mc_app_wdf_data_reg[156]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[157] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [157]), .Q(mc_app_wdf_data_reg[157]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[158] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [158]), .Q(mc_app_wdf_data_reg[158]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[159] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [159]), .Q(mc_app_wdf_data_reg[159]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[15] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [15]), .Q(mc_app_wdf_data_reg[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[160] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [160]), .Q(mc_app_wdf_data_reg[160]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[161] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [161]), .Q(mc_app_wdf_data_reg[161]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[162] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [162]), .Q(mc_app_wdf_data_reg[162]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[163] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [163]), .Q(mc_app_wdf_data_reg[163]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[164] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [164]), .Q(mc_app_wdf_data_reg[164]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[165] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [165]), .Q(mc_app_wdf_data_reg[165]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[166] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [166]), .Q(mc_app_wdf_data_reg[166]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[167] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [167]), .Q(mc_app_wdf_data_reg[167]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[168] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [168]), .Q(mc_app_wdf_data_reg[168]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[169] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [169]), .Q(mc_app_wdf_data_reg[169]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[16] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [16]), .Q(mc_app_wdf_data_reg[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[170] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [170]), .Q(mc_app_wdf_data_reg[170]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[171] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [171]), .Q(mc_app_wdf_data_reg[171]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[172] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [172]), .Q(mc_app_wdf_data_reg[172]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[173] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [173]), .Q(mc_app_wdf_data_reg[173]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[174] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [174]), .Q(mc_app_wdf_data_reg[174]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[175] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [175]), .Q(mc_app_wdf_data_reg[175]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[176] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [176]), .Q(mc_app_wdf_data_reg[176]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[177] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [177]), .Q(mc_app_wdf_data_reg[177]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[178] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [178]), .Q(mc_app_wdf_data_reg[178]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[179] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [179]), .Q(mc_app_wdf_data_reg[179]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[17] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [17]), .Q(mc_app_wdf_data_reg[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[180] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [180]), .Q(mc_app_wdf_data_reg[180]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[181] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [181]), .Q(mc_app_wdf_data_reg[181]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[182] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [182]), .Q(mc_app_wdf_data_reg[182]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[183] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [183]), .Q(mc_app_wdf_data_reg[183]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[184] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [184]), .Q(mc_app_wdf_data_reg[184]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[185] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [185]), .Q(mc_app_wdf_data_reg[185]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[186] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [186]), .Q(mc_app_wdf_data_reg[186]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[187] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [187]), .Q(mc_app_wdf_data_reg[187]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[188] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [188]), .Q(mc_app_wdf_data_reg[188]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[189] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [189]), .Q(mc_app_wdf_data_reg[189]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[18] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [18]), .Q(mc_app_wdf_data_reg[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[190] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [190]), .Q(mc_app_wdf_data_reg[190]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[191] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [191]), .Q(mc_app_wdf_data_reg[191]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[192] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [192]), .Q(mc_app_wdf_data_reg[192]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[193] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [193]), .Q(mc_app_wdf_data_reg[193]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[194] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [194]), .Q(mc_app_wdf_data_reg[194]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[195] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [195]), .Q(mc_app_wdf_data_reg[195]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[196] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [196]), .Q(mc_app_wdf_data_reg[196]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[197] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [197]), .Q(mc_app_wdf_data_reg[197]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[198] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [198]), .Q(mc_app_wdf_data_reg[198]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[199] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [199]), .Q(mc_app_wdf_data_reg[199]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[19] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [19]), .Q(mc_app_wdf_data_reg[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[1] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [1]), .Q(mc_app_wdf_data_reg[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[200] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [200]), .Q(mc_app_wdf_data_reg[200]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[201] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [201]), .Q(mc_app_wdf_data_reg[201]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[202] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [202]), .Q(mc_app_wdf_data_reg[202]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[203] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [203]), .Q(mc_app_wdf_data_reg[203]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[204] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [204]), .Q(mc_app_wdf_data_reg[204]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[205] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [205]), .Q(mc_app_wdf_data_reg[205]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[206] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [206]), .Q(mc_app_wdf_data_reg[206]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[207] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [207]), .Q(mc_app_wdf_data_reg[207]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[208] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [208]), .Q(mc_app_wdf_data_reg[208]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[209] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [209]), .Q(mc_app_wdf_data_reg[209]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[20] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [20]), .Q(mc_app_wdf_data_reg[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[210] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [210]), .Q(mc_app_wdf_data_reg[210]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[211] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [211]), .Q(mc_app_wdf_data_reg[211]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[212] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [212]), .Q(mc_app_wdf_data_reg[212]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[213] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [213]), .Q(mc_app_wdf_data_reg[213]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[214] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [214]), .Q(mc_app_wdf_data_reg[214]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[215] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [215]), .Q(mc_app_wdf_data_reg[215]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[216] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [216]), .Q(mc_app_wdf_data_reg[216]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[217] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [217]), .Q(mc_app_wdf_data_reg[217]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[218] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [218]), .Q(mc_app_wdf_data_reg[218]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[219] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [219]), .Q(mc_app_wdf_data_reg[219]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[21] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [21]), .Q(mc_app_wdf_data_reg[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[220] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [220]), .Q(mc_app_wdf_data_reg[220]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[221] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [221]), .Q(mc_app_wdf_data_reg[221]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[222] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [222]), .Q(mc_app_wdf_data_reg[222]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[223] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [223]), .Q(mc_app_wdf_data_reg[223]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[224] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [224]), .Q(mc_app_wdf_data_reg[224]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[225] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [225]), .Q(mc_app_wdf_data_reg[225]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[226] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [226]), .Q(mc_app_wdf_data_reg[226]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[227] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [227]), .Q(mc_app_wdf_data_reg[227]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[228] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [228]), .Q(mc_app_wdf_data_reg[228]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[229] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [229]), .Q(mc_app_wdf_data_reg[229]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[22] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [22]), .Q(mc_app_wdf_data_reg[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[230] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [230]), .Q(mc_app_wdf_data_reg[230]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[231] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [231]), .Q(mc_app_wdf_data_reg[231]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[232] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [232]), .Q(mc_app_wdf_data_reg[232]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[233] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [233]), .Q(mc_app_wdf_data_reg[233]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[234] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [234]), .Q(mc_app_wdf_data_reg[234]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[235] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [235]), .Q(mc_app_wdf_data_reg[235]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[236] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [236]), .Q(mc_app_wdf_data_reg[236]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[237] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [237]), .Q(mc_app_wdf_data_reg[237]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[238] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [238]), .Q(mc_app_wdf_data_reg[238]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[239] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [239]), .Q(mc_app_wdf_data_reg[239]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[23] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [23]), .Q(mc_app_wdf_data_reg[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[240] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [240]), .Q(mc_app_wdf_data_reg[240]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[241] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [241]), .Q(mc_app_wdf_data_reg[241]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[242] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [242]), .Q(mc_app_wdf_data_reg[242]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[243] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [243]), .Q(mc_app_wdf_data_reg[243]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[244] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [244]), .Q(mc_app_wdf_data_reg[244]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[245] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [245]), .Q(mc_app_wdf_data_reg[245]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[246] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [246]), .Q(mc_app_wdf_data_reg[246]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[247] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [247]), .Q(mc_app_wdf_data_reg[247]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[248] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [248]), .Q(mc_app_wdf_data_reg[248]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[249] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [249]), .Q(mc_app_wdf_data_reg[249]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[24] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [24]), .Q(mc_app_wdf_data_reg[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[250] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [250]), .Q(mc_app_wdf_data_reg[250]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[251] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [251]), .Q(mc_app_wdf_data_reg[251]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[252] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [252]), .Q(mc_app_wdf_data_reg[252]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[253] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [253]), .Q(mc_app_wdf_data_reg[253]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[254] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [254]), .Q(mc_app_wdf_data_reg[254]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[255] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [255]), .Q(mc_app_wdf_data_reg[255]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[25] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [25]), .Q(mc_app_wdf_data_reg[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[26] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [26]), .Q(mc_app_wdf_data_reg[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[27] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [27]), .Q(mc_app_wdf_data_reg[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[28] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [28]), .Q(mc_app_wdf_data_reg[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[29] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [29]), .Q(mc_app_wdf_data_reg[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[2] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [2]), .Q(mc_app_wdf_data_reg[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[30] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [30]), .Q(mc_app_wdf_data_reg[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[31] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [31]), .Q(mc_app_wdf_data_reg[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[32] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [32]), .Q(mc_app_wdf_data_reg[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[33] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [33]), .Q(mc_app_wdf_data_reg[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[34] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [34]), .Q(mc_app_wdf_data_reg[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[35] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [35]), .Q(mc_app_wdf_data_reg[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[36] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [36]), .Q(mc_app_wdf_data_reg[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[37] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [37]), .Q(mc_app_wdf_data_reg[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[38] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [38]), .Q(mc_app_wdf_data_reg[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[39] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [39]), .Q(mc_app_wdf_data_reg[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[3] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [3]), .Q(mc_app_wdf_data_reg[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[40] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [40]), .Q(mc_app_wdf_data_reg[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[41] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [41]), .Q(mc_app_wdf_data_reg[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[42] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [42]), .Q(mc_app_wdf_data_reg[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[43] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [43]), .Q(mc_app_wdf_data_reg[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[44] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [44]), .Q(mc_app_wdf_data_reg[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[45] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [45]), .Q(mc_app_wdf_data_reg[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[46] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [46]), .Q(mc_app_wdf_data_reg[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[47] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [47]), .Q(mc_app_wdf_data_reg[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[48] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [48]), .Q(mc_app_wdf_data_reg[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[49] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [49]), .Q(mc_app_wdf_data_reg[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[4] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [4]), .Q(mc_app_wdf_data_reg[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[50] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [50]), .Q(mc_app_wdf_data_reg[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[51] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [51]), .Q(mc_app_wdf_data_reg[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[52] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [52]), .Q(mc_app_wdf_data_reg[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[53] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [53]), .Q(mc_app_wdf_data_reg[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[54] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [54]), .Q(mc_app_wdf_data_reg[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[55] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [55]), .Q(mc_app_wdf_data_reg[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[56] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [56]), .Q(mc_app_wdf_data_reg[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[57] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [57]), .Q(mc_app_wdf_data_reg[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[58] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [58]), .Q(mc_app_wdf_data_reg[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[59] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [59]), .Q(mc_app_wdf_data_reg[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[5] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [5]), .Q(mc_app_wdf_data_reg[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[60] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [60]), .Q(mc_app_wdf_data_reg[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[61] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [61]), .Q(mc_app_wdf_data_reg[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[62] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [62]), .Q(mc_app_wdf_data_reg[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[63] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [63]), .Q(mc_app_wdf_data_reg[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[64] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [64]), .Q(mc_app_wdf_data_reg[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[65] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [65]), .Q(mc_app_wdf_data_reg[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[66] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [66]), .Q(mc_app_wdf_data_reg[66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[67] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [67]), .Q(mc_app_wdf_data_reg[67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[68] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [68]), .Q(mc_app_wdf_data_reg[68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[69] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [69]), .Q(mc_app_wdf_data_reg[69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[6] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [6]), .Q(mc_app_wdf_data_reg[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[70] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [70]), .Q(mc_app_wdf_data_reg[70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[71] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [71]), .Q(mc_app_wdf_data_reg[71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[72] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [72]), .Q(mc_app_wdf_data_reg[72]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[73] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [73]), .Q(mc_app_wdf_data_reg[73]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[74] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [74]), .Q(mc_app_wdf_data_reg[74]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[75] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [75]), .Q(mc_app_wdf_data_reg[75]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[76] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [76]), .Q(mc_app_wdf_data_reg[76]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[77] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [77]), .Q(mc_app_wdf_data_reg[77]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[78] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [78]), .Q(mc_app_wdf_data_reg[78]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[79] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [79]), .Q(mc_app_wdf_data_reg[79]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[7] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [7]), .Q(mc_app_wdf_data_reg[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[80] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [80]), .Q(mc_app_wdf_data_reg[80]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[81] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [81]), .Q(mc_app_wdf_data_reg[81]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[82] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [82]), .Q(mc_app_wdf_data_reg[82]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[83] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [83]), .Q(mc_app_wdf_data_reg[83]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[84] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [84]), .Q(mc_app_wdf_data_reg[84]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[85] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [85]), .Q(mc_app_wdf_data_reg[85]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[86] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [86]), .Q(mc_app_wdf_data_reg[86]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[87] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [87]), .Q(mc_app_wdf_data_reg[87]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[88] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [88]), .Q(mc_app_wdf_data_reg[88]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[89] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [89]), .Q(mc_app_wdf_data_reg[89]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[8] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [8]), .Q(mc_app_wdf_data_reg[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[90] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [90]), .Q(mc_app_wdf_data_reg[90]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[91] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [91]), .Q(mc_app_wdf_data_reg[91]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[92] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [92]), .Q(mc_app_wdf_data_reg[92]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[93] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [93]), .Q(mc_app_wdf_data_reg[93]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[94] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [94]), .Q(mc_app_wdf_data_reg[94]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[95] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [95]), .Q(mc_app_wdf_data_reg[95]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[96] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [96]), .Q(mc_app_wdf_data_reg[96]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[97] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [97]), .Q(mc_app_wdf_data_reg[97]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[98] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [98]), .Q(mc_app_wdf_data_reg[98]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[99] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [99]), .Q(mc_app_wdf_data_reg[99]), .R(1'b0)); FDRE #( .INIT(1'b0)) \mc_app_wdf_data_reg_reg[9] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [9]), .Q(mc_app_wdf_data_reg[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1420" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[0]_i_1 (.I0(s_axi_wstrb[0]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair1430" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[10]_i_1 (.I0(s_axi_wstrb[10]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[10]), .O(D[10])); (* SOFT_HLUTNM = "soft_lutpair1431" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[11]_i_1 (.I0(s_axi_wstrb[11]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[11]), .O(D[11])); (* SOFT_HLUTNM = "soft_lutpair1432" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[12]_i_1 (.I0(s_axi_wstrb[12]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[12]), .O(D[12])); (* SOFT_HLUTNM = "soft_lutpair1433" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[13]_i_1 (.I0(s_axi_wstrb[13]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[13]), .O(D[13])); (* SOFT_HLUTNM = "soft_lutpair1434" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[14]_i_1 (.I0(s_axi_wstrb[14]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[14]), .O(D[14])); (* SOFT_HLUTNM = "soft_lutpair1435" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[15]_i_1 (.I0(s_axi_wstrb[15]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[15]), .O(D[15])); (* SOFT_HLUTNM = "soft_lutpair1436" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[16]_i_1 (.I0(s_axi_wstrb[16]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[16]), .O(D[16])); (* SOFT_HLUTNM = "soft_lutpair1437" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[17]_i_1 (.I0(s_axi_wstrb[17]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[17]), .O(D[17])); (* SOFT_HLUTNM = "soft_lutpair1438" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[18]_i_1 (.I0(s_axi_wstrb[18]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[18]), .O(D[18])); (* SOFT_HLUTNM = "soft_lutpair1439" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[19]_i_1 (.I0(s_axi_wstrb[19]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[19]), .O(D[19])); (* SOFT_HLUTNM = "soft_lutpair1421" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[1]_i_1 (.I0(s_axi_wstrb[1]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[1]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair1440" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[20]_i_1 (.I0(s_axi_wstrb[20]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[20]), .O(D[20])); (* SOFT_HLUTNM = "soft_lutpair1441" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[21]_i_1 (.I0(s_axi_wstrb[21]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[21]), .O(D[21])); (* SOFT_HLUTNM = "soft_lutpair1442" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[22]_i_1 (.I0(s_axi_wstrb[22]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[22]), .O(D[22])); (* SOFT_HLUTNM = "soft_lutpair1443" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[23]_i_1 (.I0(s_axi_wstrb[23]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[23]), .O(D[23])); (* SOFT_HLUTNM = "soft_lutpair1444" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[24]_i_1 (.I0(s_axi_wstrb[24]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[24]), .O(D[24])); (* SOFT_HLUTNM = "soft_lutpair1445" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[25]_i_1 (.I0(s_axi_wstrb[25]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[25]), .O(D[25])); (* SOFT_HLUTNM = "soft_lutpair1446" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[26]_i_1 (.I0(s_axi_wstrb[26]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[26]), .O(D[26])); (* SOFT_HLUTNM = "soft_lutpair1447" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[27]_i_1 (.I0(s_axi_wstrb[27]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[27]), .O(D[27])); (* SOFT_HLUTNM = "soft_lutpair1448" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[28]_i_1 (.I0(s_axi_wstrb[28]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[28]), .O(D[28])); (* SOFT_HLUTNM = "soft_lutpair1449" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[29]_i_1 (.I0(s_axi_wstrb[29]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[29]), .O(D[29])); (* SOFT_HLUTNM = "soft_lutpair1422" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[2]_i_1 (.I0(s_axi_wstrb[2]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[2]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair1450" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[30]_i_1 (.I0(s_axi_wstrb[30]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[30]), .O(D[30])); (* SOFT_HLUTNM = "soft_lutpair1451" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[31]_i_1 (.I0(s_axi_wstrb[31]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[31]), .O(D[31])); (* SOFT_HLUTNM = "soft_lutpair1423" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[3]_i_1 (.I0(s_axi_wstrb[3]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[3]), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair1424" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[4]_i_1 (.I0(s_axi_wstrb[4]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[4]), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair1425" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[5]_i_1 (.I0(s_axi_wstrb[5]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[5]), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair1426" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[6]_i_1 (.I0(s_axi_wstrb[6]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[6]), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair1427" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[7]_i_1 (.I0(s_axi_wstrb[7]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[7]), .O(D[7])); (* SOFT_HLUTNM = "soft_lutpair1428" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[8]_i_1 (.I0(s_axi_wstrb[8]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[8]), .O(D[8])); (* SOFT_HLUTNM = "soft_lutpair1429" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[9]_i_1 (.I0(s_axi_wstrb[9]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[9]), .O(D[9])); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[0] (.C(CLK), .CE(app_wdf_rdy), .D(D[0]), .Q(mc_app_wdf_mask_reg[0]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[10] (.C(CLK), .CE(app_wdf_rdy), .D(D[10]), .Q(mc_app_wdf_mask_reg[10]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[11] (.C(CLK), .CE(app_wdf_rdy), .D(D[11]), .Q(mc_app_wdf_mask_reg[11]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[12] (.C(CLK), .CE(app_wdf_rdy), .D(D[12]), .Q(mc_app_wdf_mask_reg[12]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[13] (.C(CLK), .CE(app_wdf_rdy), .D(D[13]), .Q(mc_app_wdf_mask_reg[13]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[14] (.C(CLK), .CE(app_wdf_rdy), .D(D[14]), .Q(mc_app_wdf_mask_reg[14]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[15] (.C(CLK), .CE(app_wdf_rdy), .D(D[15]), .Q(mc_app_wdf_mask_reg[15]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[16] (.C(CLK), .CE(app_wdf_rdy), .D(D[16]), .Q(mc_app_wdf_mask_reg[16]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[17] (.C(CLK), .CE(app_wdf_rdy), .D(D[17]), .Q(mc_app_wdf_mask_reg[17]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[18] (.C(CLK), .CE(app_wdf_rdy), .D(D[18]), .Q(mc_app_wdf_mask_reg[18]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[19] (.C(CLK), .CE(app_wdf_rdy), .D(D[19]), .Q(mc_app_wdf_mask_reg[19]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[1] (.C(CLK), .CE(app_wdf_rdy), .D(D[1]), .Q(mc_app_wdf_mask_reg[1]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[20] (.C(CLK), .CE(app_wdf_rdy), .D(D[20]), .Q(mc_app_wdf_mask_reg[20]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[21] (.C(CLK), .CE(app_wdf_rdy), .D(D[21]), .Q(mc_app_wdf_mask_reg[21]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[22] (.C(CLK), .CE(app_wdf_rdy), .D(D[22]), .Q(mc_app_wdf_mask_reg[22]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[23] (.C(CLK), .CE(app_wdf_rdy), .D(D[23]), .Q(mc_app_wdf_mask_reg[23]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[24] (.C(CLK), .CE(app_wdf_rdy), .D(D[24]), .Q(mc_app_wdf_mask_reg[24]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[25] (.C(CLK), .CE(app_wdf_rdy), .D(D[25]), .Q(mc_app_wdf_mask_reg[25]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[26] (.C(CLK), .CE(app_wdf_rdy), .D(D[26]), .Q(mc_app_wdf_mask_reg[26]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[27] (.C(CLK), .CE(app_wdf_rdy), .D(D[27]), .Q(mc_app_wdf_mask_reg[27]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[28] (.C(CLK), .CE(app_wdf_rdy), .D(D[28]), .Q(mc_app_wdf_mask_reg[28]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[29] (.C(CLK), .CE(app_wdf_rdy), .D(D[29]), .Q(mc_app_wdf_mask_reg[29]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[2] (.C(CLK), .CE(app_wdf_rdy), .D(D[2]), .Q(mc_app_wdf_mask_reg[2]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[30] (.C(CLK), .CE(app_wdf_rdy), .D(D[30]), .Q(mc_app_wdf_mask_reg[30]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[31] (.C(CLK), .CE(app_wdf_rdy), .D(D[31]), .Q(mc_app_wdf_mask_reg[31]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[3] (.C(CLK), .CE(app_wdf_rdy), .D(D[3]), .Q(mc_app_wdf_mask_reg[3]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[4] (.C(CLK), .CE(app_wdf_rdy), .D(D[4]), .Q(mc_app_wdf_mask_reg[4]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[5] (.C(CLK), .CE(app_wdf_rdy), .D(D[5]), .Q(mc_app_wdf_mask_reg[5]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[6] (.C(CLK), .CE(app_wdf_rdy), .D(D[6]), .Q(mc_app_wdf_mask_reg[6]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[7] (.C(CLK), .CE(app_wdf_rdy), .D(D[7]), .Q(mc_app_wdf_mask_reg[7]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[8] (.C(CLK), .CE(app_wdf_rdy), .D(D[8]), .Q(mc_app_wdf_mask_reg[8]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \mc_app_wdf_mask_reg_reg[9] (.C(CLK), .CE(app_wdf_rdy), .D(D[9]), .Q(mc_app_wdf_mask_reg[9]), .R(areset_d1)); FDRE #( .INIT(1'b0)) mc_app_wdf_wren_reg_reg (.C(CLK), .CE(app_wdf_rdy), .D(\RD_PRI_REG_STARVE.rnw_i_reg ), .Q(mc_app_wdf_wren_reg), .R(areset_d1)); LUT3 #( .INIT(8'hB8)) valid_i_1 (.I0(s_axi_wvalid), .I1(s_axi_wready), .I2(valid), .O(wvalid_int)); FDRE #( .INIT(1'b0)) valid_reg (.C(CLK), .CE(1'b1), .D(wvalid_int), .Q(valid), .R(areset_d1)); FDRE #( .INIT(1'b0)) \wdf_data_reg[0] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [0]), .Q(wdf_data[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[100] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [100]), .Q(wdf_data[100]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[101] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [101]), .Q(wdf_data[101]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[102] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [102]), .Q(wdf_data[102]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[103] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [103]), .Q(wdf_data[103]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[104] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [104]), .Q(wdf_data[104]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[105] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [105]), .Q(wdf_data[105]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[106] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [106]), .Q(wdf_data[106]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[107] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [107]), .Q(wdf_data[107]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[108] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [108]), .Q(wdf_data[108]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[109] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [109]), .Q(wdf_data[109]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[10] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [10]), .Q(wdf_data[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[110] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [110]), .Q(wdf_data[110]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[111] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [111]), .Q(wdf_data[111]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[112] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [112]), .Q(wdf_data[112]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[113] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [113]), .Q(wdf_data[113]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[114] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [114]), .Q(wdf_data[114]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[115] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [115]), .Q(wdf_data[115]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[116] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [116]), .Q(wdf_data[116]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[117] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [117]), .Q(wdf_data[117]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[118] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [118]), .Q(wdf_data[118]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[119] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [119]), .Q(wdf_data[119]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[11] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [11]), .Q(wdf_data[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[120] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [120]), .Q(wdf_data[120]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[121] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [121]), .Q(wdf_data[121]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[122] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [122]), .Q(wdf_data[122]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[123] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [123]), .Q(wdf_data[123]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[124] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [124]), .Q(wdf_data[124]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[125] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [125]), .Q(wdf_data[125]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[126] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [126]), .Q(wdf_data[126]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[127] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [127]), .Q(wdf_data[127]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[128] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [128]), .Q(wdf_data[128]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[129] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [129]), .Q(wdf_data[129]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[12] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [12]), .Q(wdf_data[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[130] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [130]), .Q(wdf_data[130]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[131] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [131]), .Q(wdf_data[131]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[132] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [132]), .Q(wdf_data[132]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[133] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [133]), .Q(wdf_data[133]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[134] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [134]), .Q(wdf_data[134]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[135] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [135]), .Q(wdf_data[135]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[136] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [136]), .Q(wdf_data[136]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[137] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [137]), .Q(wdf_data[137]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[138] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [138]), .Q(wdf_data[138]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[139] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [139]), .Q(wdf_data[139]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[13] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [13]), .Q(wdf_data[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[140] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [140]), .Q(wdf_data[140]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[141] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [141]), .Q(wdf_data[141]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[142] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [142]), .Q(wdf_data[142]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[143] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [143]), .Q(wdf_data[143]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[144] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [144]), .Q(wdf_data[144]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[145] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [145]), .Q(wdf_data[145]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[146] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [146]), .Q(wdf_data[146]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[147] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [147]), .Q(wdf_data[147]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[148] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [148]), .Q(wdf_data[148]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[149] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [149]), .Q(wdf_data[149]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[14] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [14]), .Q(wdf_data[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[150] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [150]), .Q(wdf_data[150]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[151] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [151]), .Q(wdf_data[151]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[152] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [152]), .Q(wdf_data[152]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[153] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [153]), .Q(wdf_data[153]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[154] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [154]), .Q(wdf_data[154]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[155] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [155]), .Q(wdf_data[155]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[156] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [156]), .Q(wdf_data[156]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[157] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [157]), .Q(wdf_data[157]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[158] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [158]), .Q(wdf_data[158]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[159] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [159]), .Q(wdf_data[159]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[15] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [15]), .Q(wdf_data[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[160] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [160]), .Q(wdf_data[160]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[161] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [161]), .Q(wdf_data[161]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[162] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [162]), .Q(wdf_data[162]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[163] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [163]), .Q(wdf_data[163]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[164] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [164]), .Q(wdf_data[164]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[165] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [165]), .Q(wdf_data[165]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[166] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [166]), .Q(wdf_data[166]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[167] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [167]), .Q(wdf_data[167]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[168] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [168]), .Q(wdf_data[168]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[169] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [169]), .Q(wdf_data[169]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[16] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [16]), .Q(wdf_data[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[170] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [170]), .Q(wdf_data[170]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[171] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [171]), .Q(wdf_data[171]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[172] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [172]), .Q(wdf_data[172]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[173] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [173]), .Q(wdf_data[173]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[174] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [174]), .Q(wdf_data[174]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[175] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [175]), .Q(wdf_data[175]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[176] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [176]), .Q(wdf_data[176]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[177] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [177]), .Q(wdf_data[177]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[178] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [178]), .Q(wdf_data[178]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[179] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [179]), .Q(wdf_data[179]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[17] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [17]), .Q(wdf_data[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[180] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [180]), .Q(wdf_data[180]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[181] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [181]), .Q(wdf_data[181]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[182] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [182]), .Q(wdf_data[182]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[183] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [183]), .Q(wdf_data[183]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[184] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [184]), .Q(wdf_data[184]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[185] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [185]), .Q(wdf_data[185]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[186] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [186]), .Q(wdf_data[186]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[187] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [187]), .Q(wdf_data[187]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[188] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [188]), .Q(wdf_data[188]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[189] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [189]), .Q(wdf_data[189]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[18] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [18]), .Q(wdf_data[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[190] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [190]), .Q(wdf_data[190]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[191] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [191]), .Q(wdf_data[191]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[192] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [192]), .Q(wdf_data[192]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[193] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [193]), .Q(wdf_data[193]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[194] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [194]), .Q(wdf_data[194]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[195] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [195]), .Q(wdf_data[195]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[196] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [196]), .Q(wdf_data[196]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[197] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [197]), .Q(wdf_data[197]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[198] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [198]), .Q(wdf_data[198]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[199] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [199]), .Q(wdf_data[199]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[19] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [19]), .Q(wdf_data[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[1] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [1]), .Q(wdf_data[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[200] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [200]), .Q(wdf_data[200]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[201] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [201]), .Q(wdf_data[201]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[202] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [202]), .Q(wdf_data[202]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[203] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [203]), .Q(wdf_data[203]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[204] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [204]), .Q(wdf_data[204]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[205] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [205]), .Q(wdf_data[205]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[206] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [206]), .Q(wdf_data[206]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[207] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [207]), .Q(wdf_data[207]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[208] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [208]), .Q(wdf_data[208]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[209] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [209]), .Q(wdf_data[209]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[20] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [20]), .Q(wdf_data[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[210] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [210]), .Q(wdf_data[210]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[211] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [211]), .Q(wdf_data[211]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[212] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [212]), .Q(wdf_data[212]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[213] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [213]), .Q(wdf_data[213]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[214] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [214]), .Q(wdf_data[214]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[215] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [215]), .Q(wdf_data[215]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[216] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [216]), .Q(wdf_data[216]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[217] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [217]), .Q(wdf_data[217]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[218] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [218]), .Q(wdf_data[218]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[219] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [219]), .Q(wdf_data[219]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[21] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [21]), .Q(wdf_data[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[220] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [220]), .Q(wdf_data[220]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[221] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [221]), .Q(wdf_data[221]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[222] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [222]), .Q(wdf_data[222]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[223] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [223]), .Q(wdf_data[223]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[224] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [224]), .Q(wdf_data[224]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[225] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [225]), .Q(wdf_data[225]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[226] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [226]), .Q(wdf_data[226]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[227] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [227]), .Q(wdf_data[227]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[228] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [228]), .Q(wdf_data[228]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[229] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [229]), .Q(wdf_data[229]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[22] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [22]), .Q(wdf_data[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[230] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [230]), .Q(wdf_data[230]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[231] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [231]), .Q(wdf_data[231]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[232] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [232]), .Q(wdf_data[232]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[233] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [233]), .Q(wdf_data[233]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[234] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [234]), .Q(wdf_data[234]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[235] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [235]), .Q(wdf_data[235]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[236] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [236]), .Q(wdf_data[236]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[237] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [237]), .Q(wdf_data[237]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[238] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [238]), .Q(wdf_data[238]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[239] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [239]), .Q(wdf_data[239]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[23] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [23]), .Q(wdf_data[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[240] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [240]), .Q(wdf_data[240]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[241] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [241]), .Q(wdf_data[241]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[242] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [242]), .Q(wdf_data[242]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[243] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [243]), .Q(wdf_data[243]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[244] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [244]), .Q(wdf_data[244]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[245] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [245]), .Q(wdf_data[245]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[246] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [246]), .Q(wdf_data[246]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[247] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [247]), .Q(wdf_data[247]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[248] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [248]), .Q(wdf_data[248]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[249] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [249]), .Q(wdf_data[249]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[24] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [24]), .Q(wdf_data[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[250] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [250]), .Q(wdf_data[250]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[251] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [251]), .Q(wdf_data[251]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[252] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [252]), .Q(wdf_data[252]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[253] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [253]), .Q(wdf_data[253]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[254] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [254]), .Q(wdf_data[254]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[255] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [255]), .Q(wdf_data[255]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[25] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [25]), .Q(wdf_data[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[26] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [26]), .Q(wdf_data[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[27] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [27]), .Q(wdf_data[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[28] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [28]), .Q(wdf_data[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[29] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [29]), .Q(wdf_data[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[2] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [2]), .Q(wdf_data[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[30] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [30]), .Q(wdf_data[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[31] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [31]), .Q(wdf_data[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[32] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [32]), .Q(wdf_data[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[33] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [33]), .Q(wdf_data[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[34] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [34]), .Q(wdf_data[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[35] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [35]), .Q(wdf_data[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[36] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [36]), .Q(wdf_data[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[37] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [37]), .Q(wdf_data[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[38] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [38]), .Q(wdf_data[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[39] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [39]), .Q(wdf_data[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[3] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [3]), .Q(wdf_data[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[40] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [40]), .Q(wdf_data[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[41] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [41]), .Q(wdf_data[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[42] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [42]), .Q(wdf_data[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[43] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [43]), .Q(wdf_data[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[44] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [44]), .Q(wdf_data[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[45] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [45]), .Q(wdf_data[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[46] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [46]), .Q(wdf_data[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[47] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [47]), .Q(wdf_data[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[48] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [48]), .Q(wdf_data[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[49] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [49]), .Q(wdf_data[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[4] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [4]), .Q(wdf_data[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[50] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [50]), .Q(wdf_data[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[51] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [51]), .Q(wdf_data[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[52] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [52]), .Q(wdf_data[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[53] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [53]), .Q(wdf_data[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[54] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [54]), .Q(wdf_data[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[55] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [55]), .Q(wdf_data[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[56] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [56]), .Q(wdf_data[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[57] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [57]), .Q(wdf_data[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[58] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [58]), .Q(wdf_data[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[59] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [59]), .Q(wdf_data[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[5] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [5]), .Q(wdf_data[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[60] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [60]), .Q(wdf_data[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[61] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [61]), .Q(wdf_data[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[62] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [62]), .Q(wdf_data[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[63] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [63]), .Q(wdf_data[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[64] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [64]), .Q(wdf_data[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[65] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [65]), .Q(wdf_data[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[66] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [66]), .Q(wdf_data[66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[67] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [67]), .Q(wdf_data[67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[68] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [68]), .Q(wdf_data[68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[69] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [69]), .Q(wdf_data[69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[6] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [6]), .Q(wdf_data[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[70] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [70]), .Q(wdf_data[70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[71] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [71]), .Q(wdf_data[71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[72] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [72]), .Q(wdf_data[72]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[73] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [73]), .Q(wdf_data[73]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[74] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [74]), .Q(wdf_data[74]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[75] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [75]), .Q(wdf_data[75]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[76] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [76]), .Q(wdf_data[76]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[77] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [77]), .Q(wdf_data[77]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[78] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [78]), .Q(wdf_data[78]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[79] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [79]), .Q(wdf_data[79]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[7] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [7]), .Q(wdf_data[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[80] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [80]), .Q(wdf_data[80]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[81] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [81]), .Q(wdf_data[81]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[82] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [82]), .Q(wdf_data[82]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[83] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [83]), .Q(wdf_data[83]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[84] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [84]), .Q(wdf_data[84]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[85] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [85]), .Q(wdf_data[85]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[86] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [86]), .Q(wdf_data[86]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[87] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [87]), .Q(wdf_data[87]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[88] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [88]), .Q(wdf_data[88]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[89] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [89]), .Q(wdf_data[89]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[8] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [8]), .Q(wdf_data[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[90] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [90]), .Q(wdf_data[90]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[91] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [91]), .Q(wdf_data[91]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[92] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [92]), .Q(wdf_data[92]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[93] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [93]), .Q(wdf_data[93]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[94] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [94]), .Q(wdf_data[94]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[95] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [95]), .Q(wdf_data[95]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[96] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [96]), .Q(wdf_data[96]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[97] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [97]), .Q(wdf_data[97]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[98] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [98]), .Q(wdf_data[98]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[99] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [99]), .Q(wdf_data[99]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_data_reg[9] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [9]), .Q(wdf_data[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(wdf_mask[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[10] (.C(CLK), .CE(1'b1), .D(D[10]), .Q(wdf_mask[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[11] (.C(CLK), .CE(1'b1), .D(D[11]), .Q(wdf_mask[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[12] (.C(CLK), .CE(1'b1), .D(D[12]), .Q(wdf_mask[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[13] (.C(CLK), .CE(1'b1), .D(D[13]), .Q(wdf_mask[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[14] (.C(CLK), .CE(1'b1), .D(D[14]), .Q(wdf_mask[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[15] (.C(CLK), .CE(1'b1), .D(D[15]), .Q(wdf_mask[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[16] (.C(CLK), .CE(1'b1), .D(D[16]), .Q(wdf_mask[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[17] (.C(CLK), .CE(1'b1), .D(D[17]), .Q(wdf_mask[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[18] (.C(CLK), .CE(1'b1), .D(D[18]), .Q(wdf_mask[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[19] (.C(CLK), .CE(1'b1), .D(D[19]), .Q(wdf_mask[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(wdf_mask[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[20] (.C(CLK), .CE(1'b1), .D(D[20]), .Q(wdf_mask[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[21] (.C(CLK), .CE(1'b1), .D(D[21]), .Q(wdf_mask[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[22] (.C(CLK), .CE(1'b1), .D(D[22]), .Q(wdf_mask[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[23] (.C(CLK), .CE(1'b1), .D(D[23]), .Q(wdf_mask[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[24] (.C(CLK), .CE(1'b1), .D(D[24]), .Q(wdf_mask[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[25] (.C(CLK), .CE(1'b1), .D(D[25]), .Q(wdf_mask[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[26] (.C(CLK), .CE(1'b1), .D(D[26]), .Q(wdf_mask[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[27] (.C(CLK), .CE(1'b1), .D(D[27]), .Q(wdf_mask[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[28] (.C(CLK), .CE(1'b1), .D(D[28]), .Q(wdf_mask[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[29] (.C(CLK), .CE(1'b1), .D(D[29]), .Q(wdf_mask[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(wdf_mask[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[30] (.C(CLK), .CE(1'b1), .D(D[30]), .Q(wdf_mask[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[31] (.C(CLK), .CE(1'b1), .D(D[31]), .Q(wdf_mask[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[3] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(wdf_mask[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[4] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(wdf_mask[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[5] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(wdf_mask[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[6] (.C(CLK), .CE(1'b1), .D(D[6]), .Q(wdf_mask[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[7] (.C(CLK), .CE(1'b1), .D(D[7]), .Q(wdf_mask[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[8] (.C(CLK), .CE(1'b1), .D(D[8]), .Q(wdf_mask[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wdf_mask_reg[9] (.C(CLK), .CE(1'b1), .D(D[9]), .Q(wdf_mask[9]), .R(1'b0)); LUT4 #( .INIT(16'hABFB)) wready_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_i_1_n_0)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE #( .INIT(1'b0)) wready_reg (.C(CLK), .CE(1'b1), .D(wready_i_1_n_0), .Q(s_axi_wready), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE #( .INIT(1'b0)) wready_reg_rep (.C(CLK), .CE(1'b1), .D(wready_rep_i_1_n_0), .Q(wready_reg_rep_n_0), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE #( .INIT(1'b0)) wready_reg_rep__0 (.C(CLK), .CE(1'b1), .D(wready_rep__0_i_1_n_0), .Q(wready_reg_rep__0_n_0), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE #( .INIT(1'b0)) wready_reg_rep__1 (.C(CLK), .CE(1'b1), .D(wready_rep__1_i_1_n_0), .Q(wready_reg_rep__1_n_0), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE #( .INIT(1'b0)) wready_reg_rep__2 (.C(CLK), .CE(1'b1), .D(wready_rep__2_i_1_n_0), .Q(wready_reg_rep__2_n_0), .R(areset_d1)); LUT4 #( .INIT(16'hABFB)) wready_rep__0_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep__0_i_1_n_0)); LUT4 #( .INIT(16'hABFB)) wready_rep__1_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep__1_i_1_n_0)); LUT4 #( .INIT(16'hABFB)) wready_rep__2_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep__2_i_1_n_0)); LUT4 #( .INIT(16'hABFB)) wready_rep_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep_i_1_n_0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_wr_cmd_fsm" *) module ddr3_ifmig_7series_v4_0_axi_mc_wr_cmd_fsm (s_axi_awready, axlen_int, D, b_push, \axburst_reg[1] , \axlen_reg[7] , in0, \axaddr_incr_reg[29] , \app_addr_r1_reg[4] , \axaddr_reg[29] , \app_addr_r1_reg[5] , \app_addr_r1_reg[6] , \app_addr_r1_reg[7] , \app_addr_r1_reg[8] , \app_addr_r1_reg[9] , \app_addr_r1_reg[10] , \app_addr_r1_reg[11] , \app_addr_r1_reg[12] , \app_addr_r1_reg[13] , \app_addr_r1_reg[14] , \app_addr_r1_reg[15] , \app_addr_r1_reg[16] , \app_addr_r1_reg[17] , \app_addr_r1_reg[18] , \app_addr_r1_reg[19] , \app_addr_r1_reg[20] , \app_addr_r1_reg[21] , \app_addr_r1_reg[22] , \app_addr_r1_reg[23] , \app_addr_r1_reg[24] , \app_addr_r1_reg[25] , \app_addr_r1_reg[26] , \app_addr_r1_reg[27] , S, \app_addr_r1_reg[3] , \axaddr_incr_reg[29]_0 , \int_addr_reg[3] , \axlen_cnt_reg[3] , awvalid_int, b_awid, E, \axlen_cnt_reg[0] , \axaddr_incr_reg[11] , areset_d1, CLK, Q, axready_reg_0, \axlen_reg[7]_0 , s_axi_awlen, axvalid, s_axi_awvalid, \RD_PRI_REG_STARVE.rnw_i_reg , s_axi_awaddr, \axaddr_reg[29]_0 , \axaddr_incr_reg[29]_1 , \int_addr_reg[3]_0 , out, axready_reg_1, \int_addr_reg[3]_1 , \axlen_cnt_reg[3]_0 , axburst, s_axi_awburst, \RD_PRI_REG_STARVE.rnw_i_reg_0 , s_axi_awid, axid); output s_axi_awready; output [3:0]axlen_int; output [7:0]D; output b_push; output \axburst_reg[1] ; output [3:0]\axlen_reg[7] ; output [3:0]in0; output [24:0]\axaddr_incr_reg[29] ; output \app_addr_r1_reg[4] ; output [29:0]\axaddr_reg[29] ; output \app_addr_r1_reg[5] ; output [0:0]\app_addr_r1_reg[6] ; output \app_addr_r1_reg[7] ; output \app_addr_r1_reg[8] ; output \app_addr_r1_reg[9] ; output \app_addr_r1_reg[10] ; output \app_addr_r1_reg[11] ; output \app_addr_r1_reg[12] ; output \app_addr_r1_reg[13] ; output \app_addr_r1_reg[14] ; output \app_addr_r1_reg[15] ; output \app_addr_r1_reg[16] ; output \app_addr_r1_reg[17] ; output \app_addr_r1_reg[18] ; output \app_addr_r1_reg[19] ; output \app_addr_r1_reg[20] ; output \app_addr_r1_reg[21] ; output \app_addr_r1_reg[22] ; output \app_addr_r1_reg[23] ; output \app_addr_r1_reg[24] ; output \app_addr_r1_reg[25] ; output \app_addr_r1_reg[26] ; output \app_addr_r1_reg[27] ; output [0:0]S; output \app_addr_r1_reg[3] ; output [29:0]\axaddr_incr_reg[29]_0 ; output [3:0]\int_addr_reg[3] ; output [3:0]\axlen_cnt_reg[3] ; output awvalid_int; output b_awid; output [0:0]E; output [0:0]\axlen_cnt_reg[0] ; output [0:0]\axaddr_incr_reg[11] ; input areset_d1; input CLK; input [7:0]Q; input axready_reg_0; input [7:0]\axlen_reg[7]_0 ; input [7:0]s_axi_awlen; input axvalid; input s_axi_awvalid; input \RD_PRI_REG_STARVE.rnw_i_reg ; input [29:0]s_axi_awaddr; input [29:0]\axaddr_reg[29]_0 ; input [29:0]\axaddr_incr_reg[29]_1 ; input \int_addr_reg[3]_0 ; input [29:0]out; input axready_reg_1; input [3:0]\int_addr_reg[3]_1 ; input [3:0]\axlen_cnt_reg[3]_0 ; input [0:0]axburst; input [0:0]s_axi_awburst; input \RD_PRI_REG_STARVE.rnw_i_reg_0 ; input [0:0]s_axi_awid; input axid; wire CLK; wire [7:0]D; wire [0:0]E; wire [7:0]Q; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire \RD_PRI_REG_STARVE.rnw_i_reg_0 ; wire [0:0]S; wire \app_addr_r1[6]_i_3_n_0 ; wire \app_addr_r1[6]_i_5_n_0 ; wire \app_addr_r1_reg[10] ; wire \app_addr_r1_reg[11] ; wire \app_addr_r1_reg[12] ; wire \app_addr_r1_reg[13] ; wire \app_addr_r1_reg[14] ; wire \app_addr_r1_reg[15] ; wire \app_addr_r1_reg[16] ; wire \app_addr_r1_reg[17] ; wire \app_addr_r1_reg[18] ; wire \app_addr_r1_reg[19] ; wire \app_addr_r1_reg[20] ; wire \app_addr_r1_reg[21] ; wire \app_addr_r1_reg[22] ; wire \app_addr_r1_reg[23] ; wire \app_addr_r1_reg[24] ; wire \app_addr_r1_reg[25] ; wire \app_addr_r1_reg[26] ; wire \app_addr_r1_reg[27] ; wire \app_addr_r1_reg[3] ; wire \app_addr_r1_reg[4] ; wire \app_addr_r1_reg[5] ; wire [0:0]\app_addr_r1_reg[6] ; wire \app_addr_r1_reg[7] ; wire \app_addr_r1_reg[8] ; wire \app_addr_r1_reg[9] ; wire areset_d1; wire awvalid_int; wire [0:0]\axaddr_incr_reg[11] ; wire [24:0]\axaddr_incr_reg[29] ; wire [29:0]\axaddr_incr_reg[29]_0 ; wire [29:0]\axaddr_incr_reg[29]_1 ; wire [29:0]\axaddr_reg[29] ; wire [29:0]\axaddr_reg[29]_0 ; wire [0:0]axburst; wire \axburst_reg[1] ; wire [8:5]\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ; wire \axi_mc_cmd_translator_0/incr_axhandshake ; wire \axi_mc_cmd_translator_0/wrap_axhandshake ; wire [8:8]axi_mc_incr_cmd_byte_addr__0; wire axid; wire \axlen_cnt[2]_i_2__0_n_0 ; wire \axlen_cnt[2]_i_2_n_0 ; wire \axlen_cnt[3]_i_2__0_n_0 ; wire \axlen_cnt[3]_i_2_n_0 ; wire \axlen_cnt[4]_i_2_n_0 ; wire \axlen_cnt[4]_i_3_n_0 ; wire \axlen_cnt[5]_i_2_n_0 ; wire \axlen_cnt[5]_i_3_n_0 ; wire \axlen_cnt[7]_i_3_n_0 ; wire \axlen_cnt[7]_i_4_n_0 ; wire [0:0]\axlen_cnt_reg[0] ; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [3:0]axlen_int; wire [3:0]\axlen_reg[7] ; wire [7:0]\axlen_reg[7]_0 ; wire axready_i_1_n_0; wire axready_reg_0; wire axready_reg_1; wire axvalid; wire b_awid; wire b_push; wire [3:0]in0; wire \int_addr[3]_i_5_n_0 ; wire [3:0]\int_addr_reg[3] ; wire \int_addr_reg[3]_0 ; wire [3:0]\int_addr_reg[3]_1 ; wire \memory_reg[7][0]_srl8_i_2_n_0 ; wire \memory_reg[7][0]_srl8_i_3_n_0 ; wire \memory_reg[7][0]_srl8_i_4_n_0 ; wire \memory_reg[7][0]_srl8_i_5_n_0 ; wire [29:0]out; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[10]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [12]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [12]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[10] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[11]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [13]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [13]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[11] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[12]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [14]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [14]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[12] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[13]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [15]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [15]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[13] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[14]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [16]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [16]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[14] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[15]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [17]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [17]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[15] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[16]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [18]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [18]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[16] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[17]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [19]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [19]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[17] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[18]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [20]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [20]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[18] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[19]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [21]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [21]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[19] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[20]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [22]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [22]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[20] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[21]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [23]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [23]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[21] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[22]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [24]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [24]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[22] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[23]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [25]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [25]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[23] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[24]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [26]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [26]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[24] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[25]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [27]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [27]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[25] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[26]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [28]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [28]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[26] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[27]_i_5 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [29]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [29]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[27] )); LUT6 #( .INIT(64'hF8FFF88888888888)) \app_addr_r1[3]_i_3 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I1(\app_addr_r1[6]_i_5_n_0 ), .I2(\axaddr_reg[29] [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .I5(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[3] )); LUT6 #( .INIT(64'hF8FFF88888888888)) \app_addr_r1[4]_i_4 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]), .I1(\app_addr_r1[6]_i_5_n_0 ), .I2(\axaddr_reg[29] [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .I5(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair1130" *) LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[4]_i_5 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [1]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6])); LUT6 #( .INIT(64'hF8FFF88888888888)) \app_addr_r1[5]_i_3 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I1(\app_addr_r1[6]_i_5_n_0 ), .I2(\axaddr_reg[29] [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .I5(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[5] )); LUT5 #( .INIT(32'hFFEAEAEA)) \app_addr_r1[6]_i_1 (.I0(\int_addr_reg[3]_0 ), .I1(\app_addr_r1[6]_i_3_n_0 ), .I2(axi_mc_incr_cmd_byte_addr__0), .I3(\app_addr_r1[6]_i_5_n_0 ), .I4(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]), .O(\app_addr_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair1136" *) LUT4 #( .INIT(16'h001D)) \app_addr_r1[6]_i_3 (.I0(axburst), .I1(s_axi_awready), .I2(s_axi_awburst), .I3(\RD_PRI_REG_STARVE.rnw_i_reg_0 ), .O(\app_addr_r1[6]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[6]_i_4 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [8]), .O(axi_mc_incr_cmd_byte_addr__0)); (* SOFT_HLUTNM = "soft_lutpair1136" *) LUT4 #( .INIT(16'h00E2)) \app_addr_r1[6]_i_5 (.I0(axburst), .I1(s_axi_awready), .I2(s_axi_awburst), .I3(\RD_PRI_REG_STARVE.rnw_i_reg_0 ), .O(\app_addr_r1[6]_i_5_n_0 )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[7]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [9]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [9]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[7] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[8]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [10]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [10]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[8] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[9]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [11]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [11]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[9] )); (* SOFT_HLUTNM = "soft_lutpair1132" *) LUT3 #( .INIT(8'hB8)) \axaddr[0]_i_1 (.I0(s_axi_awaddr[0]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [0]), .O(\axaddr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1147" *) LUT3 #( .INIT(8'hB8)) \axaddr[10]_i_1 (.I0(s_axi_awaddr[10]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [10]), .O(\axaddr_reg[29] [10])); (* SOFT_HLUTNM = "soft_lutpair1147" *) LUT3 #( .INIT(8'hB8)) \axaddr[11]_i_1 (.I0(s_axi_awaddr[11]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [11]), .O(\axaddr_reg[29] [11])); (* SOFT_HLUTNM = "soft_lutpair1146" *) LUT3 #( .INIT(8'hB8)) \axaddr[12]_i_1 (.I0(s_axi_awaddr[12]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [12]), .O(\axaddr_reg[29] [12])); (* SOFT_HLUTNM = "soft_lutpair1146" *) LUT3 #( .INIT(8'hB8)) \axaddr[13]_i_1 (.I0(s_axi_awaddr[13]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [13]), .O(\axaddr_reg[29] [13])); (* SOFT_HLUTNM = "soft_lutpair1145" *) LUT3 #( .INIT(8'hB8)) \axaddr[14]_i_1 (.I0(s_axi_awaddr[14]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [14]), .O(\axaddr_reg[29] [14])); (* SOFT_HLUTNM = "soft_lutpair1145" *) LUT3 #( .INIT(8'hB8)) \axaddr[15]_i_1 (.I0(s_axi_awaddr[15]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [15]), .O(\axaddr_reg[29] [15])); (* SOFT_HLUTNM = "soft_lutpair1144" *) LUT3 #( .INIT(8'hB8)) \axaddr[16]_i_1 (.I0(s_axi_awaddr[16]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [16]), .O(\axaddr_reg[29] [16])); (* SOFT_HLUTNM = "soft_lutpair1144" *) LUT3 #( .INIT(8'hB8)) \axaddr[17]_i_1 (.I0(s_axi_awaddr[17]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [17]), .O(\axaddr_reg[29] [17])); (* SOFT_HLUTNM = "soft_lutpair1143" *) LUT3 #( .INIT(8'hB8)) \axaddr[18]_i_1 (.I0(s_axi_awaddr[18]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [18]), .O(\axaddr_reg[29] [18])); (* SOFT_HLUTNM = "soft_lutpair1143" *) LUT3 #( .INIT(8'hB8)) \axaddr[19]_i_1 (.I0(s_axi_awaddr[19]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [19]), .O(\axaddr_reg[29] [19])); (* SOFT_HLUTNM = "soft_lutpair1133" *) LUT3 #( .INIT(8'hB8)) \axaddr[1]_i_1 (.I0(s_axi_awaddr[1]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [1]), .O(\axaddr_reg[29] [1])); (* SOFT_HLUTNM = "soft_lutpair1142" *) LUT3 #( .INIT(8'hB8)) \axaddr[20]_i_1 (.I0(s_axi_awaddr[20]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [20]), .O(\axaddr_reg[29] [20])); (* SOFT_HLUTNM = "soft_lutpair1142" *) LUT3 #( .INIT(8'hB8)) \axaddr[21]_i_1 (.I0(s_axi_awaddr[21]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [21]), .O(\axaddr_reg[29] [21])); (* SOFT_HLUTNM = "soft_lutpair1141" *) LUT3 #( .INIT(8'hB8)) \axaddr[22]_i_1 (.I0(s_axi_awaddr[22]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [22]), .O(\axaddr_reg[29] [22])); (* SOFT_HLUTNM = "soft_lutpair1141" *) LUT3 #( .INIT(8'hB8)) \axaddr[23]_i_1 (.I0(s_axi_awaddr[23]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [23]), .O(\axaddr_reg[29] [23])); (* SOFT_HLUTNM = "soft_lutpair1140" *) LUT3 #( .INIT(8'hB8)) \axaddr[24]_i_1 (.I0(s_axi_awaddr[24]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [24]), .O(\axaddr_reg[29] [24])); (* SOFT_HLUTNM = "soft_lutpair1140" *) LUT3 #( .INIT(8'hB8)) \axaddr[25]_i_1 (.I0(s_axi_awaddr[25]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [25]), .O(\axaddr_reg[29] [25])); (* SOFT_HLUTNM = "soft_lutpair1139" *) LUT3 #( .INIT(8'hB8)) \axaddr[26]_i_1 (.I0(s_axi_awaddr[26]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [26]), .O(\axaddr_reg[29] [26])); (* SOFT_HLUTNM = "soft_lutpair1139" *) LUT3 #( .INIT(8'hB8)) \axaddr[27]_i_1 (.I0(s_axi_awaddr[27]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [27]), .O(\axaddr_reg[29] [27])); (* SOFT_HLUTNM = "soft_lutpair1138" *) LUT3 #( .INIT(8'hB8)) \axaddr[28]_i_1 (.I0(s_axi_awaddr[28]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [28]), .O(\axaddr_reg[29] [28])); (* SOFT_HLUTNM = "soft_lutpair1138" *) LUT3 #( .INIT(8'hB8)) \axaddr[29]_i_1 (.I0(s_axi_awaddr[29]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [29]), .O(\axaddr_reg[29] [29])); (* SOFT_HLUTNM = "soft_lutpair1134" *) LUT3 #( .INIT(8'hB8)) \axaddr[2]_i_1 (.I0(s_axi_awaddr[2]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [2]), .O(\axaddr_reg[29] [2])); (* SOFT_HLUTNM = "soft_lutpair1135" *) LUT3 #( .INIT(8'hB8)) \axaddr[3]_i_1 (.I0(s_axi_awaddr[3]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [3]), .O(\axaddr_reg[29] [3])); (* SOFT_HLUTNM = "soft_lutpair1149" *) LUT3 #( .INIT(8'hB8)) \axaddr[4]_i_1 (.I0(s_axi_awaddr[4]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [4]), .O(\axaddr_reg[29] [4])); (* SOFT_HLUTNM = "soft_lutpair1131" *) LUT3 #( .INIT(8'hB8)) \axaddr[5]_i_1 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .O(\axaddr_reg[29] [5])); (* SOFT_HLUTNM = "soft_lutpair1130" *) LUT3 #( .INIT(8'hB8)) \axaddr[6]_i_1 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .O(\axaddr_reg[29] [6])); (* SOFT_HLUTNM = "soft_lutpair1129" *) LUT3 #( .INIT(8'hB8)) \axaddr[7]_i_1 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .O(\axaddr_reg[29] [7])); (* SOFT_HLUTNM = "soft_lutpair1128" *) LUT3 #( .INIT(8'hB8)) \axaddr[8]_i_1 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .O(\axaddr_reg[29] [8])); (* SOFT_HLUTNM = "soft_lutpair1148" *) LUT3 #( .INIT(8'hB8)) \axaddr[9]_i_1 (.I0(s_axi_awaddr[9]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [9]), .O(\axaddr_reg[29] [9])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[0]_i_1 (.I0(s_axi_awaddr[0]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [0]), .I3(axready_reg_0), .I4(out[0]), .O(\axaddr_incr_reg[29]_0 [0])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[10]_i_1 (.I0(s_axi_awaddr[10]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [10]), .I3(axready_reg_0), .I4(out[10]), .O(\axaddr_incr_reg[29]_0 [10])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[11]_i_1 (.I0(s_axi_awaddr[11]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [11]), .I3(axready_reg_0), .I4(out[11]), .O(\axaddr_incr_reg[29]_0 [11])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[12]_i_1 (.I0(s_axi_awaddr[12]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [12]), .I3(axready_reg_0), .I4(out[12]), .O(\axaddr_incr_reg[29]_0 [12])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[13]_i_1 (.I0(s_axi_awaddr[13]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [13]), .I3(axready_reg_0), .I4(out[13]), .O(\axaddr_incr_reg[29]_0 [13])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[14]_i_1 (.I0(s_axi_awaddr[14]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [14]), .I3(axready_reg_0), .I4(out[14]), .O(\axaddr_incr_reg[29]_0 [14])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[15]_i_1 (.I0(s_axi_awaddr[15]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [15]), .I3(axready_reg_0), .I4(out[15]), .O(\axaddr_incr_reg[29]_0 [15])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[16]_i_1 (.I0(s_axi_awaddr[16]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [16]), .I3(axready_reg_0), .I4(out[16]), .O(\axaddr_incr_reg[29]_0 [16])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[17]_i_1 (.I0(s_axi_awaddr[17]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [17]), .I3(axready_reg_0), .I4(out[17]), .O(\axaddr_incr_reg[29]_0 [17])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[18]_i_1 (.I0(s_axi_awaddr[18]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [18]), .I3(axready_reg_0), .I4(out[18]), .O(\axaddr_incr_reg[29]_0 [18])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[19]_i_1 (.I0(s_axi_awaddr[19]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [19]), .I3(axready_reg_0), .I4(out[19]), .O(\axaddr_incr_reg[29]_0 [19])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[1]_i_1 (.I0(s_axi_awaddr[1]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [1]), .I3(axready_reg_0), .I4(out[1]), .O(\axaddr_incr_reg[29]_0 [1])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[20]_i_1 (.I0(s_axi_awaddr[20]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [20]), .I3(axready_reg_0), .I4(out[20]), .O(\axaddr_incr_reg[29]_0 [20])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[21]_i_1 (.I0(s_axi_awaddr[21]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [21]), .I3(axready_reg_0), .I4(out[21]), .O(\axaddr_incr_reg[29]_0 [21])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[22]_i_1 (.I0(s_axi_awaddr[22]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [22]), .I3(axready_reg_0), .I4(out[22]), .O(\axaddr_incr_reg[29]_0 [22])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[23]_i_1 (.I0(s_axi_awaddr[23]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [23]), .I3(axready_reg_0), .I4(out[23]), .O(\axaddr_incr_reg[29]_0 [23])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[24]_i_1 (.I0(s_axi_awaddr[24]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [24]), .I3(axready_reg_0), .I4(out[24]), .O(\axaddr_incr_reg[29]_0 [24])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[25]_i_1 (.I0(s_axi_awaddr[25]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [25]), .I3(axready_reg_0), .I4(out[25]), .O(\axaddr_incr_reg[29]_0 [25])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[26]_i_1 (.I0(s_axi_awaddr[26]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [26]), .I3(axready_reg_0), .I4(out[26]), .O(\axaddr_incr_reg[29]_0 [26])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[27]_i_1 (.I0(s_axi_awaddr[27]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [27]), .I3(axready_reg_0), .I4(out[27]), .O(\axaddr_incr_reg[29]_0 [27])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[28]_i_1 (.I0(s_axi_awaddr[28]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [28]), .I3(axready_reg_0), .I4(out[28]), .O(\axaddr_incr_reg[29]_0 [28])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[29]_i_1 (.I0(s_axi_awaddr[29]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [29]), .I3(axready_reg_0), .I4(out[29]), .O(\axaddr_incr_reg[29]_0 [29])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[2]_i_1 (.I0(s_axi_awaddr[2]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [2]), .I3(axready_reg_0), .I4(out[2]), .O(\axaddr_incr_reg[29]_0 [2])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[3]_i_1 (.I0(s_axi_awaddr[3]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [3]), .I3(axready_reg_0), .I4(out[3]), .O(\axaddr_incr_reg[29]_0 [3])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[4]_i_1 (.I0(s_axi_awaddr[4]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [4]), .I3(axready_reg_0), .I4(out[4]), .O(\axaddr_incr_reg[29]_0 [4])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[5]_i_1 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .I3(axready_reg_0), .I4(out[5]), .O(\axaddr_incr_reg[29]_0 [5])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[6]_i_1 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .I3(axready_reg_0), .I4(out[6]), .O(\axaddr_incr_reg[29]_0 [6])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[7]_i_1 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .I3(axready_reg_0), .I4(out[7]), .O(\axaddr_incr_reg[29]_0 [7])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[8]_i_1 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(axready_reg_0), .I4(out[8]), .O(\axaddr_incr_reg[29]_0 [8])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[9]_i_1 (.I0(s_axi_awaddr[9]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [9]), .I3(axready_reg_0), .I4(out[9]), .O(\axaddr_incr_reg[29]_0 [9])); (* SOFT_HLUTNM = "soft_lutpair1135" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_1 (.I0(s_axi_awaddr[3]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [3]), .O(in0[3])); (* SOFT_HLUTNM = "soft_lutpair1134" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_2 (.I0(s_axi_awaddr[2]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [2]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [2]), .O(in0[2])); (* SOFT_HLUTNM = "soft_lutpair1133" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_3 (.I0(s_axi_awaddr[1]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [1]), .O(in0[1])); (* SOFT_HLUTNM = "soft_lutpair1132" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_4 (.I0(s_axi_awaddr[0]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [0]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [0]), .O(in0[0])); LUT3 #( .INIT(8'h08)) axaddr_incr_p_inferred_i_5 (.I0(s_axi_awvalid), .I1(s_axi_awready), .I2(s_axi_awburst), .O(\axi_mc_cmd_translator_0/incr_axhandshake )); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_1 (.I0(s_axi_awaddr[11]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [11]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [11]), .O(\axaddr_incr_reg[29] [6])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_2 (.I0(s_axi_awaddr[10]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [10]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [10]), .O(\axaddr_incr_reg[29] [5])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_3 (.I0(s_axi_awaddr[9]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [9]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [9]), .O(\axaddr_incr_reg[29] [4])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_4__0 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [8]), .O(\axaddr_incr_reg[11] )); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_1 (.I0(s_axi_awaddr[15]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [15]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [15]), .O(\axaddr_incr_reg[29] [10])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_2 (.I0(s_axi_awaddr[14]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [14]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [14]), .O(\axaddr_incr_reg[29] [9])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_3 (.I0(s_axi_awaddr[13]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [13]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [13]), .O(\axaddr_incr_reg[29] [8])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_4 (.I0(s_axi_awaddr[12]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [12]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [12]), .O(\axaddr_incr_reg[29] [7])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_1 (.I0(s_axi_awaddr[19]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [19]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [19]), .O(\axaddr_incr_reg[29] [14])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_2 (.I0(s_axi_awaddr[18]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [18]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [18]), .O(\axaddr_incr_reg[29] [13])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_3 (.I0(s_axi_awaddr[17]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [17]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [17]), .O(\axaddr_incr_reg[29] [12])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_4 (.I0(s_axi_awaddr[16]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [16]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [16]), .O(\axaddr_incr_reg[29] [11])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_1 (.I0(s_axi_awaddr[23]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [23]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [23]), .O(\axaddr_incr_reg[29] [18])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_2 (.I0(s_axi_awaddr[22]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [22]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [22]), .O(\axaddr_incr_reg[29] [17])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_3 (.I0(s_axi_awaddr[21]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [21]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [21]), .O(\axaddr_incr_reg[29] [16])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_4 (.I0(s_axi_awaddr[20]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [20]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [20]), .O(\axaddr_incr_reg[29] [15])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_1 (.I0(s_axi_awaddr[27]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [27]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [27]), .O(\axaddr_incr_reg[29] [22])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_2 (.I0(s_axi_awaddr[26]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [26]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [26]), .O(\axaddr_incr_reg[29] [21])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_3 (.I0(s_axi_awaddr[25]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [25]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [25]), .O(\axaddr_incr_reg[29] [20])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_4 (.I0(s_axi_awaddr[24]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [24]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [24]), .O(\axaddr_incr_reg[29] [19])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_1 (.I0(s_axi_awaddr[29]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [29]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [29]), .O(\axaddr_incr_reg[29] [24])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_2 (.I0(s_axi_awaddr[28]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [28]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [28]), .O(\axaddr_incr_reg[29] [23])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_1 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .O(\axaddr_incr_reg[29] [1])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_2 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .O(\axaddr_incr_reg[29] [3])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_3 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .O(\axaddr_incr_reg[29] [2])); LUT5 #( .INIT(32'h111DDD1D)) axaddr_incr_p_reg0_carry_i_4 (.I0(\axaddr_incr_reg[29]_1 [5]), .I1(\axi_mc_cmd_translator_0/incr_axhandshake ), .I2(\axaddr_reg[29]_0 [5]), .I3(s_axi_awready), .I4(s_axi_awaddr[5]), .O(S)); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_5 (.I0(s_axi_awaddr[4]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [4]), .O(\axaddr_incr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1137" *) LUT3 #( .INIT(8'hB8)) \axburst[1]_i_1 (.I0(s_axi_awburst), .I1(s_axi_awready), .I2(axburst), .O(\axburst_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1137" *) LUT3 #( .INIT(8'hB8)) \axid[0]_i_1 (.I0(s_axi_awid), .I1(s_axi_awready), .I2(axid), .O(b_awid)); LUT3 #( .INIT(8'hB8)) \axlen[0]_i_1 (.I0(s_axi_awlen[0]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [0]), .O(axlen_int[0])); LUT3 #( .INIT(8'hB8)) \axlen[1]_i_1 (.I0(s_axi_awlen[1]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [1]), .O(axlen_int[1])); LUT3 #( .INIT(8'hB8)) \axlen[2]_i_1 (.I0(s_axi_awlen[2]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [2]), .O(axlen_int[2])); LUT3 #( .INIT(8'hB8)) \axlen[3]_i_1 (.I0(s_axi_awlen[3]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [3]), .O(axlen_int[3])); (* SOFT_HLUTNM = "soft_lutpair1150" *) LUT3 #( .INIT(8'hB8)) \axlen[4]_i_1 (.I0(s_axi_awlen[4]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [4]), .O(\axlen_reg[7] [0])); (* SOFT_HLUTNM = "soft_lutpair1150" *) LUT3 #( .INIT(8'hB8)) \axlen[5]_i_1 (.I0(s_axi_awlen[5]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [5]), .O(\axlen_reg[7] [1])); (* SOFT_HLUTNM = "soft_lutpair1149" *) LUT3 #( .INIT(8'hB8)) \axlen[6]_i_1 (.I0(s_axi_awlen[6]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [6]), .O(\axlen_reg[7] [2])); (* SOFT_HLUTNM = "soft_lutpair1148" *) LUT3 #( .INIT(8'hB8)) \axlen[7]_i_1 (.I0(s_axi_awlen[7]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [7]), .O(\axlen_reg[7] [3])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1 (.I0(axready_reg_0), .I1(Q[0]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7]_0 [0]), .I4(s_axi_awready), .I5(s_axi_awlen[0]), .O(D[0])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1__0 (.I0(axready_reg_1), .I1(\axlen_cnt_reg[3]_0 [0]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7]_0 [0]), .I4(s_axi_awready), .I5(s_axi_awlen[0]), .O(\axlen_cnt_reg[3] [0])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[1]), .I2(axlen_int[0]), .I3(Q[0]), .I4(axready_reg_0), .I5(axlen_int[1]), .O(D[1])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1__0 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [1]), .I2(axlen_int[0]), .I3(\axlen_cnt_reg[3]_0 [0]), .I4(axready_reg_1), .I5(axlen_int[1]), .O(\axlen_cnt_reg[3] [1])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[2]), .I2(\axlen_cnt[2]_i_2_n_0 ), .I3(axready_reg_0), .I4(axlen_int[2]), .O(D[2])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1__0 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axlen_cnt[2]_i_2__0_n_0 ), .I3(axready_reg_1), .I4(axlen_int[2]), .O(\axlen_cnt_reg[3] [2])); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2 (.I0(Q[0]), .I1(axlen_int[0]), .I2(Q[1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(axlen_int[1]), .O(\axlen_cnt[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2__0 (.I0(\axlen_cnt_reg[3]_0 [0]), .I1(axlen_int[0]), .I2(\axlen_cnt_reg[3]_0 [1]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(axlen_int[1]), .O(\axlen_cnt[2]_i_2__0_n_0 )); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[3]_i_1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[3]), .I2(\axlen_cnt[3]_i_2_n_0 ), .I3(axready_reg_0), .I4(axlen_int[3]), .O(D[3])); LUT5 #( .INIT(32'hFF1E00B4)) \axlen_cnt[3]_i_1__0 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [3]), .I2(\axlen_cnt[3]_i_2__0_n_0 ), .I3(axready_reg_1), .I4(axlen_int[3]), .O(\axlen_cnt_reg[3] [3])); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \axlen_cnt[3]_i_2 (.I0(\axlen_cnt[2]_i_2_n_0 ), .I1(Q[2]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7]_0 [2]), .I4(s_axi_awready), .I5(s_axi_awlen[2]), .O(\axlen_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h0101015151510151)) \axlen_cnt[3]_i_2__0 (.I0(\axlen_cnt[2]_i_2__0_n_0 ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7]_0 [2]), .I4(s_axi_awready), .I5(s_axi_awlen[2]), .O(\axlen_cnt[3]_i_2__0_n_0 )); LUT6 #( .INIT(64'hF606F6F6F6060606)) \axlen_cnt[4]_i_1 (.I0(\axlen_cnt[4]_i_2_n_0 ), .I1(\axlen_cnt[4]_i_3_n_0 ), .I2(axready_reg_0), .I3(s_axi_awlen[4]), .I4(s_axi_awready), .I5(\axlen_reg[7]_0 [4]), .O(D[4])); LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[4]_i_2 (.I0(s_axi_awlen[4]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[4]), .O(\axlen_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'h0101015151510151)) \axlen_cnt[4]_i_3 (.I0(\axlen_cnt[3]_i_2_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7]_0 [3]), .I4(s_axi_awready), .I5(s_axi_awlen[3]), .O(\axlen_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[5]_i_1 (.I0(\axlen_cnt[5]_i_2_n_0 ), .I1(\axlen_cnt[5]_i_3_n_0 ), .I2(axready_reg_0), .I3(s_axi_awlen[5]), .I4(s_axi_awready), .I5(\axlen_reg[7]_0 [5]), .O(D[5])); LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[5]_i_2 (.I0(s_axi_awlen[5]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[5]), .O(\axlen_cnt[5]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFEFEA)) \axlen_cnt[5]_i_3 (.I0(\axlen_cnt[4]_i_2_n_0 ), .I1(axlen_int[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(Q[3]), .I4(\axlen_cnt[3]_i_2_n_0 ), .O(\axlen_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[6]_i_1 (.I0(\axlen_cnt[7]_i_3_n_0 ), .I1(\axlen_cnt[7]_i_4_n_0 ), .I2(axready_reg_0), .I3(s_axi_awlen[6]), .I4(s_axi_awready), .I5(\axlen_reg[7]_0 [6]), .O(D[6])); LUT5 #( .INIT(32'h0E000ECC)) \axlen_cnt[7]_i_1 (.I0(s_axi_awvalid), .I1(\RD_PRI_REG_STARVE.rnw_i_reg ), .I2(s_axi_awburst), .I3(s_axi_awready), .I4(axburst), .O(E)); LUT6 #( .INIT(64'hFFFFEEE10000444B)) \axlen_cnt[7]_i_2 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[7]), .I2(\axlen_cnt[7]_i_3_n_0 ), .I3(\axlen_cnt[7]_i_4_n_0 ), .I4(axready_reg_0), .I5(\axlen_reg[7] [3]), .O(D[7])); LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[7]_i_3 (.I0(s_axi_awlen[6]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[6]), .O(\axlen_cnt[7]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEAE)) \axlen_cnt[7]_i_4 (.I0(\axlen_cnt[3]_i_2_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(axlen_int[3]), .I4(\axlen_cnt[4]_i_2_n_0 ), .I5(\axlen_cnt[5]_i_2_n_0 ), .O(\axlen_cnt[7]_i_4_n_0 )); LUT4 #( .INIT(16'hABFB)) axready_i_1 (.I0(b_push), .I1(axvalid), .I2(s_axi_awready), .I3(s_axi_awvalid), .O(axready_i_1_n_0)); FDRE #( .INIT(1'b0)) axready_reg (.C(CLK), .CE(1'b1), .D(axready_i_1_n_0), .Q(s_axi_awready), .R(areset_d1)); LUT3 #( .INIT(8'hB8)) axvalid_i_1 (.I0(s_axi_awvalid), .I1(s_axi_awready), .I2(axvalid), .O(awvalid_int)); LUT6 #( .INIT(64'hF606F6F6F6060606)) \int_addr[0]_i_1 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I1(axlen_int[0]), .I2(axready_reg_1), .I3(s_axi_awaddr[5]), .I4(s_axi_awready), .I5(\axaddr_reg[29]_0 [5]), .O(\int_addr_reg[3] [0])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[1]_i_1 (.I0(axready_reg_1), .I1(axlen_int[1]), .I2(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I3(\int_addr_reg[3]_1 [1]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [6]), .O(\int_addr_reg[3] [1])); (* SOFT_HLUTNM = "soft_lutpair1131" *) LUT5 #( .INIT(32'hB8FFB800)) \int_addr[1]_i_2 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [0]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[2]_i_1 (.I0(axready_reg_1), .I1(axlen_int[2]), .I2(\int_addr[3]_i_5_n_0 ), .I3(\int_addr_reg[3]_1 [2]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [7]), .O(\int_addr_reg[3] [2])); LUT3 #( .INIT(8'h80)) \int_addr[2]_i_2 (.I0(s_axi_awvalid), .I1(s_axi_awready), .I2(s_axi_awburst), .O(\axi_mc_cmd_translator_0/wrap_axhandshake )); LUT5 #( .INIT(32'hCFC08080)) \int_addr[3]_i_1 (.I0(s_axi_awvalid), .I1(s_axi_awburst), .I2(s_axi_awready), .I3(axburst), .I4(\RD_PRI_REG_STARVE.rnw_i_reg ), .O(\axlen_cnt_reg[0] )); LUT6 #( .INIT(64'h8BBBBBBBB8888888)) \int_addr[3]_i_2 (.I0(\axaddr_reg[29] [8]), .I1(axready_reg_1), .I2(axlen_int[3]), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I4(\int_addr[3]_i_5_n_0 ), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]), .O(\int_addr_reg[3] [3])); (* SOFT_HLUTNM = "soft_lutpair1129" *) LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_4 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [2]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7])); LUT6 #( .INIT(64'hEEE222E200000000)) \int_addr[3]_i_5 (.I0(\int_addr_reg[3]_1 [1]), .I1(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I2(\axaddr_reg[29]_0 [6]), .I3(s_axi_awready), .I4(s_axi_awaddr[6]), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .O(\int_addr[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1128" *) LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_6 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [3]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8])); LUT5 #( .INIT(32'hAA000C00)) \memory_reg[7][0]_srl8_i_1 (.I0(\memory_reg[7][0]_srl8_i_2_n_0 ), .I1(\memory_reg[7][0]_srl8_i_3_n_0 ), .I2(\axlen_cnt[3]_i_2_n_0 ), .I3(\RD_PRI_REG_STARVE.rnw_i_reg ), .I4(\axburst_reg[1] ), .O(b_push)); LUT6 #( .INIT(64'h0000000000440347)) \memory_reg[7][0]_srl8_i_2 (.I0(axlen_int[2]), .I1(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I2(\axlen_cnt_reg[3]_0 [2]), .I3(axlen_int[3]), .I4(\axlen_cnt_reg[3]_0 [3]), .I5(\axlen_cnt[2]_i_2__0_n_0 ), .O(\memory_reg[7][0]_srl8_i_2_n_0 )); LUT5 #( .INIT(32'h00000001)) \memory_reg[7][0]_srl8_i_3 (.I0(\axlen_cnt[4]_i_2_n_0 ), .I1(\axlen_cnt[5]_i_2_n_0 ), .I2(\memory_reg[7][0]_srl8_i_4_n_0 ), .I3(\memory_reg[7][0]_srl8_i_5_n_0 ), .I4(\axlen_cnt[7]_i_3_n_0 ), .O(\memory_reg[7][0]_srl8_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \memory_reg[7][0]_srl8_i_4 (.I0(s_axi_awlen[7]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[7]), .O(\memory_reg[7][0]_srl8_i_4_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \memory_reg[7][0]_srl8_i_5 (.I0(s_axi_awlen[3]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[3]), .O(\memory_reg[7][0]_srl8_i_5_n_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_wrap_cmd" *) module ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd (\int_addr_reg[3]_0 , \axlen_cnt_reg[3]_0 , areset_d1, axready_reg, axready_reg_0, CLK, \axlen_cnt_reg[3]_1 ); output [3:0]\int_addr_reg[3]_0 ; output [3:0]\axlen_cnt_reg[3]_0 ; input areset_d1; input [0:0]axready_reg; input [3:0]axready_reg_0; input CLK; input [3:0]\axlen_cnt_reg[3]_1 ; wire CLK; wire areset_d1; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [3:0]\axlen_cnt_reg[3]_1 ; wire [0:0]axready_reg; wire [3:0]axready_reg_0; wire [3:0]\int_addr_reg[3]_0 ; FDSE #( .INIT(1'b1)) \axlen_cnt_reg[0] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [0]), .Q(\axlen_cnt_reg[3]_0 [0]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[1] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [1]), .Q(\axlen_cnt_reg[3]_0 [1]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[2] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [2]), .Q(\axlen_cnt_reg[3]_0 [2]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[3] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [3]), .Q(\axlen_cnt_reg[3]_0 [3]), .S(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[0] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[0]), .Q(\int_addr_reg[3]_0 [0]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[1] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[1]), .Q(\int_addr_reg[3]_0 [1]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[2] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[2]), .Q(\int_addr_reg[3]_0 [2]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[3] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[3]), .Q(\int_addr_reg[3]_0 [3]), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_wrap_cmd" *) module ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd__parameterized0 (\app_addr_r1_reg[6] , \axlen_cnt_reg[3]_0 , areset_d1, axready_reg, axready_reg_0, CLK, \axlen_cnt_reg[3]_1 ); output [3:0]\app_addr_r1_reg[6] ; output [3:0]\axlen_cnt_reg[3]_0 ; input areset_d1; input [0:0]axready_reg; input [3:0]axready_reg_0; input CLK; input [3:0]\axlen_cnt_reg[3]_1 ; wire CLK; wire [3:0]\app_addr_r1_reg[6] ; wire areset_d1; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [3:0]\axlen_cnt_reg[3]_1 ; wire [0:0]axready_reg; wire [3:0]axready_reg_0; FDSE #( .INIT(1'b1)) \axlen_cnt_reg[0] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [0]), .Q(\axlen_cnt_reg[3]_0 [0]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[1] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [1]), .Q(\axlen_cnt_reg[3]_0 [1]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[2] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [2]), .Q(\axlen_cnt_reg[3]_0 [2]), .S(areset_d1)); FDSE #( .INIT(1'b1)) \axlen_cnt_reg[3] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [3]), .Q(\axlen_cnt_reg[3]_0 [3]), .S(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[0] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[0]), .Q(\app_addr_r1_reg[6] [0]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[1] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[1]), .Q(\app_addr_r1_reg[6] [1]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[2] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[2]), .Q(\app_addr_r1_reg[6] [2]), .R(areset_d1)); FDRE #( .INIT(1'b0)) \int_addr_reg[3] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[3]), .Q(\app_addr_r1_reg[6] [3]), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_cntrl" *) module ddr3_ifmig_7series_v4_0_bank_cntrl (rb_hit_busy_r, E, idle_r_lcl_reg, \rd_this_rank_r_reg[0] , \act_this_rank_r_reg[0] , req_periodic_rd_r, bm_end_r1_reg, row_hit_r, bm_end_r1, bm_end_r1_reg_0, \rp_timer.rp_timer_r_reg[1] , act_this_rank_r, req_bank_rdy_r, req_bank_rdy_ns, demand_priority_r, demanded_prior_r, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, wait_for_maint_r_lcl_reg, bm_end_r1_reg_1, pre_bm_end_r, rb_hit_busies_r, pre_passing_open_bank_r, tail_r, q_entry_r, idle_r_lcl_reg_0, \rp_timer.rp_timer_r_reg[1]_0 , ordered_r_lcl, req_bank_rdy_r_reg, ofs_rdy_r0, granted_col_ns, granted_col_r_reg, Q, head_r_lcl_reg, head_r_lcl_reg_0, set_order_q_7, \ras_timer_r_reg[2] , \ras_timer_r_reg[1] , \ras_timer_r_reg[0] , pre_wait_r_reg, pre_wait_r_reg_0, \q_entry_r_reg[0] , act_wait_r_lcl_reg, granted_pre_ns, \grant_r_reg[1] , granted_row_r_reg, req_bank_rdy_r_reg_0, rnk_config_strobe_ns, \rnk_config_strobe_r_reg[0] , granted_col_r_reg_0, auto_pre_r_lcl_reg, pass_open_bank_r_lcl_reg, \cmd_pipe_plus.mc_address_reg[14] , \cmd_pipe_plus.mc_bank_reg[2] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_address_reg[24] , p_67_out, CLK, periodic_rd_insert, hi_priority, override_demand_ns, rstdiv0_sync_r1_reg_rep__0, phy_mc_ctl_full, SR, of_ctl_full_v, wait_for_maint_ns, pass_open_bank_r_lcl_reg_0, rb_hit_busies_ns, idle_r_lcl_reg_1, \q_entry_r_reg[0]_0 , head_r_lcl_reg_1, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg, ordered_r_lcl_reg_0, \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , rd_wr_r_lcl_reg, col_wait_r_reg, \wtr_timer.wtr_cnt_r_reg[1] , \grant_r_reg[0] , cmd, \grant_r_reg[1]_0 , periodic_rd_ack_r_lcl_reg, use_addr, accept_internal_r, req_wr_r_lcl_reg, pre_bm_end_r_reg, rb_hit_busy_r_reg, periodic_rd_ack_r_lcl_reg_0, periodic_rd_ack_r_lcl_reg_1, \ras_timer_r_reg[2]_0 , bm_end_r1_reg_2, rd_wr_r_lcl_reg_0, \grant_r_reg[0]_0 , bm_end_r1_reg_3, req_wr_r_lcl_reg_0, pre_passing_open_bank_r_0, pass_open_bank_r_lcl_reg_1, maint_req_r, was_wr, accept_r_reg, rstdiv0_sync_r1_reg_rep__21, app_hi_pri_r2, idle_r_lcl_reg_2, accept_r_reg_0, \grant_r_reg[0]_1 , auto_pre_r_lcl_reg_1, \grant_r_reg[1]_1 , \rnk_config_strobe_r_reg[0]_0 , req_bank_rdy_ns_1, demand_priority_r_reg, rnk_config_valid_r_lcl_reg, \rnk_config_strobe_r_reg[0]_1 , \order_q_r_reg[0] , req_wr_r_lcl_reg_1, \maint_controller.maint_wip_r_lcl_reg , periodic_rd_cntr_r_reg, demanded_prior_r_1, demand_priority_r_2, \app_addr_r1_reg[27] , req_bank_rdy_r_reg_1, \app_addr_r1_reg[12] , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , D, \app_addr_r1_reg[9] , rstdiv0_sync_r1_reg_rep__20, pass_open_bank_r_lcl_reg_2, granted_col_r_reg_1); output [0:0]rb_hit_busy_r; output [0:0]E; output [0:0]idle_r_lcl_reg; output \rd_this_rank_r_reg[0] ; output \act_this_rank_r_reg[0] ; output [0:0]req_periodic_rd_r; output bm_end_r1_reg; output row_hit_r; output bm_end_r1; output bm_end_r1_reg_0; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]act_this_rank_r; output req_bank_rdy_r; output req_bank_rdy_ns; output demand_priority_r; output demanded_prior_r; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output wait_for_maint_r_lcl_reg; output bm_end_r1_reg_1; output pre_bm_end_r; output [0:0]rb_hit_busies_r; output pre_passing_open_bank_r; output tail_r; output q_entry_r; output idle_r_lcl_reg_0; output \rp_timer.rp_timer_r_reg[1]_0 ; output ordered_r_lcl; output req_bank_rdy_r_reg; output ofs_rdy_r0; output granted_col_ns; output granted_col_r_reg; output [1:0]Q; output head_r_lcl_reg; output head_r_lcl_reg_0; output set_order_q_7; output \ras_timer_r_reg[2] ; output \ras_timer_r_reg[1] ; output \ras_timer_r_reg[0] ; output pre_wait_r_reg; output pre_wait_r_reg_0; output \q_entry_r_reg[0] ; output act_wait_r_lcl_reg; output granted_pre_ns; output \grant_r_reg[1] ; output granted_row_r_reg; output req_bank_rdy_r_reg_0; output rnk_config_strobe_ns; output \rnk_config_strobe_r_reg[0] ; output granted_col_r_reg_0; output auto_pre_r_lcl_reg; output pass_open_bank_r_lcl_reg; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input p_67_out; input CLK; input periodic_rd_insert; input hi_priority; input override_demand_ns; input rstdiv0_sync_r1_reg_rep__0; input phy_mc_ctl_full; input [0:0]SR; input [0:0]of_ctl_full_v; input wait_for_maint_ns; input pass_open_bank_r_lcl_reg_0; input rb_hit_busies_ns; input idle_r_lcl_reg_1; input \q_entry_r_reg[0]_0 ; input head_r_lcl_reg_1; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg; input ordered_r_lcl_reg_0; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input rd_wr_r_lcl_reg; input col_wait_r_reg; input \wtr_timer.wtr_cnt_r_reg[1] ; input \grant_r_reg[0] ; input [1:0]cmd; input [1:0]\grant_r_reg[1]_0 ; input periodic_rd_ack_r_lcl_reg; input use_addr; input accept_internal_r; input req_wr_r_lcl_reg; input pre_bm_end_r_reg; input rb_hit_busy_r_reg; input periodic_rd_ack_r_lcl_reg_0; input periodic_rd_ack_r_lcl_reg_1; input \ras_timer_r_reg[2]_0 ; input bm_end_r1_reg_2; input rd_wr_r_lcl_reg_0; input [0:0]\grant_r_reg[0]_0 ; input bm_end_r1_reg_3; input req_wr_r_lcl_reg_0; input pre_passing_open_bank_r_0; input pass_open_bank_r_lcl_reg_1; input maint_req_r; input was_wr; input accept_r_reg; input rstdiv0_sync_r1_reg_rep__21; input app_hi_pri_r2; input [0:0]idle_r_lcl_reg_2; input accept_r_reg_0; input [0:0]\grant_r_reg[0]_1 ; input auto_pre_r_lcl_reg_1; input \grant_r_reg[1]_1 ; input \rnk_config_strobe_r_reg[0]_0 ; input req_bank_rdy_ns_1; input demand_priority_r_reg; input rnk_config_valid_r_lcl_reg; input \rnk_config_strobe_r_reg[0]_1 ; input \order_q_r_reg[0] ; input req_wr_r_lcl_reg_1; input \maint_controller.maint_wip_r_lcl_reg ; input periodic_rd_cntr_r_reg; input demanded_prior_r_1; input demand_priority_r_2; input [14:0]\app_addr_r1_reg[27] ; input req_bank_rdy_r_reg_1; input [2:0]\app_addr_r1_reg[12] ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [1:0]D; input [6:0]\app_addr_r1_reg[9] ; input rstdiv0_sync_r1_reg_rep__20; input pass_open_bank_r_lcl_reg_2; input granted_col_r_reg_1; wire CLK; wire [1:0]D; wire [0:0]E; wire [1:0]Q; wire [0:0]SR; wire accept_internal_r; wire accept_r_reg; wire accept_r_reg_0; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0] ; wire act_wait_ns; wire act_wait_r_lcl_reg; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire app_hi_pri_r2; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire bank_compare0_n_14; wire bank_compare0_n_15; wire bank_queue0_n_23; wire bank_state0_n_26; wire bm_end_r1; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire [1:0]cmd; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r; wire col_wait_r_reg; wire demand_priority_r; wire demand_priority_r_2; wire demand_priority_r_reg; wire demanded_prior_r; wire demanded_prior_r_1; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire \grant_r_reg[0] ; wire [0:0]\grant_r_reg[0]_0 ; wire [0:0]\grant_r_reg[0]_1 ; wire \grant_r_reg[1] ; wire [1:0]\grant_r_reg[1]_0 ; wire \grant_r_reg[1]_1 ; wire granted_col_ns; wire granted_col_r_reg; wire granted_col_r_reg_0; wire granted_col_r_reg_1; wire granted_pre_ns; wire granted_row_r_reg; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire hi_priority; wire [0:0]idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire [0:0]idle_r_lcl_reg_2; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r; wire ofs_rdy_r0; wire \order_q_r_reg[0] ; wire ordered_r_lcl; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire override_demand_ns; wire p_67_out; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire pass_open_bank_r_lcl_reg_1; wire pass_open_bank_r_lcl_reg_2; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire phy_mc_ctl_full; wire pre_bm_end_ns; wire pre_bm_end_r; wire pre_bm_end_r_reg; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_0; wire pre_wait_r_reg; wire pre_wait_r_reg_0; wire q_entry_r; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire q_has_priority; wire q_has_rd; wire [2:0]ras_timer_passed_ns; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire ras_timer_zero_r; wire rb_hit_busies_ns; wire [0:0]rb_hit_busies_r; wire [0:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire [0:0]rd_this_rank_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_ns; wire req_bank_rdy_ns_1; wire req_bank_rdy_r; wire req_bank_rdy_r_reg; wire req_bank_rdy_r_reg_0; wire req_bank_rdy_r_reg_1; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire rnk_config_strobe_ns; wire \rnk_config_strobe_r_reg[0] ; wire \rnk_config_strobe_r_reg[0]_0 ; wire \rnk_config_strobe_r_reg[0]_1 ; wire rnk_config_valid_r_lcl_reg; wire row_hit_r; wire \rp_timer.rp_timer_r_reg[1] ; wire \rp_timer.rp_timer_r_reg[1]_0 ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire set_order_q_7; wire start_wtp_timer0; wire tail_r; wire use_addr; wire wait_for_maint_ns; wire wait_for_maint_r_lcl_reg; wire was_wr; wire [0:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; ddr3_ifmig_7series_v4_0_bank_compare_0 bank_compare0 (.CLK(CLK), .D(D), .Q(Q), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .bm_end_r1_reg(bm_end_r1_reg), .cmd(cmd), .\cmd_pipe_plus.mc_address_reg[14] (\cmd_pipe_plus.mc_address_reg[14] ), .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\col_mux.col_data_buf_addr_r_reg[4] (\col_mux.col_data_buf_addr_r_reg[4] ), .col_wait_r(col_wait_r), .col_wait_r_reg(col_wait_r_reg), .demand_priority_r_reg(bank_compare0_n_14), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[1] (\grant_r_reg[1]_0 ), .granted_col_ns(granted_col_ns), .granted_col_r_reg(granted_col_r_reg), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg), .idle_r_lcl_reg_0(E), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .\order_q_r_reg[0] (req_bank_rdy_r_reg), .override_demand_r_reg(bank_state0_n_26), .p_67_out(p_67_out), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .pass_open_bank_r_lcl_reg_0(bm_end_r1_reg_1), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg), .periodic_rd_insert(periodic_rd_insert), .pre_passing_open_bank_r_reg(bank_queue0_n_23), .ras_timer_zero_r_reg(bank_compare0_n_15), .rb_hit_busy_r(rb_hit_busy_r), .\rd_this_rank_r_reg[0] (\rd_this_rank_r_reg[0] ), .rd_wr_ns(rd_wr_ns), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg), .req_bank_rdy_ns(req_bank_rdy_ns), .req_bank_rdy_r_reg(req_bank_rdy_r_reg_0), .req_periodic_rd_r(req_periodic_rd_r), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0]_0 ), .row_hit_r(row_hit_r), .start_wtp_timer0(start_wtp_timer0), .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_ifmig_7series_v4_0_bank_queue bank_queue0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .accept_internal_r(accept_internal_r), .accept_r_reg(accept_r_reg), .accept_r_reg_0(accept_r_reg_0), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg(\act_this_rank_r_reg[0] ), .app_hi_pri_r2(app_hi_pri_r2), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .bm_end_r1_reg(bm_end_r1_reg_1), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(\ras_timer_r_reg[2] ), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bm_end_r1_reg_3(\ras_timer_r_reg[1] ), .bm_end_r1_reg_4(bm_end_r1_reg_3), .cmd(cmd[0]), .\grant_r_reg[0] (\grant_r_reg[1]_0 [0]), .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ), .\grant_r_reg[1] (\grant_r_reg[1]_1 ), .granted_row_r_reg(granted_row_r_reg), .head_r_lcl_reg_0(head_r_lcl_reg), .head_r_lcl_reg_1(head_r_lcl_reg_0), .head_r_lcl_reg_2(head_r_lcl_reg_1), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(idle_r_lcl_reg_0), .idle_r_lcl_reg_2(idle_r_lcl_reg_1), .idle_r_lcl_reg_3(idle_r_lcl_reg_2), .maint_req_r(maint_req_r), .ordered_r_lcl(ordered_r_lcl), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0), .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1), .periodic_rd_insert(periodic_rd_insert), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r(pre_bm_end_r), .pre_bm_end_r_reg_0(pre_bm_end_r_reg), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_passing_open_bank_r_0(pre_passing_open_bank_r_0), .q_entry_r(q_entry_r), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ), .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ), .q_has_priority(q_has_priority), .q_has_rd(q_has_rd), .\ras_timer_r_reg[1] (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[2] (bank_queue0_n_23), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2]_0 ), .ras_timer_zero_r(ras_timer_zero_r), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (rb_hit_busies_r), .rb_hit_busies_ns(rb_hit_busies_ns), .rb_hit_busy_r(rb_hit_busy_r), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rd_wr_ns(rd_wr_ns), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .req_bank_rdy_r_reg(req_bank_rdy_r_reg), .\req_data_buf_addr_r_reg[4] (E), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .req_wr_r_lcl_reg_0(bm_end_r1_reg), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_0), .\rp_timer.rp_timer_r_reg[1] (\rp_timer.rp_timer_r_reg[1]_0 ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .set_order_q_7(set_order_q_7), .tail_r(tail_r), .use_addr(use_addr), .wait_for_maint_ns(wait_for_maint_ns), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .was_wr(was_wr)); ddr3_ifmig_7series_v4_0_bank_state bank_state0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .accept_r_reg(accept_r_reg), .act_this_rank_r(act_this_rank_r), .\act_this_rank_r_reg[0]_0 (\act_this_rank_r_reg[0] ), .act_wait_ns(act_wait_ns), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(\rp_timer.rp_timer_r_reg[1]_0 ), .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1), .bm_end_r1(bm_end_r1), .bm_end_r1_reg_0(bm_end_r1_reg_3), .col_wait_r(col_wait_r), .demand_priority_r_2(demand_priority_r_2), .demand_priority_r_reg_0(demand_priority_r_reg), .demanded_prior_r_1(demanded_prior_r_1), .demanded_prior_r_reg_0(demand_priority_r), .demanded_prior_r_reg_1(demanded_prior_r), .\entry_cnt_reg[2] (\entry_cnt_reg[2] ), .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2]_0 ), .\grant_r_reg[0] (\grant_r_reg[0]_0 ), .\grant_r_reg[0]_0 (\grant_r_reg[0]_1 ), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ), .granted_col_r_reg(granted_col_r_reg_0), .granted_col_r_reg_0(bank_state0_n_26), .granted_col_r_reg_1(granted_col_r_reg_1), .granted_pre_ns(granted_pre_ns), .idle_r_lcl_reg(idle_r_lcl_reg), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r0(ofs_rdy_r0), .\order_q_r_reg[0] (bank_compare0_n_14), .\order_q_r_reg[0]_0 (\order_q_r_reg[0] ), .override_demand_ns(override_demand_ns), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_0), .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_1), .pass_open_bank_r_lcl_reg_1(bm_end_r1_reg_1), .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg_2), .phy_mc_ctl_full(phy_mc_ctl_full), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r_reg(bm_end_r1_reg_0), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r_reg(bank_queue0_n_23), .pre_wait_r_reg_0(pre_wait_r_reg), .pre_wait_r_reg_1(pre_wait_r_reg_0), .q_has_priority(q_has_priority), .q_has_rd(q_has_rd), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2] ), .ras_timer_zero_r(ras_timer_zero_r), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_1(bank_compare0_n_15), .rd_wr_r_lcl_reg_2(req_bank_rdy_r_reg_0), .req_bank_rdy_ns(req_bank_rdy_ns), .req_bank_rdy_ns_1(req_bank_rdy_ns_1), .req_bank_rdy_r(req_bank_rdy_r), .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_1), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg(bm_end_r1_reg), .rnk_config_strobe_ns(rnk_config_strobe_ns), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_1 ), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg), .\rp_timer.rp_timer_r_reg[1]_0 (\rp_timer.rp_timer_r_reg[1] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .start_wtp_timer0(start_wtp_timer0), .tail_r(tail_r), .wr_this_rank_r(wr_this_rank_r)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_cntrl" *) module ddr3_ifmig_7series_v4_0_bank_cntrl__parameterized0 (q_has_priority_r_reg, E, idle_r_lcl_reg, \rd_this_rank_r_reg[0] , row_cmd_wr, req_periodic_rd_r, bm_end_r1_reg, act_this_rank_r, wr_this_rank_r, rd_this_rank_r, row_hit_r_0, bm_end_r1_0, bm_end_r1_reg_0, req_bank_rdy_r, req_bank_rdy_ns_1, demand_priority_r, demanded_prior_r, ofs_rdy_r, wait_for_maint_r_lcl_reg, bm_end_r1_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , pre_passing_open_bank_r, q_has_rd, q_has_priority, \rcd_timer_gt_2.rcd_timer_r_reg[0] , idle_r_lcl_reg_0, \order_q_r_reg[0] , tail_r_3, q_entry_r_4, \rp_timer.rp_timer_r_reg[1] , req_bank_rdy_r_reg, rb_hit_busies_ns, granted_col_r_reg, p_9_in, Q, pass_open_bank_r_lcl_reg, head_r_lcl_reg, \q_entry_r_reg[0] , \q_entry_r_reg[0]_0 , set_order_q, \q_entry_r_reg[0]_1 , \ras_timer_r_reg[2] , \ras_timer_r_reg[0] , \ras_timer_r_reg[1] , \ras_timer_r_reg[2]_0 , \cmd_pipe_plus.mc_address_reg[10] , \cmd_pipe_plus.mc_address_reg[14] , granted_row_ns, granted_row_r_reg, ras_timer_zero_r_reg, auto_pre_r_lcl_reg, \pre_4_1_1T_arb.granted_pre_r_reg , \rnk_config_strobe_r_reg[0] , \cmd_pipe_plus.mc_address_reg[40] , \cmd_pipe_plus.mc_bank_reg[2] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_address_reg[24] , p_28_out, CLK, periodic_rd_insert, hi_priority, rstdiv0_sync_r1_reg_rep__0, ofs_rdy_r0, wait_for_maint_ns, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 , q_has_rd_r_reg, q_has_priority_r_reg_0, SR, head_r_lcl_reg_0, ordered_r_lcl_reg, idle_r_lcl_reg_1, \q_entry_r_reg[0]_2 , auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_0, \req_bank_r_lcl_reg[0] , rb_hit_busies_r, idle_r_lcl_reg_2, rstdiv0_sync_r1_reg_rep__20, \wtr_timer.wtr_cnt_r_reg[1] , \order_q_r_reg[0]_0 , \grant_r_reg[0] , init_calib_complete_reg_rep__6, cmd, \grant_r_reg[1] , periodic_rd_ack_r_lcl_reg, use_addr, accept_internal_r, periodic_rd_ack_r_lcl_reg_0, periodic_rd_ack_r_lcl_reg_1, pre_bm_end_r_reg, bm_end_r1_reg_2, \grant_r_reg[1]_0 , rtp_timer_ns1, accept_r_reg, rstdiv0_sync_r1_reg_rep__21, rb_hit_busy_r, \ras_timer_r_reg[1]_0 , bm_end_r1_reg_3, bm_end_r1_reg_4, req_wr_r_lcl_reg, pre_passing_open_bank_r_0, \req_row_r_lcl_reg[10] , \grant_r_reg[0]_0 , act_wait_r_lcl_reg, mc_cs_n_ns, head_r_lcl_reg_1, \grant_r_reg[0]_1 , \ras_timer_r_reg[2]_1 , rd_wr_r_lcl_reg, \maint_controller.maint_wip_r_lcl_reg , periodic_rd_cntr_r_reg, maint_req_r, \grant_r_reg[1]_1 , demanded_prior_r_1, demand_priority_r_2, \app_addr_r1_reg[27] , req_bank_rdy_r_reg_0, \app_addr_r1_reg[12] , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , D, \app_addr_r1_reg[9] , granted_col_r_reg_0); output q_has_priority_r_reg; output [0:0]E; output [0:0]idle_r_lcl_reg; output \rd_this_rank_r_reg[0] ; output [0:0]row_cmd_wr; output [0:0]req_periodic_rd_r; output bm_end_r1_reg; output [0:0]act_this_rank_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output row_hit_r_0; output bm_end_r1_0; output bm_end_r1_reg_0; output req_bank_rdy_r; output req_bank_rdy_ns_1; output demand_priority_r; output demanded_prior_r; output ofs_rdy_r; output wait_for_maint_r_lcl_reg; output bm_end_r1_reg_1; output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; output pre_passing_open_bank_r; output q_has_rd; output q_has_priority; output \rcd_timer_gt_2.rcd_timer_r_reg[0] ; output idle_r_lcl_reg_0; output \order_q_r_reg[0] ; output tail_r_3; output q_entry_r_4; output \rp_timer.rp_timer_r_reg[1] ; output req_bank_rdy_r_reg; output rb_hit_busies_ns; output granted_col_r_reg; output p_9_in; output [1:0]Q; output pass_open_bank_r_lcl_reg; output head_r_lcl_reg; output \q_entry_r_reg[0] ; output \q_entry_r_reg[0]_0 ; output set_order_q; output \q_entry_r_reg[0]_1 ; output \ras_timer_r_reg[2] ; output \ras_timer_r_reg[0] ; output \ras_timer_r_reg[1] ; output \ras_timer_r_reg[2]_0 ; output [0:0]\cmd_pipe_plus.mc_address_reg[10] ; output [13:0]\cmd_pipe_plus.mc_address_reg[14] ; output granted_row_ns; output granted_row_r_reg; output [2:0]ras_timer_zero_r_reg; output auto_pre_r_lcl_reg; output \pre_4_1_1T_arb.granted_pre_r_reg ; output \rnk_config_strobe_r_reg[0] ; output \cmd_pipe_plus.mc_address_reg[40] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input p_28_out; input CLK; input periodic_rd_insert; input hi_priority; input rstdiv0_sync_r1_reg_rep__0; input ofs_rdy_r0; input wait_for_maint_ns; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; input q_has_rd_r_reg; input q_has_priority_r_reg_0; input [0:0]SR; input head_r_lcl_reg_0; input ordered_r_lcl_reg; input idle_r_lcl_reg_1; input \q_entry_r_reg[0]_2 ; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_0; input \req_bank_r_lcl_reg[0] ; input [0:0]rb_hit_busies_r; input [0:0]idle_r_lcl_reg_2; input rstdiv0_sync_r1_reg_rep__20; input \wtr_timer.wtr_cnt_r_reg[1] ; input \order_q_r_reg[0]_0 ; input \grant_r_reg[0] ; input init_calib_complete_reg_rep__6; input [1:0]cmd; input [1:0]\grant_r_reg[1] ; input periodic_rd_ack_r_lcl_reg; input use_addr; input accept_internal_r; input periodic_rd_ack_r_lcl_reg_0; input periodic_rd_ack_r_lcl_reg_1; input pre_bm_end_r_reg; input bm_end_r1_reg_2; input [0:0]\grant_r_reg[1]_0 ; input rtp_timer_ns1; input accept_r_reg; input rstdiv0_sync_r1_reg_rep__21; input [0:0]rb_hit_busy_r; input \ras_timer_r_reg[1]_0 ; input bm_end_r1_reg_3; input bm_end_r1_reg_4; input req_wr_r_lcl_reg; input pre_passing_open_bank_r_0; input [0:0]\req_row_r_lcl_reg[10] ; input \grant_r_reg[0]_0 ; input act_wait_r_lcl_reg; input [0:0]mc_cs_n_ns; input head_r_lcl_reg_1; input \grant_r_reg[0]_1 ; input \ras_timer_r_reg[2]_1 ; input rd_wr_r_lcl_reg; input \maint_controller.maint_wip_r_lcl_reg ; input periodic_rd_cntr_r_reg; input maint_req_r; input [1:0]\grant_r_reg[1]_1 ; input demanded_prior_r_1; input demand_priority_r_2; input [14:0]\app_addr_r1_reg[27] ; input req_bank_rdy_r_reg_0; input [2:0]\app_addr_r1_reg[12] ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [1:0]D; input [6:0]\app_addr_r1_reg[9] ; input granted_col_r_reg_0; wire CLK; wire [1:0]D; wire [0:0]E; wire [1:0]Q; wire [0:0]SR; wire accept_internal_r; wire accept_r_reg; wire [0:0]act_this_rank_r; wire act_wait_ns; wire act_wait_r_lcl_reg; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire bank_compare0_n_12; wire bank_queue0_n_18; wire bank_state0_n_16; wire bank_state0_n_27; wire bm_end_r1_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire [1:0]cmd; wire [0:0]\cmd_pipe_plus.mc_address_reg[10] ; wire [13:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire \cmd_pipe_plus.mc_address_reg[40] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r; wire demand_priority_ns; wire demand_priority_r; wire demand_priority_r_2; wire demanded_prior_r; wire demanded_prior_r_1; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[0]_1 ; wire [1:0]\grant_r_reg[1] ; wire [0:0]\grant_r_reg[1]_0 ; wire [1:0]\grant_r_reg[1]_1 ; wire granted_col_r_reg; wire granted_col_r_reg_0; wire granted_row_ns; wire granted_row_r_reg; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire hi_priority; wire [0:0]idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire [0:0]idle_r_lcl_reg_2; wire init_calib_complete_reg_rep__6; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [0:0]mc_cs_n_ns; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire ofs_rdy_r; wire ofs_rdy_r0; wire \order_q_r_reg[0] ; wire \order_q_r_reg[0]_0 ; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire p_28_out; wire p_9_in; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire pre_bm_end_ns; wire pre_bm_end_r; wire pre_bm_end_r_reg; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_0; wire pre_wait_r; wire q_entry_r_4; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire \q_entry_r_reg[0]_2 ; wire q_has_priority; wire q_has_priority_r_reg; wire q_has_priority_r_reg_0; wire q_has_rd; wire q_has_rd_r_reg; wire [2:0]ras_timer_passed_ns; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire ras_timer_zero_r; wire [2:0]ras_timer_zero_r_reg; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; wire rb_hit_busies_ns; wire [0:0]rb_hit_busies_r; wire [0:0]rb_hit_busy_r; wire \rcd_timer_gt_2.rcd_timer_r_reg[0] ; wire [0:0]rd_this_rank_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire rd_wr_r_lcl_reg; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_ns_1; wire req_bank_rdy_r; wire req_bank_rdy_r_reg; wire req_bank_rdy_r_reg_0; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire [25:25]req_row_r; wire [0:0]\req_row_r_lcl_reg[10] ; wire req_wr_r_lcl_reg; wire \rnk_config_strobe_r_reg[0] ; wire [0:0]row_cmd_wr; wire row_hit_r_0; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rtp_timer_ns1; wire set_order_q; wire start_wtp_timer0; wire tail_r_3; wire use_addr; wire wait_for_maint_ns; wire wait_for_maint_r_lcl_reg; wire [0:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; ddr3_ifmig_7series_v4_0_bank_compare bank_compare0 (.CLK(CLK), .D(D), .Q(Q), .accept_r_reg(accept_r_reg), .act_wait_r_lcl_reg(row_cmd_wr), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .bm_end_r1_reg(bm_end_r1_reg), .cmd(cmd), .\cmd_pipe_plus.mc_address_reg[14] ({\cmd_pipe_plus.mc_address_reg[14] [13:10],req_row_r,\cmd_pipe_plus.mc_address_reg[14] [9:0]}), .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ), .\cmd_pipe_plus.mc_address_reg[40] (\cmd_pipe_plus.mc_address_reg[40] ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\col_mux.col_data_buf_addr_r_reg[4] (\col_mux.col_data_buf_addr_r_reg[4] ), .\grant_r_reg[1] (\grant_r_reg[1] [1]), .\grant_r_reg[1]_0 (\grant_r_reg[1]_1 ), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg), .idle_r_lcl_reg_0(E), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .p_28_out(p_28_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .pass_open_bank_r_lcl_reg_0(bm_end_r1_reg_1), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg), .periodic_rd_insert(periodic_rd_insert), .pre_bm_end_r(pre_bm_end_r), .pre_bm_end_r_reg(pre_bm_end_r_reg), .pre_wait_r(pre_wait_r), .\q_entry_r_reg[0] (\q_entry_r_reg[0] ), .q_has_priority_r_reg(q_has_priority_r_reg), .\ras_timer_r_reg[2] (\ras_timer_r_reg[2] ), .ras_timer_zero_r_reg(bank_compare0_n_12), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .rb_hit_busy_r(rb_hit_busy_r), .\rd_this_rank_r_reg[0] (\rd_this_rank_r_reg[0] ), .rd_wr_ns(rd_wr_ns), .req_periodic_rd_r(req_periodic_rd_r), .req_priority_r(req_priority_r), .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ), .row_hit_r_0(row_hit_r_0), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .start_wtp_timer0(start_wtp_timer0), .tail_r_3(tail_r_3), .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg)); ddr3_ifmig_7series_v4_0_bank_queue__parameterized0 bank_queue0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .accept_internal_r(accept_internal_r), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg(bank_queue0_n_18), .act_wait_r_lcl_reg_0(row_cmd_wr), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .bm_end_r1_reg(bm_end_r1_reg_1), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_2), .bm_end_r1_reg_2(bm_end_r1_reg_3), .bm_end_r1_reg_3(\ras_timer_r_reg[1] ), .bm_end_r1_reg_4(bm_end_r1_reg_4), .cmd(cmd[0]), .col_wait_r(col_wait_r), .col_wait_r_reg(bank_state0_n_16), .demand_priority_ns(demand_priority_ns), .demand_priority_r_reg(bank_state0_n_27), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[0]_0 (\grant_r_reg[0]_1 ), .\grant_r_reg[1] (\grant_r_reg[1] [1]), .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ), .granted_col_r_reg(granted_col_r_reg), .granted_row_ns(granted_row_ns), .granted_row_r_reg(granted_row_r_reg), .head_r_lcl_reg_0(head_r_lcl_reg), .head_r_lcl_reg_1(head_r_lcl_reg_0), .head_r_lcl_reg_2(head_r_lcl_reg_1), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(idle_r_lcl_reg_0), .idle_r_lcl_reg_2(idle_r_lcl_reg_1), .idle_r_lcl_reg_3(idle_r_lcl_reg_2), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .\order_q_r_reg[0]_0 (\order_q_r_reg[0] ), .\order_q_r_reg[0]_1 (\order_q_r_reg[0]_0 ), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0), .p_9_in(p_9_in), .pass_open_bank_ns(pass_open_bank_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1), .periodic_rd_insert(periodic_rd_insert), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r(pre_bm_end_r), .pre_bm_end_r_reg_0(pre_bm_end_r_reg), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_passing_open_bank_r_0(pre_passing_open_bank_r_0), .q_entry_r_4(q_entry_r_4), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_0 ), .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_1 ), .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_2 ), .q_has_priority(q_has_priority), .q_has_priority_r_reg_0(q_has_priority_r_reg_0), .q_has_rd(q_has_rd), .q_has_rd_r_reg_0(q_has_rd_r_reg), .\ras_timer_r_reg[1] (\ras_timer_r_reg[1]_0 ), .\ras_timer_r_reg[2] (\ras_timer_r_reg[2]_0 ), .ras_timer_zero_r(ras_timer_zero_r), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .rb_hit_busies_ns(rb_hit_busies_ns), .rb_hit_busies_r(rb_hit_busies_r), .rb_hit_busy_r(rb_hit_busy_r), .rb_hit_busy_r_reg(\q_entry_r_reg[0] ), .rb_hit_busy_r_reg_0(q_has_priority_r_reg), .rd_wr_ns(rd_wr_ns), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(\ras_timer_r_reg[0] ), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .req_bank_rdy_r_reg(req_bank_rdy_r_reg), .\req_data_buf_addr_r_reg[4] (E), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg(pass_open_bank_r_lcl_reg), .req_wr_r_lcl_reg_0(bm_end_r1_reg), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg), .\rp_timer.rp_timer_r_reg[1] (\rp_timer.rp_timer_r_reg[1] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .set_order_q(set_order_q), .tail_r_3(tail_r_3), .use_addr(use_addr), .wait_for_maint_ns(wait_for_maint_ns), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_ifmig_7series_v4_0_bank_state__parameterized0 bank_state0 (.CLK(CLK), .D(ras_timer_passed_ns), .Q(ras_timer_zero_r_reg), .SR(SR), .accept_r_reg(accept_r_reg), .act_this_rank_r(act_this_rank_r), .\act_this_rank_r_reg[0]_0 (row_cmd_wr), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(\rp_timer.rp_timer_r_reg[1] ), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg_0(bm_end_r1_reg_2), .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ), .col_wait_r(col_wait_r), .demand_priority_ns(demand_priority_ns), .demand_priority_r_2(demand_priority_r_2), .demand_priority_r_reg_0(bank_state0_n_16), .demand_priority_r_reg_1(bank_state0_n_27), .demanded_prior_r(demanded_prior_r), .demanded_prior_r_1(demanded_prior_r_1), .demanded_prior_r_reg_0(demand_priority_r), .\grant_r_reg[0] (\grant_r_reg[0]_0 ), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ), .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 [1]), .granted_col_r_reg(granted_col_r_reg_0), .mc_cs_n_ns(mc_cs_n_ns), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r0(ofs_rdy_r0), .\order_q_r_reg[0] (req_bank_rdy_r_reg), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(bm_end_r1_reg_1), .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r_reg(bm_end_r1_reg_0), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r_reg(bank_queue0_n_18), .pre_wait_r(pre_wait_r), .q_has_rd(q_has_rd), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2]_0 ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2]_1 ), .ras_timer_zero_r(ras_timer_zero_r), .\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 (\rcd_timer_gt_2.rcd_timer_r_reg[0] ), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(bank_compare0_n_12), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg), .req_bank_rdy_ns_1(req_bank_rdy_ns_1), .req_bank_rdy_r(req_bank_rdy_r), .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_0), .\req_row_r_lcl_reg[10] (req_row_r), .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ), .req_wr_r_lcl_reg(bm_end_r1_reg), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rtp_timer_ns1(rtp_timer_ns1), .start_wtp_timer0(start_wtp_timer0), .tail_r_3(tail_r_3), .wr_this_rank_r(wr_this_rank_r)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_common" *) module ddr3_ifmig_7series_v4_0_bank_common (\maint_controller.maint_hit_busies_r_reg[0]_0 , insert_maint_r1_lcl_reg, accept_internal_r, was_wr_reg_0, head_r_lcl_reg, accept_ns, was_wr, req_periodic_rd_r_lcl_reg, wait_for_maint_ns, wait_for_maint_r_lcl_reg, D, wait_for_maint_ns_0, wait_for_maint_r_lcl_reg_0, \req_cmd_r_reg[1] , periodic_rd_insert, head_r_lcl_reg_0, pass_open_bank_r_lcl_reg, q_has_rd_r_reg, q_has_priority_r_reg, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 , CLK, p_9_in, maint_srx_r, SR, \periodic_read_request.periodic_rd_r_lcl_reg , maint_req_r, rstdiv0_sync_r1_reg_rep__21, wait_for_maint_r_2, idle_r_lcl_reg, idle_r_lcl_reg_0, init_calib_complete_reg_rep__6, periodic_rd_r, cmd, Q, \maint_controller.maint_wip_r_lcl_reg_0 , clear_req, use_addr, head_r, E, wait_for_maint_r, \req_cmd_r_reg[1]_0 , req_wr_r_lcl_reg, idle_r, rb_hit_busy_r_reg, rb_hit_busy_r, \generate_maint_cmds.insert_maint_r_lcl_reg_0 , \maintenance_request.maint_zq_r_lcl_reg , \generate_maint_cmds.insert_maint_r_lcl_reg_1 , p_52_out, rstdiv0_sync_r1_reg_rep__20, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ); output \maint_controller.maint_hit_busies_r_reg[0]_0 ; output insert_maint_r1_lcl_reg; output accept_internal_r; output was_wr_reg_0; output head_r_lcl_reg; output accept_ns; output was_wr; output req_periodic_rd_r_lcl_reg; output wait_for_maint_ns; output wait_for_maint_r_lcl_reg; output [1:0]D; output wait_for_maint_ns_0; output wait_for_maint_r_lcl_reg_0; output [1:0]\req_cmd_r_reg[1] ; output periodic_rd_insert; output head_r_lcl_reg_0; output pass_open_bank_r_lcl_reg; output q_has_rd_r_reg; output q_has_priority_r_reg; output [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; input CLK; input p_9_in; input maint_srx_r; input [0:0]SR; input \periodic_read_request.periodic_rd_r_lcl_reg ; input maint_req_r; input rstdiv0_sync_r1_reg_rep__21; input wait_for_maint_r_2; input [0:0]idle_r_lcl_reg; input [0:0]idle_r_lcl_reg_0; input init_calib_complete_reg_rep__6; input periodic_rd_r; input [1:0]cmd; input [1:0]Q; input \maint_controller.maint_wip_r_lcl_reg_0 ; input clear_req; input use_addr; input [1:0]head_r; input [0:0]E; input wait_for_maint_r; input [1:0]\req_cmd_r_reg[1]_0 ; input req_wr_r_lcl_reg; input [0:0]idle_r; input [0:0]rb_hit_busy_r_reg; input [0:0]rb_hit_busy_r; input \generate_maint_cmds.insert_maint_r_lcl_reg_0 ; input \maintenance_request.maint_zq_r_lcl_reg ; input \generate_maint_cmds.insert_maint_r_lcl_reg_1 ; input p_52_out; input rstdiv0_sync_r1_reg_rep__20; input [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ; wire CLK; wire [1:0]D; wire [0:0]E; wire [1:0]Q; wire [0:0]SR; wire accept_internal_r; wire accept_ns; wire clear_req; wire [1:0]cmd; wire \generate_maint_cmds.insert_maint_r_lcl_reg_0 ; wire \generate_maint_cmds.insert_maint_r_lcl_reg_1 ; wire [1:0]head_r; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire [0:0]idle_r; wire [0:0]idle_r_lcl_reg; wire [0:0]idle_r_lcl_reg_0; wire init_calib_complete_reg_rep__6; wire insert_maint_ns; wire insert_maint_r1_lcl_reg; wire \maint_controller.maint_hit_busies_r_reg[0]_0 ; wire \maint_controller.maint_wip_r_lcl_i_2_n_0 ; wire \maint_controller.maint_wip_r_lcl_reg_0 ; wire [1:0]maint_hit_busies_ns; wire [1:0]maint_hit_busies_r; wire maint_rdy; wire maint_rdy_r1; wire maint_req_r; wire maint_srx_r; wire maint_srx_r1; wire maint_wip_ns; wire \maintenance_request.maint_zq_r_lcl_reg ; wire p_52_out; wire p_9_in; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_ns; wire periodic_rd_insert; wire periodic_rd_r; wire \periodic_read_request.periodic_rd_r_lcl_reg ; wire q_has_priority_r_reg; wire q_has_rd_r_reg; wire [0:0]rb_hit_busy_r; wire [0:0]rb_hit_busy_r_reg; wire [1:0]\req_cmd_r_reg[1] ; wire [1:0]\req_cmd_r_reg[1]_0 ; wire req_periodic_rd_r_lcl_reg; wire req_wr_r_lcl_reg; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; wire [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ; wire [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ; wire [7:2]rfc_zq_xsdll_timer_ns; wire [7:2]rfc_zq_xsdll_timer_r; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire use_addr; wire wait_for_maint_ns; wire wait_for_maint_ns_0; wire wait_for_maint_r; wire wait_for_maint_r_2; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire was_wr; wire was_wr0; wire was_wr_reg_0; FDRE #( .INIT(1'b0)) accept_internal_r_reg (.C(CLK), .CE(1'b1), .D(p_9_in), .Q(accept_internal_r), .R(1'b0)); LUT6 #( .INIT(64'hE0000000E0E0E0E0)) accept_r_i_1 (.I0(idle_r_lcl_reg), .I1(idle_r_lcl_reg_0), .I2(init_calib_complete_reg_rep__6), .I3(was_wr_reg_0), .I4(req_periodic_rd_r_lcl_reg), .I5(periodic_rd_r), .O(accept_ns)); FDRE #( .INIT(1'b0)) accept_r_reg (.C(CLK), .CE(1'b1), .D(accept_ns), .Q(head_r_lcl_reg), .R(1'b0)); LUT6 #( .INIT(64'h444444444444444F)) \generate_maint_cmds.insert_maint_r_lcl_i_1 (.I0(maint_srx_r1), .I1(maint_srx_r), .I2(maint_rdy_r1), .I3(maint_hit_busies_ns[1]), .I4(maint_hit_busies_ns[0]), .I5(\maint_controller.maint_wip_r_lcl_reg_0 ), .O(insert_maint_ns)); FDRE #( .INIT(1'b0)) \generate_maint_cmds.insert_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(insert_maint_ns), .Q(insert_maint_r1_lcl_reg), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1064" *) LUT4 #( .INIT(16'h07FF)) i___11_i_1 (.I0(use_addr), .I1(head_r_lcl_reg), .I2(was_wr_reg_0), .I3(rb_hit_busy_r_reg), .O(pass_open_bank_r_lcl_reg)); LUT4 #( .INIT(16'hFFFE)) i___20_i_1 (.I0(rfc_zq_xsdll_timer_r[3]), .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .I3(rfc_zq_xsdll_timer_r[2]), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 )); (* SOFT_HLUTNM = "soft_lutpair1063" *) LUT3 #( .INIT(8'h15)) i___35_i_2 (.I0(was_wr_reg_0), .I1(head_r_lcl_reg), .I2(use_addr), .O(q_has_priority_r_reg)); LUT5 #( .INIT(32'hE0000000)) i___4_i_1 (.I0(was_wr_reg_0), .I1(use_addr), .I2(accept_internal_r), .I3(head_r[0]), .I4(idle_r), .O(wait_for_maint_r_lcl_reg_0)); (* SOFT_HLUTNM = "soft_lutpair1064" *) LUT4 #( .INIT(16'h07FF)) i___4_i_2 (.I0(use_addr), .I1(head_r_lcl_reg), .I2(was_wr_reg_0), .I3(rb_hit_busy_r), .O(q_has_rd_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1063" *) LUT5 #( .INIT(32'hF80707F8)) i___5_i_1 (.I0(use_addr), .I1(head_r_lcl_reg), .I2(was_wr_reg_0), .I3(E), .I4(idle_r), .O(head_r_lcl_reg_0)); LUT5 #( .INIT(32'hE0000000)) i___8_i_1 (.I0(was_wr_reg_0), .I1(use_addr), .I2(accept_internal_r), .I3(head_r[1]), .I4(E), .O(wait_for_maint_r_lcl_reg)); LUT6 #( .INIT(64'h888A8888888A888A)) \maint_controller.maint_hit_busies_r[0]_i_1 (.I0(req_wr_r_lcl_reg), .I1(maint_hit_busies_r[0]), .I2(idle_r_lcl_reg), .I3(\maint_controller.maint_hit_busies_r_reg[0]_0 ), .I4(req_periodic_rd_r_lcl_reg), .I5(maint_req_r), .O(maint_hit_busies_ns[0])); LUT6 #( .INIT(64'h4445444444454445)) \maint_controller.maint_hit_busies_r[1]_i_1 (.I0(clear_req), .I1(maint_hit_busies_r[1]), .I2(idle_r_lcl_reg_0), .I3(\maint_controller.maint_hit_busies_r_reg[0]_0 ), .I4(req_periodic_rd_r_lcl_reg), .I5(maint_req_r), .O(maint_hit_busies_ns[1])); FDRE #( .INIT(1'b0)) \maint_controller.maint_hit_busies_r_reg[0] (.C(CLK), .CE(1'b1), .D(maint_hit_busies_ns[0]), .Q(maint_hit_busies_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \maint_controller.maint_hit_busies_r_reg[1] (.C(CLK), .CE(1'b1), .D(maint_hit_busies_ns[1]), .Q(maint_hit_busies_r[1]), .R(1'b0)); LUT5 #( .INIT(32'h00005455)) \maint_controller.maint_rdy_r1_i_1 (.I0(maint_hit_busies_ns[1]), .I1(p_52_out), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(maint_hit_busies_r[0]), .I4(\maint_controller.maint_wip_r_lcl_reg_0 ), .O(maint_rdy)); FDRE #( .INIT(1'b0)) \maint_controller.maint_rdy_r1_reg (.C(CLK), .CE(1'b1), .D(maint_rdy), .Q(maint_rdy_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \maint_controller.maint_srx_r1_reg (.C(CLK), .CE(1'b1), .D(maint_srx_r), .Q(maint_srx_r1), .R(1'b0)); LUT6 #( .INIT(64'h000000000000FFBF)) \maint_controller.maint_wip_r_lcl_i_1 (.I0(rfc_zq_xsdll_timer_r[2]), .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .I3(\maint_controller.maint_wip_r_lcl_i_2_n_0 ), .I4(\maint_controller.maint_wip_r_lcl_reg_0 ), .I5(rstdiv0_sync_r1_reg_rep__21), .O(maint_wip_ns)); LUT5 #( .INIT(32'hFFFFFFFE)) \maint_controller.maint_wip_r_lcl_i_2 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]), .I1(rfc_zq_xsdll_timer_r[5]), .I2(rfc_zq_xsdll_timer_r[7]), .I3(rfc_zq_xsdll_timer_r[3]), .I4(rfc_zq_xsdll_timer_r[6]), .O(\maint_controller.maint_wip_r_lcl_i_2_n_0 )); FDRE #( .INIT(1'b0)) \maint_controller.maint_wip_r_lcl_reg (.C(CLK), .CE(1'b1), .D(maint_wip_ns), .Q(\maint_controller.maint_hit_busies_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00E0E0E000000000)) periodic_rd_ack_r_lcl_i_1 (.I0(idle_r_lcl_reg), .I1(idle_r_lcl_reg_0), .I2(init_calib_complete_reg_rep__6), .I3(was_wr_reg_0), .I4(req_periodic_rd_r_lcl_reg), .I5(periodic_rd_r), .O(periodic_rd_ack_ns)); FDRE #( .INIT(1'b0)) periodic_rd_ack_r_lcl_reg (.C(CLK), .CE(1'b1), .D(periodic_rd_ack_ns), .Q(was_wr_reg_0), .R(1'b0)); FDRE #( .INIT(1'b0)) periodic_rd_cntr_r_reg (.C(CLK), .CE(1'b1), .D(\periodic_read_request.periodic_rd_r_lcl_reg ), .Q(req_periodic_rd_r_lcl_reg), .R(SR)); LUT6 #( .INIT(64'hBFAAFFFFBFAA0000)) \req_cmd_r[0]_i_1 (.I0(cmd[0]), .I1(was_wr_reg_0), .I2(req_periodic_rd_r_lcl_reg), .I3(periodic_rd_r), .I4(idle_r_lcl_reg_0), .I5(Q[0]), .O(D[0])); LUT6 #( .INIT(64'hBFAAFFFFBFAA0000)) \req_cmd_r[0]_i_1__0 (.I0(cmd[0]), .I1(was_wr_reg_0), .I2(req_periodic_rd_r_lcl_reg), .I3(periodic_rd_r), .I4(idle_r_lcl_reg), .I5(\req_cmd_r_reg[1]_0 [0]), .O(\req_cmd_r_reg[1] [0])); LUT6 #( .INIT(64'h80AAFFFF80AA0000)) \req_cmd_r[1]_i_1 (.I0(cmd[1]), .I1(was_wr_reg_0), .I2(req_periodic_rd_r_lcl_reg), .I3(periodic_rd_r), .I4(idle_r_lcl_reg_0), .I5(Q[1]), .O(D[1])); LUT6 #( .INIT(64'h80AAFFFF80AA0000)) \req_cmd_r[1]_i_1__0 (.I0(cmd[1]), .I1(was_wr_reg_0), .I2(req_periodic_rd_r_lcl_reg), .I3(periodic_rd_r), .I4(idle_r_lcl_reg), .I5(\req_cmd_r_reg[1]_0 [1]), .O(\req_cmd_r_reg[1] [1])); (* SOFT_HLUTNM = "soft_lutpair1065" *) LUT3 #( .INIT(8'h2A)) req_periodic_rd_r_lcl_i_1 (.I0(periodic_rd_r), .I1(req_periodic_rd_r_lcl_reg), .I2(was_wr_reg_0), .O(periodic_rd_insert)); LUT5 #( .INIT(32'h11100001)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 (.I0(insert_maint_r1_lcl_reg), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .I4(rfc_zq_xsdll_timer_r[2]), .O(rfc_zq_xsdll_timer_ns[2])); LUT6 #( .INIT(64'hEEEEEEEBAAAAAAAA)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg ), .I1(rfc_zq_xsdll_timer_r[3]), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .I4(rfc_zq_xsdll_timer_r[2]), .I5(\generate_maint_cmds.insert_maint_r_lcl_reg_1 ), .O(rfc_zq_xsdll_timer_ns[3])); LUT6 #( .INIT(64'hAAAAAAAAAAAAEEEB)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg ), .I1(rfc_zq_xsdll_timer_r[5]), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ), .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]), .I4(rstdiv0_sync_r1_reg_rep__21), .I5(insert_maint_r1_lcl_reg), .O(rfc_zq_xsdll_timer_ns[5])); LUT6 #( .INIT(64'h1111111000000001)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 (.I0(insert_maint_r1_lcl_reg), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]), .I3(rfc_zq_xsdll_timer_r[5]), .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ), .I5(rfc_zq_xsdll_timer_r[6]), .O(rfc_zq_xsdll_timer_ns[6])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 (.I0(\maint_controller.maint_wip_r_lcl_i_2_n_0 ), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(insert_maint_r1_lcl_reg), .I3(rfc_zq_xsdll_timer_r[2]), .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'hFFFFFFFF02020200)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2 (.I0(rfc_zq_xsdll_timer_r[7]), .I1(insert_maint_r1_lcl_reg), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(rfc_zq_xsdll_timer_r[6]), .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ), .I5(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ), .O(rfc_zq_xsdll_timer_ns[7])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]), .I1(rfc_zq_xsdll_timer_r[5]), .I2(rfc_zq_xsdll_timer_r[2]), .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .I5(rfc_zq_xsdll_timer_r[3]), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [0]), .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [1]), .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[2]), .Q(rfc_zq_xsdll_timer_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[3]), .Q(rfc_zq_xsdll_timer_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [2]), .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[5]), .Q(rfc_zq_xsdll_timer_r[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[6]), .Q(rfc_zq_xsdll_timer_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[7]), .Q(rfc_zq_xsdll_timer_r[7]), .R(1'b0)); LUT6 #( .INIT(64'h00BA00BA00BA0000)) wait_for_maint_r_lcl_i_1 (.I0(\maint_controller.maint_hit_busies_r_reg[0]_0 ), .I1(req_periodic_rd_r_lcl_reg), .I2(maint_req_r), .I3(rstdiv0_sync_r1_reg_rep__21), .I4(wait_for_maint_r_lcl_reg), .I5(wait_for_maint_r_2), .O(wait_for_maint_ns)); LUT6 #( .INIT(64'h00BA00BA00BA0000)) wait_for_maint_r_lcl_i_1__0 (.I0(\maint_controller.maint_hit_busies_r_reg[0]_0 ), .I1(req_periodic_rd_r_lcl_reg), .I2(maint_req_r), .I3(rstdiv0_sync_r1_reg_rep__21), .I4(wait_for_maint_r_lcl_reg_0), .I5(wait_for_maint_r), .O(wait_for_maint_ns_0)); (* SOFT_HLUTNM = "soft_lutpair1065" *) LUT3 #( .INIT(8'h8A)) was_wr_i_1 (.I0(cmd[0]), .I1(was_wr_reg_0), .I2(periodic_rd_r), .O(was_wr0)); FDRE #( .INIT(1'b0)) was_wr_reg (.C(CLK), .CE(1'b1), .D(was_wr0), .Q(was_wr), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_compare" *) module ddr3_ifmig_7series_v4_0_bank_compare (q_has_priority_r_reg, \rd_this_rank_r_reg[0] , req_periodic_rd_r, bm_end_r1_reg, req_priority_r, row_hit_r_0, Q, pass_open_bank_ns, pass_open_bank_r_lcl_reg, \ras_timer_r_reg[2] , \q_entry_r_reg[0] , ras_timer_zero_r_reg, start_wtp_timer0, \cmd_pipe_plus.mc_address_reg[14] , \cmd_pipe_plus.mc_address_reg[40] , \cmd_pipe_plus.mc_bank_reg[2] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_address_reg[24] , p_28_out, CLK, rd_wr_ns, idle_r_lcl_reg, periodic_rd_insert, hi_priority, cmd, accept_r_reg, tail_r_3, pre_wait_r, pass_open_bank_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[1] , pre_bm_end_r, rb_hit_busy_r, pre_bm_end_r_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , \maint_controller.maint_wip_r_lcl_reg , periodic_rd_cntr_r_reg, maint_req_r, wait_for_maint_r_lcl_reg, \app_addr_r1_reg[27] , act_wait_r_lcl_reg, \grant_r_reg[1]_0 , act_wait_r_lcl_reg_0, \req_row_r_lcl_reg[10]_0 , \app_addr_r1_reg[12] , idle_r_lcl_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , D, \app_addr_r1_reg[9] ); output q_has_priority_r_reg; output \rd_this_rank_r_reg[0] ; output [0:0]req_periodic_rd_r; output bm_end_r1_reg; output req_priority_r; output row_hit_r_0; output [1:0]Q; output pass_open_bank_ns; output pass_open_bank_r_lcl_reg; output \ras_timer_r_reg[2] ; output \q_entry_r_reg[0] ; output ras_timer_zero_r_reg; output start_wtp_timer0; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output \cmd_pipe_plus.mc_address_reg[40] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input p_28_out; input CLK; input rd_wr_ns; input idle_r_lcl_reg; input periodic_rd_insert; input hi_priority; input [1:0]cmd; input accept_r_reg; input tail_r_3; input pre_wait_r; input pass_open_bank_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\grant_r_reg[1] ; input pre_bm_end_r; input [0:0]rb_hit_busy_r; input pre_bm_end_r_reg; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; input \maint_controller.maint_wip_r_lcl_reg ; input periodic_rd_cntr_r_reg; input maint_req_r; input wait_for_maint_r_lcl_reg; input [14:0]\app_addr_r1_reg[27] ; input act_wait_r_lcl_reg; input [1:0]\grant_r_reg[1]_0 ; input act_wait_r_lcl_reg_0; input [0:0]\req_row_r_lcl_reg[10]_0 ; input [2:0]\app_addr_r1_reg[12] ; input idle_r_lcl_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [1:0]D; input [6:0]\app_addr_r1_reg[9] ; wire CLK; wire [1:0]D; wire [1:0]Q; wire accept_r_reg; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire bm_end_r1_reg; wire [1:0]cmd; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire \cmd_pipe_plus.mc_address_reg[40] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire [0:0]\grant_r_reg[1] ; wire [1:0]\grant_r_reg[1]_0 ; wire hi_priority; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire p_28_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_i_2_n_0; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire pre_bm_end_r; wire pre_bm_end_r_reg; wire pre_wait_r; wire \q_entry_r_reg[0] ; wire q_has_priority_r_reg; wire \ras_timer_r_reg[2] ; wire ras_timer_zero_r_reg; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire [0:0]rb_hit_busy_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire [0:0]\req_row_r_lcl_reg[10]_0 ; wire req_wr_r_lcl0; wire row_hit_ns_carry__0_i_1__0_n_0; wire row_hit_ns_carry__0_n_3; wire row_hit_ns_carry_i_1__0_n_0; wire row_hit_ns_carry_i_2__0_n_0; wire row_hit_ns_carry_i_3__0_n_0; wire row_hit_ns_carry_i_4__0_n_0; wire row_hit_ns_carry_n_0; wire row_hit_ns_carry_n_1; wire row_hit_ns_carry_n_2; wire row_hit_ns_carry_n_3; wire row_hit_r_0; wire rstdiv0_sync_r1_reg_rep__21; wire start_wtp_timer0; wire tail_r_3; wire wait_for_maint_r_lcl_reg; wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED; wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED; wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1057" *) LUT4 #( .INIT(16'h7000)) act_wait_r_lcl_i_4 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(pass_open_bank_r_lcl_reg_0), .I3(\grant_r_reg[1] ), .O(\ras_timer_r_reg[2] )); LUT6 #( .INIT(64'h8F80808080808080)) \cmd_pipe_plus.mc_address[40]_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[14] [10]), .I1(act_wait_r_lcl_reg), .I2(\grant_r_reg[1]_0 [1]), .I3(\grant_r_reg[1]_0 [0]), .I4(act_wait_r_lcl_reg_0), .I5(\req_row_r_lcl_reg[10]_0 ), .O(\cmd_pipe_plus.mc_address_reg[40] )); LUT4 #( .INIT(16'h6999)) i___12_i_1 (.I0(q_has_priority_r_reg), .I1(rb_hit_busy_r), .I2(pre_bm_end_r_reg), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .O(\q_entry_r_reg[0] )); LUT6 #( .INIT(64'hFFFFFFFFBFAAAAAA)) i___13_i_2 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg_0), .I4(\grant_r_reg[1] ), .I5(pre_bm_end_r), .O(pass_open_bank_r_lcl_reg)); LUT6 #( .INIT(64'h5555555500000400)) pass_open_bank_r_lcl_i_1 (.I0(pass_open_bank_r_lcl_reg), .I1(pass_open_bank_r_lcl_i_2_n_0), .I2(accept_r_reg), .I3(tail_r_3), .I4(pre_wait_r), .I5(pass_open_bank_r_lcl_reg_0), .O(pass_open_bank_ns)); LUT5 #( .INIT(32'hAAAA2022)) pass_open_bank_r_lcl_i_2 (.I0(row_hit_r_0), .I1(\maint_controller.maint_wip_r_lcl_reg ), .I2(periodic_rd_cntr_r_reg), .I3(maint_req_r), .I4(wait_for_maint_r_lcl_reg), .O(pass_open_bank_r_lcl_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1057" *) LUT2 #( .INIT(4'hB)) ras_timer_zero_r_i_2 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[1] ), .O(ras_timer_zero_r_reg)); FDRE #( .INIT(1'b0)) rb_hit_busy_r_reg (.C(CLK), .CE(1'b1), .D(p_28_out), .Q(q_has_priority_r_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) rd_wr_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rd_wr_ns), .Q(\rd_this_rank_r_reg[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_bank_r_lcl_reg[0] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[12] [0]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_bank_r_lcl_reg[1] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[12] [1]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_bank_r_lcl_reg[2] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[12] [2]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [0]), .Q(\cmd_pipe_plus.mc_address_reg[24] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [1]), .Q(\cmd_pipe_plus.mc_address_reg[24] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[5] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [2]), .Q(\cmd_pipe_plus.mc_address_reg[24] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[6] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [3]), .Q(\cmd_pipe_plus.mc_address_reg[24] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[7] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [4]), .Q(\cmd_pipe_plus.mc_address_reg[24] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[8] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [5]), .Q(\cmd_pipe_plus.mc_address_reg[24] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[9] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [6]), .Q(\cmd_pipe_plus.mc_address_reg[24] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[0] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[1] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[2] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) req_periodic_rd_r_lcl_reg (.C(CLK), .CE(idle_r_lcl_reg), .D(periodic_rd_insert), .Q(req_periodic_rd_r), .R(1'b0)); FDRE #( .INIT(1'b0)) req_priority_r_reg (.C(CLK), .CE(idle_r_lcl_reg), .D(hi_priority), .Q(req_priority_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[0] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [0]), .Q(\cmd_pipe_plus.mc_address_reg[14] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[10] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [10]), .Q(\cmd_pipe_plus.mc_address_reg[14] [10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[11] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [11]), .Q(\cmd_pipe_plus.mc_address_reg[14] [11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[12] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [12]), .Q(\cmd_pipe_plus.mc_address_reg[14] [12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[13] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [13]), .Q(\cmd_pipe_plus.mc_address_reg[14] [13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[14] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [14]), .Q(\cmd_pipe_plus.mc_address_reg[14] [14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[1] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [1]), .Q(\cmd_pipe_plus.mc_address_reg[14] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[2] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [2]), .Q(\cmd_pipe_plus.mc_address_reg[14] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[3] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [3]), .Q(\cmd_pipe_plus.mc_address_reg[14] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[4] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [4]), .Q(\cmd_pipe_plus.mc_address_reg[14] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[5] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [5]), .Q(\cmd_pipe_plus.mc_address_reg[14] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[6] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [6]), .Q(\cmd_pipe_plus.mc_address_reg[14] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[7] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [7]), .Q(\cmd_pipe_plus.mc_address_reg[14] [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[8] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [8]), .Q(\cmd_pipe_plus.mc_address_reg[14] [8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[9] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [9]), .Q(\cmd_pipe_plus.mc_address_reg[14] [9]), .R(1'b0)); LUT6 #( .INIT(64'h00AFCCAF00AFFFAF)) req_wr_r_lcl_i_1 (.I0(Q[1]), .I1(cmd[1]), .I2(Q[0]), .I3(idle_r_lcl_reg), .I4(periodic_rd_insert), .I5(cmd[0]), .O(req_wr_r_lcl0)); FDRE #( .INIT(1'b0)) req_wr_r_lcl_reg (.C(CLK), .CE(idle_r_lcl_reg), .D(req_wr_r_lcl0), .Q(bm_end_r1_reg), .R(1'b0)); CARRY4 row_hit_ns_carry (.CI(1'b0), .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]), .S({row_hit_ns_carry_i_1__0_n_0,row_hit_ns_carry_i_2__0_n_0,row_hit_ns_carry_i_3__0_n_0,row_hit_ns_carry_i_4__0_n_0})); CARRY4 row_hit_ns_carry__0 (.CI(row_hit_ns_carry_n_0), .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__0_n_0})); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry__0_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [14]), .I1(\app_addr_r1_reg[27] [14]), .I2(\cmd_pipe_plus.mc_address_reg[14] [13]), .I3(\app_addr_r1_reg[27] [13]), .I4(\app_addr_r1_reg[27] [12]), .I5(\cmd_pipe_plus.mc_address_reg[14] [12]), .O(row_hit_ns_carry__0_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [11]), .I1(\app_addr_r1_reg[27] [11]), .I2(\cmd_pipe_plus.mc_address_reg[14] [10]), .I3(\app_addr_r1_reg[27] [10]), .I4(\app_addr_r1_reg[27] [9]), .I5(\cmd_pipe_plus.mc_address_reg[14] [9]), .O(row_hit_ns_carry_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [8]), .I1(\app_addr_r1_reg[27] [8]), .I2(\cmd_pipe_plus.mc_address_reg[14] [6]), .I3(\app_addr_r1_reg[27] [6]), .I4(\app_addr_r1_reg[27] [7]), .I5(\cmd_pipe_plus.mc_address_reg[14] [7]), .O(row_hit_ns_carry_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_3__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [5]), .I1(\app_addr_r1_reg[27] [5]), .I2(\cmd_pipe_plus.mc_address_reg[14] [3]), .I3(\app_addr_r1_reg[27] [3]), .I4(\app_addr_r1_reg[27] [4]), .I5(\cmd_pipe_plus.mc_address_reg[14] [4]), .O(row_hit_ns_carry_i_3__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_4__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [2]), .I1(\app_addr_r1_reg[27] [2]), .I2(\cmd_pipe_plus.mc_address_reg[14] [0]), .I3(\app_addr_r1_reg[27] [0]), .I4(\app_addr_r1_reg[27] [1]), .I5(\cmd_pipe_plus.mc_address_reg[14] [1]), .O(row_hit_ns_carry_i_4__0_n_0)); FDRE #( .INIT(1'b0)) row_hit_r_reg (.C(CLK), .CE(1'b1), .D(row_hit_ns_carry__0_n_3), .Q(row_hit_r_0), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wr_this_rank_r[0]_i_1__0 (.I0(\rd_this_rank_r_reg[0] ), .O(start_wtp_timer0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_compare" *) module ddr3_ifmig_7series_v4_0_bank_compare_0 (rb_hit_busy_r, \rd_this_rank_r_reg[0] , req_periodic_rd_r, bm_end_r1_reg, req_priority_r, row_hit_r, granted_col_ns, granted_col_r_reg, Q, act_wait_r_lcl_reg, start_wtp_timer0, req_bank_rdy_r_reg, req_bank_rdy_ns, demand_priority_r_reg, ras_timer_zero_r_reg, pass_open_bank_r_lcl_reg, \cmd_pipe_plus.mc_address_reg[14] , \cmd_pipe_plus.mc_bank_reg[2] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_address_reg[24] , p_67_out, CLK, rd_wr_ns, idle_r_lcl_reg, periodic_rd_insert, hi_priority, col_wait_r_reg, \wtr_timer.wtr_cnt_r_reg[1] , pre_passing_open_bank_r_reg, col_wait_r, \grant_r_reg[0] , cmd, pass_open_bank_r_lcl_reg_0, \grant_r_reg[1] , override_demand_r_reg, \rnk_config_strobe_r_reg[0] , \order_q_r_reg[0] , rd_wr_r_lcl_reg_0, req_wr_r_lcl_reg_0, \maint_controller.maint_wip_r_lcl_reg , periodic_rd_cntr_r_reg, maint_req_r, wait_for_maint_r_lcl_reg, \app_addr_r1_reg[27] , \app_addr_r1_reg[12] , idle_r_lcl_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , D, \app_addr_r1_reg[9] ); output [0:0]rb_hit_busy_r; output \rd_this_rank_r_reg[0] ; output [0:0]req_periodic_rd_r; output bm_end_r1_reg; output req_priority_r; output row_hit_r; output granted_col_ns; output granted_col_r_reg; output [1:0]Q; output act_wait_r_lcl_reg; output start_wtp_timer0; output req_bank_rdy_r_reg; output req_bank_rdy_ns; output demand_priority_r_reg; output ras_timer_zero_r_reg; output pass_open_bank_r_lcl_reg; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input p_67_out; input CLK; input rd_wr_ns; input idle_r_lcl_reg; input periodic_rd_insert; input hi_priority; input col_wait_r_reg; input \wtr_timer.wtr_cnt_r_reg[1] ; input pre_passing_open_bank_r_reg; input col_wait_r; input \grant_r_reg[0] ; input [1:0]cmd; input pass_open_bank_r_lcl_reg_0; input [1:0]\grant_r_reg[1] ; input override_demand_r_reg; input \rnk_config_strobe_r_reg[0] ; input \order_q_r_reg[0] ; input rd_wr_r_lcl_reg_0; input req_wr_r_lcl_reg_0; input \maint_controller.maint_wip_r_lcl_reg ; input periodic_rd_cntr_r_reg; input maint_req_r; input wait_for_maint_r_lcl_reg; input [14:0]\app_addr_r1_reg[27] ; input [2:0]\app_addr_r1_reg[12] ; input idle_r_lcl_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [1:0]D; input [6:0]\app_addr_r1_reg[9] ; wire CLK; wire [1:0]D; wire [1:0]Q; wire act_wait_r_lcl_reg; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire bm_end_r1_reg; wire [1:0]cmd; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r; wire col_wait_r_reg; wire demand_priority_r_reg; wire \grant_r[1]_i_7_n_0 ; wire \grant_r_reg[0] ; wire [1:0]\grant_r_reg[1] ; wire granted_col_ns; wire granted_col_r_reg; wire hi_priority; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire \order_q_r_reg[0] ; wire override_demand_r_reg; wire p_67_out; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire pre_passing_open_bank_r_reg; wire ras_timer_zero_r_reg; wire [0:0]rb_hit_busy_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_ns; wire req_bank_rdy_r_reg; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire req_wr_r_lcl0; wire req_wr_r_lcl_reg_0; wire \rnk_config_strobe_r_reg[0] ; wire row_hit_ns; wire row_hit_ns_carry__0_i_1_n_0; wire row_hit_ns_carry_i_1_n_0; wire row_hit_ns_carry_i_2_n_0; wire row_hit_ns_carry_i_3_n_0; wire row_hit_ns_carry_i_4_n_0; wire row_hit_ns_carry_n_0; wire row_hit_ns_carry_n_1; wire row_hit_ns_carry_n_2; wire row_hit_ns_carry_n_3; wire row_hit_r; wire start_wtp_timer0; wire wait_for_maint_r_lcl_reg; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED; wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED; wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1050" *) LUT4 #( .INIT(16'h7000)) act_wait_r_lcl_i_4__0 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(pass_open_bank_r_lcl_reg_0), .I3(\grant_r_reg[1] [0]), .O(act_wait_r_lcl_reg)); (* SOFT_HLUTNM = "soft_lutpair1049" *) LUT3 #( .INIT(8'h08)) demand_priority_r_i_3 (.I0(req_bank_rdy_r_reg), .I1(\order_q_r_reg[0] ), .I2(\rd_this_rank_r_reg[0] ), .O(demand_priority_r_reg)); LUT6 #( .INIT(64'h00A800FC00A80000)) \grant_r[1]_i_3 (.I0(\wtr_timer.wtr_cnt_r_reg[1] ), .I1(pre_passing_open_bank_r_reg), .I2(col_wait_r), .I3(\grant_r[1]_i_7_n_0 ), .I4(\rd_this_rank_r_reg[0] ), .I5(\grant_r_reg[0] ), .O(granted_col_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1049" *) LUT5 #( .INIT(32'hEEEEFEEE)) \grant_r[1]_i_7 (.I0(override_demand_r_reg), .I1(\rnk_config_strobe_r_reg[0] ), .I2(req_bank_rdy_r_reg), .I3(\order_q_r_reg[0] ), .I4(\rd_this_rank_r_reg[0] ), .O(\grant_r[1]_i_7_n_0 )); LUT2 #( .INIT(4'hE)) granted_col_r_i_1 (.I0(granted_col_r_reg), .I1(col_wait_r_reg), .O(granted_col_ns)); LUT6 #( .INIT(64'hBF00BFBFBFBFBFBF)) i___10_i_2 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[1] [0]), .I2(bm_end_r1_reg), .I3(rd_wr_r_lcl_reg_0), .I4(\grant_r_reg[1] [1]), .I5(req_wr_r_lcl_reg_0), .O(req_bank_rdy_r_reg)); LUT5 #( .INIT(32'hAAAA2022)) i___37_i_1 (.I0(row_hit_r), .I1(\maint_controller.maint_wip_r_lcl_reg ), .I2(periodic_rd_cntr_r_reg), .I3(maint_req_r), .I4(wait_for_maint_r_lcl_reg), .O(pass_open_bank_r_lcl_reg)); (* SOFT_HLUTNM = "soft_lutpair1050" *) LUT2 #( .INIT(4'hB)) ras_timer_zero_r_i_2__0 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[1] [0]), .O(ras_timer_zero_r_reg)); FDRE #( .INIT(1'b0)) rb_hit_busy_r_reg (.C(CLK), .CE(1'b1), .D(p_67_out), .Q(rb_hit_busy_r), .R(1'b0)); FDRE #( .INIT(1'b0)) rd_wr_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rd_wr_ns), .Q(\rd_this_rank_r_reg[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_bank_r_lcl_reg[0] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[12] [0]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_bank_r_lcl_reg[1] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[12] [1]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_bank_r_lcl_reg[2] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[12] [2]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [2]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1051" *) LUT4 #( .INIT(16'h8AAA)) req_bank_rdy_r_i_1 (.I0(col_wait_r), .I1(\rd_this_rank_r_reg[0] ), .I2(\order_q_r_reg[0] ), .I3(req_bank_rdy_r_reg), .O(req_bank_rdy_ns)); FDRE #( .INIT(1'b0)) \req_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [0]), .Q(\cmd_pipe_plus.mc_address_reg[24] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [1]), .Q(\cmd_pipe_plus.mc_address_reg[24] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[5] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [2]), .Q(\cmd_pipe_plus.mc_address_reg[24] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[6] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [3]), .Q(\cmd_pipe_plus.mc_address_reg[24] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[7] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [4]), .Q(\cmd_pipe_plus.mc_address_reg[24] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[8] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [5]), .Q(\cmd_pipe_plus.mc_address_reg[24] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[9] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[9] [6]), .Q(\cmd_pipe_plus.mc_address_reg[24] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[0] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[1] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[2] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_data_buf_addr_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) req_periodic_rd_r_lcl_reg (.C(CLK), .CE(idle_r_lcl_reg), .D(periodic_rd_insert), .Q(req_periodic_rd_r), .R(1'b0)); FDRE #( .INIT(1'b0)) req_priority_r_reg (.C(CLK), .CE(idle_r_lcl_reg), .D(hi_priority), .Q(req_priority_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[0] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [0]), .Q(\cmd_pipe_plus.mc_address_reg[14] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[10] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [10]), .Q(\cmd_pipe_plus.mc_address_reg[14] [10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[11] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [11]), .Q(\cmd_pipe_plus.mc_address_reg[14] [11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[12] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [12]), .Q(\cmd_pipe_plus.mc_address_reg[14] [12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[13] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [13]), .Q(\cmd_pipe_plus.mc_address_reg[14] [13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[14] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [14]), .Q(\cmd_pipe_plus.mc_address_reg[14] [14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[1] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [1]), .Q(\cmd_pipe_plus.mc_address_reg[14] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[2] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [2]), .Q(\cmd_pipe_plus.mc_address_reg[14] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[3] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [3]), .Q(\cmd_pipe_plus.mc_address_reg[14] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[4] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [4]), .Q(\cmd_pipe_plus.mc_address_reg[14] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[5] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [5]), .Q(\cmd_pipe_plus.mc_address_reg[14] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[6] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [6]), .Q(\cmd_pipe_plus.mc_address_reg[14] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[7] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [7]), .Q(\cmd_pipe_plus.mc_address_reg[14] [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[8] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [8]), .Q(\cmd_pipe_plus.mc_address_reg[14] [8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_row_r_lcl_reg[9] (.C(CLK), .CE(idle_r_lcl_reg), .D(\app_addr_r1_reg[27] [9]), .Q(\cmd_pipe_plus.mc_address_reg[14] [9]), .R(1'b0)); LUT6 #( .INIT(64'h00AFCCAF00AFFFAF)) req_wr_r_lcl_i_1__0 (.I0(Q[1]), .I1(cmd[1]), .I2(Q[0]), .I3(idle_r_lcl_reg), .I4(periodic_rd_insert), .I5(cmd[0]), .O(req_wr_r_lcl0)); FDRE #( .INIT(1'b0)) req_wr_r_lcl_reg (.C(CLK), .CE(idle_r_lcl_reg), .D(req_wr_r_lcl0), .Q(bm_end_r1_reg), .R(1'b0)); CARRY4 row_hit_ns_carry (.CI(1'b0), .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]), .S({row_hit_ns_carry_i_1_n_0,row_hit_ns_carry_i_2_n_0,row_hit_ns_carry_i_3_n_0,row_hit_ns_carry_i_4_n_0})); CARRY4 row_hit_ns_carry__0 (.CI(row_hit_ns_carry_n_0), .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1_n_0})); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry__0_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[14] [14]), .I1(\app_addr_r1_reg[27] [14]), .I2(\cmd_pipe_plus.mc_address_reg[14] [13]), .I3(\app_addr_r1_reg[27] [13]), .I4(\app_addr_r1_reg[27] [12]), .I5(\cmd_pipe_plus.mc_address_reg[14] [12]), .O(row_hit_ns_carry__0_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[14] [11]), .I1(\app_addr_r1_reg[27] [11]), .I2(\cmd_pipe_plus.mc_address_reg[14] [9]), .I3(\app_addr_r1_reg[27] [9]), .I4(\app_addr_r1_reg[27] [10]), .I5(\cmd_pipe_plus.mc_address_reg[14] [10]), .O(row_hit_ns_carry_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[14] [8]), .I1(\app_addr_r1_reg[27] [8]), .I2(\cmd_pipe_plus.mc_address_reg[14] [7]), .I3(\app_addr_r1_reg[27] [7]), .I4(\app_addr_r1_reg[27] [6]), .I5(\cmd_pipe_plus.mc_address_reg[14] [6]), .O(row_hit_ns_carry_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_3 (.I0(\cmd_pipe_plus.mc_address_reg[14] [5]), .I1(\app_addr_r1_reg[27] [5]), .I2(\cmd_pipe_plus.mc_address_reg[14] [4]), .I3(\app_addr_r1_reg[27] [4]), .I4(\app_addr_r1_reg[27] [3]), .I5(\cmd_pipe_plus.mc_address_reg[14] [3]), .O(row_hit_ns_carry_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[14] [2]), .I1(\app_addr_r1_reg[27] [2]), .I2(\cmd_pipe_plus.mc_address_reg[14] [1]), .I3(\app_addr_r1_reg[27] [1]), .I4(\app_addr_r1_reg[27] [0]), .I5(\cmd_pipe_plus.mc_address_reg[14] [0]), .O(row_hit_ns_carry_i_4_n_0)); FDRE #( .INIT(1'b0)) row_hit_r_reg (.C(CLK), .CE(1'b1), .D(row_hit_ns), .Q(row_hit_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1051" *) LUT1 #( .INIT(2'h1)) \wr_this_rank_r[0]_i_1 (.I0(\rd_this_rank_r_reg[0] ), .O(start_wtp_timer0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_mach" *) module ddr3_ifmig_7series_v4_0_bank_mach (maint_wip_r, insert_maint_r1_lcl_reg, insert_maint_r1, periodic_rd_ack_r, accept_ns, q_has_priority_r_reg, idle_r, idle_r_lcl_reg, idle_r_lcl_reg_0, was_wr, sent_col, DIC, rd_wr_r, col_data_buf_addr, \act_this_rank_r_reg[0] , cke_r, req_wr_r, row_hit_r, bm_end_r1, p_52_out, pre_wait_r, req_bank_rdy_ns, override_demand_ns, wr_this_rank_r, wait_for_maint_r, bm_end_r1_reg, pre_bm_end_r, row_hit_r_0, bm_end_r1_0, p_13_out, req_bank_rdy_ns_1, wait_for_maint_r_2, bm_end_r1_reg_0, rb_hit_busies_r, q_has_rd, q_has_priority, \rcd_timer_gt_2.rcd_timer_r_reg[0] , rnk_config_valid_r, periodic_rd_cntr_r, tail_r, q_entry_r, head_r, auto_pre_r, \order_q_r_reg[0] , ordered_r_lcl, order_q_r, tail_r_3, q_entry_r_4, auto_pre_r_5, order_q_r_6, \periodic_rd_generation.periodic_rd_timer_r_reg[0] , Q, read_this_rank, D, \rtw_timer.rtw_cnt_r_reg[1] , mc_odt_ns, col_rd_wr, mc_data_offset_2_ns, wait_for_maint_r_lcl_reg, clear_req, head_r_lcl_reg, q_has_priority_r_reg_0, \q_entry_r_reg[0] , \q_entry_r_reg[0]_0 , set_order_q, wait_for_maint_r_lcl_reg_0, head_r_lcl_reg_0, head_r_lcl_reg_1, set_order_q_7, \cmd_pipe_plus.mc_address_reg[0] , pass_open_bank_r_lcl_reg, \q_entry_r_reg[0]_1 , rtp_timer_r, q_has_rd_r_reg, \q_entry_r_reg[0]_2 , mc_cas_n_ns, mc_cs_n_ns, mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[5] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_bank_reg[2]_0 , \cmd_pipe_plus.mc_address_reg[25] , req_bank_rdy_r_reg, \rnk_config_strobe_r_reg[0] , \rnk_config_strobe_r_reg[0]_0 , ras_timer_zero_r_reg, head_r_lcl_reg_2, auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 , pass_open_bank_r_lcl_reg_0, \wtr_timer.wtr_cnt_r_reg[2] , act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , E, \cmd_pipe_plus.mc_address_reg[40] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[7] , \cmd_pipe_plus.mc_bank_reg[6] , \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_address_reg[43] , \cmd_pipe_plus.mc_address_reg[42] , \cmd_pipe_plus.mc_address_reg[41] , \cmd_pipe_plus.mc_address_reg[39] , \cmd_pipe_plus.mc_address_reg[38] , \cmd_pipe_plus.mc_address_reg[37] , \cmd_pipe_plus.mc_address_reg[36] , \cmd_pipe_plus.mc_address_reg[35] , \cmd_pipe_plus.mc_address_reg[34] , \cmd_pipe_plus.mc_address_reg[33] , \cmd_pipe_plus.mc_address_reg[32] , \cmd_pipe_plus.mc_address_reg[31] , \cmd_pipe_plus.mc_address_reg[30] , \cmd_pipe_plus.mc_we_n_reg[2] , \cmd_pipe_plus.mc_cas_n_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , CLK, p_67_out, p_28_out, maint_srx_r, SR, mc_cke_ns, hi_priority, rstdiv0_sync_r1_reg_rep__0, phy_mc_ctl_full, of_ctl_full_v, pass_open_bank_r_lcl_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , q_has_rd_r_reg_0, q_has_priority_r_reg_1, rnk_config_valid_r_lcl_reg, \periodic_read_request.periodic_rd_r_lcl_reg , idle_r_lcl_reg_1, \q_entry_r_reg[0]_3 , head_r_lcl_reg_3, head_r_lcl_reg_4, auto_pre_r_lcl_reg_1, ordered_r_lcl_reg, ordered_r_lcl_reg_0, ordered_r_lcl_reg_1, idle_r_lcl_reg_2, \q_entry_r_reg[0]_4 , auto_pre_r_lcl_reg_2, ordered_r_lcl_reg_2, \req_bank_r_lcl_reg[0] , rstdiv0_sync_r1_reg_rep__20, \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , read_this_rank_r, rstdiv0_sync_r1_reg_rep__21, \wtr_timer.wtr_cnt_r_reg[1] , \rtw_timer.rtw_cnt_r_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_2_reg[3] , col_rd_wr_r1, maint_req_r, init_calib_complete_reg_rep__6, periodic_rd_r, cmd, \maint_controller.maint_wip_r_lcl_reg , use_addr, req_wr_r_lcl_reg, bm_end_r1_reg_1, bm_end_r1_reg_2, rtp_timer_ns1, pass_open_bank_r_lcl_reg_2, app_hi_pri_r2, maint_zq_r, \grant_r_reg[1] , inhbt_act_faw_r, \ras_timer_r_reg[2] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] , \generate_maint_cmds.insert_maint_r_lcl_reg , \maintenance_request.maint_zq_r_lcl_reg , \generate_maint_cmds.insert_maint_r_lcl_reg_0 , \app_addr_r1_reg[27] , \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , \app_addr_r1_reg[12] , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[9] , pass_open_bank_r_lcl_reg_3); output maint_wip_r; output insert_maint_r1_lcl_reg; output insert_maint_r1; output periodic_rd_ack_r; output accept_ns; output [0:0]q_has_priority_r_reg; output [1:0]idle_r; output idle_r_lcl_reg; output idle_r_lcl_reg_0; output was_wr; output sent_col; output [0:0]DIC; output [1:0]rd_wr_r; output [4:0]col_data_buf_addr; output [0:0]\act_this_rank_r_reg[0] ; output cke_r; output [1:0]req_wr_r; output row_hit_r; output bm_end_r1; output p_52_out; output pre_wait_r; output req_bank_rdy_ns; output override_demand_ns; output [1:0]wr_this_rank_r; output wait_for_maint_r; output bm_end_r1_reg; output pre_bm_end_r; output row_hit_r_0; output bm_end_r1_0; output p_13_out; output req_bank_rdy_ns_1; output wait_for_maint_r_2; output bm_end_r1_reg_0; output [0:0]rb_hit_busies_r; output q_has_rd; output q_has_priority; output \rcd_timer_gt_2.rcd_timer_r_reg[0] ; output rnk_config_valid_r; output periodic_rd_cntr_r; output tail_r; output q_entry_r; output [1:0]head_r; output auto_pre_r; output \order_q_r_reg[0] ; output ordered_r_lcl; output order_q_r; output tail_r_3; output q_entry_r_4; output auto_pre_r_5; output order_q_r_6; output \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; output [1:0]Q; output read_this_rank; output [1:0]D; output \rtw_timer.rtw_cnt_r_reg[1] ; output [0:0]mc_odt_ns; output col_rd_wr; output [0:0]mc_data_offset_2_ns; output wait_for_maint_r_lcl_reg; output clear_req; output head_r_lcl_reg; output q_has_priority_r_reg_0; output \q_entry_r_reg[0] ; output \q_entry_r_reg[0]_0 ; output set_order_q; output wait_for_maint_r_lcl_reg_0; output head_r_lcl_reg_0; output head_r_lcl_reg_1; output set_order_q_7; output [1:0]\cmd_pipe_plus.mc_address_reg[0] ; output pass_open_bank_r_lcl_reg; output \q_entry_r_reg[0]_1 ; output [1:0]rtp_timer_r; output q_has_rd_r_reg; output \q_entry_r_reg[0]_2 ; output [1:0]mc_cas_n_ns; output [0:0]mc_cs_n_ns; output [1:0]mc_ras_n_ns; output [5:0]\cmd_pipe_plus.mc_bank_reg[5] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; output [22:0]\cmd_pipe_plus.mc_address_reg[25] ; output req_bank_rdy_r_reg; output \rnk_config_strobe_r_reg[0] ; output \rnk_config_strobe_r_reg[0]_0 ; output [2:0]ras_timer_zero_r_reg; output head_r_lcl_reg_2; output auto_pre_r_lcl_reg; output auto_pre_r_lcl_reg_0; output [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ; output pass_open_bank_r_lcl_reg_0; output \wtr_timer.wtr_cnt_r_reg[2] ; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output [0:0]E; output \cmd_pipe_plus.mc_address_reg[40] ; output \cmd_pipe_plus.mc_bank_reg[8] ; output \cmd_pipe_plus.mc_bank_reg[7] ; output \cmd_pipe_plus.mc_bank_reg[6] ; output \cmd_pipe_plus.mc_address_reg[44] ; output \cmd_pipe_plus.mc_address_reg[43] ; output \cmd_pipe_plus.mc_address_reg[42] ; output \cmd_pipe_plus.mc_address_reg[41] ; output \cmd_pipe_plus.mc_address_reg[39] ; output \cmd_pipe_plus.mc_address_reg[38] ; output \cmd_pipe_plus.mc_address_reg[37] ; output \cmd_pipe_plus.mc_address_reg[36] ; output \cmd_pipe_plus.mc_address_reg[35] ; output \cmd_pipe_plus.mc_address_reg[34] ; output \cmd_pipe_plus.mc_address_reg[33] ; output \cmd_pipe_plus.mc_address_reg[32] ; output \cmd_pipe_plus.mc_address_reg[31] ; output \cmd_pipe_plus.mc_address_reg[30] ; output \cmd_pipe_plus.mc_we_n_reg[2] ; output \cmd_pipe_plus.mc_cas_n_reg[2] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; input CLK; input p_67_out; input p_28_out; input maint_srx_r; input [0:0]SR; input [0:0]mc_cke_ns; input hi_priority; input rstdiv0_sync_r1_reg_rep__0; input phy_mc_ctl_full; input [0:0]of_ctl_full_v; input pass_open_bank_r_lcl_reg_1; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; input q_has_rd_r_reg_0; input q_has_priority_r_reg_1; input rnk_config_valid_r_lcl_reg; input \periodic_read_request.periodic_rd_r_lcl_reg ; input idle_r_lcl_reg_1; input \q_entry_r_reg[0]_3 ; input head_r_lcl_reg_3; input head_r_lcl_reg_4; input auto_pre_r_lcl_reg_1; input ordered_r_lcl_reg; input ordered_r_lcl_reg_0; input ordered_r_lcl_reg_1; input idle_r_lcl_reg_2; input \q_entry_r_reg[0]_4 ; input auto_pre_r_lcl_reg_2; input ordered_r_lcl_reg_2; input \req_bank_r_lcl_reg[0] ; input rstdiv0_sync_r1_reg_rep__20; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input read_this_rank_r; input rstdiv0_sync_r1_reg_rep__21; input \wtr_timer.wtr_cnt_r_reg[1] ; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_2_reg[3] ; input col_rd_wr_r1; input maint_req_r; input init_calib_complete_reg_rep__6; input periodic_rd_r; input [1:0]cmd; input \maint_controller.maint_wip_r_lcl_reg ; input use_addr; input req_wr_r_lcl_reg; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input rtp_timer_ns1; input pass_open_bank_r_lcl_reg_2; input app_hi_pri_r2; input maint_zq_r; input \grant_r_reg[1] ; input inhbt_act_faw_r; input \ras_timer_r_reg[2] ; input [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input \maintenance_request.maint_zq_r_lcl_reg ; input \generate_maint_cmds.insert_maint_r_lcl_reg_0 ; input [14:0]\app_addr_r1_reg[27] ; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [2:0]\app_addr_r1_reg[12] ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [6:0]\app_addr_r1_reg[9] ; input pass_open_bank_r_lcl_reg_3; wire CLK; wire [1:0]D; wire [0:0]DIC; wire [0:0]E; wire [1:0]Q; wire [0:0]SR; wire accept_internal_r; wire accept_ns; wire act_this_rank; wire [1:0]act_this_rank_r; wire [0:0]\act_this_rank_r_reg[0] ; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire app_hi_pri_r2; wire arb_mux0_n_16; wire arb_mux0_n_58; wire arb_mux0_n_59; wire arb_mux0_n_60; wire arb_mux0_n_62; wire arb_mux0_n_66; wire arb_mux0_n_67; wire arb_mux0_n_68; wire \arb_row_col0/granted_col_ns ; wire \arb_row_col0/rnk_config_strobe_ns ; wire auto_pre_r; wire auto_pre_r_5; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire \bank_cntrl[0].bank0_n_32 ; wire \bank_cntrl[0].bank0_n_38 ; wire \bank_cntrl[0].bank0_n_39 ; wire \bank_cntrl[0].bank0_n_40 ; wire \bank_cntrl[0].bank0_n_44 ; wire \bank_cntrl[0].bank0_n_46 ; wire \bank_cntrl[0].bank0_n_47 ; wire \bank_cntrl[0].bank0_n_51 ; wire \bank_cntrl[1].bank0_n_32 ; wire \bank_cntrl[1].bank0_n_42 ; wire \bank_cntrl[1].bank0_n_43 ; wire \bank_cntrl[1].bank0_n_44 ; wire \bank_cntrl[1].bank0_n_45 ; wire \bank_cntrl[1].bank0_n_62 ; wire \bank_cntrl[1].bank0_n_67 ; wire bank_common0_n_10; wire bank_common0_n_11; wire bank_common0_n_14; wire bank_common0_n_15; wire bank_common0_n_4; wire [1:0]\bank_compare0/req_cmd_r ; wire [1:0]\bank_compare0/req_cmd_r_2 ; wire [9:3]\bank_compare0/req_col_r ; wire [9:3]\bank_compare0/req_col_r_1 ; wire \bank_queue0/pre_passing_open_bank_r ; wire \bank_queue0/pre_passing_open_bank_r_3 ; wire \bank_queue0/rb_hit_busies_ns ; wire \bank_queue0/wait_for_maint_ns ; wire \bank_queue0/wait_for_maint_ns_8 ; wire \bank_state0/demand_priority_r ; wire \bank_state0/demand_priority_r_6 ; wire \bank_state0/demanded_prior_r ; wire \bank_state0/demanded_prior_r_5 ; wire \bank_state0/ofs_rdy_r ; wire \bank_state0/ofs_rdy_r0 ; wire \bank_state0/ofs_rdy_r_4 ; wire \bank_state0/req_bank_rdy_r ; wire \bank_state0/req_bank_rdy_r_7 ; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire cke_r; wire clear_req; wire [1:0]cmd; wire [1:0]\cmd_pipe_plus.mc_address_reg[0] ; wire [22:0]\cmd_pipe_plus.mc_address_reg[25] ; wire \cmd_pipe_plus.mc_address_reg[30] ; wire \cmd_pipe_plus.mc_address_reg[31] ; wire \cmd_pipe_plus.mc_address_reg[32] ; wire \cmd_pipe_plus.mc_address_reg[33] ; wire \cmd_pipe_plus.mc_address_reg[34] ; wire \cmd_pipe_plus.mc_address_reg[35] ; wire \cmd_pipe_plus.mc_address_reg[36] ; wire \cmd_pipe_plus.mc_address_reg[37] ; wire \cmd_pipe_plus.mc_address_reg[38] ; wire \cmd_pipe_plus.mc_address_reg[39] ; wire \cmd_pipe_plus.mc_address_reg[40] ; wire \cmd_pipe_plus.mc_address_reg[41] ; wire \cmd_pipe_plus.mc_address_reg[42] ; wire \cmd_pipe_plus.mc_address_reg[43] ; wire \cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; wire [5:0]\cmd_pipe_plus.mc_bank_reg[5] ; wire \cmd_pipe_plus.mc_bank_reg[6] ; wire \cmd_pipe_plus.mc_bank_reg[7] ; wire \cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_cas_n_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_2_reg[3] ; wire \cmd_pipe_plus.mc_we_n_reg[2] ; wire [4:0]col_data_buf_addr; wire col_rd_wr; wire col_rd_wr_r1; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \generate_maint_cmds.insert_maint_r_lcl_reg_0 ; wire \grant_r_reg[1] ; wire granted_pre_ns; wire granted_row_ns; wire [1:0]head_r; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire head_r_lcl_reg_3; wire head_r_lcl_reg_4; wire hi_priority; wire [1:0]idle_r; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire insert_maint_r1; wire insert_maint_r1_lcl_reg; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire maint_srx_r; wire maint_wip_r; wire maint_zq_r; wire \maintenance_request.maint_zq_r_lcl_reg ; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cke_ns; wire [0:0]mc_cs_n_ns; wire [0:0]mc_data_offset_2_ns; wire [0:0]mc_odt_ns; wire [1:0]mc_ras_n_ns; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [0:0]of_ctl_full_v; wire order_q_r; wire order_q_r_6; wire \order_q_r_reg[0] ; wire ordered_r_lcl; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire ordered_r_lcl_reg_2; wire override_demand_ns; wire p_13_out; wire p_28_out; wire p_52_out; wire p_67_out; wire p_9_in; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire pass_open_bank_r_lcl_reg_1; wire pass_open_bank_r_lcl_reg_2; wire pass_open_bank_r_lcl_reg_3; wire periodic_rd_ack_r; wire periodic_rd_cntr_r; wire \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; wire periodic_rd_insert; wire periodic_rd_r; wire \periodic_read_request.periodic_rd_r_lcl_reg ; wire phy_mc_ctl_full; wire pre_bm_end_r; wire pre_wait_r; wire q_entry_r; wire q_entry_r_4; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire \q_entry_r_reg[0]_2 ; wire \q_entry_r_reg[0]_3 ; wire \q_entry_r_reg[0]_4 ; wire q_has_priority; wire [0:0]q_has_priority_r_reg; wire q_has_priority_r_reg_0; wire q_has_priority_r_reg_1; wire q_has_rd; wire q_has_rd_r_reg; wire q_has_rd_r_reg_0; wire \ras_timer_r_reg[2] ; wire [2:0]ras_timer_zero_r_reg; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire [0:0]rb_hit_busies_r; wire [1:1]rb_hit_busies_r_0; wire [0:0]rb_hit_busy_r; wire \rcd_timer_gt_2.rcd_timer_r_reg[0] ; wire [1:0]rd_this_rank_r; wire [1:0]rd_wr_r; wire read_this_rank; wire read_this_rank_r; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_ns; wire req_bank_rdy_ns_1; wire req_bank_rdy_r_reg; wire [9:0]req_data_buf_addr_r; wire [1:0]req_periodic_rd_r; wire [29:0]req_row_r; wire [1:0]req_wr_r; wire req_wr_r_lcl_reg; wire [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; wire [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ; wire \rnk_config_strobe_r_reg[0] ; wire \rnk_config_strobe_r_reg[0]_0 ; wire rnk_config_valid_r; wire rnk_config_valid_r_lcl_reg; wire [1:1]row_cmd_wr; wire row_hit_r; wire row_hit_r_0; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rtp_timer_ns1; wire [1:0]rtp_timer_r; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [1:0]sending_pre; wire sent_col; wire set_order_q; wire set_order_q_7; wire tail_r; wire tail_r_3; wire use_addr; wire wait_for_maint_r; wire wait_for_maint_r_2; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire was_wr; wire [1:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire \wtr_timer.wtr_cnt_r_reg[2] ; ddr3_ifmig_7series_v4_0_arb_mux arb_mux0 (.CLK(CLK), .D(D), .DIC(DIC), .Q(Q), .SR(SR), .act_this_rank(act_this_rank), .act_this_rank_r(act_this_rank_r), .act_wait_r_lcl_reg(\act_this_rank_r_reg[0] ), .auto_pre_r_lcl_reg(\bank_cntrl[1].bank0_n_67 ), .auto_pre_r_lcl_reg_0(\bank_cntrl[0].bank0_n_46 ), .auto_pre_r_lcl_reg_1(auto_pre_r), .auto_pre_r_lcl_reg_2(auto_pre_r_5), .cke_r(cke_r), .\cmd_pipe_plus.mc_address_reg[0] (insert_maint_r1), .\cmd_pipe_plus.mc_address_reg[0]_0 (\cmd_pipe_plus.mc_address_reg[0] ), .\cmd_pipe_plus.mc_address_reg[10] (arb_mux0_n_68), .\cmd_pipe_plus.mc_address_reg[25] ({\cmd_pipe_plus.mc_address_reg[25] [22:11],\cmd_pipe_plus.mc_address_reg[25] [9:0]}), .\cmd_pipe_plus.mc_address_reg[30] (\cmd_pipe_plus.mc_address_reg[30] ), .\cmd_pipe_plus.mc_address_reg[31] (\cmd_pipe_plus.mc_address_reg[31] ), .\cmd_pipe_plus.mc_address_reg[32] (\cmd_pipe_plus.mc_address_reg[32] ), .\cmd_pipe_plus.mc_address_reg[33] (\cmd_pipe_plus.mc_address_reg[33] ), .\cmd_pipe_plus.mc_address_reg[34] (\cmd_pipe_plus.mc_address_reg[34] ), .\cmd_pipe_plus.mc_address_reg[35] (\cmd_pipe_plus.mc_address_reg[35] ), .\cmd_pipe_plus.mc_address_reg[36] (\cmd_pipe_plus.mc_address_reg[36] ), .\cmd_pipe_plus.mc_address_reg[37] (\cmd_pipe_plus.mc_address_reg[37] ), .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ), .\cmd_pipe_plus.mc_address_reg[39] (\cmd_pipe_plus.mc_address_reg[39] ), .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ), .\cmd_pipe_plus.mc_address_reg[42] (\cmd_pipe_plus.mc_address_reg[42] ), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] ), .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[5] ), .\cmd_pipe_plus.mc_bank_reg[6] (\cmd_pipe_plus.mc_bank_reg[6] ), .\cmd_pipe_plus.mc_bank_reg[7] (\cmd_pipe_plus.mc_bank_reg[7] ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_cas_n_reg[2] (sending_pre), .\cmd_pipe_plus.mc_cas_n_reg[2]_0 (\cmd_pipe_plus.mc_cas_n_reg[2] ), .\cmd_pipe_plus.mc_cmd_reg[0] (sent_col), .\cmd_pipe_plus.mc_cs_n_reg[0] (mc_cs_n_ns), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg[3] ), .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ), .col_data_buf_addr(col_data_buf_addr), .col_rd_wr(col_rd_wr), .col_rd_wr_r1(col_rd_wr_r1), .col_wait_r_reg(\bank_cntrl[0].bank0_n_32 ), .col_wait_r_reg_0(\bank_cntrl[1].bank0_n_32 ), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ), .demand_priority_r_reg(arb_mux0_n_66), .demand_priority_r_reg_0(arb_mux0_n_67), .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r1_lcl_reg), .\grant_r_reg[1] (\grant_r_reg[1] ), .granted_col_ns(\arb_row_col0/granted_col_ns ), .granted_col_r_reg(arb_mux0_n_16), .granted_col_r_reg_0(arb_mux0_n_59), .granted_col_r_reg_1(arb_mux0_n_60), .granted_pre_ns(granted_pre_ns), .granted_row_ns(granted_row_ns), .granted_row_r_reg(arb_mux0_n_58), .granted_row_r_reg_0(arb_mux0_n_62), .head_r_lcl_reg(\bank_cntrl[1].bank0_n_62 ), .head_r_lcl_reg_0(\bank_cntrl[0].bank0_n_47 ), .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .mc_cas_n_ns(mc_cas_n_ns), .mc_cke_ns(mc_cke_ns), .mc_data_offset_2_ns(mc_data_offset_2_ns), .mc_odt_ns(mc_odt_ns), .mc_ras_n_ns(mc_ras_n_ns), .ofs_rdy_r(\bank_state0/ofs_rdy_r_4 ), .ofs_rdy_r_0(\bank_state0/ofs_rdy_r ), .override_demand_ns(override_demand_ns), .\periodic_rd_generation.periodic_rd_timer_r_reg[0] (\periodic_rd_generation.periodic_rd_timer_r_reg[0] ), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(rd_wr_r[1]), .rd_wr_r_lcl_reg_0(rd_wr_r[0]), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .\req_bank_r_lcl_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .req_bank_rdy_r(\bank_state0/req_bank_rdy_r ), .req_bank_rdy_r_1(\bank_state0/req_bank_rdy_r_7 ), .\req_col_r_reg[9] (\bank_compare0/req_col_r ), .\req_col_r_reg[9]_0 (\bank_compare0/req_col_r_1 ), .req_data_buf_addr_r(req_data_buf_addr_r), .req_periodic_rd_r(req_periodic_rd_r), .req_row_r({req_row_r[29:26],req_row_r[24:11],req_row_r[9:0]}), .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ), .\rnk_config_strobe_r_reg[0] (rnk_config_valid_r), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[2] (\wtr_timer.wtr_cnt_r_reg[2] )); ddr3_ifmig_7series_v4_0_bank_cntrl \bank_cntrl[0].bank0 (.CLK(CLK), .D({bank_common0_n_14,bank_common0_n_15}), .E(idle_r[0]), .Q(\bank_compare0/req_cmd_r ), .SR(SR), .accept_internal_r(accept_internal_r), .accept_r_reg(q_has_rd_r_reg), .accept_r_reg_0(bank_common0_n_4), .act_this_rank_r(act_this_rank_r[0]), .\act_this_rank_r_reg[0] (\act_this_rank_r_reg[0] ), .act_wait_r_lcl_reg(\bank_cntrl[0].bank0_n_44 ), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .app_hi_pri_r2(app_hi_pri_r2), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_1(\bank_cntrl[1].bank0_n_67 ), .bm_end_r1(bm_end_r1), .bm_end_r1_reg(req_wr_r[0]), .bm_end_r1_reg_0(p_52_out), .bm_end_r1_reg_1(bm_end_r1_reg), .bm_end_r1_reg_2(\bank_cntrl[1].bank0_n_44 ), .bm_end_r1_reg_3(bm_end_r1_reg_1), .cmd(cmd), .\cmd_pipe_plus.mc_address_reg[14] (req_row_r[14:0]), .\cmd_pipe_plus.mc_address_reg[24] (\bank_compare0/req_col_r ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[4:0]), .col_wait_r_reg(\bank_cntrl[1].bank0_n_32 ), .demand_priority_r(\bank_state0/demand_priority_r ), .demand_priority_r_2(\bank_state0/demand_priority_r_6 ), .demand_priority_r_reg(\rnk_config_strobe_r_reg[0]_0 ), .demanded_prior_r(\bank_state0/demanded_prior_r ), .demanded_prior_r_1(\bank_state0/demanded_prior_r_5 ), .\entry_cnt_reg[2] (\entry_cnt_reg[2] ), .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2]_0 ), .\grant_r_reg[0] (arb_mux0_n_16), .\grant_r_reg[0]_0 (\cmd_pipe_plus.mc_address_reg[0] [0]), .\grant_r_reg[0]_1 (sending_pre[0]), .\grant_r_reg[1] (\bank_cntrl[0].bank0_n_46 ), .\grant_r_reg[1]_0 (Q), .\grant_r_reg[1]_1 (arb_mux0_n_62), .granted_col_ns(\arb_row_col0/granted_col_ns ), .granted_col_r_reg(\bank_cntrl[0].bank0_n_32 ), .granted_col_r_reg_0(\bank_cntrl[0].bank0_n_51 ), .granted_col_r_reg_1(sent_col), .granted_pre_ns(granted_pre_ns), .granted_row_r_reg(\bank_cntrl[0].bank0_n_47 ), .head_r_lcl_reg(head_r_lcl_reg_0), .head_r_lcl_reg_0(head_r_lcl_reg_1), .head_r_lcl_reg_1(head_r_lcl_reg_3), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg), .idle_r_lcl_reg_0(head_r[0]), .idle_r_lcl_reg_1(idle_r_lcl_reg_1), .idle_r_lcl_reg_2(idle_r[1]), .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r(\bank_state0/ofs_rdy_r ), .ofs_rdy_r0(\bank_state0/ofs_rdy_r0 ), .\order_q_r_reg[0] (order_q_r_6), .ordered_r_lcl(ordered_r_lcl), .ordered_r_lcl_reg(ordered_r_lcl_reg_0), .ordered_r_lcl_reg_0(ordered_r_lcl_reg_1), .override_demand_ns(override_demand_ns), .p_67_out(p_67_out), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_0), .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_1), .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_2), .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg_3), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg_0(q_has_priority_r_reg_0), .periodic_rd_ack_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r), .periodic_rd_insert(periodic_rd_insert), .phy_mc_ctl_full(phy_mc_ctl_full), .pre_bm_end_r(pre_bm_end_r), .pre_bm_end_r_reg(p_13_out), .pre_passing_open_bank_r(\bank_queue0/pre_passing_open_bank_r ), .pre_passing_open_bank_r_0(\bank_queue0/pre_passing_open_bank_r_3 ), .pre_wait_r_reg(rtp_timer_r[0]), .pre_wait_r_reg_0(rtp_timer_r[1]), .q_entry_r(q_entry_r), .\q_entry_r_reg[0] (\q_entry_r_reg[0]_2 ), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_3 ), .\ras_timer_r_reg[0] (\bank_cntrl[0].bank0_n_40 ), .\ras_timer_r_reg[1] (\bank_cntrl[0].bank0_n_39 ), .\ras_timer_r_reg[2] (\bank_cntrl[0].bank0_n_38 ), .\ras_timer_r_reg[2]_0 (\bank_cntrl[1].bank0_n_45 ), .rb_hit_busies_ns(\bank_queue0/rb_hit_busies_ns ), .rb_hit_busies_r(rb_hit_busies_r_0), .rb_hit_busy_r(rb_hit_busy_r), .rb_hit_busy_r_reg(q_has_priority_r_reg), .rd_this_rank_r(rd_this_rank_r[0]), .\rd_this_rank_r_reg[0] (rd_wr_r[0]), .rd_wr_r_lcl_reg(rd_wr_r[1]), .rd_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_43 ), .req_bank_rdy_ns(req_bank_rdy_ns), .req_bank_rdy_ns_1(req_bank_rdy_ns_1), .req_bank_rdy_r(\bank_state0/req_bank_rdy_r ), .req_bank_rdy_r_reg(order_q_r), .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg), .req_bank_rdy_r_reg_1(arb_mux0_n_66), .req_periodic_rd_r(req_periodic_rd_r[0]), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .req_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_42 ), .req_wr_r_lcl_reg_1(req_wr_r[1]), .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_60), .\rnk_config_strobe_r_reg[0]_1 (arb_mux0_n_59), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r), .row_hit_r(row_hit_r), .\rp_timer.rp_timer_r_reg[1] (pre_wait_r), .\rp_timer.rp_timer_r_reg[1]_0 (auto_pre_r), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .set_order_q_7(set_order_q_7), .tail_r(tail_r), .use_addr(use_addr), .wait_for_maint_ns(\bank_queue0/wait_for_maint_ns ), .wait_for_maint_r_lcl_reg(wait_for_maint_r), .was_wr(was_wr), .wr_this_rank_r(wr_this_rank_r[0]), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_ifmig_7series_v4_0_bank_cntrl__parameterized0 \bank_cntrl[1].bank0 (.CLK(CLK), .D({bank_common0_n_10,bank_common0_n_11}), .E(idle_r[1]), .Q(\bank_compare0/req_cmd_r_2 ), .SR(SR), .accept_internal_r(accept_internal_r), .accept_r_reg(pass_open_bank_r_lcl_reg), .act_this_rank_r(act_this_rank_r[1]), .act_wait_r_lcl_reg(\act_this_rank_r_reg[0] ), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_2), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg(req_wr_r[1]), .bm_end_r1_reg_0(p_13_out), .bm_end_r1_reg_1(bm_end_r1_reg_0), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bm_end_r1_reg_3(\bank_cntrl[0].bank0_n_39 ), .bm_end_r1_reg_4(\bank_cntrl[0].bank0_n_38 ), .cmd(cmd), .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[25] [10]), .\cmd_pipe_plus.mc_address_reg[14] ({req_row_r[29:26],req_row_r[24:15]}), .\cmd_pipe_plus.mc_address_reg[24] (\bank_compare0/req_col_r_1 ), .\cmd_pipe_plus.mc_address_reg[40] (\cmd_pipe_plus.mc_address_reg[40] ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[9:5]), .demand_priority_r(\bank_state0/demand_priority_r_6 ), .demand_priority_r_2(\bank_state0/demand_priority_r ), .demanded_prior_r(\bank_state0/demanded_prior_r_5 ), .demanded_prior_r_1(\bank_state0/demanded_prior_r ), .\grant_r_reg[0] (arb_mux0_n_16), .\grant_r_reg[0]_0 (arb_mux0_n_68), .\grant_r_reg[0]_1 (arb_mux0_n_58), .\grant_r_reg[1] (Q), .\grant_r_reg[1]_0 (\cmd_pipe_plus.mc_address_reg[0] [1]), .\grant_r_reg[1]_1 (sending_pre), .granted_col_r_reg(\bank_cntrl[1].bank0_n_32 ), .granted_col_r_reg_0(sent_col), .granted_row_ns(granted_row_ns), .granted_row_r_reg(\bank_cntrl[1].bank0_n_62 ), .head_r_lcl_reg(head_r_lcl_reg), .head_r_lcl_reg_0(head_r_lcl_reg_4), .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_47 ), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg_0), .idle_r_lcl_reg_0(head_r[1]), .idle_r_lcl_reg_1(idle_r_lcl_reg_2), .idle_r_lcl_reg_2(idle_r_lcl_reg), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r), .maint_req_r(maint_req_r), .mc_cs_n_ns(mc_cs_n_ns), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .ofs_rdy_r(\bank_state0/ofs_rdy_r_4 ), .ofs_rdy_r0(\bank_state0/ofs_rdy_r0 ), .\order_q_r_reg[0] (\order_q_r_reg[0] ), .\order_q_r_reg[0]_0 (\bank_cntrl[0].bank0_n_51 ), .ordered_r_lcl_reg(ordered_r_lcl_reg), .ordered_r_lcl_reg_0(ordered_r_lcl_reg_2), .p_28_out(p_28_out), .p_9_in(p_9_in), .pass_open_bank_r_lcl_reg(clear_req), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg_0(q_has_priority_r_reg_0), .periodic_rd_ack_r_lcl_reg_1(wait_for_maint_r_lcl_reg), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r), .periodic_rd_insert(periodic_rd_insert), .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[1].bank0_n_67 ), .pre_bm_end_r_reg(p_52_out), .pre_passing_open_bank_r(\bank_queue0/pre_passing_open_bank_r_3 ), .pre_passing_open_bank_r_0(\bank_queue0/pre_passing_open_bank_r ), .q_entry_r_4(q_entry_r_4), .\q_entry_r_reg[0] (\q_entry_r_reg[0] ), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_0 ), .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_1 ), .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_4 ), .q_has_priority(q_has_priority), .q_has_priority_r_reg(q_has_priority_r_reg), .q_has_priority_r_reg_0(q_has_priority_r_reg_1), .q_has_rd(q_has_rd), .q_has_rd_r_reg(q_has_rd_r_reg_0), .\ras_timer_r_reg[0] (\bank_cntrl[1].bank0_n_43 ), .\ras_timer_r_reg[1] (\bank_cntrl[1].bank0_n_44 ), .\ras_timer_r_reg[1]_0 (\bank_cntrl[0].bank0_n_40 ), .\ras_timer_r_reg[2] (\bank_cntrl[1].bank0_n_42 ), .\ras_timer_r_reg[2]_0 (\bank_cntrl[1].bank0_n_45 ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2] ), .ras_timer_zero_r_reg(ras_timer_zero_r_reg), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (rb_hit_busies_r), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .rb_hit_busies_ns(\bank_queue0/rb_hit_busies_ns ), .rb_hit_busies_r(rb_hit_busies_r_0), .rb_hit_busy_r(rb_hit_busy_r), .\rcd_timer_gt_2.rcd_timer_r_reg[0] (\rcd_timer_gt_2.rcd_timer_r_reg[0] ), .rd_this_rank_r(rd_this_rank_r[1]), .\rd_this_rank_r_reg[0] (rd_wr_r[1]), .rd_wr_r_lcl_reg(req_bank_rdy_r_reg), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .req_bank_rdy_ns_1(req_bank_rdy_ns_1), .req_bank_rdy_r(\bank_state0/req_bank_rdy_r_7 ), .req_bank_rdy_r_reg(order_q_r_6), .req_bank_rdy_r_reg_0(arb_mux0_n_67), .req_periodic_rd_r(req_periodic_rd_r[1]), .\req_row_r_lcl_reg[10] (req_row_r[10]), .req_wr_r_lcl_reg(\bank_cntrl[0].bank0_n_44 ), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0]_0 ), .row_cmd_wr(row_cmd_wr), .row_hit_r_0(row_hit_r_0), .\rp_timer.rp_timer_r_reg[1] (auto_pre_r_5), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rtp_timer_ns1(rtp_timer_ns1), .set_order_q(set_order_q), .tail_r_3(tail_r_3), .use_addr(use_addr), .wait_for_maint_ns(\bank_queue0/wait_for_maint_ns_8 ), .wait_for_maint_r_lcl_reg(wait_for_maint_r_2), .wr_this_rank_r(wr_this_rank_r[1]), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_ifmig_7series_v4_0_bank_common bank_common0 (.CLK(CLK), .D({bank_common0_n_10,bank_common0_n_11}), .E(idle_r[1]), .Q(\bank_compare0/req_cmd_r_2 ), .SR(SR), .accept_internal_r(accept_internal_r), .accept_ns(accept_ns), .clear_req(clear_req), .cmd(cmd), .\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\generate_maint_cmds.insert_maint_r_lcl_reg_1 (\generate_maint_cmds.insert_maint_r_lcl_reg_0 ), .head_r(head_r), .head_r_lcl_reg(bank_common0_n_4), .head_r_lcl_reg_0(head_r_lcl_reg_2), .idle_r(idle_r[0]), .idle_r_lcl_reg(idle_r_lcl_reg), .idle_r_lcl_reg_0(idle_r_lcl_reg_0), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .insert_maint_r1_lcl_reg(insert_maint_r1_lcl_reg), .\maint_controller.maint_hit_busies_r_reg[0]_0 (maint_wip_r), .\maint_controller.maint_wip_r_lcl_reg_0 (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .maint_srx_r(maint_srx_r), .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ), .p_52_out(p_52_out), .p_9_in(p_9_in), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ), .q_has_priority_r_reg(q_has_priority_r_reg_0), .q_has_rd_r_reg(q_has_rd_r_reg), .rb_hit_busy_r(rb_hit_busy_r), .rb_hit_busy_r_reg(q_has_priority_r_reg), .\req_cmd_r_reg[1] ({bank_common0_n_14,bank_common0_n_15}), .\req_cmd_r_reg[1]_0 (\bank_compare0/req_cmd_r ), .req_periodic_rd_r_lcl_reg(periodic_rd_cntr_r), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (E), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .use_addr(use_addr), .wait_for_maint_ns(\bank_queue0/wait_for_maint_ns_8 ), .wait_for_maint_ns_0(\bank_queue0/wait_for_maint_ns ), .wait_for_maint_r(wait_for_maint_r), .wait_for_maint_r_2(wait_for_maint_r_2), .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0), .was_wr(was_wr), .was_wr_reg_0(periodic_rd_ack_r)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_queue" *) module ddr3_ifmig_7series_v4_0_bank_queue (\req_data_buf_addr_r_reg[4] , idle_r_lcl_reg_0, wait_for_maint_r_lcl_reg_0, bm_end_r1_reg, pre_bm_end_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 , pre_passing_open_bank_r, q_has_rd, q_has_priority, tail_r, q_entry_r, idle_r_lcl_reg_1, \rp_timer.rp_timer_r_reg[1] , ordered_r_lcl, req_bank_rdy_r_reg, rd_wr_ns, head_r_lcl_reg_0, head_r_lcl_reg_1, bm_end_r1_reg_0, set_order_q_7, D, \ras_timer_r_reg[2] , act_wait_ns, \q_entry_r_reg[0]_0 , granted_row_r_reg, CLK, wait_for_maint_ns, pass_open_bank_r_lcl_reg_0, pre_bm_end_ns, rb_hit_busies_ns, pre_passing_open_bank_ns, rstdiv0_sync_r1_reg_rep__0, idle_r_lcl_reg_2, \q_entry_r_reg[0]_1 , SR, head_r_lcl_reg_2, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_0, ordered_r_lcl_reg_1, cmd, periodic_rd_insert, rd_wr_r_lcl_reg, \grant_r_reg[0] , periodic_rd_ack_r_lcl_reg, use_addr, accept_internal_r, req_wr_r_lcl_reg, pre_bm_end_r_reg_0, rb_hit_busy_r_reg, rb_hit_busy_r, periodic_rd_ack_r_lcl_reg_0, periodic_rd_ack_r_lcl_reg_1, req_wr_r_lcl_reg_0, \ras_timer_r_reg[2]_0 , bm_end_r1_reg_1, bm_end_r1_reg_2, bm_end_r1_reg_3, rd_wr_r_lcl_reg_0, \ras_timer_r_reg[1] , \grant_r_reg[0]_0 , act_wait_r_lcl_reg, bm_end_r1_reg_4, req_wr_r_lcl_reg_1, pre_passing_open_bank_r_0, maint_req_r, was_wr, accept_r_reg, rstdiv0_sync_r1_reg_rep__21, app_hi_pri_r2, idle_r_lcl_reg_3, accept_r_reg_0, ras_timer_zero_r, \grant_r_reg[1] ); output \req_data_buf_addr_r_reg[4] ; output idle_r_lcl_reg_0; output wait_for_maint_r_lcl_reg_0; output bm_end_r1_reg; output pre_bm_end_r; output \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ; output pre_passing_open_bank_r; output q_has_rd; output q_has_priority; output tail_r; output q_entry_r; output idle_r_lcl_reg_1; output \rp_timer.rp_timer_r_reg[1] ; output ordered_r_lcl; output req_bank_rdy_r_reg; output rd_wr_ns; output head_r_lcl_reg_0; output head_r_lcl_reg_1; output bm_end_r1_reg_0; output set_order_q_7; output [2:0]D; output \ras_timer_r_reg[2] ; output act_wait_ns; output \q_entry_r_reg[0]_0 ; output granted_row_r_reg; input CLK; input wait_for_maint_ns; input pass_open_bank_r_lcl_reg_0; input pre_bm_end_ns; input rb_hit_busies_ns; input pre_passing_open_bank_ns; input rstdiv0_sync_r1_reg_rep__0; input idle_r_lcl_reg_2; input \q_entry_r_reg[0]_1 ; input [0:0]SR; input head_r_lcl_reg_2; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_0; input ordered_r_lcl_reg_1; input [0:0]cmd; input periodic_rd_insert; input rd_wr_r_lcl_reg; input [0:0]\grant_r_reg[0] ; input periodic_rd_ack_r_lcl_reg; input use_addr; input accept_internal_r; input req_wr_r_lcl_reg; input pre_bm_end_r_reg_0; input rb_hit_busy_r_reg; input [0:0]rb_hit_busy_r; input periodic_rd_ack_r_lcl_reg_0; input periodic_rd_ack_r_lcl_reg_1; input req_wr_r_lcl_reg_0; input \ras_timer_r_reg[2]_0 ; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input bm_end_r1_reg_3; input rd_wr_r_lcl_reg_0; input \ras_timer_r_reg[1] ; input [0:0]\grant_r_reg[0]_0 ; input act_wait_r_lcl_reg; input bm_end_r1_reg_4; input req_wr_r_lcl_reg_1; input pre_passing_open_bank_r_0; input maint_req_r; input was_wr; input accept_r_reg; input rstdiv0_sync_r1_reg_rep__21; input app_hi_pri_r2; input [0:0]idle_r_lcl_reg_3; input accept_r_reg_0; input ras_timer_zero_r; input \grant_r_reg[1] ; wire CLK; wire [2:0]D; wire [0:0]SR; wire accept_internal_r; wire accept_r_reg; wire accept_r_reg_0; wire act_wait_ns; wire act_wait_r_lcl_reg; wire app_hi_pri_r2; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire [0:0]cmd; wire [0:0]\grant_r_reg[0] ; wire [0:0]\grant_r_reg[0]_0 ; wire \grant_r_reg[1] ; wire granted_row_r_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire i___6_i_2_n_0; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire [0:0]idle_r_lcl_reg_3; wire maint_req_r; wire ordered_r_lcl; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire pass_open_bank_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_insert; wire pre_bm_end_ns; wire pre_bm_end_r; wire pre_bm_end_r_reg_0; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_0; wire q_entry_r; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire q_has_priority; wire q_has_priority_ns; wire q_has_rd; wire q_has_rd_ns; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire ras_timer_zero_r; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ; wire rb_hit_busies_ns; wire [0:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire rd_wr_ns; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_r_reg; wire \req_data_buf_addr_r_reg[4] ; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__21; wire set_order_q_7; wire tail_r; wire use_addr; wire wait_for_maint_ns; wire wait_for_maint_r_lcl_reg_0; wire was_wr; LUT6 #( .INIT(64'hFFFFFFFF88888F88)) act_wait_r_lcl_i_1 (.I0(bm_end_r1_reg), .I1(bm_end_r1_reg_0), .I2(\grant_r_reg[0]_0 ), .I3(act_wait_r_lcl_reg), .I4(\ras_timer_r_reg[2] ), .I5(bm_end_r1_reg_4), .O(act_wait_ns)); LUT5 #( .INIT(32'h00E00000)) act_wait_r_lcl_i_2 (.I0(req_wr_r_lcl_reg_1), .I1(pre_passing_open_bank_r_0), .I2(q_entry_r), .I3(\req_data_buf_addr_r_reg[4] ), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .O(\ras_timer_r_reg[2] )); FDRE #( .INIT(1'b0)) auto_pre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(auto_pre_r_lcl_reg_0), .Q(\rp_timer.rp_timer_r_reg[1] ), .R(1'b0)); LUT5 #( .INIT(32'hAAEAEAEA)) bm_end_r1_i_1__0 (.I0(pre_bm_end_r), .I1(\grant_r_reg[0] ), .I2(bm_end_r1_reg), .I3(rd_wr_r_lcl_reg), .I4(req_wr_r_lcl_reg_0), .O(bm_end_r1_reg_0)); FDRE #( .INIT(1'b1)) \compute_tail.tail_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_2), .Q(tail_r), .R(rstdiv0_sync_r1_reg_rep__0)); LUT6 #( .INIT(64'h0000000000200000)) \grant_r[1]_i_3__1 (.I0(idle_r_lcl_reg_1), .I1(wait_for_maint_r_lcl_reg_0), .I2(act_wait_r_lcl_reg), .I3(\req_data_buf_addr_r_reg[4] ), .I4(ras_timer_zero_r), .I5(\grant_r_reg[1] ), .O(granted_row_r_reg)); FDSE #( .INIT(1'b1)) head_r_lcl_reg (.C(CLK), .CE(1'b1), .D(head_r_lcl_reg_2), .Q(idle_r_lcl_reg_1), .S(SR)); LUT6 #( .INIT(64'h8000800080000000)) i___10_i_1 (.I0(req_wr_r_lcl_reg_0), .I1(\req_data_buf_addr_r_reg[4] ), .I2(idle_r_lcl_reg_1), .I3(accept_internal_r), .I4(use_addr), .I5(periodic_rd_ack_r_lcl_reg), .O(set_order_q_7)); LUT6 #( .INIT(64'h6969699669966996)) i___12_i_2 (.I0(bm_end_r1_reg_0), .I1(\req_data_buf_addr_r_reg[4] ), .I2(idle_r_lcl_reg_3), .I3(periodic_rd_ack_r_lcl_reg), .I4(accept_r_reg_0), .I5(use_addr), .O(\q_entry_r_reg[0]_0 )); LUT6 #( .INIT(64'hFFFFFFFFF0F8FFF8)) i___5_i_3 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .I1(pre_bm_end_r_reg_0), .I2(periodic_rd_ack_r_lcl_reg_1), .I3(\req_data_buf_addr_r_reg[4] ), .I4(periodic_rd_ack_r_lcl_reg_0), .I5(bm_end_r1_reg_0), .O(head_r_lcl_reg_1)); LUT6 #( .INIT(64'h8BBBB888B8888BBB)) i___6_i_1 (.I0(q_entry_r), .I1(i___6_i_2_n_0), .I2(pre_bm_end_r_reg_0), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .I4(rb_hit_busy_r_reg), .I5(rb_hit_busy_r), .O(head_r_lcl_reg_0)); LUT5 #( .INIT(32'h00880F88)) i___6_i_2 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .I1(pre_bm_end_r_reg_0), .I2(periodic_rd_ack_r_lcl_reg_0), .I3(\req_data_buf_addr_r_reg[4] ), .I4(periodic_rd_ack_r_lcl_reg_1), .O(i___6_i_2_n_0)); LUT6 #( .INIT(64'h02AAAAAAFFFFFFFF)) idle_r_lcl_i_1__0 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(periodic_rd_ack_r_lcl_reg), .I2(use_addr), .I3(accept_internal_r), .I4(idle_r_lcl_reg_1), .I5(req_wr_r_lcl_reg), .O(idle_r_lcl_reg_0)); FDRE #( .INIT(1'b0)) idle_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_0), .Q(\req_data_buf_addr_r_reg[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \order_q_r_reg[0] (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_1), .Q(req_bank_rdy_r_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) ordered_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_0), .Q(ordered_r_lcl), .R(1'b0)); FDRE #( .INIT(1'b0)) pass_open_bank_r_lcl_reg (.C(CLK), .CE(1'b1), .D(pass_open_bank_r_lcl_reg_0), .Q(bm_end_r1_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) pre_bm_end_r_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_ns), .Q(pre_bm_end_r), .R(1'b0)); FDRE #( .INIT(1'b0)) pre_passing_open_bank_r_reg (.C(CLK), .CE(1'b1), .D(pre_passing_open_bank_ns), .Q(pre_passing_open_bank_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \q_entry_r_reg[0] (.C(CLK), .CE(1'b1), .D(\q_entry_r_reg[0]_1 ), .Q(q_entry_r), .R(rstdiv0_sync_r1_reg_rep__0)); LUT6 #( .INIT(64'h1010111010101010)) q_has_priority_r_i_1 (.I0(bm_end_r1_reg_0), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(q_has_priority), .I3(rb_hit_busy_r), .I4(periodic_rd_ack_r_lcl_reg_0), .I5(app_hi_pri_r2), .O(q_has_priority_ns)); FDRE #( .INIT(1'b0)) q_has_priority_r_reg (.C(CLK), .CE(1'b1), .D(q_has_priority_ns), .Q(q_has_priority), .R(1'b0)); LUT6 #( .INIT(64'h88A888A888A8AAAA)) q_has_rd_r_i_1 (.I0(req_wr_r_lcl_reg), .I1(q_has_rd), .I2(maint_req_r), .I3(\req_data_buf_addr_r_reg[4] ), .I4(was_wr), .I5(accept_r_reg), .O(q_has_rd_ns)); FDRE #( .INIT(1'b0)) q_has_rd_r_reg (.C(CLK), .CE(1'b1), .D(q_has_rd_ns), .Q(q_has_rd), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1052" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[0]_i_1 (.I0(rd_wr_r_lcl_reg_0), .I1(\ras_timer_r_reg[2] ), .I2(\ras_timer_r_reg[1] ), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair1052" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[1]_i_1 (.I0(bm_end_r1_reg_2), .I1(\ras_timer_r_reg[2] ), .I2(bm_end_r1_reg_3), .O(D[1])); LUT3 #( .INIT(8'hB8)) \ras_timer_r[2]_i_1 (.I0(\ras_timer_r_reg[2]_0 ), .I1(\ras_timer_r_reg[2] ), .I2(bm_end_r1_reg_1), .O(D[2])); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (.C(CLK), .CE(1'b1), .D(rb_hit_busies_ns), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .R(1'b0)); LUT5 #( .INIT(32'hE0E0EFE0)) rd_wr_r_lcl_i_1__0 (.I0(cmd), .I1(periodic_rd_insert), .I2(idle_r_lcl_reg_0), .I3(rd_wr_r_lcl_reg), .I4(\grant_r_reg[0] ), .O(rd_wr_ns)); FDRE #( .INIT(1'b0)) wait_for_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(wait_for_maint_ns), .Q(wait_for_maint_r_lcl_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_queue" *) module ddr3_ifmig_7series_v4_0_bank_queue__parameterized0 (\req_data_buf_addr_r_reg[4] , idle_r_lcl_reg_0, wait_for_maint_r_lcl_reg_0, bm_end_r1_reg, pre_bm_end_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 , pre_passing_open_bank_r, q_has_rd, q_has_priority, idle_r_lcl_reg_1, \order_q_r_reg[0]_0 , tail_r_3, q_entry_r_4, \rp_timer.rp_timer_r_reg[1] , req_bank_rdy_r_reg, rb_hit_busies_ns, bm_end_r1_reg_0, granted_col_r_reg, act_wait_r_lcl_reg, p_9_in, rd_wr_ns, demand_priority_ns, head_r_lcl_reg_0, \q_entry_r_reg[0]_0 , set_order_q, act_wait_ns, \q_entry_r_reg[0]_1 , D, granted_row_ns, granted_row_r_reg, CLK, wait_for_maint_ns, pass_open_bank_ns, pre_bm_end_ns, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 , pre_passing_open_bank_ns, q_has_rd_r_reg_0, q_has_priority_r_reg_0, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_1, ordered_r_lcl_reg_0, idle_r_lcl_reg_2, SR, \q_entry_r_reg[0]_2 , auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_1, \req_bank_r_lcl_reg[0] , rb_hit_busies_r, idle_r_lcl_reg_3, rstdiv0_sync_r1_reg_rep__20, \wtr_timer.wtr_cnt_r_reg[1] , col_wait_r, \order_q_r_reg[0]_1 , rd_wr_r_lcl_reg, \grant_r_reg[0] , init_calib_complete_reg_rep__6, cmd, periodic_rd_insert, \grant_r_reg[1] , demand_priority_r_reg, req_priority_r, col_wait_r_reg, req_wr_r_lcl_reg, periodic_rd_ack_r_lcl_reg, use_addr, accept_internal_r, periodic_rd_ack_r_lcl_reg_0, periodic_rd_ack_r_lcl_reg_1, rb_hit_busy_r_reg, pre_bm_end_r_reg_0, req_wr_r_lcl_reg_0, bm_end_r1_reg_1, \grant_r_reg[1]_0 , act_wait_r_lcl_reg_0, rb_hit_busy_r_reg_0, rb_hit_busy_r, \ras_timer_r_reg[1] , rd_wr_r_lcl_reg_0, bm_end_r1_reg_2, bm_end_r1_reg_3, bm_end_r1_reg_4, \ras_timer_r_reg[2] , req_wr_r_lcl_reg_1, pre_passing_open_bank_r_0, head_r_lcl_reg_2, ras_timer_zero_r, \grant_r_reg[0]_0 , rd_wr_r_lcl_reg_1); output \req_data_buf_addr_r_reg[4] ; output idle_r_lcl_reg_0; output wait_for_maint_r_lcl_reg_0; output bm_end_r1_reg; output pre_bm_end_r; output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; output pre_passing_open_bank_r; output q_has_rd; output q_has_priority; output idle_r_lcl_reg_1; output \order_q_r_reg[0]_0 ; output tail_r_3; output q_entry_r_4; output \rp_timer.rp_timer_r_reg[1] ; output req_bank_rdy_r_reg; output rb_hit_busies_ns; output bm_end_r1_reg_0; output granted_col_r_reg; output act_wait_r_lcl_reg; output p_9_in; output rd_wr_ns; output demand_priority_ns; output head_r_lcl_reg_0; output \q_entry_r_reg[0]_0 ; output set_order_q; output act_wait_ns; output \q_entry_r_reg[0]_1 ; output [2:0]D; output granted_row_ns; output granted_row_r_reg; input CLK; input wait_for_maint_ns; input pass_open_bank_ns; input pre_bm_end_ns; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ; input pre_passing_open_bank_ns; input q_has_rd_r_reg_0; input q_has_priority_r_reg_0; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_1; input ordered_r_lcl_reg_0; input idle_r_lcl_reg_2; input [0:0]SR; input \q_entry_r_reg[0]_2 ; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_1; input \req_bank_r_lcl_reg[0] ; input [0:0]rb_hit_busies_r; input [0:0]idle_r_lcl_reg_3; input rstdiv0_sync_r1_reg_rep__20; input \wtr_timer.wtr_cnt_r_reg[1] ; input col_wait_r; input \order_q_r_reg[0]_1 ; input rd_wr_r_lcl_reg; input \grant_r_reg[0] ; input init_calib_complete_reg_rep__6; input [0:0]cmd; input periodic_rd_insert; input [0:0]\grant_r_reg[1] ; input demand_priority_r_reg; input req_priority_r; input col_wait_r_reg; input req_wr_r_lcl_reg; input periodic_rd_ack_r_lcl_reg; input use_addr; input accept_internal_r; input periodic_rd_ack_r_lcl_reg_0; input periodic_rd_ack_r_lcl_reg_1; input rb_hit_busy_r_reg; input pre_bm_end_r_reg_0; input req_wr_r_lcl_reg_0; input bm_end_r1_reg_1; input [0:0]\grant_r_reg[1]_0 ; input act_wait_r_lcl_reg_0; input rb_hit_busy_r_reg_0; input [0:0]rb_hit_busy_r; input \ras_timer_r_reg[1] ; input rd_wr_r_lcl_reg_0; input bm_end_r1_reg_2; input bm_end_r1_reg_3; input bm_end_r1_reg_4; input \ras_timer_r_reg[2] ; input req_wr_r_lcl_reg_1; input pre_passing_open_bank_r_0; input head_r_lcl_reg_2; input ras_timer_zero_r; input \grant_r_reg[0]_0 ; input rd_wr_r_lcl_reg_1; wire CLK; wire [2:0]D; wire [0:0]SR; wire accept_internal_r; wire act_wait_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire [0:0]cmd; wire col_wait_r; wire col_wait_r_reg; wire demand_priority_ns; wire demand_priority_r_i_3__0_n_0; wire demand_priority_r_reg; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire [0:0]\grant_r_reg[1] ; wire [0:0]\grant_r_reg[1]_0 ; wire granted_col_r_reg; wire granted_row_ns; wire granted_row_r_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire i___7_i_3_n_0; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire [0:0]idle_r_lcl_reg_3; wire init_calib_complete_reg_rep__6; wire \order_q_r_reg[0]_0 ; wire \order_q_r_reg[0]_1 ; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire p_9_in; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_insert; wire pre_bm_end_ns; wire pre_bm_end_r; wire pre_bm_end_r_reg_0; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_0; wire q_entry_r_4; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire \q_entry_r_reg[0]_2 ; wire q_has_priority; wire q_has_priority_r_reg_0; wire q_has_rd; wire q_has_rd_r_reg_0; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[2] ; wire ras_timer_zero_r; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ; wire rb_hit_busies_ns; wire [0:0]rb_hit_busies_r; wire [0:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rd_wr_ns; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_r_reg; wire \req_data_buf_addr_r_reg[4] ; wire req_priority_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire set_order_q; wire tail_r_3; wire use_addr; wire wait_for_maint_ns; wire wait_for_maint_r_lcl_reg_0; wire \wtr_timer.wtr_cnt_r_reg[1] ; LUT3 #( .INIT(8'hA8)) accept_internal_r_i_1 (.I0(init_calib_complete_reg_rep__6), .I1(idle_r_lcl_reg_0), .I2(idle_r_lcl_reg_3), .O(p_9_in)); LUT6 #( .INIT(64'hEAEAEAEAEAFFEAEA)) act_wait_r_lcl_i_1__0 (.I0(bm_end_r1_reg_1), .I1(bm_end_r1_reg_0), .I2(bm_end_r1_reg), .I3(\grant_r_reg[1]_0 ), .I4(act_wait_r_lcl_reg_0), .I5(act_wait_r_lcl_reg), .O(act_wait_ns)); LUT5 #( .INIT(32'h00E00000)) act_wait_r_lcl_i_3 (.I0(req_wr_r_lcl_reg_1), .I1(pre_passing_open_bank_r_0), .I2(q_entry_r_4), .I3(\req_data_buf_addr_r_reg[4] ), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .O(act_wait_r_lcl_reg)); FDRE #( .INIT(1'b0)) auto_pre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(auto_pre_r_lcl_reg_0), .Q(\rp_timer.rp_timer_r_reg[1] ), .R(1'b0)); LUT5 #( .INIT(32'hAAEAEAEA)) bm_end_r1_i_1 (.I0(pre_bm_end_r), .I1(\grant_r_reg[1] ), .I2(bm_end_r1_reg), .I3(rd_wr_r_lcl_reg), .I4(req_wr_r_lcl_reg_0), .O(bm_end_r1_reg_0)); FDRE #( .INIT(1'b1)) \compute_tail.tail_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_2), .Q(tail_r_3), .R(rstdiv0_sync_r1_reg_rep__0)); LUT6 #( .INIT(64'h000000000000AAFE)) demand_priority_r_i_1 (.I0(demand_priority_r_reg), .I1(req_priority_r), .I2(q_has_priority), .I3(demand_priority_r_i_3__0_n_0), .I4(col_wait_r_reg), .I5(idle_r_lcl_reg_0), .O(demand_priority_ns)); LUT3 #( .INIT(8'h08)) demand_priority_r_i_3__0 (.I0(rd_wr_r_lcl_reg_1), .I1(req_bank_rdy_r_reg), .I2(rd_wr_r_lcl_reg), .O(demand_priority_r_i_3__0_n_0)); LUT6 #( .INIT(64'h00A800FC00A80000)) \grant_r[1]_i_2 (.I0(\wtr_timer.wtr_cnt_r_reg[1] ), .I1(act_wait_r_lcl_reg), .I2(col_wait_r), .I3(\order_q_r_reg[0]_1 ), .I4(rd_wr_r_lcl_reg), .I5(\grant_r_reg[0] ), .O(granted_col_r_reg)); LUT6 #( .INIT(64'h0000000000200000)) \grant_r[1]_i_2__0 (.I0(idle_r_lcl_reg_1), .I1(wait_for_maint_r_lcl_reg_0), .I2(act_wait_r_lcl_reg_0), .I3(\req_data_buf_addr_r_reg[4] ), .I4(ras_timer_zero_r), .I5(\grant_r_reg[0]_0 ), .O(granted_row_r_reg)); LUT2 #( .INIT(4'hE)) granted_row_r_i_1 (.I0(granted_row_r_reg), .I1(head_r_lcl_reg_2), .O(granted_row_ns)); FDRE #( .INIT(1'b0)) head_r_lcl_reg (.C(CLK), .CE(1'b1), .D(head_r_lcl_reg_1), .Q(idle_r_lcl_reg_1), .R(rstdiv0_sync_r1_reg_rep__0)); LUT6 #( .INIT(64'h8000800080000000)) i___14_i_1 (.I0(req_wr_r_lcl_reg_0), .I1(\req_data_buf_addr_r_reg[4] ), .I2(idle_r_lcl_reg_1), .I3(accept_internal_r), .I4(use_addr), .I5(periodic_rd_ack_r_lcl_reg), .O(set_order_q)); LUT4 #( .INIT(16'h8778)) i___5_i_2 (.I0(bm_end_r1_reg_0), .I1(rb_hit_busies_r), .I2(rb_hit_busy_r_reg_0), .I3(rb_hit_busy_r), .O(\q_entry_r_reg[0]_1 )); LUT6 #( .INIT(64'hBBBBBABB88888A88)) i___7_i_1 (.I0(q_entry_r_4), .I1(i___7_i_3_n_0), .I2(periodic_rd_ack_r_lcl_reg_0), .I3(\req_data_buf_addr_r_reg[4] ), .I4(periodic_rd_ack_r_lcl_reg_1), .I5(rb_hit_busy_r_reg), .O(head_r_lcl_reg_0)); LUT6 #( .INIT(64'hEFFFEFEEEFEEEFEE)) i___7_i_2 (.I0(bm_end_r1_reg_0), .I1(periodic_rd_ack_r_lcl_reg_1), .I2(periodic_rd_ack_r_lcl_reg_0), .I3(\req_data_buf_addr_r_reg[4] ), .I4(pre_bm_end_r_reg_0), .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .O(\q_entry_r_reg[0]_0 )); LUT3 #( .INIT(8'h08)) i___7_i_3 (.I0(pre_bm_end_r_reg_0), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .I2(\req_data_buf_addr_r_reg[4] ), .O(i___7_i_3_n_0)); LUT6 #( .INIT(64'hAAAEEEEEEEEEEEEE)) idle_r_lcl_i_1 (.I0(req_wr_r_lcl_reg), .I1(\req_data_buf_addr_r_reg[4] ), .I2(periodic_rd_ack_r_lcl_reg), .I3(use_addr), .I4(accept_internal_r), .I5(idle_r_lcl_reg_1), .O(idle_r_lcl_reg_0)); FDRE #( .INIT(1'b0)) idle_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_0), .Q(\req_data_buf_addr_r_reg[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \order_q_r_reg[0] (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_1), .Q(req_bank_rdy_r_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) ordered_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_0), .Q(\order_q_r_reg[0]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) pass_open_bank_r_lcl_reg (.C(CLK), .CE(1'b1), .D(pass_open_bank_ns), .Q(bm_end_r1_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) pre_bm_end_r_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_ns), .Q(pre_bm_end_r), .R(1'b0)); FDRE #( .INIT(1'b0)) pre_passing_open_bank_r_reg (.C(CLK), .CE(1'b1), .D(pre_passing_open_bank_ns), .Q(pre_passing_open_bank_r), .R(1'b0)); FDSE #( .INIT(1'b1)) \q_entry_r_reg[0] (.C(CLK), .CE(1'b1), .D(\q_entry_r_reg[0]_2 ), .Q(q_entry_r_4), .S(SR)); FDRE #( .INIT(1'b0)) q_has_priority_r_reg (.C(CLK), .CE(1'b1), .D(q_has_priority_r_reg_0), .Q(q_has_priority), .R(1'b0)); FDRE #( .INIT(1'b0)) q_has_rd_r_reg (.C(CLK), .CE(1'b1), .D(q_has_rd_r_reg_0), .Q(q_has_rd), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1058" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[0]_i_1__0 (.I0(\ras_timer_r_reg[1] ), .I1(act_wait_r_lcl_reg), .I2(rd_wr_r_lcl_reg_0), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair1058" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[1]_i_1__0 (.I0(bm_end_r1_reg_2), .I1(act_wait_r_lcl_reg), .I2(bm_end_r1_reg_3), .O(D[1])); LUT3 #( .INIT(8'hB8)) \ras_timer_r[2]_i_1__0 (.I0(bm_end_r1_reg_4), .I1(act_wait_r_lcl_reg), .I2(\ras_timer_r_reg[2] ), .O(D[2])); LUT6 #( .INIT(64'h00000000000022F0)) \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 (.I0(\req_bank_r_lcl_reg[0] ), .I1(idle_r_lcl_reg_0), .I2(rb_hit_busies_r), .I3(idle_r_lcl_reg_3), .I4(bm_end_r1_reg_0), .I5(rstdiv0_sync_r1_reg_rep__20), .O(rb_hit_busies_ns)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .R(1'b0)); LUT5 #( .INIT(32'hE0E0EFE0)) rd_wr_r_lcl_i_1 (.I0(cmd), .I1(periodic_rd_insert), .I2(idle_r_lcl_reg_0), .I3(rd_wr_r_lcl_reg), .I4(\grant_r_reg[1] ), .O(rd_wr_ns)); FDRE #( .INIT(1'b0)) wait_for_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(wait_for_maint_ns), .Q(wait_for_maint_r_lcl_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_state" *) module ddr3_ifmig_7series_v4_0_bank_state (\act_this_rank_r_reg[0]_0 , bm_end_r1, ras_timer_zero_r, \rp_timer.rp_timer_r_reg[1]_0 , act_this_rank_r, req_bank_rdy_r, demanded_prior_r_reg_0, demanded_prior_r_reg_1, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, col_wait_r, ofs_rdy_r0, pre_wait_r_reg_0, pre_wait_r_reg_1, pre_bm_end_ns, pre_passing_open_bank_ns, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[2]_0 , granted_pre_ns, \grant_r_reg[1] , rnk_config_strobe_ns, \rnk_config_strobe_r_reg[0] , granted_col_r_reg, \ras_timer_r_reg[0]_0 , auto_pre_r_lcl_reg, granted_col_r_reg_0, act_wait_ns, CLK, pre_bm_end_r_reg, req_bank_rdy_ns, override_demand_ns, rstdiv0_sync_r1_reg_rep__0, phy_mc_ctl_full, SR, of_ctl_full_v, start_wtp_timer0, rd_wr_r_lcl_reg, \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , rd_wr_r_lcl_reg_0, req_priority_r, q_has_priority, \order_q_r_reg[0] , idle_r_lcl_reg, \grant_r_reg[1]_0 , pre_passing_open_bank_r_reg, pass_open_bank_r_lcl_reg, pass_open_bank_r_lcl_reg_0, rd_wr_r_lcl_reg_1, bm_end_r1_reg_0, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[0] , \grant_r_reg[0]_0 , auto_pre_r_lcl_reg_0, auto_pre_r_lcl_reg_1, req_bank_rdy_ns_1, demand_priority_r_reg_0, rnk_config_valid_r_lcl_reg, \rnk_config_strobe_r_reg[0]_0 , rd_wr_r_lcl_reg_2, \order_q_r_reg[0]_0 , tail_r, accept_r_reg, demanded_prior_r_1, demand_priority_r_2, q_has_rd, req_wr_r_lcl_reg, req_bank_rdy_r_reg_0, D, rstdiv0_sync_r1_reg_rep__20, pass_open_bank_r_lcl_reg_1, pass_open_bank_r_lcl_reg_2, granted_col_r_reg_1); output \act_this_rank_r_reg[0]_0 ; output bm_end_r1; output ras_timer_zero_r; output \rp_timer.rp_timer_r_reg[1]_0 ; output [0:0]act_this_rank_r; output req_bank_rdy_r; output demanded_prior_r_reg_0; output demanded_prior_r_reg_1; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output col_wait_r; output ofs_rdy_r0; output pre_wait_r_reg_0; output pre_wait_r_reg_1; output pre_bm_end_ns; output pre_passing_open_bank_ns; output \ras_timer_r_reg[1]_0 ; output \ras_timer_r_reg[2]_0 ; output granted_pre_ns; output \grant_r_reg[1] ; output rnk_config_strobe_ns; output \rnk_config_strobe_r_reg[0] ; output granted_col_r_reg; output \ras_timer_r_reg[0]_0 ; output auto_pre_r_lcl_reg; output granted_col_r_reg_0; input act_wait_ns; input CLK; input pre_bm_end_r_reg; input req_bank_rdy_ns; input override_demand_ns; input rstdiv0_sync_r1_reg_rep__0; input phy_mc_ctl_full; input [0:0]SR; input [0:0]of_ctl_full_v; input start_wtp_timer0; input rd_wr_r_lcl_reg; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input rd_wr_r_lcl_reg_0; input req_priority_r; input q_has_priority; input \order_q_r_reg[0] ; input [0:0]idle_r_lcl_reg; input [1:0]\grant_r_reg[1]_0 ; input pre_passing_open_bank_r_reg; input pass_open_bank_r_lcl_reg; input pass_open_bank_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input bm_end_r1_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\grant_r_reg[0] ; input [0:0]\grant_r_reg[0]_0 ; input auto_pre_r_lcl_reg_0; input auto_pre_r_lcl_reg_1; input req_bank_rdy_ns_1; input demand_priority_r_reg_0; input rnk_config_valid_r_lcl_reg; input \rnk_config_strobe_r_reg[0]_0 ; input rd_wr_r_lcl_reg_2; input \order_q_r_reg[0]_0 ; input tail_r; input accept_r_reg; input demanded_prior_r_1; input demand_priority_r_2; input q_has_rd; input req_wr_r_lcl_reg; input req_bank_rdy_r_reg_0; input [2:0]D; input rstdiv0_sync_r1_reg_rep__20; input pass_open_bank_r_lcl_reg_1; input pass_open_bank_r_lcl_reg_2; input granted_col_r_reg_1; wire CLK; wire [2:0]D; wire [0:0]SR; wire accept_r_reg; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0]_0 ; wire act_wait_ns; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire \bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ; wire \bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ; wire bm_end_r1; wire bm_end_r1_reg_0; wire col_wait_r; wire col_wait_r_i_1_n_0; wire demand_priority_ns; wire demand_priority_r_2; wire demand_priority_r_i_2_n_0; wire demand_priority_r_i_4_n_0; wire demand_priority_r_reg_0; wire demanded_prior_ns; wire demanded_prior_r_1; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire \grant_r[1]_i_8_n_0 ; wire [0:0]\grant_r_reg[0] ; wire [0:0]\grant_r_reg[0]_0 ; wire \grant_r_reg[1] ; wire [1:0]\grant_r_reg[1]_0 ; wire granted_col_r_reg; wire granted_col_r_reg_0; wire granted_col_r_reg_1; wire granted_pre_ns; wire [0:0]idle_r_lcl_reg; wire [0:0]of_ctl_full_v; wire ofs_rdy_r; wire ofs_rdy_r0; wire ofs_rdy_r0_0; wire \order_q_r_reg[0] ; wire \order_q_r_reg[0]_0 ; wire override_demand_ns; wire override_demand_r; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire pass_open_bank_r_lcl_reg_1; wire pass_open_bank_r_lcl_reg_2; wire phy_mc_ctl_full; wire pre_bm_end_ns; wire pre_bm_end_r_reg; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r_reg; wire pre_wait_ns; wire pre_wait_r_reg_0; wire pre_wait_r_reg_1; wire q_has_priority; wire q_has_rd; wire [2:0]ras_timer_r; wire \ras_timer_r[2]_i_4_n_0 ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2]_0 ; wire ras_timer_zero_ns; wire ras_timer_zero_r; wire rcd_active_r; wire \rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ; wire [0:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire req_bank_rdy_ns; wire req_bank_rdy_ns_1; wire req_bank_rdy_r; wire req_bank_rdy_r_reg_0; wire req_priority_r; wire req_wr_r_lcl_reg; wire rnk_config_strobe_ns; wire \rnk_config_strobe_r_reg[0] ; wire \rnk_config_strobe_r_reg[0]_0 ; wire rnk_config_valid_r_lcl_reg; wire \rp_timer.rp_timer_r[0]_i_1_n_0 ; wire \rp_timer.rp_timer_r[1]_i_2_n_0 ; wire \rp_timer.rp_timer_r_reg[1]_0 ; wire [0:0]rp_timer_ns; wire [1:0]rp_timer_r; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire \rtp_timer_r[0]_i_1_n_0 ; wire start_pre; wire start_wtp_timer0; wire [1:0]starve_limit_cntr_r; wire \starve_limit_cntr_r[0]_i_1_n_0 ; wire \starve_limit_cntr_r[1]_i_1_n_0 ; wire tail_r; wire [0:0]wr_this_rank_r; FDRE #( .INIT(1'b0)) \act_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(\act_this_rank_r_reg[0]_0 ), .Q(act_this_rank_r), .R(1'b0)); FDRE #( .INIT(1'b0)) act_wait_r_lcl_reg (.C(CLK), .CE(1'b1), .D(act_wait_ns), .Q(\act_this_rank_r_reg[0]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) bm_end_r1_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_r_reg), .Q(bm_end_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1055" *) LUT4 #( .INIT(16'hFFBA)) col_wait_r_i_1 (.I0(rcd_active_r), .I1(\grant_r_reg[1]_0 [0]), .I2(col_wait_r), .I3(pre_passing_open_bank_r_reg), .O(col_wait_r_i_1_n_0)); FDRE #( .INIT(1'b0)) col_wait_r_reg (.C(CLK), .CE(1'b1), .D(col_wait_r_i_1_n_0), .Q(col_wait_r), .R(SR)); LUT6 #( .INIT(64'h000000000000AAFE)) demand_priority_r_i_1__0 (.I0(demand_priority_r_i_2_n_0), .I1(req_priority_r), .I2(q_has_priority), .I3(\order_q_r_reg[0] ), .I4(demand_priority_r_i_4_n_0), .I5(idle_r_lcl_reg), .O(demand_priority_ns)); LUT6 #( .INIT(64'hEAAAEAEAAAAAAAAA)) demand_priority_r_i_2 (.I0(demanded_prior_r_reg_0), .I1(starve_limit_cntr_r[0]), .I2(starve_limit_cntr_r[1]), .I3(q_has_rd), .I4(req_wr_r_lcl_reg), .I5(req_bank_rdy_r_reg_0), .O(demand_priority_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1055" *) LUT4 #( .INIT(16'h0051)) demand_priority_r_i_4 (.I0(pre_passing_open_bank_r_reg), .I1(col_wait_r), .I2(\grant_r_reg[1]_0 [0]), .I3(rcd_active_r), .O(demand_priority_r_i_4_n_0)); FDRE #( .INIT(1'b0)) demand_priority_r_reg (.C(CLK), .CE(1'b1), .D(demand_priority_ns), .Q(demanded_prior_r_reg_0), .R(1'b0)); LUT5 #( .INIT(32'h00000D00)) demanded_prior_r_i_1 (.I0(demanded_prior_r_reg_0), .I1(demanded_prior_r_reg_1), .I2(demanded_prior_r_1), .I3(demand_priority_r_2), .I4(\grant_r_reg[1]_0 [1]), .O(demanded_prior_ns)); FDRE #( .INIT(1'b0)) demanded_prior_r_reg (.C(CLK), .CE(1'b1), .D(demanded_prior_ns), .Q(demanded_prior_r_reg_1), .R(1'b0)); LUT6 #( .INIT(64'h00000100FFFFFFFF)) \grant_r[1]_i_10 (.I0(override_demand_r), .I1(demanded_prior_r_reg_0), .I2(demanded_prior_r_1), .I3(demand_priority_r_2), .I4(\grant_r_reg[1]_0 [1]), .I5(rnk_config_valid_r_lcl_reg), .O(granted_col_r_reg_0)); (* SOFT_HLUTNM = "soft_lutpair1053" *) LUT4 #( .INIT(16'h1000)) \grant_r[1]_i_3__0 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[0]_0 ), .I2(\rp_timer.rp_timer_r_reg[1]_0 ), .I3(ras_timer_zero_r), .O(\grant_r_reg[1] )); LUT5 #( .INIT(32'hEEEEFEEE)) \grant_r[1]_i_5 (.I0(\grant_r[1]_i_8_n_0 ), .I1(\rnk_config_strobe_r_reg[0]_0 ), .I2(rd_wr_r_lcl_reg_2), .I3(\order_q_r_reg[0]_0 ), .I4(rd_wr_r_lcl_reg_0), .O(granted_col_r_reg)); LUT6 #( .INIT(64'h5555555555575555)) \grant_r[1]_i_8 (.I0(rnk_config_valid_r_lcl_reg), .I1(override_demand_r), .I2(demand_priority_r_2), .I3(demanded_prior_r_reg_1), .I4(demanded_prior_r_reg_0), .I5(\grant_r_reg[1]_0 [0]), .O(\grant_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'h2222222220222020)) i___36_i_1 (.I0(tail_r), .I1(accept_r_reg), .I2(rcd_active_r), .I3(\grant_r_reg[1]_0 [0]), .I4(col_wait_r), .I5(\act_this_rank_r_reg[0]_0 ), .O(auto_pre_r_lcl_reg)); LUT4 #( .INIT(16'h0010)) i___43_i_1 (.I0(demand_priority_r_2), .I1(demanded_prior_r_reg_1), .I2(demanded_prior_r_reg_0), .I3(\grant_r_reg[1]_0 [0]), .O(\rnk_config_strobe_r_reg[0] )); LUT5 #( .INIT(32'h000F0001)) ofs_rdy_r_i_1 (.I0(\entry_cnt_reg[2] ), .I1(\entry_cnt_reg[2]_0 ), .I2(\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ), .I3(\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ), .I4(rd_wr_r_lcl_reg), .O(ofs_rdy_r0_0)); LUT5 #( .INIT(32'h000F0001)) ofs_rdy_r_i_1__0 (.I0(\entry_cnt_reg[2] ), .I1(\entry_cnt_reg[2]_0 ), .I2(\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ), .I3(\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ), .I4(rd_wr_r_lcl_reg_0), .O(ofs_rdy_r0)); FDRE #( .INIT(1'b0)) ofs_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ofs_rdy_r0_0), .Q(ofs_rdy_r), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) override_demand_r_reg (.C(CLK), .CE(1'b1), .D(override_demand_ns), .Q(override_demand_r), .R(1'b0)); FDRE #( .INIT(1'b0)) phy_mc_cmd_full_r_reg (.C(CLK), .CE(1'b1), .D(of_ctl_full_v), .Q(\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ), .R(SR)); FDRE #( .INIT(1'b0)) phy_mc_ctl_full_r_reg (.C(CLK), .CE(1'b1), .D(phy_mc_ctl_full), .Q(\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ), .R(rstdiv0_sync_r1_reg_rep__0)); (* SOFT_HLUTNM = "soft_lutpair1054" *) LUT5 #( .INIT(32'hFFFF0008)) \pre_4_1_1T_arb.granted_pre_r_i_1 (.I0(ras_timer_zero_r), .I1(\rp_timer.rp_timer_r_reg[1]_0 ), .I2(\grant_r_reg[0]_0 ), .I3(auto_pre_r_lcl_reg_0), .I4(auto_pre_r_lcl_reg_1), .O(granted_pre_ns)); (* SOFT_HLUTNM = "soft_lutpair1056" *) LUT3 #( .INIT(8'hBA)) pre_bm_end_r_i_1__0 (.I0(pre_passing_open_bank_ns), .I1(rp_timer_r[1]), .I2(rp_timer_r[0]), .O(pre_bm_end_ns)); LUT6 #( .INIT(64'hAAA8AAAAAAA8AAA8)) pre_passing_open_bank_r_i_1__0 (.I0(pass_open_bank_r_lcl_reg), .I1(\grant_r_reg[1]_0 [0]), .I2(pre_wait_r_reg_1), .I3(pre_wait_r_reg_0), .I4(ras_timer_zero_r), .I5(\rp_timer.rp_timer_r_reg[1]_0 ), .O(pre_passing_open_bank_ns)); LUT6 #( .INIT(64'h0040555500400040)) pre_wait_r_i_1__0 (.I0(pass_open_bank_r_lcl_reg), .I1(pass_open_bank_r_lcl_reg_0), .I2(pre_wait_r_reg_0), .I3(pre_wait_r_reg_1), .I4(rp_timer_ns), .I5(\rp_timer.rp_timer_r_reg[1]_0 ), .O(pre_wait_ns)); (* SOFT_HLUTNM = "soft_lutpair1053" *) LUT5 #( .INIT(32'hEAEAEAAA)) pre_wait_r_i_3 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(ras_timer_zero_r), .I2(\rp_timer.rp_timer_r_reg[1]_0 ), .I3(\grant_r_reg[0]_0 ), .I4(auto_pre_r_lcl_reg_0), .O(rp_timer_ns)); FDRE #( .INIT(1'b0)) pre_wait_r_reg (.C(CLK), .CE(1'b1), .D(pre_wait_ns), .Q(\rp_timer.rp_timer_r_reg[1]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h000000000E0E000E)) \ras_timer_r[0]_i_3 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(\grant_r_reg[1]_0 [0]), .I4(rd_wr_r_lcl_reg), .I5(bm_end_r1_reg_0), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'h1110101111101010)) \ras_timer_r[1]_i_3 (.I0(bm_end_r1), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\ras_timer_r[2]_i_4_n_0 ), .I3(ras_timer_r[0]), .I4(ras_timer_r[1]), .I5(ras_timer_r[2]), .O(\ras_timer_r_reg[1]_0 )); LUT6 #( .INIT(64'h1110111011101010)) \ras_timer_r[2]_i_3 (.I0(bm_end_r1), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\ras_timer_r[2]_i_4_n_0 ), .I3(ras_timer_r[2]), .I4(ras_timer_r[1]), .I5(ras_timer_r[0]), .O(\ras_timer_r_reg[2]_0 )); LUT6 #( .INIT(64'h22222222222222F2)) \ras_timer_r[2]_i_4 (.I0(\grant_r_reg[1]_0 [0]), .I1(rd_wr_r_lcl_reg), .I2(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ), .I3(ras_timer_r[2]), .I4(ras_timer_r[1]), .I5(ras_timer_r[0]), .O(\ras_timer_r[2]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \ras_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(ras_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ras_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(ras_timer_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ras_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(ras_timer_r[2]), .R(1'b0)); LUT6 #( .INIT(64'hFFFF1000FFFF1100)) ras_timer_zero_r_i_1 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(rd_wr_r_lcl_reg_1), .I4(bm_end_r1_reg_0), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ), .O(ras_timer_zero_ns)); FDRE #( .INIT(1'b0)) ras_timer_zero_r_reg (.C(CLK), .CE(1'b1), .D(ras_timer_zero_ns), .Q(ras_timer_zero_r), .R(1'b0)); LUT2 #( .INIT(4'h8)) \rcd_timer_gt_2.rcd_timer_r[0]_i_1 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[0] ), .O(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rcd_timer_gt_2.rcd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ), .Q(rcd_active_r), .R(SR)); FDRE #( .INIT(1'b0)) \rd_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_wr_r_lcl_reg), .Q(rd_this_rank_r), .R(1'b0)); FDRE #( .INIT(1'b0)) req_bank_rdy_r_reg (.C(CLK), .CE(1'b1), .D(req_bank_rdy_ns), .Q(req_bank_rdy_r), .R(1'b0)); LUT6 #( .INIT(64'h0000004F00000044)) \rnk_config_strobe_r[0]_i_1 (.I0(\rnk_config_strobe_r_reg[0] ), .I1(req_bank_rdy_ns_1), .I2(demand_priority_r_reg_0), .I3(rnk_config_valid_r_lcl_reg), .I4(override_demand_ns), .I5(req_bank_rdy_ns), .O(rnk_config_strobe_ns)); (* SOFT_HLUTNM = "soft_lutpair1056" *) LUT4 #( .INIT(16'h0004)) \rp_timer.rp_timer_r[0]_i_1 (.I0(rp_timer_r[0]), .I1(rp_timer_r[1]), .I2(start_pre), .I3(rstdiv0_sync_r1_reg_rep__20), .O(\rp_timer.rp_timer_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1054" *) LUT4 #( .INIT(16'hE000)) \rp_timer.rp_timer_r[0]_i_2 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[0]_0 ), .I2(\rp_timer.rp_timer_r_reg[1]_0 ), .I3(ras_timer_zero_r), .O(start_pre)); LUT6 #( .INIT(64'hF888F888F8888888)) \rp_timer.rp_timer_r[1]_i_2 (.I0(rp_timer_r[1]), .I1(rp_timer_r[0]), .I2(ras_timer_zero_r), .I3(\rp_timer.rp_timer_r_reg[1]_0 ), .I4(\grant_r_reg[0]_0 ), .I5(auto_pre_r_lcl_reg_0), .O(\rp_timer.rp_timer_r[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[0]_i_1_n_0 ), .Q(rp_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[1]_i_2_n_0 ), .Q(rp_timer_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); LUT4 #( .INIT(16'h0010)) \rtp_timer_r[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(pass_open_bank_r_lcl_reg_1), .I2(pre_wait_r_reg_1), .I3(pre_wait_r_reg_0), .O(\rtp_timer_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rtp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[0]_i_1_n_0 ), .Q(pre_wait_r_reg_0), .R(1'b0)); FDRE #( .INIT(1'b0)) \rtp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(pass_open_bank_r_lcl_reg_2), .Q(pre_wait_r_reg_1), .R(1'b0)); LUT6 #( .INIT(64'hFFF7080800000000)) \starve_limit_cntr_r[0]_i_1 (.I0(req_bank_rdy_r), .I1(granted_col_r_reg_1), .I2(\grant_r_reg[1]_0 [0]), .I3(starve_limit_cntr_r[1]), .I4(starve_limit_cntr_r[0]), .I5(col_wait_r), .O(\starve_limit_cntr_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFF08FF0000000000)) \starve_limit_cntr_r[1]_i_1 (.I0(req_bank_rdy_r), .I1(granted_col_r_reg_1), .I2(\grant_r_reg[1]_0 [0]), .I3(starve_limit_cntr_r[1]), .I4(starve_limit_cntr_r[0]), .I5(col_wait_r), .O(\starve_limit_cntr_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \starve_limit_cntr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[0]_i_1_n_0 ), .Q(starve_limit_cntr_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \starve_limit_cntr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[1]_i_1_n_0 ), .Q(starve_limit_cntr_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(start_wtp_timer0), .Q(wr_this_rank_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_state" *) module ddr3_ifmig_7series_v4_0_bank_state__parameterized0 (\act_this_rank_r_reg[0]_0 , act_this_rank_r, wr_this_rank_r, rd_this_rank_r, bm_end_r1_0, ras_timer_zero_r, pre_wait_r, req_bank_rdy_r, req_bank_rdy_ns_1, demanded_prior_r_reg_0, demanded_prior_r, ofs_rdy_r, \rcd_timer_gt_2.rcd_timer_r_reg[0]_0 , col_wait_r, pre_bm_end_ns, pre_passing_open_bank_ns, demand_priority_r_reg_0, \cmd_pipe_plus.mc_address_reg[10] , Q, \ras_timer_r_reg[2]_0 , \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[0]_0 , auto_pre_r_lcl_reg, \pre_4_1_1T_arb.granted_pre_r_reg , \rnk_config_strobe_r_reg[0] , demand_priority_r_reg_1, act_wait_ns, CLK, start_wtp_timer0, rd_wr_r_lcl_reg, pre_bm_end_r_reg, demand_priority_ns, rstdiv0_sync_r1_reg_rep__0, ofs_rdy_r0, SR, pass_open_bank_ns, \grant_r_reg[1] , rtp_timer_ns1, pre_passing_open_bank_r_reg, \req_row_r_lcl_reg[10] , \grant_r_reg[0] , act_wait_r_lcl_reg_0, \req_row_r_lcl_reg[10]_0 , mc_cs_n_ns, rd_wr_r_lcl_reg_0, bm_end_r1_reg_0, \ras_timer_r_reg[2]_1 , rstdiv0_sync_r1_reg_rep__21, \order_q_r_reg[0] , rd_wr_r_lcl_reg_1, tail_r_3, accept_r_reg, \grant_r_reg[1]_0 , auto_pre_r_lcl_reg_0, \grant_r_reg[1]_1 , demanded_prior_r_1, demand_priority_r_2, q_has_rd, req_wr_r_lcl_reg, req_bank_rdy_r_reg_0, D, pass_open_bank_r_lcl_reg, rstdiv0_sync_r1_reg_rep__20, granted_col_r_reg); output \act_this_rank_r_reg[0]_0 ; output [0:0]act_this_rank_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output bm_end_r1_0; output ras_timer_zero_r; output pre_wait_r; output req_bank_rdy_r; output req_bank_rdy_ns_1; output demanded_prior_r_reg_0; output demanded_prior_r; output ofs_rdy_r; output \rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ; output col_wait_r; output pre_bm_end_ns; output pre_passing_open_bank_ns; output demand_priority_r_reg_0; output [0:0]\cmd_pipe_plus.mc_address_reg[10] ; output [2:0]Q; output \ras_timer_r_reg[2]_0 ; output \ras_timer_r_reg[1]_0 ; output \ras_timer_r_reg[0]_0 ; output auto_pre_r_lcl_reg; output \pre_4_1_1T_arb.granted_pre_r_reg ; output \rnk_config_strobe_r_reg[0] ; output demand_priority_r_reg_1; input act_wait_ns; input CLK; input start_wtp_timer0; input rd_wr_r_lcl_reg; input pre_bm_end_r_reg; input demand_priority_ns; input rstdiv0_sync_r1_reg_rep__0; input ofs_rdy_r0; input [0:0]SR; input pass_open_bank_ns; input [1:0]\grant_r_reg[1] ; input rtp_timer_ns1; input pre_passing_open_bank_r_reg; input [0:0]\req_row_r_lcl_reg[10] ; input \grant_r_reg[0] ; input act_wait_r_lcl_reg_0; input [0:0]\req_row_r_lcl_reg[10]_0 ; input [0:0]mc_cs_n_ns; input rd_wr_r_lcl_reg_0; input bm_end_r1_reg_0; input \ras_timer_r_reg[2]_1 ; input rstdiv0_sync_r1_reg_rep__21; input \order_q_r_reg[0] ; input rd_wr_r_lcl_reg_1; input tail_r_3; input accept_r_reg; input [0:0]\grant_r_reg[1]_0 ; input auto_pre_r_lcl_reg_0; input [0:0]\grant_r_reg[1]_1 ; input demanded_prior_r_1; input demand_priority_r_2; input q_has_rd; input req_wr_r_lcl_reg; input req_bank_rdy_r_reg_0; input [2:0]D; input pass_open_bank_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__20; input granted_col_r_reg; wire CLK; wire [2:0]D; wire [2:0]Q; wire [0:0]SR; wire accept_r_reg; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0]_0 ; wire act_wait_ns; wire act_wait_r_lcl_reg_0; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_0; wire bm_end_r1_reg_0; wire [0:0]\cmd_pipe_plus.mc_address_reg[10] ; wire col_wait_r; wire col_wait_r_i_1__0_n_0; wire demand_priority_ns; wire demand_priority_r_2; wire demand_priority_r_reg_0; wire demand_priority_r_reg_1; wire demanded_prior_ns; wire demanded_prior_r; wire demanded_prior_r_1; wire demanded_prior_r_reg_0; wire \grant_r_reg[0] ; wire [1:0]\grant_r_reg[1] ; wire [0:0]\grant_r_reg[1]_0 ; wire [0:0]\grant_r_reg[1]_1 ; wire granted_col_r_reg; wire [0:0]mc_cs_n_ns; wire ofs_rdy_r; wire ofs_rdy_r0; wire \order_q_r_reg[0] ; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire pre_bm_end_ns; wire pre_bm_end_r_reg; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r_reg; wire pre_wait_ns; wire pre_wait_r; wire q_has_rd; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire ras_timer_zero_r; wire ras_timer_zero_r_i_1__0_n_0; wire rcd_active_r; wire \rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ; wire [0:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire req_bank_rdy_ns_1; wire req_bank_rdy_r; wire req_bank_rdy_r_reg_0; wire [0:0]\req_row_r_lcl_reg[10] ; wire [0:0]\req_row_r_lcl_reg[10]_0 ; wire req_wr_r_lcl_reg; wire \rnk_config_strobe_r_reg[0] ; wire \rp_timer.rp_timer_r[0]_i_1_n_0 ; wire \rp_timer.rp_timer_r[1]_i_1_n_0 ; wire \rp_timer.rp_timer_r_reg_n_0_[0] ; wire \rp_timer.rp_timer_r_reg_n_0_[1] ; wire [0:0]rp_timer_ns; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rtp_timer_ns1; wire [1:0]rtp_timer_r; wire \rtp_timer_r[0]_i_1_n_0 ; wire \rtp_timer_r[1]_i_1_n_0 ; wire start_pre; wire start_wtp_timer0; wire [1:0]starve_limit_cntr_r; wire \starve_limit_cntr_r[0]_i_1_n_0 ; wire \starve_limit_cntr_r[1]_i_1_n_0 ; wire tail_r_3; wire [0:0]wr_this_rank_r; FDRE #( .INIT(1'b0)) \act_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(\act_this_rank_r_reg[0]_0 ), .Q(act_this_rank_r), .R(1'b0)); FDRE #( .INIT(1'b0)) act_wait_r_lcl_reg (.C(CLK), .CE(1'b1), .D(act_wait_ns), .Q(\act_this_rank_r_reg[0]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) bm_end_r1_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_r_reg), .Q(bm_end_r1_0), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFF8888888)) \cmd_pipe_plus.mc_address[10]_i_1 (.I0(\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ), .I1(\req_row_r_lcl_reg[10] ), .I2(\grant_r_reg[0] ), .I3(act_wait_r_lcl_reg_0), .I4(\req_row_r_lcl_reg[10]_0 ), .I5(mc_cs_n_ns), .O(\cmd_pipe_plus.mc_address_reg[10] )); (* SOFT_HLUTNM = "soft_lutpair1062" *) LUT4 #( .INIT(16'hFFBA)) col_wait_r_i_1__0 (.I0(rcd_active_r), .I1(\grant_r_reg[1] [1]), .I2(col_wait_r), .I3(pre_passing_open_bank_r_reg), .O(col_wait_r_i_1__0_n_0)); FDRE #( .INIT(1'b0)) col_wait_r_reg (.C(CLK), .CE(1'b1), .D(col_wait_r_i_1__0_n_0), .Q(col_wait_r), .R(SR)); LUT6 #( .INIT(64'hEAAAEAEAAAAAAAAA)) demand_priority_r_i_2__0 (.I0(demanded_prior_r_reg_0), .I1(starve_limit_cntr_r[0]), .I2(starve_limit_cntr_r[1]), .I3(q_has_rd), .I4(req_wr_r_lcl_reg), .I5(req_bank_rdy_r_reg_0), .O(demand_priority_r_reg_1)); (* SOFT_HLUTNM = "soft_lutpair1062" *) LUT4 #( .INIT(16'h0051)) demand_priority_r_i_4__0 (.I0(pre_passing_open_bank_r_reg), .I1(col_wait_r), .I2(\grant_r_reg[1] [1]), .I3(rcd_active_r), .O(demand_priority_r_reg_0)); FDRE #( .INIT(1'b0)) demand_priority_r_reg (.C(CLK), .CE(1'b1), .D(demand_priority_ns), .Q(demanded_prior_r_reg_0), .R(1'b0)); LUT5 #( .INIT(32'h00000D00)) demanded_prior_r_i_1__0 (.I0(demanded_prior_r_reg_0), .I1(demanded_prior_r), .I2(demanded_prior_r_1), .I3(demand_priority_r_2), .I4(\grant_r_reg[1] [0]), .O(demanded_prior_ns)); FDRE #( .INIT(1'b0)) demanded_prior_r_reg (.C(CLK), .CE(1'b1), .D(demanded_prior_ns), .Q(demanded_prior_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1059" *) LUT4 #( .INIT(16'h1000)) \grant_r[1]_i_2__1 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[1]_1 ), .I2(pre_wait_r), .I3(ras_timer_zero_r), .O(\pre_4_1_1T_arb.granted_pre_r_reg )); LUT6 #( .INIT(64'h2222222220222020)) i___13_i_1 (.I0(tail_r_3), .I1(accept_r_reg), .I2(rcd_active_r), .I3(\grant_r_reg[1] [1]), .I4(col_wait_r), .I5(\act_this_rank_r_reg[0]_0 ), .O(auto_pre_r_lcl_reg)); LUT4 #( .INIT(16'h0010)) i___43_i_2 (.I0(demand_priority_r_2), .I1(demanded_prior_r), .I2(demanded_prior_r_reg_0), .I3(\grant_r_reg[1] [1]), .O(\rnk_config_strobe_r_reg[0] )); FDRE #( .INIT(1'b0)) ofs_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ofs_rdy_r0), .Q(ofs_rdy_r), .R(rstdiv0_sync_r1_reg_rep__0)); (* SOFT_HLUTNM = "soft_lutpair1061" *) LUT3 #( .INIT(8'hBA)) pre_bm_end_r_i_1 (.I0(pre_passing_open_bank_ns), .I1(\rp_timer.rp_timer_r_reg_n_0_[1] ), .I2(\rp_timer.rp_timer_r_reg_n_0_[0] ), .O(pre_bm_end_ns)); LUT6 #( .INIT(64'hAAA8AAAAAAA8AAA8)) pre_passing_open_bank_r_i_1 (.I0(pass_open_bank_ns), .I1(\grant_r_reg[1] [1]), .I2(rtp_timer_r[1]), .I3(rtp_timer_r[0]), .I4(ras_timer_zero_r), .I5(pre_wait_r), .O(pre_passing_open_bank_ns)); LUT6 #( .INIT(64'h0404040404550404)) pre_wait_r_i_1 (.I0(pass_open_bank_ns), .I1(pre_wait_r), .I2(rp_timer_ns), .I3(rtp_timer_ns1), .I4(rtp_timer_r[0]), .I5(rtp_timer_r[1]), .O(pre_wait_ns)); (* SOFT_HLUTNM = "soft_lutpair1059" *) LUT5 #( .INIT(32'hEAEAEAAA)) pre_wait_r_i_2__0 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(ras_timer_zero_r), .I2(pre_wait_r), .I3(\grant_r_reg[1]_1 ), .I4(auto_pre_r_lcl_reg_0), .O(rp_timer_ns)); FDRE #( .INIT(1'b0)) pre_wait_r_reg (.C(CLK), .CE(1'b1), .D(pre_wait_ns), .Q(pre_wait_r), .R(1'b0)); LUT6 #( .INIT(64'h000000000000BBB0)) \ras_timer_r[0]_i_2 (.I0(rd_wr_r_lcl_reg), .I1(\grant_r_reg[1] [1]), .I2(Q[2]), .I3(Q[1]), .I4(bm_end_r1_reg_0), .I5(Q[0]), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'h1110101111101010)) \ras_timer_r[1]_i_2 (.I0(bm_end_r1_0), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\ras_timer_r_reg[2]_1 ), .I3(Q[0]), .I4(Q[1]), .I5(Q[2]), .O(\ras_timer_r_reg[1]_0 )); LUT6 #( .INIT(64'h000000000000EEEA)) \ras_timer_r[2]_i_2 (.I0(\ras_timer_r_reg[2]_1 ), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(bm_end_r1_0), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\ras_timer_r_reg[2]_0 )); FDRE #( .INIT(1'b0)) \ras_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ras_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ras_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(1'b0)); LUT6 #( .INIT(64'hFF02FF00FF02FF02)) ras_timer_zero_r_i_1__0 (.I0(rd_wr_r_lcl_reg_0), .I1(Q[2]), .I2(Q[1]), .I3(bm_end_r1_reg_0), .I4(Q[0]), .I5(\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ), .O(ras_timer_zero_r_i_1__0_n_0)); FDRE #( .INIT(1'b0)) ras_timer_zero_r_reg (.C(CLK), .CE(1'b1), .D(ras_timer_zero_r_i_1__0_n_0), .Q(ras_timer_zero_r), .R(1'b0)); LUT2 #( .INIT(4'h8)) \rcd_timer_gt_2.rcd_timer_r[0]_i_1__0 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[1]_0 ), .O(\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \rcd_timer_gt_2.rcd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ), .Q(rcd_active_r), .R(SR)); FDRE #( .INIT(1'b0)) \rd_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_wr_r_lcl_reg), .Q(rd_this_rank_r), .R(1'b0)); LUT4 #( .INIT(16'h8AAA)) req_bank_rdy_r_i_1__0 (.I0(col_wait_r), .I1(rd_wr_r_lcl_reg), .I2(\order_q_r_reg[0] ), .I3(rd_wr_r_lcl_reg_1), .O(req_bank_rdy_ns_1)); FDRE #( .INIT(1'b0)) req_bank_rdy_r_reg (.C(CLK), .CE(1'b1), .D(req_bank_rdy_ns_1), .Q(req_bank_rdy_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1061" *) LUT4 #( .INIT(16'h0004)) \rp_timer.rp_timer_r[0]_i_1 (.I0(\rp_timer.rp_timer_r_reg_n_0_[0] ), .I1(\rp_timer.rp_timer_r_reg_n_0_[1] ), .I2(start_pre), .I3(rstdiv0_sync_r1_reg_rep__20), .O(\rp_timer.rp_timer_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'hE000)) \rp_timer.rp_timer_r[0]_i_2__0 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[1]_1 ), .I2(pre_wait_r), .I3(ras_timer_zero_r), .O(start_pre)); LUT6 #( .INIT(64'hF888F888F8888888)) \rp_timer.rp_timer_r[1]_i_1 (.I0(\rp_timer.rp_timer_r_reg_n_0_[1] ), .I1(\rp_timer.rp_timer_r_reg_n_0_[0] ), .I2(ras_timer_zero_r), .I3(pre_wait_r), .I4(\grant_r_reg[1]_1 ), .I5(auto_pre_r_lcl_reg_0), .O(\rp_timer.rp_timer_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[0]_i_1_n_0 ), .Q(\rp_timer.rp_timer_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[1]_i_1_n_0 ), .Q(\rp_timer.rp_timer_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__0)); (* SOFT_HLUTNM = "soft_lutpair1060" *) LUT4 #( .INIT(16'h0002)) \rtp_timer_r[0]_i_1 (.I0(rtp_timer_r[1]), .I1(rtp_timer_r[0]), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(pass_open_bank_r_lcl_reg), .O(\rtp_timer_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1060" *) LUT5 #( .INIT(32'h000000C2)) \rtp_timer_r[1]_i_1 (.I0(\grant_r_reg[1] [1]), .I1(rtp_timer_r[1]), .I2(rtp_timer_r[0]), .I3(pass_open_bank_r_lcl_reg), .I4(rstdiv0_sync_r1_reg_rep__20), .O(\rtp_timer_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rtp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[0]_i_1_n_0 ), .Q(rtp_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rtp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[1]_i_1_n_0 ), .Q(rtp_timer_r[1]), .R(1'b0)); LUT6 #( .INIT(64'hFFF7080800000000)) \starve_limit_cntr_r[0]_i_1 (.I0(req_bank_rdy_r), .I1(granted_col_r_reg), .I2(\grant_r_reg[1] [1]), .I3(starve_limit_cntr_r[1]), .I4(starve_limit_cntr_r[0]), .I5(col_wait_r), .O(\starve_limit_cntr_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFF08FF0000000000)) \starve_limit_cntr_r[1]_i_1 (.I0(req_bank_rdy_r), .I1(granted_col_r_reg), .I2(\grant_r_reg[1] [1]), .I3(starve_limit_cntr_r[1]), .I4(starve_limit_cntr_r[0]), .I5(col_wait_r), .O(\starve_limit_cntr_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \starve_limit_cntr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[0]_i_1_n_0 ), .Q(starve_limit_cntr_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \starve_limit_cntr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[1]_i_1_n_0 ), .Q(starve_limit_cntr_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(start_wtp_timer0), .Q(wr_this_rank_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_clk_ibuf" *) module ddr3_ifmig_7series_v4_0_clk_ibuf (mmcm_clk, sys_clk_i); output mmcm_clk; input sys_clk_i; (* RTL_KEEP = "true" *) (* syn_keep = "true" *) wire sys_clk_ibufg; assign mmcm_clk = sys_clk_ibufg; assign sys_clk_ibufg = sys_clk_i; endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_col_mach" *) module ddr3_ifmig_7series_v4_0_col_mach (col_rd_wr_r1, col_rd_wr_r2, sent_col_r2, D, bypass__0, Q, mc_read_idle_r_reg, \read_fifo.tail_r_reg[2]_0 , mc_ref_zq_wip_ns, \read_fifo.tail_r_reg[1]_0 , wr_data_en_ns, \read_fifo.fifo_out_data_r_reg[7]_0 , app_rd_data_end_ns, CLK, col_data_buf_addr, ADDRA, DIC, col_rd_wr, mc_cmd, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \rd_buf_indx.rd_buf_indx_r_reg[4] , maint_ref_zq_wip, rstdiv0_sync_r1_reg_rep__22, \not_strict_mode.status_ram.rd_buf_we_r1_reg , SR, \read_fifo.tail_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__0, E); output col_rd_wr_r1; output col_rd_wr_r2; output sent_col_r2; output [3:0]D; output bypass__0; output [7:0]Q; output mc_read_idle_r_reg; output [1:0]\read_fifo.tail_r_reg[2]_0 ; output mc_ref_zq_wip_ns; output \read_fifo.tail_r_reg[1]_0 ; output wr_data_en_ns; output \read_fifo.fifo_out_data_r_reg[7]_0 ; output app_rd_data_end_ns; input CLK; input [4:0]col_data_buf_addr; input [2:0]ADDRA; input [0:0]DIC; input col_rd_wr; input [0:0]mc_cmd; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; input maint_ref_zq_wip; input rstdiv0_sync_r1_reg_rep__22; input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; input [0:0]SR; input \read_fifo.tail_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__0; input [0:0]E; wire [2:0]ADDRA; wire CLK; wire [3:0]D; wire [0:0]DIC; wire [0:0]E; wire [7:0]Q; wire [0:0]SR; wire app_rd_data_end_ns; wire bypass__0; wire [4:0]col_data_buf_addr; wire col_rd_wr; wire col_rd_wr_r1; wire col_rd_wr_r2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire [7:0]fifo_out_data_ns; wire [4:0]head_r; wire maint_ref_zq_wip; wire [0:0]mc_cmd; wire mc_read_idle_r_reg; wire mc_ref_zq_wip_ns; wire mc_ref_zq_wip_r_i_2_n_0; wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [4:0]p_0_in; wire \rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ; wire \rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ; wire [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; wire \read_fifo.fifo_out_data_r_reg[7]_0 ; wire \read_fifo.tail_r[1]_i_1_n_0 ; wire \read_fifo.tail_r[2]_i_1_n_0 ; wire \read_fifo.tail_r[3]_i_1_n_0 ; wire \read_fifo.tail_r[4]_i_1_n_0 ; wire \read_fifo.tail_r_reg[0]_0 ; wire \read_fifo.tail_r_reg[1]_0 ; wire [1:0]\read_fifo.tail_r_reg[2]_0 ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__22; wire sent_col_r2; wire [3:0]tail_ns; wire [4:3]tail_r; wire wr_data_en_ns; wire [1:0]\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ; wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ; LUT2 #( .INIT(4'h2)) \cmd_pipe_plus.wr_data_en_i_1 (.I0(mc_cmd), .I1(col_rd_wr_r1), .O(wr_data_en_ns)); FDRE #( .INIT(1'b0)) \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[0]), .Q(D[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[1]), .Q(D[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[2]), .Q(D[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[3]), .Q(D[3]), .R(1'b0)); LUT6 #( .INIT(64'h9555555555555555)) i___56_i_2 (.I0(tail_r[4]), .I1(\read_fifo.tail_r_reg[2]_0 [0]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\read_fifo.tail_r_reg[1]_0 ), .I4(\read_fifo.tail_r_reg[2]_0 [1]), .I5(tail_r[3]), .O(\read_fifo.fifo_out_data_r_reg[7]_0 )); LUT5 #( .INIT(32'h09000009)) mc_read_idle_r_i_1 (.I0(tail_r[4]), .I1(head_r[4]), .I2(mc_ref_zq_wip_r_i_2_n_0), .I3(head_r[3]), .I4(tail_r[3]), .O(mc_read_idle_r_reg)); LUT6 #( .INIT(64'h0082000000000082)) mc_ref_zq_wip_r_i_1 (.I0(maint_ref_zq_wip), .I1(tail_r[4]), .I2(head_r[4]), .I3(mc_ref_zq_wip_r_i_2_n_0), .I4(head_r[3]), .I5(tail_r[3]), .O(mc_ref_zq_wip_ns)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) mc_ref_zq_wip_r_i_2 (.I0(head_r[1]), .I1(\read_fifo.tail_r_reg[2]_0 [0]), .I2(head_r[2]), .I3(\read_fifo.tail_r_reg[2]_0 [1]), .I4(\read_fifo.tail_r_reg[1]_0 ), .I5(head_r[0]), .O(mc_ref_zq_wip_r_i_2_n_0)); LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data_end_i_1 (.I0(Q[7]), .I1(bypass__0), .I2(\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .O(app_rd_data_end_ns)); FDRE #( .INIT(1'b0)) \offset_pipe_0.col_rd_wr_r1_reg (.C(CLK), .CE(1'b1), .D(col_rd_wr), .Q(col_rd_wr_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \offset_pipe_1.col_rd_wr_r2_reg (.C(CLK), .CE(1'b1), .D(col_rd_wr_r1), .Q(col_rd_wr_r2), .R(1'b0)); LUT6 #( .INIT(64'h2000000000002000)) \rd_buf_indx.rd_buf_indx_r[0]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(Q[6]), .I2(\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ), .I3(\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ), .I4(\rd_buf_indx.rd_buf_indx_r_reg[4] [1]), .I5(Q[2]), .O(bypass__0)); LUT4 #( .INIT(16'h9009)) \rd_buf_indx.rd_buf_indx_r[0]_i_3 (.I0(Q[5]), .I1(\rd_buf_indx.rd_buf_indx_r_reg[4] [4]), .I2(Q[1]), .I3(\rd_buf_indx.rd_buf_indx_r_reg[4] [0]), .O(\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 )); LUT4 #( .INIT(16'h9009)) \rd_buf_indx.rd_buf_indx_r[0]_i_4 (.I0(Q[3]), .I1(\rd_buf_indx.rd_buf_indx_r_reg[4] [2]), .I2(Q[4]), .I3(\rd_buf_indx.rd_buf_indx_r_reg[4] [3]), .O(\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[0] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[1] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[2] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[3] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[4] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[5] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[5]), .Q(Q[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[6]), .Q(Q[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \read_fifo.fifo_out_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[7]), .Q(Q[7]), .R(1'b0)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \read_fifo.fifo_ram[0].RAM32M0 (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRD(head_r), .DIA(col_data_buf_addr[4:3]), .DIB(col_data_buf_addr[2:1]), .DIC({col_data_buf_addr[0],1'b0}), .DID({1'b0,1'b0}), .DOA(fifo_out_data_ns[5:4]), .DOB(fifo_out_data_ns[3:2]), .DOC(fifo_out_data_ns[1:0]), .DOD(\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(1'b1)); LUT6 #( .INIT(64'h000000007FFF8000)) \read_fifo.fifo_ram[0].RAM32M0_i_6 (.I0(\read_fifo.tail_r_reg[2]_0 [0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\read_fifo.tail_r_reg[1]_0 ), .I3(\read_fifo.tail_r_reg[2]_0 [1]), .I4(tail_r[3]), .I5(rstdiv0_sync_r1_reg_rep__22), .O(tail_ns[3])); LUT3 #( .INIT(8'h06)) \read_fifo.fifo_ram[0].RAM32M0_i_7 (.I0(\read_fifo.tail_r_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(rstdiv0_sync_r1_reg_rep__22), .O(tail_ns[0])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \read_fifo.fifo_ram[1].RAM32M0 (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRD(head_r), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b1,DIC}), .DID({1'b0,1'b0}), .DOA(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]), .DOC(fifo_out_data_ns[7:6]), .DOD(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(1'b1)); LUT1 #( .INIT(2'h1)) \read_fifo.head_r[0]_i_1 (.I0(head_r[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair1068" *) LUT2 #( .INIT(4'h6)) \read_fifo.head_r[1]_i_1 (.I0(head_r[0]), .I1(head_r[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair1068" *) LUT3 #( .INIT(8'h6A)) \read_fifo.head_r[2]_i_1 (.I0(head_r[2]), .I1(head_r[1]), .I2(head_r[0]), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair1066" *) LUT4 #( .INIT(16'h6AAA)) \read_fifo.head_r[3]_i_1 (.I0(head_r[3]), .I1(head_r[0]), .I2(head_r[1]), .I3(head_r[2]), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair1066" *) LUT5 #( .INIT(32'h6AAAAAAA)) \read_fifo.head_r[4]_i_1 (.I0(head_r[4]), .I1(head_r[2]), .I2(head_r[1]), .I3(head_r[0]), .I4(head_r[3]), .O(p_0_in[4])); FDRE #( .INIT(1'b0)) \read_fifo.head_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in[0]), .Q(head_r[0]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \read_fifo.head_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in[1]), .Q(head_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \read_fifo.head_r_reg[2] (.C(CLK), .CE(E), .D(p_0_in[2]), .Q(head_r[2]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \read_fifo.head_r_reg[3] (.C(CLK), .CE(E), .D(p_0_in[3]), .Q(head_r[3]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \read_fifo.head_r_reg[4] (.C(CLK), .CE(E), .D(p_0_in[4]), .Q(head_r[4]), .R(rstdiv0_sync_r1_reg_rep__0)); LUT3 #( .INIT(8'h78)) \read_fifo.tail_r[1]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\read_fifo.tail_r_reg[1]_0 ), .I2(\read_fifo.tail_r_reg[2]_0 [0]), .O(\read_fifo.tail_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1067" *) LUT4 #( .INIT(16'h7F80)) \read_fifo.tail_r[2]_i_1 (.I0(\read_fifo.tail_r_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\read_fifo.tail_r_reg[2]_0 [0]), .I3(\read_fifo.tail_r_reg[2]_0 [1]), .O(\read_fifo.tail_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1067" *) LUT5 #( .INIT(32'h6AAAAAAA)) \read_fifo.tail_r[3]_i_1 (.I0(tail_r[3]), .I1(\read_fifo.tail_r_reg[2]_0 [1]), .I2(\read_fifo.tail_r_reg[1]_0 ), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\read_fifo.tail_r_reg[2]_0 [0]), .O(\read_fifo.tail_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \read_fifo.tail_r[4]_i_1 (.I0(tail_r[3]), .I1(\read_fifo.tail_r_reg[2]_0 [1]), .I2(\read_fifo.tail_r_reg[1]_0 ), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\read_fifo.tail_r_reg[2]_0 [0]), .I5(tail_r[4]), .O(\read_fifo.tail_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \read_fifo.tail_r_reg[0] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r_reg[0]_0 ), .Q(\read_fifo.tail_r_reg[1]_0 ), .R(SR)); FDRE #( .INIT(1'b0)) \read_fifo.tail_r_reg[1] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[1]_i_1_n_0 ), .Q(\read_fifo.tail_r_reg[2]_0 [0]), .R(SR)); FDRE #( .INIT(1'b0)) \read_fifo.tail_r_reg[2] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[2]_i_1_n_0 ), .Q(\read_fifo.tail_r_reg[2]_0 [1]), .R(SR)); FDRE #( .INIT(1'b0)) \read_fifo.tail_r_reg[3] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[3]_i_1_n_0 ), .Q(tail_r[3]), .R(SR)); FDRE #( .INIT(1'b0)) \read_fifo.tail_r_reg[4] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[4]_i_1_n_0 ), .Q(tail_r[4]), .R(SR)); FDRE #( .INIT(1'b0)) sent_col_r2_reg (.C(CLK), .CE(1'b1), .D(mc_cmd), .Q(sent_col_r2), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io (mem_dqs_out, mem_dqs_ts, D0, D1, D2, D3, D4, D5, D6, D7, mem_dq_out, mem_dq_ts, idelay_ld_rst, rst_r4, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0, A_rst_primitives, A_rst_primitives_reg, CLKB0, iserdes_clkdiv, of_dqbus, E, \fine_delay_mod_reg[23] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D0; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst; output rst_r4; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0; input iserdes_clkdiv; input [35:0]of_dqbus; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0; wire [0:0]CTSBUS; wire [3:0]D0; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire [0:0]E; wire LD0; wire data_in_dly_0; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire [7:0]\fine_delay_mod_reg[23] ; wire [23:2]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_i_1_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r3_reg_srl3_n_0; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* __SRVAL = "TRUE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[11] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [3]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[14] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [4]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[17] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [5]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[20] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [6]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[23] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [7]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[2] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [0]), .Q(fine_delay_r[2]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[5] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [1]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[8] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [2]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1 (.I0(idelay_ld_rst), .I1(rst_r4), .O(idelay_ld_rst_i_1_n_0)); FDSE #( .INIT(1'b1)) idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1_n_0), .Q(idelay_ld_rst), .S(A_rst_primitives)); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_0), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[2],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[0].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_0), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D0[3]), .Q2(D0[2]), .Q3(D0[1]), .Q4(D0[0]), .Q5(\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[0].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 " *) SRL16E #( .INIT(16'h0000)) rst_r3_reg_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(A_rst_primitives), .Q(rst_r3_reg_srl3_n_0)); FDRE #( .INIT(1'b0)) rst_r4_reg (.C(CLK), .CE(1'b1), .D(rst_r3_reg_srl3_n_0), .Q(rst_r4), .R(1'b0)); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized0 (mem_dqs_out, mem_dqs_ts, D1, D2, D3, D4, D5, D6, D7, D8, mem_dq_out, mem_dq_ts, idelay_ld_rst_0, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0_3, A_rst_primitives, A_rst_primitives_reg, CLKB0_7, iserdes_clkdiv, of_dqbus, rst_r4, \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[0] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_0; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0_3; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0_7; input iserdes_clkdiv; input [35:0]of_dqbus; input rst_r4; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; input [7:0]\calib_sel_reg[0] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0_7; wire [0:0]CTSBUS; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire LD0_3; wire [7:0]\calib_sel_reg[0] ; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire data_in_dly_8; wire [26:5]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; wire idelay_inc; wire idelay_ld_rst_0; wire idelay_ld_rst_i_1__0_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* __SRVAL = "TRUE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[11] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [2]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[14] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [3]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[17] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [4]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[20] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [5]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[23] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [6]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[26] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [7]), .Q(fine_delay_r[26]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[5] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [0]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[8] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [1]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1__0 (.I0(idelay_ld_rst_0), .I1(rst_r4), .O(idelay_ld_rst_i_1__0_n_0)); FDSE #( .INIT(1'b1)) idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1__0_n_0), .Q(idelay_ld_rst_0), .S(A_rst_primitives)); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_8), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[26],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[8].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_8), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D8[3]), .Q2(D8[2]), .Q3(D8[1]), .Q4(D8[0]), .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[8].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized1 (mem_dqs_out, mem_dqs_ts, D1, D2, D3, D4, D5, D6, D7, D8, mem_dq_out, mem_dq_ts, idelay_ld_rst_1, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0_4, A_rst_primitives, A_rst_primitives_reg, CLKB0_8, iserdes_clkdiv, of_dqbus, rst_r4, \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_1; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0_4; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0_8; input iserdes_clkdiv; input [35:0]of_dqbus; input rst_r4; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; input [7:0]\calib_sel_reg[1] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0_8; wire [0:0]CTSBUS; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire LD0_4; wire [7:0]\calib_sel_reg[1] ; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire data_in_dly_8; wire [26:5]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; wire idelay_inc; wire idelay_ld_rst_1; wire idelay_ld_rst_i_1__1_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* __SRVAL = "TRUE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[11] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [2]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[14] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [3]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[17] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [4]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[20] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [5]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[23] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [6]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[26] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [7]), .Q(fine_delay_r[26]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[5] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [0]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[8] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [1]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1__1 (.I0(idelay_ld_rst_1), .I1(rst_r4), .O(idelay_ld_rst_i_1__1_n_0)); FDSE #( .INIT(1'b1)) idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1__1_n_0), .Q(idelay_ld_rst_1), .S(A_rst_primitives)); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_8), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[26],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[8].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_8), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D8[3]), .Q2(D8[2]), .Q3(D8[1]), .Q4(D8[0]), .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[8].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized2 (mem_dqs_out, mem_dqs_ts, D1, D2, D3, D4, D5, D6, D7, D8, mem_dq_out, mem_dq_ts, idelay_ld_rst_2, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0_5, A_rst_primitives, A_rst_primitives_reg, CLKB0_9, iserdes_clkdiv, of_dqbus, rst_r4, \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[0] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_2; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0_5; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0_9; input iserdes_clkdiv; input [35:0]of_dqbus; input rst_r4; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; input [7:0]\calib_sel_reg[0] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0_9; wire [0:0]CTSBUS; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire LD0_5; wire [7:0]\calib_sel_reg[0] ; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire data_in_dly_8; wire [26:5]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; wire idelay_inc; wire idelay_ld_rst_2; wire idelay_ld_rst_i_1__2_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* __SRVAL = "TRUE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[11] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [2]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[14] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [3]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[17] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [4]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[20] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [5]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[23] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [6]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[26] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [7]), .Q(fine_delay_r[26]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[5] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [0]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE #( .INIT(1'b0)) \fine_delay_r_reg[8] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [1]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1__2 (.I0(idelay_ld_rst_2), .I1(rst_r4), .O(idelay_ld_rst_i_1__2_n_0)); FDSE #( .INIT(1'b1)) idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1__2_n_0), .Q(idelay_ld_rst_2), .S(A_rst_primitives)); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_8), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[26],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* box_type = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[8].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_8), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D8[3]), .Q2(D8[2]), .Q3(D8[1]), .Q4(D8[0]), .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[8].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized3 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, oserdes_rst); output [1:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [7:0]oserdes_dq; input oserdes_rst; wire [1:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [7:0]oserdes_dq; wire oserdes_rst; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[0].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[1].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized4 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, oserdes_rst); output [2:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [11:0]oserdes_dq; input oserdes_rst; wire [2:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [11:0]oserdes_dq; wire oserdes_rst; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[10].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[11].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[8]), .D2(oserdes_dq[9]), .D3(oserdes_dq[10]), .D4(oserdes_dq[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[4].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized5 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, po_oserdes_rst); output [9:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [39:0]oserdes_dq; input po_oserdes_rst; wire [9:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [39:0]oserdes_dq; wire po_oserdes_rst; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[10].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[32]), .D2(oserdes_dq[33]), .D3(oserdes_dq[34]), .D4(oserdes_dq[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[11].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[36]), .D2(oserdes_dq[37]), .D3(oserdes_dq[38]), .D4(oserdes_dq[39]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[9]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[2].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[3].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[4].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[8]), .D2(oserdes_dq[9]), .D3(oserdes_dq[10]), .D4(oserdes_dq[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[5].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[12]), .D2(oserdes_dq[13]), .D3(oserdes_dq[14]), .D4(oserdes_dq[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[6].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[16]), .D2(oserdes_dq[17]), .D3(oserdes_dq[18]), .D4(oserdes_dq[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[7].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[20]), .D2(oserdes_dq[21]), .D3(oserdes_dq[22]), .D4(oserdes_dq[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[8].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[24]), .D2(oserdes_dq[25]), .D3(oserdes_dq[26]), .D4(oserdes_dq[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[9].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[28]), .D2(oserdes_dq[29]), .D3(oserdes_dq[30]), .D4(oserdes_dq[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized6 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, po_oserdes_rst); output [8:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [35:0]oserdes_dq; input po_oserdes_rst; wire [8:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [35:0]oserdes_dq; wire po_oserdes_rst; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[1].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[2].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[3].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[8]), .D2(oserdes_dq[9]), .D3(oserdes_dq[10]), .D4(oserdes_dq[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[4].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[12]), .D2(oserdes_dq[13]), .D3(oserdes_dq[14]), .D4(oserdes_dq[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[5].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[16]), .D2(oserdes_dq[17]), .D3(oserdes_dq[18]), .D4(oserdes_dq[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[6].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[20]), .D2(oserdes_dq[21]), .D3(oserdes_dq[22]), .D4(oserdes_dq[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[7].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[24]), .D2(oserdes_dq[25]), .D3(oserdes_dq[26]), .D4(oserdes_dq[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[8].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[28]), .D2(oserdes_dq[29]), .D3(oserdes_dq[30]), .D4(oserdes_dq[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[9].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[32]), .D2(oserdes_dq[33]), .D3(oserdes_dq[34]), .D4(oserdes_dq[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane (\pi_dqs_found_lanes_r1_reg[0] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , pi_phase_locked_all_r1_reg, COUNTERREADVAL, \po_counter_read_val_reg[8] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, if_empty_r, \wr_ptr_reg[1] , idelay_ld_rst, rst_r4, \not_strict_mode.app_rd_data_reg[252] , \my_empty_reg[1] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[24] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7] , A_byte_rd_en, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0, CLKB0, phy_if_reset, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \byte_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \byte_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 , \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , A, phy_dout, E, \fine_delay_mod_reg[23] , D_byte_rd_en, B_byte_rd_en, if_empty_r_0, my_empty, \po_stg2_wrcal_cnt_reg[1] ); output [0:0]\pi_dqs_found_lanes_r1_reg[0] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output pi_phase_locked_all_r1_reg; output [5:0]COUNTERREADVAL; output [8:0]\po_counter_read_val_reg[8] ; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output [0:0]if_empty_r; output [0:0]\wr_ptr_reg[1] ; output idelay_ld_rst; output rst_r4; output \not_strict_mode.app_rd_data_reg[252] ; output \my_empty_reg[1] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[24] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7] ; output A_byte_rd_en; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[287] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input \byte_r_reg[0] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input \byte_r_reg[1] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]A; input [71:0]phy_dout; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; input D_byte_rd_en; input B_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]my_empty; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]A; wire A_byte_rd_en; wire A_rst_primitives; wire B_byte_rd_en; wire CLK; wire CLKB0; wire [5:0]COUNTERLOADVAL; wire [5:0]COUNTERREADVAL; wire D_byte_rd_en; wire [0:0]E; wire LD0; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire \calib_sel_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire [63:0]\data_bytes_r_reg[63] ; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ; wire [7:0]\fine_delay_mod_reg[23] ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire [3:0]if_d0; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_wrdata_en; wire [0:0]my_empty; wire \my_empty_reg[1] ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire p_0_out; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_7 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_reset; wire [0:0]\pi_dqs_found_lanes_r1_reg[0] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [79:0]rd_data; wire [65:1]rd_data_r; wire [1:0]\rd_mux_sel_r_reg[1] ; wire \read_fifo.fifo_out_data_r_reg[6] ; wire rst_r4; wire sync_pulse; wire [0:0]\wr_ptr_reg[1] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[287] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0(CLKB0), .CTSBUS(oserdes_dqs_ts[0]), .D0(if_d0), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .E(E), .LD0(LD0), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23] ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus({of_dqbus[39:36],of_dqbus[31:0]}), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_data[0]), .Q(\not_strict_mode.app_rd_data_reg[31]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (.C(CLK), .CE(1'b1), .D(rd_data[1]), .Q(rd_data_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (.C(CLK), .CE(1'b1), .D(rd_data[2]), .Q(rd_data_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (.C(CLK), .CE(1'b1), .D(rd_data[3]), .Q(rd_data_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (.C(CLK), .CE(1'b1), .D(rd_data[4]), .Q(rd_data_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (.C(CLK), .CE(1'b1), .D(rd_data[5]), .Q(rd_data_r[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(rd_data_r[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_6 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A(A), .A_byte_rd_en(A_byte_rd_en), .B_byte_rd_en(B_byte_rd_en), .CLK(CLK), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r,\not_strict_mode.app_rd_data_reg[31]_0 }), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .if_empty_r_0(if_empty_r_0), .ififo_rst(ififo_rst), .my_empty(my_empty), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[252]_0 (\not_strict_mode.app_rd_data_reg[252]_0 ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255]_0 ), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31]_1 ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .p_0_out(p_0_out), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] )); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0(if_d0), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8({1'b0,1'b0,1'b0,1'b0}), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized2 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[287] (\write_buffer.wr_buf_out_data_reg[287] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0(\write_buffer.wr_buf_out_data_reg[255] ), .D1(\write_buffer.wr_buf_out_data_reg[254] ), .D2(\write_buffer.wr_buf_out_data_reg[253] ), .D3(\write_buffer.wr_buf_out_data_reg[252] ), .D4(\write_buffer.wr_buf_out_data_reg[251] ), .D5(\write_buffer.wr_buf_out_data_reg[250] ), .D6(\write_buffer.wr_buf_out_data_reg[249] ), .D7(\write_buffer.wr_buf_out_data_reg[248] ), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* box_type = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_AUTO_RECAL(1'b1), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(COUNTERLOADVAL), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(COUNTERREADVAL), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[0] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(pi_phase_locked_all_r1_reg), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(\phaser_in_gen.phaser_in_n_7 ), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(\po_counter_read_val_reg[8] ), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized0 (\pi_dqs_found_lanes_r1_reg[1] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , B_rclk, COUNTERREADVAL, \po_counter_read_val_reg[8] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, if_empty_r, \rd_ptr_timing_reg[1] , idelay_ld_rst_0, \not_strict_mode.app_rd_data_reg[244] , \my_empty_reg[1] , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , phy_rddata_en, mux_rd_valid_r_reg, \read_fifo.tail_r_reg[0] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[247]_0 , pi_phase_locked_all_r1_reg, phy_if_empty_r_reg, \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7] , B_byte_rd_en, Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0_3, CLKB0_7, phy_if_reset, mux_wrdata_en, rst_r4, \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[286] , if_empty_r_0, my_empty, \my_empty_reg[4] , prbs_rdlvl_start_reg, out, tail_r, \read_fifo.fifo_out_data_r_reg[6]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , A_rst_primitives_reg, A_rst_primitives_reg_0, A_rst_primitives_reg_1, phy_dout, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[0]_0 , D_byte_rd_en, A_byte_rd_en); output [0:0]\pi_dqs_found_lanes_r1_reg[1] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output B_rclk; output [5:0]COUNTERREADVAL; output [8:0]\po_counter_read_val_reg[8] ; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output [0:0]if_empty_r; output [0:0]\rd_ptr_timing_reg[1] ; output idelay_ld_rst_0; output \not_strict_mode.app_rd_data_reg[244] ; output \my_empty_reg[1] ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output phy_rddata_en; output mux_rd_valid_r_reg; output \read_fifo.tail_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[247]_0 ; output pi_phase_locked_all_r1_reg; output phy_if_empty_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7] ; output B_byte_rd_en; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0_3; input CLKB0_7; input phy_if_reset; input mux_wrdata_en; input rst_r4; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[286] ; input [0:0]if_empty_r_0; input [1:0]my_empty; input \my_empty_reg[4] ; input prbs_rdlvl_start_reg; input out; input [0:0]tail_r; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input A_rst_primitives_reg; input A_rst_primitives_reg_0; input A_rst_primitives_reg_1; input [71:0]phy_dout; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; input [7:0]\calib_sel_reg[0]_0 ; input D_byte_rd_en; input A_byte_rd_en; wire A_byte_rd_en; wire A_rst_primitives; wire A_rst_primitives_reg; wire A_rst_primitives_reg_0; wire A_rst_primitives_reg_1; wire B_byte_rd_en; wire B_rclk; wire CLK; wire CLKB0_7; wire [5:0]COUNTERREADVAL; wire D_byte_rd_en; wire LD0_3; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \calib_sel_reg[0] ; wire [7:0]\calib_sel_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; wire idelay_inc; wire idelay_ld_rst_0; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire [3:0]if_d8; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_rd_valid_r_reg; wire mux_wrdata_en; wire [1:0]my_empty; wire \my_empty_reg[1] ; wire \my_empty_reg[4] ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire [63:0]\not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[247]_0 ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_6 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_rddata_en; wire [0:0]\pi_dqs_found_lanes_r1_reg[1] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rd_buf_we; wire [79:0]rd_data; wire [71:6]rd_data_r; wire [0:0]\rd_ptr_timing_reg[1] ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire rst_r4; wire sync_pulse; wire [0:0]tail_r; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[286] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized0 ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0_7(CLKB0_7), .CTSBUS(oserdes_dqs_ts[0]), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .D8(if_d8), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .LD0_3(LD0_3), .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .idelay_inc(idelay_inc), .idelay_ld_rst_0(idelay_ld_rst_0), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus(of_dqbus[39:4]), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (.C(CLK), .CE(1'b1), .D(rd_data[66]), .Q(rd_data_r[66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (.C(CLK), .CE(1'b1), .D(rd_data[67]), .Q(rd_data_r[67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (.C(CLK), .CE(1'b1), .D(rd_data[68]), .Q(rd_data_r[68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (.C(CLK), .CE(1'b1), .D(rd_data[69]), .Q(rd_data_r[69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (.C(CLK), .CE(1'b1), .D(rd_data[70]), .Q(rd_data_r[70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (.C(CLK), .CE(1'b1), .D(rd_data[71]), .Q(rd_data_r[71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(\not_strict_mode.app_rd_data_reg[23]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_5 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A_byte_rd_en(A_byte_rd_en), .B_byte_rd_en(B_byte_rd_en), .CLK(CLK), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r[71:9],\not_strict_mode.app_rd_data_reg[23]_0 ,rd_data_r[7:6]}), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r), .if_empty_r_0(if_empty_r_0), .ififo_rst(ififo_rst), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .my_empty(my_empty), .\my_empty_reg[4]_0 (\my_empty_reg[4] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[22] (\not_strict_mode.app_rd_data_reg[22] ), .\not_strict_mode.app_rd_data_reg[23] (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23]_1 ), .\not_strict_mode.app_rd_data_reg[240] (\not_strict_mode.app_rd_data_reg[240] ), .\not_strict_mode.app_rd_data_reg[241] (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[244]_0 (\not_strict_mode.app_rd_data_reg[244]_0 ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247]_0 ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .out(out), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_rddata_en(phy_rddata_en), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .tail_r(tail_r)); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0({1'b0,1'b0,1'b0,1'b0}), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8(if_d8), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized3 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[286] (\write_buffer.wr_buf_out_data_reg[286] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D1(\write_buffer.wr_buf_out_data_reg[247] ), .D2(\write_buffer.wr_buf_out_data_reg[246] ), .D3(\write_buffer.wr_buf_out_data_reg[245] ), .D4(\write_buffer.wr_buf_out_data_reg[244] ), .D5(\write_buffer.wr_buf_out_data_reg[243] ), .D6(\write_buffer.wr_buf_out_data_reg[242] ), .D7(\write_buffer.wr_buf_out_data_reg[241] ), .D8(\write_buffer.wr_buf_out_data_reg[240] ), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* box_type = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_AUTO_RECAL(1'b1), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(COUNTERREADVAL), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[1] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(B_rclk), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(\po_counter_read_val_reg[8] ), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT4 #( .INIT(16'h8000)) pi_phase_locked_all_inferred_i_1 (.I0(\phaser_in_gen.phaser_in_n_6 ), .I1(A_rst_primitives_reg), .I2(A_rst_primitives_reg_0), .I3(A_rst_primitives_reg_1), .O(pi_phase_locked_all_r1_reg)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized1 (\pi_dqs_found_lanes_r1_reg[2] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , pi_phase_locked_all_r1_reg, COUNTERREADVAL, \po_counter_read_val_reg[8] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, if_empty_r, \rd_ptr_timing_reg[1] , idelay_ld_rst_1, \not_strict_mode.app_rd_data_reg[236] , \my_empty_reg[1] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[239]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7] , C_byte_rd_en, Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[1] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0_4, CLKB0_8, phy_if_reset, mux_wrdata_en, rst_r4, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[285] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , phy_dout, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[1]_0 , D_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4] ); output [0:0]\pi_dqs_found_lanes_r1_reg[2] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output pi_phase_locked_all_r1_reg; output [5:0]COUNTERREADVAL; output [8:0]\po_counter_read_val_reg[8] ; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output [0:0]if_empty_r; output [1:0]\rd_ptr_timing_reg[1] ; output idelay_ld_rst_1; output \not_strict_mode.app_rd_data_reg[236] ; output \my_empty_reg[1] ; output [63:0]\not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[239]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7] ; output C_byte_rd_en; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[1] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0_4; input CLKB0_8; input phy_if_reset; input mux_wrdata_en; input rst_r4; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[285] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [71:0]phy_dout; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; input [7:0]\calib_sel_reg[1]_0 ; input D_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4] ; wire A_byte_rd_en; wire A_rst_primitives; wire CLK; wire CLKB0_8; wire [5:0]COUNTERREADVAL; wire C_byte_rd_en; wire D_byte_rd_en; wire LD0_4; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \calib_sel_reg[1] ; wire [7:0]\calib_sel_reg[1]_0 ; wire [5:0]\calib_zero_inputs_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; wire idelay_inc; wire idelay_ld_rst_1; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire [3:0]if_d8; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_wrdata_en; wire \my_empty_reg[1] ; wire [0:0]\my_empty_reg[4] ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire [63:0]\not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[239]_0 ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_7 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_reset; wire [0:0]\pi_dqs_found_lanes_r1_reg[2] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire [79:0]rd_data; wire [71:6]rd_data_r; wire [1:0]\rd_ptr_timing_reg[1] ; wire \read_fifo.fifo_out_data_r_reg[6] ; wire rst_r4; wire sync_pulse; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[285] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized1 ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0_8(CLKB0_8), .CTSBUS(oserdes_dqs_ts[0]), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .D8(if_d8), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .LD0_4(LD0_4), .\calib_sel_reg[1] (\calib_sel_reg[1]_0 ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .idelay_inc(idelay_inc), .idelay_ld_rst_1(idelay_ld_rst_1), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus(of_dqbus[39:4]), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (.C(CLK), .CE(1'b1), .D(rd_data[66]), .Q(rd_data_r[66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (.C(CLK), .CE(1'b1), .D(rd_data[67]), .Q(rd_data_r[67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (.C(CLK), .CE(1'b1), .D(rd_data[68]), .Q(rd_data_r[68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (.C(CLK), .CE(1'b1), .D(rd_data[69]), .Q(rd_data_r[69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (.C(CLK), .CE(1'b1), .D(rd_data[70]), .Q(rd_data_r[70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (.C(CLK), .CE(1'b1), .D(rd_data[71]), .Q(rd_data_r[71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(\not_strict_mode.app_rd_data_reg[15]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_4 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A_byte_rd_en(A_byte_rd_en), .CLK(CLK), .C_byte_rd_en(C_byte_rd_en), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r[71:9],\not_strict_mode.app_rd_data_reg[15]_0 ,rd_data_r[7:6]}), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r), .if_empty_r_0(if_empty_r_0), .ififo_rst(ififo_rst), .\my_empty_reg[4]_0 (\my_empty_reg[4] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15]_1 ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ), .\not_strict_mode.app_rd_data_reg[233] (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[234] (\not_strict_mode.app_rd_data_reg[234] ), .\not_strict_mode.app_rd_data_reg[235] (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[236] (\not_strict_mode.app_rd_data_reg[236] ), .\not_strict_mode.app_rd_data_reg[236]_0 (\not_strict_mode.app_rd_data_reg[236]_0 ), .\not_strict_mode.app_rd_data_reg[237] (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[238] (\not_strict_mode.app_rd_data_reg[238] ), .\not_strict_mode.app_rd_data_reg[239] (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239]_0 ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[72] (\not_strict_mode.app_rd_data_reg[72] ), .\not_strict_mode.app_rd_data_reg[73] (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[74] (\not_strict_mode.app_rd_data_reg[74] ), .\not_strict_mode.app_rd_data_reg[75] (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[76] (\not_strict_mode.app_rd_data_reg[76] ), .\not_strict_mode.app_rd_data_reg[77] (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[78] (\not_strict_mode.app_rd_data_reg[78] ), .\not_strict_mode.app_rd_data_reg[79] (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .phy_if_empty_r_reg(\rd_ptr_timing_reg[1] [0]), .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] [1]), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] )); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0({1'b0,1'b0,1'b0,1'b0}), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8(if_d8), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized4 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[285] (\write_buffer.wr_buf_out_data_reg[285] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D1(\write_buffer.wr_buf_out_data_reg[239] ), .D2(\write_buffer.wr_buf_out_data_reg[238] ), .D3(\write_buffer.wr_buf_out_data_reg[237] ), .D4(\write_buffer.wr_buf_out_data_reg[236] ), .D5(\write_buffer.wr_buf_out_data_reg[235] ), .D6(\write_buffer.wr_buf_out_data_reg[234] ), .D7(\write_buffer.wr_buf_out_data_reg[233] ), .D8(\write_buffer.wr_buf_out_data_reg[232] ), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* box_type = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_AUTO_RECAL(1'b1), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ), .COUNTERREADEN(\calib_sel_reg[1] ), .COUNTERREADVAL(COUNTERREADVAL), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[2] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(pi_phase_locked_all_r1_reg), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(\phaser_in_gen.phaser_in_n_7 ), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[1] ), .COUNTERREADVAL(\po_counter_read_val_reg[8] ), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized2 (\pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , pi_phase_locked_all_r1_reg, mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, idelay_ld_rst_2, \not_strict_mode.app_rd_data_reg[228] , \my_empty_reg[1] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[0] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[231]_0 , mux_rd_valid_r_reg, \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7] , D_byte_rd_en, D, \po_counter_read_val_reg[8] , Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0_5, CLKB0_9, phy_if_reset, mux_wrdata_en, rst_r4, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[284] , \read_fifo.fifo_out_data_r_reg[6] , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \my_empty_reg[4] , if_empty_r, phy_dout, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[0]_0 , C_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4]_0 , COUNTERREADVAL, \calib_sel_reg[1] , A_rst_primitives_reg, A_rst_primitives_reg_0, A_rst_primitives_reg_1, A_rst_primitives_reg_2, A_rst_primitives_reg_3); output [0:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output pi_phase_locked_all_r1_reg; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_2; output \not_strict_mode.app_rd_data_reg[228] ; output \my_empty_reg[1] ; output [63:0]\not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[0] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[231]_0 ; output mux_rd_valid_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7] ; output D_byte_rd_en; output [5:0]D; output [8:0]\po_counter_read_val_reg[8] ; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0_5; input CLKB0_9; input phy_if_reset; input mux_wrdata_en; input rst_r4; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[284] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [0:0]\my_empty_reg[4] ; input [0:0]if_empty_r; input [71:0]phy_dout; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; input [7:0]\calib_sel_reg[0]_0 ; input C_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4]_0 ; input [5:0]COUNTERREADVAL; input [1:0]\calib_sel_reg[1] ; input [5:0]A_rst_primitives_reg; input [5:0]A_rst_primitives_reg_0; input [8:0]A_rst_primitives_reg_1; input [8:0]A_rst_primitives_reg_2; input [8:0]A_rst_primitives_reg_3; wire A_byte_rd_en; wire A_rst_primitives; wire [5:0]A_rst_primitives_reg; wire [5:0]A_rst_primitives_reg_0; wire [8:0]A_rst_primitives_reg_1; wire [8:0]A_rst_primitives_reg_2; wire [8:0]A_rst_primitives_reg_3; wire CLK; wire CLKB0_9; wire [5:0]COUNTERREADVAL; wire C_byte_rd_en; wire [5:0]D; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_byte_rd_en; wire [5:0]D_pi_counter_read_val; wire [8:0]D_po_counter_read_val; wire LD0_5; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \calib_sel_reg[0] ; wire [7:0]\calib_sel_reg[0]_0 ; wire [1:0]\calib_sel_reg[1] ; wire [5:0]\calib_zero_inputs_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; wire idelay_inc; wire idelay_ld_rst_2; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire [3:0]if_d8; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire [3:3]if_empty_r_1; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_rd_valid_r_reg; wire mux_wrdata_en; wire \my_empty_reg[1] ; wire [0:0]\my_empty_reg[4] ; wire [0:0]\my_empty_reg[4]_0 ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire [63:0]\not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[231]_0 ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_7 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_reset; wire [0:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire [79:0]rd_data; wire [71:6]rd_data_r; wire \read_fifo.fifo_out_data_r_reg[6] ; wire rst_r4; wire sync_pulse; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[284] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized2 ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0_9(CLKB0_9), .CTSBUS(oserdes_dqs_ts[0]), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .D8(if_d8), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .LD0_5(LD0_5), .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .idelay_inc(idelay_inc), .idelay_ld_rst_2(idelay_ld_rst_2), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus(of_dqbus[39:4]), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r_1), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (.C(CLK), .CE(1'b1), .D(rd_data[66]), .Q(rd_data_r[66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (.C(CLK), .CE(1'b1), .D(rd_data[67]), .Q(rd_data_r[67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (.C(CLK), .CE(1'b1), .D(rd_data[68]), .Q(rd_data_r[68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (.C(CLK), .CE(1'b1), .D(rd_data[69]), .Q(rd_data_r[69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (.C(CLK), .CE(1'b1), .D(rd_data[70]), .Q(rd_data_r[70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (.C(CLK), .CE(1'b1), .D(rd_data[71]), .Q(rd_data_r[71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(\not_strict_mode.app_rd_data_reg[7]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_ifmig_7series_v4_0_ddr_if_post_fifo \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A_byte_rd_en(A_byte_rd_en), .CLK(CLK), .C_byte_rd_en(C_byte_rd_en), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r[71:9],\not_strict_mode.app_rd_data_reg[7]_0 ,rd_data_r[7:6]}), .if_empty_r(if_empty_r), .if_empty_r_0(if_empty_r_0), .if_empty_r_1(if_empty_r_1), .ififo_rst(ififo_rst), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .\my_empty_reg[4]_0 (\my_empty_reg[4] ), .\my_empty_reg[4]_1 (\my_empty_reg[4]_0 ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), .\not_strict_mode.app_rd_data_reg[227] (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[228] (\not_strict_mode.app_rd_data_reg[228] ), .\not_strict_mode.app_rd_data_reg[228]_0 (\not_strict_mode.app_rd_data_reg[228]_0 ), .\not_strict_mode.app_rd_data_reg[229] (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[230] (\not_strict_mode.app_rd_data_reg[230] ), .\not_strict_mode.app_rd_data_reg[231] (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231]_0 ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), .\not_strict_mode.app_rd_data_reg[70] (\not_strict_mode.app_rd_data_reg[70] ), .\not_strict_mode.app_rd_data_reg[71] (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[7] (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7]_1 ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] )); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0({1'b0,1'b0,1'b0,1'b0}), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8(if_d8), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized5 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[284] (\write_buffer.wr_buf_out_data_reg[284] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D1(\write_buffer.wr_buf_out_data_reg[231] ), .D2(\write_buffer.wr_buf_out_data_reg[230] ), .D3(\write_buffer.wr_buf_out_data_reg[229] ), .D4(\write_buffer.wr_buf_out_data_reg[228] ), .D5(\write_buffer.wr_buf_out_data_reg[227] ), .D6(\write_buffer.wr_buf_out_data_reg[226] ), .D7(\write_buffer.wr_buf_out_data_reg[225] ), .D8(\write_buffer.wr_buf_out_data_reg[224] ), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* box_type = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_AUTO_RECAL(1'b1), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(D_pi_counter_read_val), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[3] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(pi_phase_locked_all_r1_reg), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(\phaser_in_gen.phaser_in_n_7 ), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(D_po_counter_read_val), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[0]_i_1 (.I0(D_pi_counter_read_val[0]), .I1(COUNTERREADVAL[0]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[0]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[0]), .O(D[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[1]_i_1 (.I0(D_pi_counter_read_val[1]), .I1(COUNTERREADVAL[1]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[1]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[1]), .O(D[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[2]_i_1 (.I0(D_pi_counter_read_val[2]), .I1(COUNTERREADVAL[2]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[2]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[2]), .O(D[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[3]_i_1 (.I0(D_pi_counter_read_val[3]), .I1(COUNTERREADVAL[3]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[3]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[3]), .O(D[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[4]_i_1 (.I0(D_pi_counter_read_val[4]), .I1(COUNTERREADVAL[4]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[4]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[4]), .O(D[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[5]_i_1 (.I0(D_pi_counter_read_val[5]), .I1(COUNTERREADVAL[5]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[5]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[5]), .O(D[5])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[0]_i_1__0 (.I0(D_po_counter_read_val[0]), .I1(A_rst_primitives_reg_1[0]), .I2(A_rst_primitives_reg_2[0]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[0]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [0])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[1]_i_1__0 (.I0(D_po_counter_read_val[1]), .I1(A_rst_primitives_reg_1[1]), .I2(A_rst_primitives_reg_2[1]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[1]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [1])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[2]_i_1__0 (.I0(D_po_counter_read_val[2]), .I1(A_rst_primitives_reg_1[2]), .I2(A_rst_primitives_reg_2[2]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[2]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [2])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[3]_i_1__0 (.I0(D_po_counter_read_val[3]), .I1(A_rst_primitives_reg_1[3]), .I2(A_rst_primitives_reg_2[3]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[3]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [3])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[4]_i_1__0 (.I0(D_po_counter_read_val[4]), .I1(A_rst_primitives_reg_1[4]), .I2(A_rst_primitives_reg_2[4]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[4]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [4])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[5]_i_1__0 (.I0(D_po_counter_read_val[5]), .I1(A_rst_primitives_reg_1[5]), .I2(A_rst_primitives_reg_2[5]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[5]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [5])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[6]_i_1__0 (.I0(D_po_counter_read_val[6]), .I1(A_rst_primitives_reg_1[6]), .I2(A_rst_primitives_reg_2[6]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[6]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [6])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[7]_i_1__0 (.I0(D_po_counter_read_val[7]), .I1(A_rst_primitives_reg_1[7]), .I2(A_rst_primitives_reg_2[7]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[7]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [7])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[8]_i_1__0 (.I0(D_po_counter_read_val[8]), .I1(A_rst_primitives_reg_1[8]), .I2(A_rst_primitives_reg_2[8]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[8]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [8])); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized3 (SR, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , A_of_full, COUNTERREADVAL, wr_en, \my_empty_reg[1] , Q, mem_dq_out, A_rst_primitives, CLK, D0, D1, OUTBURSTPENDING, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , freq_refclk, mem_refclk, \calib_sel_reg[1]_2 , sync_pulse, PCENABLECALIB, mux_cmd_wren, mem_out); output [0:0]SR; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output A_of_full; output [8:0]COUNTERREADVAL; output wr_en; output \my_empty_reg[1] ; output [3:0]Q; output [1:0]mem_dq_out; input A_rst_primitives; input CLK; input [2:0]D0; input [2:0]D1; input [0:0]OUTBURSTPENDING; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[1]_2 ; input sync_pulse; input [1:0]PCENABLECALIB; input mux_cmd_wren; input [11:0]mem_out; wire A_of_a_full; wire A_of_full; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_rst_primitives; wire CLK; wire [8:0]COUNTERREADVAL; wire [2:0]D0; wire [2:0]D1; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [3:0]Q; wire [0:0]SR; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [1:0]mem_dq_out; wire [11:0]mem_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_2; wire po_oserdes_rst; wire po_rd_enable; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire sync_pulse; wire wr_en; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized3 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q1,of_q0}), .oserdes_rst(po_oserdes_rst)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized6 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .Q(Q), .SR(SR), .mem_out(mem_out), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .ofifo_rst_reg(A_of_full), .\rd_ptr_timing_reg[0]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_2 ), .wr_en(wr_en)); FDRE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(A_rst_primitives), .Q(SR), .R(1'b0)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(A_of_a_full), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D0}), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D1}), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .EMPTY(out_fifo_n_2), .FULL(A_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 )); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(\calib_sel_reg[1] ), .COARSEINC(\calib_sel_reg[1] ), .COARSEOVERFLOW(A_po_coarse_overflow), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERREADVAL(COUNTERREADVAL), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(\calib_sel_reg[1]_0 ), .FINEINC(\calib_sel_reg[1]_1 ), .FINEOVERFLOW(A_po_fine_overflow), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(\calib_sel_reg[1]_2 ), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized4 (\rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , COUNTERREADVAL, wr_en_5, \my_empty_reg[1] , of_ctl_full_v, Q, mem_dq_out, SR, CLK, init_calib_complete_reg_rep__6, D5, D6, OUTBURSTPENDING, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , freq_refclk, mem_refclk, A_rst_primitives, \calib_sel_reg[1]_2 , sync_pulse, PCENABLECALIB, mux_cmd_wren, \rd_ptr_reg[3] , C_of_full, A_of_full, D_of_full); output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output [8:0]COUNTERREADVAL; output wr_en_5; output \my_empty_reg[1] ; output [0:0]of_ctl_full_v; output [3:0]Q; output [2:0]mem_dq_out; input [0:0]SR; input CLK; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [0:0]OUTBURSTPENDING; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input freq_refclk; input mem_refclk; input A_rst_primitives; input \calib_sel_reg[1]_2 ; input sync_pulse; input [1:0]PCENABLECALIB; input mux_cmd_wren; input [17:0]\rd_ptr_reg[3] ; input C_of_full; input A_of_full; input D_of_full; wire A_of_full; wire A_rst_primitives; wire B_of_a_full; wire B_of_full; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire CLK; wire [8:0]COUNTERREADVAL; wire C_of_full; wire [3:0]D5; wire [3:0]D6; wire D_of_full; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [3:0]Q; wire [0:0]SR; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [3:0]init_calib_complete_reg_rep__6; wire [2:0]mem_dq_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire [0:0]of_ctl_full_v; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_2; wire po_oserdes_rst; wire po_rd_enable; wire [17:0]\rd_ptr_reg[3] ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire sync_pulse; wire wr_en_5; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized4 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q4}), .oserdes_rst(po_oserdes_rst)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized7 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.B_of_full(B_of_full), .CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }), .Q(Q), .SR(SR), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_full_reg[3]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_2 ), .wr_en_5(wr_en_5)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(B_of_a_full), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,init_calib_complete_reg_rep__6}), .D5({D5,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D6({D6,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }), .EMPTY(out_fifo_n_2), .FULL(B_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 )); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(\calib_sel_reg[1] ), .COARSEINC(\calib_sel_reg[1] ), .COARSEOVERFLOW(B_po_coarse_overflow), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERREADVAL(COUNTERREADVAL), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(\calib_sel_reg[1]_0 ), .FINEINC(\calib_sel_reg[1]_1 ), .FINEOVERFLOW(B_po_fine_overflow), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(\calib_sel_reg[1]_2 ), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT4 #( .INIT(16'hFFFE)) phy_mc_cmd_full_r_i_1 (.I0(B_of_full), .I1(C_of_full), .I2(A_of_full), .I3(D_of_full), .O(of_ctl_full_v)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized5 (C_of_full, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , COUNTERREADVAL, wr_en_6, \my_empty_reg[1] , Q, mem_dq_out, SR, CLK, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, OUTBURSTPENDING, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, A_rst_primitives, \calib_sel_reg[0]_2 , sync_pulse, PCENABLECALIB, mux_cmd_wren, \rd_ptr_reg[3] ); output C_of_full; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output [8:0]COUNTERREADVAL; output wr_en_6; output \my_empty_reg[1] ; output [3:0]Q; output [9:0]mem_dq_out; input [0:0]SR; input CLK; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [0:0]OUTBURSTPENDING; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input A_rst_primitives; input \calib_sel_reg[0]_2 ; input sync_pulse; input [1:0]PCENABLECALIB; input mux_cmd_wren; input [33:0]\rd_ptr_reg[3] ; wire A_rst_primitives; wire CLK; wire [8:0]COUNTERREADVAL; wire C_of_a_full; wire C_of_full; wire C_po_coarse_overflow; wire C_po_fine_overflow; wire [2:0]D2; wire [2:0]D3; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [3:0]Q; wire [0:0]SR; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire [9:0]mem_dq_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_2; wire po_oserdes_rst; wire po_rd_enable; wire [33:0]\rd_ptr_reg[3] ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire sync_pulse; wire wr_en_6; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized5 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2}), .po_oserdes_rst(po_oserdes_rst)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized8 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }), .Q(Q), .SR(SR), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .ofifo_rst_reg(C_of_full), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ), .\rd_ptr_timing_reg[0]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_2 ), .wr_en_6(wr_en_6)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(C_of_a_full), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D2}), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D3}), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] }), .D5(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .D6(\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,D7}), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,D8}), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,D9}), .EMPTY(out_fifo_n_2), .FULL(C_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 )); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(\calib_sel_reg[0] ), .COARSEINC(\calib_sel_reg[0] ), .COARSEOVERFLOW(C_po_coarse_overflow), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERREADVAL(COUNTERREADVAL), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(\calib_sel_reg[0]_0 ), .FINEINC(\calib_sel_reg[0]_1 ), .FINEOVERFLOW(C_po_fine_overflow), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(\calib_sel_reg[0]_2 ), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized6 (\my_empty_reg[1] , D, ddr_ck_out, D_of_full, mem_dq_out, \my_empty_reg[7] , init_calib_complete_reg_rep__5, mc_cas_n, mc_address, init_calib_complete_reg_rep, COUNTERREADVAL, A_rst_primitives_reg, \calib_sel_reg[1] , A_rst_primitives_reg_0, SR, CLK, OUTBURSTPENDING, D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, freq_refclk, mem_refclk, A_rst_primitives, D_po_sel_fine_oclk_delay125_out, sync_pulse, PCENABLECALIB, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , mux_cmd_wren, phy_dout, init_calib_complete_reg_rep__6); output \my_empty_reg[1] ; output [8:0]D; output [1:0]ddr_ck_out; output D_of_full; output [8:0]mem_dq_out; output [31:0]\my_empty_reg[7] ; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]mc_address; input init_calib_complete_reg_rep; input [8:0]COUNTERREADVAL; input [8:0]A_rst_primitives_reg; input [1:0]\calib_sel_reg[1] ; input [8:0]A_rst_primitives_reg_0; input [0:0]SR; input CLK; input [0:0]OUTBURSTPENDING; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input freq_refclk; input mem_refclk; input A_rst_primitives; input D_po_sel_fine_oclk_delay125_out; input sync_pulse; input [1:0]PCENABLECALIB; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input mux_cmd_wren; input [35:0]phy_dout; input init_calib_complete_reg_rep__6; wire A_rst_primitives; wire [8:0]A_rst_primitives_reg; wire [8:0]A_rst_primitives_reg_0; wire CLK; wire [8:0]COUNTERREADVAL; wire [8:0]D; wire [3:0]D4; wire D_of_full; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire [8:0]D_po_counter_read_val; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [0:0]SR; wire [1:0]\calib_sel_reg[1] ; wire [1:0]ddr_ck_out; wire [0:0]ddr_ck_out_q; wire freq_refclk; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire init_calib_complete_reg_rep__6; wire [1:0]mc_address; wire [0:0]mc_cas_n; wire [8:0]mem_dq_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire [31:0]\my_empty_reg[7] ; wire [3:0]of_d9; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire phaser_out_n_0; wire phaser_out_n_1; wire [35:0]phy_dout; wire po_oserdes_rst; wire po_rd_enable; wire sync_pulse; wire \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized6 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1}), .po_oserdes_rst(po_oserdes_rst)); (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck (.C(oserdes_clk), .CE(1'b1), .D1(1'b0), .D2(1'b1), .Q(ddr_ck_out_q), .R(1'b0), .S(\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED )); (* CAPACITANCE = "DONT_CARE" *) (* XILINX_LEGACY_PRIM = "OBUFDS" *) (* box_type = "PRIMITIVE" *) OBUFDS #( .IOSTANDARD("DEFAULT")) \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf (.I(ddr_ck_out_q), .O(ddr_ck_out[0]), .OB(ddr_ck_out[1])); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized9 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 }), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}), .SR(SR), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .mc_address(mc_address), .mc_cas_n(mc_cas_n), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst_reg(D_of_full), .phy_dout(phy_dout)); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,D4}), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}), .EMPTY(out_fifo_n_2), .FULL(D_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 )); (* box_type = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.111111), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(D_po_coarse_enable110_out), .COARSEINC(D_po_coarse_enable110_out), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(D_po_counter_read_en122_out), .COUNTERREADVAL(D_po_counter_read_val), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(D_po_fine_enable107_out), .FINEINC(D_po_fine_inc113_out), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(D_po_sel_fine_oclk_delay125_out), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[0]_i_1 (.I0(D_po_counter_read_val[0]), .I1(COUNTERREADVAL[0]), .I2(A_rst_primitives_reg[0]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[0]), .I5(\calib_sel_reg[1] [0]), .O(D[0])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[1]_i_1 (.I0(D_po_counter_read_val[1]), .I1(COUNTERREADVAL[1]), .I2(A_rst_primitives_reg[1]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[1]), .I5(\calib_sel_reg[1] [0]), .O(D[1])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[2]_i_1 (.I0(D_po_counter_read_val[2]), .I1(COUNTERREADVAL[2]), .I2(A_rst_primitives_reg[2]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[2]), .I5(\calib_sel_reg[1] [0]), .O(D[2])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[3]_i_1 (.I0(D_po_counter_read_val[3]), .I1(COUNTERREADVAL[3]), .I2(A_rst_primitives_reg[3]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[3]), .I5(\calib_sel_reg[1] [0]), .O(D[3])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[4]_i_1 (.I0(D_po_counter_read_val[4]), .I1(COUNTERREADVAL[4]), .I2(A_rst_primitives_reg[4]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[4]), .I5(\calib_sel_reg[1] [0]), .O(D[4])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[5]_i_1 (.I0(D_po_counter_read_val[5]), .I1(COUNTERREADVAL[5]), .I2(A_rst_primitives_reg[5]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[5]), .I5(\calib_sel_reg[1] [0]), .O(D[5])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[6]_i_1 (.I0(D_po_counter_read_val[6]), .I1(COUNTERREADVAL[6]), .I2(A_rst_primitives_reg[6]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[6]), .I5(\calib_sel_reg[1] [0]), .O(D[6])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[7]_i_1 (.I0(D_po_counter_read_val[7]), .I1(COUNTERREADVAL[7]), .I2(A_rst_primitives_reg[7]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[7]), .I5(\calib_sel_reg[1] [0]), .O(D[7])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[8]_i_1 (.I0(D_po_counter_read_val[8]), .I1(COUNTERREADVAL[8]), .I2(A_rst_primitives_reg[8]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[8]), .I5(\calib_sel_reg[1] [0]), .O(D[8])); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_calib_top" *) module ddr3_ifmig_7series_v4_0_ddr_calib_top (idelay_inc, phy_dout, phy_if_reset, \samps_r_reg[9] , \my_empty_reg[7] , \rd_ptr_timing_reg[0] , app_zq_r_reg, \periodic_rd_generation.periodic_rd_timer_r_reg[1] , init_calib_complete_r_reg, \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_en_stg2_f_timing_reg, out, dqs_po_en_stg2_f_reg, prbs_rdlvl_start_r_reg, A, fine_delay_sel_r_reg, \rd_ptr_timing_reg[0]_0 , \my_empty_reg[7]_0 , \my_empty_reg[7]_1 , \my_empty_reg[7]_2 , \my_empty_reg[7]_3 , LD0, \po_rdval_cnt_reg[8] , LD0_0, LD0_1, LD0_2, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_coarse_enable110_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , \po_counter_read_val_reg[8]_6 , \po_counter_read_val_reg[8]_7 , \po_counter_read_val_reg[8]_8 , \po_counter_read_val_reg[8]_9 , \po_counter_read_val_reg[8]_10 , \po_counter_read_val_reg[8]_11 , E, \po_counter_read_val_reg[8]_12 , \po_counter_read_val_reg[8]_13 , \po_counter_read_val_reg[8]_14 , \po_counter_read_val_reg[8]_15 , \pi_dqs_found_lanes_r1_reg[3] , \fine_delay_r_reg[5] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \po_counter_read_val_reg[8]_16 , \po_counter_read_val_reg[8]_17 , \po_counter_read_val_reg[8]_18 , ififo_rst_reg, \pi_dqs_found_lanes_r1_reg[3]_0 , \pi_dqs_found_lanes_r1_reg[3]_1 , \pi_dqs_found_lanes_r1_reg[3]_2 , \pi_dqs_found_lanes_r1_reg[2] , \fine_delay_r_reg[5]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \po_counter_read_val_reg[8]_19 , \po_counter_read_val_reg[8]_20 , \po_counter_read_val_reg[8]_21 , ififo_rst_reg_0, \pi_dqs_found_lanes_r1_reg[2]_0 , \pi_dqs_found_lanes_r1_reg[2]_1 , \pi_dqs_found_lanes_r1_reg[2]_2 , \pi_dqs_found_lanes_r1_reg[1] , \fine_delay_r_reg[5]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \po_counter_read_val_reg[8]_22 , \po_counter_read_val_reg[8]_23 , \po_counter_read_val_reg[8]_24 , ififo_rst_reg_1, \pi_dqs_found_lanes_r1_reg[1]_0 , \pi_dqs_found_lanes_r1_reg[1]_1 , \pi_dqs_found_lanes_r1_reg[1]_2 , D, COUNTERLOADVAL, \pi_dqs_found_lanes_r1_reg[0] , \fine_delay_r_reg[2] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , \po_counter_read_val_reg[8]_25 , \po_counter_read_val_reg[8]_26 , \po_counter_read_val_reg[8]_27 , ififo_rst_reg_2, \pi_dqs_found_lanes_r1_reg[0]_0 , \pi_dqs_found_lanes_r1_reg[0]_1 , \pi_dqs_found_lanes_r1_reg[0]_2 , \po_counter_read_val_reg[8]_28 , \po_counter_read_val_reg[8]_29 , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, A_1__s_port_, \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 , \A[1]__4 , D2, D0, D3, D5, D6, D1, \rd_ptr_timing_reg[0]_1 , D7, D8, \rd_ptr_timing_reg[0]_2 , \my_empty_reg[7]_4 , \my_empty_reg[7]_5 , \my_empty_reg[7]_6 , D4, \my_empty_reg[7]_7 , \my_empty_reg[7]_8 , \my_empty_reg[7]_9 , \my_empty_reg[7]_10 , \my_full_reg[3] , \rd_ptr_timing_reg[0]_3 , D9, \my_empty_reg[7]_11 , \my_empty_reg[7]_12 , \my_empty_reg[7]_13 , \my_empty_reg[7]_14 , \my_empty_reg[7]_15 , \my_empty_reg[7]_16 , \my_empty_reg[7]_17 , \my_empty_reg[7]_18 , \my_empty_reg[7]_19 , \my_empty_reg[7]_20 , \my_empty_reg[7]_21 , \my_empty_reg[7]_22 , \my_empty_reg[7]_23 , \my_empty_reg[7]_24 , \my_empty_reg[7]_25 , \my_empty_reg[7]_26 , \my_empty_reg[7]_27 , \my_empty_reg[7]_28 , \my_empty_reg[7]_29 , \my_empty_reg[7]_30 , \my_empty_reg[7]_31 , \my_empty_reg[7]_32 , \my_empty_reg[7]_33 , \my_empty_reg[7]_34 , \my_empty_reg[7]_35 , \my_empty_reg[7]_36 , \my_empty_reg[7]_37 , \my_empty_reg[7]_38 , \my_empty_reg[7]_39 , \my_empty_reg[7]_40 , \my_empty_reg[7]_41 , \my_empty_reg[7]_42 , \byte_r_reg[0] , \byte_r_reg[1] , \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , \zero2fuzz_r_reg[0] , maint_prescaler_r1, \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[5] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \rdlvl_dqs_tap_cnt_r_reg[0][3][0] , \idelay_tap_cnt_r_reg[0][3][0] , \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , \fine_delay_mod_reg[5] , \fine_delay_mod_reg[20] , \phy_ctl_wd_i1_reg[24] , phy_write_calib, phy_read_calib, \fine_delay_mod_reg[26] , \genblk9[1].fine_delay_incdec_pb_reg[1] , \genblk9[2].fine_delay_incdec_pb_reg[2] , \genblk9[3].fine_delay_incdec_pb_reg[3] , \genblk9[5].fine_delay_incdec_pb_reg[5] , \genblk9[6].fine_delay_incdec_pb_reg[6] , \genblk9[7].fine_delay_incdec_pb_reg[7] , mux_wrdata_en, mux_cmd_wren, mux_reset_n, \data_offset_1_i1_reg[5] , \rd_ptr_timing_reg[0]_4 , \my_full_reg[3]_0 , \byte_sel_data_map_reg[1] , \A[0]__4 , \A[0]__0 , \A[2]__2 , \A[1]__0 , \A[1]__4_0 , \A[1]__3 , \A[2]__1 , \pi_dqs_found_lanes_r1_reg[1]_3 , \pi_dqs_found_lanes_r1_reg[2]_3 , \pi_dqs_found_lanes_r1_reg[3]_3 , \fine_delay_r_reg[26] , \fine_delay_r_reg[26]_0 , \fine_delay_r_reg[26]_1 , \qcntr_r_reg[0] , CLK, rstdiv0_sync_r1_reg_rep__20, poc_sample_pd, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__9, phy_rddata_en, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 , \po_stg2_wrcal_cnt_reg[1] , \po_stg2_wrcal_cnt_reg[1]_0 , \po_stg2_wrcal_cnt_reg[1]_1 , \po_stg2_wrcal_cnt_reg[1]_2 , \mcGo_r_reg[15] , in0, rstdiv0_sync_r1_reg_rep__12, SR, rstdiv0_sync_r1_reg_rep__23, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, \rd_mux_sel_r_reg[1] , \rd_mux_sel_r_reg[1]_0 , \rd_mux_sel_r_reg[1]_1 , \rd_mux_sel_r_reg[1]_2 , \rd_mux_sel_r_reg[1]_3 , \rd_mux_sel_r_reg[1]_4 , \rd_mux_sel_r_reg[1]_5 , \rd_mux_sel_r_reg[1]_6 , \rd_mux_sel_r_reg[1]_7 , \rd_mux_sel_r_reg[1]_8 , \rd_mux_sel_r_reg[1]_9 , \rd_mux_sel_r_reg[1]_10 , \rd_mux_sel_r_reg[1]_11 , \rd_mux_sel_r_reg[1]_12 , \rd_mux_sel_r_reg[1]_13 , \rd_mux_sel_r_reg[1]_14 , \rd_mux_sel_r_reg[1]_15 , \rd_mux_sel_r_reg[1]_16 , \rd_mux_sel_r_reg[1]_17 , \rd_mux_sel_r_reg[1]_18 , \rd_mux_sel_r_reg[1]_19 , \rd_mux_sel_r_reg[1]_20 , \rd_mux_sel_r_reg[1]_21 , \rd_mux_sel_r_reg[1]_22 , \rd_mux_sel_r_reg[1]_23 , \rd_mux_sel_r_reg[1]_24 , \rd_mux_sel_r_reg[1]_25 , \rd_mux_sel_r_reg[1]_26 , \rd_mux_sel_r_reg[1]_27 , \rd_mux_sel_r_reg[1]_28 , \rd_mux_sel_r_reg[1]_29 , \rd_mux_sel_r_reg[1]_30 , \rd_mux_sel_r_reg[1]_31 , \rd_mux_sel_r_reg[1]_32 , \rd_mux_sel_r_reg[1]_33 , \rd_mux_sel_r_reg[1]_34 , \rd_mux_sel_r_reg[1]_35 , \rd_mux_sel_r_reg[1]_36 , \rd_mux_sel_r_reg[1]_37 , \rd_mux_sel_r_reg[1]_38 , \rd_mux_sel_r_reg[1]_39 , \rd_mux_sel_r_reg[1]_40 , \rd_mux_sel_r_reg[1]_41 , \rd_mux_sel_r_reg[1]_42 , \rd_mux_sel_r_reg[1]_43 , \rd_mux_sel_r_reg[1]_44 , \rd_mux_sel_r_reg[1]_45 , \rd_mux_sel_r_reg[1]_46 , \rd_mux_sel_r_reg[1]_47 , \rd_mux_sel_r_reg[1]_48 , \rd_mux_sel_r_reg[1]_49 , \rd_mux_sel_r_reg[1]_50 , \rd_mux_sel_r_reg[1]_51 , \rd_mux_sel_r_reg[1]_52 , \rd_mux_sel_r_reg[1]_53 , \rd_mux_sel_r_reg[1]_54 , \rd_mux_sel_r_reg[1]_55 , \rd_mux_sel_r_reg[1]_56 , \rd_mux_sel_r_reg[1]_57 , \rd_mux_sel_r_reg[1]_58 , \rd_mux_sel_r_reg[1]_59 , \rd_mux_sel_r_reg[1]_60 , \rd_mux_sel_r_reg[1]_61 , \rd_mux_sel_r_reg[1]_62 , rstdiv0_sync_r1_reg_rep__22, A_rst_primitives_reg, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__17, rstdiv0_sync_r1_reg_rep__16, SS, tempmon_sample_en, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__6, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 , rstdiv0_sync_r1_reg_rep__7, \A[1]_0 , \A[1]_1 , \A[1]_2 , \A[1]_3 , \A[1]_4 , \A[1]_5 , \A[1]_6 , \A[1]_7 , \A[1]_8 , \A[1]_9 , \A[1]_10 , \A[1]_11 , \A[1]_12 , \A[1]_13 , \A[1]_14 , \A[1]_15 , \A[1]_16 , \A[1]_17 , \A[1]_18 , \A[1]_19 , \A[1]_20 , \A[1]_21 , \A[1]_22 , \A[1]_23 , \A[1]_24 , \A[1]_25 , \A[1]_26 , \A[1]_27 , \A[1]_28 , \A[1]_29 , \A[1]_30 , \A[1]_31 , \A[1]_32 , \A[1]_33 , \A[1]_34 , \A[1]_35 , \A[1]_36 , \A[1]_37 , \A[1]_38 , \A[1]_39 , \A[1]_40 , \A[1]_41 , \A[1]_42 , \A[1]_43 , \A[1]_44 , \A[1]_45 , \A[1]_46 , \A[1]_47 , \A[1]_48 , \A[1]_49 , \A[1]_50 , \A[1]_51 , \A[1]_52 , \A[1]_53 , \A[1]_54 , \A[1]_55 , \A[1]_56 , \A[1]_57 , \A[1]_58 , \A[1]_59 , \A[1]_60 , \A[1]_61 , \A[1]_62 , \A[1]_63 , rstdiv0_sync_r1_reg_rep__8, rstdiv0_sync_r1_reg_rep, p_0_out, \po_stg2_wrcal_cnt_reg[1]_3 , \po_stg2_wrcal_cnt_reg[1]_4 , \po_stg2_wrcal_cnt_reg[1]_5 , \po_stg2_wrcal_cnt_reg[1]_6 , \po_stg2_wrcal_cnt_reg[1]_7 , \po_stg2_wrcal_cnt_reg[1]_8 , \po_stg2_wrcal_cnt_reg[1]_9 , \po_stg2_wrcal_cnt_reg[1]_10 , \po_stg2_wrcal_cnt_reg[1]_11 , \po_stg2_wrcal_cnt_reg[1]_12 , \po_stg2_wrcal_cnt_reg[1]_13 , \po_stg2_wrcal_cnt_reg[1]_14 , \po_stg2_wrcal_cnt_reg[1]_15 , \po_stg2_wrcal_cnt_reg[1]_16 , \po_stg2_wrcal_cnt_reg[1]_17 , \po_stg2_wrcal_cnt_reg[1]_18 , \po_stg2_wrcal_cnt_reg[1]_19 , \po_stg2_wrcal_cnt_reg[1]_20 , \po_stg2_wrcal_cnt_reg[1]_21 , \po_stg2_wrcal_cnt_reg[1]_22 , \po_stg2_wrcal_cnt_reg[1]_23 , \po_stg2_wrcal_cnt_reg[1]_24 , \po_stg2_wrcal_cnt_reg[1]_25 , \po_stg2_wrcal_cnt_reg[1]_26 , \po_stg2_wrcal_cnt_reg[1]_27 , \po_stg2_wrcal_cnt_reg[1]_28 , \po_stg2_wrcal_cnt_reg[1]_29 , \po_stg2_wrcal_cnt_reg[1]_30 , \po_stg2_wrcal_cnt_reg[1]_31 , \po_stg2_wrcal_cnt_reg[1]_32 , \po_stg2_wrcal_cnt_reg[1]_33 , \po_stg2_wrcal_cnt_reg[1]_34 , \po_stg2_wrcal_cnt_reg[1]_35 , \po_stg2_wrcal_cnt_reg[1]_36 , \po_stg2_wrcal_cnt_reg[1]_37 , \po_stg2_wrcal_cnt_reg[1]_38 , \po_stg2_wrcal_cnt_reg[1]_39 , \po_stg2_wrcal_cnt_reg[1]_40 , \po_stg2_wrcal_cnt_reg[1]_41 , \po_stg2_wrcal_cnt_reg[1]_42 , \po_stg2_wrcal_cnt_reg[1]_43 , \po_stg2_wrcal_cnt_reg[1]_44 , \po_stg2_wrcal_cnt_reg[1]_45 , \po_stg2_wrcal_cnt_reg[1]_46 , \po_stg2_wrcal_cnt_reg[1]_47 , \po_stg2_wrcal_cnt_reg[1]_48 , \po_stg2_wrcal_cnt_reg[1]_49 , \po_stg2_wrcal_cnt_reg[1]_50 , \po_stg2_wrcal_cnt_reg[1]_51 , \po_stg2_wrcal_cnt_reg[1]_52 , \po_stg2_wrcal_cnt_reg[1]_53 , \po_stg2_wrcal_cnt_reg[1]_54 , \po_stg2_wrcal_cnt_reg[1]_55 , \po_stg2_wrcal_cnt_reg[1]_56 , \po_stg2_wrcal_cnt_reg[1]_57 , \po_stg2_wrcal_cnt_reg[1]_58 , \po_stg2_wrcal_cnt_reg[1]_59 , \po_stg2_wrcal_cnt_reg[1]_60 , \po_stg2_wrcal_cnt_reg[1]_61 , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__5, Q, idelay_ld_rst, idelay_ld_rst_3, idelay_ld_rst_4, idelay_ld_rst_5, rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__25_0, rstdiv0_sync_r1_reg_rep__24, \sm_r_reg[0]_0 , fine_delay_sel_r, fine_delay_mod, mc_cas_n, \rd_ptr_reg[3] , \my_empty_reg[1] , mem_out, \my_empty_reg[1]_0 , mc_ras_n, mc_odt, \rd_ptr_reg[3]_0 , \my_empty_reg[1]_1 , mc_cke, mc_we_n, mc_address, \rd_ptr_reg[3]_1 , \my_empty_reg[1]_2 , mc_bank, \rd_ptr_reg[3]_2 , \my_empty_reg[1]_3 , \rd_ptr_reg[3]_3 , \my_empty_reg[1]_4 , \rd_ptr_reg[3]_4 , \my_empty_reg[1]_5 , \rd_ptr_reg[3]_5 , \my_empty_reg[1]_6 , mc_cs_n, \pi_counter_read_val_reg[5] , \po_counter_read_val_reg[2] , rstdiv0_sync_r1_reg_rep__25_1, rstdiv0_sync_r1_reg_rep__25_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , \po_counter_read_val_reg[8]_30 , \po_counter_read_val_reg[8]_31 , \po_counter_read_val_reg[5] , \A[2]__2_0 , psdone, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__19, \byte_r_reg[0]_0 , fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__23_0, p_81_in, rstdiv0_sync_r1_reg_rep__23_1, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , my_empty, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 , my_empty_6, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 , my_empty_7, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , my_empty_8, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 , po_cnt_dec_reg, \device_temp_r_reg[11] , mc_wrdata_en, \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 , mc_cmd, \cmd_pipe_plus.mc_data_offset_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_reg[5]_0 , \stg3_r_reg[0] , pd_out); output idelay_inc; output [33:0]phy_dout; output phy_if_reset; output \samps_r_reg[9] ; output \my_empty_reg[7] ; output \rd_ptr_timing_reg[0] ; output app_zq_r_reg; output \periodic_rd_generation.periodic_rd_timer_r_reg[1] ; output init_calib_complete_r_reg; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_en_stg2_f_timing_reg; output out; output dqs_po_en_stg2_f_reg; output prbs_rdlvl_start_r_reg; output [1:0]A; output fine_delay_sel_r_reg; output [33:0]\rd_ptr_timing_reg[0]_0 ; output [71:0]\my_empty_reg[7]_0 ; output [71:0]\my_empty_reg[7]_1 ; output [71:0]\my_empty_reg[7]_2 ; output [71:0]\my_empty_reg[7]_3 ; output LD0; output [2:0]\po_rdval_cnt_reg[8] ; output LD0_0; output LD0_1; output LD0_2; output D_po_counter_read_en122_out; output D_po_fine_enable107_out; output D_po_coarse_enable110_out; output D_po_fine_inc113_out; output D_po_sel_fine_oclk_delay125_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output \po_counter_read_val_reg[8]_6 ; output \po_counter_read_val_reg[8]_7 ; output \po_counter_read_val_reg[8]_8 ; output \po_counter_read_val_reg[8]_9 ; output \po_counter_read_val_reg[8]_10 ; output \po_counter_read_val_reg[8]_11 ; output [0:0]E; output \po_counter_read_val_reg[8]_12 ; output \po_counter_read_val_reg[8]_13 ; output \po_counter_read_val_reg[8]_14 ; output \po_counter_read_val_reg[8]_15 ; output \pi_dqs_found_lanes_r1_reg[3] ; output [0:0]\fine_delay_r_reg[5] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \po_counter_read_val_reg[8]_16 ; output \po_counter_read_val_reg[8]_17 ; output \po_counter_read_val_reg[8]_18 ; output ififo_rst_reg; output \pi_dqs_found_lanes_r1_reg[3]_0 ; output \pi_dqs_found_lanes_r1_reg[3]_1 ; output \pi_dqs_found_lanes_r1_reg[3]_2 ; output \pi_dqs_found_lanes_r1_reg[2] ; output [0:0]\fine_delay_r_reg[5]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \po_counter_read_val_reg[8]_19 ; output \po_counter_read_val_reg[8]_20 ; output \po_counter_read_val_reg[8]_21 ; output ififo_rst_reg_0; output \pi_dqs_found_lanes_r1_reg[2]_0 ; output \pi_dqs_found_lanes_r1_reg[2]_1 ; output \pi_dqs_found_lanes_r1_reg[2]_2 ; output \pi_dqs_found_lanes_r1_reg[1] ; output [0:0]\fine_delay_r_reg[5]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \po_counter_read_val_reg[8]_22 ; output \po_counter_read_val_reg[8]_23 ; output \po_counter_read_val_reg[8]_24 ; output ififo_rst_reg_1; output \pi_dqs_found_lanes_r1_reg[1]_0 ; output \pi_dqs_found_lanes_r1_reg[1]_1 ; output \pi_dqs_found_lanes_r1_reg[1]_2 ; output [7:0]D; output [5:0]COUNTERLOADVAL; output \pi_dqs_found_lanes_r1_reg[0] ; output [0:0]\fine_delay_r_reg[2] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output \po_counter_read_val_reg[8]_25 ; output \po_counter_read_val_reg[8]_26 ; output \po_counter_read_val_reg[8]_27 ; output ififo_rst_reg_2; output \pi_dqs_found_lanes_r1_reg[0]_0 ; output \pi_dqs_found_lanes_r1_reg[0]_1 ; output \pi_dqs_found_lanes_r1_reg[0]_2 ; output \po_counter_read_val_reg[8]_28 ; output \po_counter_read_val_reg[8]_29 ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output A_1__s_port_; output [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; output \A[1]__4 ; output [2:0]D2; output [2:0]D0; output [2:0]D3; output [3:0]D5; output [3:0]D6; output [2:0]D1; output [7:0]\rd_ptr_timing_reg[0]_1 ; output [3:0]D7; output [3:0]D8; output [7:0]\rd_ptr_timing_reg[0]_2 ; output [3:0]\my_empty_reg[7]_4 ; output [3:0]\my_empty_reg[7]_5 ; output [3:0]\my_empty_reg[7]_6 ; output [3:0]D4; output [3:0]\my_empty_reg[7]_7 ; output [3:0]\my_empty_reg[7]_8 ; output [3:0]\my_empty_reg[7]_9 ; output [3:0]\my_empty_reg[7]_10 ; output [3:0]\my_full_reg[3] ; output [3:0]\rd_ptr_timing_reg[0]_3 ; output [3:0]D9; output [7:0]\my_empty_reg[7]_11 ; output [7:0]\my_empty_reg[7]_12 ; output [7:0]\my_empty_reg[7]_13 ; output [7:0]\my_empty_reg[7]_14 ; output [7:0]\my_empty_reg[7]_15 ; output [7:0]\my_empty_reg[7]_16 ; output [7:0]\my_empty_reg[7]_17 ; output [7:0]\my_empty_reg[7]_18 ; output [7:0]\my_empty_reg[7]_19 ; output [7:0]\my_empty_reg[7]_20 ; output [7:0]\my_empty_reg[7]_21 ; output [7:0]\my_empty_reg[7]_22 ; output [7:0]\my_empty_reg[7]_23 ; output [7:0]\my_empty_reg[7]_24 ; output [7:0]\my_empty_reg[7]_25 ; output [7:0]\my_empty_reg[7]_26 ; output [7:0]\my_empty_reg[7]_27 ; output [7:0]\my_empty_reg[7]_28 ; output [7:0]\my_empty_reg[7]_29 ; output [7:0]\my_empty_reg[7]_30 ; output [7:0]\my_empty_reg[7]_31 ; output [7:0]\my_empty_reg[7]_32 ; output [7:0]\my_empty_reg[7]_33 ; output [7:0]\my_empty_reg[7]_34 ; output [7:0]\my_empty_reg[7]_35 ; output [7:0]\my_empty_reg[7]_36 ; output [7:0]\my_empty_reg[7]_37 ; output [7:0]\my_empty_reg[7]_38 ; output [7:0]\my_empty_reg[7]_39 ; output [7:0]\my_empty_reg[7]_40 ; output [7:0]\my_empty_reg[7]_41 ; output [7:0]\my_empty_reg[7]_42 ; output \byte_r_reg[0] ; output \byte_r_reg[1] ; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]\zero2fuzz_r_reg[0] ; output maint_prescaler_r1; output \cmd_pipe_plus.mc_data_offset_reg[4] ; output [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; output \cmd_pipe_plus.mc_data_offset_reg[1] ; output \cmd_pipe_plus.mc_data_offset_1_reg[4] ; output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; output \cmd_pipe_plus.mc_data_offset_1_reg[1] ; output \cmd_pipe_plus.mc_data_offset_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ; output [1:0]\idelay_tap_cnt_r_reg[0][3][0] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output \fine_delay_mod_reg[5] ; output \fine_delay_mod_reg[20] ; output [10:0]\phy_ctl_wd_i1_reg[24] ; output phy_write_calib; output phy_read_calib; output \fine_delay_mod_reg[26] ; output \genblk9[1].fine_delay_incdec_pb_reg[1] ; output \genblk9[2].fine_delay_incdec_pb_reg[2] ; output \genblk9[3].fine_delay_incdec_pb_reg[3] ; output \genblk9[5].fine_delay_incdec_pb_reg[5] ; output \genblk9[6].fine_delay_incdec_pb_reg[6] ; output \genblk9[7].fine_delay_incdec_pb_reg[7] ; output mux_wrdata_en; output mux_cmd_wren; output mux_reset_n; output [5:0]\data_offset_1_i1_reg[5] ; output [1:0]\rd_ptr_timing_reg[0]_4 ; output [1:0]\my_full_reg[3]_0 ; output \byte_sel_data_map_reg[1] ; output \A[0]__4 ; output \A[0]__0 ; output \A[2]__2 ; output \A[1]__0 ; output \A[1]__4_0 ; output \A[1]__3 ; output \A[2]__1 ; output [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ; output [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ; output [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ; output [7:0]\fine_delay_r_reg[26] ; output [7:0]\fine_delay_r_reg[26]_0 ; output [7:0]\fine_delay_r_reg[26]_1 ; output [0:0]\qcntr_r_reg[0] ; input CLK; input rstdiv0_sync_r1_reg_rep__20; input poc_sample_pd; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__9; input phy_rddata_en; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ; input \po_stg2_wrcal_cnt_reg[1] ; input \po_stg2_wrcal_cnt_reg[1]_0 ; input \po_stg2_wrcal_cnt_reg[1]_1 ; input \po_stg2_wrcal_cnt_reg[1]_2 ; input \mcGo_r_reg[15] ; input [3:0]in0; input [0:0]rstdiv0_sync_r1_reg_rep__12; input [0:0]SR; input rstdiv0_sync_r1_reg_rep__23; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input \rd_mux_sel_r_reg[1] ; input \rd_mux_sel_r_reg[1]_0 ; input \rd_mux_sel_r_reg[1]_1 ; input \rd_mux_sel_r_reg[1]_2 ; input \rd_mux_sel_r_reg[1]_3 ; input \rd_mux_sel_r_reg[1]_4 ; input \rd_mux_sel_r_reg[1]_5 ; input \rd_mux_sel_r_reg[1]_6 ; input \rd_mux_sel_r_reg[1]_7 ; input \rd_mux_sel_r_reg[1]_8 ; input \rd_mux_sel_r_reg[1]_9 ; input \rd_mux_sel_r_reg[1]_10 ; input \rd_mux_sel_r_reg[1]_11 ; input \rd_mux_sel_r_reg[1]_12 ; input \rd_mux_sel_r_reg[1]_13 ; input \rd_mux_sel_r_reg[1]_14 ; input \rd_mux_sel_r_reg[1]_15 ; input \rd_mux_sel_r_reg[1]_16 ; input \rd_mux_sel_r_reg[1]_17 ; input \rd_mux_sel_r_reg[1]_18 ; input \rd_mux_sel_r_reg[1]_19 ; input \rd_mux_sel_r_reg[1]_20 ; input \rd_mux_sel_r_reg[1]_21 ; input \rd_mux_sel_r_reg[1]_22 ; input \rd_mux_sel_r_reg[1]_23 ; input \rd_mux_sel_r_reg[1]_24 ; input \rd_mux_sel_r_reg[1]_25 ; input \rd_mux_sel_r_reg[1]_26 ; input \rd_mux_sel_r_reg[1]_27 ; input \rd_mux_sel_r_reg[1]_28 ; input \rd_mux_sel_r_reg[1]_29 ; input \rd_mux_sel_r_reg[1]_30 ; input \rd_mux_sel_r_reg[1]_31 ; input \rd_mux_sel_r_reg[1]_32 ; input \rd_mux_sel_r_reg[1]_33 ; input \rd_mux_sel_r_reg[1]_34 ; input \rd_mux_sel_r_reg[1]_35 ; input \rd_mux_sel_r_reg[1]_36 ; input \rd_mux_sel_r_reg[1]_37 ; input \rd_mux_sel_r_reg[1]_38 ; input \rd_mux_sel_r_reg[1]_39 ; input \rd_mux_sel_r_reg[1]_40 ; input \rd_mux_sel_r_reg[1]_41 ; input \rd_mux_sel_r_reg[1]_42 ; input \rd_mux_sel_r_reg[1]_43 ; input \rd_mux_sel_r_reg[1]_44 ; input \rd_mux_sel_r_reg[1]_45 ; input \rd_mux_sel_r_reg[1]_46 ; input \rd_mux_sel_r_reg[1]_47 ; input \rd_mux_sel_r_reg[1]_48 ; input \rd_mux_sel_r_reg[1]_49 ; input \rd_mux_sel_r_reg[1]_50 ; input \rd_mux_sel_r_reg[1]_51 ; input \rd_mux_sel_r_reg[1]_52 ; input \rd_mux_sel_r_reg[1]_53 ; input \rd_mux_sel_r_reg[1]_54 ; input \rd_mux_sel_r_reg[1]_55 ; input \rd_mux_sel_r_reg[1]_56 ; input \rd_mux_sel_r_reg[1]_57 ; input \rd_mux_sel_r_reg[1]_58 ; input \rd_mux_sel_r_reg[1]_59 ; input \rd_mux_sel_r_reg[1]_60 ; input \rd_mux_sel_r_reg[1]_61 ; input \rd_mux_sel_r_reg[1]_62 ; input rstdiv0_sync_r1_reg_rep__22; input A_rst_primitives_reg; input rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [1:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input tempmon_sample_en; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__6; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ; input [0:0]rstdiv0_sync_r1_reg_rep__7; input \A[1]_0 ; input \A[1]_1 ; input \A[1]_2 ; input \A[1]_3 ; input \A[1]_4 ; input \A[1]_5 ; input \A[1]_6 ; input \A[1]_7 ; input \A[1]_8 ; input \A[1]_9 ; input \A[1]_10 ; input \A[1]_11 ; input \A[1]_12 ; input \A[1]_13 ; input \A[1]_14 ; input \A[1]_15 ; input \A[1]_16 ; input \A[1]_17 ; input \A[1]_18 ; input \A[1]_19 ; input \A[1]_20 ; input \A[1]_21 ; input \A[1]_22 ; input \A[1]_23 ; input \A[1]_24 ; input \A[1]_25 ; input \A[1]_26 ; input \A[1]_27 ; input \A[1]_28 ; input \A[1]_29 ; input \A[1]_30 ; input \A[1]_31 ; input \A[1]_32 ; input \A[1]_33 ; input \A[1]_34 ; input \A[1]_35 ; input \A[1]_36 ; input \A[1]_37 ; input \A[1]_38 ; input \A[1]_39 ; input \A[1]_40 ; input \A[1]_41 ; input \A[1]_42 ; input \A[1]_43 ; input \A[1]_44 ; input \A[1]_45 ; input \A[1]_46 ; input \A[1]_47 ; input \A[1]_48 ; input \A[1]_49 ; input \A[1]_50 ; input \A[1]_51 ; input \A[1]_52 ; input \A[1]_53 ; input \A[1]_54 ; input \A[1]_55 ; input \A[1]_56 ; input \A[1]_57 ; input \A[1]_58 ; input \A[1]_59 ; input \A[1]_60 ; input \A[1]_61 ; input \A[1]_62 ; input \A[1]_63 ; input rstdiv0_sync_r1_reg_rep__8; input rstdiv0_sync_r1_reg_rep; input p_0_out; input \po_stg2_wrcal_cnt_reg[1]_3 ; input \po_stg2_wrcal_cnt_reg[1]_4 ; input \po_stg2_wrcal_cnt_reg[1]_5 ; input \po_stg2_wrcal_cnt_reg[1]_6 ; input \po_stg2_wrcal_cnt_reg[1]_7 ; input \po_stg2_wrcal_cnt_reg[1]_8 ; input \po_stg2_wrcal_cnt_reg[1]_9 ; input \po_stg2_wrcal_cnt_reg[1]_10 ; input \po_stg2_wrcal_cnt_reg[1]_11 ; input \po_stg2_wrcal_cnt_reg[1]_12 ; input \po_stg2_wrcal_cnt_reg[1]_13 ; input \po_stg2_wrcal_cnt_reg[1]_14 ; input \po_stg2_wrcal_cnt_reg[1]_15 ; input \po_stg2_wrcal_cnt_reg[1]_16 ; input \po_stg2_wrcal_cnt_reg[1]_17 ; input \po_stg2_wrcal_cnt_reg[1]_18 ; input \po_stg2_wrcal_cnt_reg[1]_19 ; input \po_stg2_wrcal_cnt_reg[1]_20 ; input \po_stg2_wrcal_cnt_reg[1]_21 ; input \po_stg2_wrcal_cnt_reg[1]_22 ; input \po_stg2_wrcal_cnt_reg[1]_23 ; input \po_stg2_wrcal_cnt_reg[1]_24 ; input \po_stg2_wrcal_cnt_reg[1]_25 ; input \po_stg2_wrcal_cnt_reg[1]_26 ; input \po_stg2_wrcal_cnt_reg[1]_27 ; input \po_stg2_wrcal_cnt_reg[1]_28 ; input \po_stg2_wrcal_cnt_reg[1]_29 ; input \po_stg2_wrcal_cnt_reg[1]_30 ; input \po_stg2_wrcal_cnt_reg[1]_31 ; input \po_stg2_wrcal_cnt_reg[1]_32 ; input \po_stg2_wrcal_cnt_reg[1]_33 ; input \po_stg2_wrcal_cnt_reg[1]_34 ; input \po_stg2_wrcal_cnt_reg[1]_35 ; input \po_stg2_wrcal_cnt_reg[1]_36 ; input \po_stg2_wrcal_cnt_reg[1]_37 ; input \po_stg2_wrcal_cnt_reg[1]_38 ; input \po_stg2_wrcal_cnt_reg[1]_39 ; input \po_stg2_wrcal_cnt_reg[1]_40 ; input \po_stg2_wrcal_cnt_reg[1]_41 ; input \po_stg2_wrcal_cnt_reg[1]_42 ; input \po_stg2_wrcal_cnt_reg[1]_43 ; input \po_stg2_wrcal_cnt_reg[1]_44 ; input \po_stg2_wrcal_cnt_reg[1]_45 ; input \po_stg2_wrcal_cnt_reg[1]_46 ; input \po_stg2_wrcal_cnt_reg[1]_47 ; input \po_stg2_wrcal_cnt_reg[1]_48 ; input \po_stg2_wrcal_cnt_reg[1]_49 ; input \po_stg2_wrcal_cnt_reg[1]_50 ; input \po_stg2_wrcal_cnt_reg[1]_51 ; input \po_stg2_wrcal_cnt_reg[1]_52 ; input \po_stg2_wrcal_cnt_reg[1]_53 ; input \po_stg2_wrcal_cnt_reg[1]_54 ; input \po_stg2_wrcal_cnt_reg[1]_55 ; input \po_stg2_wrcal_cnt_reg[1]_56 ; input \po_stg2_wrcal_cnt_reg[1]_57 ; input \po_stg2_wrcal_cnt_reg[1]_58 ; input \po_stg2_wrcal_cnt_reg[1]_59 ; input \po_stg2_wrcal_cnt_reg[1]_60 ; input \po_stg2_wrcal_cnt_reg[1]_61 ; input [0:0]rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__5; input [287:0]Q; input idelay_ld_rst; input idelay_ld_rst_3; input idelay_ld_rst_4; input idelay_ld_rst_5; input rstdiv0_sync_r1_reg_rep__25; input rstdiv0_sync_r1_reg_rep__25_0; input rstdiv0_sync_r1_reg_rep__24; input [0:0]\sm_r_reg[0]_0 ; input fine_delay_sel_r; input [8:0]fine_delay_mod; input [2:0]mc_cas_n; input [37:0]\rd_ptr_reg[3] ; input \my_empty_reg[1] ; input [5:0]mem_out; input \my_empty_reg[1]_0 ; input [2:0]mc_ras_n; input [0:0]mc_odt; input [11:0]\rd_ptr_reg[3]_0 ; input \my_empty_reg[1]_1 ; input [0:0]mc_cke; input [2:0]mc_we_n; input [35:0]mc_address; input [31:0]\rd_ptr_reg[3]_1 ; input \my_empty_reg[1]_2 ; input [8:0]mc_bank; input [63:0]\rd_ptr_reg[3]_2 ; input \my_empty_reg[1]_3 ; input [63:0]\rd_ptr_reg[3]_3 ; input \my_empty_reg[1]_4 ; input [63:0]\rd_ptr_reg[3]_4 ; input \my_empty_reg[1]_5 ; input [63:0]\rd_ptr_reg[3]_5 ; input \my_empty_reg[1]_6 ; input [0:0]mc_cs_n; input [5:0]\pi_counter_read_val_reg[5] ; input \po_counter_read_val_reg[2] ; input rstdiv0_sync_r1_reg_rep__25_1; input rstdiv0_sync_r1_reg_rep__25_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input [4:0]\po_counter_read_val_reg[8]_30 ; input [4:0]\po_counter_read_val_reg[8]_31 ; input [5:0]\po_counter_read_val_reg[5] ; input \A[2]__2_0 ; input psdone; input rstdiv0_sync_r1_reg_rep__0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [63:0]\byte_r_reg[0]_0 ; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__23_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__23_1; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [0:0]my_empty; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; input [0:0]my_empty_6; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; input [0:0]my_empty_7; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [0:0]my_empty_8; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; input [0:0]po_cnt_dec_reg; input [11:0]\device_temp_r_reg[11] ; input mc_wrdata_en; input \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[2] ; input \cmd_pipe_plus.mc_data_offset_1_reg[3] ; input \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; input [1:0]mc_cmd; input \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[2] ; input \cmd_pipe_plus.mc_data_offset_reg[3] ; input \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; input \stg3_r_reg[0] ; input pd_out; wire [1:0]A; wire \A[0]__0 ; wire \A[0]__4 ; wire \A[1]_0 ; wire \A[1]_1 ; wire \A[1]_10 ; wire \A[1]_11 ; wire \A[1]_12 ; wire \A[1]_13 ; wire \A[1]_14 ; wire \A[1]_15 ; wire \A[1]_16 ; wire \A[1]_17 ; wire \A[1]_18 ; wire \A[1]_19 ; wire \A[1]_2 ; wire \A[1]_20 ; wire \A[1]_21 ; wire \A[1]_22 ; wire \A[1]_23 ; wire \A[1]_24 ; wire \A[1]_25 ; wire \A[1]_26 ; wire \A[1]_27 ; wire \A[1]_28 ; wire \A[1]_29 ; wire \A[1]_3 ; wire \A[1]_30 ; wire \A[1]_31 ; wire \A[1]_32 ; wire \A[1]_33 ; wire \A[1]_34 ; wire \A[1]_35 ; wire \A[1]_36 ; wire \A[1]_37 ; wire \A[1]_38 ; wire \A[1]_39 ; wire \A[1]_4 ; wire \A[1]_40 ; wire \A[1]_41 ; wire \A[1]_42 ; wire \A[1]_43 ; wire \A[1]_44 ; wire \A[1]_45 ; wire \A[1]_46 ; wire \A[1]_47 ; wire \A[1]_48 ; wire \A[1]_49 ; wire \A[1]_5 ; wire \A[1]_50 ; wire \A[1]_51 ; wire \A[1]_52 ; wire \A[1]_53 ; wire \A[1]_54 ; wire \A[1]_55 ; wire \A[1]_56 ; wire \A[1]_57 ; wire \A[1]_58 ; wire \A[1]_59 ; wire \A[1]_6 ; wire \A[1]_60 ; wire \A[1]_61 ; wire \A[1]_62 ; wire \A[1]_63 ; wire \A[1]_7 ; wire \A[1]_8 ; wire \A[1]_9 ; wire \A[1]__0 ; wire \A[1]__3 ; wire \A[1]__4 ; wire \A[1]__4_0 ; wire \A[2]__1 ; wire \A[2]__2 ; wire \A[2]__2_0 ; wire A_1__s_net_1; wire A_rst_primitives_reg; wire CLK; wire [5:0]COUNTERLOADVAL; wire [7:0]D; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]E; wire LD0; wire LD0_0; wire LD0_1; wire LD0_2; wire [287:0]Q; wire [0:0]SR; wire [0:0]SS; wire app_zq_r_reg; wire bit_cnt; wire burst_addr_r_i_1_n_0; wire \byte_r_reg[0] ; wire [63:0]\byte_r_reg[0]_0 ; wire \byte_r_reg[1] ; wire [2:2]byte_sel_cnt; wire \byte_sel_data_map_reg[1] ; wire cal1_cnt_cpt_r1; wire cal1_state_r1535_out; wire cal1_wait_r; wire cal2_done_r; wire cal2_done_r_i_1_n_0; wire cal2_if_reset_i_1_n_0; wire calib_complete; wire calib_in_common; wire [1:1]calib_zero_inputs; wire [0:0]calib_zero_inputs__0; wire ck_addr_cmd_delay_done; wire ck_po_stg2_f_en; wire ck_po_stg2_f_en_i_1_n_0; wire ck_po_stg2_f_indec; wire ck_po_stg2_f_indec_i_1_n_0; wire cmd_delay_start0; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; wire cmd_po_en_stg2_f; wire cnt_cmd_done_r; wire cnt_dllk_zqinit_done_r; wire cnt_dllk_zqinit_done_r_i_1_n_0; wire [7:6]cnt_dllk_zqinit_r_reg__0; wire cnt_init_af_done_r; wire cnt_init_af_done_r_i_1_n_0; wire [1:0]cnt_init_af_r; wire cnt_init_mr_done_r; wire cnt_init_mr_done_r_i_1_n_0; wire [1:0]cnt_init_mr_r; wire cnt_init_mr_r1; wire cnt_pwron_cke_done_r; wire cnt_pwron_cke_done_r_i_1_n_0; wire [7:0]cnt_pwron_r_reg__0; wire cnt_pwron_reset_done_r; wire cnt_pwron_reset_done_r0; wire cnt_pwron_reset_done_r_i_1_n_0; wire cnt_shift_r0; wire cnt_txpr_done_r; wire cnt_txpr_done_r_i_1_n_0; wire [2:0]cnt_txpr_r_reg__0; wire cnt_wait_state; wire complex_act_start; wire complex_init_pi_dec_done; wire complex_init_pi_dec_done_r_i_1_n_0; wire complex_ocal_num_samples_done_r; wire [2:0]complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_reset_rd_addr; wire complex_oclk_calib_resume; wire complex_pi_incdec_done; wire complex_pi_incdec_done_i_1_n_0; wire \complex_row_cnt_ocal_reg[0] ; wire [2:0]ctl_lane_cnt; wire ctl_lane_sel; wire [5:0]\data_offset_1_i1_reg[5] ; wire ddr2_pre_flag_r_i_1_n_0; wire ddr2_refresh_flag_r; wire ddr2_refresh_flag_r_i_1_n_0; wire ddr3_lm_done_r; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ; (* MAX_FANOUT = "100" *) (* RTL_MAX_FANOUT = "found" *) wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ; (* MAX_FANOUT = "100" *) (* RTL_MAX_FANOUT = "found" *) wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ; wire ddr_phy_tempmon_0_n_2; wire ddr_phy_tempmon_0_n_3; wire ddr_phy_tempmon_0_n_4; wire ddr_phy_tempmon_0_n_5; wire ddr_phy_tempmon_0_n_6; wire [5:0]dec_cnt_reg; wire detect_edge_done_r; wire detect_pi_found_dqs; wire [11:0]\device_temp_r_reg[11] ; wire done_dqs_dec239_out; wire done_dqs_tap_inc; wire dq_cnt_inc_i_1_n_0; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; wire dqs_found_prech_req; wire dqs_found_prech_req_i_1_n_0; wire dqs_po_dec_done; wire dqs_po_dec_done_r2; wire dqs_po_en_stg2_f; wire dqs_po_en_stg2_f_reg; wire dqs_po_stg2_f_incdec; wire dqs_wl_po_stg2_c_incdec; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_107 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_69 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_70 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_72 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_75 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_81 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_83 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_99 ; wire early1_data_i_1_n_0; wire early2_data_i_1_n_0; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire [2:1]final_coarse_tap; wire final_dec_done_i_1_n_0; wire fine_adj_state_r144_out; wire fine_adj_state_r16_out; wire fine_adjust_done_r_i_1_n_0; wire fine_adjust_i_1_n_0; wire fine_adjust_reg; wire [8:0]fine_delay_mod; wire \fine_delay_mod_reg[20] ; wire \fine_delay_mod_reg[26] ; wire \fine_delay_mod_reg[5] ; wire [7:0]\fine_delay_r_reg[26] ; wire [7:0]\fine_delay_r_reg[26]_0 ; wire [7:0]\fine_delay_r_reg[26]_1 ; wire [0:0]\fine_delay_r_reg[2] ; wire [0:0]\fine_delay_r_reg[5] ; wire [0:0]\fine_delay_r_reg[5]_0 ; wire [0:0]\fine_delay_r_reg[5]_1 ; wire fine_delay_sel_i_1_n_0; wire fine_delay_sel_r; wire fine_delay_sel_r_reg; wire fine_dly_error_i_1_n_0; wire first_rdlvl_pat_r; wire first_wrcal_pat_r; wire flag_ck_negedge09_out; wire flag_ck_negedge_i_1_n_0; wire found_first_edge_r_i_1_n_0; wire found_second_edge_r_i_1_n_0; wire found_stable_eye_last_r; wire found_stable_eye_last_r_i_1_n_0; wire [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ; wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ; wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ; wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ; wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ; wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ; wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ; wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ; wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ; wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ; wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ; wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ; wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ; wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ; wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ; wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ; wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ; wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ; wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ; wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ; wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ; wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ; wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ; wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ; wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ; wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ; wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ; wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ; wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ; wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ; wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ; wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ; wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ; wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ; wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ; wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ; wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ; wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ; wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ; wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ; wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ; wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ; wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ; wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ; wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ; wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ; wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ; wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ; wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ; wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ; wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ; wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ; wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ; wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ; wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ; wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ; wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ; wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ; wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ; wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ; wire \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ; wire \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg ; wire \genblk8[0].left_edge_found_pb[0]_i_1_n_0 ; wire \genblk8[0].left_edge_updated[0]_i_1_n_0 ; wire \genblk8[0].right_edge_found_pb[0]_i_1_n_0 ; wire \genblk8[1].left_edge_found_pb[1]_i_1_n_0 ; wire \genblk8[1].left_edge_updated[1]_i_1_n_0 ; wire \genblk8[1].right_edge_found_pb[1]_i_1_n_0 ; wire \genblk8[2].left_edge_found_pb[2]_i_1_n_0 ; wire \genblk8[2].left_edge_updated[2]_i_1_n_0 ; wire \genblk8[2].right_edge_found_pb[2]_i_1_n_0 ; wire \genblk8[3].left_edge_found_pb[3]_i_1_n_0 ; wire \genblk8[3].left_edge_updated[3]_i_1_n_0 ; wire \genblk8[3].right_edge_found_pb[3]_i_1_n_0 ; wire \genblk8[4].left_edge_found_pb[4]_i_1_n_0 ; wire \genblk8[4].left_edge_updated[4]_i_1_n_0 ; wire \genblk8[4].right_edge_found_pb[4]_i_1_n_0 ; wire \genblk8[5].left_edge_found_pb[5]_i_1_n_0 ; wire \genblk8[5].left_edge_updated[5]_i_1_n_0 ; wire \genblk8[5].right_edge_found_pb[5]_i_1_n_0 ; wire \genblk8[6].left_edge_found_pb[6]_i_1_n_0 ; wire \genblk8[6].left_edge_updated[6]_i_1_n_0 ; wire \genblk8[6].right_edge_found_pb[6]_i_1_n_0 ; wire \genblk8[7].left_edge_found_pb[7]_i_1_n_0 ; wire \genblk8[7].left_edge_updated[7]_i_1_n_0 ; wire \genblk8[7].right_edge_found_pb[7]_i_1_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ; wire \genblk9[1].fine_delay_incdec_pb_reg[1] ; wire \genblk9[2].fine_delay_incdec_pb_reg[2] ; wire \genblk9[3].fine_delay_incdec_pb_reg[3] ; wire \genblk9[5].fine_delay_incdec_pb_reg[5] ; wire \genblk9[6].fine_delay_incdec_pb_reg[6] ; wire \genblk9[7].fine_delay_incdec_pb_reg[7] ; wire idel_adj_inc_i_1_n_0; wire idel_pat_detect_valid_r_i_1_n_0; wire idelay_ce; wire idelay_ce_int; wire idelay_ce_r1; wire idelay_inc; wire idelay_inc_int; wire idelay_inc_r1; wire idelay_ld; wire idelay_ld_done_i_1_n_0; wire idelay_ld_i_1_n_0; wire idelay_ld_rst; wire idelay_ld_rst_3; wire idelay_ld_rst_4; wire idelay_ld_rst_5; wire [1:0]\idelay_tap_cnt_r_reg[0][3][0] ; wire ififo_rst_reg; wire ififo_rst_reg_0; wire ififo_rst_reg_1; wire ififo_rst_reg_2; wire [3:0]in0; wire inhibit_edge_detect_r; wire inhibit_edge_detect_r_i_1_n_0; wire init_calib_complete_r_reg; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__0_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__10_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__11_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__12_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__13_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__1_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__2_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__3_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__4_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__8_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__9_n_0; wire init_complete_r_i_1_n_0; wire init_complete_r_timing_i_1_n_0; wire init_complete_r_timing_orig; wire init_dec_done_i_1_n_0; wire init_dqsfound_done_r2; wire init_dqsfound_done_r5; wire init_dqsfound_done_r_i_1_n_0; wire [6:6]init_state_r; wire [7:0]left_edge_updated; wire lim2init_prech_req; wire maint_prescaler_r1; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ; wire \mcGo_r_reg[15] ; wire [35:0]mc_address; wire [8:0]mc_bank; wire [2:0]mc_cas_n; wire [0:0]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_we_n; wire mc_wrdata_en; wire mem_init_done_r; wire [5:0]mem_out; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mpr_dec_cpt_r_i_1_n_0; wire mpr_end_if_reset; wire mpr_last_byte_done; wire mpr_last_byte_done_i_1_n_0; wire mpr_rank_done_r_i_1_n_0; wire mpr_rdlvl_done_r_i_1_n_0; wire mpr_rdlvl_start_r; wire mpr_rnk_done; wire mux_cmd_wren; wire mux_reset_n; wire mux_wrdata_en; wire [0:0]my_empty; wire [0:0]my_empty_6; wire [0:0]my_empty_7; wire [0:0]my_empty_8; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire \my_empty_reg[7] ; wire [71:0]\my_empty_reg[7]_0 ; wire [71:0]\my_empty_reg[7]_1 ; wire [3:0]\my_empty_reg[7]_10 ; wire [7:0]\my_empty_reg[7]_11 ; wire [7:0]\my_empty_reg[7]_12 ; wire [7:0]\my_empty_reg[7]_13 ; wire [7:0]\my_empty_reg[7]_14 ; wire [7:0]\my_empty_reg[7]_15 ; wire [7:0]\my_empty_reg[7]_16 ; wire [7:0]\my_empty_reg[7]_17 ; wire [7:0]\my_empty_reg[7]_18 ; wire [7:0]\my_empty_reg[7]_19 ; wire [71:0]\my_empty_reg[7]_2 ; wire [7:0]\my_empty_reg[7]_20 ; wire [7:0]\my_empty_reg[7]_21 ; wire [7:0]\my_empty_reg[7]_22 ; wire [7:0]\my_empty_reg[7]_23 ; wire [7:0]\my_empty_reg[7]_24 ; wire [7:0]\my_empty_reg[7]_25 ; wire [7:0]\my_empty_reg[7]_26 ; wire [7:0]\my_empty_reg[7]_27 ; wire [7:0]\my_empty_reg[7]_28 ; wire [7:0]\my_empty_reg[7]_29 ; wire [71:0]\my_empty_reg[7]_3 ; wire [7:0]\my_empty_reg[7]_30 ; wire [7:0]\my_empty_reg[7]_31 ; wire [7:0]\my_empty_reg[7]_32 ; wire [7:0]\my_empty_reg[7]_33 ; wire [7:0]\my_empty_reg[7]_34 ; wire [7:0]\my_empty_reg[7]_35 ; wire [7:0]\my_empty_reg[7]_36 ; wire [7:0]\my_empty_reg[7]_37 ; wire [7:0]\my_empty_reg[7]_38 ; wire [7:0]\my_empty_reg[7]_39 ; wire [3:0]\my_empty_reg[7]_4 ; wire [7:0]\my_empty_reg[7]_40 ; wire [7:0]\my_empty_reg[7]_41 ; wire [7:0]\my_empty_reg[7]_42 ; wire [3:0]\my_empty_reg[7]_5 ; wire [3:0]\my_empty_reg[7]_6 ; wire [3:0]\my_empty_reg[7]_7 ; wire [3:0]\my_empty_reg[7]_8 ; wire [3:0]\my_empty_reg[7]_9 ; wire [3:0]\my_full_reg[3] ; wire [1:0]\my_full_reg[3]_0 ; wire new_cnt_dqs_r; wire new_cnt_dqs_r_i_1_n_0; wire no_err_win_detected_latch_i_1_n_0; wire num_samples_done_ind_i_1_n_0; wire num_samples_done_r; wire ocal_last_byte_done; wire ocd_prech_req; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ; wire out; wire p_0_in; wire p_0_in102_in; wire p_0_in10_in; wire p_0_in13_in; wire p_0_in16_in; wire p_0_in1_in; wire p_0_in23_in; wire p_0_in4_in; wire p_0_in7_in; wire p_0_in84_in; wire p_0_in87_in; wire p_0_in90_in; wire p_0_in93_in; wire p_0_in96_in; wire p_0_in99_in; wire [3:2]p_0_in_0; wire p_0_in_2; wire p_0_out; wire p_103_out; wire p_106_out; wire p_119_out; wire p_122_out; wire p_127_out; wire p_130_out; wire p_143_out; wire p_146_out; wire p_154_out; wire p_1_in; wire p_1_in27_in; wire p_1_in50_in; wire p_2_in24_in; wire p_3_in25_in; wire p_81_in; wire p_95_out; wire p_98_out; wire [7:0]pb_detect_edge_done_r; wire pb_found_stable_eye_r52_out; wire pb_found_stable_eye_r56_out; wire pb_found_stable_eye_r60_out; wire pb_found_stable_eye_r64_out; wire pb_found_stable_eye_r68_out; wire pb_found_stable_eye_r72_out; wire pb_found_stable_eye_r76_out; wire pd_out; wire \periodic_rd_generation.periodic_rd_timer_r_reg[1] ; wire \phaser_in_gen.phaser_in_i_12__0_n_0 ; wire \phaser_in_gen.phaser_in_i_12__1_n_0 ; wire \phaser_in_gen.phaser_in_i_12__2_n_0 ; wire \phaser_in_gen.phaser_in_i_12_n_0 ; wire [10:0]\phy_ctl_wd_i1_reg[24] ; wire [33:0]phy_dout; wire phy_if_reset; wire phy_if_reset0__0; wire phy_if_reset_w; wire phy_rddata_en; wire phy_rddata_en_1; wire phy_read_calib; wire phy_write_calib; wire pi_calib_done; wire pi_cnt_dec_i_1_n_0; wire [0:0]pi_cnt_dec_reg; wire [5:0]\pi_counter_read_val_reg[5] ; wire [1:1]pi_dqs_found_all_bank; wire [1:0]pi_dqs_found_all_bank_r; wire [0:0]pi_dqs_found_any_bank; wire \pi_dqs_found_any_bank[0]_i_1_n_0 ; wire pi_dqs_found_done_r1; wire \pi_dqs_found_lanes_r1_reg[0] ; wire \pi_dqs_found_lanes_r1_reg[0]_0 ; wire \pi_dqs_found_lanes_r1_reg[0]_1 ; wire \pi_dqs_found_lanes_r1_reg[0]_2 ; wire \pi_dqs_found_lanes_r1_reg[1] ; wire \pi_dqs_found_lanes_r1_reg[1]_0 ; wire \pi_dqs_found_lanes_r1_reg[1]_1 ; wire \pi_dqs_found_lanes_r1_reg[1]_2 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ; wire \pi_dqs_found_lanes_r1_reg[2] ; wire \pi_dqs_found_lanes_r1_reg[2]_0 ; wire \pi_dqs_found_lanes_r1_reg[2]_1 ; wire \pi_dqs_found_lanes_r1_reg[2]_2 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ; wire \pi_dqs_found_lanes_r1_reg[3] ; wire \pi_dqs_found_lanes_r1_reg[3]_0 ; wire \pi_dqs_found_lanes_r1_reg[3]_1 ; wire \pi_dqs_found_lanes_r1_reg[3]_2 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ; wire pi_dqs_found_rank_done; wire pi_en_stg2_f_timing_reg; wire pi_fine_dly_dec_done; wire \pi_rst_stg1_cal_r_reg[0] ; wire pi_stg2_f_incdec_timing_i_1_n_0; wire pi_stg2_load_timing_i_1_n_0; wire [1:0]pi_stg2_rdlvl_cnt; wire po_cnt_dec_i_1__0_n_0; wire po_cnt_dec_i_1_n_0; wire [0:0]po_cnt_dec_reg; wire po_cnt_inc_i_1_n_0; wire \po_counter_read_val_reg[2] ; wire [5:0]\po_counter_read_val_reg[5] ; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_10 ; wire \po_counter_read_val_reg[8]_11 ; wire \po_counter_read_val_reg[8]_12 ; wire \po_counter_read_val_reg[8]_13 ; wire \po_counter_read_val_reg[8]_14 ; wire \po_counter_read_val_reg[8]_15 ; wire \po_counter_read_val_reg[8]_16 ; wire \po_counter_read_val_reg[8]_17 ; wire \po_counter_read_val_reg[8]_18 ; wire \po_counter_read_val_reg[8]_19 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_20 ; wire \po_counter_read_val_reg[8]_21 ; wire \po_counter_read_val_reg[8]_22 ; wire \po_counter_read_val_reg[8]_23 ; wire \po_counter_read_val_reg[8]_24 ; wire \po_counter_read_val_reg[8]_25 ; wire \po_counter_read_val_reg[8]_26 ; wire \po_counter_read_val_reg[8]_27 ; wire \po_counter_read_val_reg[8]_28 ; wire \po_counter_read_val_reg[8]_29 ; wire \po_counter_read_val_reg[8]_3 ; wire [4:0]\po_counter_read_val_reg[8]_30 ; wire [4:0]\po_counter_read_val_reg[8]_31 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire \po_counter_read_val_reg[8]_6 ; wire \po_counter_read_val_reg[8]_7 ; wire \po_counter_read_val_reg[8]_8 ; wire \po_counter_read_val_reg[8]_9 ; wire po_en_stg23; wire [0:0]po_enstg2_f; wire [2:0]\po_rdval_cnt_reg[8] ; wire po_stg23_incdec; wire [0:0]po_stg2_fincdec; wire [2:2]po_stg2_wrcal_cnt; wire \po_stg2_wrcal_cnt_reg[1] ; wire \po_stg2_wrcal_cnt_reg[1]_0 ; wire \po_stg2_wrcal_cnt_reg[1]_1 ; wire \po_stg2_wrcal_cnt_reg[1]_10 ; wire \po_stg2_wrcal_cnt_reg[1]_11 ; wire \po_stg2_wrcal_cnt_reg[1]_12 ; wire \po_stg2_wrcal_cnt_reg[1]_13 ; wire \po_stg2_wrcal_cnt_reg[1]_14 ; wire \po_stg2_wrcal_cnt_reg[1]_15 ; wire \po_stg2_wrcal_cnt_reg[1]_16 ; wire \po_stg2_wrcal_cnt_reg[1]_17 ; wire \po_stg2_wrcal_cnt_reg[1]_18 ; wire \po_stg2_wrcal_cnt_reg[1]_19 ; wire \po_stg2_wrcal_cnt_reg[1]_2 ; wire \po_stg2_wrcal_cnt_reg[1]_20 ; wire \po_stg2_wrcal_cnt_reg[1]_21 ; wire \po_stg2_wrcal_cnt_reg[1]_22 ; wire \po_stg2_wrcal_cnt_reg[1]_23 ; wire \po_stg2_wrcal_cnt_reg[1]_24 ; wire \po_stg2_wrcal_cnt_reg[1]_25 ; wire \po_stg2_wrcal_cnt_reg[1]_26 ; wire \po_stg2_wrcal_cnt_reg[1]_27 ; wire \po_stg2_wrcal_cnt_reg[1]_28 ; wire \po_stg2_wrcal_cnt_reg[1]_29 ; wire \po_stg2_wrcal_cnt_reg[1]_3 ; wire \po_stg2_wrcal_cnt_reg[1]_30 ; wire \po_stg2_wrcal_cnt_reg[1]_31 ; wire \po_stg2_wrcal_cnt_reg[1]_32 ; wire \po_stg2_wrcal_cnt_reg[1]_33 ; wire \po_stg2_wrcal_cnt_reg[1]_34 ; wire \po_stg2_wrcal_cnt_reg[1]_35 ; wire \po_stg2_wrcal_cnt_reg[1]_36 ; wire \po_stg2_wrcal_cnt_reg[1]_37 ; wire \po_stg2_wrcal_cnt_reg[1]_38 ; wire \po_stg2_wrcal_cnt_reg[1]_39 ; wire \po_stg2_wrcal_cnt_reg[1]_4 ; wire \po_stg2_wrcal_cnt_reg[1]_40 ; wire \po_stg2_wrcal_cnt_reg[1]_41 ; wire \po_stg2_wrcal_cnt_reg[1]_42 ; wire \po_stg2_wrcal_cnt_reg[1]_43 ; wire \po_stg2_wrcal_cnt_reg[1]_44 ; wire \po_stg2_wrcal_cnt_reg[1]_45 ; wire \po_stg2_wrcal_cnt_reg[1]_46 ; wire \po_stg2_wrcal_cnt_reg[1]_47 ; wire \po_stg2_wrcal_cnt_reg[1]_48 ; wire \po_stg2_wrcal_cnt_reg[1]_49 ; wire \po_stg2_wrcal_cnt_reg[1]_5 ; wire \po_stg2_wrcal_cnt_reg[1]_50 ; wire \po_stg2_wrcal_cnt_reg[1]_51 ; wire \po_stg2_wrcal_cnt_reg[1]_52 ; wire \po_stg2_wrcal_cnt_reg[1]_53 ; wire \po_stg2_wrcal_cnt_reg[1]_54 ; wire \po_stg2_wrcal_cnt_reg[1]_55 ; wire \po_stg2_wrcal_cnt_reg[1]_56 ; wire \po_stg2_wrcal_cnt_reg[1]_57 ; wire \po_stg2_wrcal_cnt_reg[1]_58 ; wire \po_stg2_wrcal_cnt_reg[1]_59 ; wire \po_stg2_wrcal_cnt_reg[1]_6 ; wire \po_stg2_wrcal_cnt_reg[1]_60 ; wire \po_stg2_wrcal_cnt_reg[1]_61 ; wire \po_stg2_wrcal_cnt_reg[1]_7 ; wire \po_stg2_wrcal_cnt_reg[1]_8 ; wire \po_stg2_wrcal_cnt_reg[1]_9 ; wire poc_sample_pd; wire \prbs_dqs_cnt_r[0]_i_1_n_0 ; wire \prbs_dqs_cnt_r[1]_i_1_n_0 ; wire \prbs_dqs_cnt_r[2]_i_1_n_0 ; wire prbs_dqs_tap_limit_r_i_1_n_0; wire prbs_found_1st_edge_r_i_1_n_0; wire prbs_last_byte_done; wire prbs_last_byte_done_i_1_n_0; wire prbs_last_byte_done_r; wire prbs_pi_stg2_f_en; wire prbs_pi_stg2_f_incdec; wire prbs_prech_req_r; wire prbs_prech_req_r_i_1_n_0; wire prbs_rdlvl_done_i_1_n_0; wire prbs_rdlvl_done_pulse0; wire prbs_rdlvl_done_r1; wire prbs_rdlvl_start_r; wire prbs_rdlvl_start_r_reg; wire [4:0]prbs_state_r; wire prbs_state_r178_out; wire prbs_tap_en_r; wire prbs_tap_en_r_i_1_n_0; wire prbs_tap_inc_r; wire prbs_tap_inc_r_i_1_n_0; wire prech_done; wire prech_pending_r; wire prech_pending_r_i_1_n_0; wire prech_req; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire rank_done_r_i_1_n_0; wire rd_active_r1; wire rd_active_r2; wire \rd_addr[7]_i_1_n_0 ; wire \rd_byte_data_offset_reg[0]_3 ; wire rd_data_offset_cal_done; wire [3:2]rd_data_offset_ranks_0; wire [3:2]rd_data_offset_ranks_1; wire \rd_mux_sel_r_reg[1] ; wire \rd_mux_sel_r_reg[1]_0 ; wire \rd_mux_sel_r_reg[1]_1 ; wire \rd_mux_sel_r_reg[1]_10 ; wire \rd_mux_sel_r_reg[1]_11 ; wire \rd_mux_sel_r_reg[1]_12 ; wire \rd_mux_sel_r_reg[1]_13 ; wire \rd_mux_sel_r_reg[1]_14 ; wire \rd_mux_sel_r_reg[1]_15 ; wire \rd_mux_sel_r_reg[1]_16 ; wire \rd_mux_sel_r_reg[1]_17 ; wire \rd_mux_sel_r_reg[1]_18 ; wire \rd_mux_sel_r_reg[1]_19 ; wire \rd_mux_sel_r_reg[1]_2 ; wire \rd_mux_sel_r_reg[1]_20 ; wire \rd_mux_sel_r_reg[1]_21 ; wire \rd_mux_sel_r_reg[1]_22 ; wire \rd_mux_sel_r_reg[1]_23 ; wire \rd_mux_sel_r_reg[1]_24 ; wire \rd_mux_sel_r_reg[1]_25 ; wire \rd_mux_sel_r_reg[1]_26 ; wire \rd_mux_sel_r_reg[1]_27 ; wire \rd_mux_sel_r_reg[1]_28 ; wire \rd_mux_sel_r_reg[1]_29 ; wire \rd_mux_sel_r_reg[1]_3 ; wire \rd_mux_sel_r_reg[1]_30 ; wire \rd_mux_sel_r_reg[1]_31 ; wire \rd_mux_sel_r_reg[1]_32 ; wire \rd_mux_sel_r_reg[1]_33 ; wire \rd_mux_sel_r_reg[1]_34 ; wire \rd_mux_sel_r_reg[1]_35 ; wire \rd_mux_sel_r_reg[1]_36 ; wire \rd_mux_sel_r_reg[1]_37 ; wire \rd_mux_sel_r_reg[1]_38 ; wire \rd_mux_sel_r_reg[1]_39 ; wire \rd_mux_sel_r_reg[1]_4 ; wire \rd_mux_sel_r_reg[1]_40 ; wire \rd_mux_sel_r_reg[1]_41 ; wire \rd_mux_sel_r_reg[1]_42 ; wire \rd_mux_sel_r_reg[1]_43 ; wire \rd_mux_sel_r_reg[1]_44 ; wire \rd_mux_sel_r_reg[1]_45 ; wire \rd_mux_sel_r_reg[1]_46 ; wire \rd_mux_sel_r_reg[1]_47 ; wire \rd_mux_sel_r_reg[1]_48 ; wire \rd_mux_sel_r_reg[1]_49 ; wire \rd_mux_sel_r_reg[1]_5 ; wire \rd_mux_sel_r_reg[1]_50 ; wire \rd_mux_sel_r_reg[1]_51 ; wire \rd_mux_sel_r_reg[1]_52 ; wire \rd_mux_sel_r_reg[1]_53 ; wire \rd_mux_sel_r_reg[1]_54 ; wire \rd_mux_sel_r_reg[1]_55 ; wire \rd_mux_sel_r_reg[1]_56 ; wire \rd_mux_sel_r_reg[1]_57 ; wire \rd_mux_sel_r_reg[1]_58 ; wire \rd_mux_sel_r_reg[1]_59 ; wire \rd_mux_sel_r_reg[1]_6 ; wire \rd_mux_sel_r_reg[1]_60 ; wire \rd_mux_sel_r_reg[1]_61 ; wire \rd_mux_sel_r_reg[1]_62 ; wire \rd_mux_sel_r_reg[1]_7 ; wire \rd_mux_sel_r_reg[1]_8 ; wire \rd_mux_sel_r_reg[1]_9 ; wire [37:0]\rd_ptr_reg[3] ; wire [11:0]\rd_ptr_reg[3]_0 ; wire [31:0]\rd_ptr_reg[3]_1 ; wire [63:0]\rd_ptr_reg[3]_2 ; wire [63:0]\rd_ptr_reg[3]_3 ; wire [63:0]\rd_ptr_reg[3]_4 ; wire [63:0]\rd_ptr_reg[3]_5 ; wire \rd_ptr_timing_reg[0] ; wire [33:0]\rd_ptr_timing_reg[0]_0 ; wire [7:0]\rd_ptr_timing_reg[0]_1 ; wire [7:0]\rd_ptr_timing_reg[0]_2 ; wire [3:0]\rd_ptr_timing_reg[0]_3 ; wire [1:0]\rd_ptr_timing_reg[0]_4 ; wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ; wire rdlvl_last_byte_done; wire rdlvl_last_byte_done_int_i_1_n_0; wire rdlvl_pi_incdec; wire rdlvl_pi_incdec_i_1_n_0; wire rdlvl_prech_req; wire rdlvl_rank_done_r_i_1_n_0; wire [14:14]rdlvl_start_dly0_r; wire rdlvl_start_pre; wire rdlvl_start_pre_i_1_n_0; wire rdlvl_stg1_done_int; wire rdlvl_stg1_done_int_i_1_n_0; wire rdlvl_stg1_rank_done; wire rdlvl_stg1_start_i_1_n_0; wire rdlvl_stg1_start_int; wire [2:2]regl_dqs_cnt; wire reset_if; wire reset_if_r8_reg_srl8_n_0; wire reset_if_r9; wire reset_rd_addr; wire reset_rd_addr0; wire reset_rd_addr_i_1_n_0; wire right_edge_found; wire right_edge_found_i_1_n_0; wire right_gain_pb; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire rst_dqs_find; wire rst_dqs_find_i_1_n_0; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [1:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__23_0; wire rstdiv0_sync_r1_reg_rep__23_1; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__25_1; wire rstdiv0_sync_r1_reg_rep__25_2; wire [0:0]rstdiv0_sync_r1_reg_rep__4; wire rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire [0:0]rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire samples_cnt_r; wire \samps_r_reg[9] ; wire sel; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire sr_valid_r108_out; wire stable_cnt1; wire stable_cnt227_in; wire stg1_wr_done; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire store_sr_r_i_1_n_0; wire temp_lmr_done; wire tempmon_pi_f_en_r; wire tempmon_pi_f_inc; wire tempmon_pi_f_inc_r; wire tempmon_sample_en; wire tempmon_sel_pi_incdec; wire u_ddr_phy_init_n_101; wire u_ddr_phy_init_n_102; wire u_ddr_phy_init_n_104; wire u_ddr_phy_init_n_105; wire u_ddr_phy_init_n_106; wire u_ddr_phy_init_n_107; wire u_ddr_phy_init_n_108; wire u_ddr_phy_init_n_109; wire u_ddr_phy_init_n_110; wire u_ddr_phy_init_n_111; wire u_ddr_phy_init_n_114; wire u_ddr_phy_init_n_115; wire u_ddr_phy_init_n_116; wire u_ddr_phy_init_n_117; wire u_ddr_phy_init_n_120; wire u_ddr_phy_init_n_121; wire u_ddr_phy_init_n_122; wire u_ddr_phy_init_n_123; wire u_ddr_phy_init_n_124; wire u_ddr_phy_init_n_125; wire u_ddr_phy_init_n_126; wire u_ddr_phy_init_n_127; wire u_ddr_phy_init_n_18; wire u_ddr_phy_init_n_24; wire u_ddr_phy_init_n_29; wire u_ddr_phy_init_n_31; wire u_ddr_phy_init_n_33; wire u_ddr_phy_init_n_462; wire u_ddr_phy_init_n_464; wire u_ddr_phy_init_n_465; wire u_ddr_phy_init_n_468; wire u_ddr_phy_init_n_469; wire u_ddr_phy_init_n_470; wire u_ddr_phy_init_n_473; wire u_ddr_phy_init_n_474; wire u_ddr_phy_init_n_475; wire u_ddr_phy_init_n_476; wire u_ddr_phy_init_n_477; wire u_ddr_phy_init_n_478; wire u_ddr_phy_init_n_479; wire u_ddr_phy_init_n_480; wire u_ddr_phy_init_n_485; wire u_ddr_phy_init_n_490; wire u_ddr_phy_init_n_496; wire u_ddr_phy_init_n_497; wire u_ddr_phy_init_n_499; wire u_ddr_phy_init_n_500; wire u_ddr_phy_init_n_501; wire u_ddr_phy_init_n_502; wire u_ddr_phy_init_n_784; wire u_ddr_phy_init_n_785; wire u_ddr_phy_init_n_786; wire u_ddr_phy_init_n_790; wire u_ddr_phy_init_n_791; wire u_ddr_phy_init_n_9; wire u_ddr_phy_wrcal_n_100; wire u_ddr_phy_wrcal_n_101; wire u_ddr_phy_wrcal_n_102; wire u_ddr_phy_wrcal_n_103; wire u_ddr_phy_wrcal_n_104; wire u_ddr_phy_wrcal_n_105; wire u_ddr_phy_wrcal_n_106; wire u_ddr_phy_wrcal_n_107; wire u_ddr_phy_wrcal_n_108; wire u_ddr_phy_wrcal_n_109; wire u_ddr_phy_wrcal_n_110; wire u_ddr_phy_wrcal_n_111; wire u_ddr_phy_wrcal_n_112; wire u_ddr_phy_wrcal_n_113; wire u_ddr_phy_wrcal_n_114; wire u_ddr_phy_wrcal_n_115; wire u_ddr_phy_wrcal_n_116; wire u_ddr_phy_wrcal_n_117; wire u_ddr_phy_wrcal_n_118; wire u_ddr_phy_wrcal_n_119; wire u_ddr_phy_wrcal_n_120; wire u_ddr_phy_wrcal_n_4; wire u_ddr_phy_wrcal_n_5; wire u_ddr_phy_wrcal_n_66; wire u_ddr_phy_wrcal_n_67; wire u_ddr_phy_wrcal_n_69; wire u_ddr_phy_wrcal_n_71; wire u_ddr_phy_wrcal_n_73; wire u_ddr_phy_wrcal_n_74; wire u_ddr_phy_wrcal_n_81; wire u_ddr_phy_wrcal_n_82; wire u_ddr_phy_wrcal_n_83; wire u_ddr_phy_wrcal_n_84; wire u_ddr_phy_wrcal_n_85; wire u_ddr_phy_wrcal_n_89; wire u_ddr_phy_wrcal_n_90; wire u_ddr_phy_wrcal_n_91; wire u_ddr_phy_wrcal_n_92; wire u_ddr_phy_wrcal_n_93; wire u_ddr_phy_wrcal_n_94; wire u_ddr_phy_wrcal_n_95; wire u_ddr_phy_wrcal_n_96; wire u_ddr_phy_wrcal_n_97; wire u_ddr_phy_wrcal_n_98; wire u_ddr_prbs_gen_n_0; wire u_ddr_prbs_gen_n_1; wire u_ddr_prbs_gen_n_10; wire u_ddr_prbs_gen_n_100; wire u_ddr_prbs_gen_n_101; wire u_ddr_prbs_gen_n_102; wire u_ddr_prbs_gen_n_103; wire u_ddr_prbs_gen_n_104; wire u_ddr_prbs_gen_n_105; wire u_ddr_prbs_gen_n_106; wire u_ddr_prbs_gen_n_107; wire u_ddr_prbs_gen_n_108; wire u_ddr_prbs_gen_n_109; wire u_ddr_prbs_gen_n_11; wire u_ddr_prbs_gen_n_110; wire u_ddr_prbs_gen_n_111; wire u_ddr_prbs_gen_n_112; wire u_ddr_prbs_gen_n_113; wire u_ddr_prbs_gen_n_114; wire u_ddr_prbs_gen_n_115; wire u_ddr_prbs_gen_n_116; wire u_ddr_prbs_gen_n_117; wire u_ddr_prbs_gen_n_118; wire u_ddr_prbs_gen_n_119; wire u_ddr_prbs_gen_n_12; wire u_ddr_prbs_gen_n_120; wire u_ddr_prbs_gen_n_121; wire u_ddr_prbs_gen_n_13; wire u_ddr_prbs_gen_n_14; wire u_ddr_prbs_gen_n_15; wire u_ddr_prbs_gen_n_16; wire u_ddr_prbs_gen_n_17; wire u_ddr_prbs_gen_n_18; wire u_ddr_prbs_gen_n_19; wire u_ddr_prbs_gen_n_2; wire u_ddr_prbs_gen_n_20; wire u_ddr_prbs_gen_n_21; wire u_ddr_prbs_gen_n_22; wire u_ddr_prbs_gen_n_23; wire u_ddr_prbs_gen_n_24; wire u_ddr_prbs_gen_n_25; wire u_ddr_prbs_gen_n_26; wire u_ddr_prbs_gen_n_27; wire u_ddr_prbs_gen_n_28; wire u_ddr_prbs_gen_n_29; wire u_ddr_prbs_gen_n_3; wire u_ddr_prbs_gen_n_30; wire u_ddr_prbs_gen_n_31; wire u_ddr_prbs_gen_n_32; wire u_ddr_prbs_gen_n_33; wire u_ddr_prbs_gen_n_34; wire u_ddr_prbs_gen_n_35; wire u_ddr_prbs_gen_n_36; wire u_ddr_prbs_gen_n_37; wire u_ddr_prbs_gen_n_38; wire u_ddr_prbs_gen_n_39; wire u_ddr_prbs_gen_n_4; wire u_ddr_prbs_gen_n_40; wire u_ddr_prbs_gen_n_41; wire u_ddr_prbs_gen_n_42; wire u_ddr_prbs_gen_n_43; wire u_ddr_prbs_gen_n_44; wire u_ddr_prbs_gen_n_45; wire u_ddr_prbs_gen_n_46; wire u_ddr_prbs_gen_n_47; wire u_ddr_prbs_gen_n_48; wire u_ddr_prbs_gen_n_49; wire u_ddr_prbs_gen_n_5; wire u_ddr_prbs_gen_n_50; wire u_ddr_prbs_gen_n_51; wire u_ddr_prbs_gen_n_52; wire u_ddr_prbs_gen_n_53; wire u_ddr_prbs_gen_n_54; wire u_ddr_prbs_gen_n_55; wire u_ddr_prbs_gen_n_56; wire u_ddr_prbs_gen_n_57; wire u_ddr_prbs_gen_n_58; wire u_ddr_prbs_gen_n_59; wire u_ddr_prbs_gen_n_6; wire u_ddr_prbs_gen_n_60; wire u_ddr_prbs_gen_n_61; wire u_ddr_prbs_gen_n_62; wire u_ddr_prbs_gen_n_63; wire u_ddr_prbs_gen_n_64; wire u_ddr_prbs_gen_n_65; wire u_ddr_prbs_gen_n_66; wire u_ddr_prbs_gen_n_67; wire u_ddr_prbs_gen_n_68; wire u_ddr_prbs_gen_n_69; wire u_ddr_prbs_gen_n_7; wire u_ddr_prbs_gen_n_70; wire u_ddr_prbs_gen_n_71; wire u_ddr_prbs_gen_n_72; wire u_ddr_prbs_gen_n_73; wire u_ddr_prbs_gen_n_74; wire u_ddr_prbs_gen_n_75; wire u_ddr_prbs_gen_n_76; wire u_ddr_prbs_gen_n_77; wire u_ddr_prbs_gen_n_78; wire u_ddr_prbs_gen_n_79; wire u_ddr_prbs_gen_n_8; wire u_ddr_prbs_gen_n_80; wire u_ddr_prbs_gen_n_81; wire u_ddr_prbs_gen_n_82; wire u_ddr_prbs_gen_n_83; wire u_ddr_prbs_gen_n_84; wire u_ddr_prbs_gen_n_85; wire u_ddr_prbs_gen_n_86; wire u_ddr_prbs_gen_n_87; wire u_ddr_prbs_gen_n_88; wire u_ddr_prbs_gen_n_89; wire u_ddr_prbs_gen_n_9; wire u_ddr_prbs_gen_n_90; wire u_ddr_prbs_gen_n_91; wire u_ddr_prbs_gen_n_92; wire u_ddr_prbs_gen_n_93; wire u_ddr_prbs_gen_n_94; wire u_ddr_prbs_gen_n_95; wire u_ddr_prbs_gen_n_96; wire u_ddr_prbs_gen_n_97; wire u_ddr_prbs_gen_n_98; wire u_ddr_prbs_gen_n_99; wire [2:0]\u_ocd_lim/stg2_tap_cnt_reg ; wire [2:0]\u_ocd_lim/stg3_dec_val00_out ; wire [2:0]\u_ocd_lim/stg3_init_val ; wire [8:2]\u_ocd_po_cntlr/stg2_target_ns ; wire [1:0]wait_cnt_r_reg__0; wire [0:0]wait_cnt_r_reg__0_1; wire wl_edge_detect_valid_r_i_1_n_0; wire [0:0]wl_po_fine_cnt_sel_0; wire [2:1]wl_po_fine_cnt_sel_0__0; wire wl_sm_start; wire wr_level_done_i_1_n_0; wire wr_level_done_r_i_1_n_0; wire wrcal_pat_resume_r; wire wrcal_pat_resume_r_i_1_n_0; wire wrcal_prech_req; wire wrcal_rd_wait; wire wrcal_resume_r; wire wrcal_resume_w; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done_i_2_n_0; wire wrlvl_byte_done; wire wrlvl_byte_redo; wire wrlvl_byte_redo_i_1_n_0; wire wrlvl_byte_redo_r; wire wrlvl_done_r1; wire wrlvl_final_if_rst; wire wrlvl_final_mux; wire wrlvl_final_r; wire wrlvl_rank_done; wire wrlvl_rank_done_r_i_1_n_0; wire [0:0]\zero2fuzz_r_reg[0] ; assign A_1__s_port_ = A_1__s_net_1; (* SOFT_HLUTNM = "soft_lutpair727" *) LUT3 #( .INIT(8'h08)) \A[0]__0_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(byte_sel_cnt), .O(\A[0]__0 )); (* SOFT_HLUTNM = "soft_lutpair726" *) LUT3 #( .INIT(8'h20)) \A[0]__4_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(byte_sel_cnt), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .O(\A[0]__4 )); (* SOFT_HLUTNM = "soft_lutpair726" *) LUT3 #( .INIT(8'h02)) \A[1]__0_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(byte_sel_cnt), .O(\A[1]__0 )); (* SOFT_HLUTNM = "soft_lutpair730" *) LUT2 #( .INIT(4'h2)) \A[1]__3_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(byte_sel_cnt), .O(\A[1]__3 )); (* SOFT_HLUTNM = "soft_lutpair725" *) LUT3 #( .INIT(8'h02)) \A[1]__4_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(byte_sel_cnt), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .O(\A[1]__4_0 )); (* SOFT_HLUTNM = "soft_lutpair729" *) LUT2 #( .INIT(4'h1)) \A[1]_i_1 (.I0(byte_sel_cnt), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .O(\A[1]__4 )); (* SOFT_HLUTNM = "soft_lutpair729" *) LUT2 #( .INIT(4'h4)) \A[1]_i_2 (.I0(byte_sel_cnt), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .O(A_1__s_net_1)); (* SOFT_HLUTNM = "soft_lutpair730" *) LUT1 #( .INIT(2'h1)) \A[2]__1_i_1 (.I0(byte_sel_cnt), .O(\A[2]__1 )); (* SOFT_HLUTNM = "soft_lutpair727" *) LUT3 #( .INIT(8'h07)) \A[2]__2_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(byte_sel_cnt), .O(\A[2]__2 )); LUT5 #( .INIT(32'h000000AB)) burst_addr_r_i_1 (.I0(u_ddr_phy_init_n_476), .I1(u_ddr_phy_init_n_31), .I2(u_ddr_phy_init_n_109), .I3(u_ddr_phy_wrcal_n_82), .I4(rstdiv0_sync_r1_reg_rep__23), .O(burst_addr_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair725" *) LUT3 #( .INIT(8'h40)) \byte_sel_data_map[1]_i_1 (.I0(byte_sel_cnt), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .O(\byte_sel_data_map_reg[1] )); LUT4 #( .INIT(16'hBFB0)) cal2_done_r_i_1 (.I0(u_ddr_phy_wrcal_n_5), .I1(wrcal_sanity_chk), .I2(u_ddr_phy_wrcal_n_117), .I3(cal2_done_r), .O(cal2_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFBABF00008A80)) cal2_if_reset_i_1 (.I0(u_ddr_phy_wrcal_n_120), .I1(u_ddr_phy_wrcal_n_115), .I2(u_ddr_phy_wrcal_n_111), .I3(u_ddr_phy_wrcal_n_114), .I4(u_ddr_phy_wrcal_n_108), .I5(phy_if_reset_w), .O(cal2_if_reset_i_1_n_0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \calib_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ), .Q(\po_rdval_cnt_reg[8] [0]), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \calib_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_99 ), .Q(\po_rdval_cnt_reg[8] [1]), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \calib_sel_reg[3] (.C(CLK), .CE(1'b1), .D(ddr_phy_tempmon_0_n_3), .Q(\po_rdval_cnt_reg[8] [2]), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \calib_zero_inputs_reg[0] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ), .Q(calib_zero_inputs__0), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \calib_zero_inputs_reg[1] (.C(CLK), .CE(1'b1), .D(ddr_phy_tempmon_0_n_4), .Q(calib_zero_inputs), .R(1'b0)); LUT5 #( .INIT(32'hDFBF0820)) ck_po_stg2_f_en_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I4(ck_po_stg2_f_en), .O(ck_po_stg2_f_en_i_1_n_0)); LUT5 #( .INIT(32'hD7BF0020)) ck_po_stg2_f_indec_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I4(ck_po_stg2_f_indec), .O(ck_po_stg2_f_indec_i_1_n_0)); LUT4 #( .INIT(16'hEAAA)) cnt_dllk_zqinit_done_r_i_1 (.I0(cnt_dllk_zqinit_done_r), .I1(cnt_dllk_zqinit_r_reg__0[6]), .I2(u_ddr_phy_init_n_496), .I3(cnt_dllk_zqinit_r_reg__0[7]), .O(cnt_dllk_zqinit_done_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000BA8A8A8A)) cnt_init_af_done_r_i_1 (.I0(cnt_init_af_done_r), .I1(mem_init_done_r), .I2(u_ddr_phy_init_n_110), .I3(cnt_init_af_r[1]), .I4(cnt_init_af_r[0]), .I5(u_ddr_phy_init_n_115), .O(cnt_init_af_done_r_i_1_n_0)); LUT6 #( .INIT(64'h000000000000E222)) cnt_init_mr_done_r_i_1 (.I0(cnt_init_mr_done_r), .I1(temp_lmr_done), .I2(cnt_init_mr_r[0]), .I3(cnt_init_mr_r[1]), .I4(cnt_init_mr_r1), .I5(u_ddr_phy_init_n_115), .O(cnt_init_mr_done_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000AAAABAAA)) cnt_pwron_cke_done_r_i_1 (.I0(cnt_pwron_cke_done_r), .I1(u_ddr_phy_init_n_490), .I2(cnt_pwron_r_reg__0[7]), .I3(cnt_pwron_r_reg__0[1]), .I4(cnt_pwron_r_reg__0[0]), .I5(cnt_pwron_reset_done_r0), .O(cnt_pwron_cke_done_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000FFFF0040)) cnt_pwron_reset_done_r_i_1 (.I0(cnt_pwron_r_reg__0[7]), .I1(cnt_pwron_r_reg__0[5]), .I2(cnt_pwron_r_reg__0[0]), .I3(u_ddr_phy_init_n_485), .I4(cnt_pwron_reset_done_r), .I5(cnt_pwron_reset_done_r0), .O(cnt_pwron_reset_done_r_i_1_n_0)); LUT5 #( .INIT(32'hBAAAAAAA)) cnt_txpr_done_r_i_1 (.I0(cnt_txpr_done_r), .I1(u_ddr_phy_init_n_500), .I2(cnt_txpr_r_reg__0[2]), .I3(cnt_txpr_r_reg__0[0]), .I4(cnt_txpr_r_reg__0[1]), .O(cnt_txpr_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFB00000020)) complex_init_pi_dec_done_r_i_1 (.I0(prbs_state_r[4]), .I1(prbs_state_r[3]), .I2(prbs_state_r[0]), .I3(prbs_state_r[2]), .I4(prbs_state_r[1]), .I5(complex_init_pi_dec_done), .O(complex_init_pi_dec_done_r_i_1_n_0)); LUT6 #( .INIT(64'h4474FFFF44740000)) complex_pi_incdec_done_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ), .I1(prbs_state_r[0]), .I2(cnt_wait_state), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ), .I5(complex_pi_incdec_done), .O(complex_pi_incdec_done_i_1_n_0)); LUT4 #( .INIT(16'h00CE)) ddr2_pre_flag_r_i_1 (.I0(u_ddr_phy_init_n_29), .I1(temp_lmr_done), .I2(u_ddr_phy_init_n_479), .I3(u_ddr_phy_init_n_115), .O(ddr2_pre_flag_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000FFFF70F0)) ddr2_refresh_flag_r_i_1 (.I0(u_ddr_phy_init_n_480), .I1(cnt_cmd_done_r), .I2(ddr2_refresh_flag_r), .I3(cnt_init_mr_done_r), .I4(cnt_init_mr_r1), .I5(u_ddr_phy_init_n_115), .O(ddr2_refresh_flag_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair724" *) LUT3 #( .INIT(8'hAC)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/d_out (.I0(app_zq_r_reg), .I1(\rd_ptr_reg[3]_0 [3]), .I2(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [3])); ddr3_ifmig_7series_v4_0_ddr_phy_prbs_rdlvl \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl (.A(A), .\A[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .\A[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .\A[1]_1 (\A[1]_0 ), .\A[1]_10 (\A[1]_9 ), .\A[1]_11 (\A[1]_10 ), .\A[1]_12 (\A[1]_11 ), .\A[1]_13 (\A[1]_12 ), .\A[1]_14 (\A[1]_13 ), .\A[1]_15 (\A[1]_14 ), .\A[1]_16 (\A[1]_15 ), .\A[1]_17 (\A[1]_16 ), .\A[1]_18 (\A[1]_17 ), .\A[1]_19 (\A[1]_18 ), .\A[1]_2 (\A[1]_1 ), .\A[1]_20 (\A[1]_19 ), .\A[1]_21 (\A[1]_20 ), .\A[1]_22 (\A[1]_21 ), .\A[1]_23 (\A[1]_22 ), .\A[1]_24 (\A[1]_23 ), .\A[1]_25 (\A[1]_24 ), .\A[1]_26 (\A[1]_25 ), .\A[1]_27 (\A[1]_26 ), .\A[1]_28 (\A[1]_27 ), .\A[1]_29 (\A[1]_28 ), .\A[1]_3 (\A[1]_2 ), .\A[1]_30 (\A[1]_29 ), .\A[1]_31 (\A[1]_30 ), .\A[1]_32 (\A[1]_31 ), .\A[1]_33 (\A[1]_32 ), .\A[1]_34 (\A[1]_33 ), .\A[1]_35 (\A[1]_34 ), .\A[1]_36 (\A[1]_35 ), .\A[1]_37 (\A[1]_36 ), .\A[1]_38 (\A[1]_37 ), .\A[1]_39 (\A[1]_38 ), .\A[1]_4 (\A[1]_3 ), .\A[1]_40 (\A[1]_39 ), .\A[1]_41 (\A[1]_40 ), .\A[1]_42 (\A[1]_41 ), .\A[1]_43 (\A[1]_42 ), .\A[1]_44 (\A[1]_43 ), .\A[1]_45 (\A[1]_44 ), .\A[1]_46 (\A[1]_45 ), .\A[1]_47 (\A[1]_46 ), .\A[1]_48 (\A[1]_47 ), .\A[1]_49 (\A[1]_48 ), .\A[1]_5 (\A[1]_4 ), .\A[1]_50 (\A[1]_49 ), .\A[1]_51 (\A[1]_50 ), .\A[1]_52 (\A[1]_51 ), .\A[1]_53 (\A[1]_52 ), .\A[1]_54 (\A[1]_53 ), .\A[1]_55 (\A[1]_54 ), .\A[1]_56 (\A[1]_55 ), .\A[1]_57 (\A[1]_56 ), .\A[1]_58 (\A[1]_57 ), .\A[1]_59 (\A[1]_58 ), .\A[1]_6 (\A[1]_5 ), .\A[1]_60 (\A[1]_59 ), .\A[1]_61 (\A[1]_60 ), .\A[1]_62 (\A[1]_61 ), .\A[1]_63 (\A[1]_62 ), .\A[1]_64 (\A[1]_63 ), .\A[1]_7 (\A[1]_6 ), .\A[1]_8 (\A[1]_7 ), .\A[1]_9 (\A[1]_8 ), .\A[2]__2 (\A[2]__2_0 ), .CLK(CLK), .D(left_edge_updated), .E(samples_cnt_r), .Q(prbs_state_r), .SR(SR), .bit_cnt(bit_cnt), .\calib_sel_reg[3] (\po_rdval_cnt_reg[8] [2]), .\calib_sel_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ), .\calib_sel_reg[3]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ), .\calib_sel_reg[3]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ), .cnt_wait_state(cnt_wait_state), .compare_err_latch_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ), .complex_act_start(complex_act_start), .complex_init_pi_dec_done(complex_init_pi_dec_done), .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr), .complex_oclkdelay_calib_done_r1_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .complex_pi_incdec_done(complex_pi_incdec_done), .complex_pi_incdec_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ), .complex_pi_incdec_done_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .\dec_cnt_reg[0]_0 (fine_dly_error_i_1_n_0), .\dout_o_reg[0] (u_ddr_prbs_gen_n_114), .\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_115), .\dout_o_reg[0]_1 (u_ddr_prbs_gen_n_116), .\dout_o_reg[0]_2 (u_ddr_prbs_gen_n_117), .\dout_o_reg[0]_3 (u_ddr_prbs_gen_n_118), .\dout_o_reg[0]_4 (u_ddr_prbs_gen_n_119), .\dout_o_reg[0]_5 (u_ddr_prbs_gen_n_120), .\dout_o_reg[0]_6 (u_ddr_prbs_gen_n_121), .\dout_o_reg[1] (u_ddr_prbs_gen_n_106), .\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_107), .\dout_o_reg[1]_1 (u_ddr_prbs_gen_n_108), .\dout_o_reg[1]_2 (u_ddr_prbs_gen_n_109), .\dout_o_reg[1]_3 (u_ddr_prbs_gen_n_110), .\dout_o_reg[1]_4 (u_ddr_prbs_gen_n_111), .\dout_o_reg[1]_5 (u_ddr_prbs_gen_n_112), .\dout_o_reg[1]_6 (u_ddr_prbs_gen_n_113), .\dout_o_reg[2] (u_ddr_prbs_gen_n_98), .\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_99), .\dout_o_reg[2]_1 (u_ddr_prbs_gen_n_100), .\dout_o_reg[2]_2 (u_ddr_prbs_gen_n_101), .\dout_o_reg[2]_3 (u_ddr_prbs_gen_n_102), .\dout_o_reg[2]_4 (u_ddr_prbs_gen_n_103), .\dout_o_reg[2]_5 (u_ddr_prbs_gen_n_104), .\dout_o_reg[2]_6 (u_ddr_prbs_gen_n_105), .\dout_o_reg[3] (u_ddr_prbs_gen_n_90), .\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_91), .\dout_o_reg[3]_1 (u_ddr_prbs_gen_n_92), .\dout_o_reg[3]_2 (u_ddr_prbs_gen_n_93), .\dout_o_reg[3]_3 (u_ddr_prbs_gen_n_94), .\dout_o_reg[3]_4 (u_ddr_prbs_gen_n_95), .\dout_o_reg[3]_5 (u_ddr_prbs_gen_n_96), .\dout_o_reg[3]_6 (u_ddr_prbs_gen_n_97), .\dout_o_reg[4] (u_ddr_prbs_gen_n_82), .\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_83), .\dout_o_reg[4]_1 (u_ddr_prbs_gen_n_84), .\dout_o_reg[4]_2 (u_ddr_prbs_gen_n_85), .\dout_o_reg[4]_3 (u_ddr_prbs_gen_n_86), .\dout_o_reg[4]_4 (u_ddr_prbs_gen_n_87), .\dout_o_reg[4]_5 (u_ddr_prbs_gen_n_88), .\dout_o_reg[4]_6 (u_ddr_prbs_gen_n_89), .\dout_o_reg[5] (u_ddr_prbs_gen_n_74), .\dout_o_reg[5]_0 (u_ddr_prbs_gen_n_75), .\dout_o_reg[5]_1 (u_ddr_prbs_gen_n_76), .\dout_o_reg[5]_2 (u_ddr_prbs_gen_n_77), .\dout_o_reg[5]_3 (u_ddr_prbs_gen_n_78), .\dout_o_reg[5]_4 (u_ddr_prbs_gen_n_79), .\dout_o_reg[5]_5 (u_ddr_prbs_gen_n_80), .\dout_o_reg[5]_6 (u_ddr_prbs_gen_n_81), .\dout_o_reg[6] (u_ddr_prbs_gen_n_66), .\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_67), .\dout_o_reg[6]_1 (u_ddr_prbs_gen_n_68), .\dout_o_reg[6]_2 (u_ddr_prbs_gen_n_69), .\dout_o_reg[6]_3 (u_ddr_prbs_gen_n_70), .\dout_o_reg[6]_4 (u_ddr_prbs_gen_n_71), .\dout_o_reg[6]_5 (u_ddr_prbs_gen_n_72), .\dout_o_reg[6]_6 (u_ddr_prbs_gen_n_73), .\dout_o_reg[7] (u_ddr_prbs_gen_n_58), .\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_59), .\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_60), .\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_61), .\dout_o_reg[7]_3 (u_ddr_prbs_gen_n_62), .\dout_o_reg[7]_4 (u_ddr_prbs_gen_n_63), .\dout_o_reg[7]_5 (u_ddr_prbs_gen_n_64), .\dout_o_reg[7]_6 (u_ddr_prbs_gen_n_65), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .\fine_delay_mod_reg[20] (\fine_delay_mod_reg[20] ), .\fine_delay_mod_reg[26] (\fine_delay_mod_reg[26] ), .\fine_delay_mod_reg[5] (\fine_delay_mod_reg[5] ), .fine_delay_sel_r_reg(fine_delay_sel_r_reg), .fine_delay_sel_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ), .fine_delay_sel_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ), .fine_dly_error_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ), .fine_dly_error_reg_1(prbs_rdlvl_done_i_1_n_0), .\genblk8[0].left_edge_found_pb_reg[0]_0 (\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ), .\genblk8[0].left_edge_updated_reg[0]_0 (\genblk8[0].left_edge_updated[0]_i_1_n_0 ), .\genblk8[0].left_loss_pb_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ), .\genblk8[0].left_loss_pb_reg[0]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .\genblk8[0].right_edge_found_pb_reg[0]_0 (\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ), .\genblk8[0].right_edge_pb_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ), .\genblk8[0].right_edge_pb_reg[0]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ), .\genblk8[1].left_edge_found_pb_reg[1]_0 (\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ), .\genblk8[1].left_edge_updated_reg[1]_0 (\genblk8[1].left_edge_updated[1]_i_1_n_0 ), .\genblk8[1].left_loss_pb_reg[6]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ), .\genblk8[1].right_edge_found_pb_reg[1]_0 (\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ), .\genblk8[1].right_edge_pb_reg[6]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ), .\genblk8[2].left_edge_found_pb_reg[2]_0 (\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ), .\genblk8[2].left_edge_updated_reg[2]_0 (\genblk8[2].left_edge_updated[2]_i_1_n_0 ), .\genblk8[2].left_loss_pb_reg[12]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ), .\genblk8[2].right_edge_found_pb_reg[2]_0 (\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ), .\genblk8[2].right_edge_pb_reg[12]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ), .\genblk8[2].right_edge_pb_reg[12]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ), .\genblk8[2].right_edge_pb_reg[12]_2 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .\genblk8[3].left_edge_found_pb_reg[3]_0 (\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ), .\genblk8[3].left_edge_updated_reg[3]_0 (\genblk8[3].left_edge_updated[3]_i_1_n_0 ), .\genblk8[3].left_loss_pb_reg[18]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ), .\genblk8[3].right_edge_found_pb_reg[3]_0 (\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ), .\genblk8[3].right_edge_pb_reg[18]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ), .\genblk8[4].left_edge_found_pb_reg[4]_0 (\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ), .\genblk8[4].left_edge_updated_reg[4]_0 (\genblk8[4].left_edge_updated[4]_i_1_n_0 ), .\genblk8[4].left_loss_pb_reg[24]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ), .\genblk8[4].right_edge_found_pb_reg[4]_0 (\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ), .\genblk8[4].right_edge_pb_reg[24]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ), .\genblk8[5].left_edge_found_pb_reg[5]_0 (\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ), .\genblk8[5].left_edge_updated_reg[5]_0 (\genblk8[5].left_edge_updated[5]_i_1_n_0 ), .\genblk8[5].left_loss_pb_reg[30]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ), .\genblk8[5].right_edge_found_pb_reg[5]_0 (\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ), .\genblk8[5].right_edge_pb_reg[30]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ), .\genblk8[5].right_edge_pb_reg[30]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ), .\genblk8[5].right_gain_pb_reg[30]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .\genblk8[6].left_edge_found_pb_reg[6]_0 (\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ), .\genblk8[6].left_edge_updated_reg[6]_0 (\genblk8[6].left_edge_updated[6]_i_1_n_0 ), .\genblk8[6].left_loss_pb_reg[36]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ), .\genblk8[6].right_edge_found_pb_reg[6]_0 (\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ), .\genblk8[6].right_edge_pb_reg[36]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ), .\genblk8[7].left_edge_found_pb_reg[7]_0 (\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ), .\genblk8[7].left_edge_updated_reg[7]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .\genblk8[7].left_edge_updated_reg[7]_1 (\genblk8[7].left_edge_updated[7]_i_1_n_0 ), .\genblk8[7].left_loss_pb_reg[42]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ), .\genblk8[7].right_edge_found_pb_reg[7]_0 (\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ), .\genblk8[7].right_edge_pb_reg[42]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ), .\genblk8[7].right_edge_pb_reg[42]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .\genblk9[0].fine_delay_incdec_pb_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ), .\genblk9[1].fine_delay_incdec_pb_reg[1]_0 (\genblk9[1].fine_delay_incdec_pb_reg[1] ), .\genblk9[2].fine_delay_incdec_pb_reg[2]_0 (\genblk9[2].fine_delay_incdec_pb_reg[2] ), .\genblk9[3].fine_delay_incdec_pb_reg[3]_0 (\genblk9[3].fine_delay_incdec_pb_reg[3] ), .\genblk9[5].fine_delay_incdec_pb_reg[5]_0 (\genblk9[5].fine_delay_incdec_pb_reg[5] ), .\genblk9[6].fine_delay_incdec_pb_reg[6]_0 (\genblk9[6].fine_delay_incdec_pb_reg[6] ), .\genblk9[7].fine_delay_incdec_pb_reg[7]_0 (\genblk9[7].fine_delay_incdec_pb_reg[7] ), .\init_state_r_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ), .\init_state_r_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ), .\init_state_r_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ), .\init_state_r_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ), .\largest_left_edge_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ), .\match_flag_or_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ), .new_cnt_dqs_r(new_cnt_dqs_r), .new_cnt_dqs_r_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ), .new_cnt_dqs_r_reg_1(prbs_dqs_tap_limit_r_i_1_n_0), .no_err_win_detected_latch_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ), .no_err_win_detected_latch_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ), .no_err_win_detected_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ), .no_err_win_detected_reg_1(right_edge_found_i_1_n_0), .\num_refresh_reg[1] (u_ddr_phy_init_n_117), .num_samples_done_ind_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ), .num_samples_done_r(num_samples_done_r), .ocal_last_byte_done(ocal_last_byte_done), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .\oclkdelay_ref_cnt_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ), .\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116), .p_103_out(p_103_out), .p_106_out(p_106_out), .p_119_out(p_119_out), .p_122_out(p_122_out), .p_127_out(p_127_out), .p_130_out(p_130_out), .p_143_out(p_143_out), .p_146_out(p_146_out), .p_154_out(p_154_out), .p_95_out(p_95_out), .p_98_out(p_98_out), .\pi_counter_read_val_reg[5] ({\pi_counter_read_val_reg[5] [5],\pi_counter_read_val_reg[5] [3],\pi_counter_read_val_reg[5] [1:0]}), .pi_en_stg2_f_timing_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ), .\prbs_dec_tap_cnt_reg[1]_0 ({dec_cnt_reg[5],dec_cnt_reg[0]}), .\prbs_dqs_cnt_r_reg[0]_0 (\prbs_dqs_cnt_r[1]_i_1_n_0 ), .\prbs_dqs_cnt_r_reg[0]_1 (\prbs_dqs_cnt_r[0]_i_1_n_0 ), .\prbs_dqs_cnt_r_reg[0]_2 (\prbs_dqs_cnt_r[2]_i_1_n_0 ), .\prbs_dqs_cnt_r_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .\prbs_dqs_cnt_r_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ), .prbs_found_1st_edge_r_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ), .prbs_found_1st_edge_r_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ), .prbs_last_byte_done(prbs_last_byte_done), .prbs_last_byte_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ), .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en), .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec), .prbs_prech_req_r(prbs_prech_req_r), .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0), .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1), .prbs_rdlvl_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ), .prbs_rdlvl_done_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ), .prbs_rdlvl_start_r(prbs_rdlvl_start_r), .prbs_rdlvl_start_reg(prbs_rdlvl_start_r_reg), .prbs_rdlvl_start_reg_0(u_ddr_phy_init_n_127), .prbs_state_r178_out(prbs_state_r178_out), .\prbs_state_r_reg[0]_0 (fine_delay_sel_i_1_n_0), .\prbs_state_r_reg[0]_1 (prbs_tap_inc_r_i_1_n_0), .\prbs_state_r_reg[0]_2 (prbs_tap_en_r_i_1_n_0), .\prbs_state_r_reg[0]_3 (prbs_last_byte_done_i_1_n_0), .\prbs_state_r_reg[0]_4 (complex_pi_incdec_done_i_1_n_0), .\prbs_state_r_reg[3]_0 (prbs_found_1st_edge_r_i_1_n_0), .\prbs_state_r_reg[3]_1 (no_err_win_detected_latch_i_1_n_0), .\prbs_state_r_reg[4]_0 (new_cnt_dqs_r_i_1_n_0), .\prbs_state_r_reg[4]_1 (num_samples_done_ind_i_1_n_0), .\prbs_state_r_reg[4]_2 (reset_rd_addr_i_1_n_0), .\prbs_state_r_reg[4]_3 (complex_init_pi_dec_done_r_i_1_n_0), .prbs_tap_en_r(prbs_tap_en_r), .prbs_tap_en_r_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ), .prbs_tap_inc_r(prbs_tap_inc_r), .prbs_tap_inc_r_reg_0(pi_stg2_f_incdec_timing_i_1_n_0), .prech_done(prech_done), .prech_done_reg(prbs_prech_req_r_i_1_n_0), .prech_req_r_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ), .\rd_victim_sel_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ), .\rd_victim_sel_reg[2]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ), .\rd_victim_sel_reg[2]_2 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ), .\rd_victim_sel_reg[2]_3 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ), .\rdlvl_cpt_tap_cnt_reg[5]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ), .\rdlvl_cpt_tap_cnt_reg[5]_1 ({\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }), .rdlvl_last_byte_done(rdlvl_last_byte_done), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_start_int(rdlvl_stg1_start_int), .reset_rd_addr(reset_rd_addr), .reset_rd_addr0(reset_rd_addr0), .right_edge_found(right_edge_found), .right_edge_found_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ), .right_edge_found_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ), .right_gain_pb(right_gain_pb), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\stage_cnt_reg[1]_0 (\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ), .\stg1_wr_rd_cnt_reg[3] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .wrlvl_final_mux(wrlvl_final_mux)); ddr3_ifmig_7series_v4_0_ddr_phy_rdlvl \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl (.CLK(CLK), .COUNTERLOADVAL(COUNTERLOADVAL), .D({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }), .E(u_ddr_phy_init_n_465), .\FSM_sequential_cal1_state_r_reg[1]_0 (rdlvl_pi_incdec_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[2]_0 (idel_adj_inc_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[3]_0 (mpr_dec_cpt_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_0 (idel_pat_detect_valid_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_1 (mpr_last_byte_done_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_2 (mpr_rank_done_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_3 (rdlvl_rank_done_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_4 (rdlvl_last_byte_done_int_i_1_n_0), .Q(calib_zero_inputs__0), .SR(SR), .cal1_cnt_cpt_r1(cal1_cnt_cpt_r1), .cal1_dq_idel_ce_reg_0(u_ddr_phy_wrcal_n_89), .cal1_state_r1535_out(cal1_state_r1535_out), .cal1_wait_r(cal1_wait_r), .calib_in_common(calib_in_common), .\calib_sel_reg[3] (\po_rdval_cnt_reg[8] ), .\calib_sel_reg[3]_0 ({\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }), .cmd_delay_start0(cmd_delay_start0), .\cnt_idel_dec_cpt_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ), .cnt_init_af_done_r(cnt_init_af_done_r), .complex_ocal_ref_req(complex_ocal_ref_req), .detect_edge_done_r(detect_edge_done_r), .\dout_o_reg[6] (u_ddr_prbs_gen_n_70), .\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_66), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .dqs_found_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ), .dqs_found_prech_req(dqs_found_prech_req), .dqs_po_dec_done(dqs_po_dec_done), .dqs_po_dec_done_r2(dqs_po_dec_done_r2), .first_wrcal_pat_r(first_wrcal_pat_r), .found_edge_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ), .found_edge_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ), .found_edge_r_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ), .found_edge_r_reg_3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ), .found_edge_r_reg_4(found_first_edge_r_i_1_n_0), .found_first_edge_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ), .found_stable_eye_last_r(found_stable_eye_last_r), .found_stable_eye_last_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ), .found_stable_eye_last_r_reg_1(found_second_edge_r_i_1_n_0), .found_stable_eye_r_reg_0(found_stable_eye_last_r_i_1_n_0), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ), .\gen_byte_sel_div1.calib_in_common_reg (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\phaser_in_gen.phaser_in_i_12_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\phaser_in_gen.phaser_in_i_12__0_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\phaser_in_gen.phaser_in_i_12__1_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\phaser_in_gen.phaser_in_i_12__2_n_0 ), .\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ), .\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 (\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ), .\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 (\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ), .\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ), .\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ), .\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 (\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ), .\gen_track_left_edge[0].pb_found_stable_eye_r_reg (\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ), .\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ), .\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ), .\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 (\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ), .\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ), .\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 (\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ), .\gen_track_left_edge[1].pb_found_stable_eye_r_reg (\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ), .\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 (\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ), .\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ), .\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 (\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ), .\gen_track_left_edge[2].pb_found_stable_eye_r_reg (\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ), .\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 (\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ), .\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ), .\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 (\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ), .\gen_track_left_edge[3].pb_found_stable_eye_r_reg (\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ), .\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 (\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ), .\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ), .\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ), .\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 (\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ), .\gen_track_left_edge[4].pb_found_stable_eye_r_reg (\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ), .\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 (\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ), .\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ), .\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 (\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ), .\gen_track_left_edge[5].pb_found_stable_eye_r_reg (\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ), .\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 (\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ), .\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ), .\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ), .\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 (\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ), .\gen_track_left_edge[6].pb_found_stable_eye_r_reg (\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ), .\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 (\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ), .\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ), .\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ), .\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 (\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ), .\gen_track_left_edge[7].pb_found_stable_eye_r_reg (\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ), .\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ), .\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .idel_adj_inc_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ), .idel_adj_inc_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ), .idel_adj_inc_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ), .\idel_dec_cnt_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ), .idelay_ce_int(idelay_ce_int), .idelay_inc_int(idelay_inc_int), .\init_state_r_reg[0] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ), .\init_state_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ), .\init_state_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ), .\init_state_r_reg[0]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ), .\init_state_r_reg[0]_3 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ), .\init_state_r_reg[0]_4 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ), .\init_state_r_reg[1] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ), .\init_state_r_reg[1]_0 ({u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}), .\init_state_r_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ), .\init_state_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ), .\init_state_r_reg[2]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ), .\init_state_r_reg[2]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ), .\init_state_r_reg[3] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ), .\init_state_r_reg[3]_0 (u_ddr_phy_init_n_111), .\init_state_r_reg[4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ), .\init_state_r_reg[5] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ), .\init_state_r_reg[5]_0 (u_ddr_phy_init_n_474), .mem_init_done_r(mem_init_done_r), .mpr_dec_cpt_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ), .mpr_dec_cpt_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ), .mpr_last_byte_done(mpr_last_byte_done), .mpr_last_byte_done_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ), .mpr_rank_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ), .mpr_rank_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ), .mpr_rd_rise0_prev_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ), .mpr_rd_rise0_prev_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ), .mpr_rdlvl_done_r1_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .mpr_rdlvl_done_r_reg_0(mpr_rdlvl_done_r_i_1_n_0), .mpr_rdlvl_done_r_reg_1(rdlvl_stg1_done_int_i_1_n_0), .mpr_rdlvl_start_r(mpr_rdlvl_start_r), .mpr_rdlvl_start_reg(u_ddr_phy_init_n_464), .mpr_rnk_done(mpr_rnk_done), .mpr_valid_r1_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ), .mpr_valid_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ), .\num_refresh_reg[1] (u_ddr_phy_init_n_117), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116), .out({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 }), .p_0_in(p_0_in), .p_0_in102_in(p_0_in102_in), .p_0_in10_in(p_0_in10_in), .p_0_in13_in(p_0_in13_in), .p_0_in16_in(p_0_in16_in), .p_0_in1_in(p_0_in1_in), .p_0_in4_in(p_0_in4_in), .p_0_in7_in(p_0_in7_in), .p_0_in84_in(p_0_in84_in), .p_0_in87_in(p_0_in87_in), .p_0_in90_in(p_0_in90_in), .p_0_in93_in(p_0_in93_in), .p_0_in96_in(p_0_in96_in), .p_0_in99_in(p_0_in99_in), .pb_detect_edge_done_r(pb_detect_edge_done_r), .pb_found_stable_eye_r52_out(pb_found_stable_eye_r52_out), .pb_found_stable_eye_r56_out(pb_found_stable_eye_r56_out), .pb_found_stable_eye_r60_out(pb_found_stable_eye_r60_out), .pb_found_stable_eye_r64_out(pb_found_stable_eye_r64_out), .pb_found_stable_eye_r68_out(pb_found_stable_eye_r68_out), .pb_found_stable_eye_r72_out(pb_found_stable_eye_r72_out), .pb_found_stable_eye_r76_out(pb_found_stable_eye_r76_out), .phy_rddata_en_1(phy_rddata_en_1), .pi_cnt_dec_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ), .pi_cnt_dec_reg_1(pi_cnt_dec_reg), .\pi_counter_read_val_reg[5] ({\pi_counter_read_val_reg[5] [5:4],\pi_counter_read_val_reg[5] [2:0]}), .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0]_0 ), .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_1 ), .\pi_dqs_found_lanes_r1_reg[0]_1 (\pi_dqs_found_lanes_r1_reg[0]_2 ), .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[1]_0 ), .\pi_dqs_found_lanes_r1_reg[1]_0 (\pi_dqs_found_lanes_r1_reg[1]_1 ), .\pi_dqs_found_lanes_r1_reg[1]_1 (\pi_dqs_found_lanes_r1_reg[1]_2 ), .\pi_dqs_found_lanes_r1_reg[1]_2 (\pi_dqs_found_lanes_r1_reg[1]_3 ), .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2]_0 ), .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_1 ), .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_2 ), .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_3 ), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3]_0 ), .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_1 ), .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_2 ), .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_3 ), .pi_en_stg2_f_timing_reg_0(pi_en_stg2_f_timing_reg), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .\pi_rdval_cnt_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ), .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt), .\pi_stg2_reg_l_timing_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ), .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_85), .\po_stg2_wrcal_cnt_reg[1] (\idelay_tap_cnt_r_reg[0][3][0] [1]), .\po_stg2_wrcal_cnt_reg[2] (u_ddr_phy_wrcal_n_107), .\prbs_dqs_cnt_r_reg[2] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ), .prbs_last_byte_done_r(prbs_last_byte_done_r), .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en), .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prbs_rdlvl_done_reg_rep_0(u_ddr_phy_init_n_497), .prbs_rdlvl_done_reg_rep_1(u_ddr_phy_wrcal_n_94), .prbs_rdlvl_prech_req_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ), .prech_done(prech_done), .prech_req(prech_req), .\rd_mux_sel_r_reg[1]_0 (\rd_mux_sel_r_reg[1] ), .\rd_mux_sel_r_reg[1]_1 (\rd_mux_sel_r_reg[1]_0 ), .\rd_mux_sel_r_reg[1]_10 (\rd_mux_sel_r_reg[1]_9 ), .\rd_mux_sel_r_reg[1]_11 (\rd_mux_sel_r_reg[1]_10 ), .\rd_mux_sel_r_reg[1]_12 (\rd_mux_sel_r_reg[1]_11 ), .\rd_mux_sel_r_reg[1]_13 (\rd_mux_sel_r_reg[1]_12 ), .\rd_mux_sel_r_reg[1]_14 (\rd_mux_sel_r_reg[1]_13 ), .\rd_mux_sel_r_reg[1]_15 (\rd_mux_sel_r_reg[1]_14 ), .\rd_mux_sel_r_reg[1]_16 (\rd_mux_sel_r_reg[1]_15 ), .\rd_mux_sel_r_reg[1]_17 (\rd_mux_sel_r_reg[1]_16 ), .\rd_mux_sel_r_reg[1]_18 (\rd_mux_sel_r_reg[1]_17 ), .\rd_mux_sel_r_reg[1]_19 (\rd_mux_sel_r_reg[1]_18 ), .\rd_mux_sel_r_reg[1]_2 (\rd_mux_sel_r_reg[1]_1 ), .\rd_mux_sel_r_reg[1]_20 (\rd_mux_sel_r_reg[1]_19 ), .\rd_mux_sel_r_reg[1]_21 (\rd_mux_sel_r_reg[1]_20 ), .\rd_mux_sel_r_reg[1]_22 (\rd_mux_sel_r_reg[1]_21 ), .\rd_mux_sel_r_reg[1]_23 (\rd_mux_sel_r_reg[1]_22 ), .\rd_mux_sel_r_reg[1]_24 (\rd_mux_sel_r_reg[1]_23 ), .\rd_mux_sel_r_reg[1]_25 (\rd_mux_sel_r_reg[1]_24 ), .\rd_mux_sel_r_reg[1]_26 (\rd_mux_sel_r_reg[1]_25 ), .\rd_mux_sel_r_reg[1]_27 (\rd_mux_sel_r_reg[1]_26 ), .\rd_mux_sel_r_reg[1]_28 (\rd_mux_sel_r_reg[1]_27 ), .\rd_mux_sel_r_reg[1]_29 (\rd_mux_sel_r_reg[1]_28 ), .\rd_mux_sel_r_reg[1]_3 (\rd_mux_sel_r_reg[1]_2 ), .\rd_mux_sel_r_reg[1]_30 (\rd_mux_sel_r_reg[1]_29 ), .\rd_mux_sel_r_reg[1]_31 (\rd_mux_sel_r_reg[1]_30 ), .\rd_mux_sel_r_reg[1]_32 (\rd_mux_sel_r_reg[1]_31 ), .\rd_mux_sel_r_reg[1]_33 (\rd_mux_sel_r_reg[1]_32 ), .\rd_mux_sel_r_reg[1]_34 (\rd_mux_sel_r_reg[1]_33 ), .\rd_mux_sel_r_reg[1]_35 (\rd_mux_sel_r_reg[1]_34 ), .\rd_mux_sel_r_reg[1]_36 (\rd_mux_sel_r_reg[1]_35 ), .\rd_mux_sel_r_reg[1]_37 (\rd_mux_sel_r_reg[1]_36 ), .\rd_mux_sel_r_reg[1]_38 (\rd_mux_sel_r_reg[1]_37 ), .\rd_mux_sel_r_reg[1]_39 (\rd_mux_sel_r_reg[1]_38 ), .\rd_mux_sel_r_reg[1]_4 (\rd_mux_sel_r_reg[1]_3 ), .\rd_mux_sel_r_reg[1]_40 (\rd_mux_sel_r_reg[1]_39 ), .\rd_mux_sel_r_reg[1]_41 (\rd_mux_sel_r_reg[1]_40 ), .\rd_mux_sel_r_reg[1]_42 (\rd_mux_sel_r_reg[1]_41 ), .\rd_mux_sel_r_reg[1]_43 (\rd_mux_sel_r_reg[1]_42 ), .\rd_mux_sel_r_reg[1]_44 (\rd_mux_sel_r_reg[1]_43 ), .\rd_mux_sel_r_reg[1]_45 (\rd_mux_sel_r_reg[1]_44 ), .\rd_mux_sel_r_reg[1]_46 (\rd_mux_sel_r_reg[1]_45 ), .\rd_mux_sel_r_reg[1]_47 (\rd_mux_sel_r_reg[1]_46 ), .\rd_mux_sel_r_reg[1]_48 (\rd_mux_sel_r_reg[1]_47 ), .\rd_mux_sel_r_reg[1]_49 (\rd_mux_sel_r_reg[1]_48 ), .\rd_mux_sel_r_reg[1]_5 (\rd_mux_sel_r_reg[1]_4 ), .\rd_mux_sel_r_reg[1]_50 (\rd_mux_sel_r_reg[1]_49 ), .\rd_mux_sel_r_reg[1]_51 (\rd_mux_sel_r_reg[1]_50 ), .\rd_mux_sel_r_reg[1]_52 (\rd_mux_sel_r_reg[1]_51 ), .\rd_mux_sel_r_reg[1]_53 (\rd_mux_sel_r_reg[1]_52 ), .\rd_mux_sel_r_reg[1]_54 (\rd_mux_sel_r_reg[1]_53 ), .\rd_mux_sel_r_reg[1]_55 (\rd_mux_sel_r_reg[1]_54 ), .\rd_mux_sel_r_reg[1]_56 (\rd_mux_sel_r_reg[1]_55 ), .\rd_mux_sel_r_reg[1]_57 (\rd_mux_sel_r_reg[1]_56 ), .\rd_mux_sel_r_reg[1]_58 (\rd_mux_sel_r_reg[1]_57 ), .\rd_mux_sel_r_reg[1]_59 (\rd_mux_sel_r_reg[1]_58 ), .\rd_mux_sel_r_reg[1]_6 (\rd_mux_sel_r_reg[1]_5 ), .\rd_mux_sel_r_reg[1]_60 (\rd_mux_sel_r_reg[1]_59 ), .\rd_mux_sel_r_reg[1]_61 (\rd_mux_sel_r_reg[1]_60 ), .\rd_mux_sel_r_reg[1]_62 (\rd_mux_sel_r_reg[1]_61 ), .\rd_mux_sel_r_reg[1]_63 (\rd_mux_sel_r_reg[1]_62 ), .\rd_mux_sel_r_reg[1]_7 (\rd_mux_sel_r_reg[1]_6 ), .\rd_mux_sel_r_reg[1]_8 (\rd_mux_sel_r_reg[1]_7 ), .\rd_mux_sel_r_reg[1]_9 (\rd_mux_sel_r_reg[1]_8 ), .\rdlvl_cpt_tap_cnt_reg[1] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ), .\rdlvl_cpt_tap_cnt_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ), .\rdlvl_cpt_tap_cnt_reg[4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ), .\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ), .rdlvl_last_byte_done(rdlvl_last_byte_done), .rdlvl_pi_incdec(rdlvl_pi_incdec), .rdlvl_pi_incdec_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ), .rdlvl_pi_incdec_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ), .rdlvl_prech_req(rdlvl_prech_req), .rdlvl_rank_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ), .rdlvl_stg1_done_int(rdlvl_stg1_done_int), .rdlvl_stg1_done_r1_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done), .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33), .rdlvl_stg1_start_reg_0(cnt_shift_r0), .\regl_dqs_cnt_r_reg[2]_0 (regl_dqs_cnt), .\regl_dqs_cnt_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ), .\regl_dqs_cnt_reg[2]_0 (pi_stg2_load_timing_i_1_n_0), .\right_edge_taps_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ), .\right_edge_taps_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ), .\right_edge_taps_r_reg[0]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .samp_cnt_done_r_reg_0(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ), .samp_cnt_done_r_reg_1(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ), .samp_cnt_done_r_reg_2(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ), .samp_cnt_done_r_reg_3(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ), .samp_cnt_done_r_reg_4(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ), .samp_cnt_done_r_reg_5(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ), .samp_cnt_done_r_reg_6(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg_0(samp_edge_cnt0_en_r_reg), .\second_edge_taps_r_reg[5]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ), .sr_valid_r108_out(sr_valid_r108_out), .sr_valid_r1_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ), .stg1_wr_done(stg1_wr_done), .\stg1_wr_rd_cnt_reg[3] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ), .store_sr_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ), .store_sr_req_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ), .store_sr_req_r_reg_1(store_sr_r_i_1_n_0), .tempmon_pi_f_en_r(tempmon_pi_f_en_r), .tempmon_pi_f_inc_r(tempmon_pi_f_inc_r), .\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0), .\wait_cnt_r_reg[0]_1 (pi_cnt_dec_i_1_n_0), .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .wrcal_prech_req(wrcal_prech_req), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_done_r1_reg(u_ddr_phy_wrcal_n_91), .wrlvl_done_r1_reg_0(u_ddr_phy_init_n_499), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_mux_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 )); ddr3_ifmig_7series_v4_0_ddr_phy_tempmon ddr_phy_tempmon_0 (.CLK(CLK), .D(ddr_phy_tempmon_0_n_3), .SS(SS), .calib_complete(calib_complete), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] (ddr_phy_tempmon_0_n_4), .\calib_zero_inputs_reg[1]_0 (ddr_phy_tempmon_0_n_5), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .cmd_delay_start0(cmd_delay_start0), .ctl_lane_sel(ctl_lane_sel), .delay_done_r4_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .fine_adjust_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (ddr_phy_tempmon_0_n_2), .\gen_byte_sel_div1.calib_in_common_reg (ddr_phy_tempmon_0_n_6), .oclkdelay_calib_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ), .rd_data_offset_cal_done(rd_data_offset_cal_done), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .tempmon_pi_f_inc(tempmon_pi_f_inc), .tempmon_sample_en(tempmon_sample_en), .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec)); LUT6 #( .INIT(64'hFEFFFFFF02000000)) dq_cnt_inc_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I4(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ), .I5(p_0_in_2), .O(dq_cnt_inc_i_1_n_0)); LUT6 #( .INIT(64'h00E2FFFF00E20000)) dqs_found_prech_req_i_1 (.I0(fine_adj_state_r16_out), .I1(fine_adj_state_r144_out), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ), .I5(dqs_found_prech_req), .O(dqs_found_prech_req_i_1_n_0)); ddr3_ifmig_7series_v4_0_ddr_phy_dqs_found_cal \dqsfind_calib_right.u_ddr_phy_dqs_found_cal (.CLK(CLK), .D({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_99 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 }), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .\FSM_sequential_fine_adj_state_r_reg[0]_0 ({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 }), .\FSM_sequential_fine_adj_state_r_reg[0]_1 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ), .\FSM_sequential_fine_adj_state_r_reg[0]_2 (fine_adjust_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[0]_3 (fine_adjust_done_r_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_0 (rst_dqs_find_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_1 (final_dec_done_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_2 (ck_po_stg2_f_indec_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_3 (ck_po_stg2_f_en_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[2]_0 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ), .\FSM_sequential_fine_adj_state_r_reg[2]_1 (dqs_found_prech_req_i_1_n_0), .Q(\po_rdval_cnt_reg[8] [1:0]), .SR(SR), .byte_sel_cnt(byte_sel_cnt), .\calib_data_offset_0_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ), .\calib_data_offset_0_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ), .\calib_data_offset_0_reg[4] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ), .\calib_data_offset_0_reg[5] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ), .\calib_data_offset_1_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ), .\calib_data_offset_1_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ), .\calib_data_offset_1_reg[4] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ), .\calib_data_offset_1_reg[5] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ), .\calib_zero_inputs_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ), .\calib_zero_inputs_reg[1]_0 ({calib_zero_inputs,calib_zero_inputs__0}), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .ck_po_stg2_f_en(ck_po_stg2_f_en), .ck_po_stg2_f_indec(ck_po_stg2_f_indec), .cmd_delay_start0(cmd_delay_start0), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1] ), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4] ), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ), .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0] ), .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1] ), .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4] ), .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ), .cnt_cmd_done_r(cnt_cmd_done_r), .ctl_lane_cnt(ctl_lane_cnt), .ctl_lane_sel(ctl_lane_sel), .\dec_cnt_reg[0]_0 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ), .detect_pi_found_dqs(detect_pi_found_dqs), .dqs_found_prech_req(dqs_found_prech_req), .dqs_found_prech_req_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ), .dqs_found_prech_req_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ), .dqs_po_dec_done(dqs_po_dec_done), .dqs_po_en_stg2_f(dqs_po_en_stg2_f), .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec), .final_dec_done_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ), .final_dec_done_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_75 ), .fine_adj_state_r144_out(fine_adj_state_r144_out), .fine_adj_state_r16_out(fine_adj_state_r16_out), .fine_adjust_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ), .fine_adjust_reg_0(fine_adjust_reg), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .\gen_byte_sel_div1.calib_in_common_reg (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\phaser_in_gen.phaser_in_i_12_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\phaser_in_gen.phaser_in_i_12__0_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\phaser_in_gen.phaser_in_i_12__1_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\phaser_in_gen.phaser_in_i_12__2_n_0 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 (\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ), .\gen_byte_sel_div1.ctl_lane_sel_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 (\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ), .\gen_byte_sel_div1.ctl_lane_sel_reg[2] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 (\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_83 ), .ififo_rst_reg(ififo_rst_reg), .ififo_rst_reg_0(ififo_rst_reg_0), .ififo_rst_reg_1(ififo_rst_reg_1), .ififo_rst_reg_2(ififo_rst_reg_2), .in0(in0), .init_calib_complete_reg(ddr_phy_tempmon_0_n_5), .init_dec_done_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ), .init_dec_done_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ), .init_dec_done_reg_2(init_dec_done_i_1_n_0), .init_dqsfound_done_r2(init_dqsfound_done_r2), .init_dqsfound_done_r5(init_dqsfound_done_r5), .init_dqsfound_done_r_reg_0(init_dqsfound_done_r_i_1_n_0), .\init_state_r_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_81 ), .\init_state_r_reg[1]_0 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ), .\init_state_r_reg[1]_1 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ), .\init_state_r_reg[2] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ), .\num_refresh_reg[1] (u_ddr_phy_init_n_117), .oclkdelay_calib_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ), .oclkdelay_calib_done_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .out({p_3_in25_in,p_2_in24_in,p_0_in23_in,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 }), .p_1_in27_in(p_1_in27_in), .p_1_in50_in(p_1_in50_in), .pi_calib_done(pi_calib_done), .\pi_dqs_found_all_bank_r_reg[1]_0 (pi_dqs_found_all_bank), .\pi_dqs_found_all_bank_r_reg[1]_1 (rank_done_r_i_1_n_0), .pi_dqs_found_any_bank(pi_dqs_found_any_bank), .pi_dqs_found_done_r1(pi_dqs_found_done_r1), .pi_dqs_found_done_r1_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .\pi_dqs_found_lanes_r3_reg[3]_0 (\pi_dqs_found_any_bank[0]_i_1_n_0 ), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .pi_dqs_found_start_reg(u_ddr_phy_init_n_502), .pi_dqs_found_start_reg_0(u_ddr_phy_init_n_501), .pi_f_inc_reg(ddr_phy_tempmon_0_n_6), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .\pi_rst_stg1_cal_r_reg[0]_0 (\pi_rst_stg1_cal_r_reg[0] ), .\pi_rst_stg1_cal_r_reg[0]_1 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_72 ), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_1 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_2 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_6 ), .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_23 ), .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_25 ), .\po_counter_read_val_reg[8]_12 (\po_counter_read_val_reg[8]_26 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_7 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_9 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_10 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_16 ), .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_17 ), .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_19 ), .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_20 ), .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_22 ), .po_en_stg23(po_en_stg23), .po_en_stg2_f(cmd_po_en_stg2_f), .po_enstg2_f(po_enstg2_f), .po_stg23_incdec(po_stg23_incdec), .po_stg2_fincdec(po_stg2_fincdec), .prbs_last_byte_done_r(prbs_last_byte_done_r), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prech_done(prech_done), .rank_done_r_reg_0(pi_dqs_found_all_bank_r), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_69 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_70 }), .\rank_final_loop[0].final_do_max_reg[0][3]_0 (rd_data_offset_ranks_0), .\rank_final_loop[0].final_do_max_reg[0][3]_1 (rd_data_offset_ranks_1), .\rd_byte_data_offset_reg[0][9]_0 (p_0_in_0), .\rd_byte_data_offset_reg[0]_3 (\rd_byte_data_offset_reg[0]_3 ), .rd_data_offset_cal_done(rd_data_offset_cal_done), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rst_dqs_find(rst_dqs_find), .rst_dqs_find_r1_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ), .rst_dqs_find_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ), .rst_dqs_find_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_107 ), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_final_mux(wrlvl_final_mux)); LUT4 #( .INIT(16'h2F20)) early1_data_i_1 (.I0(u_ddr_phy_wrcal_n_67), .I1(u_ddr_phy_wrcal_n_110), .I2(u_ddr_phy_wrcal_n_119), .I3(u_ddr_phy_wrcal_n_73), .O(early1_data_i_1_n_0)); LUT5 #( .INIT(32'h04FF0400)) early2_data_i_1 (.I0(u_ddr_phy_wrcal_n_67), .I1(u_ddr_phy_wrcal_n_66), .I2(u_ddr_phy_wrcal_n_110), .I3(u_ddr_phy_wrcal_n_119), .I4(u_ddr_phy_wrcal_n_74), .O(early2_data_i_1_n_0)); LUT5 #( .INIT(32'hFFFF0400)) final_dec_done_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_75 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ), .O(final_dec_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00100000)) fine_adjust_done_r_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I2(p_1_in27_in), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I5(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ), .O(fine_adjust_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00000100)) fine_adjust_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I3(init_dqsfound_done_r5), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I5(\pi_rst_stg1_cal_r_reg[0] ), .O(fine_adjust_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair711" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[11]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[3]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [2])); (* SOFT_HLUTNM = "soft_lutpair699" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[11]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[3]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair711" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[11]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[3]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [2])); (* SOFT_HLUTNM = "soft_lutpair699" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[11]_i_1__2 (.I0(fine_delay_mod[3]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair710" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[14]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[4]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [3])); (* SOFT_HLUTNM = "soft_lutpair700" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[14]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[4]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair710" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[14]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[4]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [3])); (* SOFT_HLUTNM = "soft_lutpair700" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[14]_i_1__2 (.I0(fine_delay_mod[4]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair702" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[17]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[5]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [4])); (* SOFT_HLUTNM = "soft_lutpair708" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[17]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[5]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair708" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[17]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[5]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [4])); (* SOFT_HLUTNM = "soft_lutpair702" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[17]_i_1__2 (.I0(fine_delay_mod[5]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair701" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[20]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[6]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [5])); (* SOFT_HLUTNM = "soft_lutpair709" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[20]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[6]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair709" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[20]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[6]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [5])); (* SOFT_HLUTNM = "soft_lutpair701" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[20]_i_1__2 (.I0(fine_delay_mod[6]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair703" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[23]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[7]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [6])); (* SOFT_HLUTNM = "soft_lutpair712" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[23]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[7]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair712" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[23]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[7]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [6])); (* SOFT_HLUTNM = "soft_lutpair697" *) LUT5 #( .INIT(32'h0000AB00)) \fine_delay_r[23]_i_1__2 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair703" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[23]_i_2 (.I0(fine_delay_mod[7]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[7])); (* SOFT_HLUTNM = "soft_lutpair694" *) LUT5 #( .INIT(32'h0000EA00)) \fine_delay_r[26]_i_1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair697" *) LUT5 #( .INIT(32'h0000BA00)) \fine_delay_r[26]_i_1__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair694" *) LUT5 #( .INIT(32'h0000BA00)) \fine_delay_r[26]_i_1__1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[5]_1 )); (* SOFT_HLUTNM = "soft_lutpair706" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[26]_i_2 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[8]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [7])); (* SOFT_HLUTNM = "soft_lutpair706" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[26]_i_2__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[8]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair714" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[26]_i_2__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[8]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [7])); (* SOFT_HLUTNM = "soft_lutpair705" *) LUT5 #( .INIT(32'h44440004)) \fine_delay_r[2]_i_1 (.I0(calib_zero_inputs__0), .I1(fine_delay_mod[0]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair704" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[5]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[1]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [0])); (* SOFT_HLUTNM = "soft_lutpair713" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[5]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[1]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair713" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[5]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[1]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [0])); (* SOFT_HLUTNM = "soft_lutpair704" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[5]_i_1__2 (.I0(fine_delay_mod[1]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair707" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[8]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[2]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [1])); (* SOFT_HLUTNM = "soft_lutpair707" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[8]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[2]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair698" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[8]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[2]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [1])); (* SOFT_HLUTNM = "soft_lutpair698" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[8]_i_1__2 (.I0(fine_delay_mod[2]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[2])); LUT6 #( .INIT(64'hFFFFDFDD00000008)) fine_delay_sel_i_1 (.I0(prbs_state_r[0]), .I1(prbs_state_r[4]), .I2(prbs_state_r[3]), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ), .I5(fine_delay_sel_r_reg), .O(fine_delay_sel_i_1_n_0)); LUT6 #( .INIT(64'h8FFFFFFF80000000)) fine_dly_error_i_1 (.I0(dec_cnt_reg[0]), .I1(dec_cnt_reg[5]), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ), .I3(prbs_state_r[1]), .I4(prbs_state_r[0]), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ), .O(fine_dly_error_i_1_n_0)); LUT6 #( .INIT(64'h00000000FFFFAAA8)) flag_ck_negedge_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ), .I2(stable_cnt1), .I3(stable_cnt227_in), .I4(flag_ck_negedge09_out), .I5(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ), .O(flag_ck_negedge_i_1_n_0)); LUT6 #( .INIT(64'h3F3FFBFF00000800)) found_first_edge_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ), .O(found_first_edge_r_i_1_n_0)); LUT5 #( .INIT(32'h08FF0800)) found_second_edge_r_i_1 (.I0(found_stable_eye_last_r), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ), .O(found_second_edge_r_i_1_n_0)); LUT3 #( .INIT(8'hB8)) found_stable_eye_last_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ), .I1(detect_edge_done_r), .I2(found_stable_eye_last_r), .O(found_stable_eye_last_r_i_1_n_0)); FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.byte_sel_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ), .Q(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.byte_sel_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ), .Q(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.byte_sel_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ), .Q(byte_sel_cnt), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.calib_in_common_reg (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ), .Q(calib_in_common), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.ctl_lane_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ), .Q(\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.ctl_lane_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ), .Q(\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \gen_byte_sel_div1.ctl_lane_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ), .Q(\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__9)); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .O(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .O(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .O(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .O(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I3(pb_detect_edge_done_r[0]), .O(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[0].pb_found_edge_r[0]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ), .I5(pb_detect_edge_done_r[0]), .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ), .I1(pb_detect_edge_done_r[0]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ), .I4(pb_found_stable_eye_r76_out), .I5(\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in102_in), .I3(pb_detect_edge_done_r[1]), .O(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[1].pb_found_edge_r[1]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in16_in), .I5(pb_detect_edge_done_r[1]), .O(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ), .I1(pb_detect_edge_done_r[1]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ), .I4(pb_found_stable_eye_r72_out), .I5(\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in99_in), .I3(pb_detect_edge_done_r[2]), .O(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[2].pb_found_edge_r[2]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in13_in), .I5(pb_detect_edge_done_r[2]), .O(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ), .I1(pb_detect_edge_done_r[2]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ), .I4(pb_found_stable_eye_r68_out), .I5(\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in96_in), .I3(pb_detect_edge_done_r[3]), .O(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[3].pb_found_edge_r[3]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in10_in), .I5(pb_detect_edge_done_r[3]), .O(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ), .I1(pb_detect_edge_done_r[3]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ), .I4(pb_found_stable_eye_r64_out), .I5(\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in93_in), .I3(pb_detect_edge_done_r[4]), .O(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[4].pb_found_edge_r[4]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in7_in), .I5(pb_detect_edge_done_r[4]), .O(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ), .I1(pb_detect_edge_done_r[4]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ), .I4(pb_found_stable_eye_r60_out), .I5(\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in90_in), .I3(pb_detect_edge_done_r[5]), .O(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[5].pb_found_edge_r[5]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in4_in), .I5(pb_detect_edge_done_r[5]), .O(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ), .I1(pb_detect_edge_done_r[5]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ), .I4(pb_found_stable_eye_r56_out), .I5(\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in87_in), .I3(pb_detect_edge_done_r[6]), .O(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[6].pb_found_edge_r[6]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in1_in), .I5(pb_detect_edge_done_r[6]), .O(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ), .I1(pb_detect_edge_done_r[6]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ), .I4(pb_found_stable_eye_r52_out), .I5(\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in84_in), .I3(pb_detect_edge_done_r[7]), .O(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[7].pb_found_edge_r[7]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in), .I5(pb_detect_edge_done_r[7]), .O(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ), .I1(pb_detect_edge_done_r[7]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ), .I5(\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[0].left_edge_found_pb[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ), .O(\genblk8[0].left_edge_found_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[0].left_edge_updated[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[0]), .O(\genblk8[0].left_edge_updated[0]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[0].right_edge_found_pb[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[0].right_edge_found_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[1].left_edge_found_pb[1]_i_1 (.I0(p_146_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ), .O(\genblk8[1].left_edge_found_pb[1]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[1].left_edge_updated[1]_i_1 (.I0(p_146_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[1]), .O(\genblk8[1].left_edge_updated[1]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[1].right_edge_found_pb[1]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ), .I2(p_143_out), .I3(p_146_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[1].right_edge_found_pb[1]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[2].left_edge_found_pb[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ), .O(\genblk8[2].left_edge_found_pb[2]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[2].left_edge_updated[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[2]), .O(\genblk8[2].left_edge_updated[2]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[2].right_edge_found_pb[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[2].right_edge_found_pb[2]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[3].left_edge_found_pb[3]_i_1 (.I0(p_130_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ), .O(\genblk8[3].left_edge_found_pb[3]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[3].left_edge_updated[3]_i_1 (.I0(p_130_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[3]), .O(\genblk8[3].left_edge_updated[3]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[3].right_edge_found_pb[3]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ), .I2(p_127_out), .I3(p_130_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[3].right_edge_found_pb[3]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[4].left_edge_found_pb[4]_i_1 (.I0(p_122_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ), .O(\genblk8[4].left_edge_found_pb[4]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[4].left_edge_updated[4]_i_1 (.I0(p_122_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[4]), .O(\genblk8[4].left_edge_updated[4]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[4].right_edge_found_pb[4]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ), .I2(p_119_out), .I3(p_122_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[4].right_edge_found_pb[4]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[5].left_edge_found_pb[5]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ), .O(\genblk8[5].left_edge_found_pb[5]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[5].left_edge_updated[5]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[5]), .O(\genblk8[5].left_edge_updated[5]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[5].right_edge_found_pb[5]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[5].right_edge_found_pb[5]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[6].left_edge_found_pb[6]_i_1 (.I0(p_106_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ), .O(\genblk8[6].left_edge_found_pb[6]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[6].left_edge_updated[6]_i_1 (.I0(p_106_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[6]), .O(\genblk8[6].left_edge_updated[6]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[6].right_edge_found_pb[6]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ), .I2(p_103_out), .I3(p_106_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[6].right_edge_found_pb[6]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[7].left_edge_found_pb[7]_i_1 (.I0(p_98_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ), .O(\genblk8[7].left_edge_found_pb[7]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[7].left_edge_updated[7]_i_1 (.I0(p_98_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[7]), .O(\genblk8[7].left_edge_updated[7]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[7].right_edge_found_pb[7]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ), .I2(p_95_out), .I3(p_98_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[7].right_edge_found_pb[7]_i_1_n_0 )); LUT2 #( .INIT(4'h4)) \genblk9[0].fine_delay_incdec_pb[0]_i_7 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ), .I1(bit_cnt), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 )); LUT6 #( .INIT(64'hFFDF77DF00000000)) idel_adj_inc_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ), .I4(cal1_wait_r), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ), .O(idel_adj_inc_i_1_n_0)); LUT6 #( .INIT(64'hF0F0B1F0F0B0F0F0)) idel_pat_detect_valid_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ), .O(idel_pat_detect_valid_r_i_1_n_0)); FDRE #( .INIT(1'b0)) idelay_ce_r1_reg (.C(CLK), .CE(1'b1), .D(idelay_ce_int), .Q(idelay_ce_r1), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) idelay_ce_r2_reg (.C(CLK), .CE(1'b1), .D(idelay_ce_r1), .Q(idelay_ce), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) idelay_inc_r1_reg (.C(CLK), .CE(1'b1), .D(idelay_inc_int), .Q(idelay_inc_r1), .R(rstdiv0_sync_r1_reg_rep__9)); (* syn_maxfan = "30" *) FDRE #( .INIT(1'b0)) idelay_inc_r2_reg (.C(CLK), .CE(1'b1), .D(idelay_inc_r1), .Q(idelay_inc), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hFFFFFCFF00000080)) idelay_ld_done_i_1 (.I0(u_ddr_phy_wrcal_n_113), .I1(u_ddr_phy_wrcal_n_111), .I2(u_ddr_phy_wrcal_n_109), .I3(u_ddr_phy_wrcal_n_110), .I4(u_ddr_phy_wrcal_n_108), .I5(u_ddr_phy_wrcal_n_69), .O(idelay_ld_done_i_1_n_0)); LUT4 #( .INIT(16'h2F20)) idelay_ld_i_1 (.I0(u_ddr_phy_wrcal_n_4), .I1(u_ddr_phy_wrcal_n_109), .I2(u_ddr_phy_wrcal_n_116), .I3(idelay_ld), .O(idelay_ld_i_1_n_0)); LUT3 #( .INIT(8'hB8)) inhibit_edge_detect_r_i_1 (.I0(inhibit_edge_detect_r), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ), .O(inhibit_edge_detect_r_i_1_n_0)); (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(phy_dout[33]), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(\my_empty_reg[7] ), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__0 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__0_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__1 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__1_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__10 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__10_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__11 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__11_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__12 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__12_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__13 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__13_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__14 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_r_reg), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__2 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__2_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__3 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__3_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__4 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__4_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__5 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(\rd_ptr_timing_reg[0] ), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__6 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(app_zq_r_reg), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__7 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__8 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__8_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) init_calib_complete_reg_rep__9 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__9_n_0), .R(1'b0)); LUT5 #( .INIT(32'hFFFF0004)) init_complete_r_i_1 (.I0(init_state_r), .I1(u_ddr_phy_init_n_105), .I2(u_ddr_phy_init_n_104), .I3(u_ddr_phy_init_n_470), .I4(u_ddr_phy_init_n_18), .O(init_complete_r_i_1_n_0)); LUT5 #( .INIT(32'hFFFF0004)) init_complete_r_timing_i_1 (.I0(init_state_r), .I1(u_ddr_phy_init_n_105), .I2(u_ddr_phy_init_n_104), .I3(u_ddr_phy_init_n_470), .I4(init_complete_r_timing_orig), .O(init_complete_r_timing_i_1_n_0)); LUT6 #( .INIT(64'hAAAAAAAAAABAAAAA)) init_dec_done_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ), .I5(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .O(init_dec_done_i_1_n_0)); LUT6 #( .INIT(64'h00000000000000E2)) init_dqsfound_done_r_i_1 (.I0(rd_data_offset_cal_done), .I1(p_1_in27_in), .I2(\rd_byte_data_offset_reg[0]_3 ), .I3(rstdiv0_sync_r1_reg_rep__23), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_72 ), .I5(p_1_in50_in), .O(init_dqsfound_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair696" *) LUT5 #( .INIT(32'h0000AB00)) \input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 )); (* SOFT_HLUTNM = "soft_lutpair695" *) LUT5 #( .INIT(32'h0000EA00)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair695" *) LUT5 #( .INIT(32'h0000BA00)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair696" *) LUT5 #( .INIT(32'h0000BA00)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 )); ddr3_ifmig_7series_v4_0_ddr_phy_ck_addr_cmd_delay \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay (.CLK(CLK), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .Q(\po_rdval_cnt_reg[8] [1:0]), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .cmd_delay_start0(cmd_delay_start0), .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r), .ctl_lane_cnt(ctl_lane_cnt), .delay_dec_done_reg_0(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ), .delay_dec_done_reg_1(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ), .dqs_po_dec_done(dqs_po_dec_done), .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec), .\init_state_r_reg[0] (\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ), .\mcGo_r_reg[15] (\mcGo_r_reg[15] ), .p_1_in(p_1_in), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .po_cnt_inc_reg_0(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_0 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_4 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_5 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_18 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_21 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_24 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_27 ), .po_en_stg2_f(cmd_po_en_stg2_f), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0_1), .\wait_cnt_r_reg[0]_1 (po_cnt_inc_i_1_n_0), .\wait_cnt_r_reg[0]_2 (po_cnt_dec_i_1_n_0)); ddr3_ifmig_7series_v4_0_ddr_phy_wrlvl \mb_wrlvl_inst.u_ddr_phy_wrlvl (.CLK(CLK), .D({\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}), .\FSM_sequential_wl_state_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ), .\FSM_sequential_wl_state_r_reg[0]_1 (wr_level_done_r_i_1_n_0), .\FSM_sequential_wl_state_r_reg[1]_0 (dq_cnt_inc_i_1_n_0), .\FSM_sequential_wl_state_r_reg[2]_0 (wl_edge_detect_valid_r_i_1_n_0), .\FSM_sequential_wl_state_r_reg[2]_1 (wrlvl_rank_done_r_i_1_n_0), .O({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }), .Q(\u_ocd_lim/stg3_init_val ), .S(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ), .SR({rstdiv0_sync_r1_reg_rep__16,rstdiv0_sync_r1_reg_rep__14[0]}), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[1] (\byte_r_reg[1] ), .byte_sel_cnt(byte_sel_cnt), .\calib_sel_reg[3] (\po_rdval_cnt_reg[8] [2]), .delay_done_r4_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ), .done_dqs_dec239_out(done_dqs_dec239_out), .done_dqs_tap_inc(done_dqs_tap_inc), .dq_cnt_inc_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ), .dqs_po_dec_done(dqs_po_dec_done), .dqs_po_en_stg2_f(dqs_po_en_stg2_f), .dqs_po_en_stg2_f_reg_0(dqs_po_en_stg2_f_reg), .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec), .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec), .early1_data_reg(u_ddr_phy_wrcal_n_101), .early1_data_reg_0(u_ddr_phy_wrcal_n_73), .flag_ck_negedge09_out(flag_ck_negedge09_out), .flag_ck_negedge_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ), .flag_ck_negedge_reg_1(flag_ck_negedge_i_1_n_0), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ), .inhibit_edge_detect_r(inhibit_edge_detect_r), .inhibit_edge_detect_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ), .inhibit_edge_detect_r_reg_1(inhibit_edge_detect_r_i_1_n_0), .\lim_state_reg[12] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ), .\mcGo_r_reg[15] (\mcGo_r_reg[15] ), .my_empty(my_empty), .my_empty_6(my_empty_6), .my_empty_7(my_empty_7), .my_empty_8(my_empty_8), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_calib_done_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ), .oclkdelay_calib_done_r_reg_1(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ), .out({\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 }), .p_0_in(p_0_in_2), .p_1_in(p_1_in), .pi_f_inc_reg(ddr_phy_tempmon_0_n_2), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .po_cnt_dec_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ), .po_cnt_dec_reg_1(po_cnt_dec_reg), .\po_counter_read_val_reg[5] ({\po_counter_read_val_reg[5] [5:4],\po_counter_read_val_reg[5] [2:1]}), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_30 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_31 ), .\po_rdval_cnt_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ), .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_100), .\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_98), .\po_stg2_wrcal_cnt_reg[2] ({po_stg2_wrcal_cnt,\idelay_tap_cnt_r_reg[0][3][0] }), .\po_stg2_wrcal_cnt_reg[2]_0 (u_ddr_phy_wrcal_n_97), .\prbs_dqs_cnt_r_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ), .\rank_cnt_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ), .\rank_cnt_r_reg[0]_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ), .\rd_data_edge_detect_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ), .\rd_data_edge_detect_r_reg[0]_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .\single_rank.done_dqs_dec_reg_0 (wr_level_done_i_1_n_0), .stable_cnt1(stable_cnt1), .stable_cnt227_in(stable_cnt227_in), .\stable_cnt_reg[3]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ), .\stg2_r_reg[0] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ), .\stg2_r_reg[4] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ), .\stg2_r_reg[5] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ), .\stg2_tap_cnt_reg[2] (\u_ocd_lim/stg2_tap_cnt_reg ), .\stg2_target_r_reg[4] (wl_po_fine_cnt_sel_0__0), .\stg3_dec_val_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ), .\stg3_dec_val_reg[2]_0 (\u_ocd_lim/stg3_dec_val00_out ), .\stg3_r_reg[5] ({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }), .\wait_cnt_reg[0]_0 (po_cnt_dec_i_1__0_n_0), .wl_sm_start(wl_sm_start), .wr_level_done_r1_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ), .wr_level_done_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ), .wr_lvl_start_reg(u_ddr_phy_init_n_790), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_r(wrlvl_byte_redo_r), .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_102), .wrlvl_done_r_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_r(wrlvl_final_r), .wrlvl_rank_done(wrlvl_rank_done), .wrlvl_rank_done_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ), .\wrlvl_redo_corse_inc_reg[2]_0 (final_coarse_tap)); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1 (.I0(init_calib_complete_reg_rep__13_n_0), .I1(mc_cas_n[1]), .O(phy_dout[32])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[260]), .O(\my_empty_reg[7]_0 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[261]), .O(\my_empty_reg[7]_1 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__3 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[262]), .O(\my_empty_reg[7]_2 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__4 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[263]), .O(\my_empty_reg[7]_3 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[256]), .O(\my_empty_reg[7]_0 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[257]), .O(\my_empty_reg[7]_1 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__3 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[258]), .O(\my_empty_reg[7]_2 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__4 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[259]), .O(\my_empty_reg[7]_3 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[268]), .O(\my_empty_reg[7]_0 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[269]), .O(\my_empty_reg[7]_1 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__3 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[270]), .O(\my_empty_reg[7]_2 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__4 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[271]), .O(\my_empty_reg[7]_3 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__0 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[264]), .O(\my_empty_reg[7]_0 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[265]), .O(\my_empty_reg[7]_1 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[266]), .O(\my_empty_reg[7]_2 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__3 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[267]), .O(\my_empty_reg[7]_3 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[276]), .O(\my_empty_reg[7]_0 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5__0 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[277]), .O(\my_empty_reg[7]_1 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[278]), .O(\my_empty_reg[7]_2 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[279]), .O(\my_empty_reg[7]_3 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[272]), .O(\my_empty_reg[7]_0 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6__0 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[273]), .O(\my_empty_reg[7]_1 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[274]), .O(\my_empty_reg[7]_2 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[275]), .O(\my_empty_reg[7]_3 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[284]), .O(\my_empty_reg[7]_0 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1__0 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[285]), .O(\my_empty_reg[7]_1 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[286]), .O(\my_empty_reg[7]_2 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[287]), .O(\my_empty_reg[7]_3 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[280]), .O(\my_empty_reg[7]_0 [70])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2__0 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[281]), .O(\my_empty_reg[7]_1 [70])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2__1 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[282]), .O(\my_empty_reg[7]_2 [70])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2__2 (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .I1(Q[283]), .O(\my_empty_reg[7]_3 [70])); LUT6 #( .INIT(64'hAFFFFFFF04000000)) mpr_dec_cpt_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ), .O(mpr_dec_cpt_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair715" *) LUT4 #( .INIT(16'h2F20)) mpr_last_byte_done_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ), .I3(mpr_last_byte_done), .O(mpr_last_byte_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFC8C00000080)) mpr_rank_done_r_i_1 (.I0(cal1_cnt_cpt_r1), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ), .I5(mpr_rnk_done), .O(mpr_rank_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair728" *) LUT2 #( .INIT(4'hE)) mpr_rdlvl_done_r_i_1 (.I0(rdlvl_stg1_done_int), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .O(mpr_rdlvl_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFEFFFF00020000)) new_cnt_dqs_r_i_1 (.I0(new_cnt_dqs_r), .I1(prbs_state_r[4]), .I2(prbs_state_r[1]), .I3(prbs_state_r[2]), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ), .O(new_cnt_dqs_r_i_1_n_0)); LUT6 #( .INIT(64'h8F888FFF80888000)) no_err_win_detected_latch_i_1 (.I0(prbs_state_r[3]), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ), .I3(prbs_state_r[0]), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ), .O(no_err_win_detected_latch_i_1_n_0)); LUT6 #( .INIT(64'hF0F0F4F0B0B0F0F0)) num_samples_done_ind_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ), .I1(prbs_state_r[4]), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ), .I3(num_samples_done_r), .I4(prbs_state_r[1]), .I5(prbs_state_r[0]), .O(num_samples_done_ind_i_1_n_0)); ddr3_ifmig_7series_v4_0_ddr_phy_oclkdelay_cal \oclk_calib.u_ddr_phy_oclkdelay_cal (.CLK(CLK), .D(\u_ocd_lim/stg3_dec_val00_out ), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .O({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }), .Q(\po_rdval_cnt_reg[8] [1:0]), .S(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ), .\byte_r_reg[0]_1 (\byte_r_reg[0]_0 ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\cal2_state_r_reg[0] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .cnt_cmd_done_r(cnt_cmd_done_r), .\cnt_shift_r_reg[0] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ), .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r), .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel), .complex_ocal_ref_req(complex_ocal_ref_req), .complex_oclk_calib_resume(complex_oclk_calib_resume), .done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ), .\gen_byte_sel_div1.calib_in_common_reg (\phaser_in_gen.phaser_in_i_12__0_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\phaser_in_gen.phaser_in_i_12__2_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\phaser_in_gen.phaser_in_i_12__1_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\phaser_in_gen.phaser_in_i_12_n_0 ), .\init_state_r_reg[0] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ), .\init_state_r_reg[0]_0 (u_ddr_phy_init_n_114), .\init_state_r_reg[0]_1 (u_ddr_phy_init_n_478), .\init_state_r_reg[2] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ), .\init_state_r_reg[4] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ), .\init_state_r_reg[4]_0 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ), .\init_state_r_reg[4]_1 ({u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_108}), .\init_state_r_reg[5] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ), .\init_state_r_reg[5]_0 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ), .\init_state_r_reg[5]_1 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ), .\init_state_r_reg[6] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ), .lim2init_prech_req(lim2init_prech_req), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .ocal_last_byte_done(ocal_last_byte_done), .ocal_last_byte_done_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .ocal_last_byte_done_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ), .ocd_prech_req(ocd_prech_req), .oclkdelay_calib_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ), .oclkdelay_calib_start_int_reg(u_ddr_phy_init_n_462), .oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_24), .oclkdelay_center_calib_start_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ), .oclkdelay_int_ref_req_reg(u_ddr_phy_init_n_477), .pd_out(pd_out), .phy_rddata_en(phy_rddata_en), .phy_rddata_en_1(phy_rddata_en_1), .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt), .\po_counter_read_val_reg[2] (\po_counter_read_val_reg[2] ), .\po_counter_read_val_reg[5] (\po_counter_read_val_reg[5] ), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_3 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_8 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_11 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_12 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_13 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_14 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_15 ), .po_en_stg23(po_en_stg23), .po_stg23_incdec(po_stg23_incdec), .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_105), .\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_106), .poc_sample_pd(poc_sample_pd), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prech_done(prech_done), .prech_req_posedge_r_reg(u_ddr_phy_init_n_9), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .rd_active_r1(rd_active_r1), .rd_active_r2(rd_active_r2), .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33), .\resume_wait_r_reg[5] (E), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0), .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1), .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\samps_r_reg[9] (\samps_r_reg[9] ), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .sr_valid_r108_out(sr_valid_r108_out), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .\stg2_tap_cnt_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ), .\stg2_tap_cnt_reg[3] (\u_ocd_lim/stg2_tap_cnt_reg ), .\stg2_target_r_reg[8] ({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .\stg3_tap_cnt_reg[2] (\u_ocd_lim/stg3_init_val ), .\wl_po_fine_cnt_reg[14] (wl_po_fine_cnt_sel_0__0), .\wl_po_fine_cnt_reg[17] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ), .\wl_po_fine_cnt_reg[18] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ), .\wl_po_fine_cnt_reg[23] ({\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}), .\wl_po_fine_cnt_reg[3] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ), .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_mux_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .\zero2fuzz_r_reg[0] (\zero2fuzz_r_reg[0] )); LUT4 #( .INIT(16'h88F0)) out_fifo_i_10__6 (.I0(mc_address[35]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3]_0 [2]), .I3(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [2])); LUT4 #( .INIT(16'h88F0)) out_fifo_i_11__2 (.I0(\rd_ptr_timing_reg[0] ), .I1(mc_cas_n[1]), .I2(\rd_ptr_reg[3]_0 [1]), .I3(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [1])); LUT4 #( .INIT(16'h88F0)) out_fifo_i_12__6 (.I0(mc_address[13]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3]_0 [0]), .I3(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_15__6 (.I0(mc_we_n[2]), .I1(\my_empty_reg[7] ), .I2(mem_out[5]), .I3(\my_empty_reg[1]_0 ), .O(D1[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_17__5 (.I0(mc_we_n[0]), .I1(\my_empty_reg[7] ), .I2(mem_out[3]), .I3(\my_empty_reg[1]_0 ), .O(D1[0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_17__6 (.I0(mc_cas_n[2]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [2]), .I3(\my_empty_reg[1] ), .O(D2[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_19__6 (.I0(mc_cas_n[0]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [0]), .I3(\my_empty_reg[1] ), .O(D2[0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_25__5 (.I0(mc_ras_n[2]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [5]), .I3(\my_empty_reg[1] ), .O(D3[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_27__5 (.I0(mc_ras_n[0]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [3]), .I3(\my_empty_reg[1] ), .O(D3[0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_7__6 (.I0(mc_ras_n[2]), .I1(\my_empty_reg[7] ), .I2(mem_out[2]), .I3(\my_empty_reg[1]_0 ), .O(D0[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_9__6 (.I0(mc_cs_n), .I1(\my_empty_reg[7] ), .I2(mem_out[0]), .I3(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair724" *) LUT1 #( .INIT(2'h1)) \periodic_read_request.periodic_rd_r_lcl_i_1 (.I0(app_zq_r_reg), .O(maint_prescaler_r1)); (* SOFT_HLUTNM = "soft_lutpair721" *) LUT3 #( .INIT(8'hEA)) \phaser_in_gen.phaser_in_i_12 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .O(\phaser_in_gen.phaser_in_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair722" *) LUT3 #( .INIT(8'hBA)) \phaser_in_gen.phaser_in_i_12__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .O(\phaser_in_gen.phaser_in_i_12__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair722" *) LUT3 #( .INIT(8'hBA)) \phaser_in_gen.phaser_in_i_12__1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .O(\phaser_in_gen.phaser_in_i_12__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair721" *) LUT3 #( .INIT(8'hAB)) \phaser_in_gen.phaser_in_i_12__2 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .O(\phaser_in_gen.phaser_in_i_12__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair705" *) LUT4 #( .INIT(16'h00F8)) \phaser_in_gen.phaser_in_i_2 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair714" *) LUT4 #( .INIT(16'h00F2)) \phaser_in_gen.phaser_in_i_2__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair718" *) LUT4 #( .INIT(16'h00F2)) \phaser_in_gen.phaser_in_i_2__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair718" *) LUT4 #( .INIT(16'h00F1)) \phaser_in_gen.phaser_in_i_2__2 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair717" *) LUT4 #( .INIT(16'h0040)) phaser_out_i_2 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(calib_zero_inputs), .O(D_po_counter_read_en122_out)); (* SOFT_HLUTNM = "soft_lutpair719" *) LUT4 #( .INIT(16'h0001)) phaser_out_i_2__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(calib_zero_inputs), .O(\po_counter_read_val_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair717" *) LUT4 #( .INIT(16'h0004)) phaser_out_i_2__5 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(calib_zero_inputs), .O(\po_counter_read_val_reg[8]_28 )); (* SOFT_HLUTNM = "soft_lutpair719" *) LUT4 #( .INIT(16'h0004)) phaser_out_i_2__6 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(calib_zero_inputs), .O(\po_counter_read_val_reg[8]_29 )); LUT4 #( .INIT(16'hFFFE)) phy_if_reset0 (.I0(reset_if), .I1(phy_if_reset_w), .I2(mpr_end_if_reset), .I3(wrlvl_final_if_rst), .O(phy_if_reset0__0)); FDRE #( .INIT(1'b0)) phy_if_reset_reg (.C(CLK), .CE(1'b1), .D(phy_if_reset0__0), .Q(phy_if_reset), .R(1'b0)); LUT6 #( .INIT(64'h0000000000400000)) pi_cnt_dec_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ), .I1(wait_cnt_r_reg__0[0]), .I2(dqs_po_dec_done_r2), .I3(wait_cnt_r_reg__0[1]), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ), .I5(rstdiv0_sync_r1_reg_rep__22), .O(pi_cnt_dec_i_1_n_0)); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \pi_dqs_found_any_bank[0]_i_1 (.I0(p_3_in25_in), .I1(p_2_in24_in), .I2(p_0_in23_in), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ), .I4(u_ddr_phy_init_n_502), .I5(pi_dqs_found_any_bank), .O(\pi_dqs_found_any_bank[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair723" *) LUT3 #( .INIT(8'h08)) pi_stg2_f_incdec_timing_i_1 (.I0(prbs_tap_inc_r), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ), .I2(rstdiv0_sync_r1_reg_rep__22), .O(pi_stg2_f_incdec_timing_i_1_n_0)); LUT3 #( .INIT(8'h04)) pi_stg2_load_timing_i_1 (.I0(regl_dqs_cnt), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ), .O(pi_stg2_load_timing_i_1_n_0)); LUT6 #( .INIT(64'h0000000000800000)) po_cnt_dec_i_1 (.I0(wait_cnt_r_reg__0_1), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ), .I4(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ), .I5(rstdiv0_sync_r1_reg_rep__24), .O(po_cnt_dec_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair720" *) LUT3 #( .INIT(8'h04)) po_cnt_dec_i_1__0 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ), .I2(rstdiv0_sync_r1_reg_rep__22), .O(po_cnt_dec_i_1__0_n_0)); LUT5 #( .INIT(32'h00000020)) po_cnt_inc_i_1 (.I0(wait_cnt_r_reg__0_1), .I1(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ), .I2(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ), .I3(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ), .I4(rstdiv0_sync_r1_reg_rep__23), .O(po_cnt_inc_i_1_n_0)); LUT4 #( .INIT(16'hFFFE)) po_en_stg2_f0 (.I0(ck_po_stg2_f_en), .I1(dqs_po_en_stg2_f), .I2(cmd_po_en_stg2_f), .I3(po_en_stg23), .O(po_enstg2_f)); LUT3 #( .INIT(8'hFE)) po_stg2_f_incdec0 (.I0(ck_po_stg2_f_indec), .I1(dqs_po_stg2_f_incdec), .I2(po_stg23_incdec), .O(po_stg2_fincdec)); LUT2 #( .INIT(4'h6)) \prbs_dqs_cnt_r[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .O(\prbs_dqs_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair716" *) LUT3 #( .INIT(8'h78)) \prbs_dqs_cnt_r[1]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .O(\prbs_dqs_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair716" *) LUT4 #( .INIT(16'h7F80)) \prbs_dqs_cnt_r[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ), .O(\prbs_dqs_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair723" *) LUT3 #( .INIT(8'h02)) prbs_dqs_tap_limit_r_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(rstdiv0_sync_r1_reg_rep__22), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ), .O(prbs_dqs_tap_limit_r_i_1_n_0)); LUT6 #( .INIT(64'hF2FFFFFF02000000)) prbs_found_1st_edge_r_i_1 (.I0(prbs_state_r178_out), .I1(prbs_state_r[3]), .I2(prbs_state_r[0]), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ), .O(prbs_found_1st_edge_r_i_1_n_0)); LUT6 #( .INIT(64'hDFDFF5F502000000)) prbs_last_byte_done_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I1(prbs_state_r[0]), .I2(prbs_state_r[1]), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ), .I4(prbs_state_r[3]), .I5(prbs_last_byte_done), .O(prbs_last_byte_done_i_1_n_0)); LUT6 #( .INIT(64'hFFF337F300000400)) prbs_prech_req_r_i_1 (.I0(prech_done), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I2(prbs_state_r[1]), .I3(prbs_state_r[3]), .I4(prbs_state_r[0]), .I5(prbs_prech_req_r), .O(prbs_prech_req_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFF7FFF00004000)) prbs_rdlvl_done_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ), .I2(prbs_state_r[3]), .I3(prbs_state_r[1]), .I4(prbs_state_r[2]), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .O(prbs_rdlvl_done_i_1_n_0)); LUT6 #( .INIT(64'hA8AAFFFFA8AA0000)) prbs_tap_en_r_i_1 (.I0(prbs_state_r[0]), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ), .I2(prbs_state_r[1]), .I3(prbs_state_r[3]), .I4(prbs_tap_en_r), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ), .O(prbs_tap_en_r_i_1_n_0)); LUT6 #( .INIT(64'h8A00FFFF8A000000)) prbs_tap_inc_r_i_1 (.I0(prbs_state_r[0]), .I1(prbs_state_r[1]), .I2(prbs_state_r[3]), .I3(prbs_state_r[2]), .I4(prbs_tap_en_r), .I5(prbs_tap_inc_r), .O(prbs_tap_inc_r_i_1_n_0)); LUT3 #( .INIT(8'hBA)) prech_pending_r_i_1 (.I0(u_ddr_phy_init_n_9), .I1(u_ddr_phy_init_n_468), .I2(prech_pending_r), .O(prech_pending_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000707070)) rank_done_r_i_1 (.I0(pi_dqs_found_all_bank_r[1]), .I1(pi_dqs_found_all_bank_r[0]), .I2(p_1_in27_in), .I3(rd_data_offset_cal_done), .I4(\rd_byte_data_offset_reg[0]_3 ), .I5(rstdiv0_sync_r1_reg_rep__23), .O(rank_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair720" *) LUT3 #( .INIT(8'hFE)) \rd_addr[7]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(complex_ocal_reset_rd_addr), .I2(reset_rd_addr), .O(\rd_addr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair715" *) LUT4 #( .INIT(16'h8F80)) rdlvl_last_byte_done_int_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ), .I3(rdlvl_last_byte_done), .O(rdlvl_last_byte_done_int_i_1_n_0)); LUT5 #( .INIT(32'h70FF7000)) rdlvl_pi_incdec_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ), .I4(rdlvl_pi_incdec), .O(rdlvl_pi_incdec_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFC8C00000080)) rdlvl_rank_done_r_i_1 (.I0(cal1_cnt_cpt_r1), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ), .I5(rdlvl_stg1_rank_done), .O(rdlvl_rank_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00010000)) rdlvl_start_pre_i_1 (.I0(u_ddr_phy_init_n_102), .I1(u_ddr_phy_init_n_469), .I2(u_ddr_phy_init_n_108), .I3(u_ddr_phy_init_n_107), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .I5(rdlvl_start_pre), .O(rdlvl_start_pre_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair728" *) LUT3 #( .INIT(8'hB8)) rdlvl_stg1_done_int_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .I1(rdlvl_stg1_done_int), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .O(rdlvl_stg1_done_int_i_1_n_0)); LUT6 #( .INIT(64'hFFFEFFFF00020000)) rdlvl_stg1_start_i_1 (.I0(rdlvl_start_dly0_r), .I1(u_ddr_phy_init_n_473), .I2(u_ddr_phy_init_n_108), .I3(u_ddr_phy_init_n_107), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .I5(u_ddr_phy_init_n_33), .O(rdlvl_stg1_start_i_1_n_0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 " *) SRL16E #( .INIT(16'h0000)) reset_if_r8_reg_srl8 (.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(reset_if), .Q(reset_if_r8_reg_srl8_n_0)); FDRE #( .INIT(1'b0)) reset_if_r9_reg (.C(CLK), .CE(1'b1), .D(reset_if_r8_reg_srl8_n_0), .Q(reset_if_r9), .R(1'b0)); FDRE #( .INIT(1'b0)) reset_if_reg (.C(CLK), .CE(1'b1), .D(u_ddr_phy_init_n_101), .Q(reset_if), .R(1'b0)); LUT6 #( .INIT(64'hFFEFFEFF00000010)) reset_rd_addr_i_1 (.I0(prbs_state_r[4]), .I1(prbs_state_r[2]), .I2(prbs_state_r[3]), .I3(prbs_state_r[0]), .I4(prbs_state_r[1]), .I5(reset_rd_addr), .O(reset_rd_addr_i_1_n_0)); LUT5 #( .INIT(32'h04FF0400)) right_edge_found_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ), .I2(prbs_state_r[4]), .I3(right_edge_found), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ), .O(right_edge_found_i_1_n_0)); LUT5 #( .INIT(32'hBABF8A80)) rst_dqs_find_i_1 (.I0(rst_dqs_find), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_107 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ), .O(rst_dqs_find_i_1_n_0)); LUT4 #( .INIT(16'hABAA)) store_sr_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ), .O(store_sr_r_i_1_n_0)); FDRE #( .INIT(1'b0)) tempmon_pi_f_en_r_reg (.C(CLK), .CE(1'b1), .D(tempmon_sel_pi_incdec), .Q(tempmon_pi_f_en_r), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) tempmon_pi_f_inc_r_reg (.C(CLK), .CE(1'b1), .D(tempmon_pi_f_inc), .Q(tempmon_pi_f_inc_r), .R(rstdiv0_sync_r1_reg_rep__9)); ddr3_ifmig_7series_v4_0_ddr_phy_init u_ddr_phy_init (.A_rst_primitives_reg(A_rst_primitives_reg), .CLK(CLK), .D({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }), .D0(D0[1]), .D1(D1[1]), .D2(D2[1]), .D3(D3[1]), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8), .D9(D9), .E(u_ddr_phy_init_n_465), .Q({init_state_r,u_ddr_phy_init_n_104,u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}), .\back_to_back_reads_4_1.num_reads_reg[0]_0 (u_ddr_phy_init_n_473), .\back_to_back_reads_4_1.num_reads_reg[1]_0 (u_ddr_phy_init_n_474), .burst_addr_r_reg_0(u_ddr_phy_init_n_31), .burst_addr_r_reg_1(u_ddr_phy_init_n_476), .burst_addr_r_reg_2(burst_addr_r_i_1_n_0), .cal1_state_r1535_out(cal1_state_r1535_out), .calib_complete(calib_complete), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2] ), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2] ), .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3] ), .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5]_0 ), .cnt_cmd_done_r(cnt_cmd_done_r), .cnt_cmd_done_r_reg_0(ddr2_refresh_flag_r_i_1_n_0), .cnt_cmd_done_r_reg_1(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ), .cnt_dllk_zqinit_done_r(cnt_dllk_zqinit_done_r), .cnt_dllk_zqinit_done_r_reg_0(cnt_dllk_zqinit_done_r_i_1_n_0), .cnt_init_af_done_r(cnt_init_af_done_r), .cnt_init_af_done_r_reg_0(cnt_init_af_done_r_i_1_n_0), .cnt_init_af_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ), .cnt_init_af_r(cnt_init_af_r), .cnt_init_mr_done_r(cnt_init_mr_done_r), .cnt_init_mr_done_r_reg_0(cnt_init_mr_done_r_i_1_n_0), .cnt_init_mr_r(cnt_init_mr_r), .cnt_init_mr_r1(cnt_init_mr_r1), .\cnt_init_mr_r_reg[1]_0 (u_ddr_phy_init_n_110), .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r), .cnt_pwron_cke_done_r_reg_0(u_ddr_phy_init_n_490), .cnt_pwron_cke_done_r_reg_1(cnt_pwron_cke_done_r_i_1_n_0), .\cnt_pwron_r_reg[7]_0 ({cnt_pwron_r_reg__0[7],cnt_pwron_r_reg__0[5],cnt_pwron_r_reg__0[1:0]}), .\cnt_pwron_r_reg[7]_1 (cnt_pwron_reset_done_r_i_1_n_0), .cnt_pwron_reset_done_r(cnt_pwron_reset_done_r), .cnt_pwron_reset_done_r_reg_0(u_ddr_phy_init_n_485), .\cnt_shift_r_reg[0] (cnt_shift_r0), .\cnt_shift_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ), .cnt_txpr_done_r(cnt_txpr_done_r), .cnt_txpr_done_r_reg_0(u_ddr_phy_init_n_500), .cnt_txpr_done_r_reg_1(cnt_txpr_done_r_i_1_n_0), .\cnt_txpr_r_reg[2]_0 (cnt_txpr_r_reg__0), .complex_act_start(complex_act_start), .complex_init_pi_dec_done(complex_init_pi_dec_done), .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r), .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel), .complex_ocal_ref_req(complex_ocal_ref_req), .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr), .complex_oclk_calib_resume(complex_oclk_calib_resume), .complex_oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_114), .complex_pi_incdec_done(complex_pi_incdec_done), .\complex_row_cnt_ocal_reg[0]_0 (\complex_row_cnt_ocal_reg[0] ), .complex_victim_inc_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ), .\data_offset_1_i1_reg[5] (\data_offset_1_i1_reg[5] ), .ddr2_pre_flag_r_reg_0(u_ddr_phy_init_n_29), .ddr2_pre_flag_r_reg_1(u_ddr_phy_init_n_479), .ddr2_pre_flag_r_reg_2(ddr2_pre_flag_r_i_1_n_0), .ddr2_refresh_flag_r(ddr2_refresh_flag_r), .ddr2_refresh_flag_r_reg_0(u_ddr_phy_init_n_480), .ddr3_lm_done_r(ddr3_lm_done_r), .delay_done_r4_reg(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ), .detect_pi_found_dqs(detect_pi_found_dqs), .done_dqs_tap_inc(done_dqs_tap_inc), .done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ), .\dout_o_reg[0] (u_ddr_prbs_gen_n_120), .\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_116), .\dout_o_reg[10] (u_ddr_prbs_gen_n_6), .\dout_o_reg[10]_0 (u_ddr_prbs_gen_n_5), .\dout_o_reg[11] (u_ddr_prbs_gen_n_41), .\dout_o_reg[11]_0 (u_ddr_prbs_gen_n_42), .\dout_o_reg[11]_1 (u_ddr_prbs_gen_n_51), .\dout_o_reg[11]_2 (u_ddr_prbs_gen_n_52), .\dout_o_reg[11]_3 (u_ddr_prbs_gen_n_16), .\dout_o_reg[11]_4 (u_ddr_prbs_gen_n_15), .\dout_o_reg[12] (u_ddr_prbs_gen_n_2), .\dout_o_reg[12]_0 (u_ddr_prbs_gen_n_1), .\dout_o_reg[13] (u_ddr_prbs_gen_n_53), .\dout_o_reg[13]_0 (u_ddr_prbs_gen_n_54), .\dout_o_reg[13]_1 (u_ddr_prbs_gen_n_28), .\dout_o_reg[13]_2 (u_ddr_prbs_gen_n_27), .\dout_o_reg[13]_3 (u_ddr_prbs_gen_n_18), .\dout_o_reg[13]_4 (u_ddr_prbs_gen_n_17), .\dout_o_reg[13]_5 (u_ddr_prbs_gen_n_14), .\dout_o_reg[13]_6 (u_ddr_prbs_gen_n_13), .\dout_o_reg[14] (u_ddr_prbs_gen_n_46), .\dout_o_reg[14]_0 (u_ddr_prbs_gen_n_45), .\dout_o_reg[14]_1 (u_ddr_prbs_gen_n_44), .\dout_o_reg[14]_2 (u_ddr_prbs_gen_n_43), .\dout_o_reg[15] (u_ddr_prbs_gen_n_12), .\dout_o_reg[15]_0 (u_ddr_prbs_gen_n_11), .\dout_o_reg[15]_1 (u_ddr_prbs_gen_n_10), .\dout_o_reg[15]_2 (u_ddr_prbs_gen_n_9), .\dout_o_reg[1] (u_ddr_prbs_gen_n_19), .\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_20), .\dout_o_reg[2] (u_ddr_prbs_gen_n_105), .\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_101), .\dout_o_reg[3] (u_ddr_prbs_gen_n_21), .\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_22), .\dout_o_reg[4] (u_ddr_prbs_gen_n_88), .\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_84), .\dout_o_reg[6] (u_ddr_prbs_gen_n_56), .\dout_o_reg[7] (u_ddr_prbs_gen_n_24), .\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_23), .\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_25), .\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_26), .\dout_o_reg[8] (u_ddr_prbs_gen_n_48), .\dout_o_reg[8]_0 (u_ddr_prbs_gen_n_47), .\dout_o_reg[8]_1 (u_ddr_prbs_gen_n_8), .\dout_o_reg[8]_2 (u_ddr_prbs_gen_n_7), .\dout_o_reg[8]_3 (u_ddr_prbs_gen_n_4), .\dout_o_reg[8]_4 (u_ddr_prbs_gen_n_3), .\dout_o_reg[9] (u_ddr_prbs_gen_n_49), .\dout_o_reg[9]_0 (u_ddr_prbs_gen_n_50), .\dout_o_reg[9]_1 (u_ddr_prbs_gen_n_38), .\dout_o_reg[9]_2 (u_ddr_prbs_gen_n_37), .\dout_o_reg[9]_3 (u_ddr_prbs_gen_n_36), .\dout_o_reg[9]_4 (u_ddr_prbs_gen_n_35), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .dqs_found_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_83 ), .dqs_found_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ), .dqs_found_done_r_reg_2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ), .dqs_found_prech_req(dqs_found_prech_req), .dqs_found_start_r_reg(u_ddr_phy_init_n_502), .\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .first_rdlvl_pat_r(first_rdlvl_pat_r), .first_rdlvl_pat_r_reg_0(u_ddr_prbs_gen_n_55), .first_wrcal_pat_r(first_wrcal_pat_r), .in0(init_complete_r_timing_orig), .init_calib_complete_reg_rep(\my_empty_reg[7] ), .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0_n_0), .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1_n_0), .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10_n_0), .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11_n_0), .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12_n_0), .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13_n_0), .init_calib_complete_reg_rep__14(init_calib_complete_r_reg), .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2_n_0), .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3_n_0), .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4_n_0), .init_calib_complete_reg_rep__5(\rd_ptr_timing_reg[0] ), .init_calib_complete_reg_rep__6(app_zq_r_reg), .init_calib_complete_reg_rep__7(\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8_n_0), .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_n_0), .init_complete_r1_reg_0(u_ddr_phy_init_n_18), .init_dqsfound_done_r2(init_dqsfound_done_r2), .\init_state_r_reg[0]_0 (u_ddr_phy_init_n_497), .\init_state_r_reg[0]_1 (rdlvl_start_pre_i_1_n_0), .\init_state_r_reg[1]_0 (u_ddr_phy_init_n_111), .\init_state_r_reg[1]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ), .\init_state_r_reg[2]_0 (u_ddr_phy_init_n_117), .\init_state_r_reg[2]_1 (u_ddr_phy_init_n_499), .\init_state_r_reg[2]_2 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ), .\init_state_r_reg[4]_0 (u_ddr_phy_init_n_475), .\init_state_r_reg[5]_0 (u_ddr_phy_init_n_478), .\init_state_r_reg[6]_0 (init_complete_r_i_1_n_0), .\init_state_r_reg[6]_1 (init_complete_r_timing_i_1_n_0), .lim2init_prech_req(lim2init_prech_req), .lim_start_r_reg(u_ddr_phy_init_n_462), .\mcGo_r_reg[15] (\mcGo_r_reg[15] ), .mc_address({mc_address[34:14],mc_address[12:0]}), .mc_bank(mc_bank), .mc_cas_n(mc_cas_n[1]), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n[1]), .mc_we_n(mc_we_n[1]), .mc_wrdata_en(mc_wrdata_en), .mem_init_done_r(mem_init_done_r), .mem_init_done_r_reg_0(cnt_dllk_zqinit_r_reg__0), .mem_init_done_r_reg_1(u_ddr_phy_init_n_496), .mem_init_done_r_reg_2(u_ddr_phy_wrcal_n_92), .mem_out({mem_out[4],mem_out[1]}), .mpr_end_if_reset(mpr_end_if_reset), .mpr_last_byte_done(mpr_last_byte_done), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .mpr_rdlvl_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ), .mpr_rdlvl_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ), .mpr_rdlvl_done_r_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ), .mpr_rdlvl_start_r(mpr_rdlvl_start_r), .mpr_rdlvl_start_r_reg(u_ddr_phy_init_n_464), .mux_cmd_wren(mux_cmd_wren), .mux_reset_n(mux_reset_n), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ), .\my_empty_reg[1]_3 (\my_empty_reg[1]_3 ), .\my_empty_reg[1]_4 (\my_empty_reg[1]_4 ), .\my_empty_reg[1]_5 (\my_empty_reg[1]_5 ), .\my_empty_reg[1]_6 (\my_empty_reg[1]_6 ), .\my_empty_reg[7] (\my_empty_reg[7]_4 ), .\my_empty_reg[7]_0 (\my_empty_reg[7]_5 ), .\my_empty_reg[7]_1 (\my_empty_reg[7]_6 ), .\my_empty_reg[7]_10 (\my_empty_reg[7]_15 ), .\my_empty_reg[7]_11 (\my_empty_reg[7]_16 ), .\my_empty_reg[7]_12 (\my_empty_reg[7]_17 ), .\my_empty_reg[7]_13 (\my_empty_reg[7]_18 ), .\my_empty_reg[7]_14 (\my_empty_reg[7]_19 ), .\my_empty_reg[7]_15 (\my_empty_reg[7]_20 ), .\my_empty_reg[7]_16 (\my_empty_reg[7]_21 ), .\my_empty_reg[7]_17 (\my_empty_reg[7]_22 ), .\my_empty_reg[7]_18 (\my_empty_reg[7]_23 ), .\my_empty_reg[7]_19 (\my_empty_reg[7]_24 ), .\my_empty_reg[7]_2 (\my_empty_reg[7]_7 ), .\my_empty_reg[7]_20 (\my_empty_reg[7]_25 ), .\my_empty_reg[7]_21 (\my_empty_reg[7]_26 ), .\my_empty_reg[7]_22 (\my_empty_reg[7]_27 ), .\my_empty_reg[7]_23 (\my_empty_reg[7]_28 ), .\my_empty_reg[7]_24 (\my_empty_reg[7]_29 ), .\my_empty_reg[7]_25 (\my_empty_reg[7]_30 ), .\my_empty_reg[7]_26 (\my_empty_reg[7]_31 ), .\my_empty_reg[7]_27 (\my_empty_reg[7]_32 ), .\my_empty_reg[7]_28 (\my_empty_reg[7]_33 ), .\my_empty_reg[7]_29 (\my_empty_reg[7]_34 ), .\my_empty_reg[7]_3 (\my_empty_reg[7]_8 ), .\my_empty_reg[7]_30 (\my_empty_reg[7]_35 ), .\my_empty_reg[7]_31 (\my_empty_reg[7]_36 ), .\my_empty_reg[7]_32 (\my_empty_reg[7]_37 ), .\my_empty_reg[7]_33 (\my_empty_reg[7]_38 ), .\my_empty_reg[7]_34 (\my_empty_reg[7]_39 ), .\my_empty_reg[7]_35 (\my_empty_reg[7]_40 ), .\my_empty_reg[7]_36 (\my_empty_reg[7]_41 ), .\my_empty_reg[7]_37 (\my_empty_reg[7]_42 ), .\my_empty_reg[7]_38 (\my_empty_reg[7]_0 [63:0]), .\my_empty_reg[7]_39 (\my_empty_reg[7]_1 [63:0]), .\my_empty_reg[7]_4 (\my_empty_reg[7]_9 ), .\my_empty_reg[7]_40 (\my_empty_reg[7]_2 [63:0]), .\my_empty_reg[7]_41 (\my_empty_reg[7]_3 [63:0]), .\my_empty_reg[7]_5 (\my_empty_reg[7]_10 ), .\my_empty_reg[7]_6 (\my_empty_reg[7]_11 ), .\my_empty_reg[7]_7 (\my_empty_reg[7]_12 ), .\my_empty_reg[7]_8 (\my_empty_reg[7]_13 ), .\my_empty_reg[7]_9 (\my_empty_reg[7]_14 ), .\my_full_reg[3] (\my_full_reg[3]_0 ), .new_cnt_dqs_r_reg(u_ddr_phy_init_n_127), .num_samples_done_r(num_samples_done_r), .ocal_last_byte_done(ocal_last_byte_done), .ocd_prech_req(ocd_prech_req), .oclk_calib_resume_level_reg_0(u_ddr_phy_init_n_102), .oclk_calib_resume_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ), .oclk_calib_resume_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ), .oclkdelay_calib_done_r_reg(u_ddr_prbs_gen_n_40), .oclkdelay_calib_done_r_reg_0(u_ddr_prbs_gen_n_39), .oclkdelay_calib_done_r_reg_1(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ), .oclkdelay_calib_done_r_reg_2(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_calib_done_r_reg_3(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ), .oclkdelay_calib_done_r_reg_4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_81 ), .oclkdelay_calib_done_r_reg_5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ), .oclkdelay_center_calib_done_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .oclkdelay_center_calib_start_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ), .oclkdelay_center_calib_start_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ), .oclkdelay_int_ref_req_reg_0(u_ddr_phy_init_n_477), .\oclkdelay_ref_cnt_reg[13]_0 (u_ddr_phy_init_n_24), .\odd_cwl.phy_cas_n_reg[1]_0 (u_ddr_phy_init_n_109), .\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_116), .out(out), .p_81_in(p_81_in), .\phy_ctl_wd_i1_reg[24] (\phy_ctl_wd_i1_reg[24] ), .phy_dout(phy_dout[31:0]), .phy_if_empty_r_reg(u_ddr_prbs_gen_n_0), .phy_rddata_en_1(phy_rddata_en_1), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .pi_calib_done(pi_calib_done), .\pi_dqs_found_all_bank_reg[1] (u_ddr_phy_init_n_501), .\pi_dqs_found_all_bank_reg[1]_0 (pi_dqs_found_all_bank), .pi_dqs_found_done_r1(pi_dqs_found_done_r1), .pi_dqs_found_done_r1_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ), .pi_dqs_found_done_r1_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ), .pi_dqs_found_done_r1_reg_2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ), .pi_dqs_found_done_r1_reg_3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ), .pi_dqs_found_done_r1_reg_4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ), .pi_dqs_found_done_r1_reg_5(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ), .pi_dqs_found_done_r1_reg_6(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ), .pi_dqs_found_done_r1_reg_7(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .prbs_last_byte_done(prbs_last_byte_done), .prbs_last_byte_done_r(prbs_last_byte_done_r), .prbs_last_byte_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ), .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0), .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prbs_rdlvl_done_reg_rep_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ), .prbs_rdlvl_done_reg_rep_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ), .prbs_rdlvl_done_reg_rep_2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ), .prbs_rdlvl_done_reg_rep_3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ), .prbs_rdlvl_prech_req_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ), .prbs_rdlvl_start_r(prbs_rdlvl_start_r), .prbs_rdlvl_start_r_reg(prbs_rdlvl_start_r_reg), .prech_done(prech_done), .prech_pending_r(prech_pending_r), .prech_pending_r_reg_0(u_ddr_phy_init_n_9), .prech_pending_r_reg_1(u_ddr_phy_init_n_468), .prech_req(prech_req), .prech_req_posedge_r_reg_0(prech_pending_r_i_1_n_0), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] (rd_data_offset_ranks_0), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (rd_data_offset_ranks_1), .\rd_addr_reg[0] (u_ddr_phy_init_n_786), .\rd_addr_reg[3] (u_ddr_prbs_gen_n_57), .\rd_addr_reg_rep[7] (u_ddr_phy_init_n_785), .\rd_byte_data_offset_reg[0][3] ({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_69 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_70 }), .\rd_byte_data_offset_reg[0][9] (p_0_in_0), .\rd_ptr_reg[3] ({\rd_ptr_reg[3] [37:6],\rd_ptr_reg[3] [4],\rd_ptr_reg[3] [1]}), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 [11:4]), .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ), .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_2 ), .\rd_ptr_reg[3]_3 (\rd_ptr_reg[3]_3 ), .\rd_ptr_reg[3]_4 (\rd_ptr_reg[3]_4 ), .\rd_ptr_reg[3]_5 (\rd_ptr_reg[3]_5 ), .\rd_ptr_timing_reg[0] (\rd_ptr_timing_reg[0]_0 ), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0]_1 ), .\rd_ptr_timing_reg[0]_1 (\rd_ptr_timing_reg[0]_2 ), .\rd_ptr_timing_reg[0]_2 (\rd_ptr_timing_reg[0]_3 ), .\rd_ptr_timing_reg[0]_3 (\rd_ptr_timing_reg[0]_4 ), .\rd_victim_sel_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ), .\rd_victim_sel_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ), .\rd_victim_sel_reg[2] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ), .rdlvl_last_byte_done(rdlvl_last_byte_done), .rdlvl_pi_incdec(rdlvl_pi_incdec), .rdlvl_prech_req(rdlvl_prech_req), .rdlvl_start_dly0_r(rdlvl_start_dly0_r), .\rdlvl_start_dly0_r_reg[14]_0 (rdlvl_stg1_start_i_1_n_0), .rdlvl_start_pre(rdlvl_start_pre), .rdlvl_start_pre_reg_0(u_ddr_phy_init_n_469), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_done_int_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ), .rdlvl_stg1_done_int_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ), .rdlvl_stg1_done_int_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ), .rdlvl_stg1_done_int_reg_3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ), .rdlvl_stg1_done_int_reg_4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ), .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done), .rdlvl_stg1_start_int(rdlvl_stg1_start_int), .rdlvl_stg1_start_r_reg(u_ddr_phy_init_n_33), .read_calib_reg_0(u_ddr_phy_init_n_470), .\reg_ctrl_cnt_r_reg[3]_0 (u_ddr_phy_init_n_115), .reset_if(reset_if), .reset_if_r9(reset_if_r9), .reset_if_reg(u_ddr_phy_init_n_101), .reset_rd_addr(reset_rd_addr), .reset_rd_addr0(reset_rd_addr0), .\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__17[0]), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0), .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .\samples_cnt_r_reg[11] (samples_cnt_r), .\samples_cnt_r_reg[11]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ), .stg1_wr_done(stg1_wr_done), .temp_lmr_done(temp_lmr_done), .\victim_sel_rotate.sel_reg[31] ({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}), .wl_sm_start(wl_sm_start), .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .wr_level_start_r_reg(u_ddr_phy_init_n_790), .wrcal_done_reg(u_ddr_phy_wrcal_n_103), .wrcal_done_reg_0(u_ddr_phy_wrcal_n_83), .wrcal_done_reg_1(u_ddr_phy_wrcal_n_84), .wrcal_done_reg_10(u_ddr_phy_wrcal_n_82), .wrcal_done_reg_11(u_ddr_phy_wrcal_n_81), .wrcal_done_reg_2(u_ddr_phy_wrcal_n_104), .wrcal_done_reg_3(u_ddr_prbs_gen_n_34), .wrcal_done_reg_4(u_ddr_prbs_gen_n_33), .wrcal_done_reg_5(u_ddr_prbs_gen_n_32), .wrcal_done_reg_6(u_ddr_prbs_gen_n_31), .wrcal_done_reg_7(u_ddr_prbs_gen_n_30), .wrcal_done_reg_8(u_ddr_prbs_gen_n_29), .wrcal_done_reg_9(u_ddr_phy_wrcal_n_93), .\wrcal_dqs_cnt_r_reg[0] (u_ddr_phy_init_n_784), .wrcal_prech_req(wrcal_prech_req), .wrcal_rd_wait(wrcal_rd_wait), .wrcal_resume_r(wrcal_resume_r), .wrcal_resume_w(wrcal_resume_w), .wrcal_sanity_chk(wrcal_sanity_chk), .wrcal_sanity_chk_done_reg(u_ddr_phy_wrcal_n_96), .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71), .wrcal_sanity_chk_r_reg(u_ddr_phy_wrcal_n_5), .wrcal_start_reg_0(u_ddr_phy_init_n_791), .\write_buffer.wr_buf_out_data_reg[255] (Q[255:0]), .write_request_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95), .wrlvl_byte_redo_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_final_if_rst(wrlvl_final_if_rst), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_mux_reg(u_ddr_phy_wrcal_n_90), .wrlvl_final_mux_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ), .wrlvl_rank_done(wrlvl_rank_done)); ddr3_ifmig_7series_v4_0_ddr_phy_wrcal u_ddr_phy_wrcal (.CLK(CLK), .\FSM_sequential_wl_state_r_reg[0] (u_ddr_phy_wrcal_n_102), .LD0(LD0), .LD0_0(LD0_0), .LD0_1(LD0_1), .LD0_2(LD0_2), .Q(calib_zero_inputs__0), .cal2_done_r(cal2_done_r), .cal2_done_r_reg_0(u_ddr_phy_wrcal_n_117), .cal2_if_reset_reg_0(u_ddr_phy_wrcal_n_114), .cal2_if_reset_reg_1(u_ddr_phy_wrcal_n_115), .cal2_if_reset_reg_2(u_ddr_phy_wrcal_n_120), .\cal2_state_r_reg[0]_0 (idelay_ld_done_i_1_n_0), .\cal2_state_r_reg[0]_1 (cal2_if_reset_i_1_n_0), .\cal2_state_r_reg[2]_0 (wrcal_pat_resume_r_i_1_n_0), .\cal2_state_r_reg[3]_0 (wrcal_sanity_chk_done_i_2_n_0), .calib_in_common(calib_in_common), .\calib_sel_reg[1] (\po_rdval_cnt_reg[8] [1:0]), .\corse_cnt_reg[0][2] (u_ddr_phy_wrcal_n_100), .\corse_cnt_reg[1][2] (u_ddr_phy_wrcal_n_97), .\corse_cnt_reg[2][2] (u_ddr_phy_wrcal_n_98), .ddr3_lm_done_r(ddr3_lm_done_r), .done_dqs_dec239_out(done_dqs_dec239_out), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .dqs_found_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ), .early1_data_reg_0(u_ddr_phy_wrcal_n_67), .early1_data_reg_1(u_ddr_phy_wrcal_n_73), .early1_data_reg_2(u_ddr_phy_wrcal_n_119), .early2_data_reg_0(u_ddr_phy_wrcal_n_66), .early2_data_reg_1(u_ddr_phy_wrcal_n_74), .\final_coarse_tap_reg[3][2] (final_coarse_tap), .first_wrcal_pat_r(first_wrcal_pat_r), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_phy_wrcal_n_105), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (u_ddr_phy_wrcal_n_106), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_phy_wrcal_n_107), .\gen_pat_match_div4.early1_data_match_r_reg_0 (early1_data_i_1_n_0), .\gen_pat_match_div4.early1_data_match_r_reg_1 (early2_data_i_1_n_0), .\gen_pat_match_div4.early2_data_match_r_reg_0 (wrlvl_byte_redo_i_1_n_0), .\gen_pat_match_div4.pat_data_match_valid_r_reg_0 (idelay_ld_i_1_n_0), .\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 (\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 (\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 (\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 (\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 (\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 (\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 (\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 (\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 (\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 (\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 (\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 (\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 (\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 (\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 (\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 (\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 (\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 (\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 (\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 (\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 (\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 (\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 (\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 (\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 (\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 (\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 (\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ), .\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 (\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 (\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 (\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 (\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 (\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 (\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 (\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 (\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 (\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 (\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 (\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 (\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 (\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 (\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 (\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 (\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 (\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 (\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 (\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 (\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 (\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 (\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 (\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 (\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 (\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 (\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 (\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 (\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 (\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 (\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ), .\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 (\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 (\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 (\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .idelay_ce_int(idelay_ce_int), .idelay_ld(idelay_ld), .idelay_ld_done_reg_0(u_ddr_phy_wrcal_n_113), .idelay_ld_reg_0(u_ddr_phy_wrcal_n_4), .idelay_ld_reg_1(u_ddr_phy_wrcal_n_116), .idelay_ld_rst(idelay_ld_rst), .idelay_ld_rst_3(idelay_ld_rst_3), .idelay_ld_rst_4(idelay_ld_rst_4), .idelay_ld_rst_5(idelay_ld_rst_5), .\idelay_tap_cnt_r_reg[0][1][0] (u_ddr_phy_wrcal_n_89), .\idelay_tap_cnt_r_reg[0][2][0] (u_ddr_phy_wrcal_n_85), .\idelay_tap_cnt_r_reg[0][2][0]_0 ({po_stg2_wrcal_cnt,\idelay_tap_cnt_r_reg[0][3][0] }), .\init_state_r_reg[0] (u_ddr_phy_wrcal_n_90), .\init_state_r_reg[0]_0 (u_ddr_phy_wrcal_n_93), .\init_state_r_reg[0]_1 (u_ddr_phy_wrcal_n_94), .\init_state_r_reg[0]_2 (u_ddr_phy_wrcal_n_96), .\init_state_r_reg[2] (u_ddr_phy_wrcal_n_91), .\init_state_r_reg[3] (u_ddr_phy_wrcal_n_81), .\init_state_r_reg[4] (u_ddr_phy_wrcal_n_92), .\init_state_r_reg[5] (u_ddr_phy_wrcal_n_95), .mem_init_done_r(mem_init_done_r), .mpr_last_byte_done(mpr_last_byte_done), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .\not_empty_wait_cnt_reg[0]_0 ({u_ddr_phy_wrcal_n_108,u_ddr_phy_wrcal_n_109,u_ddr_phy_wrcal_n_110,u_ddr_phy_wrcal_n_111}), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_calib_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .p_0_out(p_0_out), .phy_if_reset_w(phy_if_reset_w), .phy_rddata_en_1(phy_rddata_en_1), .phy_rddata_en_r1_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ), .\po_stg2_wrcal_cnt_reg[1]_0 (\po_stg2_wrcal_cnt_reg[1] ), .\po_stg2_wrcal_cnt_reg[1]_1 (\po_stg2_wrcal_cnt_reg[1]_0 ), .\po_stg2_wrcal_cnt_reg[1]_10 (\po_stg2_wrcal_cnt_reg[1]_9 ), .\po_stg2_wrcal_cnt_reg[1]_11 (\po_stg2_wrcal_cnt_reg[1]_10 ), .\po_stg2_wrcal_cnt_reg[1]_12 (\po_stg2_wrcal_cnt_reg[1]_11 ), .\po_stg2_wrcal_cnt_reg[1]_13 (\po_stg2_wrcal_cnt_reg[1]_12 ), .\po_stg2_wrcal_cnt_reg[1]_14 (\po_stg2_wrcal_cnt_reg[1]_13 ), .\po_stg2_wrcal_cnt_reg[1]_15 (\po_stg2_wrcal_cnt_reg[1]_14 ), .\po_stg2_wrcal_cnt_reg[1]_16 (\po_stg2_wrcal_cnt_reg[1]_15 ), .\po_stg2_wrcal_cnt_reg[1]_17 (\po_stg2_wrcal_cnt_reg[1]_16 ), .\po_stg2_wrcal_cnt_reg[1]_18 (\po_stg2_wrcal_cnt_reg[1]_17 ), .\po_stg2_wrcal_cnt_reg[1]_19 (\po_stg2_wrcal_cnt_reg[1]_18 ), .\po_stg2_wrcal_cnt_reg[1]_2 (\po_stg2_wrcal_cnt_reg[1]_1 ), .\po_stg2_wrcal_cnt_reg[1]_20 (\po_stg2_wrcal_cnt_reg[1]_19 ), .\po_stg2_wrcal_cnt_reg[1]_21 (\po_stg2_wrcal_cnt_reg[1]_20 ), .\po_stg2_wrcal_cnt_reg[1]_22 (\po_stg2_wrcal_cnt_reg[1]_21 ), .\po_stg2_wrcal_cnt_reg[1]_23 (\po_stg2_wrcal_cnt_reg[1]_22 ), .\po_stg2_wrcal_cnt_reg[1]_24 (\po_stg2_wrcal_cnt_reg[1]_23 ), .\po_stg2_wrcal_cnt_reg[1]_25 (\po_stg2_wrcal_cnt_reg[1]_24 ), .\po_stg2_wrcal_cnt_reg[1]_26 (\po_stg2_wrcal_cnt_reg[1]_25 ), .\po_stg2_wrcal_cnt_reg[1]_27 (\po_stg2_wrcal_cnt_reg[1]_26 ), .\po_stg2_wrcal_cnt_reg[1]_28 (\po_stg2_wrcal_cnt_reg[1]_27 ), .\po_stg2_wrcal_cnt_reg[1]_29 (\po_stg2_wrcal_cnt_reg[1]_28 ), .\po_stg2_wrcal_cnt_reg[1]_3 (\po_stg2_wrcal_cnt_reg[1]_2 ), .\po_stg2_wrcal_cnt_reg[1]_30 (\po_stg2_wrcal_cnt_reg[1]_29 ), .\po_stg2_wrcal_cnt_reg[1]_31 (\po_stg2_wrcal_cnt_reg[1]_30 ), .\po_stg2_wrcal_cnt_reg[1]_32 (\po_stg2_wrcal_cnt_reg[1]_31 ), .\po_stg2_wrcal_cnt_reg[1]_33 (\po_stg2_wrcal_cnt_reg[1]_32 ), .\po_stg2_wrcal_cnt_reg[1]_34 (\po_stg2_wrcal_cnt_reg[1]_33 ), .\po_stg2_wrcal_cnt_reg[1]_35 (\po_stg2_wrcal_cnt_reg[1]_34 ), .\po_stg2_wrcal_cnt_reg[1]_36 (\po_stg2_wrcal_cnt_reg[1]_35 ), .\po_stg2_wrcal_cnt_reg[1]_37 (\po_stg2_wrcal_cnt_reg[1]_36 ), .\po_stg2_wrcal_cnt_reg[1]_38 (\po_stg2_wrcal_cnt_reg[1]_37 ), .\po_stg2_wrcal_cnt_reg[1]_39 (\po_stg2_wrcal_cnt_reg[1]_38 ), .\po_stg2_wrcal_cnt_reg[1]_4 (\po_stg2_wrcal_cnt_reg[1]_3 ), .\po_stg2_wrcal_cnt_reg[1]_40 (\po_stg2_wrcal_cnt_reg[1]_39 ), .\po_stg2_wrcal_cnt_reg[1]_41 (\po_stg2_wrcal_cnt_reg[1]_40 ), .\po_stg2_wrcal_cnt_reg[1]_42 (\po_stg2_wrcal_cnt_reg[1]_41 ), .\po_stg2_wrcal_cnt_reg[1]_43 (\po_stg2_wrcal_cnt_reg[1]_42 ), .\po_stg2_wrcal_cnt_reg[1]_44 (\po_stg2_wrcal_cnt_reg[1]_43 ), .\po_stg2_wrcal_cnt_reg[1]_45 (\po_stg2_wrcal_cnt_reg[1]_44 ), .\po_stg2_wrcal_cnt_reg[1]_46 (\po_stg2_wrcal_cnt_reg[1]_45 ), .\po_stg2_wrcal_cnt_reg[1]_47 (\po_stg2_wrcal_cnt_reg[1]_46 ), .\po_stg2_wrcal_cnt_reg[1]_48 (\po_stg2_wrcal_cnt_reg[1]_47 ), .\po_stg2_wrcal_cnt_reg[1]_49 (\po_stg2_wrcal_cnt_reg[1]_48 ), .\po_stg2_wrcal_cnt_reg[1]_5 (\po_stg2_wrcal_cnt_reg[1]_4 ), .\po_stg2_wrcal_cnt_reg[1]_50 (\po_stg2_wrcal_cnt_reg[1]_49 ), .\po_stg2_wrcal_cnt_reg[1]_51 (\po_stg2_wrcal_cnt_reg[1]_50 ), .\po_stg2_wrcal_cnt_reg[1]_52 (\po_stg2_wrcal_cnt_reg[1]_51 ), .\po_stg2_wrcal_cnt_reg[1]_53 (\po_stg2_wrcal_cnt_reg[1]_52 ), .\po_stg2_wrcal_cnt_reg[1]_54 (\po_stg2_wrcal_cnt_reg[1]_53 ), .\po_stg2_wrcal_cnt_reg[1]_55 (\po_stg2_wrcal_cnt_reg[1]_54 ), .\po_stg2_wrcal_cnt_reg[1]_56 (\po_stg2_wrcal_cnt_reg[1]_55 ), .\po_stg2_wrcal_cnt_reg[1]_57 (\po_stg2_wrcal_cnt_reg[1]_56 ), .\po_stg2_wrcal_cnt_reg[1]_58 (\po_stg2_wrcal_cnt_reg[1]_57 ), .\po_stg2_wrcal_cnt_reg[1]_59 (\po_stg2_wrcal_cnt_reg[1]_58 ), .\po_stg2_wrcal_cnt_reg[1]_6 (\po_stg2_wrcal_cnt_reg[1]_5 ), .\po_stg2_wrcal_cnt_reg[1]_60 (\po_stg2_wrcal_cnt_reg[1]_59 ), .\po_stg2_wrcal_cnt_reg[1]_61 (\po_stg2_wrcal_cnt_reg[1]_60 ), .\po_stg2_wrcal_cnt_reg[1]_62 (\po_stg2_wrcal_cnt_reg[1]_61 ), .\po_stg2_wrcal_cnt_reg[1]_7 (\po_stg2_wrcal_cnt_reg[1]_6 ), .\po_stg2_wrcal_cnt_reg[1]_8 (\po_stg2_wrcal_cnt_reg[1]_7 ), .\po_stg2_wrcal_cnt_reg[1]_9 (\po_stg2_wrcal_cnt_reg[1]_8 ), .\prbs_dqs_cnt_r_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .\prbs_dqs_cnt_r_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prbs_rdlvl_done_reg_rep_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ), .prech_done(prech_done), .prech_req_posedge_r_reg(u_ddr_phy_init_n_9), .rd_active_r1(rd_active_r1), .rd_active_r2(rd_active_r2), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_done_int_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ), .rdlvl_stg1_start_int_reg(u_ddr_phy_init_n_475), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .wl_sm_start(wl_sm_start), .wrcal_done_reg_0(u_ddr_phy_wrcal_n_5), .wrcal_done_reg_1(u_ddr_phy_wrcal_n_82), .wrcal_pat_resume_r(wrcal_pat_resume_r), .wrcal_pat_resume_r_reg_0(u_ddr_phy_wrcal_n_69), .wrcal_pat_resume_r_reg_1(u_ddr_phy_wrcal_n_112), .wrcal_prech_req(wrcal_prech_req), .wrcal_rd_wait(wrcal_rd_wait), .wrcal_resume_r(wrcal_resume_r), .wrcal_resume_w(wrcal_resume_w), .wrcal_sanity_chk(wrcal_sanity_chk), .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71), .wrcal_sanity_chk_r_reg_0(cal2_done_r_i_1_n_0), .wrcal_sanity_chk_reg(u_ddr_phy_init_n_784), .wrcal_start_reg(u_ddr_phy_init_n_791), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_phy_wrcal_n_84), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_phy_wrcal_n_104), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_phy_wrcal_n_103), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_phy_wrcal_n_83), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_r(wrlvl_byte_redo_r), .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_118), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_final_mux(wrlvl_final_mux), .\wrlvl_redo_corse_inc_reg[2] (u_ddr_phy_wrcal_n_101)); ddr3_ifmig_7series_v4_0_ddr_prbs_gen u_ddr_prbs_gen (.CLK(CLK), .D({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}), .E(u_ddr_phy_init_n_786), .Q(u_ddr_prbs_gen_n_57), .SR(\rd_addr[7]_i_1_n_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ), .first_rdlvl_pat_r(first_rdlvl_pat_r), .\gen_mux_rd[0].compare_data_fall0_r1_reg[0] (u_ddr_prbs_gen_n_66), .\gen_mux_rd[0].compare_data_fall1_r1_reg[0] (u_ddr_prbs_gen_n_82), .\gen_mux_rd[0].compare_data_fall2_r1_reg[0] (u_ddr_prbs_gen_n_98), .\gen_mux_rd[0].compare_data_fall3_r1_reg[0] (u_ddr_prbs_gen_n_114), .\gen_mux_rd[0].compare_data_rise0_r1_reg[0] (u_ddr_prbs_gen_n_58), .\gen_mux_rd[0].compare_data_rise1_r1_reg[0] (u_ddr_prbs_gen_n_74), .\gen_mux_rd[0].compare_data_rise2_r1_reg[0] (u_ddr_prbs_gen_n_90), .\gen_mux_rd[0].compare_data_rise3_r1_reg[0] (u_ddr_prbs_gen_n_106), .\gen_mux_rd[1].compare_data_fall0_r1_reg[1] (u_ddr_prbs_gen_n_67), .\gen_mux_rd[1].compare_data_fall1_r1_reg[1] (u_ddr_prbs_gen_n_83), .\gen_mux_rd[1].compare_data_fall2_r1_reg[1] (u_ddr_prbs_gen_n_99), .\gen_mux_rd[1].compare_data_fall3_r1_reg[1] (u_ddr_prbs_gen_n_115), .\gen_mux_rd[1].compare_data_rise0_r1_reg[1] (u_ddr_prbs_gen_n_59), .\gen_mux_rd[1].compare_data_rise1_r1_reg[1] (u_ddr_prbs_gen_n_75), .\gen_mux_rd[1].compare_data_rise2_r1_reg[1] (u_ddr_prbs_gen_n_91), .\gen_mux_rd[1].compare_data_rise3_r1_reg[1] (u_ddr_prbs_gen_n_107), .\gen_mux_rd[2].compare_data_fall0_r1_reg[2] (u_ddr_prbs_gen_n_68), .\gen_mux_rd[2].compare_data_fall2_r1_reg[2] (u_ddr_prbs_gen_n_100), .\gen_mux_rd[2].compare_data_fall3_r1_reg[2] (u_ddr_prbs_gen_n_116), .\gen_mux_rd[2].compare_data_rise0_r1_reg[2] (u_ddr_prbs_gen_n_60), .\gen_mux_rd[2].compare_data_rise1_r1_reg[2] (u_ddr_prbs_gen_n_76), .\gen_mux_rd[2].compare_data_rise2_r1_reg[2] (u_ddr_prbs_gen_n_92), .\gen_mux_rd[2].compare_data_rise3_r1_reg[2] (u_ddr_prbs_gen_n_108), .\gen_mux_rd[3].compare_data_fall0_r1_reg[3] (u_ddr_prbs_gen_n_69), .\gen_mux_rd[3].compare_data_fall1_r1_reg[3] (u_ddr_prbs_gen_n_85), .\gen_mux_rd[3].compare_data_fall3_r1_reg[3] (u_ddr_prbs_gen_n_117), .\gen_mux_rd[3].compare_data_rise0_r1_reg[3] (u_ddr_prbs_gen_n_61), .\gen_mux_rd[3].compare_data_rise1_r1_reg[3] (u_ddr_prbs_gen_n_77), .\gen_mux_rd[3].compare_data_rise2_r1_reg[3] (u_ddr_prbs_gen_n_93), .\gen_mux_rd[3].compare_data_rise3_r1_reg[3] (u_ddr_prbs_gen_n_109), .\gen_mux_rd[4].compare_data_fall0_r1_reg[4] (u_ddr_prbs_gen_n_70), .\gen_mux_rd[4].compare_data_fall1_r1_reg[4] (u_ddr_prbs_gen_n_86), .\gen_mux_rd[4].compare_data_fall2_r1_reg[4] (u_ddr_prbs_gen_n_102), .\gen_mux_rd[4].compare_data_fall3_r1_reg[4] (u_ddr_prbs_gen_n_118), .\gen_mux_rd[4].compare_data_rise0_r1_reg[4] (u_ddr_prbs_gen_n_62), .\gen_mux_rd[4].compare_data_rise1_r1_reg[4] (u_ddr_prbs_gen_n_78), .\gen_mux_rd[4].compare_data_rise2_r1_reg[4] (u_ddr_prbs_gen_n_94), .\gen_mux_rd[4].compare_data_rise3_r1_reg[4] (u_ddr_prbs_gen_n_110), .\gen_mux_rd[5].compare_data_fall0_r1_reg[5] (u_ddr_prbs_gen_n_71), .\gen_mux_rd[5].compare_data_fall1_r1_reg[5] (u_ddr_prbs_gen_n_87), .\gen_mux_rd[5].compare_data_fall2_r1_reg[5] (u_ddr_prbs_gen_n_103), .\gen_mux_rd[5].compare_data_fall3_r1_reg[5] (u_ddr_prbs_gen_n_119), .\gen_mux_rd[5].compare_data_rise0_r1_reg[5] (u_ddr_prbs_gen_n_63), .\gen_mux_rd[5].compare_data_rise1_r1_reg[5] (u_ddr_prbs_gen_n_79), .\gen_mux_rd[5].compare_data_rise2_r1_reg[5] (u_ddr_prbs_gen_n_95), .\gen_mux_rd[5].compare_data_rise3_r1_reg[5] (u_ddr_prbs_gen_n_111), .\gen_mux_rd[6].compare_data_fall0_r1_reg[6] (u_ddr_prbs_gen_n_72), .\gen_mux_rd[6].compare_data_fall2_r1_reg[6] (u_ddr_prbs_gen_n_104), .\gen_mux_rd[6].compare_data_fall3_r1_reg[6] (u_ddr_prbs_gen_n_120), .\gen_mux_rd[6].compare_data_rise0_r1_reg[6] (u_ddr_prbs_gen_n_64), .\gen_mux_rd[6].compare_data_rise1_r1_reg[6] (u_ddr_prbs_gen_n_80), .\gen_mux_rd[6].compare_data_rise2_r1_reg[6] (u_ddr_prbs_gen_n_96), .\gen_mux_rd[6].compare_data_rise3_r1_reg[6] (u_ddr_prbs_gen_n_112), .\gen_mux_rd[7].compare_data_fall0_r1_reg[7] (u_ddr_prbs_gen_n_73), .\gen_mux_rd[7].compare_data_fall1_r1_reg[7] (u_ddr_prbs_gen_n_89), .\gen_mux_rd[7].compare_data_fall3_r1_reg[7] (u_ddr_prbs_gen_n_121), .\gen_mux_rd[7].compare_data_rise0_r1_reg[7] (u_ddr_prbs_gen_n_65), .\gen_mux_rd[7].compare_data_rise1_r1_reg[7] (u_ddr_prbs_gen_n_81), .\gen_mux_rd[7].compare_data_rise2_r1_reg[7] (u_ddr_prbs_gen_n_97), .\gen_mux_rd[7].compare_data_rise3_r1_reg[7] (u_ddr_prbs_gen_n_113), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .\rd_addr_reg[0]_0 (u_ddr_prbs_gen_n_0), .\rd_addr_reg[3]_0 (u_ddr_phy_init_n_785), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] (u_ddr_prbs_gen_n_1), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] (u_ddr_prbs_gen_n_29), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] (u_ddr_prbs_gen_n_84), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] (u_ddr_prbs_gen_n_30), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] (u_ddr_prbs_gen_n_2), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] (u_ddr_prbs_gen_n_31), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] (u_ddr_prbs_gen_n_88), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] (u_ddr_prbs_gen_n_32), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] (u_ddr_prbs_gen_n_22), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] (u_ddr_prbs_gen_n_42), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] (u_ddr_prbs_gen_n_15), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] (u_ddr_prbs_gen_n_52), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] (u_ddr_prbs_gen_n_21), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] (u_ddr_prbs_gen_n_41), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] (u_ddr_prbs_gen_n_16), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] (u_ddr_prbs_gen_n_51), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] (u_ddr_prbs_gen_n_33), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] (u_ddr_prbs_gen_n_39), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_prbs_gen_n_5), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] (u_ddr_prbs_gen_n_101), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] (u_ddr_prbs_gen_n_34), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] (u_ddr_prbs_gen_n_40), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] (u_ddr_prbs_gen_n_6), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_prbs_gen_n_105), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] (u_ddr_prbs_gen_n_35), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] (u_ddr_prbs_gen_n_50), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] (u_ddr_prbs_gen_n_20), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] (u_ddr_prbs_gen_n_36), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] (u_ddr_prbs_gen_n_37), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_prbs_gen_n_49), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] (u_ddr_prbs_gen_n_19), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] (u_ddr_prbs_gen_n_38), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] (u_ddr_prbs_gen_n_47), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] (u_ddr_prbs_gen_n_3), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] (u_ddr_prbs_gen_n_9), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] (u_ddr_prbs_gen_n_7), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] (u_ddr_prbs_gen_n_48), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] (u_ddr_prbs_gen_n_4), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] (u_ddr_prbs_gen_n_8), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] (u_ddr_prbs_gen_n_23), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] (u_ddr_prbs_gen_n_26), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] (u_ddr_prbs_gen_n_10), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] (u_ddr_prbs_gen_n_11), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] (u_ddr_prbs_gen_n_24), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] (u_ddr_prbs_gen_n_25), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] (u_ddr_prbs_gen_n_12), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (u_ddr_prbs_gen_n_55), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] (u_ddr_prbs_gen_n_43), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] (u_ddr_prbs_gen_n_44), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] (u_ddr_prbs_gen_n_56), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] (u_ddr_prbs_gen_n_45), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] (u_ddr_prbs_gen_n_46), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] (u_ddr_prbs_gen_n_54), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] (u_ddr_prbs_gen_n_13), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] (u_ddr_prbs_gen_n_17), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_prbs_gen_n_27), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] (u_ddr_prbs_gen_n_53), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] (u_ddr_prbs_gen_n_14), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] (u_ddr_prbs_gen_n_18), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] (u_ddr_prbs_gen_n_28)); LUT6 #( .INIT(64'hEEBAFFFF00001000)) wl_edge_detect_valid_r_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ), .I4(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I5(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ), .O(wl_edge_detect_valid_r_i_1_n_0)); LUT5 #( .INIT(32'hA2A200A2)) wr_level_done_i_1 (.I0(done_dqs_tap_inc), .I1(wrlvl_final_mux), .I2(wrlvl_final_r), .I3(wrlvl_byte_redo), .I4(wrlvl_byte_redo_r), .O(wr_level_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFF0200000002)) wr_level_done_r_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I4(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ), .I5(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ), .O(wr_level_done_r_i_1_n_0)); LUT5 #( .INIT(32'hF8FFF800)) wrcal_pat_resume_r_i_1 (.I0(u_ddr_phy_wrcal_n_109), .I1(u_ddr_phy_wrcal_n_69), .I2(u_ddr_phy_wrcal_n_110), .I3(u_ddr_phy_wrcal_n_112), .I4(wrcal_pat_resume_r), .O(wrcal_pat_resume_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00004000)) wrcal_sanity_chk_done_i_2 (.I0(u_ddr_phy_wrcal_n_108), .I1(u_ddr_phy_wrcal_n_109), .I2(u_ddr_phy_wrcal_n_5), .I3(u_ddr_phy_wrcal_n_110), .I4(u_ddr_phy_wrcal_n_111), .I5(u_ddr_phy_wrcal_n_71), .O(wrcal_sanity_chk_done_i_2_n_0)); LUT6 #( .INIT(64'h0EFFFFFF0E000000)) wrlvl_byte_redo_i_1 (.I0(u_ddr_phy_wrcal_n_66), .I1(u_ddr_phy_wrcal_n_67), .I2(u_ddr_phy_wrcal_n_110), .I3(u_ddr_phy_wrcal_n_118), .I4(u_ddr_phy_wrcal_n_111), .I5(wrlvl_byte_redo), .O(wrlvl_byte_redo_i_1_n_0)); FDRE #( .INIT(1'b0)) wrlvl_final_mux_reg (.C(CLK), .CE(1'b1), .D(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .Q(wrlvl_final_mux), .R(1'b0)); LUT5 #( .INIT(32'h40FF4000)) wrlvl_rank_done_r_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ), .I4(wrlvl_rank_done), .O(wrlvl_rank_done_r_i_1_n_0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_if_post_fifo (\not_strict_mode.app_rd_data_reg[228] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[0] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[231]_0 , mux_rd_valid_r_reg, \not_strict_mode.app_rd_data_reg[7]_0 , D_byte_rd_en, ififo_rst, CLK, if_empty_r_1, \read_fifo.fifo_out_data_r_reg[6] , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \my_empty_reg[4]_0 , if_empty_r, Q, C_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4]_1 ); output \not_strict_mode.app_rd_data_reg[228] ; output [63:0]\not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[0] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[231]_0 ; output mux_rd_valid_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output D_byte_rd_en; input ififo_rst; input CLK; input [0:0]if_empty_r_1; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [0:0]\my_empty_reg[4]_0 ; input [0:0]if_empty_r; input [65:0]Q; input C_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4]_1 ; wire A_byte_rd_en; wire CLK; wire C_byte_rd_en; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_byte_rd_en; wire [65:0]Q; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire [0:0]if_empty_r_1; wire ififo_rst; wire [71:9]mem_out; wire mem_reg_0_3_6_11_n_0; wire mem_reg_0_3_6_11_n_1; wire mux_rd_valid_r_reg; wire [3:0]my_empty; wire \my_empty[4]_i_1_n_0 ; wire \my_empty[4]_i_2__2_n_0 ; wire [0:0]\my_empty_reg[4]_0 ; wire [0:0]\my_empty_reg[4]_1 ; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1__2_n_0 ; wire \my_full[0]_i_2__2_n_0 ; wire \my_full[1]_i_1__2_n_0 ; wire \my_full[1]_i_2__2_n_0 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire [63:0]\not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[231]_0 ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1__2_n_0 ; wire \rd_ptr[1]_i_1__2_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__6_n_0 ; wire \rd_ptr_timing[1]_i_1__7_n_0 ; wire \read_fifo.fifo_out_data_r_reg[6] ; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__8_n_0 ; wire \wr_ptr[1]_i_1__8_n_0 ; wire \wr_ptr[1]_i_3__2_n_0 ; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair887" *) LUT4 #( .INIT(16'hF888)) i___55_i_2 (.I0(my_empty[0]), .I1(if_empty_r_1), .I2(\my_empty_reg[4]_0 ), .I3(if_empty_r), .O(mux_rd_valid_r_reg)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(mem_out[65:64]), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_66_71 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[67:66]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}), .DOB({mem_out[9],\not_strict_mode.app_rd_data_reg[7]_0 }), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_6_11_i_1__1 (.I0(if_empty_r_1), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3__2_n_0 ), .I3(my_empty[2]), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair920" *) LUT1 #( .INIT(2'h2)) mem_reg_0_3_6_11_i_2__1 (.I0(my_empty[0]), .O(my_empty[2])); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1 (.I0(my_full[1]), .I1(if_empty_r_1), .I2(\wr_ptr[1]_i_3__2_n_0 ), .I3(my_empty[1]), .O(\my_empty[4]_i_1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2__2 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty[1]), .O(\my_empty[4]_i_2__2_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1_n_0 ), .D(\my_empty[4]_i_2__2_n_0 ), .Q(my_empty[0]), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1_n_0 ), .D(\my_empty[4]_i_2__2_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1_n_0 ), .D(\my_empty[4]_i_2__2_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1__2 (.I0(my_full[0]), .I1(my_empty[1]), .I2(my_full[1]), .I3(if_empty_r_1), .I4(\wr_ptr[1]_i_3__2_n_0 ), .I5(\my_full[0]_i_2__2_n_0 ), .O(\my_full[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2__2 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2__2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1__2 (.I0(\my_full[1]_i_2__2_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair885" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2__2 (.I0(my_empty[1]), .I1(my_full[1]), .I2(if_empty_r_1), .I3(\wr_ptr[1]_i_3__2_n_0 ), .O(\my_full[1]_i_2__2_n_0 )); FDRE #( .INIT(1'b0)) \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1__2_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE #( .INIT(1'b0)) \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1__2_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair888" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[0] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOC[0]), .O(\not_strict_mode.app_rd_data_reg[231] [0])); (* SOFT_HLUTNM = "soft_lutpair902" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[100]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[100] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [28])); (* SOFT_HLUTNM = "soft_lutpair902" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[101]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[101] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [29])); (* SOFT_HLUTNM = "soft_lutpair903" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[102]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[102] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [30])); (* SOFT_HLUTNM = "soft_lutpair903" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[103]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[103] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [31])); (* SOFT_HLUTNM = "soft_lutpair904" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[128]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[128] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [32])); (* SOFT_HLUTNM = "soft_lutpair904" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[129]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[129] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [33])); (* SOFT_HLUTNM = "soft_lutpair905" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[130]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[130] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [34])); (* SOFT_HLUTNM = "soft_lutpair906" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[131]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[131] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [35])); (* SOFT_HLUTNM = "soft_lutpair905" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[132]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[132] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [36])); (* SOFT_HLUTNM = "soft_lutpair906" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[133]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[133] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [37])); (* SOFT_HLUTNM = "soft_lutpair907" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[134]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[134] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [38])); (* SOFT_HLUTNM = "soft_lutpair907" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[135]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[135] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [39])); (* SOFT_HLUTNM = "soft_lutpair908" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[160]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[160] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [40])); (* SOFT_HLUTNM = "soft_lutpair908" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[161]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[161] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [41])); (* SOFT_HLUTNM = "soft_lutpair909" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[162]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[162] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [42])); (* SOFT_HLUTNM = "soft_lutpair909" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[163]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[163] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [43])); (* SOFT_HLUTNM = "soft_lutpair910" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[164]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[164] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [44])); (* SOFT_HLUTNM = "soft_lutpair910" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[165]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[165] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [45])); (* SOFT_HLUTNM = "soft_lutpair911" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[166]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[166] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [46])); (* SOFT_HLUTNM = "soft_lutpair911" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[167]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[167] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [47])); (* SOFT_HLUTNM = "soft_lutpair912" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[192]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[192] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [48])); (* SOFT_HLUTNM = "soft_lutpair912" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[193]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[193] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [49])); (* SOFT_HLUTNM = "soft_lutpair913" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[194]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[194] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [50])); (* SOFT_HLUTNM = "soft_lutpair913" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[195]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[195] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [51])); (* SOFT_HLUTNM = "soft_lutpair914" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[196]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[196] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [52])); (* SOFT_HLUTNM = "soft_lutpair914" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[197]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[197] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [53])); (* SOFT_HLUTNM = "soft_lutpair915" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[198]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[198] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [54])); (* SOFT_HLUTNM = "soft_lutpair915" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[199]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[199] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [55])); (* SOFT_HLUTNM = "soft_lutpair889" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[1] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOC[1]), .O(\not_strict_mode.app_rd_data_reg[231] [1])); (* SOFT_HLUTNM = "soft_lutpair916" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[224]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[224] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [56])); (* SOFT_HLUTNM = "soft_lutpair916" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[225]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[225] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [57])); (* SOFT_HLUTNM = "soft_lutpair917" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[226]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[226] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [58])); (* SOFT_HLUTNM = "soft_lutpair917" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[227]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[227] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [59])); (* SOFT_HLUTNM = "soft_lutpair918" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[228]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[228]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [60])); (* SOFT_HLUTNM = "soft_lutpair918" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[229]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[229] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [61])); (* SOFT_HLUTNM = "soft_lutpair919" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[230]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[230] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [62])); (* SOFT_HLUTNM = "soft_lutpair919" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[231]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[231]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [63])); (* SOFT_HLUTNM = "soft_lutpair890" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[2] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOB[0]), .O(\not_strict_mode.app_rd_data_reg[231] [2])); (* SOFT_HLUTNM = "soft_lutpair891" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[32]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[32] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [8])); (* SOFT_HLUTNM = "soft_lutpair892" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[33]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[33] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [9])); (* SOFT_HLUTNM = "soft_lutpair893" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[34]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[34] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [10])); (* SOFT_HLUTNM = "soft_lutpair893" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[35]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[35] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [11])); (* SOFT_HLUTNM = "soft_lutpair894" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[36]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[36] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [12])); (* SOFT_HLUTNM = "soft_lutpair894" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[37]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[37] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [13])); (* SOFT_HLUTNM = "soft_lutpair895" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[38]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[38] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [14])); (* SOFT_HLUTNM = "soft_lutpair895" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[39]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[39] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [15])); (* SOFT_HLUTNM = "soft_lutpair891" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[3] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOB[1]), .O(\not_strict_mode.app_rd_data_reg[231] [3])); (* SOFT_HLUTNM = "soft_lutpair892" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[4] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOA[0]), .O(\not_strict_mode.app_rd_data_reg[231] [4])); (* SOFT_HLUTNM = "soft_lutpair888" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[5] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOA[1]), .O(\not_strict_mode.app_rd_data_reg[231] [5])); (* SOFT_HLUTNM = "soft_lutpair896" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[64]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[64] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [16])); (* SOFT_HLUTNM = "soft_lutpair896" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[65]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[65] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [17])); (* SOFT_HLUTNM = "soft_lutpair897" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[66]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[66] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [18])); (* SOFT_HLUTNM = "soft_lutpair897" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[67]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[67] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [19])); (* SOFT_HLUTNM = "soft_lutpair898" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[68]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[68] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [20])); (* SOFT_HLUTNM = "soft_lutpair898" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[69]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[69] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [21])); (* SOFT_HLUTNM = "soft_lutpair889" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[6] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[231] [6])); (* SOFT_HLUTNM = "soft_lutpair899" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[70]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[70] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [22])); (* SOFT_HLUTNM = "soft_lutpair899" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[71]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[71] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [23])); (* SOFT_HLUTNM = "soft_lutpair890" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[7] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[231] [7])); (* SOFT_HLUTNM = "soft_lutpair900" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[96]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[96] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [24])); (* SOFT_HLUTNM = "soft_lutpair900" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[97]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[97] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [25])); (* SOFT_HLUTNM = "soft_lutpair901" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[98]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[98] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [26])); (* SOFT_HLUTNM = "soft_lutpair901" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[99]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[99] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [27])); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2 (.I0(Q[18]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[5] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3 (.I0(Q[26]), .I1(mem_out[32]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[4] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4 (.I0(Q[34]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[3] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5 (.I0(Q[42]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[2] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6 (.I0(Q[50]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[1] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7 (.I0(Q[58]), .I1(mem_out[64]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[0] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_8 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[228] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1 (.I0(Q[52]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[65] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2 (.I0(Q[60]), .I1(mem_out[66]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[64] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1 (.I0(Q[4]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[71] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2 (.I0(Q[12]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[70] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3 (.I0(Q[20]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[69] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4 (.I0(Q[28]), .I1(mem_out[34]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[68] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5 (.I0(Q[36]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[67] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6 (.I0(Q[44]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[66] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1 (.I0(Q[21]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[101] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2 (.I0(Q[29]), .I1(mem_out[35]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[100] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3 (.I0(Q[37]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[99] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4 (.I0(Q[45]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[98] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5 (.I0(Q[53]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[97] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6 (.I0(Q[61]), .I1(mem_out[67]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[96] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5 (.I0(Q[5]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[103] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6 (.I0(Q[13]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[102] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5 (.I0(Q[2]), .I1(\not_strict_mode.app_rd_data_reg[7]_0 ), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[7] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6 (.I0(Q[10]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[6] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1 (.I0(Q[38]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[131] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2 (.I0(Q[46]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[130] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3 (.I0(Q[54]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[129] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4 (.I0(Q[62]), .I1(mem_out[68]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[128] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3 (.I0(Q[6]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[135] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4 (.I0(Q[14]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[134] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5 (.I0(Q[22]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[133] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_6 (.I0(Q[30]), .I1(mem_out[36]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[132] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1 (.I0(Q[55]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[161] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2 (.I0(Q[63]), .I1(mem_out[69]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[160] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1 (.I0(Q[7]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[167] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2 (.I0(Q[15]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[166] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3 (.I0(Q[23]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[165] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4 (.I0(Q[31]), .I1(mem_out[37]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[164] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5 (.I0(Q[39]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[163] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_6 (.I0(Q[47]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[162] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1 (.I0(Q[24]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[197] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2 (.I0(Q[32]), .I1(mem_out[38]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[196] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3 (.I0(Q[40]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[195] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4 (.I0(Q[48]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[194] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5 (.I0(Q[56]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[193] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_6 (.I0(Q[64]), .I1(mem_out[70]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[192] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5 (.I0(Q[8]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[199] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_6 (.I0(Q[16]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[198] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1 (.I0(Q[41]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[227] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2 (.I0(Q[49]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[226] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3 (.I0(Q[57]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[225] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4 (.I0(Q[65]), .I1(mem_out[71]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[224] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3 (.I0(Q[9]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[231]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4 (.I0(Q[17]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[230] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5 (.I0(Q[25]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[229] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_6 (.I0(Q[33]), .I1(mem_out[39]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[228]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1 (.I0(Q[35]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[35] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2 (.I0(Q[43]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[34] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3 (.I0(Q[51]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[33] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4 (.I0(Q[59]), .I1(mem_out[65]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[32] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3 (.I0(Q[3]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[39] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4 (.I0(Q[11]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[38] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5 (.I0(Q[19]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[37] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6 (.I0(Q[27]), .I1(mem_out[33]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[36] )); (* SOFT_HLUTNM = "soft_lutpair886" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1__2 (.I0(my_empty[1]), .I1(\wr_ptr[1]_i_3__2_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair886" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1__2 (.I0(rd_ptr[0]), .I1(my_empty[1]), .I2(\wr_ptr[1]_i_3__2_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1__2_n_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1__2_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1__2_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__6 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3__2_n_0 ), .I2(my_empty[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__6_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__7 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3__2_n_0 ), .I4(my_empty[1]), .O(\rd_ptr_timing[1]_i_1__7_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__6_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__7_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair885" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__8 (.I0(if_empty_r_1), .I1(my_empty[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3__2_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__8_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__8 (.I0(wr_ptr[0]), .I1(if_empty_r_1), .I2(my_empty[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3__2_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair920" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2__2 (.I0(my_empty[0]), .O(my_empty[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3__2 (.I0(my_empty[3]), .I1(if_empty_r_1), .I2(C_byte_rd_en), .I3(A_byte_rd_en), .I4(if_empty_r_0), .I5(\my_empty_reg[4]_1 ), .O(\wr_ptr[1]_i_3__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair887" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_4__1 (.I0(my_empty[0]), .O(my_empty[3])); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_5__1 (.I0(if_empty_r_1), .I1(my_empty[3]), .O(D_byte_rd_en)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__8_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__8_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_4 (phy_if_empty_r_reg, \not_strict_mode.app_rd_data_reg[236] , \rd_ptr_timing_reg[1]_0 , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[239]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , C_byte_rd_en, ififo_rst, CLK, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , Q, D_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4]_0 ); output phy_if_empty_r_reg; output \not_strict_mode.app_rd_data_reg[236] ; output [0:0]\rd_ptr_timing_reg[1]_0 ; output [63:0]\not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[239]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output C_byte_rd_en; input ififo_rst; input CLK; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [65:0]Q; input D_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4]_0 ; wire A_byte_rd_en; wire CLK; wire C_byte_rd_en; wire D_byte_rd_en; wire [65:0]Q; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire [0:0]if_empty_r_0; wire ififo_rst; wire [71:9]mem_out; wire mem_reg_0_3_6_11_n_0; wire mem_reg_0_3_6_11_n_1; wire [2:1]my_empty; wire \my_empty[4]_i_1__0_n_0 ; wire \my_empty[4]_i_2__1_n_0 ; wire [0:0]\my_empty_reg[4]_0 ; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1__1_n_0 ; wire \my_full[0]_i_2__1_n_0 ; wire \my_full[1]_i_1__1_n_0 ; wire \my_full[1]_i_2__1_n_0 ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire [63:0]\not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[239]_0 ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ; wire phy_if_empty_r_reg; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1__1_n_0 ; wire \rd_ptr[1]_i_1__1_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__4_n_0 ; wire \rd_ptr_timing[1]_i_1__6_n_0 ; wire [0:0]\rd_ptr_timing_reg[1]_0 ; wire \read_fifo.fifo_out_data_r_reg[6] ; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__6_n_0 ; wire \wr_ptr[1]_i_1__6_n_0 ; wire \wr_ptr[1]_i_3__1_n_0 ; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(mem_out[65:64]), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_66_71 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[67:66]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}), .DOB({mem_out[9],\not_strict_mode.app_rd_data_reg[15]_0 }), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_6_11_i_1__0 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3__1_n_0 ), .I3(my_empty[2]), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair868" *) LUT1 #( .INIT(2'h2)) mem_reg_0_3_6_11_i_2__0 (.I0(phy_if_empty_r_reg), .O(my_empty[2])); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1__0 (.I0(my_full[1]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\wr_ptr[1]_i_3__1_n_0 ), .I3(my_empty[1]), .O(\my_empty[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2__1 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty[1]), .O(\my_empty[4]_i_2__1_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1__0_n_0 ), .D(\my_empty[4]_i_2__1_n_0 ), .Q(phy_if_empty_r_reg), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1__0_n_0 ), .D(\my_empty[4]_i_2__1_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1__0_n_0 ), .D(\my_empty[4]_i_2__1_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1__1 (.I0(my_full[0]), .I1(my_empty[1]), .I2(my_full[1]), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\wr_ptr[1]_i_3__1_n_0 ), .I5(\my_full[0]_i_2__1_n_0 ), .O(\my_full[0]_i_1__1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2__1 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2__1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1__1 (.I0(\my_full[1]_i_2__1_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair834" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2__1 (.I0(my_empty[1]), .I1(my_full[1]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\wr_ptr[1]_i_3__1_n_0 ), .O(\my_full[1]_i_2__1_n_0 )); FDRE #( .INIT(1'b0)) \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1__1_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE #( .INIT(1'b0)) \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1__1_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair848" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[104]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[104] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [24])); (* SOFT_HLUTNM = "soft_lutpair848" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[105]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[105] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [25])); (* SOFT_HLUTNM = "soft_lutpair849" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[106]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[106] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [26])); (* SOFT_HLUTNM = "soft_lutpair849" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[107]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[107] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [27])); (* SOFT_HLUTNM = "soft_lutpair850" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[108]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[108] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [28])); (* SOFT_HLUTNM = "soft_lutpair850" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[109]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[109] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [29])); (* SOFT_HLUTNM = "soft_lutpair838" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[10]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[10] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [2])); (* SOFT_HLUTNM = "soft_lutpair851" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[110]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[110] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [30])); (* SOFT_HLUTNM = "soft_lutpair851" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[111]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[111] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [31])); (* SOFT_HLUTNM = "soft_lutpair839" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[11]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[11] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [3])); (* SOFT_HLUTNM = "soft_lutpair840" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[12]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[12] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [4])); (* SOFT_HLUTNM = "soft_lutpair852" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[136]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[136] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [32])); (* SOFT_HLUTNM = "soft_lutpair852" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[137]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[137] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [33])); (* SOFT_HLUTNM = "soft_lutpair853" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[138]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[138] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [34])); (* SOFT_HLUTNM = "soft_lutpair853" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[139]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[139] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [35])); (* SOFT_HLUTNM = "soft_lutpair837" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[13]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[13] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [5])); (* SOFT_HLUTNM = "soft_lutpair854" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[140]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[140] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [36])); (* SOFT_HLUTNM = "soft_lutpair854" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[141]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[141] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [37])); (* SOFT_HLUTNM = "soft_lutpair855" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[142]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[142] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [38])); (* SOFT_HLUTNM = "soft_lutpair855" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[143]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[143] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [39])); (* SOFT_HLUTNM = "soft_lutpair838" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[14]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[14] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [6])); (* SOFT_HLUTNM = "soft_lutpair839" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[15]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[15] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [7])); (* SOFT_HLUTNM = "soft_lutpair856" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[168]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[168] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [40])); (* SOFT_HLUTNM = "soft_lutpair856" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[169]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[169] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [41])); (* SOFT_HLUTNM = "soft_lutpair857" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[170]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[170] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [42])); (* SOFT_HLUTNM = "soft_lutpair857" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[171]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[171] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [43])); (* SOFT_HLUTNM = "soft_lutpair858" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[172]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[172] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [44])); (* SOFT_HLUTNM = "soft_lutpair858" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[173]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[173] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [45])); (* SOFT_HLUTNM = "soft_lutpair859" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[174]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[174] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [46])); (* SOFT_HLUTNM = "soft_lutpair859" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[175]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[175] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [47])); (* SOFT_HLUTNM = "soft_lutpair860" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[200]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[200] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [48])); (* SOFT_HLUTNM = "soft_lutpair860" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[201]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[201] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [49])); (* SOFT_HLUTNM = "soft_lutpair861" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[202]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[202] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [50])); (* SOFT_HLUTNM = "soft_lutpair861" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[203]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[203] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [51])); (* SOFT_HLUTNM = "soft_lutpair862" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[204]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[204] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [52])); (* SOFT_HLUTNM = "soft_lutpair862" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[205]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[205] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [53])); (* SOFT_HLUTNM = "soft_lutpair863" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[206]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[206] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [54])); (* SOFT_HLUTNM = "soft_lutpair863" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[207]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[207] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [55])); (* SOFT_HLUTNM = "soft_lutpair864" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[232]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[232] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [56])); (* SOFT_HLUTNM = "soft_lutpair864" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[233]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[233] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [57])); (* SOFT_HLUTNM = "soft_lutpair865" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[234]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[234] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [58])); (* SOFT_HLUTNM = "soft_lutpair865" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[235]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[235] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [59])); (* SOFT_HLUTNM = "soft_lutpair866" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[236]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[236]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [60])); (* SOFT_HLUTNM = "soft_lutpair866" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[237]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[237] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [61])); (* SOFT_HLUTNM = "soft_lutpair867" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[238]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[238] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [62])); (* SOFT_HLUTNM = "soft_lutpair867" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[239]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[239]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [63])); (* SOFT_HLUTNM = "soft_lutpair836" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[40]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[40] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [8])); (* SOFT_HLUTNM = "soft_lutpair840" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[41]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[41] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [9])); (* SOFT_HLUTNM = "soft_lutpair841" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[42]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[42] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [10])); (* SOFT_HLUTNM = "soft_lutpair841" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[43]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[43] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [11])); (* SOFT_HLUTNM = "soft_lutpair842" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[44]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[44] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [12])); (* SOFT_HLUTNM = "soft_lutpair842" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[45]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[45] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [13])); (* SOFT_HLUTNM = "soft_lutpair843" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[46]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[46] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [14])); (* SOFT_HLUTNM = "soft_lutpair843" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[47]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[47] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [15])); (* SOFT_HLUTNM = "soft_lutpair844" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[72]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[72] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [16])); (* SOFT_HLUTNM = "soft_lutpair844" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[73]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[73] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [17])); (* SOFT_HLUTNM = "soft_lutpair845" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[74]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[74] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [18])); (* SOFT_HLUTNM = "soft_lutpair845" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[75]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[75] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [19])); (* SOFT_HLUTNM = "soft_lutpair846" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[76]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[76] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [20])); (* SOFT_HLUTNM = "soft_lutpair846" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[77]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[77] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [21])); (* SOFT_HLUTNM = "soft_lutpair847" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[78]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[78] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [22])); (* SOFT_HLUTNM = "soft_lutpair847" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[79]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[79] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [23])); (* SOFT_HLUTNM = "soft_lutpair836" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[8]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[8] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[239] [0])); (* SOFT_HLUTNM = "soft_lutpair837" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[9]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[9] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[239] [1])); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1 (.I0(Q[20]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[77] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2 (.I0(Q[28]), .I1(mem_out[34]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[76] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3 (.I0(Q[36]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[75] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4 (.I0(Q[44]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[74] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5 (.I0(Q[52]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[73] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6 (.I0(Q[60]), .I1(mem_out[66]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[72] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5 (.I0(Q[4]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[79] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6 (.I0(Q[12]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[78] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1 (.I0(Q[37]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[107] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2 (.I0(Q[45]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[106] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3 (.I0(Q[53]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[105] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4 (.I0(Q[61]), .I1(mem_out[67]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[104] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3 (.I0(Q[5]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[111] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4 (.I0(Q[13]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[110] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5 (.I0(Q[21]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[109] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6 (.I0(Q[29]), .I1(mem_out[35]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[108] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1 (.I0(Q[34]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[11] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2 (.I0(Q[42]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[10] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3 (.I0(Q[50]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[9] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4 (.I0(Q[58]), .I1(mem_out[64]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[8] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1 (.I0(Q[54]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[137] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2 (.I0(Q[62]), .I1(mem_out[68]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[136] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1 (.I0(Q[6]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[143] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2 (.I0(Q[14]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[142] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3 (.I0(Q[22]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[141] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4 (.I0(Q[30]), .I1(mem_out[36]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[140] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5 (.I0(Q[38]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[139] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_6 (.I0(Q[46]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[138] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1 (.I0(Q[23]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[173] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2 (.I0(Q[31]), .I1(mem_out[37]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[172] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3 (.I0(Q[39]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[171] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4 (.I0(Q[47]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[170] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5 (.I0(Q[55]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[169] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_6 (.I0(Q[63]), .I1(mem_out[69]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[168] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5 (.I0(Q[7]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[175] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_6 (.I0(Q[15]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[174] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3 (.I0(Q[2]), .I1(\not_strict_mode.app_rd_data_reg[15]_0 ), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[15] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4 (.I0(Q[10]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[14] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5 (.I0(Q[18]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[13] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6 (.I0(Q[26]), .I1(mem_out[32]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[12] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_8 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[236] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1 (.I0(Q[40]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[203] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2 (.I0(Q[48]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[202] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3 (.I0(Q[56]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[201] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4 (.I0(Q[64]), .I1(mem_out[70]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[200] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3 (.I0(Q[8]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[207] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4 (.I0(Q[16]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[206] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5 (.I0(Q[24]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[205] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_6 (.I0(Q[32]), .I1(mem_out[38]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[204] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1 (.I0(Q[57]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[233] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2 (.I0(Q[65]), .I1(mem_out[71]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[232] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1 (.I0(Q[9]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[239]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2 (.I0(Q[17]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[238] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3 (.I0(Q[25]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[237] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4 (.I0(Q[33]), .I1(mem_out[39]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[236]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5 (.I0(Q[41]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[235] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_6 (.I0(Q[49]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[234] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1 (.I0(Q[51]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[41] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2 (.I0(Q[59]), .I1(mem_out[65]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[40] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1 (.I0(Q[3]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[47] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2 (.I0(Q[11]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[46] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3 (.I0(Q[19]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[45] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4 (.I0(Q[27]), .I1(mem_out[33]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[44] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5 (.I0(Q[35]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[43] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6 (.I0(Q[43]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[42] )); (* SOFT_HLUTNM = "soft_lutpair835" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1__1 (.I0(my_empty[1]), .I1(\wr_ptr[1]_i_3__1_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair835" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1__1 (.I0(rd_ptr[0]), .I1(my_empty[1]), .I2(\wr_ptr[1]_i_3__1_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1__1_n_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1__1_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1__1_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__4 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3__1_n_0 ), .I2(my_empty[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__6 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3__1_n_0 ), .I4(my_empty[1]), .O(\rd_ptr_timing[1]_i_1__6_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__4_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__6_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair834" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__6 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3__1_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__6_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__6 (.I0(wr_ptr[0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(my_empty[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3__1_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__6_n_0 )); LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2__1 (.I0(phy_if_empty_r_reg), .O(my_empty[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3__1 (.I0(\rd_ptr_timing_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(D_byte_rd_en), .I3(A_byte_rd_en), .I4(if_empty_r_0), .I5(\my_empty_reg[4]_0 ), .O(\wr_ptr[1]_i_3__1_n_0 )); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_5__0 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\rd_ptr_timing_reg[1]_0 ), .O(C_byte_rd_en)); (* SOFT_HLUTNM = "soft_lutpair868" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_7 (.I0(phy_if_empty_r_reg), .O(\rd_ptr_timing_reg[1]_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__6_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__6_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_5 (\not_strict_mode.app_rd_data_reg[244] , \rd_ptr_timing_reg[1]_0 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , phy_rddata_en, mux_rd_valid_r_reg, \read_fifo.tail_r_reg[0] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[247]_0 , phy_if_empty_r_reg, \not_strict_mode.app_rd_data_reg[23]_0 , B_byte_rd_en, ififo_rst, CLK, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, if_empty_r_0, my_empty, \my_empty_reg[4]_0 , prbs_rdlvl_start_reg, out, tail_r, \read_fifo.fifo_out_data_r_reg[6]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , Q, D_byte_rd_en, A_byte_rd_en); output \not_strict_mode.app_rd_data_reg[244] ; output [0:0]\rd_ptr_timing_reg[1]_0 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output phy_rddata_en; output mux_rd_valid_r_reg; output \read_fifo.tail_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[247]_0 ; output phy_if_empty_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output B_byte_rd_en; input ififo_rst; input CLK; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input [0:0]if_empty_r_0; input [1:0]my_empty; input \my_empty_reg[4]_0 ; input prbs_rdlvl_start_reg; input out; input [0:0]tail_r; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [65:0]Q; input D_byte_rd_en; input A_byte_rd_en; wire A_byte_rd_en; wire B_byte_rd_en; wire CLK; wire D_byte_rd_en; wire [65:0]Q; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire [0:0]if_empty_r_0; wire ififo_rst; wire [71:9]mem_out; wire mem_reg_0_3_6_11_n_0; wire mem_reg_0_3_6_11_n_1; wire mux_rd_valid_r_reg; wire [1:0]my_empty; wire \my_empty[4]_i_1__1_n_0 ; wire \my_empty[4]_i_2__0_n_0 ; wire [2:0]my_empty_0; wire \my_empty_reg[4]_0 ; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1__0_n_0 ; wire \my_full[0]_i_2__0_n_0 ; wire \my_full[1]_i_1__0_n_0 ; wire \my_full[1]_i_2__0_n_0 ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire [63:0]\not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[247]_0 ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire out; wire phy_if_empty_r_reg; wire phy_rddata_en; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rd_buf_we; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1__0_n_0 ; wire \rd_ptr[1]_i_1__0_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__2_n_0 ; wire \rd_ptr_timing[1]_i_1__5_n_0 ; wire [0:0]\rd_ptr_timing_reg[1]_0 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]tail_r; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__4_n_0 ; wire \wr_ptr[1]_i_1__4_n_0 ; wire \wr_ptr[1]_i_3__0_n_0 ; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; LUT6 #( .INIT(64'h0000077700000000)) i___55_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .I5(out), .O(\not_strict_mode.status_ram.rd_buf_we_r1_reg )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(mem_out[65:64]), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_66_71 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[67:66]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}), .DOB({mem_out[9],\not_strict_mode.app_rd_data_reg[23]_0 }), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_6_11_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3__0_n_0 ), .I3(my_empty_0[2]), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair817" *) LUT1 #( .INIT(2'h2)) mem_reg_0_3_6_11_i_2 (.I0(my_empty_0[0]), .O(my_empty_0[2])); LUT6 #( .INIT(64'h0000077700000000)) mux_rd_valid_r_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .I5(prbs_rdlvl_start_reg), .O(mux_rd_valid_r_reg)); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1__1 (.I0(my_full[1]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\wr_ptr[1]_i_3__0_n_0 ), .I3(my_empty_0[1]), .O(\my_empty[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2__0 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty_0[1]), .O(\my_empty[4]_i_2__0_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1__1_n_0 ), .D(\my_empty[4]_i_2__0_n_0 ), .Q(my_empty_0[0]), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1__1_n_0 ), .D(\my_empty[4]_i_2__0_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1__1_n_0 ), .D(\my_empty[4]_i_2__0_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1__0 (.I0(my_full[0]), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\wr_ptr[1]_i_3__0_n_0 ), .I5(\my_full[0]_i_2__0_n_0 ), .O(\my_full[0]_i_1__0_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2__0 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2__0_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1__0 (.I0(\my_full[1]_i_2__0_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair783" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2__0 (.I0(my_empty_0[1]), .I1(my_full[1]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\wr_ptr[1]_i_3__0_n_0 ), .O(\my_full[1]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1__0_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE #( .INIT(1'b0)) \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1__0_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair797" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[112]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[112] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [24])); (* SOFT_HLUTNM = "soft_lutpair797" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[113]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[113] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [25])); (* SOFT_HLUTNM = "soft_lutpair798" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[114]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[114] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [26])); (* SOFT_HLUTNM = "soft_lutpair798" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[115]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[115] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [27])); (* SOFT_HLUTNM = "soft_lutpair799" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[116]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[116] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [28])); (* SOFT_HLUTNM = "soft_lutpair799" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[117]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[117] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [29])); (* SOFT_HLUTNM = "soft_lutpair800" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[118]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[118] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [30])); (* SOFT_HLUTNM = "soft_lutpair800" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[119]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[119] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [31])); (* SOFT_HLUTNM = "soft_lutpair801" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[144]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[144] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [32])); (* SOFT_HLUTNM = "soft_lutpair801" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[145]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[145] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [33])); (* SOFT_HLUTNM = "soft_lutpair802" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[146]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[146] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [34])); (* SOFT_HLUTNM = "soft_lutpair802" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[147]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[147] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [35])); (* SOFT_HLUTNM = "soft_lutpair803" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[148]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[148] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [36])); (* SOFT_HLUTNM = "soft_lutpair804" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[149]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[149] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [37])); (* SOFT_HLUTNM = "soft_lutpair803" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[150]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[150] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [38])); (* SOFT_HLUTNM = "soft_lutpair804" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[151]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[151] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [39])); (* SOFT_HLUTNM = "soft_lutpair785" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[16]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[16] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[247] [0])); (* SOFT_HLUTNM = "soft_lutpair805" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[176]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[176] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [40])); (* SOFT_HLUTNM = "soft_lutpair805" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[177]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[177] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [41])); (* SOFT_HLUTNM = "soft_lutpair806" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[178]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[178] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [42])); (* SOFT_HLUTNM = "soft_lutpair806" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[179]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[179] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [43])); (* SOFT_HLUTNM = "soft_lutpair786" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[17]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[17] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[247] [1])); (* SOFT_HLUTNM = "soft_lutpair807" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[180]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[180] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [44])); (* SOFT_HLUTNM = "soft_lutpair807" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[181]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[181] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [45])); (* SOFT_HLUTNM = "soft_lutpair808" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[182]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[182] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [46])); (* SOFT_HLUTNM = "soft_lutpair808" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[183]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[183] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [47])); (* SOFT_HLUTNM = "soft_lutpair787" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[18]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[18] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [2])); (* SOFT_HLUTNM = "soft_lutpair788" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[19]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[19] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [3])); (* SOFT_HLUTNM = "soft_lutpair809" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[208]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[208] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [48])); (* SOFT_HLUTNM = "soft_lutpair809" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[209]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[209] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [49])); (* SOFT_HLUTNM = "soft_lutpair789" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[20]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[20] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [4])); (* SOFT_HLUTNM = "soft_lutpair810" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[210]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[210] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [50])); (* SOFT_HLUTNM = "soft_lutpair810" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[211]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[211] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [51])); (* SOFT_HLUTNM = "soft_lutpair811" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[212]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[212] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [52])); (* SOFT_HLUTNM = "soft_lutpair811" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[213]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[213] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [53])); (* SOFT_HLUTNM = "soft_lutpair812" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[214]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[214] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [54])); (* SOFT_HLUTNM = "soft_lutpair812" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[215]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[215] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [55])); (* SOFT_HLUTNM = "soft_lutpair790" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[21]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[21] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [5])); (* SOFT_HLUTNM = "soft_lutpair791" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[22]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[22] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [6])); (* SOFT_HLUTNM = "soft_lutpair792" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[23]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[23] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [7])); (* SOFT_HLUTNM = "soft_lutpair813" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[240]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[240] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [56])); (* SOFT_HLUTNM = "soft_lutpair813" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[241]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[241] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [57])); (* SOFT_HLUTNM = "soft_lutpair814" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[242]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[242] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [58])); (* SOFT_HLUTNM = "soft_lutpair814" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[243]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[243] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [59])); (* SOFT_HLUTNM = "soft_lutpair815" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[244]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[244]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [60])); (* SOFT_HLUTNM = "soft_lutpair815" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[245]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[245] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [61])); (* SOFT_HLUTNM = "soft_lutpair816" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[246]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[246] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [62])); (* SOFT_HLUTNM = "soft_lutpair816" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[247]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[247]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [63])); (* SOFT_HLUTNM = "soft_lutpair785" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[48]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[48] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [8])); (* SOFT_HLUTNM = "soft_lutpair786" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[49]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[49] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [9])); (* SOFT_HLUTNM = "soft_lutpair787" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[50]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[50] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [10])); (* SOFT_HLUTNM = "soft_lutpair788" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[51]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[51] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [11])); (* SOFT_HLUTNM = "soft_lutpair789" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[52]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[52] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [12])); (* SOFT_HLUTNM = "soft_lutpair790" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[53]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[53] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [13])); (* SOFT_HLUTNM = "soft_lutpair791" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[54]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[54] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [14])); (* SOFT_HLUTNM = "soft_lutpair792" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[55]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[55] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [15])); (* SOFT_HLUTNM = "soft_lutpair793" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[80]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[80] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [16])); (* SOFT_HLUTNM = "soft_lutpair793" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[81]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[81] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [17])); (* SOFT_HLUTNM = "soft_lutpair794" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[82]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[82] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [18])); (* SOFT_HLUTNM = "soft_lutpair794" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[83]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[83] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [19])); (* SOFT_HLUTNM = "soft_lutpair795" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[84]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[84] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [20])); (* SOFT_HLUTNM = "soft_lutpair795" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[85]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[85] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [21])); (* SOFT_HLUTNM = "soft_lutpair796" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[86]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[86] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [22])); (* SOFT_HLUTNM = "soft_lutpair796" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[87]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[87] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [23])); LUT3 #( .INIT(8'h2F)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1 (.I0(\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(ram_init_done_r), .O(rd_buf_we)); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1 (.I0(Q[36]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[83] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2 (.I0(Q[44]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[82] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3 (.I0(Q[52]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[81] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4 (.I0(Q[60]), .I1(mem_out[66]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[80] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3 (.I0(Q[4]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[87] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4 (.I0(Q[12]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[86] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5 (.I0(Q[20]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[85] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6 (.I0(Q[28]), .I1(mem_out[34]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[84] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1 (.I0(Q[53]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[113] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2 (.I0(Q[61]), .I1(mem_out[67]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[112] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1 (.I0(Q[5]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[119] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2 (.I0(Q[13]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[118] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3 (.I0(Q[21]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[117] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4 (.I0(Q[29]), .I1(mem_out[35]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[116] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5 (.I0(Q[37]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[115] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6 (.I0(Q[45]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[114] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1 (.I0(Q[22]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[149] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2 (.I0(Q[30]), .I1(mem_out[36]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[148] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3 (.I0(Q[38]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[147] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4 (.I0(Q[46]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[146] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5 (.I0(Q[54]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[145] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_6 (.I0(Q[62]), .I1(mem_out[68]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[144] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5 (.I0(Q[6]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[151] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_6 (.I0(Q[14]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[150] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1 (.I0(Q[39]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[179] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2 (.I0(Q[47]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[178] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3 (.I0(Q[55]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[177] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4 (.I0(Q[63]), .I1(mem_out[69]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[176] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1 (.I0(Q[50]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[17] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2 (.I0(Q[58]), .I1(mem_out[64]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[16] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3 (.I0(Q[7]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[183] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4 (.I0(Q[15]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[182] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5 (.I0(Q[23]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[181] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_6 (.I0(Q[31]), .I1(mem_out[37]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[180] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1 (.I0(Q[56]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[209] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2 (.I0(Q[64]), .I1(mem_out[70]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[208] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1 (.I0(Q[8]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[215] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2 (.I0(Q[16]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[214] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3 (.I0(Q[24]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[213] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4 (.I0(Q[32]), .I1(mem_out[38]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[212] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5 (.I0(Q[40]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[211] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_6 (.I0(Q[48]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[210] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1 (.I0(Q[2]), .I1(\not_strict_mode.app_rd_data_reg[23]_0 ), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[23] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2 (.I0(Q[10]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[22] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3 (.I0(Q[18]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[21] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4 (.I0(Q[26]), .I1(mem_out[32]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[20] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5 (.I0(Q[34]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[19] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6 (.I0(Q[42]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[18] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[244] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1 (.I0(Q[25]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[245] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2 (.I0(Q[33]), .I1(mem_out[39]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[244]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3 (.I0(Q[41]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[243] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4 (.I0(Q[49]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[242] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5 (.I0(Q[57]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[241] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_6 (.I0(Q[65]), .I1(mem_out[71]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[240] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5 (.I0(Q[9]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[247]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_6 (.I0(Q[17]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[246] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1 (.I0(Q[19]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[53] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2 (.I0(Q[27]), .I1(mem_out[33]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[52] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3 (.I0(Q[35]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[51] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4 (.I0(Q[43]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[50] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5 (.I0(Q[51]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[49] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6 (.I0(Q[59]), .I1(mem_out[65]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[48] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5 (.I0(Q[3]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[55] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6 (.I0(Q[11]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[54] )); (* SOFT_HLUTNM = "soft_lutpair782" *) LUT5 #( .INIT(32'hFFFFF888)) phy_if_empty_r_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .O(phy_if_empty_r_reg)); (* SOFT_HLUTNM = "soft_lutpair782" *) LUT5 #( .INIT(32'h00000777)) phy_rddata_en_r1_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .O(phy_rddata_en)); (* SOFT_HLUTNM = "soft_lutpair784" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1__0 (.I0(my_empty_0[1]), .I1(\wr_ptr[1]_i_3__0_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair784" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1__0 (.I0(rd_ptr[0]), .I1(my_empty_0[1]), .I2(\wr_ptr[1]_i_3__0_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1__0_n_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1__0_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1__0_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__2 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3__0_n_0 ), .I2(my_empty_0[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__5 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3__0_n_0 ), .I4(my_empty_0[1]), .O(\rd_ptr_timing[1]_i_1__5_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__2_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__5_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); LUT2 #( .INIT(4'h6)) \read_fifo.tail_r[0]_i_1 (.I0(\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .I1(tail_r), .O(\read_fifo.tail_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair783" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__4 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3__0_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__4_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__4 (.I0(wr_ptr[0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(my_empty_0[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3__0_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__4_n_0 )); LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2__0 (.I0(my_empty_0[0]), .O(my_empty_0[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3__0 (.I0(\rd_ptr_timing_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(D_byte_rd_en), .I3(A_byte_rd_en), .I4(if_empty_r_0), .I5(my_empty[1]), .O(\wr_ptr[1]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair817" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_4__0 (.I0(my_empty_0[0]), .O(\rd_ptr_timing_reg[1]_0 )); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_6 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\rd_ptr_timing_reg[1]_0 ), .O(B_byte_rd_en)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__4_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__4_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_6 (\wr_ptr_reg[1]_0 , \not_strict_mode.app_rd_data_reg[252] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[24] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , \not_strict_mode.app_rd_data_reg[31]_0 , A_byte_rd_en, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , ififo_rst, CLK, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] , \byte_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \byte_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , A, Q, D_byte_rd_en, B_byte_rd_en, if_empty_r_0, my_empty, \po_stg2_wrcal_cnt_reg[1] ); output \wr_ptr_reg[1]_0 ; output \not_strict_mode.app_rd_data_reg[252] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[24] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output A_byte_rd_en; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; input ififo_rst; input CLK; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; input \byte_r_reg[0] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input \byte_r_reg[1] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]A; input [65:0]Q; input D_byte_rd_en; input B_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]my_empty; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]A; wire A_byte_rd_en; wire B_byte_rd_en; wire CLK; wire D_byte_rd_en; wire [65:0]Q; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire [63:0]\data_bytes_r_reg[63] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire [0:0]if_empty_r_0; wire ififo_rst; wire [63:1]mem_out; wire mem_reg_0_3_60_65_n_4; wire mem_reg_0_3_60_65_n_5; wire [0:0]my_empty; wire \my_empty[4]_i_1__2_n_0 ; wire \my_empty[4]_i_2_n_0 ; wire [3:1]my_empty_0; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1_n_0 ; wire \my_full[0]_i_2_n_0 ; wire \my_full[1]_i_1_n_0 ; wire \my_full[1]_i_2_n_0 ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ; wire p_0_out; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1_n_0 ; wire \rd_ptr[1]_i_1_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__0_n_0 ; wire \rd_ptr_timing[1]_i_1__4_n_0 ; wire \read_fifo.fifo_out_data_r_reg[6] ; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__2_n_0 ; wire \wr_ptr[1]_i_1__2_n_0 ; wire \wr_ptr[1]_i_3_n_0 ; wire \wr_ptr_reg[1]_0 ; wire [1:0]NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\data_bytes_r_reg[63] [0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[10]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\data_bytes_r_reg[63] [10])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[11]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\data_bytes_r_reg[63] [11])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[12]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\data_bytes_r_reg[63] [12])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[13]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\data_bytes_r_reg[63] [13])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[14]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\data_bytes_r_reg[63] [14])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[15]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\data_bytes_r_reg[63] [15])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[16]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(\data_bytes_r_reg[63] [16])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[17]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\data_bytes_r_reg[63] [17])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[18]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\data_bytes_r_reg[63] [18])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[19]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\data_bytes_r_reg[63] [19])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\data_bytes_r_reg[63] [1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[20]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\data_bytes_r_reg[63] [20])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[21]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\data_bytes_r_reg[63] [21])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[22]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\data_bytes_r_reg[63] [22])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[23]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\data_bytes_r_reg[63] [23])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[24]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\data_bytes_r_reg[63] [24])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[25]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\data_bytes_r_reg[63] [25])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[26]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\data_bytes_r_reg[63] [26])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[27]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\data_bytes_r_reg[63] [27])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[28]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\data_bytes_r_reg[63] [28])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[29]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\data_bytes_r_reg[63] [29])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\data_bytes_r_reg[63] [2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[30]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\data_bytes_r_reg[63] [30])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[31]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\data_bytes_r_reg[63] [31])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[32]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\data_bytes_r_reg[63] [32])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[33]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\data_bytes_r_reg[63] [33])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[34]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\data_bytes_r_reg[63] [34])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[35]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\data_bytes_r_reg[63] [35])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[36]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\data_bytes_r_reg[63] [36])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[37]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\data_bytes_r_reg[63] [37])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[38]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\data_bytes_r_reg[63] [38])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[39]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\data_bytes_r_reg[63] [39])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\data_bytes_r_reg[63] [3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[40]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\data_bytes_r_reg[63] [40])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[41]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\data_bytes_r_reg[63] [41])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[42]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\data_bytes_r_reg[63] [42])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[43]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\data_bytes_r_reg[63] [43])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[44]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\data_bytes_r_reg[63] [44])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[45]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\data_bytes_r_reg[63] [45])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[46]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\data_bytes_r_reg[63] [46])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[47]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\data_bytes_r_reg[63] [47])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[48]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\data_bytes_r_reg[63] [48])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[49]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\data_bytes_r_reg[63] [49])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\data_bytes_r_reg[63] [4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[50]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\data_bytes_r_reg[63] [50])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[51]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\data_bytes_r_reg[63] [51])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[52]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\data_bytes_r_reg[63] [52])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[53]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\data_bytes_r_reg[63] [53])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[54]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\data_bytes_r_reg[63] [54])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[55]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\data_bytes_r_reg[63] [55])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[56]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\data_bytes_r_reg[63] [56])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[57]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\data_bytes_r_reg[63] [57])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[58]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\data_bytes_r_reg[63] [58])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[59]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\data_bytes_r_reg[63] [59])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\data_bytes_r_reg[63] [5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[60]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\data_bytes_r_reg[63] [60])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[61]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\data_bytes_r_reg[63] [61])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[62]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\data_bytes_r_reg[63] [62])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[63]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\data_bytes_r_reg[63] [63])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\data_bytes_r_reg[63] [6])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\data_bytes_r_reg[63] [7])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[8]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\data_bytes_r_reg[63] [8])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[9]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\data_bytes_r_reg[63] [9])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\gen_mux_rd[0].mux_rd_fall0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\gen_mux_rd[0].mux_rd_fall1_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\gen_mux_rd[0].mux_rd_fall2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\gen_mux_rd[0].mux_rd_fall3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(\gen_mux_rd[0].mux_rd_rise1_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise2_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\gen_mux_rd[0].mux_rd_rise2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\gen_mux_rd[0].mux_rd_rise3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\gen_mux_rd[2].mux_rd_fall0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\gen_mux_rd[2].mux_rd_fall1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\gen_mux_rd[2].mux_rd_fall2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\gen_mux_rd[2].mux_rd_rise1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\gen_mux_rd[2].mux_rd_rise2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\gen_mux_rd[2].mux_rd_rise3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise3_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\gen_mux_rd[4].mux_rd_fall0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\gen_mux_rd[4].mux_rd_fall1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\gen_mux_rd[4].mux_rd_fall2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\gen_mux_rd[4].mux_rd_fall3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\gen_mux_rd[4].mux_rd_rise1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise2_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\gen_mux_rd[4].mux_rd_rise2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\gen_mux_rd[4].mux_rd_rise3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\gen_mux_rd[5].mux_rd_rise0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\gen_mux_rd[6].mux_rd_fall0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\gen_mux_rd[6].mux_rd_fall1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\gen_mux_rd[6].mux_rd_fall2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\gen_mux_rd[6].mux_rd_fall3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\gen_mux_rd[6].mux_rd_rise0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\gen_mux_rd[6].mux_rd_rise1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\gen_mux_rd[6].mux_rd_rise2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\gen_mux_rd[6].mux_rd_rise3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\gen_mux_rd[7].mux_rd_rise0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise3_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(p_0_out)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_0_5 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_out[1],\not_strict_mode.app_rd_data_reg[31]_0 }), .DOB(mem_out[3:2]), .DOC(mem_out[5:4]), .DOD(NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_0_5_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3_n_0 ), .I3(my_empty_0[2]), .O(wr_en)); LUT1 #( .INIT(2'h2)) mem_reg_0_3_0_5_i_2 (.I0(\wr_ptr_reg[1]_0 ), .O(my_empty_0[2])); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[7:6]), .DOB(mem_out[9:8]), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1__2 (.I0(my_full[1]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\wr_ptr[1]_i_3_n_0 ), .I3(my_empty_0[1]), .O(\my_empty[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty_0[1]), .O(\my_empty[4]_i_2_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1__2_n_0 ), .D(\my_empty[4]_i_2_n_0 ), .Q(\wr_ptr_reg[1]_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1__2_n_0 ), .D(\my_empty[4]_i_2_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE #( .INIT(1'b1)) \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1__2_n_0 ), .D(\my_empty[4]_i_2_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1 (.I0(my_full[0]), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\wr_ptr[1]_i_3_n_0 ), .I5(\my_full[0]_i_2_n_0 ), .O(\my_full[0]_i_1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1 (.I0(\my_full[1]_i_2_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair731" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2 (.I0(my_empty_0[1]), .I1(my_full[1]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\wr_ptr[1]_i_3_n_0 ), .O(\my_full[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE #( .INIT(1'b0)) \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair757" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[120]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [24])); (* SOFT_HLUTNM = "soft_lutpair758" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[121]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [25])); (* SOFT_HLUTNM = "soft_lutpair759" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[122]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [26])); (* SOFT_HLUTNM = "soft_lutpair760" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[123]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [27])); (* SOFT_HLUTNM = "soft_lutpair761" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[124]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [28])); (* SOFT_HLUTNM = "soft_lutpair762" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[125]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [29])); (* SOFT_HLUTNM = "soft_lutpair763" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[126]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [30])); (* SOFT_HLUTNM = "soft_lutpair764" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[127]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [31])); (* SOFT_HLUTNM = "soft_lutpair764" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[152]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [32])); (* SOFT_HLUTNM = "soft_lutpair763" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[153]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [33])); (* SOFT_HLUTNM = "soft_lutpair762" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[154]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [34])); (* SOFT_HLUTNM = "soft_lutpair761" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[155]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [35])); (* SOFT_HLUTNM = "soft_lutpair760" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[156]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [36])); (* SOFT_HLUTNM = "soft_lutpair759" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[157]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [37])); (* SOFT_HLUTNM = "soft_lutpair758" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[158]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [38])); (* SOFT_HLUTNM = "soft_lutpair757" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[159]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [39])); (* SOFT_HLUTNM = "soft_lutpair756" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[184]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [40])); (* SOFT_HLUTNM = "soft_lutpair755" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[185]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [41])); (* SOFT_HLUTNM = "soft_lutpair754" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[186]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [42])); (* SOFT_HLUTNM = "soft_lutpair753" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[187]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [43])); (* SOFT_HLUTNM = "soft_lutpair752" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[188]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [44])); (* SOFT_HLUTNM = "soft_lutpair751" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[189]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [45])); (* SOFT_HLUTNM = "soft_lutpair750" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[190]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [46])); (* SOFT_HLUTNM = "soft_lutpair749" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[191]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [47])); (* SOFT_HLUTNM = "soft_lutpair748" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[216]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [48])); (* SOFT_HLUTNM = "soft_lutpair747" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[217]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [49])); (* SOFT_HLUTNM = "soft_lutpair746" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[218]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [50])); (* SOFT_HLUTNM = "soft_lutpair745" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[219]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [51])); (* SOFT_HLUTNM = "soft_lutpair744" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[220]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [52])); (* SOFT_HLUTNM = "soft_lutpair743" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[221]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [53])); (* SOFT_HLUTNM = "soft_lutpair742" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[222]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [54])); (* SOFT_HLUTNM = "soft_lutpair741" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[223]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [55])); (* SOFT_HLUTNM = "soft_lutpair740" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[248]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [56])); (* SOFT_HLUTNM = "soft_lutpair739" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[249]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [57])); (* SOFT_HLUTNM = "soft_lutpair733" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[24]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair738" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[250]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [58])); (* SOFT_HLUTNM = "soft_lutpair737" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[251]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [59])); (* SOFT_HLUTNM = "soft_lutpair736" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[252]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [60])); (* SOFT_HLUTNM = "soft_lutpair735" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[253]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [61])); (* SOFT_HLUTNM = "soft_lutpair734" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[254]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [62])); (* SOFT_HLUTNM = "soft_lutpair733" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[255]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [63])); (* SOFT_HLUTNM = "soft_lutpair734" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[25]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair735" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[26]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair736" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[27]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair737" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[28]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair738" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[29]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair739" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[30]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair740" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[31]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair741" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[56]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [8])); (* SOFT_HLUTNM = "soft_lutpair742" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[57]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [9])); (* SOFT_HLUTNM = "soft_lutpair743" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[58]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [10])); (* SOFT_HLUTNM = "soft_lutpair744" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[59]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [11])); (* SOFT_HLUTNM = "soft_lutpair745" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[60]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [12])); (* SOFT_HLUTNM = "soft_lutpair746" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[61]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [13])); (* SOFT_HLUTNM = "soft_lutpair747" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[62]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [14])); (* SOFT_HLUTNM = "soft_lutpair748" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[63]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [15])); (* SOFT_HLUTNM = "soft_lutpair749" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[88]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [16])); (* SOFT_HLUTNM = "soft_lutpair750" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[89]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [17])); (* SOFT_HLUTNM = "soft_lutpair751" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[90]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [18])); (* SOFT_HLUTNM = "soft_lutpair752" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[91]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [19])); (* SOFT_HLUTNM = "soft_lutpair753" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[92]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [20])); (* SOFT_HLUTNM = "soft_lutpair754" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[93]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [21])); (* SOFT_HLUTNM = "soft_lutpair755" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[94]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [22])); (* SOFT_HLUTNM = "soft_lutpair756" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[95]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [23])); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3 (.I0(Q[1]), .I1(mem_out[1]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[63] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4 (.I0(Q[9]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[62] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5 (.I0(Q[17]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[61] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6 (.I0(Q[25]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[60] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1 (.I0(Q[50]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[89] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2 (.I0(Q[58]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[88] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1 (.I0(Q[2]), .I1(mem_out[2]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[95] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2 (.I0(Q[10]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[94] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3 (.I0(Q[18]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[93] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4 (.I0(Q[26]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[92] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5 (.I0(Q[34]), .I1(mem_out[34]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[91] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6 (.I0(Q[42]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[90] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1 (.I0(Q[19]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[125] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2 (.I0(Q[27]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[124] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3 (.I0(Q[35]), .I1(mem_out[35]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[123] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4 (.I0(Q[43]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[122] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5 (.I0(Q[51]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[121] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6 (.I0(Q[59]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[120] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5 (.I0(Q[3]), .I1(mem_out[3]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[127] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_6 (.I0(Q[11]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[126] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1 (.I0(Q[36]), .I1(mem_out[36]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[155] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2 (.I0(Q[44]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[154] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3 (.I0(Q[52]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[153] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4 (.I0(Q[60]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[152] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3 (.I0(Q[4]), .I1(mem_out[4]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[159] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4 (.I0(Q[12]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[158] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5 (.I0(Q[20]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[157] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_6 (.I0(Q[28]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[156] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1 (.I0(Q[53]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[185] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2 (.I0(Q[61]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[184] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1 (.I0(Q[5]), .I1(mem_out[5]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[191] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2 (.I0(Q[13]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[190] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3 (.I0(Q[21]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[189] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4 (.I0(Q[29]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[188] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5 (.I0(Q[37]), .I1(mem_out[37]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[187] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_6 (.I0(Q[45]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[186] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1 (.I0(Q[22]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[221] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2 (.I0(Q[30]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[220] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3 (.I0(Q[38]), .I1(mem_out[38]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[219] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4 (.I0(Q[46]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[218] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5 (.I0(Q[54]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[217] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_6 (.I0(Q[62]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[216] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5 (.I0(Q[6]), .I1(mem_out[6]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[223] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_6 (.I0(Q[14]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[222] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1 (.I0(Q[39]), .I1(mem_out[39]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[251] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2 (.I0(Q[47]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[250] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3 (.I0(Q[55]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[249] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4 (.I0(Q[63]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[248] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1 (.I0(Q[7]), .I1(mem_out[7]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[255] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2 (.I0(Q[15]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[254] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3 (.I0(Q[23]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[253] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4 (.I0(Q[31]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[252]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1 (.I0(Q[16]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[29] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2 (.I0(Q[24]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[28] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3 (.I0(Q[32]), .I1(mem_out[32]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[27] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4 (.I0(Q[40]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[26] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5 (.I0(Q[48]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[25] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6 (.I0(Q[56]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[24] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[252] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5 (.I0(Q[0]), .I1(\not_strict_mode.app_rd_data_reg[31]_0 ), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[31] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6 (.I0(Q[8]), .I1(mem_out[8]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[30] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1 (.I0(Q[33]), .I1(mem_out[33]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[59] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2 (.I0(Q[41]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[58] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3 (.I0(Q[49]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[57] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4 (.I0(Q[57]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[56] )); (* SOFT_HLUTNM = "soft_lutpair732" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1 (.I0(my_empty_0[1]), .I1(\wr_ptr[1]_i_3_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair732" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1 (.I0(rd_ptr[0]), .I1(my_empty_0[1]), .I2(\wr_ptr[1]_i_3_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1_n_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__0 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3_n_0 ), .I2(my_empty_0[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__0_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__4 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3_n_0 ), .I4(my_empty_0[1]), .O(\rd_ptr_timing[1]_i_1__4_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__0_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__4_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair731" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__2 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__2 (.I0(wr_ptr[0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(my_empty_0[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair765" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2 (.I0(\wr_ptr_reg[1]_0 ), .O(my_empty_0[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3 (.I0(my_empty_0[3]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(D_byte_rd_en), .I3(B_byte_rd_en), .I4(if_empty_r_0), .I5(my_empty), .O(\wr_ptr[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair765" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_4 (.I0(\wr_ptr_reg[1]_0 ), .O(my_empty_0[3])); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_5 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[3]), .O(A_byte_rd_en)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__2_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__2_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_mc_phy" *) module ddr3_ifmig_7series_v4_0_ddr_mc_phy (\rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, idelay_ld_rst, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , idelay_ld_rst_0, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , idelay_ld_rst_1, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , idelay_ld_rst_2, \calib_seq_reg[0] , \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[228] , \my_empty_reg[1] , \my_empty_reg[1]_0 , phy_mc_ctl_full, \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \my_empty_reg[1]_3 , \my_empty_reg[1]_4 , \my_empty_reg[1]_5 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , \my_empty_reg[1]_6 , phy_rddata_en, mux_rd_valid_r_reg, rst_sync_r1_reg, \byte_r_reg[0] , \po_counter_read_val_r_reg[5] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \read_fifo.tail_r_reg[0] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , of_ctl_full_v, pi_phase_locked_all_r1_reg, \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , wr_en, wr_en_5, wr_en_6, \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7] , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7]_1 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7]_2 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \po_rdval_cnt_reg[8] , \pi_rdval_cnt_reg[5] , \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , \po_rdval_cnt_reg[8]_0 , phy_if_empty_r_reg, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , ddr_ck_out, \my_empty_reg[7]_3 , CLK, init_calib_complete_reg_rep__6, D5, D6, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, D0, D1, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, \calib_sel_reg[0]_2 , sync_pulse, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , \calib_sel_reg[1]_2 , \calib_sel_reg[1]_3 , \gen_byte_sel_div1.calib_in_common_reg_1 , \calib_sel_reg[1]_4 , \calib_sel_reg[1]_5 , \calib_sel_reg[1]_6 , phy_ctl_wr_i2, pll_locked, phy_read_calib, in0, phy_write_calib, Q, \data_offset_1_i2_reg[5] , \gen_byte_sel_div1.calib_in_common_reg_2 , \calib_sel_reg[0]_3 , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, mem_dqs_in, \gen_byte_sel_div1.calib_in_common_reg_3 , COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_4 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_5 , mem_dq_in, idelay_inc, LD0, CLKB0, phy_if_reset, \gen_byte_sel_div1.calib_in_common_reg_6 , \calib_sel_reg[0]_4 , pi_en_stg2_f_reg_0, pi_stg2_f_incdec_reg_0, \gen_byte_sel_div1.calib_in_common_reg_7 , \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_8 , ck_po_stg2_f_en_reg_0, ck_po_stg2_f_indec_reg_0, delay_done_r4_reg_0, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_9 , LD0_3, CLKB0_7, \gen_byte_sel_div1.calib_in_common_reg_10 , \calib_sel_reg[1]_7 , pi_en_stg2_f_reg_1, pi_stg2_f_incdec_reg_1, \gen_byte_sel_div1.calib_in_common_reg_11 , \calib_zero_inputs_reg[0]_0 , \gen_byte_sel_div1.calib_in_common_reg_12 , ck_po_stg2_f_en_reg_1, ck_po_stg2_f_indec_reg_1, delay_done_r4_reg_1, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_13 , LD0_4, CLKB0_8, \gen_byte_sel_div1.calib_in_common_reg_14 , \calib_sel_reg[0]_5 , pi_en_stg2_f_reg_2, pi_stg2_f_incdec_reg_2, \gen_byte_sel_div1.calib_in_common_reg_15 , \calib_zero_inputs_reg[0]_1 , \gen_byte_sel_div1.calib_in_common_reg_16 , ck_po_stg2_f_en_reg_2, ck_po_stg2_f_indec_reg_2, delay_done_r4_reg_2, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_17 , LD0_5, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, mux_cmd_wren, mem_out, \rd_ptr_reg[3] , mux_wrdata_en, \rd_ptr_reg[3]_0 , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, init_calib_complete_reg_rep__5, mc_cas_n, mc_address, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , prbs_rdlvl_start_reg, out, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, \byte_r_reg[0]_0 , \byte_r_reg[1] , tail_r, \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , A, mux_wrdata, mux_wrdata_mask, E, \fine_delay_mod_reg[23] , \gen_byte_sel_div1.calib_in_common_reg_18 , \calib_sel_reg[0]_6 , \gen_byte_sel_div1.calib_in_common_reg_19 , \calib_sel_reg[1]_8 , \gen_byte_sel_div1.calib_in_common_reg_20 , \calib_sel_reg[0]_7 , \calib_sel_reg[3] , \po_stg2_wrcal_cnt_reg[1] , D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , phy_dout, init_calib_complete_reg_rep__6_0); output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output [3:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output [3:0]mem_dqs_out; output [3:0]mem_dqs_ts; output [59:0]mem_dq_out; output [35:0]mem_dq_ts; output idelay_ld_rst; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output idelay_ld_rst_0; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output idelay_ld_rst_1; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output idelay_ld_rst_2; output \calib_seq_reg[0] ; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[228] ; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output phy_mc_ctl_full; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \my_empty_reg[1]_3 ; output \my_empty_reg[1]_4 ; output \my_empty_reg[1]_5 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output \my_empty_reg[1]_6 ; output phy_rddata_en; output mux_rd_valid_r_reg; output rst_sync_r1_reg; output \byte_r_reg[0] ; output [5:0]\po_counter_read_val_r_reg[5] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \read_fifo.tail_r_reg[0] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output [0:0]of_ctl_full_v; output pi_phase_locked_all_r1_reg; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output wr_en; output wr_en_5; output wr_en_6; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7] ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7]_2 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [4:0]\po_rdval_cnt_reg[8] ; output [5:0]\pi_rdval_cnt_reg[5] ; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output [4:0]\po_rdval_cnt_reg[8]_0 ; output phy_if_empty_r_reg; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output [1:0]ddr_ck_out; output [31:0]\my_empty_reg[7]_3 ; input CLK; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [2:0]D0; input [2:0]D1; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[0]_2 ; input sync_pulse; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input \calib_sel_reg[1]_2 ; input \calib_sel_reg[1]_3 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \calib_sel_reg[1]_4 ; input \calib_sel_reg[1]_5 ; input \calib_sel_reg[1]_6 ; input phy_ctl_wr_i2; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input [10:0]Q; input [5:0]\data_offset_1_i2_reg[5] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \calib_sel_reg[0]_3 ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input [3:0]mem_dqs_in; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_4 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_5 ; input [31:0]mem_dq_in; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input \gen_byte_sel_div1.calib_in_common_reg_6 ; input \calib_sel_reg[0]_4 ; input pi_en_stg2_f_reg_0; input pi_stg2_f_incdec_reg_0; input \gen_byte_sel_div1.calib_in_common_reg_7 ; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_8 ; input ck_po_stg2_f_en_reg_0; input ck_po_stg2_f_indec_reg_0; input delay_done_r4_reg_0; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_9 ; input LD0_3; input CLKB0_7; input \gen_byte_sel_div1.calib_in_common_reg_10 ; input \calib_sel_reg[1]_7 ; input pi_en_stg2_f_reg_1; input pi_stg2_f_incdec_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_11 ; input [5:0]\calib_zero_inputs_reg[0]_0 ; input \gen_byte_sel_div1.calib_in_common_reg_12 ; input ck_po_stg2_f_en_reg_1; input ck_po_stg2_f_indec_reg_1; input delay_done_r4_reg_1; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_13 ; input LD0_4; input CLKB0_8; input \gen_byte_sel_div1.calib_in_common_reg_14 ; input \calib_sel_reg[0]_5 ; input pi_en_stg2_f_reg_2; input pi_stg2_f_incdec_reg_2; input \gen_byte_sel_div1.calib_in_common_reg_15 ; input [5:0]\calib_zero_inputs_reg[0]_1 ; input \gen_byte_sel_div1.calib_in_common_reg_16 ; input ck_po_stg2_f_en_reg_2; input ck_po_stg2_f_indec_reg_2; input delay_done_r4_reg_2; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_17 ; input LD0_5; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input mux_cmd_wren; input [11:0]mem_out; input [33:0]\rd_ptr_reg[3] ; input mux_wrdata_en; input [17:0]\rd_ptr_reg[3]_0 ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]mc_address; input init_calib_complete_reg_rep; input [31:0]\write_buffer.wr_buf_out_data_reg[287] ; input prbs_rdlvl_start_reg; input out; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input \byte_r_reg[0]_0 ; input \byte_r_reg[1] ; input [0:0]tail_r; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input [1:0]A; input [255:0]mux_wrdata; input [31:0]mux_wrdata_mask; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; input [7:0]\calib_sel_reg[0]_6 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; input [7:0]\calib_sel_reg[1]_8 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; input [7:0]\calib_sel_reg[0]_7 ; input [2:0]\calib_sel_reg[3] ; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input D_po_sel_fine_oclk_delay125_out; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input [35:0]phy_dout; input init_calib_complete_reg_rep__6_0; wire [1:0]A; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [5:0]COUNTERLOADVAL; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]E; wire LD0; wire LD0_3; wire LD0_4; wire LD0_5; wire [10:0]Q; wire RST0; wire [0:0]_phy_ctl_full_p__0; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[1] ; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire \calib_sel_reg[0]_3 ; wire \calib_sel_reg[0]_4 ; wire \calib_sel_reg[0]_5 ; wire [7:0]\calib_sel_reg[0]_6 ; wire [7:0]\calib_sel_reg[0]_7 ; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire \calib_sel_reg[1]_3 ; wire \calib_sel_reg[1]_4 ; wire \calib_sel_reg[1]_5 ; wire \calib_sel_reg[1]_6 ; wire \calib_sel_reg[1]_7 ; wire [7:0]\calib_sel_reg[1]_8 ; wire [2:0]\calib_sel_reg[3] ; wire \calib_seq_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0]_1 ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_en_reg_0; wire ck_po_stg2_f_en_reg_1; wire ck_po_stg2_f_en_reg_2; wire ck_po_stg2_f_indec_reg; wire ck_po_stg2_f_indec_reg_0; wire ck_po_stg2_f_indec_reg_1; wire ck_po_stg2_f_indec_reg_2; wire [63:0]\data_bytes_r_reg[63] ; wire [5:0]\data_offset_1_i2_reg[5] ; wire [1:0]ddr_ck_out; wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ; wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ; wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ; wire delay_done_r4_reg; wire delay_done_r4_reg_0; wire delay_done_r4_reg_1; wire delay_done_r4_reg_2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire [7:0]\fine_delay_mod_reg[23] ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_10 ; wire \gen_byte_sel_div1.calib_in_common_reg_11 ; wire \gen_byte_sel_div1.calib_in_common_reg_12 ; wire \gen_byte_sel_div1.calib_in_common_reg_13 ; wire \gen_byte_sel_div1.calib_in_common_reg_14 ; wire \gen_byte_sel_div1.calib_in_common_reg_15 ; wire \gen_byte_sel_div1.calib_in_common_reg_16 ; wire \gen_byte_sel_div1.calib_in_common_reg_17 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.calib_in_common_reg_4 ; wire \gen_byte_sel_div1.calib_in_common_reg_5 ; wire \gen_byte_sel_div1.calib_in_common_reg_6 ; wire \gen_byte_sel_div1.calib_in_common_reg_7 ; wire \gen_byte_sel_div1.calib_in_common_reg_8 ; wire \gen_byte_sel_div1.calib_in_common_reg_9 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_0; wire idelay_ld_rst_1; wire idelay_ld_rst_2; wire in0; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire [3:0]init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire \mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ; wire \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ; wire mcGo_r_reg_gate_n_0; wire mcGo_r_reg_r_0_n_0; wire mcGo_r_reg_r_10_n_0; wire mcGo_r_reg_r_11_n_0; wire mcGo_r_reg_r_12_n_0; wire mcGo_r_reg_r_13_n_0; wire mcGo_r_reg_r_1_n_0; wire mcGo_r_reg_r_2_n_0; wire mcGo_r_reg_r_3_n_0; wire mcGo_r_reg_r_4_n_0; wire mcGo_r_reg_r_5_n_0; wire mcGo_r_reg_r_6_n_0; wire mcGo_r_reg_r_7_n_0; wire mcGo_r_reg_r_8_n_0; wire mcGo_r_reg_r_9_n_0; wire mcGo_r_reg_r_n_0; wire [1:1]mcGo_w__0; wire [1:0]mc_address; wire [0:0]mc_cas_n; wire [31:0]mem_dq_in; wire [59:0]mem_dq_out; wire [35:0]mem_dq_ts; wire [3:0]mem_dqs_in; wire [3:0]mem_dqs_out; wire [3:0]mem_dqs_ts; wire [11:0]mem_out; wire mem_refclk; wire mmcm_locked; wire mux_cmd_wren; wire mux_rd_valid_r_reg; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire [63:0]\my_empty_reg[7] ; wire [63:0]\my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire [63:0]\my_empty_reg[7]_2 ; wire [31:0]\my_empty_reg[7]_3 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire out; wire p_0_out; wire phy_ctl_mstr_empty; wire phy_ctl_wr_i2; wire [35:0]phy_dout; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_mc_ctl_full; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [3:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_en_stg2_f_reg_0; wire pi_en_stg2_f_reg_1; wire pi_en_stg2_f_reg_2; wire pi_phase_locked_all_r1_reg; wire [5:0]\pi_rdval_cnt_reg[5] ; wire pi_stg2_f_incdec_reg; wire pi_stg2_f_incdec_reg_0; wire pi_stg2_f_incdec_reg_1; wire pi_stg2_f_incdec_reg_2; wire pll_locked; wire [5:0]\po_counter_read_val_r_reg[5] ; wire [5:1]\po_counter_read_val_w[0]_0 ; wire [4:0]\po_rdval_cnt_reg[8] ; wire [4:0]\po_rdval_cnt_reg[8]_0 ; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rclk_delay_11; wire \rclk_delay_reg[10]_srl11_i_1_n_0 ; wire rd_buf_we; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [33:0]\rd_ptr_reg[3] ; wire [17:0]\rd_ptr_reg[3]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [1:1]ref_dll_lock_w; wire rst_out_i_1_n_0; wire rst_primitives; wire rst_primitives_i_1_n_0; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; wire [31:0]\write_buffer.wr_buf_out_data_reg[287] ; ddr3_ifmig_7series_v4_0_ddr_phy_4lanes \ddr_phy_4lanes_0.u_ddr_phy_4lanes (.A(A), .CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .COUNTERLOADVAL(COUNTERLOADVAL), .DOA(DOA), .DOB(DOB), .DOC(DOC), .E(E), .LD0(LD0), .LD0_3(LD0_3), .LD0_4(LD0_4), .LD0_5(LD0_5), .Q(Q), .RST0(RST0), ._phy_ctl_full_p__0(_phy_ctl_full_p__0), .\byte_r_reg[0] (\byte_r_reg[0]_0 ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\calib_sel_reg[0] (\calib_sel_reg[0]_3 ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_4 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_5 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_6 ), .\calib_sel_reg[0]_3 (\calib_sel_reg[0]_7 ), .\calib_sel_reg[1] (\calib_sel_reg[1]_7 ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_8 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[3] [1:0]), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ), .\calib_zero_inputs_reg[0]_0 (\calib_zero_inputs_reg[0]_0 ), .\calib_zero_inputs_reg[0]_1 (\calib_zero_inputs_reg[0]_1 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg), .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0), .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1), .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg), .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0), .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1), .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .delay_done_r4_reg(delay_done_r4_reg), .delay_done_r4_reg_0(delay_done_r4_reg_0), .delay_done_r4_reg_1(delay_done_r4_reg_1), .delay_done_r4_reg_2(delay_done_r4_reg_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23] ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_4 ), .\gen_byte_sel_div1.calib_in_common_reg_10 (\gen_byte_sel_div1.calib_in_common_reg_13 ), .\gen_byte_sel_div1.calib_in_common_reg_11 (\gen_byte_sel_div1.calib_in_common_reg_14 ), .\gen_byte_sel_div1.calib_in_common_reg_12 (\gen_byte_sel_div1.calib_in_common_reg_15 ), .\gen_byte_sel_div1.calib_in_common_reg_13 (\gen_byte_sel_div1.calib_in_common_reg_16 ), .\gen_byte_sel_div1.calib_in_common_reg_14 (\gen_byte_sel_div1.calib_in_common_reg_17 ), .\gen_byte_sel_div1.calib_in_common_reg_15 (\gen_byte_sel_div1.calib_in_common_reg_18 ), .\gen_byte_sel_div1.calib_in_common_reg_16 (\gen_byte_sel_div1.calib_in_common_reg_19 ), .\gen_byte_sel_div1.calib_in_common_reg_17 (\gen_byte_sel_div1.calib_in_common_reg_20 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_5 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_6 ), .\gen_byte_sel_div1.calib_in_common_reg_4 (\gen_byte_sel_div1.calib_in_common_reg_7 ), .\gen_byte_sel_div1.calib_in_common_reg_5 (\gen_byte_sel_div1.calib_in_common_reg_8 ), .\gen_byte_sel_div1.calib_in_common_reg_6 (\gen_byte_sel_div1.calib_in_common_reg_9 ), .\gen_byte_sel_div1.calib_in_common_reg_7 (\gen_byte_sel_div1.calib_in_common_reg_10 ), .\gen_byte_sel_div1.calib_in_common_reg_8 (\gen_byte_sel_div1.calib_in_common_reg_11 ), .\gen_byte_sel_div1.calib_in_common_reg_9 (\gen_byte_sel_div1.calib_in_common_reg_12 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .idelay_ld_rst_0(idelay_ld_rst_0), .idelay_ld_rst_1(idelay_ld_rst_1), .idelay_ld_rst_2(idelay_ld_rst_2), .in0(in0), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ), .mcGo_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ), .mcGo_w__0(mcGo_w__0), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out[35:0]), .mem_dq_ts(mem_dq_ts), .mem_dqs_in(mem_dqs_in), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .mem_refclk(mem_refclk), .mmcm_locked(mmcm_locked), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .mux_wrdata(mux_wrdata), .mux_wrdata_en(mux_wrdata_en), .mux_wrdata_mask(mux_wrdata_mask), .\my_empty_reg[1] (\my_empty_reg[1]_2 ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_3 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_4 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_5 ), .\my_empty_reg[7] (\my_empty_reg[7] ), .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ), .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] 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(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .ofs_rdy_r_reg(ofs_rdy_r_reg), .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0), .out(out), .p_0_out(p_0_out), .phy_ctl_mstr_empty(phy_ctl_mstr_empty), .phy_ctl_wr_i2(phy_ctl_wr_i2), .phy_ctl_wr_i2_reg(rst_primitives_i_1_n_0), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_if_reset(phy_if_reset), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ), .pi_en_stg2_f_reg(pi_en_stg2_f_reg), .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0), .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1), .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2), .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg), .\pi_rdval_cnt_reg[5] (\pi_rdval_cnt_reg[5] ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg), .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0), .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1), .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2), .pll_locked(pll_locked), .\po_rdval_cnt_reg[8] ({\po_rdval_cnt_reg[8] [4:2],\po_counter_read_val_w[0]_0 [5:4],\po_rdval_cnt_reg[8] [1],\po_counter_read_val_w[0]_0 [2:1],\po_rdval_cnt_reg[8] [0]}), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rclk_delay_11(rclk_delay_11), .\rclk_delay_reg[11]_0 (rst_out_i_1_n_0), .rd_buf_we(rd_buf_we), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .ref_dll_lock_w(ref_dll_lock_w), .rst_primitives(rst_primitives), .rst_primitives_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ), .rst_primitives_reg_1(\rclk_delay_reg[10]_srl11_i_1_n_0 ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .\write_buffer.wr_buf_out_data_reg[224] (\write_buffer.wr_buf_out_data_reg[224] ), .\write_buffer.wr_buf_out_data_reg[225] (\write_buffer.wr_buf_out_data_reg[225] ), .\write_buffer.wr_buf_out_data_reg[226] (\write_buffer.wr_buf_out_data_reg[226] ), .\write_buffer.wr_buf_out_data_reg[227] (\write_buffer.wr_buf_out_data_reg[227] ), .\write_buffer.wr_buf_out_data_reg[228] (\write_buffer.wr_buf_out_data_reg[228] ), .\write_buffer.wr_buf_out_data_reg[229] (\write_buffer.wr_buf_out_data_reg[229] ), .\write_buffer.wr_buf_out_data_reg[230] (\write_buffer.wr_buf_out_data_reg[230] ), .\write_buffer.wr_buf_out_data_reg[231] (\write_buffer.wr_buf_out_data_reg[231] ), .\write_buffer.wr_buf_out_data_reg[232] (\write_buffer.wr_buf_out_data_reg[232] ), .\write_buffer.wr_buf_out_data_reg[233] (\write_buffer.wr_buf_out_data_reg[233] ), .\write_buffer.wr_buf_out_data_reg[234] (\write_buffer.wr_buf_out_data_reg[234] ), .\write_buffer.wr_buf_out_data_reg[235] (\write_buffer.wr_buf_out_data_reg[235] ), .\write_buffer.wr_buf_out_data_reg[236] (\write_buffer.wr_buf_out_data_reg[236] ), .\write_buffer.wr_buf_out_data_reg[237] (\write_buffer.wr_buf_out_data_reg[237] ), .\write_buffer.wr_buf_out_data_reg[238] (\write_buffer.wr_buf_out_data_reg[238] ), .\write_buffer.wr_buf_out_data_reg[239] (\write_buffer.wr_buf_out_data_reg[239] ), .\write_buffer.wr_buf_out_data_reg[240] (\write_buffer.wr_buf_out_data_reg[240] ), .\write_buffer.wr_buf_out_data_reg[241] (\write_buffer.wr_buf_out_data_reg[241] ), .\write_buffer.wr_buf_out_data_reg[242] (\write_buffer.wr_buf_out_data_reg[242] ), .\write_buffer.wr_buf_out_data_reg[243] (\write_buffer.wr_buf_out_data_reg[243] ), .\write_buffer.wr_buf_out_data_reg[244] (\write_buffer.wr_buf_out_data_reg[244] ), .\write_buffer.wr_buf_out_data_reg[245] (\write_buffer.wr_buf_out_data_reg[245] ), .\write_buffer.wr_buf_out_data_reg[246] (\write_buffer.wr_buf_out_data_reg[246] ), .\write_buffer.wr_buf_out_data_reg[247] (\write_buffer.wr_buf_out_data_reg[247] ), .\write_buffer.wr_buf_out_data_reg[248] (\write_buffer.wr_buf_out_data_reg[248] ), .\write_buffer.wr_buf_out_data_reg[249] (\write_buffer.wr_buf_out_data_reg[249] ), .\write_buffer.wr_buf_out_data_reg[250] (\write_buffer.wr_buf_out_data_reg[250] ), .\write_buffer.wr_buf_out_data_reg[251] (\write_buffer.wr_buf_out_data_reg[251] ), .\write_buffer.wr_buf_out_data_reg[252] (\write_buffer.wr_buf_out_data_reg[252] ), .\write_buffer.wr_buf_out_data_reg[253] (\write_buffer.wr_buf_out_data_reg[253] ), .\write_buffer.wr_buf_out_data_reg[254] (\write_buffer.wr_buf_out_data_reg[254] ), .\write_buffer.wr_buf_out_data_reg[255] (\write_buffer.wr_buf_out_data_reg[255] ), .\write_buffer.wr_buf_out_data_reg[287] (\write_buffer.wr_buf_out_data_reg[287] )); ddr3_ifmig_7series_v4_0_ddr_phy_4lanes__parameterized0 \ddr_phy_4lanes_1.u_ddr_phy_4lanes (.CLK(CLK), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8), .D9(D9), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .D_po_counter_read_en122_out(D_po_counter_read_en122_out), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .PHYCTLWD({Q[10:9],\data_offset_1_i2_reg[5] ,Q[2:0]}), .Q(\wr_ptr_timing_reg[2] ), .RST0(RST0), ._phy_ctl_full_p__0(_phy_ctl_full_p__0), .\byte_r_reg[0] (\byte_r_reg[0] ), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_1 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_2 ), .\calib_sel_reg[1]_3 (\calib_sel_reg[1]_3 ), .\calib_sel_reg[1]_4 (\calib_sel_reg[1]_4 ), .\calib_sel_reg[1]_5 (\calib_sel_reg[1]_5 ), .\calib_sel_reg[1]_6 (\calib_sel_reg[1]_6 ), .\calib_sel_reg[3] (\calib_sel_reg[3] ), .ddr_ck_out(ddr_ck_out), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .in0(in0), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0), .mcGo_w__0(mcGo_w__0), .mc_address(mc_address), .mc_cas_n(mc_cas_n), .mem_dq_out(mem_dq_out[59:36]), .mem_out(mem_out), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_6 ), .\my_empty_reg[7] (\my_empty_reg[7]_3 ), .of_ctl_full_v(of_ctl_full_v), .phy_ctl_mstr_empty(phy_ctl_mstr_empty), .phy_ctl_wr_i2(phy_ctl_wr_i2), .phy_dout(phy_dout), .phy_mc_ctl_full(phy_mc_ctl_full), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .pll_locked(pll_locked), .\po_counter_read_val_r_reg[5] (\po_counter_read_val_r_reg[5] ), .\po_counter_read_val_reg[5]_0 ({\po_counter_read_val_w[0]_0 [5:4],\po_rdval_cnt_reg[8] [1],\po_counter_read_val_w[0]_0 [2:1],\po_rdval_cnt_reg[8] [0]}), .\po_rdval_cnt_reg[8] (\po_rdval_cnt_reg[8]_0 ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .ref_dll_lock_w(ref_dll_lock_w), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_1 )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 " *) SRL16E #( .INIT(16'h0000)) \mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 (.A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ), .Q(\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 )); FDRE #( .INIT(1'b0)) \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 (.C(CLK), .CE(1'b1), .D(\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ), .Q(\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \mcGo_r_reg[15] (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_gate_n_0), .Q(\calib_seq_reg[0] ), .R(in0)); LUT2 #( .INIT(4'h8)) mcGo_r_reg_gate (.I0(\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ), .I1(mcGo_r_reg_r_13_n_0), .O(mcGo_r_reg_gate_n_0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r (.C(CLK), .CE(1'b1), .D(1'b1), .Q(mcGo_r_reg_r_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_0 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_n_0), .Q(mcGo_r_reg_r_0_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_1 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_0_n_0), .Q(mcGo_r_reg_r_1_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_10 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_9_n_0), .Q(mcGo_r_reg_r_10_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_11 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_10_n_0), .Q(mcGo_r_reg_r_11_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_12 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_11_n_0), .Q(mcGo_r_reg_r_12_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_13 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_12_n_0), .Q(mcGo_r_reg_r_13_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_2 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_1_n_0), .Q(mcGo_r_reg_r_2_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_3 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_2_n_0), .Q(mcGo_r_reg_r_3_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_4 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_3_n_0), .Q(mcGo_r_reg_r_4_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_5 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_4_n_0), .Q(mcGo_r_reg_r_5_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_6 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_5_n_0), .Q(mcGo_r_reg_r_6_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_7 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_6_n_0), .Q(mcGo_r_reg_r_7_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_8 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_7_n_0), .Q(mcGo_r_reg_r_8_n_0), .R(in0)); FDRE #( .INIT(1'b0)) mcGo_r_reg_r_9 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_8_n_0), .Q(mcGo_r_reg_r_9_n_0), .R(in0)); LUT1 #( .INIT(2'h1)) \rclk_delay_reg[10]_srl11_i_1 (.I0(rst_primitives), .O(\rclk_delay_reg[10]_srl11_i_1_n_0 )); LUT2 #( .INIT(4'hE)) rst_out_i_1 (.I0(rclk_delay_11), .I1(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ), .O(rst_out_i_1_n_0)); LUT1 #( .INIT(2'h1)) rst_primitives_i_1 (.I0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ), .O(rst_primitives_i_1_n_0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_mc_phy_wrapper" *) module ddr3_ifmig_7series_v4_0_ddr_mc_phy_wrapper (ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, fine_delay_sel_r, \fine_delay_mod_reg[26]_0 , \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \not_strict_mode.app_rd_data_reg[252] , idelay_ld_rst, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \not_strict_mode.app_rd_data_reg[244] , idelay_ld_rst_0, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \not_strict_mode.app_rd_data_reg[236] , idelay_ld_rst_1, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , \not_strict_mode.app_rd_data_reg[228] , idelay_ld_rst_2, \calib_seq_reg[0] , \my_empty_reg[1] , \my_empty_reg[1]_0 , phy_mc_ctl_full, \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \my_empty_reg[1]_3 , \my_empty_reg[1]_4 , \my_empty_reg[1]_5 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , \my_empty_reg[7] , \my_empty_reg[1]_6 , phy_rddata_en, mux_rd_valid_r_reg, rst_sync_r1_reg, \byte_r_reg[0] , \po_counter_read_val_r_reg[5] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \read_fifo.tail_r_reg[0] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , of_ctl_full_v, pd_out, pi_phase_locked_all_r1_reg, \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , wr_en, wr_en_5, wr_en_6, fine_delay_mod, \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7]_0 , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7]_1 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7]_2 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7]_3 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \po_rdval_cnt_reg[8] , \pi_rdval_cnt_reg[5] , \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , \po_rdval_cnt_reg[8]_0 , phy_if_empty_r_reg, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , ddr_ck_out, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, mux_reset_n, idle, mmcm_ps_clk, rst_sync_r1, CLK, mux_cmd_wren, \gen_byte_sel_div1.byte_sel_cnt_reg[2] , \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 , fine_delay_sel_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 , \gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 , init_calib_complete_reg_rep__6, D5, D6, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, D0, D1, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, \calib_sel_reg[0]_2 , sync_pulse, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , \calib_sel_reg[1]_2 , \calib_sel_reg[1]_3 , \gen_byte_sel_div1.calib_in_common_reg_1 , \calib_sel_reg[1]_4 , \calib_sel_reg[1]_5 , \calib_sel_reg[1]_6 , pll_locked, phy_read_calib, in0, phy_write_calib, \gen_byte_sel_div1.calib_in_common_reg_2 , \calib_sel_reg[0]_3 , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, \gen_byte_sel_div1.calib_in_common_reg_3 , COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_4 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_5 , idelay_inc, LD0, CLKB0, phy_if_reset, \gen_byte_sel_div1.calib_in_common_reg_6 , \calib_sel_reg[0]_4 , pi_en_stg2_f_reg_0, pi_stg2_f_incdec_reg_0, \gen_byte_sel_div1.calib_in_common_reg_7 , \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_8 , ck_po_stg2_f_en_reg_0, ck_po_stg2_f_indec_reg_0, delay_done_r4_reg_0, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_9 , LD0_3, CLKB0_7, \gen_byte_sel_div1.calib_in_common_reg_10 , \calib_sel_reg[1]_7 , pi_en_stg2_f_reg_1, pi_stg2_f_incdec_reg_1, \gen_byte_sel_div1.calib_in_common_reg_11 , \calib_zero_inputs_reg[0]_0 , \gen_byte_sel_div1.calib_in_common_reg_12 , ck_po_stg2_f_en_reg_1, ck_po_stg2_f_indec_reg_1, delay_done_r4_reg_1, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_13 , LD0_4, CLKB0_8, \gen_byte_sel_div1.calib_in_common_reg_14 , \calib_sel_reg[0]_5 , pi_en_stg2_f_reg_2, pi_stg2_f_incdec_reg_2, \gen_byte_sel_div1.calib_in_common_reg_15 , \calib_zero_inputs_reg[0]_1 , \gen_byte_sel_div1.calib_in_common_reg_16 , ck_po_stg2_f_en_reg_2, ck_po_stg2_f_indec_reg_2, delay_done_r4_reg_2, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_17 , LD0_5, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, \gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 , mem_out, \rd_ptr_reg[3] , mux_wrdata_en, \rd_ptr_reg[3]_0 , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, \genblk9[6].fine_delay_incdec_pb_reg[6] , \genblk9[5].fine_delay_incdec_pb_reg[5] , \genblk9[7].fine_delay_incdec_pb_reg[7] , \genblk9[4].fine_delay_incdec_pb_reg[4] , \genblk9[3].fine_delay_incdec_pb_reg[3] , \genblk9[4].fine_delay_incdec_pb_reg[4]_0 , init_calib_complete_reg_rep__5, mc_cas_n, mc_address, init_calib_complete_reg_rep, Q, prbs_rdlvl_start_reg, out, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, \byte_r_reg[0]_0 , \byte_r_reg[1] , tail_r, \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , \genblk9[0].fine_delay_incdec_pb_reg[0] , \genblk9[1].fine_delay_incdec_pb_reg[1] , \genblk9[2].fine_delay_incdec_pb_reg[2] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , A, SR, D, \cmd_pipe_plus.mc_data_offset_1_reg[5] , mux_wrdata, mux_wrdata_mask, E, \fine_delay_mod_reg[23]_0 , \gen_byte_sel_div1.calib_in_common_reg_18 , \calib_sel_reg[0]_6 , \gen_byte_sel_div1.calib_in_common_reg_19 , \calib_sel_reg[1]_8 , \gen_byte_sel_div1.calib_in_common_reg_20 , \calib_sel_reg[0]_7 , \calib_sel_reg[3] , \po_stg2_wrcal_cnt_reg[1] , D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , phy_dout, init_calib_complete_reg_rep__6_0); output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output fine_delay_sel_r; output \fine_delay_mod_reg[26]_0 ; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output [3:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output [0:0]\not_strict_mode.app_rd_data_reg[252] ; output idelay_ld_rst; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[244] ; output idelay_ld_rst_0; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[236] ; output idelay_ld_rst_1; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [0:0]\not_strict_mode.app_rd_data_reg[228] ; output idelay_ld_rst_2; output \calib_seq_reg[0] ; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output phy_mc_ctl_full; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \my_empty_reg[1]_3 ; output \my_empty_reg[1]_4 ; output \my_empty_reg[1]_5 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output [31:0]\my_empty_reg[7] ; output \my_empty_reg[1]_6 ; output phy_rddata_en; output mux_rd_valid_r_reg; output rst_sync_r1_reg; output \byte_r_reg[0] ; output [5:0]\po_counter_read_val_r_reg[5] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \read_fifo.tail_r_reg[0] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output [0:0]of_ctl_full_v; output pd_out; output pi_phase_locked_all_r1_reg; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output wr_en; output wr_en_5; output wr_en_6; output [8:0]fine_delay_mod; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7]_2 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7]_3 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [4:0]\po_rdval_cnt_reg[8] ; output [5:0]\pi_rdval_cnt_reg[5] ; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output [4:0]\po_rdval_cnt_reg[8]_0 ; output phy_if_empty_r_reg; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output [1:0]ddr_ck_out; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input mux_reset_n; input idle; input mmcm_ps_clk; input rst_sync_r1; input CLK; input mux_cmd_wren; input \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; input \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; input fine_delay_sel_reg; input \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [2:0]D0; input [2:0]D1; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[0]_2 ; input sync_pulse; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input \calib_sel_reg[1]_2 ; input \calib_sel_reg[1]_3 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \calib_sel_reg[1]_4 ; input \calib_sel_reg[1]_5 ; input \calib_sel_reg[1]_6 ; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \calib_sel_reg[0]_3 ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_4 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_5 ; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input \gen_byte_sel_div1.calib_in_common_reg_6 ; input \calib_sel_reg[0]_4 ; input pi_en_stg2_f_reg_0; input pi_stg2_f_incdec_reg_0; input \gen_byte_sel_div1.calib_in_common_reg_7 ; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_8 ; input ck_po_stg2_f_en_reg_0; input ck_po_stg2_f_indec_reg_0; input delay_done_r4_reg_0; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_9 ; input LD0_3; input CLKB0_7; input \gen_byte_sel_div1.calib_in_common_reg_10 ; input \calib_sel_reg[1]_7 ; input pi_en_stg2_f_reg_1; input pi_stg2_f_incdec_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_11 ; input [5:0]\calib_zero_inputs_reg[0]_0 ; input \gen_byte_sel_div1.calib_in_common_reg_12 ; input ck_po_stg2_f_en_reg_1; input ck_po_stg2_f_indec_reg_1; input delay_done_r4_reg_1; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_13 ; input LD0_4; input CLKB0_8; input \gen_byte_sel_div1.calib_in_common_reg_14 ; input \calib_sel_reg[0]_5 ; input pi_en_stg2_f_reg_2; input pi_stg2_f_incdec_reg_2; input \gen_byte_sel_div1.calib_in_common_reg_15 ; input [5:0]\calib_zero_inputs_reg[0]_1 ; input \gen_byte_sel_div1.calib_in_common_reg_16 ; input ck_po_stg2_f_en_reg_2; input ck_po_stg2_f_indec_reg_2; input delay_done_r4_reg_2; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_17 ; input LD0_5; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input \gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ; input [11:0]mem_out; input [33:0]\rd_ptr_reg[3] ; input mux_wrdata_en; input [17:0]\rd_ptr_reg[3]_0 ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input \genblk9[6].fine_delay_incdec_pb_reg[6] ; input \genblk9[5].fine_delay_incdec_pb_reg[5] ; input \genblk9[7].fine_delay_incdec_pb_reg[7] ; input \genblk9[4].fine_delay_incdec_pb_reg[4] ; input \genblk9[3].fine_delay_incdec_pb_reg[3] ; input \genblk9[4].fine_delay_incdec_pb_reg[4]_0 ; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]mc_address; input init_calib_complete_reg_rep; input [31:0]Q; input prbs_rdlvl_start_reg; input out; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input \byte_r_reg[0]_0 ; input \byte_r_reg[1] ; input [0:0]tail_r; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input \genblk9[0].fine_delay_incdec_pb_reg[0] ; input \genblk9[1].fine_delay_incdec_pb_reg[1] ; input \genblk9[2].fine_delay_incdec_pb_reg[2] ; input [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; input [1:0]A; input [0:0]SR; input [10:0]D; input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; input [255:0]mux_wrdata; input [31:0]mux_wrdata_mask; input [0:0]E; input [7:0]\fine_delay_mod_reg[23]_0 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; input [7:0]\calib_sel_reg[0]_6 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; input [7:0]\calib_sel_reg[1]_8 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; input [7:0]\calib_sel_reg[0]_7 ; input [2:0]\calib_sel_reg[3] ; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input D_po_sel_fine_oclk_delay125_out; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input [35:0]phy_dout; input init_calib_complete_reg_rep__6_0; wire [1:0]A; wire \A[0]__0_n_0 ; wire \A[0]__4_n_0 ; wire \A[1]__0_n_0 ; wire \A[1]__3_n_0 ; wire \A[1]__4_n_0 ; wire \A[2]__1_n_0 ; wire \A_n_0_[1] ; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [5:0]COUNTERLOADVAL; wire [10:0]D; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]E; wire LD0; wire LD0_3; wire LD0_4; wire LD0_5; wire [31:0]Q; wire RST0; wire [0:0]SR; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[1] ; wire [1:1]byte_sel_data_map; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire \calib_sel_reg[0]_3 ; wire \calib_sel_reg[0]_4 ; wire \calib_sel_reg[0]_5 ; wire [7:0]\calib_sel_reg[0]_6 ; wire [7:0]\calib_sel_reg[0]_7 ; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire \calib_sel_reg[1]_3 ; wire \calib_sel_reg[1]_4 ; wire \calib_sel_reg[1]_5 ; wire \calib_sel_reg[1]_6 ; wire \calib_sel_reg[1]_7 ; wire [7:0]\calib_sel_reg[1]_8 ; wire [2:0]\calib_sel_reg[3] ; wire \calib_seq_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0]_1 ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_en_reg_0; wire ck_po_stg2_f_en_reg_1; wire ck_po_stg2_f_en_reg_2; wire ck_po_stg2_f_indec_reg; wire ck_po_stg2_f_indec_reg_0; wire ck_po_stg2_f_indec_reg_1; wire ck_po_stg2_f_indec_reg_2; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire [63:0]\data_bytes_r_reg[63] ; wire [5:0]data_offset_1_i1; wire [5:0]data_offset_1_i2; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire delay_done_r4_reg; wire delay_done_r4_reg_0; wire delay_done_r4_reg_1; wire delay_done_r4_reg_2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire [8:0]fine_delay_mod; wire [11:2]fine_delay_mod0; wire \fine_delay_mod[11]_i_10_n_0 ; wire \fine_delay_mod[11]_i_11_n_0 ; wire \fine_delay_mod[11]_i_12_n_0 ; wire \fine_delay_mod[11]_i_1_n_0 ; wire \fine_delay_mod[11]_i_2_n_0 ; wire \fine_delay_mod[11]_i_3_n_0 ; wire \fine_delay_mod[11]_i_4_n_0 ; wire \fine_delay_mod[11]_i_5_n_0 ; wire \fine_delay_mod[11]_i_7_n_0 ; wire \fine_delay_mod[11]_i_9_n_0 ; wire \fine_delay_mod[14]_i_1_n_0 ; wire \fine_delay_mod[14]_i_2_n_0 ; wire \fine_delay_mod[14]_i_3_n_0 ; wire \fine_delay_mod[14]_i_4_n_0 ; wire \fine_delay_mod[14]_i_5_n_0 ; wire \fine_delay_mod[14]_i_6_n_0 ; wire \fine_delay_mod[14]_i_7_n_0 ; wire \fine_delay_mod[14]_i_8_n_0 ; wire \fine_delay_mod[17]_i_1_n_0 ; wire \fine_delay_mod[17]_i_2_n_0 ; wire \fine_delay_mod[17]_i_3_n_0 ; wire \fine_delay_mod[17]_i_4_n_0 ; wire \fine_delay_mod[17]_i_5_n_0 ; wire \fine_delay_mod[17]_i_6_n_0 ; wire \fine_delay_mod[17]_i_7_n_0 ; wire \fine_delay_mod[17]_i_8_n_0 ; wire \fine_delay_mod[17]_i_9_n_0 ; wire \fine_delay_mod[20]_i_1_n_0 ; wire \fine_delay_mod[20]_i_2_n_0 ; wire \fine_delay_mod[20]_i_3_n_0 ; wire \fine_delay_mod[20]_i_4_n_0 ; wire \fine_delay_mod[20]_i_5_n_0 ; wire \fine_delay_mod[20]_i_6_n_0 ; wire \fine_delay_mod[20]_i_7_n_0 ; wire \fine_delay_mod[20]_i_8_n_0 ; wire \fine_delay_mod[20]_i_9_n_0 ; wire \fine_delay_mod[23]_i_10_n_0 ; wire \fine_delay_mod[23]_i_1_n_0 ; wire \fine_delay_mod[23]_i_2_n_0 ; wire \fine_delay_mod[23]_i_3_n_0 ; wire \fine_delay_mod[23]_i_4_n_0 ; wire \fine_delay_mod[23]_i_5_n_0 ; wire \fine_delay_mod[23]_i_6_n_0 ; wire \fine_delay_mod[23]_i_7_n_0 ; wire \fine_delay_mod[23]_i_8_n_0 ; wire \fine_delay_mod[23]_i_9_n_0 ; wire \fine_delay_mod[26]_i_1_n_0 ; wire \fine_delay_mod[2]_i_10_n_0 ; wire \fine_delay_mod[2]_i_1_n_0 ; wire \fine_delay_mod[2]_i_2_n_0 ; wire \fine_delay_mod[2]_i_3_n_0 ; wire \fine_delay_mod[2]_i_4_n_0 ; wire \fine_delay_mod[2]_i_5_n_0 ; wire \fine_delay_mod[2]_i_7_n_0 ; wire \fine_delay_mod[2]_i_8_n_0 ; wire \fine_delay_mod[2]_i_9_n_0 ; wire \fine_delay_mod[5]_i_10_n_0 ; wire \fine_delay_mod[5]_i_11_n_0 ; wire \fine_delay_mod[5]_i_12_n_0 ; wire \fine_delay_mod[5]_i_1_n_0 ; wire \fine_delay_mod[5]_i_2_n_0 ; wire \fine_delay_mod[5]_i_3_n_0 ; wire \fine_delay_mod[5]_i_4_n_0 ; wire \fine_delay_mod[5]_i_5_n_0 ; wire \fine_delay_mod[5]_i_7_n_0 ; wire \fine_delay_mod[5]_i_8_n_0 ; wire \fine_delay_mod[5]_i_9_n_0 ; wire \fine_delay_mod[8]_i_10_n_0 ; wire \fine_delay_mod[8]_i_1_n_0 ; wire \fine_delay_mod[8]_i_2_n_0 ; wire \fine_delay_mod[8]_i_3_n_0 ; wire \fine_delay_mod[8]_i_4_n_0 ; wire \fine_delay_mod[8]_i_5_n_0 ; wire \fine_delay_mod[8]_i_7_n_0 ; wire \fine_delay_mod[8]_i_8_n_0 ; wire \fine_delay_mod[8]_i_9_n_0 ; wire [7:0]\fine_delay_mod_reg[23]_0 ; wire \fine_delay_mod_reg[26]_0 ; wire fine_delay_sel_r; wire fine_delay_sel_reg; wire freq_refclk; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ; wire [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_10 ; wire \gen_byte_sel_div1.calib_in_common_reg_11 ; wire \gen_byte_sel_div1.calib_in_common_reg_12 ; wire \gen_byte_sel_div1.calib_in_common_reg_13 ; wire \gen_byte_sel_div1.calib_in_common_reg_14 ; wire \gen_byte_sel_div1.calib_in_common_reg_15 ; wire \gen_byte_sel_div1.calib_in_common_reg_16 ; wire \gen_byte_sel_div1.calib_in_common_reg_17 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.calib_in_common_reg_4 ; wire \gen_byte_sel_div1.calib_in_common_reg_5 ; wire \gen_byte_sel_div1.calib_in_common_reg_6 ; wire \gen_byte_sel_div1.calib_in_common_reg_7 ; wire \gen_byte_sel_div1.calib_in_common_reg_8 ; wire \gen_byte_sel_div1.calib_in_common_reg_9 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire \genblk9[0].fine_delay_incdec_pb_reg[0] ; wire \genblk9[1].fine_delay_incdec_pb_reg[1] ; wire \genblk9[2].fine_delay_incdec_pb_reg[2] ; wire \genblk9[3].fine_delay_incdec_pb_reg[3] ; wire \genblk9[4].fine_delay_incdec_pb_reg[4] ; wire \genblk9[4].fine_delay_incdec_pb_reg[4]_0 ; wire \genblk9[5].fine_delay_incdec_pb_reg[5] ; wire \genblk9[6].fine_delay_incdec_pb_reg[6] ; wire \genblk9[7].fine_delay_incdec_pb_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_0; wire idelay_ld_rst_1; wire idelay_ld_rst_2; wire idle; wire in0; wire in_dqs_lpbk_to_iddr_0; wire in_dqs_lpbk_to_iddr_1; wire in_dqs_lpbk_to_iddr_2; wire in_dqs_lpbk_to_iddr_3; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire [3:0]init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire [1:0]mc_address; wire [0:0]mc_cas_n; wire [38:0]mem_dq_in; wire [93:0]mem_dq_out; wire [45:0]mem_dq_ts; wire [3:0]mem_dqs_in; wire [3:0]mem_dqs_out; wire [3:0]mem_dqs_ts; wire [11:0]mem_out; wire mem_refclk; wire mmcm_locked; wire mmcm_ps_clk; wire mux_cmd_wren; wire mux_rd_valid_r_reg; wire mux_reset_n; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire [31:0]\my_empty_reg[7] ; wire [63:0]\my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire [63:0]\my_empty_reg[7]_2 ; wire [63:0]\my_empty_reg[7]_3 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire [0:0]\not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire [0:0]\not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire [0:0]\not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire [0:0]\not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire out; wire p_0_out; wire pd_out; wire [2:0]pd_out_pre; wire [24:0]phy_ctl_wd_i1; wire [24:0]phy_ctl_wd_i2; wire phy_ctl_wr_i1; wire phy_ctl_wr_i2; wire [35:0]phy_dout; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_mc_ctl_full; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [3:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_en_stg2_f_reg_0; wire pi_en_stg2_f_reg_1; wire pi_en_stg2_f_reg_2; wire pi_phase_locked_all_r1_reg; wire [5:0]\pi_rdval_cnt_reg[5] ; wire pi_stg2_f_incdec_reg; wire pi_stg2_f_incdec_reg_0; wire pi_stg2_f_incdec_reg_1; wire pi_stg2_f_incdec_reg_2; wire pll_locked; wire [5:0]\po_counter_read_val_r_reg[5] ; wire [4:0]\po_rdval_cnt_reg[8] ; wire [4:0]\po_rdval_cnt_reg[8]_0 ; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rd_buf_we; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [33:0]\rd_ptr_reg[3] ; wire [17:0]\rd_ptr_reg[3]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; FDRE #( .INIT(1'b0)) \A[0]__0 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ), .Q(\A[0]__0_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \A[0]__4 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ), .Q(\A[0]__4_n_0 ), .R(1'b0)); FDSE #( .INIT(1'b1)) \A[1] (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ), .Q(\A_n_0_[1] ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDSE #( .INIT(1'b1)) \A[1]__0 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ), .Q(\A[1]__0_n_0 ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDSE #( .INIT(1'b1)) \A[1]__3 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ), .Q(\A[1]__3_n_0 ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDSE #( .INIT(1'b1)) \A[1]__4 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ), .Q(\A[1]__4_n_0 ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDRE #( .INIT(1'b0)) \A[2]__1 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ), .Q(\A[2]__1_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \A[2]__2 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0] ), .Q(\fine_delay_mod_reg[26]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \byte_sel_data_map_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ), .Q(byte_sel_data_map), .R(1'b0)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf (.I(mem_dq_out[71]), .O(ddr3_cke)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf (.I(mem_dq_out[70]), .O(ddr3_odt)); FDRE #( .INIT(1'b0)) \data_offset_1_i1_reg[0] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .Q(data_offset_1_i1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i1_reg[1] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .Q(data_offset_1_i1[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i1_reg[2] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .Q(data_offset_1_i1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i1_reg[3] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .Q(data_offset_1_i1[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i1_reg[4] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]), .Q(data_offset_1_i1[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i1_reg[5] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]), .Q(data_offset_1_i1[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i2_reg[0] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[0]), .Q(data_offset_1_i2[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i2_reg[1] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[1]), .Q(data_offset_1_i2[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i2_reg[2] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[2]), .Q(data_offset_1_i2[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i2_reg[3] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[3]), .Q(data_offset_1_i2[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i2_reg[4] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[4]), .Q(data_offset_1_i2[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_offset_1_i2_reg[5] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[5]), .Q(data_offset_1_i2[5]), .R(1'b0)); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[11]_i_1 (.I0(\fine_delay_mod[11]_i_2_n_0 ), .I1(\fine_delay_mod[11]_i_3_n_0 ), .I2(\fine_delay_mod[11]_i_4_n_0 ), .I3(\fine_delay_mod[11]_i_5_n_0 ), .I4(fine_delay_mod0[11]), .I5(fine_delay_mod[3]), .O(\fine_delay_mod[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1024" *) LUT5 #( .INIT(32'h00575757)) \fine_delay_mod[11]_i_10 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(byte_sel_data_map), .I3(\fine_delay_mod_reg[26]_0 ), .I4(\A[1]__3_n_0 ), .O(\fine_delay_mod[11]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1023" *) LUT5 #( .INIT(32'h0000F888)) \fine_delay_mod[11]_i_11 (.I0(\A[1]__0_n_0 ), .I1(\A[0]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A_n_0_[1] ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[11]_i_11_n_0 )); LUT6 #( .INIT(64'h0088008800F80088)) \fine_delay_mod[11]_i_12 (.I0(\A[0]__4_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\fine_delay_mod_reg[26]_0 ), .I4(byte_sel_data_map), .I5(\A[0]__0_n_0 ), .O(\fine_delay_mod[11]_i_12_n_0 )); LUT6 #( .INIT(64'hF780808080808080)) \fine_delay_mod[11]_i_2 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\A[1]__3_n_0 ), .I4(\genblk9[5].fine_delay_incdec_pb_reg[5] ), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[11]_i_2_n_0 )); LUT6 #( .INIT(64'h0000770400000000)) \fine_delay_mod[11]_i_3 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\fine_delay_mod[11]_i_7_n_0 ), .I4(\A[2]__1_n_0 ), .I5(\fine_delay_mod[23]_i_6_n_0 ), .O(\fine_delay_mod[11]_i_3_n_0 )); LUT6 #( .INIT(64'h0700000000000000)) \fine_delay_mod[11]_i_4 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[11]_i_4_n_0 )); LUT6 #( .INIT(64'h8000800088008000)) \fine_delay_mod[11]_i_5 (.I0(\fine_delay_mod[11]_i_9_n_0 ), .I1(\fine_delay_mod[11]_i_10_n_0 ), .I2(\A[2]__1_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\fine_delay_mod[23]_i_8_n_0 ), .I5(\A[1]__0_n_0 ), .O(\fine_delay_mod[11]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFF888)) \fine_delay_mod[11]_i_6 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__3_n_0 ), .I4(\fine_delay_mod[11]_i_11_n_0 ), .I5(\fine_delay_mod[11]_i_12_n_0 ), .O(fine_delay_mod0[11])); (* SOFT_HLUTNM = "soft_lutpair1035" *) LUT3 #( .INIT(8'h1F)) \fine_delay_mod[11]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[11]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1029" *) LUT4 #( .INIT(16'h0008)) \fine_delay_mod[11]_i_9 (.I0(byte_sel_data_map), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .O(\fine_delay_mod[11]_i_9_n_0 )); LUT5 #( .INIT(32'hEEEFEEE0)) \fine_delay_mod[14]_i_1 (.I0(\fine_delay_mod[14]_i_2_n_0 ), .I1(\fine_delay_mod[14]_i_3_n_0 ), .I2(\fine_delay_mod[14]_i_4_n_0 ), .I3(\fine_delay_mod[14]_i_5_n_0 ), .I4(fine_delay_mod[4]), .O(\fine_delay_mod[14]_i_1_n_0 )); LUT6 #( .INIT(64'hC480FFFFC4800000)) \fine_delay_mod[14]_i_2 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[14]_i_6_n_0 ), .I3(\genblk9[3].fine_delay_incdec_pb_reg[3] ), .I4(\fine_delay_mod[14]_i_7_n_0 ), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .O(\fine_delay_mod[14]_i_2_n_0 )); LUT6 #( .INIT(64'h00B0003000300030)) \fine_delay_mod[14]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[17]_i_8_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .I5(\fine_delay_mod[14]_i_8_n_0 ), .O(\fine_delay_mod[14]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1032" *) LUT4 #( .INIT(16'h444C)) \fine_delay_mod[14]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[14]_i_4_n_0 )); LUT6 #( .INIT(64'h000000FF02020202)) \fine_delay_mod[14]_i_5 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[14]_i_5_n_0 )); LUT6 #( .INIT(64'h020202FF02020200)) \fine_delay_mod[14]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[14]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1037" *) LUT3 #( .INIT(8'hFD)) \fine_delay_mod[14]_i_7 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[14]_i_7_n_0 )); LUT2 #( .INIT(4'hE)) \fine_delay_mod[14]_i_8 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .O(\fine_delay_mod[14]_i_8_n_0 )); LUT5 #( .INIT(32'hEEEFEEE0)) \fine_delay_mod[17]_i_1 (.I0(\fine_delay_mod[17]_i_2_n_0 ), .I1(\fine_delay_mod[17]_i_3_n_0 ), .I2(\fine_delay_mod[17]_i_4_n_0 ), .I3(\fine_delay_mod[17]_i_5_n_0 ), .I4(fine_delay_mod[5]), .O(\fine_delay_mod[17]_i_1_n_0 )); LUT6 #( .INIT(64'hC840FFFFC8400000)) \fine_delay_mod[17]_i_2 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[17]_i_6_n_0 ), .I3(\genblk9[3].fine_delay_incdec_pb_reg[3] ), .I4(\fine_delay_mod[17]_i_7_n_0 ), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .O(\fine_delay_mod[17]_i_2_n_0 )); LUT6 #( .INIT(64'h7030000030300000)) \fine_delay_mod[17]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[17]_i_8_n_0 ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\fine_delay_mod[17]_i_9_n_0 ), .O(\fine_delay_mod[17]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1032" *) LUT4 #( .INIT(16'h88C8)) \fine_delay_mod[17]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[17]_i_4_n_0 )); LUT6 #( .INIT(64'h0000FF0020202020)) \fine_delay_mod[17]_i_5 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[17]_i_5_n_0 )); LUT6 #( .INIT(64'h08FF080808000808)) \fine_delay_mod[17]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A_n_0_[1] ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[17]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1038" *) LUT3 #( .INIT(8'hDF)) \fine_delay_mod[17]_i_7 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[17]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1026" *) LUT4 #( .INIT(16'h0400)) \fine_delay_mod[17]_i_8 (.I0(byte_sel_data_map), .I1(\A[0]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .O(\fine_delay_mod[17]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1040" *) LUT2 #( .INIT(4'hB)) \fine_delay_mod[17]_i_9 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[17]_i_9_n_0 )); LUT6 #( .INIT(64'hFCFFFEFEFC00FEFE)) \fine_delay_mod[20]_i_1 (.I0(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .I1(\fine_delay_mod[20]_i_2_n_0 ), .I2(\fine_delay_mod[20]_i_3_n_0 ), .I3(\fine_delay_mod[20]_i_4_n_0 ), .I4(\fine_delay_mod[20]_i_5_n_0 ), .I5(fine_delay_mod[6]), .O(\fine_delay_mod[20]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1036" *) LUT3 #( .INIT(8'h80)) \fine_delay_mod[20]_i_2 (.I0(\fine_delay_mod[20]_i_6_n_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[20]_i_5_n_0 ), .O(\fine_delay_mod[20]_i_2_n_0 )); LUT5 #( .INIT(32'h004400C4)) \fine_delay_mod[20]_i_3 (.I0(\A[2]__1_n_0 ), .I1(\fine_delay_mod[23]_i_7_n_0 ), .I2(\fine_delay_mod[20]_i_7_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .O(\fine_delay_mod[20]_i_3_n_0 )); LUT5 #( .INIT(32'hFF808080)) \fine_delay_mod[20]_i_4 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\fine_delay_mod[20]_i_8_n_0 ), .I3(\A[2]__1_n_0 ), .I4(\fine_delay_mod[20]_i_9_n_0 ), .O(\fine_delay_mod[20]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1037" *) LUT3 #( .INIT(8'hF7)) \fine_delay_mod[20]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[20]_i_5_n_0 )); LUT6 #( .INIT(64'h08FF080808000808)) \fine_delay_mod[20]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[20]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1040" *) LUT2 #( .INIT(4'hB)) \fine_delay_mod[20]_i_7 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .O(\fine_delay_mod[20]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1039" *) LUT2 #( .INIT(4'h1)) \fine_delay_mod[20]_i_8 (.I0(\A[0]__0_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[20]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1030" *) LUT4 #( .INIT(16'h22F2)) \fine_delay_mod[20]_i_9 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__0_n_0 ), .I3(\A[0]__0_n_0 ), .O(\fine_delay_mod[20]_i_9_n_0 )); LUT6 #( .INIT(64'hFCFFFEFEFC00FEFE)) \fine_delay_mod[23]_i_1 (.I0(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .I1(\fine_delay_mod[23]_i_2_n_0 ), .I2(\fine_delay_mod[23]_i_3_n_0 ), .I3(\fine_delay_mod[23]_i_4_n_0 ), .I4(\fine_delay_mod[23]_i_5_n_0 ), .I5(fine_delay_mod[7]), .O(\fine_delay_mod[23]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1027" *) LUT4 #( .INIT(16'hF888)) \fine_delay_mod[23]_i_10 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[23]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1036" *) LUT3 #( .INIT(8'h80)) \fine_delay_mod[23]_i_2 (.I0(\fine_delay_mod[23]_i_6_n_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[23]_i_5_n_0 ), .O(\fine_delay_mod[23]_i_2_n_0 )); LUT5 #( .INIT(32'h4400C400)) \fine_delay_mod[23]_i_3 (.I0(\A[2]__1_n_0 ), .I1(\fine_delay_mod[23]_i_7_n_0 ), .I2(\fine_delay_mod[23]_i_8_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .O(\fine_delay_mod[23]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1025" *) LUT5 #( .INIT(32'hFF808080)) \fine_delay_mod[23]_i_4 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\fine_delay_mod[23]_i_9_n_0 ), .I3(\A[2]__1_n_0 ), .I4(\fine_delay_mod[23]_i_10_n_0 ), .O(\fine_delay_mod[23]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1038" *) LUT3 #( .INIT(8'h7F)) \fine_delay_mod[23]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[23]_i_5_n_0 )); LUT6 #( .INIT(64'hFF80808000808080)) \fine_delay_mod[23]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[23]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1029" *) LUT4 #( .INIT(16'h0800)) \fine_delay_mod[23]_i_7 (.I0(byte_sel_data_map), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .O(\fine_delay_mod[23]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1031" *) LUT2 #( .INIT(4'h7)) \fine_delay_mod[23]_i_8 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .O(\fine_delay_mod[23]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1039" *) LUT2 #( .INIT(4'h2)) \fine_delay_mod[23]_i_9 (.I0(\A[0]__0_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[23]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFEF00000020)) \fine_delay_mod[26]_i_1 (.I0(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I1(\A[0]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .I4(byte_sel_data_map), .I5(fine_delay_mod[8]), .O(\fine_delay_mod[26]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[2]_i_1 (.I0(\fine_delay_mod[2]_i_2_n_0 ), .I1(\fine_delay_mod[2]_i_3_n_0 ), .I2(\fine_delay_mod[2]_i_4_n_0 ), .I3(\fine_delay_mod[2]_i_5_n_0 ), .I4(fine_delay_mod0[2]), .I5(fine_delay_mod[0]), .O(\fine_delay_mod[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1027" *) LUT4 #( .INIT(16'h111F)) \fine_delay_mod[2]_i_10 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[2]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1033" *) LUT4 #( .INIT(16'h1000)) \fine_delay_mod[2]_i_2 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[2]_i_2_n_0 )); LUT5 #( .INIT(32'h00A80000)) \fine_delay_mod[2]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[1]__4_n_0 ), .I2(\fine_delay_mod[2]_i_7_n_0 ), .I3(\A[2]__1_n_0 ), .I4(\fine_delay_mod[14]_i_6_n_0 ), .O(\fine_delay_mod[2]_i_3_n_0 )); LUT6 #( .INIT(64'h5500752055005500)) \fine_delay_mod[2]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[0]__4_n_0 ), .I2(\A[1]__4_n_0 ), .I3(\genblk9[7].fine_delay_incdec_pb_reg[7] ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[2]_i_4_n_0 )); LUT6 #( .INIT(64'hAA80000000000000)) \fine_delay_mod[2]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(\fine_delay_mod[5]_i_8_n_0 ), .I5(\fine_delay_mod[2]_i_8_n_0 ), .O(\fine_delay_mod[2]_i_5_n_0 )); LUT6 #( .INIT(64'hFDDDFDDDFFFFFDDD)) \fine_delay_mod[2]_i_6 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\fine_delay_mod[2]_i_9_n_0 ), .I2(\fine_delay_mod[5]_i_11_n_0 ), .I3(\fine_delay_mod[20]_i_8_n_0 ), .I4(\fine_delay_mod[2]_i_10_n_0 ), .I5(\A[2]__1_n_0 ), .O(fine_delay_mod0[2])); (* SOFT_HLUTNM = "soft_lutpair1034" *) LUT3 #( .INIT(8'hF8)) \fine_delay_mod[2]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[2]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1022" *) LUT5 #( .INIT(32'h00FF00A8)) \fine_delay_mod[2]_i_8 (.I0(\A[1]__0_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A_n_0_[1] ), .I3(\A[0]__0_n_0 ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[2]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1028" *) LUT4 #( .INIT(16'h010F)) \fine_delay_mod[2]_i_9 (.I0(byte_sel_data_map), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__4_n_0 ), .I3(\A[1]__4_n_0 ), .O(\fine_delay_mod[2]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[5]_i_1 (.I0(\fine_delay_mod[5]_i_2_n_0 ), .I1(\fine_delay_mod[5]_i_3_n_0 ), .I2(\fine_delay_mod[5]_i_4_n_0 ), .I3(\fine_delay_mod[5]_i_5_n_0 ), .I4(fine_delay_mod0[5]), .I5(fine_delay_mod[1]), .O(\fine_delay_mod[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1028" *) LUT4 #( .INIT(16'h10F0)) \fine_delay_mod[5]_i_10 (.I0(byte_sel_data_map), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__4_n_0 ), .I3(\A[1]__4_n_0 ), .O(\fine_delay_mod[5]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1025" *) LUT2 #( .INIT(4'h1)) \fine_delay_mod[5]_i_11 (.I0(byte_sel_data_map), .I1(\A[0]__0_n_0 ), .O(\fine_delay_mod[5]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1030" *) LUT4 #( .INIT(16'h22F2)) \fine_delay_mod[5]_i_12 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[5]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1033" *) LUT4 #( .INIT(16'h0040)) \fine_delay_mod[5]_i_2 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1031" *) LUT4 #( .INIT(16'h0400)) \fine_delay_mod[5]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\fine_delay_mod[5]_i_7_n_0 ), .I2(\A[2]__1_n_0 ), .I3(\fine_delay_mod[17]_i_6_n_0 ), .O(\fine_delay_mod[5]_i_3_n_0 )); LUT6 #( .INIT(64'hAA00EA40AA00AA00)) \fine_delay_mod[5]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .I3(\genblk9[7].fine_delay_incdec_pb_reg[7] ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[5]_i_4_n_0 )); LUT6 #( .INIT(64'h4055000000000000)) \fine_delay_mod[5]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(\fine_delay_mod[5]_i_8_n_0 ), .I5(\fine_delay_mod[5]_i_9_n_0 ), .O(\fine_delay_mod[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFEEEFEEEFFFFFEEE)) \fine_delay_mod[5]_i_6 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\fine_delay_mod[5]_i_10_n_0 ), .I2(\fine_delay_mod[5]_i_11_n_0 ), .I3(\fine_delay_mod[23]_i_9_n_0 ), .I4(\fine_delay_mod[5]_i_12_n_0 ), .I5(\A[2]__1_n_0 ), .O(fine_delay_mod0[5])); (* SOFT_HLUTNM = "soft_lutpair1035" *) LUT3 #( .INIT(8'h8F)) \fine_delay_mod[5]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1026" *) LUT4 #( .INIT(16'h0004)) \fine_delay_mod[5]_i_8 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I2(\A[0]__0_n_0 ), .I3(byte_sel_data_map), .O(\fine_delay_mod[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1022" *) LUT5 #( .INIT(32'hFF008A00)) \fine_delay_mod[5]_i_9 (.I0(\A[1]__0_n_0 ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[5]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[8]_i_1 (.I0(\fine_delay_mod[8]_i_2_n_0 ), .I1(\fine_delay_mod[8]_i_3_n_0 ), .I2(\fine_delay_mod[8]_i_4_n_0 ), .I3(\fine_delay_mod[8]_i_5_n_0 ), .I4(fine_delay_mod0[8]), .I5(fine_delay_mod[2]), .O(\fine_delay_mod[8]_i_1_n_0 )); LUT6 #( .INIT(64'h00440044004F0044)) \fine_delay_mod[8]_i_10 (.I0(\A[0]__4_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\fine_delay_mod_reg[26]_0 ), .I4(byte_sel_data_map), .I5(\A[0]__0_n_0 ), .O(\fine_delay_mod[8]_i_10_n_0 )); LUT6 #( .INIT(64'h40404040FB404040)) \fine_delay_mod[8]_i_2 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\A[1]__3_n_0 ), .I4(\genblk9[5].fine_delay_incdec_pb_reg[5] ), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[8]_i_2_n_0 )); LUT6 #( .INIT(64'h0000DD0C00000000)) \fine_delay_mod[8]_i_3 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\fine_delay_mod[8]_i_7_n_0 ), .I4(\A[2]__1_n_0 ), .I5(\fine_delay_mod[20]_i_6_n_0 ), .O(\fine_delay_mod[8]_i_3_n_0 )); LUT6 #( .INIT(64'h000D000000000000)) \fine_delay_mod[8]_i_4 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0080008000880080)) \fine_delay_mod[8]_i_5 (.I0(\fine_delay_mod[11]_i_9_n_0 ), .I1(\fine_delay_mod[8]_i_8_n_0 ), .I2(\A[2]__1_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\fine_delay_mod[20]_i_7_n_0 ), .I5(\A[1]__0_n_0 ), .O(\fine_delay_mod[8]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF4F44)) \fine_delay_mod[8]_i_6 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__3_n_0 ), .I4(\fine_delay_mod[8]_i_9_n_0 ), .I5(\fine_delay_mod[8]_i_10_n_0 ), .O(fine_delay_mod0[8])); (* SOFT_HLUTNM = "soft_lutpair1034" *) LUT3 #( .INIT(8'hF1)) \fine_delay_mod[8]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[8]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1024" *) LUT5 #( .INIT(32'hAB00ABAB)) \fine_delay_mod[8]_i_8 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(byte_sel_data_map), .I3(\fine_delay_mod_reg[26]_0 ), .I4(\A[1]__3_n_0 ), .O(\fine_delay_mod[8]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1023" *) LUT5 #( .INIT(32'h00004F44)) \fine_delay_mod[8]_i_9 (.I0(\A[0]__0_n_0 ), .I1(\A[1]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A_n_0_[1] ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[8]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[11] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[11]_i_1_n_0 ), .Q(fine_delay_mod[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[14] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[14]_i_1_n_0 ), .Q(fine_delay_mod[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[17] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[17]_i_1_n_0 ), .Q(fine_delay_mod[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[20] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[20]_i_1_n_0 ), .Q(fine_delay_mod[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[23] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[23]_i_1_n_0 ), .Q(fine_delay_mod[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[26] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[26]_i_1_n_0 ), .Q(fine_delay_mod[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[2] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[2]_i_1_n_0 ), .Q(fine_delay_mod[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[5] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[5]_i_1_n_0 ), .Q(fine_delay_mod[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fine_delay_mod_reg[8] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[8]_i_1_n_0 ), .Q(fine_delay_mod[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) fine_delay_sel_r_reg (.C(CLK), .CE(1'b1), .D(fine_delay_sel_reg), .Q(fine_delay_sel_r), .R(1'b0)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[0].u_addr_obuf (.I(mem_dq_out[83]), .O(ddr3_addr[0])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[10].u_addr_obuf (.I(mem_dq_out[90]), .O(ddr3_addr[10])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[11].u_addr_obuf (.I(mem_dq_out[91]), .O(ddr3_addr[11])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[12].u_addr_obuf (.I(mem_dq_out[92]), .O(ddr3_addr[12])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[13].u_addr_obuf (.I(mem_dq_out[93]), .O(ddr3_addr[13])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[14].u_addr_obuf (.I(mem_dq_out[64]), .O(ddr3_addr[14])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[1].u_addr_obuf (.I(mem_dq_out[78]), .O(ddr3_addr[1])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[2].u_addr_obuf (.I(mem_dq_out[79]), .O(ddr3_addr[2])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[3].u_addr_obuf (.I(mem_dq_out[80]), .O(ddr3_addr[3])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[4].u_addr_obuf (.I(mem_dq_out[77]), .O(ddr3_addr[4])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[5].u_addr_obuf (.I(mem_dq_out[85]), .O(ddr3_addr[5])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[6].u_addr_obuf (.I(mem_dq_out[86]), .O(ddr3_addr[6])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[7].u_addr_obuf (.I(mem_dq_out[87]), .O(ddr3_addr[7])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[8].u_addr_obuf (.I(mem_dq_out[88]), .O(ddr3_addr[8])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[9].u_addr_obuf (.I(mem_dq_out[89]), .O(ddr3_addr[9])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_bank_obuf[0].u_bank_obuf (.I(mem_dq_out[76]), .O(ddr3_ba[0])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_bank_obuf[1].u_bank_obuf (.I(mem_dq_out[81]), .O(ddr3_ba[1])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_bank_obuf[2].u_bank_obuf (.I(mem_dq_out[82]), .O(ddr3_ba[2])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf (.I(mem_dq_out[48]), .O(ddr3_cs_n)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[0].u_dm_obuf (.I(mem_dq_out[45]), .O(ddr3_dm[0]), .T(mem_dq_ts[45])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[1].u_dm_obuf (.I(mem_dq_out[33]), .O(ddr3_dm[1]), .T(mem_dq_ts[33])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[2].u_dm_obuf (.I(mem_dq_out[21]), .O(ddr3_dm[2]), .T(mem_dq_ts[21])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[3].u_dm_obuf (.I(mem_dq_out[9]), .O(ddr3_dm[3]), .T(mem_dq_ts[9])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[0].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[44]), .IBUFDISABLE(idle), .IO(ddr3_dq[0]), .O(mem_dq_in[38]), .T(mem_dq_ts[44])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[10].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[30]), .IBUFDISABLE(idle), .IO(ddr3_dq[10]), .O(mem_dq_in[26]), .T(mem_dq_ts[30])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[11].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[29]), .IBUFDISABLE(idle), .IO(ddr3_dq[11]), .O(mem_dq_in[25]), .T(mem_dq_ts[29])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[12].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[28]), .IBUFDISABLE(idle), .IO(ddr3_dq[12]), .O(mem_dq_in[24]), .T(mem_dq_ts[28])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[13].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[27]), .IBUFDISABLE(idle), .IO(ddr3_dq[13]), .O(mem_dq_in[23]), .T(mem_dq_ts[27])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[14].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[26]), .IBUFDISABLE(idle), .IO(ddr3_dq[14]), .O(mem_dq_in[22]), .T(mem_dq_ts[26])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[15].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[25]), .IBUFDISABLE(idle), .IO(ddr3_dq[15]), .O(mem_dq_in[21]), .T(mem_dq_ts[25])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[16].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[20]), .IBUFDISABLE(idle), .IO(ddr3_dq[16]), .O(mem_dq_in[18]), .T(mem_dq_ts[20])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[17].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[19]), .IBUFDISABLE(idle), .IO(ddr3_dq[17]), .O(mem_dq_in[17]), .T(mem_dq_ts[19])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[18].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[18]), .IBUFDISABLE(idle), .IO(ddr3_dq[18]), .O(mem_dq_in[16]), .T(mem_dq_ts[18])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[19].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[17]), .IBUFDISABLE(idle), .IO(ddr3_dq[19]), .O(mem_dq_in[15]), .T(mem_dq_ts[17])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[1].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[43]), .IBUFDISABLE(idle), .IO(ddr3_dq[1]), .O(mem_dq_in[37]), .T(mem_dq_ts[43])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[20].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[16]), .IBUFDISABLE(idle), .IO(ddr3_dq[20]), .O(mem_dq_in[14]), .T(mem_dq_ts[16])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[21].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[15]), .IBUFDISABLE(idle), .IO(ddr3_dq[21]), .O(mem_dq_in[13]), .T(mem_dq_ts[15])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[22].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[14]), .IBUFDISABLE(idle), .IO(ddr3_dq[22]), .O(mem_dq_in[12]), .T(mem_dq_ts[14])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[23].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[13]), .IBUFDISABLE(idle), .IO(ddr3_dq[23]), .O(mem_dq_in[11]), .T(mem_dq_ts[13])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[24].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[7]), .IBUFDISABLE(idle), .IO(ddr3_dq[24]), .O(mem_dq_in[7]), .T(mem_dq_ts[7])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[25].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[6]), .IBUFDISABLE(idle), .IO(ddr3_dq[25]), .O(mem_dq_in[6]), .T(mem_dq_ts[6])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[26].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[5]), .IBUFDISABLE(idle), .IO(ddr3_dq[26]), .O(mem_dq_in[5]), .T(mem_dq_ts[5])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[27].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[4]), .IBUFDISABLE(idle), .IO(ddr3_dq[27]), .O(mem_dq_in[4]), .T(mem_dq_ts[4])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[28].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[3]), .IBUFDISABLE(idle), .IO(ddr3_dq[28]), .O(mem_dq_in[3]), .T(mem_dq_ts[3])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[29].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[2]), .IBUFDISABLE(idle), .IO(ddr3_dq[29]), .O(mem_dq_in[2]), .T(mem_dq_ts[2])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[2].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[42]), .IBUFDISABLE(idle), .IO(ddr3_dq[2]), .O(mem_dq_in[36]), .T(mem_dq_ts[42])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[30].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[1]), .IBUFDISABLE(idle), .IO(ddr3_dq[30]), .O(mem_dq_in[1]), .T(mem_dq_ts[1])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[31].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[0]), .IBUFDISABLE(idle), .IO(ddr3_dq[31]), .O(mem_dq_in[0]), .T(mem_dq_ts[0])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[3].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[41]), .IBUFDISABLE(idle), .IO(ddr3_dq[3]), .O(mem_dq_in[35]), .T(mem_dq_ts[41])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[4].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[40]), .IBUFDISABLE(idle), .IO(ddr3_dq[4]), .O(mem_dq_in[34]), .T(mem_dq_ts[40])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[5].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[39]), .IBUFDISABLE(idle), .IO(ddr3_dq[5]), .O(mem_dq_in[33]), .T(mem_dq_ts[39])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[6].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[38]), .IBUFDISABLE(idle), .IO(ddr3_dq[6]), .O(mem_dq_in[32]), .T(mem_dq_ts[38])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[7].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[37]), .IBUFDISABLE(idle), .IO(ddr3_dq[7]), .O(mem_dq_in[31]), .T(mem_dq_ts[37])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[8].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[32]), .IBUFDISABLE(idle), .IO(ddr3_dq[8]), .O(mem_dq_in[28]), .T(mem_dq_ts[32])); (* box_type = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[9].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[31]), .IBUFDISABLE(idle), .IO(ddr3_dq[9]), .O(mem_dq_in[27]), .T(mem_dq_ts[31])); ddr3_ifmig_7series_v4_0_poc_pd \gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .in_dqs_lpbk_to_iddr_0(in_dqs_lpbk_to_iddr_0), .mmcm_ps_clk(mmcm_ps_clk), .pd_out_pre(pd_out_pre[0]), .rst_sync_r1(rst_sync_r1)); (* box_type = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[3]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[0]), .IOB(ddr3_dqs_n[0]), .O(mem_dqs_in[3]), .OB(in_dqs_lpbk_to_iddr_0), .TM(mem_dqs_ts[3]), .TS(mem_dqs_ts[3])); ddr3_ifmig_7series_v4_0_poc_pd_1 \gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .in_dqs_lpbk_to_iddr_1(in_dqs_lpbk_to_iddr_1), .mmcm_ps_clk(mmcm_ps_clk), .pd_out_pre(pd_out_pre[1]), .rst_sync_r1(rst_sync_r1)); (* box_type = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[2]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[1]), .IOB(ddr3_dqs_n[1]), .O(mem_dqs_in[2]), .OB(in_dqs_lpbk_to_iddr_1), .TM(mem_dqs_ts[2]), .TS(mem_dqs_ts[2])); ddr3_ifmig_7series_v4_0_poc_pd_2 \gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .in_dqs_lpbk_to_iddr_2(in_dqs_lpbk_to_iddr_2), .mmcm_ps_clk(mmcm_ps_clk), .pd_out_pre(pd_out_pre[2]), .rst_sync_r1(rst_sync_r1)); (* box_type = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[1]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[2]), .IOB(ddr3_dqs_n[2]), .O(mem_dqs_in[1]), .OB(in_dqs_lpbk_to_iddr_2), .TM(mem_dqs_ts[1]), .TS(mem_dqs_ts[1])); ddr3_ifmig_7series_v4_0_poc_pd_3 \gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\gen_byte_sel_div1.byte_sel_cnt_reg[1] ), .in_dqs_lpbk_to_iddr_3(in_dqs_lpbk_to_iddr_3), .mmcm_ps_clk(mmcm_ps_clk), .pd_out(pd_out), .pd_out_r_reg_0(pd_out_pre), .rst_sync_r1(rst_sync_r1)); (* box_type = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[0]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[3]), .IOB(ddr3_dqs_n[3]), .O(mem_dqs_in[0]), .OB(in_dqs_lpbk_to_iddr_3), .TM(mem_dqs_ts[0]), .TS(mem_dqs_ts[0])); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_reset_obuf.u_reset_obuf (.I(mux_reset_n), .O(ddr3_reset_n)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo \genblk24.phy_ctl_pre_fifo_0 (.CLK(CLK), .SR(SR)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized0 \genblk24.phy_ctl_pre_fifo_1 (.CLK(CLK), .SR(SR)); ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized1 \genblk24.phy_ctl_pre_fifo_2 (.CLK(CLK), .SR(SR)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(phy_ctl_wd_i1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[17] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(phy_ctl_wd_i1[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[18] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(phy_ctl_wd_i1[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[19] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(phy_ctl_wd_i1[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(phy_ctl_wd_i1[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[20] (.C(CLK), .CE(1'b1), .D(D[6]), .Q(phy_ctl_wd_i1[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[21] (.C(CLK), .CE(1'b1), .D(D[7]), .Q(phy_ctl_wd_i1[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[22] (.C(CLK), .CE(1'b1), .D(D[8]), .Q(phy_ctl_wd_i1[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[23] (.C(CLK), .CE(1'b1), .D(D[9]), .Q(phy_ctl_wd_i1[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[24] (.C(CLK), .CE(1'b1), .D(D[10]), .Q(phy_ctl_wd_i1[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i1_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(phy_ctl_wd_i1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[0] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[0]), .Q(phy_ctl_wd_i2[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[17] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[17]), .Q(phy_ctl_wd_i2[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[18] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[18]), .Q(phy_ctl_wd_i2[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[19] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[19]), .Q(phy_ctl_wd_i2[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[1] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[1]), .Q(phy_ctl_wd_i2[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[20] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[20]), .Q(phy_ctl_wd_i2[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[21] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[21]), .Q(phy_ctl_wd_i2[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[22] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[22]), .Q(phy_ctl_wd_i2[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[23] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[23]), .Q(phy_ctl_wd_i2[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[24] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[24]), .Q(phy_ctl_wd_i2[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \phy_ctl_wd_i2_reg[2] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[2]), .Q(phy_ctl_wd_i2[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) phy_ctl_wr_i1_reg (.C(CLK), .CE(1'b1), .D(mux_cmd_wren), .Q(phy_ctl_wr_i1), .R(1'b0)); FDRE #( .INIT(1'b0)) phy_ctl_wr_i2_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_wr_i1), .Q(phy_ctl_wr_i2), .R(1'b0)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) u_cas_n_obuf (.I(mem_dq_out[74]), .O(ddr3_cas_n)); ddr3_ifmig_7series_v4_0_ddr_mc_phy u_ddr_mc_phy (.A(A), .CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .COUNTERLOADVAL(COUNTERLOADVAL), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8), .D9(D9), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .D_po_counter_read_en122_out(D_po_counter_read_en122_out), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .E(E), .LD0(LD0), .LD0_3(LD0_3), .LD0_4(LD0_4), .LD0_5(LD0_5), .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}), .RST0(RST0), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[0]_0 (\byte_r_reg[0]_0 ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ), .\calib_sel_reg[0]_3 (\calib_sel_reg[0]_3 ), .\calib_sel_reg[0]_4 (\calib_sel_reg[0]_4 ), .\calib_sel_reg[0]_5 (\calib_sel_reg[0]_5 ), .\calib_sel_reg[0]_6 (\calib_sel_reg[0]_6 ), .\calib_sel_reg[0]_7 (\calib_sel_reg[0]_7 ), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_1 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_2 ), .\calib_sel_reg[1]_3 (\calib_sel_reg[1]_3 ), .\calib_sel_reg[1]_4 (\calib_sel_reg[1]_4 ), .\calib_sel_reg[1]_5 (\calib_sel_reg[1]_5 ), .\calib_sel_reg[1]_6 (\calib_sel_reg[1]_6 ), .\calib_sel_reg[1]_7 (\calib_sel_reg[1]_7 ), .\calib_sel_reg[1]_8 (\calib_sel_reg[1]_8 ), .\calib_sel_reg[3] (\calib_sel_reg[3] ), .\calib_seq_reg[0] (\calib_seq_reg[0] ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ), .\calib_zero_inputs_reg[0]_0 (\calib_zero_inputs_reg[0]_0 ), .\calib_zero_inputs_reg[0]_1 (\calib_zero_inputs_reg[0]_1 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg), .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0), .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1), .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg), .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0), .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1), .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .\data_offset_1_i2_reg[5] (data_offset_1_i2), .ddr_ck_out(ddr_ck_out), .delay_done_r4_reg(delay_done_r4_reg), .delay_done_r4_reg_0(delay_done_r4_reg_0), .delay_done_r4_reg_1(delay_done_r4_reg_1), .delay_done_r4_reg_2(delay_done_r4_reg_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23]_0 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_byte_sel_div1.calib_in_common_reg_10 (\gen_byte_sel_div1.calib_in_common_reg_10 ), .\gen_byte_sel_div1.calib_in_common_reg_11 (\gen_byte_sel_div1.calib_in_common_reg_11 ), .\gen_byte_sel_div1.calib_in_common_reg_12 (\gen_byte_sel_div1.calib_in_common_reg_12 ), .\gen_byte_sel_div1.calib_in_common_reg_13 (\gen_byte_sel_div1.calib_in_common_reg_13 ), .\gen_byte_sel_div1.calib_in_common_reg_14 (\gen_byte_sel_div1.calib_in_common_reg_14 ), .\gen_byte_sel_div1.calib_in_common_reg_15 (\gen_byte_sel_div1.calib_in_common_reg_15 ), .\gen_byte_sel_div1.calib_in_common_reg_16 (\gen_byte_sel_div1.calib_in_common_reg_16 ), .\gen_byte_sel_div1.calib_in_common_reg_17 (\gen_byte_sel_div1.calib_in_common_reg_17 ), .\gen_byte_sel_div1.calib_in_common_reg_18 (\gen_byte_sel_div1.calib_in_common_reg_18 ), .\gen_byte_sel_div1.calib_in_common_reg_19 (\gen_byte_sel_div1.calib_in_common_reg_19 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_20 (\gen_byte_sel_div1.calib_in_common_reg_20 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .\gen_byte_sel_div1.calib_in_common_reg_4 (\gen_byte_sel_div1.calib_in_common_reg_4 ), .\gen_byte_sel_div1.calib_in_common_reg_5 (\gen_byte_sel_div1.calib_in_common_reg_5 ), .\gen_byte_sel_div1.calib_in_common_reg_6 (\gen_byte_sel_div1.calib_in_common_reg_6 ), .\gen_byte_sel_div1.calib_in_common_reg_7 (\gen_byte_sel_div1.calib_in_common_reg_7 ), .\gen_byte_sel_div1.calib_in_common_reg_8 (\gen_byte_sel_div1.calib_in_common_reg_8 ), .\gen_byte_sel_div1.calib_in_common_reg_9 (\gen_byte_sel_div1.calib_in_common_reg_9 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .idelay_ld_rst_0(idelay_ld_rst_0), .idelay_ld_rst_1(idelay_ld_rst_1), .idelay_ld_rst_2(idelay_ld_rst_2), .in0(in0), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0), .mc_address(mc_address), .mc_cas_n(mc_cas_n), .mem_dq_in({mem_dq_in[38:31],mem_dq_in[28:21],mem_dq_in[18:11],mem_dq_in[7:0]}), .mem_dq_out({mem_dq_out[93:85],mem_dq_out[83:74],mem_dq_out[71:70],mem_dq_out[64],mem_dq_out[49:48],mem_dq_out[45:37],mem_dq_out[33:25],mem_dq_out[21:13],mem_dq_out[9],mem_dq_out[7:0]}), .mem_dq_ts({mem_dq_ts[45:37],mem_dq_ts[33:25],mem_dq_ts[21:13],mem_dq_ts[9],mem_dq_ts[7:0]}), .mem_dqs_in(mem_dqs_in), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .mem_out(mem_out), .mem_refclk(mem_refclk), .mmcm_locked(mmcm_locked), .mux_cmd_wren(mux_cmd_wren), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .mux_wrdata(mux_wrdata), .mux_wrdata_en(mux_wrdata_en), .mux_wrdata_mask(mux_wrdata_mask), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ), .\my_empty_reg[1]_3 (\my_empty_reg[1]_3 ), .\my_empty_reg[1]_4 (\my_empty_reg[1]_4 ), .\my_empty_reg[1]_5 (\my_empty_reg[1]_5 ), .\my_empty_reg[1]_6 (\my_empty_reg[1]_6 ), .\my_empty_reg[7] (\my_empty_reg[7]_0 ), .\my_empty_reg[7]_0 (\my_empty_reg[7]_1 ), .\my_empty_reg[7]_1 (\my_empty_reg[7]_2 ), .\my_empty_reg[7]_2 (\my_empty_reg[7]_3 ), .\my_empty_reg[7]_3 (\my_empty_reg[7] ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] 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(\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r_reg(ofs_rdy_r_reg), .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0), .out(out), .p_0_out(p_0_out), .phy_ctl_wr_i2(phy_ctl_wr_i2), .phy_dout(phy_dout), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_if_reset(phy_if_reset), .phy_mc_ctl_full(phy_mc_ctl_full), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ), .pi_en_stg2_f_reg(pi_en_stg2_f_reg), .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0), .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1), .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2), .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg), .\pi_rdval_cnt_reg[5] (\pi_rdval_cnt_reg[5] ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg), .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0), .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1), .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2), .pll_locked(pll_locked), .\po_counter_read_val_r_reg[5] (\po_counter_read_val_r_reg[5] ), .\po_rdval_cnt_reg[8] (\po_rdval_cnt_reg[8] ), .\po_rdval_cnt_reg[8]_0 (\po_rdval_cnt_reg[8]_0 ), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_1 ), .\write_buffer.wr_buf_out_data_reg[224] (\write_buffer.wr_buf_out_data_reg[224] ), .\write_buffer.wr_buf_out_data_reg[225] (\write_buffer.wr_buf_out_data_reg[225] ), .\write_buffer.wr_buf_out_data_reg[226] (\write_buffer.wr_buf_out_data_reg[226] ), .\write_buffer.wr_buf_out_data_reg[227] (\write_buffer.wr_buf_out_data_reg[227] ), .\write_buffer.wr_buf_out_data_reg[228] (\write_buffer.wr_buf_out_data_reg[228] ), .\write_buffer.wr_buf_out_data_reg[229] (\write_buffer.wr_buf_out_data_reg[229] ), .\write_buffer.wr_buf_out_data_reg[230] (\write_buffer.wr_buf_out_data_reg[230] ), .\write_buffer.wr_buf_out_data_reg[231] (\write_buffer.wr_buf_out_data_reg[231] ), .\write_buffer.wr_buf_out_data_reg[232] (\write_buffer.wr_buf_out_data_reg[232] ), .\write_buffer.wr_buf_out_data_reg[233] (\write_buffer.wr_buf_out_data_reg[233] ), .\write_buffer.wr_buf_out_data_reg[234] (\write_buffer.wr_buf_out_data_reg[234] ), .\write_buffer.wr_buf_out_data_reg[235] (\write_buffer.wr_buf_out_data_reg[235] ), .\write_buffer.wr_buf_out_data_reg[236] (\write_buffer.wr_buf_out_data_reg[236] ), .\write_buffer.wr_buf_out_data_reg[237] (\write_buffer.wr_buf_out_data_reg[237] ), .\write_buffer.wr_buf_out_data_reg[238] (\write_buffer.wr_buf_out_data_reg[238] ), .\write_buffer.wr_buf_out_data_reg[239] (\write_buffer.wr_buf_out_data_reg[239] ), .\write_buffer.wr_buf_out_data_reg[240] (\write_buffer.wr_buf_out_data_reg[240] ), .\write_buffer.wr_buf_out_data_reg[241] (\write_buffer.wr_buf_out_data_reg[241] ), .\write_buffer.wr_buf_out_data_reg[242] (\write_buffer.wr_buf_out_data_reg[242] ), .\write_buffer.wr_buf_out_data_reg[243] (\write_buffer.wr_buf_out_data_reg[243] ), .\write_buffer.wr_buf_out_data_reg[244] (\write_buffer.wr_buf_out_data_reg[244] ), .\write_buffer.wr_buf_out_data_reg[245] (\write_buffer.wr_buf_out_data_reg[245] ), .\write_buffer.wr_buf_out_data_reg[246] (\write_buffer.wr_buf_out_data_reg[246] ), .\write_buffer.wr_buf_out_data_reg[247] (\write_buffer.wr_buf_out_data_reg[247] ), .\write_buffer.wr_buf_out_data_reg[248] (\write_buffer.wr_buf_out_data_reg[248] ), .\write_buffer.wr_buf_out_data_reg[249] (\write_buffer.wr_buf_out_data_reg[249] ), .\write_buffer.wr_buf_out_data_reg[250] (\write_buffer.wr_buf_out_data_reg[250] ), .\write_buffer.wr_buf_out_data_reg[251] (\write_buffer.wr_buf_out_data_reg[251] ), .\write_buffer.wr_buf_out_data_reg[252] (\write_buffer.wr_buf_out_data_reg[252] ), .\write_buffer.wr_buf_out_data_reg[253] (\write_buffer.wr_buf_out_data_reg[253] ), .\write_buffer.wr_buf_out_data_reg[254] (\write_buffer.wr_buf_out_data_reg[254] ), .\write_buffer.wr_buf_out_data_reg[255] (\write_buffer.wr_buf_out_data_reg[255] ), .\write_buffer.wr_buf_out_data_reg[287] (Q)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) u_ras_n_obuf (.I(mem_dq_out[75]), .O(ddr3_ras_n)); (* CAPACITANCE = "DONT_CARE" *) (* box_type = "PRIMITIVE" *) OBUF #( .IOSTANDARD("DEFAULT")) u_we_n_obuf (.I(mem_dq_out[49]), .O(ddr3_we_n)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo (SR, CLK); input [0:0]SR; input CLK; wire CLK; wire [0:0]SR; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(wr_en)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[2]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized0 (SR, CLK); input [0:0]SR; input CLK; wire CLK; wire [0:0]SR; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(wr_en)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[2]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized1 (SR, CLK); input [0:0]SR; input CLK; wire CLK; wire [0:0]SR; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(wr_en)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[2]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized2 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D8, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D8; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[287] ; input [71:0]phy_dout; wire CLK; wire [7:0]D8; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1_n_0 ; wire \entry_cnt[1]_i_1_n_0 ; wire \entry_cnt[2]_i_1_n_0 ; wire \entry_cnt[3]_i_1_n_0 ; wire \entry_cnt[4]_i_1_n_0 ; wire \entry_cnt[4]_i_2_n_0 ; wire \entry_cnt[4]_i_3_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_60_65_n_4; wire mem_reg_0_15_60_65_n_5; wire mem_reg_0_15_66_71_n_0; wire mem_reg_0_15_66_71_n_1; wire mem_reg_0_15_66_71_n_2; wire mem_reg_0_15_66_71_n_3; wire mem_reg_0_15_66_71_n_4; wire mem_reg_0_15_66_71_n_5; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__0_n_0 ; wire \my_empty[7]_i_1__0_n_0 ; wire \my_empty[7]_i_3__0_n_0 ; wire \my_empty[7]_i_4__0_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1_n_0 ; wire \my_full[4]_i_3__0_n_0 ; wire \my_full[4]_i_4__0_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__0_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[287] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair769" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair766" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair769" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1 (.I0(\entry_cnt[4]_i_3_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair766" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[0]_i_1_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[1]_i_1_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[2]_i_1_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[3]_i_1_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[4]_i_2_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[1:0]), .DIB(phy_dout[3:2]), .DIC(phy_dout[5:4]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [1:0]), .DOB(\my_empty_reg[7]_1 [3:2]), .DOC(\my_empty_reg[7]_1 [5:4]), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__0 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[13:12]), .DIB(phy_dout[15:14]), .DIC(phy_dout[17:16]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [13:12]), .DOB(\my_empty_reg[7]_1 [15:14]), .DOC(\my_empty_reg[7]_1 [17:16]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[19:18]), .DIB(phy_dout[21:20]), .DIC(phy_dout[23:22]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [19:18]), .DOB(\my_empty_reg[7]_1 [21:20]), .DOC(\my_empty_reg[7]_1 [23:22]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[25:24]), .DIB(phy_dout[27:26]), .DIC(phy_dout[29:28]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [25:24]), .DOB(\my_empty_reg[7]_1 [27:26]), .DOC(\my_empty_reg[7]_1 [29:28]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[31:30]), .DIB(phy_dout[33:32]), .DIC(phy_dout[35:34]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [31:30]), .DOB(\my_empty_reg[7]_1 [33:32]), .DOC(\my_empty_reg[7]_1 [35:34]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[37:36]), .DIB(phy_dout[39:38]), .DIC(phy_dout[41:40]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [37:36]), .DOB(\my_empty_reg[7]_1 [39:38]), .DOC(\my_empty_reg[7]_1 [41:40]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[43:42]), .DIB(phy_dout[45:44]), .DIC(phy_dout[47:46]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [43:42]), .DOB(\my_empty_reg[7]_1 [45:44]), .DOC(\my_empty_reg[7]_1 [47:46]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[49:48]), .DIB(phy_dout[51:50]), .DIC(phy_dout[53:52]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [49:48]), .DOB(\my_empty_reg[7]_1 [51:50]), .DOC(\my_empty_reg[7]_1 [53:52]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[55:54]), .DIB(phy_dout[57:56]), .DIC(phy_dout[59:58]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [55:54]), .DOB(\my_empty_reg[7]_1 [57:56]), .DOC(\my_empty_reg[7]_1 [59:58]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[61:60]), .DIB(phy_dout[63:62]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [61:60]), .DOB(\my_empty_reg[7]_1 [63:62]), .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}), .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}), .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[7:6]), .DIB(phy_dout[9:8]), .DIC(phy_dout[11:10]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [7:6]), .DOB(\my_empty_reg[7]_1 [9:8]), .DOC(\my_empty_reg[7]_1 [11:10]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__0 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__0 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__0 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__0_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__0_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair768" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__0 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair768" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__0 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__0_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__0_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__0 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__0_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__0_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair767" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__0 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair767" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__0 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__3 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair775" *) LUT2 #( .INIT(4'h2)) out_fifo_i_66__0 (.I0(mem_reg_0_15_66_71_n_4), .I1(\my_empty_reg[1]_0 ), .O(D8[7])); (* SOFT_HLUTNM = "soft_lutpair772" *) LUT2 #( .INIT(4'h2)) out_fifo_i_67__0 (.I0(mem_reg_0_15_66_71_n_5), .I1(\my_empty_reg[1]_0 ), .O(D8[6])); (* SOFT_HLUTNM = "soft_lutpair774" *) LUT2 #( .INIT(4'h2)) out_fifo_i_68__1 (.I0(mem_reg_0_15_66_71_n_2), .I1(\my_empty_reg[1]_0 ), .O(D8[5])); (* SOFT_HLUTNM = "soft_lutpair770" *) LUT2 #( .INIT(4'h2)) out_fifo_i_69__1 (.I0(mem_reg_0_15_66_71_n_3), .I1(\my_empty_reg[1]_0 ), .O(D8[4])); (* SOFT_HLUTNM = "soft_lutpair778" *) LUT2 #( .INIT(4'h2)) out_fifo_i_70 (.I0(mem_reg_0_15_66_71_n_0), .I1(\my_empty_reg[1]_0 ), .O(D8[3])); (* SOFT_HLUTNM = "soft_lutpair771" *) LUT2 #( .INIT(4'h2)) out_fifo_i_71 (.I0(mem_reg_0_15_66_71_n_1), .I1(\my_empty_reg[1]_0 ), .O(D8[2])); (* SOFT_HLUTNM = "soft_lutpair779" *) LUT2 #( .INIT(4'h2)) out_fifo_i_72 (.I0(mem_reg_0_15_60_65_n_4), .I1(\my_empty_reg[1]_0 ), .O(D8[1])); (* SOFT_HLUTNM = "soft_lutpair773" *) LUT2 #( .INIT(4'h2)) out_fifo_i_73 (.I0(mem_reg_0_15_60_65_n_5), .I1(\my_empty_reg[1]_0 ), .O(D8[0])); (* SOFT_HLUTNM = "soft_lutpair772" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair775" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair773" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair771" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair774" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair778" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair770" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair779" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair780" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__1 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair780" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__0 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair777" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__0 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__0 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair777" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__0 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair781" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__3 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair781" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__3 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair776" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__2 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair776" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized3 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D0, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[286] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D0; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[286] ; input [71:0]phy_dout; wire CLK; wire [7:0]D0; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1__0_n_0 ; wire \entry_cnt[1]_i_1__0_n_0 ; wire \entry_cnt[2]_i_1__0_n_0 ; wire \entry_cnt[3]_i_1__0_n_0 ; wire \entry_cnt[4]_i_1__0_n_0 ; wire \entry_cnt[4]_i_2__0_n_0 ; wire \entry_cnt[4]_i_3__0_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_0_5_n_0; wire mem_reg_0_15_0_5_n_1; wire mem_reg_0_15_0_5_n_2; wire mem_reg_0_15_0_5_n_3; wire mem_reg_0_15_0_5_n_4; wire mem_reg_0_15_0_5_n_5; wire mem_reg_0_15_6_11_n_0; wire mem_reg_0_15_6_11_n_1; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__1_n_0 ; wire \my_empty[7]_i_1__1_n_0 ; wire \my_empty[7]_i_3__1_n_0 ; wire \my_empty[7]_i_4__1_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1__0_n_0 ; wire \my_full[4]_i_3__1_n_0 ; wire \my_full[4]_i_4__1_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__1_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[286] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair820" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1__0 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair818" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1__0 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1__0 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair820" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1__0 (.I0(\entry_cnt[4]_i_3__0_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1__0_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1__0 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2__0 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3__0_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair818" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3__0 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3__0_n_0 )); FDRE #( .INIT(1'b0)) \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[0]_i_1__0_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[1]_i_1__0_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[2]_i_1__0_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[3]_i_1__0_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[4]_i_2__0_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}), .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}), .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__1 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[5:4]), .DIB(phy_dout[7:6]), .DIC(phy_dout[9:8]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [5:4]), .DOB(\my_empty_reg[7]_1 [7:6]), .DOC(\my_empty_reg[7]_1 [9:8]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[11:10]), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [11:10]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[17:16]), .DIB(phy_dout[19:18]), .DIC(phy_dout[21:20]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [17:16]), .DOB(\my_empty_reg[7]_1 [19:18]), .DOC(\my_empty_reg[7]_1 [21:20]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[23:22]), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [23:22]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[29:28]), .DIB(phy_dout[31:30]), .DIC(phy_dout[33:32]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [29:28]), .DOB(\my_empty_reg[7]_1 [31:30]), .DOC(\my_empty_reg[7]_1 [33:32]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[35:34]), .DIB(phy_dout[37:36]), .DIC(phy_dout[39:38]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [35:34]), .DOB(\my_empty_reg[7]_1 [37:36]), .DOC(\my_empty_reg[7]_1 [39:38]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[41:40]), .DIB(phy_dout[43:42]), .DIC(phy_dout[45:44]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [41:40]), .DOB(\my_empty_reg[7]_1 [43:42]), .DOC(\my_empty_reg[7]_1 [45:44]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[47:46]), .DIB(phy_dout[49:48]), .DIC(phy_dout[51:50]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [47:46]), .DOB(\my_empty_reg[7]_1 [49:48]), .DOC(\my_empty_reg[7]_1 [51:50]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[53:52]), .DIB(phy_dout[55:54]), .DIC(phy_dout[57:56]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [53:52]), .DOB(\my_empty_reg[7]_1 [55:54]), .DOC(\my_empty_reg[7]_1 [57:56]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[59:58]), .DIB(phy_dout[61:60]), .DIC(phy_dout[63:62]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [59:58]), .DOB(\my_empty_reg[7]_1 [61:60]), .DOC(\my_empty_reg[7]_1 [63:62]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__1 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__1 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__1 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__1_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__1_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair821" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__1 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair821" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__1 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__1_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__1_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1__0 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__1 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__1_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__1_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair819" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__1 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair819" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__1 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1__0_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__4 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair827" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__3 (.I0(mem_reg_0_15_6_11_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[7])); (* SOFT_HLUTNM = "soft_lutpair823" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__3 (.I0(mem_reg_0_15_6_11_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[6])); (* SOFT_HLUTNM = "soft_lutpair828" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__3 (.I0(mem_reg_0_15_0_5_n_4), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair825" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__3 (.I0(mem_reg_0_15_0_5_n_5), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair826" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__3 (.I0(mem_reg_0_15_0_5_n_2), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair824" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair827" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair825" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair826" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair823" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair829" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair822" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__2 (.I0(mem_reg_0_15_0_5_n_3), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair822" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair828" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair829" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__2 (.I0(mem_reg_0_15_0_5_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair824" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__2 (.I0(mem_reg_0_15_0_5_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair833" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__3 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair833" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__1 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair831" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__1 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__1 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair831" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__1 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair832" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__5 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair832" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__5 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair830" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__3 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair830" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2__0 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized4 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D0, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[285] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D0; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[285] ; input [71:0]phy_dout; wire CLK; wire [7:0]D0; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1__1_n_0 ; wire \entry_cnt[1]_i_1__1_n_0 ; wire \entry_cnt[2]_i_1__1_n_0 ; wire \entry_cnt[3]_i_1__1_n_0 ; wire \entry_cnt[4]_i_1__1_n_0 ; wire \entry_cnt[4]_i_2__1_n_0 ; wire \entry_cnt[4]_i_3__1_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_0_5_n_0; wire mem_reg_0_15_0_5_n_1; wire mem_reg_0_15_0_5_n_2; wire mem_reg_0_15_0_5_n_3; wire mem_reg_0_15_0_5_n_4; wire mem_reg_0_15_0_5_n_5; wire mem_reg_0_15_6_11_n_0; wire mem_reg_0_15_6_11_n_1; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__2_n_0 ; wire \my_empty[7]_i_1__2_n_0 ; wire \my_empty[7]_i_3__2_n_0 ; wire \my_empty[7]_i_4__2_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1__1_n_0 ; wire \my_full[4]_i_3__2_n_0 ; wire \my_full[4]_i_4__2_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__2_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[285] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair871" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1__1 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair869" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1__1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1__1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair871" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1__1 (.I0(\entry_cnt[4]_i_3__1_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1__1_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1__1 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2__1 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3__1_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair869" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3__1 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3__1_n_0 )); FDRE #( .INIT(1'b0)) \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[0]_i_1__1_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[1]_i_1__1_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[2]_i_1__1_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[3]_i_1__1_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[4]_i_2__1_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}), .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}), .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[5:4]), .DIB(phy_dout[7:6]), .DIC(phy_dout[9:8]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [5:4]), .DOB(\my_empty_reg[7]_1 [7:6]), .DOC(\my_empty_reg[7]_1 [9:8]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[11:10]), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [11:10]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[17:16]), .DIB(phy_dout[19:18]), .DIC(phy_dout[21:20]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [17:16]), .DOB(\my_empty_reg[7]_1 [19:18]), .DOC(\my_empty_reg[7]_1 [21:20]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[23:22]), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [23:22]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[29:28]), .DIB(phy_dout[31:30]), .DIC(phy_dout[33:32]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [29:28]), .DOB(\my_empty_reg[7]_1 [31:30]), .DOC(\my_empty_reg[7]_1 [33:32]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[35:34]), .DIB(phy_dout[37:36]), .DIC(phy_dout[39:38]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [35:34]), .DOB(\my_empty_reg[7]_1 [37:36]), .DOC(\my_empty_reg[7]_1 [39:38]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[41:40]), .DIB(phy_dout[43:42]), .DIC(phy_dout[45:44]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [41:40]), .DOB(\my_empty_reg[7]_1 [43:42]), .DOC(\my_empty_reg[7]_1 [45:44]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[47:46]), .DIB(phy_dout[49:48]), .DIC(phy_dout[51:50]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [47:46]), .DOB(\my_empty_reg[7]_1 [49:48]), .DOC(\my_empty_reg[7]_1 [51:50]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[53:52]), .DIB(phy_dout[55:54]), .DIC(phy_dout[57:56]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [53:52]), .DOB(\my_empty_reg[7]_1 [55:54]), .DOC(\my_empty_reg[7]_1 [57:56]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[59:58]), .DIB(phy_dout[61:60]), .DIC(phy_dout[63:62]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [59:58]), .DOB(\my_empty_reg[7]_1 [61:60]), .DOC(\my_empty_reg[7]_1 [63:62]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__2_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__2 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__2_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__2_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair872" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__2 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair872" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__2 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__2_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__2_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__2_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1__1 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__2 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__2_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__2_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair870" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__2 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair870" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__2 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__2_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1__1_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__5 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair878" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__4 (.I0(mem_reg_0_15_6_11_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[7])); (* SOFT_HLUTNM = "soft_lutpair874" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__4 (.I0(mem_reg_0_15_6_11_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[6])); (* SOFT_HLUTNM = "soft_lutpair879" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__4 (.I0(mem_reg_0_15_0_5_n_4), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair876" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__4 (.I0(mem_reg_0_15_0_5_n_5), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair877" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__4 (.I0(mem_reg_0_15_0_5_n_2), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair875" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair878" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair876" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair877" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair874" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair880" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair873" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__3 (.I0(mem_reg_0_15_0_5_n_3), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair873" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair879" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair880" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__3 (.I0(mem_reg_0_15_0_5_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair875" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__3 (.I0(mem_reg_0_15_0_5_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair884" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__5 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair884" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__2 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair882" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__2 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__2 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair882" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__2 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair883" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__7 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair883" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__7 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair881" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__4 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__4 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair881" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2__1 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized5 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D0, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[284] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D0; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[284] ; input [71:0]phy_dout; wire CLK; wire [7:0]D0; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1__2_n_0 ; wire \entry_cnt[1]_i_1__2_n_0 ; wire \entry_cnt[2]_i_1__2_n_0 ; wire \entry_cnt[3]_i_1__2_n_0 ; wire \entry_cnt[4]_i_1__2_n_0 ; wire \entry_cnt[4]_i_2__2_n_0 ; wire \entry_cnt[4]_i_3__2_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_0_5_n_0; wire mem_reg_0_15_0_5_n_1; wire mem_reg_0_15_0_5_n_2; wire mem_reg_0_15_0_5_n_3; wire mem_reg_0_15_0_5_n_4; wire mem_reg_0_15_0_5_n_5; wire mem_reg_0_15_6_11_n_0; wire mem_reg_0_15_6_11_n_1; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__3_n_0 ; wire \my_empty[7]_i_1__3_n_0 ; wire \my_empty[7]_i_3__3_n_0 ; wire \my_empty[7]_i_4__3_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1__2_n_0 ; wire \my_full[4]_i_3__3_n_0 ; wire \my_full[4]_i_4__3_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__3_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[284] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair923" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1__2 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair921" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1__2 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1__2 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair923" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1__2 (.I0(\entry_cnt[4]_i_3__2_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1__2_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1__2 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2__2 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3__2_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair921" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3__2 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3__2_n_0 )); FDRE #( .INIT(1'b0)) \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[0]_i_1__2_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[1]_i_1__2_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[2]_i_1__2_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[3]_i_1__2_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE #( .INIT(1'b0)) \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[4]_i_2__2_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}), .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}), .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[5:4]), .DIB(phy_dout[7:6]), .DIC(phy_dout[9:8]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [5:4]), .DOB(\my_empty_reg[7]_1 [7:6]), .DOC(\my_empty_reg[7]_1 [9:8]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[11:10]), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [11:10]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[17:16]), .DIB(phy_dout[19:18]), .DIC(phy_dout[21:20]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [17:16]), .DOB(\my_empty_reg[7]_1 [19:18]), .DOC(\my_empty_reg[7]_1 [21:20]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[23:22]), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [23:22]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[29:28]), .DIB(phy_dout[31:30]), .DIC(phy_dout[33:32]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [29:28]), .DOB(\my_empty_reg[7]_1 [31:30]), .DOC(\my_empty_reg[7]_1 [33:32]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[35:34]), .DIB(phy_dout[37:36]), .DIC(phy_dout[39:38]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [35:34]), .DOB(\my_empty_reg[7]_1 [37:36]), .DOC(\my_empty_reg[7]_1 [39:38]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[41:40]), .DIB(phy_dout[43:42]), .DIC(phy_dout[45:44]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [41:40]), .DOB(\my_empty_reg[7]_1 [43:42]), .DOC(\my_empty_reg[7]_1 [45:44]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[47:46]), .DIB(phy_dout[49:48]), .DIC(phy_dout[51:50]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [47:46]), .DOB(\my_empty_reg[7]_1 [49:48]), .DOC(\my_empty_reg[7]_1 [51:50]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[53:52]), .DIB(phy_dout[55:54]), .DIC(phy_dout[57:56]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [53:52]), .DOB(\my_empty_reg[7]_1 [55:54]), .DOC(\my_empty_reg[7]_1 [57:56]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[59:58]), .DIB(phy_dout[61:60]), .DIC(phy_dout[63:62]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [59:58]), .DOB(\my_empty_reg[7]_1 [61:60]), .DOC(\my_empty_reg[7]_1 [63:62]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__3_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__3 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__3_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__3_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair924" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__3 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair924" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__3 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__3_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__3_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__3_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1__2 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__3 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__3_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__3_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair922" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__3 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair922" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__3 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__3_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1__2_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__6 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair930" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__5 (.I0(mem_reg_0_15_6_11_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[7])); (* SOFT_HLUTNM = "soft_lutpair926" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__5 (.I0(mem_reg_0_15_6_11_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[6])); (* SOFT_HLUTNM = "soft_lutpair931" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__5 (.I0(mem_reg_0_15_0_5_n_4), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair928" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__5 (.I0(mem_reg_0_15_0_5_n_5), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair929" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__5 (.I0(mem_reg_0_15_0_5_n_2), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair927" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair930" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair928" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair929" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair926" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair932" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair925" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__4 (.I0(mem_reg_0_15_0_5_n_3), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair925" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair931" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair932" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__4 (.I0(mem_reg_0_15_0_5_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair927" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__4 (.I0(mem_reg_0_15_0_5_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair936" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__7 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair936" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__3 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair934" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__3 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__3 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair934" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__3 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair935" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__9 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair935" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__9 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair933" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__5 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__5 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair933" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2__2 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized6 (\rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , wr_en, \my_empty_reg[1]_0 , D0, D1, \rd_ptr_timing_reg[0]_0 , D2, Q, SR, CLK, mux_cmd_wren, ofifo_rst_reg, mem_out); output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output wr_en; output \my_empty_reg[1]_0 ; output [4:0]D0; output [4:0]D1; output \rd_ptr_timing_reg[0]_0 ; output [1:0]D2; output [3:0]Q; input [0:0]SR; input CLK; input mux_cmd_wren; input ofifo_rst_reg; input [11:0]mem_out; wire CLK; wire [4:0]D0; wire [4:0]D1; wire [1:0]D2; wire [3:0]Q; wire [0:0]SR; wire [11:0]mem_out; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1__6_n_0 ; wire \my_empty[6]_i_1__1_n_0 ; wire \my_empty[6]_i_3_n_0 ; wire \my_empty[6]_i_4_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg_n_0_[6] ; wire my_full0; wire \my_full[3]_i_1_n_0 ; wire \my_full[3]_i_3_n_0 ; wire \my_full[3]_i_4_n_0 ; wire \my_full_reg_n_0_[3] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst_reg; wire \rd_ptr[0]_i_1__1_n_0 ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire wr_en; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; (* SOFT_HLUTNM = "soft_lutpair937" *) LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[1]_i_1__6 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg[1]_0 ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[1]_i_1__6_n_0 )); LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[6]_i_1__1 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg_n_0_[6] ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[6]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[6]_i_2 (.I0(wr_ptr_timing[2]), .I1(\my_empty[6]_i_3_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[6]_i_4_n_0 ), .I4(\rd_ptr_timing_reg[2]_2 ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair938" *) LUT5 #( .INIT(32'h00000040)) \my_empty[6]_i_3 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_timing_reg[2]_0 ), .I2(\rd_ptr_timing_reg[2]_1 ), .I3(\rd_ptr_timing_reg[2]_3 ), .I4(wr_ptr_timing[0]), .O(\my_empty[6]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair938" *) LUT5 #( .INIT(32'h84210842)) \my_empty[6]_i_4 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_timing_reg[2]_0 ), .I3(\rd_ptr_timing_reg[2]_1 ), .I4(\rd_ptr_timing_reg[2]_3 ), .O(\my_empty[6]_i_4_n_0 )); (* syn_maxfan = "3" *) FDSE #( .INIT(1'b1)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__6_n_0 ), .Q(\my_empty_reg[1]_0 ), .S(SR)); (* syn_maxfan = "3" *) FDSE #( .INIT(1'b1)) \my_empty_reg[6] (.C(CLK), .CE(1'b1), .D(\my_empty[6]_i_1__1_n_0 ), .Q(\my_empty_reg_n_0_[6] ), .S(SR)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[3]_i_1 (.I0(my_full0), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[3] ), .I4(\my_empty_reg_n_0_[6] ), .I5(SR), .O(\my_full[3]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[3]_i_2 (.I0(rd_ptr_timing[2]), .I1(\my_full[3]_i_3_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[3]_i_4_n_0 ), .I4(Q[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair939" *) LUT5 #( .INIT(32'h00000040)) \my_full[3]_i_3 (.I0(rd_ptr_timing[1]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(rd_ptr_timing[0]), .O(\my_full[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair939" *) LUT5 #( .INIT(32'h84210842)) \my_full[3]_i_4 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(\my_full[3]_i_4_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[3] (.C(CLK), .CE(1'b1), .D(\my_full[3]_i_1_n_0 ), .Q(\my_full_reg_n_0_[3] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair948" *) LUT2 #( .INIT(4'h2)) out_fifo_i_10__0 (.I0(mem_out[9]), .I1(\my_empty_reg[1]_0 ), .O(D1[4])); (* SOFT_HLUTNM = "soft_lutpair944" *) LUT2 #( .INIT(4'h2)) out_fifo_i_11__0 (.I0(mem_out[8]), .I1(\my_empty_reg[1]_0 ), .O(D1[3])); (* SOFT_HLUTNM = "soft_lutpair947" *) LUT2 #( .INIT(4'h2)) out_fifo_i_12__0 (.I0(mem_out[7]), .I1(\my_empty_reg[1]_0 ), .O(D1[2])); (* SOFT_HLUTNM = "soft_lutpair945" *) LUT2 #( .INIT(4'h2)) out_fifo_i_13__0 (.I0(mem_out[6]), .I1(\my_empty_reg[1]_0 ), .O(D1[1])); (* SOFT_HLUTNM = "soft_lutpair949" *) LUT2 #( .INIT(4'hE)) out_fifo_i_14 (.I0(mem_out[5]), .I1(\my_empty_reg[1]_0 ), .O(D1[0])); (* SOFT_HLUTNM = "soft_lutpair946" *) LUT2 #( .INIT(4'h2)) out_fifo_i_18__0 (.I0(mem_out[11]), .I1(\my_empty_reg[1]_0 ), .O(D2[1])); (* SOFT_HLUTNM = "soft_lutpair946" *) LUT2 #( .INIT(4'h2)) out_fifo_i_19__0 (.I0(mem_out[10]), .I1(\my_empty_reg[1]_0 ), .O(D2[0])); (* SOFT_HLUTNM = "soft_lutpair937" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1__0 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .O(\rd_ptr_timing_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair948" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__0 (.I0(mem_out[4]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair944" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__0 (.I0(mem_out[3]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair949" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__0 (.I0(mem_out[2]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair945" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__0 (.I0(mem_out[1]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair947" *) LUT2 #( .INIT(4'hE)) out_fifo_i_6__0 (.I0(mem_out[0]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); LUT2 #( .INIT(4'h1)) \rd_ptr[0]_i_1__1 (.I0(\my_empty_reg_n_0_[6] ), .I1(ofifo_rst_reg), .O(\rd_ptr[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair942" *) LUT2 #( .INIT(4'h9)) \rd_ptr[0]_i_2 (.I0(\rd_ptr_timing_reg[2]_3 ), .I1(\rd_ptr_timing_reg[2]_0 ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair942" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[1]_i_1 (.I0(\rd_ptr_timing_reg[2]_3 ), .I1(\rd_ptr_timing_reg[2]_0 ), .I2(\rd_ptr_timing_reg[2]_1 ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair941" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr[2]_i_1 (.I0(\rd_ptr_timing_reg[2]_2 ), .I1(\rd_ptr_timing_reg[2]_0 ), .I2(\rd_ptr_timing_reg[2]_1 ), .I3(\rd_ptr_timing_reg[2]_3 ), .O(nxt_rd_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair941" *) LUT4 #( .INIT(16'h4000)) \rd_ptr[3]_i_1 (.I0(\rd_ptr_timing_reg[2]_3 ), .I1(\rd_ptr_timing_reg[2]_1 ), .I2(\rd_ptr_timing_reg[2]_0 ), .I3(\rd_ptr_timing_reg[2]_2 ), .O(nxt_rd_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_timing_reg[2]_0 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_timing_reg[2]_1 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_timing_reg[2]_2 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_timing_reg[2]_3 ), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg_n_0_[6] ), .O(wr_ptr0__0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(Q[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(Q[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(Q[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(Q[3]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair943" *) LUT2 #( .INIT(4'h9)) \wr_ptr_timing[0]_i_1 (.I0(Q[3]), .I1(Q[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair943" *) LUT3 #( .INIT(8'hB4)) \wr_ptr_timing[1]_i_1 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair940" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr_timing[2]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair940" *) LUT4 #( .INIT(16'h4000)) \wr_ptr_timing[3]_i_1 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .O(nxt_wr_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized7 (\rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , wr_en_5, \my_empty_reg[1]_0 , \my_full_reg[3]_0 , D0, D3, D5, D6, D7, Q, SR, CLK, mux_cmd_wren, B_of_full, \rd_ptr_reg[3]_0 ); output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output wr_en_5; output \my_empty_reg[1]_0 ; output \my_full_reg[3]_0 ; output [5:0]D0; output [1:0]D3; output [1:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]Q; input [0:0]SR; input CLK; input mux_cmd_wren; input B_of_full; input [17:0]\rd_ptr_reg[3]_0 ; wire B_of_full; wire CLK; wire [5:0]D0; wire [1:0]D3; wire [1:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]Q; wire [0:0]SR; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1__4_n_0 ; wire \my_empty[6]_i_1_n_0 ; wire \my_empty[6]_i_3__0_n_0 ; wire \my_empty[6]_i_4__0_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg_n_0_[6] ; wire my_full0; wire \my_full[3]_i_1__0_n_0 ; wire \my_full[3]_i_3__0_n_0 ; wire \my_full[3]_i_4__0_n_0 ; wire \my_full_reg[3]_0 ; wire \my_full_reg_n_0_[3] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire \rd_ptr[3]_i_1__0_n_0 ; wire [17:0]\rd_ptr_reg[3]_0 ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire wr_en_5; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; (* SOFT_HLUTNM = "soft_lutpair952" *) LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[1]_i_1__4 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg[1]_0 ), .I3(B_of_full), .I4(mux_cmd_wren), .O(\my_empty[1]_i_1__4_n_0 )); LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[6]_i_1 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg_n_0_[6] ), .I3(B_of_full), .I4(mux_cmd_wren), .O(\my_empty[6]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[6]_i_2__0 (.I0(wr_ptr_timing[2]), .I1(\my_empty[6]_i_3__0_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[6]_i_4__0_n_0 ), .I4(\rd_ptr_timing_reg[2]_1 ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair951" *) LUT5 #( .INIT(32'h00000040)) \my_empty[6]_i_3__0 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .I4(wr_ptr_timing[0]), .O(\my_empty[6]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair951" *) LUT5 #( .INIT(32'h84210842)) \my_empty[6]_i_4__0 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_2 ), .I4(\rd_ptr_timing_reg[2]_0 ), .O(\my_empty[6]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDSE #( .INIT(1'b1)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__4_n_0 ), .Q(\my_empty_reg[1]_0 ), .S(SR)); (* syn_maxfan = "3" *) FDSE #( .INIT(1'b1)) \my_empty_reg[6] (.C(CLK), .CE(1'b1), .D(\my_empty[6]_i_1_n_0 ), .Q(\my_empty_reg_n_0_[6] ), .S(SR)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[3]_i_1__0 (.I0(my_full0), .I1(mux_cmd_wren), .I2(B_of_full), .I3(\my_full_reg_n_0_[3] ), .I4(\my_empty_reg_n_0_[6] ), .I5(SR), .O(\my_full[3]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[3]_i_2__0 (.I0(rd_ptr_timing[2]), .I1(\my_full[3]_i_3__0_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[3]_i_4__0_n_0 ), .I4(Q[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair950" *) LUT5 #( .INIT(32'h00000040)) \my_full[3]_i_3__0 (.I0(rd_ptr_timing[1]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(rd_ptr_timing[0]), .O(\my_full[3]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair950" *) LUT5 #( .INIT(32'h84210842)) \my_full[3]_i_4__0 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(\my_full[3]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[3] (.C(CLK), .CE(1'b1), .D(\my_full[3]_i_1__0_n_0 ), .Q(\my_full_reg_n_0_[3] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair958" *) LUT2 #( .INIT(4'h2)) out_fifo_i_17 (.I0(\rd_ptr_reg[3]_0 [9]), .I1(\my_empty_reg[1]_0 ), .O(D5[1])); (* SOFT_HLUTNM = "soft_lutpair964" *) LUT2 #( .INIT(4'h2)) out_fifo_i_18__1 (.I0(\rd_ptr_reg[3]_0 [8]), .I1(\my_empty_reg[1]_0 ), .O(D5[0])); (* SOFT_HLUTNM = "soft_lutpair952" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1__1 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(B_of_full), .O(\my_full_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair960" *) LUT2 #( .INIT(4'h2)) out_fifo_i_23 (.I0(\rd_ptr_reg[3]_0 [13]), .I1(\my_empty_reg[1]_0 ), .O(D6[3])); (* SOFT_HLUTNM = "soft_lutpair964" *) LUT2 #( .INIT(4'h2)) out_fifo_i_24__0 (.I0(\rd_ptr_reg[3]_0 [12]), .I1(\my_empty_reg[1]_0 ), .O(D6[2])); (* SOFT_HLUTNM = "soft_lutpair959" *) LUT2 #( .INIT(4'h2)) out_fifo_i_25 (.I0(\rd_ptr_reg[3]_0 [11]), .I1(\my_empty_reg[1]_0 ), .O(D6[1])); (* SOFT_HLUTNM = "soft_lutpair962" *) LUT2 #( .INIT(4'h2)) out_fifo_i_26__0 (.I0(\rd_ptr_reg[3]_0 [10]), .I1(\my_empty_reg[1]_0 ), .O(D6[0])); (* SOFT_HLUTNM = "soft_lutpair965" *) LUT2 #( .INIT(4'h2)) out_fifo_i_27__0 (.I0(\rd_ptr_reg[3]_0 [17]), .I1(\my_empty_reg[1]_0 ), .O(D7[3])); (* SOFT_HLUTNM = "soft_lutpair961" *) LUT2 #( .INIT(4'h2)) out_fifo_i_28__0 (.I0(\rd_ptr_reg[3]_0 [16]), .I1(\my_empty_reg[1]_0 ), .O(D7[2])); (* SOFT_HLUTNM = "soft_lutpair957" *) LUT2 #( .INIT(4'h2)) out_fifo_i_29__0 (.I0(\rd_ptr_reg[3]_0 [15]), .I1(\my_empty_reg[1]_0 ), .O(D7[1])); (* SOFT_HLUTNM = "soft_lutpair961" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__1 (.I0(\rd_ptr_reg[3]_0 [1]), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair965" *) LUT2 #( .INIT(4'h2)) out_fifo_i_30 (.I0(\rd_ptr_reg[3]_0 [14]), .I1(\my_empty_reg[1]_0 ), .O(D7[0])); (* SOFT_HLUTNM = "soft_lutpair958" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__1 (.I0(\rd_ptr_reg[3]_0 [0]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair962" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__1 (.I0(\rd_ptr_reg[3]_0 [5]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair959" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__1 (.I0(\rd_ptr_reg[3]_0 [4]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair960" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__1 (.I0(\rd_ptr_reg[3]_0 [3]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair957" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__0 (.I0(\rd_ptr_reg[3]_0 [2]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair963" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__0 (.I0(\rd_ptr_reg[3]_0 [7]), .I1(\my_empty_reg[1]_0 ), .O(D3[1])); (* SOFT_HLUTNM = "soft_lutpair963" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__0 (.I0(\rd_ptr_reg[3]_0 [6]), .I1(\my_empty_reg[1]_0 ), .O(D3[0])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(B_of_full), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en_5)); (* SOFT_HLUTNM = "soft_lutpair955" *) LUT2 #( .INIT(4'h9)) \rd_ptr[0]_i_1 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair955" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[1]_i_1__0 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair953" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr[2]_i_1__0 (.I0(\rd_ptr_timing_reg[2]_1 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr[3]_i_1__0 (.I0(\my_empty_reg_n_0_[6] ), .I1(B_of_full), .O(\rd_ptr[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair953" *) LUT4 #( .INIT(16'h4000)) \rd_ptr[3]_i_2 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_2 ), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_1 ), .O(nxt_rd_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_timing_reg[2]_3 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_timing_reg[2]_2 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_timing_reg[2]_1 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_timing_reg[2]_0 ), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(B_of_full), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg_n_0_[6] ), .O(wr_ptr0__0)); (* SOFT_HLUTNM = "soft_lutpair956" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__0 (.I0(Q[3]), .I1(Q[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair956" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__0 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair954" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair954" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_1__0 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(Q[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(Q[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(Q[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(Q[3]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized8 (\rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , wr_en_6, \my_empty_reg[1]_0 , D2, D3, \rd_ptr_timing_reg[0]_0 , D0, D1, D4, D7, D8, D9, Q, SR, CLK, mux_cmd_wren, ofifo_rst_reg, \rd_ptr_reg[3]_0 ); output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output wr_en_6; output \my_empty_reg[1]_0 ; output [4:0]D2; output [4:0]D3; output \rd_ptr_timing_reg[0]_0 ; output [5:0]D0; output [3:0]D1; output [3:0]D4; output [3:0]D7; output [3:0]D8; output [1:0]D9; output [3:0]Q; input [0:0]SR; input CLK; input mux_cmd_wren; input ofifo_rst_reg; input [33:0]\rd_ptr_reg[3]_0 ; wire CLK; wire [5:0]D0; wire [3:0]D1; wire [4:0]D2; wire [4:0]D3; wire [3:0]D4; wire [3:0]D7; wire [3:0]D8; wire [1:0]D9; wire [3:0]Q; wire [0:0]SR; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1__5_n_0 ; wire \my_empty[6]_i_1__0_n_0 ; wire \my_empty[6]_i_3__1_n_0 ; wire \my_empty[6]_i_4__1_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg_n_0_[6] ; wire my_full0; wire \my_full[3]_i_1__1_n_0 ; wire \my_full[3]_i_3__1_n_0 ; wire \my_full[3]_i_4__1_n_0 ; wire \my_full_reg_n_0_[3] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst_reg; wire \rd_ptr[3]_i_1__1_n_0 ; wire [33:0]\rd_ptr_reg[3]_0 ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire wr_en_6; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; (* SOFT_HLUTNM = "soft_lutpair968" *) LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[1]_i_1__5 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg[1]_0 ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[1]_i_1__5_n_0 )); LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[6]_i_1__0 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg_n_0_[6] ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[6]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[6]_i_2__1 (.I0(wr_ptr_timing[2]), .I1(\my_empty[6]_i_3__1_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[6]_i_4__1_n_0 ), .I4(\rd_ptr_timing_reg[2]_1 ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair966" *) LUT5 #( .INIT(32'h00000040)) \my_empty[6]_i_3__1 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .I4(wr_ptr_timing[0]), .O(\my_empty[6]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair966" *) LUT5 #( .INIT(32'h84210842)) \my_empty[6]_i_4__1 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_2 ), .I4(\rd_ptr_timing_reg[2]_0 ), .O(\my_empty[6]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDSE #( .INIT(1'b1)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__5_n_0 ), .Q(\my_empty_reg[1]_0 ), .S(SR)); (* syn_maxfan = "3" *) FDSE #( .INIT(1'b1)) \my_empty_reg[6] (.C(CLK), .CE(1'b1), .D(\my_empty[6]_i_1__0_n_0 ), .Q(\my_empty_reg_n_0_[6] ), .S(SR)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[3]_i_1__1 (.I0(my_full0), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[3] ), .I4(\my_empty_reg_n_0_[6] ), .I5(SR), .O(\my_full[3]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[3]_i_2__1 (.I0(rd_ptr_timing[2]), .I1(\my_full[3]_i_3__1_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[3]_i_4__1_n_0 ), .I4(Q[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair967" *) LUT5 #( .INIT(32'h00000040)) \my_full[3]_i_3__1 (.I0(rd_ptr_timing[1]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(rd_ptr_timing[0]), .O(\my_full[3]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair967" *) LUT5 #( .INIT(32'h84210842)) \my_full[3]_i_4__1 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(\my_full[3]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[3] (.C(CLK), .CE(1'b1), .D(\my_full[3]_i_1__1_n_0 ), .Q(\my_full_reg_n_0_[3] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair982" *) LUT2 #( .INIT(4'h2)) out_fifo_i_10__1 (.I0(\rd_ptr_reg[3]_0 [7]), .I1(\my_empty_reg[1]_0 ), .O(D1[1])); (* SOFT_HLUTNM = "soft_lutpair976" *) LUT2 #( .INIT(4'h2)) out_fifo_i_11__1 (.I0(\rd_ptr_reg[3]_0 [6]), .I1(\my_empty_reg[1]_0 ), .O(D1[0])); (* SOFT_HLUTNM = "soft_lutpair983" *) LUT2 #( .INIT(4'h2)) out_fifo_i_12__1 (.I0(\rd_ptr_reg[3]_0 [14]), .I1(\my_empty_reg[1]_0 ), .O(D2[4])); (* SOFT_HLUTNM = "soft_lutpair979" *) LUT2 #( .INIT(4'h2)) out_fifo_i_13__1 (.I0(\rd_ptr_reg[3]_0 [13]), .I1(\my_empty_reg[1]_0 ), .O(D2[3])); (* SOFT_HLUTNM = "soft_lutpair976" *) LUT2 #( .INIT(4'h2)) out_fifo_i_14__0 (.I0(\rd_ptr_reg[3]_0 [12]), .I1(\my_empty_reg[1]_0 ), .O(D2[2])); (* SOFT_HLUTNM = "soft_lutpair978" *) LUT2 #( .INIT(4'h2)) out_fifo_i_15 (.I0(\rd_ptr_reg[3]_0 [11]), .I1(\my_empty_reg[1]_0 ), .O(D2[1])); (* SOFT_HLUTNM = "soft_lutpair975" *) LUT2 #( .INIT(4'hE)) out_fifo_i_16 (.I0(\rd_ptr_reg[3]_0 [10]), .I1(\my_empty_reg[1]_0 ), .O(D2[0])); (* SOFT_HLUTNM = "soft_lutpair968" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1__2 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .O(\rd_ptr_timing_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair986" *) LUT2 #( .INIT(4'h2)) out_fifo_i_20__0 (.I0(\rd_ptr_reg[3]_0 [19]), .I1(\my_empty_reg[1]_0 ), .O(D3[4])); (* SOFT_HLUTNM = "soft_lutpair979" *) LUT2 #( .INIT(4'h2)) out_fifo_i_21__0 (.I0(\rd_ptr_reg[3]_0 [18]), .I1(\my_empty_reg[1]_0 ), .O(D3[3])); (* SOFT_HLUTNM = "soft_lutpair987" *) LUT2 #( .INIT(4'h2)) out_fifo_i_22 (.I0(\rd_ptr_reg[3]_0 [17]), .I1(\my_empty_reg[1]_0 ), .O(D3[2])); (* SOFT_HLUTNM = "soft_lutpair978" *) LUT2 #( .INIT(4'h2)) out_fifo_i_23__0 (.I0(\rd_ptr_reg[3]_0 [16]), .I1(\my_empty_reg[1]_0 ), .O(D3[1])); (* SOFT_HLUTNM = "soft_lutpair985" *) LUT2 #( .INIT(4'hE)) out_fifo_i_24 (.I0(\rd_ptr_reg[3]_0 [15]), .I1(\my_empty_reg[1]_0 ), .O(D3[0])); (* SOFT_HLUTNM = "soft_lutpair988" *) LUT2 #( .INIT(4'h2)) out_fifo_i_28__1 (.I0(\rd_ptr_reg[3]_0 [23]), .I1(\my_empty_reg[1]_0 ), .O(D4[3])); (* SOFT_HLUTNM = "soft_lutpair973" *) LUT2 #( .INIT(4'h2)) out_fifo_i_29__1 (.I0(\rd_ptr_reg[3]_0 [22]), .I1(\my_empty_reg[1]_0 ), .O(D4[2])); (* SOFT_HLUTNM = "soft_lutpair980" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__2 (.I0(\rd_ptr_reg[3]_0 [1]), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair989" *) LUT2 #( .INIT(4'h2)) out_fifo_i_30__0 (.I0(\rd_ptr_reg[3]_0 [21]), .I1(\my_empty_reg[1]_0 ), .O(D4[1])); (* SOFT_HLUTNM = "soft_lutpair983" *) LUT2 #( .INIT(4'h2)) out_fifo_i_31 (.I0(\rd_ptr_reg[3]_0 [20]), .I1(\my_empty_reg[1]_0 ), .O(D4[0])); (* SOFT_HLUTNM = "soft_lutpair975" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__2 (.I0(\rd_ptr_reg[3]_0 [0]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair982" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__2 (.I0(\rd_ptr_reg[3]_0 [5]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair988" *) LUT2 #( .INIT(4'h2)) out_fifo_i_52__0 (.I0(\rd_ptr_reg[3]_0 [27]), .I1(\my_empty_reg[1]_0 ), .O(D7[3])); (* SOFT_HLUTNM = "soft_lutpair977" *) LUT2 #( .INIT(4'h2)) out_fifo_i_53__0 (.I0(\rd_ptr_reg[3]_0 [26]), .I1(\my_empty_reg[1]_0 ), .O(D7[2])); (* SOFT_HLUTNM = "soft_lutpair985" *) LUT2 #( .INIT(4'h2)) out_fifo_i_54 (.I0(\rd_ptr_reg[3]_0 [25]), .I1(\my_empty_reg[1]_0 ), .O(D7[1])); (* SOFT_HLUTNM = "soft_lutpair981" *) LUT2 #( .INIT(4'h2)) out_fifo_i_55 (.I0(\rd_ptr_reg[3]_0 [24]), .I1(\my_empty_reg[1]_0 ), .O(D7[0])); (* SOFT_HLUTNM = "soft_lutpair977" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__2 (.I0(\rd_ptr_reg[3]_0 [4]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair986" *) LUT2 #( .INIT(4'h2)) out_fifo_i_60__0 (.I0(\rd_ptr_reg[3]_0 [31]), .I1(\my_empty_reg[1]_0 ), .O(D8[3])); (* SOFT_HLUTNM = "soft_lutpair984" *) LUT2 #( .INIT(4'h2)) out_fifo_i_61__0 (.I0(\rd_ptr_reg[3]_0 [30]), .I1(\my_empty_reg[1]_0 ), .O(D8[2])); (* SOFT_HLUTNM = "soft_lutpair989" *) LUT2 #( .INIT(4'h2)) out_fifo_i_62 (.I0(\rd_ptr_reg[3]_0 [29]), .I1(\my_empty_reg[1]_0 ), .O(D8[1])); (* SOFT_HLUTNM = "soft_lutpair974" *) LUT2 #( .INIT(4'h2)) out_fifo_i_63 (.I0(\rd_ptr_reg[3]_0 [28]), .I1(\my_empty_reg[1]_0 ), .O(D8[0])); (* SOFT_HLUTNM = "soft_lutpair987" *) LUT2 #( .INIT(4'h2)) out_fifo_i_68__0 (.I0(\rd_ptr_reg[3]_0 [33]), .I1(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair984" *) LUT2 #( .INIT(4'h2)) out_fifo_i_69__0 (.I0(\rd_ptr_reg[3]_0 [32]), .I1(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair980" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__2 (.I0(\rd_ptr_reg[3]_0 [3]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair973" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__1 (.I0(\rd_ptr_reg[3]_0 [2]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair981" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__1 (.I0(\rd_ptr_reg[3]_0 [9]), .I1(\my_empty_reg[1]_0 ), .O(D1[3])); (* SOFT_HLUTNM = "soft_lutpair974" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__1 (.I0(\rd_ptr_reg[3]_0 [8]), .I1(\my_empty_reg[1]_0 ), .O(D1[2])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en_6)); (* SOFT_HLUTNM = "soft_lutpair972" *) LUT2 #( .INIT(4'h9)) \rd_ptr[0]_i_1__0 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair972" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[1]_i_1__1 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair969" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr[2]_i_1__1 (.I0(\rd_ptr_timing_reg[2]_1 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr[3]_i_1__1 (.I0(\my_empty_reg_n_0_[6] ), .I1(ofifo_rst_reg), .O(\rd_ptr[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair969" *) LUT4 #( .INIT(16'h4000)) \rd_ptr[3]_i_2__0 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_2 ), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_1 ), .O(nxt_rd_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_timing_reg[2]_3 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_timing_reg[2]_2 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_timing_reg[2]_1 ), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_timing_reg[2]_0 ), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg_n_0_[6] ), .O(wr_ptr0__0)); (* SOFT_HLUTNM = "soft_lutpair971" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__1 (.I0(Q[3]), .I1(Q[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair971" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__1 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair970" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair970" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_1__1 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(Q[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(Q[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(Q[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(Q[3]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized9 (D9, \my_empty_reg[1]_0 , \my_empty_reg[7]_0 , D0, D1, D2, D3, D4, D5, D6, D7, D8, \my_empty_reg[7]_1 , SR, CLK, init_calib_complete_reg_rep__5, mc_cas_n, mc_address, init_calib_complete_reg_rep, mux_cmd_wren, ofifo_rst_reg, phy_dout, init_calib_complete_reg_rep__6); output [7:0]D9; output \my_empty_reg[1]_0 ; output \my_empty_reg[7]_0 ; output [5:0]D0; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [31:0]\my_empty_reg[7]_1 ; input [0:0]SR; input CLK; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]mc_address; input init_calib_complete_reg_rep; input mux_cmd_wren; input ofifo_rst_reg; input [35:0]phy_dout; input init_calib_complete_reg_rep__6; wire CLK; wire [5:0]D0; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [7:0]D9; wire [0:0]SR; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire init_calib_complete_reg_rep__6; wire [1:0]mc_address; wire [0:0]mc_cas_n; wire [77:0]mem_out; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1_n_0 ; wire \my_empty[7]_i_1_n_0 ; wire \my_empty[7]_i_3_n_0 ; wire \my_empty[7]_i_4_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [31:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1_n_0 ; wire \my_full[4]_i_3_n_0 ; wire \my_full[4]_i_4_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst_reg; wire [35:0]phy_dout; wire [3:0]rd_ptr; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1000" *) LUT3 #( .INIT(8'hAC)) d_out (.I0(init_calib_complete_reg_rep__6), .I1(mem_out[75]), .I2(\my_empty_reg[1]_0 ), .O(D9[3])); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_0_5 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(mem_out[1:0]), .DOB(mem_out[3:2]), .DOC(mem_out[5:4]), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_12_17 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(phy_dout[5:4]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(\my_empty_reg[7]_1 [5:4]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_18_23 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[7:6]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [7:6]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_24_29 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[9:8]), .DIB(phy_dout[11:10]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [9:8]), .DOB(\my_empty_reg[7]_1 [11:10]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_30_35 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_36_41 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(phy_dout[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(\my_empty_reg[7]_1 [17:16]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_42_47 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[19:18]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [19:18]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_48_53 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[21:20]), .DIB(phy_dout[23:22]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [21:20]), .DOB(\my_empty_reg[7]_1 [23:22]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_54_59 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_60_65 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(phy_dout[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(\my_empty_reg[7]_1 [29:28]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_66_71 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[31:30]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [31:30]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_6_11 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA(mem_out[7:6]), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000)) mem_reg_0_15_72_77 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[33:32]), .DIB(phy_dout[35:34]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(mem_out[73:72]), .DOB(mem_out[75:74]), .DOC(mem_out[77:76]), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(SR), .O(\my_empty[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(SR), .O(\my_empty[7]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4_n_0 ), .I4(rd_ptr[2]), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair990" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3 (.I0(wr_ptr_timing[1]), .I1(rd_ptr[0]), .I2(rd_ptr[1]), .I3(rd_ptr[3]), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair990" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(rd_ptr[0]), .I3(rd_ptr[1]), .I4(rd_ptr[3]), .O(\my_empty[7]_i_4_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1 (.I0(my_full0), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(SR), .O(\my_full[4]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair991" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair991" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4_n_0 )); (* syn_maxfan = "3" *) FDRE #( .INIT(1'b0)) \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair998" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair1006" *) LUT2 #( .INIT(4'h2)) out_fifo_i_10 (.I0(mem_out[15]), .I1(\my_empty_reg[1]_0 ), .O(D1[3])); (* SOFT_HLUTNM = "soft_lutpair995" *) LUT2 #( .INIT(4'h2)) out_fifo_i_11 (.I0(mem_out[14]), .I1(\my_empty_reg[1]_0 ), .O(D1[2])); (* SOFT_HLUTNM = "soft_lutpair1009" *) LUT2 #( .INIT(4'h2)) out_fifo_i_12 (.I0(mem_out[13]), .I1(\my_empty_reg[1]_0 ), .O(D1[1])); (* SOFT_HLUTNM = "soft_lutpair1000" *) LUT2 #( .INIT(4'h2)) out_fifo_i_13 (.I0(mem_out[12]), .I1(\my_empty_reg[1]_0 ), .O(D1[0])); (* SOFT_HLUTNM = "soft_lutpair1010" *) LUT2 #( .INIT(4'h2)) out_fifo_i_18 (.I0(mem_out[23]), .I1(\my_empty_reg[1]_0 ), .O(D2[3])); (* SOFT_HLUTNM = "soft_lutpair1003" *) LUT2 #( .INIT(4'h2)) out_fifo_i_19 (.I0(mem_out[22]), .I1(\my_empty_reg[1]_0 ), .O(D2[2])); (* SOFT_HLUTNM = "soft_lutpair1007" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2 (.I0(mem_out[7]), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair1010" *) LUT2 #( .INIT(4'h2)) out_fifo_i_20 (.I0(mem_out[21]), .I1(\my_empty_reg[1]_0 ), .O(D2[1])); (* SOFT_HLUTNM = "soft_lutpair1002" *) LUT2 #( .INIT(4'h2)) out_fifo_i_21 (.I0(mem_out[20]), .I1(\my_empty_reg[1]_0 ), .O(D2[0])); (* SOFT_HLUTNM = "soft_lutpair1015" *) LUT2 #( .INIT(4'h2)) out_fifo_i_26 (.I0(mem_out[31]), .I1(\my_empty_reg[1]_0 ), .O(D3[3])); (* SOFT_HLUTNM = "soft_lutpair1003" *) LUT2 #( .INIT(4'h2)) out_fifo_i_27 (.I0(mem_out[30]), .I1(\my_empty_reg[1]_0 ), .O(D3[2])); (* SOFT_HLUTNM = "soft_lutpair1016" *) LUT2 #( .INIT(4'h2)) out_fifo_i_28 (.I0(mem_out[29]), .I1(\my_empty_reg[1]_0 ), .O(D3[1])); (* SOFT_HLUTNM = "soft_lutpair1005" *) LUT2 #( .INIT(4'h2)) out_fifo_i_29 (.I0(mem_out[28]), .I1(\my_empty_reg[1]_0 ), .O(D3[0])); (* SOFT_HLUTNM = "soft_lutpair996" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3 (.I0(mem_out[6]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair1018" *) LUT2 #( .INIT(4'h2)) out_fifo_i_34 (.I0(mem_out[39]), .I1(\my_empty_reg[1]_0 ), .O(D4[3])); (* SOFT_HLUTNM = "soft_lutpair1004" *) LUT2 #( .INIT(4'h2)) out_fifo_i_35 (.I0(mem_out[38]), .I1(\my_empty_reg[1]_0 ), .O(D4[2])); LUT2 #( .INIT(4'h2)) out_fifo_i_36 (.I0(mem_out[37]), .I1(\my_empty_reg[1]_0 ), .O(D4[1])); (* SOFT_HLUTNM = "soft_lutpair1008" *) LUT2 #( .INIT(4'h2)) out_fifo_i_37 (.I0(mem_out[36]), .I1(\my_empty_reg[1]_0 ), .O(D4[0])); (* SOFT_HLUTNM = "soft_lutpair1008" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4 (.I0(mem_out[5]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair1017" *) LUT2 #( .INIT(4'h2)) out_fifo_i_42 (.I0(mem_out[47]), .I1(\my_empty_reg[1]_0 ), .O(D5[3])); (* SOFT_HLUTNM = "soft_lutpair1006" *) LUT2 #( .INIT(4'h2)) out_fifo_i_43 (.I0(mem_out[46]), .I1(\my_empty_reg[1]_0 ), .O(D5[2])); (* SOFT_HLUTNM = "soft_lutpair1014" *) LUT2 #( .INIT(4'h2)) out_fifo_i_44 (.I0(mem_out[45]), .I1(\my_empty_reg[1]_0 ), .O(D5[1])); (* SOFT_HLUTNM = "soft_lutpair1004" *) LUT2 #( .INIT(4'h2)) out_fifo_i_45 (.I0(mem_out[44]), .I1(\my_empty_reg[1]_0 ), .O(D5[0])); (* SOFT_HLUTNM = "soft_lutpair1001" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5 (.I0(mem_out[4]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair1014" *) LUT2 #( .INIT(4'h2)) out_fifo_i_50 (.I0(mem_out[55]), .I1(\my_empty_reg[1]_0 ), .O(D6[3])); (* SOFT_HLUTNM = "soft_lutpair1011" *) LUT2 #( .INIT(4'h2)) out_fifo_i_51 (.I0(mem_out[54]), .I1(\my_empty_reg[1]_0 ), .O(D6[2])); (* SOFT_HLUTNM = "soft_lutpair1015" *) LUT2 #( .INIT(4'h2)) out_fifo_i_52 (.I0(mem_out[53]), .I1(\my_empty_reg[1]_0 ), .O(D6[1])); (* SOFT_HLUTNM = "soft_lutpair1011" *) LUT2 #( .INIT(4'h2)) out_fifo_i_53 (.I0(mem_out[52]), .I1(\my_empty_reg[1]_0 ), .O(D6[0])); (* SOFT_HLUTNM = "soft_lutpair1012" *) LUT2 #( .INIT(4'h2)) out_fifo_i_58 (.I0(mem_out[63]), .I1(\my_empty_reg[1]_0 ), .O(D7[3])); (* SOFT_HLUTNM = "soft_lutpair1002" *) LUT2 #( .INIT(4'h2)) out_fifo_i_59 (.I0(mem_out[62]), .I1(\my_empty_reg[1]_0 ), .O(D7[2])); (* SOFT_HLUTNM = "soft_lutpair1005" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6 (.I0(mem_out[3]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair1016" *) LUT2 #( .INIT(4'h2)) out_fifo_i_60 (.I0(mem_out[61]), .I1(\my_empty_reg[1]_0 ), .O(D7[1])); (* SOFT_HLUTNM = "soft_lutpair1007" *) LUT2 #( .INIT(4'h2)) out_fifo_i_61 (.I0(mem_out[60]), .I1(\my_empty_reg[1]_0 ), .O(D7[0])); (* SOFT_HLUTNM = "soft_lutpair1017" *) LUT2 #( .INIT(4'h2)) out_fifo_i_66 (.I0(mem_out[71]), .I1(\my_empty_reg[1]_0 ), .O(D8[3])); (* SOFT_HLUTNM = "soft_lutpair1012" *) LUT2 #( .INIT(4'h2)) out_fifo_i_67 (.I0(mem_out[70]), .I1(\my_empty_reg[1]_0 ), .O(D8[2])); (* SOFT_HLUTNM = "soft_lutpair1013" *) LUT2 #( .INIT(4'h2)) out_fifo_i_68 (.I0(mem_out[69]), .I1(\my_empty_reg[1]_0 ), .O(D8[1])); (* SOFT_HLUTNM = "soft_lutpair1001" *) LUT2 #( .INIT(4'h2)) out_fifo_i_69 (.I0(mem_out[68]), .I1(\my_empty_reg[1]_0 ), .O(D8[0])); (* SOFT_HLUTNM = "soft_lutpair994" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7 (.I0(mem_out[2]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair1018" *) LUT2 #( .INIT(4'h2)) out_fifo_i_74 (.I0(mem_out[77]), .I1(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair1013" *) LUT2 #( .INIT(4'h2)) out_fifo_i_75 (.I0(mem_out[76]), .I1(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair996" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76 (.I0(mc_address[1]), .I1(init_calib_complete_reg_rep), .I2(mem_out[74]), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair995" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77 (.I0(init_calib_complete_reg_rep__5), .I1(mc_cas_n), .I2(mem_out[73]), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair994" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78 (.I0(mc_address[0]), .I1(init_calib_complete_reg_rep), .I2(mem_out[72]), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair1009" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8 (.I0(mem_out[1]), .I1(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair998" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9 (.I0(mem_out[0]), .I1(\my_empty_reg[1]_0 ), .O(D9[6])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr[3]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair999" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1 (.I0(rd_ptr[3]), .I1(rd_ptr[0]), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair999" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1 (.I0(rd_ptr[3]), .I1(rd_ptr[0]), .I2(rd_ptr[1]), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair993" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1 (.I0(rd_ptr[2]), .I1(rd_ptr[0]), .I2(rd_ptr[1]), .I3(rd_ptr[3]), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair993" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2 (.I0(rd_ptr[3]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(rd_ptr[2]), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0__0)); (* SOFT_HLUTNM = "soft_lutpair997" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair997" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair992" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair992" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_1 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_4lanes" *) module ddr3_ifmig_7series_v4_0_ddr_phy_4lanes (\pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, idelay_ld_rst, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , idelay_ld_rst_0, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , idelay_ld_rst_1, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , idelay_ld_rst_2, _phy_ctl_full_p__0, rst_primitives_reg_0, rst_primitives, mcGo_reg_0, rclk_delay_11, \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[228] , \my_empty_reg[1] , \my_empty_reg[1]_0 , \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , phy_rddata_en, mux_rd_valid_r_reg, rst_sync_r1_reg, \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \read_fifo.tail_r_reg[0] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , pi_phase_locked_all_r1_reg, \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7] , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7]_1 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7]_2 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \po_rdval_cnt_reg[8] , \pi_rdval_cnt_reg[5] , phy_if_empty_r_reg, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0, CLKB0, phy_if_reset, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[0]_0 , pi_en_stg2_f_reg_0, pi_stg2_f_incdec_reg_0, \gen_byte_sel_div1.calib_in_common_reg_4 , \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_5 , ck_po_stg2_f_en_reg_0, ck_po_stg2_f_indec_reg_0, delay_done_r4_reg_0, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_6 , LD0_3, CLKB0_7, \gen_byte_sel_div1.calib_in_common_reg_7 , \calib_sel_reg[1] , pi_en_stg2_f_reg_1, pi_stg2_f_incdec_reg_1, \gen_byte_sel_div1.calib_in_common_reg_8 , \calib_zero_inputs_reg[0]_0 , \gen_byte_sel_div1.calib_in_common_reg_9 , ck_po_stg2_f_en_reg_1, ck_po_stg2_f_indec_reg_1, delay_done_r4_reg_1, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_10 , LD0_4, CLKB0_8, \gen_byte_sel_div1.calib_in_common_reg_11 , \calib_sel_reg[0]_1 , pi_en_stg2_f_reg_2, pi_stg2_f_incdec_reg_2, \gen_byte_sel_div1.calib_in_common_reg_12 , \calib_zero_inputs_reg[0]_1 , \gen_byte_sel_div1.calib_in_common_reg_13 , ck_po_stg2_f_en_reg_2, ck_po_stg2_f_indec_reg_2, delay_done_r4_reg_2, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_14 , LD0_5, CLKB0_9, phy_ctl_mstr_empty, phy_ctl_wr_i2, pll_locked, phy_read_calib, in0, phy_write_calib, Q, RST0, phy_ctl_wr_i2_reg, \rclk_delay_reg[11]_0 , rstdiv0_sync_r1_reg_rep__9, rst_primitives_reg_1, mux_wrdata_en, mcGo_w__0, \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , prbs_rdlvl_start_reg, out, ref_dll_lock_w, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, \byte_r_reg[0] , \byte_r_reg[1] , tail_r, \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , A, mux_wrdata, mux_wrdata_mask, E, \fine_delay_mod_reg[23] , \gen_byte_sel_div1.calib_in_common_reg_15 , \calib_sel_reg[0]_2 , \gen_byte_sel_div1.calib_in_common_reg_16 , \calib_sel_reg[1]_0 , \gen_byte_sel_div1.calib_in_common_reg_17 , \calib_sel_reg[0]_3 , \calib_sel_reg[1]_1 , \po_stg2_wrcal_cnt_reg[1] ); output [3:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output [3:0]mem_dqs_out; output [3:0]mem_dqs_ts; output [35:0]mem_dq_out; output [35:0]mem_dq_ts; output idelay_ld_rst; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output idelay_ld_rst_0; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output idelay_ld_rst_1; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output idelay_ld_rst_2; output [0:0]_phy_ctl_full_p__0; output rst_primitives_reg_0; output rst_primitives; output mcGo_reg_0; output rclk_delay_11; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[228] ; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output phy_rddata_en; output mux_rd_valid_r_reg; output rst_sync_r1_reg; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \read_fifo.tail_r_reg[0] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output pi_phase_locked_all_r1_reg; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7] ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7]_2 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [8:0]\po_rdval_cnt_reg[8] ; output [5:0]\pi_rdval_cnt_reg[5] ; output phy_if_empty_r_reg; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [3:0]mem_dqs_in; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [31:0]mem_dq_in; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input \calib_sel_reg[0]_0 ; input pi_en_stg2_f_reg_0; input pi_stg2_f_incdec_reg_0; input \gen_byte_sel_div1.calib_in_common_reg_4 ; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_5 ; input ck_po_stg2_f_en_reg_0; input ck_po_stg2_f_indec_reg_0; input delay_done_r4_reg_0; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_6 ; input LD0_3; input CLKB0_7; input \gen_byte_sel_div1.calib_in_common_reg_7 ; input \calib_sel_reg[1] ; input pi_en_stg2_f_reg_1; input pi_stg2_f_incdec_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_8 ; input [5:0]\calib_zero_inputs_reg[0]_0 ; input \gen_byte_sel_div1.calib_in_common_reg_9 ; input ck_po_stg2_f_en_reg_1; input ck_po_stg2_f_indec_reg_1; input delay_done_r4_reg_1; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_10 ; input LD0_4; input CLKB0_8; input \gen_byte_sel_div1.calib_in_common_reg_11 ; input \calib_sel_reg[0]_1 ; input pi_en_stg2_f_reg_2; input pi_stg2_f_incdec_reg_2; input \gen_byte_sel_div1.calib_in_common_reg_12 ; input [5:0]\calib_zero_inputs_reg[0]_1 ; input \gen_byte_sel_div1.calib_in_common_reg_13 ; input ck_po_stg2_f_en_reg_2; input ck_po_stg2_f_indec_reg_2; input delay_done_r4_reg_2; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_14 ; input LD0_5; input CLKB0_9; input phy_ctl_mstr_empty; input phy_ctl_wr_i2; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input [10:0]Q; input RST0; input phy_ctl_wr_i2_reg; input \rclk_delay_reg[11]_0 ; input rstdiv0_sync_r1_reg_rep__9; input rst_primitives_reg_1; input mux_wrdata_en; input [0:0]mcGo_w__0; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input init_calib_complete_reg_rep; input [31:0]\write_buffer.wr_buf_out_data_reg[287] ; input prbs_rdlvl_start_reg; input out; input [0:0]ref_dll_lock_w; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input \byte_r_reg[0] ; input \byte_r_reg[1] ; input [0:0]tail_r; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input [1:0]A; input [255:0]mux_wrdata; input [31:0]mux_wrdata_mask; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_15 ; input [7:0]\calib_sel_reg[0]_2 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_16 ; input [7:0]\calib_sel_reg[1]_0 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_17 ; input [7:0]\calib_sel_reg[0]_3 ; input [1:0]\calib_sel_reg[1]_1 ; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]A; wire A_byte_rd_en; wire [5:0]A_pi_counter_read_val; (* async_reg = "true" *) wire A_pi_rst_div2; wire [8:0]A_po_counter_read_val; wire A_rst_primitives; wire B_byte_rd_en; wire [5:0]B_pi_counter_read_val; (* async_reg = "true" *) wire B_pi_rst_div2; wire [8:0]B_po_counter_read_val; wire B_rclk; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [5:0]COUNTERLOADVAL; wire C_byte_rd_en; wire [5:0]C_pi_counter_read_val; (* async_reg = "true" *) wire C_pi_rst_div2; wire [8:0]C_po_counter_read_val; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_byte_rd_en; (* async_reg = "true" *) wire D_pi_rst_div2; wire [0:0]E; wire LD0; wire LD0_3; wire LD0_4; wire LD0_5; wire [10:0]Q; wire RST0; wire [0:0]_phy_ctl_full_p__0; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire [7:0]\calib_sel_reg[0]_2 ; wire [7:0]\calib_sel_reg[0]_3 ; wire \calib_sel_reg[1] ; wire [7:0]\calib_sel_reg[1]_0 ; wire [1:0]\calib_sel_reg[1]_1 ; wire [5:0]\calib_zero_inputs_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0]_1 ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_en_reg_0; wire ck_po_stg2_f_en_reg_1; wire ck_po_stg2_f_en_reg_2; wire ck_po_stg2_f_indec_reg; wire ck_po_stg2_f_indec_reg_0; wire ck_po_stg2_f_indec_reg_1; wire ck_po_stg2_f_indec_reg_2; wire [63:0]\data_bytes_r_reg[63] ; wire \ddr_byte_lane_A.ddr_byte_lane_A_n_2 ; wire \ddr_byte_lane_C.ddr_byte_lane_C_n_2 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_154 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_2 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_222 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_223 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_224 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_225 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_226 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_227 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_228 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_229 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_230 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_231 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_232 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_233 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_234 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_235 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_236 ; wire delay_done_r4_reg; wire delay_done_r4_reg_0; wire delay_done_r4_reg_1; wire delay_done_r4_reg_2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ; wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 ; wire [7:0]\fine_delay_mod_reg[23] ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_10 ; wire \gen_byte_sel_div1.calib_in_common_reg_11 ; wire \gen_byte_sel_div1.calib_in_common_reg_12 ; wire \gen_byte_sel_div1.calib_in_common_reg_13 ; wire \gen_byte_sel_div1.calib_in_common_reg_14 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_15 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_16 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_17 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.calib_in_common_reg_4 ; wire \gen_byte_sel_div1.calib_in_common_reg_5 ; wire \gen_byte_sel_div1.calib_in_common_reg_6 ; wire \gen_byte_sel_div1.calib_in_common_reg_7 ; wire \gen_byte_sel_div1.calib_in_common_reg_8 ; wire \gen_byte_sel_div1.calib_in_common_reg_9 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_0; wire idelay_ld_rst_1; wire idelay_ld_rst_2; wire [3:3]if_empty_r; wire [3:3]if_empty_r_2; wire [3:3]if_empty_r_5; wire in0; wire init_calib_complete_reg_rep; wire \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ; wire mcGo_reg_0; wire [0:0]mcGo_w; wire [0:0]mcGo_w__0; wire [31:0]mem_dq_in; wire [35:0]mem_dq_out; wire [35:0]mem_dq_ts; wire [3:0]mem_dqs_in; wire [3:0]mem_dqs_out; wire [3:0]mem_dqs_ts; wire mem_refclk; wire mmcm_locked; wire mux_rd_valid_r_reg; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire [63:0]\my_empty_reg[7] ; wire [63:0]\my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire [63:0]\my_empty_reg[7]_2 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire out; wire p_0_out; wire [15:0]phaser_ctl_bus; wire phy_control_i_n_0; wire phy_control_i_n_1; wire phy_control_i_n_14; wire phy_control_i_n_15; wire phy_control_i_n_16; wire phy_control_i_n_17; wire phy_ctl_mstr_empty; wire phy_ctl_wr_i2; wire phy_ctl_wr_i2_reg; wire [1:0]phy_encalib; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [3:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_en_stg2_f_reg_0; wire pi_en_stg2_f_reg_1; wire pi_en_stg2_f_reg_2; wire pi_phase_locked_all_r1_reg; wire [5:0]\pi_rdval_cnt_reg[5] ; wire pi_stg2_f_incdec_reg; wire pi_stg2_f_incdec_reg_0; wire pi_stg2_f_incdec_reg_1; wire pi_stg2_f_incdec_reg_2; wire pll_locked; wire [8:0]\po_rdval_cnt_reg[8] ; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rclk_delay_11; wire \rclk_delay_reg[10]_srl11_n_0 ; wire \rclk_delay_reg[11]_0 ; wire rd_buf_we; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]ref_dll_lock_w; wire [0:0]ref_dll_lock_w__0; wire rst_primitives; wire rst_primitives_reg_0; wire rst_primitives_reg_1; wire rst_r4; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; wire [31:0]\write_buffer.wr_buf_out_data_reg[287] ; FDRE #( .INIT(1'b0)) A_rst_primitives_reg (.C(CLK), .CE(1'b1), .D(rst_primitives), .Q(A_rst_primitives), .R(1'b0)); ddr3_ifmig_7series_v4_0_ddr_byte_lane \ddr_byte_lane_A.ddr_byte_lane_A (.A(A), .A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .B_byte_rd_en(B_byte_rd_en), .CLK(CLK), .CLKB0(CLKB0), .COUNTERLOADVAL(COUNTERLOADVAL), .COUNTERREADVAL(A_pi_counter_read_val), .D_byte_rd_en(D_byte_rd_en), .E(E), .LD0(LD0), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .delay_done_r4_reg(delay_done_r4_reg), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\not_strict_mode.app_rd_data_reg[79] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\not_strict_mode.app_rd_data_reg[87] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 (\not_strict_mode.app_rd_data_reg[71] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\not_strict_mode.app_rd_data_reg[111] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\not_strict_mode.app_rd_data_reg[119] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 (\not_strict_mode.app_rd_data_reg[103] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\not_strict_mode.app_rd_data_reg[143] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\not_strict_mode.app_rd_data_reg[151] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 (\not_strict_mode.app_rd_data_reg[135] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\not_strict_mode.app_rd_data_reg[175] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\not_strict_mode.app_rd_data_reg[183] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 (\not_strict_mode.app_rd_data_reg[167] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\not_strict_mode.app_rd_data_reg[207] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\not_strict_mode.app_rd_data_reg[215] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 (\not_strict_mode.app_rd_data_reg[199] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\not_strict_mode.app_rd_data_reg[239] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\not_strict_mode.app_rd_data_reg[247] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 (\not_strict_mode.app_rd_data_reg[231] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\not_strict_mode.app_rd_data_reg[14] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\not_strict_mode.app_rd_data_reg[22] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\not_strict_mode.app_rd_data_reg[6] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\not_strict_mode.app_rd_data_reg[46] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\not_strict_mode.app_rd_data_reg[54] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\not_strict_mode.app_rd_data_reg[38] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\not_strict_mode.app_rd_data_reg[78] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\not_strict_mode.app_rd_data_reg[86] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\not_strict_mode.app_rd_data_reg[70] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\not_strict_mode.app_rd_data_reg[110] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\not_strict_mode.app_rd_data_reg[118] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\not_strict_mode.app_rd_data_reg[102] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\not_strict_mode.app_rd_data_reg[142] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\not_strict_mode.app_rd_data_reg[150] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\not_strict_mode.app_rd_data_reg[134] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\not_strict_mode.app_rd_data_reg[174] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\not_strict_mode.app_rd_data_reg[182] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\not_strict_mode.app_rd_data_reg[166] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\not_strict_mode.app_rd_data_reg[206] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\not_strict_mode.app_rd_data_reg[214] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\not_strict_mode.app_rd_data_reg[198] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\not_strict_mode.app_rd_data_reg[238] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\not_strict_mode.app_rd_data_reg[246] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\not_strict_mode.app_rd_data_reg[230] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\not_strict_mode.app_rd_data_reg[13] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\not_strict_mode.app_rd_data_reg[21] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\not_strict_mode.app_rd_data_reg[5] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\not_strict_mode.app_rd_data_reg[45] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\not_strict_mode.app_rd_data_reg[53] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\not_strict_mode.app_rd_data_reg[37] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\not_strict_mode.app_rd_data_reg[77] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\not_strict_mode.app_rd_data_reg[85] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\not_strict_mode.app_rd_data_reg[69] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\not_strict_mode.app_rd_data_reg[109] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\not_strict_mode.app_rd_data_reg[117] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\not_strict_mode.app_rd_data_reg[101] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\not_strict_mode.app_rd_data_reg[141] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\not_strict_mode.app_rd_data_reg[149] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\not_strict_mode.app_rd_data_reg[133] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\not_strict_mode.app_rd_data_reg[173] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\not_strict_mode.app_rd_data_reg[181] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\not_strict_mode.app_rd_data_reg[165] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\not_strict_mode.app_rd_data_reg[205] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\not_strict_mode.app_rd_data_reg[213] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\not_strict_mode.app_rd_data_reg[197] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\not_strict_mode.app_rd_data_reg[237] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\not_strict_mode.app_rd_data_reg[245] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\not_strict_mode.app_rd_data_reg[229] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\not_strict_mode.app_rd_data_reg[12] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\not_strict_mode.app_rd_data_reg[20] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\not_strict_mode.app_rd_data_reg[4] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\not_strict_mode.app_rd_data_reg[44] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\not_strict_mode.app_rd_data_reg[52] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\not_strict_mode.app_rd_data_reg[36] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\not_strict_mode.app_rd_data_reg[76] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\not_strict_mode.app_rd_data_reg[84] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\not_strict_mode.app_rd_data_reg[68] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\not_strict_mode.app_rd_data_reg[108] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\not_strict_mode.app_rd_data_reg[116] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\not_strict_mode.app_rd_data_reg[100] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\not_strict_mode.app_rd_data_reg[140] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\not_strict_mode.app_rd_data_reg[148] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\not_strict_mode.app_rd_data_reg[132] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\not_strict_mode.app_rd_data_reg[172] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\not_strict_mode.app_rd_data_reg[180] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\not_strict_mode.app_rd_data_reg[164] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\not_strict_mode.app_rd_data_reg[204] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\not_strict_mode.app_rd_data_reg[212] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\not_strict_mode.app_rd_data_reg[196] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\not_strict_mode.app_rd_data_reg[236]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\not_strict_mode.app_rd_data_reg[244]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\not_strict_mode.app_rd_data_reg[228]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\not_strict_mode.app_rd_data_reg[11] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\not_strict_mode.app_rd_data_reg[19] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\not_strict_mode.app_rd_data_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\not_strict_mode.app_rd_data_reg[43] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\not_strict_mode.app_rd_data_reg[51] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\not_strict_mode.app_rd_data_reg[35] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\not_strict_mode.app_rd_data_reg[75] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\not_strict_mode.app_rd_data_reg[83] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\not_strict_mode.app_rd_data_reg[67] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\not_strict_mode.app_rd_data_reg[107] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\not_strict_mode.app_rd_data_reg[115] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\not_strict_mode.app_rd_data_reg[99] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\not_strict_mode.app_rd_data_reg[139] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\not_strict_mode.app_rd_data_reg[147] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\not_strict_mode.app_rd_data_reg[131] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\not_strict_mode.app_rd_data_reg[171] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\not_strict_mode.app_rd_data_reg[179] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\not_strict_mode.app_rd_data_reg[163] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\not_strict_mode.app_rd_data_reg[203] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\not_strict_mode.app_rd_data_reg[211] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\not_strict_mode.app_rd_data_reg[195] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\not_strict_mode.app_rd_data_reg[235] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\not_strict_mode.app_rd_data_reg[243] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\not_strict_mode.app_rd_data_reg[227] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\not_strict_mode.app_rd_data_reg[10] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\not_strict_mode.app_rd_data_reg[18] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\not_strict_mode.app_rd_data_reg[2] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\not_strict_mode.app_rd_data_reg[42] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\not_strict_mode.app_rd_data_reg[50] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\not_strict_mode.app_rd_data_reg[34] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\not_strict_mode.app_rd_data_reg[74] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\not_strict_mode.app_rd_data_reg[82] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\not_strict_mode.app_rd_data_reg[66] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\not_strict_mode.app_rd_data_reg[106] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\not_strict_mode.app_rd_data_reg[114] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\not_strict_mode.app_rd_data_reg[98] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\not_strict_mode.app_rd_data_reg[138] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\not_strict_mode.app_rd_data_reg[146] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\not_strict_mode.app_rd_data_reg[130] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\not_strict_mode.app_rd_data_reg[170] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\not_strict_mode.app_rd_data_reg[178] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\not_strict_mode.app_rd_data_reg[162] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\not_strict_mode.app_rd_data_reg[202] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\not_strict_mode.app_rd_data_reg[210] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\not_strict_mode.app_rd_data_reg[194] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\not_strict_mode.app_rd_data_reg[234] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\not_strict_mode.app_rd_data_reg[242] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\not_strict_mode.app_rd_data_reg[226] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\not_strict_mode.app_rd_data_reg[9] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\not_strict_mode.app_rd_data_reg[17] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\not_strict_mode.app_rd_data_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\not_strict_mode.app_rd_data_reg[41] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\not_strict_mode.app_rd_data_reg[49] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\not_strict_mode.app_rd_data_reg[33] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\not_strict_mode.app_rd_data_reg[73] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\not_strict_mode.app_rd_data_reg[81] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\not_strict_mode.app_rd_data_reg[65] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\not_strict_mode.app_rd_data_reg[105] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\not_strict_mode.app_rd_data_reg[113] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\not_strict_mode.app_rd_data_reg[97] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\not_strict_mode.app_rd_data_reg[137] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\not_strict_mode.app_rd_data_reg[145] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\not_strict_mode.app_rd_data_reg[129] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\not_strict_mode.app_rd_data_reg[169] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\not_strict_mode.app_rd_data_reg[177] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\not_strict_mode.app_rd_data_reg[161] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\not_strict_mode.app_rd_data_reg[201] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\not_strict_mode.app_rd_data_reg[209] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\not_strict_mode.app_rd_data_reg[193] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\not_strict_mode.app_rd_data_reg[233] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\not_strict_mode.app_rd_data_reg[241] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\not_strict_mode.app_rd_data_reg[225] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\not_strict_mode.app_rd_data_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\not_strict_mode.app_rd_data_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\not_strict_mode.app_rd_data_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\not_strict_mode.app_rd_data_reg[40] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\not_strict_mode.app_rd_data_reg[48] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\not_strict_mode.app_rd_data_reg[32] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\not_strict_mode.app_rd_data_reg[72] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\not_strict_mode.app_rd_data_reg[80] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\not_strict_mode.app_rd_data_reg[64] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\not_strict_mode.app_rd_data_reg[104] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\not_strict_mode.app_rd_data_reg[112] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\not_strict_mode.app_rd_data_reg[96] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\not_strict_mode.app_rd_data_reg[136] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\not_strict_mode.app_rd_data_reg[144] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\not_strict_mode.app_rd_data_reg[128] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\not_strict_mode.app_rd_data_reg[168] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\not_strict_mode.app_rd_data_reg[176] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\not_strict_mode.app_rd_data_reg[160] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\not_strict_mode.app_rd_data_reg[200] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\not_strict_mode.app_rd_data_reg[208] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\not_strict_mode.app_rd_data_reg[192] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\not_strict_mode.app_rd_data_reg[232] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\not_strict_mode.app_rd_data_reg[240] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\not_strict_mode.app_rd_data_reg[224] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\not_strict_mode.app_rd_data_reg[15] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\not_strict_mode.app_rd_data_reg[23] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\not_strict_mode.app_rd_data_reg[7] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\not_strict_mode.app_rd_data_reg[47] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\not_strict_mode.app_rd_data_reg[55] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 (\not_strict_mode.app_rd_data_reg[39] ), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23] ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .if_empty_r(if_empty_r), .if_empty_r_0(if_empty_r_5), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[7:0]), .mem_dq_out(mem_dq_out[8:0]), .mem_dq_ts(mem_dq_ts[8:0]), .mem_dqs_in(mem_dqs_in[0]), .mem_dqs_out(mem_dqs_out[0]), .mem_dqs_ts(mem_dqs_ts[0]), .mem_refclk(mem_refclk), .mux_wrdata_en(mux_wrdata_en), .my_empty(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3]), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[7] (\my_empty_reg[7] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[252]_0 (\not_strict_mode.app_rd_data_reg[252]_0 ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 ({\not_strict_mode.app_rd_data_reg[255]_0 [255:248],\not_strict_mode.app_rd_data_reg[255]_0 [223:216],\not_strict_mode.app_rd_data_reg[255]_0 [191:184],\not_strict_mode.app_rd_data_reg[255]_0 [159:152],\not_strict_mode.app_rd_data_reg[255]_0 [127:120],\not_strict_mode.app_rd_data_reg[255]_0 [95:88],\not_strict_mode.app_rd_data_reg[255]_0 [63:56],\not_strict_mode.app_rd_data_reg[255]_0 [31:24]}), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31]_0 ), .\not_strict_mode.app_rd_data_reg[31]_1 (\not_strict_mode.app_rd_data_reg[31]_1 ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ), .p_0_out(p_0_out), .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}), .phy_dout({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}), .phy_if_reset(phy_if_reset), .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[3] [0]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg), .pi_phase_locked_all_r1_reg(\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg), .\po_counter_read_val_reg[8] (A_po_counter_read_val), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6]_0 ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .\wr_ptr_reg[1] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\write_buffer.wr_buf_out_data_reg[248] (\write_buffer.wr_buf_out_data_reg[248] ), .\write_buffer.wr_buf_out_data_reg[249] (\write_buffer.wr_buf_out_data_reg[249] ), .\write_buffer.wr_buf_out_data_reg[250] (\write_buffer.wr_buf_out_data_reg[250] ), .\write_buffer.wr_buf_out_data_reg[251] (\write_buffer.wr_buf_out_data_reg[251] ), .\write_buffer.wr_buf_out_data_reg[252] (\write_buffer.wr_buf_out_data_reg[252] ), .\write_buffer.wr_buf_out_data_reg[253] (\write_buffer.wr_buf_out_data_reg[253] ), .\write_buffer.wr_buf_out_data_reg[254] (\write_buffer.wr_buf_out_data_reg[254] ), .\write_buffer.wr_buf_out_data_reg[255] (\write_buffer.wr_buf_out_data_reg[255] ), .\write_buffer.wr_buf_out_data_reg[287] ({\write_buffer.wr_buf_out_data_reg[287] [31],\write_buffer.wr_buf_out_data_reg[287] [27],\write_buffer.wr_buf_out_data_reg[287] [23],\write_buffer.wr_buf_out_data_reg[287] [19],\write_buffer.wr_buf_out_data_reg[287] [15],\write_buffer.wr_buf_out_data_reg[287] [11],\write_buffer.wr_buf_out_data_reg[287] [7],\write_buffer.wr_buf_out_data_reg[287] [3]})); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized0 \ddr_byte_lane_B.ddr_byte_lane_B (.A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ), .A_rst_primitives_reg_0(\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ), .A_rst_primitives_reg_1(\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ), .B_byte_rd_en(B_byte_rd_en), .B_rclk(B_rclk), .CLK(CLK), .CLKB0_7(CLKB0_7), .COUNTERREADVAL(B_pi_counter_read_val), .D_byte_rd_en(D_byte_rd_en), .LD0_3(LD0_3), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ), .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_2 ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_0), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_0), .delay_done_r4_reg(delay_done_r4_reg_0), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_3 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_4 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_5 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_6 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_15 ), .idelay_inc(idelay_inc), .idelay_ld_rst_0(idelay_ld_rst_0), .if_empty_r(if_empty_r_2), .if_empty_r_0(if_empty_r_5), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[15:8]), .mem_dq_out(mem_dq_out[17:9]), .mem_dq_ts(mem_dq_ts[17:9]), .mem_dqs_in(mem_dqs_in[1]), .mem_dqs_out(mem_dqs_out[1]), .mem_dqs_ts(mem_dqs_ts[1]), .mem_refclk(mem_refclk), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .mux_wrdata_en(mux_wrdata_en), .my_empty({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}), .\my_empty_reg[1] (\my_empty_reg[1]_0 ), .\my_empty_reg[4] (\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ), .\my_empty_reg[7] (\my_empty_reg[7]_0 ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[22] (\not_strict_mode.app_rd_data_reg[22] ), .\not_strict_mode.app_rd_data_reg[23] (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23]_0 ), .\not_strict_mode.app_rd_data_reg[23]_1 (\not_strict_mode.app_rd_data_reg[23]_1 ), .\not_strict_mode.app_rd_data_reg[240] (\not_strict_mode.app_rd_data_reg[240] ), .\not_strict_mode.app_rd_data_reg[241] (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[244]_0 (\not_strict_mode.app_rd_data_reg[244]_0 ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] ({\not_strict_mode.app_rd_data_reg[255]_0 [247:240],\not_strict_mode.app_rd_data_reg[255]_0 [215:208],\not_strict_mode.app_rd_data_reg[255]_0 [183:176],\not_strict_mode.app_rd_data_reg[255]_0 [151:144],\not_strict_mode.app_rd_data_reg[255]_0 [119:112],\not_strict_mode.app_rd_data_reg[255]_0 [87:80],\not_strict_mode.app_rd_data_reg[255]_0 [55:48],\not_strict_mode.app_rd_data_reg[255]_0 [23:16]}), .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .out(out), .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}), .phy_dout({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_if_reset(phy_if_reset), .phy_rddata_en(phy_rddata_en), .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[3] [1]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg_0), .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_0), .\po_counter_read_val_reg[8] (B_po_counter_read_val), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_ptr_timing_reg[1] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .tail_r(tail_r), .\write_buffer.wr_buf_out_data_reg[240] (\write_buffer.wr_buf_out_data_reg[240] ), .\write_buffer.wr_buf_out_data_reg[241] (\write_buffer.wr_buf_out_data_reg[241] ), .\write_buffer.wr_buf_out_data_reg[242] (\write_buffer.wr_buf_out_data_reg[242] ), .\write_buffer.wr_buf_out_data_reg[243] (\write_buffer.wr_buf_out_data_reg[243] ), .\write_buffer.wr_buf_out_data_reg[244] (\write_buffer.wr_buf_out_data_reg[244] ), .\write_buffer.wr_buf_out_data_reg[245] (\write_buffer.wr_buf_out_data_reg[245] ), .\write_buffer.wr_buf_out_data_reg[246] (\write_buffer.wr_buf_out_data_reg[246] ), .\write_buffer.wr_buf_out_data_reg[247] (\write_buffer.wr_buf_out_data_reg[247] ), .\write_buffer.wr_buf_out_data_reg[286] ({\write_buffer.wr_buf_out_data_reg[287] [30],\write_buffer.wr_buf_out_data_reg[287] [26],\write_buffer.wr_buf_out_data_reg[287] [22],\write_buffer.wr_buf_out_data_reg[287] [18],\write_buffer.wr_buf_out_data_reg[287] [14],\write_buffer.wr_buf_out_data_reg[287] [10],\write_buffer.wr_buf_out_data_reg[287] [6],\write_buffer.wr_buf_out_data_reg[287] [2]})); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized1 \ddr_byte_lane_C.ddr_byte_lane_C (.A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .CLK(CLK), .CLKB0_8(CLKB0_8), .COUNTERREADVAL(C_pi_counter_read_val), .C_byte_rd_en(C_byte_rd_en), .D_byte_rd_en(D_byte_rd_en), .LD0_4(LD0_4), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0]_0 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_1), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_1), .delay_done_r4_reg(delay_done_r4_reg_1), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_7 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_8 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_9 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_10 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_16 ), .idelay_inc(idelay_inc), .idelay_ld_rst_1(idelay_ld_rst_1), .if_empty_r(if_empty_r_5), .if_empty_r_0(if_empty_r_2), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[23:16]), .mem_dq_out(mem_dq_out[26:18]), .mem_dq_ts(mem_dq_ts[26:18]), .mem_dqs_in(mem_dqs_in[2]), .mem_dqs_out(mem_dqs_out[2]), .mem_dqs_ts(mem_dqs_ts[2]), .mem_refclk(mem_refclk), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1] (\my_empty_reg[1]_1 ), .\my_empty_reg[4] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ), .\my_empty_reg[7] (\my_empty_reg[7]_1 ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15]_0 ), .\not_strict_mode.app_rd_data_reg[15]_1 (\not_strict_mode.app_rd_data_reg[15]_1 ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ), .\not_strict_mode.app_rd_data_reg[233] (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[234] (\not_strict_mode.app_rd_data_reg[234] ), .\not_strict_mode.app_rd_data_reg[235] (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[236] (\not_strict_mode.app_rd_data_reg[236] ), .\not_strict_mode.app_rd_data_reg[236]_0 (\not_strict_mode.app_rd_data_reg[236]_0 ), .\not_strict_mode.app_rd_data_reg[237] (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[238] (\not_strict_mode.app_rd_data_reg[238] ), .\not_strict_mode.app_rd_data_reg[239] ({\not_strict_mode.app_rd_data_reg[255]_0 [239:232],\not_strict_mode.app_rd_data_reg[255]_0 [207:200],\not_strict_mode.app_rd_data_reg[255]_0 [175:168],\not_strict_mode.app_rd_data_reg[255]_0 [143:136],\not_strict_mode.app_rd_data_reg[255]_0 [111:104],\not_strict_mode.app_rd_data_reg[255]_0 [79:72],\not_strict_mode.app_rd_data_reg[255]_0 [47:40],\not_strict_mode.app_rd_data_reg[255]_0 [15:8]}), .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[72] (\not_strict_mode.app_rd_data_reg[72] ), .\not_strict_mode.app_rd_data_reg[73] (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[74] (\not_strict_mode.app_rd_data_reg[74] ), .\not_strict_mode.app_rd_data_reg[75] (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[76] (\not_strict_mode.app_rd_data_reg[76] ), .\not_strict_mode.app_rd_data_reg[77] (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[78] (\not_strict_mode.app_rd_data_reg[78] ), .\not_strict_mode.app_rd_data_reg[79] (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ), .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}), .phy_dout({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}), .phy_if_reset(phy_if_reset), .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[3] [2]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg_1), .pi_phase_locked_all_r1_reg(\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_1), .\po_counter_read_val_reg[8] (C_po_counter_read_val), .\rd_ptr_timing_reg[1] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6]_0 ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .\write_buffer.wr_buf_out_data_reg[232] (\write_buffer.wr_buf_out_data_reg[232] ), .\write_buffer.wr_buf_out_data_reg[233] (\write_buffer.wr_buf_out_data_reg[233] ), .\write_buffer.wr_buf_out_data_reg[234] (\write_buffer.wr_buf_out_data_reg[234] ), .\write_buffer.wr_buf_out_data_reg[235] (\write_buffer.wr_buf_out_data_reg[235] ), .\write_buffer.wr_buf_out_data_reg[236] (\write_buffer.wr_buf_out_data_reg[236] ), .\write_buffer.wr_buf_out_data_reg[237] (\write_buffer.wr_buf_out_data_reg[237] ), .\write_buffer.wr_buf_out_data_reg[238] (\write_buffer.wr_buf_out_data_reg[238] ), .\write_buffer.wr_buf_out_data_reg[239] (\write_buffer.wr_buf_out_data_reg[239] ), .\write_buffer.wr_buf_out_data_reg[285] ({\write_buffer.wr_buf_out_data_reg[287] [29],\write_buffer.wr_buf_out_data_reg[287] [25],\write_buffer.wr_buf_out_data_reg[287] [21],\write_buffer.wr_buf_out_data_reg[287] [17],\write_buffer.wr_buf_out_data_reg[287] [13],\write_buffer.wr_buf_out_data_reg[287] [9],\write_buffer.wr_buf_out_data_reg[287] [5],\write_buffer.wr_buf_out_data_reg[287] [1]})); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized2 \ddr_byte_lane_D.ddr_byte_lane_D (.A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(C_pi_counter_read_val), .A_rst_primitives_reg_0(A_pi_counter_read_val), .A_rst_primitives_reg_1(B_po_counter_read_val), .A_rst_primitives_reg_2(C_po_counter_read_val), .A_rst_primitives_reg_3(A_po_counter_read_val), .CLK(CLK), .CLKB0_9(CLKB0_9), .COUNTERREADVAL(B_pi_counter_read_val), .C_byte_rd_en(C_byte_rd_en), .D({\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_227 }), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_byte_rd_en(D_byte_rd_en), .LD0_5(LD0_5), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ), .\calib_sel_reg[0] (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_3 ), .\calib_sel_reg[1] (\calib_sel_reg[1]_1 ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0]_1 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_2), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_2), .delay_done_r4_reg(delay_done_r4_reg_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_11 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_12 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_13 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_14 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_17 ), .idelay_inc(idelay_inc), .idelay_ld_rst_2(idelay_ld_rst_2), .if_empty_r(if_empty_r), .if_empty_r_0(if_empty_r_2), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[31:24]), .mem_dq_out(mem_dq_out[35:27]), .mem_dq_ts(mem_dq_ts[35:27]), .mem_dqs_in(mem_dqs_in[3]), .mem_dqs_out(mem_dqs_out[3]), .mem_dqs_ts(mem_dqs_ts[3]), .mem_refclk(mem_refclk), .mux_rd_valid_r_reg(\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1] (\my_empty_reg[1]_2 ), .\my_empty_reg[4] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\my_empty_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ), .\my_empty_reg[7] (\my_empty_reg[7]_2 ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), .\not_strict_mode.app_rd_data_reg[227] (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[228] (\not_strict_mode.app_rd_data_reg[228] ), .\not_strict_mode.app_rd_data_reg[228]_0 (\not_strict_mode.app_rd_data_reg[228]_0 ), .\not_strict_mode.app_rd_data_reg[229] (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[230] (\not_strict_mode.app_rd_data_reg[230] ), .\not_strict_mode.app_rd_data_reg[231] ({\not_strict_mode.app_rd_data_reg[255]_0 [231:224],\not_strict_mode.app_rd_data_reg[255]_0 [199:192],\not_strict_mode.app_rd_data_reg[255]_0 [167:160],\not_strict_mode.app_rd_data_reg[255]_0 [135:128],\not_strict_mode.app_rd_data_reg[255]_0 [103:96],\not_strict_mode.app_rd_data_reg[255]_0 [71:64],\not_strict_mode.app_rd_data_reg[255]_0 [39:32],\not_strict_mode.app_rd_data_reg[255]_0 [7:0]}), .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), .\not_strict_mode.app_rd_data_reg[70] (\not_strict_mode.app_rd_data_reg[70] ), .\not_strict_mode.app_rd_data_reg[71] (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[7] (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7]_0 ), .\not_strict_mode.app_rd_data_reg[7]_1 (\not_strict_mode.app_rd_data_reg[7]_1 ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ), .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}), .phy_dout({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}), .phy_if_reset(phy_if_reset), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] [3]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg_2), .pi_phase_locked_all_r1_reg(\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_2), .\po_counter_read_val_reg[8] ({\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_236 }), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6]_0 ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .\write_buffer.wr_buf_out_data_reg[224] (\write_buffer.wr_buf_out_data_reg[224] ), .\write_buffer.wr_buf_out_data_reg[225] (\write_buffer.wr_buf_out_data_reg[225] ), .\write_buffer.wr_buf_out_data_reg[226] (\write_buffer.wr_buf_out_data_reg[226] ), .\write_buffer.wr_buf_out_data_reg[227] (\write_buffer.wr_buf_out_data_reg[227] ), .\write_buffer.wr_buf_out_data_reg[228] (\write_buffer.wr_buf_out_data_reg[228] ), .\write_buffer.wr_buf_out_data_reg[229] (\write_buffer.wr_buf_out_data_reg[229] ), .\write_buffer.wr_buf_out_data_reg[230] (\write_buffer.wr_buf_out_data_reg[230] ), .\write_buffer.wr_buf_out_data_reg[231] (\write_buffer.wr_buf_out_data_reg[231] ), .\write_buffer.wr_buf_out_data_reg[284] ({\write_buffer.wr_buf_out_data_reg[287] [28],\write_buffer.wr_buf_out_data_reg[287] [24],\write_buffer.wr_buf_out_data_reg[287] [20],\write_buffer.wr_buf_out_data_reg[287] [16],\write_buffer.wr_buf_out_data_reg[287] [12],\write_buffer.wr_buf_out_data_reg[287] [8],\write_buffer.wr_buf_out_data_reg[287] [4],\write_buffer.wr_buf_out_data_reg[287] [0]})); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(A_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(B_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(C_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(D_pi_rst_div2)); LUT2 #( .INIT(4'h8)) \mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_i_1 (.I0(mcGo_w), .I1(mcGo_w__0), .O(\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 )); FDRE #( .INIT(1'b0)) mcGo_reg (.C(CLK), .CE(1'b1), .D(mcGo_reg_0), .Q(mcGo_w), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) ofs_rdy_r_i_2 (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [2]), .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [4]), .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [3]), .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [2]), .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [4]), .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [3]), .O(ofs_rdy_r_reg_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) ofs_rdy_r_i_3 (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [2]), .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [4]), .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [3]), .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [2]), .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [4]), .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [3]), .O(ofs_rdy_r_reg)); (* box_type = "PRIMITIVE" *) PHASER_REF #( .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0)) phaser_ref_i (.CLKIN(freq_refclk), .LOCKED(ref_dll_lock_w__0), .PWRDWN(1'b0), .RST(RST0)); (* box_type = "PRIMITIVE" *) PHY_CONTROL #( .AO_TOGGLE(1), .AO_WRLVL_EN(4'b0000), .BURST_MODE("TRUE"), .CLK_RATIO(4), .CMD_OFFSET(8), .CO_DURATION(1), .DATA_CTL_A_N("TRUE"), .DATA_CTL_B_N("TRUE"), .DATA_CTL_C_N("TRUE"), .DATA_CTL_D_N("TRUE"), .DISABLE_SEQ_MATCH("TRUE"), .DI_DURATION(1), .DO_DURATION(1), .EVENTS_DELAY(18), .FOUR_WINDOW_CLOCKS(63), .MULTI_REGION("TRUE"), .PHY_COUNT_ENABLE("FALSE"), .RD_CMD_OFFSET_0(10), .RD_CMD_OFFSET_1(10), .RD_CMD_OFFSET_2(10), .RD_CMD_OFFSET_3(10), .RD_DURATION_0(6), .RD_DURATION_1(6), .RD_DURATION_2(6), .RD_DURATION_3(6), .SYNC_MODE("FALSE"), .WR_CMD_OFFSET_0(8), .WR_CMD_OFFSET_1(8), .WR_CMD_OFFSET_2(8), .WR_CMD_OFFSET_3(8), .WR_DURATION_0(7), .WR_DURATION_1(7), .WR_DURATION_2(7), .WR_DURATION_3(7)) phy_control_i (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}), .INBURSTPENDING(phaser_ctl_bus[7:4]), .INRANKA(phaser_ctl_bus[9:8]), .INRANKB(phaser_ctl_bus[11:10]), .INRANKC(phaser_ctl_bus[13:12]), .INRANKD(phaser_ctl_bus[15:14]), .MEMREFCLK(mem_refclk), .OUTBURSTPENDING(phaser_ctl_bus[3:0]), .PCENABLECALIB(phy_encalib), .PHYCLK(CLK), .PHYCTLALMOSTFULL(phy_control_i_n_0), .PHYCTLEMPTY(phy_control_i_n_1), .PHYCTLFULL(_phy_ctl_full_p__0), .PHYCTLMSTREMPTY(phy_ctl_mstr_empty), .PHYCTLREADY(rst_primitives_reg_0), .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}), .PHYCTLWRENABLE(phy_ctl_wr_i2), .PLLLOCK(pll_locked), .READCALIBENABLE(phy_read_calib), .REFDLLLOCK(ref_dll_lock_w__0), .RESET(in0), .SYNCIN(sync_pulse), .WRITECALIBENABLE(phy_write_calib)); FDRE #( .INIT(1'b0)) \pi_counter_read_val_reg[0] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_227 ), .Q(\pi_rdval_cnt_reg[5] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_counter_read_val_reg[1] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ), .Q(\pi_rdval_cnt_reg[5] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_counter_read_val_reg[2] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ), .Q(\pi_rdval_cnt_reg[5] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_counter_read_val_reg[3] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ), .Q(\pi_rdval_cnt_reg[5] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_counter_read_val_reg[4] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ), .Q(\pi_rdval_cnt_reg[5] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_counter_read_val_reg[5] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ), .Q(\pi_rdval_cnt_reg[5] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[0] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ), .Q(\po_rdval_cnt_reg[8] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[1] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ), .Q(\po_rdval_cnt_reg[8] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[2] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ), .Q(\po_rdval_cnt_reg[8] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[3] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ), .Q(\po_rdval_cnt_reg[8] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[4] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ), .Q(\po_rdval_cnt_reg[8] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[5] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ), .Q(\po_rdval_cnt_reg[8] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[6] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ), .Q(\po_rdval_cnt_reg[8] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[7] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ), .Q(\po_rdval_cnt_reg[8] [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[8] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ), .Q(\po_rdval_cnt_reg[8] [8]), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) SRL16E #( .INIT(16'h0000)) \rclk_delay_reg[10]_srl11 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(rst_primitives_reg_1), .Q(\rclk_delay_reg[10]_srl11_n_0 )); FDRE #( .INIT(1'b0)) \rclk_delay_reg[11] (.C(CLK), .CE(1'b1), .D(\rclk_delay_reg[10]_srl11_n_0 ), .Q(rclk_delay_11), .R(1'b0)); FDCE #( .INIT(1'b0)) rst_out_reg (.C(CLK), .CE(1'b1), .CLR(rstdiv0_sync_r1_reg_rep__9), .D(\rclk_delay_reg[11]_0 ), .Q(mcGo_reg_0)); FDRE #( .INIT(1'b0)) rst_primitives_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_wr_i2_reg), .Q(rst_primitives), .R(1'b0)); LUT5 #( .INIT(32'h7FFFFFFF)) \rstdiv2_sync_r[11]_i_1 (.I0(ref_dll_lock_w__0), .I1(ref_dll_lock_w), .I2(sys_rst), .I3(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .I4(mmcm_locked), .O(rst_sync_r1_reg)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_4lanes" *) module ddr3_ifmig_7series_v4_0_ddr_phy_4lanes__parameterized0 (\rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , phy_ctl_mstr_empty, ref_dll_lock_w, mcGo_w__0, \my_empty_reg[1] , \my_empty_reg[1]_0 , phy_mc_ctl_full, \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \byte_r_reg[0] , \po_counter_read_val_r_reg[5] , of_ctl_full_v, wr_en, wr_en_5, wr_en_6, Q, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , mem_dq_out, \po_rdval_cnt_reg[8] , ddr_ck_out, \my_empty_reg[7] , CLK, init_calib_complete_reg_rep__6, D5, D6, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, D0, D1, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, \calib_sel_reg[0]_2 , sync_pulse, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , \calib_sel_reg[1]_2 , \calib_sel_reg[1]_3 , \gen_byte_sel_div1.calib_in_common_reg_1 , \calib_sel_reg[1]_4 , \calib_sel_reg[1]_5 , \calib_sel_reg[1]_6 , phy_ctl_wr_i2, pll_locked, phy_read_calib, in0, phy_write_calib, PHYCTLWD, RST0, rstdiv0_sync_r1_reg_rep__9, mux_cmd_wren, mem_out, \rd_ptr_reg[3] , _phy_ctl_full_p__0, \rd_ptr_reg[3]_0 , init_calib_complete_reg_rep__5, mc_cas_n, mc_address, init_calib_complete_reg_rep, \calib_sel_reg[3] , \po_counter_read_val_reg[5]_0 , D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , phy_dout, init_calib_complete_reg_rep__6_0); output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output phy_ctl_mstr_empty; output [0:0]ref_dll_lock_w; output [0:0]mcGo_w__0; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output phy_mc_ctl_full; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \byte_r_reg[0] ; output [5:0]\po_counter_read_val_r_reg[5] ; output [0:0]of_ctl_full_v; output wr_en; output wr_en_5; output wr_en_6; output [3:0]Q; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [23:0]mem_dq_out; output [4:0]\po_rdval_cnt_reg[8] ; output [1:0]ddr_ck_out; output [31:0]\my_empty_reg[7] ; input CLK; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [2:0]D0; input [2:0]D1; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[0]_2 ; input sync_pulse; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input \calib_sel_reg[1]_2 ; input \calib_sel_reg[1]_3 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \calib_sel_reg[1]_4 ; input \calib_sel_reg[1]_5 ; input \calib_sel_reg[1]_6 ; input phy_ctl_wr_i2; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input [10:0]PHYCTLWD; input RST0; input rstdiv0_sync_r1_reg_rep__9; input mux_cmd_wren; input [11:0]mem_out; input [33:0]\rd_ptr_reg[3] ; input [0:0]_phy_ctl_full_p__0; input [17:0]\rd_ptr_reg[3]_0 ; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]mc_address; input init_calib_complete_reg_rep; input [2:0]\calib_sel_reg[3] ; input [5:0]\po_counter_read_val_reg[5]_0 ; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input D_po_sel_fine_oclk_delay125_out; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input [35:0]phy_dout; input init_calib_complete_reg_rep__6_0; wire A_of_full; (* async_reg = "true" *) wire A_pi_rst_div2; wire [8:0]A_po_counter_read_val; wire A_rst_primitives; (* async_reg = "true" *) wire B_pi_rst_div2; wire [8:0]B_po_counter_read_val; wire CLK; wire C_of_full; (* async_reg = "true" *) wire C_pi_rst_div2; wire [8:0]C_po_counter_read_val; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire D_of_full; (* async_reg = "true" *) wire D_pi_rst_div2; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [10:0]PHYCTLWD; wire [3:0]Q; wire RST0; wire [1:1]_phy_ctl_full_p; wire [0:0]_phy_ctl_full_p__0; wire \byte_r_reg[0] ; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire \calib_sel_reg[1]_3 ; wire \calib_sel_reg[1]_4 ; wire \calib_sel_reg[1]_5 ; wire \calib_sel_reg[1]_6 ; wire [2:0]\calib_sel_reg[3] ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_1 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_2 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_3 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_4 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_5 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_6 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_7 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_8 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_9 ; wire [1:0]ddr_ck_out; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire in0; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire [3:0]init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire [0:0]mcGo_w__0; wire [1:0]mc_address; wire [0:0]mc_cas_n; wire [23:0]mem_dq_out; wire [11:0]mem_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire [31:0]\my_empty_reg[7] ; wire [0:0]of_ctl_full_v; wire ofifo_rst; wire [3:3]phaser_ctl_bus; wire phy_control_i_n_0; wire phy_control_i_n_10; wire phy_control_i_n_11; wire phy_control_i_n_14; wire phy_control_i_n_15; wire phy_control_i_n_16; wire phy_control_i_n_17; wire phy_control_i_n_18; wire phy_control_i_n_19; wire phy_control_i_n_20; wire phy_control_i_n_21; wire phy_control_i_n_23; wire phy_control_i_n_24; wire phy_control_i_n_25; wire phy_control_i_n_3; wire phy_control_i_n_4; wire phy_control_i_n_5; wire phy_control_i_n_6; wire phy_control_i_n_7; wire phy_control_i_n_8; wire phy_control_i_n_9; wire phy_ctl_mstr_empty; wire phy_ctl_wr_i2; wire [35:0]phy_dout; wire [1:0]phy_encalib; wire phy_mc_ctl_full; wire phy_read_calib; wire phy_write_calib; wire pll_locked; wire [5:0]\po_counter_read_val_r_reg[5] ; wire [5:0]\po_counter_read_val_reg[5]_0 ; wire [5:1]\po_counter_read_val_w[1]_2 ; wire [4:0]\po_rdval_cnt_reg[8] ; wire rclk_delay_11; wire \rclk_delay_reg[10]_srl11_i_1__0_n_0 ; wire \rclk_delay_reg[10]_srl11_n_0 ; wire [33:0]\rd_ptr_reg[3] ; wire [17:0]\rd_ptr_reg[3]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]ref_dll_lock_w; wire rst_out_i_1__0_n_0; wire rst_out_reg_n_0; wire rst_primitives; wire rst_primitives_i_1__0_n_0; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; FDRE #( .INIT(1'b0)) A_rst_primitives_reg (.C(CLK), .CE(1'b1), .D(rst_primitives), .Q(A_rst_primitives), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \byte_r[0]_i_3 (.I0(\po_counter_read_val_r_reg[5] [2]), .I1(\po_counter_read_val_r_reg[5] [5]), .I2(\po_counter_read_val_r_reg[5] [0]), .I3(\po_counter_read_val_r_reg[5] [3]), .I4(\po_counter_read_val_r_reg[5] [1]), .I5(\po_counter_read_val_r_reg[5] [4]), .O(\byte_r_reg[0] )); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized3 \ddr_byte_lane_A.ddr_byte_lane_A (.A_of_full(A_of_full), .A_rst_primitives(A_rst_primitives), .CLK(CLK), .COUNTERREADVAL(A_po_counter_read_val), .D0(D0), .D1(D1), .OUTBURSTPENDING(phy_control_i_n_25), .PCENABLECALIB(phy_encalib), .Q(\wr_ptr_timing_reg[2]_0 ), .SR(ofifo_rst), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_1 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_2 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_0 ), .mem_dq_out(mem_dq_out[1:0]), .mem_out(mem_out), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1] ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_9 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_10 ), .sync_pulse(sync_pulse), .wr_en(wr_en)); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized4 \ddr_byte_lane_B.ddr_byte_lane_B (.A_of_full(A_of_full), .A_rst_primitives(A_rst_primitives), .CLK(CLK), .COUNTERREADVAL(B_po_counter_read_val), .C_of_full(C_of_full), .D5(D5), .D6(D6), .D_of_full(D_of_full), .OUTBURSTPENDING(phy_control_i_n_24), .PCENABLECALIB(phy_encalib), .Q(Q), .SR(ofifo_rst), .\calib_sel_reg[1] (\calib_sel_reg[1]_3 ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_4 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_5 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_6 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_1 ), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .mem_dq_out(mem_dq_out[4:2]), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1]_1 ), .of_ctl_full_v(of_ctl_full_v), .\rd_ptr_reg[3] (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .sync_pulse(sync_pulse), .wr_en_5(wr_en_5)); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized5 \ddr_byte_lane_C.ddr_byte_lane_C (.A_rst_primitives(A_rst_primitives), .CLK(CLK), .COUNTERREADVAL(C_po_counter_read_val), .C_of_full(C_of_full), .D2(D2), .D3(D3), .D7(D7), .D8(D8), .D9(D9), .OUTBURSTPENDING(phy_control_i_n_23), .PCENABLECALIB(phy_encalib), .Q(\wr_ptr_timing_reg[2] ), .SR(ofifo_rst), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .mem_dq_out(mem_dq_out[14:5]), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1]_0 ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_6 ), .sync_pulse(sync_pulse), .wr_en_6(wr_en_6)); ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized6 \ddr_byte_lane_D.ddr_byte_lane_D (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(C_po_counter_read_val), .A_rst_primitives_reg_0(A_po_counter_read_val), .CLK(CLK), .COUNTERREADVAL(B_po_counter_read_val), .D({\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_9 }), .D4(D4), .D_of_full(D_of_full), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .D_po_counter_read_en122_out(D_po_counter_read_en122_out), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .OUTBURSTPENDING(phaser_ctl_bus), .PCENABLECALIB(phy_encalib), .SR(ofifo_rst), .\calib_sel_reg[1] (\calib_sel_reg[3] [1:0]), .ddr_ck_out(ddr_ck_out), .freq_refclk(freq_refclk), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0), .mc_address(mc_address), .mc_cas_n(mc_cas_n), .mem_dq_out(mem_dq_out[23:15]), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1]_2 ), .\my_empty_reg[7] (\my_empty_reg[7] ), .phy_dout(phy_dout), .sync_pulse(sync_pulse)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(A_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(B_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(C_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(D_pi_rst_div2)); FDRE #( .INIT(1'b0)) mcGo_reg (.C(CLK), .CE(1'b1), .D(rst_out_reg_n_0), .Q(mcGo_w__0), .R(1'b0)); (* box_type = "PRIMITIVE" *) PHASER_REF #( .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0)) phaser_ref_i (.CLKIN(freq_refclk), .LOCKED(ref_dll_lock_w), .PWRDWN(1'b0), .RST(RST0)); (* box_type = "PRIMITIVE" *) PHY_CONTROL #( .AO_TOGGLE(1), .AO_WRLVL_EN(4'b0000), .BURST_MODE("TRUE"), .CLK_RATIO(4), .CMD_OFFSET(8), .CO_DURATION(1), .DATA_CTL_A_N("FALSE"), .DATA_CTL_B_N("FALSE"), .DATA_CTL_C_N("FALSE"), .DATA_CTL_D_N("FALSE"), .DISABLE_SEQ_MATCH("TRUE"), .DI_DURATION(1), .DO_DURATION(1), .EVENTS_DELAY(18), .FOUR_WINDOW_CLOCKS(63), .MULTI_REGION("TRUE"), .PHY_COUNT_ENABLE("FALSE"), .RD_CMD_OFFSET_0(10), .RD_CMD_OFFSET_1(10), .RD_CMD_OFFSET_2(10), .RD_CMD_OFFSET_3(10), .RD_DURATION_0(6), .RD_DURATION_1(6), .RD_DURATION_2(6), .RD_DURATION_3(6), .SYNC_MODE("FALSE"), .WR_CMD_OFFSET_0(8), .WR_CMD_OFFSET_1(8), .WR_CMD_OFFSET_2(8), .WR_CMD_OFFSET_3(8), .WR_DURATION_0(7), .WR_DURATION_1(7), .WR_DURATION_2(7), .WR_DURATION_3(7)) phy_control_i (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}), .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}), .INRANKA({phy_control_i_n_4,phy_control_i_n_5}), .INRANKB({phy_control_i_n_6,phy_control_i_n_7}), .INRANKC({phy_control_i_n_8,phy_control_i_n_9}), .INRANKD({phy_control_i_n_10,phy_control_i_n_11}), .MEMREFCLK(mem_refclk), .OUTBURSTPENDING({phaser_ctl_bus,phy_control_i_n_23,phy_control_i_n_24,phy_control_i_n_25}), .PCENABLECALIB(phy_encalib), .PHYCLK(CLK), .PHYCTLALMOSTFULL(phy_control_i_n_0), .PHYCTLEMPTY(phy_ctl_mstr_empty), .PHYCTLFULL(_phy_ctl_full_p), .PHYCTLMSTREMPTY(phy_ctl_mstr_empty), .PHYCTLREADY(phy_control_i_n_3), .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}), .PHYCTLWRENABLE(phy_ctl_wr_i2), .PLLLOCK(pll_locked), .READCALIBENABLE(phy_read_calib), .REFDLLLOCK(ref_dll_lock_w), .RESET(in0), .SYNCIN(sync_pulse), .WRITECALIBENABLE(phy_write_calib)); LUT2 #( .INIT(4'hE)) phy_mc_ctl_full_r_i_1 (.I0(_phy_ctl_full_p), .I1(_phy_ctl_full_p__0), .O(phy_mc_ctl_full)); (* SOFT_HLUTNM = "soft_lutpair1019" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[0]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_counter_read_val_reg[5]_0 [0]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [0])); (* SOFT_HLUTNM = "soft_lutpair1019" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[1]_i_1 (.I0(\po_counter_read_val_w[1]_2 [1]), .I1(\po_counter_read_val_reg[5]_0 [1]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [1])); (* SOFT_HLUTNM = "soft_lutpair1020" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[2]_i_1 (.I0(\po_counter_read_val_w[1]_2 [2]), .I1(\po_counter_read_val_reg[5]_0 [2]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [2])); (* SOFT_HLUTNM = "soft_lutpair1020" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[3]_i_1 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_counter_read_val_reg[5]_0 [3]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [3])); (* SOFT_HLUTNM = "soft_lutpair1021" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[4]_i_1 (.I0(\po_counter_read_val_w[1]_2 [4]), .I1(\po_counter_read_val_reg[5]_0 [4]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [4])); (* SOFT_HLUTNM = "soft_lutpair1021" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[5]_i_1 (.I0(\po_counter_read_val_w[1]_2 [5]), .I1(\po_counter_read_val_reg[5]_0 [5]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [5])); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[0] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_9 ), .Q(\po_rdval_cnt_reg[8] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[1] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ), .Q(\po_counter_read_val_w[1]_2 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[2] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ), .Q(\po_counter_read_val_w[1]_2 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[3] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ), .Q(\po_rdval_cnt_reg[8] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[4] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ), .Q(\po_counter_read_val_w[1]_2 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[5] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ), .Q(\po_counter_read_val_w[1]_2 [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[6] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ), .Q(\po_rdval_cnt_reg[8] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[7] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ), .Q(\po_rdval_cnt_reg[8] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_reg[8] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ), .Q(\po_rdval_cnt_reg[8] [4]), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) SRL16E #( .INIT(16'h0000)) \rclk_delay_reg[10]_srl11 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(\rclk_delay_reg[10]_srl11_i_1__0_n_0 ), .Q(\rclk_delay_reg[10]_srl11_n_0 )); LUT1 #( .INIT(2'h1)) \rclk_delay_reg[10]_srl11_i_1__0 (.I0(rst_primitives), .O(\rclk_delay_reg[10]_srl11_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \rclk_delay_reg[11] (.C(CLK), .CE(1'b1), .D(\rclk_delay_reg[10]_srl11_n_0 ), .Q(rclk_delay_11), .R(1'b0)); LUT2 #( .INIT(4'hE)) rst_out_i_1__0 (.I0(rclk_delay_11), .I1(rst_out_reg_n_0), .O(rst_out_i_1__0_n_0)); FDCE #( .INIT(1'b0)) rst_out_reg (.C(CLK), .CE(1'b1), .CLR(rstdiv0_sync_r1_reg_rep__9), .D(rst_out_i_1__0_n_0), .Q(rst_out_reg_n_0)); LUT1 #( .INIT(2'h1)) rst_primitives_i_1__0 (.I0(phy_control_i_n_3), .O(rst_primitives_i_1__0_n_0)); FDRE #( .INIT(1'b0)) rst_primitives_reg (.C(CLK), .CE(1'b1), .D(rst_primitives_i_1__0_n_0), .Q(rst_primitives), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ck_addr_cmd_delay (ck_addr_cmd_delay_done, po_en_stg2_f, D_po_coarse_enable110_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , \wait_cnt_r_reg[0]_0 , \init_state_r_reg[0] , delay_dec_done_reg_0, delay_dec_done_reg_1, ctl_lane_cnt, po_cnt_inc_reg_0, CLK, rstdiv0_sync_r1_reg_rep__9, \wait_cnt_r_reg[0]_1 , \wait_cnt_r_reg[0]_2 , Q, calib_in_common, dqs_wl_po_stg2_c_incdec, \calib_zero_inputs_reg[1] , cnt_pwron_cke_done_r, \mcGo_r_reg[15] , pi_fine_dly_dec_done, dqs_po_dec_done, rstdiv0_sync_r1_reg_rep__24, rstdiv0_sync_r1_reg_rep__23, cmd_delay_start0, p_1_in); output ck_addr_cmd_delay_done; output po_en_stg2_f; output D_po_coarse_enable110_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output [0:0]\wait_cnt_r_reg[0]_0 ; output \init_state_r_reg[0] ; output delay_dec_done_reg_0; output delay_dec_done_reg_1; output [2:0]ctl_lane_cnt; output po_cnt_inc_reg_0; input CLK; input rstdiv0_sync_r1_reg_rep__9; input \wait_cnt_r_reg[0]_1 ; input \wait_cnt_r_reg[0]_2 ; input [1:0]Q; input calib_in_common; input dqs_wl_po_stg2_c_incdec; input [1:0]\calib_zero_inputs_reg[1] ; input cnt_pwron_cke_done_r; input \mcGo_r_reg[15] ; input pi_fine_dly_dec_done; input dqs_po_dec_done; input rstdiv0_sync_r1_reg_rep__24; input rstdiv0_sync_r1_reg_rep__23; input cmd_delay_start0; input p_1_in; wire CLK; wire D_po_coarse_enable110_out; wire [1:0]Q; wire calib_in_common; wire [1:0]\calib_zero_inputs_reg[1] ; wire ck_addr_cmd_delay_done; wire cmd_delay_start0; wire cnt_pwron_cke_done_r; wire [2:0]ctl_lane_cnt; wire ctl_lane_cnt1; wire \ctl_lane_cnt[0]_i_1_n_0 ; wire \ctl_lane_cnt[1]_i_1_n_0 ; wire \ctl_lane_cnt[2]_i_1_n_0 ; wire \ctl_lane_cnt[2]_i_4_n_0 ; wire \ctl_lane_cnt[3]_i_1_n_0 ; wire \ctl_lane_cnt[3]_i_3_n_0 ; wire \ctl_lane_cnt_reg_n_0_[3] ; wire delay_cnt_r0; wire \delay_cnt_r[0]_i_1_n_0 ; wire \delay_cnt_r[0]_i_2_n_0 ; wire \delay_cnt_r[1]_i_1_n_0 ; wire \delay_cnt_r[2]_i_1_n_0 ; wire \delay_cnt_r[3]_i_1_n_0 ; wire \delay_cnt_r[4]_i_1_n_0 ; wire \delay_cnt_r[5]_i_1_n_0 ; wire \delay_cnt_r[5]_i_3_n_0 ; wire \delay_cnt_r[5]_i_5_n_0 ; wire \delay_cnt_r_reg_n_0_[0] ; wire \delay_cnt_r_reg_n_0_[1] ; wire \delay_cnt_r_reg_n_0_[2] ; wire \delay_cnt_r_reg_n_0_[3] ; wire \delay_cnt_r_reg_n_0_[4] ; wire \delay_cnt_r_reg_n_0_[5] ; wire delay_dec_done; wire delay_dec_done_i_1_n_0; wire delay_dec_done_reg_0; wire delay_dec_done_reg_1; wire delay_done_r3_reg_srl3_n_0; wire delaydec_cnt_r0; wire delaydec_cnt_r10_in; wire \delaydec_cnt_r[0]_i_1_n_0 ; wire \delaydec_cnt_r[1]_i_1_n_0 ; wire \delaydec_cnt_r[2]_i_1_n_0 ; wire \delaydec_cnt_r[3]_i_1_n_0 ; wire \delaydec_cnt_r[4]_i_1_n_0 ; wire \delaydec_cnt_r[5]_i_1_n_0 ; wire \delaydec_cnt_r[5]_i_3_n_0 ; wire [5:0]delaydec_cnt_r_reg__0; wire dqs_po_dec_done; wire dqs_wl_po_stg2_c_incdec; wire \init_state_r_reg[0] ; wire \mcGo_r_reg[15] ; wire p_1_in; wire p_3_in; wire pi_fine_dly_dec_done; wire po_cnt_dec; wire po_cnt_inc; wire po_cnt_inc_reg_0; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire po_en_stg2_f; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__9; wire wait_cnt_r0; wire [0:0]wait_cnt_r0__0; wire \wait_cnt_r[1]_i_1__0_n_0 ; wire \wait_cnt_r[2]_i_1__1_n_0 ; wire \wait_cnt_r[3]_i_1__0_n_0 ; wire \wait_cnt_r[3]_i_3__0_n_0 ; wire [0:0]\wait_cnt_r_reg[0]_0 ; wire \wait_cnt_r_reg[0]_1 ; wire \wait_cnt_r_reg[0]_2 ; wire [3:1]wait_cnt_r_reg__0__0; LUT6 #( .INIT(64'h00000000DE000000)) \ctl_lane_cnt[0]_i_1 (.I0(ctl_lane_cnt[0]), .I1(ctl_lane_cnt1), .I2(delaydec_cnt_r10_in), .I3(pi_fine_dly_dec_done), .I4(dqs_po_dec_done), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\ctl_lane_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000DEEE0000)) \ctl_lane_cnt[1]_i_1 (.I0(ctl_lane_cnt[1]), .I1(ctl_lane_cnt1), .I2(delaydec_cnt_r10_in), .I3(ctl_lane_cnt[0]), .I4(cmd_delay_start0), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\ctl_lane_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000006AAA)) \ctl_lane_cnt[2]_i_1 (.I0(ctl_lane_cnt[2]), .I1(delaydec_cnt_r10_in), .I2(ctl_lane_cnt[0]), .I3(ctl_lane_cnt[1]), .I4(p_1_in), .I5(ctl_lane_cnt1), .O(\ctl_lane_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair305" *) LUT4 #( .INIT(16'h0004)) \ctl_lane_cnt[2]_i_3 (.I0(\delay_cnt_r[0]_i_2_n_0 ), .I1(delaydec_cnt_r_reg__0[0]), .I2(delay_dec_done), .I3(\ctl_lane_cnt[2]_i_4_n_0 ), .O(ctl_lane_cnt1)); LUT5 #( .INIT(32'hFFFFFFFE)) \ctl_lane_cnt[2]_i_4 (.I0(delaydec_cnt_r_reg__0[4]), .I1(delaydec_cnt_r_reg__0[2]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[3]), .I4(delaydec_cnt_r_reg__0[5]), .O(\ctl_lane_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'h000000006AAAAAAA)) \ctl_lane_cnt[3]_i_1 (.I0(\ctl_lane_cnt_reg_n_0_[3] ), .I1(delaydec_cnt_r10_in), .I2(ctl_lane_cnt[2]), .I3(ctl_lane_cnt[1]), .I4(ctl_lane_cnt[0]), .I5(\ctl_lane_cnt[3]_i_3_n_0 ), .O(\ctl_lane_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000054555555)) \ctl_lane_cnt[3]_i_2 (.I0(delay_dec_done_reg_1), .I1(\ctl_lane_cnt_reg_n_0_[3] ), .I2(ctl_lane_cnt[2]), .I3(ctl_lane_cnt[1]), .I4(ctl_lane_cnt[0]), .I5(delay_dec_done_reg_0), .O(delaydec_cnt_r10_in)); LUT4 #( .INIT(16'hFFBF)) \ctl_lane_cnt[3]_i_3 (.I0(ctl_lane_cnt1), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\ctl_lane_cnt[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[0]_i_1_n_0 ), .Q(ctl_lane_cnt[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[1]_i_1_n_0 ), .Q(ctl_lane_cnt[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[2]_i_1_n_0 ), .Q(ctl_lane_cnt[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[3]_i_1_n_0 ), .Q(\ctl_lane_cnt_reg_n_0_[3] ), .R(1'b0)); LUT5 #( .INIT(32'hDDFFEEFC)) \delay_cnt_r[0]_i_1 (.I0(po_cnt_inc), .I1(delay_dec_done_reg_0), .I2(\delay_cnt_r[0]_i_2_n_0 ), .I3(delay_dec_done_reg_1), .I4(\delay_cnt_r_reg_n_0_[0] ), .O(\delay_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair302" *) LUT4 #( .INIT(16'hEFFF)) \delay_cnt_r[0]_i_2 (.I0(\ctl_lane_cnt_reg_n_0_[3] ), .I1(ctl_lane_cnt[2]), .I2(ctl_lane_cnt[1]), .I3(ctl_lane_cnt[0]), .O(\delay_cnt_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair307" *) LUT2 #( .INIT(4'h9)) \delay_cnt_r[1]_i_1 (.I0(\delay_cnt_r_reg_n_0_[0] ), .I1(\delay_cnt_r_reg_n_0_[1] ), .O(\delay_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair307" *) LUT3 #( .INIT(8'hE1)) \delay_cnt_r[2]_i_1 (.I0(\delay_cnt_r_reg_n_0_[1] ), .I1(\delay_cnt_r_reg_n_0_[0] ), .I2(\delay_cnt_r_reg_n_0_[2] ), .O(\delay_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair303" *) LUT4 #( .INIT(16'hFE01)) \delay_cnt_r[3]_i_1 (.I0(\delay_cnt_r_reg_n_0_[2] ), .I1(\delay_cnt_r_reg_n_0_[0] ), .I2(\delay_cnt_r_reg_n_0_[1] ), .I3(\delay_cnt_r_reg_n_0_[3] ), .O(\delay_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair303" *) LUT5 #( .INIT(32'hFFFE0001)) \delay_cnt_r[4]_i_1 (.I0(\delay_cnt_r_reg_n_0_[3] ), .I1(\delay_cnt_r_reg_n_0_[1] ), .I2(\delay_cnt_r_reg_n_0_[0] ), .I3(\delay_cnt_r_reg_n_0_[2] ), .I4(\delay_cnt_r_reg_n_0_[4] ), .O(\delay_cnt_r[4]_i_1_n_0 )); LUT3 #( .INIT(8'hFE)) \delay_cnt_r[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(delay_dec_done_reg_0), .I2(\delay_cnt_r[5]_i_5_n_0 ), .O(\delay_cnt_r[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \delay_cnt_r[5]_i_2 (.I0(delay_dec_done_reg_1), .I1(po_cnt_inc), .O(delay_cnt_r0)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \delay_cnt_r[5]_i_3 (.I0(\delay_cnt_r_reg_n_0_[4] ), .I1(\delay_cnt_r_reg_n_0_[2] ), .I2(\delay_cnt_r_reg_n_0_[0] ), .I3(\delay_cnt_r_reg_n_0_[1] ), .I4(\delay_cnt_r_reg_n_0_[3] ), .I5(\delay_cnt_r_reg_n_0_[5] ), .O(\delay_cnt_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \delay_cnt_r[5]_i_4 (.I0(delaydec_cnt_r_reg__0[5]), .I1(delaydec_cnt_r_reg__0[3]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[2]), .I4(delaydec_cnt_r_reg__0[4]), .I5(delaydec_cnt_r_reg__0[0]), .O(delay_dec_done_reg_0)); (* SOFT_HLUTNM = "soft_lutpair302" *) LUT5 #( .INIT(32'h0000FFF7)) \delay_cnt_r[5]_i_5 (.I0(ctl_lane_cnt[0]), .I1(ctl_lane_cnt[1]), .I2(ctl_lane_cnt[2]), .I3(\ctl_lane_cnt_reg_n_0_[3] ), .I4(delay_dec_done_reg_1), .O(\delay_cnt_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \delay_cnt_r[5]_i_6 (.I0(\delay_cnt_r_reg_n_0_[4] ), .I1(\delay_cnt_r_reg_n_0_[2] ), .I2(\delay_cnt_r_reg_n_0_[0] ), .I3(\delay_cnt_r_reg_n_0_[1] ), .I4(\delay_cnt_r_reg_n_0_[3] ), .I5(\delay_cnt_r_reg_n_0_[5] ), .O(delay_dec_done_reg_1)); FDRE #( .INIT(1'b0)) \delay_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\delay_cnt_r[0]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \delay_cnt_r_reg[1] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[1]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[1] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \delay_cnt_r_reg[2] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[2]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[2] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \delay_cnt_r_reg[3] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[3]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[3] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \delay_cnt_r_reg[4] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[4]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[4] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \delay_cnt_r_reg[5] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[5]_i_3_n_0 ), .Q(\delay_cnt_r_reg_n_0_[5] ), .R(\delay_cnt_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000AAAB0000)) delay_dec_done_i_1 (.I0(delay_dec_done), .I1(\delay_cnt_r[0]_i_2_n_0 ), .I2(delay_dec_done_reg_0), .I3(delay_dec_done_reg_1), .I4(cmd_delay_start0), .I5(rstdiv0_sync_r1_reg_rep__24), .O(delay_dec_done_i_1_n_0)); FDRE #( .INIT(1'b0)) delay_dec_done_reg (.C(CLK), .CE(1'b1), .D(delay_dec_done_i_1_n_0), .Q(delay_dec_done), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 " *) SRL16E #( .INIT(16'h0000)) delay_done_r3_reg_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(delay_dec_done), .Q(delay_done_r3_reg_srl3_n_0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) delay_done_r4_reg (.C(CLK), .CE(1'b1), .D(delay_done_r3_reg_srl3_n_0), .Q(ck_addr_cmd_delay_done), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair309" *) LUT1 #( .INIT(2'h1)) \delaydec_cnt_r[0]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .O(\delaydec_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair305" *) LUT2 #( .INIT(4'h9)) \delaydec_cnt_r[1]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[1]), .O(\delaydec_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair309" *) LUT3 #( .INIT(8'hE1)) \delaydec_cnt_r[2]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[1]), .I2(delaydec_cnt_r_reg__0[2]), .O(\delaydec_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair304" *) LUT4 #( .INIT(16'hFE01)) \delaydec_cnt_r[3]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[1]), .I2(delaydec_cnt_r_reg__0[2]), .I3(delaydec_cnt_r_reg__0[3]), .O(\delaydec_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair304" *) LUT5 #( .INIT(32'hFFFE0001)) \delaydec_cnt_r[4]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[2]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[3]), .I4(delaydec_cnt_r_reg__0[4]), .O(\delaydec_cnt_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'hFFBF)) \delaydec_cnt_r[5]_i_1 (.I0(delaydec_cnt_r10_in), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\delaydec_cnt_r[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \delaydec_cnt_r[5]_i_2 (.I0(delay_dec_done_reg_0), .I1(po_cnt_dec), .O(delaydec_cnt_r0)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \delaydec_cnt_r[5]_i_3 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[3]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[2]), .I4(delaydec_cnt_r_reg__0[4]), .I5(delaydec_cnt_r_reg__0[5]), .O(\delaydec_cnt_r[5]_i_3_n_0 )); FDSE #( .INIT(1'b1)) \delaydec_cnt_r_reg[0] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[0]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[0]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \delaydec_cnt_r_reg[1] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[1]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[1]), .R(\delaydec_cnt_r[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \delaydec_cnt_r_reg[2] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[2]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[2]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \delaydec_cnt_r_reg[3] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[3]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[3]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \delaydec_cnt_r_reg[4] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[4]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[4]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \delaydec_cnt_r_reg[5] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[5]_i_3_n_0 ), .Q(delaydec_cnt_r_reg__0[5]), .R(\delaydec_cnt_r[5]_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \init_state_r[0]_i_39 (.I0(ck_addr_cmd_delay_done), .I1(cnt_pwron_cke_done_r), .I2(\mcGo_r_reg[15] ), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h0000000008080800)) phaser_out_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(D_po_coarse_enable110_out)); LUT6 #( .INIT(64'h0000000001010100)) phaser_out_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8] )); LUT6 #( .INIT(64'h0000000004040400)) phaser_out_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_0 )); LUT6 #( .INIT(64'h0000000004040400)) phaser_out_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_1 )); LUT6 #( .INIT(64'h00000000EAEAEA00)) phaser_out_i_1__3 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_2 )); LUT6 #( .INIT(64'h00000000BABABA00)) phaser_out_i_1__4 (.I0(calib_in_common), .I1(Q[0]), .I2(Q[1]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_3 )); LUT6 #( .INIT(64'h00000000BABABA00)) phaser_out_i_1__5 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_4 )); LUT6 #( .INIT(64'h00000000ABABAB00)) phaser_out_i_1__6 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_5 )); FDRE #( .INIT(1'b0)) po_cnt_dec_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_r_reg[0]_2 ), .Q(po_cnt_dec), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair306" *) LUT3 #( .INIT(8'hFE)) po_cnt_inc_i_2 (.I0(wait_cnt_r_reg__0__0[2]), .I1(wait_cnt_r_reg__0__0[1]), .I2(wait_cnt_r_reg__0__0[3]), .O(po_cnt_inc_reg_0)); FDRE #( .INIT(1'b0)) po_cnt_inc_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_r_reg[0]_1 ), .Q(po_cnt_inc), .R(1'b0)); FDRE #( .INIT(1'b0)) po_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(po_cnt_dec), .Q(po_en_stg2_f), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) po_stg2_c_incdec_reg (.C(CLK), .CE(1'b1), .D(po_cnt_inc), .Q(p_3_in), .R(rstdiv0_sync_r1_reg_rep__9)); LUT1 #( .INIT(2'h1)) \wait_cnt_r[0]_i_1__0 (.I0(\wait_cnt_r_reg[0]_0 ), .O(wait_cnt_r0__0)); (* SOFT_HLUTNM = "soft_lutpair308" *) LUT2 #( .INIT(4'h9)) \wait_cnt_r[1]_i_1__0 (.I0(\wait_cnt_r_reg[0]_0 ), .I1(wait_cnt_r_reg__0__0[1]), .O(\wait_cnt_r[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair308" *) LUT3 #( .INIT(8'hE1)) \wait_cnt_r[2]_i_1__1 (.I0(wait_cnt_r_reg__0__0[1]), .I1(\wait_cnt_r_reg[0]_0 ), .I2(wait_cnt_r_reg__0__0[2]), .O(\wait_cnt_r[2]_i_1__1_n_0 )); LUT3 #( .INIT(8'hFE)) \wait_cnt_r[3]_i_1__0 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(po_cnt_dec), .I2(po_cnt_inc), .O(\wait_cnt_r[3]_i_1__0_n_0 )); LUT6 #( .INIT(64'hC0C0C0C0C0C0C080)) \wait_cnt_r[3]_i_2__0 (.I0(\wait_cnt_r_reg[0]_0 ), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(wait_cnt_r_reg__0__0[2]), .I4(wait_cnt_r_reg__0__0[1]), .I5(wait_cnt_r_reg__0__0[3]), .O(wait_cnt_r0)); (* SOFT_HLUTNM = "soft_lutpair306" *) LUT4 #( .INIT(16'hFE01)) \wait_cnt_r[3]_i_3__0 (.I0(\wait_cnt_r_reg[0]_0 ), .I1(wait_cnt_r_reg__0__0[1]), .I2(wait_cnt_r_reg__0__0[2]), .I3(wait_cnt_r_reg__0__0[3]), .O(\wait_cnt_r[3]_i_3__0_n_0 )); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[0] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0), .Q(\wait_cnt_r_reg[0]_0 ), .R(\wait_cnt_r[3]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[1] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[1]_i_1__0_n_0 ), .Q(wait_cnt_r_reg__0__0[1]), .R(\wait_cnt_r[3]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[2] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[2]_i_1__1_n_0 ), .Q(wait_cnt_r_reg__0__0[2]), .R(\wait_cnt_r[3]_i_1__0_n_0 )); FDSE #( .INIT(1'b1)) \wait_cnt_r_reg[3] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[3]_i_3__0_n_0 ), .Q(wait_cnt_r_reg__0__0[3]), .S(\wait_cnt_r[3]_i_1__0_n_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_dqs_found_cal" *) module ddr3_ifmig_7series_v4_0_ddr_phy_dqs_found_cal (init_dqsfound_done_r2, init_dqsfound_done_r5, out, pi_dqs_found_any_bank, pi_dqs_found_rank_done, rd_data_offset_cal_done, rst_dqs_find_r1_reg_0, pi_dqs_found_done_r1_reg, \pi_rst_stg1_cal_r_reg[0]_0 , fine_adjust_done_r_reg_0, init_dec_done_reg_0, final_dec_done_reg_0, dqs_found_prech_req, ck_po_stg2_f_indec, ck_po_stg2_f_en, \pi_dqs_found_all_bank_r_reg[1]_0 , D_po_fine_enable107_out, D_po_fine_inc113_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \gen_byte_sel_div1.calib_in_common_reg , \po_counter_read_val_reg[8]_5 , \po_counter_read_val_reg[8]_6 , ififo_rst_reg, \po_counter_read_val_reg[8]_7 , \po_counter_read_val_reg[8]_8 , ififo_rst_reg_0, \po_counter_read_val_reg[8]_9 , \po_counter_read_val_reg[8]_10 , ififo_rst_reg_1, \po_counter_read_val_reg[8]_11 , \po_counter_read_val_reg[8]_12 , ififo_rst_reg_2, fine_adj_state_r144_out, \FSM_sequential_fine_adj_state_r_reg[2]_0 , \dec_cnt_reg[0]_0 , \FSM_sequential_fine_adj_state_r_reg[0]_0 , \rd_byte_data_offset_reg[0][9]_0 , \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[5] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \rd_byte_data_offset_reg[0]_3 , p_1_in27_in, \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 , p_1_in50_in, \pi_rst_stg1_cal_r_reg[0]_1 , fine_adj_state_r16_out, dqs_found_prech_req_reg_0, final_dec_done_reg_1, \FSM_sequential_fine_adj_state_r_reg[0]_1 , \rank_final_loop[0].final_do_max_reg[0][3]_0 , \rank_final_loop[0].final_do_max_reg[0][3]_1 , \init_state_r_reg[1] , \init_state_r_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \init_state_r_reg[1]_0 , \init_state_r_reg[1]_1 , \calib_data_offset_0_reg[5] , \calib_data_offset_0_reg[4] , \calib_data_offset_0_reg[1] , \calib_data_offset_0_reg[0] , \calib_data_offset_1_reg[5] , \calib_data_offset_1_reg[4] , \calib_data_offset_1_reg[1] , \calib_data_offset_1_reg[0] , \gen_byte_sel_div1.ctl_lane_sel_reg[0] , ctl_lane_sel, \gen_byte_sel_div1.ctl_lane_sel_reg[1] , \gen_byte_sel_div1.ctl_lane_sel_reg[2] , \calib_zero_inputs_reg[1] , D, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[0] , rank_done_r_reg_0, rst_dqs_find_reg_0, dqs_found_prech_req_reg_1, rst_dqs_find_reg_1, init_dec_done_reg_1, rst_dqs_find, CLK, in0, pi_dqs_found_start_reg, rstdiv0_sync_r1_reg_rep__12, SR, rstdiv0_sync_r1_reg_rep__13, \pi_dqs_found_lanes_r3_reg[3]_0 , \pi_dqs_found_all_bank_r_reg[1]_1 , init_dqsfound_done_r_reg_0, \FSM_sequential_fine_adj_state_r_reg[0]_2 , \FSM_sequential_fine_adj_state_r_reg[1]_0 , \FSM_sequential_fine_adj_state_r_reg[0]_3 , init_dec_done_reg_2, \FSM_sequential_fine_adj_state_r_reg[1]_1 , \FSM_sequential_fine_adj_state_r_reg[2]_1 , \FSM_sequential_fine_adj_state_r_reg[1]_2 , \FSM_sequential_fine_adj_state_r_reg[1]_3 , pi_dqs_found_start_reg_0, Q, calib_in_common, po_enstg2_f, \calib_zero_inputs_reg[1]_0 , po_stg2_fincdec, pi_calib_done, oclkdelay_calib_done_r_reg, pi_f_inc_reg, \gen_byte_sel_div1.calib_in_common_reg_0 , dqs_po_stg2_f_incdec, po_stg23_incdec, dqs_po_en_stg2_f, po_en_stg2_f, po_en_stg23, \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , \gen_byte_sel_div1.calib_in_common_reg_3 , wrcal_done_reg, rdlvl_stg1_done_int_reg, prbs_rdlvl_done_reg_rep, rstdiv0_sync_r1_reg_rep__23, detect_pi_found_dqs, \num_refresh_reg[1] , oclkdelay_calib_done_r_reg_0, mpr_rdlvl_done_r_reg, cnt_cmd_done_r, prbs_last_byte_done_r, wrlvl_byte_redo, wrlvl_done_r1, oclkdelay_center_calib_done_r_reg, wrlvl_final_mux, pi_dqs_found_done_r1, ck_addr_cmd_delay_done, ctl_lane_cnt, \gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 , \gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 , \gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 , pi_fine_dly_dec_done, dqs_po_dec_done, tempmon_sel_pi_incdec, byte_sel_cnt, \gen_byte_sel_div1.byte_sel_cnt_reg[1] , init_calib_complete_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 , cmd_delay_start0, rstdiv0_sync_r1_reg_rep__24, fine_adjust_reg_0, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__19, prech_done); output init_dqsfound_done_r2; output init_dqsfound_done_r5; output [3:0]out; output [0:0]pi_dqs_found_any_bank; output pi_dqs_found_rank_done; output rd_data_offset_cal_done; output rst_dqs_find_r1_reg_0; output pi_dqs_found_done_r1_reg; output \pi_rst_stg1_cal_r_reg[0]_0 ; output fine_adjust_done_r_reg_0; output init_dec_done_reg_0; output final_dec_done_reg_0; output dqs_found_prech_req; output ck_po_stg2_f_indec; output ck_po_stg2_f_en; output [0:0]\pi_dqs_found_all_bank_r_reg[1]_0 ; output D_po_fine_enable107_out; output D_po_fine_inc113_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \gen_byte_sel_div1.calib_in_common_reg ; output \po_counter_read_val_reg[8]_5 ; output \po_counter_read_val_reg[8]_6 ; output ififo_rst_reg; output \po_counter_read_val_reg[8]_7 ; output \po_counter_read_val_reg[8]_8 ; output ififo_rst_reg_0; output \po_counter_read_val_reg[8]_9 ; output \po_counter_read_val_reg[8]_10 ; output ififo_rst_reg_1; output \po_counter_read_val_reg[8]_11 ; output \po_counter_read_val_reg[8]_12 ; output ififo_rst_reg_2; output fine_adj_state_r144_out; output \FSM_sequential_fine_adj_state_r_reg[2]_0 ; output \dec_cnt_reg[0]_0 ; output [3:0]\FSM_sequential_fine_adj_state_r_reg[0]_0 ; output [1:0]\rd_byte_data_offset_reg[0][9]_0 ; output \cmd_pipe_plus.mc_data_offset_reg[4] ; output [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; output \cmd_pipe_plus.mc_data_offset_reg[1] ; output \cmd_pipe_plus.mc_data_offset_1_reg[4] ; output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; output \cmd_pipe_plus.mc_data_offset_1_reg[1] ; output \cmd_pipe_plus.mc_data_offset_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \rd_byte_data_offset_reg[0]_3 ; output p_1_in27_in; output [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ; output p_1_in50_in; output \pi_rst_stg1_cal_r_reg[0]_1 ; output fine_adj_state_r16_out; output dqs_found_prech_req_reg_0; output final_dec_done_reg_1; output \FSM_sequential_fine_adj_state_r_reg[0]_1 ; output [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_0 ; output [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_1 ; output \init_state_r_reg[1] ; output \init_state_r_reg[2] ; output \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; output \init_state_r_reg[1]_0 ; output \init_state_r_reg[1]_1 ; output \calib_data_offset_0_reg[5] ; output \calib_data_offset_0_reg[4] ; output \calib_data_offset_0_reg[1] ; output \calib_data_offset_0_reg[0] ; output \calib_data_offset_1_reg[5] ; output \calib_data_offset_1_reg[4] ; output \calib_data_offset_1_reg[1] ; output \calib_data_offset_1_reg[0] ; output \gen_byte_sel_div1.ctl_lane_sel_reg[0] ; output ctl_lane_sel; output \gen_byte_sel_div1.ctl_lane_sel_reg[1] ; output \gen_byte_sel_div1.ctl_lane_sel_reg[2] ; output \calib_zero_inputs_reg[1] ; output [1:0]D; output [0:0]\calib_zero_inputs_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output [1:0]rank_done_r_reg_0; output rst_dqs_find_reg_0; output dqs_found_prech_req_reg_1; output rst_dqs_find_reg_1; output init_dec_done_reg_1; output rst_dqs_find; input CLK; input [3:0]in0; input pi_dqs_found_start_reg; input [0:0]rstdiv0_sync_r1_reg_rep__12; input [0:0]SR; input rstdiv0_sync_r1_reg_rep__13; input \pi_dqs_found_lanes_r3_reg[3]_0 ; input \pi_dqs_found_all_bank_r_reg[1]_1 ; input init_dqsfound_done_r_reg_0; input \FSM_sequential_fine_adj_state_r_reg[0]_2 ; input \FSM_sequential_fine_adj_state_r_reg[1]_0 ; input \FSM_sequential_fine_adj_state_r_reg[0]_3 ; input init_dec_done_reg_2; input \FSM_sequential_fine_adj_state_r_reg[1]_1 ; input \FSM_sequential_fine_adj_state_r_reg[2]_1 ; input \FSM_sequential_fine_adj_state_r_reg[1]_2 ; input \FSM_sequential_fine_adj_state_r_reg[1]_3 ; input pi_dqs_found_start_reg_0; input [1:0]Q; input calib_in_common; input [0:0]po_enstg2_f; input [1:0]\calib_zero_inputs_reg[1]_0 ; input [0:0]po_stg2_fincdec; input pi_calib_done; input oclkdelay_calib_done_r_reg; input pi_f_inc_reg; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input dqs_po_stg2_f_incdec; input po_stg23_incdec; input dqs_po_en_stg2_f; input po_en_stg2_f; input po_en_stg23; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input wrcal_done_reg; input rdlvl_stg1_done_int_reg; input prbs_rdlvl_done_reg_rep; input rstdiv0_sync_r1_reg_rep__23; input detect_pi_found_dqs; input \num_refresh_reg[1] ; input oclkdelay_calib_done_r_reg_0; input mpr_rdlvl_done_r_reg; input cnt_cmd_done_r; input prbs_last_byte_done_r; input wrlvl_byte_redo; input wrlvl_done_r1; input oclkdelay_center_calib_done_r_reg; input wrlvl_final_mux; input pi_dqs_found_done_r1; input ck_addr_cmd_delay_done; input [2:0]ctl_lane_cnt; input \gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ; input \gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ; input \gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ; input pi_fine_dly_dec_done; input dqs_po_dec_done; input tempmon_sel_pi_incdec; input [0:0]byte_sel_cnt; input \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; input init_calib_complete_reg; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; input cmd_delay_start0; input rstdiv0_sync_r1_reg_rep__24; input fine_adjust_reg_0; input rstdiv0_sync_r1_reg_rep__2; input [0:0]rstdiv0_sync_r1_reg_rep__19; input prech_done; wire CLK; wire [1:0]D; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire \FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ; wire \FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ; wire \FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ; wire \FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ; (* RTL_KEEP = "yes" *) wire [3:0]\FSM_sequential_fine_adj_state_r_reg[0]_0 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_1 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_2 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_3 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_0 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_1 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_2 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_3 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r_reg[2]_0 ; wire \FSM_sequential_fine_adj_state_r_reg[2]_1 ; wire [1:0]Q; wire [0:0]SR; wire [0:0]byte_sel_cnt; wire \calib_data_offset_0_reg[0] ; wire \calib_data_offset_0_reg[1] ; wire \calib_data_offset_0_reg[4] ; wire \calib_data_offset_0_reg[5] ; wire \calib_data_offset_1_reg[0] ; wire \calib_data_offset_1_reg[1] ; wire \calib_data_offset_1_reg[4] ; wire \calib_data_offset_1_reg[5] ; wire calib_in_common; wire [0:0]\calib_zero_inputs_reg[0] ; wire \calib_zero_inputs_reg[1] ; wire [1:0]\calib_zero_inputs_reg[1]_0 ; wire ck_addr_cmd_delay_done; wire ck_po_stg2_f_en; wire ck_po_stg2_f_indec; wire cmd_delay_start0; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; wire cnt_cmd_done_r; wire [2:0]ctl_lane_cnt; wire ctl_lane_cnt_0; wire [3:0]ctl_lane_cnt__0; wire \ctl_lane_cnt_reg_n_0_[3] ; wire ctl_lane_sel; wire [5:0]dec_cnt; wire \dec_cnt[0]_i_2_n_0 ; wire \dec_cnt[0]_i_4_n_0 ; wire \dec_cnt[0]_i_5_n_0 ; wire \dec_cnt[0]_i_6_n_0 ; wire \dec_cnt[0]_i_7_n_0 ; wire \dec_cnt[1]_i_2_n_0 ; wire \dec_cnt[1]_i_3_n_0 ; wire \dec_cnt[1]_i_4_n_0 ; wire \dec_cnt[2]_i_2_n_0 ; wire \dec_cnt[2]_i_3_n_0 ; wire \dec_cnt[2]_i_4_n_0 ; wire \dec_cnt[3]_i_2_n_0 ; wire \dec_cnt[3]_i_3_n_0 ; wire \dec_cnt[3]_i_4_n_0 ; wire \dec_cnt[4]_i_2_n_0 ; wire \dec_cnt[4]_i_3_n_0 ; wire \dec_cnt[4]_i_5_n_0 ; wire \dec_cnt[4]_i_6_n_0 ; wire \dec_cnt[4]_i_7_n_0 ; wire \dec_cnt[5]_i_10_n_0 ; wire \dec_cnt[5]_i_1_n_0 ; wire \dec_cnt[5]_i_3_n_0 ; wire \dec_cnt[5]_i_4_n_0 ; wire \dec_cnt[5]_i_6_n_0 ; wire \dec_cnt[5]_i_7_n_0 ; wire \dec_cnt[5]_i_8_n_0 ; wire \dec_cnt[5]_i_9_n_0 ; wire \dec_cnt_reg[0]_0 ; wire \dec_cnt_reg[0]_i_3_n_0 ; wire \dec_cnt_reg[0]_i_3_n_1 ; wire \dec_cnt_reg[0]_i_3_n_2 ; wire \dec_cnt_reg[0]_i_3_n_3 ; wire \dec_cnt_reg[0]_i_3_n_4 ; wire \dec_cnt_reg[0]_i_3_n_5 ; wire \dec_cnt_reg[0]_i_3_n_6 ; wire \dec_cnt_reg[4]_i_4_n_3 ; wire \dec_cnt_reg[4]_i_4_n_6 ; wire \dec_cnt_reg[4]_i_4_n_7 ; wire \dec_cnt_reg_n_0_[0] ; wire \dec_cnt_reg_n_0_[1] ; wire \dec_cnt_reg_n_0_[2] ; wire \dec_cnt_reg_n_0_[3] ; wire \dec_cnt_reg_n_0_[4] ; wire \dec_cnt_reg_n_0_[5] ; wire detect_pi_found_dqs; wire detect_rd_cnt0; wire [3:0]detect_rd_cnt0__0; wire \detect_rd_cnt[1]_i_1_n_0 ; wire \detect_rd_cnt[3]_i_1_n_0 ; wire [3:0]detect_rd_cnt_reg__0; wire dqs_found_done_r0; wire dqs_found_done_r_i_3_n_0; wire dqs_found_prech_req; wire dqs_found_prech_req_i_5_n_0; wire dqs_found_prech_req_reg_0; wire dqs_found_prech_req_reg_1; wire dqs_found_start_r; wire dqs_po_dec_done; wire dqs_po_en_stg2_f; wire dqs_po_stg2_f_incdec; wire final_data_offset; wire final_data_offset_mc; wire final_dec_done_reg_0; wire final_dec_done_reg_1; wire fine_adj_state_r110_out; wire fine_adj_state_r134_out; wire fine_adj_state_r141_out; wire fine_adj_state_r144_out; wire fine_adj_state_r167_out; wire fine_adj_state_r16_out; wire fine_adj_state_r17_out; wire fine_adjust_done_r_reg_0; wire [2:0]fine_adjust_lane_cnt; wire fine_adjust_reg_0; wire first_fail_detect; wire first_fail_detect_i_1_n_0; wire first_fail_detect_i_2_n_0; wire first_fail_detect_reg_n_0; wire \first_fail_taps[0]_i_1_n_0 ; wire \first_fail_taps[1]_i_1_n_0 ; wire \first_fail_taps[2]_i_1_n_0 ; wire \first_fail_taps[3]_i_1_n_0 ; wire \first_fail_taps[4]_i_1_n_0 ; wire \first_fail_taps[5]_i_2_n_0 ; wire \first_fail_taps[5]_i_4_n_0 ; wire \first_fail_taps[5]_i_5_n_0 ; wire \first_fail_taps[5]_i_6_n_0 ; wire \first_fail_taps[5]_i_7_n_0 ; wire \first_fail_taps_reg_n_0_[0] ; wire \first_fail_taps_reg_n_0_[1] ; wire \first_fail_taps_reg_n_0_[2] ; wire \first_fail_taps_reg_n_0_[3] ; wire \first_fail_taps_reg_n_0_[4] ; wire \first_fail_taps_reg_n_0_[5] ; wire \gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.calib_in_common_i_2_n_0 ; wire \gen_byte_sel_div1.calib_in_common_i_5_n_0 ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[0] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[1] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[2] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire ififo_rst_reg; wire ififo_rst_reg_0; wire ififo_rst_reg_1; wire ififo_rst_reg_2; wire [3:0]in0; wire inc_cnt; wire \inc_cnt[4]_i_1_n_0 ; wire \inc_cnt_reg_n_0_[0] ; wire \inc_cnt_reg_n_0_[1] ; wire \inc_cnt_reg_n_0_[2] ; wire \inc_cnt_reg_n_0_[3] ; wire \inc_cnt_reg_n_0_[4] ; wire \inc_cnt_reg_n_0_[5] ; wire init_calib_complete_reg; wire init_dec_cnt; wire [5:0]init_dec_cnt0; wire \init_dec_cnt[1]_i_1_n_0 ; wire [5:0]init_dec_cnt_reg__0; wire init_dec_done_reg_0; wire init_dec_done_reg_1; wire init_dec_done_reg_2; wire init_dqsfound_done_r1_reg_n_0; wire init_dqsfound_done_r2; wire init_dqsfound_done_r4_reg_srl2_n_0; wire init_dqsfound_done_r5; wire init_dqsfound_done_r_reg_0; wire \init_state_r[1]_i_29_n_0 ; wire \init_state_r[1]_i_30_n_0 ; wire \init_state_r_reg[1] ; wire \init_state_r_reg[1]_0 ; wire \init_state_r_reg[1]_1 ; wire \init_state_r_reg[2] ; wire mpr_rdlvl_done_r_reg; wire n_0_0; wire n_0_1; wire n_0_2; wire n_0_3; wire \num_refresh_reg[1] ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_center_calib_done_r_reg; wire [5:0]p_0_in; wire p_0_in19_in; wire [5:0]p_0_in__0; wire [4:0]p_0_in__1; wire [5:0]p_1_in; wire p_1_in27_in; wire p_1_in50_in; wire p_22_out; wire pi_calib_done; wire [0:0]pi_dqs_found_all_bank; wire \pi_dqs_found_all_bank[0]_i_1_n_0 ; wire [0:0]\pi_dqs_found_all_bank_r_reg[1]_0 ; wire \pi_dqs_found_all_bank_r_reg[1]_1 ; wire [0:0]pi_dqs_found_any_bank; wire \pi_dqs_found_any_bank_r_reg_n_0_[0] ; wire pi_dqs_found_done_r1; wire pi_dqs_found_done_r1_reg; (* async_reg = "true" *) wire [7:0]pi_dqs_found_lanes_r1; (* async_reg = "true" *) wire [7:0]pi_dqs_found_lanes_r2; (* async_reg = "true" *) wire [7:0]pi_dqs_found_lanes_r3; wire \pi_dqs_found_lanes_r3_reg[3]_0 ; wire pi_dqs_found_rank_done; wire pi_dqs_found_start_reg; wire pi_dqs_found_start_reg_0; wire pi_f_inc_reg; wire pi_fine_dly_dec_done; wire \pi_rst_stg1_cal[0]_i_1_n_0 ; wire \pi_rst_stg1_cal[1]_i_1_n_0 ; wire pi_rst_stg1_cal_r1_reg0; wire pi_rst_stg1_cal_r1_reg017_out; wire \pi_rst_stg1_cal_r1_reg_n_0_[0] ; wire \pi_rst_stg1_cal_r[0]_i_1_n_0 ; wire \pi_rst_stg1_cal_r[0]_i_2_n_0 ; wire \pi_rst_stg1_cal_r[0]_i_3_n_0 ; wire \pi_rst_stg1_cal_r[1]_i_1_n_0 ; wire \pi_rst_stg1_cal_r[1]_i_2_n_0 ; wire \pi_rst_stg1_cal_r_reg[0]_0 ; wire \pi_rst_stg1_cal_r_reg[0]_1 ; wire \pi_rst_stg1_cal_reg_n_0_[1] ; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_10 ; wire \po_counter_read_val_reg[8]_11 ; wire \po_counter_read_val_reg[8]_12 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire \po_counter_read_val_reg[8]_6 ; wire \po_counter_read_val_reg[8]_7 ; wire \po_counter_read_val_reg[8]_8 ; wire \po_counter_read_val_reg[8]_9 ; wire po_en_stg23; wire po_en_stg2_f; wire [0:0]po_enstg2_f; wire po_stg23_incdec; wire [0:0]po_stg2_fincdec; wire prbs_last_byte_done_r; wire prbs_rdlvl_done_reg_rep; wire prech_done; wire rank_done_r1; wire [1:0]rank_done_r_reg_0; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ; wire [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index_reg_n_0_[0][0] ; wire \rank_final_loop[0].final_do_index_reg_n_0_[0][1] ; wire \rank_final_loop[0].final_do_index_reg_n_0_[0][2] ; wire \rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ; wire \rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ; wire \rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ; wire [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_0 ; wire [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_1 ; wire [5:0]\rank_final_loop[0].final_do_max_reg[0]__0 ; wire rd_byte_data_offset; wire \rd_byte_data_offset[0][11]_i_1_n_0 ; wire \rd_byte_data_offset[0][11]_i_2_n_0 ; wire \rd_byte_data_offset[0][11]_i_4_n_0 ; wire \rd_byte_data_offset[0][5]_i_1_n_0 ; wire \rd_byte_data_offset[0][5]_i_3_n_0 ; wire \rd_byte_data_offset[0][5]_i_4_n_0 ; wire \rd_byte_data_offset[0][7]_i_1_n_0 ; wire [1:0]\rd_byte_data_offset_reg[0][9]_0 ; wire \rd_byte_data_offset_reg[0]_3 ; wire \rd_byte_data_offset_reg_n_0_[0][0] ; wire \rd_byte_data_offset_reg_n_0_[0][1] ; wire \rd_byte_data_offset_reg_n_0_[0][4] ; wire \rd_byte_data_offset_reg_n_0_[0][5] ; wire rd_data_offset_cal_done; wire [5:0]rd_data_offset_ranks_0; wire [5:0]rd_data_offset_ranks_1; wire rdlvl_stg1_done_int_reg; wire \rnk_cnt_r[0]_i_1_n_0 ; wire \rnk_cnt_r[1]_i_1_n_0 ; wire \rnk_cnt_r_reg_n_0_[0] ; wire \rnk_cnt_r_reg_n_0_[1] ; wire rst_dqs_find; wire rst_dqs_find_i_5_n_0; wire rst_dqs_find_i_6_n_0; wire rst_dqs_find_r1; wire rst_dqs_find_r1_reg_0; wire rst_dqs_find_r2; wire rst_dqs_find_reg_0; wire rst_dqs_find_reg_1; wire [0:0]rst_stg1_cal; wire [0:0]rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire stable_pass_cnt; wire \stable_pass_cnt[3]_i_1_n_0 ; wire \stable_pass_cnt[5]_i_2_n_0 ; wire \stable_pass_cnt[5]_i_3_n_0 ; wire [5:1]stable_pass_cnt_reg__0; wire \stable_pass_cnt_reg_n_0_[0] ; wire tempmon_sel_pi_incdec; wire wrcal_done_reg; wire wrlvl_byte_redo; wire wrlvl_done_r1; wire wrlvl_final_mux; wire [0:0]\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED ; wire [3:1]\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED ; wire [3:2]\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED ; assign out[3:0] = pi_dqs_found_lanes_r3[3:0]; LUT6 #( .INIT(64'hF3B0FFFFF3B00000)) \FSM_sequential_fine_adj_state_r[0]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ), .O(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair270" *) LUT4 #( .INIT(16'h0008)) \FSM_sequential_fine_adj_state_r[0]_i_2 (.I0(fine_adjust_lane_cnt[1]), .I1(fine_adjust_lane_cnt[0]), .I2(\ctl_lane_cnt_reg_n_0_[3] ), .I3(fine_adjust_lane_cnt[2]), .O(\FSM_sequential_fine_adj_state_r_reg[0]_1 )); LUT5 #( .INIT(32'hA8AAFFFF)) \FSM_sequential_fine_adj_state_r[0]_i_4 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I1(\dec_cnt_reg[0]_0 ), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 )); LUT5 #( .INIT(32'hCCCC7477)) \FSM_sequential_fine_adj_state_r[0]_i_5 (.I0(fine_adj_state_r167_out), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(final_dec_done_reg_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFAFF0AFF030F030)) \FSM_sequential_fine_adj_state_r[1]_i_2 (.I0(fine_adj_state_r167_out), .I1(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FFEA00EA)) \FSM_sequential_fine_adj_state_r[1]_i_3 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I1(pi_dqs_found_all_bank), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair267" *) LUT5 #( .INIT(32'h00000040)) \FSM_sequential_fine_adj_state_r[1]_i_4 (.I0(detect_rd_cnt_reg__0[1]), .I1(detect_rd_cnt_reg__0[0]), .I2(detect_pi_found_dqs), .I3(detect_rd_cnt_reg__0[2]), .I4(detect_rd_cnt_reg__0[3]), .O(fine_adj_state_r167_out)); LUT6 #( .INIT(64'h0000000000001000)) \FSM_sequential_fine_adj_state_r[1]_i_5 (.I0(fine_adjust_lane_cnt[2]), .I1(\ctl_lane_cnt_reg_n_0_[3] ), .I2(fine_adjust_lane_cnt[0]), .I3(fine_adjust_lane_cnt[1]), .I4(\dec_cnt_reg[0]_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .O(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h0033CCBB33FFFC00)) \FSM_sequential_fine_adj_state_r[2]_i_1 (.I0(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hC8FF40FF88FF0000)) \FSM_sequential_fine_adj_state_r[2]_i_2 (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I1(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ), .I2(fine_adj_state_r134_out), .I3(fine_adj_state_r144_out), .I4(fine_adj_state_r110_out), .I5(fine_adj_state_r17_out), .O(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 )); LUT3 #( .INIT(8'h8F)) \FSM_sequential_fine_adj_state_r[2]_i_3 (.I0(\first_fail_taps[5]_i_5_n_0 ), .I1(\first_fail_taps[5]_i_7_n_0 ), .I2(first_fail_detect_reg_n_0), .O(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 )); LUT3 #( .INIT(8'h54)) \FSM_sequential_fine_adj_state_r[2]_i_4 (.I0(fine_adj_state_r141_out), .I1(first_fail_detect_i_2_n_0), .I2(first_fail_detect_reg_n_0), .O(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 )); LUT5 #( .INIT(32'h0000BF00)) \FSM_sequential_fine_adj_state_r[2]_i_5 (.I0(\first_fail_taps[5]_i_6_n_0 ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[4] ), .I3(\first_fail_taps[5]_i_5_n_0 ), .I4(\first_fail_taps[5]_i_7_n_0 ), .O(fine_adj_state_r134_out)); LUT6 #( .INIT(64'h0000000000101000)) \FSM_sequential_fine_adj_state_r[2]_i_6 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[3] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[5] ), .O(fine_adj_state_r110_out)); LUT6 #( .INIT(64'h0000008000000028)) \FSM_sequential_fine_adj_state_r[2]_i_7 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[4] ), .I2(\inc_cnt_reg_n_0_[2] ), .I3(\inc_cnt_reg_n_0_[0] ), .I4(\inc_cnt_reg_n_0_[1] ), .I5(\inc_cnt_reg_n_0_[3] ), .O(fine_adj_state_r17_out)); LUT5 #( .INIT(32'hB8FFB800)) \FSM_sequential_fine_adj_state_r[3]_i_1 (.I0(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I4(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ), .O(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h33BBFF88CC003000)) \FSM_sequential_fine_adj_state_r[3]_i_2 (.I0(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hBFBFBFBFFFFCFCFC)) \FSM_sequential_fine_adj_state_r[3]_i_3 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(pi_dqs_found_all_bank), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'hBFBFBFBFCFCCCCCC)) \FSM_sequential_fine_adj_state_r[3]_i_4 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(pi_dqs_found_all_bank), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFF4FFFFFFF40)) \FSM_sequential_fine_adj_state_r[3]_i_5 (.I0(pi_dqs_found_any_bank), .I1(rst_dqs_find_r2), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(init_dqsfound_done_r5), .O(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 )); LUT5 #( .INIT(32'h0000FD0D)) \FSM_sequential_fine_adj_state_r[3]_i_6 (.I0(first_fail_detect_i_2_n_0), .I1(fine_adj_state_r16_out), .I2(fine_adj_state_r144_out), .I3(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_fine_adj_state_r[3]_i_7 (.I0(init_dec_cnt_reg__0[5]), .I1(init_dec_cnt_reg__0[3]), .I2(init_dec_cnt_reg__0[0]), .I3(init_dec_cnt_reg__0[1]), .I4(init_dec_cnt_reg__0[2]), .I5(init_dec_cnt_reg__0[4]), .O(\FSM_sequential_fine_adj_state_r_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFB8FFFFFFBB)) \FSM_sequential_fine_adj_state_r[3]_i_8 (.I0(fine_adj_state_r110_out), .I1(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I2(fine_adj_state_r17_out), .I3(fine_adj_state_r141_out), .I4(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ), .I5(fine_adj_state_r134_out), .O(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 )); LUT2 #( .INIT(4'h1)) \FSM_sequential_fine_adj_state_r[3]_i_9 (.I0(first_fail_detect_reg_n_0), .I1(first_fail_detect_i_2_n_0), .O(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 )); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_fine_adj_state_r_reg[0] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_fine_adj_state_r_reg[0]_i_3 (.I0(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ), .I1(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ), .O(\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ), .S(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0])); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_fine_adj_state_r_reg[1] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_fine_adj_state_r_reg[1]_i_1 (.I0(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ), .I1(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ), .O(\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ), .S(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1])); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_fine_adj_state_r_reg[2] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__19)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_fine_adj_state_r_reg[3] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .R(rstdiv0_sync_r1_reg_rep__19)); (* SOFT_HLUTNM = "soft_lutpair293" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[0]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[0]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\calib_data_offset_0_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair292" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[1]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[1]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][1] ), .O(\calib_data_offset_0_reg[1] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[4]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[4]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][4] ), .O(\calib_data_offset_0_reg[4] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[5]_i_2 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[5]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][5] ), .O(\calib_data_offset_0_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair291" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[0]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[0]), .I2(init_dqsfound_done_r2), .I3(p_0_in[0]), .O(\calib_data_offset_1_reg[0] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[1]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[1]), .I2(init_dqsfound_done_r2), .I3(p_0_in[1]), .O(\calib_data_offset_1_reg[1] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[4]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[4]), .I2(init_dqsfound_done_r2), .I3(p_0_in[4]), .O(\calib_data_offset_1_reg[4] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[5]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[5]), .I2(init_dqsfound_done_r2), .I3(p_0_in[5]), .O(\calib_data_offset_1_reg[5] )); LUT6 #( .INIT(64'h4040404F00000000)) \calib_sel[0]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ), .I1(\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ), .I2(ctl_lane_sel), .I3(byte_sel_cnt), .I4(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ), .I5(init_calib_complete_reg), .O(D[0])); LUT6 #( .INIT(64'h4040404F00000000)) \calib_sel[1]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ), .I1(\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ), .I2(ctl_lane_sel), .I3(byte_sel_cnt), .I4(\gen_byte_sel_div1.byte_sel_cnt_reg[1] ), .I5(init_calib_complete_reg), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair275" *) LUT5 #( .INIT(32'h08008888)) \calib_sel[3]_i_2 (.I0(dqs_po_dec_done), .I1(pi_fine_dly_dec_done), .I2(fine_adjust_done_r_reg_0), .I3(rd_data_offset_cal_done), .I4(ck_addr_cmd_delay_done), .O(ctl_lane_sel)); (* SOFT_HLUTNM = "soft_lutpair285" *) LUT4 #( .INIT(16'h10FF)) \calib_zero_inputs[0]_i_1 (.I0(rst_stg1_cal), .I1(\pi_rst_stg1_cal_reg_n_0_[1] ), .I2(ctl_lane_sel), .I3(init_calib_complete_reg), .O(\calib_zero_inputs_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair275" *) LUT3 #( .INIT(8'hA2)) \calib_zero_inputs[1]_i_2 (.I0(ck_addr_cmd_delay_done), .I1(rd_data_offset_cal_done), .I2(fine_adjust_done_r_reg_0), .O(\calib_zero_inputs_reg[1] )); FDRE #( .INIT(1'b0)) ck_po_stg2_f_en_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_3 ), .Q(ck_po_stg2_f_en), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) ck_po_stg2_f_indec_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_2 ), .Q(ck_po_stg2_f_indec), .R(rstdiv0_sync_r1_reg_rep__12)); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_data_offset[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .O(\cmd_pipe_plus.mc_data_offset_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair272" *) LUT2 #( .INIT(4'h6)) \cmd_pipe_plus.mc_data_offset[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .I1(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .O(\cmd_pipe_plus.mc_data_offset_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair272" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cmd_pipe_plus.mc_data_offset[4]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] [4]), .I1(\cmd_pipe_plus.mc_data_offset_reg[5] [2]), .I2(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .I3(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .I4(\cmd_pipe_plus.mc_data_offset_reg[5] [3]), .O(\cmd_pipe_plus.mc_data_offset_reg[4] )); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_data_offset_1[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair281" *) LUT2 #( .INIT(4'h6)) \cmd_pipe_plus.mc_data_offset_1[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair281" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cmd_pipe_plus.mc_data_offset_1[4]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .I2(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .I3(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .I4(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair300" *) LUT1 #( .INIT(2'h1)) \ctl_lane_cnt[0]_i_1__0 (.I0(fine_adjust_lane_cnt[0]), .O(ctl_lane_cnt__0[0])); (* SOFT_HLUTNM = "soft_lutpair300" *) LUT2 #( .INIT(4'h6)) \ctl_lane_cnt[1]_i_1__0 (.I0(fine_adjust_lane_cnt[0]), .I1(fine_adjust_lane_cnt[1]), .O(ctl_lane_cnt__0[1])); (* SOFT_HLUTNM = "soft_lutpair290" *) LUT4 #( .INIT(16'h4AAA)) \ctl_lane_cnt[2]_i_1__0 (.I0(fine_adjust_lane_cnt[2]), .I1(\ctl_lane_cnt_reg_n_0_[3] ), .I2(fine_adjust_lane_cnt[0]), .I3(fine_adjust_lane_cnt[1]), .O(ctl_lane_cnt__0[2])); LUT4 #( .INIT(16'h2040)) \ctl_lane_cnt[3]_i_1__0 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(ctl_lane_cnt_0)); (* SOFT_HLUTNM = "soft_lutpair290" *) LUT4 #( .INIT(16'h6AAA)) \ctl_lane_cnt[3]_i_2__0 (.I0(\ctl_lane_cnt_reg_n_0_[3] ), .I1(fine_adjust_lane_cnt[0]), .I2(fine_adjust_lane_cnt[1]), .I3(fine_adjust_lane_cnt[2]), .O(ctl_lane_cnt__0[3])); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[0] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[0]), .Q(fine_adjust_lane_cnt[0]), .R(SR)); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[1] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[1]), .Q(fine_adjust_lane_cnt[1]), .R(SR)); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[2] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[2]), .Q(fine_adjust_lane_cnt[2]), .R(SR)); FDRE #( .INIT(1'b0)) \ctl_lane_cnt_reg[3] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[3]), .Q(\ctl_lane_cnt_reg_n_0_[3] ), .R(SR)); LUT6 #( .INIT(64'h7444744474777444)) \dec_cnt[0]_i_1 (.I0(\dec_cnt_reg_n_0_[0] ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\dec_cnt[0]_i_2_n_0 ), .I3(fine_adj_state_r144_out), .I4(\dec_cnt_reg[0]_i_3_n_6 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(dec_cnt[0])); LUT6 #( .INIT(64'h0000888BFFFF888B)) \dec_cnt[0]_i_2 (.I0(\dec_cnt_reg[0]_i_3_n_6 ), .I1(first_fail_detect_i_2_n_0), .I2(\first_fail_taps_reg_n_0_[1] ), .I3(\first_fail_taps[5]_i_5_n_0 ), .I4(fine_adj_state_r141_out), .I5(\inc_cnt_reg_n_0_[1] ), .O(\dec_cnt[0]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_4 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\first_fail_taps_reg_n_0_[3] ), .O(\dec_cnt[0]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_5 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\first_fail_taps_reg_n_0_[2] ), .O(\dec_cnt[0]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_6 (.I0(\inc_cnt_reg_n_0_[1] ), .I1(\first_fail_taps_reg_n_0_[1] ), .O(\dec_cnt[0]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_7 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\first_fail_taps_reg_n_0_[0] ), .O(\dec_cnt[0]_i_7_n_0 )); LUT4 #( .INIT(16'h9F90)) \dec_cnt[1]_i_1 (.I0(\dec_cnt_reg_n_0_[0] ), .I1(\dec_cnt_reg_n_0_[1] ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\dec_cnt[1]_i_2_n_0 ), .O(dec_cnt[1])); LUT6 #( .INIT(64'h08880888FBBB0888)) \dec_cnt[1]_i_2 (.I0(\dec_cnt[1]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(pi_dqs_found_all_bank), .I4(\dec_cnt_reg[0]_i_3_n_5 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(\dec_cnt[1]_i_2_n_0 )); LUT6 #( .INIT(64'h6F606F6F6F606060)) \dec_cnt[1]_i_3 (.I0(\inc_cnt_reg_n_0_[1] ), .I1(\inc_cnt_reg_n_0_[2] ), .I2(fine_adj_state_r141_out), .I3(\dec_cnt_reg[0]_i_3_n_5 ), .I4(first_fail_detect_i_2_n_0), .I5(\dec_cnt[1]_i_4_n_0 ), .O(\dec_cnt[1]_i_3_n_0 )); LUT6 #( .INIT(64'h5555555540000000)) \dec_cnt[1]_i_4 (.I0(\first_fail_taps_reg_n_0_[2] ), .I1(stable_pass_cnt_reg__0[4]), .I2(stable_pass_cnt_reg__0[3]), .I3(stable_pass_cnt_reg__0[2]), .I4(stable_pass_cnt_reg__0[1]), .I5(stable_pass_cnt_reg__0[5]), .O(\dec_cnt[1]_i_4_n_0 )); LUT5 #( .INIT(32'hE1FFE100)) \dec_cnt[2]_i_1 (.I0(\dec_cnt_reg_n_0_[0] ), .I1(\dec_cnt_reg_n_0_[1] ), .I2(\dec_cnt_reg_n_0_[2] ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\dec_cnt[2]_i_2_n_0 ), .O(dec_cnt[2])); LUT6 #( .INIT(64'h08880888FBBB0888)) \dec_cnt[2]_i_2 (.I0(\dec_cnt[2]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(pi_dqs_found_all_bank), .I4(\dec_cnt_reg[0]_i_3_n_4 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(\dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B888B888B8BB)) \dec_cnt[2]_i_3 (.I0(\dec_cnt[2]_i_4_n_0 ), .I1(fine_adj_state_r141_out), .I2(\dec_cnt_reg[0]_i_3_n_4 ), .I3(first_fail_detect_i_2_n_0), .I4(\first_fail_taps_reg_n_0_[3] ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\dec_cnt[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair296" *) LUT3 #( .INIT(8'h6A)) \dec_cnt[2]_i_4 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[2] ), .O(\dec_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFE01FFFFFE010000)) \dec_cnt[3]_i_1 (.I0(\dec_cnt_reg_n_0_[2] ), .I1(\dec_cnt_reg_n_0_[1] ), .I2(\dec_cnt_reg_n_0_[0] ), .I3(\dec_cnt_reg_n_0_[3] ), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I5(\dec_cnt[3]_i_2_n_0 ), .O(dec_cnt[3])); LUT6 #( .INIT(64'h08880888FBBB0888)) \dec_cnt[3]_i_2 (.I0(\dec_cnt[3]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(pi_dqs_found_all_bank), .I4(\dec_cnt_reg[4]_i_4_n_7 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(\dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B888B888B8BB)) \dec_cnt[3]_i_3 (.I0(\dec_cnt[3]_i_4_n_0 ), .I1(fine_adj_state_r141_out), .I2(\dec_cnt_reg[4]_i_4_n_7 ), .I3(first_fail_detect_i_2_n_0), .I4(\first_fail_taps_reg_n_0_[4] ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\dec_cnt[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair279" *) LUT4 #( .INIT(16'h6AAA)) \dec_cnt[3]_i_4 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[3] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .O(\dec_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'hB888B888B8BBB888)) \dec_cnt[4]_i_1 (.I0(\dec_cnt[4]_i_2_n_0 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\dec_cnt[4]_i_3_n_0 ), .I3(fine_adj_state_r144_out), .I4(\dec_cnt_reg[4]_i_4_n_6 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(dec_cnt[4])); (* SOFT_HLUTNM = "soft_lutpair282" *) LUT5 #( .INIT(32'hFFFE0001)) \dec_cnt[4]_i_2 (.I0(\dec_cnt_reg_n_0_[3] ), .I1(\dec_cnt_reg_n_0_[0] ), .I2(\dec_cnt_reg_n_0_[1] ), .I3(\dec_cnt_reg_n_0_[2] ), .I4(\dec_cnt_reg_n_0_[4] ), .O(\dec_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B888B888B8BB)) \dec_cnt[4]_i_3 (.I0(\dec_cnt[4]_i_5_n_0 ), .I1(fine_adj_state_r141_out), .I2(\dec_cnt_reg[4]_i_4_n_6 ), .I3(first_fail_detect_i_2_n_0), .I4(\first_fail_taps_reg_n_0_[5] ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\dec_cnt[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair279" *) LUT5 #( .INIT(32'h6AAAAAAA)) \dec_cnt[4]_i_5 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[4] ), .I2(\inc_cnt_reg_n_0_[2] ), .I3(\inc_cnt_reg_n_0_[1] ), .I4(\inc_cnt_reg_n_0_[3] ), .O(\dec_cnt[4]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[4]_i_6 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\first_fail_taps_reg_n_0_[5] ), .O(\dec_cnt[4]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[4]_i_7 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\first_fail_taps_reg_n_0_[4] ), .O(\dec_cnt[4]_i_7_n_0 )); LUT6 #( .INIT(64'h0808C80800000000)) \dec_cnt[5]_i_1 (.I0(\dec_cnt[5]_i_3_n_0 ), .I1(\dec_cnt[5]_i_4_n_0 ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\dec_cnt_reg[0]_0 ), .I4(\dec_cnt[5]_i_6_n_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(\dec_cnt[5]_i_1_n_0 )); LUT4 #( .INIT(16'h2220)) \dec_cnt[5]_i_10 (.I0(\first_fail_taps[5]_i_4_n_0 ), .I1(fine_adj_state_r141_out), .I2(first_fail_detect_reg_n_0), .I3(first_fail_detect_i_2_n_0), .O(\dec_cnt[5]_i_10_n_0 )); LUT6 #( .INIT(64'h9F909F9F9F909090)) \dec_cnt[5]_i_2 (.I0(\dec_cnt[5]_i_7_n_0 ), .I1(\dec_cnt_reg_n_0_[5] ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\dec_cnt[5]_i_8_n_0 ), .I4(fine_adj_state_r144_out), .I5(\dec_cnt[5]_i_9_n_0 ), .O(dec_cnt[5])); LUT6 #( .INIT(64'h0555000035550000)) \dec_cnt[5]_i_3 (.I0(\dec_cnt[5]_i_10_n_0 ), .I1(fine_adj_state_r16_out), .I2(pi_dqs_found_all_bank), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(detect_pi_found_dqs), .I5(first_fail_detect_i_2_n_0), .O(\dec_cnt[5]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \dec_cnt[5]_i_4 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \dec_cnt[5]_i_5 (.I0(\dec_cnt_reg_n_0_[5] ), .I1(\dec_cnt_reg_n_0_[3] ), .I2(\dec_cnt_reg_n_0_[0] ), .I3(\dec_cnt_reg_n_0_[1] ), .I4(\dec_cnt_reg_n_0_[2] ), .I5(\dec_cnt_reg_n_0_[4] ), .O(\dec_cnt_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair270" *) LUT5 #( .INIT(32'hFEFFFFFF)) \dec_cnt[5]_i_6 (.I0(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I1(fine_adjust_lane_cnt[2]), .I2(\ctl_lane_cnt_reg_n_0_[3] ), .I3(fine_adjust_lane_cnt[0]), .I4(fine_adjust_lane_cnt[1]), .O(\dec_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair282" *) LUT5 #( .INIT(32'hFFFFFFFE)) \dec_cnt[5]_i_7 (.I0(\dec_cnt_reg_n_0_[4] ), .I1(\dec_cnt_reg_n_0_[2] ), .I2(\dec_cnt_reg_n_0_[1] ), .I3(\dec_cnt_reg_n_0_[0] ), .I4(\dec_cnt_reg_n_0_[3] ), .O(\dec_cnt[5]_i_7_n_0 )); LUT6 #( .INIT(64'h0080000000D00000)) \dec_cnt[5]_i_8 (.I0(\first_fail_taps[5]_i_5_n_0 ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[4] ), .I3(\first_fail_taps[5]_i_6_n_0 ), .I4(\inc_cnt_reg_n_0_[5] ), .I5(first_fail_detect_reg_n_0), .O(\dec_cnt[5]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFE0000FFFFFFFF)) \dec_cnt[5]_i_9 (.I0(\first_fail_taps_reg_n_0_[2] ), .I1(\first_fail_taps_reg_n_0_[1] ), .I2(\first_fail_taps_reg_n_0_[4] ), .I3(\first_fail_taps_reg_n_0_[3] ), .I4(\first_fail_taps_reg_n_0_[5] ), .I5(first_fail_detect_reg_n_0), .O(\dec_cnt[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \dec_cnt_reg[0] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[0]), .Q(\dec_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__12)); CARRY4 \dec_cnt_reg[0]_i_3 (.CI(1'b0), .CO({\dec_cnt_reg[0]_i_3_n_0 ,\dec_cnt_reg[0]_i_3_n_1 ,\dec_cnt_reg[0]_i_3_n_2 ,\dec_cnt_reg[0]_i_3_n_3 }), .CYINIT(1'b1), .DI({\inc_cnt_reg_n_0_[3] ,\inc_cnt_reg_n_0_[2] ,\inc_cnt_reg_n_0_[1] ,\inc_cnt_reg_n_0_[0] }), .O({\dec_cnt_reg[0]_i_3_n_4 ,\dec_cnt_reg[0]_i_3_n_5 ,\dec_cnt_reg[0]_i_3_n_6 ,\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED [0]}), .S({\dec_cnt[0]_i_4_n_0 ,\dec_cnt[0]_i_5_n_0 ,\dec_cnt[0]_i_6_n_0 ,\dec_cnt[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \dec_cnt_reg[1] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[1]), .Q(\dec_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \dec_cnt_reg[2] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[2]), .Q(\dec_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \dec_cnt_reg[3] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[3]), .Q(\dec_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \dec_cnt_reg[4] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[4]), .Q(\dec_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__12)); CARRY4 \dec_cnt_reg[4]_i_4 (.CI(\dec_cnt_reg[0]_i_3_n_0 ), .CO({\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED [3:1],\dec_cnt_reg[4]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\inc_cnt_reg_n_0_[4] }), .O({\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED [3:2],\dec_cnt_reg[4]_i_4_n_6 ,\dec_cnt_reg[4]_i_4_n_7 }), .S({1'b0,1'b0,\dec_cnt[4]_i_6_n_0 ,\dec_cnt[4]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \dec_cnt_reg[5] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[5]), .Q(\dec_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__12)); LUT1 #( .INIT(2'h1)) \detect_rd_cnt[0]_i_1 (.I0(detect_rd_cnt_reg__0[0]), .O(detect_rd_cnt0__0[0])); (* SOFT_HLUTNM = "soft_lutpair295" *) LUT2 #( .INIT(4'h9)) \detect_rd_cnt[1]_i_1 (.I0(detect_rd_cnt_reg__0[0]), .I1(detect_rd_cnt_reg__0[1]), .O(\detect_rd_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair295" *) LUT3 #( .INIT(8'hA9)) \detect_rd_cnt[2]_i_1 (.I0(detect_rd_cnt_reg__0[2]), .I1(detect_rd_cnt_reg__0[1]), .I2(detect_rd_cnt_reg__0[0]), .O(detect_rd_cnt0__0[2])); LUT5 #( .INIT(32'hAAAAAAAB)) \detect_rd_cnt[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_rd_cnt_reg__0[3]), .I3(detect_rd_cnt_reg__0[0]), .I4(detect_rd_cnt_reg__0[1]), .O(\detect_rd_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'hAAAAAAA8)) \detect_rd_cnt[3]_i_2 (.I0(detect_pi_found_dqs), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_rd_cnt_reg__0[3]), .I3(detect_rd_cnt_reg__0[0]), .I4(detect_rd_cnt_reg__0[1]), .O(detect_rd_cnt0)); (* SOFT_HLUTNM = "soft_lutpair267" *) LUT4 #( .INIT(16'hAAA9)) \detect_rd_cnt[3]_i_3 (.I0(detect_rd_cnt_reg__0[3]), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_rd_cnt_reg__0[0]), .I3(detect_rd_cnt_reg__0[1]), .O(detect_rd_cnt0__0[3])); FDSE #( .INIT(1'b1)) \detect_rd_cnt_reg[0] (.C(CLK), .CE(detect_rd_cnt0), .D(detect_rd_cnt0__0[0]), .Q(detect_rd_cnt_reg__0[0]), .S(\detect_rd_cnt[3]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \detect_rd_cnt_reg[1] (.C(CLK), .CE(detect_rd_cnt0), .D(\detect_rd_cnt[1]_i_1_n_0 ), .Q(detect_rd_cnt_reg__0[1]), .S(\detect_rd_cnt[3]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \detect_rd_cnt_reg[2] (.C(CLK), .CE(detect_rd_cnt0), .D(detect_rd_cnt0__0[2]), .Q(detect_rd_cnt_reg__0[2]), .S(\detect_rd_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \detect_rd_cnt_reg[3] (.C(CLK), .CE(detect_rd_cnt0), .D(detect_rd_cnt0__0[3]), .Q(detect_rd_cnt_reg__0[3]), .R(\detect_rd_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000800000000000)) dqs_found_done_r_i_1 (.I0(\rd_byte_data_offset_reg[0]_3 ), .I1(init_dqsfound_done_r1_reg_n_0), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I3(dqs_found_done_r_i_3_n_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I5(p_1_in27_in), .O(dqs_found_done_r0)); LUT2 #( .INIT(4'h1)) dqs_found_done_r_i_2 (.I0(\rnk_cnt_r_reg_n_0_[1] ), .I1(\rnk_cnt_r_reg_n_0_[0] ), .O(\rd_byte_data_offset_reg[0]_3 )); LUT2 #( .INIT(4'h1)) dqs_found_done_r_i_3 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(dqs_found_done_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair289" *) LUT2 #( .INIT(4'h8)) dqs_found_done_r_i_4 (.I0(pi_dqs_found_all_bank), .I1(\pi_dqs_found_all_bank_r_reg[1]_0 ), .O(p_1_in27_in)); FDRE #( .INIT(1'b0)) dqs_found_done_r_reg (.C(CLK), .CE(1'b1), .D(dqs_found_done_r0), .Q(pi_dqs_found_done_r1_reg), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'h0201010000020200)) dqs_found_prech_req_i_2 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[0] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[5] ), .O(fine_adj_state_r16_out)); LUT3 #( .INIT(8'hB8)) dqs_found_prech_req_i_3 (.I0(fine_adj_state_r110_out), .I1(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I2(fine_adj_state_r17_out), .O(dqs_found_prech_req_reg_0)); LUT6 #( .INIT(64'hC008000800000000)) dqs_found_prech_req_i_4 (.I0(dqs_found_prech_req_i_5_n_0), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(prech_done), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(dqs_found_prech_req_reg_1)); LUT6 #( .INIT(64'hF0C0F040F0800000)) dqs_found_prech_req_i_5 (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I1(\dec_cnt[5]_i_10_n_0 ), .I2(detect_pi_found_dqs), .I3(p_1_in27_in), .I4(fine_adj_state_r110_out), .I5(fine_adj_state_r17_out), .O(dqs_found_prech_req_i_5_n_0)); FDRE #( .INIT(1'b0)) dqs_found_prech_req_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[2]_1 ), .Q(dqs_found_prech_req), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) dqs_found_start_r_reg (.C(CLK), .CE(1'b1), .D(pi_dqs_found_start_reg), .Q(dqs_found_start_r), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) final_dec_done_i_2 (.I0(\dec_cnt_reg[0]_0 ), .I1(fine_adjust_lane_cnt[1]), .I2(fine_adjust_lane_cnt[0]), .I3(\ctl_lane_cnt_reg_n_0_[3] ), .I4(fine_adjust_lane_cnt[2]), .I5(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .O(final_dec_done_reg_1)); FDRE #( .INIT(1'b0)) final_dec_done_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_1 ), .Q(final_dec_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) fine_adjust_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[0]_3 ), .Q(fine_adjust_done_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) fine_adjust_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[0]_2 ), .Q(\pi_rst_stg1_cal_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT5 #( .INIT(32'hFFFFAEAF)) first_fail_detect_i_1 (.I0(\first_fail_taps[5]_i_4_n_0 ), .I1(\first_fail_taps[5]_i_5_n_0 ), .I2(first_fail_detect_i_2_n_0), .I3(first_fail_detect_reg_n_0), .I4(fine_adj_state_r141_out), .O(first_fail_detect_i_1_n_0)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) first_fail_detect_i_2 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[3] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[0] ), .O(first_fail_detect_i_2_n_0)); LUT6 #( .INIT(64'h000000000000FF08)) first_fail_detect_i_3 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\first_fail_taps[5]_i_6_n_0 ), .I3(\inc_cnt_reg_n_0_[5] ), .I4(\first_fail_taps[5]_i_5_n_0 ), .I5(first_fail_detect_reg_n_0), .O(fine_adj_state_r141_out)); FDRE #( .INIT(1'b0)) first_fail_detect_reg (.C(CLK), .CE(first_fail_detect), .D(first_fail_detect_i_1_n_0), .Q(first_fail_detect_reg_n_0), .R(SR)); LUT3 #( .INIT(8'hB8)) \first_fail_taps[0]_i_1 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[0]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[1]_i_1 (.I0(\inc_cnt_reg_n_0_[1] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[1]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[2]_i_1 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[2]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[3]_i_1 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[3]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[4]_i_1 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[4]_i_1_n_0 )); LUT6 #( .INIT(64'h0020000000000000)) \first_fail_taps[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(fine_adj_state_r144_out), .I5(first_fail_detect_i_1_n_0), .O(first_fail_detect)); LUT3 #( .INIT(8'hB8)) \first_fail_taps[5]_i_2 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[5]_i_2_n_0 )); LUT3 #( .INIT(8'h2A)) \first_fail_taps[5]_i_3 (.I0(detect_pi_found_dqs), .I1(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I2(pi_dqs_found_all_bank), .O(fine_adj_state_r144_out)); LUT6 #( .INIT(64'hFFFFF7FF00FF00FF)) \first_fail_taps[5]_i_4 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\first_fail_taps[5]_i_6_n_0 ), .I3(first_fail_detect_reg_n_0), .I4(\first_fail_taps[5]_i_7_n_0 ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[5]_i_4_n_0 )); LUT5 #( .INIT(32'h15555555)) \first_fail_taps[5]_i_5 (.I0(stable_pass_cnt_reg__0[5]), .I1(stable_pass_cnt_reg__0[1]), .I2(stable_pass_cnt_reg__0[2]), .I3(stable_pass_cnt_reg__0[3]), .I4(stable_pass_cnt_reg__0[4]), .O(\first_fail_taps[5]_i_5_n_0 )); LUT3 #( .INIT(8'h7F)) \first_fail_taps[5]_i_6 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[3] ), .O(\first_fail_taps[5]_i_6_n_0 )); LUT6 #( .INIT(64'h00000001FFFFFFFF)) \first_fail_taps[5]_i_7 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[0] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[5] ), .O(\first_fail_taps[5]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \first_fail_taps_reg[0] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[0]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \first_fail_taps_reg[1] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[1]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \first_fail_taps_reg[2] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[2]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \first_fail_taps_reg[3] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[3]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \first_fail_taps_reg[4] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[4]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \first_fail_taps_reg[5] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[5]_i_2_n_0 ), .Q(\first_fail_taps_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'hFFFFFFFF88A8FFFF)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_4 (.I0(ck_addr_cmd_delay_done), .I1(\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ), .I2(rd_data_offset_cal_done), .I3(fine_adjust_done_r_reg_0), .I4(cmd_delay_start0), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair288" *) LUT2 #( .INIT(4'h7)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_9 (.I0(pi_dqs_found_done_r1_reg), .I1(pi_calib_done), .O(\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 )); LUT6 #( .INIT(64'hAAAAAAEAAAAAAA2A)) \gen_byte_sel_div1.calib_in_common_i_1 (.I0(\gen_byte_sel_div1.calib_in_common_i_2_n_0 ), .I1(pi_dqs_found_done_r1_reg), .I2(pi_calib_done), .I3(oclkdelay_calib_done_r_reg), .I4(pi_f_inc_reg), .I5(calib_in_common), .O(\gen_byte_sel_div1.calib_in_common_reg )); LUT6 #( .INIT(64'hBFBFFFBFFFBFFFBF)) \gen_byte_sel_div1.calib_in_common_i_2 (.I0(\gen_byte_sel_div1.calib_in_common_i_5_n_0 ), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(\calib_zero_inputs_reg[1] ), .I4(pi_calib_done), .I5(pi_dqs_found_done_r1_reg), .O(\gen_byte_sel_div1.calib_in_common_i_2_n_0 )); LUT6 #( .INIT(64'h3533000005000000)) \gen_byte_sel_div1.calib_in_common_i_5 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(oclkdelay_calib_done_r_reg), .I2(fine_adjust_done_r_reg_0), .I3(rd_data_offset_cal_done), .I4(ck_addr_cmd_delay_done), .I5(tempmon_sel_pi_incdec), .O(\gen_byte_sel_div1.calib_in_common_i_5_n_0 )); LUT6 #( .INIT(64'h8F80FFFF8F800000)) \gen_byte_sel_div1.ctl_lane_sel[0]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(fine_adjust_lane_cnt[0]), .I2(ck_addr_cmd_delay_done), .I3(ctl_lane_cnt[0]), .I4(ctl_lane_sel), .I5(\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ), .O(\gen_byte_sel_div1.ctl_lane_sel_reg[0] )); LUT6 #( .INIT(64'h8F80FFFF8F800000)) \gen_byte_sel_div1.ctl_lane_sel[1]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(fine_adjust_lane_cnt[1]), .I2(ck_addr_cmd_delay_done), .I3(ctl_lane_cnt[1]), .I4(ctl_lane_sel), .I5(\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ), .O(\gen_byte_sel_div1.ctl_lane_sel_reg[1] )); LUT6 #( .INIT(64'h8F80FFFF8F800000)) \gen_byte_sel_div1.ctl_lane_sel[2]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(fine_adjust_lane_cnt[2]), .I2(ck_addr_cmd_delay_done), .I3(ctl_lane_cnt[2]), .I4(ctl_lane_sel), .I5(\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ), .O(\gen_byte_sel_div1.ctl_lane_sel_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair285" *) LUT2 #( .INIT(4'h1)) \gen_byte_sel_div1.ctl_lane_sel[2]_i_2 (.I0(rst_stg1_cal), .I1(\pi_rst_stg1_cal_reg_n_0_[1] ), .O(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair287" *) LUT3 #( .INIT(8'h80)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3 (.I0(pi_dqs_found_done_r1_reg), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg_rep), .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] )); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b1), .O(n_0_0)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b1), .O(n_0_1)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b1), .O(n_0_2)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b1), .O(n_0_3)); (* SOFT_HLUTNM = "soft_lutpair299" *) LUT1 #( .INIT(2'h1)) \inc_cnt[0]_i_1 (.I0(\inc_cnt_reg_n_0_[0] ), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair299" *) LUT2 #( .INIT(4'h6)) \inc_cnt[1]_i_1 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\inc_cnt_reg_n_0_[1] ), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair296" *) LUT3 #( .INIT(8'h6A)) \inc_cnt[2]_i_1 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[0] ), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair284" *) LUT4 #( .INIT(16'h6AAA)) \inc_cnt[3]_i_1 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair284" *) LUT5 #( .INIT(32'h6AAAAAAA)) \inc_cnt[4]_i_1 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[2] ), .I3(\inc_cnt_reg_n_0_[1] ), .I4(\inc_cnt_reg_n_0_[3] ), .O(\inc_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'h00200000)) \inc_cnt[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(inc_cnt)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \inc_cnt[5]_i_2 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[3] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[0] ), .I5(\inc_cnt_reg_n_0_[4] ), .O(p_0_in__0[5])); FDRE #( .INIT(1'b0)) \inc_cnt_reg[0] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[0]), .Q(\inc_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \inc_cnt_reg[1] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[1]), .Q(\inc_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \inc_cnt_reg[2] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[2]), .Q(\inc_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \inc_cnt_reg[3] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[3]), .Q(\inc_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \inc_cnt_reg[4] (.C(CLK), .CE(inc_cnt), .D(\inc_cnt[4]_i_1_n_0 ), .Q(\inc_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \inc_cnt_reg[5] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[5]), .Q(\inc_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__2)); LUT1 #( .INIT(2'h1)) \init_dec_cnt[0]_i_1 (.I0(init_dec_cnt_reg__0[0]), .O(init_dec_cnt0[0])); (* SOFT_HLUTNM = "soft_lutpair297" *) LUT2 #( .INIT(4'h9)) \init_dec_cnt[1]_i_1 (.I0(init_dec_cnt_reg__0[0]), .I1(init_dec_cnt_reg__0[1]), .O(\init_dec_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair297" *) LUT3 #( .INIT(8'hE1)) \init_dec_cnt[2]_i_1 (.I0(init_dec_cnt_reg__0[0]), .I1(init_dec_cnt_reg__0[1]), .I2(init_dec_cnt_reg__0[2]), .O(init_dec_cnt0[2])); (* SOFT_HLUTNM = "soft_lutpair280" *) LUT4 #( .INIT(16'hFE01)) \init_dec_cnt[3]_i_1 (.I0(init_dec_cnt_reg__0[2]), .I1(init_dec_cnt_reg__0[1]), .I2(init_dec_cnt_reg__0[0]), .I3(init_dec_cnt_reg__0[3]), .O(init_dec_cnt0[3])); (* SOFT_HLUTNM = "soft_lutpair280" *) LUT5 #( .INIT(32'hFFFE0001)) \init_dec_cnt[4]_i_1 (.I0(init_dec_cnt_reg__0[3]), .I1(init_dec_cnt_reg__0[0]), .I2(init_dec_cnt_reg__0[1]), .I3(init_dec_cnt_reg__0[2]), .I4(init_dec_cnt_reg__0[4]), .O(init_dec_cnt0[4])); LUT6 #( .INIT(64'h2000000000000000)) \init_dec_cnt[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I4(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(init_dec_cnt)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \init_dec_cnt[5]_i_2 (.I0(init_dec_cnt_reg__0[4]), .I1(init_dec_cnt_reg__0[2]), .I2(init_dec_cnt_reg__0[1]), .I3(init_dec_cnt_reg__0[0]), .I4(init_dec_cnt_reg__0[3]), .I5(init_dec_cnt_reg__0[5]), .O(init_dec_cnt0[5])); FDSE #( .INIT(1'b1)) \init_dec_cnt_reg[0] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[0]), .Q(init_dec_cnt_reg__0[0]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE #( .INIT(1'b1)) \init_dec_cnt_reg[1] (.C(CLK), .CE(init_dec_cnt), .D(\init_dec_cnt[1]_i_1_n_0 ), .Q(init_dec_cnt_reg__0[1]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE #( .INIT(1'b1)) \init_dec_cnt_reg[2] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[2]), .Q(init_dec_cnt_reg__0[2]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE #( .INIT(1'b1)) \init_dec_cnt_reg[3] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[3]), .Q(init_dec_cnt_reg__0[3]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE #( .INIT(1'b1)) \init_dec_cnt_reg[4] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[4]), .Q(init_dec_cnt_reg__0[4]), .S(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \init_dec_cnt_reg[5] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[5]), .Q(init_dec_cnt_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__2)); LUT3 #( .INIT(8'h08)) init_dec_done_i_2 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(init_dec_done_reg_1)); FDRE #( .INIT(1'b0)) init_dec_done_reg (.C(CLK), .CE(1'b1), .D(init_dec_done_reg_2), .Q(init_dec_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) init_dqsfound_done_r1_reg (.C(CLK), .CE(1'b1), .D(rd_data_offset_cal_done), .Q(init_dqsfound_done_r1_reg_n_0), .R(1'b0)); FDRE #( .INIT(1'b0)) init_dqsfound_done_r2_reg (.C(CLK), .CE(1'b1), .D(init_dqsfound_done_r1_reg_n_0), .Q(init_dqsfound_done_r2), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r4_reg_srl2 " *) SRL16E #( .INIT(16'h0000)) init_dqsfound_done_r4_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(init_dqsfound_done_r2), .Q(init_dqsfound_done_r4_reg_srl2_n_0)); FDRE #( .INIT(1'b0)) init_dqsfound_done_r5_reg (.C(CLK), .CE(1'b1), .D(init_dqsfound_done_r4_reg_srl2_n_0), .Q(init_dqsfound_done_r5), .R(1'b0)); FDRE #( .INIT(1'b0)) init_dqsfound_done_r_reg (.C(CLK), .CE(1'b1), .D(init_dqsfound_done_r_reg_0), .Q(rd_data_offset_cal_done), .R(1'b0)); LUT6 #( .INIT(64'h0003FFFF33A3FFFF)) \init_state_r[1]_i_14 (.I0(\init_state_r[1]_i_29_n_0 ), .I1(\num_refresh_reg[1] ), .I2(oclkdelay_calib_done_r_reg_0), .I3(mpr_rdlvl_done_r_reg), .I4(cnt_cmd_done_r), .I5(\init_state_r[1]_i_30_n_0 ), .O(\init_state_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair288" *) LUT4 #( .INIT(16'h00DF)) \init_state_r[1]_i_29 (.I0(pi_dqs_found_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_last_byte_done_r), .I3(wrcal_done_reg), .O(\init_state_r[1]_i_29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair287" *) LUT4 #( .INIT(16'h5DFD)) \init_state_r[1]_i_30 (.I0(pi_dqs_found_done_r1_reg), .I1(wrcal_done_reg), .I2(rdlvl_stg1_done_int_reg), .I3(prbs_rdlvl_done_reg_rep), .O(\init_state_r[1]_i_30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair286" *) LUT2 #( .INIT(4'h7)) \init_state_r[1]_i_31 (.I0(pi_dqs_found_done_r1_reg), .I1(wrcal_done_reg), .O(\init_state_r_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair286" *) LUT4 #( .INIT(16'hFFFB)) \init_state_r[1]_i_44 (.I0(wrlvl_final_mux), .I1(pi_dqs_found_done_r1_reg), .I2(wrlvl_byte_redo), .I3(wrlvl_done_r1), .O(\init_state_r_reg[1]_0 )); LUT6 #( .INIT(64'hF0FDFDFDFDFDFDFD)) \init_state_r[2]_i_31 (.I0(pi_dqs_found_done_r1_reg), .I1(wrlvl_byte_redo), .I2(wrlvl_done_r1), .I3(oclkdelay_center_calib_done_r_reg), .I4(prbs_rdlvl_done_reg_rep), .I5(rdlvl_stg1_done_int_reg), .O(\init_state_r_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT5 #( .INIT(32'h0000EA00)) \phaser_in_gen.phaser_in_i_5 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg)); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_5__0 (.I0(calib_in_common), .I1(Q[0]), .I2(Q[1]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg_0)); (* SOFT_HLUTNM = "soft_lutpair264" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_5__1 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg_1)); (* SOFT_HLUTNM = "soft_lutpair264" *) LUT5 #( .INIT(32'h0000AB00)) \phaser_in_gen.phaser_in_i_5__2 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg_2)); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__1 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_6 )); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__2 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_8 )); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__3 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_10 )); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_12 )); (* SOFT_HLUTNM = "soft_lutpair268" *) LUT5 #( .INIT(32'h00000800)) phaser_out_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(D_po_fine_enable107_out)); (* SOFT_HLUTNM = "soft_lutpair268" *) LUT5 #( .INIT(32'h00000100)) phaser_out_i_3__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair271" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_3__1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_1 )); (* SOFT_HLUTNM = "soft_lutpair271" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_3__2 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_3 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__3 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_5 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_7 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__5 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_9 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__6 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_11 )); (* SOFT_HLUTNM = "soft_lutpair265" *) LUT5 #( .INIT(32'h00000800)) phaser_out_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(D_po_fine_inc113_out)); (* SOFT_HLUTNM = "soft_lutpair266" *) LUT5 #( .INIT(32'h00000100)) phaser_out_i_4__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_0 )); (* SOFT_HLUTNM = "soft_lutpair265" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_4__1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_2 )); (* SOFT_HLUTNM = "soft_lutpair266" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_4__2 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_4 )); LUT6 #( .INIT(64'h8000FFFF80000000)) \pi_dqs_found_all_bank[0]_i_1 (.I0(pi_dqs_found_lanes_r3[2]), .I1(pi_dqs_found_lanes_r3[3]), .I2(pi_dqs_found_lanes_r3[1]), .I3(pi_dqs_found_lanes_r3[0]), .I4(pi_dqs_found_start_reg), .I5(pi_dqs_found_all_bank), .O(\pi_dqs_found_all_bank[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \pi_dqs_found_all_bank_r_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_all_bank), .Q(rank_done_r_reg_0[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_dqs_found_all_bank_r_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_all_bank_r_reg[1]_0 ), .Q(rank_done_r_reg_0[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_dqs_found_all_bank_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_all_bank[0]_i_1_n_0 ), .Q(pi_dqs_found_all_bank), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \pi_dqs_found_all_bank_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_start_reg_0), .Q(\pi_dqs_found_all_bank_r_reg[1]_0 ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \pi_dqs_found_any_bank_r_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_any_bank), .Q(\pi_dqs_found_any_bank_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_dqs_found_any_bank_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_lanes_r3_reg[3]_0 ), .Q(pi_dqs_found_any_bank), .R(rstdiv0_sync_r1_reg_rep__13)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[0] (.C(CLK), .CE(1'b1), .D(in0[0]), .Q(pi_dqs_found_lanes_r1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[1] (.C(CLK), .CE(1'b1), .D(in0[1]), .Q(pi_dqs_found_lanes_r1[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[2] (.C(CLK), .CE(1'b1), .D(in0[2]), .Q(pi_dqs_found_lanes_r1[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[3] (.C(CLK), .CE(1'b1), .D(in0[3]), .Q(pi_dqs_found_lanes_r1[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[4] (.C(CLK), .CE(1'b1), .D(n_0_3), .Q(pi_dqs_found_lanes_r1[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[5] (.C(CLK), .CE(1'b1), .D(n_0_2), .Q(pi_dqs_found_lanes_r1[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[6] (.C(CLK), .CE(1'b1), .D(n_0_1), .Q(pi_dqs_found_lanes_r1[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r1_reg[7] (.C(CLK), .CE(1'b1), .D(n_0_0), .Q(pi_dqs_found_lanes_r1[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[0]), .Q(pi_dqs_found_lanes_r2[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[1]), .Q(pi_dqs_found_lanes_r2[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[2] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[2]), .Q(pi_dqs_found_lanes_r2[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[3] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[3]), .Q(pi_dqs_found_lanes_r2[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[4]), .Q(pi_dqs_found_lanes_r2[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[5]), .Q(pi_dqs_found_lanes_r2[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[6] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[6]), .Q(pi_dqs_found_lanes_r2[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r2_reg[7] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[7]), .Q(pi_dqs_found_lanes_r2[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[0]), .Q(pi_dqs_found_lanes_r3[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[1]), .Q(pi_dqs_found_lanes_r3[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[2] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[2]), .Q(pi_dqs_found_lanes_r3[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[3] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[3]), .Q(pi_dqs_found_lanes_r3[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[4]), .Q(pi_dqs_found_lanes_r3[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[5]), .Q(pi_dqs_found_lanes_r3[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[6] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[6]), .Q(pi_dqs_found_lanes_r3[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \pi_dqs_found_lanes_r3_reg[7] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[7]), .Q(pi_dqs_found_lanes_r3[7]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair301" *) LUT2 #( .INIT(4'hE)) \pi_rst_stg1_cal[0]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_1 ), .I1(rst_dqs_find_r1_reg_0), .O(\pi_rst_stg1_cal[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair301" *) LUT2 #( .INIT(4'hE)) \pi_rst_stg1_cal[1]_i_1 (.I0(p_1_in50_in), .I1(rst_dqs_find_r1_reg_0), .O(\pi_rst_stg1_cal[1]_i_1_n_0 )); LUT6 #( .INIT(64'h1111111010101010)) \pi_rst_stg1_cal_r1[0]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(\pi_rst_stg1_cal_r_reg[0]_1 ), .I3(\pi_dqs_found_any_bank_r_reg_n_0_[0] ), .I4(pi_dqs_found_all_bank), .I5(\pi_rst_stg1_cal_r1_reg_n_0_[0] ), .O(pi_rst_stg1_cal_r1_reg017_out)); LUT5 #( .INIT(32'h11101010)) \pi_rst_stg1_cal_r1[1]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(p_1_in50_in), .I3(p_0_in19_in), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .O(pi_rst_stg1_cal_r1_reg0)); FDRE #( .INIT(1'b0)) \pi_rst_stg1_cal_r1_reg[0] (.C(CLK), .CE(1'b1), .D(pi_rst_stg1_cal_r1_reg017_out), .Q(\pi_rst_stg1_cal_r1_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_rst_stg1_cal_r1_reg[1] (.C(CLK), .CE(1'b1), .D(pi_rst_stg1_cal_r1_reg0), .Q(p_0_in19_in), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000FE)) \pi_rst_stg1_cal_r[0]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_1 ), .I1(\pi_rst_stg1_cal_r[0]_i_2_n_0 ), .I2(\pi_rst_stg1_cal_r[0]_i_3_n_0 ), .I3(rstdiv0_sync_r1_reg_rep__23), .I4(\pi_rst_stg1_cal_r_reg[0]_0 ), .I5(\pi_rst_stg1_cal_r1_reg_n_0_[0] ), .O(\pi_rst_stg1_cal_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h0007)) \pi_rst_stg1_cal_r[0]_i_2 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I2(\rd_byte_data_offset_reg_n_0_[0][5] ), .I3(\rd_byte_data_offset_reg_n_0_[0][4] ), .O(\pi_rst_stg1_cal_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair289" *) LUT4 #( .INIT(16'h4F44)) \pi_rst_stg1_cal_r[0]_i_3 (.I0(dqs_found_start_r), .I1(pi_dqs_found_start_reg), .I2(pi_dqs_found_all_bank), .I3(\pi_dqs_found_any_bank_r_reg_n_0_[0] ), .O(\pi_rst_stg1_cal_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000EFEE0000)) \pi_rst_stg1_cal_r[1]_i_1 (.I0(p_1_in50_in), .I1(\pi_rst_stg1_cal_r[1]_i_2_n_0 ), .I2(dqs_found_start_r), .I3(pi_dqs_found_start_reg), .I4(fine_adjust_reg_0), .I5(p_0_in19_in), .O(\pi_rst_stg1_cal_r[1]_i_1_n_0 )); LUT4 #( .INIT(16'h0007)) \pi_rst_stg1_cal_r[1]_i_2 (.I0(\rd_byte_data_offset_reg[0][9]_0 [1]), .I1(\rd_byte_data_offset_reg[0][9]_0 [0]), .I2(p_0_in[5]), .I3(p_0_in[4]), .O(\pi_rst_stg1_cal_r[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \pi_rst_stg1_cal_r_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal_r[0]_i_1_n_0 ), .Q(\pi_rst_stg1_cal_r_reg[0]_1 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_rst_stg1_cal_r_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal_r[1]_i_1_n_0 ), .Q(p_1_in50_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_rst_stg1_cal_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal[0]_i_1_n_0 ), .Q(rst_stg1_cal), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \pi_rst_stg1_cal_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal[1]_i_1_n_0 ), .Q(\pi_rst_stg1_cal_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) rank_done_r1_reg (.C(CLK), .CE(1'b1), .D(pi_dqs_found_rank_done), .Q(rank_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_all_bank_r_reg[1]_1 ), .Q(pi_dqs_found_rank_done), .R(1'b0)); LUT2 #( .INIT(4'h2)) \rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 (.I0(rd_data_offset_cal_done), .I1(init_dqsfound_done_r1_reg_n_0), .O(p_22_out)); (* SOFT_HLUTNM = "soft_lutpair293" *) LUT1 #( .INIT(2'h1)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 (.I0(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair292" *) LUT2 #( .INIT(4'h9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 (.I0(\rd_byte_data_offset_reg_n_0_[0][1] ), .I1(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I1(\rd_byte_data_offset_reg_n_0_[0][0] ), .I2(\rd_byte_data_offset_reg_n_0_[0][1] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair274" *) LUT4 #( .INIT(16'hAAA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I2(\rd_byte_data_offset_reg_n_0_[0][1] ), .I3(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair274" *) LUT5 #( .INIT(32'hAAAAAAA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I2(\rd_byte_data_offset_reg_n_0_[0][0] ), .I3(\rd_byte_data_offset_reg_n_0_[0][1] ), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 )); LUT3 #( .INIT(8'h04)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 (.I0(init_dqsfound_done_r1_reg_n_0), .I1(rd_data_offset_cal_done), .I2(rstdiv0_sync_r1_reg_rep__23), .O(final_data_offset_mc)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ), .I1(\rd_byte_data_offset_reg_n_0_[0][4] ), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I3(\rd_byte_data_offset_reg_n_0_[0][1] ), .I4(\rd_byte_data_offset_reg_n_0_[0][0] ), .I5(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][0] ), .Q(rd_data_offset_ranks_0[0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][1] ), .Q(rd_data_offset_ranks_0[1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] (.C(CLK), .CE(p_22_out), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] (.C(CLK), .CE(p_22_out), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][4] ), .Q(rd_data_offset_ranks_0[4]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][5] ), .Q(rd_data_offset_ranks_0[5]), .R(rstdiv0_sync_r1_reg_rep__12)); LUT3 #( .INIT(8'h8A)) \rank_final_loop[0].bank_final_loop[1].final_data_offset[0][11]_i_1 (.I0(init_dqsfound_done_r5), .I1(init_dqsfound_done_r1_reg_n_0), .I2(rd_data_offset_cal_done), .O(final_data_offset)); LUT4 #( .INIT(16'h00D0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1 (.I0(rd_data_offset_cal_done), .I1(init_dqsfound_done_r1_reg_n_0), .I2(init_dqsfound_done_r5), .I3(rstdiv0_sync_r1_reg_rep__23), .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .Q(rd_data_offset_ranks_1[4]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .Q(rd_data_offset_ranks_1[5]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .Q(rd_data_offset_ranks_1[0]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .Q(rd_data_offset_ranks_1[1]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]), .R(rstdiv0_sync_r1_reg_rep__13)); LUT1 #( .INIT(2'h1)) \rank_final_loop[0].final_do_index[0][0]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .O(\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair283" *) LUT2 #( .INIT(4'h6)) \rank_final_loop[0].final_do_index[0][1]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .O(\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair269" *) LUT3 #( .INIT(8'h6A)) \rank_final_loop[0].final_do_index[0][2]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .O(\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_index_reg[0][0] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_index_reg[0][1] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_index_reg[0][2] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__13)); (* SOFT_HLUTNM = "soft_lutpair273" *) LUT5 #( .INIT(32'hEFEEEFFF)) \rank_final_loop[0].final_do_max[0][0]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(rd_data_offset_ranks_1[0]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(rd_data_offset_ranks_0[0]), .O(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'hFAF5FCFCFAF5F3F3)) \rank_final_loop[0].final_do_max[0][1]_i_1 (.I0(rd_data_offset_ranks_1[1]), .I1(rd_data_offset_ranks_0[1]), .I2(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ), .I3(rd_data_offset_ranks_1[0]), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I5(rd_data_offset_ranks_0[0]), .O(\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h555555555555A959)) \rank_final_loop[0].final_do_max[0][2]_i_1 (.I0(\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ), .I1(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I5(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FAFFFACC)) \rank_final_loop[0].final_do_max[0][2]_i_2 (.I0(rd_data_offset_ranks_1[0]), .I1(rd_data_offset_ranks_0[0]), .I2(rd_data_offset_ranks_1[1]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(rd_data_offset_ranks_0[1]), .I5(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ), .O(\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h555555555555A959)) \rank_final_loop[0].final_do_max[0][3]_i_1 (.I0(\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ), .I1(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I5(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF10111000)) \rank_final_loop[0].final_do_max[0][3]_i_2 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I5(\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ), .O(\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 )); LUT6 #( .INIT(64'hEFEEEFFF10111000)) \rank_final_loop[0].final_do_max[0][4]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(rd_data_offset_ranks_1[4]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(rd_data_offset_ranks_0[4]), .I5(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ), .O(\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FFFF4F44)) \rank_final_loop[0].final_do_max[0][5]_i_1 (.I0(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .I1(rd_data_offset_ranks_0[5]), .I2(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .I3(rd_data_offset_ranks_0[4]), .I4(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ), .I5(\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 )); LUT6 #( .INIT(64'h4540BABF45404540)) \rank_final_loop[0].final_do_max[0][5]_i_2 (.I0(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ), .I1(rd_data_offset_ranks_1[5]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(rd_data_offset_ranks_0[5]), .I4(\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ), .I5(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FFFF4F44)) \rank_final_loop[0].final_do_max[0][5]_i_3 (.I0(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .I1(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I2(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .I3(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I4(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ), .I5(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair269" *) LUT5 #( .INIT(32'hFFFFFFF4)) \rank_final_loop[0].final_do_max[0][5]_i_4 (.I0(rd_data_offset_ranks_0[5]), .I1(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair273" *) LUT2 #( .INIT(4'hE)) \rank_final_loop[0].final_do_max[0][5]_i_5 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .O(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair283" *) LUT5 #( .INIT(32'h000000E2)) \rank_final_loop[0].final_do_max[0][5]_i_6 (.I0(rd_data_offset_ranks_0[4]), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I2(rd_data_offset_ranks_1[4]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000EFEEEFFF)) \rank_final_loop[0].final_do_max[0][5]_i_7 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I5(\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 )); LUT6 #( .INIT(64'h40F4000040F440F4)) \rank_final_loop[0].final_do_max[0][5]_i_8 (.I0(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .I1(rd_data_offset_ranks_0[0]), .I2(rd_data_offset_ranks_0[1]), .I3(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .I4(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I5(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .O(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 )); LUT4 #( .INIT(16'h4F44)) \rank_final_loop[0].final_do_max[0][5]_i_9 (.I0(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I1(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .I2(rd_data_offset_ranks_0[4]), .I3(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .O(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_max_reg[0][0] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_max_reg[0][1] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_max_reg[0][2] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_max_reg[0][3] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_max_reg[0][4] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \rank_final_loop[0].final_do_max_reg[0][5] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair278" *) LUT5 #( .INIT(32'hAAAAAAA9)) \rd_byte_data_offset[0][10]_i_1 (.I0(p_0_in[4]), .I1(\rd_byte_data_offset_reg[0][9]_0 [1]), .I2(p_0_in[1]), .I3(p_0_in[0]), .I4(\rd_byte_data_offset_reg[0][9]_0 [0]), .O(p_1_in[4])); LUT4 #( .INIT(16'hAAAB)) \rd_byte_data_offset[0][11]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\rd_byte_data_offset[0][11]_i_4_n_0 ), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .O(\rd_byte_data_offset[0][11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000080000000000)) \rd_byte_data_offset[0][11]_i_2 (.I0(\rd_byte_data_offset[0][5]_i_4_n_0 ), .I1(\rd_byte_data_offset_reg[0]_3 ), .I2(\pi_rst_stg1_cal_r_reg[0]_0 ), .I3(dqs_found_start_r), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I5(\rd_byte_data_offset[0][11]_i_4_n_0 ), .O(\rd_byte_data_offset[0][11]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \rd_byte_data_offset[0][11]_i_3 (.I0(p_0_in[5]), .I1(p_0_in[4]), .I2(\rd_byte_data_offset_reg[0][9]_0 [0]), .I3(p_0_in[0]), .I4(p_0_in[1]), .I5(\rd_byte_data_offset_reg[0][9]_0 [1]), .O(p_1_in[5])); LUT6 #( .INIT(64'hBBBBBBB0BBB0BBB0)) \rd_byte_data_offset[0][11]_i_4 (.I0(rd_data_offset_cal_done), .I1(rank_done_r1), .I2(p_0_in[4]), .I3(p_0_in[5]), .I4(\rd_byte_data_offset_reg[0][9]_0 [0]), .I5(\rd_byte_data_offset_reg[0][9]_0 [1]), .O(\rd_byte_data_offset[0][11]_i_4_n_0 )); LUT4 #( .INIT(16'hAAAB)) \rd_byte_data_offset[0][5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\rd_byte_data_offset[0][5]_i_3_n_0 ), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .O(\rd_byte_data_offset[0][5]_i_1_n_0 )); LUT6 #( .INIT(64'h0000080000000000)) \rd_byte_data_offset[0][5]_i_2 (.I0(\rd_byte_data_offset[0][5]_i_4_n_0 ), .I1(\rd_byte_data_offset_reg[0]_3 ), .I2(\pi_rst_stg1_cal_r_reg[0]_0 ), .I3(dqs_found_start_r), .I4(pi_dqs_found_all_bank), .I5(\rd_byte_data_offset[0][5]_i_3_n_0 ), .O(rd_byte_data_offset)); LUT6 #( .INIT(64'hFEEE0000FEEEFEEE)) \rd_byte_data_offset[0][5]_i_3 (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ), .I1(\rd_byte_data_offset_reg_n_0_[0][5] ), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I4(rd_data_offset_cal_done), .I5(rank_done_r1), .O(\rd_byte_data_offset[0][5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000001000)) \rd_byte_data_offset[0][5]_i_4 (.I0(detect_rd_cnt_reg__0[3]), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_pi_found_dqs), .I3(detect_rd_cnt_reg__0[0]), .I4(detect_rd_cnt_reg__0[1]), .I5(rd_data_offset_cal_done), .O(\rd_byte_data_offset[0][5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair298" *) LUT1 #( .INIT(2'h1)) \rd_byte_data_offset[0][6]_i_1 (.I0(p_0_in[0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair291" *) LUT2 #( .INIT(4'h9)) \rd_byte_data_offset[0][7]_i_1 (.I0(p_0_in[0]), .I1(p_0_in[1]), .O(\rd_byte_data_offset[0][7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair298" *) LUT3 #( .INIT(8'hA9)) \rd_byte_data_offset[0][8]_i_1 (.I0(\rd_byte_data_offset_reg[0][9]_0 [0]), .I1(p_0_in[1]), .I2(p_0_in[0]), .O(p_1_in[2])); (* SOFT_HLUTNM = "soft_lutpair278" *) LUT4 #( .INIT(16'hAAA9)) \rd_byte_data_offset[0][9]_i_1 (.I0(\rd_byte_data_offset_reg[0][9]_0 [1]), .I1(\rd_byte_data_offset_reg[0][9]_0 [0]), .I2(p_0_in[0]), .I3(p_0_in[1]), .O(p_1_in[3])); FDRE #( .INIT(1'b0)) \rd_byte_data_offset_reg[0][0] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][0] ), .R(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \rd_byte_data_offset_reg[0][10] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[4]), .Q(p_0_in[4]), .S(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_byte_data_offset_reg[0][11] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[5]), .Q(p_0_in[5]), .R(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \rd_byte_data_offset_reg[0][1] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][1] ), .S(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_byte_data_offset_reg[0][2] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ), .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .R(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \rd_byte_data_offset_reg[0][3] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ), .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .S(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \rd_byte_data_offset_reg[0][4] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][4] ), .S(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_byte_data_offset_reg[0][5] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][5] ), .R(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_byte_data_offset_reg[0][6] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[0]), .Q(p_0_in[0]), .R(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \rd_byte_data_offset_reg[0][7] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(\rd_byte_data_offset[0][7]_i_1_n_0 ), .Q(p_0_in[1]), .S(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_byte_data_offset_reg[0][8] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[2]), .Q(\rd_byte_data_offset_reg[0][9]_0 [0]), .R(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \rd_byte_data_offset_reg[0][9] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[3]), .Q(\rd_byte_data_offset_reg[0][9]_0 [1]), .S(\rd_byte_data_offset[0][11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair294" *) LUT3 #( .INIT(8'hD2)) \rnk_cnt_r[0]_i_1 (.I0(pi_dqs_found_rank_done), .I1(rd_data_offset_cal_done), .I2(\rnk_cnt_r_reg_n_0_[0] ), .O(\rnk_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair294" *) LUT4 #( .INIT(16'hF708)) \rnk_cnt_r[1]_i_1 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(pi_dqs_found_rank_done), .I2(rd_data_offset_cal_done), .I3(\rnk_cnt_r_reg_n_0_[1] ), .O(\rnk_cnt_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rnk_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[0]_i_1_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rnk_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[1]_i_1_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT5 #( .INIT(32'h8800FF30)) rst_dqs_find_i_2 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I2(init_dqsfound_done_r5), .I3(rst_dqs_find_i_5_n_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(rst_dqs_find)); LUT6 #( .INIT(64'hBB00BB0030333000)) rst_dqs_find_i_3 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(rst_dqs_find_i_6_n_0), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(p_1_in27_in), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(rst_dqs_find_reg_1)); LUT6 #( .INIT(64'h0000004F00000040)) rst_dqs_find_i_4 (.I0(pi_dqs_found_any_bank), .I1(rst_dqs_find_r2), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(init_dqsfound_done_r5), .O(rst_dqs_find_reg_0)); LUT5 #( .INIT(32'hFFFF8A80)) rst_dqs_find_i_5 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(fine_adj_state_r144_out), .I3(first_fail_detect_i_2_n_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(rst_dqs_find_i_5_n_0)); LUT6 #( .INIT(64'h40F0F0F040000000)) rst_dqs_find_i_6 (.I0(fine_adj_state_r16_out), .I1(first_fail_detect_i_2_n_0), .I2(detect_pi_found_dqs), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(pi_dqs_found_all_bank), .I5(\dec_cnt[5]_i_10_n_0 ), .O(rst_dqs_find_i_6_n_0)); FDRE #( .INIT(1'b0)) rst_dqs_find_r1_reg (.C(CLK), .CE(1'b1), .D(rst_dqs_find_r1_reg_0), .Q(rst_dqs_find_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) rst_dqs_find_r2_reg (.C(CLK), .CE(1'b1), .D(rst_dqs_find_r1), .Q(rst_dqs_find_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) rst_dqs_find_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_0 ), .Q(rst_dqs_find_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__13)); (* SOFT_HLUTNM = "soft_lutpair277" *) LUT4 #( .INIT(16'h4055)) \stable_pass_cnt[0]_i_1 (.I0(\stable_pass_cnt_reg_n_0_[0] ), .I1(pi_dqs_found_all_bank), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(detect_pi_found_dqs), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair277" *) LUT5 #( .INIT(32'h60006666)) \stable_pass_cnt[1]_i_1 (.I0(stable_pass_cnt_reg__0[1]), .I1(\stable_pass_cnt_reg_n_0_[0] ), .I2(pi_dqs_found_all_bank), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(detect_pi_found_dqs), .O(p_0_in__1[1])); LUT6 #( .INIT(64'h7800000078787878)) \stable_pass_cnt[2]_i_1 (.I0(\stable_pass_cnt_reg_n_0_[0] ), .I1(stable_pass_cnt_reg__0[1]), .I2(stable_pass_cnt_reg__0[2]), .I3(pi_dqs_found_all_bank), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I5(detect_pi_found_dqs), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair276" *) LUT5 #( .INIT(32'h15554000)) \stable_pass_cnt[3]_i_1 (.I0(fine_adj_state_r144_out), .I1(stable_pass_cnt_reg__0[2]), .I2(stable_pass_cnt_reg__0[1]), .I3(\stable_pass_cnt_reg_n_0_[0] ), .I4(stable_pass_cnt_reg__0[3]), .O(\stable_pass_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h000000007FFF8000)) \stable_pass_cnt[4]_i_1 (.I0(\stable_pass_cnt_reg_n_0_[0] ), .I1(stable_pass_cnt_reg__0[1]), .I2(stable_pass_cnt_reg__0[2]), .I3(stable_pass_cnt_reg__0[3]), .I4(stable_pass_cnt_reg__0[4]), .I5(fine_adj_state_r144_out), .O(p_0_in__1[4])); LUT5 #( .INIT(32'h00200000)) \stable_pass_cnt[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(detect_pi_found_dqs), .O(stable_pass_cnt)); LUT5 #( .INIT(32'h15554000)) \stable_pass_cnt[5]_i_2 (.I0(fine_adj_state_r144_out), .I1(stable_pass_cnt_reg__0[4]), .I2(stable_pass_cnt_reg__0[3]), .I3(\stable_pass_cnt[5]_i_3_n_0 ), .I4(stable_pass_cnt_reg__0[5]), .O(\stable_pass_cnt[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair276" *) LUT3 #( .INIT(8'h80)) \stable_pass_cnt[5]_i_3 (.I0(stable_pass_cnt_reg__0[2]), .I1(stable_pass_cnt_reg__0[1]), .I2(\stable_pass_cnt_reg_n_0_[0] ), .O(\stable_pass_cnt[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \stable_pass_cnt_reg[0] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[0]), .Q(\stable_pass_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \stable_pass_cnt_reg[1] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[1]), .Q(stable_pass_cnt_reg__0[1]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \stable_pass_cnt_reg[2] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[2]), .Q(stable_pass_cnt_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \stable_pass_cnt_reg[3] (.C(CLK), .CE(stable_pass_cnt), .D(\stable_pass_cnt[3]_i_1_n_0 ), .Q(stable_pass_cnt_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \stable_pass_cnt_reg[4] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[4]), .Q(stable_pass_cnt_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \stable_pass_cnt_reg[5] (.C(CLK), .CE(stable_pass_cnt), .D(\stable_pass_cnt[5]_i_2_n_0 ), .Q(stable_pass_cnt_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__2)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_init" *) module ddr3_ifmig_7series_v4_0_ddr_phy_init (prbs_rdlvl_done_r1, prech_done, rdlvl_start_pre, rdlvl_start_dly0_r, in0, out, cnt_cmd_done_r, wrlvl_done_r1, prbs_last_byte_done_r, prech_pending_r_reg_0, pi_calib_done, wrcal_resume_r, complex_ocal_reset_rd_addr, wl_sm_start, wrcal_rd_wait, wrcal_sanity_chk, detect_pi_found_dqs, mpr_end_if_reset, init_complete_r1_reg_0, calib_complete, cnt_pwron_reset_done_r, cnt_pwron_cke_done_r, pi_dqs_found_done_r1, complex_act_start, \oclkdelay_ref_cnt_reg[13]_0 , cnt_txpr_done_r, cnt_dllk_zqinit_done_r, cnt_init_mr_done_r, ddr2_refresh_flag_r, ddr2_pre_flag_r_reg_0, cnt_init_af_done_r, burst_addr_r_reg_0, prech_pending_r, rdlvl_stg1_start_r_reg, ocal_last_byte_done, \rd_ptr_timing_reg[0] , phy_dout, reset_if_reg, oclk_calib_resume_level_reg_0, Q, \odd_cwl.phy_cas_n_reg[1]_0 , \cnt_init_mr_r_reg[1]_0 , \init_state_r_reg[1]_0 , cnt_init_mr_r, complex_oclkdelay_calib_start_int_reg_0, \reg_ctrl_cnt_r_reg[3]_0 , \one_rank.stg1_wr_done_reg_0 , \init_state_r_reg[2]_0 , mem_init_done_r, \victim_sel_rotate.sel_reg[31] , new_cnt_dqs_r_reg, prbs_rdlvl_start_r_reg, first_wrcal_pat_r, D2, D0, D3, D5, D6, D1, \rd_ptr_timing_reg[0]_0 , D7, D8, \rd_ptr_timing_reg[0]_1 , \my_empty_reg[7] , \my_empty_reg[7]_0 , \my_empty_reg[7]_1 , D4, \my_empty_reg[7]_2 , \my_empty_reg[7]_3 , \my_empty_reg[7]_4 , \my_empty_reg[7]_5 , \rd_ptr_timing_reg[0]_2 , D9, \my_empty_reg[7]_6 , \my_empty_reg[7]_7 , \my_empty_reg[7]_8 , \my_empty_reg[7]_9 , \my_empty_reg[7]_10 , \my_empty_reg[7]_11 , \my_empty_reg[7]_12 , \my_empty_reg[7]_13 , \my_empty_reg[7]_14 , \my_empty_reg[7]_15 , \my_empty_reg[7]_16 , \my_empty_reg[7]_17 , \my_empty_reg[7]_18 , \my_empty_reg[7]_19 , \my_empty_reg[7]_20 , \my_empty_reg[7]_21 , \my_empty_reg[7]_22 , \my_empty_reg[7]_23 , \my_empty_reg[7]_24 , \my_empty_reg[7]_25 , \my_empty_reg[7]_26 , \my_empty_reg[7]_27 , \my_empty_reg[7]_28 , \my_empty_reg[7]_29 , \my_empty_reg[7]_30 , \my_empty_reg[7]_31 , \my_empty_reg[7]_32 , \my_empty_reg[7]_33 , \my_empty_reg[7]_34 , \my_empty_reg[7]_35 , \my_empty_reg[7]_36 , \my_empty_reg[7]_37 , lim_start_r_reg, cal1_state_r1535_out, mpr_rdlvl_start_r_reg, E, \cnt_shift_r_reg[0] , cnt_init_mr_r1, prech_pending_r_reg_1, rdlvl_start_pre_reg_0, read_calib_reg_0, temp_lmr_done, stg1_wr_done, \back_to_back_reads_4_1.num_reads_reg[0]_0 , \back_to_back_reads_4_1.num_reads_reg[1]_0 , \init_state_r_reg[4]_0 , burst_addr_r_reg_1, oclkdelay_int_ref_req_reg_0, \init_state_r_reg[5]_0 , ddr2_pre_flag_r_reg_1, ddr2_refresh_flag_r_reg_0, \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 , \complex_row_cnt_ocal_reg[0]_0 , ddr3_lm_done_r, \row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 , cnt_pwron_reset_done_r_reg_0, \cnt_pwron_r_reg[7]_0 , cnt_pwron_cke_done_r_reg_0, \cnt_txpr_r_reg[2]_0 , mem_init_done_r_reg_0, mem_init_done_r_reg_1, \init_state_r_reg[0]_0 , rdlvl_stg1_start_int, \init_state_r_reg[2]_1 , cnt_txpr_done_r_reg_0, \pi_dqs_found_all_bank_reg[1] , dqs_found_start_r_reg, mux_wrdata_en, mux_cmd_wren, mux_reset_n, \data_offset_1_i1_reg[5] , \rd_ptr_timing_reg[0]_3 , \my_full_reg[3] , \phy_ctl_wd_i1_reg[24] , \my_empty_reg[7]_38 , \my_empty_reg[7]_39 , \my_empty_reg[7]_40 , \my_empty_reg[7]_41 , \samples_cnt_r_reg[11] , \wrcal_dqs_cnt_r_reg[0] , \rd_addr_reg_rep[7] , \rd_addr_reg[0] , cnt_init_af_r, wrlvl_final_if_rst, wr_level_start_r_reg, wrcal_start_reg_0, phy_write_calib, phy_read_calib, first_rdlvl_pat_r, prbs_rdlvl_done_reg_rep, CLK, rdlvl_stg1_done_int_reg, A_rst_primitives_reg, rstdiv0_sync_r1_reg_rep__11, wr_level_done_reg, prbs_last_byte_done, wrlvl_rank_done, prbs_rdlvl_done_pulse0, rstdiv0_sync_r1_reg_rep__12, reset_rd_addr0, prech_req, wrcal_resume_w, rdlvl_last_byte_done, dqs_found_done_r_reg, rstdiv0_sync_r1_reg_rep__10, cnt_pwron_cke_done_r_reg_1, cnt_txpr_done_r_reg_1, cnt_dllk_zqinit_done_r_reg_0, cnt_init_mr_done_r_reg_0, cnt_cmd_done_r_reg_0, ddr2_pre_flag_r_reg_2, cnt_init_af_done_r_reg_0, burst_addr_r_reg_2, prech_req_posedge_r_reg_0, \init_state_r_reg[0]_1 , \rdlvl_start_dly0_r_reg[14]_0 , \init_state_r_reg[6]_0 , \cnt_pwron_r_reg[7]_1 , \init_state_r_reg[6]_1 , oclkdelay_center_calib_done_r_reg, rdlvl_stg1_done_int_reg_0, oclkdelay_calib_done_r_reg, oclkdelay_calib_done_r_reg_0, \dout_o_reg[11] , \dout_o_reg[11]_0 , D, wrcal_done_reg, \dout_o_reg[9] , \dout_o_reg[9]_0 , \dout_o_reg[11]_1 , \dout_o_reg[11]_2 , \dout_o_reg[13] , \dout_o_reg[13]_0 , wrcal_done_reg_0, \dout_o_reg[9]_1 , \dout_o_reg[9]_2 , \dout_o_reg[9]_3 , \dout_o_reg[9]_4 , \dout_o_reg[13]_1 , \dout_o_reg[13]_2 , \dout_o_reg[1] , \dout_o_reg[1]_0 , \dout_o_reg[13]_3 , \dout_o_reg[13]_4 , oclkdelay_calib_done_r_reg_1, \dout_o_reg[11]_3 , \dout_o_reg[11]_4 , \dout_o_reg[13]_5 , \dout_o_reg[13]_6 , \dout_o_reg[15] , \dout_o_reg[7] , \dout_o_reg[15]_0 , \dout_o_reg[15]_1 , \dout_o_reg[7]_0 , \dout_o_reg[15]_2 , wrcal_done_reg_1, \dout_o_reg[3] , \dout_o_reg[3]_0 , \dout_o_reg[7]_1 , \dout_o_reg[7]_2 , \dout_o_reg[8] , \dout_o_reg[8]_0 , \dout_o_reg[14] , \dout_o_reg[14]_0 , \dout_o_reg[6] , \dout_o_reg[14]_1 , \dout_o_reg[14]_2 , first_rdlvl_pat_r_reg_0, wrcal_done_reg_2, \dout_o_reg[2] , \dout_o_reg[2]_0 , \dout_o_reg[4] , \dout_o_reg[4]_0 , \dout_o_reg[8]_1 , \dout_o_reg[8]_2 , \dout_o_reg[10] , \dout_o_reg[10]_0 , \dout_o_reg[8]_3 , \dout_o_reg[8]_4 , \dout_o_reg[12] , \dout_o_reg[12]_0 , wrcal_done_reg_3, wrcal_done_reg_4, wrcal_done_reg_5, wrcal_done_reg_6, wrcal_done_reg_7, wrcal_done_reg_8, init_calib_complete_reg_rep__13, rstdiv0_sync_r1_reg_rep__24, reset_if_r9, prbs_rdlvl_done_reg, reset_if, delay_done_r4_reg, dqs_found_done_r_reg_0, wrcal_done_reg_9, oclkdelay_center_calib_start_r_reg, oclk_calib_resume_r_reg, prbs_rdlvl_done_reg_rep_0, complex_oclk_calib_resume, pi_dqs_found_rank_done, wrcal_sanity_chk_done_reg, wrcal_done_reg_10, wrlvl_byte_redo, wrcal_prech_req, \init_state_r_reg[1]_1 , prbs_rdlvl_start_r, oclkdelay_calib_done_r_reg_2, mc_cas_n, init_calib_complete_reg_rep__6, \rd_ptr_reg[3] , \my_empty_reg[1] , mem_out, \my_empty_reg[1]_0 , mc_ras_n, mc_odt, \rd_ptr_reg[3]_0 , \my_empty_reg[1]_1 , mc_cke, mc_we_n, mc_address, \rd_ptr_reg[3]_1 , \my_empty_reg[1]_2 , init_calib_complete_reg_rep__5, mc_bank, \write_buffer.wr_buf_out_data_reg[255] , \rd_ptr_reg[3]_2 , \my_empty_reg[1]_3 , \rd_ptr_reg[3]_3 , \my_empty_reg[1]_4 , init_calib_complete_reg_rep__4, \rd_ptr_reg[3]_4 , \my_empty_reg[1]_5 , \rd_ptr_reg[3]_5 , \my_empty_reg[1]_6 , init_calib_complete_reg_rep__3, init_calib_complete_reg_rep__2, init_calib_complete_reg_rep__1, init_calib_complete_reg_rep__0, init_calib_complete_reg_rep, \rd_byte_data_offset_reg[0][3] , init_dqsfound_done_r2, \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] , \rd_byte_data_offset_reg[0][9] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] , mpr_rdlvl_start_r, phy_rddata_en_1, mpr_rdlvl_done_r_reg, \cnt_shift_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__22, \mcGo_r_reg[15] , ck_addr_cmd_delay_done, prbs_rdlvl_done_reg_0, wrlvl_final_mux, mpr_rdlvl_done_r_reg_0, \init_state_r_reg[2]_2 , rstdiv0_sync_r1_reg_rep__23, rdlvl_pi_incdec, dqs_found_prech_req, prbs_rdlvl_prech_req_reg, complex_ocal_ref_req, rdlvl_prech_req, complex_pi_incdec_done, wrcal_done_reg_11, rdlvl_stg1_done_int_reg_1, phy_if_empty_r_reg, wrcal_sanity_chk_done_reg_0, rdlvl_stg1_done_int_reg_2, oclkdelay_calib_done_r_reg_3, lim2init_prech_req, ocd_prech_req, oclkdelay_calib_done_r_reg_4, cnt_cmd_done_r_reg_1, oclkdelay_center_calib_start_r_reg_0, oclk_calib_resume_r_reg_0, mpr_rdlvl_done_r_reg_1, dqs_found_done_r_reg_1, wrlvl_byte_redo_reg, mpr_rdlvl_done_r_reg_2, oclkdelay_center_calib_done_r_reg_0, complex_victim_inc_reg, complex_ocal_num_samples_done_r, reset_rd_addr, dqs_found_done_r_reg_2, prbs_last_byte_done_reg, \rd_victim_sel_reg[1] , \rd_victim_sel_reg[0] , \rd_victim_sel_reg[2] , cnt_init_af_done_r_reg_1, num_samples_done_r, complex_init_pi_dec_done, done_r_reg, rdlvl_stg1_rank_done, write_request_r_reg, complex_ocal_rd_victim_sel, prbs_rdlvl_done_reg_rep_1, prbs_rdlvl_done_reg_rep_2, wrlvl_final_mux_reg, oclkdelay_calib_done_r_reg_5, wrlvl_byte_redo_reg_0, mem_init_done_r_reg_2, rdlvl_stg1_done_int_reg_3, wrlvl_final_mux_reg_0, prbs_rdlvl_done_reg_rep_3, mpr_last_byte_done, rdlvl_stg1_done_int_reg_4, \dout_o_reg[0] , \dout_o_reg[0]_0 , \pi_dqs_found_all_bank_reg[1]_0 , mc_wrdata_en, init_calib_complete_reg_rep__14, \cmd_pipe_plus.mc_data_offset_1_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , mc_cmd, \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[5] , init_calib_complete_reg_rep__12, init_calib_complete_reg_rep__11, init_calib_complete_reg_rep__10, init_calib_complete_reg_rep__9, init_calib_complete_reg_rep__8, init_calib_complete_reg_rep__7, \samples_cnt_r_reg[11]_0 , wrcal_sanity_chk_r_reg, \rd_addr_reg[3] , rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__23_0, done_dqs_tap_inc, p_81_in, rstdiv0_sync_r1_reg_rep__23_1, pi_dqs_found_done_r1_reg_0, pi_dqs_found_done_r1_reg_1, pi_dqs_found_done_r1_reg_2, pi_dqs_found_done_r1_reg_3, pi_dqs_found_done_r1_reg_4, pi_dqs_found_done_r1_reg_5, pi_dqs_found_done_r1_reg_6, pi_dqs_found_done_r1_reg_7, rstdiv0_sync_r1_reg_rep__19, rstdiv0_sync_r1_reg_rep__18); output prbs_rdlvl_done_r1; output prech_done; output rdlvl_start_pre; output [0:0]rdlvl_start_dly0_r; output in0; output out; output cnt_cmd_done_r; output wrlvl_done_r1; output prbs_last_byte_done_r; output prech_pending_r_reg_0; output pi_calib_done; output wrcal_resume_r; output complex_ocal_reset_rd_addr; output wl_sm_start; output wrcal_rd_wait; output wrcal_sanity_chk; output detect_pi_found_dqs; output mpr_end_if_reset; output init_complete_r1_reg_0; output calib_complete; output cnt_pwron_reset_done_r; output cnt_pwron_cke_done_r; output pi_dqs_found_done_r1; output complex_act_start; output \oclkdelay_ref_cnt_reg[13]_0 ; output cnt_txpr_done_r; output cnt_dllk_zqinit_done_r; output cnt_init_mr_done_r; output ddr2_refresh_flag_r; output ddr2_pre_flag_r_reg_0; output cnt_init_af_done_r; output burst_addr_r_reg_0; output prech_pending_r; output rdlvl_stg1_start_r_reg; output ocal_last_byte_done; output [33:0]\rd_ptr_timing_reg[0] ; output [31:0]phy_dout; output reset_if_reg; output oclk_calib_resume_level_reg_0; output [5:0]Q; output \odd_cwl.phy_cas_n_reg[1]_0 ; output \cnt_init_mr_r_reg[1]_0 ; output \init_state_r_reg[1]_0 ; output [1:0]cnt_init_mr_r; output complex_oclkdelay_calib_start_int_reg_0; output \reg_ctrl_cnt_r_reg[3]_0 ; output \one_rank.stg1_wr_done_reg_0 ; output \init_state_r_reg[2]_0 ; output mem_init_done_r; output [7:0]\victim_sel_rotate.sel_reg[31] ; output new_cnt_dqs_r_reg; output prbs_rdlvl_start_r_reg; output first_wrcal_pat_r; output [0:0]D2; output [0:0]D0; output [0:0]D3; output [3:0]D5; output [3:0]D6; output [0:0]D1; output [7:0]\rd_ptr_timing_reg[0]_0 ; output [3:0]D7; output [3:0]D8; output [7:0]\rd_ptr_timing_reg[0]_1 ; output [3:0]\my_empty_reg[7] ; output [3:0]\my_empty_reg[7]_0 ; output [3:0]\my_empty_reg[7]_1 ; output [3:0]D4; output [3:0]\my_empty_reg[7]_2 ; output [3:0]\my_empty_reg[7]_3 ; output [3:0]\my_empty_reg[7]_4 ; output [3:0]\my_empty_reg[7]_5 ; output [3:0]\rd_ptr_timing_reg[0]_2 ; output [3:0]D9; output [7:0]\my_empty_reg[7]_6 ; output [7:0]\my_empty_reg[7]_7 ; output [7:0]\my_empty_reg[7]_8 ; output [7:0]\my_empty_reg[7]_9 ; output [7:0]\my_empty_reg[7]_10 ; output [7:0]\my_empty_reg[7]_11 ; output [7:0]\my_empty_reg[7]_12 ; output [7:0]\my_empty_reg[7]_13 ; output [7:0]\my_empty_reg[7]_14 ; output [7:0]\my_empty_reg[7]_15 ; output [7:0]\my_empty_reg[7]_16 ; output [7:0]\my_empty_reg[7]_17 ; output [7:0]\my_empty_reg[7]_18 ; output [7:0]\my_empty_reg[7]_19 ; output [7:0]\my_empty_reg[7]_20 ; output [7:0]\my_empty_reg[7]_21 ; output [7:0]\my_empty_reg[7]_22 ; output [7:0]\my_empty_reg[7]_23 ; output [7:0]\my_empty_reg[7]_24 ; output [7:0]\my_empty_reg[7]_25 ; output [7:0]\my_empty_reg[7]_26 ; output [7:0]\my_empty_reg[7]_27 ; output [7:0]\my_empty_reg[7]_28 ; output [7:0]\my_empty_reg[7]_29 ; output [7:0]\my_empty_reg[7]_30 ; output [7:0]\my_empty_reg[7]_31 ; output [7:0]\my_empty_reg[7]_32 ; output [7:0]\my_empty_reg[7]_33 ; output [7:0]\my_empty_reg[7]_34 ; output [7:0]\my_empty_reg[7]_35 ; output [7:0]\my_empty_reg[7]_36 ; output [7:0]\my_empty_reg[7]_37 ; output lim_start_r_reg; output cal1_state_r1535_out; output mpr_rdlvl_start_r_reg; output [0:0]E; output [0:0]\cnt_shift_r_reg[0] ; output cnt_init_mr_r1; output prech_pending_r_reg_1; output rdlvl_start_pre_reg_0; output read_calib_reg_0; output temp_lmr_done; output stg1_wr_done; output \back_to_back_reads_4_1.num_reads_reg[0]_0 ; output \back_to_back_reads_4_1.num_reads_reg[1]_0 ; output \init_state_r_reg[4]_0 ; output burst_addr_r_reg_1; output oclkdelay_int_ref_req_reg_0; output \init_state_r_reg[5]_0 ; output ddr2_pre_flag_r_reg_1; output ddr2_refresh_flag_r_reg_0; output \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ; output \complex_row_cnt_ocal_reg[0]_0 ; output ddr3_lm_done_r; output \row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ; output cnt_pwron_reset_done_r_reg_0; output [3:0]\cnt_pwron_r_reg[7]_0 ; output cnt_pwron_cke_done_r_reg_0; output [2:0]\cnt_txpr_r_reg[2]_0 ; output [1:0]mem_init_done_r_reg_0; output mem_init_done_r_reg_1; output \init_state_r_reg[0]_0 ; output rdlvl_stg1_start_int; output \init_state_r_reg[2]_1 ; output cnt_txpr_done_r_reg_0; output \pi_dqs_found_all_bank_reg[1] ; output dqs_found_start_r_reg; output mux_wrdata_en; output mux_cmd_wren; output mux_reset_n; output [5:0]\data_offset_1_i1_reg[5] ; output [1:0]\rd_ptr_timing_reg[0]_3 ; output [1:0]\my_full_reg[3] ; output [10:0]\phy_ctl_wd_i1_reg[24] ; output [63:0]\my_empty_reg[7]_38 ; output [63:0]\my_empty_reg[7]_39 ; output [63:0]\my_empty_reg[7]_40 ; output [63:0]\my_empty_reg[7]_41 ; output [0:0]\samples_cnt_r_reg[11] ; output \wrcal_dqs_cnt_r_reg[0] ; output \rd_addr_reg_rep[7] ; output [0:0]\rd_addr_reg[0] ; output [1:0]cnt_init_af_r; output wrlvl_final_if_rst; output wr_level_start_r_reg; output wrcal_start_reg_0; output phy_write_calib; output phy_read_calib; output first_rdlvl_pat_r; input prbs_rdlvl_done_reg_rep; input CLK; input rdlvl_stg1_done_int_reg; input A_rst_primitives_reg; input rstdiv0_sync_r1_reg_rep__11; input wr_level_done_reg; input prbs_last_byte_done; input wrlvl_rank_done; input prbs_rdlvl_done_pulse0; input [0:0]rstdiv0_sync_r1_reg_rep__12; input reset_rd_addr0; input prech_req; input wrcal_resume_w; input rdlvl_last_byte_done; input dqs_found_done_r_reg; input rstdiv0_sync_r1_reg_rep__10; input cnt_pwron_cke_done_r_reg_1; input cnt_txpr_done_r_reg_1; input cnt_dllk_zqinit_done_r_reg_0; input cnt_init_mr_done_r_reg_0; input cnt_cmd_done_r_reg_0; input ddr2_pre_flag_r_reg_2; input cnt_init_af_done_r_reg_0; input burst_addr_r_reg_2; input prech_req_posedge_r_reg_0; input \init_state_r_reg[0]_1 ; input \rdlvl_start_dly0_r_reg[14]_0 ; input \init_state_r_reg[6]_0 ; input \cnt_pwron_r_reg[7]_1 ; input \init_state_r_reg[6]_1 ; input oclkdelay_center_calib_done_r_reg; input rdlvl_stg1_done_int_reg_0; input oclkdelay_calib_done_r_reg; input oclkdelay_calib_done_r_reg_0; input \dout_o_reg[11] ; input \dout_o_reg[11]_0 ; input [1:0]D; input wrcal_done_reg; input \dout_o_reg[9] ; input \dout_o_reg[9]_0 ; input \dout_o_reg[11]_1 ; input \dout_o_reg[11]_2 ; input \dout_o_reg[13] ; input \dout_o_reg[13]_0 ; input wrcal_done_reg_0; input \dout_o_reg[9]_1 ; input \dout_o_reg[9]_2 ; input \dout_o_reg[9]_3 ; input \dout_o_reg[9]_4 ; input \dout_o_reg[13]_1 ; input \dout_o_reg[13]_2 ; input \dout_o_reg[1] ; input \dout_o_reg[1]_0 ; input \dout_o_reg[13]_3 ; input \dout_o_reg[13]_4 ; input oclkdelay_calib_done_r_reg_1; input \dout_o_reg[11]_3 ; input \dout_o_reg[11]_4 ; input \dout_o_reg[13]_5 ; input \dout_o_reg[13]_6 ; input \dout_o_reg[15] ; input \dout_o_reg[7] ; input \dout_o_reg[15]_0 ; input \dout_o_reg[15]_1 ; input \dout_o_reg[7]_0 ; input \dout_o_reg[15]_2 ; input wrcal_done_reg_1; input \dout_o_reg[3] ; input \dout_o_reg[3]_0 ; input \dout_o_reg[7]_1 ; input \dout_o_reg[7]_2 ; input \dout_o_reg[8] ; input \dout_o_reg[8]_0 ; input \dout_o_reg[14] ; input \dout_o_reg[14]_0 ; input \dout_o_reg[6] ; input \dout_o_reg[14]_1 ; input \dout_o_reg[14]_2 ; input first_rdlvl_pat_r_reg_0; input wrcal_done_reg_2; input \dout_o_reg[2] ; input \dout_o_reg[2]_0 ; input \dout_o_reg[4] ; input \dout_o_reg[4]_0 ; input \dout_o_reg[8]_1 ; input \dout_o_reg[8]_2 ; input \dout_o_reg[10] ; input \dout_o_reg[10]_0 ; input \dout_o_reg[8]_3 ; input \dout_o_reg[8]_4 ; input \dout_o_reg[12] ; input \dout_o_reg[12]_0 ; input wrcal_done_reg_3; input wrcal_done_reg_4; input wrcal_done_reg_5; input wrcal_done_reg_6; input wrcal_done_reg_7; input wrcal_done_reg_8; input init_calib_complete_reg_rep__13; input rstdiv0_sync_r1_reg_rep__24; input reset_if_r9; input prbs_rdlvl_done_reg; input reset_if; input delay_done_r4_reg; input dqs_found_done_r_reg_0; input wrcal_done_reg_9; input oclkdelay_center_calib_start_r_reg; input oclk_calib_resume_r_reg; input prbs_rdlvl_done_reg_rep_0; input complex_oclk_calib_resume; input pi_dqs_found_rank_done; input wrcal_sanity_chk_done_reg; input wrcal_done_reg_10; input wrlvl_byte_redo; input wrcal_prech_req; input \init_state_r_reg[1]_1 ; input prbs_rdlvl_start_r; input oclkdelay_calib_done_r_reg_2; input [0:0]mc_cas_n; input init_calib_complete_reg_rep__6; input [33:0]\rd_ptr_reg[3] ; input \my_empty_reg[1] ; input [1:0]mem_out; input \my_empty_reg[1]_0 ; input [0:0]mc_ras_n; input [0:0]mc_odt; input [7:0]\rd_ptr_reg[3]_0 ; input \my_empty_reg[1]_1 ; input [0:0]mc_cke; input [0:0]mc_we_n; input [33:0]mc_address; input [31:0]\rd_ptr_reg[3]_1 ; input \my_empty_reg[1]_2 ; input init_calib_complete_reg_rep__5; input [8:0]mc_bank; input [255:0]\write_buffer.wr_buf_out_data_reg[255] ; input [63:0]\rd_ptr_reg[3]_2 ; input \my_empty_reg[1]_3 ; input [63:0]\rd_ptr_reg[3]_3 ; input \my_empty_reg[1]_4 ; input init_calib_complete_reg_rep__4; input [63:0]\rd_ptr_reg[3]_4 ; input \my_empty_reg[1]_5 ; input [63:0]\rd_ptr_reg[3]_5 ; input \my_empty_reg[1]_6 ; input init_calib_complete_reg_rep__3; input init_calib_complete_reg_rep__2; input init_calib_complete_reg_rep__1; input init_calib_complete_reg_rep__0; input init_calib_complete_reg_rep; input [1:0]\rd_byte_data_offset_reg[0][3] ; input init_dqsfound_done_r2; input [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ; input [1:0]\rd_byte_data_offset_reg[0][9] ; input [1:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ; input mpr_rdlvl_start_r; input phy_rddata_en_1; input mpr_rdlvl_done_r_reg; input \cnt_shift_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__22; input \mcGo_r_reg[15] ; input ck_addr_cmd_delay_done; input prbs_rdlvl_done_reg_0; input wrlvl_final_mux; input mpr_rdlvl_done_r_reg_0; input \init_state_r_reg[2]_2 ; input rstdiv0_sync_r1_reg_rep__23; input rdlvl_pi_incdec; input dqs_found_prech_req; input prbs_rdlvl_prech_req_reg; input complex_ocal_ref_req; input rdlvl_prech_req; input complex_pi_incdec_done; input wrcal_done_reg_11; input rdlvl_stg1_done_int_reg_1; input phy_if_empty_r_reg; input wrcal_sanity_chk_done_reg_0; input rdlvl_stg1_done_int_reg_2; input oclkdelay_calib_done_r_reg_3; input lim2init_prech_req; input ocd_prech_req; input oclkdelay_calib_done_r_reg_4; input cnt_cmd_done_r_reg_1; input oclkdelay_center_calib_start_r_reg_0; input oclk_calib_resume_r_reg_0; input mpr_rdlvl_done_r_reg_1; input dqs_found_done_r_reg_1; input wrlvl_byte_redo_reg; input mpr_rdlvl_done_r_reg_2; input oclkdelay_center_calib_done_r_reg_0; input complex_victim_inc_reg; input complex_ocal_num_samples_done_r; input reset_rd_addr; input dqs_found_done_r_reg_2; input prbs_last_byte_done_reg; input \rd_victim_sel_reg[1] ; input \rd_victim_sel_reg[0] ; input \rd_victim_sel_reg[2] ; input cnt_init_af_done_r_reg_1; input num_samples_done_r; input complex_init_pi_dec_done; input done_r_reg; input rdlvl_stg1_rank_done; input write_request_r_reg; input [2:0]complex_ocal_rd_victim_sel; input prbs_rdlvl_done_reg_rep_1; input prbs_rdlvl_done_reg_rep_2; input wrlvl_final_mux_reg; input oclkdelay_calib_done_r_reg_5; input wrlvl_byte_redo_reg_0; input mem_init_done_r_reg_2; input rdlvl_stg1_done_int_reg_3; input wrlvl_final_mux_reg_0; input prbs_rdlvl_done_reg_rep_3; input mpr_last_byte_done; input rdlvl_stg1_done_int_reg_4; input \dout_o_reg[0] ; input \dout_o_reg[0]_0 ; input [0:0]\pi_dqs_found_all_bank_reg[1]_0 ; input mc_wrdata_en; input init_calib_complete_reg_rep__14; input \cmd_pipe_plus.mc_data_offset_1_reg[0] ; input \cmd_pipe_plus.mc_data_offset_1_reg[1] ; input \cmd_pipe_plus.mc_data_offset_1_reg[2] ; input \cmd_pipe_plus.mc_data_offset_1_reg[3] ; input \cmd_pipe_plus.mc_data_offset_1_reg[4] ; input \cmd_pipe_plus.mc_data_offset_1_reg[5] ; input [1:0]mc_cmd; input \cmd_pipe_plus.mc_data_offset_reg[0] ; input \cmd_pipe_plus.mc_data_offset_reg[1] ; input \cmd_pipe_plus.mc_data_offset_reg[2] ; input \cmd_pipe_plus.mc_data_offset_reg[3] ; input \cmd_pipe_plus.mc_data_offset_reg[4] ; input \cmd_pipe_plus.mc_data_offset_reg[5] ; input init_calib_complete_reg_rep__12; input init_calib_complete_reg_rep__11; input init_calib_complete_reg_rep__10; input init_calib_complete_reg_rep__9; input init_calib_complete_reg_rep__8; input init_calib_complete_reg_rep__7; input \samples_cnt_r_reg[11]_0 ; input wrcal_sanity_chk_r_reg; input [0:0]\rd_addr_reg[3] ; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__23_0; input done_dqs_tap_inc; input p_81_in; input rstdiv0_sync_r1_reg_rep__23_1; input pi_dqs_found_done_r1_reg_0; input pi_dqs_found_done_r1_reg_1; input pi_dqs_found_done_r1_reg_2; input pi_dqs_found_done_r1_reg_3; input pi_dqs_found_done_r1_reg_4; input pi_dqs_found_done_r1_reg_5; input pi_dqs_found_done_r1_reg_6; input pi_dqs_found_done_r1_reg_7; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [0:0]rstdiv0_sync_r1_reg_rep__18; wire A_rst_primitives_reg; wire CLK; wire [1:0]D; wire [0:0]D0; wire [0:0]D1; wire [0:0]D2; wire [0:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ; wire [0:0]E; wire [5:0]Q; wire \back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ; wire \back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ; wire \back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ; wire \back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ; wire \back_to_back_reads_4_1.num_reads_reg[0]_0 ; wire \back_to_back_reads_4_1.num_reads_reg[1]_0 ; wire [1:0]bank_w; wire burst_addr_r_reg_0; wire burst_addr_r_reg_1; wire burst_addr_r_reg_2; wire cal1_state_r1535_out; wire [3:3]calib_cke; wire [2:0]calib_cmd; wire \calib_cmd[0]_i_1_n_0 ; wire \calib_cmd[1]_i_1_n_0 ; wire \calib_cmd[2]_i_1_n_0 ; wire \calib_cmd[2]_i_2_n_0 ; wire \calib_cmd[2]_i_3_n_0 ; wire \calib_cmd[2]_i_4_n_0 ; wire \calib_cmd[2]_i_5_n_0 ; wire \calib_cmd[2]_i_6_n_0 ; wire \calib_cmd[2]_i_7_n_0 ; wire \calib_cmd[2]_i_8_n_0 ; wire calib_complete; wire calib_ctl_wren; wire calib_ctl_wren0; wire [5:0]calib_data_offset_0; wire \calib_data_offset_0[2]_i_1_n_0 ; wire \calib_data_offset_0[3]_i_1_n_0 ; wire \calib_data_offset_0[3]_i_2_n_0 ; wire \calib_data_offset_0[5]_i_1_n_0 ; wire [5:0]calib_data_offset_1; wire \calib_data_offset_1[2]_i_1_n_0 ; wire \calib_data_offset_1[3]_i_1_n_0 ; wire [0:0]calib_odt; wire \calib_odt[0]_i_1_n_0 ; wire \calib_odt[0]_i_2_n_0 ; wire \calib_odt[0]_i_3_n_0 ; wire \calib_odt[0]_i_4_n_0 ; wire \calib_seq[0]_i_1_n_0 ; wire \calib_seq[1]_i_1_n_0 ; wire calib_wrdata_en; wire ck_addr_cmd_delay_done; wire clear; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_reg[5] ; wire cnt_cmd_done_m7_r; wire cnt_cmd_done_m7_r_i_1_n_0; wire cnt_cmd_done_m7_r_i_2_n_0; wire cnt_cmd_done_r; wire cnt_cmd_done_r_i_1_n_0; wire cnt_cmd_done_r_reg_0; wire cnt_cmd_done_r_reg_1; wire \cnt_cmd_r[0]_i_1_n_0 ; wire \cnt_cmd_r[1]_i_1_n_0 ; wire \cnt_cmd_r[2]_i_1_n_0 ; wire \cnt_cmd_r[3]_i_1_n_0 ; wire \cnt_cmd_r[4]_i_1_n_0 ; wire \cnt_cmd_r[5]_i_1_n_0 ; wire \cnt_cmd_r[6]_i_1_n_0 ; wire \cnt_cmd_r[6]_i_2_n_0 ; wire \cnt_cmd_r[6]_i_3_n_0 ; wire \cnt_cmd_r[6]_i_4_n_0 ; wire \cnt_cmd_r[6]_i_5_n_0 ; wire \cnt_cmd_r_reg_n_0_[0] ; wire \cnt_cmd_r_reg_n_0_[1] ; wire \cnt_cmd_r_reg_n_0_[2] ; wire \cnt_cmd_r_reg_n_0_[3] ; wire \cnt_cmd_r_reg_n_0_[4] ; wire \cnt_cmd_r_reg_n_0_[5] ; wire \cnt_cmd_r_reg_n_0_[6] ; wire cnt_dllk_zqinit_done_r; wire cnt_dllk_zqinit_done_r_reg_0; wire cnt_dllk_zqinit_r; wire [5:0]cnt_dllk_zqinit_r_reg__0; wire cnt_init_af_done_r; wire cnt_init_af_done_r_reg_0; wire cnt_init_af_done_r_reg_1; wire [1:0]cnt_init_af_r; wire \cnt_init_af_r[0]_i_1_n_0 ; wire \cnt_init_af_r[1]_i_1_n_0 ; wire cnt_init_mr_done_r; wire cnt_init_mr_done_r_reg_0; wire [1:0]cnt_init_mr_r; wire cnt_init_mr_r1; wire \cnt_init_mr_r[0]_i_1_n_0 ; wire \cnt_init_mr_r[1]_i_1_n_0 ; wire \cnt_init_mr_r_reg[1]_0 ; wire [9:0]cnt_pwron_ce_r_reg__0; wire cnt_pwron_cke_done_r; wire cnt_pwron_cke_done_r_reg_0; wire cnt_pwron_cke_done_r_reg_1; wire \cnt_pwron_r[6]_i_2_n_0 ; wire \cnt_pwron_r[8]_i_2_n_0 ; wire [3:0]\cnt_pwron_r_reg[7]_0 ; wire \cnt_pwron_r_reg[7]_1 ; wire [8:2]cnt_pwron_r_reg__0; wire cnt_pwron_reset_done_r; wire cnt_pwron_reset_done_r_reg_0; wire [0:0]\cnt_shift_r_reg[0] ; wire \cnt_shift_r_reg[0]_0 ; wire cnt_txpr_done_r; wire cnt_txpr_done_r_reg_0; wire cnt_txpr_done_r_reg_1; wire \cnt_txpr_r[7]_i_3_n_0 ; wire [2:0]\cnt_txpr_r_reg[2]_0 ; wire [7:3]cnt_txpr_r_reg__0; wire complex_act_start; wire complex_act_start0; wire complex_address0; wire \complex_address[9]_i_2_n_0 ; wire \complex_address[9]_i_3_n_0 ; wire \complex_address[9]_i_4_n_0 ; wire \complex_address_reg_n_0_[0] ; wire \complex_address_reg_n_0_[1] ; wire \complex_address_reg_n_0_[2] ; wire \complex_address_reg_n_0_[3] ; wire \complex_address_reg_n_0_[4] ; wire \complex_address_reg_n_0_[5] ; wire \complex_address_reg_n_0_[6] ; wire \complex_address_reg_n_0_[7] ; wire \complex_address_reg_n_0_[8] ; wire \complex_address_reg_n_0_[9] ; wire complex_byte_rd_done; wire complex_byte_rd_done_i_1_n_0; wire complex_byte_rd_done_i_2_n_0; wire complex_init_pi_dec_done; wire complex_mask_lim_done; wire complex_mask_lim_done_i_1_n_0; wire \complex_num_reads[0]_i_1_n_0 ; wire \complex_num_reads[1]_i_1_n_0 ; wire \complex_num_reads[1]_i_2_n_0 ; wire \complex_num_reads[2]_i_1_n_0 ; wire \complex_num_reads[2]_i_2_n_0 ; wire \complex_num_reads[2]_i_3_n_0 ; wire \complex_num_reads[2]_i_4_n_0 ; wire \complex_num_reads[2]_i_5_n_0 ; wire \complex_num_reads[2]_i_6_n_0 ; wire \complex_num_reads[3]_i_1_n_0 ; wire \complex_num_reads[3]_i_2_n_0 ; wire \complex_num_reads[3]_i_3_n_0 ; wire \complex_num_reads[3]_i_4_n_0 ; wire \complex_num_reads[3]_i_5_n_0 ; wire \complex_num_reads[3]_i_6_n_0 ; wire \complex_num_reads[3]_i_7_n_0 ; wire \complex_num_reads[3]_i_8_n_0 ; wire \complex_num_reads_dec[3]_i_1_n_0 ; wire \complex_num_reads_dec[3]_i_3_n_0 ; wire \complex_num_reads_dec[3]_i_4_n_0 ; wire [3:0]complex_num_reads_dec_reg__0; wire \complex_num_reads_reg_n_0_[0] ; wire \complex_num_reads_reg_n_0_[1] ; wire \complex_num_reads_reg_n_0_[2] ; wire \complex_num_reads_reg_n_0_[3] ; wire \complex_num_writes[0]_i_1_n_0 ; wire \complex_num_writes[0]_i_2_n_0 ; wire \complex_num_writes[1]_i_1_n_0 ; wire \complex_num_writes[1]_i_2_n_0 ; wire \complex_num_writes[2]_i_1_n_0 ; wire \complex_num_writes[2]_i_2_n_0 ; wire \complex_num_writes[2]_i_3_n_0 ; wire \complex_num_writes[2]_i_4_n_0 ; wire \complex_num_writes[2]_i_5_n_0 ; wire \complex_num_writes[2]_i_6_n_0 ; wire \complex_num_writes[2]_i_7_n_0 ; wire \complex_num_writes[2]_i_8_n_0 ; wire \complex_num_writes[3]_i_1_n_0 ; wire \complex_num_writes[3]_i_2_n_0 ; wire \complex_num_writes[3]_i_3_n_0 ; wire \complex_num_writes[3]_i_4_n_0 ; wire \complex_num_writes[4]_i_10_n_0 ; wire \complex_num_writes[4]_i_11_n_0 ; wire \complex_num_writes[4]_i_12_n_0 ; wire \complex_num_writes[4]_i_13_n_0 ; wire \complex_num_writes[4]_i_14_n_0 ; wire \complex_num_writes[4]_i_15_n_0 ; wire \complex_num_writes[4]_i_1_n_0 ; wire \complex_num_writes[4]_i_2_n_0 ; wire \complex_num_writes[4]_i_3_n_0 ; wire \complex_num_writes[4]_i_4_n_0 ; wire \complex_num_writes[4]_i_5_n_0 ; wire \complex_num_writes[4]_i_6_n_0 ; wire \complex_num_writes[4]_i_7_n_0 ; wire \complex_num_writes[4]_i_8_n_0 ; wire \complex_num_writes[4]_i_9_n_0 ; wire \complex_num_writes_dec[4]_i_2_n_0 ; wire \complex_num_writes_dec[4]_i_4_n_0 ; wire \complex_num_writes_dec[4]_i_5_n_0 ; wire \complex_num_writes_dec[4]_i_6_n_0 ; wire [4:0]complex_num_writes_dec_reg__0; wire \complex_num_writes_reg_n_0_[0] ; wire \complex_num_writes_reg_n_0_[1] ; wire \complex_num_writes_reg_n_0_[2] ; wire \complex_num_writes_reg_n_0_[3] ; wire \complex_num_writes_reg_n_0_[4] ; wire complex_ocal_num_samples_done_r; wire complex_ocal_odt_ext; wire complex_ocal_odt_ext_i_1_n_0; wire complex_ocal_odt_ext_i_2_n_0; wire complex_ocal_odt_ext_i_3_n_0; wire complex_ocal_odt_ext_i_4_n_0; wire [2:0]complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_reset_rd_addr; wire complex_ocal_reset_rd_addr0; wire complex_ocal_reset_rd_addr_i_2_n_0; wire complex_ocal_reset_rd_addr_i_3_n_0; wire complex_ocal_wr_start; wire complex_ocal_wr_start_i_1_n_0; wire complex_oclk_calib_resume; wire complex_oclkdelay_calib_done_r1; wire complex_oclkdelay_calib_start_int; wire complex_oclkdelay_calib_start_int_i_1_n_0; wire complex_oclkdelay_calib_start_int_i_2_n_0; wire complex_oclkdelay_calib_start_int_reg_0; wire complex_oclkdelay_calib_start_r1; wire complex_oclkdelay_calib_start_r2; wire complex_odt_ext; wire complex_odt_ext_i_1_n_0; wire complex_pi_incdec_done; wire complex_row0_rd_done; wire complex_row0_rd_done1; wire complex_row0_rd_done_i_1_n_0; wire complex_row0_rd_done_i_2_n_0; wire complex_row0_wr_done; wire complex_row0_wr_done0; wire [2:0]complex_row1_rd_cnt; wire \complex_row1_rd_cnt[0]_i_1_n_0 ; wire \complex_row1_rd_cnt[1]_i_1_n_0 ; wire \complex_row1_rd_cnt[2]_i_1_n_0 ; wire complex_row1_rd_done; wire complex_row1_rd_done_i_1_n_0; wire complex_row1_rd_done_i_2_n_0; wire complex_row1_rd_done_r1; wire complex_row1_wr_done; wire complex_row_cnt; wire complex_row_cnt_ocal; wire complex_row_cnt_ocal0; wire \complex_row_cnt_ocal[7]_i_5_n_0 ; wire \complex_row_cnt_ocal[7]_i_6_n_0 ; wire \complex_row_cnt_ocal[7]_i_7_n_0 ; wire \complex_row_cnt_ocal[7]_i_8_n_0 ; wire \complex_row_cnt_ocal[7]_i_9_n_0 ; wire \complex_row_cnt_ocal_reg[0]_0 ; wire [7:0]complex_row_cnt_ocal_reg__0; wire complex_sample_cnt_inc; wire complex_sample_cnt_inc0; wire complex_sample_cnt_inc_i_2_n_0; wire complex_sample_cnt_inc_r1; wire complex_sample_cnt_inc_r2; wire complex_victim_inc_reg; wire \complex_wait_cnt[3]_i_1_n_0 ; wire \complex_wait_cnt[3]_i_3_n_0 ; wire [3:0]complex_wait_cnt_reg__0; wire complex_wr_done; wire [5:0]\data_offset_1_i1_reg[5] ; wire ddr2_pre_flag_r_reg_0; wire ddr2_pre_flag_r_reg_1; wire ddr2_pre_flag_r_reg_2; wire ddr2_refresh_flag_r; wire ddr2_refresh_flag_r_reg_0; wire ddr3_lm_done_r; wire ddr3_lm_done_r_i_1_n_0; wire ddr3_lm_done_r_i_2_n_0; wire delay_done_r4_reg; wire detect_pi_found_dqs; wire detect_pi_found_dqs0; wire done_dqs_tap_inc; wire done_r_reg; wire \dout_o_reg[0] ; wire \dout_o_reg[0]_0 ; wire \dout_o_reg[10] ; wire \dout_o_reg[10]_0 ; wire \dout_o_reg[11] ; wire \dout_o_reg[11]_0 ; wire \dout_o_reg[11]_1 ; wire \dout_o_reg[11]_2 ; wire \dout_o_reg[11]_3 ; wire \dout_o_reg[11]_4 ; wire \dout_o_reg[12] ; wire \dout_o_reg[12]_0 ; wire \dout_o_reg[13] ; wire \dout_o_reg[13]_0 ; wire \dout_o_reg[13]_1 ; wire \dout_o_reg[13]_2 ; wire \dout_o_reg[13]_3 ; wire \dout_o_reg[13]_4 ; wire \dout_o_reg[13]_5 ; wire \dout_o_reg[13]_6 ; wire \dout_o_reg[14] ; wire \dout_o_reg[14]_0 ; wire \dout_o_reg[14]_1 ; wire \dout_o_reg[14]_2 ; wire \dout_o_reg[15] ; wire \dout_o_reg[15]_0 ; wire \dout_o_reg[15]_1 ; wire \dout_o_reg[15]_2 ; wire \dout_o_reg[1] ; wire \dout_o_reg[1]_0 ; wire \dout_o_reg[2] ; wire \dout_o_reg[2]_0 ; wire \dout_o_reg[3] ; wire \dout_o_reg[3]_0 ; wire \dout_o_reg[4] ; wire \dout_o_reg[4]_0 ; wire \dout_o_reg[6] ; wire \dout_o_reg[7] ; wire \dout_o_reg[7]_0 ; wire \dout_o_reg[7]_1 ; wire \dout_o_reg[7]_2 ; wire \dout_o_reg[8] ; wire \dout_o_reg[8]_0 ; wire \dout_o_reg[8]_1 ; wire \dout_o_reg[8]_2 ; wire \dout_o_reg[8]_3 ; wire \dout_o_reg[8]_4 ; wire \dout_o_reg[9] ; wire \dout_o_reg[9]_0 ; wire \dout_o_reg[9]_1 ; wire \dout_o_reg[9]_2 ; wire \dout_o_reg[9]_3 ; wire \dout_o_reg[9]_4 ; wire [1:0]dqs_asrt_cnt; wire \dqs_asrt_cnt[0]_i_1_n_0 ; wire \dqs_asrt_cnt[1]_i_1_n_0 ; wire dqs_found_done_r_reg; wire dqs_found_done_r_reg_0; wire dqs_found_done_r_reg_1; wire dqs_found_done_r_reg_2; wire dqs_found_prech_req; wire dqs_found_start_r_reg; wire \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ; wire \en_cnt_div4.wrlvl_odt_i_1_n_0 ; wire \en_cnt_div4.wrlvl_odt_i_2_n_0 ; wire [4:0]enable_wrlvl_cnt; wire enable_wrlvl_cnt0; wire first_rdlvl_pat_r; wire first_rdlvl_pat_r_i_1_n_0; wire first_rdlvl_pat_r_reg_0; wire first_wrcal_pat_r; wire first_wrcal_pat_r_i_1_n_0; wire first_wrcal_pat_r_i_2_n_0; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ; wire [1:1]\gen_rnk[0].mr1_r_reg[0]_196 ; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__0; wire init_calib_complete_reg_rep__1; wire init_calib_complete_reg_rep__10; wire init_calib_complete_reg_rep__11; wire init_calib_complete_reg_rep__12; wire init_calib_complete_reg_rep__13; wire init_calib_complete_reg_rep__14; wire init_calib_complete_reg_rep__2; wire init_calib_complete_reg_rep__3; wire init_calib_complete_reg_rep__4; wire init_calib_complete_reg_rep__5; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__7; wire init_calib_complete_reg_rep__8; wire init_calib_complete_reg_rep__9; wire init_complete_r1; wire init_complete_r1_reg_0; (* RTL_KEEP = "true" *) wire init_complete_r1_timing; wire init_complete_r2; (* RTL_KEEP = "true" *) wire init_complete_r_timing; wire init_dqsfound_done_r2; wire init_next_state1100_out; wire [6:0]init_state_r1; wire \init_state_r[0]_i_10_n_0 ; wire \init_state_r[0]_i_11_n_0 ; wire \init_state_r[0]_i_13_n_0 ; wire \init_state_r[0]_i_14_n_0 ; wire \init_state_r[0]_i_15_n_0 ; wire \init_state_r[0]_i_16_n_0 ; wire \init_state_r[0]_i_17_n_0 ; wire \init_state_r[0]_i_18_n_0 ; wire \init_state_r[0]_i_19_n_0 ; wire \init_state_r[0]_i_1_n_0 ; wire \init_state_r[0]_i_20_n_0 ; wire \init_state_r[0]_i_21_n_0 ; wire \init_state_r[0]_i_22_n_0 ; wire \init_state_r[0]_i_23_n_0 ; wire \init_state_r[0]_i_24_n_0 ; wire \init_state_r[0]_i_25_n_0 ; wire \init_state_r[0]_i_26_n_0 ; wire \init_state_r[0]_i_27_n_0 ; wire \init_state_r[0]_i_28_n_0 ; wire \init_state_r[0]_i_29_n_0 ; wire \init_state_r[0]_i_2_n_0 ; wire \init_state_r[0]_i_30_n_0 ; wire \init_state_r[0]_i_31_n_0 ; wire \init_state_r[0]_i_33_n_0 ; wire \init_state_r[0]_i_34_n_0 ; wire \init_state_r[0]_i_3_n_0 ; wire \init_state_r[0]_i_40_n_0 ; wire \init_state_r[0]_i_41_n_0 ; wire \init_state_r[0]_i_42_n_0 ; wire \init_state_r[0]_i_43_n_0 ; wire \init_state_r[0]_i_45_n_0 ; wire \init_state_r[0]_i_46_n_0 ; wire \init_state_r[0]_i_51_n_0 ; wire \init_state_r[0]_i_5_n_0 ; wire \init_state_r[0]_i_6_n_0 ; wire \init_state_r[0]_i_7_n_0 ; wire \init_state_r[0]_i_8_n_0 ; wire \init_state_r[0]_i_9_n_0 ; wire \init_state_r[1]_i_10_n_0 ; wire \init_state_r[1]_i_11_n_0 ; wire \init_state_r[1]_i_12_n_0 ; wire \init_state_r[1]_i_13_n_0 ; wire \init_state_r[1]_i_15_n_0 ; wire \init_state_r[1]_i_16_n_0 ; wire \init_state_r[1]_i_17_n_0 ; wire \init_state_r[1]_i_18_n_0 ; wire \init_state_r[1]_i_19_n_0 ; wire \init_state_r[1]_i_1_n_0 ; wire \init_state_r[1]_i_20_n_0 ; wire \init_state_r[1]_i_21_n_0 ; wire \init_state_r[1]_i_22_n_0 ; wire \init_state_r[1]_i_23_n_0 ; wire \init_state_r[1]_i_24_n_0 ; wire \init_state_r[1]_i_25_n_0 ; wire \init_state_r[1]_i_26_n_0 ; wire \init_state_r[1]_i_27_n_0 ; wire \init_state_r[1]_i_28_n_0 ; wire \init_state_r[1]_i_2_n_0 ; wire \init_state_r[1]_i_33_n_0 ; wire \init_state_r[1]_i_34_n_0 ; wire \init_state_r[1]_i_35_n_0 ; wire \init_state_r[1]_i_36_n_0 ; wire \init_state_r[1]_i_37_n_0 ; wire \init_state_r[1]_i_39_n_0 ; wire \init_state_r[1]_i_3_n_0 ; wire \init_state_r[1]_i_40_n_0 ; wire \init_state_r[1]_i_41_n_0 ; wire \init_state_r[1]_i_42_n_0 ; wire \init_state_r[1]_i_43_n_0 ; wire \init_state_r[1]_i_46_n_0 ; wire \init_state_r[1]_i_47_n_0 ; wire \init_state_r[1]_i_48_n_0 ; wire \init_state_r[1]_i_5_n_0 ; wire \init_state_r[1]_i_6_n_0 ; wire \init_state_r[1]_i_7_n_0 ; wire \init_state_r[1]_i_8_n_0 ; wire \init_state_r[1]_i_9_n_0 ; wire \init_state_r[2]_i_10_n_0 ; wire \init_state_r[2]_i_11_n_0 ; wire \init_state_r[2]_i_12_n_0 ; wire \init_state_r[2]_i_14_n_0 ; wire \init_state_r[2]_i_16_n_0 ; wire \init_state_r[2]_i_17_n_0 ; wire \init_state_r[2]_i_18_n_0 ; wire \init_state_r[2]_i_1_n_0 ; wire \init_state_r[2]_i_20_n_0 ; wire \init_state_r[2]_i_21_n_0 ; wire \init_state_r[2]_i_22_n_0 ; wire \init_state_r[2]_i_24_n_0 ; wire \init_state_r[2]_i_25_n_0 ; wire \init_state_r[2]_i_26_n_0 ; wire \init_state_r[2]_i_27_n_0 ; wire \init_state_r[2]_i_2_n_0 ; wire \init_state_r[2]_i_32_n_0 ; wire \init_state_r[2]_i_33_n_0 ; wire \init_state_r[2]_i_34_n_0 ; wire \init_state_r[2]_i_35_n_0 ; wire \init_state_r[2]_i_36_n_0 ; wire \init_state_r[2]_i_37_n_0 ; wire \init_state_r[2]_i_3_n_0 ; wire \init_state_r[2]_i_4_n_0 ; wire \init_state_r[2]_i_5_n_0 ; wire \init_state_r[2]_i_6_n_0 ; wire \init_state_r[2]_i_7_n_0 ; wire \init_state_r[2]_i_8_n_0 ; wire \init_state_r[2]_i_9_n_0 ; wire \init_state_r[3]_i_10_n_0 ; wire \init_state_r[3]_i_11_n_0 ; wire \init_state_r[3]_i_13_n_0 ; wire \init_state_r[3]_i_14_n_0 ; wire \init_state_r[3]_i_15_n_0 ; wire \init_state_r[3]_i_16_n_0 ; wire \init_state_r[3]_i_17_n_0 ; wire \init_state_r[3]_i_18_n_0 ; wire \init_state_r[3]_i_19_n_0 ; wire \init_state_r[3]_i_1_n_0 ; wire \init_state_r[3]_i_20_n_0 ; wire \init_state_r[3]_i_21_n_0 ; wire \init_state_r[3]_i_22_n_0 ; wire \init_state_r[3]_i_23_n_0 ; wire \init_state_r[3]_i_24_n_0 ; wire \init_state_r[3]_i_25_n_0 ; wire \init_state_r[3]_i_2_n_0 ; wire \init_state_r[3]_i_3_n_0 ; wire \init_state_r[3]_i_4_n_0 ; wire \init_state_r[3]_i_5_n_0 ; wire \init_state_r[3]_i_6_n_0 ; wire \init_state_r[3]_i_7_n_0 ; wire \init_state_r[4]_i_10_n_0 ; wire \init_state_r[4]_i_11_n_0 ; wire \init_state_r[4]_i_12_n_0 ; wire \init_state_r[4]_i_13_n_0 ; wire \init_state_r[4]_i_15_n_0 ; wire \init_state_r[4]_i_16_n_0 ; wire \init_state_r[4]_i_17_n_0 ; wire \init_state_r[4]_i_18_n_0 ; wire \init_state_r[4]_i_19_n_0 ; wire \init_state_r[4]_i_1_n_0 ; wire \init_state_r[4]_i_20_n_0 ; wire \init_state_r[4]_i_21_n_0 ; wire \init_state_r[4]_i_22_n_0 ; wire \init_state_r[4]_i_26_n_0 ; wire \init_state_r[4]_i_27_n_0 ; wire \init_state_r[4]_i_28_n_0 ; wire \init_state_r[4]_i_29_n_0 ; wire \init_state_r[4]_i_2_n_0 ; wire \init_state_r[4]_i_30_n_0 ; wire \init_state_r[4]_i_31_n_0 ; wire \init_state_r[4]_i_32_n_0 ; wire \init_state_r[4]_i_33_n_0 ; wire \init_state_r[4]_i_37_n_0 ; wire \init_state_r[4]_i_38_n_0 ; wire \init_state_r[4]_i_39_n_0 ; wire \init_state_r[4]_i_3_n_0 ; wire \init_state_r[4]_i_40_n_0 ; wire \init_state_r[4]_i_4_n_0 ; wire \init_state_r[4]_i_5_n_0 ; wire \init_state_r[4]_i_6_n_0 ; wire \init_state_r[4]_i_7_n_0 ; wire \init_state_r[4]_i_8_n_0 ; wire \init_state_r[4]_i_9_n_0 ; wire \init_state_r[5]_i_10_n_0 ; wire \init_state_r[5]_i_11_n_0 ; wire \init_state_r[5]_i_12_n_0 ; wire \init_state_r[5]_i_13_n_0 ; wire \init_state_r[5]_i_14_n_0 ; wire \init_state_r[5]_i_15_n_0 ; wire \init_state_r[5]_i_16_n_0 ; wire \init_state_r[5]_i_17_n_0 ; wire \init_state_r[5]_i_18_n_0 ; wire \init_state_r[5]_i_19_n_0 ; wire \init_state_r[5]_i_1_n_0 ; wire \init_state_r[5]_i_20_n_0 ; wire \init_state_r[5]_i_21_n_0 ; wire \init_state_r[5]_i_22_n_0 ; wire \init_state_r[5]_i_23_n_0 ; wire \init_state_r[5]_i_24_n_0 ; wire \init_state_r[5]_i_25_n_0 ; wire \init_state_r[5]_i_26_n_0 ; wire \init_state_r[5]_i_27_n_0 ; wire \init_state_r[5]_i_29_n_0 ; wire \init_state_r[5]_i_2_n_0 ; wire \init_state_r[5]_i_31_n_0 ; wire \init_state_r[5]_i_32_n_0 ; wire \init_state_r[5]_i_33_n_0 ; wire \init_state_r[5]_i_34_n_0 ; wire \init_state_r[5]_i_35_n_0 ; wire \init_state_r[5]_i_36_n_0 ; wire \init_state_r[5]_i_38_n_0 ; wire \init_state_r[5]_i_39_n_0 ; wire \init_state_r[5]_i_3_n_0 ; wire \init_state_r[5]_i_40_n_0 ; wire \init_state_r[5]_i_41_n_0 ; wire \init_state_r[5]_i_42_n_0 ; wire \init_state_r[5]_i_43_n_0 ; wire \init_state_r[5]_i_44_n_0 ; wire \init_state_r[5]_i_45_n_0 ; wire \init_state_r[5]_i_48_n_0 ; wire \init_state_r[5]_i_49_n_0 ; wire \init_state_r[5]_i_4_n_0 ; wire \init_state_r[5]_i_50_n_0 ; wire \init_state_r[5]_i_51_n_0 ; wire \init_state_r[5]_i_52_n_0 ; wire \init_state_r[5]_i_53_n_0 ; wire \init_state_r[5]_i_54_n_0 ; wire \init_state_r[5]_i_56_n_0 ; wire \init_state_r[5]_i_57_n_0 ; wire \init_state_r[5]_i_58_n_0 ; wire \init_state_r[5]_i_5_n_0 ; wire \init_state_r[5]_i_60_n_0 ; wire \init_state_r[5]_i_61_n_0 ; wire \init_state_r[5]_i_62_n_0 ; wire \init_state_r[5]_i_6_n_0 ; wire \init_state_r[5]_i_7_n_0 ; wire \init_state_r[5]_i_8_n_0 ; wire \init_state_r[5]_i_9_n_0 ; wire \init_state_r[6]_i_10_n_0 ; wire \init_state_r[6]_i_11_n_0 ; wire \init_state_r[6]_i_12_n_0 ; wire \init_state_r[6]_i_13_n_0 ; wire \init_state_r[6]_i_14_n_0 ; wire \init_state_r[6]_i_15_n_0 ; wire \init_state_r[6]_i_16_n_0 ; wire \init_state_r[6]_i_17_n_0 ; wire \init_state_r[6]_i_18_n_0 ; wire \init_state_r[6]_i_19_n_0 ; wire \init_state_r[6]_i_20_n_0 ; wire \init_state_r[6]_i_21_n_0 ; wire \init_state_r[6]_i_22_n_0 ; wire \init_state_r[6]_i_23_n_0 ; wire \init_state_r[6]_i_2_n_0 ; wire \init_state_r[6]_i_3_n_0 ; wire \init_state_r[6]_i_4_n_0 ; wire \init_state_r[6]_i_5_n_0 ; wire \init_state_r[6]_i_6_n_0 ; wire \init_state_r[6]_i_8_n_0 ; wire \init_state_r[6]_i_9_n_0 ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[1]_0 ; wire \init_state_r_reg[1]_1 ; wire \init_state_r_reg[2]_0 ; wire \init_state_r_reg[2]_1 ; wire \init_state_r_reg[2]_2 ; wire \init_state_r_reg[4]_0 ; wire \init_state_r_reg[5]_0 ; wire \init_state_r_reg[6]_0 ; wire \init_state_r_reg[6]_1 ; wire \init_state_r_reg_n_0_[3] ; wire lim2init_prech_req; wire lim_start_r_reg; wire mask_lim_done; wire mask_lim_done_i_1_n_0; wire \mcGo_r_reg[15] ; wire [33:0]mc_address; wire [8:0]mc_bank; wire [0:0]mc_cas_n; wire [0:0]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_odt; wire [0:0]mc_ras_n; wire [0:0]mc_we_n; wire mc_wrdata_en; wire mem_init_done_r; wire mem_init_done_r_i_1_n_0; wire [1:0]mem_init_done_r_reg_0; wire mem_init_done_r_reg_1; wire mem_init_done_r_reg_2; wire [1:0]mem_out; wire mpr_end_if_reset; wire mpr_end_if_reset0; wire mpr_last_byte_done; wire mpr_rdlvl_done_r_reg; wire mpr_rdlvl_done_r_reg_0; wire mpr_rdlvl_done_r_reg_1; wire mpr_rdlvl_done_r_reg_2; wire mpr_rdlvl_start_i_1_n_0; wire mpr_rdlvl_start_i_2_n_0; wire mpr_rdlvl_start_r; wire mpr_rdlvl_start_r_reg; wire mux_cmd_wren; wire mux_reset_n; wire mux_wrdata_en; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire [3:0]\my_empty_reg[7] ; wire [3:0]\my_empty_reg[7]_0 ; wire [3:0]\my_empty_reg[7]_1 ; wire [7:0]\my_empty_reg[7]_10 ; wire [7:0]\my_empty_reg[7]_11 ; wire [7:0]\my_empty_reg[7]_12 ; wire [7:0]\my_empty_reg[7]_13 ; wire [7:0]\my_empty_reg[7]_14 ; wire [7:0]\my_empty_reg[7]_15 ; wire [7:0]\my_empty_reg[7]_16 ; wire [7:0]\my_empty_reg[7]_17 ; wire [7:0]\my_empty_reg[7]_18 ; wire [7:0]\my_empty_reg[7]_19 ; wire [3:0]\my_empty_reg[7]_2 ; wire [7:0]\my_empty_reg[7]_20 ; wire [7:0]\my_empty_reg[7]_21 ; wire [7:0]\my_empty_reg[7]_22 ; wire [7:0]\my_empty_reg[7]_23 ; wire [7:0]\my_empty_reg[7]_24 ; wire [7:0]\my_empty_reg[7]_25 ; wire [7:0]\my_empty_reg[7]_26 ; wire [7:0]\my_empty_reg[7]_27 ; wire [7:0]\my_empty_reg[7]_28 ; wire [7:0]\my_empty_reg[7]_29 ; wire [3:0]\my_empty_reg[7]_3 ; wire [7:0]\my_empty_reg[7]_30 ; wire [7:0]\my_empty_reg[7]_31 ; wire [7:0]\my_empty_reg[7]_32 ; wire [7:0]\my_empty_reg[7]_33 ; wire [7:0]\my_empty_reg[7]_34 ; wire [7:0]\my_empty_reg[7]_35 ; wire [7:0]\my_empty_reg[7]_36 ; wire [7:0]\my_empty_reg[7]_37 ; wire [63:0]\my_empty_reg[7]_38 ; wire [63:0]\my_empty_reg[7]_39 ; wire [3:0]\my_empty_reg[7]_4 ; wire [63:0]\my_empty_reg[7]_40 ; wire [63:0]\my_empty_reg[7]_41 ; wire [3:0]\my_empty_reg[7]_5 ; wire [7:0]\my_empty_reg[7]_6 ; wire [7:0]\my_empty_reg[7]_7 ; wire [7:0]\my_empty_reg[7]_8 ; wire [7:0]\my_empty_reg[7]_9 ; wire [1:0]\my_full_reg[3] ; wire new_cnt_dqs_r_reg; wire [2:0]num_reads; wire num_reads0; wire num_refresh0; wire \num_refresh[3]_i_1_n_0 ; wire \num_refresh[3]_i_4_n_0 ; wire \num_refresh[3]_i_5_n_0 ; wire \num_refresh[3]_i_6_n_0 ; wire [3:0]num_refresh_reg__0; wire num_samples_done_r; wire \ocal_act_wait_cnt[3]_i_1_n_0 ; wire \ocal_act_wait_cnt[3]_i_3_n_0 ; wire [3:0]ocal_act_wait_cnt_reg__0; wire ocal_last_byte_done; wire ocd_prech_req; wire oclk_calib_resume_level; wire oclk_calib_resume_level_i_1_n_0; wire oclk_calib_resume_level_reg_0; wire oclk_calib_resume_r_reg; wire oclk_calib_resume_r_reg_0; wire [3:2]oclk_wr_cnt0; wire \oclk_wr_cnt[0]_i_1_n_0 ; wire \oclk_wr_cnt[1]_i_1_n_0 ; wire \oclk_wr_cnt[3]_i_1_n_0 ; wire \oclk_wr_cnt[3]_i_4_n_0 ; wire [3:0]oclk_wr_cnt_reg__0; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_calib_done_r_reg_1; wire oclkdelay_calib_done_r_reg_2; wire oclkdelay_calib_done_r_reg_3; wire oclkdelay_calib_done_r_reg_4; wire oclkdelay_calib_done_r_reg_5; wire oclkdelay_calib_start_int_i_1_n_0; wire oclkdelay_calib_start_pre; wire oclkdelay_center_calib_done_r_reg; wire oclkdelay_center_calib_done_r_reg_0; wire oclkdelay_center_calib_start_r_reg; wire oclkdelay_center_calib_start_r_reg_0; wire oclkdelay_int_ref_req0; wire oclkdelay_int_ref_req_i_1_n_0; wire oclkdelay_int_ref_req_i_2_n_0; wire oclkdelay_int_ref_req_i_3_n_0; wire oclkdelay_int_ref_req_i_5_n_0; wire oclkdelay_int_ref_req_reg_0; wire \oclkdelay_ref_cnt[0]_i_1_n_0 ; wire \oclkdelay_ref_cnt[0]_i_4_n_0 ; wire \oclkdelay_ref_cnt[0]_i_5_n_0 ; wire \oclkdelay_ref_cnt[0]_i_6_n_0 ; wire \oclkdelay_ref_cnt[0]_i_7_n_0 ; wire \oclkdelay_ref_cnt[12]_i_2_n_0 ; wire \oclkdelay_ref_cnt[12]_i_3_n_0 ; wire \oclkdelay_ref_cnt[4]_i_2_n_0 ; wire \oclkdelay_ref_cnt[4]_i_3_n_0 ; wire \oclkdelay_ref_cnt[4]_i_4_n_0 ; wire \oclkdelay_ref_cnt[4]_i_5_n_0 ; wire \oclkdelay_ref_cnt[8]_i_2_n_0 ; wire \oclkdelay_ref_cnt[8]_i_3_n_0 ; wire \oclkdelay_ref_cnt[8]_i_4_n_0 ; wire \oclkdelay_ref_cnt[8]_i_5_n_0 ; wire [13:0]oclkdelay_ref_cnt_reg; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_0 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_1 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_2 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_3 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_4 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_5 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_6 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_7 ; wire \oclkdelay_ref_cnt_reg[12]_i_1_n_3 ; wire \oclkdelay_ref_cnt_reg[12]_i_1_n_6 ; wire \oclkdelay_ref_cnt_reg[12]_i_1_n_7 ; wire \oclkdelay_ref_cnt_reg[13]_0 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_0 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_1 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_2 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_3 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_4 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_5 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_6 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_7 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_0 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_1 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_2 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_3 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_4 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_5 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_6 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_7 ; wire [5:5]oclkdelay_start_dly_r; wire \oclkdelay_start_dly_r_reg[4]_srl5_n_0 ; wire \odd_cwl.phy_cas_n[1]_i_1_n_0 ; wire \odd_cwl.phy_cas_n_reg[1]_0 ; wire \odd_cwl.phy_ras_n[1]_i_1_n_0 ; wire \odd_cwl.phy_ras_n[1]_i_2_n_0 ; wire \odd_cwl.phy_we_n[1]_i_1_n_0 ; wire \one_rank.stg1_wr_done_i_1_n_0 ; wire \one_rank.stg1_wr_done_reg_0 ; wire \one_rank_complex.complex_wr_done_i_1_n_0 ; wire \one_rank_complex.complex_wr_done_i_2_n_0 ; wire \one_rank_complex.complex_wr_done_i_3_n_0 ; wire \one_rank_complex.complex_wr_done_i_4_n_0 ; wire \one_rank_complex.complex_wr_done_i_5_n_0 ; wire p_0_in0_in; wire [9:0]p_0_in__0; wire [8:0]p_0_in__0__0; wire [7:0]p_0_in__1; wire [3:1]p_0_in__2; wire [7:0]p_0_in__3; wire [3:0]p_0_in__4; wire [7:0]p_0_in__5; wire [3:0]p_0_in__6; wire [4:0]p_0_in__7; wire [3:0]p_0_in__8; wire [3:0]p_0_in__9; wire p_81_in; wire [11:9]phy_bank; wire [1:1]phy_cas_n; wire [1:1]phy_cs_n; wire [10:0]\phy_ctl_wd_i1_reg[24] ; wire [31:0]phy_dout; wire phy_if_empty_r_reg; wire [1:1]phy_ras_n; wire phy_rddata_en_1; wire phy_read_calib; wire phy_reset_n; wire [1:1]phy_we_n; wire [255:24]phy_wrdata; wire phy_wrdata_en; wire phy_write_calib; wire pi_calib_done; wire pi_calib_done_r; wire pi_calib_done_r_i_1_n_0; wire pi_calib_rank_done_r; wire \pi_dqs_found_all_bank_reg[1] ; wire [0:0]\pi_dqs_found_all_bank_reg[1]_0 ; wire pi_dqs_found_done_r1; wire pi_dqs_found_done_r1_reg_0; wire pi_dqs_found_done_r1_reg_1; wire pi_dqs_found_done_r1_reg_2; wire pi_dqs_found_done_r1_reg_3; wire pi_dqs_found_done_r1_reg_4; wire pi_dqs_found_done_r1_reg_5; wire pi_dqs_found_done_r1_reg_6; wire pi_dqs_found_done_r1_reg_7; wire pi_dqs_found_rank_done; wire pi_dqs_found_start_i_1_n_0; (* async_reg = "true" *) wire pi_phase_locked_all_r1; (* async_reg = "true" *) wire pi_phase_locked_all_r2; (* async_reg = "true" *) wire pi_phase_locked_all_r3; (* async_reg = "true" *) wire pi_phase_locked_all_r4; wire prbs_gen_clk_en; wire prbs_gen_clk_en040_out; wire prbs_gen_clk_en_i_1_n_0; wire prbs_gen_clk_en_i_2_n_0; wire prbs_gen_clk_en_i_3_n_0; wire prbs_gen_clk_en_i_5_n_0; wire prbs_gen_oclk_clk_en; wire prbs_gen_oclk_clk_en_i_1_n_0; wire prbs_gen_oclk_clk_en_i_2_n_0; wire prbs_gen_oclk_clk_en_i_3_n_0; wire prbs_gen_oclk_clk_en_i_4_n_0; wire prbs_gen_oclk_clk_en_i_5_n_0; wire prbs_gen_oclk_clk_en_i_6_n_0; wire prbs_gen_oclk_clk_en_i_7_n_0; wire prbs_gen_oclk_clk_en_i_8_n_0; wire prbs_gen_oclk_clk_en_i_9_n_0; wire prbs_last_byte_done; wire prbs_last_byte_done_r; wire prbs_last_byte_done_reg; wire prbs_rdlvl_done_pulse; wire prbs_rdlvl_done_pulse0; wire prbs_rdlvl_done_r1; wire prbs_rdlvl_done_r2; wire prbs_rdlvl_done_r3; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_0; wire prbs_rdlvl_done_reg_rep; wire prbs_rdlvl_done_reg_rep_0; wire prbs_rdlvl_done_reg_rep_1; wire prbs_rdlvl_done_reg_rep_2; wire prbs_rdlvl_done_reg_rep_3; wire prbs_rdlvl_prech_req_reg; wire prbs_rdlvl_start_i_1_n_0; wire prbs_rdlvl_start_i_2_n_0; wire prbs_rdlvl_start_i_3_n_0; wire prbs_rdlvl_start_r; wire prbs_rdlvl_start_r_reg; wire prech_done; wire \prech_done_dly_r_reg[15]_srl16_n_0 ; wire prech_done_pre; wire prech_done_r2; wire prech_done_r3; wire prech_pending_r; wire prech_pending_r_i_3_n_0; wire prech_pending_r_i_4_n_0; wire prech_pending_r_i_5_n_0; wire prech_pending_r_i_6_n_0; wire prech_pending_r_i_7_n_0; wire prech_pending_r_i_8_n_0; wire prech_pending_r_i_9_n_0; wire prech_pending_r_reg_0; wire prech_pending_r_reg_1; wire prech_req; wire prech_req_posedge_r0; wire prech_req_posedge_r_i_2_n_0; wire prech_req_posedge_r_reg_0; wire prech_req_r; wire pwron_ce_r; wire pwron_ce_r_i_2_n_0; wire pwron_ce_r_i_3_n_0; wire [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ; wire [1:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ; wire [0:0]\rd_addr_reg[0] ; wire [0:0]\rd_addr_reg[3] ; wire \rd_addr_reg_rep[7] ; wire [1:0]\rd_byte_data_offset_reg[0][3] ; wire [1:0]\rd_byte_data_offset_reg[0][9] ; wire [33:0]\rd_ptr_reg[3] ; wire [7:0]\rd_ptr_reg[3]_0 ; wire [31:0]\rd_ptr_reg[3]_1 ; wire [63:0]\rd_ptr_reg[3]_2 ; wire [63:0]\rd_ptr_reg[3]_3 ; wire [63:0]\rd_ptr_reg[3]_4 ; wire [63:0]\rd_ptr_reg[3]_5 ; wire [33:0]\rd_ptr_timing_reg[0] ; wire [7:0]\rd_ptr_timing_reg[0]_0 ; wire [7:0]\rd_ptr_timing_reg[0]_1 ; wire [3:0]\rd_ptr_timing_reg[0]_2 ; wire [1:0]\rd_ptr_timing_reg[0]_3 ; wire \rd_victim_sel_reg[0] ; wire \rd_victim_sel_reg[1] ; wire \rd_victim_sel_reg[2] ; wire rdlvl_last_byte_done; wire rdlvl_last_byte_done_r; wire rdlvl_pi_incdec; wire rdlvl_prech_req; wire [0:0]rdlvl_start_dly0_r; wire \rdlvl_start_dly0_r_reg[13]_srl14_n_0 ; wire \rdlvl_start_dly0_r_reg[14]_0 ; wire rdlvl_start_pre; wire rdlvl_start_pre_reg_0; wire rdlvl_stg1_done_int_reg; wire rdlvl_stg1_done_int_reg_0; wire rdlvl_stg1_done_int_reg_1; wire rdlvl_stg1_done_int_reg_2; wire rdlvl_stg1_done_int_reg_3; wire rdlvl_stg1_done_int_reg_4; wire rdlvl_stg1_done_r1; wire rdlvl_stg1_rank_done; wire rdlvl_stg1_start_int; wire rdlvl_stg1_start_int_i_1_n_0; wire rdlvl_stg1_start_int_i_2_n_0; wire rdlvl_stg1_start_r_reg; wire read_calib_i_1_n_0; wire read_calib_i_2_n_0; wire read_calib_reg_0; wire reg_ctrl_cnt_r; wire \reg_ctrl_cnt_r[0]_i_1_n_0 ; wire \reg_ctrl_cnt_r_reg[3]_0 ; wire [3:0]reg_ctrl_cnt_r_reg__0; wire reset_if; wire reset_if_i_2_n_0; wire reset_if_r9; wire reset_if_reg; wire reset_rd_addr; wire reset_rd_addr0; wire reset_rd_addr_r1; wire \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__12; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__23_0; wire rstdiv0_sync_r1_reg_rep__23_1; wire rstdiv0_sync_r1_reg_rep__24; wire [0:0]\samples_cnt_r_reg[11] ; wire \samples_cnt_r_reg[11]_0 ; wire stg1_wr_done; wire \stg1_wr_rd_cnt[0]_i_1_n_0 ; wire \stg1_wr_rd_cnt[1]_i_1_n_0 ; wire \stg1_wr_rd_cnt[2]_i_1_n_0 ; wire \stg1_wr_rd_cnt[3]_i_1_n_0 ; wire \stg1_wr_rd_cnt[3]_i_2_n_0 ; wire \stg1_wr_rd_cnt[4]_i_1_n_0 ; wire \stg1_wr_rd_cnt[4]_i_3_n_0 ; wire \stg1_wr_rd_cnt[4]_i_4_n_0 ; wire \stg1_wr_rd_cnt[4]_i_5_n_0 ; wire \stg1_wr_rd_cnt[4]_i_6_n_0 ; wire \stg1_wr_rd_cnt[5]_i_1_n_0 ; wire \stg1_wr_rd_cnt[5]_i_2_n_0 ; wire \stg1_wr_rd_cnt[6]_i_1_n_0 ; wire \stg1_wr_rd_cnt[6]_i_2_n_0 ; wire \stg1_wr_rd_cnt[7]_i_1_n_0 ; wire \stg1_wr_rd_cnt[8]_i_1_n_0 ; wire \stg1_wr_rd_cnt[8]_i_2_n_0 ; wire \stg1_wr_rd_cnt[8]_i_3_n_0 ; wire \stg1_wr_rd_cnt[8]_i_4_n_0 ; wire \stg1_wr_rd_cnt[8]_i_5_n_0 ; wire \stg1_wr_rd_cnt[8]_i_6_n_0 ; wire \stg1_wr_rd_cnt_reg_n_0_[0] ; wire \stg1_wr_rd_cnt_reg_n_0_[1] ; wire \stg1_wr_rd_cnt_reg_n_0_[2] ; wire \stg1_wr_rd_cnt_reg_n_0_[3] ; wire \stg1_wr_rd_cnt_reg_n_0_[4] ; wire \stg1_wr_rd_cnt_reg_n_0_[5] ; wire \stg1_wr_rd_cnt_reg_n_0_[6] ; wire \stg1_wr_rd_cnt_reg_n_0_[7] ; wire \stg1_wr_rd_cnt_reg_n_0_[8] ; wire temp_lmr_done; wire \victim_sel[0]_i_1_n_0 ; wire \victim_sel[0]_i_2_n_0 ; wire \victim_sel[1]_i_1_n_0 ; wire \victim_sel[1]_i_2_n_0 ; wire \victim_sel[2]_i_1_n_0 ; wire \victim_sel[2]_i_2_n_0 ; wire \victim_sel[2]_i_3_n_0 ; wire \victim_sel[2]_i_4_n_0 ; wire \victim_sel[2]_i_5_n_0 ; wire \victim_sel_reg_n_0_[0] ; wire \victim_sel_reg_n_0_[1] ; wire \victim_sel_reg_n_0_[2] ; wire [7:0]\victim_sel_rotate.sel_reg[31] ; wire wl_sm_start; wire \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ; wire \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ; wire wr_level_done_reg; wire wr_level_dqs_asrt; wire wr_level_dqs_asrt_i_1_n_0; wire wr_level_dqs_asrt_r1; wire wr_level_start_r_reg; wire wr_lvl_start_i_1_n_0; wire wr_victim_inc; wire wr_victim_inc0; wire wr_victim_inc_i_2_n_0; wire wr_victim_inc_i_3_n_0; wire [2:0]wr_victim_sel; wire \wr_victim_sel[0]_i_1_n_0 ; wire \wr_victim_sel[1]_i_1_n_0 ; wire \wr_victim_sel[2]_i_1_n_0 ; wire [2:0]wr_victim_sel_ocal; wire \wr_victim_sel_ocal[0]_i_1_n_0 ; wire \wr_victim_sel_ocal[1]_i_1_n_0 ; wire \wr_victim_sel_ocal[2]_i_1_n_0 ; wire wrcal_done_reg; wire wrcal_done_reg_0; wire wrcal_done_reg_1; wire wrcal_done_reg_10; wire wrcal_done_reg_11; wire wrcal_done_reg_2; wire wrcal_done_reg_3; wire wrcal_done_reg_4; wire wrcal_done_reg_5; wire wrcal_done_reg_6; wire wrcal_done_reg_7; wire wrcal_done_reg_8; wire wrcal_done_reg_9; wire \wrcal_dqs_cnt_r_reg[0] ; wire wrcal_final_chk; wire wrcal_final_chk_i_1_n_0; wire wrcal_final_chk_i_2_n_0; wire wrcal_prech_req; wire wrcal_rd_wait; wire wrcal_rd_wait_i_1_n_0; wire wrcal_reads; wire wrcal_reads05_out; wire \wrcal_reads[0]_i_1_n_0 ; wire \wrcal_reads[1]_i_1_n_0 ; wire \wrcal_reads[2]_i_1_n_0 ; wire \wrcal_reads[3]_i_1_n_0 ; wire \wrcal_reads[4]_i_1_n_0 ; wire \wrcal_reads[5]_i_1_n_0 ; wire \wrcal_reads[5]_i_2_n_0 ; wire \wrcal_reads[6]_i_1_n_0 ; wire \wrcal_reads[7]_i_2_n_0 ; wire \wrcal_reads[7]_i_3_n_0 ; wire \wrcal_reads[7]_i_5_n_0 ; wire \wrcal_reads[7]_i_6_n_0 ; wire \wrcal_reads[7]_i_7_n_0 ; wire \wrcal_reads_reg_n_0_[0] ; wire \wrcal_reads_reg_n_0_[1] ; wire \wrcal_reads_reg_n_0_[2] ; wire \wrcal_reads_reg_n_0_[3] ; wire \wrcal_reads_reg_n_0_[4] ; wire \wrcal_reads_reg_n_0_[5] ; wire \wrcal_reads_reg_n_0_[6] ; wire \wrcal_reads_reg_n_0_[7] ; wire wrcal_resume_r; wire wrcal_resume_w; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done_reg; wire wrcal_sanity_chk_done_reg_0; wire wrcal_sanity_chk_r_reg; wire [5:5]wrcal_start_dly_r; wire \wrcal_start_dly_r_reg[4]_srl5_n_0 ; wire wrcal_start_i_1_n_0; wire wrcal_start_pre; wire wrcal_start_reg_0; wire [3:2]wrcal_wr_cnt0; wire \wrcal_wr_cnt[0]_i_1_n_0 ; wire \wrcal_wr_cnt[1]_i_1_n_0 ; wire \wrcal_wr_cnt[3]_i_1_n_0 ; wire \wrcal_wr_cnt[3]_i_2_n_0 ; wire \wrcal_wr_cnt[3]_i_4_n_0 ; wire [3:0]wrcal_wr_cnt_reg__0; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ; wire [255:0]\write_buffer.wr_buf_out_data_reg[255] ; wire write_calib_i_1_n_0; wire write_calib_i_2_n_0; wire write_request_r_reg; wire wrlvl_active; wire wrlvl_active_i_1_n_0; wire wrlvl_active_r1; wire wrlvl_byte_redo; wire wrlvl_byte_redo_reg; wire wrlvl_byte_redo_reg_0; wire wrlvl_done_r; wire wrlvl_done_r1; wire wrlvl_final_if_rst; wire wrlvl_final_if_rst_i_1_n_0; wire wrlvl_final_if_rst_i_2_n_0; wire wrlvl_final_mux; wire wrlvl_final_mux_reg; wire wrlvl_final_mux_reg_0; wire wrlvl_odt; wire wrlvl_odt_ctl; wire wrlvl_odt_ctl_i_1_n_0; wire wrlvl_odt_ctl_i_2_n_0; wire wrlvl_odt_ctl_i_3_n_0; wire wrlvl_rank_done; wire wrlvl_rank_done_r1; wire wrlvl_rank_done_r6_reg_srl5_n_0; wire wrlvl_rank_done_r7; wire [3:1]\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED ; assign in0 = init_complete_r_timing; assign out = init_complete_r1_timing; LUT6 #( .INIT(64'h000000000000E0EE)) \DDR3_1rank.phy_int_cs_n[1]_i_1 (.I0(\odd_cwl.phy_cas_n_reg[1]_0 ), .I1(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ), .I2(rdlvl_stg1_start_int_i_2_n_0), .I3(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ), .I4(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ), .I5(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ), .O(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \DDR3_1rank.phy_int_cs_n[1]_i_2 (.I0(\calib_cmd[2]_i_2_n_0 ), .I1(\calib_cmd[2]_i_3_n_0 ), .O(\odd_cwl.phy_cas_n_reg[1]_0 )); LUT6 #( .INIT(64'h0000000000000010)) \DDR3_1rank.phy_int_cs_n[1]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[5]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[3]), .I5(Q[4]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair594" *) LUT3 #( .INIT(8'h04)) \DDR3_1rank.phy_int_cs_n[1]_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[0]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAABBA)) \DDR3_1rank.phy_int_cs_n[1]_i_5 (.I0(write_calib_i_2_n_0), .I1(read_calib_i_2_n_0), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(prbs_rdlvl_start_i_2_n_0), .I5(temp_lmr_done), .O(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \DDR3_1rank.phy_int_cs_n[1]_i_6 (.I0(\num_refresh[3]_i_4_n_0 ), .I1(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ), .I2(\victim_sel[2]_i_5_n_0 ), .I3(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ), .I4(complex_row1_rd_done_i_2_n_0), .I5(\cnt_init_mr_r_reg[1]_0 ), .O(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000040000)) \DDR3_1rank.phy_int_cs_n[1]_i_7 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[5]), .I4(Q[3]), .I5(Q[4]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \DDR3_1rank.phy_int_cs_n[1]_i_8 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[4]), .I3(prbs_rdlvl_start_i_2_n_0), .I4(Q[5]), .I5(Q[3]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 )); FDSE #( .INIT(1'b1)) \DDR3_1rank.phy_int_cs_n_reg[1] (.C(CLK), .CE(1'b1), .D(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ), .Q(phy_cs_n), .S(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'h2)) \FSM_sequential_cal1_state_r[5]_i_10 (.I0(mpr_rdlvl_start_r_reg), .I1(mpr_rdlvl_start_r), .O(cal1_state_r1535_out)); LUT6 #( .INIT(64'h0000000066666706)) \back_to_back_reads_4_1.num_reads[0]_i_1 (.I0(num_reads[0]), .I1(num_reads0), .I2(Q[1]), .I3(Q[0]), .I4(\back_to_back_reads_4_1.num_reads_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair501" *) LUT3 #( .INIT(8'hFE)) \back_to_back_reads_4_1.num_reads[0]_i_2 (.I0(num_reads[0]), .I1(num_reads[2]), .I2(num_reads[1]), .O(num_reads0)); (* SOFT_HLUTNM = "soft_lutpair518" *) LUT5 #( .INIT(32'hFFFFFEFF)) \back_to_back_reads_4_1.num_reads[0]_i_3 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[5]), .I3(Q[3]), .I4(Q[4]), .O(\back_to_back_reads_4_1.num_reads_reg[0]_0 )); LUT6 #( .INIT(64'h00000000CC320000)) \back_to_back_reads_4_1.num_reads[1]_i_1 (.I0(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ), .I1(num_reads[1]), .I2(num_reads[2]), .I3(num_reads[0]), .I4(\back_to_back_reads_4_1.num_reads_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \back_to_back_reads_4_1.num_reads[1]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(Q[4]), .I2(Q[3]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 )); LUT5 #( .INIT(32'h00C80000)) \back_to_back_reads_4_1.num_reads[2]_i_1 (.I0(num_reads[1]), .I1(num_reads[2]), .I2(num_reads[0]), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(\back_to_back_reads_4_1.num_reads_reg[1]_0 ), .O(\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \back_to_back_reads_4_1.num_reads_reg[0] (.C(CLK), .CE(1'b1), .D(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ), .Q(num_reads[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \back_to_back_reads_4_1.num_reads_reg[1] (.C(CLK), .CE(1'b1), .D(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ), .Q(num_reads[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \back_to_back_reads_4_1.num_reads_reg[2] (.C(CLK), .CE(1'b1), .D(\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ), .Q(num_reads[2]), .R(1'b0)); LUT6 #( .INIT(64'h0000010000009595)) burst_addr_r_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(\init_state_r[5]_i_26_n_0 ), .I5(Q[3]), .O(burst_addr_r_reg_1)); FDRE #( .INIT(1'b0)) burst_addr_r_reg (.C(CLK), .CE(1'b1), .D(burst_addr_r_reg_2), .Q(burst_addr_r_reg_0), .R(1'b0)); FDRE #( .INIT(1'b0)) \calib_cke_reg[0] (.C(CLK), .CE(1'b1), .D(cnt_pwron_cke_done_r), .Q(calib_cke), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair572" *) LUT3 #( .INIT(8'hFB)) \calib_cmd[0]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_cmd[2]_i_3_n_0 ), .O(\calib_cmd[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair572" *) LUT3 #( .INIT(8'h40)) \calib_cmd[1]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_cmd[2]_i_3_n_0 ), .O(\calib_cmd[1]_i_1_n_0 )); LUT3 #( .INIT(8'h04)) \calib_cmd[2]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_cmd[2]_i_3_n_0 ), .O(\calib_cmd[2]_i_1_n_0 )); LUT3 #( .INIT(8'h01)) \calib_cmd[2]_i_2 (.I0(\wrcal_wr_cnt[3]_i_2_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I2(\calib_cmd[2]_i_4_n_0 ), .O(\calib_cmd[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFEFEFEFEFFFFFEFF)) \calib_cmd[2]_i_3 (.I0(\calib_cmd[2]_i_5_n_0 ), .I1(\calib_cmd[2]_i_6_n_0 ), .I2(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ), .I3(\calib_cmd[2]_i_7_n_0 ), .I4(\calib_cmd[2]_i_8_n_0 ), .I5(rdlvl_pi_incdec), .O(\calib_cmd[2]_i_3_n_0 )); LUT6 #( .INIT(64'h08080000000000FF)) \calib_cmd[2]_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(read_calib_i_2_n_0), .I3(prbs_rdlvl_start_i_3_n_0), .I4(Q[0]), .I5(Q[1]), .O(\calib_cmd[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000040048)) \calib_cmd[2]_i_5 (.I0(Q[1]), .I1(Q[0]), .I2(Q[3]), .I3(\init_state_r[5]_i_26_n_0 ), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\calib_cmd[2]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000040200)) \calib_cmd[2]_i_6 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[0]), .I3(Q[2]), .I4(Q[3]), .I5(\init_state_r[5]_i_26_n_0 ), .O(\calib_cmd[2]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair504" *) LUT5 #( .INIT(32'hFFFFFDFF)) \calib_cmd[2]_i_7 (.I0(Q[0]), .I1(read_calib_i_2_n_0), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[1]), .O(\calib_cmd[2]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000000100)) \calib_cmd[2]_i_8 (.I0(Q[1]), .I1(Q[0]), .I2(Q[4]), .I3(Q[3]), .I4(Q[5]), .I5(oclk_calib_resume_level_reg_0), .O(\calib_cmd[2]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \calib_cmd_reg[0] (.C(CLK), .CE(1'b1), .D(\calib_cmd[0]_i_1_n_0 ), .Q(calib_cmd[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \calib_cmd_reg[1] (.C(CLK), .CE(1'b1), .D(\calib_cmd[1]_i_1_n_0 ), .Q(calib_cmd[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \calib_cmd_reg[2] (.C(CLK), .CE(1'b1), .D(\calib_cmd[2]_i_1_n_0 ), .Q(calib_cmd[2]), .R(1'b0)); LUT2 #( .INIT(4'h8)) calib_ctl_wren_i_1 (.I0(cnt_pwron_cke_done_r), .I1(\mcGo_r_reg[15] ), .O(calib_ctl_wren0)); FDRE #( .INIT(1'b0)) calib_ctl_wren_reg (.C(CLK), .CE(1'b1), .D(calib_ctl_wren0), .Q(calib_ctl_wren), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_0[2]_i_1 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][3] [0]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [0]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_0[2]_i_1_n_0 )); LUT2 #( .INIT(4'hB)) \calib_data_offset_0[3]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .O(\calib_data_offset_0[3]_i_1_n_0 )); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_0[3]_i_2 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][3] [1]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [1]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_0[3]_i_2_n_0 )); LUT4 #( .INIT(16'hBFFF)) \calib_data_offset_0[5]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(pi_calib_done), .I3(\calib_cmd[2]_i_3_n_0 ), .O(\calib_data_offset_0[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_0_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_3), .Q(calib_data_offset_0[0]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_0_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_2), .Q(calib_data_offset_0[1]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \calib_data_offset_0_reg[2] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_0[2]_i_1_n_0 ), .Q(calib_data_offset_0[2]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \calib_data_offset_0_reg[3] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_0[3]_i_2_n_0 ), .Q(calib_data_offset_0[3]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_0_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_1), .Q(calib_data_offset_0[4]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_0_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_0), .Q(calib_data_offset_0[5]), .R(\calib_data_offset_0[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_1[2]_i_1 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][9] [0]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [0]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_1[2]_i_1_n_0 )); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_1[3]_i_1 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][9] [1]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [1]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_1[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_1_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_7), .Q(calib_data_offset_1[0]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_1_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_6), .Q(calib_data_offset_1[1]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \calib_data_offset_1_reg[2] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_1[2]_i_1_n_0 ), .Q(calib_data_offset_1[2]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \calib_data_offset_1_reg[3] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_1[3]_i_1_n_0 ), .Q(calib_data_offset_1[3]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_1_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_5), .Q(calib_data_offset_1[4]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_data_offset_1_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_4), .Q(calib_data_offset_1[5]), .R(\calib_data_offset_0[5]_i_1_n_0 )); LUT5 #( .INIT(32'h0000AAA2)) \calib_odt[0]_i_1 (.I0(\gen_rnk[0].mr1_r_reg[0]_196 ), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_odt[0]_i_2_n_0 ), .I3(\calib_odt[0]_i_3_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__23), .O(\calib_odt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hCFDCCFDFCCDCCCDF)) \calib_odt[0]_i_2 (.I0(first_wrcal_pat_r_i_2_n_0), .I1(stg1_wr_done), .I2(Q[1]), .I3(Q[0]), .I4(complex_ocal_odt_ext_i_4_n_0), .I5(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .O(\calib_odt[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF2000)) \calib_odt[0]_i_3 (.I0(wrlvl_odt), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(\calib_odt[0]_i_4_n_0 ), .I4(complex_odt_ext), .I5(complex_ocal_odt_ext), .O(\calib_odt[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair522" *) LUT5 #( .INIT(32'h00100000)) \calib_odt[0]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[0]), .I3(Q[3]), .I4(Q[1]), .O(\calib_odt[0]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \calib_odt_reg[0] (.C(CLK), .CE(1'b1), .D(\calib_odt[0]_i_1_n_0 ), .Q(calib_odt), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair556" *) LUT3 #( .INIT(8'h78)) \calib_seq[0]_i_1 (.I0(cnt_pwron_cke_done_r), .I1(\mcGo_r_reg[15] ), .I2(\phy_ctl_wd_i1_reg[24] [9]), .O(\calib_seq[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair556" *) LUT4 #( .INIT(16'h7F80)) \calib_seq[1]_i_1 (.I0(\phy_ctl_wd_i1_reg[24] [9]), .I1(cnt_pwron_cke_done_r), .I2(\mcGo_r_reg[15] ), .I3(\phy_ctl_wd_i1_reg[24] [10]), .O(\calib_seq[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \calib_seq_reg[0] (.C(CLK), .CE(1'b1), .D(\calib_seq[0]_i_1_n_0 ), .Q(\phy_ctl_wd_i1_reg[24] [9]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \calib_seq_reg[1] (.C(CLK), .CE(1'b1), .D(\calib_seq[1]_i_1_n_0 ), .Q(\phy_ctl_wd_i1_reg[24] [10]), .R(rstdiv0_sync_r1_reg_rep__12)); LUT1 #( .INIT(2'h1)) calib_wrdata_en_i_1 (.I0(\calib_cmd[2]_i_2_n_0 ), .O(phy_wrdata_en)); FDRE #( .INIT(1'b0)) calib_wrdata_en_reg (.C(CLK), .CE(1'b1), .D(phy_wrdata_en), .Q(calib_wrdata_en), .R(1'b0)); LUT6 #( .INIT(64'h0000000000008000)) cnt_cmd_done_m7_r_i_1 (.I0(\cnt_cmd_r_reg_n_0_[6] ), .I1(\cnt_cmd_r_reg_n_0_[5] ), .I2(\cnt_cmd_r_reg_n_0_[4] ), .I3(\cnt_cmd_r_reg_n_0_[3] ), .I4(cnt_cmd_done_m7_r_i_2_n_0), .I5(\cnt_cmd_r_reg_n_0_[2] ), .O(cnt_cmd_done_m7_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair601" *) LUT2 #( .INIT(4'hE)) cnt_cmd_done_m7_r_i_2 (.I0(\cnt_cmd_r_reg_n_0_[0] ), .I1(\cnt_cmd_r_reg_n_0_[1] ), .O(cnt_cmd_done_m7_r_i_2_n_0)); FDRE #( .INIT(1'b0)) cnt_cmd_done_m7_r_reg (.C(CLK), .CE(1'b1), .D(cnt_cmd_done_m7_r_i_1_n_0), .Q(cnt_cmd_done_m7_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair577" *) LUT3 #( .INIT(8'h80)) cnt_cmd_done_r_i_1 (.I0(\cnt_cmd_r[6]_i_5_n_0 ), .I1(\cnt_cmd_r_reg_n_0_[5] ), .I2(\cnt_cmd_r_reg_n_0_[6] ), .O(cnt_cmd_done_r_i_1_n_0)); FDRE #( .INIT(1'b0)) cnt_cmd_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_cmd_done_r_i_1_n_0), .Q(cnt_cmd_done_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cnt_cmd_r[0]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[0] ), .O(\cnt_cmd_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair601" *) LUT2 #( .INIT(4'h6)) \cnt_cmd_r[1]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[1] ), .I1(\cnt_cmd_r_reg_n_0_[0] ), .O(\cnt_cmd_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair552" *) LUT3 #( .INIT(8'h6A)) \cnt_cmd_r[2]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[2] ), .I1(\cnt_cmd_r_reg_n_0_[1] ), .I2(\cnt_cmd_r_reg_n_0_[0] ), .O(\cnt_cmd_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair552" *) LUT4 #( .INIT(16'h6AAA)) \cnt_cmd_r[3]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[3] ), .I1(\cnt_cmd_r_reg_n_0_[2] ), .I2(\cnt_cmd_r_reg_n_0_[0] ), .I3(\cnt_cmd_r_reg_n_0_[1] ), .O(\cnt_cmd_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair484" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_cmd_r[4]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[4] ), .I1(\cnt_cmd_r_reg_n_0_[3] ), .I2(\cnt_cmd_r_reg_n_0_[1] ), .I3(\cnt_cmd_r_reg_n_0_[0] ), .I4(\cnt_cmd_r_reg_n_0_[2] ), .O(\cnt_cmd_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_cmd_r[5]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[5] ), .I1(\cnt_cmd_r_reg_n_0_[4] ), .I2(\cnt_cmd_r_reg_n_0_[3] ), .I3(\cnt_cmd_r_reg_n_0_[1] ), .I4(\cnt_cmd_r_reg_n_0_[0] ), .I5(\cnt_cmd_r_reg_n_0_[2] ), .O(\cnt_cmd_r[5]_i_1_n_0 )); LUT3 #( .INIT(8'hFE)) \cnt_cmd_r[6]_i_1 (.I0(\cnt_cmd_r[6]_i_3_n_0 ), .I1(\cnt_cmd_r[6]_i_4_n_0 ), .I2(Q[5]), .O(\cnt_cmd_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair577" *) LUT3 #( .INIT(8'h6A)) \cnt_cmd_r[6]_i_2 (.I0(\cnt_cmd_r_reg_n_0_[6] ), .I1(\cnt_cmd_r_reg_n_0_[5] ), .I2(\cnt_cmd_r[6]_i_5_n_0 ), .O(\cnt_cmd_r[6]_i_2_n_0 )); LUT6 #( .INIT(64'h5544151145411111)) \cnt_cmd_r[6]_i_3 (.I0(Q[0]), .I1(Q[4]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[2]), .I4(Q[3]), .I5(Q[1]), .O(\cnt_cmd_r[6]_i_3_n_0 )); LUT6 #( .INIT(64'hA8AAA8A2A820A8AA)) \cnt_cmd_r[6]_i_4 (.I0(Q[0]), .I1(Q[3]), .I2(Q[4]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[1]), .I5(Q[2]), .O(\cnt_cmd_r[6]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair484" *) LUT5 #( .INIT(32'h80000000)) \cnt_cmd_r[6]_i_5 (.I0(\cnt_cmd_r_reg_n_0_[2] ), .I1(\cnt_cmd_r_reg_n_0_[0] ), .I2(\cnt_cmd_r_reg_n_0_[1] ), .I3(\cnt_cmd_r_reg_n_0_[3] ), .I4(\cnt_cmd_r_reg_n_0_[4] ), .O(\cnt_cmd_r[6]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[0]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[0] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[1]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[1] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[2] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[2]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[2] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[3] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[3]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[3] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[4] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[4]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[4] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[5] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[5]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[5] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_cmd_r_reg[6] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[6]_i_2_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[6] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) cnt_dllk_zqinit_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_dllk_zqinit_done_r_reg_0), .Q(cnt_dllk_zqinit_done_r), .R(cnt_dllk_zqinit_r)); LUT1 #( .INIT(2'h1)) \cnt_dllk_zqinit_r[0]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[0]), .O(p_0_in__3[0])); (* SOFT_HLUTNM = "soft_lutpair595" *) LUT2 #( .INIT(4'h6)) \cnt_dllk_zqinit_r[1]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[1]), .I1(cnt_dllk_zqinit_r_reg__0[0]), .O(p_0_in__3[1])); (* SOFT_HLUTNM = "soft_lutpair595" *) LUT3 #( .INIT(8'h6A)) \cnt_dllk_zqinit_r[2]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[2]), .I1(cnt_dllk_zqinit_r_reg__0[0]), .I2(cnt_dllk_zqinit_r_reg__0[1]), .O(p_0_in__3[2])); (* SOFT_HLUTNM = "soft_lutpair517" *) LUT4 #( .INIT(16'h6AAA)) \cnt_dllk_zqinit_r[3]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[3]), .I1(cnt_dllk_zqinit_r_reg__0[1]), .I2(cnt_dllk_zqinit_r_reg__0[0]), .I3(cnt_dllk_zqinit_r_reg__0[2]), .O(p_0_in__3[3])); (* SOFT_HLUTNM = "soft_lutpair517" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_dllk_zqinit_r[4]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[4]), .I1(cnt_dllk_zqinit_r_reg__0[2]), .I2(cnt_dllk_zqinit_r_reg__0[0]), .I3(cnt_dllk_zqinit_r_reg__0[1]), .I4(cnt_dllk_zqinit_r_reg__0[3]), .O(p_0_in__3[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_dllk_zqinit_r[5]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[5]), .I1(cnt_dllk_zqinit_r_reg__0[3]), .I2(cnt_dllk_zqinit_r_reg__0[1]), .I3(cnt_dllk_zqinit_r_reg__0[0]), .I4(cnt_dllk_zqinit_r_reg__0[2]), .I5(cnt_dllk_zqinit_r_reg__0[4]), .O(p_0_in__3[5])); (* SOFT_HLUTNM = "soft_lutpair592" *) LUT2 #( .INIT(4'h6)) \cnt_dllk_zqinit_r[6]_i_1 (.I0(mem_init_done_r_reg_0[0]), .I1(mem_init_done_r_reg_1), .O(p_0_in__3[6])); LUT6 #( .INIT(64'h0000000000000010)) \cnt_dllk_zqinit_r[7]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(cnt_dllk_zqinit_r)); (* SOFT_HLUTNM = "soft_lutpair592" *) LUT3 #( .INIT(8'h6A)) \cnt_dllk_zqinit_r[7]_i_2 (.I0(mem_init_done_r_reg_0[1]), .I1(mem_init_done_r_reg_1), .I2(mem_init_done_r_reg_0[0]), .O(p_0_in__3[7])); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__3[0]), .Q(cnt_dllk_zqinit_r_reg__0[0]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__3[1]), .Q(cnt_dllk_zqinit_r_reg__0[1]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__3[2]), .Q(cnt_dllk_zqinit_r_reg__0[2]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__3[3]), .Q(cnt_dllk_zqinit_r_reg__0[3]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__3[4]), .Q(cnt_dllk_zqinit_r_reg__0[4]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[5] (.C(CLK), .CE(1'b1), .D(p_0_in__3[5]), .Q(cnt_dllk_zqinit_r_reg__0[5]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[6] (.C(CLK), .CE(1'b1), .D(p_0_in__3[6]), .Q(mem_init_done_r_reg_0[0]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) \cnt_dllk_zqinit_r_reg[7] (.C(CLK), .CE(1'b1), .D(p_0_in__3[7]), .Q(mem_init_done_r_reg_0[1]), .R(cnt_dllk_zqinit_r)); FDRE #( .INIT(1'b0)) cnt_init_af_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_init_af_done_r_reg_0), .Q(cnt_init_af_done_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair497" *) LUT4 #( .INIT(16'h009A)) \cnt_init_af_r[0]_i_1 (.I0(cnt_init_af_r[0]), .I1(mem_init_done_r), .I2(\cnt_init_mr_r_reg[1]_0 ), .I3(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_af_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair497" *) LUT5 #( .INIT(32'h00009AAA)) \cnt_init_af_r[1]_i_1 (.I0(cnt_init_af_r[1]), .I1(mem_init_done_r), .I2(\cnt_init_mr_r_reg[1]_0 ), .I3(cnt_init_af_r[0]), .I4(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_af_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_init_af_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cnt_init_af_r[0]_i_1_n_0 ), .Q(cnt_init_af_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cnt_init_af_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cnt_init_af_r[1]_i_1_n_0 ), .Q(cnt_init_af_r[1]), .R(1'b0)); LUT6 #( .INIT(64'h0000000004000000)) cnt_init_mr_done_r_i_2 (.I0(Q[5]), .I1(Q[3]), .I2(Q[4]), .I3(\init_state_r_reg[1]_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I5(mem_init_done_r), .O(cnt_init_mr_r1)); FDRE #( .INIT(1'b0)) cnt_init_mr_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_init_mr_done_r_reg_0), .Q(cnt_init_mr_done_r), .R(1'b0)); LUT5 #( .INIT(32'h00006606)) \cnt_init_mr_r[0]_i_1 (.I0(cnt_init_mr_r[0]), .I1(temp_lmr_done), .I2(\cnt_init_mr_r_reg[1]_0 ), .I3(mem_init_done_r), .I4(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_mr_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000006A6A006A)) \cnt_init_mr_r[1]_i_1 (.I0(cnt_init_mr_r[1]), .I1(temp_lmr_done), .I2(cnt_init_mr_r[0]), .I3(\cnt_init_mr_r_reg[1]_0 ), .I4(mem_init_done_r), .I5(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_mr_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \cnt_init_mr_r[1]_i_2 (.I0(Q[1]), .I1(Q[4]), .I2(Q[5]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[3]), .I5(Q[0]), .O(temp_lmr_done)); LUT6 #( .INIT(64'h0000000000080000)) \cnt_init_mr_r[1]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(Q[4]), .I4(Q[3]), .I5(Q[5]), .O(\cnt_init_mr_r_reg[1]_0 )); FDRE #( .INIT(1'b0)) \cnt_init_mr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cnt_init_mr_r[0]_i_1_n_0 ), .Q(cnt_init_mr_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cnt_init_mr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cnt_init_mr_r[1]_i_1_n_0 ), .Q(cnt_init_mr_r[1]), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cnt_pwron_ce_r[0]_i_1 (.I0(cnt_pwron_ce_r_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair599" *) LUT2 #( .INIT(4'h6)) \cnt_pwron_ce_r[1]_i_1 (.I0(cnt_pwron_ce_r_reg__0[1]), .I1(cnt_pwron_ce_r_reg__0[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair599" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_ce_r[2]_i_1 (.I0(cnt_pwron_ce_r_reg__0[2]), .I1(cnt_pwron_ce_r_reg__0[0]), .I2(cnt_pwron_ce_r_reg__0[1]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair492" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_ce_r[3]_i_1 (.I0(cnt_pwron_ce_r_reg__0[3]), .I1(cnt_pwron_ce_r_reg__0[1]), .I2(cnt_pwron_ce_r_reg__0[0]), .I3(cnt_pwron_ce_r_reg__0[2]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair492" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_pwron_ce_r[4]_i_1 (.I0(cnt_pwron_ce_r_reg__0[4]), .I1(cnt_pwron_ce_r_reg__0[2]), .I2(cnt_pwron_ce_r_reg__0[0]), .I3(cnt_pwron_ce_r_reg__0[1]), .I4(cnt_pwron_ce_r_reg__0[3]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_pwron_ce_r[5]_i_1 (.I0(cnt_pwron_ce_r_reg__0[5]), .I1(cnt_pwron_ce_r_reg__0[3]), .I2(cnt_pwron_ce_r_reg__0[1]), .I3(cnt_pwron_ce_r_reg__0[0]), .I4(cnt_pwron_ce_r_reg__0[2]), .I5(cnt_pwron_ce_r_reg__0[4]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair598" *) LUT2 #( .INIT(4'h6)) \cnt_pwron_ce_r[6]_i_1 (.I0(cnt_pwron_ce_r_reg__0[6]), .I1(pwron_ce_r_i_3_n_0), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair598" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_ce_r[7]_i_1 (.I0(cnt_pwron_ce_r_reg__0[7]), .I1(pwron_ce_r_i_3_n_0), .I2(cnt_pwron_ce_r_reg__0[6]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair508" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_ce_r[8]_i_1 (.I0(cnt_pwron_ce_r_reg__0[8]), .I1(cnt_pwron_ce_r_reg__0[6]), .I2(pwron_ce_r_i_3_n_0), .I3(cnt_pwron_ce_r_reg__0[7]), .O(p_0_in__0[8])); (* SOFT_HLUTNM = "soft_lutpair508" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_pwron_ce_r[9]_i_1 (.I0(cnt_pwron_ce_r_reg__0[9]), .I1(cnt_pwron_ce_r_reg__0[7]), .I2(pwron_ce_r_i_3_n_0), .I3(cnt_pwron_ce_r_reg__0[6]), .I4(cnt_pwron_ce_r_reg__0[8]), .O(p_0_in__0[9])); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0[0]), .Q(cnt_pwron_ce_r_reg__0[0]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0[1]), .Q(cnt_pwron_ce_r_reg__0[1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0[2]), .Q(cnt_pwron_ce_r_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0[3]), .Q(cnt_pwron_ce_r_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__0[4]), .Q(cnt_pwron_ce_r_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[5] (.C(CLK), .CE(1'b1), .D(p_0_in__0[5]), .Q(cnt_pwron_ce_r_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[6] (.C(CLK), .CE(1'b1), .D(p_0_in__0[6]), .Q(cnt_pwron_ce_r_reg__0[6]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[7] (.C(CLK), .CE(1'b1), .D(p_0_in__0[7]), .Q(cnt_pwron_ce_r_reg__0[7]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[8] (.C(CLK), .CE(1'b1), .D(p_0_in__0[8]), .Q(cnt_pwron_ce_r_reg__0[8]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_ce_r_reg[9] (.C(CLK), .CE(1'b1), .D(p_0_in__0[9]), .Q(cnt_pwron_ce_r_reg__0[9]), .R(rstdiv0_sync_r1_reg_rep__19)); LUT6 #( .INIT(64'hFEFFFFFFFFFFFFFF)) cnt_pwron_cke_done_r_i_2 (.I0(cnt_pwron_r_reg__0[8]), .I1(cnt_pwron_r_reg__0[6]), .I2(\cnt_pwron_r_reg[7]_0 [2]), .I3(cnt_pwron_r_reg__0[4]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[2]), .O(cnt_pwron_cke_done_r_reg_0)); FDRE #( .INIT(1'b0)) cnt_pwron_cke_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_pwron_cke_done_r_reg_1), .Q(cnt_pwron_cke_done_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cnt_pwron_r[0]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [0]), .O(p_0_in__0__0[0])); (* SOFT_HLUTNM = "soft_lutpair597" *) LUT2 #( .INIT(4'h6)) \cnt_pwron_r[1]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [1]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair597" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_r[2]_i_1 (.I0(cnt_pwron_r_reg__0[2]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .O(p_0_in__0__0[2])); (* SOFT_HLUTNM = "soft_lutpair512" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_r[3]_i_1 (.I0(cnt_pwron_r_reg__0[3]), .I1(\cnt_pwron_r_reg[7]_0 [1]), .I2(\cnt_pwron_r_reg[7]_0 [0]), .I3(cnt_pwron_r_reg__0[2]), .O(p_0_in__0__0[3])); (* SOFT_HLUTNM = "soft_lutpair512" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_pwron_r[4]_i_1 (.I0(cnt_pwron_r_reg__0[4]), .I1(cnt_pwron_r_reg__0[3]), .I2(cnt_pwron_r_reg__0[2]), .I3(\cnt_pwron_r_reg[7]_0 [1]), .I4(\cnt_pwron_r_reg[7]_0 [0]), .O(p_0_in__0__0[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_pwron_r[5]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [2]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .I3(cnt_pwron_r_reg__0[2]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[4]), .O(p_0_in__0__0[5])); LUT6 #( .INIT(64'hA6AAAAAAAAAAAAAA)) \cnt_pwron_r[6]_i_1 (.I0(cnt_pwron_r_reg__0[6]), .I1(cnt_pwron_r_reg__0[4]), .I2(\cnt_pwron_r[6]_i_2_n_0 ), .I3(\cnt_pwron_r_reg[7]_0 [1]), .I4(\cnt_pwron_r_reg[7]_0 [0]), .I5(\cnt_pwron_r_reg[7]_0 [2]), .O(p_0_in__0__0[6])); LUT2 #( .INIT(4'h7)) \cnt_pwron_r[6]_i_2 (.I0(cnt_pwron_r_reg__0[3]), .I1(cnt_pwron_r_reg__0[2]), .O(\cnt_pwron_r[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair532" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_r[7]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [3]), .I1(\cnt_pwron_r[8]_i_2_n_0 ), .I2(cnt_pwron_r_reg__0[6]), .O(p_0_in__0__0[7])); (* SOFT_HLUTNM = "soft_lutpair532" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_r[8]_i_1 (.I0(cnt_pwron_r_reg__0[8]), .I1(cnt_pwron_r_reg__0[6]), .I2(\cnt_pwron_r[8]_i_2_n_0 ), .I3(\cnt_pwron_r_reg[7]_0 [3]), .O(p_0_in__0__0[8])); LUT6 #( .INIT(64'h8000000000000000)) \cnt_pwron_r[8]_i_2 (.I0(\cnt_pwron_r_reg[7]_0 [2]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .I3(cnt_pwron_r_reg__0[2]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[4]), .O(\cnt_pwron_r[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[0] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[0]), .Q(\cnt_pwron_r_reg[7]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[1] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[1]), .Q(\cnt_pwron_r_reg[7]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[2] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[2]), .Q(cnt_pwron_r_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[3] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[3]), .Q(cnt_pwron_r_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[4] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[4]), .Q(cnt_pwron_r_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[5] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[5]), .Q(\cnt_pwron_r_reg[7]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[6] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[6]), .Q(cnt_pwron_r_reg__0[6]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[7] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[7]), .Q(\cnt_pwron_r_reg[7]_0 [3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \cnt_pwron_r_reg[8] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[8]), .Q(cnt_pwron_r_reg__0[8]), .R(rstdiv0_sync_r1_reg_rep__19)); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) cnt_pwron_reset_done_r_i_2 (.I0(cnt_pwron_r_reg__0[8]), .I1(cnt_pwron_r_reg__0[6]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .I3(cnt_pwron_r_reg__0[4]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[2]), .O(cnt_pwron_reset_done_r_reg_0)); FDRE #( .INIT(1'b0)) cnt_pwron_reset_done_r_reg (.C(CLK), .CE(1'b1), .D(\cnt_pwron_r_reg[7]_1 ), .Q(cnt_pwron_reset_done_r), .R(1'b0)); LUT3 #( .INIT(8'hBA)) \cnt_shift_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(rdlvl_stg1_start_r_reg), .I2(mpr_rdlvl_done_r_reg), .O(\cnt_shift_r_reg[0] )); LUT5 #( .INIT(32'h88C88888)) \cnt_shift_r[3]_i_2 (.I0(rdlvl_stg1_start_r_reg), .I1(phy_rddata_en_1), .I2(mpr_rdlvl_start_r_reg), .I3(mpr_rdlvl_done_r_reg), .I4(\cnt_shift_r_reg[0]_0 ), .O(E)); LUT5 #( .INIT(32'hFFFFFFEF)) cnt_txpr_done_r_i_2 (.I0(cnt_txpr_r_reg__0[7]), .I1(cnt_txpr_r_reg__0[4]), .I2(cnt_txpr_r_reg__0[6]), .I3(cnt_txpr_r_reg__0[3]), .I4(cnt_txpr_r_reg__0[5]), .O(cnt_txpr_done_r_reg_0)); FDRE #( .INIT(1'b0)) cnt_txpr_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_txpr_done_r_reg_1), .Q(cnt_txpr_done_r), .R(clear)); (* SOFT_HLUTNM = "soft_lutpair606" *) LUT1 #( .INIT(2'h1)) \cnt_txpr_r[0]_i_1 (.I0(\cnt_txpr_r_reg[2]_0 [0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair606" *) LUT2 #( .INIT(4'h6)) \cnt_txpr_r[1]_i_1 (.I0(\cnt_txpr_r_reg[2]_0 [1]), .I1(\cnt_txpr_r_reg[2]_0 [0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair596" *) LUT3 #( .INIT(8'h6A)) \cnt_txpr_r[2]_i_1 (.I0(\cnt_txpr_r_reg[2]_0 [2]), .I1(\cnt_txpr_r_reg[2]_0 [0]), .I2(\cnt_txpr_r_reg[2]_0 [1]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair487" *) LUT4 #( .INIT(16'h6AAA)) \cnt_txpr_r[3]_i_1 (.I0(cnt_txpr_r_reg__0[3]), .I1(\cnt_txpr_r_reg[2]_0 [1]), .I2(\cnt_txpr_r_reg[2]_0 [0]), .I3(\cnt_txpr_r_reg[2]_0 [2]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair487" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_txpr_r[4]_i_1 (.I0(cnt_txpr_r_reg__0[4]), .I1(\cnt_txpr_r_reg[2]_0 [2]), .I2(\cnt_txpr_r_reg[2]_0 [0]), .I3(\cnt_txpr_r_reg[2]_0 [1]), .I4(cnt_txpr_r_reg__0[3]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_txpr_r[5]_i_1 (.I0(cnt_txpr_r_reg__0[5]), .I1(cnt_txpr_r_reg__0[3]), .I2(\cnt_txpr_r_reg[2]_0 [1]), .I3(\cnt_txpr_r_reg[2]_0 [0]), .I4(\cnt_txpr_r_reg[2]_0 [2]), .I5(cnt_txpr_r_reg__0[4]), .O(p_0_in__1[5])); LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_txpr_r[6]_i_1 (.I0(cnt_txpr_r_reg__0[6]), .I1(cnt_txpr_r_reg__0[4]), .I2(\cnt_txpr_r[7]_i_3_n_0 ), .I3(cnt_txpr_r_reg__0[3]), .I4(cnt_txpr_r_reg__0[5]), .O(p_0_in__1[6])); LUT1 #( .INIT(2'h1)) \cnt_txpr_r[7]_i_1 (.I0(cnt_pwron_cke_done_r), .O(clear)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_txpr_r[7]_i_2 (.I0(cnt_txpr_r_reg__0[7]), .I1(cnt_txpr_r_reg__0[6]), .I2(cnt_txpr_r_reg__0[5]), .I3(cnt_txpr_r_reg__0[3]), .I4(\cnt_txpr_r[7]_i_3_n_0 ), .I5(cnt_txpr_r_reg__0[4]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair596" *) LUT3 #( .INIT(8'h80)) \cnt_txpr_r[7]_i_3 (.I0(\cnt_txpr_r_reg[2]_0 [2]), .I1(\cnt_txpr_r_reg[2]_0 [0]), .I2(\cnt_txpr_r_reg[2]_0 [1]), .O(\cnt_txpr_r[7]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__1[0]), .Q(\cnt_txpr_r_reg[2]_0 [0]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__1[1]), .Q(\cnt_txpr_r_reg[2]_0 [1]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__1[2]), .Q(\cnt_txpr_r_reg[2]_0 [2]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__1[3]), .Q(cnt_txpr_r_reg__0[3]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__1[4]), .Q(cnt_txpr_r_reg__0[4]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[5] (.C(CLK), .CE(1'b1), .D(p_0_in__1[5]), .Q(cnt_txpr_r_reg__0[5]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[6] (.C(CLK), .CE(1'b1), .D(p_0_in__1[6]), .Q(cnt_txpr_r_reg__0[6]), .R(clear)); FDRE #( .INIT(1'b0)) \cnt_txpr_r_reg[7] (.C(CLK), .CE(1'b1), .D(p_0_in__1[7]), .Q(cnt_txpr_r_reg__0[7]), .R(clear)); LUT6 #( .INIT(64'h0000404000034040)) complex_act_start_i_1 (.I0(read_calib_reg_0), .I1(Q[4]), .I2(Q[3]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[5]), .I5(prbs_rdlvl_start_i_2_n_0), .O(complex_act_start0)); FDRE #( .INIT(1'b0)) complex_act_start_reg (.C(CLK), .CE(1'b1), .D(complex_act_start0), .Q(complex_act_start), .R(1'b0)); LUT5 #( .INIT(32'hFFFEFD00)) \complex_address[9]_i_1 (.I0(init_state_r1[2]), .I1(init_state_r1[6]), .I2(\complex_address[9]_i_2_n_0 ), .I3(\complex_address[9]_i_3_n_0 ), .I4(\complex_address[9]_i_4_n_0 ), .O(complex_address0)); (* SOFT_HLUTNM = "soft_lutpair510" *) LUT5 #( .INIT(32'hFFFF7FFF)) \complex_address[9]_i_2 (.I0(init_state_r1[3]), .I1(init_state_r1[4]), .I2(init_state_r1[5]), .I3(init_state_r1[0]), .I4(init_state_r1[1]), .O(\complex_address[9]_i_2_n_0 )); LUT6 #( .INIT(64'h2000000000000000)) \complex_address[9]_i_3 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(Q[2]), .I4(\init_state_r_reg_n_0_[3] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\complex_address[9]_i_3_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \complex_address[9]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\complex_address[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \complex_address_reg[0] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .Q(\complex_address_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[1] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .Q(\complex_address_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[2] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .Q(\complex_address_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[3] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .Q(\complex_address_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[4] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .Q(\complex_address_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[5] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .Q(\complex_address_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[6] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .Q(\complex_address_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[7] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .Q(\complex_address_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[8] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .Q(\complex_address_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \complex_address_reg[9] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .Q(\complex_address_reg_n_0_[9] ), .R(rstdiv0_sync_r1_reg_rep__11)); LUT5 #( .INIT(32'h0000000E)) complex_byte_rd_done_i_1 (.I0(complex_byte_rd_done), .I1(complex_byte_rd_done_i_2_n_0), .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I3(prbs_rdlvl_done_pulse), .I4(rstdiv0_sync_r1_reg_rep__24), .O(complex_byte_rd_done_i_1_n_0)); LUT6 #( .INIT(64'h0000800000000000)) complex_byte_rd_done_i_2 (.I0(complex_row1_rd_cnt[0]), .I1(complex_row1_rd_cnt[1]), .I2(complex_row1_rd_cnt[2]), .I3(complex_row1_rd_done), .I4(complex_row1_rd_done_r1), .I5(prbs_rdlvl_done_reg_rep), .O(complex_byte_rd_done_i_2_n_0)); FDRE #( .INIT(1'b0)) complex_byte_rd_done_reg (.C(CLK), .CE(1'b1), .D(complex_byte_rd_done_i_1_n_0), .Q(complex_byte_rd_done), .R(1'b0)); LUT5 #( .INIT(32'h000000AE)) complex_mask_lim_done_i_1 (.I0(complex_mask_lim_done), .I1(complex_oclkdelay_calib_start_int), .I2(prbs_rdlvl_done_reg), .I3(prbs_rdlvl_done_r3), .I4(rstdiv0_sync_r1_reg_rep__24), .O(complex_mask_lim_done_i_1_n_0)); FDRE #( .INIT(1'b0)) complex_mask_lim_done_reg (.C(CLK), .CE(1'b1), .D(complex_mask_lim_done_i_1_n_0), .Q(complex_mask_lim_done), .R(1'b0)); LUT5 #( .INIT(32'hFFFF26EE)) \complex_num_reads[0]_i_1 (.I0(\complex_num_reads_reg_n_0_[0] ), .I1(\complex_num_reads[3]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_5_n_0 ), .I3(\complex_num_reads[2]_i_4_n_0 ), .I4(\complex_num_reads[3]_i_4_n_0 ), .O(\complex_num_reads[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000222FE22)) \complex_num_reads[1]_i_1 (.I0(\complex_num_reads_reg_n_0_[1] ), .I1(\complex_num_reads[2]_i_2_n_0 ), .I2(\complex_num_writes[2]_i_4_n_0 ), .I3(\complex_num_reads[2]_i_4_n_0 ), .I4(\complex_num_reads[1]_i_2_n_0 ), .I5(\complex_num_reads[2]_i_5_n_0 ), .O(\complex_num_reads[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair550" *) LUT4 #( .INIT(16'hA88A)) \complex_num_reads[1]_i_2 (.I0(\complex_num_reads[3]_i_8_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_reads_reg_n_0_[1] ), .I3(\complex_num_reads_reg_n_0_[0] ), .O(\complex_num_reads[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000002E2222)) \complex_num_reads[2]_i_1 (.I0(\complex_num_reads_reg_n_0_[2] ), .I1(\complex_num_reads[2]_i_2_n_0 ), .I2(\complex_num_reads[2]_i_3_n_0 ), .I3(\complex_num_writes[2]_i_4_n_0 ), .I4(\complex_num_reads[2]_i_4_n_0 ), .I5(\complex_num_reads[2]_i_5_n_0 ), .O(\complex_num_reads[2]_i_1_n_0 )); LUT3 #( .INIT(8'hEA)) \complex_num_reads[2]_i_2 (.I0(\complex_num_reads[3]_i_2_n_0 ), .I1(\complex_num_reads[2]_i_4_n_0 ), .I2(\complex_num_reads[2]_i_6_n_0 ), .O(\complex_num_reads[2]_i_2_n_0 )); LUT4 #( .INIT(16'h802A)) \complex_num_reads[2]_i_3 (.I0(\complex_num_writes[2]_i_6_n_0 ), .I1(\complex_num_reads_reg_n_0_[1] ), .I2(\complex_num_reads_reg_n_0_[0] ), .I3(\complex_num_reads_reg_n_0_[2] ), .O(\complex_num_reads[2]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000008000)) \complex_num_reads[2]_i_4 (.I0(\complex_address[9]_i_4_n_0 ), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[3]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .I5(complex_row0_rd_done), .O(\complex_num_reads[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFFEAAAAAAAAAAAAA)) \complex_num_reads[2]_i_5 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\complex_num_reads_reg_n_0_[2] ), .I2(\complex_num_reads_reg_n_0_[1] ), .I3(\complex_num_reads_reg_n_0_[3] ), .I4(\complex_num_writes[4]_i_7_n_0 ), .I5(\complex_num_reads[2]_i_4_n_0 ), .O(\complex_num_reads[2]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \complex_num_reads[2]_i_6 (.I0(\complex_num_writes[2]_i_7_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\complex_num_reads[2]_i_6_n_0 )); LUT4 #( .INIT(16'h00E2)) \complex_num_reads[3]_i_1 (.I0(\complex_num_reads_reg_n_0_[3] ), .I1(\complex_num_reads[3]_i_2_n_0 ), .I2(\complex_num_reads[3]_i_3_n_0 ), .I3(\complex_num_reads[3]_i_4_n_0 ), .O(\complex_num_reads[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFEFEFE0EFEFEFEFE)) \complex_num_reads[3]_i_2 (.I0(\complex_num_writes[3]_i_4_n_0 ), .I1(stg1_wr_done), .I2(\complex_num_reads[2]_i_4_n_0 ), .I3(\complex_num_writes[4]_i_7_n_0 ), .I4(\complex_num_reads[3]_i_5_n_0 ), .I5(\complex_num_reads[3]_i_6_n_0 ), .O(\complex_num_reads[3]_i_2_n_0 )); LUT6 #( .INIT(64'h8AA8A8A8A8A8A8A8)) \complex_num_reads[3]_i_3 (.I0(\complex_num_reads[2]_i_4_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_reads_reg_n_0_[3] ), .I3(\complex_num_reads_reg_n_0_[1] ), .I4(\complex_num_reads_reg_n_0_[0] ), .I5(\complex_num_reads_reg_n_0_[2] ), .O(\complex_num_reads[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFEF0F0F0FEFFF0F0)) \complex_num_reads[3]_i_4 (.I0(\complex_num_reads_reg_n_0_[3] ), .I1(\complex_num_reads[3]_i_7_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__23), .I3(\complex_num_writes[4]_i_7_n_0 ), .I4(\complex_num_reads[2]_i_4_n_0 ), .I5(\complex_num_reads[3]_i_8_n_0 ), .O(\complex_num_reads[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair493" *) LUT5 #( .INIT(32'hAAAABBBF)) \complex_num_reads[3]_i_5 (.I0(\complex_num_writes[4]_i_5_n_0 ), .I1(\complex_num_reads_reg_n_0_[2] ), .I2(\complex_num_reads_reg_n_0_[0] ), .I3(\complex_num_reads_reg_n_0_[1] ), .I4(\complex_num_reads_reg_n_0_[3] ), .O(\complex_num_reads[3]_i_5_n_0 )); LUT5 #( .INIT(32'hFEAAEAAA)) \complex_num_reads[3]_i_6 (.I0(\complex_num_writes[4]_i_14_n_0 ), .I1(\complex_num_reads_reg_n_0_[1] ), .I2(\complex_num_reads_reg_n_0_[2] ), .I3(\complex_num_reads_reg_n_0_[3] ), .I4(\complex_num_writes[4]_i_15_n_0 ), .O(\complex_num_reads[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair493" *) LUT2 #( .INIT(4'h8)) \complex_num_reads[3]_i_7 (.I0(\complex_num_reads_reg_n_0_[2] ), .I1(\complex_num_reads_reg_n_0_[1] ), .O(\complex_num_reads[3]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFDEFFFFFFFFF)) \complex_num_reads[3]_i_8 (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I5(\complex_num_writes[2]_i_7_n_0 ), .O(\complex_num_reads[3]_i_8_n_0 )); LUT3 #( .INIT(8'h74)) \complex_num_reads_dec[0]_i_2 (.I0(complex_num_reads_dec_reg__0[0]), .I1(\complex_num_reads_dec[3]_i_3_n_0 ), .I2(\complex_num_reads_reg_n_0_[0] ), .O(p_0_in__8[0])); LUT4 #( .INIT(16'h9F90)) \complex_num_reads_dec[1]_i_1 (.I0(complex_num_reads_dec_reg__0[1]), .I1(complex_num_reads_dec_reg__0[0]), .I2(\complex_num_reads_dec[3]_i_3_n_0 ), .I3(\complex_num_reads_reg_n_0_[1] ), .O(p_0_in__8[1])); LUT5 #( .INIT(32'hA9FFA900)) \complex_num_reads_dec[2]_i_1 (.I0(complex_num_reads_dec_reg__0[2]), .I1(complex_num_reads_dec_reg__0[0]), .I2(complex_num_reads_dec_reg__0[1]), .I3(\complex_num_reads_dec[3]_i_3_n_0 ), .I4(\complex_num_reads_reg_n_0_[2] ), .O(p_0_in__8[2])); LUT6 #( .INIT(64'hDDDDDDDDDDDDDDD5)) \complex_num_reads_dec[3]_i_1 (.I0(\complex_num_reads_dec[3]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I2(complex_num_reads_dec_reg__0[0]), .I3(complex_num_reads_dec_reg__0[1]), .I4(complex_num_reads_dec_reg__0[2]), .I5(complex_num_reads_dec_reg__0[3]), .O(\complex_num_reads_dec[3]_i_1_n_0 )); LUT6 #( .INIT(64'hAAA9FFFFAAA90000)) \complex_num_reads_dec[3]_i_2 (.I0(complex_num_reads_dec_reg__0[3]), .I1(complex_num_reads_dec_reg__0[2]), .I2(complex_num_reads_dec_reg__0[1]), .I3(complex_num_reads_dec_reg__0[0]), .I4(\complex_num_reads_dec[3]_i_3_n_0 ), .I5(\complex_num_reads_reg_n_0_[3] ), .O(p_0_in__8[3])); LUT6 #( .INIT(64'h5545555555555555)) \complex_num_reads_dec[3]_i_3 (.I0(\complex_num_reads_dec[3]_i_4_n_0 ), .I1(complex_row0_rd_done), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(complex_oclkdelay_calib_start_int_i_2_n_0), .I4(\init_state_r_reg[1]_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\complex_num_reads_dec[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00400000)) \complex_num_reads_dec[3]_i_4 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .I5(stg1_wr_done), .O(\complex_num_reads_dec[3]_i_4_n_0 )); FDSE #( .INIT(1'b1)) \complex_num_reads_dec_reg[0] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_1_n_0 ), .D(p_0_in__8[0]), .Q(complex_num_reads_dec_reg__0[0]), .S(rstdiv0_sync_r1_reg_rep__18)); FDRE #( .INIT(1'b0)) \complex_num_reads_dec_reg[1] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_1_n_0 ), .D(p_0_in__8[1]), .Q(complex_num_reads_dec_reg__0[1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \complex_num_reads_dec_reg[2] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_1_n_0 ), .D(p_0_in__8[2]), .Q(complex_num_reads_dec_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \complex_num_reads_dec_reg[3] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_1_n_0 ), .D(p_0_in__8[3]), .Q(complex_num_reads_dec_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \complex_num_reads_reg[0] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[0]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_reads_reg[1] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[1]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_reads_reg[2] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[2]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_reads_reg[3] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[3]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[3] ), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF22622E6E)) \complex_num_writes[0]_i_1 (.I0(\complex_num_writes_reg_n_0_[0] ), .I1(\complex_num_writes[3]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .I3(\complex_num_writes[4]_i_5_n_0 ), .I4(\complex_num_writes[0]_i_2_n_0 ), .I5(\complex_num_writes[4]_i_6_n_0 ), .O(\complex_num_writes[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \complex_num_writes[0]_i_2 (.I0(complex_row0_wr_done), .I1(prbs_rdlvl_start_i_2_n_0), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[4]), .O(\complex_num_writes[0]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FEEE0222)) \complex_num_writes[1]_i_1 (.I0(\complex_num_writes_reg_n_0_[1] ), .I1(\complex_num_writes[2]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .I3(\complex_num_writes[2]_i_4_n_0 ), .I4(\complex_num_writes[1]_i_2_n_0 ), .I5(\complex_num_writes[2]_i_5_n_0 ), .O(\complex_num_writes[1]_i_1_n_0 )); LUT6 #( .INIT(64'hBAAABABABABABAAA)) \complex_num_writes[1]_i_2 (.I0(\complex_num_writes[0]_i_2_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .I3(\complex_num_writes[4]_i_11_n_0 ), .I4(\complex_num_writes_reg_n_0_[0] ), .I5(\complex_num_writes_reg_n_0_[1] ), .O(\complex_num_writes[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000E2E2E2)) \complex_num_writes[2]_i_1 (.I0(\complex_num_writes_reg_n_0_[2] ), .I1(\complex_num_writes[2]_i_2_n_0 ), .I2(\complex_num_writes[2]_i_3_n_0 ), .I3(\complex_num_writes[4]_i_4_n_0 ), .I4(\complex_num_writes[2]_i_4_n_0 ), .I5(\complex_num_writes[2]_i_5_n_0 ), .O(\complex_num_writes[2]_i_1_n_0 )); LUT3 #( .INIT(8'hBA)) \complex_num_writes[2]_i_2 (.I0(\complex_num_writes[4]_i_2_n_0 ), .I1(\complex_num_writes[2]_i_6_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFF7FD5FFFF0000)) \complex_num_writes[2]_i_3 (.I0(\complex_num_writes[2]_i_6_n_0 ), .I1(\complex_num_writes_reg_n_0_[1] ), .I2(\complex_num_writes_reg_n_0_[0] ), .I3(\complex_num_writes_reg_n_0_[2] ), .I4(\complex_num_writes[0]_i_2_n_0 ), .I5(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[2]_i_3_n_0 )); LUT6 #( .INIT(64'h0000002000000000)) \complex_num_writes[2]_i_4 (.I0(\complex_num_writes[2]_i_7_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ), .O(\complex_num_writes[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFEEEAAAAAAAAAAAA)) \complex_num_writes[2]_i_5 (.I0(complex_row0_rd_done1), .I1(\complex_num_writes[2]_i_8_n_0 ), .I2(\complex_num_writes_reg_n_0_[2] ), .I3(\complex_num_writes_reg_n_0_[1] ), .I4(\complex_num_writes[4]_i_7_n_0 ), .I5(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair550" *) LUT2 #( .INIT(4'h1)) \complex_num_writes[2]_i_6 (.I0(\complex_num_reads[2]_i_6_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .O(\complex_num_writes[2]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair558" *) LUT4 #( .INIT(16'h1000)) \complex_num_writes[2]_i_7 (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ), .O(\complex_num_writes[2]_i_7_n_0 )); LUT2 #( .INIT(4'hE)) \complex_num_writes[2]_i_8 (.I0(\complex_num_writes_reg_n_0_[4] ), .I1(\complex_num_writes_reg_n_0_[3] ), .O(\complex_num_writes[2]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000EEE2E2E2)) \complex_num_writes[3]_i_1 (.I0(\complex_num_writes_reg_n_0_[3] ), .I1(\complex_num_writes[3]_i_2_n_0 ), .I2(\complex_num_writes[3]_i_3_n_0 ), .I3(complex_row0_wr_done), .I4(\complex_num_writes[3]_i_4_n_0 ), .I5(\complex_num_writes[4]_i_6_n_0 ), .O(\complex_num_writes[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair570" *) LUT3 #( .INIT(8'hF8)) \complex_num_writes[3]_i_2 (.I0(\complex_num_writes[4]_i_5_n_0 ), .I1(\complex_num_writes[4]_i_4_n_0 ), .I2(\complex_num_writes[4]_i_2_n_0 ), .O(\complex_num_writes[3]_i_2_n_0 )); LUT6 #( .INIT(64'h8AA8A8A8A8A8A8A8)) \complex_num_writes[3]_i_3 (.I0(\complex_num_writes[4]_i_4_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_writes_reg_n_0_[3] ), .I3(\complex_num_writes_reg_n_0_[1] ), .I4(\complex_num_writes_reg_n_0_[0] ), .I5(\complex_num_writes_reg_n_0_[2] ), .O(\complex_num_writes[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000002000)) \complex_num_writes[3]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(Q[2]), .I4(\init_state_r_reg_n_0_[3] ), .I5(prbs_rdlvl_start_i_2_n_0), .O(\complex_num_writes[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000E2E2E2)) \complex_num_writes[4]_i_1 (.I0(\complex_num_writes_reg_n_0_[4] ), .I1(\complex_num_writes[4]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_3_n_0 ), .I3(\complex_num_writes[4]_i_4_n_0 ), .I4(\complex_num_writes[4]_i_5_n_0 ), .I5(\complex_num_writes[4]_i_6_n_0 ), .O(\complex_num_writes[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair575" *) LUT3 #( .INIT(8'h80)) \complex_num_writes[4]_i_10 (.I0(\complex_num_writes_reg_n_0_[2] ), .I1(\complex_num_writes_reg_n_0_[0] ), .I2(\complex_num_writes_reg_n_0_[1] ), .O(\complex_num_writes[4]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair570" *) LUT3 #( .INIT(8'h04)) \complex_num_writes[4]_i_11 (.I0(\complex_num_reads[3]_i_8_n_0 ), .I1(\complex_num_writes[4]_i_4_n_0 ), .I2(\complex_num_writes[4]_i_7_n_0 ), .O(\complex_num_writes[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair603" *) LUT2 #( .INIT(4'h7)) \complex_num_writes[4]_i_12 (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\complex_num_writes[4]_i_12_n_0 )); LUT2 #( .INIT(4'hE)) \complex_num_writes[4]_i_13 (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .O(\complex_num_writes[4]_i_13_n_0 )); LUT6 #( .INIT(64'hEEEEEEECEEECEEEC)) \complex_num_writes[4]_i_14 (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I1(\complex_num_writes[4]_i_13_n_0 ), .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I5(\stg1_wr_rd_cnt[4]_i_3_n_0 ), .O(\complex_num_writes[4]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFEFFFEFFFEFEFE)) \complex_num_writes[4]_i_15 (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ), .O(\complex_num_writes[4]_i_15_n_0 )); LUT5 #( .INIT(32'hEEE2EEEE)) \complex_num_writes[4]_i_2 (.I0(\complex_num_writes[3]_i_4_n_0 ), .I1(\complex_num_writes[4]_i_4_n_0 ), .I2(\complex_num_writes[4]_i_7_n_0 ), .I3(\complex_num_writes[4]_i_8_n_0 ), .I4(\complex_num_writes[4]_i_9_n_0 ), .O(\complex_num_writes[4]_i_2_n_0 )); LUT6 #( .INIT(64'hFF6A6A6AFF000000)) \complex_num_writes[4]_i_3 (.I0(\complex_num_writes_reg_n_0_[4] ), .I1(\complex_num_writes_reg_n_0_[3] ), .I2(\complex_num_writes[4]_i_10_n_0 ), .I3(complex_row0_wr_done), .I4(\complex_num_writes[3]_i_4_n_0 ), .I5(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000008000)) \complex_num_writes[4]_i_4 (.I0(\complex_address[9]_i_3_n_0 ), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[3]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .I5(complex_row0_wr_done), .O(\complex_num_writes[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair486" *) LUT5 #( .INIT(32'h40000000)) \complex_num_writes[4]_i_5 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\complex_num_writes[4]_i_5_n_0 )); LUT2 #( .INIT(4'hE)) \complex_num_writes[4]_i_6 (.I0(\complex_num_writes[2]_i_5_n_0 ), .I1(\complex_num_writes[4]_i_11_n_0 ), .O(\complex_num_writes[4]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF008A00)) \complex_num_writes[4]_i_7 (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I2(\complex_num_writes[4]_i_12_n_0 ), .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I5(\complex_num_writes[4]_i_13_n_0 ), .O(\complex_num_writes[4]_i_7_n_0 )); LUT6 #( .INIT(64'h000000000000222A)) \complex_num_writes[4]_i_8 (.I0(\complex_num_writes[4]_i_14_n_0 ), .I1(\complex_num_writes_reg_n_0_[2] ), .I2(\complex_num_writes_reg_n_0_[0] ), .I3(\complex_num_writes_reg_n_0_[1] ), .I4(\complex_num_writes_reg_n_0_[4] ), .I5(\complex_num_writes_reg_n_0_[3] ), .O(\complex_num_writes[4]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFE080)) \complex_num_writes[4]_i_9 (.I0(\complex_num_writes_reg_n_0_[1] ), .I1(\complex_num_writes_reg_n_0_[2] ), .I2(\complex_num_writes_reg_n_0_[3] ), .I3(\complex_num_writes[4]_i_15_n_0 ), .I4(\complex_num_writes[4]_i_14_n_0 ), .I5(\complex_num_writes_reg_n_0_[4] ), .O(\complex_num_writes[4]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair575" *) LUT3 #( .INIT(8'h74)) \complex_num_writes_dec[0]_i_1 (.I0(complex_num_writes_dec_reg__0[0]), .I1(\complex_num_writes_dec[4]_i_4_n_0 ), .I2(\complex_num_writes_reg_n_0_[0] ), .O(p_0_in__7[0])); LUT4 #( .INIT(16'h9F90)) \complex_num_writes_dec[1]_i_1 (.I0(complex_num_writes_dec_reg__0[0]), .I1(complex_num_writes_dec_reg__0[1]), .I2(\complex_num_writes_dec[4]_i_4_n_0 ), .I3(\complex_num_writes_reg_n_0_[1] ), .O(p_0_in__7[1])); (* SOFT_HLUTNM = "soft_lutpair488" *) LUT5 #( .INIT(32'hA9FFA900)) \complex_num_writes_dec[2]_i_1 (.I0(complex_num_writes_dec_reg__0[2]), .I1(complex_num_writes_dec_reg__0[1]), .I2(complex_num_writes_dec_reg__0[0]), .I3(\complex_num_writes_dec[4]_i_4_n_0 ), .I4(\complex_num_writes_reg_n_0_[2] ), .O(p_0_in__7[2])); LUT6 #( .INIT(64'hAAA9FFFFAAA90000)) \complex_num_writes_dec[3]_i_1 (.I0(complex_num_writes_dec_reg__0[3]), .I1(complex_num_writes_dec_reg__0[2]), .I2(complex_num_writes_dec_reg__0[0]), .I3(complex_num_writes_dec_reg__0[1]), .I4(\complex_num_writes_dec[4]_i_4_n_0 ), .I5(\complex_num_writes_reg_n_0_[3] ), .O(p_0_in__7[3])); LUT2 #( .INIT(4'hE)) \complex_num_writes_dec[4]_i_1 (.I0(prbs_rdlvl_done_pulse), .I1(rstdiv0_sync_r1_reg_rep__23), .O(complex_row0_rd_done1)); LUT5 #( .INIT(32'hDDDDDDD5)) \complex_num_writes_dec[4]_i_2 (.I0(\complex_num_writes_dec[4]_i_4_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I2(complex_num_writes_dec_reg__0[1]), .I3(complex_num_writes_dec_reg__0[0]), .I4(\complex_num_writes_dec[4]_i_5_n_0 ), .O(\complex_num_writes_dec[4]_i_2_n_0 )); LUT6 #( .INIT(64'hAA9AFFFFAA9A0000)) \complex_num_writes_dec[4]_i_3 (.I0(complex_num_writes_dec_reg__0[4]), .I1(complex_num_writes_dec_reg__0[3]), .I2(\complex_num_writes_dec[4]_i_6_n_0 ), .I3(complex_num_writes_dec_reg__0[2]), .I4(\complex_num_writes_dec[4]_i_4_n_0 ), .I5(\complex_num_writes_reg_n_0_[4] ), .O(p_0_in__7[4])); LUT5 #( .INIT(32'h10111111)) \complex_num_writes_dec[4]_i_4 (.I0(stg1_wr_done), .I1(\complex_num_writes[3]_i_4_n_0 ), .I2(complex_row0_rd_done), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(\complex_address[9]_i_3_n_0 ), .O(\complex_num_writes_dec[4]_i_4_n_0 )); LUT3 #( .INIT(8'hFE)) \complex_num_writes_dec[4]_i_5 (.I0(complex_num_writes_dec_reg__0[3]), .I1(complex_num_writes_dec_reg__0[2]), .I2(complex_num_writes_dec_reg__0[4]), .O(\complex_num_writes_dec[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair488" *) LUT2 #( .INIT(4'h1)) \complex_num_writes_dec[4]_i_6 (.I0(complex_num_writes_dec_reg__0[0]), .I1(complex_num_writes_dec_reg__0[1]), .O(\complex_num_writes_dec[4]_i_6_n_0 )); FDSE #( .INIT(1'b1)) \complex_num_writes_dec_reg[0] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[0]), .Q(complex_num_writes_dec_reg__0[0]), .S(complex_row0_rd_done1)); FDRE #( .INIT(1'b0)) \complex_num_writes_dec_reg[1] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[1]), .Q(complex_num_writes_dec_reg__0[1]), .R(complex_row0_rd_done1)); FDRE #( .INIT(1'b0)) \complex_num_writes_dec_reg[2] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[2]), .Q(complex_num_writes_dec_reg__0[2]), .R(complex_row0_rd_done1)); FDRE #( .INIT(1'b0)) \complex_num_writes_dec_reg[3] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[3]), .Q(complex_num_writes_dec_reg__0[3]), .R(complex_row0_rd_done1)); FDRE #( .INIT(1'b0)) \complex_num_writes_dec_reg[4] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[4]), .Q(complex_num_writes_dec_reg__0[4]), .R(complex_row0_rd_done1)); FDRE #( .INIT(1'b0)) \complex_num_writes_reg[0] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[0]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_writes_reg[1] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[1]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_writes_reg[2] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[2]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_writes_reg[3] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[3]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_num_writes_reg[4] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[4]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[4] ), .R(1'b0)); LUT5 #( .INIT(32'h0000AABA)) complex_ocal_odt_ext_i_1 (.I0(complex_ocal_odt_ext), .I1(complex_ocal_odt_ext_i_2_n_0), .I2(Q[5]), .I3(Q[1]), .I4(complex_ocal_odt_ext_i_3_n_0), .O(complex_ocal_odt_ext_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair538" *) LUT4 #( .INIT(16'hFFFE)) complex_ocal_odt_ext_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .O(complex_ocal_odt_ext_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFF400040F0)) complex_ocal_odt_ext_i_3 (.I0(\back_to_back_reads_4_1.num_reads_reg[0]_0 ), .I1(cnt_cmd_done_m7_r), .I2(Q[1]), .I3(Q[0]), .I4(complex_ocal_odt_ext_i_4_n_0), .I5(rstdiv0_sync_r1_reg_rep__23), .O(complex_ocal_odt_ext_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair518" *) LUT5 #( .INIT(32'hFFEFFFFF)) complex_ocal_odt_ext_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .O(complex_ocal_odt_ext_i_4_n_0)); FDRE #( .INIT(1'b0)) complex_ocal_odt_ext_reg (.C(CLK), .CE(1'b1), .D(complex_ocal_odt_ext_i_1_n_0), .Q(complex_ocal_odt_ext), .R(1'b0)); LUT6 #( .INIT(64'h44444F4444444444)) complex_ocal_reset_rd_addr_i_1 (.I0(prbs_last_byte_done_r), .I1(prbs_last_byte_done), .I2(complex_ocal_reset_rd_addr_i_2_n_0), .I3(complex_wait_cnt_reg__0[3]), .I4(complex_wait_cnt_reg__0[2]), .I5(complex_ocal_reset_rd_addr_i_3_n_0), .O(complex_ocal_reset_rd_addr0)); (* SOFT_HLUTNM = "soft_lutpair602" *) LUT2 #( .INIT(4'hB)) complex_ocal_reset_rd_addr_i_2 (.I0(complex_wait_cnt_reg__0[1]), .I1(complex_wait_cnt_reg__0[0]), .O(complex_ocal_reset_rd_addr_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) complex_ocal_reset_rd_addr_i_3 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r[4]_i_5_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(complex_ocal_reset_rd_addr_i_3_n_0)); FDRE #( .INIT(1'b0)) complex_ocal_reset_rd_addr_reg (.C(CLK), .CE(1'b1), .D(complex_ocal_reset_rd_addr0), .Q(complex_ocal_reset_rd_addr), .R(1'b0)); LUT2 #( .INIT(4'hE)) complex_ocal_wr_start_i_1 (.I0(complex_ocal_reset_rd_addr), .I1(complex_ocal_wr_start), .O(complex_ocal_wr_start_i_1_n_0)); FDRE #( .INIT(1'b0)) complex_ocal_wr_start_reg (.C(CLK), .CE(1'b1), .D(complex_ocal_wr_start_i_1_n_0), .Q(complex_ocal_wr_start), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) complex_oclkdelay_calib_done_r1_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_reg_rep), .Q(complex_oclkdelay_calib_done_r1), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'hFFFFFFFF00040000)) complex_oclkdelay_calib_start_int_i_1 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(complex_oclkdelay_calib_start_int_reg_0), .I4(prbs_last_byte_done_r), .I5(complex_oclkdelay_calib_start_int), .O(complex_oclkdelay_calib_start_int_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair569" *) LUT3 #( .INIT(8'hDF)) complex_oclkdelay_calib_start_int_i_2 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .O(complex_oclkdelay_calib_start_int_i_2_n_0)); LUT2 #( .INIT(4'hB)) complex_oclkdelay_calib_start_int_i_3 (.I0(Q[0]), .I1(Q[1]), .O(complex_oclkdelay_calib_start_int_reg_0)); FDRE #( .INIT(1'b0)) complex_oclkdelay_calib_start_int_reg (.C(CLK), .CE(1'b1), .D(complex_oclkdelay_calib_start_int_i_1_n_0), .Q(complex_oclkdelay_calib_start_int), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) complex_oclkdelay_calib_start_r1_reg (.C(CLK), .CE(1'b1), .D(complex_oclkdelay_calib_start_int), .Q(complex_oclkdelay_calib_start_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) complex_oclkdelay_calib_start_r2_reg (.C(CLK), .CE(1'b1), .D(complex_oclkdelay_calib_start_r1), .Q(complex_oclkdelay_calib_start_r2), .R(1'b0)); LUT6 #( .INIT(64'h000000000000AAEA)) complex_odt_ext_i_1 (.I0(complex_odt_ext), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I2(rdlvl_stg1_done_r1), .I3(complex_sample_cnt_inc_i_2_n_0), .I4(complex_row1_rd_done_i_2_n_0), .I5(rstdiv0_sync_r1_reg_rep__23), .O(complex_odt_ext_i_1_n_0)); FDRE #( .INIT(1'b0)) complex_odt_ext_reg (.C(CLK), .CE(1'b1), .D(complex_odt_ext_i_1_n_0), .Q(complex_odt_ext), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair557" *) LUT4 #( .INIT(16'h0002)) complex_row0_rd_done_i_1 (.I0(complex_row0_rd_done_i_2_n_0), .I1(prbs_rdlvl_done_pulse), .I2(rstdiv0_sync_r1_reg_rep__24), .I3(complex_sample_cnt_inc), .O(complex_row0_rd_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF0000E000)) complex_row0_rd_done_i_2 (.I0(prbs_rdlvl_start_r_reg), .I1(complex_oclkdelay_calib_start_int), .I2(complex_row1_wr_done), .I3(complex_row0_wr_done), .I4(wr_victim_inc_i_2_n_0), .I5(complex_row0_rd_done), .O(complex_row0_rd_done_i_2_n_0)); FDRE #( .INIT(1'b0)) complex_row0_rd_done_reg (.C(CLK), .CE(1'b1), .D(complex_row0_rd_done_i_1_n_0), .Q(complex_row0_rd_done), .R(1'b0)); LUT5 #( .INIT(32'h0000009A)) \complex_row1_rd_cnt[0]_i_1 (.I0(complex_row1_rd_cnt[0]), .I1(complex_row1_rd_done_r1), .I2(complex_row1_rd_done), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(prbs_rdlvl_done_pulse), .O(\complex_row1_rd_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000009AAA)) \complex_row1_rd_cnt[1]_i_1 (.I0(complex_row1_rd_cnt[1]), .I1(complex_row1_rd_done_r1), .I2(complex_row1_rd_done), .I3(complex_row1_rd_cnt[0]), .I4(rstdiv0_sync_r1_reg_rep__24), .I5(prbs_rdlvl_done_pulse), .O(\complex_row1_rd_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000009AAAAAAA)) \complex_row1_rd_cnt[2]_i_1 (.I0(complex_row1_rd_cnt[2]), .I1(complex_row1_rd_done_r1), .I2(complex_row1_rd_done), .I3(complex_row1_rd_cnt[0]), .I4(complex_row1_rd_cnt[1]), .I5(complex_row0_rd_done1), .O(\complex_row1_rd_cnt[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \complex_row1_rd_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\complex_row1_rd_cnt[0]_i_1_n_0 ), .Q(complex_row1_rd_cnt[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_row1_rd_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\complex_row1_rd_cnt[1]_i_1_n_0 ), .Q(complex_row1_rd_cnt[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \complex_row1_rd_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\complex_row1_rd_cnt[2]_i_1_n_0 ), .Q(complex_row1_rd_cnt[2]), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000AE)) complex_row1_rd_done_i_1 (.I0(complex_row1_rd_done), .I1(complex_row0_rd_done), .I2(wr_victim_inc_i_2_n_0), .I3(complex_row1_rd_done_i_2_n_0), .I4(prbs_rdlvl_done_pulse), .I5(rstdiv0_sync_r1_reg_rep__24), .O(complex_row1_rd_done_i_1_n_0)); LUT6 #( .INIT(64'h0000000000100000)) complex_row1_rd_done_i_2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[3]), .I5(Q[5]), .O(complex_row1_rd_done_i_2_n_0)); FDRE #( .INIT(1'b0)) complex_row1_rd_done_r1_reg (.C(CLK), .CE(1'b1), .D(complex_row1_rd_done), .Q(complex_row1_rd_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) complex_row1_rd_done_reg (.C(CLK), .CE(1'b1), .D(complex_row1_rd_done_i_1_n_0), .Q(complex_row1_rd_done), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair609" *) LUT1 #( .INIT(2'h1)) \complex_row_cnt_ocal[0]_i_1 (.I0(complex_row_cnt_ocal_reg__0[0]), .O(p_0_in__5[0])); (* SOFT_HLUTNM = "soft_lutpair609" *) LUT2 #( .INIT(4'h6)) \complex_row_cnt_ocal[1]_i_1 (.I0(complex_row_cnt_ocal_reg__0[1]), .I1(complex_row_cnt_ocal_reg__0[0]), .O(p_0_in__5[1])); (* SOFT_HLUTNM = "soft_lutpair560" *) LUT3 #( .INIT(8'h6A)) \complex_row_cnt_ocal[2]_i_1 (.I0(complex_row_cnt_ocal_reg__0[2]), .I1(complex_row_cnt_ocal_reg__0[0]), .I2(complex_row_cnt_ocal_reg__0[1]), .O(p_0_in__5[2])); (* SOFT_HLUTNM = "soft_lutpair560" *) LUT4 #( .INIT(16'h6AAA)) \complex_row_cnt_ocal[3]_i_1 (.I0(complex_row_cnt_ocal_reg__0[3]), .I1(complex_row_cnt_ocal_reg__0[1]), .I2(complex_row_cnt_ocal_reg__0[0]), .I3(complex_row_cnt_ocal_reg__0[2]), .O(p_0_in__5[3])); (* SOFT_HLUTNM = "soft_lutpair480" *) LUT5 #( .INIT(32'h6AAAAAAA)) \complex_row_cnt_ocal[4]_i_1 (.I0(complex_row_cnt_ocal_reg__0[4]), .I1(complex_row_cnt_ocal_reg__0[3]), .I2(complex_row_cnt_ocal_reg__0[2]), .I3(complex_row_cnt_ocal_reg__0[0]), .I4(complex_row_cnt_ocal_reg__0[1]), .O(p_0_in__5[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \complex_row_cnt_ocal[5]_i_1 (.I0(complex_row_cnt_ocal_reg__0[5]), .I1(complex_row_cnt_ocal_reg__0[1]), .I2(complex_row_cnt_ocal_reg__0[0]), .I3(complex_row_cnt_ocal_reg__0[2]), .I4(complex_row_cnt_ocal_reg__0[3]), .I5(complex_row_cnt_ocal_reg__0[4]), .O(p_0_in__5[5])); (* SOFT_HLUTNM = "soft_lutpair509" *) LUT4 #( .INIT(16'h6AAA)) \complex_row_cnt_ocal[6]_i_1 (.I0(complex_row_cnt_ocal_reg__0[6]), .I1(complex_row_cnt_ocal_reg__0[4]), .I2(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I3(complex_row_cnt_ocal_reg__0[5]), .O(p_0_in__5[6])); LUT5 #( .INIT(32'hFFFFFFFB)) \complex_row_cnt_ocal[7]_i_1 (.I0(\complex_row_cnt_ocal_reg[0]_0 ), .I1(rdlvl_stg1_done_r1), .I2(complex_byte_rd_done), .I3(rstdiv0_sync_r1_reg_rep__23), .I4(prbs_rdlvl_done_pulse), .O(complex_row_cnt_ocal0)); LUT6 #( .INIT(64'hAAAAAAAAAAAA0800)) \complex_row_cnt_ocal[7]_i_2 (.I0(\complex_row_cnt_ocal[7]_i_5_n_0 ), .I1(\complex_row_cnt_ocal[7]_i_6_n_0 ), .I2(\complex_row_cnt_ocal[7]_i_7_n_0 ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(wr_victim_inc), .I5(complex_sample_cnt_inc_r2), .O(complex_row_cnt_ocal)); (* SOFT_HLUTNM = "soft_lutpair509" *) LUT5 #( .INIT(32'h6AAAAAAA)) \complex_row_cnt_ocal[7]_i_3 (.I0(complex_row_cnt_ocal_reg__0[7]), .I1(complex_row_cnt_ocal_reg__0[5]), .I2(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I3(complex_row_cnt_ocal_reg__0[4]), .I4(complex_row_cnt_ocal_reg__0[6]), .O(p_0_in__5[7])); LUT6 #( .INIT(64'h0000000000000008)) \complex_row_cnt_ocal[7]_i_4 (.I0(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I1(wr_victim_inc), .I2(complex_row_cnt_ocal_reg__0[4]), .I3(complex_row_cnt_ocal_reg__0[7]), .I4(complex_row_cnt_ocal_reg__0[5]), .I5(complex_row_cnt_ocal_reg__0[6]), .O(\complex_row_cnt_ocal_reg[0]_0 )); LUT6 #( .INIT(64'h0000000000000004)) \complex_row_cnt_ocal[7]_i_5 (.I0(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I1(prbs_rdlvl_done_reg_rep), .I2(complex_row_cnt_ocal_reg__0[4]), .I3(complex_row_cnt_ocal_reg__0[7]), .I4(complex_row_cnt_ocal_reg__0[5]), .I5(complex_row_cnt_ocal_reg__0[6]), .O(\complex_row_cnt_ocal[7]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000002000)) \complex_row_cnt_ocal[7]_i_6 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\wrcal_reads[7]_i_5_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(\complex_row_cnt_ocal[7]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFFFFFFFF)) \complex_row_cnt_ocal[7]_i_7 (.I0(\complex_row_cnt_ocal[7]_i_9_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[1] ), .O(\complex_row_cnt_ocal[7]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair480" *) LUT4 #( .INIT(16'h8000)) \complex_row_cnt_ocal[7]_i_8 (.I0(complex_row_cnt_ocal_reg__0[1]), .I1(complex_row_cnt_ocal_reg__0[0]), .I2(complex_row_cnt_ocal_reg__0[2]), .I3(complex_row_cnt_ocal_reg__0[3]), .O(\complex_row_cnt_ocal[7]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair514" *) LUT3 #( .INIT(8'hFE)) \complex_row_cnt_ocal[7]_i_9 (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ), .O(\complex_row_cnt_ocal[7]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[0] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[0]), .Q(complex_row_cnt_ocal_reg__0[0]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[1] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[1]), .Q(complex_row_cnt_ocal_reg__0[1]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[2] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[2]), .Q(complex_row_cnt_ocal_reg__0[2]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[3] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[3]), .Q(complex_row_cnt_ocal_reg__0[3]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[4] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[4]), .Q(complex_row_cnt_ocal_reg__0[4]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[5] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[5]), .Q(complex_row_cnt_ocal_reg__0[5]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[6] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[6]), .Q(complex_row_cnt_ocal_reg__0[6]), .R(complex_row_cnt_ocal0)); FDRE #( .INIT(1'b0)) \complex_row_cnt_ocal_reg[7] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[7]), .Q(complex_row_cnt_ocal_reg__0[7]), .R(complex_row_cnt_ocal0)); LUT2 #( .INIT(4'h2)) complex_sample_cnt_inc_i_1 (.I0(complex_row1_rd_done), .I1(complex_sample_cnt_inc_i_2_n_0), .O(complex_sample_cnt_inc0)); (* SOFT_HLUTNM = "soft_lutpair486" *) LUT5 #( .INIT(32'hFFFFFFEF)) complex_sample_cnt_inc_i_2 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(complex_sample_cnt_inc_i_2_n_0)); FDRE #( .INIT(1'b0)) complex_sample_cnt_inc_r1_reg (.C(CLK), .CE(1'b1), .D(complex_sample_cnt_inc), .Q(complex_sample_cnt_inc_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) complex_sample_cnt_inc_r2_reg (.C(CLK), .CE(1'b1), .D(complex_sample_cnt_inc_r1), .Q(complex_sample_cnt_inc_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) complex_sample_cnt_inc_reg (.C(CLK), .CE(1'b1), .D(complex_sample_cnt_inc0), .Q(complex_sample_cnt_inc), .R(rstdiv0_sync_r1_reg_rep__11)); LUT1 #( .INIT(2'h1)) \complex_wait_cnt[0]_i_1 (.I0(complex_wait_cnt_reg__0[0]), .O(p_0_in__6[0])); (* SOFT_HLUTNM = "soft_lutpair602" *) LUT2 #( .INIT(4'h6)) \complex_wait_cnt[1]_i_1 (.I0(complex_wait_cnt_reg__0[1]), .I1(complex_wait_cnt_reg__0[0]), .O(p_0_in__6[1])); (* SOFT_HLUTNM = "soft_lutpair554" *) LUT3 #( .INIT(8'h78)) \complex_wait_cnt[2]_i_1 (.I0(complex_wait_cnt_reg__0[1]), .I1(complex_wait_cnt_reg__0[0]), .I2(complex_wait_cnt_reg__0[2]), .O(p_0_in__6[2])); LUT6 #( .INIT(64'hFFFFFFFFFBABEFBF)) \complex_wait_cnt[3]_i_1 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(Q[0]), .I5(\complex_wait_cnt[3]_i_3_n_0 ), .O(\complex_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair554" *) LUT4 #( .INIT(16'h6AAA)) \complex_wait_cnt[3]_i_2 (.I0(complex_wait_cnt_reg__0[3]), .I1(complex_wait_cnt_reg__0[1]), .I2(complex_wait_cnt_reg__0[0]), .I3(complex_wait_cnt_reg__0[2]), .O(p_0_in__6[3])); (* SOFT_HLUTNM = "soft_lutpair502" *) LUT5 #( .INIT(32'hEAAAAAAA)) \complex_wait_cnt[3]_i_3 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(complex_wait_cnt_reg__0[3]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .O(\complex_wait_cnt[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \complex_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__6[0]), .Q(complex_wait_cnt_reg__0[0]), .R(\complex_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \complex_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__6[1]), .Q(complex_wait_cnt_reg__0[1]), .R(\complex_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \complex_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__6[2]), .Q(complex_wait_cnt_reg__0[2]), .R(\complex_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \complex_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__6[3]), .Q(complex_wait_cnt_reg__0[3]), .R(\complex_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair585" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[0]), .O(\data_offset_1_i1_reg[5] [0])); (* SOFT_HLUTNM = "soft_lutpair586" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[1] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[1]), .O(\data_offset_1_i1_reg[5] [1])); (* SOFT_HLUTNM = "soft_lutpair587" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[2]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[2] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[2]), .O(\data_offset_1_i1_reg[5] [2])); (* SOFT_HLUTNM = "soft_lutpair588" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[3]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[3] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[3]), .O(\data_offset_1_i1_reg[5] [3])); (* SOFT_HLUTNM = "soft_lutpair587" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[4]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[4] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[4]), .O(\data_offset_1_i1_reg[5] [4])); (* SOFT_HLUTNM = "soft_lutpair586" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[5]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[5]), .O(\data_offset_1_i1_reg[5] [5])); (* SOFT_HLUTNM = "soft_lutpair536" *) LUT4 #( .INIT(16'h8000)) ddr2_pre_flag_r_i_2 (.I0(ddr2_refresh_flag_r_reg_0), .I1(cnt_cmd_done_r), .I2(ddr2_refresh_flag_r), .I3(cnt_init_mr_done_r), .O(ddr2_pre_flag_r_reg_1)); FDRE #( .INIT(1'b0)) ddr2_pre_flag_r_reg (.C(CLK), .CE(1'b1), .D(ddr2_pre_flag_r_reg_2), .Q(ddr2_pre_flag_r_reg_0), .R(1'b0)); LUT6 #( .INIT(64'h0000010000000000)) ddr2_refresh_flag_r_i_2 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[5]), .I2(Q[4]), .I3(Q[0]), .I4(Q[3]), .I5(Q[1]), .O(ddr2_refresh_flag_r_reg_0)); FDRE #( .INIT(1'b0)) ddr2_refresh_flag_r_reg (.C(CLK), .CE(1'b1), .D(cnt_cmd_done_r_reg_0), .Q(ddr2_refresh_flag_r), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000200)) ddr3_lm_done_r_i_1 (.I0(wrcal_done_reg_10), .I1(oclk_calib_resume_level_reg_0), .I2(\init_state_r[5]_i_2_n_0 ), .I3(Q[0]), .I4(ddr3_lm_done_r_i_2_n_0), .I5(ddr3_lm_done_r), .O(ddr3_lm_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair495" *) LUT2 #( .INIT(4'hB)) ddr3_lm_done_r_i_2 (.I0(Q[3]), .I1(Q[1]), .O(ddr3_lm_done_r_i_2_n_0)); FDRE #( .INIT(1'b0)) ddr3_lm_done_r_reg (.C(CLK), .CE(1'b1), .D(ddr3_lm_done_r_i_1_n_0), .Q(ddr3_lm_done_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'h0000000000000080)) detect_pi_found_dqs_i_1 (.I0(\cnt_cmd_r_reg_n_0_[5] ), .I1(\cnt_cmd_r[6]_i_5_n_0 ), .I2(Q[1]), .I3(Q[0]), .I4(\back_to_back_reads_4_1.num_reads_reg[0]_0 ), .I5(\cnt_cmd_r_reg_n_0_[6] ), .O(detect_pi_found_dqs0)); FDRE #( .INIT(1'b0)) detect_pi_found_dqs_reg (.C(CLK), .CE(1'b1), .D(detect_pi_found_dqs0), .Q(detect_pi_found_dqs), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h00000000DADA00DA)) \dqs_asrt_cnt[0]_i_1 (.I0(dqs_asrt_cnt[0]), .I1(dqs_asrt_cnt[1]), .I2(wr_level_dqs_asrt), .I3(wrlvl_done_r), .I4(wrlvl_done_r1), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\dqs_asrt_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000ECEC00EC)) \dqs_asrt_cnt[1]_i_1 (.I0(dqs_asrt_cnt[0]), .I1(dqs_asrt_cnt[1]), .I2(wr_level_dqs_asrt), .I3(wrlvl_done_r), .I4(wrlvl_done_r1), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\dqs_asrt_cnt[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \dqs_asrt_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\dqs_asrt_cnt[0]_i_1_n_0 ), .Q(dqs_asrt_cnt[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dqs_asrt_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\dqs_asrt_cnt[1]_i_1_n_0 ), .Q(dqs_asrt_cnt[1]), .R(1'b0)); LUT6 #( .INIT(64'h000000000F0F0F0E)) \en_cnt_div4.enable_wrlvl_cnt[0]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(rstdiv0_sync_r1_reg_rep__23_0), .O(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000F00FF00E)) \en_cnt_div4.enable_wrlvl_cnt[1]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(rstdiv0_sync_r1_reg_rep__23_0), .O(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFF0000E)) \en_cnt_div4.enable_wrlvl_cnt[2]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ), .O(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAA4)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_2 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ), .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h444444444444444F)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_3 (.I0(enable_wrlvl_cnt0), .I1(wrlvl_odt), .I2(read_calib_reg_0), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair516" *) LUT5 #( .INIT(32'hFFFFFFFE)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_4 (.I0(enable_wrlvl_cnt[2]), .I1(enable_wrlvl_cnt[1]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[4]), .I4(enable_wrlvl_cnt[3]), .O(enable_wrlvl_cnt0)); LUT6 #( .INIT(64'h00000000CCCCCCC8)) \en_cnt_div4.enable_wrlvl_cnt[4]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(rstdiv0_sync_r1_reg_rep__23_0), .O(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \en_cnt_div4.enable_wrlvl_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ), .Q(enable_wrlvl_cnt[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \en_cnt_div4.enable_wrlvl_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ), .Q(enable_wrlvl_cnt[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \en_cnt_div4.enable_wrlvl_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ), .Q(enable_wrlvl_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \en_cnt_div4.enable_wrlvl_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ), .Q(enable_wrlvl_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \en_cnt_div4.enable_wrlvl_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ), .Q(enable_wrlvl_cnt[4]), .R(1'b0)); LUT4 #( .INIT(16'h000E)) \en_cnt_div4.wrlvl_odt_i_1 (.I0(wrlvl_odt), .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ), .I2(wrlvl_odt_ctl), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\en_cnt_div4.wrlvl_odt_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair516" *) LUT5 #( .INIT(32'h00000010)) \en_cnt_div4.wrlvl_odt_i_2 (.I0(enable_wrlvl_cnt[4]), .I1(enable_wrlvl_cnt[3]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[2]), .I4(enable_wrlvl_cnt[1]), .O(\en_cnt_div4.wrlvl_odt_i_2_n_0 )); FDRE #( .INIT(1'b0)) \en_cnt_div4.wrlvl_odt_reg (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.wrlvl_odt_i_1_n_0 ), .Q(wrlvl_odt), .R(1'b0)); LUT4 #( .INIT(16'hFFF4)) first_rdlvl_pat_r_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(first_rdlvl_pat_r), .I2(rdlvl_stg1_rank_done), .I3(rstdiv0_sync_r1_reg_rep__23), .O(first_rdlvl_pat_r_i_1_n_0)); FDRE #( .INIT(1'b0)) first_rdlvl_pat_r_reg (.C(CLK), .CE(1'b1), .D(first_rdlvl_pat_r_i_1_n_0), .Q(first_rdlvl_pat_r), .R(1'b0)); LUT6 #( .INIT(64'hFEFEFEFEFEFCFEFF)) first_wrcal_pat_r_i_1 (.I0(first_wrcal_pat_r), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(wrcal_resume_w), .I3(Q[1]), .I4(Q[0]), .I5(first_wrcal_pat_r_i_2_n_0), .O(first_wrcal_pat_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair491" *) LUT5 #( .INIT(32'hFFFFFEFF)) first_wrcal_pat_r_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[5]), .I3(Q[4]), .I4(Q[3]), .O(first_wrcal_pat_r_i_2_n_0)); FDRE #( .INIT(1'b0)) first_wrcal_pat_r_reg (.C(CLK), .CE(1'b1), .D(first_wrcal_pat_r_i_1_n_0), .Q(first_wrcal_pat_r), .R(1'b0)); LUT6 #( .INIT(64'h0404550404040404)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ), .I3(reg_ctrl_cnt_r), .I4(reg_ctrl_cnt_r_reg__0[3]), .I5(reg_ctrl_cnt_r_reg__0[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F44FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\complex_address_reg_n_0_[0] ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 )); LUT6 #( .INIT(64'h5515FFFF55155515)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 (.I0(Q[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 )); LUT6 #( .INIT(64'h000000000000005D)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(complex_row_cnt_ocal_reg__0[0]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFF888)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I2(\complex_address_reg_n_0_[0] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I4(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0D0FF)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 )); LUT2 #( .INIT(4'h1)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair580" *) LUT2 #( .INIT(4'hE)) \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 )); LUT6 #( .INIT(64'h0010009000000010)) \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 (.I0(Q[0]), .I1(Q[1]), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 )); LUT6 #( .INIT(64'h0000554000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I1(cnt_init_mr_r[0]), .I2(cnt_init_mr_r[1]), .I3(dqs_found_done_r_reg_0), .I4(Q[5]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFDFFFD7DFFEFF)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2 (.I0(Q[0]), .I1(Q[3]), .I2(Q[4]), .I3(Q[1]), .I4(\init_state_r_reg_n_0_[3] ), .I5(Q[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair519" *) LUT5 #( .INIT(32'h00000010)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4 (.I0(Q[2]), .I1(Q[4]), .I2(Q[1]), .I3(Q[3]), .I4(Q[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 )); LUT6 #( .INIT(64'h0004010000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[5]), .I3(Q[3]), .I4(Q[4]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 (.I0(Q[0]), .I1(Q[1]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFF80)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFEAEAEAFFFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 (.I0(prbs_rdlvl_done_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I2(\complex_address_reg_n_0_[1] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F44FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\complex_address_reg_n_0_[1] ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair540" *) LUT3 #( .INIT(8'h08)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 (.I0(reg_ctrl_cnt_r), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r_reg__0[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0D0FF)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 )); LUT6 #( .INIT(64'h000000000000005D)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(complex_row_cnt_ocal_reg__0[1]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ), .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 )); LUT2 #( .INIT(4'h1)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 )); LUT6 #( .INIT(64'h010101FF01010101)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 )); LUT2 #( .INIT(4'h1)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 )); LUT6 #( .INIT(64'h5FF55FF50F3F0F30)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 (.I0(\gen_rnk[0].mr1_r_reg[0]_196 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000022202220222)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ), .I1(prbs_rdlvl_done_reg), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I3(\complex_address_reg_n_0_[2] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F44FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\complex_address_reg_n_0_[2] ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFF8080808080)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 (.I0(dqs_found_done_r_reg), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg_rep), .I3(cnt_init_mr_r[0]), .I4(\gen_rnk[0].mr1_r_reg[0]_196 ), .I5(cnt_init_mr_r[1]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair583" *) LUT3 #( .INIT(8'hEF)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 (.I0(reg_ctrl_cnt_r_reg__0[3]), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r_reg__0[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0D0FF)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 )); LUT6 #( .INIT(64'h000000000000005D)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(complex_row_cnt_ocal_reg__0[2]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 )); LUT6 #( .INIT(64'h000000000000AAAB)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 )); LUT5 #( .INIT(32'h0047FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I2(\complex_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I4(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000D000D0D0)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4 (.I0(complex_row_cnt_ocal_reg__0[3]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000AAA222A2)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\complex_address_reg_n_0_[3] ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000FFEFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[5]), .I2(Q[4]), .I3(Q[3]), .I4(Q[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 )); LUT2 #( .INIT(4'hE)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ), .I1(burst_addr_r_reg_0), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF4044)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 )); LUT6 #( .INIT(64'hABABABABABAAABAB)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FEEEFEFE)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FBFB00F3)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0014551455140014)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I1(\complex_address_reg_n_0_[4] ), .I2(\complex_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 )); LUT3 #( .INIT(8'h82)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 )); LUT6 #( .INIT(64'hBEFFBEAAAAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6 (.I0(prbs_rdlvl_done_reg), .I1(\complex_address_reg_n_0_[3] ), .I2(\complex_address_reg_n_0_[4] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 )); LUT3 #( .INIT(8'h02)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7 (.I0(complex_row_cnt_ocal_reg__0[4]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair551" *) LUT2 #( .INIT(4'h6)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 )); LUT5 #( .INIT(32'h00000100)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9 (.I0(init_state_r1[5]), .I1(init_state_r1[4]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ), .I3(init_state_r1[3]), .I4(init_state_r1[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 )); LUT6 #( .INIT(64'h0004000400045555)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFEEEF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I2(read_calib_reg_0), .I3(read_calib_i_2_n_0), .I4(\calib_cmd[2]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair499" *) LUT4 #( .INIT(16'h802A)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 )); LUT2 #( .INIT(4'hE)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 )); LUT6 #( .INIT(64'hBEFFBEAAAAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13 (.I0(prbs_rdlvl_done_reg), .I1(\complex_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4500FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FEEEFEFE)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair543" *) LUT4 #( .INIT(16'h00BF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I3(Q[5]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 )); LUT2 #( .INIT(4'hB)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 (.I0(Q[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000FFFFEAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 (.I0(cnt_init_mr_r[1]), .I1(prbs_rdlvl_done_reg), .I2(rdlvl_stg1_done_int_reg), .I3(dqs_found_done_r_reg), .I4(cnt_init_mr_r[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 )); LUT3 #( .INIT(8'h6A)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 )); LUT6 #( .INIT(64'hFF020202FFFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8 (.I0(complex_row_cnt_ocal_reg__0[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 )); LUT6 #( .INIT(64'h5555154000001540)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I1(\complex_address_reg_n_0_[4] ), .I2(\complex_address_reg_n_0_[3] ), .I3(\complex_address_reg_n_0_[5] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 )); LUT5 #( .INIT(32'h888F8888)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 (.I0(\gen_rnk[0].mr1_r_reg[0]_196 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair499" *) LUT5 #( .INIT(32'h80002AAA)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFF10FF10FF10FF)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(complex_row_cnt_ocal_reg__0[6]), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 )); LUT6 #( .INIT(64'h7447474747474747)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I2(\complex_address_reg_n_0_[6] ), .I3(\complex_address_reg_n_0_[5] ), .I4(\complex_address_reg_n_0_[4] ), .I5(\complex_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair580" *) LUT3 #( .INIT(8'h01)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000AA2A222A)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair582" *) LUT3 #( .INIT(8'h4F)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 (.I0(Q[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 )); LUT6 #( .INIT(64'h10FF10FF10FFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ), .I3(prbs_rdlvl_done_reg), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 )); LUT6 #( .INIT(64'h5555FFFFFFEF5555)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I1(dqs_found_done_r_reg_0), .I2(cnt_init_mr_r[1]), .I3(cnt_init_mr_r[0]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0FFD0)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair520" *) LUT4 #( .INIT(16'h6AAA)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair525" *) LUT4 #( .INIT(16'h9555)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9 (.I0(\complex_address_reg_n_0_[6] ), .I1(\complex_address_reg_n_0_[5] ), .I2(\complex_address_reg_n_0_[4] ), .I3(\complex_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 )); LUT6 #( .INIT(64'hAA20AAAAAA20AA20)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair525" *) LUT5 #( .INIT(32'h95555555)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 (.I0(\complex_address_reg_n_0_[7] ), .I1(\complex_address_reg_n_0_[6] ), .I2(\complex_address_reg_n_0_[3] ), .I3(\complex_address_reg_n_0_[4] ), .I4(\complex_address_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0FFD0)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00100000)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[5]), .I2(Q[4]), .I3(Q[3]), .I4(Q[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 )); LUT4 #( .INIT(16'hFBAA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(complex_row_cnt_ocal_reg__0[7]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 )); LUT4 #( .INIT(16'h5101)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 )); LUT6 #( .INIT(64'h5554555555555555)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I3(rdlvl_stg1_done_int_reg), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair510" *) LUT4 #( .INIT(16'h4000)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17 (.I0(init_state_r1[0]), .I1(init_state_r1[3]), .I2(init_state_r1[4]), .I3(init_state_r1[5]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18 (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair543" *) LUT4 #( .INIT(16'h5540)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I3(Q[5]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 )); LUT6 #( .INIT(64'h0020000000000070)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[1]), .I3(Q[3]), .I4(Q[0]), .I5(Q[4]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 )); LUT6 #( .INIT(64'h0040444055555555)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 (.I0(prbs_rdlvl_done_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000BBBAFFBA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6EEF)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 (.I0(Q[0]), .I1(Q[3]), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[4]), .I5(Q[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 )); LUT6 #( .INIT(64'hFF54000000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 (.I0(complex_row0_rd_done), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair520" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair498" *) LUT5 #( .INIT(32'hAAA8AAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(init_state_r1[1]), .I2(init_state_r1[2]), .I3(init_state_r1[6]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF111F0000)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 )); LUT6 #( .INIT(64'h800000007FFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 )); LUT6 #( .INIT(64'h9555555555555555)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 (.I0(\complex_address_reg_n_0_[8] ), .I1(\complex_address_reg_n_0_[7] ), .I2(\complex_address_reg_n_0_[5] ), .I3(\complex_address_reg_n_0_[4] ), .I4(\complex_address_reg_n_0_[3] ), .I5(\complex_address_reg_n_0_[6] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAABAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ), .I2(cnt_init_mr_r[0]), .I3(cnt_init_mr_r[1]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I5(dqs_found_done_r_reg_0), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0404040455045555)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5 (.I0(prbs_rdlvl_done_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF1F110000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair498" *) LUT3 #( .INIT(8'hDF)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 (.I0(init_state_r1[2]), .I1(init_state_r1[6]), .I2(init_state_r1[1]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 )); LUT2 #( .INIT(4'hB)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 (.I0(\complex_address_reg_n_0_[4] ), .I1(\complex_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 )); LUT6 #( .INIT(64'hBBBBBBBBBBBBBBFB)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 (.I0(first_wrcal_pat_r_i_2_n_0), .I1(Q[0]), .I2(wrcal_wr_cnt_reg__0[2]), .I3(wrcal_wr_cnt_reg__0[1]), .I4(wrcal_wr_cnt_reg__0[0]), .I5(wrcal_wr_cnt_reg__0[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF04000000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[3]), .I2(Q[5]), .I3(Q[4]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I5(\calib_cmd[2]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAEEEFAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ), .I1(complex_row0_rd_done), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I3(\one_rank.stg1_wr_done_reg_0 ), .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I5(\complex_row_cnt_ocal[7]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 )); LUT6 #( .INIT(64'h2000000000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ), .I1(\complex_num_writes[4]_i_12_n_0 ), .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair558" *) LUT3 #( .INIT(8'h02)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19 (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair555" *) LUT2 #( .INIT(4'h6)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ), .I1(init_state_r1[5]), .I2(init_state_r1[4]), .I3(init_state_r1[0]), .I4(init_state_r1[3]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 (.I0(\complex_address_reg_n_0_[9] ), .I1(\complex_address_reg_n_0_[8] ), .I2(\complex_address_reg_n_0_[6] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ), .I4(\complex_address_reg_n_0_[5] ), .I5(\complex_address_reg_n_0_[7] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAFFABABAB)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 )); LUT4 #( .INIT(16'h00FD)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 (.I0(init_state_r1[3]), .I1(wrlvl_odt_ctl_i_3_n_0), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 )); LUT6 #( .INIT(64'h00000300AAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ), .I1(oclk_wr_cnt_reg__0[3]), .I2(oclk_wr_cnt_reg__0[1]), .I3(oclk_wr_cnt_reg__0[2]), .I4(oclk_wr_cnt_reg__0[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .R(1'b0)); LUT6 #( .INIT(64'h888888888888888A)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ), .I3(Q[4]), .I4(Q[3]), .I5(Q[0]), .O(bank_w[0])); LUT6 #( .INIT(64'h0D0F0F0F0F0F040F)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .I3(\wrcal_reads[7]_i_5_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 )); LUT6 #( .INIT(64'h2000000028000000)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(Q[0]), .I5(Q[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFF00FFFF00F9FF)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4 (.I0(cnt_init_mr_r[0]), .I1(cnt_init_mr_r[1]), .I2(dqs_found_done_r_reg_0), .I3(Q[1]), .I4(\init_state_r_reg_n_0_[3] ), .I5(Q[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 )); LUT6 #( .INIT(64'h3030303034303030)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5 (.I0(reg_ctrl_cnt_r_reg__0[0]), .I1(Q[3]), .I2(Q[4]), .I3(reg_ctrl_cnt_r_reg__0[2]), .I4(reg_ctrl_cnt_r_reg__0[1]), .I5(reg_ctrl_cnt_r_reg__0[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair495" *) LUT5 #( .INIT(32'h00010000)) \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ), .I3(Q[3]), .I4(Q[1]), .O(bank_w[1])); LUT6 #( .INIT(64'hAA55FFFFFFFFFF54)) \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(dqs_found_done_r_reg_0), .I2(cnt_init_mr_r[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair540" *) LUT4 #( .INIT(16'h4000)) \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[3]), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r), .I3(reg_ctrl_cnt_r_reg__0[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (.C(CLK), .CE(1'b1), .D(bank_w[0]), .Q(phy_bank[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] (.C(CLK), .CE(1'b1), .D(bank_w[1]), .Q(phy_bank[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ), .Q(phy_bank[11]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair593" *) LUT2 #( .INIT(4'hE)) \gen_reset_obuf.u_reset_obuf_i_1 (.I0(init_calib_complete_reg_rep__14), .I1(phy_reset_n), .O(mux_reset_n)); FDRE #( .INIT(1'b0)) \gen_rnk[0].mr1_r_reg[0][1] (.C(CLK), .CE(1'b1), .D(1'b1), .Q(\gen_rnk[0].mr1_r_reg[0]_196 ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) init_calib_complete_reg (.C(CLK), .CE(1'b1), .D(init_complete_r2), .Q(calib_complete), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) init_complete_r1_reg (.C(CLK), .CE(1'b1), .D(init_complete_r1_reg_0), .Q(init_complete_r1), .R(rstdiv0_sync_r1_reg_rep__11)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) init_complete_r1_timing_reg (.C(CLK), .CE(1'b1), .D(init_complete_r_timing), .Q(init_complete_r1_timing), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) init_complete_r2_reg (.C(CLK), .CE(1'b1), .D(init_complete_r1), .Q(init_complete_r2), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) init_complete_r_reg (.C(CLK), .CE(1'b1), .D(\init_state_r_reg[6]_0 ), .Q(init_complete_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) init_complete_r_timing_reg (.C(CLK), .CE(1'b1), .D(\init_state_r_reg[6]_1 ), .Q(init_complete_r_timing), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[0] (.C(CLK), .CE(1'b1), .D(Q[0]), .Q(init_state_r1[0]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[1] (.C(CLK), .CE(1'b1), .D(Q[1]), .Q(init_state_r1[1]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[2] (.C(CLK), .CE(1'b1), .D(Q[2]), .Q(init_state_r1[2]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\init_state_r_reg_n_0_[3] ), .Q(init_state_r1[3]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[4] (.C(CLK), .CE(1'b1), .D(Q[3]), .Q(init_state_r1[4]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[5] (.C(CLK), .CE(1'b1), .D(Q[4]), .Q(init_state_r1[5]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \init_state_r1_reg[6] (.C(CLK), .CE(1'b1), .D(Q[5]), .Q(init_state_r1[6]), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'hAAAAAAAAEEEFFFFF)) \init_state_r[0]_i_1 (.I0(\init_state_r[0]_i_2_n_0 ), .I1(\init_state_r[0]_i_3_n_0 ), .I2(oclk_calib_resume_level_reg_0), .I3(\init_state_r[0]_i_5_n_0 ), .I4(\init_state_r[0]_i_6_n_0 ), .I5(\init_state_r[0]_i_7_n_0 ), .O(\init_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFF000000FFFF1103)) \init_state_r[0]_i_10 (.I0(\init_state_r[0]_i_26_n_0 ), .I1(prech_pending_r_reg_0), .I2(\init_state_r[0]_i_27_n_0 ), .I3(Q[0]), .I4(Q[1]), .I5(prbs_rdlvl_done_pulse0), .O(\init_state_r[0]_i_10_n_0 )); LUT6 #( .INIT(64'hEFEFEFEFFFEFEFEF)) \init_state_r[0]_i_11 (.I0(\init_state_r[0]_i_28_n_0 ), .I1(\init_state_r[0]_i_29_n_0 ), .I2(Q[3]), .I3(\init_state_r[0]_i_30_n_0 ), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(\init_state_r[0]_i_31_n_0 ), .O(\init_state_r[0]_i_11_n_0 )); LUT6 #( .INIT(64'hDDDFDDDDDDDDDDDD)) \init_state_r[0]_i_13 (.I0(Q[3]), .I1(\init_state_r_reg[5]_0 ), .I2(\init_state_r[4]_i_5_n_0 ), .I3(Q[0]), .I4(cnt_cmd_done_r), .I5(\init_state_r[0]_i_33_n_0 ), .O(\init_state_r[0]_i_13_n_0 )); LUT5 #( .INIT(32'hAAAABBAB)) \init_state_r[0]_i_14 (.I0(Q[1]), .I1(\init_state_r[0]_i_34_n_0 ), .I2(rdlvl_stg1_done_int_reg), .I3(rdlvl_stg1_done_r1), .I4(rdlvl_stg1_rank_done), .O(\init_state_r[0]_i_14_n_0 )); LUT6 #( .INIT(64'h0000FF00FF00FE00)) \init_state_r[0]_i_15 (.I0(prech_pending_r_reg_0), .I1(pi_dqs_found_rank_done), .I2(dqs_found_done_r_reg), .I3(Q[1]), .I4(cnt_cmd_done_r), .I5(Q[0]), .O(\init_state_r[0]_i_15_n_0 )); LUT6 #( .INIT(64'h0000000000F0FEFE)) \init_state_r[0]_i_16 (.I0(prbs_rdlvl_done_reg_rep_2), .I1(wrlvl_final_mux_reg), .I2(cnt_init_af_done_r), .I3(mem_init_done_r), .I4(oclkdelay_calib_done_r_reg_5), .I5(wrlvl_byte_redo_reg_0), .O(\init_state_r[0]_i_16_n_0 )); LUT6 #( .INIT(64'h1505155515001550)) \init_state_r[0]_i_17 (.I0(oclk_calib_resume_level_reg_0), .I1(cnt_cmd_done_r), .I2(Q[0]), .I3(Q[1]), .I4(cnt_txpr_done_r), .I5(delay_done_r4_reg), .O(\init_state_r[0]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDF005F00)) \init_state_r[0]_i_18 (.I0(Q[0]), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(\init_state_r_reg[1]_0 ), .I4(wrlvl_done_r1), .I5(\init_state_r[0]_i_40_n_0 ), .O(\init_state_r[0]_i_18_n_0 )); LUT6 #( .INIT(64'hAEBBBFBBAABBBFBB)) \init_state_r[0]_i_19 (.I0(\init_state_r[0]_i_41_n_0 ), .I1(Q[1]), .I2(reset_rd_addr_r1), .I3(Q[0]), .I4(cnt_cmd_done_r), .I5(rdlvl_stg1_done_r1), .O(\init_state_r[0]_i_19_n_0 )); LUT6 #( .INIT(64'hABABABABAAABAAAA)) \init_state_r[0]_i_2 (.I0(\init_state_r[0]_i_8_n_0 ), .I1(\init_state_r[5]_i_26_n_0 ), .I2(\init_state_r[0]_i_9_n_0 ), .I3(\init_state_r[0]_i_10_n_0 ), .I4(\init_state_r_reg[1]_0 ), .I5(\init_state_r[0]_i_11_n_0 ), .O(\init_state_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair483" *) LUT5 #( .INIT(32'hFFFDDDDD)) \init_state_r[0]_i_20 (.I0(Q[1]), .I1(Q[0]), .I2(rdlvl_stg1_done_r1), .I3(complex_sample_cnt_inc_i_2_n_0), .I4(\init_state_r[5]_i_32_n_0 ), .O(\init_state_r[0]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFF133)) \init_state_r[0]_i_21 (.I0(\init_state_r[6]_i_22_n_0 ), .I1(write_request_r_reg), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\init_state_r[0]_i_21_n_0 )); LUT6 #( .INIT(64'hFFBFAFBFAAAAAAAA)) \init_state_r[0]_i_22 (.I0(oclk_calib_resume_level_reg_0), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(burst_addr_r_reg_0), .I5(\init_state_r[0]_i_42_n_0 ), .O(\init_state_r[0]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEAEAEEEA)) \init_state_r[0]_i_23 (.I0(\init_state_r[0]_i_43_n_0 ), .I1(\init_state_r_reg[1]_0 ), .I2(\init_state_r_reg[1]_1 ), .I3(cnt_cmd_done_r), .I4(Q[0]), .I5(\init_state_r[4]_i_28_n_0 ), .O(\init_state_r[0]_i_23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair574" *) LUT3 #( .INIT(8'h10)) \init_state_r[0]_i_24 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .O(\init_state_r[0]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair537" *) LUT4 #( .INIT(16'h0010)) \init_state_r[0]_i_25 (.I0(\wrcal_reads_reg_n_0_[4] ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(\wrcal_reads_reg_n_0_[0] ), .I3(\init_state_r[0]_i_45_n_0 ), .O(\init_state_r[0]_i_25_n_0 )); LUT6 #( .INIT(64'h0888888888888888)) \init_state_r[0]_i_26 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(Q[0]), .I2(complex_wait_cnt_reg__0[0]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[2]), .I5(complex_wait_cnt_reg__0[3]), .O(\init_state_r[0]_i_26_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \init_state_r[0]_i_27 (.I0(complex_num_reads_dec_reg__0[1]), .I1(complex_num_reads_dec_reg__0[0]), .I2(prbs_rdlvl_done_reg_rep), .I3(complex_row0_rd_done), .I4(complex_num_reads_dec_reg__0[3]), .I5(complex_num_reads_dec_reg__0[2]), .O(\init_state_r[0]_i_27_n_0 )); LUT6 #( .INIT(64'h0101010101014501)) \init_state_r[0]_i_28 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(Q[1]), .I2(\init_state_r[0]_i_46_n_0 ), .I3(prbs_rdlvl_done_reg_rep_0), .I4(Q[0]), .I5(complex_oclk_calib_resume), .O(\init_state_r[0]_i_28_n_0 )); LUT6 #( .INIT(64'h0000000000F0EFE0)) \init_state_r[0]_i_29 (.I0(\init_state_r[6]_i_17_n_0 ), .I1(oclkdelay_center_calib_start_r_reg_0), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(Q[0]), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[0]_i_29_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF000E0000)) \init_state_r[0]_i_3 (.I0(\init_state_r[2]_i_12_n_0 ), .I1(wrcal_sanity_chk_done_reg), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\init_state_r[0]_i_13_n_0 ), .O(\init_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDFDFDFDD)) \init_state_r[0]_i_30 (.I0(prbs_gen_oclk_clk_en_i_8_n_0), .I1(\init_state_r[3]_i_23_n_0 ), .I2(complex_oclkdelay_calib_start_r2), .I3(prbs_rdlvl_done_reg), .I4(prbs_last_byte_done_r), .I5(\init_state_r[4]_i_39_n_0 ), .O(\init_state_r[0]_i_30_n_0 )); LUT6 #( .INIT(64'h0004000400000004)) \init_state_r[0]_i_31 (.I0(oclkdelay_center_calib_start_r_reg), .I1(prbs_gen_oclk_clk_en_i_8_n_0), .I2(prech_pending_r_reg_0), .I3(prbs_rdlvl_start_i_2_n_0), .I4(complex_row1_wr_done), .I5(\one_rank.stg1_wr_done_reg_0 ), .O(\init_state_r[0]_i_31_n_0 )); (* SOFT_HLUTNM = "soft_lutpair559" *) LUT4 #( .INIT(16'hFFEF)) \init_state_r[0]_i_33 (.I0(reg_ctrl_cnt_r_reg__0[1]), .I1(reg_ctrl_cnt_r_reg__0[0]), .I2(reg_ctrl_cnt_r_reg__0[3]), .I3(reg_ctrl_cnt_r_reg__0[2]), .O(\init_state_r[0]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair541" *) LUT4 #( .INIT(16'hFFAE)) \init_state_r[0]_i_34 (.I0(Q[0]), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_rdlvl_done_r1), .I3(prech_pending_r_reg_0), .O(\init_state_r[0]_i_34_n_0 )); LUT2 #( .INIT(4'hE)) \init_state_r[0]_i_4 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .O(oclk_calib_resume_level_reg_0)); LUT6 #( .INIT(64'hBAFFAAAABFFFAAAA)) \init_state_r[0]_i_40 (.I0(Q[3]), .I1(wrlvl_rank_done_r7), .I2(Q[1]), .I3(Q[0]), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(cnt_dllk_zqinit_done_r), .O(\init_state_r[0]_i_40_n_0 )); LUT6 #( .INIT(64'h0000400044444444)) \init_state_r[0]_i_41 (.I0(Q[1]), .I1(pi_calib_done), .I2(\init_state_r[0]_i_51_n_0 ), .I3(wrcal_done_reg_10), .I4(rdlvl_stg1_done_int_reg_4), .I5(dqs_found_done_r_reg), .O(\init_state_r[0]_i_41_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAABABB)) \init_state_r[0]_i_42 (.I0(\init_state_r[1]_i_20_n_0 ), .I1(Q[0]), .I2(wrcal_prech_req), .I3(cnt_cmd_done_r), .I4(wrcal_done_reg_10), .I5(prech_pending_r_reg_0), .O(\init_state_r[0]_i_42_n_0 )); LUT6 #( .INIT(64'h000000000000F0EF)) \init_state_r[0]_i_43 (.I0(\init_state_r[2]_i_36_n_0 ), .I1(cnt_cmd_done_r_reg_1), .I2(Q[1]), .I3(Q[0]), .I4(\init_state_r[4]_i_5_n_0 ), .I5(\init_state_r[5]_i_57_n_0 ), .O(\init_state_r[0]_i_43_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \init_state_r[0]_i_45 (.I0(\wrcal_reads_reg_n_0_[3] ), .I1(\wrcal_reads_reg_n_0_[1] ), .I2(\wrcal_reads_reg_n_0_[7] ), .I3(Q[0]), .I4(\wrcal_reads_reg_n_0_[2] ), .I5(\wrcal_reads_reg_n_0_[5] ), .O(\init_state_r[0]_i_45_n_0 )); LUT6 #( .INIT(64'h4500FFFF4545FFFF)) \init_state_r[0]_i_46 (.I0(prech_pending_r_reg_0), .I1(complex_oclkdelay_calib_done_r1), .I2(prbs_rdlvl_done_reg), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(Q[0]), .I5(complex_sample_cnt_inc_i_2_n_0), .O(\init_state_r[0]_i_46_n_0 )); LUT6 #( .INIT(64'h00000000FFFF1000)) \init_state_r[0]_i_5 (.I0(num_reads[1]), .I1(num_reads[2]), .I2(num_reads[0]), .I3(Q[0]), .I4(\init_state_r[0]_i_14_n_0 ), .I5(\init_state_r[0]_i_15_n_0 ), .O(\init_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'h0155455501550055)) \init_state_r[0]_i_50 (.I0(\init_state_r_reg[2]_0 ), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_last_byte_done_r), .I3(dqs_found_done_r_reg), .I4(rdlvl_stg1_done_int_reg), .I5(wrcal_done_reg_10), .O(\init_state_r_reg[0]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFC44)) \init_state_r[0]_i_51 (.I0(rdlvl_stg1_start_int), .I1(prbs_rdlvl_done_reg_rep), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(rdlvl_stg1_done_int_reg), .I4(rdlvl_last_byte_done), .I5(prbs_last_byte_done), .O(\init_state_r[0]_i_51_n_0 )); LUT6 #( .INIT(64'hEFAFFFBFFFFFFFFF)) \init_state_r[0]_i_6 (.I0(Q[0]), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(\init_state_r[0]_i_16_n_0 ), .I4(ddr2_pre_flag_r_reg_0), .I5(\init_state_r_reg[1]_0 ), .O(\init_state_r[0]_i_6_n_0 )); LUT6 #( .INIT(64'hABAAABABABAAABAA)) \init_state_r[0]_i_7 (.I0(\init_state_r[5]_i_2_n_0 ), .I1(\init_state_r[0]_i_17_n_0 ), .I2(\init_state_r[0]_i_18_n_0 ), .I3(\init_state_r[4]_i_5_n_0 ), .I4(\init_state_r[0]_i_19_n_0 ), .I5(\init_state_r[0]_i_20_n_0 ), .O(\init_state_r[0]_i_7_n_0 )); LUT6 #( .INIT(64'h88008A008A008A00)) \init_state_r[0]_i_8 (.I0(\init_state_r[0]_i_21_n_0 ), .I1(Q[0]), .I2(Q[2]), .I3(Q[5]), .I4(\init_state_r[5]_i_36_n_0 ), .I5(Q[1]), .O(\init_state_r[0]_i_8_n_0 )); LUT6 #( .INIT(64'h2222222200202222)) \init_state_r[0]_i_9 (.I0(\init_state_r[0]_i_22_n_0 ), .I1(\init_state_r[0]_i_23_n_0 ), .I2(wrcal_done_reg_9), .I3(Q[0]), .I4(\init_state_r[0]_i_24_n_0 ), .I5(\init_state_r[0]_i_25_n_0 ), .O(\init_state_r[0]_i_9_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAEEFE)) \init_state_r[1]_i_1 (.I0(\init_state_r[1]_i_2_n_0 ), .I1(\init_state_r[1]_i_3_n_0 ), .I2(\init_state_r_reg[1]_0 ), .I3(\init_state_r[1]_i_5_n_0 ), .I4(\init_state_r[5]_i_2_n_0 ), .I5(\init_state_r[1]_i_6_n_0 ), .O(\init_state_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair501" *) LUT5 #( .INIT(32'hFFFBAAAA)) \init_state_r[1]_i_10 (.I0(\init_state_r[0]_i_14_n_0 ), .I1(num_reads[0]), .I2(num_reads[2]), .I3(num_reads[1]), .I4(Q[0]), .O(\init_state_r[1]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair523" *) LUT5 #( .INIT(32'h22222220)) \init_state_r[1]_i_11 (.I0(Q[1]), .I1(Q[0]), .I2(dqs_found_done_r_reg), .I3(pi_dqs_found_rank_done), .I4(prech_pending_r_reg_0), .O(\init_state_r[1]_i_11_n_0 )); LUT6 #( .INIT(64'hBBBBBBFFBBFFBBFB)) \init_state_r[1]_i_12 (.I0(\init_state_r[1]_i_25_n_0 ), .I1(Q[3]), .I2(cnt_cmd_done_r), .I3(\init_state_r[4]_i_5_n_0 ), .I4(Q[0]), .I5(Q[1]), .O(\init_state_r[1]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0B0B080B)) \init_state_r[1]_i_13 (.I0(wrlvl_byte_redo_reg), .I1(mpr_rdlvl_done_r_reg_2), .I2(\init_state_r[1]_i_26_n_0 ), .I3(oclkdelay_calib_done_r_reg_2), .I4(\init_state_r[1]_i_27_n_0 ), .I5(\init_state_r[1]_i_28_n_0 ), .O(\init_state_r[1]_i_13_n_0 )); LUT6 #( .INIT(64'hFFE0FFE0FFE0FFFF)) \init_state_r[1]_i_15 (.I0(dqs_found_done_r_reg_2), .I1(prbs_last_byte_done_reg), .I2(\init_state_r[1]_i_33_n_0 ), .I3(\init_state_r[1]_i_34_n_0 ), .I4(Q[0]), .I5(\init_state_r[5]_i_32_n_0 ), .O(\init_state_r[1]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair563" *) LUT4 #( .INIT(16'h0020)) \init_state_r[1]_i_16 (.I0(Q[0]), .I1(Q[1]), .I2(cnt_dllk_zqinit_done_r), .I3(mem_init_done_r), .O(\init_state_r[1]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF7070FF70)) \init_state_r[1]_i_17 (.I0(Q[0]), .I1(wrlvl_rank_done_r7), .I2(\init_state_r[1]_i_35_n_0 ), .I3(\init_state_r_reg[1]_0 ), .I4(\init_state_r[1]_i_36_n_0 ), .I5(Q[3]), .O(\init_state_r[1]_i_17_n_0 )); LUT6 #( .INIT(64'hE0000F0FE000FFFF)) \init_state_r[1]_i_18 (.I0(cnt_init_mr_done_r), .I1(dqs_found_done_r_reg_0), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(cnt_txpr_done_r), .O(\init_state_r[1]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair530" *) LUT5 #( .INIT(32'hF2F2F2FF)) \init_state_r[1]_i_19 (.I0(cnt_cmd_done_r), .I1(wrcal_prech_req), .I2(Q[0]), .I3(prech_pending_r_reg_0), .I4(wrcal_done_reg_10), .O(\init_state_r[1]_i_19_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF0200)) \init_state_r[1]_i_2 (.I0(Q[4]), .I1(Q[5]), .I2(\init_state_r[1]_i_7_n_0 ), .I3(\init_state_r[1]_i_8_n_0 ), .I4(\init_state_r[1]_i_9_n_0 ), .I5(\init_state_r[5]_i_19_n_0 ), .O(\init_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAABAAAAAAAAAA)) \init_state_r[1]_i_20 (.I0(Q[1]), .I1(wrcal_wr_cnt_reg__0[3]), .I2(wrcal_wr_cnt_reg__0[2]), .I3(wrcal_wr_cnt_reg__0[0]), .I4(wrcal_wr_cnt_reg__0[1]), .I5(Q[0]), .O(\init_state_r[1]_i_20_n_0 )); LUT6 #( .INIT(64'hFEFEFEFEFFFEFEFE)) \init_state_r[1]_i_21 (.I0(\init_state_r[1]_i_37_n_0 ), .I1(Q[3]), .I2(mpr_rdlvl_done_r_reg_0), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\init_state_r[5]_i_57_n_0 ), .O(\init_state_r[1]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair526" *) LUT5 #( .INIT(32'hEFEEAAAA)) \init_state_r[1]_i_22 (.I0(Q[1]), .I1(prech_pending_r_reg_0), .I2(complex_oclkdelay_calib_done_r1), .I3(prbs_rdlvl_done_reg_rep), .I4(Q[0]), .O(\init_state_r[1]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFAABA)) \init_state_r[1]_i_23 (.I0(\init_state_r[1]_i_39_n_0 ), .I1(Q[0]), .I2(\init_state_r_reg[1]_0 ), .I3(\init_state_r[1]_i_40_n_0 ), .I4(\init_state_r[1]_i_41_n_0 ), .I5(\init_state_r[1]_i_42_n_0 ), .O(\init_state_r[1]_i_23_n_0 )); LUT6 #( .INIT(64'hCCCCCC88CCCCCC08)) \init_state_r[1]_i_24 (.I0(\init_state_r[5]_i_13_n_0 ), .I1(\init_state_r[1]_i_43_n_0 ), .I2(\init_state_r[0]_i_27_n_0 ), .I3(prech_pending_r_reg_0), .I4(prbs_rdlvl_done_pulse0), .I5(Q[0]), .O(\init_state_r[1]_i_24_n_0 )); LUT6 #( .INIT(64'h2820202028202820)) \init_state_r[1]_i_25 (.I0(\wrcal_reads[7]_i_5_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(wrcal_sanity_chk_done_reg_0), .I5(rdlvl_stg1_done_int_reg_2), .O(\init_state_r[1]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair490" *) LUT5 #( .INIT(32'h0020FFFF)) \init_state_r[1]_i_26 (.I0(prbs_last_byte_done_r), .I1(prbs_rdlvl_done_reg_rep), .I2(dqs_found_done_r_reg), .I3(\init_state_r_reg[2]_0 ), .I4(mem_init_done_r), .O(\init_state_r[1]_i_26_n_0 )); LUT6 #( .INIT(64'h8A8A8A88AAAAAAAA)) \init_state_r[1]_i_27 (.I0(wrlvl_final_mux_reg_0), .I1(wrlvl_done_r1), .I2(prbs_rdlvl_done_reg_rep), .I3(rdlvl_stg1_done_int_reg), .I4(prbs_last_byte_done_r), .I5(prbs_rdlvl_done_reg_rep_3), .O(\init_state_r[1]_i_27_n_0 )); LUT6 #( .INIT(64'h000000F200000000)) \init_state_r[1]_i_28 (.I0(wrcal_done_reg_10), .I1(\init_state_r[1]_i_46_n_0 ), .I2(prbs_rdlvl_done_reg_rep_1), .I3(mem_init_done_r), .I4(cnt_init_af_done_r), .I5(mpr_rdlvl_done_r_reg_1), .O(\init_state_r[1]_i_28_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000FF5D)) \init_state_r[1]_i_3 (.I0(\init_state_r[1]_i_10_n_0 ), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(\init_state_r[1]_i_11_n_0 ), .I4(oclk_calib_resume_level_reg_0), .I5(\init_state_r[1]_i_12_n_0 ), .O(\init_state_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair578" *) LUT2 #( .INIT(4'h2)) \init_state_r[1]_i_33 (.I0(pi_calib_done), .I1(Q[1]), .O(\init_state_r[1]_i_33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF10000FFF)) \init_state_r[1]_i_34 (.I0(rdlvl_stg1_done_r1), .I1(reset_rd_addr_r1), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(\init_state_r[4]_i_5_n_0 ), .O(\init_state_r[1]_i_34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair567" *) LUT3 #( .INIT(8'h08)) \init_state_r[1]_i_35 (.I0(Q[1]), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[1]_i_35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair563" *) LUT3 #( .INIT(8'h07)) \init_state_r[1]_i_36 (.I0(Q[0]), .I1(cnt_cmd_done_r), .I2(Q[1]), .O(\init_state_r[1]_i_36_n_0 )); LUT6 #( .INIT(64'h4444444044404440)) \init_state_r[1]_i_37 (.I0(Q[0]), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(\init_state_r[5]_i_49_n_0 ), .I3(Q[1]), .I4(wrcal_final_chk), .I5(wrcal_resume_r), .O(\init_state_r[1]_i_37_n_0 )); LUT6 #( .INIT(64'h1FFF0000FFFFFFFF)) \init_state_r[1]_i_39 (.I0(\one_rank.stg1_wr_done_reg_0 ), .I1(oclkdelay_center_calib_start_r_reg), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(\init_state_r[2]_i_33_n_0 ), .I4(\init_state_r[1]_i_35_n_0 ), .I5(Q[3]), .O(\init_state_r[1]_i_39_n_0 )); (* SOFT_HLUTNM = "soft_lutpair538" *) LUT2 #( .INIT(4'h2)) \init_state_r[1]_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .O(\init_state_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair548" *) LUT4 #( .INIT(16'hB0BB)) \init_state_r[1]_i_40 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[1]), .O(\init_state_r[1]_i_40_n_0 )); LUT6 #( .INIT(64'h1515100015155444)) \init_state_r[1]_i_41 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(oclkdelay_int_ref_req_reg_0), .I4(Q[0]), .I5(\init_state_r[1]_i_47_n_0 ), .O(\init_state_r[1]_i_41_n_0 )); LUT6 #( .INIT(64'h0000000088880080)) \init_state_r[1]_i_42 (.I0(Q[0]), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(\init_state_r[1]_i_48_n_0 ), .I4(prbs_rdlvl_done_pulse0), .I5(Q[1]), .O(\init_state_r[1]_i_42_n_0 )); (* SOFT_HLUTNM = "soft_lutpair567" *) LUT3 #( .INIT(8'h04)) \init_state_r[1]_i_43 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .O(\init_state_r[1]_i_43_n_0 )); LUT2 #( .INIT(4'h2)) \init_state_r[1]_i_46 (.I0(wrlvl_final_mux), .I1(wrlvl_done_r1), .O(\init_state_r[1]_i_46_n_0 )); LUT6 #( .INIT(64'h0000000000010000)) \init_state_r[1]_i_47 (.I0(wrlvl_final_mux), .I1(oclkdelay_int_ref_req_reg_0), .I2(prech_pending_r_reg_0), .I3(oclkdelay_calib_done_r_reg_2), .I4(oclkdelay_center_calib_start_r_reg), .I5(\init_state_r[6]_i_17_n_0 ), .O(\init_state_r[1]_i_47_n_0 )); (* SOFT_HLUTNM = "soft_lutpair507" *) LUT5 #( .INIT(32'h0000CC40)) \init_state_r[1]_i_48 (.I0(complex_oclkdelay_calib_start_int), .I1(done_r_reg), .I2(prbs_last_byte_done_r), .I3(prbs_rdlvl_done_reg_rep), .I4(complex_oclkdelay_calib_start_r2), .O(\init_state_r[1]_i_48_n_0 )); LUT6 #( .INIT(64'hFFFF00002222F0FF)) \init_state_r[1]_i_5 (.I0(\init_state_r[1]_i_13_n_0 ), .I1(oclkdelay_calib_done_r_reg_4), .I2(ddr2_pre_flag_r_reg_0), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(Q[0]), .O(\init_state_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h0000A2AA0000A0A8)) \init_state_r[1]_i_6 (.I0(\init_state_r[1]_i_15_n_0 ), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(\init_state_r[1]_i_16_n_0 ), .I4(\init_state_r[1]_i_17_n_0 ), .I5(\init_state_r[1]_i_18_n_0 ), .O(\init_state_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000BABAFFBA)) \init_state_r[1]_i_7 (.I0(oclk_calib_resume_level_reg_0), .I1(prbs_rdlvl_start_i_2_n_0), .I2(burst_addr_r_reg_0), .I3(\init_state_r[1]_i_19_n_0 ), .I4(\init_state_r[1]_i_20_n_0 ), .I5(\init_state_r[1]_i_21_n_0 ), .O(\init_state_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF00FD)) \init_state_r[1]_i_8 (.I0(\init_state_r[5]_i_42_n_0 ), .I1(\init_state_r[1]_i_22_n_0 ), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(\init_state_r[4]_i_5_n_0 ), .I4(\init_state_r[1]_i_23_n_0 ), .I5(\init_state_r[1]_i_24_n_0 ), .O(\init_state_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'hFF80FFFF80808080)) \init_state_r[1]_i_9 (.I0(Q[5]), .I1(Q[2]), .I2(Q[1]), .I3(prech_pending_r_reg_0), .I4(oclkdelay_calib_done_r_reg_2), .I5(\init_state_r[6]_i_12_n_0 ), .O(\init_state_r[1]_i_9_n_0 )); LUT6 #( .INIT(64'hAEAEAEAAAEAEAEAE)) \init_state_r[2]_i_1 (.I0(\init_state_r[2]_i_2_n_0 ), .I1(\init_state_r[2]_i_3_n_0 ), .I2(\init_state_r[5]_i_2_n_0 ), .I3(\init_state_r[2]_i_4_n_0 ), .I4(\init_state_r[2]_i_5_n_0 ), .I5(\init_state_r[2]_i_6_n_0 ), .O(\init_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAA0002)) \init_state_r[2]_i_10 (.I0(\init_state_r[2]_i_25_n_0 ), .I1(dqs_found_done_r_reg_0), .I2(cnt_init_mr_done_r), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\init_state_r[2]_i_26_n_0 ), .O(\init_state_r[2]_i_10_n_0 )); LUT6 #( .INIT(64'hF2FF000000000000)) \init_state_r[2]_i_11 (.I0(pi_calib_done), .I1(wrcal_done_reg_11), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(\init_state_r[2]_i_27_n_0 ), .I5(\init_state_r[0]_i_20_n_0 ), .O(\init_state_r[2]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair530" *) LUT2 #( .INIT(4'h7)) \init_state_r[2]_i_12 (.I0(Q[0]), .I1(cnt_cmd_done_r), .O(\init_state_r[2]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair494" *) LUT5 #( .INIT(32'h45454500)) \init_state_r[2]_i_14 (.I0(\init_state_r_reg[2]_0 ), .I1(mem_init_done_r), .I2(cnt_init_af_done_r), .I3(prbs_rdlvl_done_reg_rep_1), .I4(\init_state_r[4]_i_26_n_0 ), .O(\init_state_r[2]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair503" *) LUT2 #( .INIT(4'h7)) \init_state_r[2]_i_16 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .O(\init_state_r[2]_i_16_n_0 )); LUT6 #( .INIT(64'hAAAABFFFAAAABBBB)) \init_state_r[2]_i_17 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[2]), .I5(\init_state_r[5]_i_56_n_0 ), .O(\init_state_r[2]_i_17_n_0 )); LUT6 #( .INIT(64'h80AA808080AA80AA)) \init_state_r[2]_i_18 (.I0(Q[2]), .I1(prbs_rdlvl_done_pulse0), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(\init_state_r[6]_i_23_n_0 ), .I4(\init_state_r[2]_i_32_n_0 ), .I5(\init_state_r[2]_i_33_n_0 ), .O(\init_state_r[2]_i_18_n_0 )); LUT6 #( .INIT(64'hF200FFFFF200F200)) \init_state_r[2]_i_2 (.I0(complex_pi_incdec_done), .I1(prbs_rdlvl_start_i_2_n_0), .I2(\init_state_r[2]_i_7_n_0 ), .I3(Q[5]), .I4(\init_state_r[2]_i_8_n_0 ), .I5(\init_state_r[2]_i_9_n_0 ), .O(\init_state_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'h10111010FFFFFFFF)) \init_state_r[2]_i_20 (.I0(\init_state_r[2]_i_16_n_0 ), .I1(Q[2]), .I2(complex_oclkdelay_calib_start_int_reg_0), .I3(prbs_rdlvl_done_pulse0), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(Q[3]), .O(\init_state_r[2]_i_20_n_0 )); LUT6 #( .INIT(64'hF000F2F200000000)) \init_state_r[2]_i_21 (.I0(pi_phase_locked_all_r3), .I1(pi_phase_locked_all_r4), .I2(Q[0]), .I3(\init_state_r[2]_i_34_n_0 ), .I4(\init_state_r_reg_n_0_[3] ), .I5(\init_state_r[2]_i_35_n_0 ), .O(\init_state_r[2]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFF010FFFFFFFFF)) \init_state_r[2]_i_22 (.I0(\init_state_r_reg_n_0_[3] ), .I1(burst_addr_r_reg_0), .I2(Q[2]), .I3(Q[1]), .I4(Q[5]), .I5(Q[4]), .O(\init_state_r[2]_i_22_n_0 )); LUT6 #( .INIT(64'hFFBFBBBBAAAAAAAA)) \init_state_r[2]_i_24 (.I0(Q[0]), .I1(\init_state_r_reg_n_0_[3] ), .I2(\init_state_r[2]_i_36_n_0 ), .I3(cnt_cmd_done_r_reg_1), .I4(Q[1]), .I5(Q[2]), .O(\init_state_r[2]_i_24_n_0 )); LUT6 #( .INIT(64'hFF0F4F4F0F0F0F0F)) \init_state_r[2]_i_25 (.I0(mem_init_done_r), .I1(cnt_dllk_zqinit_done_r), .I2(Q[2]), .I3(wrlvl_rank_done_r7), .I4(Q[1]), .I5(Q[0]), .O(\init_state_r[2]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair545" *) LUT3 #( .INIT(8'h7F)) \init_state_r[2]_i_26 (.I0(cnt_cmd_done_r), .I1(Q[0]), .I2(Q[1]), .O(\init_state_r[2]_i_26_n_0 )); LUT6 #( .INIT(64'hEC00FFF0ECF0FFF0)) \init_state_r[2]_i_27 (.I0(reset_rd_addr_r1), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(complex_sample_cnt_inc_i_2_n_0), .O(\init_state_r[2]_i_27_n_0 )); LUT6 #( .INIT(64'hF0FFF1F1F3F3F3F3)) \init_state_r[2]_i_3 (.I0(wrlvl_done_r1), .I1(\init_state_r[2]_i_10_n_0 ), .I2(Q[3]), .I3(\init_state_r[2]_i_11_n_0 ), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hAB00AB00AB00ABFF)) \init_state_r[2]_i_30 (.I0(\init_state_r[2]_i_37_n_0 ), .I1(wrlvl_done_r1), .I2(wrlvl_byte_redo), .I3(mem_init_done_r), .I4(wrcal_done_reg_10), .I5(cnt_init_af_done_r), .O(\init_state_r_reg[2]_1 )); LUT6 #( .INIT(64'h8000800080000000)) \init_state_r[2]_i_32 (.I0(complex_wait_cnt_reg__0[3]), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[1]), .I3(complex_wait_cnt_reg__0[0]), .I4(oclkdelay_center_calib_start_r_reg), .I5(\one_rank.stg1_wr_done_reg_0 ), .O(\init_state_r[2]_i_32_n_0 )); (* SOFT_HLUTNM = "soft_lutpair523" *) LUT2 #( .INIT(4'h2)) \init_state_r[2]_i_33 (.I0(Q[0]), .I1(prech_pending_r_reg_0), .O(\init_state_r[2]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair544" *) LUT4 #( .INIT(16'h0010)) \init_state_r[2]_i_34 (.I0(oclk_wr_cnt_reg__0[3]), .I1(oclk_wr_cnt_reg__0[1]), .I2(oclk_wr_cnt_reg__0[0]), .I3(oclk_wr_cnt_reg__0[2]), .O(\init_state_r[2]_i_34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair548" *) LUT2 #( .INIT(4'h8)) \init_state_r[2]_i_35 (.I0(Q[2]), .I1(Q[1]), .O(\init_state_r[2]_i_35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair531" *) LUT2 #( .INIT(4'hE)) \init_state_r[2]_i_36 (.I0(prech_pending_r_reg_0), .I1(oclkdelay_calib_done_r_reg_2), .O(\init_state_r[2]_i_36_n_0 )); (* SOFT_HLUTNM = "soft_lutpair571" *) LUT3 #( .INIT(8'hDF)) \init_state_r[2]_i_37 (.I0(prbs_last_byte_done_r), .I1(prbs_rdlvl_done_reg_rep), .I2(dqs_found_done_r_reg), .O(\init_state_r[2]_i_37_n_0 )); LUT6 #( .INIT(64'hEEFE000000000000)) \init_state_r[2]_i_4 (.I0(wrcal_sanity_chk_done_reg_0), .I1(\init_state_r[2]_i_12_n_0 ), .I2(ddr3_lm_done_r), .I3(rdlvl_stg1_done_int_reg_2), .I4(prbs_rdlvl_start_i_2_n_0), .I5(\wrcal_reads[7]_i_5_n_0 ), .O(\init_state_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'h5FF755555555D555)) \init_state_r[2]_i_5 (.I0(Q[3]), .I1(cnt_cmd_done_r), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF040F)) \init_state_r[2]_i_6 (.I0(\init_state_r[2]_i_14_n_0 ), .I1(cnt_init_af_done_r_reg_1), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[2]), .I5(\init_state_r[2]_i_16_n_0 ), .O(\init_state_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'hAAAEAAAAAAAAAAAA)) \init_state_r[2]_i_7 (.I0(Q[2]), .I1(oclkdelay_calib_done_r_reg_2), .I2(prech_pending_r_reg_0), .I3(Q[1]), .I4(Q[0]), .I5(\init_state_r[6]_i_22_n_0 ), .O(\init_state_r[2]_i_7_n_0 )); LUT6 #( .INIT(64'h000E000E0000000E)) \init_state_r[2]_i_8 (.I0(\init_state_r[2]_i_17_n_0 ), .I1(\init_state_r[2]_i_18_n_0 ), .I2(\init_state_r_reg[2]_2 ), .I3(\init_state_r[2]_i_20_n_0 ), .I4(\init_state_r[5]_i_42_n_0 ), .I5(\init_state_r[5]_i_41_n_0 ), .O(\init_state_r[2]_i_8_n_0 )); LUT6 #( .INIT(64'h11010000FFFFFFFF)) \init_state_r[2]_i_9 (.I0(\init_state_r[2]_i_21_n_0 ), .I1(\init_state_r[2]_i_22_n_0 ), .I2(\wrcal_reads[7]_i_6_n_0 ), .I3(wrcal_done_reg_9), .I4(\init_state_r[2]_i_24_n_0 ), .I5(complex_oclkdelay_calib_start_int_i_2_n_0), .O(\init_state_r[2]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair481" *) LUT1 #( .INIT(2'h1)) \init_state_r[3]_i_1 (.I0(\init_state_r[3]_i_2_n_0 ), .O(\init_state_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair562" *) LUT4 #( .INIT(16'h0111)) \init_state_r[3]_i_10 (.I0(Q[1]), .I1(Q[0]), .I2(ddr2_pre_flag_r_reg_0), .I3(cnt_cmd_done_r), .O(\init_state_r[3]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair576" *) LUT2 #( .INIT(4'h2)) \init_state_r[3]_i_11 (.I0(\init_state_r_reg_n_0_[3] ), .I1(cnt_cmd_done_r), .O(\init_state_r[3]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair529" *) LUT5 #( .INIT(32'hF3FF23FF)) \init_state_r[3]_i_13 (.I0(\init_state_r_reg_n_0_[3] ), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(reset_rd_addr_r1), .O(\init_state_r[3]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair491" *) LUT5 #( .INIT(32'hFEFFFFFF)) \init_state_r[3]_i_14 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .O(\init_state_r[3]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF4440)) \init_state_r[3]_i_15 (.I0(\wrcal_reads[7]_i_5_n_0 ), .I1(Q[5]), .I2(\init_state_r[3]_i_19_n_0 ), .I3(\init_state_r[3]_i_20_n_0 ), .I4(\init_state_r[3]_i_21_n_0 ), .I5(\init_state_r[3]_i_22_n_0 ), .O(\init_state_r[3]_i_15_n_0 )); LUT6 #( .INIT(64'h0202222202022202)) \init_state_r[3]_i_16 (.I0(\init_state_r[5]_i_41_n_0 ), .I1(\init_state_r_reg[2]_2 ), .I2(\init_state_r[5]_i_53_n_0 ), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(complex_oclkdelay_calib_start_int_reg_0), .I5(prbs_rdlvl_done_pulse0), .O(\init_state_r[3]_i_16_n_0 )); LUT6 #( .INIT(64'hFFDDFFFFF0DDFFFF)) \init_state_r[3]_i_17 (.I0(\init_state_r[3]_i_23_n_0 ), .I1(prbs_rdlvl_done_pulse0), .I2(prech_pending_r_reg_0), .I3(Q[1]), .I4(Q[0]), .I5(oclkdelay_center_calib_start_r_reg), .O(\init_state_r[3]_i_17_n_0 )); LUT6 #( .INIT(64'hCFFFAFCF00FF00CF)) \init_state_r[3]_i_18 (.I0(oclkdelay_center_calib_start_r_reg_0), .I1(cnt_cmd_done_r), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(Q[0]), .I5(\init_state_r[5]_i_56_n_0 ), .O(\init_state_r[3]_i_18_n_0 )); LUT6 #( .INIT(64'h0044000000440400)) \init_state_r[3]_i_19 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(write_request_r_reg), .I5(\init_state_r[6]_i_22_n_0 ), .O(\init_state_r[3]_i_19_n_0 )); LUT6 #( .INIT(64'h00FE00FE00FE0000)) \init_state_r[3]_i_2 (.I0(\init_state_r[3]_i_3_n_0 ), .I1(\init_state_r[3]_i_4_n_0 ), .I2(\init_state_r[3]_i_5_n_0 ), .I3(\init_state_r[3]_i_6_n_0 ), .I4(complex_oclkdelay_calib_start_int_i_2_n_0), .I5(\init_state_r[3]_i_7_n_0 ), .O(\init_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF08880800)) \init_state_r[3]_i_20 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(complex_pi_incdec_done), .I3(Q[0]), .I4(\init_state_r[5]_i_36_n_0 ), .I5(\init_state_r[2]_i_7_n_0 ), .O(\init_state_r[3]_i_20_n_0 )); LUT6 #( .INIT(64'h0000000011014444)) \init_state_r[3]_i_21 (.I0(rdlvl_stg1_start_int_i_2_n_0), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[1]), .I3(wrlvl_rank_done_r7), .I4(Q[2]), .I5(\init_state_r[3]_i_24_n_0 ), .O(\init_state_r[3]_i_21_n_0 )); LUT6 #( .INIT(64'h0000AFAF0000C000)) \init_state_r[3]_i_22 (.I0(\init_state_r[4]_i_27_n_0 ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(read_calib_i_2_n_0), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[3]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair507" *) LUT4 #( .INIT(16'h3B30)) \init_state_r[3]_i_23 (.I0(complex_oclkdelay_calib_start_int), .I1(done_r_reg), .I2(prbs_rdlvl_done_reg_rep), .I3(prbs_last_byte_done_r), .O(\init_state_r[3]_i_23_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF40434343)) \init_state_r[3]_i_24 (.I0(\init_state_r[2]_i_12_n_0 ), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(cnt_dllk_zqinit_done_r), .I4(mem_init_done_r), .I5(\init_state_r[3]_i_25_n_0 ), .O(\init_state_r[3]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair521" *) LUT2 #( .INIT(4'h2)) \init_state_r[3]_i_25 (.I0(Q[2]), .I1(Q[0]), .O(\init_state_r[3]_i_25_n_0 )); LUT6 #( .INIT(64'h08AAAAAA08AA08AA)) \init_state_r[3]_i_3 (.I0(\init_state_r[4]_i_11_n_0 ), .I1(cnt_init_af_done_r), .I2(mem_init_done_r), .I3(mpr_rdlvl_done_r_reg_1), .I4(\init_state_r[4]_i_26_n_0 ), .I5(dqs_found_done_r_reg_1), .O(\init_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDDDD00F0)) \init_state_r[3]_i_4 (.I0(\init_state_r[2]_i_16_n_0 ), .I1(\init_state_r[4]_i_21_n_0 ), .I2(\init_state_r[3]_i_10_n_0 ), .I3(\init_state_r[3]_i_11_n_0 ), .I4(Q[2]), .I5(rdlvl_start_pre_reg_0), .O(\init_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0155555505555555)) \init_state_r[3]_i_5 (.I0(\init_state_r_reg_n_0_[3] ), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(wrcal_sanity_chk_done_reg), .O(\init_state_r[3]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000FF08)) \init_state_r[3]_i_6 (.I0(wrcal_done_reg_11), .I1(pi_calib_done), .I2(Q[1]), .I3(\init_state_r[3]_i_13_n_0 ), .I4(\init_state_r[3]_i_14_n_0 ), .I5(\init_state_r[3]_i_15_n_0 ), .O(\init_state_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hAAAAAA2AAAA0AA20)) \init_state_r[3]_i_7 (.I0(\init_state_r[3]_i_16_n_0 ), .I1(prbs_gen_oclk_clk_en_i_8_n_0), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(\init_state_r[3]_i_17_n_0 ), .I5(\init_state_r[3]_i_18_n_0 ), .O(\init_state_r[3]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF55550051)) \init_state_r[4]_i_1 (.I0(\init_state_r[4]_i_2_n_0 ), .I1(\init_state_r[4]_i_3_n_0 ), .I2(\init_state_r[4]_i_4_n_0 ), .I3(\init_state_r[4]_i_5_n_0 ), .I4(\init_state_r[4]_i_6_n_0 ), .I5(\init_state_r[4]_i_7_n_0 ), .O(\init_state_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAA88A888888888)) \init_state_r[4]_i_10 (.I0(\init_state_r[4]_i_22_n_0 ), .I1(mem_init_done_r_reg_2), .I2(\init_state_r_reg[2]_0 ), .I3(rdlvl_stg1_done_int_reg_3), .I4(\init_state_r[4]_i_26_n_0 ), .I5(wrlvl_byte_redo_reg), .O(\init_state_r[4]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair562" *) LUT3 #( .INIT(8'h08)) \init_state_r[4]_i_11 (.I0(cnt_cmd_done_r), .I1(Q[1]), .I2(Q[0]), .O(\init_state_r[4]_i_11_n_0 )); LUT6 #( .INIT(64'h0001000DFFFFFFFF)) \init_state_r[4]_i_12 (.I0(Q[3]), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(ddr2_pre_flag_r_reg_0), .I5(\init_state_r_reg[1]_0 ), .O(\init_state_r[4]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair578" *) LUT3 #( .INIT(8'h8A)) \init_state_r[4]_i_13 (.I0(pi_calib_done), .I1(wrcal_done_reg_10), .I2(dqs_found_done_r_reg), .O(\init_state_r[4]_i_13_n_0 )); LUT6 #( .INIT(64'hFF540000FF5C000C)) \init_state_r[4]_i_14 (.I0(rdlvl_stg1_start_int), .I1(\one_rank.stg1_wr_done_reg_0 ), .I2(rdlvl_last_byte_done), .I3(rdlvl_stg1_done_int_reg), .I4(prbs_rdlvl_done_reg_rep), .I5(prbs_last_byte_done), .O(\init_state_r_reg[4]_0 )); LUT6 #( .INIT(64'h0080000000000000)) \init_state_r[4]_i_15 (.I0(Q[0]), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[2]), .I4(wrlvl_done_r1), .I5(cnt_cmd_done_r), .O(\init_state_r[4]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFF01FF01FF01)) \init_state_r[4]_i_16 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(\init_state_r[4]_i_5_n_0 ), .I2(\init_state_r[4]_i_27_n_0 ), .I3(\init_state_r[4]_i_28_n_0 ), .I4(\init_state_r[4]_i_29_n_0 ), .I5(\init_state_r[5]_i_49_n_0 ), .O(\init_state_r[4]_i_16_n_0 )); LUT6 #( .INIT(64'h00000000FF77F7F7)) \init_state_r[4]_i_17 (.I0(Q[3]), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(burst_addr_r_reg_0), .I4(Q[0]), .I5(\init_state_r[5]_i_51_n_0 ), .O(\init_state_r[4]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEAA)) \init_state_r[4]_i_18 (.I0(\init_state_r[4]_i_30_n_0 ), .I1(prech_pending_r_reg_0), .I2(\init_state_r[5]_i_13_n_0 ), .I3(\init_state_r_reg[1]_0 ), .I4(\init_state_r[4]_i_31_n_0 ), .I5(\init_state_r[4]_i_32_n_0 ), .O(\init_state_r[4]_i_18_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEA00)) \init_state_r[4]_i_19 (.I0(Q[3]), .I1(complex_pi_incdec_done), .I2(Q[0]), .I3(\init_state_r[5]_i_19_n_0 ), .I4(\init_state_r[4]_i_33_n_0 ), .I5(\init_state_r[6]_i_12_n_0 ), .O(\init_state_r[4]_i_19_n_0 )); LUT6 #( .INIT(64'hABABABABAAABAAAA)) \init_state_r[4]_i_2 (.I0(\init_state_r[5]_i_2_n_0 ), .I1(\init_state_r[4]_i_8_n_0 ), .I2(\init_state_r[4]_i_9_n_0 ), .I3(\init_state_r[4]_i_10_n_0 ), .I4(\init_state_r[4]_i_11_n_0 ), .I5(\init_state_r[4]_i_12_n_0 ), .O(\init_state_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h4000000000000000)) \init_state_r[4]_i_20 (.I0(ddr3_lm_done_r), .I1(wrcal_done_reg_10), .I2(dqs_found_done_r_reg), .I3(wrlvl_done_r1), .I4(prbs_rdlvl_done_reg_rep), .I5(rdlvl_stg1_done_int_reg), .O(\init_state_r[4]_i_20_n_0 )); LUT6 #( .INIT(64'h0000000000000400)) \init_state_r[4]_i_21 (.I0(Q[0]), .I1(cnt_cmd_done_r), .I2(reg_ctrl_cnt_r_reg__0[2]), .I3(reg_ctrl_cnt_r_reg__0[3]), .I4(reg_ctrl_cnt_r_reg__0[0]), .I5(reg_ctrl_cnt_r_reg__0[1]), .O(\init_state_r[4]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair494" *) LUT2 #( .INIT(4'hB)) \init_state_r[4]_i_22 (.I0(mem_init_done_r), .I1(cnt_init_af_done_r), .O(\init_state_r[4]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair482" *) LUT4 #( .INIT(16'hFEFF)) \init_state_r[4]_i_24 (.I0(num_refresh_reg__0[1]), .I1(num_refresh_reg__0[0]), .I2(num_refresh_reg__0[2]), .I3(num_refresh_reg__0[3]), .O(\init_state_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair490" *) LUT4 #( .INIT(16'h0800)) \init_state_r[4]_i_26 (.I0(mem_init_done_r), .I1(dqs_found_done_r_reg), .I2(prbs_rdlvl_done_reg_rep), .I3(prbs_last_byte_done_r), .O(\init_state_r[4]_i_26_n_0 )); LUT6 #( .INIT(64'h00FF00AB00FF0000)) \init_state_r[4]_i_27 (.I0(cnt_cmd_done_r_reg_1), .I1(prech_pending_r_reg_0), .I2(oclkdelay_calib_done_r_reg_2), .I3(\init_state_r[5]_i_57_n_0 ), .I4(Q[0]), .I5(Q[1]), .O(\init_state_r[4]_i_27_n_0 )); LUT4 #( .INIT(16'hABAA)) \init_state_r[4]_i_28 (.I0(Q[3]), .I1(read_calib_reg_0), .I2(pi_phase_locked_all_r4), .I3(pi_phase_locked_all_r3), .O(\init_state_r[4]_i_28_n_0 )); (* SOFT_HLUTNM = "soft_lutpair533" *) LUT4 #( .INIT(16'h0004)) \init_state_r[4]_i_29 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .O(\init_state_r[4]_i_29_n_0 )); LUT6 #( .INIT(64'h75FF75FF00FFFFFF)) \init_state_r[4]_i_3 (.I0(\init_state_r[4]_i_13_n_0 ), .I1(\init_state_r_reg[4]_0 ), .I2(dqs_found_done_r_reg), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I4(Q[3]), .I5(cnt_cmd_done_r), .O(\init_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'h4444454445454545)) \init_state_r[4]_i_30 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(oclk_calib_resume_r_reg), .I2(Q[1]), .I3(Q[3]), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(\init_state_r[4]_i_37_n_0 ), .O(\init_state_r[4]_i_30_n_0 )); LUT6 #( .INIT(64'h45004545FFFFFFFF)) \init_state_r[4]_i_31 (.I0(oclk_calib_resume_level_reg_0), .I1(\init_state_r[5]_i_56_n_0 ), .I2(Q[1]), .I3(\init_state_r[6]_i_18_n_0 ), .I4(oclkdelay_center_calib_start_r_reg), .I5(Q[3]), .O(\init_state_r[4]_i_31_n_0 )); LUT6 #( .INIT(64'h2828282828282800)) \init_state_r[4]_i_32 (.I0(\init_state_r[4]_i_38_n_0 ), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(\init_state_r[4]_i_39_n_0 ), .I5(Q[3]), .O(\init_state_r[4]_i_32_n_0 )); LUT6 #( .INIT(64'hFF00060000000000)) \init_state_r[4]_i_33 (.I0(Q[0]), .I1(write_request_r_reg), .I2(Q[1]), .I3(Q[3]), .I4(Q[2]), .I5(Q[5]), .O(\init_state_r[4]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair485" *) LUT5 #( .INIT(32'h2022FFFF)) \init_state_r[4]_i_37 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(prech_pending_r_reg_0), .I2(complex_oclkdelay_calib_done_r1), .I3(prbs_rdlvl_done_reg), .I4(Q[0]), .O(\init_state_r[4]_i_37_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFD00)) \init_state_r[4]_i_38 (.I0(\init_state_r[5]_i_54_n_0 ), .I1(\init_state_r[4]_i_40_n_0 ), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(\init_state_r[6]_i_23_n_0 ), .I5(\init_state_r_reg[1]_0 ), .O(\init_state_r[4]_i_38_n_0 )); (* SOFT_HLUTNM = "soft_lutpair545" *) LUT4 #( .INIT(16'hF4FF)) \init_state_r[4]_i_39 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg), .I2(Q[1]), .I3(Q[0]), .O(\init_state_r[4]_i_39_n_0 )); LUT6 #( .INIT(64'hAAAAFFFFAAAABBFA)) \init_state_r[4]_i_4 (.I0(\init_state_r[5]_i_12_n_0 ), .I1(rdlvl_stg1_done_r1), .I2(Q[3]), .I3(cnt_cmd_done_r), .I4(prbs_rdlvl_start_i_2_n_0), .I5(reset_rd_addr_r1), .O(\init_state_r[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair505" *) LUT5 #( .INIT(32'h2AAAAAAA)) \init_state_r[4]_i_40 (.I0(Q[3]), .I1(complex_wait_cnt_reg__0[3]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .O(\init_state_r[4]_i_40_n_0 )); LUT2 #( .INIT(4'h7)) \init_state_r[4]_i_5 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF0400)) \init_state_r[4]_i_6 (.I0(oclk_calib_resume_level_reg_0), .I1(cnt_cmd_done_r), .I2(prbs_rdlvl_start_i_2_n_0), .I3(dqs_found_done_r_reg_0), .I4(\init_state_r[4]_i_15_n_0 ), .I5(Q[3]), .O(\init_state_r[4]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF44450000)) \init_state_r[4]_i_7 (.I0(\init_state_r[5]_i_26_n_0 ), .I1(\init_state_r[4]_i_16_n_0 ), .I2(oclk_calib_resume_level_reg_0), .I3(\init_state_r[4]_i_17_n_0 ), .I4(\init_state_r[4]_i_18_n_0 ), .I5(\init_state_r[4]_i_19_n_0 ), .O(\init_state_r[4]_i_7_n_0 )); LUT6 #( .INIT(64'hA2AAA200AAAAAAAA)) \init_state_r[4]_i_8 (.I0(\wrcal_reads[7]_i_5_n_0 ), .I1(\init_state_r[4]_i_20_n_0 ), .I2(wrcal_sanity_chk_done_reg_0), .I3(cnt_cmd_done_r), .I4(Q[3]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\init_state_r[4]_i_8_n_0 )); LUT6 #( .INIT(64'h57DF55555555FFFF)) \init_state_r[4]_i_9 (.I0(Q[3]), .I1(Q[1]), .I2(\init_state_r[4]_i_21_n_0 ), .I3(Q[0]), .I4(\init_state_r_reg_n_0_[3] ), .I5(Q[2]), .O(\init_state_r[4]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF1110)) \init_state_r[5]_i_1 (.I0(\init_state_r[5]_i_2_n_0 ), .I1(\init_state_r[5]_i_3_n_0 ), .I2(\init_state_r[5]_i_4_n_0 ), .I3(\init_state_r[5]_i_5_n_0 ), .I4(\init_state_r[5]_i_6_n_0 ), .I5(\init_state_r[5]_i_7_n_0 ), .O(\init_state_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000AA10)) \init_state_r[5]_i_10 (.I0(Q[1]), .I1(cnt_cmd_done_r), .I2(Q[4]), .I3(Q[0]), .I4(\init_state_r[4]_i_5_n_0 ), .I5(\init_state_r[5]_i_31_n_0 ), .O(\init_state_r[5]_i_10_n_0 )); LUT6 #( .INIT(64'h00000000002A0000)) \init_state_r[5]_i_11 (.I0(\init_state_r[1]_i_10_n_0 ), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[4]), .I5(\init_state_r[1]_i_11_n_0 ), .O(\init_state_r[5]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair483" *) LUT5 #( .INIT(32'h02220202)) \init_state_r[5]_i_12 (.I0(Q[1]), .I1(Q[0]), .I2(\init_state_r[5]_i_32_n_0 ), .I3(complex_sample_cnt_inc_i_2_n_0), .I4(rdlvl_stg1_done_r1), .O(\init_state_r[5]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair500" *) LUT5 #( .INIT(32'h00000010)) \init_state_r[5]_i_13 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\init_state_r[5]_i_13_n_0 )); LUT6 #( .INIT(64'h7500FFFF75007500)) \init_state_r[5]_i_14 (.I0(pi_calib_done), .I1(wrcal_done_reg_10), .I2(dqs_found_done_r_reg), .I3(\init_state_r[5]_i_33_n_0 ), .I4(prbs_rdlvl_start_i_2_n_0), .I5(reset_rd_addr_r1), .O(\init_state_r[5]_i_14_n_0 )); LUT6 #( .INIT(64'h00000000000FCDCD)) \init_state_r[5]_i_15 (.I0(cnt_txpr_done_r), .I1(\init_state_r[5]_i_34_n_0 ), .I2(\init_state_r[5]_i_16_n_0 ), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[5]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair524" *) LUT2 #( .INIT(4'h7)) \init_state_r[5]_i_16 (.I0(Q[4]), .I1(Q[0]), .O(\init_state_r[5]_i_16_n_0 )); LUT6 #( .INIT(64'h0000000040700000)) \init_state_r[5]_i_17 (.I0(wrlvl_rank_done_r7), .I1(Q[1]), .I2(Q[0]), .I3(cnt_dllk_zqinit_done_r), .I4(\init_state_r[5]_i_35_n_0 ), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[5]_i_17_n_0 )); LUT2 #( .INIT(4'h8)) \init_state_r[5]_i_18 (.I0(Q[0]), .I1(complex_pi_incdec_done), .O(\init_state_r[5]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair521" *) LUT5 #( .INIT(32'h00E00000)) \init_state_r[5]_i_19 (.I0(\init_state_r[5]_i_36_n_0 ), .I1(Q[0]), .I2(Q[5]), .I3(Q[2]), .I4(Q[1]), .O(\init_state_r[5]_i_19_n_0 )); LUT2 #( .INIT(4'hE)) \init_state_r[5]_i_2 (.I0(Q[5]), .I1(Q[4]), .O(\init_state_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'hBFBF15B7FFFFFFFF)) \init_state_r[5]_i_20 (.I0(Q[0]), .I1(Q[4]), .I2(write_request_r_reg), .I3(\init_state_r[6]_i_22_n_0 ), .I4(prech_pending_r_reg_0), .I5(\init_state_r[5]_i_38_n_0 ), .O(\init_state_r[5]_i_20_n_0 )); LUT6 #( .INIT(64'h444F44444F4F4F4F)) \init_state_r[5]_i_21 (.I0(\init_state_r[5]_i_39_n_0 ), .I1(\init_state_r[5]_i_40_n_0 ), .I2(\init_state_r[5]_i_41_n_0 ), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(Q[4]), .I5(\init_state_r[5]_i_42_n_0 ), .O(\init_state_r[5]_i_21_n_0 )); LUT6 #( .INIT(64'h0808080888888808)) \init_state_r[5]_i_22 (.I0(\init_state_r[5]_i_43_n_0 ), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(Q[4]), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(prbs_rdlvl_done_pulse0), .O(\init_state_r[5]_i_22_n_0 )); LUT6 #( .INIT(64'h4F4F4F4FFF4F4F4F)) \init_state_r[5]_i_23 (.I0(\init_state_r[5]_i_44_n_0 ), .I1(\init_state_r[5]_i_45_n_0 ), .I2(Q[3]), .I3(\init_state_r_reg[5]_0 ), .I4(Q[4]), .I5(oclk_calib_resume_r_reg_0), .O(\init_state_r[5]_i_23_n_0 )); LUT6 #( .INIT(64'h44455555FFFFFFFF)) \init_state_r[5]_i_24 (.I0(\init_state_r[5]_i_48_n_0 ), .I1(\init_state_r[5]_i_49_n_0 ), .I2(Q[4]), .I3(wrcal_resume_r), .I4(\wrcal_reads[7]_i_6_n_0 ), .I5(\wrcal_reads[7]_i_5_n_0 ), .O(\init_state_r[5]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEEFEE)) \init_state_r[5]_i_25 (.I0(\init_state_r[5]_i_50_n_0 ), .I1(Q[3]), .I2(\init_state_r[5]_i_51_n_0 ), .I3(Q[4]), .I4(oclk_calib_resume_level_reg_0), .I5(\init_state_r[5]_i_52_n_0 ), .O(\init_state_r[5]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair547" *) LUT2 #( .INIT(4'hB)) \init_state_r[5]_i_26 (.I0(Q[5]), .I1(Q[4]), .O(\init_state_r[5]_i_26_n_0 )); LUT6 #( .INIT(64'h00000000000000D0)) \init_state_r[5]_i_27 (.I0(cnt_init_af_done_r), .I1(mem_init_done_r), .I2(num_refresh_reg__0[3]), .I3(num_refresh_reg__0[2]), .I4(num_refresh_reg__0[0]), .I5(num_refresh_reg__0[1]), .O(\init_state_r[5]_i_27_n_0 )); LUT6 #( .INIT(64'h44FEFFFF44EEFFFF)) \init_state_r[5]_i_29 (.I0(rdlvl_stg1_done_int_reg), .I1(wrcal_done_reg_10), .I2(prbs_last_byte_done_r), .I3(prbs_rdlvl_done_reg_rep), .I4(dqs_found_done_r_reg), .I5(mem_init_done_r), .O(\init_state_r[5]_i_29_n_0 )); LUT6 #( .INIT(64'h000000000000D5DD)) \init_state_r[5]_i_3 (.I0(\init_state_r_reg[1]_0 ), .I1(\init_state_r[5]_i_8_n_0 ), .I2(cnt_cmd_done_r), .I3(\init_state_r[5]_i_9_n_0 ), .I4(\init_state_r[5]_i_10_n_0 ), .I5(\init_state_r[5]_i_11_n_0 ), .O(\init_state_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h00010000FFFFFFFF)) \init_state_r[5]_i_31 (.I0(cnt_cmd_done_r), .I1(\init_state_r[5]_i_16_n_0 ), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(Q[3]), .O(\init_state_r[5]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFFFFFFFF)) \init_state_r[5]_i_32 (.I0(\complex_num_writes_dec[4]_i_5_n_0 ), .I1(rdlvl_stg1_done_r1), .I2(complex_row0_wr_done), .I3(prbs_rdlvl_done_reg_rep), .I4(complex_num_writes_dec_reg__0[1]), .I5(complex_num_writes_dec_reg__0[0]), .O(\init_state_r[5]_i_32_n_0 )); (* SOFT_HLUTNM = "soft_lutpair529" *) LUT3 #( .INIT(8'h20)) \init_state_r[5]_i_33 (.I0(cnt_cmd_done_r), .I1(Q[1]), .I2(Q[0]), .O(\init_state_r[5]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair524" *) LUT5 #( .INIT(32'h04444444)) \init_state_r[5]_i_34 (.I0(Q[0]), .I1(Q[4]), .I2(\mcGo_r_reg[15] ), .I3(cnt_pwron_cke_done_r), .I4(ck_addr_cmd_delay_done), .O(\init_state_r[5]_i_34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair519" *) LUT2 #( .INIT(4'h8)) \init_state_r[5]_i_35 (.I0(Q[4]), .I1(Q[2]), .O(\init_state_r[5]_i_35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair535" *) LUT4 #( .INIT(16'h7FFF)) \init_state_r[5]_i_36 (.I0(ocal_act_wait_cnt_reg__0[2]), .I1(ocal_act_wait_cnt_reg__0[1]), .I2(ocal_act_wait_cnt_reg__0[0]), .I3(ocal_act_wait_cnt_reg__0[3]), .O(\init_state_r[5]_i_36_n_0 )); (* SOFT_HLUTNM = "soft_lutpair574" *) LUT2 #( .INIT(4'h1)) \init_state_r[5]_i_38 (.I0(Q[2]), .I1(Q[1]), .O(\init_state_r[5]_i_38_n_0 )); LUT6 #( .INIT(64'h0000444FFFFFFFFF)) \init_state_r[5]_i_39 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[4]), .I4(complex_oclkdelay_calib_start_int_reg_0), .I5(\init_state_r[5]_i_53_n_0 ), .O(\init_state_r[5]_i_39_n_0 )); LUT6 #( .INIT(64'h5555555544444544)) \init_state_r[5]_i_4 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(\init_state_r[5]_i_12_n_0 ), .I2(complex_oclkdelay_calib_start_int_reg_0), .I3(Q[4]), .I4(\init_state_r[5]_i_13_n_0 ), .I5(\init_state_r[5]_i_14_n_0 ), .O(\init_state_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFE2)) \init_state_r[5]_i_40 (.I0(\init_state_r[0]_i_27_n_0 ), .I1(Q[0]), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[4]), .I4(Q[1]), .I5(\init_state_r[5]_i_13_n_0 ), .O(\init_state_r[5]_i_40_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEAAEA)) \init_state_r[5]_i_41 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(Q[0]), .I2(prbs_rdlvl_done_reg), .I3(complex_oclkdelay_calib_done_r1), .I4(prech_pending_r_reg_0), .I5(Q[1]), .O(\init_state_r[5]_i_41_n_0 )); (* SOFT_HLUTNM = "soft_lutpair485" *) LUT2 #( .INIT(4'hB)) \init_state_r[5]_i_42 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(Q[0]), .O(\init_state_r[5]_i_42_n_0 )); LUT6 #( .INIT(64'hAAAAAAAABFBBAAAA)) \init_state_r[5]_i_43 (.I0(\init_state_r[6]_i_23_n_0 ), .I1(\init_state_r[5]_i_54_n_0 ), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[4]), .I4(Q[0]), .I5(prech_pending_r_reg_0), .O(\init_state_r[5]_i_43_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF03000101)) \init_state_r[5]_i_44 (.I0(Q[4]), .I1(Q[1]), .I2(Q[0]), .I3(oclkdelay_int_ref_req_reg_0), .I4(cnt_cmd_done_r), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[5]_i_44_n_0 )); LUT6 #( .INIT(64'h3373F373FFFFFFFF)) \init_state_r[5]_i_45 (.I0(oclkdelay_center_calib_start_r_reg_0), .I1(\init_state_r[5]_i_56_n_0 ), .I2(Q[4]), .I3(Q[0]), .I4(cnt_cmd_done_r), .I5(Q[1]), .O(\init_state_r[5]_i_45_n_0 )); (* SOFT_HLUTNM = "soft_lutpair533" *) LUT4 #( .INIT(16'h4000)) \init_state_r[5]_i_46 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .O(\init_state_r_reg[5]_0 )); LUT6 #( .INIT(64'hFFFFFFFFE8E8C8E8)) \init_state_r[5]_i_48 (.I0(Q[1]), .I1(Q[0]), .I2(Q[4]), .I3(pi_phase_locked_all_r3), .I4(pi_phase_locked_all_r4), .I5(\init_state_r[0]_i_25_n_0 ), .O(\init_state_r[5]_i_48_n_0 )); (* SOFT_HLUTNM = "soft_lutpair531" *) LUT4 #( .INIT(16'h5554)) \init_state_r[5]_i_49 (.I0(wrcal_resume_r), .I1(wrcal_done_reg_10), .I2(prech_pending_r_reg_0), .I3(wrlvl_byte_redo), .O(\init_state_r[5]_i_49_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEEFEE)) \init_state_r[5]_i_5 (.I0(\init_state_r[5]_i_15_n_0 ), .I1(Q[3]), .I2(\init_state_r[5]_i_16_n_0 ), .I3(\init_state_r_reg_n_0_[3] ), .I4(cnt_cmd_done_r), .I5(\init_state_r[5]_i_17_n_0 ), .O(\init_state_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000EEEEFEEE)) \init_state_r[5]_i_50 (.I0(\init_state_r[5]_i_57_n_0 ), .I1(\init_state_r[5]_i_58_n_0 ), .I2(Q[1]), .I3(Q[4]), .I4(oclkdelay_calib_done_r_reg_3), .I5(\init_state_r[5]_i_60_n_0 ), .O(\init_state_r[5]_i_50_n_0 )); LUT6 #( .INIT(64'h0054000000540054)) \init_state_r[5]_i_51 (.I0(Q[1]), .I1(wrcal_done_reg_10), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(wrcal_prech_req), .I5(cnt_cmd_done_r), .O(\init_state_r[5]_i_51_n_0 )); LUT6 #( .INIT(64'h00000000F2F200F2)) \init_state_r[5]_i_52 (.I0(\init_state_r[5]_i_61_n_0 ), .I1(wrcal_prech_req), .I2(\init_state_r[1]_i_20_n_0 ), .I3(Q[1]), .I4(\init_state_r[5]_i_62_n_0 ), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[5]_i_52_n_0 )); LUT6 #( .INIT(64'h4044404040444044)) \init_state_r[5]_i_53 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[1]), .I3(prech_pending_r_reg_0), .I4(prbs_rdlvl_done_r1), .I5(prbs_rdlvl_done_reg), .O(\init_state_r[5]_i_53_n_0 )); LUT6 #( .INIT(64'hFFFF00BFFFFFFFFF)) \init_state_r[5]_i_54 (.I0(complex_row1_wr_done), .I1(complex_ocal_num_samples_done_r), .I2(complex_oclkdelay_calib_start_int), .I3(\one_rank.stg1_wr_done_reg_0 ), .I4(oclkdelay_center_calib_start_r_reg), .I5(prbs_gen_oclk_clk_en_i_8_n_0), .O(\init_state_r[5]_i_54_n_0 )); (* SOFT_HLUTNM = "soft_lutpair534" *) LUT4 #( .INIT(16'hEEEF)) \init_state_r[5]_i_56 (.I0(oclkdelay_int_ref_req_reg_0), .I1(Q[0]), .I2(complex_oclk_calib_resume), .I3(oclk_calib_resume_level), .O(\init_state_r[5]_i_56_n_0 )); LUT6 #( .INIT(64'h0004000000000000)) \init_state_r[5]_i_57 (.I0(oclk_wr_cnt_reg__0[2]), .I1(oclk_wr_cnt_reg__0[0]), .I2(oclk_wr_cnt_reg__0[1]), .I3(oclk_wr_cnt_reg__0[3]), .I4(Q[1]), .I5(Q[0]), .O(\init_state_r[5]_i_57_n_0 )); LUT6 #( .INIT(64'h5D5D5D5D5D5D7D5D)) \init_state_r[5]_i_58 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(lim2init_prech_req), .I5(ocd_prech_req), .O(\init_state_r[5]_i_58_n_0 )); LUT6 #( .INIT(64'hFFCF8F8FCCCC8888)) \init_state_r[5]_i_6 (.I0(\init_state_r[5]_i_18_n_0 ), .I1(\init_state_r[5]_i_19_n_0 ), .I2(\init_state_r[5]_i_20_n_0 ), .I3(Q[2]), .I4(Q[4]), .I5(Q[5]), .O(\init_state_r[5]_i_6_n_0 )); LUT6 #( .INIT(64'h000000F1FFFFFFFF)) \init_state_r[5]_i_60 (.I0(cnt_cmd_done_r), .I1(Q[0]), .I2(\init_state_r_reg[1]_1 ), .I3(Q[4]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[5]_i_60_n_0 )); (* SOFT_HLUTNM = "soft_lutpair536" *) LUT2 #( .INIT(4'h2)) \init_state_r[5]_i_61 (.I0(cnt_cmd_done_r), .I1(Q[0]), .O(\init_state_r[5]_i_61_n_0 )); (* SOFT_HLUTNM = "soft_lutpair576" *) LUT3 #( .INIT(8'hCA)) \init_state_r[5]_i_62 (.I0(cnt_cmd_done_r), .I1(burst_addr_r_reg_0), .I2(Q[0]), .O(\init_state_r[5]_i_62_n_0 )); LUT6 #( .INIT(64'h00000000FEFE00FE)) \init_state_r[5]_i_7 (.I0(\init_state_r[5]_i_21_n_0 ), .I1(\init_state_r[5]_i_22_n_0 ), .I2(\init_state_r[5]_i_23_n_0 ), .I3(\init_state_r[5]_i_24_n_0 ), .I4(\init_state_r[5]_i_25_n_0 ), .I5(\init_state_r[5]_i_26_n_0 ), .O(\init_state_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFF5FFFDFDFDFDF)) \init_state_r[5]_i_8 (.I0(\init_state_r[4]_i_11_n_0 ), .I1(oclkdelay_calib_done_r_reg_2), .I2(\init_state_r[5]_i_27_n_0 ), .I3(wrlvl_byte_redo_reg), .I4(\init_state_r[5]_i_29_n_0 ), .I5(mpr_rdlvl_done_r_reg_2), .O(\init_state_r[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair594" *) LUT2 #( .INIT(4'h2)) \init_state_r[5]_i_9 (.I0(Q[4]), .I1(Q[0]), .O(\init_state_r[5]_i_9_n_0 )); LUT6 #( .INIT(64'hAAAA20AAAAAAAAAA)) \init_state_r[6]_i_10 (.I0(\init_state_r[6]_i_20_n_0 ), .I1(prbs_rdlvl_done_r1), .I2(prbs_rdlvl_done_reg), .I3(Q[5]), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\init_state_r[6]_i_10_n_0 )); LUT6 #( .INIT(64'h0100000000000000)) \init_state_r[6]_i_11 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(Q[4]), .I2(ddr3_lm_done_r_i_2_n_0), .I3(\init_state_r[6]_i_21_n_0 ), .I4(cnt_cmd_done_r), .I5(rdlvl_stg1_done_r1), .O(\init_state_r[6]_i_11_n_0 )); LUT6 #( .INIT(64'h0020002000200000)) \init_state_r[6]_i_12 (.I0(Q[0]), .I1(Q[1]), .I2(Q[5]), .I3(Q[2]), .I4(\init_state_r[6]_i_22_n_0 ), .I5(prech_pending_r_reg_0), .O(\init_state_r[6]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair526" *) LUT4 #( .INIT(16'hAA08)) \init_state_r[6]_i_13 (.I0(Q[0]), .I1(prbs_rdlvl_done_reg_rep), .I2(complex_oclkdelay_calib_done_r1), .I3(prech_pending_r_reg_0), .O(\init_state_r[6]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair547" *) LUT4 #( .INIT(16'hFF4F)) \init_state_r[6]_i_14 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg), .I2(Q[5]), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .O(\init_state_r[6]_i_14_n_0 )); LUT4 #( .INIT(16'hFFAE)) \init_state_r[6]_i_15 (.I0(\init_state_r[5]_i_13_n_0 ), .I1(prbs_rdlvl_done_reg), .I2(prbs_rdlvl_done_r1), .I3(prech_pending_r_reg_0), .O(\init_state_r[6]_i_15_n_0 )); LUT6 #( .INIT(64'h8000FFFF80000000)) \init_state_r[6]_i_16 (.I0(complex_wait_cnt_reg__0[0]), .I1(complex_wait_cnt_reg__0[1]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[3]), .I4(Q[0]), .I5(\init_state_r[0]_i_27_n_0 ), .O(\init_state_r[6]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair534" *) LUT2 #( .INIT(4'hE)) \init_state_r[6]_i_17 (.I0(oclk_calib_resume_level), .I1(complex_oclk_calib_resume), .O(\init_state_r[6]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \init_state_r[6]_i_18 (.I0(Q[1]), .I1(Q[0]), .I2(wrlvl_final_mux), .I3(oclkdelay_int_ref_req_reg_0), .I4(prech_pending_r_reg_0), .I5(oclkdelay_calib_done_r_reg_2), .O(\init_state_r[6]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair506" *) LUT2 #( .INIT(4'h6)) \init_state_r[6]_i_19 (.I0(Q[0]), .I1(Q[1]), .O(\init_state_r[6]_i_19_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00D00000)) \init_state_r[6]_i_2 (.I0(\init_state_r[6]_i_3_n_0 ), .I1(\init_state_r[6]_i_4_n_0 ), .I2(Q[4]), .I3(Q[5]), .I4(Q[3]), .I5(\init_state_r[6]_i_5_n_0 ), .O(\init_state_r[6]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFABFB0000)) \init_state_r[6]_i_20 (.I0(prech_pending_r_reg_0), .I1(Q[5]), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(oclkdelay_center_calib_start_r_reg), .I4(Q[0]), .I5(\init_state_r[6]_i_23_n_0 ), .O(\init_state_r[6]_i_20_n_0 )); (* SOFT_HLUTNM = "soft_lutpair541" *) LUT2 #( .INIT(4'h2)) \init_state_r[6]_i_21 (.I0(Q[0]), .I1(reset_rd_addr_r1), .O(\init_state_r[6]_i_21_n_0 )); LUT4 #( .INIT(16'h0004)) \init_state_r[6]_i_22 (.I0(mask_lim_done), .I1(done_r_reg), .I2(complex_mask_lim_done), .I3(oclkdelay_center_calib_start_r_reg), .O(\init_state_r[6]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair506" *) LUT5 #( .INIT(32'h37773737)) \init_state_r[6]_i_23 (.I0(Q[0]), .I1(Q[1]), .I2(prbs_rdlvl_start_r_reg), .I3(num_samples_done_r), .I4(complex_init_pi_dec_done), .O(\init_state_r[6]_i_23_n_0 )); LUT6 #( .INIT(64'hFBFBFBFAFBFBFBFB)) \init_state_r[6]_i_3 (.I0(\init_state_r[6]_i_6_n_0 ), .I1(complex_oclkdelay_calib_start_int_reg_0), .I2(\init_state_r[4]_i_5_n_0 ), .I3(prbs_rdlvl_done_reg_rep_0), .I4(complex_oclk_calib_resume), .I5(Q[5]), .O(\init_state_r[6]_i_3_n_0 )); LUT6 #( .INIT(64'h0503FFFF05F3FFFF)) \init_state_r[6]_i_4 (.I0(\init_state_r[6]_i_8_n_0 ), .I1(\init_state_r[6]_i_9_n_0 ), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[3]), .I5(\init_state_r[6]_i_10_n_0 ), .O(\init_state_r[6]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000FAFACAFA)) \init_state_r[6]_i_5 (.I0(\init_state_r[6]_i_11_n_0 ), .I1(Q[2]), .I2(Q[5]), .I3(complex_pi_incdec_done), .I4(prbs_rdlvl_start_i_2_n_0), .I5(\init_state_r[6]_i_12_n_0 ), .O(\init_state_r[6]_i_5_n_0 )); LUT6 #( .INIT(64'h5555555545455545)) \init_state_r[6]_i_6 (.I0(Q[1]), .I1(prbs_gen_oclk_clk_en_i_8_n_0), .I2(Q[5]), .I3(Q[0]), .I4(complex_sample_cnt_inc_i_2_n_0), .I5(\init_state_r[6]_i_13_n_0 ), .O(\init_state_r[6]_i_6_n_0 )); LUT6 #( .INIT(64'hEEEEFFFFEEEEF0FF)) \init_state_r[6]_i_8 (.I0(\init_state_r[6]_i_14_n_0 ), .I1(Q[0]), .I2(\init_state_r[6]_i_15_n_0 ), .I3(Q[5]), .I4(Q[1]), .I5(\init_state_r[6]_i_16_n_0 ), .O(\init_state_r[6]_i_8_n_0 )); LUT6 #( .INIT(64'hFAFAFBFBFA00FBFB)) \init_state_r[6]_i_9 (.I0(\init_state_r[6]_i_17_n_0 ), .I1(oclkdelay_center_calib_start_r_reg), .I2(\init_state_r[6]_i_18_n_0 ), .I3(\init_state_r[6]_i_19_n_0 ), .I4(Q[5]), .I5(cnt_cmd_done_r), .O(\init_state_r[6]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \init_state_r_reg[0] (.C(CLK), .CE(1'b1), .D(\init_state_r[0]_i_1_n_0 ), .Q(Q[0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r_reg[1] (.C(CLK), .CE(1'b1), .D(\init_state_r[1]_i_1_n_0 ), .Q(Q[1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r_reg[2] (.C(CLK), .CE(1'b1), .D(\init_state_r[2]_i_1_n_0 ), .Q(Q[2]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r_reg[3] (.C(CLK), .CE(1'b1), .D(\init_state_r[3]_i_1_n_0 ), .Q(\init_state_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r_reg[4] (.C(CLK), .CE(1'b1), .D(\init_state_r[4]_i_1_n_0 ), .Q(Q[3]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r_reg[5] (.C(CLK), .CE(1'b1), .D(\init_state_r[5]_i_1_n_0 ), .Q(Q[4]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \init_state_r_reg[6] (.C(CLK), .CE(1'b1), .D(\init_state_r[6]_i_2_n_0 ), .Q(Q[5]), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair605" *) LUT2 #( .INIT(4'h2)) lim_start_r_i_3 (.I0(\oclkdelay_ref_cnt_reg[13]_0 ), .I1(oclkdelay_calib_done_r_reg_2), .O(lim_start_r_reg)); LUT4 #( .INIT(16'h000E)) mask_lim_done_i_1 (.I0(mask_lim_done), .I1(prech_pending_r), .I2(prech_done_r3), .I3(rstdiv0_sync_r1_reg_rep__24), .O(mask_lim_done_i_1_n_0)); FDRE #( .INIT(1'b0)) mask_lim_done_reg (.C(CLK), .CE(1'b1), .D(mask_lim_done_i_1_n_0), .Q(mask_lim_done), .R(1'b0)); LUT5 #( .INIT(32'hFFFF4000)) mem_init_done_r_i_1 (.I0(cnt_dllk_zqinit_done_r), .I1(mem_init_done_r_reg_0[1]), .I2(mem_init_done_r_reg_1), .I3(mem_init_done_r_reg_0[0]), .I4(mem_init_done_r), .O(mem_init_done_r_i_1_n_0)); LUT6 #( .INIT(64'h8000000000000000)) mem_init_done_r_i_2 (.I0(cnt_dllk_zqinit_r_reg__0[5]), .I1(cnt_dllk_zqinit_r_reg__0[3]), .I2(cnt_dllk_zqinit_r_reg__0[1]), .I3(cnt_dllk_zqinit_r_reg__0[0]), .I4(cnt_dllk_zqinit_r_reg__0[2]), .I5(cnt_dllk_zqinit_r_reg__0[4]), .O(mem_init_done_r_reg_1)); FDRE #( .INIT(1'b0)) mem_init_done_r_reg (.C(CLK), .CE(1'b1), .D(mem_init_done_r_i_1_n_0), .Q(mem_init_done_r), .R(rstdiv0_sync_r1_reg_rep__11)); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_0_5_i_1 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_cs_n), .O(\rd_ptr_timing_reg[0]_3 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [63]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [31]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [127]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [95]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [191]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_7 (.I0(\write_buffer.wr_buf_out_data_reg[255] [159]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [4])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_12_17_i_1 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_cas_n), .O(\rd_ptr_timing_reg[0] [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__0 (.I0(mc_address[16]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [167]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [175]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [183]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [190]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2 (.I0(mc_address[6]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [135]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [143]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [151]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [158]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [231]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [239]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [247]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [254]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [199]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [207]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [215]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [222]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [38]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [46]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [54]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [61]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [6]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [14]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [22]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [29]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [102]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [110]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [118]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [125]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [19])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_18_23_i_1__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2 (.I0(mc_address[27]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [70]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [78]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [86]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [93]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [166]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [174]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [182]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [189]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [134]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [142]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [150]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [157]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [230]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [238]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [246]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [253]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [198]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [206]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [214]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [221]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [22])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_24_29_i_1 (.I0(mc_ras_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_ras_n), .O(\rd_ptr_timing_reg[0] [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__0 (.I0(mc_address[17]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [37]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [45]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [53]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [60]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2 (.I0(mc_address[7]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [5]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [13]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [21]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [28]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [101]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [109]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [117]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [124]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [27])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_24_29_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4 (.I0(mc_address[28]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [69]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [77]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [85]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [92]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [165]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [173]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [181]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [188]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [133]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [141]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [149]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [156]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1 (.I0(mc_address[18]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__0 (.I0(mc_bank[3]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [229]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [237]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [245]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [252]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2 (.I0(mc_address[8]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__0 (.I0(mc_bank[0]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [197]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [205]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [213]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [220]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [36]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [44]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [52]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [59]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [33])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_30_35_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[15])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_30_35_i_3__4 (.I0(phy_bank[9]), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4 (.I0(mc_address[29]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__0 (.I0(mc_bank[6]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [4]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [12]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [20]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [27]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [100]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [108]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [116]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [123]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [68]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [76]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [84]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [91]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1 (.I0(mc_address[14]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__0 (.I0(mc_address[19]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [164]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [172]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [180]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [187]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2 (.I0(mc_address[4]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__0 (.I0(mc_address[9]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [132]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [140]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [148]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [155]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [228]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [236]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [244]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [251]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [196]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [204]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [212]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [219]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [35]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [43]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [51]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [58]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [3]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [11]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [19]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [26]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [40])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_42_47_i_1 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__14), .I2(calib_odt), .O(\my_full_reg[3] [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [99]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [107]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [115]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [122]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [43])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_42_47_i_1__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [9])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_42_47_i_1__5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2 (.I0(mc_address[25]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__0 (.I0(mc_address[30]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [67]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [75]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [83]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [90]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3 (.I0(mc_bank[5]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [163]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [171]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [179]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [186]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4 (.I0(mc_bank[2]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [131]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [139]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [147]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [154]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [227]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [235]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [243]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [250]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [47])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_42_47_i_5__3 (.I0(phy_bank[11]), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6 (.I0(mc_bank[8]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [195]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [203]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [211]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [218]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [46])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_48_53_i_1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__14), .I2(calib_cke), .O(\my_full_reg[3] [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__0 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__1 (.I0(mc_address[20]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [34]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [42]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [50]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [57]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2 (.I0(mc_address[1]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__0 (.I0(mc_address[10]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [2]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [40])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [10]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [40])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [18]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [40])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [25]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [98]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [43])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [106]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [43])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [114]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [43])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [121]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [51])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_48_53_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [17])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_48_53_i_3__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4 (.I0(mc_address[22]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__0 (.I0(mc_address[31]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [66]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [74]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [82]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [89]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [162]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [170]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [178]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [185]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6 (.I0(mc_address[0]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [130]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [138]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [146]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [153]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [226]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [47])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [234]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [47])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [242]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [47])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [249]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [55])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_54_59_i_1__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2 (.I0(mc_address[11]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__0 (.I0(mc_address[21]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [194]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [46])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [202]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [46])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [210]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [46])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [217]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [33]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [41]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [49]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [56]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [57])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_54_59_i_3__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4 (.I0(mc_address[2]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__0 (.I0(mc_address[32]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [1]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [9]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [17]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [24]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [97]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [51])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [105]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [51])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [113]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [51])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [120]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [59])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_54_59_i_5__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6 (.I0(mc_address[23]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [65]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [73]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [81]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [88]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1 (.I0(mc_address[13]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__0 (.I0(mc_ras_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [161]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [169]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [177]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [184]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2 (.I0(mc_address[3]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__0 (.I0(mc_address[12]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [129]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [137]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [145]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [152]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [225]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [55])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [233]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [55])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [241]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [55])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [248]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [193]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [201]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [209]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [216]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [62])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [32]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [57])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [40]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [57])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [48]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [57])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [0]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__13), .O(\my_empty_reg[7]_38 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [8]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [16]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [96]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [59])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [104]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [59])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [112]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [59])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_66_71_i_1__2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [29])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_66_71_i_1__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2 (.I0(mc_address[24]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__0 (.I0(mc_address[33]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [64]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [72]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [80]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [160]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [168]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [176]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [128]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [136]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [144]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [224]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [232]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [240]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [192]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [62])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [200]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [62])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [208]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [62])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_6_11_i_1 (.I0(mc_we_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_we_n), .O(\rd_ptr_timing_reg[0]_3 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__0 (.I0(mc_address[15]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [39]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [47]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [55]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [255]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2 (.I0(mc_address[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [7]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [15]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [23]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [223]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [62]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [103]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [111]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [119]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [3])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_6_11_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4 (.I0(mc_address[26]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [30]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [71]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [79]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [87]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [126]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [94]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_72_77_i_1__0 (.I0(mc_bank[4]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_72_77_i_2 (.I0(mc_bank[1]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [30])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_72_77_i_3 (.I0(phy_bank[10]), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_72_77_i_4 (.I0(mc_bank[7]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [32])); (* SOFT_HLUTNM = "soft_lutpair482" *) LUT5 #( .INIT(32'hAAAAAAA8)) mpr_end_if_reset_i_1 (.I0(mpr_last_byte_done), .I1(num_refresh_reg__0[2]), .I2(num_refresh_reg__0[0]), .I3(num_refresh_reg__0[1]), .I4(num_refresh_reg__0[3]), .O(mpr_end_if_reset0)); FDRE #( .INIT(1'b0)) mpr_end_if_reset_reg (.C(CLK), .CE(1'b1), .D(mpr_end_if_reset0), .Q(mpr_end_if_reset), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'hFFFFFFFF00100000)) mpr_rdlvl_start_i_1 (.I0(mpr_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(dqs_found_done_r_reg), .I5(mpr_rdlvl_start_r_reg), .O(mpr_rdlvl_start_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair522" *) LUT4 #( .INIT(16'hFBFF)) mpr_rdlvl_start_i_2 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(Q[0]), .O(mpr_rdlvl_start_i_2_n_0)); FDRE #( .INIT(1'b0)) mpr_rdlvl_start_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_start_i_1_n_0), .Q(mpr_rdlvl_start_r_reg), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair608" *) LUT1 #( .INIT(2'h1)) \num_refresh[0]_i_1 (.I0(num_refresh_reg__0[0]), .O(p_0_in__4[0])); (* SOFT_HLUTNM = "soft_lutpair608" *) LUT2 #( .INIT(4'h6)) \num_refresh[1]_i_1 (.I0(num_refresh_reg__0[1]), .I1(num_refresh_reg__0[0]), .O(p_0_in__4[1])); (* SOFT_HLUTNM = "soft_lutpair553" *) LUT3 #( .INIT(8'h6A)) \num_refresh[2]_i_1 (.I0(num_refresh_reg__0[2]), .I1(num_refresh_reg__0[0]), .I2(num_refresh_reg__0[1]), .O(p_0_in__4[2])); LUT6 #( .INIT(64'hFEFEFEFEFEFFFEFE)) \num_refresh[3]_i_1 (.I0(\num_refresh[3]_i_4_n_0 ), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(\num_refresh[3]_i_5_n_0 ), .I3(prbs_rdlvl_start_i_2_n_0), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(read_calib_i_2_n_0), .O(\num_refresh[3]_i_1_n_0 )); LUT6 #( .INIT(64'h22A2AAA2AAAAAAAA)) \num_refresh[3]_i_2 (.I0(\cnt_init_mr_r_reg[1]_0 ), .I1(dqs_found_done_r_reg), .I2(wrcal_done_reg_10), .I3(rdlvl_stg1_done_int_reg), .I4(prbs_rdlvl_done_reg), .I5(oclkdelay_calib_done_r_reg_2), .O(num_refresh0)); (* SOFT_HLUTNM = "soft_lutpair553" *) LUT4 #( .INIT(16'h6AAA)) \num_refresh[3]_i_3 (.I0(num_refresh_reg__0[3]), .I1(num_refresh_reg__0[1]), .I2(num_refresh_reg__0[0]), .I3(num_refresh_reg__0[2]), .O(p_0_in__4[3])); (* SOFT_HLUTNM = "soft_lutpair503" *) LUT5 #( .INIT(32'h404000FF)) \num_refresh[3]_i_4 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[0]), .I3(\num_refresh[3]_i_6_n_0 ), .I4(Q[1]), .O(\num_refresh[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000002000)) \num_refresh[3]_i_5 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(complex_oclkdelay_calib_start_int_reg_0), .O(\num_refresh[3]_i_5_n_0 )); LUT6 #( .INIT(64'hFBFFFFFFFEFFFFFF)) \num_refresh[3]_i_6 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(Q[0]), .O(\num_refresh[3]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \num_refresh_reg[0] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[0]), .Q(num_refresh_reg__0[0]), .R(\num_refresh[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \num_refresh_reg[1] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[1]), .Q(num_refresh_reg__0[1]), .R(\num_refresh[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \num_refresh_reg[2] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[2]), .Q(num_refresh_reg__0[2]), .R(\num_refresh[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \num_refresh_reg[3] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[3]), .Q(num_refresh_reg__0[3]), .R(\num_refresh[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \ocal_act_wait_cnt[0]_i_1 (.I0(ocal_act_wait_cnt_reg__0[0]), .O(p_0_in__9[0])); (* SOFT_HLUTNM = "soft_lutpair600" *) LUT2 #( .INIT(4'h6)) \ocal_act_wait_cnt[1]_i_1 (.I0(ocal_act_wait_cnt_reg__0[1]), .I1(ocal_act_wait_cnt_reg__0[0]), .O(p_0_in__9[1])); (* SOFT_HLUTNM = "soft_lutpair600" *) LUT3 #( .INIT(8'h6A)) \ocal_act_wait_cnt[2]_i_1 (.I0(ocal_act_wait_cnt_reg__0[2]), .I1(ocal_act_wait_cnt_reg__0[1]), .I2(ocal_act_wait_cnt_reg__0[0]), .O(p_0_in__9[2])); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) \ocal_act_wait_cnt[3]_i_1 (.I0(\ocal_act_wait_cnt[3]_i_3_n_0 ), .I1(Q[4]), .I2(Q[3]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[5]), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\ocal_act_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair535" *) LUT4 #( .INIT(16'h6AAA)) \ocal_act_wait_cnt[3]_i_2 (.I0(ocal_act_wait_cnt_reg__0[3]), .I1(ocal_act_wait_cnt_reg__0[0]), .I2(ocal_act_wait_cnt_reg__0[1]), .I3(ocal_act_wait_cnt_reg__0[2]), .O(p_0_in__9[3])); LUT6 #( .INIT(64'h000000007FFF0000)) \ocal_act_wait_cnt[3]_i_3 (.I0(ocal_act_wait_cnt_reg__0[3]), .I1(ocal_act_wait_cnt_reg__0[0]), .I2(ocal_act_wait_cnt_reg__0[1]), .I3(ocal_act_wait_cnt_reg__0[2]), .I4(Q[1]), .I5(Q[0]), .O(\ocal_act_wait_cnt[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \ocal_act_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__9[0]), .Q(ocal_act_wait_cnt_reg__0[0]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ocal_act_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__9[1]), .Q(ocal_act_wait_cnt_reg__0[1]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ocal_act_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__9[2]), .Q(ocal_act_wait_cnt_reg__0[2]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ocal_act_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__9[3]), .Q(ocal_act_wait_cnt_reg__0[3]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) ocal_last_byte_done_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_center_calib_done_r_reg), .Q(ocal_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h00000000EEEEEE0E)) oclk_calib_resume_level_i_1 (.I0(oclk_calib_resume_level), .I1(complex_oclk_calib_resume), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(complex_oclkdelay_calib_start_int_i_2_n_0), .I4(oclk_calib_resume_level_reg_0), .I5(rstdiv0_sync_r1_reg_rep__24), .O(oclk_calib_resume_level_i_1_n_0)); FDRE #( .INIT(1'b0)) oclk_calib_resume_level_reg (.C(CLK), .CE(1'b1), .D(oclk_calib_resume_level_i_1_n_0), .Q(oclk_calib_resume_level), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair604" *) LUT1 #( .INIT(2'h1)) \oclk_wr_cnt[0]_i_1 (.I0(oclk_wr_cnt_reg__0[0]), .O(\oclk_wr_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair604" *) LUT2 #( .INIT(4'h9)) \oclk_wr_cnt[1]_i_1 (.I0(oclk_wr_cnt_reg__0[0]), .I1(oclk_wr_cnt_reg__0[1]), .O(\oclk_wr_cnt[1]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \oclk_wr_cnt[2]_i_1 (.I0(oclk_wr_cnt_reg__0[2]), .I1(oclk_wr_cnt_reg__0[1]), .I2(oclk_wr_cnt_reg__0[0]), .O(oclk_wr_cnt0[2])); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAAB)) \oclk_wr_cnt[3]_i_1 (.I0(\oclk_wr_cnt[3]_i_4_n_0 ), .I1(oclk_wr_cnt_reg__0[2]), .I2(oclk_wr_cnt_reg__0[0]), .I3(oclk_wr_cnt_reg__0[1]), .I4(oclk_wr_cnt_reg__0[3]), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\oclk_wr_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'h00800000)) \oclk_wr_cnt[3]_i_2 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(read_calib_i_2_n_0), .I4(\init_state_r_reg_n_0_[3] ), .O(p_0_in0_in)); (* SOFT_HLUTNM = "soft_lutpair544" *) LUT4 #( .INIT(16'hAAA9)) \oclk_wr_cnt[3]_i_3 (.I0(oclk_wr_cnt_reg__0[3]), .I1(oclk_wr_cnt_reg__0[2]), .I2(oclk_wr_cnt_reg__0[0]), .I3(oclk_wr_cnt_reg__0[1]), .O(oclk_wr_cnt0[3])); LUT6 #( .INIT(64'h0000000000100000)) \oclk_wr_cnt[3]_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(Q[4]), .I3(Q[5]), .I4(Q[3]), .I5(oclk_calib_resume_level_reg_0), .O(\oclk_wr_cnt[3]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \oclk_wr_cnt_reg[0] (.C(CLK), .CE(p_0_in0_in), .D(\oclk_wr_cnt[0]_i_1_n_0 ), .Q(oclk_wr_cnt_reg__0[0]), .R(\oclk_wr_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \oclk_wr_cnt_reg[1] (.C(CLK), .CE(p_0_in0_in), .D(\oclk_wr_cnt[1]_i_1_n_0 ), .Q(oclk_wr_cnt_reg__0[1]), .R(\oclk_wr_cnt[3]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclk_wr_cnt_reg[2] (.C(CLK), .CE(p_0_in0_in), .D(oclk_wr_cnt0[2]), .Q(oclk_wr_cnt_reg__0[2]), .S(\oclk_wr_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \oclk_wr_cnt_reg[3] (.C(CLK), .CE(p_0_in0_in), .D(oclk_wr_cnt0[3]), .Q(oclk_wr_cnt_reg__0[3]), .R(\oclk_wr_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair605" *) LUT2 #( .INIT(4'hE)) oclkdelay_calib_start_int_i_1 (.I0(oclkdelay_start_dly_r), .I1(\oclkdelay_ref_cnt_reg[13]_0 ), .O(oclkdelay_calib_start_int_i_1_n_0)); FDRE #( .INIT(1'b0)) oclkdelay_calib_start_int_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_start_int_i_1_n_0), .Q(\oclkdelay_ref_cnt_reg[13]_0 ), .R(rstdiv0_sync_r1_reg_rep__12)); LUT5 #( .INIT(32'h0000AAEA)) oclkdelay_int_ref_req_i_1 (.I0(oclkdelay_int_ref_req_reg_0), .I1(oclkdelay_int_ref_req_i_2_n_0), .I2(oclkdelay_ref_cnt_reg[0]), .I3(oclkdelay_int_ref_req_i_3_n_0), .I4(oclkdelay_int_ref_req0), .O(oclkdelay_int_ref_req_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000001)) oclkdelay_int_ref_req_i_2 (.I0(oclkdelay_ref_cnt_reg[12]), .I1(oclkdelay_ref_cnt_reg[8]), .I2(oclkdelay_ref_cnt_reg[11]), .I3(oclkdelay_ref_cnt_reg[13]), .I4(oclkdelay_ref_cnt_reg[10]), .I5(oclkdelay_ref_cnt_reg[9]), .O(oclkdelay_int_ref_req_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) oclkdelay_int_ref_req_i_3 (.I0(oclkdelay_ref_cnt_reg[5]), .I1(oclkdelay_ref_cnt_reg[4]), .I2(oclkdelay_ref_cnt_reg[6]), .I3(oclkdelay_int_ref_req_i_5_n_0), .O(oclkdelay_int_ref_req_i_3_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF4)) oclkdelay_int_ref_req_i_4 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .I2(ocal_last_byte_done), .I3(oclkdelay_center_calib_done_r_reg_0), .I4(rstdiv0_sync_r1_reg_rep__23), .I5(oclkdelay_calib_done_r_reg_2), .O(oclkdelay_int_ref_req0)); LUT4 #( .INIT(16'hFFFE)) oclkdelay_int_ref_req_i_5 (.I0(oclkdelay_ref_cnt_reg[1]), .I1(oclkdelay_ref_cnt_reg[3]), .I2(oclkdelay_ref_cnt_reg[7]), .I3(oclkdelay_ref_cnt_reg[2]), .O(oclkdelay_int_ref_req_i_5_n_0)); FDRE #( .INIT(1'b0)) oclkdelay_int_ref_req_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_int_ref_req_i_1_n_0), .Q(oclkdelay_int_ref_req_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hEEEEEFEEEEEEEEEE)) \oclkdelay_ref_cnt[0]_i_1 (.I0(prbs_rdlvl_done_reg_0), .I1(\cnt_init_mr_r_reg[1]_0 ), .I2(oclkdelay_int_ref_req_i_3_n_0), .I3(\oclkdelay_ref_cnt_reg[13]_0 ), .I4(oclkdelay_ref_cnt_reg[0]), .I5(oclkdelay_int_ref_req_i_2_n_0), .O(\oclkdelay_ref_cnt[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_4 (.I0(oclkdelay_ref_cnt_reg[3]), .O(\oclkdelay_ref_cnt[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_5 (.I0(oclkdelay_ref_cnt_reg[2]), .O(\oclkdelay_ref_cnt[0]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_6 (.I0(oclkdelay_ref_cnt_reg[1]), .O(\oclkdelay_ref_cnt[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_7 (.I0(oclkdelay_ref_cnt_reg[0]), .O(\oclkdelay_ref_cnt[0]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[12]_i_2 (.I0(oclkdelay_ref_cnt_reg[13]), .O(\oclkdelay_ref_cnt[12]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[12]_i_3 (.I0(oclkdelay_ref_cnt_reg[12]), .O(\oclkdelay_ref_cnt[12]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_2 (.I0(oclkdelay_ref_cnt_reg[7]), .O(\oclkdelay_ref_cnt[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_3 (.I0(oclkdelay_ref_cnt_reg[6]), .O(\oclkdelay_ref_cnt[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_4 (.I0(oclkdelay_ref_cnt_reg[5]), .O(\oclkdelay_ref_cnt[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_5 (.I0(oclkdelay_ref_cnt_reg[4]), .O(\oclkdelay_ref_cnt[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_2 (.I0(oclkdelay_ref_cnt_reg[11]), .O(\oclkdelay_ref_cnt[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_3 (.I0(oclkdelay_ref_cnt_reg[10]), .O(\oclkdelay_ref_cnt[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_4 (.I0(oclkdelay_ref_cnt_reg[9]), .O(\oclkdelay_ref_cnt[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_5 (.I0(oclkdelay_ref_cnt_reg[8]), .O(\oclkdelay_ref_cnt[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \oclkdelay_ref_cnt_reg[0] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_7 ), .Q(oclkdelay_ref_cnt_reg[0]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[0]_i_2 (.CI(1'b0), .CO({\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_1 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_2 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_7 }), .S({\oclkdelay_ref_cnt[0]_i_4_n_0 ,\oclkdelay_ref_cnt[0]_i_5_n_0 ,\oclkdelay_ref_cnt[0]_i_6_n_0 ,\oclkdelay_ref_cnt[0]_i_7_n_0 })); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[10] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ), .Q(oclkdelay_ref_cnt_reg[10]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \oclkdelay_ref_cnt_reg[11] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ), .Q(oclkdelay_ref_cnt_reg[11]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[12] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[12]_i_1_n_7 ), .Q(oclkdelay_ref_cnt_reg[12]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[12]_i_1 (.CI(\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ), .CO({\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED [3:1],\oclkdelay_ref_cnt_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED [3:2],\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ,\oclkdelay_ref_cnt_reg[12]_i_1_n_7 }), .S({1'b0,1'b0,\oclkdelay_ref_cnt[12]_i_2_n_0 ,\oclkdelay_ref_cnt[12]_i_3_n_0 })); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[13] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ), .Q(oclkdelay_ref_cnt_reg[13]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[1] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ), .Q(oclkdelay_ref_cnt_reg[1]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[2] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ), .Q(oclkdelay_ref_cnt_reg[2]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[3] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ), .Q(oclkdelay_ref_cnt_reg[3]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[4] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_7 ), .Q(oclkdelay_ref_cnt_reg[4]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[4]_i_1 (.CI(\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ), .CO({\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_1 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_2 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_7 }), .S({\oclkdelay_ref_cnt[4]_i_2_n_0 ,\oclkdelay_ref_cnt[4]_i_3_n_0 ,\oclkdelay_ref_cnt[4]_i_4_n_0 ,\oclkdelay_ref_cnt[4]_i_5_n_0 })); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[5] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ), .Q(oclkdelay_ref_cnt_reg[5]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \oclkdelay_ref_cnt_reg[6] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ), .Q(oclkdelay_ref_cnt_reg[6]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[7] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ), .Q(oclkdelay_ref_cnt_reg[7]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \oclkdelay_ref_cnt_reg[8] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_7 ), .Q(oclkdelay_ref_cnt_reg[8]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[8]_i_1 (.CI(\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ), .CO({\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_1 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_2 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_7 }), .S({\oclkdelay_ref_cnt[8]_i_2_n_0 ,\oclkdelay_ref_cnt[8]_i_3_n_0 ,\oclkdelay_ref_cnt[8]_i_4_n_0 ,\oclkdelay_ref_cnt[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \oclkdelay_ref_cnt_reg[9] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ), .Q(oclkdelay_ref_cnt_reg[9]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[4]_srl5 " *) SRL16E #( .INIT(16'h0000)) \oclkdelay_start_dly_r_reg[4]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(oclkdelay_calib_start_pre), .Q(\oclkdelay_start_dly_r_reg[4]_srl5_n_0 )); LUT6 #( .INIT(64'h0000000020000000)) \oclkdelay_start_dly_r_reg[4]_srl5_i_1 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(Q[2]), .I4(\init_state_r_reg_n_0_[3] ), .I5(prbs_rdlvl_start_i_2_n_0), .O(oclkdelay_calib_start_pre)); FDRE #( .INIT(1'b0)) \oclkdelay_start_dly_r_reg[5] (.C(CLK), .CE(1'b1), .D(\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ), .Q(oclkdelay_start_dly_r), .R(1'b0)); LUT3 #( .INIT(8'h02)) \odd_cwl.phy_cas_n[1]_i_1 (.I0(\odd_cwl.phy_cas_n_reg[1]_0 ), .I1(\odd_cwl.phy_ras_n[1]_i_2_n_0 ), .I2(\cnt_init_mr_r_reg[1]_0 ), .O(\odd_cwl.phy_cas_n[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \odd_cwl.phy_cas_n_reg[1] (.C(CLK), .CE(1'b1), .D(\odd_cwl.phy_cas_n[1]_i_1_n_0 ), .Q(phy_cas_n), .R(1'b0)); LUT2 #( .INIT(4'h1)) \odd_cwl.phy_ras_n[1]_i_1 (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ), .I1(\odd_cwl.phy_ras_n[1]_i_2_n_0 ), .O(\odd_cwl.phy_ras_n[1]_i_1_n_0 )); LUT6 #( .INIT(64'hEEEEEEEEEEEEEEEF)) \odd_cwl.phy_ras_n[1]_i_2 (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ), .I1(reg_ctrl_cnt_r), .I2(Q[5]), .I3(Q[4]), .I4(Q[3]), .I5(read_calib_reg_0), .O(\odd_cwl.phy_ras_n[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \odd_cwl.phy_ras_n_reg[1] (.C(CLK), .CE(1'b1), .D(\odd_cwl.phy_ras_n[1]_i_1_n_0 ), .Q(phy_ras_n), .R(1'b0)); LUT3 #( .INIT(8'h04)) \odd_cwl.phy_we_n[1]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\odd_cwl.phy_ras_n[1]_i_2_n_0 ), .O(\odd_cwl.phy_we_n[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \odd_cwl.phy_we_n_reg[1] (.C(CLK), .CE(1'b1), .D(\odd_cwl.phy_we_n[1]_i_1_n_0 ), .Q(phy_we_n), .R(1'b0)); LUT6 #( .INIT(64'h000000000000000E)) \one_rank.stg1_wr_done_i_1 (.I0(\one_rank.stg1_wr_done_reg_0 ), .I1(stg1_wr_done), .I2(\reg_ctrl_cnt_r_reg[3]_0 ), .I3(rdlvl_last_byte_done), .I4(prbs_rdlvl_done_pulse), .I5(complex_byte_rd_done), .O(\one_rank.stg1_wr_done_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \one_rank.stg1_wr_done_i_2 (.I0(Q[1]), .I1(Q[3]), .I2(Q[0]), .I3(Q[5]), .I4(Q[4]), .I5(\init_state_r[4]_i_5_n_0 ), .O(stg1_wr_done)); FDRE #( .INIT(1'b0)) \one_rank.stg1_wr_done_reg (.C(CLK), .CE(1'b1), .D(\one_rank.stg1_wr_done_i_1_n_0 ), .Q(\one_rank.stg1_wr_done_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000000E0E0E)) \one_rank_complex.complex_wr_done_i_1 (.I0(complex_wr_done), .I1(\one_rank_complex.complex_wr_done_i_2_n_0 ), .I2(\one_rank_complex.complex_wr_done_i_3_n_0 ), .I3(prbs_rdlvl_done_reg), .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I5(\one_rank_complex.complex_wr_done_i_4_n_0 ), .O(\one_rank_complex.complex_wr_done_i_1_n_0 )); LUT6 #( .INIT(64'h0000800000000000)) \one_rank_complex.complex_wr_done_i_2 (.I0(\one_rank_complex.complex_wr_done_i_5_n_0 ), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[3]), .I3(complex_row1_wr_done), .I4(complex_wait_cnt_reg__0[1]), .I5(complex_wait_cnt_reg__0[0]), .O(\one_rank_complex.complex_wr_done_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000080000)) \one_rank_complex.complex_wr_done_i_3 (.I0(complex_byte_rd_done), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[0]), .I4(Q[2]), .I5(complex_oclkdelay_calib_start_int_i_2_n_0), .O(\one_rank_complex.complex_wr_done_i_3_n_0 )); LUT3 #( .INIT(8'hFE)) \one_rank_complex.complex_wr_done_i_4 (.I0(\reg_ctrl_cnt_r_reg[3]_0 ), .I1(rdlvl_last_byte_done), .I2(prbs_rdlvl_done_pulse), .O(\one_rank_complex.complex_wr_done_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair513" *) LUT5 #( .INIT(32'h00001800)) \one_rank_complex.complex_wr_done_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[2]), .I4(complex_oclkdelay_calib_start_int_i_2_n_0), .O(\one_rank_complex.complex_wr_done_i_5_n_0 )); FDRE #( .INIT(1'b0)) \one_rank_complex.complex_wr_done_reg (.C(CLK), .CE(1'b1), .D(\one_rank_complex.complex_wr_done_i_1_n_0 ), .Q(complex_wr_done), .R(1'b0)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [231]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [7]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [239]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [7]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [247]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [7]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [254]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [15]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [199]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [6]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [207]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [6]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [215]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [6]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [222]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [14]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [167]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [5]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [175]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [5]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [183]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [5]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [190]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [13]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [5])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_13__2 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [3]), .I4(\my_empty_reg[1]_1 ), .O(D5[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [135]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [4]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [143]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [4]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [151]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [4]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [158]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [12]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [4])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_14__1 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [2]), .I4(\my_empty_reg[1]_1 ), .O(D5[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [103]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [3]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [111]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [3]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [119]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [3]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [126]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [11]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_14__6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [3]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [3])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_15__0 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [1]), .I4(\my_empty_reg[1]_1 ), .O(D5[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__1 (.I0(mc_address[26]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [2]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [71]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [2]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [79]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [2]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [87]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [2]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [94]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [10]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [2])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_16__0 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [0]), .I4(\my_empty_reg[1]_1 ), .O(D5[0])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_16__1 (.I0(mc_we_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_we_n), .I3(mem_out[1]), .I4(\my_empty_reg[1]_0 ), .O(D1)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__2 (.I0(mc_address[15]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [1]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [39]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [1]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [47]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [1]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [55]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [1]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [62]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [9]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__0 (.I0(mc_address[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [0]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [7]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [0]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [15]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [0]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [23]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [0]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [30]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [8]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [0])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_18__2 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_cas_n), .I3(\rd_ptr_reg[3] [0]), .I4(\my_empty_reg[1] ), .O(D2)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [230]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [15]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [238]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [15]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [246]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [15]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [253]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [23]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [7])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_19__1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [7]), .I4(\my_empty_reg[1]_1 ), .O(D6[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [198]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [14]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [206]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [14]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [214]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [14]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [221]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [22]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [6])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_20__1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [6]), .I4(\my_empty_reg[1]_1 ), .O(D6[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [166]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [13]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [174]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [13]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [182]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [13]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [189]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [21]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [5])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_21__1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [5]), .I4(\my_empty_reg[1]_1 ), .O(D6[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [134]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [12]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [142]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [12]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [150]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [12]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [157]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [20]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [4])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_22__0 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [4]), .I4(\my_empty_reg[1]_1 ), .O(D6[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [102]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [11]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [110]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [11]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [118]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [11]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [125]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [19]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_22__5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [7]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__1 (.I0(mc_address[27]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [6]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [70]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [10]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [78]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [10]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [86]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [10]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [93]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [18]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__1 (.I0(mc_address[16]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [5]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [38]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [9]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [46]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [9]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [54]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [9]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [61]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [17]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__0 (.I0(mc_address[6]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [4]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [6]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [8]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [14]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [8]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [22]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [8]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [29]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [16]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [0])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_26__1 (.I0(mc_ras_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_ras_n), .I3(\rd_ptr_reg[3] [1]), .I4(\my_empty_reg[1] ), .O(D3)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [229]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [23]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [237]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [23]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [245]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [23]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [252]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [31]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [197]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [22]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [205]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [22]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [213]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [22]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [220]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [30]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [165]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [21]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [173]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [21]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [181]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [21]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [188]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [29]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [133]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [20]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [141]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [20]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [149]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [20]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [156]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [28]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_2__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [255]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [7]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [101]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [19]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [109]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [19]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [117]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [19]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [124]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [27]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_30__5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [11]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__0 (.I0(mc_address[28]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [10]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [69]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [18]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [77]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [18]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [85]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [18]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [92]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [26]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32 (.I0(mc_address[17]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [9]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [37]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [17]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [45]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [17]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [53]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [17]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [60]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [25]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_32__4 (.I0(phy_bank[9]), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3] [5]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33 (.I0(mc_address[7]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [8]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__0 (.I0(mc_bank[6]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [4]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [5]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [16]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [13]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [16]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [21]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [16]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [28]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [24]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__0 (.I0(mc_bank[3]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [3]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [228]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [31]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [236]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [31]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [244]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [31]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [251]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [39]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__0 (.I0(mc_bank[0]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [2]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [196]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [30]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [204]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [30]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [212]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [30]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [219]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [38]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [164]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [29]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [172]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [29]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [180]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [29]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [187]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [37]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [5])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_36__4 (.I0(phy_bank[11]), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3] [13]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__0 (.I0(mc_bank[8]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [12]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [132]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [28]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [140]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [28]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [148]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [28]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [155]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [36]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38 (.I0(mc_bank[5]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [11]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [100]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [27]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [108]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [27]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [116]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [27]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [123]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [35]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_38__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [15]), .I3(\my_empty_reg[1]_2 ), .O(D4[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39 (.I0(mc_address[29]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [14]), .I4(\my_empty_reg[1]_2 ), .O(D4[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__0 (.I0(mc_bank[2]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [10]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [68]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [26]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [76]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [26]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [84]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [26]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [91]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [34]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_3__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [223]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [6]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40 (.I0(mc_address[18]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [13]), .I4(\my_empty_reg[1]_2 ), .O(D4[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [36]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [25]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [44]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [25]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [52]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [25]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [59]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [33]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [1])); (* SOFT_HLUTNM = "soft_lutpair551" *) LUT4 #( .INIT(16'hEEF0)) out_fifo_i_40__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [9]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41 (.I0(mc_address[8]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [12]), .I4(\my_empty_reg[1]_2 ), .O(D4[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__0 (.I0(mc_address[25]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [8]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [4]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [24]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [12]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [24]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [20]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [24]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [27]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [32]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__0 (.I0(mc_address[14]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [7]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [227]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [39]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [235]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [39]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [243]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [39]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [250]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [47]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__0 (.I0(mc_address[4]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [6]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [195]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [38]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [203]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [38]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [211]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [38]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [218]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [46]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [163]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [37]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [171]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [37]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [179]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [37]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [186]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [45]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [5])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_44__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [21]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__0 (.I0(mc_address[21]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [20]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [131]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [36]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [139]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [36]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [147]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [36]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [154]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [44]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [19]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [99]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [35]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [107]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [35]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [115]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [35]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [122]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [43]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [3])); (* SOFT_HLUTNM = "soft_lutpair555" *) LUT4 #( .INIT(16'hEEF0)) out_fifo_i_46__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [19]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47 (.I0(mc_address[0]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [18]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__0 (.I0(mc_address[30]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [18]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [67]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [34]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [75]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [34]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [83]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [34]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [90]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [42]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48 (.I0(mc_address[19]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [17]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [35]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [33]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [43]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [33]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [51]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [33]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [58]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [41]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_48__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [17]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49 (.I0(mc_address[9]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [16]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__0 (.I0(mc_address[22]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [16]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [3]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [32]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [11]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [32]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [19]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [32]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [26]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [40]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_4__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [191]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [5]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__0 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [15]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [226]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [47]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [234]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [47]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [242]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [47]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [249]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [55]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__0 (.I0(mc_address[1]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [14]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [194]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [46]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [202]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [46]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [210]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [46]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [217]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [54]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [162]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [45]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [170]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [45]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [178]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [45]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [185]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [53]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [130]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [44]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [138]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [44]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [146]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [44]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [153]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [52]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [98]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [43]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [106]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [43]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [114]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [43]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [121]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [51]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_54__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3]_1 [23]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__0 (.I0(mc_address[31]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [22]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [66]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [42]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [74]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [42]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [82]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [42]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [89]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [50]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56 (.I0(mc_address[20]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [21]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [34]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [41]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [42]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [41]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [50]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [41]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [57]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [49]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_56__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [25]), .I3(\my_empty_reg[1] ), .O(D7[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57 (.I0(mc_address[10]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [20]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__0 (.I0(mc_address[23]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [24]), .I4(\my_empty_reg[1] ), .O(D7[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [2]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [40]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [10]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [40]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [18]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [40]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [25]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [48]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__0 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [23]), .I4(\my_empty_reg[1] ), .O(D7[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [225]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [55]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [233]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [55]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [241]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [55]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [248]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [63]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__0 (.I0(mc_address[2]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [22]), .I4(\my_empty_reg[1] ), .O(D7[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [193]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [54]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [201]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [54]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [209]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [54]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [216]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [62]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_5__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [159]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [4]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [161]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [53]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [169]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [53]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [177]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [53]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [184]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [61]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [129]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [52]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [137]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [52]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [145]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [52]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [152]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [60]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [97]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [51]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [105]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [51]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [113]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [51]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [120]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [59]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_62__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3]_1 [27]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__0 (.I0(mc_address[32]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [26]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [65]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [50]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [73]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [50]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [81]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [50]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [88]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [58]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [25]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [33]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [49]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [41]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [49]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [49]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [49]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [56]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [57]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_64__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [29]), .I3(\my_empty_reg[1] ), .O(D8[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65 (.I0(mc_address[11]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [24]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__0 (.I0(mc_address[24]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [28]), .I4(\my_empty_reg[1] ), .O(D8[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [1]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [48]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [9]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [48]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [17]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [48]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [24]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [56]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__1 (.I0(mc_address[13]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [27]), .I4(\my_empty_reg[1] ), .O(D8[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [224]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [63]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [232]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [63]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [240]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [63]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__1 (.I0(mc_address[3]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [26]), .I4(\my_empty_reg[1] ), .O(D8[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [192]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [62]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [200]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [62]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [208]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [62]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_68__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [160]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [61]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_68__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [168]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [61]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_68__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [176]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [61]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_69__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [128]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [60]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_69__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [136]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [60]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_69__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [144]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [60]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_6__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [127]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [3]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_70__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [96]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [59]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_70__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [104]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [59]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_70__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [112]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [59]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_70__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3]_1 [31]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_70__4 (.I0(phy_bank[10]), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3] [33]), .I3(\my_empty_reg[1] ), .O(D9[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__0 (.I0(mc_address[33]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [30]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__1 (.I0(mc_bank[7]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [32]), .I4(\my_empty_reg[1] ), .O(D9[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [64]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [58]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [72]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [58]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [80]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [58]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__0 (.I0(mc_ras_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [29]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__1 (.I0(mc_bank[4]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [31]), .I4(\my_empty_reg[1] ), .O(D9[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [32]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [57]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [40]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [57]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [48]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [57]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__0 (.I0(mc_address[12]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [28]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__1 (.I0(mc_bank[1]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [30]), .I4(\my_empty_reg[1] ), .O(D9[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [0]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [56]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [8]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [56]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [16]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [56]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_7__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [95]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [2]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [2])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_8__5 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_cs_n), .I3(mem_out[0]), .I4(\my_empty_reg[1]_0 ), .O(D0)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_8__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [63]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [1]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_9__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [31]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [0]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [0])); (* SOFT_HLUTNM = "soft_lutpair588" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[0]_i_1 (.I0(mc_cmd[0]), .I1(calib_cmd[0]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [0])); (* SOFT_HLUTNM = "soft_lutpair589" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[17]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[0] ), .I1(calib_data_offset_0[0]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [3])); (* SOFT_HLUTNM = "soft_lutpair590" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[18]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[1] ), .I1(calib_data_offset_0[1]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [4])); (* SOFT_HLUTNM = "soft_lutpair591" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[19]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[2] ), .I1(calib_data_offset_0[2]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [5])); (* SOFT_HLUTNM = "soft_lutpair585" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[1]_i_1 (.I0(mc_cmd[1]), .I1(calib_cmd[1]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [1])); (* SOFT_HLUTNM = "soft_lutpair590" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[20]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ), .I1(calib_data_offset_0[3]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [6])); (* SOFT_HLUTNM = "soft_lutpair593" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[21]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[4] ), .I1(calib_data_offset_0[4]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [7])); (* SOFT_HLUTNM = "soft_lutpair591" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[22]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] ), .I1(calib_data_offset_0[5]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [8])); (* SOFT_HLUTNM = "soft_lutpair589" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[2]_i_1 (.I0(mc_cas_n), .I1(calib_cmd[2]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [2])); FDCE #( .INIT(1'b0)) phy_reset_n_reg (.C(CLK), .CE(1'b1), .CLR(rstdiv0_sync_r1_reg_rep__11), .D(cnt_pwron_reset_done_r), .Q(phy_reset_n)); FDRE #( .INIT(1'b0)) pi_calib_done_r1_reg (.C(CLK), .CE(1'b1), .D(pi_calib_done_r), .Q(pi_calib_done), .R(1'b0)); LUT2 #( .INIT(4'hE)) pi_calib_done_r_i_1 (.I0(pi_calib_rank_done_r), .I1(pi_calib_done_r), .O(pi_calib_done_r_i_1_n_0)); FDRE #( .INIT(1'b0)) pi_calib_done_r_reg (.C(CLK), .CE(1'b1), .D(pi_calib_done_r_i_1_n_0), .Q(pi_calib_done_r), .R(rstdiv0_sync_r1_reg_rep__11)); LUT2 #( .INIT(4'h2)) pi_calib_rank_done_r_i_1 (.I0(pi_phase_locked_all_r3), .I1(pi_phase_locked_all_r4), .O(init_next_state1100_out)); FDRE #( .INIT(1'b0)) pi_calib_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(init_next_state1100_out), .Q(pi_calib_rank_done_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'hE)) \pi_dqs_found_all_bank[1]_i_2 (.I0(dqs_found_start_r_reg), .I1(\pi_dqs_found_all_bank_reg[1]_0 ), .O(\pi_dqs_found_all_bank_reg[1] )); FDRE #( .INIT(1'b0)) pi_dqs_found_done_r1_reg (.C(CLK), .CE(1'b1), .D(dqs_found_done_r_reg), .Q(pi_dqs_found_done_r1), .R(rstdiv0_sync_r1_reg_rep__11)); LUT5 #( .INIT(32'h000000AE)) pi_dqs_found_start_i_1 (.I0(dqs_found_start_r_reg), .I1(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ), .I2(dqs_found_done_r_reg), .I3(wrlvl_byte_redo), .I4(rstdiv0_sync_r1_reg_rep__23), .O(pi_dqs_found_start_i_1_n_0)); FDRE #( .INIT(1'b0)) pi_dqs_found_start_reg (.C(CLK), .CE(1'b1), .D(pi_dqs_found_start_i_1_n_0), .Q(dqs_found_start_r_reg), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) pi_phase_locked_all_r1_reg (.C(CLK), .CE(1'b1), .D(A_rst_primitives_reg), .Q(pi_phase_locked_all_r1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) pi_phase_locked_all_r2_reg (.C(CLK), .CE(1'b1), .D(pi_phase_locked_all_r1), .Q(pi_phase_locked_all_r2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) pi_phase_locked_all_r3_reg (.C(CLK), .CE(1'b1), .D(pi_phase_locked_all_r2), .Q(pi_phase_locked_all_r3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) pi_phase_locked_all_r4_reg (.C(CLK), .CE(1'b1), .D(pi_phase_locked_all_r3), .Q(pi_phase_locked_all_r4), .R(1'b0)); LUT6 #( .INIT(64'h00000000FFFFEEFE)) prbs_gen_clk_en_i_1 (.I0(prbs_gen_clk_en), .I1(prbs_gen_clk_en_i_2_n_0), .I2(prbs_rdlvl_start_r_reg), .I3(prbs_gen_clk_en_i_3_n_0), .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I5(prbs_gen_clk_en040_out), .O(prbs_gen_clk_en_i_1_n_0)); LUT6 #( .INIT(64'h20AAAAAA20AA20AA)) prbs_gen_clk_en_i_2 (.I0(rdlvl_stg1_done_r1), .I1(prbs_gen_clk_en_i_5_n_0), .I2(\complex_num_writes[3]_i_4_n_0 ), .I3(phy_if_empty_r_reg), .I4(\stg1_wr_rd_cnt[4]_i_6_n_0 ), .I5(cnt_cmd_done_r_i_1_n_0), .O(prbs_gen_clk_en_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFEF)) prbs_gen_clk_en_i_3 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[4]), .I2(Q[3]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(prbs_gen_clk_en_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair549" *) LUT4 #( .INIT(16'hEEEF)) prbs_gen_clk_en_i_4 (.I0(prbs_rdlvl_done_reg), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(wr_victim_inc_i_2_n_0), .I3(\one_rank.stg1_wr_done_reg_0 ), .O(prbs_gen_clk_en040_out)); (* SOFT_HLUTNM = "soft_lutpair505" *) LUT4 #( .INIT(16'hFF7F)) prbs_gen_clk_en_i_5 (.I0(complex_wait_cnt_reg__0[2]), .I1(complex_wait_cnt_reg__0[3]), .I2(complex_wait_cnt_reg__0[1]), .I3(complex_wait_cnt_reg__0[0]), .O(prbs_gen_clk_en_i_5_n_0)); FDRE #( .INIT(1'b0)) prbs_gen_clk_en_reg (.C(CLK), .CE(1'b1), .D(prbs_gen_clk_en_i_1_n_0), .Q(prbs_gen_clk_en), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000002)) prbs_gen_oclk_clk_en_i_1 (.I0(prbs_gen_oclk_clk_en_i_2_n_0), .I1(prbs_gen_oclk_clk_en_i_3_n_0), .I2(\one_rank_complex.complex_wr_done_i_3_n_0 ), .I3(prbs_gen_oclk_clk_en_i_4_n_0), .I4(prbs_gen_oclk_clk_en_i_5_n_0), .I5(prbs_gen_clk_en040_out), .O(prbs_gen_oclk_clk_en_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFAE)) prbs_gen_oclk_clk_en_i_2 (.I0(prbs_gen_oclk_clk_en_i_6_n_0), .I1(prbs_rdlvl_done_r1), .I2(phy_if_empty_r_reg), .I3(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I4(prbs_gen_oclk_clk_en_i_7_n_0), .I5(prbs_gen_oclk_clk_en), .O(prbs_gen_oclk_clk_en_i_2_n_0)); LUT6 #( .INIT(64'h0000000000002000)) prbs_gen_oclk_clk_en_i_3 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(prbs_rdlvl_start_i_2_n_0), .O(prbs_gen_oclk_clk_en_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000008)) prbs_gen_oclk_clk_en_i_4 (.I0(prbs_gen_oclk_clk_en_i_8_n_0), .I1(\complex_num_writes_reg_n_0_[0] ), .I2(\complex_num_writes_reg_n_0_[1] ), .I3(\complex_num_writes_reg_n_0_[2] ), .I4(\complex_num_writes_reg_n_0_[4] ), .I5(\complex_num_writes_reg_n_0_[3] ), .O(prbs_gen_oclk_clk_en_i_4_n_0)); LUT6 #( .INIT(64'hAABAAAAAFFFFFFFF)) prbs_gen_oclk_clk_en_i_5 (.I0(prbs_gen_oclk_clk_en_i_9_n_0), .I1(complex_num_writes_dec_reg__0[0]), .I2(complex_num_writes_dec_reg__0[1]), .I3(\complex_num_writes_dec[4]_i_5_n_0 ), .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I5(complex_ocal_wr_start), .O(prbs_gen_oclk_clk_en_i_5_n_0)); LUT6 #( .INIT(64'h0001101100010001)) prbs_gen_oclk_clk_en_i_6 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(\init_state_r[4]_i_5_n_0 ), .I2(Q[1]), .I3(prbs_gen_clk_en_i_5_n_0), .I4(Q[0]), .I5(complex_oclk_calib_resume), .O(prbs_gen_oclk_clk_en_i_6_n_0)); LUT5 #( .INIT(32'h00000004)) prbs_gen_oclk_clk_en_i_7 (.I0(prbs_gen_clk_en_i_5_n_0), .I1(\complex_num_writes[3]_i_4_n_0 ), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(complex_row1_wr_done), .I4(complex_ocal_num_samples_done_r), .O(prbs_gen_oclk_clk_en_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair502" *) LUT4 #( .INIT(16'h8000)) prbs_gen_oclk_clk_en_i_8 (.I0(complex_wait_cnt_reg__0[0]), .I1(complex_wait_cnt_reg__0[1]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[3]), .O(prbs_gen_oclk_clk_en_i_8_n_0)); LUT6 #( .INIT(64'h0000D00000000000)) prbs_gen_oclk_clk_en_i_9 (.I0(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .I1(complex_oclkdelay_calib_start_int_reg_0), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ), .I3(init_state_r1[2]), .I4(init_state_r1[6]), .I5(init_state_r1[1]), .O(prbs_gen_oclk_clk_en_i_9_n_0)); FDRE #( .INIT(1'b0)) prbs_gen_oclk_clk_en_reg (.C(CLK), .CE(1'b1), .D(prbs_gen_oclk_clk_en_i_1_n_0), .Q(prbs_gen_oclk_clk_en), .R(1'b0)); FDRE #( .INIT(1'b0)) prbs_last_byte_done_r_reg (.C(CLK), .CE(1'b1), .D(prbs_last_byte_done), .Q(prbs_last_byte_done_r), .R(1'b0)); FDRE #( .INIT(1'b0)) prbs_rdlvl_done_pulse_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_pulse0), .Q(prbs_rdlvl_done_pulse), .R(1'b0)); FDRE #( .INIT(1'b0)) prbs_rdlvl_done_r1_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_reg_rep), .Q(prbs_rdlvl_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) prbs_rdlvl_done_r2_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_r1), .Q(prbs_rdlvl_done_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) prbs_rdlvl_done_r3_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_r2), .Q(prbs_rdlvl_done_r3), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000020)) prbs_rdlvl_start_i_1 (.I0(rdlvl_stg1_done_int_reg), .I1(prbs_rdlvl_done_reg), .I2(dqs_found_done_r_reg), .I3(prbs_rdlvl_start_i_2_n_0), .I4(prbs_rdlvl_start_i_3_n_0), .I5(prbs_rdlvl_start_r_reg), .O(prbs_rdlvl_start_i_1_n_0)); LUT2 #( .INIT(4'h7)) prbs_rdlvl_start_i_2 (.I0(Q[0]), .I1(Q[1]), .O(prbs_rdlvl_start_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair479" *) LUT5 #( .INIT(32'hFFFEFFFF)) prbs_rdlvl_start_i_3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[5]), .O(prbs_rdlvl_start_i_3_n_0)); FDRE #( .INIT(1'b0)) prbs_rdlvl_start_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_start_i_1_n_0), .Q(prbs_rdlvl_start_r_reg), .R(rstdiv0_sync_r1_reg_rep__11)); LUT2 #( .INIT(4'h2)) \prbs_state_r[4]_i_10 (.I0(prbs_rdlvl_start_r_reg), .I1(prbs_rdlvl_start_r), .O(new_cnt_dqs_r_reg)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 " *) SRL16E #( .INIT(16'h0000)) \prech_done_dly_r_reg[15]_srl16 (.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(prech_done_pre), .Q(\prech_done_dly_r_reg[15]_srl16_n_0 )); LUT2 #( .INIT(4'h2)) \prech_done_dly_r_reg[15]_srl16_i_1 (.I0(prech_pending_r_reg_1), .I1(prech_pending_r_reg_0), .O(prech_done_pre)); FDRE #( .INIT(1'b0)) prech_done_r2_reg (.C(CLK), .CE(1'b1), .D(prech_done), .Q(prech_done_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) prech_done_r3_reg (.C(CLK), .CE(1'b1), .D(prech_done_r2), .Q(prech_done_r3), .R(1'b0)); FDRE #( .INIT(1'b0)) prech_done_reg (.C(CLK), .CE(1'b1), .D(\prech_done_dly_r_reg[15]_srl16_n_0 ), .Q(prech_done), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAA8A8A8A8A8A)) prech_pending_r_i_2 (.I0(prech_pending_r), .I1(prech_pending_r_i_3_n_0), .I2(prech_pending_r_i_4_n_0), .I3(\complex_row_cnt_ocal[7]_i_6_n_0 ), .I4(prech_pending_r_i_5_n_0), .I5(prbs_last_byte_done_r), .O(prech_pending_r_reg_1)); LUT6 #( .INIT(64'hFFFFFFFFFF5D0000)) prech_pending_r_i_3 (.I0(prech_pending_r_i_6_n_0), .I1(\wrcal_reads[7]_i_6_n_0 ), .I2(first_wrcal_pat_r_i_2_n_0), .I3(prech_pending_r_i_7_n_0), .I4(cnt_cmd_done_r), .I5(prech_pending_r_i_8_n_0), .O(prech_pending_r_i_3_n_0)); LUT6 #( .INIT(64'h0000FDFFFDFFFDFF)) prech_pending_r_i_4 (.I0(dqs_found_prech_req), .I1(\init_state_r[4]_i_5_n_0 ), .I2(rdlvl_stg1_start_int_i_2_n_0), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I4(\num_refresh[3]_i_5_n_0 ), .I5(complex_oclkdelay_calib_start_r1), .O(prech_pending_r_i_4_n_0)); LUT6 #( .INIT(64'h0000000000000008)) prech_pending_r_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(cnt_cmd_done_r), .I2(\init_state_r[4]_i_5_n_0 ), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(prech_pending_r_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) prech_pending_r_i_6 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(rdlvl_start_pre_reg_0), .I3(oclkdelay_calib_done_r_reg_2), .I4(wrlvl_final_mux), .I5(complex_oclkdelay_calib_start_int_reg_0), .O(prech_pending_r_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair489" *) LUT5 #( .INIT(32'h00000080)) prech_pending_r_i_7 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(read_calib_i_2_n_0), .O(prech_pending_r_i_7_n_0)); LUT6 #( .INIT(64'hFFFFFFFEFFFEFFFE)) prech_pending_r_i_8 (.I0(oclkdelay_calib_start_pre), .I1(prech_pending_r_i_9_n_0), .I2(stg1_wr_done), .I3(\calib_cmd[2]_i_8_n_0 ), .I4(prech_pending_r_i_5_n_0), .I5(rdlvl_last_byte_done_r), .O(prech_pending_r_i_8_n_0)); LUT6 #( .INIT(64'h0000000000040000)) prech_pending_r_i_9 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(prech_pending_r_i_9_n_0)); FDRE #( .INIT(1'b0)) prech_pending_r_reg (.C(CLK), .CE(1'b1), .D(prech_req_posedge_r_reg_0), .Q(prech_pending_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'h1)) prech_req_posedge_r_i_1 (.I0(prech_req_r), .I1(prech_req_posedge_r_i_2_n_0), .O(prech_req_posedge_r0)); LUT6 #( .INIT(64'h000000000000000B)) prech_req_posedge_r_i_2 (.I0(\back_to_back_reads_4_1.num_reads_reg[1]_0 ), .I1(dqs_found_prech_req), .I2(prbs_rdlvl_prech_req_reg), .I3(complex_ocal_ref_req), .I4(wrcal_prech_req), .I5(rdlvl_prech_req), .O(prech_req_posedge_r_i_2_n_0)); FDRE #( .INIT(1'b0)) prech_req_posedge_r_reg (.C(CLK), .CE(1'b1), .D(prech_req_posedge_r0), .Q(prech_pending_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFEF)) prech_req_r_i_3 (.I0(complex_oclkdelay_calib_start_int_reg_0), .I1(Q[4]), .I2(Q[3]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\back_to_back_reads_4_1.num_reads_reg[1]_0 )); FDRE #( .INIT(1'b0)) prech_req_r_reg (.C(CLK), .CE(1'b1), .D(prech_req), .Q(prech_req_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT5 #( .INIT(32'h80000000)) pwron_ce_r_i_2 (.I0(cnt_pwron_ce_r_reg__0[9]), .I1(cnt_pwron_ce_r_reg__0[7]), .I2(pwron_ce_r_i_3_n_0), .I3(cnt_pwron_ce_r_reg__0[6]), .I4(cnt_pwron_ce_r_reg__0[8]), .O(pwron_ce_r_i_2_n_0)); LUT6 #( .INIT(64'h8000000000000000)) pwron_ce_r_i_3 (.I0(cnt_pwron_ce_r_reg__0[5]), .I1(cnt_pwron_ce_r_reg__0[3]), .I2(cnt_pwron_ce_r_reg__0[1]), .I3(cnt_pwron_ce_r_reg__0[0]), .I4(cnt_pwron_ce_r_reg__0[2]), .I5(cnt_pwron_ce_r_reg__0[4]), .O(pwron_ce_r_i_3_n_0)); FDRE #( .INIT(1'b0)) pwron_ce_r_reg (.C(CLK), .CE(1'b1), .D(pwron_ce_r_i_2_n_0), .Q(pwron_ce_r), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h0000BBB0FFF0FFF0)) \rd_addr[7]_i_2 (.I0(prbs_rdlvl_done_reg_rep), .I1(prbs_rdlvl_start_r_reg), .I2(prbs_gen_clk_en), .I3(prbs_gen_oclk_clk_en), .I4(complex_wr_done), .I5(phy_if_empty_r_reg), .O(\rd_addr_reg[0] )); LUT6 #( .INIT(64'h959595AAAAAAAAAA)) \rd_addr[7]_i_7 (.I0(\rd_addr_reg[3] ), .I1(phy_if_empty_r_reg), .I2(complex_wr_done), .I3(prbs_gen_oclk_clk_en), .I4(prbs_gen_clk_en), .I5(prbs_rdlvl_done_reg_rep), .O(\rd_addr_reg_rep[7] )); FDRE #( .INIT(1'b0)) rdlvl_last_byte_done_r_reg (.C(CLK), .CE(1'b1), .D(rdlvl_last_byte_done), .Q(rdlvl_last_byte_done_r), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 " *) SRL16E #( .INIT(16'h0000)) \rdlvl_start_dly0_r_reg[13]_srl14 (.A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(rdlvl_start_pre), .Q(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 )); FDRE #( .INIT(1'b0)) \rdlvl_start_dly0_r_reg[14] (.C(CLK), .CE(1'b1), .D(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ), .Q(rdlvl_start_dly0_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair582" *) LUT3 #( .INIT(8'hFB)) rdlvl_start_pre_i_2 (.I0(Q[4]), .I1(Q[3]), .I2(Q[5]), .O(rdlvl_start_pre_reg_0)); FDRE #( .INIT(1'b0)) rdlvl_start_pre_reg (.C(CLK), .CE(1'b1), .D(\init_state_r_reg[0]_1 ), .Q(rdlvl_start_pre), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) rdlvl_stg1_done_r1_reg (.C(CLK), .CE(1'b1), .D(rdlvl_stg1_done_int_reg), .Q(rdlvl_stg1_done_r1), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000080)) rdlvl_stg1_start_int_i_1 (.I0(dqs_found_done_r_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I2(cnt_cmd_done_r), .I3(\init_state_r[4]_i_5_n_0 ), .I4(rdlvl_stg1_start_int_i_2_n_0), .I5(rdlvl_stg1_start_int), .O(rdlvl_stg1_start_int_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair569" *) LUT3 #( .INIT(8'hFE)) rdlvl_stg1_start_int_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .O(rdlvl_stg1_start_int_i_2_n_0)); FDRE #( .INIT(1'b0)) rdlvl_stg1_start_int_reg (.C(CLK), .CE(1'b1), .D(rdlvl_stg1_start_int_i_1_n_0), .Q(rdlvl_stg1_start_int), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) rdlvl_stg1_start_reg (.C(CLK), .CE(1'b1), .D(\rdlvl_start_dly0_r_reg[14]_0 ), .Q(rdlvl_stg1_start_r_reg), .R(rstdiv0_sync_r1_reg_rep__12)); LUT5 #( .INIT(32'h000000AB)) read_calib_i_1 (.I0(phy_read_calib), .I1(read_calib_i_2_n_0), .I2(read_calib_reg_0), .I3(pi_calib_done), .I4(rstdiv0_sync_r1_reg_rep__23), .O(read_calib_i_1_n_0)); LUT3 #( .INIT(8'hFB)) read_calib_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .O(read_calib_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair504" *) LUT4 #( .INIT(16'hFDFF)) read_calib_i_3 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[0]), .I3(Q[2]), .O(read_calib_reg_0)); FDRE #( .INIT(1'b0)) read_calib_reg (.C(CLK), .CE(1'b1), .D(read_calib_i_1_n_0), .Q(phy_read_calib), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair607" *) LUT1 #( .INIT(2'h1)) \reg_ctrl_cnt_r[0]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[0]), .O(\reg_ctrl_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair607" *) LUT2 #( .INIT(4'h6)) \reg_ctrl_cnt_r[1]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[0]), .I1(reg_ctrl_cnt_r_reg__0[1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair583" *) LUT3 #( .INIT(8'h6A)) \reg_ctrl_cnt_r[2]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[2]), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r_reg__0[0]), .O(p_0_in__2[2])); LUT6 #( .INIT(64'h0000000000000001)) \reg_ctrl_cnt_r[3]_i_1 (.I0(Q[1]), .I1(Q[4]), .I2(Q[5]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[3]), .I5(Q[0]), .O(\reg_ctrl_cnt_r_reg[3]_0 )); LUT6 #( .INIT(64'h0000000001000000)) \reg_ctrl_cnt_r[3]_i_2 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(Q[4]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[3]), .I5(Q[5]), .O(reg_ctrl_cnt_r)); (* SOFT_HLUTNM = "soft_lutpair559" *) LUT4 #( .INIT(16'h6AAA)) \reg_ctrl_cnt_r[3]_i_3 (.I0(reg_ctrl_cnt_r_reg__0[3]), .I1(reg_ctrl_cnt_r_reg__0[2]), .I2(reg_ctrl_cnt_r_reg__0[0]), .I3(reg_ctrl_cnt_r_reg__0[1]), .O(p_0_in__2[3])); FDRE #( .INIT(1'b0)) \reg_ctrl_cnt_r_reg[0] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(\reg_ctrl_cnt_r[0]_i_1_n_0 ), .Q(reg_ctrl_cnt_r_reg__0[0]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); FDRE #( .INIT(1'b0)) \reg_ctrl_cnt_r_reg[1] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(p_0_in__2[1]), .Q(reg_ctrl_cnt_r_reg__0[1]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); FDRE #( .INIT(1'b0)) \reg_ctrl_cnt_r_reg[2] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(p_0_in__2[2]), .Q(reg_ctrl_cnt_r_reg__0[2]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); FDRE #( .INIT(1'b0)) \reg_ctrl_cnt_r_reg[3] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(p_0_in__2[3]), .Q(reg_ctrl_cnt_r_reg__0[3]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); LUT3 #( .INIT(8'h02)) reset_if_i_1 (.I0(reset_if_i_2_n_0), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(reset_if_r9), .O(reset_if_reg)); LUT5 #( .INIT(32'hFFFF22F2)) reset_if_i_2 (.I0(rdlvl_stg1_done_int_reg), .I1(rdlvl_stg1_done_r1), .I2(prbs_rdlvl_done_reg), .I3(prbs_rdlvl_done_r1), .I4(reset_if), .O(reset_if_i_2_n_0)); FDRE #( .INIT(1'b0)) reset_rd_addr_r1_reg (.C(CLK), .CE(1'b1), .D(reset_rd_addr0), .Q(reset_rd_addr_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair515" *) LUT2 #( .INIT(4'h1)) \row_cnt_victim_rotate.complex_row_cnt[0]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 )); LUT4 #( .INIT(16'h8BB8)) \row_cnt_victim_rotate.complex_row_cnt[1]_i_1 (.I0(\rd_victim_sel_reg[0] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .O(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair515" *) LUT5 #( .INIT(32'h8BB8B8B8)) \row_cnt_victim_rotate.complex_row_cnt[2]_i_1 (.I0(\rd_victim_sel_reg[1] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .O(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h8BB8B8B8B8B8B8B8)) \row_cnt_victim_rotate.complex_row_cnt[3]_i_1 (.I0(\rd_victim_sel_reg[2] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .O(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'hEEEEFFEFAAAAAAAA)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ), .I1(reset_rd_addr_r1), .I2(complex_sample_cnt_inc_r2), .I3(complex_victim_inc_reg), .I4(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_10 (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I1(\complex_row_cnt_ocal[7]_i_7_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 )); LUT3 #( .INIT(8'h0E)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_2 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I1(\one_rank.stg1_wr_done_reg_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ), .O(complex_row_cnt)); LUT6 #( .INIT(64'h000000007FFF8000)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_3 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 )); LUT4 #( .INIT(16'hFFFB)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_4 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ), .I1(rdlvl_stg1_done_r1), .I2(rstdiv0_sync_r1_reg_rep__23), .I3(prbs_rdlvl_done_reg), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 )); LUT5 #( .INIT(32'h00000001)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_5 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I4(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair546" *) LUT2 #( .INIT(4'h2)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_6 (.I0(\one_rank.stg1_wr_done_reg_0 ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 )); LUT6 #( .INIT(64'h000000000000000B)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_7 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ), .I1(\complex_row_cnt_ocal[7]_i_6_n_0 ), .I2(reset_rd_addr_r1), .I3(complex_victim_inc_reg), .I4(wr_victim_inc), .I5(complex_sample_cnt_inc_r2), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair546" *) LUT4 #( .INIT(16'h4044)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_8 (.I0(complex_victim_inc_reg), .I1(complex_sample_cnt_inc_r2), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 )); LUT6 #( .INIT(64'h0000000200000000)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_9 (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(wr_victim_inc), .O(\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 )); LUT6 #( .INIT(64'h00000000262A2A2A)) \row_cnt_victim_rotate.complex_row_cnt[5]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I1(complex_row_cnt), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \row_cnt_victim_rotate.complex_row_cnt[5]_i_2 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 )); LUT5 #( .INIT(32'h0000262A)) \row_cnt_victim_rotate.complex_row_cnt[6]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I1(complex_row_cnt), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000262A2A2A)) \row_cnt_victim_rotate.complex_row_cnt[7]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I1(complex_row_cnt), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \row_cnt_victim_rotate.complex_row_cnt[7]_i_2 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFBBFBAAAAAAAA)) \row_cnt_victim_rotate.complex_row_cnt[7]_i_3 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I2(complex_sample_cnt_inc_r2), .I3(complex_victim_inc_reg), .I4(reset_rd_addr_r1), .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[0] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[1] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[2] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[3] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[4] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[5] (.C(CLK), .CE(1'b1), .D(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[6] (.C(CLK), .CE(1'b1), .D(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \row_cnt_victim_rotate.complex_row_cnt_reg[7] (.C(CLK), .CE(1'b1), .D(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair557" *) LUT2 #( .INIT(4'hB)) \samples_cnt_r[11]_i_1 (.I0(complex_sample_cnt_inc), .I1(\samples_cnt_r_reg[11]_0 ), .O(\samples_cnt_r_reg[11] )); LUT3 #( .INIT(8'hBA)) \stg1_wr_rd_cnt[0]_i_1 (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .O(\stg1_wr_rd_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0D00000D0D0D0D0D)) \stg1_wr_rd_cnt[1]_i_1 (.I0(stg1_wr_done), .I1(rdlvl_stg1_done_int_reg), .I2(rstdiv0_sync_r1_reg_rep__23), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I5(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .O(\stg1_wr_rd_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair564" *) LUT4 #( .INIT(16'hFD57)) \stg1_wr_rd_cnt[2]_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\stg1_wr_rd_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00A8AAA8AAA800A8)) \stg1_wr_rd_cnt[3]_i_1 (.I0(rdlvl_stg1_done_int_reg_1), .I1(\stg1_wr_rd_cnt[3]_i_2_n_0 ), .I2(prbs_rdlvl_done_reg), .I3(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ), .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ), .O(\stg1_wr_rd_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFD0FF)) \stg1_wr_rd_cnt[3]_i_2 (.I0(complex_row0_rd_done), .I1(complex_row1_rd_done), .I2(complex_row1_wr_done), .I3(complex_row0_wr_done), .I4(wr_victim_inc), .O(\stg1_wr_rd_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h88888882AAAAAAAA)) \stg1_wr_rd_cnt[4]_i_1 (.I0(rdlvl_stg1_done_int_reg_1), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ), .I5(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .O(\stg1_wr_rd_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair603" *) LUT2 #( .INIT(4'hE)) \stg1_wr_rd_cnt[4]_i_3 (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\stg1_wr_rd_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0222022200000222)) \stg1_wr_rd_cnt[4]_i_4 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(rdlvl_last_byte_done), .I2(\wrcal_reads[7]_i_6_n_0 ), .I3(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .I4(prbs_rdlvl_prech_req_reg), .I5(\stg1_wr_rd_cnt[4]_i_6_n_0 ), .O(\stg1_wr_rd_cnt[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair479" *) LUT5 #( .INIT(32'h00800000)) \stg1_wr_rd_cnt[4]_i_5 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .O(\stg1_wr_rd_cnt[4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFF7FFFFFFFF)) \stg1_wr_rd_cnt[4]_i_6 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[3]), .I3(Q[4]), .I4(Q[5]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\stg1_wr_rd_cnt[4]_i_6_n_0 )); LUT6 #( .INIT(64'hEEEBEEEEAAAAAAAA)) \stg1_wr_rd_cnt[5]_i_1 (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .O(\stg1_wr_rd_cnt[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair564" *) LUT3 #( .INIT(8'h01)) \stg1_wr_rd_cnt[5]_i_2 (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ), .O(\stg1_wr_rd_cnt[5]_i_2_n_0 )); LUT4 #( .INIT(16'hFF60)) \stg1_wr_rd_cnt[6]_i_1 (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I3(\stg1_wr_rd_cnt[6]_i_2_n_0 ), .O(\stg1_wr_rd_cnt[6]_i_1_n_0 )); LUT5 #( .INIT(32'h00002022)) \stg1_wr_rd_cnt[6]_i_2 (.I0(\stg1_wr_rd_cnt[3]_i_2_n_0 ), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(rdlvl_stg1_done_int_reg), .I3(stg1_wr_done), .I4(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .O(\stg1_wr_rd_cnt[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair511" *) LUT4 #( .INIT(16'hA208)) \stg1_wr_rd_cnt[7]_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ), .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ), .O(\stg1_wr_rd_cnt[7]_i_1_n_0 )); LUT4 #( .INIT(16'hFFD5)) \stg1_wr_rd_cnt[8]_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I2(rdlvl_stg1_done_int_reg), .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .O(\stg1_wr_rd_cnt[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair511" *) LUT5 #( .INIT(32'hA8AA0200)) \stg1_wr_rd_cnt[8]_i_2 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I3(\stg1_wr_rd_cnt[8]_i_6_n_0 ), .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ), .O(\stg1_wr_rd_cnt[8]_i_2_n_0 )); LUT4 #( .INIT(16'h00A2)) \stg1_wr_rd_cnt[8]_i_3 (.I0(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .I1(stg1_wr_done), .I2(rdlvl_stg1_done_int_reg), .I3(rstdiv0_sync_r1_reg_rep__23), .O(\stg1_wr_rd_cnt[8]_i_3_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \stg1_wr_rd_cnt[8]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\wrcal_reads[7]_i_6_n_0 ), .O(\stg1_wr_rd_cnt[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000000080)) \stg1_wr_rd_cnt[8]_i_5 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(\init_state_r[5]_i_2_n_0 ), .I5(Q[3]), .O(\stg1_wr_rd_cnt[8]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \stg1_wr_rd_cnt[8]_i_6 (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ), .O(\stg1_wr_rd_cnt[8]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[0] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[0]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[1] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[1]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[2] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[2]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[3] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[3]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[4] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[4]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[5] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[5]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[6] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[6]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[7] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[7]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg1_wr_rd_cnt_reg[8] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[8]_i_2_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[8] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair579" *) LUT3 #( .INIT(8'hB8)) \victim_sel[0]_i_1 (.I0(\victim_sel[0]_i_2_n_0 ), .I1(\victim_sel[2]_i_3_n_0 ), .I2(\victim_sel_reg_n_0_[0] ), .O(\victim_sel[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \victim_sel[0]_i_2 (.I0(complex_ocal_rd_victim_sel[0]), .I1(\rd_victim_sel_reg[0] ), .I2(\victim_sel[2]_i_4_n_0 ), .I3(wr_victim_sel_ocal[0]), .I4(prbs_rdlvl_done_reg_rep), .I5(wr_victim_sel[0]), .O(\victim_sel[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair581" *) LUT3 #( .INIT(8'hB8)) \victim_sel[1]_i_1 (.I0(\victim_sel[1]_i_2_n_0 ), .I1(\victim_sel[2]_i_3_n_0 ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel[1]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \victim_sel[1]_i_2 (.I0(complex_ocal_rd_victim_sel[1]), .I1(\rd_victim_sel_reg[1] ), .I2(\victim_sel[2]_i_4_n_0 ), .I3(wr_victim_sel_ocal[1]), .I4(prbs_rdlvl_done_reg_rep), .I5(wr_victim_sel[1]), .O(\victim_sel[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair579" *) LUT3 #( .INIT(8'hB8)) \victim_sel[2]_i_1 (.I0(\victim_sel[2]_i_2_n_0 ), .I1(\victim_sel[2]_i_3_n_0 ), .I2(\victim_sel_reg_n_0_[2] ), .O(\victim_sel[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \victim_sel[2]_i_2 (.I0(complex_ocal_rd_victim_sel[2]), .I1(\rd_victim_sel_reg[2] ), .I2(\victim_sel[2]_i_4_n_0 ), .I3(wr_victim_sel_ocal[2]), .I4(prbs_rdlvl_done_reg_rep), .I5(wr_victim_sel[2]), .O(\victim_sel[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBABF)) \victim_sel[2]_i_3 (.I0(\victim_sel[2]_i_5_n_0 ), .I1(complex_wr_done), .I2(prbs_rdlvl_done_reg), .I3(\one_rank.stg1_wr_done_reg_0 ), .I4(reset_rd_addr), .I5(complex_ocal_reset_rd_addr), .O(\victim_sel[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair571" *) LUT3 #( .INIT(8'hB8)) \victim_sel[2]_i_4 (.I0(complex_wr_done), .I1(prbs_rdlvl_done_reg_rep), .I2(\one_rank.stg1_wr_done_reg_0 ), .O(\victim_sel[2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair513" *) LUT5 #( .INIT(32'h00040000)) \victim_sel[2]_i_5 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(Q[2]), .I2(Q[0]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[1]), .O(\victim_sel[2]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \victim_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\victim_sel[0]_i_1_n_0 ), .Q(\victim_sel_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \victim_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\victim_sel[1]_i_1_n_0 ), .Q(\victim_sel_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE #( .INIT(1'b0)) \victim_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\victim_sel[2]_i_1_n_0 ), .Q(\victim_sel_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair565" *) LUT3 #( .INIT(8'h01)) \victim_sel_rotate.sel[24]_i_1 (.I0(\victim_sel_reg_n_0_[2] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [0])); (* SOFT_HLUTNM = "soft_lutpair581" *) LUT3 #( .INIT(8'h02)) \victim_sel_rotate.sel[25]_i_1 (.I0(\victim_sel_reg_n_0_[0] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [1])); (* SOFT_HLUTNM = "soft_lutpair584" *) LUT3 #( .INIT(8'h02)) \victim_sel_rotate.sel[26]_i_1 (.I0(\victim_sel_reg_n_0_[1] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[0] ), .O(\victim_sel_rotate.sel_reg[31] [2])); LUT3 #( .INIT(8'h40)) \victim_sel_rotate.sel[27]_i_1 (.I0(\victim_sel_reg_n_0_[2] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [3])); (* SOFT_HLUTNM = "soft_lutpair565" *) LUT3 #( .INIT(8'h02)) \victim_sel_rotate.sel[28]_i_1 (.I0(\victim_sel_reg_n_0_[2] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [4])); (* SOFT_HLUTNM = "soft_lutpair568" *) LUT3 #( .INIT(8'h08)) \victim_sel_rotate.sel[29]_i_1 (.I0(\victim_sel_reg_n_0_[0] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [5])); (* SOFT_HLUTNM = "soft_lutpair584" *) LUT3 #( .INIT(8'h40)) \victim_sel_rotate.sel[30]_i_1 (.I0(\victim_sel_reg_n_0_[0] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [6])); (* SOFT_HLUTNM = "soft_lutpair568" *) LUT3 #( .INIT(8'h80)) \victim_sel_rotate.sel[31]_i_1 (.I0(\victim_sel_reg_n_0_[1] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[2] ), .O(\victim_sel_rotate.sel_reg[31] [7])); FDRE #( .INIT(1'b0)) wl_sm_start_reg (.C(CLK), .CE(1'b1), .D(wr_level_dqs_asrt_r1), .Q(wl_sm_start), .R(rstdiv0_sync_r1_reg_rep__11)); (* SOFT_HLUTNM = "soft_lutpair542" *) LUT4 #( .INIT(16'h00AE)) \wr_done_victim_rotate.complex_row0_wr_done_i_1 (.I0(complex_row0_wr_done), .I1(rdlvl_stg1_done_r1), .I2(wr_victim_inc_i_2_n_0), .I3(complex_row0_wr_done0), .O(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFEEFEEEEEEEEE)) \wr_done_victim_rotate.complex_row0_wr_done_i_2 (.I0(complex_row0_rd_done1), .I1(complex_byte_rd_done), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I3(prbs_rdlvl_done_reg), .I4(\complex_row_cnt_ocal[7]_i_5_n_0 ), .I5(wr_victim_inc), .O(complex_row0_wr_done0)); FDRE #( .INIT(1'b0)) \wr_done_victim_rotate.complex_row0_wr_done_reg (.C(CLK), .CE(1'b1), .D(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ), .Q(complex_row0_wr_done), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair542" *) LUT4 #( .INIT(16'h00AE)) \wr_done_victim_rotate.complex_row1_wr_done_i_1 (.I0(complex_row1_wr_done), .I1(complex_row0_wr_done), .I2(wr_victim_inc_i_2_n_0), .I3(complex_row0_wr_done0), .O(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wr_done_victim_rotate.complex_row1_wr_done_reg (.C(CLK), .CE(1'b1), .D(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ), .Q(complex_row1_wr_done), .R(1'b0)); LUT4 #( .INIT(16'h00E0)) wr_level_dqs_asrt_i_1 (.I0(wr_level_dqs_asrt), .I1(wrlvl_active_r1), .I2(\en_cnt_div4.wrlvl_odt_i_2_n_0 ), .I3(rstdiv0_sync_r1_reg_rep__24), .O(wr_level_dqs_asrt_i_1_n_0)); FDRE #( .INIT(1'b0)) wr_level_dqs_asrt_r1_reg (.C(CLK), .CE(1'b1), .D(wr_level_dqs_asrt), .Q(wr_level_dqs_asrt_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) wr_level_dqs_asrt_reg (.C(CLK), .CE(1'b1), .D(wr_level_dqs_asrt_i_1_n_0), .Q(wr_level_dqs_asrt), .R(1'b0)); LUT5 #( .INIT(32'h0000EA00)) wr_lvl_start_i_1 (.I0(wr_level_start_r_reg), .I1(dqs_asrt_cnt[0]), .I2(dqs_asrt_cnt[1]), .I3(wrlvl_active), .I4(rstdiv0_sync_r1_reg_rep__23), .O(wr_lvl_start_i_1_n_0)); FDRE #( .INIT(1'b0)) wr_lvl_start_reg (.C(CLK), .CE(1'b1), .D(wr_lvl_start_i_1_n_0), .Q(wr_level_start_r_reg), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair566" *) LUT2 #( .INIT(4'hE)) wr_ptr0_i_1 (.I0(init_calib_complete_reg_rep__14), .I1(calib_ctl_wren), .O(mux_cmd_wren)); (* SOFT_HLUTNM = "soft_lutpair566" *) LUT3 #( .INIT(8'hB8)) \wr_ptr[3]_i_3 (.I0(mc_wrdata_en), .I1(init_calib_complete_reg_rep__14), .I2(calib_wrdata_en), .O(mux_wrdata_en)); (* SOFT_HLUTNM = "soft_lutpair549" *) LUT3 #( .INIT(8'h04)) wr_victim_inc_i_1 (.I0(wr_victim_inc_i_2_n_0), .I1(complex_row0_wr_done), .I2(\one_rank.stg1_wr_done_reg_0 ), .O(wr_victim_inc0)); (* SOFT_HLUTNM = "soft_lutpair500" *) LUT5 #( .INIT(32'hFFFFFEFF)) wr_victim_inc_i_2 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(wr_victim_inc_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair514" *) LUT5 #( .INIT(32'hFFFFFFFE)) wr_victim_inc_i_3 (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ), .O(wr_victim_inc_i_3_n_0)); FDRE #( .INIT(1'b0)) wr_victim_inc_reg (.C(CLK), .CE(1'b1), .D(wr_victim_inc0), .Q(wr_victim_inc), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair527" *) LUT4 #( .INIT(16'h006A)) \wr_victim_sel[0]_i_1 (.I0(wr_victim_sel[0]), .I1(wr_victim_inc), .I2(rdlvl_stg1_done_r1), .I3(p_81_in), .O(\wr_victim_sel[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair527" *) LUT5 #( .INIT(32'h00006AAA)) \wr_victim_sel[1]_i_1 (.I0(wr_victim_sel[1]), .I1(wr_victim_inc), .I2(rdlvl_stg1_done_r1), .I3(wr_victim_sel[0]), .I4(p_81_in), .O(\wr_victim_sel[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000006AAAAAAA)) \wr_victim_sel[2]_i_1 (.I0(wr_victim_sel[2]), .I1(wr_victim_inc), .I2(rdlvl_stg1_done_r1), .I3(wr_victim_sel[1]), .I4(wr_victim_sel[0]), .I5(p_81_in), .O(\wr_victim_sel[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair528" *) LUT4 #( .INIT(16'h006A)) \wr_victim_sel_ocal[0]_i_1 (.I0(wr_victim_sel_ocal[0]), .I1(prbs_rdlvl_done_reg), .I2(wr_victim_inc), .I3(rstdiv0_sync_r1_reg_rep__23_1), .O(\wr_victim_sel_ocal[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair528" *) LUT5 #( .INIT(32'h00006AAA)) \wr_victim_sel_ocal[1]_i_1 (.I0(wr_victim_sel_ocal[1]), .I1(prbs_rdlvl_done_reg), .I2(wr_victim_inc), .I3(wr_victim_sel_ocal[0]), .I4(rstdiv0_sync_r1_reg_rep__23_1), .O(\wr_victim_sel_ocal[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000006AAAAAAA)) \wr_victim_sel_ocal[2]_i_1 (.I0(wr_victim_sel_ocal[2]), .I1(prbs_rdlvl_done_reg), .I2(wr_victim_inc), .I3(wr_victim_sel_ocal[1]), .I4(wr_victim_sel_ocal[0]), .I5(rstdiv0_sync_r1_reg_rep__23_1), .O(\wr_victim_sel_ocal[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wr_victim_sel_ocal_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel_ocal[0]_i_1_n_0 ), .Q(wr_victim_sel_ocal[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_victim_sel_ocal_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel_ocal[1]_i_1_n_0 ), .Q(wr_victim_sel_ocal[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_victim_sel_ocal_reg[2] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel_ocal[2]_i_1_n_0 ), .Q(wr_victim_sel_ocal[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_victim_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel[0]_i_1_n_0 ), .Q(wr_victim_sel[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_victim_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel[1]_i_1_n_0 ), .Q(wr_victim_sel[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_victim_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel[2]_i_1_n_0 ), .Q(wr_victim_sel[2]), .R(1'b0)); LUT2 #( .INIT(4'h2)) \wrcal_dqs_cnt_r[2]_i_4 (.I0(wrcal_sanity_chk), .I1(wrcal_sanity_chk_r_reg), .O(\wrcal_dqs_cnt_r_reg[0] )); LUT5 #( .INIT(32'hFFFF0080)) wrcal_final_chk_i_1 (.I0(\init_state_r[1]_i_1_n_0 ), .I1(\init_state_r[0]_i_1_n_0 ), .I2(\init_state_r[4]_i_1_n_0 ), .I3(wrcal_final_chk_i_2_n_0), .I4(wrcal_final_chk), .O(wrcal_final_chk_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair481" *) LUT5 #( .INIT(32'hFFFFFFDF)) wrcal_final_chk_i_2 (.I0(\init_state_r[2]_i_1_n_0 ), .I1(\init_state_r[5]_i_1_n_0 ), .I2(wrcal_done_reg_10), .I3(\init_state_r[3]_i_2_n_0 ), .I4(\init_state_r[6]_i_2_n_0 ), .O(wrcal_final_chk_i_2_n_0)); FDRE #( .INIT(1'b0)) wrcal_final_chk_reg (.C(CLK), .CE(1'b1), .D(wrcal_final_chk_i_1_n_0), .Q(wrcal_final_chk), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h0000000000100000)) wrcal_rd_wait_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(wrcal_rd_wait_i_1_n_0)); FDRE #( .INIT(1'b0)) wrcal_rd_wait_reg (.C(CLK), .CE(1'b1), .D(wrcal_rd_wait_i_1_n_0), .Q(wrcal_rd_wait), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair537" *) LUT2 #( .INIT(4'hB)) \wrcal_reads[0]_i_1 (.I0(wrcal_reads), .I1(\wrcal_reads_reg_n_0_[0] ), .O(\wrcal_reads[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair573" *) LUT3 #( .INIT(8'hF9)) \wrcal_reads[1]_i_1 (.I0(\wrcal_reads_reg_n_0_[0] ), .I1(\wrcal_reads_reg_n_0_[1] ), .I2(wrcal_reads), .O(\wrcal_reads[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair496" *) LUT4 #( .INIT(16'hFFE1)) \wrcal_reads[2]_i_1 (.I0(\wrcal_reads_reg_n_0_[1] ), .I1(\wrcal_reads_reg_n_0_[0] ), .I2(\wrcal_reads_reg_n_0_[2] ), .I3(wrcal_reads), .O(\wrcal_reads[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair496" *) LUT5 #( .INIT(32'hFFFFFE01)) \wrcal_reads[3]_i_1 (.I0(\wrcal_reads_reg_n_0_[0] ), .I1(\wrcal_reads_reg_n_0_[1] ), .I2(\wrcal_reads_reg_n_0_[2] ), .I3(\wrcal_reads_reg_n_0_[3] ), .I4(wrcal_reads), .O(\wrcal_reads[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFE0001)) \wrcal_reads[4]_i_1 (.I0(\wrcal_reads_reg_n_0_[3] ), .I1(\wrcal_reads_reg_n_0_[2] ), .I2(\wrcal_reads_reg_n_0_[1] ), .I3(\wrcal_reads_reg_n_0_[0] ), .I4(\wrcal_reads_reg_n_0_[4] ), .I5(wrcal_reads), .O(\wrcal_reads[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair573" *) LUT3 #( .INIT(8'hF6)) \wrcal_reads[5]_i_1 (.I0(\wrcal_reads[5]_i_2_n_0 ), .I1(\wrcal_reads_reg_n_0_[5] ), .I2(wrcal_reads), .O(\wrcal_reads[5]_i_1_n_0 )); LUT5 #( .INIT(32'h00000001)) \wrcal_reads[5]_i_2 (.I0(\wrcal_reads_reg_n_0_[4] ), .I1(\wrcal_reads_reg_n_0_[0] ), .I2(\wrcal_reads_reg_n_0_[1] ), .I3(\wrcal_reads_reg_n_0_[2] ), .I4(\wrcal_reads_reg_n_0_[3] ), .O(\wrcal_reads[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair539" *) LUT3 #( .INIT(8'hF6)) \wrcal_reads[6]_i_1 (.I0(\wrcal_reads[7]_i_7_n_0 ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(wrcal_reads), .O(\wrcal_reads[6]_i_1_n_0 )); LUT6 #( .INIT(64'hAABAAAAAAAAAAAAA)) \wrcal_reads[7]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(\wrcal_reads[7]_i_6_n_0 ), .O(wrcal_reads05_out)); LUT4 #( .INIT(16'hFFFD)) \wrcal_reads[7]_i_2 (.I0(\wrcal_reads[7]_i_7_n_0 ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(\wrcal_reads_reg_n_0_[7] ), .I3(wrcal_reads), .O(\wrcal_reads[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair539" *) LUT4 #( .INIT(16'hFFD2)) \wrcal_reads[7]_i_3 (.I0(\wrcal_reads[7]_i_7_n_0 ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(\wrcal_reads_reg_n_0_[7] ), .I3(wrcal_reads), .O(\wrcal_reads[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \wrcal_reads[7]_i_5 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .O(\wrcal_reads[7]_i_5_n_0 )); LUT2 #( .INIT(4'h1)) \wrcal_reads[7]_i_6 (.I0(Q[0]), .I1(Q[1]), .O(\wrcal_reads[7]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \wrcal_reads[7]_i_7 (.I0(\wrcal_reads_reg_n_0_[3] ), .I1(\wrcal_reads_reg_n_0_[2] ), .I2(\wrcal_reads_reg_n_0_[1] ), .I3(\wrcal_reads_reg_n_0_[0] ), .I4(\wrcal_reads_reg_n_0_[4] ), .I5(\wrcal_reads_reg_n_0_[5] ), .O(\wrcal_reads[7]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000004000)) \wrcal_reads[7]_i_8 (.I0(read_calib_i_2_n_0), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(\wrcal_reads[7]_i_7_n_0 ), .I4(\wrcal_reads_reg_n_0_[6] ), .I5(\wrcal_reads_reg_n_0_[7] ), .O(wrcal_reads)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[0] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[0]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[0] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[1] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[1]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[1] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[2] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[2]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[2] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[3] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[3]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[3] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[4] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[4]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[4] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[5] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[5]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[5] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[6] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[6]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[6] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) \wrcal_reads_reg[7] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[7]_i_3_n_0 ), .Q(\wrcal_reads_reg_n_0_[7] ), .R(wrcal_reads05_out)); FDRE #( .INIT(1'b0)) wrcal_resume_r_reg (.C(CLK), .CE(1'b1), .D(wrcal_resume_w), .Q(wrcal_resume_r), .R(1'b0)); FDRE #( .INIT(1'b0)) wrcal_sanity_chk_reg (.C(CLK), .CE(1'b1), .D(wrcal_final_chk), .Q(wrcal_sanity_chk), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 " *) SRL16E #( .INIT(16'h0000)) \wrcal_start_dly_r_reg[4]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(wrcal_start_pre), .Q(\wrcal_start_dly_r_reg[4]_srl5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair489" *) LUT5 #( .INIT(32'h01000400)) \wrcal_start_dly_r_reg[4]_srl5_i_1 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(read_calib_i_2_n_0), .I3(Q[0]), .I4(Q[1]), .O(wrcal_start_pre)); FDRE #( .INIT(1'b0)) \wrcal_start_dly_r_reg[5] (.C(CLK), .CE(1'b1), .D(\wrcal_start_dly_r_reg[4]_srl5_n_0 ), .Q(wrcal_start_dly_r), .R(1'b0)); LUT4 #( .INIT(16'h000E)) wrcal_start_i_1 (.I0(wrcal_start_reg_0), .I1(wrcal_start_dly_r), .I2(wrlvl_byte_redo), .I3(rstdiv0_sync_r1_reg_rep__23), .O(wrcal_start_i_1_n_0)); FDRE #( .INIT(1'b0)) wrcal_start_reg (.C(CLK), .CE(1'b1), .D(wrcal_start_i_1_n_0), .Q(wrcal_start_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair610" *) LUT1 #( .INIT(2'h1)) \wrcal_wr_cnt[0]_i_1 (.I0(wrcal_wr_cnt_reg__0[0]), .O(\wrcal_wr_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair610" *) LUT2 #( .INIT(4'h9)) \wrcal_wr_cnt[1]_i_1 (.I0(wrcal_wr_cnt_reg__0[0]), .I1(wrcal_wr_cnt_reg__0[1]), .O(\wrcal_wr_cnt[1]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \wrcal_wr_cnt[2]_i_1 (.I0(wrcal_wr_cnt_reg__0[2]), .I1(wrcal_wr_cnt_reg__0[1]), .I2(wrcal_wr_cnt_reg__0[0]), .O(wrcal_wr_cnt0[2])); LUT6 #( .INIT(64'hFFFFFFFF111111F1)) \wrcal_wr_cnt[3]_i_1 (.I0(first_wrcal_pat_r_i_2_n_0), .I1(complex_oclkdelay_calib_start_int_reg_0), .I2(\wrcal_wr_cnt[3]_i_4_n_0 ), .I3(wrcal_wr_cnt_reg__0[3]), .I4(wrcal_wr_cnt_reg__0[2]), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\wrcal_wr_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \wrcal_wr_cnt[3]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\wrcal_wr_cnt[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair561" *) LUT4 #( .INIT(16'hCCC9)) \wrcal_wr_cnt[3]_i_3 (.I0(wrcal_wr_cnt_reg__0[2]), .I1(wrcal_wr_cnt_reg__0[3]), .I2(wrcal_wr_cnt_reg__0[0]), .I3(wrcal_wr_cnt_reg__0[1]), .O(wrcal_wr_cnt0[3])); (* SOFT_HLUTNM = "soft_lutpair561" *) LUT2 #( .INIT(4'h1)) \wrcal_wr_cnt[3]_i_4 (.I0(wrcal_wr_cnt_reg__0[0]), .I1(wrcal_wr_cnt_reg__0[1]), .O(\wrcal_wr_cnt[3]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \wrcal_wr_cnt_reg[0] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(\wrcal_wr_cnt[0]_i_1_n_0 ), .Q(wrcal_wr_cnt_reg__0[0]), .R(\wrcal_wr_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrcal_wr_cnt_reg[1] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(\wrcal_wr_cnt[1]_i_1_n_0 ), .Q(wrcal_wr_cnt_reg__0[1]), .R(\wrcal_wr_cnt[3]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \wrcal_wr_cnt_reg[2] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(wrcal_wr_cnt0[2]), .Q(wrcal_wr_cnt_reg__0[2]), .S(\wrcal_wr_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrcal_wr_cnt_reg[3] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(wrcal_wr_cnt0[3]), .Q(wrcal_wr_cnt_reg__0[3]), .R(\wrcal_wr_cnt[3]_i_1_n_0 )); LUT3 #( .INIT(8'h2F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1 (.I0(first_wrcal_pat_r), .I1(wrcal_done_reg_10), .I2(oclkdelay_calib_done_r_reg_2), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); LUT5 #( .INIT(32'hFAFF3AFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1 (.I0(first_wrcal_pat_r), .I1(rdlvl_stg1_done_int_reg), .I2(wrcal_done_reg_10), .I3(oclkdelay_calib_done_r_reg_2), .I4(\dout_o_reg[0]_0 ), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 )); LUT5 #( .INIT(32'hFAFF3AFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2 (.I0(first_wrcal_pat_r), .I1(rdlvl_stg1_done_int_reg), .I2(wrcal_done_reg_10), .I3(oclkdelay_calib_done_r_reg_2), .I4(\dout_o_reg[0] ), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 )); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[12]_0 ), .Q(phy_wrdata[120]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_8), .Q(phy_wrdata[121]), .S(wrcal_done_reg_0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[4]_0 ), .Q(phy_wrdata[122]), .S(wrcal_done_reg_2)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_7), .Q(phy_wrdata[123]), .S(wrcal_done_reg_0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[12] ), .Q(phy_wrdata[124]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_6), .Q(phy_wrdata[125]), .S(wrcal_done_reg_0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[4] ), .Q(phy_wrdata[126]), .S(wrcal_done_reg_2)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_5), .Q(phy_wrdata[127]), .S(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[3]_0 ), .Q(phy_wrdata[152]), .R(wrcal_done_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_0 ), .Q(phy_wrdata[153]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_4 ), .Q(phy_wrdata[154]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_2 ), .Q(phy_wrdata[155]), .R(wrcal_done_reg)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[3] ), .Q(phy_wrdata[156]), .R(wrcal_done_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11] ), .Q(phy_wrdata[157]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_3 ), .Q(phy_wrdata[158]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_1 ), .Q(phy_wrdata[159]), .R(wrcal_done_reg)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_4), .Q(phy_wrdata[184]), .S(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(oclkdelay_calib_done_r_reg_0), .Q(phy_wrdata[185]), .R(1'b0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[10]_0 ), .Q(phy_wrdata[186]), .S(wrcal_done_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[2]_0 ), .Q(phy_wrdata[187]), .S(wrcal_done_reg_2)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_3), .Q(phy_wrdata[188]), .S(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(oclkdelay_calib_done_r_reg), .Q(phy_wrdata[189]), .R(1'b0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[10] ), .Q(phy_wrdata[190]), .S(wrcal_done_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[2] ), .Q(phy_wrdata[191]), .S(wrcal_done_reg_2)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_4 ), .Q(phy_wrdata[216]), .R(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_0 ), .Q(phy_wrdata[217]), .R(wrcal_done_reg)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[1]_0 ), .Q(phy_wrdata[218]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_3 ), .Q(phy_wrdata[219]), .R(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_2 ), .Q(phy_wrdata[220]), .R(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9] ), .Q(phy_wrdata[221]), .R(wrcal_done_reg)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[1] ), .Q(phy_wrdata[222]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_1 ), .Q(phy_wrdata[223]), .R(wrcal_done_reg_0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_0 ), .Q(phy_wrdata[248]), .S(oclkdelay_calib_done_r_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_4 ), .Q(phy_wrdata[249]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15]_2 ), .Q(phy_wrdata[24]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[250] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ), .Q(phy_wrdata[250]), .R(1'b0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_2 ), .Q(phy_wrdata[251]), .S(wrcal_done_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8] ), .Q(phy_wrdata[252]), .S(oclkdelay_calib_done_r_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_3 ), .Q(phy_wrdata[253]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ), .Q(phy_wrdata[254]), .R(1'b0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_1 ), .Q(phy_wrdata[255]), .S(wrcal_done_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7]_0 ), .Q(phy_wrdata[25]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7]_2 ), .Q(phy_wrdata[26]), .R(wrcal_done_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15]_1 ), .Q(phy_wrdata[27]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15]_0 ), .Q(phy_wrdata[28]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7] ), .Q(phy_wrdata[29]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7]_1 ), .Q(phy_wrdata[30]), .R(wrcal_done_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15] ), .Q(phy_wrdata[31]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(D[0]), .Q(phy_wrdata[56]), .R(1'b0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(first_rdlvl_pat_r_reg_0), .Q(phy_wrdata[57]), .S(oclkdelay_calib_done_r_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14]_2 ), .Q(phy_wrdata[58]), .S(oclkdelay_calib_done_r_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14]_1 ), .Q(phy_wrdata[59]), .S(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[60] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(D[1]), .Q(phy_wrdata[60]), .R(1'b0)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[6] ), .Q(phy_wrdata[61]), .S(oclkdelay_calib_done_r_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14]_0 ), .Q(phy_wrdata[62]), .S(oclkdelay_calib_done_r_reg_1)); FDSE #( .INIT(1'b1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14] ), .Q(phy_wrdata[63]), .S(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_0 ), .Q(phy_wrdata[88]), .R(wrcal_done_reg)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_6 ), .Q(phy_wrdata[89]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_4 ), .Q(phy_wrdata[90]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_2 ), .Q(phy_wrdata[91]), .R(wrcal_done_reg_0)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13] ), .Q(phy_wrdata[92]), .R(wrcal_done_reg)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_5 ), .Q(phy_wrdata[93]), .R(oclkdelay_calib_done_r_reg_1)); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_3 ), .Q(phy_wrdata[94]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_1 ), .Q(phy_wrdata[95]), .R(wrcal_done_reg_0)); LUT6 #( .INIT(64'h000000000EEEEEEE)) write_calib_i_1 (.I0(phy_write_calib), .I1(wrlvl_active_r1), .I2(done_dqs_tap_inc), .I3(write_calib_i_2_n_0), .I4(Q[1]), .I5(rstdiv0_sync_r1_reg_rep__23), .O(write_calib_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000004)) write_calib_i_2 (.I0(Q[0]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(write_calib_i_2_n_0)); FDRE #( .INIT(1'b0)) write_calib_reg (.C(CLK), .CE(1'b1), .D(write_calib_i_1_n_0), .Q(phy_write_calib), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000EA)) wrlvl_active_i_1 (.I0(wrlvl_active), .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ), .I2(wrlvl_odt), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(done_dqs_tap_inc), .I5(wrlvl_rank_done), .O(wrlvl_active_i_1_n_0)); FDRE #( .INIT(1'b0)) wrlvl_active_r1_reg (.C(CLK), .CE(1'b1), .D(wrlvl_active), .Q(wrlvl_active_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) wrlvl_active_reg (.C(CLK), .CE(1'b1), .D(wrlvl_active_i_1_n_0), .Q(wrlvl_active), .R(1'b0)); FDRE #( .INIT(1'b0)) wrlvl_done_r1_reg (.C(CLK), .CE(1'b1), .D(wrlvl_done_r), .Q(wrlvl_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) wrlvl_done_r_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_reg), .Q(wrlvl_done_r), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000AE)) wrlvl_final_if_rst_i_1 (.I0(wrlvl_final_if_rst), .I1(wrlvl_done_r), .I2(wrlvl_final_if_rst_i_2_n_0), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(\cnt_init_mr_r_reg[1]_0 ), .I5(\wrcal_wr_cnt[3]_i_2_n_0 ), .O(wrlvl_final_if_rst_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) wrlvl_final_if_rst_i_2 (.I0(Q[1]), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(\init_state_r_reg[1]_0 ), .I5(Q[0]), .O(wrlvl_final_if_rst_i_2_n_0)); FDRE #( .INIT(1'b0)) wrlvl_final_if_rst_reg (.C(CLK), .CE(1'b1), .D(wrlvl_final_if_rst_i_1_n_0), .Q(wrlvl_final_if_rst), .R(1'b0)); LUT5 #( .INIT(32'h000000AE)) wrlvl_odt_ctl_i_1 (.I0(wrlvl_odt_ctl), .I1(wrlvl_rank_done), .I2(wrlvl_rank_done_r1), .I3(wrlvl_odt_ctl_i_2_n_0), .I4(rstdiv0_sync_r1_reg_rep__24), .O(wrlvl_odt_ctl_i_1_n_0)); LUT6 #( .INIT(64'h0001000100010000)) wrlvl_odt_ctl_i_2 (.I0(read_calib_reg_0), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(wrlvl_odt_ctl_i_3_n_0), .I5(init_state_r1[3]), .O(wrlvl_odt_ctl_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) wrlvl_odt_ctl_i_3 (.I0(init_state_r1[1]), .I1(init_state_r1[6]), .I2(init_state_r1[2]), .I3(init_state_r1[5]), .I4(init_state_r1[4]), .I5(init_state_r1[0]), .O(wrlvl_odt_ctl_i_3_n_0)); FDRE #( .INIT(1'b0)) wrlvl_odt_ctl_reg (.C(CLK), .CE(1'b1), .D(wrlvl_odt_ctl_i_1_n_0), .Q(wrlvl_odt_ctl), .R(1'b0)); FDRE #( .INIT(1'b0)) wrlvl_rank_done_r1_reg (.C(CLK), .CE(1'b1), .D(wrlvl_rank_done), .Q(wrlvl_rank_done_r1), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 " *) SRL16E #( .INIT(16'h0000)) wrlvl_rank_done_r6_reg_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(wrlvl_rank_done_r1), .Q(wrlvl_rank_done_r6_reg_srl5_n_0)); FDRE #( .INIT(1'b0)) wrlvl_rank_done_r7_reg (.C(CLK), .CE(1'b1), .D(wrlvl_rank_done_r6_reg_srl5_n_0), .Q(wrlvl_rank_done_r7), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_cntlr" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_cntlr (prech_req_r_reg, rd_active_r1_reg, lim_start, wrlvl_final_mux_reg, reset_scan, complex_ocal_ref_req, \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] , \byte_r_reg[1]_0 , \byte_r_reg[0]_0 , D, \simp_stg3_final_r_reg[23] , \simp_stg3_final_r_reg[11] , \simp_stg3_final_r_reg[5] , \simp_stg3_final_r_reg[17] , done_r_reg, \rd_victim_sel_r_reg[0] , \stg3_init_val_reg[3] , sr_valid_r108_out, \init_state_r_reg[2] , \init_state_r_reg[5] , ocal_last_byte_done_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \cal2_state_r_reg[0] , ocd_cntlr2stg2_dec_r, rstdiv0_sync_r1_reg_rep__9, CLK, phy_rddata_en, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__25, done_r_reg_0, oclkdelay_calib_start_int_reg, prech_req_r_reg_0, rstdiv0_sync_r1_reg_rep__25_0, po_rdy, \po_counter_read_val_reg[2] , \simp_stg3_final_r_reg[17]_0 , \simp_stg3_final_r_reg[16] , \simp_stg3_final_r_reg[10] , \simp_stg3_final_r_reg[2] , \simp_stg3_final_r_reg[8] , \simp_stg3_final_r_reg[19] , \simp_stg3_final_r_reg[12] , lim_start_r, rstdiv0_sync_r1_reg_rep__24, \data_cnt_r_reg[7] , rstdiv0_sync_r1_reg_rep__20, rdlvl_stg1_start_reg, \cnt_shift_r_reg[0] , \init_state_r_reg[0] , \init_state_r_reg[2]_0 , prbs_rdlvl_done_reg, oclk_calib_resume_r_reg, prech_req_posedge_r_reg, cnt_cmd_done_r, oclkdelay_center_calib_done_r_reg, ocal_last_byte_done, \po_stg2_wrcal_cnt_reg[0] , wr_level_done_reg, oclkdelay_calib_done_r_reg_0, pi_stg2_rdlvl_cnt, \po_stg2_wrcal_cnt_reg[1] , rd_active_r1, wrlvl_byte_done, rstdiv0_sync_r1_reg_rep__2, prech_done, oclkdelay_calib_start_int_reg_0); output prech_req_r_reg; output rd_active_r1_reg; output lim_start; output wrlvl_final_mux_reg; output reset_scan; output complex_ocal_ref_req; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; output \byte_r_reg[1]_0 ; output \byte_r_reg[0]_0 ; output [4:0]D; output \simp_stg3_final_r_reg[23] ; output \simp_stg3_final_r_reg[11] ; output \simp_stg3_final_r_reg[5] ; output \simp_stg3_final_r_reg[17] ; output done_r_reg; output \rd_victim_sel_r_reg[0] ; output \stg3_init_val_reg[3] ; output sr_valid_r108_out; output \init_state_r_reg[2] ; output \init_state_r_reg[5] ; output ocal_last_byte_done_reg; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \cal2_state_r_reg[0] ; output ocd_cntlr2stg2_dec_r; input rstdiv0_sync_r1_reg_rep__9; input CLK; input phy_rddata_en; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__25; input done_r_reg_0; input oclkdelay_calib_start_int_reg; input prech_req_r_reg_0; input rstdiv0_sync_r1_reg_rep__25_0; input po_rdy; input \po_counter_read_val_reg[2] ; input \simp_stg3_final_r_reg[17]_0 ; input \simp_stg3_final_r_reg[16] ; input \simp_stg3_final_r_reg[10] ; input \simp_stg3_final_r_reg[2] ; input \simp_stg3_final_r_reg[8] ; input \simp_stg3_final_r_reg[19] ; input \simp_stg3_final_r_reg[12] ; input lim_start_r; input rstdiv0_sync_r1_reg_rep__24; input \data_cnt_r_reg[7] ; input rstdiv0_sync_r1_reg_rep__20; input rdlvl_stg1_start_reg; input \cnt_shift_r_reg[0] ; input \init_state_r_reg[0] ; input [1:0]\init_state_r_reg[2]_0 ; input prbs_rdlvl_done_reg; input oclk_calib_resume_r_reg; input prech_req_posedge_r_reg; input cnt_cmd_done_r; input oclkdelay_center_calib_done_r_reg; input ocal_last_byte_done; input \po_stg2_wrcal_cnt_reg[0] ; input wr_level_done_reg; input oclkdelay_calib_done_r_reg_0; input [1:0]pi_stg2_rdlvl_cnt; input \po_stg2_wrcal_cnt_reg[1] ; input rd_active_r1; input wrlvl_byte_done; input rstdiv0_sync_r1_reg_rep__2; input prech_done; input oclkdelay_calib_start_int_reg_0; wire CLK; wire [4:0]D; wire \FSM_sequential_sm_r[0]_i_1_n_0 ; wire \FSM_sequential_sm_r[1]_i_1_n_0 ; wire \FSM_sequential_sm_r[2]_i_2_n_0 ; wire \FSM_sequential_sm_r[2]_i_3_n_0 ; wire \FSM_sequential_sm_r[2]_i_5_n_0 ; wire \FSM_sequential_sm_r[2]_i_6_n_0 ; wire \FSM_sequential_sm_r_reg[2]_i_4_n_0 ; wire \byte_r[0]_i_1_n_0 ; wire \byte_r[0]_i_2_n_0 ; wire \byte_r[1]_i_1_n_0 ; wire \byte_r[1]_i_2_n_0 ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[1]_0 ; wire \cal2_state_r_reg[0] ; wire cnt_cmd_done_r; wire \cnt_shift_r_reg[0] ; wire complex_ocal_ref_req; wire \data_cnt_r_reg[7] ; wire done_r_reg; wire done_r_reg_0; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[2] ; wire [1:0]\init_state_r_reg[2]_0 ; wire \init_state_r_reg[5] ; wire lim_start; wire lim_start_r; wire lim_start_r_i_1_n_0; wire lim_start_r_i_2_n_0; wire ocal_last_byte_done; wire ocal_last_byte_done_reg; wire ocd_cntlr2stg2_dec_r; wire ocd_prech_req_ns; wire oclk_calib_resume_r_reg; wire oclkdelay_calib_done_r_i_1_n_0; wire oclkdelay_calib_done_r_i_3_n_0; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_calib_start_int_reg; wire oclkdelay_calib_start_int_reg_0; wire oclkdelay_center_calib_done_r_reg; wire phy_rddata_en; wire [1:0]pi_stg2_rdlvl_cnt; wire \po_counter_read_val_reg[2] ; wire [3:0]po_rd_wait_ns; wire \po_rd_wait_r[0]_i_2_n_0 ; wire \po_rd_wait_r[1]_i_2_n_0 ; wire \po_rd_wait_r[2]_i_2_n_0 ; wire \po_rd_wait_r[2]_i_3_n_0 ; wire \po_rd_wait_r[3]_i_1_n_0 ; wire \po_rd_wait_r[3]_i_3_n_0 ; wire \po_rd_wait_r[3]_i_4_n_0 ; wire \po_rd_wait_r[3]_i_5_n_0 ; wire \po_rd_wait_r[3]_i_6_n_0 ; wire [3:0]po_rd_wait_r_reg__0; wire po_rdy; wire \po_stg2_wrcal_cnt_reg[0] ; wire \po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_done_reg; wire prech_done; wire prech_req_posedge_r_reg; wire prech_req_r_reg; wire prech_req_r_reg_0; wire rd_active_r1; wire rd_active_r1_reg; wire \rd_victim_sel_r_reg[0] ; wire rdlvl_stg1_start_reg; wire reset_scan; wire reset_scan_r_i_1_n_0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__9; wire \simp_stg3_final_r_reg[10] ; wire \simp_stg3_final_r_reg[11] ; wire \simp_stg3_final_r_reg[12] ; wire \simp_stg3_final_r_reg[16] ; wire \simp_stg3_final_r_reg[17] ; wire \simp_stg3_final_r_reg[17]_0 ; wire \simp_stg3_final_r_reg[19] ; wire \simp_stg3_final_r_reg[23] ; wire \simp_stg3_final_r_reg[2] ; wire \simp_stg3_final_r_reg[5] ; wire \simp_stg3_final_r_reg[8] ; (* RTL_KEEP = "yes" *) wire [2:0]sm_r; wire sr_valid_r108_out; wire \stg3_init_val_reg[3] ; wire wr_level_done_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; wire wrlvl_byte_done; wire wrlvl_final_mux_reg; wire wrlvl_final_r0; LUT3 #( .INIT(8'h74)) \FSM_sequential_sm_r[0]_i_1 (.I0(sm_r[0]), .I1(\FSM_sequential_sm_r_reg[2]_i_4_n_0 ), .I2(sm_r[0]), .O(\FSM_sequential_sm_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h8FB0FFFF8FB00000)) \FSM_sequential_sm_r[1]_i_1 (.I0(\FSM_sequential_sm_r[2]_i_3_n_0 ), .I1(sm_r[2]), .I2(sm_r[1]), .I3(sm_r[0]), .I4(\FSM_sequential_sm_r_reg[2]_i_4_n_0 ), .I5(sm_r[1]), .O(\FSM_sequential_sm_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hAFC0FFFFAFC00000)) \FSM_sequential_sm_r[2]_i_2 (.I0(\FSM_sequential_sm_r[2]_i_3_n_0 ), .I1(sm_r[0]), .I2(sm_r[1]), .I3(sm_r[2]), .I4(\FSM_sequential_sm_r_reg[2]_i_4_n_0 ), .I5(sm_r[2]), .O(\FSM_sequential_sm_r[2]_i_2_n_0 )); LUT3 #( .INIT(8'h08)) \FSM_sequential_sm_r[2]_i_3 (.I0(\byte_r_reg[0]_0 ), .I1(\byte_r_reg[1]_0 ), .I2(sm_r[0]), .O(\FSM_sequential_sm_r[2]_i_3_n_0 )); LUT5 #( .INIT(32'hBBBBCFCC)) \FSM_sequential_sm_r[2]_i_5 (.I0(prech_done), .I1(sm_r[2]), .I2(wrlvl_final_mux_reg), .I3(oclkdelay_calib_start_int_reg_0), .I4(sm_r[0]), .O(\FSM_sequential_sm_r[2]_i_5_n_0 )); LUT5 #( .INIT(32'hB8FFB8CC)) \FSM_sequential_sm_r[2]_i_6 (.I0(oclkdelay_calib_done_r_i_3_n_0), .I1(sm_r[2]), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(sm_r[0]), .I4(done_r_reg_0), .O(\FSM_sequential_sm_r[2]_i_6_n_0 )); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_r_reg[0] (.C(CLK), .CE(1'b1), .D(\FSM_sequential_sm_r[0]_i_1_n_0 ), .Q(sm_r[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_r_reg[1] (.C(CLK), .CE(1'b1), .D(\FSM_sequential_sm_r[1]_i_1_n_0 ), .Q(sm_r[1]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_r_reg[2] (.C(CLK), .CE(1'b1), .D(\FSM_sequential_sm_r[2]_i_2_n_0 ), .Q(sm_r[2]), .R(rstdiv0_sync_r1_reg_rep__2)); MUXF7 \FSM_sequential_sm_r_reg[2]_i_4 (.I0(\FSM_sequential_sm_r[2]_i_5_n_0 ), .I1(\FSM_sequential_sm_r[2]_i_6_n_0 ), .O(\FSM_sequential_sm_r_reg[2]_i_4_n_0 ), .S(sm_r[1])); LUT6 #( .INIT(64'hFFFF5EDE0000A020)) \byte_r[0]_i_1 (.I0(sm_r[2]), .I1(sm_r[0]), .I2(sm_r[1]), .I3(\byte_r[0]_i_2_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__25_0), .I5(\byte_r_reg[0]_0 ), .O(\byte_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair350" *) LUT5 #( .INIT(32'h00000444)) \byte_r[0]_i_2 (.I0(\po_rd_wait_r[3]_i_6_n_0 ), .I1(po_rdy), .I2(\byte_r_reg[1]_0 ), .I3(\byte_r_reg[0]_0 ), .I4(\po_counter_read_val_reg[2] ), .O(\byte_r[0]_i_2_n_0 )); LUT4 #( .INIT(16'h4F80)) \byte_r[1]_i_1 (.I0(\byte_r_reg[0]_0 ), .I1(sm_r[1]), .I2(\byte_r[1]_i_2_n_0 ), .I3(\byte_r_reg[1]_0 ), .O(\byte_r[1]_i_1_n_0 )); LUT5 #( .INIT(32'h0000A121)) \byte_r[1]_i_2 (.I0(sm_r[2]), .I1(sm_r[0]), .I2(sm_r[1]), .I3(\byte_r[0]_i_2_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__25_0), .O(\byte_r[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \byte_r_reg[0] (.C(CLK), .CE(1'b1), .D(\byte_r[0]_i_1_n_0 ), .Q(\byte_r_reg[0]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \byte_r_reg[1] (.C(CLK), .CE(1'b1), .D(\byte_r[1]_i_1_n_0 ), .Q(\byte_r_reg[1]_0 ), .R(1'b0)); LUT3 #( .INIT(8'h40)) \cal2_state_r[3]_i_10 (.I0(rd_active_r1_reg), .I1(rd_active_r1), .I2(wrlvl_byte_done), .O(\cal2_state_r_reg[0] )); LUT2 #( .INIT(4'h2)) done_r_i_2 (.I0(lim_start), .I1(lim_start_r), .O(done_r_reg)); LUT6 #( .INIT(64'hFF00F4000000F400)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_2 (.I0(wrlvl_final_mux_reg), .I1(\byte_r_reg[0]_0 ), .I2(\po_stg2_wrcal_cnt_reg[0] ), .I3(wr_level_done_reg), .I4(oclkdelay_calib_done_r_reg_0), .I5(pi_stg2_rdlvl_cnt[0]), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'hFF00F4000000F400)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_2 (.I0(wrlvl_final_mux_reg), .I1(\byte_r_reg[1]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] ), .I3(wr_level_done_reg), .I4(oclkdelay_calib_done_r_reg_0), .I5(pi_stg2_rdlvl_cnt[1]), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[1] )); LUT6 #( .INIT(64'hAAAAAAAA00000008)) \init_state_r[2]_i_19 (.I0(\init_state_r_reg[0] ), .I1(\init_state_r_reg[2]_0 [1]), .I2(prech_req_r_reg), .I3(prech_req_r_reg_0), .I4(prbs_rdlvl_done_reg), .I5(oclk_calib_resume_r_reg), .O(\init_state_r_reg[2] )); LUT6 #( .INIT(64'h00000000EEEEEE0E)) \init_state_r[5]_i_59 (.I0(wrlvl_final_mux_reg), .I1(prech_req_posedge_r_reg), .I2(cnt_cmd_done_r), .I3(prech_req_r_reg_0), .I4(prech_req_r_reg), .I5(\init_state_r_reg[2]_0 [0]), .O(\init_state_r_reg[5] )); LUT6 #( .INIT(64'hFFFF777788880300)) lim_start_r_i_1 (.I0(lim_start_r_i_2_n_0), .I1(sm_r[1]), .I2(sm_r[0]), .I3(oclkdelay_calib_start_int_reg), .I4(sm_r[2]), .I5(lim_start), .O(lim_start_r_i_1_n_0)); LUT5 #( .INIT(32'h00007F70)) lim_start_r_i_2 (.I0(\byte_r_reg[0]_0 ), .I1(\byte_r_reg[1]_0 ), .I2(sm_r[2]), .I3(done_r_reg_0), .I4(sm_r[0]), .O(lim_start_r_i_2_n_0)); FDRE #( .INIT(1'b0)) lim_start_r_reg (.C(CLK), .CE(1'b1), .D(lim_start_r_i_1_n_0), .Q(lim_start), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair352" *) LUT4 #( .INIT(16'hFF80)) ocal_last_byte_done_i_1 (.I0(oclkdelay_center_calib_done_r_reg), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .I3(ocal_last_byte_done), .O(ocal_last_byte_done_reg)); LUT3 #( .INIT(8'h04)) ocd_prech_req_r_i_1 (.I0(sm_r[0]), .I1(sm_r[2]), .I2(sm_r[1]), .O(ocd_prech_req_ns)); FDRE #( .INIT(1'b0)) ocd_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(ocd_prech_req_ns), .Q(prech_req_r_reg), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hBFFFFFFF80000000)) oclkdelay_calib_done_r_i_1 (.I0(wrlvl_final_r0), .I1(sm_r[2]), .I2(oclkdelay_calib_done_r_i_3_n_0), .I3(sm_r[0]), .I4(sm_r[1]), .I5(wrlvl_final_mux_reg), .O(oclkdelay_calib_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair351" *) LUT5 #( .INIT(32'h00000002)) oclkdelay_calib_done_r_i_2 (.I0(po_rdy), .I1(po_rd_wait_r_reg__0[0]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[2]), .I4(po_rd_wait_r_reg__0[3]), .O(wrlvl_final_r0)); (* SOFT_HLUTNM = "soft_lutpair350" *) LUT5 #( .INIT(32'h04000000)) oclkdelay_calib_done_r_i_3 (.I0(\po_rd_wait_r[3]_i_6_n_0 ), .I1(po_rdy), .I2(\po_counter_read_val_reg[2] ), .I3(\byte_r_reg[1]_0 ), .I4(\byte_r_reg[0]_0 ), .O(oclkdelay_calib_done_r_i_3_n_0)); FDRE #( .INIT(1'b0)) oclkdelay_calib_done_r_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_i_1_n_0), .Q(wrlvl_final_mux_reg), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) phy_rddata_en_r1_reg (.C(CLK), .CE(1'b1), .D(phy_rddata_en), .Q(rd_active_r1_reg), .R(1'b0)); LUT4 #( .INIT(16'h40EF)) \po_rd_wait_r[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(\po_rd_wait_r[0]_i_2_n_0 ), .I2(sm_r[1]), .I3(po_rd_wait_r_reg__0[0]), .O(po_rd_wait_ns[0])); LUT6 #( .INIT(64'h000000004777FFFF)) \po_rd_wait_r[0]_i_2 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1]_0 ), .I4(sm_r[2]), .I5(po_rd_wait_r_reg__0[0]), .O(\po_rd_wait_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'hEFFF40004000EFFF)) \po_rd_wait_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(\po_rd_wait_r[1]_i_2_n_0 ), .I2(sm_r[2]), .I3(sm_r[1]), .I4(po_rd_wait_r_reg__0[0]), .I5(po_rd_wait_r_reg__0[1]), .O(po_rd_wait_ns[1])); LUT6 #( .INIT(64'h4777000000004777)) \po_rd_wait_r[1]_i_2 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1]_0 ), .I4(po_rd_wait_r_reg__0[0]), .I5(po_rd_wait_r_reg__0[1]), .O(\po_rd_wait_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hEF40EF40EF4040EF)) \po_rd_wait_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(\po_rd_wait_r[2]_i_2_n_0 ), .I2(sm_r[1]), .I3(po_rd_wait_r_reg__0[2]), .I4(po_rd_wait_r_reg__0[0]), .I5(po_rd_wait_r_reg__0[1]), .O(po_rd_wait_ns[2])); LUT6 #( .INIT(64'h4777FFFF00000000)) \po_rd_wait_r[2]_i_2 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1]_0 ), .I4(sm_r[2]), .I5(\po_rd_wait_r[2]_i_3_n_0 ), .O(\po_rd_wait_r[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair353" *) LUT3 #( .INIT(8'hA9)) \po_rd_wait_r[2]_i_3 (.I0(po_rd_wait_r_reg__0[2]), .I1(po_rd_wait_r_reg__0[0]), .I2(po_rd_wait_r_reg__0[1]), .O(\po_rd_wait_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \po_rd_wait_r[3]_i_1 (.I0(po_rd_wait_r_reg__0[3]), .I1(po_rd_wait_r_reg__0[2]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[0]), .I4(rstdiv0_sync_r1_reg_rep__25_0), .I5(\po_rd_wait_r[3]_i_3_n_0 ), .O(\po_rd_wait_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF01000000)) \po_rd_wait_r[3]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(sm_r[0]), .I2(\po_rd_wait_r[3]_i_4_n_0 ), .I3(sm_r[2]), .I4(sm_r[1]), .I5(\po_rd_wait_r[3]_i_5_n_0 ), .O(po_rd_wait_ns[3])); LUT6 #( .INIT(64'hFFFFFFFF8B000000)) \po_rd_wait_r[3]_i_3 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\po_rd_wait_r[3]_i_4_n_0 ), .I3(sm_r[2]), .I4(sm_r[1]), .I5(\po_rd_wait_r[3]_i_6_n_0 ), .O(\po_rd_wait_r[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair358" *) LUT2 #( .INIT(4'h7)) \po_rd_wait_r[3]_i_4 (.I0(\byte_r_reg[1]_0 ), .I1(\byte_r_reg[0]_0 ), .O(\po_rd_wait_r[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair353" *) LUT4 #( .INIT(16'hAAA9)) \po_rd_wait_r[3]_i_5 (.I0(po_rd_wait_r_reg__0[3]), .I1(po_rd_wait_r_reg__0[2]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[0]), .O(\po_rd_wait_r[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair351" *) LUT4 #( .INIT(16'hFFFE)) \po_rd_wait_r[3]_i_6 (.I0(po_rd_wait_r_reg__0[3]), .I1(po_rd_wait_r_reg__0[2]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[0]), .O(\po_rd_wait_r[3]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \po_rd_wait_r_reg[0] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[0]), .Q(po_rd_wait_r_reg__0[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_rd_wait_r_reg[1] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[1]), .Q(po_rd_wait_r_reg__0[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_rd_wait_r_reg[2] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[2]), .Q(po_rd_wait_r_reg__0[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_rd_wait_r_reg[3] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[3]), .Q(po_rd_wait_r_reg__0[3]), .R(1'b0)); LUT6 #( .INIT(64'h0080000000000000)) po_rdy_r_i_8 (.I0(sm_r[2]), .I1(\po_counter_read_val_reg[2] ), .I2(po_rdy), .I3(\po_rd_wait_r[3]_i_6_n_0 ), .I4(sm_r[0]), .I5(sm_r[1]), .O(ocd_cntlr2stg2_dec_r)); LUT2 #( .INIT(4'hE)) prech_req_r_i_2__0 (.I0(prech_req_r_reg), .I1(prech_req_r_reg_0), .O(complex_ocal_ref_req)); (* SOFT_HLUTNM = "soft_lutpair355" *) LUT3 #( .INIT(8'h04)) \rd_victim_sel_r[2]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(rd_active_r1_reg), .I2(\data_cnt_r_reg[7] ), .O(\rd_victim_sel_r_reg[0] )); LUT6 #( .INIT(64'hFAFFFFFF40400000)) reset_scan_r_i_1 (.I0(sm_r[2]), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(sm_r[0]), .I3(done_r_reg_0), .I4(sm_r[1]), .I5(reset_scan), .O(reset_scan_r_i_1_n_0)); FDSE #( .INIT(1'b1)) reset_scan_r_reg (.C(CLK), .CE(1'b1), .D(reset_scan_r_i_1_n_0), .Q(reset_scan), .S(rstdiv0_sync_r1_reg_rep__9)); (* SOFT_HLUTNM = "soft_lutpair357" *) LUT3 #( .INIT(8'h08)) \simp_stg3_final_r[11]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .O(\simp_stg3_final_r_reg[11] )); (* SOFT_HLUTNM = "soft_lutpair357" *) LUT3 #( .INIT(8'h08)) \simp_stg3_final_r[17]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\byte_r_reg[1]_0 ), .I2(\byte_r_reg[0]_0 ), .O(\simp_stg3_final_r_reg[17] )); (* SOFT_HLUTNM = "soft_lutpair352" *) LUT3 #( .INIT(8'h80)) \simp_stg3_final_r[23]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .O(\simp_stg3_final_r_reg[23] )); (* SOFT_HLUTNM = "soft_lutpair358" *) LUT3 #( .INIT(8'h02)) \simp_stg3_final_r[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .O(\simp_stg3_final_r_reg[5] )); LUT4 #( .INIT(16'h0020)) sr_valid_r_i_1 (.I0(rd_active_r1_reg), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(rdlvl_stg1_start_reg), .I3(\cnt_shift_r_reg[0] ), .O(sr_valid_r108_out)); (* SOFT_HLUTNM = "soft_lutpair356" *) LUT3 #( .INIT(8'h04)) \stg3_init_val[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(wrlvl_final_mux_reg), .I2(\simp_stg3_final_r_reg[12] ), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair354" *) LUT3 #( .INIT(8'h04)) \stg3_init_val[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(wrlvl_final_mux_reg), .I2(\simp_stg3_final_r_reg[19] ), .O(D[1])); LUT6 #( .INIT(64'hFFFFFFFFDDDDDDFD)) \stg3_init_val[2]_i_1 (.I0(wrlvl_final_mux_reg), .I1(rstdiv0_sync_r1_reg_rep__25_0), .I2(\simp_stg3_final_r_reg[2] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1]_0 ), .I5(\simp_stg3_final_r_reg[8] ), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair355" *) LUT2 #( .INIT(4'h2)) \stg3_init_val[3]_i_3 (.I0(wrlvl_final_mux_reg), .I1(rstdiv0_sync_r1_reg_rep__24), .O(\stg3_init_val_reg[3] )); LUT6 #( .INIT(64'hFFFFFFFFDDDDFDDD)) \stg3_init_val[4]_i_1 (.I0(wrlvl_final_mux_reg), .I1(rstdiv0_sync_r1_reg_rep__25_0), .I2(\simp_stg3_final_r_reg[16] ), .I3(\byte_r_reg[1]_0 ), .I4(\byte_r_reg[0]_0 ), .I5(\simp_stg3_final_r_reg[10] ), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair354" *) LUT3 #( .INIT(8'h04)) \stg3_init_val[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_0), .I1(wrlvl_final_mux_reg), .I2(\simp_stg3_final_r_reg[17]_0 ), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair356" *) LUT1 #( .INIT(2'h1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_1 (.I0(wrlvl_final_mux_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_data" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_data (E, \zero_r_reg[9] , \zero_r_reg[9]_0 , \rd_victim_sel_r_reg[0] , agg_samp_r, \byte_r_reg[0] , CLK); output [0:0]E; output \zero_r_reg[9] ; output \zero_r_reg[9]_0 ; input \rd_victim_sel_r_reg[0] ; input [1:0]agg_samp_r; input [63:0]\byte_r_reg[0] ; input CLK; wire CLK; wire [0:0]E; wire [1:0]agg_samp_r; wire [63:0]\byte_r_reg[0] ; wire [63:0]data_bytes_r; wire \rd_victim_sel_r_reg[0] ; wire \zero_r[9]_i_10_n_0 ; wire \zero_r[9]_i_11_n_0 ; wire \zero_r[9]_i_12_n_0 ; wire \zero_r[9]_i_13_n_0 ; wire \zero_r[9]_i_14_n_0 ; wire \zero_r[9]_i_15_n_0 ; wire \zero_r[9]_i_16_n_0 ; wire \zero_r[9]_i_17_n_0 ; wire \zero_r[9]_i_18_n_0 ; wire \zero_r[9]_i_19_n_0 ; wire \zero_r[9]_i_20_n_0 ; wire \zero_r[9]_i_21_n_0 ; wire \zero_r[9]_i_22_n_0 ; wire \zero_r[9]_i_23_n_0 ; wire \zero_r[9]_i_24_n_0 ; wire \zero_r[9]_i_25_n_0 ; wire \zero_r[9]_i_26_n_0 ; wire \zero_r[9]_i_27_n_0 ; wire \zero_r[9]_i_28_n_0 ; wire \zero_r[9]_i_29_n_0 ; wire \zero_r[9]_i_30_n_0 ; wire \zero_r[9]_i_31_n_0 ; wire \zero_r[9]_i_32_n_0 ; wire \zero_r[9]_i_33_n_0 ; wire \zero_r[9]_i_34_n_0 ; wire \zero_r[9]_i_35_n_0 ; wire \zero_r[9]_i_36_n_0 ; wire \zero_r[9]_i_37_n_0 ; wire \zero_r[9]_i_38_n_0 ; wire \zero_r[9]_i_39_n_0 ; wire \zero_r[9]_i_40_n_0 ; wire \zero_r[9]_i_9_n_0 ; wire \zero_r_reg[9] ; wire \zero_r_reg[9]_0 ; FDRE #( .INIT(1'b0)) \data_bytes_r_reg[0] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [0]), .Q(data_bytes_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[10] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [10]), .Q(data_bytes_r[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[11] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [11]), .Q(data_bytes_r[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[12] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [12]), .Q(data_bytes_r[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[13] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [13]), .Q(data_bytes_r[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[14] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [14]), .Q(data_bytes_r[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[15] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [15]), .Q(data_bytes_r[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[16] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [16]), .Q(data_bytes_r[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[17] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [17]), .Q(data_bytes_r[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[18] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [18]), .Q(data_bytes_r[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[19] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [19]), .Q(data_bytes_r[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[1] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [1]), .Q(data_bytes_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[20] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [20]), .Q(data_bytes_r[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[21] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [21]), .Q(data_bytes_r[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[22] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [22]), .Q(data_bytes_r[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[23] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [23]), .Q(data_bytes_r[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[24] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [24]), .Q(data_bytes_r[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[25] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [25]), .Q(data_bytes_r[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[26] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [26]), .Q(data_bytes_r[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[27] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [27]), .Q(data_bytes_r[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[28] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [28]), .Q(data_bytes_r[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[29] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [29]), .Q(data_bytes_r[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[2] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [2]), .Q(data_bytes_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[30] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [30]), .Q(data_bytes_r[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[31] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [31]), .Q(data_bytes_r[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[32] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [32]), .Q(data_bytes_r[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[33] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [33]), .Q(data_bytes_r[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[34] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [34]), .Q(data_bytes_r[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[35] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [35]), .Q(data_bytes_r[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[36] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [36]), .Q(data_bytes_r[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[37] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [37]), .Q(data_bytes_r[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[38] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [38]), .Q(data_bytes_r[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[39] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [39]), .Q(data_bytes_r[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[3] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [3]), .Q(data_bytes_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[40] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [40]), .Q(data_bytes_r[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[41] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [41]), .Q(data_bytes_r[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[42] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [42]), .Q(data_bytes_r[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[43] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [43]), .Q(data_bytes_r[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[44] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [44]), .Q(data_bytes_r[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[45] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [45]), .Q(data_bytes_r[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[46] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [46]), .Q(data_bytes_r[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[47] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [47]), .Q(data_bytes_r[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[48] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [48]), .Q(data_bytes_r[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[49] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [49]), .Q(data_bytes_r[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[4] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [4]), .Q(data_bytes_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[50] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [50]), .Q(data_bytes_r[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[51] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [51]), .Q(data_bytes_r[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[52] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [52]), .Q(data_bytes_r[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[53] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [53]), .Q(data_bytes_r[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[54] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [54]), .Q(data_bytes_r[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[55] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [55]), .Q(data_bytes_r[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[56] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [56]), .Q(data_bytes_r[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[57] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [57]), .Q(data_bytes_r[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[58] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [58]), .Q(data_bytes_r[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[59] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [59]), .Q(data_bytes_r[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[5] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [5]), .Q(data_bytes_r[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[60] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [60]), .Q(data_bytes_r[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[61] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [61]), .Q(data_bytes_r[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[62] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [62]), .Q(data_bytes_r[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[63] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [63]), .Q(data_bytes_r[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[6] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [6]), .Q(data_bytes_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[7] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [7]), .Q(data_bytes_r[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[8] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [8]), .Q(data_bytes_r[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_bytes_r_reg[9] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [9]), .Q(data_bytes_r[9]), .R(1'b0)); LUT6 #( .INIT(64'h0000010000000000)) \zero_r[9]_i_10 (.I0(data_bytes_r[53]), .I1(data_bytes_r[52]), .I2(data_bytes_r[48]), .I3(data_bytes_r[58]), .I4(data_bytes_r[1]), .I5(data_bytes_r[59]), .O(\zero_r[9]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \zero_r[9]_i_11 (.I0(\zero_r[9]_i_21_n_0 ), .I1(data_bytes_r[56]), .I2(data_bytes_r[38]), .I3(data_bytes_r[42]), .I4(data_bytes_r[35]), .I5(\zero_r[9]_i_22_n_0 ), .O(\zero_r[9]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \zero_r[9]_i_12 (.I0(\zero_r[9]_i_23_n_0 ), .I1(data_bytes_r[2]), .I2(data_bytes_r[3]), .I3(data_bytes_r[30]), .I4(data_bytes_r[39]), .I5(\zero_r[9]_i_24_n_0 ), .O(\zero_r[9]_i_12_n_0 )); LUT5 #( .INIT(32'hFFFFFF7F)) \zero_r[9]_i_13 (.I0(data_bytes_r[25]), .I1(data_bytes_r[9]), .I2(data_bytes_r[12]), .I3(\zero_r[9]_i_25_n_0 ), .I4(\zero_r[9]_i_26_n_0 ), .O(\zero_r[9]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFBFFFFFF)) \zero_r[9]_i_14 (.I0(\zero_r[9]_i_27_n_0 ), .I1(data_bytes_r[32]), .I2(data_bytes_r[29]), .I3(data_bytes_r[21]), .I4(data_bytes_r[19]), .I5(\zero_r[9]_i_28_n_0 ), .O(\zero_r[9]_i_14_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \zero_r[9]_i_15 (.I0(data_bytes_r[14]), .I1(data_bytes_r[30]), .I2(data_bytes_r[31]), .I3(data_bytes_r[46]), .I4(data_bytes_r[48]), .I5(data_bytes_r[54]), .O(\zero_r[9]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \zero_r[9]_i_16 (.I0(\zero_r[9]_i_29_n_0 ), .I1(data_bytes_r[49]), .I2(data_bytes_r[63]), .I3(data_bytes_r[22]), .I4(data_bytes_r[43]), .I5(\zero_r[9]_i_30_n_0 ), .O(\zero_r[9]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFBFFFFFF)) \zero_r[9]_i_17 (.I0(\zero_r[9]_i_31_n_0 ), .I1(data_bytes_r[53]), .I2(data_bytes_r[11]), .I3(data_bytes_r[7]), .I4(data_bytes_r[18]), .I5(\zero_r[9]_i_32_n_0 ), .O(\zero_r[9]_i_17_n_0 )); LUT5 #( .INIT(32'hFFFFFFDF)) \zero_r[9]_i_18 (.I0(data_bytes_r[36]), .I1(data_bytes_r[24]), .I2(data_bytes_r[4]), .I3(\zero_r[9]_i_33_n_0 ), .I4(\zero_r[9]_i_34_n_0 ), .O(\zero_r[9]_i_18_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_19 (.I0(data_bytes_r[43]), .I1(data_bytes_r[6]), .I2(data_bytes_r[54]), .I3(data_bytes_r[37]), .O(\zero_r[9]_i_19_n_0 )); LUT3 #( .INIT(8'h08)) \zero_r[9]_i_2 (.I0(\zero_r_reg[9] ), .I1(\rd_victim_sel_r_reg[0] ), .I2(\zero_r_reg[9]_0 ), .O(E)); LUT5 #( .INIT(32'hFFFF7FFF)) \zero_r[9]_i_20 (.I0(data_bytes_r[40]), .I1(data_bytes_r[29]), .I2(data_bytes_r[27]), .I3(data_bytes_r[60]), .I4(\zero_r[9]_i_35_n_0 ), .O(\zero_r[9]_i_20_n_0 )); LUT4 #( .INIT(16'hFFDF)) \zero_r[9]_i_21 (.I0(data_bytes_r[44]), .I1(data_bytes_r[20]), .I2(agg_samp_r[0]), .I3(data_bytes_r[55]), .O(\zero_r[9]_i_21_n_0 )); LUT5 #( .INIT(32'hFFFFFFFB)) \zero_r[9]_i_22 (.I0(data_bytes_r[19]), .I1(data_bytes_r[63]), .I2(data_bytes_r[5]), .I3(data_bytes_r[4]), .I4(\zero_r[9]_i_36_n_0 ), .O(\zero_r[9]_i_22_n_0 )); LUT4 #( .INIT(16'hFFF7)) \zero_r[9]_i_23 (.I0(data_bytes_r[61]), .I1(data_bytes_r[31]), .I2(data_bytes_r[32]), .I3(data_bytes_r[23]), .O(\zero_r[9]_i_23_n_0 )); LUT5 #( .INIT(32'hFFFFBFFF)) \zero_r[9]_i_24 (.I0(data_bytes_r[34]), .I1(data_bytes_r[41]), .I2(data_bytes_r[45]), .I3(data_bytes_r[14]), .I4(\zero_r[9]_i_37_n_0 ), .O(\zero_r[9]_i_24_n_0 )); LUT4 #( .INIT(16'hFFDF)) \zero_r[9]_i_25 (.I0(data_bytes_r[57]), .I1(data_bytes_r[16]), .I2(data_bytes_r[26]), .I3(data_bytes_r[17]), .O(\zero_r[9]_i_25_n_0 )); LUT4 #( .INIT(16'hEFFF)) \zero_r[9]_i_26 (.I0(data_bytes_r[22]), .I1(data_bytes_r[51]), .I2(data_bytes_r[13]), .I3(data_bytes_r[28]), .O(\zero_r[9]_i_26_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_27 (.I0(data_bytes_r[6]), .I1(data_bytes_r[9]), .I2(data_bytes_r[12]), .I3(data_bytes_r[60]), .O(\zero_r[9]_i_27_n_0 )); LUT5 #( .INIT(32'hFFFFBFFF)) \zero_r[9]_i_28 (.I0(data_bytes_r[47]), .I1(data_bytes_r[51]), .I2(data_bytes_r[55]), .I3(data_bytes_r[34]), .I4(\zero_r[9]_i_38_n_0 ), .O(\zero_r[9]_i_28_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_29 (.I0(data_bytes_r[39]), .I1(data_bytes_r[13]), .I2(data_bytes_r[26]), .I3(data_bytes_r[57]), .O(\zero_r[9]_i_29_n_0 )); LUT5 #( .INIT(32'hFFFFF7FF)) \zero_r[9]_i_30 (.I0(data_bytes_r[0]), .I1(data_bytes_r[5]), .I2(data_bytes_r[59]), .I3(agg_samp_r[1]), .I4(\zero_r[9]_i_39_n_0 ), .O(\zero_r[9]_i_30_n_0 )); LUT4 #( .INIT(16'hEFFF)) \zero_r[9]_i_31 (.I0(data_bytes_r[25]), .I1(data_bytes_r[10]), .I2(data_bytes_r[20]), .I3(data_bytes_r[33]), .O(\zero_r[9]_i_31_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \zero_r[9]_i_32 (.I0(data_bytes_r[27]), .I1(data_bytes_r[56]), .I2(data_bytes_r[8]), .I3(data_bytes_r[17]), .I4(\zero_r[9]_i_40_n_0 ), .O(\zero_r[9]_i_32_n_0 )); LUT4 #( .INIT(16'hFFF7)) \zero_r[9]_i_33 (.I0(data_bytes_r[23]), .I1(data_bytes_r[50]), .I2(data_bytes_r[41]), .I3(data_bytes_r[44]), .O(\zero_r[9]_i_33_n_0 )); LUT4 #( .INIT(16'hFF7F)) \zero_r[9]_i_34 (.I0(data_bytes_r[16]), .I1(data_bytes_r[35]), .I2(data_bytes_r[38]), .I3(data_bytes_r[62]), .O(\zero_r[9]_i_34_n_0 )); LUT4 #( .INIT(16'hFFFE)) \zero_r[9]_i_35 (.I0(data_bytes_r[49]), .I1(data_bytes_r[33]), .I2(data_bytes_r[18]), .I3(data_bytes_r[36]), .O(\zero_r[9]_i_35_n_0 )); LUT4 #( .INIT(16'hFFDF)) \zero_r[9]_i_36 (.I0(data_bytes_r[10]), .I1(data_bytes_r[7]), .I2(data_bytes_r[8]), .I3(data_bytes_r[21]), .O(\zero_r[9]_i_36_n_0 )); LUT4 #( .INIT(16'h7FFF)) \zero_r[9]_i_37 (.I0(data_bytes_r[15]), .I1(data_bytes_r[47]), .I2(data_bytes_r[46]), .I3(data_bytes_r[11]), .O(\zero_r[9]_i_37_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_38 (.I0(data_bytes_r[52]), .I1(data_bytes_r[61]), .I2(data_bytes_r[15]), .I3(data_bytes_r[45]), .O(\zero_r[9]_i_38_n_0 )); LUT4 #( .INIT(16'hFFFE)) \zero_r[9]_i_39 (.I0(data_bytes_r[42]), .I1(data_bytes_r[28]), .I2(data_bytes_r[40]), .I3(data_bytes_r[58]), .O(\zero_r[9]_i_39_n_0 )); LUT4 #( .INIT(16'h7FFF)) \zero_r[9]_i_40 (.I0(data_bytes_r[2]), .I1(data_bytes_r[3]), .I2(data_bytes_r[1]), .I3(data_bytes_r[37]), .O(\zero_r[9]_i_40_n_0 )); LUT5 #( .INIT(32'h00000004)) \zero_r[9]_i_5 (.I0(\zero_r[9]_i_9_n_0 ), .I1(\zero_r[9]_i_10_n_0 ), .I2(\zero_r[9]_i_11_n_0 ), .I3(\zero_r[9]_i_12_n_0 ), .I4(\zero_r[9]_i_13_n_0 ), .O(\zero_r_reg[9] )); LUT5 #( .INIT(32'h00000004)) \zero_r[9]_i_7 (.I0(\zero_r[9]_i_14_n_0 ), .I1(\zero_r[9]_i_15_n_0 ), .I2(\zero_r[9]_i_16_n_0 ), .I3(\zero_r[9]_i_17_n_0 ), .I4(\zero_r[9]_i_18_n_0 ), .O(\zero_r_reg[9]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \zero_r[9]_i_9 (.I0(\zero_r[9]_i_19_n_0 ), .I1(data_bytes_r[24]), .I2(data_bytes_r[50]), .I3(data_bytes_r[62]), .I4(data_bytes_r[0]), .I5(\zero_r[9]_i_20_n_0 ), .O(\zero_r[9]_i_9_n_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_edge" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_edge (prev_samp_valid_r, o2f_r_reg_0, \ninety_offsets_final_r_reg[0] , f2o_r_reg_0, scan_right, prev_samp_r, \ninety_offsets_final_r_reg[1] , dec_po_ns, inc_po_ns, \ninety_offsets_final_r_reg[0]_0 , reset_scan, samp_done_r_reg, CLK, scanning_right_r_reg, scanning_right_r_reg_0, \samp_result_r_reg[1] , \samp_result_r_reg[0] , rd_active_r1_reg, rd_active_r1_reg_0, scanning_right, ocd_ktap_left_r_reg, Q, \stg3_left_lim_reg[5] , rd_active_r1, samp_done, \stg3_right_lim_reg[5] , E, D, reset_scan_r_reg); output prev_samp_valid_r; output o2f_r_reg_0; output \ninety_offsets_final_r_reg[0] ; output f2o_r_reg_0; output scan_right; output [1:0]prev_samp_r; output \ninety_offsets_final_r_reg[1] ; output dec_po_ns; output inc_po_ns; output \ninety_offsets_final_r_reg[0]_0 ; input reset_scan; input samp_done_r_reg; input CLK; input scanning_right_r_reg; input scanning_right_r_reg_0; input \samp_result_r_reg[1] ; input \samp_result_r_reg[0] ; input rd_active_r1_reg; input rd_active_r1_reg_0; input scanning_right; input ocd_ktap_left_r_reg; input [5:0]Q; input [5:0]\stg3_left_lim_reg[5] ; input rd_active_r1; input samp_done; input [5:0]\stg3_right_lim_reg[5] ; input [0:0]E; input [5:0]D; input [0:0]reset_scan_r_reg; wire CLK; wire [5:0]D; wire [0:0]E; wire [5:0]Q; wire dec_po_ns; wire dec_po_r_i_10_n_0; wire dec_po_r_i_11_n_0; wire dec_po_r_i_12_n_0; wire dec_po_r_i_13_n_0; wire dec_po_r_i_14_n_0; wire dec_po_r_i_15_n_0; wire dec_po_r_i_16_n_0; wire dec_po_r_i_17_n_0; wire dec_po_r_i_18_n_0; wire dec_po_r_i_20_n_0; wire dec_po_r_i_21_n_0; wire dec_po_r_i_22_n_0; wire dec_po_r_i_23_n_0; wire dec_po_r_i_24_n_0; wire dec_po_r_i_26_n_0; wire dec_po_r_i_27_n_0; wire dec_po_r_i_28_n_0; wire dec_po_r_i_29_n_0; wire dec_po_r_i_2_n_0; wire dec_po_r_i_30_n_0; wire dec_po_r_i_31_n_0; wire dec_po_r_i_32_n_0; wire dec_po_r_i_3_n_0; wire dec_po_r_i_4_n_0; wire dec_po_r_i_5_n_0; wire dec_po_r_i_6_n_0; wire dec_po_r_i_7_n_0; wire dec_po_r_i_9_n_0; wire dec_po_r_reg_i_19_n_0; wire dec_po_r_reg_i_8_n_0; wire f2o_r_i_1_n_0; wire f2o_r_reg_0; wire \fuzz2oneeighty_r[5]_i_1_n_0 ; wire \fuzz2oneeighty_r[5]_i_2_n_0 ; wire \fuzz2oneeighty_r_reg_n_0_[0] ; wire \fuzz2oneeighty_r_reg_n_0_[1] ; wire \fuzz2oneeighty_r_reg_n_0_[2] ; wire \fuzz2oneeighty_r_reg_n_0_[3] ; wire \fuzz2oneeighty_r_reg_n_0_[4] ; wire \fuzz2oneeighty_r_reg_n_0_[5] ; wire \fuzz2zero_r_reg_n_0_[0] ; wire \fuzz2zero_r_reg_n_0_[1] ; wire \fuzz2zero_r_reg_n_0_[2] ; wire \fuzz2zero_r_reg_n_0_[3] ; wire \fuzz2zero_r_reg_n_0_[4] ; wire \fuzz2zero_r_reg_n_0_[5] ; wire inc_po_ns; wire inc_po_r_i_2_n_0; wire inc_po_r_i_3_n_0; wire inc_po_r_i_4_n_0; wire \ninety_offsets_final_r_reg[0] ; wire \ninety_offsets_final_r_reg[0]_0 ; wire \ninety_offsets_final_r_reg[1] ; wire o2f_r_reg_0; wire ocd_ktap_left_r_reg; wire \oneeighty2fuzz_r_reg_n_0_[0] ; wire \oneeighty2fuzz_r_reg_n_0_[1] ; wire \oneeighty2fuzz_r_reg_n_0_[2] ; wire \oneeighty2fuzz_r_reg_n_0_[3] ; wire \oneeighty2fuzz_r_reg_n_0_[4] ; wire \oneeighty2fuzz_r_reg_n_0_[5] ; wire [1:0]prev_samp_r; wire prev_samp_valid_r; wire rd_active_r1; wire rd_active_r1_reg; wire rd_active_r1_reg_0; wire reset_scan; wire [0:0]reset_scan_r_reg; wire samp_done; wire samp_done_r_reg; wire \samp_result_r_reg[0] ; wire \samp_result_r_reg[1] ; wire scan_right; wire scan_right_r_i_1_n_0; wire scanning_right; wire scanning_right_r_reg; wire scanning_right_r_reg_0; wire [5:0]\stg3_left_lim_reg[5] ; wire [5:0]\stg3_right_lim_reg[5] ; wire \u_ocd_po_cntlr/noise ; wire z2f_r_i_1_n_0; wire z2f_r_reg_n_0; wire zero2fuzz_ns; wire \zero2fuzz_r_reg_n_0_[0] ; wire \zero2fuzz_r_reg_n_0_[1] ; wire \zero2fuzz_r_reg_n_0_[2] ; wire \zero2fuzz_r_reg_n_0_[3] ; wire \zero2fuzz_r_reg_n_0_[4] ; wire \zero2fuzz_r_reg_n_0_[5] ; LUT6 #( .INIT(64'hFEE00000FFFFFEE0)) dec_po_r_i_1 (.I0(dec_po_r_i_2_n_0), .I1(dec_po_r_i_3_n_0), .I2(dec_po_r_i_4_n_0), .I3(Q[4]), .I4(Q[5]), .I5(dec_po_r_i_5_n_0), .O(dec_po_ns)); (* SOFT_HLUTNM = "soft_lutpair361" *) LUT3 #( .INIT(8'h8A)) dec_po_r_i_10 (.I0(\ninety_offsets_final_r_reg[0] ), .I1(z2f_r_reg_n_0), .I2(f2o_r_reg_0), .O(dec_po_r_i_10_n_0)); LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_11 (.I0(\zero2fuzz_r_reg_n_0_[3] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [3]), .I4(\fuzz2oneeighty_r_reg_n_0_[3] ), .O(dec_po_r_i_11_n_0)); LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_12 (.I0(\zero2fuzz_r_reg_n_0_[4] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [4]), .I4(\fuzz2oneeighty_r_reg_n_0_[4] ), .O(dec_po_r_i_12_n_0)); LUT6 #( .INIT(64'h1010001015155515)) dec_po_r_i_13 (.I0(ocd_ktap_left_r_reg), .I1(\zero2fuzz_r_reg_n_0_[4] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(\ninety_offsets_final_r_reg[0] ), .I5(dec_po_r_i_23_n_0), .O(dec_po_r_i_13_n_0)); LUT6 #( .INIT(64'h0000FF00AE00AE00)) dec_po_r_i_14 (.I0(dec_po_r_i_24_n_0), .I1(\u_ocd_po_cntlr/noise ), .I2(\zero2fuzz_r_reg_n_0_[5] ), .I3(ocd_ktap_left_r_reg), .I4(\fuzz2zero_r_reg_n_0_[5] ), .I5(dec_po_r_i_10_n_0), .O(dec_po_r_i_14_n_0)); (* SOFT_HLUTNM = "soft_lutpair362" *) LUT3 #( .INIT(8'h4F)) dec_po_r_i_15 (.I0(\ninety_offsets_final_r_reg[0] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .O(dec_po_r_i_15_n_0)); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_16 (.I0(\fuzz2oneeighty_r_reg_n_0_[5] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [5]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[5] ), .O(dec_po_r_i_16_n_0)); LUT6 #( .INIT(64'h0000000035355535)) dec_po_r_i_17 (.I0(dec_po_r_i_26_n_0), .I1(\zero2fuzz_r_reg_n_0_[1] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(\ninety_offsets_final_r_reg[0] ), .I5(ocd_ktap_left_r_reg), .O(dec_po_r_i_17_n_0)); LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_18 (.I0(\zero2fuzz_r_reg_n_0_[1] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [1]), .I4(\fuzz2oneeighty_r_reg_n_0_[1] ), .O(dec_po_r_i_18_n_0)); LUT6 #( .INIT(64'h008E00FF0000008E)) dec_po_r_i_2 (.I0(Q[1]), .I1(dec_po_r_i_6_n_0), .I2(dec_po_r_i_7_n_0), .I3(inc_po_r_i_3_n_0), .I4(dec_po_r_reg_i_8_n_0), .I5(Q[2]), .O(dec_po_r_i_2_n_0)); LUT5 #( .INIT(32'hEFAA20AA)) dec_po_r_i_20 (.I0(dec_po_r_i_29_n_0), .I1(\ninety_offsets_final_r_reg[0] ), .I2(f2o_r_reg_0), .I3(z2f_r_reg_n_0), .I4(\zero2fuzz_r_reg_n_0_[2] ), .O(dec_po_r_i_20_n_0)); LUT5 #( .INIT(32'hBFBB8088)) dec_po_r_i_21 (.I0(\fuzz2zero_r_reg_n_0_[2] ), .I1(\ninety_offsets_final_r_reg[0] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(dec_po_r_i_30_n_0), .O(dec_po_r_i_21_n_0)); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_22 (.I0(\fuzz2oneeighty_r_reg_n_0_[3] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [3]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[3] ), .O(dec_po_r_i_22_n_0)); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_23 (.I0(\fuzz2oneeighty_r_reg_n_0_[4] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [4]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[4] ), .O(dec_po_r_i_23_n_0)); (* SOFT_HLUTNM = "soft_lutpair361" *) LUT4 #( .INIT(16'h0437)) dec_po_r_i_24 (.I0(\fuzz2oneeighty_r_reg_n_0_[5] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [5]), .O(dec_po_r_i_24_n_0)); (* SOFT_HLUTNM = "soft_lutpair359" *) LUT2 #( .INIT(4'h8)) dec_po_r_i_25 (.I0(f2o_r_reg_0), .I1(z2f_r_reg_n_0), .O(\u_ocd_po_cntlr/noise )); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_26 (.I0(\fuzz2oneeighty_r_reg_n_0_[1] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [1]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[1] ), .O(dec_po_r_i_26_n_0)); LUT5 #( .INIT(32'h8A00BAFF)) dec_po_r_i_27 (.I0(\zero2fuzz_r_reg_n_0_[0] ), .I1(\ninety_offsets_final_r_reg[0] ), .I2(f2o_r_reg_0), .I3(z2f_r_reg_n_0), .I4(dec_po_r_i_31_n_0), .O(dec_po_r_i_27_n_0)); LUT5 #( .INIT(32'hBFBB8088)) dec_po_r_i_28 (.I0(\fuzz2zero_r_reg_n_0_[0] ), .I1(\ninety_offsets_final_r_reg[0] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(dec_po_r_i_32_n_0), .O(dec_po_r_i_28_n_0)); LUT6 #( .INIT(64'hFFAAE2AA00AAE2AA)) dec_po_r_i_29 (.I0(\stg3_right_lim_reg[5] [2]), .I1(o2f_r_reg_0), .I2(\oneeighty2fuzz_r_reg_n_0_[2] ), .I3(f2o_r_reg_0), .I4(z2f_r_reg_n_0), .I5(\fuzz2oneeighty_r_reg_n_0_[2] ), .O(dec_po_r_i_29_n_0)); LUT6 #( .INIT(64'hAEAABFAA00000000)) dec_po_r_i_3 (.I0(dec_po_r_i_9_n_0), .I1(dec_po_r_i_10_n_0), .I2(\fuzz2zero_r_reg_n_0_[3] ), .I3(ocd_ktap_left_r_reg), .I4(dec_po_r_i_11_n_0), .I5(Q[3]), .O(dec_po_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair359" *) LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_30 (.I0(\zero2fuzz_r_reg_n_0_[2] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [2]), .I4(\fuzz2oneeighty_r_reg_n_0_[2] ), .O(dec_po_r_i_30_n_0)); LUT6 #( .INIT(64'h00FF55551D1D5555)) dec_po_r_i_31 (.I0(\stg3_right_lim_reg[5] [0]), .I1(o2f_r_reg_0), .I2(\oneeighty2fuzz_r_reg_n_0_[0] ), .I3(\fuzz2oneeighty_r_reg_n_0_[0] ), .I4(f2o_r_reg_0), .I5(z2f_r_reg_n_0), .O(dec_po_r_i_31_n_0)); (* SOFT_HLUTNM = "soft_lutpair360" *) LUT5 #( .INIT(32'hFACA0ACA)) dec_po_r_i_32 (.I0(\stg3_left_lim_reg[5] [0]), .I1(\fuzz2oneeighty_r_reg_n_0_[0] ), .I2(f2o_r_reg_0), .I3(z2f_r_reg_n_0), .I4(\zero2fuzz_r_reg_n_0_[0] ), .O(dec_po_r_i_32_n_0)); LUT5 #( .INIT(32'hFFFF2070)) dec_po_r_i_4 (.I0(dec_po_r_i_10_n_0), .I1(\fuzz2zero_r_reg_n_0_[4] ), .I2(ocd_ktap_left_r_reg), .I3(dec_po_r_i_12_n_0), .I4(dec_po_r_i_13_n_0), .O(dec_po_r_i_4_n_0)); LUT5 #( .INIT(32'h55544544)) dec_po_r_i_5 (.I0(dec_po_r_i_14_n_0), .I1(ocd_ktap_left_r_reg), .I2(dec_po_r_i_15_n_0), .I3(\zero2fuzz_r_reg_n_0_[5] ), .I4(dec_po_r_i_16_n_0), .O(dec_po_r_i_5_n_0)); LUT5 #( .INIT(32'hABEFAAAA)) dec_po_r_i_6 (.I0(dec_po_r_i_17_n_0), .I1(dec_po_r_i_10_n_0), .I2(dec_po_r_i_18_n_0), .I3(\fuzz2zero_r_reg_n_0_[1] ), .I4(ocd_ktap_left_r_reg), .O(dec_po_r_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair363" *) LUT2 #( .INIT(4'hB)) dec_po_r_i_7 (.I0(dec_po_r_reg_i_19_n_0), .I1(Q[0]), .O(dec_po_r_i_7_n_0)); LUT6 #( .INIT(64'h1010001015155515)) dec_po_r_i_9 (.I0(ocd_ktap_left_r_reg), .I1(\zero2fuzz_r_reg_n_0_[3] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(\ninety_offsets_final_r_reg[0] ), .I5(dec_po_r_i_22_n_0), .O(dec_po_r_i_9_n_0)); MUXF7 dec_po_r_reg_i_19 (.I0(dec_po_r_i_27_n_0), .I1(dec_po_r_i_28_n_0), .O(dec_po_r_reg_i_19_n_0), .S(ocd_ktap_left_r_reg)); MUXF7 dec_po_r_reg_i_8 (.I0(dec_po_r_i_20_n_0), .I1(dec_po_r_i_21_n_0), .O(dec_po_r_reg_i_8_n_0), .S(ocd_ktap_left_r_reg)); LUT6 #( .INIT(64'hFFFFFFFF00000020)) f2o_r_i_1 (.I0(rd_active_r1_reg), .I1(rd_active_r1_reg_0), .I2(scanning_right), .I3(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I4(prev_samp_r[1]), .I5(f2o_r_reg_0), .O(f2o_r_i_1_n_0)); FDRE #( .INIT(1'b0)) f2o_r_reg (.C(CLK), .CE(1'b1), .D(f2o_r_i_1_n_0), .Q(f2o_r_reg_0), .R(reset_scan)); FDRE #( .INIT(1'b0)) f2z_r_reg (.C(CLK), .CE(1'b1), .D(scanning_right_r_reg_0), .Q(\ninety_offsets_final_r_reg[0] ), .R(reset_scan)); LUT6 #( .INIT(64'h0000000000100000)) \fuzz2oneeighty_r[5]_i_1 (.I0(prev_samp_r[1]), .I1(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I2(scanning_right), .I3(rd_active_r1_reg_0), .I4(rd_active_r1_reg), .I5(reset_scan), .O(\fuzz2oneeighty_r[5]_i_1_n_0 )); LUT3 #( .INIT(8'h7F)) \fuzz2oneeighty_r[5]_i_2 (.I0(prev_samp_valid_r), .I1(rd_active_r1), .I2(samp_done), .O(\fuzz2oneeighty_r[5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \fuzz2oneeighty_r_reg[0] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[0]), .Q(\fuzz2oneeighty_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2oneeighty_r_reg[1] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[1]), .Q(\fuzz2oneeighty_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2oneeighty_r_reg[2] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[2]), .Q(\fuzz2oneeighty_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2oneeighty_r_reg[3] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[3]), .Q(\fuzz2oneeighty_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2oneeighty_r_reg[4] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[4]), .Q(\fuzz2oneeighty_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2oneeighty_r_reg[5] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[5]), .Q(\fuzz2oneeighty_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2zero_r_reg[0] (.C(CLK), .CE(E), .D(Q[0]), .Q(\fuzz2zero_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2zero_r_reg[1] (.C(CLK), .CE(E), .D(Q[1]), .Q(\fuzz2zero_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2zero_r_reg[2] (.C(CLK), .CE(E), .D(Q[2]), .Q(\fuzz2zero_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2zero_r_reg[3] (.C(CLK), .CE(E), .D(Q[3]), .Q(\fuzz2zero_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2zero_r_reg[4] (.C(CLK), .CE(E), .D(Q[4]), .Q(\fuzz2zero_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \fuzz2zero_r_reg[5] (.C(CLK), .CE(E), .D(Q[5]), .Q(\fuzz2zero_r_reg_n_0_[5] ), .R(1'b0)); LUT6 #( .INIT(64'h70F770F770F710F1)) inc_po_r_i_1 (.I0(dec_po_r_i_4_n_0), .I1(Q[4]), .I2(dec_po_r_i_5_n_0), .I3(Q[5]), .I4(inc_po_r_i_2_n_0), .I5(inc_po_r_i_3_n_0), .O(inc_po_ns)); LUT6 #( .INIT(64'h0000000071FF0071)) inc_po_r_i_2 (.I0(dec_po_r_i_6_n_0), .I1(Q[1]), .I2(inc_po_r_i_4_n_0), .I3(Q[2]), .I4(dec_po_r_reg_i_8_n_0), .I5(dec_po_r_i_3_n_0), .O(inc_po_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000051554055)) inc_po_r_i_3 (.I0(dec_po_r_i_9_n_0), .I1(dec_po_r_i_10_n_0), .I2(\fuzz2zero_r_reg_n_0_[3] ), .I3(ocd_ktap_left_r_reg), .I4(dec_po_r_i_11_n_0), .I5(Q[3]), .O(inc_po_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair363" *) LUT2 #( .INIT(4'h2)) inc_po_r_i_4 (.I0(dec_po_r_reg_i_19_n_0), .I1(Q[0]), .O(inc_po_r_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair362" *) LUT3 #( .INIT(8'h20)) \ninety_offsets_final_r[0]_i_1 (.I0(f2o_r_reg_0), .I1(\ninety_offsets_final_r_reg[0] ), .I2(z2f_r_reg_n_0), .O(\ninety_offsets_final_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair360" *) LUT2 #( .INIT(4'h2)) \ninety_offsets_final_r[1]_i_1 (.I0(f2o_r_reg_0), .I1(z2f_r_reg_n_0), .O(\ninety_offsets_final_r_reg[1] )); FDRE #( .INIT(1'b0)) o2f_r_reg (.C(CLK), .CE(1'b1), .D(scanning_right_r_reg), .Q(o2f_r_reg_0), .R(reset_scan)); FDRE #( .INIT(1'b0)) \oneeighty2fuzz_r_reg[0] (.C(CLK), .CE(reset_scan_r_reg), .D(D[0]), .Q(\oneeighty2fuzz_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \oneeighty2fuzz_r_reg[1] (.C(CLK), .CE(reset_scan_r_reg), .D(D[1]), .Q(\oneeighty2fuzz_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \oneeighty2fuzz_r_reg[2] (.C(CLK), .CE(reset_scan_r_reg), .D(D[2]), .Q(\oneeighty2fuzz_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \oneeighty2fuzz_r_reg[3] (.C(CLK), .CE(reset_scan_r_reg), .D(D[3]), .Q(\oneeighty2fuzz_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \oneeighty2fuzz_r_reg[4] (.C(CLK), .CE(reset_scan_r_reg), .D(D[4]), .Q(\oneeighty2fuzz_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \oneeighty2fuzz_r_reg[5] (.C(CLK), .CE(reset_scan_r_reg), .D(D[5]), .Q(\oneeighty2fuzz_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_samp_r_reg[0] (.C(CLK), .CE(1'b1), .D(\samp_result_r_reg[0] ), .Q(prev_samp_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_samp_r_reg[1] (.C(CLK), .CE(1'b1), .D(\samp_result_r_reg[1] ), .Q(prev_samp_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) prev_samp_valid_r_reg (.C(CLK), .CE(1'b1), .D(samp_done_r_reg), .Q(prev_samp_valid_r), .R(reset_scan)); LUT6 #( .INIT(64'h0000000000000010)) scan_right_r_i_1 (.I0(rd_active_r1_reg_0), .I1(scanning_right), .I2(prev_samp_r[0]), .I3(prev_samp_r[1]), .I4(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I5(reset_scan), .O(scan_right_r_i_1_n_0)); FDRE #( .INIT(1'b0)) scan_right_r_reg (.C(CLK), .CE(1'b1), .D(scan_right_r_i_1_n_0), .Q(scan_right), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000400)) z2f_r_i_1 (.I0(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I1(scanning_right), .I2(rd_active_r1_reg_0), .I3(prev_samp_r[0]), .I4(prev_samp_r[1]), .I5(z2f_r_reg_n_0), .O(z2f_r_i_1_n_0)); FDRE #( .INIT(1'b0)) z2f_r_reg (.C(CLK), .CE(1'b1), .D(z2f_r_i_1_n_0), .Q(z2f_r_reg_n_0), .R(reset_scan)); LUT6 #( .INIT(64'h0000000000000400)) \zero2fuzz_r[5]_i_1 (.I0(prev_samp_r[1]), .I1(prev_samp_r[0]), .I2(rd_active_r1_reg_0), .I3(scanning_right), .I4(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I5(reset_scan), .O(zero2fuzz_ns)); FDRE #( .INIT(1'b0)) \zero2fuzz_r_reg[0] (.C(CLK), .CE(zero2fuzz_ns), .D(D[0]), .Q(\zero2fuzz_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \zero2fuzz_r_reg[1] (.C(CLK), .CE(zero2fuzz_ns), .D(D[1]), .Q(\zero2fuzz_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \zero2fuzz_r_reg[2] (.C(CLK), .CE(zero2fuzz_ns), .D(D[2]), .Q(\zero2fuzz_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \zero2fuzz_r_reg[3] (.C(CLK), .CE(zero2fuzz_ns), .D(D[3]), .Q(\zero2fuzz_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \zero2fuzz_r_reg[4] (.C(CLK), .CE(zero2fuzz_ns), .D(D[4]), .Q(\zero2fuzz_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \zero2fuzz_r_reg[5] (.C(CLK), .CE(zero2fuzz_ns), .D(D[5]), .Q(\zero2fuzz_r_reg_n_0_[5] ), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_lim" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_lim (lim_start_r, lim2poc_ktap_right, prech_req_r_reg_0, lim2stg2_inc, lim2stg3_dec, lim2stg3_inc, lim2stg2_dec, lim2poc_rdy, done_r_reg_0, po_stg23_sel_r_reg, stg3_dec2init_val_r_reg_0, stg3_inc2init_val_r_reg_0, \stg2_tap_cnt_reg[0]_0 , \stg2_tap_cnt_reg[3]_0 , \stg3_tap_cnt_reg[2]_0 , scanning_right_r_reg, scanning_right_r_reg_0, oclkdelay_center_calib_start_r_reg, oclkdelay_center_calib_start_r_reg_0, \init_state_r_reg[6] , \init_state_r_reg[5] , \init_state_r_reg[4] , rstdiv0_sync_r1_reg_rep__10, CLK, lim_start, rstdiv0_sync_r1_reg_rep__9, done_r_reg_1, rstdiv0_sync_r1_reg_rep__25, \po_wait_r_reg[0] , \sm_r_reg[2] , lim_start_r_reg_0, prech_done, \wl_po_fine_cnt_reg[17] , rstdiv0_sync_r1_reg_rep__20, \byte_r_reg[0] , Q, \stg2_tap_cnt_reg[2]_0 , \wl_po_fine_cnt_reg[3] , \wl_po_fine_cnt_reg[14] , \wl_po_fine_cnt_reg[18] , \rise_lead_r_reg[5] , rstdiv0_sync_r1_reg_rep__25_0, po_rdy, scan_right, scanning_right, \stg3_r_reg[5] , o2f_r_reg, \mmcm_init_trail_reg[0]_0 , \mmcm_current_reg[0]_0 , prbs_rdlvl_done_reg_rep, ocd_prech_req_r_reg, oclk_center_write_resume, cnt_cmd_done_r, rstdiv0_sync_r1_reg_rep__19, rstdiv0_sync_r1_reg_rep__11, D, oclkdelay_calib_done_r_reg); output lim_start_r; output lim2poc_ktap_right; output prech_req_r_reg_0; output lim2stg2_inc; output lim2stg3_dec; output lim2stg3_inc; output lim2stg2_dec; output lim2poc_rdy; output done_r_reg_0; output po_stg23_sel_r_reg; output stg3_dec2init_val_r_reg_0; output stg3_inc2init_val_r_reg_0; output \stg2_tap_cnt_reg[0]_0 ; output [2:0]\stg2_tap_cnt_reg[3]_0 ; output [2:0]\stg3_tap_cnt_reg[2]_0 ; output scanning_right_r_reg; output [5:0]scanning_right_r_reg_0; output oclkdelay_center_calib_start_r_reg; output [5:0]oclkdelay_center_calib_start_r_reg_0; output \init_state_r_reg[6] ; output \init_state_r_reg[5] ; output \init_state_r_reg[4] ; input rstdiv0_sync_r1_reg_rep__10; input CLK; input lim_start; input rstdiv0_sync_r1_reg_rep__9; input done_r_reg_1; input rstdiv0_sync_r1_reg_rep__25; input \po_wait_r_reg[0] ; input \sm_r_reg[2] ; input lim_start_r_reg_0; input prech_done; input \wl_po_fine_cnt_reg[17] ; input rstdiv0_sync_r1_reg_rep__20; input \byte_r_reg[0] ; input [5:0]Q; input \stg2_tap_cnt_reg[2]_0 ; input \wl_po_fine_cnt_reg[3] ; input [1:0]\wl_po_fine_cnt_reg[14] ; input \wl_po_fine_cnt_reg[18] ; input [5:0]\rise_lead_r_reg[5] ; input rstdiv0_sync_r1_reg_rep__25_0; input po_rdy; input scan_right; input scanning_right; input [5:0]\stg3_r_reg[5] ; input o2f_r_reg; input \mmcm_init_trail_reg[0]_0 ; input \mmcm_current_reg[0]_0 ; input prbs_rdlvl_done_reg_rep; input ocd_prech_req_r_reg; input oclk_center_write_resume; input cnt_cmd_done_r; input [0:0]rstdiv0_sync_r1_reg_rep__19; input rstdiv0_sync_r1_reg_rep__11; input [2:0]D; input [5:0]oclkdelay_calib_done_r_reg; wire CLK; wire [2:0]D; wire [5:0]Q; wire \byte_r_reg[0] ; wire cnt_cmd_done_r; wire detect_done_r; wire done_r_i_1__0_n_0; wire done_r_reg_0; wire done_r_reg_1; wire \init_state_r_reg[4] ; wire \init_state_r_reg[5] ; wire \init_state_r_reg[6] ; wire ktap_right_r_i_1_n_0; wire ktap_right_r_i_2_n_0; wire lim2init_write_request; wire lim2poc_ktap_right; wire lim2poc_rdy; wire lim2stg2_dec; wire lim2stg2_inc; wire lim2stg3_dec; wire lim2stg3_inc; wire lim_nxt_state; wire lim_start; wire lim_start_r; wire lim_start_r_reg_0; wire [13:0]lim_state; wire \lim_state[0]_i_1_n_0 ; wire \lim_state[0]_i_2_n_0 ; wire \lim_state[0]_i_3_n_0 ; wire \lim_state[0]_i_4_n_0 ; wire \lim_state[0]_i_5_n_0 ; wire \lim_state[10]_i_1_n_0 ; wire \lim_state[10]_i_2_n_0 ; wire \lim_state[10]_i_3_n_0 ; wire \lim_state[11]_i_1_n_0 ; wire \lim_state[11]_i_2_n_0 ; wire \lim_state[11]_i_3_n_0 ; wire \lim_state[11]_i_4_n_0 ; wire \lim_state[11]_i_5_n_0 ; wire \lim_state[11]_i_6_n_0 ; wire \lim_state[11]_i_7_n_0 ; wire \lim_state[12]_i_1_n_0 ; wire \lim_state[12]_i_2_n_0 ; wire \lim_state[12]_i_3_n_0 ; wire \lim_state[12]_i_4_n_0 ; wire \lim_state[12]_i_5_n_0 ; wire \lim_state[12]_i_7_n_0 ; wire \lim_state[13]_i_10_n_0 ; wire \lim_state[13]_i_11_n_0 ; wire \lim_state[13]_i_12_n_0 ; wire \lim_state[13]_i_13_n_0 ; wire \lim_state[13]_i_14_n_0 ; wire \lim_state[13]_i_2_n_0 ; wire \lim_state[13]_i_3_n_0 ; wire \lim_state[13]_i_4_n_0 ; wire \lim_state[13]_i_5_n_0 ; wire \lim_state[13]_i_6_n_0 ; wire \lim_state[13]_i_7_n_0 ; wire \lim_state[13]_i_8_n_0 ; wire \lim_state[13]_i_9_n_0 ; wire \lim_state[1]_i_1_n_0 ; wire \lim_state[1]_i_2_n_0 ; wire \lim_state[2]_i_1_n_0 ; wire \lim_state[2]_i_2_n_0 ; wire \lim_state[2]_i_3_n_0 ; wire \lim_state[2]_i_4_n_0 ; wire \lim_state[3]_i_1_n_0 ; wire \lim_state[4]_i_1_n_0 ; wire \lim_state[4]_i_2_n_0 ; wire \lim_state[4]_i_3_n_0 ; wire \lim_state[5]_i_1_n_0 ; wire \lim_state[5]_i_2_n_0 ; wire \lim_state[6]_i_10_n_0 ; wire \lim_state[6]_i_11_n_0 ; wire \lim_state[6]_i_12_n_0 ; wire \lim_state[6]_i_13_n_0 ; wire \lim_state[6]_i_14_n_0 ; wire \lim_state[6]_i_15_n_0 ; wire \lim_state[6]_i_16_n_0 ; wire \lim_state[6]_i_17_n_0 ; wire \lim_state[6]_i_18_n_0 ; wire \lim_state[6]_i_19_n_0 ; wire \lim_state[6]_i_1_n_0 ; wire \lim_state[6]_i_20_n_0 ; wire \lim_state[6]_i_21_n_0 ; wire \lim_state[6]_i_22_n_0 ; wire \lim_state[6]_i_2_n_0 ; wire \lim_state[6]_i_3_n_0 ; wire \lim_state[6]_i_4_n_0 ; wire \lim_state[6]_i_5_n_0 ; wire \lim_state[6]_i_6_n_0 ; wire \lim_state[6]_i_7_n_0 ; wire \lim_state[6]_i_8_n_0 ; wire \lim_state[6]_i_9_n_0 ; wire \lim_state[7]_i_1_n_0 ; wire \lim_state[7]_i_2_n_0 ; wire \lim_state[7]_i_3_n_0 ; wire \lim_state[8]_i_1_n_0 ; wire \lim_state[9]_i_1_n_0 ; wire \lim_state[9]_i_2_n_0 ; wire \lim_state[9]_i_3_n_0 ; wire \mmcm_current[0]_i_1_n_0 ; wire \mmcm_current[0]_i_2_n_0 ; wire \mmcm_current[1]_i_1_n_0 ; wire \mmcm_current[1]_i_2_n_0 ; wire \mmcm_current[2]_i_1_n_0 ; wire \mmcm_current[2]_i_2_n_0 ; wire \mmcm_current[3]_i_1_n_0 ; wire \mmcm_current[3]_i_2_n_0 ; wire \mmcm_current[4]_i_1_n_0 ; wire \mmcm_current[4]_i_2_n_0 ; wire \mmcm_current[5]_i_1_n_0 ; wire \mmcm_current[5]_i_2_n_0 ; wire \mmcm_current_reg[0]_0 ; wire \mmcm_current_reg_n_0_[0] ; wire \mmcm_current_reg_n_0_[1] ; wire \mmcm_current_reg_n_0_[2] ; wire \mmcm_current_reg_n_0_[3] ; wire \mmcm_current_reg_n_0_[4] ; wire \mmcm_current_reg_n_0_[5] ; wire mmcm_init_lead; wire \mmcm_init_lead[5]_i_2_n_0 ; wire \mmcm_init_lead[5]_i_3_n_0 ; wire \mmcm_init_lead[5]_i_4_n_0 ; wire \mmcm_init_lead[5]_i_5_n_0 ; wire \mmcm_init_lead[5]_i_6_n_0 ; wire \mmcm_init_lead[5]_i_7_n_0 ; wire \mmcm_init_lead[5]_i_8_n_0 ; wire \mmcm_init_lead_reg_n_0_[0] ; wire \mmcm_init_lead_reg_n_0_[1] ; wire \mmcm_init_lead_reg_n_0_[2] ; wire \mmcm_init_lead_reg_n_0_[3] ; wire \mmcm_init_lead_reg_n_0_[4] ; wire \mmcm_init_lead_reg_n_0_[5] ; wire mmcm_init_trail; wire \mmcm_init_trail[5]_i_2_n_0 ; wire \mmcm_init_trail[5]_i_3_n_0 ; wire \mmcm_init_trail[5]_i_4_n_0 ; wire \mmcm_init_trail_reg[0]_0 ; wire \mmcm_init_trail_reg_n_0_[0] ; wire \mmcm_init_trail_reg_n_0_[1] ; wire \mmcm_init_trail_reg_n_0_[2] ; wire \mmcm_init_trail_reg_n_0_[3] ; wire \mmcm_init_trail_reg_n_0_[4] ; wire \mmcm_init_trail_reg_n_0_[5] ; wire mod_sub0_return0__14_carry__0_i_1_n_0; wire mod_sub0_return0__14_carry__0_i_2_n_0; wire mod_sub0_return0__14_carry__0_n_1; wire mod_sub0_return0__14_carry__0_n_3; wire mod_sub0_return0__14_carry__0_n_6; wire mod_sub0_return0__14_carry__0_n_7; wire mod_sub0_return0__14_carry_i_1_n_0; wire mod_sub0_return0__14_carry_i_2_n_0; wire mod_sub0_return0__14_carry_i_3_n_0; wire mod_sub0_return0__14_carry_i_4_n_0; wire mod_sub0_return0__14_carry_n_0; wire mod_sub0_return0__14_carry_n_1; wire mod_sub0_return0__14_carry_n_2; wire mod_sub0_return0__14_carry_n_3; wire mod_sub0_return0__14_carry_n_4; wire mod_sub0_return0__14_carry_n_5; wire mod_sub0_return0__14_carry_n_6; wire mod_sub0_return0_carry__0_i_1_n_0; wire mod_sub0_return0_carry__0_i_2_n_0; wire mod_sub0_return0_carry__0_i_3_n_0; wire mod_sub0_return0_carry__0_i_4_n_0; wire mod_sub0_return0_carry__0_i_5_n_0; wire mod_sub0_return0_carry__0_n_2; wire mod_sub0_return0_carry__0_n_3; wire mod_sub0_return0_carry__0_n_5; wire mod_sub0_return0_carry__0_n_6; wire mod_sub0_return0_carry__0_n_7; wire mod_sub0_return0_carry_i_1_n_0; wire mod_sub0_return0_carry_i_2_n_0; wire mod_sub0_return0_carry_i_3_n_0; wire mod_sub0_return0_carry_i_4_n_0; wire mod_sub0_return0_carry_n_0; wire mod_sub0_return0_carry_n_1; wire mod_sub0_return0_carry_n_2; wire mod_sub0_return0_carry_n_3; wire mod_sub0_return0_carry_n_4; wire mod_sub0_return0_carry_n_5; wire mod_sub0_return0_carry_n_6; wire mod_sub0_return0_carry_n_7; wire mod_sub_return0__14_carry__0_i_1_n_0; wire mod_sub_return0__14_carry__0_i_2_n_0; wire mod_sub_return0__14_carry__0_n_1; wire mod_sub_return0__14_carry__0_n_3; wire mod_sub_return0__14_carry__0_n_6; wire mod_sub_return0__14_carry__0_n_7; wire mod_sub_return0__14_carry_i_1_n_0; wire mod_sub_return0__14_carry_i_2_n_0; wire mod_sub_return0__14_carry_i_3_n_0; wire mod_sub_return0__14_carry_i_4_n_0; wire mod_sub_return0__14_carry_n_0; wire mod_sub_return0__14_carry_n_1; wire mod_sub_return0__14_carry_n_2; wire mod_sub_return0__14_carry_n_3; wire mod_sub_return0__14_carry_n_4; wire mod_sub_return0__14_carry_n_5; wire mod_sub_return0__14_carry_n_6; wire mod_sub_return0_carry__0_i_1__0_n_0; wire mod_sub_return0_carry__0_i_2_n_0; wire mod_sub_return0_carry__0_i_3_n_0; wire mod_sub_return0_carry__0_i_4_n_0; wire mod_sub_return0_carry__0_i_5_n_0; wire mod_sub_return0_carry__0_n_2; wire mod_sub_return0_carry__0_n_3; wire mod_sub_return0_carry__0_n_5; wire mod_sub_return0_carry__0_n_6; wire mod_sub_return0_carry__0_n_7; wire mod_sub_return0_carry_i_1__0_n_0; wire mod_sub_return0_carry_i_2_n_0; wire mod_sub_return0_carry_i_3_n_0; wire mod_sub_return0_carry_i_4_n_0; wire mod_sub_return0_carry_n_0; wire mod_sub_return0_carry_n_1; wire mod_sub_return0_carry_n_2; wire mod_sub_return0_carry_n_3; wire mod_sub_return0_carry_n_4; wire mod_sub_return0_carry_n_5; wire mod_sub_return0_carry_n_6; wire mod_sub_return0_carry_n_7; wire o2f_r_reg; wire ocd_prech_req_r_reg; wire oclk_center_write_resume; wire [5:0]oclkdelay_calib_done_r_reg; wire oclkdelay_center_calib_start_r_i_3_n_0; wire oclkdelay_center_calib_start_r_i_4_n_0; wire oclkdelay_center_calib_start_r_reg; wire [5:0]oclkdelay_center_calib_start_r_reg_0; wire [3:0]p_0_in; wire [5:0]p_0_in__0; wire po_rdy; wire po_stg23_sel_r_reg; wire \po_wait_r_reg[0] ; wire poc_ready_r_i_1_n_0; wire prbs_rdlvl_done_reg_rep; wire prech_done; wire prech_req_r_i_1__0_n_0; wire prech_req_r_i_2_n_0; wire prech_req_r_reg_0; wire [5:0]\rise_lead_r_reg[5] ; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__9; wire scan_right; wire scanning_right; wire scanning_right_r_i_4_n_0; wire scanning_right_r_i_5_n_0; wire scanning_right_r_reg; wire [5:0]scanning_right_r_reg_0; wire \sm_r_reg[2] ; wire stg2_dec_req_r_i_1_n_0; wire stg2_inc_r; wire stg2_inc_r_i_1_n_0; wire stg2_inc_r_i_2_n_0; wire stg2_inc_r_i_3_n_0; wire stg2_inc_r_i_4_n_0; wire stg2_inc_req_r_i_1_n_0; wire stg2_inc_req_r_i_2_n_0; wire stg2_tap_cnt0; wire \stg2_tap_cnt[1]_i_3_n_0 ; wire \stg2_tap_cnt[1]_i_4_n_0 ; wire \stg2_tap_cnt[2]_i_3_n_0 ; wire \stg2_tap_cnt[2]_i_4_n_0 ; wire \stg2_tap_cnt[2]_i_5_n_0 ; wire \stg2_tap_cnt[2]_i_6_n_0 ; wire \stg2_tap_cnt[3]_i_3_n_0 ; wire \stg2_tap_cnt[4]_i_3_n_0 ; wire \stg2_tap_cnt[5]_i_6_n_0 ; wire \stg2_tap_cnt_reg[0]_0 ; wire \stg2_tap_cnt_reg[2]_0 ; wire [2:0]\stg2_tap_cnt_reg[3]_0 ; wire [5:3]stg2_tap_cnt_reg__0; wire stg3_dec2init_val_r; wire stg3_dec2init_val_r1; wire stg3_dec2init_val_r_i_10_n_0; wire stg3_dec2init_val_r_i_12_n_0; wire stg3_dec2init_val_r_i_13_n_0; wire stg3_dec2init_val_r_i_1_n_0; wire stg3_dec2init_val_r_i_2_n_0; wire stg3_dec2init_val_r_i_3_n_0; wire stg3_dec2init_val_r_i_4_n_0; wire stg3_dec2init_val_r_i_5_n_0; wire stg3_dec2init_val_r_i_6_n_0; wire stg3_dec2init_val_r_i_7_n_0; wire stg3_dec2init_val_r_i_8_n_0; wire stg3_dec2init_val_r_i_9_n_0; wire stg3_dec2init_val_r_reg_0; wire stg3_dec_r; wire stg3_dec_r_i_1_n_0; wire stg3_dec_r_i_2_n_0; wire stg3_dec_r_i_3_n_0; wire stg3_dec_r_i_4_n_0; wire stg3_dec_r_i_5_n_0; wire stg3_dec_req_r_i_1_n_0; wire stg3_dec_req_r_i_2_n_0; wire stg3_dec_req_r_i_3_n_0; wire [5:0]stg3_dec_val; wire [4:3]stg3_dec_val00_out; wire \stg3_dec_val[5]_i_1_n_0 ; wire \stg3_dec_val[5]_i_2_n_0 ; wire \stg3_dec_val[5]_i_3_n_0 ; wire stg3_inc2init_val_r; wire stg3_inc2init_val_r1; wire stg3_inc2init_val_r_i_1_n_0; wire stg3_inc2init_val_r_i_2_n_0; wire stg3_inc2init_val_r_i_3_n_0; wire stg3_inc2init_val_r_reg_0; wire stg3_inc_req_r_i_1_n_0; wire [5:0]stg3_inc_val; wire \stg3_inc_val[0]_i_1_n_0 ; wire \stg3_inc_val[1]_i_1_n_0 ; wire \stg3_inc_val[2]_i_1_n_0 ; wire \stg3_inc_val[2]_i_2_n_0 ; wire \stg3_inc_val[3]_i_1_n_0 ; wire \stg3_inc_val[3]_i_2_n_0 ; wire \stg3_inc_val[4]_i_1_n_0 ; wire \stg3_inc_val[5]_i_1_n_0 ; wire \stg3_inc_val[5]_i_2_n_0 ; wire \stg3_inc_val[5]_i_3_n_0 ; wire stg3_init_dec_r; wire stg3_init_dec_r_i_1_n_0; wire stg3_init_dec_r_i_2_n_0; wire stg3_init_dec_r_i_3_n_0; wire stg3_init_dec_r_i_4_n_0; wire [5:3]stg3_init_val; wire stg3_left_lim0; wire \stg3_left_lim[5]_i_1_n_0 ; wire [5:0]\stg3_r_reg[5] ; wire stg3_right_lim0; wire \stg3_right_lim[5]_i_1_n_0 ; wire stg3_tap_cnt0; wire \stg3_tap_cnt[0]_i_1_n_0 ; wire \stg3_tap_cnt[1]_i_1_n_0 ; wire \stg3_tap_cnt[1]_i_2_n_0 ; wire \stg3_tap_cnt[2]_i_1_n_0 ; wire \stg3_tap_cnt[2]_i_2_n_0 ; wire \stg3_tap_cnt[3]_i_1_n_0 ; wire \stg3_tap_cnt[3]_i_2_n_0 ; wire \stg3_tap_cnt[3]_i_3_n_0 ; wire \stg3_tap_cnt[3]_i_4_n_0 ; wire \stg3_tap_cnt[4]_i_1_n_0 ; wire \stg3_tap_cnt[5]_i_2_n_0 ; wire \stg3_tap_cnt[5]_i_4_n_0 ; wire \stg3_tap_cnt[5]_i_5_n_0 ; wire \stg3_tap_cnt[5]_i_6_n_0 ; wire [2:0]\stg3_tap_cnt_reg[2]_0 ; wire \stg3_tap_cnt_reg_n_0_[0] ; wire \stg3_tap_cnt_reg_n_0_[1] ; wire \stg3_tap_cnt_reg_n_0_[2] ; wire \stg3_tap_cnt_reg_n_0_[3] ; wire \stg3_tap_cnt_reg_n_0_[4] ; wire \stg3_tap_cnt_reg_n_0_[5] ; wire wait_cnt_done; wire wait_cnt_done_i_1_n_0; wire wait_cnt_en_r; wire wait_cnt_en_r0; wire wait_cnt_en_r_i_2_n_0; wire wait_cnt_en_r_i_3_n_0; wire \wait_cnt_r[3]_i_1_n_0 ; wire [3:0]wait_cnt_r_reg__0; wire [1:0]\wl_po_fine_cnt_reg[14] ; wire \wl_po_fine_cnt_reg[17] ; wire \wl_po_fine_cnt_reg[18] ; wire \wl_po_fine_cnt_reg[3] ; wire write_request_r_i_1_n_0; wire write_request_r_i_2_n_0; wire [0:0]NLW_mod_sub0_return0__14_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED; wire [3:2]NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_mod_sub0_return0_carry__0_O_UNCONNECTED; wire [0:0]NLW_mod_sub_return0__14_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED; wire [3:2]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_mod_sub_return0_carry__0_O_UNCONNECTED; FDRE #( .INIT(1'b0)) detect_done_r_reg (.C(CLK), .CE(1'b1), .D(done_r_reg_1), .Q(detect_done_r), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hFFFF7FFF00880000)) done_r_i_1__0 (.I0(\lim_state[0]_i_2_n_0 ), .I1(\lim_state[4]_i_3_n_0 ), .I2(lim_start_r_reg_0), .I3(lim_state[0]), .I4(lim_state[13]), .I5(done_r_reg_0), .O(done_r_i_1__0_n_0)); FDRE #( .INIT(1'b0)) done_r_reg (.C(CLK), .CE(1'b1), .D(done_r_i_1__0_n_0), .Q(done_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__9)); (* SOFT_HLUTNM = "soft_lutpair388" *) LUT3 #( .INIT(8'h02)) \init_state_r[4]_i_35 (.I0(cnt_cmd_done_r), .I1(prech_req_r_reg_0), .I2(ocd_prech_req_r_reg), .O(\init_state_r_reg[4] )); LUT2 #( .INIT(4'hE)) \init_state_r[5]_i_37 (.I0(lim2init_write_request), .I1(oclk_center_write_resume), .O(\init_state_r_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair388" *) LUT3 #( .INIT(8'hFE)) \init_state_r[6]_i_7 (.I0(prbs_rdlvl_done_reg_rep), .I1(prech_req_r_reg_0), .I2(ocd_prech_req_r_reg), .O(\init_state_r_reg[6] )); LUT6 #( .INIT(64'hFFEFFFFF01000000)) ktap_right_r_i_1 (.I0(\lim_state[13]_i_7_n_0 ), .I1(lim_state[0]), .I2(lim_state[13]), .I3(lim_state[1]), .I4(ktap_right_r_i_2_n_0), .I5(lim2poc_ktap_right), .O(ktap_right_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair380" *) LUT4 #( .INIT(16'h0001)) ktap_right_r_i_2 (.I0(lim_state[9]), .I1(lim_state[12]), .I2(lim_state[10]), .I3(lim_state[11]), .O(ktap_right_r_i_2_n_0)); FDRE #( .INIT(1'b0)) ktap_right_r_reg (.C(CLK), .CE(1'b1), .D(ktap_right_r_i_1_n_0), .Q(lim2poc_ktap_right), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) lim_start_r_reg (.C(CLK), .CE(1'b1), .D(lim_start), .Q(lim_start_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT4 #( .INIT(16'hFFD0)) \lim_state[0]_i_1 (.I0(\lim_state[0]_i_2_n_0 ), .I1(\lim_state[0]_i_3_n_0 ), .I2(wait_cnt_en_r_i_2_n_0), .I3(\lim_state[0]_i_4_n_0 ), .O(\lim_state[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair375" *) LUT4 #( .INIT(16'h0001)) \lim_state[0]_i_2 (.I0(lim_state[1]), .I1(lim_state[4]), .I2(lim_state[2]), .I3(lim_state[3]), .O(\lim_state[0]_i_2_n_0 )); LUT6 #( .INIT(64'hAAA8A880AAAAAAAA)) \lim_state[0]_i_3 (.I0(\lim_state[0]_i_5_n_0 ), .I1(lim_state[8]), .I2(lim_state[7]), .I3(lim_state[6]), .I4(lim_state[5]), .I5(\lim_state[1]_i_2_n_0 ), .O(\lim_state[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFDFFFCFCC2)) \lim_state[0]_i_4 (.I0(\lim_state[4]_i_3_n_0 ), .I1(lim_state[3]), .I2(lim_state[2]), .I3(lim_state[4]), .I4(lim_state[1]), .I5(lim_state[0]), .O(\lim_state[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFEFEEC)) \lim_state[0]_i_5 (.I0(lim_state[9]), .I1(lim_state[13]), .I2(lim_state[12]), .I3(lim_state[10]), .I4(lim_state[11]), .I5(wait_cnt_en_r_i_3_n_0), .O(\lim_state[0]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000020200)) \lim_state[10]_i_1 (.I0(\lim_state[10]_i_2_n_0 ), .I1(lim_state[0]), .I2(lim_state[9]), .I3(lim_state[7]), .I4(lim_state[8]), .I5(\lim_state[10]_i_3_n_0 ), .O(\lim_state[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair366" *) LUT5 #( .INIT(32'h00010000)) \lim_state[10]_i_2 (.I0(lim_state[12]), .I1(lim_state[13]), .I2(lim_state[11]), .I3(lim_state[10]), .I4(\lim_state[0]_i_2_n_0 ), .O(\lim_state[10]_i_2_n_0 )); LUT2 #( .INIT(4'hE)) \lim_state[10]_i_3 (.I0(lim_state[6]), .I1(lim_state[5]), .O(\lim_state[10]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000E2000000)) \lim_state[11]_i_1 (.I0(\lim_state[11]_i_2_n_0 ), .I1(lim_state[1]), .I2(\lim_state[11]_i_3_n_0 ), .I3(\lim_state[11]_i_4_n_0 ), .I4(\lim_state[11]_i_5_n_0 ), .I5(lim_state[13]), .O(\lim_state[11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000FFFFA8A00000)) \lim_state[11]_i_2 (.I0(\lim_state[6]_i_4_n_0 ), .I1(stg3_inc2init_val_r), .I2(stg3_dec2init_val_r), .I3(\lim_state[11]_i_6_n_0 ), .I4(lim_state[9]), .I5(lim_state[10]), .O(\lim_state[11]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair380" *) LUT2 #( .INIT(4'h1)) \lim_state[11]_i_3 (.I0(lim_state[10]), .I1(lim_state[9]), .O(\lim_state[11]_i_3_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[11]_i_4 (.I0(lim_state[0]), .I1(lim_state[3]), .I2(lim_state[2]), .I3(lim_state[4]), .I4(wait_cnt_en_r_i_3_n_0), .O(\lim_state[11]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair377" *) LUT2 #( .INIT(4'h1)) \lim_state[11]_i_5 (.I0(lim_state[11]), .I1(lim_state[12]), .O(\lim_state[11]_i_5_n_0 )); LUT6 #( .INIT(64'h444F444F444F4444)) \lim_state[11]_i_6 (.I0(stg3_inc_val[5]), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(\mmcm_init_lead[5]_i_3_n_0 ), .I3(\lim_state[11]_i_7_n_0 ), .I4(\mmcm_init_lead[5]_i_6_n_0 ), .I5(\mmcm_init_lead[5]_i_4_n_0 ), .O(\lim_state[11]_i_6_n_0 )); LUT6 #( .INIT(64'h00B0BBBB000000B0)) \lim_state[11]_i_7 (.I0(stg3_inc_val[4]), .I1(\stg3_tap_cnt_reg_n_0_[4] ), .I2(stg3_inc_val[2]), .I3(\stg3_tap_cnt_reg_n_0_[2] ), .I4(\stg3_tap_cnt_reg_n_0_[3] ), .I5(stg3_inc_val[3]), .O(\lim_state[11]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair365" *) LUT5 #( .INIT(32'h00005D55)) \lim_state[12]_i_1 (.I0(\lim_state[12]_i_2_n_0 ), .I1(\lim_state[12]_i_3_n_0 ), .I2(stg3_dec2init_val_r), .I3(stg3_inc2init_val_r), .I4(\lim_state[12]_i_4_n_0 ), .O(\lim_state[12]_i_1_n_0 )); LUT6 #( .INIT(64'h555F5DDF5DDF5DDF)) \lim_state[12]_i_2 (.I0(stg3_dec2init_val_r), .I1(\lim_state[12]_i_5_n_0 ), .I2(stg2_tap_cnt_reg__0[5]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg2_tap_cnt_reg__0[4]), .I5(\byte_r_reg[0] ), .O(\lim_state[12]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \lim_state[12]_i_3 (.I0(\stg2_tap_cnt_reg[3]_0 [1]), .I1(\stg2_tap_cnt_reg[3]_0 [0]), .I2(\stg2_tap_cnt_reg[3]_0 [2]), .I3(stg2_tap_cnt_reg__0[3]), .I4(stg2_tap_cnt_reg__0[5]), .I5(stg2_tap_cnt_reg__0[4]), .O(\lim_state[12]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) \lim_state[12]_i_4 (.I0(lim_state[11]), .I1(wait_cnt_en_r_i_3_n_0), .I2(lim_state[0]), .I3(lim_state[3]), .I4(\lim_state[13]_i_11_n_0 ), .I5(stg2_inc_r_i_2_n_0), .O(\lim_state[12]_i_4_n_0 )); LUT6 #( .INIT(64'h111111FF11F1F1FF)) \lim_state[12]_i_5 (.I0(stg2_tap_cnt_reg__0[4]), .I1(\byte_r_reg[0] ), .I2(\stg2_tap_cnt_reg[2]_0 ), .I3(\wl_po_fine_cnt_reg[3] ), .I4(stg2_tap_cnt_reg__0[3]), .I5(\lim_state[12]_i_7_n_0 ), .O(\lim_state[12]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair370" *) LUT2 #( .INIT(4'h2)) \lim_state[12]_i_7 (.I0(\stg2_tap_cnt_reg[3]_0 [2]), .I1(\wl_po_fine_cnt_reg[14] [1]), .O(\lim_state[12]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEEEEA)) \lim_state[13]_i_1 (.I0(lim_state[13]), .I1(\lim_state[13]_i_3_n_0 ), .I2(lim_state[4]), .I3(\lim_state[13]_i_4_n_0 ), .I4(\lim_state[13]_i_5_n_0 ), .I5(\lim_state[13]_i_6_n_0 ), .O(lim_nxt_state)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF4)) \lim_state[13]_i_10 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[3]), .I3(lim_state[2]), .I4(lim_state[4]), .I5(lim_state[1]), .O(\lim_state[13]_i_10_n_0 )); LUT3 #( .INIT(8'h01)) \lim_state[13]_i_11 (.I0(lim_state[2]), .I1(lim_state[4]), .I2(lim_state[1]), .O(\lim_state[13]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair376" *) LUT3 #( .INIT(8'h01)) \lim_state[13]_i_12 (.I0(lim_state[9]), .I1(lim_state[10]), .I2(lim_state[12]), .O(\lim_state[13]_i_12_n_0 )); LUT6 #( .INIT(64'h00000000EEEEEEFE)) \lim_state[13]_i_13 (.I0(lim_state[10]), .I1(lim_state[8]), .I2(po_rdy), .I3(lim2stg3_dec), .I4(lim2stg3_inc), .I5(\lim_state[13]_i_14_n_0 ), .O(\lim_state[13]_i_13_n_0 )); LUT5 #( .INIT(32'h000000FB)) \lim_state[13]_i_14 (.I0(lim2stg2_dec), .I1(po_rdy), .I2(lim2stg2_inc), .I3(lim_state[8]), .I4(lim_state[9]), .O(\lim_state[13]_i_14_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \lim_state[13]_i_2 (.I0(\lim_state[13]_i_7_n_0 ), .I1(\lim_state[13]_i_8_n_0 ), .I2(lim_state[1]), .I3(lim_state[13]), .I4(lim_state[12]), .I5(stg3_dec2init_val_r), .O(\lim_state[13]_i_2_n_0 )); LUT6 #( .INIT(64'hAAA8A888AAAAAAAA)) \lim_state[13]_i_3 (.I0(\lim_state[13]_i_9_n_0 ), .I1(wait_cnt_done), .I2(lim_state[4]), .I3(lim_state[1]), .I4(lim_state[2]), .I5(\lim_state[4]_i_3_n_0 ), .O(\lim_state[13]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair379" *) LUT4 #( .INIT(16'hFFFE)) \lim_state[13]_i_4 (.I0(lim_state[10]), .I1(lim_state[11]), .I2(lim_state[8]), .I3(lim_state[9]), .O(\lim_state[13]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEEE)) \lim_state[13]_i_5 (.I0(\lim_state[10]_i_3_n_0 ), .I1(lim_state[7]), .I2(lim_state[12]), .I3(prech_done), .I4(lim_state[2]), .I5(lim_state[1]), .O(\lim_state[13]_i_5_n_0 )); LUT6 #( .INIT(64'hC8CFCCC0FFF0FFF0)) \lim_state[13]_i_6 (.I0(done_r_reg_1), .I1(\lim_state[13]_i_10_n_0 ), .I2(lim_state[0]), .I3(lim_state[3]), .I4(\lim_state[13]_i_11_n_0 ), .I5(\lim_state[13]_i_12_n_0 ), .O(\lim_state[13]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \lim_state[13]_i_7 (.I0(lim_state[8]), .I1(lim_state[7]), .I2(\lim_state[10]_i_3_n_0 ), .I3(lim_state[4]), .I4(lim_state[2]), .I5(lim_state[3]), .O(\lim_state[13]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair379" *) LUT4 #( .INIT(16'hFFFE)) \lim_state[13]_i_8 (.I0(lim_state[10]), .I1(lim_state[11]), .I2(lim_state[0]), .I3(lim_state[9]), .O(\lim_state[13]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \lim_state[13]_i_9 (.I0(\lim_state[13]_i_13_n_0 ), .I1(lim_state[12]), .I2(lim_state[11]), .I3(\lim_state[13]_i_11_n_0 ), .I4(lim_state[7]), .I5(\lim_state[10]_i_3_n_0 ), .O(\lim_state[13]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair381" *) LUT4 #( .INIT(16'h0040)) \lim_state[1]_i_1 (.I0(\lim_state[13]_i_7_n_0 ), .I1(\lim_state[1]_i_2_n_0 ), .I2(lim_state[0]), .I3(lim_state[1]), .O(\lim_state[1]_i_1_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[1]_i_2 (.I0(lim_state[11]), .I1(lim_state[10]), .I2(lim_state[12]), .I3(lim_state[9]), .I4(lim_state[13]), .O(\lim_state[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \lim_state[2]_i_1 (.I0(\lim_state[2]_i_2_n_0 ), .I1(\lim_state[2]_i_3_n_0 ), .I2(lim_state[6]), .I3(lim_state[5]), .I4(lim_state[7]), .I5(\lim_state[2]_i_4_n_0 ), .O(\lim_state[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00F000F000F1FFFF)) \lim_state[2]_i_2 (.I0(stg3_inc2init_val_r), .I1(stg3_init_dec_r), .I2(\lim_state[6]_i_3_n_0 ), .I3(lim_state[12]), .I4(lim_state[9]), .I5(stg3_dec2init_val_r), .O(\lim_state[2]_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \lim_state[2]_i_3 (.I0(lim_state[0]), .I1(lim_state[3]), .I2(lim_state[1]), .I3(lim_state[2]), .O(\lim_state[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFEFFFEFFFEFFFFFF)) \lim_state[2]_i_4 (.I0(lim_state[10]), .I1(lim_state[8]), .I2(lim_state[11]), .I3(\lim_state[4]_i_2_n_0 ), .I4(lim_state[12]), .I5(lim_state[9]), .O(\lim_state[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000010000000)) \lim_state[3]_i_1 (.I0(lim_state[0]), .I1(lim_state[1]), .I2(\lim_state[4]_i_2_n_0 ), .I3(\lim_state[4]_i_3_n_0 ), .I4(lim_state[2]), .I5(lim_state[3]), .O(\lim_state[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000010000000)) \lim_state[4]_i_1 (.I0(lim_state[0]), .I1(lim_state[1]), .I2(\lim_state[4]_i_2_n_0 ), .I3(\lim_state[4]_i_3_n_0 ), .I4(lim_state[3]), .I5(lim_state[2]), .O(\lim_state[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair369" *) LUT2 #( .INIT(4'h1)) \lim_state[4]_i_2 (.I0(lim_state[4]), .I1(lim_state[13]), .O(\lim_state[4]_i_2_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[4]_i_3 (.I0(lim_state[11]), .I1(lim_state[10]), .I2(lim_state[12]), .I3(lim_state[9]), .I4(wait_cnt_en_r_i_3_n_0), .O(\lim_state[4]_i_3_n_0 )); LUT4 #( .INIT(16'h888A)) \lim_state[5]_i_1 (.I0(\lim_state[6]_i_2_n_0 ), .I1(\lim_state[5]_i_2_n_0 ), .I2(lim_state[9]), .I3(\lim_state[6]_i_5_n_0 ), .O(\lim_state[5]_i_1_n_0 )); LUT5 #( .INIT(32'h00000010)) \lim_state[5]_i_2 (.I0(lim_state[4]), .I1(stg3_init_dec_r), .I2(stg3_inc2init_val_r), .I3(stg3_dec2init_val_r), .I4(\lim_state[11]_i_6_n_0 ), .O(\lim_state[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0002AAAA00020002)) \lim_state[6]_i_1 (.I0(\lim_state[6]_i_2_n_0 ), .I1(\lim_state[6]_i_3_n_0 ), .I2(lim_state[4]), .I3(\lim_state[6]_i_4_n_0 ), .I4(lim_state[9]), .I5(\lim_state[6]_i_5_n_0 ), .O(\lim_state[6]_i_1_n_0 )); LUT6 #( .INIT(64'h1D1D1D1D1D1D1DFF)) \lim_state[6]_i_10 (.I0(\lim_state[6]_i_14_n_0 ), .I1(\lim_state[6]_i_15_n_0 ), .I2(\lim_state[6]_i_16_n_0 ), .I3(\stg3_tap_cnt_reg_n_0_[4] ), .I4(\stg3_tap_cnt_reg_n_0_[5] ), .I5(\lim_state[6]_i_17_n_0 ), .O(\lim_state[6]_i_10_n_0 )); LUT6 #( .INIT(64'hD0FD0000FFFFD0FD)) \lim_state[6]_i_11 (.I0(\stg3_tap_cnt_reg_n_0_[0] ), .I1(stg3_dec_val[0]), .I2(stg3_dec_val[1]), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(stg3_dec_val[2]), .I5(\stg3_tap_cnt_reg_n_0_[2] ), .O(\lim_state[6]_i_11_n_0 )); LUT6 #( .INIT(64'h0D000D00DD0D0D00)) \lim_state[6]_i_12 (.I0(\stg3_tap_cnt_reg[2]_0 [2]), .I1(\stg3_tap_cnt_reg_n_0_[2] ), .I2(\stg3_tap_cnt_reg[2]_0 [1]), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt_reg_n_0_[0] ), .I5(\stg3_tap_cnt_reg[2]_0 [0]), .O(\lim_state[6]_i_12_n_0 )); LUT4 #( .INIT(16'h4F44)) \lim_state[6]_i_13 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_init_val[4]), .I2(\stg3_tap_cnt_reg_n_0_[3] ), .I3(stg3_init_val[3]), .O(\lim_state[6]_i_13_n_0 )); LUT4 #( .INIT(16'h0002)) \lim_state[6]_i_14 (.I0(\lim_state[6]_i_18_n_0 ), .I1(mod_sub_return0_carry__0_n_6), .I2(mod_sub_return0_carry__0_n_5), .I3(mod_sub_return0_carry__0_n_7), .O(\lim_state[6]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair373" *) LUT5 #( .INIT(32'h4D44DDDD)) \lim_state[6]_i_15 (.I0(\mmcm_current_reg_n_0_[5] ), .I1(\mmcm_init_trail_reg_n_0_[5] ), .I2(\mmcm_current_reg_n_0_[4] ), .I3(\mmcm_init_trail_reg_n_0_[4] ), .I4(\lim_state[6]_i_19_n_0 ), .O(\lim_state[6]_i_15_n_0 )); LUT4 #( .INIT(16'h0020)) \lim_state[6]_i_16 (.I0(\lim_state[6]_i_20_n_0 ), .I1(mod_sub_return0__14_carry__0_n_7), .I2(mod_sub_return0__14_carry__0_n_1), .I3(mod_sub_return0__14_carry__0_n_6), .O(\lim_state[6]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair374" *) LUT4 #( .INIT(16'hFFFE)) \lim_state[6]_i_17 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .O(\lim_state[6]_i_17_n_0 )); LUT4 #( .INIT(16'h5557)) \lim_state[6]_i_18 (.I0(mod_sub_return0_carry_n_4), .I1(mod_sub_return0_carry_n_6), .I2(mod_sub_return0_carry_n_5), .I3(mod_sub_return0_carry_n_7), .O(\lim_state[6]_i_18_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFB000FFB0)) \lim_state[6]_i_19 (.I0(\mmcm_current_reg_n_0_[2] ), .I1(\mmcm_init_trail_reg_n_0_[2] ), .I2(\lim_state[6]_i_21_n_0 ), .I3(\mmcm_current_reg_n_0_[3] ), .I4(\mmcm_init_trail_reg_n_0_[3] ), .I5(\lim_state[6]_i_22_n_0 ), .O(\lim_state[6]_i_19_n_0 )); LUT5 #( .INIT(32'h11100000)) \lim_state[6]_i_2 (.I0(wait_cnt_en_r_i_3_n_0), .I1(\lim_state[2]_i_3_n_0 ), .I2(lim_state[4]), .I3(lim_state[9]), .I4(\lim_state[6]_i_6_n_0 ), .O(\lim_state[6]_i_2_n_0 )); LUT4 #( .INIT(16'h5557)) \lim_state[6]_i_20 (.I0(mod_sub_return0__14_carry_n_4), .I1(mod_sub_return0__14_carry_n_6), .I2(mod_sub_return0__14_carry_n_5), .I3(\mmcm_init_trail_reg[0]_0 ), .O(\lim_state[6]_i_20_n_0 )); LUT6 #( .INIT(64'h40F440F4FFFF40F4)) \lim_state[6]_i_21 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .I2(\mmcm_current_reg_n_0_[1] ), .I3(\mmcm_init_trail_reg_n_0_[1] ), .I4(\mmcm_current_reg_n_0_[2] ), .I5(\mmcm_init_trail_reg_n_0_[2] ), .O(\lim_state[6]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair373" *) LUT2 #( .INIT(4'h2)) \lim_state[6]_i_22 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_trail_reg_n_0_[4] ), .O(\lim_state[6]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair390" *) LUT2 #( .INIT(4'h9)) \lim_state[6]_i_24 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .O(stg3_inc2init_val_r_reg_0)); LUT4 #( .INIT(16'h8A08)) \lim_state[6]_i_3 (.I0(stg3_init_dec_r), .I1(stg3_dec_val[5]), .I2(\stg3_tap_cnt_reg_n_0_[5] ), .I3(\lim_state[6]_i_7_n_0 ), .O(\lim_state[6]_i_3_n_0 )); LUT6 #( .INIT(64'h1055105510555555)) \lim_state[6]_i_4 (.I0(stg3_init_dec_r), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(stg3_init_val[5]), .I3(stg3_dec2init_val_r), .I4(\lim_state[6]_i_8_n_0 ), .I5(\lim_state[6]_i_9_n_0 ), .O(\lim_state[6]_i_4_n_0 )); LUT3 #( .INIT(8'hAE)) \lim_state[6]_i_5 (.I0(stg3_dec2init_val_r_i_2_n_0), .I1(stg3_dec_r), .I2(\lim_state[6]_i_10_n_0 ), .O(\lim_state[6]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair366" *) LUT4 #( .INIT(16'h0001)) \lim_state[6]_i_6 (.I0(lim_state[10]), .I1(lim_state[11]), .I2(lim_state[13]), .I3(lim_state[12]), .O(\lim_state[6]_i_6_n_0 )); LUT5 #( .INIT(32'hD4DD44D4)) \lim_state[6]_i_7 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_dec_val[4]), .I2(\lim_state[6]_i_11_n_0 ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .I4(stg3_dec_val[3]), .O(\lim_state[6]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFFF4F44)) \lim_state[6]_i_8 (.I0(stg3_init_val[3]), .I1(\stg3_tap_cnt_reg_n_0_[3] ), .I2(\stg3_tap_cnt_reg[2]_0 [2]), .I3(\stg3_tap_cnt_reg_n_0_[2] ), .I4(\lim_state[6]_i_12_n_0 ), .I5(\lim_state[6]_i_13_n_0 ), .O(\lim_state[6]_i_8_n_0 )); LUT4 #( .INIT(16'h4F44)) \lim_state[6]_i_9 (.I0(stg3_init_val[4]), .I1(\stg3_tap_cnt_reg_n_0_[4] ), .I2(stg3_init_val[5]), .I3(\stg3_tap_cnt_reg_n_0_[5] ), .O(\lim_state[6]_i_9_n_0 )); LUT5 #( .INIT(32'h0000888A)) \lim_state[7]_i_1 (.I0(\lim_state[12]_i_2_n_0 ), .I1(stg3_dec2init_val_r), .I2(\lim_state[7]_i_2_n_0 ), .I3(stg3_inc2init_val_r), .I4(\lim_state[12]_i_4_n_0 ), .O(\lim_state[7]_i_1_n_0 )); LUT6 #( .INIT(64'h55555555D5555555)) \lim_state[7]_i_2 (.I0(stg2_inc_r), .I1(stg2_tap_cnt_reg__0[5]), .I2(stg2_tap_cnt_reg__0[4]), .I3(\stg2_tap_cnt_reg[3]_0 [1]), .I4(\stg2_tap_cnt_reg[3]_0 [0]), .I5(\lim_state[7]_i_3_n_0 ), .O(\lim_state[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair364" *) LUT2 #( .INIT(4'h7)) \lim_state[7]_i_3 (.I0(\stg2_tap_cnt_reg[3]_0 [2]), .I1(stg2_tap_cnt_reg__0[3]), .O(\lim_state[7]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair365" *) LUT4 #( .INIT(16'h0004)) \lim_state[8]_i_1 (.I0(\lim_state[12]_i_4_n_0 ), .I1(stg3_inc2init_val_r), .I2(stg3_dec2init_val_r), .I3(\lim_state[12]_i_3_n_0 ), .O(\lim_state[8]_i_1_n_0 )); LUT5 #( .INIT(32'h17001400)) \lim_state[9]_i_1 (.I0(lim_state[11]), .I1(lim_state[5]), .I2(lim_state[6]), .I3(\lim_state[9]_i_2_n_0 ), .I4(\lim_state[9]_i_3_n_0 ), .O(\lim_state[9]_i_1_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[9]_i_2 (.I0(stg2_inc_r_i_2_n_0), .I1(lim_state[4]), .I2(lim_state[8]), .I3(lim_state[7]), .I4(\lim_state[2]_i_3_n_0 ), .O(\lim_state[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair383" *) LUT4 #( .INIT(16'h0200)) \lim_state[9]_i_3 (.I0(\lim_state[7]_i_2_n_0 ), .I1(stg3_dec2init_val_r), .I2(stg3_inc2init_val_r), .I3(lim_state[11]), .O(\lim_state[9]_i_3_n_0 )); FDSE #( .INIT(1'b1)) \lim_state_reg[0] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[0]_i_1_n_0 ), .Q(lim_state[0]), .S(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[10] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[10]_i_1_n_0 ), .Q(lim_state[10]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[11] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[11]_i_1_n_0 ), .Q(lim_state[11]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[12] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[12]_i_1_n_0 ), .Q(lim_state[12]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[13] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[13]_i_2_n_0 ), .Q(lim_state[13]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[1] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[1]_i_1_n_0 ), .Q(lim_state[1]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[2] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[2]_i_1_n_0 ), .Q(lim_state[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[3] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[3]_i_1_n_0 ), .Q(lim_state[3]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[4] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[4]_i_1_n_0 ), .Q(lim_state[4]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[5] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[5]_i_1_n_0 ), .Q(lim_state[5]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[6] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[6]_i_1_n_0 ), .Q(lim_state[6]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[7] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[7]_i_1_n_0 ), .Q(lim_state[7]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[8] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[8]_i_1_n_0 ), .Q(lim_state[8]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \lim_state_reg[9] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[9]_i_1_n_0 ), .Q(lim_state[9]), .R(rstdiv0_sync_r1_reg_rep__10)); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[0]_i_1 (.I0(\mmcm_current[0]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[0] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[0]), .O(\mmcm_current[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair384" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[0]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [0]), .O(\mmcm_current[0]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[1]_i_1 (.I0(\mmcm_current[1]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[1] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[1]), .O(\mmcm_current[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair385" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[1]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[1] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [1]), .O(\mmcm_current[1]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[2]_i_1 (.I0(\mmcm_current[2]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[2] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[2]), .O(\mmcm_current[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair386" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[2]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[2] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [2]), .O(\mmcm_current[2]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[3]_i_1 (.I0(\mmcm_current[3]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[3] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[3]), .O(\mmcm_current[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair384" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[3]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[3] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [3]), .O(\mmcm_current[3]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[4]_i_1 (.I0(\mmcm_current[4]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[4] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[4]), .O(\mmcm_current[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair385" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[4]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [4]), .O(\mmcm_current[4]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[5]_i_1 (.I0(\mmcm_current[5]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[5] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[5]), .O(\mmcm_current[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair386" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[5]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[5] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [5]), .O(\mmcm_current[5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_current_reg[0] (.C(CLK), .CE(1'b1), .D(\mmcm_current[0]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \mmcm_current_reg[1] (.C(CLK), .CE(1'b1), .D(\mmcm_current[1]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \mmcm_current_reg[2] (.C(CLK), .CE(1'b1), .D(\mmcm_current[2]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \mmcm_current_reg[3] (.C(CLK), .CE(1'b1), .D(\mmcm_current[3]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \mmcm_current_reg[4] (.C(CLK), .CE(1'b1), .D(\mmcm_current[4]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \mmcm_current_reg[5] (.C(CLK), .CE(1'b1), .D(\mmcm_current[5]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__10)); LUT3 #( .INIT(8'h20)) \mmcm_init_lead[5]_i_1 (.I0(\mmcm_init_lead[5]_i_2_n_0 ), .I1(detect_done_r), .I2(done_r_reg_1), .O(mmcm_init_lead)); LUT4 #( .INIT(16'h0004)) \mmcm_init_lead[5]_i_2 (.I0(\mmcm_init_lead[5]_i_3_n_0 ), .I1(\mmcm_init_lead[5]_i_4_n_0 ), .I2(\mmcm_init_lead[5]_i_5_n_0 ), .I3(\mmcm_init_lead[5]_i_6_n_0 ), .O(\mmcm_init_lead[5]_i_2_n_0 )); LUT4 #( .INIT(16'h4F44)) \mmcm_init_lead[5]_i_3 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_inc_val[4]), .I2(\stg3_tap_cnt_reg_n_0_[5] ), .I3(stg3_inc_val[5]), .O(\mmcm_init_lead[5]_i_3_n_0 )); LUT4 #( .INIT(16'hD0DD)) \mmcm_init_lead[5]_i_4 (.I0(stg3_inc_val[1]), .I1(\stg3_tap_cnt_reg_n_0_[1] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(stg3_inc_val[0]), .O(\mmcm_init_lead[5]_i_4_n_0 )); LUT5 #( .INIT(32'h5D5DFF5D)) \mmcm_init_lead[5]_i_5 (.I0(\mmcm_init_lead[5]_i_7_n_0 ), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(stg3_inc_val[5]), .I3(\stg3_tap_cnt_reg_n_0_[0] ), .I4(stg3_inc_val[0]), .O(\mmcm_init_lead[5]_i_5_n_0 )); LUT5 #( .INIT(32'h22F2FFFF)) \mmcm_init_lead[5]_i_6 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(stg3_inc_val[1]), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(stg3_inc_val[2]), .I4(\mmcm_init_lead[5]_i_8_n_0 ), .O(\mmcm_init_lead[5]_i_6_n_0 )); LUT4 #( .INIT(16'hD0DD)) \mmcm_init_lead[5]_i_7 (.I0(stg3_inc_val[3]), .I1(\stg3_tap_cnt_reg_n_0_[3] ), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(stg3_inc_val[2]), .O(\mmcm_init_lead[5]_i_7_n_0 )); LUT4 #( .INIT(16'hD0DD)) \mmcm_init_lead[5]_i_8 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_inc_val[4]), .I2(stg3_inc_val[3]), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .O(\mmcm_init_lead[5]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_init_lead_reg[0] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [0]), .Q(\mmcm_init_lead_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_lead_reg[1] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [1]), .Q(\mmcm_init_lead_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_lead_reg[2] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [2]), .Q(\mmcm_init_lead_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_lead_reg[3] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [3]), .Q(\mmcm_init_lead_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_lead_reg[4] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [4]), .Q(\mmcm_init_lead_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_lead_reg[5] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [5]), .Q(\mmcm_init_lead_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); LUT3 #( .INIT(8'h40)) \mmcm_init_trail[5]_i_1 (.I0(detect_done_r), .I1(done_r_reg_1), .I2(\mmcm_init_trail[5]_i_2_n_0 ), .O(mmcm_init_trail)); LUT6 #( .INIT(64'h0000000009000009)) \mmcm_init_trail[5]_i_2 (.I0(stg3_dec_val[5]), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(\mmcm_init_trail[5]_i_3_n_0 ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .I4(stg3_dec_val[3]), .I5(\mmcm_init_trail[5]_i_4_n_0 ), .O(\mmcm_init_trail[5]_i_2_n_0 )); LUT2 #( .INIT(4'h6)) \mmcm_init_trail[5]_i_3 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_dec_val[4]), .O(\mmcm_init_trail[5]_i_3_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \mmcm_init_trail[5]_i_4 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(stg3_dec_val[1]), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(stg3_dec_val[2]), .I4(stg3_dec_val[0]), .I5(\stg3_tap_cnt_reg_n_0_[0] ), .O(\mmcm_init_trail[5]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_init_trail_reg[0] (.C(CLK), .CE(mmcm_init_trail), .D(Q[0]), .Q(\mmcm_init_trail_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_trail_reg[1] (.C(CLK), .CE(mmcm_init_trail), .D(Q[1]), .Q(\mmcm_init_trail_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_trail_reg[2] (.C(CLK), .CE(mmcm_init_trail), .D(Q[2]), .Q(\mmcm_init_trail_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_trail_reg[3] (.C(CLK), .CE(mmcm_init_trail), .D(Q[3]), .Q(\mmcm_init_trail_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_trail_reg[4] (.C(CLK), .CE(mmcm_init_trail), .D(Q[4]), .Q(\mmcm_init_trail_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE #( .INIT(1'b0)) \mmcm_init_trail_reg[5] (.C(CLK), .CE(mmcm_init_trail), .D(Q[5]), .Q(\mmcm_init_trail_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); CARRY4 mod_sub0_return0__14_carry (.CI(1'b0), .CO({mod_sub0_return0__14_carry_n_0,mod_sub0_return0__14_carry_n_1,mod_sub0_return0__14_carry_n_2,mod_sub0_return0__14_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_current_reg_n_0_[3] ,\mmcm_current_reg_n_0_[2] ,\mmcm_current_reg_n_0_[1] ,\mmcm_current_reg_n_0_[0] }), .O({mod_sub0_return0__14_carry_n_4,mod_sub0_return0__14_carry_n_5,mod_sub0_return0__14_carry_n_6,NLW_mod_sub0_return0__14_carry_O_UNCONNECTED[0]}), .S({mod_sub0_return0__14_carry_i_1_n_0,mod_sub0_return0__14_carry_i_2_n_0,mod_sub0_return0__14_carry_i_3_n_0,mod_sub0_return0__14_carry_i_4_n_0})); CARRY4 mod_sub0_return0__14_carry__0 (.CI(mod_sub0_return0__14_carry_n_0), .CO({NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub0_return0__14_carry__0_n_1,NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub0_return0__14_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\mmcm_current_reg_n_0_[5] ,\mmcm_current_reg_n_0_[4] }), .O({NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub0_return0__14_carry__0_n_6,mod_sub0_return0__14_carry__0_n_7}), .S({1'b0,1'b1,mod_sub0_return0__14_carry__0_i_1_n_0,mod_sub0_return0__14_carry__0_i_2_n_0})); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry__0_i_1 (.I0(\mmcm_current_reg_n_0_[5] ), .I1(\mmcm_init_lead_reg_n_0_[5] ), .O(mod_sub0_return0__14_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry__0_i_2 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_lead_reg_n_0_[4] ), .O(mod_sub0_return0__14_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_1 (.I0(\mmcm_current_reg_n_0_[3] ), .I1(\mmcm_init_lead_reg_n_0_[3] ), .O(mod_sub0_return0__14_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_2 (.I0(\mmcm_current_reg_n_0_[2] ), .I1(\mmcm_init_lead_reg_n_0_[2] ), .O(mod_sub0_return0__14_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_3 (.I0(\mmcm_current_reg_n_0_[1] ), .I1(\mmcm_init_lead_reg_n_0_[1] ), .O(mod_sub0_return0__14_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_4 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .O(mod_sub0_return0__14_carry_i_4_n_0)); CARRY4 mod_sub0_return0_carry (.CI(1'b0), .CO({mod_sub0_return0_carry_n_0,mod_sub0_return0_carry_n_1,mod_sub0_return0_carry_n_2,mod_sub0_return0_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_init_lead_reg_n_0_[3] ,\mmcm_current_reg_n_0_[2] ,\mmcm_current_reg_n_0_[1] ,\mmcm_current_reg_n_0_[0] }), .O({mod_sub0_return0_carry_n_4,mod_sub0_return0_carry_n_5,mod_sub0_return0_carry_n_6,mod_sub0_return0_carry_n_7}), .S({mod_sub0_return0_carry_i_1_n_0,mod_sub0_return0_carry_i_2_n_0,mod_sub0_return0_carry_i_3_n_0,mod_sub0_return0_carry_i_4_n_0})); CARRY4 mod_sub0_return0_carry__0 (.CI(mod_sub0_return0_carry_n_0), .CO({NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub0_return0_carry__0_n_2,mod_sub0_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,mod_sub0_return0_carry__0_i_1_n_0,mod_sub0_return0_carry__0_i_2_n_0}), .O({NLW_mod_sub0_return0_carry__0_O_UNCONNECTED[3],mod_sub0_return0_carry__0_n_5,mod_sub0_return0_carry__0_n_6,mod_sub0_return0_carry__0_n_7}), .S({1'b0,mod_sub0_return0_carry__0_i_3_n_0,mod_sub0_return0_carry__0_i_4_n_0,mod_sub0_return0_carry__0_i_5_n_0})); LUT2 #( .INIT(4'hB)) mod_sub0_return0_carry__0_i_1 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_lead_reg_n_0_[4] ), .O(mod_sub0_return0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h6)) mod_sub0_return0_carry__0_i_2 (.I0(\mmcm_init_lead_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(mod_sub0_return0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h2)) mod_sub0_return0_carry__0_i_3 (.I0(\mmcm_init_lead_reg_n_0_[5] ), .I1(\mmcm_current_reg_n_0_[5] ), .O(mod_sub0_return0_carry__0_i_3_n_0)); LUT4 #( .INIT(16'hB44B)) mod_sub0_return0_carry__0_i_4 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_lead_reg_n_0_[4] ), .I2(\mmcm_init_lead_reg_n_0_[5] ), .I3(\mmcm_current_reg_n_0_[5] ), .O(mod_sub0_return0_carry__0_i_4_n_0)); LUT3 #( .INIT(8'h69)) mod_sub0_return0_carry__0_i_5 (.I0(\mmcm_init_lead_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .I2(\mmcm_init_lead_reg_n_0_[3] ), .O(mod_sub0_return0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h6)) mod_sub0_return0_carry_i_1 (.I0(\mmcm_init_lead_reg_n_0_[3] ), .I1(\mmcm_current_reg_n_0_[3] ), .O(mod_sub0_return0_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0_carry_i_2 (.I0(\mmcm_current_reg_n_0_[2] ), .I1(\mmcm_init_lead_reg_n_0_[2] ), .O(mod_sub0_return0_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0_carry_i_3 (.I0(\mmcm_current_reg_n_0_[1] ), .I1(\mmcm_init_lead_reg_n_0_[1] ), .O(mod_sub0_return0_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0_carry_i_4 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .O(mod_sub0_return0_carry_i_4_n_0)); CARRY4 mod_sub_return0__14_carry (.CI(1'b0), .CO({mod_sub_return0__14_carry_n_0,mod_sub_return0__14_carry_n_1,mod_sub_return0__14_carry_n_2,mod_sub_return0__14_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_init_trail_reg_n_0_[3] ,\mmcm_init_trail_reg_n_0_[2] ,\mmcm_init_trail_reg_n_0_[1] ,\mmcm_init_trail_reg_n_0_[0] }), .O({mod_sub_return0__14_carry_n_4,mod_sub_return0__14_carry_n_5,mod_sub_return0__14_carry_n_6,NLW_mod_sub_return0__14_carry_O_UNCONNECTED[0]}), .S({mod_sub_return0__14_carry_i_1_n_0,mod_sub_return0__14_carry_i_2_n_0,mod_sub_return0__14_carry_i_3_n_0,mod_sub_return0__14_carry_i_4_n_0})); CARRY4 mod_sub_return0__14_carry__0 (.CI(mod_sub_return0__14_carry_n_0), .CO({NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub_return0__14_carry__0_n_1,NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub_return0__14_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\mmcm_init_trail_reg_n_0_[5] ,\mmcm_init_trail_reg_n_0_[4] }), .O({NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__14_carry__0_n_6,mod_sub_return0__14_carry__0_n_7}), .S({1'b0,1'b1,mod_sub_return0__14_carry__0_i_1_n_0,mod_sub_return0__14_carry__0_i_2_n_0})); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry__0_i_1 (.I0(\mmcm_init_trail_reg_n_0_[5] ), .I1(\mmcm_current_reg_n_0_[5] ), .O(mod_sub_return0__14_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry__0_i_2 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(mod_sub_return0__14_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_1 (.I0(\mmcm_init_trail_reg_n_0_[3] ), .I1(\mmcm_current_reg_n_0_[3] ), .O(mod_sub_return0__14_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_2 (.I0(\mmcm_init_trail_reg_n_0_[2] ), .I1(\mmcm_current_reg_n_0_[2] ), .O(mod_sub_return0__14_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_3 (.I0(\mmcm_init_trail_reg_n_0_[1] ), .I1(\mmcm_current_reg_n_0_[1] ), .O(mod_sub_return0__14_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_4 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .O(mod_sub_return0__14_carry_i_4_n_0)); CARRY4 mod_sub_return0_carry (.CI(1'b0), .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_current_reg_n_0_[3] ,\mmcm_init_trail_reg_n_0_[2] ,\mmcm_init_trail_reg_n_0_[1] ,\mmcm_init_trail_reg_n_0_[0] }), .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}), .S({mod_sub_return0_carry_i_1__0_n_0,mod_sub_return0_carry_i_2_n_0,mod_sub_return0_carry_i_3_n_0,mod_sub_return0_carry_i_4_n_0})); CARRY4 mod_sub_return0_carry__0 (.CI(mod_sub_return0_carry_n_0), .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_2,mod_sub_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,mod_sub_return0_carry__0_i_1__0_n_0,mod_sub_return0_carry__0_i_2_n_0}), .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3],mod_sub_return0_carry__0_n_5,mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}), .S({1'b0,mod_sub_return0_carry__0_i_3_n_0,mod_sub_return0_carry__0_i_4_n_0,mod_sub_return0_carry__0_i_5_n_0})); LUT2 #( .INIT(4'hB)) mod_sub_return0_carry__0_i_1__0 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(mod_sub_return0_carry__0_i_1__0_n_0)); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry__0_i_2 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_trail_reg_n_0_[4] ), .O(mod_sub_return0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h2)) mod_sub_return0_carry__0_i_3 (.I0(\mmcm_current_reg_n_0_[5] ), .I1(\mmcm_init_trail_reg_n_0_[5] ), .O(mod_sub_return0_carry__0_i_3_n_0)); LUT4 #( .INIT(16'hB44B)) mod_sub_return0_carry__0_i_4 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .I2(\mmcm_current_reg_n_0_[5] ), .I3(\mmcm_init_trail_reg_n_0_[5] ), .O(mod_sub_return0_carry__0_i_4_n_0)); LUT3 #( .INIT(8'h69)) mod_sub_return0_carry__0_i_5 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_trail_reg_n_0_[4] ), .I2(\mmcm_current_reg_n_0_[3] ), .O(mod_sub_return0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry_i_1__0 (.I0(\mmcm_current_reg_n_0_[3] ), .I1(\mmcm_init_trail_reg_n_0_[3] ), .O(mod_sub_return0_carry_i_1__0_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0_carry_i_2 (.I0(\mmcm_init_trail_reg_n_0_[2] ), .I1(\mmcm_current_reg_n_0_[2] ), .O(mod_sub_return0_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0_carry_i_3 (.I0(\mmcm_init_trail_reg_n_0_[1] ), .I1(\mmcm_current_reg_n_0_[1] ), .O(mod_sub_return0_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0_carry_i_4 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .O(mod_sub_return0_carry_i_4_n_0)); LUT4 #( .INIT(16'h8A88)) oclkdelay_center_calib_start_r_i_2 (.I0(scanning_right), .I1(o2f_r_reg), .I2(oclkdelay_center_calib_start_r_i_3_n_0), .I3(oclkdelay_center_calib_start_r_i_4_n_0), .O(oclkdelay_center_calib_start_r_reg)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) oclkdelay_center_calib_start_r_i_3 (.I0(oclkdelay_center_calib_start_r_reg_0[2]), .I1(\stg3_r_reg[5] [2]), .I2(oclkdelay_center_calib_start_r_reg_0[1]), .I3(\stg3_r_reg[5] [1]), .I4(\stg3_r_reg[5] [0]), .I5(oclkdelay_center_calib_start_r_reg_0[0]), .O(oclkdelay_center_calib_start_r_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) oclkdelay_center_calib_start_r_i_4 (.I0(oclkdelay_center_calib_start_r_reg_0[5]), .I1(\stg3_r_reg[5] [5]), .I2(oclkdelay_center_calib_start_r_reg_0[4]), .I3(\stg3_r_reg[5] [4]), .I4(oclkdelay_center_calib_start_r_reg_0[3]), .I5(\stg3_r_reg[5] [3]), .O(oclkdelay_center_calib_start_r_i_4_n_0)); LUT5 #( .INIT(32'h55555554)) po_stg23_sel_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\po_wait_r_reg[0] ), .I2(\sm_r_reg[2] ), .I3(lim2stg3_dec), .I4(lim2stg3_inc), .O(po_stg23_sel_r_reg)); LUT6 #( .INIT(64'hBFFFBFFF20200000)) poc_ready_r_i_1 (.I0(lim_state[2]), .I1(lim_state[3]), .I2(write_request_r_i_2_n_0), .I3(done_r_reg_1), .I4(wait_cnt_done), .I5(lim2poc_rdy), .O(poc_ready_r_i_1_n_0)); FDRE #( .INIT(1'b0)) poc_ready_r_reg (.C(CLK), .CE(1'b1), .D(poc_ready_r_i_1_n_0), .Q(lim2poc_rdy), .R(rstdiv0_sync_r1_reg_rep__9)); LUT5 #( .INIT(32'hFFF70004)) prech_req_r_i_1__0 (.I0(prech_done), .I1(prech_req_r_i_2_n_0), .I2(\lim_state[13]_i_4_n_0 ), .I3(\lim_state[2]_i_3_n_0 ), .I4(prech_req_r_reg_0), .O(prech_req_r_i_1__0_n_0)); LUT6 #( .INIT(64'h0000000000010000)) prech_req_r_i_2 (.I0(lim_state[6]), .I1(lim_state[5]), .I2(lim_state[7]), .I3(lim_state[4]), .I4(lim_state[12]), .I5(lim_state[13]), .O(prech_req_r_i_2_n_0)); FDRE #( .INIT(1'b0)) prech_req_r_reg (.C(CLK), .CE(1'b1), .D(prech_req_r_i_1__0_n_0), .Q(prech_req_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__10)); LUT4 #( .INIT(16'h000E)) scanning_right_r_i_2 (.I0(scanning_right_r_i_4_n_0), .I1(scanning_right_r_i_5_n_0), .I2(scan_right), .I3(scanning_right), .O(scanning_right_r_reg)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) scanning_right_r_i_4 (.I0(scanning_right_r_reg_0[0]), .I1(\stg3_r_reg[5] [0]), .I2(\stg3_r_reg[5] [1]), .I3(scanning_right_r_reg_0[1]), .I4(\stg3_r_reg[5] [2]), .I5(scanning_right_r_reg_0[2]), .O(scanning_right_r_i_4_n_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) scanning_right_r_i_5 (.I0(scanning_right_r_reg_0[3]), .I1(\stg3_r_reg[5] [3]), .I2(\stg3_r_reg[5] [4]), .I3(scanning_right_r_reg_0[4]), .I4(\stg3_r_reg[5] [5]), .I5(scanning_right_r_reg_0[5]), .O(scanning_right_r_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFFDF00000008)) stg2_dec_req_r_i_1 (.I0(stg2_inc_req_r_i_2_n_0), .I1(lim_state[8]), .I2(lim_state[10]), .I3(lim_state[0]), .I4(lim_state[7]), .I5(lim2stg2_dec), .O(stg2_dec_req_r_i_1_n_0)); FDRE #( .INIT(1'b0)) stg2_dec_req_r_reg (.C(CLK), .CE(1'b1), .D(stg2_dec_req_r_i_1_n_0), .Q(lim2stg2_dec), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hFFFFFFFD00003020)) stg2_inc_r_i_1 (.I0(\lim_state[9]_i_3_n_0 ), .I1(stg2_inc_r_i_2_n_0), .I2(stg2_inc_r_i_3_n_0), .I3(lim_state[0]), .I4(stg2_inc_r_i_4_n_0), .I5(stg2_inc_r), .O(stg2_inc_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair376" *) LUT4 #( .INIT(16'hFFFE)) stg2_inc_r_i_2 (.I0(lim_state[13]), .I1(lim_state[12]), .I2(lim_state[9]), .I3(lim_state[10]), .O(stg2_inc_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair389" *) LUT3 #( .INIT(8'h04)) stg2_inc_r_i_3 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[11]), .O(stg2_inc_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair375" *) LUT5 #( .INIT(32'hFFFFFFFE)) stg2_inc_r_i_4 (.I0(lim_state[1]), .I1(lim_state[3]), .I2(lim_state[2]), .I3(lim_state[4]), .I4(wait_cnt_en_r_i_3_n_0), .O(stg2_inc_r_i_4_n_0)); FDRE #( .INIT(1'b0)) stg2_inc_r_reg (.C(CLK), .CE(1'b1), .D(stg2_inc_r_i_1_n_0), .Q(stg2_inc_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFFF700000020)) stg2_inc_req_r_i_1 (.I0(stg2_inc_req_r_i_2_n_0), .I1(lim_state[10]), .I2(lim_state[7]), .I3(lim_state[8]), .I4(lim_state[0]), .I5(lim2stg2_inc), .O(stg2_inc_req_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000002)) stg2_inc_req_r_i_2 (.I0(\lim_state[0]_i_2_n_0 ), .I1(lim_state[12]), .I2(lim_state[11]), .I3(lim_state[13]), .I4(lim_state[9]), .I5(\lim_state[10]_i_3_n_0 ), .O(stg2_inc_req_r_i_2_n_0)); FDRE #( .INIT(1'b0)) stg2_inc_req_r_reg (.C(CLK), .CE(1'b1), .D(stg2_inc_req_r_i_1_n_0), .Q(lim2stg2_inc), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair387" *) LUT3 #( .INIT(8'h47)) \stg2_tap_cnt[0]_i_1 (.I0(\wl_po_fine_cnt_reg[18] ), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt_reg[3]_0 [0]), .O(p_0_in__0[0])); LUT5 #( .INIT(32'h8BB8B88B)) \stg2_tap_cnt[1]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt[1]_i_3_n_0 ), .I3(\stg2_tap_cnt_reg[3]_0 [1]), .I4(\stg2_tap_cnt_reg[3]_0 [0]), .O(p_0_in__0[1])); LUT6 #( .INIT(64'h0000000000000100)) \stg2_tap_cnt[1]_i_3 (.I0(\stg2_tap_cnt[1]_i_4_n_0 ), .I1(lim_state[12]), .I2(\lim_state[2]_i_3_n_0 ), .I3(lim_state[7]), .I4(lim_state[6]), .I5(lim_state[5]), .O(\stg2_tap_cnt[1]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \stg2_tap_cnt[1]_i_4 (.I0(lim_state[9]), .I1(lim_state[8]), .I2(lim_state[11]), .I3(lim_state[10]), .I4(lim_state[13]), .I5(lim_state[4]), .O(\stg2_tap_cnt[1]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair370" *) LUT5 #( .INIT(32'h8B8B8BB8)) \stg2_tap_cnt[2]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [1]), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt_reg[3]_0 [2]), .I3(\stg2_tap_cnt[2]_i_3_n_0 ), .I4(\stg2_tap_cnt[2]_i_4_n_0 ), .O(p_0_in__0[2])); LUT6 #( .INIT(64'h0001000000000000)) \stg2_tap_cnt[2]_i_3 (.I0(\stg2_tap_cnt[2]_i_5_n_0 ), .I1(\lim_state[13]_i_4_n_0 ), .I2(lim_state[12]), .I3(\lim_state[2]_i_3_n_0 ), .I4(\stg2_tap_cnt_reg[3]_0 [1]), .I5(\stg2_tap_cnt_reg[3]_0 [0]), .O(\stg2_tap_cnt[2]_i_3_n_0 )); LUT6 #( .INIT(64'h1111111111101111)) \stg2_tap_cnt[2]_i_4 (.I0(\stg2_tap_cnt_reg[3]_0 [1]), .I1(\stg2_tap_cnt_reg[3]_0 [0]), .I2(lim_state[5]), .I3(lim_state[6]), .I4(lim_state[7]), .I5(\stg2_tap_cnt[2]_i_6_n_0 ), .O(\stg2_tap_cnt[2]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \stg2_tap_cnt[2]_i_5 (.I0(lim_state[6]), .I1(lim_state[5]), .I2(lim_state[4]), .I3(lim_state[7]), .I4(lim_state[13]), .O(\stg2_tap_cnt[2]_i_5_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \stg2_tap_cnt[2]_i_6 (.I0(\lim_state[2]_i_3_n_0 ), .I1(lim_state[12]), .I2(lim_state[4]), .I3(lim_state[13]), .I4(\lim_state[13]_i_4_n_0 ), .O(\stg2_tap_cnt[2]_i_6_n_0 )); LUT5 #( .INIT(32'h74474774)) \stg2_tap_cnt[3]_i_1 (.I0(\wl_po_fine_cnt_reg[3] ), .I1(\stg2_tap_cnt[3]_i_3_n_0 ), .I2(\stg2_tap_cnt[4]_i_3_n_0 ), .I3(stg2_tap_cnt_reg__0[3]), .I4(\stg2_tap_cnt_reg[3]_0 [2]), .O(p_0_in__0[3])); LUT6 #( .INIT(64'h0000000000000110)) \stg2_tap_cnt[3]_i_3 (.I0(wait_cnt_en_r_i_2_n_0), .I1(lim_state[3]), .I2(lim_state[1]), .I3(lim_state[0]), .I4(lim_state[4]), .I5(lim_state[2]), .O(\stg2_tap_cnt[3]_i_3_n_0 )); LUT6 #( .INIT(64'h7447747474744774)) \stg2_tap_cnt[4]_i_1 (.I0(\byte_r_reg[0] ), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(stg2_tap_cnt_reg__0[4]), .I3(\stg2_tap_cnt[4]_i_3_n_0 ), .I4(stg2_tap_cnt_reg__0[3]), .I5(\stg2_tap_cnt_reg[3]_0 [2]), .O(p_0_in__0[4])); LUT5 #( .INIT(32'h01FF0101)) \stg2_tap_cnt[4]_i_3 (.I0(\stg2_tap_cnt[1]_i_3_n_0 ), .I1(\stg2_tap_cnt_reg[3]_0 [0]), .I2(\stg2_tap_cnt_reg[3]_0 [1]), .I3(\stg2_tap_cnt[2]_i_3_n_0 ), .I4(\stg2_tap_cnt_reg[3]_0 [2]), .O(\stg2_tap_cnt[4]_i_3_n_0 )); LUT2 #( .INIT(4'hE)) \stg2_tap_cnt[5]_i_2 (.I0(\stg2_tap_cnt_reg[0]_0 ), .I1(\lim_state[10]_i_1_n_0 ), .O(stg2_tap_cnt0)); (* SOFT_HLUTNM = "soft_lutpair387" *) LUT3 #( .INIT(8'h74)) \stg2_tap_cnt[5]_i_3 (.I0(\wl_po_fine_cnt_reg[17] ), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt[5]_i_6_n_0 ), .O(p_0_in__0[5])); LUT4 #( .INIT(16'h0440)) \stg2_tap_cnt[5]_i_4 (.I0(\lim_state[13]_i_7_n_0 ), .I1(\lim_state[1]_i_2_n_0 ), .I2(lim_state[0]), .I3(lim_state[1]), .O(\stg2_tap_cnt_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair364" *) LUT5 #( .INIT(32'hAAA96AAA)) \stg2_tap_cnt[5]_i_6 (.I0(stg2_tap_cnt_reg__0[5]), .I1(stg2_tap_cnt_reg__0[4]), .I2(\stg2_tap_cnt_reg[3]_0 [2]), .I3(stg2_tap_cnt_reg__0[3]), .I4(\stg2_tap_cnt[4]_i_3_n_0 ), .O(\stg2_tap_cnt[5]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \stg2_tap_cnt_reg[0] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[0]), .Q(\stg2_tap_cnt_reg[3]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \stg2_tap_cnt_reg[1] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[1]), .Q(\stg2_tap_cnt_reg[3]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \stg2_tap_cnt_reg[2] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[2]), .Q(\stg2_tap_cnt_reg[3]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \stg2_tap_cnt_reg[3] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[3]), .Q(stg2_tap_cnt_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \stg2_tap_cnt_reg[4] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[4]), .Q(stg2_tap_cnt_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \stg2_tap_cnt_reg[5] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[5]), .Q(stg2_tap_cnt_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) stg3_dec2init_val_r1_reg (.C(CLK), .CE(1'b1), .D(stg3_dec2init_val_r), .Q(stg3_dec2init_val_r1), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFAFAA00000D00)) stg3_dec2init_val_r_i_1 (.I0(lim_state[4]), .I1(stg3_dec2init_val_r_i_2_n_0), .I2(lim_state[13]), .I3(wait_cnt_done), .I4(stg3_dec2init_val_r_i_3_n_0), .I5(stg3_dec2init_val_r), .O(stg3_dec2init_val_r_i_1_n_0)); LUT4 #( .INIT(16'h5557)) stg3_dec2init_val_r_i_10 (.I0(mod_sub0_return0_carry_n_4), .I1(mod_sub0_return0_carry_n_6), .I2(mod_sub0_return0_carry_n_5), .I3(mod_sub0_return0_carry_n_7), .O(stg3_dec2init_val_r_i_10_n_0)); LUT6 #( .INIT(64'h40F440F4FFFF40F4)) stg3_dec2init_val_r_i_12 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .I2(\mmcm_init_lead_reg_n_0_[1] ), .I3(\mmcm_current_reg_n_0_[1] ), .I4(\mmcm_init_lead_reg_n_0_[2] ), .I5(\mmcm_current_reg_n_0_[2] ), .O(stg3_dec2init_val_r_i_12_n_0)); (* SOFT_HLUTNM = "soft_lutpair372" *) LUT2 #( .INIT(4'h2)) stg3_dec2init_val_r_i_13 (.I0(\mmcm_init_lead_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(stg3_dec2init_val_r_i_13_n_0)); (* SOFT_HLUTNM = "soft_lutpair390" *) LUT2 #( .INIT(4'h9)) stg3_dec2init_val_r_i_14 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .O(stg3_dec2init_val_r_reg_0)); LUT6 #( .INIT(64'h4445554544555555)) stg3_dec2init_val_r_i_2 (.I0(stg3_dec_r), .I1(stg3_dec2init_val_r_i_4_n_0), .I2(stg3_dec2init_val_r_i_5_n_0), .I3(stg3_dec2init_val_r_i_6_n_0), .I4(stg3_dec2init_val_r_i_7_n_0), .I5(stg3_dec2init_val_r_i_8_n_0), .O(stg3_dec2init_val_r_i_2_n_0)); LUT4 #( .INIT(16'hDDDF)) stg3_dec2init_val_r_i_3 (.I0(\lim_state[4]_i_3_n_0 ), .I1(\lim_state[2]_i_3_n_0 ), .I2(lim_state[4]), .I3(lim_state[13]), .O(stg3_dec2init_val_r_i_3_n_0)); LUT6 #( .INIT(64'h8000000000000000)) stg3_dec2init_val_r_i_4 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt_reg_n_0_[3] ), .I5(\stg3_tap_cnt_reg_n_0_[2] ), .O(stg3_dec2init_val_r_i_4_n_0)); LUT3 #( .INIT(8'h04)) stg3_dec2init_val_r_i_5 (.I0(mod_sub0_return0__14_carry__0_n_6), .I1(mod_sub0_return0__14_carry__0_n_1), .I2(mod_sub0_return0__14_carry__0_n_7), .O(stg3_dec2init_val_r_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair372" *) LUT5 #( .INIT(32'hB2BB2222)) stg3_dec2init_val_r_i_6 (.I0(\mmcm_init_lead_reg_n_0_[5] ), .I1(\mmcm_current_reg_n_0_[5] ), .I2(\mmcm_init_lead_reg_n_0_[4] ), .I3(\mmcm_current_reg_n_0_[4] ), .I4(stg3_dec2init_val_r_i_9_n_0), .O(stg3_dec2init_val_r_i_6_n_0)); LUT4 #( .INIT(16'h0002)) stg3_dec2init_val_r_i_7 (.I0(stg3_dec2init_val_r_i_10_n_0), .I1(mod_sub0_return0_carry__0_n_7), .I2(mod_sub0_return0_carry__0_n_5), .I3(mod_sub0_return0_carry__0_n_6), .O(stg3_dec2init_val_r_i_7_n_0)); LUT4 #( .INIT(16'h5557)) stg3_dec2init_val_r_i_8 (.I0(mod_sub0_return0__14_carry_n_4), .I1(mod_sub0_return0__14_carry_n_6), .I2(mod_sub0_return0__14_carry_n_5), .I3(\mmcm_current_reg[0]_0 ), .O(stg3_dec2init_val_r_i_8_n_0)); LUT6 #( .INIT(64'hFFFFFFFFB000FFB0)) stg3_dec2init_val_r_i_9 (.I0(\mmcm_init_lead_reg_n_0_[2] ), .I1(\mmcm_current_reg_n_0_[2] ), .I2(stg3_dec2init_val_r_i_12_n_0), .I3(\mmcm_init_lead_reg_n_0_[3] ), .I4(\mmcm_current_reg_n_0_[3] ), .I5(stg3_dec2init_val_r_i_13_n_0), .O(stg3_dec2init_val_r_i_9_n_0)); FDRE #( .INIT(1'b0)) stg3_dec2init_val_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec2init_val_r_i_1_n_0), .Q(stg3_dec2init_val_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFDFFFF30200000)) stg3_dec_r_i_1 (.I0(stg3_dec_r_i_2_n_0), .I1(stg3_dec_r_i_3_n_0), .I2(stg3_dec_r_i_4_n_0), .I3(lim_state[0]), .I4(stg3_dec_r_i_5_n_0), .I5(stg3_dec_r), .O(stg3_dec_r_i_1_n_0)); LUT4 #( .INIT(16'h8000)) stg3_dec_r_i_2 (.I0(\lim_state[6]_i_10_n_0 ), .I1(lim_state[4]), .I2(wait_cnt_done), .I3(stg3_dec_r), .O(stg3_dec_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair381" *) LUT2 #( .INIT(4'hE)) stg3_dec_r_i_3 (.I0(lim_state[2]), .I1(lim_state[1]), .O(stg3_dec_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair389" *) LUT3 #( .INIT(8'h04)) stg3_dec_r_i_4 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[4]), .O(stg3_dec_r_i_4_n_0)); LUT6 #( .INIT(64'h0000000000000004)) stg3_dec_r_i_5 (.I0(lim_state[3]), .I1(\lim_state[1]_i_2_n_0 ), .I2(lim_state[5]), .I3(lim_state[6]), .I4(lim_state[7]), .I5(lim_state[8]), .O(stg3_dec_r_i_5_n_0)); FDRE #( .INIT(1'b0)) stg3_dec_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec_r_i_1_n_0), .Q(stg3_dec_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFDFF00000020)) stg3_dec_req_r_i_1 (.I0(stg3_dec_req_r_i_2_n_0), .I1(lim_state[7]), .I2(lim_state[6]), .I3(lim_state[9]), .I4(lim_state[5]), .I5(lim2stg3_dec), .O(stg3_dec_req_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000002)) stg3_dec_req_r_i_2 (.I0(\lim_state[0]_i_2_n_0 ), .I1(stg3_dec_req_r_i_3_n_0), .I2(lim_state[13]), .I3(lim_state[12]), .I4(lim_state[0]), .I5(lim_state[8]), .O(stg3_dec_req_r_i_2_n_0)); LUT2 #( .INIT(4'hE)) stg3_dec_req_r_i_3 (.I0(lim_state[11]), .I1(lim_state[10]), .O(stg3_dec_req_r_i_3_n_0)); FDRE #( .INIT(1'b0)) stg3_dec_req_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec_req_r_i_1_n_0), .Q(lim2stg3_dec), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair368" *) LUT3 #( .INIT(8'h69)) \stg3_dec_val[3]_i_1 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .O(stg3_dec_val00_out[3])); (* SOFT_HLUTNM = "soft_lutpair368" *) LUT5 #( .INIT(32'h4DB2B24D)) \stg3_dec_val[4]_i_1 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg3_init_val[4]), .O(stg3_dec_val00_out[4])); LUT5 #( .INIT(32'hFF00FF71)) \stg3_dec_val[5]_i_1 (.I0(\stg3_inc_val[5]_i_2_n_0 ), .I1(stg3_init_val[4]), .I2(\wl_po_fine_cnt_reg[17] ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(stg3_init_val[5]), .O(\stg3_dec_val[5]_i_1_n_0 )); LUT6 #( .INIT(64'hB2FF00B24D00FF4D)) \stg3_dec_val[5]_i_2 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg3_init_val[4]), .I5(stg3_init_val[5]), .O(\stg3_dec_val[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFEE0FFFF0000FEE0)) \stg3_dec_val[5]_i_3 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\wl_po_fine_cnt_reg[14] [0]), .I2(\stg3_tap_cnt_reg[2]_0 [1]), .I3(\wl_po_fine_cnt_reg[14] [1]), .I4(\wl_po_fine_cnt_reg[3] ), .I5(\stg3_tap_cnt_reg[2]_0 [2]), .O(\stg3_dec_val[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \stg3_dec_val_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(stg3_dec_val[0]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_dec_val_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(stg3_dec_val[1]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_dec_val_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(stg3_dec_val[2]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_dec_val_reg[3] (.C(CLK), .CE(1'b1), .D(stg3_dec_val00_out[3]), .Q(stg3_dec_val[3]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_dec_val_reg[4] (.C(CLK), .CE(1'b1), .D(stg3_dec_val00_out[4]), .Q(stg3_dec_val[4]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_dec_val_reg[5] (.C(CLK), .CE(1'b1), .D(\stg3_dec_val[5]_i_2_n_0 ), .Q(stg3_dec_val[5]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) stg3_inc2init_val_r1_reg (.C(CLK), .CE(1'b1), .D(stg3_inc2init_val_r), .Q(stg3_inc2init_val_r1), .R(rstdiv0_sync_r1_reg_rep__9)); LUT5 #( .INIT(32'hFF0B0008)) stg3_inc2init_val_r_i_1 (.I0(stg3_dec_r), .I1(stg3_dec_r_i_2_n_0), .I2(lim_state[11]), .I3(stg3_inc2init_val_r_i_2_n_0), .I4(stg3_inc2init_val_r), .O(stg3_inc2init_val_r_i_1_n_0)); LUT6 #( .INIT(64'hEEEEEEEEFFFFFFEF)) stg3_inc2init_val_r_i_2 (.I0(wait_cnt_en_r_i_3_n_0), .I1(\lim_state[2]_i_3_n_0 ), .I2(stg3_inc2init_val_r_i_3_n_0), .I3(stg2_inc_r_i_2_n_0), .I4(lim_state[4]), .I5(\lim_state[1]_i_2_n_0 ), .O(stg3_inc2init_val_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair383" *) LUT3 #( .INIT(8'h20)) stg3_inc2init_val_r_i_3 (.I0(\lim_state[12]_i_3_n_0 ), .I1(stg3_dec2init_val_r), .I2(stg3_inc2init_val_r), .O(stg3_inc2init_val_r_i_3_n_0)); FDRE #( .INIT(1'b0)) stg3_inc2init_val_r_reg (.C(CLK), .CE(1'b1), .D(stg3_inc2init_val_r_i_1_n_0), .Q(stg3_inc2init_val_r), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hFFFFFFF700000020)) stg3_inc_req_r_i_1 (.I0(stg3_dec_req_r_i_2_n_0), .I1(lim_state[9]), .I2(lim_state[5]), .I3(lim_state[7]), .I4(lim_state[6]), .I5(lim2stg3_inc), .O(stg3_inc_req_r_i_1_n_0)); FDRE #( .INIT(1'b0)) stg3_inc_req_r_reg (.C(CLK), .CE(1'b1), .D(stg3_inc_req_r_i_1_n_0), .Q(lim2stg3_inc), .R(rstdiv0_sync_r1_reg_rep__9)); LUT3 #( .INIT(8'hF6)) \stg3_inc_val[0]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(\stg3_tap_cnt_reg[2]_0 [0]), .I2(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair367" *) LUT5 #( .INIT(32'hFFFF9666)) \stg3_inc_val[1]_i_1 (.I0(\stg3_tap_cnt_reg[2]_0 [1]), .I1(\wl_po_fine_cnt_reg[14] [1]), .I2(\stg3_tap_cnt_reg[2]_0 [0]), .I3(\wl_po_fine_cnt_reg[14] [0]), .I4(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[1]_i_1_n_0 )); LUT4 #( .INIT(16'hFF96)) \stg3_inc_val[2]_i_1 (.I0(\stg3_tap_cnt_reg[2]_0 [2]), .I1(\wl_po_fine_cnt_reg[3] ), .I2(\stg3_inc_val[2]_i_2_n_0 ), .I3(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair367" *) LUT4 #( .INIT(16'h077F)) \stg3_inc_val[2]_i_2 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\wl_po_fine_cnt_reg[14] [0]), .I2(\wl_po_fine_cnt_reg[14] [1]), .I3(\stg3_tap_cnt_reg[2]_0 [1]), .O(\stg3_inc_val[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair378" *) LUT4 #( .INIT(16'hFF96)) \stg3_inc_val[3]_i_1 (.I0(stg3_init_val[3]), .I1(\byte_r_reg[0] ), .I2(\stg3_inc_val[3]_i_2_n_0 ), .I3(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[3]_i_1_n_0 )); LUT6 #( .INIT(64'h077FFFFF0000077F)) \stg3_inc_val[3]_i_2 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\wl_po_fine_cnt_reg[14] [0]), .I2(\wl_po_fine_cnt_reg[14] [1]), .I3(\stg3_tap_cnt_reg[2]_0 [1]), .I4(\stg3_tap_cnt_reg[2]_0 [2]), .I5(\wl_po_fine_cnt_reg[3] ), .O(\stg3_inc_val[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair371" *) LUT4 #( .INIT(16'hFF69)) \stg3_inc_val[4]_i_1 (.I0(stg3_init_val[4]), .I1(\wl_po_fine_cnt_reg[17] ), .I2(\stg3_inc_val[5]_i_2_n_0 ), .I3(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair371" *) LUT5 #( .INIT(32'hFFFF718E)) \stg3_inc_val[5]_i_1 (.I0(\stg3_inc_val[5]_i_2_n_0 ), .I1(stg3_init_val[4]), .I2(\wl_po_fine_cnt_reg[17] ), .I3(stg3_init_val[5]), .I4(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair378" *) LUT3 #( .INIT(8'h4D)) \stg3_inc_val[5]_i_2 (.I0(\stg3_inc_val[3]_i_2_n_0 ), .I1(stg3_init_val[3]), .I2(\byte_r_reg[0] ), .O(\stg3_inc_val[5]_i_2_n_0 )); LUT6 #( .INIT(64'hB2FF00B200000000)) \stg3_inc_val[5]_i_3 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg3_init_val[4]), .I5(stg3_init_val[5]), .O(\stg3_inc_val[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \stg3_inc_val_reg[0] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[0]_i_1_n_0 ), .Q(stg3_inc_val[0]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \stg3_inc_val_reg[1] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[1]_i_1_n_0 ), .Q(stg3_inc_val[1]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \stg3_inc_val_reg[2] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[2]_i_1_n_0 ), .Q(stg3_inc_val[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \stg3_inc_val_reg[3] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[3]_i_1_n_0 ), .Q(stg3_inc_val[3]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \stg3_inc_val_reg[4] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[4]_i_1_n_0 ), .Q(stg3_inc_val[4]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \stg3_inc_val_reg[5] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[5]_i_1_n_0 ), .Q(stg3_inc_val[5]), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFFF70000FF00)) stg3_init_dec_r_i_1 (.I0(\lim_state[6]_i_3_n_0 ), .I1(stg3_init_dec_r_i_2_n_0), .I2(lim_state[0]), .I3(stg3_init_dec_r_i_3_n_0), .I4(stg3_init_dec_r_i_4_n_0), .I5(stg3_init_dec_r), .O(stg3_init_dec_r_i_1_n_0)); LUT3 #( .INIT(8'h02)) stg3_init_dec_r_i_2 (.I0(po_rdy), .I1(lim2stg3_dec), .I2(lim2stg3_inc), .O(stg3_init_dec_r_i_2_n_0)); LUT3 #( .INIT(8'h04)) stg3_init_dec_r_i_3 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[9]), .O(stg3_init_dec_r_i_3_n_0)); LUT5 #( .INIT(32'hEFEFEFFF)) stg3_init_dec_r_i_4 (.I0(\lim_state[13]_i_7_n_0 ), .I1(lim_state[1]), .I2(\lim_state[6]_i_6_n_0 ), .I3(lim_state[9]), .I4(lim_state[0]), .O(stg3_init_dec_r_i_4_n_0)); FDRE #( .INIT(1'b0)) stg3_init_dec_r_reg (.C(CLK), .CE(1'b1), .D(stg3_init_dec_r_i_1_n_0), .Q(stg3_init_dec_r), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \stg3_init_val_reg[0] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[0]), .Q(\stg3_tap_cnt_reg[2]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_init_val_reg[1] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[1]), .Q(\stg3_tap_cnt_reg[2]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_init_val_reg[2] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[2]), .Q(\stg3_tap_cnt_reg[2]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_init_val_reg[3] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[3]), .Q(stg3_init_val[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_init_val_reg[4] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[4]), .Q(stg3_init_val[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_init_val_reg[5] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[5]), .Q(stg3_init_val[5]), .R(1'b0)); LUT5 #( .INIT(32'hAAAAFBAA)) \stg3_left_lim[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(stg3_inc2init_val_r), .I2(stg3_inc2init_val_r1), .I3(lim_start), .I4(lim_start_r), .O(\stg3_left_lim[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \stg3_left_lim[5]_i_2 (.I0(stg3_inc2init_val_r), .I1(stg3_inc2init_val_r1), .O(stg3_left_lim0)); FDRE #( .INIT(1'b0)) \stg3_left_lim_reg[0] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[0] ), .Q(scanning_right_r_reg_0[0]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_left_lim_reg[1] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[1] ), .Q(scanning_right_r_reg_0[1]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_left_lim_reg[2] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[2] ), .Q(scanning_right_r_reg_0[2]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_left_lim_reg[3] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[3] ), .Q(scanning_right_r_reg_0[3]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_left_lim_reg[4] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[4] ), .Q(scanning_right_r_reg_0[4]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_left_lim_reg[5] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[5] ), .Q(scanning_right_r_reg_0[5]), .R(\stg3_left_lim[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAAAAFBAA)) \stg3_right_lim[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(stg3_dec2init_val_r), .I2(stg3_dec2init_val_r1), .I3(lim_start), .I4(lim_start_r), .O(\stg3_right_lim[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \stg3_right_lim[5]_i_2 (.I0(stg3_dec2init_val_r), .I1(stg3_dec2init_val_r1), .O(stg3_right_lim0)); FDRE #( .INIT(1'b0)) \stg3_right_lim_reg[0] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[0] ), .Q(oclkdelay_center_calib_start_r_reg_0[0]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_right_lim_reg[1] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[1] ), .Q(oclkdelay_center_calib_start_r_reg_0[1]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_right_lim_reg[2] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[2] ), .Q(oclkdelay_center_calib_start_r_reg_0[2]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_right_lim_reg[3] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[3] ), .Q(oclkdelay_center_calib_start_r_reg_0[3]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_right_lim_reg[4] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[4] ), .Q(oclkdelay_center_calib_start_r_reg_0[4]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg3_right_lim_reg[5] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[5] ), .Q(oclkdelay_center_calib_start_r_reg_0[5]), .R(\stg3_right_lim[5]_i_1_n_0 )); LUT3 #( .INIT(8'h3A)) \stg3_tap_cnt[0]_i_1 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(rstdiv0_sync_r1_reg_rep__25_0), .O(\stg3_tap_cnt[0]_i_1_n_0 )); LUT5 #( .INIT(32'h96FF9600)) \stg3_tap_cnt[1]_i_1 (.I0(\stg3_tap_cnt[1]_i_2_n_0 ), .I1(\stg3_tap_cnt_reg_n_0_[1] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(rstdiv0_sync_r1_reg_rep__25_0), .I4(\stg3_tap_cnt_reg[2]_0 [1]), .O(\stg3_tap_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \stg3_tap_cnt[1]_i_2 (.I0(\stg2_tap_cnt[1]_i_4_n_0 ), .I1(lim_state[12]), .I2(\lim_state[2]_i_3_n_0 ), .I3(lim_state[7]), .I4(lim_state[6]), .I5(lim_state[5]), .O(\stg3_tap_cnt[1]_i_2_n_0 )); LUT4 #( .INIT(16'h6F60)) \stg3_tap_cnt[2]_i_1 (.I0(\stg3_tap_cnt_reg_n_0_[2] ), .I1(\stg3_tap_cnt[2]_i_2_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__25_0), .I3(\stg3_tap_cnt_reg[2]_0 [2]), .O(\stg3_tap_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h001000000000FFEF)) \stg3_tap_cnt[2]_i_2 (.I0(\lim_state[2]_i_3_n_0 ), .I1(lim_state[12]), .I2(lim_state[5]), .I3(\stg3_tap_cnt[3]_i_4_n_0 ), .I4(\stg3_tap_cnt_reg_n_0_[0] ), .I5(\stg3_tap_cnt_reg_n_0_[1] ), .O(\stg3_tap_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hD32CFFFFD32C0000)) \stg3_tap_cnt[3]_i_1 (.I0(\stg3_tap_cnt[3]_i_2_n_0 ), .I1(\stg3_tap_cnt[3]_i_3_n_0 ), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .I4(rstdiv0_sync_r1_reg_rep__25_0), .I5(stg3_init_val[3]), .O(\stg3_tap_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000800)) \stg3_tap_cnt[3]_i_2 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(\stg3_tap_cnt[3]_i_4_n_0 ), .I3(lim_state[5]), .I4(lim_state[12]), .I5(\lim_state[2]_i_3_n_0 ), .O(\stg3_tap_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h1111111111101111)) \stg3_tap_cnt[3]_i_3 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(\lim_state[2]_i_3_n_0 ), .I3(lim_state[12]), .I4(lim_state[5]), .I5(\stg3_tap_cnt[3]_i_4_n_0 ), .O(\stg3_tap_cnt[3]_i_3_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \stg3_tap_cnt[3]_i_4 (.I0(\lim_state[13]_i_4_n_0 ), .I1(lim_state[7]), .I2(lim_state[6]), .I3(lim_state[4]), .I4(lim_state[13]), .O(\stg3_tap_cnt[3]_i_4_n_0 )); LUT5 #( .INIT(32'h56FF5600)) \stg3_tap_cnt[4]_i_1 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(\stg3_tap_cnt[5]_i_4_n_0 ), .I2(\stg3_tap_cnt[5]_i_5_n_0 ), .I3(rstdiv0_sync_r1_reg_rep__25_0), .I4(stg3_init_val[4]), .O(\stg3_tap_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'h1400FFFF)) \stg3_tap_cnt[5]_i_1 (.I0(lim_state[11]), .I1(lim_state[5]), .I2(lim_state[6]), .I3(\lim_state[9]_i_2_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__25_0), .O(stg3_tap_cnt0)); LUT6 #( .INIT(64'hD32CFFFFD32C0000)) \stg3_tap_cnt[5]_i_2 (.I0(\stg3_tap_cnt[5]_i_4_n_0 ), .I1(\stg3_tap_cnt[5]_i_5_n_0 ), .I2(\stg3_tap_cnt_reg_n_0_[4] ), .I3(\stg3_tap_cnt_reg_n_0_[5] ), .I4(rstdiv0_sync_r1_reg_rep__25_0), .I5(stg3_init_val[5]), .O(\stg3_tap_cnt[5]_i_2_n_0 )); LUT5 #( .INIT(32'h00008000)) \stg3_tap_cnt[5]_i_4 (.I0(\stg3_tap_cnt_reg_n_0_[2] ), .I1(\stg3_tap_cnt_reg_n_0_[3] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt[1]_i_2_n_0 ), .O(\stg3_tap_cnt[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair374" *) LUT5 #( .INIT(32'h00000001)) \stg3_tap_cnt[5]_i_5 (.I0(\stg3_tap_cnt_reg_n_0_[3] ), .I1(\stg3_tap_cnt_reg_n_0_[2] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt[5]_i_6_n_0 ), .O(\stg3_tap_cnt[5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair377" *) LUT4 #( .INIT(16'h0004)) \stg3_tap_cnt[5]_i_6 (.I0(\stg3_tap_cnt[3]_i_4_n_0 ), .I1(lim_state[5]), .I2(lim_state[12]), .I3(\lim_state[2]_i_3_n_0 ), .O(\stg3_tap_cnt[5]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \stg3_tap_cnt_reg[0] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[0]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_tap_cnt_reg[1] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[1]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_tap_cnt_reg[2] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[2]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_tap_cnt_reg[3] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[3]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_tap_cnt_reg[4] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[4]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_tap_cnt_reg[5] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[5]_i_2_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[5] ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) wait_cnt_done_i_1 (.I0(wait_cnt_en_r), .I1(wait_cnt_r_reg__0[2]), .I2(wait_cnt_r_reg__0[3]), .I3(wait_cnt_r_reg__0[1]), .I4(wait_cnt_r_reg__0[0]), .O(wait_cnt_done_i_1_n_0)); FDRE #( .INIT(1'b0)) wait_cnt_done_reg (.C(CLK), .CE(1'b1), .D(wait_cnt_done_i_1_n_0), .Q(wait_cnt_done), .R(1'b0)); LUT6 #( .INIT(64'h0000000000010110)) wait_cnt_en_r_i_1 (.I0(wait_cnt_en_r_i_2_n_0), .I1(lim_state[0]), .I2(lim_state[1]), .I3(lim_state[4]), .I4(lim_state[2]), .I5(lim_state[3]), .O(wait_cnt_en_r0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) wait_cnt_en_r_i_2 (.I0(wait_cnt_en_r_i_3_n_0), .I1(lim_state[13]), .I2(lim_state[9]), .I3(lim_state[12]), .I4(lim_state[10]), .I5(lim_state[11]), .O(wait_cnt_en_r_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) wait_cnt_en_r_i_3 (.I0(lim_state[5]), .I1(lim_state[6]), .I2(lim_state[7]), .I3(lim_state[8]), .O(wait_cnt_en_r_i_3_n_0)); FDRE #( .INIT(1'b0)) wait_cnt_en_r_reg (.C(CLK), .CE(1'b1), .D(wait_cnt_en_r0), .Q(wait_cnt_en_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair391" *) LUT1 #( .INIT(2'h1)) \wait_cnt_r[0]_i_1 (.I0(wait_cnt_r_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair391" *) LUT2 #( .INIT(4'h6)) \wait_cnt_r[1]_i_1 (.I0(wait_cnt_r_reg__0[0]), .I1(wait_cnt_r_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair382" *) LUT3 #( .INIT(8'h6A)) \wait_cnt_r[2]_i_1 (.I0(wait_cnt_r_reg__0[2]), .I1(wait_cnt_r_reg__0[1]), .I2(wait_cnt_r_reg__0[0]), .O(p_0_in[2])); LUT5 #( .INIT(32'h0080FFFF)) \wait_cnt_r[3]_i_1 (.I0(wait_cnt_r_reg__0[2]), .I1(wait_cnt_r_reg__0[3]), .I2(wait_cnt_r_reg__0[1]), .I3(wait_cnt_r_reg__0[0]), .I4(wait_cnt_en_r), .O(\wait_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair382" *) LUT4 #( .INIT(16'h6AAA)) \wait_cnt_r[3]_i_2 (.I0(wait_cnt_r_reg__0[3]), .I1(wait_cnt_r_reg__0[0]), .I2(wait_cnt_r_reg__0[1]), .I3(wait_cnt_r_reg__0[2]), .O(p_0_in[3])); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in[0]), .Q(wait_cnt_r_reg__0[0]), .R(\wait_cnt_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in[1]), .Q(wait_cnt_r_reg__0[1]), .R(\wait_cnt_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in[2]), .Q(wait_cnt_r_reg__0[2]), .R(\wait_cnt_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in[3]), .Q(wait_cnt_r_reg__0[3]), .R(\wait_cnt_r[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFF7F0C00)) write_request_r_i_1 (.I0(done_r_reg_1), .I1(write_request_r_i_2_n_0), .I2(lim_state[3]), .I3(lim_state[2]), .I4(lim2init_write_request), .O(write_request_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair369" *) LUT5 #( .INIT(32'h00000002)) write_request_r_i_2 (.I0(\lim_state[4]_i_3_n_0 ), .I1(lim_state[4]), .I2(lim_state[13]), .I3(lim_state[1]), .I4(lim_state[0]), .O(write_request_r_i_2_n_0)); FDRE #( .INIT(1'b0)) write_request_r_reg (.C(CLK), .CE(1'b1), .D(write_request_r_i_1_n_0), .Q(lim2init_write_request), .R(rstdiv0_sync_r1_reg_rep__9)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_mux" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_mux (po_rdy, po_stg23_incdec, \po_wait_r_reg[3]_0 , D_po_sel_fine_oclk_delay125_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , po_stg23_sel_r_reg_0, CLK, stg3_inc_req_r_reg, stg3_dec_req_r_reg, Q, calib_in_common, \calib_zero_inputs_reg[1] , rstdiv0_sync_r1_reg_rep__24, \gen_byte_sel_div1.calib_in_common_reg , ck_addr_cmd_delay_done, oclkdelay_calib_done_r_reg, mpr_rdlvl_done_r_reg, \gen_byte_sel_div1.calib_in_common_reg_0 , \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , stg2_dec_req_r_reg, setup_po, rstdiv0_sync_r1_reg_rep__10); output po_rdy; output po_stg23_incdec; output \po_wait_r_reg[3]_0 ; output D_po_sel_fine_oclk_delay125_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output po_stg23_sel_r_reg_0; input CLK; input stg3_inc_req_r_reg; input stg3_dec_req_r_reg; input [1:0]Q; input calib_in_common; input [1:0]\calib_zero_inputs_reg[1] ; input rstdiv0_sync_r1_reg_rep__24; input \gen_byte_sel_div1.calib_in_common_reg ; input ck_addr_cmd_delay_done; input oclkdelay_calib_done_r_reg; input mpr_rdlvl_done_r_reg; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input stg2_dec_req_r_reg; input setup_po; input rstdiv0_sync_r1_reg_rep__10; wire CLK; wire D_po_sel_fine_oclk_delay125_out; wire [1:0]Q; wire calib_in_common; wire [1:0]\calib_zero_inputs_reg[1] ; wire ck_addr_cmd_delay_done; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire mpr_rdlvl_done_r_reg; wire oclkdelay_calib_done_r_reg; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire po_en_stg23_r_i_1_n_0; wire po_rdy; wire po_rdy_ns; wire [0:0]po_sel_stg2stg3; wire [1:0]po_setup_r; wire po_setup_r0; wire \po_setup_r[0]_i_1_n_0 ; wire \po_setup_r[1]_i_1_n_0 ; wire po_stg23_incdec; wire po_stg23_sel; wire po_stg23_sel_r_reg_0; wire [3:0]po_wait_r; wire \po_wait_r[0]_i_1_n_0 ; wire \po_wait_r[1]_i_1_n_0 ; wire \po_wait_r[2]_i_1_n_0 ; wire \po_wait_r[3]_i_1_n_0 ; wire \po_wait_r_reg[3]_0 ; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__24; wire setup_po; wire stg2_dec_req_r_reg; wire stg3_dec_req_r_reg; wire stg3_inc_req_r_reg; LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__3 (.I0(\gen_byte_sel_div1.calib_in_common_reg ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_2 )); LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_3 )); LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__5 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_4 )); LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__6 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_5 )); (* SOFT_HLUTNM = "soft_lutpair392" *) LUT5 #( .INIT(32'h00000800)) phaser_out_i_5 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(D_po_sel_fine_oclk_delay125_out)); (* SOFT_HLUTNM = "soft_lutpair392" *) LUT5 #( .INIT(32'h00000100)) phaser_out_i_5__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair393" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_5__1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_0 )); (* SOFT_HLUTNM = "soft_lutpair393" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_5__2 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_1 )); LUT4 #( .INIT(16'h0800)) phaser_out_i_6 (.I0(ck_addr_cmd_delay_done), .I1(po_stg23_sel), .I2(oclkdelay_calib_done_r_reg), .I3(mpr_rdlvl_done_r_reg), .O(po_sel_stg2stg3)); (* SOFT_HLUTNM = "soft_lutpair394" *) LUT3 #( .INIT(8'h04)) po_en_stg23_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(po_setup_r[0]), .I2(po_setup_r[1]), .O(po_en_stg23_r_i_1_n_0)); FDRE #( .INIT(1'b0)) po_en_stg23_r_reg (.C(CLK), .CE(1'b1), .D(po_en_stg23_r_i_1_n_0), .Q(\po_wait_r_reg[3]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000001)) po_rdy_r_i_1 (.I0(setup_po), .I1(\po_wait_r[3]_i_1_n_0 ), .I2(po_setup_r0), .I3(\po_wait_r[0]_i_1_n_0 ), .I4(\po_wait_r[1]_i_1_n_0 ), .I5(\po_wait_r[2]_i_1_n_0 ), .O(po_rdy_ns)); (* SOFT_HLUTNM = "soft_lutpair394" *) LUT2 #( .INIT(4'hE)) po_rdy_r_i_3 (.I0(po_setup_r[0]), .I1(po_setup_r[1]), .O(po_setup_r0)); FDRE #( .INIT(1'b0)) po_rdy_r_reg (.C(CLK), .CE(1'b1), .D(po_rdy_ns), .Q(po_rdy), .R(1'b0)); LUT3 #( .INIT(8'hF2)) \po_setup_r[0]_i_1 (.I0(po_setup_r[1]), .I1(po_setup_r[0]), .I2(setup_po), .O(\po_setup_r[0]_i_1_n_0 )); LUT3 #( .INIT(8'hF8)) \po_setup_r[1]_i_1 (.I0(po_setup_r[1]), .I1(po_setup_r[0]), .I2(setup_po), .O(\po_setup_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \po_setup_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_setup_r[0]_i_1_n_0 ), .Q(po_setup_r[0]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \po_setup_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_setup_r[1]_i_1_n_0 ), .Q(po_setup_r[1]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) po_stg23_incdec_r_reg (.C(CLK), .CE(1'b1), .D(stg3_inc_req_r_reg), .Q(po_stg23_incdec), .R(1'b0)); LUT6 #( .INIT(64'h5555555100000000)) po_stg23_sel_r_i_2 (.I0(stg2_dec_req_r_reg), .I1(po_wait_r[0]), .I2(po_wait_r[1]), .I3(po_wait_r[3]), .I4(po_wait_r[2]), .I5(po_stg23_sel), .O(po_stg23_sel_r_reg_0)); FDRE #( .INIT(1'b0)) po_stg23_sel_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec_req_r_reg), .Q(po_stg23_sel), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000FE)) \po_wait_r[0]_i_1 (.I0(po_wait_r[1]), .I1(po_wait_r[2]), .I2(po_wait_r[3]), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(po_wait_r[0]), .I5(\po_wait_r_reg[3]_0 ), .O(\po_wait_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h5445544554455444)) \po_wait_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(\po_wait_r_reg[3]_0 ), .I2(po_wait_r[0]), .I3(po_wait_r[1]), .I4(po_wait_r[2]), .I5(po_wait_r[3]), .O(\po_wait_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h5554444555544444)) \po_wait_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(\po_wait_r_reg[3]_0 ), .I2(po_wait_r[0]), .I3(po_wait_r[1]), .I4(po_wait_r[2]), .I5(po_wait_r[3]), .O(\po_wait_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h5555555444444444)) \po_wait_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(\po_wait_r_reg[3]_0 ), .I2(po_wait_r[2]), .I3(po_wait_r[0]), .I4(po_wait_r[1]), .I5(po_wait_r[3]), .O(\po_wait_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \po_wait_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_wait_r[0]_i_1_n_0 ), .Q(po_wait_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_wait_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_wait_r[1]_i_1_n_0 ), .Q(po_wait_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_wait_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_wait_r[2]_i_1_n_0 ), .Q(po_wait_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_wait_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_wait_r[3]_i_1_n_0 ), .Q(po_wait_r[3]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_po_cntlr" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_po_cntlr (O, ocal_last_byte_done_reg, oclk_center_write_resume, complex_ocal_num_samples_done_r, \sm_r_reg[3]_0 , oclkdelay_center_calib_start_r_reg_0, scanning_right, S, Q, po_stg23_incdec_r_reg, setup_po, \stg2_r_reg[0]_0 , \two_r_reg[1]_0 , E, o2f_r_reg, f2z_r_reg, \stg2_target_r_reg[8]_0 , po_stg23_incdec_r_reg_0, \stg3_init_val_reg[5] , \stg3_init_val_reg[3] , \stg3_init_val_reg[4] , \stg3_init_val_reg[2] , \stg3_init_val_reg[1] , \stg3_init_val_reg[0] , \rise_trail_r_reg[5] , \run_ends_r_reg[1] , \sm_r_reg[0]_0 , D, samp_done_ns8_out, ninety_offsets, use_noise_window, \init_state_r_reg[0] , poc_backup_r_reg_0, edge_aligned_r_reg, \stg3_init_val_reg[4]_0 , \stg3_init_val_reg[2]_0 , rstdiv0_sync_r1_reg_rep__10, CLK, dec_po_ns, inc_po_ns, rstdiv0_sync_r1_reg_rep__9, \wl_po_fine_cnt_reg[14] , \stg3_r_reg[0]_0 , f2o_r_reg, f2o_r_reg_0, rstdiv0_sync_r1_reg_rep__25, lim2stg3_inc, po_stg23_incdec, ocd_cntlr2stg2_dec_r, scanning_right_r_reg_0, scan_right_r_reg, samp_done, rd_active_r2, poc_backup_r_reg_1, done_r_reg, rstdiv0_sync_r1_reg_rep__24, o2f_ns1_out, o2f_r_reg_0, f2z_ns5_out, f2z_r_reg_0, rstdiv0_sync_r1_reg_rep__20, lim2stg3_dec, lim2stg2_dec, \byte_r_reg[0] , \wl_po_fine_cnt_reg[3] , \wl_po_fine_cnt_reg[17] , \wl_po_fine_cnt_reg[18] , \byte_r_reg[0]_0 , \byte_r_reg[1] , oclkdelay_calib_done_r_reg, lim2poc_ktap_right, lim2poc_rdy, po_rdy, lim2stg2_inc, edge_aligned_r_reg_0, \sm_r_reg[0]_1 , reset_scan, rstdiv0_sync_r1_reg_rep__25_0, samp_done_r_reg, wrlvl_final_mux, oclkdelay_int_ref_req_reg, prech_req_posedge_r_reg, oclkdelay_calib_done_r_reg_0, \run_ends_r_reg[1]_0 , \run_ends_r_reg[0] , \po_counter_read_val_reg[5] , \byte_r_reg[0]_1 , \byte_r_reg[1]_0 , \byte_r_reg[0]_2 , \byte_r_reg[0]_3 , \wl_po_fine_cnt_reg[23] ); output [3:0]O; output ocal_last_byte_done_reg; output oclk_center_write_resume; output complex_ocal_num_samples_done_r; output \sm_r_reg[3]_0 ; output oclkdelay_center_calib_start_r_reg_0; output scanning_right; output [0:0]S; output [5:0]Q; output po_stg23_incdec_r_reg; output setup_po; output [0:0]\stg2_r_reg[0]_0 ; output \two_r_reg[1]_0 ; output [0:0]E; output o2f_r_reg; output f2z_r_reg; output [2:0]\stg2_target_r_reg[8]_0 ; output po_stg23_incdec_r_reg_0; output \stg3_init_val_reg[5] ; output [0:0]\stg3_init_val_reg[3] ; output \stg3_init_val_reg[4] ; output \stg3_init_val_reg[2] ; output \stg3_init_val_reg[1] ; output \stg3_init_val_reg[0] ; output \rise_trail_r_reg[5] ; output \run_ends_r_reg[1] ; output \sm_r_reg[0]_0 ; output [5:0]D; output samp_done_ns8_out; output [1:0]ninety_offsets; output use_noise_window; output \init_state_r_reg[0] ; output poc_backup_r_reg_0; output edge_aligned_r_reg; output \stg3_init_val_reg[4]_0 ; output \stg3_init_val_reg[2]_0 ; input rstdiv0_sync_r1_reg_rep__10; input CLK; input dec_po_ns; input inc_po_ns; input rstdiv0_sync_r1_reg_rep__9; input [1:0]\wl_po_fine_cnt_reg[14] ; input \stg3_r_reg[0]_0 ; input f2o_r_reg; input f2o_r_reg_0; input rstdiv0_sync_r1_reg_rep__25; input lim2stg3_inc; input po_stg23_incdec; input ocd_cntlr2stg2_dec_r; input scanning_right_r_reg_0; input scan_right_r_reg; input samp_done; input rd_active_r2; input poc_backup_r_reg_1; input done_r_reg; input rstdiv0_sync_r1_reg_rep__24; input o2f_ns1_out; input o2f_r_reg_0; input f2z_ns5_out; input f2z_r_reg_0; input rstdiv0_sync_r1_reg_rep__20; input lim2stg3_dec; input lim2stg2_dec; input \byte_r_reg[0] ; input \wl_po_fine_cnt_reg[3] ; input \wl_po_fine_cnt_reg[17] ; input \wl_po_fine_cnt_reg[18] ; input \byte_r_reg[0]_0 ; input \byte_r_reg[1] ; input oclkdelay_calib_done_r_reg; input lim2poc_ktap_right; input lim2poc_rdy; input po_rdy; input lim2stg2_inc; input edge_aligned_r_reg_0; input \sm_r_reg[0]_1 ; input reset_scan; input rstdiv0_sync_r1_reg_rep__25_0; input samp_done_r_reg; input wrlvl_final_mux; input oclkdelay_int_ref_req_reg; input prech_req_posedge_r_reg; input oclkdelay_calib_done_r_reg_0; input \run_ends_r_reg[1]_0 ; input \run_ends_r_reg[0] ; input [5:0]\po_counter_read_val_reg[5] ; input \byte_r_reg[0]_1 ; input \byte_r_reg[1]_0 ; input \byte_r_reg[0]_2 ; input \byte_r_reg[0]_3 ; input [7:0]\wl_po_fine_cnt_reg[23] ; wire [8:0]A; wire CLK; wire [5:0]D; wire [0:0]E; wire [3:0]O; wire [5:0]Q; wire [0:0]S; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[0]_1 ; wire \byte_r_reg[0]_2 ; wire \byte_r_reg[0]_3 ; wire \byte_r_reg[1] ; wire \byte_r_reg[1]_0 ; wire cmplx_samples_done_r_i_2_n_0; wire cmplx_samples_done_r_i_3_n_0; wire complex_ocal_num_samples_done_r; wire dec_po_ns; wire dec_po_r; wire done_r_reg; wire edge_aligned_r_reg; wire edge_aligned_r_reg_0; wire f2o_r_reg; wire f2o_r_reg_0; wire f2z_ns5_out; wire f2z_r_reg; wire f2z_r_reg_0; wire inc_po_ns; wire inc_po_r; wire \init_state_r_reg[0] ; wire lim2poc_ktap_right; wire lim2poc_rdy; wire lim2stg2_dec; wire lim2stg2_inc; wire lim2stg3_dec; wire lim2stg3_inc; wire [1:0]ninety_offsets; wire [1:0]ninety_offsets_final_r; wire ninety_offsets_ns; wire \ninety_offsets_r[0]_i_1_n_0 ; wire \ninety_offsets_r[1]_i_1_n_0 ; wire \ninety_offsets_r[1]_i_3_n_0 ; wire \ninety_offsets_r[1]_i_4_n_0 ; wire o2f_ns1_out; wire o2f_r_reg; wire o2f_r_reg_0; wire ocal_last_byte_done_reg; wire ocd2stg3_dec; wire ocd_cntlr2stg2_dec_r; wire ocd_edge_detect_rdy; wire ocd_edge_detect_rdy_r_i_1_n_0; wire ocd_ktap_left_r_i_2_n_0; wire ocd_ktap_left_r_i_3_n_0; wire ocd_ktap_left_r_i_4_n_0; wire ocd_ktap_right; wire ocd_ktap_right_r_i_1_n_0; wire oclk_calib_resume_r_i_5_n_0; wire oclk_center_write_resume; wire oclk_center_write_resume_r_i_2_n_0; wire oclk_center_write_resume_r_i_3_n_0; wire oclk_center_write_resume_r_i_4_n_0; wire oclk_center_write_resume_r_i_5_n_0; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_center_calib_done_r_i_1_n_0; wire oclkdelay_center_calib_done_r_i_2_n_0; wire oclkdelay_center_calib_done_r_i_3_n_0; wire oclkdelay_center_calib_done_r_i_4_n_0; wire oclkdelay_center_calib_start_r_i_1_n_0; wire oclkdelay_center_calib_start_r_reg_0; wire oclkdelay_int_ref_req_reg; wire [8:1]out; wire [5:0]p_0_in; wire p_0_in0_carry__0_i_1_n_0; wire p_0_in0_carry__0_i_2_n_0; wire p_0_in0_carry__0_i_3_n_0; wire p_0_in0_carry__0_i_4_n_0; wire p_0_in0_carry__0_n_2; wire p_0_in0_carry__0_n_3; wire p_0_in0_carry__0_n_5; wire p_0_in0_carry__0_n_6; wire p_0_in0_carry__0_n_7; wire p_0_in0_carry_i_10_n_0; wire p_0_in0_carry_i_10_n_1; wire p_0_in0_carry_i_10_n_2; wire p_0_in0_carry_i_10_n_3; wire p_0_in0_carry_i_10_n_4; wire p_0_in0_carry_i_10_n_5; wire p_0_in0_carry_i_10_n_6; wire p_0_in0_carry_i_11_n_3; wire p_0_in0_carry_i_11_n_6; wire p_0_in0_carry_i_11_n_7; wire p_0_in0_carry_i_12_n_3; wire p_0_in0_carry_i_13_n_0; wire p_0_in0_carry_i_14_n_0; wire p_0_in0_carry_i_15_n_0; wire p_0_in0_carry_i_16_n_0; wire p_0_in0_carry_i_17_n_0; wire p_0_in0_carry_i_18_n_0; wire p_0_in0_carry_i_19_n_0; wire p_0_in0_carry_i_1_n_0; wire p_0_in0_carry_i_20_n_0; wire p_0_in0_carry_i_21_n_0; wire p_0_in0_carry_i_22_n_0; wire p_0_in0_carry_i_23_n_0; wire p_0_in0_carry_i_24_n_0; wire p_0_in0_carry_i_2_n_0; wire p_0_in0_carry_i_3_n_0; wire p_0_in0_carry_i_4_n_0; wire p_0_in0_carry_i_5_n_0; wire p_0_in0_carry_i_6_n_0; wire p_0_in0_carry_i_7_n_0; wire p_0_in0_carry_i_8_n_0; wire p_0_in0_carry_i_8_n_1; wire p_0_in0_carry_i_8_n_2; wire p_0_in0_carry_i_8_n_3; wire p_0_in0_carry_i_9_n_0; wire p_0_in0_carry_n_0; wire p_0_in0_carry_n_1; wire p_0_in0_carry_n_2; wire p_0_in0_carry_n_3; wire p_1_in; wire p_55_in; wire p_58_in; wire p_63_in; wire [5:0]po_counter_read_val_r; wire [5:0]\po_counter_read_val_reg[5] ; wire po_done_ns; wire po_done_r; wire po_done_r_i_1_n_0; wire po_rdy; wire po_rdy_r_i_5_n_0; wire po_rdy_r_i_6_n_0; wire po_rdy_r_i_7_n_0; wire po_stg23_incdec; wire po_stg23_incdec_r_i_10_n_0; wire po_stg23_incdec_r_i_2_n_0; wire po_stg23_incdec_r_i_3_n_0; wire po_stg23_incdec_r_i_4_n_0; wire po_stg23_incdec_r_i_5_n_0; wire po_stg23_incdec_r_i_6_n_0; wire po_stg23_incdec_r_i_7_n_0; wire po_stg23_incdec_r_i_8_n_0; wire po_stg23_incdec_r_i_9_n_0; wire po_stg23_incdec_r_reg; wire po_stg23_incdec_r_reg_0; wire poc_backup_r; wire poc_backup_r_i_1__0_n_0; wire poc_backup_r_i_2__0_n_0; wire poc_backup_r_i_3_n_0; wire poc_backup_r_i_4_n_0; wire poc_backup_r_i_5_n_0; wire poc_backup_r_reg_0; wire poc_backup_r_reg_1; wire prech_req_posedge_r_reg; wire rd_active_r2; wire reset_scan; wire [9:5]resume_wait_ns0; wire [10:0]resume_wait_r; wire \resume_wait_r[0]_i_1_n_0 ; wire \resume_wait_r[10]_i_1_n_0 ; wire \resume_wait_r[10]_i_2_n_0 ; wire \resume_wait_r[10]_i_3_n_0 ; wire \resume_wait_r[10]_i_4_n_0 ; wire \resume_wait_r[1]_i_1_n_0 ; wire \resume_wait_r[2]_i_1_n_0 ; wire \resume_wait_r[2]_i_2_n_0 ; wire \resume_wait_r[3]_i_1_n_0 ; wire \resume_wait_r[4]_i_1_n_0 ; wire \resume_wait_r[4]_i_2_n_0 ; wire \resume_wait_r[7]_i_2_n_0 ; wire \resume_wait_r[9]_i_1_n_0 ; wire \resume_wait_r[9]_i_4_n_0 ; wire \resume_wait_r[9]_i_5_n_0 ; wire \resume_wait_r[9]_i_6_n_0 ; wire \resume_wait_r[9]_i_7_n_0 ; wire \resume_wait_r[9]_i_8_n_0 ; wire \rise_trail_r_reg[5] ; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__9; wire \run_ends_r_reg[0] ; wire \run_ends_r_reg[1] ; wire \run_ends_r_reg[1]_0 ; wire samp_done; wire samp_done_ns8_out; wire samp_done_r_reg; wire scan_right_r_reg; wire scanning_right; wire scanning_right_r_i_1_n_0; wire scanning_right_r_i_3_n_0; wire scanning_right_r_reg_0; wire setup_po; wire \simp_stg3_final_r_reg_n_0_[0] ; wire \simp_stg3_final_r_reg_n_0_[10] ; wire \simp_stg3_final_r_reg_n_0_[11] ; wire \simp_stg3_final_r_reg_n_0_[12] ; wire \simp_stg3_final_r_reg_n_0_[13] ; wire \simp_stg3_final_r_reg_n_0_[14] ; wire \simp_stg3_final_r_reg_n_0_[15] ; wire \simp_stg3_final_r_reg_n_0_[17] ; wire \simp_stg3_final_r_reg_n_0_[18] ; wire \simp_stg3_final_r_reg_n_0_[19] ; wire \simp_stg3_final_r_reg_n_0_[1] ; wire \simp_stg3_final_r_reg_n_0_[20] ; wire \simp_stg3_final_r_reg_n_0_[21] ; wire \simp_stg3_final_r_reg_n_0_[22] ; wire \simp_stg3_final_r_reg_n_0_[23] ; wire \simp_stg3_final_r_reg_n_0_[3] ; wire \simp_stg3_final_r_reg_n_0_[4] ; wire \simp_stg3_final_r_reg_n_0_[5] ; wire \simp_stg3_final_r_reg_n_0_[6] ; wire \simp_stg3_final_r_reg_n_0_[7] ; wire \simp_stg3_final_r_reg_n_0_[8] ; wire \simp_stg3_final_r_reg_n_0_[9] ; wire sm_ns; wire [3:0]sm_r; wire \sm_r[0]_i_1_n_0 ; wire \sm_r[0]_i_2__0_n_0 ; wire \sm_r[0]_i_3_n_0 ; wire \sm_r[1]_i_1_n_0 ; wire \sm_r[1]_i_2_n_0 ; wire \sm_r[2]_i_1_n_0 ; wire \sm_r[2]_i_2_n_0 ; wire \sm_r[3]_i_10_n_0 ; wire \sm_r[3]_i_2_n_0 ; wire \sm_r[3]_i_3_n_0 ; wire \sm_r[3]_i_4_n_0 ; wire \sm_r[3]_i_6_n_0 ; wire \sm_r[3]_i_7_n_0 ; wire \sm_r[3]_i_8_n_0 ; wire \sm_r[3]_i_9_n_0 ; wire \sm_r_reg[0]_0 ; wire \sm_r_reg[0]_1 ; wire \sm_r_reg[3]_0 ; wire [5:0]stg2_final_r; wire \stg2_final_r[0]_i_1_n_0 ; wire \stg2_final_r[1]_i_1_n_0 ; wire \stg2_final_r[2]_i_1_n_0 ; wire \stg2_final_r[3]_i_1_n_0 ; wire \stg2_final_r[4]_i_1_n_0 ; wire \stg2_final_r[5]_i_1_n_0 ; wire [8:0]stg2_ns; wire stg2_ns0_carry__0_i_1_n_0; wire stg2_ns0_carry__0_i_2_n_0; wire stg2_ns0_carry__0_i_3_n_0; wire stg2_ns0_carry__0_i_4_n_0; wire stg2_ns0_carry__0_n_1; wire stg2_ns0_carry__0_n_2; wire stg2_ns0_carry__0_n_3; wire stg2_ns0_carry_i_1_n_0; wire stg2_ns0_carry_i_2_n_0; wire stg2_ns0_carry_i_3_n_0; wire stg2_ns0_carry_i_4_n_0; wire stg2_ns0_carry_n_0; wire stg2_ns0_carry_n_1; wire stg2_ns0_carry_n_2; wire stg2_ns0_carry_n_3; wire \stg2_r[8]_i_1_n_0 ; wire \stg2_r[8]_i_3_n_0 ; wire [0:0]\stg2_r_reg[0]_0 ; wire [1:1]stg2_target_ns; wire [2:0]\stg2_target_r_reg[8]_0 ; wire \stg2_target_r_reg_n_0_[0] ; wire \stg2_target_r_reg_n_0_[1] ; wire \stg2_target_r_reg_n_0_[2] ; wire \stg2_target_r_reg_n_0_[3] ; wire \stg2_target_r_reg_n_0_[4] ; wire \stg2_target_r_reg_n_0_[5] ; wire \stg2_target_r_reg_n_0_[6] ; wire \stg2_target_r_reg_n_0_[7] ; wire \stg3_init_val[3]_i_2_n_0 ; wire \stg3_init_val_reg[0] ; wire \stg3_init_val_reg[1] ; wire \stg3_init_val_reg[2] ; wire \stg3_init_val_reg[2]_0 ; wire [0:0]\stg3_init_val_reg[3] ; wire \stg3_init_val_reg[4] ; wire \stg3_init_val_reg[4]_0 ; wire \stg3_init_val_reg[5] ; wire [5:0]stg3_ns; wire \stg3_r[5]_i_10_n_0 ; wire \stg3_r[5]_i_11_n_0 ; wire \stg3_r[5]_i_12_n_0 ; wire \stg3_r[5]_i_1_n_0 ; wire \stg3_r[5]_i_4_n_0 ; wire \stg3_r[5]_i_5_n_0 ; wire \stg3_r[5]_i_6_n_0 ; wire \stg3_r[5]_i_7_n_0 ; wire \stg3_r[5]_i_9_n_0 ; wire \stg3_r_reg[0]_0 ; wire [1:0]two_r; wire \two_r[0]_i_1_n_0 ; wire \two_r[1]_i_1_n_0 ; wire \two_r[1]_i_2_n_0 ; wire \two_r_reg[1]_0 ; wire up_r; wire up_r_i_1_n_0; wire use_noise_window; wire [1:0]\wl_po_fine_cnt_reg[14] ; wire \wl_po_fine_cnt_reg[17] ; wire \wl_po_fine_cnt_reg[18] ; wire [7:0]\wl_po_fine_cnt_reg[23] ; wire \wl_po_fine_cnt_reg[3] ; wire wrlvl_final_mux; wire [3:2]NLW_p_0_in0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_p_0_in0_carry__0_O_UNCONNECTED; wire [3:1]NLW_p_0_in0_carry_i_11_CO_UNCONNECTED; wire [3:2]NLW_p_0_in0_carry_i_11_O_UNCONNECTED; wire [3:1]NLW_p_0_in0_carry_i_12_CO_UNCONNECTED; wire [3:2]NLW_p_0_in0_carry_i_12_O_UNCONNECTED; wire [0:0]NLW_p_0_in0_carry_i_8_O_UNCONNECTED; wire [3:3]NLW_stg2_ns0_carry__0_CO_UNCONNECTED; LUT3 #( .INIT(8'h04)) cmplx_samples_done_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(complex_ocal_num_samples_done_r), .I2(cmplx_samples_done_r_i_2_n_0), .O(p_58_in)); LUT5 #( .INIT(32'h0008AAAA)) cmplx_samples_done_r_i_2 (.I0(oclk_calib_resume_r_i_5_n_0), .I1(cmplx_samples_done_r_i_3_n_0), .I2(inc_po_r), .I3(dec_po_r), .I4(sm_r[0]), .O(cmplx_samples_done_r_i_2_n_0)); LUT3 #( .INIT(8'h08)) cmplx_samples_done_r_i_3 (.I0(po_done_r), .I1(\stg2_r_reg[0]_0 ), .I2(E), .O(cmplx_samples_done_r_i_3_n_0)); FDRE #( .INIT(1'b0)) cmplx_samples_done_r_reg (.C(CLK), .CE(1'b1), .D(p_58_in), .Q(complex_ocal_num_samples_done_r), .R(1'b0)); FDRE #( .INIT(1'b0)) dec_po_r_reg (.C(CLK), .CE(1'b1), .D(dec_po_ns), .Q(dec_po_r), .R(1'b0)); LUT2 #( .INIT(4'hE)) done_r_i_2__0 (.I0(ocd_edge_detect_rdy), .I1(lim2poc_rdy), .O(\run_ends_r_reg[1] )); LUT2 #( .INIT(4'hE)) edge_aligned_r_i_4 (.I0(\sm_r_reg[3]_0 ), .I1(\rise_trail_r_reg[5] ), .O(edge_aligned_r_reg)); (* SOFT_HLUTNM = "soft_lutpair418" *) LUT3 #( .INIT(8'hB8)) f2z_r_i_1 (.I0(scanning_right), .I1(f2z_ns5_out), .I2(f2z_r_reg_0), .O(f2z_r_reg)); LUT2 #( .INIT(4'h2)) i___15_i_1 (.I0(ninety_offsets[0]), .I1(ninety_offsets[1]), .O(use_noise_window)); (* SOFT_HLUTNM = "soft_lutpair413" *) LUT2 #( .INIT(4'hE)) i___7_i_2__0 (.I0(ocd_ktap_right), .I1(lim2poc_ktap_right), .O(\rise_trail_r_reg[5] )); FDRE #( .INIT(1'b0)) inc_po_r_reg (.C(CLK), .CE(1'b1), .D(inc_po_ns), .Q(inc_po_r), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFFFE)) \init_state_r[5]_i_55 (.I0(oclkdelay_center_calib_start_r_reg_0), .I1(wrlvl_final_mux), .I2(oclkdelay_int_ref_req_reg), .I3(prech_req_posedge_r_reg), .I4(oclkdelay_calib_done_r_reg_0), .O(\init_state_r_reg[0] )); FDRE #( .INIT(1'b0)) \ninety_offsets_final_r_reg[0] (.C(CLK), .CE(1'b1), .D(f2o_r_reg_0), .Q(ninety_offsets_final_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ninety_offsets_final_r_reg[1] (.C(CLK), .CE(1'b1), .D(f2o_r_reg), .Q(ninety_offsets_final_r[1]), .R(1'b0)); LUT5 #( .INIT(32'hE0FFEF00)) \ninety_offsets_r[0]_i_1 (.I0(ninety_offsets_final_r[1]), .I1(ninety_offsets_final_r[0]), .I2(sm_r[0]), .I3(ninety_offsets_ns), .I4(ninety_offsets[0]), .O(\ninety_offsets_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair406" *) LUT4 #( .INIT(16'h4F80)) \ninety_offsets_r[1]_i_1 (.I0(ninety_offsets[0]), .I1(sm_r[2]), .I2(ninety_offsets_ns), .I3(ninety_offsets[1]), .O(\ninety_offsets_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00000040)) \ninety_offsets_r[1]_i_2 (.I0(sm_r[2]), .I1(sm_r[0]), .I2(\stg2_r_reg[0]_0 ), .I3(sm_r[3]), .I4(rstdiv0_sync_r1_reg_rep__25), .I5(\ninety_offsets_r[1]_i_3_n_0 ), .O(ninety_offsets_ns)); LUT6 #( .INIT(64'h0000000001000000)) \ninety_offsets_r[1]_i_3 (.I0(sm_r[3]), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(\ninety_offsets_r[1]_i_4_n_0 ), .I3(oclk_center_write_resume_r_i_5_n_0), .I4(done_r_reg), .I5(E), .O(\ninety_offsets_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair401" *) LUT5 #( .INIT(32'hFFFFFFFB)) \ninety_offsets_r[1]_i_4 (.I0(\stg2_r_reg[0]_0 ), .I1(sm_r[2]), .I2(sm_r[0]), .I3(\sm_r_reg[3]_0 ), .I4(ocd_ktap_right), .O(\ninety_offsets_r[1]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \ninety_offsets_r_reg[0] (.C(CLK), .CE(1'b1), .D(\ninety_offsets_r[0]_i_1_n_0 ), .Q(ninety_offsets[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \ninety_offsets_r_reg[1] (.C(CLK), .CE(1'b1), .D(\ninety_offsets_r[1]_i_1_n_0 ), .Q(ninety_offsets[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair418" *) LUT3 #( .INIT(8'hB8)) o2f_r_i_1 (.I0(scanning_right), .I1(o2f_ns1_out), .I2(o2f_r_reg_0), .O(o2f_r_reg)); (* SOFT_HLUTNM = "soft_lutpair403" *) LUT5 #( .INIT(32'hFDFF0100)) ocd_edge_detect_rdy_r_i_1 (.I0(done_r_reg), .I1(E), .I2(sm_r[3]), .I3(\sm_r[3]_i_6_n_0 ), .I4(ocd_edge_detect_rdy), .O(ocd_edge_detect_rdy_r_i_1_n_0)); FDRE #( .INIT(1'b0)) ocd_edge_detect_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ocd_edge_detect_rdy_r_i_1_n_0), .Q(ocd_edge_detect_rdy), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'h00000000EEEEEEE0)) ocd_ktap_left_r_i_1 (.I0(ocd_ktap_left_r_i_2_n_0), .I1(\sm_r_reg[3]_0 ), .I2(sm_r[0]), .I3(\stg2_r_reg[0]_0 ), .I4(ocd_ktap_left_r_i_3_n_0), .I5(rstdiv0_sync_r1_reg_rep__20), .O(p_55_in)); LUT6 #( .INIT(64'h2000000000000000)) ocd_ktap_left_r_i_2 (.I0(scanning_right_r_reg_0), .I1(\stg2_r_reg[0]_0 ), .I2(rd_active_r2), .I3(samp_done), .I4(sm_r[0]), .I5(ocd_ktap_left_r_i_4_n_0), .O(ocd_ktap_left_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair408" *) LUT4 #( .INIT(16'hFFDF)) ocd_ktap_left_r_i_3 (.I0(sm_r[2]), .I1(sm_r[3]), .I2(done_r_reg), .I3(E), .O(ocd_ktap_left_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair406" *) LUT2 #( .INIT(4'h1)) ocd_ktap_left_r_i_4 (.I0(sm_r[3]), .I1(sm_r[2]), .O(ocd_ktap_left_r_i_4_n_0)); FDRE #( .INIT(1'b0)) ocd_ktap_left_r_reg (.C(CLK), .CE(1'b1), .D(p_55_in), .Q(\sm_r_reg[3]_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFFF0200FDFF0000)) ocd_ktap_right_r_i_1 (.I0(\sm_r[3]_i_6_n_0 ), .I1(sm_r[3]), .I2(E), .I3(done_r_reg), .I4(ocd_ktap_right), .I5(\sm_r_reg[3]_0 ), .O(ocd_ktap_right_r_i_1_n_0)); FDRE #( .INIT(1'b0)) ocd_ktap_right_r_reg (.C(CLK), .CE(1'b1), .D(ocd_ktap_right_r_i_1_n_0), .Q(ocd_ktap_right), .R(rstdiv0_sync_r1_reg_rep__9)); LUT4 #( .INIT(16'h0002)) oclk_calib_resume_r_i_2 (.I0(oclk_calib_resume_r_i_5_n_0), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(\sm_r_reg[0]_1 ), .I3(sm_r[0]), .O(samp_done_ns8_out)); LUT6 #( .INIT(64'h00000000000000A3)) oclk_calib_resume_r_i_5 (.I0(po_done_r), .I1(reset_scan), .I2(\stg2_r_reg[0]_0 ), .I3(sm_r[3]), .I4(sm_r[2]), .I5(E), .O(oclk_calib_resume_r_i_5_n_0)); LUT6 #( .INIT(64'hFFFF008000000000)) oclk_center_write_resume_r_i_1 (.I0(oclk_center_write_resume_r_i_2_n_0), .I1(\stg2_r_reg[0]_0 ), .I2(po_done_r), .I3(sm_r[3]), .I4(oclk_center_write_resume), .I5(oclk_center_write_resume_r_i_3_n_0), .O(p_63_in)); LUT4 #( .INIT(16'hAAAB)) oclk_center_write_resume_r_i_2 (.I0(sm_r[2]), .I1(dec_po_r), .I2(inc_po_r), .I3(E), .O(oclk_center_write_resume_r_i_2_n_0)); LUT5 #( .INIT(32'h55554044)) oclk_center_write_resume_r_i_3 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(oclk_center_write_resume), .I2(ocd_ktap_left_r_i_3_n_0), .I3(oclk_center_write_resume_r_i_4_n_0), .I4(sm_r[0]), .O(oclk_center_write_resume_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair404" *) LUT4 #( .INIT(16'h00F1)) oclk_center_write_resume_r_i_4 (.I0(ocd_ktap_right), .I1(oclk_center_write_resume_r_i_5_n_0), .I2(\sm_r_reg[3]_0 ), .I3(\stg2_r_reg[0]_0 ), .O(oclk_center_write_resume_r_i_4_n_0)); LUT6 #( .INIT(64'h0880888888880880)) oclk_center_write_resume_r_i_5 (.I0(edge_aligned_r_reg_0), .I1(ocd_edge_detect_rdy), .I2(ninety_offsets[0]), .I3(ninety_offsets_final_r[0]), .I4(ninety_offsets[1]), .I5(ninety_offsets_final_r[1]), .O(oclk_center_write_resume_r_i_5_n_0)); FDRE #( .INIT(1'b0)) oclk_center_write_resume_r_reg (.C(CLK), .CE(1'b1), .D(p_63_in), .Q(oclk_center_write_resume), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000002)) oclkdelay_center_calib_done_r_i_1 (.I0(oclkdelay_center_calib_done_r_i_2_n_0), .I1(resume_wait_r[3]), .I2(resume_wait_r[4]), .I3(resume_wait_r[5]), .I4(oclkdelay_center_calib_done_r_i_3_n_0), .I5(oclkdelay_center_calib_done_r_i_4_n_0), .O(oclkdelay_center_calib_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair402" *) LUT5 #( .INIT(32'h00000004)) oclkdelay_center_calib_done_r_i_2 (.I0(resume_wait_r[1]), .I1(resume_wait_r[0]), .I2(resume_wait_r[2]), .I3(poc_backup_r), .I4(resume_wait_r[10]), .O(oclkdelay_center_calib_done_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair405" *) LUT4 #( .INIT(16'hFFEF)) oclkdelay_center_calib_done_r_i_3 (.I0(sm_r[2]), .I1(\stg2_r_reg[0]_0 ), .I2(sm_r[3]), .I3(sm_r[0]), .O(oclkdelay_center_calib_done_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair398" *) LUT4 #( .INIT(16'hFFFE)) oclkdelay_center_calib_done_r_i_4 (.I0(resume_wait_r[8]), .I1(resume_wait_r[7]), .I2(resume_wait_r[9]), .I3(resume_wait_r[6]), .O(oclkdelay_center_calib_done_r_i_4_n_0)); FDRE #( .INIT(1'b0)) oclkdelay_center_calib_done_r_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_center_calib_done_r_i_1_n_0), .Q(ocal_last_byte_done_reg), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hEE44EFFFEE44E000)) oclkdelay_center_calib_start_r_i_1 (.I0(sm_r[0]), .I1(poc_backup_r), .I2(\sm_r[3]_i_3_n_0 ), .I3(scanning_right_r_reg_0), .I4(oclkdelay_center_calib_done_r_i_1_n_0), .I5(oclkdelay_center_calib_start_r_reg_0), .O(oclkdelay_center_calib_start_r_i_1_n_0)); FDRE #( .INIT(1'b0)) oclkdelay_center_calib_start_r_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_center_calib_start_r_i_1_n_0), .Q(oclkdelay_center_calib_start_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__9)); CARRY4 p_0_in0_carry (.CI(1'b0), .CO({p_0_in0_carry_n_0,p_0_in0_carry_n_1,p_0_in0_carry_n_2,p_0_in0_carry_n_3}), .CYINIT(1'b0), .DI({p_0_in0_carry_i_1_n_0,p_0_in0_carry_i_2_n_0,p_0_in0_carry_i_3_n_0,1'b0}), .O(O), .S({p_0_in0_carry_i_4_n_0,p_0_in0_carry_i_5_n_0,p_0_in0_carry_i_6_n_0,p_0_in0_carry_i_7_n_0})); CARRY4 p_0_in0_carry__0 (.CI(p_0_in0_carry_n_0), .CO({NLW_p_0_in0_carry__0_CO_UNCONNECTED[3:2],p_0_in0_carry__0_n_2,p_0_in0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,p_0_in0_carry__0_i_1_n_0,p_0_in0_carry__0_i_2_n_0}), .O({NLW_p_0_in0_carry__0_O_UNCONNECTED[3],p_0_in0_carry__0_n_5,p_0_in0_carry__0_n_6,p_0_in0_carry__0_n_7}), .S({1'b0,1'b1,p_0_in0_carry__0_i_3_n_0,p_0_in0_carry__0_i_4_n_0})); LUT2 #( .INIT(4'hB)) p_0_in0_carry__0_i_1 (.I0(p_0_in0_carry_i_9_n_0), .I1(p_0_in[5]), .O(p_0_in0_carry__0_i_1_n_0)); LUT4 #( .INIT(16'hF404)) p_0_in0_carry__0_i_2 (.I0(p_0_in[3]), .I1(p_0_in[4]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_11_n_7), .O(p_0_in0_carry__0_i_2_n_0)); LUT4 #( .INIT(16'h553F)) p_0_in0_carry__0_i_3 (.I0(p_0_in0_carry_i_11_n_6), .I1(p_0_in[4]), .I2(p_0_in[5]), .I3(p_0_in0_carry_i_9_n_0), .O(p_0_in0_carry__0_i_3_n_0)); LUT6 #( .INIT(64'hAAC355C3AA0F550F)) p_0_in0_carry__0_i_4 (.I0(p_0_in0_carry_i_11_n_7), .I1(p_0_in[3]), .I2(p_0_in[5]), .I3(p_0_in0_carry_i_9_n_0), .I4(p_0_in0_carry_i_11_n_6), .I5(p_0_in[4]), .O(p_0_in0_carry__0_i_4_n_0)); LUT4 #( .INIT(16'hF404)) p_0_in0_carry_i_1 (.I0(p_0_in[2]), .I1(p_0_in[3]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_10_n_4), .O(p_0_in0_carry_i_1_n_0)); CARRY4 p_0_in0_carry_i_10 (.CI(1'b0), .CO({p_0_in0_carry_i_10_n_0,p_0_in0_carry_i_10_n_1,p_0_in0_carry_i_10_n_2,p_0_in0_carry_i_10_n_3}), .CYINIT(1'b1), .DI({1'b1,1'b1,1'b0,1'b0}), .O({p_0_in0_carry_i_10_n_4,p_0_in0_carry_i_10_n_5,p_0_in0_carry_i_10_n_6,p_0_in[0]}), .S({p_0_in0_carry_i_17_n_0,p_0_in0_carry_i_18_n_0,p_0_in0_carry_i_19_n_0,p_0_in0_carry_i_20_n_0})); CARRY4 p_0_in0_carry_i_11 (.CI(p_0_in0_carry_i_10_n_0), .CO({NLW_p_0_in0_carry_i_11_CO_UNCONNECTED[3:1],p_0_in0_carry_i_11_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({NLW_p_0_in0_carry_i_11_O_UNCONNECTED[3:2],p_0_in0_carry_i_11_n_6,p_0_in0_carry_i_11_n_7}), .S({1'b0,1'b0,p_0_in0_carry_i_21_n_0,p_0_in0_carry_i_22_n_0})); CARRY4 p_0_in0_carry_i_12 (.CI(p_0_in0_carry_i_8_n_0), .CO({NLW_p_0_in0_carry_i_12_CO_UNCONNECTED[3:1],p_0_in0_carry_i_12_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,Q[4]}), .O({NLW_p_0_in0_carry_i_12_O_UNCONNECTED[3:2],p_0_in[5:4]}), .S({1'b0,1'b0,p_0_in0_carry_i_23_n_0,p_0_in0_carry_i_24_n_0})); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_13 (.I0(Q[3]), .O(p_0_in0_carry_i_13_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_14 (.I0(Q[2]), .O(p_0_in0_carry_i_14_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_15 (.I0(Q[1]), .O(p_0_in0_carry_i_15_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_16 (.I0(Q[0]), .O(p_0_in0_carry_i_16_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_17 (.I0(Q[3]), .O(p_0_in0_carry_i_17_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_18 (.I0(Q[2]), .O(p_0_in0_carry_i_18_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_19 (.I0(Q[1]), .O(p_0_in0_carry_i_19_n_0)); LUT4 #( .INIT(16'hF404)) p_0_in0_carry_i_2 (.I0(p_0_in[1]), .I1(p_0_in[2]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_10_n_5), .O(p_0_in0_carry_i_2_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_20 (.I0(Q[0]), .O(p_0_in0_carry_i_20_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_21 (.I0(Q[5]), .O(p_0_in0_carry_i_21_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_22 (.I0(Q[4]), .O(p_0_in0_carry_i_22_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_23 (.I0(Q[5]), .O(p_0_in0_carry_i_23_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_24 (.I0(Q[4]), .O(p_0_in0_carry_i_24_n_0)); LUT3 #( .INIT(8'hEF)) p_0_in0_carry_i_3 (.I0(p_0_in[1]), .I1(p_0_in0_carry_i_9_n_0), .I2(p_0_in[0]), .O(p_0_in0_carry_i_3_n_0)); LUT6 #( .INIT(64'hA5CCA533A500A5FF)) p_0_in0_carry_i_4 (.I0(p_0_in0_carry_i_10_n_4), .I1(p_0_in[2]), .I2(p_0_in0_carry_i_11_n_7), .I3(p_0_in0_carry_i_9_n_0), .I4(p_0_in[4]), .I5(p_0_in[3]), .O(p_0_in0_carry_i_4_n_0)); LUT6 #( .INIT(64'hAA55C3C3AA550F0F)) p_0_in0_carry_i_5 (.I0(p_0_in0_carry_i_10_n_5), .I1(p_0_in[1]), .I2(p_0_in[3]), .I3(p_0_in0_carry_i_10_n_4), .I4(p_0_in0_carry_i_9_n_0), .I5(p_0_in[2]), .O(p_0_in0_carry_i_5_n_0)); LUT5 #( .INIT(32'hF033F066)) p_0_in0_carry_i_6 (.I0(p_0_in[0]), .I1(p_0_in[2]), .I2(p_0_in0_carry_i_10_n_5), .I3(p_0_in0_carry_i_9_n_0), .I4(p_0_in[1]), .O(p_0_in0_carry_i_6_n_0)); LUT4 #( .INIT(16'hF606)) p_0_in0_carry_i_7 (.I0(p_0_in[0]), .I1(p_0_in[1]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_10_n_6), .O(p_0_in0_carry_i_7_n_0)); CARRY4 p_0_in0_carry_i_8 (.CI(1'b0), .CO({p_0_in0_carry_i_8_n_0,p_0_in0_carry_i_8_n_1,p_0_in0_carry_i_8_n_2,p_0_in0_carry_i_8_n_3}), .CYINIT(1'b1), .DI(Q[3:0]), .O({p_0_in[3:1],NLW_p_0_in0_carry_i_8_O_UNCONNECTED[0]}), .S({p_0_in0_carry_i_13_n_0,p_0_in0_carry_i_14_n_0,p_0_in0_carry_i_15_n_0,p_0_in0_carry_i_16_n_0})); LUT6 #( .INIT(64'h0155555555555555)) p_0_in0_carry_i_9 (.I0(Q[5]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[3]), .O(p_0_in0_carry_i_9_n_0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [0]), .Q(po_counter_read_val_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [1]), .Q(po_counter_read_val_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [2]), .Q(po_counter_read_val_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [3]), .Q(po_counter_read_val_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [4]), .Q(po_counter_read_val_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_counter_read_val_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [5]), .Q(po_counter_read_val_r[5]), .R(1'b0)); LUT3 #( .INIT(8'hDC)) po_done_r_i_1 (.I0(\two_r_reg[1]_0 ), .I1(po_done_ns), .I2(po_done_r), .O(po_done_r_i_1_n_0)); LUT6 #( .INIT(64'hAAAAAAAABAFFAAAA)) po_done_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(two_r[0]), .I2(two_r[1]), .I3(\two_r[1]_i_2_n_0 ), .I4(po_rdy), .I5(po_done_r), .O(po_done_ns)); FDRE #( .INIT(1'b0)) po_done_r_reg (.C(CLK), .CE(1'b1), .D(po_done_r_i_1_n_0), .Q(po_done_r), .R(1'b0)); LUT4 #( .INIT(16'hFFFE)) po_rdy_r_i_2 (.I0(po_stg23_incdec_r_reg_0), .I1(lim2stg3_inc), .I2(lim2stg3_dec), .I3(\two_r_reg[1]_0 ), .O(setup_po)); LUT6 #( .INIT(64'hFFFFFFFFEEEFEEEE)) po_rdy_r_i_4 (.I0(po_stg23_incdec_r_i_2_n_0), .I1(lim2stg2_dec), .I2(up_r), .I3(po_rdy_r_i_5_n_0), .I4(po_rdy_r_i_6_n_0), .I5(po_rdy_r_i_7_n_0), .O(po_stg23_incdec_r_reg_0)); LUT6 #( .INIT(64'h0000000000000001)) po_rdy_r_i_5 (.I0(A[2]), .I1(A[5]), .I2(A[4]), .I3(A[0]), .I4(A[3]), .I5(A[1]), .O(po_rdy_r_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair409" *) LUT4 #( .INIT(16'h0002)) po_rdy_r_i_6 (.I0(\stg2_r[8]_i_3_n_0 ), .I1(A[7]), .I2(A[8]), .I3(A[6]), .O(po_rdy_r_i_6_n_0)); LUT6 #( .INIT(64'h4545444544444444)) po_rdy_r_i_7 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(ocd_cntlr2stg2_dec_r), .I2(\sm_r[3]_i_9_n_0 ), .I3(stg2_final_r[5]), .I4(po_counter_read_val_r[5]), .I5(po_stg23_incdec_r_i_4_n_0), .O(po_rdy_r_i_7_n_0)); LUT6 #( .INIT(64'h5455555554555455)) po_stg23_incdec_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(po_stg23_incdec_r_i_2_n_0), .I2(lim2stg3_inc), .I3(\stg3_r[5]_i_6_n_0 ), .I4(setup_po), .I5(po_stg23_incdec), .O(po_stg23_incdec_r_reg)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) po_stg23_incdec_r_i_10 (.I0(A[4]), .I1(A[2]), .I2(A[5]), .I3(A[1]), .I4(A[0]), .I5(A[3]), .O(po_stg23_incdec_r_i_10_n_0)); LUT5 #( .INIT(32'hFFFFFF10)) po_stg23_incdec_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(po_stg23_incdec_r_i_3_n_0), .I2(po_stg23_incdec_r_i_4_n_0), .I3(po_stg23_incdec_r_i_5_n_0), .I4(lim2stg2_inc), .O(po_stg23_incdec_r_i_2_n_0)); LUT6 #( .INIT(64'hD5DD0000D5DDD5DD)) po_stg23_incdec_r_i_3 (.I0(po_stg23_incdec_r_i_6_n_0), .I1(po_stg23_incdec_r_i_7_n_0), .I2(po_stg23_incdec_r_i_8_n_0), .I3(po_stg23_incdec_r_i_9_n_0), .I4(po_counter_read_val_r[5]), .I5(stg2_final_r[5]), .O(po_stg23_incdec_r_i_3_n_0)); LUT4 #( .INIT(16'h0002)) po_stg23_incdec_r_i_4 (.I0(po_rdy), .I1(E), .I2(oclkdelay_center_calib_done_r_i_3_n_0), .I3(poc_backup_r), .O(po_stg23_incdec_r_i_4_n_0)); LUT6 #( .INIT(64'h0100000000000000)) po_stg23_incdec_r_i_5 (.I0(A[6]), .I1(A[8]), .I2(A[7]), .I3(\stg2_r[8]_i_3_n_0 ), .I4(po_stg23_incdec_r_i_10_n_0), .I5(up_r), .O(po_stg23_incdec_r_i_5_n_0)); LUT4 #( .INIT(16'hD0DD)) po_stg23_incdec_r_i_6 (.I0(po_counter_read_val_r[5]), .I1(stg2_final_r[5]), .I2(stg2_final_r[4]), .I3(po_counter_read_val_r[4]), .O(po_stg23_incdec_r_i_6_n_0)); LUT4 #( .INIT(16'hD0DD)) po_stg23_incdec_r_i_7 (.I0(stg2_final_r[3]), .I1(po_counter_read_val_r[3]), .I2(po_counter_read_val_r[4]), .I3(stg2_final_r[4]), .O(po_stg23_incdec_r_i_7_n_0)); LUT6 #( .INIT(64'hB0BBBBBB0000B0BB)) po_stg23_incdec_r_i_8 (.I0(po_counter_read_val_r[2]), .I1(stg2_final_r[2]), .I2(po_counter_read_val_r[0]), .I3(stg2_final_r[0]), .I4(stg2_final_r[1]), .I5(po_counter_read_val_r[1]), .O(po_stg23_incdec_r_i_8_n_0)); LUT4 #( .INIT(16'hD0DD)) po_stg23_incdec_r_i_9 (.I0(po_counter_read_val_r[2]), .I1(stg2_final_r[2]), .I2(stg2_final_r[3]), .I3(po_counter_read_val_r[3]), .O(po_stg23_incdec_r_i_9_n_0)); LUT6 #( .INIT(64'hFFFFEAFF0000EA00)) poc_backup_r_i_1__0 (.I0(poc_backup_r_i_2__0_n_0), .I1(poc_backup_r_reg_1), .I2(sm_r[2]), .I3(poc_backup_r_i_3_n_0), .I4(poc_backup_r_i_4_n_0), .I5(poc_backup_r), .O(poc_backup_r_i_1__0_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFF7F)) poc_backup_r_i_2 (.I0(\run_ends_r_reg[1]_0 ), .I1(\run_ends_r_reg[0] ), .I2(\run_ends_r_reg[1] ), .I3(\sm_r_reg[3]_0 ), .I4(\rise_trail_r_reg[5] ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(poc_backup_r_reg_0)); (* SOFT_HLUTNM = "soft_lutpair403" *) LUT2 #( .INIT(4'h8)) poc_backup_r_i_2__0 (.I0(sm_r[3]), .I1(E), .O(poc_backup_r_i_2__0_n_0)); LUT3 #( .INIT(8'h01)) poc_backup_r_i_3 (.I0(sm_r[0]), .I1(\stg2_r_reg[0]_0 ), .I2(rstdiv0_sync_r1_reg_rep__24), .O(poc_backup_r_i_3_n_0)); LUT6 #( .INIT(64'hFFFFFFF0F700F700)) poc_backup_r_i_4 (.I0(poc_backup_r), .I1(po_rdy), .I2(E), .I3(sm_r[3]), .I4(poc_backup_r_i_5_n_0), .I5(sm_r[2]), .O(poc_backup_r_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair413" *) LUT4 #( .INIT(16'hFFF7)) poc_backup_r_i_5 (.I0(\sm_r[3]_i_7_n_0 ), .I1(done_r_reg), .I2(ocd_ktap_right), .I3(\sm_r_reg[3]_0 ), .O(poc_backup_r_i_5_n_0)); FDRE #( .INIT(1'b0)) poc_backup_r_reg (.C(CLK), .CE(1'b1), .D(poc_backup_r_i_1__0_n_0), .Q(poc_backup_r), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF0000FF46)) \resume_wait_r[0]_i_1 (.I0(resume_wait_r[0]), .I1(E), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(\resume_wait_r[9]_i_5_n_0 ), .I4(\resume_wait_r[10]_i_3_n_0 ), .I5(\resume_wait_r[10]_i_4_n_0 ), .O(\resume_wait_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair400" *) LUT5 #( .INIT(32'h0000FF02)) \resume_wait_r[10]_i_1 (.I0(resume_wait_r[10]), .I1(\resume_wait_r[10]_i_2_n_0 ), .I2(\resume_wait_r[9]_i_5_n_0 ), .I3(\resume_wait_r[10]_i_3_n_0 ), .I4(\resume_wait_r[10]_i_4_n_0 ), .O(\resume_wait_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair398" *) LUT5 #( .INIT(32'h00000001)) \resume_wait_r[10]_i_2 (.I0(\resume_wait_r[9]_i_6_n_0 ), .I1(resume_wait_r[6]), .I2(resume_wait_r[9]), .I3(resume_wait_r[7]), .I4(resume_wait_r[8]), .O(\resume_wait_r[10]_i_2_n_0 )); LUT6 #( .INIT(64'h0000008000000000)) \resume_wait_r[10]_i_3 (.I0(oclk_center_write_resume_r_i_2_n_0), .I1(\stg2_r_reg[0]_0 ), .I2(po_done_r), .I3(sm_r[3]), .I4(oclk_center_write_resume), .I5(oclk_center_write_resume_r_i_3_n_0), .O(\resume_wait_r[10]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000022222220)) \resume_wait_r[10]_i_4 (.I0(ocd_ktap_left_r_i_2_n_0), .I1(\sm_r_reg[3]_0 ), .I2(sm_r[0]), .I3(\stg2_r_reg[0]_0 ), .I4(ocd_ktap_left_r_i_3_n_0), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\resume_wait_r[10]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000EECEDDCE)) \resume_wait_r[1]_i_1 (.I0(resume_wait_r[1]), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(E), .I4(resume_wait_r[0]), .I5(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000EECEDDCE)) \resume_wait_r[2]_i_1 (.I0(resume_wait_r[2]), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(E), .I4(\resume_wait_r[2]_i_2_n_0 ), .I5(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[2]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \resume_wait_r[2]_i_2 (.I0(resume_wait_r[0]), .I1(resume_wait_r[1]), .O(\resume_wait_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000DDCEEECE)) \resume_wait_r[3]_i_1 (.I0(resume_wait_r[3]), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(E), .I4(\resume_wait_r[7]_i_2_n_0 ), .I5(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[3]_i_1_n_0 )); LUT4 #( .INIT(16'h00D0)) \resume_wait_r[4]_i_1 (.I0(oclk_center_write_resume), .I1(oclk_center_write_resume_r_i_3_n_0), .I2(\resume_wait_r[4]_i_2_n_0 ), .I3(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFD0DFFFFF2020)) \resume_wait_r[4]_i_2 (.I0(\resume_wait_r[7]_i_2_n_0 ), .I1(resume_wait_r[3]), .I2(E), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(\resume_wait_r[9]_i_8_n_0 ), .I5(resume_wait_r[4]), .O(\resume_wait_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \resume_wait_r[5]_i_1 (.I0(resume_wait_r[5]), .I1(resume_wait_r[3]), .I2(resume_wait_r[4]), .I3(resume_wait_r[2]), .I4(resume_wait_r[1]), .I5(resume_wait_r[0]), .O(resume_wait_ns0[5])); (* SOFT_HLUTNM = "soft_lutpair397" *) LUT5 #( .INIT(32'hFEFF0100)) \resume_wait_r[6]_i_1 (.I0(resume_wait_r[3]), .I1(resume_wait_r[4]), .I2(resume_wait_r[5]), .I3(\resume_wait_r[7]_i_2_n_0 ), .I4(resume_wait_r[6]), .O(resume_wait_ns0[6])); LUT6 #( .INIT(64'hFFFFFFFB00000004)) \resume_wait_r[7]_i_1 (.I0(resume_wait_r[6]), .I1(\resume_wait_r[7]_i_2_n_0 ), .I2(resume_wait_r[5]), .I3(resume_wait_r[4]), .I4(resume_wait_r[3]), .I5(resume_wait_r[7]), .O(resume_wait_ns0[7])); (* SOFT_HLUTNM = "soft_lutpair402" *) LUT3 #( .INIT(8'h01)) \resume_wait_r[7]_i_2 (.I0(resume_wait_r[2]), .I1(resume_wait_r[1]), .I2(resume_wait_r[0]), .O(\resume_wait_r[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair412" *) LUT3 #( .INIT(8'hE1)) \resume_wait_r[8]_i_1 (.I0(resume_wait_r[7]), .I1(\resume_wait_r[9]_i_7_n_0 ), .I2(resume_wait_r[8]), .O(resume_wait_ns0[8])); LUT4 #( .INIT(16'hEEFE)) \resume_wait_r[9]_i_1 (.I0(\resume_wait_r[9]_i_4_n_0 ), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(E), .O(\resume_wait_r[9]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \resume_wait_r[9]_i_2 (.I0(resume_wait_r[10]), .I1(resume_wait_r[8]), .I2(resume_wait_r[7]), .I3(resume_wait_r[9]), .I4(resume_wait_r[6]), .I5(\resume_wait_r[9]_i_6_n_0 ), .O(E)); (* SOFT_HLUTNM = "soft_lutpair412" *) LUT4 #( .INIT(16'hAAA9)) \resume_wait_r[9]_i_3 (.I0(resume_wait_r[9]), .I1(\resume_wait_r[9]_i_7_n_0 ), .I2(resume_wait_r[7]), .I3(resume_wait_r[8]), .O(resume_wait_ns0[9])); (* SOFT_HLUTNM = "soft_lutpair400" *) LUT2 #( .INIT(4'hE)) \resume_wait_r[9]_i_4 (.I0(\resume_wait_r[10]_i_4_n_0 ), .I1(\resume_wait_r[10]_i_3_n_0 ), .O(\resume_wait_r[9]_i_4_n_0 )); LUT3 #( .INIT(8'hF2)) \resume_wait_r[9]_i_5 (.I0(oclk_center_write_resume), .I1(oclk_center_write_resume_r_i_3_n_0), .I2(\resume_wait_r[9]_i_8_n_0 ), .O(\resume_wait_r[9]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \resume_wait_r[9]_i_6 (.I0(resume_wait_r[3]), .I1(resume_wait_r[4]), .I2(resume_wait_r[5]), .I3(resume_wait_r[0]), .I4(resume_wait_r[1]), .I5(resume_wait_r[2]), .O(\resume_wait_r[9]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair397" *) LUT5 #( .INIT(32'hFFFFFFFB)) \resume_wait_r[9]_i_7 (.I0(resume_wait_r[6]), .I1(\resume_wait_r[7]_i_2_n_0 ), .I2(resume_wait_r[5]), .I3(resume_wait_r[4]), .I4(resume_wait_r[3]), .O(\resume_wait_r[9]_i_7_n_0 )); LUT2 #( .INIT(4'h2)) \resume_wait_r[9]_i_8 (.I0(poc_backup_r), .I1(\stg3_r[5]_i_6_n_0 ), .O(\resume_wait_r[9]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[0] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[0]_i_1_n_0 ), .Q(resume_wait_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[10] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[10]_i_1_n_0 ), .Q(resume_wait_r[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[1] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[1]_i_1_n_0 ), .Q(resume_wait_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[2] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[2]_i_1_n_0 ), .Q(resume_wait_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[3] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[3]_i_1_n_0 ), .Q(resume_wait_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[4] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[4]_i_1_n_0 ), .Q(resume_wait_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[5] (.C(CLK), .CE(E), .D(resume_wait_ns0[5]), .Q(resume_wait_r[5]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[6] (.C(CLK), .CE(E), .D(resume_wait_ns0[6]), .Q(resume_wait_r[6]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[7] (.C(CLK), .CE(E), .D(resume_wait_ns0[7]), .Q(resume_wait_r[7]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[8] (.C(CLK), .CE(E), .D(resume_wait_ns0[8]), .Q(resume_wait_r[8]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \resume_wait_r_reg[9] (.C(CLK), .CE(E), .D(resume_wait_ns0[9]), .Q(resume_wait_r[9]), .R(\resume_wait_r[9]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF7F0000004000)) scanning_right_r_i_1 (.I0(scan_right_r_reg), .I1(samp_done), .I2(rd_active_r2), .I3(sm_r[0]), .I4(scanning_right_r_i_3_n_0), .I5(scanning_right), .O(scanning_right_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair395" *) LUT4 #( .INIT(16'hFFFE)) scanning_right_r_i_3 (.I0(sm_r[2]), .I1(\stg2_r_reg[0]_0 ), .I2(sm_r[3]), .I3(rstdiv0_sync_r1_reg_rep__25), .O(scanning_right_r_i_3_n_0)); FDRE #( .INIT(1'b0)) scanning_right_r_reg (.C(CLK), .CE(1'b1), .D(scanning_right_r_i_1_n_0), .Q(scanning_right), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[0] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[10] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[4]), .Q(\simp_stg3_final_r_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[11] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[12] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[13] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[14] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[2]), .Q(\simp_stg3_final_r_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[15] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[15] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[16] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[4]), .Q(\stg3_init_val_reg[4]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[17] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[17] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[18] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[18] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[19] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[19] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[1] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[20] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[2]), .Q(\simp_stg3_final_r_reg_n_0_[20] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[21] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[21] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[22] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[4]), .Q(\simp_stg3_final_r_reg_n_0_[22] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[23] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[23] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[2] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[2]), .Q(\stg3_init_val_reg[2]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[3] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[4] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[4]), .Q(\simp_stg3_final_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[5] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[6] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[7] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[8] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[2]), .Q(\simp_stg3_final_r_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \simp_stg3_final_r_reg[9] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[9] ), .R(1'b0)); LUT3 #( .INIT(8'hB8)) \sm_r[0]_i_1 (.I0(E), .I1(sm_r[3]), .I2(\sm_r[0]_i_2__0_n_0 ), .O(\sm_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000AAFFF3FFFF)) \sm_r[0]_i_2__0 (.I0(scanning_right_r_reg_0), .I1(\sm_r[0]_i_3_n_0 ), .I2(\sm_r_reg[3]_0 ), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[2]), .I5(sm_r[0]), .O(\sm_r[0]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair404" *) LUT2 #( .INIT(4'h1)) \sm_r[0]_i_3 (.I0(ocd_ktap_right), .I1(oclk_center_write_resume_r_i_5_n_0), .O(\sm_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair408" *) LUT3 #( .INIT(8'hB8)) \sm_r[1]_i_1 (.I0(E), .I1(sm_r[3]), .I2(\sm_r[1]_i_2_n_0 ), .O(\sm_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000EEEF55550000)) \sm_r[1]_i_2 (.I0(\stg2_r_reg[0]_0 ), .I1(\sm_r_reg[3]_0 ), .I2(ocd_ktap_right), .I3(edge_aligned_r_reg_0), .I4(sm_r[0]), .I5(sm_r[2]), .O(\sm_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hBBBBB88888888888)) \sm_r[2]_i_1 (.I0(E), .I1(sm_r[3]), .I2(\stg2_r_reg[0]_0 ), .I3(sm_r[0]), .I4(sm_r[2]), .I5(\sm_r[2]_i_2_n_0 ), .O(\sm_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF0DFFFF)) \sm_r[2]_i_2 (.I0(\sm_r[3]_i_7_n_0 ), .I1(ocd_ktap_right), .I2(\sm_r_reg[3]_0 ), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[2]), .I5(sm_r[0]), .O(\sm_r[2]_i_2_n_0 )); LUT4 #( .INIT(16'hFEFF)) \sm_r[3]_i_1 (.I0(\sm_r[3]_i_3_n_0 ), .I1(\sm_r[3]_i_4_n_0 ), .I2(cmplx_samples_done_r_i_2_n_0), .I3(\sm_r_reg[0]_0 ), .O(sm_ns)); LUT6 #( .INIT(64'h00B0BBBB000000B0)) \sm_r[3]_i_10 (.I0(po_counter_read_val_r[2]), .I1(stg2_final_r[2]), .I2(po_counter_read_val_r[0]), .I3(stg2_final_r[0]), .I4(stg2_final_r[1]), .I5(po_counter_read_val_r[1]), .O(\sm_r[3]_i_10_n_0 )); LUT6 #( .INIT(64'h888B888888888888)) \sm_r[3]_i_2 (.I0(E), .I1(sm_r[3]), .I2(ocd_ktap_right), .I3(\sm_r_reg[3]_0 ), .I4(\sm_r[3]_i_6_n_0 ), .I5(\sm_r[3]_i_7_n_0 ), .O(\sm_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000010000000)) \sm_r[3]_i_3 (.I0(sm_r[3]), .I1(sm_r[2]), .I2(sm_r[0]), .I3(samp_done), .I4(rd_active_r2), .I5(\stg2_r_reg[0]_0 ), .O(\sm_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000F3F203F2)) \sm_r[3]_i_4 (.I0(done_r_reg), .I1(E), .I2(sm_r[0]), .I3(\stg2_r_reg[0]_0 ), .I4(po_done_r), .I5(\sm_r[3]_i_8_n_0 ), .O(\sm_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFF7FFFFFFFF)) \sm_r[3]_i_5 (.I0(\sm_r[3]_i_9_n_0 ), .I1(po_stg23_incdec_r_i_3_n_0), .I2(poc_backup_r), .I3(oclkdelay_center_calib_done_r_i_3_n_0), .I4(E), .I5(po_rdy), .O(\sm_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair401" *) LUT3 #( .INIT(8'h04)) \sm_r[3]_i_6 (.I0(sm_r[0]), .I1(sm_r[2]), .I2(\stg2_r_reg[0]_0 ), .O(\sm_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hA22A22222222A22A)) \sm_r[3]_i_7 (.I0(edge_aligned_r_reg_0), .I1(ocd_edge_detect_rdy), .I2(ninety_offsets[0]), .I3(ninety_offsets_final_r[0]), .I4(ninety_offsets[1]), .I5(ninety_offsets_final_r[1]), .O(\sm_r[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair405" *) LUT2 #( .INIT(4'hB)) \sm_r[3]_i_8 (.I0(sm_r[3]), .I1(sm_r[2]), .O(\sm_r[3]_i_8_n_0 )); LUT4 #( .INIT(16'h08AA)) \sm_r[3]_i_9 (.I0(po_stg23_incdec_r_i_6_n_0), .I1(po_stg23_incdec_r_i_9_n_0), .I2(\sm_r[3]_i_10_n_0 ), .I3(po_stg23_incdec_r_i_7_n_0), .O(\sm_r[3]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \sm_r_reg[0] (.C(CLK), .CE(sm_ns), .D(\sm_r[0]_i_1_n_0 ), .Q(sm_r[0]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \sm_r_reg[1] (.C(CLK), .CE(sm_ns), .D(\sm_r[1]_i_1_n_0 ), .Q(\stg2_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \sm_r_reg[2] (.C(CLK), .CE(sm_ns), .D(\sm_r[2]_i_1_n_0 ), .Q(sm_r[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE #( .INIT(1'b0)) \sm_r_reg[3] (.C(CLK), .CE(sm_ns), .D(\sm_r[3]_i_2_n_0 ), .Q(sm_r[3]), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair407" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[0]_i_1 (.I0(\stg2_target_r_reg_n_0_[0] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair410" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[1]_i_1 (.I0(\stg2_target_r_reg_n_0_[1] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair411" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[2]_i_1 (.I0(\stg2_target_r_reg_n_0_[2] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair410" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[3]_i_1 (.I0(\stg2_target_r_reg_n_0_[3] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair411" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[4]_i_1 (.I0(\stg2_target_r_reg_n_0_[4] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair407" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[5]_i_1 (.I0(\stg2_target_r_reg_n_0_[5] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \stg2_final_r_reg[0] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[0]_i_1_n_0 ), .Q(stg2_final_r[0]), .R(p_1_in)); FDRE #( .INIT(1'b0)) \stg2_final_r_reg[1] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[1]_i_1_n_0 ), .Q(stg2_final_r[1]), .R(p_1_in)); FDRE #( .INIT(1'b0)) \stg2_final_r_reg[2] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[2]_i_1_n_0 ), .Q(stg2_final_r[2]), .R(p_1_in)); FDRE #( .INIT(1'b0)) \stg2_final_r_reg[3] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[3]_i_1_n_0 ), .Q(stg2_final_r[3]), .R(p_1_in)); FDRE #( .INIT(1'b0)) \stg2_final_r_reg[4] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[4]_i_1_n_0 ), .Q(stg2_final_r[4]), .R(p_1_in)); FDRE #( .INIT(1'b0)) \stg2_final_r_reg[5] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[5]_i_1_n_0 ), .Q(stg2_final_r[5]), .R(p_1_in)); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 stg2_ns0_carry (.CI(1'b0), .CO({stg2_ns0_carry_n_0,stg2_ns0_carry_n_1,stg2_ns0_carry_n_2,stg2_ns0_carry_n_3}), .CYINIT(A[0]), .DI({A[3:1],up_r}), .O(out[4:1]), .S({stg2_ns0_carry_i_1_n_0,stg2_ns0_carry_i_2_n_0,stg2_ns0_carry_i_3_n_0,stg2_ns0_carry_i_4_n_0})); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 stg2_ns0_carry__0 (.CI(stg2_ns0_carry_n_0), .CO({NLW_stg2_ns0_carry__0_CO_UNCONNECTED[3],stg2_ns0_carry__0_n_1,stg2_ns0_carry__0_n_2,stg2_ns0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,A[6:4]}), .O(out[8:5]), .S({stg2_ns0_carry__0_i_1_n_0,stg2_ns0_carry__0_i_2_n_0,stg2_ns0_carry__0_i_3_n_0,stg2_ns0_carry__0_i_4_n_0})); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_1 (.I0(A[7]), .I1(A[8]), .O(stg2_ns0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_2 (.I0(A[6]), .I1(A[7]), .O(stg2_ns0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_3 (.I0(A[5]), .I1(A[6]), .O(stg2_ns0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_4 (.I0(A[4]), .I1(A[5]), .O(stg2_ns0_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_1 (.I0(A[3]), .I1(A[4]), .O(stg2_ns0_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_2 (.I0(A[2]), .I1(A[3]), .O(stg2_ns0_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_3 (.I0(A[1]), .I1(A[2]), .O(stg2_ns0_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_4 (.I0(A[1]), .I1(up_r), .O(stg2_ns0_carry_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair416" *) LUT3 #( .INIT(8'h35)) \stg2_r[0]_i_1 (.I0(\wl_po_fine_cnt_reg[18] ), .I1(A[0]), .I2(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[0])); (* SOFT_HLUTNM = "soft_lutpair417" *) LUT3 #( .INIT(8'hB8)) \stg2_r[1]_i_1 (.I0(out[1]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[14] [0]), .O(stg2_ns[1])); (* SOFT_HLUTNM = "soft_lutpair414" *) LUT3 #( .INIT(8'hB8)) \stg2_r[2]_i_1 (.I0(out[2]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[14] [1]), .O(stg2_ns[2])); (* SOFT_HLUTNM = "soft_lutpair416" *) LUT3 #( .INIT(8'h8B)) \stg2_r[3]_i_1 (.I0(out[3]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[3] ), .O(stg2_ns[3])); (* SOFT_HLUTNM = "soft_lutpair414" *) LUT3 #( .INIT(8'h8B)) \stg2_r[4]_i_1 (.I0(out[4]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\byte_r_reg[0] ), .O(stg2_ns[4])); (* SOFT_HLUTNM = "soft_lutpair417" *) LUT3 #( .INIT(8'h8B)) \stg2_r[5]_i_1 (.I0(out[5]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[17] ), .O(stg2_ns[5])); (* SOFT_HLUTNM = "soft_lutpair409" *) LUT2 #( .INIT(4'h8)) \stg2_r[6]_i_1 (.I0(out[6]), .I1(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[6])); (* SOFT_HLUTNM = "soft_lutpair419" *) LUT2 #( .INIT(4'h8)) \stg2_r[7]_i_1 (.I0(out[7]), .I1(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[7])); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) \stg2_r[8]_i_1 (.I0(\stg2_r[8]_i_3_n_0 ), .I1(sm_r[0]), .I2(\stg2_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(sm_r[3]), .I5(sm_r[2]), .O(\stg2_r[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair419" *) LUT2 #( .INIT(4'h8)) \stg2_r[8]_i_2 (.I0(out[8]), .I1(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[8])); LUT5 #( .INIT(32'h40400040)) \stg2_r[8]_i_3 (.I0(po_done_r), .I1(po_rdy), .I2(\two_r[1]_i_2_n_0 ), .I3(two_r[1]), .I4(two_r[0]), .O(\stg2_r[8]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \stg2_r_reg[0] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[0]), .Q(A[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[1] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[1]), .Q(A[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[2] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[2]), .Q(A[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[3] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[3]), .Q(A[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[4] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[4]), .Q(A[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[5] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[5]), .Q(A[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[6] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[6]), .Q(A[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[7] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[7]), .Q(A[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_r_reg[8] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[8]), .Q(A[8]), .R(1'b0)); LUT4 #( .INIT(16'h56A6)) \stg2_target_r[1]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(p_0_in[0]), .I2(p_0_in0_carry_i_9_n_0), .I3(\stg3_r_reg[0]_0 ), .O(stg2_target_ns)); LUT4 #( .INIT(16'h56A6)) \stg2_target_r[4]_i_7 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(p_0_in[0]), .I2(p_0_in0_carry_i_9_n_0), .I3(\stg3_r_reg[0]_0 ), .O(S)); LUT1 #( .INIT(2'h2)) \stg2_target_r[8]_i_3 (.I0(p_0_in0_carry__0_n_5), .O(\stg2_target_r_reg[8]_0 [2])); LUT1 #( .INIT(2'h2)) \stg2_target_r[8]_i_4 (.I0(p_0_in0_carry__0_n_6), .O(\stg2_target_r_reg[8]_0 [1])); LUT1 #( .INIT(2'h2)) \stg2_target_r[8]_i_5 (.I0(p_0_in0_carry__0_n_7), .O(\stg2_target_r_reg[8]_0 [0])); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[0] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [0]), .Q(\stg2_target_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[1] (.C(CLK), .CE(1'b1), .D(stg2_target_ns), .Q(\stg2_target_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [1]), .Q(\stg2_target_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[3] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [2]), .Q(\stg2_target_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[4] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [3]), .Q(\stg2_target_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[5] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [4]), .Q(\stg2_target_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[6] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [5]), .Q(\stg2_target_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[7] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [6]), .Q(\stg2_target_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg2_target_r_reg[8] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [7]), .Q(p_1_in), .R(1'b0)); LUT6 #( .INIT(64'h00550F33FF550F33)) \stg3_init_val[0]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[12] ), .I1(\simp_stg3_final_r_reg_n_0_[0] ), .I2(\simp_stg3_final_r_reg_n_0_[6] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1] ), .I5(\simp_stg3_final_r_reg_n_0_[18] ), .O(\stg3_init_val_reg[0] )); LUT6 #( .INIT(64'h5500330F55FF330F)) \stg3_init_val[1]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[19] ), .I1(\simp_stg3_final_r_reg_n_0_[7] ), .I2(\simp_stg3_final_r_reg_n_0_[1] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1] ), .I5(\simp_stg3_final_r_reg_n_0_[13] ), .O(\stg3_init_val_reg[1] )); LUT5 #( .INIT(32'hFAC00AC0)) \stg3_init_val[2]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[8] ), .I1(\simp_stg3_final_r_reg_n_0_[14] ), .I2(\byte_r_reg[1] ), .I3(\byte_r_reg[0]_0 ), .I4(\simp_stg3_final_r_reg_n_0_[20] ), .O(\stg3_init_val_reg[2] )); LUT6 #( .INIT(64'h7747FFFF7444FFFF)) \stg3_init_val[3]_i_1 (.I0(\stg3_init_val[3]_i_2_n_0 ), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1] ), .I3(\simp_stg3_final_r_reg_n_0_[15] ), .I4(oclkdelay_calib_done_r_reg), .I5(\simp_stg3_final_r_reg_n_0_[3] ), .O(\stg3_init_val_reg[3] )); LUT5 #( .INIT(32'h0407C4C7)) \stg3_init_val[3]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[9] ), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1] ), .I3(\simp_stg3_final_r_reg_n_0_[5] ), .I4(\simp_stg3_final_r_reg_n_0_[21] ), .O(\stg3_init_val[3]_i_2_n_0 )); LUT5 #( .INIT(32'hF0AC00AC)) \stg3_init_val[4]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[10] ), .I1(\simp_stg3_final_r_reg_n_0_[4] ), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1] ), .I4(\simp_stg3_final_r_reg_n_0_[22] ), .O(\stg3_init_val_reg[4] )); LUT6 #( .INIT(64'h0FDD00CC0FDDFFCC)) \stg3_init_val[5]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[17] ), .I1(\stg3_init_val[3]_i_2_n_0 ), .I2(\simp_stg3_final_r_reg_n_0_[23] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1] ), .I5(\simp_stg3_final_r_reg_n_0_[11] ), .O(\stg3_init_val_reg[5] )); LUT2 #( .INIT(4'h2)) \stg3_r[0]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(Q[0]), .O(stg3_ns[0])); (* SOFT_HLUTNM = "soft_lutpair399" *) LUT4 #( .INIT(16'hD714)) \stg3_r[1]_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(Q[1]), .I2(Q[0]), .I3(ocd2stg3_dec), .O(stg3_ns[1])); (* SOFT_HLUTNM = "soft_lutpair399" *) LUT5 #( .INIT(32'h8CC2BEEE)) \stg3_r[2]_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(ocd2stg3_dec), .O(stg3_ns[2])); LUT6 #( .INIT(64'h8CCCCCC2BEEEEEEE)) \stg3_r[3]_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(ocd2stg3_dec), .O(stg3_ns[3])); LUT6 #( .INIT(64'hFF6A0000FF6AFF6A)) \stg3_r[4]_i_1 (.I0(Q[4]), .I1(Q[3]), .I2(\stg3_r[5]_i_5_n_0 ), .I3(\stg3_r[5]_i_6_n_0 ), .I4(D[4]), .I5(ocd2stg3_dec), .O(stg3_ns[4])); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) \stg3_r[5]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(sm_r[0]), .I2(\stg2_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(sm_r[3]), .I5(sm_r[2]), .O(\stg3_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'hEEEE0EEEEEEEEEEE)) \stg3_r[5]_i_10 (.I0(scan_right_r_reg), .I1(samp_done_r_reg), .I2(po_done_r), .I3(\stg2_r_reg[0]_0 ), .I4(E), .I5(inc_po_r), .O(\stg3_r[5]_i_10_n_0 )); LUT5 #( .INIT(32'hFFFFFFEF)) \stg3_r[5]_i_11 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(sm_r[0]), .I2(sm_r[3]), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[2]), .O(\stg3_r[5]_i_11_n_0 )); LUT6 #( .INIT(64'h0080AAAA00800080)) \stg3_r[5]_i_12 (.I0(\stg3_r[5]_i_9_n_0 ), .I1(cmplx_samples_done_r_i_3_n_0), .I2(dec_po_r), .I3(inc_po_r), .I4(samp_done_r_reg), .I5(scan_right_r_reg), .O(\stg3_r[5]_i_12_n_0 )); LUT6 #( .INIT(64'h006AFFFF006A006A)) \stg3_r[5]_i_2 (.I0(Q[5]), .I1(\stg3_r[5]_i_4_n_0 ), .I2(\stg3_r[5]_i_5_n_0 ), .I3(\stg3_r[5]_i_6_n_0 ), .I4(\stg3_r[5]_i_7_n_0 ), .I5(ocd2stg3_dec), .O(stg3_ns[5])); LUT2 #( .INIT(4'hB)) \stg3_r[5]_i_3 (.I0(ocd2stg3_dec), .I1(\stg3_r[5]_i_6_n_0 ), .O(\two_r_reg[1]_0 )); LUT2 #( .INIT(4'h8)) \stg3_r[5]_i_4 (.I0(Q[4]), .I1(Q[3]), .O(\stg3_r[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair415" *) LUT3 #( .INIT(8'h80)) \stg3_r[5]_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\stg3_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'hDDDDDDDDD0DDDDDD)) \stg3_r[5]_i_6 (.I0(\stg3_r[5]_i_9_n_0 ), .I1(\stg3_r[5]_i_10_n_0 ), .I2(\stg3_r[5]_i_11_n_0 ), .I3(poc_backup_r), .I4(po_rdy), .I5(E), .O(\stg3_r[5]_i_6_n_0 )); LUT6 #( .INIT(64'h5555555555555556)) \stg3_r[5]_i_7 (.I0(Q[5]), .I1(Q[4]), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(Q[3]), .O(\stg3_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAEAA)) \stg3_r[5]_i_8 (.I0(\stg3_r[5]_i_12_n_0 ), .I1(sm_r[2]), .I2(sm_r[3]), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[0]), .I5(rstdiv0_sync_r1_reg_rep__25_0), .O(ocd2stg3_dec)); LUT4 #( .INIT(16'h0100)) \stg3_r[5]_i_9 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(sm_r[3]), .I2(sm_r[2]), .I3(sm_r[0]), .O(\stg3_r[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \stg3_r_reg[0] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_r_reg[1] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_r_reg[2] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_r_reg[3] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_r_reg[4] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \stg3_r_reg[5] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[5]), .Q(Q[5]), .R(1'b0)); LUT3 #( .INIT(8'h1C)) \two_r[0]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(\stg2_r[8]_i_3_n_0 ), .I2(two_r[0]), .O(\two_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h505050501C505050)) \two_r[1]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(two_r[0]), .I2(two_r[1]), .I3(\two_r[1]_i_2_n_0 ), .I4(po_rdy), .I5(po_done_r), .O(\two_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair395" *) LUT5 #( .INIT(32'hFCFFFFEF)) \two_r[1]_i_2 (.I0(sm_r[2]), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(sm_r[3]), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[0]), .O(\two_r[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \two_r_reg[0] (.C(CLK), .CE(1'b1), .D(\two_r[0]_i_1_n_0 ), .Q(two_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \two_r_reg[1] (.C(CLK), .CE(1'b1), .D(\two_r[1]_i_1_n_0 ), .Q(two_r[1]), .R(1'b0)); LUT3 #( .INIT(8'hF8)) up_r_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(up_r), .I2(ocd2stg3_dec), .O(up_r_i_1_n_0)); FDRE #( .INIT(1'b0)) up_r_reg (.C(CLK), .CE(1'b1), .D(up_r_i_1_n_0), .Q(up_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair420" *) LUT1 #( .INIT(2'h1)) \zero2fuzz_r[0]_i_1 (.I0(Q[0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair420" *) LUT2 #( .INIT(4'h9)) \zero2fuzz_r[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair415" *) LUT3 #( .INIT(8'hA9)) \zero2fuzz_r[2]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair396" *) LUT4 #( .INIT(16'hAAA9)) \zero2fuzz_r[3]_i_1 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair396" *) LUT5 #( .INIT(32'hAAAAAAA9)) \zero2fuzz_r[4]_i_1 (.I0(Q[4]), .I1(Q[3]), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .O(D[4])); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \zero2fuzz_r[5]_i_2 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[5]), .O(D[5])); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_ocd_samp" *) module ddr3_ifmig_7series_v4_0_ddr_phy_ocd_samp (oclk_calib_resume_level_reg, \samps_r_reg[9]_0 , samp_done, oclk_calib_resume_r_reg_0, prev_samp_valid_r_reg, D, \samps_r_reg[0]_0 , agg_samp_r, \stg3_r_reg[1] , \rd_victim_sel_r_reg[2]_0 , \rd_victim_sel_r_reg[1]_0 , \rd_victim_sel_r_reg[1]_1 , \oneeighty2fuzz_r_reg[5] , o2f_ns1_out, E, f2z_ns5_out, \init_state_r_reg[4] , \init_state_r_reg[5] , \prev_samp_r_reg[0] , \prev_samp_r_reg[1] , rstdiv0_sync_r1_reg_rep__10, CLK, rstdiv0_sync_r1_reg_rep__9, samp_done_ns8_out, phy_rddata_en_r1_reg, rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__24, \sm_r_reg[0]_0 , rd_active_r1, prev_samp_valid_r, rstdiv0_sync_r1_reg_rep__20, \data_bytes_r_reg[32] , \data_bytes_r_reg[24] , rd_active_r2, \sm_r_reg[1] , scanning_right_r_reg, phy_rddata_en_r1_reg_0, reset_scan, prev_samp_r, f2o_r_reg, scanning_right, \init_state_r_reg[0] , prbs_rdlvl_done_reg, prech_req_r_reg, ocd_prech_req_r_reg, \init_state_r_reg[4]_0 , prbs_rdlvl_done_reg_rep, \rd_victim_sel_r_reg[0]_0 ); output oclk_calib_resume_level_reg; output \samps_r_reg[9]_0 ; output samp_done; output oclk_calib_resume_r_reg_0; output prev_samp_valid_r_reg; output [1:0]D; output \samps_r_reg[0]_0 ; output [1:0]agg_samp_r; output \stg3_r_reg[1] ; output \rd_victim_sel_r_reg[2]_0 ; output \rd_victim_sel_r_reg[1]_0 ; output \rd_victim_sel_r_reg[1]_1 ; output [0:0]\oneeighty2fuzz_r_reg[5] ; output o2f_ns1_out; output [0:0]E; output f2z_ns5_out; output \init_state_r_reg[4] ; output \init_state_r_reg[5] ; output \prev_samp_r_reg[0] ; output \prev_samp_r_reg[1] ; input rstdiv0_sync_r1_reg_rep__10; input CLK; input rstdiv0_sync_r1_reg_rep__9; input samp_done_ns8_out; input phy_rddata_en_r1_reg; input rstdiv0_sync_r1_reg_rep__25; input rstdiv0_sync_r1_reg_rep__24; input [0:0]\sm_r_reg[0]_0 ; input rd_active_r1; input prev_samp_valid_r; input rstdiv0_sync_r1_reg_rep__20; input \data_bytes_r_reg[32] ; input \data_bytes_r_reg[24] ; input rd_active_r2; input [0:0]\sm_r_reg[1] ; input scanning_right_r_reg; input phy_rddata_en_r1_reg_0; input reset_scan; input [1:0]prev_samp_r; input f2o_r_reg; input scanning_right; input \init_state_r_reg[0] ; input prbs_rdlvl_done_reg; input prech_req_r_reg; input ocd_prech_req_r_reg; input [0:0]\init_state_r_reg[4]_0 ; input prbs_rdlvl_done_reg_rep; input [0:0]\rd_victim_sel_r_reg[0]_0 ; wire CLK; wire [1:0]D; wire [0:0]E; wire agg_samp_ns; wire [1:0]agg_samp_r; wire \agg_samp_r[0]_i_1_n_0 ; wire \agg_samp_r[1]_i_1_n_0 ; wire \data_bytes_r_reg[24] ; wire \data_bytes_r_reg[32] ; wire data_cnt_ns; wire [7:0]data_cnt_r; wire \data_cnt_r[2]_i_1_n_0 ; wire \data_cnt_r[3]_i_1_n_0 ; wire \data_cnt_r[4]_i_1_n_0 ; wire \data_cnt_r[6]_i_3_n_0 ; wire \data_cnt_r[7]_i_1_n_0 ; wire \data_cnt_r[7]_i_2_n_0 ; wire f2o_r_reg; wire f2z_ns5_out; wire \fuzz2zero_r[5]_i_3_n_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[4] ; wire [0:0]\init_state_r_reg[4]_0 ; wire \init_state_r_reg[5] ; wire o2f_ns1_out; wire ocd_prech_req_r_reg; wire oclk_calib_resume_level_reg; wire oclk_calib_resume_r_i_1_n_0; wire oclk_calib_resume_r_i_6_n_0; wire oclk_calib_resume_r_reg_0; wire [0:0]\oneeighty2fuzz_r_reg[5] ; wire oneeighty_ge_thresh; wire oneeighty_ge_thresh_carry__0_i_1_n_0; wire oneeighty_ge_thresh_carry_i_1_n_0; wire oneeighty_ge_thresh_carry_i_2_n_0; wire oneeighty_ge_thresh_carry_i_3_n_0; wire oneeighty_ge_thresh_carry_i_4_n_0; wire oneeighty_ge_thresh_carry_i_5_n_0; wire oneeighty_ge_thresh_carry_i_6_n_0; wire oneeighty_ge_thresh_carry_n_0; wire oneeighty_ge_thresh_carry_n_1; wire oneeighty_ge_thresh_carry_n_2; wire oneeighty_ge_thresh_carry_n_3; wire oneeighty_le_half_thresh; wire oneeighty_le_half_thresh_carry__0_i_1_n_0; wire oneeighty_le_half_thresh_carry_i_1_n_0; wire oneeighty_le_half_thresh_carry_i_2_n_0; wire oneeighty_le_half_thresh_carry_i_3_n_0; wire oneeighty_le_half_thresh_carry_i_4_n_0; wire oneeighty_le_half_thresh_carry_i_5_n_0; wire oneeighty_le_half_thresh_carry_i_6_n_0; wire oneeighty_le_half_thresh_carry_i_7_n_0; wire oneeighty_le_half_thresh_carry_n_0; wire oneeighty_le_half_thresh_carry_n_1; wire oneeighty_le_half_thresh_carry_n_2; wire oneeighty_le_half_thresh_carry_n_3; wire oneeighty_ns; wire \oneeighty_r[0]_i_1_n_0 ; wire \oneeighty_r[6]_i_2_n_0 ; wire \oneeighty_r[9]_i_3_n_0 ; wire [9:0]oneeighty_r_reg__0; wire [6:0]p_0_in; wire p_0_in11_in; wire [9:1]p_0_in__1; wire [9:1]p_0_in__2; wire phy_rddata_en_r1_reg; wire phy_rddata_en_r1_reg_0; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prech_req_r_reg; wire [1:0]prev_samp_r; wire \prev_samp_r_reg[0] ; wire \prev_samp_r_reg[1] ; wire prev_samp_valid_r; wire prev_samp_valid_r_reg; wire rd_active_r1; wire rd_active_r2; wire \rd_victim_sel_r[0]_i_1_n_0 ; wire \rd_victim_sel_r[1]_i_1_n_0 ; wire \rd_victim_sel_r[2]_i_1_n_0 ; wire [0:0]\rd_victim_sel_r_reg[0]_0 ; wire \rd_victim_sel_r_reg[1]_0 ; wire \rd_victim_sel_r_reg[1]_1 ; wire \rd_victim_sel_r_reg[2]_0 ; wire reset_scan; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__9; wire samp_done; wire samp_done_ns8_out; wire samp_done_ns9_in; wire samp_done_r_i_1_n_0; wire \samp_result_r_reg_n_0_[0] ; wire samps_ns; wire [9:0]samps_r; wire [8:0]samps_r0; wire \samps_r[1]_i_1_n_0 ; wire \samps_r[4]_i_1_n_0 ; wire \samps_r[5]_i_1_n_0 ; wire \samps_r[7]_i_1_n_0 ; wire \samps_r[8]_i_3_n_0 ; wire \samps_r[8]_i_4_n_0 ; wire \samps_r[8]_i_5_n_0 ; wire \samps_r[9]_i_1_n_0 ; wire \samps_r[9]_i_2_n_0 ; wire \samps_r[9]_i_3_n_0 ; wire \samps_r_reg[0]_0 ; wire \samps_r_reg[9]_0 ; wire scanning_right; wire scanning_right_r_reg; wire \sm_r[0]_i_1__0_n_0 ; wire [0:0]\sm_r_reg[0]_0 ; wire [0:0]\sm_r_reg[1] ; wire \stg3_r_reg[1] ; wire \u_ocd_edge/samp_valid ; wire zero_ge_thresh; wire zero_ge_thresh_carry__0_i_1_n_0; wire zero_ge_thresh_carry_i_1_n_0; wire zero_ge_thresh_carry_i_2_n_0; wire zero_ge_thresh_carry_i_3_n_0; wire zero_ge_thresh_carry_i_4_n_0; wire zero_ge_thresh_carry_i_5_n_0; wire zero_ge_thresh_carry_i_6_n_0; wire zero_ge_thresh_carry_n_0; wire zero_ge_thresh_carry_n_1; wire zero_ge_thresh_carry_n_2; wire zero_ge_thresh_carry_n_3; wire zero_le_half_thresh; wire zero_le_half_thresh_carry__0_i_1_n_0; wire zero_le_half_thresh_carry_i_1_n_0; wire zero_le_half_thresh_carry_i_2_n_0; wire zero_le_half_thresh_carry_i_3_n_0; wire zero_le_half_thresh_carry_i_4_n_0; wire zero_le_half_thresh_carry_i_5_n_0; wire zero_le_half_thresh_carry_i_6_n_0; wire zero_le_half_thresh_carry_i_7_n_0; wire zero_le_half_thresh_carry_n_0; wire zero_le_half_thresh_carry_n_1; wire zero_le_half_thresh_carry_n_2; wire zero_le_half_thresh_carry_n_3; wire \zero_r[0]_i_1_n_0 ; wire \zero_r[6]_i_2_n_0 ; wire \zero_r[9]_i_8_n_0 ; wire [9:0]zero_r_reg__0; wire [3:0]NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED; wire [3:0]NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED; wire [3:0]NLW_zero_ge_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_zero_ge_thresh_carry__0_O_UNCONNECTED; wire [3:0]NLW_zero_le_half_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED; LUT6 #( .INIT(64'hFFFFFFF1F1F1FFF1)) \agg_samp_r[0]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(\samps_r_reg[0]_0 ), .I3(agg_samp_r[0]), .I4(agg_samp_ns), .I5(\data_bytes_r_reg[24] ), .O(\agg_samp_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFF1F1F1FFF1)) \agg_samp_r[1]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(\samps_r_reg[0]_0 ), .I3(agg_samp_r[1]), .I4(agg_samp_ns), .I5(\data_bytes_r_reg[32] ), .O(\agg_samp_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h4444444444444440)) \agg_samp_r[1]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(phy_rddata_en_r1_reg), .I2(\rd_victim_sel_r_reg[2]_0 ), .I3(\rd_victim_sel_r_reg[1]_0 ), .I4(\rd_victim_sel_r_reg[1]_1 ), .I5(oclk_calib_resume_r_reg_0), .O(agg_samp_ns)); FDRE #( .INIT(1'b0)) \agg_samp_r_reg[0] (.C(CLK), .CE(1'b1), .D(\agg_samp_r[0]_i_1_n_0 ), .Q(agg_samp_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \agg_samp_r_reg[1] (.C(CLK), .CE(1'b1), .D(\agg_samp_r[1]_i_1_n_0 ), .Q(agg_samp_r[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair432" *) LUT3 #( .INIT(8'h7F)) \data_cnt_r[0]_i_1 (.I0(data_cnt_r[0]), .I1(\samps_r_reg[9]_0 ), .I2(oclk_calib_resume_r_reg_0), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair432" *) LUT3 #( .INIT(8'h82)) \data_cnt_r[1]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(data_cnt_r[1]), .I2(data_cnt_r[0]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair428" *) LUT3 #( .INIT(8'hA9)) \data_cnt_r[2]_i_1 (.I0(data_cnt_r[2]), .I1(data_cnt_r[1]), .I2(data_cnt_r[0]), .O(\data_cnt_r[2]_i_1_n_0 )); LUT4 #( .INIT(16'hAAA9)) \data_cnt_r[3]_i_1 (.I0(data_cnt_r[3]), .I1(data_cnt_r[2]), .I2(data_cnt_r[1]), .I3(data_cnt_r[0]), .O(\data_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair425" *) LUT5 #( .INIT(32'hAAAAAAA9)) \data_cnt_r[4]_i_1 (.I0(data_cnt_r[4]), .I1(data_cnt_r[3]), .I2(data_cnt_r[0]), .I3(data_cnt_r[1]), .I4(data_cnt_r[2]), .O(\data_cnt_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair429" *) LUT3 #( .INIT(8'h28)) \data_cnt_r[5]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(\data_cnt_r[6]_i_3_n_0 ), .I2(data_cnt_r[5]), .O(p_0_in[5])); LUT3 #( .INIT(8'h31)) \data_cnt_r[6]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(phy_rddata_en_r1_reg), .O(data_cnt_ns)); (* SOFT_HLUTNM = "soft_lutpair429" *) LUT4 #( .INIT(16'h8A20)) \data_cnt_r[6]_i_2 (.I0(\samps_r_reg[9]_0 ), .I1(data_cnt_r[5]), .I2(\data_cnt_r[6]_i_3_n_0 ), .I3(data_cnt_r[6]), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair425" *) LUT5 #( .INIT(32'h00000001)) \data_cnt_r[6]_i_3 (.I0(data_cnt_r[3]), .I1(data_cnt_r[0]), .I2(data_cnt_r[1]), .I3(data_cnt_r[2]), .I4(data_cnt_r[4]), .O(\data_cnt_r[6]_i_3_n_0 )); LUT4 #( .INIT(16'h0323)) \data_cnt_r[7]_i_1 (.I0(phy_rddata_en_r1_reg), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(\samps_r_reg[9]_0 ), .I3(oclk_calib_resume_r_reg_0), .O(\data_cnt_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'hAAA6)) \data_cnt_r[7]_i_2 (.I0(data_cnt_r[7]), .I1(\data_cnt_r[6]_i_3_n_0 ), .I2(data_cnt_r[5]), .I3(data_cnt_r[6]), .O(\data_cnt_r[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[0] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[0]), .Q(data_cnt_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[1] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[1]), .Q(data_cnt_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[2] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[2]_i_1_n_0 ), .Q(data_cnt_r[2]), .R(\data_cnt_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[3] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[3]_i_1_n_0 ), .Q(data_cnt_r[3]), .R(\data_cnt_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[4] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[4]_i_1_n_0 ), .Q(data_cnt_r[4]), .R(\data_cnt_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[5] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[5]), .Q(data_cnt_r[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[6] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[6]), .Q(data_cnt_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \data_cnt_r_reg[7] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[7]_i_2_n_0 ), .Q(data_cnt_r[7]), .R(\data_cnt_r[7]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \fuzz2zero_r[5]_i_1 (.I0(f2z_ns5_out), .I1(reset_scan), .O(E)); LUT6 #( .INIT(64'h0080808000000000)) \fuzz2zero_r[5]_i_2 (.I0(\fuzz2zero_r[5]_i_3_n_0 ), .I1(\u_ocd_edge/samp_valid ), .I2(prev_samp_valid_r), .I3(f2o_r_reg), .I4(prev_samp_r[1]), .I5(D[0]), .O(f2z_ns5_out)); LUT3 #( .INIT(8'h04)) \fuzz2zero_r[5]_i_3 (.I0(D[1]), .I1(scanning_right), .I2(prev_samp_r[0]), .O(\fuzz2zero_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h1111111111111110)) \init_state_r[4]_i_36 (.I0(\init_state_r_reg[0] ), .I1(oclk_calib_resume_level_reg), .I2(prbs_rdlvl_done_reg), .I3(prech_req_r_reg), .I4(ocd_prech_req_r_reg), .I5(\init_state_r_reg[4]_0 ), .O(\init_state_r_reg[4] )); LUT4 #( .INIT(16'hFFFE)) \init_state_r[5]_i_47 (.I0(oclk_calib_resume_level_reg), .I1(ocd_prech_req_r_reg), .I2(prech_req_r_reg), .I3(prbs_rdlvl_done_reg_rep), .O(\init_state_r_reg[5] )); LUT5 #( .INIT(32'hAAAABAAA)) oclk_calib_resume_r_i_1 (.I0(samp_done_ns8_out), .I1(oclk_calib_resume_r_reg_0), .I2(phy_rddata_en_r1_reg), .I3(\samps_r_reg[9]_0 ), .I4(samp_done_ns9_in), .O(oclk_calib_resume_r_i_1_n_0)); LUT5 #( .INIT(32'hFFFFFEFF)) oclk_calib_resume_r_i_3 (.I0(data_cnt_r[7]), .I1(data_cnt_r[4]), .I2(data_cnt_r[3]), .I3(data_cnt_r[0]), .I4(oclk_calib_resume_r_i_6_n_0), .O(oclk_calib_resume_r_reg_0)); LUT6 #( .INIT(64'hAAAAAAABAAAAAAAA)) oclk_calib_resume_r_i_4 (.I0(samp_done), .I1(oclk_calib_resume_r_reg_0), .I2(\rd_victim_sel_r_reg[1]_1 ), .I3(\rd_victim_sel_r_reg[1]_0 ), .I4(\rd_victim_sel_r_reg[2]_0 ), .I5(\samps_r[8]_i_3_n_0 ), .O(samp_done_ns9_in)); (* SOFT_HLUTNM = "soft_lutpair428" *) LUT4 #( .INIT(16'hFFFE)) oclk_calib_resume_r_i_6 (.I0(data_cnt_r[6]), .I1(data_cnt_r[5]), .I2(data_cnt_r[1]), .I3(data_cnt_r[2]), .O(oclk_calib_resume_r_i_6_n_0)); FDRE #( .INIT(1'b0)) oclk_calib_resume_r_reg (.C(CLK), .CE(1'b1), .D(oclk_calib_resume_r_i_1_n_0), .Q(oclk_calib_resume_level_reg), .R(rstdiv0_sync_r1_reg_rep__10)); LUT2 #( .INIT(4'h2)) \oneeighty2fuzz_r[5]_i_1 (.I0(o2f_ns1_out), .I1(reset_scan), .O(\oneeighty2fuzz_r_reg[5] )); LUT6 #( .INIT(64'h8000800000008000)) \oneeighty2fuzz_r[5]_i_2 (.I0(\fuzz2zero_r[5]_i_3_n_0 ), .I1(\u_ocd_edge/samp_valid ), .I2(prev_samp_valid_r), .I3(prev_samp_r[1]), .I4(D[0]), .I5(f2o_r_reg), .O(o2f_ns1_out)); CARRY4 oneeighty_ge_thresh_carry (.CI(1'b0), .CO({oneeighty_ge_thresh_carry_n_0,oneeighty_ge_thresh_carry_n_1,oneeighty_ge_thresh_carry_n_2,oneeighty_ge_thresh_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,oneeighty_ge_thresh_carry_i_1_n_0,oneeighty_r_reg__0[3],oneeighty_ge_thresh_carry_i_2_n_0}), .O(NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED[3:0]), .S({oneeighty_ge_thresh_carry_i_3_n_0,oneeighty_ge_thresh_carry_i_4_n_0,oneeighty_ge_thresh_carry_i_5_n_0,oneeighty_ge_thresh_carry_i_6_n_0})); CARRY4 oneeighty_ge_thresh_carry__0 (.CI(oneeighty_ge_thresh_carry_n_0), .CO({NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_ge_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,oneeighty_r_reg__0[9]}), .O(NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,oneeighty_ge_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry__0_i_1 (.I0(oneeighty_r_reg__0[8]), .I1(oneeighty_r_reg__0[9]), .O(oneeighty_ge_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_ge_thresh_carry_i_1 (.I0(oneeighty_r_reg__0[4]), .I1(oneeighty_r_reg__0[5]), .O(oneeighty_ge_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_ge_thresh_carry_i_2 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(oneeighty_ge_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_ge_thresh_carry_i_3 (.I0(oneeighty_r_reg__0[7]), .I1(oneeighty_r_reg__0[6]), .O(oneeighty_ge_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry_i_4 (.I0(oneeighty_r_reg__0[5]), .I1(oneeighty_r_reg__0[4]), .O(oneeighty_ge_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry_i_5 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[3]), .O(oneeighty_ge_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry_i_6 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(oneeighty_ge_thresh_carry_i_6_n_0)); CARRY4 oneeighty_le_half_thresh_carry (.CI(1'b0), .CO({oneeighty_le_half_thresh_carry_n_0,oneeighty_le_half_thresh_carry_n_1,oneeighty_le_half_thresh_carry_n_2,oneeighty_le_half_thresh_carry_n_3}), .CYINIT(1'b1), .DI({oneeighty_le_half_thresh_carry_i_1_n_0,oneeighty_le_half_thresh_carry_i_2_n_0,1'b0,oneeighty_le_half_thresh_carry_i_3_n_0}), .O(NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED[3:0]), .S({oneeighty_le_half_thresh_carry_i_4_n_0,oneeighty_le_half_thresh_carry_i_5_n_0,oneeighty_le_half_thresh_carry_i_6_n_0,oneeighty_le_half_thresh_carry_i_7_n_0})); CARRY4 oneeighty_le_half_thresh_carry__0 (.CI(oneeighty_le_half_thresh_carry_n_0), .CO({NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_le_half_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,oneeighty_le_half_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h1)) oneeighty_le_half_thresh_carry__0_i_1 (.I0(oneeighty_r_reg__0[8]), .I1(oneeighty_r_reg__0[9]), .O(oneeighty_le_half_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h7)) oneeighty_le_half_thresh_carry_i_1 (.I0(oneeighty_r_reg__0[6]), .I1(oneeighty_r_reg__0[7]), .O(oneeighty_le_half_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h7)) oneeighty_le_half_thresh_carry_i_2 (.I0(oneeighty_r_reg__0[5]), .I1(oneeighty_r_reg__0[4]), .O(oneeighty_le_half_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h7)) oneeighty_le_half_thresh_carry_i_3 (.I0(oneeighty_r_reg__0[0]), .I1(oneeighty_r_reg__0[1]), .O(oneeighty_le_half_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_le_half_thresh_carry_i_4 (.I0(oneeighty_r_reg__0[7]), .I1(oneeighty_r_reg__0[6]), .O(oneeighty_le_half_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_le_half_thresh_carry_i_5 (.I0(oneeighty_r_reg__0[4]), .I1(oneeighty_r_reg__0[5]), .O(oneeighty_le_half_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h1)) oneeighty_le_half_thresh_carry_i_6 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[3]), .O(oneeighty_le_half_thresh_carry_i_6_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_le_half_thresh_carry_i_7 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(oneeighty_le_half_thresh_carry_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair437" *) LUT1 #( .INIT(2'h1)) \oneeighty_r[0]_i_1 (.I0(oneeighty_r_reg__0[0]), .O(\oneeighty_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair437" *) LUT2 #( .INIT(4'h6)) \oneeighty_r[1]_i_1 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair434" *) LUT3 #( .INIT(8'h6A)) \oneeighty_r[2]_i_1 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[0]), .I2(oneeighty_r_reg__0[1]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair422" *) LUT4 #( .INIT(16'h6AAA)) \oneeighty_r[3]_i_1 (.I0(oneeighty_r_reg__0[3]), .I1(oneeighty_r_reg__0[1]), .I2(oneeighty_r_reg__0[0]), .I3(oneeighty_r_reg__0[2]), .O(p_0_in__2[3])); (* SOFT_HLUTNM = "soft_lutpair422" *) LUT5 #( .INIT(32'h6AAAAAAA)) \oneeighty_r[4]_i_1 (.I0(oneeighty_r_reg__0[4]), .I1(oneeighty_r_reg__0[2]), .I2(oneeighty_r_reg__0[0]), .I3(oneeighty_r_reg__0[1]), .I4(oneeighty_r_reg__0[3]), .O(p_0_in__2[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \oneeighty_r[5]_i_1 (.I0(oneeighty_r_reg__0[5]), .I1(oneeighty_r_reg__0[3]), .I2(oneeighty_r_reg__0[1]), .I3(oneeighty_r_reg__0[0]), .I4(oneeighty_r_reg__0[2]), .I5(oneeighty_r_reg__0[4]), .O(p_0_in__2[5])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \oneeighty_r[6]_i_1 (.I0(oneeighty_r_reg__0[6]), .I1(oneeighty_r_reg__0[4]), .I2(oneeighty_r_reg__0[5]), .I3(oneeighty_r_reg__0[3]), .I4(\oneeighty_r[6]_i_2_n_0 ), .I5(oneeighty_r_reg__0[2]), .O(p_0_in__2[6])); (* SOFT_HLUTNM = "soft_lutpair434" *) LUT2 #( .INIT(4'h8)) \oneeighty_r[6]_i_2 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(\oneeighty_r[6]_i_2_n_0 )); LUT3 #( .INIT(8'h6A)) \oneeighty_r[7]_i_1 (.I0(oneeighty_r_reg__0[7]), .I1(\oneeighty_r[9]_i_3_n_0 ), .I2(oneeighty_r_reg__0[6]), .O(p_0_in__2[7])); (* SOFT_HLUTNM = "soft_lutpair427" *) LUT4 #( .INIT(16'h6AAA)) \oneeighty_r[8]_i_1 (.I0(oneeighty_r_reg__0[8]), .I1(oneeighty_r_reg__0[7]), .I2(oneeighty_r_reg__0[6]), .I3(\oneeighty_r[9]_i_3_n_0 ), .O(p_0_in__2[8])); LUT2 #( .INIT(4'h8)) \oneeighty_r[9]_i_1 (.I0(\samps_r_reg[0]_0 ), .I1(\data_bytes_r_reg[32] ), .O(oneeighty_ns)); (* SOFT_HLUTNM = "soft_lutpair427" *) LUT5 #( .INIT(32'h6AAAAAAA)) \oneeighty_r[9]_i_2 (.I0(oneeighty_r_reg__0[9]), .I1(\oneeighty_r[9]_i_3_n_0 ), .I2(oneeighty_r_reg__0[6]), .I3(oneeighty_r_reg__0[7]), .I4(oneeighty_r_reg__0[8]), .O(p_0_in__2[9])); LUT6 #( .INIT(64'h8000000000000000)) \oneeighty_r[9]_i_3 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[0]), .I2(oneeighty_r_reg__0[1]), .I3(oneeighty_r_reg__0[3]), .I4(oneeighty_r_reg__0[5]), .I5(oneeighty_r_reg__0[4]), .O(\oneeighty_r[9]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[0] (.C(CLK), .CE(oneeighty_ns), .D(\oneeighty_r[0]_i_1_n_0 ), .Q(oneeighty_r_reg__0[0]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[1] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[1]), .Q(oneeighty_r_reg__0[1]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[2] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[2]), .Q(oneeighty_r_reg__0[2]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[3] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[3]), .Q(oneeighty_r_reg__0[3]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[4] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[4]), .Q(oneeighty_r_reg__0[4]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[5] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[5]), .Q(oneeighty_r_reg__0[5]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[6] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[6]), .Q(oneeighty_r_reg__0[6]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[7] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[7]), .Q(oneeighty_r_reg__0[7]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[8] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[8]), .Q(oneeighty_r_reg__0[8]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \oneeighty_r_reg[9] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[9]), .Q(oneeighty_r_reg__0[9]), .R(\sm_r_reg[0]_0 )); LUT6 #( .INIT(64'h003AFFFF003A0000)) \prev_samp_r[0]_i_1 (.I0(zero_ge_thresh), .I1(zero_le_half_thresh), .I2(\samp_result_r_reg_n_0_[0] ), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(\u_ocd_edge/samp_valid ), .I5(prev_samp_r[0]), .O(\prev_samp_r_reg[0] )); LUT6 #( .INIT(64'h0454FFFF04540000)) \prev_samp_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(oneeighty_ge_thresh), .I2(p_0_in11_in), .I3(oneeighty_le_half_thresh), .I4(\u_ocd_edge/samp_valid ), .I5(prev_samp_r[1]), .O(\prev_samp_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair431" *) LUT2 #( .INIT(4'h8)) \prev_samp_r[1]_i_2 (.I0(samp_done), .I1(rd_active_r1), .O(\u_ocd_edge/samp_valid )); (* SOFT_HLUTNM = "soft_lutpair431" *) LUT3 #( .INIT(8'hF8)) prev_samp_valid_r_i_1 (.I0(samp_done), .I1(rd_active_r1), .I2(prev_samp_valid_r), .O(prev_samp_valid_r_reg)); LUT6 #( .INIT(64'h6664666466640000)) \rd_victim_sel_r[0]_i_1 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(\rd_victim_sel_r_reg[2]_0 ), .I4(rstdiv0_sync_r1_reg_rep__24), .I5(\samps_r_reg[9]_0 ), .O(\rd_victim_sel_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'h78787800)) \rd_victim_sel_r[1]_i_1 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(\samps_r_reg[9]_0 ), .O(\rd_victim_sel_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h7F807F807F800000)) \rd_victim_sel_r[2]_i_1 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(\rd_victim_sel_r_reg[2]_0 ), .I4(rstdiv0_sync_r1_reg_rep__24), .I5(\samps_r_reg[9]_0 ), .O(\rd_victim_sel_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_victim_sel_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel_r[0]_i_1_n_0 ), .Q(\rd_victim_sel_r_reg[1]_1 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_victim_sel_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel_r[1]_i_1_n_0 ), .Q(\rd_victim_sel_r_reg[1]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_victim_sel_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel_r[2]_i_1_n_0 ), .Q(\rd_victim_sel_r_reg[2]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAEAAA2A)) samp_done_r_i_1 (.I0(samp_done), .I1(\samps_r_reg[9]_0 ), .I2(phy_rddata_en_r1_reg), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(samp_done_ns9_in), .I5(samp_done_ns8_out), .O(samp_done_r_i_1_n_0)); FDRE #( .INIT(1'b0)) samp_done_r_reg (.C(CLK), .CE(1'b1), .D(samp_done_r_i_1_n_0), .Q(samp_done), .R(1'b0)); LUT6 #( .INIT(64'h000000003FFF8080)) \samp_result_r[0]_i_1 (.I0(zero_ge_thresh), .I1(rd_active_r1), .I2(samp_done), .I3(zero_le_half_thresh), .I4(\samp_result_r_reg_n_0_[0] ), .I5(rstdiv0_sync_r1_reg_rep__24), .O(D[0])); LUT6 #( .INIT(64'h1515400055554000)) \samp_result_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(rd_active_r1), .I2(samp_done), .I3(oneeighty_ge_thresh), .I4(p_0_in11_in), .I5(oneeighty_le_half_thresh), .O(D[1])); FDRE #( .INIT(1'b0)) \samp_result_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\samp_result_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \samp_result_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(p_0_in11_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair435" *) LUT1 #( .INIT(2'h1)) \samps_r[0]_i_1 (.I0(samps_r[0]), .O(samps_r0[0])); LUT4 #( .INIT(16'h9990)) \samps_r[1]_i_1 (.I0(samps_r[1]), .I1(samps_r[0]), .I2(\samps_r_reg[9]_0 ), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\samps_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair435" *) LUT3 #( .INIT(8'hA9)) \samps_r[2]_i_1 (.I0(samps_r[2]), .I1(samps_r[1]), .I2(samps_r[0]), .O(samps_r0[2])); (* SOFT_HLUTNM = "soft_lutpair424" *) LUT4 #( .INIT(16'hAAA9)) \samps_r[3]_i_1 (.I0(samps_r[3]), .I1(samps_r[2]), .I2(samps_r[0]), .I3(samps_r[1]), .O(samps_r0[3])); LUT6 #( .INIT(64'h00000000FFFE0001)) \samps_r[4]_i_1 (.I0(samps_r[2]), .I1(samps_r[0]), .I2(samps_r[1]), .I3(samps_r[3]), .I4(samps_r[4]), .I5(\sm_r_reg[0]_0 ), .O(\samps_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h9990)) \samps_r[5]_i_1 (.I0(\samps_r[8]_i_4_n_0 ), .I1(samps_r[5]), .I2(\samps_r_reg[9]_0 ), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\samps_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair430" *) LUT3 #( .INIT(8'hA9)) \samps_r[6]_i_1 (.I0(samps_r[6]), .I1(\samps_r[8]_i_4_n_0 ), .I2(samps_r[5]), .O(samps_r0[6])); (* SOFT_HLUTNM = "soft_lutpair430" *) LUT4 #( .INIT(16'hAAA9)) \samps_r[7]_i_1 (.I0(samps_r[7]), .I1(samps_r[6]), .I2(samps_r[5]), .I3(\samps_r[8]_i_4_n_0 ), .O(\samps_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'h1F11)) \samps_r[8]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(\samps_r[8]_i_3_n_0 ), .I3(\samps_r_reg[0]_0 ), .O(samps_ns)); (* SOFT_HLUTNM = "soft_lutpair426" *) LUT5 #( .INIT(32'hAAAAAAA9)) \samps_r[8]_i_2 (.I0(samps_r[8]), .I1(\samps_r[8]_i_4_n_0 ), .I2(samps_r[5]), .I3(samps_r[6]), .I4(samps_r[7]), .O(samps_r0[8])); LUT5 #( .INIT(32'h00000001)) \samps_r[8]_i_3 (.I0(samps_r[2]), .I1(samps_r[9]), .I2(samps_r[6]), .I3(samps_r[5]), .I4(\samps_r[8]_i_5_n_0 ), .O(\samps_r[8]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair424" *) LUT5 #( .INIT(32'hFFFFFFFE)) \samps_r[8]_i_4 (.I0(samps_r[4]), .I1(samps_r[3]), .I2(samps_r[2]), .I3(samps_r[0]), .I4(samps_r[1]), .O(\samps_r[8]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \samps_r[8]_i_5 (.I0(samps_r[4]), .I1(samps_r[3]), .I2(samps_r[8]), .I3(samps_r[0]), .I4(samps_r[1]), .I5(samps_r[7]), .O(\samps_r[8]_i_5_n_0 )); LUT4 #( .INIT(16'h1F11)) \samps_r[9]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(\samps_r[8]_i_3_n_0 ), .I3(\samps_r_reg[0]_0 ), .O(\samps_r[9]_i_1_n_0 )); LUT5 #( .INIT(32'hD2D2D2FF)) \samps_r[9]_i_2 (.I0(\samps_r[9]_i_3_n_0 ), .I1(samps_r[8]), .I2(samps_r[9]), .I3(\samps_r_reg[9]_0 ), .I4(rstdiv0_sync_r1_reg_rep__24), .O(\samps_r[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair426" *) LUT4 #( .INIT(16'h0001)) \samps_r[9]_i_3 (.I0(samps_r[7]), .I1(samps_r[6]), .I2(samps_r[5]), .I3(\samps_r[8]_i_4_n_0 ), .O(\samps_r[9]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[0] (.C(CLK), .CE(samps_ns), .D(samps_r0[0]), .Q(samps_r[0]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[1] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[1]_i_1_n_0 ), .Q(samps_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \samps_r_reg[2] (.C(CLK), .CE(samps_ns), .D(samps_r0[2]), .Q(samps_r[2]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[3] (.C(CLK), .CE(samps_ns), .D(samps_r0[3]), .Q(samps_r[3]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[4] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[4]_i_1_n_0 ), .Q(samps_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \samps_r_reg[5] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[5]_i_1_n_0 ), .Q(samps_r[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \samps_r_reg[6] (.C(CLK), .CE(samps_ns), .D(samps_r0[6]), .Q(samps_r[6]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[7] (.C(CLK), .CE(samps_ns), .D(\samps_r[7]_i_1_n_0 ), .Q(samps_r[7]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[8] (.C(CLK), .CE(samps_ns), .D(samps_r0[8]), .Q(samps_r[8]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \samps_r_reg[9] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[9]_i_2_n_0 ), .Q(samps_r[9]), .R(1'b0)); LUT4 #( .INIT(16'hAEEE)) \sm_r[0]_i_1__0 (.I0(samp_done_ns8_out), .I1(\samps_r_reg[9]_0 ), .I2(phy_rddata_en_r1_reg), .I3(samp_done_ns9_in), .O(\sm_r[0]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \sm_r_reg[0] (.C(CLK), .CE(1'b1), .D(\sm_r[0]_i_1__0_n_0 ), .Q(\samps_r_reg[9]_0 ), .R(rstdiv0_sync_r1_reg_rep__9)); LUT4 #( .INIT(16'hFFF7)) \stg3_r[5]_i_14 (.I0(samp_done), .I1(rd_active_r2), .I2(\sm_r_reg[1] ), .I3(scanning_right_r_reg), .O(\stg3_r_reg[1] )); CARRY4 zero_ge_thresh_carry (.CI(1'b0), .CO({zero_ge_thresh_carry_n_0,zero_ge_thresh_carry_n_1,zero_ge_thresh_carry_n_2,zero_ge_thresh_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,zero_ge_thresh_carry_i_1_n_0,zero_r_reg__0[3],zero_ge_thresh_carry_i_2_n_0}), .O(NLW_zero_ge_thresh_carry_O_UNCONNECTED[3:0]), .S({zero_ge_thresh_carry_i_3_n_0,zero_ge_thresh_carry_i_4_n_0,zero_ge_thresh_carry_i_5_n_0,zero_ge_thresh_carry_i_6_n_0})); CARRY4 zero_ge_thresh_carry__0 (.CI(zero_ge_thresh_carry_n_0), .CO({NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED[3:1],zero_ge_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,zero_r_reg__0[9]}), .O(NLW_zero_ge_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,zero_ge_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry__0_i_1 (.I0(zero_r_reg__0[8]), .I1(zero_r_reg__0[9]), .O(zero_ge_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h8)) zero_ge_thresh_carry_i_1 (.I0(zero_r_reg__0[4]), .I1(zero_r_reg__0[5]), .O(zero_ge_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) zero_ge_thresh_carry_i_2 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(zero_ge_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h8)) zero_ge_thresh_carry_i_3 (.I0(zero_r_reg__0[6]), .I1(zero_r_reg__0[7]), .O(zero_ge_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry_i_4 (.I0(zero_r_reg__0[5]), .I1(zero_r_reg__0[4]), .O(zero_ge_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry_i_5 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[3]), .O(zero_ge_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry_i_6 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(zero_ge_thresh_carry_i_6_n_0)); CARRY4 zero_le_half_thresh_carry (.CI(1'b0), .CO({zero_le_half_thresh_carry_n_0,zero_le_half_thresh_carry_n_1,zero_le_half_thresh_carry_n_2,zero_le_half_thresh_carry_n_3}), .CYINIT(1'b1), .DI({zero_le_half_thresh_carry_i_1_n_0,zero_le_half_thresh_carry_i_2_n_0,1'b0,zero_le_half_thresh_carry_i_3_n_0}), .O(NLW_zero_le_half_thresh_carry_O_UNCONNECTED[3:0]), .S({zero_le_half_thresh_carry_i_4_n_0,zero_le_half_thresh_carry_i_5_n_0,zero_le_half_thresh_carry_i_6_n_0,zero_le_half_thresh_carry_i_7_n_0})); CARRY4 zero_le_half_thresh_carry__0 (.CI(zero_le_half_thresh_carry_n_0), .CO({NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],zero_le_half_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,zero_le_half_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h1)) zero_le_half_thresh_carry__0_i_1 (.I0(zero_r_reg__0[8]), .I1(zero_r_reg__0[9]), .O(zero_le_half_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h7)) zero_le_half_thresh_carry_i_1 (.I0(zero_r_reg__0[7]), .I1(zero_r_reg__0[6]), .O(zero_le_half_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h7)) zero_le_half_thresh_carry_i_2 (.I0(zero_r_reg__0[5]), .I1(zero_r_reg__0[4]), .O(zero_le_half_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h7)) zero_le_half_thresh_carry_i_3 (.I0(zero_r_reg__0[0]), .I1(zero_r_reg__0[1]), .O(zero_le_half_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h8)) zero_le_half_thresh_carry_i_4 (.I0(zero_r_reg__0[6]), .I1(zero_r_reg__0[7]), .O(zero_le_half_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h8)) zero_le_half_thresh_carry_i_5 (.I0(zero_r_reg__0[4]), .I1(zero_r_reg__0[5]), .O(zero_le_half_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h1)) zero_le_half_thresh_carry_i_6 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[3]), .O(zero_le_half_thresh_carry_i_6_n_0)); LUT2 #( .INIT(4'h8)) zero_le_half_thresh_carry_i_7 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(zero_le_half_thresh_carry_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair436" *) LUT1 #( .INIT(2'h1)) \zero_r[0]_i_1 (.I0(zero_r_reg__0[0]), .O(\zero_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair436" *) LUT2 #( .INIT(4'h6)) \zero_r[1]_i_1 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair433" *) LUT3 #( .INIT(8'h6A)) \zero_r[2]_i_1 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[0]), .I2(zero_r_reg__0[1]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair421" *) LUT4 #( .INIT(16'h6AAA)) \zero_r[3]_i_1 (.I0(zero_r_reg__0[3]), .I1(zero_r_reg__0[1]), .I2(zero_r_reg__0[0]), .I3(zero_r_reg__0[2]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair421" *) LUT5 #( .INIT(32'h6AAAAAAA)) \zero_r[4]_i_1 (.I0(zero_r_reg__0[4]), .I1(zero_r_reg__0[2]), .I2(zero_r_reg__0[0]), .I3(zero_r_reg__0[1]), .I4(zero_r_reg__0[3]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \zero_r[5]_i_1 (.I0(zero_r_reg__0[5]), .I1(zero_r_reg__0[3]), .I2(zero_r_reg__0[1]), .I3(zero_r_reg__0[0]), .I4(zero_r_reg__0[2]), .I5(zero_r_reg__0[4]), .O(p_0_in__1[5])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \zero_r[6]_i_1 (.I0(zero_r_reg__0[6]), .I1(zero_r_reg__0[4]), .I2(zero_r_reg__0[5]), .I3(zero_r_reg__0[3]), .I4(\zero_r[6]_i_2_n_0 ), .I5(zero_r_reg__0[2]), .O(p_0_in__1[6])); (* SOFT_HLUTNM = "soft_lutpair433" *) LUT2 #( .INIT(4'h8)) \zero_r[6]_i_2 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(\zero_r[6]_i_2_n_0 )); LUT3 #( .INIT(8'h6A)) \zero_r[7]_i_1 (.I0(zero_r_reg__0[7]), .I1(\zero_r[9]_i_8_n_0 ), .I2(zero_r_reg__0[6]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair423" *) LUT4 #( .INIT(16'h6AAA)) \zero_r[8]_i_1 (.I0(zero_r_reg__0[8]), .I1(zero_r_reg__0[6]), .I2(zero_r_reg__0[7]), .I3(\zero_r[9]_i_8_n_0 ), .O(p_0_in__1[8])); (* SOFT_HLUTNM = "soft_lutpair423" *) LUT5 #( .INIT(32'h6AAAAAAA)) \zero_r[9]_i_3 (.I0(zero_r_reg__0[9]), .I1(zero_r_reg__0[7]), .I2(\zero_r[9]_i_8_n_0 ), .I3(zero_r_reg__0[6]), .I4(zero_r_reg__0[8]), .O(p_0_in__1[9])); LUT4 #( .INIT(16'h0002)) \zero_r[9]_i_6 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(\rd_victim_sel_r_reg[2]_0 ), .O(\samps_r_reg[0]_0 )); LUT6 #( .INIT(64'h8000000000000000)) \zero_r[9]_i_8 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[0]), .I2(zero_r_reg__0[1]), .I3(zero_r_reg__0[3]), .I4(zero_r_reg__0[5]), .I5(zero_r_reg__0[4]), .O(\zero_r[9]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[0] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(\zero_r[0]_i_1_n_0 ), .Q(zero_r_reg__0[0]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[1] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[1]), .Q(zero_r_reg__0[1]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[2] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[2]), .Q(zero_r_reg__0[2]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[3] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[3]), .Q(zero_r_reg__0[3]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[4] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[4]), .Q(zero_r_reg__0[4]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[5] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[5]), .Q(zero_r_reg__0[5]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[6] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[6]), .Q(zero_r_reg__0[6]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[7] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[7]), .Q(zero_r_reg__0[7]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[8] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[8]), .Q(zero_r_reg__0[8]), .R(\sm_r_reg[0]_0 )); FDRE #( .INIT(1'b0)) \zero_r_reg[9] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[9]), .Q(zero_r_reg__0[9]), .R(\sm_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_oclkdelay_cal" *) module ddr3_ifmig_7series_v4_0_ddr_phy_oclkdelay_cal (O, ocal_last_byte_done_reg, complex_oclk_calib_resume, ocd_prech_req, complex_ocal_num_samples_done_r, po_stg23_incdec, po_en_stg23, phy_rddata_en_1, wrlvl_final_mux_reg, lim2init_prech_req, done_r_reg, \samps_r_reg[9] , oclkdelay_center_calib_start_r_reg, D_po_sel_fine_oclk_delay125_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \resume_wait_r_reg[5] , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , complex_ocal_ref_req, stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] , \stg2_target_r_reg[8] , \stg3_tap_cnt_reg[2] , \byte_r_reg[1] , \byte_r_reg[0] , \stg2_tap_cnt_reg[3] , \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , complex_ocal_rd_victim_sel, \zero2fuzz_r_reg[0] , sr_valid_r108_out, \init_state_r_reg[4] , \init_state_r_reg[2] , \init_state_r_reg[0] , \init_state_r_reg[5] , \init_state_r_reg[5]_0 , \init_state_r_reg[6] , \init_state_r_reg[5]_1 , \init_state_r_reg[4]_0 , ocal_last_byte_done_reg_0, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \cal2_state_r_reg[0] , S, \qcntr_r_reg[0] , CLK, rstdiv0_sync_r1_reg_rep__20, poc_sample_pd, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__9, phy_rddata_en, Q, calib_in_common, \calib_zero_inputs_reg[1] , rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__25_0, oclkdelay_calib_start_int_reg, prech_done, rd_active_r2, rstdiv0_sync_r1_reg_rep__24, \sm_r_reg[0]_0 , rd_active_r1, \gen_byte_sel_div1.calib_in_common_reg , ck_addr_cmd_delay_done, mpr_rdlvl_done_r_reg, \gen_byte_sel_div1.calib_in_common_reg_0 , \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , \wl_po_fine_cnt_reg[17] , \byte_r_reg[0]_0 , D, \po_counter_read_val_reg[2] , \stg2_tap_cnt_reg[2] , \wl_po_fine_cnt_reg[3] , \wl_po_fine_cnt_reg[14] , \wl_po_fine_cnt_reg[18] , rstdiv0_sync_r1_reg_rep__25_1, rstdiv0_sync_r1_reg_rep__25_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , rdlvl_stg1_start_reg, \cnt_shift_r_reg[0] , \init_state_r_reg[0]_0 , prbs_rdlvl_done_reg, \init_state_r_reg[4]_1 , \init_state_r_reg[0]_1 , wrlvl_final_mux, oclkdelay_int_ref_req_reg, prech_req_posedge_r_reg, cnt_cmd_done_r, prbs_rdlvl_done_reg_rep, ocal_last_byte_done, \po_stg2_wrcal_cnt_reg[0] , wr_level_done_reg, oclkdelay_calib_done_r_reg, pi_stg2_rdlvl_cnt, \po_stg2_wrcal_cnt_reg[1] , wrlvl_byte_done, \wl_po_fine_cnt_reg[23] , \stg3_r_reg[0] , psdone, rstdiv0_sync_r1_reg_rep, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__19, rstdiv0_sync_r1_reg_rep__11, \po_counter_read_val_reg[5] , \byte_r_reg[0]_1 , rstdiv0_sync_r1_reg_rep__2, oclkdelay_calib_start_int_reg_0, pd_out); output [3:0]O; output ocal_last_byte_done_reg; output complex_oclk_calib_resume; output ocd_prech_req; output complex_ocal_num_samples_done_r; output po_stg23_incdec; output po_en_stg23; output phy_rddata_en_1; output wrlvl_final_mux_reg; output lim2init_prech_req; output done_r_reg; output \samps_r_reg[9] ; output oclkdelay_center_calib_start_r_reg; output D_po_sel_fine_oclk_delay125_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \resume_wait_r_reg[5] ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output complex_ocal_ref_req; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; output [2:0]\stg2_target_r_reg[8] ; output [2:0]\stg3_tap_cnt_reg[2] ; output \byte_r_reg[1] ; output \byte_r_reg[0] ; output [2:0]\stg2_tap_cnt_reg[3] ; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [2:0]complex_ocal_rd_victim_sel; output [0:0]\zero2fuzz_r_reg[0] ; output sr_valid_r108_out; output \init_state_r_reg[4] ; output \init_state_r_reg[2] ; output \init_state_r_reg[0] ; output \init_state_r_reg[5] ; output \init_state_r_reg[5]_0 ; output \init_state_r_reg[6] ; output \init_state_r_reg[5]_1 ; output \init_state_r_reg[4]_0 ; output ocal_last_byte_done_reg_0; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \cal2_state_r_reg[0] ; output [0:0]S; output [0:0]\qcntr_r_reg[0] ; input CLK; input rstdiv0_sync_r1_reg_rep__20; input poc_sample_pd; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__9; input phy_rddata_en; input [1:0]Q; input calib_in_common; input [1:0]\calib_zero_inputs_reg[1] ; input rstdiv0_sync_r1_reg_rep__25; input rstdiv0_sync_r1_reg_rep__25_0; input oclkdelay_calib_start_int_reg; input prech_done; input rd_active_r2; input rstdiv0_sync_r1_reg_rep__24; input [0:0]\sm_r_reg[0]_0 ; input rd_active_r1; input \gen_byte_sel_div1.calib_in_common_reg ; input ck_addr_cmd_delay_done; input mpr_rdlvl_done_r_reg; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \wl_po_fine_cnt_reg[17] ; input \byte_r_reg[0]_0 ; input [2:0]D; input \po_counter_read_val_reg[2] ; input \stg2_tap_cnt_reg[2] ; input \wl_po_fine_cnt_reg[3] ; input [1:0]\wl_po_fine_cnt_reg[14] ; input \wl_po_fine_cnt_reg[18] ; input rstdiv0_sync_r1_reg_rep__25_1; input rstdiv0_sync_r1_reg_rep__25_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input rdlvl_stg1_start_reg; input \cnt_shift_r_reg[0] ; input \init_state_r_reg[0]_0 ; input prbs_rdlvl_done_reg; input [2:0]\init_state_r_reg[4]_1 ; input \init_state_r_reg[0]_1 ; input wrlvl_final_mux; input oclkdelay_int_ref_req_reg; input prech_req_posedge_r_reg; input cnt_cmd_done_r; input prbs_rdlvl_done_reg_rep; input ocal_last_byte_done; input \po_stg2_wrcal_cnt_reg[0] ; input wr_level_done_reg; input oclkdelay_calib_done_r_reg; input [1:0]pi_stg2_rdlvl_cnt; input \po_stg2_wrcal_cnt_reg[1] ; input wrlvl_byte_done; input [7:0]\wl_po_fine_cnt_reg[23] ; input \stg3_r_reg[0] ; input psdone; input rstdiv0_sync_r1_reg_rep; input rstdiv0_sync_r1_reg_rep__0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input rstdiv0_sync_r1_reg_rep__11; input [5:0]\po_counter_read_val_reg[5] ; input [63:0]\byte_r_reg[0]_1 ; input rstdiv0_sync_r1_reg_rep__2; input oclkdelay_calib_start_int_reg_0; input pd_out; wire CLK; wire [2:0]D; wire D_po_sel_fine_oclk_delay125_out; wire [3:0]O; wire [1:0]Q; wire [0:0]S; wire [1:0]agg_samp_r; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire [63:0]\byte_r_reg[0]_1 ; wire \byte_r_reg[1] ; wire \cal2_state_r_reg[0] ; wire calib_in_common; wire [1:0]\calib_zero_inputs_reg[1] ; wire ck_addr_cmd_delay_done; wire cnt_cmd_done_r; wire \cnt_shift_r_reg[0] ; wire complex_ocal_num_samples_done_r; wire [2:0]complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_oclk_calib_resume; wire dec_po_ns; wire done_r_reg; wire f2z_ns5_out; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire inc_po_ns; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[2] ; wire \init_state_r_reg[4] ; wire \init_state_r_reg[4]_0 ; wire [2:0]\init_state_r_reg[4]_1 ; wire \init_state_r_reg[5] ; wire \init_state_r_reg[5]_0 ; wire \init_state_r_reg[5]_1 ; wire \init_state_r_reg[6] ; wire lim2init_prech_req; wire lim2poc_ktap_right; wire lim2poc_rdy; wire lim2stg2_dec; wire lim2stg2_inc; wire lim2stg3_dec; wire lim2stg3_inc; wire lim_start; wire lim_start_r; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mpr_rdlvl_done_r_reg; wire [1:0]ninety_offsets; wire o2f_ns1_out; wire ocal_last_byte_done; wire ocal_last_byte_done_reg; wire ocal_last_byte_done_reg_0; wire ocd_cntlr2stg2_dec_r; wire ocd_prech_req; wire oclk_center_write_resume; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_start_int_reg; wire oclkdelay_calib_start_int_reg_0; wire oclkdelay_center_calib_start_r_reg; wire oclkdelay_int_ref_req_reg; wire pd_out; wire phy_rddata_en; wire phy_rddata_en_1; wire [1:0]pi_stg2_rdlvl_cnt; wire \po_counter_read_val_reg[2] ; wire [5:0]\po_counter_read_val_reg[5] ; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire po_en_stg23; wire po_rdy; wire po_stg23_incdec; wire \po_stg2_wrcal_cnt_reg[0] ; wire \po_stg2_wrcal_cnt_reg[1] ; wire poc_sample_pd; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prech_done; wire prech_req_posedge_r_reg; wire [1:0]prev_samp_r; wire prev_samp_valid_r; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire rd_active_r1; wire rd_active_r2; wire rdlvl_stg1_start_reg; wire reset_scan; wire \resume_wait_r_reg[5] ; wire [5:0]rise_lead_right; wire [5:0]rise_trail_right; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__25_1; wire rstdiv0_sync_r1_reg_rep__25_2; wire rstdiv0_sync_r1_reg_rep__9; wire samp_done; wire samp_done_ns8_out; wire \samps_r_reg[9] ; wire scan_right; wire scanning_right; wire setup_po; wire [1:1]sm_r; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire sr_valid_r108_out; wire \stg2_tap_cnt_reg[0] ; wire \stg2_tap_cnt_reg[2] ; wire [2:0]\stg2_tap_cnt_reg[3] ; wire [2:0]\stg2_target_r_reg[8] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire [2:0]\stg3_tap_cnt_reg[2] ; wire u_ocd_cntlr_n_10; wire u_ocd_cntlr_n_11; wire u_ocd_cntlr_n_12; wire u_ocd_cntlr_n_13; wire u_ocd_cntlr_n_14; wire u_ocd_cntlr_n_15; wire u_ocd_cntlr_n_16; wire u_ocd_cntlr_n_17; wire u_ocd_cntlr_n_18; wire u_ocd_cntlr_n_19; wire u_ocd_cntlr_n_20; wire u_ocd_cntlr_n_9; wire u_ocd_data_n_0; wire u_ocd_data_n_1; wire u_ocd_data_n_2; wire u_ocd_edge_n_1; wire u_ocd_edge_n_10; wire u_ocd_edge_n_2; wire u_ocd_edge_n_3; wire u_ocd_edge_n_7; wire u_ocd_lim_n_19; wire u_ocd_lim_n_20; wire u_ocd_lim_n_21; wire u_ocd_lim_n_22; wire u_ocd_lim_n_23; wire u_ocd_lim_n_24; wire u_ocd_lim_n_25; wire u_ocd_lim_n_26; wire u_ocd_lim_n_27; wire u_ocd_lim_n_28; wire u_ocd_lim_n_29; wire u_ocd_lim_n_30; wire u_ocd_lim_n_31; wire u_ocd_lim_n_32; wire u_ocd_lim_n_9; wire u_ocd_mux_n_11; wire u_ocd_po_cntlr_n_11; wire u_ocd_po_cntlr_n_12; wire u_ocd_po_cntlr_n_13; wire u_ocd_po_cntlr_n_14; wire u_ocd_po_cntlr_n_15; wire u_ocd_po_cntlr_n_16; wire u_ocd_po_cntlr_n_17; wire u_ocd_po_cntlr_n_20; wire u_ocd_po_cntlr_n_22; wire u_ocd_po_cntlr_n_23; wire u_ocd_po_cntlr_n_27; wire u_ocd_po_cntlr_n_28; wire u_ocd_po_cntlr_n_29; wire u_ocd_po_cntlr_n_30; wire u_ocd_po_cntlr_n_31; wire u_ocd_po_cntlr_n_32; wire u_ocd_po_cntlr_n_33; wire u_ocd_po_cntlr_n_34; wire u_ocd_po_cntlr_n_35; wire u_ocd_po_cntlr_n_48; wire u_ocd_po_cntlr_n_49; wire u_ocd_po_cntlr_n_50; wire u_ocd_po_cntlr_n_51; wire u_ocd_po_cntlr_n_7; wire u_ocd_samp_n_10; wire u_ocd_samp_n_14; wire u_ocd_samp_n_16; wire u_ocd_samp_n_20; wire u_ocd_samp_n_21; wire u_ocd_samp_n_3; wire u_ocd_samp_n_4; wire u_ocd_samp_n_5; wire u_ocd_samp_n_6; wire u_ocd_samp_n_7; wire u_poc_n_0; wire u_poc_n_1; wire u_poc_n_16; wire u_poc_n_17; wire u_poc_n_2; wire use_noise_window; wire [1:0]\wl_po_fine_cnt_reg[14] ; wire \wl_po_fine_cnt_reg[17] ; wire \wl_po_fine_cnt_reg[18] ; wire [7:0]\wl_po_fine_cnt_reg[23] ; wire \wl_po_fine_cnt_reg[3] ; wire wr_level_done_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; wire wrlvl_byte_done; wire wrlvl_final_mux; wire wrlvl_final_mux_reg; wire [5:1]zero2fuzz_r0; wire [0:0]\zero2fuzz_r_reg[0] ; ddr3_ifmig_7series_v4_0_ddr_phy_ocd_cntlr u_ocd_cntlr (.CLK(CLK), .D({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}), .\byte_r_reg[0]_0 (\byte_r_reg[0] ), .\byte_r_reg[1]_0 (\byte_r_reg[1] ), .\cal2_state_r_reg[0] (\cal2_state_r_reg[0] ), .cnt_cmd_done_r(cnt_cmd_done_r), .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ), .complex_ocal_ref_req(complex_ocal_ref_req), .\data_cnt_r_reg[7] (u_ocd_samp_n_3), .done_r_reg(u_ocd_cntlr_n_18), .done_r_reg_0(done_r_reg), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\gen_byte_sel_div1.byte_sel_cnt_reg[0] ), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\gen_byte_sel_div1.byte_sel_cnt_reg[1] ), .\init_state_r_reg[0] (\init_state_r_reg[0]_1 ), .\init_state_r_reg[2] (\init_state_r_reg[2] ), .\init_state_r_reg[2]_0 (\init_state_r_reg[4]_1 [1:0]), .\init_state_r_reg[5] (\init_state_r_reg[5] ), .lim_start(lim_start), .lim_start_r(lim_start_r), .ocal_last_byte_done(ocal_last_byte_done), .ocal_last_byte_done_reg(ocal_last_byte_done_reg_0), .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r), .oclk_calib_resume_r_reg(complex_oclk_calib_resume), .oclkdelay_calib_done_r_reg_0(oclkdelay_calib_done_r_reg), .oclkdelay_calib_start_int_reg(oclkdelay_calib_start_int_reg), .oclkdelay_calib_start_int_reg_0(oclkdelay_calib_start_int_reg_0), .oclkdelay_center_calib_done_r_reg(ocal_last_byte_done_reg), .phy_rddata_en(phy_rddata_en), .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt), .\po_counter_read_val_reg[2] (\po_counter_read_val_reg[2] ), .po_rdy(po_rdy), .\po_stg2_wrcal_cnt_reg[0] (\po_stg2_wrcal_cnt_reg[0] ), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg), .prech_done(prech_done), .prech_req_posedge_r_reg(prech_req_posedge_r_reg), .prech_req_r_reg(ocd_prech_req), .prech_req_r_reg_0(lim2init_prech_req), .rd_active_r1(rd_active_r1), .rd_active_r1_reg(phy_rddata_en_1), .\rd_victim_sel_r_reg[0] (u_ocd_cntlr_n_19), .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg), .reset_scan(reset_scan), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25_0), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\simp_stg3_final_r_reg[10] (u_ocd_po_cntlr_n_30), .\simp_stg3_final_r_reg[11] (u_ocd_cntlr_n_15), .\simp_stg3_final_r_reg[12] (u_ocd_po_cntlr_n_33), .\simp_stg3_final_r_reg[16] (u_ocd_po_cntlr_n_50), .\simp_stg3_final_r_reg[17] (u_ocd_cntlr_n_17), .\simp_stg3_final_r_reg[17]_0 (u_ocd_po_cntlr_n_28), .\simp_stg3_final_r_reg[19] (u_ocd_po_cntlr_n_32), .\simp_stg3_final_r_reg[23] (u_ocd_cntlr_n_14), .\simp_stg3_final_r_reg[2] (u_ocd_po_cntlr_n_51), .\simp_stg3_final_r_reg[5] (u_ocd_cntlr_n_16), .\simp_stg3_final_r_reg[8] (u_ocd_po_cntlr_n_31), .sr_valid_r108_out(sr_valid_r108_out), .\stg3_init_val_reg[3] (u_ocd_cntlr_n_20), .wr_level_done_reg(wr_level_done_reg), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_final_mux_reg(wrlvl_final_mux_reg)); ddr3_ifmig_7series_v4_0_ddr_phy_ocd_data u_ocd_data (.CLK(CLK), .E(u_ocd_data_n_0), .agg_samp_r(agg_samp_r), .\byte_r_reg[0] (\byte_r_reg[0]_1 ), .\rd_victim_sel_r_reg[0] (u_ocd_samp_n_7), .\zero_r_reg[9] (u_ocd_data_n_1), .\zero_r_reg[9]_0 (u_ocd_data_n_2)); ddr3_ifmig_7series_v4_0_ddr_phy_ocd_edge u_ocd_edge (.CLK(CLK), .D({zero2fuzz_r0,\zero2fuzz_r_reg[0] }), .E(u_ocd_samp_n_16), .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}), .dec_po_ns(dec_po_ns), .f2o_r_reg_0(u_ocd_edge_n_3), .inc_po_ns(inc_po_ns), .\ninety_offsets_final_r_reg[0] (u_ocd_edge_n_2), .\ninety_offsets_final_r_reg[0]_0 (u_ocd_edge_n_10), .\ninety_offsets_final_r_reg[1] (u_ocd_edge_n_7), .o2f_r_reg_0(u_ocd_edge_n_1), .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7), .prev_samp_r(prev_samp_r), .prev_samp_valid_r(prev_samp_valid_r), .rd_active_r1(rd_active_r1), .rd_active_r1_reg(u_ocd_samp_n_5), .rd_active_r1_reg_0(u_ocd_samp_n_6), .reset_scan(reset_scan), .reset_scan_r_reg(u_ocd_samp_n_14), .samp_done(samp_done), .samp_done_r_reg(u_ocd_samp_n_4), .\samp_result_r_reg[0] (u_ocd_samp_n_20), .\samp_result_r_reg[1] (u_ocd_samp_n_21), .scan_right(scan_right), .scanning_right(scanning_right), .scanning_right_r_reg(u_ocd_po_cntlr_n_22), .scanning_right_r_reg_0(u_ocd_po_cntlr_n_23), .\stg3_left_lim_reg[5] ({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}), .\stg3_right_lim_reg[5] ({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32})); ddr3_ifmig_7series_v4_0_ddr_phy_ocd_lim u_ocd_lim (.CLK(CLK), .D(D), .Q(rise_trail_right), .\byte_r_reg[0] (\byte_r_reg[0]_0 ), .cnt_cmd_done_r(cnt_cmd_done_r), .done_r_reg_0(done_r_reg), .done_r_reg_1(u_poc_n_0), .\init_state_r_reg[4] (\init_state_r_reg[4]_0 ), .\init_state_r_reg[5] (\init_state_r_reg[5]_1 ), .\init_state_r_reg[6] (\init_state_r_reg[6] ), .lim2poc_ktap_right(lim2poc_ktap_right), .lim2poc_rdy(lim2poc_rdy), .lim2stg2_dec(lim2stg2_dec), .lim2stg2_inc(lim2stg2_inc), .lim2stg3_dec(lim2stg3_dec), .lim2stg3_inc(lim2stg3_inc), .lim_start(lim_start), .lim_start_r(lim_start_r), .lim_start_r_reg_0(u_ocd_cntlr_n_18), .\mmcm_current_reg[0]_0 (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0]_0 (\mmcm_init_trail_reg[0] ), .o2f_r_reg(u_ocd_edge_n_1), .ocd_prech_req_r_reg(ocd_prech_req), .oclk_center_write_resume(oclk_center_write_resume), .oclkdelay_calib_done_r_reg({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_po_cntlr_n_29,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}), .oclkdelay_center_calib_start_r_reg(u_ocd_lim_n_26), .oclkdelay_center_calib_start_r_reg_0({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32}), .po_rdy(po_rdy), .po_stg23_sel_r_reg(u_ocd_lim_n_9), .\po_wait_r_reg[0] (u_ocd_mux_n_11), .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep), .prech_done(prech_done), .prech_req_r_reg_0(lim2init_prech_req), .\rise_lead_r_reg[5] (rise_lead_right), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_1), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .scan_right(scan_right), .scanning_right(scanning_right), .scanning_right_r_reg(u_ocd_lim_n_19), .scanning_right_r_reg_0({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}), .\sm_r_reg[2] (u_ocd_po_cntlr_n_20), .\stg2_tap_cnt_reg[0]_0 (\stg2_tap_cnt_reg[0] ), .\stg2_tap_cnt_reg[2]_0 (\stg2_tap_cnt_reg[2] ), .\stg2_tap_cnt_reg[3]_0 (\stg2_tap_cnt_reg[3] ), .stg3_dec2init_val_r_reg_0(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg_0(stg3_inc2init_val_r_reg), .\stg3_r_reg[5] ({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}), .\stg3_tap_cnt_reg[2]_0 (\stg3_tap_cnt_reg[2] ), .\wl_po_fine_cnt_reg[14] (\wl_po_fine_cnt_reg[14] ), .\wl_po_fine_cnt_reg[17] (\wl_po_fine_cnt_reg[17] ), .\wl_po_fine_cnt_reg[18] (\wl_po_fine_cnt_reg[18] ), .\wl_po_fine_cnt_reg[3] (\wl_po_fine_cnt_reg[3] )); ddr3_ifmig_7series_v4_0_ddr_phy_ocd_mux u_ocd_mux (.CLK(CLK), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .Q(Q), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] (\calib_zero_inputs_reg[1] ), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_2 ), .mpr_rdlvl_done_r_reg(mpr_rdlvl_done_r_reg), .oclkdelay_calib_done_r_reg(wrlvl_final_mux_reg), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8] ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_0 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_1 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_2 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_3 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_4 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_5 ), .po_rdy(po_rdy), .po_stg23_incdec(po_stg23_incdec), .po_stg23_sel_r_reg_0(u_ocd_mux_n_11), .\po_wait_r_reg[3]_0 (po_en_stg23), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .setup_po(setup_po), .stg2_dec_req_r_reg(u_ocd_po_cntlr_n_27), .stg3_dec_req_r_reg(u_ocd_lim_n_9), .stg3_inc_req_r_reg(u_ocd_po_cntlr_n_17)); ddr3_ifmig_7series_v4_0_ddr_phy_ocd_po_cntlr u_ocd_po_cntlr (.CLK(CLK), .D({zero2fuzz_r0,\zero2fuzz_r_reg[0] }), .E(\resume_wait_r_reg[5] ), .O(O), .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}), .S(S), .\byte_r_reg[0] (\byte_r_reg[0]_0 ), .\byte_r_reg[0]_0 (\byte_r_reg[0] ), .\byte_r_reg[0]_1 (u_ocd_cntlr_n_14), .\byte_r_reg[0]_2 (u_ocd_cntlr_n_15), .\byte_r_reg[0]_3 (u_ocd_cntlr_n_16), .\byte_r_reg[1] (\byte_r_reg[1] ), .\byte_r_reg[1]_0 (u_ocd_cntlr_n_17), .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r), .dec_po_ns(dec_po_ns), .done_r_reg(u_poc_n_0), .edge_aligned_r_reg(u_ocd_po_cntlr_n_49), .edge_aligned_r_reg_0(u_poc_n_1), .f2o_r_reg(u_ocd_edge_n_7), .f2o_r_reg_0(u_ocd_edge_n_10), .f2z_ns5_out(f2z_ns5_out), .f2z_r_reg(u_ocd_po_cntlr_n_23), .f2z_r_reg_0(u_ocd_edge_n_2), .inc_po_ns(inc_po_ns), .\init_state_r_reg[0] (\init_state_r_reg[0] ), .lim2poc_ktap_right(lim2poc_ktap_right), .lim2poc_rdy(lim2poc_rdy), .lim2stg2_dec(lim2stg2_dec), .lim2stg2_inc(lim2stg2_inc), .lim2stg3_dec(lim2stg3_dec), .lim2stg3_inc(lim2stg3_inc), .ninety_offsets(ninety_offsets), .o2f_ns1_out(o2f_ns1_out), .o2f_r_reg(u_ocd_po_cntlr_n_22), .o2f_r_reg_0(u_ocd_edge_n_1), .ocal_last_byte_done_reg(ocal_last_byte_done_reg), .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r), .oclk_center_write_resume(oclk_center_write_resume), .oclkdelay_calib_done_r_reg(u_ocd_cntlr_n_20), .oclkdelay_calib_done_r_reg_0(wrlvl_final_mux_reg), .oclkdelay_center_calib_start_r_reg_0(oclkdelay_center_calib_start_r_reg), .oclkdelay_int_ref_req_reg(oclkdelay_int_ref_req_reg), .\po_counter_read_val_reg[5] (\po_counter_read_val_reg[5] ), .po_rdy(po_rdy), .po_stg23_incdec(po_stg23_incdec), .po_stg23_incdec_r_reg(u_ocd_po_cntlr_n_17), .po_stg23_incdec_r_reg_0(u_ocd_po_cntlr_n_27), .poc_backup_r_reg_0(u_ocd_po_cntlr_n_48), .poc_backup_r_reg_1(u_poc_n_2), .prech_req_posedge_r_reg(prech_req_posedge_r_reg), .rd_active_r2(rd_active_r2), .reset_scan(reset_scan), .\rise_trail_r_reg[5] (u_ocd_po_cntlr_n_34), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_2), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\run_ends_r_reg[0] (u_poc_n_16), .\run_ends_r_reg[1] (u_ocd_po_cntlr_n_35), .\run_ends_r_reg[1]_0 (u_poc_n_17), .samp_done(samp_done), .samp_done_ns8_out(samp_done_ns8_out), .samp_done_r_reg(u_ocd_samp_n_10), .scan_right_r_reg(u_ocd_lim_n_19), .scanning_right(scanning_right), .scanning_right_r_reg_0(u_ocd_lim_n_26), .setup_po(setup_po), .\sm_r_reg[0]_0 (\sm_r_reg[0] ), .\sm_r_reg[0]_1 (\samps_r_reg[9] ), .\sm_r_reg[3]_0 (u_ocd_po_cntlr_n_7), .\stg2_r_reg[0]_0 (sm_r), .\stg2_target_r_reg[8]_0 (\stg2_target_r_reg[8] ), .\stg3_init_val_reg[0] (u_ocd_po_cntlr_n_33), .\stg3_init_val_reg[1] (u_ocd_po_cntlr_n_32), .\stg3_init_val_reg[2] (u_ocd_po_cntlr_n_31), .\stg3_init_val_reg[2]_0 (u_ocd_po_cntlr_n_51), .\stg3_init_val_reg[3] (u_ocd_po_cntlr_n_29), .\stg3_init_val_reg[4] (u_ocd_po_cntlr_n_30), .\stg3_init_val_reg[4]_0 (u_ocd_po_cntlr_n_50), .\stg3_init_val_reg[5] (u_ocd_po_cntlr_n_28), .\stg3_r_reg[0]_0 (\stg3_r_reg[0] ), .\two_r_reg[1]_0 (u_ocd_po_cntlr_n_20), .use_noise_window(use_noise_window), .\wl_po_fine_cnt_reg[14] (\wl_po_fine_cnt_reg[14] ), .\wl_po_fine_cnt_reg[17] (\wl_po_fine_cnt_reg[17] ), .\wl_po_fine_cnt_reg[18] (\wl_po_fine_cnt_reg[18] ), .\wl_po_fine_cnt_reg[23] (\wl_po_fine_cnt_reg[23] ), .\wl_po_fine_cnt_reg[3] (\wl_po_fine_cnt_reg[3] ), .wrlvl_final_mux(wrlvl_final_mux)); ddr3_ifmig_7series_v4_0_ddr_phy_ocd_samp u_ocd_samp (.CLK(CLK), .D({u_ocd_samp_n_5,u_ocd_samp_n_6}), .E(u_ocd_samp_n_16), .agg_samp_r(agg_samp_r), .\data_bytes_r_reg[24] (u_ocd_data_n_1), .\data_bytes_r_reg[32] (u_ocd_data_n_2), .f2o_r_reg(u_ocd_edge_n_3), .f2z_ns5_out(f2z_ns5_out), .\init_state_r_reg[0] (\init_state_r_reg[0]_0 ), .\init_state_r_reg[4] (\init_state_r_reg[4] ), .\init_state_r_reg[4]_0 (\init_state_r_reg[4]_1 [2]), .\init_state_r_reg[5] (\init_state_r_reg[5]_0 ), .o2f_ns1_out(o2f_ns1_out), .ocd_prech_req_r_reg(ocd_prech_req), .oclk_calib_resume_level_reg(complex_oclk_calib_resume), .oclk_calib_resume_r_reg_0(u_ocd_samp_n_3), .\oneeighty2fuzz_r_reg[5] (u_ocd_samp_n_14), .phy_rddata_en_r1_reg(phy_rddata_en_1), .phy_rddata_en_r1_reg_0(u_ocd_cntlr_n_19), .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg), .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep), .prech_req_r_reg(lim2init_prech_req), .prev_samp_r(prev_samp_r), .\prev_samp_r_reg[0] (u_ocd_samp_n_20), .\prev_samp_r_reg[1] (u_ocd_samp_n_21), .prev_samp_valid_r(prev_samp_valid_r), .prev_samp_valid_r_reg(u_ocd_samp_n_4), .rd_active_r1(rd_active_r1), .rd_active_r2(rd_active_r2), .\rd_victim_sel_r_reg[0]_0 (u_ocd_data_n_0), .\rd_victim_sel_r_reg[1]_0 (complex_ocal_rd_victim_sel[1]), .\rd_victim_sel_r_reg[1]_1 (complex_ocal_rd_victim_sel[0]), .\rd_victim_sel_r_reg[2]_0 (complex_ocal_rd_victim_sel[2]), .reset_scan(reset_scan), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .samp_done(samp_done), .samp_done_ns8_out(samp_done_ns8_out), .\samps_r_reg[0]_0 (u_ocd_samp_n_7), .\samps_r_reg[9]_0 (\samps_r_reg[9] ), .scanning_right(scanning_right), .scanning_right_r_reg(u_ocd_lim_n_26), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\sm_r_reg[1] (sm_r), .\stg3_r_reg[1] (u_ocd_samp_n_10)); ddr3_ifmig_7series_v4_0_poc_top u_poc (.CLK(CLK), .Q(rise_trail_right), .detect_done_r_reg(u_poc_n_0), .\mmcm_init_lead_reg[5] (rise_lead_right), .ninety_offsets(ninety_offsets), .ocd_edge_detect_rdy_r_reg(u_ocd_po_cntlr_n_35), .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7), .ocd_ktap_left_r_reg_0(u_ocd_po_cntlr_n_49), .ocd_ktap_right_r_reg(u_ocd_po_cntlr_n_34), .pd_out(pd_out), .poc_backup_r_reg(u_poc_n_2), .poc_sample_pd(poc_sample_pd), .\prev_r_reg[0] (u_poc_n_16), .\prev_r_reg[0]_0 (u_poc_n_17), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\run_ends_r_reg[1] (u_ocd_po_cntlr_n_48), .\sm_r_reg[1] (u_poc_n_1), .use_noise_window(use_noise_window)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_prbs_rdlvl" *) module ddr3_ifmig_7series_v4_0_ddr_phy_prbs_rdlvl (prbs_rdlvl_start_r, \row_cnt_victim_rotate.complex_row_cnt_reg[4] , prech_req_r_reg, prbs_prech_req_r, pi_en_stg2_f_timing_reg_0, prbs_pi_stg2_f_en, prbs_pi_stg2_f_incdec, A, \A[0]_0 , \A[1]_0 , no_err_win_detected_latch_reg_0, cnt_wait_state, \rdlvl_cpt_tap_cnt_reg[5]_0 , prbs_found_1st_edge_r_reg_0, \genblk8[0].left_loss_pb_reg[0]_0 , \genblk8[1].left_loss_pb_reg[6]_0 , \genblk8[2].left_loss_pb_reg[12]_0 , \genblk8[3].left_loss_pb_reg[18]_0 , \genblk8[4].left_loss_pb_reg[24]_0 , \genblk8[5].left_loss_pb_reg[30]_0 , \genblk8[6].left_loss_pb_reg[36]_0 , \genblk8[7].left_loss_pb_reg[42]_0 , \genblk8[0].right_edge_pb_reg[0]_0 , \genblk8[1].right_edge_pb_reg[6]_0 , \genblk8[2].right_edge_pb_reg[12]_0 , \genblk8[3].right_edge_pb_reg[18]_0 , \genblk8[4].right_edge_pb_reg[24]_0 , \genblk8[5].right_edge_pb_reg[30]_0 , \genblk8[6].right_edge_pb_reg[36]_0 , \genblk8[7].right_edge_pb_reg[42]_0 , fine_delay_sel_r_reg, right_edge_found_reg_0, prbs_tap_inc_r, \match_flag_or_reg[0]_0 , \largest_left_edge_reg[0]_0 , D, prbs_rdlvl_done_reg_0, \stg1_wr_rd_cnt_reg[3] , prbs_last_byte_done, reset_rd_addr, complex_init_pi_dec_done, complex_pi_incdec_done, \prbs_dqs_cnt_r_reg[2]_0 , complex_oclkdelay_calib_done_r1_reg, p_154_out, p_95_out, \genblk8[7].right_edge_pb_reg[42]_1 , p_98_out, p_103_out, p_106_out, \genblk8[5].right_edge_pb_reg[30]_1 , \genblk8[5].right_gain_pb_reg[30]_0 , p_119_out, p_122_out, p_127_out, p_130_out, \genblk8[2].right_edge_pb_reg[12]_1 , \genblk8[2].right_edge_pb_reg[12]_2 , p_143_out, p_146_out, \genblk8[0].right_edge_pb_reg[0]_1 , \genblk8[0].left_loss_pb_reg[0]_1 , Q, num_samples_done_r, prbs_state_r178_out, bit_cnt, \genblk9[0].fine_delay_incdec_pb_reg[0]_0 , right_edge_found_reg_1, \prbs_dec_tap_cnt_reg[1]_0 , reset_rd_addr0, \genblk8[7].left_edge_updated_reg[7]_0 , \rd_victim_sel_reg[2]_0 , \oclkdelay_ref_cnt_reg[0] , prbs_rdlvl_done_pulse0, \init_state_r_reg[0] , \init_state_r_reg[1] , \init_state_r_reg[0]_0 , \init_state_r_reg[1]_0 , \fine_delay_mod_reg[5] , \fine_delay_mod_reg[20] , \rdlvl_cpt_tap_cnt_reg[5]_1 , right_gain_pb, right_edge_found, no_err_win_detected_reg_0, prbs_found_1st_edge_r_reg_1, prbs_tap_en_r_reg_0, prbs_tap_en_r, fine_delay_sel_reg_0, no_err_win_detected_latch_reg_1, fine_delay_sel_reg_1, complex_pi_incdec_done_reg_0, num_samples_done_ind_reg_0, complex_pi_incdec_done_reg_1, fine_dly_error_reg_0, compare_err_latch_reg_0, \prbs_dqs_cnt_r_reg[1]_0 , prbs_rdlvl_done_reg_1, prbs_last_byte_done_reg_0, new_cnt_dqs_r_reg_0, new_cnt_dqs_r, \rd_victim_sel_reg[2]_1 , \rd_victim_sel_reg[2]_2 , \rd_victim_sel_reg[2]_3 , \fine_delay_mod_reg[26] , \genblk9[1].fine_delay_incdec_pb_reg[1]_0 , \genblk9[2].fine_delay_incdec_pb_reg[2]_0 , \genblk9[3].fine_delay_incdec_pb_reg[3]_0 , \genblk9[5].fine_delay_incdec_pb_reg[5]_0 , \genblk9[6].fine_delay_incdec_pb_reg[6]_0 , \genblk9[7].fine_delay_incdec_pb_reg[7]_0 , CLK, prbs_rdlvl_start_reg, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , rstdiv0_sync_r1_reg_rep__7, \dout_o_reg[7] , \dout_o_reg[7]_0 , \dout_o_reg[7]_1 , \dout_o_reg[7]_2 , \dout_o_reg[7]_3 , \dout_o_reg[7]_4 , \dout_o_reg[7]_5 , \dout_o_reg[7]_6 , \A[1]_1 , \A[1]_2 , \A[1]_3 , \A[1]_4 , \A[1]_5 , \A[1]_6 , \A[1]_7 , \A[1]_8 , \dout_o_reg[6] , \dout_o_reg[6]_0 , \dout_o_reg[6]_1 , \dout_o_reg[6]_2 , \dout_o_reg[6]_3 , \dout_o_reg[6]_4 , \dout_o_reg[6]_5 , \dout_o_reg[6]_6 , \A[1]_9 , \A[1]_10 , \A[1]_11 , \A[1]_12 , \A[1]_13 , \A[1]_14 , \A[1]_15 , \A[1]_16 , \dout_o_reg[5] , \dout_o_reg[5]_0 , \dout_o_reg[5]_1 , \dout_o_reg[5]_2 , \dout_o_reg[5]_3 , \dout_o_reg[5]_4 , \dout_o_reg[5]_5 , \dout_o_reg[5]_6 , \A[1]_17 , \A[1]_18 , \A[1]_19 , \A[1]_20 , \A[1]_21 , \A[1]_22 , \A[1]_23 , \A[1]_24 , \dout_o_reg[4] , \dout_o_reg[4]_0 , \dout_o_reg[4]_1 , \dout_o_reg[4]_2 , \dout_o_reg[4]_3 , \dout_o_reg[4]_4 , \dout_o_reg[4]_5 , \dout_o_reg[4]_6 , \A[1]_25 , \A[1]_26 , \A[1]_27 , \A[1]_28 , \A[1]_29 , \A[1]_30 , \A[1]_31 , \A[1]_32 , \dout_o_reg[3] , \dout_o_reg[3]_0 , \dout_o_reg[3]_1 , \dout_o_reg[3]_2 , \dout_o_reg[3]_3 , \dout_o_reg[3]_4 , \dout_o_reg[3]_5 , \dout_o_reg[3]_6 , \A[1]_33 , \A[1]_34 , \A[1]_35 , \A[1]_36 , \A[1]_37 , \A[1]_38 , \A[1]_39 , \A[1]_40 , \dout_o_reg[2] , \dout_o_reg[2]_0 , \dout_o_reg[2]_1 , \dout_o_reg[2]_2 , \dout_o_reg[2]_3 , \dout_o_reg[2]_4 , \dout_o_reg[2]_5 , \dout_o_reg[2]_6 , \A[1]_41 , \A[1]_42 , \A[1]_43 , \A[1]_44 , \A[1]_45 , \A[1]_46 , \A[1]_47 , \A[1]_48 , \dout_o_reg[1] , \dout_o_reg[1]_0 , \dout_o_reg[1]_1 , \dout_o_reg[1]_2 , \dout_o_reg[1]_3 , \dout_o_reg[1]_4 , \dout_o_reg[1]_5 , \dout_o_reg[1]_6 , \A[1]_49 , \A[1]_50 , \A[1]_51 , \A[1]_52 , \A[1]_53 , \A[1]_54 , \A[1]_55 , \A[1]_56 , \dout_o_reg[0] , \dout_o_reg[0]_0 , \dout_o_reg[0]_1 , \dout_o_reg[0]_2 , \dout_o_reg[0]_3 , \dout_o_reg[0]_4 , \dout_o_reg[0]_5 , \dout_o_reg[0]_6 , \A[1]_57 , \A[1]_58 , \A[1]_59 , \A[1]_60 , \A[1]_61 , \A[1]_62 , \A[1]_63 , \A[1]_64 , rstdiv0_sync_r1_reg_rep__8, rstdiv0_sync_r1_reg_rep__2, SR, \prbs_state_r_reg[4]_0 , \prbs_state_r_reg[3]_0 , \genblk8[0].left_edge_found_pb_reg[0]_0 , \genblk8[1].left_edge_found_pb_reg[1]_0 , \genblk8[2].left_edge_found_pb_reg[2]_0 , \genblk8[3].left_edge_found_pb_reg[3]_0 , \genblk8[4].left_edge_found_pb_reg[4]_0 , \genblk8[5].left_edge_found_pb_reg[5]_0 , \genblk8[6].left_edge_found_pb_reg[6]_0 , \genblk8[7].left_edge_found_pb_reg[7]_0 , \genblk8[0].right_edge_found_pb_reg[0]_0 , \genblk8[1].right_edge_found_pb_reg[1]_0 , \genblk8[2].right_edge_found_pb_reg[2]_0 , \genblk8[3].right_edge_found_pb_reg[3]_0 , \genblk8[4].right_edge_found_pb_reg[4]_0 , \genblk8[5].right_edge_found_pb_reg[5]_0 , \genblk8[6].right_edge_found_pb_reg[6]_0 , \genblk8[7].right_edge_found_pb_reg[7]_0 , \prbs_state_r_reg[0]_0 , no_err_win_detected_reg_1, new_cnt_dqs_r_reg_1, \prbs_state_r_reg[0]_1 , \prbs_state_r_reg[0]_2 , \prbs_state_r_reg[4]_1 , \prbs_state_r_reg[3]_1 , \genblk8[0].left_edge_updated_reg[0]_0 , \genblk8[1].left_edge_updated_reg[1]_0 , \genblk8[2].left_edge_updated_reg[2]_0 , \genblk8[3].left_edge_updated_reg[3]_0 , \genblk8[4].left_edge_updated_reg[4]_0 , \genblk8[5].left_edge_updated_reg[5]_0 , \genblk8[6].left_edge_updated_reg[6]_0 , \genblk8[7].left_edge_updated_reg[7]_1 , \dec_cnt_reg[0]_0 , fine_dly_error_reg_1, \prbs_state_r_reg[0]_3 , prech_done_reg, prbs_tap_inc_r_reg_0, rstdiv0_sync_r1_reg_rep__9, \prbs_state_r_reg[4]_2 , \prbs_state_r_reg[4]_3 , \prbs_state_r_reg[0]_4 , \prbs_dqs_cnt_r_reg[0]_0 , \prbs_dqs_cnt_r_reg[0]_1 , \prbs_dqs_cnt_r_reg[0]_2 , rstdiv0_sync_r1_reg_rep, complex_ocal_reset_rd_addr, \calib_sel_reg[3] , \pi_counter_read_val_reg[5] , rstdiv0_sync_r1_reg_rep__23, oclkdelay_center_calib_done_r_reg, ocal_last_byte_done, prbs_rdlvl_done_r1, rdlvl_stg1_done_int_reg, wrcal_done_reg, dqs_found_done_r_reg, \num_refresh_reg[1] , wrlvl_final_mux, rdlvl_stg1_start_int, rdlvl_last_byte_done, \one_rank.stg1_wr_done_reg , \A[2]__2 , \calib_sel_reg[3]_0 , \calib_sel_reg[3]_1 , \calib_sel_reg[3]_2 , rstdiv0_sync_r1_reg_rep__22, complex_act_start, prech_done, prbs_rdlvl_start_reg_0, E, \stage_cnt_reg[1]_0 ); output prbs_rdlvl_start_r; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output prech_req_r_reg; output prbs_prech_req_r; output pi_en_stg2_f_timing_reg_0; output prbs_pi_stg2_f_en; output prbs_pi_stg2_f_incdec; output [1:0]A; output \A[0]_0 ; output \A[1]_0 ; output no_err_win_detected_latch_reg_0; output cnt_wait_state; output \rdlvl_cpt_tap_cnt_reg[5]_0 ; output prbs_found_1st_edge_r_reg_0; output \genblk8[0].left_loss_pb_reg[0]_0 ; output \genblk8[1].left_loss_pb_reg[6]_0 ; output \genblk8[2].left_loss_pb_reg[12]_0 ; output \genblk8[3].left_loss_pb_reg[18]_0 ; output \genblk8[4].left_loss_pb_reg[24]_0 ; output \genblk8[5].left_loss_pb_reg[30]_0 ; output \genblk8[6].left_loss_pb_reg[36]_0 ; output \genblk8[7].left_loss_pb_reg[42]_0 ; output \genblk8[0].right_edge_pb_reg[0]_0 ; output \genblk8[1].right_edge_pb_reg[6]_0 ; output \genblk8[2].right_edge_pb_reg[12]_0 ; output \genblk8[3].right_edge_pb_reg[18]_0 ; output \genblk8[4].right_edge_pb_reg[24]_0 ; output \genblk8[5].right_edge_pb_reg[30]_0 ; output \genblk8[6].right_edge_pb_reg[36]_0 ; output \genblk8[7].right_edge_pb_reg[42]_0 ; output fine_delay_sel_r_reg; output right_edge_found_reg_0; output prbs_tap_inc_r; output \match_flag_or_reg[0]_0 ; output \largest_left_edge_reg[0]_0 ; output [7:0]D; output prbs_rdlvl_done_reg_0; output \stg1_wr_rd_cnt_reg[3] ; output prbs_last_byte_done; output reset_rd_addr; output complex_init_pi_dec_done; output complex_pi_incdec_done; output \prbs_dqs_cnt_r_reg[2]_0 ; output complex_oclkdelay_calib_done_r1_reg; output p_154_out; output p_95_out; output \genblk8[7].right_edge_pb_reg[42]_1 ; output p_98_out; output p_103_out; output p_106_out; output \genblk8[5].right_edge_pb_reg[30]_1 ; output \genblk8[5].right_gain_pb_reg[30]_0 ; output p_119_out; output p_122_out; output p_127_out; output p_130_out; output \genblk8[2].right_edge_pb_reg[12]_1 ; output \genblk8[2].right_edge_pb_reg[12]_2 ; output p_143_out; output p_146_out; output \genblk8[0].right_edge_pb_reg[0]_1 ; output \genblk8[0].left_loss_pb_reg[0]_1 ; output [4:0]Q; output num_samples_done_r; output prbs_state_r178_out; output bit_cnt; output \genblk9[0].fine_delay_incdec_pb_reg[0]_0 ; output right_edge_found_reg_1; output [1:0]\prbs_dec_tap_cnt_reg[1]_0 ; output reset_rd_addr0; output \genblk8[7].left_edge_updated_reg[7]_0 ; output \rd_victim_sel_reg[2]_0 ; output \oclkdelay_ref_cnt_reg[0] ; output prbs_rdlvl_done_pulse0; output \init_state_r_reg[0] ; output \init_state_r_reg[1] ; output \init_state_r_reg[0]_0 ; output \init_state_r_reg[1]_0 ; output \fine_delay_mod_reg[5] ; output \fine_delay_mod_reg[20] ; output [2:0]\rdlvl_cpt_tap_cnt_reg[5]_1 ; output right_gain_pb; output right_edge_found; output no_err_win_detected_reg_0; output prbs_found_1st_edge_r_reg_1; output prbs_tap_en_r_reg_0; output prbs_tap_en_r; output fine_delay_sel_reg_0; output no_err_win_detected_latch_reg_1; output fine_delay_sel_reg_1; output complex_pi_incdec_done_reg_0; output num_samples_done_ind_reg_0; output complex_pi_incdec_done_reg_1; output fine_dly_error_reg_0; output compare_err_latch_reg_0; output \prbs_dqs_cnt_r_reg[1]_0 ; output prbs_rdlvl_done_reg_1; output prbs_last_byte_done_reg_0; output new_cnt_dqs_r_reg_0; output new_cnt_dqs_r; output \rd_victim_sel_reg[2]_1 ; output \rd_victim_sel_reg[2]_2 ; output \rd_victim_sel_reg[2]_3 ; output \fine_delay_mod_reg[26] ; output \genblk9[1].fine_delay_incdec_pb_reg[1]_0 ; output \genblk9[2].fine_delay_incdec_pb_reg[2]_0 ; output \genblk9[3].fine_delay_incdec_pb_reg[3]_0 ; output \genblk9[5].fine_delay_incdec_pb_reg[5]_0 ; output \genblk9[6].fine_delay_incdec_pb_reg[6]_0 ; output \genblk9[7].fine_delay_incdec_pb_reg[7]_0 ; input CLK; input prbs_rdlvl_start_reg; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input [0:0]rstdiv0_sync_r1_reg_rep__7; input \dout_o_reg[7] ; input \dout_o_reg[7]_0 ; input \dout_o_reg[7]_1 ; input \dout_o_reg[7]_2 ; input \dout_o_reg[7]_3 ; input \dout_o_reg[7]_4 ; input \dout_o_reg[7]_5 ; input \dout_o_reg[7]_6 ; input \A[1]_1 ; input \A[1]_2 ; input \A[1]_3 ; input \A[1]_4 ; input \A[1]_5 ; input \A[1]_6 ; input \A[1]_7 ; input \A[1]_8 ; input \dout_o_reg[6] ; input \dout_o_reg[6]_0 ; input \dout_o_reg[6]_1 ; input \dout_o_reg[6]_2 ; input \dout_o_reg[6]_3 ; input \dout_o_reg[6]_4 ; input \dout_o_reg[6]_5 ; input \dout_o_reg[6]_6 ; input \A[1]_9 ; input \A[1]_10 ; input \A[1]_11 ; input \A[1]_12 ; input \A[1]_13 ; input \A[1]_14 ; input \A[1]_15 ; input \A[1]_16 ; input \dout_o_reg[5] ; input \dout_o_reg[5]_0 ; input \dout_o_reg[5]_1 ; input \dout_o_reg[5]_2 ; input \dout_o_reg[5]_3 ; input \dout_o_reg[5]_4 ; input \dout_o_reg[5]_5 ; input \dout_o_reg[5]_6 ; input \A[1]_17 ; input \A[1]_18 ; input \A[1]_19 ; input \A[1]_20 ; input \A[1]_21 ; input \A[1]_22 ; input \A[1]_23 ; input \A[1]_24 ; input \dout_o_reg[4] ; input \dout_o_reg[4]_0 ; input \dout_o_reg[4]_1 ; input \dout_o_reg[4]_2 ; input \dout_o_reg[4]_3 ; input \dout_o_reg[4]_4 ; input \dout_o_reg[4]_5 ; input \dout_o_reg[4]_6 ; input \A[1]_25 ; input \A[1]_26 ; input \A[1]_27 ; input \A[1]_28 ; input \A[1]_29 ; input \A[1]_30 ; input \A[1]_31 ; input \A[1]_32 ; input \dout_o_reg[3] ; input \dout_o_reg[3]_0 ; input \dout_o_reg[3]_1 ; input \dout_o_reg[3]_2 ; input \dout_o_reg[3]_3 ; input \dout_o_reg[3]_4 ; input \dout_o_reg[3]_5 ; input \dout_o_reg[3]_6 ; input \A[1]_33 ; input \A[1]_34 ; input \A[1]_35 ; input \A[1]_36 ; input \A[1]_37 ; input \A[1]_38 ; input \A[1]_39 ; input \A[1]_40 ; input \dout_o_reg[2] ; input \dout_o_reg[2]_0 ; input \dout_o_reg[2]_1 ; input \dout_o_reg[2]_2 ; input \dout_o_reg[2]_3 ; input \dout_o_reg[2]_4 ; input \dout_o_reg[2]_5 ; input \dout_o_reg[2]_6 ; input \A[1]_41 ; input \A[1]_42 ; input \A[1]_43 ; input \A[1]_44 ; input \A[1]_45 ; input \A[1]_46 ; input \A[1]_47 ; input \A[1]_48 ; input \dout_o_reg[1] ; input \dout_o_reg[1]_0 ; input \dout_o_reg[1]_1 ; input \dout_o_reg[1]_2 ; input \dout_o_reg[1]_3 ; input \dout_o_reg[1]_4 ; input \dout_o_reg[1]_5 ; input \dout_o_reg[1]_6 ; input \A[1]_49 ; input \A[1]_50 ; input \A[1]_51 ; input \A[1]_52 ; input \A[1]_53 ; input \A[1]_54 ; input \A[1]_55 ; input \A[1]_56 ; input \dout_o_reg[0] ; input \dout_o_reg[0]_0 ; input \dout_o_reg[0]_1 ; input \dout_o_reg[0]_2 ; input \dout_o_reg[0]_3 ; input \dout_o_reg[0]_4 ; input \dout_o_reg[0]_5 ; input \dout_o_reg[0]_6 ; input \A[1]_57 ; input \A[1]_58 ; input \A[1]_59 ; input \A[1]_60 ; input \A[1]_61 ; input \A[1]_62 ; input \A[1]_63 ; input \A[1]_64 ; input rstdiv0_sync_r1_reg_rep__8; input rstdiv0_sync_r1_reg_rep__2; input [0:0]SR; input \prbs_state_r_reg[4]_0 ; input \prbs_state_r_reg[3]_0 ; input \genblk8[0].left_edge_found_pb_reg[0]_0 ; input \genblk8[1].left_edge_found_pb_reg[1]_0 ; input \genblk8[2].left_edge_found_pb_reg[2]_0 ; input \genblk8[3].left_edge_found_pb_reg[3]_0 ; input \genblk8[4].left_edge_found_pb_reg[4]_0 ; input \genblk8[5].left_edge_found_pb_reg[5]_0 ; input \genblk8[6].left_edge_found_pb_reg[6]_0 ; input \genblk8[7].left_edge_found_pb_reg[7]_0 ; input \genblk8[0].right_edge_found_pb_reg[0]_0 ; input \genblk8[1].right_edge_found_pb_reg[1]_0 ; input \genblk8[2].right_edge_found_pb_reg[2]_0 ; input \genblk8[3].right_edge_found_pb_reg[3]_0 ; input \genblk8[4].right_edge_found_pb_reg[4]_0 ; input \genblk8[5].right_edge_found_pb_reg[5]_0 ; input \genblk8[6].right_edge_found_pb_reg[6]_0 ; input \genblk8[7].right_edge_found_pb_reg[7]_0 ; input \prbs_state_r_reg[0]_0 ; input no_err_win_detected_reg_1; input new_cnt_dqs_r_reg_1; input \prbs_state_r_reg[0]_1 ; input \prbs_state_r_reg[0]_2 ; input \prbs_state_r_reg[4]_1 ; input \prbs_state_r_reg[3]_1 ; input \genblk8[0].left_edge_updated_reg[0]_0 ; input \genblk8[1].left_edge_updated_reg[1]_0 ; input \genblk8[2].left_edge_updated_reg[2]_0 ; input \genblk8[3].left_edge_updated_reg[3]_0 ; input \genblk8[4].left_edge_updated_reg[4]_0 ; input \genblk8[5].left_edge_updated_reg[5]_0 ; input \genblk8[6].left_edge_updated_reg[6]_0 ; input \genblk8[7].left_edge_updated_reg[7]_1 ; input \dec_cnt_reg[0]_0 ; input fine_dly_error_reg_1; input \prbs_state_r_reg[0]_3 ; input prech_done_reg; input prbs_tap_inc_r_reg_0; input rstdiv0_sync_r1_reg_rep__9; input \prbs_state_r_reg[4]_2 ; input \prbs_state_r_reg[4]_3 ; input \prbs_state_r_reg[0]_4 ; input \prbs_dqs_cnt_r_reg[0]_0 ; input \prbs_dqs_cnt_r_reg[0]_1 ; input \prbs_dqs_cnt_r_reg[0]_2 ; input rstdiv0_sync_r1_reg_rep; input complex_ocal_reset_rd_addr; input [0:0]\calib_sel_reg[3] ; input [3:0]\pi_counter_read_val_reg[5] ; input rstdiv0_sync_r1_reg_rep__23; input oclkdelay_center_calib_done_r_reg; input ocal_last_byte_done; input prbs_rdlvl_done_r1; input rdlvl_stg1_done_int_reg; input wrcal_done_reg; input dqs_found_done_r_reg; input \num_refresh_reg[1] ; input wrlvl_final_mux; input rdlvl_stg1_start_int; input rdlvl_last_byte_done; input \one_rank.stg1_wr_done_reg ; input \A[2]__2 ; input \calib_sel_reg[3]_0 ; input \calib_sel_reg[3]_1 ; input \calib_sel_reg[3]_2 ; input rstdiv0_sync_r1_reg_rep__22; input complex_act_start; input prech_done; input prbs_rdlvl_start_reg_0; input [0:0]E; input \stage_cnt_reg[1]_0 ; wire [1:0]A; wire \A[0]_0 ; wire \A[1]_0 ; wire \A[1]_1 ; wire \A[1]_10 ; wire \A[1]_11 ; wire \A[1]_12 ; wire \A[1]_13 ; wire \A[1]_14 ; wire \A[1]_15 ; wire \A[1]_16 ; wire \A[1]_17 ; wire \A[1]_18 ; wire \A[1]_19 ; wire \A[1]_2 ; wire \A[1]_20 ; wire \A[1]_21 ; wire \A[1]_22 ; wire \A[1]_23 ; wire \A[1]_24 ; wire \A[1]_25 ; wire \A[1]_26 ; wire \A[1]_27 ; wire \A[1]_28 ; wire \A[1]_29 ; wire \A[1]_3 ; wire \A[1]_30 ; wire \A[1]_31 ; wire \A[1]_32 ; wire \A[1]_33 ; wire \A[1]_34 ; wire \A[1]_35 ; wire \A[1]_36 ; wire \A[1]_37 ; wire \A[1]_38 ; wire \A[1]_39 ; wire \A[1]_4 ; wire \A[1]_40 ; wire \A[1]_41 ; wire \A[1]_42 ; wire \A[1]_43 ; wire \A[1]_44 ; wire \A[1]_45 ; wire \A[1]_46 ; wire \A[1]_47 ; wire \A[1]_48 ; wire \A[1]_49 ; wire \A[1]_5 ; wire \A[1]_50 ; wire \A[1]_51 ; wire \A[1]_52 ; wire \A[1]_53 ; wire \A[1]_54 ; wire \A[1]_55 ; wire \A[1]_56 ; wire \A[1]_57 ; wire \A[1]_58 ; wire \A[1]_59 ; wire \A[1]_6 ; wire \A[1]_60 ; wire \A[1]_61 ; wire \A[1]_62 ; wire \A[1]_63 ; wire \A[1]_64 ; wire \A[1]_7 ; wire \A[1]_8 ; wire \A[1]_9 ; wire \A[2]__2 ; wire CLK; wire [7:0]D; wire [0:0]E; wire [4:0]Q; wire [0:0]SR; wire bit_cnt; wire bit_cnt0; wire \bit_cnt[7]_i_3_n_0 ; wire \bit_cnt[7]_i_4_n_0 ; wire [7:0]bit_cnt_reg__0; wire [0:0]\calib_sel_reg[3] ; wire \calib_sel_reg[3]_0 ; wire \calib_sel_reg[3]_1 ; wire \calib_sel_reg[3]_2 ; wire \cmp_err_4to1.compare_err_f0_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f0_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f0_reg_n_0 ; wire \cmp_err_4to1.compare_err_f1_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f1_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f1_reg_n_0 ; wire \cmp_err_4to1.compare_err_f2_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f2_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f2_reg_n_0 ; wire \cmp_err_4to1.compare_err_f3_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f3_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f3_reg_n_0 ; wire \cmp_err_4to1.compare_err_i_4_n_0 ; wire \cmp_err_4to1.compare_err_r0_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r0_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r0_reg_n_0 ; wire \cmp_err_4to1.compare_err_r1_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r1_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r1_reg_n_0 ; wire \cmp_err_4to1.compare_err_r2_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r2_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r2_reg_n_0 ; wire \cmp_err_4to1.compare_err_r3_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r3_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r3_reg_n_0 ; wire \cmp_err_4to1.compare_err_reg_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ; wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ; wire cnt_wait_state; wire cnt_wait_state_i_1_n_0; wire compare_err0; wire compare_err086_out__0; wire compare_err2; wire compare_err_f00; wire compare_err_f10; wire compare_err_f20; wire compare_err_f30; wire compare_err_latch_i_1_n_0; wire compare_err_latch_i_2_n_0; wire compare_err_latch_reg_0; wire compare_err_latch_reg_n_0; wire [7:0]compare_err_pb; wire compare_err_pb_and2; wire compare_err_pb_and_i_1_n_0; wire compare_err_pb_and_i_2_n_0; wire compare_err_pb_and_i_3_n_0; wire compare_err_pb_and_reg_n_0; wire compare_err_pb_or_i_1_n_0; wire compare_err_pb_or_i_2_n_0; wire compare_err_pb_or_i_3_n_0; wire compare_err_r00; wire compare_err_r10; wire compare_err_r20; wire compare_err_r30; wire complex_act_start; wire complex_init_pi_dec_done; wire complex_ocal_reset_rd_addr; wire complex_oclkdelay_calib_done_r1_reg; wire complex_pi_incdec_done; wire complex_pi_incdec_done_i_3_n_0; wire complex_pi_incdec_done_i_4_n_0; wire complex_pi_incdec_done_i_5_n_0; wire complex_pi_incdec_done_i_6_n_0; wire complex_pi_incdec_done_reg_0; wire complex_pi_incdec_done_reg_1; wire complex_victim_inc__0; wire [11:1]data0; wire \dec_cnt[0]_i_11_n_0 ; wire \dec_cnt[0]_i_13_n_0 ; wire \dec_cnt[0]_i_14_n_0 ; wire \dec_cnt[0]_i_15_n_0 ; wire \dec_cnt[0]_i_16_n_0 ; wire \dec_cnt[0]_i_17_n_0 ; wire \dec_cnt[0]_i_1_n_0 ; wire \dec_cnt[0]_i_20_n_0 ; wire \dec_cnt[0]_i_21_n_0 ; wire \dec_cnt[0]_i_22_n_0 ; wire \dec_cnt[0]_i_23_n_0 ; wire \dec_cnt[0]_i_24_n_0 ; wire \dec_cnt[0]_i_25_n_0 ; wire \dec_cnt[0]_i_26_n_0 ; wire \dec_cnt[0]_i_29_n_0 ; wire \dec_cnt[0]_i_32_n_0 ; wire \dec_cnt[0]_i_33_n_0 ; wire \dec_cnt[0]_i_34_n_0 ; wire \dec_cnt[0]_i_35_n_0 ; wire \dec_cnt[0]_i_36_n_0 ; wire \dec_cnt[0]_i_37_n_0 ; wire \dec_cnt[0]_i_38_n_0 ; wire \dec_cnt[0]_i_39_n_0 ; wire \dec_cnt[0]_i_3_n_0 ; wire \dec_cnt[0]_i_40_n_0 ; wire \dec_cnt[0]_i_41_n_0 ; wire \dec_cnt[0]_i_42_n_0 ; wire \dec_cnt[0]_i_43_n_0 ; wire \dec_cnt[0]_i_44_n_0 ; wire \dec_cnt[0]_i_45_n_0 ; wire \dec_cnt[0]_i_46_n_0 ; wire \dec_cnt[0]_i_47_n_0 ; wire \dec_cnt[0]_i_4_n_0 ; wire \dec_cnt[0]_i_5_n_0 ; wire \dec_cnt[0]_i_6_n_0 ; wire \dec_cnt[0]_i_8_n_0 ; wire \dec_cnt[0]_i_9_n_0 ; wire \dec_cnt[1]_i_13_n_0 ; wire \dec_cnt[1]_i_15_n_0 ; wire \dec_cnt[1]_i_16_n_0 ; wire \dec_cnt[1]_i_19_n_0 ; wire \dec_cnt[1]_i_1_n_0 ; wire \dec_cnt[1]_i_20_n_0 ; wire \dec_cnt[1]_i_21_n_0 ; wire \dec_cnt[1]_i_22_n_0 ; wire \dec_cnt[1]_i_25_n_0 ; wire \dec_cnt[1]_i_26_n_0 ; wire \dec_cnt[1]_i_27_n_0 ; wire \dec_cnt[1]_i_28_n_0 ; wire \dec_cnt[1]_i_29_n_0 ; wire \dec_cnt[1]_i_2_n_0 ; wire \dec_cnt[1]_i_30_n_0 ; wire \dec_cnt[1]_i_31_n_0 ; wire \dec_cnt[1]_i_32_n_0 ; wire \dec_cnt[1]_i_33_n_0 ; wire \dec_cnt[1]_i_34_n_0 ; wire \dec_cnt[1]_i_35_n_0 ; wire \dec_cnt[1]_i_36_n_0 ; wire \dec_cnt[1]_i_37_n_0 ; wire \dec_cnt[1]_i_38_n_0 ; wire \dec_cnt[1]_i_3_n_0 ; wire \dec_cnt[1]_i_4_n_0 ; wire \dec_cnt[1]_i_5_n_0 ; wire \dec_cnt[1]_i_6_n_0 ; wire \dec_cnt[1]_i_8_n_0 ; wire \dec_cnt[1]_i_9_n_0 ; wire \dec_cnt[2]_i_10_n_0 ; wire \dec_cnt[2]_i_11_n_0 ; wire \dec_cnt[2]_i_12_n_0 ; wire \dec_cnt[2]_i_13_n_0 ; wire \dec_cnt[2]_i_14_n_0 ; wire \dec_cnt[2]_i_15_n_0 ; wire \dec_cnt[2]_i_17_n_0 ; wire \dec_cnt[2]_i_18_n_0 ; wire \dec_cnt[2]_i_19_n_0 ; wire \dec_cnt[2]_i_20_n_0 ; wire \dec_cnt[2]_i_21_n_0 ; wire \dec_cnt[2]_i_22_n_0 ; wire \dec_cnt[2]_i_23_n_0 ; wire \dec_cnt[2]_i_24_n_0 ; wire \dec_cnt[2]_i_25_n_0 ; wire \dec_cnt[2]_i_26_n_0 ; wire \dec_cnt[2]_i_27_n_0 ; wire \dec_cnt[2]_i_28_n_0 ; wire \dec_cnt[2]_i_29_n_0 ; wire \dec_cnt[2]_i_2_n_0 ; wire \dec_cnt[2]_i_30_n_0 ; wire \dec_cnt[2]_i_31_n_0 ; wire \dec_cnt[2]_i_32_n_0 ; wire \dec_cnt[2]_i_33_n_0 ; wire \dec_cnt[2]_i_34_n_0 ; wire \dec_cnt[2]_i_3_n_0 ; wire \dec_cnt[2]_i_5_n_0 ; wire \dec_cnt[2]_i_6_n_0 ; wire \dec_cnt[2]_i_7_n_0 ; wire \dec_cnt[3]_i_10_n_0 ; wire \dec_cnt[3]_i_11_n_0 ; wire \dec_cnt[3]_i_12_n_0 ; wire \dec_cnt[3]_i_13_n_0 ; wire \dec_cnt[3]_i_14_n_0 ; wire \dec_cnt[3]_i_15_n_0 ; wire \dec_cnt[3]_i_16_n_0 ; wire \dec_cnt[3]_i_17_n_0 ; wire \dec_cnt[3]_i_18_n_0 ; wire \dec_cnt[3]_i_19_n_0 ; wire \dec_cnt[3]_i_1_n_0 ; wire \dec_cnt[3]_i_20_n_0 ; wire \dec_cnt[3]_i_21_n_0 ; wire \dec_cnt[3]_i_22_n_0 ; wire \dec_cnt[3]_i_23_n_0 ; wire \dec_cnt[3]_i_24_n_0 ; wire \dec_cnt[3]_i_25_n_0 ; wire \dec_cnt[3]_i_26_n_0 ; wire \dec_cnt[3]_i_27_n_0 ; wire \dec_cnt[3]_i_2_n_0 ; wire \dec_cnt[3]_i_3_n_0 ; wire \dec_cnt[3]_i_4_n_0 ; wire \dec_cnt[3]_i_5_n_0 ; wire \dec_cnt[3]_i_6_n_0 ; wire \dec_cnt[3]_i_7_n_0 ; wire \dec_cnt[3]_i_8_n_0 ; wire \dec_cnt[3]_i_9_n_0 ; wire \dec_cnt[4]_i_10_n_0 ; wire \dec_cnt[4]_i_11_n_0 ; wire \dec_cnt[4]_i_12_n_0 ; wire \dec_cnt[4]_i_13_n_0 ; wire \dec_cnt[4]_i_14_n_0 ; wire \dec_cnt[4]_i_15_n_0 ; wire \dec_cnt[4]_i_16_n_0 ; wire \dec_cnt[4]_i_17_n_0 ; wire \dec_cnt[4]_i_1_n_0 ; wire \dec_cnt[4]_i_3_n_0 ; wire \dec_cnt[4]_i_4_n_0 ; wire \dec_cnt[4]_i_5_n_0 ; wire \dec_cnt[4]_i_6_n_0 ; wire \dec_cnt[4]_i_7_n_0 ; wire \dec_cnt[4]_i_8_n_0 ; wire \dec_cnt[4]_i_9_n_0 ; wire \dec_cnt[5]_i_1_n_0 ; wire \dec_cnt[5]_i_2_n_0 ; wire \dec_cnt[5]_i_3_n_0 ; wire \dec_cnt[5]_i_4_n_0 ; wire \dec_cnt[5]_i_5_n_0 ; wire \dec_cnt[5]_i_6_n_0 ; wire \dec_cnt[5]_i_7_n_0 ; wire [4:1]dec_cnt_reg; wire \dec_cnt_reg[0]_0 ; wire \dec_cnt_reg[0]_i_10_n_0 ; wire \dec_cnt_reg[0]_i_12_n_0 ; wire \dec_cnt_reg[0]_i_18_n_0 ; wire \dec_cnt_reg[0]_i_19_n_0 ; wire \dec_cnt_reg[0]_i_27_n_0 ; wire \dec_cnt_reg[0]_i_28_n_0 ; wire \dec_cnt_reg[0]_i_2_n_0 ; wire \dec_cnt_reg[0]_i_30_n_0 ; wire \dec_cnt_reg[0]_i_31_n_0 ; wire \dec_cnt_reg[0]_i_7_n_0 ; wire \dec_cnt_reg[1]_i_10_n_0 ; wire \dec_cnt_reg[1]_i_11_n_0 ; wire \dec_cnt_reg[1]_i_12_n_0 ; wire \dec_cnt_reg[1]_i_14_n_0 ; wire \dec_cnt_reg[1]_i_17_n_0 ; wire \dec_cnt_reg[1]_i_18_n_0 ; wire \dec_cnt_reg[1]_i_23_n_0 ; wire \dec_cnt_reg[1]_i_24_n_0 ; wire \dec_cnt_reg[1]_i_7_n_0 ; wire \dec_cnt_reg[2]_i_16_n_0 ; wire \dec_cnt_reg[2]_i_1_n_0 ; wire \dec_cnt_reg[2]_i_4_n_0 ; wire \dec_cnt_reg[2]_i_8_n_0 ; wire \dec_cnt_reg[2]_i_9_n_0 ; wire \dec_cnt_reg[4]_i_2_n_0 ; wire \dout_o_reg[0] ; wire \dout_o_reg[0]_0 ; wire \dout_o_reg[0]_1 ; wire \dout_o_reg[0]_2 ; wire \dout_o_reg[0]_3 ; wire \dout_o_reg[0]_4 ; wire \dout_o_reg[0]_5 ; wire \dout_o_reg[0]_6 ; wire \dout_o_reg[1] ; wire \dout_o_reg[1]_0 ; wire \dout_o_reg[1]_1 ; wire \dout_o_reg[1]_2 ; wire \dout_o_reg[1]_3 ; wire \dout_o_reg[1]_4 ; wire \dout_o_reg[1]_5 ; wire \dout_o_reg[1]_6 ; wire \dout_o_reg[2] ; wire \dout_o_reg[2]_0 ; wire \dout_o_reg[2]_1 ; wire \dout_o_reg[2]_2 ; wire \dout_o_reg[2]_3 ; wire \dout_o_reg[2]_4 ; wire \dout_o_reg[2]_5 ; wire \dout_o_reg[2]_6 ; wire \dout_o_reg[3] ; wire \dout_o_reg[3]_0 ; wire \dout_o_reg[3]_1 ; wire \dout_o_reg[3]_2 ; wire \dout_o_reg[3]_3 ; wire \dout_o_reg[3]_4 ; wire \dout_o_reg[3]_5 ; wire \dout_o_reg[3]_6 ; wire \dout_o_reg[4] ; wire \dout_o_reg[4]_0 ; wire \dout_o_reg[4]_1 ; wire \dout_o_reg[4]_2 ; wire \dout_o_reg[4]_3 ; wire \dout_o_reg[4]_4 ; wire \dout_o_reg[4]_5 ; wire \dout_o_reg[4]_6 ; wire \dout_o_reg[5] ; wire \dout_o_reg[5]_0 ; wire \dout_o_reg[5]_1 ; wire \dout_o_reg[5]_2 ; wire \dout_o_reg[5]_3 ; wire \dout_o_reg[5]_4 ; wire \dout_o_reg[5]_5 ; wire \dout_o_reg[5]_6 ; wire \dout_o_reg[6] ; wire \dout_o_reg[6]_0 ; wire \dout_o_reg[6]_1 ; wire \dout_o_reg[6]_2 ; wire \dout_o_reg[6]_3 ; wire \dout_o_reg[6]_4 ; wire \dout_o_reg[6]_5 ; wire \dout_o_reg[6]_6 ; wire \dout_o_reg[7] ; wire \dout_o_reg[7]_0 ; wire \dout_o_reg[7]_1 ; wire \dout_o_reg[7]_2 ; wire \dout_o_reg[7]_3 ; wire \dout_o_reg[7]_4 ; wire \dout_o_reg[7]_5 ; wire \dout_o_reg[7]_6 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire dqs_found_done_r_reg; wire err_chk_invalid; wire err_chk_invalid_i_1_n_0; wire \fine_delay_mod_reg[20] ; wire \fine_delay_mod_reg[26] ; wire \fine_delay_mod_reg[5] ; wire fine_delay_sel_i_4_n_0; wire fine_delay_sel_r_reg; wire fine_delay_sel_reg_0; wire fine_delay_sel_reg_1; wire fine_dly_error_reg_0; wire fine_dly_error_reg_1; wire fine_inc_stage_i_1_n_0; wire fine_inc_stage_reg_n_0; wire fine_pi_dec_cnt; wire \fine_pi_dec_cnt[0]_i_1_n_0 ; wire \fine_pi_dec_cnt[0]_i_2_n_0 ; wire \fine_pi_dec_cnt[1]_i_1_n_0 ; wire \fine_pi_dec_cnt[1]_i_2_n_0 ; wire \fine_pi_dec_cnt[2]_i_1_n_0 ; wire \fine_pi_dec_cnt[2]_i_2_n_0 ; wire \fine_pi_dec_cnt[3]_i_10_n_0 ; wire \fine_pi_dec_cnt[3]_i_1_n_0 ; wire \fine_pi_dec_cnt[3]_i_2_n_0 ; wire \fine_pi_dec_cnt[3]_i_4_n_0 ; wire \fine_pi_dec_cnt[3]_i_5_n_0 ; wire \fine_pi_dec_cnt[3]_i_6_n_0 ; wire \fine_pi_dec_cnt[3]_i_7_n_0 ; wire \fine_pi_dec_cnt[3]_i_8_n_0 ; wire \fine_pi_dec_cnt[3]_i_9_n_0 ; wire \fine_pi_dec_cnt[4]_i_2_n_0 ; wire \fine_pi_dec_cnt[4]_i_3_n_0 ; wire \fine_pi_dec_cnt[5]_i_10_n_0 ; wire \fine_pi_dec_cnt[5]_i_11_n_0 ; wire \fine_pi_dec_cnt[5]_i_3_n_0 ; wire \fine_pi_dec_cnt[5]_i_4_n_0 ; wire \fine_pi_dec_cnt[5]_i_5_n_0 ; wire \fine_pi_dec_cnt[5]_i_6_n_0 ; wire \fine_pi_dec_cnt[5]_i_7_n_0 ; wire \fine_pi_dec_cnt[5]_i_9_n_0 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_0 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_1 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_2 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_3 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_4 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_5 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_6 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_7 ; wire \fine_pi_dec_cnt_reg[4]_i_1_n_0 ; wire \fine_pi_dec_cnt_reg[5]_i_2_n_0 ; wire \fine_pi_dec_cnt_reg[5]_i_8_n_3 ; wire \fine_pi_dec_cnt_reg[5]_i_8_n_6 ; wire \fine_pi_dec_cnt_reg[5]_i_8_n_7 ; wire \fine_pi_dec_cnt_reg_n_0_[0] ; wire \fine_pi_dec_cnt_reg_n_0_[1] ; wire \fine_pi_dec_cnt_reg_n_0_[2] ; wire \fine_pi_dec_cnt_reg_n_0_[3] ; wire \fine_pi_dec_cnt_reg_n_0_[4] ; wire \fine_pi_dec_cnt_reg_n_0_[5] ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ; wire \gen_mux_rd[0].compare_data_fall0_r1_reg ; wire \gen_mux_rd[0].compare_data_fall1_r1_reg ; wire \gen_mux_rd[0].compare_data_fall2_r1_reg ; wire \gen_mux_rd[0].compare_data_fall3_r1_reg ; wire \gen_mux_rd[0].compare_data_rise0_r1_reg ; wire \gen_mux_rd[0].compare_data_rise1_r1_reg ; wire \gen_mux_rd[0].compare_data_rise2_r1_reg ; wire \gen_mux_rd[0].compare_data_rise3_r1_reg ; wire \gen_mux_rd[1].compare_data_fall0_r1_reg ; wire \gen_mux_rd[1].compare_data_fall1_r1_reg ; wire \gen_mux_rd[1].compare_data_fall2_r1_reg ; wire \gen_mux_rd[1].compare_data_fall3_r1_reg ; wire \gen_mux_rd[1].compare_data_rise0_r1_reg ; wire \gen_mux_rd[1].compare_data_rise1_r1_reg ; wire \gen_mux_rd[1].compare_data_rise2_r1_reg ; wire \gen_mux_rd[1].compare_data_rise3_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[2].compare_data_fall0_r1_reg ; wire \gen_mux_rd[2].compare_data_fall1_r1_reg ; wire \gen_mux_rd[2].compare_data_fall2_r1_reg ; wire \gen_mux_rd[2].compare_data_fall3_r1_reg ; wire \gen_mux_rd[2].compare_data_rise0_r1_reg ; wire \gen_mux_rd[2].compare_data_rise1_r1_reg ; wire \gen_mux_rd[2].compare_data_rise2_r1_reg ; wire \gen_mux_rd[2].compare_data_rise3_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[3].compare_data_fall0_r1_reg ; wire \gen_mux_rd[3].compare_data_fall1_r1_reg ; wire \gen_mux_rd[3].compare_data_fall2_r1_reg ; wire \gen_mux_rd[3].compare_data_fall3_r1_reg ; wire \gen_mux_rd[3].compare_data_rise0_r1_reg ; wire \gen_mux_rd[3].compare_data_rise1_r1_reg ; wire \gen_mux_rd[3].compare_data_rise2_r1_reg ; wire \gen_mux_rd[3].compare_data_rise3_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[4].compare_data_fall0_r1_reg ; wire \gen_mux_rd[4].compare_data_fall1_r1_reg ; wire \gen_mux_rd[4].compare_data_fall2_r1_reg ; wire \gen_mux_rd[4].compare_data_fall3_r1_reg ; wire \gen_mux_rd[4].compare_data_rise0_r1_reg ; wire \gen_mux_rd[4].compare_data_rise1_r1_reg ; wire \gen_mux_rd[4].compare_data_rise2_r1_reg ; wire \gen_mux_rd[4].compare_data_rise3_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[5].compare_data_fall0_r1_reg ; wire \gen_mux_rd[5].compare_data_fall1_r1_reg ; wire \gen_mux_rd[5].compare_data_fall2_r1_reg ; wire \gen_mux_rd[5].compare_data_fall3_r1_reg ; wire \gen_mux_rd[5].compare_data_rise0_r1_reg ; wire \gen_mux_rd[5].compare_data_rise1_r1_reg ; wire \gen_mux_rd[5].compare_data_rise2_r1_reg ; wire \gen_mux_rd[5].compare_data_rise3_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[6].compare_data_fall0_r1_reg ; wire \gen_mux_rd[6].compare_data_fall1_r1_reg ; wire \gen_mux_rd[6].compare_data_fall2_r1_reg ; wire \gen_mux_rd[6].compare_data_fall3_r1_reg ; wire \gen_mux_rd[6].compare_data_rise0_r1_reg ; wire \gen_mux_rd[6].compare_data_rise1_r1_reg ; wire \gen_mux_rd[6].compare_data_rise2_r1_reg ; wire \gen_mux_rd[6].compare_data_rise3_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[7].compare_data_fall0_r1_reg ; wire \gen_mux_rd[7].compare_data_fall1_r1_reg ; wire \gen_mux_rd[7].compare_data_fall2_r1_reg ; wire \gen_mux_rd[7].compare_data_fall3_r1_reg ; wire \gen_mux_rd[7].compare_data_rise0_r1_reg ; wire \gen_mux_rd[7].compare_data_rise1_r1_reg ; wire \gen_mux_rd[7].compare_data_rise2_r1_reg ; wire \gen_mux_rd[7].compare_data_rise3_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg ; wire \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ; wire \genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ; wire \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ; wire \genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ; wire \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ; wire \genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ; wire \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ; wire \genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ; wire \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ; wire \genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ; wire \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ; wire \genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ; wire \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ; wire \genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ; wire \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ; wire \genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ; wire \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ; wire \genblk8[0].left_edge_found_pb_reg[0]_0 ; wire \genblk8[0].left_edge_pb[0]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[1]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[2]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[3]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[4]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[5]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[5]_i_3_n_0 ; wire \genblk8[0].left_edge_pb[5]_i_5_n_0 ; wire \genblk8[0].left_edge_pb_reg_n_0_[0] ; wire \genblk8[0].left_edge_pb_reg_n_0_[1] ; wire \genblk8[0].left_edge_pb_reg_n_0_[2] ; wire \genblk8[0].left_edge_pb_reg_n_0_[3] ; wire \genblk8[0].left_edge_pb_reg_n_0_[4] ; wire \genblk8[0].left_edge_pb_reg_n_0_[5] ; wire \genblk8[0].left_edge_updated_reg[0]_0 ; wire \genblk8[0].left_loss_pb[0]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[1]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[2]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_3_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_4_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_5_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_6_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_7_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_8_n_0 ; wire \genblk8[0].left_loss_pb[4]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_10_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_11_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_12_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_13_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_15_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_16_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_17_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_18_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_20_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_21_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_22_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_23_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_24_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_25_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_26_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_27_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_28_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_29_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_2_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_30_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_31_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_7_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_8_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_9_n_0 ; wire \genblk8[0].left_loss_pb_reg[0]_0 ; wire \genblk8[0].left_loss_pb_reg[0]_1 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_3 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_5_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ; wire \genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_3 ; wire [5:2]\genblk8[0].left_loss_pb_reg__0 ; wire \genblk8[0].left_loss_pb_reg_n_0_[0] ; wire \genblk8[0].left_loss_pb_reg_n_0_[1] ; wire \genblk8[0].match_flag_pb[7]_i_1_n_0 ; wire \genblk8[0].right_edge_found_pb_reg[0]_0 ; wire \genblk8[0].right_edge_pb[1]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[2]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[3]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[4]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[5]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[5]_i_2_n_0 ; wire \genblk8[0].right_edge_pb[5]_i_3_n_0 ; wire \genblk8[0].right_edge_pb_reg[0]_0 ; wire \genblk8[0].right_edge_pb_reg[0]_1 ; wire \genblk8[0].right_edge_pb_reg_n_0_[0] ; wire \genblk8[0].right_edge_pb_reg_n_0_[1] ; wire \genblk8[0].right_edge_pb_reg_n_0_[2] ; wire \genblk8[0].right_edge_pb_reg_n_0_[3] ; wire \genblk8[0].right_edge_pb_reg_n_0_[4] ; wire \genblk8[0].right_edge_pb_reg_n_0_[5] ; wire \genblk8[0].right_gain_pb[0]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[1]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[2]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_10_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_11_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_4_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_5_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_6_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_7_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_8_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_9_n_0 ; wire \genblk8[0].right_gain_pb[4]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_11_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_12_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_13_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_14_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_15_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_16_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_17_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_18_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_19_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_20_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_23_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_24_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_25_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_26_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_27_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_28_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_2_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_30_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_31_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_32_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_33_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_35_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_36_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_37_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_38_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_3_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_40_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_41_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_42_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_43_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_44_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_45_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_46_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_47_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_48_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_49_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_50_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_52_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_53_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_54_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_55_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_56_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_57_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_58_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_59_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_60_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_61_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_62_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_8_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_9_n_0 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_3 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_3 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_6_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ; wire \genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ; wire \genblk8[0].right_gain_pb_reg[5]_i_7_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ; wire \genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ; wire [5:2]\genblk8[0].right_gain_pb_reg__0 ; wire \genblk8[0].right_gain_pb_reg_n_0_[0] ; wire \genblk8[0].right_gain_pb_reg_n_0_[1] ; wire \genblk8[1].left_edge_found_pb_reg[1]_0 ; wire \genblk8[1].left_edge_pb[11]_i_1_n_0 ; wire \genblk8[1].left_edge_pb[11]_i_3_n_0 ; wire \genblk8[1].left_edge_pb_reg_n_0_[10] ; wire \genblk8[1].left_edge_pb_reg_n_0_[11] ; wire \genblk8[1].left_edge_pb_reg_n_0_[6] ; wire \genblk8[1].left_edge_pb_reg_n_0_[7] ; wire \genblk8[1].left_edge_pb_reg_n_0_[8] ; wire \genblk8[1].left_edge_pb_reg_n_0_[9] ; wire \genblk8[1].left_edge_updated_reg[1]_0 ; wire \genblk8[1].left_loss_pb[11]_i_1_n_0 ; wire \genblk8[1].left_loss_pb_reg[6]_0 ; wire [5:2]\genblk8[1].left_loss_pb_reg__0 ; wire \genblk8[1].left_loss_pb_reg_n_0_[6] ; wire \genblk8[1].left_loss_pb_reg_n_0_[7] ; wire \genblk8[1].right_edge_found_pb_reg[1]_0 ; wire \genblk8[1].right_edge_pb[11]_i_1_n_0 ; wire \genblk8[1].right_edge_pb[11]_i_2_n_0 ; wire \genblk8[1].right_edge_pb_reg[6]_0 ; wire \genblk8[1].right_edge_pb_reg_n_0_[10] ; wire \genblk8[1].right_edge_pb_reg_n_0_[11] ; wire \genblk8[1].right_edge_pb_reg_n_0_[6] ; wire \genblk8[1].right_edge_pb_reg_n_0_[7] ; wire \genblk8[1].right_edge_pb_reg_n_0_[8] ; wire \genblk8[1].right_edge_pb_reg_n_0_[9] ; wire \genblk8[1].right_gain_pb[10]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_10_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_11_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_12_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_13_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_14_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_16_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_17_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_19_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_20_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_21_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_22_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_24_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_25_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_26_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_27_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_29_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_2_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_30_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_31_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_32_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_33_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_34_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_35_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_36_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_37_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_38_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_39_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_3_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_7_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_8_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_9_n_0 ; wire \genblk8[1].right_gain_pb[6]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[7]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[8]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_10_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_11_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_4_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_5_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_6_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_7_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_8_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_9_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_5_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ; wire \genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ; wire \genblk8[1].right_gain_pb_reg[11]_i_6_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ; wire \genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_3 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_3 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ; wire [5:2]\genblk8[1].right_gain_pb_reg__0 ; wire \genblk8[1].right_gain_pb_reg_n_0_[6] ; wire \genblk8[1].right_gain_pb_reg_n_0_[7] ; wire \genblk8[2].left_edge_found_pb_reg[2]_0 ; wire \genblk8[2].left_edge_pb[17]_i_1_n_0 ; wire \genblk8[2].left_edge_pb[17]_i_3_n_0 ; wire \genblk8[2].left_edge_pb_reg_n_0_[12] ; wire \genblk8[2].left_edge_pb_reg_n_0_[13] ; wire \genblk8[2].left_edge_pb_reg_n_0_[14] ; wire \genblk8[2].left_edge_pb_reg_n_0_[15] ; wire \genblk8[2].left_edge_pb_reg_n_0_[16] ; wire \genblk8[2].left_edge_pb_reg_n_0_[17] ; wire \genblk8[2].left_edge_updated_reg[2]_0 ; wire \genblk8[2].left_loss_pb[17]_i_1_n_0 ; wire \genblk8[2].left_loss_pb_reg[12]_0 ; wire [5:2]\genblk8[2].left_loss_pb_reg__0 ; wire \genblk8[2].left_loss_pb_reg_n_0_[12] ; wire \genblk8[2].left_loss_pb_reg_n_0_[13] ; wire \genblk8[2].right_edge_found_pb_reg[2]_0 ; wire \genblk8[2].right_edge_pb[17]_i_1_n_0 ; wire \genblk8[2].right_edge_pb[17]_i_2_n_0 ; wire \genblk8[2].right_edge_pb_reg[12]_0 ; wire \genblk8[2].right_edge_pb_reg[12]_1 ; wire \genblk8[2].right_edge_pb_reg[12]_2 ; wire \genblk8[2].right_edge_pb_reg_n_0_[12] ; wire \genblk8[2].right_edge_pb_reg_n_0_[13] ; wire \genblk8[2].right_edge_pb_reg_n_0_[14] ; wire \genblk8[2].right_edge_pb_reg_n_0_[15] ; wire \genblk8[2].right_edge_pb_reg_n_0_[16] ; wire \genblk8[2].right_edge_pb_reg_n_0_[17] ; wire \genblk8[2].right_gain_pb[12]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[13]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[14]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_10_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_11_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_4_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_5_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_6_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_7_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_8_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_9_n_0 ; wire \genblk8[2].right_gain_pb[16]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_10_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_11_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_12_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_13_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_14_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_16_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_17_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_19_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_20_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_21_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_22_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_24_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_25_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_26_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_27_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_29_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_2_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_30_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_31_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_32_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_33_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_34_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_35_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_36_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_37_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_38_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_39_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_3_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_7_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_8_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_9_n_0 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_3 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_3 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_5_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ; wire \genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ; wire \genblk8[2].right_gain_pb_reg[17]_i_6_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ; wire \genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ; wire [5:2]\genblk8[2].right_gain_pb_reg__0 ; wire \genblk8[2].right_gain_pb_reg_n_0_[12] ; wire \genblk8[2].right_gain_pb_reg_n_0_[13] ; wire \genblk8[3].left_edge_found_pb_reg[3]_0 ; wire \genblk8[3].left_edge_pb[23]_i_1_n_0 ; wire \genblk8[3].left_edge_pb[23]_i_3_n_0 ; wire \genblk8[3].left_edge_pb_reg_n_0_[18] ; wire \genblk8[3].left_edge_pb_reg_n_0_[19] ; wire \genblk8[3].left_edge_pb_reg_n_0_[20] ; wire \genblk8[3].left_edge_pb_reg_n_0_[21] ; wire \genblk8[3].left_edge_pb_reg_n_0_[22] ; wire \genblk8[3].left_edge_pb_reg_n_0_[23] ; wire \genblk8[3].left_edge_updated_reg[3]_0 ; wire \genblk8[3].left_loss_pb[23]_i_1_n_0 ; wire \genblk8[3].left_loss_pb_reg[18]_0 ; wire [5:2]\genblk8[3].left_loss_pb_reg__0 ; wire \genblk8[3].left_loss_pb_reg_n_0_[18] ; wire \genblk8[3].left_loss_pb_reg_n_0_[19] ; wire \genblk8[3].right_edge_found_pb_reg[3]_0 ; wire \genblk8[3].right_edge_pb[23]_i_1_n_0 ; wire \genblk8[3].right_edge_pb[23]_i_2_n_0 ; wire \genblk8[3].right_edge_pb_reg[18]_0 ; wire \genblk8[3].right_edge_pb_reg_n_0_[18] ; wire \genblk8[3].right_edge_pb_reg_n_0_[19] ; wire \genblk8[3].right_edge_pb_reg_n_0_[20] ; wire \genblk8[3].right_edge_pb_reg_n_0_[21] ; wire \genblk8[3].right_edge_pb_reg_n_0_[22] ; wire \genblk8[3].right_edge_pb_reg_n_0_[23] ; wire \genblk8[3].right_gain_pb[18]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[19]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[20]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_10_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_11_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_4_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_5_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_6_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_7_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_8_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_9_n_0 ; wire \genblk8[3].right_gain_pb[22]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_10_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_11_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_12_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_13_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_14_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_16_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_17_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_19_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_20_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_21_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_22_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_24_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_25_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_26_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_27_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_29_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_2_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_30_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_31_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_32_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_33_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_34_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_35_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_36_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_37_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_38_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_39_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_3_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_7_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_8_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_9_n_0 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_3 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_3 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_5_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ; wire \genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ; wire \genblk8[3].right_gain_pb_reg[23]_i_6_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ; wire \genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ; wire [5:2]\genblk8[3].right_gain_pb_reg__0 ; wire \genblk8[3].right_gain_pb_reg_n_0_[18] ; wire \genblk8[3].right_gain_pb_reg_n_0_[19] ; wire \genblk8[4].left_edge_found_pb_reg[4]_0 ; wire \genblk8[4].left_edge_pb[29]_i_1_n_0 ; wire \genblk8[4].left_edge_pb[29]_i_3_n_0 ; wire \genblk8[4].left_edge_pb_reg_n_0_[24] ; wire \genblk8[4].left_edge_pb_reg_n_0_[25] ; wire \genblk8[4].left_edge_pb_reg_n_0_[26] ; wire \genblk8[4].left_edge_pb_reg_n_0_[27] ; wire \genblk8[4].left_edge_pb_reg_n_0_[28] ; wire \genblk8[4].left_edge_pb_reg_n_0_[29] ; wire \genblk8[4].left_edge_updated_reg[4]_0 ; wire \genblk8[4].left_loss_pb[29]_i_1_n_0 ; wire \genblk8[4].left_loss_pb_reg[24]_0 ; wire [5:2]\genblk8[4].left_loss_pb_reg__0 ; wire \genblk8[4].left_loss_pb_reg_n_0_[24] ; wire \genblk8[4].left_loss_pb_reg_n_0_[25] ; wire \genblk8[4].right_edge_found_pb_reg[4]_0 ; wire \genblk8[4].right_edge_pb[29]_i_1_n_0 ; wire \genblk8[4].right_edge_pb[29]_i_2_n_0 ; wire \genblk8[4].right_edge_pb_reg[24]_0 ; wire \genblk8[4].right_edge_pb_reg_n_0_[24] ; wire \genblk8[4].right_edge_pb_reg_n_0_[25] ; wire \genblk8[4].right_edge_pb_reg_n_0_[26] ; wire \genblk8[4].right_edge_pb_reg_n_0_[27] ; wire \genblk8[4].right_edge_pb_reg_n_0_[28] ; wire \genblk8[4].right_edge_pb_reg_n_0_[29] ; wire \genblk8[4].right_gain_pb[24]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[25]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[26]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_10_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_11_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_4_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_5_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_6_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_7_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_8_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_9_n_0 ; wire \genblk8[4].right_gain_pb[28]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_10_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_11_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_12_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_13_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_14_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_16_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_17_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_19_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_20_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_21_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_22_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_24_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_25_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_26_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_27_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_29_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_2_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_30_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_31_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_32_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_33_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_34_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_35_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_36_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_37_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_38_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_39_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_3_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_7_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_8_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_9_n_0 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_3 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_3 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_5_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ; wire \genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ; wire \genblk8[4].right_gain_pb_reg[29]_i_6_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ; wire \genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ; wire [5:2]\genblk8[4].right_gain_pb_reg__0 ; wire \genblk8[4].right_gain_pb_reg_n_0_[24] ; wire \genblk8[4].right_gain_pb_reg_n_0_[25] ; wire \genblk8[5].left_edge_found_pb_reg[5]_0 ; wire \genblk8[5].left_edge_pb[35]_i_1_n_0 ; wire \genblk8[5].left_edge_pb[35]_i_3_n_0 ; wire \genblk8[5].left_edge_pb_reg_n_0_[30] ; wire \genblk8[5].left_edge_pb_reg_n_0_[31] ; wire \genblk8[5].left_edge_pb_reg_n_0_[32] ; wire \genblk8[5].left_edge_pb_reg_n_0_[33] ; wire \genblk8[5].left_edge_pb_reg_n_0_[34] ; wire \genblk8[5].left_edge_pb_reg_n_0_[35] ; wire \genblk8[5].left_edge_updated_reg[5]_0 ; wire \genblk8[5].left_loss_pb[35]_i_1_n_0 ; wire \genblk8[5].left_loss_pb_reg[30]_0 ; wire [5:2]\genblk8[5].left_loss_pb_reg__0 ; wire \genblk8[5].left_loss_pb_reg_n_0_[30] ; wire \genblk8[5].left_loss_pb_reg_n_0_[31] ; wire \genblk8[5].right_edge_found_pb_reg[5]_0 ; wire \genblk8[5].right_edge_pb[35]_i_1_n_0 ; wire \genblk8[5].right_edge_pb[35]_i_2_n_0 ; wire \genblk8[5].right_edge_pb_reg[30]_0 ; wire \genblk8[5].right_edge_pb_reg[30]_1 ; wire \genblk8[5].right_edge_pb_reg_n_0_[30] ; wire \genblk8[5].right_edge_pb_reg_n_0_[31] ; wire \genblk8[5].right_edge_pb_reg_n_0_[32] ; wire \genblk8[5].right_edge_pb_reg_n_0_[33] ; wire \genblk8[5].right_edge_pb_reg_n_0_[34] ; wire \genblk8[5].right_edge_pb_reg_n_0_[35] ; wire \genblk8[5].right_gain_pb[30]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[31]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[32]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_10_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_11_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_4_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_5_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_6_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_7_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_8_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_9_n_0 ; wire \genblk8[5].right_gain_pb[34]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_10_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_11_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_12_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_13_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_14_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_16_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_17_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_19_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_20_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_21_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_22_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_24_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_25_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_26_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_27_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_29_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_2_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_30_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_31_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_32_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_33_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_34_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_35_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_36_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_37_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_38_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_39_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_3_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_7_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_8_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_9_n_0 ; wire \genblk8[5].right_gain_pb_reg[30]_0 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_3 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_3 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_5_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ; wire \genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ; wire \genblk8[5].right_gain_pb_reg[35]_i_6_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ; wire \genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ; wire [5:2]\genblk8[5].right_gain_pb_reg__0 ; wire \genblk8[5].right_gain_pb_reg_n_0_[30] ; wire \genblk8[5].right_gain_pb_reg_n_0_[31] ; wire \genblk8[6].left_edge_found_pb_reg[6]_0 ; wire \genblk8[6].left_edge_pb[41]_i_1_n_0 ; wire \genblk8[6].left_edge_pb[41]_i_3_n_0 ; wire \genblk8[6].left_edge_pb_reg_n_0_[36] ; wire \genblk8[6].left_edge_pb_reg_n_0_[37] ; wire \genblk8[6].left_edge_pb_reg_n_0_[38] ; wire \genblk8[6].left_edge_pb_reg_n_0_[39] ; wire \genblk8[6].left_edge_pb_reg_n_0_[40] ; wire \genblk8[6].left_edge_pb_reg_n_0_[41] ; wire \genblk8[6].left_edge_updated_reg[6]_0 ; wire \genblk8[6].left_loss_pb[41]_i_1_n_0 ; wire \genblk8[6].left_loss_pb_reg[36]_0 ; wire [5:2]\genblk8[6].left_loss_pb_reg__0 ; wire \genblk8[6].left_loss_pb_reg_n_0_[36] ; wire \genblk8[6].left_loss_pb_reg_n_0_[37] ; wire \genblk8[6].right_edge_found_pb_reg[6]_0 ; wire \genblk8[6].right_edge_pb[41]_i_1_n_0 ; wire \genblk8[6].right_edge_pb[41]_i_2_n_0 ; wire \genblk8[6].right_edge_pb_reg[36]_0 ; wire \genblk8[6].right_edge_pb_reg_n_0_[36] ; wire \genblk8[6].right_edge_pb_reg_n_0_[37] ; wire \genblk8[6].right_edge_pb_reg_n_0_[38] ; wire \genblk8[6].right_edge_pb_reg_n_0_[39] ; wire \genblk8[6].right_edge_pb_reg_n_0_[40] ; wire \genblk8[6].right_edge_pb_reg_n_0_[41] ; wire \genblk8[6].right_gain_pb[36]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[37]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[38]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_10_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_11_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_4_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_5_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_6_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_7_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_8_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_9_n_0 ; wire \genblk8[6].right_gain_pb[40]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_10_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_11_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_12_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_13_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_14_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_16_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_17_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_19_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_20_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_21_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_22_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_24_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_25_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_26_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_27_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_29_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_2_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_30_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_31_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_32_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_33_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_34_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_35_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_36_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_37_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_38_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_39_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_3_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_7_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_8_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_9_n_0 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_3 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_3 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_5_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ; wire \genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ; wire \genblk8[6].right_gain_pb_reg[41]_i_6_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ; wire \genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ; wire [5:2]\genblk8[6].right_gain_pb_reg__0 ; wire \genblk8[6].right_gain_pb_reg_n_0_[36] ; wire \genblk8[6].right_gain_pb_reg_n_0_[37] ; wire \genblk8[7].left_edge_found_pb_reg[7]_0 ; wire \genblk8[7].left_edge_pb[47]_i_1_n_0 ; wire \genblk8[7].left_edge_pb[47]_i_3_n_0 ; wire \genblk8[7].left_edge_pb_reg_n_0_[42] ; wire \genblk8[7].left_edge_pb_reg_n_0_[43] ; wire \genblk8[7].left_edge_pb_reg_n_0_[44] ; wire \genblk8[7].left_edge_pb_reg_n_0_[45] ; wire \genblk8[7].left_edge_pb_reg_n_0_[46] ; wire \genblk8[7].left_edge_pb_reg_n_0_[47] ; wire \genblk8[7].left_edge_updated_reg[7]_0 ; wire \genblk8[7].left_edge_updated_reg[7]_1 ; wire \genblk8[7].left_loss_pb[47]_i_1_n_0 ; wire \genblk8[7].left_loss_pb_reg[42]_0 ; wire [5:2]\genblk8[7].left_loss_pb_reg__0 ; wire \genblk8[7].left_loss_pb_reg_n_0_[42] ; wire \genblk8[7].left_loss_pb_reg_n_0_[43] ; wire \genblk8[7].right_edge_found_pb_reg[7]_0 ; wire \genblk8[7].right_edge_pb[47]_i_1_n_0 ; wire \genblk8[7].right_edge_pb[47]_i_2_n_0 ; wire \genblk8[7].right_edge_pb_reg[42]_0 ; wire \genblk8[7].right_edge_pb_reg[42]_1 ; wire \genblk8[7].right_edge_pb_reg_n_0_[42] ; wire \genblk8[7].right_edge_pb_reg_n_0_[43] ; wire \genblk8[7].right_edge_pb_reg_n_0_[44] ; wire \genblk8[7].right_edge_pb_reg_n_0_[45] ; wire \genblk8[7].right_edge_pb_reg_n_0_[46] ; wire \genblk8[7].right_edge_pb_reg_n_0_[47] ; wire \genblk8[7].right_gain_pb[42]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[43]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[44]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_10_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_11_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_4_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_5_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_6_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_7_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_8_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_9_n_0 ; wire \genblk8[7].right_gain_pb[46]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_10_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_11_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_12_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_13_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_14_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_16_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_17_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_19_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_20_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_21_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_22_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_24_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_25_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_26_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_27_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_29_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_2_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_30_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_31_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_32_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_33_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_34_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_35_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_36_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_37_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_38_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_39_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_3_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_7_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_8_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_9_n_0 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_3 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_3 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_5_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ; wire \genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ; wire \genblk8[7].right_gain_pb_reg[47]_i_6_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ; wire \genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ; wire [5:2]\genblk8[7].right_gain_pb_reg__0 ; wire \genblk8[7].right_gain_pb_reg_n_0_[42] ; wire \genblk8[7].right_gain_pb_reg_n_0_[43] ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ; wire \genblk9[0].fine_delay_incdec_pb_reg[0]_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ; wire \genblk9[1].fine_delay_incdec_pb_reg[1]_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ; wire \genblk9[2].fine_delay_incdec_pb_reg[2]_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ; wire \genblk9[3].fine_delay_incdec_pb_reg[3]_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ; wire \genblk9[5].fine_delay_incdec_pb_reg[5]_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ; wire \genblk9[6].fine_delay_incdec_pb_reg[6]_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ; wire \genblk9[7].fine_delay_incdec_pb_reg[7]_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[1] ; wire \init_state_r_reg[1]_0 ; wire \largest_left_edge[0]_i_1_n_0 ; wire \largest_left_edge[1]_i_1_n_0 ; wire \largest_left_edge[2]_i_1_n_0 ; wire \largest_left_edge[3]_i_1_n_0 ; wire \largest_left_edge[4]_i_1_n_0 ; wire \largest_left_edge[5]_i_1_n_0 ; wire \largest_left_edge[5]_i_2_n_0 ; wire \largest_left_edge[5]_i_4_n_0 ; wire \largest_left_edge[5]_i_5_n_0 ; wire \largest_left_edge[5]_i_6_n_0 ; wire \largest_left_edge_reg[0]_0 ; wire \largest_left_edge_reg_n_0_[0] ; wire \largest_left_edge_reg_n_0_[1] ; wire \largest_left_edge_reg_n_0_[2] ; wire \largest_left_edge_reg_n_0_[3] ; wire \largest_left_edge_reg_n_0_[4] ; wire \largest_left_edge_reg_n_0_[5] ; wire left_edge_pb; wire [5:0]left_edge_ref; wire \left_edge_ref[0]_i_1_n_0 ; wire \left_edge_ref[0]_i_2_n_0 ; wire \left_edge_ref[0]_i_3_n_0 ; wire \left_edge_ref[1]_i_1_n_0 ; wire \left_edge_ref[1]_i_2_n_0 ; wire \left_edge_ref[1]_i_3_n_0 ; wire \left_edge_ref[2]_i_1_n_0 ; wire \left_edge_ref[2]_i_2_n_0 ; wire \left_edge_ref[2]_i_3_n_0 ; wire \left_edge_ref[3]_i_1_n_0 ; wire \left_edge_ref[3]_i_2_n_0 ; wire \left_edge_ref[3]_i_3_n_0 ; wire \left_edge_ref[4]_i_11_n_0 ; wire \left_edge_ref[4]_i_12_n_0 ; wire \left_edge_ref[4]_i_1_n_0 ; wire \left_edge_ref[4]_i_2_n_0 ; wire \left_edge_ref[4]_i_4_n_0 ; wire \left_edge_ref[4]_i_5_n_0 ; wire \left_edge_ref[4]_i_6_n_0 ; wire \left_edge_ref[4]_i_7_n_0 ; wire \left_edge_ref[4]_i_8_n_0 ; wire \left_edge_ref[4]_i_9_n_0 ; wire \left_edge_ref[5]_i_10_n_0 ; wire \left_edge_ref[5]_i_11_n_0 ; wire \left_edge_ref[5]_i_12_n_0 ; wire \left_edge_ref[5]_i_13_n_0 ; wire \left_edge_ref[5]_i_14_n_0 ; wire \left_edge_ref[5]_i_15_n_0 ; wire \left_edge_ref[5]_i_17_n_0 ; wire \left_edge_ref[5]_i_18_n_0 ; wire \left_edge_ref[5]_i_19_n_0 ; wire \left_edge_ref[5]_i_1_n_0 ; wire \left_edge_ref[5]_i_2_n_0 ; wire \left_edge_ref[5]_i_5_n_0 ; wire \left_edge_ref[5]_i_7_n_0 ; wire \left_edge_ref[5]_i_8_n_0 ; wire \left_edge_ref[5]_i_9_n_0 ; wire \left_edge_ref_reg[4]_i_10_n_0 ; wire \left_edge_ref_reg[4]_i_3_n_0 ; wire \left_edge_ref_reg[5]_i_16_n_0 ; wire \left_edge_ref_reg[5]_i_3_n_0 ; wire \left_edge_ref_reg[5]_i_3_n_1 ; wire \left_edge_ref_reg[5]_i_3_n_2 ; wire \left_edge_ref_reg[5]_i_3_n_3 ; wire \left_edge_ref_reg[5]_i_3_n_4 ; wire \left_edge_ref_reg[5]_i_3_n_5 ; wire \left_edge_ref_reg[5]_i_3_n_6 ; wire \left_edge_ref_reg[5]_i_3_n_7 ; wire \left_edge_ref_reg[5]_i_4_n_0 ; wire \left_edge_ref_reg[5]_i_6_n_7 ; wire match_flag_and; wire \match_flag_and[0]_i_1_n_0 ; wire \match_flag_and[1]_i_1_n_0 ; wire \match_flag_and[2]_i_1_n_0 ; wire \match_flag_and[3]_i_1_n_0 ; wire \match_flag_and[4]_i_1_n_0 ; wire \match_flag_and[5]_i_1_n_0 ; wire \match_flag_and[6]_i_1_n_0 ; wire \match_flag_and[7]_i_2_n_0 ; wire \match_flag_and[7]_i_3_n_0 ; wire \match_flag_and_reg_n_0_[0] ; wire \match_flag_and_reg_n_0_[1] ; wire \match_flag_and_reg_n_0_[2] ; wire \match_flag_and_reg_n_0_[3] ; wire \match_flag_and_reg_n_0_[4] ; wire \match_flag_and_reg_n_0_[5] ; wire \match_flag_and_reg_n_0_[6] ; wire \match_flag_and_reg_n_0_[7] ; wire \match_flag_or[0]_i_1_n_0 ; wire \match_flag_or[1]_i_1_n_0 ; wire \match_flag_or[2]_i_1_n_0 ; wire \match_flag_or[3]_i_1_n_0 ; wire \match_flag_or[4]_i_1_n_0 ; wire \match_flag_or[5]_i_1_n_0 ; wire \match_flag_or[6]_i_1_n_0 ; wire \match_flag_or_reg[0]_0 ; wire [63:0]match_flag_pb; wire mux_rd_fall0_r1; wire mux_rd_fall0_r2; wire mux_rd_fall1_r1; wire mux_rd_fall1_r2; wire mux_rd_fall2_r1; wire mux_rd_fall2_r2; wire mux_rd_fall3_r1; wire mux_rd_fall3_r2; wire mux_rd_rise0_r1; wire mux_rd_rise0_r2; wire mux_rd_rise1_r1; wire mux_rd_rise1_r2; wire mux_rd_rise2_r1; wire mux_rd_rise2_r2; wire mux_rd_rise3_r1; wire mux_rd_rise3_r2; wire mux_rd_valid_r; wire new_cnt_dqs_r; wire new_cnt_dqs_r_reg_0; wire new_cnt_dqs_r_reg_1; wire no_err_win_detected_i_1_n_0; wire no_err_win_detected_i_2_n_0; wire no_err_win_detected_i_3_n_0; wire no_err_win_detected_latch_reg_0; wire no_err_win_detected_latch_reg_1; wire no_err_win_detected_reg_0; wire no_err_win_detected_reg_1; wire \num_refresh_reg[1] ; wire num_samples_done_ind_reg_0; wire num_samples_done_r; wire ocal_last_byte_done; wire oclkdelay_center_calib_done_r_reg; wire \oclkdelay_ref_cnt_reg[0] ; wire \one_rank.stg1_wr_done_reg ; wire [3:0]p_0_in; wire [7:0]p_0_in__0; wire p_103_out; wire p_106_out; wire p_10_out; wire p_119_out; wire p_122_out; wire p_127_out; wire p_130_out; wire p_143_out; wire p_146_out; wire p_154_out; wire p_19_out; wire p_1_in159_in; wire p_28_out; wire p_37_out; wire [0:0]p_3_in; wire p_46_out; wire p_55_out; wire p_64_out; wire p_66_out; wire p_75_out; wire p_95_out; wire p_98_out; wire [3:0]\pi_counter_read_val_reg[5] ; wire pi_en_stg2_f_timing; wire pi_en_stg2_f_timing_reg_0; wire pi_stg2_f_incdec_timing; wire [5:0]prbs_dec_tap_cnt; wire \prbs_dec_tap_cnt[0]_i_1_n_0 ; wire \prbs_dec_tap_cnt[1]_i_1_n_0 ; wire \prbs_dec_tap_cnt[2]_i_1_n_0 ; wire \prbs_dec_tap_cnt[2]_i_2_n_0 ; wire \prbs_dec_tap_cnt[2]_i_3_n_0 ; wire \prbs_dec_tap_cnt[2]_i_4_n_0 ; wire \prbs_dec_tap_cnt[3]_i_1_n_0 ; wire \prbs_dec_tap_cnt[3]_i_2_n_0 ; wire \prbs_dec_tap_cnt[4]_i_2_n_0 ; wire \prbs_dec_tap_cnt[4]_i_3_n_0 ; wire \prbs_dec_tap_cnt[5]_i_1_n_0 ; wire \prbs_dec_tap_cnt[5]_i_4_n_0 ; wire \prbs_dec_tap_cnt[5]_i_5_n_0 ; wire [1:0]\prbs_dec_tap_cnt_reg[1]_0 ; wire \prbs_dec_tap_cnt_reg[4]_i_1_n_0 ; wire \prbs_dec_tap_cnt_reg[5]_i_2_n_0 ; wire \prbs_dqs_cnt_r_reg[0]_0 ; wire \prbs_dqs_cnt_r_reg[0]_1 ; wire \prbs_dqs_cnt_r_reg[0]_2 ; wire \prbs_dqs_cnt_r_reg[1]_0 ; wire \prbs_dqs_cnt_r_reg[2]_0 ; wire \prbs_dqs_tap_cnt_r[0]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[1]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[2]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_i_2_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_i_3_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[4]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[4]_i_2_n_0 ; wire \prbs_dqs_tap_cnt_r[4]_i_3_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_2_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_3_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_4_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_5_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[0] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[1] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[2] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[3] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[4] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[5] ; wire prbs_dqs_tap_limit_r; wire prbs_found_1st_edge_r_i_5_n_0; wire prbs_found_1st_edge_r_reg_0; wire prbs_found_1st_edge_r_reg_1; wire \prbs_inc_tap_cnt[0]_i_1_n_0 ; wire \prbs_inc_tap_cnt[1]_i_1_n_0 ; wire \prbs_inc_tap_cnt[1]_i_2_n_0 ; wire \prbs_inc_tap_cnt[2]_i_1_n_0 ; wire \prbs_inc_tap_cnt[2]_i_2_n_0 ; wire \prbs_inc_tap_cnt[2]_i_3_n_0 ; wire \prbs_inc_tap_cnt[3]_i_1_n_0 ; wire \prbs_inc_tap_cnt[3]_i_2_n_0 ; wire \prbs_inc_tap_cnt[3]_i_3_n_0 ; wire \prbs_inc_tap_cnt[3]_i_4_n_0 ; wire \prbs_inc_tap_cnt[4]_i_1_n_0 ; wire \prbs_inc_tap_cnt[4]_i_2_n_0 ; wire \prbs_inc_tap_cnt[5]_i_1_n_0 ; wire \prbs_inc_tap_cnt[5]_i_2_n_0 ; wire \prbs_inc_tap_cnt[5]_i_3_n_0 ; wire \prbs_inc_tap_cnt[5]_i_4_n_0 ; wire \prbs_inc_tap_cnt[5]_i_5_n_0 ; wire \prbs_inc_tap_cnt[5]_i_6_n_0 ; wire \prbs_inc_tap_cnt[5]_i_7_n_0 ; wire \prbs_inc_tap_cnt[5]_i_8_n_0 ; wire \prbs_inc_tap_cnt[5]_i_9_n_0 ; wire \prbs_inc_tap_cnt_reg_n_0_[0] ; wire \prbs_inc_tap_cnt_reg_n_0_[1] ; wire \prbs_inc_tap_cnt_reg_n_0_[2] ; wire \prbs_inc_tap_cnt_reg_n_0_[3] ; wire \prbs_inc_tap_cnt_reg_n_0_[4] ; wire \prbs_inc_tap_cnt_reg_n_0_[5] ; wire prbs_last_byte_done; wire prbs_last_byte_done_reg_0; wire prbs_pi_stg2_f_en; wire prbs_pi_stg2_f_incdec; wire prbs_prech_req_r; wire prbs_rdlvl_done_pulse0; wire prbs_rdlvl_done_r1; wire prbs_rdlvl_done_reg_0; wire prbs_rdlvl_done_reg_1; wire prbs_rdlvl_start_r; wire prbs_rdlvl_start_reg; wire prbs_rdlvl_start_reg_0; wire prbs_state_r1; wire prbs_state_r178_out; wire \prbs_state_r[0]_i_1_n_0 ; wire \prbs_state_r[0]_i_2_n_0 ; wire \prbs_state_r[0]_i_3_n_0 ; wire \prbs_state_r[0]_i_4_n_0 ; wire \prbs_state_r[0]_i_5_n_0 ; wire \prbs_state_r[1]_i_1_n_0 ; wire \prbs_state_r[1]_i_2_n_0 ; wire \prbs_state_r[1]_i_3_n_0 ; wire \prbs_state_r[1]_i_4_n_0 ; wire \prbs_state_r[1]_i_5_n_0 ; wire \prbs_state_r[1]_i_6_n_0 ; wire \prbs_state_r[2]_i_10_n_0 ; wire \prbs_state_r[2]_i_11_n_0 ; wire \prbs_state_r[2]_i_2_n_0 ; wire \prbs_state_r[2]_i_3_n_0 ; wire \prbs_state_r[2]_i_4_n_0 ; wire \prbs_state_r[2]_i_6_n_0 ; wire \prbs_state_r[2]_i_7_n_0 ; wire \prbs_state_r[2]_i_8_n_0 ; wire \prbs_state_r[2]_i_9_n_0 ; wire \prbs_state_r[3]_i_1_n_0 ; wire \prbs_state_r[3]_i_2_n_0 ; wire \prbs_state_r[3]_i_3_n_0 ; wire \prbs_state_r[3]_i_4_n_0 ; wire \prbs_state_r[4]_i_11_n_0 ; wire \prbs_state_r[4]_i_2_n_0 ; wire \prbs_state_r[4]_i_3_n_0 ; wire \prbs_state_r[4]_i_4_n_0 ; wire \prbs_state_r[4]_i_5_n_0 ; wire \prbs_state_r[4]_i_6_n_0 ; wire \prbs_state_r[4]_i_7_n_0 ; wire \prbs_state_r[4]_i_8_n_0 ; wire \prbs_state_r[4]_i_9_n_0 ; wire \prbs_state_r_reg[0]_0 ; wire \prbs_state_r_reg[0]_1 ; wire \prbs_state_r_reg[0]_2 ; wire \prbs_state_r_reg[0]_3 ; wire \prbs_state_r_reg[0]_4 ; wire \prbs_state_r_reg[2]_i_1_n_0 ; wire \prbs_state_r_reg[3]_0 ; wire \prbs_state_r_reg[3]_1 ; wire \prbs_state_r_reg[4]_0 ; wire \prbs_state_r_reg[4]_1 ; wire \prbs_state_r_reg[4]_2 ; wire \prbs_state_r_reg[4]_3 ; wire prbs_tap_en_r; wire prbs_tap_en_r_reg_0; wire prbs_tap_inc_r; wire prbs_tap_inc_r_i_3_n_0; wire prbs_tap_inc_r_reg_0; wire prech_done; wire prech_done_reg; wire prech_req_r_reg; wire rd_valid_r1; wire rd_valid_r2_reg_n_0; wire \rd_victim_sel[0]_i_1_n_0 ; wire \rd_victim_sel[1]_i_1_n_0 ; wire \rd_victim_sel[2]_i_1_n_0 ; wire \rd_victim_sel_reg[2]_0 ; wire \rd_victim_sel_reg[2]_1 ; wire \rd_victim_sel_reg[2]_2 ; wire \rd_victim_sel_reg[2]_3 ; wire [5:0]rdlvl_cpt_tap_cnt; wire \rdlvl_cpt_tap_cnt_reg[5]_0 ; wire [2:0]\rdlvl_cpt_tap_cnt_reg[5]_1 ; wire rdlvl_last_byte_done; wire rdlvl_stg1_done_int_reg; wire rdlvl_stg1_start_int; wire [7:3]ref_bit; wire \ref_bit[7]_i_3_n_0 ; wire \ref_bit[7]_i_4_n_0 ; wire \ref_bit[7]_i_5_n_0 ; wire \ref_bit[7]_i_6_n_0 ; wire ref_bit_per_bit; wire ref_bit_per_bit0; wire \ref_bit_per_bit[7]_i_2_n_0 ; wire \ref_bit_per_bit[7]_i_3_n_0 ; wire \ref_bit_per_bit_reg_n_0_[0] ; wire \ref_bit_per_bit_reg_n_0_[1] ; wire \ref_bit_per_bit_reg_n_0_[2] ; wire \ref_bit_per_bit_reg_n_0_[3] ; wire \ref_bit_per_bit_reg_n_0_[4] ; wire \ref_bit_per_bit_reg_n_0_[5] ; wire \ref_bit_per_bit_reg_n_0_[6] ; wire \ref_bit_per_bit_reg_n_0_[7] ; wire \ref_bit_reg_n_0_[0] ; wire \ref_bit_reg_n_0_[1] ; wire \ref_bit_reg_n_0_[2] ; wire ref_right_edge; wire ref_right_edge125_in; wire \ref_right_edge[0]_i_1_n_0 ; wire \ref_right_edge[0]_i_3_n_0 ; wire \ref_right_edge[0]_i_4_n_0 ; wire \ref_right_edge[1]_i_1_n_0 ; wire \ref_right_edge[1]_i_3_n_0 ; wire \ref_right_edge[1]_i_4_n_0 ; wire \ref_right_edge[1]_i_5_n_0 ; wire \ref_right_edge[1]_i_6_n_0 ; wire \ref_right_edge[2]_i_1_n_0 ; wire \ref_right_edge[2]_i_2_n_0 ; wire \ref_right_edge[2]_i_3_n_0 ; wire \ref_right_edge[3]_i_1_n_0 ; wire \ref_right_edge[3]_i_2_n_0 ; wire \ref_right_edge[3]_i_3_n_0 ; wire \ref_right_edge[4]_i_10_n_0 ; wire \ref_right_edge[4]_i_11_n_0 ; wire \ref_right_edge[4]_i_1_n_0 ; wire \ref_right_edge[4]_i_2_n_0 ; wire \ref_right_edge[4]_i_4_n_0 ; wire \ref_right_edge[4]_i_5_n_0 ; wire \ref_right_edge[4]_i_6_n_0 ; wire \ref_right_edge[4]_i_7_n_0 ; wire \ref_right_edge[4]_i_8_n_0 ; wire \ref_right_edge[4]_i_9_n_0 ; wire \ref_right_edge[5]_i_10_n_0 ; wire \ref_right_edge[5]_i_11_n_0 ; wire \ref_right_edge[5]_i_12_n_0 ; wire \ref_right_edge[5]_i_13_n_0 ; wire \ref_right_edge[5]_i_14_n_0 ; wire \ref_right_edge[5]_i_15_n_0 ; wire \ref_right_edge[5]_i_16_n_0 ; wire \ref_right_edge[5]_i_1_n_0 ; wire \ref_right_edge[5]_i_2_n_0 ; wire \ref_right_edge[5]_i_5_n_0 ; wire \ref_right_edge[5]_i_7_n_0 ; wire \ref_right_edge[5]_i_8_n_0 ; wire \ref_right_edge[5]_i_9_n_0 ; wire \ref_right_edge_reg[0]_i_2_n_0 ; wire \ref_right_edge_reg[1]_i_2_n_0 ; wire \ref_right_edge_reg[4]_i_3_n_0 ; wire \ref_right_edge_reg[5]_i_3_n_0 ; wire \ref_right_edge_reg[5]_i_3_n_1 ; wire \ref_right_edge_reg[5]_i_3_n_2 ; wire \ref_right_edge_reg[5]_i_3_n_3 ; wire \ref_right_edge_reg[5]_i_3_n_4 ; wire \ref_right_edge_reg[5]_i_3_n_5 ; wire \ref_right_edge_reg[5]_i_3_n_6 ; wire \ref_right_edge_reg[5]_i_3_n_7 ; wire \ref_right_edge_reg[5]_i_4_n_0 ; wire \ref_right_edge_reg[5]_i_6_n_7 ; wire \ref_right_edge_reg_n_0_[0] ; wire \ref_right_edge_reg_n_0_[1] ; wire \ref_right_edge_reg_n_0_[2] ; wire \ref_right_edge_reg_n_0_[3] ; wire \ref_right_edge_reg_n_0_[4] ; wire \ref_right_edge_reg_n_0_[5] ; wire reset_rd_addr; wire reset_rd_addr0; wire right_edge_found; wire right_edge_found_i_4_n_0; wire right_edge_found_i_5_n_0; wire right_edge_found_reg_0; wire right_edge_found_reg_1; wire [5:0]right_edge_ref; wire \right_edge_ref[0]_i_1_n_0 ; wire \right_edge_ref[0]_i_2_n_0 ; wire \right_edge_ref[0]_i_3_n_0 ; wire \right_edge_ref[1]_i_1_n_0 ; wire \right_edge_ref[1]_i_2_n_0 ; wire \right_edge_ref[1]_i_3_n_0 ; wire \right_edge_ref[2]_i_1_n_0 ; wire \right_edge_ref[2]_i_2_n_0 ; wire \right_edge_ref[2]_i_3_n_0 ; wire \right_edge_ref[3]_i_1_n_0 ; wire \right_edge_ref[3]_i_2_n_0 ; wire \right_edge_ref[3]_i_3_n_0 ; wire \right_edge_ref[4]_i_11_n_0 ; wire \right_edge_ref[4]_i_12_n_0 ; wire \right_edge_ref[4]_i_1_n_0 ; wire \right_edge_ref[4]_i_2_n_0 ; wire \right_edge_ref[4]_i_4_n_0 ; wire \right_edge_ref[4]_i_5_n_0 ; wire \right_edge_ref[4]_i_6_n_0 ; wire \right_edge_ref[4]_i_7_n_0 ; wire \right_edge_ref[4]_i_8_n_0 ; wire \right_edge_ref[4]_i_9_n_0 ; wire \right_edge_ref[5]_i_11_n_0 ; wire \right_edge_ref[5]_i_12_n_0 ; wire \right_edge_ref[5]_i_1_n_0 ; wire \right_edge_ref[5]_i_2_n_0 ; wire \right_edge_ref[5]_i_4_n_0 ; wire \right_edge_ref[5]_i_5_n_0 ; wire \right_edge_ref[5]_i_6_n_0 ; wire \right_edge_ref[5]_i_7_n_0 ; wire \right_edge_ref[5]_i_8_n_0 ; wire \right_edge_ref[5]_i_9_n_0 ; wire \right_edge_ref_reg[4]_i_10_n_0 ; wire \right_edge_ref_reg[4]_i_3_n_0 ; wire \right_edge_ref_reg[5]_i_10_n_0 ; wire \right_edge_ref_reg[5]_i_3_n_0 ; wire right_gain_pb; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire [0:0]rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire \samples_cnt_r[0]_i_1_n_0 ; wire \samples_cnt_r[0]_i_2_n_0 ; wire \samples_cnt_r[0]_i_3_n_0 ; wire \samples_cnt_r[10]_i_1_n_0 ; wire \samples_cnt_r[11]_i_2_n_0 ; wire \samples_cnt_r[11]_i_5_n_0 ; wire \samples_cnt_r[11]_i_6_n_0 ; wire \samples_cnt_r[11]_i_7_n_0 ; wire \samples_cnt_r[1]_i_1_n_0 ; wire \samples_cnt_r[2]_i_1_n_0 ; wire \samples_cnt_r[3]_i_1_n_0 ; wire \samples_cnt_r[4]_i_1_n_0 ; wire \samples_cnt_r[4]_i_3_n_0 ; wire \samples_cnt_r[4]_i_4_n_0 ; wire \samples_cnt_r[4]_i_5_n_0 ; wire \samples_cnt_r[4]_i_6_n_0 ; wire \samples_cnt_r[5]_i_1_n_0 ; wire \samples_cnt_r[6]_i_1_n_0 ; wire \samples_cnt_r[7]_i_1_n_0 ; wire \samples_cnt_r[8]_i_1_n_0 ; wire \samples_cnt_r[8]_i_3_n_0 ; wire \samples_cnt_r[8]_i_4_n_0 ; wire \samples_cnt_r[8]_i_5_n_0 ; wire \samples_cnt_r[8]_i_6_n_0 ; wire \samples_cnt_r[9]_i_1_n_0 ; wire \samples_cnt_r_reg[11]_i_4_n_2 ; wire \samples_cnt_r_reg[11]_i_4_n_3 ; wire \samples_cnt_r_reg[4]_i_2_n_0 ; wire \samples_cnt_r_reg[4]_i_2_n_1 ; wire \samples_cnt_r_reg[4]_i_2_n_2 ; wire \samples_cnt_r_reg[4]_i_2_n_3 ; wire \samples_cnt_r_reg[8]_i_2_n_0 ; wire \samples_cnt_r_reg[8]_i_2_n_1 ; wire \samples_cnt_r_reg[8]_i_2_n_2 ; wire \samples_cnt_r_reg[8]_i_2_n_3 ; wire \samples_cnt_r_reg_n_0_[0] ; wire \samples_cnt_r_reg_n_0_[10] ; wire \samples_cnt_r_reg_n_0_[11] ; wire \samples_cnt_r_reg_n_0_[1] ; wire \samples_cnt_r_reg_n_0_[2] ; wire \samples_cnt_r_reg_n_0_[3] ; wire \samples_cnt_r_reg_n_0_[4] ; wire \samples_cnt_r_reg_n_0_[5] ; wire \samples_cnt_r_reg_n_0_[6] ; wire \samples_cnt_r_reg_n_0_[7] ; wire \samples_cnt_r_reg_n_0_[8] ; wire \samples_cnt_r_reg_n_0_[9] ; wire [7:0]sel0; wire smallest_right_edge; wire \smallest_right_edge[0]_i_1_n_0 ; wire \smallest_right_edge[1]_i_1_n_0 ; wire \smallest_right_edge[2]_i_1_n_0 ; wire \smallest_right_edge[3]_i_1_n_0 ; wire \smallest_right_edge[4]_i_1_n_0 ; wire \smallest_right_edge[5]_i_2_n_0 ; wire \smallest_right_edge[5]_i_3_n_0 ; wire \smallest_right_edge[5]_i_4_n_0 ; wire \smallest_right_edge_reg_n_0_[0] ; wire \smallest_right_edge_reg_n_0_[1] ; wire \smallest_right_edge_reg_n_0_[2] ; wire \smallest_right_edge_reg_n_0_[3] ; wire \smallest_right_edge_reg_n_0_[4] ; wire \smallest_right_edge_reg_n_0_[5] ; wire \stage_cnt[0]_i_1_n_0 ; wire \stage_cnt[1]_i_1_n_0 ; wire \stage_cnt[1]_i_2_n_0 ; wire \stage_cnt_reg[1]_0 ; wire \stage_cnt_reg_n_0_[0] ; wire \stg1_wr_rd_cnt_reg[3] ; wire \victim_not_fixed.num_samples_done_r_i_1_n_0 ; wire \victim_not_fixed.num_samples_done_r_i_2_n_0 ; wire wait_state_cnt_en_r; wire wait_state_cnt_en_r0; wire \wait_state_cnt_r[2]_i_1_n_0 ; wire \wait_state_cnt_r[3]_i_1_n_0 ; wire [3:0]wait_state_cnt_r_reg__0; wire wrcal_done_reg; wire wrlvl_final_mux; wire [3:1]\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED ; wire [3:2]\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED ; wire [3:1]\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED ; wire [3:1]\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED ; wire [3:2]\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED ; wire [3:3]\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED ; FDRE #( .INIT(1'b0)) \A[0] (.C(CLK), .CE(1'b1), .D(\A[0]_0 ), .Q(A[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \A[1] (.C(CLK), .CE(1'b1), .D(\A[1]_0 ), .Q(A[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT1 #( .INIT(2'h1)) \bit_cnt[0]_i_1 (.I0(bit_cnt_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT2 #( .INIT(4'h6)) \bit_cnt[1]_i_1 (.I0(bit_cnt_reg__0[0]), .I1(bit_cnt_reg__0[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'h78)) \bit_cnt[2]_i_1 (.I0(bit_cnt_reg__0[0]), .I1(bit_cnt_reg__0[1]), .I2(bit_cnt_reg__0[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT4 #( .INIT(16'h7F80)) \bit_cnt[3]_i_1 (.I0(bit_cnt_reg__0[1]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[2]), .I3(bit_cnt_reg__0[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( .INIT(32'h7FFF8000)) \bit_cnt[4]_i_1 (.I0(bit_cnt_reg__0[2]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[1]), .I3(bit_cnt_reg__0[3]), .I4(bit_cnt_reg__0[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \bit_cnt[5]_i_1 (.I0(bit_cnt_reg__0[3]), .I1(bit_cnt_reg__0[1]), .I2(bit_cnt_reg__0[0]), .I3(bit_cnt_reg__0[2]), .I4(bit_cnt_reg__0[4]), .I5(bit_cnt_reg__0[5]), .O(p_0_in__0[5])); LUT2 #( .INIT(4'h6)) \bit_cnt[6]_i_1 (.I0(\bit_cnt[7]_i_4_n_0 ), .I1(bit_cnt_reg__0[6]), .O(p_0_in__0[6])); LUT6 #( .INIT(64'h0000000000000100)) \bit_cnt[7]_i_1 (.I0(bit_cnt_reg__0[6]), .I1(bit_cnt_reg__0[7]), .I2(\ref_bit_per_bit[7]_i_2_n_0 ), .I3(\bit_cnt[7]_i_3_n_0 ), .I4(bit_cnt_reg__0[5]), .I5(bit_cnt_reg__0[4]), .O(bit_cnt0)); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'h78)) \bit_cnt[7]_i_2 (.I0(\bit_cnt[7]_i_4_n_0 ), .I1(bit_cnt_reg__0[6]), .I2(bit_cnt_reg__0[7]), .O(p_0_in__0[7])); LUT6 #( .INIT(64'h0000000000000800)) \bit_cnt[7]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[4]), .I4(Q[3]), .I5(bit_cnt_reg__0[3]), .O(\bit_cnt[7]_i_3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \bit_cnt[7]_i_4 (.I0(bit_cnt_reg__0[5]), .I1(bit_cnt_reg__0[3]), .I2(bit_cnt_reg__0[1]), .I3(bit_cnt_reg__0[0]), .I4(bit_cnt_reg__0[2]), .I5(bit_cnt_reg__0[4]), .O(\bit_cnt[7]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[0] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[0]), .Q(bit_cnt_reg__0[0]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[1] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[1]), .Q(bit_cnt_reg__0[1]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[2] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[2]), .Q(bit_cnt_reg__0[2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[3] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[3]), .Q(bit_cnt_reg__0[3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[4] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[4]), .Q(bit_cnt_reg__0[4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[5] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[5]), .Q(bit_cnt_reg__0[5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[6] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[6]), .Q(bit_cnt_reg__0[6]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \bit_cnt_reg[7] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[7]), .Q(bit_cnt_reg__0[7]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f0_i_1 (.I0(\gen_mux_rd[7].compare_data_fall0_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ), .I4(\cmp_err_4to1.compare_err_f0_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f0_i_3_n_0 ), .O(compare_err_f00)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f0_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall0_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ), .O(\cmp_err_4to1.compare_err_f0_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f0_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall0_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ), .O(\cmp_err_4to1.compare_err_f0_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_f0_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f00), .Q(\cmp_err_4to1.compare_err_f0_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f1_i_1 (.I0(\gen_mux_rd[7].compare_data_fall1_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ), .I4(\cmp_err_4to1.compare_err_f1_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f1_i_3_n_0 ), .O(compare_err_f10)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f1_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall1_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ), .O(\cmp_err_4to1.compare_err_f1_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f1_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall1_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ), .O(\cmp_err_4to1.compare_err_f1_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_f1_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f10), .Q(\cmp_err_4to1.compare_err_f1_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f2_i_1 (.I0(\gen_mux_rd[7].compare_data_fall2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ), .I4(\cmp_err_4to1.compare_err_f2_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f2_i_3_n_0 ), .O(compare_err_f20)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f2_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall2_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ), .O(\cmp_err_4to1.compare_err_f2_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f2_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall2_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ), .O(\cmp_err_4to1.compare_err_f2_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_f2_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f20), .Q(\cmp_err_4to1.compare_err_f2_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f3_i_1 (.I0(\gen_mux_rd[7].compare_data_fall3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ), .I4(\cmp_err_4to1.compare_err_f3_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f3_i_3_n_0 ), .O(compare_err_f30)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f3_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall3_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ), .O(\cmp_err_4to1.compare_err_f3_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f3_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall3_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ), .O(\cmp_err_4to1.compare_err_f3_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_f3_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f30), .Q(\cmp_err_4to1.compare_err_f3_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hAAAAAAAEAAAAAEAA)) \cmp_err_4to1.compare_err_i_1 (.I0(compare_err2), .I1(Q[0]), .I2(Q[4]), .I3(Q[1]), .I4(Q[3]), .I5(Q[2]), .O(compare_err0)); LUT5 #( .INIT(32'hFFFFFFFE)) \cmp_err_4to1.compare_err_i_2 (.I0(\cmp_err_4to1.compare_err_r0_reg_n_0 ), .I1(\cmp_err_4to1.compare_err_f2_reg_n_0 ), .I2(\cmp_err_4to1.compare_err_r2_reg_n_0 ), .I3(\cmp_err_4to1.compare_err_r3_reg_n_0 ), .I4(\cmp_err_4to1.compare_err_i_4_n_0 ), .O(compare_err086_out__0)); LUT2 #( .INIT(4'hE)) \cmp_err_4to1.compare_err_i_3 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I1(rstdiv0_sync_r1_reg_rep__22), .O(compare_err2)); LUT4 #( .INIT(16'hFFFE)) \cmp_err_4to1.compare_err_i_4 (.I0(\cmp_err_4to1.compare_err_r1_reg_n_0 ), .I1(\cmp_err_4to1.compare_err_f1_reg_n_0 ), .I2(\cmp_err_4to1.compare_err_f3_reg_n_0 ), .I3(\cmp_err_4to1.compare_err_f0_reg_n_0 ), .O(\cmp_err_4to1.compare_err_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r0_i_1 (.I0(\gen_mux_rd[7].compare_data_rise0_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ), .I4(\cmp_err_4to1.compare_err_r0_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r0_i_3_n_0 ), .O(compare_err_r00)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r0_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise0_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ), .O(\cmp_err_4to1.compare_err_r0_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r0_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise0_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ), .O(\cmp_err_4to1.compare_err_r0_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_r0_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r00), .Q(\cmp_err_4to1.compare_err_r0_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r1_i_1 (.I0(\gen_mux_rd[7].compare_data_rise1_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ), .I4(\cmp_err_4to1.compare_err_r1_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r1_i_3_n_0 ), .O(compare_err_r10)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r1_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise1_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ), .O(\cmp_err_4to1.compare_err_r1_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r1_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise1_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ), .O(\cmp_err_4to1.compare_err_r1_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_r1_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r10), .Q(\cmp_err_4to1.compare_err_r1_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r2_i_1 (.I0(\gen_mux_rd[7].compare_data_rise2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ), .I4(\cmp_err_4to1.compare_err_r2_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r2_i_3_n_0 ), .O(compare_err_r20)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r2_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise2_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ), .O(\cmp_err_4to1.compare_err_r2_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r2_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise2_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ), .O(\cmp_err_4to1.compare_err_r2_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_r2_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r20), .Q(\cmp_err_4to1.compare_err_r2_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r3_i_1 (.I0(\gen_mux_rd[7].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ), .I4(\cmp_err_4to1.compare_err_r3_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r3_i_3_n_0 ), .O(compare_err_r30)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r3_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise3_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ), .O(\cmp_err_4to1.compare_err_r3_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r3_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise3_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ), .O(\cmp_err_4to1.compare_err_r3_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_r3_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r30), .Q(\cmp_err_4to1.compare_err_r3_reg_n_0 ), .R(compare_err0)); FDRE #( .INIT(1'b0)) \cmp_err_4to1.compare_err_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err086_out__0), .Q(\cmp_err_4to1.compare_err_reg_n_0 ), .R(compare_err0)); LUT5 #( .INIT(32'hFFFFFFEA)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_1 (.I0(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ), .I1(compare_err_pb_and2), .I2(err_chk_invalid), .I3(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I4(rstdiv0_sync_r1_reg_rep__22), .O(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_2 (.I0(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ), .I1(\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[0].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ), .I4(\gen_mux_rd[0].compare_data_rise3_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ), .O(p_75_out)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'h4000)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(Q[0]), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( .INIT(32'h04000010)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[3]), .I4(Q[2]), .O(compare_err_pb_and2)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall0_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ), .I3(\gen_mux_rd[0].compare_data_rise1_r1_reg ), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6 (.I0(\gen_mux_rd[0].compare_data_rise2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ), .I2(\gen_mux_rd[0].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[0].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[0].compare_err_pb_reg[0] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_75_out), .Q(compare_err_pb[0]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_1 (.I0(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[1].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ), .O(p_64_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2 (.I0(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[1].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[1].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3 (.I0(\gen_mux_rd[1].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[1].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4 (.I0(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[1].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[1].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[1].compare_err_pb_reg[1] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_64_out), .Q(compare_err_pb[1]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_1 (.I0(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[2].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[2].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ), .O(p_55_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2 (.I0(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[2].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[2].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3 (.I0(\gen_mux_rd[2].compare_data_fall3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ), .I2(\gen_mux_rd[2].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4 (.I0(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[2].compare_data_rise0_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ), .I3(\gen_mux_rd[2].compare_data_rise3_r1_reg ), .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[2].compare_err_pb_reg[2] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_55_out), .Q(compare_err_pb[2]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_1 (.I0(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[3].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[3].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ), .O(p_46_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[3].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3 (.I0(\gen_mux_rd[3].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[3].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[3].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[3].compare_err_pb_reg[3] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_46_out), .Q(compare_err_pb[3]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_1 (.I0(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[4].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ), .O(p_37_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2 (.I0(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[4].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[4].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3 (.I0(\gen_mux_rd[4].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[4].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4 (.I0(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[4].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[4].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[4].compare_err_pb_reg[4] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_37_out), .Q(compare_err_pb[4]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_1 (.I0(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[5].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[5].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ), .O(p_28_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2 (.I0(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[5].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[5].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3 (.I0(\gen_mux_rd[5].compare_data_fall3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ), .I2(\gen_mux_rd[5].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4 (.I0(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[5].compare_data_rise0_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ), .I3(\gen_mux_rd[5].compare_data_fall2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[5].compare_err_pb_reg[5] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_28_out), .Q(compare_err_pb[5]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_1 (.I0(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[6].compare_data_fall1_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ), .O(p_19_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2 (.I0(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[6].compare_data_rise3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ), .I3(\gen_mux_rd[6].compare_data_fall3_r1_reg ), .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3 (.I0(\gen_mux_rd[6].compare_data_fall0_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4 (.I0(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ), .I1(\gen_mux_rd[6].compare_data_rise2_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[6].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[6].compare_err_pb_reg[6] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_19_out), .Q(compare_err_pb[6]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_1 (.I0(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[7].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[7].compare_data_fall1_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ), .O(p_10_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2 (.I0(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[7].compare_data_rise3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ), .I3(\gen_mux_rd[7].compare_data_fall0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3 (.I0(\gen_mux_rd[7].compare_data_fall2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[7].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4 (.I0(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[7].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[7].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cmp_err_pb_4to1.(null)[7].compare_err_pb_reg[7] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_10_out), .Q(compare_err_pb[7]), .R(p_66_out)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT5 #( .INIT(32'h80000000)) cnt_wait_state_i_1 (.I0(wait_state_cnt_en_r), .I1(wait_state_cnt_r_reg__0[3]), .I2(wait_state_cnt_r_reg__0[2]), .I3(wait_state_cnt_r_reg__0[0]), .I4(wait_state_cnt_r_reg__0[1]), .O(cnt_wait_state_i_1_n_0)); FDRE #( .INIT(1'b0)) cnt_wait_state_reg (.C(CLK), .CE(1'b1), .D(cnt_wait_state_i_1_n_0), .Q(cnt_wait_state), .R(1'b0)); LUT6 #( .INIT(64'hAAAAABAAAAAAAAAA)) compare_err_latch_i_1 (.I0(compare_err_latch_i_2_n_0), .I1(compare_err_latch_reg_0), .I2(Q[2]), .I3(\cmp_err_4to1.compare_err_reg_n_0 ), .I4(Q[0]), .I5(Q[1]), .O(compare_err_latch_i_1_n_0)); LUT6 #( .INIT(64'h0000000200000000)) compare_err_latch_i_2 (.I0(compare_err_latch_reg_n_0), .I1(Q[2]), .I2(Q[3]), .I3(Q[0]), .I4(Q[4]), .I5(Q[1]), .O(compare_err_latch_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'hE)) compare_err_latch_i_3 (.I0(Q[3]), .I1(Q[4]), .O(compare_err_latch_reg_0)); FDRE #( .INIT(1'b0)) compare_err_latch_reg (.C(CLK), .CE(1'b1), .D(compare_err_latch_i_1_n_0), .Q(compare_err_latch_reg_n_0), .R(1'b0)); LUT5 #( .INIT(32'h00002022)) compare_err_pb_and_i_1 (.I0(compare_err_pb_and_i_2_n_0), .I1(rstdiv0_sync_r1_reg_rep__22), .I2(cnt_wait_state), .I3(compare_err_pb_and2), .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ), .O(compare_err_pb_and_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40000000)) compare_err_pb_and_i_2 (.I0(compare_err_pb_and_i_3_n_0), .I1(compare_err_pb[5]), .I2(compare_err_pb[4]), .I3(compare_err_pb[6]), .I4(compare_err_pb[7]), .I5(compare_err_pb_and_reg_n_0), .O(compare_err_pb_and_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h7FFF)) compare_err_pb_and_i_3 (.I0(compare_err_pb[1]), .I1(compare_err_pb[0]), .I2(compare_err_pb[3]), .I3(compare_err_pb[2]), .O(compare_err_pb_and_i_3_n_0)); FDRE #( .INIT(1'b0)) compare_err_pb_and_reg (.C(CLK), .CE(1'b1), .D(compare_err_pb_and_i_1_n_0), .Q(compare_err_pb_and_reg_n_0), .R(1'b0)); LUT5 #( .INIT(32'h00002022)) compare_err_pb_or_i_1 (.I0(compare_err_pb_or_i_2_n_0), .I1(rstdiv0_sync_r1_reg_rep__22), .I2(cnt_wait_state), .I3(compare_err_pb_and2), .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ), .O(compare_err_pb_or_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) compare_err_pb_or_i_2 (.I0(compare_err_pb_or_i_3_n_0), .I1(compare_err_pb[3]), .I2(compare_err_pb[2]), .I3(compare_err_pb[1]), .I4(compare_err_pb[0]), .I5(sel0[0]), .O(compare_err_pb_or_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'h0001)) compare_err_pb_or_i_3 (.I0(compare_err_pb[6]), .I1(compare_err_pb[7]), .I2(compare_err_pb[5]), .I3(compare_err_pb[4]), .O(compare_err_pb_or_i_3_n_0)); FDRE #( .INIT(1'b0)) compare_err_pb_or_reg (.C(CLK), .CE(1'b1), .D(compare_err_pb_or_i_1_n_0), .Q(sel0[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) complex_init_pi_dec_done_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_3 ), .Q(complex_init_pi_dec_done), .R(rstdiv0_sync_r1_reg_rep__2)); LUT6 #( .INIT(64'h88B88888B8B8B8B8)) complex_pi_incdec_done_i_2 (.I0(complex_pi_incdec_done_i_3_n_0), .I1(complex_pi_incdec_done_i_4_n_0), .I2(complex_pi_incdec_done_i_5_n_0), .I3(\prbs_state_r[1]_i_5_n_0 ), .I4(cnt_wait_state), .I5(complex_pi_incdec_done_i_6_n_0), .O(complex_pi_incdec_done_reg_0)); LUT6 #( .INIT(64'hC0F07373C0F04040)) complex_pi_incdec_done_i_3 (.I0(prbs_tap_en_r_reg_0), .I1(complex_pi_incdec_done_i_5_n_0), .I2(cnt_wait_state), .I3(p_3_in), .I4(complex_pi_incdec_done_i_6_n_0), .I5(\prbs_state_r[3]_i_4_n_0 ), .O(complex_pi_incdec_done_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT5 #( .INIT(32'h04000118)) complex_pi_incdec_done_i_4 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[2]), .I4(Q[3]), .O(complex_pi_incdec_done_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'h04040834)) complex_pi_incdec_done_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[3]), .I4(Q[2]), .O(complex_pi_incdec_done_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'hEFDCFFF7)) complex_pi_incdec_done_i_6 (.I0(Q[0]), .I1(Q[4]), .I2(Q[3]), .I3(Q[2]), .I4(Q[1]), .O(complex_pi_incdec_done_i_6_n_0)); FDRE #( .INIT(1'b0)) complex_pi_incdec_done_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_4 ), .Q(complex_pi_incdec_done), .R(rstdiv0_sync_r1_reg_rep__2)); LUT1 #( .INIT(2'h1)) complex_victim_inc_i_2 (.I0(\rd_victim_sel_reg[2]_0 ), .O(complex_victim_inc__0)); FDRE #( .INIT(1'b0)) complex_victim_inc_reg (.C(CLK), .CE(1'b1), .D(complex_victim_inc__0), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT5 #( .INIT(32'hB8FFB8CC)) \dec_cnt[0]_i_1 (.I0(\dec_cnt_reg[0]_i_2_n_0 ), .I1(\largest_left_edge_reg_n_0_[5] ), .I2(\dec_cnt[0]_i_3_n_0 ), .I3(\smallest_right_edge_reg_n_0_[5] ), .I4(\dec_cnt[0]_i_4_n_0 ), .O(\dec_cnt[0]_i_1_n_0 )); LUT5 #( .INIT(32'hAFAFCFC0)) \dec_cnt[0]_i_11 (.I0(\dec_cnt[5]_i_6_n_0 ), .I1(\dec_cnt[0]_i_29_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_14_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[0]_i_11_n_0 )); LUT5 #( .INIT(32'hFFFFDE8E)) \dec_cnt[0]_i_13 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\dec_cnt[0]_i_14_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_32_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[0]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDFFDFFFF)) \dec_cnt[0]_i_14 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[0]_i_14_n_0 )); LUT6 #( .INIT(64'h7E733BEEE73EBEC3)) \dec_cnt[0]_i_15 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_15_n_0 )); LUT6 #( .INIT(64'h3E432BAEE6323AC3)) \dec_cnt[0]_i_16 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_16_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_17 (.I0(\dec_cnt[0]_i_33_n_0 ), .I1(\dec_cnt[0]_i_34_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_26_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[0]_i_35_n_0 ), .O(\dec_cnt[0]_i_17_n_0 )); LUT6 #( .INIT(64'h9996966669699999)) \dec_cnt[0]_i_20 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_20_n_0 )); LUT6 #( .INIT(64'hC29C39C323CE9C22)) \dec_cnt[0]_i_21 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_21_n_0 )); LUT6 #( .INIT(64'h25B649A565A55A64)) \dec_cnt[0]_i_22 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_22_n_0 )); LUT6 #( .INIT(64'h7DFEF57E08818110)) \dec_cnt[0]_i_23 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_23_n_0 )); LUT6 #( .INIT(64'h9796766669899991)) \dec_cnt[0]_i_24 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_24_n_0 )); LUT6 #( .INIT(64'h629C394323C69C32)) \dec_cnt[0]_i_25 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_25_n_0 )); LUT6 #( .INIT(64'h6B7F6AF74AB756A6)) \dec_cnt[0]_i_26 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_26_n_0 )); LUT6 #( .INIT(64'h3E732BEEE736BEC3)) \dec_cnt[0]_i_29 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_29_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_3 (.I0(\dec_cnt_reg[0]_i_7_n_0 ), .I1(\dec_cnt[0]_i_8_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[0]_i_9_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt_reg[0]_i_10_n_0 ), .O(\dec_cnt[0]_i_3_n_0 )); LUT6 #( .INIT(64'h3E532BEEE7323AC3)) \dec_cnt[0]_i_32 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_32_n_0 )); LUT6 #( .INIT(64'h9B96966669699999)) \dec_cnt[0]_i_33 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_33_n_0 )); LUT6 #( .INIT(64'hC29C39C323CE9C32)) \dec_cnt[0]_i_34 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_34_n_0 )); LUT6 #( .INIT(64'h7DBEF57E08C18110)) \dec_cnt[0]_i_35 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_35_n_0 )); LUT6 #( .INIT(64'hF00FE51A1ECFF00F)) \dec_cnt[0]_i_36 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_36_n_0 )); LUT6 #( .INIT(64'h3A755DAAA6558A15)) \dec_cnt[0]_i_37 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_37_n_0 )); LUT6 #( .INIT(64'h1CC32B8CC63238C1)) \dec_cnt[0]_i_38 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_38_n_0 )); LUT6 #( .INIT(64'hFF0F00E000F0FF3F)) \dec_cnt[0]_i_39 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_39_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \dec_cnt[0]_i_4 (.I0(\dec_cnt[0]_i_11_n_0 ), .I1(\largest_left_edge_reg_n_0_[4] ), .I2(\dec_cnt_reg[0]_i_12_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[0]_i_13_n_0 ), .O(\dec_cnt[0]_i_4_n_0 )); LUT6 #( .INIT(64'hF00F87E0708FF00F)) \dec_cnt[0]_i_40 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_40_n_0 )); LUT6 #( .INIT(64'h271D55AA8A55A285)) \dec_cnt[0]_i_41 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_41_n_0 )); LUT6 #( .INIT(64'h1C532BCCC736BCC1)) \dec_cnt[0]_i_42 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_42_n_0 )); LUT6 #( .INIT(64'hF00F0FF0F00BF00F)) \dec_cnt[0]_i_43 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_43_n_0 )); LUT6 #( .INIT(64'h1DBED57E48C10110)) \dec_cnt[0]_i_44 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_44_n_0 )); LUT6 #( .INIT(64'h6A7F6AB75AB756AE)) \dec_cnt[0]_i_45 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_45_n_0 )); LUT6 #( .INIT(64'h633C33CCDC63C63A)) \dec_cnt[0]_i_46 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_46_n_0 )); LUT6 #( .INIT(64'h9796666669999995)) \dec_cnt[0]_i_47 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_47_n_0 )); LUT5 #( .INIT(32'hFFFFDE8E)) \dec_cnt[0]_i_5 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\dec_cnt[0]_i_14_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_15_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[0]_i_5_n_0 )); LUT6 #( .INIT(64'hF3B8FFFFF3B80000)) \dec_cnt[0]_i_6 (.I0(\dec_cnt[0]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[0]_i_14_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt[0]_i_17_n_0 ), .O(\dec_cnt[0]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_8 (.I0(\dec_cnt[0]_i_20_n_0 ), .I1(\dec_cnt[0]_i_21_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_22_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[0]_i_23_n_0 ), .O(\dec_cnt[0]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_9 (.I0(\dec_cnt[0]_i_24_n_0 ), .I1(\dec_cnt[0]_i_25_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_26_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[0]_i_23_n_0 ), .O(\dec_cnt[0]_i_9_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[1]_i_1 (.I0(\dec_cnt[1]_i_2_n_0 ), .I1(\largest_left_edge_reg_n_0_[5] ), .I2(\dec_cnt[1]_i_3_n_0 ), .I3(\smallest_right_edge_reg_n_0_[5] ), .I4(\dec_cnt[1]_i_4_n_0 ), .O(\dec_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hA61AAFB6BE5BA69A)) \dec_cnt[1]_i_13 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_13_n_0 )); LUT6 #( .INIT(64'hE73BE633C673CE62)) \dec_cnt[1]_i_15 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_15_n_0 )); LUT6 #( .INIT(64'h0A7F8AFE3F017F11)) \dec_cnt[1]_i_16 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_16_n_0 )); LUT6 #( .INIT(64'hE731E633C673CE62)) \dec_cnt[1]_i_19 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_19_n_0 )); LUT5 #( .INIT(32'hDE8EFFFF)) \dec_cnt[1]_i_2 (.I0(\largest_left_edge_reg_n_0_[4] ), .I1(\dec_cnt[1]_i_5_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[1]_i_6_n_0 ), .I4(\smallest_right_edge_reg_n_0_[5] ), .O(\dec_cnt[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0A7F8AFE7F017F11)) \dec_cnt[1]_i_20 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_20_n_0 )); LUT6 #( .INIT(64'h8F8E0E1EE787878F)) \dec_cnt[1]_i_21 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_21_n_0 )); LUT6 #( .INIT(64'hE759A651AE758A64)) \dec_cnt[1]_i_22 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_22_n_0 )); LUT6 #( .INIT(64'hE579A561A6E596A4)) \dec_cnt[1]_i_25 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_25_n_0 )); LUT6 #( .INIT(64'h8F8E1E1EE787878F)) \dec_cnt[1]_i_26 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_26_n_0 )); LUT6 #( .INIT(64'h6A7FAA7E3F017F11)) \dec_cnt[1]_i_27 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_27_n_0 )); LUT6 #( .INIT(64'hDAD2DAF22F4F4F4A)) \dec_cnt[1]_i_28 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_28_n_0 )); LUT6 #( .INIT(64'h6759A659A6758A64)) \dec_cnt[1]_i_29 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_29_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[1]_i_3 (.I0(\dec_cnt_reg[1]_i_7_n_0 ), .I1(\dec_cnt[1]_i_8_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[1]_i_9_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt_reg[1]_i_10_n_0 ), .O(\dec_cnt[1]_i_3_n_0 )); LUT6 #( .INIT(64'h878E8E1EE7E78787)) \dec_cnt[1]_i_30 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_30_n_0 )); LUT6 #( .INIT(64'h6663866696869696)) \dec_cnt[1]_i_31 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_31_n_0 )); LUT6 #( .INIT(64'h89C991C9EC6CCC6C)) \dec_cnt[1]_i_32 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_32_n_0 )); LUT6 #( .INIT(64'h869AA5969E5BA69A)) \dec_cnt[1]_i_33 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_33_n_0 )); LUT6 #( .INIT(64'h6966696966866666)) \dec_cnt[1]_i_34 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_34_n_0 )); LUT6 #( .INIT(64'h6616666696991696)) \dec_cnt[1]_i_35 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_35_n_0 )); LUT6 #( .INIT(64'hCF00F38C8C33F700)) \dec_cnt[1]_i_36 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_36_n_0 )); LUT6 #( .INIT(64'h861AA5969E5BA69A)) \dec_cnt[1]_i_37 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_37_n_0 )); LUT6 #( .INIT(64'h6669666696669296)) \dec_cnt[1]_i_38 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_38_n_0 )); LUT6 #( .INIT(64'hFFFF00FFB8FFB800)) \dec_cnt[1]_i_4 (.I0(\dec_cnt_reg[1]_i_11_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt_reg[1]_i_12_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[1]_i_5_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[1]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT4 #( .INIT(16'hF3B8)) \dec_cnt[1]_i_5 (.I0(\dec_cnt[1]_i_13_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[1]_i_5_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[1]_i_6 (.I0(\dec_cnt_reg[1]_i_14_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[1]_i_15_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[1]_i_16_n_0 ), .O(\dec_cnt[1]_i_6_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[1]_i_8 (.I0(\dec_cnt_reg[1]_i_14_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[1]_i_19_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[1]_i_20_n_0 ), .O(\dec_cnt[1]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[1]_i_9 (.I0(\dec_cnt[1]_i_21_n_0 ), .I1(\dec_cnt[1]_i_22_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[1]_i_15_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[1]_i_20_n_0 ), .O(\dec_cnt[1]_i_9_n_0 )); LUT6 #( .INIT(64'h42C444C433232323)) \dec_cnt[2]_i_10 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_10_n_0 )); LUT6 #( .INIT(64'hDC9CC4DC9DBDDC9D)) \dec_cnt[2]_i_11 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEFEEEEF7)) \dec_cnt[2]_i_12 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_12_n_0 )); LUT6 #( .INIT(64'h26A22524AAAAA4A4)) \dec_cnt[2]_i_13 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'hDF)) \dec_cnt[2]_i_14 (.I0(\smallest_right_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h00AE)) \dec_cnt[2]_i_15 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFBDABEB)) \dec_cnt[2]_i_17 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_17_n_0 )); LUT6 #( .INIT(64'h26A225A4AAAAA4A4)) \dec_cnt[2]_i_18 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_18_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_19 (.I0(\dec_cnt[2]_i_25_n_0 ), .I1(\dec_cnt[2]_i_26_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_27_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_28_n_0 ), .O(\dec_cnt[2]_i_19_n_0 )); LUT6 #( .INIT(64'hBBBB88BBB8BBB888)) \dec_cnt[2]_i_2 (.I0(\dec_cnt_reg[2]_i_4_n_0 ), .I1(\smallest_right_edge_reg_n_0_[5] ), .I2(\dec_cnt[2]_i_5_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[2]_i_6_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_20 (.I0(\dec_cnt[2]_i_10_n_0 ), .I1(\dec_cnt[2]_i_29_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_17_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_30_n_0 ), .O(\dec_cnt[2]_i_20_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[2]_i_21 (.I0(\dec_cnt_reg[2]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[2]_i_31_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[2]_i_30_n_0 ), .O(\dec_cnt[2]_i_21_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_22 (.I0(\dec_cnt[2]_i_32_n_0 ), .I1(\dec_cnt[2]_i_33_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_27_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_34_n_0 ), .O(\dec_cnt[2]_i_22_n_0 )); LUT6 #( .INIT(64'hDCC49DC49DCCB9DD)) \dec_cnt[2]_i_23 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_23_n_0 )); LUT6 #( .INIT(64'h424442C433232323)) \dec_cnt[2]_i_24 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_24_n_0 )); LUT6 #( .INIT(64'h242422242226B222)) \dec_cnt[2]_i_25 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_25_n_0 )); LUT6 #( .INIT(64'hB39BB39BD9CDD9D9)) \dec_cnt[2]_i_26 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_26_n_0 )); LUT6 #( .INIT(64'hCF8FFFCFF7FFF3FF)) \dec_cnt[2]_i_27 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_27_n_0 )); LUT6 #( .INIT(64'h115100108808AA8A)) \dec_cnt[2]_i_28 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_28_n_0 )); LUT6 #( .INIT(64'hDCC49DCC9DCCB9DD)) \dec_cnt[2]_i_29 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_29_n_0 )); LUT5 #( .INIT(32'hDE8EFFFF)) \dec_cnt[2]_i_3 (.I0(\largest_left_edge_reg_n_0_[4] ), .I1(\dec_cnt[2]_i_6_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[2]_i_7_n_0 ), .I4(\smallest_right_edge_reg_n_0_[5] ), .O(\dec_cnt[2]_i_3_n_0 )); LUT6 #( .INIT(64'h22A225A4AAAAA4A4)) \dec_cnt[2]_i_30 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF77011501)) \dec_cnt[2]_i_31 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_31_n_0 )); LUT6 #( .INIT(64'h00204404AAAA22A2)) \dec_cnt[2]_i_32 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_32_n_0 )); LUT6 #( .INIT(64'hBB9BB39BD9CDD9D9)) \dec_cnt[2]_i_33 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_33_n_0 )); LUT6 #( .INIT(64'h2444242422223222)) \dec_cnt[2]_i_34 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_34_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_5 (.I0(\dec_cnt[2]_i_10_n_0 ), .I1(\dec_cnt[2]_i_11_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_12_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_13_n_0 ), .O(\dec_cnt[2]_i_5_n_0 )); LUT6 #( .INIT(64'hEFEAFFFFFFFFFFFF)) \dec_cnt[2]_i_6 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\dec_cnt[2]_i_14_n_0 ), .I2(\largest_left_edge_reg_n_0_[2] ), .I3(\dec_cnt[2]_i_15_n_0 ), .I4(\smallest_right_edge_reg_n_0_[2] ), .I5(\smallest_right_edge_reg_n_0_[3] ), .O(\dec_cnt[2]_i_6_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[2]_i_7 (.I0(\dec_cnt_reg[2]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[2]_i_17_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[2]_i_18_n_0 ), .O(\dec_cnt[2]_i_7_n_0 )); LUT5 #( .INIT(32'hB8FFB8CC)) \dec_cnt[3]_i_1 (.I0(\dec_cnt[3]_i_2_n_0 ), .I1(\largest_left_edge_reg_n_0_[5] ), .I2(\dec_cnt[3]_i_3_n_0 ), .I3(\smallest_right_edge_reg_n_0_[5] ), .I4(\dec_cnt[3]_i_4_n_0 ), .O(\dec_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[3]_i_10 (.I0(\dec_cnt[3]_i_12_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_5_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[3]_i_16_n_0 ), .O(\dec_cnt[3]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[3]_i_11 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\dec_cnt[3]_i_21_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[3]_i_19_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[3]_i_22_n_0 ), .O(\dec_cnt[3]_i_11_n_0 )); LUT6 #( .INIT(64'hBBBBBBBBBB8BBBBB)) \dec_cnt[3]_i_12 (.I0(\dec_cnt[3]_i_23_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\dec_cnt[4]_i_11_n_0 ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_12_n_0 )); LUT6 #( .INIT(64'hBBB888B8BBBBBBBB)) \dec_cnt[3]_i_13 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_24_n_0 ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\dec_cnt[3]_i_25_n_0 ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT5 #( .INIT(32'hFFFFBFAA)) \dec_cnt[3]_i_14 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF775FFFF)) \dec_cnt[3]_i_15 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_15_n_0 )); LUT6 #( .INIT(64'hF1115111FFFFFFFF)) \dec_cnt[3]_i_16 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_16_n_0 )); LUT6 #( .INIT(64'h6C6C66642626B226)) \dec_cnt[3]_i_17 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_17_n_0 )); LUT6 #( .INIT(64'hB8883333B8880000)) \dec_cnt[3]_i_18 (.I0(\dec_cnt[3]_i_26_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[4]_i_15_n_0 ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\largest_left_edge_reg_n_0_[2] ), .I5(\dec_cnt[3]_i_27_n_0 ), .O(\dec_cnt[3]_i_18_n_0 )); LUT6 #( .INIT(64'hCF8FFFCFFFFFFFFF)) \dec_cnt[3]_i_19 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_19_n_0 )); LUT6 #( .INIT(64'hFFFF00FFB8FFB800)) \dec_cnt[3]_i_2 (.I0(\dec_cnt[3]_i_5_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_6_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[3]_i_7_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000AB2A2222)) \dec_cnt[3]_i_20 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_20_n_0 )); LUT6 #( .INIT(64'h4444DD4500000000)) \dec_cnt[3]_i_21 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_21_n_0 )); LUT6 #( .INIT(64'h5515110100000000)) \dec_cnt[3]_i_22 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFCDDD4CCC)) \dec_cnt[3]_i_23 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_23_n_0 )); LUT2 #( .INIT(4'h1)) \dec_cnt[3]_i_24 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h8CCF)) \dec_cnt[3]_i_25 (.I0(\smallest_right_edge_reg_n_0_[0] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT5 #( .INIT(32'h445455D5)) \dec_cnt[3]_i_26 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_26_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT5 #( .INIT(32'hAAFB0000)) \dec_cnt[3]_i_27 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_27_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[3]_i_3 (.I0(\dec_cnt[3]_i_8_n_0 ), .I1(\dec_cnt[3]_i_9_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[3]_i_10_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt[3]_i_11_n_0 ), .O(\dec_cnt[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFF00FFB8FFB800)) \dec_cnt[3]_i_4 (.I0(\dec_cnt[3]_i_12_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_13_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[3]_i_7_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'hEFE0FFFFEFE00000)) \dec_cnt[3]_i_5 (.I0(\dec_cnt[4]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[2] ), .I3(\dec_cnt[3]_i_14_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[3]_i_15_n_0 ), .O(\dec_cnt[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'hB8)) \dec_cnt[3]_i_6 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_16_n_0 ), .O(\dec_cnt[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT4 #( .INIT(16'hF3B8)) \dec_cnt[3]_i_7 (.I0(\dec_cnt[3]_i_17_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[3]_i_7_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[3]_i_8 (.I0(\dec_cnt[3]_i_18_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_19_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[3]_i_20_n_0 ), .O(\dec_cnt[3]_i_8_n_0 )); LUT4 #( .INIT(16'h88B8)) \dec_cnt[3]_i_9 (.I0(\dec_cnt[3]_i_5_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_16_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[3]_i_9_n_0 )); LUT6 #( .INIT(64'hEFEAFFFF4540AAAA)) \dec_cnt[4]_i_1 (.I0(\largest_left_edge_reg_n_0_[5] ), .I1(\dec_cnt_reg[4]_i_2_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[4]_i_3_n_0 ), .I4(\smallest_right_edge_reg_n_0_[5] ), .I5(\dec_cnt[4]_i_4_n_0 ), .O(\dec_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'hF3B8)) \dec_cnt[4]_i_10 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[4]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'h8E)) \dec_cnt[4]_i_11 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT5 #( .INIT(32'hBABBA2AA)) \dec_cnt[4]_i_12 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_12_n_0 )); LUT6 #( .INIT(64'h3000703000000000)) \dec_cnt[4]_i_13 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF5D45DDDD)) \dec_cnt[4]_i_14 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h0400)) \dec_cnt[4]_i_15 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'hD0)) \dec_cnt[4]_i_16 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h20BA)) \dec_cnt[4]_i_17 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_17_n_0 )); LUT6 #( .INIT(64'hB8BBBBBBB8BB8888)) \dec_cnt[4]_i_3 (.I0(\dec_cnt[4]_i_7_n_0 ), .I1(\largest_left_edge_reg_n_0_[4] ), .I2(\dec_cnt[4]_i_8_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\smallest_right_edge_reg_n_0_[3] ), .I5(\dec_cnt[4]_i_9_n_0 ), .O(\dec_cnt[4]_i_3_n_0 )); LUT4 #( .INIT(16'hF3B8)) \dec_cnt[4]_i_4 (.I0(\dec_cnt[4]_i_7_n_0 ), .I1(\smallest_right_edge_reg_n_0_[4] ), .I2(\dec_cnt[4]_i_10_n_0 ), .I3(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[4]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFFFFFFFF)) \dec_cnt[4]_i_5 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\dec_cnt[4]_i_11_n_0 ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[2] ), .I5(\smallest_right_edge_reg_n_0_[3] ), .O(\dec_cnt[4]_i_5_n_0 )); LUT6 #( .INIT(64'hDFD0FFFFDFD0F0F0)) \dec_cnt[4]_i_6 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\dec_cnt[4]_i_12_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[4]_i_13_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[4]_i_14_n_0 ), .O(\dec_cnt[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'hB888)) \dec_cnt[4]_i_7 (.I0(\dec_cnt[5]_i_4_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_5_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[4]_i_7_n_0 )); LUT6 #( .INIT(64'hFFDFFFFF5545DD5D)) \dec_cnt[4]_i_8 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_8_n_0 )); LUT6 #( .INIT(64'hAF0FAF00CF0FCF0F)) \dec_cnt[4]_i_9 (.I0(\dec_cnt[4]_i_15_n_0 ), .I1(\dec_cnt[4]_i_16_n_0 ), .I2(\largest_left_edge_reg_n_0_[3] ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\dec_cnt[4]_i_17_n_0 ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_9_n_0 )); LUT4 #( .INIT(16'hEF4A)) \dec_cnt[5]_i_1 (.I0(\largest_left_edge_reg_n_0_[5] ), .I1(\dec_cnt[5]_i_2_n_0 ), .I2(\smallest_right_edge_reg_n_0_[5] ), .I3(\dec_cnt[5]_i_3_n_0 ), .O(\dec_cnt[5]_i_1_n_0 )); LUT6 #( .INIT(64'h0300000080808080)) \dec_cnt[5]_i_2 (.I0(\dec_cnt[5]_i_4_n_0 ), .I1(\smallest_right_edge_reg_n_0_[4] ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[5]_i_5_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[5]_i_2_n_0 )); LUT6 #( .INIT(64'hF7FDD5FD51DC4054)) \dec_cnt[5]_i_3 (.I0(\smallest_right_edge_reg_n_0_[4] ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\smallest_right_edge_reg_n_0_[3] ), .I4(\dec_cnt[5]_i_5_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[5]_i_3_n_0 )); LUT5 #( .INIT(32'h00004000)) \dec_cnt[5]_i_4 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\dec_cnt[5]_i_7_n_0 ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'h02000000ABAA2A22)) \dec_cnt[5]_i_5 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDDFDFFFF)) \dec_cnt[5]_i_6 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'h4D)) \dec_cnt[5]_i_7 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[5]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \dec_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\dec_cnt[0]_i_1_n_0 ), .Q(\prbs_dec_tap_cnt_reg[1]_0 [0]), .R(1'b0)); MUXF8 \dec_cnt_reg[0]_i_10 (.I0(\dec_cnt_reg[0]_i_27_n_0 ), .I1(\dec_cnt_reg[0]_i_28_n_0 ), .O(\dec_cnt_reg[0]_i_10_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[0]_i_12 (.I0(\dec_cnt_reg[0]_i_30_n_0 ), .I1(\dec_cnt_reg[0]_i_31_n_0 ), .O(\dec_cnt_reg[0]_i_12_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_18 (.I0(\dec_cnt[0]_i_36_n_0 ), .I1(\dec_cnt[0]_i_37_n_0 ), .O(\dec_cnt_reg[0]_i_18_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_19 (.I0(\dec_cnt[0]_i_38_n_0 ), .I1(\dec_cnt[0]_i_39_n_0 ), .O(\dec_cnt_reg[0]_i_19_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_2 (.I0(\dec_cnt[0]_i_5_n_0 ), .I1(\dec_cnt[0]_i_6_n_0 ), .O(\dec_cnt_reg[0]_i_2_n_0 ), .S(\smallest_right_edge_reg_n_0_[4] )); MUXF7 \dec_cnt_reg[0]_i_27 (.I0(\dec_cnt[0]_i_40_n_0 ), .I1(\dec_cnt[0]_i_41_n_0 ), .O(\dec_cnt_reg[0]_i_27_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_28 (.I0(\dec_cnt[0]_i_42_n_0 ), .I1(\dec_cnt[0]_i_43_n_0 ), .O(\dec_cnt_reg[0]_i_28_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_30 (.I0(\dec_cnt[0]_i_44_n_0 ), .I1(\dec_cnt[0]_i_45_n_0 ), .O(\dec_cnt_reg[0]_i_30_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_31 (.I0(\dec_cnt[0]_i_46_n_0 ), .I1(\dec_cnt[0]_i_47_n_0 ), .O(\dec_cnt_reg[0]_i_31_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[0]_i_7 (.I0(\dec_cnt_reg[0]_i_18_n_0 ), .I1(\dec_cnt_reg[0]_i_19_n_0 ), .O(\dec_cnt_reg[0]_i_7_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); FDRE #( .INIT(1'b0)) \dec_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\dec_cnt[1]_i_1_n_0 ), .Q(dec_cnt_reg[1]), .R(1'b0)); MUXF8 \dec_cnt_reg[1]_i_10 (.I0(\dec_cnt_reg[1]_i_23_n_0 ), .I1(\dec_cnt_reg[1]_i_24_n_0 ), .O(\dec_cnt_reg[1]_i_10_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_11 (.I0(\dec_cnt[1]_i_25_n_0 ), .I1(\dec_cnt[1]_i_26_n_0 ), .O(\dec_cnt_reg[1]_i_11_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_12 (.I0(\dec_cnt[1]_i_27_n_0 ), .I1(\dec_cnt[1]_i_28_n_0 ), .O(\dec_cnt_reg[1]_i_12_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_14 (.I0(\dec_cnt[1]_i_29_n_0 ), .I1(\dec_cnt[1]_i_30_n_0 ), .O(\dec_cnt_reg[1]_i_14_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_17 (.I0(\dec_cnt[1]_i_31_n_0 ), .I1(\dec_cnt[1]_i_32_n_0 ), .O(\dec_cnt_reg[1]_i_17_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_18 (.I0(\dec_cnt[1]_i_33_n_0 ), .I1(\dec_cnt[1]_i_34_n_0 ), .O(\dec_cnt_reg[1]_i_18_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_23 (.I0(\dec_cnt[1]_i_35_n_0 ), .I1(\dec_cnt[1]_i_36_n_0 ), .O(\dec_cnt_reg[1]_i_23_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_24 (.I0(\dec_cnt[1]_i_37_n_0 ), .I1(\dec_cnt[1]_i_38_n_0 ), .O(\dec_cnt_reg[1]_i_24_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[1]_i_7 (.I0(\dec_cnt_reg[1]_i_17_n_0 ), .I1(\dec_cnt_reg[1]_i_18_n_0 ), .O(\dec_cnt_reg[1]_i_7_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); FDRE #( .INIT(1'b0)) \dec_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\dec_cnt_reg[2]_i_1_n_0 ), .Q(dec_cnt_reg[2]), .R(1'b0)); MUXF7 \dec_cnt_reg[2]_i_1 (.I0(\dec_cnt[2]_i_2_n_0 ), .I1(\dec_cnt[2]_i_3_n_0 ), .O(\dec_cnt_reg[2]_i_1_n_0 ), .S(\largest_left_edge_reg_n_0_[5] )); MUXF7 \dec_cnt_reg[2]_i_16 (.I0(\dec_cnt[2]_i_23_n_0 ), .I1(\dec_cnt[2]_i_24_n_0 ), .O(\dec_cnt_reg[2]_i_16_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[2]_i_4 (.I0(\dec_cnt_reg[2]_i_8_n_0 ), .I1(\dec_cnt_reg[2]_i_9_n_0 ), .O(\dec_cnt_reg[2]_i_4_n_0 ), .S(\smallest_right_edge_reg_n_0_[4] )); MUXF7 \dec_cnt_reg[2]_i_8 (.I0(\dec_cnt[2]_i_19_n_0 ), .I1(\dec_cnt[2]_i_20_n_0 ), .O(\dec_cnt_reg[2]_i_8_n_0 ), .S(\largest_left_edge_reg_n_0_[4] )); MUXF7 \dec_cnt_reg[2]_i_9 (.I0(\dec_cnt[2]_i_21_n_0 ), .I1(\dec_cnt[2]_i_22_n_0 ), .O(\dec_cnt_reg[2]_i_9_n_0 ), .S(\largest_left_edge_reg_n_0_[4] )); FDRE #( .INIT(1'b0)) \dec_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\dec_cnt[3]_i_1_n_0 ), .Q(dec_cnt_reg[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \dec_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(\dec_cnt[4]_i_1_n_0 ), .Q(dec_cnt_reg[4]), .R(1'b0)); MUXF7 \dec_cnt_reg[4]_i_2 (.I0(\dec_cnt[4]_i_5_n_0 ), .I1(\dec_cnt[4]_i_6_n_0 ), .O(\dec_cnt_reg[4]_i_2_n_0 ), .S(\largest_left_edge_reg_n_0_[4] )); FDRE #( .INIT(1'b0)) \dec_cnt_reg[5] (.C(CLK), .CE(1'b1), .D(\dec_cnt[5]_i_1_n_0 ), .Q(\prbs_dec_tap_cnt_reg[1]_0 [1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT3 #( .INIT(8'h7F)) err_chk_invalid_i_1 (.I0(wait_state_cnt_r_reg__0[3]), .I1(wait_state_cnt_r_reg__0[1]), .I2(wait_state_cnt_r_reg__0[2]), .O(err_chk_invalid_i_1_n_0)); FDRE #( .INIT(1'b0)) err_chk_invalid_reg (.C(CLK), .CE(1'b1), .D(err_chk_invalid_i_1_n_0), .Q(err_chk_invalid), .R(1'b0)); LUT2 #( .INIT(4'h2)) \fine_delay_mod[11]_i_8 (.I0(\fine_delay_mod_reg[20] ), .I1(\A[2]__2 ), .O(\fine_delay_mod_reg[5] )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) fine_delay_sel_i_2 (.I0(Q[4]), .I1(fine_delay_sel_i_4_n_0), .I2(bit_cnt_reg__0[7]), .I3(bit_cnt_reg__0[6]), .I4(bit_cnt_reg__0[4]), .I5(bit_cnt_reg__0[5]), .O(fine_delay_sel_reg_0)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'hBD)) fine_delay_sel_i_3 (.I0(Q[1]), .I1(Q[2]), .I2(Q[3]), .O(fine_delay_sel_reg_1)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'hFFEF)) fine_delay_sel_i_4 (.I0(bit_cnt_reg__0[2]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[3]), .I3(bit_cnt_reg__0[1]), .O(fine_delay_sel_i_4_n_0)); FDRE #( .INIT(1'b0)) fine_delay_sel_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_0 ), .Q(fine_delay_sel_r_reg), .R(rstdiv0_sync_r1_reg_rep__8)); LUT6 #( .INIT(64'h0100000022002200)) fine_dly_error_i_2 (.I0(Q[2]), .I1(Q[3]), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I5(Q[4]), .O(fine_dly_error_reg_0)); FDRE #( .INIT(1'b0)) fine_dly_error_reg (.C(CLK), .CE(1'b1), .D(\dec_cnt_reg[0]_0 ), .Q(prbs_rdlvl_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__7)); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'h7)) fine_inc_stage_i_1 (.I0(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I1(\stage_cnt_reg_n_0_[0] ), .O(fine_inc_stage_i_1_n_0)); FDSE #( .INIT(1'b1)) fine_inc_stage_reg (.C(CLK), .CE(1'b1), .D(fine_inc_stage_i_1_n_0), .Q(fine_inc_stage_reg_n_0), .S(rstdiv0_sync_r1_reg_rep__8)); LUT5 #( .INIT(32'h74777444)) \fine_pi_dec_cnt[0]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[0] ), .I1(Q[2]), .I2(\fine_pi_dec_cnt[0]_i_2_n_0 ), .I3(Q[1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_1 [0]), .O(\fine_pi_dec_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h8A8ABA8ABA8ABA8A)) \fine_pi_dec_cnt[0]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\stage_cnt_reg_n_0_[0] ), .I2(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I3(\fine_pi_dec_cnt_reg[3]_i_3_n_7 ), .I4(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I5(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\fine_pi_dec_cnt[0]_i_2_n_0 )); LUT6 #( .INIT(64'h9F909F9F9F909090)) \fine_pi_dec_cnt[1]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[0] ), .I1(\fine_pi_dec_cnt_reg_n_0_[1] ), .I2(Q[2]), .I3(\fine_pi_dec_cnt[1]_i_2_n_0 ), .I4(Q[1]), .I5(\calib_sel_reg[3]_0 ), .O(\fine_pi_dec_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h8A8ABA8ABA8ABA8A)) \fine_pi_dec_cnt[1]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I1(\stage_cnt_reg_n_0_[0] ), .I2(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I3(\fine_pi_dec_cnt_reg[3]_i_3_n_6 ), .I4(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I5(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\fine_pi_dec_cnt[1]_i_2_n_0 )); LUT5 #( .INIT(32'hE1FFE100)) \fine_pi_dec_cnt[2]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[1] ), .I1(\fine_pi_dec_cnt_reg_n_0_[0] ), .I2(\fine_pi_dec_cnt_reg_n_0_[2] ), .I3(Q[2]), .I4(\fine_pi_dec_cnt[2]_i_2_n_0 ), .O(\fine_pi_dec_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h88B8FFFF88B80000)) \fine_pi_dec_cnt[2]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\fine_pi_dec_cnt_reg[3]_i_3_n_5 ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(Q[1]), .I5(\calib_sel_reg[3]_1 ), .O(\fine_pi_dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFE01FFFFFE010000)) \fine_pi_dec_cnt[3]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[0] ), .I1(\fine_pi_dec_cnt_reg_n_0_[1] ), .I2(\fine_pi_dec_cnt_reg_n_0_[2] ), .I3(\fine_pi_dec_cnt_reg_n_0_[3] ), .I4(Q[2]), .I5(\fine_pi_dec_cnt[3]_i_2_n_0 ), .O(\fine_pi_dec_cnt[3]_i_1_n_0 )); (* HLUTNM = "lutpair3" *) LUT3 #( .INIT(8'h96)) \fine_pi_dec_cnt[3]_i_10 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\fine_pi_dec_cnt[3]_i_10_n_0 )); LUT6 #( .INIT(64'h88B8FFFF88B80000)) \fine_pi_dec_cnt[3]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\fine_pi_dec_cnt_reg[3]_i_3_n_4 ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(Q[1]), .I5(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .O(\fine_pi_dec_cnt[3]_i_2_n_0 )); (* HLUTNM = "lutpair1" *) LUT3 #( .INIT(8'hD4)) \fine_pi_dec_cnt[3]_i_4 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(dec_cnt_reg[2]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\fine_pi_dec_cnt[3]_i_4_n_0 )); (* HLUTNM = "lutpair0" *) LUT3 #( .INIT(8'hD4)) \fine_pi_dec_cnt[3]_i_5 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(dec_cnt_reg[1]), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\fine_pi_dec_cnt[3]_i_5_n_0 )); (* HLUTNM = "lutpair3" *) LUT2 #( .INIT(4'hB)) \fine_pi_dec_cnt[3]_i_6 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(\smallest_right_edge_reg_n_0_[0] ), .O(\fine_pi_dec_cnt[3]_i_6_n_0 )); (* HLUTNM = "lutpair2" *) LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[3]_i_7 (.I0(\smallest_right_edge_reg_n_0_[3] ), .I1(dec_cnt_reg[3]), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I3(\fine_pi_dec_cnt[3]_i_4_n_0 ), .O(\fine_pi_dec_cnt[3]_i_7_n_0 )); (* HLUTNM = "lutpair1" *) LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[3]_i_8 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(dec_cnt_reg[2]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\fine_pi_dec_cnt[3]_i_5_n_0 ), .O(\fine_pi_dec_cnt[3]_i_8_n_0 )); (* HLUTNM = "lutpair0" *) LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[3]_i_9 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(dec_cnt_reg[1]), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\fine_pi_dec_cnt[3]_i_6_n_0 ), .O(\fine_pi_dec_cnt[3]_i_9_n_0 )); LUT6 #( .INIT(64'h88B8FFFF88B80000)) \fine_pi_dec_cnt[4]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\fine_pi_dec_cnt_reg[5]_i_8_n_7 ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(Q[1]), .I5(\calib_sel_reg[3]_2 ), .O(\fine_pi_dec_cnt[4]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFE0001)) \fine_pi_dec_cnt[4]_i_3 (.I0(\fine_pi_dec_cnt_reg_n_0_[3] ), .I1(\fine_pi_dec_cnt_reg_n_0_[2] ), .I2(\fine_pi_dec_cnt_reg_n_0_[1] ), .I3(\fine_pi_dec_cnt_reg_n_0_[0] ), .I4(\fine_pi_dec_cnt_reg_n_0_[4] ), .O(\fine_pi_dec_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'h8E71718E718E8E71)) \fine_pi_dec_cnt[5]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(dec_cnt_reg[4]), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I4(\smallest_right_edge_reg_n_0_[5] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\fine_pi_dec_cnt[5]_i_10_n_0 )); LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[5]_i_11 (.I0(\fine_pi_dec_cnt[5]_i_9_n_0 ), .I1(dec_cnt_reg[4]), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\fine_pi_dec_cnt[5]_i_11_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \fine_pi_dec_cnt[5]_i_3 (.I0(prbs_rdlvl_start_r), .I1(prbs_rdlvl_start_reg), .I2(Q[3]), .I3(Q[2]), .I4(Q[4]), .I5(Q[1]), .O(\fine_pi_dec_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'h1010180800001808)) \fine_pi_dec_cnt[5]_i_4 (.I0(Q[1]), .I1(Q[4]), .I2(Q[3]), .I3(cnt_wait_state), .I4(Q[2]), .I5(prbs_tap_en_r_reg_0), .O(\fine_pi_dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hBBB8FFFFBBB80000)) \fine_pi_dec_cnt[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I3(\fine_pi_dec_cnt_reg[5]_i_8_n_6 ), .I4(Q[1]), .I5(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]), .O(\fine_pi_dec_cnt[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \fine_pi_dec_cnt[5]_i_6 (.I0(\fine_pi_dec_cnt_reg_n_0_[4] ), .I1(\fine_pi_dec_cnt_reg_n_0_[0] ), .I2(\fine_pi_dec_cnt_reg_n_0_[1] ), .I3(\fine_pi_dec_cnt_reg_n_0_[2] ), .I4(\fine_pi_dec_cnt_reg_n_0_[3] ), .I5(\fine_pi_dec_cnt_reg_n_0_[5] ), .O(\fine_pi_dec_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'hB)) \fine_pi_dec_cnt[5]_i_7 (.I0(\stage_cnt_reg_n_0_[0] ), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .O(\fine_pi_dec_cnt[5]_i_7_n_0 )); (* HLUTNM = "lutpair2" *) LUT3 #( .INIT(8'hD4)) \fine_pi_dec_cnt[5]_i_9 (.I0(\smallest_right_edge_reg_n_0_[3] ), .I1(dec_cnt_reg[3]), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\fine_pi_dec_cnt[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \fine_pi_dec_cnt_reg[0] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[0]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \fine_pi_dec_cnt_reg[1] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[1]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \fine_pi_dec_cnt_reg[2] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[2]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \fine_pi_dec_cnt_reg[3] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[3]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \fine_pi_dec_cnt_reg[3]_i_3 (.CI(1'b0), .CO({\fine_pi_dec_cnt_reg[3]_i_3_n_0 ,\fine_pi_dec_cnt_reg[3]_i_3_n_1 ,\fine_pi_dec_cnt_reg[3]_i_3_n_2 ,\fine_pi_dec_cnt_reg[3]_i_3_n_3 }), .CYINIT(1'b0), .DI({\fine_pi_dec_cnt[3]_i_4_n_0 ,\fine_pi_dec_cnt[3]_i_5_n_0 ,\fine_pi_dec_cnt[3]_i_6_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\fine_pi_dec_cnt_reg[3]_i_3_n_4 ,\fine_pi_dec_cnt_reg[3]_i_3_n_5 ,\fine_pi_dec_cnt_reg[3]_i_3_n_6 ,\fine_pi_dec_cnt_reg[3]_i_3_n_7 }), .S({\fine_pi_dec_cnt[3]_i_7_n_0 ,\fine_pi_dec_cnt[3]_i_8_n_0 ,\fine_pi_dec_cnt[3]_i_9_n_0 ,\fine_pi_dec_cnt[3]_i_10_n_0 })); FDRE #( .INIT(1'b0)) \fine_pi_dec_cnt_reg[4] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt_reg[4]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__7)); MUXF7 \fine_pi_dec_cnt_reg[4]_i_1 (.I0(\fine_pi_dec_cnt[4]_i_2_n_0 ), .I1(\fine_pi_dec_cnt[4]_i_3_n_0 ), .O(\fine_pi_dec_cnt_reg[4]_i_1_n_0 ), .S(Q[2])); FDRE #( .INIT(1'b0)) \fine_pi_dec_cnt_reg[5] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt_reg[5]_i_2_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__7)); MUXF7 \fine_pi_dec_cnt_reg[5]_i_1 (.I0(\fine_pi_dec_cnt[5]_i_3_n_0 ), .I1(\fine_pi_dec_cnt[5]_i_4_n_0 ), .O(fine_pi_dec_cnt), .S(Q[0])); MUXF7 \fine_pi_dec_cnt_reg[5]_i_2 (.I0(\fine_pi_dec_cnt[5]_i_5_n_0 ), .I1(\fine_pi_dec_cnt[5]_i_6_n_0 ), .O(\fine_pi_dec_cnt_reg[5]_i_2_n_0 ), .S(Q[2])); CARRY4 \fine_pi_dec_cnt_reg[5]_i_8 (.CI(\fine_pi_dec_cnt_reg[3]_i_3_n_0 ), .CO({\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED [3:1],\fine_pi_dec_cnt_reg[5]_i_8_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\fine_pi_dec_cnt[5]_i_9_n_0 }), .O({\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED [3:2],\fine_pi_dec_cnt_reg[5]_i_8_n_6 ,\fine_pi_dec_cnt_reg[5]_i_8_n_7 }), .S({1'b0,1'b0,\fine_pi_dec_cnt[5]_i_10_n_0 ,\fine_pi_dec_cnt[5]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall0_r1), .Q(mux_rd_fall0_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall0_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall1_r1), .Q(mux_rd_fall1_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall1_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall2_r1), .Q(mux_rd_fall2_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall2_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall3_r1), .Q(mux_rd_fall3_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall3_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise0_r1), .Q(mux_rd_rise0_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise0_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise1_r1), .Q(mux_rd_rise1_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise1_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise2_r1), .Q(mux_rd_rise2_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise2_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise3_r1), .Q(mux_rd_rise3_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise3_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_fall0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6] ), .Q(\gen_mux_rd[0].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_fall1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4] ), .Q(\gen_mux_rd[0].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_fall2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2] ), .Q(\gen_mux_rd[0].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_fall3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0] ), .Q(\gen_mux_rd[0].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_rise0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7] ), .Q(\gen_mux_rd[0].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_rise1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5] ), .Q(\gen_mux_rd[0].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_rise2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3] ), .Q(\gen_mux_rd[0].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].compare_data_rise3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1] ), .Q(\gen_mux_rd[0].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_9 ), .Q(mux_rd_fall0_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_25 ), .Q(mux_rd_fall1_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_41 ), .Q(mux_rd_fall2_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_57 ), .Q(mux_rd_fall3_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_1 ), .Q(mux_rd_rise0_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_17 ), .Q(mux_rd_rise1_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_33 ), .Q(mux_rd_rise2_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_49 ), .Q(mux_rd_rise3_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_fall0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_0 ), .Q(\gen_mux_rd[1].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_fall1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_0 ), .Q(\gen_mux_rd[1].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_fall2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_0 ), .Q(\gen_mux_rd[1].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_fall3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_0 ), .Q(\gen_mux_rd[1].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_rise0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_0 ), .Q(\gen_mux_rd[1].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_rise1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_0 ), .Q(\gen_mux_rd[1].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_rise2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_0 ), .Q(\gen_mux_rd[1].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].compare_data_rise3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_0 ), .Q(\gen_mux_rd[1].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_10 ), .Q(\gen_mux_rd[1].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_26 ), .Q(\gen_mux_rd[1].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_42 ), .Q(\gen_mux_rd[1].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_58 ), .Q(\gen_mux_rd[1].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_2 ), .Q(\gen_mux_rd[1].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_18 ), .Q(\gen_mux_rd[1].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_34 ), .Q(\gen_mux_rd[1].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_50 ), .Q(\gen_mux_rd[1].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_fall0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_1 ), .Q(\gen_mux_rd[2].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_fall1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_1 ), .Q(\gen_mux_rd[2].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_fall2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_1 ), .Q(\gen_mux_rd[2].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_fall3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_1 ), .Q(\gen_mux_rd[2].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_rise0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_1 ), .Q(\gen_mux_rd[2].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_rise1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_1 ), .Q(\gen_mux_rd[2].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_rise2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_1 ), .Q(\gen_mux_rd[2].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].compare_data_rise3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_1 ), .Q(\gen_mux_rd[2].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_11 ), .Q(\gen_mux_rd[2].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_27 ), .Q(\gen_mux_rd[2].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_43 ), .Q(\gen_mux_rd[2].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_59 ), .Q(\gen_mux_rd[2].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_3 ), .Q(\gen_mux_rd[2].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_19 ), .Q(\gen_mux_rd[2].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_35 ), .Q(\gen_mux_rd[2].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_51 ), .Q(\gen_mux_rd[2].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_fall0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_2 ), .Q(\gen_mux_rd[3].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_fall1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_2 ), .Q(\gen_mux_rd[3].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_fall2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_2 ), .Q(\gen_mux_rd[3].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_fall3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_2 ), .Q(\gen_mux_rd[3].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_rise0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_2 ), .Q(\gen_mux_rd[3].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_rise1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_2 ), .Q(\gen_mux_rd[3].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_rise2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_2 ), .Q(\gen_mux_rd[3].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].compare_data_rise3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_2 ), .Q(\gen_mux_rd[3].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_12 ), .Q(\gen_mux_rd[3].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_28 ), .Q(\gen_mux_rd[3].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_44 ), .Q(\gen_mux_rd[3].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_60 ), .Q(\gen_mux_rd[3].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_4 ), .Q(\gen_mux_rd[3].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_20 ), .Q(\gen_mux_rd[3].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_36 ), .Q(\gen_mux_rd[3].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_52 ), .Q(\gen_mux_rd[3].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_fall0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_3 ), .Q(\gen_mux_rd[4].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_fall1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_3 ), .Q(\gen_mux_rd[4].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_fall2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_3 ), .Q(\gen_mux_rd[4].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_fall3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_3 ), .Q(\gen_mux_rd[4].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_rise0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_3 ), .Q(\gen_mux_rd[4].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_rise1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_3 ), .Q(\gen_mux_rd[4].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_rise2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_3 ), .Q(\gen_mux_rd[4].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].compare_data_rise3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_3 ), .Q(\gen_mux_rd[4].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_13 ), .Q(\gen_mux_rd[4].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_29 ), .Q(\gen_mux_rd[4].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_45 ), .Q(\gen_mux_rd[4].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_61 ), .Q(\gen_mux_rd[4].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_5 ), .Q(\gen_mux_rd[4].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_21 ), .Q(\gen_mux_rd[4].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_37 ), .Q(\gen_mux_rd[4].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_53 ), .Q(\gen_mux_rd[4].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_fall0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_4 ), .Q(\gen_mux_rd[5].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_fall1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_4 ), .Q(\gen_mux_rd[5].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_fall2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_4 ), .Q(\gen_mux_rd[5].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_fall3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_4 ), .Q(\gen_mux_rd[5].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_rise0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_4 ), .Q(\gen_mux_rd[5].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_rise1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_4 ), .Q(\gen_mux_rd[5].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_rise2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_4 ), .Q(\gen_mux_rd[5].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].compare_data_rise3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_4 ), .Q(\gen_mux_rd[5].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_14 ), .Q(\gen_mux_rd[5].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_30 ), .Q(\gen_mux_rd[5].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_46 ), .Q(\gen_mux_rd[5].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_62 ), .Q(\gen_mux_rd[5].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_6 ), .Q(\gen_mux_rd[5].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_22 ), .Q(\gen_mux_rd[5].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_38 ), .Q(\gen_mux_rd[5].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_54 ), .Q(\gen_mux_rd[5].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_fall0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_5 ), .Q(\gen_mux_rd[6].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_fall1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_5 ), .Q(\gen_mux_rd[6].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_fall2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_5 ), .Q(\gen_mux_rd[6].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_fall3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_5 ), .Q(\gen_mux_rd[6].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_rise0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_5 ), .Q(\gen_mux_rd[6].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_rise1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_5 ), .Q(\gen_mux_rd[6].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_rise2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_5 ), .Q(\gen_mux_rd[6].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].compare_data_rise3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_5 ), .Q(\gen_mux_rd[6].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_15 ), .Q(\gen_mux_rd[6].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_31 ), .Q(\gen_mux_rd[6].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_47 ), .Q(\gen_mux_rd[6].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_63 ), .Q(\gen_mux_rd[6].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_7 ), .Q(\gen_mux_rd[6].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_23 ), .Q(\gen_mux_rd[6].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_39 ), .Q(\gen_mux_rd[6].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_55 ), .Q(\gen_mux_rd[6].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_fall0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_6 ), .Q(\gen_mux_rd[7].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_fall1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_6 ), .Q(\gen_mux_rd[7].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_fall2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_6 ), .Q(\gen_mux_rd[7].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_fall3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_6 ), .Q(\gen_mux_rd[7].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_rise0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_6 ), .Q(\gen_mux_rd[7].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_rise1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_6 ), .Q(\gen_mux_rd[7].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_rise2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_6 ), .Q(\gen_mux_rd[7].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].compare_data_rise3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_6 ), .Q(\gen_mux_rd[7].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_16 ), .Q(\gen_mux_rd[7].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_32 ), .Q(\gen_mux_rd[7].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_48 ), .Q(\gen_mux_rd[7].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_64 ), .Q(\gen_mux_rd[7].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_8 ), .Q(\gen_mux_rd[7].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_24 ), .Q(\gen_mux_rd[7].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_40 ), .Q(\gen_mux_rd[7].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_56 ), .Q(\gen_mux_rd[7].mux_rd_rise3_r1_reg ), .R(1'b0)); LUT6 #( .INIT(64'h00000001D000C000)) \genblk7[0].compare_err_pb_latch_r[0]_i_1 (.I0(cnt_wait_state), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .I4(Q[1]), .I5(Q[4]), .O(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[0].compare_err_pb_latch_r[0]_i_2 (.I0(compare_err_pb[0]), .I1(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .O(\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[0].compare_err_pb_latch_r_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ), .Q(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT2 #( .INIT(4'hE)) \genblk7[1].compare_err_pb_latch_r[1]_i_1 (.I0(compare_err_pb[1]), .I1(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .O(\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[1].compare_err_pb_latch_r_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ), .Q(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[2].compare_err_pb_latch_r[2]_i_1 (.I0(compare_err_pb[2]), .I1(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .O(\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[2].compare_err_pb_latch_r_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ), .Q(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[3].compare_err_pb_latch_r[3]_i_1 (.I0(compare_err_pb[3]), .I1(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .O(\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[3].compare_err_pb_latch_r_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ), .Q(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[4].compare_err_pb_latch_r[4]_i_1 (.I0(compare_err_pb[4]), .I1(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .O(\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[4].compare_err_pb_latch_r_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ), .Q(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[5].compare_err_pb_latch_r[5]_i_1 (.I0(compare_err_pb[5]), .I1(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .O(\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[5].compare_err_pb_latch_r_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ), .Q(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT2 #( .INIT(4'hE)) \genblk7[6].compare_err_pb_latch_r[6]_i_1 (.I0(compare_err_pb[6]), .I1(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .O(\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[6].compare_err_pb_latch_r_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ), .Q(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[7].compare_err_pb_latch_r[7]_i_1 (.I0(compare_err_pb[7]), .I1(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .O(\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk7[7].compare_err_pb_latch_r_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ), .Q(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_found_pb_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk8[0].left_edge_found_pb_reg[0]_0 ), .Q(\genblk8[0].left_loss_pb_reg[0]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT1 #( .INIT(2'h1)) \genblk8[0].left_edge_pb[0]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\genblk8[0].left_edge_pb[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \genblk8[0].left_edge_pb[1]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_edge_pb[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h78)) \genblk8[0].left_edge_pb[2]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].left_edge_pb[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT4 #( .INIT(16'h9555)) \genblk8[0].left_edge_pb[3]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_edge_pb[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'hAAAA9555)) \genblk8[0].left_edge_pb[4]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .O(\genblk8[0].left_edge_pb[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00000004)) \genblk8[0].left_edge_pb[5]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[4]), .I3(Q[1]), .I4(Q[3]), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[0].left_edge_pb[5]_i_2 (.I0(p_154_out), .I1(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(left_edge_pb)); LUT6 #( .INIT(64'hAAAAAAAAA9999999)) \genblk8[0].left_edge_pb[5]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\genblk8[0].left_edge_pb[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[0].left_edge_pb[5]_i_4 (.I0(match_flag_pb[7]), .I1(\genblk8[0].left_edge_pb[5]_i_5_n_0 ), .I2(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .I3(match_flag_pb[6]), .I4(match_flag_pb[4]), .I5(match_flag_pb[5]), .O(\genblk8[0].left_loss_pb_reg[0]_1 )); LUT4 #( .INIT(16'hFFFE)) \genblk8[0].left_edge_pb[5]_i_5 (.I0(match_flag_pb[2]), .I1(match_flag_pb[3]), .I2(match_flag_pb[0]), .I3(match_flag_pb[1]), .O(\genblk8[0].left_edge_pb[5]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_pb_reg[0] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_pb_reg[1] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_pb_reg[2] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[2] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_pb_reg[3] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[3] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_pb_reg[4] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[4] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_pb_reg[5] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[5] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( .INIT(16'h0080)) \genblk8[0].left_edge_updated[0]_i_2 (.I0(Q[0]), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .O(\genblk8[7].left_edge_updated_reg[7]_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_edge_updated_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk8[0].left_edge_updated_reg[0]_0 ), .Q(D[0]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[0]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ), .O(\genblk8[0].left_loss_pb[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[1]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ), .O(\genblk8[0].left_loss_pb[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[2]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ), .O(\genblk8[0].left_loss_pb[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[3]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ), .O(\genblk8[0].left_loss_pb[3]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \genblk8[0].left_loss_pb[3]_i_3 (.I0(left_edge_ref[3]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .O(\genblk8[0].left_loss_pb[3]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \genblk8[0].left_loss_pb[3]_i_4 (.I0(left_edge_ref[1]), .O(\genblk8[0].left_loss_pb[3]_i_4_n_0 )); LUT4 #( .INIT(16'h6966)) \genblk8[0].left_loss_pb[3]_i_5 (.I0(left_edge_ref[3]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I2(left_edge_ref[2]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].left_loss_pb[3]_i_5_n_0 )); LUT3 #( .INIT(8'h96)) \genblk8[0].left_loss_pb[3]_i_6 (.I0(left_edge_ref[1]), .I1(left_edge_ref[2]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].left_loss_pb[3]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \genblk8[0].left_loss_pb[3]_i_7 (.I0(left_edge_ref[1]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_loss_pb[3]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].left_loss_pb[3]_i_8 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I1(left_edge_ref[0]), .O(\genblk8[0].left_loss_pb[3]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[4]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ), .O(\genblk8[0].left_loss_pb[4]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[0].left_loss_pb[5]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[0].left_loss_pb_reg[0]_0 ), .I4(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(\genblk8[0].left_loss_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_10_n_0 )); LUT2 #( .INIT(4'hB)) \genblk8[0].left_loss_pb[5]_i_11 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I1(left_edge_ref[3]), .O(\genblk8[0].left_loss_pb[5]_i_11_n_0 )); LUT4 #( .INIT(16'hD22D)) \genblk8[0].left_loss_pb[5]_i_12 (.I0(left_edge_ref[4]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(left_edge_ref[5]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_12_n_0 )); LUT4 #( .INIT(16'hD22D)) \genblk8[0].left_loss_pb[5]_i_13 (.I0(left_edge_ref[3]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I2(left_edge_ref[4]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\genblk8[0].left_loss_pb[5]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_15 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_16 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_17 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_18 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[5]_i_2 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ), .O(\genblk8[0].left_loss_pb[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_23 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_23_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[0].left_loss_pb[5]_i_24 (.I0(left_edge_ref[4]), .I1(left_edge_ref[5]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I3(\genblk8[0].left_loss_pb[5]_i_31_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_24_n_0 )); LUT6 #( .INIT(64'h8CCCCEEEE0000888)) \genblk8[0].left_loss_pb[5]_i_25 (.I0(left_edge_ref[2]), .I1(left_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].left_loss_pb[5]_i_25_n_0 )); LUT4 #( .INIT(16'hCB80)) \genblk8[0].left_loss_pb[5]_i_26 (.I0(left_edge_ref[0]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I3(left_edge_ref[1]), .O(\genblk8[0].left_loss_pb[5]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_27_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[0].left_loss_pb[5]_i_28 (.I0(left_edge_ref[4]), .I1(left_edge_ref[5]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I3(\genblk8[0].left_loss_pb[5]_i_31_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_28_n_0 )); LUT6 #( .INIT(64'h4222211118888444)) \genblk8[0].left_loss_pb[5]_i_29 (.I0(left_edge_ref[2]), .I1(left_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].left_loss_pb[5]_i_29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT5 #( .INIT(32'h00400000)) \genblk8[0].left_loss_pb[5]_i_3 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(right_gain_pb)); LUT4 #( .INIT(16'h1842)) \genblk8[0].left_loss_pb[5]_i_30 (.I0(left_edge_ref[0]), .I1(left_edge_ref[1]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_loss_pb[5]_i_30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'h80)) \genblk8[0].left_loss_pb[5]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_loss_pb[5]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_8 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_loss_pb_reg[0] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_loss_pb_reg[1] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_loss_pb_reg[2] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_loss_pb_reg[3] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].left_loss_pb_reg[3]_i_2 (.CI(1'b0), .CO({\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_3 }), .CYINIT(1'b0), .DI({\genblk8[0].left_loss_pb[3]_i_3_n_0 ,\genblk8[0].left_loss_pb[3]_i_4_n_0 ,left_edge_ref[1],\prbs_dqs_tap_cnt_r_reg_n_0_[0] }), .O({\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 }), .S({\genblk8[0].left_loss_pb[3]_i_5_n_0 ,\genblk8[0].left_loss_pb[3]_i_6_n_0 ,\genblk8[0].left_loss_pb[3]_i_7_n_0 ,\genblk8[0].left_loss_pb[3]_i_8_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[0].left_loss_pb_reg[4] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].left_loss_pb_reg[5] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_14 (.CI(\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ), .CO({\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_14_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_20_n_0 ,\genblk8[0].left_loss_pb[5]_i_21_n_0 ,\genblk8[0].left_loss_pb[5]_i_22_n_0 ,\genblk8[0].left_loss_pb[5]_i_23_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_19 (.CI(1'b0), .CO({\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_19_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[0].left_loss_pb[5]_i_24_n_0 ,\genblk8[0].left_loss_pb[5]_i_25_n_0 ,\genblk8[0].left_loss_pb[5]_i_26_n_0 }), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_27_n_0 ,\genblk8[0].left_loss_pb[5]_i_28_n_0 ,\genblk8[0].left_loss_pb[5]_i_29_n_0 ,\genblk8[0].left_loss_pb[5]_i_30_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_4 (.CI(\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ), .CO({\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_7_n_0 ,\genblk8[0].left_loss_pb[5]_i_8_n_0 ,\genblk8[0].left_loss_pb[5]_i_9_n_0 ,\genblk8[0].left_loss_pb[5]_i_10_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_5 (.CI(\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ), .CO({\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED [3:1],\genblk8[0].left_loss_pb_reg[5]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\genblk8[0].left_loss_pb[5]_i_11_n_0 }), .O({\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED [3:2],\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ,\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[0].left_loss_pb[5]_i_12_n_0 ,\genblk8[0].left_loss_pb[5]_i_13_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_6 (.CI(\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ), .CO({\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_15_n_0 ,\genblk8[0].left_loss_pb[5]_i_16_n_0 ,\genblk8[0].left_loss_pb[5]_i_17_n_0 ,\genblk8[0].left_loss_pb[5]_i_18_n_0 })); LUT3 #( .INIT(8'hBA)) \genblk8[0].match_flag_pb[7]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_154_out), .I2(right_gain_pb), .O(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); LUT6 #( .INIT(64'h0002000000000000)) \genblk8[0].match_flag_pb[7]_i_2 (.I0(num_samples_done_r), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(Q[4]), .I5(Q[0]), .O(p_154_out)); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[0] (.C(CLK), .CE(p_154_out), .D(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .Q(match_flag_pb[0]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[1] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[0]), .Q(match_flag_pb[1]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[2] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[1]), .Q(match_flag_pb[2]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[3] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[2]), .Q(match_flag_pb[3]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[4] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[3]), .Q(match_flag_pb[4]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[5] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[4]), .Q(match_flag_pb[5]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[6] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[5]), .Q(match_flag_pb[6]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].match_flag_pb_reg[7] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[6]), .Q(match_flag_pb[7]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].right_edge_found_pb_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk8[0].right_edge_found_pb_reg[0]_0 ), .Q(\genblk8[0].right_edge_pb_reg[0]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT2 #( .INIT(4'h9)) \genblk8[0].right_edge_pb[1]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\genblk8[0].right_edge_pb[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'hA9)) \genblk8[0].right_edge_pb[2]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\genblk8[0].right_edge_pb[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'hAAA9)) \genblk8[0].right_edge_pb[3]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].right_edge_pb[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT5 #( .INIT(32'hAAAAAAA9)) \genblk8[0].right_edge_pb[4]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\genblk8[0].right_edge_pb[4]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[0].right_edge_pb[5]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(\genblk8[0].left_loss_pb_reg[0]_1 ), .I2(p_154_out), .I3(\genblk8[0].right_edge_pb_reg[0]_1 ), .I4(\genblk8[0].right_edge_pb_reg[0]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[0].right_edge_pb[5]_i_2 (.I0(p_154_out), .I1(\genblk8[0].right_edge_pb_reg[0]_1 ), .I2(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(\genblk8[0].right_edge_pb[5]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \genblk8[0].right_edge_pb[5]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\genblk8[0].right_edge_pb[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[0].right_edge_pb[5]_i_4 (.I0(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .I1(\genblk8[0].left_edge_pb[5]_i_5_n_0 ), .I2(match_flag_pb[7]), .I3(match_flag_pb[6]), .I4(match_flag_pb[4]), .I5(match_flag_pb[5]), .O(\genblk8[0].right_edge_pb_reg[0]_1 )); LUT6 #( .INIT(64'h8000000000000000)) \genblk8[0].right_edge_pb[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[7].right_edge_pb_reg[42]_1 )); FDSE #( .INIT(1'b1)) \genblk8[0].right_edge_pb_reg[0] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].right_edge_pb_reg[1] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].right_edge_pb_reg[2] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].right_edge_pb_reg[3] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].right_edge_pb_reg[4] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[0].right_edge_pb_reg[5] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[0]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ), .O(\genblk8[0].right_gain_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[1]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ), .O(\genblk8[0].right_gain_pb[1]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[2]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ), .O(\genblk8[0].right_gain_pb[2]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[3]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ), .O(\genblk8[0].right_gain_pb[3]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\genblk8[0].right_gain_pb[3]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\genblk8[0].right_gain_pb[3]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\genblk8[0].right_gain_pb[3]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\genblk8[0].right_gain_pb[3]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\genblk8[0].right_gain_pb[3]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\genblk8[0].right_gain_pb[3]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\genblk8[0].right_gain_pb[3]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\genblk8[0].right_gain_pb[3]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[4]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ), .O(\genblk8[0].right_gain_pb[4]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[0].right_gain_pb[5]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[0].left_loss_pb_reg[0]_1 ), .I4(\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_11 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_12 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_13 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_14 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_15 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_15_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_16 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\genblk8[0].right_gain_pb[5]_i_16_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_17 (.I0(right_edge_ref[5]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_17_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_18 (.I0(right_edge_ref[4]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\genblk8[0].right_gain_pb[5]_i_18_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[0].right_gain_pb[5]_i_19 (.I0(\genblk8[0].right_gain_pb[5]_i_27_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I2(right_edge_ref[3]), .I3(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .I4(right_edge_ref[4]), .O(\genblk8[0].right_gain_pb[5]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[0].right_gain_pb[5]_i_2 (.I0(p_154_out), .I1(\genblk8[0].right_edge_pb_reg[0]_1 ), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[0].right_edge_pb_reg[0]_0 ), .I4(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(\genblk8[0].right_gain_pb[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[0].right_gain_pb[5]_i_20 (.I0(\genblk8[0].right_gain_pb[5]_i_28_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I3(right_edge_ref[4]), .I4(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\genblk8[0].right_gain_pb[5]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_23 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_23_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_26_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[0].right_gain_pb[5]_i_27 (.I0(right_edge_ref[0]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I2(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I3(right_edge_ref[1]), .I4(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .I5(right_edge_ref[2]), .O(\genblk8[0].right_gain_pb[5]_i_27_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[0].right_gain_pb[5]_i_28 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I4(right_edge_ref[2]), .I5(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\genblk8[0].right_gain_pb[5]_i_28_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[5]_i_3 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ), .O(\genblk8[0].right_gain_pb[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_32_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_33 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_35 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_36_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_37 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_37_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_38 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_38_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_40 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_40_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_41 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_41_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_42 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_42_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_43 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_43_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[0].right_gain_pb[5]_i_44 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(right_edge_ref[4]), .I2(right_edge_ref[5]), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_44_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[0].right_gain_pb[5]_i_45 (.I0(right_edge_ref[2]), .I1(right_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_45_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[0].right_gain_pb[5]_i_46 (.I0(right_edge_ref[0]), .I1(right_edge_ref[1]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_46_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_47 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_47_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[0].right_gain_pb[5]_i_48 (.I0(right_edge_ref[4]), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(right_edge_ref[5]), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_48_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[0].right_gain_pb[5]_i_49 (.I0(right_edge_ref[2]), .I1(right_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_49_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[0].right_gain_pb[5]_i_50 (.I0(right_edge_ref[0]), .I1(right_edge_ref[1]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_50_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_52 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_52_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_53 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_53_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_54 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_54_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_55 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_55_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[0].right_gain_pb[5]_i_56 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .I2(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_56_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[0].right_gain_pb[5]_i_57 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_57_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[0].right_gain_pb[5]_i_58 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_58_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_59 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_59_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[0].right_gain_pb[5]_i_60 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_60_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[0].right_gain_pb[5]_i_61 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_61_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[0].right_gain_pb[5]_i_62 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_62_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[0].right_gain_pb[5]_i_8 (.I0(\genblk8[0].right_edge_pb_reg[0]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I4(\genblk8[0].right_gain_pb[5]_i_19_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[0].right_gain_pb[5]_i_9 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I1(right_edge_ref[5]), .I2(\genblk8[0].right_gain_pb[5]_i_20_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ), .I5(\genblk8[0].right_edge_pb_reg[0]_0 ), .O(\genblk8[0].right_gain_pb[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].right_gain_pb_reg[0] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[0]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg_n_0_[0] ), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].right_gain_pb_reg[1] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[1]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg_n_0_[1] ), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].right_gain_pb_reg[2] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[2]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [2]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].right_gain_pb_reg[3] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[3]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [3]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].right_gain_pb_reg[3]_i_2 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 }), .S({\genblk8[0].right_gain_pb[3]_i_4_n_0 ,\genblk8[0].right_gain_pb[3]_i_5_n_0 ,\genblk8[0].right_gain_pb[3]_i_6_n_0 ,\genblk8[0].right_gain_pb[3]_i_7_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[3]_i_3 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 }), .S({\genblk8[0].right_gain_pb[3]_i_8_n_0 ,\genblk8[0].right_gain_pb[3]_i_9_n_0 ,\genblk8[0].right_gain_pb[3]_i_10_n_0 ,\genblk8[0].right_gain_pb[3]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[0].right_gain_pb_reg[4] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[4]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [4]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[0].right_gain_pb_reg[5] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[5]_i_3_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [5]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_10 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_10_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_23_n_0 ,\genblk8[0].right_gain_pb[5]_i_24_n_0 ,\genblk8[0].right_gain_pb[5]_i_25_n_0 ,\genblk8[0].right_gain_pb[5]_i_26_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_21 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_21_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_30_n_0 ,\genblk8[0].right_gain_pb[5]_i_31_n_0 ,\genblk8[0].right_gain_pb[5]_i_32_n_0 ,\genblk8[0].right_gain_pb[5]_i_33_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_22 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_22_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_35_n_0 ,\genblk8[0].right_gain_pb[5]_i_36_n_0 ,\genblk8[0].right_gain_pb[5]_i_37_n_0 ,\genblk8[0].right_gain_pb[5]_i_38_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_29 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_29_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_40_n_0 ,\genblk8[0].right_gain_pb[5]_i_41_n_0 ,\genblk8[0].right_gain_pb[5]_i_42_n_0 ,\genblk8[0].right_gain_pb[5]_i_43_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_34 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_34_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[0].right_gain_pb[5]_i_44_n_0 ,\genblk8[0].right_gain_pb[5]_i_45_n_0 ,\genblk8[0].right_gain_pb[5]_i_46_n_0 }), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_47_n_0 ,\genblk8[0].right_gain_pb[5]_i_48_n_0 ,\genblk8[0].right_gain_pb[5]_i_49_n_0 ,\genblk8[0].right_gain_pb[5]_i_50_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_39 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_39_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_52_n_0 ,\genblk8[0].right_gain_pb[5]_i_53_n_0 ,\genblk8[0].right_gain_pb[5]_i_54_n_0 ,\genblk8[0].right_gain_pb[5]_i_55_n_0 })); MUXF7 \genblk8[0].right_gain_pb_reg[5]_i_4 (.I0(\genblk8[0].right_gain_pb[5]_i_8_n_0 ), .I1(\genblk8[0].right_gain_pb[5]_i_9_n_0 ), .O(\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ), .S(\genblk8[0].right_edge_pb_reg[0]_1 )); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_5 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_11_n_0 ,\genblk8[0].right_gain_pb[5]_i_12_n_0 ,\genblk8[0].right_gain_pb[5]_i_13_n_0 ,\genblk8[0].right_gain_pb[5]_i_14_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_51 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_51_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[0].right_gain_pb[5]_i_56_n_0 ,\genblk8[0].right_gain_pb[5]_i_57_n_0 ,\genblk8[0].right_gain_pb[5]_i_58_n_0 }), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_59_n_0 ,\genblk8[0].right_gain_pb[5]_i_60_n_0 ,\genblk8[0].right_gain_pb[5]_i_61_n_0 ,\genblk8[0].right_gain_pb[5]_i_62_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_6 (.CI(\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ), .CO({\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED [3:1],\genblk8[0].right_gain_pb_reg[5]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED [3:2],\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ,\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[0].right_gain_pb[5]_i_15_n_0 ,\genblk8[0].right_gain_pb[5]_i_16_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_7 (.CI(\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ), .CO({\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED [3:1],\genblk8[0].right_gain_pb_reg[5]_i_7_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED [3:2],\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ,\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 }), .S({1'b0,1'b0,\genblk8[0].right_gain_pb[5]_i_17_n_0 ,\genblk8[0].right_gain_pb[5]_i_18_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_found_pb_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk8[1].left_edge_found_pb_reg[1]_0 ), .Q(\genblk8[1].left_loss_pb_reg[6]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[1].left_edge_pb[11]_i_1 (.I0(p_154_out), .I1(p_146_out), .O(\genblk8[1].left_edge_pb[11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[1].left_edge_pb[11]_i_2 (.I0(match_flag_pb[15]), .I1(\genblk8[1].left_edge_pb[11]_i_3_n_0 ), .I2(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .I3(match_flag_pb[14]), .I4(match_flag_pb[12]), .I5(match_flag_pb[13]), .O(p_146_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[1].left_edge_pb[11]_i_3 (.I0(match_flag_pb[10]), .I1(match_flag_pb[11]), .I2(match_flag_pb[8]), .I3(match_flag_pb[9]), .O(\genblk8[1].left_edge_pb[11]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_pb_reg[10] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[10] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_pb_reg[11] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[11] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_pb_reg[6] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[6] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_pb_reg[7] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[7] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_pb_reg[8] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[8] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_pb_reg[9] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[9] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_edge_updated_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk8[1].left_edge_updated_reg[1]_0 ), .Q(D[1]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[1].left_loss_pb[11]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[1].left_loss_pb_reg[6]_0 ), .I4(p_146_out), .O(\genblk8[1].left_loss_pb[11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_loss_pb_reg[10] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_loss_pb_reg[11] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_loss_pb_reg[6] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg_n_0_[6] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_loss_pb_reg[7] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg_n_0_[7] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_loss_pb_reg[8] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].left_loss_pb_reg[9] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[10] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[9]), .Q(match_flag_pb[10]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[11] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[10]), .Q(match_flag_pb[11]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[12] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[11]), .Q(match_flag_pb[12]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[13] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[12]), .Q(match_flag_pb[13]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[14] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[13]), .Q(match_flag_pb[14]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[15] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[14]), .Q(match_flag_pb[15]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[8] (.C(CLK), .CE(p_154_out), .D(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .Q(match_flag_pb[8]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].match_flag_pb_reg[9] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[8]), .Q(match_flag_pb[9]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].right_edge_found_pb_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk8[1].right_edge_found_pb_reg[1]_0 ), .Q(\genblk8[1].right_edge_pb_reg[6]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[1].right_edge_pb[11]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_146_out), .I2(p_154_out), .I3(p_143_out), .I4(\genblk8[1].right_edge_pb_reg[6]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[1].right_edge_pb[11]_i_2 (.I0(p_154_out), .I1(p_143_out), .I2(p_146_out), .O(\genblk8[1].right_edge_pb[11]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[1].right_edge_pb[11]_i_3 (.I0(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .I1(\genblk8[1].left_edge_pb[11]_i_3_n_0 ), .I2(match_flag_pb[15]), .I3(match_flag_pb[14]), .I4(match_flag_pb[12]), .I5(match_flag_pb[13]), .O(p_143_out)); FDSE #( .INIT(1'b1)) \genblk8[1].right_edge_pb_reg[10] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].right_edge_pb_reg[11] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].right_edge_pb_reg[6] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].right_edge_pb_reg[7] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].right_edge_pb_reg[8] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[1].right_edge_pb_reg[9] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[10]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ), .I3(\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ), .O(\genblk8[1].right_gain_pb[10]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[1].right_gain_pb[11]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_146_out), .I4(\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\genblk8[1].right_gain_pb[11]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\genblk8[1].right_gain_pb[11]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\genblk8[1].right_gain_pb[11]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[1].right_gain_pb[11]_i_13 (.I0(\genblk8[1].right_gain_pb[11]_i_16_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I2(right_edge_ref[3]), .I3(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .I4(right_edge_ref[4]), .O(\genblk8[1].right_gain_pb[11]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[1].right_gain_pb[11]_i_14 (.I0(\genblk8[1].right_gain_pb[11]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I3(right_edge_ref[4]), .I4(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\genblk8[1].right_gain_pb[11]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[1].right_gain_pb[11]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I2(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I3(right_edge_ref[1]), .I4(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .I5(right_edge_ref[2]), .O(\genblk8[1].right_gain_pb[11]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[1].right_gain_pb[11]_i_17 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I4(right_edge_ref[2]), .I5(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\genblk8[1].right_gain_pb[11]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[1].right_gain_pb[11]_i_2 (.I0(p_154_out), .I1(p_143_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[1].right_edge_pb_reg[6]_0 ), .I4(p_146_out), .O(\genblk8[1].right_gain_pb[11]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[11]_i_3 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ), .I3(\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ), .O(\genblk8[1].right_gain_pb[11]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[1].right_gain_pb[11]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .I2(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[1].right_gain_pb[11]_i_34 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[1].right_gain_pb[11]_i_35 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[1].right_gain_pb[11]_i_37 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[1].right_gain_pb[11]_i_38 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[1].right_gain_pb[11]_i_39 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[1].right_gain_pb[11]_i_7 (.I0(\genblk8[1].right_edge_pb_reg[6]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I4(\genblk8[1].right_gain_pb[11]_i_13_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[1].right_gain_pb[11]_i_8 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I1(right_edge_ref[5]), .I2(\genblk8[1].right_gain_pb[11]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ), .I5(\genblk8[1].right_edge_pb_reg[6]_0 ), .O(\genblk8[1].right_gain_pb[11]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\genblk8[1].right_gain_pb[11]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[6]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ), .O(\genblk8[1].right_gain_pb[6]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[7]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ), .O(\genblk8[1].right_gain_pb[7]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[8]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ), .O(\genblk8[1].right_gain_pb[8]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[9]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ), .O(\genblk8[1].right_gain_pb[9]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\genblk8[1].right_gain_pb[9]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\genblk8[1].right_gain_pb[9]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\genblk8[1].right_gain_pb[9]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\genblk8[1].right_gain_pb[9]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\genblk8[1].right_gain_pb[9]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\genblk8[1].right_gain_pb[9]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\genblk8[1].right_gain_pb[9]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\genblk8[1].right_gain_pb[9]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].right_gain_pb_reg[10] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[10]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [4]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].right_gain_pb_reg[11] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[11]_i_3_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [5]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_15 (.CI(\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ), .CO({\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_19_n_0 ,\genblk8[1].right_gain_pb[11]_i_20_n_0 ,\genblk8[1].right_gain_pb[11]_i_21_n_0 ,\genblk8[1].right_gain_pb[11]_i_22_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_18 (.CI(\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ), .CO({\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_24_n_0 ,\genblk8[1].right_gain_pb[11]_i_25_n_0 ,\genblk8[1].right_gain_pb[11]_i_26_n_0 ,\genblk8[1].right_gain_pb[11]_i_27_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_23 (.CI(\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ), .CO({\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_29_n_0 ,\genblk8[1].right_gain_pb[11]_i_30_n_0 ,\genblk8[1].right_gain_pb[11]_i_31_n_0 ,\genblk8[1].right_gain_pb[11]_i_32_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_28 (.CI(1'b0), .CO({\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[1].right_gain_pb[11]_i_33_n_0 ,\genblk8[1].right_gain_pb[11]_i_34_n_0 ,\genblk8[1].right_gain_pb[11]_i_35_n_0 }), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_36_n_0 ,\genblk8[1].right_gain_pb[11]_i_37_n_0 ,\genblk8[1].right_gain_pb[11]_i_38_n_0 ,\genblk8[1].right_gain_pb[11]_i_39_n_0 })); MUXF7 \genblk8[1].right_gain_pb_reg[11]_i_4 (.I0(\genblk8[1].right_gain_pb[11]_i_7_n_0 ), .I1(\genblk8[1].right_gain_pb[11]_i_8_n_0 ), .O(\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ), .S(p_143_out)); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_5 (.CI(\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ), .CO({\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED [3:1],\genblk8[1].right_gain_pb_reg[11]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED [3:2],\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ,\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[1].right_gain_pb[11]_i_9_n_0 ,\genblk8[1].right_gain_pb[11]_i_10_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_6 (.CI(\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ), .CO({\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED [3:1],\genblk8[1].right_gain_pb_reg[11]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED [3:2],\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ,\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[1].right_gain_pb[11]_i_11_n_0 ,\genblk8[1].right_gain_pb[11]_i_12_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[1].right_gain_pb_reg[6] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[6]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg_n_0_[6] ), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].right_gain_pb_reg[7] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[7]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg_n_0_[7] ), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].right_gain_pb_reg[8] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[8]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [2]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[1].right_gain_pb_reg[9] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[9]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [3]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); CARRY4 \genblk8[1].right_gain_pb_reg[9]_i_2 (.CI(1'b0), .CO({\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 }), .S({\genblk8[1].right_gain_pb[9]_i_4_n_0 ,\genblk8[1].right_gain_pb[9]_i_5_n_0 ,\genblk8[1].right_gain_pb[9]_i_6_n_0 ,\genblk8[1].right_gain_pb[9]_i_7_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[9]_i_3 (.CI(1'b0), .CO({\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 }), .S({\genblk8[1].right_gain_pb[9]_i_8_n_0 ,\genblk8[1].right_gain_pb[9]_i_9_n_0 ,\genblk8[1].right_gain_pb[9]_i_10_n_0 ,\genblk8[1].right_gain_pb[9]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_found_pb_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk8[2].left_edge_found_pb_reg[2]_0 ), .Q(\genblk8[2].left_loss_pb_reg[12]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[2].left_edge_pb[17]_i_1 (.I0(p_154_out), .I1(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].left_edge_pb[17]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[2].left_edge_pb[17]_i_2 (.I0(match_flag_pb[23]), .I1(\genblk8[2].left_edge_pb[17]_i_3_n_0 ), .I2(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .I3(match_flag_pb[22]), .I4(match_flag_pb[20]), .I5(match_flag_pb[21]), .O(\genblk8[2].right_edge_pb_reg[12]_2 )); LUT4 #( .INIT(16'hFFFE)) \genblk8[2].left_edge_pb[17]_i_3 (.I0(match_flag_pb[18]), .I1(match_flag_pb[19]), .I2(match_flag_pb[16]), .I3(match_flag_pb[17]), .O(\genblk8[2].left_edge_pb[17]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_pb_reg[12] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[12] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_pb_reg[13] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[13] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_pb_reg[14] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[14] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_pb_reg[15] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[15] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_pb_reg[16] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[16] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_pb_reg[17] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[17] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_edge_updated_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk8[2].left_edge_updated_reg[2]_0 ), .Q(D[2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[2].left_loss_pb[17]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[2].left_loss_pb_reg[12]_0 ), .I4(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].left_loss_pb[17]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_loss_pb_reg[12] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg_n_0_[12] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_loss_pb_reg[13] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg_n_0_[13] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_loss_pb_reg[14] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_loss_pb_reg[15] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_loss_pb_reg[16] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].left_loss_pb_reg[17] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[16] (.C(CLK), .CE(p_154_out), .D(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .Q(match_flag_pb[16]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[17] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[16]), .Q(match_flag_pb[17]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[18] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[17]), .Q(match_flag_pb[18]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[19] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[18]), .Q(match_flag_pb[19]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[20] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[19]), .Q(match_flag_pb[20]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[21] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[20]), .Q(match_flag_pb[21]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[22] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[21]), .Q(match_flag_pb[22]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].match_flag_pb_reg[23] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[22]), .Q(match_flag_pb[23]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].right_edge_found_pb_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk8[2].right_edge_found_pb_reg[2]_0 ), .Q(\genblk8[2].right_edge_pb_reg[12]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[2].right_edge_pb[17]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(\genblk8[2].right_edge_pb_reg[12]_2 ), .I2(p_154_out), .I3(\genblk8[2].right_edge_pb_reg[12]_1 ), .I4(\genblk8[2].right_edge_pb_reg[12]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[2].right_edge_pb[17]_i_2 (.I0(p_154_out), .I1(\genblk8[2].right_edge_pb_reg[12]_1 ), .I2(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].right_edge_pb[17]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[2].right_edge_pb[17]_i_3 (.I0(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .I1(\genblk8[2].left_edge_pb[17]_i_3_n_0 ), .I2(match_flag_pb[23]), .I3(match_flag_pb[22]), .I4(match_flag_pb[20]), .I5(match_flag_pb[21]), .O(\genblk8[2].right_edge_pb_reg[12]_1 )); FDSE #( .INIT(1'b1)) \genblk8[2].right_edge_pb_reg[12] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].right_edge_pb_reg[13] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].right_edge_pb_reg[14] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].right_edge_pb_reg[15] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].right_edge_pb_reg[16] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[2].right_edge_pb_reg[17] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[12]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ), .O(\genblk8[2].right_gain_pb[12]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[13]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ), .O(\genblk8[2].right_gain_pb[13]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[14]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ), .O(\genblk8[2].right_gain_pb[14]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[15]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ), .O(\genblk8[2].right_gain_pb[15]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\genblk8[2].right_gain_pb[15]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\genblk8[2].right_gain_pb[15]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\genblk8[2].right_gain_pb[15]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\genblk8[2].right_gain_pb[15]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\genblk8[2].right_gain_pb[15]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\genblk8[2].right_gain_pb[15]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\genblk8[2].right_gain_pb[15]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\genblk8[2].right_gain_pb[15]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[16]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ), .I3(\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ), .O(\genblk8[2].right_gain_pb[16]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[2].right_gain_pb[17]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[2].right_edge_pb_reg[12]_2 ), .I4(\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .O(\genblk8[2].right_gain_pb[17]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .O(\genblk8[2].right_gain_pb[17]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .O(\genblk8[2].right_gain_pb[17]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[2].right_gain_pb[17]_i_13 (.I0(\genblk8[2].right_gain_pb[17]_i_16_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I2(right_edge_ref[3]), .I3(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I4(right_edge_ref[4]), .O(\genblk8[2].right_gain_pb[17]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[2].right_gain_pb[17]_i_14 (.I0(\genblk8[2].right_gain_pb[17]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I3(right_edge_ref[4]), .I4(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .O(\genblk8[2].right_gain_pb[17]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[2].right_gain_pb[17]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I2(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I3(right_edge_ref[1]), .I4(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .I5(right_edge_ref[2]), .O(\genblk8[2].right_gain_pb[17]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[2].right_gain_pb[17]_i_17 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I4(right_edge_ref[2]), .I5(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\genblk8[2].right_gain_pb[17]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[2].right_gain_pb[17]_i_2 (.I0(p_154_out), .I1(\genblk8[2].right_edge_pb_reg[12]_1 ), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[2].right_edge_pb_reg[12]_0 ), .I4(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].right_gain_pb[17]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[17]_i_3 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ), .I3(\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ), .O(\genblk8[2].right_gain_pb[17]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[2].right_gain_pb[17]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I2(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[2].right_gain_pb[17]_i_34 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[2].right_gain_pb[17]_i_35 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[2].right_gain_pb[17]_i_37 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[2].right_gain_pb[17]_i_38 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[2].right_gain_pb[17]_i_39 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[2].right_gain_pb[17]_i_7 (.I0(\genblk8[2].right_edge_pb_reg[12]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I4(\genblk8[2].right_gain_pb[17]_i_13_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[2].right_gain_pb[17]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(right_edge_ref[5]), .I2(\genblk8[2].right_gain_pb[17]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ), .I5(\genblk8[2].right_edge_pb_reg[12]_0 ), .O(\genblk8[2].right_gain_pb[17]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .O(\genblk8[2].right_gain_pb[17]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].right_gain_pb_reg[12] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[12]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg_n_0_[12] ), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].right_gain_pb_reg[13] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[13]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg_n_0_[13] ), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].right_gain_pb_reg[14] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[14]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [2]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].right_gain_pb_reg[15] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[15]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [3]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); CARRY4 \genblk8[2].right_gain_pb_reg[15]_i_2 (.CI(1'b0), .CO({\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 }), .S({\genblk8[2].right_gain_pb[15]_i_4_n_0 ,\genblk8[2].right_gain_pb[15]_i_5_n_0 ,\genblk8[2].right_gain_pb[15]_i_6_n_0 ,\genblk8[2].right_gain_pb[15]_i_7_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[15]_i_3 (.CI(1'b0), .CO({\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 }), .S({\genblk8[2].right_gain_pb[15]_i_8_n_0 ,\genblk8[2].right_gain_pb[15]_i_9_n_0 ,\genblk8[2].right_gain_pb[15]_i_10_n_0 ,\genblk8[2].right_gain_pb[15]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[2].right_gain_pb_reg[16] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[16]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [4]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[2].right_gain_pb_reg[17] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[17]_i_3_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [5]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_15 (.CI(\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ), .CO({\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_19_n_0 ,\genblk8[2].right_gain_pb[17]_i_20_n_0 ,\genblk8[2].right_gain_pb[17]_i_21_n_0 ,\genblk8[2].right_gain_pb[17]_i_22_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_18 (.CI(\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ), .CO({\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_24_n_0 ,\genblk8[2].right_gain_pb[17]_i_25_n_0 ,\genblk8[2].right_gain_pb[17]_i_26_n_0 ,\genblk8[2].right_gain_pb[17]_i_27_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_23 (.CI(\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ), .CO({\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_29_n_0 ,\genblk8[2].right_gain_pb[17]_i_30_n_0 ,\genblk8[2].right_gain_pb[17]_i_31_n_0 ,\genblk8[2].right_gain_pb[17]_i_32_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_28 (.CI(1'b0), .CO({\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[2].right_gain_pb[17]_i_33_n_0 ,\genblk8[2].right_gain_pb[17]_i_34_n_0 ,\genblk8[2].right_gain_pb[17]_i_35_n_0 }), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_36_n_0 ,\genblk8[2].right_gain_pb[17]_i_37_n_0 ,\genblk8[2].right_gain_pb[17]_i_38_n_0 ,\genblk8[2].right_gain_pb[17]_i_39_n_0 })); MUXF7 \genblk8[2].right_gain_pb_reg[17]_i_4 (.I0(\genblk8[2].right_gain_pb[17]_i_7_n_0 ), .I1(\genblk8[2].right_gain_pb[17]_i_8_n_0 ), .O(\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ), .S(\genblk8[2].right_edge_pb_reg[12]_1 )); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_5 (.CI(\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ), .CO({\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED [3:1],\genblk8[2].right_gain_pb_reg[17]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED [3:2],\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ,\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[2].right_gain_pb[17]_i_9_n_0 ,\genblk8[2].right_gain_pb[17]_i_10_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_6 (.CI(\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ), .CO({\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED [3:1],\genblk8[2].right_gain_pb_reg[17]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED [3:2],\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ,\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[2].right_gain_pb[17]_i_11_n_0 ,\genblk8[2].right_gain_pb[17]_i_12_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_found_pb_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk8[3].left_edge_found_pb_reg[3]_0 ), .Q(\genblk8[3].left_loss_pb_reg[18]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[3].left_edge_pb[23]_i_1 (.I0(p_154_out), .I1(p_130_out), .O(\genblk8[3].left_edge_pb[23]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[3].left_edge_pb[23]_i_2 (.I0(match_flag_pb[31]), .I1(\genblk8[3].left_edge_pb[23]_i_3_n_0 ), .I2(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .I3(match_flag_pb[30]), .I4(match_flag_pb[28]), .I5(match_flag_pb[29]), .O(p_130_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[3].left_edge_pb[23]_i_3 (.I0(match_flag_pb[26]), .I1(match_flag_pb[27]), .I2(match_flag_pb[24]), .I3(match_flag_pb[25]), .O(\genblk8[3].left_edge_pb[23]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_pb_reg[18] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[18] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_pb_reg[19] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[19] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_pb_reg[20] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[20] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_pb_reg[21] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[21] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_pb_reg[22] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[22] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_pb_reg[23] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[23] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_edge_updated_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk8[3].left_edge_updated_reg[3]_0 ), .Q(D[3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[3].left_loss_pb[23]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[3].left_loss_pb_reg[18]_0 ), .I4(p_130_out), .O(\genblk8[3].left_loss_pb[23]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_loss_pb_reg[18] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg_n_0_[18] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_loss_pb_reg[19] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg_n_0_[19] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_loss_pb_reg[20] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_loss_pb_reg[21] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_loss_pb_reg[22] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].left_loss_pb_reg[23] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[24] (.C(CLK), .CE(p_154_out), .D(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .Q(match_flag_pb[24]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[25] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[24]), .Q(match_flag_pb[25]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[26] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[25]), .Q(match_flag_pb[26]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[27] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[26]), .Q(match_flag_pb[27]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[28] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[27]), .Q(match_flag_pb[28]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[29] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[28]), .Q(match_flag_pb[29]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[30] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[29]), .Q(match_flag_pb[30]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].match_flag_pb_reg[31] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[30]), .Q(match_flag_pb[31]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].right_edge_found_pb_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk8[3].right_edge_found_pb_reg[3]_0 ), .Q(\genblk8[3].right_edge_pb_reg[18]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[3].right_edge_pb[23]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_130_out), .I2(p_154_out), .I3(p_127_out), .I4(\genblk8[3].right_edge_pb_reg[18]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[3].right_edge_pb[23]_i_2 (.I0(p_154_out), .I1(p_127_out), .I2(p_130_out), .O(\genblk8[3].right_edge_pb[23]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[3].right_edge_pb[23]_i_3 (.I0(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .I1(\genblk8[3].left_edge_pb[23]_i_3_n_0 ), .I2(match_flag_pb[31]), .I3(match_flag_pb[30]), .I4(match_flag_pb[28]), .I5(match_flag_pb[29]), .O(p_127_out)); FDSE #( .INIT(1'b1)) \genblk8[3].right_edge_pb_reg[18] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].right_edge_pb_reg[19] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].right_edge_pb_reg[20] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].right_edge_pb_reg[21] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].right_edge_pb_reg[22] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[3].right_edge_pb_reg[23] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[18]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ), .O(\genblk8[3].right_gain_pb[18]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[19]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ), .O(\genblk8[3].right_gain_pb[19]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[20]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ), .O(\genblk8[3].right_gain_pb[20]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[21]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ), .O(\genblk8[3].right_gain_pb[21]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .O(\genblk8[3].right_gain_pb[21]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .O(\genblk8[3].right_gain_pb[21]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .O(\genblk8[3].right_gain_pb[21]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .O(\genblk8[3].right_gain_pb[21]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .O(\genblk8[3].right_gain_pb[21]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .O(\genblk8[3].right_gain_pb[21]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .O(\genblk8[3].right_gain_pb[21]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .O(\genblk8[3].right_gain_pb[21]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[22]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ), .I3(\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ), .O(\genblk8[3].right_gain_pb[22]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[3].right_gain_pb[23]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_130_out), .I4(\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .O(\genblk8[3].right_gain_pb[23]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .O(\genblk8[3].right_gain_pb[23]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .O(\genblk8[3].right_gain_pb[23]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[3].right_gain_pb[23]_i_13 (.I0(\genblk8[3].right_gain_pb[23]_i_16_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I2(right_edge_ref[3]), .I3(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I4(right_edge_ref[4]), .O(\genblk8[3].right_gain_pb[23]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[3].right_gain_pb[23]_i_14 (.I0(\genblk8[3].right_gain_pb[23]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I3(right_edge_ref[4]), .I4(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .O(\genblk8[3].right_gain_pb[23]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[3].right_gain_pb[23]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I2(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I3(right_edge_ref[1]), .I4(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I5(right_edge_ref[2]), .O(\genblk8[3].right_gain_pb[23]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[3].right_gain_pb[23]_i_17 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I4(right_edge_ref[2]), .I5(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .O(\genblk8[3].right_gain_pb[23]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[3].right_gain_pb[23]_i_2 (.I0(p_154_out), .I1(p_127_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[3].right_edge_pb_reg[18]_0 ), .I4(p_130_out), .O(\genblk8[3].right_gain_pb[23]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[23]_i_3 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ), .I3(\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ), .O(\genblk8[3].right_gain_pb[23]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[3].right_gain_pb[23]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I2(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[3].right_gain_pb[23]_i_34 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[3].right_gain_pb[23]_i_35 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[3].right_gain_pb[23]_i_37 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[3].right_gain_pb[23]_i_38 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[3].right_gain_pb[23]_i_39 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[3].right_gain_pb[23]_i_7 (.I0(\genblk8[3].right_edge_pb_reg[18]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I4(\genblk8[3].right_gain_pb[23]_i_13_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[3].right_gain_pb[23]_i_8 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I1(right_edge_ref[5]), .I2(\genblk8[3].right_gain_pb[23]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ), .I5(\genblk8[3].right_edge_pb_reg[18]_0 ), .O(\genblk8[3].right_gain_pb[23]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .O(\genblk8[3].right_gain_pb[23]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].right_gain_pb_reg[18] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[18]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg_n_0_[18] ), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].right_gain_pb_reg[19] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[19]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg_n_0_[19] ), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].right_gain_pb_reg[20] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[20]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [2]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].right_gain_pb_reg[21] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[21]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [3]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); CARRY4 \genblk8[3].right_gain_pb_reg[21]_i_2 (.CI(1'b0), .CO({\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 }), .S({\genblk8[3].right_gain_pb[21]_i_4_n_0 ,\genblk8[3].right_gain_pb[21]_i_5_n_0 ,\genblk8[3].right_gain_pb[21]_i_6_n_0 ,\genblk8[3].right_gain_pb[21]_i_7_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[21]_i_3 (.CI(1'b0), .CO({\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 }), .S({\genblk8[3].right_gain_pb[21]_i_8_n_0 ,\genblk8[3].right_gain_pb[21]_i_9_n_0 ,\genblk8[3].right_gain_pb[21]_i_10_n_0 ,\genblk8[3].right_gain_pb[21]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[3].right_gain_pb_reg[22] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[22]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [4]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[3].right_gain_pb_reg[23] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[23]_i_3_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [5]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_15 (.CI(\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ), .CO({\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_19_n_0 ,\genblk8[3].right_gain_pb[23]_i_20_n_0 ,\genblk8[3].right_gain_pb[23]_i_21_n_0 ,\genblk8[3].right_gain_pb[23]_i_22_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_18 (.CI(\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ), .CO({\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_24_n_0 ,\genblk8[3].right_gain_pb[23]_i_25_n_0 ,\genblk8[3].right_gain_pb[23]_i_26_n_0 ,\genblk8[3].right_gain_pb[23]_i_27_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_23 (.CI(\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ), .CO({\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_29_n_0 ,\genblk8[3].right_gain_pb[23]_i_30_n_0 ,\genblk8[3].right_gain_pb[23]_i_31_n_0 ,\genblk8[3].right_gain_pb[23]_i_32_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_28 (.CI(1'b0), .CO({\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[3].right_gain_pb[23]_i_33_n_0 ,\genblk8[3].right_gain_pb[23]_i_34_n_0 ,\genblk8[3].right_gain_pb[23]_i_35_n_0 }), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_36_n_0 ,\genblk8[3].right_gain_pb[23]_i_37_n_0 ,\genblk8[3].right_gain_pb[23]_i_38_n_0 ,\genblk8[3].right_gain_pb[23]_i_39_n_0 })); MUXF7 \genblk8[3].right_gain_pb_reg[23]_i_4 (.I0(\genblk8[3].right_gain_pb[23]_i_7_n_0 ), .I1(\genblk8[3].right_gain_pb[23]_i_8_n_0 ), .O(\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ), .S(p_127_out)); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_5 (.CI(\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ), .CO({\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED [3:1],\genblk8[3].right_gain_pb_reg[23]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED [3:2],\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ,\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[3].right_gain_pb[23]_i_9_n_0 ,\genblk8[3].right_gain_pb[23]_i_10_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_6 (.CI(\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ), .CO({\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED [3:1],\genblk8[3].right_gain_pb_reg[23]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED [3:2],\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ,\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[3].right_gain_pb[23]_i_11_n_0 ,\genblk8[3].right_gain_pb[23]_i_12_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_found_pb_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk8[4].left_edge_found_pb_reg[4]_0 ), .Q(\genblk8[4].left_loss_pb_reg[24]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[4].left_edge_pb[29]_i_1 (.I0(p_154_out), .I1(p_122_out), .O(\genblk8[4].left_edge_pb[29]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[4].left_edge_pb[29]_i_2 (.I0(match_flag_pb[39]), .I1(\genblk8[4].left_edge_pb[29]_i_3_n_0 ), .I2(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .I3(match_flag_pb[38]), .I4(match_flag_pb[36]), .I5(match_flag_pb[37]), .O(p_122_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[4].left_edge_pb[29]_i_3 (.I0(match_flag_pb[34]), .I1(match_flag_pb[35]), .I2(match_flag_pb[32]), .I3(match_flag_pb[33]), .O(\genblk8[4].left_edge_pb[29]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_pb_reg[24] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[24] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_pb_reg[25] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[25] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_pb_reg[26] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[26] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_pb_reg[27] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[27] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_pb_reg[28] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[28] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_pb_reg[29] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[29] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_edge_updated_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk8[4].left_edge_updated_reg[4]_0 ), .Q(D[4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[4].left_loss_pb[29]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[4].left_loss_pb_reg[24]_0 ), .I4(p_122_out), .O(\genblk8[4].left_loss_pb[29]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_loss_pb_reg[24] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg_n_0_[24] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_loss_pb_reg[25] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg_n_0_[25] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_loss_pb_reg[26] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_loss_pb_reg[27] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_loss_pb_reg[28] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].left_loss_pb_reg[29] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[32] (.C(CLK), .CE(p_154_out), .D(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .Q(match_flag_pb[32]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[33] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[32]), .Q(match_flag_pb[33]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[34] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[33]), .Q(match_flag_pb[34]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[35] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[34]), .Q(match_flag_pb[35]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[36] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[35]), .Q(match_flag_pb[36]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[37] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[36]), .Q(match_flag_pb[37]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[38] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[37]), .Q(match_flag_pb[38]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].match_flag_pb_reg[39] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[38]), .Q(match_flag_pb[39]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].right_edge_found_pb_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk8[4].right_edge_found_pb_reg[4]_0 ), .Q(\genblk8[4].right_edge_pb_reg[24]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[4].right_edge_pb[29]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_122_out), .I2(p_154_out), .I3(p_119_out), .I4(\genblk8[4].right_edge_pb_reg[24]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[4].right_edge_pb[29]_i_2 (.I0(p_154_out), .I1(p_119_out), .I2(p_122_out), .O(\genblk8[4].right_edge_pb[29]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[4].right_edge_pb[29]_i_3 (.I0(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .I1(\genblk8[4].left_edge_pb[29]_i_3_n_0 ), .I2(match_flag_pb[39]), .I3(match_flag_pb[38]), .I4(match_flag_pb[36]), .I5(match_flag_pb[37]), .O(p_119_out)); FDSE #( .INIT(1'b1)) \genblk8[4].right_edge_pb_reg[24] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].right_edge_pb_reg[25] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].right_edge_pb_reg[26] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].right_edge_pb_reg[27] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].right_edge_pb_reg[28] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[4].right_edge_pb_reg[29] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[24]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ), .O(\genblk8[4].right_gain_pb[24]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[25]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ), .O(\genblk8[4].right_gain_pb[25]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[26]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ), .O(\genblk8[4].right_gain_pb[26]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[27]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ), .O(\genblk8[4].right_gain_pb[27]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .O(\genblk8[4].right_gain_pb[27]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .O(\genblk8[4].right_gain_pb[27]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .O(\genblk8[4].right_gain_pb[27]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .O(\genblk8[4].right_gain_pb[27]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .O(\genblk8[4].right_gain_pb[27]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .O(\genblk8[4].right_gain_pb[27]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .O(\genblk8[4].right_gain_pb[27]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .O(\genblk8[4].right_gain_pb[27]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[28]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ), .I3(\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ), .O(\genblk8[4].right_gain_pb[28]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[4].right_gain_pb[29]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_122_out), .I4(\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .O(\genblk8[4].right_gain_pb[29]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .O(\genblk8[4].right_gain_pb[29]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .O(\genblk8[4].right_gain_pb[29]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[4].right_gain_pb[29]_i_13 (.I0(\genblk8[4].right_gain_pb[29]_i_16_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I2(right_edge_ref[3]), .I3(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I4(right_edge_ref[4]), .O(\genblk8[4].right_gain_pb[29]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[4].right_gain_pb[29]_i_14 (.I0(\genblk8[4].right_gain_pb[29]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I3(right_edge_ref[4]), .I4(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .O(\genblk8[4].right_gain_pb[29]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[4].right_gain_pb[29]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I2(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I3(right_edge_ref[1]), .I4(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I5(right_edge_ref[2]), .O(\genblk8[4].right_gain_pb[29]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[4].right_gain_pb[29]_i_17 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I4(right_edge_ref[2]), .I5(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .O(\genblk8[4].right_gain_pb[29]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[4].right_gain_pb[29]_i_2 (.I0(p_154_out), .I1(p_119_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[4].right_edge_pb_reg[24]_0 ), .I4(p_122_out), .O(\genblk8[4].right_gain_pb[29]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[29]_i_3 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ), .I3(\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ), .O(\genblk8[4].right_gain_pb[29]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[4].right_gain_pb[29]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I2(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[4].right_gain_pb[29]_i_34 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[4].right_gain_pb[29]_i_35 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[4].right_gain_pb[29]_i_37 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[4].right_gain_pb[29]_i_38 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[4].right_gain_pb[29]_i_39 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[4].right_gain_pb[29]_i_7 (.I0(\genblk8[4].right_edge_pb_reg[24]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I4(\genblk8[4].right_gain_pb[29]_i_13_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[4].right_gain_pb[29]_i_8 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I1(right_edge_ref[5]), .I2(\genblk8[4].right_gain_pb[29]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ), .I5(\genblk8[4].right_edge_pb_reg[24]_0 ), .O(\genblk8[4].right_gain_pb[29]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .O(\genblk8[4].right_gain_pb[29]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].right_gain_pb_reg[24] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[24]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg_n_0_[24] ), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].right_gain_pb_reg[25] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[25]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg_n_0_[25] ), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].right_gain_pb_reg[26] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[26]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [2]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].right_gain_pb_reg[27] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[27]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [3]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); CARRY4 \genblk8[4].right_gain_pb_reg[27]_i_2 (.CI(1'b0), .CO({\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 }), .S({\genblk8[4].right_gain_pb[27]_i_4_n_0 ,\genblk8[4].right_gain_pb[27]_i_5_n_0 ,\genblk8[4].right_gain_pb[27]_i_6_n_0 ,\genblk8[4].right_gain_pb[27]_i_7_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[27]_i_3 (.CI(1'b0), .CO({\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 }), .S({\genblk8[4].right_gain_pb[27]_i_8_n_0 ,\genblk8[4].right_gain_pb[27]_i_9_n_0 ,\genblk8[4].right_gain_pb[27]_i_10_n_0 ,\genblk8[4].right_gain_pb[27]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[4].right_gain_pb_reg[28] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[28]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [4]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[4].right_gain_pb_reg[29] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[29]_i_3_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [5]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_15 (.CI(\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ), .CO({\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_19_n_0 ,\genblk8[4].right_gain_pb[29]_i_20_n_0 ,\genblk8[4].right_gain_pb[29]_i_21_n_0 ,\genblk8[4].right_gain_pb[29]_i_22_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_18 (.CI(\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ), .CO({\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_24_n_0 ,\genblk8[4].right_gain_pb[29]_i_25_n_0 ,\genblk8[4].right_gain_pb[29]_i_26_n_0 ,\genblk8[4].right_gain_pb[29]_i_27_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_23 (.CI(\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ), .CO({\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_29_n_0 ,\genblk8[4].right_gain_pb[29]_i_30_n_0 ,\genblk8[4].right_gain_pb[29]_i_31_n_0 ,\genblk8[4].right_gain_pb[29]_i_32_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_28 (.CI(1'b0), .CO({\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[4].right_gain_pb[29]_i_33_n_0 ,\genblk8[4].right_gain_pb[29]_i_34_n_0 ,\genblk8[4].right_gain_pb[29]_i_35_n_0 }), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_36_n_0 ,\genblk8[4].right_gain_pb[29]_i_37_n_0 ,\genblk8[4].right_gain_pb[29]_i_38_n_0 ,\genblk8[4].right_gain_pb[29]_i_39_n_0 })); MUXF7 \genblk8[4].right_gain_pb_reg[29]_i_4 (.I0(\genblk8[4].right_gain_pb[29]_i_7_n_0 ), .I1(\genblk8[4].right_gain_pb[29]_i_8_n_0 ), .O(\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ), .S(p_119_out)); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_5 (.CI(\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ), .CO({\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED [3:1],\genblk8[4].right_gain_pb_reg[29]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED [3:2],\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ,\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[4].right_gain_pb[29]_i_9_n_0 ,\genblk8[4].right_gain_pb[29]_i_10_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_6 (.CI(\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ), .CO({\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED [3:1],\genblk8[4].right_gain_pb_reg[29]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED [3:2],\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ,\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[4].right_gain_pb[29]_i_11_n_0 ,\genblk8[4].right_gain_pb[29]_i_12_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_found_pb_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk8[5].left_edge_found_pb_reg[5]_0 ), .Q(\genblk8[5].left_loss_pb_reg[30]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[5].left_edge_pb[35]_i_1 (.I0(p_154_out), .I1(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].left_edge_pb[35]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[5].left_edge_pb[35]_i_2 (.I0(match_flag_pb[47]), .I1(\genblk8[5].left_edge_pb[35]_i_3_n_0 ), .I2(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .I3(match_flag_pb[46]), .I4(match_flag_pb[44]), .I5(match_flag_pb[45]), .O(\genblk8[5].right_gain_pb_reg[30]_0 )); LUT4 #( .INIT(16'hFFFE)) \genblk8[5].left_edge_pb[35]_i_3 (.I0(match_flag_pb[42]), .I1(match_flag_pb[43]), .I2(match_flag_pb[40]), .I3(match_flag_pb[41]), .O(\genblk8[5].left_edge_pb[35]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_pb_reg[30] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[30] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_pb_reg[31] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[31] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_pb_reg[32] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[32] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_pb_reg[33] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[33] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_pb_reg[34] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[34] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_pb_reg[35] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[35] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_edge_updated_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk8[5].left_edge_updated_reg[5]_0 ), .Q(D[5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[5].left_loss_pb[35]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[5].left_loss_pb_reg[30]_0 ), .I4(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].left_loss_pb[35]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_loss_pb_reg[30] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg_n_0_[30] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_loss_pb_reg[31] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg_n_0_[31] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_loss_pb_reg[32] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_loss_pb_reg[33] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_loss_pb_reg[34] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].left_loss_pb_reg[35] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[40] (.C(CLK), .CE(p_154_out), .D(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .Q(match_flag_pb[40]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[41] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[40]), .Q(match_flag_pb[41]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[42] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[41]), .Q(match_flag_pb[42]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[43] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[42]), .Q(match_flag_pb[43]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[44] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[43]), .Q(match_flag_pb[44]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[45] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[44]), .Q(match_flag_pb[45]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[46] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[45]), .Q(match_flag_pb[46]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].match_flag_pb_reg[47] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[46]), .Q(match_flag_pb[47]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].right_edge_found_pb_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk8[5].right_edge_found_pb_reg[5]_0 ), .Q(\genblk8[5].right_edge_pb_reg[30]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[5].right_edge_pb[35]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(\genblk8[5].right_gain_pb_reg[30]_0 ), .I2(p_154_out), .I3(\genblk8[5].right_edge_pb_reg[30]_1 ), .I4(\genblk8[5].right_edge_pb_reg[30]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[5].right_edge_pb[35]_i_2 (.I0(p_154_out), .I1(\genblk8[5].right_edge_pb_reg[30]_1 ), .I2(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].right_edge_pb[35]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[5].right_edge_pb[35]_i_3 (.I0(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .I1(\genblk8[5].left_edge_pb[35]_i_3_n_0 ), .I2(match_flag_pb[47]), .I3(match_flag_pb[46]), .I4(match_flag_pb[44]), .I5(match_flag_pb[45]), .O(\genblk8[5].right_edge_pb_reg[30]_1 )); FDSE #( .INIT(1'b1)) \genblk8[5].right_edge_pb_reg[30] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].right_edge_pb_reg[31] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].right_edge_pb_reg[32] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].right_edge_pb_reg[33] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].right_edge_pb_reg[34] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[5].right_edge_pb_reg[35] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[30]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ), .O(\genblk8[5].right_gain_pb[30]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[31]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ), .O(\genblk8[5].right_gain_pb[31]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[32]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ), .O(\genblk8[5].right_gain_pb[32]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[33]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ), .O(\genblk8[5].right_gain_pb[33]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .O(\genblk8[5].right_gain_pb[33]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .O(\genblk8[5].right_gain_pb[33]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .O(\genblk8[5].right_gain_pb[33]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .O(\genblk8[5].right_gain_pb[33]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .O(\genblk8[5].right_gain_pb[33]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .O(\genblk8[5].right_gain_pb[33]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .O(\genblk8[5].right_gain_pb[33]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .O(\genblk8[5].right_gain_pb[33]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[34]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ), .I3(\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ), .O(\genblk8[5].right_gain_pb[34]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[5].right_gain_pb[35]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[5].right_gain_pb_reg[30]_0 ), .I4(\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .O(\genblk8[5].right_gain_pb[35]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .O(\genblk8[5].right_gain_pb[35]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .O(\genblk8[5].right_gain_pb[35]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[5].right_gain_pb[35]_i_13 (.I0(\genblk8[5].right_gain_pb[35]_i_16_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I2(right_edge_ref[3]), .I3(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I4(right_edge_ref[4]), .O(\genblk8[5].right_gain_pb[35]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[5].right_gain_pb[35]_i_14 (.I0(\genblk8[5].right_gain_pb[35]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(right_edge_ref[4]), .I4(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .O(\genblk8[5].right_gain_pb[35]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[5].right_gain_pb[35]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I3(right_edge_ref[1]), .I4(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I5(right_edge_ref[2]), .O(\genblk8[5].right_gain_pb[35]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[5].right_gain_pb[35]_i_17 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I4(right_edge_ref[2]), .I5(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .O(\genblk8[5].right_gain_pb[35]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[5].right_gain_pb[35]_i_2 (.I0(p_154_out), .I1(\genblk8[5].right_edge_pb_reg[30]_1 ), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[5].right_edge_pb_reg[30]_0 ), .I4(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].right_gain_pb[35]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[35]_i_3 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ), .I3(\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ), .O(\genblk8[5].right_gain_pb[35]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[5].right_gain_pb[35]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[5].right_gain_pb[35]_i_34 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[5].right_gain_pb[35]_i_35 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[5].right_gain_pb[35]_i_37 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[5].right_gain_pb[35]_i_38 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[5].right_gain_pb[35]_i_39 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[5].right_gain_pb[35]_i_7 (.I0(\genblk8[5].right_edge_pb_reg[30]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I4(\genblk8[5].right_gain_pb[35]_i_13_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[5].right_gain_pb[35]_i_8 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I1(right_edge_ref[5]), .I2(\genblk8[5].right_gain_pb[35]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ), .I5(\genblk8[5].right_edge_pb_reg[30]_0 ), .O(\genblk8[5].right_gain_pb[35]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .O(\genblk8[5].right_gain_pb[35]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].right_gain_pb_reg[30] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[30]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg_n_0_[30] ), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].right_gain_pb_reg[31] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[31]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg_n_0_[31] ), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].right_gain_pb_reg[32] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[32]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [2]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].right_gain_pb_reg[33] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[33]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [3]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); CARRY4 \genblk8[5].right_gain_pb_reg[33]_i_2 (.CI(1'b0), .CO({\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 }), .S({\genblk8[5].right_gain_pb[33]_i_4_n_0 ,\genblk8[5].right_gain_pb[33]_i_5_n_0 ,\genblk8[5].right_gain_pb[33]_i_6_n_0 ,\genblk8[5].right_gain_pb[33]_i_7_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[33]_i_3 (.CI(1'b0), .CO({\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 }), .S({\genblk8[5].right_gain_pb[33]_i_8_n_0 ,\genblk8[5].right_gain_pb[33]_i_9_n_0 ,\genblk8[5].right_gain_pb[33]_i_10_n_0 ,\genblk8[5].right_gain_pb[33]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[5].right_gain_pb_reg[34] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[34]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [4]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[5].right_gain_pb_reg[35] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[35]_i_3_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [5]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_15 (.CI(\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ), .CO({\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_19_n_0 ,\genblk8[5].right_gain_pb[35]_i_20_n_0 ,\genblk8[5].right_gain_pb[35]_i_21_n_0 ,\genblk8[5].right_gain_pb[35]_i_22_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_18 (.CI(\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ), .CO({\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_24_n_0 ,\genblk8[5].right_gain_pb[35]_i_25_n_0 ,\genblk8[5].right_gain_pb[35]_i_26_n_0 ,\genblk8[5].right_gain_pb[35]_i_27_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_23 (.CI(\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ), .CO({\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_29_n_0 ,\genblk8[5].right_gain_pb[35]_i_30_n_0 ,\genblk8[5].right_gain_pb[35]_i_31_n_0 ,\genblk8[5].right_gain_pb[35]_i_32_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_28 (.CI(1'b0), .CO({\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[5].right_gain_pb[35]_i_33_n_0 ,\genblk8[5].right_gain_pb[35]_i_34_n_0 ,\genblk8[5].right_gain_pb[35]_i_35_n_0 }), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_36_n_0 ,\genblk8[5].right_gain_pb[35]_i_37_n_0 ,\genblk8[5].right_gain_pb[35]_i_38_n_0 ,\genblk8[5].right_gain_pb[35]_i_39_n_0 })); MUXF7 \genblk8[5].right_gain_pb_reg[35]_i_4 (.I0(\genblk8[5].right_gain_pb[35]_i_7_n_0 ), .I1(\genblk8[5].right_gain_pb[35]_i_8_n_0 ), .O(\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ), .S(\genblk8[5].right_edge_pb_reg[30]_1 )); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_5 (.CI(\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ), .CO({\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED [3:1],\genblk8[5].right_gain_pb_reg[35]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED [3:2],\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ,\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[5].right_gain_pb[35]_i_9_n_0 ,\genblk8[5].right_gain_pb[35]_i_10_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_6 (.CI(\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ), .CO({\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED [3:1],\genblk8[5].right_gain_pb_reg[35]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED [3:2],\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ,\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[5].right_gain_pb[35]_i_11_n_0 ,\genblk8[5].right_gain_pb[35]_i_12_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_found_pb_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk8[6].left_edge_found_pb_reg[6]_0 ), .Q(\genblk8[6].left_loss_pb_reg[36]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[6].left_edge_pb[41]_i_1 (.I0(p_154_out), .I1(p_106_out), .O(\genblk8[6].left_edge_pb[41]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[6].left_edge_pb[41]_i_2 (.I0(match_flag_pb[55]), .I1(\genblk8[6].left_edge_pb[41]_i_3_n_0 ), .I2(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .I3(match_flag_pb[54]), .I4(match_flag_pb[52]), .I5(match_flag_pb[53]), .O(p_106_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[6].left_edge_pb[41]_i_3 (.I0(match_flag_pb[50]), .I1(match_flag_pb[51]), .I2(match_flag_pb[48]), .I3(match_flag_pb[49]), .O(\genblk8[6].left_edge_pb[41]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_pb_reg[36] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[36] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_pb_reg[37] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[37] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_pb_reg[38] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[38] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_pb_reg[39] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[39] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_pb_reg[40] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[40] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_pb_reg[41] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[41] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_edge_updated_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk8[6].left_edge_updated_reg[6]_0 ), .Q(D[6]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[6].left_loss_pb[41]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[6].left_loss_pb_reg[36]_0 ), .I4(p_106_out), .O(\genblk8[6].left_loss_pb[41]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_loss_pb_reg[36] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg_n_0_[36] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_loss_pb_reg[37] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg_n_0_[37] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_loss_pb_reg[38] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_loss_pb_reg[39] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_loss_pb_reg[40] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].left_loss_pb_reg[41] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[48] (.C(CLK), .CE(p_154_out), .D(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .Q(match_flag_pb[48]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[49] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[48]), .Q(match_flag_pb[49]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[50] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[49]), .Q(match_flag_pb[50]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[51] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[50]), .Q(match_flag_pb[51]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[52] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[51]), .Q(match_flag_pb[52]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[53] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[52]), .Q(match_flag_pb[53]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[54] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[53]), .Q(match_flag_pb[54]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].match_flag_pb_reg[55] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[54]), .Q(match_flag_pb[55]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].right_edge_found_pb_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk8[6].right_edge_found_pb_reg[6]_0 ), .Q(\genblk8[6].right_edge_pb_reg[36]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[6].right_edge_pb[41]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_106_out), .I2(p_154_out), .I3(p_103_out), .I4(\genblk8[6].right_edge_pb_reg[36]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[6].right_edge_pb[41]_i_2 (.I0(p_154_out), .I1(p_103_out), .I2(p_106_out), .O(\genblk8[6].right_edge_pb[41]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[6].right_edge_pb[41]_i_3 (.I0(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .I1(\genblk8[6].left_edge_pb[41]_i_3_n_0 ), .I2(match_flag_pb[55]), .I3(match_flag_pb[54]), .I4(match_flag_pb[52]), .I5(match_flag_pb[53]), .O(p_103_out)); FDSE #( .INIT(1'b1)) \genblk8[6].right_edge_pb_reg[36] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].right_edge_pb_reg[37] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].right_edge_pb_reg[38] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].right_edge_pb_reg[39] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].right_edge_pb_reg[40] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[6].right_edge_pb_reg[41] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[36]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ), .O(\genblk8[6].right_gain_pb[36]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[37]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ), .O(\genblk8[6].right_gain_pb[37]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[38]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ), .O(\genblk8[6].right_gain_pb[38]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[39]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ), .O(\genblk8[6].right_gain_pb[39]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .O(\genblk8[6].right_gain_pb[39]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .O(\genblk8[6].right_gain_pb[39]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .O(\genblk8[6].right_gain_pb[39]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .O(\genblk8[6].right_gain_pb[39]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .O(\genblk8[6].right_gain_pb[39]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .O(\genblk8[6].right_gain_pb[39]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .O(\genblk8[6].right_gain_pb[39]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .O(\genblk8[6].right_gain_pb[39]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[40]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ), .I3(\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ), .O(\genblk8[6].right_gain_pb[40]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[6].right_gain_pb[41]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_106_out), .I4(\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .O(\genblk8[6].right_gain_pb[41]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .O(\genblk8[6].right_gain_pb[41]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .O(\genblk8[6].right_gain_pb[41]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[6].right_gain_pb[41]_i_13 (.I0(\genblk8[6].right_gain_pb[41]_i_16_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I2(right_edge_ref[3]), .I3(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I4(right_edge_ref[4]), .O(\genblk8[6].right_gain_pb[41]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[6].right_gain_pb[41]_i_14 (.I0(\genblk8[6].right_gain_pb[41]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I3(right_edge_ref[4]), .I4(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .O(\genblk8[6].right_gain_pb[41]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[6].right_gain_pb[41]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I3(right_edge_ref[1]), .I4(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I5(right_edge_ref[2]), .O(\genblk8[6].right_gain_pb[41]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[6].right_gain_pb[41]_i_17 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I4(right_edge_ref[2]), .I5(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .O(\genblk8[6].right_gain_pb[41]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[6].right_gain_pb[41]_i_2 (.I0(p_154_out), .I1(p_103_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[6].right_edge_pb_reg[36]_0 ), .I4(p_106_out), .O(\genblk8[6].right_gain_pb[41]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[41]_i_3 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ), .I3(\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ), .O(\genblk8[6].right_gain_pb[41]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[6].right_gain_pb[41]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[6].right_gain_pb[41]_i_34 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[6].right_gain_pb[41]_i_35 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[6].right_gain_pb[41]_i_37 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[6].right_gain_pb[41]_i_38 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[6].right_gain_pb[41]_i_39 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[6].right_gain_pb[41]_i_7 (.I0(\genblk8[6].right_edge_pb_reg[36]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I4(\genblk8[6].right_gain_pb[41]_i_13_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[6].right_gain_pb[41]_i_8 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I1(right_edge_ref[5]), .I2(\genblk8[6].right_gain_pb[41]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ), .I5(\genblk8[6].right_edge_pb_reg[36]_0 ), .O(\genblk8[6].right_gain_pb[41]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .O(\genblk8[6].right_gain_pb[41]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].right_gain_pb_reg[36] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[36]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg_n_0_[36] ), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].right_gain_pb_reg[37] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[37]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg_n_0_[37] ), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].right_gain_pb_reg[38] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[38]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [2]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].right_gain_pb_reg[39] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[39]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [3]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); CARRY4 \genblk8[6].right_gain_pb_reg[39]_i_2 (.CI(1'b0), .CO({\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 }), .S({\genblk8[6].right_gain_pb[39]_i_4_n_0 ,\genblk8[6].right_gain_pb[39]_i_5_n_0 ,\genblk8[6].right_gain_pb[39]_i_6_n_0 ,\genblk8[6].right_gain_pb[39]_i_7_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[39]_i_3 (.CI(1'b0), .CO({\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 }), .S({\genblk8[6].right_gain_pb[39]_i_8_n_0 ,\genblk8[6].right_gain_pb[39]_i_9_n_0 ,\genblk8[6].right_gain_pb[39]_i_10_n_0 ,\genblk8[6].right_gain_pb[39]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[6].right_gain_pb_reg[40] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[40]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [4]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[6].right_gain_pb_reg[41] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[41]_i_3_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [5]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_15 (.CI(\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ), .CO({\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_19_n_0 ,\genblk8[6].right_gain_pb[41]_i_20_n_0 ,\genblk8[6].right_gain_pb[41]_i_21_n_0 ,\genblk8[6].right_gain_pb[41]_i_22_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_18 (.CI(\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ), .CO({\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_24_n_0 ,\genblk8[6].right_gain_pb[41]_i_25_n_0 ,\genblk8[6].right_gain_pb[41]_i_26_n_0 ,\genblk8[6].right_gain_pb[41]_i_27_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_23 (.CI(\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ), .CO({\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_29_n_0 ,\genblk8[6].right_gain_pb[41]_i_30_n_0 ,\genblk8[6].right_gain_pb[41]_i_31_n_0 ,\genblk8[6].right_gain_pb[41]_i_32_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_28 (.CI(1'b0), .CO({\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[6].right_gain_pb[41]_i_33_n_0 ,\genblk8[6].right_gain_pb[41]_i_34_n_0 ,\genblk8[6].right_gain_pb[41]_i_35_n_0 }), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_36_n_0 ,\genblk8[6].right_gain_pb[41]_i_37_n_0 ,\genblk8[6].right_gain_pb[41]_i_38_n_0 ,\genblk8[6].right_gain_pb[41]_i_39_n_0 })); MUXF7 \genblk8[6].right_gain_pb_reg[41]_i_4 (.I0(\genblk8[6].right_gain_pb[41]_i_7_n_0 ), .I1(\genblk8[6].right_gain_pb[41]_i_8_n_0 ), .O(\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ), .S(p_103_out)); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_5 (.CI(\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ), .CO({\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED [3:1],\genblk8[6].right_gain_pb_reg[41]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED [3:2],\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ,\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[6].right_gain_pb[41]_i_9_n_0 ,\genblk8[6].right_gain_pb[41]_i_10_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_6 (.CI(\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ), .CO({\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED [3:1],\genblk8[6].right_gain_pb_reg[41]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED [3:2],\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ,\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[6].right_gain_pb[41]_i_11_n_0 ,\genblk8[6].right_gain_pb[41]_i_12_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_found_pb_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk8[7].left_edge_found_pb_reg[7]_0 ), .Q(\genblk8[7].left_loss_pb_reg[42]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[7].left_edge_pb[47]_i_1 (.I0(p_154_out), .I1(p_98_out), .O(\genblk8[7].left_edge_pb[47]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[7].left_edge_pb[47]_i_2 (.I0(match_flag_pb[63]), .I1(\genblk8[7].left_edge_pb[47]_i_3_n_0 ), .I2(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .I3(match_flag_pb[62]), .I4(match_flag_pb[60]), .I5(match_flag_pb[61]), .O(p_98_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[7].left_edge_pb[47]_i_3 (.I0(match_flag_pb[58]), .I1(match_flag_pb[59]), .I2(match_flag_pb[56]), .I3(match_flag_pb[57]), .O(\genblk8[7].left_edge_pb[47]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_pb_reg[42] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[42] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_pb_reg[43] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[43] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_pb_reg[44] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[44] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_pb_reg[45] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[45] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_pb_reg[46] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[46] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_pb_reg[47] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[47] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_edge_updated_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk8[7].left_edge_updated_reg[7]_1 ), .Q(D[7]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[7].left_loss_pb[47]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[7].left_loss_pb_reg[42]_0 ), .I4(p_98_out), .O(\genblk8[7].left_loss_pb[47]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_loss_pb_reg[42] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg_n_0_[42] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_loss_pb_reg[43] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg_n_0_[43] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_loss_pb_reg[44] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_loss_pb_reg[45] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_loss_pb_reg[46] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].left_loss_pb_reg[47] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[56] (.C(CLK), .CE(p_154_out), .D(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .Q(match_flag_pb[56]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[57] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[56]), .Q(match_flag_pb[57]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[58] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[57]), .Q(match_flag_pb[58]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[59] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[58]), .Q(match_flag_pb[59]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[60] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[59]), .Q(match_flag_pb[60]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[61] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[60]), .Q(match_flag_pb[61]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[62] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[61]), .Q(match_flag_pb[62]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].match_flag_pb_reg[63] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[62]), .Q(match_flag_pb[63]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].right_edge_found_pb_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk8[7].right_edge_found_pb_reg[7]_0 ), .Q(\genblk8[7].right_edge_pb_reg[42]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[7].right_edge_pb[47]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_98_out), .I2(p_154_out), .I3(p_95_out), .I4(\genblk8[7].right_edge_pb_reg[42]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[7].right_edge_pb[47]_i_2 (.I0(p_154_out), .I1(p_95_out), .I2(p_98_out), .O(\genblk8[7].right_edge_pb[47]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[7].right_edge_pb[47]_i_3 (.I0(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .I1(\genblk8[7].left_edge_pb[47]_i_3_n_0 ), .I2(match_flag_pb[63]), .I3(match_flag_pb[62]), .I4(match_flag_pb[60]), .I5(match_flag_pb[61]), .O(p_95_out)); FDSE #( .INIT(1'b1)) \genblk8[7].right_edge_pb_reg[42] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].right_edge_pb_reg[43] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].right_edge_pb_reg[44] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].right_edge_pb_reg[45] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].right_edge_pb_reg[46] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \genblk8[7].right_edge_pb_reg[47] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[42]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ), .O(\genblk8[7].right_gain_pb[42]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[43]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ), .O(\genblk8[7].right_gain_pb[43]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[44]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ), .O(\genblk8[7].right_gain_pb[44]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[45]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ), .O(\genblk8[7].right_gain_pb[45]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .O(\genblk8[7].right_gain_pb[45]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .O(\genblk8[7].right_gain_pb[45]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .O(\genblk8[7].right_gain_pb[45]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .O(\genblk8[7].right_gain_pb[45]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .O(\genblk8[7].right_gain_pb[45]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .O(\genblk8[7].right_gain_pb[45]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .O(\genblk8[7].right_gain_pb[45]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .O(\genblk8[7].right_gain_pb[45]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[46]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ), .I3(\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ), .O(\genblk8[7].right_gain_pb[46]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[7].right_gain_pb[47]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_98_out), .I4(\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .O(\genblk8[7].right_gain_pb[47]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .O(\genblk8[7].right_gain_pb[47]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .O(\genblk8[7].right_gain_pb[47]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[7].right_gain_pb[47]_i_13 (.I0(\genblk8[7].right_gain_pb[47]_i_16_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I2(right_edge_ref[3]), .I3(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I4(right_edge_ref[4]), .O(\genblk8[7].right_gain_pb[47]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[7].right_gain_pb[47]_i_14 (.I0(\genblk8[7].right_gain_pb[47]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I3(right_edge_ref[4]), .I4(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .O(\genblk8[7].right_gain_pb[47]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[7].right_gain_pb[47]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I3(right_edge_ref[1]), .I4(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I5(right_edge_ref[2]), .O(\genblk8[7].right_gain_pb[47]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[7].right_gain_pb[47]_i_17 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I4(right_edge_ref[2]), .I5(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .O(\genblk8[7].right_gain_pb[47]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[7].right_gain_pb[47]_i_2 (.I0(p_154_out), .I1(p_95_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[7].right_edge_pb_reg[42]_0 ), .I4(p_98_out), .O(\genblk8[7].right_gain_pb[47]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[47]_i_3 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ), .I3(\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ), .O(\genblk8[7].right_gain_pb[47]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[7].right_gain_pb[47]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[7].right_gain_pb[47]_i_34 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[7].right_gain_pb[47]_i_35 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[7].right_gain_pb[47]_i_37 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[7].right_gain_pb[47]_i_38 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[7].right_gain_pb[47]_i_39 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[7].right_gain_pb[47]_i_7 (.I0(\genblk8[7].right_edge_pb_reg[42]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I4(\genblk8[7].right_gain_pb[47]_i_13_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[7].right_gain_pb[47]_i_8 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I1(right_edge_ref[5]), .I2(\genblk8[7].right_gain_pb[47]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_0 ), .O(\genblk8[7].right_gain_pb[47]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .O(\genblk8[7].right_gain_pb[47]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].right_gain_pb_reg[42] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[42]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg_n_0_[42] ), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].right_gain_pb_reg[43] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[43]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg_n_0_[43] ), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].right_gain_pb_reg[44] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[44]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [2]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].right_gain_pb_reg[45] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[45]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [3]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); CARRY4 \genblk8[7].right_gain_pb_reg[45]_i_2 (.CI(1'b0), .CO({\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 }), .S({\genblk8[7].right_gain_pb[45]_i_4_n_0 ,\genblk8[7].right_gain_pb[45]_i_5_n_0 ,\genblk8[7].right_gain_pb[45]_i_6_n_0 ,\genblk8[7].right_gain_pb[45]_i_7_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[45]_i_3 (.CI(1'b0), .CO({\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 }), .S({\genblk8[7].right_gain_pb[45]_i_8_n_0 ,\genblk8[7].right_gain_pb[45]_i_9_n_0 ,\genblk8[7].right_gain_pb[45]_i_10_n_0 ,\genblk8[7].right_gain_pb[45]_i_11_n_0 })); FDRE #( .INIT(1'b0)) \genblk8[7].right_gain_pb_reg[46] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[46]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [4]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \genblk8[7].right_gain_pb_reg[47] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[47]_i_3_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [5]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_15 (.CI(\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ), .CO({\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_19_n_0 ,\genblk8[7].right_gain_pb[47]_i_20_n_0 ,\genblk8[7].right_gain_pb[47]_i_21_n_0 ,\genblk8[7].right_gain_pb[47]_i_22_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_18 (.CI(\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ), .CO({\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_24_n_0 ,\genblk8[7].right_gain_pb[47]_i_25_n_0 ,\genblk8[7].right_gain_pb[47]_i_26_n_0 ,\genblk8[7].right_gain_pb[47]_i_27_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_23 (.CI(\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ), .CO({\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_29_n_0 ,\genblk8[7].right_gain_pb[47]_i_30_n_0 ,\genblk8[7].right_gain_pb[47]_i_31_n_0 ,\genblk8[7].right_gain_pb[47]_i_32_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_28 (.CI(1'b0), .CO({\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[7].right_gain_pb[47]_i_33_n_0 ,\genblk8[7].right_gain_pb[47]_i_34_n_0 ,\genblk8[7].right_gain_pb[47]_i_35_n_0 }), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_36_n_0 ,\genblk8[7].right_gain_pb[47]_i_37_n_0 ,\genblk8[7].right_gain_pb[47]_i_38_n_0 ,\genblk8[7].right_gain_pb[47]_i_39_n_0 })); MUXF7 \genblk8[7].right_gain_pb_reg[47]_i_4 (.I0(\genblk8[7].right_gain_pb[47]_i_7_n_0 ), .I1(\genblk8[7].right_gain_pb[47]_i_8_n_0 ), .O(\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ), .S(p_95_out)); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_5 (.CI(\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ), .CO({\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED [3:1],\genblk8[7].right_gain_pb_reg[47]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED [3:2],\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ,\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[7].right_gain_pb[47]_i_9_n_0 ,\genblk8[7].right_gain_pb[47]_i_10_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_6 (.CI(\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ), .CO({\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED [3:1],\genblk8[7].right_gain_pb_reg[47]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED [3:2],\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ,\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[7].right_gain_pb[47]_i_11_n_0 ,\genblk8[7].right_gain_pb[47]_i_12_n_0 })); LUT6 #( .INIT(64'h00000000AAAAAAA2)) \genblk9[0].fine_delay_incdec_pb[0]_i_1 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ), .I1(bit_cnt), .I2(\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ), .I3(\stage_cnt_reg_n_0_[0] ), .I4(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hFFFE)) \genblk9[0].fine_delay_incdec_pb[0]_i_10 (.I0(ref_bit[6]), .I1(ref_bit[7]), .I2(ref_bit[4]), .I3(ref_bit[5]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[0].fine_delay_incdec_pb[0]_i_11 (.I0(\genblk8[0].right_gain_pb_reg_n_0_[0] ), .I1(\genblk8[0].left_loss_pb_reg_n_0_[0] ), .I2(\genblk8[0].left_loss_pb_reg_n_0_[1] ), .I3(\genblk8[0].right_gain_pb_reg_n_0_[1] ), .I4(\genblk8[0].left_loss_pb_reg__0 [2]), .I5(\genblk8[0].right_gain_pb_reg__0 [2]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[0].fine_delay_incdec_pb[0]_i_2 (.I0(\genblk8[0].right_gain_pb_reg__0 [5]), .I1(\genblk8[0].left_loss_pb_reg__0 [5]), .I2(\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\fine_delay_mod_reg[26] ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \genblk9[0].fine_delay_incdec_pb[0]_i_3 (.I0(bit_cnt_reg__0[3]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[4]), .I3(p_1_in159_in), .I4(bit_cnt_reg__0[2]), .I5(\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ), .O(bit_cnt)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT5 #( .INIT(32'hFFFFFFFE)) \genblk9[0].fine_delay_incdec_pb[0]_i_4 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[0].fine_delay_incdec_pb[0]_i_5 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ), .I1(\genblk8[0].left_loss_pb_reg__0 [3]), .I2(\genblk8[0].right_gain_pb_reg__0 [3]), .I3(\genblk8[0].left_loss_pb_reg__0 [4]), .I4(\genblk8[0].right_gain_pb_reg__0 [4]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT3 #( .INIT(8'h02)) \genblk9[0].fine_delay_incdec_pb[0]_i_6 (.I0(bit_cnt), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT5 #( .INIT(32'h04000000)) \genblk9[0].fine_delay_incdec_pb[0]_i_8 (.I0(Q[3]), .I1(Q[4]), .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), .O(p_1_in159_in)); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'hFFFE)) \genblk9[0].fine_delay_incdec_pb[0]_i_9 (.I0(bit_cnt_reg__0[1]), .I1(bit_cnt_reg__0[7]), .I2(bit_cnt_reg__0[5]), .I3(bit_cnt_reg__0[6]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[0].fine_delay_incdec_pb_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ), .Q(\fine_delay_mod_reg[26] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[1].fine_delay_incdec_pb[1]_i_1 (.I0(\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ), .I1(\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[1].fine_delay_incdec_pb[1]_i_2 (.I0(\genblk8[1].right_gain_pb_reg__0 [5]), .I1(\genblk8[1].left_loss_pb_reg__0 [5]), .I2(\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'hFFFFFFEF)) \genblk9[1].fine_delay_incdec_pb[1]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[1].fine_delay_incdec_pb[1]_i_4 (.I0(\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ), .I1(\genblk8[1].left_loss_pb_reg__0 [3]), .I2(\genblk8[1].right_gain_pb_reg__0 [3]), .I3(\genblk8[1].left_loss_pb_reg__0 [4]), .I4(\genblk8[1].right_gain_pb_reg__0 [4]), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[1].fine_delay_incdec_pb[1]_i_5 (.I0(\genblk8[1].right_gain_pb_reg_n_0_[6] ), .I1(\genblk8[1].left_loss_pb_reg_n_0_[6] ), .I2(\genblk8[1].left_loss_pb_reg_n_0_[7] ), .I3(\genblk8[1].right_gain_pb_reg_n_0_[7] ), .I4(\genblk8[1].left_loss_pb_reg__0 [2]), .I5(\genblk8[1].right_gain_pb_reg__0 [2]), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[1].fine_delay_incdec_pb_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ), .Q(\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[2].fine_delay_incdec_pb[2]_i_1 (.I0(\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ), .I1(\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[2].fine_delay_incdec_pb[2]_i_2 (.I0(\genblk8[2].right_gain_pb_reg__0 [5]), .I1(\genblk8[2].left_loss_pb_reg__0 [5]), .I2(\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT5 #( .INIT(32'hFFFFFFEF)) \genblk9[2].fine_delay_incdec_pb[2]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[0] ), .I2(\ref_bit_reg_n_0_[1] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[2].fine_delay_incdec_pb[2]_i_4 (.I0(\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ), .I1(\genblk8[2].left_loss_pb_reg__0 [3]), .I2(\genblk8[2].right_gain_pb_reg__0 [3]), .I3(\genblk8[2].left_loss_pb_reg__0 [4]), .I4(\genblk8[2].right_gain_pb_reg__0 [4]), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[2].fine_delay_incdec_pb[2]_i_5 (.I0(\genblk8[2].right_gain_pb_reg_n_0_[12] ), .I1(\genblk8[2].left_loss_pb_reg_n_0_[12] ), .I2(\genblk8[2].left_loss_pb_reg_n_0_[13] ), .I3(\genblk8[2].right_gain_pb_reg_n_0_[13] ), .I4(\genblk8[2].left_loss_pb_reg__0 [2]), .I5(\genblk8[2].right_gain_pb_reg__0 [2]), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[2].fine_delay_incdec_pb_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ), .Q(\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[3].fine_delay_incdec_pb[3]_i_1 (.I0(\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ), .I1(\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[3].fine_delay_incdec_pb[3]_i_2 (.I0(\genblk8[3].right_gain_pb_reg__0 [5]), .I1(\genblk8[3].left_loss_pb_reg__0 [5]), .I2(\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'hFFFFFFBF)) \genblk9[3].fine_delay_incdec_pb[3]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[3].fine_delay_incdec_pb[3]_i_4 (.I0(\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ), .I1(\genblk8[3].left_loss_pb_reg__0 [3]), .I2(\genblk8[3].right_gain_pb_reg__0 [3]), .I3(\genblk8[3].left_loss_pb_reg__0 [4]), .I4(\genblk8[3].right_gain_pb_reg__0 [4]), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[3].fine_delay_incdec_pb[3]_i_5 (.I0(\genblk8[3].right_gain_pb_reg_n_0_[18] ), .I1(\genblk8[3].left_loss_pb_reg_n_0_[18] ), .I2(\genblk8[3].left_loss_pb_reg_n_0_[19] ), .I3(\genblk8[3].right_gain_pb_reg_n_0_[19] ), .I4(\genblk8[3].left_loss_pb_reg__0 [2]), .I5(\genblk8[3].right_gain_pb_reg__0 [2]), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[3].fine_delay_incdec_pb_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ), .Q(\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[4].fine_delay_incdec_pb[4]_i_1 (.I0(\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ), .I1(\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[4].fine_delay_incdec_pb[4]_i_2 (.I0(\genblk8[4].right_gain_pb_reg__0 [5]), .I1(\genblk8[4].left_loss_pb_reg__0 [5]), .I2(\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\fine_delay_mod_reg[20] ), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT5 #( .INIT(32'hFFFFFFEF)) \genblk9[4].fine_delay_incdec_pb[4]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[2] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[0] ), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[4].fine_delay_incdec_pb[4]_i_4 (.I0(\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ), .I1(\genblk8[4].left_loss_pb_reg__0 [3]), .I2(\genblk8[4].right_gain_pb_reg__0 [3]), .I3(\genblk8[4].left_loss_pb_reg__0 [4]), .I4(\genblk8[4].right_gain_pb_reg__0 [4]), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[4].fine_delay_incdec_pb[4]_i_5 (.I0(\genblk8[4].right_gain_pb_reg_n_0_[24] ), .I1(\genblk8[4].left_loss_pb_reg_n_0_[24] ), .I2(\genblk8[4].left_loss_pb_reg_n_0_[25] ), .I3(\genblk8[4].right_gain_pb_reg_n_0_[25] ), .I4(\genblk8[4].left_loss_pb_reg__0 [2]), .I5(\genblk8[4].right_gain_pb_reg__0 [2]), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[4].fine_delay_incdec_pb_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ), .Q(\fine_delay_mod_reg[20] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[5].fine_delay_incdec_pb[5]_i_1 (.I0(\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ), .I1(\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[5].fine_delay_incdec_pb[5]_i_2 (.I0(\genblk8[5].right_gain_pb_reg__0 [5]), .I1(\genblk8[5].left_loss_pb_reg__0 [5]), .I2(\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT5 #( .INIT(32'hFFFFFFBF)) \genblk9[5].fine_delay_incdec_pb[5]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[2] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[1] ), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[5].fine_delay_incdec_pb[5]_i_4 (.I0(\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ), .I1(\genblk8[5].left_loss_pb_reg__0 [3]), .I2(\genblk8[5].right_gain_pb_reg__0 [3]), .I3(\genblk8[5].left_loss_pb_reg__0 [4]), .I4(\genblk8[5].right_gain_pb_reg__0 [4]), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[5].fine_delay_incdec_pb[5]_i_5 (.I0(\genblk8[5].right_gain_pb_reg_n_0_[30] ), .I1(\genblk8[5].left_loss_pb_reg_n_0_[30] ), .I2(\genblk8[5].left_loss_pb_reg_n_0_[31] ), .I3(\genblk8[5].right_gain_pb_reg_n_0_[31] ), .I4(\genblk8[5].left_loss_pb_reg__0 [2]), .I5(\genblk8[5].right_gain_pb_reg__0 [2]), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[5].fine_delay_incdec_pb_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ), .Q(\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAAAAAA2)) \genblk9[6].fine_delay_incdec_pb[6]_i_1 (.I0(\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ), .I1(bit_cnt), .I2(\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ), .I3(\stage_cnt_reg_n_0_[0] ), .I4(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[6].fine_delay_incdec_pb[6]_i_2 (.I0(\genblk8[6].right_gain_pb_reg__0 [5]), .I1(\genblk8[6].left_loss_pb_reg__0 [5]), .I2(\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT5 #( .INIT(32'hFFFFFFBF)) \genblk9[6].fine_delay_incdec_pb[6]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[2] ), .I2(\ref_bit_reg_n_0_[1] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[0] ), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[6].fine_delay_incdec_pb[6]_i_4 (.I0(\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ), .I1(\genblk8[6].left_loss_pb_reg__0 [3]), .I2(\genblk8[6].right_gain_pb_reg__0 [3]), .I3(\genblk8[6].left_loss_pb_reg__0 [4]), .I4(\genblk8[6].right_gain_pb_reg__0 [4]), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[6].fine_delay_incdec_pb[6]_i_5 (.I0(\genblk8[6].right_gain_pb_reg_n_0_[36] ), .I1(\genblk8[6].left_loss_pb_reg_n_0_[36] ), .I2(\genblk8[6].left_loss_pb_reg_n_0_[37] ), .I3(\genblk8[6].right_gain_pb_reg_n_0_[37] ), .I4(\genblk8[6].left_loss_pb_reg__0 [2]), .I5(\genblk8[6].right_gain_pb_reg__0 [2]), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[6].fine_delay_incdec_pb_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ), .Q(\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[7].fine_delay_incdec_pb[7]_i_1 (.I0(\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ), .I1(\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[7].fine_delay_incdec_pb[7]_i_2 (.I0(\genblk8[7].right_gain_pb_reg__0 [5]), .I1(\genblk8[7].left_loss_pb_reg__0 [5]), .I2(\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT5 #( .INIT(32'hFFBFFFFF)) \genblk9[7].fine_delay_incdec_pb[7]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[7].fine_delay_incdec_pb[7]_i_4 (.I0(\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ), .I1(\genblk8[7].left_loss_pb_reg__0 [3]), .I2(\genblk8[7].right_gain_pb_reg__0 [3]), .I3(\genblk8[7].left_loss_pb_reg__0 [4]), .I4(\genblk8[7].right_gain_pb_reg__0 [4]), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[7].fine_delay_incdec_pb[7]_i_5 (.I0(\genblk8[7].right_gain_pb_reg_n_0_[42] ), .I1(\genblk8[7].left_loss_pb_reg_n_0_[42] ), .I2(\genblk8[7].left_loss_pb_reg_n_0_[43] ), .I3(\genblk8[7].right_gain_pb_reg_n_0_[43] ), .I4(\genblk8[7].left_loss_pb_reg__0 [2]), .I5(\genblk8[7].right_gain_pb_reg__0 [2]), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \genblk9[7].fine_delay_incdec_pb_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ), .Q(\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h7)) \init_state_r[0]_i_32 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(rdlvl_stg1_done_int_reg), .O(\init_state_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT5 #( .INIT(32'h000074FF)) \init_state_r[0]_i_35 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(rdlvl_stg1_done_int_reg), .I2(wrcal_done_reg), .I3(dqs_found_done_r_reg), .I4(\num_refresh_reg[1] ), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h3F332F233F332020)) \init_state_r[1]_i_32 (.I0(prbs_last_byte_done), .I1(complex_oclkdelay_calib_done_r1_reg), .I2(rdlvl_stg1_done_int_reg), .I3(rdlvl_stg1_start_int), .I4(rdlvl_last_byte_done), .I5(\one_rank.stg1_wr_done_reg ), .O(\init_state_r_reg[1]_0 )); LUT6 #( .INIT(64'hF0FF808080808080)) \init_state_r[1]_i_45 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(oclkdelay_center_calib_done_r_reg), .I2(rdlvl_stg1_done_int_reg), .I3(wrcal_done_reg), .I4(dqs_found_done_r_reg), .I5(wrlvl_final_mux), .O(\init_state_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT2 #( .INIT(4'h2)) \largest_left_edge[0]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\largest_left_edge[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT3 #( .INIT(8'h28)) \largest_left_edge[1]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\largest_left_edge[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'h2888)) \largest_left_edge[2]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\largest_left_edge[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h82222222)) \largest_left_edge[3]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\largest_left_edge[3]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888882222222)) \largest_left_edge[4]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\largest_left_edge[4]_i_1_n_0 )); LUT6 #( .INIT(64'h00002F0000000000)) \largest_left_edge[5]_i_1 (.I0(ref_bit_per_bit0), .I1(\largest_left_edge_reg[0]_0 ), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .I5(\largest_left_edge[5]_i_4_n_0 ), .O(\largest_left_edge[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT2 #( .INIT(4'h2)) \largest_left_edge[5]_i_2 (.I0(Q[2]), .I1(\largest_left_edge[5]_i_5_n_0 ), .O(\largest_left_edge[5]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \largest_left_edge[5]_i_3 (.I0(D[0]), .I1(D[1]), .I2(D[2]), .I3(D[3]), .I4(\largest_left_edge[5]_i_6_n_0 ), .O(ref_bit_per_bit0)); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'h81)) \largest_left_edge[5]_i_4 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .O(\largest_left_edge[5]_i_4_n_0 )); LUT6 #( .INIT(64'h00001555FFFFEAAA)) \largest_left_edge[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\largest_left_edge[5]_i_5_n_0 )); LUT4 #( .INIT(16'h0001)) \largest_left_edge[5]_i_6 (.I0(D[6]), .I1(D[7]), .I2(D[5]), .I3(D[4]), .O(\largest_left_edge[5]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \largest_left_edge_reg[0] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[0]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \largest_left_edge_reg[1] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[1]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \largest_left_edge_reg[2] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[2]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \largest_left_edge_reg[3] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[3]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \largest_left_edge_reg[4] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[4]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \largest_left_edge_reg[5] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[5]_i_2_n_0 ), .Q(\largest_left_edge_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); LUT3 #( .INIT(8'hB8)) \left_edge_ref[0]_i_1 (.I0(\left_edge_ref[2]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[0]_i_2_n_0 ), .O(\left_edge_ref[0]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[0]_i_2 (.I0(\left_edge_ref_reg[4]_i_10_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[0]_i_3_n_0 ), .O(\left_edge_ref[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[0]_i_3 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[0] ), .O(\left_edge_ref[0]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \left_edge_ref[1]_i_1 (.I0(\left_edge_ref[3]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[1]_i_2_n_0 ), .O(\left_edge_ref[1]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[1]_i_2 (.I0(\left_edge_ref_reg[5]_i_16_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[5]_i_15_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[1]_i_3_n_0 ), .O(\left_edge_ref[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[1]_i_3 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[1] ), .O(\left_edge_ref[1]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \left_edge_ref[2]_i_1 (.I0(\left_edge_ref[4]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[2]_i_2_n_0 ), .O(\left_edge_ref[2]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[2]_i_2 (.I0(\left_edge_ref_reg[4]_i_3_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[4]_i_5_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[2]_i_3_n_0 ), .O(\left_edge_ref[2]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[2]_i_3 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[2] ), .O(\left_edge_ref[2]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \left_edge_ref[3]_i_1 (.I0(\left_edge_ref[5]_i_5_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[3]_i_2_n_0 ), .O(\left_edge_ref[3]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[3]_i_2 (.I0(\left_edge_ref_reg[5]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[5]_i_7_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[3]_i_3_n_0 ), .O(\left_edge_ref[3]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[3]_i_3 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[3] ), .O(\left_edge_ref[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[4]_i_1 (.I0(\left_edge_ref[4]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref_reg[4]_i_3_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\left_edge_ref[4]_i_4_n_0 ), .O(\left_edge_ref[4]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_11 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[20] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[36] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[4] ), .O(\left_edge_ref[4]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_12 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[28] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[44] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[12] ), .O(\left_edge_ref[4]_i_12_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \left_edge_ref[4]_i_2 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\left_edge_ref[4]_i_5_n_0 ), .O(\left_edge_ref[4]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[4]_i_4 (.I0(\left_edge_ref[4]_i_8_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\left_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\left_edge_ref_reg[4]_i_10_n_0 ), .O(\left_edge_ref[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_5 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[26] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[42] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[10] ), .O(\left_edge_ref[4]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_6 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[22] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[38] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[6] ), .O(\left_edge_ref[4]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_7 (.I0(\genblk8[5].left_edge_pb_reg_n_0_[30] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[46] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[14] ), .O(\left_edge_ref[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'h00E2)) \left_edge_ref[4]_i_8 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\left_edge_ref[4]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_9 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[24] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[40] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[8] ), .O(\left_edge_ref[4]_i_9_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[5]_i_1 (.I0(\left_edge_ref[5]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref_reg[5]_i_4_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\left_edge_ref[5]_i_5_n_0 ), .O(\left_edge_ref[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \left_edge_ref[5]_i_10 (.I0(\ref_bit_reg_n_0_[1] ), .O(\left_edge_ref[5]_i_10_n_0 )); LUT1 #( .INIT(2'h2)) \left_edge_ref[5]_i_11 (.I0(\ref_bit_reg_n_0_[0] ), .O(\left_edge_ref[5]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_12 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[23] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[39] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[7] ), .O(\left_edge_ref[5]_i_12_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_13 (.I0(\genblk8[5].left_edge_pb_reg_n_0_[31] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[47] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[15] ), .O(\left_edge_ref[5]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT4 #( .INIT(16'h00E2)) \left_edge_ref[5]_i_14 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\left_edge_ref[5]_i_14_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_15 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[25] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[41] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[9] ), .O(\left_edge_ref[5]_i_15_n_0 )); LUT2 #( .INIT(4'h9)) \left_edge_ref[5]_i_17 (.I0(\ref_bit_reg_n_0_[2] ), .I1(ref_bit[4]), .O(\left_edge_ref[5]_i_17_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_18 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[21] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[37] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[5] ), .O(\left_edge_ref[5]_i_18_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_19 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[29] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[45] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[13] ), .O(\left_edge_ref[5]_i_19_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \left_edge_ref[5]_i_2 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\left_edge_ref[5]_i_7_n_0 ), .O(\left_edge_ref[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[5]_i_5 (.I0(\left_edge_ref[5]_i_14_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\left_edge_ref[5]_i_15_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\left_edge_ref_reg[5]_i_16_n_0 ), .O(\left_edge_ref[5]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_7 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[27] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[43] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[11] ), .O(\left_edge_ref[5]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \left_edge_ref[5]_i_8 (.I0(\ref_bit_reg_n_0_[1] ), .I1(ref_bit[3]), .O(\left_edge_ref[5]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \left_edge_ref[5]_i_9 (.I0(\ref_bit_reg_n_0_[0] ), .I1(\ref_bit_reg_n_0_[2] ), .O(\left_edge_ref[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \left_edge_ref_reg[0] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[0]_i_1_n_0 ), .Q(left_edge_ref[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \left_edge_ref_reg[1] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[1]_i_1_n_0 ), .Q(left_edge_ref[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \left_edge_ref_reg[2] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[2]_i_1_n_0 ), .Q(left_edge_ref[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \left_edge_ref_reg[3] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[3]_i_1_n_0 ), .Q(left_edge_ref[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \left_edge_ref_reg[4] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[4]_i_1_n_0 ), .Q(left_edge_ref[4]), .R(1'b0)); MUXF7 \left_edge_ref_reg[4]_i_10 (.I0(\left_edge_ref[4]_i_11_n_0 ), .I1(\left_edge_ref[4]_i_12_n_0 ), .O(\left_edge_ref_reg[4]_i_10_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); MUXF7 \left_edge_ref_reg[4]_i_3 (.I0(\left_edge_ref[4]_i_6_n_0 ), .I1(\left_edge_ref[4]_i_7_n_0 ), .O(\left_edge_ref_reg[4]_i_3_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); FDRE #( .INIT(1'b0)) \left_edge_ref_reg[5] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[5]_i_1_n_0 ), .Q(left_edge_ref[5]), .R(1'b0)); MUXF7 \left_edge_ref_reg[5]_i_16 (.I0(\left_edge_ref[5]_i_18_n_0 ), .I1(\left_edge_ref[5]_i_19_n_0 ), .O(\left_edge_ref_reg[5]_i_16_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); CARRY4 \left_edge_ref_reg[5]_i_3 (.CI(1'b0), .CO({\left_edge_ref_reg[5]_i_3_n_0 ,\left_edge_ref_reg[5]_i_3_n_1 ,\left_edge_ref_reg[5]_i_3_n_2 ,\left_edge_ref_reg[5]_i_3_n_3 }), .CYINIT(1'b0), .DI({\ref_bit_reg_n_0_[1] ,\ref_bit_reg_n_0_[0] ,1'b0,1'b1}), .O({\left_edge_ref_reg[5]_i_3_n_4 ,\left_edge_ref_reg[5]_i_3_n_5 ,\left_edge_ref_reg[5]_i_3_n_6 ,\left_edge_ref_reg[5]_i_3_n_7 }), .S({\left_edge_ref[5]_i_8_n_0 ,\left_edge_ref[5]_i_9_n_0 ,\left_edge_ref[5]_i_10_n_0 ,\left_edge_ref[5]_i_11_n_0 })); MUXF7 \left_edge_ref_reg[5]_i_4 (.I0(\left_edge_ref[5]_i_12_n_0 ), .I1(\left_edge_ref[5]_i_13_n_0 ), .O(\left_edge_ref_reg[5]_i_4_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); CARRY4 \left_edge_ref_reg[5]_i_6 (.CI(\left_edge_ref_reg[5]_i_3_n_0 ), .CO(\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED [3:1],\left_edge_ref_reg[5]_i_6_n_7 }), .S({1'b0,1'b0,1'b0,\left_edge_ref[5]_i_17_n_0 })); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[0]_i_1 (.I0(compare_err_pb_and_reg_n_0), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[0]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[1]_i_1 (.I0(\match_flag_and_reg_n_0_[0] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[1]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[2]_i_1 (.I0(\match_flag_and_reg_n_0_[1] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[2]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[3]_i_1 (.I0(\match_flag_and_reg_n_0_[2] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[3]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[4]_i_1 (.I0(\match_flag_and_reg_n_0_[3] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[4]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[5]_i_1 (.I0(\match_flag_and_reg_n_0_[4] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[5]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[6]_i_1 (.I0(\match_flag_and_reg_n_0_[5] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[6]_i_1_n_0 )); LUT6 #( .INIT(64'h00A2FFFF00A20000)) \match_flag_and[7]_i_1 (.I0(\match_flag_and[7]_i_3_n_0 ), .I1(Q[4]), .I2(num_samples_done_r), .I3(Q[2]), .I4(Q[0]), .I5(no_err_win_detected_reg_0), .O(match_flag_and)); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[7]_i_2 (.I0(\match_flag_and_reg_n_0_[6] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( .INIT(4'h1)) \match_flag_and[7]_i_3 (.I0(Q[1]), .I1(Q[3]), .O(\match_flag_and[7]_i_3_n_0 )); LUT6 #( .INIT(64'h0000444000000000)) \match_flag_and[7]_i_4 (.I0(Q[3]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[2]), .I5(Q[4]), .O(no_err_win_detected_reg_0)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[0] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[0]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[0] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[1] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[1]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[1] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[2] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[2]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[2] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[3] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[3]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[3] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[4] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[4]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[4] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[5] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[5]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[5] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[6] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[6]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[6] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE #( .INIT(1'b1)) \match_flag_and_reg[7] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[7]_i_2_n_0 ), .Q(\match_flag_and_reg_n_0_[7] ), .S(rstdiv0_sync_r1_reg_rep__8)); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[0]_i_1 (.I0(sel0[0]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[0]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[1]_i_1 (.I0(sel0[1]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[1]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[2]_i_1 (.I0(sel0[2]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[2]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[3]_i_1 (.I0(sel0[3]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[3]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[4]_i_1 (.I0(sel0[4]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[4]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[5]_i_1 (.I0(sel0[5]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[5]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[6]_i_1 (.I0(sel0[6]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[6]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \match_flag_or_reg[0] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[0]_i_1_n_0 ), .Q(sel0[1]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE #( .INIT(1'b1)) \match_flag_or_reg[1] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[1]_i_1_n_0 ), .Q(sel0[2]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE #( .INIT(1'b1)) \match_flag_or_reg[2] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[2]_i_1_n_0 ), .Q(sel0[3]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE #( .INIT(1'b1)) \match_flag_or_reg[3] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[3]_i_1_n_0 ), .Q(sel0[4]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE #( .INIT(1'b1)) \match_flag_or_reg[4] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[4]_i_1_n_0 ), .Q(sel0[5]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE #( .INIT(1'b1)) \match_flag_or_reg[5] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[5]_i_1_n_0 ), .Q(sel0[6]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE #( .INIT(1'b1)) \match_flag_or_reg[6] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[6]_i_1_n_0 ), .Q(sel0[7]), .S(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) mux_rd_valid_r_reg (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .Q(mux_rd_valid_r), .R(1'b0)); LUT5 #( .INIT(32'h88888B88)) new_cnt_dqs_r_i_2 (.I0(prech_done), .I1(Q[3]), .I2(prbs_rdlvl_start_r), .I3(prbs_rdlvl_start_reg), .I4(Q[0]), .O(new_cnt_dqs_r)); LUT6 #( .INIT(64'h0030BBBB00308888)) new_cnt_dqs_r_i_3 (.I0(cnt_wait_state), .I1(Q[0]), .I2(prech_done), .I3(prbs_last_byte_done_reg_0), .I4(Q[3]), .I5(prbs_rdlvl_start_reg_0), .O(new_cnt_dqs_r_reg_0)); FDRE #( .INIT(1'b0)) new_cnt_dqs_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_0 ), .Q(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT4 #( .INIT(16'h0100)) no_err_win_detected_i_1 (.I0(Q[1]), .I1(no_err_win_detected_i_2_n_0), .I2(no_err_win_detected_i_3_n_0), .I3(Q[4]), .O(no_err_win_detected_i_1_n_0)); LUT4 #( .INIT(16'hFFFE)) no_err_win_detected_i_2 (.I0(sel0[7]), .I1(sel0[6]), .I2(sel0[4]), .I3(sel0[5]), .O(no_err_win_detected_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) no_err_win_detected_i_3 (.I0(sel0[2]), .I1(sel0[3]), .I2(sel0[0]), .I3(sel0[1]), .O(no_err_win_detected_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT5 #( .INIT(32'h20000003)) no_err_win_detected_latch_i_2 (.I0(no_err_win_detected_latch_reg_0), .I1(Q[4]), .I2(Q[2]), .I3(Q[3]), .I4(Q[1]), .O(no_err_win_detected_latch_reg_1)); FDRE #( .INIT(1'b0)) no_err_win_detected_latch_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[3]_1 ), .Q(\largest_left_edge_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) no_err_win_detected_reg (.C(CLK), .CE(match_flag_and), .D(no_err_win_detected_i_1_n_0), .Q(no_err_win_detected_latch_reg_0), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT2 #( .INIT(4'hE)) num_samples_done_ind_i_2 (.I0(Q[2]), .I1(Q[3]), .O(num_samples_done_ind_reg_0)); FDRE #( .INIT(1'b0)) num_samples_done_ind_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_1 ), .Q(\match_flag_or_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT4 #( .INIT(16'hFFFE)) \oclkdelay_ref_cnt[0]_i_3 (.I0(\stg1_wr_rd_cnt_reg[3] ), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(oclkdelay_center_calib_done_r_reg), .I3(ocal_last_byte_done), .O(\oclkdelay_ref_cnt_reg[0] )); FDRE #( .INIT(1'b0)) pi_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing), .Q(prbs_pi_stg2_f_en), .R(1'b0)); FDRE #( .INIT(1'b0)) pi_en_stg2_f_timing_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing_reg_0), .Q(pi_en_stg2_f_timing), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) pi_stg2_f_incdec_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_f_incdec_timing), .Q(prbs_pi_stg2_f_incdec), .R(1'b0)); FDRE #( .INIT(1'b0)) pi_stg2_f_incdec_timing_reg (.C(CLK), .CE(1'b1), .D(prbs_tap_inc_r_reg_0), .Q(pi_stg2_f_incdec_timing), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT3 #( .INIT(8'h47)) \prbs_dec_tap_cnt[0]_i_1 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(Q[2]), .I2(prbs_dec_tap_cnt[0]), .O(\prbs_dec_tap_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h1AFF1A001A001AFF)) \prbs_dec_tap_cnt[1]_i_1 (.I0(dec_cnt_reg[1]), .I1(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I2(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I3(Q[2]), .I4(prbs_dec_tap_cnt[0]), .I5(prbs_dec_tap_cnt[1]), .O(\prbs_dec_tap_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h060006FF06FF0600)) \prbs_dec_tap_cnt[2]_i_1 (.I0(dec_cnt_reg[2]), .I1(\prbs_dec_tap_cnt[2]_i_2_n_0 ), .I2(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I3(Q[2]), .I4(\prbs_dec_tap_cnt[2]_i_4_n_0 ), .I5(prbs_dec_tap_cnt[2]), .O(\prbs_dec_tap_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h8)) \prbs_dec_tap_cnt[2]_i_2 (.I0(dec_cnt_reg[1]), .I1(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\prbs_dec_tap_cnt[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h8)) \prbs_dec_tap_cnt[2]_i_3 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(\prbs_dec_tap_cnt_reg[1]_0 [1]), .O(\prbs_dec_tap_cnt[2]_i_3_n_0 )); LUT2 #( .INIT(4'h1)) \prbs_dec_tap_cnt[2]_i_4 (.I0(prbs_dec_tap_cnt[0]), .I1(prbs_dec_tap_cnt[1]), .O(\prbs_dec_tap_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'hBBBBBBB88888888B)) \prbs_dec_tap_cnt[3]_i_1 (.I0(\prbs_dec_tap_cnt[3]_i_2_n_0 ), .I1(Q[2]), .I2(prbs_dec_tap_cnt[0]), .I3(prbs_dec_tap_cnt[1]), .I4(prbs_dec_tap_cnt[2]), .I5(prbs_dec_tap_cnt[3]), .O(\prbs_dec_tap_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT5 #( .INIT(32'h006AAAAA)) \prbs_dec_tap_cnt[3]_i_2 (.I0(dec_cnt_reg[3]), .I1(dec_cnt_reg[2]), .I2(dec_cnt_reg[1]), .I3(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I4(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\prbs_dec_tap_cnt[3]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFE0001)) \prbs_dec_tap_cnt[4]_i_2 (.I0(prbs_dec_tap_cnt[3]), .I1(prbs_dec_tap_cnt[2]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[0]), .I4(prbs_dec_tap_cnt[4]), .O(\prbs_dec_tap_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'h00006AAAAAAAAAAA)) \prbs_dec_tap_cnt[4]_i_3 (.I0(dec_cnt_reg[4]), .I1(dec_cnt_reg[3]), .I2(dec_cnt_reg[1]), .I3(dec_cnt_reg[2]), .I4(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I5(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\prbs_dec_tap_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'h1010100000000000)) \prbs_dec_tap_cnt[5]_i_1 (.I0(Q[4]), .I1(Q[3]), .I2(Q[1]), .I3(p_3_in), .I4(Q[2]), .I5(Q[0]), .O(\prbs_dec_tap_cnt[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \prbs_dec_tap_cnt[5]_i_3 (.I0(prbs_dec_tap_cnt[2]), .I1(prbs_dec_tap_cnt[0]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[4]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[5]), .O(p_3_in)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \prbs_dec_tap_cnt[5]_i_4 (.I0(prbs_dec_tap_cnt[4]), .I1(prbs_dec_tap_cnt[0]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[2]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[5]), .O(\prbs_dec_tap_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hEAAAAAAAAAAAAAAA)) \prbs_dec_tap_cnt[5]_i_5 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I1(dec_cnt_reg[4]), .I2(dec_cnt_reg[2]), .I3(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I4(dec_cnt_reg[1]), .I5(dec_cnt_reg[3]), .O(\prbs_dec_tap_cnt[5]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \prbs_dec_tap_cnt_reg[0] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[0]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \prbs_dec_tap_cnt_reg[1] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[1]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \prbs_dec_tap_cnt_reg[2] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[2]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \prbs_dec_tap_cnt_reg[3] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[3]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \prbs_dec_tap_cnt_reg[4] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__9)); MUXF7 \prbs_dec_tap_cnt_reg[4]_i_1 (.I0(\prbs_dec_tap_cnt[4]_i_2_n_0 ), .I1(\prbs_dec_tap_cnt[4]_i_3_n_0 ), .O(\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ), .S(Q[2])); FDRE #( .INIT(1'b0)) \prbs_dec_tap_cnt_reg[5] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ), .Q(prbs_dec_tap_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__9)); MUXF7 \prbs_dec_tap_cnt_reg[5]_i_2 (.I0(\prbs_dec_tap_cnt[5]_i_4_n_0 ), .I1(\prbs_dec_tap_cnt[5]_i_5_n_0 ), .O(\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ), .S(Q[2])); LUT6 #( .INIT(64'h0000000000000800)) \prbs_dqs_cnt_r[1]_i_2 (.I0(prbs_rdlvl_done_reg_1), .I1(Q[3]), .I2(prbs_last_byte_done_reg_0), .I3(prech_done), .I4(Q[1]), .I5(Q[2]), .O(\prbs_dqs_cnt_r_reg[1]_0 )); FDRE #( .INIT(1'b0)) \prbs_dqs_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\prbs_dqs_cnt_r_reg[0]_1 ), .Q(\A[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \prbs_dqs_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\prbs_dqs_cnt_r_reg[0]_0 ), .Q(\A[1]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \prbs_dqs_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\prbs_dqs_cnt_r_reg[0]_2 ), .Q(\prbs_dqs_cnt_r_reg[2]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT4 #( .INIT(16'h404F)) \prbs_dqs_tap_cnt_r[0]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .O(\prbs_dqs_tap_cnt_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h404F)) \prbs_dqs_tap_cnt_r[0]_rep__0_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .O(\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 )); LUT4 #( .INIT(16'h404F)) \prbs_dqs_tap_cnt_r[0]_rep_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .O(\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 )); LUT6 #( .INIT(64'h0F0066660F009999)) \prbs_dqs_tap_cnt_r[1]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\calib_sel_reg[3] ), .I3(\pi_counter_read_val_reg[5] [1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I5(prbs_tap_inc_r), .O(\prbs_dqs_tap_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0F0066660F009999)) \prbs_dqs_tap_cnt_r[1]_rep__0_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\calib_sel_reg[3] ), .I3(\pi_counter_read_val_reg[5] [1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I5(prbs_tap_inc_r), .O(\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 )); LUT6 #( .INIT(64'h0F0066660F009999)) \prbs_dqs_tap_cnt_r[1]_rep_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\calib_sel_reg[3] ), .I3(\pi_counter_read_val_reg[5] [1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I5(prbs_tap_inc_r), .O(\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 )); LUT6 #( .INIT(64'h8BB8BB88BB88B88B)) \prbs_dqs_tap_cnt_r[2]_i_1 (.I0(\calib_sel_reg[3]_1 ), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(prbs_tap_inc_r), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_dqs_tap_cnt_r[2]_i_1_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[3]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h7F80)) \prbs_dqs_tap_cnt_r[3]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'h01FE)) \prbs_dqs_tap_cnt_r[3]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[3]_rep__0_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[3]_rep_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 )); LUT6 #( .INIT(64'h8BB888888BB8BBBB)) \prbs_dqs_tap_cnt_r[4]_i_1 (.I0(\calib_sel_reg[3]_2 ), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I4(prbs_tap_inc_r), .I5(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \prbs_dqs_tap_cnt_r[4]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\prbs_dqs_tap_cnt_r[4]_i_2_n_0 )); LUT5 #( .INIT(32'h0001FFFE)) \prbs_dqs_tap_cnt_r[4]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 )); LUT4 #( .INIT(16'hFEAA)) \prbs_dqs_tap_cnt_r[5]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I1(prbs_tap_inc_r), .I2(\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ), .I3(pi_en_stg2_f_timing_reg_0), .O(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[5]_i_2 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\prbs_dqs_tap_cnt_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \prbs_dqs_tap_cnt_r[5]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\prbs_dqs_tap_cnt_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \prbs_dqs_tap_cnt_r[5]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'h00000001FFFFFFFE)) \prbs_dqs_tap_cnt_r[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 )); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[0]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[0] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[0]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[0]_rep (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[0]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[0]_rep__0 (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[1]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[1] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[1]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[1]_rep (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[1]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[1]_rep__0 (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[2] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[3]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[3] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[3]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[3]_rep (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[3]" *) FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[3]_rep__0 (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[4] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \prbs_dqs_tap_cnt_r_reg[5] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) prbs_dqs_tap_limit_r_reg (.C(CLK), .CE(1'b1), .D(new_cnt_dqs_r_reg_1), .Q(prbs_dqs_tap_limit_r), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) prbs_found_1st_edge_r_i_2 (.I0(compare_err_latch_reg_n_0), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I5(prbs_found_1st_edge_r_i_5_n_0), .O(prbs_state_r178_out)); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h1)) prbs_found_1st_edge_r_i_3 (.I0(Q[2]), .I1(Q[4]), .O(complex_pi_incdec_done_reg_1)); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h00FF2000)) prbs_found_1st_edge_r_i_4 (.I0(prbs_state_r178_out), .I1(prbs_dqs_tap_limit_r), .I2(num_samples_done_r), .I3(Q[1]), .I4(Q[3]), .O(prbs_found_1st_edge_r_reg_1)); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'hE)) prbs_found_1st_edge_r_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(prbs_found_1st_edge_r_i_5_n_0)); FDRE #( .INIT(1'b0)) prbs_found_1st_edge_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[3]_0 ), .Q(prbs_found_1st_edge_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__8)); LUT4 #( .INIT(16'h06F6)) \prbs_inc_tap_cnt[0]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I1(rdlvl_cpt_tap_cnt[0]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[0] ), .O(\prbs_inc_tap_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAA3055CFAACF5530)) \prbs_inc_tap_cnt[1]_i_1 (.I0(\prbs_inc_tap_cnt_reg_n_0_[0] ), .I1(rdlvl_cpt_tap_cnt[0]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(Q[2]), .I4(\prbs_inc_tap_cnt[1]_i_2_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'hB8)) \prbs_inc_tap_cnt[1]_i_2 (.I0(\prbs_inc_tap_cnt_reg_n_0_[1] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[1]), .O(\prbs_inc_tap_cnt[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT5 #( .INIT(32'h99699966)) \prbs_inc_tap_cnt[2]_i_1 (.I0(\prbs_inc_tap_cnt[2]_i_2_n_0 ), .I1(\prbs_inc_tap_cnt[2]_i_3_n_0 ), .I2(rdlvl_cpt_tap_cnt[1]), .I3(Q[2]), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFCFAAFFFFFFAACF)) \prbs_inc_tap_cnt[2]_i_2 (.I0(\prbs_inc_tap_cnt_reg_n_0_[0] ), .I1(rdlvl_cpt_tap_cnt[0]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(Q[2]), .I4(\prbs_inc_tap_cnt[1]_i_2_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[2]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(rdlvl_cpt_tap_cnt[2]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[2] ), .O(\prbs_inc_tap_cnt[2]_i_3_n_0 )); LUT6 #( .INIT(64'h6666669699996696)) \prbs_inc_tap_cnt[3]_i_1 (.I0(\prbs_inc_tap_cnt[3]_i_2_n_0 ), .I1(\prbs_inc_tap_cnt[3]_i_3_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(rdlvl_cpt_tap_cnt[2]), .I4(Q[2]), .I5(\prbs_inc_tap_cnt_reg_n_0_[2] ), .O(\prbs_inc_tap_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF477447740000)) \prbs_inc_tap_cnt[3]_i_2 (.I0(\prbs_inc_tap_cnt_reg_n_0_[2] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[2]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_inc_tap_cnt[3]_i_4_n_0 ), .I5(\prbs_inc_tap_cnt[2]_i_2_n_0 ), .O(\prbs_inc_tap_cnt[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[3]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(rdlvl_cpt_tap_cnt[3]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[3] ), .O(\prbs_inc_tap_cnt[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT3 #( .INIT(8'h23)) \prbs_inc_tap_cnt[3]_i_4 (.I0(rdlvl_cpt_tap_cnt[1]), .I1(Q[2]), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'h6666669699996696)) \prbs_inc_tap_cnt[4]_i_1 (.I0(\prbs_inc_tap_cnt[5]_i_5_n_0 ), .I1(\prbs_inc_tap_cnt[4]_i_2_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I3(rdlvl_cpt_tap_cnt[3]), .I4(Q[2]), .I5(\prbs_inc_tap_cnt_reg_n_0_[3] ), .O(\prbs_inc_tap_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[4]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(rdlvl_cpt_tap_cnt[4]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[4] ), .O(\prbs_inc_tap_cnt[4]_i_2_n_0 )); LUT5 #( .INIT(32'h00004540)) \prbs_inc_tap_cnt[5]_i_1 (.I0(Q[3]), .I1(\prbs_inc_tap_cnt[5]_i_3_n_0 ), .I2(Q[2]), .I3(\prbs_inc_tap_cnt[5]_i_4_n_0 ), .I4(Q[4]), .O(\prbs_inc_tap_cnt[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7878781EE1E1E178)) \prbs_inc_tap_cnt[5]_i_2 (.I0(\prbs_inc_tap_cnt[5]_i_5_n_0 ), .I1(\prbs_inc_tap_cnt[5]_i_6_n_0 ), .I2(\prbs_inc_tap_cnt[5]_i_7_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I4(Q[2]), .I5(\prbs_inc_tap_cnt[5]_i_8_n_0 ), .O(\prbs_inc_tap_cnt[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'h08)) \prbs_inc_tap_cnt[5]_i_3 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[0]), .I2(Q[1]), .O(\prbs_inc_tap_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000200000)) \prbs_inc_tap_cnt[5]_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(prbs_state_r178_out), .I3(prbs_found_1st_edge_r_reg_0), .I4(num_samples_done_r), .I5(prbs_dqs_tap_limit_r), .O(\prbs_inc_tap_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFF477447740000)) \prbs_inc_tap_cnt[5]_i_5 (.I0(\prbs_inc_tap_cnt_reg_n_0_[3] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[3]), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I4(\prbs_inc_tap_cnt[5]_i_9_n_0 ), .I5(\prbs_inc_tap_cnt[3]_i_2_n_0 ), .O(\prbs_inc_tap_cnt[5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT4 #( .INIT(16'hFD0D)) \prbs_inc_tap_cnt[5]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I1(rdlvl_cpt_tap_cnt[3]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[3] ), .O(\prbs_inc_tap_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[5]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(rdlvl_cpt_tap_cnt[5]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[5] ), .O(\prbs_inc_tap_cnt[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) \prbs_inc_tap_cnt[5]_i_8 (.I0(\prbs_inc_tap_cnt_reg_n_0_[4] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[4]), .O(\prbs_inc_tap_cnt[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT4 #( .INIT(16'hFD0D)) \prbs_inc_tap_cnt[5]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(rdlvl_cpt_tap_cnt[2]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[2] ), .O(\prbs_inc_tap_cnt[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \prbs_inc_tap_cnt_reg[0] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[0]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \prbs_inc_tap_cnt_reg[1] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[1]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \prbs_inc_tap_cnt_reg[2] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[2]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \prbs_inc_tap_cnt_reg[3] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[3]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \prbs_inc_tap_cnt_reg[4] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[4]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \prbs_inc_tap_cnt_reg[5] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[5]_i_2_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT3 #( .INIT(8'hEA)) prbs_last_byte_done_i_2 (.I0(\prbs_dqs_cnt_r_reg[2]_0 ), .I1(\A[0]_0 ), .I2(\A[1]_0 ), .O(prbs_last_byte_done_reg_0)); FDRE #( .INIT(1'b0)) prbs_last_byte_done_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_3 ), .Q(prbs_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) prbs_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(prech_done_reg), .Q(prbs_prech_req_r), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT2 #( .INIT(4'h1)) prbs_rdlvl_done_i_2 (.I0(Q[4]), .I1(Q[0]), .O(prbs_rdlvl_done_reg_1)); LUT2 #( .INIT(4'h2)) prbs_rdlvl_done_pulse_i_1 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(prbs_rdlvl_done_r1), .O(prbs_rdlvl_done_pulse0)); (* MAX_FANOUT = "100" *) (* ORIG_CELL_NAME = "prbs_rdlvl_done_reg" *) FDRE #( .INIT(1'b0)) prbs_rdlvl_done_reg (.C(CLK), .CE(1'b1), .D(fine_dly_error_reg_1), .Q(\stg1_wr_rd_cnt_reg[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* IS_FANOUT_CONSTRAINED = "1" *) (* MAX_FANOUT = "100" *) (* ORIG_CELL_NAME = "prbs_rdlvl_done_reg" *) FDRE #( .INIT(1'b0)) prbs_rdlvl_done_reg_rep (.C(CLK), .CE(1'b1), .D(fine_dly_error_reg_1), .Q(complex_oclkdelay_calib_done_r1_reg), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) prbs_rdlvl_prech_req_reg (.C(CLK), .CE(1'b1), .D(prbs_prech_req_r), .Q(prech_req_r_reg), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) prbs_rdlvl_start_r_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_start_reg), .Q(prbs_rdlvl_start_r), .R(1'b0)); LUT6 #( .INIT(64'hFFF0DFDFFFF0D0D0)) \prbs_state_r[0]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(\prbs_state_r[0]_i_2_n_0 ), .I4(\prbs_state_r[0]_i_3_n_0 ), .I5(\prbs_state_r[0]_i_4_n_0 ), .O(\prbs_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h1C1C1C1C1C1D1D1D)) \prbs_state_r[0]_i_2 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(\A[1]_0 ), .I4(\A[0]_0 ), .I5(\prbs_dqs_cnt_r_reg[2]_0 ), .O(\prbs_state_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'hB8)) \prbs_state_r[0]_i_3 (.I0(Q[2]), .I1(Q[4]), .I2(Q[3]), .O(\prbs_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hCCB8FFFFCCB80000)) \prbs_state_r[0]_i_4 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[1]), .I2(p_3_in), .I3(Q[0]), .I4(Q[2]), .I5(\prbs_state_r[0]_i_5_n_0 ), .O(\prbs_state_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'h5445FFFF)) \prbs_state_r[0]_i_5 (.I0(Q[0]), .I1(prbs_dqs_tap_limit_r), .I2(prbs_state_r178_out), .I3(prbs_found_1st_edge_r_reg_0), .I4(Q[1]), .O(\prbs_state_r[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT5 #( .INIT(32'hB8BBB888)) \prbs_state_r[1]_i_1 (.I0(\prbs_state_r[1]_i_2_n_0 ), .I1(Q[4]), .I2(\prbs_state_r[1]_i_3_n_0 ), .I3(Q[3]), .I4(\prbs_state_r[1]_i_4_n_0 ), .O(\prbs_state_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0047FFB80000FFB8)) \prbs_state_r[1]_i_2 (.I0(Q[2]), .I1(Q[4]), .I2(Q[3]), .I3(Q[1]), .I4(Q[0]), .I5(prbs_state_r1), .O(\prbs_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0F000F001F0F1F00)) \prbs_state_r[1]_i_3 (.I0(prbs_tap_en_r_reg_0), .I1(fine_inc_stage_reg_n_0), .I2(Q[1]), .I3(Q[2]), .I4(prbs_last_byte_done_reg_0), .I5(Q[0]), .O(\prbs_state_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT5 #( .INIT(32'h0C0C4C7C)) \prbs_state_r[1]_i_4 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[2]), .I2(Q[1]), .I3(\prbs_state_r[1]_i_6_n_0 ), .I4(Q[0]), .O(\prbs_state_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \prbs_state_r[1]_i_5 (.I0(\prbs_inc_tap_cnt_reg_n_0_[2] ), .I1(\prbs_inc_tap_cnt_reg_n_0_[0] ), .I2(\prbs_inc_tap_cnt_reg_n_0_[1] ), .I3(\prbs_inc_tap_cnt_reg_n_0_[4] ), .I4(\prbs_inc_tap_cnt_reg_n_0_[3] ), .I5(\prbs_inc_tap_cnt_reg_n_0_[5] ), .O(\prbs_state_r[1]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h15)) \prbs_state_r[1]_i_6 (.I0(prbs_dqs_tap_limit_r), .I1(prbs_state_r178_out), .I2(prbs_found_1st_edge_r_reg_0), .O(\prbs_state_r[1]_i_6_n_0 )); LUT4 #( .INIT(16'h7FFF)) \prbs_state_r[2]_i_10 (.I0(\genblk8[1].right_edge_pb_reg[6]_0 ), .I1(\genblk8[0].right_edge_pb_reg[0]_0 ), .I2(\genblk8[3].right_edge_pb_reg[18]_0 ), .I3(\genblk8[2].right_edge_pb_reg[12]_0 ), .O(\prbs_state_r[2]_i_10_n_0 )); LUT4 #( .INIT(16'hFFFE)) \prbs_state_r[2]_i_11 (.I0(\match_flag_and_reg_n_0_[2] ), .I1(\match_flag_and_reg_n_0_[3] ), .I2(\match_flag_and_reg_n_0_[0] ), .I3(\match_flag_and_reg_n_0_[1] ), .O(\prbs_state_r[2]_i_11_n_0 )); LUT6 #( .INIT(64'h4F00FFFF4F000000)) \prbs_state_r[2]_i_2 (.I0(Q[0]), .I1(prbs_tap_en_r_reg_0), .I2(Q[1]), .I3(Q[2]), .I4(\prbs_state_r[0]_i_3_n_0 ), .I5(\prbs_state_r[2]_i_4_n_0 ), .O(\prbs_state_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFE2E2E2FFE2E2)) \prbs_state_r[2]_i_3 (.I0(Q[3]), .I1(Q[4]), .I2(Q[2]), .I3(prbs_state_r1), .I4(Q[0]), .I5(Q[1]), .O(\prbs_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFCFCFFFFBB880000)) \prbs_state_r[2]_i_4 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[2]), .I2(\prbs_state_r[2]_i_6_n_0 ), .I3(\prbs_state_r[1]_i_6_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(\prbs_state_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'hEAEAEAEAEAEAEAAA)) \prbs_state_r[2]_i_5 (.I0(\prbs_state_r[2]_i_7_n_0 ), .I1(\prbs_state_r[2]_i_8_n_0 ), .I2(\prbs_state_r[2]_i_9_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(prbs_state_r1)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \prbs_state_r[2]_i_6 (.I0(prbs_dec_tap_cnt[0]), .I1(prbs_dec_tap_cnt[4]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[5]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[2]), .O(\prbs_state_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'hBAAAAAAAAAAAAAAA)) \prbs_state_r[2]_i_7 (.I0(prbs_dqs_tap_limit_r), .I1(\prbs_state_r[2]_i_10_n_0 ), .I2(\genblk8[5].right_edge_pb_reg[30]_0 ), .I3(\genblk8[4].right_edge_pb_reg[24]_0 ), .I4(\genblk8[6].right_edge_pb_reg[36]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_0 ), .O(\prbs_state_r[2]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT5 #( .INIT(32'hFFFFFFFE)) \prbs_state_r[2]_i_8 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\prbs_state_r[2]_i_8_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \prbs_state_r[2]_i_9 (.I0(compare_err_pb_and_reg_n_0), .I1(\prbs_state_r[2]_i_11_n_0 ), .I2(\match_flag_and_reg_n_0_[6] ), .I3(\match_flag_and_reg_n_0_[7] ), .I4(\match_flag_and_reg_n_0_[4] ), .I5(\match_flag_and_reg_n_0_[5] ), .O(\prbs_state_r[2]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT5 #( .INIT(32'hE4A5E4A0)) \prbs_state_r[3]_i_1 (.I0(Q[4]), .I1(\prbs_state_r[3]_i_2_n_0 ), .I2(Q[2]), .I3(Q[3]), .I4(\prbs_state_r[3]_i_3_n_0 ), .O(\prbs_state_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT5 #( .INIT(32'h0FF0B0FF)) \prbs_state_r[3]_i_2 (.I0(prbs_tap_en_r_reg_0), .I1(fine_inc_stage_reg_n_0), .I2(Q[1]), .I3(Q[2]), .I4(Q[0]), .O(\prbs_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAFFFFFFC00000)) \prbs_state_r[3]_i_3 (.I0(\prbs_state_r[3]_i_4_n_0 ), .I1(prbs_found_1st_edge_r_reg_0), .I2(prbs_state_r178_out), .I3(prbs_dqs_tap_limit_r), .I4(Q[1]), .I5(Q[0]), .O(\prbs_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000100)) \prbs_state_r[3]_i_4 (.I0(prbs_dec_tap_cnt[5]), .I1(prbs_dec_tap_cnt[4]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[0]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[2]), .O(\prbs_state_r[3]_i_4_n_0 )); LUT5 #( .INIT(32'h00000001)) \prbs_state_r[4]_i_11 (.I0(bit_cnt_reg__0[5]), .I1(bit_cnt_reg__0[4]), .I2(bit_cnt_reg__0[6]), .I3(bit_cnt_reg__0[7]), .I4(fine_delay_sel_i_4_n_0), .O(\prbs_state_r[4]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \prbs_state_r[4]_i_2 (.I0(\prbs_state_r[4]_i_4_n_0 ), .I1(Q[4]), .I2(\prbs_state_r[4]_i_5_n_0 ), .I3(Q[3]), .I4(\prbs_state_r[4]_i_6_n_0 ), .O(\prbs_state_r[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h4E5F4E0A)) \prbs_state_r[4]_i_3 (.I0(Q[4]), .I1(\prbs_state_r[4]_i_7_n_0 ), .I2(Q[2]), .I3(Q[3]), .I4(\prbs_state_r[4]_i_8_n_0 ), .O(\prbs_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0A3A3A3A0A0A0A0A)) \prbs_state_r[4]_i_4 (.I0(\prbs_state_r[4]_i_9_n_0 ), .I1(Q[1]), .I2(Q[2]), .I3(prbs_rdlvl_done_reg_0), .I4(Q[0]), .I5(complex_act_start), .O(\prbs_state_r[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'hFFF2FC32)) \prbs_state_r[4]_i_5 (.I0(prech_done), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(cnt_wait_state), .O(\prbs_state_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFAEF45FFFAEA40)) \prbs_state_r[4]_i_6 (.I0(Q[2]), .I1(num_samples_done_r), .I2(Q[1]), .I3(cnt_wait_state), .I4(Q[0]), .I5(prbs_rdlvl_start_reg_0), .O(\prbs_state_r[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT5 #( .INIT(32'hAA080000)) \prbs_state_r[4]_i_7 (.I0(Q[1]), .I1(fine_inc_stage_reg_n_0), .I2(prbs_tap_en_r_reg_0), .I3(Q[0]), .I4(Q[2]), .O(\prbs_state_r[4]_i_7_n_0 )); LUT6 #( .INIT(64'h8080808480848084)) \prbs_state_r[4]_i_8 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(prbs_dqs_tap_limit_r), .I4(prbs_state_r178_out), .I5(prbs_found_1st_edge_r_reg_0), .O(\prbs_state_r[4]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0FFCFAFA0F0C0)) \prbs_state_r[4]_i_9 (.I0(\prbs_state_r[4]_i_11_n_0 ), .I1(\match_flag_or_reg[0]_0 ), .I2(Q[1]), .I3(num_samples_done_r), .I4(Q[0]), .I5(cnt_wait_state), .O(\prbs_state_r[4]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \prbs_state_r_reg[0] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[0]_i_1_n_0 ), .Q(Q[0]), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \prbs_state_r_reg[1] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[1]_i_1_n_0 ), .Q(Q[1]), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \prbs_state_r_reg[2] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r_reg[2]_i_1_n_0 ), .Q(Q[2]), .R(rstdiv0_sync_r1_reg_rep__8)); MUXF7 \prbs_state_r_reg[2]_i_1 (.I0(\prbs_state_r[2]_i_2_n_0 ), .I1(\prbs_state_r[2]_i_3_n_0 ), .O(\prbs_state_r_reg[2]_i_1_n_0 ), .S(Q[4])); FDRE #( .INIT(1'b0)) \prbs_state_r_reg[3] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[3]_i_1_n_0 ), .Q(Q[3]), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \prbs_state_r_reg[4] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[4]_i_3_n_0 ), .Q(Q[4]), .R(rstdiv0_sync_r1_reg_rep__8)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) prbs_tap_en_r_i_2 (.I0(\fine_pi_dec_cnt_reg_n_0_[2] ), .I1(\fine_pi_dec_cnt_reg_n_0_[0] ), .I2(\fine_pi_dec_cnt_reg_n_0_[1] ), .I3(\fine_pi_dec_cnt_reg_n_0_[4] ), .I4(\fine_pi_dec_cnt_reg_n_0_[3] ), .I5(\fine_pi_dec_cnt_reg_n_0_[5] ), .O(prbs_tap_en_r_reg_0)); FDRE #( .INIT(1'b0)) prbs_tap_en_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_2 ), .Q(pi_en_stg2_f_timing_reg_0), .R(rstdiv0_sync_r1_reg_rep__8)); LUT6 #( .INIT(64'h888888B8888B8B88)) prbs_tap_inc_r_i_2 (.I0(prbs_tap_inc_r_i_3_n_0), .I1(Q[2]), .I2(Q[0]), .I3(Q[4]), .I4(Q[3]), .I5(Q[1]), .O(prbs_tap_en_r)); LUT6 #( .INIT(64'h1454051504440515)) prbs_tap_inc_r_i_3 (.I0(Q[4]), .I1(Q[1]), .I2(Q[0]), .I3(prbs_dqs_tap_limit_r), .I4(Q[3]), .I5(prbs_tap_en_r_reg_0), .O(prbs_tap_inc_r_i_3_n_0)); FDRE #( .INIT(1'b0)) prbs_tap_inc_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_1 ), .Q(prbs_tap_inc_r), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) rd_valid_r1_reg (.C(CLK), .CE(1'b1), .D(mux_rd_valid_r), .Q(rd_valid_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) rd_valid_r2_reg (.C(CLK), .CE(1'b1), .D(rd_valid_r1), .Q(rd_valid_r2_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'h000000000000E5A5)) \rd_victim_sel[0]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(\rd_victim_sel_reg[2]_1 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_3 ), .I4(num_samples_done_r), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\rd_victim_sel[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000DC9C)) \rd_victim_sel[1]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(\rd_victim_sel_reg[2]_1 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_3 ), .I4(num_samples_done_r), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\rd_victim_sel[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000FF40)) \rd_victim_sel[2]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(\rd_victim_sel_reg[2]_1 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_3 ), .I4(num_samples_done_r), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\rd_victim_sel[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rd_victim_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel[0]_i_1_n_0 ), .Q(\rd_victim_sel_reg[2]_2 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_victim_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel[1]_i_1_n_0 ), .Q(\rd_victim_sel_reg[2]_1 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_victim_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel[2]_i_1_n_0 ), .Q(\rd_victim_sel_reg[2]_3 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[0]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .O(\rdlvl_cpt_tap_cnt_reg[5]_1 [0])); LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[3]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [2]), .O(\rdlvl_cpt_tap_cnt_reg[5]_1 [1])); LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[5]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [3]), .O(\rdlvl_cpt_tap_cnt_reg[5]_1 [2])); FDRE #( .INIT(1'b0)) \rdlvl_cpt_tap_cnt_reg[0] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\rdlvl_cpt_tap_cnt_reg[5]_1 [0]), .Q(rdlvl_cpt_tap_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \rdlvl_cpt_tap_cnt_reg[1] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\calib_sel_reg[3]_0 ), .Q(rdlvl_cpt_tap_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \rdlvl_cpt_tap_cnt_reg[2] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\calib_sel_reg[3]_1 ), .Q(rdlvl_cpt_tap_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \rdlvl_cpt_tap_cnt_reg[3] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .Q(rdlvl_cpt_tap_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \rdlvl_cpt_tap_cnt_reg[4] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\calib_sel_reg[3]_2 ), .Q(rdlvl_cpt_tap_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE #( .INIT(1'b0)) \rdlvl_cpt_tap_cnt_reg[5] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]), .Q(rdlvl_cpt_tap_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__9)); LUT5 #( .INIT(32'h80880080)) \ref_bit[7]_i_1 (.I0(bit_cnt0), .I1(ref_right_edge125_in), .I2(\ref_bit[7]_i_3_n_0 ), .I3(\ref_right_edge[5]_i_1_n_0 ), .I4(\ref_right_edge_reg_n_0_[5] ), .O(ref_right_edge)); LUT5 #( .INIT(32'hB2FF00B2)) \ref_bit[7]_i_3 (.I0(\ref_bit[7]_i_6_n_0 ), .I1(\ref_right_edge[3]_i_1_n_0 ), .I2(\ref_right_edge_reg_n_0_[3] ), .I3(\ref_right_edge[4]_i_1_n_0 ), .I4(\ref_right_edge_reg_n_0_[4] ), .O(\ref_bit[7]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_bit[7]_i_4 (.I0(\ref_bit_per_bit_reg_n_0_[3] ), .I1(\ref_bit_per_bit_reg_n_0_[2] ), .I2(bit_cnt_reg__0[1]), .I3(\ref_bit_per_bit_reg_n_0_[1] ), .I4(bit_cnt_reg__0[0]), .I5(\ref_bit_per_bit_reg_n_0_[0] ), .O(\ref_bit[7]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_bit[7]_i_5 (.I0(\ref_bit_per_bit_reg_n_0_[7] ), .I1(\ref_bit_per_bit_reg_n_0_[6] ), .I2(bit_cnt_reg__0[1]), .I3(\ref_bit_per_bit_reg_n_0_[5] ), .I4(bit_cnt_reg__0[0]), .I5(\ref_bit_per_bit_reg_n_0_[4] ), .O(\ref_bit[7]_i_5_n_0 )); LUT6 #( .INIT(64'hDF0DFFFF0000DF0D)) \ref_bit[7]_i_6 (.I0(\ref_right_edge[0]_i_1_n_0 ), .I1(\ref_right_edge_reg_n_0_[0] ), .I2(\ref_right_edge[1]_i_1_n_0 ), .I3(\ref_right_edge_reg_n_0_[1] ), .I4(\ref_right_edge[2]_i_1_n_0 ), .I5(\ref_right_edge_reg_n_0_[2] ), .O(\ref_bit[7]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000200000)) \ref_bit_per_bit[7]_i_1 (.I0(ref_bit_per_bit0), .I1(\ref_bit_per_bit[7]_i_2_n_0 ), .I2(Q[0]), .I3(\ref_bit_per_bit[7]_i_3_n_0 ), .I4(Q[1]), .I5(Q[4]), .O(ref_bit_per_bit)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT2 #( .INIT(4'hE)) \ref_bit_per_bit[7]_i_2 (.I0(\stage_cnt_reg_n_0_[0] ), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .O(\ref_bit_per_bit[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT2 #( .INIT(4'h7)) \ref_bit_per_bit[7]_i_3 (.I0(Q[2]), .I1(Q[3]), .O(\ref_bit_per_bit[7]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[0] (.C(CLK), .CE(ref_bit_per_bit), .D(D[0]), .Q(\ref_bit_per_bit_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[1] (.C(CLK), .CE(ref_bit_per_bit), .D(D[1]), .Q(\ref_bit_per_bit_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[2] (.C(CLK), .CE(ref_bit_per_bit), .D(D[2]), .Q(\ref_bit_per_bit_reg_n_0_[2] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[3] (.C(CLK), .CE(ref_bit_per_bit), .D(D[3]), .Q(\ref_bit_per_bit_reg_n_0_[3] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[4] (.C(CLK), .CE(ref_bit_per_bit), .D(D[4]), .Q(\ref_bit_per_bit_reg_n_0_[4] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[5] (.C(CLK), .CE(ref_bit_per_bit), .D(D[5]), .Q(\ref_bit_per_bit_reg_n_0_[5] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[6] (.C(CLK), .CE(ref_bit_per_bit), .D(D[6]), .Q(\ref_bit_per_bit_reg_n_0_[6] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_per_bit_reg[7] (.C(CLK), .CE(ref_bit_per_bit), .D(D[7]), .Q(\ref_bit_per_bit_reg_n_0_[7] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[0] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[0]), .Q(\ref_bit_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[1] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[1]), .Q(\ref_bit_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[2] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[2]), .Q(\ref_bit_reg_n_0_[2] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[3] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[3]), .Q(ref_bit[3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[4] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[4]), .Q(ref_bit[4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[5] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[5]), .Q(ref_bit[5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[6] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[6]), .Q(ref_bit[6]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \ref_bit_reg[7] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[7]), .Q(ref_bit[7]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_bit_reg[7]_i_2 (.I0(\ref_bit[7]_i_4_n_0 ), .I1(\ref_bit[7]_i_5_n_0 ), .O(ref_right_edge125_in), .S(bit_cnt_reg__0[2])); LUT5 #( .INIT(32'hB8BBB888)) \ref_right_edge[0]_i_1 (.I0(\ref_right_edge[2]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge_reg[0]_i_2_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_6 ), .I4(\ref_right_edge[0]_i_3_n_0 ), .O(\ref_right_edge[0]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[0]_i_3 (.I0(\ref_right_edge[4]_i_9_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_5 ), .I2(\ref_right_edge[0]_i_4_n_0 ), .O(\ref_right_edge[0]_i_3_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[0]_i_4 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\ref_right_edge[0]_i_4_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \ref_right_edge[1]_i_1 (.I0(\ref_right_edge[3]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge_reg[1]_i_2_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_6 ), .I4(\ref_right_edge[1]_i_3_n_0 ), .O(\ref_right_edge[1]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[1]_i_3 (.I0(\ref_right_edge[5]_i_15_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_5 ), .I2(\ref_right_edge[1]_i_6_n_0 ), .O(\ref_right_edge[1]_i_3_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[1]_i_4 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\ref_right_edge[1]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[1]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\ref_right_edge[1]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[1]_i_6 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\ref_right_edge[1]_i_6_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[2]_i_1 (.I0(\ref_right_edge[4]_i_4_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge[2]_i_2_n_0 ), .O(\ref_right_edge[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_right_edge[2]_i_2 (.I0(\ref_right_edge[4]_i_7_n_0 ), .I1(\ref_right_edge[4]_i_6_n_0 ), .I2(\ref_right_edge_reg[5]_i_3_n_6 ), .I3(\ref_right_edge[4]_i_5_n_0 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[2]_i_3_n_0 ), .O(\ref_right_edge[2]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[2]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\ref_right_edge[2]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[3]_i_1 (.I0(\ref_right_edge[5]_i_5_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge[3]_i_2_n_0 ), .O(\ref_right_edge[3]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_right_edge[3]_i_2 (.I0(\ref_right_edge[5]_i_13_n_0 ), .I1(\ref_right_edge[5]_i_12_n_0 ), .I2(\ref_right_edge_reg[5]_i_3_n_6 ), .I3(\ref_right_edge[5]_i_7_n_0 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[3]_i_3_n_0 ), .O(\ref_right_edge[3]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[3]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\ref_right_edge[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \ref_right_edge[4]_i_1 (.I0(\ref_right_edge[4]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_6 ), .I2(\ref_right_edge_reg[4]_i_3_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_7 ), .I4(\ref_right_edge[4]_i_4_n_0 ), .O(\ref_right_edge[4]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_10 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\ref_right_edge[4]_i_10_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_11 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\ref_right_edge[4]_i_11_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \ref_right_edge[4]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[4]_i_5_n_0 ), .O(\ref_right_edge[4]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_right_edge[4]_i_4 (.I0(\ref_right_edge[4]_i_8_n_0 ), .I1(\ref_right_edge[4]_i_9_n_0 ), .I2(\ref_right_edge_reg[5]_i_3_n_6 ), .I3(\ref_right_edge[4]_i_10_n_0 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[4]_i_11_n_0 ), .O(\ref_right_edge[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\ref_right_edge[4]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_6 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\ref_right_edge[4]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_7 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\ref_right_edge[4]_i_7_n_0 )); LUT4 #( .INIT(16'h00E2)) \ref_right_edge[4]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .O(\ref_right_edge[4]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_9 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\ref_right_edge[4]_i_9_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \ref_right_edge[5]_i_1 (.I0(\ref_right_edge[5]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_6 ), .I2(\ref_right_edge_reg[5]_i_4_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_7 ), .I4(\ref_right_edge[5]_i_5_n_0 ), .O(\ref_right_edge[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \ref_right_edge[5]_i_10 (.I0(bit_cnt_reg__0[1]), .O(\ref_right_edge[5]_i_10_n_0 )); LUT1 #( .INIT(2'h2)) \ref_right_edge[5]_i_11 (.I0(bit_cnt_reg__0[0]), .O(\ref_right_edge[5]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_12 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\ref_right_edge[5]_i_12_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_13 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\ref_right_edge[5]_i_13_n_0 )); LUT4 #( .INIT(16'h00E2)) \ref_right_edge[5]_i_14 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .O(\ref_right_edge[5]_i_14_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_15 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\ref_right_edge[5]_i_15_n_0 )); LUT2 #( .INIT(4'h9)) \ref_right_edge[5]_i_16 (.I0(bit_cnt_reg__0[2]), .I1(bit_cnt_reg__0[4]), .O(\ref_right_edge[5]_i_16_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \ref_right_edge[5]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[5]_i_7_n_0 ), .O(\ref_right_edge[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \ref_right_edge[5]_i_5 (.I0(\ref_right_edge[5]_i_14_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_5 ), .I2(\ref_right_edge[5]_i_15_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_6 ), .I4(\ref_right_edge_reg[1]_i_2_n_0 ), .O(\ref_right_edge[5]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_7 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\ref_right_edge[5]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \ref_right_edge[5]_i_8 (.I0(bit_cnt_reg__0[1]), .I1(bit_cnt_reg__0[3]), .O(\ref_right_edge[5]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \ref_right_edge[5]_i_9 (.I0(bit_cnt_reg__0[0]), .I1(bit_cnt_reg__0[2]), .O(\ref_right_edge[5]_i_9_n_0 )); FDSE #( .INIT(1'b1)) \ref_right_edge_reg[0] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[0]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[0] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_right_edge_reg[0]_i_2 (.I0(\ref_right_edge[4]_i_11_n_0 ), .I1(\ref_right_edge[4]_i_10_n_0 ), .O(\ref_right_edge_reg[0]_i_2_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); FDSE #( .INIT(1'b1)) \ref_right_edge_reg[1] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[1]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[1] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_right_edge_reg[1]_i_2 (.I0(\ref_right_edge[1]_i_4_n_0 ), .I1(\ref_right_edge[1]_i_5_n_0 ), .O(\ref_right_edge_reg[1]_i_2_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); FDSE #( .INIT(1'b1)) \ref_right_edge_reg[2] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[2]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[2] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \ref_right_edge_reg[3] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[3]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[3] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \ref_right_edge_reg[4] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[4]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[4] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_right_edge_reg[4]_i_3 (.I0(\ref_right_edge[4]_i_6_n_0 ), .I1(\ref_right_edge[4]_i_7_n_0 ), .O(\ref_right_edge_reg[4]_i_3_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); FDSE #( .INIT(1'b1)) \ref_right_edge_reg[5] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[5]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[5] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); CARRY4 \ref_right_edge_reg[5]_i_3 (.CI(1'b0), .CO({\ref_right_edge_reg[5]_i_3_n_0 ,\ref_right_edge_reg[5]_i_3_n_1 ,\ref_right_edge_reg[5]_i_3_n_2 ,\ref_right_edge_reg[5]_i_3_n_3 }), .CYINIT(1'b0), .DI({bit_cnt_reg__0[1:0],1'b0,1'b1}), .O({\ref_right_edge_reg[5]_i_3_n_4 ,\ref_right_edge_reg[5]_i_3_n_5 ,\ref_right_edge_reg[5]_i_3_n_6 ,\ref_right_edge_reg[5]_i_3_n_7 }), .S({\ref_right_edge[5]_i_8_n_0 ,\ref_right_edge[5]_i_9_n_0 ,\ref_right_edge[5]_i_10_n_0 ,\ref_right_edge[5]_i_11_n_0 })); MUXF7 \ref_right_edge_reg[5]_i_4 (.I0(\ref_right_edge[5]_i_12_n_0 ), .I1(\ref_right_edge[5]_i_13_n_0 ), .O(\ref_right_edge_reg[5]_i_4_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); CARRY4 \ref_right_edge_reg[5]_i_6 (.CI(\ref_right_edge_reg[5]_i_3_n_0 ), .CO(\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED [3:1],\ref_right_edge_reg[5]_i_6_n_7 }), .S({1'b0,1'b0,1'b0,\ref_right_edge[5]_i_16_n_0 })); LUT2 #( .INIT(4'hE)) reset_rd_addr_r1_i_1 (.I0(reset_rd_addr), .I1(complex_ocal_reset_rd_addr), .O(reset_rd_addr0)); FDRE #( .INIT(1'b0)) reset_rd_addr_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_2 ), .Q(reset_rd_addr), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'h00000000FFFFFFFD)) right_edge_found_i_2 (.I0(right_edge_found_i_4_n_0), .I1(\genblk8[3].right_edge_pb_reg[18]_0 ), .I2(\genblk8[2].right_edge_pb_reg[12]_0 ), .I3(\genblk8[1].right_edge_pb_reg[6]_0 ), .I4(\genblk8[0].right_edge_pb_reg[0]_0 ), .I5(right_edge_found_reg_0), .O(right_edge_found_reg_1)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT5 #( .INIT(32'h80000008)) right_edge_found_i_3 (.I0(Q[1]), .I1(right_edge_found_i_5_n_0), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .O(right_edge_found)); LUT4 #( .INIT(16'h0001)) right_edge_found_i_4 (.I0(\genblk8[6].right_edge_pb_reg[36]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_0 ), .I2(\genblk8[5].right_edge_pb_reg[30]_0 ), .I3(\genblk8[4].right_edge_pb_reg[24]_0 ), .O(right_edge_found_i_4_n_0)); LUT6 #( .INIT(64'h0FE00FE00FE000E0)) right_edge_found_i_5 (.I0(right_edge_found_reg_1), .I1(no_err_win_detected_latch_reg_0), .I2(Q[3]), .I3(Q[4]), .I4(num_samples_done_r), .I5(\match_flag_or_reg[0]_0 ), .O(right_edge_found_i_5_n_0)); FDRE #( .INIT(1'b0)) right_edge_found_reg (.C(CLK), .CE(1'b1), .D(no_err_win_detected_reg_1), .Q(right_edge_found_reg_0), .R(rstdiv0_sync_r1_reg_rep__7)); LUT3 #( .INIT(8'hB8)) \right_edge_ref[0]_i_1 (.I0(\right_edge_ref[2]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[0]_i_2_n_0 ), .O(\right_edge_ref[0]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[0]_i_2 (.I0(\right_edge_ref_reg[4]_i_10_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[0]_i_3_n_0 ), .O(\right_edge_ref[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[0]_i_3 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\right_edge_ref[0]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \right_edge_ref[1]_i_1 (.I0(\right_edge_ref[3]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[1]_i_2_n_0 ), .O(\right_edge_ref[1]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[1]_i_2 (.I0(\right_edge_ref_reg[5]_i_10_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[5]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[1]_i_3_n_0 ), .O(\right_edge_ref[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[1]_i_3 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\right_edge_ref[1]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \right_edge_ref[2]_i_1 (.I0(\right_edge_ref[4]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[2]_i_2_n_0 ), .O(\right_edge_ref[2]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[2]_i_2 (.I0(\right_edge_ref_reg[4]_i_3_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[4]_i_5_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[2]_i_3_n_0 ), .O(\right_edge_ref[2]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[2]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\right_edge_ref[2]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \right_edge_ref[3]_i_1 (.I0(\right_edge_ref[5]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[3]_i_2_n_0 ), .O(\right_edge_ref[3]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[3]_i_2 (.I0(\right_edge_ref_reg[5]_i_3_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[5]_i_5_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[3]_i_3_n_0 ), .O(\right_edge_ref[3]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[3]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\right_edge_ref[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[4]_i_1 (.I0(\right_edge_ref[4]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref_reg[4]_i_3_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\right_edge_ref[4]_i_4_n_0 ), .O(\right_edge_ref[4]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_11 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\right_edge_ref[4]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_12 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\right_edge_ref[4]_i_12_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \right_edge_ref[4]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\right_edge_ref[4]_i_5_n_0 ), .O(\right_edge_ref[4]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[4]_i_4 (.I0(\right_edge_ref[4]_i_8_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\right_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\right_edge_ref_reg[4]_i_10_n_0 ), .O(\right_edge_ref[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\right_edge_ref[4]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_6 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\right_edge_ref[4]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_7 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\right_edge_ref[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT4 #( .INIT(16'h00E2)) \right_edge_ref[4]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\right_edge_ref[4]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_9 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\right_edge_ref[4]_i_9_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[5]_i_1 (.I0(\right_edge_ref[5]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref_reg[5]_i_3_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\right_edge_ref[5]_i_4_n_0 ), .O(\right_edge_ref[5]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_11 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\right_edge_ref[5]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_12 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\right_edge_ref[5]_i_12_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \right_edge_ref[5]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\right_edge_ref[5]_i_5_n_0 ), .O(\right_edge_ref[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[5]_i_4 (.I0(\right_edge_ref[5]_i_8_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\right_edge_ref[5]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\right_edge_ref_reg[5]_i_10_n_0 ), .O(\right_edge_ref[5]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\right_edge_ref[5]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_6 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\right_edge_ref[5]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_7 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\right_edge_ref[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT4 #( .INIT(16'h00E2)) \right_edge_ref[5]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\right_edge_ref[5]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_9 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\right_edge_ref[5]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \right_edge_ref_reg[0] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[0]_i_1_n_0 ), .Q(right_edge_ref[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \right_edge_ref_reg[1] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[1]_i_1_n_0 ), .Q(right_edge_ref[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \right_edge_ref_reg[2] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[2]_i_1_n_0 ), .Q(right_edge_ref[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \right_edge_ref_reg[3] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[3]_i_1_n_0 ), .Q(right_edge_ref[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \right_edge_ref_reg[4] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[4]_i_1_n_0 ), .Q(right_edge_ref[4]), .R(1'b0)); MUXF7 \right_edge_ref_reg[4]_i_10 (.I0(\right_edge_ref[4]_i_11_n_0 ), .I1(\right_edge_ref[4]_i_12_n_0 ), .O(\right_edge_ref_reg[4]_i_10_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); MUXF7 \right_edge_ref_reg[4]_i_3 (.I0(\right_edge_ref[4]_i_6_n_0 ), .I1(\right_edge_ref[4]_i_7_n_0 ), .O(\right_edge_ref_reg[4]_i_3_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); FDRE #( .INIT(1'b0)) \right_edge_ref_reg[5] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[5]_i_1_n_0 ), .Q(right_edge_ref[5]), .R(1'b0)); MUXF7 \right_edge_ref_reg[5]_i_10 (.I0(\right_edge_ref[5]_i_11_n_0 ), .I1(\right_edge_ref[5]_i_12_n_0 ), .O(\right_edge_ref_reg[5]_i_10_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); MUXF7 \right_edge_ref_reg[5]_i_3 (.I0(\right_edge_ref[5]_i_6_n_0 ), .I1(\right_edge_ref[5]_i_7_n_0 ), .O(\right_edge_ref_reg[5]_i_3_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); LUT6 #( .INIT(64'h00000000FFFFFFFE)) \samples_cnt_r[0]_i_1 (.I0(\samples_cnt_r_reg_n_0_[11] ), .I1(\samples_cnt_r_reg_n_0_[10] ), .I2(\samples_cnt_r_reg_n_0_[1] ), .I3(\samples_cnt_r[0]_i_2_n_0 ), .I4(\samples_cnt_r[0]_i_3_n_0 ), .I5(\samples_cnt_r_reg_n_0_[0] ), .O(\samples_cnt_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'hFFFE)) \samples_cnt_r[0]_i_2 (.I0(\samples_cnt_r_reg_n_0_[7] ), .I1(\samples_cnt_r_reg_n_0_[6] ), .I2(\samples_cnt_r_reg_n_0_[9] ), .I3(\samples_cnt_r_reg_n_0_[8] ), .O(\samples_cnt_r[0]_i_2_n_0 )); LUT4 #( .INIT(16'hFFF7)) \samples_cnt_r[0]_i_3 (.I0(\samples_cnt_r_reg_n_0_[3] ), .I1(\samples_cnt_r_reg_n_0_[2] ), .I2(\samples_cnt_r_reg_n_0_[5] ), .I3(\samples_cnt_r_reg_n_0_[4] ), .O(\samples_cnt_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[10]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[10]), .O(\samples_cnt_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[11]_i_2 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[11]), .O(\samples_cnt_r[11]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \samples_cnt_r[11]_i_3 (.I0(\samples_cnt_r_reg_n_0_[11] ), .I1(\samples_cnt_r_reg_n_0_[10] ), .I2(\samples_cnt_r_reg_n_0_[1] ), .I3(\samples_cnt_r[0]_i_2_n_0 ), .I4(\samples_cnt_r[0]_i_3_n_0 ), .I5(\samples_cnt_r_reg_n_0_[0] ), .O(\rd_victim_sel_reg[2]_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[11]_i_5 (.I0(\samples_cnt_r_reg_n_0_[11] ), .O(\samples_cnt_r[11]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[11]_i_6 (.I0(\samples_cnt_r_reg_n_0_[10] ), .O(\samples_cnt_r[11]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[11]_i_7 (.I0(\samples_cnt_r_reg_n_0_[9] ), .O(\samples_cnt_r[11]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[1]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[1]), .O(\samples_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[2]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[2]), .O(\samples_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[3]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[3]), .O(\samples_cnt_r[3]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \samples_cnt_r[4]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[4]), .O(\samples_cnt_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_3 (.I0(\samples_cnt_r_reg_n_0_[4] ), .O(\samples_cnt_r[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_4 (.I0(\samples_cnt_r_reg_n_0_[3] ), .O(\samples_cnt_r[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_5 (.I0(\samples_cnt_r_reg_n_0_[2] ), .O(\samples_cnt_r[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_6 (.I0(\samples_cnt_r_reg_n_0_[1] ), .O(\samples_cnt_r[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[5]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[5]), .O(\samples_cnt_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[6]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[6]), .O(\samples_cnt_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[7]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[7]), .O(\samples_cnt_r[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[8]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[8]), .O(\samples_cnt_r[8]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_3 (.I0(\samples_cnt_r_reg_n_0_[8] ), .O(\samples_cnt_r[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_4 (.I0(\samples_cnt_r_reg_n_0_[7] ), .O(\samples_cnt_r[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_5 (.I0(\samples_cnt_r_reg_n_0_[6] ), .O(\samples_cnt_r[8]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_6 (.I0(\samples_cnt_r_reg_n_0_[5] ), .O(\samples_cnt_r[8]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[9]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[9]), .O(\samples_cnt_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[0] (.C(CLK), .CE(E), .D(\samples_cnt_r[0]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[10] (.C(CLK), .CE(E), .D(\samples_cnt_r[10]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[10] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[11] (.C(CLK), .CE(E), .D(\samples_cnt_r[11]_i_2_n_0 ), .Q(\samples_cnt_r_reg_n_0_[11] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \samples_cnt_r_reg[11]_i_4 (.CI(\samples_cnt_r_reg[8]_i_2_n_0 ), .CO({\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED [3:2],\samples_cnt_r_reg[11]_i_4_n_2 ,\samples_cnt_r_reg[11]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}), .S({1'b0,\samples_cnt_r[11]_i_5_n_0 ,\samples_cnt_r[11]_i_6_n_0 ,\samples_cnt_r[11]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[1] (.C(CLK), .CE(E), .D(\samples_cnt_r[1]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[2] (.C(CLK), .CE(E), .D(\samples_cnt_r[2]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[3] (.C(CLK), .CE(E), .D(\samples_cnt_r[3]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[4] (.C(CLK), .CE(E), .D(\samples_cnt_r[4]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \samples_cnt_r_reg[4]_i_2 (.CI(1'b0), .CO({\samples_cnt_r_reg[4]_i_2_n_0 ,\samples_cnt_r_reg[4]_i_2_n_1 ,\samples_cnt_r_reg[4]_i_2_n_2 ,\samples_cnt_r_reg[4]_i_2_n_3 }), .CYINIT(\samples_cnt_r_reg_n_0_[0] ), .DI({1'b0,1'b0,1'b0,1'b0}), .O(data0[4:1]), .S({\samples_cnt_r[4]_i_3_n_0 ,\samples_cnt_r[4]_i_4_n_0 ,\samples_cnt_r[4]_i_5_n_0 ,\samples_cnt_r[4]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[5] (.C(CLK), .CE(E), .D(\samples_cnt_r[5]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[6] (.C(CLK), .CE(E), .D(\samples_cnt_r[6]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[7] (.C(CLK), .CE(E), .D(\samples_cnt_r[7]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[8] (.C(CLK), .CE(E), .D(\samples_cnt_r[8]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \samples_cnt_r_reg[8]_i_2 (.CI(\samples_cnt_r_reg[4]_i_2_n_0 ), .CO({\samples_cnt_r_reg[8]_i_2_n_0 ,\samples_cnt_r_reg[8]_i_2_n_1 ,\samples_cnt_r_reg[8]_i_2_n_2 ,\samples_cnt_r_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(data0[8:5]), .S({\samples_cnt_r[8]_i_3_n_0 ,\samples_cnt_r[8]_i_4_n_0 ,\samples_cnt_r[8]_i_5_n_0 ,\samples_cnt_r[8]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \samples_cnt_r_reg[9] (.C(CLK), .CE(E), .D(\samples_cnt_r[9]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[9] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT2 #( .INIT(4'h7)) \smallest_right_edge[0]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\smallest_right_edge[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'hD7)) \smallest_right_edge[1]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\smallest_right_edge[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT4 #( .INIT(16'hDDD7)) \smallest_right_edge[2]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\smallest_right_edge[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT5 #( .INIT(32'hDDDDDDD7)) \smallest_right_edge[3]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\smallest_right_edge[3]_i_1_n_0 )); LUT6 #( .INIT(64'hDDDDDDDDDDDDDDD7)) \smallest_right_edge[4]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\smallest_right_edge[4]_i_1_n_0 )); LUT6 #( .INIT(64'h8000800000080308)) \smallest_right_edge[5]_i_1 (.I0(\smallest_right_edge[5]_i_3_n_0 ), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .I5(Q[1]), .O(smallest_right_edge)); LUT2 #( .INIT(4'h7)) \smallest_right_edge[5]_i_2 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\smallest_right_edge[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0F40004000400040)) \smallest_right_edge[5]_i_3 (.I0(no_err_win_detected_latch_reg_0), .I1(right_edge_found_reg_1), .I2(Q[3]), .I3(Q[4]), .I4(\smallest_right_edge[5]_i_4_n_0 ), .I5(prbs_state_r1), .O(\smallest_right_edge[5]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \smallest_right_edge[5]_i_4 (.I0(num_samples_done_r), .I1(right_edge_found_reg_0), .O(\smallest_right_edge[5]_i_4_n_0 )); FDSE #( .INIT(1'b1)) \smallest_right_edge_reg[0] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[0]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[0] ), .S(rstdiv0_sync_r1_reg_rep__7)); FDSE #( .INIT(1'b1)) \smallest_right_edge_reg[1] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[1]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[1] ), .S(rstdiv0_sync_r1_reg_rep__7)); FDSE #( .INIT(1'b1)) \smallest_right_edge_reg[2] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[2]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[2] ), .S(rstdiv0_sync_r1_reg_rep__7)); FDSE #( .INIT(1'b1)) \smallest_right_edge_reg[3] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[3]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[3] ), .S(rstdiv0_sync_r1_reg_rep__7)); FDSE #( .INIT(1'b1)) \smallest_right_edge_reg[4] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[4]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[4] ), .S(rstdiv0_sync_r1_reg_rep__7)); FDSE #( .INIT(1'b1)) \smallest_right_edge_reg[5] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[5]_i_2_n_0 ), .Q(\smallest_right_edge_reg_n_0_[5] ), .S(rstdiv0_sync_r1_reg_rep__7)); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( .INIT(8'h38)) \stage_cnt[0]_i_1 (.I0(Q[4]), .I1(\stage_cnt[1]_i_2_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .O(\stage_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h2F80)) \stage_cnt[1]_i_1 (.I0(Q[4]), .I1(\stage_cnt_reg_n_0_[0] ), .I2(\stage_cnt[1]_i_2_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .O(\stage_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000202020002)) \stage_cnt[1]_i_2 (.I0(Q[0]), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(Q[1]), .I5(fine_delay_sel_reg_0), .O(\stage_cnt[1]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \stage_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\stage_cnt[0]_i_1_n_0 ), .Q(\stage_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \stage_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\stage_cnt[1]_i_1_n_0 ), .Q(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT6 #( .INIT(64'h00000000AAAAEAAA)) \victim_not_fixed.num_samples_done_r_i_1 (.I0(num_samples_done_r), .I1(\rd_victim_sel_reg[2]_3 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_1 ), .I4(\rd_victim_sel_reg[2]_0 ), .I5(\victim_not_fixed.num_samples_done_r_i_2_n_0 ), .O(\victim_not_fixed.num_samples_done_r_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAEBEEAAAAAAAA)) \victim_not_fixed.num_samples_done_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(Q[2]), .I2(Q[3]), .I3(Q[1]), .I4(Q[4]), .I5(Q[0]), .O(\victim_not_fixed.num_samples_done_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \victim_not_fixed.num_samples_done_r_reg (.C(CLK), .CE(1'b1), .D(\victim_not_fixed.num_samples_done_r_i_1_n_0 ), .Q(num_samples_done_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( .INIT(32'h00050A12)) wait_state_cnt_en_r_i_1 (.I0(Q[2]), .I1(Q[3]), .I2(Q[4]), .I3(Q[1]), .I4(Q[0]), .O(wait_state_cnt_en_r0)); FDRE #( .INIT(1'b0)) wait_state_cnt_en_r_reg (.C(CLK), .CE(1'b1), .D(wait_state_cnt_en_r0), .Q(wait_state_cnt_en_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT1 #( .INIT(2'h1)) \wait_state_cnt_r[0]_i_1 (.I0(wait_state_cnt_r_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT2 #( .INIT(4'h6)) \wait_state_cnt_r[1]_i_1 (.I0(wait_state_cnt_r_reg__0[0]), .I1(wait_state_cnt_r_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'h78)) \wait_state_cnt_r[2]_i_1 (.I0(wait_state_cnt_r_reg__0[1]), .I1(wait_state_cnt_r_reg__0[0]), .I2(wait_state_cnt_r_reg__0[2]), .O(\wait_state_cnt_r[2]_i_1_n_0 )); LUT5 #( .INIT(32'hD5555555)) \wait_state_cnt_r[3]_i_1 (.I0(wait_state_cnt_en_r), .I1(wait_state_cnt_r_reg__0[3]), .I2(wait_state_cnt_r_reg__0[2]), .I3(wait_state_cnt_r_reg__0[0]), .I4(wait_state_cnt_r_reg__0[1]), .O(\wait_state_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT4 #( .INIT(16'h7F80)) \wait_state_cnt_r[3]_i_2 (.I0(wait_state_cnt_r_reg__0[0]), .I1(wait_state_cnt_r_reg__0[1]), .I2(wait_state_cnt_r_reg__0[2]), .I3(wait_state_cnt_r_reg__0[3]), .O(p_0_in[3])); FDRE #( .INIT(1'b0)) \wait_state_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in[0]), .Q(wait_state_cnt_r_reg__0[0]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wait_state_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in[1]), .Q(wait_state_cnt_r_reg__0[1]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wait_state_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wait_state_cnt_r[2]_i_1_n_0 ), .Q(wait_state_cnt_r_reg__0[2]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wait_state_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in[3]), .Q(wait_state_cnt_r_reg__0[3]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_rdlvl" *) module ddr3_ifmig_7series_v4_0_ddr_phy_rdlvl (mpr_rdlvl_done_r1_reg_0, store_sr_r_reg_0, sr_valid_r1_reg_0, found_stable_eye_last_r_reg_0, found_first_edge_r_reg_0, mpr_rdlvl_start_r, mpr_valid_r1_reg_0, detect_edge_done_r, samp_edge_cnt0_en_r, \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 , p_0_in102_in, p_0_in99_in, p_0_in96_in, p_0_in93_in, p_0_in90_in, p_0_in87_in, p_0_in84_in, idelay_ce_int, idelay_inc_int, dqs_po_dec_done_r2, rdlvl_prech_req, pi_fine_dly_dec_done, pb_detect_edge_done_r, \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 , \gen_track_left_edge[0].pb_found_stable_eye_r_reg , \gen_track_left_edge[1].pb_found_stable_eye_r_reg , \gen_track_left_edge[2].pb_found_stable_eye_r_reg , \gen_track_left_edge[3].pb_found_stable_eye_r_reg , \gen_track_left_edge[4].pb_found_stable_eye_r_reg , \gen_track_left_edge[5].pb_found_stable_eye_r_reg , \gen_track_left_edge[6].pb_found_stable_eye_r_reg , \gen_track_left_edge[7].pb_found_stable_eye_r_reg , \gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 , found_edge_r_reg_0, found_edge_r_reg_1, found_edge_r_reg_2, \gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 , found_edge_r_reg_3, \gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 , \gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 , \right_edge_taps_r_reg[0]_0 , cal1_wait_r, found_stable_eye_last_r, mpr_rd_rise0_prev_r_reg_0, mpr_dec_cpt_r_reg_0, idel_adj_inc_reg_0, pi_en_stg2_f_timing_reg_0, mpr_last_byte_done, mpr_rnk_done, rdlvl_stg1_done_r1_reg, rdlvl_stg1_rank_done, rdlvl_last_byte_done, rdlvl_pi_incdec, \cnt_idel_dec_cpt_r_reg[0]_0 , \pi_dqs_found_lanes_r1_reg[3] , \pi_dqs_found_lanes_r1_reg[3]_0 , \pi_dqs_found_lanes_r1_reg[3]_1 , \pi_dqs_found_lanes_r1_reg[2] , \pi_dqs_found_lanes_r1_reg[2]_0 , \pi_dqs_found_lanes_r1_reg[2]_1 , \pi_dqs_found_lanes_r1_reg[1] , \pi_dqs_found_lanes_r1_reg[1]_0 , \pi_dqs_found_lanes_r1_reg[1]_1 , COUNTERLOADVAL, \pi_dqs_found_lanes_r1_reg[0] , \pi_dqs_found_lanes_r1_reg[0]_0 , \pi_dqs_found_lanes_r1_reg[0]_1 , \stg1_wr_rd_cnt_reg[3] , \init_state_r_reg[0] , \init_state_r_reg[0]_0 , \init_state_r_reg[0]_1 , out, idel_adj_inc_reg_1, \wait_cnt_r_reg[0]_0 , \right_edge_taps_r_reg[0]_1 , store_sr_req_r_reg_0, \rdlvl_cpt_tap_cnt_reg[4] , \rdlvl_cpt_tap_cnt_reg[1] , \rdlvl_cpt_tap_cnt_reg[2] , \pi_rdval_cnt_reg[1]_0 , \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 , \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 , \pi_stg2_reg_l_timing_reg[0]_0 , \regl_dqs_cnt_r_reg[2]_0 , \regl_dqs_cnt_reg[0]_0 , mpr_rd_rise0_prev_r_reg_1, \rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 , cal1_cnt_cpt_r1, mpr_valid_r_reg_0, \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 , \gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 , p_0_in16_in, \gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 , p_0_in13_in, \gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 , p_0_in10_in, \gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 , p_0_in7_in, \gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 , p_0_in4_in, \gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 , p_0_in1_in, \gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 , p_0_in, \gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 , pb_found_stable_eye_r76_out, \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 , pb_found_stable_eye_r72_out, \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 , pb_found_stable_eye_r68_out, \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 , pb_found_stable_eye_r64_out, \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 , pb_found_stable_eye_r60_out, \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 , pb_found_stable_eye_r56_out, \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 , pb_found_stable_eye_r52_out, \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 , \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 , \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 , \right_edge_taps_r_reg[0]_2 , idel_adj_inc_reg_2, pi_cnt_dec_reg_0, \init_state_r_reg[1] , prech_req, \init_state_r_reg[2] , \init_state_r_reg[2]_0 , \init_state_r_reg[2]_1 , \init_state_r_reg[5] , \init_state_r_reg[0]_2 , \init_state_r_reg[3] , \init_state_r_reg[0]_3 , \init_state_r_reg[4] , \init_state_r_reg[0]_4 , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] , \init_state_r_reg[2]_2 , D, \gen_byte_sel_div1.calib_in_common_reg , \gen_byte_sel_div1.byte_sel_cnt_reg[2] , \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 , cmd_delay_start0, \second_edge_taps_r_reg[5]_0 , \pi_dqs_found_lanes_r1_reg[1]_2 , \pi_dqs_found_lanes_r1_reg[2]_2 , \pi_dqs_found_lanes_r1_reg[3]_2 , rdlvl_pi_incdec_reg_0, pi_stg2_rdlvl_cnt, mpr_last_byte_done_reg_0, mpr_rank_done_r_reg_0, rdlvl_pi_incdec_reg_1, \idel_dec_cnt_reg[0]_0 , rdlvl_stg1_done_int, rdlvl_rank_done_r_reg_0, mpr_rank_done_r_reg_1, mpr_dec_cpt_r_reg_1, CLK, rstdiv0_sync_r1_reg_rep__14, sr_valid_r108_out, \rd_mux_sel_r_reg[1]_0 , \rd_mux_sel_r_reg[1]_1 , \rd_mux_sel_r_reg[1]_2 , \rd_mux_sel_r_reg[1]_3 , \rd_mux_sel_r_reg[1]_4 , \rd_mux_sel_r_reg[1]_5 , \rd_mux_sel_r_reg[1]_6 , \rd_mux_sel_r_reg[1]_7 , \rd_mux_sel_r_reg[1]_8 , \rd_mux_sel_r_reg[1]_9 , \rd_mux_sel_r_reg[1]_10 , \rd_mux_sel_r_reg[1]_11 , \rd_mux_sel_r_reg[1]_12 , \rd_mux_sel_r_reg[1]_13 , \rd_mux_sel_r_reg[1]_14 , \rd_mux_sel_r_reg[1]_15 , \rd_mux_sel_r_reg[1]_16 , \rd_mux_sel_r_reg[1]_17 , \rd_mux_sel_r_reg[1]_18 , \rd_mux_sel_r_reg[1]_19 , \rd_mux_sel_r_reg[1]_20 , \rd_mux_sel_r_reg[1]_21 , \rd_mux_sel_r_reg[1]_22 , \rd_mux_sel_r_reg[1]_23 , \rd_mux_sel_r_reg[1]_24 , \rd_mux_sel_r_reg[1]_25 , \rd_mux_sel_r_reg[1]_26 , \rd_mux_sel_r_reg[1]_27 , \rd_mux_sel_r_reg[1]_28 , \rd_mux_sel_r_reg[1]_29 , \rd_mux_sel_r_reg[1]_30 , \rd_mux_sel_r_reg[1]_31 , \rd_mux_sel_r_reg[1]_32 , \rd_mux_sel_r_reg[1]_33 , \rd_mux_sel_r_reg[1]_34 , \rd_mux_sel_r_reg[1]_35 , \rd_mux_sel_r_reg[1]_36 , \rd_mux_sel_r_reg[1]_37 , \rd_mux_sel_r_reg[1]_38 , \rd_mux_sel_r_reg[1]_39 , \rd_mux_sel_r_reg[1]_40 , \rd_mux_sel_r_reg[1]_41 , \rd_mux_sel_r_reg[1]_42 , \rd_mux_sel_r_reg[1]_43 , \rd_mux_sel_r_reg[1]_44 , \rd_mux_sel_r_reg[1]_45 , \rd_mux_sel_r_reg[1]_46 , \rd_mux_sel_r_reg[1]_47 , \rd_mux_sel_r_reg[1]_48 , \rd_mux_sel_r_reg[1]_49 , \rd_mux_sel_r_reg[1]_50 , \rd_mux_sel_r_reg[1]_51 , \rd_mux_sel_r_reg[1]_52 , \rd_mux_sel_r_reg[1]_53 , \rd_mux_sel_r_reg[1]_54 , \rd_mux_sel_r_reg[1]_55 , \rd_mux_sel_r_reg[1]_56 , \rd_mux_sel_r_reg[1]_57 , \rd_mux_sel_r_reg[1]_58 , \rd_mux_sel_r_reg[1]_59 , \rd_mux_sel_r_reg[1]_60 , \rd_mux_sel_r_reg[1]_61 , \rd_mux_sel_r_reg[1]_62 , \rd_mux_sel_r_reg[1]_63 , mpr_rdlvl_start_reg, rdlvl_stg1_start_reg, phy_rddata_en_1, rstdiv0_sync_r1_reg_rep__13, dqs_po_dec_done, samp_cnt_done_r_reg_0, samp_cnt_done_r_reg_1, samp_cnt_done_r_reg_2, samp_cnt_done_r_reg_3, samp_cnt_done_r_reg_4, samp_cnt_done_r_reg_5, samp_cnt_done_r_reg_6, \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 , mpr_rdlvl_done_r_reg_0, store_sr_req_r_reg_1, \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 , \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 , \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 , \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 , \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 , \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 , \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 , \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 , \gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 , \gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 , \gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 , \gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 , \gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 , \gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 , \gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 , \gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 , found_edge_r_reg_4, found_stable_eye_r_reg_0, \FSM_sequential_cal1_state_r_reg[4]_0 , \FSM_sequential_cal1_state_r_reg[3]_0 , \FSM_sequential_cal1_state_r_reg[2]_0 , \wait_cnt_r_reg[0]_1 , \FSM_sequential_cal1_state_r_reg[4]_1 , \FSM_sequential_cal1_state_r_reg[4]_2 , mpr_rdlvl_done_r_reg_1, \FSM_sequential_cal1_state_r_reg[4]_3 , \FSM_sequential_cal1_state_r_reg[4]_4 , \regl_dqs_cnt_reg[2]_0 , \FSM_sequential_cal1_state_r_reg[1]_0 , SR, found_stable_eye_last_r_reg_1, \gen_byte_sel_div1.calib_in_common_reg_0 , prbs_pi_stg2_f_incdec, tempmon_pi_f_inc_r, Q, prbs_pi_stg2_f_en, tempmon_pi_f_en_r, calib_in_common, \calib_sel_reg[3] , \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , \gen_byte_sel_div1.calib_in_common_reg_3 , rstdiv0_sync_r1_reg_rep__23, stg1_wr_done, wrcal_done_reg, dqs_found_done_r_reg, \init_state_r_reg[1]_0 , oclkdelay_calib_done_r_reg, \one_rank.stg1_wr_done_reg , cal1_state_r1535_out, rstdiv0_sync_r1_reg_rep__22, \calib_sel_reg[3]_0 , \po_stg2_wrcal_cnt_reg[0] , \po_stg2_wrcal_cnt_reg[1] , cal1_dq_idel_ce_reg_0, prech_done, \pi_counter_read_val_reg[5] , rstdiv0_sync_r1_reg_rep__20, \init_state_r_reg[3]_0 , wrcal_prech_req, complex_ocal_ref_req, prbs_rdlvl_prech_req_reg, dqs_found_prech_req, \init_state_r_reg[5]_0 , wrlvl_done_r1_reg, wrlvl_done_r1_reg_0, cnt_init_af_done_r, dqs_found_done_r_reg_0, prbs_rdlvl_done_reg_rep, wrlvl_byte_redo, wrlvl_final_mux, mem_init_done_r, prbs_rdlvl_done_reg_rep_0, \num_refresh_reg[1] , prbs_last_byte_done_r, wrlvl_final_mux_reg, prbs_rdlvl_done_reg_rep_1, oclkdelay_center_calib_done_r_reg, wrlvl_done_r1, wrlvl_byte_redo_reg, \dout_o_reg[6] , first_wrcal_pat_r, \dout_o_reg[6]_0 , prbs_rdlvl_done_reg, wr_level_done_reg, \prbs_dqs_cnt_r_reg[2] , \po_stg2_wrcal_cnt_reg[2] , rdlvl_stg1_start_reg_0, E, samp_edge_cnt0_en_r_reg_0, pi_cnt_dec_reg_1, rstdiv0_sync_r1_reg_rep__2); output mpr_rdlvl_done_r1_reg_0; output store_sr_r_reg_0; output sr_valid_r1_reg_0; output found_stable_eye_last_r_reg_0; output found_first_edge_r_reg_0; output mpr_rdlvl_start_r; output mpr_valid_r1_reg_0; output detect_edge_done_r; output samp_edge_cnt0_en_r; output \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ; output p_0_in102_in; output p_0_in99_in; output p_0_in96_in; output p_0_in93_in; output p_0_in90_in; output p_0_in87_in; output p_0_in84_in; output idelay_ce_int; output idelay_inc_int; output dqs_po_dec_done_r2; output rdlvl_prech_req; output pi_fine_dly_dec_done; output [7:0]pb_detect_edge_done_r; output \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ; output \gen_track_left_edge[0].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[1].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[2].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[3].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[4].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[5].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[6].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[7].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ; output found_edge_r_reg_0; output found_edge_r_reg_1; output found_edge_r_reg_2; output \gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ; output found_edge_r_reg_3; output \gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ; output \gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ; output \right_edge_taps_r_reg[0]_0 ; output cal1_wait_r; output found_stable_eye_last_r; output mpr_rd_rise0_prev_r_reg_0; output mpr_dec_cpt_r_reg_0; output idel_adj_inc_reg_0; output pi_en_stg2_f_timing_reg_0; output mpr_last_byte_done; output mpr_rnk_done; output rdlvl_stg1_done_r1_reg; output rdlvl_stg1_rank_done; output rdlvl_last_byte_done; output rdlvl_pi_incdec; output \cnt_idel_dec_cpt_r_reg[0]_0 ; output \pi_dqs_found_lanes_r1_reg[3] ; output \pi_dqs_found_lanes_r1_reg[3]_0 ; output \pi_dqs_found_lanes_r1_reg[3]_1 ; output \pi_dqs_found_lanes_r1_reg[2] ; output \pi_dqs_found_lanes_r1_reg[2]_0 ; output \pi_dqs_found_lanes_r1_reg[2]_1 ; output \pi_dqs_found_lanes_r1_reg[1] ; output \pi_dqs_found_lanes_r1_reg[1]_0 ; output \pi_dqs_found_lanes_r1_reg[1]_1 ; output [5:0]COUNTERLOADVAL; output \pi_dqs_found_lanes_r1_reg[0] ; output \pi_dqs_found_lanes_r1_reg[0]_0 ; output \pi_dqs_found_lanes_r1_reg[0]_1 ; output \stg1_wr_rd_cnt_reg[3] ; output \init_state_r_reg[0] ; output \init_state_r_reg[0]_0 ; output \init_state_r_reg[0]_1 ; output [4:0]out; output idel_adj_inc_reg_1; output [1:0]\wait_cnt_r_reg[0]_0 ; output \right_edge_taps_r_reg[0]_1 ; output store_sr_req_r_reg_0; output \rdlvl_cpt_tap_cnt_reg[4] ; output \rdlvl_cpt_tap_cnt_reg[1] ; output \rdlvl_cpt_tap_cnt_reg[2] ; output \pi_rdval_cnt_reg[1]_0 ; output \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ; output \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ; output \pi_stg2_reg_l_timing_reg[0]_0 ; output [0:0]\regl_dqs_cnt_r_reg[2]_0 ; output \regl_dqs_cnt_reg[0]_0 ; output mpr_rd_rise0_prev_r_reg_1; output [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ; output cal1_cnt_cpt_r1; output mpr_valid_r_reg_0; output \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ; output \gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ; output p_0_in16_in; output \gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ; output p_0_in13_in; output \gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ; output p_0_in10_in; output \gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ; output p_0_in7_in; output \gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ; output p_0_in4_in; output \gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ; output p_0_in1_in; output \gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ; output p_0_in; output \gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ; output pb_found_stable_eye_r76_out; output \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ; output pb_found_stable_eye_r72_out; output \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ; output pb_found_stable_eye_r68_out; output \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ; output pb_found_stable_eye_r64_out; output \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ; output pb_found_stable_eye_r60_out; output \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ; output pb_found_stable_eye_r56_out; output \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ; output pb_found_stable_eye_r52_out; output \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ; output \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ; output \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ; output \right_edge_taps_r_reg[0]_2 ; output idel_adj_inc_reg_2; output pi_cnt_dec_reg_0; output \init_state_r_reg[1] ; output prech_req; output \init_state_r_reg[2] ; output \init_state_r_reg[2]_0 ; output \init_state_r_reg[2]_1 ; output \init_state_r_reg[5] ; output \init_state_r_reg[0]_2 ; output \init_state_r_reg[3] ; output \init_state_r_reg[0]_3 ; output \init_state_r_reg[4] ; output \init_state_r_reg[0]_4 ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ; output \init_state_r_reg[2]_2 ; output [1:0]D; output \gen_byte_sel_div1.calib_in_common_reg ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; output cmd_delay_start0; output \second_edge_taps_r_reg[5]_0 ; output [5:0]\pi_dqs_found_lanes_r1_reg[1]_2 ; output [5:0]\pi_dqs_found_lanes_r1_reg[2]_2 ; output [5:0]\pi_dqs_found_lanes_r1_reg[3]_2 ; output rdlvl_pi_incdec_reg_0; output [1:0]pi_stg2_rdlvl_cnt; output mpr_last_byte_done_reg_0; output mpr_rank_done_r_reg_0; output rdlvl_pi_incdec_reg_1; output \idel_dec_cnt_reg[0]_0 ; output rdlvl_stg1_done_int; output rdlvl_rank_done_r_reg_0; output mpr_rank_done_r_reg_1; output mpr_dec_cpt_r_reg_1; input CLK; input [1:0]rstdiv0_sync_r1_reg_rep__14; input sr_valid_r108_out; input \rd_mux_sel_r_reg[1]_0 ; input \rd_mux_sel_r_reg[1]_1 ; input \rd_mux_sel_r_reg[1]_2 ; input \rd_mux_sel_r_reg[1]_3 ; input \rd_mux_sel_r_reg[1]_4 ; input \rd_mux_sel_r_reg[1]_5 ; input \rd_mux_sel_r_reg[1]_6 ; input \rd_mux_sel_r_reg[1]_7 ; input \rd_mux_sel_r_reg[1]_8 ; input \rd_mux_sel_r_reg[1]_9 ; input \rd_mux_sel_r_reg[1]_10 ; input \rd_mux_sel_r_reg[1]_11 ; input \rd_mux_sel_r_reg[1]_12 ; input \rd_mux_sel_r_reg[1]_13 ; input \rd_mux_sel_r_reg[1]_14 ; input \rd_mux_sel_r_reg[1]_15 ; input \rd_mux_sel_r_reg[1]_16 ; input \rd_mux_sel_r_reg[1]_17 ; input \rd_mux_sel_r_reg[1]_18 ; input \rd_mux_sel_r_reg[1]_19 ; input \rd_mux_sel_r_reg[1]_20 ; input \rd_mux_sel_r_reg[1]_21 ; input \rd_mux_sel_r_reg[1]_22 ; input \rd_mux_sel_r_reg[1]_23 ; input \rd_mux_sel_r_reg[1]_24 ; input \rd_mux_sel_r_reg[1]_25 ; input \rd_mux_sel_r_reg[1]_26 ; input \rd_mux_sel_r_reg[1]_27 ; input \rd_mux_sel_r_reg[1]_28 ; input \rd_mux_sel_r_reg[1]_29 ; input \rd_mux_sel_r_reg[1]_30 ; input \rd_mux_sel_r_reg[1]_31 ; input \rd_mux_sel_r_reg[1]_32 ; input \rd_mux_sel_r_reg[1]_33 ; input \rd_mux_sel_r_reg[1]_34 ; input \rd_mux_sel_r_reg[1]_35 ; input \rd_mux_sel_r_reg[1]_36 ; input \rd_mux_sel_r_reg[1]_37 ; input \rd_mux_sel_r_reg[1]_38 ; input \rd_mux_sel_r_reg[1]_39 ; input \rd_mux_sel_r_reg[1]_40 ; input \rd_mux_sel_r_reg[1]_41 ; input \rd_mux_sel_r_reg[1]_42 ; input \rd_mux_sel_r_reg[1]_43 ; input \rd_mux_sel_r_reg[1]_44 ; input \rd_mux_sel_r_reg[1]_45 ; input \rd_mux_sel_r_reg[1]_46 ; input \rd_mux_sel_r_reg[1]_47 ; input \rd_mux_sel_r_reg[1]_48 ; input \rd_mux_sel_r_reg[1]_49 ; input \rd_mux_sel_r_reg[1]_50 ; input \rd_mux_sel_r_reg[1]_51 ; input \rd_mux_sel_r_reg[1]_52 ; input \rd_mux_sel_r_reg[1]_53 ; input \rd_mux_sel_r_reg[1]_54 ; input \rd_mux_sel_r_reg[1]_55 ; input \rd_mux_sel_r_reg[1]_56 ; input \rd_mux_sel_r_reg[1]_57 ; input \rd_mux_sel_r_reg[1]_58 ; input \rd_mux_sel_r_reg[1]_59 ; input \rd_mux_sel_r_reg[1]_60 ; input \rd_mux_sel_r_reg[1]_61 ; input \rd_mux_sel_r_reg[1]_62 ; input \rd_mux_sel_r_reg[1]_63 ; input mpr_rdlvl_start_reg; input rdlvl_stg1_start_reg; input phy_rddata_en_1; input rstdiv0_sync_r1_reg_rep__13; input dqs_po_dec_done; input samp_cnt_done_r_reg_0; input samp_cnt_done_r_reg_1; input samp_cnt_done_r_reg_2; input samp_cnt_done_r_reg_3; input samp_cnt_done_r_reg_4; input samp_cnt_done_r_reg_5; input samp_cnt_done_r_reg_6; input \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ; input mpr_rdlvl_done_r_reg_0; input store_sr_req_r_reg_1; input \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ; input \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ; input \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ; input \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ; input \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ; input \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ; input \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ; input \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ; input \gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ; input \gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ; input \gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ; input \gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ; input \gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ; input \gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ; input \gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ; input \gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ; input found_edge_r_reg_4; input found_stable_eye_r_reg_0; input \FSM_sequential_cal1_state_r_reg[4]_0 ; input \FSM_sequential_cal1_state_r_reg[3]_0 ; input \FSM_sequential_cal1_state_r_reg[2]_0 ; input \wait_cnt_r_reg[0]_1 ; input \FSM_sequential_cal1_state_r_reg[4]_1 ; input \FSM_sequential_cal1_state_r_reg[4]_2 ; input mpr_rdlvl_done_r_reg_1; input \FSM_sequential_cal1_state_r_reg[4]_3 ; input \FSM_sequential_cal1_state_r_reg[4]_4 ; input \regl_dqs_cnt_reg[2]_0 ; input \FSM_sequential_cal1_state_r_reg[1]_0 ; input [0:0]SR; input found_stable_eye_last_r_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input prbs_pi_stg2_f_incdec; input tempmon_pi_f_inc_r; input [0:0]Q; input prbs_pi_stg2_f_en; input tempmon_pi_f_en_r; input calib_in_common; input [2:0]\calib_sel_reg[3] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input rstdiv0_sync_r1_reg_rep__23; input stg1_wr_done; input wrcal_done_reg; input dqs_found_done_r_reg; input [1:0]\init_state_r_reg[1]_0 ; input oclkdelay_calib_done_r_reg; input \one_rank.stg1_wr_done_reg ; input cal1_state_r1535_out; input rstdiv0_sync_r1_reg_rep__22; input [2:0]\calib_sel_reg[3]_0 ; input \po_stg2_wrcal_cnt_reg[0] ; input [0:0]\po_stg2_wrcal_cnt_reg[1] ; input cal1_dq_idel_ce_reg_0; input prech_done; input [4:0]\pi_counter_read_val_reg[5] ; input rstdiv0_sync_r1_reg_rep__20; input \init_state_r_reg[3]_0 ; input wrcal_prech_req; input complex_ocal_ref_req; input prbs_rdlvl_prech_req_reg; input dqs_found_prech_req; input \init_state_r_reg[5]_0 ; input wrlvl_done_r1_reg; input wrlvl_done_r1_reg_0; input cnt_init_af_done_r; input dqs_found_done_r_reg_0; input prbs_rdlvl_done_reg_rep; input wrlvl_byte_redo; input wrlvl_final_mux; input mem_init_done_r; input prbs_rdlvl_done_reg_rep_0; input \num_refresh_reg[1] ; input prbs_last_byte_done_r; input wrlvl_final_mux_reg; input prbs_rdlvl_done_reg_rep_1; input oclkdelay_center_calib_done_r_reg; input wrlvl_done_r1; input wrlvl_byte_redo_reg; input \dout_o_reg[6] ; input first_wrcal_pat_r; input \dout_o_reg[6]_0 ; input prbs_rdlvl_done_reg; input wr_level_done_reg; input \prbs_dqs_cnt_r_reg[2] ; input \po_stg2_wrcal_cnt_reg[2] ; input [0:0]rdlvl_stg1_start_reg_0; input [0:0]E; input samp_edge_cnt0_en_r_reg_0; input [0:0]pi_cnt_dec_reg_1; input rstdiv0_sync_r1_reg_rep__2; wire CLK; wire [5:0]COUNTERLOADVAL; wire [1:0]D; wire [0:0]E; wire \FSM_sequential_cal1_state_r[0]_i_11_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_12_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_14_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_8_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_9_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_10_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_11_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_12_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_13_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_8_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_9_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[3]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[3]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[3]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_11_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_8_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_9_n_0 ; wire \FSM_sequential_cal1_state_r_reg[1]_0 ; wire \FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r_reg[2]_0 ; wire \FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r_reg[3]_0 ; wire \FSM_sequential_cal1_state_r_reg[4]_0 ; wire \FSM_sequential_cal1_state_r_reg[4]_1 ; wire \FSM_sequential_cal1_state_r_reg[4]_2 ; wire \FSM_sequential_cal1_state_r_reg[4]_3 ; wire \FSM_sequential_cal1_state_r_reg[4]_4 ; wire [0:0]Q; wire [0:0]SR; wire cal1_cnt_cpt_r1; wire \cal1_cnt_cpt_r[0]_i_1_n_0 ; wire \cal1_cnt_cpt_r[1]_i_2_n_0 ; wire \cal1_cnt_cpt_r[1]_i_3_n_0 ; wire \cal1_cnt_cpt_r[1]_i_4_n_0 ; wire \cal1_cnt_cpt_r[1]_i_5_n_0 ; wire \cal1_cnt_cpt_r_reg_n_0_[0] ; wire \cal1_cnt_cpt_r_reg_n_0_[1] ; wire cal1_dlyce_cpt_r; wire cal1_dlyce_cpt_r_i_2_n_0; wire cal1_dlyce_cpt_r_reg_n_0; wire cal1_dlyinc_cpt_r; wire cal1_dlyinc_cpt_r_i_2_n_0; wire cal1_dlyinc_cpt_r_reg_n_0; wire cal1_dq_idel_ce; wire cal1_dq_idel_ce_reg_0; wire cal1_dq_idel_inc; wire cal1_prech_req_r; wire cal1_prech_req_r_reg_n_0; (* RTL_KEEP = "yes" *) wire [5:5]cal1_state_r; wire cal1_state_r1; wire cal1_state_r1533_out; wire cal1_state_r1535_out; wire \cal1_state_r1[0]_i_1_n_0 ; wire \cal1_state_r1[1]_i_1_n_0 ; wire \cal1_state_r1[2]_i_1_n_0 ; wire \cal1_state_r1[3]_i_1_n_0 ; wire \cal1_state_r1[4]_i_1_n_0 ; wire \cal1_state_r1[5]_i_1_n_0 ; wire \cal1_state_r1_reg_n_0_[0] ; wire \cal1_state_r1_reg_n_0_[1] ; wire \cal1_state_r1_reg_n_0_[2] ; wire \cal1_state_r1_reg_n_0_[3] ; wire \cal1_state_r1_reg_n_0_[4] ; wire \cal1_state_r1_reg_n_0_[5] ; wire cal1_state_r2; wire cal1_wait_cnt_en_r; wire cal1_wait_cnt_en_r0; wire \cal1_wait_cnt_r[4]_i_1_n_0 ; wire [4:0]cal1_wait_cnt_r_reg__0; wire cal1_wait_r; wire cal1_wait_r_i_1_n_0; wire calib_in_common; wire [2:0]\calib_sel_reg[3] ; wire [2:0]\calib_sel_reg[3]_0 ; wire cmd_delay_start0; wire [5:0]cnt_idel_dec_cpt_r; wire [5:1]cnt_idel_dec_cpt_r2; wire \cnt_idel_dec_cpt_r[0]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r[0]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_10_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_11_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_12_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_13_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_14_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_6_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_7_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_8_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_7_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_8_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_9_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_10_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_11_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_12_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_13_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_1_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_6_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_7_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_8_n_0 ; wire \cnt_idel_dec_cpt_r_reg[0]_0 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ; wire \cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ; wire \cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 ; wire \cnt_idel_dec_cpt_r_reg_n_0_[0] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[1] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[2] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[3] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[4] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[5] ; wire cnt_init_af_done_r; wire [3:0]cnt_shift_r_reg__0; wire complex_ocal_ref_req; wire detect_edge_done_r; wire detect_edge_done_r_i_1_n_0; wire detect_edge_done_r_i_2_n_0; wire [3:0]done_cnt; wire done_cnt1; wire \done_cnt[0]_i_1_n_0 ; wire \done_cnt[1]_i_1_n_0 ; wire \done_cnt[2]_i_1_n_0 ; wire \done_cnt[3]_i_1_n_0 ; wire \done_cnt[3]_i_3_n_0 ; wire \done_cnt[3]_i_4_n_0 ; wire \dout_o_reg[6] ; wire \dout_o_reg[6]_0 ; wire dqs_found_done_r_reg; wire dqs_found_done_r_reg_0; wire dqs_found_prech_req; wire dqs_po_dec_done; wire dqs_po_dec_done_r1; wire dqs_po_dec_done_r2; wire fine_dly_dec_done_r1; wire fine_dly_dec_done_r1_i_1_n_0; wire fine_dly_dec_done_r1_i_2_n_0; wire fine_dly_dec_done_r1_i_3_n_0; wire fine_dly_dec_done_r2; wire \first_edge_taps_r[5]_i_1_n_0 ; wire \first_edge_taps_r[5]_i_2_n_0 ; wire \first_edge_taps_r_reg_n_0_[0] ; wire \first_edge_taps_r_reg_n_0_[1] ; wire \first_edge_taps_r_reg_n_0_[2] ; wire \first_edge_taps_r_reg_n_0_[3] ; wire \first_edge_taps_r_reg_n_0_[4] ; wire \first_edge_taps_r_reg_n_0_[5] ; wire first_wrcal_pat_r; wire found_edge_r_i_1_n_0; wire found_edge_r_i_2_n_0; wire found_edge_r_reg_0; wire found_edge_r_reg_1; wire found_edge_r_reg_2; wire found_edge_r_reg_3; wire found_edge_r_reg_4; wire found_first_edge_r_reg_0; wire found_stable_eye_last_r; wire found_stable_eye_last_r_reg_0; wire found_stable_eye_last_r_reg_1; wire found_stable_eye_r_i_1_n_0; wire found_stable_eye_r_i_2_n_0; wire found_stable_eye_r_reg_0; wire \gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ; wire \gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ; wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 ; wire \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ; wire \gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ; wire \gen_track_left_edge[0].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 ; wire \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ; wire \gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ; wire \gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ; wire \gen_track_left_edge[1].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ; wire \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 ; wire \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ; wire \gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ; wire \gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ; wire \gen_track_left_edge[2].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ; wire \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 ; wire \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ; wire \gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ; wire \gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ; wire \gen_track_left_edge[3].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ; wire \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 ; wire \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ; wire \gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ; wire \gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ; wire \gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ; wire \gen_track_left_edge[4].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ; wire \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 ; wire \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ; wire \gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ; wire \gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ; wire \gen_track_left_edge[5].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ; wire \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 ; wire \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ; wire \gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ; wire \gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ; wire \gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ; wire \gen_track_left_edge[6].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ; wire \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 ; wire \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ; wire \gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ; wire \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ; wire idel_adj_inc_reg_0; wire idel_adj_inc_reg_1; wire idel_adj_inc_reg_2; wire [0:0]idel_dec_cnt; wire \idel_dec_cnt[0]_i_2_n_0 ; wire \idel_dec_cnt[1]_i_1_n_0 ; wire \idel_dec_cnt[2]_i_1_n_0 ; wire \idel_dec_cnt[3]_i_1_n_0 ; wire \idel_dec_cnt[3]_i_2_n_0 ; wire \idel_dec_cnt[4]_i_1_n_0 ; wire \idel_dec_cnt[4]_i_2_n_0 ; wire \idel_dec_cnt[4]_i_4_n_0 ; wire \idel_dec_cnt[4]_i_5_n_0 ; wire \idel_dec_cnt[4]_i_7_n_0 ; wire \idel_dec_cnt[4]_i_8_n_0 ; wire \idel_dec_cnt[4]_i_9_n_0 ; wire [4:0]idel_dec_cnt__0; wire \idel_dec_cnt_reg[0]_0 ; wire idel_mpr_pat_detect_r; wire idel_pat0_data_match_r0__0; wire idel_pat0_match_fall0_and_r; wire idel_pat0_match_fall1_and_r; wire idel_pat0_match_fall2_and_r; wire idel_pat0_match_fall3_and_r; wire idel_pat0_match_rise0_and_r; wire idel_pat0_match_rise1_and_r; wire idel_pat0_match_rise2_and_r; wire idel_pat0_match_rise3_and_r; wire idel_pat1_data_match_r0__0; wire idel_pat1_match_fall0_and_r; wire idel_pat1_match_fall1_and_r; wire idel_pat1_match_fall2_and_r; wire idel_pat1_match_fall3_and_r; wire idel_pat1_match_rise0_and_r; wire idel_pat1_match_rise1_and_r; wire idel_pat1_match_rise2_and_r; wire idel_pat1_match_rise3_and_r; wire idelay_ce_int; wire idelay_inc_int; wire [4:0]idelay_tap_cnt_r; wire \idelay_tap_cnt_r[0][0][0]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][1]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][2]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][3]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][3]_i_2_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_2_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_4_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_5_n_0 ; wire \idelay_tap_cnt_r[0][1][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][2][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][3][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][3][4]_i_2_n_0 ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][4] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][4] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][4] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][4] ; wire [4:0]idelay_tap_cnt_slice_r; wire idelay_tap_limit_r_i_1_n_0; wire idelay_tap_limit_r_i_2_n_0; wire idelay_tap_limit_r_reg_n_0; wire inhibit_edge_detect_r; wire inhibit_edge_detect_r0; wire \init_state_r[0]_i_48_n_0 ; wire \init_state_r[0]_i_49_n_0 ; wire \init_state_r[0]_i_53_n_0 ; wire \init_state_r[0]_i_54_n_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[0]_2 ; wire \init_state_r_reg[0]_3 ; wire \init_state_r_reg[0]_4 ; wire \init_state_r_reg[1] ; wire [1:0]\init_state_r_reg[1]_0 ; wire \init_state_r_reg[2] ; wire \init_state_r_reg[2]_0 ; wire \init_state_r_reg[2]_1 ; wire \init_state_r_reg[2]_2 ; wire \init_state_r_reg[3] ; wire \init_state_r_reg[3]_0 ; wire \init_state_r_reg[4] ; wire \init_state_r_reg[5] ; wire \init_state_r_reg[5]_0 ; wire mem_init_done_r; wire \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ; wire \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ; wire \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ; wire \mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ; wire \mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ; wire \mpr_4to1.stable_idel_cnt_reg_n_0_[0] ; wire \mpr_4to1.stable_idel_cnt_reg_n_0_[1] ; wire \mpr_4to1.stable_idel_cnt_reg_n_0_[2] ; wire mpr_dec_cpt_r_reg_0; wire mpr_dec_cpt_r_reg_1; wire mpr_last_byte_done; wire mpr_last_byte_done_reg_0; wire mpr_rank_done_r_reg_0; wire mpr_rank_done_r_reg_1; wire mpr_rd_fall0_prev_r; wire mpr_rd_fall1_prev_r; wire mpr_rd_fall2_prev_r; wire mpr_rd_fall3_prev_r; wire mpr_rd_rise0_prev_r; wire mpr_rd_rise0_prev_r0; wire mpr_rd_rise0_prev_r_reg_0; wire mpr_rd_rise0_prev_r_reg_1; wire mpr_rd_rise1_prev_r; wire mpr_rd_rise2_prev_r; wire mpr_rd_rise3_prev_r; wire mpr_rdlvl_done_r1; wire mpr_rdlvl_done_r1_reg_0; wire mpr_rdlvl_done_r2; wire mpr_rdlvl_done_r_reg_0; wire mpr_rdlvl_done_r_reg_1; wire mpr_rdlvl_start_r; wire mpr_rdlvl_start_reg; wire mpr_rnk_done; wire mpr_valid_r; wire mpr_valid_r1; wire mpr_valid_r1_reg_0; wire mpr_valid_r2; wire mpr_valid_r_reg_0; wire new_cnt_cpt_r; wire new_cnt_cpt_r82_out; wire new_cnt_cpt_r_i_2_n_0; wire new_cnt_cpt_r_reg_n_0; wire \num_refresh_reg[1] ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_center_calib_done_r_reg; wire \one_rank.stg1_wr_done_reg ; (* RTL_KEEP = "yes" *) wire [4:0]out; wire p_0_in; wire p_0_in102_in; wire p_0_in10_in; wire p_0_in134_in; wire p_0_in13_in; wire p_0_in155_in; wire p_0_in16_in; wire p_0_in180_in; wire p_0_in1_in; wire p_0_in205_in; wire p_0_in230_in; wire p_0_in255_in; wire p_0_in280_in; wire p_0_in305_in; wire p_0_in330_in; wire p_0_in355_in; wire p_0_in380_in; wire p_0_in405_in; wire p_0_in430_in; wire p_0_in455_in; wire p_0_in4_in; wire p_0_in539_in; wire p_0_in7_in; wire p_0_in84_in; wire p_0_in87_in; wire p_0_in90_in; wire p_0_in93_in; wire p_0_in96_in; wire p_0_in99_in; wire [5:2]p_0_in__0; wire [4:0]p_0_in__0__0; wire [3:0]p_0_in__1; wire [4:0]p_0_in__2; wire [4:0]p_0_in__3; wire [4:0]p_0_in__4; wire [4:0]p_0_in__5; wire [4:0]p_0_in__6; wire [4:0]p_0_in__7; wire [4:0]p_0_in__8; wire [4:0]p_0_in__9; wire p_137_out__0; wire p_163_out__0; wire p_188_out__0; wire p_1_in11_in; wire p_1_in14_in; wire p_1_in162_in; wire p_1_in17_in; wire p_1_in187_in; wire p_1_in212_in; wire p_1_in237_in; wire p_1_in262_in; wire p_1_in26_in; wire p_1_in287_in; wire p_1_in2_in; wire p_1_in312_in; wire p_1_in337_in; wire p_1_in362_in; wire p_1_in387_in; wire p_1_in412_in; wire p_1_in437_in; wire p_1_in462_in; wire p_1_in5_in; wire p_1_in8_in; wire p_213_out__0; wire p_238_out__0; wire p_263_out__0; wire p_288_out__0; wire p_2_in156_in; wire p_2_in181_in; wire p_2_in206_in; wire p_2_in231_in; wire p_2_in256_in; wire p_2_in281_in; wire p_2_in306_in; wire p_2_in331_in; wire p_2_in356_in; wire p_2_in381_in; wire p_2_in406_in; wire p_2_in431_in; wire p_2_in456_in; wire p_313_out__0; wire p_338_out__0; wire p_363_out__0; wire p_388_out__0; wire p_3_in135_in; wire p_3_in157_in; wire p_3_in182_in; wire p_3_in207_in; wire p_3_in232_in; wire p_3_in257_in; wire p_3_in282_in; wire p_3_in307_in; wire p_3_in332_in; wire p_3_in357_in; wire p_3_in382_in; wire p_3_in407_in; wire p_3_in432_in; wire p_3_in457_in; wire p_413_out__0; wire p_438_out__0; wire p_463_out__0; wire p_488_out__0; wire p_4_in158_in; wire p_4_in183_in; wire p_4_in208_in; wire p_4_in233_in; wire p_4_in258_in; wire p_4_in283_in; wire p_4_in308_in; wire p_4_in333_in; wire p_4_in358_in; wire p_4_in383_in; wire p_4_in408_in; wire p_4_in433_in; wire p_4_in458_in; wire p_513_out__0; wire p_5_in136_in; wire p_5_in159_in; wire p_5_in184_in; wire p_5_in209_in; wire p_5_in234_in; wire p_5_in259_in; wire p_5_in284_in; wire p_5_in309_in; wire p_5_in334_in; wire p_5_in359_in; wire p_5_in384_in; wire p_5_in409_in; wire p_5_in434_in; wire p_5_in459_in; wire p_6_in160_in; wire p_6_in185_in; wire p_6_in210_in; wire p_6_in235_in; wire p_6_in260_in; wire p_6_in285_in; wire p_6_in310_in; wire p_6_in335_in; wire p_6_in360_in; wire p_6_in385_in; wire p_6_in410_in; wire p_6_in435_in; wire p_6_in460_in; wire p_7_in; wire p_7_in161_in; wire p_7_in186_in; wire p_7_in211_in; wire p_7_in236_in; wire p_7_in261_in; wire p_7_in286_in; wire p_7_in311_in; wire p_7_in336_in; wire p_7_in361_in; wire p_7_in386_in; wire p_7_in411_in; wire p_7_in436_in; wire p_7_in461_in; wire pat0_data_match_r0__0; wire pat0_match_fall0_and_r; wire pat0_match_fall1_and_r; wire pat0_match_fall2_and_r; wire pat0_match_fall3_and_r; wire pat0_match_rise0_and_r; wire pat0_match_rise1_and_r; wire pat0_match_rise2_and_r; wire pat0_match_rise3_and_r; wire pat1_data_match_r0__0; wire pat1_match_fall0_and_r; wire pat1_match_fall1_and_r; wire pat1_match_fall2_and_r; wire pat1_match_fall3_and_r; wire pat1_match_rise0_and_r; wire pat1_match_rise1_and_r; wire pat1_match_rise2_and_r; wire pat1_match_rise3_and_r; wire pb_cnt_eye_size_r; wire pb_detect_edge; wire [7:0]pb_detect_edge_done_r; wire pb_detect_edge_setup; wire pb_found_stable_eye_r52_out; wire pb_found_stable_eye_r56_out; wire pb_found_stable_eye_r60_out; wire pb_found_stable_eye_r64_out; wire pb_found_stable_eye_r68_out; wire pb_found_stable_eye_r72_out; wire pb_found_stable_eye_r76_out; wire phy_rddata_en_1; wire pi_cnt_dec_reg_0; wire [0:0]pi_cnt_dec_reg_1; wire pi_counter_load_en; wire [5:0]pi_counter_load_val; wire [4:0]\pi_counter_read_val_reg[5] ; wire \pi_dqs_found_lanes_r1_reg[0] ; wire \pi_dqs_found_lanes_r1_reg[0]_0 ; wire \pi_dqs_found_lanes_r1_reg[0]_1 ; wire \pi_dqs_found_lanes_r1_reg[1] ; wire \pi_dqs_found_lanes_r1_reg[1]_0 ; wire \pi_dqs_found_lanes_r1_reg[1]_1 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_2 ; wire \pi_dqs_found_lanes_r1_reg[2] ; wire \pi_dqs_found_lanes_r1_reg[2]_0 ; wire \pi_dqs_found_lanes_r1_reg[2]_1 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_2 ; wire \pi_dqs_found_lanes_r1_reg[3] ; wire \pi_dqs_found_lanes_r1_reg[3]_0 ; wire \pi_dqs_found_lanes_r1_reg[3]_1 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_2 ; wire pi_en_stg2_f_timing; wire pi_en_stg2_f_timing_i_1_n_0; wire pi_en_stg2_f_timing_reg_0; wire pi_fine_dly_dec_done; wire [5:0]pi_rdval_cnt; wire \pi_rdval_cnt[0]_i_1_n_0 ; wire \pi_rdval_cnt[1]_i_1_n_0 ; wire \pi_rdval_cnt[2]_i_1_n_0 ; wire \pi_rdval_cnt[3]_i_1_n_0 ; wire \pi_rdval_cnt[3]_i_2_n_0 ; wire \pi_rdval_cnt[4]_i_1_n_0 ; wire \pi_rdval_cnt[4]_i_2_n_0 ; wire \pi_rdval_cnt[5]_i_1_n_0 ; wire \pi_rdval_cnt[5]_i_2_n_0 ; wire \pi_rdval_cnt[5]_i_4_n_0 ; wire \pi_rdval_cnt[5]_i_5_n_0 ; wire \pi_rdval_cnt_reg[1]_0 ; wire pi_stg2_f_incdec_timing; wire pi_stg2_f_incdec_timing0; wire pi_stg2_load_timing; wire [1:0]pi_stg2_rdlvl_cnt; wire [5:0]pi_stg2_reg_l_timing; wire \pi_stg2_reg_l_timing[0]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[1]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[2]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[3]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[4]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[5]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[5]_i_2_n_0 ; wire \pi_stg2_reg_l_timing_reg[0]_0 ; wire \po_stg2_wrcal_cnt_reg[0] ; wire [0:0]\po_stg2_wrcal_cnt_reg[1] ; wire \po_stg2_wrcal_cnt_reg[2] ; wire \prbs_dqs_cnt_r_reg[2] ; wire prbs_last_byte_done_r; wire prbs_pi_stg2_f_en; wire prbs_pi_stg2_f_incdec; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prbs_rdlvl_done_reg_rep_0; wire prbs_rdlvl_done_reg_rep_1; wire prbs_rdlvl_prech_req_reg; wire prech_done; wire prech_req; wire \rd_mux_sel_r_reg[1]_0 ; wire \rd_mux_sel_r_reg[1]_1 ; wire \rd_mux_sel_r_reg[1]_10 ; wire \rd_mux_sel_r_reg[1]_11 ; wire \rd_mux_sel_r_reg[1]_12 ; wire \rd_mux_sel_r_reg[1]_13 ; wire \rd_mux_sel_r_reg[1]_14 ; wire \rd_mux_sel_r_reg[1]_15 ; wire \rd_mux_sel_r_reg[1]_16 ; wire \rd_mux_sel_r_reg[1]_17 ; wire \rd_mux_sel_r_reg[1]_18 ; wire \rd_mux_sel_r_reg[1]_19 ; wire \rd_mux_sel_r_reg[1]_2 ; wire \rd_mux_sel_r_reg[1]_20 ; wire \rd_mux_sel_r_reg[1]_21 ; wire \rd_mux_sel_r_reg[1]_22 ; wire \rd_mux_sel_r_reg[1]_23 ; wire \rd_mux_sel_r_reg[1]_24 ; wire \rd_mux_sel_r_reg[1]_25 ; wire \rd_mux_sel_r_reg[1]_26 ; wire \rd_mux_sel_r_reg[1]_27 ; wire \rd_mux_sel_r_reg[1]_28 ; wire \rd_mux_sel_r_reg[1]_29 ; wire \rd_mux_sel_r_reg[1]_3 ; wire \rd_mux_sel_r_reg[1]_30 ; wire \rd_mux_sel_r_reg[1]_31 ; wire \rd_mux_sel_r_reg[1]_32 ; wire \rd_mux_sel_r_reg[1]_33 ; wire \rd_mux_sel_r_reg[1]_34 ; wire \rd_mux_sel_r_reg[1]_35 ; wire \rd_mux_sel_r_reg[1]_36 ; wire \rd_mux_sel_r_reg[1]_37 ; wire \rd_mux_sel_r_reg[1]_38 ; wire \rd_mux_sel_r_reg[1]_39 ; wire \rd_mux_sel_r_reg[1]_4 ; wire \rd_mux_sel_r_reg[1]_40 ; wire \rd_mux_sel_r_reg[1]_41 ; wire \rd_mux_sel_r_reg[1]_42 ; wire \rd_mux_sel_r_reg[1]_43 ; wire \rd_mux_sel_r_reg[1]_44 ; wire \rd_mux_sel_r_reg[1]_45 ; wire \rd_mux_sel_r_reg[1]_46 ; wire \rd_mux_sel_r_reg[1]_47 ; wire \rd_mux_sel_r_reg[1]_48 ; wire \rd_mux_sel_r_reg[1]_49 ; wire \rd_mux_sel_r_reg[1]_5 ; wire \rd_mux_sel_r_reg[1]_50 ; wire \rd_mux_sel_r_reg[1]_51 ; wire \rd_mux_sel_r_reg[1]_52 ; wire \rd_mux_sel_r_reg[1]_53 ; wire \rd_mux_sel_r_reg[1]_54 ; wire \rd_mux_sel_r_reg[1]_55 ; wire \rd_mux_sel_r_reg[1]_56 ; wire \rd_mux_sel_r_reg[1]_57 ; wire \rd_mux_sel_r_reg[1]_58 ; wire \rd_mux_sel_r_reg[1]_59 ; wire \rd_mux_sel_r_reg[1]_6 ; wire \rd_mux_sel_r_reg[1]_60 ; wire \rd_mux_sel_r_reg[1]_61 ; wire \rd_mux_sel_r_reg[1]_62 ; wire \rd_mux_sel_r_reg[1]_63 ; wire \rd_mux_sel_r_reg[1]_7 ; wire \rd_mux_sel_r_reg[1]_8 ; wire \rd_mux_sel_r_reg[1]_9 ; wire \rdlvl_cpt_tap_cnt_reg[1] ; wire \rdlvl_cpt_tap_cnt_reg[2] ; wire \rdlvl_cpt_tap_cnt_reg[4] ; wire rdlvl_dqs_tap_cnt_r; wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ; wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ; wire \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ; wire \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ; wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ; wire rdlvl_last_byte_done; wire rdlvl_pi_incdec; wire rdlvl_pi_incdec_i_4_n_0; wire rdlvl_pi_incdec_i_5_n_0; wire rdlvl_pi_incdec_i_6_n_0; wire rdlvl_pi_incdec_reg_0; wire rdlvl_pi_incdec_reg_1; wire rdlvl_pi_stg2_f_en; wire rdlvl_pi_stg2_f_incdec; wire rdlvl_prech_req; wire rdlvl_rank_done_r_reg_0; wire rdlvl_stg1_done_int; wire rdlvl_stg1_done_r1_reg; wire rdlvl_stg1_rank_done; wire rdlvl_stg1_start_r; wire rdlvl_stg1_start_reg; wire [0:0]rdlvl_stg1_start_reg_0; wire [1:0]regl_dqs_cnt; wire \regl_dqs_cnt[0]_i_1_n_0 ; wire \regl_dqs_cnt[1]_i_1_n_0 ; wire \regl_dqs_cnt[1]_i_2_n_0 ; wire \regl_dqs_cnt[2]_i_1_n_0 ; wire [2:0]regl_dqs_cnt_r; wire [0:0]\regl_dqs_cnt_r_reg[2]_0 ; wire \regl_dqs_cnt_reg[0]_0 ; wire \regl_dqs_cnt_reg[2]_0 ; wire [1:0]regl_rank_cnt; wire \regl_rank_cnt[0]_i_1_n_0 ; wire \regl_rank_cnt[1]_i_1_n_0 ; wire \right_edge_taps_r[0]_i_1_n_0 ; wire \right_edge_taps_r[1]_i_1_n_0 ; wire \right_edge_taps_r[2]_i_1_n_0 ; wire \right_edge_taps_r[3]_i_1_n_0 ; wire \right_edge_taps_r[4]_i_1_n_0 ; wire \right_edge_taps_r[5]_i_1_n_0 ; wire \right_edge_taps_r[5]_i_2_n_0 ; wire [5:0]right_edge_taps_r__0; wire \right_edge_taps_r_reg[0]_0 ; wire \right_edge_taps_r_reg[0]_1 ; wire \right_edge_taps_r_reg[0]_2 ; wire \rnk_cnt_r[0]_i_1__0_n_0 ; wire \rnk_cnt_r[1]_i_1__0_n_0 ; wire \rnk_cnt_r[1]_i_2_n_0 ; wire \rnk_cnt_r[1]_i_3_n_0 ; wire \rnk_cnt_r_reg_n_0_[0] ; wire \rnk_cnt_r_reg_n_0_[1] ; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire samp_cnt_done_r_i_1_n_0; wire samp_cnt_done_r_i_2_n_0; wire samp_cnt_done_r_i_3_n_0; wire samp_cnt_done_r_i_4_n_0; wire samp_cnt_done_r_reg_0; wire samp_cnt_done_r_reg_1; wire samp_cnt_done_r_reg_2; wire samp_cnt_done_r_reg_3; wire samp_cnt_done_r_reg_4; wire samp_cnt_done_r_reg_5; wire samp_cnt_done_r_reg_6; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg_0; wire samp_edge_cnt0_r0; wire \samp_edge_cnt0_r[0]_i_4_n_0 ; wire \samp_edge_cnt0_r[0]_i_5_n_0 ; wire \samp_edge_cnt0_r[0]_i_6_n_0 ; wire \samp_edge_cnt0_r[0]_i_7_n_0 ; wire \samp_edge_cnt0_r[4]_i_2_n_0 ; wire \samp_edge_cnt0_r[4]_i_3_n_0 ; wire \samp_edge_cnt0_r[4]_i_4_n_0 ; wire \samp_edge_cnt0_r[4]_i_5_n_0 ; wire \samp_edge_cnt0_r[8]_i_2_n_0 ; wire \samp_edge_cnt0_r[8]_i_3_n_0 ; wire \samp_edge_cnt0_r[8]_i_4_n_0 ; wire \samp_edge_cnt0_r[8]_i_5_n_0 ; wire [11:0]samp_edge_cnt0_r_reg; wire \samp_edge_cnt0_r_reg[0]_i_3_n_0 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_1 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_2 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_3 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_4 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_5 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_6 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_7 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_0 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_1 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_2 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_3 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_4 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_5 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_6 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_7 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_1 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_2 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_3 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_4 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_5 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_6 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_7 ; wire samp_edge_cnt1_en_r; wire samp_edge_cnt1_en_r0; wire samp_edge_cnt1_en_r_i_2_n_0; wire samp_edge_cnt1_en_r_i_3_n_0; wire \samp_edge_cnt1_r[0]_i_2_n_0 ; wire \samp_edge_cnt1_r[0]_i_3_n_0 ; wire \samp_edge_cnt1_r[0]_i_4_n_0 ; wire \samp_edge_cnt1_r[0]_i_5_n_0 ; wire \samp_edge_cnt1_r[4]_i_2_n_0 ; wire \samp_edge_cnt1_r[4]_i_3_n_0 ; wire \samp_edge_cnt1_r[4]_i_4_n_0 ; wire \samp_edge_cnt1_r[4]_i_5_n_0 ; wire \samp_edge_cnt1_r[8]_i_2_n_0 ; wire \samp_edge_cnt1_r[8]_i_3_n_0 ; wire \samp_edge_cnt1_r[8]_i_4_n_0 ; wire \samp_edge_cnt1_r[8]_i_5_n_0 ; wire [11:0]samp_edge_cnt1_r_reg; wire \samp_edge_cnt1_r_reg[0]_i_1_n_0 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_1 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_2 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_3 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_4 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_5 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_6 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_7 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_0 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_1 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_2 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_3 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_4 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_5 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_6 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_7 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_1 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_2 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_3 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_4 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_5 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_6 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_7 ; wire \second_edge_taps_r[0]_i_1_n_0 ; wire \second_edge_taps_r[1]_i_1_n_0 ; wire \second_edge_taps_r[2]_i_1_n_0 ; wire \second_edge_taps_r[3]_i_1_n_0 ; wire \second_edge_taps_r[4]_i_1_n_0 ; wire \second_edge_taps_r[5]_i_1_n_0 ; wire \second_edge_taps_r[5]_i_3_n_0 ; wire \second_edge_taps_r_reg[5]_0 ; wire \second_edge_taps_r_reg_n_0_[0] ; wire \second_edge_taps_r_reg_n_0_[1] ; wire \second_edge_taps_r_reg_n_0_[2] ; wire \second_edge_taps_r_reg_n_0_[3] ; wire \second_edge_taps_r_reg_n_0_[4] ; wire \second_edge_taps_r_reg_n_0_[5] ; wire sr_valid_r1; wire sr_valid_r108_out; wire sr_valid_r1_reg_0; wire sr_valid_r2; wire stable_idel_cnt; wire stable_idel_cnt0; wire stable_idel_cnt22_in; wire stg1_wr_done; wire \stg1_wr_rd_cnt_reg[3] ; wire store_sr_r0; wire store_sr_r1; wire store_sr_r_reg_0; wire store_sr_req_pulsed_r; wire store_sr_req_pulsed_r_reg_n_0; wire store_sr_req_r; wire store_sr_req_r_i_2_n_0; wire store_sr_req_r_reg_0; wire store_sr_req_r_reg_1; wire tap_cnt_cpt_r; wire tap_cnt_cpt_r0; wire \tap_cnt_cpt_r[1]_i_1_n_0 ; wire \tap_cnt_cpt_r[5]_i_4_n_0 ; wire \tap_cnt_cpt_r_reg_n_0_[0] ; wire \tap_cnt_cpt_r_reg_n_0_[1] ; wire \tap_cnt_cpt_r_reg_n_0_[2] ; wire \tap_cnt_cpt_r_reg_n_0_[3] ; wire \tap_cnt_cpt_r_reg_n_0_[4] ; wire \tap_cnt_cpt_r_reg_n_0_[5] ; wire tap_limit_cpt_r; wire tap_limit_cpt_r_i_1_n_0; wire tap_limit_cpt_r_i_2_n_0; wire tap_limit_cpt_r_i_3_n_0; wire tempmon_pi_f_en_r; wire tempmon_pi_f_inc_r; wire wait_cnt_r0; wire [3:0]wait_cnt_r0__0; wire \wait_cnt_r[1]_i_1__1_n_0 ; wire [1:0]\wait_cnt_r_reg[0]_0 ; wire \wait_cnt_r_reg[0]_1 ; wire [3:2]wait_cnt_r_reg__0; wire wr_level_done_reg; wire wrcal_done_reg; wire wrcal_prech_req; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ; wire wrlvl_byte_redo; wire wrlvl_byte_redo_reg; wire wrlvl_done_r1; wire wrlvl_done_r1_reg; wire wrlvl_done_r1_reg_0; wire wrlvl_final_mux; wire wrlvl_final_mux_reg; wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED ; wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED ; wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED ; wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED ; wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED ; wire [3:3]\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED ; LUT6 #( .INIT(64'hFFFFFEAEAAAAFEAE)) \FSM_sequential_cal1_state_r[0]_i_1 (.I0(\FSM_sequential_cal1_state_r[0]_i_2_n_0 ), .I1(\FSM_sequential_cal1_state_r[0]_i_3_n_0 ), .I2(out[0]), .I3(\FSM_sequential_cal1_state_r[0]_i_4_n_0 ), .I4(out[1]), .I5(\FSM_sequential_cal1_state_r[0]_i_5_n_0 ), .O(\FSM_sequential_cal1_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000002000000)) \FSM_sequential_cal1_state_r[0]_i_10 (.I0(\done_cnt[3]_i_3_n_0 ), .I1(regl_rank_cnt[1]), .I2(regl_rank_cnt[0]), .I3(regl_dqs_cnt[0]), .I4(regl_dqs_cnt[1]), .I5(\regl_dqs_cnt_r_reg[2]_0 ), .O(cal1_state_r1)); LUT5 #( .INIT(32'hBFFFFF00)) \FSM_sequential_cal1_state_r[0]_i_11 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(out[0]), .I4(out[2]), .O(\FSM_sequential_cal1_state_r[0]_i_11_n_0 )); LUT6 #( .INIT(64'h0000150000000000)) \FSM_sequential_cal1_state_r[0]_i_12 (.I0(\FSM_sequential_cal1_state_r[0]_i_14_n_0 ), .I1(mpr_dec_cpt_r_reg_0), .I2(stable_idel_cnt22_in), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I5(out[2]), .O(\FSM_sequential_cal1_state_r[0]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_cal1_state_r[0]_i_13 (.I0(\right_edge_taps_r_reg[0]_0 ), .I1(found_stable_eye_last_r), .O(cal1_state_r1533_out)); (* SOFT_HLUTNM = "soft_lutpair204" *) LUT4 #( .INIT(16'hFFFE)) \FSM_sequential_cal1_state_r[0]_i_14 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .O(\FSM_sequential_cal1_state_r[0]_i_14_n_0 )); LUT6 #( .INIT(64'hBBBB88B888B8BBB8)) \FSM_sequential_cal1_state_r[0]_i_2 (.I0(\FSM_sequential_cal1_state_r[0]_i_6_n_0 ), .I1(\idel_dec_cnt_reg[0]_0 ), .I2(\FSM_sequential_cal1_state_r[0]_i_7_n_0 ), .I3(out[4]), .I4(out[2]), .I5(out[0]), .O(\FSM_sequential_cal1_state_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'h8988898889998988)) \FSM_sequential_cal1_state_r[0]_i_3 (.I0(out[2]), .I1(out[4]), .I2(mpr_rdlvl_done_r1_reg_0), .I3(cal1_state_r), .I4(mpr_rdlvl_start_reg), .I5(mpr_rdlvl_start_r), .O(\FSM_sequential_cal1_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'h1110101011111111)) \FSM_sequential_cal1_state_r[0]_i_4 (.I0(out[2]), .I1(cal1_state_r), .I2(out[3]), .I3(idelay_tap_limit_r_reg_n_0), .I4(\FSM_sequential_cal1_state_r[0]_i_8_n_0 ), .I5(out[4]), .O(\FSM_sequential_cal1_state_r[0]_i_4_n_0 )); LUT6 #( .INIT(64'hEEAFEEAAEEAFEEAF)) \FSM_sequential_cal1_state_r[0]_i_5 (.I0(\FSM_sequential_cal1_state_r[0]_i_9_n_0 ), .I1(cal1_state_r1), .I2(\FSM_sequential_cal1_state_r[0]_i_11_n_0 ), .I3(cal1_state_r), .I4(out[3]), .I5(store_sr_req_r_reg_0), .O(\FSM_sequential_cal1_state_r[0]_i_5_n_0 )); LUT5 #( .INIT(32'h11040004)) \FSM_sequential_cal1_state_r[0]_i_6 (.I0(out[2]), .I1(out[3]), .I2(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I3(out[0]), .I4(mpr_rdlvl_done_r1_reg_0), .O(\FSM_sequential_cal1_state_r[0]_i_6_n_0 )); LUT5 #( .INIT(32'hFFFFA800)) \FSM_sequential_cal1_state_r[0]_i_7 (.I0(mpr_rd_rise0_prev_r_reg_0), .I1(idelay_tap_limit_r_reg_n_0), .I2(idel_mpr_pat_detect_r), .I3(out[0]), .I4(\FSM_sequential_cal1_state_r[0]_i_12_n_0 ), .O(\FSM_sequential_cal1_state_r[0]_i_7_n_0 )); LUT2 #( .INIT(4'h1)) \FSM_sequential_cal1_state_r[0]_i_8 (.I0(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .O(\FSM_sequential_cal1_state_r[0]_i_8_n_0 )); LUT6 #( .INIT(64'h2220202000000000)) \FSM_sequential_cal1_state_r[0]_i_9 (.I0(out[0]), .I1(out[3]), .I2(tap_limit_cpt_r), .I3(found_first_edge_r_reg_0), .I4(cal1_state_r1533_out), .I5(out[4]), .O(\FSM_sequential_cal1_state_r[0]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF2EEE2222)) \FSM_sequential_cal1_state_r[1]_i_1 (.I0(\FSM_sequential_cal1_state_r[1]_i_2_n_0 ), .I1(out[0]), .I2(out[4]), .I3(\FSM_sequential_cal1_state_r[1]_i_3_n_0 ), .I4(\FSM_sequential_cal1_state_r[1]_i_4_n_0 ), .I5(\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ), .O(\FSM_sequential_cal1_state_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT4 #( .INIT(16'hFEFF)) \FSM_sequential_cal1_state_r[1]_i_10 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I3(mpr_dec_cpt_r_reg_0), .O(\FSM_sequential_cal1_state_r[1]_i_10_n_0 )); LUT4 #( .INIT(16'h4474)) \FSM_sequential_cal1_state_r[1]_i_11 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(cal1_state_r), .I2(mpr_rdlvl_start_reg), .I3(mpr_rdlvl_start_r), .O(\FSM_sequential_cal1_state_r[1]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT3 #( .INIT(8'h7F)) \FSM_sequential_cal1_state_r[1]_i_12 (.I0(found_stable_eye_last_r), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(found_first_edge_r_reg_0), .O(\FSM_sequential_cal1_state_r[1]_i_12_n_0 )); LUT2 #( .INIT(4'hE)) \FSM_sequential_cal1_state_r[1]_i_13 (.I0(out[3]), .I1(out[2]), .O(\FSM_sequential_cal1_state_r[1]_i_13_n_0 )); LUT6 #( .INIT(64'h0C0C0C0C88888088)) \FSM_sequential_cal1_state_r[1]_i_2 (.I0(out[4]), .I1(\FSM_sequential_cal1_state_r[1]_i_6_n_0 ), .I2(out[1]), .I3(mpr_dec_cpt_r_reg_0), .I4(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I5(out[2]), .O(\FSM_sequential_cal1_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hEF00FF00EFFFFF00)) \FSM_sequential_cal1_state_r[1]_i_3 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(cal1_cnt_cpt_r1), .I3(out[3]), .I4(mpr_rdlvl_done_r1_reg_0), .I5(idel_adj_inc_reg_0), .O(\FSM_sequential_cal1_state_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'h5500000055510055)) \FSM_sequential_cal1_state_r[1]_i_4 (.I0(cal1_state_r), .I1(mpr_rd_rise0_prev_r_reg_0), .I2(idel_mpr_pat_detect_r), .I3(out[2]), .I4(out[1]), .I5(out[4]), .O(\FSM_sequential_cal1_state_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \FSM_sequential_cal1_state_r[1]_i_6 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I1(out[4]), .I2(stable_idel_cnt22_in), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I5(\FSM_sequential_cal1_state_r[1]_i_10_n_0 ), .O(\FSM_sequential_cal1_state_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_cal1_state_r[1]_i_7 (.I0(\pi_rdval_cnt_reg[1]_0 ), .I1(idel_dec_cnt__0[2]), .I2(idel_dec_cnt__0[1]), .I3(idel_dec_cnt__0[0]), .I4(idel_dec_cnt__0[3]), .I5(idel_dec_cnt__0[4]), .O(\FSM_sequential_cal1_state_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'h0101010151515101)) \FSM_sequential_cal1_state_r[1]_i_8 (.I0(out[2]), .I1(\FSM_sequential_cal1_state_r[1]_i_11_n_0 ), .I2(out[4]), .I3(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .I4(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .I5(out[3]), .O(\FSM_sequential_cal1_state_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'h000000004040FF40)) \FSM_sequential_cal1_state_r[1]_i_9 (.I0(tap_limit_cpt_r), .I1(\FSM_sequential_cal1_state_r[1]_i_12_n_0 ), .I2(out[4]), .I3(cal1_state_r), .I4(cal1_state_r1), .I5(\FSM_sequential_cal1_state_r[1]_i_13_n_0 ), .O(\FSM_sequential_cal1_state_r[1]_i_9_n_0 )); LUT5 #( .INIT(32'hFFFF3404)) \FSM_sequential_cal1_state_r[2]_i_1 (.I0(out[4]), .I1(out[2]), .I2(out[0]), .I3(out[3]), .I4(\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ), .O(\FSM_sequential_cal1_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h8888AAA8AAAAAAAA)) \FSM_sequential_cal1_state_r[2]_i_3 (.I0(out[4]), .I1(out[0]), .I2(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I3(mpr_dec_cpt_r_reg_0), .I4(out[2]), .I5(out[3]), .O(\FSM_sequential_cal1_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'h00AB00AB03AB00AB)) \FSM_sequential_cal1_state_r[2]_i_4 (.I0(\FSM_sequential_cal1_state_r[2]_i_5_n_0 ), .I1(out[4]), .I2(cal1_state_r), .I3(out[0]), .I4(mpr_rd_rise0_prev_r_reg_0), .I5(idel_mpr_pat_detect_r), .O(\FSM_sequential_cal1_state_r[2]_i_4_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_sequential_cal1_state_r[2]_i_5 (.I0(out[2]), .I1(out[3]), .O(\FSM_sequential_cal1_state_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'h303030003008CC08)) \FSM_sequential_cal1_state_r[3]_i_1 (.I0(\FSM_sequential_cal1_state_r[3]_i_2_n_0 ), .I1(out[2]), .I2(out[4]), .I3(out[1]), .I4(out[3]), .I5(out[0]), .O(\FSM_sequential_cal1_state_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \FSM_sequential_cal1_state_r[3]_i_2 (.I0(mpr_dec_cpt_r_reg_0), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I5(\FSM_sequential_cal1_state_r[3]_i_3_n_0 ), .O(\FSM_sequential_cal1_state_r[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_cal1_state_r[3]_i_3 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\FSM_sequential_cal1_state_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'h0C0C0C8C)) \FSM_sequential_cal1_state_r[4]_i_1 (.I0(out[2]), .I1(\FSM_sequential_cal1_state_r[4]_i_2_n_0 ), .I2(\FSM_sequential_cal1_state_r[4]_i_3_n_0 ), .I3(\FSM_sequential_cal1_state_r[4]_i_4_n_0 ), .I4(out[0]), .O(\FSM_sequential_cal1_state_r[4]_i_1_n_0 )); LUT5 #( .INIT(32'hEFFFFFFF)) \FSM_sequential_cal1_state_r[4]_i_2 (.I0(idel_adj_inc_reg_0), .I1(mpr_rdlvl_done_r1_reg_0), .I2(out[0]), .I3(out[2]), .I4(out[1]), .O(\FSM_sequential_cal1_state_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h000000000000AFEF)) \FSM_sequential_cal1_state_r[4]_i_3 (.I0(out[3]), .I1(mpr_dec_cpt_r_reg_0), .I2(out[2]), .I3(out[0]), .I4(\FSM_sequential_cal1_state_r[4]_i_5_n_0 ), .I5(\FSM_sequential_cal1_state_r[4]_i_6_n_0 ), .O(\FSM_sequential_cal1_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'hA0A0A0A0A0A0A0A1)) \FSM_sequential_cal1_state_r[4]_i_4 (.I0(out[1]), .I1(\FSM_sequential_cal1_state_r[4]_i_7_n_0 ), .I2(out[3]), .I3(stable_idel_cnt22_in), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\FSM_sequential_cal1_state_r[4]_i_4_n_0 )); LUT6 #( .INIT(64'h1000101010101010)) \FSM_sequential_cal1_state_r[4]_i_5 (.I0(out[0]), .I1(out[1]), .I2(out[4]), .I3(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I4(out[3]), .I5(mpr_dec_cpt_r_reg_0), .O(\FSM_sequential_cal1_state_r[4]_i_5_n_0 )); LUT5 #( .INIT(32'h55404440)) \FSM_sequential_cal1_state_r[4]_i_6 (.I0(out[2]), .I1(out[1]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .O(\FSM_sequential_cal1_state_r[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair204" *) LUT4 #( .INIT(16'hFFFD)) \FSM_sequential_cal1_state_r[4]_i_7 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .O(\FSM_sequential_cal1_state_r[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT5 #( .INIT(32'hFFFEFFFF)) \FSM_sequential_cal1_state_r[4]_i_8 (.I0(idelay_tap_cnt_r[4]), .I1(idelay_tap_cnt_r[3]), .I2(idelay_tap_cnt_r[2]), .I3(idelay_tap_cnt_r[1]), .I4(\idel_dec_cnt[0]_i_2_n_0 ), .O(stable_idel_cnt22_in)); LUT6 #( .INIT(64'h101F101F101F1010)) \FSM_sequential_cal1_state_r[5]_i_1 (.I0(cal1_state_r), .I1(\FSM_sequential_cal1_state_r[5]_i_3_n_0 ), .I2(out[4]), .I3(out[3]), .I4(\FSM_sequential_cal1_state_r[5]_i_4_n_0 ), .I5(\FSM_sequential_cal1_state_r[5]_i_5_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h0FF00FF050005FC0)) \FSM_sequential_cal1_state_r[5]_i_11 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_valid_r1_reg_0), .I2(out[0]), .I3(cal1_state_r), .I4(cal1_wait_r), .I5(out[1]), .O(\FSM_sequential_cal1_state_r[5]_i_11_n_0 )); LUT6 #( .INIT(64'h00005400FC00FC00)) \FSM_sequential_cal1_state_r[5]_i_2 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(out[3]), .I2(cal1_state_r), .I3(\FSM_sequential_cal1_state_r[5]_i_6_n_0 ), .I4(\rnk_cnt_r_reg_n_0_[1] ), .I5(\FSM_sequential_cal1_state_r[5]_i_7_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0000B0B1FBF5B0B1)) \FSM_sequential_cal1_state_r[5]_i_3 (.I0(out[3]), .I1(out[2]), .I2(cal1_wait_r), .I3(out[1]), .I4(out[0]), .I5(\FSM_sequential_cal1_state_r[5]_i_8_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0007FFFF00070000)) \FSM_sequential_cal1_state_r[5]_i_4 (.I0(cal1_wait_r), .I1(out[0]), .I2(cal1_state_r), .I3(out[1]), .I4(out[2]), .I5(\FSM_sequential_cal1_state_r[5]_i_9_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000010111010)) \FSM_sequential_cal1_state_r[5]_i_5 (.I0(out[0]), .I1(cal1_state_r), .I2(cal1_state_r1535_out), .I3(rdlvl_stg1_start_r), .I4(rdlvl_stg1_start_reg), .I5(out[1]), .O(\FSM_sequential_cal1_state_r[5]_i_5_n_0 )); LUT5 #( .INIT(32'hC0FE00CC)) \FSM_sequential_cal1_state_r[5]_i_6 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(out[1]), .I2(out[2]), .I3(out[4]), .I4(out[0]), .O(\FSM_sequential_cal1_state_r[5]_i_6_n_0 )); LUT5 #( .INIT(32'h80000000)) \FSM_sequential_cal1_state_r[5]_i_7 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(out[1]), .I4(out[0]), .O(\FSM_sequential_cal1_state_r[5]_i_7_n_0 )); LUT5 #( .INIT(32'hC000EEEE)) \FSM_sequential_cal1_state_r[5]_i_8 (.I0(detect_edge_done_r), .I1(out[3]), .I2(out[1]), .I3(prech_done), .I4(out[2]), .O(\FSM_sequential_cal1_state_r[5]_i_8_n_0 )); LUT5 #( .INIT(32'hFFFF00D0)) \FSM_sequential_cal1_state_r[5]_i_9 (.I0(cal1_wait_r), .I1(store_sr_req_r_reg_0), .I2(out[1]), .I3(cal1_state_r), .I4(\FSM_sequential_cal1_state_r[5]_i_11_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_9_n_0 )); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_cal1_state_r_reg[0] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[0]_i_1_n_0 ), .Q(out[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_cal1_state_r_reg[1] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[1]_i_1_n_0 ), .Q(out[1]), .R(rstdiv0_sync_r1_reg_rep__2)); MUXF7 \FSM_sequential_cal1_state_r_reg[1]_i_5 (.I0(\FSM_sequential_cal1_state_r[1]_i_8_n_0 ), .I1(\FSM_sequential_cal1_state_r[1]_i_9_n_0 ), .O(\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ), .S(out[1])); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_cal1_state_r_reg[2] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[2]_i_1_n_0 ), .Q(out[2]), .R(rstdiv0_sync_r1_reg_rep__2)); MUXF7 \FSM_sequential_cal1_state_r_reg[2]_i_2 (.I0(\FSM_sequential_cal1_state_r[2]_i_3_n_0 ), .I1(\FSM_sequential_cal1_state_r[2]_i_4_n_0 ), .O(\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ), .S(out[1])); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_cal1_state_r_reg[3] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[3]_i_1_n_0 ), .Q(out[3]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_cal1_state_r_reg[4] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[4]_i_1_n_0 ), .Q(out[4]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_cal1_state_r_reg[5] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[5]_i_2_n_0 ), .Q(cal1_state_r), .R(rstdiv0_sync_r1_reg_rep__2)); LUT3 #( .INIT(8'h34)) \cal1_cnt_cpt_r[0]_i_1 (.I0(cal1_state_r), .I1(\cal1_cnt_cpt_r[1]_i_3_n_0 ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .O(\cal1_cnt_cpt_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h1F20)) \cal1_cnt_cpt_r[1]_i_2 (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I1(cal1_state_r), .I2(\cal1_cnt_cpt_r[1]_i_3_n_0 ), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .O(\cal1_cnt_cpt_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00800A0000000000)) \cal1_cnt_cpt_r[1]_i_3 (.I0(out[1]), .I1(\cal1_cnt_cpt_r[1]_i_4_n_0 ), .I2(out[3]), .I3(cal1_state_r), .I4(out[4]), .I5(\cal1_cnt_cpt_r[1]_i_5_n_0 ), .O(\cal1_cnt_cpt_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAA2AAAAAAAAA)) \cal1_cnt_cpt_r[1]_i_4 (.I0(prech_done), .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .I4(\rnk_cnt_r_reg_n_0_[1] ), .I5(mpr_rdlvl_done_r1_reg_0), .O(\cal1_cnt_cpt_r[1]_i_4_n_0 )); LUT3 #( .INIT(8'h81)) \cal1_cnt_cpt_r[1]_i_5 (.I0(out[0]), .I1(out[2]), .I2(out[3]), .O(\cal1_cnt_cpt_r[1]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \cal1_cnt_cpt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r[0]_i_1_n_0 ), .Q(\cal1_cnt_cpt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \cal1_cnt_cpt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r[1]_i_2_n_0 ), .Q(\cal1_cnt_cpt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0010000000003000)) cal1_dlyce_cpt_r_i_1 (.I0(tap_limit_cpt_r), .I1(cal1_state_r), .I2(cal1_dlyce_cpt_r_i_2_n_0), .I3(out[2]), .I4(out[4]), .I5(out[3]), .O(cal1_dlyce_cpt_r)); LUT3 #( .INIT(8'h24)) cal1_dlyce_cpt_r_i_2 (.I0(out[0]), .I1(out[2]), .I2(out[1]), .O(cal1_dlyce_cpt_r_i_2_n_0)); FDRE #( .INIT(1'b0)) cal1_dlyce_cpt_r_reg (.C(CLK), .CE(1'b1), .D(cal1_dlyce_cpt_r), .Q(cal1_dlyce_cpt_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000000001000000)) cal1_dlyinc_cpt_r_i_1 (.I0(out[2]), .I1(tap_limit_cpt_r), .I2(cal1_state_r), .I3(out[1]), .I4(out[0]), .I5(cal1_dlyinc_cpt_r_i_2_n_0), .O(cal1_dlyinc_cpt_r)); LUT2 #( .INIT(4'h7)) cal1_dlyinc_cpt_r_i_2 (.I0(out[3]), .I1(out[4]), .O(cal1_dlyinc_cpt_r_i_2_n_0)); FDRE #( .INIT(1'b0)) cal1_dlyinc_cpt_r_reg (.C(CLK), .CE(1'b1), .D(cal1_dlyinc_cpt_r), .Q(cal1_dlyinc_cpt_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT5 #( .INIT(32'h00000020)) cal1_dq_idel_ce_i_1 (.I0(out[2]), .I1(out[3]), .I2(out[4]), .I3(out[0]), .I4(cal1_state_r), .O(cal1_dq_idel_ce)); FDRE #( .INIT(1'b0)) cal1_dq_idel_ce_reg (.C(CLK), .CE(1'b1), .D(cal1_dq_idel_ce), .Q(idelay_ce_int), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'h0000000000001000)) cal1_dq_idel_inc_i_1 (.I0(cal1_state_r), .I1(out[1]), .I2(out[4]), .I3(out[2]), .I4(out[3]), .I5(out[0]), .O(cal1_dq_idel_inc)); FDRE #( .INIT(1'b0)) cal1_dq_idel_inc_reg (.C(CLK), .CE(1'b1), .D(cal1_dq_idel_inc), .Q(idelay_inc_int), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h2000000000000000)) cal1_prech_req_r_i_1 (.I0(out[4]), .I1(cal1_state_r), .I2(out[2]), .I3(out[3]), .I4(out[1]), .I5(out[0]), .O(cal1_prech_req_r)); FDRE #( .INIT(1'b0)) cal1_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(cal1_prech_req_r), .Q(cal1_prech_req_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'h00404000501F500C)) \cal1_state_r1[0]_i_1 (.I0(cal1_state_r), .I1(out[1]), .I2(out[4]), .I3(out[3]), .I4(out[0]), .I5(out[2]), .O(\cal1_state_r1[0]_i_1_n_0 )); LUT6 #( .INIT(64'h090A010E00045440)) \cal1_state_r1[1]_i_1 (.I0(out[3]), .I1(out[0]), .I2(cal1_state_r), .I3(out[1]), .I4(out[2]), .I5(out[4]), .O(\cal1_state_r1[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000CA0F1102C)) \cal1_state_r1[2]_i_1 (.I0(out[1]), .I1(out[0]), .I2(out[4]), .I3(out[3]), .I4(out[2]), .I5(cal1_state_r), .O(\cal1_state_r1[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0101C54901008482)) \cal1_state_r1[3]_i_1 (.I0(out[2]), .I1(out[4]), .I2(out[3]), .I3(out[1]), .I4(cal1_state_r), .I5(out[0]), .O(\cal1_state_r1[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0100004500000440)) \cal1_state_r1[4]_i_1 (.I0(out[3]), .I1(out[1]), .I2(cal1_state_r), .I3(out[4]), .I4(out[2]), .I5(out[0]), .O(\cal1_state_r1[4]_i_1_n_0 )); LUT6 #( .INIT(64'h1000000800004002)) \cal1_state_r1[5]_i_1 (.I0(cal1_state_r), .I1(out[1]), .I2(out[4]), .I3(out[3]), .I4(out[2]), .I5(out[0]), .O(\cal1_state_r1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cal1_state_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[0]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cal1_state_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[1]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cal1_state_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[2]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cal1_state_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[3]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cal1_state_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[4]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cal1_state_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[5]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[5] ), .R(1'b0)); LUT6 #( .INIT(64'h06090C0600090F12)) cal1_wait_cnt_en_r_i_1 (.I0(out[1]), .I1(out[3]), .I2(cal1_state_r), .I3(out[4]), .I4(out[0]), .I5(out[2]), .O(cal1_wait_cnt_en_r0)); FDRE #( .INIT(1'b0)) cal1_wait_cnt_en_r_reg (.C(CLK), .CE(1'b1), .D(cal1_wait_cnt_en_r0), .Q(cal1_wait_cnt_en_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cal1_wait_cnt_r[0]_i_1 (.I0(cal1_wait_cnt_r_reg__0[0]), .O(p_0_in__0__0[0])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT2 #( .INIT(4'h6)) \cal1_wait_cnt_r[1]_i_1 (.I0(cal1_wait_cnt_r_reg__0[1]), .I1(cal1_wait_cnt_r_reg__0[0]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT3 #( .INIT(8'h6A)) \cal1_wait_cnt_r[2]_i_1 (.I0(cal1_wait_cnt_r_reg__0[2]), .I1(cal1_wait_cnt_r_reg__0[0]), .I2(cal1_wait_cnt_r_reg__0[1]), .O(p_0_in__0__0[2])); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT4 #( .INIT(16'h6AAA)) \cal1_wait_cnt_r[3]_i_1 (.I0(cal1_wait_cnt_r_reg__0[3]), .I1(cal1_wait_cnt_r_reg__0[1]), .I2(cal1_wait_cnt_r_reg__0[0]), .I3(cal1_wait_cnt_r_reg__0[2]), .O(p_0_in__0__0[3])); LUT6 #( .INIT(64'h40000000FFFFFFFF)) \cal1_wait_cnt_r[4]_i_1 (.I0(cal1_wait_cnt_r_reg__0[4]), .I1(cal1_wait_cnt_r_reg__0[3]), .I2(cal1_wait_cnt_r_reg__0[1]), .I3(cal1_wait_cnt_r_reg__0[0]), .I4(cal1_wait_cnt_r_reg__0[2]), .I5(cal1_wait_cnt_en_r), .O(\cal1_wait_cnt_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cal1_wait_cnt_r[4]_i_2 (.I0(cal1_wait_cnt_r_reg__0[4]), .I1(cal1_wait_cnt_r_reg__0[2]), .I2(cal1_wait_cnt_r_reg__0[0]), .I3(cal1_wait_cnt_r_reg__0[1]), .I4(cal1_wait_cnt_r_reg__0[3]), .O(p_0_in__0__0[4])); FDRE #( .INIT(1'b0)) \cal1_wait_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[0]), .Q(cal1_wait_cnt_r_reg__0[0]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cal1_wait_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[1]), .Q(cal1_wait_cnt_r_reg__0[1]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cal1_wait_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[2]), .Q(cal1_wait_cnt_r_reg__0[2]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cal1_wait_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[3]), .Q(cal1_wait_cnt_r_reg__0[3]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \cal1_wait_cnt_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[4]), .Q(cal1_wait_cnt_r_reg__0[4]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hBFFFFFFFFFFFFFFF)) cal1_wait_r_i_1 (.I0(cal1_wait_cnt_r_reg__0[4]), .I1(cal1_wait_cnt_r_reg__0[3]), .I2(cal1_wait_cnt_r_reg__0[1]), .I3(cal1_wait_cnt_r_reg__0[0]), .I4(cal1_wait_cnt_r_reg__0[2]), .I5(cal1_wait_cnt_en_r), .O(cal1_wait_r_i_1_n_0)); FDRE #( .INIT(1'b0)) cal1_wait_r_reg (.C(CLK), .CE(1'b1), .D(cal1_wait_r_i_1_n_0), .Q(cal1_wait_r), .R(1'b0)); LUT5 #( .INIT(32'h74FF7400)) \cnt_idel_dec_cpt_r[0]_i_1 (.I0(cnt_idel_dec_cpt_r2[1]), .I1(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I2(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ), .I3(out[0]), .I4(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[0])); LUT6 #( .INIT(64'hB800B8FFB8FFB800)) \cnt_idel_dec_cpt_r[0]_i_2 (.I0(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[1] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\tap_cnt_cpt_r_reg_n_0_[0] ), .I5(right_edge_taps_r__0[1]), .O(\cnt_idel_dec_cpt_r[0]_i_2_n_0 )); LUT4 #( .INIT(16'h404F)) \cnt_idel_dec_cpt_r[0]_i_3 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [0]), .I2(out[1]), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'h6F60FFFF6F600000)) \cnt_idel_dec_cpt_r[1]_i_1 (.I0(cnt_idel_dec_cpt_r2[2]), .I1(cnt_idel_dec_cpt_r2[1]), .I2(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I3(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ), .I4(out[0]), .I5(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ), .O(cnt_idel_dec_cpt_r[1])); (* SOFT_HLUTNM = "soft_lutpair207" *) LUT4 #( .INIT(16'h4BB4)) \cnt_idel_dec_cpt_r[1]_i_10 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(right_edge_taps_r__0[1]), .I2(right_edge_taps_r__0[2]), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_11 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\first_edge_taps_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[1]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_12 (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ), .I1(\first_edge_taps_r_reg_n_0_[2] ), .O(\cnt_idel_dec_cpt_r[1]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_13 (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ), .I1(\first_edge_taps_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_14 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(\first_edge_taps_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[1]_i_14_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[1]_i_3 (.I0(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[1]_i_10_n_0 ), .O(\cnt_idel_dec_cpt_r[1]_i_3_n_0 )); LUT5 #( .INIT(32'h4F40404F)) \cnt_idel_dec_cpt_r[1]_i_4 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [1]), .I2(out[1]), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_5 (.I0(\second_edge_taps_r_reg_n_0_[3] ), .I1(\first_edge_taps_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[1]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_6 (.I0(\second_edge_taps_r_reg_n_0_[2] ), .I1(\first_edge_taps_r_reg_n_0_[2] ), .O(\cnt_idel_dec_cpt_r[1]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_7 (.I0(\second_edge_taps_r_reg_n_0_[1] ), .I1(\first_edge_taps_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_8 (.I0(\second_edge_taps_r_reg_n_0_[0] ), .I1(\first_edge_taps_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[1]_i_8_n_0 )); LUT5 #( .INIT(32'hB8B8B88B)) \cnt_idel_dec_cpt_r[2]_i_2 (.I0(\rdlvl_cpt_tap_cnt_reg[2] ), .I1(out[1]), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'h6AFF6A00)) \cnt_idel_dec_cpt_r[2]_i_3 (.I0(cnt_idel_dec_cpt_r2[3]), .I1(cnt_idel_dec_cpt_r2[1]), .I2(cnt_idel_dec_cpt_r2[2]), .I3(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I4(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ), .O(\cnt_idel_dec_cpt_r[2]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[2]_i_4 (.I0(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ), .O(\cnt_idel_dec_cpt_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'h40F4BF0BBF0B40F4)) \cnt_idel_dec_cpt_r[2]_i_5 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(right_edge_taps_r__0[1]), .I2(right_edge_taps_r__0[2]), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .I4(right_edge_taps_r__0[3]), .I5(\tap_cnt_cpt_r_reg_n_0_[2] ), .O(\cnt_idel_dec_cpt_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'hB8B8B8B8B8B8B88B)) \cnt_idel_dec_cpt_r[3]_i_2 (.I0(\calib_sel_reg[3]_0 [1]), .I1(out[1]), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6AAAFFFF6AAA0000)) \cnt_idel_dec_cpt_r[3]_i_3 (.I0(cnt_idel_dec_cpt_r2[4]), .I1(cnt_idel_dec_cpt_r2[2]), .I2(cnt_idel_dec_cpt_r2[1]), .I3(cnt_idel_dec_cpt_r2[3]), .I4(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I5(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ), .O(\cnt_idel_dec_cpt_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[3]_i_4 (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[4] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ), .O(\cnt_idel_dec_cpt_r[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'h96)) \cnt_idel_dec_cpt_r[3]_i_5 (.I0(\cnt_idel_dec_cpt_r[5]_i_11_n_0 ), .I1(right_edge_taps_r__0[4]), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[3]_i_5_n_0 )); LUT6 #( .INIT(64'hB888B8BBB8BBB888)) \cnt_idel_dec_cpt_r[4]_i_1 (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ), .I1(out[0]), .I2(\rdlvl_cpt_tap_cnt_reg[4] ), .I3(out[1]), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I5(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[4])); (* SOFT_HLUTNM = "soft_lutpair205" *) LUT4 #( .INIT(16'h0001)) \cnt_idel_dec_cpt_r[4]_i_3 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[4]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[4]_i_4 (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[5] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[4]_i_7_n_0 ), .O(\cnt_idel_dec_cpt_r[4]_i_4_n_0 )); LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_idel_dec_cpt_r[4]_i_5 (.I0(cnt_idel_dec_cpt_r2[5]), .I1(cnt_idel_dec_cpt_r2[3]), .I2(cnt_idel_dec_cpt_r2[1]), .I3(cnt_idel_dec_cpt_r2[2]), .I4(cnt_idel_dec_cpt_r2[4]), .O(\cnt_idel_dec_cpt_r[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT5 #( .INIT(32'hB24D4DB2)) \cnt_idel_dec_cpt_r[4]_i_7 (.I0(\cnt_idel_dec_cpt_r[5]_i_11_n_0 ), .I1(\tap_cnt_cpt_r_reg_n_0_[3] ), .I2(right_edge_taps_r__0[4]), .I3(right_edge_taps_r__0[5]), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .O(\cnt_idel_dec_cpt_r[4]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[4]_i_8 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(\first_edge_taps_r_reg_n_0_[5] ), .O(\cnt_idel_dec_cpt_r[4]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[4]_i_9 (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ), .I1(\first_edge_taps_r_reg_n_0_[4] ), .O(\cnt_idel_dec_cpt_r[4]_i_9_n_0 )); LUT6 #( .INIT(64'h0000008800222000)) \cnt_idel_dec_cpt_r[5]_i_1 (.I0(\cnt_idel_dec_cpt_r[5]_i_3_n_0 ), .I1(out[3]), .I2(store_sr_req_r_reg_0), .I3(out[1]), .I4(out[2]), .I5(out[0]), .O(\cnt_idel_dec_cpt_r[5]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \cnt_idel_dec_cpt_r[5]_i_10 (.I0(cnt_idel_dec_cpt_r2[4]), .I1(cnt_idel_dec_cpt_r2[2]), .I2(cnt_idel_dec_cpt_r2[1]), .I3(cnt_idel_dec_cpt_r2[3]), .O(\cnt_idel_dec_cpt_r[5]_i_10_n_0 )); LUT6 #( .INIT(64'h2B222222BBBB2B22)) \cnt_idel_dec_cpt_r[5]_i_11 (.I0(right_edge_taps_r__0[3]), .I1(\tap_cnt_cpt_r_reg_n_0_[2] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(right_edge_taps_r__0[1]), .I4(right_edge_taps_r__0[2]), .I5(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[5]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[5]_i_12 (.I0(\second_edge_taps_r_reg_n_0_[5] ), .I1(\first_edge_taps_r_reg_n_0_[5] ), .O(\cnt_idel_dec_cpt_r[5]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[5]_i_13 (.I0(\second_edge_taps_r_reg_n_0_[4] ), .I1(\first_edge_taps_r_reg_n_0_[4] ), .O(\cnt_idel_dec_cpt_r[5]_i_13_n_0 )); LUT3 #( .INIT(8'h41)) \cnt_idel_dec_cpt_r[5]_i_3 (.I0(cal1_state_r), .I1(out[4]), .I2(out[3]), .O(\cnt_idel_dec_cpt_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \cnt_idel_dec_cpt_r[5]_i_4 (.I0(\rdlvl_cpt_tap_cnt_reg[4] ), .I1(\rdlvl_cpt_tap_cnt_reg[1] ), .I2(\rdlvl_cpt_tap_cnt_reg[2] ), .I3(\calib_sel_reg[3]_0 [1]), .I4(\calib_sel_reg[3]_0 [0]), .I5(\calib_sel_reg[3]_0 [2]), .O(store_sr_req_r_reg_0)); LUT5 #( .INIT(32'hB88BB8B8)) \cnt_idel_dec_cpt_r[5]_i_5 (.I0(\calib_sel_reg[3]_0 [2]), .I1(out[1]), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I4(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ), .O(\cnt_idel_dec_cpt_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'hF00F0F0F11111111)) \cnt_idel_dec_cpt_r[5]_i_6 (.I0(\cnt_idel_dec_cpt_r[5]_i_7_n_0 ), .I1(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I2(\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ), .I3(\cnt_idel_dec_cpt_r[5]_i_10_n_0 ), .I4(cnt_idel_dec_cpt_r2[5]), .I5(\cnt_idel_dec_cpt_r_reg[0]_0 ), .O(\cnt_idel_dec_cpt_r[5]_i_6_n_0 )); LUT6 #( .INIT(64'h9A59AAAA55559A59)) \cnt_idel_dec_cpt_r[5]_i_7 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(right_edge_taps_r__0[4]), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r[5]_i_11_n_0 ), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .I5(right_edge_taps_r__0[5]), .O(\cnt_idel_dec_cpt_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \cnt_idel_dec_cpt_r[5]_i_8 (.I0(right_edge_taps_r__0[2]), .I1(right_edge_taps_r__0[3]), .I2(right_edge_taps_r__0[1]), .I3(right_edge_taps_r__0[0]), .I4(right_edge_taps_r__0[5]), .I5(right_edge_taps_r__0[4]), .O(\cnt_idel_dec_cpt_r[5]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \cnt_idel_dec_cpt_r_reg[0] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[0]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cnt_idel_dec_cpt_r_reg[1] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[1]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .R(1'b0)); CARRY4 \cnt_idel_dec_cpt_r_reg[1]_i_2 (.CI(1'b0), .CO({\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ,\cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ,\cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ,\cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 }), .CYINIT(1'b1), .DI({\second_edge_taps_r_reg_n_0_[3] ,\second_edge_taps_r_reg_n_0_[2] ,\second_edge_taps_r_reg_n_0_[1] ,\second_edge_taps_r_reg_n_0_[0] }), .O({cnt_idel_dec_cpt_r2[3:1],\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED [0]}), .S({\cnt_idel_dec_cpt_r[1]_i_5_n_0 ,\cnt_idel_dec_cpt_r[1]_i_6_n_0 ,\cnt_idel_dec_cpt_r[1]_i_7_n_0 ,\cnt_idel_dec_cpt_r[1]_i_8_n_0 })); CARRY4 \cnt_idel_dec_cpt_r_reg[1]_i_9 (.CI(1'b0), .CO({\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 }), .CYINIT(1'b1), .DI({\tap_cnt_cpt_r_reg_n_0_[3] ,\tap_cnt_cpt_r_reg_n_0_[2] ,\tap_cnt_cpt_r_reg_n_0_[1] ,\tap_cnt_cpt_r_reg_n_0_[0] }), .O({\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ,\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED [0]}), .S({\cnt_idel_dec_cpt_r[1]_i_11_n_0 ,\cnt_idel_dec_cpt_r[1]_i_12_n_0 ,\cnt_idel_dec_cpt_r[1]_i_13_n_0 ,\cnt_idel_dec_cpt_r[1]_i_14_n_0 })); FDRE #( .INIT(1'b0)) \cnt_idel_dec_cpt_r_reg[2] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[2]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[2]_i_1 (.I0(\cnt_idel_dec_cpt_r[2]_i_2_n_0 ), .I1(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[2]), .S(out[0])); FDRE #( .INIT(1'b0)) \cnt_idel_dec_cpt_r_reg[3] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[3]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[3]_i_1 (.I0(\cnt_idel_dec_cpt_r[3]_i_2_n_0 ), .I1(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[3]), .S(out[0])); FDRE #( .INIT(1'b0)) \cnt_idel_dec_cpt_r_reg[4] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[4]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[4]_i_2 (.I0(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ), .I1(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ), .O(\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ), .S(\cnt_idel_dec_cpt_r_reg[0]_0 )); CARRY4 \cnt_idel_dec_cpt_r_reg[4]_i_6 (.CI(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ), .CO({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED [3:1],\cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\tap_cnt_cpt_r_reg_n_0_[4] }), .O({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED [3:2],\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ,\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 }), .S({1'b0,1'b0,\cnt_idel_dec_cpt_r[4]_i_8_n_0 ,\cnt_idel_dec_cpt_r[4]_i_9_n_0 })); FDRE #( .INIT(1'b0)) \cnt_idel_dec_cpt_r_reg[5] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[5]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[5]_i_2 (.I0(\cnt_idel_dec_cpt_r[5]_i_5_n_0 ), .I1(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ), .O(cnt_idel_dec_cpt_r[5]), .S(out[0])); CARRY4 \cnt_idel_dec_cpt_r_reg[5]_i_9 (.CI(\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ), .CO({\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [3],\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ,\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [1],\cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,\second_edge_taps_r_reg_n_0_[5] ,\second_edge_taps_r_reg_n_0_[4] }), .O({\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED [3:2],cnt_idel_dec_cpt_r2[5:4]}), .S({1'b0,1'b1,\cnt_idel_dec_cpt_r[5]_i_12_n_0 ,\cnt_idel_dec_cpt_r[5]_i_13_n_0 })); LUT6 #( .INIT(64'h00000000FFFFFFF7)) \cnt_shift_r[0]_i_1 (.I0(rdlvl_stg1_start_reg), .I1(phy_rddata_en_1), .I2(cnt_shift_r_reg__0[1]), .I3(cnt_shift_r_reg__0[3]), .I4(cnt_shift_r_reg__0[2]), .I5(cnt_shift_r_reg__0[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT2 #( .INIT(4'h6)) \cnt_shift_r[1]_i_1 (.I0(cnt_shift_r_reg__0[1]), .I1(cnt_shift_r_reg__0[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT3 #( .INIT(8'h6A)) \cnt_shift_r[2]_i_1 (.I0(cnt_shift_r_reg__0[2]), .I1(cnt_shift_r_reg__0[0]), .I2(cnt_shift_r_reg__0[1]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT4 #( .INIT(16'h6AAA)) \cnt_shift_r[3]_i_3 (.I0(cnt_shift_r_reg__0[3]), .I1(cnt_shift_r_reg__0[1]), .I2(cnt_shift_r_reg__0[0]), .I3(cnt_shift_r_reg__0[2]), .O(p_0_in__1[3])); FDSE #( .INIT(1'b1)) \cnt_shift_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in__1[0]), .Q(cnt_shift_r_reg__0[0]), .S(rdlvl_stg1_start_reg_0)); FDRE #( .INIT(1'b0)) \cnt_shift_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in__1[1]), .Q(cnt_shift_r_reg__0[1]), .R(rdlvl_stg1_start_reg_0)); FDRE #( .INIT(1'b0)) \cnt_shift_r_reg[2] (.C(CLK), .CE(E), .D(p_0_in__1[2]), .Q(cnt_shift_r_reg__0[2]), .R(rdlvl_stg1_start_reg_0)); FDRE #( .INIT(1'b0)) \cnt_shift_r_reg[3] (.C(CLK), .CE(E), .D(p_0_in__1[3]), .Q(cnt_shift_r_reg__0[3]), .R(rdlvl_stg1_start_reg_0)); LUT2 #( .INIT(4'h8)) \ctl_lane_cnt[1]_i_2 (.I0(pi_fine_dly_dec_done), .I1(dqs_po_dec_done), .O(cmd_delay_start0)); LUT5 #( .INIT(32'h00008000)) detect_edge_done_r_i_1 (.I0(pb_detect_edge_done_r[6]), .I1(pb_detect_edge_done_r[7]), .I2(pb_detect_edge_done_r[4]), .I3(pb_detect_edge_done_r[5]), .I4(detect_edge_done_r_i_2_n_0), .O(detect_edge_done_r_i_1_n_0)); LUT4 #( .INIT(16'h7FFF)) detect_edge_done_r_i_2 (.I0(pb_detect_edge_done_r[1]), .I1(pb_detect_edge_done_r[0]), .I2(pb_detect_edge_done_r[3]), .I3(pb_detect_edge_done_r[2]), .O(detect_edge_done_r_i_2_n_0)); FDRE #( .INIT(1'b0)) detect_edge_done_r_reg (.C(CLK), .CE(1'b1), .D(detect_edge_done_r_i_1_n_0), .Q(detect_edge_done_r), .R(1'b0)); LUT6 #( .INIT(64'h0000000000005554)) \done_cnt[0]_i_1 (.I0(done_cnt[0]), .I1(done_cnt[1]), .I2(done_cnt[3]), .I3(done_cnt[2]), .I4(done_cnt1), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\done_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT5 #( .INIT(32'hFFAAAAFE)) \done_cnt[1]_i_1 (.I0(done_cnt1), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[1]), .I4(done_cnt[0]), .O(\done_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000EE10)) \done_cnt[2]_i_1 (.I0(done_cnt[0]), .I1(done_cnt[1]), .I2(done_cnt[3]), .I3(done_cnt[2]), .I4(done_cnt1), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\done_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT5 #( .INIT(32'hFAFAFAEA)) \done_cnt[3]_i_1 (.I0(done_cnt1), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[1]), .I4(done_cnt[0]), .O(\done_cnt[3]_i_1_n_0 )); LUT4 #( .INIT(16'h8F88)) \done_cnt[3]_i_2 (.I0(\done_cnt[3]_i_3_n_0 ), .I1(\done_cnt[3]_i_4_n_0 ), .I2(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I3(p_0_in539_in), .O(done_cnt1)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'h0004)) \done_cnt[3]_i_3 (.I0(done_cnt[1]), .I1(done_cnt[0]), .I2(done_cnt[3]), .I3(done_cnt[2]), .O(\done_cnt[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF7)) \done_cnt[3]_i_4 (.I0(cal1_state_r), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(out[4]), .I5(out[2]), .O(\done_cnt[3]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \done_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\done_cnt[0]_i_1_n_0 ), .Q(done_cnt[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \done_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\done_cnt[1]_i_1_n_0 ), .Q(done_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \done_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\done_cnt[2]_i_1_n_0 ), .Q(done_cnt[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \done_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\done_cnt[3]_i_1_n_0 ), .Q(done_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) dqs_po_dec_done_r1_reg (.C(CLK), .CE(1'b1), .D(dqs_po_dec_done), .Q(dqs_po_dec_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) dqs_po_dec_done_r2_reg (.C(CLK), .CE(1'b1), .D(dqs_po_dec_done_r1), .Q(dqs_po_dec_done_r2), .R(1'b0)); LUT5 #( .INIT(32'hFFFF22F2)) fine_dly_dec_done_r1_i_1 (.I0(fine_dly_dec_done_r1_i_2_n_0), .I1(fine_dly_dec_done_r1_i_3_n_0), .I2(dqs_po_dec_done_r2), .I3(\pi_rdval_cnt_reg[1]_0 ), .I4(fine_dly_dec_done_r1), .O(fine_dly_dec_done_r1_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT4 #( .INIT(16'h0010)) fine_dly_dec_done_r1_i_2 (.I0(pi_rdval_cnt[1]), .I1(pi_rdval_cnt[2]), .I2(pi_rdval_cnt[0]), .I3(pi_rdval_cnt[4]), .O(fine_dly_dec_done_r1_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT3 #( .INIT(8'hFB)) fine_dly_dec_done_r1_i_3 (.I0(pi_rdval_cnt[5]), .I1(pi_en_stg2_f_timing_reg_0), .I2(pi_rdval_cnt[3]), .O(fine_dly_dec_done_r1_i_3_n_0)); FDRE #( .INIT(1'b0)) fine_dly_dec_done_r1_reg (.C(CLK), .CE(1'b1), .D(fine_dly_dec_done_r1_i_1_n_0), .Q(fine_dly_dec_done_r1), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) fine_dly_dec_done_r2_reg (.C(CLK), .CE(1'b1), .D(fine_dly_dec_done_r1), .Q(fine_dly_dec_done_r2), .R(1'b0)); LUT3 #( .INIT(8'h80)) \first_edge_taps_r[5]_i_1 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(out[2]), .O(\first_edge_taps_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888800202020)) \first_edge_taps_r[5]_i_2 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(\right_edge_taps_r_reg[0]_2 ), .I3(found_stable_eye_last_r), .I4(\right_edge_taps_r_reg[0]_0 ), .I5(out[2]), .O(\first_edge_taps_r[5]_i_2_n_0 )); LUT4 #( .INIT(16'h2000)) \first_edge_taps_r[5]_i_3 (.I0(out[4]), .I1(cal1_state_r), .I2(out[0]), .I3(out[1]), .O(\right_edge_taps_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair222" *) LUT3 #( .INIT(8'h08)) \first_edge_taps_r[5]_i_4 (.I0(detect_edge_done_r), .I1(found_first_edge_r_reg_0), .I2(tap_limit_cpt_r), .O(\right_edge_taps_r_reg[0]_2 )); FDRE #( .INIT(1'b0)) \first_edge_taps_r_reg[0] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\first_edge_taps_r_reg_n_0_[0] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \first_edge_taps_r_reg[1] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\first_edge_taps_r_reg_n_0_[1] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \first_edge_taps_r_reg[2] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\first_edge_taps_r_reg_n_0_[2] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \first_edge_taps_r_reg[3] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\first_edge_taps_r_reg_n_0_[3] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \first_edge_taps_r_reg[4] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\first_edge_taps_r_reg_n_0_[4] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \first_edge_taps_r_reg[5] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\first_edge_taps_r_reg_n_0_[5] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) found_edge_r_i_1 (.I0(found_edge_r_reg_1), .I1(found_edge_r_reg_2), .I2(found_edge_r_reg_0), .I3(found_edge_r_reg_3), .I4(found_edge_r_i_2_n_0), .O(found_edge_r_i_1_n_0)); LUT4 #( .INIT(16'hFFFE)) found_edge_r_i_2 (.I0(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .I1(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .I2(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .I3(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .O(found_edge_r_i_2_n_0)); FDRE #( .INIT(1'b0)) found_edge_r_reg (.C(CLK), .CE(1'b1), .D(found_edge_r_i_1_n_0), .Q(found_first_edge_r_reg_0), .R(1'b0)); FDRE #( .INIT(1'b0)) found_first_edge_r_reg (.C(CLK), .CE(1'b1), .D(found_edge_r_reg_4), .Q(\right_edge_taps_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) found_second_edge_r_reg (.C(CLK), .CE(1'b1), .D(found_stable_eye_last_r_reg_1), .Q(\cnt_idel_dec_cpt_r_reg[0]_0 ), .R(SR)); FDRE #( .INIT(1'b0)) found_stable_eye_last_r_reg (.C(CLK), .CE(1'b1), .D(found_stable_eye_r_reg_0), .Q(found_stable_eye_last_r), .R(pb_detect_edge_setup)); LUT5 #( .INIT(32'h00008000)) found_stable_eye_r_i_1 (.I0(\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .I1(\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .I2(\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .I3(\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .I4(found_stable_eye_r_i_2_n_0), .O(found_stable_eye_r_i_1_n_0)); LUT4 #( .INIT(16'h7FFF)) found_stable_eye_r_i_2 (.I0(\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .I1(\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .I2(\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .I3(\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .O(found_stable_eye_r_i_2_n_0)); FDRE #( .INIT(1'b0)) found_stable_eye_r_reg (.C(CLK), .CE(1'b1), .D(found_stable_eye_r_i_1_n_0), .Q(found_stable_eye_last_r_reg_0), .R(1'b0)); LUT3 #( .INIT(8'hB8)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_4 (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I1(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ), .I2(regl_dqs_cnt_r[0]), .O(pi_stg2_rdlvl_cnt[0])); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT3 #( .INIT(8'hB8)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_4 (.I0(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I1(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ), .I2(regl_dqs_cnt_r[1]), .O(pi_stg2_rdlvl_cnt[1])); LUT6 #( .INIT(64'hF0F4F0F4FFF4F0F4)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_3 (.I0(\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ), .I1(\prbs_dqs_cnt_r_reg[2] ), .I2(\po_stg2_wrcal_cnt_reg[2] ), .I3(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ), .I4(regl_dqs_cnt_r[2]), .I5(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT4 #( .INIT(16'hDFFF)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_5 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg), .I2(wrcal_done_reg), .I3(oclkdelay_calib_done_r_reg), .O(\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair206" *) LUT4 #( .INIT(16'h08FF)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_7 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(rdlvl_stg1_done_r1_reg), .I3(mpr_rdlvl_done_r1_reg_0), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF7)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_8 (.I0(cal1_state_r), .I1(out[1]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .I5(out[2]), .O(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \gen_byte_sel_div1.calib_in_common_i_3 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(prbs_rdlvl_done_reg), .I3(rdlvl_stg1_done_r1_reg), .I4(wr_level_done_reg), .I5(mpr_rdlvl_done_r1_reg_0), .O(\gen_byte_sel_div1.calib_in_common_reg )); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_8 ), .Q(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_24 ), .Q(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_40 ), .Q(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_56 ), .Q(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_0 ), .Q(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_16 ), .Q(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_32 ), .Q(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[0].mux_rd_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_48 ), .Q(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_9 ), .Q(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_25 ), .Q(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_41 ), .Q(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_57 ), .Q(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_1 ), .Q(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_17 ), .Q(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_33 ), .Q(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[1].mux_rd_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_49 ), .Q(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_10 ), .Q(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_26 ), .Q(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_42 ), .Q(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_58 ), .Q(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_2 ), .Q(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_18 ), .Q(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_34 ), .Q(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[2].mux_rd_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_50 ), .Q(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_11 ), .Q(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_27 ), .Q(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_43 ), .Q(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_59 ), .Q(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_3 ), .Q(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_19 ), .Q(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_35 ), .Q(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[3].mux_rd_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_51 ), .Q(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_12 ), .Q(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_28 ), .Q(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_44 ), .Q(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_60 ), .Q(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_4 ), .Q(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_20 ), .Q(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_36 ), .Q(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[4].mux_rd_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_52 ), .Q(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_13 ), .Q(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_29 ), .Q(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_45 ), .Q(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_61 ), .Q(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_5 ), .Q(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_21 ), .Q(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_37 ), .Q(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[5].mux_rd_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_53 ), .Q(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_14 ), .Q(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_30 ), .Q(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_46 ), .Q(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_62 ), .Q(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_6 ), .Q(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_22 ), .Q(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_38 ), .Q(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[6].mux_rd_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_54 ), .Q(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_15 ), .Q(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_31 ), .Q(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_47 ), .Q(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_63 ), .Q(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_7 ), .Q(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_23 ), .Q(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_39 ), .Q(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd[7].mux_rd_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_55 ), .Q(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ), .R(1'b0)); LUT3 #( .INIT(8'hA8)) \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r[0][0]_i_1 (.I0(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ), .I1(sr_valid_r1_reg_0), .I2(mpr_valid_r1_reg_0), .O(store_sr_r0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ), .R(1'b0)); LUT2 #( .INIT(4'hE)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r[0][0]_i_1 (.I0(sr_valid_r1_reg_0), .I1(mpr_valid_r1_reg_0), .O(store_sr_r1)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair161" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair162" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair163" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair164" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.idel_pat0_data_match_r_i_1 (.I0(idel_pat0_match_rise2_and_r), .I1(idel_pat0_match_fall2_and_r), .I2(idel_pat0_match_fall3_and_r), .I3(idel_pat0_match_rise0_and_r), .I4(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ), .O(idel_pat0_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.idel_pat0_data_match_r_i_2 (.I0(idel_pat0_match_fall0_and_r), .I1(idel_pat0_match_fall1_and_r), .I2(idel_pat0_match_rise3_and_r), .I3(idel_pat0_match_rise1_and_r), .O(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_data_match_r_reg (.C(CLK), .CE(1'b1), .D(idel_pat0_data_match_r0__0), .Q(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall0_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ), .I4(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair219" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ), .I1(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.idel_pat1_data_match_r_i_1 (.I0(idel_pat1_match_rise2_and_r), .I1(idel_pat1_match_fall2_and_r), .I2(idel_pat1_match_fall3_and_r), .I3(idel_pat1_match_rise0_and_r), .I4(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ), .O(idel_pat1_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.idel_pat1_data_match_r_i_2 (.I0(idel_pat1_match_rise1_and_r), .I1(idel_pat1_match_fall1_and_r), .I2(idel_pat1_match_rise3_and_r), .I3(idel_pat1_match_fall0_and_r), .O(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_data_match_r_reg (.C(CLK), .CE(1'b1), .D(idel_pat1_data_match_r0__0), .Q(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair223" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ), .I1(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall0_and_r), .R(1'b0)); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ), .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise1_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat0_data_match_r_i_1 (.I0(pat0_match_fall2_and_r), .I1(pat0_match_rise2_and_r), .I2(pat0_match_fall3_and_r), .I3(pat0_match_rise0_and_r), .I4(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ), .O(pat0_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat0_data_match_r_i_2 (.I0(pat0_match_rise1_and_r), .I1(pat0_match_fall1_and_r), .I2(pat0_match_rise3_and_r), .I3(pat0_match_fall0_and_r), .O(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_data_match_r_reg (.C(CLK), .CE(1'b1), .D(pat0_data_match_r0__0), .Q(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair223" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat0_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat0_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ), .Q(pat0_match_fall0_and_r), .R(1'b0)); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat0_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ), .I1(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat0_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ), .Q(pat0_match_fall1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ), .I4(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ), .Q(pat0_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ), .Q(pat0_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ), .Q(pat0_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ), .Q(pat0_match_rise1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair219" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat0_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ), .I1(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat0_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ), .Q(pat0_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ), .I4(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat0_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ), .Q(pat0_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat1_data_match_r_i_1 (.I0(pat1_match_rise2_and_r), .I1(pat1_match_fall1_and_r), .I2(pat1_match_fall3_and_r), .I3(pat1_match_rise0_and_r), .I4(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ), .O(pat1_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat1_data_match_r_i_2 (.I0(pat1_match_fall0_and_r), .I1(pat1_match_rise1_and_r), .I2(pat1_match_rise3_and_r), .I3(pat1_match_fall2_and_r), .O(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_data_match_r_reg (.C(CLK), .CE(1'b1), .D(pat1_data_match_r0__0), .Q(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat1_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat1_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ), .Q(pat1_match_fall0_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat1_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat1_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ), .Q(pat1_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat1_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ), .I4(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat1_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ), .Q(pat1_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat1_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ), .I4(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat1_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ), .Q(pat1_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat1_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat1_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ), .Q(pat1_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat1_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat1_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ), .Q(pat1_match_rise1_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat1_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat1_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ), .Q(pat1_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat1_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ), .I4(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat1_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat1_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ), .Q(pat1_match_rise3_and_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ), .I4(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ), .O(p_488_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv (.C(CLK), .CE(1'b1), .D(p_488_out__0), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ), .R(1'b0)); LUT2 #( .INIT(4'h1)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 (.I0(mpr_valid_r2), .I1(sr_valid_r2), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ), .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ), .O(p_513_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv (.C(CLK), .CE(1'b1), .D(p_513_out__0), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 )); LUT3 #( .INIT(8'hFB)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2 (.I0(mpr_valid_r1), .I1(mpr_rdlvl_start_reg), .I2(mpr_rdlvl_done_r1_reg_0), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 )); LUT3 #( .INIT(8'hFE)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3 (.I0(mpr_valid_r1), .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ), .I2(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ), .Q(p_1_in17_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 (.I0(p_2_in431_in), .I1(p_4_in433_in), .I2(p_0_in430_in), .I3(p_3_in432_in), .I4(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ), .O(p_438_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 (.I0(p_7_in436_in), .I1(p_5_in434_in), .I2(p_6_in435_in), .I3(p_1_in437_in), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv (.C(CLK), .CE(1'b1), .D(p_438_out__0), .Q(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in430_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ), .Q(p_0_in430_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in432_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ), .Q(p_3_in432_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in434_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ), .Q(p_5_in434_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in436_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ), .Q(p_7_in436_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in437_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ), .Q(p_1_in437_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in431_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ), .Q(p_2_in431_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in433_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ), .Q(p_4_in433_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in435_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ), .Q(p_6_in435_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ), .Q(p_0_in102_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 (.I0(p_2_in456_in), .I1(p_4_in458_in), .I2(p_0_in455_in), .I3(p_3_in457_in), .I4(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ), .O(p_463_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 (.I0(p_7_in461_in), .I1(p_6_in460_in), .I2(p_5_in459_in), .I3(p_1_in462_in), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv (.C(CLK), .CE(1'b1), .D(p_463_out__0), .Q(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in455_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ), .Q(p_0_in455_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in457_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ), .Q(p_3_in457_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in459_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ), .Q(p_5_in459_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in461_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ), .Q(p_7_in461_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in462_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ), .Q(p_1_in462_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in456_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ), .Q(p_2_in456_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in458_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ), .Q(p_4_in458_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in460_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ), .Q(p_6_in460_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ), .Q(p_1_in14_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 (.I0(p_3_in382_in), .I1(p_4_in383_in), .I2(p_2_in381_in), .I3(p_0_in380_in), .I4(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ), .O(p_388_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 (.I0(p_7_in386_in), .I1(p_5_in384_in), .I2(p_6_in385_in), .I3(p_1_in387_in), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv (.C(CLK), .CE(1'b1), .D(p_388_out__0), .Q(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in380_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ), .Q(p_0_in380_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in382_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ), .Q(p_3_in382_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in384_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ), .Q(p_5_in384_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in386_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ), .Q(p_7_in386_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in387_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ), .Q(p_1_in387_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in381_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ), .Q(p_2_in381_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in383_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ), .Q(p_4_in383_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in385_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ), .Q(p_6_in385_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ), .Q(p_0_in99_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 (.I0(p_2_in406_in), .I1(p_4_in408_in), .I2(p_0_in405_in), .I3(p_3_in407_in), .I4(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ), .O(p_413_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 (.I0(p_7_in411_in), .I1(p_5_in409_in), .I2(p_6_in410_in), .I3(p_1_in412_in), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv (.C(CLK), .CE(1'b1), .D(p_413_out__0), .Q(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in405_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ), .Q(p_0_in405_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in407_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ), .Q(p_3_in407_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in409_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ), .Q(p_5_in409_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in411_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ), .Q(p_7_in411_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in412_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ), .Q(p_1_in412_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in406_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ), .Q(p_2_in406_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in408_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ), .Q(p_4_in408_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in410_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ), .Q(p_6_in410_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ), .Q(p_1_in11_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 (.I0(p_3_in332_in), .I1(p_4_in333_in), .I2(p_2_in331_in), .I3(p_0_in330_in), .I4(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ), .O(p_338_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 (.I0(p_6_in335_in), .I1(p_5_in334_in), .I2(p_7_in336_in), .I3(p_1_in337_in), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv (.C(CLK), .CE(1'b1), .D(p_338_out__0), .Q(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in330_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ), .Q(p_0_in330_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in332_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ), .Q(p_3_in332_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in334_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ), .Q(p_5_in334_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in336_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ), .Q(p_7_in336_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in337_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ), .Q(p_1_in337_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in331_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ), .Q(p_2_in331_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in333_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ), .Q(p_4_in333_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in335_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ), .Q(p_6_in335_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ), .Q(p_0_in96_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 (.I0(p_4_in358_in), .I1(p_5_in359_in), .I2(p_3_in357_in), .I3(p_0_in355_in), .I4(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ), .O(p_363_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 (.I0(p_7_in361_in), .I1(p_6_in360_in), .I2(p_2_in356_in), .I3(p_1_in362_in), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv (.C(CLK), .CE(1'b1), .D(p_363_out__0), .Q(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in355_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ), .Q(p_0_in355_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in357_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ), .Q(p_3_in357_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in359_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ), .Q(p_5_in359_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in361_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ), .Q(p_7_in361_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in362_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ), .Q(p_1_in362_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in356_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ), .Q(p_2_in356_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in358_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ), .Q(p_4_in358_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair161" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in360_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ), .Q(p_6_in360_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ), .Q(p_1_in8_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 (.I0(p_4_in283_in), .I1(p_5_in284_in), .I2(p_3_in282_in), .I3(p_2_in281_in), .I4(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ), .O(p_288_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 (.I0(p_7_in286_in), .I1(p_6_in285_in), .I2(p_0_in280_in), .I3(p_1_in287_in), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv (.C(CLK), .CE(1'b1), .D(p_288_out__0), .Q(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in280_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ), .Q(p_0_in280_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in282_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ), .Q(p_3_in282_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in284_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ), .Q(p_5_in284_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in286_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ), .Q(p_7_in286_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in287_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ), .Q(p_1_in287_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in281_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ), .Q(p_2_in281_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in283_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ), .Q(p_4_in283_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in285_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ), .Q(p_6_in285_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ), .Q(p_0_in93_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 (.I0(p_4_in308_in), .I1(p_5_in309_in), .I2(p_3_in307_in), .I3(p_2_in306_in), .I4(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ), .O(p_313_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 (.I0(p_7_in311_in), .I1(p_6_in310_in), .I2(p_0_in305_in), .I3(p_1_in312_in), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv (.C(CLK), .CE(1'b1), .D(p_313_out__0), .Q(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in305_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ), .Q(p_0_in305_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in307_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ), .Q(p_3_in307_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in309_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ), .Q(p_5_in309_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in311_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ), .Q(p_7_in311_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in312_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ), .Q(p_1_in312_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in306_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ), .Q(p_2_in306_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in308_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ), .Q(p_4_in308_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair162" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in310_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ), .Q(p_6_in310_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ), .Q(p_1_in5_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 (.I0(p_4_in233_in), .I1(p_5_in234_in), .I2(p_3_in232_in), .I3(p_2_in231_in), .I4(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ), .O(p_238_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 (.I0(p_7_in236_in), .I1(p_6_in235_in), .I2(p_0_in230_in), .I3(p_1_in237_in), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv (.C(CLK), .CE(1'b1), .D(p_238_out__0), .Q(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in230_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ), .Q(p_0_in230_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in232_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ), .Q(p_3_in232_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in234_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ), .Q(p_5_in234_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in236_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ), .Q(p_7_in236_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in237_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ), .Q(p_1_in237_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in231_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ), .Q(p_2_in231_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in233_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ), .Q(p_4_in233_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in235_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ), .Q(p_6_in235_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ), .Q(p_0_in90_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 (.I0(p_4_in258_in), .I1(p_5_in259_in), .I2(p_3_in257_in), .I3(p_2_in256_in), .I4(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ), .O(p_263_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 (.I0(p_7_in261_in), .I1(p_6_in260_in), .I2(p_0_in255_in), .I3(p_1_in262_in), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv (.C(CLK), .CE(1'b1), .D(p_263_out__0), .Q(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in255_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ), .Q(p_0_in255_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in257_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ), .Q(p_3_in257_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in259_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ), .Q(p_5_in259_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in261_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ), .Q(p_7_in261_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in262_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ), .Q(p_1_in262_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in256_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ), .Q(p_2_in256_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in258_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ), .Q(p_4_in258_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair163" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in260_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ), .Q(p_6_in260_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ), .Q(p_1_in2_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 (.I0(p_4_in183_in), .I1(p_5_in184_in), .I2(p_3_in182_in), .I3(p_2_in181_in), .I4(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ), .O(p_188_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 (.I0(p_7_in186_in), .I1(p_6_in185_in), .I2(p_0_in180_in), .I3(p_1_in187_in), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv (.C(CLK), .CE(1'b1), .D(p_188_out__0), .Q(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in180_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ), .Q(p_0_in180_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in182_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ), .Q(p_3_in182_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in184_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ), .Q(p_5_in184_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in186_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ), .Q(p_7_in186_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in187_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ), .Q(p_1_in187_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in181_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ), .Q(p_2_in181_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in183_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ), .Q(p_4_in183_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in185_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ), .Q(p_6_in185_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ), .Q(p_0_in87_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 (.I0(p_4_in208_in), .I1(p_5_in209_in), .I2(p_3_in207_in), .I3(p_2_in206_in), .I4(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ), .O(p_213_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 (.I0(p_7_in211_in), .I1(p_6_in210_in), .I2(p_0_in205_in), .I3(p_1_in212_in), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv (.C(CLK), .CE(1'b1), .D(p_213_out__0), .Q(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in205_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ), .Q(p_0_in205_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in207_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ), .Q(p_3_in207_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in209_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ), .Q(p_5_in209_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in211_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ), .Q(p_7_in211_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in212_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ), .Q(p_1_in212_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in206_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ), .Q(p_2_in206_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in208_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ), .Q(p_4_in208_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair164" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in210_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ), .Q(p_6_in210_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ), .I1(p_5_in136_in), .I2(p_3_in135_in), .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ), .I4(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ), .O(p_137_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 (.I0(p_7_in), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ), .I2(p_0_in134_in), .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv (.C(CLK), .CE(1'b1), .D(p_137_out__0), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in134_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ), .Q(p_0_in134_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in135_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ), .Q(p_3_in135_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in136_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ), .Q(p_5_in136_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ), .Q(p_7_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ), .Q(p_0_in84_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 (.I0(p_4_in158_in), .I1(p_5_in159_in), .I2(p_3_in157_in), .I3(p_2_in156_in), .I4(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ), .O(p_163_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 (.I0(p_7_in161_in), .I1(p_6_in160_in), .I2(p_0_in155_in), .I3(p_1_in162_in), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv (.C(CLK), .CE(1'b1), .D(p_163_out__0), .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in155_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ), .Q(p_0_in155_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in157_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ), .Q(p_3_in157_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in159_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ), .Q(p_5_in159_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in161_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ), .Q(p_7_in161_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in162_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ), .Q(p_1_in162_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in156_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ), .Q(p_2_in156_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in158_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ), .Q(p_4_in158_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in160_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ), .Q(p_6_in160_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair215" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair215" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .O(p_0_in__2[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[0]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I5(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .O(pb_cnt_eye_size_r)); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .O(p_0_in__2[4])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ), .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .I2(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[0]), .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[0]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[1]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[2]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[3]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[4]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ), .Q(pb_detect_edge_done_r[0]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_found_edge_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ), .Q(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ), .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .O(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .O(\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4 (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .O(pb_found_stable_eye_r76_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ), .Q(\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[0]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFEFBFFFFFEF7F)) \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2 (.I0(out[3]), .I1(out[2]), .I2(out[0]), .I3(out[4]), .I4(cal1_state_r), .I5(out[1]), .O(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ), .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .O(p_0_in__3[0])); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .O(p_0_in__3[1])); (* SOFT_HLUTNM = "soft_lutpair212" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .O(p_0_in__3[2])); (* SOFT_HLUTNM = "soft_lutpair212" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .O(p_0_in__3[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[1]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I5(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .O(p_0_in__3[4])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 (.I0(p_1_in17_in), .I1(p_0_in102_in), .I2(found_edge_r_reg_0), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in16_in), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[1]), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[0]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[1]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[2]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[3]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[4]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_6), .Q(pb_detect_edge_done_r[1]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_found_edge_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ), .Q(found_edge_r_reg_0), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2 (.I0(p_0_in102_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in17_in), .I3(p_0_in16_in), .O(\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .O(\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4 (.I0(p_0_in16_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_0), .O(pb_found_stable_eye_r72_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ), .Q(\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 (.I0(p_0_in16_in), .I1(p_0_in102_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[1]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ), .Q(p_0_in16_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .O(p_0_in__4[0])); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .O(p_0_in__4[1])); (* SOFT_HLUTNM = "soft_lutpair209" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .O(p_0_in__4[2])); (* SOFT_HLUTNM = "soft_lutpair209" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .O(p_0_in__4[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[2]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I5(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .O(p_0_in__4[4])); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 (.I0(p_1_in14_in), .I1(p_0_in99_in), .I2(found_edge_r_reg_1), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in13_in), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[2]), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[0]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[1]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[2]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[3]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[4]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_5), .Q(pb_detect_edge_done_r[2]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_found_edge_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ), .Q(found_edge_r_reg_1), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2 (.I0(p_0_in99_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in14_in), .I3(p_0_in13_in), .O(\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .O(\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4 (.I0(p_0_in13_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_1), .O(pb_found_stable_eye_r68_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ), .Q(\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 (.I0(p_0_in13_in), .I1(p_0_in99_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[2]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ), .Q(p_0_in13_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .O(p_0_in__5[0])); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .O(p_0_in__5[1])); (* SOFT_HLUTNM = "soft_lutpair211" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .O(p_0_in__5[2])); (* SOFT_HLUTNM = "soft_lutpair211" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .O(p_0_in__5[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[3]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I5(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .O(p_0_in__5[4])); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 (.I0(p_1_in11_in), .I1(p_0_in96_in), .I2(found_edge_r_reg_2), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in10_in), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[3]), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[0]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[1]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[2]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[3]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[4]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_4), .Q(pb_detect_edge_done_r[3]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_found_edge_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ), .Q(found_edge_r_reg_2), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2 (.I0(p_0_in96_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in11_in), .I3(p_0_in10_in), .O(\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .O(\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4 (.I0(p_0_in10_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_2), .O(pb_found_stable_eye_r64_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ), .Q(\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 (.I0(p_0_in10_in), .I1(p_0_in96_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[3]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ), .Q(p_0_in10_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .O(p_0_in__6[0])); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .O(p_0_in__6[1])); (* SOFT_HLUTNM = "soft_lutpair216" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .O(p_0_in__6[2])); (* SOFT_HLUTNM = "soft_lutpair216" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .O(p_0_in__6[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[4]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I5(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .O(p_0_in__6[4])); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 (.I0(p_1_in8_in), .I1(p_0_in93_in), .I2(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in7_in), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[4]), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[0]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[1]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[2]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[3]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[4]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_3), .Q(pb_detect_edge_done_r[4]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_found_edge_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ), .Q(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2 (.I0(p_0_in93_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in8_in), .I3(p_0_in7_in), .O(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .O(\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4 (.I0(p_0_in7_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .O(pb_found_stable_eye_r60_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ), .Q(\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 (.I0(p_0_in7_in), .I1(p_0_in93_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[4]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ), .Q(p_0_in7_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .O(p_0_in__7[0])); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .O(p_0_in__7[1])); (* SOFT_HLUTNM = "soft_lutpair214" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .O(p_0_in__7[2])); (* SOFT_HLUTNM = "soft_lutpair214" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .O(p_0_in__7[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[5]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I5(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .O(p_0_in__7[4])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 (.I0(p_1_in5_in), .I1(p_0_in90_in), .I2(found_edge_r_reg_3), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in4_in), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair221" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[5]), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[0]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[1]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[2]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[3]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[4]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_2), .Q(pb_detect_edge_done_r[5]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_found_edge_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ), .Q(found_edge_r_reg_3), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2 (.I0(p_0_in90_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in5_in), .I3(p_0_in4_in), .O(\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .O(\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair218" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4 (.I0(p_0_in4_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_3), .O(pb_found_stable_eye_r56_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ), .Q(\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 (.I0(p_0_in4_in), .I1(p_0_in90_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[5]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ), .Q(p_0_in4_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .O(p_0_in__8[0])); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .O(p_0_in__8[1])); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .O(p_0_in__8[2])); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .O(p_0_in__8[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[6]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I5(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .O(p_0_in__8[4])); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 (.I0(p_1_in2_in), .I1(p_0_in87_in), .I2(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in1_in), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair218" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[6]), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[0]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[1]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[2]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[3]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[4]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_1), .Q(pb_detect_edge_done_r[6]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_found_edge_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ), .Q(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2 (.I0(p_0_in87_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in2_in), .I3(p_0_in1_in), .O(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 )); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .O(\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 )); (* SOFT_HLUTNM = "soft_lutpair221" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4 (.I0(p_0_in1_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .O(pb_found_stable_eye_r52_out)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ), .Q(\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 (.I0(p_0_in1_in), .I1(p_0_in87_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[6]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ), .Q(p_0_in1_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .O(p_0_in__9[0])); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .O(p_0_in__9[1])); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .O(p_0_in__9[2])); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .O(p_0_in__9[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[7]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I5(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .O(p_0_in__9[4])); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ), .I1(p_0_in84_in), .I2(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair217" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[7]), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[0]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[1]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[2]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[3]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[4]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000400040008)) \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 (.I0(out[3]), .I1(out[2]), .I2(cal1_state_r), .I3(out[4]), .I4(out[0]), .I5(out[1]), .O(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_0), .Q(pb_detect_edge_done_r[7]), .R(pb_detect_edge_setup)); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_found_edge_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ), .Q(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2 (.I0(p_0_in84_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ), .I3(p_0_in), .O(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .O(\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 )); (* SOFT_HLUTNM = "soft_lutpair217" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4 (.I0(p_0_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .O(\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ), .Q(\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 (.I0(p_0_in), .I1(p_0_in84_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[7]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ), .Q(p_0_in), .R(1'b0)); LUT4 #( .INIT(16'h0008)) idel_adj_inc_i_2 (.I0(out[4]), .I1(out[0]), .I2(cal1_state_r), .I3(out[3]), .O(idel_adj_inc_reg_1)); (* SOFT_HLUTNM = "soft_lutpair222" *) LUT3 #( .INIT(8'hA8)) idel_adj_inc_i_3 (.I0(detect_edge_done_r), .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .O(idel_adj_inc_reg_2)); FDRE #( .INIT(1'b0)) idel_adj_inc_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[2]_0 ), .Q(idel_adj_inc_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT4 #( .INIT(16'h4373)) \idel_dec_cnt[0]_i_1 (.I0(idel_dec_cnt__0[0]), .I1(out[1]), .I2(out[2]), .I3(\idel_dec_cnt[0]_i_2_n_0 ), .O(idel_dec_cnt)); LUT6 #( .INIT(64'h505F3030505F3F3F)) \idel_dec_cnt[0]_i_2 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ), .O(\idel_dec_cnt[0]_i_2_n_0 )); LUT5 #( .INIT(32'h0000E22E)) \idel_dec_cnt[1]_i_1 (.I0(idelay_tap_cnt_r[1]), .I1(out[4]), .I2(idel_dec_cnt__0[0]), .I3(idel_dec_cnt__0[1]), .I4(out[0]), .O(\idel_dec_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000EEE2222E)) \idel_dec_cnt[2]_i_1 (.I0(idelay_tap_cnt_r[2]), .I1(out[4]), .I2(idel_dec_cnt__0[1]), .I3(idel_dec_cnt__0[0]), .I4(idel_dec_cnt__0[2]), .I5(out[0]), .O(\idel_dec_cnt[2]_i_1_n_0 )); LUT5 #( .INIT(32'h00002EE2)) \idel_dec_cnt[3]_i_1 (.I0(idelay_tap_cnt_r[3]), .I1(out[4]), .I2(\idel_dec_cnt[3]_i_2_n_0 ), .I3(idel_dec_cnt__0[3]), .I4(out[0]), .O(\idel_dec_cnt[3]_i_1_n_0 )); LUT3 #( .INIT(8'h01)) \idel_dec_cnt[3]_i_2 (.I0(idel_dec_cnt__0[0]), .I1(idel_dec_cnt__0[1]), .I2(idel_dec_cnt__0[2]), .O(\idel_dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h1000001000404000)) \idel_dec_cnt[4]_i_1 (.I0(\idel_dec_cnt_reg[0]_0 ), .I1(out[0]), .I2(\idel_dec_cnt[4]_i_4_n_0 ), .I3(out[1]), .I4(out[4]), .I5(out[2]), .O(\idel_dec_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'h00002EE2)) \idel_dec_cnt[4]_i_2 (.I0(idelay_tap_cnt_r[4]), .I1(out[4]), .I2(\idel_dec_cnt[4]_i_5_n_0 ), .I3(idel_dec_cnt__0[4]), .I4(out[0]), .O(\idel_dec_cnt[4]_i_2_n_0 )); LUT2 #( .INIT(4'hE)) \idel_dec_cnt[4]_i_3 (.I0(out[3]), .I1(cal1_state_r), .O(\idel_dec_cnt_reg[0]_0 )); LUT6 #( .INIT(64'hB888FFFFB8880000)) \idel_dec_cnt[4]_i_4 (.I0(cal1_state_r2), .I1(out[4]), .I2(mpr_rd_rise0_prev_r_reg_0), .I3(idel_mpr_pat_detect_r), .I4(out[1]), .I5(\idel_dec_cnt[4]_i_7_n_0 ), .O(\idel_dec_cnt[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT4 #( .INIT(16'h0001)) \idel_dec_cnt[4]_i_5 (.I0(idel_dec_cnt__0[2]), .I1(idel_dec_cnt__0[1]), .I2(idel_dec_cnt__0[0]), .I3(idel_dec_cnt__0[3]), .O(\idel_dec_cnt[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT5 #( .INIT(32'hFFFFFFFE)) \idel_dec_cnt[4]_i_6 (.I0(idel_dec_cnt__0[4]), .I1(idel_dec_cnt__0[3]), .I2(idel_dec_cnt__0[0]), .I3(idel_dec_cnt__0[1]), .I4(idel_dec_cnt__0[2]), .O(cal1_state_r2)); LUT6 #( .INIT(64'hA800A800A8FFA800)) \idel_dec_cnt[4]_i_7 (.I0(detect_edge_done_r), .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .I3(out[4]), .I4(stable_idel_cnt22_in), .I5(\idel_dec_cnt[4]_i_8_n_0 ), .O(\idel_dec_cnt[4]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFB)) \idel_dec_cnt[4]_i_8 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I1(mpr_dec_cpt_r_reg_0), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I5(\idel_dec_cnt[4]_i_9_n_0 ), .O(\idel_dec_cnt[4]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair205" *) LUT2 #( .INIT(4'hB)) \idel_dec_cnt[4]_i_9 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .O(\idel_dec_cnt[4]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \idel_dec_cnt_reg[0] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(idel_dec_cnt), .Q(idel_dec_cnt__0[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idel_dec_cnt_reg[1] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[1]_i_1_n_0 ), .Q(idel_dec_cnt__0[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idel_dec_cnt_reg[2] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[2]_i_1_n_0 ), .Q(idel_dec_cnt__0[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idel_dec_cnt_reg[3] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[3]_i_1_n_0 ), .Q(idel_dec_cnt__0[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idel_dec_cnt_reg[4] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[4]_i_2_n_0 ), .Q(idel_dec_cnt__0[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) idel_pat_detect_valid_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_0 ), .Q(mpr_rd_rise0_prev_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT3 #( .INIT(8'h04)) \idelay_tap_cnt_r[0][0][0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(idelay_ce_int), .I2(idelay_tap_cnt_slice_r[0]), .O(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT5 #( .INIT(32'h04404004)) \idelay_tap_cnt_r[0][0][1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(idelay_ce_int), .I2(idelay_tap_cnt_slice_r[0]), .I3(idelay_tap_cnt_slice_r[1]), .I4(idelay_inc_int), .O(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h0444400044400004)) \idelay_tap_cnt_r[0][0][2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(idelay_ce_int), .I2(idelay_inc_int), .I3(idelay_tap_cnt_slice_r[0]), .I4(idelay_tap_cnt_slice_r[2]), .I5(idelay_tap_cnt_slice_r[1]), .O(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h28A0A0A0A0A0A082)) \idelay_tap_cnt_r[0][0][3]_i_1 (.I0(\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ), .I1(idelay_tap_cnt_slice_r[2]), .I2(idelay_tap_cnt_slice_r[3]), .I3(idelay_tap_cnt_slice_r[0]), .I4(idelay_inc_int), .I5(idelay_tap_cnt_slice_r[1]), .O(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT2 #( .INIT(4'h2)) \idelay_tap_cnt_r[0][0][3]_i_2 (.I0(idelay_ce_int), .I1(rstdiv0_sync_r1_reg_rep__22), .O(\idelay_tap_cnt_r[0][0][3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF111111F1)) \idelay_tap_cnt_r[0][0][4]_i_1 (.I0(\po_stg2_wrcal_cnt_reg[0] ), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ), .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT3 #( .INIT(8'h04)) \idelay_tap_cnt_r[0][0][4]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(idelay_ce_int), .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ), .O(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair220" *) LUT3 #( .INIT(8'h10)) \idelay_tap_cnt_r[0][0][4]_i_4 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(idelay_ce_int), .O(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 )); LUT6 #( .INIT(64'h9555555555555556)) \idelay_tap_cnt_r[0][0][4]_i_5 (.I0(idelay_tap_cnt_slice_r[4]), .I1(idelay_tap_cnt_slice_r[0]), .I2(idelay_inc_int), .I3(idelay_tap_cnt_slice_r[1]), .I4(idelay_tap_cnt_slice_r[3]), .I5(idelay_tap_cnt_slice_r[2]), .O(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF1111F111)) \idelay_tap_cnt_r[0][1][4]_i_1 (.I0(cal1_dq_idel_ce_reg_0), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ), .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F444444)) \idelay_tap_cnt_r[0][2][4]_i_1 (.I0(\po_stg2_wrcal_cnt_reg[0] ), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF4444444)) \idelay_tap_cnt_r[0][3][4]_i_1 (.I0(cal1_dq_idel_ce_reg_0), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(idelay_ce_int), .I3(\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ), .I4(cal1_cnt_cpt_r1), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair220" *) LUT2 #( .INIT(4'h1)) \idelay_tap_cnt_r[0][3][4]_i_2 (.I0(\rnk_cnt_r_reg_n_0_[1] ), .I1(\rnk_cnt_r_reg_n_0_[0] ), .O(\idelay_tap_cnt_r[0][3][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT2 #( .INIT(4'h8)) \idelay_tap_cnt_r[0][3][4]_i_3 (.I0(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ), .O(cal1_cnt_cpt_r1)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][0][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][0][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][0][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][0][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][0][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][1][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][1][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][1][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][1][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][1][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][2][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][2][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][2][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][2][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][2][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][3][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][3][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][3][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][3][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_r_reg[0][3][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ), .R(1'b0)); LUT6 #( .INIT(64'hFFE2CCE233E200E2)) \idelay_tap_cnt_slice_r[0]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ), .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I2(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ), .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I4(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ), .O(idelay_tap_cnt_r[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[1]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ), .O(idelay_tap_cnt_r[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[2]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ), .O(idelay_tap_cnt_r[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[3]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ), .O(idelay_tap_cnt_r[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[4]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ), .O(idelay_tap_cnt_r[4])); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_slice_r_reg[0] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[0]), .Q(idelay_tap_cnt_slice_r[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_slice_r_reg[1] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[1]), .Q(idelay_tap_cnt_slice_r[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_slice_r_reg[2] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[2]), .Q(idelay_tap_cnt_slice_r[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_slice_r_reg[3] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[3]), .Q(idelay_tap_cnt_slice_r[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \idelay_tap_cnt_slice_r_reg[4] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[4]), .Q(idelay_tap_cnt_slice_r[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT3 #( .INIT(8'h02)) idelay_tap_limit_r_i_1 (.I0(idelay_tap_limit_r_i_2_n_0), .I1(new_cnt_cpt_r_reg_n_0), .I2(rstdiv0_sync_r1_reg_rep__22), .O(idelay_tap_limit_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40000000)) idelay_tap_limit_r_i_2 (.I0(\idel_dec_cnt[0]_i_2_n_0 ), .I1(idelay_tap_cnt_r[3]), .I2(idelay_tap_cnt_r[4]), .I3(idelay_tap_cnt_r[2]), .I4(idelay_tap_cnt_r[1]), .I5(idelay_tap_limit_r_reg_n_0), .O(idelay_tap_limit_r_i_2_n_0)); FDRE #( .INIT(1'b0)) idelay_tap_limit_r_reg (.C(CLK), .CE(1'b1), .D(idelay_tap_limit_r_i_1_n_0), .Q(idelay_tap_limit_r_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair206" *) LUT3 #( .INIT(8'h54)) \init_state_r[0]_i_37 (.I0(oclkdelay_calib_done_r_reg), .I1(mpr_last_byte_done), .I2(mpr_rdlvl_done_r1_reg_0), .O(\init_state_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000AAFE0000)) \init_state_r[0]_i_38 (.I0(\init_state_r[0]_i_48_n_0 ), .I1(wrlvl_byte_redo), .I2(wrlvl_final_mux), .I3(\init_state_r[0]_i_49_n_0 ), .I4(mem_init_done_r), .I5(prbs_rdlvl_done_reg_rep_0), .O(\init_state_r_reg[0]_2 )); LUT5 #( .INIT(32'h00010000)) \init_state_r[0]_i_44 (.I0(\init_state_r_reg[1]_0 [1]), .I1(mpr_rdlvl_done_r1_reg_0), .I2(mpr_rnk_done), .I3(rdlvl_prech_req), .I4(\init_state_r_reg[1]_0 [0]), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h55FF55FF51FF51F1)) \init_state_r[0]_i_47 (.I0(\init_state_r[0]_i_53_n_0 ), .I1(oclkdelay_calib_done_r_reg), .I2(\init_state_r[0]_i_54_n_0 ), .I3(prbs_rdlvl_done_reg_rep), .I4(rdlvl_stg1_done_r1_reg), .I5(\init_state_r_reg[5] ), .O(\init_state_r_reg[0]_3 )); LUT6 #( .INIT(64'hFFFFFFFF001F0000)) \init_state_r[0]_i_48 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_last_byte_done), .I2(oclkdelay_calib_done_r_reg), .I3(\init_state_r[0]_i_53_n_0 ), .I4(wrlvl_final_mux_reg), .I5(prbs_rdlvl_done_reg_rep_1), .O(\init_state_r[0]_i_48_n_0 )); LUT6 #( .INIT(64'hFF00FF000000FF54)) \init_state_r[0]_i_49 (.I0(prbs_last_byte_done_r), .I1(mpr_last_byte_done), .I2(mpr_rdlvl_done_r1_reg_0), .I3(prbs_rdlvl_done_reg_rep), .I4(wrcal_done_reg), .I5(rdlvl_stg1_done_r1_reg), .O(\init_state_r[0]_i_49_n_0 )); (* SOFT_HLUTNM = "soft_lutpair224" *) LUT3 #( .INIT(8'h01)) \init_state_r[0]_i_52 (.I0(rdlvl_stg1_done_r1_reg), .I1(rdlvl_last_byte_done), .I2(\one_rank.stg1_wr_done_reg ), .O(\init_state_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair213" *) LUT3 #( .INIT(8'h08)) \init_state_r[0]_i_53 (.I0(rdlvl_stg1_done_r1_reg), .I1(oclkdelay_center_calib_done_r_reg), .I2(wrlvl_done_r1), .O(\init_state_r[0]_i_53_n_0 )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT3 #( .INIT(8'h4F)) \init_state_r[0]_i_54 (.I0(rdlvl_stg1_done_r1_reg), .I1(wrcal_done_reg), .I2(dqs_found_done_r_reg), .O(\init_state_r[0]_i_54_n_0 )); (* SOFT_HLUTNM = "soft_lutpair213" *) LUT4 #( .INIT(16'h0080)) \init_state_r[0]_i_57 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(oclkdelay_center_calib_done_r_reg), .I3(wrlvl_done_r1), .O(\init_state_r_reg[0]_4 )); LUT6 #( .INIT(64'h00FFFE0000000000)) \init_state_r[1]_i_38 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_rnk_done), .I2(rdlvl_prech_req), .I3(\init_state_r_reg[1]_0 [0]), .I4(\init_state_r_reg[1]_0 [1]), .I5(\init_state_r_reg[3]_0 ), .O(\init_state_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT5 #( .INIT(32'h7FFFFFFF)) \init_state_r[2]_i_13 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(wrlvl_done_r1), .I3(dqs_found_done_r_reg), .I4(wrcal_done_reg), .O(\init_state_r_reg[2]_2 )); LUT6 #( .INIT(64'hD0FFD0FFD0FFD0D0)) \init_state_r[2]_i_15 (.I0(wrlvl_done_r1_reg), .I1(\init_state_r_reg[2]_0 ), .I2(\init_state_r_reg[2]_1 ), .I3(wrlvl_done_r1_reg_0), .I4(cnt_init_af_done_r), .I5(dqs_found_done_r_reg_0), .O(\init_state_r_reg[2] )); LUT6 #( .INIT(64'hFFFFFFFF74FFFFFF)) \init_state_r[2]_i_28 (.I0(prbs_rdlvl_done_reg_rep), .I1(rdlvl_stg1_done_r1_reg), .I2(wrcal_done_reg), .I3(dqs_found_done_r_reg), .I4(oclkdelay_calib_done_r_reg), .I5(\init_state_r_reg[5] ), .O(\init_state_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair210" *) LUT4 #( .INIT(16'hAAFE)) \init_state_r[3]_i_8 (.I0(wrlvl_byte_redo_reg), .I1(mpr_rdlvl_done_r1_reg_0), .I2(mpr_last_byte_done), .I3(oclkdelay_calib_done_r_reg), .O(\init_state_r_reg[2]_1 )); LUT6 #( .INIT(64'h4040004000000040)) \init_state_r[3]_i_9 (.I0(\num_refresh_reg[1] ), .I1(\init_state_r_reg[5] ), .I2(dqs_found_done_r_reg), .I3(wrcal_done_reg), .I4(rdlvl_stg1_done_r1_reg), .I5(prbs_rdlvl_done_reg_rep), .O(\init_state_r_reg[3] )); LUT6 #( .INIT(64'hB010B010B0100000)) \init_state_r[4]_i_25 (.I0(rdlvl_stg1_done_r1_reg), .I1(wrcal_done_reg), .I2(dqs_found_done_r_reg), .I3(prbs_rdlvl_done_reg_rep), .I4(mpr_last_byte_done), .I5(mpr_rdlvl_done_r1_reg_0), .O(\init_state_r_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair210" *) LUT2 #( .INIT(4'h1)) \init_state_r[5]_i_30 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_last_byte_done), .O(\init_state_r_reg[5] )); LUT5 #( .INIT(32'h00000002)) \mpr_4to1.idel_mpr_pat_detect_r_i_1 (.I0(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ), .I1(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ), .I2(inhibit_edge_detect_r), .I3(p_1_in26_in), .I4(inhibit_edge_detect_r0), .O(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00100000)) \mpr_4to1.idel_mpr_pat_detect_r_i_2 (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ), .I1(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .I4(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ), .I5(idel_mpr_pat_detect_r), .O(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 )); LUT4 #( .INIT(16'h0008)) \mpr_4to1.idel_mpr_pat_detect_r_i_3 (.I0(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ), .I1(mpr_rd_rise0_prev_r_reg_0), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .O(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000100)) \mpr_4to1.idel_mpr_pat_detect_r_i_4 (.I0(out[3]), .I1(cal1_state_r), .I2(out[4]), .I3(out[0]), .I4(out[2]), .I5(out[1]), .O(p_1_in26_in)); FDRE #( .INIT(1'b0)) \mpr_4to1.idel_mpr_pat_detect_r_reg (.C(CLK), .CE(1'b1), .D(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ), .Q(idel_mpr_pat_detect_r), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFB00)) \mpr_4to1.inhibit_edge_detect_r_i_1 (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ), .I1(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ), .I2(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ), .I3(inhibit_edge_detect_r), .I4(inhibit_edge_detect_r0), .O(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \mpr_4to1.inhibit_edge_detect_r_i_2 (.I0(mpr_rd_rise2_prev_r), .I1(mpr_rd_rise1_prev_r), .I2(mpr_rd_rise3_prev_r), .I3(mpr_rd_fall1_prev_r), .I4(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ), .O(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000020000)) \mpr_4to1.inhibit_edge_detect_r_i_3 (.I0(out[1]), .I1(out[3]), .I2(cal1_state_r), .I3(out[4]), .I4(out[0]), .I5(out[2]), .O(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0001)) \mpr_4to1.inhibit_edge_detect_r_i_4 (.I0(idelay_tap_cnt_r[1]), .I1(idelay_tap_cnt_r[2]), .I2(idelay_tap_cnt_r[3]), .I3(idelay_tap_cnt_r[4]), .O(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAABAAAAAA)) \mpr_4to1.inhibit_edge_detect_r_i_5 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ), .I2(mpr_rd_fall2_prev_r), .I3(mpr_rd_rise2_prev_r), .I4(mpr_rd_rise1_prev_r), .I5(mpr_rd_fall0_prev_r), .O(inhibit_edge_detect_r0)); LUT4 #( .INIT(16'hFF7F)) \mpr_4to1.inhibit_edge_detect_r_i_6 (.I0(mpr_rd_fall2_prev_r), .I1(mpr_rd_fall0_prev_r), .I2(mpr_rd_fall3_prev_r), .I3(mpr_rd_rise0_prev_r), .O(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 )); LUT4 #( .INIT(16'hFFDF)) \mpr_4to1.inhibit_edge_detect_r_i_7 (.I0(mpr_rd_rise0_prev_r), .I1(mpr_rd_fall1_prev_r), .I2(mpr_rd_rise3_prev_r), .I3(mpr_rd_fall3_prev_r), .O(\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 )); FDRE #( .INIT(1'b0)) \mpr_4to1.inhibit_edge_detect_r_reg (.C(CLK), .CE(1'b1), .D(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ), .Q(inhibit_edge_detect_r), .R(1'b0)); LUT3 #( .INIT(8'h06)) \mpr_4to1.stable_idel_cnt[0]_i_1 (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I1(stable_idel_cnt), .I2(stable_idel_cnt0), .O(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h006A)) \mpr_4to1.stable_idel_cnt[1]_i_1 (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I1(stable_idel_cnt), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I3(stable_idel_cnt0), .O(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT5 #( .INIT(32'h00006AAA)) \mpr_4to1.stable_idel_cnt[2]_i_1 (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .I1(stable_idel_cnt), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I4(stable_idel_cnt0), .O(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000080)) \mpr_4to1.stable_idel_cnt[2]_i_2 (.I0(stable_idel_cnt22_in), .I1(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ), .I2(mpr_rd_rise0_prev_r_reg_0), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I4(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .I5(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ), .O(stable_idel_cnt)); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT3 #( .INIT(8'hFE)) \mpr_4to1.stable_idel_cnt[2]_i_3 (.I0(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ), .I1(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__22), .O(stable_idel_cnt0)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \mpr_4to1.stable_idel_cnt[2]_i_4 (.I0(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ), .I1(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .I2(mpr_rd_fall0_prev_r), .I3(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .I4(mpr_rd_rise2_prev_r), .I5(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ), .O(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \mpr_4to1.stable_idel_cnt[2]_i_5 (.I0(out[3]), .I1(cal1_state_r), .I2(out[2]), .I3(out[0]), .I4(out[4]), .I5(out[1]), .O(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 )); LUT4 #( .INIT(16'h6FF6)) \mpr_4to1.stable_idel_cnt[2]_i_6 (.I0(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .I1(mpr_rd_fall2_prev_r), .I2(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .I3(mpr_rd_rise1_prev_r), .O(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \mpr_4to1.stable_idel_cnt[2]_i_7 (.I0(mpr_rd_rise0_prev_r), .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .I2(mpr_rd_fall3_prev_r), .I3(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .I4(\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ), .O(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 )); LUT4 #( .INIT(16'h6FF6)) \mpr_4to1.stable_idel_cnt[2]_i_8 (.I0(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .I1(mpr_rd_fall1_prev_r), .I2(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .I3(mpr_rd_rise3_prev_r), .O(\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \mpr_4to1.stable_idel_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ), .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \mpr_4to1.stable_idel_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ), .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \mpr_4to1.stable_idel_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ), .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .R(1'b0)); LUT3 #( .INIT(8'h24)) mpr_dec_cpt_r_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .O(mpr_dec_cpt_r_reg_1)); FDRE #( .INIT(1'b0)) mpr_dec_cpt_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[3]_0 ), .Q(mpr_dec_cpt_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'h0300000000002323)) mpr_last_byte_done_i_2 (.I0(cal1_state_r1), .I1(mpr_rank_done_r_reg_0), .I2(cal1_state_r), .I3(cal1_cnt_cpt_r1), .I4(out[3]), .I5(out[4]), .O(mpr_last_byte_done_reg_0)); FDRE #( .INIT(1'b0)) mpr_last_byte_done_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_1 ), .Q(mpr_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'hFBFFFFFFFFFFFFFF)) mpr_rank_done_r_i_2 (.I0(cal1_state_r), .I1(out[4]), .I2(mpr_rdlvl_done_r1_reg_0), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I5(prech_done), .O(mpr_rank_done_r_reg_1)); LUT5 #( .INIT(32'h7E7EFFFE)) mpr_rank_done_r_i_3 (.I0(out[0]), .I1(out[2]), .I2(out[3]), .I3(cal1_state_r), .I4(out[1]), .O(mpr_rank_done_r_reg_0)); FDRE #( .INIT(1'b0)) mpr_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_2 ), .Q(mpr_rnk_done), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) mpr_rd_fall0_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .Q(mpr_rd_fall0_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rd_fall1_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .Q(mpr_rd_fall1_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rd_fall2_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .Q(mpr_rd_fall2_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rd_fall3_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .Q(mpr_rd_fall3_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rd_rise0_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .Q(mpr_rd_rise0_prev_r), .R(1'b0)); LUT6 #( .INIT(64'h0000300000001000)) mpr_rd_rise1_prev_r_i_1 (.I0(out[1]), .I1(out[3]), .I2(mpr_rd_rise0_prev_r_reg_1), .I3(out[0]), .I4(out[2]), .I5(mpr_rd_rise0_prev_r_reg_0), .O(mpr_rd_rise0_prev_r0)); LUT2 #( .INIT(4'h1)) mpr_rd_rise1_prev_r_i_2 (.I0(cal1_state_r), .I1(out[4]), .O(mpr_rd_rise0_prev_r_reg_1)); FDRE #( .INIT(1'b0)) mpr_rd_rise1_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .Q(mpr_rd_rise1_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rd_rise2_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .Q(mpr_rd_rise2_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rd_rise3_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .Q(mpr_rd_rise3_prev_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rdlvl_done_r1_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r1_reg_0), .Q(mpr_rdlvl_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_rdlvl_done_r2_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r1), .Q(mpr_rdlvl_done_r2), .R(1'b0)); LUT6 #( .INIT(64'h0000000000001000)) mpr_rdlvl_done_r_i_2 (.I0(out[1]), .I1(out[4]), .I2(cal1_state_r), .I3(out[0]), .I4(out[3]), .I5(out[2]), .O(rdlvl_stg1_done_int)); FDRE #( .INIT(1'b0)) mpr_rdlvl_done_r_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r_reg_0), .Q(mpr_rdlvl_done_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) mpr_rdlvl_start_r_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_start_reg), .Q(mpr_rdlvl_start_r), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_valid_r1_reg (.C(CLK), .CE(1'b1), .D(mpr_valid_r1_reg_0), .Q(mpr_valid_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) mpr_valid_r2_reg (.C(CLK), .CE(1'b1), .D(mpr_valid_r1), .Q(mpr_valid_r2), .R(1'b0)); LUT5 #( .INIT(32'h00000008)) mpr_valid_r_i_1 (.I0(mpr_rdlvl_start_reg), .I1(phy_rddata_en_1), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(mpr_rdlvl_done_r1_reg_0), .I4(mpr_valid_r_reg_0), .O(mpr_valid_r)); FDRE #( .INIT(1'b0)) mpr_valid_r_reg (.C(CLK), .CE(1'b1), .D(mpr_valid_r), .Q(mpr_valid_r1_reg_0), .R(1'b0)); LUT6 #( .INIT(64'h4000000000000001)) new_cnt_cpt_r_i_1 (.I0(new_cnt_cpt_r_i_2_n_0), .I1(out[2]), .I2(out[3]), .I3(out[4]), .I4(out[0]), .I5(out[1]), .O(new_cnt_cpt_r)); LUT6 #( .INIT(64'hAAAAFFEFFFFFFFEF)) new_cnt_cpt_r_i_2 (.I0(cal1_state_r), .I1(cal1_state_r1535_out), .I2(rdlvl_stg1_start_reg), .I3(rdlvl_stg1_start_r), .I4(out[4]), .I5(new_cnt_cpt_r82_out), .O(new_cnt_cpt_r_i_2_n_0)); LUT6 #( .INIT(64'h8880AAAAAAAAAAAA)) new_cnt_cpt_r_i_3 (.I0(prech_done), .I1(mpr_rdlvl_done_r1_reg_0), .I2(\rnk_cnt_r_reg_n_0_[0] ), .I3(\rnk_cnt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\cal1_cnt_cpt_r_reg_n_0_[0] ), .O(new_cnt_cpt_r82_out)); FDRE #( .INIT(1'b0)) new_cnt_cpt_r_reg (.C(CLK), .CE(1'b1), .D(new_cnt_cpt_r), .Q(new_cnt_cpt_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT5 #( .INIT(32'h0000EA00)) \phaser_in_gen.phaser_in_i_1 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [1]), .I2(\calib_sel_reg[3] [0]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[3]_1 )); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_10 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_10__0 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_10__1 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_10__2 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[1])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_11 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_11__0 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_11__1 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_11__2 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[0])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_1__0 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [0]), .I2(\calib_sel_reg[3] [1]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[2]_1 )); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_1__1 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [1]), .I2(\calib_sel_reg[3] [0]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'h0000AB00)) \phaser_in_gen.phaser_in_i_1__2 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [1]), .I2(\calib_sel_reg[3] [0]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[0]_1 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[3]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3__0 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[2]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3__1 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[1]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3__2 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[0]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[3] )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4__0 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[2] )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4__1 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[1] )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4__2 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_6 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [5])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_6__0 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [5])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_6__1 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [5])); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_6__2 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[5])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_7 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [4])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_7__0 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [4])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_7__1 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [4])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_7__2 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[4])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_8 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [3])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_8__0 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [3])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_8__1 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [3])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_8__2 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[3])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_9 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [2])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_9__0 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [2])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_9__1 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [2])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_9__2 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[2])); (* SOFT_HLUTNM = "soft_lutpair208" *) LUT2 #( .INIT(4'hE)) pi_cnt_dec_i_2 (.I0(wait_cnt_r_reg__0[2]), .I1(wait_cnt_r_reg__0[3]), .O(pi_cnt_dec_reg_0)); FDRE #( .INIT(1'b0)) pi_cnt_dec_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_r_reg[0]_1 ), .Q(pi_en_stg2_f_timing_reg_0), .R(1'b0)); FDRE #( .INIT(1'b0)) pi_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing), .Q(rdlvl_pi_stg2_f_en), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT2 #( .INIT(4'hE)) pi_en_stg2_f_timing_i_1 (.I0(cal1_dlyce_cpt_r_reg_n_0), .I1(pi_en_stg2_f_timing_reg_0), .O(pi_en_stg2_f_timing_i_1_n_0)); FDRE #( .INIT(1'b0)) pi_en_stg2_f_timing_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing_i_1_n_0), .Q(pi_en_stg2_f_timing), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) pi_fine_dly_dec_done_reg (.C(CLK), .CE(1'b1), .D(fine_dly_dec_done_r2), .Q(pi_fine_dly_dec_done), .R(1'b0)); LUT5 #( .INIT(32'h40404F40)) \pi_rdval_cnt[0]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\pi_rdval_cnt[5]_i_4_n_0 ), .I3(\pi_rdval_cnt_reg[1]_0 ), .I4(pi_rdval_cnt[0]), .O(\pi_rdval_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFB0808FBFB08FB08)) \pi_rdval_cnt[1]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[1] ), .I1(dqs_po_dec_done_r1), .I2(dqs_po_dec_done_r2), .I3(pi_rdval_cnt[1]), .I4(pi_rdval_cnt[0]), .I5(\pi_rdval_cnt_reg[1]_0 ), .O(\pi_rdval_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hB8B8B888888888B8)) \pi_rdval_cnt[2]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[2] ), .I1(\pi_rdval_cnt[5]_i_4_n_0 ), .I2(\pi_rdval_cnt_reg[1]_0 ), .I3(pi_rdval_cnt[1]), .I4(pi_rdval_cnt[0]), .I5(pi_rdval_cnt[2]), .O(\pi_rdval_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0808FB08FB080808)) \pi_rdval_cnt[3]_i_1 (.I0(\calib_sel_reg[3]_0 [1]), .I1(dqs_po_dec_done_r1), .I2(dqs_po_dec_done_r2), .I3(\pi_rdval_cnt_reg[1]_0 ), .I4(\pi_rdval_cnt[3]_i_2_n_0 ), .I5(pi_rdval_cnt[3]), .O(\pi_rdval_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT3 #( .INIT(8'h01)) \pi_rdval_cnt[3]_i_2 (.I0(pi_rdval_cnt[0]), .I1(pi_rdval_cnt[1]), .I2(pi_rdval_cnt[2]), .O(\pi_rdval_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h0808FBFBFB080808)) \pi_rdval_cnt[4]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[4] ), .I1(dqs_po_dec_done_r1), .I2(dqs_po_dec_done_r2), .I3(pi_rdval_cnt[5]), .I4(\pi_rdval_cnt[4]_i_2_n_0 ), .I5(pi_rdval_cnt[4]), .O(\pi_rdval_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT4 #( .INIT(16'h0001)) \pi_rdval_cnt[4]_i_2 (.I0(pi_rdval_cnt[2]), .I1(pi_rdval_cnt[1]), .I2(pi_rdval_cnt[0]), .I3(pi_rdval_cnt[3]), .O(\pi_rdval_cnt[4]_i_2_n_0 )); LUT4 #( .INIT(16'hBBFB)) \pi_rdval_cnt[5]_i_1 (.I0(pi_en_stg2_f_timing_reg_0), .I1(\pi_rdval_cnt_reg[1]_0 ), .I2(dqs_po_dec_done_r1), .I3(dqs_po_dec_done_r2), .O(\pi_rdval_cnt[5]_i_1_n_0 )); LUT5 #( .INIT(32'h40404F40)) \pi_rdval_cnt[5]_i_2 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [4]), .I2(\pi_rdval_cnt[5]_i_4_n_0 ), .I3(pi_rdval_cnt[5]), .I4(\pi_rdval_cnt[5]_i_5_n_0 ), .O(\pi_rdval_cnt[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \pi_rdval_cnt[5]_i_3 (.I0(pi_rdval_cnt[5]), .I1(pi_rdval_cnt[4]), .I2(pi_rdval_cnt[2]), .I3(pi_rdval_cnt[1]), .I4(pi_rdval_cnt[0]), .I5(pi_rdval_cnt[3]), .O(\pi_rdval_cnt_reg[1]_0 )); LUT2 #( .INIT(4'h2)) \pi_rdval_cnt[5]_i_4 (.I0(dqs_po_dec_done_r1), .I1(dqs_po_dec_done_r2), .O(\pi_rdval_cnt[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT5 #( .INIT(32'h00000001)) \pi_rdval_cnt[5]_i_5 (.I0(pi_rdval_cnt[3]), .I1(pi_rdval_cnt[0]), .I2(pi_rdval_cnt[1]), .I3(pi_rdval_cnt[2]), .I4(pi_rdval_cnt[4]), .O(\pi_rdval_cnt[5]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \pi_rdval_cnt_reg[0] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[0]_i_1_n_0 ), .Q(pi_rdval_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \pi_rdval_cnt_reg[1] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[1]_i_1_n_0 ), .Q(pi_rdval_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \pi_rdval_cnt_reg[2] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[2]_i_1_n_0 ), .Q(pi_rdval_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \pi_rdval_cnt_reg[3] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[3]_i_1_n_0 ), .Q(pi_rdval_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \pi_rdval_cnt_reg[4] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[4]_i_1_n_0 ), .Q(pi_rdval_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \pi_rdval_cnt_reg[5] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[5]_i_2_n_0 ), .Q(pi_rdval_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) pi_stg2_f_incdec_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_f_incdec_timing), .Q(rdlvl_pi_stg2_f_incdec), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT4 #( .INIT(16'h0008)) pi_stg2_f_incdec_timing_i_1__0 (.I0(cal1_dlyce_cpt_r_reg_n_0), .I1(cal1_dlyinc_cpt_r_reg_n_0), .I2(pi_en_stg2_f_timing_reg_0), .I3(rstdiv0_sync_r1_reg_rep__22), .O(pi_stg2_f_incdec_timing0)); FDRE #( .INIT(1'b0)) pi_stg2_f_incdec_timing_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_f_incdec_timing0), .Q(pi_stg2_f_incdec_timing), .R(1'b0)); FDRE #( .INIT(1'b0)) pi_stg2_load_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_load_timing), .Q(pi_counter_load_en), .R(1'b0)); FDRE #( .INIT(1'b0)) pi_stg2_load_timing_reg (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt_reg[2]_0 ), .Q(pi_stg2_load_timing), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_reg[0] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[0]), .Q(pi_counter_load_val[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_reg[1] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[1]), .Q(pi_counter_load_val[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_reg[2] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[2]), .Q(pi_counter_load_val[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_reg[3] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[3]), .Q(pi_counter_load_val[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_reg[4] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[4]), .Q(pi_counter_load_val[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_reg[5] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[5]), .Q(pi_counter_load_val[5]), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[0]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ), .O(\pi_stg2_reg_l_timing[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[1]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ), .O(\pi_stg2_reg_l_timing[1]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[2]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ), .O(\pi_stg2_reg_l_timing[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[3]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ), .O(\pi_stg2_reg_l_timing[3]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[4]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ), .O(\pi_stg2_reg_l_timing[4]_i_1_n_0 )); LUT3 #( .INIT(8'hEF)) \pi_stg2_reg_l_timing[5]_i_1 (.I0(\pi_stg2_reg_l_timing_reg[0]_0 ), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(\regl_dqs_cnt_reg[0]_0 ), .O(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[5]_i_2 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ), .O(\pi_stg2_reg_l_timing[5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[0]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[0]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[1]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[1]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_timing_reg[2] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[2]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[2]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_timing_reg[3] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[3]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[3]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_timing_reg[4] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[4]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[4]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \pi_stg2_reg_l_timing_reg[5] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[5]_i_2_n_0 ), .Q(pi_stg2_reg_l_timing[5]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFEFFFEFFFFFFFE)) prech_req_r_i_1 (.I0(rdlvl_prech_req), .I1(wrcal_prech_req), .I2(complex_ocal_ref_req), .I3(prbs_rdlvl_prech_req_reg), .I4(dqs_found_prech_req), .I5(\init_state_r_reg[5]_0 ), .O(prech_req)); FDRE #( .INIT(1'b0)) \rd_mux_sel_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_mux_sel_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[1]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [1]), .O(\rdlvl_cpt_tap_cnt_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[2]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [2]), .O(\rdlvl_cpt_tap_cnt_reg[2] )); LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[4]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [3]), .O(\rdlvl_cpt_tap_cnt_reg[4] )); LUT5 #( .INIT(32'h00000001)) \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I1(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFEFFFFFFFFFFFFF)) \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 (.I0(\cal1_state_r1_reg_n_0_[5] ), .I1(\cal1_state_r1_reg_n_0_[4] ), .I2(\cal1_state_r1_reg_n_0_[2] ), .I3(\cal1_state_r1_reg_n_0_[0] ), .I4(\cal1_state_r1_reg_n_0_[3] ), .I5(\cal1_state_r1_reg_n_0_[1] ), .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 )); LUT5 #( .INIT(32'h00000004)) \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I1(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .O(rdlvl_dqs_tap_cnt_r)); LUT5 #( .INIT(32'h00000002)) \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(\rnk_cnt_r_reg_n_0_[0] ), .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .O(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 )); LUT5 #( .INIT(32'h00020000)) \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(\rnk_cnt_r_reg_n_0_[0] ), .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .O(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][0][0] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][0][1] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][0][2] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][0][3] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][0][4] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][0][5] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][1][0] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][1][1] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][1][2] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][1][3] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][1][4] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][1][5] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][2][0] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][2][1] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][2][2] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][2][3] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][2][4] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][2][5] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][3][0] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][3][1] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][3][2] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][3][3] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][3][4] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) \rdlvl_dqs_tap_cnt_r_reg[0][3][5] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE #( .INIT(1'b0)) rdlvl_last_byte_done_int_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_4 ), .Q(rdlvl_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'hFFFFFFFFCC88FEAA)) rdlvl_pi_incdec_i_2 (.I0(out[3]), .I1(cal1_wait_r), .I2(store_sr_req_r_reg_0), .I3(out[1]), .I4(out[2]), .I5(rdlvl_pi_incdec_i_4_n_0), .O(rdlvl_pi_incdec_reg_0)); LUT6 #( .INIT(64'h000000000000FD0D)) rdlvl_pi_incdec_i_4 (.I0(mpr_rdlvl_start_reg), .I1(mpr_rdlvl_start_r), .I2(cal1_state_r), .I3(cal1_wait_r), .I4(out[1]), .I5(out[4]), .O(rdlvl_pi_incdec_i_4_n_0)); LUT6 #( .INIT(64'h0000000105A5AA05)) rdlvl_pi_incdec_i_5 (.I0(out[4]), .I1(cal1_wait_r), .I2(out[3]), .I3(out[0]), .I4(out[1]), .I5(cal1_state_r), .O(rdlvl_pi_incdec_i_5_n_0)); LUT6 #( .INIT(64'h0000000000001000)) rdlvl_pi_incdec_i_6 (.I0(out[1]), .I1(cal1_state_r), .I2(out[3]), .I3(out[4]), .I4(out[0]), .I5(cal1_wait_r), .O(rdlvl_pi_incdec_i_6_n_0)); FDRE #( .INIT(1'b0)) rdlvl_pi_incdec_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[1]_0 ), .Q(rdlvl_pi_incdec), .R(rstdiv0_sync_r1_reg_rep__14[0])); MUXF7 rdlvl_pi_incdec_reg_i_3 (.I0(rdlvl_pi_incdec_i_5_n_0), .I1(rdlvl_pi_incdec_i_6_n_0), .O(rdlvl_pi_incdec_reg_1), .S(out[2])); FDRE #( .INIT(1'b0)) rdlvl_prech_req_reg (.C(CLK), .CE(1'b1), .D(cal1_prech_req_r_reg_n_0), .Q(rdlvl_prech_req), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'hBFFFFFFFFFFFFFFF)) rdlvl_rank_done_r_i_2 (.I0(cal1_state_r), .I1(out[4]), .I2(mpr_rdlvl_done_r1_reg_0), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I5(prech_done), .O(rdlvl_rank_done_r_reg_0)); FDRE #( .INIT(1'b0)) rdlvl_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_3 ), .Q(rdlvl_stg1_rank_done), .R(rstdiv0_sync_r1_reg_rep__13)); (* syn_maxfan = "30" *) FDRE #( .INIT(1'b0)) rdlvl_stg1_done_int_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r_reg_1), .Q(rdlvl_stg1_done_r1_reg), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) rdlvl_stg1_start_r_reg (.C(CLK), .CE(1'b1), .D(rdlvl_stg1_start_reg), .Q(rdlvl_stg1_start_r), .R(1'b0)); LUT6 #( .INIT(64'h0004FFFFFFFF0000)) \regl_dqs_cnt[0]_i_1 (.I0(\regl_dqs_cnt_r_reg[2]_0 ), .I1(regl_dqs_cnt[1]), .I2(regl_rank_cnt[0]), .I3(regl_rank_cnt[1]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_dqs_cnt[0]), .O(\regl_dqs_cnt[0]_i_1_n_0 )); LUT3 #( .INIT(8'hBA)) \regl_dqs_cnt[1]_i_1 (.I0(\pi_stg2_reg_l_timing_reg[0]_0 ), .I1(mpr_rdlvl_done_r2), .I2(mpr_rdlvl_done_r1), .O(\regl_dqs_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h3337FFFFCCCC0000)) \regl_dqs_cnt[1]_i_2 (.I0(\regl_dqs_cnt_r_reg[2]_0 ), .I1(regl_dqs_cnt[0]), .I2(regl_rank_cnt[0]), .I3(regl_rank_cnt[1]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_dqs_cnt[1]), .O(\regl_dqs_cnt[1]_i_2_n_0 )); LUT5 #( .INIT(32'hAAAAAAAB)) \regl_dqs_cnt[1]_i_3 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[1]), .I4(done_cnt[0]), .O(\pi_stg2_reg_l_timing_reg[0]_0 )); LUT5 #( .INIT(32'h04444444)) \regl_dqs_cnt[2]_i_1 (.I0(\regl_dqs_cnt[1]_i_1_n_0 ), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(regl_dqs_cnt[1]), .I3(regl_dqs_cnt[0]), .I4(\regl_dqs_cnt_reg[0]_0 ), .O(\regl_dqs_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT5 #( .INIT(32'h00000200)) \regl_dqs_cnt[2]_i_2 (.I0(p_0_in539_in), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[0]), .I4(done_cnt[1]), .O(\regl_dqs_cnt_reg[0]_0 )); LUT6 #( .INIT(64'h0000000000020000)) \regl_dqs_cnt[2]_i_3 (.I0(out[1]), .I1(out[0]), .I2(out[4]), .I3(out[3]), .I4(cal1_state_r), .I5(out[2]), .O(p_0_in539_in)); FDRE #( .INIT(1'b0)) \regl_dqs_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(regl_dqs_cnt[0]), .Q(regl_dqs_cnt_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \regl_dqs_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(regl_dqs_cnt[1]), .Q(regl_dqs_cnt_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \regl_dqs_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt_r_reg[2]_0 ), .Q(regl_dqs_cnt_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \regl_dqs_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt[0]_i_1_n_0 ), .Q(regl_dqs_cnt[0]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \regl_dqs_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt[1]_i_2_n_0 ), .Q(regl_dqs_cnt[1]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \regl_dqs_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt[2]_i_1_n_0 ), .Q(\regl_dqs_cnt_r_reg[2]_0 ), .R(1'b0)); LUT6 #( .INIT(64'hCFFFFFFF20000000)) \regl_rank_cnt[0]_i_1 (.I0(regl_rank_cnt[1]), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(regl_dqs_cnt[1]), .I3(regl_dqs_cnt[0]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_rank_cnt[0]), .O(\regl_rank_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hDFFFFFFF20000000)) \regl_rank_cnt[1]_i_1 (.I0(regl_rank_cnt[0]), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(regl_dqs_cnt[1]), .I3(regl_dqs_cnt[0]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_rank_cnt[1]), .O(\regl_rank_cnt[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \regl_rank_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\regl_rank_cnt[0]_i_1_n_0 ), .Q(regl_rank_cnt[0]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \regl_rank_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\regl_rank_cnt[1]_i_1_n_0 ), .Q(regl_rank_cnt[1]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[0]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(out[3]), .O(\right_edge_taps_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[1]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ), .I1(out[3]), .O(\right_edge_taps_r[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[2]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ), .I1(out[3]), .O(\right_edge_taps_r[2]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[3]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(out[3]), .O(\right_edge_taps_r[3]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[4]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ), .I1(out[3]), .O(\right_edge_taps_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888800002000)) \right_edge_taps_r[5]_i_1 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(\right_edge_taps_r_reg[0]_2 ), .I3(found_stable_eye_last_r), .I4(\right_edge_taps_r_reg[0]_0 ), .I5(out[2]), .O(\right_edge_taps_r[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[5]_i_2 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(out[3]), .O(\right_edge_taps_r[5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \right_edge_taps_r_reg[0] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[0]_i_1_n_0 ), .Q(right_edge_taps_r__0[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \right_edge_taps_r_reg[1] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[1]_i_1_n_0 ), .Q(right_edge_taps_r__0[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \right_edge_taps_r_reg[2] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[2]_i_1_n_0 ), .Q(right_edge_taps_r__0[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \right_edge_taps_r_reg[3] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[3]_i_1_n_0 ), .Q(right_edge_taps_r__0[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \right_edge_taps_r_reg[4] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[4]_i_1_n_0 ), .Q(right_edge_taps_r__0[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \right_edge_taps_r_reg[5] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[5]_i_2_n_0 ), .Q(right_edge_taps_r__0[5]), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT3 #( .INIT(8'h34)) \rnk_cnt_r[0]_i_1__0 (.I0(cal1_state_r), .I1(\rnk_cnt_r[1]_i_2_n_0 ), .I2(\rnk_cnt_r_reg_n_0_[0] ), .O(\rnk_cnt_r[0]_i_1__0_n_0 )); LUT4 #( .INIT(16'h1F20)) \rnk_cnt_r[1]_i_1__0 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(cal1_state_r), .I2(\rnk_cnt_r[1]_i_2_n_0 ), .I3(\rnk_cnt_r_reg_n_0_[1] ), .O(\rnk_cnt_r[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h00800A0000000000)) \rnk_cnt_r[1]_i_2 (.I0(out[1]), .I1(\rnk_cnt_r[1]_i_3_n_0 ), .I2(out[3]), .I3(cal1_state_r), .I4(out[4]), .I5(\cal1_cnt_cpt_r[1]_i_5_n_0 ), .O(\rnk_cnt_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hE000000000000000)) \rnk_cnt_r[1]_i_3 (.I0(\rnk_cnt_r_reg_n_0_[1] ), .I1(\rnk_cnt_r_reg_n_0_[0] ), .I2(mpr_rdlvl_done_r1_reg_0), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I5(prech_done), .O(\rnk_cnt_r[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \rnk_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[0]_i_1__0_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE #( .INIT(1'b0)) \rnk_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[1]_i_1__0_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h00000000AAAE0000)) samp_cnt_done_r_i_1 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(samp_cnt_done_r_i_2_n_0), .I2(samp_cnt_done_r_i_3_n_0), .I3(samp_cnt_done_r_i_4_n_0), .I4(samp_edge_cnt0_en_r), .I5(rstdiv0_sync_r1_reg_rep__22), .O(samp_cnt_done_r_i_1_n_0)); LUT4 #( .INIT(16'h0010)) samp_cnt_done_r_i_2 (.I0(samp_edge_cnt1_r_reg[11]), .I1(samp_edge_cnt1_r_reg[7]), .I2(samp_edge_cnt1_r_reg[0]), .I3(samp_edge_cnt1_r_reg[6]), .O(samp_cnt_done_r_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) samp_cnt_done_r_i_3 (.I0(samp_edge_cnt1_r_reg[8]), .I1(samp_edge_cnt1_r_reg[3]), .I2(samp_edge_cnt1_r_reg[1]), .I3(samp_edge_cnt1_r_reg[10]), .O(samp_cnt_done_r_i_3_n_0)); LUT4 #( .INIT(16'hFFFE)) samp_cnt_done_r_i_4 (.I0(samp_edge_cnt1_r_reg[4]), .I1(samp_edge_cnt1_r_reg[9]), .I2(samp_edge_cnt1_r_reg[2]), .I3(samp_edge_cnt1_r_reg[5]), .O(samp_cnt_done_r_i_4_n_0)); FDRE #( .INIT(1'b0)) samp_cnt_done_r_reg (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_i_1_n_0), .Q(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h0100000002003000)) samp_edge_cnt0_en_r_i_1 (.I0(out[1]), .I1(cal1_state_r), .I2(out[4]), .I3(out[0]), .I4(out[2]), .I5(out[3]), .O(pb_detect_edge)); FDRE #( .INIT(1'b0)) samp_edge_cnt0_en_r_reg (.C(CLK), .CE(1'b1), .D(pb_detect_edge), .Q(samp_edge_cnt0_en_r), .R(1'b0)); LUT2 #( .INIT(4'hE)) \samp_edge_cnt0_r[0]_i_2 (.I0(sr_valid_r2), .I1(mpr_valid_r2), .O(samp_edge_cnt0_r0)); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[0]_i_4 (.I0(samp_edge_cnt0_r_reg[3]), .O(\samp_edge_cnt0_r[0]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[0]_i_5 (.I0(samp_edge_cnt0_r_reg[2]), .O(\samp_edge_cnt0_r[0]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[0]_i_6 (.I0(samp_edge_cnt0_r_reg[1]), .O(\samp_edge_cnt0_r[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \samp_edge_cnt0_r[0]_i_7 (.I0(samp_edge_cnt0_r_reg[0]), .O(\samp_edge_cnt0_r[0]_i_7_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_2 (.I0(samp_edge_cnt0_r_reg[7]), .O(\samp_edge_cnt0_r[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_3 (.I0(samp_edge_cnt0_r_reg[6]), .O(\samp_edge_cnt0_r[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_4 (.I0(samp_edge_cnt0_r_reg[5]), .O(\samp_edge_cnt0_r[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_5 (.I0(samp_edge_cnt0_r_reg[4]), .O(\samp_edge_cnt0_r[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_2 (.I0(samp_edge_cnt0_r_reg[11]), .O(\samp_edge_cnt0_r[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_3 (.I0(samp_edge_cnt0_r_reg[10]), .O(\samp_edge_cnt0_r[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_4 (.I0(samp_edge_cnt0_r_reg[9]), .O(\samp_edge_cnt0_r[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_5 (.I0(samp_edge_cnt0_r_reg[8]), .O(\samp_edge_cnt0_r[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[0] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_7 ), .Q(samp_edge_cnt0_r_reg[0]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt0_r_reg[0]_i_3 (.CI(1'b0), .CO({\samp_edge_cnt0_r_reg[0]_i_3_n_0 ,\samp_edge_cnt0_r_reg[0]_i_3_n_1 ,\samp_edge_cnt0_r_reg[0]_i_3_n_2 ,\samp_edge_cnt0_r_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\samp_edge_cnt0_r_reg[0]_i_3_n_4 ,\samp_edge_cnt0_r_reg[0]_i_3_n_5 ,\samp_edge_cnt0_r_reg[0]_i_3_n_6 ,\samp_edge_cnt0_r_reg[0]_i_3_n_7 }), .S({\samp_edge_cnt0_r[0]_i_4_n_0 ,\samp_edge_cnt0_r[0]_i_5_n_0 ,\samp_edge_cnt0_r[0]_i_6_n_0 ,\samp_edge_cnt0_r[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[10] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_5 ), .Q(samp_edge_cnt0_r_reg[10]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[11] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_4 ), .Q(samp_edge_cnt0_r_reg[11]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[1] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_6 ), .Q(samp_edge_cnt0_r_reg[1]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[2] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_5 ), .Q(samp_edge_cnt0_r_reg[2]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[3] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_4 ), .Q(samp_edge_cnt0_r_reg[3]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[4] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_7 ), .Q(samp_edge_cnt0_r_reg[4]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt0_r_reg[4]_i_1 (.CI(\samp_edge_cnt0_r_reg[0]_i_3_n_0 ), .CO({\samp_edge_cnt0_r_reg[4]_i_1_n_0 ,\samp_edge_cnt0_r_reg[4]_i_1_n_1 ,\samp_edge_cnt0_r_reg[4]_i_1_n_2 ,\samp_edge_cnt0_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt0_r_reg[4]_i_1_n_4 ,\samp_edge_cnt0_r_reg[4]_i_1_n_5 ,\samp_edge_cnt0_r_reg[4]_i_1_n_6 ,\samp_edge_cnt0_r_reg[4]_i_1_n_7 }), .S({\samp_edge_cnt0_r[4]_i_2_n_0 ,\samp_edge_cnt0_r[4]_i_3_n_0 ,\samp_edge_cnt0_r[4]_i_4_n_0 ,\samp_edge_cnt0_r[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[5] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_6 ), .Q(samp_edge_cnt0_r_reg[5]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[6] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_5 ), .Q(samp_edge_cnt0_r_reg[6]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[7] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_4 ), .Q(samp_edge_cnt0_r_reg[7]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[8] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_7 ), .Q(samp_edge_cnt0_r_reg[8]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt0_r_reg[8]_i_1 (.CI(\samp_edge_cnt0_r_reg[4]_i_1_n_0 ), .CO({\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt0_r_reg[8]_i_1_n_1 ,\samp_edge_cnt0_r_reg[8]_i_1_n_2 ,\samp_edge_cnt0_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt0_r_reg[8]_i_1_n_4 ,\samp_edge_cnt0_r_reg[8]_i_1_n_5 ,\samp_edge_cnt0_r_reg[8]_i_1_n_6 ,\samp_edge_cnt0_r_reg[8]_i_1_n_7 }), .S({\samp_edge_cnt0_r[8]_i_2_n_0 ,\samp_edge_cnt0_r[8]_i_3_n_0 ,\samp_edge_cnt0_r[8]_i_4_n_0 ,\samp_edge_cnt0_r[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \samp_edge_cnt0_r_reg[9] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_6 ), .Q(samp_edge_cnt0_r_reg[9]), .R(samp_edge_cnt0_en_r_reg_0)); LUT6 #( .INIT(64'h0000000000000002)) samp_edge_cnt1_en_r_i_1 (.I0(samp_edge_cnt1_en_r_i_2_n_0), .I1(samp_edge_cnt1_en_r_i_3_n_0), .I2(samp_edge_cnt0_r_reg[8]), .I3(samp_edge_cnt0_r_reg[7]), .I4(samp_edge_cnt0_r_reg[6]), .I5(samp_edge_cnt0_r_reg[2]), .O(samp_edge_cnt1_en_r0)); LUT6 #( .INIT(64'h0000000000000E00)) samp_edge_cnt1_en_r_i_2 (.I0(sr_valid_r2), .I1(mpr_valid_r2), .I2(samp_edge_cnt0_r_reg[3]), .I3(samp_edge_cnt0_r_reg[0]), .I4(samp_edge_cnt0_r_reg[5]), .I5(samp_edge_cnt0_r_reg[1]), .O(samp_edge_cnt1_en_r_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) samp_edge_cnt1_en_r_i_3 (.I0(samp_edge_cnt0_r_reg[11]), .I1(samp_edge_cnt0_r_reg[4]), .I2(samp_edge_cnt0_r_reg[10]), .I3(samp_edge_cnt0_r_reg[9]), .O(samp_edge_cnt1_en_r_i_3_n_0)); FDRE #( .INIT(1'b0)) samp_edge_cnt1_en_r_reg (.C(CLK), .CE(1'b1), .D(samp_edge_cnt1_en_r0), .Q(samp_edge_cnt1_en_r), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[0]_i_2 (.I0(samp_edge_cnt1_r_reg[3]), .O(\samp_edge_cnt1_r[0]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[0]_i_3 (.I0(samp_edge_cnt1_r_reg[2]), .O(\samp_edge_cnt1_r[0]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[0]_i_4 (.I0(samp_edge_cnt1_r_reg[1]), .O(\samp_edge_cnt1_r[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \samp_edge_cnt1_r[0]_i_5 (.I0(samp_edge_cnt1_r_reg[0]), .O(\samp_edge_cnt1_r[0]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_2 (.I0(samp_edge_cnt1_r_reg[7]), .O(\samp_edge_cnt1_r[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_3 (.I0(samp_edge_cnt1_r_reg[6]), .O(\samp_edge_cnt1_r[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_4 (.I0(samp_edge_cnt1_r_reg[5]), .O(\samp_edge_cnt1_r[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_5 (.I0(samp_edge_cnt1_r_reg[4]), .O(\samp_edge_cnt1_r[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_2 (.I0(samp_edge_cnt1_r_reg[11]), .O(\samp_edge_cnt1_r[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_3 (.I0(samp_edge_cnt1_r_reg[10]), .O(\samp_edge_cnt1_r[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_4 (.I0(samp_edge_cnt1_r_reg[9]), .O(\samp_edge_cnt1_r[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_5 (.I0(samp_edge_cnt1_r_reg[8]), .O(\samp_edge_cnt1_r[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[0] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_7 ), .Q(samp_edge_cnt1_r_reg[0]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt1_r_reg[0]_i_1 (.CI(1'b0), .CO({\samp_edge_cnt1_r_reg[0]_i_1_n_0 ,\samp_edge_cnt1_r_reg[0]_i_1_n_1 ,\samp_edge_cnt1_r_reg[0]_i_1_n_2 ,\samp_edge_cnt1_r_reg[0]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\samp_edge_cnt1_r_reg[0]_i_1_n_4 ,\samp_edge_cnt1_r_reg[0]_i_1_n_5 ,\samp_edge_cnt1_r_reg[0]_i_1_n_6 ,\samp_edge_cnt1_r_reg[0]_i_1_n_7 }), .S({\samp_edge_cnt1_r[0]_i_2_n_0 ,\samp_edge_cnt1_r[0]_i_3_n_0 ,\samp_edge_cnt1_r[0]_i_4_n_0 ,\samp_edge_cnt1_r[0]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[10] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_5 ), .Q(samp_edge_cnt1_r_reg[10]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[11] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_4 ), .Q(samp_edge_cnt1_r_reg[11]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[1] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_6 ), .Q(samp_edge_cnt1_r_reg[1]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[2] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_5 ), .Q(samp_edge_cnt1_r_reg[2]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[3] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_4 ), .Q(samp_edge_cnt1_r_reg[3]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[4] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_7 ), .Q(samp_edge_cnt1_r_reg[4]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt1_r_reg[4]_i_1 (.CI(\samp_edge_cnt1_r_reg[0]_i_1_n_0 ), .CO({\samp_edge_cnt1_r_reg[4]_i_1_n_0 ,\samp_edge_cnt1_r_reg[4]_i_1_n_1 ,\samp_edge_cnt1_r_reg[4]_i_1_n_2 ,\samp_edge_cnt1_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt1_r_reg[4]_i_1_n_4 ,\samp_edge_cnt1_r_reg[4]_i_1_n_5 ,\samp_edge_cnt1_r_reg[4]_i_1_n_6 ,\samp_edge_cnt1_r_reg[4]_i_1_n_7 }), .S({\samp_edge_cnt1_r[4]_i_2_n_0 ,\samp_edge_cnt1_r[4]_i_3_n_0 ,\samp_edge_cnt1_r[4]_i_4_n_0 ,\samp_edge_cnt1_r[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[5] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_6 ), .Q(samp_edge_cnt1_r_reg[5]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[6] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_5 ), .Q(samp_edge_cnt1_r_reg[6]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[7] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_4 ), .Q(samp_edge_cnt1_r_reg[7]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[8] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_7 ), .Q(samp_edge_cnt1_r_reg[8]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt1_r_reg[8]_i_1 (.CI(\samp_edge_cnt1_r_reg[4]_i_1_n_0 ), .CO({\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt1_r_reg[8]_i_1_n_1 ,\samp_edge_cnt1_r_reg[8]_i_1_n_2 ,\samp_edge_cnt1_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt1_r_reg[8]_i_1_n_4 ,\samp_edge_cnt1_r_reg[8]_i_1_n_5 ,\samp_edge_cnt1_r_reg[8]_i_1_n_6 ,\samp_edge_cnt1_r_reg[8]_i_1_n_7 }), .S({\samp_edge_cnt1_r[8]_i_2_n_0 ,\samp_edge_cnt1_r[8]_i_3_n_0 ,\samp_edge_cnt1_r[8]_i_4_n_0 ,\samp_edge_cnt1_r[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \samp_edge_cnt1_r_reg[9] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_6 ), .Q(samp_edge_cnt1_r_reg[9]), .R(samp_edge_cnt0_en_r_reg_0)); LUT1 #( .INIT(2'h1)) \second_edge_taps_r[0]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\second_edge_taps_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT2 #( .INIT(4'h9)) \second_edge_taps_r[1]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ), .I1(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\second_edge_taps_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT3 #( .INIT(8'hA9)) \second_edge_taps_r[2]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\second_edge_taps_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT4 #( .INIT(16'hAAA9)) \second_edge_taps_r[3]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\tap_cnt_cpt_r_reg_n_0_[2] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(\second_edge_taps_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT5 #( .INIT(32'hAAAAAAA9)) \second_edge_taps_r[4]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ), .I1(\tap_cnt_cpt_r_reg_n_0_[3] ), .I2(\tap_cnt_cpt_r_reg_n_0_[1] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .I4(\tap_cnt_cpt_r_reg_n_0_[2] ), .O(\second_edge_taps_r[4]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \second_edge_taps_r[5]_i_1 (.I0(out[3]), .I1(\second_edge_taps_r_reg[5]_0 ), .O(\second_edge_taps_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888820000000)) \second_edge_taps_r[5]_i_2 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(\right_edge_taps_r_reg[0]_2 ), .I3(found_stable_eye_last_r), .I4(\right_edge_taps_r_reg[0]_0 ), .I5(out[2]), .O(\second_edge_taps_r_reg[5]_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \second_edge_taps_r[5]_i_3 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(\tap_cnt_cpt_r_reg_n_0_[4] ), .I2(\tap_cnt_cpt_r_reg_n_0_[2] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .I4(\tap_cnt_cpt_r_reg_n_0_[1] ), .I5(\tap_cnt_cpt_r_reg_n_0_[3] ), .O(\second_edge_taps_r[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \second_edge_taps_r_reg[0] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[0]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[0] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \second_edge_taps_r_reg[1] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[1]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[1] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \second_edge_taps_r_reg[2] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[2]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[2] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \second_edge_taps_r_reg[3] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[3]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[3] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \second_edge_taps_r_reg[4] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[4]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[4] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \second_edge_taps_r_reg[5] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[5]_i_3_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[5] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) sr_valid_r1_reg (.C(CLK), .CE(1'b1), .D(sr_valid_r1_reg_0), .Q(sr_valid_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) sr_valid_r2_reg (.C(CLK), .CE(1'b1), .D(sr_valid_r1), .Q(sr_valid_r2), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT4 #( .INIT(16'hFFFE)) sr_valid_r_i_2 (.I0(cnt_shift_r_reg__0[0]), .I1(cnt_shift_r_reg__0[1]), .I2(cnt_shift_r_reg__0[3]), .I3(cnt_shift_r_reg__0[2]), .O(mpr_valid_r_reg_0)); FDRE #( .INIT(1'b0)) sr_valid_r_reg (.C(CLK), .CE(1'b1), .D(sr_valid_r108_out), .Q(sr_valid_r1_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair224" *) LUT3 #( .INIT(8'h45)) \stg1_wr_rd_cnt[4]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(rdlvl_stg1_done_r1_reg), .I2(stg1_wr_done), .O(\stg1_wr_rd_cnt_reg[3] )); FDRE #( .INIT(1'b0)) store_sr_r_reg (.C(CLK), .CE(1'b1), .D(store_sr_req_r_reg_1), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000100000000000)) store_sr_req_pulsed_r_i_1 (.I0(cal1_state_r), .I1(out[2]), .I2(out[1]), .I3(out[0]), .I4(out[3]), .I5(out[4]), .O(store_sr_req_pulsed_r)); FDRE #( .INIT(1'b0)) store_sr_req_pulsed_r_reg (.C(CLK), .CE(1'b1), .D(store_sr_req_pulsed_r), .Q(store_sr_req_pulsed_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000000288880002)) store_sr_req_r_i_1 (.I0(store_sr_req_r_i_2_n_0), .I1(out[4]), .I2(cal1_wait_r), .I3(store_sr_req_r_reg_0), .I4(out[0]), .I5(store_sr_req_pulsed_r_reg_n_0), .O(store_sr_req_r)); LUT4 #( .INIT(16'h0010)) store_sr_req_r_i_2 (.I0(cal1_state_r), .I1(out[3]), .I2(out[1]), .I3(out[2]), .O(store_sr_req_r_i_2_n_0)); FDRE #( .INIT(1'b0)) store_sr_req_r_reg (.C(CLK), .CE(1'b1), .D(store_sr_req_r), .Q(store_sr_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); (* SOFT_HLUTNM = "soft_lutpair207" *) LUT3 #( .INIT(8'h69)) \tap_cnt_cpt_r[1]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\tap_cnt_cpt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT4 #( .INIT(16'h6CC9)) \tap_cnt_cpt_r[2]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[2] ), .I2(\tap_cnt_cpt_r_reg_n_0_[1] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT5 #( .INIT(32'h6CCCCCC9)) \tap_cnt_cpt_r[3]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[3] ), .I2(\tap_cnt_cpt_r_reg_n_0_[2] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .I4(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(p_0_in__0[3])); LUT6 #( .INIT(64'h6CCCCCCCCCCCCCC9)) \tap_cnt_cpt_r[4]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[4] ), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .I4(\tap_cnt_cpt_r_reg_n_0_[0] ), .I5(\tap_cnt_cpt_r_reg_n_0_[2] ), .O(p_0_in__0[4])); LUT4 #( .INIT(16'hFFF4)) \tap_cnt_cpt_r[5]_i_1 (.I0(mpr_rdlvl_done_r2), .I1(mpr_rdlvl_done_r1), .I2(new_cnt_cpt_r_reg_n_0), .I3(rstdiv0_sync_r1_reg_rep__22), .O(tap_cnt_cpt_r0)); LUT4 #( .INIT(16'hAA8A)) \tap_cnt_cpt_r[5]_i_2 (.I0(cal1_dlyce_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[5] ), .I2(\tap_cnt_cpt_r[5]_i_4_n_0 ), .I3(cal1_dlyinc_cpt_r_reg_n_0), .O(tap_cnt_cpt_r)); LUT4 #( .INIT(16'h6F60)) \tap_cnt_cpt_r[5]_i_3 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(tap_limit_cpt_r_i_2_n_0), .I2(cal1_dlyinc_cpt_r_reg_n_0), .I3(\second_edge_taps_r[5]_i_3_n_0 ), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT5 #( .INIT(32'h00000001)) \tap_cnt_cpt_r[5]_i_4 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(\tap_cnt_cpt_r_reg_n_0_[2] ), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .O(\tap_cnt_cpt_r[5]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \tap_cnt_cpt_r_reg[0] (.C(CLK), .CE(tap_cnt_cpt_r), .D(\second_edge_taps_r[0]_i_1_n_0 ), .Q(\tap_cnt_cpt_r_reg_n_0_[0] ), .R(tap_cnt_cpt_r0)); FDRE #( .INIT(1'b0)) \tap_cnt_cpt_r_reg[1] (.C(CLK), .CE(tap_cnt_cpt_r), .D(\tap_cnt_cpt_r[1]_i_1_n_0 ), .Q(\tap_cnt_cpt_r_reg_n_0_[1] ), .R(tap_cnt_cpt_r0)); FDRE #( .INIT(1'b0)) \tap_cnt_cpt_r_reg[2] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[2]), .Q(\tap_cnt_cpt_r_reg_n_0_[2] ), .R(tap_cnt_cpt_r0)); FDRE #( .INIT(1'b0)) \tap_cnt_cpt_r_reg[3] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[3]), .Q(\tap_cnt_cpt_r_reg_n_0_[3] ), .R(tap_cnt_cpt_r0)); FDRE #( .INIT(1'b0)) \tap_cnt_cpt_r_reg[4] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[4]), .Q(\tap_cnt_cpt_r_reg_n_0_[4] ), .R(tap_cnt_cpt_r0)); FDRE #( .INIT(1'b0)) \tap_cnt_cpt_r_reg[5] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[5]), .Q(\tap_cnt_cpt_r_reg_n_0_[5] ), .R(tap_cnt_cpt_r0)); LUT5 #( .INIT(32'h000000EA)) tap_limit_cpt_r_i_1 (.I0(tap_limit_cpt_r), .I1(tap_limit_cpt_r_i_2_n_0), .I2(\tap_cnt_cpt_r_reg_n_0_[5] ), .I3(tap_limit_cpt_r_i_3_n_0), .I4(tap_cnt_cpt_r0), .O(tap_limit_cpt_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT5 #( .INIT(32'h80000000)) tap_limit_cpt_r_i_2 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(\tap_cnt_cpt_r_reg_n_0_[2] ), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .O(tap_limit_cpt_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000010)) tap_limit_cpt_r_i_3 (.I0(\cal1_state_r1_reg_n_0_[5] ), .I1(\cal1_state_r1_reg_n_0_[4] ), .I2(\cal1_state_r1_reg_n_0_[2] ), .I3(\cal1_state_r1_reg_n_0_[0] ), .I4(\cal1_state_r1_reg_n_0_[3] ), .I5(\cal1_state_r1_reg_n_0_[1] ), .O(tap_limit_cpt_r_i_3_n_0)); FDRE #( .INIT(1'b0)) tap_limit_cpt_r_reg (.C(CLK), .CE(1'b1), .D(tap_limit_cpt_r_i_1_n_0), .Q(tap_limit_cpt_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wait_cnt_r[0]_i_1__1 (.I0(\wait_cnt_r_reg[0]_0 [0]), .O(wait_cnt_r0__0[0])); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT2 #( .INIT(4'h9)) \wait_cnt_r[1]_i_1__1 (.I0(\wait_cnt_r_reg[0]_0 [1]), .I1(\wait_cnt_r_reg[0]_0 [0]), .O(\wait_cnt_r[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT3 #( .INIT(8'hA9)) \wait_cnt_r[2]_i_1__0 (.I0(wait_cnt_r_reg__0[2]), .I1(\wait_cnt_r_reg[0]_0 [0]), .I2(\wait_cnt_r_reg[0]_0 [1]), .O(wait_cnt_r0__0[2])); LUT5 #( .INIT(32'hAAAAAAA8)) \wait_cnt_r[3]_i_2__1 (.I0(dqs_po_dec_done_r2), .I1(wait_cnt_r_reg__0[2]), .I2(wait_cnt_r_reg__0[3]), .I3(\wait_cnt_r_reg[0]_0 [1]), .I4(\wait_cnt_r_reg[0]_0 [0]), .O(wait_cnt_r0)); (* SOFT_HLUTNM = "soft_lutpair208" *) LUT4 #( .INIT(16'hAAA9)) \wait_cnt_r[3]_i_3 (.I0(wait_cnt_r_reg__0[3]), .I1(wait_cnt_r_reg__0[2]), .I2(\wait_cnt_r_reg[0]_0 [1]), .I3(\wait_cnt_r_reg[0]_0 [0]), .O(wait_cnt_r0__0[3])); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[0] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0[0]), .Q(\wait_cnt_r_reg[0]_0 [0]), .R(pi_cnt_dec_reg_1)); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[1] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[1]_i_1__1_n_0 ), .Q(\wait_cnt_r_reg[0]_0 [1]), .R(pi_cnt_dec_reg_1)); FDRE #( .INIT(1'b0)) \wait_cnt_r_reg[2] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0[2]), .Q(wait_cnt_r_reg__0[2]), .R(pi_cnt_dec_reg_1)); FDSE #( .INIT(1'b1)) \wait_cnt_r_reg[3] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0[3]), .Q(wait_cnt_r_reg__0[3]), .S(pi_cnt_dec_reg_1)); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT4 #( .INIT(16'h7FFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_1 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(oclkdelay_calib_done_r_reg), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] )); LUT5 #( .INIT(32'hDFDF0FFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[56]_i_1 (.I0(rdlvl_stg1_done_r1_reg), .I1(\dout_o_reg[6]_0 ), .I2(oclkdelay_calib_done_r_reg), .I3(first_wrcal_pat_r), .I4(wrcal_done_reg), .O(D[0])); LUT5 #( .INIT(32'hDFDF0FFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[60]_i_1 (.I0(rdlvl_stg1_done_r1_reg), .I1(\dout_o_reg[6] ), .I2(oclkdelay_calib_done_r_reg), .I3(first_wrcal_pat_r), .I4(wrcal_done_reg), .O(D[1])); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_tempmon" *) module ddr3_ifmig_7series_v4_0_ddr_phy_tempmon (tempmon_pi_f_inc, tempmon_sel_pi_incdec, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , D, \calib_zero_inputs_reg[1] , \calib_zero_inputs_reg[1]_0 , \gen_byte_sel_div1.calib_in_common_reg , CLK, SS, tempmon_sample_en, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__6, oclkdelay_calib_done_r_reg, ck_addr_cmd_delay_done, ctl_lane_sel, rstdiv0_sync_r1_reg_rep__24, calib_complete, cmd_delay_start0, delay_done_r4_reg, calib_in_common, fine_adjust_done_r_reg, rd_data_offset_cal_done, rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__7); output tempmon_pi_f_inc; output tempmon_sel_pi_incdec; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output [0:0]D; output [0:0]\calib_zero_inputs_reg[1] ; output \calib_zero_inputs_reg[1]_0 ; output \gen_byte_sel_div1.calib_in_common_reg ; input CLK; input [0:0]SS; input tempmon_sample_en; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__6; input oclkdelay_calib_done_r_reg; input ck_addr_cmd_delay_done; input ctl_lane_sel; input rstdiv0_sync_r1_reg_rep__24; input calib_complete; input cmd_delay_start0; input delay_done_r4_reg; input calib_in_common; input fine_adjust_done_r_reg; input rd_data_offset_cal_done; input [0:0]rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input [0:0]rstdiv0_sync_r1_reg_rep__7; wire CLK; wire [0:0]D; wire [0:0]SS; wire calib_complete; wire calib_in_common; wire [0:0]\calib_zero_inputs_reg[1] ; wire \calib_zero_inputs_reg[1]_0 ; wire ck_addr_cmd_delay_done; wire cmd_delay_start0; wire ctl_lane_sel; wire delay_done_r4_reg; wire [11:0]device_temp_101; wire [11:0]device_temp_init; wire \device_temp_init[11]_i_2_n_0 ; wire \device_temp_init[11]_i_3_n_0 ; wire [11:0]\device_temp_r_reg[11] ; wire fine_adjust_done_r_reg; wire [11:0]four_dec_min_limit; wire \four_dec_min_limit[11]_i_2_n_0 ; wire \four_dec_min_limit[11]_i_3_n_0 ; wire \four_dec_min_limit[5]_i_2_n_0 ; wire \four_dec_min_limit[5]_i_3_n_0 ; wire \four_dec_min_limit[5]_i_4_n_0 ; wire \four_dec_min_limit[5]_i_5_n_0 ; wire \four_dec_min_limit[9]_i_2_n_0 ; wire \four_dec_min_limit[9]_i_3_n_0 ; wire \four_dec_min_limit[9]_i_4_n_0 ; wire \four_dec_min_limit[9]_i_5_n_0 ; wire [11:2]four_dec_min_limit_nxt; wire \four_dec_min_limit_reg[11]_i_1_n_3 ; wire \four_dec_min_limit_reg[5]_i_1_n_0 ; wire \four_dec_min_limit_reg[5]_i_1_n_1 ; wire \four_dec_min_limit_reg[5]_i_1_n_2 ; wire \four_dec_min_limit_reg[5]_i_1_n_3 ; wire \four_dec_min_limit_reg[9]_i_1_n_0 ; wire \four_dec_min_limit_reg[9]_i_1_n_1 ; wire \four_dec_min_limit_reg[9]_i_1_n_2 ; wire \four_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]four_inc_max_limit; wire \four_inc_max_limit[11]_i_2_n_0 ; wire \four_inc_max_limit[11]_i_3_n_0 ; wire \four_inc_max_limit[11]_i_4_n_0 ; wire \four_inc_max_limit[1]_i_2_n_0 ; wire \four_inc_max_limit[4]_i_2_n_0 ; wire \four_inc_max_limit[4]_i_3_n_0 ; wire \four_inc_max_limit[4]_i_4_n_0 ; wire \four_inc_max_limit[4]_i_5_n_0 ; wire \four_inc_max_limit[8]_i_2_n_0 ; wire \four_inc_max_limit[8]_i_3_n_0 ; wire \four_inc_max_limit[8]_i_4_n_0 ; wire \four_inc_max_limit[8]_i_5_n_0 ; wire [11:1]four_inc_max_limit_nxt; wire \four_inc_max_limit_reg[11]_i_1_n_2 ; wire \four_inc_max_limit_reg[11]_i_1_n_3 ; wire \four_inc_max_limit_reg[4]_i_1_n_0 ; wire \four_inc_max_limit_reg[4]_i_1_n_1 ; wire \four_inc_max_limit_reg[4]_i_1_n_2 ; wire \four_inc_max_limit_reg[4]_i_1_n_3 ; wire \four_inc_max_limit_reg[8]_i_1_n_0 ; wire \four_inc_max_limit_reg[8]_i_1_n_1 ; wire \four_inc_max_limit_reg[8]_i_1_n_2 ; wire \four_inc_max_limit_reg[8]_i_1_n_3 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [11:1]neutral_max_limit; wire \neutral_max_limit[11]_i_2_n_0 ; wire \neutral_max_limit[11]_i_3_n_0 ; wire \neutral_max_limit[11]_i_4_n_0 ; wire \neutral_max_limit[4]_i_2_n_0 ; wire \neutral_max_limit[4]_i_3_n_0 ; wire \neutral_max_limit[4]_i_4_n_0 ; wire \neutral_max_limit[4]_i_5_n_0 ; wire \neutral_max_limit[8]_i_2_n_0 ; wire \neutral_max_limit[8]_i_3_n_0 ; wire \neutral_max_limit[8]_i_4_n_0 ; wire \neutral_max_limit[8]_i_5_n_0 ; wire [11:1]neutral_max_limit_nxt; wire \neutral_max_limit_reg[11]_i_1_n_2 ; wire \neutral_max_limit_reg[11]_i_1_n_3 ; wire \neutral_max_limit_reg[4]_i_1_n_0 ; wire \neutral_max_limit_reg[4]_i_1_n_1 ; wire \neutral_max_limit_reg[4]_i_1_n_2 ; wire \neutral_max_limit_reg[4]_i_1_n_3 ; wire \neutral_max_limit_reg[8]_i_1_n_0 ; wire \neutral_max_limit_reg[8]_i_1_n_1 ; wire \neutral_max_limit_reg[8]_i_1_n_2 ; wire \neutral_max_limit_reg[8]_i_1_n_3 ; wire [11:1]neutral_min_limit; wire \neutral_min_limit[11]_i_2_n_0 ; wire \neutral_min_limit[11]_i_3_n_0 ; wire \neutral_min_limit[5]_i_2_n_0 ; wire \neutral_min_limit[5]_i_3_n_0 ; wire \neutral_min_limit[5]_i_4_n_0 ; wire \neutral_min_limit[5]_i_5_n_0 ; wire \neutral_min_limit[9]_i_2_n_0 ; wire \neutral_min_limit[9]_i_3_n_0 ; wire \neutral_min_limit[9]_i_4_n_0 ; wire \neutral_min_limit[9]_i_5_n_0 ; wire [11:2]neutral_min_limit_nxt; wire \neutral_min_limit_reg[11]_i_1_n_3 ; wire \neutral_min_limit_reg[5]_i_1_n_0 ; wire \neutral_min_limit_reg[5]_i_1_n_1 ; wire \neutral_min_limit_reg[5]_i_1_n_2 ; wire \neutral_min_limit_reg[5]_i_1_n_3 ; wire \neutral_min_limit_reg[9]_i_1_n_0 ; wire \neutral_min_limit_reg[9]_i_1_n_1 ; wire \neutral_min_limit_reg[9]_i_1_n_2 ; wire \neutral_min_limit_reg[9]_i_1_n_3 ; wire oclkdelay_calib_done_r_reg; wire [11:1]one_dec_max_limit; wire \one_dec_max_limit[11]_i_2_n_0 ; wire \one_dec_max_limit[11]_i_3_n_0 ; wire \one_dec_max_limit[11]_i_4_n_0 ; wire \one_dec_max_limit[4]_i_2_n_0 ; wire \one_dec_max_limit[4]_i_3_n_0 ; wire \one_dec_max_limit[4]_i_4_n_0 ; wire \one_dec_max_limit[4]_i_5_n_0 ; wire \one_dec_max_limit[8]_i_2_n_0 ; wire \one_dec_max_limit[8]_i_3_n_0 ; wire \one_dec_max_limit[8]_i_4_n_0 ; wire \one_dec_max_limit[8]_i_5_n_0 ; wire [11:1]one_dec_max_limit_nxt; wire \one_dec_max_limit_reg[11]_i_1_n_2 ; wire \one_dec_max_limit_reg[11]_i_1_n_3 ; wire \one_dec_max_limit_reg[4]_i_1_n_0 ; wire \one_dec_max_limit_reg[4]_i_1_n_1 ; wire \one_dec_max_limit_reg[4]_i_1_n_2 ; wire \one_dec_max_limit_reg[4]_i_1_n_3 ; wire \one_dec_max_limit_reg[8]_i_1_n_0 ; wire \one_dec_max_limit_reg[8]_i_1_n_1 ; wire \one_dec_max_limit_reg[8]_i_1_n_2 ; wire \one_dec_max_limit_reg[8]_i_1_n_3 ; wire [11:1]one_dec_min_limit; wire \one_dec_min_limit[11]_i_2_n_0 ; wire \one_dec_min_limit[11]_i_3_n_0 ; wire \one_dec_min_limit[5]_i_2_n_0 ; wire \one_dec_min_limit[5]_i_3_n_0 ; wire \one_dec_min_limit[5]_i_4_n_0 ; wire \one_dec_min_limit[5]_i_5_n_0 ; wire \one_dec_min_limit[9]_i_2_n_0 ; wire \one_dec_min_limit[9]_i_3_n_0 ; wire \one_dec_min_limit[9]_i_4_n_0 ; wire \one_dec_min_limit[9]_i_5_n_0 ; wire [11:2]one_dec_min_limit_nxt; wire \one_dec_min_limit_reg[11]_i_1_n_3 ; wire \one_dec_min_limit_reg[5]_i_1_n_0 ; wire \one_dec_min_limit_reg[5]_i_1_n_1 ; wire \one_dec_min_limit_reg[5]_i_1_n_2 ; wire \one_dec_min_limit_reg[5]_i_1_n_3 ; wire \one_dec_min_limit_reg[9]_i_1_n_0 ; wire \one_dec_min_limit_reg[9]_i_1_n_1 ; wire \one_dec_min_limit_reg[9]_i_1_n_2 ; wire \one_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]one_inc_max_limit; wire \one_inc_max_limit[11]_i_2_n_0 ; wire \one_inc_max_limit[11]_i_3_n_0 ; wire \one_inc_max_limit[11]_i_4_n_0 ; wire \one_inc_max_limit[4]_i_2_n_0 ; wire \one_inc_max_limit[4]_i_3_n_0 ; wire \one_inc_max_limit[4]_i_4_n_0 ; wire \one_inc_max_limit[4]_i_5_n_0 ; wire \one_inc_max_limit[8]_i_2_n_0 ; wire \one_inc_max_limit[8]_i_3_n_0 ; wire \one_inc_max_limit[8]_i_4_n_0 ; wire \one_inc_max_limit[8]_i_5_n_0 ; wire [11:1]one_inc_max_limit_nxt; wire \one_inc_max_limit_reg[11]_i_1_n_2 ; wire \one_inc_max_limit_reg[11]_i_1_n_3 ; wire \one_inc_max_limit_reg[4]_i_1_n_0 ; wire \one_inc_max_limit_reg[4]_i_1_n_1 ; wire \one_inc_max_limit_reg[4]_i_1_n_2 ; wire \one_inc_max_limit_reg[4]_i_1_n_3 ; wire \one_inc_max_limit_reg[8]_i_1_n_0 ; wire \one_inc_max_limit_reg[8]_i_1_n_1 ; wire \one_inc_max_limit_reg[8]_i_1_n_2 ; wire \one_inc_max_limit_reg[8]_i_1_n_3 ; wire [11:1]one_inc_min_limit; wire \one_inc_min_limit[11]_i_2_n_0 ; wire \one_inc_min_limit[11]_i_3_n_0 ; wire \one_inc_min_limit[5]_i_2_n_0 ; wire \one_inc_min_limit[5]_i_3_n_0 ; wire \one_inc_min_limit[5]_i_4_n_0 ; wire \one_inc_min_limit[5]_i_5_n_0 ; wire \one_inc_min_limit[9]_i_2_n_0 ; wire \one_inc_min_limit[9]_i_3_n_0 ; wire \one_inc_min_limit[9]_i_4_n_0 ; wire \one_inc_min_limit[9]_i_5_n_0 ; wire [11:2]one_inc_min_limit_nxt; wire \one_inc_min_limit_reg[11]_i_1_n_3 ; wire \one_inc_min_limit_reg[5]_i_1_n_0 ; wire \one_inc_min_limit_reg[5]_i_1_n_1 ; wire \one_inc_min_limit_reg[5]_i_1_n_2 ; wire \one_inc_min_limit_reg[5]_i_1_n_3 ; wire \one_inc_min_limit_reg[9]_i_1_n_0 ; wire \one_inc_min_limit_reg[9]_i_1_n_1 ; wire \one_inc_min_limit_reg[9]_i_1_n_2 ; wire \one_inc_min_limit_reg[9]_i_1_n_3 ; wire p_0_in; wire pi_f_dec_i_2_n_0; wire pi_f_dec_nxt; wire pi_f_inc_i_10_n_0; wire pi_f_inc_i_2_n_0; wire pi_f_inc_i_3_n_0; wire pi_f_inc_i_5_n_0; wire pi_f_inc_i_6_n_0; wire pi_f_inc_i_7_n_0; wire pi_f_inc_i_8_n_0; wire pi_f_inc_i_9_n_0; wire pi_f_inc_nxt; wire rd_data_offset_cal_done; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__24; wire [0:0]rstdiv0_sync_r1_reg_rep__4; wire rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire [0:0]rstdiv0_sync_r1_reg_rep__7; wire temp_cmp_four_dec_min_101; wire temp_cmp_four_dec_min_102; wire temp_cmp_four_dec_min_102_i_10_n_0; wire temp_cmp_four_dec_min_102_i_11_n_0; wire temp_cmp_four_dec_min_102_i_12_n_0; wire temp_cmp_four_dec_min_102_i_13_n_0; wire temp_cmp_four_dec_min_102_i_14_n_0; wire temp_cmp_four_dec_min_102_i_3_n_0; wire temp_cmp_four_dec_min_102_i_4_n_0; wire temp_cmp_four_dec_min_102_i_5_n_0; wire temp_cmp_four_dec_min_102_i_6_n_0; wire temp_cmp_four_dec_min_102_i_7_n_0; wire temp_cmp_four_dec_min_102_i_8_n_0; wire temp_cmp_four_dec_min_102_i_9_n_0; wire temp_cmp_four_dec_min_102_reg_i_1_n_3; wire temp_cmp_four_dec_min_102_reg_i_2_n_0; wire temp_cmp_four_dec_min_102_reg_i_2_n_1; wire temp_cmp_four_dec_min_102_reg_i_2_n_2; wire temp_cmp_four_dec_min_102_reg_i_2_n_3; wire temp_cmp_four_inc_max_101; wire temp_cmp_four_inc_max_102; wire temp_cmp_four_inc_max_102_i_10_n_0; wire temp_cmp_four_inc_max_102_i_11_n_0; wire temp_cmp_four_inc_max_102_i_12_n_0; wire temp_cmp_four_inc_max_102_i_13_n_0; wire temp_cmp_four_inc_max_102_i_14_n_0; wire temp_cmp_four_inc_max_102_i_3_n_0; wire temp_cmp_four_inc_max_102_i_4_n_0; wire temp_cmp_four_inc_max_102_i_5_n_0; wire temp_cmp_four_inc_max_102_i_6_n_0; wire temp_cmp_four_inc_max_102_i_7_n_0; wire temp_cmp_four_inc_max_102_i_8_n_0; wire temp_cmp_four_inc_max_102_i_9_n_0; wire temp_cmp_four_inc_max_102_reg_i_1_n_3; wire temp_cmp_four_inc_max_102_reg_i_2_n_0; wire temp_cmp_four_inc_max_102_reg_i_2_n_1; wire temp_cmp_four_inc_max_102_reg_i_2_n_2; wire temp_cmp_four_inc_max_102_reg_i_2_n_3; wire temp_cmp_neutral_max_101; wire temp_cmp_neutral_max_102; wire temp_cmp_neutral_max_102_i_10_n_0; wire temp_cmp_neutral_max_102_i_11_n_0; wire temp_cmp_neutral_max_102_i_12_n_0; wire temp_cmp_neutral_max_102_i_13_n_0; wire temp_cmp_neutral_max_102_i_14_n_0; wire temp_cmp_neutral_max_102_i_3_n_0; wire temp_cmp_neutral_max_102_i_4_n_0; wire temp_cmp_neutral_max_102_i_5_n_0; wire temp_cmp_neutral_max_102_i_6_n_0; wire temp_cmp_neutral_max_102_i_7_n_0; wire temp_cmp_neutral_max_102_i_8_n_0; wire temp_cmp_neutral_max_102_i_9_n_0; wire temp_cmp_neutral_max_102_reg_i_1_n_3; wire temp_cmp_neutral_max_102_reg_i_2_n_0; wire temp_cmp_neutral_max_102_reg_i_2_n_1; wire temp_cmp_neutral_max_102_reg_i_2_n_2; wire temp_cmp_neutral_max_102_reg_i_2_n_3; wire temp_cmp_neutral_min_101; wire temp_cmp_neutral_min_102; wire temp_cmp_neutral_min_102_i_10_n_0; wire temp_cmp_neutral_min_102_i_11_n_0; wire temp_cmp_neutral_min_102_i_12_n_0; wire temp_cmp_neutral_min_102_i_13_n_0; wire temp_cmp_neutral_min_102_i_14_n_0; wire temp_cmp_neutral_min_102_i_3_n_0; wire temp_cmp_neutral_min_102_i_4_n_0; wire temp_cmp_neutral_min_102_i_5_n_0; wire temp_cmp_neutral_min_102_i_6_n_0; wire temp_cmp_neutral_min_102_i_7_n_0; wire temp_cmp_neutral_min_102_i_8_n_0; wire temp_cmp_neutral_min_102_i_9_n_0; wire temp_cmp_neutral_min_102_reg_i_1_n_3; wire temp_cmp_neutral_min_102_reg_i_2_n_0; wire temp_cmp_neutral_min_102_reg_i_2_n_1; wire temp_cmp_neutral_min_102_reg_i_2_n_2; wire temp_cmp_neutral_min_102_reg_i_2_n_3; wire temp_cmp_one_dec_max_101; wire temp_cmp_one_dec_max_102; wire temp_cmp_one_dec_max_102_i_10_n_0; wire temp_cmp_one_dec_max_102_i_11_n_0; wire temp_cmp_one_dec_max_102_i_12_n_0; wire temp_cmp_one_dec_max_102_i_13_n_0; wire temp_cmp_one_dec_max_102_i_14_n_0; wire temp_cmp_one_dec_max_102_i_3_n_0; wire temp_cmp_one_dec_max_102_i_4_n_0; wire temp_cmp_one_dec_max_102_i_5_n_0; wire temp_cmp_one_dec_max_102_i_6_n_0; wire temp_cmp_one_dec_max_102_i_7_n_0; wire temp_cmp_one_dec_max_102_i_8_n_0; wire temp_cmp_one_dec_max_102_i_9_n_0; wire temp_cmp_one_dec_max_102_reg_i_1_n_3; wire temp_cmp_one_dec_max_102_reg_i_2_n_0; wire temp_cmp_one_dec_max_102_reg_i_2_n_1; wire temp_cmp_one_dec_max_102_reg_i_2_n_2; wire temp_cmp_one_dec_max_102_reg_i_2_n_3; wire temp_cmp_one_dec_min_101; wire temp_cmp_one_dec_min_102; wire temp_cmp_one_dec_min_102_i_10_n_0; wire temp_cmp_one_dec_min_102_i_11_n_0; wire temp_cmp_one_dec_min_102_i_12_n_0; wire temp_cmp_one_dec_min_102_i_13_n_0; wire temp_cmp_one_dec_min_102_i_14_n_0; wire temp_cmp_one_dec_min_102_i_3_n_0; wire temp_cmp_one_dec_min_102_i_4_n_0; wire temp_cmp_one_dec_min_102_i_5_n_0; wire temp_cmp_one_dec_min_102_i_6_n_0; wire temp_cmp_one_dec_min_102_i_7_n_0; wire temp_cmp_one_dec_min_102_i_8_n_0; wire temp_cmp_one_dec_min_102_i_9_n_0; wire temp_cmp_one_dec_min_102_reg_i_1_n_3; wire temp_cmp_one_dec_min_102_reg_i_2_n_0; wire temp_cmp_one_dec_min_102_reg_i_2_n_1; wire temp_cmp_one_dec_min_102_reg_i_2_n_2; wire temp_cmp_one_dec_min_102_reg_i_2_n_3; wire temp_cmp_one_inc_max_101; wire temp_cmp_one_inc_max_102; wire temp_cmp_one_inc_max_102_i_10_n_0; wire temp_cmp_one_inc_max_102_i_11_n_0; wire temp_cmp_one_inc_max_102_i_12_n_0; wire temp_cmp_one_inc_max_102_i_13_n_0; wire temp_cmp_one_inc_max_102_i_14_n_0; wire temp_cmp_one_inc_max_102_i_3_n_0; wire temp_cmp_one_inc_max_102_i_4_n_0; wire temp_cmp_one_inc_max_102_i_5_n_0; wire temp_cmp_one_inc_max_102_i_6_n_0; wire temp_cmp_one_inc_max_102_i_7_n_0; wire temp_cmp_one_inc_max_102_i_8_n_0; wire temp_cmp_one_inc_max_102_i_9_n_0; wire temp_cmp_one_inc_max_102_reg_i_1_n_3; wire temp_cmp_one_inc_max_102_reg_i_2_n_0; wire temp_cmp_one_inc_max_102_reg_i_2_n_1; wire temp_cmp_one_inc_max_102_reg_i_2_n_2; wire temp_cmp_one_inc_max_102_reg_i_2_n_3; wire temp_cmp_one_inc_min_101; wire temp_cmp_one_inc_min_102; wire temp_cmp_one_inc_min_102_i_10_n_0; wire temp_cmp_one_inc_min_102_i_11_n_0; wire temp_cmp_one_inc_min_102_i_12_n_0; wire temp_cmp_one_inc_min_102_i_13_n_0; wire temp_cmp_one_inc_min_102_i_14_n_0; wire temp_cmp_one_inc_min_102_i_3_n_0; wire temp_cmp_one_inc_min_102_i_4_n_0; wire temp_cmp_one_inc_min_102_i_5_n_0; wire temp_cmp_one_inc_min_102_i_6_n_0; wire temp_cmp_one_inc_min_102_i_7_n_0; wire temp_cmp_one_inc_min_102_i_8_n_0; wire temp_cmp_one_inc_min_102_i_9_n_0; wire temp_cmp_one_inc_min_102_reg_i_1_n_3; wire temp_cmp_one_inc_min_102_reg_i_2_n_0; wire temp_cmp_one_inc_min_102_reg_i_2_n_1; wire temp_cmp_one_inc_min_102_reg_i_2_n_2; wire temp_cmp_one_inc_min_102_reg_i_2_n_3; wire temp_cmp_three_dec_max_101; wire temp_cmp_three_dec_max_102; wire temp_cmp_three_dec_max_102_i_10_n_0; wire temp_cmp_three_dec_max_102_i_11_n_0; wire temp_cmp_three_dec_max_102_i_12_n_0; wire temp_cmp_three_dec_max_102_i_13_n_0; wire temp_cmp_three_dec_max_102_i_14_n_0; wire temp_cmp_three_dec_max_102_i_3_n_0; wire temp_cmp_three_dec_max_102_i_4_n_0; wire temp_cmp_three_dec_max_102_i_5_n_0; wire temp_cmp_three_dec_max_102_i_6_n_0; wire temp_cmp_three_dec_max_102_i_7_n_0; wire temp_cmp_three_dec_max_102_i_8_n_0; wire temp_cmp_three_dec_max_102_i_9_n_0; wire temp_cmp_three_dec_max_102_reg_i_1_n_3; wire temp_cmp_three_dec_max_102_reg_i_2_n_0; wire temp_cmp_three_dec_max_102_reg_i_2_n_1; wire temp_cmp_three_dec_max_102_reg_i_2_n_2; wire temp_cmp_three_dec_max_102_reg_i_2_n_3; wire temp_cmp_three_dec_min_101; wire temp_cmp_three_dec_min_102; wire temp_cmp_three_dec_min_102_i_10_n_0; wire temp_cmp_three_dec_min_102_i_11_n_0; wire temp_cmp_three_dec_min_102_i_12_n_0; wire temp_cmp_three_dec_min_102_i_13_n_0; wire temp_cmp_three_dec_min_102_i_14_n_0; wire temp_cmp_three_dec_min_102_i_3_n_0; wire temp_cmp_three_dec_min_102_i_4_n_0; wire temp_cmp_three_dec_min_102_i_5_n_0; wire temp_cmp_three_dec_min_102_i_6_n_0; wire temp_cmp_three_dec_min_102_i_7_n_0; wire temp_cmp_three_dec_min_102_i_8_n_0; wire temp_cmp_three_dec_min_102_i_9_n_0; wire temp_cmp_three_dec_min_102_reg_i_1_n_3; wire temp_cmp_three_dec_min_102_reg_i_2_n_0; wire temp_cmp_three_dec_min_102_reg_i_2_n_1; wire temp_cmp_three_dec_min_102_reg_i_2_n_2; wire temp_cmp_three_dec_min_102_reg_i_2_n_3; wire temp_cmp_three_inc_max_101; wire temp_cmp_three_inc_max_102; wire temp_cmp_three_inc_max_102_i_10_n_0; wire temp_cmp_three_inc_max_102_i_11_n_0; wire temp_cmp_three_inc_max_102_i_12_n_0; wire temp_cmp_three_inc_max_102_i_13_n_0; wire temp_cmp_three_inc_max_102_i_14_n_0; wire temp_cmp_three_inc_max_102_i_3_n_0; wire temp_cmp_three_inc_max_102_i_4_n_0; wire temp_cmp_three_inc_max_102_i_5_n_0; wire temp_cmp_three_inc_max_102_i_6_n_0; wire temp_cmp_three_inc_max_102_i_7_n_0; wire temp_cmp_three_inc_max_102_i_8_n_0; wire temp_cmp_three_inc_max_102_i_9_n_0; wire temp_cmp_three_inc_max_102_reg_i_1_n_3; wire temp_cmp_three_inc_max_102_reg_i_2_n_0; wire temp_cmp_three_inc_max_102_reg_i_2_n_1; wire temp_cmp_three_inc_max_102_reg_i_2_n_2; wire temp_cmp_three_inc_max_102_reg_i_2_n_3; wire temp_cmp_three_inc_min_101; wire temp_cmp_three_inc_min_102; wire temp_cmp_three_inc_min_102_i_10_n_0; wire temp_cmp_three_inc_min_102_i_11_n_0; wire temp_cmp_three_inc_min_102_i_12_n_0; wire temp_cmp_three_inc_min_102_i_13_n_0; wire temp_cmp_three_inc_min_102_i_14_n_0; wire temp_cmp_three_inc_min_102_i_3_n_0; wire temp_cmp_three_inc_min_102_i_4_n_0; wire temp_cmp_three_inc_min_102_i_5_n_0; wire temp_cmp_three_inc_min_102_i_6_n_0; wire temp_cmp_three_inc_min_102_i_7_n_0; wire temp_cmp_three_inc_min_102_i_8_n_0; wire temp_cmp_three_inc_min_102_i_9_n_0; wire temp_cmp_three_inc_min_102_reg_i_1_n_3; wire temp_cmp_three_inc_min_102_reg_i_2_n_0; wire temp_cmp_three_inc_min_102_reg_i_2_n_1; wire temp_cmp_three_inc_min_102_reg_i_2_n_2; wire temp_cmp_three_inc_min_102_reg_i_2_n_3; wire temp_cmp_two_dec_max_101; wire temp_cmp_two_dec_max_102; wire temp_cmp_two_dec_max_102_i_10_n_0; wire temp_cmp_two_dec_max_102_i_11_n_0; wire temp_cmp_two_dec_max_102_i_12_n_0; wire temp_cmp_two_dec_max_102_i_13_n_0; wire temp_cmp_two_dec_max_102_i_14_n_0; wire temp_cmp_two_dec_max_102_i_3_n_0; wire temp_cmp_two_dec_max_102_i_4_n_0; wire temp_cmp_two_dec_max_102_i_5_n_0; wire temp_cmp_two_dec_max_102_i_6_n_0; wire temp_cmp_two_dec_max_102_i_7_n_0; wire temp_cmp_two_dec_max_102_i_8_n_0; wire temp_cmp_two_dec_max_102_i_9_n_0; wire temp_cmp_two_dec_max_102_reg_i_1_n_3; wire temp_cmp_two_dec_max_102_reg_i_2_n_0; wire temp_cmp_two_dec_max_102_reg_i_2_n_1; wire temp_cmp_two_dec_max_102_reg_i_2_n_2; wire temp_cmp_two_dec_max_102_reg_i_2_n_3; wire temp_cmp_two_dec_min_101; wire temp_cmp_two_dec_min_102; wire temp_cmp_two_dec_min_102_i_10_n_0; wire temp_cmp_two_dec_min_102_i_11_n_0; wire temp_cmp_two_dec_min_102_i_12_n_0; wire temp_cmp_two_dec_min_102_i_13_n_0; wire temp_cmp_two_dec_min_102_i_14_n_0; wire temp_cmp_two_dec_min_102_i_3_n_0; wire temp_cmp_two_dec_min_102_i_4_n_0; wire temp_cmp_two_dec_min_102_i_5_n_0; wire temp_cmp_two_dec_min_102_i_6_n_0; wire temp_cmp_two_dec_min_102_i_7_n_0; wire temp_cmp_two_dec_min_102_i_8_n_0; wire temp_cmp_two_dec_min_102_i_9_n_0; wire temp_cmp_two_dec_min_102_reg_i_1_n_3; wire temp_cmp_two_dec_min_102_reg_i_2_n_0; wire temp_cmp_two_dec_min_102_reg_i_2_n_1; wire temp_cmp_two_dec_min_102_reg_i_2_n_2; wire temp_cmp_two_dec_min_102_reg_i_2_n_3; wire temp_cmp_two_inc_max_101; wire temp_cmp_two_inc_max_102; wire temp_cmp_two_inc_max_102_i_10_n_0; wire temp_cmp_two_inc_max_102_i_11_n_0; wire temp_cmp_two_inc_max_102_i_12_n_0; wire temp_cmp_two_inc_max_102_i_13_n_0; wire temp_cmp_two_inc_max_102_i_14_n_0; wire temp_cmp_two_inc_max_102_i_3_n_0; wire temp_cmp_two_inc_max_102_i_4_n_0; wire temp_cmp_two_inc_max_102_i_5_n_0; wire temp_cmp_two_inc_max_102_i_6_n_0; wire temp_cmp_two_inc_max_102_i_7_n_0; wire temp_cmp_two_inc_max_102_i_8_n_0; wire temp_cmp_two_inc_max_102_i_9_n_0; wire temp_cmp_two_inc_max_102_reg_i_1_n_3; wire temp_cmp_two_inc_max_102_reg_i_2_n_0; wire temp_cmp_two_inc_max_102_reg_i_2_n_1; wire temp_cmp_two_inc_max_102_reg_i_2_n_2; wire temp_cmp_two_inc_max_102_reg_i_2_n_3; wire temp_cmp_two_inc_min_101; wire temp_cmp_two_inc_min_102; wire temp_cmp_two_inc_min_102_i_10_n_0; wire temp_cmp_two_inc_min_102_i_11_n_0; wire temp_cmp_two_inc_min_102_i_12_n_0; wire temp_cmp_two_inc_min_102_i_13_n_0; wire temp_cmp_two_inc_min_102_i_14_n_0; wire temp_cmp_two_inc_min_102_i_3_n_0; wire temp_cmp_two_inc_min_102_i_4_n_0; wire temp_cmp_two_inc_min_102_i_5_n_0; wire temp_cmp_two_inc_min_102_i_6_n_0; wire temp_cmp_two_inc_min_102_i_7_n_0; wire temp_cmp_two_inc_min_102_i_8_n_0; wire temp_cmp_two_inc_min_102_i_9_n_0; wire temp_cmp_two_inc_min_102_reg_i_1_n_3; wire temp_cmp_two_inc_min_102_reg_i_2_n_0; wire temp_cmp_two_inc_min_102_reg_i_2_n_1; wire temp_cmp_two_inc_min_102_reg_i_2_n_2; wire temp_cmp_two_inc_min_102_reg_i_2_n_3; wire temp_gte_three_dec_max; wire tempmon_init_complete; wire tempmon_pi_f_dec; wire tempmon_pi_f_inc; wire tempmon_sample_en; wire tempmon_sample_en_101; wire tempmon_sample_en_102; wire tempmon_sel_pi_incdec; wire [10:0]tempmon_state; wire \tempmon_state[0]_i_2_n_0 ; wire \tempmon_state[10]_i_10_n_0 ; wire \tempmon_state[10]_i_11_n_0 ; wire \tempmon_state[10]_i_12_n_0 ; wire \tempmon_state[10]_i_13_n_0 ; wire \tempmon_state[10]_i_14_n_0 ; wire \tempmon_state[10]_i_15_n_0 ; wire \tempmon_state[10]_i_16_n_0 ; wire \tempmon_state[10]_i_2_n_0 ; wire \tempmon_state[10]_i_3_n_0 ; wire \tempmon_state[10]_i_4_n_0 ; wire \tempmon_state[10]_i_5_n_0 ; wire \tempmon_state[10]_i_6_n_0 ; wire \tempmon_state[10]_i_7_n_0 ; wire \tempmon_state[10]_i_8_n_0 ; wire \tempmon_state[10]_i_9_n_0 ; wire \tempmon_state[1]_i_1_n_0 ; wire \tempmon_state[2]_i_1_n_0 ; wire \tempmon_state[3]_i_1_n_0 ; wire \tempmon_state[4]_i_1_n_0 ; wire \tempmon_state[5]_i_1_n_0 ; wire \tempmon_state[6]_i_1_n_0 ; wire \tempmon_state[6]_i_2_n_0 ; wire \tempmon_state[7]_i_1_n_0 ; wire \tempmon_state[8]_i_1_n_0 ; wire \tempmon_state[9]_i_1_n_0 ; wire tempmon_state_init; wire tempmon_state_nxt; wire [11:0]three_dec_max_limit; wire \three_dec_max_limit[0]_i_1_n_0 ; wire \three_dec_max_limit[10]_i_1_n_0 ; wire \three_dec_max_limit[11]_i_1_n_0 ; wire \three_dec_max_limit[11]_i_3_n_0 ; wire \three_dec_max_limit[11]_i_4_n_0 ; wire \three_dec_max_limit[11]_i_5_n_0 ; wire \three_dec_max_limit[1]_i_1_n_0 ; wire \three_dec_max_limit[2]_i_1_n_0 ; wire \three_dec_max_limit[3]_i_1_n_0 ; wire \three_dec_max_limit[4]_i_1_n_0 ; wire \three_dec_max_limit[4]_i_3_n_0 ; wire \three_dec_max_limit[4]_i_4_n_0 ; wire \three_dec_max_limit[4]_i_5_n_0 ; wire \three_dec_max_limit[4]_i_6_n_0 ; wire \three_dec_max_limit[5]_i_1_n_0 ; wire \three_dec_max_limit[6]_i_1_n_0 ; wire \three_dec_max_limit[7]_i_1_n_0 ; wire \three_dec_max_limit[8]_i_1_n_0 ; wire \three_dec_max_limit[8]_i_3_n_0 ; wire \three_dec_max_limit[8]_i_4_n_0 ; wire \three_dec_max_limit[8]_i_5_n_0 ; wire \three_dec_max_limit[8]_i_6_n_0 ; wire \three_dec_max_limit[9]_i_1_n_0 ; wire \three_dec_max_limit_reg[11]_i_2_n_2 ; wire \three_dec_max_limit_reg[11]_i_2_n_3 ; wire \three_dec_max_limit_reg[11]_i_2_n_5 ; wire \three_dec_max_limit_reg[11]_i_2_n_6 ; wire \three_dec_max_limit_reg[11]_i_2_n_7 ; wire \three_dec_max_limit_reg[1]_i_2_n_0 ; wire \three_dec_max_limit_reg[4]_i_2_n_0 ; wire \three_dec_max_limit_reg[4]_i_2_n_1 ; wire \three_dec_max_limit_reg[4]_i_2_n_2 ; wire \three_dec_max_limit_reg[4]_i_2_n_3 ; wire \three_dec_max_limit_reg[4]_i_2_n_4 ; wire \three_dec_max_limit_reg[4]_i_2_n_5 ; wire \three_dec_max_limit_reg[4]_i_2_n_6 ; wire \three_dec_max_limit_reg[8]_i_2_n_0 ; wire \three_dec_max_limit_reg[8]_i_2_n_1 ; wire \three_dec_max_limit_reg[8]_i_2_n_2 ; wire \three_dec_max_limit_reg[8]_i_2_n_3 ; wire \three_dec_max_limit_reg[8]_i_2_n_4 ; wire \three_dec_max_limit_reg[8]_i_2_n_5 ; wire \three_dec_max_limit_reg[8]_i_2_n_6 ; wire \three_dec_max_limit_reg[8]_i_2_n_7 ; wire [11:0]three_dec_min_limit; wire \three_dec_min_limit[11]_i_2_n_0 ; wire \three_dec_min_limit[11]_i_3_n_0 ; wire \three_dec_min_limit[5]_i_2_n_0 ; wire \three_dec_min_limit[5]_i_3_n_0 ; wire \three_dec_min_limit[5]_i_4_n_0 ; wire \three_dec_min_limit[5]_i_5_n_0 ; wire \three_dec_min_limit[9]_i_2_n_0 ; wire \three_dec_min_limit[9]_i_3_n_0 ; wire \three_dec_min_limit[9]_i_4_n_0 ; wire \three_dec_min_limit[9]_i_5_n_0 ; wire [11:2]three_dec_min_limit_nxt; wire \three_dec_min_limit_reg[11]_i_1_n_3 ; wire \three_dec_min_limit_reg[5]_i_1_n_0 ; wire \three_dec_min_limit_reg[5]_i_1_n_1 ; wire \three_dec_min_limit_reg[5]_i_1_n_2 ; wire \three_dec_min_limit_reg[5]_i_1_n_3 ; wire \three_dec_min_limit_reg[9]_i_1_n_0 ; wire \three_dec_min_limit_reg[9]_i_1_n_1 ; wire \three_dec_min_limit_reg[9]_i_1_n_2 ; wire \three_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]three_inc_max_limit; wire \three_inc_max_limit[11]_i_2_n_0 ; wire \three_inc_max_limit[11]_i_3_n_0 ; wire \three_inc_max_limit[11]_i_4_n_0 ; wire \three_inc_max_limit[4]_i_2_n_0 ; wire \three_inc_max_limit[4]_i_3_n_0 ; wire \three_inc_max_limit[4]_i_4_n_0 ; wire \three_inc_max_limit[4]_i_5_n_0 ; wire \three_inc_max_limit[8]_i_2_n_0 ; wire \three_inc_max_limit[8]_i_3_n_0 ; wire \three_inc_max_limit[8]_i_4_n_0 ; wire \three_inc_max_limit[8]_i_5_n_0 ; wire [11:1]three_inc_max_limit_nxt; wire \three_inc_max_limit_reg[11]_i_1_n_2 ; wire \three_inc_max_limit_reg[11]_i_1_n_3 ; wire \three_inc_max_limit_reg[4]_i_1_n_0 ; wire \three_inc_max_limit_reg[4]_i_1_n_1 ; wire \three_inc_max_limit_reg[4]_i_1_n_2 ; wire \three_inc_max_limit_reg[4]_i_1_n_3 ; wire \three_inc_max_limit_reg[8]_i_1_n_0 ; wire \three_inc_max_limit_reg[8]_i_1_n_1 ; wire \three_inc_max_limit_reg[8]_i_1_n_2 ; wire \three_inc_max_limit_reg[8]_i_1_n_3 ; wire [11:1]three_inc_min_limit; wire \three_inc_min_limit[11]_i_2_n_0 ; wire \three_inc_min_limit[11]_i_3_n_0 ; wire \three_inc_min_limit[5]_i_2_n_0 ; wire \three_inc_min_limit[5]_i_3_n_0 ; wire \three_inc_min_limit[5]_i_4_n_0 ; wire \three_inc_min_limit[5]_i_5_n_0 ; wire \three_inc_min_limit[9]_i_2_n_0 ; wire \three_inc_min_limit[9]_i_3_n_0 ; wire \three_inc_min_limit[9]_i_4_n_0 ; wire \three_inc_min_limit[9]_i_5_n_0 ; wire [11:2]three_inc_min_limit_nxt; wire \three_inc_min_limit_reg[11]_i_1_n_3 ; wire \three_inc_min_limit_reg[5]_i_1_n_0 ; wire \three_inc_min_limit_reg[5]_i_1_n_1 ; wire \three_inc_min_limit_reg[5]_i_1_n_2 ; wire \three_inc_min_limit_reg[5]_i_1_n_3 ; wire \three_inc_min_limit_reg[9]_i_1_n_0 ; wire \three_inc_min_limit_reg[9]_i_1_n_1 ; wire \three_inc_min_limit_reg[9]_i_1_n_2 ; wire \three_inc_min_limit_reg[9]_i_1_n_3 ; wire [11:0]two_dec_max_limit; wire \two_dec_max_limit[0]_i_1_n_0 ; wire \two_dec_max_limit[11]_i_2_n_0 ; wire \two_dec_max_limit[11]_i_3_n_0 ; wire \two_dec_max_limit[11]_i_4_n_0 ; wire \two_dec_max_limit[4]_i_2_n_0 ; wire \two_dec_max_limit[4]_i_3_n_0 ; wire \two_dec_max_limit[4]_i_4_n_0 ; wire \two_dec_max_limit[4]_i_5_n_0 ; wire \two_dec_max_limit[8]_i_2_n_0 ; wire \two_dec_max_limit[8]_i_3_n_0 ; wire \two_dec_max_limit[8]_i_4_n_0 ; wire \two_dec_max_limit[8]_i_5_n_0 ; wire [11:1]two_dec_max_limit_nxt; wire \two_dec_max_limit_reg[11]_i_1_n_2 ; wire \two_dec_max_limit_reg[11]_i_1_n_3 ; wire \two_dec_max_limit_reg[4]_i_1_n_0 ; wire \two_dec_max_limit_reg[4]_i_1_n_1 ; wire \two_dec_max_limit_reg[4]_i_1_n_2 ; wire \two_dec_max_limit_reg[4]_i_1_n_3 ; wire \two_dec_max_limit_reg[8]_i_1_n_0 ; wire \two_dec_max_limit_reg[8]_i_1_n_1 ; wire \two_dec_max_limit_reg[8]_i_1_n_2 ; wire \two_dec_max_limit_reg[8]_i_1_n_3 ; wire [11:1]two_dec_min_limit; wire \two_dec_min_limit[11]_i_2_n_0 ; wire \two_dec_min_limit[11]_i_3_n_0 ; wire \two_dec_min_limit[5]_i_2_n_0 ; wire \two_dec_min_limit[5]_i_3_n_0 ; wire \two_dec_min_limit[5]_i_4_n_0 ; wire \two_dec_min_limit[5]_i_5_n_0 ; wire \two_dec_min_limit[9]_i_2_n_0 ; wire \two_dec_min_limit[9]_i_3_n_0 ; wire \two_dec_min_limit[9]_i_4_n_0 ; wire \two_dec_min_limit[9]_i_5_n_0 ; wire [11:2]two_dec_min_limit_nxt; wire \two_dec_min_limit_reg[11]_i_1_n_3 ; wire \two_dec_min_limit_reg[5]_i_1_n_0 ; wire \two_dec_min_limit_reg[5]_i_1_n_1 ; wire \two_dec_min_limit_reg[5]_i_1_n_2 ; wire \two_dec_min_limit_reg[5]_i_1_n_3 ; wire \two_dec_min_limit_reg[9]_i_1_n_0 ; wire \two_dec_min_limit_reg[9]_i_1_n_1 ; wire \two_dec_min_limit_reg[9]_i_1_n_2 ; wire \two_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]two_inc_max_limit; wire \two_inc_max_limit[11]_i_2_n_0 ; wire \two_inc_max_limit[11]_i_3_n_0 ; wire \two_inc_max_limit[11]_i_4_n_0 ; wire \two_inc_max_limit[4]_i_2_n_0 ; wire \two_inc_max_limit[4]_i_3_n_0 ; wire \two_inc_max_limit[4]_i_4_n_0 ; wire \two_inc_max_limit[4]_i_5_n_0 ; wire \two_inc_max_limit[8]_i_2_n_0 ; wire \two_inc_max_limit[8]_i_3_n_0 ; wire \two_inc_max_limit[8]_i_4_n_0 ; wire \two_inc_max_limit[8]_i_5_n_0 ; wire [11:1]two_inc_max_limit_nxt; wire \two_inc_max_limit_reg[11]_i_1_n_2 ; wire \two_inc_max_limit_reg[11]_i_1_n_3 ; wire \two_inc_max_limit_reg[4]_i_1_n_0 ; wire \two_inc_max_limit_reg[4]_i_1_n_1 ; wire \two_inc_max_limit_reg[4]_i_1_n_2 ; wire \two_inc_max_limit_reg[4]_i_1_n_3 ; wire \two_inc_max_limit_reg[8]_i_1_n_0 ; wire \two_inc_max_limit_reg[8]_i_1_n_1 ; wire \two_inc_max_limit_reg[8]_i_1_n_2 ; wire \two_inc_max_limit_reg[8]_i_1_n_3 ; wire [11:1]two_inc_min_limit; wire \two_inc_min_limit[11]_i_2_n_0 ; wire \two_inc_min_limit[11]_i_3_n_0 ; wire \two_inc_min_limit[5]_i_2_n_0 ; wire \two_inc_min_limit[5]_i_3_n_0 ; wire \two_inc_min_limit[5]_i_4_n_0 ; wire \two_inc_min_limit[5]_i_5_n_0 ; wire \two_inc_min_limit[9]_i_2_n_0 ; wire \two_inc_min_limit[9]_i_3_n_0 ; wire \two_inc_min_limit[9]_i_4_n_0 ; wire \two_inc_min_limit[9]_i_5_n_0 ; wire [11:2]two_inc_min_limit_nxt; wire \two_inc_min_limit_reg[11]_i_1_n_3 ; wire \two_inc_min_limit_reg[5]_i_1_n_0 ; wire \two_inc_min_limit_reg[5]_i_1_n_1 ; wire \two_inc_min_limit_reg[5]_i_1_n_2 ; wire \two_inc_min_limit_reg[5]_i_1_n_3 ; wire \two_inc_min_limit_reg[9]_i_1_n_0 ; wire \two_inc_min_limit_reg[9]_i_1_n_1 ; wire \two_inc_min_limit_reg[9]_i_1_n_2 ; wire \two_inc_min_limit_reg[9]_i_1_n_3 ; wire update_temp_101__0; wire update_temp_102; wire [3:1]\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [3:2]\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED; wire [2:2]\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED ; wire [3:3]\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED ; wire [3:0]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED ; wire [3:1]\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [0:0]\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair247" *) LUT4 #( .INIT(16'h3331)) \calib_sel[1]_i_2 (.I0(calib_complete), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(tempmon_pi_f_inc), .I3(tempmon_pi_f_dec), .O(\calib_zero_inputs_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT5 #( .INIT(32'h00A800AA)) \calib_sel[3]_i_1 (.I0(ctl_lane_sel), .I1(tempmon_pi_f_dec), .I2(tempmon_pi_f_inc), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(calib_complete), .O(D)); LUT6 #( .INIT(64'h00000200FFFFFFFF)) \calib_zero_inputs[1]_i_1 (.I0(cmd_delay_start0), .I1(tempmon_pi_f_inc), .I2(tempmon_pi_f_dec), .I3(delay_done_r4_reg), .I4(calib_in_common), .I5(\calib_zero_inputs_reg[1]_0 ), .O(\calib_zero_inputs_reg[1] )); FDRE #( .INIT(1'b0)) \device_temp_101_reg[0] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [0]), .Q(device_temp_101[0]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[10] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [10]), .Q(device_temp_101[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[11] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [11]), .Q(device_temp_101[11]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[1] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [1]), .Q(device_temp_101[1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[2] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [2]), .Q(device_temp_101[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[3] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [3]), .Q(device_temp_101[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[4] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [4]), .Q(device_temp_101[4]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[5] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [5]), .Q(device_temp_101[5]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[6] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [6]), .Q(device_temp_101[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[7] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [7]), .Q(device_temp_101[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[8] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [8]), .Q(device_temp_101[8]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \device_temp_101_reg[9] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [9]), .Q(device_temp_101[9]), .R(rstdiv0_sync_r1_reg_rep__5)); LUT5 #( .INIT(32'h00000800)) \device_temp_init[11]_i_1 (.I0(\device_temp_init[11]_i_2_n_0 ), .I1(\device_temp_init[11]_i_3_n_0 ), .I2(tempmon_state[0]), .I3(tempmon_state[1]), .I4(tempmon_state[2]), .O(tempmon_state_init)); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT4 #( .INIT(16'h0001)) \device_temp_init[11]_i_2 (.I0(tempmon_state[6]), .I1(tempmon_state[5]), .I2(tempmon_state[4]), .I3(tempmon_state[3]), .O(\device_temp_init[11]_i_2_n_0 )); LUT4 #( .INIT(16'h0001)) \device_temp_init[11]_i_3 (.I0(tempmon_state[10]), .I1(tempmon_state[9]), .I2(tempmon_state[8]), .I3(tempmon_state[7]), .O(\device_temp_init[11]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \device_temp_init_reg[0] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[0]), .Q(device_temp_init[0]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[10] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[10]), .Q(device_temp_init[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[11] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[11]), .Q(device_temp_init[11]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[1] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[1]), .Q(device_temp_init[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[2] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[2]), .Q(device_temp_init[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[3] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[3]), .Q(device_temp_init[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[4] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[4]), .Q(device_temp_init[4]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[5] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[5]), .Q(device_temp_init[5]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[6] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[6]), .Q(device_temp_init[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[7] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[7]), .Q(device_temp_init[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[8] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[8]), .Q(device_temp_init[8]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \device_temp_init_reg[9] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[9]), .Q(device_temp_init[9]), .R(rstdiv0_sync_r1_reg_rep__4)); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[11]_i_2 (.I0(three_dec_max_limit[11]), .O(\four_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[11]_i_3 (.I0(three_dec_max_limit[10]), .O(\four_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[5]_i_2 (.I0(three_dec_max_limit[5]), .O(\four_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[5]_i_3 (.I0(three_dec_max_limit[4]), .O(\four_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[5]_i_4 (.I0(three_dec_max_limit[3]), .O(\four_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \four_dec_min_limit[5]_i_5 (.I0(three_dec_max_limit[2]), .O(\four_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_2 (.I0(three_dec_max_limit[9]), .O(\four_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_3 (.I0(three_dec_max_limit[8]), .O(\four_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_4 (.I0(three_dec_max_limit[7]), .O(\four_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_5 (.I0(three_dec_max_limit[6]), .O(\four_dec_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[0] (.C(CLK), .CE(1'b1), .D(three_dec_max_limit[0]), .Q(four_dec_min_limit[0]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[10]), .Q(four_dec_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[11]), .Q(four_dec_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \four_dec_min_limit_reg[11]_i_1 (.CI(\four_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\four_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}), .O({\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\four_dec_min_limit[11]_i_2_n_0 ,\four_dec_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(three_dec_max_limit[1]), .Q(four_dec_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[2]), .Q(four_dec_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[3]), .Q(four_dec_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[4]), .Q(four_dec_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[5]), .Q(four_dec_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \four_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\four_dec_min_limit_reg[5]_i_1_n_0 ,\four_dec_min_limit_reg[5]_i_1_n_1 ,\four_dec_min_limit_reg[5]_i_1_n_2 ,\four_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({three_dec_max_limit[5:3],1'b0}), .O(four_dec_min_limit_nxt[5:2]), .S({\four_dec_min_limit[5]_i_2_n_0 ,\four_dec_min_limit[5]_i_3_n_0 ,\four_dec_min_limit[5]_i_4_n_0 ,\four_dec_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[6]), .Q(four_dec_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[7]), .Q(four_dec_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[8]), .Q(four_dec_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \four_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[9]), .Q(four_dec_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \four_dec_min_limit_reg[9]_i_1 (.CI(\four_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\four_dec_min_limit_reg[9]_i_1_n_0 ,\four_dec_min_limit_reg[9]_i_1_n_1 ,\four_dec_min_limit_reg[9]_i_1_n_2 ,\four_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(three_dec_max_limit[9:6]), .O(four_dec_min_limit_nxt[9:6]), .S({\four_dec_min_limit[9]_i_2_n_0 ,\four_dec_min_limit[9]_i_3_n_0 ,\four_dec_min_limit[9]_i_4_n_0 ,\four_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\four_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\four_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \four_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\four_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[1]_i_2 (.I0(device_temp_init[1]), .O(\four_inc_max_limit[1]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\four_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\four_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\four_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\four_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \four_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\four_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\four_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \four_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\four_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\four_inc_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[10]), .Q(four_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[11]), .Q(four_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \four_inc_max_limit_reg[11]_i_1 (.CI(\four_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\four_inc_max_limit_reg[11]_i_1_n_2 ,\four_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10],1'b0}), .O({\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],four_inc_max_limit_nxt[11:9]}), .S({1'b0,\four_inc_max_limit[11]_i_2_n_0 ,\four_inc_max_limit[11]_i_3_n_0 ,\four_inc_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[1]), .Q(four_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__5)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \four_inc_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],four_inc_max_limit_nxt[1]}), .S({\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\four_inc_max_limit[1]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[2]), .Q(four_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[3]), .Q(four_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[4]), .Q(four_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \four_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\four_inc_max_limit_reg[4]_i_1_n_0 ,\four_inc_max_limit_reg[4]_i_1_n_1 ,\four_inc_max_limit_reg[4]_i_1_n_2 ,\four_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI(device_temp_init[4:1]), .O({four_inc_max_limit_nxt[4:2],two_inc_max_limit_nxt[1]}), .S({\four_inc_max_limit[4]_i_2_n_0 ,\four_inc_max_limit[4]_i_3_n_0 ,\four_inc_max_limit[4]_i_4_n_0 ,\four_inc_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[5]), .Q(four_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[6]), .Q(four_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[7]), .Q(four_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[8]), .Q(four_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \four_inc_max_limit_reg[8]_i_1 (.CI(\four_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\four_inc_max_limit_reg[8]_i_1_n_0 ,\four_inc_max_limit_reg[8]_i_1_n_1 ,\four_inc_max_limit_reg[8]_i_1_n_2 ,\four_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,device_temp_init[7],1'b0,device_temp_init[5]}), .O(four_inc_max_limit_nxt[8:5]), .S({\four_inc_max_limit[8]_i_2_n_0 ,\four_inc_max_limit[8]_i_3_n_0 ,\four_inc_max_limit[8]_i_4_n_0 ,\four_inc_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \four_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[9]), .Q(four_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__5)); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT4 #( .INIT(16'hFE00)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_2 (.I0(tempmon_pi_f_inc), .I1(tempmon_pi_f_dec), .I2(oclkdelay_calib_done_r_reg), .I3(ck_addr_cmd_delay_done), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'hFDFFFDFDFFFFFFFF)) \gen_byte_sel_div1.calib_in_common_i_4 (.I0(cmd_delay_start0), .I1(tempmon_pi_f_inc), .I2(tempmon_pi_f_dec), .I3(fine_adjust_done_r_reg), .I4(rd_data_offset_cal_done), .I5(ck_addr_cmd_delay_done), .O(\gen_byte_sel_div1.calib_in_common_reg )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\neutral_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\neutral_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\neutral_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\neutral_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\neutral_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\neutral_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\neutral_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\neutral_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\neutral_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\neutral_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\neutral_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[10]), .Q(neutral_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[11]), .Q(neutral_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \neutral_max_limit_reg[11]_i_1 (.CI(\neutral_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\neutral_max_limit_reg[11]_i_1_n_2 ,\neutral_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED [3],neutral_max_limit_nxt[11:9]}), .S({1'b0,\neutral_max_limit[11]_i_2_n_0 ,\neutral_max_limit[11]_i_3_n_0 ,\neutral_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[1]), .Q(neutral_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \neutral_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],neutral_max_limit_nxt[1]}), .S({\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\four_inc_max_limit[1]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[2]), .Q(neutral_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[3]), .Q(neutral_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[4]), .Q(neutral_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \neutral_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\neutral_max_limit_reg[4]_i_1_n_0 ,\neutral_max_limit_reg[4]_i_1_n_1 ,\neutral_max_limit_reg[4]_i_1_n_2 ,\neutral_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({device_temp_init[4],1'b0,device_temp_init[2:1]}), .O({neutral_max_limit_nxt[4:2],\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\neutral_max_limit[4]_i_2_n_0 ,\neutral_max_limit[4]_i_3_n_0 ,\neutral_max_limit[4]_i_4_n_0 ,\neutral_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[5]), .Q(neutral_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[6]), .Q(neutral_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[7]), .Q(neutral_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[8]), .Q(neutral_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \neutral_max_limit_reg[8]_i_1 (.CI(\neutral_max_limit_reg[4]_i_1_n_0 ), .CO({\neutral_max_limit_reg[8]_i_1_n_0 ,\neutral_max_limit_reg[8]_i_1_n_1 ,\neutral_max_limit_reg[8]_i_1_n_2 ,\neutral_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[6:5]}), .O(neutral_max_limit_nxt[8:5]), .S({\neutral_max_limit[8]_i_2_n_0 ,\neutral_max_limit[8]_i_3_n_0 ,\neutral_max_limit[8]_i_4_n_0 ,\neutral_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \neutral_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[9]), .Q(neutral_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \neutral_min_limit[11]_i_2 (.I0(one_inc_max_limit[11]), .O(\neutral_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[11]_i_3 (.I0(one_inc_max_limit[10]), .O(\neutral_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[5]_i_2 (.I0(one_inc_max_limit[5]), .O(\neutral_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[5]_i_3 (.I0(one_inc_max_limit[4]), .O(\neutral_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[5]_i_4 (.I0(one_inc_max_limit[3]), .O(\neutral_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_min_limit[5]_i_5 (.I0(one_inc_max_limit[2]), .O(\neutral_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_2 (.I0(one_inc_max_limit[9]), .O(\neutral_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_3 (.I0(one_inc_max_limit[8]), .O(\neutral_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_4 (.I0(one_inc_max_limit[7]), .O(\neutral_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_5 (.I0(one_inc_max_limit[6]), .O(\neutral_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[10]), .Q(neutral_min_limit[10]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[11]), .Q(neutral_min_limit[11]), .R(SS)); CARRY4 \neutral_min_limit_reg[11]_i_1 (.CI(\neutral_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\neutral_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}), .O({\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\neutral_min_limit[11]_i_2_n_0 ,\neutral_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit[1]), .Q(neutral_min_limit[1]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[2]), .Q(neutral_min_limit[2]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[3]), .Q(neutral_min_limit[3]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[4]), .Q(neutral_min_limit[4]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[5]), .Q(neutral_min_limit[5]), .R(SS)); CARRY4 \neutral_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\neutral_min_limit_reg[5]_i_1_n_0 ,\neutral_min_limit_reg[5]_i_1_n_1 ,\neutral_min_limit_reg[5]_i_1_n_2 ,\neutral_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({one_inc_max_limit[5:3],1'b0}), .O(neutral_min_limit_nxt[5:2]), .S({\neutral_min_limit[5]_i_2_n_0 ,\neutral_min_limit[5]_i_3_n_0 ,\neutral_min_limit[5]_i_4_n_0 ,\neutral_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[6]), .Q(neutral_min_limit[6]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[7]), .Q(neutral_min_limit[7]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[8]), .Q(neutral_min_limit[8]), .R(SS)); FDRE #( .INIT(1'b0)) \neutral_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[9]), .Q(neutral_min_limit[9]), .R(SS)); CARRY4 \neutral_min_limit_reg[9]_i_1 (.CI(\neutral_min_limit_reg[5]_i_1_n_0 ), .CO({\neutral_min_limit_reg[9]_i_1_n_0 ,\neutral_min_limit_reg[9]_i_1_n_1 ,\neutral_min_limit_reg[9]_i_1_n_2 ,\neutral_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(one_inc_max_limit[9:6]), .O(neutral_min_limit_nxt[9:6]), .S({\neutral_min_limit[9]_i_2_n_0 ,\neutral_min_limit[9]_i_3_n_0 ,\neutral_min_limit[9]_i_4_n_0 ,\neutral_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\one_dec_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\one_dec_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\one_dec_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\one_dec_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\one_dec_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\one_dec_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\one_dec_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\one_dec_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\one_dec_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\one_dec_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\one_dec_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[10]), .Q(one_dec_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[11]), .Q(one_dec_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_dec_max_limit_reg[11]_i_1 (.CI(\one_dec_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_dec_max_limit_reg[11]_i_1_n_2 ,\one_dec_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_dec_max_limit_nxt[11:9]}), .S({1'b0,\one_dec_max_limit[11]_i_2_n_0 ,\one_dec_max_limit[11]_i_3_n_0 ,\one_dec_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[1]), .Q(one_dec_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \one_dec_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_dec_max_limit_nxt[1]}), .S({\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]})); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[2]), .Q(one_dec_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[3]), .Q(one_dec_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[4]), .Q(one_dec_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_dec_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\one_dec_max_limit_reg[4]_i_1_n_0 ,\one_dec_max_limit_reg[4]_i_1_n_1 ,\one_dec_max_limit_reg[4]_i_1_n_2 ,\one_dec_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,1'b0,device_temp_init[2],1'b0}), .O({one_dec_max_limit_nxt[4:2],\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\one_dec_max_limit[4]_i_2_n_0 ,\one_dec_max_limit[4]_i_3_n_0 ,\one_dec_max_limit[4]_i_4_n_0 ,\one_dec_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[5]), .Q(one_dec_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[6]), .Q(one_dec_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[7]), .Q(one_dec_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[8]), .Q(one_dec_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_dec_max_limit_reg[8]_i_1 (.CI(\one_dec_max_limit_reg[4]_i_1_n_0 ), .CO({\one_dec_max_limit_reg[8]_i_1_n_0 ,\one_dec_max_limit_reg[8]_i_1_n_1 ,\one_dec_max_limit_reg[8]_i_1_n_2 ,\one_dec_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8],1'b0,device_temp_init[6:5]}), .O(one_dec_max_limit_nxt[8:5]), .S({\one_dec_max_limit[8]_i_2_n_0 ,\one_dec_max_limit[8]_i_3_n_0 ,\one_dec_max_limit[8]_i_4_n_0 ,\one_dec_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \one_dec_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[9]), .Q(one_dec_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[11]_i_2 (.I0(neutral_max_limit[11]), .O(\one_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[11]_i_3 (.I0(neutral_max_limit[10]), .O(\one_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[5]_i_2 (.I0(neutral_max_limit[5]), .O(\one_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[5]_i_3 (.I0(neutral_max_limit[4]), .O(\one_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[5]_i_4 (.I0(neutral_max_limit[3]), .O(\one_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_min_limit[5]_i_5 (.I0(neutral_max_limit[2]), .O(\one_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_2 (.I0(neutral_max_limit[9]), .O(\one_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_3 (.I0(neutral_max_limit[8]), .O(\one_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_4 (.I0(neutral_max_limit[7]), .O(\one_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_5 (.I0(neutral_max_limit[6]), .O(\one_dec_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[10]), .Q(one_dec_min_limit[10]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[11]), .Q(one_dec_min_limit[11]), .R(SS)); CARRY4 \one_dec_min_limit_reg[11]_i_1 (.CI(\one_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}), .O({\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\one_dec_min_limit[11]_i_2_n_0 ,\one_dec_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(neutral_max_limit[1]), .Q(one_dec_min_limit[1]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[2]), .Q(one_dec_min_limit[2]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[3]), .Q(one_dec_min_limit[3]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[4]), .Q(one_dec_min_limit[4]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[5]), .Q(one_dec_min_limit[5]), .R(SS)); CARRY4 \one_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\one_dec_min_limit_reg[5]_i_1_n_0 ,\one_dec_min_limit_reg[5]_i_1_n_1 ,\one_dec_min_limit_reg[5]_i_1_n_2 ,\one_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({neutral_max_limit[5:3],1'b0}), .O(one_dec_min_limit_nxt[5:2]), .S({\one_dec_min_limit[5]_i_2_n_0 ,\one_dec_min_limit[5]_i_3_n_0 ,\one_dec_min_limit[5]_i_4_n_0 ,\one_dec_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[6]), .Q(one_dec_min_limit[6]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[7]), .Q(one_dec_min_limit[7]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[8]), .Q(one_dec_min_limit[8]), .R(SS)); FDRE #( .INIT(1'b0)) \one_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[9]), .Q(one_dec_min_limit[9]), .R(SS)); CARRY4 \one_dec_min_limit_reg[9]_i_1 (.CI(\one_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\one_dec_min_limit_reg[9]_i_1_n_0 ,\one_dec_min_limit_reg[9]_i_1_n_1 ,\one_dec_min_limit_reg[9]_i_1_n_2 ,\one_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(neutral_max_limit[9:6]), .O(one_dec_min_limit_nxt[9:6]), .S({\one_dec_min_limit[9]_i_2_n_0 ,\one_dec_min_limit[9]_i_3_n_0 ,\one_dec_min_limit[9]_i_4_n_0 ,\one_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\one_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\one_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\one_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\one_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\one_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\one_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\one_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\one_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\one_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\one_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\one_inc_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[10]), .Q(one_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[11]), .Q(one_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_inc_max_limit_reg[11]_i_1 (.CI(\one_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_inc_max_limit_reg[11]_i_1_n_2 ,\one_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10:9]}), .O({\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_inc_max_limit_nxt[11:9]}), .S({1'b0,\one_inc_max_limit[11]_i_2_n_0 ,\one_inc_max_limit[11]_i_3_n_0 ,\one_inc_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[1]), .Q(one_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \one_inc_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_inc_max_limit_nxt[1]}), .S({\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]})); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[2]), .Q(one_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[3]), .Q(one_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[4]), .Q(one_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\one_inc_max_limit_reg[4]_i_1_n_0 ,\one_inc_max_limit_reg[4]_i_1_n_1 ,\one_inc_max_limit_reg[4]_i_1_n_2 ,\one_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,device_temp_init[3],1'b0,1'b0}), .O({one_inc_max_limit_nxt[4:2],\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\one_inc_max_limit[4]_i_2_n_0 ,\one_inc_max_limit[4]_i_3_n_0 ,\one_inc_max_limit[4]_i_4_n_0 ,\one_inc_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[5]), .Q(one_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[6]), .Q(one_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[7]), .Q(one_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[8]), .Q(one_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_inc_max_limit_reg[8]_i_1 (.CI(\one_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\one_inc_max_limit_reg[8]_i_1_n_0 ,\one_inc_max_limit_reg[8]_i_1_n_1 ,\one_inc_max_limit_reg[8]_i_1_n_2 ,\one_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8:7],1'b0,1'b0}), .O(one_inc_max_limit_nxt[8:5]), .S({\one_inc_max_limit[8]_i_2_n_0 ,\one_inc_max_limit[8]_i_3_n_0 ,\one_inc_max_limit[8]_i_4_n_0 ,\one_inc_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \one_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[9]), .Q(one_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[11]_i_2 (.I0(two_inc_max_limit[11]), .O(\one_inc_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[11]_i_3 (.I0(two_inc_max_limit[10]), .O(\one_inc_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[5]_i_2 (.I0(two_inc_max_limit[5]), .O(\one_inc_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[5]_i_3 (.I0(two_inc_max_limit[4]), .O(\one_inc_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[5]_i_4 (.I0(two_inc_max_limit[3]), .O(\one_inc_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_min_limit[5]_i_5 (.I0(two_inc_max_limit[2]), .O(\one_inc_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_2 (.I0(two_inc_max_limit[9]), .O(\one_inc_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_3 (.I0(two_inc_max_limit[8]), .O(\one_inc_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_4 (.I0(two_inc_max_limit[7]), .O(\one_inc_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_5 (.I0(two_inc_max_limit[6]), .O(\one_inc_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[10]), .Q(one_inc_min_limit[10]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[11]), .Q(one_inc_min_limit[11]), .R(SS)); CARRY4 \one_inc_min_limit_reg[11]_i_1 (.CI(\one_inc_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_inc_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}), .O({\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\one_inc_min_limit[11]_i_2_n_0 ,\one_inc_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit[1]), .Q(one_inc_min_limit[1]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[2]), .Q(one_inc_min_limit[2]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[3]), .Q(one_inc_min_limit[3]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[4]), .Q(one_inc_min_limit[4]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[5]), .Q(one_inc_min_limit[5]), .R(SS)); CARRY4 \one_inc_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\one_inc_min_limit_reg[5]_i_1_n_0 ,\one_inc_min_limit_reg[5]_i_1_n_1 ,\one_inc_min_limit_reg[5]_i_1_n_2 ,\one_inc_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({two_inc_max_limit[5:3],1'b0}), .O(one_inc_min_limit_nxt[5:2]), .S({\one_inc_min_limit[5]_i_2_n_0 ,\one_inc_min_limit[5]_i_3_n_0 ,\one_inc_min_limit[5]_i_4_n_0 ,\one_inc_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[6]), .Q(one_inc_min_limit[6]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[7]), .Q(one_inc_min_limit[7]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[8]), .Q(one_inc_min_limit[8]), .R(SS)); FDRE #( .INIT(1'b0)) \one_inc_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[9]), .Q(one_inc_min_limit[9]), .R(SS)); CARRY4 \one_inc_min_limit_reg[9]_i_1 (.CI(\one_inc_min_limit_reg[5]_i_1_n_0 ), .CO({\one_inc_min_limit_reg[9]_i_1_n_0 ,\one_inc_min_limit_reg[9]_i_1_n_1 ,\one_inc_min_limit_reg[9]_i_1_n_2 ,\one_inc_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(two_inc_max_limit[9:6]), .O(one_inc_min_limit_nxt[9:6]), .S({\one_inc_min_limit[9]_i_2_n_0 ,\one_inc_min_limit[9]_i_3_n_0 ,\one_inc_min_limit[9]_i_4_n_0 ,\one_inc_min_limit[9]_i_5_n_0 })); LUT4 #( .INIT(16'hF080)) pi_f_dec_i_1 (.I0(update_temp_102), .I1(pi_f_dec_i_2_n_0), .I2(\tempmon_state[10]_i_7_n_0 ), .I3(\tempmon_state[10]_i_3_n_0 ), .O(pi_f_dec_nxt)); LUT6 #( .INIT(64'hFFFFF888F888F888)) pi_f_dec_i_2 (.I0(temp_cmp_three_inc_max_102), .I1(tempmon_state[3]), .I2(tempmon_state[5]), .I3(temp_cmp_one_inc_max_102), .I4(tempmon_state[4]), .I5(temp_cmp_two_inc_max_102), .O(pi_f_dec_i_2_n_0)); FDRE #( .INIT(1'b0)) pi_f_dec_reg (.C(CLK), .CE(1'b1), .D(pi_f_dec_nxt), .Q(tempmon_pi_f_dec), .R(SS)); LUT6 #( .INIT(64'hEFEEEEEEEEEEEEEE)) pi_f_inc_i_1 (.I0(pi_f_inc_i_2_n_0), .I1(pi_f_inc_i_3_n_0), .I2(temp_gte_three_dec_max), .I3(tempmon_state[9]), .I4(temp_cmp_three_dec_min_102), .I5(pi_f_inc_i_5_n_0), .O(pi_f_inc_nxt)); LUT4 #( .INIT(16'h0800)) pi_f_inc_i_10 (.I0(tempmon_state[5]), .I1(update_temp_102), .I2(temp_cmp_one_inc_max_102), .I3(temp_cmp_one_inc_min_102), .O(pi_f_inc_i_10_n_0)); LUT6 #( .INIT(64'hFAEAEAEAEAEAEAEA)) pi_f_inc_i_2 (.I0(pi_f_inc_i_6_n_0), .I1(pi_f_inc_i_7_n_0), .I2(\tempmon_state[10]_i_7_n_0 ), .I3(tempmon_state[10]), .I4(temp_cmp_four_dec_min_102), .I5(update_temp_102), .O(pi_f_inc_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT5 #( .INIT(32'h40000000)) pi_f_inc_i_3 (.I0(temp_cmp_two_dec_max_102), .I1(tempmon_state[8]), .I2(temp_cmp_two_dec_min_102), .I3(update_temp_102), .I4(\tempmon_state[10]_i_7_n_0 ), .O(pi_f_inc_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT2 #( .INIT(4'h8)) pi_f_inc_i_4 (.I0(update_temp_102), .I1(temp_cmp_three_dec_max_102), .O(temp_gte_three_dec_max)); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT2 #( .INIT(4'h8)) pi_f_inc_i_5 (.I0(\tempmon_state[10]_i_7_n_0 ), .I1(update_temp_102), .O(pi_f_inc_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00008000)) pi_f_inc_i_6 (.I0(\tempmon_state[10]_i_7_n_0 ), .I1(update_temp_102), .I2(temp_cmp_one_dec_min_102), .I3(tempmon_state[7]), .I4(temp_cmp_one_dec_max_102), .I5(pi_f_inc_i_8_n_0), .O(pi_f_inc_i_6_n_0)); LUT6 #( .INIT(64'hFFFFFFFFAAEAAAAA)) pi_f_inc_i_7 (.I0(pi_f_inc_i_9_n_0), .I1(tempmon_state[4]), .I2(update_temp_102), .I3(temp_cmp_two_inc_max_102), .I4(temp_cmp_two_inc_min_102), .I5(pi_f_inc_i_10_n_0), .O(pi_f_inc_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT5 #( .INIT(32'h40000000)) pi_f_inc_i_8 (.I0(temp_cmp_neutral_max_102), .I1(tempmon_state[6]), .I2(temp_cmp_neutral_min_102), .I3(update_temp_102), .I4(\tempmon_state[10]_i_7_n_0 ), .O(pi_f_inc_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'h0800)) pi_f_inc_i_9 (.I0(tempmon_state[3]), .I1(update_temp_102), .I2(temp_cmp_three_inc_max_102), .I3(temp_cmp_three_inc_min_102), .O(pi_f_inc_i_9_n_0)); FDRE #( .INIT(1'b0)) pi_f_inc_reg (.C(CLK), .CE(1'b1), .D(pi_f_inc_nxt), .Q(tempmon_pi_f_inc), .R(rstdiv0_sync_r1_reg_rep__2)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_10 (.I0(four_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(four_dec_min_limit[1]), .O(temp_cmp_four_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_11 (.I0(four_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(four_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_four_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_12 (.I0(four_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(four_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_four_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_13 (.I0(four_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(four_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_four_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_14 (.I0(four_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(four_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_four_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_3 (.I0(four_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(four_dec_min_limit[11]), .O(temp_cmp_four_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_4 (.I0(four_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(four_dec_min_limit[9]), .O(temp_cmp_four_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_5 (.I0(four_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(four_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_four_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_6 (.I0(four_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(four_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_four_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_7 (.I0(four_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(four_dec_min_limit[7]), .O(temp_cmp_four_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_8 (.I0(four_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(four_dec_min_limit[5]), .O(temp_cmp_four_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_9 (.I0(four_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(four_dec_min_limit[3]), .O(temp_cmp_four_dec_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_four_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_four_dec_min_101), .Q(temp_cmp_four_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_four_dec_min_102_reg_i_1 (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_four_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(four_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_four_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(four_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(four_inc_max_limit[7]), .O(temp_cmp_four_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(four_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(four_inc_max_limit[5]), .O(temp_cmp_four_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(four_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(four_inc_max_limit[3]), .O(temp_cmp_four_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(four_inc_max_limit[1]), .O(temp_cmp_four_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(four_inc_max_limit[10]), .I2(four_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_four_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(four_inc_max_limit[8]), .I2(four_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_four_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(four_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(four_inc_max_limit[11]), .O(temp_cmp_four_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(four_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(four_inc_max_limit[9]), .O(temp_cmp_four_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(four_inc_max_limit[6]), .I2(four_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_four_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(four_inc_max_limit[4]), .I2(four_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_four_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(four_inc_max_limit[2]), .I2(four_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_four_inc_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_four_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_four_inc_max_101), .Q(temp_cmp_four_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_four_inc_max_102_reg_i_1 (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_four_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(neutral_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_neutral_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_11 (.I0(device_temp_101[6]), .I1(neutral_max_limit[6]), .I2(device_temp_101[7]), .I3(neutral_max_limit[7]), .O(temp_cmp_neutral_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_12 (.I0(device_temp_101[4]), .I1(neutral_max_limit[4]), .I2(device_temp_101[5]), .I3(neutral_max_limit[5]), .O(temp_cmp_neutral_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_13 (.I0(device_temp_101[2]), .I1(neutral_max_limit[2]), .I2(device_temp_101[3]), .I3(neutral_max_limit[3]), .O(temp_cmp_neutral_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(neutral_max_limit[1]), .O(temp_cmp_neutral_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_3 (.I0(device_temp_101[10]), .I1(neutral_max_limit[10]), .I2(neutral_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_neutral_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_4 (.I0(device_temp_101[8]), .I1(neutral_max_limit[8]), .I2(neutral_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_neutral_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_5 (.I0(device_temp_101[10]), .I1(neutral_max_limit[10]), .I2(device_temp_101[11]), .I3(neutral_max_limit[11]), .O(temp_cmp_neutral_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_6 (.I0(device_temp_101[8]), .I1(neutral_max_limit[8]), .I2(device_temp_101[9]), .I3(neutral_max_limit[9]), .O(temp_cmp_neutral_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_7 (.I0(device_temp_101[6]), .I1(neutral_max_limit[6]), .I2(neutral_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_neutral_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_8 (.I0(device_temp_101[4]), .I1(neutral_max_limit[4]), .I2(neutral_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_neutral_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_9 (.I0(device_temp_101[2]), .I1(neutral_max_limit[2]), .I2(neutral_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_neutral_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_neutral_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_neutral_max_101), .Q(temp_cmp_neutral_max_102), .R(1'b0)); CARRY4 temp_cmp_neutral_max_102_reg_i_1 (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}), .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0})); CARRY4 temp_cmp_neutral_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}), .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(neutral_min_limit[1]), .O(temp_cmp_neutral_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_11 (.I0(neutral_min_limit[6]), .I1(device_temp_101[6]), .I2(neutral_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_neutral_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_12 (.I0(neutral_min_limit[4]), .I1(device_temp_101[4]), .I2(neutral_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_neutral_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_13 (.I0(neutral_min_limit[2]), .I1(device_temp_101[2]), .I2(neutral_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_neutral_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(neutral_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_neutral_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_3 (.I0(neutral_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(neutral_min_limit[11]), .O(temp_cmp_neutral_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_4 (.I0(neutral_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(neutral_min_limit[9]), .O(temp_cmp_neutral_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_5 (.I0(neutral_min_limit[10]), .I1(device_temp_101[10]), .I2(neutral_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_neutral_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_6 (.I0(neutral_min_limit[8]), .I1(device_temp_101[8]), .I2(neutral_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_neutral_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_7 (.I0(neutral_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(neutral_min_limit[7]), .O(temp_cmp_neutral_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_8 (.I0(neutral_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(neutral_min_limit[5]), .O(temp_cmp_neutral_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_9 (.I0(neutral_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(neutral_min_limit[3]), .O(temp_cmp_neutral_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_neutral_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_neutral_min_101), .Q(temp_cmp_neutral_min_102), .R(1'b0)); CARRY4 temp_cmp_neutral_min_102_reg_i_1 (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}), .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0})); CARRY4 temp_cmp_neutral_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}), .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(one_dec_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_dec_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_11 (.I0(device_temp_101[6]), .I1(one_dec_max_limit[6]), .I2(device_temp_101[7]), .I3(one_dec_max_limit[7]), .O(temp_cmp_one_dec_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_12 (.I0(device_temp_101[4]), .I1(one_dec_max_limit[4]), .I2(device_temp_101[5]), .I3(one_dec_max_limit[5]), .O(temp_cmp_one_dec_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_13 (.I0(device_temp_101[2]), .I1(one_dec_max_limit[2]), .I2(device_temp_101[3]), .I3(one_dec_max_limit[3]), .O(temp_cmp_one_dec_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(one_dec_max_limit[1]), .O(temp_cmp_one_dec_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_3 (.I0(device_temp_101[10]), .I1(one_dec_max_limit[10]), .I2(one_dec_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_dec_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_4 (.I0(device_temp_101[8]), .I1(one_dec_max_limit[8]), .I2(one_dec_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_dec_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_5 (.I0(device_temp_101[10]), .I1(one_dec_max_limit[10]), .I2(device_temp_101[11]), .I3(one_dec_max_limit[11]), .O(temp_cmp_one_dec_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_6 (.I0(device_temp_101[8]), .I1(one_dec_max_limit[8]), .I2(device_temp_101[9]), .I3(one_dec_max_limit[9]), .O(temp_cmp_one_dec_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_7 (.I0(device_temp_101[6]), .I1(one_dec_max_limit[6]), .I2(one_dec_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_dec_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_8 (.I0(device_temp_101[4]), .I1(one_dec_max_limit[4]), .I2(one_dec_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_dec_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_9 (.I0(device_temp_101[2]), .I1(one_dec_max_limit[2]), .I2(one_dec_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_dec_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_one_dec_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_dec_max_101), .Q(temp_cmp_one_dec_max_102), .R(1'b0)); CARRY4 temp_cmp_one_dec_max_102_reg_i_1 (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}), .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0})); CARRY4 temp_cmp_one_dec_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}), .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(one_dec_min_limit[1]), .O(temp_cmp_one_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_11 (.I0(one_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(one_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_12 (.I0(one_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(one_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_13 (.I0(one_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(one_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(one_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_3 (.I0(one_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(one_dec_min_limit[11]), .O(temp_cmp_one_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_4 (.I0(one_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(one_dec_min_limit[9]), .O(temp_cmp_one_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_5 (.I0(one_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(one_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_6 (.I0(one_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(one_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_7 (.I0(one_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(one_dec_min_limit[7]), .O(temp_cmp_one_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_8 (.I0(one_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(one_dec_min_limit[5]), .O(temp_cmp_one_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_9 (.I0(one_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(one_dec_min_limit[3]), .O(temp_cmp_one_dec_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_one_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_dec_min_101), .Q(temp_cmp_one_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_one_dec_min_102_reg_i_1 (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_one_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(one_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(one_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(one_inc_max_limit[7]), .O(temp_cmp_one_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(one_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(one_inc_max_limit[5]), .O(temp_cmp_one_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(one_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(one_inc_max_limit[3]), .O(temp_cmp_one_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(one_inc_max_limit[1]), .O(temp_cmp_one_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(one_inc_max_limit[10]), .I2(one_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(one_inc_max_limit[8]), .I2(one_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(one_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(one_inc_max_limit[11]), .O(temp_cmp_one_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(one_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(one_inc_max_limit[9]), .O(temp_cmp_one_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(one_inc_max_limit[6]), .I2(one_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(one_inc_max_limit[4]), .I2(one_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(one_inc_max_limit[2]), .I2(one_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_inc_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_one_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_inc_max_101), .Q(temp_cmp_one_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_one_inc_max_102_reg_i_1 (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_one_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(one_inc_min_limit[1]), .O(temp_cmp_one_inc_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_11 (.I0(one_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(one_inc_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_inc_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_12 (.I0(one_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(one_inc_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_inc_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_13 (.I0(one_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(one_inc_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_inc_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(one_inc_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_inc_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_3 (.I0(one_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(one_inc_min_limit[11]), .O(temp_cmp_one_inc_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_4 (.I0(one_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(one_inc_min_limit[9]), .O(temp_cmp_one_inc_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_5 (.I0(one_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(one_inc_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_inc_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_6 (.I0(one_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(one_inc_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_inc_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_7 (.I0(one_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(one_inc_min_limit[7]), .O(temp_cmp_one_inc_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_8 (.I0(one_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(one_inc_min_limit[5]), .O(temp_cmp_one_inc_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_9 (.I0(one_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(one_inc_min_limit[3]), .O(temp_cmp_one_inc_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_one_inc_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_inc_min_101), .Q(temp_cmp_one_inc_min_102), .R(1'b0)); CARRY4 temp_cmp_one_inc_min_102_reg_i_1 (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}), .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0})); CARRY4 temp_cmp_one_inc_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}), .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_10 (.I0(device_temp_101[0]), .I1(three_dec_max_limit[0]), .I2(three_dec_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_dec_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_11 (.I0(device_temp_101[6]), .I1(three_dec_max_limit[6]), .I2(device_temp_101[7]), .I3(three_dec_max_limit[7]), .O(temp_cmp_three_dec_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_12 (.I0(device_temp_101[4]), .I1(three_dec_max_limit[4]), .I2(device_temp_101[5]), .I3(three_dec_max_limit[5]), .O(temp_cmp_three_dec_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_13 (.I0(device_temp_101[2]), .I1(three_dec_max_limit[2]), .I2(device_temp_101[3]), .I3(three_dec_max_limit[3]), .O(temp_cmp_three_dec_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_14 (.I0(device_temp_101[0]), .I1(three_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(three_dec_max_limit[1]), .O(temp_cmp_three_dec_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_3 (.I0(device_temp_101[10]), .I1(three_dec_max_limit[10]), .I2(three_dec_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_dec_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_4 (.I0(device_temp_101[8]), .I1(three_dec_max_limit[8]), .I2(three_dec_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_dec_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_5 (.I0(device_temp_101[10]), .I1(three_dec_max_limit[10]), .I2(device_temp_101[11]), .I3(three_dec_max_limit[11]), .O(temp_cmp_three_dec_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_6 (.I0(device_temp_101[8]), .I1(three_dec_max_limit[8]), .I2(device_temp_101[9]), .I3(three_dec_max_limit[9]), .O(temp_cmp_three_dec_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_7 (.I0(device_temp_101[6]), .I1(three_dec_max_limit[6]), .I2(three_dec_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_dec_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_8 (.I0(device_temp_101[4]), .I1(three_dec_max_limit[4]), .I2(three_dec_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_dec_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_9 (.I0(device_temp_101[2]), .I1(three_dec_max_limit[2]), .I2(three_dec_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_dec_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_three_dec_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_dec_max_101), .Q(temp_cmp_three_dec_max_102), .R(1'b0)); CARRY4 temp_cmp_three_dec_max_102_reg_i_1 (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}), .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0})); CARRY4 temp_cmp_three_dec_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}), .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(three_dec_min_limit[1]), .O(temp_cmp_three_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_11 (.I0(three_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(three_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_12 (.I0(three_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(three_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_13 (.I0(three_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(three_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(three_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_3 (.I0(three_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(three_dec_min_limit[11]), .O(temp_cmp_three_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_4 (.I0(three_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(three_dec_min_limit[9]), .O(temp_cmp_three_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_5 (.I0(three_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(three_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_6 (.I0(three_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(three_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_7 (.I0(three_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(three_dec_min_limit[7]), .O(temp_cmp_three_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_8 (.I0(three_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(three_dec_min_limit[5]), .O(temp_cmp_three_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_9 (.I0(three_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(three_dec_min_limit[3]), .O(temp_cmp_three_dec_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_three_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_dec_min_101), .Q(temp_cmp_three_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_three_dec_min_102_reg_i_1 (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_three_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(three_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(three_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(three_inc_max_limit[7]), .O(temp_cmp_three_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(three_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(three_inc_max_limit[5]), .O(temp_cmp_three_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(three_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(three_inc_max_limit[3]), .O(temp_cmp_three_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(three_inc_max_limit[1]), .O(temp_cmp_three_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(three_inc_max_limit[10]), .I2(three_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(three_inc_max_limit[8]), .I2(three_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(three_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(three_inc_max_limit[11]), .O(temp_cmp_three_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(three_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(three_inc_max_limit[9]), .O(temp_cmp_three_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(three_inc_max_limit[6]), .I2(three_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(three_inc_max_limit[4]), .I2(three_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(three_inc_max_limit[2]), .I2(three_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_inc_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_three_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_inc_max_101), .Q(temp_cmp_three_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_three_inc_max_102_reg_i_1 (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_three_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(three_inc_min_limit[1]), .O(temp_cmp_three_inc_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_11 (.I0(three_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(three_inc_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_inc_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_12 (.I0(three_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(three_inc_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_inc_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_13 (.I0(three_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(three_inc_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_inc_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(three_inc_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_inc_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_3 (.I0(three_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(three_inc_min_limit[11]), .O(temp_cmp_three_inc_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_4 (.I0(three_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(three_inc_min_limit[9]), .O(temp_cmp_three_inc_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_5 (.I0(three_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(three_inc_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_inc_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_6 (.I0(three_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(three_inc_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_inc_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_7 (.I0(three_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(three_inc_min_limit[7]), .O(temp_cmp_three_inc_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_8 (.I0(three_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(three_inc_min_limit[5]), .O(temp_cmp_three_inc_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_9 (.I0(three_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(three_inc_min_limit[3]), .O(temp_cmp_three_inc_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_three_inc_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_inc_min_101), .Q(temp_cmp_three_inc_min_102), .R(1'b0)); CARRY4 temp_cmp_three_inc_min_102_reg_i_1 (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}), .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0})); CARRY4 temp_cmp_three_inc_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}), .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(two_dec_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_dec_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_11 (.I0(device_temp_101[6]), .I1(two_dec_max_limit[6]), .I2(device_temp_101[7]), .I3(two_dec_max_limit[7]), .O(temp_cmp_two_dec_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_12 (.I0(device_temp_101[4]), .I1(two_dec_max_limit[4]), .I2(device_temp_101[5]), .I3(two_dec_max_limit[5]), .O(temp_cmp_two_dec_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_13 (.I0(device_temp_101[2]), .I1(two_dec_max_limit[2]), .I2(device_temp_101[3]), .I3(two_dec_max_limit[3]), .O(temp_cmp_two_dec_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(two_dec_max_limit[1]), .O(temp_cmp_two_dec_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_3 (.I0(device_temp_101[10]), .I1(two_dec_max_limit[10]), .I2(two_dec_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_dec_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_4 (.I0(device_temp_101[8]), .I1(two_dec_max_limit[8]), .I2(two_dec_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_dec_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_5 (.I0(device_temp_101[10]), .I1(two_dec_max_limit[10]), .I2(device_temp_101[11]), .I3(two_dec_max_limit[11]), .O(temp_cmp_two_dec_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_6 (.I0(device_temp_101[8]), .I1(two_dec_max_limit[8]), .I2(device_temp_101[9]), .I3(two_dec_max_limit[9]), .O(temp_cmp_two_dec_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_7 (.I0(device_temp_101[6]), .I1(two_dec_max_limit[6]), .I2(two_dec_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_dec_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_8 (.I0(device_temp_101[4]), .I1(two_dec_max_limit[4]), .I2(two_dec_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_dec_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_9 (.I0(device_temp_101[2]), .I1(two_dec_max_limit[2]), .I2(two_dec_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_dec_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_two_dec_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_dec_max_101), .Q(temp_cmp_two_dec_max_102), .R(1'b0)); CARRY4 temp_cmp_two_dec_max_102_reg_i_1 (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}), .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0})); CARRY4 temp_cmp_two_dec_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}), .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(two_dec_min_limit[1]), .O(temp_cmp_two_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_11 (.I0(two_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(two_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_12 (.I0(two_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(two_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_13 (.I0(two_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(two_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(two_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_3 (.I0(two_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(two_dec_min_limit[11]), .O(temp_cmp_two_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_4 (.I0(two_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(two_dec_min_limit[9]), .O(temp_cmp_two_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_5 (.I0(two_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(two_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_6 (.I0(two_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(two_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_7 (.I0(two_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(two_dec_min_limit[7]), .O(temp_cmp_two_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_8 (.I0(two_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(two_dec_min_limit[5]), .O(temp_cmp_two_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_9 (.I0(two_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(two_dec_min_limit[3]), .O(temp_cmp_two_dec_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_two_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_dec_min_101), .Q(temp_cmp_two_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_two_dec_min_102_reg_i_1 (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_two_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(two_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(two_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(two_inc_max_limit[7]), .O(temp_cmp_two_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(two_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(two_inc_max_limit[5]), .O(temp_cmp_two_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(two_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(two_inc_max_limit[3]), .O(temp_cmp_two_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(two_inc_max_limit[1]), .O(temp_cmp_two_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(two_inc_max_limit[10]), .I2(two_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(two_inc_max_limit[8]), .I2(two_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(two_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(two_inc_max_limit[11]), .O(temp_cmp_two_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(two_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(two_inc_max_limit[9]), .O(temp_cmp_two_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(two_inc_max_limit[6]), .I2(two_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(two_inc_max_limit[4]), .I2(two_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(two_inc_max_limit[2]), .I2(two_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_inc_max_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_two_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_inc_max_101), .Q(temp_cmp_two_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_two_inc_max_102_reg_i_1 (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_two_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(two_inc_min_limit[1]), .O(temp_cmp_two_inc_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_11 (.I0(two_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(two_inc_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_inc_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_12 (.I0(two_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(two_inc_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_inc_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_13 (.I0(two_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(two_inc_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_inc_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(two_inc_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_inc_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_3 (.I0(two_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(two_inc_min_limit[11]), .O(temp_cmp_two_inc_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_4 (.I0(two_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(two_inc_min_limit[9]), .O(temp_cmp_two_inc_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_5 (.I0(two_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(two_inc_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_inc_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_6 (.I0(two_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(two_inc_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_inc_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_7 (.I0(two_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(two_inc_min_limit[7]), .O(temp_cmp_two_inc_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_8 (.I0(two_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(two_inc_min_limit[5]), .O(temp_cmp_two_inc_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_9 (.I0(two_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(two_inc_min_limit[3]), .O(temp_cmp_two_inc_min_102_i_9_n_0)); FDRE #( .INIT(1'b0)) temp_cmp_two_inc_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_inc_min_101), .Q(temp_cmp_two_inc_min_102), .R(1'b0)); CARRY4 temp_cmp_two_inc_min_102_reg_i_1 (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}), .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0})); CARRY4 temp_cmp_two_inc_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}), .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0})); FDRE #( .INIT(1'b0)) tempmon_init_complete_reg (.C(CLK), .CE(tempmon_state_init), .D(tempmon_state_init), .Q(tempmon_init_complete), .R(SS)); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT2 #( .INIT(4'hE)) tempmon_pi_f_en_r_i_1 (.I0(tempmon_pi_f_inc), .I1(tempmon_pi_f_dec), .O(tempmon_sel_pi_incdec)); FDRE #( .INIT(1'b0)) tempmon_sample_en_101_reg (.C(CLK), .CE(1'b1), .D(tempmon_sample_en), .Q(tempmon_sample_en_101), .R(SS)); FDRE #( .INIT(1'b0)) tempmon_sample_en_102_reg (.C(CLK), .CE(1'b1), .D(tempmon_sample_en_101), .Q(tempmon_sample_en_102), .R(SS)); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT1 #( .INIT(2'h1)) \tempmon_state[0]_i_2 (.I0(\tempmon_state[10]_i_7_n_0 ), .O(\tempmon_state[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFEAFFFFFFFF)) \tempmon_state[10]_i_1 (.I0(\tempmon_state[10]_i_3_n_0 ), .I1(\tempmon_state[10]_i_4_n_0 ), .I2(update_temp_102), .I3(\tempmon_state[10]_i_5_n_0 ), .I4(\tempmon_state[10]_i_6_n_0 ), .I5(\tempmon_state[10]_i_7_n_0 ), .O(tempmon_state_nxt)); LUT3 #( .INIT(8'h80)) \tempmon_state[10]_i_10 (.I0(update_temp_102), .I1(temp_cmp_four_dec_min_102), .I2(tempmon_state[10]), .O(\tempmon_state[10]_i_10_n_0 )); LUT5 #( .INIT(32'hF0808080)) \tempmon_state[10]_i_11 (.I0(tempmon_state[5]), .I1(temp_cmp_one_inc_min_102), .I2(update_temp_102), .I3(tempmon_state[4]), .I4(temp_cmp_two_inc_min_102), .O(\tempmon_state[10]_i_11_n_0 )); LUT6 #( .INIT(64'hFFEAEAEAEAEAEAEA)) \tempmon_state[10]_i_12 (.I0(tempmon_state[1]), .I1(calib_complete), .I2(tempmon_state[0]), .I3(update_temp_102), .I4(tempmon_state[9]), .I5(temp_cmp_three_dec_min_102), .O(\tempmon_state[10]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT5 #( .INIT(32'h00010116)) \tempmon_state[10]_i_13 (.I0(tempmon_state[0]), .I1(tempmon_state[1]), .I2(tempmon_state[2]), .I3(tempmon_state[3]), .I4(tempmon_state[4]), .O(\tempmon_state[10]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT5 #( .INIT(32'hFFFEFEE8)) \tempmon_state[10]_i_14 (.I0(tempmon_state[0]), .I1(tempmon_state[1]), .I2(tempmon_state[2]), .I3(tempmon_state[3]), .I4(tempmon_state[4]), .O(\tempmon_state[10]_i_14_n_0 )); LUT6 #( .INIT(64'h0000000100010116)) \tempmon_state[10]_i_15 (.I0(tempmon_state[5]), .I1(tempmon_state[6]), .I2(tempmon_state[7]), .I3(tempmon_state[8]), .I4(tempmon_state[9]), .I5(tempmon_state[10]), .O(\tempmon_state[10]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFEFEE8)) \tempmon_state[10]_i_16 (.I0(tempmon_state[5]), .I1(tempmon_state[6]), .I2(tempmon_state[7]), .I3(tempmon_state[8]), .I4(tempmon_state[9]), .I5(tempmon_state[10]), .O(\tempmon_state[10]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT4 #( .INIT(16'h8000)) \tempmon_state[10]_i_2 (.I0(tempmon_state[9]), .I1(\tempmon_state[10]_i_7_n_0 ), .I2(temp_cmp_three_dec_max_102), .I3(update_temp_102), .O(\tempmon_state[10]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFF80)) \tempmon_state[10]_i_3 (.I0(temp_cmp_four_inc_max_102), .I1(update_temp_102), .I2(tempmon_state[2]), .I3(\tempmon_state[10]_i_8_n_0 ), .I4(\tempmon_state[10]_i_9_n_0 ), .O(\tempmon_state[10]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT2 #( .INIT(4'h8)) \tempmon_state[10]_i_4 (.I0(tempmon_state[6]), .I1(temp_cmp_neutral_min_102), .O(\tempmon_state[10]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFAAEAAA)) \tempmon_state[10]_i_5 (.I0(\tempmon_state[10]_i_10_n_0 ), .I1(tempmon_state[3]), .I2(temp_cmp_three_inc_min_102), .I3(update_temp_102), .I4(pi_f_dec_i_2_n_0), .I5(\tempmon_state[10]_i_11_n_0 ), .O(\tempmon_state[10]_i_5_n_0 )); LUT6 #( .INIT(64'hFFAAEAAAEAAAEAAA)) \tempmon_state[10]_i_6 (.I0(\tempmon_state[10]_i_12_n_0 ), .I1(temp_cmp_one_dec_min_102), .I2(tempmon_state[7]), .I3(update_temp_102), .I4(temp_cmp_two_dec_min_102), .I5(tempmon_state[8]), .O(\tempmon_state[10]_i_6_n_0 )); LUT4 #( .INIT(16'h0012)) \tempmon_state[10]_i_7 (.I0(\tempmon_state[10]_i_13_n_0 ), .I1(\tempmon_state[10]_i_14_n_0 ), .I2(\tempmon_state[10]_i_15_n_0 ), .I3(\tempmon_state[10]_i_16_n_0 ), .O(\tempmon_state[10]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT5 #( .INIT(32'hF0808080)) \tempmon_state[10]_i_8 (.I0(temp_cmp_two_dec_max_102), .I1(tempmon_state[8]), .I2(update_temp_102), .I3(temp_cmp_three_dec_max_102), .I4(tempmon_state[9]), .O(\tempmon_state[10]_i_8_n_0 )); LUT5 #( .INIT(32'hF0808080)) \tempmon_state[10]_i_9 (.I0(temp_cmp_neutral_max_102), .I1(tempmon_state[6]), .I2(update_temp_102), .I3(temp_cmp_one_dec_max_102), .I4(tempmon_state[7]), .O(\tempmon_state[10]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT2 #( .INIT(4'h8)) \tempmon_state[1]_i_1 (.I0(\tempmon_state[10]_i_7_n_0 ), .I1(tempmon_state[0]), .O(\tempmon_state[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'h0888)) \tempmon_state[2]_i_1 (.I0(tempmon_state[3]), .I1(\tempmon_state[10]_i_7_n_0 ), .I2(update_temp_102), .I3(temp_cmp_three_inc_max_102), .O(\tempmon_state[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT5 #( .INIT(32'hFF007000)) \tempmon_state[3]_i_1 (.I0(temp_cmp_two_inc_max_102), .I1(update_temp_102), .I2(tempmon_state[4]), .I3(\tempmon_state[10]_i_7_n_0 ), .I4(tempmon_state[2]), .O(\tempmon_state[3]_i_1_n_0 )); LUT6 #( .INIT(64'h8FFF000088000000)) \tempmon_state[4]_i_1 (.I0(tempmon_state[3]), .I1(temp_cmp_three_inc_max_102), .I2(temp_cmp_one_inc_max_102), .I3(update_temp_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[5]), .O(\tempmon_state[4]_i_1_n_0 )); LUT6 #( .INIT(64'h8FFF000080800000)) \tempmon_state[5]_i_1 (.I0(tempmon_state[4]), .I1(temp_cmp_two_inc_max_102), .I2(update_temp_102), .I3(temp_cmp_neutral_max_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[6]), .O(\tempmon_state[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFF00EE00AE00EE00)) \tempmon_state[6]_i_1 (.I0(tempmon_state[1]), .I1(tempmon_state[7]), .I2(temp_cmp_one_dec_max_102), .I3(\tempmon_state[10]_i_7_n_0 ), .I4(update_temp_102), .I5(\tempmon_state[6]_i_2_n_0 ), .O(\tempmon_state[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT2 #( .INIT(4'h8)) \tempmon_state[6]_i_2 (.I0(tempmon_state[5]), .I1(temp_cmp_one_inc_max_102), .O(\tempmon_state[6]_i_2_n_0 )); LUT6 #( .INIT(64'hFC4C00004C4C0000)) \tempmon_state[7]_i_1 (.I0(temp_cmp_two_dec_max_102), .I1(tempmon_state[8]), .I2(update_temp_102), .I3(temp_cmp_neutral_max_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[6]), .O(\tempmon_state[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFC4C00004C4C0000)) \tempmon_state[8]_i_1 (.I0(temp_cmp_three_dec_max_102), .I1(tempmon_state[9]), .I2(update_temp_102), .I3(temp_cmp_one_dec_max_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[7]), .O(\tempmon_state[8]_i_1_n_0 )); LUT5 #( .INIT(32'hFF800000)) \tempmon_state[9]_i_1 (.I0(update_temp_102), .I1(temp_cmp_two_dec_max_102), .I2(tempmon_state[8]), .I3(tempmon_state[10]), .I4(\tempmon_state[10]_i_7_n_0 ), .O(\tempmon_state[9]_i_1_n_0 )); FDSE #( .INIT(1'b1)) \tempmon_state_reg[0] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[0]_i_2_n_0 ), .Q(tempmon_state[0]), .S(SS)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[10] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[10]_i_2_n_0 ), .Q(tempmon_state[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[1] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[1]_i_1_n_0 ), .Q(tempmon_state[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[2] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[2]_i_1_n_0 ), .Q(tempmon_state[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[3] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[3]_i_1_n_0 ), .Q(tempmon_state[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[4] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[4]_i_1_n_0 ), .Q(tempmon_state[4]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[5] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[5]_i_1_n_0 ), .Q(tempmon_state[5]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[6] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[6]_i_1_n_0 ), .Q(tempmon_state[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[7] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[7]_i_1_n_0 ), .Q(tempmon_state[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[8] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[8]_i_1_n_0 ), .Q(tempmon_state[8]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \tempmon_state_reg[9] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[9]_i_1_n_0 ), .Q(tempmon_state[9]), .R(rstdiv0_sync_r1_reg_rep__4)); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT2 #( .INIT(4'hB)) \three_dec_max_limit[0]_i_1 (.I0(p_0_in), .I1(device_temp_init[0]), .O(\three_dec_max_limit[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[10]_i_1 (.I0(\three_dec_max_limit_reg[11]_i_2_n_6 ), .I1(p_0_in), .O(\three_dec_max_limit[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[11]_i_1 (.I0(\three_dec_max_limit_reg[11]_i_2_n_5 ), .I1(p_0_in), .O(\three_dec_max_limit[11]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[11]_i_3 (.I0(device_temp_init[11]), .O(\three_dec_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[11]_i_4 (.I0(device_temp_init[10]), .O(\three_dec_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_max_limit[11]_i_5 (.I0(device_temp_init[9]), .O(\three_dec_max_limit[11]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[1]_i_1 (.I0(\three_dec_max_limit_reg[1]_i_2_n_0 ), .I1(p_0_in), .O(\three_dec_max_limit[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[2]_i_1 (.I0(\three_dec_max_limit_reg[4]_i_2_n_6 ), .I1(p_0_in), .O(\three_dec_max_limit[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[3]_i_1 (.I0(\three_dec_max_limit_reg[4]_i_2_n_5 ), .I1(p_0_in), .O(\three_dec_max_limit[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[4]_i_1 (.I0(\three_dec_max_limit_reg[4]_i_2_n_4 ), .I1(p_0_in), .O(\three_dec_max_limit[4]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_3 (.I0(device_temp_init[4]), .O(\three_dec_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_4 (.I0(device_temp_init[3]), .O(\three_dec_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_5 (.I0(device_temp_init[2]), .O(\three_dec_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_6 (.I0(device_temp_init[1]), .O(\three_dec_max_limit[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[5]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_7 ), .I1(p_0_in), .O(\three_dec_max_limit[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[6]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_6 ), .I1(p_0_in), .O(\three_dec_max_limit[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[7]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_5 ), .I1(p_0_in), .O(\three_dec_max_limit[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[8]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_4 ), .I1(p_0_in), .O(\three_dec_max_limit[8]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_max_limit[8]_i_3 (.I0(device_temp_init[8]), .O(\three_dec_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[8]_i_4 (.I0(device_temp_init[7]), .O(\three_dec_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_max_limit[8]_i_5 (.I0(device_temp_init[6]), .O(\three_dec_max_limit[8]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[8]_i_6 (.I0(device_temp_init[5]), .O(\three_dec_max_limit[8]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[9]_i_1 (.I0(\three_dec_max_limit_reg[11]_i_2_n_7 ), .I1(p_0_in), .O(\three_dec_max_limit[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[0] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[0]_i_1_n_0 ), .Q(three_dec_max_limit[0]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[10]_i_1_n_0 ), .Q(three_dec_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[11]_i_1_n_0 ), .Q(three_dec_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \three_dec_max_limit_reg[11]_i_2 (.CI(\three_dec_max_limit_reg[8]_i_2_n_0 ), .CO({p_0_in,\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED [2],\three_dec_max_limit_reg[11]_i_2_n_2 ,\three_dec_max_limit_reg[11]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,device_temp_init[9]}), .O({\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED [3],\three_dec_max_limit_reg[11]_i_2_n_5 ,\three_dec_max_limit_reg[11]_i_2_n_6 ,\three_dec_max_limit_reg[11]_i_2_n_7 }), .S({1'b1,\three_dec_max_limit[11]_i_3_n_0 ,\three_dec_max_limit[11]_i_4_n_0 ,\three_dec_max_limit[11]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[1]_i_1_n_0 ), .Q(three_dec_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__7)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \three_dec_max_limit_reg[1]_i_2_CARRY4 (.CI(1'b0), .CO(\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED [3:1],\three_dec_max_limit_reg[1]_i_2_n_0 }), .S({\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]})); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[2]_i_1_n_0 ), .Q(three_dec_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[3]_i_1_n_0 ), .Q(three_dec_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[4]_i_1_n_0 ), .Q(three_dec_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \three_dec_max_limit_reg[4]_i_2 (.CI(1'b0), .CO({\three_dec_max_limit_reg[4]_i_2_n_0 ,\three_dec_max_limit_reg[4]_i_2_n_1 ,\three_dec_max_limit_reg[4]_i_2_n_2 ,\three_dec_max_limit_reg[4]_i_2_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\three_dec_max_limit_reg[4]_i_2_n_4 ,\three_dec_max_limit_reg[4]_i_2_n_5 ,\three_dec_max_limit_reg[4]_i_2_n_6 ,\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED [0]}), .S({\three_dec_max_limit[4]_i_3_n_0 ,\three_dec_max_limit[4]_i_4_n_0 ,\three_dec_max_limit[4]_i_5_n_0 ,\three_dec_max_limit[4]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[5]_i_1_n_0 ), .Q(three_dec_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[6]_i_1_n_0 ), .Q(three_dec_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[7]_i_1_n_0 ), .Q(three_dec_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[8]_i_1_n_0 ), .Q(three_dec_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \three_dec_max_limit_reg[8]_i_2 (.CI(\three_dec_max_limit_reg[4]_i_2_n_0 ), .CO({\three_dec_max_limit_reg[8]_i_2_n_0 ,\three_dec_max_limit_reg[8]_i_2_n_1 ,\three_dec_max_limit_reg[8]_i_2_n_2 ,\three_dec_max_limit_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8],1'b0,device_temp_init[6],1'b0}), .O({\three_dec_max_limit_reg[8]_i_2_n_4 ,\three_dec_max_limit_reg[8]_i_2_n_5 ,\three_dec_max_limit_reg[8]_i_2_n_6 ,\three_dec_max_limit_reg[8]_i_2_n_7 }), .S({\three_dec_max_limit[8]_i_3_n_0 ,\three_dec_max_limit[8]_i_4_n_0 ,\three_dec_max_limit[8]_i_5_n_0 ,\three_dec_max_limit[8]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \three_dec_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[9]_i_1_n_0 ), .Q(three_dec_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__7)); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[11]_i_2 (.I0(two_dec_max_limit[11]), .O(\three_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[11]_i_3 (.I0(two_dec_max_limit[10]), .O(\three_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[5]_i_2 (.I0(two_dec_max_limit[5]), .O(\three_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[5]_i_3 (.I0(two_dec_max_limit[4]), .O(\three_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[5]_i_4 (.I0(two_dec_max_limit[3]), .O(\three_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_min_limit[5]_i_5 (.I0(two_dec_max_limit[2]), .O(\three_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_2 (.I0(two_dec_max_limit[9]), .O(\three_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_3 (.I0(two_dec_max_limit[8]), .O(\three_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_4 (.I0(two_dec_max_limit[7]), .O(\three_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_5 (.I0(two_dec_max_limit[6]), .O(\three_dec_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[0] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit[0]), .Q(three_dec_min_limit[0]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[10]), .Q(three_dec_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[11]), .Q(three_dec_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__2)); CARRY4 \three_dec_min_limit_reg[11]_i_1 (.CI(\three_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}), .O({\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\three_dec_min_limit[11]_i_2_n_0 ,\three_dec_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit[1]), .Q(three_dec_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[2]), .Q(three_dec_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[3]), .Q(three_dec_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[4]), .Q(three_dec_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[5]), .Q(three_dec_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__2)); CARRY4 \three_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\three_dec_min_limit_reg[5]_i_1_n_0 ,\three_dec_min_limit_reg[5]_i_1_n_1 ,\three_dec_min_limit_reg[5]_i_1_n_2 ,\three_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({two_dec_max_limit[5:3],1'b0}), .O(three_dec_min_limit_nxt[5:2]), .S({\three_dec_min_limit[5]_i_2_n_0 ,\three_dec_min_limit[5]_i_3_n_0 ,\three_dec_min_limit[5]_i_4_n_0 ,\three_dec_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[6]), .Q(three_dec_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[7]), .Q(three_dec_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[8]), .Q(three_dec_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) \three_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[9]), .Q(three_dec_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__2)); CARRY4 \three_dec_min_limit_reg[9]_i_1 (.CI(\three_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\three_dec_min_limit_reg[9]_i_1_n_0 ,\three_dec_min_limit_reg[9]_i_1_n_1 ,\three_dec_min_limit_reg[9]_i_1_n_2 ,\three_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(two_dec_max_limit[9:6]), .O(three_dec_min_limit_nxt[9:6]), .S({\three_dec_min_limit[9]_i_2_n_0 ,\three_dec_min_limit[9]_i_3_n_0 ,\three_dec_min_limit[9]_i_4_n_0 ,\three_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\three_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\three_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\three_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\three_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\three_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\three_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\three_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\three_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\three_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\three_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\three_inc_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[10]), .Q(three_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[11]), .Q(three_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_max_limit_reg[11]_i_1 (.CI(\three_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\three_inc_max_limit_reg[11]_i_1_n_2 ,\three_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10],1'b0}), .O({\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],three_inc_max_limit_nxt[11:9]}), .S({1'b0,\three_inc_max_limit[11]_i_2_n_0 ,\three_inc_max_limit[11]_i_3_n_0 ,\three_inc_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[1]), .Q(three_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[2]), .Q(three_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[3]), .Q(three_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[4]), .Q(three_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\three_inc_max_limit_reg[4]_i_1_n_0 ,\three_inc_max_limit_reg[4]_i_1_n_1 ,\three_inc_max_limit_reg[4]_i_1_n_2 ,\three_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,device_temp_init[3:2],1'b0}), .O(three_inc_max_limit_nxt[4:1]), .S({\three_inc_max_limit[4]_i_2_n_0 ,\three_inc_max_limit[4]_i_3_n_0 ,\three_inc_max_limit[4]_i_4_n_0 ,\three_inc_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[5]), .Q(three_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[6]), .Q(three_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[7]), .Q(three_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[8]), .Q(three_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_max_limit_reg[8]_i_1 (.CI(\three_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\three_inc_max_limit_reg[8]_i_1_n_0 ,\three_inc_max_limit_reg[8]_i_1_n_1 ,\three_inc_max_limit_reg[8]_i_1_n_2 ,\three_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8:7],1'b0,device_temp_init[5]}), .O(three_inc_max_limit_nxt[8:5]), .S({\three_inc_max_limit[8]_i_2_n_0 ,\three_inc_max_limit[8]_i_3_n_0 ,\three_inc_max_limit[8]_i_4_n_0 ,\three_inc_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \three_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[9]), .Q(three_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__5)); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[11]_i_2 (.I0(four_inc_max_limit[11]), .O(\three_inc_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[11]_i_3 (.I0(four_inc_max_limit[10]), .O(\three_inc_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[5]_i_2 (.I0(four_inc_max_limit[5]), .O(\three_inc_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[5]_i_3 (.I0(four_inc_max_limit[4]), .O(\three_inc_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[5]_i_4 (.I0(four_inc_max_limit[3]), .O(\three_inc_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_min_limit[5]_i_5 (.I0(four_inc_max_limit[2]), .O(\three_inc_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_2 (.I0(four_inc_max_limit[9]), .O(\three_inc_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_3 (.I0(four_inc_max_limit[8]), .O(\three_inc_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_4 (.I0(four_inc_max_limit[7]), .O(\three_inc_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_5 (.I0(four_inc_max_limit[6]), .O(\three_inc_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[10]), .Q(three_inc_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[11]), .Q(three_inc_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_min_limit_reg[11]_i_1 (.CI(\three_inc_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_inc_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}), .O({\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\three_inc_min_limit[11]_i_2_n_0 ,\three_inc_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit[1]), .Q(three_inc_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[2]), .Q(three_inc_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[3]), .Q(three_inc_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[4]), .Q(three_inc_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[5]), .Q(three_inc_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\three_inc_min_limit_reg[5]_i_1_n_0 ,\three_inc_min_limit_reg[5]_i_1_n_1 ,\three_inc_min_limit_reg[5]_i_1_n_2 ,\three_inc_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({four_inc_max_limit[5:3],1'b0}), .O(three_inc_min_limit_nxt[5:2]), .S({\three_inc_min_limit[5]_i_2_n_0 ,\three_inc_min_limit[5]_i_3_n_0 ,\three_inc_min_limit[5]_i_4_n_0 ,\three_inc_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[6]), .Q(three_inc_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[7]), .Q(three_inc_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[8]), .Q(three_inc_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) \three_inc_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[9]), .Q(three_inc_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_min_limit_reg[9]_i_1 (.CI(\three_inc_min_limit_reg[5]_i_1_n_0 ), .CO({\three_inc_min_limit_reg[9]_i_1_n_0 ,\three_inc_min_limit_reg[9]_i_1_n_1 ,\three_inc_min_limit_reg[9]_i_1_n_2 ,\three_inc_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(four_inc_max_limit[9:6]), .O(three_inc_min_limit_nxt[9:6]), .S({\three_inc_min_limit[9]_i_2_n_0 ,\three_inc_min_limit[9]_i_3_n_0 ,\three_inc_min_limit[9]_i_4_n_0 ,\three_inc_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[0]_i_1 (.I0(device_temp_init[0]), .O(\two_dec_max_limit[0]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\two_dec_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\two_dec_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\two_dec_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\two_dec_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\two_dec_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\two_dec_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\two_dec_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\two_dec_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\two_dec_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\two_dec_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\two_dec_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[0] (.C(CLK), .CE(1'b1), .D(\two_dec_max_limit[0]_i_1_n_0 ), .Q(two_dec_max_limit[0]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[10]), .Q(two_dec_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[11]), .Q(two_dec_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \two_dec_max_limit_reg[11]_i_1 (.CI(\two_dec_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_dec_max_limit_reg[11]_i_1_n_2 ,\two_dec_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,device_temp_init[9]}), .O({\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_dec_max_limit_nxt[11:9]}), .S({1'b0,\two_dec_max_limit[11]_i_2_n_0 ,\two_dec_max_limit[11]_i_3_n_0 ,\two_dec_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[1]), .Q(two_dec_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \two_dec_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],two_dec_max_limit_nxt[1]}), .S({\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\four_inc_max_limit[1]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[2]), .Q(two_dec_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[3]), .Q(two_dec_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[4]), .Q(two_dec_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \two_dec_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\two_dec_max_limit_reg[4]_i_1_n_0 ,\two_dec_max_limit_reg[4]_i_1_n_1 ,\two_dec_max_limit_reg[4]_i_1_n_2 ,\two_dec_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({device_temp_init[4],1'b0,1'b0,device_temp_init[1]}), .O({two_dec_max_limit_nxt[4:2],\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\two_dec_max_limit[4]_i_2_n_0 ,\two_dec_max_limit[4]_i_3_n_0 ,\two_dec_max_limit[4]_i_4_n_0 ,\two_dec_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[5]), .Q(two_dec_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[6]), .Q(two_dec_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[7]), .Q(two_dec_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[8]), .Q(two_dec_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \two_dec_max_limit_reg[8]_i_1 (.CI(\two_dec_max_limit_reg[4]_i_1_n_0 ), .CO({\two_dec_max_limit_reg[8]_i_1_n_0 ,\two_dec_max_limit_reg[8]_i_1_n_1 ,\two_dec_max_limit_reg[8]_i_1_n_2 ,\two_dec_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[6],1'b0}), .O(two_dec_max_limit_nxt[8:5]), .S({\two_dec_max_limit[8]_i_2_n_0 ,\two_dec_max_limit[8]_i_3_n_0 ,\two_dec_max_limit[8]_i_4_n_0 ,\two_dec_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \two_dec_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[9]), .Q(two_dec_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[11]_i_2 (.I0(one_dec_max_limit[11]), .O(\two_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[11]_i_3 (.I0(one_dec_max_limit[10]), .O(\two_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[5]_i_2 (.I0(one_dec_max_limit[5]), .O(\two_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[5]_i_3 (.I0(one_dec_max_limit[4]), .O(\two_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[5]_i_4 (.I0(one_dec_max_limit[3]), .O(\two_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_min_limit[5]_i_5 (.I0(one_dec_max_limit[2]), .O(\two_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_2 (.I0(one_dec_max_limit[9]), .O(\two_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_3 (.I0(one_dec_max_limit[8]), .O(\two_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_4 (.I0(one_dec_max_limit[7]), .O(\two_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_5 (.I0(one_dec_max_limit[6]), .O(\two_dec_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[10]), .Q(two_dec_min_limit[10]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[11]), .Q(two_dec_min_limit[11]), .R(SS)); CARRY4 \two_dec_min_limit_reg[11]_i_1 (.CI(\two_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}), .O({\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\two_dec_min_limit[11]_i_2_n_0 ,\two_dec_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit[1]), .Q(two_dec_min_limit[1]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[2]), .Q(two_dec_min_limit[2]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[3]), .Q(two_dec_min_limit[3]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[4]), .Q(two_dec_min_limit[4]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[5]), .Q(two_dec_min_limit[5]), .R(SS)); CARRY4 \two_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\two_dec_min_limit_reg[5]_i_1_n_0 ,\two_dec_min_limit_reg[5]_i_1_n_1 ,\two_dec_min_limit_reg[5]_i_1_n_2 ,\two_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({one_dec_max_limit[5:3],1'b0}), .O(two_dec_min_limit_nxt[5:2]), .S({\two_dec_min_limit[5]_i_2_n_0 ,\two_dec_min_limit[5]_i_3_n_0 ,\two_dec_min_limit[5]_i_4_n_0 ,\two_dec_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[6]), .Q(two_dec_min_limit[6]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[7]), .Q(two_dec_min_limit[7]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[8]), .Q(two_dec_min_limit[8]), .R(SS)); FDRE #( .INIT(1'b0)) \two_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[9]), .Q(two_dec_min_limit[9]), .R(SS)); CARRY4 \two_dec_min_limit_reg[9]_i_1 (.CI(\two_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\two_dec_min_limit_reg[9]_i_1_n_0 ,\two_dec_min_limit_reg[9]_i_1_n_1 ,\two_dec_min_limit_reg[9]_i_1_n_2 ,\two_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(one_dec_max_limit[9:6]), .O(two_dec_min_limit_nxt[9:6]), .S({\two_dec_min_limit[9]_i_2_n_0 ,\two_dec_min_limit[9]_i_3_n_0 ,\two_dec_min_limit[9]_i_4_n_0 ,\two_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\two_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\two_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\two_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\two_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\two_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\two_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\two_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\two_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\two_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\two_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\two_inc_max_limit[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[10]), .Q(two_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[11]), .Q(two_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_max_limit_reg[11]_i_1 (.CI(\two_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_inc_max_limit_reg[11]_i_1_n_2 ,\two_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10:9]}), .O({\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_inc_max_limit_nxt[11:9]}), .S({1'b0,\two_inc_max_limit[11]_i_2_n_0 ,\two_inc_max_limit[11]_i_3_n_0 ,\two_inc_max_limit[11]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[1]), .Q(two_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[2]), .Q(two_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[3]), .Q(two_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[4]), .Q(two_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\two_inc_max_limit_reg[4]_i_1_n_0 ,\two_inc_max_limit_reg[4]_i_1_n_1 ,\two_inc_max_limit_reg[4]_i_1_n_2 ,\two_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({device_temp_init[4:3],1'b0,device_temp_init[1]}), .O({two_inc_max_limit_nxt[4:2],\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\two_inc_max_limit[4]_i_2_n_0 ,\two_inc_max_limit[4]_i_3_n_0 ,\two_inc_max_limit[4]_i_4_n_0 ,\two_inc_max_limit[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[5]), .Q(two_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[6]), .Q(two_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[7]), .Q(two_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[8]), .Q(two_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_max_limit_reg[8]_i_1 (.CI(\two_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\two_inc_max_limit_reg[8]_i_1_n_0 ,\two_inc_max_limit_reg[8]_i_1_n_1 ,\two_inc_max_limit_reg[8]_i_1_n_2 ,\two_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,device_temp_init[7],1'b0,1'b0}), .O(two_inc_max_limit_nxt[8:5]), .S({\two_inc_max_limit[8]_i_2_n_0 ,\two_inc_max_limit[8]_i_3_n_0 ,\two_inc_max_limit[8]_i_4_n_0 ,\two_inc_max_limit[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \two_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[9]), .Q(two_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__4)); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[11]_i_2 (.I0(three_inc_max_limit[11]), .O(\two_inc_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[11]_i_3 (.I0(three_inc_max_limit[10]), .O(\two_inc_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[5]_i_2 (.I0(three_inc_max_limit[5]), .O(\two_inc_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[5]_i_3 (.I0(three_inc_max_limit[4]), .O(\two_inc_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[5]_i_4 (.I0(three_inc_max_limit[3]), .O(\two_inc_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_min_limit[5]_i_5 (.I0(three_inc_max_limit[2]), .O(\two_inc_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_2 (.I0(three_inc_max_limit[9]), .O(\two_inc_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_3 (.I0(three_inc_max_limit[8]), .O(\two_inc_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_4 (.I0(three_inc_max_limit[7]), .O(\two_inc_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_5 (.I0(three_inc_max_limit[6]), .O(\two_inc_min_limit[9]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[10]), .Q(two_inc_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[11]), .Q(two_inc_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_min_limit_reg[11]_i_1 (.CI(\two_inc_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_inc_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}), .O({\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\two_inc_min_limit[11]_i_2_n_0 ,\two_inc_min_limit[11]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit[1]), .Q(two_inc_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[2]), .Q(two_inc_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[3]), .Q(two_inc_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[4]), .Q(two_inc_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[5]), .Q(two_inc_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\two_inc_min_limit_reg[5]_i_1_n_0 ,\two_inc_min_limit_reg[5]_i_1_n_1 ,\two_inc_min_limit_reg[5]_i_1_n_2 ,\two_inc_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({three_inc_max_limit[5:3],1'b0}), .O(two_inc_min_limit_nxt[5:2]), .S({\two_inc_min_limit[5]_i_2_n_0 ,\two_inc_min_limit[5]_i_3_n_0 ,\two_inc_min_limit[5]_i_4_n_0 ,\two_inc_min_limit[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[6]), .Q(two_inc_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[7]), .Q(two_inc_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[8]), .Q(two_inc_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \two_inc_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[9]), .Q(two_inc_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_min_limit_reg[9]_i_1 (.CI(\two_inc_min_limit_reg[5]_i_1_n_0 ), .CO({\two_inc_min_limit_reg[9]_i_1_n_0 ,\two_inc_min_limit_reg[9]_i_1_n_1 ,\two_inc_min_limit_reg[9]_i_1_n_2 ,\two_inc_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(three_inc_max_limit[9:6]), .O(two_inc_min_limit_nxt[9:6]), .S({\two_inc_min_limit[9]_i_2_n_0 ,\two_inc_min_limit[9]_i_3_n_0 ,\two_inc_min_limit[9]_i_4_n_0 ,\two_inc_min_limit[9]_i_5_n_0 })); LUT3 #( .INIT(8'h40)) update_temp_101 (.I0(tempmon_sample_en_102), .I1(tempmon_init_complete), .I2(tempmon_sample_en_101), .O(update_temp_101__0)); FDRE #( .INIT(1'b0)) update_temp_102_reg (.C(CLK), .CE(1'b1), .D(update_temp_101__0), .Q(update_temp_102), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_top" *) module ddr3_ifmig_7series_v4_0_ddr_phy_top (ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , phy_dout, \samps_r_reg[9] , app_zq_r_reg, \periodic_rd_generation.periodic_rd_timer_r_reg[1] , init_calib_complete_r_reg, \calib_seq_reg[0] , \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_en_stg2_f_timing_reg, dqs_po_en_stg2_f_reg, \rd_ptr_timing_reg[0] , \resume_wait_r_reg[5] , phy_mc_ctl_full, stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , rst_sync_r1_reg, \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , D, \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[228] , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , maint_prescaler_r1, \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[5] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \read_fifo.tail_r_reg[0] , \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , \not_strict_mode.app_rd_data_reg[255]_0 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[0]_0 , wr_en, wr_en_5, wr_en_6, of_ctl_full_v, ddr_ck_out, \qcntr_r_reg[0] , ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, idle, mmcm_ps_clk, rst_sync_r1, CLK, rstdiv0_sync_r1_reg_rep__20, poc_sample_pd, freq_refclk, mem_refclk, sync_pulse, pll_locked, in0, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__12, SR, rstdiv0_sync_r1_reg_rep__23, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, rstdiv0_sync_r1_reg_rep__22, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__17, rstdiv0_sync_r1_reg_rep__16, SS, tempmon_sample_en, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__6, \cmd_pipe_plus.mc_address_reg[43] , Q, mem_out, \rd_ptr_reg[3] , rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__25_0, rstdiv0_sync_r1_reg_rep__24, \sm_r_reg[0]_0 , \rd_ptr_reg[3]_0 , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, mc_cas_n, mc_ras_n, mc_odt, mc_cke, mc_we_n, mc_address, mc_bank, mc_cs_n, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, rstdiv0_sync_r1_reg_rep__25_1, rstdiv0_sync_r1_reg_rep__25_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , tail_r, \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , psdone, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__19, fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__23_0, p_81_in, rstdiv0_sync_r1_reg_rep__23_1, po_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__7, mc_wrdata_en, \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 , mc_cmd, \cmd_pipe_plus.mc_data_offset_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_reg[5]_0 , \stg3_r_reg[0] , rstdiv0_sync_r1_reg_rep__8); output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [3:0]phy_dout; output \samps_r_reg[9] ; output app_zq_r_reg; output \periodic_rd_generation.periodic_rd_timer_r_reg[1] ; output init_calib_complete_r_reg; output \calib_seq_reg[0] ; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_en_stg2_f_timing_reg; output dqs_po_en_stg2_f_reg; output [33:0]\rd_ptr_timing_reg[0] ; output \resume_wait_r_reg[5] ; output phy_mc_ctl_full; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output rst_sync_r1_reg; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]D; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[228] ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output maint_prescaler_r1; output \cmd_pipe_plus.mc_data_offset_reg[4] ; output [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; output \cmd_pipe_plus.mc_data_offset_reg[1] ; output \cmd_pipe_plus.mc_data_offset_1_reg[4] ; output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; output \cmd_pipe_plus.mc_data_offset_1_reg[1] ; output \read_fifo.tail_r_reg[0] ; output \cmd_pipe_plus.mc_data_offset_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output [1:0]\rd_ptr_timing_reg[0]_0 ; output wr_en; output wr_en_5; output wr_en_6; output [0:0]of_ctl_full_v; output [1:0]ddr_ck_out; output [0:0]\qcntr_r_reg[0] ; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input idle; input mmcm_ps_clk; input rst_sync_r1; input CLK; input rstdiv0_sync_r1_reg_rep__20; input poc_sample_pd; input freq_refclk; input mem_refclk; input sync_pulse; input pll_locked; input in0; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__10; input [0:0]rstdiv0_sync_r1_reg_rep__12; input [0:0]SR; input rstdiv0_sync_r1_reg_rep__23; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input rstdiv0_sync_r1_reg_rep__22; input rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [1:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input tempmon_sample_en; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__6; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input [287:0]Q; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input rstdiv0_sync_r1_reg_rep__25; input rstdiv0_sync_r1_reg_rep__25_0; input rstdiv0_sync_r1_reg_rep__24; input [0:0]\sm_r_reg[0]_0 ; input [29:0]\rd_ptr_reg[3]_0 ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input [2:0]mc_cas_n; input [2:0]mc_ras_n; input [0:0]mc_odt; input [0:0]mc_cke; input [2:0]mc_we_n; input [37:0]mc_address; input [8:0]mc_bank; input [0:0]mc_cs_n; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input rstdiv0_sync_r1_reg_rep__25_1; input rstdiv0_sync_r1_reg_rep__25_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input [0:0]tail_r; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input psdone; input rstdiv0_sync_r1_reg_rep__0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__23_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__23_1; input [0:0]po_cnt_dec_reg; input [0:0]rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input [0:0]rstdiv0_sync_r1_reg_rep__7; input mc_wrdata_en; input \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[2] ; input \cmd_pipe_plus.mc_data_offset_1_reg[3] ; input \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; input [1:0]mc_cmd; input \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[2] ; input \cmd_pipe_plus.mc_data_offset_reg[3] ; input \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; input \stg3_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__8; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [287:0]Q; wire RST0; wire [0:0]SR; wire [0:0]SS; wire app_zq_r_reg; wire [1:0]byte_sel_cnt; wire [1:0]calib_sel; wire [3:3]calib_sel__0; wire [1:0]calib_seq; wire \calib_seq_reg[0] ; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; wire cnt_pwron_reset_done_r0; wire \complex_row_cnt_ocal_reg[0] ; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire [1:0]\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ; wire [11:0]\device_temp_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire dqs_po_en_stg2_f_reg; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire fine_adjust_reg; wire [26:2]fine_delay_mod; wire fine_delay_sel_r; wire freq_refclk; wire idelay_inc; wire idle; wire in0; wire init_calib_complete_r_reg; wire maint_prescaler_r1; wire [37:0]mc_address; wire [8:0]mc_bank; wire [2:0]mc_cas_n; wire [0:0]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_we_n; wire mc_wrdata_en; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [57:5]mux_address; wire mux_cmd_wren; wire [5:0]mux_data_offset_1; wire mux_reset_n; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [55:0]\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns ; wire [7:0]\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire [22:0]p_1_out; wire p_81_in; wire pd_out; wire \periodic_rd_generation.periodic_rd_timer_r_reg[1] ; wire [3:0]phy_dout; wire phy_if_reset; wire phy_mc_ctl_full; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [0:0]pi_cnt_dec_reg; wire pi_en_stg2_f_timing_reg; wire \pi_rst_stg1_cal_r_reg[0] ; wire pll_locked; wire [0:0]po_cnt_dec_reg; wire [1:0]po_stg2_wrcal_cnt; wire poc_sample_pd; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire ram_init_done_r; wire rd_buf_we; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [33:0]\rd_ptr_timing_reg[0] ; wire [1:0]\rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire \resume_wait_r_reg[5] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [1:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__23_0; wire rstdiv0_sync_r1_reg_rep__23_1; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__25_1; wire rstdiv0_sync_r1_reg_rep__25_2; wire [0:0]rstdiv0_sync_r1_reg_rep__4; wire rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire [0:0]rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire \samps_r_reg[9] ; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire tempmon_sample_en; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_37; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_38; wire u_ddr_calib_top_n_385; wire u_ddr_calib_top_n_386; wire u_ddr_calib_top_n_387; wire u_ddr_calib_top_n_388; wire u_ddr_calib_top_n_389; wire u_ddr_calib_top_n_390; wire u_ddr_calib_top_n_391; wire u_ddr_calib_top_n_392; wire u_ddr_calib_top_n_393; wire u_ddr_calib_top_n_394; wire u_ddr_calib_top_n_395; wire u_ddr_calib_top_n_396; wire u_ddr_calib_top_n_397; wire u_ddr_calib_top_n_399; wire u_ddr_calib_top_n_400; wire u_ddr_calib_top_n_401; wire u_ddr_calib_top_n_402; wire u_ddr_calib_top_n_403; wire u_ddr_calib_top_n_404; wire u_ddr_calib_top_n_405; wire u_ddr_calib_top_n_406; wire u_ddr_calib_top_n_407; wire u_ddr_calib_top_n_408; wire u_ddr_calib_top_n_409; wire u_ddr_calib_top_n_410; wire u_ddr_calib_top_n_411; wire u_ddr_calib_top_n_412; wire u_ddr_calib_top_n_413; wire u_ddr_calib_top_n_414; wire u_ddr_calib_top_n_415; wire u_ddr_calib_top_n_416; wire u_ddr_calib_top_n_417; wire u_ddr_calib_top_n_418; wire u_ddr_calib_top_n_419; wire u_ddr_calib_top_n_420; wire u_ddr_calib_top_n_421; wire u_ddr_calib_top_n_422; wire u_ddr_calib_top_n_423; wire u_ddr_calib_top_n_424; wire u_ddr_calib_top_n_425; wire u_ddr_calib_top_n_426; wire u_ddr_calib_top_n_427; wire u_ddr_calib_top_n_428; wire u_ddr_calib_top_n_429; wire u_ddr_calib_top_n_430; wire u_ddr_calib_top_n_431; wire u_ddr_calib_top_n_432; wire u_ddr_calib_top_n_433; wire u_ddr_calib_top_n_434; wire u_ddr_calib_top_n_435; wire u_ddr_calib_top_n_436; wire u_ddr_calib_top_n_437; wire u_ddr_calib_top_n_438; wire u_ddr_calib_top_n_439; wire u_ddr_calib_top_n_441; wire u_ddr_calib_top_n_442; wire u_ddr_calib_top_n_443; wire u_ddr_calib_top_n_444; wire u_ddr_calib_top_n_445; wire u_ddr_calib_top_n_446; wire u_ddr_calib_top_n_447; wire u_ddr_calib_top_n_448; wire u_ddr_calib_top_n_449; wire u_ddr_calib_top_n_45; wire u_ddr_calib_top_n_450; wire u_ddr_calib_top_n_451; wire u_ddr_calib_top_n_452; wire u_ddr_calib_top_n_453; wire u_ddr_calib_top_n_454; wire u_ddr_calib_top_n_455; wire u_ddr_calib_top_n_456; wire u_ddr_calib_top_n_457; wire u_ddr_calib_top_n_458; wire u_ddr_calib_top_n_461; wire u_ddr_calib_top_n_464; wire u_ddr_calib_top_n_47; wire u_ddr_calib_top_n_50; wire u_ddr_calib_top_n_809; wire u_ddr_calib_top_n_810; wire u_ddr_calib_top_n_833; wire u_ddr_calib_top_n_834; wire u_ddr_calib_top_n_840; wire u_ddr_calib_top_n_841; wire u_ddr_calib_top_n_855; wire u_ddr_calib_top_n_856; wire u_ddr_calib_top_n_857; wire u_ddr_calib_top_n_858; wire u_ddr_calib_top_n_859; wire u_ddr_calib_top_n_860; wire u_ddr_calib_top_n_861; wire u_ddr_calib_top_n_875; wire u_ddr_calib_top_n_876; wire u_ddr_calib_top_n_877; wire u_ddr_calib_top_n_878; wire u_ddr_calib_top_n_879; wire u_ddr_calib_top_n_880; wire u_ddr_calib_top_n_881; wire u_ddr_calib_top_n_882; wire [2:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay ; wire [26:5]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay ; wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ; wire [26:5]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay ; wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ; wire [26:5]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay ; wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [0:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ; wire [0:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ; wire [7:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ; wire [7:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ; wire [67:8]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ; wire [5:0]\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ; wire [8:0]\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ; wire [8:0]\u_ddr_mc_phy/po_counter_read_val_w[1]_2 ; wire u_ddr_mc_phy_wrapper_n_1000; wire u_ddr_mc_phy_wrapper_n_1001; wire u_ddr_mc_phy_wrapper_n_1002; wire u_ddr_mc_phy_wrapper_n_1003; wire u_ddr_mc_phy_wrapper_n_1004; wire u_ddr_mc_phy_wrapper_n_1005; wire u_ddr_mc_phy_wrapper_n_1006; wire u_ddr_mc_phy_wrapper_n_1007; wire u_ddr_mc_phy_wrapper_n_1008; wire u_ddr_mc_phy_wrapper_n_1009; wire u_ddr_mc_phy_wrapper_n_1010; wire u_ddr_mc_phy_wrapper_n_1011; wire u_ddr_mc_phy_wrapper_n_1012; wire u_ddr_mc_phy_wrapper_n_1013; wire u_ddr_mc_phy_wrapper_n_1014; wire u_ddr_mc_phy_wrapper_n_1015; wire u_ddr_mc_phy_wrapper_n_1016; wire u_ddr_mc_phy_wrapper_n_1017; wire u_ddr_mc_phy_wrapper_n_1018; wire u_ddr_mc_phy_wrapper_n_1019; wire u_ddr_mc_phy_wrapper_n_102; wire u_ddr_mc_phy_wrapper_n_1020; wire u_ddr_mc_phy_wrapper_n_1021; wire u_ddr_mc_phy_wrapper_n_1022; wire u_ddr_mc_phy_wrapper_n_1023; wire u_ddr_mc_phy_wrapper_n_1024; wire u_ddr_mc_phy_wrapper_n_1025; wire u_ddr_mc_phy_wrapper_n_1026; wire u_ddr_mc_phy_wrapper_n_1027; wire u_ddr_mc_phy_wrapper_n_1028; wire u_ddr_mc_phy_wrapper_n_1029; wire u_ddr_mc_phy_wrapper_n_1030; wire u_ddr_mc_phy_wrapper_n_1033; wire u_ddr_mc_phy_wrapper_n_1034; wire u_ddr_mc_phy_wrapper_n_1035; wire u_ddr_mc_phy_wrapper_n_1036; wire u_ddr_mc_phy_wrapper_n_1037; wire u_ddr_mc_phy_wrapper_n_1038; wire u_ddr_mc_phy_wrapper_n_1039; wire u_ddr_mc_phy_wrapper_n_104; wire u_ddr_mc_phy_wrapper_n_1040; wire u_ddr_mc_phy_wrapper_n_1041; wire u_ddr_mc_phy_wrapper_n_1042; wire u_ddr_mc_phy_wrapper_n_1043; wire u_ddr_mc_phy_wrapper_n_1044; wire u_ddr_mc_phy_wrapper_n_1045; wire u_ddr_mc_phy_wrapper_n_1046; wire u_ddr_mc_phy_wrapper_n_1047; wire u_ddr_mc_phy_wrapper_n_1048; wire u_ddr_mc_phy_wrapper_n_1049; wire u_ddr_mc_phy_wrapper_n_1050; wire u_ddr_mc_phy_wrapper_n_1051; wire u_ddr_mc_phy_wrapper_n_1052; wire u_ddr_mc_phy_wrapper_n_1053; wire u_ddr_mc_phy_wrapper_n_1054; wire u_ddr_mc_phy_wrapper_n_1055; wire u_ddr_mc_phy_wrapper_n_1056; wire u_ddr_mc_phy_wrapper_n_1057; wire u_ddr_mc_phy_wrapper_n_1058; wire u_ddr_mc_phy_wrapper_n_1059; wire u_ddr_mc_phy_wrapper_n_106; wire u_ddr_mc_phy_wrapper_n_1060; wire u_ddr_mc_phy_wrapper_n_1061; wire u_ddr_mc_phy_wrapper_n_1062; wire u_ddr_mc_phy_wrapper_n_1063; wire u_ddr_mc_phy_wrapper_n_1064; wire u_ddr_mc_phy_wrapper_n_1065; wire u_ddr_mc_phy_wrapper_n_1066; wire u_ddr_mc_phy_wrapper_n_1067; wire u_ddr_mc_phy_wrapper_n_1068; wire u_ddr_mc_phy_wrapper_n_1069; wire u_ddr_mc_phy_wrapper_n_107; wire u_ddr_mc_phy_wrapper_n_1070; wire u_ddr_mc_phy_wrapper_n_1071; wire u_ddr_mc_phy_wrapper_n_1072; wire u_ddr_mc_phy_wrapper_n_1073; wire u_ddr_mc_phy_wrapper_n_1074; wire u_ddr_mc_phy_wrapper_n_1075; wire u_ddr_mc_phy_wrapper_n_1076; wire u_ddr_mc_phy_wrapper_n_1077; wire u_ddr_mc_phy_wrapper_n_1078; wire u_ddr_mc_phy_wrapper_n_1079; wire u_ddr_mc_phy_wrapper_n_108; wire u_ddr_mc_phy_wrapper_n_1080; wire u_ddr_mc_phy_wrapper_n_1081; wire u_ddr_mc_phy_wrapper_n_1082; wire u_ddr_mc_phy_wrapper_n_1083; wire u_ddr_mc_phy_wrapper_n_1084; wire u_ddr_mc_phy_wrapper_n_1085; wire u_ddr_mc_phy_wrapper_n_1086; wire u_ddr_mc_phy_wrapper_n_1087; wire u_ddr_mc_phy_wrapper_n_1088; wire u_ddr_mc_phy_wrapper_n_1089; wire u_ddr_mc_phy_wrapper_n_109; wire u_ddr_mc_phy_wrapper_n_1090; wire u_ddr_mc_phy_wrapper_n_1091; wire u_ddr_mc_phy_wrapper_n_1092; wire u_ddr_mc_phy_wrapper_n_1093; wire u_ddr_mc_phy_wrapper_n_1094; wire u_ddr_mc_phy_wrapper_n_1095; wire u_ddr_mc_phy_wrapper_n_1096; wire u_ddr_mc_phy_wrapper_n_110; wire u_ddr_mc_phy_wrapper_n_111; wire u_ddr_mc_phy_wrapper_n_112; wire u_ddr_mc_phy_wrapper_n_1127; wire u_ddr_mc_phy_wrapper_n_1129; wire u_ddr_mc_phy_wrapper_n_1130; wire u_ddr_mc_phy_wrapper_n_1131; wire u_ddr_mc_phy_wrapper_n_1132; wire u_ddr_mc_phy_wrapper_n_1133; wire u_ddr_mc_phy_wrapper_n_1134; wire u_ddr_mc_phy_wrapper_n_1135; wire u_ddr_mc_phy_wrapper_n_1136; wire u_ddr_mc_phy_wrapper_n_1137; wire u_ddr_mc_phy_wrapper_n_1138; wire u_ddr_mc_phy_wrapper_n_1139; wire u_ddr_mc_phy_wrapper_n_1140; wire u_ddr_mc_phy_wrapper_n_1141; wire u_ddr_mc_phy_wrapper_n_1142; wire u_ddr_mc_phy_wrapper_n_1143; wire u_ddr_mc_phy_wrapper_n_1144; wire u_ddr_mc_phy_wrapper_n_1145; wire u_ddr_mc_phy_wrapper_n_1146; wire u_ddr_mc_phy_wrapper_n_1147; wire u_ddr_mc_phy_wrapper_n_1148; wire u_ddr_mc_phy_wrapper_n_1149; wire u_ddr_mc_phy_wrapper_n_1150; wire u_ddr_mc_phy_wrapper_n_1151; wire u_ddr_mc_phy_wrapper_n_1152; wire u_ddr_mc_phy_wrapper_n_1153; wire u_ddr_mc_phy_wrapper_n_1154; wire u_ddr_mc_phy_wrapper_n_1155; wire u_ddr_mc_phy_wrapper_n_1156; wire u_ddr_mc_phy_wrapper_n_1157; wire u_ddr_mc_phy_wrapper_n_1158; wire u_ddr_mc_phy_wrapper_n_1159; wire u_ddr_mc_phy_wrapper_n_1160; wire u_ddr_mc_phy_wrapper_n_1161; wire u_ddr_mc_phy_wrapper_n_1162; wire u_ddr_mc_phy_wrapper_n_1163; wire u_ddr_mc_phy_wrapper_n_1164; wire u_ddr_mc_phy_wrapper_n_1165; wire u_ddr_mc_phy_wrapper_n_1166; wire u_ddr_mc_phy_wrapper_n_1167; wire u_ddr_mc_phy_wrapper_n_1168; wire u_ddr_mc_phy_wrapper_n_1169; wire u_ddr_mc_phy_wrapper_n_1170; wire u_ddr_mc_phy_wrapper_n_1171; wire u_ddr_mc_phy_wrapper_n_1172; wire u_ddr_mc_phy_wrapper_n_1173; wire u_ddr_mc_phy_wrapper_n_1174; wire u_ddr_mc_phy_wrapper_n_1175; wire u_ddr_mc_phy_wrapper_n_1176; wire u_ddr_mc_phy_wrapper_n_1177; wire u_ddr_mc_phy_wrapper_n_1178; wire u_ddr_mc_phy_wrapper_n_1179; wire u_ddr_mc_phy_wrapper_n_1180; wire u_ddr_mc_phy_wrapper_n_1181; wire u_ddr_mc_phy_wrapper_n_1182; wire u_ddr_mc_phy_wrapper_n_1183; wire u_ddr_mc_phy_wrapper_n_1184; wire u_ddr_mc_phy_wrapper_n_1185; wire u_ddr_mc_phy_wrapper_n_1186; wire u_ddr_mc_phy_wrapper_n_1187; wire u_ddr_mc_phy_wrapper_n_1188; wire u_ddr_mc_phy_wrapper_n_1189; wire u_ddr_mc_phy_wrapper_n_1190; wire u_ddr_mc_phy_wrapper_n_1191; wire u_ddr_mc_phy_wrapper_n_30; wire u_ddr_mc_phy_wrapper_n_43; wire u_ddr_mc_phy_wrapper_n_434; wire u_ddr_mc_phy_wrapper_n_435; wire u_ddr_mc_phy_wrapper_n_436; wire u_ddr_mc_phy_wrapper_n_437; wire u_ddr_mc_phy_wrapper_n_438; wire u_ddr_mc_phy_wrapper_n_439; wire u_ddr_mc_phy_wrapper_n_44; wire u_ddr_mc_phy_wrapper_n_440; wire u_ddr_mc_phy_wrapper_n_441; wire u_ddr_mc_phy_wrapper_n_442; wire u_ddr_mc_phy_wrapper_n_443; wire u_ddr_mc_phy_wrapper_n_444; wire u_ddr_mc_phy_wrapper_n_445; wire u_ddr_mc_phy_wrapper_n_446; wire u_ddr_mc_phy_wrapper_n_447; wire u_ddr_mc_phy_wrapper_n_448; wire u_ddr_mc_phy_wrapper_n_449; wire u_ddr_mc_phy_wrapper_n_45; wire u_ddr_mc_phy_wrapper_n_450; wire u_ddr_mc_phy_wrapper_n_451; wire u_ddr_mc_phy_wrapper_n_452; wire u_ddr_mc_phy_wrapper_n_453; wire u_ddr_mc_phy_wrapper_n_454; wire u_ddr_mc_phy_wrapper_n_455; wire u_ddr_mc_phy_wrapper_n_456; wire u_ddr_mc_phy_wrapper_n_457; wire u_ddr_mc_phy_wrapper_n_458; wire u_ddr_mc_phy_wrapper_n_459; wire u_ddr_mc_phy_wrapper_n_46; wire u_ddr_mc_phy_wrapper_n_460; wire u_ddr_mc_phy_wrapper_n_461; wire u_ddr_mc_phy_wrapper_n_462; wire u_ddr_mc_phy_wrapper_n_463; wire u_ddr_mc_phy_wrapper_n_464; wire u_ddr_mc_phy_wrapper_n_465; wire u_ddr_mc_phy_wrapper_n_466; wire u_ddr_mc_phy_wrapper_n_467; wire u_ddr_mc_phy_wrapper_n_468; wire u_ddr_mc_phy_wrapper_n_469; wire u_ddr_mc_phy_wrapper_n_470; wire u_ddr_mc_phy_wrapper_n_471; wire u_ddr_mc_phy_wrapper_n_472; wire u_ddr_mc_phy_wrapper_n_473; wire u_ddr_mc_phy_wrapper_n_474; wire u_ddr_mc_phy_wrapper_n_475; wire u_ddr_mc_phy_wrapper_n_476; wire u_ddr_mc_phy_wrapper_n_477; wire u_ddr_mc_phy_wrapper_n_478; wire u_ddr_mc_phy_wrapper_n_479; wire u_ddr_mc_phy_wrapper_n_480; wire u_ddr_mc_phy_wrapper_n_481; wire u_ddr_mc_phy_wrapper_n_482; wire u_ddr_mc_phy_wrapper_n_483; wire u_ddr_mc_phy_wrapper_n_484; wire u_ddr_mc_phy_wrapper_n_485; wire u_ddr_mc_phy_wrapper_n_486; wire u_ddr_mc_phy_wrapper_n_487; wire u_ddr_mc_phy_wrapper_n_488; wire u_ddr_mc_phy_wrapper_n_489; wire u_ddr_mc_phy_wrapper_n_490; wire u_ddr_mc_phy_wrapper_n_491; wire u_ddr_mc_phy_wrapper_n_492; wire u_ddr_mc_phy_wrapper_n_493; wire u_ddr_mc_phy_wrapper_n_494; wire u_ddr_mc_phy_wrapper_n_495; wire u_ddr_mc_phy_wrapper_n_496; wire u_ddr_mc_phy_wrapper_n_497; wire u_ddr_mc_phy_wrapper_n_60; wire u_ddr_mc_phy_wrapper_n_61; wire u_ddr_mc_phy_wrapper_n_63; wire u_ddr_mc_phy_wrapper_n_64; wire u_ddr_mc_phy_wrapper_n_65; wire u_ddr_mc_phy_wrapper_n_66; wire u_ddr_mc_phy_wrapper_n_67; wire u_ddr_mc_phy_wrapper_n_756; wire u_ddr_mc_phy_wrapper_n_757; wire u_ddr_mc_phy_wrapper_n_758; wire u_ddr_mc_phy_wrapper_n_759; wire u_ddr_mc_phy_wrapper_n_760; wire u_ddr_mc_phy_wrapper_n_761; wire u_ddr_mc_phy_wrapper_n_762; wire u_ddr_mc_phy_wrapper_n_763; wire u_ddr_mc_phy_wrapper_n_764; wire u_ddr_mc_phy_wrapper_n_765; wire u_ddr_mc_phy_wrapper_n_766; wire u_ddr_mc_phy_wrapper_n_767; wire u_ddr_mc_phy_wrapper_n_768; wire u_ddr_mc_phy_wrapper_n_769; wire u_ddr_mc_phy_wrapper_n_770; wire u_ddr_mc_phy_wrapper_n_771; wire u_ddr_mc_phy_wrapper_n_772; wire u_ddr_mc_phy_wrapper_n_773; wire u_ddr_mc_phy_wrapper_n_774; wire u_ddr_mc_phy_wrapper_n_775; wire u_ddr_mc_phy_wrapper_n_776; wire u_ddr_mc_phy_wrapper_n_777; wire u_ddr_mc_phy_wrapper_n_778; wire u_ddr_mc_phy_wrapper_n_779; wire u_ddr_mc_phy_wrapper_n_780; wire u_ddr_mc_phy_wrapper_n_781; wire u_ddr_mc_phy_wrapper_n_782; wire u_ddr_mc_phy_wrapper_n_783; wire u_ddr_mc_phy_wrapper_n_784; wire u_ddr_mc_phy_wrapper_n_785; wire u_ddr_mc_phy_wrapper_n_786; wire u_ddr_mc_phy_wrapper_n_787; wire u_ddr_mc_phy_wrapper_n_788; wire u_ddr_mc_phy_wrapper_n_789; wire u_ddr_mc_phy_wrapper_n_790; wire u_ddr_mc_phy_wrapper_n_791; wire u_ddr_mc_phy_wrapper_n_792; wire u_ddr_mc_phy_wrapper_n_793; wire u_ddr_mc_phy_wrapper_n_794; wire u_ddr_mc_phy_wrapper_n_795; wire u_ddr_mc_phy_wrapper_n_796; wire u_ddr_mc_phy_wrapper_n_797; wire u_ddr_mc_phy_wrapper_n_798; wire u_ddr_mc_phy_wrapper_n_799; wire u_ddr_mc_phy_wrapper_n_800; wire u_ddr_mc_phy_wrapper_n_801; wire u_ddr_mc_phy_wrapper_n_802; wire u_ddr_mc_phy_wrapper_n_803; wire u_ddr_mc_phy_wrapper_n_804; wire u_ddr_mc_phy_wrapper_n_805; wire u_ddr_mc_phy_wrapper_n_806; wire u_ddr_mc_phy_wrapper_n_807; wire u_ddr_mc_phy_wrapper_n_808; wire u_ddr_mc_phy_wrapper_n_809; wire u_ddr_mc_phy_wrapper_n_810; wire u_ddr_mc_phy_wrapper_n_811; wire u_ddr_mc_phy_wrapper_n_812; wire u_ddr_mc_phy_wrapper_n_813; wire u_ddr_mc_phy_wrapper_n_814; wire u_ddr_mc_phy_wrapper_n_815; wire u_ddr_mc_phy_wrapper_n_816; wire u_ddr_mc_phy_wrapper_n_817; wire u_ddr_mc_phy_wrapper_n_818; wire u_ddr_mc_phy_wrapper_n_819; wire u_ddr_mc_phy_wrapper_n_820; wire u_ddr_mc_phy_wrapper_n_835; wire u_ddr_mc_phy_wrapper_n_836; wire u_ddr_mc_phy_wrapper_n_837; wire u_ddr_mc_phy_wrapper_n_838; wire u_ddr_mc_phy_wrapper_n_839; wire u_ddr_mc_phy_wrapper_n_840; wire u_ddr_mc_phy_wrapper_n_841; wire u_ddr_mc_phy_wrapper_n_842; wire u_ddr_mc_phy_wrapper_n_843; wire u_ddr_mc_phy_wrapper_n_844; wire u_ddr_mc_phy_wrapper_n_845; wire u_ddr_mc_phy_wrapper_n_846; wire u_ddr_mc_phy_wrapper_n_847; wire u_ddr_mc_phy_wrapper_n_848; wire u_ddr_mc_phy_wrapper_n_849; wire u_ddr_mc_phy_wrapper_n_850; wire u_ddr_mc_phy_wrapper_n_851; wire u_ddr_mc_phy_wrapper_n_852; wire u_ddr_mc_phy_wrapper_n_853; wire u_ddr_mc_phy_wrapper_n_854; wire u_ddr_mc_phy_wrapper_n_855; wire u_ddr_mc_phy_wrapper_n_856; wire u_ddr_mc_phy_wrapper_n_857; wire u_ddr_mc_phy_wrapper_n_858; wire u_ddr_mc_phy_wrapper_n_859; wire u_ddr_mc_phy_wrapper_n_860; wire u_ddr_mc_phy_wrapper_n_861; wire u_ddr_mc_phy_wrapper_n_862; wire u_ddr_mc_phy_wrapper_n_863; wire u_ddr_mc_phy_wrapper_n_864; wire u_ddr_mc_phy_wrapper_n_865; wire u_ddr_mc_phy_wrapper_n_866; wire u_ddr_mc_phy_wrapper_n_867; wire u_ddr_mc_phy_wrapper_n_868; wire u_ddr_mc_phy_wrapper_n_869; wire u_ddr_mc_phy_wrapper_n_870; wire u_ddr_mc_phy_wrapper_n_871; wire u_ddr_mc_phy_wrapper_n_872; wire u_ddr_mc_phy_wrapper_n_873; wire u_ddr_mc_phy_wrapper_n_874; wire u_ddr_mc_phy_wrapper_n_875; wire u_ddr_mc_phy_wrapper_n_876; wire u_ddr_mc_phy_wrapper_n_877; wire u_ddr_mc_phy_wrapper_n_878; wire u_ddr_mc_phy_wrapper_n_879; wire u_ddr_mc_phy_wrapper_n_880; wire u_ddr_mc_phy_wrapper_n_881; wire u_ddr_mc_phy_wrapper_n_882; wire u_ddr_mc_phy_wrapper_n_883; wire u_ddr_mc_phy_wrapper_n_884; wire u_ddr_mc_phy_wrapper_n_885; wire u_ddr_mc_phy_wrapper_n_886; wire u_ddr_mc_phy_wrapper_n_887; wire u_ddr_mc_phy_wrapper_n_888; wire u_ddr_mc_phy_wrapper_n_889; wire u_ddr_mc_phy_wrapper_n_890; wire u_ddr_mc_phy_wrapper_n_891; wire u_ddr_mc_phy_wrapper_n_892; wire u_ddr_mc_phy_wrapper_n_893; wire u_ddr_mc_phy_wrapper_n_894; wire u_ddr_mc_phy_wrapper_n_895; wire u_ddr_mc_phy_wrapper_n_896; wire u_ddr_mc_phy_wrapper_n_897; wire u_ddr_mc_phy_wrapper_n_898; wire u_ddr_mc_phy_wrapper_n_901; wire u_ddr_mc_phy_wrapper_n_902; wire u_ddr_mc_phy_wrapper_n_903; wire u_ddr_mc_phy_wrapper_n_904; wire u_ddr_mc_phy_wrapper_n_905; wire u_ddr_mc_phy_wrapper_n_906; wire u_ddr_mc_phy_wrapper_n_907; wire u_ddr_mc_phy_wrapper_n_908; wire u_ddr_mc_phy_wrapper_n_909; wire u_ddr_mc_phy_wrapper_n_910; wire u_ddr_mc_phy_wrapper_n_911; wire u_ddr_mc_phy_wrapper_n_912; wire u_ddr_mc_phy_wrapper_n_913; wire u_ddr_mc_phy_wrapper_n_914; wire u_ddr_mc_phy_wrapper_n_915; wire u_ddr_mc_phy_wrapper_n_916; wire u_ddr_mc_phy_wrapper_n_917; wire u_ddr_mc_phy_wrapper_n_918; wire u_ddr_mc_phy_wrapper_n_919; wire u_ddr_mc_phy_wrapper_n_920; wire u_ddr_mc_phy_wrapper_n_921; wire u_ddr_mc_phy_wrapper_n_922; wire u_ddr_mc_phy_wrapper_n_923; wire u_ddr_mc_phy_wrapper_n_924; wire u_ddr_mc_phy_wrapper_n_925; wire u_ddr_mc_phy_wrapper_n_926; wire u_ddr_mc_phy_wrapper_n_927; wire u_ddr_mc_phy_wrapper_n_928; wire u_ddr_mc_phy_wrapper_n_929; wire u_ddr_mc_phy_wrapper_n_930; wire u_ddr_mc_phy_wrapper_n_931; wire u_ddr_mc_phy_wrapper_n_932; wire u_ddr_mc_phy_wrapper_n_933; wire u_ddr_mc_phy_wrapper_n_934; wire u_ddr_mc_phy_wrapper_n_935; wire u_ddr_mc_phy_wrapper_n_936; wire u_ddr_mc_phy_wrapper_n_937; wire u_ddr_mc_phy_wrapper_n_938; wire u_ddr_mc_phy_wrapper_n_939; wire u_ddr_mc_phy_wrapper_n_940; wire u_ddr_mc_phy_wrapper_n_941; wire u_ddr_mc_phy_wrapper_n_942; wire u_ddr_mc_phy_wrapper_n_943; wire u_ddr_mc_phy_wrapper_n_944; wire u_ddr_mc_phy_wrapper_n_945; wire u_ddr_mc_phy_wrapper_n_946; wire u_ddr_mc_phy_wrapper_n_947; wire u_ddr_mc_phy_wrapper_n_948; wire u_ddr_mc_phy_wrapper_n_949; wire u_ddr_mc_phy_wrapper_n_950; wire u_ddr_mc_phy_wrapper_n_951; wire u_ddr_mc_phy_wrapper_n_952; wire u_ddr_mc_phy_wrapper_n_953; wire u_ddr_mc_phy_wrapper_n_954; wire u_ddr_mc_phy_wrapper_n_955; wire u_ddr_mc_phy_wrapper_n_956; wire u_ddr_mc_phy_wrapper_n_957; wire u_ddr_mc_phy_wrapper_n_958; wire u_ddr_mc_phy_wrapper_n_959; wire u_ddr_mc_phy_wrapper_n_960; wire u_ddr_mc_phy_wrapper_n_961; wire u_ddr_mc_phy_wrapper_n_962; wire u_ddr_mc_phy_wrapper_n_963; wire u_ddr_mc_phy_wrapper_n_964; wire u_ddr_mc_phy_wrapper_n_967; wire u_ddr_mc_phy_wrapper_n_968; wire u_ddr_mc_phy_wrapper_n_969; wire u_ddr_mc_phy_wrapper_n_970; wire u_ddr_mc_phy_wrapper_n_971; wire u_ddr_mc_phy_wrapper_n_972; wire u_ddr_mc_phy_wrapper_n_973; wire u_ddr_mc_phy_wrapper_n_974; wire u_ddr_mc_phy_wrapper_n_975; wire u_ddr_mc_phy_wrapper_n_976; wire u_ddr_mc_phy_wrapper_n_977; wire u_ddr_mc_phy_wrapper_n_978; wire u_ddr_mc_phy_wrapper_n_979; wire u_ddr_mc_phy_wrapper_n_980; wire u_ddr_mc_phy_wrapper_n_981; wire u_ddr_mc_phy_wrapper_n_982; wire u_ddr_mc_phy_wrapper_n_983; wire u_ddr_mc_phy_wrapper_n_984; wire u_ddr_mc_phy_wrapper_n_985; wire u_ddr_mc_phy_wrapper_n_986; wire u_ddr_mc_phy_wrapper_n_987; wire u_ddr_mc_phy_wrapper_n_988; wire u_ddr_mc_phy_wrapper_n_989; wire u_ddr_mc_phy_wrapper_n_990; wire u_ddr_mc_phy_wrapper_n_991; wire u_ddr_mc_phy_wrapper_n_992; wire u_ddr_mc_phy_wrapper_n_993; wire u_ddr_mc_phy_wrapper_n_994; wire u_ddr_mc_phy_wrapper_n_995; wire u_ddr_mc_phy_wrapper_n_996; wire u_ddr_mc_phy_wrapper_n_997; wire u_ddr_mc_phy_wrapper_n_998; wire u_ddr_mc_phy_wrapper_n_999; wire \u_ddr_phy_wrcal/p_0_out ; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; ddr3_ifmig_7series_v4_0_ddr_calib_top u_ddr_calib_top (.A(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ), .\A[0]__0 (u_ddr_calib_top_n_877), .\A[0]__4 (u_ddr_calib_top_n_876), .\A[1]_0 (u_ddr_mc_phy_wrapper_n_813), .\A[1]_1 (u_ddr_mc_phy_wrapper_n_805), .\A[1]_10 (u_ddr_mc_phy_wrapper_n_798), .\A[1]_11 (u_ddr_mc_phy_wrapper_n_790), .\A[1]_12 (u_ddr_mc_phy_wrapper_n_782), .\A[1]_13 (u_ddr_mc_phy_wrapper_n_774), .\A[1]_14 (u_ddr_mc_phy_wrapper_n_766), .\A[1]_15 (u_ddr_mc_phy_wrapper_n_758), .\A[1]_16 (u_ddr_mc_phy_wrapper_n_815), .\A[1]_17 (u_ddr_mc_phy_wrapper_n_807), .\A[1]_18 (u_ddr_mc_phy_wrapper_n_799), .\A[1]_19 (u_ddr_mc_phy_wrapper_n_791), .\A[1]_2 (u_ddr_mc_phy_wrapper_n_797), .\A[1]_20 (u_ddr_mc_phy_wrapper_n_783), .\A[1]_21 (u_ddr_mc_phy_wrapper_n_775), .\A[1]_22 (u_ddr_mc_phy_wrapper_n_767), .\A[1]_23 (u_ddr_mc_phy_wrapper_n_759), .\A[1]_24 (u_ddr_mc_phy_wrapper_n_816), .\A[1]_25 (u_ddr_mc_phy_wrapper_n_808), .\A[1]_26 (u_ddr_mc_phy_wrapper_n_800), .\A[1]_27 (u_ddr_mc_phy_wrapper_n_792), .\A[1]_28 (u_ddr_mc_phy_wrapper_n_784), .\A[1]_29 (u_ddr_mc_phy_wrapper_n_776), .\A[1]_3 (u_ddr_mc_phy_wrapper_n_789), .\A[1]_30 (u_ddr_mc_phy_wrapper_n_768), .\A[1]_31 (u_ddr_mc_phy_wrapper_n_760), .\A[1]_32 (u_ddr_mc_phy_wrapper_n_817), .\A[1]_33 (u_ddr_mc_phy_wrapper_n_809), .\A[1]_34 (u_ddr_mc_phy_wrapper_n_801), .\A[1]_35 (u_ddr_mc_phy_wrapper_n_793), .\A[1]_36 (u_ddr_mc_phy_wrapper_n_785), .\A[1]_37 (u_ddr_mc_phy_wrapper_n_777), .\A[1]_38 (u_ddr_mc_phy_wrapper_n_769), .\A[1]_39 (u_ddr_mc_phy_wrapper_n_761), .\A[1]_4 (u_ddr_mc_phy_wrapper_n_781), .\A[1]_40 (u_ddr_mc_phy_wrapper_n_818), .\A[1]_41 (u_ddr_mc_phy_wrapper_n_810), .\A[1]_42 (u_ddr_mc_phy_wrapper_n_802), .\A[1]_43 (u_ddr_mc_phy_wrapper_n_794), .\A[1]_44 (u_ddr_mc_phy_wrapper_n_786), .\A[1]_45 (u_ddr_mc_phy_wrapper_n_778), .\A[1]_46 (u_ddr_mc_phy_wrapper_n_770), .\A[1]_47 (u_ddr_mc_phy_wrapper_n_762), .\A[1]_48 (u_ddr_mc_phy_wrapper_n_819), .\A[1]_49 (u_ddr_mc_phy_wrapper_n_811), .\A[1]_5 (u_ddr_mc_phy_wrapper_n_773), .\A[1]_50 (u_ddr_mc_phy_wrapper_n_803), .\A[1]_51 (u_ddr_mc_phy_wrapper_n_795), .\A[1]_52 (u_ddr_mc_phy_wrapper_n_787), .\A[1]_53 (u_ddr_mc_phy_wrapper_n_779), .\A[1]_54 (u_ddr_mc_phy_wrapper_n_771), .\A[1]_55 (u_ddr_mc_phy_wrapper_n_763), .\A[1]_56 (u_ddr_mc_phy_wrapper_n_820), .\A[1]_57 (u_ddr_mc_phy_wrapper_n_812), .\A[1]_58 (u_ddr_mc_phy_wrapper_n_804), .\A[1]_59 (u_ddr_mc_phy_wrapper_n_796), .\A[1]_6 (u_ddr_mc_phy_wrapper_n_765), .\A[1]_60 (u_ddr_mc_phy_wrapper_n_788), .\A[1]_61 (u_ddr_mc_phy_wrapper_n_780), .\A[1]_62 (u_ddr_mc_phy_wrapper_n_772), .\A[1]_63 (u_ddr_mc_phy_wrapper_n_764), .\A[1]_7 (u_ddr_mc_phy_wrapper_n_757), .\A[1]_8 (u_ddr_mc_phy_wrapper_n_814), .\A[1]_9 (u_ddr_mc_phy_wrapper_n_806), .\A[1]__0 (u_ddr_calib_top_n_879), .\A[1]__3 (u_ddr_calib_top_n_881), .\A[1]__4 (u_ddr_calib_top_n_464), .\A[1]__4_0 (u_ddr_calib_top_n_880), .\A[2]__1 (u_ddr_calib_top_n_882), .\A[2]__2 (u_ddr_calib_top_n_878), .\A[2]__2_0 (u_ddr_mc_phy_wrapper_n_30), .A_1__s_port_(u_ddr_calib_top_n_461), .A_rst_primitives_reg(u_ddr_mc_phy_wrapper_n_756), .CLK(CLK), .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}), .D({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }), .D0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ), .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .D2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ), .D_po_coarse_enable110_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ), .D_po_counter_read_en122_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ), .D_po_fine_enable107_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ), .D_po_fine_inc113_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ), .D_po_sel_fine_oclk_delay125_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ), .E(\resume_wait_r_reg[5] ), .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ), .LD0_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ), .LD0_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ), .LD0_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ), .Q(Q), .SR(SR), .SS(SS), .app_zq_r_reg(app_zq_r_reg), .\byte_r_reg[0] (u_ddr_calib_top_n_809), .\byte_r_reg[0]_0 ({\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }), .\byte_r_reg[1] (u_ddr_calib_top_n_810), .\byte_sel_data_map_reg[1] (u_ddr_calib_top_n_875), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1] ), .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2] ), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4] ), .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ), .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0] ), .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1] ), .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2] ), .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3] ), .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4] ), .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ), .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_reg[5]_0 ), .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0), .\complex_row_cnt_ocal_reg[0] (\complex_row_cnt_ocal_reg[0] ), .\data_offset_1_i1_reg[5] (mux_data_offset_1), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (u_ddr_calib_top_n_405), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (u_ddr_calib_top_n_415), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (u_ddr_calib_top_n_425), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (u_ddr_calib_top_n_449), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_1127), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (u_ddr_mc_phy_wrapper_n_104), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\not_strict_mode.app_rd_data_reg[6] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\not_strict_mode.app_rd_data_reg[14] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\not_strict_mode.app_rd_data_reg[22] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\not_strict_mode.app_rd_data_reg[29] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\not_strict_mode.app_rd_data_reg[5] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\not_strict_mode.app_rd_data_reg[13] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\not_strict_mode.app_rd_data_reg[21] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\not_strict_mode.app_rd_data_reg[28] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\not_strict_mode.app_rd_data_reg[4] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\not_strict_mode.app_rd_data_reg[12] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\not_strict_mode.app_rd_data_reg[20] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\not_strict_mode.app_rd_data_reg[27] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\not_strict_mode.app_rd_data_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\not_strict_mode.app_rd_data_reg[11] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\not_strict_mode.app_rd_data_reg[19] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\not_strict_mode.app_rd_data_reg[26] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\not_strict_mode.app_rd_data_reg[2] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\not_strict_mode.app_rd_data_reg[10] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\not_strict_mode.app_rd_data_reg[18] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\not_strict_mode.app_rd_data_reg[25] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\not_strict_mode.app_rd_data_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\not_strict_mode.app_rd_data_reg[9] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\not_strict_mode.app_rd_data_reg[17] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\not_strict_mode.app_rd_data_reg[24] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\not_strict_mode.app_rd_data_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\not_strict_mode.app_rd_data_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\not_strict_mode.app_rd_data_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\not_strict_mode.app_rd_data_reg[30] ), .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .fine_adjust_reg(fine_adjust_reg), .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}), .\fine_delay_mod_reg[20] (u_ddr_calib_top_n_841), .\fine_delay_mod_reg[26] (u_ddr_calib_top_n_855), .\fine_delay_mod_reg[5] (u_ddr_calib_top_n_840), .\fine_delay_r_reg[26] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}), .\fine_delay_r_reg[26]_0 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}), .\fine_delay_r_reg[26]_1 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}), .\fine_delay_r_reg[2] (u_ddr_calib_top_n_448), .\fine_delay_r_reg[5] (u_ddr_calib_top_n_404), .\fine_delay_r_reg[5]_0 (u_ddr_calib_top_n_414), .\fine_delay_r_reg[5]_1 (u_ddr_calib_top_n_424), .fine_delay_sel_r(fine_delay_sel_r), .fine_delay_sel_r_reg(u_ddr_calib_top_n_50), .\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (byte_sel_cnt), .\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_856), .\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_857), .\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_858), .\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_859), .\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_860), .\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_861), .idelay_inc(idelay_inc), .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_5(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ), .\idelay_tap_cnt_r_reg[0][3][0] (po_stg2_wrcal_cnt), .ififo_rst_reg(u_ddr_calib_top_n_409), .ififo_rst_reg_0(u_ddr_calib_top_n_419), .ififo_rst_reg_1(u_ddr_calib_top_n_429), .ififo_rst_reg_2(u_ddr_calib_top_n_453), .in0({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}), .init_calib_complete_r_reg(init_calib_complete_r_reg), .maint_prescaler_r1(maint_prescaler_r1), .\mcGo_r_reg[15] (\calib_seq_reg[0] ), .mc_address({mc_address[37],mc_address[35:14],mc_address[12:0]}), .mc_bank(mc_bank), .mc_cas_n(mc_cas_n), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_cs_n(mc_cs_n), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n), .mc_we_n(mc_we_n), .mc_wrdata_en(mc_wrdata_en), .mem_out({mem_out[10:8],mem_out[2:0]}), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mux_cmd_wren(mux_cmd_wren), .mux_reset_n(mux_reset_n), .mux_wrdata_en(mux_wrdata_en), .my_empty(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .my_empty_6(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .my_empty_7(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .my_empty_8(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_61), .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_60), .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63), .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_102), .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_67), .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66), .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_65), .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_64), .\my_empty_reg[7] (u_ddr_calib_top_n_37), .\my_empty_reg[7]_0 ({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}), .\my_empty_reg[7]_1 ({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}), .\my_empty_reg[7]_10 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\my_empty_reg[7]_11 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\my_empty_reg[7]_12 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\my_empty_reg[7]_13 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\my_empty_reg[7]_14 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\my_empty_reg[7]_15 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .\my_empty_reg[7]_16 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\my_empty_reg[7]_17 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\my_empty_reg[7]_18 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\my_empty_reg[7]_19 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .\my_empty_reg[7]_2 ({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}), .\my_empty_reg[7]_20 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .\my_empty_reg[7]_21 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\my_empty_reg[7]_22 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\my_empty_reg[7]_23 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\my_empty_reg[7]_24 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .\my_empty_reg[7]_25 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .\my_empty_reg[7]_26 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ), .\my_empty_reg[7]_27 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ), .\my_empty_reg[7]_28 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ), .\my_empty_reg[7]_29 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .\my_empty_reg[7]_3 ({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}), .\my_empty_reg[7]_30 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .\my_empty_reg[7]_31 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .\my_empty_reg[7]_32 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ), .\my_empty_reg[7]_33 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ), .\my_empty_reg[7]_34 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ), .\my_empty_reg[7]_35 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ), .\my_empty_reg[7]_36 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ), .\my_empty_reg[7]_37 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ), .\my_empty_reg[7]_38 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ), .\my_empty_reg[7]_39 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ), .\my_empty_reg[7]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\my_empty_reg[7]_40 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ), .\my_empty_reg[7]_41 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .\my_empty_reg[7]_42 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ), .\my_empty_reg[7]_5 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\my_empty_reg[7]_6 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\my_empty_reg[7]_7 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\my_empty_reg[7]_8 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\my_empty_reg[7]_9 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\my_full_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .\my_full_reg[3]_0 (phy_dout[3:2]), .out(u_ddr_calib_top_n_45), .p_0_out(\u_ddr_phy_wrcal/p_0_out ), .p_81_in(p_81_in), .pd_out(pd_out), .\periodic_rd_generation.periodic_rd_timer_r_reg[1] (\periodic_rd_generation.periodic_rd_timer_r_reg[1] ), .\phy_ctl_wd_i1_reg[24] ({calib_seq,p_1_out[22:17],p_1_out[2:0]}), .phy_dout({phy_dout[1:0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}), .phy_if_reset(phy_if_reset), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .pi_cnt_dec_reg(pi_cnt_dec_reg), .\pi_counter_read_val_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ), .\pi_dqs_found_lanes_r1_reg[0] (u_ddr_calib_top_n_447), .\pi_dqs_found_lanes_r1_reg[0]_0 (u_ddr_calib_top_n_454), .\pi_dqs_found_lanes_r1_reg[0]_1 (u_ddr_calib_top_n_455), .\pi_dqs_found_lanes_r1_reg[0]_2 (u_ddr_calib_top_n_456), .\pi_dqs_found_lanes_r1_reg[1] (u_ddr_calib_top_n_423), .\pi_dqs_found_lanes_r1_reg[1]_0 (u_ddr_calib_top_n_430), .\pi_dqs_found_lanes_r1_reg[1]_1 (u_ddr_calib_top_n_431), .\pi_dqs_found_lanes_r1_reg[1]_2 (u_ddr_calib_top_n_432), .\pi_dqs_found_lanes_r1_reg[1]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ), .\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_413), .\pi_dqs_found_lanes_r1_reg[2]_0 (u_ddr_calib_top_n_420), .\pi_dqs_found_lanes_r1_reg[2]_1 (u_ddr_calib_top_n_421), .\pi_dqs_found_lanes_r1_reg[2]_2 (u_ddr_calib_top_n_422), .\pi_dqs_found_lanes_r1_reg[2]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ), .\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_403), .\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_calib_top_n_410), .\pi_dqs_found_lanes_r1_reg[3]_1 (u_ddr_calib_top_n_411), .\pi_dqs_found_lanes_r1_reg[3]_2 (u_ddr_calib_top_n_412), .\pi_dqs_found_lanes_r1_reg[3]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ), .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg), .\pi_rst_stg1_cal_r_reg[0] (\pi_rst_stg1_cal_r_reg[0] ), .po_cnt_dec_reg(po_cnt_dec_reg), .\po_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_106), .\po_counter_read_val_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}), .\po_counter_read_val_reg[8] (u_ddr_calib_top_n_385), .\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_386), .\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_387), .\po_counter_read_val_reg[8]_10 (u_ddr_calib_top_n_396), .\po_counter_read_val_reg[8]_11 (u_ddr_calib_top_n_397), .\po_counter_read_val_reg[8]_12 (u_ddr_calib_top_n_399), .\po_counter_read_val_reg[8]_13 (u_ddr_calib_top_n_400), .\po_counter_read_val_reg[8]_14 (u_ddr_calib_top_n_401), .\po_counter_read_val_reg[8]_15 (u_ddr_calib_top_n_402), .\po_counter_read_val_reg[8]_16 (u_ddr_calib_top_n_406), .\po_counter_read_val_reg[8]_17 (u_ddr_calib_top_n_407), .\po_counter_read_val_reg[8]_18 (u_ddr_calib_top_n_408), .\po_counter_read_val_reg[8]_19 (u_ddr_calib_top_n_416), .\po_counter_read_val_reg[8]_2 (u_ddr_calib_top_n_388), .\po_counter_read_val_reg[8]_20 (u_ddr_calib_top_n_417), .\po_counter_read_val_reg[8]_21 (u_ddr_calib_top_n_418), .\po_counter_read_val_reg[8]_22 (u_ddr_calib_top_n_426), .\po_counter_read_val_reg[8]_23 (u_ddr_calib_top_n_427), .\po_counter_read_val_reg[8]_24 (u_ddr_calib_top_n_428), .\po_counter_read_val_reg[8]_25 (u_ddr_calib_top_n_450), .\po_counter_read_val_reg[8]_26 (u_ddr_calib_top_n_451), .\po_counter_read_val_reg[8]_27 (u_ddr_calib_top_n_452), .\po_counter_read_val_reg[8]_28 (u_ddr_calib_top_n_457), .\po_counter_read_val_reg[8]_29 (u_ddr_calib_top_n_458), .\po_counter_read_val_reg[8]_3 (u_ddr_calib_top_n_389), .\po_counter_read_val_reg[8]_30 ({\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}), .\po_counter_read_val_reg[8]_31 ({\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}), .\po_counter_read_val_reg[8]_4 (u_ddr_calib_top_n_390), .\po_counter_read_val_reg[8]_5 (u_ddr_calib_top_n_391), .\po_counter_read_val_reg[8]_6 (u_ddr_calib_top_n_392), .\po_counter_read_val_reg[8]_7 (u_ddr_calib_top_n_393), .\po_counter_read_val_reg[8]_8 (u_ddr_calib_top_n_394), .\po_counter_read_val_reg[8]_9 (u_ddr_calib_top_n_395), .\po_rdval_cnt_reg[8] ({calib_sel__0,calib_sel}), .\po_stg2_wrcal_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_1152), .\po_stg2_wrcal_cnt_reg[1]_0 (u_ddr_mc_phy_wrapper_n_1156), .\po_stg2_wrcal_cnt_reg[1]_1 (u_ddr_mc_phy_wrapper_n_1171), .\po_stg2_wrcal_cnt_reg[1]_10 (u_ddr_mc_phy_wrapper_n_1136), .\po_stg2_wrcal_cnt_reg[1]_11 (u_ddr_mc_phy_wrapper_n_1137), .\po_stg2_wrcal_cnt_reg[1]_12 (u_ddr_mc_phy_wrapper_n_1138), .\po_stg2_wrcal_cnt_reg[1]_13 (u_ddr_mc_phy_wrapper_n_1139), .\po_stg2_wrcal_cnt_reg[1]_14 (u_ddr_mc_phy_wrapper_n_1140), .\po_stg2_wrcal_cnt_reg[1]_15 (u_ddr_mc_phy_wrapper_n_1141), .\po_stg2_wrcal_cnt_reg[1]_16 (u_ddr_mc_phy_wrapper_n_1142), .\po_stg2_wrcal_cnt_reg[1]_17 (u_ddr_mc_phy_wrapper_n_1143), .\po_stg2_wrcal_cnt_reg[1]_18 (u_ddr_mc_phy_wrapper_n_1144), .\po_stg2_wrcal_cnt_reg[1]_19 (u_ddr_mc_phy_wrapper_n_1145), .\po_stg2_wrcal_cnt_reg[1]_2 (u_ddr_mc_phy_wrapper_n_1175), .\po_stg2_wrcal_cnt_reg[1]_20 (u_ddr_mc_phy_wrapper_n_1146), .\po_stg2_wrcal_cnt_reg[1]_21 (u_ddr_mc_phy_wrapper_n_1147), .\po_stg2_wrcal_cnt_reg[1]_22 (u_ddr_mc_phy_wrapper_n_1148), .\po_stg2_wrcal_cnt_reg[1]_23 (u_ddr_mc_phy_wrapper_n_1149), .\po_stg2_wrcal_cnt_reg[1]_24 (u_ddr_mc_phy_wrapper_n_1150), .\po_stg2_wrcal_cnt_reg[1]_25 (u_ddr_mc_phy_wrapper_n_1151), .\po_stg2_wrcal_cnt_reg[1]_26 (u_ddr_mc_phy_wrapper_n_1153), .\po_stg2_wrcal_cnt_reg[1]_27 (u_ddr_mc_phy_wrapper_n_1154), .\po_stg2_wrcal_cnt_reg[1]_28 (u_ddr_mc_phy_wrapper_n_1155), .\po_stg2_wrcal_cnt_reg[1]_29 (u_ddr_mc_phy_wrapper_n_1157), .\po_stg2_wrcal_cnt_reg[1]_3 (u_ddr_mc_phy_wrapper_n_1129), .\po_stg2_wrcal_cnt_reg[1]_30 (u_ddr_mc_phy_wrapper_n_1158), .\po_stg2_wrcal_cnt_reg[1]_31 (u_ddr_mc_phy_wrapper_n_1159), .\po_stg2_wrcal_cnt_reg[1]_32 (u_ddr_mc_phy_wrapper_n_1160), .\po_stg2_wrcal_cnt_reg[1]_33 (u_ddr_mc_phy_wrapper_n_1161), .\po_stg2_wrcal_cnt_reg[1]_34 (u_ddr_mc_phy_wrapper_n_1162), .\po_stg2_wrcal_cnt_reg[1]_35 (u_ddr_mc_phy_wrapper_n_1163), .\po_stg2_wrcal_cnt_reg[1]_36 (u_ddr_mc_phy_wrapper_n_1164), .\po_stg2_wrcal_cnt_reg[1]_37 (u_ddr_mc_phy_wrapper_n_1165), .\po_stg2_wrcal_cnt_reg[1]_38 (u_ddr_mc_phy_wrapper_n_1166), .\po_stg2_wrcal_cnt_reg[1]_39 (u_ddr_mc_phy_wrapper_n_1167), .\po_stg2_wrcal_cnt_reg[1]_4 (u_ddr_mc_phy_wrapper_n_1130), .\po_stg2_wrcal_cnt_reg[1]_40 (u_ddr_mc_phy_wrapper_n_1168), .\po_stg2_wrcal_cnt_reg[1]_41 (u_ddr_mc_phy_wrapper_n_1169), .\po_stg2_wrcal_cnt_reg[1]_42 (u_ddr_mc_phy_wrapper_n_1170), .\po_stg2_wrcal_cnt_reg[1]_43 (u_ddr_mc_phy_wrapper_n_1172), .\po_stg2_wrcal_cnt_reg[1]_44 (u_ddr_mc_phy_wrapper_n_1173), .\po_stg2_wrcal_cnt_reg[1]_45 (u_ddr_mc_phy_wrapper_n_1174), .\po_stg2_wrcal_cnt_reg[1]_46 (u_ddr_mc_phy_wrapper_n_1176), .\po_stg2_wrcal_cnt_reg[1]_47 (u_ddr_mc_phy_wrapper_n_1177), .\po_stg2_wrcal_cnt_reg[1]_48 (u_ddr_mc_phy_wrapper_n_1178), .\po_stg2_wrcal_cnt_reg[1]_49 (u_ddr_mc_phy_wrapper_n_1179), .\po_stg2_wrcal_cnt_reg[1]_5 (u_ddr_mc_phy_wrapper_n_1131), .\po_stg2_wrcal_cnt_reg[1]_50 (u_ddr_mc_phy_wrapper_n_1180), .\po_stg2_wrcal_cnt_reg[1]_51 (u_ddr_mc_phy_wrapper_n_1181), .\po_stg2_wrcal_cnt_reg[1]_52 (u_ddr_mc_phy_wrapper_n_1182), .\po_stg2_wrcal_cnt_reg[1]_53 (u_ddr_mc_phy_wrapper_n_1183), .\po_stg2_wrcal_cnt_reg[1]_54 (u_ddr_mc_phy_wrapper_n_1184), .\po_stg2_wrcal_cnt_reg[1]_55 (u_ddr_mc_phy_wrapper_n_1185), .\po_stg2_wrcal_cnt_reg[1]_56 (u_ddr_mc_phy_wrapper_n_1186), .\po_stg2_wrcal_cnt_reg[1]_57 (u_ddr_mc_phy_wrapper_n_1187), .\po_stg2_wrcal_cnt_reg[1]_58 (u_ddr_mc_phy_wrapper_n_1188), .\po_stg2_wrcal_cnt_reg[1]_59 (u_ddr_mc_phy_wrapper_n_1189), .\po_stg2_wrcal_cnt_reg[1]_6 (u_ddr_mc_phy_wrapper_n_1132), .\po_stg2_wrcal_cnt_reg[1]_60 (u_ddr_mc_phy_wrapper_n_1190), .\po_stg2_wrcal_cnt_reg[1]_61 (u_ddr_mc_phy_wrapper_n_1191), .\po_stg2_wrcal_cnt_reg[1]_7 (u_ddr_mc_phy_wrapper_n_1133), .\po_stg2_wrcal_cnt_reg[1]_8 (u_ddr_mc_phy_wrapper_n_1134), .\po_stg2_wrcal_cnt_reg[1]_9 (u_ddr_mc_phy_wrapper_n_1135), .poc_sample_pd(poc_sample_pd), .prbs_rdlvl_start_r_reg(u_ddr_calib_top_n_47), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .\rd_mux_sel_r_reg[1] (u_ddr_mc_phy_wrapper_n_490), .\rd_mux_sel_r_reg[1]_0 (u_ddr_mc_phy_wrapper_n_482), .\rd_mux_sel_r_reg[1]_1 (u_ddr_mc_phy_wrapper_n_474), .\rd_mux_sel_r_reg[1]_10 (u_ddr_mc_phy_wrapper_n_467), .\rd_mux_sel_r_reg[1]_11 (u_ddr_mc_phy_wrapper_n_459), .\rd_mux_sel_r_reg[1]_12 (u_ddr_mc_phy_wrapper_n_451), .\rd_mux_sel_r_reg[1]_13 (u_ddr_mc_phy_wrapper_n_443), .\rd_mux_sel_r_reg[1]_14 (u_ddr_mc_phy_wrapper_n_435), .\rd_mux_sel_r_reg[1]_15 (u_ddr_mc_phy_wrapper_n_492), .\rd_mux_sel_r_reg[1]_16 (u_ddr_mc_phy_wrapper_n_484), .\rd_mux_sel_r_reg[1]_17 (u_ddr_mc_phy_wrapper_n_476), .\rd_mux_sel_r_reg[1]_18 (u_ddr_mc_phy_wrapper_n_468), .\rd_mux_sel_r_reg[1]_19 (u_ddr_mc_phy_wrapper_n_460), .\rd_mux_sel_r_reg[1]_2 (u_ddr_mc_phy_wrapper_n_466), .\rd_mux_sel_r_reg[1]_20 (u_ddr_mc_phy_wrapper_n_452), .\rd_mux_sel_r_reg[1]_21 (u_ddr_mc_phy_wrapper_n_444), .\rd_mux_sel_r_reg[1]_22 (u_ddr_mc_phy_wrapper_n_436), .\rd_mux_sel_r_reg[1]_23 (u_ddr_mc_phy_wrapper_n_493), .\rd_mux_sel_r_reg[1]_24 (u_ddr_mc_phy_wrapper_n_485), .\rd_mux_sel_r_reg[1]_25 (u_ddr_mc_phy_wrapper_n_477), .\rd_mux_sel_r_reg[1]_26 (u_ddr_mc_phy_wrapper_n_469), .\rd_mux_sel_r_reg[1]_27 (u_ddr_mc_phy_wrapper_n_461), .\rd_mux_sel_r_reg[1]_28 (u_ddr_mc_phy_wrapper_n_453), .\rd_mux_sel_r_reg[1]_29 (u_ddr_mc_phy_wrapper_n_445), .\rd_mux_sel_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_458), .\rd_mux_sel_r_reg[1]_30 (u_ddr_mc_phy_wrapper_n_437), .\rd_mux_sel_r_reg[1]_31 (u_ddr_mc_phy_wrapper_n_494), .\rd_mux_sel_r_reg[1]_32 (u_ddr_mc_phy_wrapper_n_486), .\rd_mux_sel_r_reg[1]_33 (u_ddr_mc_phy_wrapper_n_478), .\rd_mux_sel_r_reg[1]_34 (u_ddr_mc_phy_wrapper_n_470), .\rd_mux_sel_r_reg[1]_35 (u_ddr_mc_phy_wrapper_n_462), .\rd_mux_sel_r_reg[1]_36 (u_ddr_mc_phy_wrapper_n_454), .\rd_mux_sel_r_reg[1]_37 (u_ddr_mc_phy_wrapper_n_446), .\rd_mux_sel_r_reg[1]_38 (u_ddr_mc_phy_wrapper_n_438), .\rd_mux_sel_r_reg[1]_39 (u_ddr_mc_phy_wrapper_n_495), .\rd_mux_sel_r_reg[1]_4 (u_ddr_mc_phy_wrapper_n_450), .\rd_mux_sel_r_reg[1]_40 (u_ddr_mc_phy_wrapper_n_487), .\rd_mux_sel_r_reg[1]_41 (u_ddr_mc_phy_wrapper_n_479), .\rd_mux_sel_r_reg[1]_42 (u_ddr_mc_phy_wrapper_n_471), .\rd_mux_sel_r_reg[1]_43 (u_ddr_mc_phy_wrapper_n_463), .\rd_mux_sel_r_reg[1]_44 (u_ddr_mc_phy_wrapper_n_455), .\rd_mux_sel_r_reg[1]_45 (u_ddr_mc_phy_wrapper_n_447), .\rd_mux_sel_r_reg[1]_46 (u_ddr_mc_phy_wrapper_n_439), .\rd_mux_sel_r_reg[1]_47 (u_ddr_mc_phy_wrapper_n_496), .\rd_mux_sel_r_reg[1]_48 (u_ddr_mc_phy_wrapper_n_488), .\rd_mux_sel_r_reg[1]_49 (u_ddr_mc_phy_wrapper_n_480), .\rd_mux_sel_r_reg[1]_5 (u_ddr_mc_phy_wrapper_n_442), .\rd_mux_sel_r_reg[1]_50 (u_ddr_mc_phy_wrapper_n_472), .\rd_mux_sel_r_reg[1]_51 (u_ddr_mc_phy_wrapper_n_464), .\rd_mux_sel_r_reg[1]_52 (u_ddr_mc_phy_wrapper_n_456), .\rd_mux_sel_r_reg[1]_53 (u_ddr_mc_phy_wrapper_n_448), .\rd_mux_sel_r_reg[1]_54 (u_ddr_mc_phy_wrapper_n_440), .\rd_mux_sel_r_reg[1]_55 (u_ddr_mc_phy_wrapper_n_497), .\rd_mux_sel_r_reg[1]_56 (u_ddr_mc_phy_wrapper_n_489), .\rd_mux_sel_r_reg[1]_57 (u_ddr_mc_phy_wrapper_n_481), .\rd_mux_sel_r_reg[1]_58 (u_ddr_mc_phy_wrapper_n_473), .\rd_mux_sel_r_reg[1]_59 (u_ddr_mc_phy_wrapper_n_465), .\rd_mux_sel_r_reg[1]_6 (u_ddr_mc_phy_wrapper_n_434), .\rd_mux_sel_r_reg[1]_60 (u_ddr_mc_phy_wrapper_n_457), .\rd_mux_sel_r_reg[1]_61 (u_ddr_mc_phy_wrapper_n_449), .\rd_mux_sel_r_reg[1]_62 (u_ddr_mc_phy_wrapper_n_441), .\rd_mux_sel_r_reg[1]_7 (u_ddr_mc_phy_wrapper_n_491), .\rd_mux_sel_r_reg[1]_8 (u_ddr_mc_phy_wrapper_n_483), .\rd_mux_sel_r_reg[1]_9 (u_ddr_mc_phy_wrapper_n_475), .\rd_ptr_reg[3] ({\rd_ptr_reg[3] [69:66],\rd_ptr_reg[3] [61:58],\rd_ptr_reg[3] [53:34],\rd_ptr_reg[3] [29:26],\rd_ptr_reg[3] [20:18],\rd_ptr_reg[3] [12:10]}), .\rd_ptr_reg[3]_0 ({\rd_ptr_reg[3]_0 [25:22],\rd_ptr_reg[3]_0 [17:14],\rd_ptr_reg[3]_0 [11:8]}), .\rd_ptr_reg[3]_1 ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}), .\rd_ptr_reg[3]_2 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}), .\rd_ptr_reg[3]_3 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}), .\rd_ptr_reg[3]_4 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}), .\rd_ptr_reg[3]_5 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}), .\rd_ptr_timing_reg[0] (u_ddr_calib_top_n_38), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0] ), .\rd_ptr_timing_reg[0]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\rd_ptr_timing_reg[0]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\rd_ptr_timing_reg[0]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\rd_ptr_timing_reg[0]_4 (\rd_ptr_timing_reg[0]_0 ), .\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ({u_ddr_calib_top_n_833,u_ddr_calib_top_n_834}), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .rstdiv0_sync_r1_reg_rep(in0), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0), .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0), .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1), .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg), .\samps_r_reg[9] (\samps_r_reg[9] ), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .tempmon_sample_en(tempmon_sample_en), .\zero2fuzz_r_reg[0] (D)); ddr3_ifmig_7series_v4_0_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper (.A(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ), .CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}), .D({calib_seq,p_1_out[22:17],p_1_out[2:0]}), .D0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ), .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .D2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_po_coarse_enable110_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ), .D_po_counter_read_en122_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ), .D_po_fine_enable107_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ), .D_po_fine_inc113_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ), .D_po_sel_fine_oclk_delay125_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ), .E(u_ddr_calib_top_n_448), .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ), .LD0_3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ), .LD0_4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ), .LD0_5(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ), .Q(Q[287:256]), .RST0(RST0), .SR(SR), .\byte_r_reg[0] (u_ddr_mc_phy_wrapper_n_106), .\byte_r_reg[0]_0 (u_ddr_calib_top_n_809), .\byte_r_reg[1] (u_ddr_calib_top_n_810), .\calib_sel_reg[0] (u_ddr_calib_top_n_390), .\calib_sel_reg[0]_0 (u_ddr_calib_top_n_395), .\calib_sel_reg[0]_1 (u_ddr_calib_top_n_396), .\calib_sel_reg[0]_2 (u_ddr_calib_top_n_397), .\calib_sel_reg[0]_3 (u_ddr_calib_top_n_447), .\calib_sel_reg[0]_4 (u_ddr_calib_top_n_423), .\calib_sel_reg[0]_5 (u_ddr_calib_top_n_403), .\calib_sel_reg[0]_6 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}), .\calib_sel_reg[0]_7 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}), .\calib_sel_reg[1] (u_ddr_calib_top_n_386), .\calib_sel_reg[1]_0 (u_ddr_calib_top_n_387), .\calib_sel_reg[1]_1 (u_ddr_calib_top_n_388), .\calib_sel_reg[1]_2 (u_ddr_calib_top_n_389), .\calib_sel_reg[1]_3 (u_ddr_calib_top_n_391), .\calib_sel_reg[1]_4 (u_ddr_calib_top_n_392), .\calib_sel_reg[1]_5 (u_ddr_calib_top_n_393), .\calib_sel_reg[1]_6 (u_ddr_calib_top_n_394), .\calib_sel_reg[1]_7 (u_ddr_calib_top_n_413), .\calib_sel_reg[1]_8 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}), .\calib_sel_reg[3] ({calib_sel__0,calib_sel}), .\calib_seq_reg[0] (\calib_seq_reg[0] ), .\calib_zero_inputs_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ), .\calib_zero_inputs_reg[0]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ), .\calib_zero_inputs_reg[0]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ), .ck_po_stg2_f_en_reg(u_ddr_calib_top_n_451), .ck_po_stg2_f_en_reg_0(u_ddr_calib_top_n_427), .ck_po_stg2_f_en_reg_1(u_ddr_calib_top_n_417), .ck_po_stg2_f_en_reg_2(u_ddr_calib_top_n_407), .ck_po_stg2_f_indec_reg(u_ddr_calib_top_n_450), .ck_po_stg2_f_indec_reg_0(u_ddr_calib_top_n_426), .ck_po_stg2_f_indec_reg_1(u_ddr_calib_top_n_416), .ck_po_stg2_f_indec_reg_2(u_ddr_calib_top_n_406), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (mux_data_offset_1), .\data_bytes_r_reg[63] ({\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .delay_done_r4_reg(u_ddr_calib_top_n_400), .delay_done_r4_reg_0(u_ddr_calib_top_n_401), .delay_done_r4_reg_1(u_ddr_calib_top_n_399), .delay_done_r4_reg_2(u_ddr_calib_top_n_402), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}), .\fine_delay_mod_reg[23]_0 ({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }), .\fine_delay_mod_reg[26]_0 (u_ddr_mc_phy_wrapper_n_30), .fine_delay_sel_r(fine_delay_sel_r), .fine_delay_sel_reg(u_ddr_calib_top_n_50), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_calib_top_n_878), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (u_ddr_calib_top_n_877), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 (u_ddr_calib_top_n_876), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 (u_ddr_calib_top_n_879), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 (u_ddr_calib_top_n_881), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 (u_ddr_calib_top_n_880), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (byte_sel_cnt), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_calib_top_n_464), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (u_ddr_calib_top_n_461), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 (u_ddr_calib_top_n_882), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 (u_ddr_calib_top_n_875), .\gen_byte_sel_div1.calib_in_common_reg (u_ddr_calib_top_n_457), .\gen_byte_sel_div1.calib_in_common_reg_0 (u_ddr_calib_top_n_385), .\gen_byte_sel_div1.calib_in_common_reg_1 (u_ddr_calib_top_n_458), .\gen_byte_sel_div1.calib_in_common_reg_10 (u_ddr_calib_top_n_422), .\gen_byte_sel_div1.calib_in_common_reg_11 (u_ddr_calib_top_n_419), .\gen_byte_sel_div1.calib_in_common_reg_12 (u_ddr_calib_top_n_418), .\gen_byte_sel_div1.calib_in_common_reg_13 (u_ddr_calib_top_n_415), .\gen_byte_sel_div1.calib_in_common_reg_14 (u_ddr_calib_top_n_412), .\gen_byte_sel_div1.calib_in_common_reg_15 (u_ddr_calib_top_n_409), .\gen_byte_sel_div1.calib_in_common_reg_16 (u_ddr_calib_top_n_408), .\gen_byte_sel_div1.calib_in_common_reg_17 (u_ddr_calib_top_n_405), .\gen_byte_sel_div1.calib_in_common_reg_18 (u_ddr_calib_top_n_424), .\gen_byte_sel_div1.calib_in_common_reg_19 (u_ddr_calib_top_n_414), .\gen_byte_sel_div1.calib_in_common_reg_2 (u_ddr_calib_top_n_456), .\gen_byte_sel_div1.calib_in_common_reg_20 (u_ddr_calib_top_n_404), .\gen_byte_sel_div1.calib_in_common_reg_3 (u_ddr_calib_top_n_453), .\gen_byte_sel_div1.calib_in_common_reg_4 (u_ddr_calib_top_n_452), .\gen_byte_sel_div1.calib_in_common_reg_5 (u_ddr_calib_top_n_449), .\gen_byte_sel_div1.calib_in_common_reg_6 (u_ddr_calib_top_n_432), .\gen_byte_sel_div1.calib_in_common_reg_7 (u_ddr_calib_top_n_429), .\gen_byte_sel_div1.calib_in_common_reg_8 (u_ddr_calib_top_n_428), .\gen_byte_sel_div1.calib_in_common_reg_9 (u_ddr_calib_top_n_425), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_814), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_491), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_816), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_493), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_818), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_495), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_820), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_497), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_813), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_490), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_815), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (u_ddr_mc_phy_wrapper_n_492), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_817), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_494), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_819), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_496), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_806), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_483), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_808), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_485), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_810), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_487), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_812), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_489), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_805), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_482), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_807), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_484), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_809), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_486), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_811), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_488), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_798), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_475), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_800), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_477), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_802), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_479), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_804), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_481), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_797), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_474), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_799), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_476), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_801), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_478), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_803), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_480), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_790), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_467), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_792), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_469), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_794), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_471), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_796), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_473), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_789), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_466), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_791), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_468), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_793), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_470), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_795), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_472), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_782), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_459), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_784), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_461), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_786), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_463), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_788), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_465), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_781), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_458), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_783), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_460), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_785), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_462), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_787), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_464), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_774), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_451), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_776), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_453), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_778), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_455), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_780), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_457), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_773), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_450), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_775), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_452), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_777), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_454), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_779), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_456), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_766), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_443), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_768), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_445), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_770), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_447), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_772), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_449), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_765), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_442), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_767), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_444), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_769), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_446), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_771), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_448), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_758), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_435), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_760), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_437), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_762), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_439), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_764), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_441), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_757), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_434), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_759), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_436), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_761), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_438), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_763), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_440), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1144), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_1184), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1160), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1136), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1176), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1168), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1145), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1185), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1161), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1137), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1177), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1129), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1153), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1169), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1146), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1186), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1162), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1138), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1178), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1130), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1154), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1170), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1147), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1187), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1163), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1139), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1179), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1131), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1155), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1148), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1188), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1164), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1140), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1180), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1132), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1172), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1149), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1189), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1165), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1141), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1181), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1133), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1157), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1173), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1150), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1190), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1166), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1142), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1182), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1134), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1158), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1174), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1151), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1191), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1167), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1143), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1183), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1135), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1159), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1152), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1171), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1156), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1175), .\genblk9[0].fine_delay_incdec_pb_reg[0] (u_ddr_calib_top_n_855), .\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_856), .\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_857), .\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_858), .\genblk9[4].fine_delay_incdec_pb_reg[4] (u_ddr_calib_top_n_840), .\genblk9[4].fine_delay_incdec_pb_reg[4]_0 (u_ddr_calib_top_n_841), .\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_859), .\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_860), .\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_861), .idelay_inc(idelay_inc), .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ), .idle(idle), .in0(in0), .init_calib_complete_reg_rep(u_ddr_calib_top_n_37), .init_calib_complete_reg_rep__5(u_ddr_calib_top_n_38), .init_calib_complete_reg_rep__6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .init_calib_complete_reg_rep__6_0(app_zq_r_reg), .mc_address({mc_address[36],mc_address[13]}), .mc_cas_n(mc_cas_n[1]), .mem_out({mem_out[17:11],mem_out[7:3]}), .mem_refclk(mem_refclk), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .mux_cmd_wren(mux_cmd_wren), .mux_rd_valid_r_reg(u_ddr_mc_phy_wrapper_n_104), .mux_reset_n(mux_reset_n), .mux_wrdata(mux_wrdata), .mux_wrdata_en(mux_wrdata_en), .mux_wrdata_mask(mux_wrdata_mask), .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_60), .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_61), .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63), .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_64), .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_65), .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66), .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_67), .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_102), .\my_empty_reg[7] ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}), .\my_empty_reg[7]_0 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}), .\my_empty_reg[7]_1 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}), .\my_empty_reg[7]_2 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}), .\my_empty_reg[7]_3 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ), .\not_strict_mode.app_rd_data_reg[15]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), 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(\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\not_strict_mode.app_rd_data_reg[244]_0 (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\not_strict_mode.app_rd_data_reg[252]_0 (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255]_0 ), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ), .\not_strict_mode.app_rd_data_reg[31]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 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(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r_reg(ofs_rdy_r_reg), .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0), .out(u_ddr_calib_top_n_45), .p_0_out(\u_ddr_phy_wrcal/p_0_out ), .pd_out(pd_out), .phy_dout({phy_dout[1],\cmd_pipe_plus.mc_address_reg[43] [1],phy_dout[0],\cmd_pipe_plus.mc_address_reg[43] [0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}), .phy_if_empty_r_reg(u_ddr_mc_phy_wrapper_n_1127), .phy_if_reset(phy_if_reset), .phy_mc_ctl_full(phy_mc_ctl_full), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .\pi_dqs_found_lanes_r1_reg[3] ({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}), .pi_en_stg2_f_reg(u_ddr_calib_top_n_455), .pi_en_stg2_f_reg_0(u_ddr_calib_top_n_431), .pi_en_stg2_f_reg_1(u_ddr_calib_top_n_421), .pi_en_stg2_f_reg_2(u_ddr_calib_top_n_411), .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_756), .\pi_rdval_cnt_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ), .pi_stg2_f_incdec_reg(u_ddr_calib_top_n_454), .pi_stg2_f_incdec_reg_0(u_ddr_calib_top_n_430), .pi_stg2_f_incdec_reg_1(u_ddr_calib_top_n_420), .pi_stg2_f_incdec_reg_2(u_ddr_calib_top_n_410), .pll_locked(pll_locked), .\po_counter_read_val_r_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}), .\po_rdval_cnt_reg[8] ({\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}), .\po_rdval_cnt_reg[8]_0 ({\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}), .\po_stg2_wrcal_cnt_reg[1] (po_stg2_wrcal_cnt), .prbs_rdlvl_start_reg(u_ddr_calib_top_n_47), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_mux_sel_r_reg[1] ({u_ddr_calib_top_n_833,u_ddr_calib_top_n_834}), .\rd_ptr_reg[3] ({\rd_ptr_reg[3] [71:70],\rd_ptr_reg[3] [65:62],\rd_ptr_reg[3] [57:54],\rd_ptr_reg[3] [33:30],\rd_ptr_reg[3] [25:21],\rd_ptr_reg[3] [17:13],\rd_ptr_reg[3] [9:0]}), .\rd_ptr_reg[3]_0 ({\rd_ptr_reg[3]_0 [29:26],\rd_ptr_reg[3]_0 [21:18],\rd_ptr_reg[3]_0 [13:12],\rd_ptr_reg[3]_0 [7:0]}), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_1 ), .\write_buffer.wr_buf_out_data_reg[224] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\write_buffer.wr_buf_out_data_reg[225] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\write_buffer.wr_buf_out_data_reg[226] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\write_buffer.wr_buf_out_data_reg[227] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\write_buffer.wr_buf_out_data_reg[228] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .\write_buffer.wr_buf_out_data_reg[229] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\write_buffer.wr_buf_out_data_reg[230] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\write_buffer.wr_buf_out_data_reg[231] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\write_buffer.wr_buf_out_data_reg[232] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .\write_buffer.wr_buf_out_data_reg[233] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .\write_buffer.wr_buf_out_data_reg[234] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\write_buffer.wr_buf_out_data_reg[235] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\write_buffer.wr_buf_out_data_reg[236] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\write_buffer.wr_buf_out_data_reg[237] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .\write_buffer.wr_buf_out_data_reg[238] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .\write_buffer.wr_buf_out_data_reg[239] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ), .\write_buffer.wr_buf_out_data_reg[240] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ), .\write_buffer.wr_buf_out_data_reg[241] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ), .\write_buffer.wr_buf_out_data_reg[242] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .\write_buffer.wr_buf_out_data_reg[243] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .\write_buffer.wr_buf_out_data_reg[244] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .\write_buffer.wr_buf_out_data_reg[245] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ), .\write_buffer.wr_buf_out_data_reg[246] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ), .\write_buffer.wr_buf_out_data_reg[247] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ), .\write_buffer.wr_buf_out_data_reg[248] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ), .\write_buffer.wr_buf_out_data_reg[249] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ), .\write_buffer.wr_buf_out_data_reg[250] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ), .\write_buffer.wr_buf_out_data_reg[251] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ), .\write_buffer.wr_buf_out_data_reg[252] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ), .\write_buffer.wr_buf_out_data_reg[253] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ), .\write_buffer.wr_buf_out_data_reg[254] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .\write_buffer.wr_buf_out_data_reg[255] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_wrcal" *) module ddr3_ifmig_7series_v4_0_ddr_phy_wrcal (rd_active_r1, rd_active_r2, wrcal_pat_resume_r, wrcal_resume_w, idelay_ld_reg_0, wrcal_done_reg_0, \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 , \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 , \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 , \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 , \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 , \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 , \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 , \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 , \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 , \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 , \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 , \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 , \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 , \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 , \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 , \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 , \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 , \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 , \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 , \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 , \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 , \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 , \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 , \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 , \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 , \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 , \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 , \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 , \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 , \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 , \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 , \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 , \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 , \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 , \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 , \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 , \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 , \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 , \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 , \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 , \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 , \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 , \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 , \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 , \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 , \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 , \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 , \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 , \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 , \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 , \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 , \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 , \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 , \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 , \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 , \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 , \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 , \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 , \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 , \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 , early2_data_reg_0, early1_data_reg_0, wrcal_prech_req, wrcal_pat_resume_r_reg_0, cal2_done_r, wrcal_sanity_chk_done_reg_0, wrlvl_byte_redo, early1_data_reg_1, early2_data_reg_1, idelay_ld, phy_if_reset_w, LD0, LD0_0, LD0_1, LD0_2, \init_state_r_reg[3] , wrcal_done_reg_1, \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] , \idelay_tap_cnt_r_reg[0][2][0] , \idelay_tap_cnt_r_reg[0][2][0]_0 , \idelay_tap_cnt_r_reg[0][1][0] , \init_state_r_reg[0] , \init_state_r_reg[2] , \init_state_r_reg[4] , \init_state_r_reg[0]_0 , \init_state_r_reg[0]_1 , \init_state_r_reg[5] , \init_state_r_reg[0]_2 , \corse_cnt_reg[1][2] , \corse_cnt_reg[2][2] , done_dqs_dec239_out, \corse_cnt_reg[0][2] , \wrlvl_redo_corse_inc_reg[2] , \FSM_sequential_wl_state_r_reg[0] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] , \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \gen_byte_sel_div1.byte_sel_cnt_reg[2] , \not_empty_wait_cnt_reg[0]_0 , wrcal_pat_resume_r_reg_1, idelay_ld_done_reg_0, cal2_if_reset_reg_0, cal2_if_reset_reg_1, idelay_ld_reg_1, cal2_done_r_reg_0, wrlvl_byte_redo_reg_0, early1_data_reg_2, cal2_if_reset_reg_2, phy_rddata_en_1, CLK, \po_stg2_wrcal_cnt_reg[1]_0 , \po_stg2_wrcal_cnt_reg[1]_1 , \po_stg2_wrcal_cnt_reg[1]_2 , \po_stg2_wrcal_cnt_reg[1]_3 , wrcal_sanity_chk, p_0_out, \po_stg2_wrcal_cnt_reg[1]_4 , \po_stg2_wrcal_cnt_reg[1]_5 , \po_stg2_wrcal_cnt_reg[1]_6 , \po_stg2_wrcal_cnt_reg[1]_7 , \po_stg2_wrcal_cnt_reg[1]_8 , \po_stg2_wrcal_cnt_reg[1]_9 , \po_stg2_wrcal_cnt_reg[1]_10 , \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 , \po_stg2_wrcal_cnt_reg[1]_11 , \po_stg2_wrcal_cnt_reg[1]_12 , \po_stg2_wrcal_cnt_reg[1]_13 , \po_stg2_wrcal_cnt_reg[1]_14 , \po_stg2_wrcal_cnt_reg[1]_15 , \po_stg2_wrcal_cnt_reg[1]_16 , \po_stg2_wrcal_cnt_reg[1]_17 , \po_stg2_wrcal_cnt_reg[1]_18 , \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 , \po_stg2_wrcal_cnt_reg[1]_19 , \po_stg2_wrcal_cnt_reg[1]_20 , \po_stg2_wrcal_cnt_reg[1]_21 , \po_stg2_wrcal_cnt_reg[1]_22 , \po_stg2_wrcal_cnt_reg[1]_23 , \po_stg2_wrcal_cnt_reg[1]_24 , \po_stg2_wrcal_cnt_reg[1]_25 , \po_stg2_wrcal_cnt_reg[1]_26 , \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 , \po_stg2_wrcal_cnt_reg[1]_27 , \po_stg2_wrcal_cnt_reg[1]_28 , \po_stg2_wrcal_cnt_reg[1]_29 , \po_stg2_wrcal_cnt_reg[1]_30 , \po_stg2_wrcal_cnt_reg[1]_31 , \po_stg2_wrcal_cnt_reg[1]_32 , \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 , \po_stg2_wrcal_cnt_reg[1]_33 , \po_stg2_wrcal_cnt_reg[1]_34 , \po_stg2_wrcal_cnt_reg[1]_35 , \po_stg2_wrcal_cnt_reg[1]_36 , \po_stg2_wrcal_cnt_reg[1]_37 , \po_stg2_wrcal_cnt_reg[1]_38 , \po_stg2_wrcal_cnt_reg[1]_39 , \po_stg2_wrcal_cnt_reg[1]_40 , \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 , \po_stg2_wrcal_cnt_reg[1]_41 , \po_stg2_wrcal_cnt_reg[1]_42 , \po_stg2_wrcal_cnt_reg[1]_43 , \po_stg2_wrcal_cnt_reg[1]_44 , \po_stg2_wrcal_cnt_reg[1]_45 , \po_stg2_wrcal_cnt_reg[1]_46 , \po_stg2_wrcal_cnt_reg[1]_47 , \po_stg2_wrcal_cnt_reg[1]_48 , \po_stg2_wrcal_cnt_reg[1]_49 , \po_stg2_wrcal_cnt_reg[1]_50 , \po_stg2_wrcal_cnt_reg[1]_51 , \po_stg2_wrcal_cnt_reg[1]_52 , \po_stg2_wrcal_cnt_reg[1]_53 , \po_stg2_wrcal_cnt_reg[1]_54 , \po_stg2_wrcal_cnt_reg[1]_55 , \po_stg2_wrcal_cnt_reg[1]_56 , \po_stg2_wrcal_cnt_reg[1]_57 , \po_stg2_wrcal_cnt_reg[1]_58 , \po_stg2_wrcal_cnt_reg[1]_59 , \po_stg2_wrcal_cnt_reg[1]_60 , \po_stg2_wrcal_cnt_reg[1]_61 , \po_stg2_wrcal_cnt_reg[1]_62 , \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 , rstdiv0_sync_r1_reg_rep__6, wrlvl_byte_done, rstdiv0_sync_r1_reg_rep__4, \cal2_state_r_reg[0]_0 , \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 , wrcal_sanity_chk_r_reg_0, rstdiv0_sync_r1_reg_rep__5, \cal2_state_r_reg[3]_0 , \gen_pat_match_div4.early2_data_match_r_reg_0 , \gen_pat_match_div4.early1_data_match_r_reg_0 , rstdiv0_sync_r1_reg_rep__2, \gen_pat_match_div4.early1_data_match_r_reg_1 , \gen_pat_match_div4.pat_data_match_valid_r_reg_0 , \cal2_state_r_reg[2]_0 , \cal2_state_r_reg[0]_1 , Q, \calib_sel_reg[1] , calib_in_common, idelay_ld_rst, idelay_ld_rst_3, idelay_ld_rst_4, idelay_ld_rst_5, dqs_found_done_r_reg, rdlvl_stg1_start_int_reg, rdlvl_stg1_done_int_reg, oclkdelay_calib_done_r_reg, first_wrcal_pat_r, idelay_ce_int, oclkdelay_calib_done_r_reg_0, wrlvl_final_mux, mem_init_done_r, dqs_found_done_r_reg_0, mpr_rdlvl_done_r_reg, mpr_last_byte_done, prbs_rdlvl_done_reg_rep, prech_req_posedge_r_reg, wrcal_resume_r, wrlvl_done_r1, rdlvl_stg1_done_int_reg_0, oclkdelay_center_calib_done_r_reg, prbs_rdlvl_done_reg_rep_0, ddr3_lm_done_r, wrlvl_byte_redo_r, \final_coarse_tap_reg[3][2] , wl_sm_start, prbs_rdlvl_done_reg, \prbs_dqs_cnt_r_reg[0] , \prbs_dqs_cnt_r_reg[1] , rstdiv0_sync_r1_reg_rep__22, wrcal_rd_wait, wrcal_start_reg, prech_done, wrcal_sanity_chk_reg, phy_rddata_en_r1_reg); output rd_active_r1; output rd_active_r2; output wrcal_pat_resume_r; output wrcal_resume_w; output idelay_ld_reg_0; output wrcal_done_reg_0; output \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ; output \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ; output \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ; output \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ; output \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ; output \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ; output \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ; output \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ; output \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ; output \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ; output \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ; output \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ; output \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ; output \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ; output \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ; output \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ; output \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ; output \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ; output \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ; output \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ; output \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ; output \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ; output \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ; output \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ; output \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ; output \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ; output \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ; output \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ; output \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ; output \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ; output \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ; output \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ; output \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ; output \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ; output \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ; output \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ; output \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ; output \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ; output \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ; output \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ; output \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ; output \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ; output \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ; output \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ; output \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ; output \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ; output \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ; output \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ; output \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ; output \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ; output \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ; output \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ; output \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ; output \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ; output \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ; output \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ; output \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ; output \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ; output \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ; output \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ; output early2_data_reg_0; output early1_data_reg_0; output wrcal_prech_req; output wrcal_pat_resume_r_reg_0; output cal2_done_r; output wrcal_sanity_chk_done_reg_0; output wrlvl_byte_redo; output early1_data_reg_1; output early2_data_reg_1; output idelay_ld; output phy_if_reset_w; output LD0; output LD0_0; output LD0_1; output LD0_2; output \init_state_r_reg[3] ; output wrcal_done_reg_1; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; output \idelay_tap_cnt_r_reg[0][2][0] ; output [2:0]\idelay_tap_cnt_r_reg[0][2][0]_0 ; output \idelay_tap_cnt_r_reg[0][1][0] ; output \init_state_r_reg[0] ; output \init_state_r_reg[2] ; output \init_state_r_reg[4] ; output \init_state_r_reg[0]_0 ; output \init_state_r_reg[0]_1 ; output \init_state_r_reg[5] ; output \init_state_r_reg[0]_2 ; output \corse_cnt_reg[1][2] ; output \corse_cnt_reg[2][2] ; output done_dqs_dec239_out; output \corse_cnt_reg[0][2] ; output \wrlvl_redo_corse_inc_reg[2] ; output \FSM_sequential_wl_state_r_reg[0] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; output [3:0]\not_empty_wait_cnt_reg[0]_0 ; output wrcal_pat_resume_r_reg_1; output idelay_ld_done_reg_0; output cal2_if_reset_reg_0; output cal2_if_reset_reg_1; output idelay_ld_reg_1; output cal2_done_r_reg_0; output wrlvl_byte_redo_reg_0; output early1_data_reg_2; output cal2_if_reset_reg_2; input phy_rddata_en_1; input CLK; input \po_stg2_wrcal_cnt_reg[1]_0 ; input \po_stg2_wrcal_cnt_reg[1]_1 ; input \po_stg2_wrcal_cnt_reg[1]_2 ; input \po_stg2_wrcal_cnt_reg[1]_3 ; input wrcal_sanity_chk; input p_0_out; input \po_stg2_wrcal_cnt_reg[1]_4 ; input \po_stg2_wrcal_cnt_reg[1]_5 ; input \po_stg2_wrcal_cnt_reg[1]_6 ; input \po_stg2_wrcal_cnt_reg[1]_7 ; input \po_stg2_wrcal_cnt_reg[1]_8 ; input \po_stg2_wrcal_cnt_reg[1]_9 ; input \po_stg2_wrcal_cnt_reg[1]_10 ; input \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_11 ; input \po_stg2_wrcal_cnt_reg[1]_12 ; input \po_stg2_wrcal_cnt_reg[1]_13 ; input \po_stg2_wrcal_cnt_reg[1]_14 ; input \po_stg2_wrcal_cnt_reg[1]_15 ; input \po_stg2_wrcal_cnt_reg[1]_16 ; input \po_stg2_wrcal_cnt_reg[1]_17 ; input \po_stg2_wrcal_cnt_reg[1]_18 ; input \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_19 ; input \po_stg2_wrcal_cnt_reg[1]_20 ; input \po_stg2_wrcal_cnt_reg[1]_21 ; input \po_stg2_wrcal_cnt_reg[1]_22 ; input \po_stg2_wrcal_cnt_reg[1]_23 ; input \po_stg2_wrcal_cnt_reg[1]_24 ; input \po_stg2_wrcal_cnt_reg[1]_25 ; input \po_stg2_wrcal_cnt_reg[1]_26 ; input \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_27 ; input \po_stg2_wrcal_cnt_reg[1]_28 ; input \po_stg2_wrcal_cnt_reg[1]_29 ; input \po_stg2_wrcal_cnt_reg[1]_30 ; input \po_stg2_wrcal_cnt_reg[1]_31 ; input \po_stg2_wrcal_cnt_reg[1]_32 ; input \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_33 ; input \po_stg2_wrcal_cnt_reg[1]_34 ; input \po_stg2_wrcal_cnt_reg[1]_35 ; input \po_stg2_wrcal_cnt_reg[1]_36 ; input \po_stg2_wrcal_cnt_reg[1]_37 ; input \po_stg2_wrcal_cnt_reg[1]_38 ; input \po_stg2_wrcal_cnt_reg[1]_39 ; input \po_stg2_wrcal_cnt_reg[1]_40 ; input \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_41 ; input \po_stg2_wrcal_cnt_reg[1]_42 ; input \po_stg2_wrcal_cnt_reg[1]_43 ; input \po_stg2_wrcal_cnt_reg[1]_44 ; input \po_stg2_wrcal_cnt_reg[1]_45 ; input \po_stg2_wrcal_cnt_reg[1]_46 ; input \po_stg2_wrcal_cnt_reg[1]_47 ; input \po_stg2_wrcal_cnt_reg[1]_48 ; input \po_stg2_wrcal_cnt_reg[1]_49 ; input \po_stg2_wrcal_cnt_reg[1]_50 ; input \po_stg2_wrcal_cnt_reg[1]_51 ; input \po_stg2_wrcal_cnt_reg[1]_52 ; input \po_stg2_wrcal_cnt_reg[1]_53 ; input \po_stg2_wrcal_cnt_reg[1]_54 ; input \po_stg2_wrcal_cnt_reg[1]_55 ; input \po_stg2_wrcal_cnt_reg[1]_56 ; input \po_stg2_wrcal_cnt_reg[1]_57 ; input \po_stg2_wrcal_cnt_reg[1]_58 ; input \po_stg2_wrcal_cnt_reg[1]_59 ; input \po_stg2_wrcal_cnt_reg[1]_60 ; input \po_stg2_wrcal_cnt_reg[1]_61 ; input \po_stg2_wrcal_cnt_reg[1]_62 ; input \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ; input rstdiv0_sync_r1_reg_rep__6; input wrlvl_byte_done; input [0:0]rstdiv0_sync_r1_reg_rep__4; input \cal2_state_r_reg[0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ; input wrcal_sanity_chk_r_reg_0; input rstdiv0_sync_r1_reg_rep__5; input \cal2_state_r_reg[3]_0 ; input \gen_pat_match_div4.early2_data_match_r_reg_0 ; input \gen_pat_match_div4.early1_data_match_r_reg_0 ; input rstdiv0_sync_r1_reg_rep__2; input \gen_pat_match_div4.early1_data_match_r_reg_1 ; input \gen_pat_match_div4.pat_data_match_valid_r_reg_0 ; input \cal2_state_r_reg[2]_0 ; input \cal2_state_r_reg[0]_1 ; input [0:0]Q; input [1:0]\calib_sel_reg[1] ; input calib_in_common; input idelay_ld_rst; input idelay_ld_rst_3; input idelay_ld_rst_4; input idelay_ld_rst_5; input dqs_found_done_r_reg; input rdlvl_stg1_start_int_reg; input rdlvl_stg1_done_int_reg; input oclkdelay_calib_done_r_reg; input first_wrcal_pat_r; input idelay_ce_int; input oclkdelay_calib_done_r_reg_0; input wrlvl_final_mux; input mem_init_done_r; input dqs_found_done_r_reg_0; input mpr_rdlvl_done_r_reg; input mpr_last_byte_done; input prbs_rdlvl_done_reg_rep; input prech_req_posedge_r_reg; input wrcal_resume_r; input wrlvl_done_r1; input rdlvl_stg1_done_int_reg_0; input oclkdelay_center_calib_done_r_reg; input prbs_rdlvl_done_reg_rep_0; input ddr3_lm_done_r; input wrlvl_byte_redo_r; input [1:0]\final_coarse_tap_reg[3][2] ; input wl_sm_start; input prbs_rdlvl_done_reg; input \prbs_dqs_cnt_r_reg[0] ; input \prbs_dqs_cnt_r_reg[1] ; input rstdiv0_sync_r1_reg_rep__22; input wrcal_rd_wait; input wrcal_start_reg; input prech_done; input wrcal_sanity_chk_reg; input phy_rddata_en_r1_reg; wire CLK; wire \FSM_sequential_wl_state_r_reg[0] ; wire LD0; wire LD0_0; wire LD0_1; wire LD0_2; wire [0:0]Q; wire cal2_done_r; wire cal2_done_r_reg_0; wire cal2_if_reset_i_5_n_0; wire cal2_if_reset_reg_0; wire cal2_if_reset_reg_1; wire cal2_if_reset_reg_2; wire cal2_prech_req_r; wire cal2_prech_req_r_i_2_n_0; wire cal2_prech_req_r_i_3_n_0; wire cal2_state_r; wire \cal2_state_r[0]_i_1_n_0 ; wire \cal2_state_r[0]_i_2_n_0 ; wire \cal2_state_r[0]_i_3_n_0 ; wire \cal2_state_r[0]_i_4_n_0 ; wire \cal2_state_r[0]_i_5_n_0 ; wire \cal2_state_r[1]_i_1_n_0 ; wire \cal2_state_r[1]_i_2_n_0 ; wire \cal2_state_r[1]_i_3_n_0 ; wire \cal2_state_r[2]_i_1_n_0 ; wire \cal2_state_r[2]_i_2_n_0 ; wire \cal2_state_r[2]_i_3_n_0 ; wire \cal2_state_r[3]_i_11_n_0 ; wire \cal2_state_r[3]_i_3_n_0 ; wire \cal2_state_r[3]_i_4_n_0 ; wire \cal2_state_r[3]_i_5_n_0 ; wire \cal2_state_r[3]_i_6_n_0 ; wire \cal2_state_r[3]_i_7_n_0 ; wire \cal2_state_r[3]_i_8_n_0 ; wire \cal2_state_r[3]_i_9_n_0 ; wire \cal2_state_r_reg[0]_0 ; wire \cal2_state_r_reg[0]_1 ; wire \cal2_state_r_reg[2]_0 ; wire \cal2_state_r_reg[3]_0 ; wire calib_in_common; wire [1:0]\calib_sel_reg[1] ; wire \corse_cnt_reg[0][2] ; wire \corse_cnt_reg[1][2] ; wire \corse_cnt_reg[2][2] ; wire ddr3_lm_done_r; wire done_dqs_dec239_out; wire dqs_found_done_r_reg; wire dqs_found_done_r_reg_0; wire early1_data_i_3_n_0; wire early1_data_match_r0__0; wire early1_data_reg_0; wire early1_data_reg_1; wire early1_data_reg_2; wire early1_match_fall0_and_r; wire early1_match_fall1_and_r; wire early1_match_fall2_and_r; wire early1_match_fall3_and_r; wire early1_match_rise0_and_r; wire early1_match_rise1_and_r; wire early1_match_rise2_and_r; wire early1_match_rise3_and_r; wire early2_data_match_r0__0; wire early2_data_reg_0; wire early2_data_reg_1; wire early2_match_fall0_and_r; wire early2_match_fall1_and_r; wire early2_match_fall2_and_r; wire early2_match_fall3_and_r; wire early2_match_rise0_and_r; wire early2_match_rise1_and_r; wire early2_match_rise2_and_r; wire early2_match_rise3_and_r; wire [1:0]\final_coarse_tap_reg[3][2] ; wire first_wrcal_pat_r; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ; wire \gen_pat_match_div4.early1_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_data_match_r_reg_0 ; wire \gen_pat_match_div4.early1_data_match_r_reg_1 ; wire \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_data_match_r_reg_0 ; wire \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.pat_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.pat_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.pat_data_match_valid_r_reg_0 ; wire \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ; wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ; wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ; wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ; wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ; wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ; wire \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ; wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ; wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ; wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ; wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ; wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ; wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ; wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ; wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ; wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ; wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ; wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ; wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ; wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ; wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ; wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ; wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ; wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ; wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ; wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ; wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ; wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ; wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ; wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ; wire \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ; wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ; wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ; wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ; wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ; wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ; wire \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ; wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ; wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ; wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ; wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ; wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ; wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ; wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ; wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ; wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ; wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ; wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ; wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ; wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ; wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ; wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ; wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ; wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ; wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ; wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ; wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ; wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ; wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ; wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ; wire \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ; wire idelay_ce_int; wire idelay_ld; wire idelay_ld_done_reg_0; wire idelay_ld_reg_0; wire idelay_ld_reg_1; wire idelay_ld_rst; wire idelay_ld_rst_3; wire idelay_ld_rst_4; wire idelay_ld_rst_5; wire \idelay_tap_cnt_r_reg[0][1][0] ; wire \idelay_tap_cnt_r_reg[0][2][0] ; wire [2:0]\idelay_tap_cnt_r_reg[0][2][0]_0 ; wire \init_state_r[0]_i_56_n_0 ; wire \init_state_r[4]_i_34_n_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[0]_2 ; wire \init_state_r_reg[2] ; wire \init_state_r_reg[3] ; wire \init_state_r_reg[4] ; wire \init_state_r_reg[5] ; wire mem_init_done_r; wire mpr_last_byte_done; wire mpr_rdlvl_done_r_reg; wire \not_empty_wait_cnt[4]_i_1_n_0 ; wire [3:0]\not_empty_wait_cnt_reg[0]_0 ; wire \not_empty_wait_cnt_reg_n_0_[0] ; wire \not_empty_wait_cnt_reg_n_0_[1] ; wire \not_empty_wait_cnt_reg_n_0_[2] ; wire \not_empty_wait_cnt_reg_n_0_[3] ; wire \not_empty_wait_cnt_reg_n_0_[4] ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_center_calib_done_r_reg; wire [4:0]p_0_in; wire [3:0]p_0_in__0; wire p_0_out; wire pat_data_match_r0__0; wire pat_match_fall0_and_r; wire pat_match_fall1_and_r; wire pat_match_fall2_and_r; wire pat_match_fall3_and_r; wire pat_match_rise0_and_r; wire pat_match_rise1_and_r; wire pat_match_rise2_and_r; wire pat_match_rise3_and_r; wire phy_if_reset_w; wire phy_rddata_en_1; wire phy_rddata_en_r1_reg; wire \po_stg2_wrcal_cnt_reg[1]_0 ; wire \po_stg2_wrcal_cnt_reg[1]_1 ; wire \po_stg2_wrcal_cnt_reg[1]_10 ; wire \po_stg2_wrcal_cnt_reg[1]_11 ; wire \po_stg2_wrcal_cnt_reg[1]_12 ; wire \po_stg2_wrcal_cnt_reg[1]_13 ; wire \po_stg2_wrcal_cnt_reg[1]_14 ; wire \po_stg2_wrcal_cnt_reg[1]_15 ; wire \po_stg2_wrcal_cnt_reg[1]_16 ; wire \po_stg2_wrcal_cnt_reg[1]_17 ; wire \po_stg2_wrcal_cnt_reg[1]_18 ; wire \po_stg2_wrcal_cnt_reg[1]_19 ; wire \po_stg2_wrcal_cnt_reg[1]_2 ; wire \po_stg2_wrcal_cnt_reg[1]_20 ; wire \po_stg2_wrcal_cnt_reg[1]_21 ; wire \po_stg2_wrcal_cnt_reg[1]_22 ; wire \po_stg2_wrcal_cnt_reg[1]_23 ; wire \po_stg2_wrcal_cnt_reg[1]_24 ; wire \po_stg2_wrcal_cnt_reg[1]_25 ; wire \po_stg2_wrcal_cnt_reg[1]_26 ; wire \po_stg2_wrcal_cnt_reg[1]_27 ; wire \po_stg2_wrcal_cnt_reg[1]_28 ; wire \po_stg2_wrcal_cnt_reg[1]_29 ; wire \po_stg2_wrcal_cnt_reg[1]_3 ; wire \po_stg2_wrcal_cnt_reg[1]_30 ; wire \po_stg2_wrcal_cnt_reg[1]_31 ; wire \po_stg2_wrcal_cnt_reg[1]_32 ; wire \po_stg2_wrcal_cnt_reg[1]_33 ; wire \po_stg2_wrcal_cnt_reg[1]_34 ; wire \po_stg2_wrcal_cnt_reg[1]_35 ; wire \po_stg2_wrcal_cnt_reg[1]_36 ; wire \po_stg2_wrcal_cnt_reg[1]_37 ; wire \po_stg2_wrcal_cnt_reg[1]_38 ; wire \po_stg2_wrcal_cnt_reg[1]_39 ; wire \po_stg2_wrcal_cnt_reg[1]_4 ; wire \po_stg2_wrcal_cnt_reg[1]_40 ; wire \po_stg2_wrcal_cnt_reg[1]_41 ; wire \po_stg2_wrcal_cnt_reg[1]_42 ; wire \po_stg2_wrcal_cnt_reg[1]_43 ; wire \po_stg2_wrcal_cnt_reg[1]_44 ; wire \po_stg2_wrcal_cnt_reg[1]_45 ; wire \po_stg2_wrcal_cnt_reg[1]_46 ; wire \po_stg2_wrcal_cnt_reg[1]_47 ; wire \po_stg2_wrcal_cnt_reg[1]_48 ; wire \po_stg2_wrcal_cnt_reg[1]_49 ; wire \po_stg2_wrcal_cnt_reg[1]_5 ; wire \po_stg2_wrcal_cnt_reg[1]_50 ; wire \po_stg2_wrcal_cnt_reg[1]_51 ; wire \po_stg2_wrcal_cnt_reg[1]_52 ; wire \po_stg2_wrcal_cnt_reg[1]_53 ; wire \po_stg2_wrcal_cnt_reg[1]_54 ; wire \po_stg2_wrcal_cnt_reg[1]_55 ; wire \po_stg2_wrcal_cnt_reg[1]_56 ; wire \po_stg2_wrcal_cnt_reg[1]_57 ; wire \po_stg2_wrcal_cnt_reg[1]_58 ; wire \po_stg2_wrcal_cnt_reg[1]_59 ; wire \po_stg2_wrcal_cnt_reg[1]_6 ; wire \po_stg2_wrcal_cnt_reg[1]_60 ; wire \po_stg2_wrcal_cnt_reg[1]_61 ; wire \po_stg2_wrcal_cnt_reg[1]_62 ; wire \po_stg2_wrcal_cnt_reg[1]_7 ; wire \po_stg2_wrcal_cnt_reg[1]_8 ; wire \po_stg2_wrcal_cnt_reg[1]_9 ; wire \prbs_dqs_cnt_r_reg[0] ; wire \prbs_dqs_cnt_r_reg[1] ; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prbs_rdlvl_done_reg_rep_0; wire prech_done; wire prech_req_posedge_r_reg; wire rd_active_r1; wire rd_active_r2; wire rd_active_r3; wire rdlvl_stg1_done_int_reg; wire rdlvl_stg1_done_int_reg_0; wire rdlvl_stg1_start_int_reg; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__22; wire [0:0]rstdiv0_sync_r1_reg_rep__4; wire rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire \tap_inc_wait_cnt[3]_i_1_n_0 ; wire [3:0]tap_inc_wait_cnt_reg__0; wire wl_sm_start; wire wrcal_done_i_1_n_0; wire wrcal_done_reg_0; wire wrcal_done_reg_1; wire [2:2]wrcal_dqs_cnt_r; wire \wrcal_dqs_cnt_r[0]_i_1_n_0 ; wire \wrcal_dqs_cnt_r[1]_i_1_n_0 ; wire \wrcal_dqs_cnt_r[2]_i_1_n_0 ; wire \wrcal_dqs_cnt_r[2]_i_2_n_0 ; wire \wrcal_dqs_cnt_r[2]_i_3_n_0 ; wire \wrcal_dqs_cnt_r_reg_n_0_[0] ; wire \wrcal_dqs_cnt_r_reg_n_0_[1] ; wire wrcal_pat_resume_r; wire wrcal_pat_resume_r2_reg_srl2_n_0; wire wrcal_pat_resume_r_i_3_n_0; wire wrcal_pat_resume_r_reg_0; wire wrcal_pat_resume_r_reg_1; wire wrcal_prech_req; wire wrcal_rd_wait; wire wrcal_resume_r; wire wrcal_resume_w; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done_reg_0; wire wrcal_sanity_chk_r_reg_0; wire wrcal_sanity_chk_reg; wire wrcal_start_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; wire wrlvl_byte_done; wire wrlvl_byte_done_r; wire wrlvl_byte_redo; wire wrlvl_byte_redo_i_3_n_0; wire wrlvl_byte_redo_r; wire wrlvl_byte_redo_reg_0; wire wrlvl_done_r1; wire wrlvl_final_mux; wire \wrlvl_redo_corse_inc_reg[2] ; (* SOFT_HLUTNM = "soft_lutpair632" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_wl_state_r[4]_i_13 (.I0(wrlvl_byte_redo), .I1(wl_sm_start), .O(\FSM_sequential_wl_state_r_reg[0] )); LUT4 #( .INIT(16'hDD45)) \FSM_sequential_wl_state_r[4]_i_6 (.I0(early1_data_reg_1), .I1(\final_coarse_tap_reg[3][2] [0]), .I2(early2_data_reg_1), .I3(\final_coarse_tap_reg[3][2] [1]), .O(\wrlvl_redo_corse_inc_reg[2] )); LUT4 #( .INIT(16'h0040)) cal2_done_r_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(\not_empty_wait_cnt_reg[0]_0 [0]), .O(cal2_done_r_reg_0)); FDRE #( .INIT(1'b0)) cal2_done_r_reg (.C(CLK), .CE(1'b1), .D(wrcal_sanity_chk_r_reg_0), .Q(cal2_done_r), .R(rstdiv0_sync_r1_reg_rep__6)); LUT6 #( .INIT(64'h004F0040F000F000)) cal2_if_reset_i_2 (.I0(phy_rddata_en_1), .I1(rd_active_r1), .I2(\not_empty_wait_cnt_reg[0]_0 [0]), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(wrcal_done_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [1]), .O(cal2_if_reset_reg_2)); LUT6 #( .INIT(64'h00FF000008FF08FF)) cal2_if_reset_i_3 (.I0(wrlvl_byte_done), .I1(rd_active_r1), .I2(phy_rddata_en_1), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(idelay_ld_done_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [2]), .O(cal2_if_reset_reg_1)); LUT6 #( .INIT(64'hFF80FFFFFF800000)) cal2_if_reset_i_4 (.I0(prech_done), .I1(cal2_prech_req_r_i_3_n_0), .I2(wrcal_done_reg_0), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(cal2_if_reset_i_5_n_0), .O(cal2_if_reset_reg_0)); LUT6 #( .INIT(64'h8000FFFF80000000)) cal2_if_reset_i_5 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(tap_inc_wait_cnt_reg__0[3]), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .I5(wrcal_start_reg), .O(cal2_if_reset_i_5_n_0)); FDRE #( .INIT(1'b0)) cal2_if_reset_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[0]_1 ), .Q(phy_if_reset_w), .R(rstdiv0_sync_r1_reg_rep__5)); LUT6 #( .INIT(64'h0000000010110000)) cal2_prech_req_r_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(cal2_prech_req_r_i_3_n_0), .I3(wrcal_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(\not_empty_wait_cnt_reg[0]_0 [0]), .O(cal2_prech_req_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair631" *) LUT3 #( .INIT(8'h08)) cal2_prech_req_r_i_3 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I2(wrcal_dqs_cnt_r), .O(cal2_prech_req_r_i_3_n_0)); FDRE #( .INIT(1'b0)) cal2_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(cal2_prech_req_r_i_2_n_0), .Q(cal2_prech_req_r), .R(rstdiv0_sync_r1_reg_rep__6)); LUT6 #( .INIT(64'h00000000E2FFE200)) \cal2_state_r[0]_i_1 (.I0(\cal2_state_r[0]_i_2_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\not_empty_wait_cnt_reg[0]_0 [0]), .I4(\cal2_state_r[0]_i_3_n_0 ), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(\cal2_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hBBB8BBBB88888888)) \cal2_state_r[0]_i_2 (.I0(tap_inc_wait_cnt_reg__0[0]), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(early2_data_reg_0), .I3(early1_data_reg_0), .I4(wrcal_pat_resume_r_reg_0), .I5(\cal2_state_r[0]_i_4_n_0 ), .O(\cal2_state_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'h000F0000DFDFDFDF)) \cal2_state_r[0]_i_3 (.I0(prech_done), .I1(\cal2_state_r[0]_i_5_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrcal_done_reg_0), .I4(wrcal_pat_resume_r_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [2]), .O(\cal2_state_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair615" *) LUT3 #( .INIT(8'h04)) \cal2_state_r[0]_i_4 (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I1(idelay_ld_reg_0), .I2(wrcal_done_reg_0), .O(\cal2_state_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair614" *) LUT3 #( .INIT(8'hF7)) \cal2_state_r[0]_i_5 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I2(wrcal_dqs_cnt_r), .O(\cal2_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \cal2_state_r[1]_i_1 (.I0(\cal2_state_r[1]_i_2_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(\cal2_state_r[1]_i_3_n_0 ), .O(\cal2_state_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair615" *) LUT5 #( .INIT(32'hFF003200)) \cal2_state_r[1]_i_2 (.I0(early2_data_reg_0), .I1(wrcal_done_reg_0), .I2(early1_data_reg_0), .I3(idelay_ld_reg_0), .I4(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .O(\cal2_state_r[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair616" *) LUT5 #( .INIT(32'h0F0050D0)) \cal2_state_r[1]_i_3 (.I0(prech_done), .I1(cal2_prech_req_r_i_3_n_0), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrcal_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .O(\cal2_state_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'h4F4AFFFF4F4A0000)) \cal2_state_r[2]_i_1 (.I0(\not_empty_wait_cnt_reg[0]_0 [1]), .I1(tap_inc_wait_cnt_reg__0[2]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\cal2_state_r[2]_i_2_n_0 ), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(\cal2_state_r[2]_i_3_n_0 ), .O(\cal2_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000010)) \cal2_state_r[2]_i_2 (.I0(early2_data_reg_0), .I1(wrcal_done_reg_0), .I2(idelay_ld_reg_0), .I3(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I4(early1_data_reg_0), .I5(wrcal_pat_resume_r_reg_0), .O(\cal2_state_r[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair616" *) LUT5 #( .INIT(32'h0F00D0D0)) \cal2_state_r[2]_i_3 (.I0(prech_done), .I1(cal2_prech_req_r_i_3_n_0), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrcal_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .O(\cal2_state_r[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair612" *) LUT4 #( .INIT(16'h8000)) \cal2_state_r[3]_i_11 (.I0(\not_empty_wait_cnt_reg_n_0_[2] ), .I1(\not_empty_wait_cnt_reg_n_0_[1] ), .I2(\not_empty_wait_cnt_reg_n_0_[0] ), .I3(\not_empty_wait_cnt_reg_n_0_[3] ), .O(\cal2_state_r[3]_i_11_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \cal2_state_r[3]_i_3 (.I0(\cal2_state_r[3]_i_6_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(tap_inc_wait_cnt_reg__0[3]), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(\cal2_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h45404F4F45404A4A)) \cal2_state_r[3]_i_4 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\cal2_state_r[3]_i_7_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(\cal2_state_r[3]_i_8_n_0 ), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .I5(wrcal_start_reg), .O(\cal2_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000EEE222E2)) \cal2_state_r[3]_i_5 (.I0(\cal2_state_r[3]_i_9_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(phy_rddata_en_r1_reg), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(\cal2_state_r[3]_i_8_n_0 ), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(\cal2_state_r[3]_i_5_n_0 )); LUT6 #( .INIT(64'h00FF0010FFFFFFFF)) \cal2_state_r[3]_i_6 (.I0(early2_data_reg_0), .I1(early1_data_reg_0), .I2(wrcal_pat_resume_r_reg_0), .I3(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I4(wrcal_done_reg_0), .I5(idelay_ld_reg_0), .O(\cal2_state_r[3]_i_6_n_0 )); LUT5 #( .INIT(32'h3B3B3808)) \cal2_state_r[3]_i_7 (.I0(wrcal_sanity_chk), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(wrcal_done_reg_0), .I3(\cal2_state_r[0]_i_5_n_0 ), .I4(prech_done), .O(\cal2_state_r[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair627" *) LUT4 #( .INIT(16'h8000)) \cal2_state_r[3]_i_8 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(tap_inc_wait_cnt_reg__0[3]), .O(\cal2_state_r[3]_i_8_n_0 )); LUT5 #( .INIT(32'hBBBBB888)) \cal2_state_r[3]_i_9 (.I0(idelay_ld_done_reg_0), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(\cal2_state_r[3]_i_11_n_0 ), .I3(\not_empty_wait_cnt_reg_n_0_[4] ), .I4(idelay_ld_reg_0), .O(\cal2_state_r[3]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \cal2_state_r_reg[0] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[0]_i_1_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \cal2_state_r_reg[1] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[1]_i_1_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \cal2_state_r_reg[2] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[2]_i_1_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE #( .INIT(1'b0)) \cal2_state_r_reg[3] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[3]_i_3_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [3]), .R(rstdiv0_sync_r1_reg_rep__4)); MUXF7 \cal2_state_r_reg[3]_i_2 (.I0(\cal2_state_r[3]_i_4_n_0 ), .I1(\cal2_state_r[3]_i_5_n_0 ), .O(cal2_state_r), .S(\not_empty_wait_cnt_reg[0]_0 [0])); LUT2 #( .INIT(4'h1)) \corse_cnt[0][2]_i_11 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .I1(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .O(\corse_cnt_reg[0][2] )); (* SOFT_HLUTNM = "soft_lutpair622" *) LUT4 #( .INIT(16'hFBFF)) \corse_cnt[1][2]_i_5 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .I1(wrlvl_byte_redo), .I2(wrlvl_byte_redo_r), .I3(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .O(\corse_cnt_reg[1][2] )); (* SOFT_HLUTNM = "soft_lutpair632" *) LUT3 #( .INIT(8'hDF)) \corse_cnt[2][2]_i_5 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [1]), .I1(wrlvl_byte_redo_r), .I2(wrlvl_byte_redo), .O(\corse_cnt_reg[2][2] )); LUT5 #( .INIT(32'h45400000)) early1_data_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(early1_data_i_3_n_0), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrlvl_byte_redo_i_3_n_0), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .O(early1_data_reg_2)); LUT4 #( .INIT(16'h0008)) early1_data_i_3 (.I0(wrlvl_byte_done), .I1(rd_active_r1), .I2(phy_rddata_en_1), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .O(early1_data_i_3_n_0)); FDRE #( .INIT(1'b0)) early1_data_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_data_match_r_reg_0 ), .Q(early1_data_reg_1), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) early2_data_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_data_match_r_reg_1 ), .Q(early2_data_reg_1), .R(rstdiv0_sync_r1_reg_rep__2)); LUT6 #( .INIT(64'h0CAA000000AA0000)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_3 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg), .I3(wrcal_done_reg_1), .I4(oclkdelay_calib_done_r_reg), .I5(\prbs_dqs_cnt_r_reg[0] ), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'h0CAA000000AA0000)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_3 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [1]), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg), .I3(wrcal_done_reg_1), .I4(oclkdelay_calib_done_r_reg), .I5(\prbs_dqs_cnt_r_reg[1] ), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair629" *) LUT4 #( .INIT(16'h0800)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_6 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .I1(mpr_rdlvl_done_r_reg), .I2(wrcal_done_reg_1), .I3(oclkdelay_calib_done_r_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_19 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_55 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_33 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_11 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_47 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_out), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_41 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_20 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_56 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_34 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_12 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_48 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_4 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_27 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_42 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_21 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_57 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_35 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_13 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_49 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_5 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_28 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_43 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_22 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_58 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_36 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_14 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_50 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_6 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_29 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_23 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_59 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_37 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_15 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_51 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_7 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_44 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_24 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_60 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_38 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_16 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_52 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_8 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_30 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_45 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_25 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_61 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_39 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_17 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_53 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_9 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_31 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_46 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_26 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_62 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_40 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_18 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_54 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_10 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_32 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early1_data_match_r_i_1 (.I0(early1_match_rise2_and_r), .I1(early1_match_rise3_and_r), .I2(early1_match_fall1_and_r), .I3(early1_match_rise1_and_r), .I4(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ), .O(early1_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early1_data_match_r_i_2 (.I0(early1_match_rise0_and_r), .I1(early1_match_fall3_and_r), .I2(early1_match_fall0_and_r), .I3(early1_match_fall2_and_r), .O(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_data_match_r_reg (.C(CLK), .CE(1'b1), .D(early1_data_match_r0__0), .Q(early1_data_reg_0), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early1_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ), .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early1_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ), .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ), .Q(early1_match_fall0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ), .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair613" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ), .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ), .Q(early1_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ), .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ), .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ), .Q(early1_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ), .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair619" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ), .Q(early1_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early1_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ), .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early1_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ), .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ), .Q(early1_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ), .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair621" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ), .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ), .Q(early1_match_rise1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair617" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ), .I4(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ), .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ), .Q(early1_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ), .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ), .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early1_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ), .Q(early1_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early2_data_match_r_i_1 (.I0(early2_match_fall0_and_r), .I1(early2_match_rise2_and_r), .I2(early2_match_fall3_and_r), .I3(early2_match_rise1_and_r), .I4(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ), .O(early2_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early2_data_match_r_i_2 (.I0(early2_match_rise3_and_r), .I1(early2_match_fall2_and_r), .I2(early2_match_fall1_and_r), .I3(early2_match_rise0_and_r), .O(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_data_match_r_reg (.C(CLK), .CE(1'b1), .D(early2_data_match_r0__0), .Q(early2_data_reg_0), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ), .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair618" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ), .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ), .Q(early2_match_fall0_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair613" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ), .I4(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ), .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ), .Q(early2_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early2_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ), .I4(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early2_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ), .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ), .Q(early2_match_fall2_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair619" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ), .I4(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ), .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ), .Q(early2_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ), .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair611" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ), .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ), .Q(early2_match_rise0_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair621" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ), .I4(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ), .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ), .Q(early2_match_rise1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ), .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair617" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ), .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ), .Q(early2_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early2_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ), .I4(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early2_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ), .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.early2_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ), .Q(early2_match_rise3_and_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat_data_match_r_i_1 (.I0(pat_match_rise0_and_r), .I1(pat_match_rise3_and_r), .I2(pat_match_fall2_and_r), .I3(pat_match_fall3_and_r), .I4(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ), .O(pat_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat_data_match_r_i_2 (.I0(pat_match_fall0_and_r), .I1(pat_match_rise2_and_r), .I2(pat_match_rise1_and_r), .I3(pat_match_fall1_and_r), .O(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_data_match_r_reg (.C(CLK), .CE(1'b1), .D(pat_data_match_r0__0), .Q(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_data_match_valid_r_reg (.C(CLK), .CE(1'b1), .D(rd_active_r3), .Q(idelay_ld_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair618" *) LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ), .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ), .Q(pat_match_fall0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ), .Q(pat_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ), .O(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ), .Q(pat_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ), .Q(pat_match_fall3_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair611" *) LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ), .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ), .Q(pat_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ), .O(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ), .Q(pat_match_rise1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ), .O(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ), .Q(pat_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ), .O(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gen_pat_match_div4.pat_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ), .Q(pat_match_rise3_and_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 " *) SRL16E #( .INIT(16'h0000)) \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_0 ), .Q(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 " *) SRL16E #( .INIT(16'h0000)) \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_2 ), .Q(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 " *) SRL16E #( .INIT(16'h0000)) \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_1 ), .Q(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 )); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 " *) SRL16E #( .INIT(16'h0000)) \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_3 ), .Q(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair625" *) LUT4 #( .INIT(16'h0002)) idelay_ld_done_i_2 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(tap_inc_wait_cnt_reg__0[3]), .O(idelay_ld_done_reg_0)); FDRE #( .INIT(1'b0)) idelay_ld_done_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[0]_0 ), .Q(wrcal_pat_resume_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__4)); LUT6 #( .INIT(64'h0000540400000000)) idelay_ld_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\cal2_state_r[2]_i_2_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(idelay_ld_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(\not_empty_wait_cnt_reg[0]_0 [0]), .O(idelay_ld_reg_1)); FDRE #( .INIT(1'b0)) idelay_ld_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ), .Q(idelay_ld), .R(rstdiv0_sync_r1_reg_rep__5)); (* SOFT_HLUTNM = "soft_lutpair624" *) LUT4 #( .INIT(16'hFFEF)) \idelay_tap_cnt_r[0][0][4]_i_3 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .I1(idelay_ce_int), .I2(idelay_ld), .I3(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .O(\idelay_tap_cnt_r_reg[0][2][0] )); (* SOFT_HLUTNM = "soft_lutpair624" *) LUT4 #( .INIT(16'hFBFF)) \idelay_tap_cnt_r[0][1][4]_i_2 (.I0(idelay_ce_int), .I1(idelay_ld), .I2(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .I3(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .O(\idelay_tap_cnt_r_reg[0][1][0] )); LUT6 #( .INIT(64'h5555555545555555)) \init_state_r[0]_i_12 (.I0(wrcal_sanity_chk_done_reg_0), .I1(prbs_rdlvl_done_reg_rep_0), .I2(wrlvl_done_r1), .I3(dqs_found_done_r_reg), .I4(wrcal_done_reg_1), .I5(ddr3_lm_done_r), .O(\init_state_r_reg[0]_2 )); LUT6 #( .INIT(64'h5700575757575757)) \init_state_r[0]_i_36 (.I0(oclkdelay_calib_done_r_reg_0), .I1(wrlvl_final_mux), .I2(wrlvl_byte_redo), .I3(mem_init_done_r), .I4(\init_state_r_reg[2] ), .I5(dqs_found_done_r_reg_0), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h00D000D000D0FFFF)) \init_state_r[0]_i_55 (.I0(prbs_rdlvl_done_reg_rep), .I1(\init_state_r[0]_i_56_n_0 ), .I2(wrlvl_done_r1), .I3(wrlvl_byte_redo), .I4(rdlvl_stg1_done_int_reg_0), .I5(dqs_found_done_r_reg), .O(\init_state_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair623" *) LUT2 #( .INIT(4'h7)) \init_state_r[0]_i_56 (.I0(wrcal_done_reg_1), .I1(rdlvl_stg1_done_int_reg), .O(\init_state_r[0]_i_56_n_0 )); (* SOFT_HLUTNM = "soft_lutpair626" *) LUT4 #( .INIT(16'h0001)) \init_state_r[2]_i_23 (.I0(wrcal_done_reg_1), .I1(prech_req_posedge_r_reg), .I2(wrlvl_byte_redo), .I3(wrcal_resume_r), .O(\init_state_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair623" *) LUT4 #( .INIT(16'hB0BB)) \init_state_r[2]_i_29 (.I0(wrlvl_done_r1), .I1(wrlvl_final_mux), .I2(wrcal_done_reg_1), .I3(wrlvl_byte_redo), .O(\init_state_r_reg[2] )); LUT3 #( .INIT(8'h08)) \init_state_r[3]_i_12 (.I0(wrcal_done_reg_1), .I1(dqs_found_done_r_reg), .I2(rdlvl_stg1_start_int_reg), .O(\init_state_r_reg[3] )); LUT6 #( .INIT(64'h2FAF2FAF2FAF0000)) \init_state_r[4]_i_23 (.I0(\init_state_r[4]_i_34_n_0 ), .I1(mem_init_done_r), .I2(oclkdelay_calib_done_r_reg), .I3(wrcal_done_reg_1), .I4(mpr_rdlvl_done_r_reg), .I5(mpr_last_byte_done), .O(\init_state_r_reg[4] )); LUT6 #( .INIT(64'hB010000000000000)) \init_state_r[4]_i_34 (.I0(rdlvl_stg1_done_int_reg), .I1(wrcal_done_reg_1), .I2(dqs_found_done_r_reg), .I3(prbs_rdlvl_done_reg_rep), .I4(\init_state_r_reg[2] ), .I5(dqs_found_done_r_reg_0), .O(\init_state_r[4]_i_34_n_0 )); LUT6 #( .INIT(64'hFFFBFFFBFF00FFFB)) \init_state_r[5]_i_28 (.I0(wrlvl_byte_redo), .I1(dqs_found_done_r_reg), .I2(wrlvl_final_mux), .I3(wrlvl_done_r1), .I4(oclkdelay_center_calib_done_r_reg), .I5(prbs_rdlvl_done_reg_rep_0), .O(\init_state_r_reg[5] )); LUT6 #( .INIT(64'hFFFFFFFF44440004)) \input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [0]), .I3(\calib_sel_reg[1] [1]), .I4(calib_in_common), .I5(idelay_ld_rst), .O(LD0)); LUT6 #( .INIT(64'hFFFFFFFF44440040)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [0]), .I3(\calib_sel_reg[1] [1]), .I4(calib_in_common), .I5(idelay_ld_rst_3), .O(LD0_0)); LUT6 #( .INIT(64'hFFFFFFFF44440040)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__0 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [1]), .I3(\calib_sel_reg[1] [0]), .I4(calib_in_common), .I5(idelay_ld_rst_4), .O(LD0_1)); LUT6 #( .INIT(64'hFFFFFFFF44444000)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__1 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [0]), .I3(\calib_sel_reg[1] [1]), .I4(calib_in_common), .I5(idelay_ld_rst_5), .O(LD0_2)); (* SOFT_HLUTNM = "soft_lutpair633" *) LUT1 #( .INIT(2'h1)) \not_empty_wait_cnt[0]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[0] ), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair633" *) LUT2 #( .INIT(4'h6)) \not_empty_wait_cnt[1]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[0] ), .I1(\not_empty_wait_cnt_reg_n_0_[1] ), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair628" *) LUT3 #( .INIT(8'h6A)) \not_empty_wait_cnt[2]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[2] ), .I1(\not_empty_wait_cnt_reg_n_0_[1] ), .I2(\not_empty_wait_cnt_reg_n_0_[0] ), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair628" *) LUT4 #( .INIT(16'h6AAA)) \not_empty_wait_cnt[3]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[3] ), .I1(\not_empty_wait_cnt_reg_n_0_[0] ), .I2(\not_empty_wait_cnt_reg_n_0_[1] ), .I3(\not_empty_wait_cnt_reg_n_0_[2] ), .O(p_0_in[3])); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) \not_empty_wait_cnt[4]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\not_empty_wait_cnt_reg[0]_0 [3]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(wrcal_rd_wait), .O(\not_empty_wait_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair612" *) LUT5 #( .INIT(32'h6AAAAAAA)) \not_empty_wait_cnt[4]_i_2 (.I0(\not_empty_wait_cnt_reg_n_0_[4] ), .I1(\not_empty_wait_cnt_reg_n_0_[2] ), .I2(\not_empty_wait_cnt_reg_n_0_[1] ), .I3(\not_empty_wait_cnt_reg_n_0_[0] ), .I4(\not_empty_wait_cnt_reg_n_0_[3] ), .O(p_0_in[4])); FDRE #( .INIT(1'b0)) \not_empty_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in[0]), .Q(\not_empty_wait_cnt_reg_n_0_[0] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \not_empty_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in[1]), .Q(\not_empty_wait_cnt_reg_n_0_[1] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \not_empty_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in[2]), .Q(\not_empty_wait_cnt_reg_n_0_[2] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \not_empty_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in[3]), .Q(\not_empty_wait_cnt_reg_n_0_[3] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \not_empty_wait_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in[4]), .Q(\not_empty_wait_cnt_reg_n_0_[4] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \po_stg2_wrcal_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .Q(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_stg2_wrcal_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .Q(\idelay_tap_cnt_r_reg[0][2][0]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \po_stg2_wrcal_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(wrcal_dqs_cnt_r), .Q(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) rd_active_r1_reg (.C(CLK), .CE(1'b1), .D(phy_rddata_en_1), .Q(rd_active_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) rd_active_r2_reg (.C(CLK), .CE(1'b1), .D(rd_active_r1), .Q(rd_active_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) rd_active_r3_reg (.C(CLK), .CE(1'b1), .D(rd_active_r2), .Q(rd_active_r3), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair634" *) LUT1 #( .INIT(2'h1)) \tap_inc_wait_cnt[0]_i_1 (.I0(tap_inc_wait_cnt_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair634" *) LUT2 #( .INIT(4'h6)) \tap_inc_wait_cnt[1]_i_1 (.I0(tap_inc_wait_cnt_reg__0[1]), .I1(tap_inc_wait_cnt_reg__0[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair627" *) LUT3 #( .INIT(8'h6A)) \tap_inc_wait_cnt[2]_i_1 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .O(p_0_in__0[2])); LUT5 #( .INIT(32'hFFFFAFEF)) \tap_inc_wait_cnt[3]_i_1 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\not_empty_wait_cnt_reg[0]_0 [0]), .I4(rstdiv0_sync_r1_reg_rep__22), .O(\tap_inc_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair625" *) LUT4 #( .INIT(16'h6AAA)) \tap_inc_wait_cnt[3]_i_2 (.I0(tap_inc_wait_cnt_reg__0[3]), .I1(tap_inc_wait_cnt_reg__0[1]), .I2(tap_inc_wait_cnt_reg__0[0]), .I3(tap_inc_wait_cnt_reg__0[2]), .O(p_0_in__0[3])); FDRE #( .INIT(1'b0)) \tap_inc_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0[0]), .Q(tap_inc_wait_cnt_reg__0[0]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \tap_inc_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0[1]), .Q(tap_inc_wait_cnt_reg__0[1]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \tap_inc_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0[2]), .Q(tap_inc_wait_cnt_reg__0[2]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \tap_inc_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0[3]), .Q(tap_inc_wait_cnt_reg__0[3]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair622" *) LUT2 #( .INIT(4'h2)) \wl_tap_count_r[5]_i_3 (.I0(wrlvl_byte_redo), .I1(wrlvl_byte_redo_r), .O(done_dqs_dec239_out)); LUT5 #( .INIT(32'h0E0E000E)) wrcal_done_i_1 (.I0(wrcal_done_reg_1), .I1(cal2_done_r), .I2(rstdiv0_sync_r1_reg_rep__22), .I3(wrcal_sanity_chk), .I4(wrcal_done_reg_0), .O(wrcal_done_i_1_n_0)); FDRE #( .INIT(1'b0)) wrcal_done_reg (.C(CLK), .CE(1'b1), .D(wrcal_done_i_1_n_0), .Q(wrcal_done_reg_1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair631" *) LUT3 #( .INIT(8'h34)) \wrcal_dqs_cnt_r[0]_i_1 (.I0(\not_empty_wait_cnt_reg[0]_0 [2]), .I1(\wrcal_dqs_cnt_r[2]_i_2_n_0 ), .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .O(\wrcal_dqs_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair620" *) LUT4 #( .INIT(16'h1F20)) \wrcal_dqs_cnt_r[1]_i_1 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(\wrcal_dqs_cnt_r[2]_i_2_n_0 ), .I3(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .O(\wrcal_dqs_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair620" *) LUT5 #( .INIT(32'h07FF0800)) \wrcal_dqs_cnt_r[2]_i_1 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\wrcal_dqs_cnt_r[2]_i_2_n_0 ), .I4(wrcal_dqs_cnt_r), .O(\wrcal_dqs_cnt_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000054040000)) \wrcal_dqs_cnt_r[2]_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\wrcal_dqs_cnt_r[2]_i_3_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(wrcal_sanity_chk_reg), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(\not_empty_wait_cnt_reg[0]_0 [0]), .O(\wrcal_dqs_cnt_r[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair614" *) LUT5 #( .INIT(32'hCFFF8AAA)) \wrcal_dqs_cnt_r[2]_i_3 (.I0(prech_done), .I1(wrcal_dqs_cnt_r), .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I3(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I4(wrcal_done_reg_0), .O(\wrcal_dqs_cnt_r[2]_i_3_n_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wrcal_dqs_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r[0]_i_1_n_0 ), .Q(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__2)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wrcal_dqs_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r[1]_i_1_n_0 ), .Q(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__2)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \wrcal_dqs_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r[2]_i_1_n_0 ), .Q(wrcal_dqs_cnt_r), .R(rstdiv0_sync_r1_reg_rep__2)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 " *) SRL16E #( .INIT(16'h0000)) wrcal_pat_resume_r2_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(wrcal_pat_resume_r), .Q(wrcal_pat_resume_r2_reg_srl2_n_0)); LUT6 #( .INIT(64'h08000800033C003C)) wrcal_pat_resume_r_i_2 (.I0(\cal2_state_r[3]_i_8_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [0]), .I2(\not_empty_wait_cnt_reg[0]_0 [3]), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(wrcal_pat_resume_r_i_3_n_0), .I5(\not_empty_wait_cnt_reg[0]_0 [1]), .O(wrcal_pat_resume_r_reg_1)); LUT6 #( .INIT(64'h0000800000000000)) wrcal_pat_resume_r_i_3 (.I0(wrcal_pat_resume_r_reg_0), .I1(tap_inc_wait_cnt_reg__0[2]), .I2(tap_inc_wait_cnt_reg__0[0]), .I3(tap_inc_wait_cnt_reg__0[1]), .I4(wrcal_done_reg_0), .I5(tap_inc_wait_cnt_reg__0[3]), .O(wrcal_pat_resume_r_i_3_n_0)); FDRE #( .INIT(1'b0)) wrcal_pat_resume_r_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[2]_0 ), .Q(wrcal_pat_resume_r), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE #( .INIT(1'b0)) wrcal_pat_resume_reg (.C(CLK), .CE(1'b1), .D(wrcal_pat_resume_r2_reg_srl2_n_0), .Q(wrcal_resume_w), .R(1'b0)); FDRE #( .INIT(1'b0)) wrcal_prech_req_reg (.C(CLK), .CE(1'b1), .D(cal2_prech_req_r), .Q(wrcal_prech_req), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE #( .INIT(1'b0)) wrcal_sanity_chk_done_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[3]_0 ), .Q(wrcal_sanity_chk_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE #( .INIT(1'b0)) wrcal_sanity_chk_r_reg (.C(CLK), .CE(1'b1), .D(wrcal_sanity_chk), .Q(wrcal_done_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair630" *) LUT3 #( .INIT(8'h1F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_1 (.I0(wrcal_done_reg_1), .I1(first_wrcal_pat_r), .I2(oclkdelay_calib_done_r_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] )); (* SOFT_HLUTNM = "soft_lutpair630" *) LUT3 #( .INIT(8'h7F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1 (.I0(wrcal_done_reg_1), .I1(oclkdelay_calib_done_r_reg), .I2(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] )); (* SOFT_HLUTNM = "soft_lutpair626" *) LUT2 #( .INIT(4'h7)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_1 (.I0(wrcal_done_reg_1), .I1(oclkdelay_calib_done_r_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] )); (* SOFT_HLUTNM = "soft_lutpair629" *) LUT3 #( .INIT(8'h2F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_1 (.I0(wrcal_done_reg_1), .I1(rdlvl_stg1_done_int_reg), .I2(oclkdelay_calib_done_r_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] )); FDRE #( .INIT(1'b0)) wrlvl_byte_done_r_reg (.C(CLK), .CE(1'b1), .D(wrlvl_byte_done), .Q(wrlvl_byte_done_r), .R(1'b0)); LUT6 #( .INIT(64'h0000000022222E22)) wrlvl_byte_redo_i_2 (.I0(wrlvl_byte_redo_i_3_n_0), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(wrlvl_byte_done), .I4(wrlvl_byte_done_r), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(wrlvl_byte_redo_reg_0)); LUT6 #( .INIT(64'h0000000000300020)) wrlvl_byte_redo_i_3 (.I0(early1_data_reg_0), .I1(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I2(idelay_ld_reg_0), .I3(wrcal_done_reg_0), .I4(early2_data_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [2]), .O(wrlvl_byte_redo_i_3_n_0)); FDRE #( .INIT(1'b0)) wrlvl_byte_redo_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_data_match_r_reg_0 ), .Q(wrlvl_byte_redo), .R(rstdiv0_sync_r1_reg_rep__6)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_wrlvl" *) module ddr3_ifmig_7series_v4_0_ddr_phy_wrlvl (wr_level_done_r1_reg_0, wrlvl_byte_redo_r, wrlvl_final_r, dqs_po_dec_done, dqs_po_stg2_f_incdec, dqs_po_en_stg2_f, dqs_wl_po_stg2_c_incdec, \rd_data_edge_detect_r_reg[0]_0 , \FSM_sequential_wl_state_r_reg[0]_0 , p_0_in, \rd_data_edge_detect_r_reg[0]_1 , dqs_po_en_stg2_f_reg_0, wrlvl_done_r_reg, wrlvl_rank_done, D, \stg2_target_r_reg[4] , \stg2_r_reg[4] , \stg3_dec_val_reg[2] , \stg2_r_reg[5] , out, stable_cnt227_in, \stg3_dec_val_reg[2]_0 , \lim_state_reg[12] , \stg2_r_reg[0] , \po_rdval_cnt_reg[0]_0 , flag_ck_negedge09_out, \stable_cnt_reg[3]_0 , \rank_cnt_r_reg[0]_0 , \rank_cnt_r_reg[0]_1 , stable_cnt1, \wrlvl_redo_corse_inc_reg[2]_0 , po_cnt_dec_reg_0, flag_ck_negedge_reg_0, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \gen_byte_sel_div1.byte_sel_cnt_reg[2] , p_1_in, wrlvl_byte_done, done_dqs_tap_inc, wr_level_done_r_reg_0, wrlvl_rank_done_r_reg_0, dq_cnt_inc_reg_0, inhibit_edge_detect_r, inhibit_edge_detect_r_reg_0, \mcGo_r_reg[15] , CLK, wrlvl_byte_redo, wrlvl_final_mux, wr_lvl_start_reg, rstdiv0_sync_r1_reg_rep__17, SR, flag_ck_negedge_reg_1, \FSM_sequential_wl_state_r_reg[2]_0 , \FSM_sequential_wl_state_r_reg[0]_1 , \FSM_sequential_wl_state_r_reg[1]_0 , inhibit_edge_detect_r_reg_1, \wait_cnt_reg[0]_0 , \single_rank.done_dqs_dec_reg_0 , \FSM_sequential_wl_state_r_reg[2]_1 , S, \stg3_r_reg[5] , O, wl_sm_start, \byte_r_reg[0] , \byte_r_reg[1] , Q, \stg2_tap_cnt_reg[2] , \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \calib_sel_reg[3] , \po_counter_read_val_reg[5] , rstdiv0_sync_r1_reg_rep__22, oclkdelay_calib_done_r_reg, \po_stg2_wrcal_cnt_reg[2] , early1_data_reg, early1_data_reg_0, rstdiv0_sync_r1_reg_rep__20, \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 , pi_f_inc_reg, oclkdelay_calib_done_r_reg_0, delay_done_r4_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 , oclkdelay_calib_done_r_reg_1, byte_sel_cnt, \prbs_dqs_cnt_r_reg[2] , rstdiv0_sync_r1_reg_rep__24, pi_fine_dly_dec_done, rstdiv0_sync_r1_reg_rep, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , my_empty, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 , my_empty_6, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 , my_empty_7, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , my_empty_8, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 , po_cnt_dec_reg_1, rstdiv0_sync_r1_reg_rep__19, done_dqs_dec239_out, \po_stg2_wrcal_cnt_reg[0] , \po_stg2_wrcal_cnt_reg[2]_0 , \po_stg2_wrcal_cnt_reg[1] , wrlvl_byte_redo_reg); output wr_level_done_r1_reg_0; output wrlvl_byte_redo_r; output wrlvl_final_r; output dqs_po_dec_done; output dqs_po_stg2_f_incdec; output dqs_po_en_stg2_f; output dqs_wl_po_stg2_c_incdec; output \rd_data_edge_detect_r_reg[0]_0 ; output \FSM_sequential_wl_state_r_reg[0]_0 ; output p_0_in; output \rd_data_edge_detect_r_reg[0]_1 ; output dqs_po_en_stg2_f_reg_0; output wrlvl_done_r_reg; output wrlvl_rank_done; output [7:0]D; output [1:0]\stg2_target_r_reg[4] ; output \stg2_r_reg[4] ; output \stg3_dec_val_reg[2] ; output \stg2_r_reg[5] ; output [4:0]out; output stable_cnt227_in; output [2:0]\stg3_dec_val_reg[2]_0 ; output \lim_state_reg[12] ; output \stg2_r_reg[0] ; output \po_rdval_cnt_reg[0]_0 ; output flag_ck_negedge09_out; output [0:0]\stable_cnt_reg[3]_0 ; output \rank_cnt_r_reg[0]_0 ; output \rank_cnt_r_reg[0]_1 ; output stable_cnt1; output [1:0]\wrlvl_redo_corse_inc_reg[2]_0 ; output po_cnt_dec_reg_0; output flag_ck_negedge_reg_0; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; output p_1_in; output wrlvl_byte_done; output done_dqs_tap_inc; output wr_level_done_r_reg_0; output wrlvl_rank_done_r_reg_0; output dq_cnt_inc_reg_0; output inhibit_edge_detect_r; output inhibit_edge_detect_r_reg_0; input \mcGo_r_reg[15] ; input CLK; input wrlvl_byte_redo; input wrlvl_final_mux; input wr_lvl_start_reg; input [1:0]rstdiv0_sync_r1_reg_rep__17; input [1:0]SR; input flag_ck_negedge_reg_1; input \FSM_sequential_wl_state_r_reg[2]_0 ; input \FSM_sequential_wl_state_r_reg[0]_1 ; input \FSM_sequential_wl_state_r_reg[1]_0 ; input inhibit_edge_detect_r_reg_1; input \wait_cnt_reg[0]_0 ; input \single_rank.done_dqs_dec_reg_0 ; input \FSM_sequential_wl_state_r_reg[2]_1 ; input [0:0]S; input [2:0]\stg3_r_reg[5] ; input [3:0]O; input wl_sm_start; input \byte_r_reg[0] ; input \byte_r_reg[1] ; input [2:0]Q; input [2:0]\stg2_tap_cnt_reg[2] ; input [4:0]\po_counter_read_val_reg[8] ; input [4:0]\po_counter_read_val_reg[8]_0 ; input [0:0]\calib_sel_reg[3] ; input [3:0]\po_counter_read_val_reg[5] ; input rstdiv0_sync_r1_reg_rep__22; input oclkdelay_calib_done_r_reg; input [2:0]\po_stg2_wrcal_cnt_reg[2] ; input early1_data_reg; input early1_data_reg_0; input rstdiv0_sync_r1_reg_rep__20; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; input pi_f_inc_reg; input oclkdelay_calib_done_r_reg_0; input delay_done_r4_reg; input \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; input oclkdelay_calib_done_r_reg_1; input [0:0]byte_sel_cnt; input \prbs_dqs_cnt_r_reg[2] ; input rstdiv0_sync_r1_reg_rep__24; input pi_fine_dly_dec_done; input rstdiv0_sync_r1_reg_rep; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [0:0]my_empty; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; input [0:0]my_empty_6; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; input [0:0]my_empty_7; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [0:0]my_empty_8; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; input [0:0]po_cnt_dec_reg_1; input [0:0]rstdiv0_sync_r1_reg_rep__19; input done_dqs_dec239_out; input \po_stg2_wrcal_cnt_reg[0] ; input \po_stg2_wrcal_cnt_reg[2]_0 ; input \po_stg2_wrcal_cnt_reg[1] ; input wrlvl_byte_redo_reg; wire CLK; wire [7:0]D; wire \FSM_sequential_wl_state_r[0]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_13_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_14_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_15_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_16_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_4_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_4_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_12_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_13_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_14_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_15_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_4_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_12_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_9_n_0 ; wire \FSM_sequential_wl_state_r_reg[0]_0 ; wire \FSM_sequential_wl_state_r_reg[0]_1 ; wire \FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ; wire \FSM_sequential_wl_state_r_reg[1]_0 ; wire \FSM_sequential_wl_state_r_reg[2]_0 ; wire \FSM_sequential_wl_state_r_reg[2]_1 ; wire \FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ; wire \FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ; wire [3:0]O; wire [2:0]Q; wire [0:0]S; wire [1:0]SR; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire [0:0]byte_sel_cnt; wire [0:0]\calib_sel_reg[3] ; wire [2:0]corse_cnt; wire \corse_cnt[0][0]_i_1_n_0 ; wire \corse_cnt[0][0]_i_3_n_0 ; wire \corse_cnt[0][0]_i_4_n_0 ; wire \corse_cnt[0][1]_i_1_n_0 ; wire \corse_cnt[0][1]_i_3_n_0 ; wire \corse_cnt[0][1]_i_4_n_0 ; wire \corse_cnt[0][1]_i_5_n_0 ; wire \corse_cnt[0][2]_i_10_n_0 ; wire \corse_cnt[0][2]_i_1_n_0 ; wire \corse_cnt[0][2]_i_3_n_0 ; wire \corse_cnt[0][2]_i_4_n_0 ; wire \corse_cnt[0][2]_i_5_n_0 ; wire \corse_cnt[0][2]_i_6_n_0 ; wire \corse_cnt[0][2]_i_7_n_0 ; wire \corse_cnt[0][2]_i_8_n_0 ; wire \corse_cnt[0][2]_i_9_n_0 ; wire \corse_cnt[1][0]_i_1_n_0 ; wire \corse_cnt[1][1]_i_1_n_0 ; wire \corse_cnt[1][2]_i_1_n_0 ; wire \corse_cnt[1][2]_i_2_n_0 ; wire \corse_cnt[1][2]_i_3_n_0 ; wire \corse_cnt[1][2]_i_4_n_0 ; wire \corse_cnt[2][0]_i_1_n_0 ; wire \corse_cnt[2][1]_i_1_n_0 ; wire \corse_cnt[2][2]_i_1_n_0 ; wire \corse_cnt[2][2]_i_2_n_0 ; wire \corse_cnt[2][2]_i_3_n_0 ; wire \corse_cnt[2][2]_i_4_n_0 ; wire \corse_cnt[3][0]_i_1_n_0 ; wire \corse_cnt[3][1]_i_1_n_0 ; wire \corse_cnt[3][2]_i_1_n_0 ; wire \corse_cnt[3][2]_i_2_n_0 ; wire \corse_cnt[3][2]_i_3_n_0 ; wire \corse_cnt[3][2]_i_4_n_0 ; wire \corse_cnt_reg_n_0_[0][0] ; wire \corse_cnt_reg_n_0_[0][1] ; wire \corse_cnt_reg_n_0_[0][2] ; wire \corse_cnt_reg_n_0_[1][0] ; wire \corse_cnt_reg_n_0_[1][1] ; wire \corse_cnt_reg_n_0_[1][2] ; wire \corse_cnt_reg_n_0_[2][0] ; wire \corse_cnt_reg_n_0_[2][1] ; wire \corse_cnt_reg_n_0_[2][2] ; wire \corse_cnt_reg_n_0_[3][0] ; wire \corse_cnt_reg_n_0_[3][1] ; wire \corse_cnt_reg_n_0_[3][2] ; wire \corse_dec[0][0]_i_1_n_0 ; wire \corse_dec[0][1]_i_1_n_0 ; wire \corse_dec[0][2]_i_1_n_0 ; wire \corse_dec[0][2]_i_2_n_0 ; wire \corse_dec[1][0]_i_1_n_0 ; wire \corse_dec[1][1]_i_1_n_0 ; wire \corse_dec[1][2]_i_1_n_0 ; wire \corse_dec[1][2]_i_2_n_0 ; wire \corse_dec[2][0]_i_1_n_0 ; wire \corse_dec[2][1]_i_1_n_0 ; wire \corse_dec[2][2]_i_1_n_0 ; wire \corse_dec[2][2]_i_2_n_0 ; wire \corse_dec[3][0]_i_1_n_0 ; wire \corse_dec[3][1]_i_1_n_0 ; wire \corse_dec[3][2]_i_1_n_0 ; wire \corse_dec[3][2]_i_2_n_0 ; wire \corse_dec[3][2]_i_3_n_0 ; wire \corse_dec[3][2]_i_4_n_0 ; wire \corse_dec[3][2]_i_5_n_0 ; wire \corse_dec_reg_n_0_[0][0] ; wire \corse_dec_reg_n_0_[0][1] ; wire \corse_dec_reg_n_0_[0][2] ; wire \corse_dec_reg_n_0_[1][0] ; wire \corse_dec_reg_n_0_[1][1] ; wire \corse_dec_reg_n_0_[1][2] ; wire \corse_dec_reg_n_0_[2][0] ; wire \corse_dec_reg_n_0_[2][1] ; wire \corse_dec_reg_n_0_[2][2] ; wire \corse_dec_reg_n_0_[3][0] ; wire \corse_dec_reg_n_0_[3][1] ; wire \corse_dec_reg_n_0_[3][2] ; wire \corse_inc[0][0]_i_1_n_0 ; wire \corse_inc[0][1]_i_1_n_0 ; wire \corse_inc[0][2]_i_1_n_0 ; wire \corse_inc[0][2]_i_2_n_0 ; wire \corse_inc[0][2]_i_3_n_0 ; wire \corse_inc[1][0]_i_1_n_0 ; wire \corse_inc[1][1]_i_1_n_0 ; wire \corse_inc[1][2]_i_1_n_0 ; wire \corse_inc[1][2]_i_2_n_0 ; wire \corse_inc[1][2]_i_3_n_0 ; wire \corse_inc[2][0]_i_1_n_0 ; wire \corse_inc[2][1]_i_1_n_0 ; wire \corse_inc[2][2]_i_1_n_0 ; wire \corse_inc[2][2]_i_2_n_0 ; wire \corse_inc[2][2]_i_3_n_0 ; wire \corse_inc[3][0]_i_1_n_0 ; wire \corse_inc[3][0]_i_2_n_0 ; wire \corse_inc[3][1]_i_1_n_0 ; wire \corse_inc[3][1]_i_2_n_0 ; wire \corse_inc[3][2]_i_1_n_0 ; wire \corse_inc[3][2]_i_2_n_0 ; wire \corse_inc[3][2]_i_3_n_0 ; wire \corse_inc[3][2]_i_4_n_0 ; wire \corse_inc[3][2]_i_5_n_0 ; wire \corse_inc[3][2]_i_6_n_0 ; wire \corse_inc[3][2]_i_7_n_0 ; wire \corse_inc_reg_n_0_[0][0] ; wire \corse_inc_reg_n_0_[0][1] ; wire \corse_inc_reg_n_0_[0][2] ; wire \corse_inc_reg_n_0_[1][0] ; wire \corse_inc_reg_n_0_[1][1] ; wire \corse_inc_reg_n_0_[1][2] ; wire \corse_inc_reg_n_0_[2][0] ; wire \corse_inc_reg_n_0_[2][1] ; wire \corse_inc_reg_n_0_[2][2] ; wire \corse_inc_reg_n_0_[3][0] ; wire \corse_inc_reg_n_0_[3][1] ; wire \corse_inc_reg_n_0_[3][2] ; wire delay_done_r4_reg; wire done_dqs_dec; wire done_dqs_dec239_out; wire done_dqs_tap_inc; wire dq_cnt_inc_reg_0; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; wire [2:0]dqs_count_r; wire dqs_count_r140_out; wire \dqs_count_r[0]_i_1_n_0 ; wire \dqs_count_r[0]_i_4_n_0 ; wire \dqs_count_r[0]_i_5_n_0 ; wire \dqs_count_r[0]_i_6_n_0 ; wire \dqs_count_r[0]_i_7_n_0 ; wire \dqs_count_r[0]_i_8_n_0 ; wire \dqs_count_r[1]_i_1_n_0 ; wire \dqs_count_r[1]_i_4_n_0 ; wire \dqs_count_r[1]_i_5_n_0 ; wire \dqs_count_r[1]_i_6_n_0 ; wire \dqs_count_r[1]_i_7_n_0 ; wire \dqs_count_r[1]_i_8_n_0 ; wire \dqs_count_r[2]_i_10_n_0 ; wire \dqs_count_r[2]_i_11_n_0 ; wire \dqs_count_r[2]_i_2_n_0 ; wire \dqs_count_r[2]_i_5_n_0 ; wire \dqs_count_r[2]_i_6_n_0 ; wire \dqs_count_r[2]_i_7_n_0 ; wire \dqs_count_r[2]_i_8_n_0 ; wire \dqs_count_r[2]_i_9_n_0 ; wire \dqs_count_r_reg[0]_i_2_n_0 ; wire \dqs_count_r_reg[0]_i_3_n_0 ; wire \dqs_count_r_reg[0]_rep_n_0 ; wire \dqs_count_r_reg[1]_i_2_n_0 ; wire \dqs_count_r_reg[1]_i_3_n_0 ; wire \dqs_count_r_reg[1]_rep_n_0 ; wire \dqs_count_r_reg[2]_i_3_n_0 ; wire \dqs_count_r_reg[2]_i_4_n_0 ; wire dqs_po_dec_done; wire dqs_po_en_stg2_f; wire dqs_po_en_stg2_f_i_1_n_0; wire dqs_po_en_stg2_f_reg_0; wire dqs_po_stg2_f_incdec; wire dqs_po_stg2_f_incdec0; wire dqs_po_stg2_f_incdec_i_2_n_0; wire dqs_po_stg2_f_incdec_i_3_n_0; wire dqs_wl_po_stg2_c_incdec; wire dqs_wl_po_stg2_c_incdec_i_1_n_0; wire early1_data_reg; wire early1_data_reg_0; wire [0:0]final_coarse_tap; wire \final_coarse_tap_reg_n_0_[0][0] ; wire \final_coarse_tap_reg_n_0_[0][1] ; wire \final_coarse_tap_reg_n_0_[0][2] ; wire \final_coarse_tap_reg_n_0_[1][0] ; wire \final_coarse_tap_reg_n_0_[1][1] ; wire \final_coarse_tap_reg_n_0_[1][2] ; wire \final_coarse_tap_reg_n_0_[2][0] ; wire \final_coarse_tap_reg_n_0_[2][1] ; wire \final_coarse_tap_reg_n_0_[2][2] ; wire \final_coarse_tap_reg_n_0_[3][0] ; wire \final_coarse_tap_reg_n_0_[3][1] ; wire \final_coarse_tap_reg_n_0_[3][2] ; wire [5:0]fine_dec_cnt; wire \fine_dec_cnt[1]_i_2_n_0 ; wire \fine_dec_cnt[2]_i_2_n_0 ; wire \fine_dec_cnt[3]_i_2_n_0 ; wire \fine_dec_cnt[4]_i_2_n_0 ; wire \fine_dec_cnt[5]_i_3_n_0 ; wire \fine_dec_cnt[5]_i_4_n_0 ; wire \fine_dec_cnt[5]_i_5_n_0 ; wire \fine_dec_cnt[5]_i_6_n_0 ; wire \fine_dec_cnt[5]_i_7_n_0 ; wire \fine_dec_cnt[5]_i_8_n_0 ; wire [5:0]fine_dec_cnt__0; wire \fine_dec_cnt_reg[5]_i_1_n_0 ; wire [5:0]fine_inc; wire \fine_inc[0][5]_i_1_n_0 ; wire \fine_inc[0][5]_i_3_n_0 ; wire \fine_inc[1][0]_i_1_n_0 ; wire \fine_inc[1][1]_i_1_n_0 ; wire \fine_inc[1][2]_i_1_n_0 ; wire \fine_inc[1][3]_i_1_n_0 ; wire \fine_inc[1][4]_i_1_n_0 ; wire \fine_inc[1][5]_i_1_n_0 ; wire \fine_inc[1][5]_i_2_n_0 ; wire \fine_inc[1][5]_i_3_n_0 ; wire \fine_inc[2][0]_i_1_n_0 ; wire \fine_inc[2][1]_i_1_n_0 ; wire \fine_inc[2][2]_i_1_n_0 ; wire \fine_inc[2][3]_i_1_n_0 ; wire \fine_inc[2][4]_i_1_n_0 ; wire \fine_inc[2][5]_i_1_n_0 ; wire \fine_inc[2][5]_i_2_n_0 ; wire \fine_inc[2][5]_i_3_n_0 ; wire \fine_inc[3][0]_i_1_n_0 ; wire \fine_inc[3][1]_i_1_n_0 ; wire \fine_inc[3][2]_i_1_n_0 ; wire \fine_inc[3][2]_i_2_n_0 ; wire \fine_inc[3][2]_i_3_n_0 ; wire \fine_inc[3][2]_i_4_n_0 ; wire \fine_inc[3][3]_i_1_n_0 ; wire \fine_inc[3][4]_i_1_n_0 ; wire \fine_inc[3][4]_i_2_n_0 ; wire \fine_inc[3][4]_i_3_n_0 ; wire \fine_inc[3][4]_i_4_n_0 ; wire \fine_inc[3][5]_i_1_n_0 ; wire \fine_inc[3][5]_i_2_n_0 ; wire \fine_inc[3][5]_i_3_n_0 ; wire \fine_inc[3][5]_i_5_n_0 ; wire \fine_inc[3][5]_i_6_n_0 ; wire \fine_inc[3][5]_i_7_n_0 ; wire \fine_inc[3][5]_i_8_n_0 ; wire \fine_inc_reg_n_0_[0][0] ; wire \fine_inc_reg_n_0_[0][1] ; wire \fine_inc_reg_n_0_[0][2] ; wire \fine_inc_reg_n_0_[0][3] ; wire \fine_inc_reg_n_0_[0][4] ; wire \fine_inc_reg_n_0_[0][5] ; wire \fine_inc_reg_n_0_[1][0] ; wire \fine_inc_reg_n_0_[1][1] ; wire \fine_inc_reg_n_0_[1][2] ; wire \fine_inc_reg_n_0_[1][3] ; wire \fine_inc_reg_n_0_[1][4] ; wire \fine_inc_reg_n_0_[1][5] ; wire \fine_inc_reg_n_0_[2][0] ; wire \fine_inc_reg_n_0_[2][1] ; wire \fine_inc_reg_n_0_[2][2] ; wire \fine_inc_reg_n_0_[2][3] ; wire \fine_inc_reg_n_0_[2][4] ; wire \fine_inc_reg_n_0_[2][5] ; wire \fine_inc_reg_n_0_[3][0] ; wire \fine_inc_reg_n_0_[3][1] ; wire \fine_inc_reg_n_0_[3][2] ; wire \fine_inc_reg_n_0_[3][3] ; wire \fine_inc_reg_n_0_[3][4] ; wire \fine_inc_reg_n_0_[3][5] ; wire flag_ck_negedge09_out; wire flag_ck_negedge_i_10_n_0; wire flag_ck_negedge_i_6_n_0; wire flag_ck_negedge_i_7_n_0; wire flag_ck_negedge_i_8_n_0; wire flag_ck_negedge_reg_0; wire flag_ck_negedge_reg_1; wire flag_init; wire flag_init_i_1_n_0; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][0] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][1] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][2] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][3] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][4] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][5] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][0] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][1] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][2] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][3] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][4] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][5] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][0] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][1] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][2] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][3] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][4] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][5] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][0] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][1] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][2] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][3] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][4] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][5] ; wire \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ; wire \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ; wire \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ; wire \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ; wire \incdec_wait_cnt[3]_i_1_n_0 ; wire [3:0]incdec_wait_cnt_reg__0; wire inhibit_edge_detect_r; wire inhibit_edge_detect_r_i_4_n_0; wire inhibit_edge_detect_r_reg_0; wire inhibit_edge_detect_r_reg_1; wire [5:0]largest; wire \lim_state_reg[12] ; wire \mcGo_r_reg[15] ; wire [0:0]my_empty; wire [0:0]my_empty_6; wire [0:0]my_empty_7; wire [0:0]my_empty_8; wire [5:3]\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_calib_done_r_reg_1; (* RTL_KEEP = "yes" *) wire [4:0]out; wire p_0_in; wire p_0_in32_in; wire [3:0]p_0_in__0; wire [3:0]p_0_in__0__0; wire \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ; wire \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ; wire \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ; wire \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ; wire \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ; wire \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ; wire \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ; wire \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ; wire p_1_in; wire p_1_in1_in; wire p_1_in28_in; wire p_1_in_0; wire p_21_out; wire phy_ctl_ready_r4_reg_srl4_n_0; wire phy_ctl_ready_r5; wire phy_ctl_ready_r6_reg_n_0; wire pi_f_inc_reg; wire pi_fine_dly_dec_done; wire po_cnt_dec_reg_0; wire [0:0]po_cnt_dec_reg_1; wire [3:0]\po_counter_read_val_reg[5] ; wire [4:0]\po_counter_read_val_reg[8] ; wire [4:0]\po_counter_read_val_reg[8]_0 ; wire po_dec_done; wire po_dec_done_i_1_n_0; wire po_dec_done_i_2_n_0; wire po_dec_done_i_3_n_0; wire [8:0]po_rdval_cnt; wire \po_rdval_cnt[0]_i_1_n_0 ; wire \po_rdval_cnt[1]_i_1_n_0 ; wire \po_rdval_cnt[2]_i_1_n_0 ; wire \po_rdval_cnt[3]_i_1_n_0 ; wire \po_rdval_cnt[4]_i_1_n_0 ; wire \po_rdval_cnt[4]_i_2_n_0 ; wire \po_rdval_cnt[5]_i_1_n_0 ; wire \po_rdval_cnt[5]_i_2_n_0 ; wire \po_rdval_cnt[6]_i_1_n_0 ; wire \po_rdval_cnt[6]_i_2_n_0 ; wire \po_rdval_cnt[7]_i_1_n_0 ; wire \po_rdval_cnt[7]_i_2_n_0 ; wire \po_rdval_cnt[8]_i_1_n_0 ; wire \po_rdval_cnt[8]_i_2_n_0 ; wire \po_rdval_cnt[8]_i_4_n_0 ; wire \po_rdval_cnt[8]_i_5_n_0 ; wire \po_rdval_cnt[8]_i_6_n_0 ; wire \po_rdval_cnt[8]_i_7_n_0 ; wire \po_rdval_cnt_reg[0]_0 ; wire \po_stg2_wrcal_cnt_reg[0] ; wire \po_stg2_wrcal_cnt_reg[1] ; wire [2:0]\po_stg2_wrcal_cnt_reg[2] ; wire \po_stg2_wrcal_cnt_reg[2]_0 ; wire \prbs_dqs_cnt_r_reg[2] ; wire rank_cnt_r; wire \rank_cnt_r[0]_i_1_n_0 ; wire \rank_cnt_r[1]_i_1_n_0 ; wire \rank_cnt_r_reg[0]_0 ; wire \rank_cnt_r_reg[0]_1 ; wire rd_data_edge_detect_r0; wire \rd_data_edge_detect_r[0]_i_1_n_0 ; wire \rd_data_edge_detect_r[1]_i_1_n_0 ; wire \rd_data_edge_detect_r[2]_i_1_n_0 ; wire \rd_data_edge_detect_r[3]_i_2_n_0 ; wire \rd_data_edge_detect_r[3]_i_3_n_0 ; wire \rd_data_edge_detect_r[3]_i_4_n_0 ; wire \rd_data_edge_detect_r[3]_i_5_n_0 ; wire \rd_data_edge_detect_r[3]_i_6_n_0 ; wire \rd_data_edge_detect_r_reg[0]_0 ; wire \rd_data_edge_detect_r_reg[0]_1 ; wire \rd_data_edge_detect_r_reg_n_0_[0] ; wire \rd_data_edge_detect_r_reg_n_0_[1] ; wire \rd_data_edge_detect_r_reg_n_0_[2] ; wire \rd_data_edge_detect_r_reg_n_0_[3] ; wire rd_data_previous_r0; wire \rd_data_previous_r[3]_i_2_n_0 ; wire \rd_data_previous_r[3]_i_3_n_0 ; wire \rd_data_previous_r[3]_i_4_n_0 ; wire \rd_data_previous_r_reg_n_0_[0] ; wire \rd_data_previous_r_reg_n_0_[1] ; wire \rd_data_previous_r_reg_n_0_[2] ; wire \rd_data_previous_r_reg_n_0_[3] ; wire rstdiv0_sync_r1_reg_rep; wire [1:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__24; wire \single_rank.done_dqs_dec_i_1_n_0 ; wire \single_rank.done_dqs_dec_reg_0 ; wire \smallest[0][0]_i_2_n_0 ; wire \smallest[0][1]_i_2_n_0 ; wire \smallest[0][2]_i_2_n_0 ; wire \smallest[0][3]_i_2_n_0 ; wire \smallest[0][4]_i_2_n_0 ; wire \smallest[0][5]_i_2_n_0 ; wire \smallest[0][5]_i_4_n_0 ; wire \smallest[0][5]_i_5_n_0 ; wire \smallest[1][0]_i_1_n_0 ; wire \smallest[1][1]_i_1_n_0 ; wire \smallest[1][2]_i_1_n_0 ; wire \smallest[1][3]_i_1_n_0 ; wire \smallest[1][4]_i_1_n_0 ; wire \smallest[1][5]_i_1_n_0 ; wire \smallest[1][5]_i_2_n_0 ; wire \smallest[2][0]_i_1_n_0 ; wire \smallest[2][1]_i_1_n_0 ; wire \smallest[2][2]_i_1_n_0 ; wire \smallest[2][3]_i_1_n_0 ; wire \smallest[2][4]_i_1_n_0 ; wire \smallest[2][5]_i_1_n_0 ; wire \smallest[2][5]_i_2_n_0 ; wire \smallest[3][0]_i_1_n_0 ; wire \smallest[3][1]_i_1_n_0 ; wire \smallest[3][2]_i_1_n_0 ; wire \smallest[3][3]_i_1_n_0 ; wire \smallest[3][4]_i_1_n_0 ; wire \smallest[3][5]_i_1_n_0 ; wire \smallest[3][5]_i_2_n_0 ; wire [5:0]\smallest_reg[0]__0 ; wire [5:0]\smallest_reg[1]__0 ; wire [5:0]\smallest_reg[2]__0 ; wire [5:0]\smallest_reg[3]__0 ; wire stable_cnt; wire stable_cnt0; wire stable_cnt1; wire stable_cnt227_in; wire \stable_cnt[3]_i_4_n_0 ; wire \stable_cnt[3]_i_6_n_0 ; wire \stable_cnt[3]_i_7_n_0 ; wire [0:0]\stable_cnt_reg[3]_0 ; wire \stable_cnt_reg_n_0_[1] ; wire \stable_cnt_reg_n_0_[2] ; wire \stable_cnt_reg_n_0_[3] ; wire \stg2_r_reg[0] ; wire \stg2_r_reg[4] ; wire \stg2_r_reg[5] ; wire \stg2_tap_cnt[3]_i_4_n_0 ; wire [2:0]\stg2_tap_cnt_reg[2] ; wire \stg2_target_r[4]_i_4_n_0 ; wire \stg2_target_r[4]_i_5_n_0 ; wire \stg2_target_r[8]_i_6_n_0 ; wire [1:0]\stg2_target_r_reg[4] ; wire \stg2_target_r_reg[4]_i_1_n_0 ; wire \stg2_target_r_reg[4]_i_1_n_1 ; wire \stg2_target_r_reg[4]_i_1_n_2 ; wire \stg2_target_r_reg[4]_i_1_n_3 ; wire \stg2_target_r_reg[8]_i_1_n_1 ; wire \stg2_target_r_reg[8]_i_1_n_2 ; wire \stg2_target_r_reg[8]_i_1_n_3 ; wire \stg3_dec_val_reg[2] ; wire [2:0]\stg3_dec_val_reg[2]_0 ; wire [2:0]\stg3_r_reg[5] ; wire \u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ; wire wait_cnt0; wire [3:0]wait_cnt0__0; wire \wait_cnt[1]_i_1_n_0 ; wire \wait_cnt_reg[0]_0 ; wire [3:0]wait_cnt_reg__0; wire wl_corse_cnt; wire \wl_corse_cnt[0][0][0]_i_1_n_0 ; wire \wl_corse_cnt[0][0][1]_i_1_n_0 ; wire \wl_corse_cnt[0][0][2]_i_2_n_0 ; wire \wl_corse_cnt[0][0][2]_i_3_n_0 ; wire \wl_corse_cnt[0][0][2]_i_4_n_0 ; wire \wl_corse_cnt[0][1][2]_i_1_n_0 ; wire \wl_corse_cnt[0][2][2]_i_1_n_0 ; wire \wl_corse_cnt[0][3][2]_i_1_n_0 ; wire [2:0]\wl_corse_cnt_reg[0][0]__0 ; wire [2:0]\wl_corse_cnt_reg[0][1]__0 ; wire [2:0]\wl_corse_cnt_reg[0][2]__0 ; wire [2:0]\wl_corse_cnt_reg[0][3]__0 ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][5] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][5] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][5] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][5] ; wire [23:0]wl_po_fine_cnt; wire wl_sm_start; wire wl_state_r1; wire \wl_state_r1[0]_i_1_n_0 ; wire \wl_state_r1[1]_i_1_n_0 ; wire \wl_state_r1[2]_i_1_n_0 ; wire \wl_state_r1[3]_i_1_n_0 ; wire \wl_state_r1[4]_i_1_n_0 ; wire \wl_state_r1_reg_n_0_[0] ; wire \wl_state_r1_reg_n_0_[1] ; wire \wl_state_r1_reg_n_0_[2] ; wire \wl_state_r1_reg_n_0_[3] ; wire \wl_state_r1_reg_n_0_[4] ; wire [5:0]wl_tap_count_r; wire \wl_tap_count_r[0]_i_2_n_0 ; wire \wl_tap_count_r[0]_i_3_n_0 ; wire \wl_tap_count_r[1]_i_2_n_0 ; wire \wl_tap_count_r[1]_i_3_n_0 ; wire \wl_tap_count_r[1]_i_4_n_0 ; wire \wl_tap_count_r[2]_i_2_n_0 ; wire \wl_tap_count_r[2]_i_3_n_0 ; wire \wl_tap_count_r[2]_i_4_n_0 ; wire \wl_tap_count_r[3]_i_2_n_0 ; wire \wl_tap_count_r[3]_i_3_n_0 ; wire \wl_tap_count_r[3]_i_4_n_0 ; wire \wl_tap_count_r[4]_i_2_n_0 ; wire \wl_tap_count_r[4]_i_3_n_0 ; wire \wl_tap_count_r[4]_i_4_n_0 ; wire \wl_tap_count_r[5]_i_1_n_0 ; wire \wl_tap_count_r[5]_i_4_n_0 ; wire \wl_tap_count_r[5]_i_5_n_0 ; wire \wl_tap_count_r[5]_i_6_n_0 ; wire \wl_tap_count_r_reg_n_0_[0] ; wire \wl_tap_count_r_reg_n_0_[1] ; wire \wl_tap_count_r_reg_n_0_[2] ; wire \wl_tap_count_r_reg_n_0_[3] ; wire \wl_tap_count_r_reg_n_0_[4] ; wire \wl_tap_count_r_reg_n_0_[5] ; wire wr_level_done0; wire wr_level_done_r1; wire wr_level_done_r1_reg_0; wire wr_level_done_r2; wire wr_level_done_r3; wire wr_level_done_r4; wire wr_level_done_r5; wire wr_level_done_r_reg_0; wire wr_level_start_r; wire wr_lvl_start_reg; wire wrlvl_byte_done; wire wrlvl_byte_done_i_1_n_0; wire wrlvl_byte_redo; wire wrlvl_byte_redo_r; wire wrlvl_byte_redo_reg; wire wrlvl_done_r_reg; wire wrlvl_final_mux; wire wrlvl_final_r; wire wrlvl_rank_done; wire wrlvl_rank_done_r_reg_0; wire \wrlvl_redo_corse_inc[0]_i_1_n_0 ; wire \wrlvl_redo_corse_inc[1]_i_1_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_1_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_2_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_3_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_4_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_7_n_0 ; wire [2:0]wrlvl_redo_corse_inc__0; wire [1:0]\wrlvl_redo_corse_inc_reg[2]_0 ; wire [0:0]\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED ; wire [3:3]\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED ; LUT6 #( .INIT(64'hFFFFFFBF00000000)) \FSM_sequential_wl_state_r[0]_i_1 (.I0(\FSM_sequential_wl_state_r[0]_i_2_n_0 ), .I1(out[4]), .I2(\FSM_sequential_wl_state_r_reg[0]_0 ), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[0]_i_3_n_0 ), .I5(\FSM_sequential_wl_state_r[0]_i_4_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hEEAEEEAEEEAEEFAF)) \FSM_sequential_wl_state_r[0]_i_10 (.I0(out[4]), .I1(out[3]), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I4(stable_cnt227_in), .I5(stable_cnt1), .O(\FSM_sequential_wl_state_r[0]_i_10_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_sequential_wl_state_r[0]_i_11 (.I0(out[3]), .I1(out[0]), .O(\FSM_sequential_wl_state_r[0]_i_11_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_sequential_wl_state_r[0]_i_13 (.I0(p_0_in), .I1(out[3]), .O(\FSM_sequential_wl_state_r[0]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair344" *) LUT3 #( .INIT(8'hF4)) \FSM_sequential_wl_state_r[0]_i_14 (.I0(wr_level_done_r5), .I1(wl_sm_start), .I2(wrlvl_byte_redo), .O(\FSM_sequential_wl_state_r[0]_i_14_n_0 )); LUT5 #( .INIT(32'hFC7FFC7C)) \FSM_sequential_wl_state_r[0]_i_15 (.I0(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I1(out[1]), .I2(out[3]), .I3(out[4]), .I4(wl_state_r1), .O(\FSM_sequential_wl_state_r[0]_i_15_n_0 )); LUT6 #( .INIT(64'h3434343430333030)) \FSM_sequential_wl_state_r[0]_i_16 (.I0(wr_level_done_r5), .I1(out[1]), .I2(out[4]), .I3(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I4(wrlvl_byte_redo), .I5(out[3]), .O(\FSM_sequential_wl_state_r[0]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair344" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_wl_state_r[0]_i_17 (.I0(wr_level_start_r), .I1(wl_sm_start), .I2(wr_level_done_r1_reg_0), .O(wl_state_r1)); LUT4 #( .INIT(16'hFFFE)) \FSM_sequential_wl_state_r[0]_i_2 (.I0(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I1(out[0]), .I2(\FSM_sequential_wl_state_r[0]_i_5_n_0 ), .I3(out[2]), .O(\FSM_sequential_wl_state_r[0]_i_2_n_0 )); LUT3 #( .INIT(8'h7F)) \FSM_sequential_wl_state_r[0]_i_3 (.I0(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .I1(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I2(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAEAAAAAA)) \FSM_sequential_wl_state_r[0]_i_4 (.I0(\FSM_sequential_wl_state_r[0]_i_6_n_0 ), .I1(out[2]), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[3]_i_7_n_0 ), .I4(out[3]), .I5(\FSM_sequential_wl_state_r[0]_i_7_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair310" *) LUT3 #( .INIT(8'h7F)) \FSM_sequential_wl_state_r[0]_i_5 (.I0(\wl_tap_count_r_reg_n_0_[5] ), .I1(\wl_tap_count_r_reg_n_0_[4] ), .I2(\wl_tap_count_r_reg_n_0_[3] ), .O(\FSM_sequential_wl_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'hEA00000000000000)) \FSM_sequential_wl_state_r[0]_i_6 (.I0(out[2]), .I1(out[3]), .I2(p_0_in), .I3(out[4]), .I4(\FSM_sequential_wl_state_r[0]_i_8_n_0 ), .I5(\FSM_sequential_wl_state_r[0]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_6_n_0 )); LUT6 #( .INIT(64'hB888FFFFB8880000)) \FSM_sequential_wl_state_r[0]_i_7 (.I0(\FSM_sequential_wl_state_r[0]_i_10_n_0 ), .I1(out[1]), .I2(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I3(\FSM_sequential_wl_state_r[0]_i_11_n_0 ), .I4(out[2]), .I5(\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFF7FFFFFFFF)) \FSM_sequential_wl_state_r[0]_i_8 (.I0(out[0]), .I1(dqs_count_r[0]), .I2(dqs_count_r[2]), .I3(\FSM_sequential_wl_state_r[0]_i_13_n_0 ), .I4(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I5(dqs_count_r[1]), .O(\FSM_sequential_wl_state_r[0]_i_8_n_0 )); LUT5 #( .INIT(32'hFF5D5D5D)) \FSM_sequential_wl_state_r[0]_i_9 (.I0(out[0]), .I1(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I2(\FSM_sequential_wl_state_r[0]_i_14_n_0 ), .I3(p_0_in), .I4(out[3]), .O(\FSM_sequential_wl_state_r[0]_i_9_n_0 )); LUT6 #( .INIT(64'hA888A88888A88888)) \FSM_sequential_wl_state_r[1]_i_1 (.I0(\FSM_sequential_wl_state_r[1]_i_2_n_0 ), .I1(\FSM_sequential_wl_state_r[1]_i_3_n_0 ), .I2(\FSM_sequential_wl_state_r[1]_i_4_n_0 ), .I3(out[1]), .I4(out[4]), .I5(out[2]), .O(\FSM_sequential_wl_state_r[1]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFA200)) \FSM_sequential_wl_state_r[1]_i_10 (.I0(out[2]), .I1(out[4]), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I4(\FSM_sequential_wl_state_r[1]_i_11_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_10_n_0 )); LUT6 #( .INIT(64'h00BB00BBFF0BFFBB)) \FSM_sequential_wl_state_r[1]_i_11 (.I0(\FSM_sequential_wl_state_r[0]_i_14_n_0 ), .I1(out[4]), .I2(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I3(out[3]), .I4(wrlvl_byte_redo), .I5(out[2]), .O(\FSM_sequential_wl_state_r[1]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFDFFF)) \FSM_sequential_wl_state_r[1]_i_2 (.I0(out[3]), .I1(\FSM_sequential_wl_state_r[0]_i_3_n_0 ), .I2(\FSM_sequential_wl_state_r_reg[0]_0 ), .I3(\FSM_sequential_wl_state_r[1]_i_5_n_0 ), .I4(out[0]), .I5(out[1]), .O(\FSM_sequential_wl_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h8F8F8F8F8F808080)) \FSM_sequential_wl_state_r[1]_i_3 (.I0(\FSM_sequential_wl_state_r[1]_i_6_n_0 ), .I1(\FSM_sequential_wl_state_r[1]_i_7_n_0 ), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[1]_i_8_n_0 ), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[1]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_3_n_0 )); LUT5 #( .INIT(32'h3FAAFF00)) \FSM_sequential_wl_state_r[1]_i_4 (.I0(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I1(\FSM_sequential_wl_state_r_reg[0]_0 ), .I2(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I3(out[4]), .I4(out[3]), .O(\FSM_sequential_wl_state_r[1]_i_4_n_0 )); LUT4 #( .INIT(16'h4000)) \FSM_sequential_wl_state_r[1]_i_5 (.I0(out[2]), .I1(\wl_tap_count_r_reg_n_0_[3] ), .I2(\wl_tap_count_r_reg_n_0_[4] ), .I3(\wl_tap_count_r_reg_n_0_[5] ), .O(\FSM_sequential_wl_state_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h7F7F7F7F7F7F7FFF)) \FSM_sequential_wl_state_r[1]_i_6 (.I0(out[4]), .I1(wrlvl_byte_redo), .I2(out[2]), .I3(wrlvl_redo_corse_inc__0[1]), .I4(wrlvl_redo_corse_inc__0[0]), .I5(wrlvl_redo_corse_inc__0[2]), .O(\FSM_sequential_wl_state_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'h0007FFFF00070000)) \FSM_sequential_wl_state_r[1]_i_7 (.I0(out[3]), .I1(wr_level_done_r5), .I2(out[4]), .I3(out[2]), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[1]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'hAAA8FFFFAAA8AAA8)) \FSM_sequential_wl_state_r[1]_i_8 (.I0(out[4]), .I1(\corse_dec[3][2]_i_2_n_0 ), .I2(\corse_dec[3][2]_i_3_n_0 ), .I3(\corse_dec[3][2]_i_4_n_0 ), .I4(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I5(out[3]), .O(\FSM_sequential_wl_state_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'hAAA2A0A0AAA20000)) \FSM_sequential_wl_state_r[1]_i_9 (.I0(out[2]), .I1(stable_cnt227_in), .I2(out[3]), .I3(stable_cnt1), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_9_n_0 )); LUT5 #( .INIT(32'hAAA8A8A8)) \FSM_sequential_wl_state_r[2]_i_1 (.I0(\FSM_sequential_wl_state_r[2]_i_2_n_0 ), .I1(\FSM_sequential_wl_state_r[2]_i_3_n_0 ), .I2(\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ), .I3(\FSM_sequential_wl_state_r[2]_i_5_n_0 ), .I4(out[2]), .O(\FSM_sequential_wl_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_wl_state_r[2]_i_10 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(\fine_inc[3][5]_i_8_n_0 ), .I4(\fine_inc[3][4]_i_3_n_0 ), .I5(\fine_inc[3][4]_i_4_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_10_n_0 )); LUT6 #( .INIT(64'h1000100010001010)) \FSM_sequential_wl_state_r[2]_i_11 (.I0(out[3]), .I1(out[0]), .I2(out[2]), .I3(out[4]), .I4(stable_cnt227_in), .I5(stable_cnt1), .O(\FSM_sequential_wl_state_r[2]_i_11_n_0 )); LUT5 #( .INIT(32'h00200000)) \FSM_sequential_wl_state_r[2]_i_12 (.I0(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I1(out[1]), .I2(out[0]), .I3(out[4]), .I4(wrlvl_byte_redo), .O(\FSM_sequential_wl_state_r[2]_i_12_n_0 )); LUT5 #( .INIT(32'h10101F10)) \FSM_sequential_wl_state_r[2]_i_13 (.I0(\FSM_sequential_wl_state_r_reg[0]_0 ), .I1(out[0]), .I2(out[4]), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_13_n_0 )); LUT6 #( .INIT(64'h0B3B0B0B3B3B3B3B)) \FSM_sequential_wl_state_r[2]_i_14 (.I0(out[0]), .I1(out[3]), .I2(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I3(wr_level_done_r5), .I4(wl_sm_start), .I5(out[4]), .O(\FSM_sequential_wl_state_r[2]_i_14_n_0 )); LUT6 #( .INIT(64'h011F077F077F077F)) \FSM_sequential_wl_state_r[2]_i_15 (.I0(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .I1(wrlvl_redo_corse_inc__0[1]), .I2(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .I3(wrlvl_redo_corse_inc__0[2]), .I4(wrlvl_redo_corse_inc__0[0]), .I5(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFF7FFF00000000)) \FSM_sequential_wl_state_r[2]_i_2 (.I0(\FSM_sequential_wl_state_r[2]_i_6_n_0 ), .I1(out[4]), .I2(out[0]), .I3(wrlvl_byte_redo), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[2]_i_7_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAAE)) \FSM_sequential_wl_state_r[2]_i_3 (.I0(\FSM_sequential_wl_state_r[2]_i_8_n_0 ), .I1(out[2]), .I2(\FSM_sequential_wl_state_r[2]_i_9_n_0 ), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I5(\FSM_sequential_wl_state_r[2]_i_11_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hBFAFBFAFB0AFB0A0)) \FSM_sequential_wl_state_r[2]_i_5 (.I0(out[4]), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(wrlvl_byte_redo), .I5(\FSM_sequential_wl_state_r[2]_i_14_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair333" *) LUT3 #( .INIT(8'h01)) \FSM_sequential_wl_state_r[2]_i_6 (.I0(wrlvl_redo_corse_inc__0[1]), .I1(wrlvl_redo_corse_inc__0[0]), .I2(wrlvl_redo_corse_inc__0[2]), .O(\FSM_sequential_wl_state_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFDFFDFFFFFFFF)) \FSM_sequential_wl_state_r[2]_i_7 (.I0(out[0]), .I1(\FSM_sequential_wl_state_r[2]_i_15_n_0 ), .I2(out[2]), .I3(out[1]), .I4(out[4]), .I5(wrlvl_byte_redo), .O(\FSM_sequential_wl_state_r[2]_i_7_n_0 )); LUT6 #( .INIT(64'h0500000035330000)) \FSM_sequential_wl_state_r[2]_i_8 (.I0(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I1(out[4]), .I2(out[0]), .I3(out[3]), .I4(out[1]), .I5(out[2]), .O(\FSM_sequential_wl_state_r[2]_i_8_n_0 )); LUT5 #( .INIT(32'h8888F888)) \FSM_sequential_wl_state_r[2]_i_9 (.I0(out[0]), .I1(out[3]), .I2(dqs_count_r[1]), .I3(dqs_count_r[0]), .I4(dqs_count_r[2]), .O(\FSM_sequential_wl_state_r[2]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFEFEAEFEAEFEA)) \FSM_sequential_wl_state_r[3]_i_1 (.I0(\FSM_sequential_wl_state_r[3]_i_2_n_0 ), .I1(\FSM_sequential_wl_state_r[3]_i_3_n_0 ), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[3]_i_4_n_0 ), .I4(out[3]), .I5(\FSM_sequential_wl_state_r[3]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_wl_state_r[3]_i_10 (.I0(fine_dec_cnt__0[5]), .I1(fine_dec_cnt__0[3]), .I2(fine_dec_cnt__0[1]), .I3(fine_dec_cnt__0[0]), .I4(fine_dec_cnt__0[2]), .I5(fine_dec_cnt__0[4]), .O(\FSM_sequential_wl_state_r[3]_i_10_n_0 )); LUT6 #( .INIT(64'h0100010005AA0500)) \FSM_sequential_wl_state_r[3]_i_2 (.I0(out[1]), .I1(\FSM_sequential_wl_state_r[3]_i_6_n_0 ), .I2(out[2]), .I3(out[3]), .I4(out[0]), .I5(out[4]), .O(\FSM_sequential_wl_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6200000062626262)) \FSM_sequential_wl_state_r[3]_i_3 (.I0(out[4]), .I1(out[1]), .I2(wr_level_done_r5), .I3(\FSM_sequential_wl_state_r[3]_i_7_n_0 ), .I4(\FSM_sequential_wl_state_r[3]_i_8_n_0 ), .I5(out[2]), .O(\FSM_sequential_wl_state_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'h00400000)) \FSM_sequential_wl_state_r[3]_i_4 (.I0(stable_cnt1), .I1(out[1]), .I2(out[2]), .I3(out[4]), .I4(stable_cnt227_in), .O(\FSM_sequential_wl_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'h33BB338830883088)) \FSM_sequential_wl_state_r[3]_i_5 (.I0(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I1(out[0]), .I2(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[3]_i_7_n_0 ), .I5(out[2]), .O(\FSM_sequential_wl_state_r[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair310" *) LUT5 #( .INIT(32'h5555D555)) \FSM_sequential_wl_state_r[3]_i_6 (.I0(\FSM_sequential_wl_state_r_reg[0]_0 ), .I1(\wl_tap_count_r_reg_n_0_[5] ), .I2(\wl_tap_count_r_reg_n_0_[4] ), .I3(\wl_tap_count_r_reg_n_0_[3] ), .I4(\rd_data_edge_detect_r[3]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair315" *) LUT4 #( .INIT(16'hFFF7)) \FSM_sequential_wl_state_r[3]_i_7 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(dqs_count_r[2]), .O(\FSM_sequential_wl_state_r[3]_i_7_n_0 )); LUT5 #( .INIT(32'h00005100)) \FSM_sequential_wl_state_r[3]_i_8 (.I0(wrlvl_byte_redo), .I1(wl_sm_start), .I2(wr_level_done_r5), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I4(out[1]), .O(\FSM_sequential_wl_state_r[3]_i_8_n_0 )); LUT3 #( .INIT(8'h01)) \FSM_sequential_wl_state_r[3]_i_9 (.I0(\corse_inc[3][0]_i_2_n_0 ), .I1(\corse_inc[3][2]_i_4_n_0 ), .I2(\corse_inc[3][2]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[3]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF03031D1C)) \FSM_sequential_wl_state_r[4]_i_1 (.I0(out[0]), .I1(out[4]), .I2(out[2]), .I3(\FSM_sequential_wl_state_r[4]_i_3_n_0 ), .I4(out[1]), .I5(\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hE0FFFF00E000FF00)) \FSM_sequential_wl_state_r[4]_i_10 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo_reg), .I2(out[4]), .I3(out[0]), .I4(out[2]), .I5(\FSM_sequential_wl_state_r[4]_i_12_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_10_n_0 )); LUT4 #( .INIT(16'hF8FA)) \FSM_sequential_wl_state_r[4]_i_11 (.I0(wr_level_done_r5), .I1(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I2(out[1]), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair318" *) LUT4 #( .INIT(16'h0010)) \FSM_sequential_wl_state_r[4]_i_12 (.I0(incdec_wait_cnt_reg__0[1]), .I1(incdec_wait_cnt_reg__0[0]), .I2(incdec_wait_cnt_reg__0[3]), .I3(incdec_wait_cnt_reg__0[2]), .O(\FSM_sequential_wl_state_r[4]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFF080403070804)) \FSM_sequential_wl_state_r[4]_i_2 (.I0(out[0]), .I1(out[2]), .I2(out[3]), .I3(out[1]), .I4(out[4]), .I5(\FSM_sequential_wl_state_r[4]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h08FF080808080808)) \FSM_sequential_wl_state_r[4]_i_3 (.I0(early1_data_reg), .I1(wrlvl_byte_redo), .I2(wrlvl_byte_redo_r), .I3(wr_level_done_r1_reg_0), .I4(wl_sm_start), .I5(wr_level_start_r), .O(\FSM_sequential_wl_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'h000000000F0FBBB0)) \FSM_sequential_wl_state_r[4]_i_5 (.I0(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I1(out[3]), .I2(out[1]), .I3(\FSM_sequential_wl_state_r_reg[0]_0 ), .I4(out[0]), .I5(\FSM_sequential_wl_state_r[4]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hF0F0FFFCF0F02020)) \FSM_sequential_wl_state_r[4]_i_7 (.I0(out[2]), .I1(out[4]), .I2(wl_sm_start), .I3(wrlvl_byte_redo), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[4]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_7_n_0 )); LUT6 #( .INIT(64'h22222020FFF000FF)) \FSM_sequential_wl_state_r[4]_i_8 (.I0(\FSM_sequential_wl_state_r[4]_i_11_n_0 ), .I1(out[4]), .I2(\FSM_sequential_wl_state_r[4]_i_12_n_0 ), .I3(out[1]), .I4(out[0]), .I5(out[2]), .O(\FSM_sequential_wl_state_r[4]_i_8_n_0 )); LUT5 #( .INIT(32'h00005545)) \FSM_sequential_wl_state_r[4]_i_9 (.I0(out[3]), .I1(wr_level_done_r5), .I2(wl_sm_start), .I3(wrlvl_byte_redo), .I4(out[1]), .O(\FSM_sequential_wl_state_r[4]_i_9_n_0 )); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_wl_state_r_reg[0] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[0]_i_1_n_0 ), .Q(out[0]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_wl_state_r_reg[0]_i_12 (.I0(\FSM_sequential_wl_state_r[0]_i_15_n_0 ), .I1(\FSM_sequential_wl_state_r[0]_i_16_n_0 ), .O(\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ), .S(out[0])); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_wl_state_r_reg[1] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[1]_i_1_n_0 ), .Q(out[1]), .R(rstdiv0_sync_r1_reg_rep__19)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_wl_state_r_reg[2] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[2]_i_1_n_0 ), .Q(out[2]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_wl_state_r_reg[2]_i_4 (.I0(\FSM_sequential_wl_state_r[2]_i_12_n_0 ), .I1(\FSM_sequential_wl_state_r[2]_i_13_n_0 ), .O(\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ), .S(out[3])); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_wl_state_r_reg[3] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[3]_i_1_n_0 ), .Q(out[3]), .R(rstdiv0_sync_r1_reg_rep__19)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_wl_state_r_reg[4] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[4]_i_2_n_0 ), .Q(out[4]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_wl_state_r_reg[4]_i_4 (.I0(\FSM_sequential_wl_state_r[4]_i_7_n_0 ), .I1(\FSM_sequential_wl_state_r[4]_i_8_n_0 ), .O(\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ), .S(out[3])); (* SOFT_HLUTNM = "soft_lutpair345" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[0][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[0][2]_i_3_n_0 ), .I2(\corse_cnt_reg_n_0_[0][0] ), .O(\corse_cnt[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00F000F088F8FFF8)) \corse_cnt[0][0]_i_2 (.I0(\corse_cnt[0][0]_i_3_n_0 ), .I1(out[0]), .I2(\corse_cnt[0][0]_i_4_n_0 ), .I3(out[2]), .I4(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I5(out[3]), .O(corse_cnt[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][0]_i_3 (.I0(\final_coarse_tap_reg_n_0_[3][0] ), .I1(\final_coarse_tap_reg_n_0_[1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\final_coarse_tap_reg_n_0_[2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\final_coarse_tap_reg_n_0_[0][0] ), .O(\corse_cnt[0][0]_i_3_n_0 )); LUT4 #( .INIT(16'h8830)) \corse_cnt[0][0]_i_4 (.I0(p_0_in), .I1(out[0]), .I2(final_coarse_tap), .I3(out[1]), .O(\corse_cnt[0][0]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][0]_i_5 (.I0(\final_coarse_tap_reg_n_0_[3][0] ), .I1(\final_coarse_tap_reg_n_0_[1][0] ), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\final_coarse_tap_reg_n_0_[2][0] ), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\final_coarse_tap_reg_n_0_[0][0] ), .O(final_coarse_tap)); (* SOFT_HLUTNM = "soft_lutpair334" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[0][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[0][2]_i_3_n_0 ), .I2(\corse_cnt_reg_n_0_[0][1] ), .O(\corse_cnt[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFF080808FF08)) \corse_cnt[0][1]_i_2 (.I0(\corse_cnt[0][1]_i_3_n_0 ), .I1(out[0]), .I2(out[3]), .I3(\corse_cnt[0][1]_i_4_n_0 ), .I4(out[2]), .I5(\corse_cnt[0][1]_i_5_n_0 ), .O(corse_cnt[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][1]_i_3 (.I0(\final_coarse_tap_reg_n_0_[3][1] ), .I1(\final_coarse_tap_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\final_coarse_tap_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\final_coarse_tap_reg_n_0_[0][1] ), .O(\corse_cnt[0][1]_i_3_n_0 )); LUT4 #( .INIT(16'h8830)) \corse_cnt[0][1]_i_4 (.I0(p_0_in), .I1(out[0]), .I2(\wrlvl_redo_corse_inc_reg[2]_0 [0]), .I3(out[1]), .O(\corse_cnt[0][1]_i_4_n_0 )); LUT3 #( .INIT(8'h06)) \corse_cnt[0][1]_i_5 (.I0(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I1(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .I2(out[3]), .O(\corse_cnt[0][1]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair335" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[0][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[0][2]_i_3_n_0 ), .I2(\corse_cnt_reg_n_0_[0][2] ), .O(\corse_cnt[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00010000)) \corse_cnt[0][2]_i_10 (.I0(out[1]), .I1(dqs_count_r[2]), .I2(dqs_count_r[1]), .I3(dqs_count_r[0]), .I4(wrlvl_final_mux), .I5(out[3]), .O(\corse_cnt[0][2]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFF080808FF08)) \corse_cnt[0][2]_i_2 (.I0(\corse_cnt[0][2]_i_4_n_0 ), .I1(out[0]), .I2(out[3]), .I3(\corse_cnt[0][2]_i_5_n_0 ), .I4(out[2]), .I5(\corse_cnt[0][2]_i_6_n_0 ), .O(corse_cnt[2])); LUT6 #( .INIT(64'h0040004055400040)) \corse_cnt[0][2]_i_3 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[0][2]_i_8_n_0 ), .I2(\corse_cnt[0][2]_i_9_n_0 ), .I3(out[0]), .I4(\corse_cnt[0][2]_i_10_n_0 ), .I5(out[2]), .O(\corse_cnt[0][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][2]_i_4 (.I0(\final_coarse_tap_reg_n_0_[3][2] ), .I1(\final_coarse_tap_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\final_coarse_tap_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\final_coarse_tap_reg_n_0_[0][2] ), .O(\corse_cnt[0][2]_i_4_n_0 )); LUT4 #( .INIT(16'h8830)) \corse_cnt[0][2]_i_5 (.I0(p_0_in), .I1(out[0]), .I2(\wrlvl_redo_corse_inc_reg[2]_0 [1]), .I3(out[1]), .O(\corse_cnt[0][2]_i_5_n_0 )); LUT4 #( .INIT(16'h0078)) \corse_cnt[0][2]_i_6 (.I0(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .I1(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I2(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .I3(out[3]), .O(\corse_cnt[0][2]_i_6_n_0 )); LUT3 #( .INIT(8'hBC)) \corse_cnt[0][2]_i_7 (.I0(p_0_in), .I1(out[3]), .I2(out[4]), .O(\corse_cnt[0][2]_i_7_n_0 )); LUT6 #( .INIT(64'h202020202F202020)) \corse_cnt[0][2]_i_8 (.I0(\fine_inc[0][5]_i_3_n_0 ), .I1(\dqs_count_r[0]_i_8_n_0 ), .I2(out[2]), .I3(\po_stg2_wrcal_cnt_reg[0] ), .I4(done_dqs_dec239_out), .I5(\po_stg2_wrcal_cnt_reg[2] [1]), .O(\corse_cnt[0][2]_i_8_n_0 )); LUT2 #( .INIT(4'h1)) \corse_cnt[0][2]_i_9 (.I0(out[3]), .I1(out[1]), .O(\corse_cnt[0][2]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair332" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[1][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[1][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[1][0] ), .O(\corse_cnt[1][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair336" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[1][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[1][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[1][1] ), .O(\corse_cnt[1][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair337" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[1][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[1][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[1][2] ), .O(\corse_cnt[1][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0040004055400040)) \corse_cnt[1][2]_i_2 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[1][2]_i_3_n_0 ), .I2(\corse_cnt[0][2]_i_9_n_0 ), .I3(out[0]), .I4(\corse_cnt[1][2]_i_4_n_0 ), .I5(out[2]), .O(\corse_cnt[1][2]_i_2_n_0 )); LUT6 #( .INIT(64'h8A008A008A008AFF)) \corse_cnt[1][2]_i_3 (.I0(\fine_inc[1][5]_i_3_n_0 ), .I1(wrlvl_byte_redo), .I2(wr_level_done_r5), .I3(out[2]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\po_stg2_wrcal_cnt_reg[2]_0 ), .O(\corse_cnt[1][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00100000)) \corse_cnt[1][2]_i_4 (.I0(out[1]), .I1(dqs_count_r[2]), .I2(dqs_count_r[0]), .I3(dqs_count_r[1]), .I4(wrlvl_final_mux), .I5(out[3]), .O(\corse_cnt[1][2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair345" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[2][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[2][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[2][0] ), .O(\corse_cnt[2][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair336" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[2][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[2][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[2][1] ), .O(\corse_cnt[2][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair335" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[2][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[2][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[2][2] ), .O(\corse_cnt[2][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0040004055400040)) \corse_cnt[2][2]_i_2 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[2][2]_i_3_n_0 ), .I2(\corse_cnt[0][2]_i_9_n_0 ), .I3(out[0]), .I4(\corse_cnt[2][2]_i_4_n_0 ), .I5(out[2]), .O(\corse_cnt[2][2]_i_2_n_0 )); LUT6 #( .INIT(64'h202020202020202F)) \corse_cnt[2][2]_i_3 (.I0(\fine_inc[2][5]_i_3_n_0 ), .I1(\dqs_count_r[0]_i_8_n_0 ), .I2(out[2]), .I3(\po_stg2_wrcal_cnt_reg[2] [2]), .I4(\po_stg2_wrcal_cnt_reg[2] [0]), .I5(\po_stg2_wrcal_cnt_reg[1] ), .O(\corse_cnt[2][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00100000)) \corse_cnt[2][2]_i_4 (.I0(out[1]), .I1(dqs_count_r[2]), .I2(dqs_count_r[1]), .I3(dqs_count_r[0]), .I4(wrlvl_final_mux), .I5(out[3]), .O(\corse_cnt[2][2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair332" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[3][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[3][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[3][0] ), .O(\corse_cnt[3][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair334" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[3][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[3][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[3][1] ), .O(\corse_cnt[3][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair337" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[3][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[3][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[3][2] ), .O(\corse_cnt[3][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000455550004)) \corse_cnt[3][2]_i_2 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[3][2]_i_3_n_0 ), .I2(out[3]), .I3(out[1]), .I4(out[0]), .I5(\corse_cnt[3][2]_i_4_n_0 ), .O(\corse_cnt[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'h8A008A008AFF8A00)) \corse_cnt[3][2]_i_3 (.I0(\fine_inc[3][5]_i_5_n_0 ), .I1(wrlvl_byte_redo), .I2(wr_level_done_r5), .I3(out[2]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\po_stg2_wrcal_cnt_reg[2]_0 ), .O(\corse_cnt[3][2]_i_3_n_0 )); LUT5 #( .INIT(32'hBBBBEFFF)) \corse_cnt[3][2]_i_4 (.I0(out[2]), .I1(out[3]), .I2(wrlvl_final_mux), .I3(\fine_inc[3][5]_i_5_n_0 ), .I4(out[1]), .O(\corse_cnt[3][2]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \corse_cnt_reg[0][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[0][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[0][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[0][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[0][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[0][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[1][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[1][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[1][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[1][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[1][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[1][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[2][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[2][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[2][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[2][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[2][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[2][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[3][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[3][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[3][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[3][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \corse_cnt_reg[3][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[3][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[0][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[0][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[0][0] ), .O(\corse_dec[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[0][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[0][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[0][1] ), .O(\corse_dec[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[0][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[0][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[0][2] ), .O(\corse_dec[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[0][2]_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[0][5]_i_3_n_0 ), .O(\corse_dec[0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[1][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[1][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[1][0] ), .O(\corse_dec[1][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[1][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[1][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[1][1] ), .O(\corse_dec[1][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[1][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[1][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[1][2] ), .O(\corse_dec[1][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[1][2]_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[1][5]_i_3_n_0 ), .O(\corse_dec[1][2]_i_2_n_0 )); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[2][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[2][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[2][0] ), .O(\corse_dec[2][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[2][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[2][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[2][1] ), .O(\corse_dec[2][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[2][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[2][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[2][2] ), .O(\corse_dec[2][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[2][2]_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[2][5]_i_3_n_0 ), .O(\corse_dec[2][2]_i_2_n_0 )); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[3][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[3][2]_i_5_n_0 ), .I5(\corse_dec_reg_n_0_[3][0] ), .O(\corse_dec[3][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[3][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[3][2]_i_5_n_0 ), .I5(\corse_dec_reg_n_0_[3][1] ), .O(\corse_dec[3][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[3][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[3][2]_i_5_n_0 ), .I5(\corse_dec_reg_n_0_[3][2] ), .O(\corse_dec[3][2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_dec[3][2]_i_2 (.I0(\corse_dec_reg_n_0_[3][0] ), .I1(\corse_dec_reg_n_0_[1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_dec_reg_n_0_[2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_dec_reg_n_0_[0][0] ), .O(\corse_dec[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_dec[3][2]_i_3 (.I0(\corse_dec_reg_n_0_[3][2] ), .I1(\corse_dec_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_dec_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_dec_reg_n_0_[0][2] ), .O(\corse_dec[3][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_dec[3][2]_i_4 (.I0(\corse_dec_reg_n_0_[3][1] ), .I1(\corse_dec_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_dec_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_dec_reg_n_0_[0][1] ), .O(\corse_dec[3][2]_i_4_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[3][2]_i_5 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[3][5]_i_5_n_0 ), .O(\corse_dec[3][2]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \corse_dec_reg[0][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[0][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[0][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[0][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[0][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[0][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[0][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[0][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[0][2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[1][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[1][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[1][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[1][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[1][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[1][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[1][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[1][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[1][2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[2][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[2][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[2][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[2][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[2][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[2][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[2][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[2][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[2][2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[3][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[3][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[3][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[3][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[3][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[3][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_dec_reg[3][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[3][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[3][2] ), .R(SR[0])); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[0][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[0][0] ), .I3(out[0]), .I4(\corse_inc[0][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[0][0] ), .O(\corse_inc[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[0][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[0][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[0][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[0][1] ), .O(\corse_inc[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[0][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[0][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[0][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[0][2] ), .O(\corse_inc[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[0][2]_i_2 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[0][2]_i_3_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \corse_inc[0][2]_i_3 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[0][2]_i_3_n_0 )); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[1][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[1][0] ), .I3(out[0]), .I4(\corse_inc[1][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[1][0] ), .O(\corse_inc[1][0]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[1][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[1][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[1][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[1][1] ), .O(\corse_inc[1][1]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[1][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[1][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[1][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[1][2] ), .O(\corse_inc[1][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[1][2]_i_2 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[1][2]_i_3_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[1][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \corse_inc[1][2]_i_3 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[0]), .I4(dqs_count_r[1]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[1][2]_i_3_n_0 )); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[2][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[2][0] ), .I3(out[0]), .I4(\corse_inc[2][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[2][0] ), .O(\corse_inc[2][0]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[2][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[2][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[2][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[2][1] ), .O(\corse_inc[2][1]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[2][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[2][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[2][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[2][2] ), .O(\corse_inc[2][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[2][2]_i_2 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[2][2]_i_3_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[2][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \corse_inc[2][2]_i_3 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[2][2]_i_3_n_0 )); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[3][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[3][0] ), .I3(out[0]), .I4(\corse_inc[3][2]_i_3_n_0 ), .I5(\corse_inc_reg_n_0_[3][0] ), .O(\corse_inc[3][0]_i_1_n_0 )); LUT6 #( .INIT(64'hF0FFF000AACCAACC)) \corse_inc[3][0]_i_2 (.I0(\corse_inc_reg_n_0_[2][0] ), .I1(\corse_inc_reg_n_0_[0][0] ), .I2(\corse_inc_reg_n_0_[3][0] ), .I3(\dqs_count_r_reg[1]_rep_n_0 ), .I4(\corse_inc_reg_n_0_[1][0] ), .I5(\dqs_count_r_reg[0]_rep_n_0 ), .O(\corse_inc[3][0]_i_2_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[3][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[3][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[3][2]_i_3_n_0 ), .I5(\corse_inc_reg_n_0_[3][1] ), .O(\corse_inc[3][1]_i_1_n_0 )); LUT3 #( .INIT(8'h09)) \corse_inc[3][1]_i_2 (.I0(\corse_inc[3][0]_i_2_n_0 ), .I1(\corse_inc[3][2]_i_4_n_0 ), .I2(out[4]), .O(\corse_inc[3][1]_i_2_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[3][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[3][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[3][2]_i_3_n_0 ), .I5(\corse_inc_reg_n_0_[3][2] ), .O(\corse_inc[3][2]_i_1_n_0 )); LUT4 #( .INIT(16'h00E1)) \corse_inc[3][2]_i_2 (.I0(\corse_inc[3][2]_i_4_n_0 ), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\corse_inc[3][2]_i_5_n_0 ), .I3(out[4]), .O(\corse_inc[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[3][2]_i_3 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[3][2]_i_7_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[3][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_inc[3][2]_i_4 (.I0(\corse_inc_reg_n_0_[3][1] ), .I1(\corse_inc_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_inc_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_inc_reg_n_0_[0][1] ), .O(\corse_inc[3][2]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_inc[3][2]_i_5 (.I0(\corse_inc_reg_n_0_[3][2] ), .I1(\corse_inc_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_inc_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_inc_reg_n_0_[0][2] ), .O(\corse_inc[3][2]_i_5_n_0 )); LUT3 #( .INIT(8'h02)) \corse_inc[3][2]_i_6 (.I0(out[2]), .I1(out[4]), .I2(out[1]), .O(\corse_inc[3][2]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000002000000)) \corse_inc[3][2]_i_7 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[3][2]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \corse_inc_reg[0][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[0][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[0][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[0][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[0][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[0][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[0][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[0][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[0][2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[1][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[1][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[1][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[1][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[1][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[1][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[1][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[1][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[1][2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[2][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[2][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[2][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[2][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[2][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[2][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[2][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[2][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[2][2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[3][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[3][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[3][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[3][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[3][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[3][1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \corse_inc_reg[3][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[3][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[3][2] ), .R(SR[0])); LUT3 #( .INIT(8'hBF)) \ctl_lane_cnt[2]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(dqs_po_dec_done), .I2(pi_fine_dly_dec_done), .O(p_1_in)); LUT5 #( .INIT(32'h77770777)) dq_cnt_inc_i_2 (.I0(wrlvl_byte_redo), .I1(out[3]), .I2(dqs_count_r[0]), .I3(dqs_count_r[1]), .I4(dqs_count_r[2]), .O(dq_cnt_inc_reg_0)); FDSE #( .INIT(1'b1)) dq_cnt_inc_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[1]_0 ), .Q(p_0_in), .S(SR[0])); LUT6 #( .INIT(64'hF444FFFFF4440000)) \dqs_count_r[0]_i_1 (.I0(out[4]), .I1(\dqs_count_r_reg[0]_i_2_n_0 ), .I2(\dqs_count_r_reg[0]_i_3_n_0 ), .I3(out[0]), .I4(\dqs_count_r[2]_i_5_n_0 ), .I5(\dqs_count_r_reg[0]_rep_n_0 ), .O(\dqs_count_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hCACC0A00CACCCACC)) \dqs_count_r[0]_i_4 (.I0(\po_stg2_wrcal_cnt_reg[2] [0]), .I1(\dqs_count_r_reg[0]_rep_n_0 ), .I2(wrlvl_byte_redo_r), .I3(wrlvl_byte_redo), .I4(wrlvl_final_r), .I5(wrlvl_final_mux), .O(\dqs_count_r[0]_i_4_n_0 )); LUT6 #( .INIT(64'hBFBFBFB0000F000F)) \dqs_count_r[0]_i_5 (.I0(wr_level_done_r5), .I1(wr_level_done_r4), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I4(\fine_inc[3][5]_i_5_n_0 ), .I5(dqs_count_r[0]), .O(\dqs_count_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFBFFF80000FF03FF)) \dqs_count_r[0]_i_6 (.I0(p_0_in), .I1(out[1]), .I2(wrlvl_byte_redo), .I3(out[3]), .I4(\fine_inc[3][5]_i_5_n_0 ), .I5(dqs_count_r[0]), .O(\dqs_count_r[0]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000ADAAAAAA)) \dqs_count_r[0]_i_7 (.I0(dqs_count_r[0]), .I1(\fine_inc[3][5]_i_5_n_0 ), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I4(\dqs_count_r[0]_i_8_n_0 ), .I5(out[3]), .O(\dqs_count_r[0]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair319" *) LUT2 #( .INIT(4'h2)) \dqs_count_r[0]_i_8 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .O(\dqs_count_r[0]_i_8_n_0 )); LUT6 #( .INIT(64'hF444FFFFF4440000)) \dqs_count_r[1]_i_1 (.I0(out[4]), .I1(\dqs_count_r_reg[1]_i_2_n_0 ), .I2(\dqs_count_r_reg[1]_i_3_n_0 ), .I3(out[0]), .I4(\dqs_count_r[2]_i_5_n_0 ), .I5(\dqs_count_r_reg[1]_rep_n_0 ), .O(\dqs_count_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hCACC0A00CACCCACC)) \dqs_count_r[1]_i_4 (.I0(\po_stg2_wrcal_cnt_reg[2] [1]), .I1(dqs_count_r[1]), .I2(wrlvl_byte_redo_r), .I3(wrlvl_byte_redo), .I4(wrlvl_final_r), .I5(wrlvl_final_mux), .O(\dqs_count_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'h7477030377770000)) \dqs_count_r[1]_i_5 (.I0(dqs_count_r140_out), .I1(out[0]), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(dqs_count_r[2]), .I4(dqs_count_r[1]), .I5(dqs_count_r[0]), .O(\dqs_count_r[1]_i_5_n_0 )); LUT5 #( .INIT(32'h8BBBBB88)) \dqs_count_r[1]_i_6 (.I0(\dqs_count_r[1]_i_8_n_0 ), .I1(out[3]), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .O(\dqs_count_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000CCCCCC6E)) \dqs_count_r[1]_i_7 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .I2(dqs_count_r[2]), .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I4(\dqs_count_r[2]_i_11_n_0 ), .I5(out[3]), .O(\dqs_count_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'hF8FB0300FBFB0300)) \dqs_count_r[1]_i_8 (.I0(p_0_in), .I1(out[1]), .I2(wrlvl_byte_redo), .I3(dqs_count_r[0]), .I4(dqs_count_r[1]), .I5(dqs_count_r[2]), .O(\dqs_count_r[1]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair339" *) LUT2 #( .INIT(4'h7)) \dqs_count_r[2]_i_10 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .O(\dqs_count_r[2]_i_10_n_0 )); LUT3 #( .INIT(8'hBF)) \dqs_count_r[2]_i_11 (.I0(wrlvl_byte_redo), .I1(wr_level_done_r5), .I2(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\dqs_count_r[2]_i_11_n_0 )); LUT6 #( .INIT(64'hF444FFFFF4440000)) \dqs_count_r[2]_i_2 (.I0(out[4]), .I1(\dqs_count_r_reg[2]_i_3_n_0 ), .I2(\dqs_count_r_reg[2]_i_4_n_0 ), .I3(out[0]), .I4(\dqs_count_r[2]_i_5_n_0 ), .I5(dqs_count_r[2]), .O(\dqs_count_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'h00805889)) \dqs_count_r[2]_i_5 (.I0(out[4]), .I1(out[0]), .I2(out[3]), .I3(out[2]), .I4(out[1]), .O(\dqs_count_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'hFB080808FB08FB08)) \dqs_count_r[2]_i_6 (.I0(\po_stg2_wrcal_cnt_reg[2] [2]), .I1(wrlvl_byte_redo), .I2(wrlvl_byte_redo_r), .I3(dqs_count_r[2]), .I4(wrlvl_final_r), .I5(wrlvl_final_mux), .O(\dqs_count_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'h7040707070707070)) \dqs_count_r[2]_i_7 (.I0(dqs_count_r140_out), .I1(out[0]), .I2(dqs_count_r[2]), .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I4(dqs_count_r[0]), .I5(dqs_count_r[1]), .O(\dqs_count_r[2]_i_7_n_0 )); LUT6 #( .INIT(64'hFBFFF80000000000)) \dqs_count_r[2]_i_8 (.I0(p_0_in), .I1(out[1]), .I2(wrlvl_byte_redo), .I3(out[3]), .I4(\dqs_count_r[2]_i_10_n_0 ), .I5(dqs_count_r[2]), .O(\dqs_count_r[2]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000FFBF0000)) \dqs_count_r[2]_i_9 (.I0(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .I3(\dqs_count_r[2]_i_11_n_0 ), .I4(dqs_count_r[2]), .I5(out[3]), .O(\dqs_count_r[2]_i_9_n_0 )); (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) FDRE #( .INIT(1'b0)) \dqs_count_r_reg[0] (.C(CLK), .CE(1'b1), .D(\dqs_count_r[0]_i_1_n_0 ), .Q(dqs_count_r[0]), .R(rstdiv0_sync_r1_reg_rep__17[1])); MUXF7 \dqs_count_r_reg[0]_i_2 (.I0(\dqs_count_r[0]_i_4_n_0 ), .I1(\dqs_count_r[0]_i_5_n_0 ), .O(\dqs_count_r_reg[0]_i_2_n_0 ), .S(out[3])); MUXF7 \dqs_count_r_reg[0]_i_3 (.I0(\dqs_count_r[0]_i_6_n_0 ), .I1(\dqs_count_r[0]_i_7_n_0 ), .O(\dqs_count_r_reg[0]_i_3_n_0 ), .S(out[2])); (* IS_FANOUT_CONSTRAINED = "1" *) (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) FDRE #( .INIT(1'b0)) \dqs_count_r_reg[0]_rep (.C(CLK), .CE(1'b1), .D(\dqs_count_r[0]_i_1_n_0 ), .Q(\dqs_count_r_reg[0]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) FDRE #( .INIT(1'b0)) \dqs_count_r_reg[1] (.C(CLK), .CE(1'b1), .D(\dqs_count_r[1]_i_1_n_0 ), .Q(dqs_count_r[1]), .R(rstdiv0_sync_r1_reg_rep__17[1])); MUXF7 \dqs_count_r_reg[1]_i_2 (.I0(\dqs_count_r[1]_i_4_n_0 ), .I1(\dqs_count_r[1]_i_5_n_0 ), .O(\dqs_count_r_reg[1]_i_2_n_0 ), .S(out[3])); MUXF7 \dqs_count_r_reg[1]_i_3 (.I0(\dqs_count_r[1]_i_6_n_0 ), .I1(\dqs_count_r[1]_i_7_n_0 ), .O(\dqs_count_r_reg[1]_i_3_n_0 ), .S(out[2])); (* IS_FANOUT_CONSTRAINED = "1" *) (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) FDRE #( .INIT(1'b0)) \dqs_count_r_reg[1]_rep (.C(CLK), .CE(1'b1), .D(\dqs_count_r[1]_i_1_n_0 ), .Q(\dqs_count_r_reg[1]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* MAX_FANOUT = "50" *) FDRE #( .INIT(1'b0)) \dqs_count_r_reg[2] (.C(CLK), .CE(1'b1), .D(\dqs_count_r[2]_i_2_n_0 ), .Q(dqs_count_r[2]), .R(rstdiv0_sync_r1_reg_rep__17[1])); MUXF7 \dqs_count_r_reg[2]_i_3 (.I0(\dqs_count_r[2]_i_6_n_0 ), .I1(\dqs_count_r[2]_i_7_n_0 ), .O(\dqs_count_r_reg[2]_i_3_n_0 ), .S(out[3])); MUXF7 \dqs_count_r_reg[2]_i_4 (.I0(\dqs_count_r[2]_i_8_n_0 ), .I1(\dqs_count_r[2]_i_9_n_0 ), .O(\dqs_count_r_reg[2]_i_4_n_0 ), .S(out[2])); (* syn_maxfan = "2" *) FDRE #( .INIT(1'b0)) dqs_po_dec_done_reg (.C(CLK), .CE(1'b1), .D(po_dec_done), .Q(dqs_po_dec_done), .R(1'b0)); LUT6 #( .INIT(64'hAAAABBABAAAAAABA)) dqs_po_en_stg2_f_i_1 (.I0(dqs_po_en_stg2_f_reg_0), .I1(out[2]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .I5(out[1]), .O(dqs_po_en_stg2_f_i_1_n_0)); FDRE #( .INIT(1'b0)) dqs_po_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(dqs_po_en_stg2_f_i_1_n_0), .Q(dqs_po_en_stg2_f), .R(rstdiv0_sync_r1_reg_rep__17[0])); LUT3 #( .INIT(8'h02)) dqs_po_stg2_f_incdec_i_1 (.I0(dqs_po_stg2_f_incdec_i_2_n_0), .I1(dqs_po_stg2_f_incdec_i_3_n_0), .I2(rstdiv0_sync_r1_reg_rep__22), .O(dqs_po_stg2_f_incdec0)); LUT6 #( .INIT(64'h00000000FFFFFEDF)) dqs_po_stg2_f_incdec_i_2 (.I0(out[1]), .I1(out[4]), .I2(out[0]), .I3(out[3]), .I4(out[2]), .I5(dqs_po_en_stg2_f_reg_0), .O(dqs_po_stg2_f_incdec_i_2_n_0)); LUT5 #( .INIT(32'hFBFEFFFF)) dqs_po_stg2_f_incdec_i_3 (.I0(out[2]), .I1(out[0]), .I2(out[4]), .I3(out[3]), .I4(out[1]), .O(dqs_po_stg2_f_incdec_i_3_n_0)); FDRE #( .INIT(1'b0)) dqs_po_stg2_f_incdec_reg (.C(CLK), .CE(1'b1), .D(dqs_po_stg2_f_incdec0), .Q(dqs_po_stg2_f_incdec), .R(1'b0)); LUT5 #( .INIT(32'h00000002)) dqs_wl_po_stg2_c_incdec_i_1 (.I0(out[2]), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(out[4]), .O(dqs_wl_po_stg2_c_incdec_i_1_n_0)); FDRE #( .INIT(1'b0)) dqs_wl_po_stg2_c_incdec_reg (.C(CLK), .CE(1'b1), .D(dqs_wl_po_stg2_c_incdec_i_1_n_0), .Q(dqs_wl_po_stg2_c_incdec), .R(SR[0])); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[0][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][0]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[0][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[0][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][0]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[0][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[0][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][0]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[0][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[1][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][1]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[1][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[1][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][1]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[1][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[1][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][1]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[1][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[2][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][2]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[2][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[2][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][2]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[2][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[2][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][2]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[2][2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[3][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][3]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[3][0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[3][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][3]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[3][1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \final_coarse_tap_reg[3][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][3]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[3][2] ), .R(1'b0)); LUT6 #( .INIT(64'h303F000035370504)) \fine_dec_cnt[0]_i_1 (.I0(fine_dec_cnt__0[0]), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[0] ), .I5(out[4]), .O(fine_dec_cnt[0])); LUT6 #( .INIT(64'hBABFAAAABABBAAAA)) \fine_dec_cnt[1]_i_1 (.I0(\fine_dec_cnt[1]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[1] ), .I5(out[4]), .O(fine_dec_cnt[1])); LUT6 #( .INIT(64'h1001100110010000)) \fine_dec_cnt[1]_i_2 (.I0(out[4]), .I1(out[2]), .I2(fine_dec_cnt__0[1]), .I3(fine_dec_cnt__0[0]), .I4(out[1]), .I5(out[3]), .O(\fine_dec_cnt[1]_i_2_n_0 )); LUT6 #( .INIT(64'h303F000035370505)) \fine_dec_cnt[2]_i_1 (.I0(\fine_dec_cnt[2]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[2] ), .I5(out[4]), .O(fine_dec_cnt[2])); LUT5 #( .INIT(32'h1F1F1FF1)) \fine_dec_cnt[2]_i_2 (.I0(out[3]), .I1(out[1]), .I2(fine_dec_cnt__0[2]), .I3(fine_dec_cnt__0[0]), .I4(fine_dec_cnt__0[1]), .O(\fine_dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'h303F000035370505)) \fine_dec_cnt[3]_i_1 (.I0(\fine_dec_cnt[3]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[3] ), .I5(out[4]), .O(fine_dec_cnt[3])); LUT6 #( .INIT(64'h1F1F1F1F1F1F1FF1)) \fine_dec_cnt[3]_i_2 (.I0(out[3]), .I1(out[1]), .I2(fine_dec_cnt__0[3]), .I3(fine_dec_cnt__0[1]), .I4(fine_dec_cnt__0[0]), .I5(fine_dec_cnt__0[2]), .O(\fine_dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h303F00003A3B0A08)) \fine_dec_cnt[4]_i_1 (.I0(\fine_dec_cnt[4]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[4] ), .I5(out[4]), .O(fine_dec_cnt[4])); LUT5 #( .INIT(32'hFFFE0001)) \fine_dec_cnt[4]_i_2 (.I0(fine_dec_cnt__0[3]), .I1(fine_dec_cnt__0[1]), .I2(fine_dec_cnt__0[0]), .I3(fine_dec_cnt__0[2]), .I4(fine_dec_cnt__0[4]), .O(\fine_dec_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'h303F00003A3B0A08)) \fine_dec_cnt[5]_i_2 (.I0(\fine_dec_cnt[5]_i_5_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[5] ), .I5(out[4]), .O(fine_dec_cnt[5])); LUT5 #( .INIT(32'h11800080)) \fine_dec_cnt[5]_i_3 (.I0(out[2]), .I1(out[1]), .I2(\fine_dec_cnt[5]_i_6_n_0 ), .I3(out[3]), .I4(\fine_dec_cnt[5]_i_7_n_0 ), .O(\fine_dec_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'h4444040000000400)) \fine_dec_cnt[5]_i_4 (.I0(out[3]), .I1(\fine_dec_cnt[5]_i_8_n_0 ), .I2(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I3(wrlvl_byte_redo), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(\fine_dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \fine_dec_cnt[5]_i_5 (.I0(fine_dec_cnt__0[5]), .I1(fine_dec_cnt__0[3]), .I2(fine_dec_cnt__0[1]), .I3(fine_dec_cnt__0[0]), .I4(fine_dec_cnt__0[2]), .I5(fine_dec_cnt__0[4]), .O(\fine_dec_cnt[5]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000080000000)) \fine_dec_cnt[5]_i_6 (.I0(\stable_cnt_reg_n_0_[1] ), .I1(\stable_cnt_reg_n_0_[2] ), .I2(\stable_cnt_reg_n_0_[3] ), .I3(wl_sm_start), .I4(stable_cnt227_in), .I5(out[4]), .O(\fine_dec_cnt[5]_i_6_n_0 )); LUT6 #( .INIT(64'h0020FFFF00200000)) \fine_dec_cnt[5]_i_7 (.I0(\FSM_sequential_wl_state_r[0]_i_3_n_0 ), .I1(\FSM_sequential_wl_state_r[0]_i_5_n_0 ), .I2(\FSM_sequential_wl_state_r_reg[0]_0 ), .I3(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I4(out[4]), .I5(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(\fine_dec_cnt[5]_i_7_n_0 )); LUT2 #( .INIT(4'h1)) \fine_dec_cnt[5]_i_8 (.I0(out[2]), .I1(out[4]), .O(\fine_dec_cnt[5]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \fine_dec_cnt_reg[0] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[0]), .Q(fine_dec_cnt__0[0]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \fine_dec_cnt_reg[1] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[1]), .Q(fine_dec_cnt__0[1]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \fine_dec_cnt_reg[2] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[2]), .Q(fine_dec_cnt__0[2]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \fine_dec_cnt_reg[3] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[3]), .Q(fine_dec_cnt__0[3]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \fine_dec_cnt_reg[4] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[4]), .Q(fine_dec_cnt__0[4]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \fine_dec_cnt_reg[5] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[5]), .Q(fine_dec_cnt__0[5]), .R(rstdiv0_sync_r1_reg_rep__17[0])); MUXF7 \fine_dec_cnt_reg[5]_i_1 (.I0(\fine_dec_cnt[5]_i_3_n_0 ), .I1(\fine_dec_cnt[5]_i_4_n_0 ), .O(\fine_dec_cnt_reg[5]_i_1_n_0 ), .S(out[0])); LUT4 #( .INIT(16'h0074)) \fine_inc[0][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[0].final_val_reg_n_0_[0][0] ), .I3(out[4]), .O(fine_inc[0])); LUT5 #( .INIT(32'h090F0900)) \fine_inc[0][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[0].final_val_reg_n_0_[0][1] ), .O(fine_inc[1])); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[0][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[0].final_val_reg_n_0_[0][2] ), .O(fine_inc[2])); LUT5 #( .INIT(32'h060F0600)) \fine_inc[0][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[0].final_val_reg_n_0_[0][3] ), .O(fine_inc[3])); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[0][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[0].final_val_reg_n_0_[0][4] ), .O(fine_inc[4])); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[0][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[0][5]_i_3_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[0][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[0][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[0].final_val_reg_n_0_[0][5] ), .I3(out[4]), .O(fine_inc[5])); (* SOFT_HLUTNM = "soft_lutpair338" *) LUT3 #( .INIT(8'h01)) \fine_inc[0][5]_i_3 (.I0(dqs_count_r[2]), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .O(\fine_inc[0][5]_i_3_n_0 )); LUT4 #( .INIT(16'h0074)) \fine_inc[1][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[1].final_val_reg_n_0_[1][0] ), .I3(out[4]), .O(\fine_inc[1][0]_i_1_n_0 )); LUT5 #( .INIT(32'h090F0900)) \fine_inc[1][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[1].final_val_reg_n_0_[1][1] ), .O(\fine_inc[1][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[1][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[1].final_val_reg_n_0_[1][2] ), .O(\fine_inc[1][2]_i_1_n_0 )); LUT5 #( .INIT(32'h060F0600)) \fine_inc[1][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[1].final_val_reg_n_0_[1][3] ), .O(\fine_inc[1][3]_i_1_n_0 )); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[1][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[1].final_val_reg_n_0_[1][4] ), .O(\fine_inc[1][4]_i_1_n_0 )); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[1][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[1][5]_i_3_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[1][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[1][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[1].final_val_reg_n_0_[1][5] ), .I3(out[4]), .O(\fine_inc[1][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair338" *) LUT3 #( .INIT(8'h04)) \fine_inc[1][5]_i_3 (.I0(dqs_count_r[2]), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .O(\fine_inc[1][5]_i_3_n_0 )); LUT4 #( .INIT(16'h0074)) \fine_inc[2][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[2].final_val_reg_n_0_[2][0] ), .I3(out[4]), .O(\fine_inc[2][0]_i_1_n_0 )); LUT5 #( .INIT(32'h090F0900)) \fine_inc[2][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[2].final_val_reg_n_0_[2][1] ), .O(\fine_inc[2][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[2][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[2].final_val_reg_n_0_[2][2] ), .O(\fine_inc[2][2]_i_1_n_0 )); LUT5 #( .INIT(32'h060F0600)) \fine_inc[2][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[2].final_val_reg_n_0_[2][3] ), .O(\fine_inc[2][3]_i_1_n_0 )); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[2][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[2].final_val_reg_n_0_[2][4] ), .O(\fine_inc[2][4]_i_1_n_0 )); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[2][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[2][5]_i_3_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[2][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[2][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[2].final_val_reg_n_0_[2][5] ), .I3(out[4]), .O(\fine_inc[2][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair339" *) LUT3 #( .INIT(8'h04)) \fine_inc[2][5]_i_3 (.I0(dqs_count_r[2]), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .O(\fine_inc[2][5]_i_3_n_0 )); LUT4 #( .INIT(16'h0074)) \fine_inc[3][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[3].final_val_reg_n_0_[3][0] ), .I3(out[4]), .O(\fine_inc[3][0]_i_1_n_0 )); LUT5 #( .INIT(32'h090F0900)) \fine_inc[3][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[3].final_val_reg_n_0_[3][1] ), .O(\fine_inc[3][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[3][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[3].final_val_reg_n_0_[3][2] ), .O(\fine_inc[3][2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][2]_i_2 (.I0(\fine_inc_reg_n_0_[3][1] ), .I1(\fine_inc_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][1] ), .O(\fine_inc[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][2]_i_3 (.I0(\fine_inc_reg_n_0_[3][0] ), .I1(\fine_inc_reg_n_0_[1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][0] ), .O(\fine_inc[3][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][2]_i_4 (.I0(\fine_inc_reg_n_0_[3][2] ), .I1(\fine_inc_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][2] ), .O(\fine_inc[3][2]_i_4_n_0 )); LUT5 #( .INIT(32'h060F0600)) \fine_inc[3][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[3].final_val_reg_n_0_[3][3] ), .O(\fine_inc[3][3]_i_1_n_0 )); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[3][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[3].final_val_reg_n_0_[3][4] ), .O(\fine_inc[3][4]_i_1_n_0 )); LUT3 #( .INIT(8'h01)) \fine_inc[3][4]_i_2 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .O(\fine_inc[3][4]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][4]_i_3 (.I0(\fine_inc_reg_n_0_[3][3] ), .I1(\fine_inc_reg_n_0_[1][3] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][3] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][3] ), .O(\fine_inc[3][4]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][4]_i_4 (.I0(\fine_inc_reg_n_0_[3][4] ), .I1(\fine_inc_reg_n_0_[1][4] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][4] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][4] ), .O(\fine_inc[3][4]_i_4_n_0 )); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[3][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[3][5]_i_5_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[3][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[3][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[3].final_val_reg_n_0_[3][5] ), .I3(out[4]), .O(\fine_inc[3][5]_i_2_n_0 )); LUT3 #( .INIT(8'h08)) \fine_inc[3][5]_i_3 (.I0(out[0]), .I1(out[3]), .I2(out[4]), .O(\fine_inc[3][5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair342" *) LUT2 #( .INIT(4'h2)) \fine_inc[3][5]_i_4 (.I0(wr_level_done_r4), .I1(wr_level_done_r5), .O(dqs_count_r140_out)); (* SOFT_HLUTNM = "soft_lutpair315" *) LUT3 #( .INIT(8'h40)) \fine_inc[3][5]_i_5 (.I0(dqs_count_r[2]), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .O(\fine_inc[3][5]_i_5_n_0 )); LUT5 #( .INIT(32'h0100FFFF)) \fine_inc[3][5]_i_6 (.I0(\fine_inc[3][5]_i_8_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(\fine_inc[3][4]_i_2_n_0 ), .I4(wr_level_done_r5), .O(\fine_inc[3][5]_i_6_n_0 )); LUT5 #( .INIT(32'h0000FD02)) \fine_inc[3][5]_i_7 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(\fine_inc[3][5]_i_8_n_0 ), .I4(out[4]), .O(\fine_inc[3][5]_i_7_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][5]_i_8 (.I0(\fine_inc_reg_n_0_[3][5] ), .I1(\fine_inc_reg_n_0_[1][5] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][5] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][5] ), .O(\fine_inc[3][5]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \fine_inc_reg[0][0] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[0]), .Q(\fine_inc_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[0][1] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[1]), .Q(\fine_inc_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[0][2] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[2]), .Q(\fine_inc_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[0][3] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[3]), .Q(\fine_inc_reg_n_0_[0][3] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[0][4] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[4]), .Q(\fine_inc_reg_n_0_[0][4] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[0][5] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[5]), .Q(\fine_inc_reg_n_0_[0][5] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[1][0] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][0]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[1][1] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][1]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[1][2] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][2]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[1][3] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][3]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][3] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[1][4] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][4]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][4] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[1][5] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][5]_i_2_n_0 ), .Q(\fine_inc_reg_n_0_[1][5] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[2][0] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][0]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[2][1] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][1]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[2][2] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][2]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[2][3] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][3]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][3] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[2][4] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][4]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][4] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[2][5] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][5]_i_2_n_0 ), .Q(\fine_inc_reg_n_0_[2][5] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[3][0] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][0]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[3][1] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][1]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[3][2] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][2]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[3][3] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][3]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][3] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[3][4] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][4]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][4] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \fine_inc_reg[3][5] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][5]_i_2_n_0 ), .Q(\fine_inc_reg_n_0_[3][5] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); LUT5 #( .INIT(32'h00820000)) flag_ck_negedge_i_10 (.I0(out[1]), .I1(out[2]), .I2(out[3]), .I3(out[4]), .I4(out[0]), .O(flag_ck_negedge_i_10_n_0)); (* SOFT_HLUTNM = "soft_lutpair311" *) LUT3 #( .INIT(8'h7F)) flag_ck_negedge_i_2 (.I0(\stable_cnt_reg_n_0_[3] ), .I1(\stable_cnt_reg_n_0_[2] ), .I2(\stable_cnt_reg_n_0_[1] ), .O(stable_cnt1)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) flag_ck_negedge_i_3 (.I0(\rd_data_previous_r_reg_n_0_[3] ), .I1(\rd_data_previous_r_reg_n_0_[2] ), .I2(\dqs_count_r_reg[1]_rep_n_0 ), .I3(\rd_data_previous_r_reg_n_0_[1] ), .I4(\dqs_count_r_reg[0]_rep_n_0 ), .I5(\rd_data_previous_r_reg_n_0_[0] ), .O(stable_cnt227_in)); LUT6 #( .INIT(64'h0040FFFF00400040)) flag_ck_negedge_i_4 (.I0(out[1]), .I1(out[2]), .I2(flag_ck_negedge_i_6_n_0), .I3(out[3]), .I4(flag_ck_negedge_i_7_n_0), .I5(stable_cnt227_in), .O(flag_ck_negedge09_out)); LUT4 #( .INIT(16'hFFFE)) flag_ck_negedge_i_5 (.I0(\stable_cnt[3]_i_6_n_0 ), .I1(wr_level_done_r1_reg_0), .I2(flag_ck_negedge_i_8_n_0), .I3(rstdiv0_sync_r1_reg_rep__20), .O(flag_ck_negedge_reg_0)); LUT2 #( .INIT(4'h1)) flag_ck_negedge_i_6 (.I0(out[4]), .I1(out[0]), .O(flag_ck_negedge_i_6_n_0)); LUT6 #( .INIT(64'h0000000000000001)) flag_ck_negedge_i_7 (.I0(\stable_cnt_reg_n_0_[2] ), .I1(\stable_cnt_reg_n_0_[3] ), .I2(p_1_in_0), .I3(flag_ck_negedge_i_10_n_0), .I4(\stable_cnt_reg[3]_0 ), .I5(\stable_cnt_reg_n_0_[1] ), .O(flag_ck_negedge_i_7_n_0)); LUT4 #( .INIT(16'h4000)) flag_ck_negedge_i_8 (.I0(out[2]), .I1(out[3]), .I2(out[0]), .I3(out[4]), .O(flag_ck_negedge_i_8_n_0)); LUT5 #( .INIT(32'h10000000)) flag_ck_negedge_i_9 (.I0(out[4]), .I1(out[0]), .I2(out[3]), .I3(out[2]), .I4(out[1]), .O(p_1_in_0)); FDRE #( .INIT(1'b0)) flag_ck_negedge_reg (.C(CLK), .CE(1'b1), .D(flag_ck_negedge_reg_1), .Q(\rd_data_edge_detect_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAAAAAA8AAAAA)) flag_init_i_1 (.I0(flag_init), .I1(\wl_state_r1_reg_n_0_[0] ), .I2(p_1_in28_in), .I3(\wl_state_r1_reg_n_0_[4] ), .I4(\wl_state_r1_reg_n_0_[2] ), .I5(\wl_state_r1_reg_n_0_[3] ), .O(flag_init_i_1_n_0)); LUT5 #( .INIT(32'h04000000)) flag_init_i_2 (.I0(out[3]), .I1(out[0]), .I2(out[4]), .I3(out[2]), .I4(out[1]), .O(p_1_in28_in)); FDSE #( .INIT(1'b1)) flag_init_reg (.C(CLK), .CE(1'b1), .D(flag_init_i_1_n_0), .Q(flag_init), .S(rstdiv0_sync_r1_reg_rep__17[0])); LUT6 #( .INIT(64'h00000000EEEE22E2)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ), .I1(pi_f_inc_reg), .I2(dqs_count_r[0]), .I3(wrlvl_done_r_reg), .I4(oclkdelay_calib_done_r_reg_0), .I5(delay_done_r4_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'h00000000EEEE22E2)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ), .I1(pi_f_inc_reg), .I2(dqs_count_r[1]), .I3(wrlvl_done_r_reg), .I4(oclkdelay_calib_done_r_reg_1), .I5(delay_done_r4_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[1] )); LUT6 #( .INIT(64'h00000000EEE222E2)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_1 (.I0(byte_sel_cnt), .I1(pi_f_inc_reg), .I2(dqs_count_r[2]), .I3(wrlvl_done_r_reg), .I4(\prbs_dqs_cnt_r_reg[2] ), .I5(delay_done_r4_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); LUT2 #( .INIT(4'h2)) \gen_final_tap[0].final_val[0][5]_i_1 (.I0(wr_level_done_r2), .I1(wr_level_done_r3), .O(p_21_out)); FDRE #( .INIT(1'b0)) \gen_final_tap[0].final_val_reg[0][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [0]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[0].final_val_reg[0][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [1]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[0].final_val_reg[0][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [2]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[0].final_val_reg[0][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [3]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][3] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[0].final_val_reg[0][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [4]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][4] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[0].final_val_reg[0][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [5]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][5] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[1].final_val_reg[1][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [0]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[1].final_val_reg[1][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [1]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[1].final_val_reg[1][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [2]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[1].final_val_reg[1][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [3]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][3] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[1].final_val_reg[1][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [4]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][4] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[1].final_val_reg[1][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [5]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][5] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[2].final_val_reg[2][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [0]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[2].final_val_reg[2][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [1]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][1] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \gen_final_tap[2].final_val_reg[2][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [2]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][2] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \gen_final_tap[2].final_val_reg[2][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [3]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][3] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \gen_final_tap[2].final_val_reg[2][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [4]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][4] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \gen_final_tap[2].final_val_reg[2][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [5]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][5] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \gen_final_tap[3].final_val_reg[3][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [0]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[3].final_val_reg[3][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [1]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[3].final_val_reg[3][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [2]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[3].final_val_reg[3][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [3]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][3] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[3].final_val_reg[3][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [4]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][4] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_final_tap[3].final_val_reg[3][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [5]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][5] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \gen_rd[0].rd_data_rise_wl_r_reg[0] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ), .Q(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_rd[1].rd_data_rise_wl_r_reg[1] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ), .Q(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_rd[2].rd_data_rise_wl_r_reg[2] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ), .Q(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \gen_rd[3].rd_data_rise_wl_r_reg[3] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ), .Q(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .R(1'b0)); LUT1 #( .INIT(2'h1)) \incdec_wait_cnt[0]_i_1 (.I0(incdec_wait_cnt_reg__0[0]), .O(p_0_in__0__0[0])); (* SOFT_HLUTNM = "soft_lutpair347" *) LUT2 #( .INIT(4'h6)) \incdec_wait_cnt[1]_i_1 (.I0(incdec_wait_cnt_reg__0[0]), .I1(incdec_wait_cnt_reg__0[1]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair347" *) LUT3 #( .INIT(8'h6A)) \incdec_wait_cnt[2]_i_1 (.I0(incdec_wait_cnt_reg__0[2]), .I1(incdec_wait_cnt_reg__0[1]), .I2(incdec_wait_cnt_reg__0[0]), .O(p_0_in__0__0[2])); LUT6 #( .INIT(64'hFFFBFFEFFEFFFFFF)) \incdec_wait_cnt[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(out[1]), .I2(out[0]), .I3(out[4]), .I4(out[2]), .I5(out[3]), .O(\incdec_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair318" *) LUT4 #( .INIT(16'h6AAA)) \incdec_wait_cnt[3]_i_2 (.I0(incdec_wait_cnt_reg__0[3]), .I1(incdec_wait_cnt_reg__0[0]), .I2(incdec_wait_cnt_reg__0[1]), .I3(incdec_wait_cnt_reg__0[2]), .O(p_0_in__0__0[3])); FDRE #( .INIT(1'b0)) \incdec_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[0]), .Q(incdec_wait_cnt_reg__0[0]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \incdec_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[1]), .Q(incdec_wait_cnt_reg__0[1]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \incdec_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[2]), .Q(incdec_wait_cnt_reg__0[2]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \incdec_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[3]), .Q(incdec_wait_cnt_reg__0[3]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h2F203F3F2F203333)) inhibit_edge_detect_r_i_2 (.I0(wrlvl_byte_redo), .I1(out[3]), .I2(out[4]), .I3(stable_cnt227_in), .I4(out[2]), .I5(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(inhibit_edge_detect_r)); LUT6 #( .INIT(64'h0000008303080003)) inhibit_edge_detect_r_i_3 (.I0(inhibit_edge_detect_r_i_4_n_0), .I1(out[2]), .I2(out[4]), .I3(out[3]), .I4(out[1]), .I5(out[0]), .O(inhibit_edge_detect_r_reg_0)); LUT6 #( .INIT(64'h8080808080808F80)) inhibit_edge_detect_r_i_4 (.I0(wrlvl_byte_redo), .I1(\FSM_sequential_wl_state_r[2]_i_6_n_0 ), .I2(out[4]), .I3(wl_sm_start), .I4(stable_cnt1), .I5(stable_cnt227_in), .O(inhibit_edge_detect_r_i_4_n_0)); FDSE #( .INIT(1'b1)) inhibit_edge_detect_r_reg (.C(CLK), .CE(1'b1), .D(inhibit_edge_detect_r_reg_1), .Q(\rd_data_edge_detect_r_reg[0]_1 ), .S(SR[0])); LUT6 #( .INIT(64'h222222F2F2F2F2FF)) \lim_state[12]_i_6 (.I0(\stg2_target_r_reg[4] [1]), .I1(\stg2_tap_cnt_reg[2] [2]), .I2(\stg2_target_r_reg[4] [0]), .I3(\stg2_r_reg[0] ), .I4(\stg2_tap_cnt_reg[2] [0]), .I5(\stg2_tap_cnt_reg[2] [1]), .O(\lim_state_reg[12] )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ), .O(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .I3(my_empty), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .O(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I4(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ), .O(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ), .I3(my_empty_6), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .O(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .I4(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ), .O(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ), .I3(my_empty_7), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ), .I4(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ), .O(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .I3(my_empty_8), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ), .O(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 )); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 " *) SRL16E #( .INIT(16'h0000)) phy_ctl_ready_r4_reg_srl4 (.A0(1'b1), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\mcGo_r_reg[15] ), .Q(phy_ctl_ready_r4_reg_srl4_n_0)); FDRE #( .INIT(1'b0)) phy_ctl_ready_r5_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_ready_r4_reg_srl4_n_0), .Q(phy_ctl_ready_r5), .R(1'b0)); FDRE #( .INIT(1'b0)) phy_ctl_ready_r6_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_ready_r5), .Q(phy_ctl_ready_r6_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair313" *) LUT5 #( .INIT(32'hFFFFFDFF)) po_cnt_dec_i_2 (.I0(wait_cnt_reg__0[0]), .I1(wait_cnt_reg__0[1]), .I2(wait_cnt_reg__0[3]), .I3(phy_ctl_ready_r6_reg_n_0), .I4(wait_cnt_reg__0[2]), .O(po_cnt_dec_reg_0)); FDRE #( .INIT(1'b0)) po_cnt_dec_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_reg[0]_0 ), .Q(dqs_po_en_stg2_f_reg_0), .R(1'b0)); LUT3 #( .INIT(8'hF4)) po_dec_done_i_1 (.I0(po_dec_done_i_2_n_0), .I1(po_dec_done_i_3_n_0), .I2(po_dec_done), .O(po_dec_done_i_1_n_0)); LUT5 #( .INIT(32'hEEEFFFEF)) po_dec_done_i_2 (.I0(po_rdval_cnt[2]), .I1(po_rdval_cnt[1]), .I2(phy_ctl_ready_r6_reg_n_0), .I3(po_rdval_cnt[0]), .I4(dqs_po_en_stg2_f_reg_0), .O(po_dec_done_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000001)) po_dec_done_i_3 (.I0(po_rdval_cnt[7]), .I1(po_rdval_cnt[3]), .I2(po_rdval_cnt[4]), .I3(po_rdval_cnt[5]), .I4(po_rdval_cnt[6]), .I5(po_rdval_cnt[8]), .O(po_dec_done_i_3_n_0)); FDRE #( .INIT(1'b0)) po_dec_done_reg (.C(CLK), .CE(1'b1), .D(po_dec_done_i_1_n_0), .Q(po_dec_done), .R(rstdiv0_sync_r1_reg_rep__17[0])); LUT6 #( .INIT(64'hAC00AC00ACFFAC00)) \po_rdval_cnt[0]_i_1 (.I0(\po_counter_read_val_reg[8] [0]), .I1(\po_counter_read_val_reg[8]_0 [0]), .I2(\calib_sel_reg[3] ), .I3(\po_rdval_cnt[8]_i_4_n_0 ), .I4(\po_rdval_cnt_reg[0]_0 ), .I5(po_rdval_cnt[0]), .O(\po_rdval_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFB0808080808FB08)) \po_rdval_cnt[1]_i_1 (.I0(\po_counter_read_val_reg[5] [0]), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(\po_rdval_cnt_reg[0]_0 ), .I4(po_rdval_cnt[0]), .I5(po_rdval_cnt[1]), .O(\po_rdval_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hB8B8B888888888B8)) \po_rdval_cnt[2]_i_1 (.I0(\po_counter_read_val_reg[5] [1]), .I1(\po_rdval_cnt[8]_i_4_n_0 ), .I2(\po_rdval_cnt_reg[0]_0 ), .I3(po_rdval_cnt[1]), .I4(po_rdval_cnt[0]), .I5(po_rdval_cnt[2]), .O(\po_rdval_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAC00ACFFACFFAC00)) \po_rdval_cnt[3]_i_1 (.I0(\po_counter_read_val_reg[8] [1]), .I1(\po_counter_read_val_reg[8]_0 [1]), .I2(\calib_sel_reg[3] ), .I3(\po_rdval_cnt[8]_i_4_n_0 ), .I4(po_rdval_cnt[3]), .I5(\po_rdval_cnt[4]_i_2_n_0 ), .O(\po_rdval_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFB0808FBFB08FB08)) \po_rdval_cnt[4]_i_1 (.I0(\po_counter_read_val_reg[5] [2]), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(po_rdval_cnt[4]), .I4(po_rdval_cnt[3]), .I5(\po_rdval_cnt[4]_i_2_n_0 ), .O(\po_rdval_cnt[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0001)) \po_rdval_cnt[4]_i_2 (.I0(po_rdval_cnt[1]), .I1(po_rdval_cnt[0]), .I2(po_rdval_cnt[2]), .I3(po_dec_done_i_3_n_0), .O(\po_rdval_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'hFB0808080808FB08)) \po_rdval_cnt[5]_i_1 (.I0(\po_counter_read_val_reg[5] [3]), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(\po_rdval_cnt_reg[0]_0 ), .I4(\po_rdval_cnt[5]_i_2_n_0 ), .I5(po_rdval_cnt[5]), .O(\po_rdval_cnt[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair312" *) LUT5 #( .INIT(32'hFFFFFFFE)) \po_rdval_cnt[5]_i_2 (.I0(po_rdval_cnt[3]), .I1(po_rdval_cnt[4]), .I2(po_rdval_cnt[1]), .I3(po_rdval_cnt[0]), .I4(po_rdval_cnt[2]), .O(\po_rdval_cnt[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFACFF0000AC00)) \po_rdval_cnt[6]_i_1 (.I0(\po_counter_read_val_reg[8] [2]), .I1(\po_counter_read_val_reg[8]_0 [2]), .I2(\calib_sel_reg[3] ), .I3(phy_ctl_ready_r5), .I4(phy_ctl_ready_r6_reg_n_0), .I5(\po_rdval_cnt[6]_i_2_n_0 ), .O(\po_rdval_cnt[6]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAA8A00000020)) \po_rdval_cnt[6]_i_2 (.I0(\po_rdval_cnt_reg[0]_0 ), .I1(po_rdval_cnt[5]), .I2(\po_rdval_cnt[8]_i_7_n_0 ), .I3(po_rdval_cnt[4]), .I4(po_rdval_cnt[3]), .I5(po_rdval_cnt[6]), .O(\po_rdval_cnt[6]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFACFF0000AC00)) \po_rdval_cnt[7]_i_1 (.I0(\po_counter_read_val_reg[8] [3]), .I1(\po_counter_read_val_reg[8]_0 [3]), .I2(\calib_sel_reg[3] ), .I3(phy_ctl_ready_r5), .I4(phy_ctl_ready_r6_reg_n_0), .I5(\po_rdval_cnt[7]_i_2_n_0 ), .O(\po_rdval_cnt[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFC00000002)) \po_rdval_cnt[7]_i_2 (.I0(po_rdval_cnt[8]), .I1(po_rdval_cnt[1]), .I2(po_rdval_cnt[0]), .I3(po_rdval_cnt[2]), .I4(\po_rdval_cnt[8]_i_6_n_0 ), .I5(po_rdval_cnt[7]), .O(\po_rdval_cnt[7]_i_2_n_0 )); LUT4 #( .INIT(16'hAEFF)) \po_rdval_cnt[8]_i_1 (.I0(dqs_po_en_stg2_f_reg_0), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(\po_rdval_cnt_reg[0]_0 ), .O(\po_rdval_cnt[8]_i_1_n_0 )); LUT6 #( .INIT(64'hACFFAC00AC00AC00)) \po_rdval_cnt[8]_i_2 (.I0(\po_counter_read_val_reg[8] [4]), .I1(\po_counter_read_val_reg[8]_0 [4]), .I2(\calib_sel_reg[3] ), .I3(\po_rdval_cnt[8]_i_4_n_0 ), .I4(po_rdval_cnt[8]), .I5(\po_rdval_cnt[8]_i_5_n_0 ), .O(\po_rdval_cnt[8]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \po_rdval_cnt[8]_i_3 (.I0(po_rdval_cnt[8]), .I1(po_rdval_cnt[1]), .I2(po_rdval_cnt[0]), .I3(po_rdval_cnt[2]), .I4(\po_rdval_cnt[8]_i_6_n_0 ), .I5(po_rdval_cnt[7]), .O(\po_rdval_cnt_reg[0]_0 )); LUT2 #( .INIT(4'h2)) \po_rdval_cnt[8]_i_4 (.I0(phy_ctl_ready_r5), .I1(phy_ctl_ready_r6_reg_n_0), .O(\po_rdval_cnt[8]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \po_rdval_cnt[8]_i_5 (.I0(po_rdval_cnt[7]), .I1(po_rdval_cnt[3]), .I2(po_rdval_cnt[4]), .I3(po_rdval_cnt[5]), .I4(po_rdval_cnt[6]), .I5(\po_rdval_cnt[8]_i_7_n_0 ), .O(\po_rdval_cnt[8]_i_5_n_0 )); LUT4 #( .INIT(16'hFFFE)) \po_rdval_cnt[8]_i_6 (.I0(po_rdval_cnt[3]), .I1(po_rdval_cnt[4]), .I2(po_rdval_cnt[5]), .I3(po_rdval_cnt[6]), .O(\po_rdval_cnt[8]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair312" *) LUT3 #( .INIT(8'h01)) \po_rdval_cnt[8]_i_7 (.I0(po_rdval_cnt[2]), .I1(po_rdval_cnt[0]), .I2(po_rdval_cnt[1]), .O(\po_rdval_cnt[8]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[0] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[0]_i_1_n_0 ), .Q(po_rdval_cnt[0]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[1] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[1]_i_1_n_0 ), .Q(po_rdval_cnt[1]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[2] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[2]_i_1_n_0 ), .Q(po_rdval_cnt[2]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[3] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[3]_i_1_n_0 ), .Q(po_rdval_cnt[3]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[4] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[4]_i_1_n_0 ), .Q(po_rdval_cnt[4]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[5] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[5]_i_1_n_0 ), .Q(po_rdval_cnt[5]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[6] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[6]_i_1_n_0 ), .Q(po_rdval_cnt[6]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[7] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[7]_i_1_n_0 ), .Q(po_rdval_cnt[7]), .R(SR[0])); FDRE #( .INIT(1'b0)) \po_rdval_cnt_reg[8] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[8]_i_2_n_0 ), .Q(po_rdval_cnt[8]), .R(SR[0])); (* SOFT_HLUTNM = "soft_lutpair346" *) LUT3 #( .INIT(8'h38)) \rank_cnt_r[0]_i_1 (.I0(\rank_cnt_r_reg[0]_0 ), .I1(rank_cnt_r), .I2(\rank_cnt_r_reg[0]_1 ), .O(\rank_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair346" *) LUT3 #( .INIT(8'h78)) \rank_cnt_r[1]_i_1 (.I0(\rank_cnt_r_reg[0]_1 ), .I1(rank_cnt_r), .I2(\rank_cnt_r_reg[0]_0 ), .O(\rank_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \rank_cnt_r[1]_i_2 (.I0(out[4]), .I1(out[2]), .I2(out[1]), .I3(out[0]), .I4(p_0_in), .I5(out[3]), .O(rank_cnt_r)); FDRE #( .INIT(1'b0)) \rank_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rank_cnt_r[0]_i_1_n_0 ), .Q(\rank_cnt_r_reg[0]_1 ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \rank_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rank_cnt_r[1]_i_1_n_0 ), .Q(\rank_cnt_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__17[1])); (* SOFT_HLUTNM = "soft_lutpair341" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[0]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .I2(\rd_data_previous_r_reg_n_0_[0] ), .O(\rd_data_edge_detect_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair341" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[1]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .I2(\rd_data_previous_r_reg_n_0_[1] ), .O(\rd_data_edge_detect_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair343" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[2]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .I2(\rd_data_previous_r_reg_n_0_[2] ), .O(\rd_data_edge_detect_r[2]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \rd_data_edge_detect_r[3]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I1(\rd_data_edge_detect_r_reg[0]_1 ), .I2(flag_init), .I3(rstdiv0_sync_r1_reg_rep__22), .I4(\rd_data_edge_detect_r_reg[0]_0 ), .O(rd_data_edge_detect_r0)); LUT6 #( .INIT(64'h49484044FFFFFFFF)) \rd_data_edge_detect_r[3]_i_2 (.I0(out[3]), .I1(out[2]), .I2(out[4]), .I3(out[0]), .I4(out[1]), .I5(\rd_data_edge_detect_r[3]_i_5_n_0 ), .O(\rd_data_edge_detect_r[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair343" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[3]_i_3 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .I2(\rd_data_previous_r_reg_n_0_[3] ), .O(\rd_data_edge_detect_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \rd_data_edge_detect_r[3]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[0] ), .I1(\wl_tap_count_r_reg_n_0_[1] ), .I2(\wl_tap_count_r_reg_n_0_[2] ), .I3(\wl_tap_count_r_reg_n_0_[3] ), .I4(\wl_tap_count_r_reg_n_0_[5] ), .I5(\wl_tap_count_r_reg_n_0_[4] ), .O(\rd_data_edge_detect_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \rd_data_edge_detect_r[3]_i_5 (.I0(\rd_data_edge_detect_r_reg_n_0_[3] ), .I1(\rd_data_edge_detect_r_reg_n_0_[2] ), .I2(\dqs_count_r_reg[1]_rep_n_0 ), .I3(\rd_data_edge_detect_r_reg_n_0_[1] ), .I4(\dqs_count_r_reg[0]_rep_n_0 ), .I5(\rd_data_edge_detect_r_reg_n_0_[0] ), .O(\rd_data_edge_detect_r[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair311" *) LUT5 #( .INIT(32'h000080FF)) \rd_data_edge_detect_r[3]_i_6 (.I0(\stable_cnt_reg_n_0_[3] ), .I1(\stable_cnt_reg_n_0_[2] ), .I2(\stable_cnt_reg_n_0_[1] ), .I3(stable_cnt227_in), .I4(\rd_data_edge_detect_r[3]_i_5_n_0 ), .O(\rd_data_edge_detect_r[3]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \rd_data_edge_detect_r_reg[0] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[0]_i_1_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[0] ), .R(rd_data_edge_detect_r0)); FDRE #( .INIT(1'b0)) \rd_data_edge_detect_r_reg[1] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[1]_i_1_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[1] ), .R(rd_data_edge_detect_r0)); FDRE #( .INIT(1'b0)) \rd_data_edge_detect_r_reg[2] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[2]_i_1_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[2] ), .R(rd_data_edge_detect_r0)); FDRE #( .INIT(1'b0)) \rd_data_edge_detect_r_reg[3] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[3]_i_3_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[3] ), .R(rd_data_edge_detect_r0)); LUT6 #( .INIT(64'hAAEEAAAAFFABAAFA)) \rd_data_previous_r[3]_i_1 (.I0(\rd_data_previous_r[3]_i_2_n_0 ), .I1(out[1]), .I2(out[0]), .I3(out[4]), .I4(out[2]), .I5(out[3]), .O(rd_data_previous_r0)); LUT6 #( .INIT(64'hFFFFFFFF00000020)) \rd_data_previous_r[3]_i_2 (.I0(\FSM_sequential_wl_state_r_reg[0]_0 ), .I1(\rd_data_previous_r[3]_i_3_n_0 ), .I2(out[3]), .I3(out[2]), .I4(out[1]), .I5(\rd_data_previous_r[3]_i_4_n_0 ), .O(\rd_data_previous_r[3]_i_2_n_0 )); LUT2 #( .INIT(4'hB)) \rd_data_previous_r[3]_i_3 (.I0(out[0]), .I1(out[4]), .O(\rd_data_previous_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000400)) \rd_data_previous_r[3]_i_4 (.I0(\wl_state_r1_reg_n_0_[0] ), .I1(p_0_in32_in), .I2(\wl_state_r1_reg_n_0_[4] ), .I3(\wl_state_r1_reg_n_0_[2] ), .I4(\wl_state_r1_reg_n_0_[3] ), .I5(\wl_state_r1_reg_n_0_[1] ), .O(\rd_data_previous_r[3]_i_4_n_0 )); LUT5 #( .INIT(32'h00000100)) \rd_data_previous_r[3]_i_5 (.I0(out[3]), .I1(out[4]), .I2(out[0]), .I3(out[1]), .I4(out[2]), .O(p_0_in32_in)); FDRE #( .INIT(1'b0)) \rd_data_previous_r_reg[0] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .Q(\rd_data_previous_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_data_previous_r_reg[1] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .Q(\rd_data_previous_r_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_data_previous_r_reg[2] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .Q(\rd_data_previous_r_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_data_previous_r_reg[3] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .Q(\rd_data_previous_r_reg_n_0_[3] ), .R(1'b0)); LUT6 #( .INIT(64'h000000000000FBF8)) \single_rank.done_dqs_dec_i_1 (.I0(done_dqs_tap_inc), .I1(oclkdelay_calib_done_r_reg), .I2(done_dqs_dec), .I3(wr_level_done_r1_reg_0), .I4(wr_level_done0), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\single_rank.done_dqs_dec_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair342" *) LUT3 #( .INIT(8'h08)) \single_rank.done_dqs_dec_i_2 (.I0(oclkdelay_calib_done_r_reg), .I1(wr_level_done_r3), .I2(wr_level_done_r4), .O(done_dqs_dec)); (* SOFT_HLUTNM = "soft_lutpair319" *) LUT4 #( .INIT(16'h4F44)) \single_rank.done_dqs_dec_i_3 (.I0(wrlvl_byte_redo_r), .I1(wrlvl_byte_redo), .I2(wrlvl_final_r), .I3(wrlvl_final_mux), .O(wr_level_done0)); FDRE #( .INIT(1'b0)) \single_rank.done_dqs_dec_reg (.C(CLK), .CE(1'b1), .D(\single_rank.done_dqs_dec_i_1_n_0 ), .Q(done_dqs_tap_inc), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair329" *) LUT3 #( .INIT(8'hB8)) \smallest[0][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(largest[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][0]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ), .O(\smallest[0][0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair330" *) LUT3 #( .INIT(8'hB8)) \smallest[0][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(largest[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][1]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ), .O(\smallest[0][1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair329" *) LUT3 #( .INIT(8'hB8)) \smallest[0][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(largest[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][2]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ), .O(\smallest[0][2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair331" *) LUT3 #( .INIT(8'hB8)) \smallest[0][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(largest[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][3]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ), .O(\smallest[0][3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair330" *) LUT3 #( .INIT(8'hB8)) \smallest[0][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(largest[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][4]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ), .O(\smallest[0][4]_i_2_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[0][5]_i_2 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[0][5]_i_3_n_0 ), .O(\smallest[0][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair331" *) LUT3 #( .INIT(8'hB8)) \smallest[0][5]_i_3 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(largest[5])); LUT5 #( .INIT(32'hFDFFF7FF)) \smallest[0][5]_i_4 (.I0(out[4]), .I1(out[0]), .I2(out[2]), .I3(out[3]), .I4(out[1]), .O(\smallest[0][5]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][5]_i_5 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ), .O(\smallest[0][5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair324" *) LUT3 #( .INIT(8'hB8)) \smallest[1][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(\smallest[1][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair324" *) LUT3 #( .INIT(8'hB8)) \smallest[1][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(\smallest[1][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair327" *) LUT3 #( .INIT(8'hB8)) \smallest[1][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(\smallest[1][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair327" *) LUT3 #( .INIT(8'hB8)) \smallest[1][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(\smallest[1][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair328" *) LUT3 #( .INIT(8'hB8)) \smallest[1][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(\smallest[1][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[1][5]_i_1 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[1][5]_i_3_n_0 ), .O(\smallest[1][5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair328" *) LUT3 #( .INIT(8'hB8)) \smallest[1][5]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(\smallest[1][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair321" *) LUT3 #( .INIT(8'hB8)) \smallest[2][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(\smallest[2][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair321" *) LUT3 #( .INIT(8'hB8)) \smallest[2][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(\smallest[2][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair322" *) LUT3 #( .INIT(8'hB8)) \smallest[2][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(\smallest[2][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair322" *) LUT3 #( .INIT(8'hB8)) \smallest[2][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(\smallest[2][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair326" *) LUT3 #( .INIT(8'hB8)) \smallest[2][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(\smallest[2][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[2][5]_i_1 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[2][5]_i_3_n_0 ), .O(\smallest[2][5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair326" *) LUT3 #( .INIT(8'hB8)) \smallest[2][5]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(\smallest[2][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair320" *) LUT3 #( .INIT(8'hB8)) \smallest[3][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(\smallest[3][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair323" *) LUT3 #( .INIT(8'hB8)) \smallest[3][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(\smallest[3][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair325" *) LUT3 #( .INIT(8'hB8)) \smallest[3][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(\smallest[3][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair325" *) LUT3 #( .INIT(8'hB8)) \smallest[3][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(\smallest[3][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair323" *) LUT3 #( .INIT(8'hB8)) \smallest[3][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(\smallest[3][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[3][5]_i_1 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[3][5]_i_5_n_0 ), .O(\smallest[3][5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair320" *) LUT3 #( .INIT(8'hB8)) \smallest[3][5]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(\smallest[3][5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \smallest_reg[0][0] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[0]), .Q(\smallest_reg[0]__0 [0]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[0][1] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[1]), .Q(\smallest_reg[0]__0 [1]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[0][2] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[2]), .Q(\smallest_reg[0]__0 [2]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[0][3] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[3]), .Q(\smallest_reg[0]__0 [3]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[0][4] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[4]), .Q(\smallest_reg[0]__0 [4]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[0][5] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[5]), .Q(\smallest_reg[0]__0 [5]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[1][0] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][0]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [0]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[1][1] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][1]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [1]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[1][2] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][2]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [2]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[1][3] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][3]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [3]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[1][4] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][4]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [4]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[1][5] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][5]_i_2_n_0 ), .Q(\smallest_reg[1]__0 [5]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[2][0] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][0]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [0]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[2][1] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][1]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [1]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[2][2] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][2]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [2]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[2][3] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][3]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [3]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[2][4] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][4]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [4]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[2][5] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][5]_i_2_n_0 ), .Q(\smallest_reg[2]__0 [5]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[3][0] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][0]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [0]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[3][1] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][1]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [1]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[3][2] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][2]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [2]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[3][3] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][3]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [3]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[3][4] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][4]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [4]), .R(SR[1])); FDRE #( .INIT(1'b0)) \smallest_reg[3][5] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][5]_i_2_n_0 ), .Q(\smallest_reg[3]__0 [5]), .R(SR[1])); (* SOFT_HLUTNM = "soft_lutpair349" *) LUT1 #( .INIT(2'h1)) \stable_cnt[0]_i_1 (.I0(\stable_cnt_reg[3]_0 ), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair349" *) LUT2 #( .INIT(4'h6)) \stable_cnt[1]_i_1 (.I0(\stable_cnt_reg[3]_0 ), .I1(\stable_cnt_reg_n_0_[1] ), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair317" *) LUT3 #( .INIT(8'h6A)) \stable_cnt[2]_i_1 (.I0(\stable_cnt_reg_n_0_[2] ), .I1(\stable_cnt_reg_n_0_[1] ), .I2(\stable_cnt_reg[3]_0 ), .O(p_0_in__0[2])); LUT5 #( .INIT(32'hFFFFFFFB)) \stable_cnt[3]_i_1 (.I0(\stable_cnt[3]_i_4_n_0 ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(p_1_in1_in), .I3(rstdiv0_sync_r1_reg_rep__22), .I4(\stable_cnt[3]_i_6_n_0 ), .O(stable_cnt0)); LUT6 #( .INIT(64'h0000000015550000)) \stable_cnt[3]_i_2 (.I0(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I1(\stable_cnt_reg_n_0_[1] ), .I2(\stable_cnt_reg_n_0_[2] ), .I3(\stable_cnt_reg_n_0_[3] ), .I4(\rd_data_previous_r[3]_i_2_n_0 ), .I5(\stable_cnt[3]_i_4_n_0 ), .O(stable_cnt)); (* SOFT_HLUTNM = "soft_lutpair317" *) LUT4 #( .INIT(16'h6AAA)) \stable_cnt[3]_i_3 (.I0(\stable_cnt_reg_n_0_[3] ), .I1(\stable_cnt_reg[3]_0 ), .I2(\stable_cnt_reg_n_0_[1] ), .I3(\stable_cnt_reg_n_0_[2] ), .O(p_0_in__0[3])); LUT2 #( .INIT(4'h6)) \stable_cnt[3]_i_4 (.I0(stable_cnt227_in), .I1(\stable_cnt[3]_i_7_n_0 ), .O(\stable_cnt[3]_i_4_n_0 )); LUT5 #( .INIT(32'h00000020)) \stable_cnt[3]_i_5 (.I0(out[1]), .I1(out[4]), .I2(out[0]), .I3(out[3]), .I4(out[2]), .O(p_1_in1_in)); LUT5 #( .INIT(32'h00000020)) \stable_cnt[3]_i_6 (.I0(\wl_state_r1_reg_n_0_[0] ), .I1(\wl_state_r1_reg_n_0_[4] ), .I2(\wl_state_r1_reg_n_0_[2] ), .I3(\wl_state_r1_reg_n_0_[3] ), .I4(\wl_state_r1_reg_n_0_[1] ), .O(\stable_cnt[3]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \stable_cnt[3]_i_7 (.I0(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .I1(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .I2(\dqs_count_r_reg[1]_rep_n_0 ), .I3(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .I4(\dqs_count_r_reg[0]_rep_n_0 ), .I5(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .O(\stable_cnt[3]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \stable_cnt_reg[0] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[0]), .Q(\stable_cnt_reg[3]_0 ), .R(stable_cnt0)); FDRE #( .INIT(1'b0)) \stable_cnt_reg[1] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[1]), .Q(\stable_cnt_reg_n_0_[1] ), .R(stable_cnt0)); FDRE #( .INIT(1'b0)) \stable_cnt_reg[2] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[2]), .Q(\stable_cnt_reg_n_0_[2] ), .R(stable_cnt0)); FDRE #( .INIT(1'b0)) \stable_cnt_reg[3] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[3]), .Q(\stable_cnt_reg_n_0_[3] ), .R(stable_cnt0)); LUT6 #( .INIT(64'h55330F0055330FFF)) \stg2_tap_cnt[0]_i_2 (.I0(wl_po_fine_cnt[18]), .I1(wl_po_fine_cnt[12]), .I2(wl_po_fine_cnt[6]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[0]), .O(\stg2_r_reg[0] )); LUT6 #( .INIT(64'h55FFDDF05500DDF0)) \stg2_tap_cnt[1]_i_2 (.I0(\stg2_tap_cnt[3]_i_4_n_0 ), .I1(wl_po_fine_cnt[7]), .I2(wl_po_fine_cnt[1]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[13]), .O(\stg2_target_r_reg[4] [0])); LUT6 #( .INIT(64'hFFAAF0CC00AAF0CC)) \stg2_tap_cnt[2]_i_2 (.I0(wl_po_fine_cnt[14]), .I1(wl_po_fine_cnt[2]), .I2(wl_po_fine_cnt[8]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[20]), .O(\stg2_target_r_reg[4] [1])); LUT6 #( .INIT(64'h00AA0F22FFAA0F22)) \stg2_tap_cnt[3]_i_2 (.I0(\stg2_tap_cnt[3]_i_4_n_0 ), .I1(wl_po_fine_cnt[3]), .I2(wl_po_fine_cnt[9]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[21]), .O(\stg3_dec_val_reg[2] )); LUT4 #( .INIT(16'h4F7F)) \stg2_tap_cnt[3]_i_4 (.I0(wl_po_fine_cnt[19]), .I1(\byte_r_reg[0] ), .I2(\byte_r_reg[1] ), .I3(wl_po_fine_cnt[15]), .O(\stg2_tap_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0511AF1105BBAFBB)) \stg2_tap_cnt[4]_i_2 (.I0(\byte_r_reg[0] ), .I1(wl_po_fine_cnt[4]), .I2(wl_po_fine_cnt[16]), .I3(\byte_r_reg[1] ), .I4(wl_po_fine_cnt[22]), .I5(wl_po_fine_cnt[10]), .O(\stg2_r_reg[4] )); LUT6 #( .INIT(64'h00550F33FF550F33)) \stg2_tap_cnt[5]_i_5 (.I0(wl_po_fine_cnt[17]), .I1(wl_po_fine_cnt[5]), .I2(wl_po_fine_cnt[11]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[23]), .O(\stg2_r_reg[5] )); LUT6 #( .INIT(64'hFECEF2C23E0E3202)) \stg2_target_r[0]_i_1 (.I0(wl_po_fine_cnt[0]), .I1(\byte_r_reg[1] ), .I2(\byte_r_reg[0] ), .I3(wl_po_fine_cnt[6]), .I4(wl_po_fine_cnt[12]), .I5(wl_po_fine_cnt[18]), .O(D[0])); LUT1 #( .INIT(2'h1)) \stg2_target_r[4]_i_2 (.I0(\stg2_r_reg[4] ), .O(\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4])); LUT1 #( .INIT(2'h1)) \stg2_target_r[4]_i_3 (.I0(\stg3_dec_val_reg[2] ), .O(\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [3])); LUT2 #( .INIT(4'h9)) \stg2_target_r[4]_i_4 (.I0(\stg2_r_reg[4] ), .I1(O[2]), .O(\stg2_target_r[4]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \stg2_target_r[4]_i_5 (.I0(\stg3_dec_val_reg[2] ), .I1(O[1]), .O(\stg2_target_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hBF8FBC8CB383B080)) \stg2_target_r[8]_i_2 (.I0(wl_po_fine_cnt[23]), .I1(\byte_r_reg[1] ), .I2(\byte_r_reg[0] ), .I3(wl_po_fine_cnt[11]), .I4(wl_po_fine_cnt[5]), .I5(wl_po_fine_cnt[17]), .O(\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5])); LUT2 #( .INIT(4'h9)) \stg2_target_r[8]_i_6 (.I0(\stg2_r_reg[5] ), .I1(O[3]), .O(\stg2_target_r[8]_i_6_n_0 )); CARRY4 \stg2_target_r_reg[4]_i_1 (.CI(1'b0), .CO({\stg2_target_r_reg[4]_i_1_n_0 ,\stg2_target_r_reg[4]_i_1_n_1 ,\stg2_target_r_reg[4]_i_1_n_2 ,\stg2_target_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4:3],\stg2_target_r_reg[4] }), .O({D[3:1],\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\stg2_target_r[4]_i_4_n_0 ,\stg2_target_r[4]_i_5_n_0 ,\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ,S})); CARRY4 \stg2_target_r_reg[8]_i_1 (.CI(\stg2_target_r_reg[4]_i_1_n_0 ), .CO({\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED [3],\stg2_target_r_reg[8]_i_1_n_1 ,\stg2_target_r_reg[8]_i_1_n_2 ,\stg2_target_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5]}), .O(D[7:4]), .S({\stg3_r_reg[5] ,\stg2_target_r[8]_i_6_n_0 })); (* SOFT_HLUTNM = "soft_lutpair316" *) LUT2 #( .INIT(4'h9)) \stg3_dec_val[0]_i_1 (.I0(\stg2_target_r_reg[4] [0]), .I1(Q[0]), .O(\stg3_dec_val_reg[2]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair316" *) LUT4 #( .INIT(16'hE11E)) \stg3_dec_val[1]_i_1 (.I0(\stg2_target_r_reg[4] [0]), .I1(Q[0]), .I2(\stg2_target_r_reg[4] [1]), .I3(Q[1]), .O(\stg3_dec_val_reg[2]_0 [1])); LUT6 #( .INIT(64'h1117EEE8EEE81117)) \stg3_dec_val[2]_i_1 (.I0(\stg2_target_r_reg[4] [1]), .I1(Q[1]), .I2(\stg2_target_r_reg[4] [0]), .I3(Q[0]), .I4(\stg3_dec_val_reg[2] ), .I5(Q[2]), .O(\stg3_dec_val_reg[2]_0 [2])); LUT2 #( .INIT(4'h6)) \u_ocd_po_cntlr/stg2_target_r[4]_i_6 (.I0(\stg2_target_r_reg[4] [1]), .I1(O[0]), .O(\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \wait_cnt[0]_i_1 (.I0(wait_cnt_reg__0[0]), .O(wait_cnt0__0[0])); (* SOFT_HLUTNM = "soft_lutpair348" *) LUT2 #( .INIT(4'h9)) \wait_cnt[1]_i_1 (.I0(wait_cnt_reg__0[0]), .I1(wait_cnt_reg__0[1]), .O(\wait_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair348" *) LUT3 #( .INIT(8'hA9)) \wait_cnt[2]_i_1 (.I0(wait_cnt_reg__0[2]), .I1(wait_cnt_reg__0[1]), .I2(wait_cnt_reg__0[0]), .O(wait_cnt0__0[2])); LUT5 #( .INIT(32'hAAAAAAA8)) \wait_cnt[3]_i_2 (.I0(phy_ctl_ready_r6_reg_n_0), .I1(wait_cnt_reg__0[3]), .I2(wait_cnt_reg__0[1]), .I3(wait_cnt_reg__0[0]), .I4(wait_cnt_reg__0[2]), .O(wait_cnt0)); (* SOFT_HLUTNM = "soft_lutpair313" *) LUT4 #( .INIT(16'hAAA9)) \wait_cnt[3]_i_3 (.I0(wait_cnt_reg__0[3]), .I1(wait_cnt_reg__0[2]), .I2(wait_cnt_reg__0[0]), .I3(wait_cnt_reg__0[1]), .O(wait_cnt0__0[3])); FDRE #( .INIT(1'b0)) \wait_cnt_reg[0] (.C(CLK), .CE(wait_cnt0), .D(wait_cnt0__0[0]), .Q(wait_cnt_reg__0[0]), .R(po_cnt_dec_reg_1)); FDRE #( .INIT(1'b0)) \wait_cnt_reg[1] (.C(CLK), .CE(wait_cnt0), .D(\wait_cnt[1]_i_1_n_0 ), .Q(wait_cnt_reg__0[1]), .R(po_cnt_dec_reg_1)); FDRE #( .INIT(1'b0)) \wait_cnt_reg[2] (.C(CLK), .CE(wait_cnt0), .D(wait_cnt0__0[2]), .Q(wait_cnt_reg__0[2]), .R(po_cnt_dec_reg_1)); FDSE #( .INIT(1'b1)) \wait_cnt_reg[3] (.C(CLK), .CE(wait_cnt0), .D(wait_cnt0__0[3]), .Q(wait_cnt_reg__0[3]), .S(po_cnt_dec_reg_1)); LUT6 #( .INIT(64'hF0FFF000AACCAACC)) \wl_corse_cnt[0][0][0]_i_1 (.I0(\corse_cnt_reg_n_0_[2][0] ), .I1(\corse_cnt_reg_n_0_[0][0] ), .I2(\corse_cnt_reg_n_0_[3][0] ), .I3(\dqs_count_r_reg[1]_rep_n_0 ), .I4(\corse_cnt_reg_n_0_[1][0] ), .I5(\dqs_count_r_reg[0]_rep_n_0 ), .O(\wl_corse_cnt[0][0][0]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_corse_cnt[0][0][1]_i_1 (.I0(\corse_cnt_reg_n_0_[3][1] ), .I1(\corse_cnt_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_cnt_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_cnt_reg_n_0_[0][1] ), .O(\wl_corse_cnt[0][0][1]_i_1_n_0 )); LUT4 #( .INIT(16'h0100)) \wl_corse_cnt[0][0][2]_i_1 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .I2(dqs_count_r[2]), .I3(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .O(wl_corse_cnt)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_corse_cnt[0][0][2]_i_2 (.I0(\corse_cnt_reg_n_0_[3][2] ), .I1(\corse_cnt_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_cnt_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_cnt_reg_n_0_[0][2] ), .O(\wl_corse_cnt[0][0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0200088000800000)) \wl_corse_cnt[0][0][2]_i_3 (.I0(\wl_corse_cnt[0][0][2]_i_4_n_0 ), .I1(out[1]), .I2(out[2]), .I3(out[4]), .I4(out[0]), .I5(out[3]), .O(\wl_corse_cnt[0][0][2]_i_3_n_0 )); LUT2 #( .INIT(4'h1)) \wl_corse_cnt[0][0][2]_i_4 (.I0(\rank_cnt_r_reg[0]_0 ), .I1(\rank_cnt_r_reg[0]_1 ), .O(\wl_corse_cnt[0][0][2]_i_4_n_0 )); LUT4 #( .INIT(16'h0020)) \wl_corse_cnt[0][1][2]_i_1 (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .I3(dqs_count_r[2]), .O(\wl_corse_cnt[0][1][2]_i_1_n_0 )); LUT4 #( .INIT(16'h0020)) \wl_corse_cnt[0][2][2]_i_1 (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .I3(dqs_count_r[2]), .O(\wl_corse_cnt[0][2][2]_i_1_n_0 )); LUT4 #( .INIT(16'h0080)) \wl_corse_cnt[0][3][2]_i_1 (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .I3(dqs_count_r[2]), .O(\wl_corse_cnt[0][3][2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][0][0] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][0]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][0][1] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][0]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][0][2] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][0]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][1][0] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][1]__0 [0]), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][1][1] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][1]__0 [1]), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][1][2] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][1]__0 [2]), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][2][0] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][2]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][2][1] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][2]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][2][2] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][2]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][3][0] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][3]__0 [0]), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][3][1] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][3]__0 [1]), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_corse_cnt_reg[0][3][2] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][3]__0 [2]), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][0][0] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][0][1] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][0][2] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][0][3] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][0][4] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][0][5] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][1][0] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][1][1] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][1][2] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][1][3] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][1][4] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][1][5] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][2][0] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][2][1] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][2][2] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][2][3] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][2][4] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][2][5] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][3][0] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][3][1] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][3][2] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][3][3] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][3][4] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_dqs_tap_count_r_reg[0][3][5] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ), .R(SR[1])); FDRE #( .INIT(1'b0)) wl_edge_detect_valid_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[2]_0 ), .Q(\FSM_sequential_wl_state_r_reg[0]_0 ), .R(SR[1])); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [0]), .Q(wl_po_fine_cnt[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[10] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [4]), .Q(wl_po_fine_cnt[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[11] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [5]), .Q(wl_po_fine_cnt[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[12] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [0]), .Q(wl_po_fine_cnt[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[13] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [1]), .Q(wl_po_fine_cnt[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[14] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [2]), .Q(wl_po_fine_cnt[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[15] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [3]), .Q(wl_po_fine_cnt[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[16] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [4]), .Q(wl_po_fine_cnt[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[17] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [5]), .Q(wl_po_fine_cnt[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[18] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [0]), .Q(wl_po_fine_cnt[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[19] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [1]), .Q(wl_po_fine_cnt[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [1]), .Q(wl_po_fine_cnt[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[20] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [2]), .Q(wl_po_fine_cnt[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[21] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [3]), .Q(wl_po_fine_cnt[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[22] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [4]), .Q(wl_po_fine_cnt[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[23] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [5]), .Q(wl_po_fine_cnt[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [2]), .Q(wl_po_fine_cnt[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [3]), .Q(wl_po_fine_cnt[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [4]), .Q(wl_po_fine_cnt[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[5] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [5]), .Q(wl_po_fine_cnt[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[6] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [0]), .Q(wl_po_fine_cnt[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[7] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [1]), .Q(wl_po_fine_cnt[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[8] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [2]), .Q(wl_po_fine_cnt[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wl_po_fine_cnt_reg[9] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [3]), .Q(wl_po_fine_cnt[9]), .R(1'b0)); LUT5 #( .INIT(32'h1B15D560)) \wl_state_r1[0]_i_1 (.I0(out[1]), .I1(out[2]), .I2(out[4]), .I3(out[0]), .I4(out[3]), .O(\wl_state_r1[0]_i_1_n_0 )); LUT5 #( .INIT(32'h293CEA22)) \wl_state_r1[1]_i_1 (.I0(out[1]), .I1(out[4]), .I2(out[3]), .I3(out[0]), .I4(out[2]), .O(\wl_state_r1[1]_i_1_n_0 )); LUT5 #( .INIT(32'h0505C478)) \wl_state_r1[2]_i_1 (.I0(out[2]), .I1(out[1]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .O(\wl_state_r1[2]_i_1_n_0 )); LUT5 #( .INIT(32'h67425208)) \wl_state_r1[3]_i_1 (.I0(out[4]), .I1(out[2]), .I2(out[1]), .I3(out[0]), .I4(out[3]), .O(\wl_state_r1[3]_i_1_n_0 )); LUT5 #( .INIT(32'h55512B08)) \wl_state_r1[4]_i_1 (.I0(out[3]), .I1(out[0]), .I2(out[1]), .I3(out[2]), .I4(out[4]), .O(\wl_state_r1[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \wl_state_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[0]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[0] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \wl_state_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[1]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[1] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \wl_state_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[2]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[2] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \wl_state_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[3]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[3] ), .R(SR[0])); FDRE #( .INIT(1'b0)) \wl_state_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[4]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[4] ), .R(SR[0])); LUT4 #( .INIT(16'hFF10)) \wl_tap_count_r[0]_i_1 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r[0]_i_2_n_0 ), .I3(\wl_tap_count_r[0]_i_3_n_0 ), .O(wl_tap_count_r[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[0]_i_2 (.I0(\smallest_reg[3]__0 [0]), .I1(\smallest_reg[1]__0 [0]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [0]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [0]), .O(\wl_tap_count_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'h0003000005050000)) \wl_tap_count_r[0]_i_3 (.I0(out[0]), .I1(out[4]), .I2(\wl_tap_count_r_reg_n_0_[0] ), .I3(wr_level_done_r5), .I4(out[1]), .I5(out[3]), .O(\wl_tap_count_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hCCCFCCEECCCCCCEE)) \wl_tap_count_r[1]_i_1 (.I0(\wl_tap_count_r[1]_i_2_n_0 ), .I1(\wl_tap_count_r[1]_i_3_n_0 ), .I2(out[0]), .I3(out[3]), .I4(out[1]), .I5(\wl_tap_count_r[1]_i_4_n_0 ), .O(wl_tap_count_r[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[1]_i_2 (.I0(\smallest_reg[3]__0 [1]), .I1(\smallest_reg[1]__0 [1]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [1]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [1]), .O(\wl_tap_count_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000880)) \wl_tap_count_r[1]_i_3 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r_reg_n_0_[0] ), .I3(\wl_tap_count_r_reg_n_0_[1] ), .I4(wr_level_done_r5), .I5(out[4]), .O(\wl_tap_count_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair340" *) LUT2 #( .INIT(4'h6)) \wl_tap_count_r[1]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[1] ), .I1(\wl_tap_count_r_reg_n_0_[0] ), .O(\wl_tap_count_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'h02C232F202C202C2)) \wl_tap_count_r[2]_i_1 (.I0(\wl_tap_count_r[2]_i_2_n_0 ), .I1(out[3]), .I2(out[1]), .I3(\wl_tap_count_r[2]_i_3_n_0 ), .I4(out[0]), .I5(\wl_tap_count_r[2]_i_4_n_0 ), .O(wl_tap_count_r[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[2]_i_2 (.I0(\smallest_reg[3]__0 [2]), .I1(\smallest_reg[1]__0 [2]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [2]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [2]), .O(\wl_tap_count_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFEEFEFEF)) \wl_tap_count_r[2]_i_3 (.I0(out[4]), .I1(wr_level_done_r5), .I2(\wl_tap_count_r_reg_n_0_[2] ), .I3(\wl_tap_count_r_reg_n_0_[0] ), .I4(\wl_tap_count_r_reg_n_0_[1] ), .O(\wl_tap_count_r[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair340" *) LUT3 #( .INIT(8'h6A)) \wl_tap_count_r[2]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[2] ), .I1(\wl_tap_count_r_reg_n_0_[0] ), .I2(\wl_tap_count_r_reg_n_0_[1] ), .O(\wl_tap_count_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'h02C202C202C232F2)) \wl_tap_count_r[3]_i_1 (.I0(\wl_tap_count_r[3]_i_2_n_0 ), .I1(out[3]), .I2(out[1]), .I3(\wl_tap_count_r[3]_i_3_n_0 ), .I4(out[0]), .I5(\wl_tap_count_r[3]_i_4_n_0 ), .O(wl_tap_count_r[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[3]_i_2 (.I0(\smallest_reg[3]__0 [3]), .I1(\smallest_reg[1]__0 [3]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [3]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [3]), .O(\wl_tap_count_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEBBBBBBB)) \wl_tap_count_r[3]_i_3 (.I0(out[4]), .I1(\wl_tap_count_r_reg_n_0_[3] ), .I2(\wl_tap_count_r_reg_n_0_[2] ), .I3(\wl_tap_count_r_reg_n_0_[1] ), .I4(\wl_tap_count_r_reg_n_0_[0] ), .I5(wr_level_done_r5), .O(\wl_tap_count_r[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair314" *) LUT4 #( .INIT(16'h9555)) \wl_tap_count_r[3]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[3] ), .I1(\wl_tap_count_r_reg_n_0_[2] ), .I2(\wl_tap_count_r_reg_n_0_[1] ), .I3(\wl_tap_count_r_reg_n_0_[0] ), .O(\wl_tap_count_r[3]_i_4_n_0 )); LUT4 #( .INIT(16'hFF10)) \wl_tap_count_r[4]_i_1 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r[4]_i_2_n_0 ), .I3(\wl_tap_count_r[4]_i_3_n_0 ), .O(wl_tap_count_r[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[4]_i_2 (.I0(\smallest_reg[3]__0 [4]), .I1(\smallest_reg[1]__0 [4]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [4]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [4]), .O(\wl_tap_count_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h0003000005050000)) \wl_tap_count_r[4]_i_3 (.I0(out[0]), .I1(out[4]), .I2(\wl_tap_count_r[4]_i_4_n_0 ), .I3(wr_level_done_r5), .I4(out[1]), .I5(out[3]), .O(\wl_tap_count_r[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair314" *) LUT5 #( .INIT(32'h95555555)) \wl_tap_count_r[4]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[4] ), .I1(\wl_tap_count_r_reg_n_0_[0] ), .I2(\wl_tap_count_r_reg_n_0_[1] ), .I3(\wl_tap_count_r_reg_n_0_[2] ), .I4(\wl_tap_count_r_reg_n_0_[3] ), .O(\wl_tap_count_r[4]_i_4_n_0 )); LUT6 #( .INIT(64'h4400000044551110)) \wl_tap_count_r[5]_i_1 (.I0(out[2]), .I1(out[0]), .I2(done_dqs_dec239_out), .I3(out[3]), .I4(out[1]), .I5(out[4]), .O(\wl_tap_count_r[5]_i_1_n_0 )); LUT4 #( .INIT(16'hFF10)) \wl_tap_count_r[5]_i_2 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r[5]_i_4_n_0 ), .I3(\wl_tap_count_r[5]_i_5_n_0 ), .O(wl_tap_count_r[5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[5]_i_4 (.I0(\smallest_reg[3]__0 [5]), .I1(\smallest_reg[1]__0 [5]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [5]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [5]), .O(\wl_tap_count_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'h0300000055000000)) \wl_tap_count_r[5]_i_5 (.I0(out[0]), .I1(out[4]), .I2(wr_level_done_r5), .I3(\wl_tap_count_r[5]_i_6_n_0 ), .I4(out[1]), .I5(out[3]), .O(\wl_tap_count_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \wl_tap_count_r[5]_i_6 (.I0(\wl_tap_count_r_reg_n_0_[5] ), .I1(\wl_tap_count_r_reg_n_0_[4] ), .I2(\wl_tap_count_r_reg_n_0_[3] ), .I3(\wl_tap_count_r_reg_n_0_[2] ), .I4(\wl_tap_count_r_reg_n_0_[1] ), .I5(\wl_tap_count_r_reg_n_0_[0] ), .O(\wl_tap_count_r[5]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \wl_tap_count_r_reg[0] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[0]), .Q(\wl_tap_count_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_tap_count_r_reg[1] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[1]), .Q(\wl_tap_count_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_tap_count_r_reg[2] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[2]), .Q(\wl_tap_count_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_tap_count_r_reg[3] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[3]), .Q(\wl_tap_count_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_tap_count_r_reg[4] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[4]), .Q(\wl_tap_count_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) \wl_tap_count_r_reg[5] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[5]), .Q(\wl_tap_count_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__17[1])); FDRE #( .INIT(1'b0)) wr_level_done_r1_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r1_reg_0), .Q(wr_level_done_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) wr_level_done_r2_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r1), .Q(wr_level_done_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) wr_level_done_r3_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r2), .Q(wr_level_done_r3), .R(1'b0)); FDRE #( .INIT(1'b0)) wr_level_done_r4_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r3), .Q(wr_level_done_r4), .R(1'b0)); FDRE #( .INIT(1'b0)) wr_level_done_r5_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r4), .Q(wr_level_done_r5), .R(1'b0)); LUT6 #( .INIT(64'hF5FFFFFFFFFFFFBB)) wr_level_done_r_i_2 (.I0(out[4]), .I1(wr_level_done0), .I2(p_0_in), .I3(out[3]), .I4(out[1]), .I5(out[0]), .O(wr_level_done_r_reg_0)); FDRE #( .INIT(1'b0)) wr_level_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[0]_1 ), .Q(wr_level_done_r1_reg_0), .R(SR[1])); (* syn_maxfan = "2" *) FDRE #( .INIT(1'b0)) wr_level_done_reg (.C(CLK), .CE(1'b1), .D(\single_rank.done_dqs_dec_reg_0 ), .Q(wrlvl_done_r_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) wr_level_start_r_reg (.C(CLK), .CE(1'b1), .D(wr_lvl_start_reg), .Q(wr_level_start_r), .R(1'b0)); LUT6 #( .INIT(64'h00000000AEAA00AA)) wrlvl_byte_done_i_1 (.I0(wrlvl_byte_done), .I1(wr_level_done_r3), .I2(wr_level_done_r4), .I3(wrlvl_byte_redo), .I4(wrlvl_byte_redo_r), .I5(rstdiv0_sync_r1_reg_rep__22), .O(wrlvl_byte_done_i_1_n_0)); FDRE #( .INIT(1'b0)) wrlvl_byte_done_reg (.C(CLK), .CE(1'b1), .D(wrlvl_byte_done_i_1_n_0), .Q(wrlvl_byte_done), .R(1'b0)); FDRE #( .INIT(1'b0)) wrlvl_byte_redo_r_reg (.C(CLK), .CE(1'b1), .D(wrlvl_byte_redo), .Q(wrlvl_byte_redo_r), .R(1'b0)); FDRE #( .INIT(1'b0)) wrlvl_final_r_reg (.C(CLK), .CE(1'b1), .D(wrlvl_final_mux), .Q(wrlvl_final_r), .R(1'b0)); LUT6 #( .INIT(64'h0000400000050005)) wrlvl_rank_done_r_i_2 (.I0(out[2]), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(p_0_in), .I5(out[4]), .O(wrlvl_rank_done_r_reg_0)); FDRE #( .INIT(1'b0)) wrlvl_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[2]_1 ), .Q(wrlvl_rank_done), .R(SR[0])); LUT4 #( .INIT(16'h0F40)) \wrlvl_redo_corse_inc[0]_i_1 (.I0(out[4]), .I1(out[2]), .I2(\wrlvl_redo_corse_inc[2]_i_4_n_0 ), .I3(wrlvl_redo_corse_inc__0[0]), .O(\wrlvl_redo_corse_inc[0]_i_1_n_0 )); LUT5 #( .INIT(32'h45FF1500)) \wrlvl_redo_corse_inc[1]_i_1 (.I0(out[4]), .I1(wrlvl_redo_corse_inc__0[0]), .I2(out[2]), .I3(\wrlvl_redo_corse_inc[2]_i_4_n_0 ), .I4(wrlvl_redo_corse_inc__0[1]), .O(\wrlvl_redo_corse_inc[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0074FFFF00B80000)) \wrlvl_redo_corse_inc[2]_i_1 (.I0(\wrlvl_redo_corse_inc[2]_i_2_n_0 ), .I1(out[2]), .I2(\wrlvl_redo_corse_inc[2]_i_3_n_0 ), .I3(out[4]), .I4(\wrlvl_redo_corse_inc[2]_i_4_n_0 ), .I5(wrlvl_redo_corse_inc__0[2]), .O(\wrlvl_redo_corse_inc[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair333" *) LUT2 #( .INIT(4'h1)) \wrlvl_redo_corse_inc[2]_i_2 (.I0(wrlvl_redo_corse_inc__0[0]), .I1(wrlvl_redo_corse_inc__0[1]), .O(\wrlvl_redo_corse_inc[2]_i_2_n_0 )); LUT3 #( .INIT(8'hD5)) \wrlvl_redo_corse_inc[2]_i_3 (.I0(early1_data_reg_0), .I1(\wrlvl_redo_corse_inc_reg[2]_0 [0]), .I2(\wrlvl_redo_corse_inc_reg[2]_0 [1]), .O(\wrlvl_redo_corse_inc[2]_i_3_n_0 )); LUT6 #( .INIT(64'h00000020A0A00020)) \wrlvl_redo_corse_inc[2]_i_4 (.I0(\wrlvl_redo_corse_inc[2]_i_7_n_0 ), .I1(early1_data_reg), .I2(wrlvl_byte_redo), .I3(wrlvl_byte_redo_r), .I4(out[2]), .I5(\FSM_sequential_wl_state_r[2]_i_6_n_0 ), .O(\wrlvl_redo_corse_inc[2]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wrlvl_redo_corse_inc[2]_i_5 (.I0(\final_coarse_tap_reg_n_0_[3][1] ), .I1(\final_coarse_tap_reg_n_0_[1][1] ), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\final_coarse_tap_reg_n_0_[2][1] ), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\final_coarse_tap_reg_n_0_[0][1] ), .O(\wrlvl_redo_corse_inc_reg[2]_0 [0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wrlvl_redo_corse_inc[2]_i_6 (.I0(\final_coarse_tap_reg_n_0_[3][2] ), .I1(\final_coarse_tap_reg_n_0_[1][2] ), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\final_coarse_tap_reg_n_0_[2][2] ), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\final_coarse_tap_reg_n_0_[0][2] ), .O(\wrlvl_redo_corse_inc_reg[2]_0 [1])); LUT4 #( .INIT(16'h0001)) \wrlvl_redo_corse_inc[2]_i_7 (.I0(out[4]), .I1(out[3]), .I2(out[0]), .I3(out[1]), .O(\wrlvl_redo_corse_inc[2]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \wrlvl_redo_corse_inc_reg[0] (.C(CLK), .CE(1'b1), .D(\wrlvl_redo_corse_inc[0]_i_1_n_0 ), .Q(wrlvl_redo_corse_inc__0[0]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wrlvl_redo_corse_inc_reg[1] (.C(CLK), .CE(1'b1), .D(\wrlvl_redo_corse_inc[1]_i_1_n_0 ), .Q(wrlvl_redo_corse_inc__0[1]), .R(rstdiv0_sync_r1_reg_rep__17[0])); FDRE #( .INIT(1'b0)) \wrlvl_redo_corse_inc_reg[2] (.C(CLK), .CE(1'b1), .D(\wrlvl_redo_corse_inc[2]_i_1_n_0 ), .Q(wrlvl_redo_corse_inc__0[2]), .R(rstdiv0_sync_r1_reg_rep__17[0])); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_prbs_gen" *) module ddr3_ifmig_7series_v4_0_ddr_prbs_gen (\rd_addr_reg[0]_0 , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] , Q, \gen_mux_rd[0].compare_data_rise0_r1_reg[0] , \gen_mux_rd[1].compare_data_rise0_r1_reg[1] , \gen_mux_rd[2].compare_data_rise0_r1_reg[2] , \gen_mux_rd[3].compare_data_rise0_r1_reg[3] , \gen_mux_rd[4].compare_data_rise0_r1_reg[4] , \gen_mux_rd[5].compare_data_rise0_r1_reg[5] , \gen_mux_rd[6].compare_data_rise0_r1_reg[6] , \gen_mux_rd[7].compare_data_rise0_r1_reg[7] , \gen_mux_rd[0].compare_data_fall0_r1_reg[0] , \gen_mux_rd[1].compare_data_fall0_r1_reg[1] , \gen_mux_rd[2].compare_data_fall0_r1_reg[2] , \gen_mux_rd[3].compare_data_fall0_r1_reg[3] , \gen_mux_rd[4].compare_data_fall0_r1_reg[4] , \gen_mux_rd[5].compare_data_fall0_r1_reg[5] , \gen_mux_rd[6].compare_data_fall0_r1_reg[6] , \gen_mux_rd[7].compare_data_fall0_r1_reg[7] , \gen_mux_rd[0].compare_data_rise1_r1_reg[0] , \gen_mux_rd[1].compare_data_rise1_r1_reg[1] , \gen_mux_rd[2].compare_data_rise1_r1_reg[2] , \gen_mux_rd[3].compare_data_rise1_r1_reg[3] , \gen_mux_rd[4].compare_data_rise1_r1_reg[4] , \gen_mux_rd[5].compare_data_rise1_r1_reg[5] , \gen_mux_rd[6].compare_data_rise1_r1_reg[6] , \gen_mux_rd[7].compare_data_rise1_r1_reg[7] , \gen_mux_rd[0].compare_data_fall1_r1_reg[0] , \gen_mux_rd[1].compare_data_fall1_r1_reg[1] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] , \gen_mux_rd[3].compare_data_fall1_r1_reg[3] , \gen_mux_rd[4].compare_data_fall1_r1_reg[4] , \gen_mux_rd[5].compare_data_fall1_r1_reg[5] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] , \gen_mux_rd[7].compare_data_fall1_r1_reg[7] , \gen_mux_rd[0].compare_data_rise2_r1_reg[0] , \gen_mux_rd[1].compare_data_rise2_r1_reg[1] , \gen_mux_rd[2].compare_data_rise2_r1_reg[2] , \gen_mux_rd[3].compare_data_rise2_r1_reg[3] , \gen_mux_rd[4].compare_data_rise2_r1_reg[4] , \gen_mux_rd[5].compare_data_rise2_r1_reg[5] , \gen_mux_rd[6].compare_data_rise2_r1_reg[6] , \gen_mux_rd[7].compare_data_rise2_r1_reg[7] , \gen_mux_rd[0].compare_data_fall2_r1_reg[0] , \gen_mux_rd[1].compare_data_fall2_r1_reg[1] , \gen_mux_rd[2].compare_data_fall2_r1_reg[2] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] , \gen_mux_rd[4].compare_data_fall2_r1_reg[4] , \gen_mux_rd[5].compare_data_fall2_r1_reg[5] , \gen_mux_rd[6].compare_data_fall2_r1_reg[6] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] , \gen_mux_rd[0].compare_data_rise3_r1_reg[0] , \gen_mux_rd[1].compare_data_rise3_r1_reg[1] , \gen_mux_rd[2].compare_data_rise3_r1_reg[2] , \gen_mux_rd[3].compare_data_rise3_r1_reg[3] , \gen_mux_rd[4].compare_data_rise3_r1_reg[4] , \gen_mux_rd[5].compare_data_rise3_r1_reg[5] , \gen_mux_rd[6].compare_data_rise3_r1_reg[6] , \gen_mux_rd[7].compare_data_rise3_r1_reg[7] , \gen_mux_rd[0].compare_data_fall3_r1_reg[0] , \gen_mux_rd[1].compare_data_fall3_r1_reg[1] , \gen_mux_rd[2].compare_data_fall3_r1_reg[2] , \gen_mux_rd[3].compare_data_fall3_r1_reg[3] , \gen_mux_rd[4].compare_data_fall3_r1_reg[4] , \gen_mux_rd[5].compare_data_fall3_r1_reg[5] , \gen_mux_rd[6].compare_data_fall3_r1_reg[6] , \gen_mux_rd[7].compare_data_fall3_r1_reg[7] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , CLK, rdlvl_stg1_done_int_reg, wrcal_done_reg, first_rdlvl_pat_r, oclkdelay_calib_done_r_reg, \rd_addr_reg[3]_0 , rstdiv0_sync_r1_reg_rep__19, D, SR, E); output \rd_addr_reg[0]_0 ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ; output [0:0]Q; output \gen_mux_rd[0].compare_data_rise0_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise0_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise0_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise0_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise0_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise0_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise0_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise0_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall0_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall0_r1_reg[1] ; output \gen_mux_rd[2].compare_data_fall0_r1_reg[2] ; output \gen_mux_rd[3].compare_data_fall0_r1_reg[3] ; output \gen_mux_rd[4].compare_data_fall0_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall0_r1_reg[5] ; output \gen_mux_rd[6].compare_data_fall0_r1_reg[6] ; output \gen_mux_rd[7].compare_data_fall0_r1_reg[7] ; output \gen_mux_rd[0].compare_data_rise1_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise1_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise1_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise1_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise1_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise1_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise1_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise1_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall1_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall1_r1_reg[1] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ; output \gen_mux_rd[3].compare_data_fall1_r1_reg[3] ; output \gen_mux_rd[4].compare_data_fall1_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall1_r1_reg[5] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ; output \gen_mux_rd[7].compare_data_fall1_r1_reg[7] ; output \gen_mux_rd[0].compare_data_rise2_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise2_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise2_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise2_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise2_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise2_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise2_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise2_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall2_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall2_r1_reg[1] ; output \gen_mux_rd[2].compare_data_fall2_r1_reg[2] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ; output \gen_mux_rd[4].compare_data_fall2_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall2_r1_reg[5] ; output \gen_mux_rd[6].compare_data_fall2_r1_reg[6] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; output \gen_mux_rd[0].compare_data_rise3_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise3_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise3_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise3_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise3_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise3_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise3_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise3_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall3_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall3_r1_reg[1] ; output \gen_mux_rd[2].compare_data_fall3_r1_reg[2] ; output \gen_mux_rd[3].compare_data_fall3_r1_reg[3] ; output \gen_mux_rd[4].compare_data_fall3_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall3_r1_reg[5] ; output \gen_mux_rd[6].compare_data_fall3_r1_reg[6] ; output \gen_mux_rd[7].compare_data_fall3_r1_reg[7] ; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input CLK; input rdlvl_stg1_done_int_reg; input wrcal_done_reg; input first_rdlvl_pat_r; input oclkdelay_calib_done_r_reg; input \rd_addr_reg[3]_0 ; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [7:0]D; input [0:0]SR; input [0:0]E; wire CLK; wire [7:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire \dout_o[0]_i_1_n_0 ; wire \dout_o[0]_i_2_n_0 ; wire \dout_o[0]_i_3_n_0 ; wire \dout_o[0]_i_4_n_0 ; wire \dout_o[10]_i_1_n_0 ; wire \dout_o[10]_i_2_n_0 ; wire \dout_o[10]_i_3_n_0 ; wire \dout_o[11]_i_1_n_0 ; wire \dout_o[11]_i_2_n_0 ; wire \dout_o[11]_i_3_n_0 ; wire \dout_o[11]_i_4_n_0 ; wire \dout_o[12]_i_1_n_0 ; wire \dout_o[12]_i_2_n_0 ; wire \dout_o[12]_i_3_n_0 ; wire \dout_o[12]_i_4_n_0 ; wire \dout_o[13]_i_1_n_0 ; wire \dout_o[13]_i_2_n_0 ; wire \dout_o[13]_i_3_n_0 ; wire \dout_o[13]_i_4_n_0 ; wire \dout_o[14]_i_1_n_0 ; wire \dout_o[14]_i_2_n_0 ; wire \dout_o[14]_i_3_n_0 ; wire \dout_o[14]_i_4_n_0 ; wire \dout_o[15]_i_1_n_0 ; wire \dout_o[15]_i_2_n_0 ; wire \dout_o[15]_i_3_n_0 ; wire \dout_o[15]_i_4_n_0 ; wire \dout_o[1]_i_1_n_0 ; wire \dout_o[1]_i_2_n_0 ; wire \dout_o[1]_i_3_n_0 ; wire \dout_o[1]_i_4_n_0 ; wire \dout_o[2]_i_1_n_0 ; wire \dout_o[2]_i_2_n_0 ; wire \dout_o[2]_i_3_n_0 ; wire \dout_o[2]_i_4_n_0 ; wire \dout_o[3]_i_1_n_0 ; wire \dout_o[3]_i_2_n_0 ; wire \dout_o[3]_i_3_n_0 ; wire \dout_o[3]_i_4_n_0 ; wire \dout_o[4]_i_1_n_0 ; wire \dout_o[4]_i_2_n_0 ; wire \dout_o[4]_i_3_n_0 ; wire \dout_o[4]_i_4_n_0 ; wire \dout_o[5]_i_1_n_0 ; wire \dout_o[5]_i_2_n_0 ; wire \dout_o[5]_i_3_n_0 ; wire \dout_o[5]_i_4_n_0 ; wire \dout_o[6]_i_1_n_0 ; wire \dout_o[6]_i_2_n_0 ; wire \dout_o[6]_i_3_n_0 ; wire \dout_o[6]_i_4_n_0 ; wire \dout_o[7]_i_1_n_0 ; wire \dout_o[7]_i_2_n_0 ; wire \dout_o[7]_i_3_n_0 ; wire \dout_o[7]_i_4_n_0 ; wire \dout_o[8]_i_1_n_0 ; wire \dout_o[8]_i_2_n_0 ; wire \dout_o[8]_i_3_n_0 ; wire \dout_o[8]_i_4_n_0 ; wire \dout_o[9]_i_1_n_0 ; wire \dout_o[9]_i_2_n_0 ; wire \dout_o[9]_i_3_n_0 ; wire \dout_o[9]_i_4_n_0 ; wire \dout_o_reg_n_0_[0] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire first_rdlvl_pat_r; wire \gen_mux_rd[0].compare_data_fall0_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_fall1_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_fall2_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_fall3_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise0_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise1_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise2_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise3_r1_reg[0] ; wire \gen_mux_rd[1].compare_data_fall0_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_fall1_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_fall2_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_fall3_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise0_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise1_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise2_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise3_r1_reg[1] ; wire \gen_mux_rd[2].compare_data_fall0_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_fall2_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_fall3_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise0_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise1_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise2_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise3_r1_reg[2] ; wire \gen_mux_rd[3].compare_data_fall0_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_fall1_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_fall3_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise0_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise1_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise2_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise3_r1_reg[3] ; wire \gen_mux_rd[4].compare_data_fall0_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_fall1_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_fall2_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_fall3_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise0_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise1_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise2_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise3_r1_reg[4] ; wire \gen_mux_rd[5].compare_data_fall0_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_fall1_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_fall2_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_fall3_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise0_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise1_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise2_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise3_r1_reg[5] ; wire \gen_mux_rd[6].compare_data_fall0_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_fall2_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_fall3_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise0_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise1_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise2_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise3_r1_reg[6] ; wire \gen_mux_rd[7].compare_data_fall0_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_fall1_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_fall3_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise0_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise1_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise2_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise3_r1_reg[7] ; wire oclkdelay_calib_done_r_reg; wire p_0_in102_in; wire p_0_in106_in; wire p_0_in110_in; wire p_0_in114_in; wire p_0_in118_in; wire p_0_in122_in; wire p_0_in94_in; wire p_0_in98_in; wire p_1_in; wire p_1_in124_in; wire p_1_in190_in; wire p_1_in256_in; wire p_1_in322_in; wire p_1_in388_in; wire p_1_in454_in; wire p_1_in520_in; wire [7:0]p_1_in__0; wire p_2_in; wire p_2_in126_in; wire p_2_in192_in; wire p_2_in258_in; wire p_2_in324_in; wire p_2_in390_in; wire p_2_in456_in; wire \rd_addr[7]_i_4_n_0 ; wire \rd_addr[7]_i_5_n_0 ; wire \rd_addr[7]_i_6_n_0 ; wire \rd_addr_reg[0]_0 ; wire \rd_addr_reg[3]_0 ; wire \rd_addr_reg_n_0_[0] ; wire \rd_addr_reg_n_0_[1] ; wire \rd_addr_reg_n_0_[2] ; wire \rd_addr_reg_n_0_[4] ; wire \rd_addr_reg_n_0_[5] ; wire \rd_addr_reg_n_0_[6] ; wire \rd_addr_reg_n_0_[7] ; wire \rd_addr_reg_rep_n_0_[0] ; wire \rd_addr_reg_rep_n_0_[1] ; wire \rd_addr_reg_rep_n_0_[2] ; wire \rd_addr_reg_rep_n_0_[3] ; wire \rd_addr_reg_rep_n_0_[4] ; wire \rd_addr_reg_rep_n_0_[5] ; wire \rd_addr_reg_rep_n_0_[6] ; wire \rd_addr_reg_rep_n_0_[7] ; wire rdlvl_stg1_done_int_reg; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire wrcal_done_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ; LUT5 #( .INIT(32'hFCBBFC88)) \dout_o[0]_i_1 (.I0(\dout_o[0]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[0]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[0]_i_4_n_0 ), .O(\dout_o[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFBA702DC40FD7BA7)) \dout_o[0]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF941DDE1)) \dout_o[0]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[0]_i_3_n_0 )); LUT6 #( .INIT(64'h5F74ABA8D4EB4862)) \dout_o[0]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[0]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[10]_i_1 (.I0(\dout_o[12]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[10]_i_2_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[10]_i_3_n_0 ), .O(\dout_o[10]_i_1_n_0 )); LUT6 #( .INIT(64'h000000004599CD27)) \dout_o[10]_i_2 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[10]_i_2_n_0 )); LUT6 #( .INIT(64'h139126016C0923FA)) \dout_o[10]_i_3 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[10]_i_3_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[11]_i_1 (.I0(\dout_o[11]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[11]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[11]_i_4_n_0 ), .O(\dout_o[11]_i_1_n_0 )); LUT6 #( .INIT(64'h713DD3CC4AE43A65)) \dout_o[11]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[11]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000322002AD)) \dout_o[11]_i_3 (.I0(\rd_addr_reg_rep_n_0_[1] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[11]_i_3_n_0 )); LUT6 #( .INIT(64'h7BB6E4333589857B)) \dout_o[11]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[1] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[11]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[12]_i_1 (.I0(\dout_o[12]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[12]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[12]_i_4_n_0 ), .O(\dout_o[12]_i_1_n_0 )); LUT6 #( .INIT(64'h9100E82800132190)) \dout_o[12]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[12]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000031C1E208)) \dout_o[12]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[12]_i_3_n_0 )); LUT6 #( .INIT(64'h447C4014C71C60A6)) \dout_o[12]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[12]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[13]_i_1 (.I0(\dout_o[13]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[13]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[13]_i_4_n_0 ), .O(\dout_o[13]_i_1_n_0 )); LUT6 #( .INIT(64'h5D37E7F8E29A3F4D)) \dout_o[13]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[2] ), .I2(\rd_addr_reg_rep_n_0_[3] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[13]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000040055161)) \dout_o[13]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[13]_i_3_n_0 )); LUT6 #( .INIT(64'h6EEDFF5CF2C694A7)) \dout_o[13]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[13]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[14]_i_1 (.I0(\dout_o[14]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[14]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[14]_i_4_n_0 ), .O(\dout_o[14]_i_1_n_0 )); LUT6 #( .INIT(64'h9100682100130190)) \dout_o[14]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[14]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000118A8B19)) \dout_o[14]_i_3 (.I0(\rd_addr_reg_rep_n_0_[1] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[14]_i_3_n_0 )); LUT6 #( .INIT(64'hD473D375410D7424)) \dout_o[14]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[14]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[15]_i_1 (.I0(\dout_o[15]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[15]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[15]_i_4_n_0 ), .O(\dout_o[15]_i_1_n_0 )); LUT6 #( .INIT(64'h5D27F5EADA9A3F4D)) \dout_o[15]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[2] ), .I2(\rd_addr_reg_rep_n_0_[3] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[15]_i_2_n_0 )); LUT6 #( .INIT(64'h000000004115533E)) \dout_o[15]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[15]_i_3_n_0 )); LUT6 #( .INIT(64'h5EF9FF567BFFCDB5)) \dout_o[15]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[15]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[1]_i_1 (.I0(\dout_o[1]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[1]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[1]_i_4_n_0 ), .O(\dout_o[1]_i_1_n_0 )); LUT6 #( .INIT(64'hE7E55AE75A58865A)) \dout_o[1]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000051880521)) \dout_o[1]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[1]_i_3_n_0 )); LUT6 #( .INIT(64'h7ADF52E8C4A8E711)) \dout_o[1]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[1]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[2]_i_1 (.I0(\dout_o[2]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[2]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[2]_i_4_n_0 ), .O(\dout_o[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFB02235842E57B02)) \dout_o[2]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[2]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000020DCBD5)) \dout_o[2]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[2]_i_3_n_0 )); LUT6 #( .INIT(64'hCF45D0CFCE2B8950)) \dout_o[2]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[2]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[3]_i_1 (.I0(\dout_o[3]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[3]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[3]_i_4_n_0 ), .O(\dout_o[3]_i_1_n_0 )); LUT6 #( .INIT(64'h46E55AC658188658)) \dout_o[3]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[3]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000019C0421)) \dout_o[3]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[3]_i_3_n_0 )); LUT6 #( .INIT(64'h2DCA4E194B652751)) \dout_o[3]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[1] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[3]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[4]_i_1 (.I0(\dout_o[4]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[4]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[4]_i_4_n_0 ), .O(\dout_o[4]_i_1_n_0 )); LUT6 #( .INIT(64'hD87BBD58DE86587B)) \dout_o[4]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[4]_i_2_n_0 )); LUT6 #( .INIT(64'h000000000455F0E2)) \dout_o[4]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[0] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[4]_i_3_n_0 )); LUT6 #( .INIT(64'h1A563E3E1BBEA40C)) \dout_o[4]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[5]_i_1 (.I0(\dout_o[5]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[5]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[5]_i_4_n_0 ), .O(\dout_o[5]_i_1_n_0 )); LUT6 #( .INIT(64'h42588642FDA55AFD)) \dout_o[5]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000013A810A9)) \dout_o[5]_i_3 (.I0(\rd_addr_reg_rep_n_0_[1] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[5]_i_3_n_0 )); LUT6 #( .INIT(64'h183B5DF6A40A3E0D)) \dout_o[5]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[5]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[6]_i_1 (.I0(\dout_o[6]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[6]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[6]_i_4_n_0 ), .O(\dout_o[6]_i_1_n_0 )); LUT6 #( .INIT(64'hA35A585A84A7235A)) \dout_o[6]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[6]_i_2_n_0 )); LUT6 #( .INIT(64'h000000004441C9B1)) \dout_o[6]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[6]_i_3_n_0 )); LUT6 #( .INIT(64'h00D98F5FB527B08E)) \dout_o[6]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[6]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[7]_i_1 (.I0(\dout_o[7]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[7]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[7]_i_4_n_0 ), .O(\dout_o[7]_i_1_n_0 )); LUT6 #( .INIT(64'h5C00BF1AFFA5DC00)) \dout_o[7]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[7]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000016D00494)) \dout_o[7]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[7]_i_3_n_0 )); LUT6 #( .INIT(64'hAA852B305155E79F)) \dout_o[7]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[7]_i_4_n_0 )); LUT5 #( .INIT(32'hFCBBFC88)) \dout_o[8]_i_1 (.I0(\dout_o[8]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[8]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[8]_i_4_n_0 ), .O(\dout_o[8]_i_1_n_0 )); LUT6 #( .INIT(64'h91C9002800211311)) \dout_o[8]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[8]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD8D3F245)) \dout_o[8]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[8]_i_3_n_0 )); LUT6 #( .INIT(64'h0A06800432120528)) \dout_o[8]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[2] ), .O(\dout_o[8]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[9]_i_1 (.I0(\dout_o[9]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[9]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[9]_i_4_n_0 ), .O(\dout_o[9]_i_1_n_0 )); LUT6 #( .INIT(64'hF3F5C3DC0AE47A65)) \dout_o[9]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[9]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000040E06D5)) \dout_o[9]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[9]_i_3_n_0 )); LUT6 #( .INIT(64'h20350802BEE285FB)) \dout_o[9]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \dout_o_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o[0]_i_1_n_0 ), .Q(\dout_o_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[10] (.C(CLK), .CE(1'b1), .D(\dout_o[10]_i_1_n_0 ), .Q(p_1_in388_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[11] (.C(CLK), .CE(1'b1), .D(\dout_o[11]_i_1_n_0 ), .Q(p_1_in322_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[12] (.C(CLK), .CE(1'b1), .D(\dout_o[12]_i_1_n_0 ), .Q(p_1_in256_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[13] (.C(CLK), .CE(1'b1), .D(\dout_o[13]_i_1_n_0 ), .Q(p_1_in190_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[14] (.C(CLK), .CE(1'b1), .D(\dout_o[14]_i_1_n_0 ), .Q(p_1_in124_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[15] (.C(CLK), .CE(1'b1), .D(\dout_o[15]_i_1_n_0 ), .Q(p_1_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o[1]_i_1_n_0 ), .Q(p_2_in456_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o[2]_i_1_n_0 ), .Q(p_2_in390_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o[3]_i_1_n_0 ), .Q(p_2_in324_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o[4]_i_1_n_0 ), .Q(p_2_in258_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o[5]_i_1_n_0 ), .Q(p_2_in192_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o[6]_i_1_n_0 ), .Q(p_2_in126_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o[7]_i_1_n_0 ), .Q(p_2_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[8] (.C(CLK), .CE(1'b1), .D(\dout_o[8]_i_1_n_0 ), .Q(p_1_in520_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \dout_o_reg[9] (.C(CLK), .CE(1'b1), .D(\dout_o[9]_i_1_n_0 ), .Q(p_1_in454_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair683" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall0_r1[0]_i_1 (.I0(p_2_in126_in), .I1(p_0_in94_in), .I2(p_1_in124_in), .O(\gen_mux_rd[0].compare_data_fall0_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair636" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall1_r1[0]_i_1 (.I0(p_2_in258_in), .I1(p_0_in94_in), .I2(p_1_in256_in), .O(\gen_mux_rd[0].compare_data_fall1_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair690" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall2_r1[0]_i_1 (.I0(p_2_in390_in), .I1(p_0_in94_in), .I2(p_1_in388_in), .O(\gen_mux_rd[0].compare_data_fall2_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair659" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall3_r1[0]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in94_in), .I2(p_1_in520_in), .O(\gen_mux_rd[0].compare_data_fall3_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair644" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise0_r1[0]_i_1 (.I0(p_2_in), .I1(p_0_in94_in), .I2(p_1_in), .O(\gen_mux_rd[0].compare_data_rise0_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair679" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise1_r1[0]_i_1 (.I0(p_2_in192_in), .I1(p_0_in94_in), .I2(p_1_in190_in), .O(\gen_mux_rd[0].compare_data_rise1_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair635" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise2_r1[0]_i_1 (.I0(p_2_in324_in), .I1(p_0_in94_in), .I2(p_1_in322_in), .O(\gen_mux_rd[0].compare_data_rise2_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair672" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise3_r1[0]_i_1 (.I0(p_2_in456_in), .I1(p_0_in94_in), .I2(p_1_in454_in), .O(\gen_mux_rd[0].compare_data_rise3_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair688" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall0_r1[1]_i_1 (.I0(p_2_in126_in), .I1(p_0_in98_in), .I2(p_1_in124_in), .O(\gen_mux_rd[1].compare_data_fall0_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair685" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall1_r1[1]_i_1 (.I0(p_2_in258_in), .I1(p_0_in98_in), .I2(p_1_in256_in), .O(\gen_mux_rd[1].compare_data_fall1_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair692" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall2_r1[1]_i_1 (.I0(p_2_in390_in), .I1(p_0_in98_in), .I2(p_1_in388_in), .O(\gen_mux_rd[1].compare_data_fall2_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair638" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall3_r1[1]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in98_in), .I2(p_1_in520_in), .O(\gen_mux_rd[1].compare_data_fall3_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair687" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise0_r1[1]_i_1 (.I0(p_2_in), .I1(p_0_in98_in), .I2(p_1_in), .O(\gen_mux_rd[1].compare_data_rise0_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair648" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise1_r1[1]_i_1 (.I0(p_2_in192_in), .I1(p_0_in98_in), .I2(p_1_in190_in), .O(\gen_mux_rd[1].compare_data_rise1_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair691" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise2_r1[1]_i_1 (.I0(p_2_in324_in), .I1(p_0_in98_in), .I2(p_1_in322_in), .O(\gen_mux_rd[1].compare_data_rise2_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair677" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise3_r1[1]_i_1 (.I0(p_2_in456_in), .I1(p_0_in98_in), .I2(p_1_in454_in), .O(\gen_mux_rd[1].compare_data_rise3_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair662" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_fall0_r1[2]_i_1 (.I0(p_2_in126_in), .I1(p_0_in102_in), .I2(p_1_in124_in), .O(\gen_mux_rd[2].compare_data_fall0_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair640" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_fall2_r1[2]_i_1 (.I0(p_2_in390_in), .I1(p_0_in102_in), .I2(p_1_in388_in), .O(\gen_mux_rd[2].compare_data_fall2_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair684" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_fall3_r1[2]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in102_in), .I2(p_1_in520_in), .O(\gen_mux_rd[2].compare_data_fall3_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair661" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise0_r1[2]_i_1 (.I0(p_2_in), .I1(p_0_in102_in), .I2(p_1_in), .O(\gen_mux_rd[2].compare_data_rise0_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair652" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise1_r1[2]_i_1 (.I0(p_2_in192_in), .I1(p_0_in102_in), .I2(p_1_in190_in), .O(\gen_mux_rd[2].compare_data_rise1_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair650" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise2_r1[2]_i_1 (.I0(p_2_in324_in), .I1(p_0_in102_in), .I2(p_1_in322_in), .O(\gen_mux_rd[2].compare_data_rise2_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair655" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise3_r1[2]_i_1 (.I0(p_2_in456_in), .I1(p_0_in102_in), .I2(p_1_in454_in), .O(\gen_mux_rd[2].compare_data_rise3_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair664" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_fall0_r1[3]_i_1 (.I0(p_2_in126_in), .I1(p_0_in106_in), .I2(p_1_in124_in), .O(\gen_mux_rd[3].compare_data_fall0_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair689" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_fall1_r1[3]_i_1 (.I0(p_2_in258_in), .I1(p_0_in106_in), .I2(p_1_in256_in), .O(\gen_mux_rd[3].compare_data_fall1_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair642" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_fall3_r1[3]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in106_in), .I2(p_1_in520_in), .O(\gen_mux_rd[3].compare_data_fall3_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair645" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise0_r1[3]_i_1 (.I0(p_2_in), .I1(p_0_in106_in), .I2(p_1_in), .O(\gen_mux_rd[3].compare_data_rise0_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair676" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise1_r1[3]_i_1 (.I0(p_2_in192_in), .I1(p_0_in106_in), .I2(p_1_in190_in), .O(\gen_mux_rd[3].compare_data_rise1_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair682" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise2_r1[3]_i_1 (.I0(p_2_in324_in), .I1(p_0_in106_in), .I2(p_1_in322_in), .O(\gen_mux_rd[3].compare_data_rise2_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair675" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise3_r1[3]_i_1 (.I0(p_2_in456_in), .I1(p_0_in106_in), .I2(p_1_in454_in), .O(\gen_mux_rd[3].compare_data_rise3_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair683" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall0_r1[4]_i_1 (.I0(p_2_in126_in), .I1(p_0_in110_in), .I2(p_1_in124_in), .O(\gen_mux_rd[4].compare_data_fall0_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair637" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall1_r1[4]_i_1 (.I0(p_2_in258_in), .I1(p_0_in110_in), .I2(p_1_in256_in), .O(\gen_mux_rd[4].compare_data_fall1_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair693" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall2_r1[4]_i_1 (.I0(p_2_in390_in), .I1(p_0_in110_in), .I2(p_1_in388_in), .O(\gen_mux_rd[4].compare_data_fall2_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair658" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall3_r1[4]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in110_in), .I2(p_1_in520_in), .O(\gen_mux_rd[4].compare_data_fall3_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair646" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise0_r1[4]_i_1 (.I0(p_2_in), .I1(p_0_in110_in), .I2(p_1_in), .O(\gen_mux_rd[4].compare_data_rise0_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair681" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise1_r1[4]_i_1 (.I0(p_2_in192_in), .I1(p_0_in110_in), .I2(p_1_in190_in), .O(\gen_mux_rd[4].compare_data_rise1_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair656" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise2_r1[4]_i_1 (.I0(p_2_in324_in), .I1(p_0_in110_in), .I2(p_1_in322_in), .O(\gen_mux_rd[4].compare_data_rise2_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair669" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise3_r1[4]_i_1 (.I0(p_2_in456_in), .I1(p_0_in110_in), .I2(p_1_in454_in), .O(\gen_mux_rd[4].compare_data_rise3_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair688" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall0_r1[5]_i_1 (.I0(p_2_in126_in), .I1(p_0_in114_in), .I2(p_1_in124_in), .O(\gen_mux_rd[5].compare_data_fall0_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair689" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall1_r1[5]_i_1 (.I0(p_2_in258_in), .I1(p_0_in114_in), .I2(p_1_in256_in), .O(\gen_mux_rd[5].compare_data_fall1_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair690" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall2_r1[5]_i_1 (.I0(p_2_in390_in), .I1(p_0_in114_in), .I2(p_1_in388_in), .O(\gen_mux_rd[5].compare_data_fall2_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair639" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall3_r1[5]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in114_in), .I2(p_1_in520_in), .O(\gen_mux_rd[5].compare_data_fall3_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair687" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise0_r1[5]_i_1 (.I0(p_2_in), .I1(p_0_in114_in), .I2(p_1_in), .O(\gen_mux_rd[5].compare_data_rise0_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair649" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise1_r1[5]_i_1 (.I0(p_2_in192_in), .I1(p_0_in114_in), .I2(p_1_in190_in), .O(\gen_mux_rd[5].compare_data_rise1_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair691" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise2_r1[5]_i_1 (.I0(p_2_in324_in), .I1(p_0_in114_in), .I2(p_1_in322_in), .O(\gen_mux_rd[5].compare_data_rise2_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair680" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise3_r1[5]_i_1 (.I0(p_2_in456_in), .I1(p_0_in114_in), .I2(p_1_in454_in), .O(\gen_mux_rd[5].compare_data_rise3_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair665" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_fall0_r1[6]_i_1 (.I0(p_2_in126_in), .I1(p_0_in118_in), .I2(p_1_in124_in), .O(\gen_mux_rd[6].compare_data_fall0_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair641" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_fall2_r1[6]_i_1 (.I0(p_2_in390_in), .I1(p_0_in118_in), .I2(p_1_in388_in), .O(\gen_mux_rd[6].compare_data_fall2_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair684" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_fall3_r1[6]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in118_in), .I2(p_1_in520_in), .O(\gen_mux_rd[6].compare_data_fall3_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair660" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise0_r1[6]_i_1 (.I0(p_2_in), .I1(p_0_in118_in), .I2(p_1_in), .O(\gen_mux_rd[6].compare_data_rise0_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair653" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise1_r1[6]_i_1 (.I0(p_2_in192_in), .I1(p_0_in118_in), .I2(p_1_in190_in), .O(\gen_mux_rd[6].compare_data_rise1_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair651" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise2_r1[6]_i_1 (.I0(p_2_in324_in), .I1(p_0_in118_in), .I2(p_1_in322_in), .O(\gen_mux_rd[6].compare_data_rise2_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair654" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise3_r1[6]_i_1 (.I0(p_2_in456_in), .I1(p_0_in118_in), .I2(p_1_in454_in), .O(\gen_mux_rd[6].compare_data_rise3_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair663" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_fall0_r1[7]_i_1 (.I0(p_2_in126_in), .I1(p_0_in122_in), .I2(p_1_in124_in), .O(\gen_mux_rd[7].compare_data_fall0_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair685" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_fall1_r1[7]_i_1 (.I0(p_2_in258_in), .I1(p_0_in122_in), .I2(p_1_in256_in), .O(\gen_mux_rd[7].compare_data_fall1_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair643" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_fall3_r1[7]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in122_in), .I2(p_1_in520_in), .O(\gen_mux_rd[7].compare_data_fall3_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair647" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise0_r1[7]_i_1 (.I0(p_2_in), .I1(p_0_in122_in), .I2(p_1_in), .O(\gen_mux_rd[7].compare_data_rise0_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair671" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise1_r1[7]_i_1 (.I0(p_2_in192_in), .I1(p_0_in122_in), .I2(p_1_in190_in), .O(\gen_mux_rd[7].compare_data_rise1_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair678" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise2_r1[7]_i_1 (.I0(p_2_in324_in), .I1(p_0_in122_in), .I2(p_1_in322_in), .O(\gen_mux_rd[7].compare_data_rise2_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair670" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise3_r1[7]_i_1 (.I0(p_2_in456_in), .I1(p_0_in122_in), .I2(p_1_in454_in), .O(\gen_mux_rd[7].compare_data_rise3_r1_reg[7] )); FDRE #( .INIT(1'b0)) phy_if_empty_r_reg (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .Q(\rd_addr_reg[0]_0 ), .R(1'b0)); LUT2 #( .INIT(4'h1)) \rd_addr[0]_i_1 (.I0(\rd_addr_reg_n_0_[0] ), .I1(\rd_addr[7]_i_5_n_0 ), .O(p_1_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair673" *) LUT2 #( .INIT(4'h6)) \rd_addr[1]_i_1 (.I0(\rd_addr_reg_n_0_[0] ), .I1(\rd_addr_reg_n_0_[1] ), .O(p_1_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair657" *) LUT4 #( .INIT(16'h1540)) \rd_addr[2]_i_1 (.I0(\rd_addr[7]_i_5_n_0 ), .I1(\rd_addr_reg_n_0_[0] ), .I2(\rd_addr_reg_n_0_[1] ), .I3(\rd_addr_reg_n_0_[2] ), .O(p_1_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair657" *) LUT5 #( .INIT(32'h15554000)) \rd_addr[3]_i_1 (.I0(\rd_addr[7]_i_5_n_0 ), .I1(\rd_addr_reg_n_0_[1] ), .I2(\rd_addr_reg_n_0_[0] ), .I3(\rd_addr_reg_n_0_[2] ), .I4(Q), .O(p_1_in__0[3])); LUT6 #( .INIT(64'h1555555540000000)) \rd_addr[4]_i_1 (.I0(\rd_addr[7]_i_5_n_0 ), .I1(\rd_addr_reg_n_0_[2] ), .I2(\rd_addr_reg_n_0_[0] ), .I3(\rd_addr_reg_n_0_[1] ), .I4(Q), .I5(\rd_addr_reg_n_0_[4] ), .O(p_1_in__0[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \rd_addr[5]_i_1 (.I0(\rd_addr_reg_n_0_[5] ), .I1(Q), .I2(\rd_addr_reg_n_0_[1] ), .I3(\rd_addr_reg_n_0_[0] ), .I4(\rd_addr_reg_n_0_[2] ), .I5(\rd_addr_reg_n_0_[4] ), .O(p_1_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair674" *) LUT2 #( .INIT(4'h6)) \rd_addr[6]_i_1 (.I0(\rd_addr_reg_n_0_[6] ), .I1(\rd_addr[7]_i_4_n_0 ), .O(p_1_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair674" *) LUT4 #( .INIT(16'h006A)) \rd_addr[7]_i_3 (.I0(\rd_addr_reg_n_0_[7] ), .I1(\rd_addr[7]_i_4_n_0 ), .I2(\rd_addr_reg_n_0_[6] ), .I3(\rd_addr[7]_i_5_n_0 ), .O(p_1_in__0[7])); LUT6 #( .INIT(64'h8000000000000000)) \rd_addr[7]_i_4 (.I0(\rd_addr_reg_n_0_[5] ), .I1(\rd_addr_reg_n_0_[4] ), .I2(\rd_addr_reg_n_0_[2] ), .I3(\rd_addr_reg_n_0_[0] ), .I4(\rd_addr_reg_n_0_[1] ), .I5(Q), .O(\rd_addr[7]_i_4_n_0 )); LUT5 #( .INIT(32'h00000010)) \rd_addr[7]_i_5 (.I0(\rd_addr[7]_i_6_n_0 ), .I1(\rd_addr_reg_n_0_[5] ), .I2(\rd_addr_reg_n_0_[7] ), .I3(\rd_addr_reg_n_0_[6] ), .I4(\rd_addr_reg[3]_0 ), .O(\rd_addr[7]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair673" *) LUT4 #( .INIT(16'hEFFF)) \rd_addr[7]_i_6 (.I0(\rd_addr_reg_n_0_[1] ), .I1(\rd_addr_reg_n_0_[0] ), .I2(\rd_addr_reg_n_0_[4] ), .I3(\rd_addr_reg_n_0_[2] ), .O(\rd_addr[7]_i_6_n_0 )); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[0] (.C(CLK), .CE(E), .D(p_1_in__0[0]), .Q(\rd_addr_reg_n_0_[0] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[1] (.C(CLK), .CE(E), .D(p_1_in__0[1]), .Q(\rd_addr_reg_n_0_[1] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[2] (.C(CLK), .CE(E), .D(p_1_in__0[2]), .Q(\rd_addr_reg_n_0_[2] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[3] (.C(CLK), .CE(E), .D(p_1_in__0[3]), .Q(Q), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[4] (.C(CLK), .CE(E), .D(p_1_in__0[4]), .Q(\rd_addr_reg_n_0_[4] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[5] (.C(CLK), .CE(E), .D(p_1_in__0[5]), .Q(\rd_addr_reg_n_0_[5] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[6] (.C(CLK), .CE(E), .D(p_1_in__0[6]), .Q(\rd_addr_reg_n_0_[6] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE #( .INIT(1'b0)) \rd_addr_reg[7] (.C(CLK), .CE(E), .D(p_1_in__0[7]), .Q(\rd_addr_reg_n_0_[7] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[0] (.C(CLK), .CE(E), .D(p_1_in__0[0]), .Q(\rd_addr_reg_rep_n_0_[0] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[1] (.C(CLK), .CE(E), .D(p_1_in__0[1]), .Q(\rd_addr_reg_rep_n_0_[1] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[2] (.C(CLK), .CE(E), .D(p_1_in__0[2]), .Q(\rd_addr_reg_rep_n_0_[2] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[3] (.C(CLK), .CE(E), .D(p_1_in__0[3]), .Q(\rd_addr_reg_rep_n_0_[3] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[4] (.C(CLK), .CE(E), .D(p_1_in__0[4]), .Q(\rd_addr_reg_rep_n_0_[4] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[5] (.C(CLK), .CE(E), .D(p_1_in__0[5]), .Q(\rd_addr_reg_rep_n_0_[5] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[6] (.C(CLK), .CE(E), .D(p_1_in__0[6]), .Q(\rd_addr_reg_rep_n_0_[6] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \rd_addr_reg_rep[7] (.C(CLK), .CE(E), .D(p_1_in__0[7]), .Q(\rd_addr_reg_rep_n_0_[7] ), .R(SR)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[24] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(p_0_in94_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[25] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(p_0_in98_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[26] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(p_0_in102_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[27] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(p_0_in106_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[28] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(p_0_in110_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[29] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(p_0_in114_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[30] (.C(CLK), .CE(1'b1), .D(D[6]), .Q(p_0_in118_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE #( .INIT(1'b0)) \victim_sel_rotate.sel_reg[31] (.C(CLK), .CE(1'b1), .D(D[7]), .Q(p_0_in122_in), .R(rstdiv0_sync_r1_reg_rep__19)); (* SOFT_HLUTNM = "soft_lutpair636" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1 (.I0(p_1_in256_in), .I1(p_0_in94_in), .I2(p_2_in258_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] )); (* SOFT_HLUTNM = "soft_lutpair666" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[121]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in98_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] )); (* SOFT_HLUTNM = "soft_lutpair686" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[122]_i_1 (.I0(p_2_in258_in), .I1(p_0_in102_in), .I2(p_1_in256_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] )); (* SOFT_HLUTNM = "soft_lutpair666" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[123]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in106_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] )); (* SOFT_HLUTNM = "soft_lutpair637" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1 (.I0(p_1_in256_in), .I1(p_0_in110_in), .I2(p_2_in258_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] )); (* SOFT_HLUTNM = "soft_lutpair667" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[125]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in114_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] )); (* SOFT_HLUTNM = "soft_lutpair686" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[126]_i_1 (.I0(p_2_in258_in), .I1(p_0_in118_in), .I2(p_1_in256_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] )); (* SOFT_HLUTNM = "soft_lutpair667" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[127]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in122_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] )); (* SOFT_HLUTNM = "soft_lutpair635" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[152]_i_1 (.I0(p_2_in324_in), .I1(p_0_in94_in), .I2(p_1_in322_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] )); LUT6 #( .INIT(64'hE200000000000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[153]_i_1 (.I0(p_1_in322_in), .I1(p_0_in98_in), .I2(p_2_in324_in), .I3(oclkdelay_calib_done_r_reg), .I4(wrcal_done_reg), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] )); (* SOFT_HLUTNM = "soft_lutpair650" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[154]_i_1 (.I0(p_1_in322_in), .I1(p_0_in102_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] )); (* SOFT_HLUTNM = "soft_lutpair682" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[155]_i_1 (.I0(p_1_in322_in), .I1(p_0_in106_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] )); (* SOFT_HLUTNM = "soft_lutpair656" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_2 (.I0(p_2_in324_in), .I1(p_0_in110_in), .I2(p_1_in322_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] )); LUT6 #( .INIT(64'hE200000000000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[157]_i_1 (.I0(p_1_in322_in), .I1(p_0_in114_in), .I2(p_2_in324_in), .I3(oclkdelay_calib_done_r_reg), .I4(wrcal_done_reg), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] )); (* SOFT_HLUTNM = "soft_lutpair651" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_2 (.I0(p_1_in322_in), .I1(p_0_in118_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] )); (* SOFT_HLUTNM = "soft_lutpair678" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[159]_i_1 (.I0(p_1_in322_in), .I1(p_0_in122_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] )); (* SOFT_HLUTNM = "soft_lutpair668" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in388_in), .I2(p_0_in94_in), .I3(p_2_in390_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] )); LUT6 #( .INIT(64'hF7FFF77777777777)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[185]_i_1 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(p_2_in390_in), .I3(p_0_in98_in), .I4(p_1_in388_in), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] )); (* SOFT_HLUTNM = "soft_lutpair640" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1 (.I0(p_1_in388_in), .I1(p_0_in102_in), .I2(p_2_in390_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] )); (* SOFT_HLUTNM = "soft_lutpair692" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1 (.I0(p_2_in390_in), .I1(p_0_in106_in), .I2(p_1_in388_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] )); (* SOFT_HLUTNM = "soft_lutpair668" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in388_in), .I2(p_0_in110_in), .I3(p_2_in390_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] )); LUT6 #( .INIT(64'hF7FFF77777777777)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[189]_i_1 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(p_2_in390_in), .I3(p_0_in114_in), .I4(p_1_in388_in), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] )); (* SOFT_HLUTNM = "soft_lutpair641" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1 (.I0(p_1_in388_in), .I1(p_0_in118_in), .I2(p_2_in390_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] )); (* SOFT_HLUTNM = "soft_lutpair693" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_2 (.I0(p_2_in390_in), .I1(p_0_in122_in), .I2(p_1_in388_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] )); (* SOFT_HLUTNM = "soft_lutpair672" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[216]_i_1 (.I0(p_1_in454_in), .I1(p_0_in94_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] )); (* SOFT_HLUTNM = "soft_lutpair677" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[217]_i_1 (.I0(p_1_in454_in), .I1(p_0_in98_in), .I2(p_2_in456_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] )); (* SOFT_HLUTNM = "soft_lutpair655" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[218]_i_1 (.I0(p_2_in456_in), .I1(p_0_in102_in), .I2(p_1_in454_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] )); (* SOFT_HLUTNM = "soft_lutpair675" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[219]_i_1 (.I0(p_1_in454_in), .I1(p_0_in106_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] )); (* SOFT_HLUTNM = "soft_lutpair669" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[220]_i_1 (.I0(p_1_in454_in), .I1(p_0_in110_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] )); (* SOFT_HLUTNM = "soft_lutpair680" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_2 (.I0(p_1_in454_in), .I1(p_0_in114_in), .I2(p_2_in456_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] )); (* SOFT_HLUTNM = "soft_lutpair654" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_2 (.I0(p_2_in456_in), .I1(p_0_in118_in), .I2(p_1_in454_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] )); (* SOFT_HLUTNM = "soft_lutpair670" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_2 (.I0(p_1_in454_in), .I1(p_0_in122_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] )); (* SOFT_HLUTNM = "soft_lutpair659" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1 (.I0(p_1_in520_in), .I1(p_0_in94_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] )); (* SOFT_HLUTNM = "soft_lutpair638" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1 (.I0(p_1_in520_in), .I1(p_0_in98_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] )); (* SOFT_HLUTNM = "soft_lutpair644" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[24]_i_1 (.I0(p_1_in), .I1(p_0_in94_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] )); (* SOFT_HLUTNM = "soft_lutpair642" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1 (.I0(p_1_in520_in), .I1(p_0_in106_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] )); (* SOFT_HLUTNM = "soft_lutpair658" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1 (.I0(p_1_in520_in), .I1(p_0_in110_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] )); (* SOFT_HLUTNM = "soft_lutpair639" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1 (.I0(p_1_in520_in), .I1(p_0_in114_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] )); (* SOFT_HLUTNM = "soft_lutpair643" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1 (.I0(p_1_in520_in), .I1(p_0_in122_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] )); LUT6 #( .INIT(64'hB800B8FFFFFFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[25]_i_1 (.I0(p_2_in), .I1(p_0_in98_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(first_rdlvl_pat_r), .I5(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] )); (* SOFT_HLUTNM = "soft_lutpair661" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[26]_i_1 (.I0(p_2_in), .I1(p_0_in102_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] )); (* SOFT_HLUTNM = "soft_lutpair645" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[27]_i_1 (.I0(p_1_in), .I1(p_0_in106_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] )); (* SOFT_HLUTNM = "soft_lutpair646" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[28]_i_1 (.I0(p_1_in), .I1(p_0_in110_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] )); LUT6 #( .INIT(64'hB800B8FFFFFFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[29]_i_1 (.I0(p_2_in), .I1(p_0_in114_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(first_rdlvl_pat_r), .I5(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] )); (* SOFT_HLUTNM = "soft_lutpair660" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[30]_i_1 (.I0(p_2_in), .I1(p_0_in118_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] )); (* SOFT_HLUTNM = "soft_lutpair647" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[31]_i_1 (.I0(p_1_in), .I1(p_0_in122_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] )); LUT6 #( .INIT(64'hC0CCC00088888888)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[57]_i_1 (.I0(first_rdlvl_pat_r), .I1(wrcal_done_reg), .I2(p_2_in126_in), .I3(p_0_in98_in), .I4(p_1_in124_in), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] )); (* SOFT_HLUTNM = "soft_lutpair662" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1 (.I0(p_1_in124_in), .I1(p_0_in102_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] )); (* SOFT_HLUTNM = "soft_lutpair664" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[59]_i_1 (.I0(p_1_in124_in), .I1(p_0_in106_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] )); LUT6 #( .INIT(64'hB8FFB80000000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[61]_i_1 (.I0(p_2_in126_in), .I1(p_0_in114_in), .I2(p_1_in124_in), .I3(rdlvl_stg1_done_int_reg), .I4(first_rdlvl_pat_r), .I5(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] )); (* SOFT_HLUTNM = "soft_lutpair665" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1 (.I0(p_1_in124_in), .I1(p_0_in118_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] )); (* SOFT_HLUTNM = "soft_lutpair663" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[63]_i_1 (.I0(p_1_in124_in), .I1(p_0_in122_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] )); (* SOFT_HLUTNM = "soft_lutpair679" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[88]_i_1 (.I0(p_1_in190_in), .I1(p_0_in94_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] )); (* SOFT_HLUTNM = "soft_lutpair648" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[89]_i_1 (.I0(p_1_in190_in), .I1(p_0_in98_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] )); (* SOFT_HLUTNM = "soft_lutpair652" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[90]_i_1 (.I0(p_1_in190_in), .I1(p_0_in102_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] )); (* SOFT_HLUTNM = "soft_lutpair676" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[91]_i_1 (.I0(p_1_in190_in), .I1(p_0_in106_in), .I2(p_2_in192_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] )); (* SOFT_HLUTNM = "soft_lutpair681" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[92]_i_1 (.I0(p_1_in190_in), .I1(p_0_in110_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] )); (* SOFT_HLUTNM = "soft_lutpair649" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[93]_i_1 (.I0(p_1_in190_in), .I1(p_0_in114_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] )); (* SOFT_HLUTNM = "soft_lutpair653" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[94]_i_1 (.I0(p_1_in190_in), .I1(p_0_in118_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] )); (* SOFT_HLUTNM = "soft_lutpair671" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[95]_i_1 (.I0(p_1_in190_in), .I1(p_0_in122_in), .I2(p_2_in192_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_infrastructure" *) module ddr3_ifmig_7series_v4_0_infrastructure (mmcm_locked, psdone, CLK, mmcm_ps_clk, freq_refclk, mem_refclk, sync_pulse, poc_sample_pd, rst_sync_r1, \stg3_tap_cnt_reg[0] , reset_reg, \simp_stg3_final_r_reg[17] , in0, \read_fifo.head_r_reg[0] , SR, \wrcal_dqs_cnt_r_reg[2] , SS, \cal2_state_r_reg[0] , cal2_if_reset_reg, cal2_prech_req_r_reg, \three_dec_max_limit_reg[11] , prbs_found_1st_edge_r_reg, rst_out_reg, \en_cnt_div4.enable_wrlvl_cnt_reg[2] , \complex_address_reg[0] , \init_state_r_reg[6] , \first_fail_taps_reg[0] , \pi_rdval_cnt_reg[0] , \gen_final_tap[2].final_val_reg[2][1] , \wl_tap_count_r_reg[0] , \victim_sel_rotate.sel_reg[31] , \last_master_r_reg[2] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , \wait_cnt_reg[3] , \wrcal_reads_reg[0] , \oneeighty_r_reg[0] , RST0, \stg3_r_reg[1] , \oneeighty_r_reg[0]_0 , pll_locked, pre_wait_r_reg, rtp_timer_ns1, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] , ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, \pi_rst_stg1_cal_r_reg[1] , \samp_edge_cnt0_r_reg[11] , \wait_cnt_r_reg[3] , \en_cnt_div4.enable_wrlvl_cnt_reg[4] , p_81_in, \wr_victim_sel_ocal_reg[2] , cnt_pwron_reset_done_r0, \wait_cnt_reg[3]_0 , E, mmcm_clk, AS, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , \lim_state_reg[0] , poc_backup_r_reg, \resume_wait_r_reg[10] , sm_r, pass_open_bank_r, pass_open_bank_r_0, insert_maint_r, bm_end_r1, bm_end_r1_1, fine_adjust_reg, samp_edge_cnt0_en_r, pi_cnt_dec, \en_cnt_div4.wrlvl_odt_reg , \row_cnt_victim_rotate.complex_row_cnt_reg[7] , wr_victim_inc_reg, phy_mc_go, po_cnt_dec); output mmcm_locked; output psdone; output CLK; output mmcm_ps_clk; output freq_refclk; output mem_refclk; output sync_pulse; output poc_sample_pd; output rst_sync_r1; output \stg3_tap_cnt_reg[0] ; output reset_reg; output \simp_stg3_final_r_reg[17] ; output in0; output \read_fifo.head_r_reg[0] ; output [0:0]SR; output \wrcal_dqs_cnt_r_reg[2] ; output [0:0]SS; output [0:0]\cal2_state_r_reg[0] ; output cal2_if_reset_reg; output cal2_prech_req_r_reg; output [0:0]\three_dec_max_limit_reg[11] ; output prbs_found_1st_edge_r_reg; output rst_out_reg; output \en_cnt_div4.enable_wrlvl_cnt_reg[2] ; output \complex_address_reg[0] ; output [0:0]\init_state_r_reg[6] ; output \first_fail_taps_reg[0] ; output [1:0]\pi_rdval_cnt_reg[0] ; output [0:0]\gen_final_tap[2].final_val_reg[2][1] ; output [1:0]\wl_tap_count_r_reg[0] ; output [0:0]\victim_sel_rotate.sel_reg[31] ; output \last_master_r_reg[2] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output \wait_cnt_reg[3] ; output \wrcal_reads_reg[0] ; output \oneeighty_r_reg[0] ; output RST0; output \stg3_r_reg[1] ; output [0:0]\oneeighty_r_reg[0]_0 ; output pll_locked; output pre_wait_r_reg; output rtp_timer_ns1; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ; output ras_timer_zero_r_reg; output ras_timer_zero_r_reg_0; output \pi_rst_stg1_cal_r_reg[1] ; output \samp_edge_cnt0_r_reg[11] ; output [0:0]\wait_cnt_r_reg[3] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[4] ; output p_81_in; output \wr_victim_sel_ocal_reg[2] ; output cnt_pwron_reset_done_r0; output [0:0]\wait_cnt_reg[3]_0 ; input [0:0]E; input mmcm_clk; input [0:0]AS; input \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input \lim_state_reg[0] ; input poc_backup_r_reg; input \resume_wait_r_reg[10] ; input sm_r; input pass_open_bank_r; input pass_open_bank_r_0; input insert_maint_r; input bm_end_r1; input bm_end_r1_1; input fine_adjust_reg; input samp_edge_cnt0_en_r; input pi_cnt_dec; input \en_cnt_div4.wrlvl_odt_reg ; input \row_cnt_victim_rotate.complex_row_cnt_reg[7] ; input wr_victim_inc_reg; input phy_mc_go; input po_cnt_dec; wire [0:0]AS; wire CLK; wire [0:0]E; wire RST0; wire RST0_0; wire [0:0]SR; wire [0:0]SS; wire bm_end_r1; wire bm_end_r1_1; wire cal2_if_reset_reg; wire cal2_prech_req_r_reg; wire [0:0]\cal2_state_r_reg[0] ; wire clk_div2_bufg_in; wire clk_pll_i; wire cnt_pwron_reset_done_r0; wire \complex_address_reg[0] ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ; wire \en_cnt_div4.wrlvl_odt_reg ; wire fine_adjust_reg; wire \first_fail_taps_reg[0] ; wire first_rising_ps_clk_ns; wire first_rising_ps_clk_r; wire freq_refclk; wire [0:0]\gen_final_tap[2].final_val_reg[2][1] ; wire \gen_mmcm.u_bufg_clk_div2_n_0 ; wire in0; wire [0:0]\init_state_r_reg[6] ; wire insert_maint_r; wire inv_poc_sample_ns0_out; wire inv_poc_sample_r; wire inv_poc_sample_r_i_2_n_0; wire \last_master_r_reg[2] ; wire \lim_state_reg[0] ; wire mem_refclk; wire mmcm_clk; wire mmcm_hi0_r; wire mmcm_hi0_r_i_1_n_0; wire mmcm_locked; wire mmcm_ps_clk; wire mmcm_ps_clk_bufg_in; wire \oneeighty_r_reg[0] ; wire [0:0]\oneeighty_r_reg[0]_0 ; wire [7:0]p_0_in__2; wire p_81_in; wire pass_open_bank_r; wire pass_open_bank_r_0; wire phy_mc_go; wire pi_cnt_dec; wire [1:0]\pi_rdval_cnt_reg[0] ; wire \pi_rst_stg1_cal_r_reg[1] ; wire pll_clk3; wire pll_clk3_out; wire pll_clkfbout; wire pll_locked; wire pll_locked_i; wire po_cnt_dec; wire poc_backup_r_reg; wire poc_sample_pd; wire poc_sample_pd_ns; wire poc_sample_pd_r_i_2_n_0; wire prbs_found_1st_edge_r_reg; wire pre_wait_r_reg; wire psdone; wire qcntr_ns; wire \qcntr_r[2]_i_1_n_0 ; wire \qcntr_r[3]_i_1_n_0 ; wire \qcntr_r[4]_i_1_n_0 ; wire \qcntr_r[5]_i_1_n_0 ; wire \qcntr_r[7]_i_3_n_0 ; wire [7:0]qcntr_r_reg__0; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire \read_fifo.head_r_reg[0] ; wire reset_reg; wire \resume_wait_r_reg[10] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[7] ; wire rst_out_reg; wire \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire [11:0]rst_sync_r; wire rst_sync_r1; wire [11:0]rstdiv0_sync_r; wire rstdiv0_sync_r1_reg_rep__0_n_0; wire rstdiv0_sync_r1_reg_rep__10_n_0; wire rstdiv0_sync_r1_reg_rep__11_n_0; wire rstdiv0_sync_r1_reg_rep__12_n_0; wire rstdiv0_sync_r1_reg_rep__13_n_0; wire rstdiv0_sync_r1_reg_rep__14_n_0; wire rstdiv0_sync_r1_reg_rep__15_n_0; wire rstdiv0_sync_r1_reg_rep__16_n_0; wire rstdiv0_sync_r1_reg_rep__17_n_0; wire rstdiv0_sync_r1_reg_rep__18_n_0; wire rstdiv0_sync_r1_reg_rep__19_n_0; wire rstdiv0_sync_r1_reg_rep__1_n_0; wire rstdiv0_sync_r1_reg_rep__20_n_0; wire rstdiv0_sync_r1_reg_rep__21_n_0; wire rstdiv0_sync_r1_reg_rep__22_n_0; wire rstdiv0_sync_r1_reg_rep__23_n_0; wire rstdiv0_sync_r1_reg_rep__24_n_0; wire rstdiv0_sync_r1_reg_rep__25_n_0; wire rstdiv0_sync_r1_reg_rep__2_n_0; wire rstdiv0_sync_r1_reg_rep__3_n_0; wire rstdiv0_sync_r1_reg_rep__4_n_0; wire rstdiv0_sync_r1_reg_rep__5_n_0; wire rstdiv0_sync_r1_reg_rep__6_n_0; wire rstdiv0_sync_r1_reg_rep__7_n_0; wire rstdiv0_sync_r1_reg_rep__8_n_0; wire rstdiv0_sync_r1_reg_rep__9_n_0; wire rstdiv0_sync_r1_reg_rep_n_0; wire [11:0]rstdiv2_sync_r; (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rstdiv2_sync_r1; wire rtp_timer_ns1; wire samp_edge_cnt0_en_r; wire \samp_edge_cnt0_r_reg[11] ; wire \simp_stg3_final_r_reg[17] ; wire sm_r; wire \stg3_r_reg[1] ; wire \stg3_tap_cnt_reg[0] ; wire sync_pulse; wire [0:0]\three_dec_max_limit_reg[11] ; wire [0:0]\victim_sel_rotate.sel_reg[31] ; wire [0:0]\wait_cnt_r_reg[3] ; wire \wait_cnt_reg[3] ; wire [0:0]\wait_cnt_reg[3]_0 ; wire [1:0]\wl_tap_count_r_reg[0] ; wire wr_victim_inc_reg; wire \wr_victim_sel_ocal_reg[2] ; wire \wrcal_dqs_cnt_r_reg[2] ; wire \wrcal_reads_reg[0] ; wire \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ; wire [15:0]\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ; wire NLW_plle2_i_CLKOUT4_UNCONNECTED; wire NLW_plle2_i_CLKOUT5_UNCONNECTED; wire NLW_plle2_i_DRDY_UNCONNECTED; wire [15:0]NLW_plle2_i_DO_UNCONNECTED; (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \FSM_sequential_sm_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__2_n_0), .O(\wrcal_dqs_cnt_r_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'hE)) act_wait_r_lcl_i_2__0 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(bm_end_r1_1), .O(ras_timer_zero_r_reg_0)); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'hE)) act_wait_r_lcl_i_3__0 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(bm_end_r1), .O(ras_timer_zero_r_reg)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \cal1_cnt_cpt_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__14_n_0), .O(\pi_rdval_cnt_reg[0] [1])); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) cal2_prech_req_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__6_n_0), .O(cal2_prech_req_r_reg)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \cal2_state_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__4_n_0), .O(\cal2_state_r_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) cke_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__1_n_0), .O(SR)); LUT2 #( .INIT(4'hB)) cnt_pwron_cke_done_r_i_3 (.I0(\wrcal_reads_reg[0] ), .I1(phy_mc_go), .O(cnt_pwron_reset_done_r0)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \complex_num_reads_dec[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__18_n_0), .O(\wl_tap_count_r_reg[0] [0])); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) complex_victim_inc_i_1 (.I0(rstdiv0_sync_r1_reg_rep__7_n_0), .O(\three_dec_max_limit_reg[11] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \dqs_count_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__17_n_0), .O(\wl_tap_count_r_reg[0] [1])); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__10_n_0), .O(\en_cnt_div4.enable_wrlvl_cnt_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'hE)) \en_cnt_div4.enable_wrlvl_cnt[4]_i_2 (.I0(\wrcal_reads_reg[0] ), .I1(\en_cnt_div4.wrlvl_odt_reg ), .O(\en_cnt_div4.enable_wrlvl_cnt_reg[4] )); LUT1 #( .INIT(2'h1)) first_rising_ps_clk_r_i_1 (.I0(reset_reg), .O(first_rising_ps_clk_ns)); FDRE #( .INIT(1'b0)) first_rising_ps_clk_r_reg (.C(mmcm_ps_clk), .CE(1'b1), .D(first_rising_ps_clk_ns), .Q(first_rising_ps_clk_r), .R(1'b0)); (* box_type = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("HIGH"), .CLKFBOUT_MULT_F(4.000000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(4.444444), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(8.000000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("TRUE"), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.000000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) \gen_mmcm.mmcm_i (.CLKFBIN(CLK), .CLKFBOUT(clk_pll_i), .CLKFBOUTB(\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ), .CLKFBSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ), .CLKIN1(pll_clk3), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ), .CLKOUT0(mmcm_ps_clk_bufg_in), .CLKOUT0B(\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ), .CLKOUT1(clk_div2_bufg_in), .CLKOUT1B(\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ), .CLKOUT2(\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ), .CLKOUT2B(\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ), .CLKOUT3(\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ), .CLKOUT3B(\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ), .CLKOUT4(\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ), .CLKOUT5(\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ), .CLKOUT6(\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]), .DRDY(\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ), .DWE(1'b0), .LOCKED(mmcm_locked), .PSCLK(CLK), .PSDONE(psdone), .PSEN(E), .PSINCDEC(1'b1), .PWRDWN(1'b0), .RST(RST0_0)); LUT1 #( .INIT(2'h1)) \gen_mmcm.mmcm_i_i_2 (.I0(pll_locked_i), .O(RST0_0)); (* box_type = "PRIMITIVE" *) BUFG \gen_mmcm.u_bufg_clk_div2 (.I(clk_div2_bufg_in), .O(\gen_mmcm.u_bufg_clk_div2_n_0 )); (* box_type = "PRIMITIVE" *) BUFG \gen_mmcm.u_bufg_mmcm_ps_clk (.I(mmcm_ps_clk_bufg_in), .O(mmcm_ps_clk)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___0_i_1 (.I0(rstdiv0_sync_r1_reg_rep__20_n_0), .O(\last_master_r_reg[2] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___35_i_1 (.I0(rstdiv0_sync_r1_reg_rep__21_n_0), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___56_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22_n_0), .O(\wait_cnt_reg[3] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \init_state_r[6]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__12_n_0), .O(\init_state_r_reg[6] )); LUT6 #( .INIT(64'h000000007FFF8000)) inv_poc_sample_r_i_1 (.I0(qcntr_r_reg__0[7]), .I1(qcntr_r_reg__0[6]), .I2(inv_poc_sample_r_i_2_n_0), .I3(E), .I4(inv_poc_sample_r), .I5(reset_reg), .O(inv_poc_sample_ns0_out)); LUT6 #( .INIT(64'hEAAAAAAAAAAAAAAA)) inv_poc_sample_r_i_2 (.I0(qcntr_r_reg__0[5]), .I1(qcntr_r_reg__0[4]), .I2(qcntr_r_reg__0[2]), .I3(qcntr_r_reg__0[0]), .I4(qcntr_r_reg__0[1]), .I5(qcntr_r_reg__0[3]), .O(inv_poc_sample_r_i_2_n_0)); FDRE #( .INIT(1'b0)) inv_poc_sample_r_reg (.C(CLK), .CE(1'b1), .D(inv_poc_sample_ns0_out), .Q(inv_poc_sample_r), .R(1'b0)); LUT2 #( .INIT(4'h7)) mmcm_hi0_r_i_1 (.I0(mmcm_hi0_r), .I1(first_rising_ps_clk_r), .O(mmcm_hi0_r_i_1_n_0)); FDRE #( .INIT(1'b0)) mmcm_hi0_r_reg (.C(CLK), .CE(1'b1), .D(mmcm_hi0_r_i_1_n_0), .Q(mmcm_hi0_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h7)) phaser_ref_i_i_1 (.I0(pll_locked_i), .I1(mmcm_locked), .O(RST0)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h8)) phy_control_i_i_1 (.I0(pll_locked_i), .I1(mmcm_locked), .O(pll_locked)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \pi_dqs_found_all_bank[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__13_n_0), .O(\first_fail_taps_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'h1)) \pi_rst_stg1_cal_r[1]_i_3 (.I0(\wrcal_reads_reg[0] ), .I1(fine_adjust_reg), .O(\pi_rst_stg1_cal_r_reg[1] )); (* box_type = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(9), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(2), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(337.500000), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(32), .CLKOUT2_DUTY_CYCLE(0.062500), .CLKOUT2_PHASE(9.843750), .CLKOUT3_DIVIDE(8), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(4), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(168.750000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("INTERNAL"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_i (.CLKFBIN(pll_clkfbout), .CLKFBOUT(pll_clkfbout), .CLKIN1(mmcm_clk), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(freq_refclk), .CLKOUT1(mem_refclk), .CLKOUT2(sync_pulse), .CLKOUT3(pll_clk3_out), .CLKOUT4(NLW_plle2_i_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_i_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(pll_locked_i), .PWRDWN(1'b0), .RST(AS)); LUT6 #( .INIT(64'hBBBBEBBB44441444)) poc_sample_pd_r_i_1 (.I0(reset_reg), .I1(inv_poc_sample_r), .I2(E), .I3(inv_poc_sample_r_i_2_n_0), .I4(poc_sample_pd_r_i_2_n_0), .I5(mmcm_hi0_r), .O(poc_sample_pd_ns)); LUT2 #( .INIT(4'h7)) poc_sample_pd_r_i_2 (.I0(qcntr_r_reg__0[6]), .I1(qcntr_r_reg__0[7]), .O(poc_sample_pd_r_i_2_n_0)); FDRE #( .INIT(1'b0)) poc_sample_pd_r_reg (.C(CLK), .CE(1'b1), .D(poc_sample_pd_ns), .Q(poc_sample_pd), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \prbs_state_r[4]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__8_n_0), .O(prbs_found_1st_edge_r_reg)); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h1)) pre_wait_r_i_2 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(pass_open_bank_r), .O(pre_wait_r_reg)); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'hE)) pre_wait_r_i_3__0 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(pass_open_bank_r_0), .O(rtp_timer_ns1)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) pwron_ce_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__11_n_0), .O(\complex_address_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT1 #( .INIT(2'h1)) \qcntr_r[0]_i_1 (.I0(qcntr_r_reg__0[0]), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h6)) \qcntr_r[1]_i_1 (.I0(qcntr_r_reg__0[0]), .I1(qcntr_r_reg__0[1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'h78)) \qcntr_r[2]_i_1 (.I0(qcntr_r_reg__0[1]), .I1(qcntr_r_reg__0[0]), .I2(qcntr_r_reg__0[2]), .O(\qcntr_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h7F80)) \qcntr_r[3]_i_1 (.I0(qcntr_r_reg__0[2]), .I1(qcntr_r_reg__0[0]), .I2(qcntr_r_reg__0[1]), .I3(qcntr_r_reg__0[3]), .O(\qcntr_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h7FFF8000)) \qcntr_r[4]_i_1 (.I0(qcntr_r_reg__0[3]), .I1(qcntr_r_reg__0[1]), .I2(qcntr_r_reg__0[0]), .I3(qcntr_r_reg__0[2]), .I4(qcntr_r_reg__0[4]), .O(\qcntr_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \qcntr_r[5]_i_1 (.I0(qcntr_r_reg__0[4]), .I1(qcntr_r_reg__0[2]), .I2(qcntr_r_reg__0[0]), .I3(qcntr_r_reg__0[1]), .I4(qcntr_r_reg__0[3]), .I5(qcntr_r_reg__0[5]), .O(\qcntr_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB4)) \qcntr_r[6]_i_1 (.I0(\qcntr_r[7]_i_3_n_0 ), .I1(qcntr_r_reg__0[5]), .I2(qcntr_r_reg__0[6]), .O(p_0_in__2[6])); LUT6 #( .INIT(64'hFFFFFFFFB0000000)) \qcntr_r[7]_i_1 (.I0(qcntr_r_reg__0[5]), .I1(\qcntr_r[7]_i_3_n_0 ), .I2(E), .I3(qcntr_r_reg__0[7]), .I4(qcntr_r_reg__0[6]), .I5(reset_reg), .O(qcntr_ns)); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'hBF40)) \qcntr_r[7]_i_2 (.I0(\qcntr_r[7]_i_3_n_0 ), .I1(qcntr_r_reg__0[5]), .I2(qcntr_r_reg__0[6]), .I3(qcntr_r_reg__0[7]), .O(p_0_in__2[7])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h7FFFFFFF)) \qcntr_r[7]_i_3 (.I0(qcntr_r_reg__0[3]), .I1(qcntr_r_reg__0[1]), .I2(qcntr_r_reg__0[0]), .I3(qcntr_r_reg__0[2]), .I4(qcntr_r_reg__0[4]), .O(\qcntr_r[7]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \qcntr_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in__2[0]), .Q(qcntr_r_reg__0[0]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in__2[1]), .Q(qcntr_r_reg__0[1]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[2] (.C(CLK), .CE(E), .D(\qcntr_r[2]_i_1_n_0 ), .Q(qcntr_r_reg__0[2]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[3] (.C(CLK), .CE(E), .D(\qcntr_r[3]_i_1_n_0 ), .Q(qcntr_r_reg__0[3]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[4] (.C(CLK), .CE(E), .D(\qcntr_r[4]_i_1_n_0 ), .Q(qcntr_r_reg__0[4]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[5] (.C(CLK), .CE(E), .D(\qcntr_r[5]_i_1_n_0 ), .Q(qcntr_r_reg__0[5]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[6] (.C(CLK), .CE(E), .D(p_0_in__2[6]), .Q(qcntr_r_reg__0[6]), .R(qcntr_ns)); FDRE #( .INIT(1'b0)) \qcntr_r_reg[7] (.C(CLK), .CE(E), .D(p_0_in__2[7]), .Q(qcntr_r_reg__0[7]), .R(qcntr_ns)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \rdlvl_dqs_tap_cnt_r[0][2][4]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__15_n_0), .O(\pi_rdval_cnt_reg[0] [0])); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) reset_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25_n_0), .O(reset_reg)); LUT2 #( .INIT(4'h1)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(insert_maint_r), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \rp_timer.rp_timer_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__0_n_0), .O(\read_fifo.head_r_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) rst_out_i_2 (.I0(rstdiv0_sync_r1_reg_rep__9_n_0), .O(rst_out_reg)); FDPE #( .INIT(1'b1)) rst_sync_r1_reg (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r1)); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[0] (.C(mmcm_ps_clk), .CE(1'b1), .D(1'b0), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[0])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[10] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[9]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[10])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[11] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[10]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[11])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[1] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[0]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[1])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[2] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[1]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[2])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[3] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[2]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[3])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[4] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[3]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[4])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[5] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[4]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[5])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[6] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[5]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[6])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[7] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[6]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[7])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[8] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[7]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[8])); FDPE #( .INIT(1'b1)) \rst_sync_r_reg[9] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[8]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[9])); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__0 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__0_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__1 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__1_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__10 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__10_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__11 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__11_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__12 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__12_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__13 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__13_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__14 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__14_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__15 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__15_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__16 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__16_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__17 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__17_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__18 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__18_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__19 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__19_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__2 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__2_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__20 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__20_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__21 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__21_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__22 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__22_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__23 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__23_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__24 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__24_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__25 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__25_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__3 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__3_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__4 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__4_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__5 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__5_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__6 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__6_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__7 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__7_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__8 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__8_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE #( .INIT(1'b1)) rstdiv0_sync_r1_reg_rep__9 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__9_n_0)); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[0] (.C(CLK), .CE(1'b1), .D(1'b0), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[0])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[10] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[9]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[10])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[11] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[10]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[11])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[1] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[0]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[1])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[2] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[1]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[2])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[3] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[2]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[3])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[4] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[3]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[4])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[5] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[4]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[5])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[6] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[5]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[6])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[7] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[6]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[7])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[8] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[7]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[8])); FDPE #( .INIT(1'b1)) \rstdiv0_sync_r_reg[9] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[8]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[9])); (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) rstdiv2_sync_r1_reg (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r1)); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[0] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(1'b0), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[0])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[10] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[9]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[10])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[11] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[10]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[11])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[1] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[0]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[1])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[2] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[1]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[2])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[3] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[2]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[3])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[4] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[3]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[4])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[5] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[4]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[5])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[6] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[5]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[6])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[7] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[6]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[7])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[8] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[7]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[8])); FDPE #( .INIT(1'b1)) \rstdiv2_sync_r_reg[9] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[8]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[9])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT2 #( .INIT(4'hB)) \samp_edge_cnt0_r[0]_i_1 (.I0(\wait_cnt_reg[3] ), .I1(samp_edge_cnt0_en_r), .O(\samp_edge_cnt0_r_reg[11] )); LUT2 #( .INIT(4'h1)) \simp_stg3_final_r[23]_i_2 (.I0(reset_reg), .I1(poc_backup_r_reg), .O(\simp_stg3_final_r_reg[17] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \smallest[0][5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__16_n_0), .O(\gen_final_tap[2].final_val_reg[2][1] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \stg2_tap_cnt[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__19_n_0), .O(\victim_sel_rotate.sel_reg[31] )); LUT2 #( .INIT(4'hE)) \stg3_r[5]_i_13 (.I0(reset_reg), .I1(\resume_wait_r_reg[10] ), .O(\stg3_r_reg[1] )); LUT2 #( .INIT(4'h1)) \stg3_tap_cnt[5]_i_3 (.I0(reset_reg), .I1(\lim_state_reg[0] ), .O(\stg3_tap_cnt_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \tempmon_state[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__3_n_0), .O(SS)); (* box_type = "PRIMITIVE" *) BUFG u_bufg_clkdiv0 (.I(clk_pll_i), .O(CLK)); (* box_type = "PRIMITIVE" *) BUFH u_bufh_pll_clk3 (.I(pll_clk3_out), .O(pll_clk3)); LUT1 #( .INIT(2'h2)) ui_clk_sync_rst_INST_0 (.I0(rstdiv0_sync_r1_reg_rep_n_0), .O(in0)); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT2 #( .INIT(4'hE)) \wait_cnt[3]_i_1 (.I0(\wait_cnt_reg[3] ), .I1(po_cnt_dec), .O(\wait_cnt_reg[3]_0 )); LUT2 #( .INIT(4'hE)) \wait_cnt_r[3]_i_1__1 (.I0(\wait_cnt_reg[3] ), .I1(pi_cnt_dec), .O(\wait_cnt_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT2 #( .INIT(4'hE)) \wr_victim_sel[2]_i_2 (.I0(\wrcal_reads_reg[0] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg[7] ), .O(p_81_in)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT2 #( .INIT(4'hE)) \wr_victim_sel_ocal[2]_i_2 (.I0(\wrcal_reads_reg[0] ), .I1(wr_victim_inc_reg), .O(\wr_victim_sel_ocal_reg[2] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \wrcal_reads[7]_i_4 (.I0(rstdiv0_sync_r1_reg_rep__23_n_0), .O(\wrcal_reads_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) wrcal_sanity_chk_done_i_1 (.I0(rstdiv0_sync_r1_reg_rep__5_n_0), .O(cal2_if_reset_reg)); LUT2 #( .INIT(4'h1)) \zero_r[9]_i_1 (.I0(\oneeighty_r_reg[0] ), .I1(sm_r), .O(\oneeighty_r_reg[0]_0 )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \zero_r[9]_i_4 (.I0(rstdiv0_sync_r1_reg_rep__24_n_0), .O(\oneeighty_r_reg[0] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_iodelay_ctrl" *) module ddr3_ifmig_7series_v4_0_iodelay_ctrl (AS, rst_sync_r1_reg, mmcm_clk, sys_rst); output [0:0]AS; output [0:0]rst_sync_r1_reg; input mmcm_clk; input sys_rst; wire [0:0]AS; wire \clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ; wire clk_ref_mmcm_400; wire [0:0]iodelay_ctrl_rdy; wire mmcm_clk; wire mmcm_clkfbout; wire rst_ref_0; wire rst_ref_1; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ; wire \rst_ref_sync_r_reg_n_0_[0][0] ; wire \rst_ref_sync_r_reg_n_0_[0][10] ; wire \rst_ref_sync_r_reg_n_0_[0][11] ; wire \rst_ref_sync_r_reg_n_0_[0][12] ; wire \rst_ref_sync_r_reg_n_0_[0][13] ; wire \rst_ref_sync_r_reg_n_0_[0][1] ; wire \rst_ref_sync_r_reg_n_0_[0][2] ; wire \rst_ref_sync_r_reg_n_0_[0][3] ; wire \rst_ref_sync_r_reg_n_0_[0][4] ; wire \rst_ref_sync_r_reg_n_0_[0][5] ; wire \rst_ref_sync_r_reg_n_0_[0][6] ; wire \rst_ref_sync_r_reg_n_0_[0][7] ; wire \rst_ref_sync_r_reg_n_0_[0][8] ; wire \rst_ref_sync_r_reg_n_0_[0][9] ; wire [0:0]rst_sync_r1_reg; wire sys_rst; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ; wire [15:0]\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED ; (* box_type = "PRIMITIVE" *) BUFG \clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400 (.I(clk_ref_mmcm_400), .O(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 )); (* box_type = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("HIGH"), .CLKFBOUT_MULT_F(6.000000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(4.000000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), .CLKOUT1_DIVIDE(3), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("INTERNAL"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.000000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) \clk_ref_mmcm_gen.mmcm_i (.CLKFBIN(mmcm_clkfbout), .CLKFBOUT(mmcm_clkfbout), .CLKFBOUTB(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ), .CLKFBSTOPPED(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ), .CLKIN1(mmcm_clk), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ), .CLKOUT0(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ), .CLKOUT0B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ), .CLKOUT1(clk_ref_mmcm_400), .CLKOUT1B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ), .CLKOUT2(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ), .CLKOUT2B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ), .CLKOUT3(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ), .CLKOUT3B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ), .CLKOUT4(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ), .CLKOUT5(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ), .CLKOUT6(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED [15:0]), .DRDY(\NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ), .DWE(1'b0), .LOCKED(\NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ), .PSCLK(1'b0), .PSDONE(\NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ), .PSEN(1'b0), .PSINCDEC(1'b0), .PWRDWN(1'b0), .RST(AS)); LUT1 #( .INIT(2'h1)) \clk_ref_mmcm_gen.mmcm_i_i_1 (.I0(sys_rst), .O(AS)); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) (* box_type = "PRIMITIVE" *) IDELAYCTRL #( .SIM_DEVICE("7SERIES")) \idelayctrl_gen_1.u_idelayctrl_300_400 (.RDY(rst_sync_r1_reg), .REFCLK(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .RST(rst_ref_1)); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][0] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(1'b0), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][10] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][11] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][12] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][13] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ), .PRE(AS), .Q(rst_ref_1)); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][1] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][2] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][3] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][4] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][5] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][6] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][7] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][8] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_gen_1.rst_ref_sync_r_reg[1][9] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][0] (.C(mmcm_clk), .CE(1'b1), .D(1'b0), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][0] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][10] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][9] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][10] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][11] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][10] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][11] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][12] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][11] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][12] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][13] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][12] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][13] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][14] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][13] ), .PRE(AS), .Q(rst_ref_0)); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][1] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][0] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][1] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][2] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][1] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][2] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][3] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][2] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][3] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][4] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][3] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][4] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][5] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][4] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][5] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][6] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][5] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][6] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][7] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][6] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][7] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][8] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][7] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][8] )); (* syn_maxfan = "10" *) FDPE #( .INIT(1'b1)) \rst_ref_sync_r_reg[0][9] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][8] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][9] )); (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG0" *) (* box_type = "PRIMITIVE" *) IDELAYCTRL #( .SIM_DEVICE("7SERIES")) u_idelayctrl_200 (.RDY(iodelay_ctrl_rdy), .REFCLK(mmcm_clk), .RST(rst_ref_0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_mc" *) module ddr3_ifmig_7series_v4_0_mc (insert_maint_r1_lcl_reg, app_ref_ack, app_zq_ack, accept_ns, E, idle_r_lcl_reg, bm_end_r1, bm_end_r1_reg, bm_end_r1_0, bm_end_r1_reg_0, mc_cmd, \read_data_indx.rd_data_indx_r_reg[0] , tempmon_sample_en, mc_ras_n, mc_cs_n, mc_odt, mc_cke, mc_wrdata_en, mc_cas_n, idle, app_sr_active, \read_fifo.tail_r_reg[1] , \rd_ptr_timing_reg[0] , mc_we_n, \rd_ptr_timing_reg[0]_0 , phy_dout, mc_address, \my_empty_reg[7] , bypass__0, Q, \cmd_pipe_plus.mc_bank_reg[2]_0 , \cmd_pipe_plus.mc_bank_reg[2]_1 , pointer_we, app_rd_data_end_ns, \write_buffer.wr_buf_out_data_reg[287] , mc_bank, \phy_ctl_wd_i1_reg[22] , \phy_ctl_wd_i1_reg[21] , \phy_ctl_wd_i1_reg[18] , \phy_ctl_wd_i1_reg[17] , \phy_ctl_wd_i1_reg[20] , \phy_ctl_wd_i1_reg[19] , \data_offset_1_i1_reg[5] , \data_offset_1_i1_reg[4] , \data_offset_1_i1_reg[1] , \data_offset_1_i1_reg[0] , \data_offset_1_i1_reg[3] , \data_offset_1_i1_reg[2] , CLK, p_67_out, p_28_out, SR, hi_priority, rstdiv0_sync_r1_reg_rep__0, phy_mc_ctl_full, of_ctl_full_v, maint_prescaler_r1, rstdiv0_sync_r1_reg_rep__20, init_calib_complete_reg_rep__6, app_ref_req, app_zq_req, \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] , rstdiv0_sync_r1_reg_rep__21, app_hi_pri_r2, app_sr_req, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , rstdiv0_sync_r1_reg_rep__22, \req_bank_r_lcl_reg[0] , init_calib_complete_reg_rep__7, \req_bank_r_lcl_reg[0]_0 , \rd_buf_indx.rd_buf_indx_r_reg[4] , \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , cmd, use_addr, bm_end_r1_reg_1, bm_end_r1_reg_2, rtp_timer_ns1, pass_open_bank_r_lcl_reg, \generate_maint_cmds.insert_maint_r_lcl_reg , \app_addr_r1_reg[27] , ram_init_done_r, \not_strict_mode.status_ram.rd_buf_we_r1_reg , \app_addr_r1_reg[12] , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[9] , \read_fifo.tail_r_reg[0] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 , \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ); output insert_maint_r1_lcl_reg; output app_ref_ack; output app_zq_ack; output accept_ns; output [0:0]E; output [0:0]idle_r_lcl_reg; output bm_end_r1; output bm_end_r1_reg; output bm_end_r1_0; output bm_end_r1_reg_0; output [1:0]mc_cmd; output [0:0]\read_data_indx.rd_data_indx_r_reg[0] ; output tempmon_sample_en; output [2:0]mc_ras_n; output [0:0]mc_cs_n; output [0:0]mc_odt; output [0:0]mc_cke; output mc_wrdata_en; output [2:0]mc_cas_n; output idle; output app_sr_active; output [0:0]\read_fifo.tail_r_reg[1] ; output [2:0]\rd_ptr_timing_reg[0] ; output [2:0]mc_we_n; output [3:0]\rd_ptr_timing_reg[0]_0 ; output [1:0]phy_dout; output [37:0]mc_address; output [1:0]\my_empty_reg[7] ; output bypass__0; output [7:0]Q; output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ; output pointer_we; output app_rd_data_end_ns; output [3:0]\write_buffer.wr_buf_out_data_reg[287] ; output [8:0]mc_bank; output \phy_ctl_wd_i1_reg[22] ; output \phy_ctl_wd_i1_reg[21] ; output \phy_ctl_wd_i1_reg[18] ; output \phy_ctl_wd_i1_reg[17] ; output \phy_ctl_wd_i1_reg[20] ; output \phy_ctl_wd_i1_reg[19] ; output \data_offset_1_i1_reg[5] ; output \data_offset_1_i1_reg[4] ; output \data_offset_1_i1_reg[1] ; output \data_offset_1_i1_reg[0] ; output \data_offset_1_i1_reg[3] ; output \data_offset_1_i1_reg[2] ; input CLK; input p_67_out; input p_28_out; input [0:0]SR; input hi_priority; input rstdiv0_sync_r1_reg_rep__0; input phy_mc_ctl_full; input [0:0]of_ctl_full_v; input maint_prescaler_r1; input rstdiv0_sync_r1_reg_rep__20; input init_calib_complete_reg_rep__6; input app_ref_req; input app_zq_req; input [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ; input [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ; input rstdiv0_sync_r1_reg_rep__21; input app_hi_pri_r2; input app_sr_req; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input rstdiv0_sync_r1_reg_rep__22; input \req_bank_r_lcl_reg[0] ; input init_calib_complete_reg_rep__7; input \req_bank_r_lcl_reg[0]_0 ; input [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input [1:0]cmd; input use_addr; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input rtp_timer_ns1; input pass_open_bank_r_lcl_reg; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input [14:0]\app_addr_r1_reg[27] ; input ram_init_done_r; input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; input [2:0]\app_addr_r1_reg[12] ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [6:0]\app_addr_r1_reg[9] ; input \read_fifo.tail_r_reg[0] ; input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ; input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ; input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ; input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ; input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ; input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ; wire CLK; wire [0:0]E; wire [7:0]Q; wire [0:0]SR; wire accept_ns; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire app_hi_pri_r2; wire app_rd_data_end_ns; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire \arb_mux0/arb_select0/cke_r ; wire \bank_cntrl[0].bank0/auto_pre_r ; wire \bank_cntrl[0].bank0/bank_queue0/order_q_r ; wire \bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ; wire \bank_cntrl[0].bank0/bank_queue0/q_entry_r ; wire \bank_cntrl[0].bank0/bank_queue0/set_order_q ; wire \bank_cntrl[0].bank0/bank_state0/override_demand_ns ; wire \bank_cntrl[0].bank0/bank_state0/req_bank_rdy_ns ; wire [1:0]\bank_cntrl[0].bank0/bank_state0/rtp_timer_r ; wire \bank_cntrl[0].bank0/pre_wait_r ; wire \bank_cntrl[0].bank0/row_hit_r ; wire \bank_cntrl[0].bank0/tail_r ; wire \bank_cntrl[0].bank0/wait_for_maint_r ; wire \bank_cntrl[1].bank0/auto_pre_r ; wire \bank_cntrl[1].bank0/bank_queue0/clear_req ; wire \bank_cntrl[1].bank0/bank_queue0/order_q_r ; wire \bank_cntrl[1].bank0/bank_queue0/q_entry_r ; wire \bank_cntrl[1].bank0/bank_queue0/set_order_q ; wire [2:0]\bank_cntrl[1].bank0/bank_state0/ras_timer_r ; wire \bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ; wire \bank_cntrl[1].bank0/q_has_priority ; wire \bank_cntrl[1].bank0/q_has_rd ; wire [2:2]\bank_cntrl[1].bank0/rb_hit_busies_r ; wire \bank_cntrl[1].bank0/row_hit_r ; wire \bank_cntrl[1].bank0/tail_r ; wire \bank_cntrl[1].bank0/wait_for_maint_r ; wire \bank_common0/periodic_rd_cntr_r ; wire [4:0]\bank_common0/rfc_zq_xsdll_timer_r ; wire bank_mach0_n_128; wire bank_mach0_n_129; wire bank_mach0_n_130; wire bank_mach0_n_134; wire bank_mach0_n_135; wire bank_mach0_n_136; wire bank_mach0_n_140; wire bank_mach0_n_141; wire bank_mach0_n_142; wire bank_mach0_n_144; wire bank_mach0_n_145; wire bank_mach0_n_146; wire bank_mach0_n_147; wire bank_mach0_n_148; wire bank_mach0_n_149; wire bank_mach0_n_150; wire bank_mach0_n_151; wire bank_mach0_n_152; wire bank_mach0_n_153; wire bank_mach0_n_154; wire bank_mach0_n_155; wire bank_mach0_n_156; wire bank_mach0_n_157; wire bank_mach0_n_158; wire bank_mach0_n_159; wire bank_mach0_n_160; wire bank_mach0_n_161; wire bank_mach0_n_162; wire bank_mach0_n_163; wire bank_mach0_n_164; wire bank_mach0_n_165; wire bank_mach0_n_166; wire bank_mach0_n_44; wire bank_mach0_n_52; wire bank_mach0_n_59; wire bank_mach0_n_65; wire bank_mach0_n_69; wire bank_mach0_n_71; wire bank_mach0_n_72; wire bank_mach0_n_73; wire bank_mach0_n_74; wire bank_mach0_n_76; wire bank_mach0_n_77; wire bank_mach0_n_78; wire bank_mach0_n_82; wire bank_mach0_n_83; wire bank_mach0_n_86; wire bank_mach0_n_87; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bypass__0; wire [1:0]cmd; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ; wire \cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ; wire [4:0]col_data_buf_addr; wire col_mach0_n_16; wire col_mach0_n_22; wire col_periodic_rd; wire col_rd_wr; wire col_rd_wr_r1; wire col_rd_wr_r2; wire [3:0]col_wr_data_buf_addr_r; wire \data_offset_1_i1_reg[0] ; wire \data_offset_1_i1_reg[1] ; wire \data_offset_1_i1_reg[2] ; wire \data_offset_1_i1_reg[3] ; wire \data_offset_1_i1_reg[4] ; wire \data_offset_1_i1_reg[5] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire [2:0]faw_cnt_r; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire [1:0]head_r; wire hi_priority; wire i___0_n_0; wire i___10_n_0; wire i___11_n_0; wire i___12_n_0; wire i___13_n_0; wire i___14_n_0; wire i___15_n_0; wire i___16_n_0; wire i___17_n_0; wire i___18_n_0; wire i___19_n_0; wire i___1_n_0; wire i___20_n_0; wire i___21_n_0; wire i___22_n_0; wire i___23_n_0; wire i___24_n_0; wire i___25_n_0; wire i___26_n_0; wire i___27_n_0; wire i___28_n_0; wire i___29_n_0; wire i___2_n_0; wire i___30_n_0; wire i___31_n_0; wire i___32_n_0; wire i___33_n_0; wire i___34_n_0; wire i___35_n_0; wire i___36_n_0; wire i___37_n_0; wire i___38_n_0; wire i___39_n_0; wire i___3_n_0; wire i___40_n_0; wire i___41_n_0; wire i___42_n_0; wire i___43_n_0; wire i___44_n_0; wire i___45_n_0; wire i___46_n_0; wire i___47_n_0; wire i___48_n_0; wire i___49_n_0; wire i___4_n_0; wire i___50_n_0; wire i___51_n_0; wire i___52_n_0; wire i___53_n_0; wire i___54_n_0; wire i___55_n_0; wire i___56_n_0; wire i___57_n_0; wire i___58_n_0; wire i___59_n_0; wire i___5_n_0; wire i___60_n_0; wire i___6_n_0; wire i___7_n_0; wire i___8_n_0; wire i___9_n_0; wire idle; wire [1:0]idle_r; wire [0:0]idle_r_lcl_reg; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__7; wire insert_maint_r1; wire insert_maint_r1_lcl_reg; wire maint_prescaler_r1; wire maint_ref_zq_wip; wire maint_req_r; wire maint_sre_r; wire maint_srx_r; wire maint_wip_r; wire maint_zq_r; wire [37:0]mc_address; wire [25:0]mc_address_ns; wire [8:0]mc_bank; wire [5:0]mc_bank_ns; wire [2:0]mc_cas_n; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cke; wire [1:1]mc_cke_ns; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_cs_n_ns; wire [3:3]mc_data_offset_2_ns; wire [0:0]mc_odt; wire [0:0]mc_odt_ns; wire [2:0]mc_ras_n; wire [2:0]mc_ras_n_ns; wire mc_ref_zq_wip_ns; wire [2:0]mc_we_n; wire [1:0]mc_we_n_ns; wire mc_wrdata_en; wire [1:0]\my_empty_reg[7] ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [0:0]of_ctl_full_v; wire ordered_r_lcl; wire p_13_out; wire p_28_out; wire p_52_out; wire p_67_out; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r; wire periodic_rd_r; wire \phy_ctl_wd_i1_reg[17] ; wire \phy_ctl_wd_i1_reg[18] ; wire \phy_ctl_wd_i1_reg[19] ; wire \phy_ctl_wd_i1_reg[20] ; wire \phy_ctl_wd_i1_reg[21] ; wire \phy_ctl_wd_i1_reg[22] ; wire [1:0]phy_dout; wire phy_mc_ctl_full; wire pointer_we; wire ram_init_done_r; wire \rank_cntrl[0].rank_cntrl0/act_delayed ; wire \rank_cntrl[0].rank_cntrl0/act_this_rank ; wire \rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ; wire \rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ; wire \rank_cntrl[0].rank_cntrl0/read_this_rank ; wire \rank_cntrl[0].rank_cntrl0/read_this_rank_r ; wire \rank_cntrl[0].rank_cntrl0/refresh_bank_r ; wire \rank_common0/app_ref_r ; wire \rank_common0/app_zq_r ; wire [2:0]\rank_common0/maint_grant_r ; wire [1:0]\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ; wire \rank_common0/maint_prescaler_tick_ns ; wire [2:0]\rank_common0/maintenance_request.maint_arb0/last_master_r ; wire \rank_common0/new_maint_rank_r ; wire \rank_common0/periodic_rd_grant_r ; wire \rank_common0/periodic_rd_r_cnt ; wire [1:0]\rank_common0/refresh_timer.refresh_timer_r_reg__0 ; wire \rank_common0/sre_request_r ; wire \rank_common0/upd_last_master_r ; wire \rank_common0/zq_request_r ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ; wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ; wire [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ; wire rank_mach0_n_27; wire rank_mach0_n_30; wire rank_mach0_n_34; wire rank_mach0_n_40; wire rank_mach0_n_42; wire rank_mach0_n_43; wire rank_mach0_n_44; wire rank_mach0_n_45; wire rank_mach0_n_46; wire rank_mach0_n_47; wire rank_mach0_n_48; wire rank_mach0_n_49; wire rank_mach0_n_5; wire rank_mach0_n_50; wire rank_mach0_n_51; wire rank_mach0_n_52; wire rank_mach0_n_53; wire rank_mach0_n_54; wire rank_mach0_n_55; wire rank_mach0_n_56; wire rank_mach0_n_57; wire rank_mach0_n_58; wire rank_mach0_n_59; wire rank_mach0_n_60; wire rank_mach0_n_61; wire rank_mach0_n_62; wire rank_mach0_n_63; wire rank_mach0_n_64; wire rank_mach0_n_68; wire [1:1]rb_hit_busy_r; wire [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; wire [2:0]\rd_ptr_timing_reg[0] ; wire [3:0]\rd_ptr_timing_reg[0]_0 ; wire [1:0]rd_wr_r; wire [0:0]\read_data_indx.rd_data_indx_r_reg[0] ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]\read_fifo.tail_r_reg[1] ; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[0]_0 ; wire [1:0]req_wr_r; wire [0:0]rfc_zq_xsdll_timer_ns; wire rnk_config_valid_r; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1; wire [1:1]rtw_cnt_r; wire [1:0]sending_col; wire [1:0]sending_row; wire sent_col; wire sent_col_r2; wire [2:1]tail_r; wire tempmon_sample_en; wire use_addr; wire was_wr; wire wr_data_en_ns; wire [1:0]wr_this_rank_r; wire [3:0]\write_buffer.wr_buf_out_data_reg[287] ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ; wire [3:3]\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ; ddr3_ifmig_7series_v4_0_bank_mach bank_mach0 (.CLK(CLK), .D(mc_we_n_ns), .DIC(col_periodic_rd), .E(bank_mach0_n_145), .Q(sending_col), .SR(SR), .accept_ns(accept_ns), .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ), .\act_this_rank_r_reg[0] (row_cmd_wr), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .app_hi_pri_r2(app_hi_pri_r2), .auto_pre_r(\bank_cntrl[0].bank0/auto_pre_r ), .auto_pre_r_5(\bank_cntrl[1].bank0/auto_pre_r ), .auto_pre_r_lcl_reg(bank_mach0_n_135), .auto_pre_r_lcl_reg_0(bank_mach0_n_136), .auto_pre_r_lcl_reg_1(i___36_n_0), .auto_pre_r_lcl_reg_2(i___13_n_0), .bm_end_r1(bm_end_r1), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg(bm_end_r1_reg), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .cke_r(\arb_mux0/arb_select0/cke_r ), .clear_req(\bank_cntrl[1].bank0/bank_queue0/clear_req ), .cmd(cmd), .\cmd_pipe_plus.mc_address_reg[0] (sending_row), .\cmd_pipe_plus.mc_address_reg[25] ({mc_address_ns[25:18],mc_address_ns[14:0]}), .\cmd_pipe_plus.mc_address_reg[30] (bank_mach0_n_163), .\cmd_pipe_plus.mc_address_reg[31] (bank_mach0_n_162), .\cmd_pipe_plus.mc_address_reg[32] (bank_mach0_n_161), .\cmd_pipe_plus.mc_address_reg[33] (bank_mach0_n_160), .\cmd_pipe_plus.mc_address_reg[34] (bank_mach0_n_159), .\cmd_pipe_plus.mc_address_reg[35] (bank_mach0_n_158), .\cmd_pipe_plus.mc_address_reg[36] (bank_mach0_n_157), .\cmd_pipe_plus.mc_address_reg[37] (bank_mach0_n_156), .\cmd_pipe_plus.mc_address_reg[38] (bank_mach0_n_155), .\cmd_pipe_plus.mc_address_reg[39] (bank_mach0_n_154), .\cmd_pipe_plus.mc_address_reg[40] (bank_mach0_n_146), .\cmd_pipe_plus.mc_address_reg[41] (bank_mach0_n_153), .\cmd_pipe_plus.mc_address_reg[42] (bank_mach0_n_152), .\cmd_pipe_plus.mc_address_reg[43] (bank_mach0_n_151), .\cmd_pipe_plus.mc_address_reg[44] (bank_mach0_n_150), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_1 ), .\cmd_pipe_plus.mc_bank_reg[5] (mc_bank_ns), .\cmd_pipe_plus.mc_bank_reg[6] (bank_mach0_n_149), .\cmd_pipe_plus.mc_bank_reg[7] (bank_mach0_n_148), .\cmd_pipe_plus.mc_bank_reg[8] (bank_mach0_n_147), .\cmd_pipe_plus.mc_cas_n_reg[2] (bank_mach0_n_165), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (bank_mach0_n_166), .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ), .\cmd_pipe_plus.mc_we_n_reg[2] (bank_mach0_n_164), .col_data_buf_addr(col_data_buf_addr), .col_rd_wr(col_rd_wr), .col_rd_wr_r1(col_rd_wr_r1), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (col_wr_data_buf_addr_r), .\entry_cnt_reg[2] (\entry_cnt_reg[2] ), .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2]_0 ), .\generate_maint_cmds.insert_maint_r_lcl_reg (rank_mach0_n_40), .\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\grant_r_reg[1] (i___41_n_0), .head_r(head_r), .head_r_lcl_reg(bank_mach0_n_71), .head_r_lcl_reg_0(bank_mach0_n_77), .head_r_lcl_reg_1(bank_mach0_n_78), .head_r_lcl_reg_2(bank_mach0_n_134), .head_r_lcl_reg_3(i___6_n_0), .head_r_lcl_reg_4(i___7_n_0), .hi_priority(hi_priority), .idle_r(idle_r), .idle_r_lcl_reg(E), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(i___4_n_0), .idle_r_lcl_reg_2(i___11_n_0), .\inhbt_act_faw.inhbt_act_faw_r_reg (bank_mach0_n_144), .inhbt_act_faw_r(inhbt_act_faw_r), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .insert_maint_r1(insert_maint_r1), .insert_maint_r1_lcl_reg(insert_maint_r1_lcl_reg), .\maint_controller.maint_wip_r_lcl_reg (i___45_n_0), .maint_req_r(maint_req_r), .maint_srx_r(maint_srx_r), .maint_wip_r(maint_wip_r), .maint_zq_r(maint_zq_r), .\maintenance_request.maint_zq_r_lcl_reg (rank_mach0_n_42), .mc_cas_n_ns(mc_cas_n_ns), .mc_cke_ns(mc_cke_ns), .mc_cs_n_ns(mc_cs_n_ns), .mc_data_offset_2_ns(mc_data_offset_2_ns), .mc_odt_ns(mc_odt_ns), .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .of_ctl_full_v(of_ctl_full_v), .order_q_r(\bank_cntrl[0].bank0/bank_queue0/order_q_r ), .order_q_r_6(\bank_cntrl[1].bank0/bank_queue0/order_q_r ), .\order_q_r_reg[0] (bank_mach0_n_52), .ordered_r_lcl(ordered_r_lcl), .ordered_r_lcl_reg(i___8_n_0), .ordered_r_lcl_reg_0(i___9_n_0), .ordered_r_lcl_reg_1(i___10_n_0), .ordered_r_lcl_reg_2(i___14_n_0), .override_demand_ns(\bank_cntrl[0].bank0/bank_state0/override_demand_ns ), .p_13_out(p_13_out), .p_28_out(p_28_out), .p_52_out(p_52_out), .p_67_out(p_67_out), .pass_open_bank_r_lcl_reg(bank_mach0_n_82), .pass_open_bank_r_lcl_reg_0(bank_mach0_n_141), .pass_open_bank_r_lcl_reg_1(i___37_n_0), .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg), .pass_open_bank_r_lcl_reg_3(i___0_n_0), .periodic_rd_ack_r(periodic_rd_ack_r), .periodic_rd_cntr_r(\bank_common0/periodic_rd_cntr_r ), .\periodic_rd_generation.periodic_rd_timer_r_reg[0] (bank_mach0_n_59), .periodic_rd_r(periodic_rd_r), .\periodic_read_request.periodic_rd_r_lcl_reg (i___40_n_0), .phy_mc_ctl_full(phy_mc_ctl_full), .pre_bm_end_r(\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ), .pre_wait_r(\bank_cntrl[0].bank0/pre_wait_r ), .q_entry_r(\bank_cntrl[0].bank0/bank_queue0/q_entry_r ), .q_entry_r_4(\bank_cntrl[1].bank0/bank_queue0/q_entry_r ), .\q_entry_r_reg[0] (bank_mach0_n_73), .\q_entry_r_reg[0]_0 (bank_mach0_n_74), .\q_entry_r_reg[0]_1 (bank_mach0_n_83), .\q_entry_r_reg[0]_2 (bank_mach0_n_87), .\q_entry_r_reg[0]_3 (i___5_n_0), .\q_entry_r_reg[0]_4 (i___12_n_0), .q_has_priority(\bank_cntrl[1].bank0/q_has_priority ), .q_has_priority_r_reg(rb_hit_busy_r), .q_has_priority_r_reg_0(bank_mach0_n_72), .q_has_priority_r_reg_1(i___35_n_0), .q_has_rd(\bank_cntrl[1].bank0/q_has_rd ), .q_has_rd_r_reg(bank_mach0_n_86), .q_has_rd_r_reg_0(i___34_n_0), .\ras_timer_r_reg[2] (i___44_n_0), .ras_timer_zero_r_reg(\bank_cntrl[1].bank0/bank_state0/ras_timer_r ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (i___33_n_0), .rb_hit_busies_r(\bank_cntrl[1].bank0/rb_hit_busies_r ), .\rcd_timer_gt_2.rcd_timer_r_reg[0] (bank_mach0_n_44), .rd_wr_r(rd_wr_r), .read_this_rank(\rank_cntrl[0].rank_cntrl0/read_this_rank ), .read_this_rank_r(\rank_cntrl[0].rank_cntrl0/read_this_rank_r ), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0]_0 ), .req_bank_rdy_ns(\bank_cntrl[0].bank0/bank_state0/req_bank_rdy_ns ), .req_bank_rdy_ns_1(\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ), .req_bank_rdy_r_reg(bank_mach0_n_128), .req_wr_r(req_wr_r), .req_wr_r_lcl_reg(i___38_n_0), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ({i___20_n_0,i___19_n_0,rfc_zq_xsdll_timer_ns}), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ({\bank_common0/rfc_zq_xsdll_timer_r [4],\bank_common0/rfc_zq_xsdll_timer_r [1:0]}), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 (bank_mach0_n_140), .\rnk_config_strobe_r_reg[0] (bank_mach0_n_129), .\rnk_config_strobe_r_reg[0]_0 (bank_mach0_n_130), .rnk_config_valid_r(rnk_config_valid_r), .rnk_config_valid_r_lcl_reg(i___43_n_0), .row_hit_r(\bank_cntrl[0].bank0/row_hit_r ), .row_hit_r_0(\bank_cntrl[1].bank0/row_hit_r ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rtp_timer_ns1(rtp_timer_ns1), .rtp_timer_r(\bank_cntrl[0].bank0/bank_state0/rtp_timer_r ), .\rtw_timer.rtw_cnt_r_reg[1] (bank_mach0_n_65), .\rtw_timer.rtw_cnt_r_reg[1]_0 (rtw_cnt_r), .sent_col(sent_col), .set_order_q(\bank_cntrl[1].bank0/bank_queue0/set_order_q ), .set_order_q_7(\bank_cntrl[0].bank0/bank_queue0/set_order_q ), .tail_r(\bank_cntrl[0].bank0/tail_r ), .tail_r_3(\bank_cntrl[1].bank0/tail_r ), .use_addr(use_addr), .wait_for_maint_r(\bank_cntrl[0].bank0/wait_for_maint_r ), .wait_for_maint_r_2(\bank_cntrl[1].bank0/wait_for_maint_r ), .wait_for_maint_r_lcl_reg(bank_mach0_n_69), .wait_for_maint_r_lcl_reg_0(bank_mach0_n_76), .was_wr(was_wr), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[1] (rank_mach0_n_68), .\wtr_timer.wtr_cnt_r_reg[2] (bank_mach0_n_142)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[0] (.C(CLK), .CE(1'b1), .D(mc_address_ns[0]), .Q(mc_address[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[10] (.C(CLK), .CE(1'b1), .D(mc_address_ns[10]), .Q(mc_address[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[11] (.C(CLK), .CE(1'b1), .D(mc_address_ns[11]), .Q(mc_address[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[12] (.C(CLK), .CE(1'b1), .D(mc_address_ns[12]), .Q(mc_address[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[13] (.C(CLK), .CE(1'b1), .D(mc_address_ns[13]), .Q(mc_address[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[14] (.C(CLK), .CE(1'b1), .D(mc_address_ns[14]), .Q(mc_address[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[18] (.C(CLK), .CE(1'b1), .D(mc_address_ns[18]), .Q(mc_address[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[19] (.C(CLK), .CE(1'b1), .D(mc_address_ns[19]), .Q(mc_address[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[1] (.C(CLK), .CE(1'b1), .D(mc_address_ns[1]), .Q(mc_address[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[20] (.C(CLK), .CE(1'b1), .D(mc_address_ns[20]), .Q(mc_address[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[21] (.C(CLK), .CE(1'b1), .D(mc_address_ns[21]), .Q(mc_address[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[22] (.C(CLK), .CE(1'b1), .D(mc_address_ns[22]), .Q(mc_address[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[23] (.C(CLK), .CE(1'b1), .D(mc_address_ns[23]), .Q(mc_address[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[24] (.C(CLK), .CE(1'b1), .D(mc_address_ns[24]), .Q(mc_address[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[25] (.C(CLK), .CE(1'b1), .D(mc_address_ns[25]), .Q(mc_address[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[2] (.C(CLK), .CE(1'b1), .D(mc_address_ns[2]), .Q(mc_address[2]), .R(1'b0)); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[30] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_163), .Q(mc_address[23]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[31] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_162), .Q(mc_address[24]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[32] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_161), .Q(mc_address[25]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[33] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_160), .Q(mc_address[26]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[34] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_159), .Q(mc_address[27]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[35] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_158), .Q(mc_address[28]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[36] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_157), .Q(mc_address[29]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[37] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_156), .Q(mc_address[30]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[38] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_155), .Q(mc_address[31]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[39] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_154), .Q(mc_address[32]), .S(mc_ras_n_ns[2])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[3] (.C(CLK), .CE(1'b1), .D(mc_address_ns[3]), .Q(mc_address[3]), .R(1'b0)); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[40] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_146), .Q(mc_address[33]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[41] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_153), .Q(mc_address[34]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[42] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_152), .Q(mc_address[35]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[43] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_151), .Q(mc_address[36]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_address_reg[44] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_150), .Q(mc_address[37]), .S(mc_ras_n_ns[2])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[4] (.C(CLK), .CE(1'b1), .D(mc_address_ns[4]), .Q(mc_address[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[5] (.C(CLK), .CE(1'b1), .D(mc_address_ns[5]), .Q(mc_address[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[6] (.C(CLK), .CE(1'b1), .D(mc_address_ns[6]), .Q(mc_address[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[7] (.C(CLK), .CE(1'b1), .D(mc_address_ns[7]), .Q(mc_address[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[8] (.C(CLK), .CE(1'b1), .D(mc_address_ns[8]), .Q(mc_address[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_address_reg[9] (.C(CLK), .CE(1'b1), .D(mc_address_ns[9]), .Q(mc_address[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_bank_reg[0] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[0]), .Q(mc_bank[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_bank_reg[1] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[1]), .Q(mc_bank[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_bank_reg[2] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[2]), .Q(mc_bank[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_bank_reg[3] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[3]), .Q(mc_bank[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_bank_reg[4] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[4]), .Q(mc_bank[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_bank_reg[5] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[5]), .Q(mc_bank[5]), .R(1'b0)); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_bank_reg[6] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_149), .Q(mc_bank[6]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_bank_reg[7] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_148), .Q(mc_bank[7]), .S(mc_ras_n_ns[2])); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_bank_reg[8] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_147), .Q(mc_bank[8]), .S(mc_ras_n_ns[2])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cas_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_cas_n_ns[0]), .Q(mc_cas_n[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cas_n_reg[1] (.C(CLK), .CE(1'b1), .D(mc_cas_n_ns[1]), .Q(mc_cas_n[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cas_n_reg[2] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_165), .Q(mc_cas_n[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cke_reg[3] (.C(CLK), .CE(1'b1), .D(mc_cke_ns), .Q(mc_cke), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cmd_reg[0] (.C(CLK), .CE(1'b1), .D(sent_col), .Q(mc_cmd[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cmd_reg[1] (.C(CLK), .CE(1'b1), .D(i___32_n_0), .Q(mc_cmd[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_cs_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_cs_n_ns), .Q(mc_cs_n), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_1_reg[0] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ), .Q(\data_offset_1_i1_reg[0] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_1_reg[1] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ), .Q(\data_offset_1_i1_reg[1] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_1_reg[2] (.C(CLK), .CE(1'b1), .D(i___28_n_0), .Q(\data_offset_1_i1_reg[2] ), .R(mc_cas_n_ns[1])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_1_reg[3] (.C(CLK), .CE(1'b1), .D(i___29_n_0), .Q(\data_offset_1_i1_reg[3] ), .R(mc_cas_n_ns[1])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_1_reg[4] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ), .Q(\data_offset_1_i1_reg[4] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_1_reg[5] (.C(CLK), .CE(1'b1), .D(i___54_n_0), .Q(\data_offset_1_i1_reg[5] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_2_reg[3] (.C(CLK), .CE(1'b1), .D(mc_data_offset_2_ns), .Q(\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_reg[0] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ), .Q(\phy_ctl_wd_i1_reg[17] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_reg[1] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ), .Q(\phy_ctl_wd_i1_reg[18] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_reg[2] (.C(CLK), .CE(1'b1), .D(i___30_n_0), .Q(\phy_ctl_wd_i1_reg[19] ), .R(mc_cas_n_ns[1])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_reg[3] (.C(CLK), .CE(1'b1), .D(i___31_n_0), .Q(\phy_ctl_wd_i1_reg[20] ), .R(mc_cas_n_ns[1])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_reg[4] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ), .Q(\phy_ctl_wd_i1_reg[21] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_data_offset_reg[5] (.C(CLK), .CE(1'b1), .D(i___53_n_0), .Q(\phy_ctl_wd_i1_reg[22] ), .R(bank_mach0_n_166)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_odt_reg[0] (.C(CLK), .CE(1'b1), .D(mc_odt_ns), .Q(mc_odt), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_ras_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_ras_n_ns[0]), .Q(mc_ras_n[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_ras_n_reg[1] (.C(CLK), .CE(1'b1), .D(i___27_n_0), .Q(mc_ras_n[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_ras_n_reg[2] (.C(CLK), .CE(1'b1), .D(mc_ras_n_ns[2]), .Q(mc_ras_n[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_we_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_we_n_ns[0]), .Q(mc_we_n[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_we_n_reg[1] (.C(CLK), .CE(1'b1), .D(mc_we_n_ns[1]), .Q(mc_we_n[1]), .R(1'b0)); FDSE #( .INIT(1'b1)) \cmd_pipe_plus.mc_we_n_reg[2] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_164), .Q(mc_we_n[2]), .S(mc_ras_n_ns[2])); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.mc_wrdata_en_reg (.C(CLK), .CE(1'b1), .D(i___58_n_0), .Q(mc_wrdata_en), .R(1'b0)); (* syn_maxfan = "30" *) FDRE #( .INIT(1'b0)) \cmd_pipe_plus.wr_data_addr_reg[0] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[0]), .Q(\write_buffer.wr_buf_out_data_reg[287] [0]), .R(1'b0)); (* syn_maxfan = "30" *) FDRE #( .INIT(1'b0)) \cmd_pipe_plus.wr_data_addr_reg[1] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[1]), .Q(\write_buffer.wr_buf_out_data_reg[287] [1]), .R(1'b0)); (* syn_maxfan = "30" *) FDRE #( .INIT(1'b0)) \cmd_pipe_plus.wr_data_addr_reg[2] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[2]), .Q(\write_buffer.wr_buf_out_data_reg[287] [2]), .R(1'b0)); (* syn_maxfan = "30" *) FDRE #( .INIT(1'b0)) \cmd_pipe_plus.wr_data_addr_reg[3] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[3]), .Q(\write_buffer.wr_buf_out_data_reg[287] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cmd_pipe_plus.wr_data_en_reg (.C(CLK), .CE(1'b1), .D(wr_data_en_ns), .Q(\read_data_indx.rd_data_indx_r_reg[0] ), .R(1'b0)); ddr3_ifmig_7series_v4_0_col_mach col_mach0 (.ADDRA({i___56_n_0,i___55_n_0,i___57_n_0}), .CLK(CLK), .D(col_wr_data_buf_addr_r), .DIC(col_periodic_rd), .E(i___32_n_0), .Q(Q), .SR(SR), .app_rd_data_end_ns(app_rd_data_end_ns), .bypass__0(bypass__0), .col_data_buf_addr(col_data_buf_addr), .col_rd_wr(col_rd_wr), .col_rd_wr_r1(col_rd_wr_r1), .col_rd_wr_r2(col_rd_wr_r2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .maint_ref_zq_wip(maint_ref_zq_wip), .mc_cmd(mc_cmd[0]), .mc_read_idle_r_reg(col_mach0_n_16), .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .\rd_buf_indx.rd_buf_indx_r_reg[4] (\rd_buf_indx.rd_buf_indx_r_reg[4] ), .\read_fifo.fifo_out_data_r_reg[7]_0 (col_mach0_n_22), .\read_fifo.tail_r_reg[0]_0 (\read_fifo.tail_r_reg[0] ), .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1] ), .\read_fifo.tail_r_reg[2]_0 (tail_r), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .sent_col_r2(sent_col_r2), .wr_data_en_ns(wr_data_en_ns)); LUT5 #( .INIT(32'h11000010)) i___0 (.I0(bm_end_r1_reg), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(sending_col[0]), .I3(\bank_cntrl[0].bank0/bank_state0/rtp_timer_r [1]), .I4(\bank_cntrl[0].bank0/bank_state0/rtp_timer_r [0]), .O(i___0_n_0)); LUT5 #( .INIT(32'hFFFF0008)) i___1 (.I0(\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ), .I1(init_calib_complete_reg_rep__6), .I2(rank_mach0_n_5), .I3(periodic_rd_r), .I4(\rank_common0/periodic_rd_grant_r ), .O(i___1_n_0)); LUT6 #( .INIT(64'h1BB100000AA0A00A)) i___10 (.I0(\bank_cntrl[0].bank0/bank_queue0/set_order_q ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(ordered_r_lcl), .I3(bank_mach0_n_52), .I4(bank_mach0_n_128), .I5(\bank_cntrl[0].bank0/bank_queue0/order_q_r ), .O(i___10_n_0)); LUT6 #( .INIT(64'hCFFFCCEECCEECCEE)) i___11 (.I0(p_13_out), .I1(bank_mach0_n_69), .I2(idle_r[1]), .I3(p_52_out), .I4(bank_mach0_n_82), .I5(\bank_cntrl[1].bank0/tail_r ), .O(i___11_n_0)); LUT6 #( .INIT(64'hF404FFFFF7070000)) i___12 (.I0(bank_mach0_n_73), .I1(bank_mach0_n_69), .I2(p_13_out), .I3(bank_mach0_n_87), .I4(bank_mach0_n_74), .I5(\bank_cntrl[1].bank0/bank_queue0/q_entry_r ), .O(i___12_n_0)); LUT6 #( .INIT(64'h00000000AAAEEEEE)) i___13 (.I0(\bank_cntrl[1].bank0/auto_pre_r ), .I1(bank_mach0_n_135), .I2(\bank_cntrl[1].bank0/wait_for_maint_r ), .I3(i___45_n_0), .I4(\bank_cntrl[1].bank0/row_hit_r ), .I5(\bank_cntrl[1].bank0/bank_queue0/clear_req ), .O(i___13_n_0)); LUT6 #( .INIT(64'h1BB100000AA0A00A)) i___14 (.I0(\bank_cntrl[1].bank0/bank_queue0/set_order_q ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(ordered_r_lcl), .I3(bank_mach0_n_52), .I4(bank_mach0_n_128), .I5(\bank_cntrl[1].bank0/bank_queue0/order_q_r ), .O(i___14_n_0)); LUT2 #( .INIT(4'hB)) i___15 (.I0(\rank_common0/maint_prescaler_tick_ns ), .I1(init_calib_complete_reg_rep__6), .O(i___15_n_0)); (* SOFT_HLUTNM = "soft_lutpair1081" *) LUT5 #( .INIT(32'h88820008)) i___16 (.I0(init_calib_complete_reg_rep__6), .I1(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .I2(app_ref_req), .I3(rank_mach0_n_27), .I4(rank_mach0_n_43), .O(i___16_n_0)); (* SOFT_HLUTNM = "soft_lutpair1081" *) LUT2 #( .INIT(4'hB)) i___17 (.I0(rank_mach0_n_27), .I1(init_calib_complete_reg_rep__6), .O(i___17_n_0)); LUT5 #( .INIT(32'hFF2AFFFF)) i___18 (.I0(\rank_common0/zq_request_r ), .I1(insert_maint_r1), .I2(maint_zq_r), .I3(app_zq_req), .I4(rank_mach0_n_30), .O(i___18_n_0)); LUT5 #( .INIT(32'h00415541)) i___19 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\bank_common0/rfc_zq_xsdll_timer_r [1]), .I2(\bank_common0/rfc_zq_xsdll_timer_r [0]), .I3(insert_maint_r1_lcl_reg), .I4(rank_mach0_n_34), .O(i___19_n_0)); LUT4 #( .INIT(16'h2F20)) i___2 (.I0(maint_sre_r), .I1(maint_srx_r), .I2(insert_maint_r1), .I3(app_sr_active), .O(i___2_n_0)); LUT5 #( .INIT(32'h00415541)) i___20 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(bank_mach0_n_140), .I2(\bank_common0/rfc_zq_xsdll_timer_r [4]), .I3(insert_maint_r1_lcl_reg), .I4(rank_mach0_n_34), .O(i___20_n_0)); LUT5 #( .INIT(32'h45444044)) i___21 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [0]), .I2(\rank_common0/new_maint_rank_r ), .I3(\rank_common0/upd_last_master_r ), .I4(\rank_common0/maint_grant_r [0]), .O(i___21_n_0)); LUT5 #( .INIT(32'h45444044)) i___22 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [1]), .I2(\rank_common0/new_maint_rank_r ), .I3(\rank_common0/upd_last_master_r ), .I4(\rank_common0/maint_grant_r [1]), .O(i___22_n_0)); LUT5 #( .INIT(32'h10111511)) i___23 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [2]), .I2(\rank_common0/new_maint_rank_r ), .I3(\rank_common0/upd_last_master_r ), .I4(\rank_common0/maint_grant_r [2]), .O(i___23_n_0)); LUT5 #( .INIT(32'h54005500)) i___24 (.I0(maint_wip_r), .I1(\rank_common0/zq_request_r ), .I2(\rank_common0/sre_request_r ), .I3(init_calib_complete_reg_rep__6), .I4(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .O(i___24_n_0)); LUT6 #( .INIT(64'h00001555FFFFFFFF)) i___25 (.I0(bank_mach0_n_59), .I1(periodic_rd_ack_r), .I2(\rank_common0/periodic_rd_grant_r ), .I3(\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ), .I4(rank_mach0_n_64), .I5(init_calib_complete_reg_rep__6), .O(i___25_n_0)); (* SOFT_HLUTNM = "soft_lutpair1085" *) LUT3 #( .INIT(8'h78)) i___26 (.I0(\rank_common0/periodic_rd_grant_r ), .I1(periodic_rd_ack_r), .I2(\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ), .O(i___26_n_0)); LUT3 #( .INIT(8'hEF)) i___27 (.I0(sending_col[1]), .I1(sending_col[0]), .I2(sent_col), .O(i___27_n_0)); (* SOFT_HLUTNM = "soft_lutpair1082" *) LUT4 #( .INIT(16'h78FF)) i___28 (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]), .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]), .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]), .I3(col_rd_wr), .O(i___28_n_0)); (* SOFT_HLUTNM = "soft_lutpair1082" *) LUT5 #( .INIT(32'h7F80FFFF)) i___29 (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]), .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]), .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]), .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]), .I4(col_rd_wr), .O(i___29_n_0)); LUT6 #( .INIT(64'hFFFFC400C400C400)) i___3 (.I0(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .I1(init_calib_complete_reg_rep__6), .I2(\rank_common0/zq_request_r ), .I3(insert_maint_r1), .I4(maint_wip_r), .I5(maint_ref_zq_wip), .O(i___3_n_0)); (* SOFT_HLUTNM = "soft_lutpair1083" *) LUT4 #( .INIT(16'h78FF)) i___30 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]), .I3(col_rd_wr), .O(i___30_n_0)); (* SOFT_HLUTNM = "soft_lutpair1083" *) LUT5 #( .INIT(32'h7F80FFFF)) i___31 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]), .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]), .I4(col_rd_wr), .O(i___31_n_0)); LUT6 #( .INIT(64'hFECE320200000000)) i___32 (.I0(col_rd_wr_r1), .I1(sending_col[1]), .I2(sending_col[0]), .I3(rd_wr_r[0]), .I4(rd_wr_r[1]), .I5(sent_col), .O(i___32_n_0)); LUT6 #( .INIT(64'h00000000000022F0)) i___33 (.I0(\req_bank_r_lcl_reg[0] ), .I1(E), .I2(\bank_cntrl[1].bank0/rb_hit_busies_r ), .I3(idle_r_lcl_reg), .I4(p_52_out), .I5(rstdiv0_sync_r1_reg_rep__20), .O(i___33_n_0)); LUT6 #( .INIT(64'h4454445444545555)) i___34 (.I0(\bank_cntrl[1].bank0/bank_queue0/clear_req ), .I1(\bank_cntrl[1].bank0/q_has_rd ), .I2(maint_req_r), .I3(idle_r[1]), .I4(was_wr), .I5(bank_mach0_n_82), .O(i___34_n_0)); LUT6 #( .INIT(64'h1010111010101010)) i___35 (.I0(p_13_out), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\bank_cntrl[1].bank0/q_has_priority ), .I3(rb_hit_busy_r), .I4(bank_mach0_n_72), .I5(app_hi_pri_r2), .O(i___35_n_0)); LUT6 #( .INIT(64'h888888A8A8A8A8A8)) i___36 (.I0(i___38_n_0), .I1(\bank_cntrl[0].bank0/auto_pre_r ), .I2(bank_mach0_n_136), .I3(\bank_cntrl[0].bank0/wait_for_maint_r ), .I4(i___45_n_0), .I5(\bank_cntrl[0].bank0/row_hit_r ), .O(i___36_n_0)); LUT6 #( .INIT(64'h88888A8888888888)) i___37 (.I0(i___38_n_0), .I1(bm_end_r1_reg), .I2(bank_mach0_n_86), .I3(\bank_cntrl[0].bank0/tail_r ), .I4(\bank_cntrl[0].bank0/pre_wait_r ), .I5(bank_mach0_n_141), .O(i___37_n_0)); LUT6 #( .INIT(64'h0000000040555555)) i___38 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(req_wr_r[0]), .I2(rd_wr_r[0]), .I3(bm_end_r1_reg), .I4(sending_col[0]), .I5(\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ), .O(i___38_n_0)); (* SOFT_HLUTNM = "soft_lutpair1084" *) LUT3 #( .INIT(8'h78)) i___39 (.I0(periodic_rd_r), .I1(periodic_rd_ack_r), .I2(\rank_common0/periodic_rd_r_cnt ), .O(i___39_n_0)); LUT6 #( .INIT(64'hCFFFCCEECCEECCEE)) i___4 (.I0(p_52_out), .I1(bank_mach0_n_76), .I2(idle_r[0]), .I3(p_13_out), .I4(bank_mach0_n_86), .I5(\bank_cntrl[0].bank0/tail_r ), .O(i___4_n_0)); (* SOFT_HLUTNM = "soft_lutpair1085" *) LUT3 #( .INIT(8'h78)) i___40 (.I0(periodic_rd_r), .I1(periodic_rd_ack_r), .I2(\bank_common0/periodic_rd_cntr_r ), .O(i___40_n_0)); LUT6 #( .INIT(64'h4040404040454040)) i___41 (.I0(sending_row[1]), .I1(row_cmd_wr), .I2(sending_row[0]), .I3(maint_zq_r), .I4(insert_maint_r1), .I5(rstdiv0_sync_r1_reg_rep__21), .O(i___41_n_0)); LUT5 #( .INIT(32'h00F0F8F8)) i___42 (.I0(app_sr_req), .I1(init_calib_complete_reg_rep__6), .I2(\rank_common0/sre_request_r ), .I3(insert_maint_r1), .I4(maint_sre_r), .O(i___42_n_0)); LUT6 #( .INIT(64'hFF00FF4FFF00FF44)) i___43 (.I0(bank_mach0_n_129), .I1(\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ), .I2(bank_mach0_n_130), .I3(rnk_config_valid_r), .I4(\bank_cntrl[0].bank0/bank_state0/override_demand_ns ), .I5(\bank_cntrl[0].bank0/bank_state0/req_bank_rdy_ns ), .O(i___43_n_0)); LUT6 #( .INIT(64'h01000100FFFF0100)) i___44 (.I0(\bank_cntrl[1].bank0/bank_state0/ras_timer_r [2]), .I1(\bank_cntrl[1].bank0/bank_state0/ras_timer_r [1]), .I2(\bank_cntrl[1].bank0/bank_state0/ras_timer_r [0]), .I3(bank_mach0_n_44), .I4(sending_col[1]), .I5(rd_wr_r[1]), .O(i___44_n_0)); LUT3 #( .INIT(8'h45)) i___45 (.I0(maint_wip_r), .I1(\bank_common0/periodic_rd_cntr_r ), .I2(maint_req_r), .O(i___45_n_0)); LUT5 #( .INIT(32'h00151515)) i___46 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(sending_col[1]), .I2(wr_this_rank_r[1]), .I3(sending_col[0]), .I4(wr_this_rank_r[0]), .O(i___46_n_0)); (* SOFT_HLUTNM = "soft_lutpair1084" *) LUT4 #( .INIT(16'hFF4C)) i___47 (.I0(periodic_rd_ack_r), .I1(periodic_rd_r), .I2(\rank_common0/periodic_rd_r_cnt ), .I3(rank_mach0_n_5), .O(i___47_n_0)); LUT3 #( .INIT(8'hBA)) i___48 (.I0(app_ref_req), .I1(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .I2(\rank_common0/app_ref_r ), .O(i___48_n_0)); LUT3 #( .INIT(8'hEA)) i___49 (.I0(app_zq_req), .I1(\rank_common0/app_zq_r ), .I2(\rank_common0/zq_request_r ), .O(i___49_n_0)); LUT6 #( .INIT(64'hB888FFFFB8BB0000)) i___5 (.I0(bank_mach0_n_134), .I1(p_52_out), .I2(bank_mach0_n_83), .I3(bank_mach0_n_76), .I4(bank_mach0_n_78), .I5(\bank_cntrl[0].bank0/bank_queue0/q_entry_r ), .O(i___5_n_0)); (* SOFT_HLUTNM = "soft_lutpair1080" *) LUT4 #( .INIT(16'h1441)) i___50 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(\rank_cntrl[0].rank_cntrl0/act_delayed ), .I2(bank_mach0_n_144), .I3(faw_cnt_r[0]), .O(i___50_n_0)); (* SOFT_HLUTNM = "soft_lutpair1080" *) LUT5 #( .INIT(32'h44411444)) i___51 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(faw_cnt_r[1]), .I2(bank_mach0_n_144), .I3(\rank_cntrl[0].rank_cntrl0/act_delayed ), .I4(faw_cnt_r[0]), .O(i___51_n_0)); LUT6 #( .INIT(64'h5551455500041000)) i___52 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(faw_cnt_r[1]), .I2(\rank_cntrl[0].rank_cntrl0/act_delayed ), .I3(bank_mach0_n_144), .I4(faw_cnt_r[0]), .I5(faw_cnt_r[2]), .O(i___52_n_0)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) i___53 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [5]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]), .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]), .I5(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [4]), .O(i___53_n_0)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) i___54 (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [5]), .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]), .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]), .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]), .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]), .I5(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [4]), .O(i___54_n_0)); LUT5 #( .INIT(32'h15554000)) i___55 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(\read_fifo.tail_r_reg[1] ), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(tail_r[1]), .I4(tail_r[2]), .O(i___55_n_0)); LUT2 #( .INIT(4'h1)) i___56 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(col_mach0_n_22), .O(i___56_n_0)); LUT4 #( .INIT(16'h1540)) i___57 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\read_fifo.tail_r_reg[1] ), .I3(tail_r[1]), .O(i___57_n_0)); LUT2 #( .INIT(4'h2)) i___58 (.I0(sent_col_r2), .I1(col_rd_wr_r2), .O(i___58_n_0)); LUT2 #( .INIT(4'h9)) i___59 (.I0(\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [0]), .I1(\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [1]), .O(i___59_n_0)); LUT5 #( .INIT(32'h5CFF5C00)) i___6 (.I0(bank_mach0_n_134), .I1(bank_mach0_n_77), .I2(p_52_out), .I3(bank_mach0_n_78), .I4(head_r[0]), .O(i___6_n_0)); LUT2 #( .INIT(4'h9)) i___60 (.I0(\rank_common0/refresh_timer.refresh_timer_r_reg__0 [0]), .I1(\rank_common0/refresh_timer.refresh_timer_r_reg__0 [1]), .O(i___60_n_0)); LUT6 #( .INIT(64'h1F10FFFF1F100000)) i___7 (.I0(p_52_out), .I1(bank_mach0_n_134), .I2(p_13_out), .I3(bank_mach0_n_71), .I4(bank_mach0_n_74), .I5(head_r[1]), .O(i___7_n_0)); LUT6 #( .INIT(64'h00000000EAEA0AEA)) i___8 (.I0(bank_mach0_n_52), .I1(bank_mach0_n_69), .I2(req_wr_r[1]), .I3(sending_col[1]), .I4(rd_wr_r[1]), .I5(rstdiv0_sync_r1_reg_rep__20), .O(i___8_n_0)); LUT6 #( .INIT(64'h00000000EAEA0AEA)) i___9 (.I0(ordered_r_lcl), .I1(bank_mach0_n_76), .I2(req_wr_r[0]), .I3(sending_col[0]), .I4(rd_wr_r[0]), .I5(rstdiv0_sync_r1_reg_rep__20), .O(i___9_n_0)); FDRE #( .INIT(1'b0)) mc_read_idle_r_reg (.C(CLK), .CE(1'b1), .D(col_mach0_n_16), .Q(idle), .R(maint_prescaler_r1)); FDRE #( .INIT(1'b0)) mc_ref_zq_wip_r_reg (.C(CLK), .CE(1'b1), .D(mc_ref_zq_wip_ns), .Q(tempmon_sample_en), .R(1'b0)); LUT2 #( .INIT(4'hB)) mem_reg_0_15_0_5_i_2__0 (.I0(mc_cs_n), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0] [0])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_0_5_i_3__0 (.I0(mc_ras_n[2]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [3])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_12_17_i_2__4 (.I0(mc_cas_n[0]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [0])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_18_23_i_1__4 (.I0(mc_cas_n[2]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [1])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_24_29_i_2__4 (.I0(mc_ras_n[0]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [2])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_30_35_i_1__5 (.I0(mc_address[14]), .I1(init_calib_complete_reg_rep__7), .O(phy_dout[0])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_30_35_i_2__5 (.I0(mc_address[37]), .I1(init_calib_complete_reg_rep__7), .O(phy_dout[1])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_6_11_i_2__4 (.I0(mc_we_n[0]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0] [1])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_6_11_i_3__4 (.I0(mc_we_n[2]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0] [2])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__0 (.I0(mc_address[13]), .I1(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7] [0])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__0 (.I0(mc_address[36]), .I1(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7] [1])); LUT2 #( .INIT(4'hB)) \pointer_ram.rams[0].RAM32M0_i_1 (.I0(\read_data_indx.rd_data_indx_r_reg[0] ), .I1(ram_init_done_r), .O(pointer_we)); ddr3_ifmig_7series_v4_0_rank_mach rank_mach0 (.CLK(CLK), .D({i___22_n_0,i___21_n_0}), .E(bank_mach0_n_145), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }), .Q(\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ), .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}), .SR(SR), .SS(i___15_n_0), .act_delayed(\rank_cntrl[0].rank_cntrl0/act_delayed ), .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ), .\act_this_rank_r_reg[0] (bank_mach0_n_144), .app_ref_ack(app_ref_ack), .app_ref_r(\rank_common0/app_ref_r ), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_r(\rank_common0/app_zq_r ), .app_zq_r_reg(i___49_n_0), .cke_r(\arb_mux0/arb_select0/cke_r ), .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r1_lcl_reg), .\grant_r_reg[0] (bank_mach0_n_65), .\grant_r_reg[1] (i___46_n_0), .granted_col_r_reg(rank_mach0_n_68), .\inhbt_act_faw.faw_cnt_r_reg[1] ({i___52_n_0,i___51_n_0,i___50_n_0}), .\inhbt_act_faw.inhbt_act_faw_r_reg (faw_cnt_r), .inhbt_act_faw_r(inhbt_act_faw_r), .init_calib_complete_reg_rep__6(i___42_n_0), .init_calib_complete_reg_rep__6_0(i___16_n_0), .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_2(i___17_n_0), .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7), .insert_maint_r1(insert_maint_r1), .\last_master_r_reg[2] (\rank_common0/maintenance_request.maint_arb0/last_master_r ), .\last_master_r_reg[2]_0 (i___23_n_0), .\maint_controller.maint_wip_r_lcl_reg (i___24_n_0), .\maint_prescaler.maint_prescaler_r_reg[0] (i___59_n_0), .maint_prescaler_r1(maint_prescaler_r1), .maint_prescaler_tick_ns(\rank_common0/maint_prescaler_tick_ns ), .maint_ref_zq_wip(maint_ref_zq_wip), .maint_req_r(maint_req_r), .maint_sre_r(maint_sre_r), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .\maintenance_request.maint_sre_r_lcl_reg (\rank_common0/maint_grant_r ), .\maintenance_request.maint_sre_r_lcl_reg_0 (i___2_n_0), .mc_cke_ns(mc_cke_ns), .new_maint_rank_r(\rank_common0/new_maint_rank_r ), .periodic_rd_ack_r_lcl_reg(i___25_n_0), .periodic_rd_ack_r_lcl_reg_0(i___47_n_0), .periodic_rd_cntr1_r(\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ), .\periodic_rd_generation.periodic_rd_request_r_reg (rank_mach0_n_64), .\periodic_rd_generation.periodic_rd_request_r_reg_0 (i___1_n_0), .\periodic_rd_generation.read_this_rank_r_reg (bank_mach0_n_59), .periodic_rd_grant_r(\rank_common0/periodic_rd_grant_r ), .periodic_rd_r(periodic_rd_r), .periodic_rd_r_cnt(\rank_common0/periodic_rd_r_cnt ), .periodic_rd_request_r(\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ), .\periodic_read_request.periodic_rd_grant_r_reg[0] (i___26_n_0), .\periodic_read_request.periodic_rd_r_lcl_reg (i___39_n_0), .\periodic_read_request.upd_last_master_r_reg (rank_mach0_n_5), .read_this_rank(\rank_cntrl[0].rank_cntrl0/read_this_rank ), .read_this_rank_r(\rank_cntrl[0].rank_cntrl0/read_this_rank_r ), .refresh_bank_r(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .\refresh_generation.refresh_bank_r_reg[0] (rank_mach0_n_43), .\refresh_generation.refresh_bank_r_reg[0]_0 (i___48_n_0), .\refresh_generation.refresh_bank_r_reg[0]_1 (i___3_n_0), .\refresh_timer.refresh_timer_r_reg[0] (i___60_n_0), .\refresh_timer.refresh_timer_r_reg[4] (\rank_common0/refresh_timer.refresh_timer_r_reg__0 ), .\refresh_timer.refresh_timer_r_reg[5] (rank_mach0_n_27), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (rfc_zq_xsdll_timer_ns), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\bank_common0/rfc_zq_xsdll_timer_r [0]), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (rank_mach0_n_34), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (rank_mach0_n_42), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (rank_mach0_n_40), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\rtw_timer.rtw_cnt_r_reg[1] (rtw_cnt_r), .sre_request_r(\rank_common0/sre_request_r ), .upd_last_master_r(\rank_common0/upd_last_master_r ), .\wr_this_rank_r_reg[0] (bank_mach0_n_142), .\zq_cntrl.zq_request_logic.zq_request_r_reg (i___18_n_0), .\zq_cntrl.zq_timer.zq_timer_r_reg[0] (rank_mach0_n_30), .\zq_cntrl.zq_timer.zq_timer_r_reg[11] ({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}), .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }), .\zq_cntrl.zq_timer.zq_timer_r_reg[15] ({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}), .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }), .\zq_cntrl.zq_timer.zq_timer_r_reg[19] ({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63}), .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }), .\zq_cntrl.zq_timer.zq_timer_r_reg[7] ({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}), .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }), .zq_request_r(\rank_common0/zq_request_r )); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 (.CI(1'b0), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }), .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }), .S({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ), .CO({\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }), .S({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }), .S({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }), .S({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55})); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_mem_intfc" *) module ddr3_ifmig_7series_v4_0_mem_intfc (insert_maint_r1_lcl_reg, app_ref_ack, app_zq_ack, accept_ns, idle_ns, bm_end_r1, bm_end_r1_reg, bm_end_r1_0, bm_end_r1_reg_0, E, app_sr_active, ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , phy_dout, \samps_r_reg[9] , init_calib_complete_r_reg, \calib_seq_reg[0] , \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_en_stg2_f_timing_reg, dqs_po_en_stg2_f_reg, \rd_ptr_timing_reg[0] , \rd_ptr_timing_reg[0]_0 , \resume_wait_r_reg[5] , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, bypass__0, \not_strict_mode.app_rd_data_end_reg , rd_buf_we, rst_sync_r1_reg, \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , D, \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[228] , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_bank_reg[2]_0 , \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , pointer_we, \not_strict_mode.app_rd_data_reg[255]_0 , app_rd_data_end_ns, \write_buffer.wr_buf_out_data_reg[287] , \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , wr_en, wr_en_5, wr_en_6, ddr_ck_out, \qcntr_r_reg[0] , ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, CLK, p_67_out, p_28_out, SR, hi_priority, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__20, app_ref_req, app_zq_req, rstdiv0_sync_r1_reg_rep__21, app_hi_pri_r2, app_sr_req, rstdiv0_sync_r1_reg_rep__22, mmcm_ps_clk, rst_sync_r1, poc_sample_pd, freq_refclk, mem_refclk, sync_pulse, pll_locked, in0, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__10, \req_bank_r_lcl_reg[0] , rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__23, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__17, rstdiv0_sync_r1_reg_rep__16, SS, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__6, Q, mem_out, \rd_ptr_reg[3] , rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__25_0, rstdiv0_sync_r1_reg_rep__24, \sm_r_reg[0]_0 , \rd_ptr_reg[3]_0 , \req_bank_r_lcl_reg[0]_0 , \rd_buf_indx.rd_buf_indx_r_reg[4] , ram_init_done_r, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, rstdiv0_sync_r1_reg_rep__25_1, rstdiv0_sync_r1_reg_rep__25_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , cmd, use_addr, bm_end_r1_reg_1, bm_end_r1_reg_2, rtp_timer_ns1, pass_open_bank_r_lcl_reg, \generate_maint_cmds.insert_maint_r_lcl_reg , \app_addr_r1_reg[27] , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , \not_strict_mode.status_ram.rd_buf_we_r1_reg , \app_addr_r1_reg[12] , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[9] , psdone, rstdiv0_sync_r1_reg_rep__19, fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__23_0, p_81_in, rstdiv0_sync_r1_reg_rep__23_1, po_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__7, \stg3_r_reg[0] , rstdiv0_sync_r1_reg_rep__8); output insert_maint_r1_lcl_reg; output app_ref_ack; output app_zq_ack; output accept_ns; output [1:0]idle_ns; output bm_end_r1; output bm_end_r1_reg; output bm_end_r1_0; output bm_end_r1_reg_0; output [0:0]E; output app_sr_active; output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [5:0]phy_dout; output \samps_r_reg[9] ; output init_calib_complete_r_reg; output \calib_seq_reg[0] ; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_en_stg2_f_timing_reg; output dqs_po_en_stg2_f_reg; output [37:0]\rd_ptr_timing_reg[0] ; output [4:0]\rd_ptr_timing_reg[0]_0 ; output [0:0]\resume_wait_r_reg[5] ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output bypass__0; output [6:0]\not_strict_mode.app_rd_data_end_reg ; output rd_buf_we; output rst_sync_r1_reg; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]D; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[228] ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output pointer_we; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output app_rd_data_end_ns; output [3:0]\write_buffer.wr_buf_out_data_reg[287] ; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output wr_en; output wr_en_5; output wr_en_6; output [1:0]ddr_ck_out; output [0:0]\qcntr_r_reg[0] ; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input CLK; input p_67_out; input p_28_out; input [0:0]SR; input hi_priority; input rstdiv0_sync_r1_reg_rep__0; input rstdiv0_sync_r1_reg_rep__20; input app_ref_req; input app_zq_req; input rstdiv0_sync_r1_reg_rep__21; input app_hi_pri_r2; input app_sr_req; input rstdiv0_sync_r1_reg_rep__22; input mmcm_ps_clk; input rst_sync_r1; input poc_sample_pd; input freq_refclk; input mem_refclk; input sync_pulse; input pll_locked; input in0; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__10; input \req_bank_r_lcl_reg[0] ; input [0:0]rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__23; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [1:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__6; input [287:0]Q; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input rstdiv0_sync_r1_reg_rep__25; input rstdiv0_sync_r1_reg_rep__25_0; input rstdiv0_sync_r1_reg_rep__24; input [0:0]\sm_r_reg[0]_0 ; input [29:0]\rd_ptr_reg[3]_0 ; input \req_bank_r_lcl_reg[0]_0 ; input [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; input ram_init_done_r; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input rstdiv0_sync_r1_reg_rep__25_1; input rstdiv0_sync_r1_reg_rep__25_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input [1:0]cmd; input use_addr; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input rtp_timer_ns1; input pass_open_bank_r_lcl_reg; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input [14:0]\app_addr_r1_reg[27] ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; input [2:0]\app_addr_r1_reg[12] ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [6:0]\app_addr_r1_reg[9] ; input psdone; input [0:0]rstdiv0_sync_r1_reg_rep__19; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__23_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__23_1; input [0:0]po_cnt_dec_reg; input [0:0]rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input [0:0]rstdiv0_sync_r1_reg_rep__7; input \stg3_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__8; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [0:0]E; wire [287:0]Q; wire RST0; wire [0:0]SR; wire [0:0]SS; wire accept_ns; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire app_hi_pri_r2; wire app_rd_data_end_ns; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bypass__0; wire \calib_seq_reg[0] ; wire [1:0]cmd; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; wire cnt_pwron_reset_done_r0; wire \col_mach0/p_0_in ; wire \complex_row_cnt_ocal_reg[0] ; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire ddr_phy_top0_n_359; wire ddr_phy_top0_n_360; wire ddr_phy_top0_n_361; wire ddr_phy_top0_n_362; wire ddr_phy_top0_n_363; wire ddr_phy_top0_n_364; wire ddr_phy_top0_n_365; wire ddr_phy_top0_n_366; wire ddr_phy_top0_n_367; wire ddr_phy_top0_n_368; wire ddr_phy_top0_n_369; wire ddr_phy_top0_n_370; wire ddr_phy_top0_n_371; wire ddr_phy_top0_n_372; wire ddr_phy_top0_n_373; wire ddr_phy_top0_n_374; wire ddr_phy_top0_n_375; wire ddr_phy_top0_n_376; wire ddr_phy_top0_n_377; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_50; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_51; wire ddr_phy_top0_n_637; wire ddr_phy_top0_n_638; wire ddr_phy_top0_n_97; wire [11:0]\device_temp_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire dqs_po_en_stg2_f_reg; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire fine_adjust_reg; wire freq_refclk; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire hi_priority; wire idle; wire [1:0]idle_ns; wire in0; wire init_calib_complete_r_reg; wire insert_maint_r1_lcl_reg; wire mc0_n_109; wire mc0_n_110; wire mc0_n_111; wire mc0_n_112; wire mc0_n_113; wire mc0_n_114; wire mc0_n_115; wire mc0_n_116; wire mc0_n_117; wire mc0_n_118; wire mc0_n_119; wire mc0_n_120; wire [44:0]mc_address; wire [8:0]mc_bank; wire [2:0]mc_cas_n; wire [3:3]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_we_n; wire mc_wrdata_en; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [43:13]mux_address; wire [6:0]\not_strict_mode.app_rd_data_end_reg ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire p_28_out; wire p_67_out; wire p_81_in; wire pass_open_bank_r_lcl_reg; wire [5:0]phy_dout; wire phy_mc_ctl_full; wire [0:0]pi_cnt_dec_reg; wire pi_en_stg2_f_timing_reg; wire \pi_rst_stg1_cal_r_reg[0] ; wire pll_locked; wire [0:0]po_cnt_dec_reg; wire poc_sample_pd; wire pointer_we; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire ram_init_done_r; wire \rank_mach0/rank_common0/maint_prescaler_r1 ; wire [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; wire rd_buf_we; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [37:0]\rd_ptr_timing_reg[0] ; wire [4:0]\rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[0]_0 ; wire [0:0]\resume_wait_r_reg[5] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [1:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__23_0; wire rstdiv0_sync_r1_reg_rep__23_1; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__25_1; wire rstdiv0_sync_r1_reg_rep__25_2; wire [0:0]rstdiv0_sync_r1_reg_rep__4; wire rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire [0:0]rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire rtp_timer_ns1; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire \samps_r_reg[9] ; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire tempmon_sample_en; wire [1:1]\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ; wire use_addr; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; wire [3:0]\write_buffer.wr_buf_out_data_reg[287] ; ddr3_ifmig_7series_v4_0_ddr_phy_top ddr_phy_top0 (.CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .D(D), .DOA(DOA), .DOB(DOB), .DOC(DOC), .Q(Q), .RST0(RST0), .SR(SR), .SS(SS), .app_zq_r_reg(ddr_phy_top0_n_50), .\calib_seq_reg[0] (\calib_seq_reg[0] ), .\cmd_pipe_plus.mc_address_reg[43] ({mux_address[43],mux_address[13]}), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (ddr_phy_top0_n_377), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (mc0_n_118), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (ddr_phy_top0_n_374), .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (mc0_n_117), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (mc0_n_120), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (mc0_n_119), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (ddr_phy_top0_n_367), .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (mc0_n_116), .\cmd_pipe_plus.mc_data_offset_1_reg[5] ({ddr_phy_top0_n_368,ddr_phy_top0_n_369,ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373}), .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (mc0_n_115), .\cmd_pipe_plus.mc_data_offset_reg[0] (ddr_phy_top0_n_376), .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_112), .\cmd_pipe_plus.mc_data_offset_reg[1] (ddr_phy_top0_n_366), .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_111), .\cmd_pipe_plus.mc_data_offset_reg[2] (mc0_n_114), .\cmd_pipe_plus.mc_data_offset_reg[3] (mc0_n_113), .\cmd_pipe_plus.mc_data_offset_reg[4] (ddr_phy_top0_n_359), .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_110), .\cmd_pipe_plus.mc_data_offset_reg[5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}), .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_109), .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0), .\complex_row_cnt_ocal_reg[0] (\complex_row_cnt_ocal_reg[0] ), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .fine_adjust_reg(fine_adjust_reg), .freq_refclk(freq_refclk), .idle(idle), .in0(in0), .init_calib_complete_r_reg(init_calib_complete_r_reg), .maint_prescaler_r1(\rank_mach0/rank_common0/maint_prescaler_r1 ), .mc_address({mc_address[44:30],mc_address[25:18],mc_address[14:0]}), .mc_bank(mc_bank), .mc_cas_n(mc_cas_n), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_cs_n(mc_cs_n), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n), .mc_we_n(mc_we_n), .mc_wrdata_en(mc_wrdata_en), .mem_out(mem_out), .mem_refclk(mem_refclk), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), .\not_strict_mode.app_rd_data_reg[227] (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[228] (\not_strict_mode.app_rd_data_reg[228] ), .\not_strict_mode.app_rd_data_reg[229] (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[22] (\not_strict_mode.app_rd_data_reg[22] ), .\not_strict_mode.app_rd_data_reg[230] (\not_strict_mode.app_rd_data_reg[230] ), .\not_strict_mode.app_rd_data_reg[231] (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ), .\not_strict_mode.app_rd_data_reg[233] (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[234] (\not_strict_mode.app_rd_data_reg[234] ), .\not_strict_mode.app_rd_data_reg[235] (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[236] (\not_strict_mode.app_rd_data_reg[236] ), .\not_strict_mode.app_rd_data_reg[237] (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[238] (\not_strict_mode.app_rd_data_reg[238] ), .\not_strict_mode.app_rd_data_reg[239] (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[23] (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[240] (\not_strict_mode.app_rd_data_reg[240] ), .\not_strict_mode.app_rd_data_reg[241] (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255]_0 ), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), .\not_strict_mode.app_rd_data_reg[70] (\not_strict_mode.app_rd_data_reg[70] ), .\not_strict_mode.app_rd_data_reg[71] (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[72] (\not_strict_mode.app_rd_data_reg[72] ), .\not_strict_mode.app_rd_data_reg[73] (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[74] (\not_strict_mode.app_rd_data_reg[74] ), .\not_strict_mode.app_rd_data_reg[75] (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[76] (\not_strict_mode.app_rd_data_reg[76] ), .\not_strict_mode.app_rd_data_reg[77] (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[78] (\not_strict_mode.app_rd_data_reg[78] ), .\not_strict_mode.app_rd_data_reg[79] (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[7] (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (ddr_phy_top0_n_97), .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ), .ofs_rdy_r_reg(ddr_phy_top0_n_637), .ofs_rdy_r_reg_0(ddr_phy_top0_n_638), .p_81_in(p_81_in), .\periodic_rd_generation.periodic_rd_timer_r_reg[1] (ddr_phy_top0_n_51), .phy_dout({phy_dout[5:3],phy_dout[1]}), .phy_mc_ctl_full(phy_mc_ctl_full), .pi_cnt_dec_reg(pi_cnt_dec_reg), .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg), .\pi_rst_stg1_cal_r_reg[0] (\pi_rst_stg1_cal_r_reg[0] ), .pll_locked(pll_locked), .po_cnt_dec_reg(po_cnt_dec_reg), .poc_sample_pd(poc_sample_pd), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[0] ({\rd_ptr_timing_reg[0] [37:6],\rd_ptr_timing_reg[0] [4],\rd_ptr_timing_reg[0] [1]}), .\rd_ptr_timing_reg[0]_0 ({\rd_ptr_timing_reg[0]_0 [3],\rd_ptr_timing_reg[0]_0 [1]}), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\col_mach0/p_0_in ), .\read_fifo.fifo_out_data_r_reg[6]_0 (bypass__0), .\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_375), .\resume_wait_r_reg[5] (\resume_wait_r_reg[5] ), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0), .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0), .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1), .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg), .\samps_r_reg[9] (\samps_r_reg[9] ), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .tempmon_sample_en(tempmon_sample_en), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_1 )); ddr3_ifmig_7series_v4_0_mc mc0 (.CLK(CLK), .E(idle_ns[0]), .Q({\not_strict_mode.app_rd_data_end_reg [6],\col_mach0/p_0_in ,\not_strict_mode.app_rd_data_end_reg [5:0]}), .SR(SR), .accept_ns(accept_ns), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .app_hi_pri_r2(app_hi_pri_r2), .app_rd_data_end_ns(app_rd_data_end_ns), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .bm_end_r1(bm_end_r1), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg(bm_end_r1_reg), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bypass__0(bypass__0), .cmd(cmd), .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2] ), .\cmd_pipe_plus.mc_bank_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .\data_offset_1_i1_reg[0] (mc0_n_118), .\data_offset_1_i1_reg[1] (mc0_n_117), .\data_offset_1_i1_reg[2] (mc0_n_120), .\data_offset_1_i1_reg[3] (mc0_n_119), .\data_offset_1_i1_reg[4] (mc0_n_116), .\data_offset_1_i1_reg[5] (mc0_n_115), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (ddr_phy_top0_n_97), .\entry_cnt_reg[2] (ddr_phy_top0_n_638), .\entry_cnt_reg[2]_0 (ddr_phy_top0_n_637), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .hi_priority(hi_priority), .idle(idle), .idle_r_lcl_reg(idle_ns[1]), .init_calib_complete_reg_rep__6(ddr_phy_top0_n_50), .init_calib_complete_reg_rep__7(ddr_phy_top0_n_51), .insert_maint_r1_lcl_reg(insert_maint_r1_lcl_reg), .maint_prescaler_r1(\rank_mach0/rank_common0/maint_prescaler_r1 ), .mc_address({mc_address[44:30],mc_address[25:18],mc_address[14:0]}), .mc_bank(mc_bank), .mc_cas_n(mc_cas_n), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_cs_n(mc_cs_n), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n), .mc_we_n(mc_we_n), .mc_wrdata_en(mc_wrdata_en), .\my_empty_reg[7] ({mux_address[43],mux_address[13]}), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ), .p_28_out(p_28_out), .p_67_out(p_67_out), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .\phy_ctl_wd_i1_reg[17] (mc0_n_112), .\phy_ctl_wd_i1_reg[18] (mc0_n_111), .\phy_ctl_wd_i1_reg[19] (mc0_n_114), .\phy_ctl_wd_i1_reg[20] (mc0_n_113), .\phy_ctl_wd_i1_reg[21] (mc0_n_110), .\phy_ctl_wd_i1_reg[22] (mc0_n_109), .phy_dout({phy_dout[2],phy_dout[0]}), .phy_mc_ctl_full(phy_mc_ctl_full), .pointer_we(pointer_we), .ram_init_done_r(ram_init_done_r), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_366), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (ddr_phy_top0_n_376), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (ddr_phy_top0_n_359), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (ddr_phy_top0_n_367), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ({ddr_phy_top0_n_368,ddr_phy_top0_n_369,ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373}), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (ddr_phy_top0_n_374), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 (ddr_phy_top0_n_377), .\rd_buf_indx.rd_buf_indx_r_reg[4] (\rd_buf_indx.rd_buf_indx_r_reg[4] ), .\rd_ptr_timing_reg[0] ({\rd_ptr_timing_reg[0]_0 [4],\rd_ptr_timing_reg[0]_0 [2],\rd_ptr_timing_reg[0]_0 [0]}), .\rd_ptr_timing_reg[0]_0 ({\rd_ptr_timing_reg[0] [5],\rd_ptr_timing_reg[0] [3:2],\rd_ptr_timing_reg[0] [0]}), .\read_data_indx.rd_data_indx_r_reg[0] (E), .\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_375), .\read_fifo.tail_r_reg[1] (tail_r), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .\req_bank_r_lcl_reg[0]_0 (\req_bank_r_lcl_reg[0]_0 ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1(rtp_timer_ns1), .tempmon_sample_en(tempmon_sample_en), .use_addr(use_addr), .\write_buffer.wr_buf_out_data_reg[287] (\write_buffer.wr_buf_out_data_reg[287] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_memc_ui_top_axi" *) module ddr3_ifmig_7series_v4_0_memc_ui_top_axi (insert_maint_r, app_ref_ack, app_zq_ack, bm_end_r1, pass_open_bank_r, bm_end_r1_0, pass_open_bank_r_1, app_sr_active, ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , phy_dout, sm_r, phy_mc_go, \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_cnt_dec, po_cnt_dec, \rd_ptr_timing_reg[0] , \rd_ptr_timing_reg[0]_0 , \resume_wait_r_reg[5] , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, rst_sync_r1_reg, s_axi_arready, \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , D, \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , Q, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , wr_en, wr_en_5, wr_en_6, ddr_ck_out, E, s_axi_awready, s_axi_wready, out, s_axi_rid, s_axi_bid, s_axi_bvalid, s_axi_rvalid, s_axi_rlast, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, CLK, SR, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__20, app_ref_req, app_zq_req, rstdiv0_sync_r1_reg_rep__21, app_sr_req, rstdiv0_sync_r1_reg_rep__22, mmcm_ps_clk, rst_sync_r1, poc_sample_pd, freq_refclk, mem_refclk, sync_pulse, pll_locked, in0, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__23, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__17, rstdiv0_sync_r1_reg_rep__16, SS, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__6, mem_out, \rd_ptr_reg[3] , rstdiv0_sync_r1_reg_rep__25_0, rstdiv0_sync_r1_reg_rep__24, \sm_r_reg[0]_0 , \rd_ptr_reg[3]_0 , sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, s_axi_arvalid, rstdiv0_sync_r1_reg_rep__25_1, rstdiv0_sync_r1_reg_rep__25_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , bm_end_r1_reg, bm_end_r1_reg_0, rtp_timer_ns1, pass_open_bank_r_lcl_reg, \generate_maint_cmds.insert_maint_r_lcl_reg , psdone, rstdiv0_sync_r1_reg_rep__19, fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__23_0, p_81_in, rstdiv0_sync_r1_reg_rep__23_1, po_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__7, \stg3_r_reg[0] , rstdiv0_sync_r1_reg_rep__8, s_axi_awlen, s_axi_bready, s_axi_awvalid, s_axi_awaddr, s_axi_awburst, s_axi_wvalid, s_axi_awid, s_axi_arlen, s_axi_araddr, s_axi_arburst, s_axi_rready, s_axi_wstrb, s_axi_wdata, aresetn, s_axi_arid); output insert_maint_r; output app_ref_ack; output app_zq_ack; output bm_end_r1; output pass_open_bank_r; output bm_end_r1_0; output pass_open_bank_r_1; output app_sr_active; output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [5:0]phy_dout; output sm_r; output phy_mc_go; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_cnt_dec; output po_cnt_dec; output [37:0]\rd_ptr_timing_reg[0] ; output [4:0]\rd_ptr_timing_reg[0]_0 ; output \resume_wait_r_reg[5] ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output rst_sync_r1_reg; output s_axi_arready; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]D; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output [3:0]Q; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output wr_en; output wr_en_5; output wr_en_6; output [1:0]ddr_ck_out; output [0:0]E; output s_axi_awready; output s_axi_wready; output [256:0]out; output [0:0]s_axi_rid; output [0:0]s_axi_bid; output s_axi_bvalid; output s_axi_rvalid; output s_axi_rlast; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input CLK; input [0:0]SR; input rstdiv0_sync_r1_reg_rep__0; input rstdiv0_sync_r1_reg_rep__20; input app_ref_req; input app_zq_req; input rstdiv0_sync_r1_reg_rep__21; input app_sr_req; input rstdiv0_sync_r1_reg_rep__22; input mmcm_ps_clk; input rst_sync_r1; input poc_sample_pd; input freq_refclk; input mem_refclk; input sync_pulse; input pll_locked; input in0; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__25; input [0:0]rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__23; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [1:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__6; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input rstdiv0_sync_r1_reg_rep__25_0; input rstdiv0_sync_r1_reg_rep__24; input [0:0]\sm_r_reg[0]_0 ; input [29:0]\rd_ptr_reg[3]_0 ; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input s_axi_arvalid; input rstdiv0_sync_r1_reg_rep__25_1; input rstdiv0_sync_r1_reg_rep__25_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input bm_end_r1_reg; input bm_end_r1_reg_0; input rtp_timer_ns1; input pass_open_bank_r_lcl_reg; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input psdone; input [0:0]rstdiv0_sync_r1_reg_rep__19; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__23_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__23_1; input [0:0]po_cnt_dec_reg; input [0:0]rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input [0:0]rstdiv0_sync_r1_reg_rep__7; input \stg3_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__8; input [7:0]s_axi_awlen; input s_axi_bready; input s_axi_awvalid; input [29:0]s_axi_awaddr; input [0:0]s_axi_awburst; input s_axi_wvalid; input [0:0]s_axi_awid; input [7:0]s_axi_arlen; input [29:0]s_axi_araddr; input [0:0]s_axi_arburst; input s_axi_rready; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; input aresetn; input [0:0]s_axi_arid; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [0:0]E; wire [3:0]Q; wire RST0; wire [0:0]SR; wire [0:0]SS; wire accept_ns; wire [27:3]app_addr; wire [0:0]app_cmd; wire [255:0]app_rd_data; wire [255:0]app_rd_data_ns; wire app_rd_data_valid; wire app_rdy; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire app_zq_ack; wire app_zq_req; wire aresetn; wire [255:0]\axi_mc_w_channel_0/mc_app_wdf_data_reg ; wire [31:0]\axi_mc_w_channel_0/mc_app_wdf_mask_reg ; wire \axi_mc_w_channel_0/mc_app_wdf_wren_reg ; wire [255:0]\axi_mc_w_channel_0/next_wdf_data ; wire [31:0]\axi_mc_w_channel_0/next_wdf_mask ; wire [2:0]bank; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire [1:0]cmd; wire cnt_pwron_reset_done_r0; wire [9:3]col; wire \complex_row_cnt_ocal_reg[0] ; wire [4:0]data_buf_addr; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire [11:0]\device_temp_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire fine_adjust_reg; wire freq_refclk; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire hi_priority; wire in0; wire init_calib_complete_r; wire insert_maint_r; wire [1:0]\mc0/bank_mach0/idle_ns ; wire \mc0/bank_mach0/p_28_out ; wire \mc0/bank_mach0/p_67_out ; wire [20:18]\mc0/p_2_in ; wire [2:0]\mc0/req_bank_r_lcl ; wire mem_intfc0_n_129; wire mem_intfc0_n_130; wire mem_intfc0_n_131; wire mem_intfc0_n_132; wire mem_intfc0_n_133; wire mem_intfc0_n_134; wire mem_intfc0_n_135; wire mem_intfc0_n_136; wire mem_intfc0_n_137; wire mem_intfc0_n_138; wire mem_intfc0_n_139; wire mem_intfc0_n_140; wire mem_intfc0_n_141; wire mem_intfc0_n_142; wire mem_intfc0_n_143; wire mem_intfc0_n_144; wire mem_intfc0_n_145; wire mem_intfc0_n_146; wire mem_intfc0_n_147; wire mem_intfc0_n_148; wire mem_intfc0_n_149; wire mem_intfc0_n_150; wire mem_intfc0_n_151; wire mem_intfc0_n_152; wire mem_intfc0_n_153; wire mem_intfc0_n_154; wire mem_intfc0_n_155; wire mem_intfc0_n_156; wire mem_intfc0_n_157; wire mem_intfc0_n_158; wire mem_intfc0_n_159; wire mem_intfc0_n_160; wire mem_intfc0_n_161; wire mem_intfc0_n_162; wire mem_intfc0_n_163; wire mem_intfc0_n_164; wire mem_intfc0_n_165; wire mem_intfc0_n_166; wire mem_intfc0_n_167; wire mem_intfc0_n_168; wire mem_intfc0_n_169; wire mem_intfc0_n_170; wire mem_intfc0_n_171; wire mem_intfc0_n_172; wire mem_intfc0_n_173; wire mem_intfc0_n_174; wire mem_intfc0_n_175; wire mem_intfc0_n_176; wire mem_intfc0_n_177; wire mem_intfc0_n_178; wire mem_intfc0_n_179; wire mem_intfc0_n_180; wire mem_intfc0_n_181; wire mem_intfc0_n_182; wire mem_intfc0_n_183; wire mem_intfc0_n_184; wire mem_intfc0_n_185; wire mem_intfc0_n_186; wire mem_intfc0_n_187; wire mem_intfc0_n_188; wire mem_intfc0_n_189; wire mem_intfc0_n_190; wire mem_intfc0_n_191; wire mem_intfc0_n_192; wire mem_intfc0_n_193; wire mem_intfc0_n_194; wire mem_intfc0_n_195; wire mem_intfc0_n_196; wire mem_intfc0_n_197; wire mem_intfc0_n_198; wire mem_intfc0_n_199; wire mem_intfc0_n_200; wire mem_intfc0_n_201; wire mem_intfc0_n_202; wire mem_intfc0_n_203; wire mem_intfc0_n_204; wire mem_intfc0_n_205; wire mem_intfc0_n_206; wire mem_intfc0_n_207; wire mem_intfc0_n_208; wire mem_intfc0_n_209; wire mem_intfc0_n_210; wire mem_intfc0_n_211; wire mem_intfc0_n_212; wire mem_intfc0_n_213; wire mem_intfc0_n_214; wire mem_intfc0_n_215; wire mem_intfc0_n_216; wire mem_intfc0_n_217; wire mem_intfc0_n_218; wire mem_intfc0_n_219; wire mem_intfc0_n_220; wire mem_intfc0_n_221; wire mem_intfc0_n_222; wire mem_intfc0_n_223; wire mem_intfc0_n_224; wire mem_intfc0_n_225; wire mem_intfc0_n_226; wire mem_intfc0_n_227; wire mem_intfc0_n_228; wire mem_intfc0_n_229; wire mem_intfc0_n_230; wire mem_intfc0_n_231; wire mem_intfc0_n_232; wire mem_intfc0_n_233; wire mem_intfc0_n_234; wire mem_intfc0_n_235; wire mem_intfc0_n_236; wire mem_intfc0_n_237; wire mem_intfc0_n_238; wire mem_intfc0_n_239; wire mem_intfc0_n_240; wire mem_intfc0_n_241; wire mem_intfc0_n_242; wire mem_intfc0_n_243; wire mem_intfc0_n_244; wire mem_intfc0_n_245; wire mem_intfc0_n_246; wire mem_intfc0_n_247; wire mem_intfc0_n_248; wire mem_intfc0_n_249; wire mem_intfc0_n_250; wire mem_intfc0_n_251; wire mem_intfc0_n_252; wire mem_intfc0_n_253; wire mem_intfc0_n_254; wire mem_intfc0_n_255; wire mem_intfc0_n_256; wire mem_intfc0_n_257; wire mem_intfc0_n_258; wire mem_intfc0_n_259; wire mem_intfc0_n_260; wire mem_intfc0_n_261; wire mem_intfc0_n_262; wire mem_intfc0_n_263; wire mem_intfc0_n_264; wire mem_intfc0_n_265; wire mem_intfc0_n_266; wire mem_intfc0_n_267; wire mem_intfc0_n_268; wire mem_intfc0_n_269; wire mem_intfc0_n_270; wire mem_intfc0_n_271; wire mem_intfc0_n_272; wire mem_intfc0_n_273; wire mem_intfc0_n_274; wire mem_intfc0_n_275; wire mem_intfc0_n_276; wire mem_intfc0_n_277; wire mem_intfc0_n_278; wire mem_intfc0_n_279; wire mem_intfc0_n_280; wire mem_intfc0_n_281; wire mem_intfc0_n_282; wire mem_intfc0_n_283; wire mem_intfc0_n_284; wire mem_intfc0_n_285; wire mem_intfc0_n_286; wire mem_intfc0_n_287; wire mem_intfc0_n_288; wire mem_intfc0_n_289; wire mem_intfc0_n_290; wire mem_intfc0_n_291; wire mem_intfc0_n_292; wire mem_intfc0_n_293; wire mem_intfc0_n_294; wire mem_intfc0_n_295; wire mem_intfc0_n_296; wire mem_intfc0_n_297; wire mem_intfc0_n_298; wire mem_intfc0_n_299; wire mem_intfc0_n_300; wire mem_intfc0_n_301; wire mem_intfc0_n_302; wire mem_intfc0_n_303; wire mem_intfc0_n_304; wire mem_intfc0_n_305; wire mem_intfc0_n_306; wire mem_intfc0_n_307; wire mem_intfc0_n_308; wire mem_intfc0_n_309; wire mem_intfc0_n_310; wire mem_intfc0_n_311; wire mem_intfc0_n_312; wire mem_intfc0_n_313; wire mem_intfc0_n_314; wire mem_intfc0_n_315; wire mem_intfc0_n_316; wire mem_intfc0_n_317; wire mem_intfc0_n_318; wire mem_intfc0_n_319; wire mem_intfc0_n_320; wire mem_intfc0_n_321; wire mem_intfc0_n_322; wire mem_intfc0_n_323; wire mem_intfc0_n_324; wire mem_intfc0_n_325; wire mem_intfc0_n_326; wire mem_intfc0_n_327; wire mem_intfc0_n_328; wire mem_intfc0_n_329; wire mem_intfc0_n_330; wire mem_intfc0_n_331; wire mem_intfc0_n_332; wire mem_intfc0_n_333; wire mem_intfc0_n_334; wire mem_intfc0_n_335; wire mem_intfc0_n_336; wire mem_intfc0_n_337; wire mem_intfc0_n_338; wire mem_intfc0_n_339; wire mem_intfc0_n_340; wire mem_intfc0_n_341; wire mem_intfc0_n_342; wire mem_intfc0_n_343; wire mem_intfc0_n_344; wire mem_intfc0_n_345; wire mem_intfc0_n_346; wire mem_intfc0_n_347; wire mem_intfc0_n_348; wire mem_intfc0_n_349; wire mem_intfc0_n_350; wire mem_intfc0_n_351; wire mem_intfc0_n_352; wire mem_intfc0_n_353; wire mem_intfc0_n_354; wire mem_intfc0_n_355; wire mem_intfc0_n_356; wire mem_intfc0_n_357; wire mem_intfc0_n_358; wire mem_intfc0_n_359; wire mem_intfc0_n_360; wire mem_intfc0_n_361; wire mem_intfc0_n_362; wire mem_intfc0_n_363; wire mem_intfc0_n_364; wire mem_intfc0_n_365; wire mem_intfc0_n_366; wire mem_intfc0_n_367; wire mem_intfc0_n_368; wire mem_intfc0_n_369; wire mem_intfc0_n_370; wire mem_intfc0_n_371; wire mem_intfc0_n_372; wire mem_intfc0_n_373; wire mem_intfc0_n_374; wire mem_intfc0_n_375; wire mem_intfc0_n_376; wire mem_intfc0_n_377; wire mem_intfc0_n_378; wire mem_intfc0_n_379; wire mem_intfc0_n_380; wire mem_intfc0_n_381; wire mem_intfc0_n_382; wire mem_intfc0_n_383; wire mem_intfc0_n_384; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire mem_intfc0_n_64; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [256:0]out; wire p_81_in; wire pass_open_bank_r; wire pass_open_bank_r_1; wire pass_open_bank_r_lcl_reg; wire [5:0]phy_dout; wire phy_mc_go; wire pi_cnt_dec; wire [0:0]pi_cnt_dec_reg; wire \pi_rst_stg1_cal_r_reg[0] ; wire pll_locked; wire po_cnt_dec; wire [0:0]po_cnt_dec_reg; wire poc_sample_pd; wire psdone; wire [3:0]ram_init_addr; wire ram_init_done_r; wire [4:0]rd_data_addr; wire rd_data_end; wire rd_data_offset; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [37:0]\rd_ptr_timing_reg[0] ; wire [4:0]\rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire reset_reg_n_0; wire \resume_wait_r_reg[5] ; wire [14:0]row; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [1:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__23_0; wire rstdiv0_sync_r1_reg_rep__23_1; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__25_0; wire rstdiv0_sync_r1_reg_rep__25_1; wire rstdiv0_sync_r1_reg_rep__25_2; wire [0:0]rstdiv0_sync_r1_reg_rep__4; wire rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire [0:0]rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire rtp_timer_ns1; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire sm_r; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_rst; wire u_ui_top_n_1; wire u_ui_top_n_260; wire u_ui_top_n_261; wire u_ui_top_n_272; wire u_ui_top_n_274; wire \ui_cmd0/app_addr_r10 ; wire \ui_cmd0/app_en_ns1 ; wire \ui_cmd0/app_en_r1 ; wire \ui_cmd0/app_hi_pri_r2 ; wire \ui_rd_data0/app_rd_data_end_ns ; wire \ui_rd_data0/bypass__0 ; wire [1:0]\ui_rd_data0/p_100_out ; wire [1:0]\ui_rd_data0/p_101_out ; wire [1:0]\ui_rd_data0/p_102_out ; wire [1:0]\ui_rd_data0/p_103_out ; wire [1:0]\ui_rd_data0/p_104_out ; wire [1:0]\ui_rd_data0/p_105_out ; wire [1:0]\ui_rd_data0/p_106_out ; wire [1:0]\ui_rd_data0/p_107_out ; wire [1:0]\ui_rd_data0/p_108_out ; wire [1:0]\ui_rd_data0/p_109_out ; wire [1:0]\ui_rd_data0/p_10_out ; wire [1:0]\ui_rd_data0/p_110_out ; wire [1:0]\ui_rd_data0/p_111_out ; wire [1:0]\ui_rd_data0/p_112_out ; wire [1:0]\ui_rd_data0/p_113_out ; wire [1:0]\ui_rd_data0/p_114_out ; wire [1:0]\ui_rd_data0/p_115_out ; wire [1:0]\ui_rd_data0/p_116_out ; wire [1:0]\ui_rd_data0/p_117_out ; wire [1:0]\ui_rd_data0/p_118_out ; wire [1:0]\ui_rd_data0/p_119_out ; wire [1:0]\ui_rd_data0/p_11_out ; wire [1:0]\ui_rd_data0/p_120_out ; wire [1:0]\ui_rd_data0/p_121_out ; wire [1:0]\ui_rd_data0/p_122_out ; wire [1:0]\ui_rd_data0/p_123_out ; wire [1:0]\ui_rd_data0/p_124_out ; wire [1:0]\ui_rd_data0/p_125_out ; wire [1:0]\ui_rd_data0/p_127_out ; wire [1:0]\ui_rd_data0/p_128_out ; wire [1:0]\ui_rd_data0/p_129_out ; wire [1:0]\ui_rd_data0/p_12_out ; wire [1:0]\ui_rd_data0/p_13_out ; wire [1:0]\ui_rd_data0/p_14_out ; wire [1:0]\ui_rd_data0/p_15_out ; wire [1:0]\ui_rd_data0/p_16_out ; wire [1:0]\ui_rd_data0/p_17_out ; wire [1:0]\ui_rd_data0/p_18_out ; wire [1:0]\ui_rd_data0/p_19_out ; wire [1:0]\ui_rd_data0/p_1_out ; wire [1:0]\ui_rd_data0/p_20_out ; wire [1:0]\ui_rd_data0/p_21_out ; wire [1:0]\ui_rd_data0/p_22_out ; wire [1:0]\ui_rd_data0/p_23_out ; wire [1:0]\ui_rd_data0/p_24_out ; wire [1:0]\ui_rd_data0/p_25_out ; wire [1:0]\ui_rd_data0/p_26_out ; wire [1:0]\ui_rd_data0/p_27_out ; wire [1:0]\ui_rd_data0/p_28_out ; wire [1:0]\ui_rd_data0/p_29_out ; wire [1:0]\ui_rd_data0/p_30_out ; wire [1:0]\ui_rd_data0/p_31_out ; wire [1:0]\ui_rd_data0/p_32_out ; wire [1:0]\ui_rd_data0/p_33_out ; wire [1:0]\ui_rd_data0/p_34_out ; wire [1:0]\ui_rd_data0/p_35_out ; wire [1:0]\ui_rd_data0/p_36_out ; wire [1:0]\ui_rd_data0/p_37_out ; wire [1:0]\ui_rd_data0/p_38_out ; wire [1:0]\ui_rd_data0/p_39_out ; wire [1:0]\ui_rd_data0/p_3_out ; wire [1:0]\ui_rd_data0/p_40_out ; wire [1:0]\ui_rd_data0/p_41_out ; wire [1:0]\ui_rd_data0/p_42_out ; wire [1:0]\ui_rd_data0/p_43_out ; wire [1:0]\ui_rd_data0/p_44_out ; wire [1:0]\ui_rd_data0/p_45_out ; wire [1:0]\ui_rd_data0/p_46_out ; wire [1:0]\ui_rd_data0/p_47_out ; wire [1:0]\ui_rd_data0/p_48_out ; wire [1:0]\ui_rd_data0/p_49_out ; wire [1:0]\ui_rd_data0/p_4_out ; wire [1:0]\ui_rd_data0/p_50_out ; wire [1:0]\ui_rd_data0/p_51_out ; wire [1:0]\ui_rd_data0/p_52_out ; wire [1:0]\ui_rd_data0/p_53_out ; wire [1:0]\ui_rd_data0/p_54_out ; wire [1:0]\ui_rd_data0/p_55_out ; wire [1:0]\ui_rd_data0/p_56_out ; wire [1:0]\ui_rd_data0/p_57_out ; wire [1:0]\ui_rd_data0/p_58_out ; wire [1:0]\ui_rd_data0/p_59_out ; wire [1:0]\ui_rd_data0/p_5_out ; wire [1:0]\ui_rd_data0/p_60_out ; wire [1:0]\ui_rd_data0/p_61_out ; wire [1:0]\ui_rd_data0/p_62_out ; wire [1:0]\ui_rd_data0/p_63_out ; wire [1:0]\ui_rd_data0/p_64_out ; wire [1:0]\ui_rd_data0/p_65_out ; wire [1:0]\ui_rd_data0/p_66_out ; wire [1:0]\ui_rd_data0/p_67_out ; wire [1:0]\ui_rd_data0/p_68_out ; wire [1:0]\ui_rd_data0/p_69_out ; wire [1:0]\ui_rd_data0/p_6_out ; wire [1:0]\ui_rd_data0/p_70_out ; wire [1:0]\ui_rd_data0/p_71_out ; wire [1:0]\ui_rd_data0/p_72_out ; wire [1:0]\ui_rd_data0/p_73_out ; wire [1:0]\ui_rd_data0/p_74_out ; wire [1:0]\ui_rd_data0/p_75_out ; wire [1:0]\ui_rd_data0/p_76_out ; wire [1:0]\ui_rd_data0/p_77_out ; wire [1:0]\ui_rd_data0/p_78_out ; wire [1:0]\ui_rd_data0/p_79_out ; wire [1:0]\ui_rd_data0/p_7_out ; wire [1:0]\ui_rd_data0/p_80_out ; wire [1:0]\ui_rd_data0/p_81_out ; wire [1:0]\ui_rd_data0/p_82_out ; wire [1:0]\ui_rd_data0/p_83_out ; wire [1:0]\ui_rd_data0/p_84_out ; wire [1:0]\ui_rd_data0/p_85_out ; wire [1:0]\ui_rd_data0/p_86_out ; wire [1:0]\ui_rd_data0/p_87_out ; wire [1:0]\ui_rd_data0/p_88_out ; wire [1:0]\ui_rd_data0/p_89_out ; wire [1:0]\ui_rd_data0/p_8_out ; wire [1:0]\ui_rd_data0/p_90_out ; wire [1:0]\ui_rd_data0/p_91_out ; wire [1:0]\ui_rd_data0/p_92_out ; wire [1:0]\ui_rd_data0/p_93_out ; wire [1:0]\ui_rd_data0/p_94_out ; wire [1:0]\ui_rd_data0/p_95_out ; wire [1:0]\ui_rd_data0/p_96_out ; wire [1:0]\ui_rd_data0/p_97_out ; wire [1:0]\ui_rd_data0/p_98_out ; wire [1:0]\ui_rd_data0/p_99_out ; wire [1:0]\ui_rd_data0/p_9_out ; wire \ui_rd_data0/rd_buf_we ; wire [1:1]\ui_rd_data0/rd_status ; wire \ui_wr_data0/pointer_we ; wire use_addr; wire w_cmd_rdy; wire [255:0]wr_data; wire [3:0]wr_data_addr; wire wr_data_en; wire [31:0]wr_data_mask; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; FDRE #( .INIT(1'b0)) init_calib_complete_r_reg (.C(CLK), .CE(1'b1), .D(mem_intfc0_n_64), .Q(init_calib_complete_r), .R(1'b0)); ddr3_ifmig_7series_v4_0_mem_intfc mem_intfc0 (.CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .D(D), .DOA(\ui_rd_data0/p_129_out ), .DOB(\ui_rd_data0/p_128_out ), .DOC(\ui_rd_data0/p_127_out ), .E(wr_data_en), .Q({wr_data_mask,wr_data}), .RST0(RST0), .SR(SR), .SS(SS), .accept_ns(accept_ns), .\app_addr_r1_reg[12] (bank), .\app_addr_r1_reg[27] (row), .\app_addr_r1_reg[9] (col), .app_hi_pri_r2(\ui_cmd0/app_hi_pri_r2 ), .app_rd_data_end_ns(\ui_rd_data0/app_rd_data_end_ns ), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .bm_end_r1(bm_end_r1), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg(pass_open_bank_r), .bm_end_r1_reg_0(pass_open_bank_r_1), .bm_end_r1_reg_1(bm_end_r1_reg), .bm_end_r1_reg_2(bm_end_r1_reg_0), .bypass__0(\ui_rd_data0/bypass__0 ), .\calib_seq_reg[0] (phy_mc_go), .cmd(cmd), .\cmd_pipe_plus.mc_bank_reg[2] (\mc0/req_bank_r_lcl ), .\cmd_pipe_plus.mc_bank_reg[2]_0 (\mc0/p_2_in ), .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0), .\complex_row_cnt_ocal_reg[0] (\complex_row_cnt_ocal_reg[0] ), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .dqs_po_en_stg2_f_reg(po_cnt_dec), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .fine_adjust_reg(fine_adjust_reg), .freq_refclk(freq_refclk), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .hi_priority(hi_priority), .idle_ns(\mc0/bank_mach0/idle_ns ), .in0(in0), .init_calib_complete_r_reg(mem_intfc0_n_64), .insert_maint_r1_lcl_reg(insert_maint_r), .mem_out(mem_out), .mem_refclk(mem_refclk), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .\not_strict_mode.app_rd_data_end_reg ({rd_data_end,rd_data_addr,rd_data_offset}), .\not_strict_mode.app_rd_data_reg[0] (mem_intfc0_n_384), .\not_strict_mode.app_rd_data_reg[100] (mem_intfc0_n_272), .\not_strict_mode.app_rd_data_reg[101] (mem_intfc0_n_268), .\not_strict_mode.app_rd_data_reg[102] (mem_intfc0_n_264), .\not_strict_mode.app_rd_data_reg[103] (mem_intfc0_n_260), .\not_strict_mode.app_rd_data_reg[104] (mem_intfc0_n_286), .\not_strict_mode.app_rd_data_reg[105] (mem_intfc0_n_282), .\not_strict_mode.app_rd_data_reg[106] (mem_intfc0_n_278), .\not_strict_mode.app_rd_data_reg[107] (mem_intfc0_n_274), .\not_strict_mode.app_rd_data_reg[108] (mem_intfc0_n_270), .\not_strict_mode.app_rd_data_reg[109] (mem_intfc0_n_266), .\not_strict_mode.app_rd_data_reg[10] (mem_intfc0_n_374), .\not_strict_mode.app_rd_data_reg[110] (mem_intfc0_n_262), .\not_strict_mode.app_rd_data_reg[111] (mem_intfc0_n_258), .\not_strict_mode.app_rd_data_reg[112] (mem_intfc0_n_287), .\not_strict_mode.app_rd_data_reg[113] (mem_intfc0_n_283), .\not_strict_mode.app_rd_data_reg[114] (mem_intfc0_n_279), .\not_strict_mode.app_rd_data_reg[115] (mem_intfc0_n_275), .\not_strict_mode.app_rd_data_reg[116] (mem_intfc0_n_271), .\not_strict_mode.app_rd_data_reg[117] (mem_intfc0_n_267), .\not_strict_mode.app_rd_data_reg[118] (mem_intfc0_n_263), .\not_strict_mode.app_rd_data_reg[119] (mem_intfc0_n_259), .\not_strict_mode.app_rd_data_reg[11] (mem_intfc0_n_370), .\not_strict_mode.app_rd_data_reg[120] (mem_intfc0_n_285), .\not_strict_mode.app_rd_data_reg[121] (mem_intfc0_n_281), .\not_strict_mode.app_rd_data_reg[122] (mem_intfc0_n_277), .\not_strict_mode.app_rd_data_reg[123] (mem_intfc0_n_273), .\not_strict_mode.app_rd_data_reg[124] (mem_intfc0_n_269), .\not_strict_mode.app_rd_data_reg[125] (mem_intfc0_n_265), .\not_strict_mode.app_rd_data_reg[126] (mem_intfc0_n_261), .\not_strict_mode.app_rd_data_reg[127] (mem_intfc0_n_257), .\not_strict_mode.app_rd_data_reg[128] (mem_intfc0_n_256), .\not_strict_mode.app_rd_data_reg[129] (mem_intfc0_n_252), .\not_strict_mode.app_rd_data_reg[12] (mem_intfc0_n_366), .\not_strict_mode.app_rd_data_reg[130] (mem_intfc0_n_248), .\not_strict_mode.app_rd_data_reg[131] (mem_intfc0_n_244), .\not_strict_mode.app_rd_data_reg[132] (mem_intfc0_n_240), .\not_strict_mode.app_rd_data_reg[133] (mem_intfc0_n_236), .\not_strict_mode.app_rd_data_reg[134] (mem_intfc0_n_232), .\not_strict_mode.app_rd_data_reg[135] (mem_intfc0_n_228), .\not_strict_mode.app_rd_data_reg[136] (mem_intfc0_n_254), .\not_strict_mode.app_rd_data_reg[137] (mem_intfc0_n_250), .\not_strict_mode.app_rd_data_reg[138] (mem_intfc0_n_246), .\not_strict_mode.app_rd_data_reg[139] (mem_intfc0_n_242), .\not_strict_mode.app_rd_data_reg[13] (mem_intfc0_n_362), .\not_strict_mode.app_rd_data_reg[140] (mem_intfc0_n_238), .\not_strict_mode.app_rd_data_reg[141] (mem_intfc0_n_234), .\not_strict_mode.app_rd_data_reg[142] (mem_intfc0_n_230), .\not_strict_mode.app_rd_data_reg[143] (mem_intfc0_n_226), .\not_strict_mode.app_rd_data_reg[144] (mem_intfc0_n_255), .\not_strict_mode.app_rd_data_reg[145] (mem_intfc0_n_251), .\not_strict_mode.app_rd_data_reg[146] (mem_intfc0_n_247), .\not_strict_mode.app_rd_data_reg[147] (mem_intfc0_n_243), .\not_strict_mode.app_rd_data_reg[148] (mem_intfc0_n_239), .\not_strict_mode.app_rd_data_reg[149] (mem_intfc0_n_235), .\not_strict_mode.app_rd_data_reg[14] (mem_intfc0_n_358), .\not_strict_mode.app_rd_data_reg[150] (mem_intfc0_n_231), .\not_strict_mode.app_rd_data_reg[151] (mem_intfc0_n_227), .\not_strict_mode.app_rd_data_reg[152] (mem_intfc0_n_253), .\not_strict_mode.app_rd_data_reg[153] (mem_intfc0_n_249), .\not_strict_mode.app_rd_data_reg[154] (mem_intfc0_n_245), .\not_strict_mode.app_rd_data_reg[155] (mem_intfc0_n_241), .\not_strict_mode.app_rd_data_reg[156] (mem_intfc0_n_237), .\not_strict_mode.app_rd_data_reg[157] (mem_intfc0_n_233), .\not_strict_mode.app_rd_data_reg[158] (mem_intfc0_n_229), .\not_strict_mode.app_rd_data_reg[159] (mem_intfc0_n_225), .\not_strict_mode.app_rd_data_reg[15] (mem_intfc0_n_354), .\not_strict_mode.app_rd_data_reg[160] (mem_intfc0_n_224), .\not_strict_mode.app_rd_data_reg[161] (mem_intfc0_n_220), .\not_strict_mode.app_rd_data_reg[162] (mem_intfc0_n_216), .\not_strict_mode.app_rd_data_reg[163] (mem_intfc0_n_212), .\not_strict_mode.app_rd_data_reg[164] (mem_intfc0_n_208), .\not_strict_mode.app_rd_data_reg[165] (mem_intfc0_n_204), .\not_strict_mode.app_rd_data_reg[166] (mem_intfc0_n_200), .\not_strict_mode.app_rd_data_reg[167] (mem_intfc0_n_196), .\not_strict_mode.app_rd_data_reg[168] (mem_intfc0_n_222), .\not_strict_mode.app_rd_data_reg[169] (mem_intfc0_n_218), .\not_strict_mode.app_rd_data_reg[16] (mem_intfc0_n_383), .\not_strict_mode.app_rd_data_reg[170] (mem_intfc0_n_214), .\not_strict_mode.app_rd_data_reg[171] (mem_intfc0_n_210), .\not_strict_mode.app_rd_data_reg[172] (mem_intfc0_n_206), .\not_strict_mode.app_rd_data_reg[173] (mem_intfc0_n_202), .\not_strict_mode.app_rd_data_reg[174] (mem_intfc0_n_198), .\not_strict_mode.app_rd_data_reg[175] (mem_intfc0_n_194), .\not_strict_mode.app_rd_data_reg[176] (mem_intfc0_n_223), .\not_strict_mode.app_rd_data_reg[177] (mem_intfc0_n_219), .\not_strict_mode.app_rd_data_reg[178] (mem_intfc0_n_215), .\not_strict_mode.app_rd_data_reg[179] (mem_intfc0_n_211), .\not_strict_mode.app_rd_data_reg[17] (mem_intfc0_n_379), .\not_strict_mode.app_rd_data_reg[180] (mem_intfc0_n_207), .\not_strict_mode.app_rd_data_reg[181] (mem_intfc0_n_203), .\not_strict_mode.app_rd_data_reg[182] (mem_intfc0_n_199), .\not_strict_mode.app_rd_data_reg[183] (mem_intfc0_n_195), .\not_strict_mode.app_rd_data_reg[184] (mem_intfc0_n_221), .\not_strict_mode.app_rd_data_reg[185] (mem_intfc0_n_217), .\not_strict_mode.app_rd_data_reg[186] (mem_intfc0_n_213), .\not_strict_mode.app_rd_data_reg[187] (mem_intfc0_n_209), .\not_strict_mode.app_rd_data_reg[188] (mem_intfc0_n_205), .\not_strict_mode.app_rd_data_reg[189] (mem_intfc0_n_201), .\not_strict_mode.app_rd_data_reg[18] (mem_intfc0_n_375), .\not_strict_mode.app_rd_data_reg[190] (mem_intfc0_n_197), .\not_strict_mode.app_rd_data_reg[191] (mem_intfc0_n_193), .\not_strict_mode.app_rd_data_reg[192] (mem_intfc0_n_192), .\not_strict_mode.app_rd_data_reg[193] (mem_intfc0_n_188), .\not_strict_mode.app_rd_data_reg[194] (mem_intfc0_n_184), .\not_strict_mode.app_rd_data_reg[195] (mem_intfc0_n_180), .\not_strict_mode.app_rd_data_reg[196] (mem_intfc0_n_176), .\not_strict_mode.app_rd_data_reg[197] (mem_intfc0_n_172), .\not_strict_mode.app_rd_data_reg[198] (mem_intfc0_n_168), .\not_strict_mode.app_rd_data_reg[199] (mem_intfc0_n_164), .\not_strict_mode.app_rd_data_reg[19] (mem_intfc0_n_371), .\not_strict_mode.app_rd_data_reg[1] (mem_intfc0_n_380), .\not_strict_mode.app_rd_data_reg[200] (mem_intfc0_n_190), .\not_strict_mode.app_rd_data_reg[201] (mem_intfc0_n_186), .\not_strict_mode.app_rd_data_reg[202] (mem_intfc0_n_182), .\not_strict_mode.app_rd_data_reg[203] (mem_intfc0_n_178), .\not_strict_mode.app_rd_data_reg[204] (mem_intfc0_n_174), .\not_strict_mode.app_rd_data_reg[205] (mem_intfc0_n_170), .\not_strict_mode.app_rd_data_reg[206] (mem_intfc0_n_166), .\not_strict_mode.app_rd_data_reg[207] (mem_intfc0_n_162), .\not_strict_mode.app_rd_data_reg[208] (mem_intfc0_n_191), .\not_strict_mode.app_rd_data_reg[209] (mem_intfc0_n_187), .\not_strict_mode.app_rd_data_reg[20] (mem_intfc0_n_367), .\not_strict_mode.app_rd_data_reg[210] (mem_intfc0_n_183), .\not_strict_mode.app_rd_data_reg[211] (mem_intfc0_n_179), .\not_strict_mode.app_rd_data_reg[212] (mem_intfc0_n_175), .\not_strict_mode.app_rd_data_reg[213] (mem_intfc0_n_171), .\not_strict_mode.app_rd_data_reg[214] (mem_intfc0_n_167), .\not_strict_mode.app_rd_data_reg[215] (mem_intfc0_n_163), .\not_strict_mode.app_rd_data_reg[216] (mem_intfc0_n_189), .\not_strict_mode.app_rd_data_reg[217] (mem_intfc0_n_185), .\not_strict_mode.app_rd_data_reg[218] (mem_intfc0_n_181), .\not_strict_mode.app_rd_data_reg[219] (mem_intfc0_n_177), .\not_strict_mode.app_rd_data_reg[21] (mem_intfc0_n_363), .\not_strict_mode.app_rd_data_reg[220] (mem_intfc0_n_173), .\not_strict_mode.app_rd_data_reg[221] (mem_intfc0_n_169), .\not_strict_mode.app_rd_data_reg[222] (mem_intfc0_n_165), .\not_strict_mode.app_rd_data_reg[223] (mem_intfc0_n_161), .\not_strict_mode.app_rd_data_reg[224] (mem_intfc0_n_160), .\not_strict_mode.app_rd_data_reg[225] (mem_intfc0_n_156), .\not_strict_mode.app_rd_data_reg[226] (mem_intfc0_n_152), .\not_strict_mode.app_rd_data_reg[227] (mem_intfc0_n_148), .\not_strict_mode.app_rd_data_reg[228] (mem_intfc0_n_144), .\not_strict_mode.app_rd_data_reg[229] (mem_intfc0_n_140), .\not_strict_mode.app_rd_data_reg[22] (mem_intfc0_n_359), .\not_strict_mode.app_rd_data_reg[230] (mem_intfc0_n_136), .\not_strict_mode.app_rd_data_reg[231] (mem_intfc0_n_132), .\not_strict_mode.app_rd_data_reg[232] (mem_intfc0_n_158), .\not_strict_mode.app_rd_data_reg[233] (mem_intfc0_n_154), .\not_strict_mode.app_rd_data_reg[234] (mem_intfc0_n_150), .\not_strict_mode.app_rd_data_reg[235] (mem_intfc0_n_146), .\not_strict_mode.app_rd_data_reg[236] (mem_intfc0_n_142), .\not_strict_mode.app_rd_data_reg[237] (mem_intfc0_n_138), .\not_strict_mode.app_rd_data_reg[238] (mem_intfc0_n_134), .\not_strict_mode.app_rd_data_reg[239] (mem_intfc0_n_130), .\not_strict_mode.app_rd_data_reg[23] (mem_intfc0_n_355), .\not_strict_mode.app_rd_data_reg[240] (mem_intfc0_n_159), .\not_strict_mode.app_rd_data_reg[241] (mem_intfc0_n_155), .\not_strict_mode.app_rd_data_reg[242] (mem_intfc0_n_151), .\not_strict_mode.app_rd_data_reg[243] (mem_intfc0_n_147), .\not_strict_mode.app_rd_data_reg[244] (mem_intfc0_n_143), .\not_strict_mode.app_rd_data_reg[245] (mem_intfc0_n_139), .\not_strict_mode.app_rd_data_reg[246] (mem_intfc0_n_135), .\not_strict_mode.app_rd_data_reg[247] (mem_intfc0_n_131), .\not_strict_mode.app_rd_data_reg[248] (mem_intfc0_n_157), .\not_strict_mode.app_rd_data_reg[249] (mem_intfc0_n_153), .\not_strict_mode.app_rd_data_reg[24] (mem_intfc0_n_381), .\not_strict_mode.app_rd_data_reg[250] (mem_intfc0_n_149), .\not_strict_mode.app_rd_data_reg[251] (mem_intfc0_n_145), .\not_strict_mode.app_rd_data_reg[252] (mem_intfc0_n_141), .\not_strict_mode.app_rd_data_reg[253] (mem_intfc0_n_137), .\not_strict_mode.app_rd_data_reg[254] (mem_intfc0_n_133), .\not_strict_mode.app_rd_data_reg[255] (mem_intfc0_n_129), .\not_strict_mode.app_rd_data_reg[255]_0 (app_rd_data_ns), .\not_strict_mode.app_rd_data_reg[25] (mem_intfc0_n_377), .\not_strict_mode.app_rd_data_reg[26] (mem_intfc0_n_373), .\not_strict_mode.app_rd_data_reg[27] (mem_intfc0_n_369), .\not_strict_mode.app_rd_data_reg[28] (mem_intfc0_n_365), .\not_strict_mode.app_rd_data_reg[29] (mem_intfc0_n_361), .\not_strict_mode.app_rd_data_reg[2] (mem_intfc0_n_376), .\not_strict_mode.app_rd_data_reg[30] (mem_intfc0_n_357), .\not_strict_mode.app_rd_data_reg[31] (mem_intfc0_n_353), .\not_strict_mode.app_rd_data_reg[32] (mem_intfc0_n_352), .\not_strict_mode.app_rd_data_reg[33] (mem_intfc0_n_348), .\not_strict_mode.app_rd_data_reg[34] (mem_intfc0_n_344), .\not_strict_mode.app_rd_data_reg[35] (mem_intfc0_n_340), .\not_strict_mode.app_rd_data_reg[36] (mem_intfc0_n_336), .\not_strict_mode.app_rd_data_reg[37] (mem_intfc0_n_332), .\not_strict_mode.app_rd_data_reg[38] (mem_intfc0_n_328), .\not_strict_mode.app_rd_data_reg[39] (mem_intfc0_n_324), .\not_strict_mode.app_rd_data_reg[3] (mem_intfc0_n_372), .\not_strict_mode.app_rd_data_reg[40] (mem_intfc0_n_350), .\not_strict_mode.app_rd_data_reg[41] (mem_intfc0_n_346), .\not_strict_mode.app_rd_data_reg[42] (mem_intfc0_n_342), .\not_strict_mode.app_rd_data_reg[43] (mem_intfc0_n_338), .\not_strict_mode.app_rd_data_reg[44] (mem_intfc0_n_334), .\not_strict_mode.app_rd_data_reg[45] (mem_intfc0_n_330), .\not_strict_mode.app_rd_data_reg[46] (mem_intfc0_n_326), .\not_strict_mode.app_rd_data_reg[47] (mem_intfc0_n_322), .\not_strict_mode.app_rd_data_reg[48] (mem_intfc0_n_351), .\not_strict_mode.app_rd_data_reg[49] (mem_intfc0_n_347), .\not_strict_mode.app_rd_data_reg[4] (mem_intfc0_n_368), .\not_strict_mode.app_rd_data_reg[50] (mem_intfc0_n_343), .\not_strict_mode.app_rd_data_reg[51] (mem_intfc0_n_339), .\not_strict_mode.app_rd_data_reg[52] (mem_intfc0_n_335), .\not_strict_mode.app_rd_data_reg[53] (mem_intfc0_n_331), .\not_strict_mode.app_rd_data_reg[54] (mem_intfc0_n_327), .\not_strict_mode.app_rd_data_reg[55] (mem_intfc0_n_323), .\not_strict_mode.app_rd_data_reg[56] (mem_intfc0_n_349), .\not_strict_mode.app_rd_data_reg[57] (mem_intfc0_n_345), .\not_strict_mode.app_rd_data_reg[58] (mem_intfc0_n_341), .\not_strict_mode.app_rd_data_reg[59] (mem_intfc0_n_337), .\not_strict_mode.app_rd_data_reg[5] (mem_intfc0_n_364), .\not_strict_mode.app_rd_data_reg[60] (mem_intfc0_n_333), .\not_strict_mode.app_rd_data_reg[61] (mem_intfc0_n_329), .\not_strict_mode.app_rd_data_reg[62] (mem_intfc0_n_325), .\not_strict_mode.app_rd_data_reg[63] (mem_intfc0_n_321), .\not_strict_mode.app_rd_data_reg[64] (mem_intfc0_n_320), .\not_strict_mode.app_rd_data_reg[65] (mem_intfc0_n_316), .\not_strict_mode.app_rd_data_reg[66] (mem_intfc0_n_312), .\not_strict_mode.app_rd_data_reg[67] (mem_intfc0_n_308), .\not_strict_mode.app_rd_data_reg[68] (mem_intfc0_n_304), .\not_strict_mode.app_rd_data_reg[69] (mem_intfc0_n_300), .\not_strict_mode.app_rd_data_reg[6] (mem_intfc0_n_360), .\not_strict_mode.app_rd_data_reg[70] (mem_intfc0_n_296), .\not_strict_mode.app_rd_data_reg[71] (mem_intfc0_n_292), .\not_strict_mode.app_rd_data_reg[72] (mem_intfc0_n_318), .\not_strict_mode.app_rd_data_reg[73] (mem_intfc0_n_314), .\not_strict_mode.app_rd_data_reg[74] (mem_intfc0_n_310), .\not_strict_mode.app_rd_data_reg[75] (mem_intfc0_n_306), .\not_strict_mode.app_rd_data_reg[76] (mem_intfc0_n_302), .\not_strict_mode.app_rd_data_reg[77] (mem_intfc0_n_298), .\not_strict_mode.app_rd_data_reg[78] (mem_intfc0_n_294), .\not_strict_mode.app_rd_data_reg[79] (mem_intfc0_n_290), .\not_strict_mode.app_rd_data_reg[7] (mem_intfc0_n_356), .\not_strict_mode.app_rd_data_reg[80] (mem_intfc0_n_319), .\not_strict_mode.app_rd_data_reg[81] (mem_intfc0_n_315), .\not_strict_mode.app_rd_data_reg[82] (mem_intfc0_n_311), .\not_strict_mode.app_rd_data_reg[83] (mem_intfc0_n_307), .\not_strict_mode.app_rd_data_reg[84] (mem_intfc0_n_303), .\not_strict_mode.app_rd_data_reg[85] (mem_intfc0_n_299), .\not_strict_mode.app_rd_data_reg[86] (mem_intfc0_n_295), .\not_strict_mode.app_rd_data_reg[87] (mem_intfc0_n_291), .\not_strict_mode.app_rd_data_reg[88] (mem_intfc0_n_317), .\not_strict_mode.app_rd_data_reg[89] (mem_intfc0_n_313), .\not_strict_mode.app_rd_data_reg[8] (mem_intfc0_n_382), .\not_strict_mode.app_rd_data_reg[90] (mem_intfc0_n_309), .\not_strict_mode.app_rd_data_reg[91] (mem_intfc0_n_305), .\not_strict_mode.app_rd_data_reg[92] (mem_intfc0_n_301), .\not_strict_mode.app_rd_data_reg[93] (mem_intfc0_n_297), .\not_strict_mode.app_rd_data_reg[94] (mem_intfc0_n_293), .\not_strict_mode.app_rd_data_reg[95] (mem_intfc0_n_289), .\not_strict_mode.app_rd_data_reg[96] (mem_intfc0_n_288), .\not_strict_mode.app_rd_data_reg[97] (mem_intfc0_n_284), .\not_strict_mode.app_rd_data_reg[98] (mem_intfc0_n_280), .\not_strict_mode.app_rd_data_reg[99] (mem_intfc0_n_276), .\not_strict_mode.app_rd_data_reg[9] (mem_intfc0_n_378), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (data_buf_addr), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\ui_rd_data0/p_123_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\ui_rd_data0/p_124_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\ui_rd_data0/p_125_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\ui_rd_data0/p_116_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\ui_rd_data0/p_26_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\ui_rd_data0/p_21_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\ui_rd_data0/p_22_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\ui_rd_data0/p_23_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\ui_rd_data0/p_18_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\ui_rd_data0/p_19_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\ui_rd_data0/p_20_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\ui_rd_data0/p_15_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\ui_rd_data0/p_16_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\ui_rd_data0/p_17_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\ui_rd_data0/p_111_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\ui_rd_data0/p_12_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\ui_rd_data0/p_13_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\ui_rd_data0/p_14_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\ui_rd_data0/p_9_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\ui_rd_data0/p_10_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\ui_rd_data0/p_11_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\ui_rd_data0/p_6_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\ui_rd_data0/p_7_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\ui_rd_data0/p_8_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\ui_rd_data0/p_3_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\ui_rd_data0/p_112_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\ui_rd_data0/p_4_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\ui_rd_data0/p_5_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ({u_ui_top_n_260,u_ui_top_n_261}), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\ui_rd_data0/p_1_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\ui_rd_data0/p_113_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\ui_rd_data0/p_108_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\ui_rd_data0/p_109_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\ui_rd_data0/p_110_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\ui_rd_data0/p_105_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\ui_rd_data0/p_106_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\ui_rd_data0/p_107_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\ui_rd_data0/p_120_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\ui_rd_data0/p_102_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\ui_rd_data0/p_103_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\ui_rd_data0/p_104_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\ui_rd_data0/p_99_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\ui_rd_data0/p_100_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\ui_rd_data0/p_101_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\ui_rd_data0/p_96_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\ui_rd_data0/p_97_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\ui_rd_data0/p_98_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\ui_rd_data0/p_93_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\ui_rd_data0/p_121_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\ui_rd_data0/p_94_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\ui_rd_data0/p_95_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\ui_rd_data0/p_90_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\ui_rd_data0/p_91_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\ui_rd_data0/p_92_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\ui_rd_data0/p_87_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\ui_rd_data0/p_88_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\ui_rd_data0/p_89_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\ui_rd_data0/p_84_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\ui_rd_data0/p_85_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\ui_rd_data0/p_122_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\ui_rd_data0/p_86_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\ui_rd_data0/p_81_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\ui_rd_data0/p_82_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\ui_rd_data0/p_83_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\ui_rd_data0/p_78_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\ui_rd_data0/p_79_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\ui_rd_data0/p_80_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\ui_rd_data0/p_75_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\ui_rd_data0/p_76_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\ui_rd_data0/p_77_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\ui_rd_data0/p_117_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\ui_rd_data0/p_72_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\ui_rd_data0/p_73_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\ui_rd_data0/p_74_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\ui_rd_data0/p_69_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\ui_rd_data0/p_70_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\ui_rd_data0/p_71_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\ui_rd_data0/p_66_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\ui_rd_data0/p_67_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\ui_rd_data0/p_68_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\ui_rd_data0/p_63_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\ui_rd_data0/p_118_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\ui_rd_data0/p_64_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\ui_rd_data0/p_65_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\ui_rd_data0/p_60_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\ui_rd_data0/p_61_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\ui_rd_data0/p_62_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\ui_rd_data0/p_57_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\ui_rd_data0/p_58_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\ui_rd_data0/p_59_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\ui_rd_data0/p_54_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\ui_rd_data0/p_55_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\ui_rd_data0/p_119_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\ui_rd_data0/p_56_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\ui_rd_data0/p_51_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\ui_rd_data0/p_52_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\ui_rd_data0/p_53_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\ui_rd_data0/p_48_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\ui_rd_data0/p_49_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\ui_rd_data0/p_50_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\ui_rd_data0/p_45_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\ui_rd_data0/p_46_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\ui_rd_data0/p_47_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\ui_rd_data0/p_114_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\ui_rd_data0/p_42_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\ui_rd_data0/p_43_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\ui_rd_data0/p_44_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\ui_rd_data0/p_39_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\ui_rd_data0/p_40_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\ui_rd_data0/p_41_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\ui_rd_data0/p_36_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\ui_rd_data0/p_37_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\ui_rd_data0/p_38_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\ui_rd_data0/p_33_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\ui_rd_data0/p_115_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\ui_rd_data0/p_34_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\ui_rd_data0/p_35_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\ui_rd_data0/p_30_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\ui_rd_data0/p_31_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\ui_rd_data0/p_32_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\ui_rd_data0/p_27_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\ui_rd_data0/p_28_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\ui_rd_data0/p_29_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\ui_rd_data0/p_24_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\ui_rd_data0/p_25_out ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\ui_rd_data0/rd_status ), .p_28_out(\mc0/bank_mach0/p_28_out ), .p_67_out(\mc0/bank_mach0/p_67_out ), .p_81_in(p_81_in), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .phy_dout(phy_dout), .pi_cnt_dec_reg(pi_cnt_dec_reg), .pi_en_stg2_f_timing_reg(pi_cnt_dec), .\pi_rst_stg1_cal_r_reg[0] (\pi_rst_stg1_cal_r_reg[0] ), .pll_locked(pll_locked), .po_cnt_dec_reg(po_cnt_dec_reg), .poc_sample_pd(poc_sample_pd), .pointer_we(\ui_wr_data0/pointer_we ), .psdone(psdone), .\qcntr_r_reg[0] (E), .ram_init_done_r(ram_init_done_r), .\rd_buf_indx.rd_buf_indx_r_reg[4] ({u_ui_top_n_1,ram_init_addr}), .rd_buf_we(\ui_rd_data0/rd_buf_we ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[0] (\rd_ptr_timing_reg[0] ), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\req_bank_r_lcl_reg[0] (u_ui_top_n_274), .\req_bank_r_lcl_reg[0]_0 (u_ui_top_n_272), .\resume_wait_r_reg[5] (\resume_wait_r_reg[5] ), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0), .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0), .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1), .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .rtp_timer_ns1(rtp_timer_ns1), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg), .\samps_r_reg[9] (sm_r), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .use_addr(use_addr), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (Q), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_0 ), .\write_buffer.wr_buf_out_data_reg[287] (wr_data_addr)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) reset_reg (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r1_reg_rep__25), .Q(reset_reg_n_0), .R(1'b0)); ddr3_ifmig_7series_v4_0_axi_mc u_axi_mc (.CLK(CLK), .D(\axi_mc_w_channel_0/next_wdf_mask ), .E(\ui_cmd0/app_addr_r10 ), .Q(app_rd_data), .\app_addr_r1_reg[27] (app_addr), .app_en_ns1(\ui_cmd0/app_en_ns1 ), .app_en_r1(\ui_cmd0/app_en_r1 ), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .app_wdf_rdy(app_wdf_rdy), .aresetn(aresetn), .mc_app_cmd(app_cmd), .mc_app_wdf_data_reg(\axi_mc_w_channel_0/mc_app_wdf_data_reg ), .\mc_app_wdf_data_reg_reg[255] (\axi_mc_w_channel_0/next_wdf_data ), .mc_app_wdf_mask_reg(\axi_mc_w_channel_0/mc_app_wdf_mask_reg ), .mc_app_wdf_wren_reg(\axi_mc_w_channel_0/mc_app_wdf_wren_reg ), .mc_init_complete(init_calib_complete_r), .out(out), .reset_reg(reset_reg_n_0), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .w_cmd_rdy(w_cmd_rdy)); ddr3_ifmig_7series_v4_0_ui_top u_ui_top (.CLK(CLK), .D(\axi_mc_w_channel_0/next_wdf_mask ), .DIA({mem_intfc0_n_364,mem_intfc0_n_368}), .DIB({mem_intfc0_n_372,mem_intfc0_n_376}), .DIC({mem_intfc0_n_380,mem_intfc0_n_384}), .DOA(\ui_rd_data0/p_129_out ), .DOB(\ui_rd_data0/p_128_out ), .DOC(\ui_rd_data0/p_127_out ), .E(wr_data_en), .Q({u_ui_top_n_1,ram_init_addr}), .accept_ns(accept_ns), .app_en_ns1(\ui_cmd0/app_en_ns1 ), .app_en_r1(\ui_cmd0/app_en_r1 ), .app_hi_pri_r2(\ui_cmd0/app_hi_pri_r2 ), .app_rd_data_end_ns(\ui_rd_data0/app_rd_data_end_ns ), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .app_rdy_r_reg(\ui_cmd0/app_addr_r10 ), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .app_wdf_rdy(app_wdf_rdy), .\axaddr_incr_reg[29] (app_addr), .bypass__0(\ui_rd_data0/bypass__0 ), .cmd(cmd), .\cmd_pipe_plus.wr_data_addr_reg[3] (wr_data_addr), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ({mem_intfc0_n_353,mem_intfc0_n_357}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ({mem_intfc0_n_292,mem_intfc0_n_296}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ({mem_intfc0_n_290,mem_intfc0_n_294}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ({mem_intfc0_n_291,mem_intfc0_n_295}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ({mem_intfc0_n_260,mem_intfc0_n_264}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ({mem_intfc0_n_258,mem_intfc0_n_262}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ({mem_intfc0_n_259,mem_intfc0_n_263}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ({mem_intfc0_n_228,mem_intfc0_n_232}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ({mem_intfc0_n_226,mem_intfc0_n_230}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ({mem_intfc0_n_227,mem_intfc0_n_231}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ({mem_intfc0_n_196,mem_intfc0_n_200}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ({mem_intfc0_n_194,mem_intfc0_n_198}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ({mem_intfc0_n_195,mem_intfc0_n_199}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ({mem_intfc0_n_164,mem_intfc0_n_168}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ({mem_intfc0_n_162,mem_intfc0_n_166}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ({mem_intfc0_n_163,mem_intfc0_n_167}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ({mem_intfc0_n_132,mem_intfc0_n_136}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ({mem_intfc0_n_130,mem_intfc0_n_134}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ({mem_intfc0_n_131,mem_intfc0_n_135}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ({mem_intfc0_n_361,mem_intfc0_n_365}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ({mem_intfc0_n_329,mem_intfc0_n_333}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ({mem_intfc0_n_297,mem_intfc0_n_301}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ({mem_intfc0_n_265,mem_intfc0_n_269}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ({mem_intfc0_n_321,mem_intfc0_n_325}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ({mem_intfc0_n_233,mem_intfc0_n_237}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ({mem_intfc0_n_201,mem_intfc0_n_205}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ({mem_intfc0_n_169,mem_intfc0_n_173}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ({mem_intfc0_n_137,mem_intfc0_n_141}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ({mem_intfc0_n_362,mem_intfc0_n_366}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ({mem_intfc0_n_363,mem_intfc0_n_367}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ({mem_intfc0_n_332,mem_intfc0_n_336}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ({mem_intfc0_n_330,mem_intfc0_n_334}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ({mem_intfc0_n_331,mem_intfc0_n_335}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ({mem_intfc0_n_300,mem_intfc0_n_304}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ({mem_intfc0_n_298,mem_intfc0_n_302}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ({mem_intfc0_n_299,mem_intfc0_n_303}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ({mem_intfc0_n_268,mem_intfc0_n_272}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ({mem_intfc0_n_266,mem_intfc0_n_270}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ({mem_intfc0_n_267,mem_intfc0_n_271}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ({mem_intfc0_n_236,mem_intfc0_n_240}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ({mem_intfc0_n_234,mem_intfc0_n_238}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ({mem_intfc0_n_235,mem_intfc0_n_239}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ({mem_intfc0_n_204,mem_intfc0_n_208}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ({mem_intfc0_n_202,mem_intfc0_n_206}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ({mem_intfc0_n_203,mem_intfc0_n_207}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ({mem_intfc0_n_289,mem_intfc0_n_293}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ({mem_intfc0_n_172,mem_intfc0_n_176}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ({mem_intfc0_n_170,mem_intfc0_n_174}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ({mem_intfc0_n_171,mem_intfc0_n_175}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ({mem_intfc0_n_140,mem_intfc0_n_144}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ({mem_intfc0_n_138,mem_intfc0_n_142}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ({mem_intfc0_n_139,mem_intfc0_n_143}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ({mem_intfc0_n_369,mem_intfc0_n_373}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ({mem_intfc0_n_337,mem_intfc0_n_341}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ({mem_intfc0_n_305,mem_intfc0_n_309}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ({mem_intfc0_n_273,mem_intfc0_n_277}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ({mem_intfc0_n_241,mem_intfc0_n_245}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ({mem_intfc0_n_209,mem_intfc0_n_213}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ({mem_intfc0_n_177,mem_intfc0_n_181}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ({mem_intfc0_n_145,mem_intfc0_n_149}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ({mem_intfc0_n_257,mem_intfc0_n_261}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ({mem_intfc0_n_370,mem_intfc0_n_374}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ({mem_intfc0_n_371,mem_intfc0_n_375}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ({mem_intfc0_n_340,mem_intfc0_n_344}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ({mem_intfc0_n_338,mem_intfc0_n_342}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ({mem_intfc0_n_339,mem_intfc0_n_343}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ({mem_intfc0_n_308,mem_intfc0_n_312}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ({mem_intfc0_n_306,mem_intfc0_n_310}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ({mem_intfc0_n_307,mem_intfc0_n_311}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ({mem_intfc0_n_276,mem_intfc0_n_280}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ({mem_intfc0_n_274,mem_intfc0_n_278}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ({mem_intfc0_n_275,mem_intfc0_n_279}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ({mem_intfc0_n_244,mem_intfc0_n_248}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ({mem_intfc0_n_242,mem_intfc0_n_246}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ({mem_intfc0_n_243,mem_intfc0_n_247}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ({mem_intfc0_n_212,mem_intfc0_n_216}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ({mem_intfc0_n_210,mem_intfc0_n_214}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ({mem_intfc0_n_211,mem_intfc0_n_215}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ({mem_intfc0_n_180,mem_intfc0_n_184}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ({mem_intfc0_n_178,mem_intfc0_n_182}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ({mem_intfc0_n_179,mem_intfc0_n_183}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ({mem_intfc0_n_148,mem_intfc0_n_152}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ({mem_intfc0_n_146,mem_intfc0_n_150}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ({mem_intfc0_n_147,mem_intfc0_n_151}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ({mem_intfc0_n_377,mem_intfc0_n_381}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ({mem_intfc0_n_345,mem_intfc0_n_349}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ({mem_intfc0_n_225,mem_intfc0_n_229}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ({mem_intfc0_n_313,mem_intfc0_n_317}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ({mem_intfc0_n_281,mem_intfc0_n_285}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ({mem_intfc0_n_249,mem_intfc0_n_253}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ({mem_intfc0_n_217,mem_intfc0_n_221}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ({mem_intfc0_n_185,mem_intfc0_n_189}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ({mem_intfc0_n_153,mem_intfc0_n_157}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ({mem_intfc0_n_378,mem_intfc0_n_382}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ({mem_intfc0_n_379,mem_intfc0_n_383}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ({mem_intfc0_n_348,mem_intfc0_n_352}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ({mem_intfc0_n_346,mem_intfc0_n_350}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ({mem_intfc0_n_347,mem_intfc0_n_351}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ({mem_intfc0_n_316,mem_intfc0_n_320}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ({mem_intfc0_n_314,mem_intfc0_n_318}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ({mem_intfc0_n_315,mem_intfc0_n_319}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ({mem_intfc0_n_284,mem_intfc0_n_288}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ({mem_intfc0_n_282,mem_intfc0_n_286}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ({mem_intfc0_n_283,mem_intfc0_n_287}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ({mem_intfc0_n_193,mem_intfc0_n_197}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ({mem_intfc0_n_252,mem_intfc0_n_256}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ({mem_intfc0_n_250,mem_intfc0_n_254}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ({mem_intfc0_n_251,mem_intfc0_n_255}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ({mem_intfc0_n_220,mem_intfc0_n_224}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ({mem_intfc0_n_218,mem_intfc0_n_222}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ({mem_intfc0_n_219,mem_intfc0_n_223}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ({mem_intfc0_n_188,mem_intfc0_n_192}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ({mem_intfc0_n_186,mem_intfc0_n_190}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ({mem_intfc0_n_187,mem_intfc0_n_191}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ({mem_intfc0_n_156,mem_intfc0_n_160}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ({mem_intfc0_n_154,mem_intfc0_n_158}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ({mem_intfc0_n_155,mem_intfc0_n_159}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ({mem_intfc0_n_161,mem_intfc0_n_165}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ({mem_intfc0_n_129,mem_intfc0_n_133}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (app_rd_data_ns), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ({mem_intfc0_n_356,mem_intfc0_n_360}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ({mem_intfc0_n_354,mem_intfc0_n_358}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ({mem_intfc0_n_355,mem_intfc0_n_359}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ({mem_intfc0_n_324,mem_intfc0_n_328}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ({mem_intfc0_n_322,mem_intfc0_n_326}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ({mem_intfc0_n_323,mem_intfc0_n_327}), .hi_priority(hi_priority), .idle_ns(\mc0/bank_mach0/idle_ns ), .mc_app_cmd(app_cmd), .mc_app_wdf_data_reg(\axi_mc_w_channel_0/mc_app_wdf_data_reg ), .mc_app_wdf_mask_reg(\axi_mc_w_channel_0/mc_app_wdf_mask_reg ), .mc_app_wdf_wren_reg(\axi_mc_w_channel_0/mc_app_wdf_wren_reg ), .\my_empty_reg[7] ({wr_data_mask,wr_data}), .\not_strict_mode.app_rd_data_end_reg (\ui_rd_data0/rd_status ), .\not_strict_mode.app_rd_data_reg[101] (\ui_rd_data0/p_80_out ), .\not_strict_mode.app_rd_data_reg[103] (\ui_rd_data0/p_75_out ), .\not_strict_mode.app_rd_data_reg[105] (\ui_rd_data0/p_76_out ), .\not_strict_mode.app_rd_data_reg[107] (\ui_rd_data0/p_77_out ), .\not_strict_mode.app_rd_data_reg[109] (\ui_rd_data0/p_72_out ), .\not_strict_mode.app_rd_data_reg[111] (\ui_rd_data0/p_73_out ), .\not_strict_mode.app_rd_data_reg[113] (\ui_rd_data0/p_74_out ), .\not_strict_mode.app_rd_data_reg[115] (\ui_rd_data0/p_69_out ), .\not_strict_mode.app_rd_data_reg[117] (\ui_rd_data0/p_70_out ), .\not_strict_mode.app_rd_data_reg[119] (\ui_rd_data0/p_71_out ), .\not_strict_mode.app_rd_data_reg[11] (\ui_rd_data0/p_125_out ), .\not_strict_mode.app_rd_data_reg[121] (\ui_rd_data0/p_66_out ), .\not_strict_mode.app_rd_data_reg[123] (\ui_rd_data0/p_67_out ), .\not_strict_mode.app_rd_data_reg[125] (\ui_rd_data0/p_68_out ), .\not_strict_mode.app_rd_data_reg[127] (\ui_rd_data0/p_63_out ), .\not_strict_mode.app_rd_data_reg[129] (\ui_rd_data0/p_64_out ), .\not_strict_mode.app_rd_data_reg[131] (\ui_rd_data0/p_65_out ), .\not_strict_mode.app_rd_data_reg[133] (\ui_rd_data0/p_60_out ), .\not_strict_mode.app_rd_data_reg[135] (\ui_rd_data0/p_61_out ), .\not_strict_mode.app_rd_data_reg[137] (\ui_rd_data0/p_62_out ), .\not_strict_mode.app_rd_data_reg[139] (\ui_rd_data0/p_57_out ), .\not_strict_mode.app_rd_data_reg[13] (\ui_rd_data0/p_120_out ), .\not_strict_mode.app_rd_data_reg[141] (\ui_rd_data0/p_58_out ), .\not_strict_mode.app_rd_data_reg[143] (\ui_rd_data0/p_59_out ), .\not_strict_mode.app_rd_data_reg[145] (\ui_rd_data0/p_54_out ), .\not_strict_mode.app_rd_data_reg[147] (\ui_rd_data0/p_55_out ), .\not_strict_mode.app_rd_data_reg[149] (\ui_rd_data0/p_56_out ), .\not_strict_mode.app_rd_data_reg[151] (\ui_rd_data0/p_51_out ), .\not_strict_mode.app_rd_data_reg[153] (\ui_rd_data0/p_52_out ), .\not_strict_mode.app_rd_data_reg[155] (\ui_rd_data0/p_53_out ), .\not_strict_mode.app_rd_data_reg[157] (\ui_rd_data0/p_48_out ), .\not_strict_mode.app_rd_data_reg[159] (\ui_rd_data0/p_49_out ), .\not_strict_mode.app_rd_data_reg[15] (\ui_rd_data0/p_121_out ), .\not_strict_mode.app_rd_data_reg[161] (\ui_rd_data0/p_50_out ), .\not_strict_mode.app_rd_data_reg[163] (\ui_rd_data0/p_45_out ), .\not_strict_mode.app_rd_data_reg[165] (\ui_rd_data0/p_46_out ), .\not_strict_mode.app_rd_data_reg[167] (\ui_rd_data0/p_47_out ), .\not_strict_mode.app_rd_data_reg[169] (\ui_rd_data0/p_42_out ), .\not_strict_mode.app_rd_data_reg[171] (\ui_rd_data0/p_43_out ), .\not_strict_mode.app_rd_data_reg[173] (\ui_rd_data0/p_44_out ), .\not_strict_mode.app_rd_data_reg[175] (\ui_rd_data0/p_39_out ), .\not_strict_mode.app_rd_data_reg[177] (\ui_rd_data0/p_40_out ), .\not_strict_mode.app_rd_data_reg[179] (\ui_rd_data0/p_41_out ), .\not_strict_mode.app_rd_data_reg[17] (\ui_rd_data0/p_122_out ), .\not_strict_mode.app_rd_data_reg[181] (\ui_rd_data0/p_36_out ), .\not_strict_mode.app_rd_data_reg[183] (\ui_rd_data0/p_37_out ), .\not_strict_mode.app_rd_data_reg[185] (\ui_rd_data0/p_38_out ), .\not_strict_mode.app_rd_data_reg[187] (\ui_rd_data0/p_33_out ), .\not_strict_mode.app_rd_data_reg[189] (\ui_rd_data0/p_34_out ), .\not_strict_mode.app_rd_data_reg[191] (\ui_rd_data0/p_35_out ), .\not_strict_mode.app_rd_data_reg[193] (\ui_rd_data0/p_30_out ), .\not_strict_mode.app_rd_data_reg[195] (\ui_rd_data0/p_31_out ), .\not_strict_mode.app_rd_data_reg[197] (\ui_rd_data0/p_32_out ), .\not_strict_mode.app_rd_data_reg[199] (\ui_rd_data0/p_27_out ), .\not_strict_mode.app_rd_data_reg[19] (\ui_rd_data0/p_117_out ), .\not_strict_mode.app_rd_data_reg[201] (\ui_rd_data0/p_28_out ), .\not_strict_mode.app_rd_data_reg[203] (\ui_rd_data0/p_29_out ), .\not_strict_mode.app_rd_data_reg[205] (\ui_rd_data0/p_24_out ), .\not_strict_mode.app_rd_data_reg[207] (\ui_rd_data0/p_25_out ), .\not_strict_mode.app_rd_data_reg[209] (\ui_rd_data0/p_26_out ), .\not_strict_mode.app_rd_data_reg[211] (\ui_rd_data0/p_21_out ), .\not_strict_mode.app_rd_data_reg[213] (\ui_rd_data0/p_22_out ), .\not_strict_mode.app_rd_data_reg[215] (\ui_rd_data0/p_23_out ), .\not_strict_mode.app_rd_data_reg[217] (\ui_rd_data0/p_18_out ), .\not_strict_mode.app_rd_data_reg[219] (\ui_rd_data0/p_19_out ), .\not_strict_mode.app_rd_data_reg[21] (\ui_rd_data0/p_118_out ), .\not_strict_mode.app_rd_data_reg[221] (\ui_rd_data0/p_20_out ), .\not_strict_mode.app_rd_data_reg[223] (\ui_rd_data0/p_15_out ), .\not_strict_mode.app_rd_data_reg[225] (\ui_rd_data0/p_16_out ), .\not_strict_mode.app_rd_data_reg[227] (\ui_rd_data0/p_17_out ), .\not_strict_mode.app_rd_data_reg[229] (\ui_rd_data0/p_12_out ), .\not_strict_mode.app_rd_data_reg[231] (\ui_rd_data0/p_13_out ), .\not_strict_mode.app_rd_data_reg[233] (\ui_rd_data0/p_14_out ), .\not_strict_mode.app_rd_data_reg[235] (\ui_rd_data0/p_9_out ), .\not_strict_mode.app_rd_data_reg[237] (\ui_rd_data0/p_10_out ), .\not_strict_mode.app_rd_data_reg[239] (\ui_rd_data0/p_11_out ), .\not_strict_mode.app_rd_data_reg[23] (\ui_rd_data0/p_119_out ), .\not_strict_mode.app_rd_data_reg[241] (\ui_rd_data0/p_6_out ), .\not_strict_mode.app_rd_data_reg[243] (\ui_rd_data0/p_7_out ), .\not_strict_mode.app_rd_data_reg[245] (\ui_rd_data0/p_8_out ), .\not_strict_mode.app_rd_data_reg[247] (\ui_rd_data0/p_3_out ), .\not_strict_mode.app_rd_data_reg[249] (\ui_rd_data0/p_4_out ), .\not_strict_mode.app_rd_data_reg[251] (\ui_rd_data0/p_5_out ), .\not_strict_mode.app_rd_data_reg[253] ({u_ui_top_n_260,u_ui_top_n_261}), .\not_strict_mode.app_rd_data_reg[255] (\ui_rd_data0/p_1_out ), .\not_strict_mode.app_rd_data_reg[25] (\ui_rd_data0/p_114_out ), .\not_strict_mode.app_rd_data_reg[27] (\ui_rd_data0/p_115_out ), .\not_strict_mode.app_rd_data_reg[29] (\ui_rd_data0/p_116_out ), .\not_strict_mode.app_rd_data_reg[31] (\ui_rd_data0/p_111_out ), .\not_strict_mode.app_rd_data_reg[33] (\ui_rd_data0/p_112_out ), .\not_strict_mode.app_rd_data_reg[35] (\ui_rd_data0/p_113_out ), .\not_strict_mode.app_rd_data_reg[37] (\ui_rd_data0/p_108_out ), .\not_strict_mode.app_rd_data_reg[39] (\ui_rd_data0/p_109_out ), .\not_strict_mode.app_rd_data_reg[41] (\ui_rd_data0/p_110_out ), .\not_strict_mode.app_rd_data_reg[43] (\ui_rd_data0/p_105_out ), .\not_strict_mode.app_rd_data_reg[45] (\ui_rd_data0/p_106_out ), .\not_strict_mode.app_rd_data_reg[47] (\ui_rd_data0/p_107_out ), .\not_strict_mode.app_rd_data_reg[49] (\ui_rd_data0/p_102_out ), .\not_strict_mode.app_rd_data_reg[51] (\ui_rd_data0/p_103_out ), .\not_strict_mode.app_rd_data_reg[53] (\ui_rd_data0/p_104_out ), .\not_strict_mode.app_rd_data_reg[55] (\ui_rd_data0/p_99_out ), .\not_strict_mode.app_rd_data_reg[57] (\ui_rd_data0/p_100_out ), .\not_strict_mode.app_rd_data_reg[59] (\ui_rd_data0/p_101_out ), .\not_strict_mode.app_rd_data_reg[61] (\ui_rd_data0/p_96_out ), .\not_strict_mode.app_rd_data_reg[63] (\ui_rd_data0/p_97_out ), .\not_strict_mode.app_rd_data_reg[65] (\ui_rd_data0/p_98_out ), .\not_strict_mode.app_rd_data_reg[67] (\ui_rd_data0/p_93_out ), .\not_strict_mode.app_rd_data_reg[69] (\ui_rd_data0/p_94_out ), .\not_strict_mode.app_rd_data_reg[71] (\ui_rd_data0/p_95_out ), .\not_strict_mode.app_rd_data_reg[73] (\ui_rd_data0/p_90_out ), .\not_strict_mode.app_rd_data_reg[75] (\ui_rd_data0/p_91_out ), .\not_strict_mode.app_rd_data_reg[77] (\ui_rd_data0/p_92_out ), .\not_strict_mode.app_rd_data_reg[79] (\ui_rd_data0/p_87_out ), .\not_strict_mode.app_rd_data_reg[7] (\ui_rd_data0/p_123_out ), .\not_strict_mode.app_rd_data_reg[81] (\ui_rd_data0/p_88_out ), .\not_strict_mode.app_rd_data_reg[83] (\ui_rd_data0/p_89_out ), .\not_strict_mode.app_rd_data_reg[85] (\ui_rd_data0/p_84_out ), .\not_strict_mode.app_rd_data_reg[87] (\ui_rd_data0/p_85_out ), .\not_strict_mode.app_rd_data_reg[89] (\ui_rd_data0/p_86_out ), .\not_strict_mode.app_rd_data_reg[91] (\ui_rd_data0/p_81_out ), .\not_strict_mode.app_rd_data_reg[93] (\ui_rd_data0/p_82_out ), .\not_strict_mode.app_rd_data_reg[95] (\ui_rd_data0/p_83_out ), .\not_strict_mode.app_rd_data_reg[97] (\ui_rd_data0/p_78_out ), .\not_strict_mode.app_rd_data_reg[99] (\ui_rd_data0/p_79_out ), .\not_strict_mode.app_rd_data_reg[9] (\ui_rd_data0/p_124_out ), .p_28_out(\mc0/bank_mach0/p_28_out ), .p_67_out(\mc0/bank_mach0/p_67_out ), .pointer_we(\ui_wr_data0/pointer_we ), .ram_init_done_r(ram_init_done_r), .rb_hit_busy_r_reg(u_ui_top_n_272), .rb_hit_busy_r_reg_0(u_ui_top_n_274), .rd_buf_we(\ui_rd_data0/rd_buf_we ), .\read_fifo.fifo_out_data_r_reg[7] ({rd_data_end,rd_data_addr,rd_data_offset}), .\req_bank_r_lcl_reg[2] (bank), .\req_bank_r_lcl_reg[2]_0 (\mc0/p_2_in ), .\req_bank_r_lcl_reg[2]_1 (\mc0/req_bank_r_lcl ), .\req_col_r_reg[9] (col), .\req_data_buf_addr_r_reg[4] (data_buf_addr), .\req_row_r_lcl_reg[14] (row), .reset_reg(reset_reg_n_0), .\s_axi_rdata[255] (app_rd_data), .use_addr(use_addr), .w_cmd_rdy(w_cmd_rdy), .wready_reg_rep__1(\axi_mc_w_channel_0/next_wdf_data )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_edge_store" *) module ddr3_ifmig_7series_v4_0_poc_edge_store (Q, \rise_trail_center_offset_r_reg[3] , E, \tap_r_reg[5] , CLK, run_polarity_r_reg, D); output [5:0]Q; output [5:0]\rise_trail_center_offset_r_reg[3] ; input [0:0]E; input [5:0]\tap_r_reg[5] ; input CLK; input [0:0]run_polarity_r_reg; input [5:0]D; wire CLK; wire [5:0]D; wire [0:0]E; wire [5:0]Q; wire [5:0]\rise_trail_center_offset_r_reg[3] ; wire [0:0]run_polarity_r_reg; wire [5:0]\tap_r_reg[5] ; FDRE #( .INIT(1'b0)) \rise_lead_r_reg[0] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[1] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[2] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[3] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[4] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[5] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [5]), .Q(Q[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[0] (.C(CLK), .CE(run_polarity_r_reg), .D(D[0]), .Q(\rise_trail_center_offset_r_reg[3] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[1] (.C(CLK), .CE(run_polarity_r_reg), .D(D[1]), .Q(\rise_trail_center_offset_r_reg[3] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[2] (.C(CLK), .CE(run_polarity_r_reg), .D(D[2]), .Q(\rise_trail_center_offset_r_reg[3] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[3] (.C(CLK), .CE(run_polarity_r_reg), .D(D[3]), .Q(\rise_trail_center_offset_r_reg[3] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[4] (.C(CLK), .CE(run_polarity_r_reg), .D(D[4]), .Q(\rise_trail_center_offset_r_reg[3] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[5] (.C(CLK), .CE(run_polarity_r_reg), .D(D[5]), .Q(\rise_trail_center_offset_r_reg[3] [5]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_edge_store" *) module ddr3_ifmig_7series_v4_0_poc_edge_store_7 (DI, \center_diff_r_reg[5] , \window_center_r_reg[6] , \window_center_r_reg[6]_0 , S, D, \center_diff_r_reg[0] , \center_diff_r_reg[0]_0 , \center_diff_r_reg[0]_1 , \center_diff_r_reg[5]_0 , \center_diff_r_reg[1] , \window_center_r_reg[6]_1 , \window_center_r_reg[3] , \window_center_r_reg[0] , \window_center_r_reg[6]_2 , \center_diff_r_reg[3] , \center_diff_r_reg[3]_0 , Q, center0_return3, use_noise_window, \rise_trail_r_reg[5]_0 , \rise_lead_r_reg[5]_0 , O, \rise_trail_r_reg[3]_0 , \rise_lead_r_reg[0]_0 , \rise_lead_r_reg[4]_0 , \rise_trail_r_reg[4]_0 , \rise_trail_r_reg[1]_0 , \rise_trail_r_reg[2]_0 , E, \tap_r_reg[5] , CLK, samps_zero_r_reg, \tap_r_reg[4] ); output [1:0]DI; output [0:0]\center_diff_r_reg[5] ; output [5:0]\window_center_r_reg[6] ; output [5:0]\window_center_r_reg[6]_0 ; output [0:0]S; output [2:0]D; output \center_diff_r_reg[0] ; output \center_diff_r_reg[0]_0 ; output \center_diff_r_reg[0]_1 ; output [0:0]\center_diff_r_reg[5]_0 ; output \center_diff_r_reg[1] ; output [0:0]\window_center_r_reg[6]_1 ; output [2:0]\window_center_r_reg[3] ; output [2:0]\window_center_r_reg[0] ; output [1:0]\window_center_r_reg[6]_2 ; output [0:0]\center_diff_r_reg[3] ; output [0:0]\center_diff_r_reg[3]_0 ; input [1:0]Q; input [3:0]center0_return3; input use_noise_window; input [3:0]\rise_trail_r_reg[5]_0 ; input [3:0]\rise_lead_r_reg[5]_0 ; input [0:0]O; input \rise_trail_r_reg[3]_0 ; input \rise_lead_r_reg[0]_0 ; input [1:0]\rise_lead_r_reg[4]_0 ; input [1:0]\rise_trail_r_reg[4]_0 ; input \rise_trail_r_reg[1]_0 ; input \rise_trail_r_reg[2]_0 ; input [0:0]E; input [5:0]\tap_r_reg[5] ; input CLK; input [0:0]samps_zero_r_reg; input [5:0]\tap_r_reg[4] ; wire CLK; wire [2:0]D; wire [1:0]DI; wire [0:0]E; wire [0:0]O; wire [1:0]Q; wire [0:0]S; wire [3:0]center0_return3; wire \center_diff_r[5]_i_11_n_0 ; wire \center_diff_r[5]_i_6_n_0 ; wire \center_diff_r[5]_i_8_n_0 ; wire \center_diff_r[5]_i_9_n_0 ; wire \center_diff_r_reg[0] ; wire \center_diff_r_reg[0]_0 ; wire \center_diff_r_reg[0]_1 ; wire \center_diff_r_reg[1] ; wire [0:0]\center_diff_r_reg[3] ; wire [0:0]\center_diff_r_reg[3]_0 ; wire [0:0]\center_diff_r_reg[5] ; wire [0:0]\center_diff_r_reg[5]_0 ; wire mod_sub1_return0_carry__0_i_3_n_0; wire \rise_lead_r_reg[0]_0 ; wire [1:0]\rise_lead_r_reg[4]_0 ; wire [3:0]\rise_lead_r_reg[5]_0 ; wire \rise_trail_r_reg[1]_0 ; wire \rise_trail_r_reg[2]_0 ; wire \rise_trail_r_reg[3]_0 ; wire [1:0]\rise_trail_r_reg[4]_0 ; wire [3:0]\rise_trail_r_reg[5]_0 ; wire [0:0]samps_zero_r_reg; wire [5:0]\tap_r_reg[4] ; wire [5:0]\tap_r_reg[5] ; wire use_noise_window; wire [2:0]\window_center_r_reg[0] ; wire [2:0]\window_center_r_reg[3] ; wire [5:0]\window_center_r_reg[6] ; wire [5:0]\window_center_r_reg[6]_0 ; wire [0:0]\window_center_r_reg[6]_1 ; wire [1:0]\window_center_r_reg[6]_2 ; LUT5 #( .INIT(32'hAAAA8000)) center0_return1__0_carry__0_i_1 (.I0(Q[0]), .I1(center0_return3[2]), .I2(center0_return3[1]), .I3(center0_return3[0]), .I4(center0_return3[3]), .O(DI[1])); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry__0_i_2 (.I0(\window_center_r_reg[6] [3]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [3]), .O(DI[0])); LUT6 #( .INIT(64'h5F5F3FC0A0A03FC0)) center0_return1__0_carry__0_i_3 (.I0(\window_center_r_reg[6] [4]), .I1(\window_center_r_reg[6]_0 [4]), .I2(Q[1]), .I3(\window_center_r_reg[6]_0 [5]), .I4(use_noise_window), .I5(\window_center_r_reg[6] [5]), .O(S)); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry_i_1 (.I0(\window_center_r_reg[6] [2]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [2]), .O(\window_center_r_reg[3] [2])); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry_i_2 (.I0(\window_center_r_reg[6] [1]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [1]), .O(\window_center_r_reg[3] [1])); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry_i_3 (.I0(\window_center_r_reg[6] [0]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [0]), .O(\window_center_r_reg[3] [0])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry__0_i_1 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .O(\window_center_r_reg[6]_2 [1])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry__0_i_2 (.I0(\window_center_r_reg[6] [3]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [3]), .O(\window_center_r_reg[6]_2 [0])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry__0_i_3 (.I0(\window_center_r_reg[6] [5]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [5]), .O(\window_center_r_reg[6]_1 )); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry_i_1 (.I0(\window_center_r_reg[6] [2]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [2]), .O(\window_center_r_reg[0] [2])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry_i_2 (.I0(\window_center_r_reg[6] [1]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [1]), .O(\window_center_r_reg[0] [1])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry_i_3 (.I0(\window_center_r_reg[6] [0]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [0]), .O(\window_center_r_reg[0] [0])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[0]_i_1 (.I0(O), .I1(\center_diff_r_reg[0] ), .I2(\center_diff_r_reg[0]_0 ), .I3(\rise_trail_r_reg[3]_0 ), .I4(\center_diff_r_reg[0]_1 ), .I5(\rise_lead_r_reg[0]_0 ), .O(D[0])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[4]_i_1 (.I0(\rise_lead_r_reg[4]_0 [0]), .I1(\center_diff_r_reg[0] ), .I2(\center_diff_r_reg[0]_0 ), .I3(\rise_trail_r_reg[3]_0 ), .I4(\center_diff_r_reg[0]_1 ), .I5(\rise_trail_r_reg[4]_0 [0]), .O(D[1])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[5]_i_1 (.I0(\rise_lead_r_reg[4]_0 [1]), .I1(\center_diff_r_reg[0] ), .I2(\center_diff_r_reg[0]_0 ), .I3(\rise_trail_r_reg[3]_0 ), .I4(\center_diff_r_reg[0]_1 ), .I5(\rise_trail_r_reg[4]_0 [1]), .O(D[2])); LUT5 #( .INIT(32'h335ACC5A)) \center_diff_r[5]_i_11 (.I0(\window_center_r_reg[6]_0 [3]), .I1(\window_center_r_reg[6] [3]), .I2(\rise_lead_r_reg[5]_0 [1]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [1]), .O(\center_diff_r[5]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair439" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_12 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .O(\center_diff_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair438" *) LUT5 #( .INIT(32'hCCAFFFAF)) \center_diff_r[5]_i_2 (.I0(\window_center_r_reg[6]_0 [5]), .I1(\window_center_r_reg[6] [5]), .I2(\rise_lead_r_reg[5]_0 [3]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [3]), .O(\center_diff_r_reg[0] )); LUT6 #( .INIT(64'hFFFFFFFFB200FFB2)) \center_diff_r[5]_i_3 (.I0(\center_diff_r[5]_i_6_n_0 ), .I1(\rise_trail_r_reg[1]_0 ), .I2(\center_diff_r[5]_i_8_n_0 ), .I3(\center_diff_r[5]_i_9_n_0 ), .I4(\rise_trail_r_reg[2]_0 ), .I5(\center_diff_r[5]_i_11_n_0 ), .O(\center_diff_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000FF77CF47)) \center_diff_r[5]_i_5 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .I3(\rise_trail_r_reg[5]_0 [2]), .I4(\rise_lead_r_reg[5]_0 [2]), .I5(mod_sub1_return0_carry__0_i_3_n_0), .O(\center_diff_r_reg[0]_1 )); LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_6 (.I0(\window_center_r_reg[6] [1]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [1]), .O(\center_diff_r[5]_i_6_n_0 )); LUT5 #( .INIT(32'h000ACC0A)) \center_diff_r[5]_i_8 (.I0(\window_center_r_reg[6]_0 [0]), .I1(\window_center_r_reg[6] [0]), .I2(\rise_lead_r_reg[5]_0 [0]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [0]), .O(\center_diff_r[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair439" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_9 (.I0(\window_center_r_reg[6] [2]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [2]), .O(\center_diff_r[5]_i_9_n_0 )); LUT5 #( .INIT(32'h478B74B8)) mod_sub1_return0_carry__0_i_1 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .I3(\rise_trail_r_reg[5]_0 [2]), .I4(\rise_lead_r_reg[5]_0 [2]), .O(\center_diff_r_reg[5] )); LUT6 #( .INIT(64'h555595955A559A95)) mod_sub1_return0_carry__0_i_2 (.I0(mod_sub1_return0_carry__0_i_3_n_0), .I1(\window_center_r_reg[6] [4]), .I2(use_noise_window), .I3(\window_center_r_reg[6]_0 [4]), .I4(\rise_trail_r_reg[5]_0 [2]), .I5(\rise_lead_r_reg[5]_0 [2]), .O(\center_diff_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair438" *) LUT5 #( .INIT(32'h335ACC5A)) mod_sub1_return0_carry__0_i_3 (.I0(\window_center_r_reg[6]_0 [5]), .I1(\window_center_r_reg[6] [5]), .I2(\rise_lead_r_reg[5]_0 [3]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [3]), .O(mod_sub1_return0_carry__0_i_3_n_0)); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_1 (.I0(\window_center_r_reg[6] [3]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [3]), .O(\center_diff_r_reg[3]_0 )); LUT5 #( .INIT(32'h335ACC5A)) mod_sub1_return0_carry_i_5 (.I0(\window_center_r_reg[6]_0 [3]), .I1(\window_center_r_reg[6] [3]), .I2(\rise_lead_r_reg[5]_0 [1]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [1]), .O(\center_diff_r_reg[3] )); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[0] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [0]), .Q(\window_center_r_reg[6] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[1] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [1]), .Q(\window_center_r_reg[6] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[2] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [2]), .Q(\window_center_r_reg[6] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[3] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [3]), .Q(\window_center_r_reg[6] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[4] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [4]), .Q(\window_center_r_reg[6] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[5] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [5]), .Q(\window_center_r_reg[6] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[0] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [0]), .Q(\window_center_r_reg[6]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[1] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [1]), .Q(\window_center_r_reg[6]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[2] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [2]), .Q(\window_center_r_reg[6]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[3] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [3]), .Q(\window_center_r_reg[6]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[4] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [4]), .Q(\window_center_r_reg[6]_0 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[5] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [5]), .Q(\window_center_r_reg[6]_0 [5]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_edge_store" *) module ddr3_ifmig_7series_v4_0_poc_edge_store_8 (trailing_edge00_in, D, \center_diff_r_reg[1] , \mmcm_init_trail_reg[5] , \mmcm_init_lead_reg[5] , \center_diff_r_reg[5] , \center_diff_r_reg[3] , \center_diff_r_reg[0] , \center_diff_r_reg[0]_0 , \center_diff_r_reg[3]_0 , \center_diff_r_reg[5]_0 , Q, \tap_r_reg[5] , S, DI, \tap_r_reg[5]_0 , O, \rise_trail_r_reg[5]_0 , \rise_lead_r_reg[1]_0 , \rise_lead_r_reg[4]_0 , \rise_trail_r_reg[3]_0 , \rise_lead_r_reg[3]_0 , use_noise_window, \rise_lead_r_reg[4]_1 , \rise_lead_r_reg[5]_0 , \rise_trail_r_reg[5]_1 , E, CLK, samps_zero_r_reg, \tap_r_reg[4] ); output [4:0]trailing_edge00_in; output [2:0]D; output \center_diff_r_reg[1] ; output [5:0]\mmcm_init_trail_reg[5] ; output [5:0]\mmcm_init_lead_reg[5] ; output [0:0]\center_diff_r_reg[5] ; output [3:0]\center_diff_r_reg[3] ; output \center_diff_r_reg[0] ; output \center_diff_r_reg[0]_0 ; output [2:0]\center_diff_r_reg[3]_0 ; output [0:0]\center_diff_r_reg[5]_0 ; input [0:0]Q; input [5:0]\tap_r_reg[5] ; input [3:0]S; input [0:0]DI; input [1:0]\tap_r_reg[5]_0 ; input [2:0]O; input \rise_trail_r_reg[5]_0 ; input \rise_lead_r_reg[1]_0 ; input \rise_lead_r_reg[4]_0 ; input [2:0]\rise_trail_r_reg[3]_0 ; input [0:0]\rise_lead_r_reg[3]_0 ; input use_noise_window; input \rise_lead_r_reg[4]_1 ; input [0:0]\rise_lead_r_reg[5]_0 ; input [0:0]\rise_trail_r_reg[5]_1 ; input [0:0]E; input CLK; input [0:0]samps_zero_r_reg; input [5:0]\tap_r_reg[4] ; wire CLK; wire [2:0]D; wire [0:0]DI; wire [0:0]E; wire [2:0]O; wire [0:0]Q; wire [3:0]S; wire \center_diff_r[5]_i_13_n_0 ; wire \center_diff_r_reg[0] ; wire \center_diff_r_reg[0]_0 ; wire \center_diff_r_reg[1] ; wire [3:0]\center_diff_r_reg[3] ; wire [2:0]\center_diff_r_reg[3]_0 ; wire [0:0]\center_diff_r_reg[5] ; wire [0:0]\center_diff_r_reg[5]_0 ; wire [5:0]\mmcm_init_lead_reg[5] ; wire [5:0]\mmcm_init_trail_reg[5] ; wire \rise_lead_r_reg[1]_0 ; wire [0:0]\rise_lead_r_reg[3]_0 ; wire \rise_lead_r_reg[4]_0 ; wire \rise_lead_r_reg[4]_1 ; wire [0:0]\rise_lead_r_reg[5]_0 ; wire [2:0]\rise_trail_r_reg[3]_0 ; wire \rise_trail_r_reg[5]_0 ; wire [0:0]\rise_trail_r_reg[5]_1 ; wire [0:0]samps_zero_r_reg; wire [5:0]\tap_r_reg[4] ; wire [5:0]\tap_r_reg[5] ; wire [1:0]\tap_r_reg[5]_0 ; wire [4:0]trailing_edge00_in; wire \trailing_edge0_inferred__0/i__carry__0_n_3 ; wire \trailing_edge0_inferred__0/i__carry_n_0 ; wire \trailing_edge0_inferred__0/i__carry_n_1 ; wire \trailing_edge0_inferred__0/i__carry_n_2 ; wire \trailing_edge0_inferred__0/i__carry_n_3 ; wire use_noise_window; wire [0:0]\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED ; wire [3:1]\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:2]\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED ; LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[1]_i_1 (.I0(O[0]), .I1(\rise_trail_r_reg[5]_0 ), .I2(\rise_lead_r_reg[1]_0 ), .I3(\center_diff_r_reg[1] ), .I4(\rise_lead_r_reg[4]_0 ), .I5(\rise_trail_r_reg[3]_0 [0]), .O(D[0])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[2]_i_1 (.I0(O[1]), .I1(\rise_trail_r_reg[5]_0 ), .I2(\rise_lead_r_reg[1]_0 ), .I3(\center_diff_r_reg[1] ), .I4(\rise_lead_r_reg[4]_0 ), .I5(\rise_trail_r_reg[3]_0 [1]), .O(D[1])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[3]_i_1 (.I0(O[2]), .I1(\rise_trail_r_reg[5]_0 ), .I2(\rise_lead_r_reg[1]_0 ), .I3(\center_diff_r_reg[1] ), .I4(\rise_lead_r_reg[4]_0 ), .I5(\rise_trail_r_reg[3]_0 [2]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair440" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_10 (.I0(\mmcm_init_trail_reg[5] [2]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [2]), .O(\center_diff_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair440" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_13 (.I0(\mmcm_init_trail_reg[5] [4]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [4]), .O(\center_diff_r[5]_i_13_n_0 )); LUT6 #( .INIT(64'h4540FFFF45404540)) \center_diff_r[5]_i_4 (.I0(\rise_lead_r_reg[3]_0 ), .I1(\mmcm_init_trail_reg[5] [3]), .I2(use_noise_window), .I3(\mmcm_init_lead_reg[5] [3]), .I4(\rise_lead_r_reg[4]_1 ), .I5(\center_diff_r[5]_i_13_n_0 ), .O(\center_diff_r_reg[1] )); LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_7 (.I0(\mmcm_init_trail_reg[5] [1]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [1]), .O(\center_diff_r_reg[0]_0 )); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry__0_i_1 (.I0(\mmcm_init_trail_reg[5] [4]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [4]), .O(\center_diff_r_reg[5]_0 )); LUT5 #( .INIT(32'hB8748B47)) mod_sub1_return0__0_carry__0_i_2 (.I0(\mmcm_init_trail_reg[5] [5]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [5]), .I3(\rise_lead_r_reg[5]_0 ), .I4(\rise_trail_r_reg[5]_1 ), .O(\center_diff_r_reg[5] )); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_1 (.I0(\mmcm_init_trail_reg[5] [3]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [3]), .O(\center_diff_r_reg[3] [3])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_2 (.I0(\mmcm_init_trail_reg[5] [2]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [2]), .O(\center_diff_r_reg[3] [2])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_3 (.I0(\mmcm_init_trail_reg[5] [1]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [1]), .O(\center_diff_r_reg[3] [1])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_4 (.I0(\mmcm_init_trail_reg[5] [0]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [0]), .O(\center_diff_r_reg[3] [0])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_2 (.I0(\mmcm_init_trail_reg[5] [2]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [2]), .O(\center_diff_r_reg[3]_0 [2])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_3 (.I0(\mmcm_init_trail_reg[5] [1]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [1]), .O(\center_diff_r_reg[3]_0 [1])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_4 (.I0(\mmcm_init_trail_reg[5] [0]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [0]), .O(\center_diff_r_reg[3]_0 [0])); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[0] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [0]), .Q(\mmcm_init_lead_reg[5] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[1] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [1]), .Q(\mmcm_init_lead_reg[5] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[2] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [2]), .Q(\mmcm_init_lead_reg[5] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[3] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [3]), .Q(\mmcm_init_lead_reg[5] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[4] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [4]), .Q(\mmcm_init_lead_reg[5] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_r_reg[5] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [5]), .Q(\mmcm_init_lead_reg[5] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[0] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [0]), .Q(\mmcm_init_trail_reg[5] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[1] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [1]), .Q(\mmcm_init_trail_reg[5] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[2] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [2]), .Q(\mmcm_init_trail_reg[5] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[3] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [3]), .Q(\mmcm_init_trail_reg[5] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[4] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [4]), .Q(\mmcm_init_trail_reg[5] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_r_reg[5] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [5]), .Q(\mmcm_init_trail_reg[5] [5]), .R(1'b0)); CARRY4 \trailing_edge0_inferred__0/i__carry (.CI(1'b0), .CO({\trailing_edge0_inferred__0/i__carry_n_0 ,\trailing_edge0_inferred__0/i__carry_n_1 ,\trailing_edge0_inferred__0/i__carry_n_2 ,\trailing_edge0_inferred__0/i__carry_n_3 }), .CYINIT(1'b1), .DI({Q,\tap_r_reg[5] [2:0]}), .O({trailing_edge00_in[2:0],\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED [0]}), .S(S)); CARRY4 \trailing_edge0_inferred__0/i__carry__0 (.CI(\trailing_edge0_inferred__0/i__carry_n_0 ), .CO({\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],\trailing_edge0_inferred__0/i__carry__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,DI}), .O({\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED [3:2],trailing_edge00_in[4:3]}), .S({1'b0,1'b0,\tap_r_reg[5]_0 })); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_meta" *) module ddr3_ifmig_7series_v4_0_poc_meta (detect_done_r_reg, \sm_r_reg[1] , poc_backup_r_reg_0, run_polarity_held_r, Q, center_return3, \edge_diff_r_reg[0]_0 , center0_return3, O, \center_diff_r_reg[5]_0 , \center_diff_r_reg[3]_0 , \center_diff_r_reg[5]_1 , \diff_r_reg[7]_0 , \diff_r_reg[7]_1 , \edge_center_r_reg[6]_0 , \prev_r_reg[0]_0 , \prev_r_reg[0]_1 , \prev_r_reg[2]_0 , \window_center_r_reg[6]_0 , CLK, samps_zero_r_reg, samps_zero_r_reg_0, S, \rise_lead_center_offset_r_reg[4]_0 , \rise_lead_center_offset_r_reg[2]_0 , DI, \edge_diff_r_reg[4]_0 , \rise_trail_center_offset_r_reg[2]_0 , \rise_lead_center_offset_r_reg[4]_1 , \rise_trail_center_offset_r_reg[3]_0 , \rise_trail_center_offset_r_reg[5]_0 , \rise_lead_r_reg[2] , \rise_trail_r_reg[2] , \rise_lead_r_reg[4] , \rise_lead_r_reg[5] , \rise_lead_r_reg[2]_0 , \rise_trail_r_reg[2]_0 , \center_diff_r_reg[4]_0 , \rise_lead_r_reg[4]_0 , \rise_lead_r_reg[3] , \rise_trail_r_reg[3] , \rise_lead_r_reg[4]_1 , \rise_lead_r_reg[4]_2 , \rise_trail_r_reg[3]_0 , \rise_lead_r_reg[3]_0 , \rise_trail_r_reg[4] , \rise_trail_r_reg[5] , \edge_center_r_reg[6]_1 , \window_center_r_reg[6]_1 , \edge_center_r_reg[3]_0 , \edge_center_r_reg[5]_0 , \window_center_r_reg[6]_2 , \edge_center_r_reg[0]_0 , \edge_center_r_reg[3]_1 , \edge_center_r_reg[6]_2 , ocd_ktap_right_r_reg, ocd_ktap_left_r_reg, \run_ends_r_reg[1]_0 , rstdiv0_sync_r1_reg_rep__20, ocd_ktap_left_r_reg_0, ocd_edge_detect_rdy_r_reg, \diff_r_reg[2]_0 , run_too_small_r_reg, D, \rise_lead_r_reg[3]_1 , \rise_trail_r_reg[3]_1 , \rise_trail_center_offset_r_reg[0]_0 ); output detect_done_r_reg; output \sm_r_reg[1] ; output poc_backup_r_reg_0; output run_polarity_held_r; output [5:0]Q; output [3:0]center_return3; output [5:0]\edge_diff_r_reg[0]_0 ; output [3:0]center0_return3; output [3:0]O; output [1:0]\center_diff_r_reg[5]_0 ; output [2:0]\center_diff_r_reg[3]_0 ; output [1:0]\center_diff_r_reg[5]_1 ; output [6:0]\diff_r_reg[7]_0 ; output [6:0]\diff_r_reg[7]_1 ; output [4:0]\edge_center_r_reg[6]_0 ; output \prev_r_reg[0]_0 ; output \prev_r_reg[0]_1 ; output [2:0]\prev_r_reg[2]_0 ; output [4:0]\window_center_r_reg[6]_0 ; input CLK; input samps_zero_r_reg; input samps_zero_r_reg_0; input [2:0]S; input [1:0]\rise_lead_center_offset_r_reg[4]_0 ; input [2:0]\rise_lead_center_offset_r_reg[2]_0 ; input [0:0]DI; input [1:0]\edge_diff_r_reg[4]_0 ; input [2:0]\rise_trail_center_offset_r_reg[2]_0 ; input [1:0]\rise_lead_center_offset_r_reg[4]_1 ; input [3:0]\rise_trail_center_offset_r_reg[3]_0 ; input [1:0]\rise_trail_center_offset_r_reg[5]_0 ; input [2:0]\rise_lead_r_reg[2] ; input [2:0]\rise_trail_r_reg[2] ; input [1:0]\rise_lead_r_reg[4] ; input [2:0]\rise_lead_r_reg[5] ; input [2:0]\rise_lead_r_reg[2]_0 ; input [2:0]\rise_trail_r_reg[2]_0 ; input [1:0]\center_diff_r_reg[4]_0 ; input [2:0]\rise_lead_r_reg[4]_0 ; input [3:0]\rise_lead_r_reg[3] ; input [3:0]\rise_trail_r_reg[3] ; input [0:0]\rise_lead_r_reg[4]_1 ; input [1:0]\rise_lead_r_reg[4]_2 ; input [3:0]\rise_trail_r_reg[3]_0 ; input [3:0]\rise_lead_r_reg[3]_0 ; input [0:0]\rise_trail_r_reg[4] ; input [1:0]\rise_trail_r_reg[5] ; input [3:0]\edge_center_r_reg[6]_1 ; input [3:0]\window_center_r_reg[6]_1 ; input [3:0]\edge_center_r_reg[3]_0 ; input [1:0]\edge_center_r_reg[5]_0 ; input [3:0]\window_center_r_reg[6]_2 ; input [0:0]\edge_center_r_reg[0]_0 ; input [3:0]\edge_center_r_reg[3]_1 ; input [2:0]\edge_center_r_reg[6]_2 ; input ocd_ktap_right_r_reg; input ocd_ktap_left_r_reg; input \run_ends_r_reg[1]_0 ; input rstdiv0_sync_r1_reg_rep__20; input ocd_ktap_left_r_reg_0; input ocd_edge_detect_rdy_r_reg; input \diff_r_reg[2]_0 ; input run_too_small_r_reg; input [5:0]D; input [5:0]\rise_lead_r_reg[3]_1 ; input [5:0]\rise_trail_r_reg[3]_1 ; input \rise_trail_center_offset_r_reg[0]_0 ; wire CLK; wire [5:0]D; wire [0:0]DI; wire [3:0]O; wire [5:0]Q; wire [2:0]S; wire [6:0]center0_return0; wire center0_return1__0_carry__0_n_2; wire center0_return1__0_carry__0_n_3; wire center0_return1__0_carry_i_7_n_0; wire center0_return1__0_carry_n_0; wire center0_return1__0_carry_n_1; wire center0_return1__0_carry_n_2; wire center0_return1__0_carry_n_3; wire center0_return1__1_carry__0_n_2; wire center0_return1__1_carry__0_n_3; wire center0_return1__1_carry_i_7_n_0; wire center0_return1__1_carry_n_0; wire center0_return1__1_carry_n_1; wire center0_return1__1_carry_n_2; wire center0_return1__1_carry_n_3; wire [3:0]center0_return3; wire [2:0]\center_diff_r_reg[3]_0 ; wire [1:0]\center_diff_r_reg[4]_0 ; wire [1:0]\center_diff_r_reg[5]_0 ; wire [1:0]\center_diff_r_reg[5]_1 ; wire \center_diff_r_reg_n_0_[0] ; wire [6:0]center_return0; wire center_return1__0_carry__0_i_1_n_0; wire center_return1__0_carry__0_n_2; wire center_return1__0_carry__0_n_3; wire center_return1__0_carry_i_4_n_0; wire center_return1__0_carry_n_0; wire center_return1__0_carry_n_1; wire center_return1__0_carry_n_2; wire center_return1__0_carry_n_3; wire center_return1__1_carry__0_i_1_n_0; wire center_return1__1_carry__0_n_2; wire center_return1__1_carry__0_n_3; wire center_return1__1_carry_i_4_n_0; wire center_return1__1_carry_n_0; wire center_return1__1_carry_n_1; wire center_return1__1_carry_n_2; wire center_return1__1_carry_n_3; wire [3:0]center_return3; wire detect_done_r_reg; wire [0:0]diff; wire [7:0]diff_ns; wire [7:0]diff_ns0; wire [6:1]diff_ns00_in; wire diff_ns0_carry__0_n_1; wire diff_ns0_carry__0_n_2; wire diff_ns0_carry__0_n_3; wire diff_ns0_carry_n_0; wire diff_ns0_carry_n_1; wire diff_ns0_carry_n_2; wire diff_ns0_carry_n_3; wire \diff_ns0_inferred__0/i__carry__0_n_0 ; wire \diff_ns0_inferred__0/i__carry__0_n_2 ; wire \diff_ns0_inferred__0/i__carry__0_n_3 ; wire \diff_ns0_inferred__0/i__carry_n_0 ; wire \diff_ns0_inferred__0/i__carry_n_1 ; wire \diff_ns0_inferred__0/i__carry_n_2 ; wire \diff_ns0_inferred__0/i__carry_n_3 ; wire diff_ns1; wire diff_ns1_carry_n_1; wire diff_ns1_carry_n_2; wire diff_ns1_carry_n_3; wire \diff_r_reg[2]_0 ; wire [6:0]\diff_r_reg[7]_0 ; wire [6:0]\diff_r_reg[7]_1 ; wire \diff_r_reg_n_0_[3] ; wire \diff_r_reg_n_0_[4] ; wire \diff_r_reg_n_0_[5] ; wire \diff_r_reg_n_0_[6] ; wire \diff_r_reg_n_0_[7] ; wire diffs_eq_ns; wire diffs_eq_r; wire done_ns; wire edge_aligned_ns; wire edge_aligned_r_i_2_n_0; wire edge_aligned_r_i_3_n_0; wire [0:0]\edge_center_r_reg[0]_0 ; wire [3:0]\edge_center_r_reg[3]_0 ; wire [3:0]\edge_center_r_reg[3]_1 ; wire [1:0]\edge_center_r_reg[5]_0 ; wire [4:0]\edge_center_r_reg[6]_0 ; wire [3:0]\edge_center_r_reg[6]_1 ; wire [2:0]\edge_center_r_reg[6]_2 ; wire \edge_diff_r[5]_i_2_n_0 ; wire \edge_diff_r[5]_i_3_n_0 ; wire [5:0]\edge_diff_r_reg[0]_0 ; wire [1:0]\edge_diff_r_reg[4]_0 ; wire mod_sub1_return0__0_carry__0_n_3; wire mod_sub1_return0__0_carry_n_0; wire mod_sub1_return0__0_carry_n_1; wire mod_sub1_return0__0_carry_n_2; wire mod_sub1_return0__0_carry_n_3; wire mod_sub1_return0_carry__0_n_3; wire mod_sub1_return0_carry_n_0; wire mod_sub1_return0_carry_n_1; wire mod_sub1_return0_carry_n_2; wire mod_sub1_return0_carry_n_3; wire [5:0]mod_sub_return; wire mod_sub_return0__0_carry__0_n_3; wire mod_sub_return0__0_carry__0_n_6; wire mod_sub_return0__0_carry__0_n_7; wire mod_sub_return0__0_carry_n_0; wire mod_sub_return0__0_carry_n_1; wire mod_sub_return0__0_carry_n_2; wire mod_sub_return0__0_carry_n_3; wire mod_sub_return0__0_carry_n_4; wire mod_sub_return0__0_carry_n_5; wire mod_sub_return0__0_carry_n_6; wire mod_sub_return0_carry__0_i_1_n_0; wire mod_sub_return0_carry__0_n_3; wire mod_sub_return0_carry__0_n_6; wire mod_sub_return0_carry__0_n_7; wire mod_sub_return0_carry_i_1_n_0; wire mod_sub_return0_carry_n_0; wire mod_sub_return0_carry_n_1; wire mod_sub_return0_carry_n_2; wire mod_sub_return0_carry_n_3; wire mod_sub_return0_carry_n_4; wire mod_sub_return0_carry_n_5; wire mod_sub_return0_carry_n_6; wire mod_sub_return0_carry_n_7; wire ocd_edge_detect_rdy_r_reg; wire ocd_ktap_left_r_reg; wire ocd_ktap_left_r_reg_0; wire ocd_ktap_right_r_reg; wire poc_backup_ns; wire poc_backup_ns0; wire poc_backup_ns0_carry_i_10_n_0; wire poc_backup_ns0_carry_i_11_n_0; wire poc_backup_ns0_carry_i_12_n_0; wire poc_backup_ns0_carry_i_13_n_0; wire poc_backup_ns0_carry_i_14_n_0; wire poc_backup_ns0_carry_i_15_n_0; wire poc_backup_ns0_carry_i_16_n_0; wire poc_backup_ns0_carry_i_1_n_0; wire poc_backup_ns0_carry_i_2_n_0; wire poc_backup_ns0_carry_i_3_n_0; wire poc_backup_ns0_carry_i_4_n_0; wire poc_backup_ns0_carry_i_5_n_0; wire poc_backup_ns0_carry_i_6_n_0; wire poc_backup_ns0_carry_i_7_n_0; wire poc_backup_ns0_carry_i_8_n_0; wire poc_backup_ns0_carry_i_9_n_0; wire poc_backup_ns0_carry_n_1; wire poc_backup_ns0_carry_n_2; wire poc_backup_ns0_carry_n_3; wire poc_backup_r_reg_0; wire [7:0]prev_r; wire \prev_r_reg[0]_0 ; wire \prev_r_reg[0]_1 ; wire [2:0]\prev_r_reg[2]_0 ; wire reset_run_ends; wire [2:0]\rise_lead_center_offset_r_reg[2]_0 ; wire [1:0]\rise_lead_center_offset_r_reg[4]_0 ; wire [1:0]\rise_lead_center_offset_r_reg[4]_1 ; wire [2:0]\rise_lead_r_reg[2] ; wire [2:0]\rise_lead_r_reg[2]_0 ; wire [3:0]\rise_lead_r_reg[3] ; wire [3:0]\rise_lead_r_reg[3]_0 ; wire [5:0]\rise_lead_r_reg[3]_1 ; wire [1:0]\rise_lead_r_reg[4] ; wire [2:0]\rise_lead_r_reg[4]_0 ; wire [0:0]\rise_lead_r_reg[4]_1 ; wire [1:0]\rise_lead_r_reg[4]_2 ; wire [2:0]\rise_lead_r_reg[5] ; wire \rise_trail_center_offset_r_reg[0]_0 ; wire [2:0]\rise_trail_center_offset_r_reg[2]_0 ; wire [3:0]\rise_trail_center_offset_r_reg[3]_0 ; wire [1:0]\rise_trail_center_offset_r_reg[5]_0 ; wire [2:0]\rise_trail_r_reg[2] ; wire [2:0]\rise_trail_r_reg[2]_0 ; wire [3:0]\rise_trail_r_reg[3] ; wire [3:0]\rise_trail_r_reg[3]_0 ; wire [5:0]\rise_trail_r_reg[3]_1 ; wire [0:0]\rise_trail_r_reg[4] ; wire [1:0]\rise_trail_r_reg[5] ; wire rstdiv0_sync_r1_reg_rep__20; wire run_end_r2_reg_srl3_n_0; wire run_end_r3; wire \run_ends_r[0]_i_1_n_0 ; wire \run_ends_r[1]_i_1_n_0 ; wire \run_ends_r_reg[1]_0 ; wire run_polarity_held_r; wire run_too_small_r10; wire run_too_small_r2_reg_srl2_n_0; wire run_too_small_r3; wire run_too_small_r_reg; wire samps_zero_r_reg; wire samps_zero_r_reg_0; wire \sm_r_reg[1] ; wire [4:0]\window_center_r_reg[6]_0 ; wire [3:0]\window_center_r_reg[6]_1 ; wire [3:0]\window_center_r_reg[6]_2 ; wire [0:0]NLW_center0_return1__0_carry_O_UNCONNECTED; wire [3:2]NLW_center0_return1__0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center0_return1__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_center0_return1__1_carry_O_UNCONNECTED; wire [2:2]NLW_center0_return1__1_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center0_return1__1_carry__0_O_UNCONNECTED; wire [0:0]NLW_center_return1__0_carry_O_UNCONNECTED; wire [3:2]NLW_center_return1__0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center_return1__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_center_return1__1_carry_O_UNCONNECTED; wire [2:2]NLW_center_return1__1_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center_return1__1_carry__0_O_UNCONNECTED; wire [3:3]NLW_diff_ns0_carry__0_CO_UNCONNECTED; wire [0:0]\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED ; wire [2:2]\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:3]\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED ; wire [3:0]NLW_diff_ns1_carry_O_UNCONNECTED; wire [0:0]NLW_mod_sub1_return0__0_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub1_return0_carry__0_O_UNCONNECTED; wire [0:0]NLW_mod_sub_return0__0_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub_return0_carry__0_O_UNCONNECTED; wire [3:0]NLW_poc_backup_ns0_carry_O_UNCONNECTED; CARRY4 center0_return1__0_carry (.CI(1'b0), .CO({center0_return1__0_carry_n_0,center0_return1__0_carry_n_1,center0_return1__0_carry_n_2,center0_return1__0_carry_n_3}), .CYINIT(1'b0), .DI({\rise_lead_r_reg[2]_0 ,1'b0}), .O({center0_return0[3:1],NLW_center0_return1__0_carry_O_UNCONNECTED[0]}), .S({\rise_trail_r_reg[2]_0 ,center0_return1__0_carry_i_7_n_0})); CARRY4 center0_return1__0_carry__0 (.CI(center0_return1__0_carry_n_0), .CO({NLW_center0_return1__0_carry__0_CO_UNCONNECTED[3:2],center0_return1__0_carry__0_n_2,center0_return1__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\center_diff_r_reg[4]_0 }), .O({NLW_center0_return1__0_carry__0_O_UNCONNECTED[3],center0_return0[6:4]}), .S({1'b0,\rise_lead_r_reg[4]_0 })); LUT1 #( .INIT(2'h2)) center0_return1__0_carry_i_7 (.I0(\center_diff_r_reg_n_0_[0] ), .O(center0_return1__0_carry_i_7_n_0)); CARRY4 center0_return1__1_carry (.CI(1'b0), .CO({center0_return1__1_carry_n_0,center0_return1__1_carry_n_1,center0_return1__1_carry_n_2,center0_return1__1_carry_n_3}), .CYINIT(1'b0), .DI({\rise_lead_r_reg[2] ,1'b0}), .O({NLW_center0_return1__1_carry_O_UNCONNECTED[3:1],center0_return0[0]}), .S({\rise_trail_r_reg[2] ,center0_return1__1_carry_i_7_n_0})); CARRY4 center0_return1__1_carry__0 (.CI(center0_return1__1_carry_n_0), .CO({center0_return3[3],NLW_center0_return1__1_carry__0_CO_UNCONNECTED[2],center0_return1__1_carry__0_n_2,center0_return1__1_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\rise_lead_r_reg[4] }), .O({NLW_center0_return1__1_carry__0_O_UNCONNECTED[3],center0_return3[2:0]}), .S({1'b1,\rise_lead_r_reg[5] })); LUT1 #( .INIT(2'h2)) center0_return1__1_carry_i_7 (.I0(\center_diff_r_reg_n_0_[0] ), .O(center0_return1__1_carry_i_7_n_0)); FDRE #( .INIT(1'b0)) \center_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\center_diff_r_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \center_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(\window_center_r_reg[6]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \center_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(\window_center_r_reg[6]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \center_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(\window_center_r_reg[6]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \center_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(\window_center_r_reg[6]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \center_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(\window_center_r_reg[6]_0 [4]), .R(1'b0)); CARRY4 center_return1__0_carry (.CI(1'b0), .CO({center_return1__0_carry_n_0,center_return1__0_carry_n_1,center_return1__0_carry_n_2,center_return1__0_carry_n_3}), .CYINIT(1'b0), .DI({Q[2:0],1'b0}), .O({center_return0[3:1],NLW_center_return1__0_carry_O_UNCONNECTED[0]}), .S({\rise_lead_center_offset_r_reg[2]_0 ,center_return1__0_carry_i_4_n_0})); CARRY4 center_return1__0_carry__0 (.CI(center_return1__0_carry_n_0), .CO({NLW_center_return1__0_carry__0_CO_UNCONNECTED[3:2],center_return1__0_carry__0_n_2,center_return1__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,DI,Q[3]}), .O({NLW_center_return1__0_carry__0_O_UNCONNECTED[3],center_return0[6:4]}), .S({1'b0,center_return1__0_carry__0_i_1_n_0,\edge_diff_r_reg[4]_0 })); LUT3 #( .INIT(8'h78)) center_return1__0_carry__0_i_1 (.I0(Q[4]), .I1(\edge_center_r_reg[6]_0 [4]), .I2(Q[5]), .O(center_return1__0_carry__0_i_1_n_0)); LUT1 #( .INIT(2'h2)) center_return1__0_carry_i_4 (.I0(diff), .O(center_return1__0_carry_i_4_n_0)); CARRY4 center_return1__1_carry (.CI(1'b0), .CO({center_return1__1_carry_n_0,center_return1__1_carry_n_1,center_return1__1_carry_n_2,center_return1__1_carry_n_3}), .CYINIT(1'b0), .DI({Q[2:0],1'b0}), .O({NLW_center_return1__1_carry_O_UNCONNECTED[3:1],center_return0[0]}), .S({S,center_return1__1_carry_i_4_n_0})); CARRY4 center_return1__1_carry__0 (.CI(center_return1__1_carry_n_0), .CO({center_return3[3],NLW_center_return1__1_carry__0_CO_UNCONNECTED[2],center_return1__1_carry__0_n_2,center_return1__1_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,Q[4:3]}), .O({NLW_center_return1__1_carry__0_O_UNCONNECTED[3],center_return3[2:0]}), .S({1'b1,center_return1__1_carry__0_i_1_n_0,\rise_lead_center_offset_r_reg[4]_0 })); LUT1 #( .INIT(2'h2)) center_return1__1_carry__0_i_1 (.I0(Q[5]), .O(center_return1__1_carry__0_i_1_n_0)); LUT1 #( .INIT(2'h2)) center_return1__1_carry_i_4 (.I0(diff), .O(center_return1__1_carry_i_4_n_0)); CARRY4 diff_ns0_carry (.CI(1'b0), .CO({diff_ns0_carry_n_0,diff_ns0_carry_n_1,diff_ns0_carry_n_2,diff_ns0_carry_n_3}), .CYINIT(1'b1), .DI(\diff_r_reg[7]_0 [3:0]), .O(diff_ns0[3:0]), .S(\edge_center_r_reg[3]_0 )); CARRY4 diff_ns0_carry__0 (.CI(diff_ns0_carry_n_0), .CO({NLW_diff_ns0_carry__0_CO_UNCONNECTED[3],diff_ns0_carry__0_n_1,diff_ns0_carry__0_n_2,diff_ns0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,\edge_center_r_reg[5]_0 ,\diff_r_reg[7]_1 [4]}), .O(diff_ns0[7:4]), .S(\window_center_r_reg[6]_2 )); CARRY4 \diff_ns0_inferred__0/i__carry (.CI(1'b0), .CO({\diff_ns0_inferred__0/i__carry_n_0 ,\diff_ns0_inferred__0/i__carry_n_1 ,\diff_ns0_inferred__0/i__carry_n_2 ,\diff_ns0_inferred__0/i__carry_n_3 }), .CYINIT(1'b1), .DI(\diff_r_reg[7]_0 [3:0]), .O({diff_ns00_in[3:1],\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED [0]}), .S(\edge_center_r_reg[3]_1 )); CARRY4 \diff_ns0_inferred__0/i__carry__0 (.CI(\diff_ns0_inferred__0/i__carry_n_0 ), .CO({\diff_ns0_inferred__0/i__carry__0_n_0 ,\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED [2],\diff_ns0_inferred__0/i__carry__0_n_2 ,\diff_ns0_inferred__0/i__carry__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,\diff_r_reg[7]_0 [6:4]}), .O({\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED [3],diff_ns00_in[6:4]}), .S({1'b1,\edge_center_r_reg[6]_2 })); CARRY4 diff_ns1_carry (.CI(1'b0), .CO({diff_ns1,diff_ns1_carry_n_1,diff_ns1_carry_n_2,diff_ns1_carry_n_3}), .CYINIT(1'b1), .DI(\edge_center_r_reg[6]_1 ), .O(NLW_diff_ns1_carry_O_UNCONNECTED[3:0]), .S(\window_center_r_reg[6]_1 )); (* SOFT_HLUTNM = "soft_lutpair444" *) LUT3 #( .INIT(8'hAC)) \diff_r[0]_i_1 (.I0(\edge_center_r_reg[0]_0 ), .I1(diff_ns0[0]), .I2(diff_ns1), .O(diff_ns[0])); (* SOFT_HLUTNM = "soft_lutpair445" *) LUT3 #( .INIT(8'hAC)) \diff_r[1]_i_1 (.I0(diff_ns00_in[1]), .I1(diff_ns0[1]), .I2(diff_ns1), .O(diff_ns[1])); (* SOFT_HLUTNM = "soft_lutpair443" *) LUT3 #( .INIT(8'hAC)) \diff_r[2]_i_1 (.I0(diff_ns00_in[2]), .I1(diff_ns0[2]), .I2(diff_ns1), .O(diff_ns[2])); (* SOFT_HLUTNM = "soft_lutpair446" *) LUT3 #( .INIT(8'hAC)) \diff_r[3]_i_1 (.I0(diff_ns00_in[3]), .I1(diff_ns0[3]), .I2(diff_ns1), .O(diff_ns[3])); (* SOFT_HLUTNM = "soft_lutpair446" *) LUT3 #( .INIT(8'hAC)) \diff_r[4]_i_1 (.I0(diff_ns00_in[4]), .I1(diff_ns0[4]), .I2(diff_ns1), .O(diff_ns[4])); (* SOFT_HLUTNM = "soft_lutpair443" *) LUT3 #( .INIT(8'hAC)) \diff_r[5]_i_1 (.I0(diff_ns00_in[5]), .I1(diff_ns0[5]), .I2(diff_ns1), .O(diff_ns[5])); (* SOFT_HLUTNM = "soft_lutpair445" *) LUT3 #( .INIT(8'hAC)) \diff_r[6]_i_1 (.I0(diff_ns00_in[6]), .I1(diff_ns0[6]), .I2(diff_ns1), .O(diff_ns[6])); (* SOFT_HLUTNM = "soft_lutpair444" *) LUT3 #( .INIT(8'h5C)) \diff_r[7]_i_1 (.I0(\diff_ns0_inferred__0/i__carry__0_n_0 ), .I1(diff_ns0[7]), .I2(diff_ns1), .O(diff_ns[7])); FDRE #( .INIT(1'b0)) \diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(diff_ns[0]), .Q(\prev_r_reg[2]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(diff_ns[1]), .Q(\prev_r_reg[2]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(diff_ns[2]), .Q(\prev_r_reg[2]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(diff_ns[3]), .Q(\diff_r_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(diff_ns[4]), .Q(\diff_r_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(diff_ns[5]), .Q(\diff_r_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[6] (.C(CLK), .CE(1'b1), .D(diff_ns[6]), .Q(\diff_r_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \diff_r_reg[7] (.C(CLK), .CE(1'b1), .D(diff_ns[7]), .Q(\diff_r_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h000000000000BF80)) diffs_eq_r_i_1 (.I0(edge_aligned_r_i_2_n_0), .I1(done_ns), .I2(detect_done_r_reg), .I3(diffs_eq_r), .I4(ocd_ktap_right_r_reg), .I5(ocd_ktap_left_r_reg), .O(diffs_eq_ns)); FDRE #( .INIT(1'b0)) diffs_eq_r_reg (.C(CLK), .CE(1'b1), .D(diffs_eq_ns), .Q(diffs_eq_r), .R(1'b0)); LUT3 #( .INIT(8'h80)) done_r_i_1 (.I0(ocd_edge_detect_rdy_r_reg), .I1(\prev_r_reg[0]_0 ), .I2(\prev_r_reg[0]_1 ), .O(done_ns)); FDRE #( .INIT(1'b0)) done_r_reg (.C(CLK), .CE(1'b1), .D(done_ns), .Q(detect_done_r_reg), .R(1'b0)); LUT6 #( .INIT(64'h000000F400000000)) edge_aligned_r_i_1 (.I0(edge_aligned_r_i_2_n_0), .I1(diffs_eq_r), .I2(edge_aligned_r_i_3_n_0), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_left_r_reg_0), .I5(done_ns), .O(edge_aligned_ns)); LUT6 #( .INIT(64'h4000000055551555)) edge_aligned_r_i_2 (.I0(\diff_r_reg_n_0_[6] ), .I1(\diff_r_reg_n_0_[5] ), .I2(\diff_r_reg_n_0_[4] ), .I3(\diff_r_reg_n_0_[3] ), .I4(\diff_r_reg[2]_0 ), .I5(\diff_r_reg_n_0_[7] ), .O(edge_aligned_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000004)) edge_aligned_r_i_3 (.I0(\diff_r_reg_n_0_[3] ), .I1(\diff_r_reg[2]_0 ), .I2(\diff_r_reg_n_0_[4] ), .I3(\diff_r_reg_n_0_[5] ), .I4(\diff_r_reg_n_0_[6] ), .I5(\diff_r_reg_n_0_[7] ), .O(edge_aligned_r_i_3_n_0)); FDRE #( .INIT(1'b0)) edge_aligned_r_reg (.C(CLK), .CE(1'b1), .D(edge_aligned_ns), .Q(\sm_r_reg[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[0] (.C(CLK), .CE(1'b1), .D(center_return0[0]), .Q(\diff_r_reg[7]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[1] (.C(CLK), .CE(1'b1), .D(center_return0[1]), .Q(\diff_r_reg[7]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[2] (.C(CLK), .CE(1'b1), .D(center_return0[2]), .Q(\diff_r_reg[7]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[3] (.C(CLK), .CE(1'b1), .D(center_return0[3]), .Q(\diff_r_reg[7]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[4] (.C(CLK), .CE(1'b1), .D(center_return0[4]), .Q(\diff_r_reg[7]_0 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[5] (.C(CLK), .CE(1'b1), .D(center_return0[5]), .Q(\diff_r_reg[7]_0 [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_center_r_reg[6] (.C(CLK), .CE(1'b1), .D(center_return0[6]), .Q(\diff_r_reg[7]_0 [6]), .R(1'b0)); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[0]_i_1 (.I0(\rise_trail_center_offset_r_reg[0]_0 ), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_7), .O(mod_sub_return[0])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[1]_i_1 (.I0(mod_sub_return0__0_carry_n_6), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_6), .O(mod_sub_return[1])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[2]_i_1 (.I0(mod_sub_return0__0_carry_n_5), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_5), .O(mod_sub_return[2])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[3]_i_1 (.I0(mod_sub_return0__0_carry_n_4), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_4), .O(mod_sub_return[3])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[4]_i_1 (.I0(mod_sub_return0__0_carry__0_n_7), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry__0_n_7), .O(mod_sub_return[4])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[5]_i_1 (.I0(mod_sub_return0__0_carry__0_n_6), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry__0_n_6), .O(mod_sub_return[5])); LUT5 #( .INIT(32'hB2FF00B2)) \edge_diff_r[5]_i_2 (.I0(\edge_diff_r[5]_i_3_n_0 ), .I1(Q[3]), .I2(\edge_diff_r_reg[0]_0 [3]), .I3(Q[4]), .I4(\edge_diff_r_reg[0]_0 [4]), .O(\edge_diff_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'hDF0DFFFF0000DF0D)) \edge_diff_r[5]_i_3 (.I0(Q[0]), .I1(\edge_diff_r_reg[0]_0 [0]), .I2(Q[1]), .I3(\edge_diff_r_reg[0]_0 [1]), .I4(Q[2]), .I5(\edge_diff_r_reg[0]_0 [2]), .O(\edge_diff_r[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \edge_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(mod_sub_return[0]), .Q(diff), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(mod_sub_return[1]), .Q(\edge_center_r_reg[6]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(mod_sub_return[2]), .Q(\edge_center_r_reg[6]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(mod_sub_return[3]), .Q(\edge_center_r_reg[6]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(mod_sub_return[4]), .Q(\edge_center_r_reg[6]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \edge_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(mod_sub_return[5]), .Q(\edge_center_r_reg[6]_0 [4]), .R(1'b0)); CARRY4 mod_sub1_return0__0_carry (.CI(1'b0), .CO({mod_sub1_return0__0_carry_n_0,mod_sub1_return0__0_carry_n_1,mod_sub1_return0__0_carry_n_2,mod_sub1_return0__0_carry_n_3}), .CYINIT(1'b1), .DI(\rise_trail_r_reg[3]_0 ), .O({\center_diff_r_reg[3]_0 ,NLW_mod_sub1_return0__0_carry_O_UNCONNECTED[0]}), .S(\rise_lead_r_reg[3]_0 )); CARRY4 mod_sub1_return0__0_carry__0 (.CI(mod_sub1_return0__0_carry_n_0), .CO({NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\rise_trail_r_reg[4] }), .O({NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED[3:2],\center_diff_r_reg[5]_1 }), .S({1'b0,1'b0,\rise_trail_r_reg[5] })); CARRY4 mod_sub1_return0_carry (.CI(1'b0), .CO({mod_sub1_return0_carry_n_0,mod_sub1_return0_carry_n_1,mod_sub1_return0_carry_n_2,mod_sub1_return0_carry_n_3}), .CYINIT(1'b1), .DI(\rise_lead_r_reg[3] ), .O(O), .S(\rise_trail_r_reg[3] )); CARRY4 mod_sub1_return0_carry__0 (.CI(mod_sub1_return0_carry_n_0), .CO({NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\rise_lead_r_reg[4]_1 }), .O({NLW_mod_sub1_return0_carry__0_O_UNCONNECTED[3:2],\center_diff_r_reg[5]_0 }), .S({1'b0,1'b0,\rise_lead_r_reg[4]_2 })); CARRY4 mod_sub_return0__0_carry (.CI(1'b0), .CO({mod_sub_return0__0_carry_n_0,mod_sub_return0__0_carry_n_1,mod_sub_return0__0_carry_n_2,mod_sub_return0__0_carry_n_3}), .CYINIT(1'b1), .DI(\edge_diff_r_reg[0]_0 [3:0]), .O({mod_sub_return0__0_carry_n_4,mod_sub_return0__0_carry_n_5,mod_sub_return0__0_carry_n_6,NLW_mod_sub_return0__0_carry_O_UNCONNECTED[0]}), .S(\rise_trail_center_offset_r_reg[3]_0 )); CARRY4 mod_sub_return0__0_carry__0 (.CI(mod_sub_return0__0_carry_n_0), .CO({NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\edge_diff_r_reg[0]_0 [4]}), .O({NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__0_carry__0_n_6,mod_sub_return0__0_carry__0_n_7}), .S({1'b0,1'b0,\rise_trail_center_offset_r_reg[5]_0 })); CARRY4 mod_sub_return0_carry (.CI(1'b0), .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}), .CYINIT(1'b1), .DI({Q[3],\edge_diff_r_reg[0]_0 [2:0]}), .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}), .S({mod_sub_return0_carry_i_1_n_0,\rise_trail_center_offset_r_reg[2]_0 })); CARRY4 mod_sub_return0_carry__0 (.CI(mod_sub_return0_carry_n_0), .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,mod_sub_return0_carry__0_i_1_n_0}), .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}), .S({1'b0,1'b0,\rise_lead_center_offset_r_reg[4]_1 })); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry__0_i_1 (.I0(Q[4]), .I1(\edge_diff_r_reg[0]_0 [4]), .O(mod_sub_return0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry_i_1 (.I0(\edge_diff_r_reg[0]_0 [3]), .I1(Q[3]), .O(mod_sub_return0_carry_i_1_n_0)); CARRY4 poc_backup_ns0_carry (.CI(1'b0), .CO({poc_backup_ns0,poc_backup_ns0_carry_n_1,poc_backup_ns0_carry_n_2,poc_backup_ns0_carry_n_3}), .CYINIT(1'b0), .DI({poc_backup_ns0_carry_i_1_n_0,poc_backup_ns0_carry_i_2_n_0,poc_backup_ns0_carry_i_3_n_0,poc_backup_ns0_carry_i_4_n_0}), .O(NLW_poc_backup_ns0_carry_O_UNCONNECTED[3:0]), .S({poc_backup_ns0_carry_i_5_n_0,poc_backup_ns0_carry_i_6_n_0,poc_backup_ns0_carry_i_7_n_0,poc_backup_ns0_carry_i_8_n_0})); LUT6 #( .INIT(64'h154015407FD51540)) poc_backup_ns0_carry_i_1 (.I0(prev_r[7]), .I1(\diff_r_reg_n_0_[6] ), .I2(poc_backup_ns0_carry_i_9_n_0), .I3(\diff_r_reg_n_0_[7] ), .I4(poc_backup_ns0_carry_i_10_n_0), .I5(prev_r[6]), .O(poc_backup_ns0_carry_i_1_n_0)); LUT6 #( .INIT(64'hF00C0C0C580C0C0C)) poc_backup_ns0_carry_i_10 (.I0(\diff_r_reg[2]_0 ), .I1(\diff_r_reg_n_0_[7] ), .I2(\diff_r_reg_n_0_[6] ), .I3(\diff_r_reg_n_0_[4] ), .I4(\diff_r_reg_n_0_[5] ), .I5(\diff_r_reg_n_0_[3] ), .O(poc_backup_ns0_carry_i_10_n_0)); (* SOFT_HLUTNM = "soft_lutpair441" *) LUT2 #( .INIT(4'h1)) poc_backup_ns0_carry_i_11 (.I0(\diff_r_reg_n_0_[6] ), .I1(\diff_r_reg_n_0_[7] ), .O(poc_backup_ns0_carry_i_11_n_0)); (* SOFT_HLUTNM = "soft_lutpair442" *) LUT4 #( .INIT(16'h0001)) poc_backup_ns0_carry_i_12 (.I0(\prev_r_reg[2]_0 [1]), .I1(\prev_r_reg[2]_0 [0]), .I2(\prev_r_reg[2]_0 [2]), .I3(\diff_r_reg_n_0_[3] ), .O(poc_backup_ns0_carry_i_12_n_0)); LUT6 #( .INIT(64'h0FF00FF00FF00F8F)) poc_backup_ns0_carry_i_13 (.I0(\diff_r_reg_n_0_[4] ), .I1(\diff_r_reg_n_0_[5] ), .I2(\diff_r_reg_n_0_[3] ), .I3(\diff_r_reg[2]_0 ), .I4(\diff_r_reg_n_0_[6] ), .I5(\diff_r_reg_n_0_[7] ), .O(poc_backup_ns0_carry_i_13_n_0)); (* SOFT_HLUTNM = "soft_lutpair442" *) LUT4 #( .INIT(16'h6663)) poc_backup_ns0_carry_i_14 (.I0(poc_backup_ns0_carry_i_15_n_0), .I1(\prev_r_reg[2]_0 [2]), .I2(\prev_r_reg[2]_0 [0]), .I3(\prev_r_reg[2]_0 [1]), .O(poc_backup_ns0_carry_i_14_n_0)); (* SOFT_HLUTNM = "soft_lutpair441" *) LUT5 #( .INIT(32'h01111111)) poc_backup_ns0_carry_i_15 (.I0(\diff_r_reg_n_0_[7] ), .I1(\diff_r_reg_n_0_[6] ), .I2(\diff_r_reg_n_0_[4] ), .I3(\diff_r_reg_n_0_[5] ), .I4(\diff_r_reg_n_0_[3] ), .O(poc_backup_ns0_carry_i_15_n_0)); LUT6 #( .INIT(64'hA556A956A956A956)) poc_backup_ns0_carry_i_16 (.I0(prev_r[3]), .I1(poc_backup_ns0_carry_i_11_n_0), .I2(\diff_r_reg[2]_0 ), .I3(\diff_r_reg_n_0_[3] ), .I4(\diff_r_reg_n_0_[5] ), .I5(\diff_r_reg_n_0_[4] ), .O(poc_backup_ns0_carry_i_16_n_0)); LUT6 #( .INIT(64'h44541101C5F45351)) poc_backup_ns0_carry_i_2 (.I0(prev_r[5]), .I1(poc_backup_ns0_carry_i_11_n_0), .I2(\diff_r_reg_n_0_[4] ), .I3(poc_backup_ns0_carry_i_12_n_0), .I4(\diff_r_reg_n_0_[5] ), .I5(prev_r[4]), .O(poc_backup_ns0_carry_i_2_n_0)); LUT4 #( .INIT(16'h1117)) poc_backup_ns0_carry_i_3 (.I0(prev_r[3]), .I1(poc_backup_ns0_carry_i_13_n_0), .I2(prev_r[2]), .I3(poc_backup_ns0_carry_i_14_n_0), .O(poc_backup_ns0_carry_i_3_n_0)); LUT5 #( .INIT(32'h5014D45C)) poc_backup_ns0_carry_i_4 (.I0(prev_r[1]), .I1(\prev_r_reg[2]_0 [0]), .I2(\prev_r_reg[2]_0 [1]), .I3(poc_backup_ns0_carry_i_15_n_0), .I4(prev_r[0]), .O(poc_backup_ns0_carry_i_4_n_0)); LUT6 #( .INIT(64'h6A95000000006A95)) poc_backup_ns0_carry_i_5 (.I0(\diff_r_reg_n_0_[7] ), .I1(poc_backup_ns0_carry_i_9_n_0), .I2(\diff_r_reg_n_0_[6] ), .I3(prev_r[7]), .I4(poc_backup_ns0_carry_i_10_n_0), .I5(prev_r[6]), .O(poc_backup_ns0_carry_i_5_n_0)); LUT6 #( .INIT(64'h9006990006900096)) poc_backup_ns0_carry_i_6 (.I0(\diff_r_reg_n_0_[5] ), .I1(prev_r[5]), .I2(poc_backup_ns0_carry_i_11_n_0), .I3(\diff_r_reg_n_0_[4] ), .I4(poc_backup_ns0_carry_i_12_n_0), .I5(prev_r[4]), .O(poc_backup_ns0_carry_i_6_n_0)); LUT6 #( .INIT(64'h828282A02828280A)) poc_backup_ns0_carry_i_7 (.I0(poc_backup_ns0_carry_i_16_n_0), .I1(poc_backup_ns0_carry_i_15_n_0), .I2(\prev_r_reg[2]_0 [2]), .I3(\prev_r_reg[2]_0 [0]), .I4(\prev_r_reg[2]_0 [1]), .I5(prev_r[2]), .O(poc_backup_ns0_carry_i_7_n_0)); LUT5 #( .INIT(32'h960000C3)) poc_backup_ns0_carry_i_8 (.I0(poc_backup_ns0_carry_i_15_n_0), .I1(\prev_r_reg[2]_0 [1]), .I2(prev_r[1]), .I3(\prev_r_reg[2]_0 [0]), .I4(prev_r[0]), .O(poc_backup_ns0_carry_i_8_n_0)); LUT6 #( .INIT(64'h8888888888888880)) poc_backup_ns0_carry_i_9 (.I0(\diff_r_reg_n_0_[5] ), .I1(\diff_r_reg_n_0_[4] ), .I2(\diff_r_reg_n_0_[3] ), .I3(\prev_r_reg[2]_0 [2]), .I4(\prev_r_reg[2]_0 [0]), .I5(\prev_r_reg[2]_0 [1]), .O(poc_backup_ns0_carry_i_9_n_0)); LUT5 #( .INIT(32'h20202220)) poc_backup_r_i_1 (.I0(poc_backup_ns0), .I1(\run_ends_r_reg[1]_0 ), .I2(edge_aligned_r_i_3_n_0), .I3(diffs_eq_r), .I4(edge_aligned_r_i_2_n_0), .O(poc_backup_ns)); FDRE #( .INIT(1'b0)) poc_backup_r_reg (.C(CLK), .CE(1'b1), .D(poc_backup_ns), .Q(poc_backup_r_reg_0), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[0] (.C(CLK), .CE(done_ns), .D(\prev_r_reg[2]_0 [0]), .Q(prev_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[1] (.C(CLK), .CE(done_ns), .D(\prev_r_reg[2]_0 [1]), .Q(prev_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[2] (.C(CLK), .CE(done_ns), .D(\prev_r_reg[2]_0 [2]), .Q(prev_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[3] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[3] ), .Q(prev_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[4] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[4] ), .Q(prev_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[5] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[5] ), .Q(prev_r[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[6] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[6] ), .Q(prev_r[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \prev_r_reg[7] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[7] ), .Q(prev_r[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_center_offset_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_center_offset_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_center_offset_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_center_offset_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_center_offset_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_lead_center_offset_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [5]), .Q(Q[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_center_offset_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [0]), .Q(\edge_diff_r_reg[0]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_center_offset_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [1]), .Q(\edge_diff_r_reg[0]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_center_offset_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [2]), .Q(\edge_diff_r_reg[0]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_center_offset_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [3]), .Q(\edge_diff_r_reg[0]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_center_offset_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [4]), .Q(\edge_diff_r_reg[0]_0 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rise_trail_center_offset_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [5]), .Q(\edge_diff_r_reg[0]_0 [5]), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r2_reg_srl3 " *) SRL16E #( .INIT(16'h0000)) run_end_r2_reg_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(samps_zero_r_reg_0), .Q(run_end_r2_reg_srl3_n_0)); FDRE #( .INIT(1'b0)) run_end_r3_reg (.C(CLK), .CE(1'b1), .D(run_end_r2_reg_srl3_n_0), .Q(run_end_r3), .R(1'b0)); LUT5 #( .INIT(32'h0000DACA)) \run_ends_r[0]_i_1 (.I0(\prev_r_reg[0]_0 ), .I1(\prev_r_reg[0]_1 ), .I2(run_end_r3), .I3(run_polarity_held_r), .I4(reset_run_ends), .O(\run_ends_r[0]_i_1_n_0 )); LUT3 #( .INIT(8'hFB)) \run_ends_r[0]_i_2 (.I0(run_too_small_r3), .I1(ocd_edge_detect_rdy_r_reg), .I2(rstdiv0_sync_r1_reg_rep__20), .O(reset_run_ends)); LUT6 #( .INIT(64'h0000000000EC0000)) \run_ends_r[1]_i_1 (.I0(\prev_r_reg[0]_0 ), .I1(\prev_r_reg[0]_1 ), .I2(run_end_r3), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_edge_detect_rdy_r_reg), .I5(run_too_small_r3), .O(\run_ends_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \run_ends_r_reg[0] (.C(CLK), .CE(1'b1), .D(\run_ends_r[0]_i_1_n_0 ), .Q(\prev_r_reg[0]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \run_ends_r_reg[1] (.C(CLK), .CE(1'b1), .D(\run_ends_r[1]_i_1_n_0 ), .Q(\prev_r_reg[0]_1 ), .R(1'b0)); FDRE #( .INIT(1'b0)) run_polarity_held_r_reg (.C(CLK), .CE(1'b1), .D(samps_zero_r_reg), .Q(run_polarity_held_r), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r2_reg_srl2 " *) SRL16E #( .INIT(16'h0000)) run_too_small_r2_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(run_too_small_r10), .Q(run_too_small_r2_reg_srl2_n_0)); LUT3 #( .INIT(8'h08)) run_too_small_r2_reg_srl2_i_1 (.I0(run_too_small_r_reg), .I1(\prev_r_reg[0]_0 ), .I2(\prev_r_reg[0]_1 ), .O(run_too_small_r10)); FDRE #( .INIT(1'b0)) run_too_small_r3_reg (.C(CLK), .CE(1'b1), .D(run_too_small_r2_reg_srl2_n_0), .Q(run_too_small_r3), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[0] (.C(CLK), .CE(1'b1), .D(center0_return0[0]), .Q(\diff_r_reg[7]_1 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[1] (.C(CLK), .CE(1'b1), .D(center0_return0[1]), .Q(\diff_r_reg[7]_1 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[2] (.C(CLK), .CE(1'b1), .D(center0_return0[2]), .Q(\diff_r_reg[7]_1 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[3] (.C(CLK), .CE(1'b1), .D(center0_return0[3]), .Q(\diff_r_reg[7]_1 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[4] (.C(CLK), .CE(1'b1), .D(center0_return0[4]), .Q(\diff_r_reg[7]_1 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[5] (.C(CLK), .CE(1'b1), .D(center0_return0[5]), .Q(\diff_r_reg[7]_1 [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \window_center_r_reg[6] (.C(CLK), .CE(1'b1), .D(center0_return0[6]), .Q(\diff_r_reg[7]_1 [6]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_ifmig_7series_v4_0_poc_pd (pd_out_pre, mmcm_ps_clk, in_dqs_lpbk_to_iddr_0, rst_sync_r1, CLK); output [0:0]pd_out_pre; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_0; input rst_sync_r1; input CLK; wire CLK; wire in_dqs_lpbk_to_iddr_0; wire mmcm_ps_clk; wire [0:0]pd_out_pre; wire pos_edge_samp; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE #( .INIT(1'b0)) \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(pos_edge_samp), .R(1'b0)); FDRE #( .INIT(1'b0)) pd_out_r_reg (.C(CLK), .CE(1'b1), .D(pos_edge_samp), .Q(pd_out_pre), .R(1'b0)); (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_0), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_ifmig_7series_v4_0_poc_pd_1 (pd_out_pre, mmcm_ps_clk, in_dqs_lpbk_to_iddr_1, rst_sync_r1, CLK); output [0:0]pd_out_pre; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_1; input rst_sync_r1; input CLK; wire CLK; wire in_dqs_lpbk_to_iddr_1; wire mmcm_ps_clk; wire \no_eXes.pos_edge_samp_reg_n_0 ; wire [0:0]pd_out_pre; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE #( .INIT(1'b0)) \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(\no_eXes.pos_edge_samp_reg_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) pd_out_r_reg (.C(CLK), .CE(1'b1), .D(\no_eXes.pos_edge_samp_reg_n_0 ), .Q(pd_out_pre), .R(1'b0)); (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_1), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_ifmig_7series_v4_0_poc_pd_2 (pd_out_pre, mmcm_ps_clk, in_dqs_lpbk_to_iddr_2, rst_sync_r1, CLK); output [0:0]pd_out_pre; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_2; input rst_sync_r1; input CLK; wire CLK; wire in_dqs_lpbk_to_iddr_2; wire mmcm_ps_clk; wire \no_eXes.pos_edge_samp_reg_n_0 ; wire [0:0]pd_out_pre; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE #( .INIT(1'b0)) \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(\no_eXes.pos_edge_samp_reg_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) pd_out_r_reg (.C(CLK), .CE(1'b1), .D(\no_eXes.pos_edge_samp_reg_n_0 ), .Q(pd_out_pre), .R(1'b0)); (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_2), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_ifmig_7series_v4_0_poc_pd_3 (pd_out, mmcm_ps_clk, in_dqs_lpbk_to_iddr_3, rst_sync_r1, CLK, pd_out_r_reg_0, \gen_byte_sel_div1.byte_sel_cnt_reg[1] ); output pd_out; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_3; input rst_sync_r1; input CLK; input [2:0]pd_out_r_reg_0; input [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire CLK; wire [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire in_dqs_lpbk_to_iddr_3; wire mmcm_ps_clk; wire \no_eXes.pos_edge_samp_reg_n_0 ; wire pd_out; wire [3:3]pd_out_pre; wire [2:0]pd_out_r_reg_0; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE #( .INIT(1'b0)) \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(\no_eXes.pos_edge_samp_reg_n_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) pd_out_r_reg (.C(CLK), .CE(1'b1), .D(\no_eXes.pos_edge_samp_reg_n_0 ), .Q(pd_out_pre), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \samps_hi_r[3]_i_7 (.I0(pd_out_pre), .I1(pd_out_r_reg_0[2]), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1] [1]), .I3(pd_out_r_reg_0[1]), .I4(\gen_byte_sel_div1.byte_sel_cnt_reg[1] [0]), .I5(pd_out_r_reg_0[0]), .O(pd_out)); (* __SRVAL = "FALSE" *) (* box_type = "PRIMITIVE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_3), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_tap_base" *) module ddr3_ifmig_7series_v4_0_poc_tap_base (\run_r_reg[0]_0 , run_too_small_r3_reg, \run_r_reg[0]_1 , \run_r_reg[0]_2 , Q, S, \samp_cntr_r_reg[8]_0 , \samp_cntr_r_reg[12]_0 , \samp_cntr_r_reg[16]_0 , \samps_hi_r_reg[3]_0 , \samps_hi_r_reg[7]_0 , \samps_hi_r_reg[11]_0 , \samps_hi_r_reg[15]_0 , \samps_hi_r_reg[17]_0 , samps_zero_r_reg_0, \tap_r_reg[0]_0 , \run_r_reg[4]_0 , run_too_small_r_reg_0, \rise_trail_r_reg[0] , \sm_r_reg[0]_0 , \sm_r_reg[0]_1 , \qcntr_r_reg[0] , \rise_lead_r_reg[5] , DI, samps_zero_r_reg_1, samps_zero_r_reg_2, samps_zero_r_reg_3, samps_zero_r_reg_4, samps_zero_r_reg_5, \samp_cntr_r_reg[0]_0 , \rise_trail_r_reg[5] , \rise_trail_r_reg[5]_0 , \rise_trail_r_reg[5]_1 , \rise_trail_r_reg[3] , \samp_wait_r_reg[6]_0 , \samp_wait_r_reg[7]_0 , \rise_trail_r_reg[5]_2 , \rise_trail_r_reg[5]_3 , CLK, samps_lo, rstdiv0_sync_r1_reg_rep__20, \run_r_reg[2]_0 , ocd_ktap_left_r_reg, ocd_ktap_right_r_reg, trailing_edge0, trailing_edge00_in, poc_sample_pd, \samp_wait_r_reg[4]_0 , samp_cntr_ns0, samps_hi_ns0, psdone, rstdiv0_sync_r1_reg_rep, D, rstdiv0_sync_r1_reg_rep__0, E); output \run_r_reg[0]_0 ; output run_too_small_r3_reg; output \run_r_reg[0]_1 ; output \run_r_reg[0]_2 ; output [4:0]Q; output [3:0]S; output [3:0]\samp_cntr_r_reg[8]_0 ; output [3:0]\samp_cntr_r_reg[12]_0 ; output [3:0]\samp_cntr_r_reg[16]_0 ; output [2:0]\samps_hi_r_reg[3]_0 ; output [3:0]\samps_hi_r_reg[7]_0 ; output [3:0]\samps_hi_r_reg[11]_0 ; output [3:0]\samps_hi_r_reg[15]_0 ; output [1:0]\samps_hi_r_reg[17]_0 ; output [3:0]samps_zero_r_reg_0; output \tap_r_reg[0]_0 ; output [4:0]\run_r_reg[4]_0 ; output run_too_small_r_reg_0; output [0:0]\rise_trail_r_reg[0] ; output \sm_r_reg[0]_0 ; output \sm_r_reg[0]_1 ; output [0:0]\qcntr_r_reg[0] ; output [5:0]\rise_lead_r_reg[5] ; output [0:0]DI; output [3:0]samps_zero_r_reg_1; output [2:0]samps_zero_r_reg_2; output [2:0]samps_zero_r_reg_3; output [0:0]samps_zero_r_reg_4; output [0:0]samps_zero_r_reg_5; output [0:0]\samp_cntr_r_reg[0]_0 ; output [5:0]\rise_trail_r_reg[5] ; output [0:0]\rise_trail_r_reg[5]_0 ; output [0:0]\rise_trail_r_reg[5]_1 ; output [0:0]\rise_trail_r_reg[3] ; output \samp_wait_r_reg[6]_0 ; output [6:0]\samp_wait_r_reg[7]_0 ; output [0:0]\rise_trail_r_reg[5]_2 ; output [0:0]\rise_trail_r_reg[5]_3 ; input CLK; input [14:0]samps_lo; input rstdiv0_sync_r1_reg_rep__20; input \run_r_reg[2]_0 ; input ocd_ktap_left_r_reg; input ocd_ktap_right_r_reg; input [5:0]trailing_edge0; input [5:0]trailing_edge00_in; input poc_sample_pd; input \samp_wait_r_reg[4]_0 ; input [15:0]samp_cntr_ns0; input [17:0]samps_hi_ns0; input psdone; input rstdiv0_sync_r1_reg_rep; input [1:0]D; input rstdiv0_sync_r1_reg_rep__0; input [0:0]E; wire CLK; wire [1:0]D; wire [0:0]DI; wire [0:0]E; wire [4:0]Q; wire [3:0]S; wire ocd_ktap_left_r_reg; wire ocd_ktap_right_r_reg; wire [5:0]p_0_in; wire [5:0]p_0_in__0; wire [7:0]p_1_in; wire poc_sample_pd; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire [5:0]\rise_lead_r_reg[5] ; wire \rise_trail_r[5]_i_4_n_0 ; wire \rise_trail_r[5]_i_6_n_0 ; wire \rise_trail_r[5]_i_7_n_0 ; wire \rise_trail_r[5]_i_8_n_0 ; wire \rise_trail_r[5]_i_9_n_0 ; wire [0:0]\rise_trail_r_reg[0] ; wire [0:0]\rise_trail_r_reg[3] ; wire [5:0]\rise_trail_r_reg[5] ; wire [0:0]\rise_trail_r_reg[5]_0 ; wire [0:0]\rise_trail_r_reg[5]_1 ; wire [0:0]\rise_trail_r_reg[5]_2 ; wire [0:0]\rise_trail_r_reg[5]_3 ; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire run_polarity_ns2_out; wire \run_r[5]_i_2_n_0 ; wire \run_r_reg[0]_0 ; wire \run_r_reg[0]_1 ; wire \run_r_reg[0]_2 ; wire \run_r_reg[2]_0 ; wire [4:0]\run_r_reg[4]_0 ; wire \run_r_reg_n_0_[5] ; wire run_too_small_ns; wire run_too_small_r3_reg; wire run_too_small_r_reg_0; wire [16:16]samp_cntr; wire [15:0]samp_cntr_ns0; wire \samp_cntr_r[0]_i_1_n_0 ; wire \samp_cntr_r[10]_i_1_n_0 ; wire \samp_cntr_r[11]_i_1_n_0 ; wire \samp_cntr_r[12]_i_1_n_0 ; wire \samp_cntr_r[13]_i_1_n_0 ; wire \samp_cntr_r[14]_i_1_n_0 ; wire \samp_cntr_r[15]_i_1_n_0 ; wire \samp_cntr_r[16]_i_1_n_0 ; wire \samp_cntr_r[1]_i_1_n_0 ; wire \samp_cntr_r[2]_i_1_n_0 ; wire \samp_cntr_r[3]_i_1_n_0 ; wire \samp_cntr_r[4]_i_1_n_0 ; wire \samp_cntr_r[5]_i_1_n_0 ; wire \samp_cntr_r[6]_i_1_n_0 ; wire \samp_cntr_r[7]_i_1_n_0 ; wire \samp_cntr_r[8]_i_1_n_0 ; wire \samp_cntr_r[9]_i_1_n_0 ; wire [0:0]\samp_cntr_r_reg[0]_0 ; wire [3:0]\samp_cntr_r_reg[12]_0 ; wire [3:0]\samp_cntr_r_reg[16]_0 ; wire [3:0]\samp_cntr_r_reg[8]_0 ; wire \samp_cntr_r_reg_n_0_[10] ; wire \samp_cntr_r_reg_n_0_[11] ; wire \samp_cntr_r_reg_n_0_[12] ; wire \samp_cntr_r_reg_n_0_[13] ; wire \samp_cntr_r_reg_n_0_[14] ; wire \samp_cntr_r_reg_n_0_[15] ; wire \samp_cntr_r_reg_n_0_[1] ; wire \samp_cntr_r_reg_n_0_[2] ; wire \samp_cntr_r_reg_n_0_[3] ; wire \samp_cntr_r_reg_n_0_[4] ; wire \samp_cntr_r_reg_n_0_[5] ; wire \samp_cntr_r_reg_n_0_[6] ; wire \samp_cntr_r_reg_n_0_[7] ; wire \samp_cntr_r_reg_n_0_[8] ; wire \samp_cntr_r_reg_n_0_[9] ; wire [5:5]samp_wait_r; wire \samp_wait_r[4]_i_2_n_0 ; wire \samp_wait_r[7]_i_1_n_0 ; wire \samp_wait_r_reg[4]_0 ; wire \samp_wait_r_reg[6]_0 ; wire [6:0]\samp_wait_r_reg[7]_0 ; wire [17:17]samps_hi; wire [17:0]samps_hi_ns0; wire \samps_hi_r[0]_i_1_n_0 ; wire \samps_hi_r[10]_i_1_n_0 ; wire \samps_hi_r[11]_i_1_n_0 ; wire \samps_hi_r[12]_i_1_n_0 ; wire \samps_hi_r[13]_i_1_n_0 ; wire \samps_hi_r[14]_i_1_n_0 ; wire \samps_hi_r[15]_i_1_n_0 ; wire \samps_hi_r[16]_i_1_n_0 ; wire \samps_hi_r[17]_i_1_n_0 ; wire \samps_hi_r[1]_i_1_n_0 ; wire \samps_hi_r[2]_i_1_n_0 ; wire \samps_hi_r[3]_i_1_n_0 ; wire \samps_hi_r[4]_i_1_n_0 ; wire \samps_hi_r[5]_i_1_n_0 ; wire \samps_hi_r[6]_i_1_n_0 ; wire \samps_hi_r[7]_i_1_n_0 ; wire \samps_hi_r[8]_i_1_n_0 ; wire \samps_hi_r[9]_i_1_n_0 ; wire [3:0]\samps_hi_r_reg[11]_0 ; wire [3:0]\samps_hi_r_reg[15]_0 ; wire [1:0]\samps_hi_r_reg[17]_0 ; wire [2:0]\samps_hi_r_reg[3]_0 ; wire [3:0]\samps_hi_r_reg[7]_0 ; wire \samps_hi_r_reg_n_0_[11] ; wire \samps_hi_r_reg_n_0_[12] ; wire \samps_hi_r_reg_n_0_[13] ; wire \samps_hi_r_reg_n_0_[14] ; wire \samps_hi_r_reg_n_0_[15] ; wire \samps_hi_r_reg_n_0_[16] ; wire \samps_hi_r_reg_n_0_[3] ; wire \samps_hi_r_reg_n_0_[4] ; wire \samps_hi_r_reg_n_0_[5] ; wire \samps_hi_r_reg_n_0_[6] ; wire \samps_hi_r_reg_n_0_[7] ; wire \samps_hi_r_reg_n_0_[8] ; wire [14:0]samps_lo; wire samps_one_ns; wire samps_one_r0_carry__0_i_1_n_0; wire samps_one_r0_carry__0_i_2_n_0; wire samps_one_r0_carry__0_i_3_n_0; wire samps_one_r0_carry__0_i_4_n_0; wire samps_one_r0_carry__0_i_5_n_0; wire samps_one_r0_carry__0_i_6_n_0; wire samps_one_r0_carry__0_i_7_n_0; wire samps_one_r0_carry__0_n_0; wire samps_one_r0_carry__0_n_1; wire samps_one_r0_carry__0_n_2; wire samps_one_r0_carry__0_n_3; wire samps_one_r0_carry__1_i_1_n_0; wire samps_one_r0_carry__1_i_2_n_0; wire samps_one_r0_carry_i_1_n_0; wire samps_one_r0_carry_i_2_n_0; wire samps_one_r0_carry_i_3_n_0; wire samps_one_r0_carry_i_4_n_0; wire samps_one_r0_carry_i_5_n_0; wire samps_one_r0_carry_i_6_n_0; wire samps_one_r0_carry_i_7_n_0; wire samps_one_r0_carry_n_0; wire samps_one_r0_carry_n_1; wire samps_one_r0_carry_n_2; wire samps_one_r0_carry_n_3; wire samps_zero_ns; wire samps_zero_r0_carry__0_i_1_n_0; wire samps_zero_r0_carry__0_i_2_n_0; wire samps_zero_r0_carry__0_i_3_n_0; wire samps_zero_r0_carry__0_i_5_n_0; wire samps_zero_r0_carry__0_i_6_n_0; wire samps_zero_r0_carry__0_i_7_n_0; wire samps_zero_r0_carry__0_i_8_n_0; wire samps_zero_r0_carry__0_n_0; wire samps_zero_r0_carry__0_n_1; wire samps_zero_r0_carry__0_n_2; wire samps_zero_r0_carry__0_n_3; wire samps_zero_r0_carry__1_i_1_n_0; wire samps_zero_r0_carry__1_i_2_n_0; wire samps_zero_r0_carry_i_1_n_0; wire samps_zero_r0_carry_i_3_n_0; wire samps_zero_r0_carry_i_4_n_0; wire samps_zero_r0_carry_i_5_n_0; wire samps_zero_r0_carry_i_6_n_0; wire samps_zero_r0_carry_i_7_n_0; wire samps_zero_r0_carry_i_8_n_0; wire samps_zero_r0_carry_n_0; wire samps_zero_r0_carry_n_1; wire samps_zero_r0_carry_n_2; wire samps_zero_r0_carry_n_3; wire [3:0]samps_zero_r_reg_0; wire [3:0]samps_zero_r_reg_1; wire [2:0]samps_zero_r_reg_2; wire [2:0]samps_zero_r_reg_3; wire [0:0]samps_zero_r_reg_4; wire [0:0]samps_zero_r_reg_5; wire sm_ns0_carry__0_i_1_n_0; wire sm_ns0_carry__0_i_2_n_0; wire sm_ns0_carry__0_n_2; wire sm_ns0_carry__0_n_3; wire sm_ns0_carry_i_1_n_0; wire sm_ns0_carry_i_2_n_0; wire sm_ns0_carry_i_3_n_0; wire sm_ns0_carry_i_4_n_0; wire sm_ns0_carry_n_0; wire sm_ns0_carry_n_1; wire sm_ns0_carry_n_2; wire sm_ns0_carry_n_3; wire \sm_r[0]_i_1_n_0 ; wire \sm_r[0]_i_2_n_0 ; wire \sm_r[1]_i_1_n_0 ; wire \sm_r_reg[0]_0 ; wire \sm_r_reg[0]_1 ; wire \tap_r_reg[0]_0 ; wire [5:0]trailing_edge0; wire [5:0]trailing_edge00_in; wire [3:0]NLW_samps_one_r0_carry_O_UNCONNECTED; wire [3:0]NLW_samps_one_r0_carry__0_O_UNCONNECTED; wire [3:1]NLW_samps_one_r0_carry__1_CO_UNCONNECTED; wire [3:0]NLW_samps_one_r0_carry__1_O_UNCONNECTED; wire [3:0]NLW_samps_zero_r0_carry_O_UNCONNECTED; wire [3:0]NLW_samps_zero_r0_carry__0_O_UNCONNECTED; wire [3:1]NLW_samps_zero_r0_carry__1_CO_UNCONNECTED; wire [3:0]NLW_samps_zero_r0_carry__1_O_UNCONNECTED; wire [3:0]NLW_sm_ns0_carry_O_UNCONNECTED; wire [3:2]NLW_sm_ns0_carry__0_CO_UNCONNECTED; wire [3:0]NLW_sm_ns0_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair450" *) LUT3 #( .INIT(8'h04)) \gen_mmcm.mmcm_i_i_1 (.I0(\sm_r_reg[0]_0 ), .I1(\sm_r_reg[0]_1 ), .I2(rstdiv0_sync_r1_reg_rep__20), .O(\qcntr_r_reg[0] )); LUT6 #( .INIT(64'h0000000000000001)) i___12_i_1__0 (.I0(\samp_wait_r_reg[7]_0 [3]), .I1(\samp_wait_r_reg[7]_0 [0]), .I2(\samp_wait_r_reg[7]_0 [1]), .I3(\samp_wait_r_reg[7]_0 [2]), .I4(\samp_wait_r_reg[7]_0 [4]), .I5(samp_wait_r), .O(\samp_wait_r_reg[6]_0 )); LUT6 #( .INIT(64'h0000000000B80000)) i___7_i_1__0 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\run_r_reg[0]_2 ), .I3(\sm_r_reg[0]_0 ), .I4(\sm_r_reg[0]_1 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(run_too_small_r_reg_0)); LUT1 #( .INIT(2'h1)) i__carry__0_i_1 (.I0(\run_r_reg[4]_0 [3]), .O(DI)); LUT4 #( .INIT(16'h9699)) i__carry__0_i_2 (.I0(\rise_lead_r_reg[5] [5]), .I1(\run_r_reg_n_0_[5] ), .I2(\rise_lead_r_reg[5] [4]), .I3(\run_r_reg[4]_0 [4]), .O(\rise_trail_r_reg[5]_0 )); LUT2 #( .INIT(4'h6)) i__carry_i_1 (.I0(\rise_lead_r_reg[5] [3]), .I1(\run_r_reg[4]_0 [3]), .O(\rise_trail_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair457" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[0]_i_1 (.I0(trailing_edge0[0]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[0]), .O(\rise_trail_r_reg[5] [0])); (* SOFT_HLUTNM = "soft_lutpair457" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[1]_i_1 (.I0(trailing_edge0[1]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[1]), .O(\rise_trail_r_reg[5] [1])); (* SOFT_HLUTNM = "soft_lutpair456" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[2]_i_1 (.I0(trailing_edge0[2]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[2]), .O(\rise_trail_r_reg[5] [2])); (* SOFT_HLUTNM = "soft_lutpair456" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[3]_i_1 (.I0(trailing_edge0[3]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[3]), .O(\rise_trail_r_reg[5] [3])); (* SOFT_HLUTNM = "soft_lutpair455" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[4]_i_1 (.I0(trailing_edge0[4]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[4]), .O(\rise_trail_r_reg[5] [4])); LUT4 #( .INIT(16'h0008)) \rise_trail_r[5]_i_1 (.I0(\run_r_reg[0]_0 ), .I1(run_too_small_r_reg_0), .I2(ocd_ktap_left_r_reg), .I3(ocd_ktap_right_r_reg), .O(\rise_trail_r_reg[0] )); LUT5 #( .INIT(32'h00800000)) \rise_trail_r[5]_i_1__0 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\tap_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_right_r_reg), .O(\rise_trail_r_reg[5]_2 )); LUT5 #( .INIT(32'h00800000)) \rise_trail_r[5]_i_1__1 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\tap_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_left_r_reg), .O(\rise_trail_r_reg[5]_3 )); (* SOFT_HLUTNM = "soft_lutpair455" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[5]_i_2 (.I0(trailing_edge0[5]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[5]), .O(\rise_trail_r_reg[5] [5])); LUT6 #( .INIT(64'h88888888A8AA88A8)) \rise_trail_r[5]_i_4 (.I0(\rise_trail_r[5]_i_6_n_0 ), .I1(\rise_trail_r[5]_i_7_n_0 ), .I2(\rise_trail_r[5]_i_8_n_0 ), .I3(\run_r_reg[4]_0 [3]), .I4(\rise_lead_r_reg[5] [3]), .I5(\rise_trail_r[5]_i_9_n_0 ), .O(\rise_trail_r[5]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \rise_trail_r[5]_i_5 (.I0(\run_r_reg_n_0_[5] ), .I1(\rise_lead_r_reg[5] [5]), .O(\rise_trail_r_reg[5]_1 )); (* SOFT_HLUTNM = "soft_lutpair451" *) LUT2 #( .INIT(4'hB)) \rise_trail_r[5]_i_6 (.I0(\rise_lead_r_reg[5] [5]), .I1(\run_r_reg_n_0_[5] ), .O(\rise_trail_r[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair451" *) LUT4 #( .INIT(16'h4F44)) \rise_trail_r[5]_i_7 (.I0(\run_r_reg_n_0_[5] ), .I1(\rise_lead_r_reg[5] [5]), .I2(\run_r_reg[4]_0 [4]), .I3(\rise_lead_r_reg[5] [4]), .O(\rise_trail_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'hDF0D4F04DF0DDF0D)) \rise_trail_r[5]_i_8 (.I0(\run_r_reg[4]_0 [1]), .I1(\rise_lead_r_reg[5] [1]), .I2(\run_r_reg[4]_0 [2]), .I3(\rise_lead_r_reg[5] [2]), .I4(\rise_lead_r_reg[5] [0]), .I5(\run_r_reg[4]_0 [0]), .O(\rise_trail_r[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair454" *) LUT2 #( .INIT(4'h2)) \rise_trail_r[5]_i_9 (.I0(\run_r_reg[4]_0 [4]), .I1(\rise_lead_r_reg[5] [4]), .O(\rise_trail_r[5]_i_9_n_0 )); LUT6 #( .INIT(64'h5151040055550400)) run_polarity_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\sm_r_reg[0]_1 ), .I2(\sm_r_reg[0]_0 ), .I3(\run_r_reg[0]_2 ), .I4(\run_r_reg[0]_0 ), .I5(\run_r_reg[0]_1 ), .O(run_polarity_ns2_out)); FDRE #( .INIT(1'b0)) run_polarity_r_reg (.C(CLK), .CE(1'b1), .D(run_polarity_ns2_out), .Q(\run_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000333347FF)) \run_r[0]_i_1 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\run_r_reg[0]_2 ), .I3(\tap_r_reg[0]_0 ), .I4(rstdiv0_sync_r1_reg_rep__20), .I5(\run_r_reg[4]_0 [0]), .O(p_0_in__0[0])); LUT3 #( .INIT(8'h28)) \run_r[1]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [0]), .I2(\run_r_reg[4]_0 [1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair448" *) LUT4 #( .INIT(16'h2A80)) \run_r[2]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [1]), .I2(\run_r_reg[4]_0 [0]), .I3(\run_r_reg[4]_0 [2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair448" *) LUT5 #( .INIT(32'h2AAA8000)) \run_r[3]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [0]), .I2(\run_r_reg[4]_0 [1]), .I3(\run_r_reg[4]_0 [2]), .I4(\run_r_reg[4]_0 [3]), .O(p_0_in__0[3])); LUT6 #( .INIT(64'h2AAAAAAA80000000)) \run_r[4]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [2]), .I2(\run_r_reg[4]_0 [1]), .I3(\run_r_reg[4]_0 [0]), .I4(\run_r_reg[4]_0 [3]), .I5(\run_r_reg[4]_0 [4]), .O(p_0_in__0[4])); (* SOFT_HLUTNM = "soft_lutpair454" *) LUT4 #( .INIT(16'h8A20)) \run_r[5]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[2]_0 ), .I2(\run_r_reg[4]_0 [4]), .I3(\run_r_reg_n_0_[5] ), .O(p_0_in__0[5])); LUT6 #( .INIT(64'h5151FBFF5555FBFF)) \run_r[5]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\sm_r_reg[0]_1 ), .I2(\sm_r_reg[0]_0 ), .I3(\run_r_reg[0]_2 ), .I4(\run_r_reg[0]_0 ), .I5(\run_r_reg[0]_1 ), .O(\run_r[5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \run_r_reg[0] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[0]), .Q(\run_r_reg[4]_0 [0]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \run_r_reg[1] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[1]), .Q(\run_r_reg[4]_0 [1]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \run_r_reg[2] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[2]), .Q(\run_r_reg[4]_0 [2]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \run_r_reg[3] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[3]), .Q(\run_r_reg[4]_0 [3]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \run_r_reg[4] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[4]), .Q(\run_r_reg[4]_0 [4]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \run_r_reg[5] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[5]), .Q(\run_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep)); LUT6 #( .INIT(64'h0002020202020202)) run_too_small_r_i_1 (.I0(run_too_small_r_reg_0), .I1(\run_r_reg[4]_0 [4]), .I2(\run_r_reg_n_0_[5] ), .I3(\run_r_reg[4]_0 [3]), .I4(\run_r_reg[4]_0 [2]), .I5(\run_r_reg[4]_0 [1]), .O(run_too_small_ns)); FDRE #( .INIT(1'b0)) run_too_small_r_reg (.C(CLK), .CE(1'b1), .D(run_too_small_ns), .Q(run_too_small_r3_reg), .R(1'b0)); LUT2 #( .INIT(4'h1)) \samp_cntr_r[0]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\samp_cntr_r_reg[0]_0 ), .O(\samp_cntr_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair474" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[10]_i_1 (.I0(samp_cntr_ns0[9]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair466" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[11]_i_1 (.I0(samp_cntr_ns0[10]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair469" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[12]_i_1 (.I0(samp_cntr_ns0[11]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[12]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_3 (.I0(\samp_cntr_r_reg_n_0_[12] ), .O(\samp_cntr_r_reg[12]_0 [3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_4 (.I0(\samp_cntr_r_reg_n_0_[11] ), .O(\samp_cntr_r_reg[12]_0 [2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_5 (.I0(\samp_cntr_r_reg_n_0_[10] ), .O(\samp_cntr_r_reg[12]_0 [1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_6 (.I0(\samp_cntr_r_reg_n_0_[9] ), .O(\samp_cntr_r_reg[12]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair470" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[13]_i_1 (.I0(samp_cntr_ns0[12]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair470" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[14]_i_1 (.I0(samp_cntr_ns0[13]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair473" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[15]_i_1 (.I0(samp_cntr_ns0[14]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair471" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[16]_i_1 (.I0(samp_cntr_ns0[15]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[16]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_3 (.I0(samp_cntr), .O(\samp_cntr_r_reg[16]_0 [3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_4 (.I0(\samp_cntr_r_reg_n_0_[15] ), .O(\samp_cntr_r_reg[16]_0 [2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_5 (.I0(\samp_cntr_r_reg_n_0_[14] ), .O(\samp_cntr_r_reg[16]_0 [1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_6 (.I0(\samp_cntr_r_reg_n_0_[13] ), .O(\samp_cntr_r_reg[16]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair463" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[1]_i_1 (.I0(samp_cntr_ns0[0]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair461" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[2]_i_1 (.I0(samp_cntr_ns0[1]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair465" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[3]_i_1 (.I0(samp_cntr_ns0[2]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair474" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[4]_i_1 (.I0(samp_cntr_ns0[3]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_3 (.I0(\samp_cntr_r_reg_n_0_[4] ), .O(S[3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_4 (.I0(\samp_cntr_r_reg_n_0_[3] ), .O(S[2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_5 (.I0(\samp_cntr_r_reg_n_0_[2] ), .O(S[1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_6 (.I0(\samp_cntr_r_reg_n_0_[1] ), .O(S[0])); (* SOFT_HLUTNM = "soft_lutpair464" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[5]_i_1 (.I0(samp_cntr_ns0[4]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair468" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[6]_i_1 (.I0(samp_cntr_ns0[5]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair472" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[7]_i_1 (.I0(samp_cntr_ns0[6]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair459" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[8]_i_1 (.I0(samp_cntr_ns0[7]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[8]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_3 (.I0(\samp_cntr_r_reg_n_0_[8] ), .O(\samp_cntr_r_reg[8]_0 [3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_4 (.I0(\samp_cntr_r_reg_n_0_[7] ), .O(\samp_cntr_r_reg[8]_0 [2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_5 (.I0(\samp_cntr_r_reg_n_0_[6] ), .O(\samp_cntr_r_reg[8]_0 [1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_6 (.I0(\samp_cntr_r_reg_n_0_[5] ), .O(\samp_cntr_r_reg[8]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair462" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[9]_i_1 (.I0(samp_cntr_ns0[8]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[0] (.C(CLK), .CE(E), .D(\samp_cntr_r[0]_i_1_n_0 ), .Q(\samp_cntr_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[10] (.C(CLK), .CE(E), .D(\samp_cntr_r[10]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[10] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[11] (.C(CLK), .CE(E), .D(\samp_cntr_r[11]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[11] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[12] (.C(CLK), .CE(E), .D(\samp_cntr_r[12]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[12] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[13] (.C(CLK), .CE(E), .D(\samp_cntr_r[13]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[13] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[14] (.C(CLK), .CE(E), .D(\samp_cntr_r[14]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[14] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[15] (.C(CLK), .CE(E), .D(\samp_cntr_r[15]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[15] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[16] (.C(CLK), .CE(E), .D(\samp_cntr_r[16]_i_1_n_0 ), .Q(samp_cntr), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[1] (.C(CLK), .CE(E), .D(\samp_cntr_r[1]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[2] (.C(CLK), .CE(E), .D(\samp_cntr_r[2]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[3] (.C(CLK), .CE(E), .D(\samp_cntr_r[3]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[4] (.C(CLK), .CE(E), .D(\samp_cntr_r[4]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[5] (.C(CLK), .CE(E), .D(\samp_cntr_r[5]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[6] (.C(CLK), .CE(E), .D(\samp_cntr_r[6]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[7] (.C(CLK), .CE(E), .D(\samp_cntr_r[7]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[8] (.C(CLK), .CE(E), .D(\samp_cntr_r[8]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samp_cntr_r_reg[9] (.C(CLK), .CE(E), .D(\samp_cntr_r[9]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[9] ), .R(rstdiv0_sync_r1_reg_rep__0)); (* SOFT_HLUTNM = "soft_lutpair453" *) LUT3 #( .INIT(8'h8F)) \samp_wait_r[0]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[7]_0 [0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair453" *) LUT4 #( .INIT(16'hF88F)) \samp_wait_r[1]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[7]_0 [1]), .I3(\samp_wait_r_reg[7]_0 [0]), .O(p_1_in[1])); LUT6 #( .INIT(64'hFFFFFFFEAAAAAAAB)) \samp_wait_r[4]_i_1 (.I0(\samp_wait_r[4]_i_2_n_0 ), .I1(\samp_wait_r_reg[7]_0 [3]), .I2(\samp_wait_r_reg[7]_0 [0]), .I3(\samp_wait_r_reg[7]_0 [1]), .I4(\samp_wait_r_reg[7]_0 [2]), .I5(\samp_wait_r_reg[7]_0 [4]), .O(p_1_in[4])); (* SOFT_HLUTNM = "soft_lutpair452" *) LUT2 #( .INIT(4'h8)) \samp_wait_r[4]_i_2 (.I0(\sm_r_reg[0]_0 ), .I1(\sm_r_reg[0]_1 ), .O(\samp_wait_r[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair452" *) LUT4 #( .INIT(16'h8FF8)) \samp_wait_r[5]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[4]_0 ), .I3(samp_wait_r), .O(p_1_in[5])); (* SOFT_HLUTNM = "soft_lutpair447" *) LUT4 #( .INIT(16'h8FF8)) \samp_wait_r[6]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[6]_0 ), .I3(\samp_wait_r_reg[7]_0 [5]), .O(p_1_in[6])); LUT5 #( .INIT(32'hFFFFFF8F)) \samp_wait_r[7]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[6]_0 ), .I3(\samp_wait_r_reg[7]_0 [5]), .I4(\samp_wait_r_reg[7]_0 [6]), .O(\samp_wait_r[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair447" *) LUT5 #( .INIT(32'hFF8F88F8)) \samp_wait_r[7]_i_2 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[6]_0 ), .I3(\samp_wait_r_reg[7]_0 [5]), .I4(\samp_wait_r_reg[7]_0 [6]), .O(p_1_in[7])); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[0] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[0]), .Q(\samp_wait_r_reg[7]_0 [0]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[1] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[1]), .Q(\samp_wait_r_reg[7]_0 [1]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[2] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(D[0]), .Q(\samp_wait_r_reg[7]_0 [2]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[3] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(D[1]), .Q(\samp_wait_r_reg[7]_0 [3]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[4] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[4]), .Q(\samp_wait_r_reg[7]_0 [4]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[5] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[5]), .Q(samp_wait_r), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[6] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[6]), .Q(\samp_wait_r_reg[7]_0 [5]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \samp_wait_r_reg[7] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[7]), .Q(\samp_wait_r_reg[7]_0 [6]), .R(rstdiv0_sync_r1_reg_rep)); (* SOFT_HLUTNM = "soft_lutpair471" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[0]_i_1 (.I0(samps_hi_ns0[0]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair467" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[10]_i_1 (.I0(samps_hi_ns0[10]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair465" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[11]_i_1 (.I0(samps_hi_ns0[11]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[11]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_3 (.I0(\samps_hi_r_reg_n_0_[11] ), .O(\samps_hi_r_reg[11]_0 [3])); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_4 (.I0(Q[4]), .O(\samps_hi_r_reg[11]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_5 (.I0(Q[3]), .O(\samps_hi_r_reg[11]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_6 (.I0(\samps_hi_r_reg_n_0_[8] ), .O(\samps_hi_r_reg[11]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair464" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[12]_i_1 (.I0(samps_hi_ns0[12]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair459" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[13]_i_1 (.I0(samps_hi_ns0[13]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair463" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[14]_i_1 (.I0(samps_hi_ns0[14]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair461" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[15]_i_1 (.I0(samps_hi_ns0[15]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[15]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_3 (.I0(\samps_hi_r_reg_n_0_[15] ), .O(\samps_hi_r_reg[15]_0 [3])); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_4 (.I0(\samps_hi_r_reg_n_0_[14] ), .O(\samps_hi_r_reg[15]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_5 (.I0(\samps_hi_r_reg_n_0_[13] ), .O(\samps_hi_r_reg[15]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_6 (.I0(\samps_hi_r_reg_n_0_[12] ), .O(\samps_hi_r_reg[15]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair460" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[16]_i_1 (.I0(samps_hi_ns0[16]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[16]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair458" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[17]_i_1 (.I0(samps_hi_ns0[17]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[17]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[17]_i_3 (.I0(samps_hi), .O(\samps_hi_r_reg[17]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[17]_i_4 (.I0(\samps_hi_r_reg_n_0_[16] ), .O(\samps_hi_r_reg[17]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair460" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[1]_i_1 (.I0(samps_hi_ns0[1]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair458" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[2]_i_1 (.I0(samps_hi_ns0[2]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair467" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[3]_i_1 (.I0(samps_hi_ns0[3]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[3]_i_3 (.I0(\samps_hi_r_reg_n_0_[3] ), .O(\samps_hi_r_reg[3]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[3]_i_4 (.I0(Q[2]), .O(\samps_hi_r_reg[3]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[3]_i_5 (.I0(Q[1]), .O(\samps_hi_r_reg[3]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair473" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[4]_i_1 (.I0(samps_hi_ns0[4]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair466" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[5]_i_1 (.I0(samps_hi_ns0[5]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair472" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[6]_i_1 (.I0(samps_hi_ns0[6]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair469" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[7]_i_1 (.I0(samps_hi_ns0[7]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_3 (.I0(\samps_hi_r_reg_n_0_[7] ), .O(\samps_hi_r_reg[7]_0 [3])); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_4 (.I0(\samps_hi_r_reg_n_0_[6] ), .O(\samps_hi_r_reg[7]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_5 (.I0(\samps_hi_r_reg_n_0_[5] ), .O(\samps_hi_r_reg[7]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_6 (.I0(\samps_hi_r_reg_n_0_[4] ), .O(\samps_hi_r_reg[7]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair468" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[8]_i_1 (.I0(samps_hi_ns0[8]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair462" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[9]_i_1 (.I0(samps_hi_ns0[9]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[0] (.C(CLK), .CE(E), .D(\samps_hi_r[0]_i_1_n_0 ), .Q(Q[0]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[10] (.C(CLK), .CE(E), .D(\samps_hi_r[10]_i_1_n_0 ), .Q(Q[4]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[11] (.C(CLK), .CE(E), .D(\samps_hi_r[11]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[11] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[12] (.C(CLK), .CE(E), .D(\samps_hi_r[12]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[12] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[13] (.C(CLK), .CE(E), .D(\samps_hi_r[13]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[13] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[14] (.C(CLK), .CE(E), .D(\samps_hi_r[14]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[14] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[15] (.C(CLK), .CE(E), .D(\samps_hi_r[15]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[15] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[16] (.C(CLK), .CE(E), .D(\samps_hi_r[16]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[16] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[17] (.C(CLK), .CE(E), .D(\samps_hi_r[17]_i_1_n_0 ), .Q(samps_hi), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[1] (.C(CLK), .CE(E), .D(\samps_hi_r[1]_i_1_n_0 ), .Q(Q[1]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[2] (.C(CLK), .CE(E), .D(\samps_hi_r[2]_i_1_n_0 ), .Q(Q[2]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[3] (.C(CLK), .CE(E), .D(\samps_hi_r[3]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[4] (.C(CLK), .CE(E), .D(\samps_hi_r[4]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[5] (.C(CLK), .CE(E), .D(\samps_hi_r[5]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[6] (.C(CLK), .CE(E), .D(\samps_hi_r[6]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[7] (.C(CLK), .CE(E), .D(\samps_hi_r[7]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[8] (.C(CLK), .CE(E), .D(\samps_hi_r[8]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) \samps_hi_r_reg[9] (.C(CLK), .CE(E), .D(\samps_hi_r[9]_i_1_n_0 ), .Q(Q[3]), .R(rstdiv0_sync_r1_reg_rep__0)); CARRY4 samps_one_r0_carry (.CI(1'b0), .CO({samps_one_r0_carry_n_0,samps_one_r0_carry_n_1,samps_one_r0_carry_n_2,samps_one_r0_carry_n_3}), .CYINIT(1'b1), .DI({samps_one_r0_carry_i_1_n_0,\samps_hi_r_reg_n_0_[5] ,samps_one_r0_carry_i_2_n_0,samps_one_r0_carry_i_3_n_0}), .O(NLW_samps_one_r0_carry_O_UNCONNECTED[3:0]), .S({samps_one_r0_carry_i_4_n_0,samps_one_r0_carry_i_5_n_0,samps_one_r0_carry_i_6_n_0,samps_one_r0_carry_i_7_n_0})); CARRY4 samps_one_r0_carry__0 (.CI(samps_one_r0_carry_n_0), .CO({samps_one_r0_carry__0_n_0,samps_one_r0_carry__0_n_1,samps_one_r0_carry__0_n_2,samps_one_r0_carry__0_n_3}), .CYINIT(1'b0), .DI({samps_one_r0_carry__0_i_1_n_0,samps_one_r0_carry__0_i_2_n_0,samps_one_r0_carry__0_i_3_n_0,Q[3]}), .O(NLW_samps_one_r0_carry__0_O_UNCONNECTED[3:0]), .S({samps_one_r0_carry__0_i_4_n_0,samps_one_r0_carry__0_i_5_n_0,samps_one_r0_carry__0_i_6_n_0,samps_one_r0_carry__0_i_7_n_0})); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__0_i_1 (.I0(\samps_hi_r_reg_n_0_[15] ), .I1(\samps_hi_r_reg_n_0_[14] ), .O(samps_one_r0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__0_i_2 (.I0(\samps_hi_r_reg_n_0_[13] ), .I1(\samps_hi_r_reg_n_0_[12] ), .O(samps_one_r0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__0_i_3 (.I0(\samps_hi_r_reg_n_0_[11] ), .I1(Q[4]), .O(samps_one_r0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__0_i_4 (.I0(\samps_hi_r_reg_n_0_[14] ), .I1(\samps_hi_r_reg_n_0_[15] ), .O(samps_one_r0_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__0_i_5 (.I0(\samps_hi_r_reg_n_0_[12] ), .I1(\samps_hi_r_reg_n_0_[13] ), .O(samps_one_r0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__0_i_6 (.I0(Q[4]), .I1(\samps_hi_r_reg_n_0_[11] ), .O(samps_one_r0_carry__0_i_6_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry__0_i_7 (.I0(\samps_hi_r_reg_n_0_[8] ), .I1(Q[3]), .O(samps_one_r0_carry__0_i_7_n_0)); CARRY4 samps_one_r0_carry__1 (.CI(samps_one_r0_carry__0_n_0), .CO({NLW_samps_one_r0_carry__1_CO_UNCONNECTED[3:1],samps_one_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_1_n_0}), .O(NLW_samps_one_r0_carry__1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_2_n_0})); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__1_i_1 (.I0(samps_hi), .I1(\samps_hi_r_reg_n_0_[16] ), .O(samps_one_r0_carry__1_i_1_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__1_i_2 (.I0(\samps_hi_r_reg_n_0_[16] ), .I1(samps_hi), .O(samps_one_r0_carry__1_i_2_n_0)); LUT2 #( .INIT(4'h8)) samps_one_r0_carry_i_1 (.I0(\samps_hi_r_reg_n_0_[7] ), .I1(\samps_hi_r_reg_n_0_[6] ), .O(samps_one_r0_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) samps_one_r0_carry_i_2 (.I0(\samps_hi_r_reg_n_0_[3] ), .I1(Q[2]), .O(samps_one_r0_carry_i_2_n_0)); LUT2 #( .INIT(4'h8)) samps_one_r0_carry_i_3 (.I0(Q[0]), .I1(Q[1]), .O(samps_one_r0_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_4 (.I0(\samps_hi_r_reg_n_0_[7] ), .I1(\samps_hi_r_reg_n_0_[6] ), .O(samps_one_r0_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_5 (.I0(\samps_hi_r_reg_n_0_[4] ), .I1(\samps_hi_r_reg_n_0_[5] ), .O(samps_one_r0_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_6 (.I0(\samps_hi_r_reg_n_0_[3] ), .I1(Q[2]), .O(samps_one_r0_carry_i_6_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_7 (.I0(Q[1]), .I1(Q[0]), .O(samps_one_r0_carry_i_7_n_0)); FDRE #( .INIT(1'b0)) samps_one_r_reg (.C(CLK), .CE(1'b1), .D(samps_one_ns), .Q(\run_r_reg[0]_2 ), .R(1'b0)); CARRY4 samps_zero_r0_carry (.CI(1'b0), .CO({samps_zero_r0_carry_n_0,samps_zero_r0_carry_n_1,samps_zero_r0_carry_n_2,samps_zero_r0_carry_n_3}), .CYINIT(1'b1), .DI({samps_zero_r0_carry_i_1_n_0,samps_lo[2],samps_zero_r0_carry_i_3_n_0,samps_zero_r0_carry_i_4_n_0}), .O(NLW_samps_zero_r0_carry_O_UNCONNECTED[3:0]), .S({samps_zero_r0_carry_i_5_n_0,samps_zero_r0_carry_i_6_n_0,samps_zero_r0_carry_i_7_n_0,samps_zero_r0_carry_i_8_n_0})); CARRY4 samps_zero_r0_carry__0 (.CI(samps_zero_r0_carry_n_0), .CO({samps_zero_r0_carry__0_n_0,samps_zero_r0_carry__0_n_1,samps_zero_r0_carry__0_n_2,samps_zero_r0_carry__0_n_3}), .CYINIT(1'b0), .DI({samps_zero_r0_carry__0_i_1_n_0,samps_zero_r0_carry__0_i_2_n_0,samps_zero_r0_carry__0_i_3_n_0,samps_lo[6]}), .O(NLW_samps_zero_r0_carry__0_O_UNCONNECTED[3:0]), .S({samps_zero_r0_carry__0_i_5_n_0,samps_zero_r0_carry__0_i_6_n_0,samps_zero_r0_carry__0_i_7_n_0,samps_zero_r0_carry__0_i_8_n_0})); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__0_i_1 (.I0(samps_lo[12]), .I1(samps_lo[11]), .O(samps_zero_r0_carry__0_i_1_n_0)); LUT1 #( .INIT(2'h2)) samps_zero_r0_carry__0_i_11 (.I0(Q[3]), .O(samps_zero_r_reg_0[3])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_12 (.I0(\samps_hi_r_reg_n_0_[8] ), .O(samps_zero_r_reg_0[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_13 (.I0(\samps_hi_r_reg_n_0_[7] ), .O(samps_zero_r_reg_0[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_14 (.I0(\samps_hi_r_reg_n_0_[6] ), .O(samps_zero_r_reg_0[0])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_15 (.I0(samps_hi), .O(samps_zero_r_reg_1[3])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_16 (.I0(\samps_hi_r_reg_n_0_[16] ), .O(samps_zero_r_reg_1[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_17 (.I0(\samps_hi_r_reg_n_0_[15] ), .O(samps_zero_r_reg_1[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_18 (.I0(\samps_hi_r_reg_n_0_[14] ), .O(samps_zero_r_reg_1[0])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_19 (.I0(Q[3]), .O(samps_zero_r_reg_5)); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__0_i_2 (.I0(samps_lo[10]), .I1(samps_lo[9]), .O(samps_zero_r0_carry__0_i_2_n_0)); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_20 (.I0(\samps_hi_r_reg_n_0_[13] ), .O(samps_zero_r_reg_2[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_21 (.I0(\samps_hi_r_reg_n_0_[12] ), .O(samps_zero_r_reg_2[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_22 (.I0(\samps_hi_r_reg_n_0_[11] ), .O(samps_zero_r_reg_2[0])); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__0_i_3 (.I0(samps_lo[8]), .I1(samps_lo[7]), .O(samps_zero_r0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__0_i_5 (.I0(samps_lo[11]), .I1(samps_lo[12]), .O(samps_zero_r0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__0_i_6 (.I0(samps_lo[9]), .I1(samps_lo[10]), .O(samps_zero_r0_carry__0_i_6_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__0_i_7 (.I0(samps_lo[7]), .I1(samps_lo[8]), .O(samps_zero_r0_carry__0_i_7_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry__0_i_8 (.I0(samps_lo[5]), .I1(samps_lo[6]), .O(samps_zero_r0_carry__0_i_8_n_0)); CARRY4 samps_zero_r0_carry__1 (.CI(samps_zero_r0_carry__0_n_0), .CO({NLW_samps_zero_r0_carry__1_CO_UNCONNECTED[3:1],samps_zero_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_1_n_0}), .O(NLW_samps_zero_r0_carry__1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_2_n_0})); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__1_i_1 (.I0(samps_lo[14]), .I1(samps_lo[13]), .O(samps_zero_r0_carry__1_i_1_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__1_i_2 (.I0(samps_lo[13]), .I1(samps_lo[14]), .O(samps_zero_r0_carry__1_i_2_n_0)); LUT2 #( .INIT(4'h8)) samps_zero_r0_carry_i_1 (.I0(samps_lo[4]), .I1(samps_lo[3]), .O(samps_zero_r0_carry_i_1_n_0)); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_10 (.I0(\samps_hi_r_reg_n_0_[5] ), .O(samps_zero_r_reg_3[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_11 (.I0(\samps_hi_r_reg_n_0_[4] ), .O(samps_zero_r_reg_3[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_12 (.I0(\samps_hi_r_reg_n_0_[3] ), .O(samps_zero_r_reg_3[0])); LUT3 #( .INIT(8'h28)) samps_zero_r0_carry_i_3 (.I0(samps_lo[0]), .I1(Q[2]), .I2(Q[1]), .O(samps_zero_r0_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry_i_4 (.I0(Q[1]), .I1(Q[0]), .O(samps_zero_r0_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry_i_5 (.I0(samps_lo[4]), .I1(samps_lo[3]), .O(samps_zero_r0_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry_i_6 (.I0(samps_lo[1]), .I1(samps_lo[2]), .O(samps_zero_r0_carry_i_6_n_0)); LUT3 #( .INIT(8'h82)) samps_zero_r0_carry_i_7 (.I0(samps_lo[0]), .I1(Q[2]), .I2(Q[1]), .O(samps_zero_r0_carry_i_7_n_0)); LUT2 #( .INIT(4'h8)) samps_zero_r0_carry_i_8 (.I0(Q[0]), .I1(Q[1]), .O(samps_zero_r0_carry_i_8_n_0)); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_9 (.I0(Q[1]), .O(samps_zero_r_reg_4)); FDRE #( .INIT(1'b0)) samps_zero_r_reg (.C(CLK), .CE(1'b1), .D(samps_zero_ns), .Q(\run_r_reg[0]_1 ), .R(1'b0)); CARRY4 sm_ns0_carry (.CI(1'b0), .CO({sm_ns0_carry_n_0,sm_ns0_carry_n_1,sm_ns0_carry_n_2,sm_ns0_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_sm_ns0_carry_O_UNCONNECTED[3:0]), .S({sm_ns0_carry_i_1_n_0,sm_ns0_carry_i_2_n_0,sm_ns0_carry_i_3_n_0,sm_ns0_carry_i_4_n_0})); CARRY4 sm_ns0_carry__0 (.CI(sm_ns0_carry_n_0), .CO({NLW_sm_ns0_carry__0_CO_UNCONNECTED[3:2],sm_ns0_carry__0_n_2,sm_ns0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_sm_ns0_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,sm_ns0_carry__0_i_1_n_0,sm_ns0_carry__0_i_2_n_0})); LUT2 #( .INIT(4'h1)) sm_ns0_carry__0_i_1 (.I0(samp_cntr), .I1(\samp_cntr_r_reg_n_0_[15] ), .O(sm_ns0_carry__0_i_1_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry__0_i_2 (.I0(\samp_cntr_r_reg_n_0_[13] ), .I1(\samp_cntr_r_reg_n_0_[14] ), .I2(\samp_cntr_r_reg_n_0_[12] ), .O(sm_ns0_carry__0_i_2_n_0)); LUT3 #( .INIT(8'h04)) sm_ns0_carry_i_1 (.I0(\samp_cntr_r_reg_n_0_[11] ), .I1(\samp_cntr_r_reg_n_0_[9] ), .I2(\samp_cntr_r_reg_n_0_[10] ), .O(sm_ns0_carry_i_1_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry_i_2 (.I0(\samp_cntr_r_reg_n_0_[7] ), .I1(\samp_cntr_r_reg_n_0_[8] ), .I2(\samp_cntr_r_reg_n_0_[6] ), .O(sm_ns0_carry_i_2_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry_i_3 (.I0(\samp_cntr_r_reg_n_0_[4] ), .I1(\samp_cntr_r_reg_n_0_[5] ), .I2(\samp_cntr_r_reg_n_0_[3] ), .O(sm_ns0_carry_i_3_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry_i_4 (.I0(\samp_cntr_r_reg_n_0_[1] ), .I1(\samp_cntr_r_reg_n_0_[2] ), .I2(\samp_cntr_r_reg[0]_0 ), .O(sm_ns0_carry_i_4_n_0)); LUT6 #( .INIT(64'h000000002F2A2A2A)) \sm_r[0]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(psdone), .I2(\sm_r_reg[0]_0 ), .I3(\sm_r[0]_i_2_n_0 ), .I4(sm_ns0_carry__0_n_2), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\sm_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h0008)) \sm_r[0]_i_2 (.I0(poc_sample_pd), .I1(\samp_wait_r_reg[6]_0 ), .I2(\samp_wait_r_reg[7]_0 [5]), .I3(\samp_wait_r_reg[7]_0 [6]), .O(\sm_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair450" *) LUT4 #( .INIT(16'h007A)) \sm_r[1]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(psdone), .I2(\sm_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .O(\sm_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_r_reg[0] (.C(CLK), .CE(1'b1), .D(\sm_r[0]_i_1_n_0 ), .Q(\sm_r_reg[0]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \sm_r_reg[1] (.C(CLK), .CE(1'b1), .D(\sm_r[1]_i_1_n_0 ), .Q(\sm_r_reg[0]_1 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair449" *) LUT4 #( .INIT(16'h070F)) \tap_r[0]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [0]), .I3(\rise_lead_r_reg[5] [3]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair449" *) LUT5 #( .INIT(32'h07700FF0)) \tap_r[1]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [1]), .I3(\rise_lead_r_reg[5] [0]), .I4(\rise_lead_r_reg[5] [3]), .O(p_0_in[1])); LUT6 #( .INIT(64'h077070700FF0F0F0)) \tap_r[2]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [2]), .I3(\rise_lead_r_reg[5] [1]), .I4(\rise_lead_r_reg[5] [0]), .I5(\rise_lead_r_reg[5] [3]), .O(p_0_in[2])); LUT6 #( .INIT(64'h0770707070707070)) \tap_r[3]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [3]), .I3(\rise_lead_r_reg[5] [0]), .I4(\rise_lead_r_reg[5] [1]), .I5(\rise_lead_r_reg[5] [2]), .O(p_0_in[3])); LUT6 #( .INIT(64'h15557FFFC0000000)) \tap_r[4]_i_1 (.I0(\rise_lead_r_reg[5] [5]), .I1(\rise_lead_r_reg[5] [2]), .I2(\rise_lead_r_reg[5] [1]), .I3(\rise_lead_r_reg[5] [0]), .I4(\rise_lead_r_reg[5] [3]), .I5(\rise_lead_r_reg[5] [4]), .O(p_0_in[4])); LUT2 #( .INIT(4'h2)) \tap_r[5]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .O(\tap_r_reg[0]_0 )); LUT6 #( .INIT(64'h644444444CCCCCCC)) \tap_r[5]_i_2 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [2]), .I3(\rise_lead_r_reg[5] [1]), .I4(\rise_lead_r_reg[5] [0]), .I5(\rise_lead_r_reg[5] [3]), .O(p_0_in[5])); FDRE #( .INIT(1'b0)) \tap_r_reg[0] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[0]), .Q(\rise_lead_r_reg[5] [0]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \tap_r_reg[1] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[1]), .Q(\rise_lead_r_reg[5] [1]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \tap_r_reg[2] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[2]), .Q(\rise_lead_r_reg[5] [2]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \tap_r_reg[3] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[3]), .Q(\rise_lead_r_reg[5] [3]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \tap_r_reg[4] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[4]), .Q(\rise_lead_r_reg[5] [4]), .R(rstdiv0_sync_r1_reg_rep)); FDRE #( .INIT(1'b0)) \tap_r_reg[5] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[5]), .Q(\rise_lead_r_reg[5] [5]), .R(rstdiv0_sync_r1_reg_rep)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_top" *) module ddr3_ifmig_7series_v4_0_poc_top (detect_done_r_reg, \sm_r_reg[1] , poc_backup_r_reg, Q, \mmcm_init_lead_reg[5] , \qcntr_r_reg[0] , \prev_r_reg[0] , \prev_r_reg[0]_0 , CLK, rstdiv0_sync_r1_reg_rep__20, ocd_ktap_left_r_reg, ocd_ktap_right_r_reg, poc_sample_pd, use_noise_window, pd_out, \run_ends_r_reg[1] , ocd_ktap_left_r_reg_0, ocd_edge_detect_rdy_r_reg, psdone, rstdiv0_sync_r1_reg_rep, rstdiv0_sync_r1_reg_rep__0, ninety_offsets); output detect_done_r_reg; output \sm_r_reg[1] ; output poc_backup_r_reg; output [5:0]Q; output [5:0]\mmcm_init_lead_reg[5] ; output [0:0]\qcntr_r_reg[0] ; output \prev_r_reg[0] ; output \prev_r_reg[0]_0 ; input CLK; input rstdiv0_sync_r1_reg_rep__20; input ocd_ktap_left_r_reg; input ocd_ktap_right_r_reg; input poc_sample_pd; input use_noise_window; input pd_out; input \run_ends_r_reg[1] ; input ocd_ktap_left_r_reg_0; input ocd_edge_detect_rdy_r_reg; input psdone; input rstdiv0_sync_r1_reg_rep; input rstdiv0_sync_r1_reg_rep__0; input [1:0]ninety_offsets; wire CLK; wire [5:0]Q; wire center0_return1__0_carry__0_i_4_n_0; wire center0_return1__0_carry__0_i_5_n_0; wire center0_return1__0_carry__0_i_6_n_0; wire center0_return1__0_carry_i_4_n_0; wire center0_return1__0_carry_i_5_n_0; wire center0_return1__0_carry_i_6_n_0; wire center0_return1__1_carry__0_i_4_n_0; wire center0_return1__1_carry__0_i_5_n_0; wire center0_return1__1_carry_i_4_n_0; wire center0_return1__1_carry_i_5_n_0; wire center0_return1__1_carry_i_6_n_0; wire [7:4]center0_return3; wire \center_diff_r_reg[0]_i_2_n_0 ; wire center_return1__0_carry__0_i_2_n_0; wire center_return1__0_carry__0_i_3_n_0; wire center_return1__0_carry__0_i_4_n_0; wire center_return1__0_carry_i_1_n_0; wire center_return1__0_carry_i_2_n_0; wire center_return1__0_carry_i_3_n_0; wire center_return1__1_carry__0_i_2_n_0; wire center_return1__1_carry__0_i_3_n_0; wire center_return1__1_carry_i_1_n_0; wire center_return1__1_carry_i_2_n_0; wire center_return1__1_carry_i_3_n_0; wire [7:4]center_return3; wire detect_done_r_reg; wire [5:1]diff; wire [0:0]diff_ns00_in; wire diff_ns0_carry__0_i_1_n_0; wire diff_ns0_carry__0_i_2_n_0; wire diff_ns1_carry_i_1_n_0; wire diff_ns1_carry_i_2_n_0; wire diff_ns1_carry_i_3_n_0; wire diff_ns1_carry_i_4_n_0; wire diff_ns1_carry_i_5_n_0; wire diff_ns1_carry_i_6_n_0; wire diff_ns1_carry_i_7_n_0; wire [6:0]edge_center; wire \edge_diff_r_reg[0]_i_2_n_0 ; wire fall_lead_r0; wire i___10_n_0; wire i___11_n_0; wire i___12_n_0; wire i___13_n_0; wire i___14_n_0; wire i___15_n_0; wire i___16_n_0; wire i___17_n_0; wire i___18_n_0; wire i___18_rep_n_0; wire i___19_n_0; wire i___19_rep_n_0; wire i___20_n_0; wire i___20_rep__0_n_0; wire i___20_rep_n_0; wire i___21_n_0; wire i___21_rep_n_0; wire i___22_n_0; wire i___23_n_0; wire i___24_n_0; wire i___25_n_0; wire i___25_rep_n_0; wire i___26_n_0; wire i___26_rep__0_n_0; wire i___26_rep_n_0; wire i___27_n_0; wire i___28_n_0; wire i___29_n_0; wire i___30_n_0; wire i___31_n_0; wire i___32_n_0; wire i___33_n_0; wire i___34_n_0; wire i___34_rep_n_0; wire i___35_n_0; wire i___35_rep_n_0; wire i___36_n_0; wire i___36_rep__0_n_0; wire i___36_rep_n_0; wire i___37_n_0; wire i___38_n_0; wire i___38_rep_n_0; wire i___39_n_0; wire i___39_rep_n_0; wire i___40_n_0; wire i___41_n_0; wire i___42_n_0; wire i___43_n_0; wire i___44_n_0; wire i___45_n_0; wire i___46_n_0; wire i___47_n_0; wire i___47_rep_n_0; wire i___48_n_0; wire i___48_rep__0_n_0; wire i___48_rep_n_0; wire i___4_n_0; wire i___5_n_0; wire i___6_n_0; wire i___7_n_0; wire i___8_n_0; wire i___9_n_0; wire [5:0]\mmcm_init_lead_reg[5] ; wire [5:0]mod_sub1_return; wire [1:0]ninety_offsets; wire ocd_edge_detect_rdy_r_reg; wire ocd_ktap_left_r_reg; wire ocd_ktap_left_r_reg_0; wire ocd_ktap_right_r_reg; wire [5:1]offset0_return0; wire [5:1]offset_return0; wire [6:1]p_0_in1_in; wire pd_out; wire poc_backup_r_reg; wire poc_sample_pd; wire \prev_r_reg[0] ; wire \prev_r_reg[0]_0 ; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire [5:0]rise_lead_center_0; wire \rise_lead_center_offset_r[5]_i_2_n_0 ; wire [5:0]rise_lead_left_0; wire [5:0]rise_trail_center_0; wire \rise_trail_center_offset_r[5]_i_2_n_0 ; wire [5:0]rise_trail_left_0; wire \rise_trail_r_reg[3]_i_2_n_0 ; wire \rise_trail_r_reg[3]_i_2_n_1 ; wire \rise_trail_r_reg[3]_i_2_n_2 ; wire \rise_trail_r_reg[3]_i_2_n_3 ; wire \rise_trail_r_reg[5]_i_3_n_3 ; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire \run_ends_r_reg[1] ; wire run_polarity_held_r; wire [16:1]samp_cntr_ns0; wire \samp_cntr_r_reg[12]_i_2_n_0 ; wire \samp_cntr_r_reg[12]_i_2_n_1 ; wire \samp_cntr_r_reg[12]_i_2_n_2 ; wire \samp_cntr_r_reg[12]_i_2_n_3 ; wire \samp_cntr_r_reg[16]_i_2_n_1 ; wire \samp_cntr_r_reg[16]_i_2_n_2 ; wire \samp_cntr_r_reg[16]_i_2_n_3 ; wire \samp_cntr_r_reg[4]_i_2_n_0 ; wire \samp_cntr_r_reg[4]_i_2_n_1 ; wire \samp_cntr_r_reg[4]_i_2_n_2 ; wire \samp_cntr_r_reg[4]_i_2_n_3 ; wire \samp_cntr_r_reg[8]_i_2_n_0 ; wire \samp_cntr_r_reg[8]_i_2_n_1 ; wire \samp_cntr_r_reg[8]_i_2_n_2 ; wire \samp_cntr_r_reg[8]_i_2_n_3 ; wire [7:0]samp_wait_r; wire [17:0]samps_hi_ns0; wire \samps_hi_r[3]_i_6_n_0 ; wire \samps_hi_r_reg[11]_i_2_n_0 ; wire \samps_hi_r_reg[11]_i_2_n_1 ; wire \samps_hi_r_reg[11]_i_2_n_2 ; wire \samps_hi_r_reg[11]_i_2_n_3 ; wire \samps_hi_r_reg[15]_i_2_n_0 ; wire \samps_hi_r_reg[15]_i_2_n_1 ; wire \samps_hi_r_reg[15]_i_2_n_2 ; wire \samps_hi_r_reg[15]_i_2_n_3 ; wire \samps_hi_r_reg[17]_i_2_n_3 ; wire \samps_hi_r_reg[3]_i_2_n_0 ; wire \samps_hi_r_reg[3]_i_2_n_1 ; wire \samps_hi_r_reg[3]_i_2_n_2 ; wire \samps_hi_r_reg[3]_i_2_n_3 ; wire \samps_hi_r_reg[7]_i_2_n_0 ; wire \samps_hi_r_reg[7]_i_2_n_1 ; wire \samps_hi_r_reg[7]_i_2_n_2 ; wire \samps_hi_r_reg[7]_i_2_n_3 ; wire [17:3]samps_lo; wire samps_zero_r0_carry__0_i_10_n_0; wire samps_zero_r0_carry__0_i_10_n_1; wire samps_zero_r0_carry__0_i_10_n_2; wire samps_zero_r0_carry__0_i_10_n_3; wire samps_zero_r0_carry__0_i_4_n_0; wire samps_zero_r0_carry__0_i_4_n_1; wire samps_zero_r0_carry__0_i_4_n_2; wire samps_zero_r0_carry__0_i_4_n_3; wire samps_zero_r0_carry__0_i_9_n_1; wire samps_zero_r0_carry__0_i_9_n_2; wire samps_zero_r0_carry__0_i_9_n_3; wire samps_zero_r0_carry_i_2_n_0; wire samps_zero_r0_carry_i_2_n_1; wire samps_zero_r0_carry_i_2_n_2; wire samps_zero_r0_carry_i_2_n_3; wire \sm_r_reg[1] ; wire [5:0]trailing_edge; wire [5:0]trailing_edge0; wire [5:0]trailing_edge00_in; wire u_edge_left_n_0; wire u_edge_left_n_1; wire u_edge_left_n_15; wire u_edge_left_n_19; wire u_edge_left_n_2; wire u_edge_left_n_20; wire u_edge_left_n_21; wire u_edge_left_n_22; wire u_edge_left_n_23; wire u_edge_left_n_24; wire u_edge_left_n_25; wire u_edge_left_n_26; wire u_edge_left_n_27; wire u_edge_left_n_28; wire u_edge_left_n_29; wire u_edge_left_n_30; wire u_edge_left_n_31; wire u_edge_left_n_32; wire u_edge_left_n_33; wire u_edge_left_n_34; wire u_edge_right_n_21; wire u_edge_right_n_22; wire u_edge_right_n_23; wire u_edge_right_n_24; wire u_edge_right_n_25; wire u_edge_right_n_26; wire u_edge_right_n_27; wire u_edge_right_n_28; wire u_edge_right_n_29; wire u_edge_right_n_30; wire u_edge_right_n_31; wire u_edge_right_n_8; wire u_poc_meta_n_14; wire u_poc_meta_n_15; wire u_poc_meta_n_16; wire u_poc_meta_n_17; wire u_poc_meta_n_18; wire u_poc_meta_n_19; wire u_poc_meta_n_24; wire u_poc_meta_n_25; wire u_poc_meta_n_26; wire u_poc_meta_n_27; wire u_poc_meta_n_28; wire u_poc_meta_n_29; wire u_poc_meta_n_30; wire u_poc_meta_n_31; wire u_poc_meta_n_32; wire u_poc_meta_n_33; wire u_poc_meta_n_34; wire u_poc_meta_n_56; wire u_poc_meta_n_57; wire u_poc_meta_n_58; wire u_poc_meta_n_59; wire u_poc_meta_n_60; wire u_poc_meta_n_61; wire u_poc_meta_n_62; wire u_poc_meta_n_63; wire u_poc_tap_base_n_0; wire u_poc_tap_base_n_1; wire u_poc_tap_base_n_10; wire u_poc_tap_base_n_11; wire u_poc_tap_base_n_12; wire u_poc_tap_base_n_13; wire u_poc_tap_base_n_14; wire u_poc_tap_base_n_15; wire u_poc_tap_base_n_16; wire u_poc_tap_base_n_17; wire u_poc_tap_base_n_18; wire u_poc_tap_base_n_19; wire u_poc_tap_base_n_2; wire u_poc_tap_base_n_20; wire u_poc_tap_base_n_21; wire u_poc_tap_base_n_22; wire u_poc_tap_base_n_23; wire u_poc_tap_base_n_24; wire u_poc_tap_base_n_25; wire u_poc_tap_base_n_26; wire u_poc_tap_base_n_27; wire u_poc_tap_base_n_28; wire u_poc_tap_base_n_29; wire u_poc_tap_base_n_3; wire u_poc_tap_base_n_30; wire u_poc_tap_base_n_31; wire u_poc_tap_base_n_32; wire u_poc_tap_base_n_33; wire u_poc_tap_base_n_34; wire u_poc_tap_base_n_35; wire u_poc_tap_base_n_36; wire u_poc_tap_base_n_37; wire u_poc_tap_base_n_38; wire u_poc_tap_base_n_39; wire u_poc_tap_base_n_4; wire u_poc_tap_base_n_40; wire u_poc_tap_base_n_41; wire u_poc_tap_base_n_42; wire u_poc_tap_base_n_43; wire u_poc_tap_base_n_44; wire u_poc_tap_base_n_45; wire u_poc_tap_base_n_46; wire u_poc_tap_base_n_47; wire u_poc_tap_base_n_48; wire u_poc_tap_base_n_49; wire u_poc_tap_base_n_5; wire u_poc_tap_base_n_50; wire u_poc_tap_base_n_51; wire u_poc_tap_base_n_52; wire u_poc_tap_base_n_53; wire u_poc_tap_base_n_54; wire u_poc_tap_base_n_55; wire u_poc_tap_base_n_57; wire u_poc_tap_base_n_58; wire u_poc_tap_base_n_59; wire u_poc_tap_base_n_6; wire u_poc_tap_base_n_60; wire u_poc_tap_base_n_61; wire u_poc_tap_base_n_62; wire u_poc_tap_base_n_63; wire u_poc_tap_base_n_64; wire u_poc_tap_base_n_65; wire u_poc_tap_base_n_66; wire u_poc_tap_base_n_67; wire u_poc_tap_base_n_68; wire u_poc_tap_base_n_69; wire u_poc_tap_base_n_7; wire u_poc_tap_base_n_70; wire u_poc_tap_base_n_71; wire u_poc_tap_base_n_72; wire u_poc_tap_base_n_73; wire u_poc_tap_base_n_74; wire u_poc_tap_base_n_75; wire u_poc_tap_base_n_76; wire u_poc_tap_base_n_8; wire u_poc_tap_base_n_83; wire u_poc_tap_base_n_84; wire u_poc_tap_base_n_85; wire u_poc_tap_base_n_86; wire u_poc_tap_base_n_9; wire u_poc_tap_base_n_95; wire use_noise_window; wire [6:0]window_center; wire [3:1]\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED ; wire [3:2]\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED ; wire [3:3]\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED ; wire [3:1]\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED ; wire [3:2]\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED ; wire [3:3]NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED; wire [0:0]NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED; LUT6 #( .INIT(64'h1555FFFFEAAA0000)) center0_return1__0_carry__0_i_4 (.I0(center0_return3[7]), .I1(center0_return3[4]), .I2(center0_return3[5]), .I3(center0_return3[6]), .I4(u_poc_meta_n_60), .I5(center0_return1__0_carry__0_i_6_n_0), .O(center0_return1__0_carry__0_i_4_n_0)); LUT6 #( .INIT(64'hA999999956666666)) center0_return1__0_carry__0_i_5 (.I0(u_poc_meta_n_60), .I1(center0_return3[7]), .I2(center0_return3[4]), .I3(center0_return3[5]), .I4(center0_return3[6]), .I5(u_edge_left_n_1), .O(center0_return1__0_carry__0_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry__0_i_6 (.I0(rise_trail_left_0[4]), .I1(use_noise_window), .I2(rise_lead_left_0[4]), .I3(u_poc_meta_n_59), .O(center0_return1__0_carry__0_i_6_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry_i_4 (.I0(rise_trail_left_0[2]), .I1(use_noise_window), .I2(rise_lead_left_0[2]), .I3(u_poc_meta_n_61), .O(center0_return1__0_carry_i_4_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry_i_5 (.I0(rise_trail_left_0[1]), .I1(use_noise_window), .I2(rise_lead_left_0[1]), .I3(u_poc_meta_n_62), .O(center0_return1__0_carry_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry_i_6 (.I0(rise_trail_left_0[0]), .I1(use_noise_window), .I2(rise_lead_left_0[0]), .I3(u_poc_meta_n_63), .O(center0_return1__0_carry_i_6_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry__0_i_4 (.I0(rise_trail_left_0[4]), .I1(use_noise_window), .I2(rise_lead_left_0[4]), .I3(u_poc_meta_n_59), .O(center0_return1__1_carry__0_i_4_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry__0_i_5 (.I0(rise_trail_left_0[3]), .I1(use_noise_window), .I2(rise_lead_left_0[3]), .I3(u_poc_meta_n_60), .O(center0_return1__1_carry__0_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry_i_4 (.I0(rise_trail_left_0[2]), .I1(use_noise_window), .I2(rise_lead_left_0[2]), .I3(u_poc_meta_n_61), .O(center0_return1__1_carry_i_4_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry_i_5 (.I0(rise_trail_left_0[1]), .I1(use_noise_window), .I2(rise_lead_left_0[1]), .I3(u_poc_meta_n_62), .O(center0_return1__1_carry_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry_i_6 (.I0(rise_trail_left_0[0]), .I1(use_noise_window), .I2(rise_lead_left_0[0]), .I3(u_poc_meta_n_63), .O(center0_return1__1_carry_i_6_n_0)); LUT1 #( .INIT(2'h1)) \center_diff_r_reg[0]_i_2 (.I0(i___20_n_0), .O(\center_diff_r_reg[0]_i_2_n_0 )); LUT6 #( .INIT(64'h007FFFFFFF800000)) center_return1__0_carry__0_i_2 (.I0(center_return3[5]), .I1(center_return3[4]), .I2(center_return3[6]), .I3(center_return3[7]), .I4(diff[4]), .I5(center_return1__0_carry__0_i_4_n_0), .O(center_return1__0_carry__0_i_2_n_0)); LUT6 #( .INIT(64'hAAAA955555556AAA)) center_return1__0_carry__0_i_3 (.I0(diff[4]), .I1(center_return3[5]), .I2(center_return3[4]), .I3(center_return3[6]), .I4(center_return3[7]), .I5(p_0_in1_in[4]), .O(center_return1__0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry__0_i_4 (.I0(p_0_in1_in[5]), .I1(diff[5]), .O(center_return1__0_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry_i_1 (.I0(p_0_in1_in[3]), .I1(diff[3]), .O(center_return1__0_carry_i_1_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry_i_2 (.I0(p_0_in1_in[2]), .I1(diff[2]), .O(center_return1__0_carry_i_2_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry_i_3 (.I0(p_0_in1_in[1]), .I1(diff[1]), .O(center_return1__0_carry_i_3_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry__0_i_2 (.I0(p_0_in1_in[5]), .I1(diff[5]), .O(center_return1__1_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry__0_i_3 (.I0(p_0_in1_in[4]), .I1(diff[4]), .O(center_return1__1_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry_i_1 (.I0(p_0_in1_in[3]), .I1(diff[3]), .O(center_return1__1_carry_i_1_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry_i_2 (.I0(p_0_in1_in[2]), .I1(diff[2]), .O(center_return1__1_carry_i_2_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry_i_3 (.I0(p_0_in1_in[1]), .I1(diff[1]), .O(center_return1__1_carry_i_3_n_0)); LUT2 #( .INIT(4'h6)) diff_ns0_carry__0_i_1 (.I0(window_center[5]), .I1(edge_center[5]), .O(diff_ns0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h6)) diff_ns0_carry__0_i_2 (.I0(edge_center[4]), .I1(window_center[4]), .O(diff_ns0_carry__0_i_2_n_0)); LUT4 #( .INIT(16'h2F02)) diff_ns1_carry_i_1 (.I0(edge_center[4]), .I1(window_center[4]), .I2(window_center[5]), .I3(edge_center[5]), .O(diff_ns1_carry_i_1_n_0)); LUT4 #( .INIT(16'h2F02)) diff_ns1_carry_i_2 (.I0(edge_center[2]), .I1(window_center[2]), .I2(window_center[3]), .I3(edge_center[3]), .O(diff_ns1_carry_i_2_n_0)); LUT4 #( .INIT(16'h2F02)) diff_ns1_carry_i_3 (.I0(edge_center[0]), .I1(window_center[0]), .I2(window_center[1]), .I3(edge_center[1]), .O(diff_ns1_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) diff_ns1_carry_i_4 (.I0(window_center[6]), .I1(edge_center[6]), .O(diff_ns1_carry_i_4_n_0)); LUT4 #( .INIT(16'h9009)) diff_ns1_carry_i_5 (.I0(edge_center[4]), .I1(window_center[4]), .I2(edge_center[5]), .I3(window_center[5]), .O(diff_ns1_carry_i_5_n_0)); LUT4 #( .INIT(16'h9009)) diff_ns1_carry_i_6 (.I0(edge_center[2]), .I1(window_center[2]), .I2(edge_center[3]), .I3(window_center[3]), .O(diff_ns1_carry_i_6_n_0)); LUT4 #( .INIT(16'h9009)) diff_ns1_carry_i_7 (.I0(edge_center[0]), .I1(window_center[0]), .I2(edge_center[1]), .I3(window_center[1]), .O(diff_ns1_carry_i_7_n_0)); LUT1 #( .INIT(2'h1)) \diff_r_reg[0]_i_2 (.I0(i___48_n_0), .O(diff_ns00_in)); LUT1 #( .INIT(2'h1)) \edge_diff_r_reg[0]_i_2 (.I0(i___36_n_0), .O(\edge_diff_r_reg[0]_i_2_n_0 )); LUT5 #( .INIT(32'hFFF8888F)) i___10 (.I0(u_poc_tap_base_n_55), .I1(u_poc_tap_base_n_54), .I2(samp_wait_r[0]), .I3(samp_wait_r[1]), .I4(samp_wait_r[2]), .O(i___10_n_0)); LUT6 #( .INIT(64'hFFFFFFF88888888F)) i___11 (.I0(u_poc_tap_base_n_55), .I1(u_poc_tap_base_n_54), .I2(samp_wait_r[2]), .I3(samp_wait_r[1]), .I4(samp_wait_r[0]), .I5(samp_wait_r[3]), .O(i___11_n_0)); LUT6 #( .INIT(64'h5555555500000040)) i___12 (.I0(u_poc_tap_base_n_54), .I1(poc_sample_pd), .I2(u_poc_tap_base_n_86), .I3(samp_wait_r[6]), .I4(samp_wait_r[7]), .I5(u_poc_tap_base_n_55), .O(i___12_n_0)); LUT5 #( .INIT(32'h00000001)) i___13 (.I0(samp_wait_r[4]), .I1(samp_wait_r[2]), .I2(samp_wait_r[1]), .I3(samp_wait_r[0]), .I4(samp_wait_r[3]), .O(i___13_n_0)); LUT5 #( .INIT(32'hA8888888)) i___14 (.I0(diff[4]), .I1(center_return3[7]), .I2(center_return3[6]), .I3(center_return3[4]), .I4(center_return3[5]), .O(i___14_n_0)); LUT6 #( .INIT(64'h478B74B8B8748B47)) i___15 (.I0(rise_lead_left_0[4]), .I1(use_noise_window), .I2(rise_trail_left_0[4]), .I3(Q[4]), .I4(\mmcm_init_lead_reg[5] [4]), .I5(u_edge_left_n_1), .O(i___15_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___16 (.I0(\mmcm_init_lead_reg[5] [4]), .I1(Q[4]), .I2(rise_trail_left_0[4]), .I3(use_noise_window), .I4(rise_lead_left_0[4]), .O(i___16_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___17 (.I0(\mmcm_init_lead_reg[5] [3]), .I1(Q[3]), .I2(rise_trail_left_0[3]), .I3(use_noise_window), .I4(rise_lead_left_0[3]), .O(i___17_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___18 (.I0(\mmcm_init_lead_reg[5] [2]), .I1(Q[2]), .I2(rise_trail_left_0[2]), .I3(use_noise_window), .I4(rise_lead_left_0[2]), .O(i___18_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___18_rep (.I0(\mmcm_init_lead_reg[5] [2]), .I1(Q[2]), .I2(rise_trail_left_0[2]), .I3(use_noise_window), .I4(rise_lead_left_0[2]), .O(i___18_rep_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___19 (.I0(\mmcm_init_lead_reg[5] [1]), .I1(Q[1]), .I2(rise_trail_left_0[1]), .I3(use_noise_window), .I4(rise_lead_left_0[1]), .O(i___19_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___19_rep (.I0(\mmcm_init_lead_reg[5] [1]), .I1(Q[1]), .I2(rise_trail_left_0[1]), .I3(use_noise_window), .I4(rise_lead_left_0[1]), .O(i___19_rep_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___20 (.I0(\mmcm_init_lead_reg[5] [0]), .I1(Q[0]), .I2(rise_trail_left_0[0]), .I3(use_noise_window), .I4(rise_lead_left_0[0]), .O(i___20_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___20_rep (.I0(\mmcm_init_lead_reg[5] [0]), .I1(Q[0]), .I2(rise_trail_left_0[0]), .I3(use_noise_window), .I4(rise_lead_left_0[0]), .O(i___20_rep_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___20_rep__0 (.I0(\mmcm_init_lead_reg[5] [0]), .I1(Q[0]), .I2(rise_trail_left_0[0]), .I3(use_noise_window), .I4(rise_lead_left_0[0]), .O(i___20_rep__0_n_0)); LUT2 #( .INIT(4'h9)) i___21 (.I0(u_poc_tap_base_n_60), .I1(u_poc_tap_base_n_49), .O(i___21_n_0)); LUT2 #( .INIT(4'h9)) i___21_rep (.I0(u_poc_tap_base_n_60), .I1(u_poc_tap_base_n_49), .O(i___21_rep_n_0)); LUT2 #( .INIT(4'h9)) i___22 (.I0(u_poc_tap_base_n_59), .I1(u_poc_tap_base_n_48), .O(i___22_n_0)); LUT3 #( .INIT(8'h69)) i___23 (.I0(u_poc_tap_base_n_47), .I1(u_poc_tap_base_n_58), .I2(u_poc_tap_base_n_48), .O(i___23_n_0)); LUT2 #( .INIT(4'h9)) i___24 (.I0(u_poc_tap_base_n_58), .I1(u_poc_tap_base_n_47), .O(i___24_n_0)); LUT2 #( .INIT(4'h9)) i___25 (.I0(u_poc_tap_base_n_61), .I1(u_poc_tap_base_n_50), .O(i___25_n_0)); LUT2 #( .INIT(4'h9)) i___25_rep (.I0(u_poc_tap_base_n_61), .I1(u_poc_tap_base_n_50), .O(i___25_rep_n_0)); (* SOFT_HLUTNM = "soft_lutpair475" *) LUT2 #( .INIT(4'h9)) i___26 (.I0(u_poc_tap_base_n_62), .I1(u_poc_tap_base_n_51), .O(i___26_n_0)); LUT2 #( .INIT(4'h9)) i___26_rep (.I0(u_poc_tap_base_n_62), .I1(u_poc_tap_base_n_51), .O(i___26_rep_n_0)); LUT2 #( .INIT(4'h9)) i___26_rep__0 (.I0(u_poc_tap_base_n_62), .I1(u_poc_tap_base_n_51), .O(i___26_rep__0_n_0)); LUT2 #( .INIT(4'h6)) i___27 (.I0(u_poc_tap_base_n_7), .I1(u_poc_tap_base_n_6), .O(i___27_n_0)); LUT2 #( .INIT(4'h6)) i___28 (.I0(u_poc_tap_base_n_5), .I1(u_poc_tap_base_n_4), .O(i___28_n_0)); LUT4 #( .INIT(16'hD22D)) i___29 (.I0(p_0_in1_in[5]), .I1(u_poc_meta_n_15), .I2(p_0_in1_in[6]), .I3(u_poc_meta_n_14), .O(i___29_n_0)); LUT2 #( .INIT(4'h9)) i___30 (.I0(u_poc_meta_n_14), .I1(p_0_in1_in[6]), .O(i___30_n_0)); LUT3 #( .INIT(8'h69)) i___31 (.I0(p_0_in1_in[5]), .I1(u_poc_meta_n_15), .I2(p_0_in1_in[4]), .O(i___31_n_0)); LUT2 #( .INIT(4'h9)) i___32 (.I0(u_poc_meta_n_15), .I1(p_0_in1_in[5]), .O(i___32_n_0)); LUT2 #( .INIT(4'h9)) i___33 (.I0(u_poc_meta_n_16), .I1(p_0_in1_in[4]), .O(i___33_n_0)); LUT2 #( .INIT(4'h9)) i___34 (.I0(u_poc_meta_n_17), .I1(p_0_in1_in[3]), .O(i___34_n_0)); LUT2 #( .INIT(4'h9)) i___34_rep (.I0(u_poc_meta_n_17), .I1(p_0_in1_in[3]), .O(i___34_rep_n_0)); LUT2 #( .INIT(4'h9)) i___35 (.I0(u_poc_meta_n_18), .I1(p_0_in1_in[2]), .O(i___35_n_0)); LUT2 #( .INIT(4'h9)) i___35_rep (.I0(u_poc_meta_n_18), .I1(p_0_in1_in[2]), .O(i___35_rep_n_0)); LUT2 #( .INIT(4'h9)) i___36 (.I0(u_poc_meta_n_19), .I1(p_0_in1_in[1]), .O(i___36_n_0)); LUT2 #( .INIT(4'h9)) i___36_rep (.I0(u_poc_meta_n_19), .I1(p_0_in1_in[1]), .O(i___36_rep_n_0)); LUT2 #( .INIT(4'h9)) i___36_rep__0 (.I0(u_poc_meta_n_19), .I1(p_0_in1_in[1]), .O(i___36_rep__0_n_0)); LUT4 #( .INIT(16'hD22D)) i___37 (.I0(window_center[5]), .I1(edge_center[5]), .I2(window_center[6]), .I3(edge_center[6]), .O(i___37_n_0)); LUT2 #( .INIT(4'h9)) i___38 (.I0(edge_center[2]), .I1(window_center[2]), .O(i___38_n_0)); LUT2 #( .INIT(4'h9)) i___38_rep (.I0(edge_center[2]), .I1(window_center[2]), .O(i___38_rep_n_0)); LUT2 #( .INIT(4'h9)) i___39 (.I0(edge_center[1]), .I1(window_center[1]), .O(i___39_n_0)); LUT2 #( .INIT(4'h9)) i___39_rep (.I0(edge_center[1]), .I1(window_center[1]), .O(i___39_rep_n_0)); LUT6 #( .INIT(64'hFFFFCFFF00008800)) i___4 (.I0(u_poc_tap_base_n_2), .I1(u_poc_tap_base_n_0), .I2(u_poc_tap_base_n_3), .I3(u_poc_tap_base_n_46), .I4(rstdiv0_sync_r1_reg_rep__20), .I5(run_polarity_held_r), .O(i___4_n_0)); LUT2 #( .INIT(4'h2)) i___40 (.I0(window_center[6]), .I1(edge_center[6]), .O(i___40_n_0)); LUT2 #( .INIT(4'h9)) i___41 (.I0(edge_center[6]), .I1(window_center[6]), .O(i___41_n_0)); LUT2 #( .INIT(4'h2)) i___42 (.I0(edge_center[6]), .I1(window_center[6]), .O(i___42_n_0)); LUT3 #( .INIT(8'h69)) i___43 (.I0(window_center[5]), .I1(edge_center[5]), .I2(window_center[4]), .O(i___43_n_0)); LUT2 #( .INIT(4'h9)) i___44 (.I0(edge_center[5]), .I1(window_center[5]), .O(i___44_n_0)); LUT2 #( .INIT(4'hB)) i___45 (.I0(edge_center[5]), .I1(window_center[5]), .O(i___45_n_0)); LUT2 #( .INIT(4'h9)) i___46 (.I0(edge_center[4]), .I1(window_center[4]), .O(i___46_n_0)); LUT2 #( .INIT(4'h9)) i___47 (.I0(edge_center[3]), .I1(window_center[3]), .O(i___47_n_0)); LUT2 #( .INIT(4'h9)) i___47_rep (.I0(edge_center[3]), .I1(window_center[3]), .O(i___47_rep_n_0)); LUT2 #( .INIT(4'h9)) i___48 (.I0(edge_center[0]), .I1(window_center[0]), .O(i___48_n_0)); LUT2 #( .INIT(4'h9)) i___48_rep (.I0(edge_center[0]), .I1(window_center[0]), .O(i___48_rep_n_0)); LUT2 #( .INIT(4'h9)) i___48_rep__0 (.I0(edge_center[0]), .I1(window_center[0]), .O(i___48_rep__0_n_0)); LUT5 #( .INIT(32'h00400000)) i___5 (.I0(u_poc_tap_base_n_0), .I1(u_poc_tap_base_n_3), .I2(u_poc_tap_base_n_46), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_right_r_reg), .O(i___5_n_0)); LUT5 #( .INIT(32'h00400000)) i___6 (.I0(u_poc_tap_base_n_0), .I1(u_poc_tap_base_n_3), .I2(u_poc_tap_base_n_46), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_left_r_reg), .O(i___6_n_0)); LUT4 #( .INIT(16'h0004)) i___7 (.I0(u_poc_tap_base_n_0), .I1(u_poc_tap_base_n_52), .I2(ocd_ktap_left_r_reg), .I3(ocd_ktap_right_r_reg), .O(i___7_n_0)); LUT3 #( .INIT(8'h01)) i___8 (.I0(u_poc_meta_n_56), .I1(u_poc_meta_n_58), .I2(u_poc_meta_n_57), .O(i___8_n_0)); (* SOFT_HLUTNM = "soft_lutpair475" *) LUT4 #( .INIT(16'h7FFF)) i___9 (.I0(u_poc_tap_base_n_49), .I1(u_poc_tap_base_n_50), .I2(u_poc_tap_base_n_51), .I3(u_poc_tap_base_n_48), .O(i___9_n_0)); (* SOFT_HLUTNM = "soft_lutpair478" *) LUT2 #( .INIT(4'h6)) \rise_lead_center_offset_r[1]_i_1 (.I0(rise_lead_center_0[1]), .I1(ninety_offsets[0]), .O(offset_return0[1])); (* SOFT_HLUTNM = "soft_lutpair476" *) LUT4 #( .INIT(16'h4BB4)) \rise_lead_center_offset_r[2]_i_1 (.I0(rise_lead_center_0[1]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_lead_center_0[2]), .O(offset_return0[2])); LUT6 #( .INIT(64'h5A4969254969925A)) \rise_lead_center_offset_r[3]_i_1 (.I0(rise_lead_center_0[3]), .I1(rise_lead_center_0[5]), .I2(\rise_lead_center_offset_r[5]_i_2_n_0 ), .I3(rise_lead_center_0[4]), .I4(ninety_offsets[1]), .I5(ninety_offsets[0]), .O(offset_return0[3])); LUT6 #( .INIT(64'h998564666466621A)) \rise_lead_center_offset_r[4]_i_1 (.I0(rise_lead_center_0[4]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_lead_center_0[5]), .I4(rise_lead_center_0[3]), .I5(\rise_lead_center_offset_r[5]_i_2_n_0 ), .O(offset_return0[4])); LUT6 #( .INIT(64'hF00E871887700EF0)) \rise_lead_center_offset_r[5]_i_1 (.I0(rise_lead_center_0[3]), .I1(\rise_lead_center_offset_r[5]_i_2_n_0 ), .I2(rise_lead_center_0[5]), .I3(ninety_offsets[1]), .I4(ninety_offsets[0]), .I5(rise_lead_center_0[4]), .O(offset_return0[5])); (* SOFT_HLUTNM = "soft_lutpair476" *) LUT4 #( .INIT(16'hE460)) \rise_lead_center_offset_r[5]_i_2 (.I0(ninety_offsets[1]), .I1(ninety_offsets[0]), .I2(rise_lead_center_0[2]), .I3(rise_lead_center_0[1]), .O(\rise_lead_center_offset_r[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair478" *) LUT2 #( .INIT(4'h6)) \rise_trail_center_offset_r[1]_i_1 (.I0(rise_trail_center_0[1]), .I1(ninety_offsets[0]), .O(offset0_return0[1])); (* SOFT_HLUTNM = "soft_lutpair477" *) LUT4 #( .INIT(16'h4BB4)) \rise_trail_center_offset_r[2]_i_1 (.I0(rise_trail_center_0[1]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_trail_center_0[2]), .O(offset0_return0[2])); LUT6 #( .INIT(64'h5A4969254969925A)) \rise_trail_center_offset_r[3]_i_1 (.I0(rise_trail_center_0[3]), .I1(rise_trail_center_0[5]), .I2(\rise_trail_center_offset_r[5]_i_2_n_0 ), .I3(rise_trail_center_0[4]), .I4(ninety_offsets[1]), .I5(ninety_offsets[0]), .O(offset0_return0[3])); LUT6 #( .INIT(64'h998564666466621A)) \rise_trail_center_offset_r[4]_i_1 (.I0(rise_trail_center_0[4]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_trail_center_0[5]), .I4(rise_trail_center_0[3]), .I5(\rise_trail_center_offset_r[5]_i_2_n_0 ), .O(offset0_return0[4])); LUT6 #( .INIT(64'hF00E871887700EF0)) \rise_trail_center_offset_r[5]_i_1 (.I0(rise_trail_center_0[3]), .I1(\rise_trail_center_offset_r[5]_i_2_n_0 ), .I2(rise_trail_center_0[5]), .I3(ninety_offsets[1]), .I4(ninety_offsets[0]), .I5(rise_trail_center_0[4]), .O(offset0_return0[5])); (* SOFT_HLUTNM = "soft_lutpair477" *) LUT4 #( .INIT(16'hE460)) \rise_trail_center_offset_r[5]_i_2 (.I0(ninety_offsets[1]), .I1(ninety_offsets[0]), .I2(rise_trail_center_0[2]), .I3(rise_trail_center_0[1]), .O(\rise_trail_center_offset_r[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \rise_trail_r_reg[0]_i_2 (.I0(i___26_n_0), .O(trailing_edge00_in[0])); CARRY4 \rise_trail_r_reg[3]_i_2 (.CI(1'b0), .CO({\rise_trail_r_reg[3]_i_2_n_0 ,\rise_trail_r_reg[3]_i_2_n_1 ,\rise_trail_r_reg[3]_i_2_n_2 ,\rise_trail_r_reg[3]_i_2_n_3 }), .CYINIT(1'b1), .DI({u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .O(trailing_edge0[3:0]), .S({i___22_n_0,i___21_rep_n_0,i___25_rep_n_0,i___26_rep_n_0})); CARRY4 \rise_trail_r_reg[5]_i_3 (.CI(\rise_trail_r_reg[3]_i_2_n_0 ), .CO({\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED [3:1],\rise_trail_r_reg[5]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_58}), .O({\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED [3:2],trailing_edge0[5:4]}), .S({1'b0,1'b0,u_poc_tap_base_n_84,i___24_n_0})); CARRY4 \samp_cntr_r_reg[12]_i_2 (.CI(\samp_cntr_r_reg[8]_i_2_n_0 ), .CO({\samp_cntr_r_reg[12]_i_2_n_0 ,\samp_cntr_r_reg[12]_i_2_n_1 ,\samp_cntr_r_reg[12]_i_2_n_2 ,\samp_cntr_r_reg[12]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[12:9]), .S({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20})); CARRY4 \samp_cntr_r_reg[16]_i_2 (.CI(\samp_cntr_r_reg[12]_i_2_n_0 ), .CO({\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED [3],\samp_cntr_r_reg[16]_i_2_n_1 ,\samp_cntr_r_reg[16]_i_2_n_2 ,\samp_cntr_r_reg[16]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[16:13]), .S({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24})); CARRY4 \samp_cntr_r_reg[4]_i_2 (.CI(1'b0), .CO({\samp_cntr_r_reg[4]_i_2_n_0 ,\samp_cntr_r_reg[4]_i_2_n_1 ,\samp_cntr_r_reg[4]_i_2_n_2 ,\samp_cntr_r_reg[4]_i_2_n_3 }), .CYINIT(u_poc_tap_base_n_76), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[4:1]), .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12})); CARRY4 \samp_cntr_r_reg[8]_i_2 (.CI(\samp_cntr_r_reg[4]_i_2_n_0 ), .CO({\samp_cntr_r_reg[8]_i_2_n_0 ,\samp_cntr_r_reg[8]_i_2_n_1 ,\samp_cntr_r_reg[8]_i_2_n_2 ,\samp_cntr_r_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[8:5]), .S({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16})); LUT2 #( .INIT(4'h6)) \samps_hi_r[3]_i_6 (.I0(u_poc_tap_base_n_8), .I1(pd_out), .O(\samps_hi_r[3]_i_6_n_0 )); CARRY4 \samps_hi_r_reg[11]_i_2 (.CI(\samps_hi_r_reg[7]_i_2_n_0 ), .CO({\samps_hi_r_reg[11]_i_2_n_0 ,\samps_hi_r_reg[11]_i_2_n_1 ,\samps_hi_r_reg[11]_i_2_n_2 ,\samps_hi_r_reg[11]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_hi_ns0[11:8]), .S({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35})); CARRY4 \samps_hi_r_reg[15]_i_2 (.CI(\samps_hi_r_reg[11]_i_2_n_0 ), .CO({\samps_hi_r_reg[15]_i_2_n_0 ,\samps_hi_r_reg[15]_i_2_n_1 ,\samps_hi_r_reg[15]_i_2_n_2 ,\samps_hi_r_reg[15]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_hi_ns0[15:12]), .S({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39})); CARRY4 \samps_hi_r_reg[17]_i_2 (.CI(\samps_hi_r_reg[15]_i_2_n_0 ), .CO({\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED [3:1],\samps_hi_r_reg[17]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED [3:2],samps_hi_ns0[17:16]}), .S({1'b0,1'b0,u_poc_tap_base_n_40,u_poc_tap_base_n_41})); CARRY4 \samps_hi_r_reg[3]_i_2 (.CI(1'b0), .CO({\samps_hi_r_reg[3]_i_2_n_0 ,\samps_hi_r_reg[3]_i_2_n_1 ,\samps_hi_r_reg[3]_i_2_n_2 ,\samps_hi_r_reg[3]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_8}), .O(samps_hi_ns0[3:0]), .S({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27,\samps_hi_r[3]_i_6_n_0 })); CARRY4 \samps_hi_r_reg[7]_i_2 (.CI(\samps_hi_r_reg[3]_i_2_n_0 ), .CO({\samps_hi_r_reg[7]_i_2_n_0 ,\samps_hi_r_reg[7]_i_2_n_1 ,\samps_hi_r_reg[7]_i_2_n_2 ,\samps_hi_r_reg[7]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_hi_ns0[7:4]), .S({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31})); CARRY4 samps_zero_r0_carry__0_i_10 (.CI(samps_zero_r0_carry__0_i_4_n_0), .CO({samps_zero_r0_carry__0_i_10_n_0,samps_zero_r0_carry__0_i_10_n_1,samps_zero_r0_carry__0_i_10_n_2,samps_zero_r0_carry__0_i_10_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_75}), .O(samps_lo[13:10]), .S({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70,i___28_n_0})); CARRY4 samps_zero_r0_carry__0_i_4 (.CI(samps_zero_r0_carry_i_2_n_0), .CO({samps_zero_r0_carry__0_i_4_n_0,samps_zero_r0_carry__0_i_4_n_1,samps_zero_r0_carry__0_i_4_n_2,samps_zero_r0_carry__0_i_4_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_lo[9:6]), .S({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45})); CARRY4 samps_zero_r0_carry__0_i_9 (.CI(samps_zero_r0_carry__0_i_10_n_0), .CO({NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED[3],samps_zero_r0_carry__0_i_9_n_1,samps_zero_r0_carry__0_i_9_n_2,samps_zero_r0_carry__0_i_9_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_lo[17:14]), .S({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67})); CARRY4 samps_zero_r0_carry_i_2 (.CI(1'b0), .CO({samps_zero_r0_carry_i_2_n_0,samps_zero_r0_carry_i_2_n_1,samps_zero_r0_carry_i_2_n_2,samps_zero_r0_carry_i_2_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_74}), .O({samps_lo[5:3],NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED[0]}), .S({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73,i___27_n_0})); ddr3_ifmig_7series_v4_0_poc_edge_store u_edge_center (.CLK(CLK), .D(trailing_edge), .E(i___7_n_0), .Q(rise_lead_center_0), .\rise_trail_center_offset_r_reg[3] (rise_trail_center_0), .run_polarity_r_reg(u_poc_tap_base_n_53), .\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62})); ddr3_ifmig_7series_v4_0_poc_edge_store_7 u_edge_left (.CLK(CLK), .D({mod_sub1_return[5:4],mod_sub1_return[0]}), .DI({u_edge_left_n_0,u_edge_left_n_1}), .E(i___6_n_0), .O(u_poc_meta_n_27), .Q({u_poc_meta_n_59,u_poc_meta_n_60}), .S(u_edge_left_n_15), .center0_return3(center0_return3), .\center_diff_r_reg[0] (u_edge_left_n_19), .\center_diff_r_reg[0]_0 (u_edge_left_n_20), .\center_diff_r_reg[0]_1 (u_edge_left_n_21), .\center_diff_r_reg[1] (u_edge_left_n_23), .\center_diff_r_reg[3] (u_edge_left_n_33), .\center_diff_r_reg[3]_0 (u_edge_left_n_34), .\center_diff_r_reg[5] (u_edge_left_n_2), .\center_diff_r_reg[5]_0 (u_edge_left_n_22), .\rise_lead_r_reg[0]_0 (\center_diff_r_reg[0]_i_2_n_0 ), .\rise_lead_r_reg[4]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}), .\rise_lead_r_reg[5]_0 ({\mmcm_init_lead_reg[5] [5:3],\mmcm_init_lead_reg[5] [0]}), .\rise_trail_r_reg[1]_0 (u_edge_right_n_27), .\rise_trail_r_reg[2]_0 (u_edge_right_n_26), .\rise_trail_r_reg[3]_0 (u_edge_right_n_8), .\rise_trail_r_reg[4]_0 ({u_poc_meta_n_33,u_poc_meta_n_34}), .\rise_trail_r_reg[5]_0 ({Q[5:3],Q[0]}), .samps_zero_r_reg(u_poc_tap_base_n_95), .\tap_r_reg[4] (trailing_edge), .\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .use_noise_window(use_noise_window), .\window_center_r_reg[0] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}), .\window_center_r_reg[3] ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}), .\window_center_r_reg[6] (rise_lead_left_0), .\window_center_r_reg[6]_0 (rise_trail_left_0), .\window_center_r_reg[6]_1 (u_edge_left_n_24), .\window_center_r_reg[6]_2 ({u_edge_left_n_31,u_edge_left_n_32})); ddr3_ifmig_7series_v4_0_poc_edge_store_8 u_edge_right (.CLK(CLK), .D(mod_sub1_return[3:1]), .DI(u_poc_tap_base_n_63), .E(i___5_n_0), .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26}), .Q(u_poc_tap_base_n_48), .S({u_poc_tap_base_n_85,i___21_n_0,i___25_n_0,i___26_rep__0_n_0}), .\center_diff_r_reg[0] (u_edge_right_n_26), .\center_diff_r_reg[0]_0 (u_edge_right_n_27), .\center_diff_r_reg[1] (u_edge_right_n_8), .\center_diff_r_reg[3] ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}), .\center_diff_r_reg[3]_0 ({u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}), .\center_diff_r_reg[5] (u_edge_right_n_21), .\center_diff_r_reg[5]_0 (u_edge_right_n_31), .\mmcm_init_lead_reg[5] (\mmcm_init_lead_reg[5] ), .\mmcm_init_trail_reg[5] (Q), .\rise_lead_r_reg[1]_0 (u_edge_left_n_20), .\rise_lead_r_reg[3]_0 (u_edge_left_n_1), .\rise_lead_r_reg[4]_0 (u_edge_left_n_21), .\rise_lead_r_reg[4]_1 (u_edge_left_n_23), .\rise_lead_r_reg[5]_0 (rise_lead_left_0[5]), .\rise_trail_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}), .\rise_trail_r_reg[5]_0 (u_edge_left_n_19), .\rise_trail_r_reg[5]_1 (rise_trail_left_0[5]), .samps_zero_r_reg(fall_lead_r0), .\tap_r_reg[4] (trailing_edge), .\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .\tap_r_reg[5]_0 ({u_poc_tap_base_n_83,i___23_n_0}), .trailing_edge00_in(trailing_edge00_in[5:1]), .use_noise_window(use_noise_window)); ddr3_ifmig_7series_v4_0_poc_meta u_poc_meta (.CLK(CLK), .D(mod_sub1_return), .DI(i___14_n_0), .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26,u_poc_meta_n_27}), .Q(p_0_in1_in), .S({center_return1__1_carry_i_1_n_0,center_return1__1_carry_i_2_n_0,center_return1__1_carry_i_3_n_0}), .center0_return3(center0_return3), .\center_diff_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}), .\center_diff_r_reg[4]_0 ({u_edge_left_n_0,u_edge_left_n_1}), .\center_diff_r_reg[5]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}), .\center_diff_r_reg[5]_1 ({u_poc_meta_n_33,u_poc_meta_n_34}), .center_return3(center_return3), .detect_done_r_reg(detect_done_r_reg), .\diff_r_reg[2]_0 (i___8_n_0), .\diff_r_reg[7]_0 (edge_center), .\diff_r_reg[7]_1 (window_center), .\edge_center_r_reg[0]_0 (diff_ns00_in), .\edge_center_r_reg[3]_0 ({i___47_rep_n_0,i___38_rep_n_0,i___39_rep_n_0,i___48_rep_n_0}), .\edge_center_r_reg[3]_1 ({i___47_n_0,i___38_n_0,i___39_n_0,i___48_rep__0_n_0}), .\edge_center_r_reg[5]_0 ({i___45_n_0,diff_ns0_carry__0_i_1_n_0}), .\edge_center_r_reg[6]_0 (diff), .\edge_center_r_reg[6]_1 ({i___42_n_0,diff_ns1_carry_i_1_n_0,diff_ns1_carry_i_2_n_0,diff_ns1_carry_i_3_n_0}), .\edge_center_r_reg[6]_2 ({i___41_n_0,i___44_n_0,i___46_n_0}), .\edge_diff_r_reg[0]_0 ({u_poc_meta_n_14,u_poc_meta_n_15,u_poc_meta_n_16,u_poc_meta_n_17,u_poc_meta_n_18,u_poc_meta_n_19}), .\edge_diff_r_reg[4]_0 ({center_return1__0_carry__0_i_2_n_0,center_return1__0_carry__0_i_3_n_0}), .ocd_edge_detect_rdy_r_reg(ocd_edge_detect_rdy_r_reg), .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg), .ocd_ktap_left_r_reg_0(ocd_ktap_left_r_reg_0), .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg), .poc_backup_r_reg_0(poc_backup_r_reg), .\prev_r_reg[0]_0 (\prev_r_reg[0] ), .\prev_r_reg[0]_1 (\prev_r_reg[0]_0 ), .\prev_r_reg[2]_0 ({u_poc_meta_n_56,u_poc_meta_n_57,u_poc_meta_n_58}), .\rise_lead_center_offset_r_reg[2]_0 ({center_return1__0_carry_i_1_n_0,center_return1__0_carry_i_2_n_0,center_return1__0_carry_i_3_n_0}), .\rise_lead_center_offset_r_reg[4]_0 ({center_return1__1_carry__0_i_2_n_0,center_return1__1_carry__0_i_3_n_0}), .\rise_lead_center_offset_r_reg[4]_1 ({i___29_n_0,i___31_n_0}), .\rise_lead_r_reg[2] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}), .\rise_lead_r_reg[2]_0 ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}), .\rise_lead_r_reg[3] ({u_edge_left_n_34,u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}), .\rise_lead_r_reg[3]_0 ({i___17_n_0,i___18_n_0,i___19_n_0,i___20_rep__0_n_0}), .\rise_lead_r_reg[3]_1 ({offset_return0,rise_lead_center_0[0]}), .\rise_lead_r_reg[4] ({u_edge_left_n_31,u_edge_left_n_32}), .\rise_lead_r_reg[4]_0 ({u_edge_left_n_15,center0_return1__0_carry__0_i_4_n_0,center0_return1__0_carry__0_i_5_n_0}), .\rise_lead_r_reg[4]_1 (u_edge_left_n_2), .\rise_lead_r_reg[4]_2 ({u_edge_left_n_22,i___15_n_0}), .\rise_lead_r_reg[5] ({u_edge_left_n_24,center0_return1__1_carry__0_i_4_n_0,center0_return1__1_carry__0_i_5_n_0}), .\rise_trail_center_offset_r_reg[0]_0 (\edge_diff_r_reg[0]_i_2_n_0 ), .\rise_trail_center_offset_r_reg[2]_0 ({i___34_rep_n_0,i___35_rep_n_0,i___36_rep_n_0}), .\rise_trail_center_offset_r_reg[3]_0 ({i___33_n_0,i___34_n_0,i___35_n_0,i___36_rep__0_n_0}), .\rise_trail_center_offset_r_reg[5]_0 ({i___30_n_0,i___32_n_0}), .\rise_trail_r_reg[2] ({center0_return1__1_carry_i_4_n_0,center0_return1__1_carry_i_5_n_0,center0_return1__1_carry_i_6_n_0}), .\rise_trail_r_reg[2]_0 ({center0_return1__0_carry_i_4_n_0,center0_return1__0_carry_i_5_n_0,center0_return1__0_carry_i_6_n_0}), .\rise_trail_r_reg[3] ({u_edge_left_n_33,i___18_rep_n_0,i___19_rep_n_0,i___20_rep_n_0}), .\rise_trail_r_reg[3]_0 ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}), .\rise_trail_r_reg[3]_1 ({offset0_return0,rise_trail_center_0[0]}), .\rise_trail_r_reg[4] (u_edge_right_n_31), .\rise_trail_r_reg[5] ({u_edge_right_n_21,i___16_n_0}), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\run_ends_r_reg[1]_0 (\run_ends_r_reg[1] ), .run_polarity_held_r(run_polarity_held_r), .run_too_small_r_reg(u_poc_tap_base_n_1), .samps_zero_r_reg(i___4_n_0), .samps_zero_r_reg_0(u_poc_tap_base_n_52), .\sm_r_reg[1] (\sm_r_reg[1] ), .\window_center_r_reg[6]_0 ({u_poc_meta_n_59,u_poc_meta_n_60,u_poc_meta_n_61,u_poc_meta_n_62,u_poc_meta_n_63}), .\window_center_r_reg[6]_1 ({diff_ns1_carry_i_4_n_0,diff_ns1_carry_i_5_n_0,diff_ns1_carry_i_6_n_0,diff_ns1_carry_i_7_n_0}), .\window_center_r_reg[6]_2 ({i___40_n_0,i___37_n_0,i___43_n_0,diff_ns0_carry__0_i_2_n_0})); ddr3_ifmig_7series_v4_0_poc_tap_base u_poc_tap_base (.CLK(CLK), .D({i___11_n_0,i___10_n_0}), .DI(u_poc_tap_base_n_63), .E(i___12_n_0), .Q({u_poc_tap_base_n_4,u_poc_tap_base_n_5,u_poc_tap_base_n_6,u_poc_tap_base_n_7,u_poc_tap_base_n_8}), .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12}), .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg), .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg), .poc_sample_pd(poc_sample_pd), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .\rise_lead_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .\rise_trail_r_reg[0] (u_poc_tap_base_n_53), .\rise_trail_r_reg[3] (u_poc_tap_base_n_85), .\rise_trail_r_reg[5] (trailing_edge), .\rise_trail_r_reg[5]_0 (u_poc_tap_base_n_83), .\rise_trail_r_reg[5]_1 (u_poc_tap_base_n_84), .\rise_trail_r_reg[5]_2 (fall_lead_r0), .\rise_trail_r_reg[5]_3 (u_poc_tap_base_n_95), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\run_r_reg[0]_0 (u_poc_tap_base_n_0), .\run_r_reg[0]_1 (u_poc_tap_base_n_2), .\run_r_reg[0]_2 (u_poc_tap_base_n_3), .\run_r_reg[2]_0 (i___9_n_0), .\run_r_reg[4]_0 ({u_poc_tap_base_n_47,u_poc_tap_base_n_48,u_poc_tap_base_n_49,u_poc_tap_base_n_50,u_poc_tap_base_n_51}), .run_too_small_r3_reg(u_poc_tap_base_n_1), .run_too_small_r_reg_0(u_poc_tap_base_n_52), .samp_cntr_ns0(samp_cntr_ns0), .\samp_cntr_r_reg[0]_0 (u_poc_tap_base_n_76), .\samp_cntr_r_reg[12]_0 ({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20}), .\samp_cntr_r_reg[16]_0 ({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24}), .\samp_cntr_r_reg[8]_0 ({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16}), .\samp_wait_r_reg[4]_0 (i___13_n_0), .\samp_wait_r_reg[6]_0 (u_poc_tap_base_n_86), .\samp_wait_r_reg[7]_0 ({samp_wait_r[7:6],samp_wait_r[4:0]}), .samps_hi_ns0(samps_hi_ns0), .\samps_hi_r_reg[11]_0 ({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35}), .\samps_hi_r_reg[15]_0 ({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39}), .\samps_hi_r_reg[17]_0 ({u_poc_tap_base_n_40,u_poc_tap_base_n_41}), .\samps_hi_r_reg[3]_0 ({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27}), .\samps_hi_r_reg[7]_0 ({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31}), .samps_lo(samps_lo), .samps_zero_r_reg_0({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45}), .samps_zero_r_reg_1({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67}), .samps_zero_r_reg_2({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70}), .samps_zero_r_reg_3({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73}), .samps_zero_r_reg_4(u_poc_tap_base_n_74), .samps_zero_r_reg_5(u_poc_tap_base_n_75), .\sm_r_reg[0]_0 (u_poc_tap_base_n_54), .\sm_r_reg[0]_1 (u_poc_tap_base_n_55), .\tap_r_reg[0]_0 (u_poc_tap_base_n_46), .trailing_edge0(trailing_edge0), .trailing_edge00_in(trailing_edge00_in)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_rank_cntrl" *) module ddr3_ifmig_7series_v4_0_rank_cntrl (act_delayed, read_this_rank_r, inhbt_act_faw_r, periodic_rd_request_r, periodic_rd_cntr1_r, \grant_r_reg[0] , \rtw_timer.rtw_cnt_r_reg[1]_0 , \periodic_rd_generation.periodic_rd_request_r_reg_0 , \inhbt_act_faw.inhbt_act_faw_r_reg_0 , granted_col_r_reg, act_this_rank, CLK, read_this_rank, SR, periodic_rd_ack_r_lcl_reg, \periodic_read_request.periodic_rd_grant_r_reg[0] , init_calib_complete_reg_rep__6, \grant_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[1] , \wr_this_rank_r_reg[0] , maint_prescaler_tick_r, \act_this_rank_r_reg[0] , init_calib_complete_reg_rep__7, \periodic_rd_generation.read_this_rank_r_reg_0 , init_calib_complete_reg_rep__6_0, \inhbt_act_faw.faw_cnt_r_reg[1]_0 ); output act_delayed; output read_this_rank_r; output inhbt_act_faw_r; output periodic_rd_request_r; output periodic_rd_cntr1_r; output \grant_r_reg[0] ; output [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; output \periodic_rd_generation.periodic_rd_request_r_reg_0 ; output [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg_0 ; output granted_col_r_reg; input act_this_rank; input CLK; input read_this_rank; input [0:0]SR; input periodic_rd_ack_r_lcl_reg; input \periodic_read_request.periodic_rd_grant_r_reg[0] ; input init_calib_complete_reg_rep__6; input \grant_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input \grant_r_reg[1] ; input \wr_this_rank_r_reg[0] ; input maint_prescaler_tick_r; input \act_this_rank_r_reg[0] ; input init_calib_complete_reg_rep__7; input \periodic_rd_generation.read_this_rank_r_reg_0 ; input init_calib_complete_reg_rep__6_0; input [2:0]\inhbt_act_faw.faw_cnt_r_reg[1]_0 ; wire CLK; wire [0:0]SR; wire act_delayed; wire act_this_rank; wire \act_this_rank_r_reg[0] ; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[1] ; wire granted_col_r_reg; wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[1]_0 ; wire \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ; wire [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg_0 ; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire init_calib_complete_reg_rep__7; wire maint_prescaler_tick_r; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_cntr1_r; wire \periodic_rd_generation.periodic_rd_request_r_reg_0 ; wire \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ; wire \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ; wire \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ; wire \periodic_rd_generation.read_this_rank_r_reg_0 ; wire periodic_rd_request_r; wire [2:0]periodic_rd_timer_r; wire \periodic_read_request.periodic_rd_grant_r_reg[0] ; wire read_this_rank; wire read_this_rank_r; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire [1:0]rtw_cnt_ns; wire [0:0]rtw_cnt_r; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire \wr_this_rank_r_reg[0] ; wire [2:0]wtr_cnt_ns; wire [2:0]wtr_cnt_r; LUT4 #( .INIT(16'hCCCD)) \grant_r[1]_i_4__0 (.I0(\wr_this_rank_r_reg[0] ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(wtr_cnt_r[1]), .I3(wtr_cnt_r[2]), .O(granted_col_r_reg)); LUT5 #( .INIT(32'h55554555)) i___25_i_2 (.I0(periodic_rd_request_r), .I1(periodic_rd_timer_r[2]), .I2(maint_prescaler_tick_r), .I3(periodic_rd_timer_r[0]), .I4(periodic_rd_timer_r[1]), .O(\periodic_rd_generation.periodic_rd_request_r_reg_0 )); (* XILINX_LEGACY_PRIM = "SRLC32E" *) (* box_type = "PRIMITIVE" *) (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 " *) SRL16E #( .INIT(16'h0000), .IS_CLK_INVERTED(1'b0)) \inhbt_act_faw.SRLC32E0 (.A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(act_this_rank), .Q(act_delayed)); FDRE #( .INIT(1'b0)) \inhbt_act_faw.faw_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.faw_cnt_r_reg[1]_0 [0]), .Q(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \inhbt_act_faw.faw_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.faw_cnt_r_reg[1]_0 [1]), .Q(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \inhbt_act_faw.faw_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.faw_cnt_r_reg[1]_0 [2]), .Q(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]), .R(1'b0)); LUT6 #( .INIT(64'h0001000020000220)) \inhbt_act_faw.inhbt_act_faw_r_i_1 (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(act_delayed), .I3(\act_this_rank_r_reg[0] ), .I4(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]), .I5(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]), .O(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \inhbt_act_faw.inhbt_act_faw_r_reg (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ), .Q(inhbt_act_faw_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \periodic_rd_generation.periodic_rd_cntr1_r_reg (.C(CLK), .CE(1'b1), .D(\periodic_read_request.periodic_rd_grant_r_reg[0] ), .Q(periodic_rd_cntr1_r), .R(SR)); FDRE #( .INIT(1'b0)) \periodic_rd_generation.periodic_rd_request_r_reg (.C(CLK), .CE(1'b1), .D(periodic_rd_ack_r_lcl_reg), .Q(periodic_rd_request_r), .R(SR)); LUT6 #( .INIT(64'hFFFFFFFF3C78FFFF)) \periodic_rd_generation.periodic_rd_timer_r[0]_i_1 (.I0(periodic_rd_timer_r[2]), .I1(maint_prescaler_tick_r), .I2(periodic_rd_timer_r[0]), .I3(periodic_rd_timer_r[1]), .I4(init_calib_complete_reg_rep__6_0), .I5(\periodic_rd_generation.read_this_rank_r_reg_0 ), .O(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000F3080000)) \periodic_rd_generation.periodic_rd_timer_r[1]_i_1 (.I0(periodic_rd_timer_r[2]), .I1(maint_prescaler_tick_r), .I2(periodic_rd_timer_r[0]), .I3(periodic_rd_timer_r[1]), .I4(init_calib_complete_reg_rep__7), .I5(\periodic_rd_generation.read_this_rank_r_reg_0 ), .O(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAE2FFFF)) \periodic_rd_generation.periodic_rd_timer_r[2]_i_1 (.I0(periodic_rd_timer_r[2]), .I1(maint_prescaler_tick_r), .I2(periodic_rd_timer_r[0]), .I3(periodic_rd_timer_r[1]), .I4(init_calib_complete_reg_rep__7), .I5(\periodic_rd_generation.read_this_rank_r_reg_0 ), .O(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \periodic_rd_generation.periodic_rd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ), .Q(periodic_rd_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \periodic_rd_generation.periodic_rd_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ), .Q(periodic_rd_timer_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \periodic_rd_generation.periodic_rd_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ), .Q(periodic_rd_timer_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \periodic_rd_generation.read_this_rank_r_reg (.C(CLK), .CE(1'b1), .D(read_this_rank), .Q(read_this_rank_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \refresh_generation.refresh_bank_r_reg[0] (.C(CLK), .CE(1'b1), .D(init_calib_complete_reg_rep__6), .Q(\grant_r_reg[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1069" *) LUT4 #( .INIT(16'h0008)) \rtw_timer.rtw_cnt_r[0]_i_1 (.I0(\grant_r_reg[0]_0 ), .I1(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(rtw_cnt_r), .O(rtw_cnt_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1069" *) LUT4 #( .INIT(16'h0D05)) \rtw_timer.rtw_cnt_r[1]_i_1 (.I0(\grant_r_reg[0]_0 ), .I1(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(rtw_cnt_r), .O(rtw_cnt_ns[1])); FDRE #( .INIT(1'b0)) \rtw_timer.rtw_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(rtw_cnt_ns[0]), .Q(rtw_cnt_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \rtw_timer.rtw_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(rtw_cnt_ns[1]), .Q(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1070" *) LUT4 #( .INIT(16'h5400)) \wtr_timer.wtr_cnt_r[0]_i_1 (.I0(wtr_cnt_r[0]), .I1(wtr_cnt_r[2]), .I2(wtr_cnt_r[1]), .I3(\grant_r_reg[1] ), .O(wtr_cnt_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1070" *) LUT4 #( .INIT(16'h8820)) \wtr_timer.wtr_cnt_r[1]_i_1 (.I0(\grant_r_reg[1] ), .I1(wtr_cnt_r[1]), .I2(wtr_cnt_r[2]), .I3(wtr_cnt_r[0]), .O(wtr_cnt_ns[1])); LUT5 #( .INIT(32'h0000FFA8)) \wtr_timer.wtr_cnt_r[2]_i_1 (.I0(wtr_cnt_r[2]), .I1(wtr_cnt_r[0]), .I2(wtr_cnt_r[1]), .I3(\wr_this_rank_r_reg[0] ), .I4(rstdiv0_sync_r1_reg_rep__21), .O(wtr_cnt_ns[2])); FDRE #( .INIT(1'b0)) \wtr_timer.wtr_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(wtr_cnt_ns[0]), .Q(wtr_cnt_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wtr_timer.wtr_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(wtr_cnt_ns[1]), .Q(wtr_cnt_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wtr_timer.wtr_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(wtr_cnt_ns[2]), .Q(wtr_cnt_r[2]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_rank_common" *) module ddr3_ifmig_7series_v4_0_rank_common (maint_prescaler_tick_r, maint_prescaler_tick_ns, \maintenance_request.new_maint_rank_r_reg_0 , \maintenance_request.maint_req_r_lcl_reg_0 , maint_req_r, \periodic_read_request.upd_last_master_r_reg_0 , app_ref_ack, app_zq_ack, \maint_controller.maint_srx_r1_reg , \maintenance_request.maint_sre_r_lcl_reg_0 , \grant_r_reg[0] , \grant_r_reg[0]_0 , \maintenance_request.maint_zq_r_lcl_reg_0 , periodic_rd_r, app_ref_r, app_zq_r, periodic_rd_r_cnt, periodic_rd_grant_r, app_sr_active, maint_ref_zq_wip, Q, \refresh_timer.refresh_timer_r_reg[5]_0 , \refresh_timer.refresh_timer_r_reg[4]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 , \maintenance_request.maint_sre_r_lcl_reg_1 , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] , \last_master_r_reg[2] , mc_cke_ns, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] , \refresh_generation.refresh_bank_r_reg[0] , S, \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 , CLK, \maint_controller.maint_wip_r_lcl_reg , SR, \zq_cntrl.zq_request_logic.zq_request_r_reg_0 , init_calib_complete_reg_rep__6, maint_prescaler_r1, periodic_rd_ack_r_lcl_reg, \refresh_generation.refresh_bank_r_reg[0]_0 , app_zq_r_reg_0, \periodic_read_request.periodic_rd_r_lcl_reg_0 , \periodic_rd_generation.periodic_rd_request_r_reg , \maintenance_request.maint_sre_r_lcl_reg_2 , \refresh_generation.refresh_bank_r_reg[0]_1 , O, \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 , \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 , \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 , \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 , init_calib_complete_reg_rep__6_0, app_sr_req, D, \refresh_generation.refresh_bank_r_reg[0]_2 , \last_master_r_reg[2]_0 , rstdiv0_sync_r1_reg_rep__20, periodic_rd_request_r, cke_r, insert_maint_r1, E, \generate_maint_cmds.insert_maint_r_lcl_reg , rstdiv0_sync_r1_reg_rep__21, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 , SS, \maint_prescaler.maint_prescaler_r_reg[0]_0 , init_calib_complete_reg_rep__6_1, \refresh_timer.refresh_timer_r_reg[0]_0 ); output maint_prescaler_tick_r; output maint_prescaler_tick_ns; output \maintenance_request.new_maint_rank_r_reg_0 ; output \maintenance_request.maint_req_r_lcl_reg_0 ; output maint_req_r; output \periodic_read_request.upd_last_master_r_reg_0 ; output app_ref_ack; output app_zq_ack; output \maint_controller.maint_srx_r1_reg ; output \maintenance_request.maint_sre_r_lcl_reg_0 ; output \grant_r_reg[0] ; output \grant_r_reg[0]_0 ; output \maintenance_request.maint_zq_r_lcl_reg_0 ; output periodic_rd_r; output app_ref_r; output app_zq_r; output periodic_rd_r_cnt; output periodic_rd_grant_r; output app_sr_active; output maint_ref_zq_wip; output [1:0]Q; output \refresh_timer.refresh_timer_r_reg[5]_0 ; output [1:0]\refresh_timer.refresh_timer_r_reg[4]_0 ; output \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ; output [2:0]\maintenance_request.maint_sre_r_lcl_reg_1 ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; output [2:0]\last_master_r_reg[2] ; output [0:0]mc_cke_ns; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; output \refresh_generation.refresh_bank_r_reg[0] ; output [3:0]S; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; input CLK; input \maint_controller.maint_wip_r_lcl_reg ; input [0:0]SR; input \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ; input init_calib_complete_reg_rep__6; input maint_prescaler_r1; input periodic_rd_ack_r_lcl_reg; input \refresh_generation.refresh_bank_r_reg[0]_0 ; input app_zq_r_reg_0; input \periodic_read_request.periodic_rd_r_lcl_reg_0 ; input \periodic_rd_generation.periodic_rd_request_r_reg ; input \maintenance_request.maint_sre_r_lcl_reg_2 ; input \refresh_generation.refresh_bank_r_reg[0]_1 ; input [3:0]O; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ; input init_calib_complete_reg_rep__6_0; input app_sr_req; input [1:0]D; input \refresh_generation.refresh_bank_r_reg[0]_2 ; input \last_master_r_reg[2]_0 ; input rstdiv0_sync_r1_reg_rep__20; input periodic_rd_request_r; input cke_r; input insert_maint_r1; input [0:0]E; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; input [0:0]SS; input [0:0]\maint_prescaler.maint_prescaler_r_reg[0]_0 ; input [0:0]init_calib_complete_reg_rep__6_1; input [0:0]\refresh_timer.refresh_timer_r_reg[0]_0 ; wire CLK; wire [1:0]D; wire [0:0]E; wire [3:0]O; wire [1:0]Q; wire [3:0]S; wire [0:0]SR; wire [0:0]SS; wire app_ref_ack; wire app_ref_ack_ns; wire app_ref_r; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_ack_ns; wire app_zq_r; wire app_zq_r_reg_0; wire cke_r; wire [1:0]ckesr_timer_r; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire i___16_i_3_n_0; wire i___18_i_2_n_0; wire inhbt_srx; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire [0:0]init_calib_complete_reg_rep__6_1; wire insert_maint_r1; wire [2:0]\last_master_r_reg[2] ; wire \last_master_r_reg[2]_0 ; wire \maint_controller.maint_srx_r1_reg ; wire \maint_controller.maint_wip_r_lcl_reg ; wire [0:0]\maint_prescaler.maint_prescaler_r_reg[0]_0 ; wire [5:2]\maint_prescaler.maint_prescaler_r_reg__0 ; wire [5:0]maint_prescaler_r0; wire maint_prescaler_r1; wire maint_prescaler_tick_ns; wire maint_prescaler_tick_r; wire maint_ref_zq_wip; wire maint_req_r; wire \maintenance_request.maint_arb0_n_0 ; wire \maintenance_request.maint_arb0_n_4 ; wire \maintenance_request.maint_arb0_n_8 ; wire \maintenance_request.maint_req_r_lcl_reg_0 ; wire \maintenance_request.maint_sre_r_lcl_reg_0 ; wire [2:0]\maintenance_request.maint_sre_r_lcl_reg_1 ; wire \maintenance_request.maint_sre_r_lcl_reg_2 ; wire \maintenance_request.maint_srx_r_lcl_i_2_n_0 ; wire \maintenance_request.maint_zq_r_lcl_reg_0 ; wire \maintenance_request.new_maint_rank_r_reg_0 ; wire [0:0]mc_cke_ns; wire periodic_rd_ack_r_lcl_reg; wire \periodic_rd_generation.periodic_rd_request_r_reg ; wire periodic_rd_grant_r; wire periodic_rd_r; wire periodic_rd_r_cnt; wire periodic_rd_request_r; wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ; wire \periodic_read_request.upd_last_master_r_reg_0 ; wire \refresh_generation.refresh_bank_r_reg[0] ; wire \refresh_generation.refresh_bank_r_reg[0]_0 ; wire \refresh_generation.refresh_bank_r_reg[0]_1 ; wire \refresh_generation.refresh_bank_r_reg[0]_2 ; wire \refresh_timer.refresh_timer_r[5]_i_3_n_0 ; wire [0:0]\refresh_timer.refresh_timer_r_reg[0]_0 ; wire [1:0]\refresh_timer.refresh_timer_r_reg[4]_0 ; wire \refresh_timer.refresh_timer_r_reg[5]_0 ; wire [5:2]\refresh_timer.refresh_timer_r_reg__0 ; wire [5:0]refresh_timer_r0; wire refresh_timer_r0_0; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire sel; wire \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ; wire \sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ; wire upd_last_master_ns; wire \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ; wire [19:0]\zq_cntrl.zq_timer.zq_timer_r_reg ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ; wire zq_timer_r0; (* SOFT_HLUTNM = "soft_lutpair1079" *) LUT3 #( .INIT(8'h8A)) app_ref_ack_r_i_1 (.I0(app_ref_r), .I1(\refresh_generation.refresh_bank_r_reg[0]_2 ), .I2(init_calib_complete_reg_rep__6_0), .O(app_ref_ack_ns)); FDRE #( .INIT(1'b0)) app_ref_ack_r_reg (.C(CLK), .CE(1'b1), .D(app_ref_ack_ns), .Q(app_ref_ack), .R(1'b0)); FDRE #( .INIT(1'b0)) app_ref_r_reg (.C(CLK), .CE(1'b1), .D(\refresh_generation.refresh_bank_r_reg[0]_0 ), .Q(app_ref_r), .R(maint_prescaler_r1)); FDRE #( .INIT(1'b0)) app_sr_active_r_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_sre_r_lcl_reg_2 ), .Q(app_sr_active), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1079" *) LUT3 #( .INIT(8'h2A)) app_zq_ack_r_i_1 (.I0(app_zq_r), .I1(init_calib_complete_reg_rep__6_0), .I2(\grant_r_reg[0] ), .O(app_zq_ack_ns)); FDRE #( .INIT(1'b0)) app_zq_ack_r_reg (.C(CLK), .CE(1'b1), .D(app_zq_ack_ns), .Q(app_zq_ack), .R(1'b0)); FDRE #( .INIT(1'b0)) app_zq_r_reg (.C(CLK), .CE(1'b1), .D(app_zq_r_reg_0), .Q(app_zq_r), .R(maint_prescaler_r1)); (* SOFT_HLUTNM = "soft_lutpair1075" *) LUT4 #( .INIT(16'h0ECC)) cke_r_i_2 (.I0(\maint_controller.maint_srx_r1_reg ), .I1(cke_r), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(insert_maint_r1), .O(mc_cke_ns)); LUT6 #( .INIT(64'h0000000000100000)) i___16_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [2]), .I1(\refresh_timer.refresh_timer_r_reg__0 [5]), .I2(maint_prescaler_tick_r), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I4(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I5(i___16_i_3_n_0), .O(\refresh_timer.refresh_timer_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair1075" *) LUT4 #( .INIT(16'h0100)) i___16_i_2 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I2(\maint_controller.maint_srx_r1_reg ), .I3(insert_maint_r1), .O(\refresh_generation.refresh_bank_r_reg[0] )); LUT2 #( .INIT(4'hE)) i___16_i_3 (.I0(\refresh_timer.refresh_timer_r_reg__0 [3]), .I1(\refresh_timer.refresh_timer_r_reg__0 [4]), .O(i___16_i_3_n_0)); LUT4 #( .INIT(16'hA8AA)) i___18_i_1 (.I0(init_calib_complete_reg_rep__6_0), .I1(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ), .I2(i___18_i_2_n_0), .I3(\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair1074" *) LUT5 #( .INIT(32'hFFFFFFBF)) i___18_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ), .I1(maint_prescaler_tick_r), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .O(i___18_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1073" *) LUT3 #( .INIT(8'h54)) i___19_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maint_controller.maint_srx_r1_reg ), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair1071" *) LUT1 #( .INIT(2'h1)) \maint_prescaler.maint_prescaler_r[0]_i_1 (.I0(Q[0]), .O(maint_prescaler_r0[0])); (* SOFT_HLUTNM = "soft_lutpair1077" *) LUT3 #( .INIT(8'hA9)) \maint_prescaler.maint_prescaler_r[2]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I1(Q[1]), .I2(Q[0]), .O(maint_prescaler_r0[2])); (* SOFT_HLUTNM = "soft_lutpair1077" *) LUT4 #( .INIT(16'hAAA9)) \maint_prescaler.maint_prescaler_r[3]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I2(Q[0]), .I3(Q[1]), .O(maint_prescaler_r0[3])); (* SOFT_HLUTNM = "soft_lutpair1071" *) LUT5 #( .INIT(32'hAAAAAAA9)) \maint_prescaler.maint_prescaler_r[4]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I2(Q[1]), .I3(Q[0]), .I4(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .O(maint_prescaler_r0[4])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \maint_prescaler.maint_prescaler_r[5]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I2(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .I3(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I4(Q[0]), .I5(Q[1]), .O(sel)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \maint_prescaler.maint_prescaler_r[5]_i_2 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .I1(Q[1]), .I2(Q[0]), .I3(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I4(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I5(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .O(maint_prescaler_r0[5])); FDRE #( .INIT(1'b0)) \maint_prescaler.maint_prescaler_r_reg[0] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[0]), .Q(Q[0]), .R(SS)); FDRE #( .INIT(1'b0)) \maint_prescaler.maint_prescaler_r_reg[1] (.C(CLK), .CE(sel), .D(\maint_prescaler.maint_prescaler_r_reg[0]_0 ), .Q(Q[1]), .R(SS)); FDSE #( .INIT(1'b1)) \maint_prescaler.maint_prescaler_r_reg[2] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[2]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .S(SS)); FDSE #( .INIT(1'b1)) \maint_prescaler.maint_prescaler_r_reg[3] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[3]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .S(SS)); FDRE #( .INIT(1'b0)) \maint_prescaler.maint_prescaler_r_reg[4] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[4]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .R(SS)); FDSE #( .INIT(1'b1)) \maint_prescaler.maint_prescaler_r_reg[5] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[5]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .S(SS)); LUT6 #( .INIT(64'h0000000000010000)) \maint_prescaler.maint_prescaler_tick_r_lcl_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I2(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .I3(Q[1]), .I4(Q[0]), .I5(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .O(maint_prescaler_tick_ns)); FDRE #( .INIT(1'b0)) \maint_prescaler.maint_prescaler_tick_r_lcl_reg (.C(CLK), .CE(1'b1), .D(maint_prescaler_tick_ns), .Q(maint_prescaler_tick_r), .R(1'b0)); FDRE #( .INIT(1'b0)) maint_ref_zq_wip_r_reg (.C(CLK), .CE(1'b1), .D(\refresh_generation.refresh_bank_r_reg[0]_1 ), .Q(maint_ref_zq_wip), .R(SR)); ddr3_ifmig_7series_v4_0_round_robin_arb \maintenance_request.maint_arb0 (.CLK(CLK), .D(D), .Q(\maintenance_request.maint_sre_r_lcl_reg_1 ), .app_sr_req(app_sr_req), .ckesr_timer_r(ckesr_timer_r), .inhbt_srx(inhbt_srx), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0), .\last_master_r_reg[2]_0 (\last_master_r_reg[2] ), .\last_master_r_reg[2]_1 (\last_master_r_reg[2]_0 ), .\maintenance_request.maint_sre_r_lcl_reg (\maintenance_request.maint_arb0_n_0 ), .\maintenance_request.maint_sre_r_lcl_reg_0 (\maintenance_request.maint_sre_r_lcl_reg_0 ), .\maintenance_request.maint_srx_r_lcl_reg (\maintenance_request.maint_arb0_n_4 ), .\maintenance_request.maint_srx_r_lcl_reg_0 (\maint_controller.maint_srx_r1_reg ), .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_arb0_n_8 ), .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ), .\maintenance_request.new_maint_rank_r_reg (\maintenance_request.maint_req_r_lcl_reg_0 ), .\maintenance_request.upd_last_master_r_reg (\maintenance_request.maint_srx_r_lcl_i_2_n_0 ), .\maintenance_request.upd_last_master_r_reg_0 (\maintenance_request.new_maint_rank_r_reg_0 ), .\refresh_generation.refresh_bank_r_reg[0] (\refresh_generation.refresh_bank_r_reg[0]_2 ), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\sr_cntrl.sre_request_logic.sre_request_r_reg (\grant_r_reg[0]_0 ), .\zq_cntrl.zq_request_logic.zq_request_r_reg (\grant_r_reg[0] )); FDRE #( .INIT(1'b0)) \maintenance_request.maint_req_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_req_r_lcl_reg_0 ), .Q(maint_req_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \maintenance_request.maint_sre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_arb0_n_0 ), .Q(\maintenance_request.maint_sre_r_lcl_reg_0 ), .R(SR)); LUT2 #( .INIT(4'h2)) \maintenance_request.maint_srx_r_lcl_i_2 (.I0(\maintenance_request.new_maint_rank_r_reg_0 ), .I1(\maintenance_request.maint_req_r_lcl_reg_0 ), .O(\maintenance_request.maint_srx_r_lcl_i_2_n_0 )); LUT2 #( .INIT(4'hE)) \maintenance_request.maint_srx_r_lcl_i_3 (.I0(ckesr_timer_r[0]), .I1(ckesr_timer_r[1]), .O(inhbt_srx)); FDRE #( .INIT(1'b0)) \maintenance_request.maint_srx_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_arb0_n_4 ), .Q(\maint_controller.maint_srx_r1_reg ), .R(SR)); FDRE #( .INIT(1'b0)) \maintenance_request.maint_zq_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_arb0_n_8 ), .Q(\maintenance_request.maint_zq_r_lcl_reg_0 ), .R(SR)); FDRE #( .INIT(1'b0)) \maintenance_request.new_maint_rank_r_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.new_maint_rank_r_reg_0 ), .Q(\maintenance_request.maint_req_r_lcl_reg_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \maintenance_request.upd_last_master_r_reg (.C(CLK), .CE(1'b1), .D(\maint_controller.maint_wip_r_lcl_reg ), .Q(\maintenance_request.new_maint_rank_r_reg_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \periodic_read_request.periodic_rd_grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_request_r_reg ), .Q(periodic_rd_grant_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \periodic_read_request.periodic_rd_r_cnt_reg (.C(CLK), .CE(1'b1), .D(\periodic_read_request.periodic_rd_r_lcl_reg_0 ), .Q(periodic_rd_r_cnt), .R(SR)); FDRE #( .INIT(1'b0)) \periodic_read_request.periodic_rd_r_lcl_reg (.C(CLK), .CE(1'b1), .D(periodic_rd_ack_r_lcl_reg), .Q(periodic_rd_r), .R(maint_prescaler_r1)); LUT4 #( .INIT(16'h0008)) \periodic_read_request.upd_last_master_r_i_1 (.I0(periodic_rd_request_r), .I1(init_calib_complete_reg_rep__6_0), .I2(\periodic_read_request.upd_last_master_r_reg_0 ), .I3(periodic_rd_r), .O(upd_last_master_ns)); FDRE #( .INIT(1'b0)) \periodic_read_request.upd_last_master_r_reg (.C(CLK), .CE(1'b1), .D(upd_last_master_ns), .Q(\periodic_read_request.upd_last_master_r_reg_0 ), .R(1'b0)); LUT1 #( .INIT(2'h1)) \refresh_timer.refresh_timer_r[0]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .O(refresh_timer_r0[0])); (* SOFT_HLUTNM = "soft_lutpair1078" *) LUT3 #( .INIT(8'hA9)) \refresh_timer.refresh_timer_r[2]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [2]), .I1(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I2(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .O(refresh_timer_r0[2])); (* SOFT_HLUTNM = "soft_lutpair1072" *) LUT4 #( .INIT(16'hAAA9)) \refresh_timer.refresh_timer_r[3]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [3]), .I1(\refresh_timer.refresh_timer_r_reg__0 [2]), .I2(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .O(refresh_timer_r0[3])); (* SOFT_HLUTNM = "soft_lutpair1072" *) LUT5 #( .INIT(32'hAAAAAAA9)) \refresh_timer.refresh_timer_r[4]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [4]), .I1(\refresh_timer.refresh_timer_r_reg__0 [3]), .I2(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I4(\refresh_timer.refresh_timer_r_reg__0 [2]), .O(refresh_timer_r0[4])); LUT5 #( .INIT(32'hAAAAAA8A)) \refresh_timer.refresh_timer_r[5]_i_1 (.I0(maint_prescaler_tick_r), .I1(\refresh_timer.refresh_timer_r_reg__0 [5]), .I2(\refresh_timer.refresh_timer_r[5]_i_3_n_0 ), .I3(\refresh_timer.refresh_timer_r_reg__0 [4]), .I4(\refresh_timer.refresh_timer_r_reg__0 [3]), .O(refresh_timer_r0_0)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \refresh_timer.refresh_timer_r[5]_i_2 (.I0(\refresh_timer.refresh_timer_r_reg__0 [5]), .I1(\refresh_timer.refresh_timer_r_reg__0 [3]), .I2(\refresh_timer.refresh_timer_r_reg__0 [4]), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I4(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I5(\refresh_timer.refresh_timer_r_reg__0 [2]), .O(refresh_timer_r0[5])); (* SOFT_HLUTNM = "soft_lutpair1078" *) LUT3 #( .INIT(8'h01)) \refresh_timer.refresh_timer_r[5]_i_3 (.I0(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I1(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I2(\refresh_timer.refresh_timer_r_reg__0 [2]), .O(\refresh_timer.refresh_timer_r[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \refresh_timer.refresh_timer_r_reg[0] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[0]), .Q(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .R(init_calib_complete_reg_rep__6_1)); FDSE #( .INIT(1'b1)) \refresh_timer.refresh_timer_r_reg[1] (.C(CLK), .CE(refresh_timer_r0_0), .D(\refresh_timer.refresh_timer_r_reg[0]_0 ), .Q(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .S(init_calib_complete_reg_rep__6_1)); FDSE #( .INIT(1'b1)) \refresh_timer.refresh_timer_r_reg[2] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[2]), .Q(\refresh_timer.refresh_timer_r_reg__0 [2]), .S(init_calib_complete_reg_rep__6_1)); FDRE #( .INIT(1'b0)) \refresh_timer.refresh_timer_r_reg[3] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[3]), .Q(\refresh_timer.refresh_timer_r_reg__0 [3]), .R(init_calib_complete_reg_rep__6_1)); FDRE #( .INIT(1'b0)) \refresh_timer.refresh_timer_r_reg[4] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[4]), .Q(\refresh_timer.refresh_timer_r_reg__0 [4]), .R(init_calib_complete_reg_rep__6_1)); FDSE #( .INIT(1'b1)) \refresh_timer.refresh_timer_r_reg[5] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[5]), .Q(\refresh_timer.refresh_timer_r_reg__0 [5]), .S(init_calib_complete_reg_rep__6_1)); LUT6 #( .INIT(64'h00000101000000FF)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 (.I0(\maint_controller.maint_srx_r1_reg ), .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .I4(rstdiv0_sync_r1_reg_rep__21), .I5(\generate_maint_cmds.insert_maint_r_lcl_reg ), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1073" *) LUT5 #( .INIT(32'h00000100)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_2 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I2(\maint_controller.maint_srx_r1_reg ), .I3(\generate_maint_cmds.insert_maint_r_lcl_reg ), .I4(rstdiv0_sync_r1_reg_rep__21), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] )); LUT6 #( .INIT(64'h5555555555555D55)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4 (.I0(E), .I1(\generate_maint_cmds.insert_maint_r_lcl_reg ), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(\maint_controller.maint_srx_r1_reg ), .I4(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I5(\maintenance_request.maint_sre_r_lcl_reg_0 ), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair1076" *) LUT4 #( .INIT(16'h0222)) \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 (.I0(ckesr_timer_r[1]), .I1(ckesr_timer_r[0]), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(insert_maint_r1), .O(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1076" *) LUT4 #( .INIT(16'hF888)) \sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1 (.I0(ckesr_timer_r[1]), .I1(ckesr_timer_r[0]), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(insert_maint_r1), .O(\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ), .Q(ckesr_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ), .Q(ckesr_timer_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \sr_cntrl.sre_request_logic.sre_request_r_reg (.C(CLK), .CE(1'b1), .D(init_calib_complete_reg_rep__6), .Q(\grant_r_reg[0]_0 ), .R(SR)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_request_logic.zq_request_r_reg (.C(CLK), .CE(1'b1), .D(\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ), .Q(\grant_r_reg[0] ), .R(SR)); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_1 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ), .O(zq_timer_r0)); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_10 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [1]), .O(S[1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_11 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .O(S[0])); LUT4 #( .INIT(16'hFFFE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_12 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [3]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [5]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [4]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 )); LUT6 #( .INIT(64'hAAAAAAA8AAAAAAAA)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_2 (.I0(maint_prescaler_tick_r), .I1(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .I3(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ), .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ), .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [8]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [7]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [17]), .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1074" *) LUT2 #( .INIT(4'hE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 )); LUT4 #( .INIT(16'hFFFE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_6 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [1]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [16]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [15]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 )); LUT5 #( .INIT(32'h00000001)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_7 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [10]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [11]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [12]), .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [14]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_8 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [3]), .O(S[3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_9 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .O(S[2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [15]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [12]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [0])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [16]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [0])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [5]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [4]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [0])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [11]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [10]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [8]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [0])); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[0] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .R(zq_timer_r0)); FDSE #( .INIT(1'b1)) \zq_cntrl.zq_timer.zq_timer_r_reg[10] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [10]), .S(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[11] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [11]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[12] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [12]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[13] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [13]), .R(zq_timer_r0)); FDSE #( .INIT(1'b1)) \zq_cntrl.zq_timer.zq_timer_r_reg[14] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [14]), .S(zq_timer_r0)); FDSE #( .INIT(1'b1)) \zq_cntrl.zq_timer.zq_timer_r_reg[15] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [15]), .S(zq_timer_r0)); FDSE #( .INIT(1'b1)) \zq_cntrl.zq_timer.zq_timer_r_reg[16] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [16]), .S(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[17] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [17]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[18] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [18]), .R(zq_timer_r0)); FDSE #( .INIT(1'b1)) \zq_cntrl.zq_timer.zq_timer_r_reg[19] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [19]), .S(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[1] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [1]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[2] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[3] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [3]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[4] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [4]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[5] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [5]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[6] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [6]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[7] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [7]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[8] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [8]), .R(zq_timer_r0)); FDRE #( .INIT(1'b0)) \zq_cntrl.zq_timer.zq_timer_r_reg[9] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .R(zq_timer_r0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_rank_mach" *) module ddr3_ifmig_7series_v4_0_rank_mach (act_delayed, maint_prescaler_tick_ns, upd_last_master_r, new_maint_rank_r, maint_req_r, \periodic_read_request.upd_last_master_r_reg , app_ref_ack, app_zq_ack, read_this_rank_r, inhbt_act_faw_r, maint_srx_r, maint_sre_r, zq_request_r, sre_request_r, maint_zq_r, periodic_rd_request_r, periodic_rd_r, app_ref_r, app_zq_r, periodic_rd_r_cnt, periodic_rd_grant_r, app_sr_active, maint_ref_zq_wip, periodic_rd_cntr1_r, refresh_bank_r, Q, \refresh_timer.refresh_timer_r_reg[5] , \refresh_timer.refresh_timer_r_reg[4] , \zq_cntrl.zq_timer.zq_timer_r_reg[0] , \maintenance_request.maint_sre_r_lcl_reg , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] , \last_master_r_reg[2] , \rtw_timer.rtw_cnt_r_reg[1] , mc_cke_ns, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] , \refresh_generation.refresh_bank_r_reg[0] , S, \zq_cntrl.zq_timer.zq_timer_r_reg[7] , \zq_cntrl.zq_timer.zq_timer_r_reg[11] , \zq_cntrl.zq_timer.zq_timer_r_reg[15] , \zq_cntrl.zq_timer.zq_timer_r_reg[19] , \periodic_rd_generation.periodic_rd_request_r_reg , \inhbt_act_faw.inhbt_act_faw_r_reg , granted_col_r_reg, act_this_rank, CLK, \maint_controller.maint_wip_r_lcl_reg , read_this_rank, SR, \zq_cntrl.zq_request_logic.zq_request_r_reg , init_calib_complete_reg_rep__6, periodic_rd_ack_r_lcl_reg, maint_prescaler_r1, periodic_rd_ack_r_lcl_reg_0, \refresh_generation.refresh_bank_r_reg[0]_0 , app_zq_r_reg, \periodic_read_request.periodic_rd_r_lcl_reg , \periodic_rd_generation.periodic_rd_request_r_reg_0 , \maintenance_request.maint_sre_r_lcl_reg_0 , \refresh_generation.refresh_bank_r_reg[0]_1 , \periodic_read_request.periodic_rd_grant_r_reg[0] , init_calib_complete_reg_rep__6_0, O, \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 , init_calib_complete_reg_rep__6_1, app_sr_req, D, \last_master_r_reg[2]_0 , rstdiv0_sync_r1_reg_rep__20, \grant_r_reg[0] , rstdiv0_sync_r1_reg_rep__21, cke_r, insert_maint_r1, E, \generate_maint_cmds.insert_maint_r_lcl_reg , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 , \grant_r_reg[1] , \wr_this_rank_r_reg[0] , \act_this_rank_r_reg[0] , init_calib_complete_reg_rep__7, \periodic_rd_generation.read_this_rank_r_reg , \inhbt_act_faw.faw_cnt_r_reg[1] , SS, \maint_prescaler.maint_prescaler_r_reg[0] , init_calib_complete_reg_rep__6_2, \refresh_timer.refresh_timer_r_reg[0] ); output act_delayed; output maint_prescaler_tick_ns; output upd_last_master_r; output new_maint_rank_r; output maint_req_r; output \periodic_read_request.upd_last_master_r_reg ; output app_ref_ack; output app_zq_ack; output read_this_rank_r; output inhbt_act_faw_r; output maint_srx_r; output maint_sre_r; output zq_request_r; output sre_request_r; output maint_zq_r; output periodic_rd_request_r; output periodic_rd_r; output app_ref_r; output app_zq_r; output periodic_rd_r_cnt; output periodic_rd_grant_r; output app_sr_active; output maint_ref_zq_wip; output periodic_rd_cntr1_r; output refresh_bank_r; output [1:0]Q; output \refresh_timer.refresh_timer_r_reg[5] ; output [1:0]\refresh_timer.refresh_timer_r_reg[4] ; output \zq_cntrl.zq_timer.zq_timer_r_reg[0] ; output [2:0]\maintenance_request.maint_sre_r_lcl_reg ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; output [2:0]\last_master_r_reg[2] ; output [0:0]\rtw_timer.rtw_cnt_r_reg[1] ; output [0:0]mc_cke_ns; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; output \refresh_generation.refresh_bank_r_reg[0] ; output [3:0]S; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ; output \periodic_rd_generation.periodic_rd_request_r_reg ; output [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg ; output granted_col_r_reg; input act_this_rank; input CLK; input \maint_controller.maint_wip_r_lcl_reg ; input read_this_rank; input [0:0]SR; input \zq_cntrl.zq_request_logic.zq_request_r_reg ; input init_calib_complete_reg_rep__6; input periodic_rd_ack_r_lcl_reg; input maint_prescaler_r1; input periodic_rd_ack_r_lcl_reg_0; input \refresh_generation.refresh_bank_r_reg[0]_0 ; input app_zq_r_reg; input \periodic_read_request.periodic_rd_r_lcl_reg ; input \periodic_rd_generation.periodic_rd_request_r_reg_0 ; input \maintenance_request.maint_sre_r_lcl_reg_0 ; input \refresh_generation.refresh_bank_r_reg[0]_1 ; input \periodic_read_request.periodic_rd_grant_r_reg[0] ; input init_calib_complete_reg_rep__6_0; input [3:0]O; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; input init_calib_complete_reg_rep__6_1; input app_sr_req; input [1:0]D; input \last_master_r_reg[2]_0 ; input rstdiv0_sync_r1_reg_rep__20; input \grant_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__21; input cke_r; input insert_maint_r1; input [0:0]E; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; input \grant_r_reg[1] ; input \wr_this_rank_r_reg[0] ; input \act_this_rank_r_reg[0] ; input init_calib_complete_reg_rep__7; input \periodic_rd_generation.read_this_rank_r_reg ; input [2:0]\inhbt_act_faw.faw_cnt_r_reg[1] ; input [0:0]SS; input [0:0]\maint_prescaler.maint_prescaler_r_reg[0] ; input [0:0]init_calib_complete_reg_rep__6_2; input [0:0]\refresh_timer.refresh_timer_r_reg[0] ; wire CLK; wire [1:0]D; wire [0:0]E; wire [3:0]O; wire [1:0]Q; wire [3:0]S; wire [0:0]SR; wire [0:0]SS; wire act_delayed; wire act_this_rank; wire \act_this_rank_r_reg[0] ; wire app_ref_ack; wire app_ref_r; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_r; wire app_zq_r_reg; wire cke_r; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[0] ; wire \grant_r_reg[1] ; wire granted_col_r_reg; wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[1] ; wire [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire init_calib_complete_reg_rep__6_1; wire [0:0]init_calib_complete_reg_rep__6_2; wire init_calib_complete_reg_rep__7; wire insert_maint_r1; wire [2:0]\last_master_r_reg[2] ; wire \last_master_r_reg[2]_0 ; wire \maint_controller.maint_wip_r_lcl_reg ; wire [0:0]\maint_prescaler.maint_prescaler_r_reg[0] ; wire maint_prescaler_r1; wire maint_prescaler_tick_ns; wire maint_prescaler_tick_r; wire maint_ref_zq_wip; wire maint_req_r; wire maint_sre_r; wire maint_srx_r; wire maint_zq_r; wire [2:0]\maintenance_request.maint_sre_r_lcl_reg ; wire \maintenance_request.maint_sre_r_lcl_reg_0 ; wire [0:0]mc_cke_ns; wire new_maint_rank_r; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_cntr1_r; wire \periodic_rd_generation.periodic_rd_request_r_reg ; wire \periodic_rd_generation.periodic_rd_request_r_reg_0 ; wire \periodic_rd_generation.read_this_rank_r_reg ; wire periodic_rd_grant_r; wire periodic_rd_r; wire periodic_rd_r_cnt; wire periodic_rd_request_r; wire \periodic_read_request.periodic_rd_grant_r_reg[0] ; wire \periodic_read_request.periodic_rd_r_lcl_reg ; wire \periodic_read_request.upd_last_master_r_reg ; wire read_this_rank; wire read_this_rank_r; wire refresh_bank_r; wire \refresh_generation.refresh_bank_r_reg[0] ; wire \refresh_generation.refresh_bank_r_reg[0]_0 ; wire \refresh_generation.refresh_bank_r_reg[0]_1 ; wire [0:0]\refresh_timer.refresh_timer_r_reg[0] ; wire [1:0]\refresh_timer.refresh_timer_r_reg[4] ; wire \refresh_timer.refresh_timer_r_reg[5] ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1] ; wire sre_request_r; wire upd_last_master_r; wire \wr_this_rank_r_reg[0] ; wire \zq_cntrl.zq_request_logic.zq_request_r_reg ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; wire zq_request_r; ddr3_ifmig_7series_v4_0_rank_cntrl \rank_cntrl[0].rank_cntrl0 (.CLK(CLK), .SR(SR), .act_delayed(act_delayed), .act_this_rank(act_this_rank), .\act_this_rank_r_reg[0] (\act_this_rank_r_reg[0] ), .\grant_r_reg[0] (refresh_bank_r), .\grant_r_reg[0]_0 (\grant_r_reg[0] ), .\grant_r_reg[1] (\grant_r_reg[1] ), .granted_col_r_reg(granted_col_r_reg), .\inhbt_act_faw.faw_cnt_r_reg[1]_0 (\inhbt_act_faw.faw_cnt_r_reg[1] ), .\inhbt_act_faw.inhbt_act_faw_r_reg_0 (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1), .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7), .maint_prescaler_tick_r(maint_prescaler_tick_r), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_cntr1_r(periodic_rd_cntr1_r), .\periodic_rd_generation.periodic_rd_request_r_reg_0 (\periodic_rd_generation.periodic_rd_request_r_reg ), .\periodic_rd_generation.read_this_rank_r_reg_0 (\periodic_rd_generation.read_this_rank_r_reg ), .periodic_rd_request_r(periodic_rd_request_r), .\periodic_read_request.periodic_rd_grant_r_reg[0] (\periodic_read_request.periodic_rd_grant_r_reg[0] ), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1] ), .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] )); ddr3_ifmig_7series_v4_0_rank_common rank_common0 (.CLK(CLK), .D(D), .E(E), .O(O), .Q(Q), .S(S), .SR(SR), .SS(SS), .app_ref_ack(app_ref_ack), .app_ref_r(app_ref_r), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_r(app_zq_r), .app_zq_r_reg_0(app_zq_r_reg), .cke_r(cke_r), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\grant_r_reg[0] (zq_request_r), .\grant_r_reg[0]_0 (sre_request_r), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1), .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6_2), .insert_maint_r1(insert_maint_r1), .\last_master_r_reg[2] (\last_master_r_reg[2] ), .\last_master_r_reg[2]_0 (\last_master_r_reg[2]_0 ), .\maint_controller.maint_srx_r1_reg (maint_srx_r), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .\maint_prescaler.maint_prescaler_r_reg[0]_0 (\maint_prescaler.maint_prescaler_r_reg[0] ), .maint_prescaler_r1(maint_prescaler_r1), .maint_prescaler_tick_ns(maint_prescaler_tick_ns), .maint_prescaler_tick_r(maint_prescaler_tick_r), .maint_ref_zq_wip(maint_ref_zq_wip), .maint_req_r(maint_req_r), .\maintenance_request.maint_req_r_lcl_reg_0 (new_maint_rank_r), .\maintenance_request.maint_sre_r_lcl_reg_0 (maint_sre_r), .\maintenance_request.maint_sre_r_lcl_reg_1 (\maintenance_request.maint_sre_r_lcl_reg ), .\maintenance_request.maint_sre_r_lcl_reg_2 (\maintenance_request.maint_sre_r_lcl_reg_0 ), .\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r), .\maintenance_request.new_maint_rank_r_reg_0 (upd_last_master_r), .mc_cke_ns(mc_cke_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_0), .\periodic_rd_generation.periodic_rd_request_r_reg (\periodic_rd_generation.periodic_rd_request_r_reg_0 ), .periodic_rd_grant_r(periodic_rd_grant_r), .periodic_rd_r(periodic_rd_r), .periodic_rd_r_cnt(periodic_rd_r_cnt), .periodic_rd_request_r(periodic_rd_request_r), .\periodic_read_request.periodic_rd_r_lcl_reg_0 (\periodic_read_request.periodic_rd_r_lcl_reg ), .\periodic_read_request.upd_last_master_r_reg_0 (\periodic_read_request.upd_last_master_r_reg ), .\refresh_generation.refresh_bank_r_reg[0] (\refresh_generation.refresh_bank_r_reg[0] ), .\refresh_generation.refresh_bank_r_reg[0]_0 (\refresh_generation.refresh_bank_r_reg[0]_0 ), .\refresh_generation.refresh_bank_r_reg[0]_1 (\refresh_generation.refresh_bank_r_reg[0]_1 ), .\refresh_generation.refresh_bank_r_reg[0]_2 (refresh_bank_r), .\refresh_timer.refresh_timer_r_reg[0]_0 (\refresh_timer.refresh_timer_r_reg[0] ), .\refresh_timer.refresh_timer_r_reg[4]_0 (\refresh_timer.refresh_timer_r_reg[4] ), .\refresh_timer.refresh_timer_r_reg[5]_0 (\refresh_timer.refresh_timer_r_reg[5] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\zq_cntrl.zq_request_logic.zq_request_r_reg_0 (\zq_cntrl.zq_request_logic.zq_request_r_reg ), .\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[0] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[11] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ), .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[15] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ), .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[19] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ), .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[7] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_ifmig_7series_v4_0_round_robin_arb (\maintenance_request.maint_sre_r_lcl_reg , Q, \maintenance_request.maint_srx_r_lcl_reg , \last_master_r_reg[2]_0 , \maintenance_request.maint_zq_r_lcl_reg , \maintenance_request.upd_last_master_r_reg , \maintenance_request.maint_sre_r_lcl_reg_0 , ckesr_timer_r, app_sr_req, \maintenance_request.maint_srx_r_lcl_reg_0 , inhbt_srx, D, init_calib_complete_reg_rep__6, \refresh_generation.refresh_bank_r_reg[0] , \sr_cntrl.sre_request_logic.sre_request_r_reg , \zq_cntrl.zq_request_logic.zq_request_r_reg , \last_master_r_reg[2]_1 , \maintenance_request.upd_last_master_r_reg_0 , \maintenance_request.new_maint_rank_r_reg , rstdiv0_sync_r1_reg_rep__20, \maintenance_request.maint_zq_r_lcl_reg_0 , CLK); output \maintenance_request.maint_sre_r_lcl_reg ; output [2:0]Q; output \maintenance_request.maint_srx_r_lcl_reg ; output [2:0]\last_master_r_reg[2]_0 ; output \maintenance_request.maint_zq_r_lcl_reg ; input \maintenance_request.upd_last_master_r_reg ; input \maintenance_request.maint_sre_r_lcl_reg_0 ; input [1:0]ckesr_timer_r; input app_sr_req; input \maintenance_request.maint_srx_r_lcl_reg_0 ; input inhbt_srx; input [1:0]D; input init_calib_complete_reg_rep__6; input \refresh_generation.refresh_bank_r_reg[0] ; input \sr_cntrl.sre_request_logic.sre_request_r_reg ; input \zq_cntrl.zq_request_logic.zq_request_r_reg ; input \last_master_r_reg[2]_1 ; input \maintenance_request.upd_last_master_r_reg_0 ; input \maintenance_request.new_maint_rank_r_reg ; input rstdiv0_sync_r1_reg_rep__20; input \maintenance_request.maint_zq_r_lcl_reg_0 ; input CLK; wire CLK; wire [1:0]D; wire [2:0]Q; wire app_sr_req; wire [1:0]ckesr_timer_r; wire \grant_r[0]_i_1_n_0 ; wire \grant_r[1]_i_1_n_0 ; wire \grant_r[2]_i_1_n_0 ; wire inhbt_srx; wire init_calib_complete_reg_rep__6; wire \last_master_r[2]_i_1_n_0 ; wire [2:0]\last_master_r_reg[2]_0 ; wire \last_master_r_reg[2]_1 ; wire \maintenance_request.maint_sre_r_lcl_reg ; wire \maintenance_request.maint_sre_r_lcl_reg_0 ; wire \maintenance_request.maint_srx_r_lcl_reg ; wire \maintenance_request.maint_srx_r_lcl_reg_0 ; wire \maintenance_request.maint_zq_r_lcl_reg ; wire \maintenance_request.maint_zq_r_lcl_reg_0 ; wire \maintenance_request.new_maint_rank_r_reg ; wire \maintenance_request.upd_last_master_r_reg ; wire \maintenance_request.upd_last_master_r_reg_0 ; wire \refresh_generation.refresh_bank_r_reg[0] ; wire rstdiv0_sync_r1_reg_rep__20; wire \sr_cntrl.sre_request_logic.sre_request_r_reg ; wire \zq_cntrl.zq_request_logic.zq_request_r_reg ; LUT6 #( .INIT(64'h0000000C040C040C)) \grant_r[0]_i_1 (.I0(D[1]), .I1(init_calib_complete_reg_rep__6), .I2(\refresh_generation.refresh_bank_r_reg[0] ), .I3(\sr_cntrl.sre_request_logic.sre_request_r_reg ), .I4(\zq_cntrl.zq_request_logic.zq_request_r_reg ), .I5(D[0]), .O(\grant_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000A0808080A080)) \grant_r[1]_i_1 (.I0(\zq_cntrl.zq_request_logic.zq_request_r_reg ), .I1(\refresh_generation.refresh_bank_r_reg[0] ), .I2(init_calib_complete_reg_rep__6), .I3(\last_master_r_reg[2]_1 ), .I4(D[1]), .I5(\sr_cntrl.sre_request_logic.sre_request_r_reg ), .O(\grant_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0EAE000000000000)) \grant_r[2]_i_1 (.I0(\last_master_r_reg[2]_1 ), .I1(\refresh_generation.refresh_bank_r_reg[0] ), .I2(\zq_cntrl.zq_request_logic.zq_request_r_reg ), .I3(D[0]), .I4(init_calib_complete_reg_rep__6), .I5(\sr_cntrl.sre_request_logic.sre_request_r_reg ), .O(\grant_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1_n_0 ), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \grant_r_reg[2] (.C(CLK), .CE(1'b1), .D(\grant_r[2]_i_1_n_0 ), .Q(Q[2]), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFB08)) \last_master_r[2]_i_1 (.I0(Q[2]), .I1(\maintenance_request.upd_last_master_r_reg_0 ), .I2(\maintenance_request.new_maint_rank_r_reg ), .I3(\last_master_r_reg[2]_0 [2]), .I4(rstdiv0_sync_r1_reg_rep__20), .O(\last_master_r[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\last_master_r_reg[2]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(\last_master_r_reg[2]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \last_master_r_reg[2] (.C(CLK), .CE(1'b1), .D(\last_master_r[2]_i_1_n_0 ), .Q(\last_master_r_reg[2]_0 [2]), .R(1'b0)); LUT6 #( .INIT(64'hB8B8B8B8B8B8B888)) \maintenance_request.maint_sre_r_lcl_i_1 (.I0(Q[2]), .I1(\maintenance_request.upd_last_master_r_reg ), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(ckesr_timer_r[0]), .I4(ckesr_timer_r[1]), .I5(app_sr_req), .O(\maintenance_request.maint_sre_r_lcl_reg )); LUT6 #( .INIT(64'h000000FFA2A2A2A2)) \maintenance_request.maint_srx_r_lcl_i_1 (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ), .I1(\maintenance_request.upd_last_master_r_reg ), .I2(Q[2]), .I3(app_sr_req), .I4(inhbt_srx), .I5(\maintenance_request.maint_sre_r_lcl_reg_0 ), .O(\maintenance_request.maint_srx_r_lcl_reg )); LUT4 #( .INIT(16'hBA8A)) \maintenance_request.maint_zq_r_lcl_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maintenance_request.new_maint_rank_r_reg ), .I2(\maintenance_request.upd_last_master_r_reg_0 ), .I3(Q[1]), .O(\maintenance_request.maint_zq_r_lcl_reg )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized1 (Q, \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[7] , \cmd_pipe_plus.mc_bank_reg[6] , \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_address_reg[43] , \cmd_pipe_plus.mc_address_reg[42] , \cmd_pipe_plus.mc_address_reg[41] , \cmd_pipe_plus.mc_address_reg[39] , \cmd_pipe_plus.mc_address_reg[38] , \cmd_pipe_plus.mc_address_reg[37] , \cmd_pipe_plus.mc_address_reg[36] , \cmd_pipe_plus.mc_address_reg[35] , \cmd_pipe_plus.mc_address_reg[34] , \cmd_pipe_plus.mc_address_reg[33] , \cmd_pipe_plus.mc_address_reg[32] , \cmd_pipe_plus.mc_address_reg[31] , \cmd_pipe_plus.mc_address_reg[30] , \cmd_pipe_plus.mc_we_n_reg[2] , \cmd_pipe_plus.mc_cas_n_reg[2] , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__21, cs_en2, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , req_row_r, row_cmd_wr, act_wait_r_lcl_reg, CLK); output [1:0]Q; output \cmd_pipe_plus.mc_bank_reg[8] ; output \cmd_pipe_plus.mc_bank_reg[7] ; output \cmd_pipe_plus.mc_bank_reg[6] ; output \cmd_pipe_plus.mc_address_reg[44] ; output \cmd_pipe_plus.mc_address_reg[43] ; output \cmd_pipe_plus.mc_address_reg[42] ; output \cmd_pipe_plus.mc_address_reg[41] ; output \cmd_pipe_plus.mc_address_reg[39] ; output \cmd_pipe_plus.mc_address_reg[38] ; output \cmd_pipe_plus.mc_address_reg[37] ; output \cmd_pipe_plus.mc_address_reg[36] ; output \cmd_pipe_plus.mc_address_reg[35] ; output \cmd_pipe_plus.mc_address_reg[34] ; output \cmd_pipe_plus.mc_address_reg[33] ; output \cmd_pipe_plus.mc_address_reg[32] ; output \cmd_pipe_plus.mc_address_reg[31] ; output \cmd_pipe_plus.mc_address_reg[30] ; output \cmd_pipe_plus.mc_we_n_reg[2] ; output \cmd_pipe_plus.mc_cas_n_reg[2] ; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__21; input cs_en2; input [2:0]\req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [27:0]req_row_r; input [0:0]row_cmd_wr; input act_wait_r_lcl_reg; input CLK; wire CLK; wire [1:0]Q; wire act_wait_r_lcl_reg; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire \cmd_pipe_plus.mc_address_reg[30] ; wire \cmd_pipe_plus.mc_address_reg[31] ; wire \cmd_pipe_plus.mc_address_reg[32] ; wire \cmd_pipe_plus.mc_address_reg[33] ; wire \cmd_pipe_plus.mc_address_reg[34] ; wire \cmd_pipe_plus.mc_address_reg[35] ; wire \cmd_pipe_plus.mc_address_reg[36] ; wire \cmd_pipe_plus.mc_address_reg[37] ; wire \cmd_pipe_plus.mc_address_reg[38] ; wire \cmd_pipe_plus.mc_address_reg[39] ; wire \cmd_pipe_plus.mc_address_reg[41] ; wire \cmd_pipe_plus.mc_address_reg[42] ; wire \cmd_pipe_plus.mc_address_reg[43] ; wire \cmd_pipe_plus.mc_address_reg[44] ; wire \cmd_pipe_plus.mc_bank_reg[6] ; wire \cmd_pipe_plus.mc_bank_reg[7] ; wire \cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_cas_n_reg[2] ; wire \cmd_pipe_plus.mc_we_n_reg[2] ; wire cs_en2; wire \grant_r[0]_i_1__1_n_0 ; wire \grant_r[1]_i_1__1_n_0 ; wire [1:0]last_master_r; wire \last_master_r[0]_i_1_n_0 ; wire \last_master_r[1]_i_1_n_0 ; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [27:0]req_row_r; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__21; LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[30]_i_1 (.I0(req_row_r[14]), .I1(Q[1]), .I2(req_row_r[0]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[30] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[31]_i_1 (.I0(req_row_r[15]), .I1(Q[1]), .I2(req_row_r[1]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[31] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[32]_i_1 (.I0(req_row_r[16]), .I1(Q[1]), .I2(req_row_r[2]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[32] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[33]_i_1 (.I0(req_row_r[17]), .I1(Q[1]), .I2(req_row_r[3]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[33] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[34]_i_1 (.I0(req_row_r[18]), .I1(Q[1]), .I2(req_row_r[4]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[34] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[35]_i_1 (.I0(req_row_r[19]), .I1(Q[1]), .I2(req_row_r[5]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[35] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[36]_i_1 (.I0(req_row_r[20]), .I1(Q[1]), .I2(req_row_r[6]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[36] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[37]_i_1 (.I0(req_row_r[21]), .I1(Q[1]), .I2(req_row_r[7]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[37] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[38]_i_1 (.I0(req_row_r[22]), .I1(Q[1]), .I2(req_row_r[8]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[38] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[39]_i_1 (.I0(req_row_r[23]), .I1(Q[1]), .I2(req_row_r[9]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[39] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[41]_i_1 (.I0(req_row_r[24]), .I1(Q[1]), .I2(req_row_r[10]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[41] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[42]_i_1 (.I0(req_row_r[25]), .I1(Q[1]), .I2(req_row_r[11]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[42] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[43]_i_1 (.I0(req_row_r[26]), .I1(Q[1]), .I2(req_row_r[12]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[43] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_address[44]_i_1 (.I0(req_row_r[27]), .I1(Q[1]), .I2(req_row_r[13]), .I3(Q[0]), .O(\cmd_pipe_plus.mc_address_reg[44] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_bank[6]_i_1 (.I0(\req_bank_r_lcl_reg[2] [0]), .I1(Q[1]), .I2(Q[0]), .I3(\req_bank_r_lcl_reg[2]_0 [0]), .O(\cmd_pipe_plus.mc_bank_reg[6] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_bank[7]_i_1 (.I0(\req_bank_r_lcl_reg[2] [1]), .I1(Q[1]), .I2(Q[0]), .I3(\req_bank_r_lcl_reg[2]_0 [1]), .O(\cmd_pipe_plus.mc_bank_reg[7] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_bank[8]_i_1 (.I0(\req_bank_r_lcl_reg[2] [2]), .I1(Q[1]), .I2(Q[0]), .I3(\req_bank_r_lcl_reg[2]_0 [2]), .O(\cmd_pipe_plus.mc_bank_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair1045" *) LUT3 #( .INIT(8'hFD)) \cmd_pipe_plus.mc_cas_n[2]_i_1 (.I0(cs_en2), .I1(Q[0]), .I2(Q[1]), .O(\cmd_pipe_plus.mc_cas_n_reg[2] )); LUT4 #( .INIT(16'hB888)) \cmd_pipe_plus.mc_we_n[2]_i_2 (.I0(row_cmd_wr), .I1(Q[1]), .I2(act_wait_r_lcl_reg), .I3(Q[0]), .O(\cmd_pipe_plus.mc_we_n_reg[2] )); LUT6 #( .INIT(64'hAAAAAAAA222AAA2A)) \grant_r[0]_i_1__1 (.I0(auto_pre_r_lcl_reg_0), .I1(auto_pre_r_lcl_reg), .I2(last_master_r[0]), .I3(cs_en2), .I4(Q[0]), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\grant_r[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'h2222222A2A2A222A)) \grant_r[1]_i_1__1 (.I0(auto_pre_r_lcl_reg), .I1(auto_pre_r_lcl_reg_0), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(last_master_r[1]), .I4(cs_en2), .I5(Q[1]), .O(\grant_r[1]_i_1__1_n_0 )); FDRE #( .INIT(1'b0)) \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1__1_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1__1_n_0 ), .Q(Q[1]), .R(1'b0)); LUT4 #( .INIT(16'h00E2)) \last_master_r[0]_i_1 (.I0(last_master_r[0]), .I1(cs_en2), .I2(Q[0]), .I3(rstdiv0_sync_r1_reg_rep__21), .O(\last_master_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1045" *) LUT4 #( .INIT(16'hFEAE)) \last_master_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(last_master_r[1]), .I2(cs_en2), .I3(Q[1]), .O(\last_master_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(\last_master_r[0]_i_1_n_0 ), .Q(last_master_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(\last_master_r[1]_i_1_n_0 ), .Q(last_master_r[1]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized2 (Q, mc_cas_n_ns, mc_ras_n_ns, D, \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_address_reg[14] , granted_row_r_reg, granted_row_r_reg_0, act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , \cmd_pipe_plus.mc_address_reg[10] , head_r_lcl_reg, head_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__21, sent_row, maint_zq_r, maint_srx_r, insert_maint_r1_lcl_reg, insert_maint_r1_lcl_reg_0, \grant_r_reg[1]_0 , row_cmd_wr, insert_maint_r1_lcl_reg_1, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , req_row_r, act_wait_r_lcl_reg, \generate_maint_cmds.insert_maint_r_lcl_reg , inhbt_act_faw_r, act_this_rank_r, CLK); output [1:0]Q; output [0:0]mc_cas_n_ns; output [0:0]mc_ras_n_ns; output [0:0]D; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [13:0]\cmd_pipe_plus.mc_address_reg[14] ; output granted_row_r_reg; output granted_row_r_reg_0; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output \cmd_pipe_plus.mc_address_reg[10] ; input head_r_lcl_reg; input head_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__21; input sent_row; input maint_zq_r; input maint_srx_r; input insert_maint_r1_lcl_reg; input insert_maint_r1_lcl_reg_0; input \grant_r_reg[1]_0 ; input [0:0]row_cmd_wr; input insert_maint_r1_lcl_reg_1; input [2:0]\req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [27:0]req_row_r; input act_wait_r_lcl_reg; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input inhbt_act_faw_r; input [1:0]act_this_rank_r; input CLK; wire CLK; wire [0:0]D; wire [1:0]Q; wire act_this_rank; wire [1:0]act_this_rank_r; wire act_wait_r_lcl_reg; wire \cmd_pipe_plus.mc_address_reg[10] ; wire [13:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r[0]_i_1__2_n_0 ; wire \grant_r[1]_i_1__2_n_0 ; wire \grant_r_reg[1]_0 ; wire granted_row_r_reg; wire granted_row_r_reg_0; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire insert_maint_r1_lcl_reg; wire insert_maint_r1_lcl_reg_0; wire insert_maint_r1_lcl_reg_1; wire [1:0]last_master_r; wire \last_master_r[0]_i_1__0_n_0 ; wire \last_master_r[1]_i_1__0_n_0 ; wire maint_srx_r; wire maint_zq_r; wire [0:0]mc_cas_n_ns; wire [0:0]mc_ras_n_ns; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [27:0]req_row_r; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__21; wire sent_row; LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[0]_i_1 (.I0(Q[0]), .I1(req_row_r[0]), .I2(Q[1]), .I3(req_row_r[14]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [0])); (* SOFT_HLUTNM = "soft_lutpair1046" *) LUT2 #( .INIT(4'h2)) \cmd_pipe_plus.mc_address[10]_i_2 (.I0(Q[0]), .I1(Q[1]), .O(\cmd_pipe_plus.mc_address_reg[10] )); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[11]_i_1 (.I0(Q[0]), .I1(req_row_r[10]), .I2(Q[1]), .I3(req_row_r[24]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [10])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[12]_i_1 (.I0(Q[0]), .I1(req_row_r[11]), .I2(Q[1]), .I3(req_row_r[25]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [11])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[13]_i_1 (.I0(Q[0]), .I1(req_row_r[12]), .I2(Q[1]), .I3(req_row_r[26]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [12])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[14]_i_1 (.I0(Q[0]), .I1(req_row_r[13]), .I2(Q[1]), .I3(req_row_r[27]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [13])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[1]_i_1 (.I0(Q[0]), .I1(req_row_r[1]), .I2(Q[1]), .I3(req_row_r[15]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [1])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[2]_i_1 (.I0(Q[0]), .I1(req_row_r[2]), .I2(Q[1]), .I3(req_row_r[16]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [2])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[3]_i_1 (.I0(Q[0]), .I1(req_row_r[3]), .I2(Q[1]), .I3(req_row_r[17]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [3])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[4]_i_1 (.I0(Q[0]), .I1(req_row_r[4]), .I2(Q[1]), .I3(req_row_r[18]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [4])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[5]_i_1 (.I0(Q[0]), .I1(req_row_r[5]), .I2(Q[1]), .I3(req_row_r[19]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [5])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[6]_i_1 (.I0(Q[0]), .I1(req_row_r[6]), .I2(Q[1]), .I3(req_row_r[20]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [6])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[7]_i_1 (.I0(Q[0]), .I1(req_row_r[7]), .I2(Q[1]), .I3(req_row_r[21]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [7])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[8]_i_1 (.I0(Q[0]), .I1(req_row_r[8]), .I2(Q[1]), .I3(req_row_r[22]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [8])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_address[9]_i_1 (.I0(Q[0]), .I1(req_row_r[9]), .I2(Q[1]), .I3(req_row_r[23]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_address_reg[14] [9])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_bank[0]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [0]), .I2(Q[1]), .I3(\req_bank_r_lcl_reg[2]_0 [0]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_bank_reg[2] [0])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_bank[1]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [1]), .I2(Q[1]), .I3(\req_bank_r_lcl_reg[2]_0 [1]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_bank_reg[2] [1])); LUT6 #( .INIT(64'hF808F808F808FFFF)) \cmd_pipe_plus.mc_bank[2]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [2]), .I2(Q[1]), .I3(\req_bank_r_lcl_reg[2]_0 [2]), .I4(insert_maint_r1_lcl_reg_1), .I5(sent_row), .O(\cmd_pipe_plus.mc_bank_reg[2] [2])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFE0)) \cmd_pipe_plus.mc_cas_n[0]_i_1 (.I0(maint_zq_r), .I1(maint_srx_r), .I2(insert_maint_r1_lcl_reg), .I3(Q[0]), .I4(Q[1]), .I5(insert_maint_r1_lcl_reg_0), .O(mc_cas_n_ns)); LUT6 #( .INIT(64'hAAAAAAAAAAAAFEAA)) \cmd_pipe_plus.mc_ras_n[0]_i_1 (.I0(insert_maint_r1_lcl_reg_0), .I1(maint_zq_r), .I2(maint_srx_r), .I3(insert_maint_r1_lcl_reg), .I4(Q[1]), .I5(Q[0]), .O(mc_ras_n_ns)); LUT5 #( .INIT(32'hEAEAEAFF)) \cmd_pipe_plus.mc_we_n[0]_i_1 (.I0(\grant_r_reg[1]_0 ), .I1(row_cmd_wr), .I2(Q[1]), .I3(insert_maint_r1_lcl_reg_1), .I4(sent_row), .O(D)); LUT6 #( .INIT(64'hAAAAAAAA222AAA2A)) \grant_r[0]_i_1__2 (.I0(head_r_lcl_reg_0), .I1(head_r_lcl_reg), .I2(last_master_r[0]), .I3(sent_row), .I4(Q[0]), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\grant_r[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'h2222222A2A2A222A)) \grant_r[1]_i_1__2 (.I0(head_r_lcl_reg), .I1(head_r_lcl_reg_0), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(last_master_r[1]), .I4(sent_row), .I5(Q[1]), .O(\grant_r[1]_i_1__2_n_0 )); LUT5 #( .INIT(32'hFFFFFFF8)) \grant_r[1]_i_4 (.I0(Q[0]), .I1(act_wait_r_lcl_reg), .I2(\generate_maint_cmds.insert_maint_r_lcl_reg ), .I3(inhbt_act_faw_r), .I4(Q[1]), .O(granted_row_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1046" *) LUT5 #( .INIT(32'hFFFFFFF8)) \grant_r[1]_i_5__0 (.I0(Q[1]), .I1(row_cmd_wr), .I2(\generate_maint_cmds.insert_maint_r_lcl_reg ), .I3(inhbt_act_faw_r), .I4(Q[0]), .O(granted_row_r_reg_0)); FDRE #( .INIT(1'b0)) \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1__2_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1__2_n_0 ), .Q(Q[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1047" *) LUT4 #( .INIT(16'h0777)) i___50_i_1 (.I0(act_this_rank_r[1]), .I1(Q[1]), .I2(act_this_rank_r[0]), .I3(Q[0]), .O(\inhbt_act_faw.inhbt_act_faw_r_reg )); (* SOFT_HLUTNM = "soft_lutpair1047" *) LUT4 #( .INIT(16'hF888)) \inhbt_act_faw.SRLC32E0_i_1 (.I0(Q[0]), .I1(act_this_rank_r[0]), .I2(Q[1]), .I3(act_this_rank_r[1]), .O(act_this_rank)); LUT4 #( .INIT(16'h00E2)) \last_master_r[0]_i_1__0 (.I0(last_master_r[0]), .I1(sent_row), .I2(Q[0]), .I3(rstdiv0_sync_r1_reg_rep__21), .O(\last_master_r[0]_i_1__0_n_0 )); LUT4 #( .INIT(16'hFEAE)) \last_master_r[1]_i_1__0 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(last_master_r[1]), .I2(sent_row), .I3(Q[1]), .O(\last_master_r[1]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(\last_master_r[0]_i_1__0_n_0 ), .Q(last_master_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(\last_master_r[1]_i_1__0_n_0 ), .Q(last_master_r[1]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized4 (\periodic_rd_generation.periodic_rd_timer_r_reg[0] , Q, read_this_rank, D, granted_col_r_reg, \rtw_timer.rtw_cnt_r_reg[1] , mc_odt_ns, col_rd_wr, mc_data_offset_2_ns, granted_col_r_reg_0, granted_col_r_reg_1, \wtr_timer.wtr_cnt_r_reg[2] , col_data_buf_addr, DIC, demand_priority_r_reg, \cmd_pipe_plus.mc_bank_reg[5] , demand_priority_r_reg_0, \cmd_pipe_plus.mc_address_reg[25] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , read_this_rank_r, rd_this_rank_r, granted_col_r_reg_2, rd_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, col_wait_r_reg, col_wait_r_reg_0, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, \rtw_timer.rtw_cnt_r_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_2_reg[3] , col_rd_wr_r1, rnk_config_strobe, \genblk3[2].rnk_config_strobe_r_reg , \genblk3[1].rnk_config_strobe_r_reg , ofs_rdy_r, ofs_rdy_r_0, wr_this_rank_r, req_data_buf_addr_r, col_data_buf_addr_r, \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , req_periodic_rd_r, col_periodic_rd_r, req_bank_rdy_r, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , req_bank_rdy_r_1, \req_col_r_reg[9] , \req_col_r_reg[9]_0 , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, CLK); output \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; output [1:0]Q; output read_this_rank; output [0:0]D; output granted_col_r_reg; output \rtw_timer.rtw_cnt_r_reg[1] ; output [0:0]mc_odt_ns; output col_rd_wr; output [0:0]mc_data_offset_2_ns; output granted_col_r_reg_0; output granted_col_r_reg_1; output \wtr_timer.wtr_cnt_r_reg[2] ; output [4:0]col_data_buf_addr; output [0:0]DIC; output demand_priority_r_reg; output [2:0]\cmd_pipe_plus.mc_bank_reg[5] ; output demand_priority_r_reg_0; output [7:0]\cmd_pipe_plus.mc_address_reg[25] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; input read_this_rank_r; input [1:0]rd_this_rank_r; input granted_col_r_reg_2; input rd_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input col_wait_r_reg; input col_wait_r_reg_0; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_2_reg[3] ; input col_rd_wr_r1; input rnk_config_strobe; input \genblk3[2].rnk_config_strobe_r_reg ; input \genblk3[1].rnk_config_strobe_r_reg ; input ofs_rdy_r; input ofs_rdy_r_0; input [1:0]wr_this_rank_r; input [9:0]req_data_buf_addr_r; input [0:0]col_data_buf_addr_r; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [1:0]req_periodic_rd_r; input col_periodic_rd_r; input req_bank_rdy_r; input [2:0]\req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input req_bank_rdy_r_1; input [6:0]\req_col_r_reg[9] ; input [6:0]\req_col_r_reg[9]_0 ; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input CLK; wire CLK; wire [0:0]D; wire [0:0]DIC; wire [1:0]Q; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire [7:0]\cmd_pipe_plus.mc_address_reg[25] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_2_reg[3] ; wire [4:0]col_data_buf_addr; wire [0:0]col_data_buf_addr_r; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r1; wire col_wait_r_reg; wire col_wait_r_reg_0; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire \genblk3[1].rnk_config_strobe_r_reg ; wire \genblk3[2].rnk_config_strobe_r_reg ; wire \grant_r[0]_i_1__0_n_0 ; wire \grant_r[1]_i_1__0_n_0 ; wire granted_col_r_reg; wire granted_col_r_reg_0; wire granted_col_r_reg_1; wire granted_col_r_reg_2; wire [1:0]last_master_r; wire \last_master_r[0]_i_1__1_n_0 ; wire \last_master_r[1]_i_1__1_n_0 ; wire [0:0]mc_data_offset_2_ns; wire [0:0]mc_odt_ns; wire ofs_rdy_r; wire ofs_rdy_r_0; wire \periodic_rd_generation.periodic_rd_timer_r_reg[0] ; wire [1:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire read_this_rank; wire read_this_rank_r; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire req_bank_rdy_r; wire req_bank_rdy_r_1; wire [6:0]\req_col_r_reg[9] ; wire [6:0]\req_col_r_reg[9]_0 ; wire [9:0]req_data_buf_addr_r; wire [1:0]req_periodic_rd_r; wire rnk_config_strobe; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [1:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[2] ; LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[18]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [0]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [0]), .O(\cmd_pipe_plus.mc_address_reg[25] [0])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[19]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [1]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [1]), .O(\cmd_pipe_plus.mc_address_reg[25] [1])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[20]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [2]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [2]), .O(\cmd_pipe_plus.mc_address_reg[25] [2])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[21]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [3]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [3]), .O(\cmd_pipe_plus.mc_address_reg[25] [3])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[22]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [4]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [4]), .O(\cmd_pipe_plus.mc_address_reg[25] [4])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[23]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [5]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [5]), .O(\cmd_pipe_plus.mc_address_reg[25] [5])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[24]_i_1 (.I0(Q[0]), .I1(\req_col_r_reg[9] [6]), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(\req_col_r_reg[9]_0 [6]), .O(\cmd_pipe_plus.mc_address_reg[25] [6])); LUT5 #( .INIT(32'hFF8F0F8F)) \cmd_pipe_plus.mc_address[25]_i_1 (.I0(Q[0]), .I1(auto_pre_r_lcl_reg), .I2(granted_col_r_reg_2), .I3(Q[1]), .I4(auto_pre_r_lcl_reg_0), .O(\cmd_pipe_plus.mc_address_reg[25] [7])); LUT5 #( .INIT(32'hFF0F8F8F)) \cmd_pipe_plus.mc_bank[3]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [0]), .I2(granted_col_r_reg_2), .I3(\req_bank_r_lcl_reg[2]_0 [0]), .I4(Q[1]), .O(\cmd_pipe_plus.mc_bank_reg[5] [0])); LUT5 #( .INIT(32'hFF0F8F8F)) \cmd_pipe_plus.mc_bank[4]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [1]), .I2(granted_col_r_reg_2), .I3(\req_bank_r_lcl_reg[2]_0 [1]), .I4(Q[1]), .O(\cmd_pipe_plus.mc_bank_reg[5] [1])); LUT5 #( .INIT(32'hFF0F8F8F)) \cmd_pipe_plus.mc_bank[5]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [2]), .I2(granted_col_r_reg_2), .I3(\req_bank_r_lcl_reg[2]_0 [2]), .I4(Q[1]), .O(\cmd_pipe_plus.mc_bank_reg[5] [2])); LUT6 #( .INIT(64'h77775F5577775FFF)) \cmd_pipe_plus.mc_data_offset[5]_i_1 (.I0(granted_col_r_reg_2), .I1(rd_wr_r_lcl_reg), .I2(rd_wr_r_lcl_reg_0), .I3(Q[0]), .I4(Q[1]), .I5(col_rd_wr_r1), .O(\cmd_pipe_plus.mc_data_offset_1_reg[0] )); LUT6 #( .INIT(64'h00020A02A0A2AAA2)) \cmd_pipe_plus.mc_data_offset_2[3]_i_1 (.I0(granted_col_r_reg_2), .I1(col_rd_wr_r1), .I2(Q[1]), .I3(Q[0]), .I4(rd_wr_r_lcl_reg_0), .I5(rd_wr_r_lcl_reg), .O(mc_data_offset_2_ns)); LUT3 #( .INIT(8'hBA)) \cmd_pipe_plus.mc_odt[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[3] ), .I1(col_rd_wr), .I2(granted_col_r_reg_2), .O(mc_odt_ns)); LUT5 #( .INIT(32'hDFD5D5D5)) \cmd_pipe_plus.mc_we_n[1]_i_1 (.I0(granted_col_r_reg_2), .I1(rd_wr_r_lcl_reg), .I2(Q[1]), .I3(rd_wr_r_lcl_reg_0), .I4(Q[0]), .O(D)); (* SOFT_HLUTNM = "soft_lutpair1043" *) LUT3 #( .INIT(8'h08)) demand_priority_r_i_5 (.I0(req_bank_rdy_r), .I1(granted_col_r_reg_2), .I2(Q[0]), .O(demand_priority_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1044" *) LUT3 #( .INIT(8'h08)) demand_priority_r_i_5__0 (.I0(req_bank_rdy_r_1), .I1(granted_col_r_reg_2), .I2(Q[1]), .O(demand_priority_r_reg_0)); LUT6 #( .INIT(64'hAAAAAAAA222AAA2A)) \grant_r[0]_i_1__0 (.I0(col_wait_r_reg), .I1(col_wait_r_reg_0), .I2(last_master_r[0]), .I3(granted_col_r_reg_2), .I4(Q[0]), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\grant_r[0]_i_1__0_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \grant_r[1]_i_11 (.I0(rnk_config_strobe), .I1(\genblk3[2].rnk_config_strobe_r_reg ), .I2(\genblk3[1].rnk_config_strobe_r_reg ), .I3(ofs_rdy_r_0), .I4(Q[0]), .O(granted_col_r_reg_1)); LUT6 #( .INIT(64'h2222222A2A2A222A)) \grant_r[1]_i_1__0 (.I0(col_wait_r_reg_0), .I1(col_wait_r_reg), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(last_master_r[1]), .I4(granted_col_r_reg_2), .I5(Q[1]), .O(\grant_r[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFFFF0000FFFF07F7)) \grant_r[1]_i_6 (.I0(Q[0]), .I1(rd_wr_r_lcl_reg_0), .I2(Q[1]), .I3(rd_wr_r_lcl_reg), .I4(rstdiv0_sync_r1_reg_rep__21), .I5(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .O(granted_col_r_reg)); LUT5 #( .INIT(32'hFFFFFEFF)) \grant_r[1]_i_9 (.I0(rnk_config_strobe), .I1(\genblk3[2].rnk_config_strobe_r_reg ), .I2(\genblk3[1].rnk_config_strobe_r_reg ), .I3(ofs_rdy_r), .I4(Q[1]), .O(granted_col_r_reg_0)); FDRE #( .INIT(1'b0)) \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1__0_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1__0_n_0 ), .Q(Q[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1042" *) LUT5 #( .INIT(32'hAA808080)) i___25_i_1 (.I0(read_this_rank_r), .I1(Q[0]), .I2(rd_this_rank_r[0]), .I3(Q[1]), .I4(rd_this_rank_r[1]), .O(\periodic_rd_generation.periodic_rd_timer_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1043" *) LUT4 #( .INIT(16'h00E2)) \last_master_r[0]_i_1__1 (.I0(last_master_r[0]), .I1(granted_col_r_reg_2), .I2(Q[0]), .I3(rstdiv0_sync_r1_reg_rep__21), .O(\last_master_r[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1044" *) LUT4 #( .INIT(16'hFEAE)) \last_master_r[1]_i_1__1 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(last_master_r[1]), .I2(granted_col_r_reg_2), .I3(Q[1]), .O(\last_master_r[1]_i_1__1_n_0 )); FDRE #( .INIT(1'b0)) \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(\last_master_r[0]_i_1__1_n_0 ), .Q(last_master_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(\last_master_r[1]_i_1__1_n_0 ), .Q(last_master_r[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1041" *) LUT5 #( .INIT(32'hAACFAAC0)) \offset_pipe_0.col_rd_wr_r1_i_1 (.I0(rd_wr_r_lcl_reg), .I1(rd_wr_r_lcl_reg_0), .I2(Q[0]), .I3(Q[1]), .I4(col_rd_wr_r1), .O(col_rd_wr)); (* SOFT_HLUTNM = "soft_lutpair1042" *) LUT4 #( .INIT(16'hF888)) \periodic_rd_generation.read_this_rank_r_i_1 (.I0(Q[0]), .I1(rd_this_rank_r[0]), .I2(Q[1]), .I3(rd_this_rank_r[1]), .O(read_this_rank)); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_1 (.I0(req_data_buf_addr_r[9]), .I1(Q[1]), .I2(req_data_buf_addr_r[4]), .I3(Q[0]), .I4(col_data_buf_addr_r), .O(col_data_buf_addr[4])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_2 (.I0(req_data_buf_addr_r[8]), .I1(Q[1]), .I2(req_data_buf_addr_r[3]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [3]), .O(col_data_buf_addr[3])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_3 (.I0(req_data_buf_addr_r[7]), .I1(Q[1]), .I2(req_data_buf_addr_r[2]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [2]), .O(col_data_buf_addr[2])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_4 (.I0(req_data_buf_addr_r[6]), .I1(Q[1]), .I2(req_data_buf_addr_r[1]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [1]), .O(col_data_buf_addr[1])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_5 (.I0(req_data_buf_addr_r[5]), .I1(Q[1]), .I2(req_data_buf_addr_r[0]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [0]), .O(col_data_buf_addr[0])); LUT6 #( .INIT(64'hB888B888B8BBB888)) \read_fifo.fifo_ram[1].RAM32M0_i_1 (.I0(req_periodic_rd_r[1]), .I1(Q[1]), .I2(req_periodic_rd_r[0]), .I3(Q[0]), .I4(col_periodic_rd_r), .I5(rstdiv0_sync_r1_reg_rep__21), .O(DIC)); (* SOFT_HLUTNM = "soft_lutpair1041" *) LUT4 #( .INIT(16'h07F7)) \rtw_timer.rtw_cnt_r[1]_i_2 (.I0(Q[0]), .I1(rd_wr_r_lcl_reg_0), .I2(Q[1]), .I3(rd_wr_r_lcl_reg), .O(\rtw_timer.rtw_cnt_r_reg[1] )); LUT4 #( .INIT(16'hF888)) \wtr_timer.wtr_cnt_r[2]_i_2 (.I0(wr_this_rank_r[0]), .I1(Q[0]), .I2(wr_this_rank_r[1]), .I3(Q[1]), .O(\wtr_timer.wtr_cnt_r_reg[2] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_tempmon" *) module ddr3_ifmig_7series_v4_0_tempmon (out, D, mmcm_clk, in0, CLK); output [11:0]out; output [11:0]D; input mmcm_clk; input in0; input CLK; wire CLK; wire [11:0]D; wire \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ; wire \device_temp_101[11]_i_4_n_0 ; wire \device_temp_101[11]_i_5_n_0 ; wire \device_temp_101[11]_i_6_n_0 ; wire \device_temp_101[11]_i_7_n_0 ; wire \device_temp_101[11]_i_8_n_0 ; wire [11:0]device_temp_lcl; (* async_reg = "true" *) wire [11:0]device_temp_r; wire \device_temp_r[11]_i_1_n_0 ; (* async_reg = "true" *) wire [11:0]device_temp_sync_r1; (* async_reg = "true" *) wire [11:0]device_temp_sync_r2; (* async_reg = "true" *) (* syn_srlstyle = "registers" *) wire [11:0]device_temp_sync_r3; (* async_reg = "true" *) wire [11:0]device_temp_sync_r4; wire device_temp_sync_r4_neq_r3; wire device_temp_sync_r4_neq_r3_i_2_n_0; wire device_temp_sync_r4_neq_r3_i_3_n_0; wire device_temp_sync_r4_neq_r3_i_4_n_0; wire device_temp_sync_r4_neq_r3_i_5_n_0; wire device_temp_sync_r4_neq_r3_reg_i_1_n_0; wire device_temp_sync_r4_neq_r3_reg_i_1_n_1; wire device_temp_sync_r4_neq_r3_reg_i_1_n_2; wire device_temp_sync_r4_neq_r3_reg_i_1_n_3; (* async_reg = "true" *) wire [11:0]device_temp_sync_r5; wire in0; wire mmcm_clk; wire [11:0]p_0_in; wire [10:1]p_0_in__0; wire [1:0]p_0_in__1; (* async_reg = "true" *) wire rst_r1; (* async_reg = "true" *) wire rst_r2; wire sample_en; wire sample_en0; wire sample_timer0; wire sample_timer_en; wire sync_cntr0; wire \sync_cntr[2]_i_1_n_0 ; wire \sync_cntr[3]_i_2_n_0 ; wire \sync_cntr[3]_i_3_n_0 ; wire [3:0]sync_cntr_reg__0; (* RTL_KEEP = "yes" *) wire temperature; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ; wire xadc_den; wire [15:0]xadc_do; wire xadc_drdy; wire xadc_drdy_r; wire \xadc_supplied_temperature.sample_en_i_2_n_0 ; wire \xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ; wire \xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ; wire \xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ; wire \xadc_supplied_temperature.sample_timer_en_i_1_n_0 ; wire [10:0]\xadc_supplied_temperature.sample_timer_reg__0 ; wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED; wire \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ; wire [7:0]\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ; wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ; wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ; assign out[11:0] = device_temp_r; LUT6 #( .INIT(64'hFFFFFEEEFEEEFEEE)) \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1 (.I0(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .I1(temperature), .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .I3(sample_en), .I4(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .I5(xadc_drdy_r), .O(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 )); (* KEEP = "yes" *) FDSE #( .INIT(1'b1)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(temperature), .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .S(rst_r2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .R(rst_r2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .R(rst_r2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .Q(temperature), .R(rst_r2)); LUT3 #( .INIT(8'h10)) \device_temp_101[0]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[0]), .O(D[0])); LUT3 #( .INIT(8'hBA)) \device_temp_101[10]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[10]), .O(D[10])); LUT3 #( .INIT(8'hFE)) \device_temp_101[11]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[11]), .O(D[11])); LUT6 #( .INIT(64'h0000000011111115)) \device_temp_101[11]_i_2 (.I0(\device_temp_101[11]_i_4_n_0 ), .I1(device_temp_r[11]), .I2(device_temp_r[8]), .I3(device_temp_r[10]), .I4(device_temp_r[9]), .I5(\device_temp_101[11]_i_5_n_0 ), .O(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low )); LUT5 #( .INIT(32'h0000FD55)) \device_temp_101[11]_i_3 (.I0(\device_temp_101[11]_i_6_n_0 ), .I1(device_temp_r[1]), .I2(device_temp_r[0]), .I3(device_temp_r[2]), .I4(\device_temp_101[11]_i_7_n_0 ), .O(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high )); LUT4 #( .INIT(16'h8000)) \device_temp_101[11]_i_4 (.I0(device_temp_r[4]), .I1(device_temp_r[11]), .I2(device_temp_r[7]), .I3(device_temp_r[5]), .O(\device_temp_101[11]_i_4_n_0 )); LUT6 #( .INIT(64'hE000A000A000A000)) \device_temp_101[11]_i_5 (.I0(device_temp_r[6]), .I1(device_temp_r[5]), .I2(device_temp_r[7]), .I3(device_temp_r[11]), .I4(device_temp_r[2]), .I5(device_temp_r[3]), .O(\device_temp_101[11]_i_5_n_0 )); LUT5 #( .INIT(32'h00000001)) \device_temp_101[11]_i_6 (.I0(device_temp_r[6]), .I1(device_temp_r[9]), .I2(device_temp_r[8]), .I3(device_temp_r[4]), .I4(device_temp_r[3]), .O(\device_temp_101[11]_i_6_n_0 )); LUT6 #( .INIT(64'h7F777F777F77FF77)) \device_temp_101[11]_i_7 (.I0(device_temp_r[11]), .I1(device_temp_r[10]), .I2(device_temp_r[7]), .I3(\device_temp_101[11]_i_8_n_0 ), .I4(device_temp_r[6]), .I5(device_temp_r[5]), .O(\device_temp_101[11]_i_7_n_0 )); LUT2 #( .INIT(4'h1)) \device_temp_101[11]_i_8 (.I0(device_temp_r[9]), .I1(device_temp_r[8]), .O(\device_temp_101[11]_i_8_n_0 )); LUT3 #( .INIT(8'h10)) \device_temp_101[1]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[1]), .O(D[1])); LUT3 #( .INIT(8'hFE)) \device_temp_101[2]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[2]), .O(D[2])); LUT3 #( .INIT(8'hDC)) \device_temp_101[3]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[3]), .O(D[3])); LUT3 #( .INIT(8'h10)) \device_temp_101[4]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[4]), .O(D[4])); LUT3 #( .INIT(8'hFE)) \device_temp_101[5]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[5]), .O(D[5])); LUT3 #( .INIT(8'h10)) \device_temp_101[6]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[6]), .O(D[6])); LUT3 #( .INIT(8'hFE)) \device_temp_101[7]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[7]), .O(D[7])); LUT3 #( .INIT(8'h10)) \device_temp_101[8]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[8]), .O(D[8])); LUT3 #( .INIT(8'h10)) \device_temp_101[9]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[9]), .O(D[9])); LUT4 #( .INIT(16'h8000)) \device_temp_r[11]_i_1 (.I0(sync_cntr_reg__0[3]), .I1(sync_cntr_reg__0[2]), .I2(sync_cntr_reg__0[0]), .I3(sync_cntr_reg__0[1]), .O(\device_temp_r[11]_i_1_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[0] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[0]), .Q(device_temp_r[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[10] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[10]), .Q(device_temp_r[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[11] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[11]), .Q(device_temp_r[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[1] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[1]), .Q(device_temp_r[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[2] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[2]), .Q(device_temp_r[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[3] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[3]), .Q(device_temp_r[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[4] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[4]), .Q(device_temp_r[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[5] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[5]), .Q(device_temp_r[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[6] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[6]), .Q(device_temp_r[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[7] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[7]), .Q(device_temp_r[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[8] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[8]), .Q(device_temp_r[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_r_reg[9] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[9]), .Q(device_temp_r[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[0]), .Q(device_temp_sync_r1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[10]), .Q(device_temp_sync_r1[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[11]), .Q(device_temp_sync_r1[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[1]), .Q(device_temp_sync_r1[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[2]), .Q(device_temp_sync_r1[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[3]), .Q(device_temp_sync_r1[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[4]), .Q(device_temp_sync_r1[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[5]), .Q(device_temp_sync_r1[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[6]), .Q(device_temp_sync_r1[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[7]), .Q(device_temp_sync_r1[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[8]), .Q(device_temp_sync_r1[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r1_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[9]), .Q(device_temp_sync_r1[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[0]), .Q(device_temp_sync_r2[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[10]), .Q(device_temp_sync_r2[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[11]), .Q(device_temp_sync_r2[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[1]), .Q(device_temp_sync_r2[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[2]), .Q(device_temp_sync_r2[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[3]), .Q(device_temp_sync_r2[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[4]), .Q(device_temp_sync_r2[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[5]), .Q(device_temp_sync_r2[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[6]), .Q(device_temp_sync_r2[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[7]), .Q(device_temp_sync_r2[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[8]), .Q(device_temp_sync_r2[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r2_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[9]), .Q(device_temp_sync_r2[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[0]), .Q(device_temp_sync_r3[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[10]), .Q(device_temp_sync_r3[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[11]), .Q(device_temp_sync_r3[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[1]), .Q(device_temp_sync_r3[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[2]), .Q(device_temp_sync_r3[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[3]), .Q(device_temp_sync_r3[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[4]), .Q(device_temp_sync_r3[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[5]), .Q(device_temp_sync_r3[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[6]), .Q(device_temp_sync_r3[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[7]), .Q(device_temp_sync_r3[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[8]), .Q(device_temp_sync_r3[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r3_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[9]), .Q(device_temp_sync_r3[9]), .R(1'b0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_2 (.I0(device_temp_sync_r4[9]), .I1(device_temp_sync_r3[9]), .I2(device_temp_sync_r3[11]), .I3(device_temp_sync_r4[11]), .I4(device_temp_sync_r3[10]), .I5(device_temp_sync_r4[10]), .O(device_temp_sync_r4_neq_r3_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_3 (.I0(device_temp_sync_r4[6]), .I1(device_temp_sync_r3[6]), .I2(device_temp_sync_r3[8]), .I3(device_temp_sync_r4[8]), .I4(device_temp_sync_r3[7]), .I5(device_temp_sync_r4[7]), .O(device_temp_sync_r4_neq_r3_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_4 (.I0(device_temp_sync_r4[3]), .I1(device_temp_sync_r3[3]), .I2(device_temp_sync_r3[5]), .I3(device_temp_sync_r4[5]), .I4(device_temp_sync_r3[4]), .I5(device_temp_sync_r4[4]), .O(device_temp_sync_r4_neq_r3_i_4_n_0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_5 (.I0(device_temp_sync_r4[0]), .I1(device_temp_sync_r3[0]), .I2(device_temp_sync_r3[2]), .I3(device_temp_sync_r4[2]), .I4(device_temp_sync_r3[1]), .I5(device_temp_sync_r4[1]), .O(device_temp_sync_r4_neq_r3_i_5_n_0)); FDRE #( .INIT(1'b0)) device_temp_sync_r4_neq_r3_reg (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0), .Q(device_temp_sync_r4_neq_r3), .R(1'b0)); CARRY4 device_temp_sync_r4_neq_r3_reg_i_1 (.CI(1'b0), .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]), .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0})); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[0]), .Q(device_temp_sync_r4[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[10]), .Q(device_temp_sync_r4[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[11]), .Q(device_temp_sync_r4[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[1]), .Q(device_temp_sync_r4[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[2]), .Q(device_temp_sync_r4[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[3]), .Q(device_temp_sync_r4[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[4]), .Q(device_temp_sync_r4[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[5]), .Q(device_temp_sync_r4[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[6]), .Q(device_temp_sync_r4[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[7]), .Q(device_temp_sync_r4[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[8]), .Q(device_temp_sync_r4[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r4_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[9]), .Q(device_temp_sync_r4[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[0]), .Q(device_temp_sync_r5[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[10]), .Q(device_temp_sync_r5[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[11]), .Q(device_temp_sync_r5[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[1]), .Q(device_temp_sync_r5[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[2]), .Q(device_temp_sync_r5[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[3]), .Q(device_temp_sync_r5[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[4]), .Q(device_temp_sync_r5[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[5]), .Q(device_temp_sync_r5[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[6]), .Q(device_temp_sync_r5[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[7]), .Q(device_temp_sync_r5[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[8]), .Q(device_temp_sync_r5[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \device_temp_sync_r5_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[9]), .Q(device_temp_sync_r5[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT1 #( .INIT(2'h1)) \sync_cntr[0]_i_1 (.I0(sync_cntr_reg__0[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \sync_cntr[1]_i_1 (.I0(sync_cntr_reg__0[0]), .I1(sync_cntr_reg__0[1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'h78)) \sync_cntr[2]_i_1 (.I0(sync_cntr_reg__0[1]), .I1(sync_cntr_reg__0[0]), .I2(sync_cntr_reg__0[2]), .O(\sync_cntr[2]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \sync_cntr[3]_i_1 (.I0(in0), .I1(device_temp_sync_r4_neq_r3), .O(sync_cntr0)); LUT4 #( .INIT(16'h7FFF)) \sync_cntr[3]_i_2 (.I0(sync_cntr_reg__0[1]), .I1(sync_cntr_reg__0[0]), .I2(sync_cntr_reg__0[2]), .I3(sync_cntr_reg__0[3]), .O(\sync_cntr[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h7F80)) \sync_cntr[3]_i_3 (.I0(sync_cntr_reg__0[2]), .I1(sync_cntr_reg__0[0]), .I2(sync_cntr_reg__0[1]), .I3(sync_cntr_reg__0[3]), .O(\sync_cntr[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \sync_cntr_reg[0] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(p_0_in__1[0]), .Q(sync_cntr_reg__0[0]), .R(sync_cntr0)); FDRE #( .INIT(1'b0)) \sync_cntr_reg[1] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(p_0_in__1[1]), .Q(sync_cntr_reg__0[1]), .R(sync_cntr0)); FDRE #( .INIT(1'b0)) \sync_cntr_reg[2] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(\sync_cntr[2]_i_1_n_0 ), .Q(sync_cntr_reg__0[2]), .R(sync_cntr0)); FDRE #( .INIT(1'b0)) \sync_cntr_reg[3] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(\sync_cntr[3]_i_3_n_0 ), .Q(sync_cntr_reg__0[3]), .R(sync_cntr0)); (* box_type = "PRIMITIVE" *) XADC #( .INIT_40(16'h1000), .INIT_41(16'h2FFF), .INIT_42(16'h0800), .INIT_43(16'h0000), .INIT_44(16'h0000), .INIT_45(16'h0000), .INIT_46(16'h0000), .INIT_47(16'h0000), .INIT_48(16'h0101), .INIT_49(16'h0000), .INIT_4A(16'h0100), .INIT_4B(16'h0000), .INIT_4C(16'h0000), .INIT_4D(16'h0000), .INIT_4E(16'h0000), .INIT_4F(16'h0000), .INIT_50(16'hB5ED), .INIT_51(16'h57E4), .INIT_52(16'hA147), .INIT_53(16'hCA33), .INIT_54(16'hA93A), .INIT_55(16'h52C6), .INIT_56(16'h9555), .INIT_57(16'hAE4E), .INIT_58(16'h5999), .INIT_59(16'h0000), .INIT_5A(16'h0000), .INIT_5B(16'h0000), .INIT_5C(16'h5111), .INIT_5D(16'h0000), .INIT_5E(16'h0000), .INIT_5F(16'h0000), .IS_CONVSTCLK_INVERTED(1'b0), .IS_DCLK_INVERTED(1'b0), .SIM_DEVICE("7SERIES"), .SIM_MONITOR_FILE("design.txt")) \xadc_supplied_temperature.XADC_inst (.ALM(\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]), .BUSY(\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ), .CHANNEL(\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]), .CONVST(1'b0), .CONVSTCLK(1'b0), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(mmcm_clk), .DEN(xadc_den), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(xadc_do), .DRDY(xadc_drdy), .DWE(1'b0), .EOC(\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ), .EOS(\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ), .JTAGBUSY(\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ), .JTAGLOCKED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ), .JTAGMODIFIED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ), .MUXADDR(\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]), .OT(\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ), .RESET(1'b0), .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .VN(1'b0), .VP(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.rst_r1_reg (.C(mmcm_clk), .CE(1'b1), .D(in0), .Q(rst_r1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.rst_r2_reg (.C(mmcm_clk), .CE(1'b1), .D(rst_r1), .Q(rst_r2), .R(1'b0)); LUT6 #( .INIT(64'h0000020000000000)) \xadc_supplied_temperature.sample_en_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I5(\xadc_supplied_temperature.sample_en_i_2_n_0 ), .O(sample_en0)); LUT6 #( .INIT(64'h0080000000000000)) \xadc_supplied_temperature.sample_en_i_2 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [10]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .O(\xadc_supplied_temperature.sample_en_i_2_n_0 )); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_en_reg (.C(mmcm_clk), .CE(1'b1), .D(sample_en0), .Q(sample_en), .R(1'b0)); LUT1 #( .INIT(2'h1)) \xadc_supplied_temperature.sample_timer[0]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .O(\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \xadc_supplied_temperature.sample_timer[10]_i_1 (.I0(rst_r2), .I1(xadc_den), .O(sample_timer0)); LUT6 #( .INIT(64'hF7FFFFFF08000000)) \xadc_supplied_temperature.sample_timer[10]_i_2 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [10]), .O(p_0_in__0[10])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \xadc_supplied_temperature.sample_timer[10]_i_3 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .O(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \xadc_supplied_temperature.sample_timer[1]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h78)) \xadc_supplied_temperature.sample_timer[2]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h7F80)) \xadc_supplied_temperature.sample_timer[3]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'h7FFF8000)) \xadc_supplied_temperature.sample_timer[4]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \xadc_supplied_temperature.sample_timer[5]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h9)) \xadc_supplied_temperature.sample_timer[6]_i_1 (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( .INIT(8'hD2)) \xadc_supplied_temperature.sample_timer[7]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'hDF20)) \xadc_supplied_temperature.sample_timer[8]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .O(p_0_in__0[8])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'hF7FF0800)) \xadc_supplied_temperature.sample_timer[9]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .O(p_0_in__0[9])); LUT4 #( .INIT(16'h000E)) \xadc_supplied_temperature.sample_timer_clr_i_1 (.I0(xadc_den), .I1(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .I3(rst_r2), .O(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 )); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_clr_reg (.C(mmcm_clk), .CE(1'b1), .D(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ), .Q(xadc_den), .R(1'b0)); LUT5 #( .INIT(32'h000000FE)) \xadc_supplied_temperature.sample_timer_en_i_1 (.I0(sample_timer_en), .I1(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .I2(temperature), .I3(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .I4(rst_r2), .O(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 )); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_en_reg (.C(mmcm_clk), .CE(1'b1), .D(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ), .Q(sample_timer_en), .R(1'b0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[0] (.C(mmcm_clk), .CE(sample_timer_en), .D(\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[10] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[10]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [10]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[1] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[1]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[2] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[2]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[3] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[3]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[4] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[4]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[5] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[5]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[6] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[6]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[7] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[7]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[8] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[8]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[9] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[9]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[0] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[0]), .Q(device_temp_lcl[0]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[10] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[10]), .Q(device_temp_lcl[10]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[11] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[11]), .Q(device_temp_lcl[11]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[1] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[1]), .Q(device_temp_lcl[1]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[2] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[2]), .Q(device_temp_lcl[2]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[3] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[3]), .Q(device_temp_lcl[3]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[4] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[4]), .Q(device_temp_lcl[4]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[5] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[5]), .Q(device_temp_lcl[5]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[6] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[6]), .Q(device_temp_lcl[6]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[7] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[7]), .Q(device_temp_lcl[7]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[8] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[8]), .Q(device_temp_lcl[8]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[9] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[9]), .Q(device_temp_lcl[9]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[10] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[10]), .Q(p_0_in[6]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[11] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[11]), .Q(p_0_in[7]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[12] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[12]), .Q(p_0_in[8]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[13] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[13]), .Q(p_0_in[9]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[14] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[14]), .Q(p_0_in[10]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[15] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[15]), .Q(p_0_in[11]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[4] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[4]), .Q(p_0_in[0]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[5] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[5]), .Q(p_0_in[1]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[6] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[6]), .Q(p_0_in[2]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[7] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[7]), .Q(p_0_in[3]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[8] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[8]), .Q(p_0_in[4]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[9] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[9]), .Q(p_0_in[5]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_drdy_r_reg (.C(mmcm_clk), .CE(1'b1), .D(xadc_drdy), .Q(xadc_drdy_r), .R(rst_r2)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ui_cmd" *) module ddr3_ifmig_7series_v4_0_ui_cmd (E, app_en_r1, app_hi_pri_r2, hi_priority, cmd, p_28_out, rb_hit_busy_r_reg, p_67_out, rb_hit_busy_r_reg_0, \req_bank_r_lcl_reg[2] , \wr_req_counter.wr_req_cnt_r_reg[4] , \wr_req_counter.wr_req_cnt_r_reg[3] , wr_accepted, \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] , rd_accepted, use_addr, \req_data_buf_addr_r_reg[4] , \req_row_r_lcl_reg[14] , \req_col_r_reg[9] , app_rdy_ns, CLK, app_en_ns1, mc_app_cmd, idle_ns, \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , reset_reg, p_0_in, wr_req_cnt_r, Q, wr_data_buf_addr, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , app_rdy_r_reg_0, \axaddr_incr_reg[29] ); output [0:0]E; output app_en_r1; output app_hi_pri_r2; output hi_priority; output [1:0]cmd; output p_28_out; output rb_hit_busy_r_reg; output p_67_out; output rb_hit_busy_r_reg_0; output [2:0]\req_bank_r_lcl_reg[2] ; output \wr_req_counter.wr_req_cnt_r_reg[4] ; output \wr_req_counter.wr_req_cnt_r_reg[3] ; output wr_accepted; output \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ; output rd_accepted; output use_addr; output [4:0]\req_data_buf_addr_r_reg[4] ; output [14:0]\req_row_r_lcl_reg[14] ; output [6:0]\req_col_r_reg[9] ; input app_rdy_ns; input CLK; input app_en_ns1; input [0:0]mc_app_cmd; input [1:0]idle_ns; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input reset_reg; input [0:0]p_0_in; input [1:0]wr_req_cnt_r; input [1:0]Q; input [3:0]wr_data_buf_addr; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [0:0]app_rdy_r_reg_0; input [24:0]\axaddr_incr_reg[29] ; wire CLK; wire [0:0]E; wire [1:0]Q; wire \app_addr_r1_reg_n_0_[13] ; wire \app_addr_r1_reg_n_0_[14] ; wire \app_addr_r1_reg_n_0_[15] ; wire \app_addr_r1_reg_n_0_[16] ; wire \app_addr_r1_reg_n_0_[17] ; wire \app_addr_r1_reg_n_0_[18] ; wire \app_addr_r1_reg_n_0_[19] ; wire \app_addr_r1_reg_n_0_[20] ; wire \app_addr_r1_reg_n_0_[21] ; wire \app_addr_r1_reg_n_0_[22] ; wire \app_addr_r1_reg_n_0_[23] ; wire \app_addr_r1_reg_n_0_[24] ; wire \app_addr_r1_reg_n_0_[25] ; wire \app_addr_r1_reg_n_0_[26] ; wire \app_addr_r1_reg_n_0_[27] ; wire \app_addr_r1_reg_n_0_[3] ; wire \app_addr_r1_reg_n_0_[4] ; wire \app_addr_r1_reg_n_0_[5] ; wire \app_addr_r1_reg_n_0_[6] ; wire \app_addr_r1_reg_n_0_[7] ; wire \app_addr_r1_reg_n_0_[8] ; wire \app_addr_r1_reg_n_0_[9] ; wire \app_addr_r2_reg_n_0_[13] ; wire \app_addr_r2_reg_n_0_[14] ; wire \app_addr_r2_reg_n_0_[15] ; wire \app_addr_r2_reg_n_0_[16] ; wire \app_addr_r2_reg_n_0_[17] ; wire \app_addr_r2_reg_n_0_[18] ; wire \app_addr_r2_reg_n_0_[19] ; wire \app_addr_r2_reg_n_0_[20] ; wire \app_addr_r2_reg_n_0_[21] ; wire \app_addr_r2_reg_n_0_[22] ; wire \app_addr_r2_reg_n_0_[23] ; wire \app_addr_r2_reg_n_0_[24] ; wire \app_addr_r2_reg_n_0_[25] ; wire \app_addr_r2_reg_n_0_[26] ; wire \app_addr_r2_reg_n_0_[27] ; wire \app_addr_r2_reg_n_0_[3] ; wire \app_addr_r2_reg_n_0_[4] ; wire \app_addr_r2_reg_n_0_[5] ; wire \app_addr_r2_reg_n_0_[6] ; wire \app_addr_r2_reg_n_0_[7] ; wire \app_addr_r2_reg_n_0_[8] ; wire \app_addr_r2_reg_n_0_[9] ; wire [0:0]app_cmd_r1; wire \app_cmd_r1[0]_i_1_n_0 ; wire [1:0]app_cmd_r2; wire app_en_ns1; wire app_en_ns2; wire app_en_r1; wire app_en_r2; wire app_hi_pri_r2; wire app_rdy_ns; wire [0:0]app_rdy_r_reg_0; wire [24:0]\axaddr_incr_reg[29] ; wire [1:0]cmd; wire hi_priority; wire [1:0]idle_ns; wire [0:0]mc_app_cmd; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ; wire [0:0]p_0_in; wire [2:0]p_0_in_0; wire [2:0]p_1_in; wire p_28_out; wire p_67_out; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rd_accepted; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [6:0]\req_col_r_reg[9] ; wire [4:0]\req_data_buf_addr_r_reg[4] ; wire [14:0]\req_row_r_lcl_reg[14] ; wire reset_reg; wire use_addr; wire wr_accepted; wire [3:0]wr_data_buf_addr; wire [1:0]wr_req_cnt_r; wire \wr_req_counter.wr_req_cnt_r_reg[3] ; wire \wr_req_counter.wr_req_cnt_r_reg[4] ; FDRE #( .INIT(1'b0)) \app_addr_r1_reg[10] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [7]), .Q(p_1_in[0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[11] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [8]), .Q(p_1_in[1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[12] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [9]), .Q(p_1_in[2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[13] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [10]), .Q(\app_addr_r1_reg_n_0_[13] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[14] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [11]), .Q(\app_addr_r1_reg_n_0_[14] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[15] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [12]), .Q(\app_addr_r1_reg_n_0_[15] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[16] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [13]), .Q(\app_addr_r1_reg_n_0_[16] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[17] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [14]), .Q(\app_addr_r1_reg_n_0_[17] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[18] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [15]), .Q(\app_addr_r1_reg_n_0_[18] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[19] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [16]), .Q(\app_addr_r1_reg_n_0_[19] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[20] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [17]), .Q(\app_addr_r1_reg_n_0_[20] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[21] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [18]), .Q(\app_addr_r1_reg_n_0_[21] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[22] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [19]), .Q(\app_addr_r1_reg_n_0_[22] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[23] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [20]), .Q(\app_addr_r1_reg_n_0_[23] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[24] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [21]), .Q(\app_addr_r1_reg_n_0_[24] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[25] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [22]), .Q(\app_addr_r1_reg_n_0_[25] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[26] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [23]), .Q(\app_addr_r1_reg_n_0_[26] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[27] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [24]), .Q(\app_addr_r1_reg_n_0_[27] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[3] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [0]), .Q(\app_addr_r1_reg_n_0_[3] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[4] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [1]), .Q(\app_addr_r1_reg_n_0_[4] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[5] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [2]), .Q(\app_addr_r1_reg_n_0_[5] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[6] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [3]), .Q(\app_addr_r1_reg_n_0_[6] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[7] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [4]), .Q(\app_addr_r1_reg_n_0_[7] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[8] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [5]), .Q(\app_addr_r1_reg_n_0_[8] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[9] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [6]), .Q(\app_addr_r1_reg_n_0_[9] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[10] (.C(CLK), .CE(E), .D(p_1_in[0]), .Q(p_0_in_0[0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[11] (.C(CLK), .CE(E), .D(p_1_in[1]), .Q(p_0_in_0[1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[12] (.C(CLK), .CE(E), .D(p_1_in[2]), .Q(p_0_in_0[2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[13] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[13] ), .Q(\app_addr_r2_reg_n_0_[13] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[14] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[14] ), .Q(\app_addr_r2_reg_n_0_[14] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[15] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[15] ), .Q(\app_addr_r2_reg_n_0_[15] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[16] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[16] ), .Q(\app_addr_r2_reg_n_0_[16] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[17] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[17] ), .Q(\app_addr_r2_reg_n_0_[17] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[18] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[18] ), .Q(\app_addr_r2_reg_n_0_[18] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[19] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[19] ), .Q(\app_addr_r2_reg_n_0_[19] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[20] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[20] ), .Q(\app_addr_r2_reg_n_0_[20] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[21] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[21] ), .Q(\app_addr_r2_reg_n_0_[21] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[22] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[22] ), .Q(\app_addr_r2_reg_n_0_[22] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[23] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[23] ), .Q(\app_addr_r2_reg_n_0_[23] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[24] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[24] ), .Q(\app_addr_r2_reg_n_0_[24] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[25] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[25] ), .Q(\app_addr_r2_reg_n_0_[25] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[26] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[26] ), .Q(\app_addr_r2_reg_n_0_[26] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[27] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[27] ), .Q(\app_addr_r2_reg_n_0_[27] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[3] ), .Q(\app_addr_r2_reg_n_0_[3] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[4] ), .Q(\app_addr_r2_reg_n_0_[4] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[5] ), .Q(\app_addr_r2_reg_n_0_[5] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[6] ), .Q(\app_addr_r2_reg_n_0_[6] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[7] ), .Q(\app_addr_r2_reg_n_0_[7] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[8] ), .Q(\app_addr_r2_reg_n_0_[8] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[9] ), .Q(\app_addr_r2_reg_n_0_[9] ), .R(reset_reg)); (* SOFT_HLUTNM = "soft_lutpair1461" *) LUT3 #( .INIT(8'hB8)) \app_cmd_r1[0]_i_1 (.I0(mc_app_cmd), .I1(E), .I2(app_cmd_r1), .O(\app_cmd_r1[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \app_cmd_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\app_cmd_r1[0]_i_1_n_0 ), .Q(app_cmd_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1461" *) LUT3 #( .INIT(8'hB8)) \app_cmd_r2[0]_i_1 (.I0(app_cmd_r1), .I1(E), .I2(app_cmd_r2[0]), .O(cmd[0])); (* SOFT_HLUTNM = "soft_lutpair1456" *) LUT2 #( .INIT(4'h2)) \app_cmd_r2[1]_i_1 (.I0(app_cmd_r2[1]), .I1(E), .O(cmd[1])); FDRE #( .INIT(1'b0)) \app_cmd_r2_reg[0] (.C(CLK), .CE(1'b1), .D(cmd[0]), .Q(app_cmd_r2[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_cmd_r2_reg[1] (.C(CLK), .CE(1'b1), .D(cmd[1]), .Q(app_cmd_r2[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) app_en_r1_reg (.C(CLK), .CE(1'b1), .D(app_en_ns1), .Q(app_en_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1457" *) LUT4 #( .INIT(16'h2230)) app_en_r2_i_1 (.I0(app_en_r1), .I1(reset_reg), .I2(app_en_r2), .I3(E), .O(app_en_ns2)); FDRE #( .INIT(1'b0)) app_en_r2_reg (.C(CLK), .CE(1'b1), .D(app_en_ns2), .Q(app_en_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) app_hi_pri_r2_reg (.C(CLK), .CE(1'b1), .D(hi_priority), .Q(app_hi_pri_r2), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) app_rdy_r_reg (.C(CLK), .CE(1'b1), .D(app_rdy_ns), .Q(E), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1454" *) LUT4 #( .INIT(16'h8008)) \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 (.I0(E), .I1(app_en_r2), .I2(app_cmd_r2[0]), .I3(app_cmd_r2[1]), .O(wr_accepted)); LUT6 #( .INIT(64'h9009000000009009)) i___33_i_1 (.I0(\req_bank_r_lcl_reg[2] [0]), .I1(\req_bank_r_lcl_reg[2]_1 [0]), .I2(\req_bank_r_lcl_reg[2]_1 [1]), .I3(\req_bank_r_lcl_reg[2] [1]), .I4(\req_bank_r_lcl_reg[2]_1 [2]), .I5(\req_bank_r_lcl_reg[2] [2]), .O(rb_hit_busy_r_reg_0)); (* SOFT_HLUTNM = "soft_lutpair1454" *) LUT2 #( .INIT(4'h8)) idle_r_lcl_i_2 (.I0(app_en_r2), .I1(E), .O(use_addr)); (* SOFT_HLUTNM = "soft_lutpair1453" *) LUT4 #( .INIT(16'h4000)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_1 (.I0(app_cmd_r2[1]), .I1(app_cmd_r2[0]), .I2(E), .I3(app_en_r2), .O(rd_accepted)); LUT6 #( .INIT(64'h7555555510000000)) \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2 (.I0(Q[1]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(E), .I4(app_en_r2), .I5(Q[0]), .O(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] )); LUT2 #( .INIT(4'h2)) rb_hit_busy_r_i_1 (.I0(rb_hit_busy_r_reg), .I1(idle_ns[1]), .O(p_28_out)); LUT2 #( .INIT(4'h2)) rb_hit_busy_r_i_1__0 (.I0(rb_hit_busy_r_reg_0), .I1(idle_ns[0]), .O(p_67_out)); LUT6 #( .INIT(64'h9009000000009009)) rb_hit_busy_r_i_2 (.I0(\req_bank_r_lcl_reg[2] [0]), .I1(\req_bank_r_lcl_reg[2]_0 [0]), .I2(\req_bank_r_lcl_reg[2]_0 [1]), .I3(\req_bank_r_lcl_reg[2] [1]), .I4(\req_bank_r_lcl_reg[2]_0 [2]), .I5(\req_bank_r_lcl_reg[2] [2]), .O(rb_hit_busy_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1467" *) LUT3 #( .INIT(8'hB8)) \req_bank_r_lcl[0]_i_1 (.I0(p_1_in[0]), .I1(E), .I2(p_0_in_0[0]), .O(\req_bank_r_lcl_reg[2] [0])); (* SOFT_HLUTNM = "soft_lutpair1467" *) LUT3 #( .INIT(8'hB8)) \req_bank_r_lcl[1]_i_1 (.I0(p_1_in[1]), .I1(E), .I2(p_0_in_0[1]), .O(\req_bank_r_lcl_reg[2] [1])); (* SOFT_HLUTNM = "soft_lutpair1466" *) LUT3 #( .INIT(8'hB8)) \req_bank_r_lcl[2]_i_1 (.I0(p_1_in[2]), .I1(E), .I2(p_0_in_0[2]), .O(\req_bank_r_lcl_reg[2] [2])); (* SOFT_HLUTNM = "soft_lutpair1470" *) LUT3 #( .INIT(8'hB8)) \req_col_r[3]_i_1 (.I0(\app_addr_r1_reg_n_0_[3] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[3] ), .O(\req_col_r_reg[9] [0])); LUT3 #( .INIT(8'hB8)) \req_col_r[4]_i_1 (.I0(\app_addr_r1_reg_n_0_[4] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[4] ), .O(\req_col_r_reg[9] [1])); (* SOFT_HLUTNM = "soft_lutpair1470" *) LUT3 #( .INIT(8'hB8)) \req_col_r[5]_i_1 (.I0(\app_addr_r1_reg_n_0_[5] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[5] ), .O(\req_col_r_reg[9] [2])); (* SOFT_HLUTNM = "soft_lutpair1469" *) LUT3 #( .INIT(8'hB8)) \req_col_r[6]_i_1 (.I0(\app_addr_r1_reg_n_0_[6] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[6] ), .O(\req_col_r_reg[9] [3])); (* SOFT_HLUTNM = "soft_lutpair1469" *) LUT3 #( .INIT(8'hB8)) \req_col_r[7]_i_1 (.I0(\app_addr_r1_reg_n_0_[7] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[7] ), .O(\req_col_r_reg[9] [4])); (* SOFT_HLUTNM = "soft_lutpair1468" *) LUT3 #( .INIT(8'hB8)) \req_col_r[8]_i_1 (.I0(\app_addr_r1_reg_n_0_[8] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[8] ), .O(\req_col_r_reg[9] [5])); (* SOFT_HLUTNM = "soft_lutpair1468" *) LUT3 #( .INIT(8'hB8)) \req_col_r[9]_i_1 (.I0(\app_addr_r1_reg_n_0_[9] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[9] ), .O(\req_col_r_reg[9] [6])); LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[0]_i_1 (.I0(wr_data_buf_addr[0]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .O(\req_data_buf_addr_r_reg[4] [0])); (* SOFT_HLUTNM = "soft_lutpair1456" *) LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[1]_i_1 (.I0(wr_data_buf_addr[1]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .O(\req_data_buf_addr_r_reg[4] [1])); (* SOFT_HLUTNM = "soft_lutpair1455" *) LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[2]_i_1 (.I0(wr_data_buf_addr[2]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .O(\req_data_buf_addr_r_reg[4] [2])); LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[3]_i_1 (.I0(wr_data_buf_addr[3]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .O(\req_data_buf_addr_r_reg[4] [3])); (* SOFT_HLUTNM = "soft_lutpair1455" *) LUT3 #( .INIT(8'h28)) \req_data_buf_addr_r[4]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .I1(app_cmd_r2[0]), .I2(app_cmd_r2[1]), .O(\req_data_buf_addr_r_reg[4] [4])); (* SOFT_HLUTNM = "soft_lutpair1457" *) LUT2 #( .INIT(4'h2)) req_priority_r_i_1 (.I0(app_hi_pri_r2), .I1(E), .O(hi_priority)); (* SOFT_HLUTNM = "soft_lutpair1460" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[0]_i_1 (.I0(\app_addr_r1_reg_n_0_[13] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[13] ), .O(\req_row_r_lcl_reg[14] [0])); (* SOFT_HLUTNM = "soft_lutpair1464" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[10]_i_1 (.I0(\app_addr_r1_reg_n_0_[23] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[23] ), .O(\req_row_r_lcl_reg[14] [10])); (* SOFT_HLUTNM = "soft_lutpair1463" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[11]_i_1 (.I0(\app_addr_r1_reg_n_0_[24] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[24] ), .O(\req_row_r_lcl_reg[14] [11])); (* SOFT_HLUTNM = "soft_lutpair1466" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[12]_i_1 (.I0(\app_addr_r1_reg_n_0_[25] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[25] ), .O(\req_row_r_lcl_reg[14] [12])); (* SOFT_HLUTNM = "soft_lutpair1465" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[13]_i_1 (.I0(\app_addr_r1_reg_n_0_[26] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[26] ), .O(\req_row_r_lcl_reg[14] [13])); (* SOFT_HLUTNM = "soft_lutpair1465" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[14]_i_1 (.I0(\app_addr_r1_reg_n_0_[27] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[27] ), .O(\req_row_r_lcl_reg[14] [14])); (* SOFT_HLUTNM = "soft_lutpair1460" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[1]_i_1 (.I0(\app_addr_r1_reg_n_0_[14] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[14] ), .O(\req_row_r_lcl_reg[14] [1])); (* SOFT_HLUTNM = "soft_lutpair1458" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[2]_i_1 (.I0(\app_addr_r1_reg_n_0_[15] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[15] ), .O(\req_row_r_lcl_reg[14] [2])); (* SOFT_HLUTNM = "soft_lutpair1459" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[3]_i_1 (.I0(\app_addr_r1_reg_n_0_[16] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[16] ), .O(\req_row_r_lcl_reg[14] [3])); (* SOFT_HLUTNM = "soft_lutpair1459" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[4]_i_1 (.I0(\app_addr_r1_reg_n_0_[17] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[17] ), .O(\req_row_r_lcl_reg[14] [4])); (* SOFT_HLUTNM = "soft_lutpair1458" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[5]_i_1 (.I0(\app_addr_r1_reg_n_0_[18] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[18] ), .O(\req_row_r_lcl_reg[14] [5])); (* SOFT_HLUTNM = "soft_lutpair1463" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[6]_i_1 (.I0(\app_addr_r1_reg_n_0_[19] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[19] ), .O(\req_row_r_lcl_reg[14] [6])); (* SOFT_HLUTNM = "soft_lutpair1462" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[7]_i_1 (.I0(\app_addr_r1_reg_n_0_[20] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[20] ), .O(\req_row_r_lcl_reg[14] [7])); (* SOFT_HLUTNM = "soft_lutpair1462" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[8]_i_1 (.I0(\app_addr_r1_reg_n_0_[21] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[21] ), .O(\req_row_r_lcl_reg[14] [8])); (* SOFT_HLUTNM = "soft_lutpair1464" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[9]_i_1 (.I0(\app_addr_r1_reg_n_0_[22] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[22] ), .O(\req_row_r_lcl_reg[14] [9])); LUT6 #( .INIT(64'hD55555D540000040)) \wr_req_counter.wr_req_cnt_r[3]_i_2 (.I0(wr_req_cnt_r[1]), .I1(E), .I2(app_en_r2), .I3(app_cmd_r2[0]), .I4(app_cmd_r2[1]), .I5(wr_req_cnt_r[0]), .O(\wr_req_counter.wr_req_cnt_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair1453" *) LUT5 #( .INIT(32'h96555555)) \wr_req_counter.wr_req_cnt_r[3]_i_3 (.I0(p_0_in), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(app_en_r2), .I4(E), .O(\wr_req_counter.wr_req_cnt_r_reg[4] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ui_rd_data" *) module ddr3_ifmig_7series_v4_0_ui_rd_data (\not_strict_mode.app_rd_data_end_reg_0 , Q, DOA, DOB, DOC, \not_strict_mode.app_rd_data_reg[11]_0 , \not_strict_mode.app_rd_data_reg[9]_0 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[17]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[13]_0 , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[21]_0 , \not_strict_mode.app_rd_data_reg[19]_0 , \not_strict_mode.app_rd_data_reg[29]_0 , \not_strict_mode.app_rd_data_reg[27]_0 , \not_strict_mode.app_rd_data_reg[25]_0 , \not_strict_mode.app_rd_data_reg[35]_0 , \not_strict_mode.app_rd_data_reg[33]_0 , \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[41]_0 , \not_strict_mode.app_rd_data_reg[39]_0 , \not_strict_mode.app_rd_data_reg[37]_0 , \not_strict_mode.app_rd_data_reg[47]_0 , \not_strict_mode.app_rd_data_reg[45]_0 , \not_strict_mode.app_rd_data_reg[43]_0 , \not_strict_mode.app_rd_data_reg[53]_0 , \not_strict_mode.app_rd_data_reg[51]_0 , \not_strict_mode.app_rd_data_reg[49]_0 , \not_strict_mode.app_rd_data_reg[59]_0 , \not_strict_mode.app_rd_data_reg[57]_0 , \not_strict_mode.app_rd_data_reg[55]_0 , \not_strict_mode.app_rd_data_reg[65]_0 , \not_strict_mode.app_rd_data_reg[63]_0 , \not_strict_mode.app_rd_data_reg[61]_0 , \not_strict_mode.app_rd_data_reg[71]_0 , \not_strict_mode.app_rd_data_reg[69]_0 , \not_strict_mode.app_rd_data_reg[67]_0 , \not_strict_mode.app_rd_data_reg[77]_0 , \not_strict_mode.app_rd_data_reg[75]_0 , \not_strict_mode.app_rd_data_reg[73]_0 , \not_strict_mode.app_rd_data_reg[83]_0 , \not_strict_mode.app_rd_data_reg[81]_0 , \not_strict_mode.app_rd_data_reg[79]_0 , \not_strict_mode.app_rd_data_reg[89]_0 , \not_strict_mode.app_rd_data_reg[87]_0 , \not_strict_mode.app_rd_data_reg[85]_0 , \not_strict_mode.app_rd_data_reg[95]_0 , \not_strict_mode.app_rd_data_reg[93]_0 , \not_strict_mode.app_rd_data_reg[91]_0 , \not_strict_mode.app_rd_data_reg[101]_0 , \not_strict_mode.app_rd_data_reg[99]_0 , \not_strict_mode.app_rd_data_reg[97]_0 , \not_strict_mode.app_rd_data_reg[107]_0 , \not_strict_mode.app_rd_data_reg[105]_0 , \not_strict_mode.app_rd_data_reg[103]_0 , \not_strict_mode.app_rd_data_reg[113]_0 , \not_strict_mode.app_rd_data_reg[111]_0 , \not_strict_mode.app_rd_data_reg[109]_0 , \not_strict_mode.app_rd_data_reg[119]_0 , \not_strict_mode.app_rd_data_reg[117]_0 , \not_strict_mode.app_rd_data_reg[115]_0 , \not_strict_mode.app_rd_data_reg[125]_0 , \not_strict_mode.app_rd_data_reg[123]_0 , \not_strict_mode.app_rd_data_reg[121]_0 , \not_strict_mode.app_rd_data_reg[131]_0 , \not_strict_mode.app_rd_data_reg[129]_0 , \not_strict_mode.app_rd_data_reg[127]_0 , \not_strict_mode.app_rd_data_reg[137]_0 , \not_strict_mode.app_rd_data_reg[135]_0 , \not_strict_mode.app_rd_data_reg[133]_0 , \not_strict_mode.app_rd_data_reg[143]_0 , \not_strict_mode.app_rd_data_reg[141]_0 , \not_strict_mode.app_rd_data_reg[139]_0 , \not_strict_mode.app_rd_data_reg[149]_0 , \not_strict_mode.app_rd_data_reg[147]_0 , \not_strict_mode.app_rd_data_reg[145]_0 , \not_strict_mode.app_rd_data_reg[155]_0 , \not_strict_mode.app_rd_data_reg[153]_0 , \not_strict_mode.app_rd_data_reg[151]_0 , \not_strict_mode.app_rd_data_reg[161]_0 , \not_strict_mode.app_rd_data_reg[159]_0 , \not_strict_mode.app_rd_data_reg[157]_0 , \not_strict_mode.app_rd_data_reg[167]_0 , \not_strict_mode.app_rd_data_reg[165]_0 , \not_strict_mode.app_rd_data_reg[163]_0 , \not_strict_mode.app_rd_data_reg[173]_0 , \not_strict_mode.app_rd_data_reg[171]_0 , \not_strict_mode.app_rd_data_reg[169]_0 , \not_strict_mode.app_rd_data_reg[179]_0 , \not_strict_mode.app_rd_data_reg[177]_0 , \not_strict_mode.app_rd_data_reg[175]_0 , \not_strict_mode.app_rd_data_reg[185]_0 , \not_strict_mode.app_rd_data_reg[183]_0 , \not_strict_mode.app_rd_data_reg[181]_0 , \not_strict_mode.app_rd_data_reg[191]_0 , \not_strict_mode.app_rd_data_reg[189]_0 , \not_strict_mode.app_rd_data_reg[187]_0 , \not_strict_mode.app_rd_data_reg[197]_0 , \not_strict_mode.app_rd_data_reg[195]_0 , \not_strict_mode.app_rd_data_reg[193]_0 , \not_strict_mode.app_rd_data_reg[203]_0 , \not_strict_mode.app_rd_data_reg[201]_0 , \not_strict_mode.app_rd_data_reg[199]_0 , \not_strict_mode.app_rd_data_reg[209]_0 , \not_strict_mode.app_rd_data_reg[207]_0 , \not_strict_mode.app_rd_data_reg[205]_0 , \not_strict_mode.app_rd_data_reg[215]_0 , \not_strict_mode.app_rd_data_reg[213]_0 , \not_strict_mode.app_rd_data_reg[211]_0 , \not_strict_mode.app_rd_data_reg[221]_0 , \not_strict_mode.app_rd_data_reg[219]_0 , \not_strict_mode.app_rd_data_reg[217]_0 , \not_strict_mode.app_rd_data_reg[227]_0 , \not_strict_mode.app_rd_data_reg[225]_0 , \not_strict_mode.app_rd_data_reg[223]_0 , \not_strict_mode.app_rd_data_reg[233]_0 , \not_strict_mode.app_rd_data_reg[231]_0 , \not_strict_mode.app_rd_data_reg[229]_0 , \not_strict_mode.app_rd_data_reg[239]_0 , \not_strict_mode.app_rd_data_reg[237]_0 , \not_strict_mode.app_rd_data_reg[235]_0 , \not_strict_mode.app_rd_data_reg[245]_0 , \not_strict_mode.app_rd_data_reg[243]_0 , \not_strict_mode.app_rd_data_reg[241]_0 , \not_strict_mode.app_rd_data_reg[251]_0 , \not_strict_mode.app_rd_data_reg[249]_0 , \not_strict_mode.app_rd_data_reg[247]_0 , \not_strict_mode.app_rd_data_reg[255]_0 , \not_strict_mode.app_rd_data_reg[253]_0 , \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 , app_rd_data_valid, D, \not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 , \rd_buf_indx.ram_init_done_r_lcl_reg_0 , ADDRD, pointer_wr_data, \s_axi_rdata[255] , CLK, rd_buf_we, DIA, DIB, DIC, \read_fifo.fifo_out_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] , app_rd_data_end_ns, rd_accepted, reset_reg, \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 , bypass__0, \read_data_indx.rd_data_indx_r_reg[3] , \cmd_pipe_plus.wr_data_addr_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ); output [0:0]\not_strict_mode.app_rd_data_end_reg_0 ; output [4:0]Q; output [1:0]DOA; output [1:0]DOB; output [1:0]DOC; output [1:0]\not_strict_mode.app_rd_data_reg[11]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[9]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[17]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[13]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[21]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[19]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[29]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[27]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[25]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[35]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[33]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[41]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[39]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[37]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[47]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[45]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[43]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[53]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[51]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[49]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[59]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[57]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[55]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[65]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[63]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[61]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[71]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[69]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[67]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[77]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[75]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[73]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[83]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[81]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[79]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[89]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[87]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[85]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[95]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[93]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[91]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[101]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[99]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[97]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[107]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[105]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[103]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[113]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[111]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[109]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[119]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[117]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[115]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[125]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[123]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[121]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[131]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[129]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[127]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[137]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[135]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[133]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[143]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[141]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[139]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[149]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[147]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[145]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[155]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[153]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[151]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[161]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[159]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[157]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[167]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[165]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[163]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[173]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[171]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[169]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[179]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[177]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[175]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[185]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[183]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[181]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[191]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[189]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[187]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[197]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[195]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[193]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[203]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[201]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[199]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[209]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[207]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[205]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[215]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[213]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[211]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[221]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[219]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[217]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[227]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[225]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[223]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[233]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[231]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[229]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[239]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[237]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[235]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[245]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[243]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[241]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[251]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[249]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[247]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[253]_0 ; output \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ; output app_rd_data_valid; output [0:0]D; output [1:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ; output [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ; output \rd_buf_indx.ram_init_done_r_lcl_reg_0 ; output [3:0]ADDRD; output [3:0]pointer_wr_data; output [255:0]\s_axi_rdata[255] ; input CLK; input rd_buf_we; input [1:0]DIA; input [1:0]DIB; input [1:0]DIC; input [6:0]\read_fifo.fifo_out_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; input app_rd_data_end_ns; input rd_accepted; input reset_reg; input \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ; input bypass__0; input [3:0]\read_data_indx.rd_data_indx_r_reg[3] ; input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; input [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [3:0]ADDRD; wire CLK; wire [0:0]D; wire [1:0]DIA; wire [1:0]DIB; wire [1:0]DIC; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [4:0]Q; wire app_rd_data_end; wire app_rd_data_end_ns; wire app_rd_data_valid; wire app_rd_data_valid_copy; wire app_rd_data_valid_ns; wire bypass__0; wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire [0:0]\not_strict_mode.app_rd_data_end_reg_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[101]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[103]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[105]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[107]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[109]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[111]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[113]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[115]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[117]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[119]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[11]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[121]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[123]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[125]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[127]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[129]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[131]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[133]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[135]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[137]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[139]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[13]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[141]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[143]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[145]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[147]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[149]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[151]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[153]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[155]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[157]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[159]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[161]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[163]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[165]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[167]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[169]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[171]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[173]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[175]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[177]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[179]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[17]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[181]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[183]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[185]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[187]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[189]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[191]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[193]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[195]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[197]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[199]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[19]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[201]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[203]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[205]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[207]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[209]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[211]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[213]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[215]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[217]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[219]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[21]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[221]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[223]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[225]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[227]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[229]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[231]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[233]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[235]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[237]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[239]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[241]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[243]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[245]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[247]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[249]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[251]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[253]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[25]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[27]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[29]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[33]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[35]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[37]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[39]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[41]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[43]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[45]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[47]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[49]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[51]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[53]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[55]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[57]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[59]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[61]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[63]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[65]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[67]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[69]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[71]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[73]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[75]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[77]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[79]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[81]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[83]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[85]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[87]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[89]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[91]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[93]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[95]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[97]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[99]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[9]_0 ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ; wire [1:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ; wire \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ; wire [5:2]occ_cnt_r; wire [4:0]p_0_in__2; wire [3:0]pointer_wr_data; wire ram_init_done_ns; wire rd_accepted; wire \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ; wire \rd_buf_indx.ram_init_done_r_lcl_reg_0 ; wire \rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ; wire \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ; wire \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ; (* RTL_KEEP = "true" *) (* syn_keep = "true" *) wire [4:0]rd_buf_indx_copy_r; wire [5:0]rd_buf_indx_ns; wire rd_buf_we; wire rd_buf_we_r1; wire [0:0]rd_status; wire [3:0]\read_data_indx.rd_data_indx_r_reg[3] ; wire [6:0]\read_fifo.fifo_out_data_r_reg[7] ; wire reset_reg; wire [255:0]\s_axi_rdata[255] ; wire [4:0]status_ram_wr_addr_ns; wire [4:0]status_ram_wr_addr_r; wire [1:0]status_ram_wr_data_ns; wire [1:0]status_ram_wr_data_r; wire wr_status; wire wr_status_r1; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED ; wire [1:1]\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED ; FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_end_reg (.C(CLK), .CE(1'b1), .D(app_rd_data_end_ns), .Q(app_rd_data_end), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[0] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [0]), .Q(\s_axi_rdata[255] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[100] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [100]), .Q(\s_axi_rdata[255] [100]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[101] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [101]), .Q(\s_axi_rdata[255] [101]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[102] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [102]), .Q(\s_axi_rdata[255] [102]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[103] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [103]), .Q(\s_axi_rdata[255] [103]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[104] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [104]), .Q(\s_axi_rdata[255] [104]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[105] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [105]), .Q(\s_axi_rdata[255] [105]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[106] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [106]), .Q(\s_axi_rdata[255] [106]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[107] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [107]), .Q(\s_axi_rdata[255] [107]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[108] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [108]), .Q(\s_axi_rdata[255] [108]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[109] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [109]), .Q(\s_axi_rdata[255] [109]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[10] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [10]), .Q(\s_axi_rdata[255] [10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[110] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [110]), .Q(\s_axi_rdata[255] [110]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[111] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [111]), .Q(\s_axi_rdata[255] [111]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[112] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [112]), .Q(\s_axi_rdata[255] [112]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[113] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [113]), .Q(\s_axi_rdata[255] [113]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[114] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [114]), .Q(\s_axi_rdata[255] [114]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[115] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [115]), .Q(\s_axi_rdata[255] [115]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[116] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [116]), .Q(\s_axi_rdata[255] [116]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[117] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [117]), .Q(\s_axi_rdata[255] [117]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[118] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [118]), .Q(\s_axi_rdata[255] [118]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[119] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [119]), .Q(\s_axi_rdata[255] [119]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[11] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [11]), .Q(\s_axi_rdata[255] [11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[120] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [120]), .Q(\s_axi_rdata[255] [120]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[121] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [121]), .Q(\s_axi_rdata[255] [121]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[122] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [122]), .Q(\s_axi_rdata[255] [122]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[123] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [123]), .Q(\s_axi_rdata[255] [123]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[124] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [124]), .Q(\s_axi_rdata[255] [124]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[125] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [125]), .Q(\s_axi_rdata[255] [125]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[126] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [126]), .Q(\s_axi_rdata[255] [126]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[127] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [127]), .Q(\s_axi_rdata[255] [127]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[128] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [128]), .Q(\s_axi_rdata[255] [128]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[129] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [129]), .Q(\s_axi_rdata[255] [129]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[12] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [12]), .Q(\s_axi_rdata[255] [12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[130] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [130]), .Q(\s_axi_rdata[255] [130]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[131] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [131]), .Q(\s_axi_rdata[255] [131]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[132] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [132]), .Q(\s_axi_rdata[255] [132]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[133] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [133]), .Q(\s_axi_rdata[255] [133]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[134] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [134]), .Q(\s_axi_rdata[255] [134]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[135] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [135]), .Q(\s_axi_rdata[255] [135]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[136] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [136]), .Q(\s_axi_rdata[255] [136]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[137] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [137]), .Q(\s_axi_rdata[255] [137]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[138] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [138]), .Q(\s_axi_rdata[255] [138]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[139] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [139]), .Q(\s_axi_rdata[255] [139]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[13] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [13]), .Q(\s_axi_rdata[255] [13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[140] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [140]), .Q(\s_axi_rdata[255] [140]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[141] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [141]), .Q(\s_axi_rdata[255] [141]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[142] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [142]), .Q(\s_axi_rdata[255] [142]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[143] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [143]), .Q(\s_axi_rdata[255] [143]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[144] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [144]), .Q(\s_axi_rdata[255] [144]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[145] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [145]), .Q(\s_axi_rdata[255] [145]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[146] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [146]), .Q(\s_axi_rdata[255] [146]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[147] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [147]), .Q(\s_axi_rdata[255] [147]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[148] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [148]), .Q(\s_axi_rdata[255] [148]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[149] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [149]), .Q(\s_axi_rdata[255] [149]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[14] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [14]), .Q(\s_axi_rdata[255] [14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[150] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [150]), .Q(\s_axi_rdata[255] [150]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[151] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [151]), .Q(\s_axi_rdata[255] [151]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[152] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [152]), .Q(\s_axi_rdata[255] [152]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[153] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [153]), .Q(\s_axi_rdata[255] [153]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[154] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [154]), .Q(\s_axi_rdata[255] [154]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[155] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [155]), .Q(\s_axi_rdata[255] [155]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[156] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [156]), .Q(\s_axi_rdata[255] [156]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[157] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [157]), .Q(\s_axi_rdata[255] [157]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[158] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [158]), .Q(\s_axi_rdata[255] [158]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[159] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [159]), .Q(\s_axi_rdata[255] [159]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[15] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [15]), .Q(\s_axi_rdata[255] [15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[160] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [160]), .Q(\s_axi_rdata[255] [160]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[161] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [161]), .Q(\s_axi_rdata[255] [161]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[162] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [162]), .Q(\s_axi_rdata[255] [162]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[163] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [163]), .Q(\s_axi_rdata[255] [163]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[164] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [164]), .Q(\s_axi_rdata[255] [164]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[165] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [165]), .Q(\s_axi_rdata[255] [165]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[166] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [166]), .Q(\s_axi_rdata[255] [166]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[167] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [167]), .Q(\s_axi_rdata[255] [167]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[168] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [168]), .Q(\s_axi_rdata[255] [168]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[169] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [169]), .Q(\s_axi_rdata[255] [169]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[16] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [16]), .Q(\s_axi_rdata[255] [16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[170] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [170]), .Q(\s_axi_rdata[255] [170]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[171] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [171]), .Q(\s_axi_rdata[255] [171]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[172] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [172]), .Q(\s_axi_rdata[255] [172]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[173] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [173]), .Q(\s_axi_rdata[255] [173]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[174] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [174]), .Q(\s_axi_rdata[255] [174]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[175] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [175]), .Q(\s_axi_rdata[255] [175]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[176] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [176]), .Q(\s_axi_rdata[255] [176]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[177] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [177]), .Q(\s_axi_rdata[255] [177]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[178] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [178]), .Q(\s_axi_rdata[255] [178]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[179] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [179]), .Q(\s_axi_rdata[255] [179]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[17] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [17]), .Q(\s_axi_rdata[255] [17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[180] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [180]), .Q(\s_axi_rdata[255] [180]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[181] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [181]), .Q(\s_axi_rdata[255] [181]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[182] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [182]), .Q(\s_axi_rdata[255] [182]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[183] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [183]), .Q(\s_axi_rdata[255] [183]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[184] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [184]), .Q(\s_axi_rdata[255] [184]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[185] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [185]), .Q(\s_axi_rdata[255] [185]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[186] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [186]), .Q(\s_axi_rdata[255] [186]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[187] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [187]), .Q(\s_axi_rdata[255] [187]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[188] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [188]), .Q(\s_axi_rdata[255] [188]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[189] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [189]), .Q(\s_axi_rdata[255] [189]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[18] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [18]), .Q(\s_axi_rdata[255] [18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[190] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [190]), .Q(\s_axi_rdata[255] [190]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[191] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [191]), .Q(\s_axi_rdata[255] [191]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[192] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [192]), .Q(\s_axi_rdata[255] [192]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[193] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [193]), .Q(\s_axi_rdata[255] [193]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[194] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [194]), .Q(\s_axi_rdata[255] [194]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[195] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [195]), .Q(\s_axi_rdata[255] [195]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[196] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [196]), .Q(\s_axi_rdata[255] [196]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[197] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [197]), .Q(\s_axi_rdata[255] [197]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[198] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [198]), .Q(\s_axi_rdata[255] [198]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[199] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [199]), .Q(\s_axi_rdata[255] [199]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[19] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [19]), .Q(\s_axi_rdata[255] [19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[1] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [1]), .Q(\s_axi_rdata[255] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[200] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [200]), .Q(\s_axi_rdata[255] [200]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[201] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [201]), .Q(\s_axi_rdata[255] [201]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[202] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [202]), .Q(\s_axi_rdata[255] [202]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[203] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [203]), .Q(\s_axi_rdata[255] [203]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[204] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [204]), .Q(\s_axi_rdata[255] [204]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[205] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [205]), .Q(\s_axi_rdata[255] [205]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[206] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [206]), .Q(\s_axi_rdata[255] [206]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[207] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [207]), .Q(\s_axi_rdata[255] [207]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[208] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [208]), .Q(\s_axi_rdata[255] [208]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[209] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [209]), .Q(\s_axi_rdata[255] [209]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[20] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [20]), .Q(\s_axi_rdata[255] [20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[210] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [210]), .Q(\s_axi_rdata[255] [210]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[211] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [211]), .Q(\s_axi_rdata[255] [211]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[212] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [212]), .Q(\s_axi_rdata[255] [212]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[213] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [213]), .Q(\s_axi_rdata[255] [213]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[214] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [214]), .Q(\s_axi_rdata[255] [214]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[215] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [215]), .Q(\s_axi_rdata[255] [215]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[216] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [216]), .Q(\s_axi_rdata[255] [216]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[217] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [217]), .Q(\s_axi_rdata[255] [217]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[218] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [218]), .Q(\s_axi_rdata[255] [218]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[219] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [219]), .Q(\s_axi_rdata[255] [219]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[21] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [21]), .Q(\s_axi_rdata[255] [21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[220] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [220]), .Q(\s_axi_rdata[255] [220]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[221] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [221]), .Q(\s_axi_rdata[255] [221]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[222] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [222]), .Q(\s_axi_rdata[255] [222]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[223] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [223]), .Q(\s_axi_rdata[255] [223]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[224] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [224]), .Q(\s_axi_rdata[255] [224]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[225] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [225]), .Q(\s_axi_rdata[255] [225]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[226] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [226]), .Q(\s_axi_rdata[255] [226]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[227] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [227]), .Q(\s_axi_rdata[255] [227]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[228] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [228]), .Q(\s_axi_rdata[255] [228]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[229] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [229]), .Q(\s_axi_rdata[255] [229]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[22] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [22]), .Q(\s_axi_rdata[255] [22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[230] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [230]), .Q(\s_axi_rdata[255] [230]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[231] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [231]), .Q(\s_axi_rdata[255] [231]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[232] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [232]), .Q(\s_axi_rdata[255] [232]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[233] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [233]), .Q(\s_axi_rdata[255] [233]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[234] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [234]), .Q(\s_axi_rdata[255] [234]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[235] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [235]), .Q(\s_axi_rdata[255] [235]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[236] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [236]), .Q(\s_axi_rdata[255] [236]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[237] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [237]), .Q(\s_axi_rdata[255] [237]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[238] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [238]), .Q(\s_axi_rdata[255] [238]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[239] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [239]), .Q(\s_axi_rdata[255] [239]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[23] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [23]), .Q(\s_axi_rdata[255] [23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[240] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [240]), .Q(\s_axi_rdata[255] [240]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[241] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [241]), .Q(\s_axi_rdata[255] [241]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[242] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [242]), .Q(\s_axi_rdata[255] [242]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[243] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [243]), .Q(\s_axi_rdata[255] [243]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[244] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [244]), .Q(\s_axi_rdata[255] [244]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[245] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [245]), .Q(\s_axi_rdata[255] [245]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[246] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [246]), .Q(\s_axi_rdata[255] [246]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[247] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [247]), .Q(\s_axi_rdata[255] [247]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[248] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [248]), .Q(\s_axi_rdata[255] [248]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[249] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [249]), .Q(\s_axi_rdata[255] [249]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[24] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [24]), .Q(\s_axi_rdata[255] [24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[250] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [250]), .Q(\s_axi_rdata[255] [250]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[251] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [251]), .Q(\s_axi_rdata[255] [251]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[252] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [252]), .Q(\s_axi_rdata[255] [252]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[253] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [253]), .Q(\s_axi_rdata[255] [253]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[254] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [254]), .Q(\s_axi_rdata[255] [254]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[255] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [255]), .Q(\s_axi_rdata[255] [255]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[25] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [25]), .Q(\s_axi_rdata[255] [25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[26] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [26]), .Q(\s_axi_rdata[255] [26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[27] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [27]), .Q(\s_axi_rdata[255] [27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[28] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [28]), .Q(\s_axi_rdata[255] [28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[29] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [29]), .Q(\s_axi_rdata[255] [29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[2] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [2]), .Q(\s_axi_rdata[255] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[30] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [30]), .Q(\s_axi_rdata[255] [30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[31] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [31]), .Q(\s_axi_rdata[255] [31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[32] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [32]), .Q(\s_axi_rdata[255] [32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[33] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [33]), .Q(\s_axi_rdata[255] [33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[34] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [34]), .Q(\s_axi_rdata[255] [34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[35] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [35]), .Q(\s_axi_rdata[255] [35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[36] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [36]), .Q(\s_axi_rdata[255] [36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[37] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [37]), .Q(\s_axi_rdata[255] [37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[38] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [38]), .Q(\s_axi_rdata[255] [38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[39] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [39]), .Q(\s_axi_rdata[255] [39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[3] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [3]), .Q(\s_axi_rdata[255] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[40] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [40]), .Q(\s_axi_rdata[255] [40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[41] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [41]), .Q(\s_axi_rdata[255] [41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[42] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [42]), .Q(\s_axi_rdata[255] [42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[43] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [43]), .Q(\s_axi_rdata[255] [43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[44] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [44]), .Q(\s_axi_rdata[255] [44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[45] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [45]), .Q(\s_axi_rdata[255] [45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[46] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [46]), .Q(\s_axi_rdata[255] [46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[47] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [47]), .Q(\s_axi_rdata[255] [47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[48] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [48]), .Q(\s_axi_rdata[255] [48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[49] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [49]), .Q(\s_axi_rdata[255] [49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[4] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [4]), .Q(\s_axi_rdata[255] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[50] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [50]), .Q(\s_axi_rdata[255] [50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[51] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [51]), .Q(\s_axi_rdata[255] [51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[52] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [52]), .Q(\s_axi_rdata[255] [52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[53] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [53]), .Q(\s_axi_rdata[255] [53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[54] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [54]), .Q(\s_axi_rdata[255] [54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[55] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [55]), .Q(\s_axi_rdata[255] [55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[56] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [56]), .Q(\s_axi_rdata[255] [56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[57] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [57]), .Q(\s_axi_rdata[255] [57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[58] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [58]), .Q(\s_axi_rdata[255] [58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[59] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [59]), .Q(\s_axi_rdata[255] [59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[5] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [5]), .Q(\s_axi_rdata[255] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[60] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [60]), .Q(\s_axi_rdata[255] [60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[61] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [61]), .Q(\s_axi_rdata[255] [61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[62] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [62]), .Q(\s_axi_rdata[255] [62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[63] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [63]), .Q(\s_axi_rdata[255] [63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[64] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [64]), .Q(\s_axi_rdata[255] [64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[65] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [65]), .Q(\s_axi_rdata[255] [65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[66] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [66]), .Q(\s_axi_rdata[255] [66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[67] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [67]), .Q(\s_axi_rdata[255] [67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[68] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [68]), .Q(\s_axi_rdata[255] [68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[69] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [69]), .Q(\s_axi_rdata[255] [69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[6] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [6]), .Q(\s_axi_rdata[255] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[70] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [70]), .Q(\s_axi_rdata[255] [70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[71] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [71]), .Q(\s_axi_rdata[255] [71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[72] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [72]), .Q(\s_axi_rdata[255] [72]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[73] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [73]), .Q(\s_axi_rdata[255] [73]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[74] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [74]), .Q(\s_axi_rdata[255] [74]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[75] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [75]), .Q(\s_axi_rdata[255] [75]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[76] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [76]), .Q(\s_axi_rdata[255] [76]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[77] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [77]), .Q(\s_axi_rdata[255] [77]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[78] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [78]), .Q(\s_axi_rdata[255] [78]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[79] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [79]), .Q(\s_axi_rdata[255] [79]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[7] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [7]), .Q(\s_axi_rdata[255] [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[80] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [80]), .Q(\s_axi_rdata[255] [80]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[81] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [81]), .Q(\s_axi_rdata[255] [81]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[82] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [82]), .Q(\s_axi_rdata[255] [82]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[83] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [83]), .Q(\s_axi_rdata[255] [83]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[84] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [84]), .Q(\s_axi_rdata[255] [84]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[85] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [85]), .Q(\s_axi_rdata[255] [85]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[86] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [86]), .Q(\s_axi_rdata[255] [86]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[87] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [87]), .Q(\s_axi_rdata[255] [87]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[88] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [88]), .Q(\s_axi_rdata[255] [88]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[89] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [89]), .Q(\s_axi_rdata[255] [89]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[8] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [8]), .Q(\s_axi_rdata[255] [8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[90] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [90]), .Q(\s_axi_rdata[255] [90]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[91] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [91]), .Q(\s_axi_rdata[255] [91]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[92] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [92]), .Q(\s_axi_rdata[255] [92]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[93] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [93]), .Q(\s_axi_rdata[255] [93]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[94] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [94]), .Q(\s_axi_rdata[255] [94]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[95] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [95]), .Q(\s_axi_rdata[255] [95]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[96] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [96]), .Q(\s_axi_rdata[255] [96]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[97] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [97]), .Q(\s_axi_rdata[255] [97]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[98] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [98]), .Q(\s_axi_rdata[255] [98]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[99] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [99]), .Q(\s_axi_rdata[255] [99]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_reg[9] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [9]), .Q(\s_axi_rdata[255] [9]), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_valid_copy_reg (.C(CLK), .CE(1'b1), .D(app_rd_data_valid_ns), .Q(app_rd_data_valid_copy), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1472" *) LUT4 #( .INIT(16'hEB00)) \not_strict_mode.app_rd_data_valid_i_1 (.I0(bypass__0), .I1(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I2(rd_status), .I3(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .O(app_rd_data_valid_ns)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \not_strict_mode.app_rd_data_valid_reg (.C(CLK), .CE(1'b1), .D(app_rd_data_valid_ns), .Q(app_rd_data_valid), .R(1'b0)); LUT1 #( .INIT(2'h1)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[0]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair1478" *) LUT2 #( .INIT(4'h6)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[1]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair1478" *) LUT3 #( .INIT(8'h78)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[2]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair1473" *) LUT4 #( .INIT(16'h7F80)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[3]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]), .O(p_0_in__2[3])); (* SOFT_HLUTNM = "soft_lutpair1473" *) LUT5 #( .INIT(32'h7FFF8000)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_2 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]), .I4(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]), .O(p_0_in__2[4])); FDRE #( .INIT(1'b0)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[0] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[0]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[1] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[1]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[2] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[2]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[3] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[3]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[4]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]), .R(reset_reg)); (* SOFT_HLUTNM = "soft_lutpair1474" *) LUT5 #( .INIT(32'h00009666)) \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I1(rd_accepted), .I2(app_rd_data_valid_copy), .I3(app_rd_data_end), .I4(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000C96C6C6C)) \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I2(rd_accepted), .I3(app_rd_data_valid_copy), .I4(app_rd_data_end), .I5(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF81007E008100)) \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I1(rd_accepted), .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I4(occ_cnt_r[2]), .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF81007E008100)) \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1 (.I0(occ_cnt_r[2]), .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ), .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I4(occ_cnt_r[3]), .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFF906090)) \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1 (.I0(occ_cnt_r[3]), .I1(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ), .I2(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I3(occ_cnt_r[4]), .I4(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF81007E008100)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_1 (.I0(occ_cnt_r[4]), .I1(occ_cnt_r[3]), .I2(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ), .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I4(occ_cnt_r[5]), .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(D)); LUT5 #( .INIT(32'h8000FFFE)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I1(rd_accepted), .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I3(occ_cnt_r[2]), .I4(occ_cnt_r[3]), .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1474" *) LUT4 #( .INIT(16'h006A)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3 (.I0(rd_accepted), .I1(app_rd_data_valid_copy), .I2(app_rd_data_end), .I3(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1475" *) LUT4 #( .INIT(16'h0095)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4 (.I0(rd_accepted), .I1(app_rd_data_valid_copy), .I2(app_rd_data_end), .I3(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \not_strict_mode.occupied_counter.occ_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ), .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ), .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ), .Q(occ_cnt_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ), .Q(occ_cnt_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.occupied_counter.occ_cnt_r_reg[4] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ), .Q(occ_cnt_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.occupied_counter.occ_cnt_r_reg[5] (.C(CLK), .CE(1'b1), .D(D), .Q(occ_cnt_r[5]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE #( .INIT(1'b0)) \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[0]), .Q(rd_buf_indx_copy_r[0]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE #( .INIT(1'b0)) \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[1]), .Q(rd_buf_indx_copy_r[1]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE #( .INIT(1'b0)) \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[2]), .Q(rd_buf_indx_copy_r[2]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE #( .INIT(1'b0)) \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[3]), .Q(rd_buf_indx_copy_r[3]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE #( .INIT(1'b0)) \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[4]), .Q(rd_buf_indx_copy_r[4]), .R(1'b0)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID({1'b0,1'b0}), .DOA(DOA), .DOB(DOB), .DOC(DOC), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[65]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[63]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[61]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[71]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[69]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[67]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[77]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[75]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[73]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[83]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[81]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[79]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[89]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[87]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[85]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[95]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[93]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[91]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[101]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[99]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[97]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[107]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[105]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[103]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[113]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[111]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[109]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[119]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[117]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[115]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[11]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[9]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[7]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[125]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[123]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[121]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[131]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[129]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[127]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[137]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[135]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[133]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[143]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[141]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[139]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[149]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[147]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[145]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[155]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[153]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[151]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[161]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[159]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[157]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[167]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[165]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[163]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[173]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[171]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[169]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[179]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[177]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[175]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[17]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[15]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[13]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[185]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[183]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[181]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[191]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[189]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[187]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[197]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[195]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[193]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[203]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[201]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[199]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[209]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[207]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[205]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[215]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[213]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[211]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[221]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[219]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[217]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[227]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[225]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[223]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[233]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[231]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[229]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[239]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[237]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[235]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[23]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[21]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[19]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[245]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[243]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[241]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[251]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[249]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[247]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA({1'b0,1'b0}), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .DID({1'b0,1'b0}), .DOA(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(\not_strict_mode.app_rd_data_reg[255]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[253]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[29]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[27]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[25]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[35]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[33]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[31]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[41]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[39]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[37]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[47]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[45]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[43]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[53]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[51]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[49]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[59]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[57]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[55]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.status_ram.RAM32M0 (.ADDRA(Q), .ADDRB({1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRC(status_ram_wr_addr_ns), .ADDRD(status_ram_wr_addr_r), .DIA(status_ram_wr_data_r), .DIB({1'b0,1'b0}), .DIC(status_ram_wr_data_r), .DID(status_ram_wr_data_r), .DOA({\not_strict_mode.app_rd_data_end_reg_0 ,rd_status}), .DOB(\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED [1:0]), .DOC({\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED [1],wr_status}), .DOD(\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we_r1)); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_1 (.I0(\read_fifo.fifo_out_data_r_reg[7] [5]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[4]), .O(status_ram_wr_addr_ns[4])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_2 (.I0(\read_fifo.fifo_out_data_r_reg[7] [4]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[3]), .O(status_ram_wr_addr_ns[3])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_3 (.I0(\read_fifo.fifo_out_data_r_reg[7] [3]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[2]), .O(status_ram_wr_addr_ns[2])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_4 (.I0(\read_fifo.fifo_out_data_r_reg[7] [2]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[1]), .O(status_ram_wr_addr_ns[1])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_5 (.I0(\read_fifo.fifo_out_data_r_reg[7] [1]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[0]), .O(status_ram_wr_addr_ns[0])); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.rd_buf_we_r1_reg (.C(CLK), .CE(1'b1), .D(rd_buf_we), .Q(rd_buf_we_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[0]), .Q(status_ram_wr_addr_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[1]), .Q(status_ram_wr_addr_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[2]), .Q(status_ram_wr_addr_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[3]), .Q(status_ram_wr_addr_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[4]), .Q(status_ram_wr_addr_r[4]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1476" *) LUT4 #( .INIT(16'h404C)) \not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1 (.I0(wr_status_r1), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(\read_fifo.fifo_out_data_r_reg[7] [0]), .I3(wr_status), .O(status_ram_wr_data_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1476" *) LUT2 #( .INIT(4'h8)) \not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1 (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[7] [6]), .O(status_ram_wr_data_ns[1])); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0] (.C(CLK), .CE(1'b1), .D(status_ram_wr_data_ns[0]), .Q(status_ram_wr_data_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1] (.C(CLK), .CE(1'b1), .D(status_ram_wr_data_ns[1]), .Q(status_ram_wr_data_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \not_strict_mode.status_ram.wr_status_r1_reg (.C(CLK), .CE(1'b1), .D(wr_status), .Q(wr_status_r1), .R(1'b0)); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_2 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [1]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[1]), .O(pointer_wr_data[1])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_3 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [0]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[0]), .O(pointer_wr_data[0])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_4 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [3]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[3]), .O(ADDRD[3])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_5 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [2]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[2]), .O(ADDRD[2])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_6 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [1]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[1]), .O(ADDRD[1])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_7 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [0]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[0]), .O(ADDRD[0])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[1].RAM32M0_i_1 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [3]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[3]), .O(pointer_wr_data[3])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[1].RAM32M0_i_2 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [2]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[2]), .O(pointer_wr_data[2])); LUT6 #( .INIT(64'hFFFFFFFF80000000)) \rd_buf_indx.ram_init_done_r_lcl_i_1 (.I0(Q[3]), .I1(Q[4]), .I2(\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ), .I3(Q[2]), .I4(Q[1]), .I5(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ), .O(ram_init_done_ns)); LUT2 #( .INIT(4'h2)) \rd_buf_indx.ram_init_done_r_lcl_i_2 (.I0(Q[0]), .I1(reset_reg), .O(\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1475" *) LUT2 #( .INIT(4'h2)) \rd_buf_indx.ram_init_done_r_lcl_i_3 (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I1(reset_reg), .O(\rd_buf_indx.ram_init_done_r_lcl_reg_0 )); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) \rd_buf_indx.ram_init_done_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ram_init_done_ns), .Q(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h000000001400EBFF)) \rd_buf_indx.rd_buf_indx_r[0]_i_1 (.I0(bypass__0), .I1(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I2(rd_status), .I3(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I4(Q[0]), .I5(reset_reg), .O(rd_buf_indx_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1477" *) LUT3 #( .INIT(8'h09)) \rd_buf_indx.rd_buf_indx_r[1]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ), .I1(Q[1]), .I2(reset_reg), .O(rd_buf_indx_ns[1])); (* SOFT_HLUTNM = "soft_lutpair1472" *) LUT5 #( .INIT(32'h0028FFFF)) \rd_buf_indx.rd_buf_indx_r[1]_i_2 (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I1(rd_status), .I2(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I3(bypass__0), .I4(Q[0]), .O(\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1477" *) LUT3 #( .INIT(8'h06)) \rd_buf_indx.rd_buf_indx_r[2]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I1(Q[2]), .I2(reset_reg), .O(rd_buf_indx_ns[2])); (* SOFT_HLUTNM = "soft_lutpair1471" *) LUT4 #( .INIT(16'h0078)) \rd_buf_indx.rd_buf_indx_r[3]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(reset_reg), .O(rd_buf_indx_ns[3])); (* SOFT_HLUTNM = "soft_lutpair1471" *) LUT5 #( .INIT(32'h00007F80)) \rd_buf_indx.rd_buf_indx_r[4]_i_1 (.I0(Q[3]), .I1(Q[2]), .I2(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I3(Q[4]), .I4(reset_reg), .O(rd_buf_indx_ns[4])); LUT6 #( .INIT(64'h000000007FFF8000)) \rd_buf_indx.rd_buf_indx_r[5]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I5(reset_reg), .O(rd_buf_indx_ns[5])); LUT6 #( .INIT(64'h8880808888888888)) \rd_buf_indx.rd_buf_indx_r[5]_i_2 (.I0(Q[1]), .I1(Q[0]), .I2(bypass__0), .I3(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I4(rd_status), .I5(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .O(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \rd_buf_indx.rd_buf_indx_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_buf_indx.rd_buf_indx_r_reg[1] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_buf_indx.rd_buf_indx_r_reg[2] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_buf_indx.rd_buf_indx_r_reg[3] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_buf_indx.rd_buf_indx_r_reg[4] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rd_buf_indx.rd_buf_indx_r_reg[5] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[5]), .Q(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ui_top" *) module ddr3_ifmig_7series_v4_0_ui_top (\not_strict_mode.app_rd_data_end_reg , Q, DOA, DOB, DOC, \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[253] , app_rdy, app_en_r1, app_hi_pri_r2, hi_priority, ram_init_done_r, app_wdf_rdy, app_rd_data_valid, cmd, p_28_out, rb_hit_busy_r_reg, p_67_out, rb_hit_busy_r_reg_0, \req_bank_r_lcl_reg[2] , use_addr, \req_data_buf_addr_r_reg[4] , \req_row_r_lcl_reg[14] , \req_col_r_reg[9] , \my_empty_reg[7] , \s_axi_rdata[255] , CLK, pointer_we, \cmd_pipe_plus.wr_data_addr_reg[3] , rd_buf_we, DIA, DIB, DIC, \read_fifo.fifo_out_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] , app_en_ns1, E, app_rd_data_end_ns, reset_reg, mc_app_cmd, idle_ns, \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , mc_app_wdf_wren_reg, w_cmd_rdy, D, mc_app_wdf_mask_reg, wready_reg_rep__1, mc_app_wdf_data_reg, accept_ns, bypass__0, app_rdy_r_reg, \axaddr_incr_reg[29] , app_wdf_data, app_wdf_mask, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ); output [0:0]\not_strict_mode.app_rd_data_end_reg ; output [4:0]Q; output [1:0]DOA; output [1:0]DOB; output [1:0]DOC; output [1:0]\not_strict_mode.app_rd_data_reg[11] ; output [1:0]\not_strict_mode.app_rd_data_reg[9] ; output [1:0]\not_strict_mode.app_rd_data_reg[7] ; output [1:0]\not_strict_mode.app_rd_data_reg[17] ; output [1:0]\not_strict_mode.app_rd_data_reg[15] ; output [1:0]\not_strict_mode.app_rd_data_reg[13] ; output [1:0]\not_strict_mode.app_rd_data_reg[23] ; output [1:0]\not_strict_mode.app_rd_data_reg[21] ; output [1:0]\not_strict_mode.app_rd_data_reg[19] ; output [1:0]\not_strict_mode.app_rd_data_reg[29] ; output [1:0]\not_strict_mode.app_rd_data_reg[27] ; output [1:0]\not_strict_mode.app_rd_data_reg[25] ; output [1:0]\not_strict_mode.app_rd_data_reg[35] ; output [1:0]\not_strict_mode.app_rd_data_reg[33] ; output [1:0]\not_strict_mode.app_rd_data_reg[31] ; output [1:0]\not_strict_mode.app_rd_data_reg[41] ; output [1:0]\not_strict_mode.app_rd_data_reg[39] ; output [1:0]\not_strict_mode.app_rd_data_reg[37] ; output [1:0]\not_strict_mode.app_rd_data_reg[47] ; output [1:0]\not_strict_mode.app_rd_data_reg[45] ; output [1:0]\not_strict_mode.app_rd_data_reg[43] ; output [1:0]\not_strict_mode.app_rd_data_reg[53] ; output [1:0]\not_strict_mode.app_rd_data_reg[51] ; output [1:0]\not_strict_mode.app_rd_data_reg[49] ; output [1:0]\not_strict_mode.app_rd_data_reg[59] ; output [1:0]\not_strict_mode.app_rd_data_reg[57] ; output [1:0]\not_strict_mode.app_rd_data_reg[55] ; output [1:0]\not_strict_mode.app_rd_data_reg[65] ; output [1:0]\not_strict_mode.app_rd_data_reg[63] ; output [1:0]\not_strict_mode.app_rd_data_reg[61] ; output [1:0]\not_strict_mode.app_rd_data_reg[71] ; output [1:0]\not_strict_mode.app_rd_data_reg[69] ; output [1:0]\not_strict_mode.app_rd_data_reg[67] ; output [1:0]\not_strict_mode.app_rd_data_reg[77] ; output [1:0]\not_strict_mode.app_rd_data_reg[75] ; output [1:0]\not_strict_mode.app_rd_data_reg[73] ; output [1:0]\not_strict_mode.app_rd_data_reg[83] ; output [1:0]\not_strict_mode.app_rd_data_reg[81] ; output [1:0]\not_strict_mode.app_rd_data_reg[79] ; output [1:0]\not_strict_mode.app_rd_data_reg[89] ; output [1:0]\not_strict_mode.app_rd_data_reg[87] ; output [1:0]\not_strict_mode.app_rd_data_reg[85] ; output [1:0]\not_strict_mode.app_rd_data_reg[95] ; output [1:0]\not_strict_mode.app_rd_data_reg[93] ; output [1:0]\not_strict_mode.app_rd_data_reg[91] ; output [1:0]\not_strict_mode.app_rd_data_reg[101] ; output [1:0]\not_strict_mode.app_rd_data_reg[99] ; output [1:0]\not_strict_mode.app_rd_data_reg[97] ; output [1:0]\not_strict_mode.app_rd_data_reg[107] ; output [1:0]\not_strict_mode.app_rd_data_reg[105] ; output [1:0]\not_strict_mode.app_rd_data_reg[103] ; output [1:0]\not_strict_mode.app_rd_data_reg[113] ; output [1:0]\not_strict_mode.app_rd_data_reg[111] ; output [1:0]\not_strict_mode.app_rd_data_reg[109] ; output [1:0]\not_strict_mode.app_rd_data_reg[119] ; output [1:0]\not_strict_mode.app_rd_data_reg[117] ; output [1:0]\not_strict_mode.app_rd_data_reg[115] ; output [1:0]\not_strict_mode.app_rd_data_reg[125] ; output [1:0]\not_strict_mode.app_rd_data_reg[123] ; output [1:0]\not_strict_mode.app_rd_data_reg[121] ; output [1:0]\not_strict_mode.app_rd_data_reg[131] ; output [1:0]\not_strict_mode.app_rd_data_reg[129] ; output [1:0]\not_strict_mode.app_rd_data_reg[127] ; output [1:0]\not_strict_mode.app_rd_data_reg[137] ; output [1:0]\not_strict_mode.app_rd_data_reg[135] ; output [1:0]\not_strict_mode.app_rd_data_reg[133] ; output [1:0]\not_strict_mode.app_rd_data_reg[143] ; output [1:0]\not_strict_mode.app_rd_data_reg[141] ; output [1:0]\not_strict_mode.app_rd_data_reg[139] ; output [1:0]\not_strict_mode.app_rd_data_reg[149] ; output [1:0]\not_strict_mode.app_rd_data_reg[147] ; output [1:0]\not_strict_mode.app_rd_data_reg[145] ; output [1:0]\not_strict_mode.app_rd_data_reg[155] ; output [1:0]\not_strict_mode.app_rd_data_reg[153] ; output [1:0]\not_strict_mode.app_rd_data_reg[151] ; output [1:0]\not_strict_mode.app_rd_data_reg[161] ; output [1:0]\not_strict_mode.app_rd_data_reg[159] ; output [1:0]\not_strict_mode.app_rd_data_reg[157] ; output [1:0]\not_strict_mode.app_rd_data_reg[167] ; output [1:0]\not_strict_mode.app_rd_data_reg[165] ; output [1:0]\not_strict_mode.app_rd_data_reg[163] ; output [1:0]\not_strict_mode.app_rd_data_reg[173] ; output [1:0]\not_strict_mode.app_rd_data_reg[171] ; output [1:0]\not_strict_mode.app_rd_data_reg[169] ; output [1:0]\not_strict_mode.app_rd_data_reg[179] ; output [1:0]\not_strict_mode.app_rd_data_reg[177] ; output [1:0]\not_strict_mode.app_rd_data_reg[175] ; output [1:0]\not_strict_mode.app_rd_data_reg[185] ; output [1:0]\not_strict_mode.app_rd_data_reg[183] ; output [1:0]\not_strict_mode.app_rd_data_reg[181] ; output [1:0]\not_strict_mode.app_rd_data_reg[191] ; output [1:0]\not_strict_mode.app_rd_data_reg[189] ; output [1:0]\not_strict_mode.app_rd_data_reg[187] ; output [1:0]\not_strict_mode.app_rd_data_reg[197] ; output [1:0]\not_strict_mode.app_rd_data_reg[195] ; output [1:0]\not_strict_mode.app_rd_data_reg[193] ; output [1:0]\not_strict_mode.app_rd_data_reg[203] ; output [1:0]\not_strict_mode.app_rd_data_reg[201] ; output [1:0]\not_strict_mode.app_rd_data_reg[199] ; output [1:0]\not_strict_mode.app_rd_data_reg[209] ; output [1:0]\not_strict_mode.app_rd_data_reg[207] ; output [1:0]\not_strict_mode.app_rd_data_reg[205] ; output [1:0]\not_strict_mode.app_rd_data_reg[215] ; output [1:0]\not_strict_mode.app_rd_data_reg[213] ; output [1:0]\not_strict_mode.app_rd_data_reg[211] ; output [1:0]\not_strict_mode.app_rd_data_reg[221] ; output [1:0]\not_strict_mode.app_rd_data_reg[219] ; output [1:0]\not_strict_mode.app_rd_data_reg[217] ; output [1:0]\not_strict_mode.app_rd_data_reg[227] ; output [1:0]\not_strict_mode.app_rd_data_reg[225] ; output [1:0]\not_strict_mode.app_rd_data_reg[223] ; output [1:0]\not_strict_mode.app_rd_data_reg[233] ; output [1:0]\not_strict_mode.app_rd_data_reg[231] ; output [1:0]\not_strict_mode.app_rd_data_reg[229] ; output [1:0]\not_strict_mode.app_rd_data_reg[239] ; output [1:0]\not_strict_mode.app_rd_data_reg[237] ; output [1:0]\not_strict_mode.app_rd_data_reg[235] ; output [1:0]\not_strict_mode.app_rd_data_reg[245] ; output [1:0]\not_strict_mode.app_rd_data_reg[243] ; output [1:0]\not_strict_mode.app_rd_data_reg[241] ; output [1:0]\not_strict_mode.app_rd_data_reg[251] ; output [1:0]\not_strict_mode.app_rd_data_reg[249] ; output [1:0]\not_strict_mode.app_rd_data_reg[247] ; output [1:0]\not_strict_mode.app_rd_data_reg[255] ; output [1:0]\not_strict_mode.app_rd_data_reg[253] ; output app_rdy; output app_en_r1; output app_hi_pri_r2; output hi_priority; output ram_init_done_r; output app_wdf_rdy; output app_rd_data_valid; output [1:0]cmd; output p_28_out; output rb_hit_busy_r_reg; output p_67_out; output rb_hit_busy_r_reg_0; output [2:0]\req_bank_r_lcl_reg[2] ; output use_addr; output [4:0]\req_data_buf_addr_r_reg[4] ; output [14:0]\req_row_r_lcl_reg[14] ; output [6:0]\req_col_r_reg[9] ; output [287:0]\my_empty_reg[7] ; output [255:0]\s_axi_rdata[255] ; input CLK; input pointer_we; input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; input rd_buf_we; input [1:0]DIA; input [1:0]DIB; input [1:0]DIC; input [6:0]\read_fifo.fifo_out_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; input app_en_ns1; input [0:0]E; input app_rd_data_end_ns; input reset_reg; input [0:0]mc_app_cmd; input [1:0]idle_ns; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input mc_app_wdf_wren_reg; input w_cmd_rdy; input [31:0]D; input [31:0]mc_app_wdf_mask_reg; input [255:0]wready_reg_rep__1; input [255:0]mc_app_wdf_data_reg; input accept_ns; input bypass__0; input [0:0]app_rdy_r_reg; input [24:0]\axaddr_incr_reg[29] ; input [255:0]app_wdf_data; input [31:0]app_wdf_mask; input [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire CLK; wire [31:0]D; wire [1:0]DIA; wire [1:0]DIB; wire [1:0]DIC; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [0:0]E; wire [4:0]Q; wire accept_ns; wire app_en_ns1; wire app_en_r1; wire app_hi_pri_r2; wire app_rd_data_end_ns; wire app_rd_data_valid; wire app_rdy; wire app_rdy_ns; wire [0:0]app_rdy_r_reg; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire [24:0]\axaddr_incr_reg[29] ; wire bypass__0; wire [1:0]cmd; wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire hi_priority; wire [1:0]idle_ns; wire [0:0]mc_app_cmd; wire [255:0]mc_app_wdf_data_reg; wire [31:0]mc_app_wdf_mask_reg; wire mc_app_wdf_wren_reg; wire [287:0]\my_empty_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_end_reg ; wire [1:0]\not_strict_mode.app_rd_data_reg[101] ; wire [1:0]\not_strict_mode.app_rd_data_reg[103] ; wire [1:0]\not_strict_mode.app_rd_data_reg[105] ; wire [1:0]\not_strict_mode.app_rd_data_reg[107] ; wire [1:0]\not_strict_mode.app_rd_data_reg[109] ; wire [1:0]\not_strict_mode.app_rd_data_reg[111] ; wire [1:0]\not_strict_mode.app_rd_data_reg[113] ; wire [1:0]\not_strict_mode.app_rd_data_reg[115] ; wire [1:0]\not_strict_mode.app_rd_data_reg[117] ; wire [1:0]\not_strict_mode.app_rd_data_reg[119] ; wire [1:0]\not_strict_mode.app_rd_data_reg[11] ; wire [1:0]\not_strict_mode.app_rd_data_reg[121] ; wire [1:0]\not_strict_mode.app_rd_data_reg[123] ; wire [1:0]\not_strict_mode.app_rd_data_reg[125] ; wire [1:0]\not_strict_mode.app_rd_data_reg[127] ; wire [1:0]\not_strict_mode.app_rd_data_reg[129] ; wire [1:0]\not_strict_mode.app_rd_data_reg[131] ; wire [1:0]\not_strict_mode.app_rd_data_reg[133] ; wire [1:0]\not_strict_mode.app_rd_data_reg[135] ; wire [1:0]\not_strict_mode.app_rd_data_reg[137] ; wire [1:0]\not_strict_mode.app_rd_data_reg[139] ; wire [1:0]\not_strict_mode.app_rd_data_reg[13] ; wire [1:0]\not_strict_mode.app_rd_data_reg[141] ; wire [1:0]\not_strict_mode.app_rd_data_reg[143] ; wire [1:0]\not_strict_mode.app_rd_data_reg[145] ; wire [1:0]\not_strict_mode.app_rd_data_reg[147] ; wire [1:0]\not_strict_mode.app_rd_data_reg[149] ; wire [1:0]\not_strict_mode.app_rd_data_reg[151] ; wire [1:0]\not_strict_mode.app_rd_data_reg[153] ; wire [1:0]\not_strict_mode.app_rd_data_reg[155] ; wire [1:0]\not_strict_mode.app_rd_data_reg[157] ; wire [1:0]\not_strict_mode.app_rd_data_reg[159] ; wire [1:0]\not_strict_mode.app_rd_data_reg[15] ; wire [1:0]\not_strict_mode.app_rd_data_reg[161] ; wire [1:0]\not_strict_mode.app_rd_data_reg[163] ; wire [1:0]\not_strict_mode.app_rd_data_reg[165] ; wire [1:0]\not_strict_mode.app_rd_data_reg[167] ; wire [1:0]\not_strict_mode.app_rd_data_reg[169] ; wire [1:0]\not_strict_mode.app_rd_data_reg[171] ; wire [1:0]\not_strict_mode.app_rd_data_reg[173] ; wire [1:0]\not_strict_mode.app_rd_data_reg[175] ; wire [1:0]\not_strict_mode.app_rd_data_reg[177] ; wire [1:0]\not_strict_mode.app_rd_data_reg[179] ; wire [1:0]\not_strict_mode.app_rd_data_reg[17] ; wire [1:0]\not_strict_mode.app_rd_data_reg[181] ; wire [1:0]\not_strict_mode.app_rd_data_reg[183] ; wire [1:0]\not_strict_mode.app_rd_data_reg[185] ; wire [1:0]\not_strict_mode.app_rd_data_reg[187] ; wire [1:0]\not_strict_mode.app_rd_data_reg[189] ; wire [1:0]\not_strict_mode.app_rd_data_reg[191] ; wire [1:0]\not_strict_mode.app_rd_data_reg[193] ; wire [1:0]\not_strict_mode.app_rd_data_reg[195] ; wire [1:0]\not_strict_mode.app_rd_data_reg[197] ; wire [1:0]\not_strict_mode.app_rd_data_reg[199] ; wire [1:0]\not_strict_mode.app_rd_data_reg[19] ; wire [1:0]\not_strict_mode.app_rd_data_reg[201] ; wire [1:0]\not_strict_mode.app_rd_data_reg[203] ; wire [1:0]\not_strict_mode.app_rd_data_reg[205] ; wire [1:0]\not_strict_mode.app_rd_data_reg[207] ; wire [1:0]\not_strict_mode.app_rd_data_reg[209] ; wire [1:0]\not_strict_mode.app_rd_data_reg[211] ; wire [1:0]\not_strict_mode.app_rd_data_reg[213] ; wire [1:0]\not_strict_mode.app_rd_data_reg[215] ; wire [1:0]\not_strict_mode.app_rd_data_reg[217] ; wire [1:0]\not_strict_mode.app_rd_data_reg[219] ; wire [1:0]\not_strict_mode.app_rd_data_reg[21] ; wire [1:0]\not_strict_mode.app_rd_data_reg[221] ; wire [1:0]\not_strict_mode.app_rd_data_reg[223] ; wire [1:0]\not_strict_mode.app_rd_data_reg[225] ; wire [1:0]\not_strict_mode.app_rd_data_reg[227] ; wire [1:0]\not_strict_mode.app_rd_data_reg[229] ; wire [1:0]\not_strict_mode.app_rd_data_reg[231] ; wire [1:0]\not_strict_mode.app_rd_data_reg[233] ; wire [1:0]\not_strict_mode.app_rd_data_reg[235] ; wire [1:0]\not_strict_mode.app_rd_data_reg[237] ; wire [1:0]\not_strict_mode.app_rd_data_reg[239] ; wire [1:0]\not_strict_mode.app_rd_data_reg[23] ; wire [1:0]\not_strict_mode.app_rd_data_reg[241] ; wire [1:0]\not_strict_mode.app_rd_data_reg[243] ; wire [1:0]\not_strict_mode.app_rd_data_reg[245] ; wire [1:0]\not_strict_mode.app_rd_data_reg[247] ; wire [1:0]\not_strict_mode.app_rd_data_reg[249] ; wire [1:0]\not_strict_mode.app_rd_data_reg[251] ; wire [1:0]\not_strict_mode.app_rd_data_reg[253] ; wire [1:0]\not_strict_mode.app_rd_data_reg[255] ; wire [1:0]\not_strict_mode.app_rd_data_reg[25] ; wire [1:0]\not_strict_mode.app_rd_data_reg[27] ; wire [1:0]\not_strict_mode.app_rd_data_reg[29] ; wire [1:0]\not_strict_mode.app_rd_data_reg[31] ; wire [1:0]\not_strict_mode.app_rd_data_reg[33] ; wire [1:0]\not_strict_mode.app_rd_data_reg[35] ; wire [1:0]\not_strict_mode.app_rd_data_reg[37] ; wire [1:0]\not_strict_mode.app_rd_data_reg[39] ; wire [1:0]\not_strict_mode.app_rd_data_reg[41] ; wire [1:0]\not_strict_mode.app_rd_data_reg[43] ; wire [1:0]\not_strict_mode.app_rd_data_reg[45] ; wire [1:0]\not_strict_mode.app_rd_data_reg[47] ; wire [1:0]\not_strict_mode.app_rd_data_reg[49] ; wire [1:0]\not_strict_mode.app_rd_data_reg[51] ; wire [1:0]\not_strict_mode.app_rd_data_reg[53] ; wire [1:0]\not_strict_mode.app_rd_data_reg[55] ; wire [1:0]\not_strict_mode.app_rd_data_reg[57] ; wire [1:0]\not_strict_mode.app_rd_data_reg[59] ; wire [1:0]\not_strict_mode.app_rd_data_reg[61] ; wire [1:0]\not_strict_mode.app_rd_data_reg[63] ; wire [1:0]\not_strict_mode.app_rd_data_reg[65] ; wire [1:0]\not_strict_mode.app_rd_data_reg[67] ; wire [1:0]\not_strict_mode.app_rd_data_reg[69] ; wire [1:0]\not_strict_mode.app_rd_data_reg[71] ; wire [1:0]\not_strict_mode.app_rd_data_reg[73] ; wire [1:0]\not_strict_mode.app_rd_data_reg[75] ; wire [1:0]\not_strict_mode.app_rd_data_reg[77] ; wire [1:0]\not_strict_mode.app_rd_data_reg[79] ; wire [1:0]\not_strict_mode.app_rd_data_reg[7] ; wire [1:0]\not_strict_mode.app_rd_data_reg[81] ; wire [1:0]\not_strict_mode.app_rd_data_reg[83] ; wire [1:0]\not_strict_mode.app_rd_data_reg[85] ; wire [1:0]\not_strict_mode.app_rd_data_reg[87] ; wire [1:0]\not_strict_mode.app_rd_data_reg[89] ; wire [1:0]\not_strict_mode.app_rd_data_reg[91] ; wire [1:0]\not_strict_mode.app_rd_data_reg[93] ; wire [1:0]\not_strict_mode.app_rd_data_reg[95] ; wire [1:0]\not_strict_mode.app_rd_data_reg[97] ; wire [1:0]\not_strict_mode.app_rd_data_reg[99] ; wire [1:0]\not_strict_mode.app_rd_data_reg[9] ; wire [1:0]occ_cnt_r; wire [0:0]p_0_in; wire p_28_out; wire p_67_out; wire pointer_we; wire [3:0]pointer_wr_addr; wire [3:0]pointer_wr_data; wire ram_init_done_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rd_accepted; wire rd_buf_we; wire [4:0]rd_data_buf_addr_r; wire [3:0]\read_data_indx.rd_data_indx_r_reg__0 ; wire [6:0]\read_fifo.fifo_out_data_r_reg[7] ; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [6:0]\req_col_r_reg[9] ; wire [4:0]\req_data_buf_addr_r_reg[4] ; wire [14:0]\req_row_r_lcl_reg[14] ; wire reset_reg; wire [255:0]\s_axi_rdata[255] ; wire ui_cmd0_n_13; wire ui_cmd0_n_14; wire ui_cmd0_n_16; wire ui_rd_data0_n_264; wire ui_rd_data0_n_272; wire use_addr; wire w_cmd_rdy; wire wr_accepted; wire [3:0]wr_data_buf_addr; wire [1:0]wr_req_cnt_r; wire [255:0]wready_reg_rep__1; ddr3_ifmig_7series_v4_0_ui_cmd ui_cmd0 (.CLK(CLK), .E(app_rdy), .Q(occ_cnt_r), .app_en_ns1(app_en_ns1), .app_en_r1(app_en_r1), .app_hi_pri_r2(app_hi_pri_r2), .app_rdy_ns(app_rdy_ns), .app_rdy_r_reg_0(app_rdy_r_reg), .\axaddr_incr_reg[29] (\axaddr_incr_reg[29] ), .cmd(cmd), .hi_priority(hi_priority), .idle_ns(idle_ns), .mc_app_cmd(mc_app_cmd), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (rd_data_buf_addr_r), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] (ui_cmd0_n_16), .p_0_in(p_0_in), .p_28_out(p_28_out), .p_67_out(p_67_out), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0), .rd_accepted(rd_accepted), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ), .\req_col_r_reg[9] (\req_col_r_reg[9] ), .\req_data_buf_addr_r_reg[4] (\req_data_buf_addr_r_reg[4] ), .\req_row_r_lcl_reg[14] (\req_row_r_lcl_reg[14] ), .reset_reg(reset_reg), .use_addr(use_addr), .wr_accepted(wr_accepted), .wr_data_buf_addr(wr_data_buf_addr), .wr_req_cnt_r(wr_req_cnt_r), .\wr_req_counter.wr_req_cnt_r_reg[3] (ui_cmd0_n_14), .\wr_req_counter.wr_req_cnt_r_reg[4] (ui_cmd0_n_13)); ddr3_ifmig_7series_v4_0_ui_rd_data ui_rd_data0 (.ADDRD(pointer_wr_addr), .CLK(CLK), .D(ui_rd_data0_n_264), .DIA(DIA), .DIB(DIB), .DIC(DIC), .DOA(DOA), .DOB(DOB), .DOC(DOC), .Q(Q), .app_rd_data_end_ns(app_rd_data_end_ns), .app_rd_data_valid(app_rd_data_valid), .bypass__0(bypass__0), .\cmd_pipe_plus.wr_data_addr_reg[3] (\cmd_pipe_plus.wr_data_addr_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .\not_strict_mode.app_rd_data_end_reg_0 (\not_strict_mode.app_rd_data_end_reg ), .\not_strict_mode.app_rd_data_reg[101]_0 (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[103]_0 (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[105]_0 (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[107]_0 (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[109]_0 (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[111]_0 (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[113]_0 (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[115]_0 (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[117]_0 (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[119]_0 (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11]_0 (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[121]_0 (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[123]_0 (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[125]_0 (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[127]_0 (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[129]_0 (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[131]_0 (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[133]_0 (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[135]_0 (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[137]_0 (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[139]_0 (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13]_0 (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[141]_0 (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[143]_0 (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[145]_0 (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[147]_0 (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[149]_0 (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[151]_0 (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[153]_0 (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[155]_0 (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[157]_0 (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[159]_0 (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[161]_0 (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[163]_0 (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[165]_0 (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[167]_0 (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[169]_0 (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[171]_0 (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[173]_0 (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[175]_0 (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[177]_0 (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[179]_0 (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17]_0 (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[181]_0 (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[183]_0 (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[185]_0 (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[187]_0 (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[189]_0 (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[191]_0 (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[193]_0 (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[195]_0 (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[197]_0 (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[199]_0 (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[19]_0 (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[201]_0 (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[203]_0 (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[205]_0 (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[207]_0 (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[209]_0 (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[211]_0 (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[213]_0 (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[215]_0 (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[217]_0 (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[219]_0 (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[21]_0 (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[221]_0 (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[223]_0 (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[225]_0 (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[227]_0 (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[229]_0 (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[233]_0 (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[235]_0 (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[237]_0 (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[241]_0 (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[243]_0 (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[245]_0 (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[249]_0 (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[251]_0 (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[253]_0 (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[25]_0 (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[27]_0 (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[29]_0 (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[33]_0 (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[35]_0 (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[37]_0 (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[39]_0 (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[41]_0 (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[43]_0 (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[45]_0 (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[47]_0 (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[49]_0 (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[51]_0 (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[53]_0 (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[55]_0 (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[57]_0 (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[59]_0 (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[61]_0 (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[63]_0 (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[65]_0 (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[67]_0 (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[69]_0 (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[71]_0 (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[73]_0 (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[75]_0 (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[77]_0 (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[79]_0 (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[81]_0 (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[83]_0 (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[85]_0 (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[87]_0 (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.app_rd_data_reg[89]_0 (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[91]_0 (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[93]_0 (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[95]_0 (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[97]_0 (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[99]_0 (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9]_0 (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 (rd_data_buf_addr_r), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 (ui_cmd0_n_16), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 (occ_cnt_r), .\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 (ram_init_done_r), .pointer_wr_data(pointer_wr_data), .rd_accepted(rd_accepted), .\rd_buf_indx.ram_init_done_r_lcl_reg_0 (ui_rd_data0_n_272), .rd_buf_we(rd_buf_we), .\read_data_indx.rd_data_indx_r_reg[3] (\read_data_indx.rd_data_indx_r_reg__0 ), .\read_fifo.fifo_out_data_r_reg[7] (\read_fifo.fifo_out_data_r_reg[7] ), .reset_reg(reset_reg), .\s_axi_rdata[255] (\s_axi_rdata[255] )); ddr3_ifmig_7series_v4_0_ui_wr_data ui_wr_data0 (.ADDRD(pointer_wr_addr), .CLK(CLK), .D(D), .E(E), .Q(\read_data_indx.rd_data_indx_r_reg__0 ), .accept_ns(accept_ns), .app_rdy_ns(app_rdy_ns), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .\cmd_pipe_plus.wr_data_addr_reg[3] (\cmd_pipe_plus.wr_data_addr_reg[3] ), .mc_app_wdf_data_reg(mc_app_wdf_data_reg), .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg), .\mc_app_wdf_mask_reg_reg[0] (app_wdf_rdy), .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg), .\my_empty_reg[7] (\my_empty_reg[7] ), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] (ui_rd_data0_n_264), .p_0_in(p_0_in), .pointer_we(pointer_we), .pointer_wr_data(pointer_wr_data), .ram_init_done_r(ram_init_done_r), .\rd_buf_indx.ram_init_done_r_lcl_reg (ui_rd_data0_n_272), .\read_data_indx.rd_data_upd_indx_r_reg_0 (ui_cmd0_n_13), .reset_reg(reset_reg), .w_cmd_rdy(w_cmd_rdy), .wr_accepted(wr_accepted), .wr_data_buf_addr(wr_data_buf_addr), .\wr_req_counter.wr_req_cnt_r_reg[1]_0 (wr_req_cnt_r), .\wr_req_counter.wr_req_cnt_r_reg[1]_1 (ui_cmd0_n_14), .wready_reg_rep__1(wready_reg_rep__1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ui_wr_data" *) module ddr3_ifmig_7series_v4_0_ui_wr_data (wr_data_buf_addr, p_0_in, \mc_app_wdf_mask_reg_reg[0] , app_rdy_ns, \wr_req_counter.wr_req_cnt_r_reg[1]_0 , Q, \my_empty_reg[7] , CLK, pointer_we, pointer_wr_data, ADDRD, \cmd_pipe_plus.wr_data_addr_reg[3] , E, mc_app_wdf_wren_reg, w_cmd_rdy, reset_reg, D, mc_app_wdf_mask_reg, wready_reg_rep__1, mc_app_wdf_data_reg, \not_strict_mode.occupied_counter.occ_cnt_r_reg[4] , accept_ns, wr_accepted, \wr_req_counter.wr_req_cnt_r_reg[1]_1 , \read_data_indx.rd_data_upd_indx_r_reg_0 , \rd_buf_indx.ram_init_done_r_lcl_reg , ram_init_done_r, app_wdf_data, app_wdf_mask); output [3:0]wr_data_buf_addr; output [0:0]p_0_in; output \mc_app_wdf_mask_reg_reg[0] ; output app_rdy_ns; output [1:0]\wr_req_counter.wr_req_cnt_r_reg[1]_0 ; output [3:0]Q; output [287:0]\my_empty_reg[7] ; input CLK; input pointer_we; input [3:0]pointer_wr_data; input [3:0]ADDRD; input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; input [0:0]E; input mc_app_wdf_wren_reg; input w_cmd_rdy; input reset_reg; input [31:0]D; input [31:0]mc_app_wdf_mask_reg; input [255:0]wready_reg_rep__1; input [255:0]mc_app_wdf_data_reg; input [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ; input accept_ns; input wr_accepted; input \wr_req_counter.wr_req_cnt_r_reg[1]_1 ; input \read_data_indx.rd_data_upd_indx_r_reg_0 ; input \rd_buf_indx.ram_init_done_r_lcl_reg ; input ram_init_done_r; input [255:0]app_wdf_data; input [31:0]app_wdf_mask; wire [3:0]ADDRD; wire CLK; wire [31:0]D; wire [0:0]E; wire [3:0]Q; wire accept_ns; wire app_rdy_ns; wire app_rdy_r_i_2_n_0; wire app_rdy_r_i_3_n_0; wire [255:0]app_wdf_data; wire [255:0]app_wdf_data_r1; wire app_wdf_end_ns1; wire app_wdf_end_r1; wire [31:0]app_wdf_mask; wire [31:0]app_wdf_mask_r1; wire app_wdf_rdy_r_copy1; wire app_wdf_rdy_r_copy2; wire app_wdf_rdy_r_copy3; wire app_wdf_wren_ns1; wire app_wdf_wren_r1; wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; wire [3:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 ; wire [255:0]mc_app_wdf_data_reg; wire [31:0]mc_app_wdf_mask_reg; wire \mc_app_wdf_mask_reg_reg[0] ; wire mc_app_wdf_wren_reg; wire [287:0]\my_empty_reg[7] ; wire [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ; wire \occupied_counter.occ_cnt[0]_i_1_n_0 ; wire \occupied_counter.occ_cnt[10]_i_1_n_0 ; wire \occupied_counter.occ_cnt[11]_i_1_n_0 ; wire \occupied_counter.occ_cnt[12]_i_1_n_0 ; wire \occupied_counter.occ_cnt[13]_i_1_n_0 ; wire \occupied_counter.occ_cnt[14]_i_1_n_0 ; wire \occupied_counter.occ_cnt[15]_i_1_n_0 ; wire \occupied_counter.occ_cnt[15]_i_2_n_0 ; wire \occupied_counter.occ_cnt[1]_i_1_n_0 ; wire \occupied_counter.occ_cnt[2]_i_1_n_0 ; wire \occupied_counter.occ_cnt[3]_i_1_n_0 ; wire \occupied_counter.occ_cnt[4]_i_1_n_0 ; wire \occupied_counter.occ_cnt[5]_i_1_n_0 ; wire \occupied_counter.occ_cnt[6]_i_1_n_0 ; wire \occupied_counter.occ_cnt[7]_i_1_n_0 ; wire \occupied_counter.occ_cnt[8]_i_1_n_0 ; wire \occupied_counter.occ_cnt[9]_i_1_n_0 ; wire \occupied_counter.occ_cnt_reg_n_0_[0] ; wire \occupied_counter.occ_cnt_reg_n_0_[10] ; wire \occupied_counter.occ_cnt_reg_n_0_[11] ; wire \occupied_counter.occ_cnt_reg_n_0_[12] ; wire \occupied_counter.occ_cnt_reg_n_0_[13] ; wire \occupied_counter.occ_cnt_reg_n_0_[15] ; wire \occupied_counter.occ_cnt_reg_n_0_[1] ; wire \occupied_counter.occ_cnt_reg_n_0_[2] ; wire \occupied_counter.occ_cnt_reg_n_0_[3] ; wire \occupied_counter.occ_cnt_reg_n_0_[4] ; wire \occupied_counter.occ_cnt_reg_n_0_[5] ; wire \occupied_counter.occ_cnt_reg_n_0_[6] ; wire \occupied_counter.occ_cnt_reg_n_0_[7] ; wire \occupied_counter.occ_cnt_reg_n_0_[8] ; wire \occupied_counter.occ_cnt_reg_n_0_[9] ; wire [0:0]p_0_in; wire [3:0]p_0_in__0; wire [1:1]p_0_in__0_0; wire [3:0]p_0_in__0__0; wire [3:0]p_0_in__1; wire p_4_in; wire pointer_we; wire [3:0]pointer_wr_data; wire ram_init_done_r; wire \rd_buf_indx.ram_init_done_r_lcl_reg ; wire \read_data_indx.rd_data_upd_indx_r_reg_0 ; wire reset_reg; wire w_cmd_rdy; wire wb_wr_data_addr0_ns; wire wb_wr_data_addr0_r; wire [4:1]wb_wr_data_addr_r; wire [4:1]wb_wr_data_addr_w; wire wdf_rdy_ns; wire wr_accepted; wire [287:0]wr_buf_in_data; wire [287:0]wr_buf_out_data_w; wire wr_data_addr_le; wire [3:0]wr_data_buf_addr; wire [3:0]wr_data_pntr; wire [4:2]wr_req_cnt_r; wire \wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ; wire [1:0]\wr_req_counter.wr_req_cnt_r_reg[1]_0 ; wire \wr_req_counter.wr_req_cnt_r_reg[1]_1 ; wire [255:0]wready_reg_rep__1; wire [3:0]\write_data_control.wr_data_indx_r_reg__0 ; wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ; LUT5 #( .INIT(32'h44440444)) app_rdy_r_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ), .I1(accept_ns), .I2(app_rdy_r_i_2_n_0), .I3(app_rdy_r_i_3_n_0), .I4(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ), .O(app_rdy_ns)); LUT6 #( .INIT(64'hFFFF00007FFE8001)) app_rdy_r_i_2 (.I0(wr_req_cnt_r[3]), .I1(wr_req_cnt_r[2]), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I3(\wr_req_counter.wr_req_cnt_r_reg[1]_1 ), .I4(wr_req_cnt_r[4]), .I5(\read_data_indx.rd_data_upd_indx_r_reg_0 ), .O(app_rdy_r_i_2_n_0)); LUT6 #( .INIT(64'h0040010000001001)) app_rdy_r_i_3 (.I0(reset_reg), .I1(wr_req_cnt_r[2]), .I2(wr_accepted), .I3(p_0_in), .I4(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I5(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .O(app_rdy_r_i_3_n_0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[0] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[0]), .Q(app_wdf_data_r1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[100] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[100]), .Q(app_wdf_data_r1[100]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[101] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[101]), .Q(app_wdf_data_r1[101]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[102] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[102]), .Q(app_wdf_data_r1[102]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[103] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[103]), .Q(app_wdf_data_r1[103]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[104] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[104]), .Q(app_wdf_data_r1[104]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[105] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[105]), .Q(app_wdf_data_r1[105]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[106] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[106]), .Q(app_wdf_data_r1[106]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[107] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[107]), .Q(app_wdf_data_r1[107]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[108] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[108]), .Q(app_wdf_data_r1[108]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[109] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[109]), .Q(app_wdf_data_r1[109]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[10] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[10]), .Q(app_wdf_data_r1[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[110] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[110]), .Q(app_wdf_data_r1[110]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[111] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[111]), .Q(app_wdf_data_r1[111]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[112] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[112]), .Q(app_wdf_data_r1[112]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[113] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[113]), .Q(app_wdf_data_r1[113]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[114] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[114]), .Q(app_wdf_data_r1[114]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[115] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[115]), .Q(app_wdf_data_r1[115]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[116] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[116]), .Q(app_wdf_data_r1[116]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[117] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[117]), .Q(app_wdf_data_r1[117]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[118] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[118]), .Q(app_wdf_data_r1[118]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[119] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[119]), .Q(app_wdf_data_r1[119]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[11] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[11]), .Q(app_wdf_data_r1[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[120] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[120]), .Q(app_wdf_data_r1[120]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[121] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[121]), .Q(app_wdf_data_r1[121]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[122] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[122]), .Q(app_wdf_data_r1[122]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[123] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[123]), .Q(app_wdf_data_r1[123]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[124] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[124]), .Q(app_wdf_data_r1[124]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[125] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[125]), .Q(app_wdf_data_r1[125]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[126] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[126]), .Q(app_wdf_data_r1[126]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[127] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[127]), .Q(app_wdf_data_r1[127]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[128] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[128]), .Q(app_wdf_data_r1[128]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[129] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[129]), .Q(app_wdf_data_r1[129]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[12] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[12]), .Q(app_wdf_data_r1[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[130] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[130]), .Q(app_wdf_data_r1[130]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[131] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[131]), .Q(app_wdf_data_r1[131]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[132] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[132]), .Q(app_wdf_data_r1[132]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[133] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[133]), .Q(app_wdf_data_r1[133]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[134] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[134]), .Q(app_wdf_data_r1[134]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[135] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[135]), .Q(app_wdf_data_r1[135]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[136] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[136]), .Q(app_wdf_data_r1[136]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[137] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[137]), .Q(app_wdf_data_r1[137]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[138] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[138]), .Q(app_wdf_data_r1[138]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[139] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[139]), .Q(app_wdf_data_r1[139]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[13] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[13]), .Q(app_wdf_data_r1[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[140] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[140]), .Q(app_wdf_data_r1[140]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[141] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[141]), .Q(app_wdf_data_r1[141]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[142] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[142]), .Q(app_wdf_data_r1[142]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[143] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[143]), .Q(app_wdf_data_r1[143]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[144] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[144]), .Q(app_wdf_data_r1[144]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[145] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[145]), .Q(app_wdf_data_r1[145]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[146] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[146]), .Q(app_wdf_data_r1[146]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[147] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[147]), .Q(app_wdf_data_r1[147]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[148] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[148]), .Q(app_wdf_data_r1[148]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[149] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[149]), .Q(app_wdf_data_r1[149]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[14] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[14]), .Q(app_wdf_data_r1[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[150] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[150]), .Q(app_wdf_data_r1[150]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[151] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[151]), .Q(app_wdf_data_r1[151]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[152] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[152]), .Q(app_wdf_data_r1[152]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[153] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[153]), .Q(app_wdf_data_r1[153]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[154] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[154]), .Q(app_wdf_data_r1[154]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[155] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[155]), .Q(app_wdf_data_r1[155]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[156] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[156]), .Q(app_wdf_data_r1[156]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[157] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[157]), .Q(app_wdf_data_r1[157]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[158] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[158]), .Q(app_wdf_data_r1[158]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[159] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[159]), .Q(app_wdf_data_r1[159]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[15] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[15]), .Q(app_wdf_data_r1[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[160] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[160]), .Q(app_wdf_data_r1[160]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[161] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[161]), .Q(app_wdf_data_r1[161]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[162] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[162]), .Q(app_wdf_data_r1[162]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[163] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[163]), .Q(app_wdf_data_r1[163]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[164] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[164]), .Q(app_wdf_data_r1[164]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[165] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[165]), .Q(app_wdf_data_r1[165]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[166] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[166]), .Q(app_wdf_data_r1[166]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[167] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[167]), .Q(app_wdf_data_r1[167]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[168] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[168]), .Q(app_wdf_data_r1[168]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[169] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[169]), .Q(app_wdf_data_r1[169]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[16] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[16]), .Q(app_wdf_data_r1[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[170] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[170]), .Q(app_wdf_data_r1[170]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[171] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[171]), .Q(app_wdf_data_r1[171]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[172] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[172]), .Q(app_wdf_data_r1[172]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[173] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[173]), .Q(app_wdf_data_r1[173]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[174] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[174]), .Q(app_wdf_data_r1[174]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[175] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[175]), .Q(app_wdf_data_r1[175]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[176] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[176]), .Q(app_wdf_data_r1[176]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[177] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[177]), .Q(app_wdf_data_r1[177]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[178] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[178]), .Q(app_wdf_data_r1[178]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[179] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[179]), .Q(app_wdf_data_r1[179]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[17] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[17]), .Q(app_wdf_data_r1[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[180] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[180]), .Q(app_wdf_data_r1[180]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[181] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[181]), .Q(app_wdf_data_r1[181]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[182] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[182]), .Q(app_wdf_data_r1[182]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[183] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[183]), .Q(app_wdf_data_r1[183]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[184] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[184]), .Q(app_wdf_data_r1[184]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[185] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[185]), .Q(app_wdf_data_r1[185]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[186] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[186]), .Q(app_wdf_data_r1[186]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[187] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[187]), .Q(app_wdf_data_r1[187]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[188] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[188]), .Q(app_wdf_data_r1[188]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[189] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[189]), .Q(app_wdf_data_r1[189]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[18] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[18]), .Q(app_wdf_data_r1[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[190] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[190]), .Q(app_wdf_data_r1[190]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[191] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[191]), .Q(app_wdf_data_r1[191]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[192] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[192]), .Q(app_wdf_data_r1[192]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[193] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[193]), .Q(app_wdf_data_r1[193]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[194] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[194]), .Q(app_wdf_data_r1[194]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[195] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[195]), .Q(app_wdf_data_r1[195]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[196] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[196]), .Q(app_wdf_data_r1[196]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[197] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[197]), .Q(app_wdf_data_r1[197]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[198] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[198]), .Q(app_wdf_data_r1[198]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[199] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[199]), .Q(app_wdf_data_r1[199]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[19] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[19]), .Q(app_wdf_data_r1[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[1] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[1]), .Q(app_wdf_data_r1[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[200] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[200]), .Q(app_wdf_data_r1[200]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[201] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[201]), .Q(app_wdf_data_r1[201]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[202] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[202]), .Q(app_wdf_data_r1[202]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[203] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[203]), .Q(app_wdf_data_r1[203]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[204] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[204]), .Q(app_wdf_data_r1[204]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[205] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[205]), .Q(app_wdf_data_r1[205]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[206] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[206]), .Q(app_wdf_data_r1[206]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[207] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[207]), .Q(app_wdf_data_r1[207]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[208] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[208]), .Q(app_wdf_data_r1[208]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[209] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[209]), .Q(app_wdf_data_r1[209]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[20] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[20]), .Q(app_wdf_data_r1[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[210] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[210]), .Q(app_wdf_data_r1[210]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[211] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[211]), .Q(app_wdf_data_r1[211]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[212] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[212]), .Q(app_wdf_data_r1[212]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[213] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[213]), .Q(app_wdf_data_r1[213]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[214] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[214]), .Q(app_wdf_data_r1[214]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[215] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[215]), .Q(app_wdf_data_r1[215]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[216] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[216]), .Q(app_wdf_data_r1[216]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[217] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[217]), .Q(app_wdf_data_r1[217]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[218] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[218]), .Q(app_wdf_data_r1[218]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[219] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[219]), .Q(app_wdf_data_r1[219]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[21] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[21]), .Q(app_wdf_data_r1[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[220] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[220]), .Q(app_wdf_data_r1[220]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[221] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[221]), .Q(app_wdf_data_r1[221]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[222] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[222]), .Q(app_wdf_data_r1[222]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[223] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[223]), .Q(app_wdf_data_r1[223]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[224] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[224]), .Q(app_wdf_data_r1[224]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[225] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[225]), .Q(app_wdf_data_r1[225]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[226] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[226]), .Q(app_wdf_data_r1[226]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[227] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[227]), .Q(app_wdf_data_r1[227]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[228] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[228]), .Q(app_wdf_data_r1[228]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[229] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[229]), .Q(app_wdf_data_r1[229]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[22] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[22]), .Q(app_wdf_data_r1[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[230] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[230]), .Q(app_wdf_data_r1[230]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[231] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[231]), .Q(app_wdf_data_r1[231]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[232] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[232]), .Q(app_wdf_data_r1[232]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[233] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[233]), .Q(app_wdf_data_r1[233]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[234] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[234]), .Q(app_wdf_data_r1[234]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[235] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[235]), .Q(app_wdf_data_r1[235]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[236] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[236]), .Q(app_wdf_data_r1[236]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[237] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[237]), .Q(app_wdf_data_r1[237]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[238] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[238]), .Q(app_wdf_data_r1[238]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[239] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[239]), .Q(app_wdf_data_r1[239]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[23] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[23]), .Q(app_wdf_data_r1[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[240] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[240]), .Q(app_wdf_data_r1[240]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[241] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[241]), .Q(app_wdf_data_r1[241]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[242] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[242]), .Q(app_wdf_data_r1[242]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[243] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[243]), .Q(app_wdf_data_r1[243]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[244] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[244]), .Q(app_wdf_data_r1[244]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[245] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[245]), .Q(app_wdf_data_r1[245]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[246] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[246]), .Q(app_wdf_data_r1[246]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[247] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[247]), .Q(app_wdf_data_r1[247]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[248] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[248]), .Q(app_wdf_data_r1[248]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[249] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[249]), .Q(app_wdf_data_r1[249]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[24] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[24]), .Q(app_wdf_data_r1[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[250] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[250]), .Q(app_wdf_data_r1[250]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[251] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[251]), .Q(app_wdf_data_r1[251]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[252] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[252]), .Q(app_wdf_data_r1[252]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[253] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[253]), .Q(app_wdf_data_r1[253]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[254] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[254]), .Q(app_wdf_data_r1[254]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[255] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[255]), .Q(app_wdf_data_r1[255]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[25] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[25]), .Q(app_wdf_data_r1[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[26] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[26]), .Q(app_wdf_data_r1[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[27] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[27]), .Q(app_wdf_data_r1[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[28] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[28]), .Q(app_wdf_data_r1[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[29] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[29]), .Q(app_wdf_data_r1[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[2] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[2]), .Q(app_wdf_data_r1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[30] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[30]), .Q(app_wdf_data_r1[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[31] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[31]), .Q(app_wdf_data_r1[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[32] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[32]), .Q(app_wdf_data_r1[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[33] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[33]), .Q(app_wdf_data_r1[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[34] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[34]), .Q(app_wdf_data_r1[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[35] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[35]), .Q(app_wdf_data_r1[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[36] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[36]), .Q(app_wdf_data_r1[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[37] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[37]), .Q(app_wdf_data_r1[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[38] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[38]), .Q(app_wdf_data_r1[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[39] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[39]), .Q(app_wdf_data_r1[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[3] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[3]), .Q(app_wdf_data_r1[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[40] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[40]), .Q(app_wdf_data_r1[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[41] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[41]), .Q(app_wdf_data_r1[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[42] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[42]), .Q(app_wdf_data_r1[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[43] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[43]), .Q(app_wdf_data_r1[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[44] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[44]), .Q(app_wdf_data_r1[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[45] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[45]), .Q(app_wdf_data_r1[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[46] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[46]), .Q(app_wdf_data_r1[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[47] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[47]), .Q(app_wdf_data_r1[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[48] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[48]), .Q(app_wdf_data_r1[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[49] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[49]), .Q(app_wdf_data_r1[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[4] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[4]), .Q(app_wdf_data_r1[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[50] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[50]), .Q(app_wdf_data_r1[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[51] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[51]), .Q(app_wdf_data_r1[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[52] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[52]), .Q(app_wdf_data_r1[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[53] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[53]), .Q(app_wdf_data_r1[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[54] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[54]), .Q(app_wdf_data_r1[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[55] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[55]), .Q(app_wdf_data_r1[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[56] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[56]), .Q(app_wdf_data_r1[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[57] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[57]), .Q(app_wdf_data_r1[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[58] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[58]), .Q(app_wdf_data_r1[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[59] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[59]), .Q(app_wdf_data_r1[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[5] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[5]), .Q(app_wdf_data_r1[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[60] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[60]), .Q(app_wdf_data_r1[60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[61] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[61]), .Q(app_wdf_data_r1[61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[62] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[62]), .Q(app_wdf_data_r1[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[63] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[63]), .Q(app_wdf_data_r1[63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[64] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[64]), .Q(app_wdf_data_r1[64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[65] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[65]), .Q(app_wdf_data_r1[65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[66] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[66]), .Q(app_wdf_data_r1[66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[67] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[67]), .Q(app_wdf_data_r1[67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[68] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[68]), .Q(app_wdf_data_r1[68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[69] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[69]), .Q(app_wdf_data_r1[69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[6] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[6]), .Q(app_wdf_data_r1[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[70] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[70]), .Q(app_wdf_data_r1[70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[71] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[71]), .Q(app_wdf_data_r1[71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[72] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[72]), .Q(app_wdf_data_r1[72]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[73] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[73]), .Q(app_wdf_data_r1[73]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[74] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[74]), .Q(app_wdf_data_r1[74]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[75] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[75]), .Q(app_wdf_data_r1[75]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[76] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[76]), .Q(app_wdf_data_r1[76]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[77] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[77]), .Q(app_wdf_data_r1[77]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[78] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[78]), .Q(app_wdf_data_r1[78]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[79] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[79]), .Q(app_wdf_data_r1[79]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[7] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[7]), .Q(app_wdf_data_r1[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[80] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[80]), .Q(app_wdf_data_r1[80]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[81] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[81]), .Q(app_wdf_data_r1[81]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[82] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[82]), .Q(app_wdf_data_r1[82]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[83] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[83]), .Q(app_wdf_data_r1[83]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[84] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[84]), .Q(app_wdf_data_r1[84]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[85] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[85]), .Q(app_wdf_data_r1[85]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[86] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[86]), .Q(app_wdf_data_r1[86]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[87] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[87]), .Q(app_wdf_data_r1[87]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[88] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[88]), .Q(app_wdf_data_r1[88]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[89] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[89]), .Q(app_wdf_data_r1[89]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[8] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[8]), .Q(app_wdf_data_r1[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[90] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[90]), .Q(app_wdf_data_r1[90]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[91] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[91]), .Q(app_wdf_data_r1[91]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[92] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[92]), .Q(app_wdf_data_r1[92]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[93] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[93]), .Q(app_wdf_data_r1[93]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[94] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[94]), .Q(app_wdf_data_r1[94]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[95] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[95]), .Q(app_wdf_data_r1[95]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[96] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[96]), .Q(app_wdf_data_r1[96]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[97] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[97]), .Q(app_wdf_data_r1[97]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[98] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[98]), .Q(app_wdf_data_r1[98]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[99] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[99]), .Q(app_wdf_data_r1[99]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_data_r1_reg[9] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[9]), .Q(app_wdf_data_r1[9]), .R(1'b0)); LUT6 #( .INIT(64'h00E200E200FF0000)) app_wdf_end_r1_i_1 (.I0(mc_app_wdf_wren_reg), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(w_cmd_rdy), .I3(reset_reg), .I4(app_wdf_end_r1), .I5(app_wdf_rdy_r_copy2), .O(app_wdf_end_ns1)); FDRE #( .INIT(1'b0)) app_wdf_end_r1_reg (.C(CLK), .CE(1'b1), .D(app_wdf_end_ns1), .Q(app_wdf_end_r1), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[0] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[0]), .Q(app_wdf_mask_r1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[10] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[10]), .Q(app_wdf_mask_r1[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[11] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[11]), .Q(app_wdf_mask_r1[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[12] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[12]), .Q(app_wdf_mask_r1[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[13] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[13]), .Q(app_wdf_mask_r1[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[14] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[14]), .Q(app_wdf_mask_r1[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[15] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[15]), .Q(app_wdf_mask_r1[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[16] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[16]), .Q(app_wdf_mask_r1[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[17] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[17]), .Q(app_wdf_mask_r1[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[18] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[18]), .Q(app_wdf_mask_r1[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[19] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[19]), .Q(app_wdf_mask_r1[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[1] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[1]), .Q(app_wdf_mask_r1[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[20] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[20]), .Q(app_wdf_mask_r1[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[21] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[21]), .Q(app_wdf_mask_r1[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[22] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[22]), .Q(app_wdf_mask_r1[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[23] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[23]), .Q(app_wdf_mask_r1[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[24] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[24]), .Q(app_wdf_mask_r1[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[25] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[25]), .Q(app_wdf_mask_r1[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[26] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[26]), .Q(app_wdf_mask_r1[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[27] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[27]), .Q(app_wdf_mask_r1[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[28] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[28]), .Q(app_wdf_mask_r1[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[29] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[29]), .Q(app_wdf_mask_r1[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[2] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[2]), .Q(app_wdf_mask_r1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[30] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[30]), .Q(app_wdf_mask_r1[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[31] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[31]), .Q(app_wdf_mask_r1[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[3] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[3]), .Q(app_wdf_mask_r1[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[4] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[4]), .Q(app_wdf_mask_r1[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[5] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[5]), .Q(app_wdf_mask_r1[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[6] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[6]), .Q(app_wdf_mask_r1[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[7] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[7]), .Q(app_wdf_mask_r1[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[8] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[8]), .Q(app_wdf_mask_r1[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \app_wdf_mask_r1_reg[9] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[9]), .Q(app_wdf_mask_r1[9]), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) app_wdf_rdy_r_copy1_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(app_wdf_rdy_r_copy1), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) app_wdf_rdy_r_copy2_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(app_wdf_rdy_r_copy2), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) app_wdf_rdy_r_copy3_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(app_wdf_rdy_r_copy3), .R(1'b0)); LUT6 #( .INIT(64'h00E200E200FF0000)) app_wdf_wren_r1_i_1 (.I0(mc_app_wdf_wren_reg), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(w_cmd_rdy), .I3(reset_reg), .I4(app_wdf_wren_r1), .I5(app_wdf_rdy_r_copy2), .O(app_wdf_wren_ns1)); FDRE #( .INIT(1'b0)) app_wdf_wren_r1_reg (.C(CLK), .CE(1'b1), .D(app_wdf_wren_ns1), .Q(app_wdf_wren_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1486" *) LUT1 #( .INIT(2'h1)) \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair1486" *) LUT2 #( .INIT(4'h6)) \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair1484" *) LUT3 #( .INIT(8'h78)) \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair1484" *) LUT4 #( .INIT(16'h7F80)) \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]), .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]), .O(p_0_in__0[3])); FDRE #( .INIT(1'b0)) \data_buf_address_counter.data_buf_addr_cnt_r_reg[0] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[0]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \data_buf_address_counter.data_buf_addr_cnt_r_reg[1] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[1]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \data_buf_address_counter.data_buf_addr_cnt_r_reg[2] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[2]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \data_buf_address_counter.data_buf_addr_cnt_r_reg[3] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[3]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]), .R(reset_reg)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \occupied_counter.app_wdf_rdy_r_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(\mc_app_wdf_mask_reg_reg[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1481" *) LUT4 #( .INIT(16'hEAAA)) \occupied_counter.occ_cnt[0]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ), .I1(app_wdf_rdy_r_copy1), .I2(app_wdf_end_r1), .I3(app_wdf_wren_r1), .O(\occupied_counter.occ_cnt[0]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[10]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[9] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[11] ), .O(\occupied_counter.occ_cnt[10]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[11]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[10] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[12] ), .O(\occupied_counter.occ_cnt[11]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[12]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[11] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[13] ), .O(\occupied_counter.occ_cnt[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1482" *) LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[13]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[12] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(p_4_in), .O(\occupied_counter.occ_cnt[13]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[14]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[13] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[15] ), .O(\occupied_counter.occ_cnt[14]_i_1_n_0 )); LUT4 #( .INIT(16'h6AAA)) \occupied_counter.occ_cnt[15]_i_1 (.I0(p_0_in), .I1(app_wdf_rdy_r_copy1), .I2(app_wdf_end_r1), .I3(app_wdf_wren_r1), .O(\occupied_counter.occ_cnt[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1482" *) LUT4 #( .INIT(16'h8000)) \occupied_counter.occ_cnt[15]_i_2 (.I0(app_wdf_wren_r1), .I1(app_wdf_end_r1), .I2(app_wdf_rdy_r_copy1), .I3(p_4_in), .O(\occupied_counter.occ_cnt[15]_i_2_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[1]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[0] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[2] ), .O(\occupied_counter.occ_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1481" *) LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[2]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[3] ), .O(\occupied_counter.occ_cnt[2]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[3]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[2] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[4] ), .O(\occupied_counter.occ_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[4]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[3] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[5] ), .O(\occupied_counter.occ_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[5]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[4] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[6] ), .O(\occupied_counter.occ_cnt[5]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[6]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[5] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[7] ), .O(\occupied_counter.occ_cnt[6]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[7]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[6] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[8] ), .O(\occupied_counter.occ_cnt[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1479" *) LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[8]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[7] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[9] ), .O(\occupied_counter.occ_cnt[8]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[9]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[8] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[10] ), .O(\occupied_counter.occ_cnt[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[0] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[0]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[0] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[10] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[10]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[10] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[11] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[11]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[11] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[12] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[12]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[12] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[13] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[13]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[13] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[14] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[14]_i_1_n_0 ), .Q(p_4_in), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[15] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[15]_i_2_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[15] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[1] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[1]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[1] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[2] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[2]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[2] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[3] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[3]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[3] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[4] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[4]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[4] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[5] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[5]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[5] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[6] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[6]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[6] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[7] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[7]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[7] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[8] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[8]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[8] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \occupied_counter.occ_cnt_reg[9] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[9]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[9] ), .R(reset_reg)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \pointer_ram.rams[0].RAM32M0 (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }), .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg__0 }), .ADDRD({1'b0,ADDRD}), .DIA({1'b0,1'b0}), .DIB(pointer_wr_data[1:0]), .DIC(pointer_wr_data[1:0]), .DID({1'b0,1'b0}), .DOA(\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(wr_data_buf_addr[1:0]), .DOC(wr_data_pntr[1:0]), .DOD(\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(pointer_we)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \pointer_ram.rams[1].RAM32M0 (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }), .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg__0 }), .ADDRD({1'b0,ADDRD}), .DIA({1'b0,1'b0}), .DIB(pointer_wr_data[3:2]), .DIC(pointer_wr_data[3:2]), .DID({1'b0,1'b0}), .DOA(\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(wr_data_buf_addr[3:2]), .DOC(wr_data_pntr[3:2]), .DOD(\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(pointer_we)); (* SOFT_HLUTNM = "soft_lutpair1487" *) LUT1 #( .INIT(2'h1)) \read_data_indx.rd_data_indx_r[0]_i_1 (.I0(Q[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair1487" *) LUT2 #( .INIT(4'h6)) \read_data_indx.rd_data_indx_r[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair1483" *) LUT3 #( .INIT(8'h78)) \read_data_indx.rd_data_indx_r[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair1483" *) LUT4 #( .INIT(16'h7F80)) \read_data_indx.rd_data_indx_r[3]_i_1 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(p_0_in__1[3])); FDRE #( .INIT(1'b0)) \read_data_indx.rd_data_indx_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in__1[0]), .Q(Q[0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \read_data_indx.rd_data_indx_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in__1[1]), .Q(Q[1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \read_data_indx.rd_data_indx_r_reg[2] (.C(CLK), .CE(E), .D(p_0_in__1[2]), .Q(Q[2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \read_data_indx.rd_data_indx_r_reg[3] (.C(CLK), .CE(E), .D(p_0_in__1[3]), .Q(Q[3]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \read_data_indx.rd_data_upd_indx_r_reg (.C(CLK), .CE(1'b1), .D(E), .Q(p_0_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1480" *) LUT4 #( .INIT(16'h0096)) \wr_req_counter.wr_req_cnt_r[0]_i_1 (.I0(p_0_in), .I1(wr_accepted), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I3(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1480" *) LUT5 #( .INIT(32'h0000D2B4)) \wr_req_counter.wr_req_cnt_r[1]_i_1 (.I0(wr_accepted), .I1(p_0_in), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I3(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I4(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000F7EF0810)) \wr_req_counter.wr_req_cnt_r[2]_i_1 (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I2(p_0_in), .I3(wr_accepted), .I4(wr_req_cnt_r[2]), .I5(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FF7E0081)) \wr_req_counter.wr_req_cnt_r[3]_i_1 (.I0(wr_req_cnt_r[2]), .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_1 ), .I3(\read_data_indx.rd_data_upd_indx_r_reg_0 ), .I4(wr_req_cnt_r[3]), .I5(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h000000009CCCCCC9)) \wr_req_counter.wr_req_cnt_r[4]_i_1 (.I0(\read_data_indx.rd_data_upd_indx_r_reg_0 ), .I1(wr_req_cnt_r[4]), .I2(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ), .I3(wr_req_cnt_r[2]), .I4(wr_req_cnt_r[3]), .I5(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h80FE)) \wr_req_counter.wr_req_cnt_r[4]_i_2 (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I1(wr_accepted), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I3(wr_req_cnt_r[2]), .O(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \wr_req_counter.wr_req_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ), .Q(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_req_counter.wr_req_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ), .Q(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_req_counter.wr_req_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ), .Q(wr_req_cnt_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_req_counter.wr_req_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ), .Q(wr_req_cnt_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wr_req_counter.wr_req_cnt_r_reg[4] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ), .Q(wr_req_cnt_r[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[0] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[0]), .Q(\my_empty_reg[7] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[100] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[100]), .Q(\my_empty_reg[7] [100]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[101] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[101]), .Q(\my_empty_reg[7] [101]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[102] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[102]), .Q(\my_empty_reg[7] [102]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[103] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[103]), .Q(\my_empty_reg[7] [103]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[104] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[104]), .Q(\my_empty_reg[7] [104]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[105] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[105]), .Q(\my_empty_reg[7] [105]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[106] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[106]), .Q(\my_empty_reg[7] [106]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[107] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[107]), .Q(\my_empty_reg[7] [107]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[108] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[108]), .Q(\my_empty_reg[7] [108]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[109] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[109]), .Q(\my_empty_reg[7] [109]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[10] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[10]), .Q(\my_empty_reg[7] [10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[110] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[110]), .Q(\my_empty_reg[7] [110]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[111] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[111]), .Q(\my_empty_reg[7] [111]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[112] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[112]), .Q(\my_empty_reg[7] [112]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[113] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[113]), .Q(\my_empty_reg[7] [113]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[114] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[114]), .Q(\my_empty_reg[7] [114]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[115] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[115]), .Q(\my_empty_reg[7] [115]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[116] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[116]), .Q(\my_empty_reg[7] [116]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[117] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[117]), .Q(\my_empty_reg[7] [117]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[118] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[118]), .Q(\my_empty_reg[7] [118]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[119] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[119]), .Q(\my_empty_reg[7] [119]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[11] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[11]), .Q(\my_empty_reg[7] [11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[120] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[120]), .Q(\my_empty_reg[7] [120]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[121] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[121]), .Q(\my_empty_reg[7] [121]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[122] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[122]), .Q(\my_empty_reg[7] [122]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[123] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[123]), .Q(\my_empty_reg[7] [123]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[124] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[124]), .Q(\my_empty_reg[7] [124]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[125] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[125]), .Q(\my_empty_reg[7] [125]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[126] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[126]), .Q(\my_empty_reg[7] [126]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[127] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[127]), .Q(\my_empty_reg[7] [127]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[128] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[128]), .Q(\my_empty_reg[7] [128]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[129] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[129]), .Q(\my_empty_reg[7] [129]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[12] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[12]), .Q(\my_empty_reg[7] [12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[130] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[130]), .Q(\my_empty_reg[7] [130]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[131] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[131]), .Q(\my_empty_reg[7] [131]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[132] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[132]), .Q(\my_empty_reg[7] [132]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[133] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[133]), .Q(\my_empty_reg[7] [133]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[134] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[134]), .Q(\my_empty_reg[7] [134]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[135] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[135]), .Q(\my_empty_reg[7] [135]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[136] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[136]), .Q(\my_empty_reg[7] [136]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[137] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[137]), .Q(\my_empty_reg[7] [137]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[138] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[138]), .Q(\my_empty_reg[7] [138]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[139] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[139]), .Q(\my_empty_reg[7] [139]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[13] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[13]), .Q(\my_empty_reg[7] [13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[140] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[140]), .Q(\my_empty_reg[7] [140]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[141] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[141]), .Q(\my_empty_reg[7] [141]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[142] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[142]), .Q(\my_empty_reg[7] [142]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[143] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[143]), .Q(\my_empty_reg[7] [143]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[144] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[144]), .Q(\my_empty_reg[7] [144]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[145] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[145]), .Q(\my_empty_reg[7] [145]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[146] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[146]), .Q(\my_empty_reg[7] [146]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[147] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[147]), .Q(\my_empty_reg[7] [147]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[148] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[148]), .Q(\my_empty_reg[7] [148]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[149] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[149]), .Q(\my_empty_reg[7] [149]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[14] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[14]), .Q(\my_empty_reg[7] [14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[150] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[150]), .Q(\my_empty_reg[7] [150]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[151] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[151]), .Q(\my_empty_reg[7] [151]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[152] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[152]), .Q(\my_empty_reg[7] [152]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[153] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[153]), .Q(\my_empty_reg[7] [153]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[154] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[154]), .Q(\my_empty_reg[7] [154]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[155] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[155]), .Q(\my_empty_reg[7] [155]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[156] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[156]), .Q(\my_empty_reg[7] [156]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[157] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[157]), .Q(\my_empty_reg[7] [157]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[158] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[158]), .Q(\my_empty_reg[7] [158]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[159] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[159]), .Q(\my_empty_reg[7] [159]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[15] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[15]), .Q(\my_empty_reg[7] [15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[160] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[160]), .Q(\my_empty_reg[7] [160]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[161] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[161]), .Q(\my_empty_reg[7] [161]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[162] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[162]), .Q(\my_empty_reg[7] [162]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[163] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[163]), .Q(\my_empty_reg[7] [163]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[164] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[164]), .Q(\my_empty_reg[7] [164]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[165] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[165]), .Q(\my_empty_reg[7] [165]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[166] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[166]), .Q(\my_empty_reg[7] [166]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[167] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[167]), .Q(\my_empty_reg[7] [167]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[168] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[168]), .Q(\my_empty_reg[7] [168]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[169] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[169]), .Q(\my_empty_reg[7] [169]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[16] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[16]), .Q(\my_empty_reg[7] [16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[170] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[170]), .Q(\my_empty_reg[7] [170]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[171] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[171]), .Q(\my_empty_reg[7] [171]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[172] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[172]), .Q(\my_empty_reg[7] [172]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[173] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[173]), .Q(\my_empty_reg[7] [173]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[174] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[174]), .Q(\my_empty_reg[7] [174]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[175] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[175]), .Q(\my_empty_reg[7] [175]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[176] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[176]), .Q(\my_empty_reg[7] [176]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[177] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[177]), .Q(\my_empty_reg[7] [177]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[178] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[178]), .Q(\my_empty_reg[7] [178]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[179] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[179]), .Q(\my_empty_reg[7] [179]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[17] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[17]), .Q(\my_empty_reg[7] [17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[180] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[180]), .Q(\my_empty_reg[7] [180]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[181] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[181]), .Q(\my_empty_reg[7] [181]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[182] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[182]), .Q(\my_empty_reg[7] [182]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[183] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[183]), .Q(\my_empty_reg[7] [183]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[184] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[184]), .Q(\my_empty_reg[7] [184]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[185] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[185]), .Q(\my_empty_reg[7] [185]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[186] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[186]), .Q(\my_empty_reg[7] [186]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[187] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[187]), .Q(\my_empty_reg[7] [187]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[188] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[188]), .Q(\my_empty_reg[7] [188]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[189] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[189]), .Q(\my_empty_reg[7] [189]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[18] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[18]), .Q(\my_empty_reg[7] [18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[190] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[190]), .Q(\my_empty_reg[7] [190]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[191] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[191]), .Q(\my_empty_reg[7] [191]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[192] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[192]), .Q(\my_empty_reg[7] [192]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[193] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[193]), .Q(\my_empty_reg[7] [193]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[194] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[194]), .Q(\my_empty_reg[7] [194]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[195] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[195]), .Q(\my_empty_reg[7] [195]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[196] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[196]), .Q(\my_empty_reg[7] [196]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[197] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[197]), .Q(\my_empty_reg[7] [197]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[198] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[198]), .Q(\my_empty_reg[7] [198]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[199] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[199]), .Q(\my_empty_reg[7] [199]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[19] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[19]), .Q(\my_empty_reg[7] [19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[1] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[1]), .Q(\my_empty_reg[7] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[200] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[200]), .Q(\my_empty_reg[7] [200]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[201] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[201]), .Q(\my_empty_reg[7] [201]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[202] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[202]), .Q(\my_empty_reg[7] [202]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[203] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[203]), .Q(\my_empty_reg[7] [203]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[204] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[204]), .Q(\my_empty_reg[7] [204]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[205] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[205]), .Q(\my_empty_reg[7] [205]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[206] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[206]), .Q(\my_empty_reg[7] [206]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[207] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[207]), .Q(\my_empty_reg[7] [207]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[208] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[208]), .Q(\my_empty_reg[7] [208]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[209] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[209]), .Q(\my_empty_reg[7] [209]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[20] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[20]), .Q(\my_empty_reg[7] [20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[210] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[210]), .Q(\my_empty_reg[7] [210]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[211] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[211]), .Q(\my_empty_reg[7] [211]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[212] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[212]), .Q(\my_empty_reg[7] [212]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[213] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[213]), .Q(\my_empty_reg[7] [213]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[214] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[214]), .Q(\my_empty_reg[7] [214]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[215] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[215]), .Q(\my_empty_reg[7] [215]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[216] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[216]), .Q(\my_empty_reg[7] [216]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[217] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[217]), .Q(\my_empty_reg[7] [217]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[218] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[218]), .Q(\my_empty_reg[7] [218]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[219] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[219]), .Q(\my_empty_reg[7] [219]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[21] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[21]), .Q(\my_empty_reg[7] [21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[220] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[220]), .Q(\my_empty_reg[7] [220]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[221] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[221]), .Q(\my_empty_reg[7] [221]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[222] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[222]), .Q(\my_empty_reg[7] [222]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[223] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[223]), .Q(\my_empty_reg[7] [223]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[224] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[224]), .Q(\my_empty_reg[7] [224]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[225] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[225]), .Q(\my_empty_reg[7] [225]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[226] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[226]), .Q(\my_empty_reg[7] [226]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[227] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[227]), .Q(\my_empty_reg[7] [227]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[228] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[228]), .Q(\my_empty_reg[7] [228]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[229] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[229]), .Q(\my_empty_reg[7] [229]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[22] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[22]), .Q(\my_empty_reg[7] [22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[230] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[230]), .Q(\my_empty_reg[7] [230]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[231] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[231]), .Q(\my_empty_reg[7] [231]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[232] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[232]), .Q(\my_empty_reg[7] [232]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[233] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[233]), .Q(\my_empty_reg[7] [233]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[234] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[234]), .Q(\my_empty_reg[7] [234]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[235] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[235]), .Q(\my_empty_reg[7] [235]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[236] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[236]), .Q(\my_empty_reg[7] [236]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[237] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[237]), .Q(\my_empty_reg[7] [237]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[238] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[238]), .Q(\my_empty_reg[7] [238]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[239] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[239]), .Q(\my_empty_reg[7] [239]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[23] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[23]), .Q(\my_empty_reg[7] [23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[240] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[240]), .Q(\my_empty_reg[7] [240]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[241] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[241]), .Q(\my_empty_reg[7] [241]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[242] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[242]), .Q(\my_empty_reg[7] [242]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[243] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[243]), .Q(\my_empty_reg[7] [243]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[244] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[244]), .Q(\my_empty_reg[7] [244]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[245] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[245]), .Q(\my_empty_reg[7] [245]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[246] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[246]), .Q(\my_empty_reg[7] [246]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[247] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[247]), .Q(\my_empty_reg[7] [247]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[248] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[248]), .Q(\my_empty_reg[7] [248]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[249] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[249]), .Q(\my_empty_reg[7] [249]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[24] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[24]), .Q(\my_empty_reg[7] [24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[250] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[250]), .Q(\my_empty_reg[7] [250]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[251] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[251]), .Q(\my_empty_reg[7] [251]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[252] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[252]), .Q(\my_empty_reg[7] [252]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[253] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[253]), .Q(\my_empty_reg[7] [253]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[254] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[254]), .Q(\my_empty_reg[7] [254]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[255] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[255]), .Q(\my_empty_reg[7] [255]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[256] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[256]), .Q(\my_empty_reg[7] [256]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[257] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[257]), .Q(\my_empty_reg[7] [257]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[258] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[258]), .Q(\my_empty_reg[7] [258]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[259] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[259]), .Q(\my_empty_reg[7] [259]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[25] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[25]), .Q(\my_empty_reg[7] [25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[260] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[260]), .Q(\my_empty_reg[7] [260]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[261] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[261]), .Q(\my_empty_reg[7] [261]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[262] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[262]), .Q(\my_empty_reg[7] [262]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[263] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[263]), .Q(\my_empty_reg[7] [263]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[264] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[264]), .Q(\my_empty_reg[7] [264]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[265] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[265]), .Q(\my_empty_reg[7] [265]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[266] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[266]), .Q(\my_empty_reg[7] [266]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[267] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[267]), .Q(\my_empty_reg[7] [267]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[268] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[268]), .Q(\my_empty_reg[7] [268]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[269] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[269]), .Q(\my_empty_reg[7] [269]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[26] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[26]), .Q(\my_empty_reg[7] [26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[270] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[270]), .Q(\my_empty_reg[7] [270]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[271] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[271]), .Q(\my_empty_reg[7] [271]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[272] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[272]), .Q(\my_empty_reg[7] [272]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[273] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[273]), .Q(\my_empty_reg[7] [273]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[274] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[274]), .Q(\my_empty_reg[7] [274]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[275] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[275]), .Q(\my_empty_reg[7] [275]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[276] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[276]), .Q(\my_empty_reg[7] [276]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[277] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[277]), .Q(\my_empty_reg[7] [277]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[278] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[278]), .Q(\my_empty_reg[7] [278]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[279] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[279]), .Q(\my_empty_reg[7] [279]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[27] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[27]), .Q(\my_empty_reg[7] [27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[280] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[280]), .Q(\my_empty_reg[7] [280]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[281] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[281]), .Q(\my_empty_reg[7] [281]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[282] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[282]), .Q(\my_empty_reg[7] [282]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[283] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[283]), .Q(\my_empty_reg[7] [283]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[284] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[284]), .Q(\my_empty_reg[7] [284]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[285] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[285]), .Q(\my_empty_reg[7] [285]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[286] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[286]), .Q(\my_empty_reg[7] [286]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[287] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[287]), .Q(\my_empty_reg[7] [287]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[28] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[28]), .Q(\my_empty_reg[7] [28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[29] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[29]), .Q(\my_empty_reg[7] [29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[2] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[2]), .Q(\my_empty_reg[7] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[30] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[30]), .Q(\my_empty_reg[7] [30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[31] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[31]), .Q(\my_empty_reg[7] [31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[32] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[32]), .Q(\my_empty_reg[7] [32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[33] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[33]), .Q(\my_empty_reg[7] [33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[34] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[34]), .Q(\my_empty_reg[7] [34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[35] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[35]), .Q(\my_empty_reg[7] [35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[36] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[36]), .Q(\my_empty_reg[7] [36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[37] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[37]), .Q(\my_empty_reg[7] [37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[38] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[38]), .Q(\my_empty_reg[7] [38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[39] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[39]), .Q(\my_empty_reg[7] [39]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[3] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[3]), .Q(\my_empty_reg[7] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[40] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[40]), .Q(\my_empty_reg[7] [40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[41] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[41]), .Q(\my_empty_reg[7] [41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[42] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[42]), .Q(\my_empty_reg[7] [42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[43] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[43]), .Q(\my_empty_reg[7] [43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[44] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[44]), .Q(\my_empty_reg[7] [44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[45] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[45]), .Q(\my_empty_reg[7] [45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[46] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[46]), .Q(\my_empty_reg[7] [46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[47] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[47]), .Q(\my_empty_reg[7] [47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[48] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[48]), .Q(\my_empty_reg[7] [48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[49] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[49]), .Q(\my_empty_reg[7] [49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[4] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[4]), .Q(\my_empty_reg[7] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[50] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[50]), .Q(\my_empty_reg[7] [50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[51] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[51]), .Q(\my_empty_reg[7] [51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[52] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[52]), .Q(\my_empty_reg[7] [52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[53] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[53]), .Q(\my_empty_reg[7] [53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[54] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[54]), .Q(\my_empty_reg[7] [54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[55] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[55]), .Q(\my_empty_reg[7] [55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[56] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[56]), .Q(\my_empty_reg[7] [56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[57] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[57]), .Q(\my_empty_reg[7] [57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[58] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[58]), .Q(\my_empty_reg[7] [58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[59] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[59]), .Q(\my_empty_reg[7] [59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[5] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[5]), .Q(\my_empty_reg[7] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[60] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[60]), .Q(\my_empty_reg[7] [60]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[61] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[61]), .Q(\my_empty_reg[7] [61]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[62] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[62]), .Q(\my_empty_reg[7] [62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[63] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[63]), .Q(\my_empty_reg[7] [63]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[64] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[64]), .Q(\my_empty_reg[7] [64]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[65] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[65]), .Q(\my_empty_reg[7] [65]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[66] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[66]), .Q(\my_empty_reg[7] [66]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[67] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[67]), .Q(\my_empty_reg[7] [67]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[68] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[68]), .Q(\my_empty_reg[7] [68]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[69] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[69]), .Q(\my_empty_reg[7] [69]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[6] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[6]), .Q(\my_empty_reg[7] [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[70] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[70]), .Q(\my_empty_reg[7] [70]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[71] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[71]), .Q(\my_empty_reg[7] [71]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[72] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[72]), .Q(\my_empty_reg[7] [72]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[73] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[73]), .Q(\my_empty_reg[7] [73]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[74] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[74]), .Q(\my_empty_reg[7] [74]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[75] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[75]), .Q(\my_empty_reg[7] [75]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[76] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[76]), .Q(\my_empty_reg[7] [76]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[77] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[77]), .Q(\my_empty_reg[7] [77]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[78] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[78]), .Q(\my_empty_reg[7] [78]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[79] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[79]), .Q(\my_empty_reg[7] [79]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[7] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[7]), .Q(\my_empty_reg[7] [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[80] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[80]), .Q(\my_empty_reg[7] [80]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[81] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[81]), .Q(\my_empty_reg[7] [81]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[82] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[82]), .Q(\my_empty_reg[7] [82]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[83] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[83]), .Q(\my_empty_reg[7] [83]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[84] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[84]), .Q(\my_empty_reg[7] [84]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[85] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[85]), .Q(\my_empty_reg[7] [85]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[86] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[86]), .Q(\my_empty_reg[7] [86]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[87] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[87]), .Q(\my_empty_reg[7] [87]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[88] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[88]), .Q(\my_empty_reg[7] [88]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[89] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[89]), .Q(\my_empty_reg[7] [89]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[8] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[8]), .Q(\my_empty_reg[7] [8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[90] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[90]), .Q(\my_empty_reg[7] [90]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[91] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[91]), .Q(\my_empty_reg[7] [91]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[92] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[92]), .Q(\my_empty_reg[7] [92]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[93] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[93]), .Q(\my_empty_reg[7] [93]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[94] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[94]), .Q(\my_empty_reg[7] [94]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[95] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[95]), .Q(\my_empty_reg[7] [95]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[96] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[96]), .Q(\my_empty_reg[7] [96]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[97] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[97]), .Q(\my_empty_reg[7] [97]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[98] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[98]), .Q(\my_empty_reg[7] [98]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[99] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[99]), .Q(\my_empty_reg[7] [99]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_buffer.wr_buf_out_data_reg[9] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[9]), .Q(\my_empty_reg[7] [9]), .R(1'b0)); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[0].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[5:4]), .DIB(wr_buf_in_data[3:2]), .DIC(wr_buf_in_data[1:0]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[5:4]), .DOB(wr_buf_out_data_w[3:2]), .DOC(wr_buf_out_data_w[1:0]), .DOD(\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT6 #( .INIT(64'h4040404040444444)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_1 (.I0(reset_reg), .I1(ram_init_done_r), .I2(p_0_in), .I3(p_0_in__0_0), .I4(p_4_in), .I5(\occupied_counter.occ_cnt_reg_n_0_[15] ), .O(wdf_rdy_ns)); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_10 (.I0(wr_data_pntr[1]), .I1(wb_wr_data_addr_r[2]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[2])); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_11 (.I0(wr_data_pntr[0]), .I1(wb_wr_data_addr_r[1]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[1])); LUT5 #( .INIT(32'h02020F00)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_12 (.I0(app_wdf_rdy_r_copy3), .I1(app_wdf_end_r1), .I2(reset_reg), .I3(wb_wr_data_addr0_r), .I4(app_wdf_wren_r1), .O(wb_wr_data_addr0_ns)); (* SOFT_HLUTNM = "soft_lutpair1479" *) LUT3 #( .INIT(8'h80)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_13 (.I0(app_wdf_wren_r1), .I1(app_wdf_end_r1), .I2(app_wdf_rdy_r_copy1), .O(p_0_in__0_0)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_2 (.I0(wready_reg_rep__1[5]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[5]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[5]), .O(wr_buf_in_data[5])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_3 (.I0(wready_reg_rep__1[4]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[4]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[4]), .O(wr_buf_in_data[4])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_4 (.I0(wready_reg_rep__1[3]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[3]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[3]), .O(wr_buf_in_data[3])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_5 (.I0(wready_reg_rep__1[2]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[2]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[2]), .O(wr_buf_in_data[2])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_6 (.I0(wready_reg_rep__1[1]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[1]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[1]), .O(wr_buf_in_data[1])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_7 (.I0(wready_reg_rep__1[0]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[0]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[0]), .O(wr_buf_in_data[0])); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_8 (.I0(wr_data_pntr[3]), .I1(wb_wr_data_addr_r[4]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[4])); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_9 (.I0(wr_data_pntr[2]), .I1(wb_wr_data_addr_r[3]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[3])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[10].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[65:64]), .DIB(wr_buf_in_data[63:62]), .DIC(wr_buf_in_data[61:60]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[65:64]), .DOB(wr_buf_out_data_w[63:62]), .DOC(wr_buf_out_data_w[61:60]), .DOD(\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_1 (.I0(wready_reg_rep__1[65]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[65]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[65]), .O(wr_buf_in_data[65])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_2 (.I0(wready_reg_rep__1[64]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[64]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[64]), .O(wr_buf_in_data[64])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_3 (.I0(wready_reg_rep__1[63]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[63]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[63]), .O(wr_buf_in_data[63])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_4 (.I0(wready_reg_rep__1[62]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[62]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[62]), .O(wr_buf_in_data[62])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_5 (.I0(wready_reg_rep__1[61]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[61]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[61]), .O(wr_buf_in_data[61])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_6 (.I0(wready_reg_rep__1[60]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[60]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[60]), .O(wr_buf_in_data[60])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[11].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[71:70]), .DIB(wr_buf_in_data[69:68]), .DIC(wr_buf_in_data[67:66]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[71:70]), .DOB(wr_buf_out_data_w[69:68]), .DOC(wr_buf_out_data_w[67:66]), .DOD(\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_1 (.I0(wready_reg_rep__1[71]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[71]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[71]), .O(wr_buf_in_data[71])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_2 (.I0(wready_reg_rep__1[70]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[70]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[70]), .O(wr_buf_in_data[70])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_3 (.I0(wready_reg_rep__1[69]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[69]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[69]), .O(wr_buf_in_data[69])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_4 (.I0(wready_reg_rep__1[68]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[68]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[68]), .O(wr_buf_in_data[68])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_5 (.I0(wready_reg_rep__1[67]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[67]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[67]), .O(wr_buf_in_data[67])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_6 (.I0(wready_reg_rep__1[66]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[66]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[66]), .O(wr_buf_in_data[66])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[12].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[77:76]), .DIB(wr_buf_in_data[75:74]), .DIC(wr_buf_in_data[73:72]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[77:76]), .DOB(wr_buf_out_data_w[75:74]), .DOC(wr_buf_out_data_w[73:72]), .DOD(\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_1 (.I0(wready_reg_rep__1[77]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[77]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[77]), .O(wr_buf_in_data[77])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_2 (.I0(wready_reg_rep__1[76]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[76]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[76]), .O(wr_buf_in_data[76])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_3 (.I0(wready_reg_rep__1[75]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[75]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[75]), .O(wr_buf_in_data[75])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_4 (.I0(wready_reg_rep__1[74]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[74]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[74]), .O(wr_buf_in_data[74])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_5 (.I0(wready_reg_rep__1[73]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[73]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[73]), .O(wr_buf_in_data[73])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_6 (.I0(wready_reg_rep__1[72]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[72]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[72]), .O(wr_buf_in_data[72])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[13].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[83:82]), .DIB(wr_buf_in_data[81:80]), .DIC(wr_buf_in_data[79:78]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[83:82]), .DOB(wr_buf_out_data_w[81:80]), .DOC(wr_buf_out_data_w[79:78]), .DOD(\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_1 (.I0(wready_reg_rep__1[83]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[83]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[83]), .O(wr_buf_in_data[83])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_2 (.I0(wready_reg_rep__1[82]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[82]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[82]), .O(wr_buf_in_data[82])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_3 (.I0(wready_reg_rep__1[81]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[81]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[81]), .O(wr_buf_in_data[81])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_4 (.I0(wready_reg_rep__1[80]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[80]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[80]), .O(wr_buf_in_data[80])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_5 (.I0(wready_reg_rep__1[79]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[79]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[79]), .O(wr_buf_in_data[79])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_6 (.I0(wready_reg_rep__1[78]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[78]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[78]), .O(wr_buf_in_data[78])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[14].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[89:88]), .DIB(wr_buf_in_data[87:86]), .DIC(wr_buf_in_data[85:84]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[89:88]), .DOB(wr_buf_out_data_w[87:86]), .DOC(wr_buf_out_data_w[85:84]), .DOD(\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_1 (.I0(wready_reg_rep__1[89]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[89]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[89]), .O(wr_buf_in_data[89])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_2 (.I0(wready_reg_rep__1[88]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[88]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[88]), .O(wr_buf_in_data[88])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_3 (.I0(wready_reg_rep__1[87]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[87]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[87]), .O(wr_buf_in_data[87])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_4 (.I0(wready_reg_rep__1[86]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[86]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[86]), .O(wr_buf_in_data[86])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_5 (.I0(wready_reg_rep__1[85]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[85]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[85]), .O(wr_buf_in_data[85])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_6 (.I0(wready_reg_rep__1[84]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[84]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[84]), .O(wr_buf_in_data[84])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[15].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[95:94]), .DIB(wr_buf_in_data[93:92]), .DIC(wr_buf_in_data[91:90]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[95:94]), .DOB(wr_buf_out_data_w[93:92]), .DOC(wr_buf_out_data_w[91:90]), .DOD(\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_1 (.I0(wready_reg_rep__1[95]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[95]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[95]), .O(wr_buf_in_data[95])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_2 (.I0(wready_reg_rep__1[94]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[94]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[94]), .O(wr_buf_in_data[94])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_3 (.I0(wready_reg_rep__1[93]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[93]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[93]), .O(wr_buf_in_data[93])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_4 (.I0(wready_reg_rep__1[92]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[92]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[92]), .O(wr_buf_in_data[92])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_5 (.I0(wready_reg_rep__1[91]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[91]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[91]), .O(wr_buf_in_data[91])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_6 (.I0(wready_reg_rep__1[90]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[90]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[90]), .O(wr_buf_in_data[90])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[16].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[101:100]), .DIB(wr_buf_in_data[99:98]), .DIC(wr_buf_in_data[97:96]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[101:100]), .DOB(wr_buf_out_data_w[99:98]), .DOC(wr_buf_out_data_w[97:96]), .DOD(\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_1 (.I0(wready_reg_rep__1[101]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[101]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[101]), .O(wr_buf_in_data[101])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_2 (.I0(wready_reg_rep__1[100]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[100]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[100]), .O(wr_buf_in_data[100])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_3 (.I0(wready_reg_rep__1[99]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[99]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[99]), .O(wr_buf_in_data[99])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_4 (.I0(wready_reg_rep__1[98]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[98]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[98]), .O(wr_buf_in_data[98])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_5 (.I0(wready_reg_rep__1[97]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[97]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[97]), .O(wr_buf_in_data[97])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_6 (.I0(wready_reg_rep__1[96]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[96]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[96]), .O(wr_buf_in_data[96])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[17].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[107:106]), .DIB(wr_buf_in_data[105:104]), .DIC(wr_buf_in_data[103:102]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[107:106]), .DOB(wr_buf_out_data_w[105:104]), .DOC(wr_buf_out_data_w[103:102]), .DOD(\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_1 (.I0(wready_reg_rep__1[107]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[107]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[107]), .O(wr_buf_in_data[107])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_2 (.I0(wready_reg_rep__1[106]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[106]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[106]), .O(wr_buf_in_data[106])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_3 (.I0(wready_reg_rep__1[105]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[105]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[105]), .O(wr_buf_in_data[105])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_4 (.I0(wready_reg_rep__1[104]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[104]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[104]), .O(wr_buf_in_data[104])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_5 (.I0(wready_reg_rep__1[103]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[103]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[103]), .O(wr_buf_in_data[103])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_6 (.I0(wready_reg_rep__1[102]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[102]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[102]), .O(wr_buf_in_data[102])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[18].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[113:112]), .DIB(wr_buf_in_data[111:110]), .DIC(wr_buf_in_data[109:108]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[113:112]), .DOB(wr_buf_out_data_w[111:110]), .DOC(wr_buf_out_data_w[109:108]), .DOD(\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_1 (.I0(wready_reg_rep__1[113]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[113]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[113]), .O(wr_buf_in_data[113])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_2 (.I0(wready_reg_rep__1[112]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[112]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[112]), .O(wr_buf_in_data[112])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_3 (.I0(wready_reg_rep__1[111]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[111]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[111]), .O(wr_buf_in_data[111])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_4 (.I0(wready_reg_rep__1[110]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[110]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[110]), .O(wr_buf_in_data[110])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_5 (.I0(wready_reg_rep__1[109]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[109]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[109]), .O(wr_buf_in_data[109])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_6 (.I0(wready_reg_rep__1[108]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[108]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[108]), .O(wr_buf_in_data[108])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[19].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[119:118]), .DIB(wr_buf_in_data[117:116]), .DIC(wr_buf_in_data[115:114]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[119:118]), .DOB(wr_buf_out_data_w[117:116]), .DOC(wr_buf_out_data_w[115:114]), .DOD(\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_1 (.I0(wready_reg_rep__1[119]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[119]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[119]), .O(wr_buf_in_data[119])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_2 (.I0(wready_reg_rep__1[118]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[118]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[118]), .O(wr_buf_in_data[118])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_3 (.I0(wready_reg_rep__1[117]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[117]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[117]), .O(wr_buf_in_data[117])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_4 (.I0(wready_reg_rep__1[116]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[116]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[116]), .O(wr_buf_in_data[116])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_5 (.I0(wready_reg_rep__1[115]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[115]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[115]), .O(wr_buf_in_data[115])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_6 (.I0(wready_reg_rep__1[114]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[114]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[114]), .O(wr_buf_in_data[114])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[1].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[11:10]), .DIB(wr_buf_in_data[9:8]), .DIC(wr_buf_in_data[7:6]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[11:10]), .DOB(wr_buf_out_data_w[9:8]), .DOC(wr_buf_out_data_w[7:6]), .DOD(\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_1 (.I0(wready_reg_rep__1[11]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[11]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[11]), .O(wr_buf_in_data[11])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_2 (.I0(wready_reg_rep__1[10]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[10]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[10]), .O(wr_buf_in_data[10])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_3 (.I0(wready_reg_rep__1[9]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[9]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[9]), .O(wr_buf_in_data[9])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_4 (.I0(wready_reg_rep__1[8]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[8]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[8]), .O(wr_buf_in_data[8])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_5 (.I0(wready_reg_rep__1[7]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[7]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[7]), .O(wr_buf_in_data[7])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_6 (.I0(wready_reg_rep__1[6]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[6]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[6]), .O(wr_buf_in_data[6])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[20].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[125:124]), .DIB(wr_buf_in_data[123:122]), .DIC(wr_buf_in_data[121:120]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[125:124]), .DOB(wr_buf_out_data_w[123:122]), .DOC(wr_buf_out_data_w[121:120]), .DOD(\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_1 (.I0(wready_reg_rep__1[125]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[125]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[125]), .O(wr_buf_in_data[125])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_2 (.I0(wready_reg_rep__1[124]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[124]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[124]), .O(wr_buf_in_data[124])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_3 (.I0(wready_reg_rep__1[123]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[123]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[123]), .O(wr_buf_in_data[123])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_4 (.I0(wready_reg_rep__1[122]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[122]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[122]), .O(wr_buf_in_data[122])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_5 (.I0(wready_reg_rep__1[121]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[121]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[121]), .O(wr_buf_in_data[121])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_6 (.I0(wready_reg_rep__1[120]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[120]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[120]), .O(wr_buf_in_data[120])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[21].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[131:130]), .DIB(wr_buf_in_data[129:128]), .DIC(wr_buf_in_data[127:126]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[131:130]), .DOB(wr_buf_out_data_w[129:128]), .DOC(wr_buf_out_data_w[127:126]), .DOD(\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_1 (.I0(wready_reg_rep__1[131]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[131]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[131]), .O(wr_buf_in_data[131])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_2 (.I0(wready_reg_rep__1[130]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[130]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[130]), .O(wr_buf_in_data[130])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_3 (.I0(wready_reg_rep__1[129]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[129]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[129]), .O(wr_buf_in_data[129])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_4 (.I0(wready_reg_rep__1[128]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[128]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[128]), .O(wr_buf_in_data[128])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_5 (.I0(wready_reg_rep__1[127]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[127]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[127]), .O(wr_buf_in_data[127])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_6 (.I0(wready_reg_rep__1[126]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[126]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[126]), .O(wr_buf_in_data[126])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[22].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[137:136]), .DIB(wr_buf_in_data[135:134]), .DIC(wr_buf_in_data[133:132]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[137:136]), .DOB(wr_buf_out_data_w[135:134]), .DOC(wr_buf_out_data_w[133:132]), .DOD(\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_1 (.I0(wready_reg_rep__1[137]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[137]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[137]), .O(wr_buf_in_data[137])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_2 (.I0(wready_reg_rep__1[136]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[136]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[136]), .O(wr_buf_in_data[136])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_3 (.I0(wready_reg_rep__1[135]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[135]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[135]), .O(wr_buf_in_data[135])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_4 (.I0(wready_reg_rep__1[134]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[134]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[134]), .O(wr_buf_in_data[134])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_5 (.I0(wready_reg_rep__1[133]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[133]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[133]), .O(wr_buf_in_data[133])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_6 (.I0(wready_reg_rep__1[132]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[132]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[132]), .O(wr_buf_in_data[132])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[23].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[143:142]), .DIB(wr_buf_in_data[141:140]), .DIC(wr_buf_in_data[139:138]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[143:142]), .DOB(wr_buf_out_data_w[141:140]), .DOC(wr_buf_out_data_w[139:138]), .DOD(\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_1 (.I0(wready_reg_rep__1[143]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[143]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[143]), .O(wr_buf_in_data[143])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_2 (.I0(wready_reg_rep__1[142]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[142]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[142]), .O(wr_buf_in_data[142])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_3 (.I0(wready_reg_rep__1[141]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[141]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[141]), .O(wr_buf_in_data[141])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_4 (.I0(wready_reg_rep__1[140]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[140]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[140]), .O(wr_buf_in_data[140])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_5 (.I0(wready_reg_rep__1[139]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[139]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[139]), .O(wr_buf_in_data[139])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_6 (.I0(wready_reg_rep__1[138]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[138]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[138]), .O(wr_buf_in_data[138])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[24].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[149:148]), .DIB(wr_buf_in_data[147:146]), .DIC(wr_buf_in_data[145:144]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[149:148]), .DOB(wr_buf_out_data_w[147:146]), .DOC(wr_buf_out_data_w[145:144]), .DOD(\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_1 (.I0(wready_reg_rep__1[149]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[149]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[149]), .O(wr_buf_in_data[149])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_2 (.I0(wready_reg_rep__1[148]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[148]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[148]), .O(wr_buf_in_data[148])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_3 (.I0(wready_reg_rep__1[147]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[147]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[147]), .O(wr_buf_in_data[147])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_4 (.I0(wready_reg_rep__1[146]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[146]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[146]), .O(wr_buf_in_data[146])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_5 (.I0(wready_reg_rep__1[145]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[145]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[145]), .O(wr_buf_in_data[145])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_6 (.I0(wready_reg_rep__1[144]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[144]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[144]), .O(wr_buf_in_data[144])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[25].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[155:154]), .DIB(wr_buf_in_data[153:152]), .DIC(wr_buf_in_data[151:150]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[155:154]), .DOB(wr_buf_out_data_w[153:152]), .DOC(wr_buf_out_data_w[151:150]), .DOD(\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_1 (.I0(wready_reg_rep__1[155]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[155]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[155]), .O(wr_buf_in_data[155])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_2 (.I0(wready_reg_rep__1[154]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[154]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[154]), .O(wr_buf_in_data[154])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_3 (.I0(wready_reg_rep__1[153]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[153]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[153]), .O(wr_buf_in_data[153])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_4 (.I0(wready_reg_rep__1[152]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[152]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[152]), .O(wr_buf_in_data[152])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_5 (.I0(wready_reg_rep__1[151]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[151]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[151]), .O(wr_buf_in_data[151])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_6 (.I0(wready_reg_rep__1[150]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[150]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[150]), .O(wr_buf_in_data[150])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[26].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[161:160]), .DIB(wr_buf_in_data[159:158]), .DIC(wr_buf_in_data[157:156]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[161:160]), .DOB(wr_buf_out_data_w[159:158]), .DOC(wr_buf_out_data_w[157:156]), .DOD(\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_1 (.I0(wready_reg_rep__1[161]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[161]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[161]), .O(wr_buf_in_data[161])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_2 (.I0(wready_reg_rep__1[160]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[160]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[160]), .O(wr_buf_in_data[160])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_3 (.I0(wready_reg_rep__1[159]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[159]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[159]), .O(wr_buf_in_data[159])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_4 (.I0(wready_reg_rep__1[158]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[158]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[158]), .O(wr_buf_in_data[158])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_5 (.I0(wready_reg_rep__1[157]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[157]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[157]), .O(wr_buf_in_data[157])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_6 (.I0(wready_reg_rep__1[156]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[156]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[156]), .O(wr_buf_in_data[156])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[27].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[167:166]), .DIB(wr_buf_in_data[165:164]), .DIC(wr_buf_in_data[163:162]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[167:166]), .DOB(wr_buf_out_data_w[165:164]), .DOC(wr_buf_out_data_w[163:162]), .DOD(\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_1 (.I0(wready_reg_rep__1[167]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[167]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[167]), .O(wr_buf_in_data[167])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_2 (.I0(wready_reg_rep__1[166]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[166]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[166]), .O(wr_buf_in_data[166])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_3 (.I0(wready_reg_rep__1[165]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[165]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[165]), .O(wr_buf_in_data[165])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_4 (.I0(wready_reg_rep__1[164]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[164]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[164]), .O(wr_buf_in_data[164])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_5 (.I0(wready_reg_rep__1[163]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[163]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[163]), .O(wr_buf_in_data[163])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_6 (.I0(wready_reg_rep__1[162]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[162]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[162]), .O(wr_buf_in_data[162])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[28].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[173:172]), .DIB(wr_buf_in_data[171:170]), .DIC(wr_buf_in_data[169:168]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[173:172]), .DOB(wr_buf_out_data_w[171:170]), .DOC(wr_buf_out_data_w[169:168]), .DOD(\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_1 (.I0(wready_reg_rep__1[173]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[173]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[173]), .O(wr_buf_in_data[173])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_2 (.I0(wready_reg_rep__1[172]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[172]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[172]), .O(wr_buf_in_data[172])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_3 (.I0(wready_reg_rep__1[171]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[171]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[171]), .O(wr_buf_in_data[171])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_4 (.I0(wready_reg_rep__1[170]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[170]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[170]), .O(wr_buf_in_data[170])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_5 (.I0(wready_reg_rep__1[169]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[169]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[169]), .O(wr_buf_in_data[169])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_6 (.I0(wready_reg_rep__1[168]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[168]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[168]), .O(wr_buf_in_data[168])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[29].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[179:178]), .DIB(wr_buf_in_data[177:176]), .DIC(wr_buf_in_data[175:174]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[179:178]), .DOB(wr_buf_out_data_w[177:176]), .DOC(wr_buf_out_data_w[175:174]), .DOD(\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_1 (.I0(wready_reg_rep__1[179]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[179]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[179]), .O(wr_buf_in_data[179])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_2 (.I0(wready_reg_rep__1[178]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[178]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[178]), .O(wr_buf_in_data[178])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_3 (.I0(wready_reg_rep__1[177]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[177]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[177]), .O(wr_buf_in_data[177])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_4 (.I0(wready_reg_rep__1[176]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[176]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[176]), .O(wr_buf_in_data[176])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_5 (.I0(wready_reg_rep__1[175]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[175]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[175]), .O(wr_buf_in_data[175])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_6 (.I0(wready_reg_rep__1[174]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[174]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[174]), .O(wr_buf_in_data[174])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[2].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[17:16]), .DIB(wr_buf_in_data[15:14]), .DIC(wr_buf_in_data[13:12]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[17:16]), .DOB(wr_buf_out_data_w[15:14]), .DOC(wr_buf_out_data_w[13:12]), .DOD(\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_1 (.I0(wready_reg_rep__1[17]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[17]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[17]), .O(wr_buf_in_data[17])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_2 (.I0(wready_reg_rep__1[16]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[16]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[16]), .O(wr_buf_in_data[16])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_3 (.I0(wready_reg_rep__1[15]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[15]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[15]), .O(wr_buf_in_data[15])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_4 (.I0(wready_reg_rep__1[14]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[14]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[14]), .O(wr_buf_in_data[14])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_5 (.I0(wready_reg_rep__1[13]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[13]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[13]), .O(wr_buf_in_data[13])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_6 (.I0(wready_reg_rep__1[12]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[12]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[12]), .O(wr_buf_in_data[12])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[30].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[185:184]), .DIB(wr_buf_in_data[183:182]), .DIC(wr_buf_in_data[181:180]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[185:184]), .DOB(wr_buf_out_data_w[183:182]), .DOC(wr_buf_out_data_w[181:180]), .DOD(\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_1 (.I0(wready_reg_rep__1[185]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[185]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[185]), .O(wr_buf_in_data[185])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_2 (.I0(wready_reg_rep__1[184]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[184]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[184]), .O(wr_buf_in_data[184])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_3 (.I0(wready_reg_rep__1[183]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[183]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[183]), .O(wr_buf_in_data[183])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_4 (.I0(wready_reg_rep__1[182]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[182]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[182]), .O(wr_buf_in_data[182])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_5 (.I0(wready_reg_rep__1[181]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[181]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[181]), .O(wr_buf_in_data[181])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_6 (.I0(wready_reg_rep__1[180]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[180]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[180]), .O(wr_buf_in_data[180])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[31].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[191:190]), .DIB(wr_buf_in_data[189:188]), .DIC(wr_buf_in_data[187:186]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[191:190]), .DOB(wr_buf_out_data_w[189:188]), .DOC(wr_buf_out_data_w[187:186]), .DOD(\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_1 (.I0(wready_reg_rep__1[191]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[191]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[191]), .O(wr_buf_in_data[191])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_2 (.I0(wready_reg_rep__1[190]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[190]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[190]), .O(wr_buf_in_data[190])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_3 (.I0(wready_reg_rep__1[189]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[189]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[189]), .O(wr_buf_in_data[189])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_4 (.I0(wready_reg_rep__1[188]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[188]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[188]), .O(wr_buf_in_data[188])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_5 (.I0(wready_reg_rep__1[187]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[187]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[187]), .O(wr_buf_in_data[187])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_6 (.I0(wready_reg_rep__1[186]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[186]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[186]), .O(wr_buf_in_data[186])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[32].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[197:196]), .DIB(wr_buf_in_data[195:194]), .DIC(wr_buf_in_data[193:192]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[197:196]), .DOB(wr_buf_out_data_w[195:194]), .DOC(wr_buf_out_data_w[193:192]), .DOD(\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_1 (.I0(wready_reg_rep__1[197]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[197]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[197]), .O(wr_buf_in_data[197])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_2 (.I0(wready_reg_rep__1[196]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[196]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[196]), .O(wr_buf_in_data[196])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_3 (.I0(wready_reg_rep__1[195]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[195]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[195]), .O(wr_buf_in_data[195])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_4 (.I0(wready_reg_rep__1[194]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[194]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[194]), .O(wr_buf_in_data[194])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_5 (.I0(wready_reg_rep__1[193]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[193]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[193]), .O(wr_buf_in_data[193])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_6 (.I0(wready_reg_rep__1[192]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[192]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[192]), .O(wr_buf_in_data[192])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[33].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[203:202]), .DIB(wr_buf_in_data[201:200]), .DIC(wr_buf_in_data[199:198]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[203:202]), .DOB(wr_buf_out_data_w[201:200]), .DOC(wr_buf_out_data_w[199:198]), .DOD(\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_1 (.I0(wready_reg_rep__1[203]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[203]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[203]), .O(wr_buf_in_data[203])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_2 (.I0(wready_reg_rep__1[202]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[202]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[202]), .O(wr_buf_in_data[202])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_3 (.I0(wready_reg_rep__1[201]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[201]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[201]), .O(wr_buf_in_data[201])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_4 (.I0(wready_reg_rep__1[200]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[200]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[200]), .O(wr_buf_in_data[200])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_5 (.I0(wready_reg_rep__1[199]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[199]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[199]), .O(wr_buf_in_data[199])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_6 (.I0(wready_reg_rep__1[198]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[198]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[198]), .O(wr_buf_in_data[198])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[34].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[209:208]), .DIB(wr_buf_in_data[207:206]), .DIC(wr_buf_in_data[205:204]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[209:208]), .DOB(wr_buf_out_data_w[207:206]), .DOC(wr_buf_out_data_w[205:204]), .DOD(\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_1 (.I0(wready_reg_rep__1[209]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[209]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[209]), .O(wr_buf_in_data[209])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_2 (.I0(wready_reg_rep__1[208]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[208]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[208]), .O(wr_buf_in_data[208])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_3 (.I0(wready_reg_rep__1[207]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[207]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[207]), .O(wr_buf_in_data[207])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_4 (.I0(wready_reg_rep__1[206]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[206]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[206]), .O(wr_buf_in_data[206])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_5 (.I0(wready_reg_rep__1[205]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[205]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[205]), .O(wr_buf_in_data[205])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_6 (.I0(wready_reg_rep__1[204]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[204]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[204]), .O(wr_buf_in_data[204])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[35].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[215:214]), .DIB(wr_buf_in_data[213:212]), .DIC(wr_buf_in_data[211:210]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[215:214]), .DOB(wr_buf_out_data_w[213:212]), .DOC(wr_buf_out_data_w[211:210]), .DOD(\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_1 (.I0(wready_reg_rep__1[215]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[215]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[215]), .O(wr_buf_in_data[215])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_2 (.I0(wready_reg_rep__1[214]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[214]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[214]), .O(wr_buf_in_data[214])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_3 (.I0(wready_reg_rep__1[213]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[213]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[213]), .O(wr_buf_in_data[213])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_4 (.I0(wready_reg_rep__1[212]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[212]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[212]), .O(wr_buf_in_data[212])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_5 (.I0(wready_reg_rep__1[211]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[211]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[211]), .O(wr_buf_in_data[211])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_6 (.I0(wready_reg_rep__1[210]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[210]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[210]), .O(wr_buf_in_data[210])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[36].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[221:220]), .DIB(wr_buf_in_data[219:218]), .DIC(wr_buf_in_data[217:216]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[221:220]), .DOB(wr_buf_out_data_w[219:218]), .DOC(wr_buf_out_data_w[217:216]), .DOD(\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_1 (.I0(wready_reg_rep__1[221]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[221]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[221]), .O(wr_buf_in_data[221])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_2 (.I0(wready_reg_rep__1[220]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[220]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[220]), .O(wr_buf_in_data[220])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_3 (.I0(wready_reg_rep__1[219]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[219]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[219]), .O(wr_buf_in_data[219])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_4 (.I0(wready_reg_rep__1[218]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[218]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[218]), .O(wr_buf_in_data[218])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_5 (.I0(wready_reg_rep__1[217]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[217]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[217]), .O(wr_buf_in_data[217])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_6 (.I0(wready_reg_rep__1[216]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[216]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[216]), .O(wr_buf_in_data[216])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[37].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[227:226]), .DIB(wr_buf_in_data[225:224]), .DIC(wr_buf_in_data[223:222]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[227:226]), .DOB(wr_buf_out_data_w[225:224]), .DOC(wr_buf_out_data_w[223:222]), .DOD(\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_1 (.I0(wready_reg_rep__1[227]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[227]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[227]), .O(wr_buf_in_data[227])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_2 (.I0(wready_reg_rep__1[226]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[226]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[226]), .O(wr_buf_in_data[226])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_3 (.I0(wready_reg_rep__1[225]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[225]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[225]), .O(wr_buf_in_data[225])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_4 (.I0(wready_reg_rep__1[224]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[224]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[224]), .O(wr_buf_in_data[224])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_5 (.I0(wready_reg_rep__1[223]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[223]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[223]), .O(wr_buf_in_data[223])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_6 (.I0(wready_reg_rep__1[222]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[222]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[222]), .O(wr_buf_in_data[222])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[38].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[233:232]), .DIB(wr_buf_in_data[231:230]), .DIC(wr_buf_in_data[229:228]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[233:232]), .DOB(wr_buf_out_data_w[231:230]), .DOC(wr_buf_out_data_w[229:228]), .DOD(\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_1 (.I0(wready_reg_rep__1[233]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[233]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[233]), .O(wr_buf_in_data[233])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_2 (.I0(wready_reg_rep__1[232]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[232]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[232]), .O(wr_buf_in_data[232])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_3 (.I0(wready_reg_rep__1[231]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[231]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[231]), .O(wr_buf_in_data[231])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_4 (.I0(wready_reg_rep__1[230]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[230]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[230]), .O(wr_buf_in_data[230])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_5 (.I0(wready_reg_rep__1[229]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[229]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[229]), .O(wr_buf_in_data[229])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_6 (.I0(wready_reg_rep__1[228]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[228]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[228]), .O(wr_buf_in_data[228])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[39].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[239:238]), .DIB(wr_buf_in_data[237:236]), .DIC(wr_buf_in_data[235:234]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[239:238]), .DOB(wr_buf_out_data_w[237:236]), .DOC(wr_buf_out_data_w[235:234]), .DOD(\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_1 (.I0(wready_reg_rep__1[239]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[239]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[239]), .O(wr_buf_in_data[239])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_2 (.I0(wready_reg_rep__1[238]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[238]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[238]), .O(wr_buf_in_data[238])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_3 (.I0(wready_reg_rep__1[237]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[237]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[237]), .O(wr_buf_in_data[237])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_4 (.I0(wready_reg_rep__1[236]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[236]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[236]), .O(wr_buf_in_data[236])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_5 (.I0(wready_reg_rep__1[235]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[235]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[235]), .O(wr_buf_in_data[235])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_6 (.I0(wready_reg_rep__1[234]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[234]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[234]), .O(wr_buf_in_data[234])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[3].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[23:22]), .DIB(wr_buf_in_data[21:20]), .DIC(wr_buf_in_data[19:18]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[23:22]), .DOB(wr_buf_out_data_w[21:20]), .DOC(wr_buf_out_data_w[19:18]), .DOD(\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_1 (.I0(wready_reg_rep__1[23]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[23]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[23]), .O(wr_buf_in_data[23])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_2 (.I0(wready_reg_rep__1[22]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[22]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[22]), .O(wr_buf_in_data[22])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_3 (.I0(wready_reg_rep__1[21]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[21]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[21]), .O(wr_buf_in_data[21])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_4 (.I0(wready_reg_rep__1[20]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[20]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[20]), .O(wr_buf_in_data[20])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_5 (.I0(wready_reg_rep__1[19]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[19]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[19]), .O(wr_buf_in_data[19])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_6 (.I0(wready_reg_rep__1[18]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[18]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[18]), .O(wr_buf_in_data[18])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[40].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[245:244]), .DIB(wr_buf_in_data[243:242]), .DIC(wr_buf_in_data[241:240]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[245:244]), .DOB(wr_buf_out_data_w[243:242]), .DOC(wr_buf_out_data_w[241:240]), .DOD(\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_1 (.I0(wready_reg_rep__1[245]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[245]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[245]), .O(wr_buf_in_data[245])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_2 (.I0(wready_reg_rep__1[244]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[244]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[244]), .O(wr_buf_in_data[244])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_3 (.I0(wready_reg_rep__1[243]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[243]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[243]), .O(wr_buf_in_data[243])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_4 (.I0(wready_reg_rep__1[242]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[242]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[242]), .O(wr_buf_in_data[242])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_5 (.I0(wready_reg_rep__1[241]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[241]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[241]), .O(wr_buf_in_data[241])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_6 (.I0(wready_reg_rep__1[240]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[240]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[240]), .O(wr_buf_in_data[240])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[41].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[251:250]), .DIB(wr_buf_in_data[249:248]), .DIC(wr_buf_in_data[247:246]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[251:250]), .DOB(wr_buf_out_data_w[249:248]), .DOC(wr_buf_out_data_w[247:246]), .DOD(\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_1 (.I0(wready_reg_rep__1[251]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[251]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[251]), .O(wr_buf_in_data[251])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_2 (.I0(wready_reg_rep__1[250]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[250]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[250]), .O(wr_buf_in_data[250])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_3 (.I0(wready_reg_rep__1[249]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[249]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[249]), .O(wr_buf_in_data[249])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_4 (.I0(wready_reg_rep__1[248]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[248]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[248]), .O(wr_buf_in_data[248])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_5 (.I0(wready_reg_rep__1[247]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[247]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[247]), .O(wr_buf_in_data[247])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_6 (.I0(wready_reg_rep__1[246]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[246]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[246]), .O(wr_buf_in_data[246])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[42].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[257:256]), .DIB(wr_buf_in_data[255:254]), .DIC(wr_buf_in_data[253:252]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[257:256]), .DOB(wr_buf_out_data_w[255:254]), .DOC(wr_buf_out_data_w[253:252]), .DOD(\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_1 (.I0(D[1]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[1]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[1]), .O(wr_buf_in_data[257])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_2 (.I0(D[0]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[0]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[0]), .O(wr_buf_in_data[256])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_3 (.I0(wready_reg_rep__1[255]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[255]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[255]), .O(wr_buf_in_data[255])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_4 (.I0(wready_reg_rep__1[254]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[254]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[254]), .O(wr_buf_in_data[254])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_5 (.I0(wready_reg_rep__1[253]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[253]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[253]), .O(wr_buf_in_data[253])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_6 (.I0(wready_reg_rep__1[252]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[252]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[252]), .O(wr_buf_in_data[252])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[43].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[263:262]), .DIB(wr_buf_in_data[261:260]), .DIC(wr_buf_in_data[259:258]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[263:262]), .DOB(wr_buf_out_data_w[261:260]), .DOC(wr_buf_out_data_w[259:258]), .DOD(\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_1 (.I0(D[7]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[7]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[7]), .O(wr_buf_in_data[263])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_2 (.I0(D[6]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[6]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[6]), .O(wr_buf_in_data[262])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_3 (.I0(D[5]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[5]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[5]), .O(wr_buf_in_data[261])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_4 (.I0(D[4]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[4]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[4]), .O(wr_buf_in_data[260])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_5 (.I0(D[3]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[3]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[3]), .O(wr_buf_in_data[259])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_6 (.I0(D[2]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[2]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[2]), .O(wr_buf_in_data[258])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[44].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[269:268]), .DIB(wr_buf_in_data[267:266]), .DIC(wr_buf_in_data[265:264]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[269:268]), .DOB(wr_buf_out_data_w[267:266]), .DOC(wr_buf_out_data_w[265:264]), .DOD(\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_1 (.I0(D[13]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[13]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[13]), .O(wr_buf_in_data[269])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_2 (.I0(D[12]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[12]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[12]), .O(wr_buf_in_data[268])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_3 (.I0(D[11]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[11]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[11]), .O(wr_buf_in_data[267])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_4 (.I0(D[10]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[10]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[10]), .O(wr_buf_in_data[266])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_5 (.I0(D[9]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[9]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[9]), .O(wr_buf_in_data[265])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_6 (.I0(D[8]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[8]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[8]), .O(wr_buf_in_data[264])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[45].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[275:274]), .DIB(wr_buf_in_data[273:272]), .DIC(wr_buf_in_data[271:270]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[275:274]), .DOB(wr_buf_out_data_w[273:272]), .DOC(wr_buf_out_data_w[271:270]), .DOD(\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_1 (.I0(D[19]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[19]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[19]), .O(wr_buf_in_data[275])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_2 (.I0(D[18]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[18]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[18]), .O(wr_buf_in_data[274])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_3 (.I0(D[17]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[17]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[17]), .O(wr_buf_in_data[273])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_4 (.I0(D[16]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[16]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[16]), .O(wr_buf_in_data[272])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_5 (.I0(D[15]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[15]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[15]), .O(wr_buf_in_data[271])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_6 (.I0(D[14]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[14]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[14]), .O(wr_buf_in_data[270])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[46].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[281:280]), .DIB(wr_buf_in_data[279:278]), .DIC(wr_buf_in_data[277:276]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[281:280]), .DOB(wr_buf_out_data_w[279:278]), .DOC(wr_buf_out_data_w[277:276]), .DOD(\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_1 (.I0(D[25]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[25]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[25]), .O(wr_buf_in_data[281])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_2 (.I0(D[24]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[24]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[24]), .O(wr_buf_in_data[280])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_3 (.I0(D[23]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[23]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[23]), .O(wr_buf_in_data[279])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_4 (.I0(D[22]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[22]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[22]), .O(wr_buf_in_data[278])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_5 (.I0(D[21]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[21]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[21]), .O(wr_buf_in_data[277])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_6 (.I0(D[20]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[20]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[20]), .O(wr_buf_in_data[276])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[47].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[287:286]), .DIB(wr_buf_in_data[285:284]), .DIC(wr_buf_in_data[283:282]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[287:286]), .DOB(wr_buf_out_data_w[285:284]), .DOC(wr_buf_out_data_w[283:282]), .DOD(\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_1 (.I0(D[31]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[31]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[31]), .O(wr_buf_in_data[287])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_2 (.I0(D[30]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[30]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[30]), .O(wr_buf_in_data[286])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_3 (.I0(D[29]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[29]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[29]), .O(wr_buf_in_data[285])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_4 (.I0(D[28]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[28]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[28]), .O(wr_buf_in_data[284])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_5 (.I0(D[27]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[27]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[27]), .O(wr_buf_in_data[283])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_6 (.I0(D[26]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[26]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[26]), .O(wr_buf_in_data[282])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[4].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[29:28]), .DIB(wr_buf_in_data[27:26]), .DIC(wr_buf_in_data[25:24]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[29:28]), .DOB(wr_buf_out_data_w[27:26]), .DOC(wr_buf_out_data_w[25:24]), .DOD(\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_1 (.I0(wready_reg_rep__1[29]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[29]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[29]), .O(wr_buf_in_data[29])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_2 (.I0(wready_reg_rep__1[28]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[28]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[28]), .O(wr_buf_in_data[28])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_3 (.I0(wready_reg_rep__1[27]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[27]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[27]), .O(wr_buf_in_data[27])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_4 (.I0(wready_reg_rep__1[26]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[26]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[26]), .O(wr_buf_in_data[26])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_5 (.I0(wready_reg_rep__1[25]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[25]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[25]), .O(wr_buf_in_data[25])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_6 (.I0(wready_reg_rep__1[24]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[24]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[24]), .O(wr_buf_in_data[24])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[5].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[35:34]), .DIB(wr_buf_in_data[33:32]), .DIC(wr_buf_in_data[31:30]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[35:34]), .DOB(wr_buf_out_data_w[33:32]), .DOC(wr_buf_out_data_w[31:30]), .DOD(\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_1 (.I0(wready_reg_rep__1[35]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[35]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[35]), .O(wr_buf_in_data[35])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_2 (.I0(wready_reg_rep__1[34]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[34]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[34]), .O(wr_buf_in_data[34])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_3 (.I0(wready_reg_rep__1[33]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[33]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[33]), .O(wr_buf_in_data[33])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_4 (.I0(wready_reg_rep__1[32]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[32]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[32]), .O(wr_buf_in_data[32])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_5 (.I0(wready_reg_rep__1[31]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[31]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[31]), .O(wr_buf_in_data[31])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_6 (.I0(wready_reg_rep__1[30]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[30]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[30]), .O(wr_buf_in_data[30])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[6].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[41:40]), .DIB(wr_buf_in_data[39:38]), .DIC(wr_buf_in_data[37:36]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[41:40]), .DOB(wr_buf_out_data_w[39:38]), .DOC(wr_buf_out_data_w[37:36]), .DOD(\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_1 (.I0(wready_reg_rep__1[41]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[41]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[41]), .O(wr_buf_in_data[41])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_2 (.I0(wready_reg_rep__1[40]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[40]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[40]), .O(wr_buf_in_data[40])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_3 (.I0(wready_reg_rep__1[39]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[39]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[39]), .O(wr_buf_in_data[39])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_4 (.I0(wready_reg_rep__1[38]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[38]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[38]), .O(wr_buf_in_data[38])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_5 (.I0(wready_reg_rep__1[37]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[37]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[37]), .O(wr_buf_in_data[37])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_6 (.I0(wready_reg_rep__1[36]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[36]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[36]), .O(wr_buf_in_data[36])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[7].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[47:46]), .DIB(wr_buf_in_data[45:44]), .DIC(wr_buf_in_data[43:42]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[47:46]), .DOB(wr_buf_out_data_w[45:44]), .DOC(wr_buf_out_data_w[43:42]), .DOD(\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_1 (.I0(wready_reg_rep__1[47]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[47]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[47]), .O(wr_buf_in_data[47])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_2 (.I0(wready_reg_rep__1[46]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[46]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[46]), .O(wr_buf_in_data[46])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_3 (.I0(wready_reg_rep__1[45]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[45]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[45]), .O(wr_buf_in_data[45])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_4 (.I0(wready_reg_rep__1[44]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[44]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[44]), .O(wr_buf_in_data[44])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_5 (.I0(wready_reg_rep__1[43]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[43]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[43]), .O(wr_buf_in_data[43])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_6 (.I0(wready_reg_rep__1[42]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[42]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[42]), .O(wr_buf_in_data[42])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[8].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[53:52]), .DIB(wr_buf_in_data[51:50]), .DIC(wr_buf_in_data[49:48]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[53:52]), .DOB(wr_buf_out_data_w[51:50]), .DOC(wr_buf_out_data_w[49:48]), .DOD(\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_1 (.I0(wready_reg_rep__1[53]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[53]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[53]), .O(wr_buf_in_data[53])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_2 (.I0(wready_reg_rep__1[52]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[52]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[52]), .O(wr_buf_in_data[52])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_3 (.I0(wready_reg_rep__1[51]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[51]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[51]), .O(wr_buf_in_data[51])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_4 (.I0(wready_reg_rep__1[50]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[50]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[50]), .O(wr_buf_in_data[50])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_5 (.I0(wready_reg_rep__1[49]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[49]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[49]), .O(wr_buf_in_data[49])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_6 (.I0(wready_reg_rep__1[48]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[48]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[48]), .O(wr_buf_in_data[48])); (* box_type = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[9].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[59:58]), .DIB(wr_buf_in_data[57:56]), .DIC(wr_buf_in_data[55:54]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[59:58]), .DOB(wr_buf_out_data_w[57:56]), .DOC(wr_buf_out_data_w[55:54]), .DOD(\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_1 (.I0(wready_reg_rep__1[59]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[59]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[59]), .O(wr_buf_in_data[59])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_2 (.I0(wready_reg_rep__1[58]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[58]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[58]), .O(wr_buf_in_data[58])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_3 (.I0(wready_reg_rep__1[57]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[57]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[57]), .O(wr_buf_in_data[57])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_4 (.I0(wready_reg_rep__1[56]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[56]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[56]), .O(wr_buf_in_data[56])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_5 (.I0(wready_reg_rep__1[55]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[55]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[55]), .O(wr_buf_in_data[55])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_6 (.I0(wready_reg_rep__1[54]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[54]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[54]), .O(wr_buf_in_data[54])); FDRE #( .INIT(1'b0)) \write_data_control.wb_wr_data_addr0_r_reg (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr0_ns), .Q(wb_wr_data_addr0_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_data_control.wb_wr_data_addr_r_reg[1] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[1]), .Q(wb_wr_data_addr_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_data_control.wb_wr_data_addr_r_reg[2] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[2]), .Q(wb_wr_data_addr_r[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_data_control.wb_wr_data_addr_r_reg[3] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[3]), .Q(wb_wr_data_addr_r[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \write_data_control.wb_wr_data_addr_r_reg[4] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[4]), .Q(wb_wr_data_addr_r[4]), .R(1'b0)); LUT1 #( .INIT(2'h1)) \write_data_control.wr_data_indx_r[0]_i_1 (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]), .O(p_0_in__0__0[0])); LUT2 #( .INIT(4'h6)) \write_data_control.wr_data_indx_r[1]_i_1 (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]), .I1(\write_data_control.wr_data_indx_r_reg__0 [1]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair1485" *) LUT3 #( .INIT(8'h78)) \write_data_control.wr_data_indx_r[2]_i_1 (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]), .I1(\write_data_control.wr_data_indx_r_reg__0 [1]), .I2(\write_data_control.wr_data_indx_r_reg__0 [2]), .O(p_0_in__0__0[2])); LUT6 #( .INIT(64'hF000FFFF10001000)) \write_data_control.wr_data_indx_r[3]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[15] ), .I1(p_4_in), .I2(p_0_in__0_0), .I3(\rd_buf_indx.ram_init_done_r_lcl_reg ), .I4(app_wdf_rdy_r_copy1), .I5(p_0_in), .O(wr_data_addr_le)); (* SOFT_HLUTNM = "soft_lutpair1485" *) LUT4 #( .INIT(16'h7F80)) \write_data_control.wr_data_indx_r[3]_i_2 (.I0(\write_data_control.wr_data_indx_r_reg__0 [2]), .I1(\write_data_control.wr_data_indx_r_reg__0 [1]), .I2(\write_data_control.wr_data_indx_r_reg__0 [0]), .I3(\write_data_control.wr_data_indx_r_reg__0 [3]), .O(p_0_in__0__0[3])); FDSE #( .INIT(1'b1)) \write_data_control.wr_data_indx_r_reg[0] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[0]), .Q(\write_data_control.wr_data_indx_r_reg__0 [0]), .S(reset_reg)); FDRE #( .INIT(1'b0)) \write_data_control.wr_data_indx_r_reg[1] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[1]), .Q(\write_data_control.wr_data_indx_r_reg__0 [1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \write_data_control.wr_data_indx_r_reg[2] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[2]), .Q(\write_data_control.wr_data_indx_r_reg__0 [2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \write_data_control.wr_data_indx_r_reg[3] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[3]), .Q(\write_data_control.wr_data_indx_r_reg__0 [3]), .R(reset_reg)); endmodule module dvi_pll (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire dvi_bit_clock; wire pixel_clock; wire sysclk; dvi_pll_dvi_pll_clk_wiz inst (.dvi_bit_clock(dvi_bit_clock), .pixel_clock(pixel_clock), .sysclk(sysclk)); endmodule (* ORIG_REF_NAME = "dvi_pll_clk_wiz" *) module dvi_pll_dvi_pll_clk_wiz (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire clkfbout_buf_dvi_pll; wire clkfbout_dvi_pll; wire dvi_bit_clock; wire dvi_bit_clock_dvi_pll; wire pixel_clock; wire pixel_clock_dvi_pll; wire sysclk; wire sysclk_dvi_pll; wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED; wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* box_type = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_dvi_pll), .O(clkfbout_buf_dvi_pll)); (* box_type = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_dvi_pll)); (* box_type = "PRIMITIVE" *) BUFG clkout1_buf (.I(pixel_clock_dvi_pll), .O(pixel_clock)); (* box_type = "PRIMITIVE" *) BUFG clkout2_buf (.I(dvi_bit_clock_dvi_pll), .O(dvi_bit_clock)); (* box_type = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(37), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(10), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(5), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_adv_inst (.CLKFBIN(clkfbout_buf_dvi_pll), .CLKFBOUT(clkfbout_dvi_pll), .CLKIN1(sysclk_dvi_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(pixel_clock_dvi_pll), .CLKOUT1(dvi_bit_clock_dvi_pll), .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED), .PWRDWN(1'b0), .RST(1'b0)); endmodule module dvi_tx (hdmi_d0, hdmi_d1, hdmi_d2, hdmi_clk, dvi_bit_clock, pixel_clock, SR, dvi_den, reset_n_IBUF, D); output [1:0]hdmi_d0; output [1:0]hdmi_d1; output [1:0]hdmi_d2; output [1:0]hdmi_clk; input dvi_bit_clock; input pixel_clock; input [0:0]SR; input dvi_den; input reset_n_IBUF; input [1:0]D; wire [1:0]D; wire RST; wire [0:0]SR; wire den_lat; wire dvi_bit_clock; wire dvi_den; wire \gen_lane[0].lane_enc_n_1 ; wire [1:0]hdmi_clk; wire [1:0]hdmi_d0; wire [1:0]hdmi_d1; wire [1:0]hdmi_d2; wire pixel_clock; wire reset_n_IBUF; wire [9:0]tmds_enc_0; wire [8:0]tmds_enc_10; wire [2:0]tmds_enc_20; dvi_tx_clk_drv clock_phy (.hdmi_clk(hdmi_clk), .pixel_clock(pixel_clock)); dvi_tx_tmds_enc \gen_lane[0].lane_enc (.D(D), .Q({tmds_enc_0[9:8],tmds_enc_0[2],tmds_enc_0[0]}), .SR(SR), .\cnt_q_reg[8]_0 (\gen_lane[0].lane_enc_n_1 ), .den_lat(den_lat), .dvi_den(dvi_den), .pixel_clock(pixel_clock), .reset_n_IBUF(reset_n_IBUF)); dvi_tx_tmds_phy \gen_lane[0].lane_phy (.Q({tmds_enc_0[9:8],tmds_enc_0[2],tmds_enc_0[0]}), .RST(RST), .SR(SR), .dvi_bit_clock(dvi_bit_clock), .hdmi_d0(hdmi_d0), .pixel_clock(pixel_clock)); dvi_tx_tmds_enc_0 \gen_lane[1].lane_enc (.SR(SR), .den_lat(den_lat), .den_lat_reg(\gen_lane[0].lane_enc_n_1 ), .pixel_clock(pixel_clock), .tmds_enc_10({tmds_enc_10[8],tmds_enc_10[2],tmds_enc_10[0]})); dvi_tx_tmds_phy_1 \gen_lane[1].lane_phy (.RST(RST), .dvi_bit_clock(dvi_bit_clock), .hdmi_d1(hdmi_d1), .pixel_clock(pixel_clock), .tmds_enc_10({tmds_enc_10[8],tmds_enc_10[2],tmds_enc_10[0]})); dvi_tx_tmds_enc_2 \gen_lane[2].lane_enc (.Q({tmds_enc_20[2],tmds_enc_20[0]}), .SR(SR), .den_lat(den_lat), .den_lat_reg(\gen_lane[0].lane_enc_n_1 ), .pixel_clock(pixel_clock)); dvi_tx_tmds_phy_3 \gen_lane[2].lane_phy (.Q({tmds_enc_20[2],tmds_enc_20[0]}), .RST(RST), .dvi_bit_clock(dvi_bit_clock), .hdmi_d2(hdmi_d2), .pixel_clock(pixel_clock), .tmds_enc_10(tmds_enc_10[8])); endmodule module dvi_tx_clk_drv (hdmi_clk, pixel_clock); output [1:0]hdmi_clk; input pixel_clock; wire [1:0]hdmi_clk; wire pixel_clock; wire tmds_clk_pre; wire NLW_clk_oddr_R_UNCONNECTED; wire NLW_clk_oddr_S_UNCONNECTED; (* CAPACITANCE = "DONT_CARE" *) (* XILINX_LEGACY_PRIM = "OBUFDS" *) (* box_type = "PRIMITIVE" *) OBUFDS #( .IOSTANDARD("DEFAULT")) clk_obuf (.I(tmds_clk_pre), .O(hdmi_clk[1]), .OB(hdmi_clk[0])); (* __SRVAL = "TRUE" *) (* box_type = "PRIMITIVE" *) ODDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) clk_oddr (.C(pixel_clock), .CE(1'b1), .D1(1'b1), .D2(1'b0), .Q(tmds_clk_pre), .R(NLW_clk_oddr_R_UNCONNECTED), .S(NLW_clk_oddr_S_UNCONNECTED)); endmodule module dvi_tx_tmds_enc (den_lat, \cnt_q_reg[8]_0 , Q, SR, dvi_den, pixel_clock, reset_n_IBUF, D); output den_lat; output \cnt_q_reg[8]_0 ; output [3:0]Q; input [0:0]SR; input dvi_den; input pixel_clock; input reset_n_IBUF; input [1:0]D; wire [1:0]D; wire [3:0]Q; wire [0:0]SR; wire [8:0]cnt_d0; wire [8:0]cnt_q; wire \cnt_q[0]_i_1__0_n_0 ; wire \cnt_q[0]_i_3_n_0 ; wire \cnt_q[0]_i_4__0_n_0 ; wire \cnt_q[0]_i_5_n_0 ; wire \cnt_q[0]_i_6_n_0 ; wire \cnt_q[1]_i_1_n_0 ; wire \cnt_q[1]_i_3_n_0 ; wire \cnt_q[1]_i_4_n_0 ; wire \cnt_q[1]_i_5_n_0 ; wire \cnt_q[1]_i_6_n_0 ; wire \cnt_q[2]_i_1_n_0 ; wire \cnt_q[3]_i_1_n_0 ; wire \cnt_q[4]_i_1_n_0 ; wire \cnt_q[4]_i_3_n_0 ; wire \cnt_q[4]_i_4_n_0 ; wire \cnt_q[4]_i_5_n_0 ; wire \cnt_q[4]_i_6_n_0 ; wire \cnt_q[5]_i_1_n_0 ; wire \cnt_q[5]_i_3_n_0 ; wire \cnt_q[5]_i_4_n_0 ; wire \cnt_q[5]_i_5_n_0 ; wire \cnt_q[5]_i_6_n_0 ; wire \cnt_q[6]_i_1_n_0 ; wire \cnt_q[7]_i_1_n_0 ; wire \cnt_q[8]_i_1_n_0 ; wire \cnt_q[8]_i_3_n_0 ; wire \cnt_q_reg[0]_i_2_n_0 ; wire \cnt_q_reg[0]_i_2_n_1 ; wire \cnt_q_reg[0]_i_2_n_2 ; wire \cnt_q_reg[0]_i_2_n_3 ; wire \cnt_q_reg[1]_i_2_n_0 ; wire \cnt_q_reg[1]_i_2_n_1 ; wire \cnt_q_reg[1]_i_2_n_2 ; wire \cnt_q_reg[1]_i_2_n_3 ; wire \cnt_q_reg[1]_i_2_n_4 ; wire \cnt_q_reg[1]_i_2_n_5 ; wire \cnt_q_reg[1]_i_2_n_6 ; wire \cnt_q_reg[1]_i_2_n_7 ; wire \cnt_q_reg[4]_i_2_n_0 ; wire \cnt_q_reg[4]_i_2_n_1 ; wire \cnt_q_reg[4]_i_2_n_2 ; wire \cnt_q_reg[4]_i_2_n_3 ; wire \cnt_q_reg[5]_i_2_n_1 ; wire \cnt_q_reg[5]_i_2_n_2 ; wire \cnt_q_reg[5]_i_2_n_3 ; wire \cnt_q_reg[5]_i_2_n_4 ; wire \cnt_q_reg[5]_i_2_n_5 ; wire \cnt_q_reg[5]_i_2_n_6 ; wire \cnt_q_reg[5]_i_2_n_7 ; wire \cnt_q_reg[8]_0 ; wire [1:0]ctrl_lat; wire den_lat; wire dvi_den; wire pixel_clock; wire q_out23_in; wire q_out2_carry_i_1_n_0; wire q_out2_carry_i_2_n_0; wire q_out2_carry_i_3_n_0; wire q_out2_carry_n_2; wire q_out2_carry_n_3; wire reset_n_IBUF; wire \tmds[0]_i_1_n_0 ; wire \tmds[2]_i_1_n_0 ; wire \tmds[8]_i_1_n_0 ; wire \tmds[9]_i_1_n_0 ; wire [3:3]\NLW_cnt_q_reg[5]_i_2_CO_UNCONNECTED ; wire [3:0]\NLW_cnt_q_reg[8]_i_2_CO_UNCONNECTED ; wire [3:1]\NLW_cnt_q_reg[8]_i_2_O_UNCONNECTED ; wire [3:3]NLW_q_out2_carry_CO_UNCONNECTED; wire [3:0]NLW_q_out2_carry_O_UNCONNECTED; LUT2 #( .INIT(4'h7)) \cnt_q[0]_i_1 (.I0(reset_n_IBUF), .I1(den_lat), .O(\cnt_q_reg[8]_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[0]_i_1__0 (.I0(cnt_q[0]), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[0]), .O(\cnt_q[0]_i_1__0_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[0]_i_3 (.I0(cnt_q[3]), .O(\cnt_q[0]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_4__0 (.I0(cnt_q[2]), .O(\cnt_q[0]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_5 (.I0(cnt_q[1]), .O(\cnt_q[0]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_6 (.I0(cnt_q[0]), .O(\cnt_q[0]_i_6_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[1]_i_1 (.I0(\cnt_q_reg[1]_i_2_n_7 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[1]), .O(\cnt_q[1]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \cnt_q[1]_i_3 (.I0(cnt_q[3]), .I1(cnt_q[4]), .O(\cnt_q[1]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[1]_i_4 (.I0(cnt_q[3]), .O(\cnt_q[1]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \cnt_q[1]_i_5 (.I0(cnt_q[1]), .I1(cnt_q[2]), .O(\cnt_q[1]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[1]_i_6 (.I0(cnt_q[1]), .O(\cnt_q[1]_i_6_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[2]_i_1 (.I0(\cnt_q_reg[1]_i_2_n_6 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[2]), .O(\cnt_q[2]_i_1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[3]_i_1 (.I0(\cnt_q_reg[1]_i_2_n_5 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[3]), .O(\cnt_q[3]_i_1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[4]_i_1 (.I0(\cnt_q_reg[1]_i_2_n_4 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[4]), .O(\cnt_q[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_3 (.I0(cnt_q[7]), .O(\cnt_q[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_4 (.I0(cnt_q[6]), .O(\cnt_q[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_5 (.I0(cnt_q[5]), .O(\cnt_q[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_6 (.I0(cnt_q[4]), .O(\cnt_q[4]_i_6_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[5]_i_1 (.I0(\cnt_q_reg[5]_i_2_n_7 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[5]), .O(\cnt_q[5]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_3 (.I0(cnt_q[8]), .O(\cnt_q[5]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_4 (.I0(cnt_q[7]), .O(\cnt_q[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_5 (.I0(cnt_q[6]), .O(\cnt_q[5]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_6 (.I0(cnt_q[5]), .O(\cnt_q[5]_i_6_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[6]_i_1 (.I0(\cnt_q_reg[5]_i_2_n_6 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[6]), .O(\cnt_q[6]_i_1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[7]_i_1 (.I0(\cnt_q_reg[5]_i_2_n_5 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[7]), .O(\cnt_q[7]_i_1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[8]_i_1 (.I0(\cnt_q_reg[5]_i_2_n_4 ), .I1(cnt_q[8]), .I2(q_out23_in), .I3(cnt_d0[8]), .O(\cnt_q[8]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[8]_i_3 (.I0(cnt_q[8]), .O(\cnt_q[8]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[0] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[0]_i_1__0_n_0 ), .Q(cnt_q[0]), .R(\cnt_q_reg[8]_0 )); CARRY4 \cnt_q_reg[0]_i_2 (.CI(1'b0), .CO({\cnt_q_reg[0]_i_2_n_0 ,\cnt_q_reg[0]_i_2_n_1 ,\cnt_q_reg[0]_i_2_n_2 ,\cnt_q_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({cnt_q[3:1],1'b0}), .O(cnt_d0[3:0]), .S({\cnt_q[0]_i_3_n_0 ,\cnt_q[0]_i_4__0_n_0 ,\cnt_q[0]_i_5_n_0 ,\cnt_q[0]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[1] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[1]_i_1_n_0 ), .Q(cnt_q[1]), .R(\cnt_q_reg[8]_0 )); CARRY4 \cnt_q_reg[1]_i_2 (.CI(1'b0), .CO({\cnt_q_reg[1]_i_2_n_0 ,\cnt_q_reg[1]_i_2_n_1 ,\cnt_q_reg[1]_i_2_n_2 ,\cnt_q_reg[1]_i_2_n_3 }), .CYINIT(1'b0), .DI({cnt_q[3],1'b0,cnt_q[1],1'b0}), .O({\cnt_q_reg[1]_i_2_n_4 ,\cnt_q_reg[1]_i_2_n_5 ,\cnt_q_reg[1]_i_2_n_6 ,\cnt_q_reg[1]_i_2_n_7 }), .S({\cnt_q[1]_i_3_n_0 ,\cnt_q[1]_i_4_n_0 ,\cnt_q[1]_i_5_n_0 ,\cnt_q[1]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[2] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[2]_i_1_n_0 ), .Q(cnt_q[2]), .R(\cnt_q_reg[8]_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[3] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[3]_i_1_n_0 ), .Q(cnt_q[3]), .R(\cnt_q_reg[8]_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[4] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[4]_i_1_n_0 ), .Q(cnt_q[4]), .R(\cnt_q_reg[8]_0 )); CARRY4 \cnt_q_reg[4]_i_2 (.CI(\cnt_q_reg[0]_i_2_n_0 ), .CO({\cnt_q_reg[4]_i_2_n_0 ,\cnt_q_reg[4]_i_2_n_1 ,\cnt_q_reg[4]_i_2_n_2 ,\cnt_q_reg[4]_i_2_n_3 }), .CYINIT(1'b0), .DI(cnt_q[7:4]), .O(cnt_d0[7:4]), .S({\cnt_q[4]_i_3_n_0 ,\cnt_q[4]_i_4_n_0 ,\cnt_q[4]_i_5_n_0 ,\cnt_q[4]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[5] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[5]_i_1_n_0 ), .Q(cnt_q[5]), .R(\cnt_q_reg[8]_0 )); CARRY4 \cnt_q_reg[5]_i_2 (.CI(\cnt_q_reg[1]_i_2_n_0 ), .CO({\NLW_cnt_q_reg[5]_i_2_CO_UNCONNECTED [3],\cnt_q_reg[5]_i_2_n_1 ,\cnt_q_reg[5]_i_2_n_2 ,\cnt_q_reg[5]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\cnt_q_reg[5]_i_2_n_4 ,\cnt_q_reg[5]_i_2_n_5 ,\cnt_q_reg[5]_i_2_n_6 ,\cnt_q_reg[5]_i_2_n_7 }), .S({\cnt_q[5]_i_3_n_0 ,\cnt_q[5]_i_4_n_0 ,\cnt_q[5]_i_5_n_0 ,\cnt_q[5]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[6] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[6]_i_1_n_0 ), .Q(cnt_q[6]), .R(\cnt_q_reg[8]_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[7] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[7]_i_1_n_0 ), .Q(cnt_q[7]), .R(\cnt_q_reg[8]_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[8] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[8]_i_1_n_0 ), .Q(cnt_q[8]), .R(\cnt_q_reg[8]_0 )); CARRY4 \cnt_q_reg[8]_i_2 (.CI(\cnt_q_reg[4]_i_2_n_0 ), .CO(\NLW_cnt_q_reg[8]_i_2_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_cnt_q_reg[8]_i_2_O_UNCONNECTED [3:1],cnt_d0[8]}), .S({1'b0,1'b0,1'b0,\cnt_q[8]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \ctrl_lat_reg[0] (.C(pixel_clock), .CE(1'b1), .D(D[0]), .Q(ctrl_lat[0]), .R(SR)); FDRE #( .INIT(1'b0)) \ctrl_lat_reg[1] (.C(pixel_clock), .CE(1'b1), .D(D[1]), .Q(ctrl_lat[1]), .R(SR)); FDRE #( .INIT(1'b0)) den_lat_reg (.C(pixel_clock), .CE(1'b1), .D(dvi_den), .Q(den_lat), .R(SR)); CARRY4 q_out2_carry (.CI(1'b0), .CO({NLW_q_out2_carry_CO_UNCONNECTED[3],q_out23_in,q_out2_carry_n_2,q_out2_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_q_out2_carry_O_UNCONNECTED[3:0]), .S({1'b0,q_out2_carry_i_1_n_0,q_out2_carry_i_2_n_0,q_out2_carry_i_3_n_0})); LUT3 #( .INIT(8'h01)) q_out2_carry_i_1 (.I0(cnt_q[6]), .I1(cnt_q[7]), .I2(cnt_q[8]), .O(q_out2_carry_i_1_n_0)); LUT3 #( .INIT(8'h01)) q_out2_carry_i_2 (.I0(cnt_q[3]), .I1(cnt_q[4]), .I2(cnt_q[5]), .O(q_out2_carry_i_2_n_0)); LUT3 #( .INIT(8'h01)) q_out2_carry_i_3 (.I0(cnt_q[2]), .I1(cnt_q[1]), .I2(cnt_q[0]), .O(q_out2_carry_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h2F20)) \tmds[0]_i_1 (.I0(cnt_q[8]), .I1(q_out23_in), .I2(den_lat), .I3(ctrl_lat[0]), .O(\tmds[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'h0C55)) \tmds[2]_i_1 (.I0(ctrl_lat[0]), .I1(cnt_q[8]), .I2(q_out23_in), .I3(den_lat), .O(\tmds[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'hB)) \tmds[8]_i_1 (.I0(den_lat), .I1(ctrl_lat[0]), .O(\tmds[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'h00F09999)) \tmds[9]_i_1 (.I0(ctrl_lat[1]), .I1(ctrl_lat[0]), .I2(cnt_q[8]), .I3(q_out23_in), .I4(den_lat), .O(\tmds[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \tmds_reg[0] (.C(pixel_clock), .CE(1'b1), .D(\tmds[0]_i_1_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \tmds_reg[2] (.C(pixel_clock), .CE(1'b1), .D(\tmds[2]_i_1_n_0 ), .Q(Q[1]), .R(SR)); FDRE #( .INIT(1'b0)) \tmds_reg[8] (.C(pixel_clock), .CE(1'b1), .D(\tmds[8]_i_1_n_0 ), .Q(Q[2]), .R(SR)); FDRE #( .INIT(1'b0)) \tmds_reg[9] (.C(pixel_clock), .CE(1'b1), .D(\tmds[9]_i_1_n_0 ), .Q(Q[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "dvi_tx_tmds_enc" *) module dvi_tx_tmds_enc_0 (tmds_enc_10, den_lat_reg, pixel_clock, SR, den_lat); output [2:0]tmds_enc_10; input den_lat_reg; input pixel_clock; input [0:0]SR; input den_lat; wire [0:0]SR; wire \cnt_q[0]_i_1__1_n_0 ; wire \cnt_q[0]_i_3__0_n_0 ; wire \cnt_q[0]_i_4__1_n_0 ; wire \cnt_q[0]_i_5__0_n_0 ; wire \cnt_q[0]_i_6__0_n_0 ; wire \cnt_q[1]_i_1__0_n_0 ; wire \cnt_q[1]_i_3_n_0 ; wire \cnt_q[1]_i_4__0_n_0 ; wire \cnt_q[1]_i_5_n_0 ; wire \cnt_q[1]_i_6__0_n_0 ; wire \cnt_q[2]_i_1__0_n_0 ; wire \cnt_q[3]_i_1__0_n_0 ; wire \cnt_q[4]_i_1__0_n_0 ; wire \cnt_q[4]_i_3__0_n_0 ; wire \cnt_q[4]_i_4__0_n_0 ; wire \cnt_q[4]_i_5__0_n_0 ; wire \cnt_q[4]_i_6__0_n_0 ; wire \cnt_q[5]_i_1__0_n_0 ; wire \cnt_q[5]_i_3__0_n_0 ; wire \cnt_q[5]_i_4__0_n_0 ; wire \cnt_q[5]_i_5__0_n_0 ; wire \cnt_q[5]_i_6__0_n_0 ; wire \cnt_q[6]_i_1__0_n_0 ; wire \cnt_q[7]_i_1__0_n_0 ; wire \cnt_q[8]_i_1__0_n_0 ; wire \cnt_q[8]_i_3__0_n_0 ; wire \cnt_q_reg[0]_i_2__0_n_0 ; wire \cnt_q_reg[0]_i_2__0_n_1 ; wire \cnt_q_reg[0]_i_2__0_n_2 ; wire \cnt_q_reg[0]_i_2__0_n_3 ; wire \cnt_q_reg[0]_i_2__0_n_4 ; wire \cnt_q_reg[0]_i_2__0_n_5 ; wire \cnt_q_reg[0]_i_2__0_n_6 ; wire \cnt_q_reg[0]_i_2__0_n_7 ; wire \cnt_q_reg[1]_i_2__0_n_0 ; wire \cnt_q_reg[1]_i_2__0_n_1 ; wire \cnt_q_reg[1]_i_2__0_n_2 ; wire \cnt_q_reg[1]_i_2__0_n_3 ; wire \cnt_q_reg[1]_i_2__0_n_4 ; wire \cnt_q_reg[1]_i_2__0_n_5 ; wire \cnt_q_reg[1]_i_2__0_n_6 ; wire \cnt_q_reg[1]_i_2__0_n_7 ; wire \cnt_q_reg[4]_i_2__0_n_0 ; wire \cnt_q_reg[4]_i_2__0_n_1 ; wire \cnt_q_reg[4]_i_2__0_n_2 ; wire \cnt_q_reg[4]_i_2__0_n_3 ; wire \cnt_q_reg[4]_i_2__0_n_4 ; wire \cnt_q_reg[4]_i_2__0_n_5 ; wire \cnt_q_reg[4]_i_2__0_n_6 ; wire \cnt_q_reg[4]_i_2__0_n_7 ; wire \cnt_q_reg[5]_i_2__0_n_1 ; wire \cnt_q_reg[5]_i_2__0_n_2 ; wire \cnt_q_reg[5]_i_2__0_n_3 ; wire \cnt_q_reg[5]_i_2__0_n_4 ; wire \cnt_q_reg[5]_i_2__0_n_5 ; wire \cnt_q_reg[5]_i_2__0_n_6 ; wire \cnt_q_reg[5]_i_2__0_n_7 ; wire \cnt_q_reg[8]_i_2__0_n_7 ; wire \cnt_q_reg_n_0_[0] ; wire \cnt_q_reg_n_0_[1] ; wire \cnt_q_reg_n_0_[2] ; wire \cnt_q_reg_n_0_[3] ; wire \cnt_q_reg_n_0_[4] ; wire \cnt_q_reg_n_0_[5] ; wire \cnt_q_reg_n_0_[6] ; wire \cnt_q_reg_n_0_[7] ; wire \cnt_q_reg_n_0_[8] ; wire den_lat; wire den_lat_reg; wire pixel_clock; wire q_out23_in; wire q_out2_carry_i_1__0_n_0; wire q_out2_carry_i_2__0_n_0; wire q_out2_carry_i_3__0_n_0; wire q_out2_carry_n_2; wire q_out2_carry_n_3; wire \tmds[0]_i_1__0_n_0 ; wire \tmds[2]_i_1__0_n_0 ; wire [2:0]tmds_enc_10; wire [3:3]\NLW_cnt_q_reg[5]_i_2__0_CO_UNCONNECTED ; wire [3:0]\NLW_cnt_q_reg[8]_i_2__0_CO_UNCONNECTED ; wire [3:1]\NLW_cnt_q_reg[8]_i_2__0_O_UNCONNECTED ; wire [3:3]NLW_q_out2_carry_CO_UNCONNECTED; wire [3:0]NLW_q_out2_carry_O_UNCONNECTED; LUT4 #( .INIT(16'hFB08)) \cnt_q[0]_i_1__1 (.I0(\cnt_q_reg_n_0_[0] ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_2__0_n_7 ), .O(\cnt_q[0]_i_1__1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[0]_i_3__0 (.I0(\cnt_q_reg_n_0_[3] ), .O(\cnt_q[0]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_4__1 (.I0(\cnt_q_reg_n_0_[2] ), .O(\cnt_q[0]_i_4__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_5__0 (.I0(\cnt_q_reg_n_0_[1] ), .O(\cnt_q[0]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_6__0 (.I0(\cnt_q_reg_n_0_[0] ), .O(\cnt_q[0]_i_6__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[1]_i_1__0 (.I0(\cnt_q_reg[1]_i_2__0_n_7 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_2__0_n_6 ), .O(\cnt_q[1]_i_1__0_n_0 )); LUT2 #( .INIT(4'h6)) \cnt_q[1]_i_3 (.I0(\cnt_q_reg_n_0_[3] ), .I1(\cnt_q_reg_n_0_[4] ), .O(\cnt_q[1]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[1]_i_4__0 (.I0(\cnt_q_reg_n_0_[3] ), .O(\cnt_q[1]_i_4__0_n_0 )); LUT2 #( .INIT(4'h6)) \cnt_q[1]_i_5 (.I0(\cnt_q_reg_n_0_[1] ), .I1(\cnt_q_reg_n_0_[2] ), .O(\cnt_q[1]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[1]_i_6__0 (.I0(\cnt_q_reg_n_0_[1] ), .O(\cnt_q[1]_i_6__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[2]_i_1__0 (.I0(\cnt_q_reg[1]_i_2__0_n_6 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_2__0_n_5 ), .O(\cnt_q[2]_i_1__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[3]_i_1__0 (.I0(\cnt_q_reg[1]_i_2__0_n_5 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_2__0_n_4 ), .O(\cnt_q[3]_i_1__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[4]_i_1__0 (.I0(\cnt_q_reg[1]_i_2__0_n_4 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__0_n_7 ), .O(\cnt_q[4]_i_1__0_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_3__0 (.I0(\cnt_q_reg_n_0_[7] ), .O(\cnt_q[4]_i_3__0_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_4__0 (.I0(\cnt_q_reg_n_0_[6] ), .O(\cnt_q[4]_i_4__0_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_5__0 (.I0(\cnt_q_reg_n_0_[5] ), .O(\cnt_q[4]_i_5__0_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_6__0 (.I0(\cnt_q_reg_n_0_[4] ), .O(\cnt_q[4]_i_6__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[5]_i_1__0 (.I0(\cnt_q_reg[5]_i_2__0_n_7 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__0_n_6 ), .O(\cnt_q[5]_i_1__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_3__0 (.I0(\cnt_q_reg_n_0_[8] ), .O(\cnt_q[5]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_4__0 (.I0(\cnt_q_reg_n_0_[7] ), .O(\cnt_q[5]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_5__0 (.I0(\cnt_q_reg_n_0_[6] ), .O(\cnt_q[5]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_6__0 (.I0(\cnt_q_reg_n_0_[5] ), .O(\cnt_q[5]_i_6__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[6]_i_1__0 (.I0(\cnt_q_reg[5]_i_2__0_n_6 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__0_n_5 ), .O(\cnt_q[6]_i_1__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[7]_i_1__0 (.I0(\cnt_q_reg[5]_i_2__0_n_5 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__0_n_4 ), .O(\cnt_q[7]_i_1__0_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[8]_i_1__0 (.I0(\cnt_q_reg[5]_i_2__0_n_4 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[8]_i_2__0_n_7 ), .O(\cnt_q[8]_i_1__0_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[8]_i_3__0 (.I0(\cnt_q_reg_n_0_[8] ), .O(\cnt_q[8]_i_3__0_n_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[0] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[0]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[0] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[0]_i_2__0 (.CI(1'b0), .CO({\cnt_q_reg[0]_i_2__0_n_0 ,\cnt_q_reg[0]_i_2__0_n_1 ,\cnt_q_reg[0]_i_2__0_n_2 ,\cnt_q_reg[0]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({\cnt_q_reg_n_0_[3] ,\cnt_q_reg_n_0_[2] ,\cnt_q_reg_n_0_[1] ,1'b0}), .O({\cnt_q_reg[0]_i_2__0_n_4 ,\cnt_q_reg[0]_i_2__0_n_5 ,\cnt_q_reg[0]_i_2__0_n_6 ,\cnt_q_reg[0]_i_2__0_n_7 }), .S({\cnt_q[0]_i_3__0_n_0 ,\cnt_q[0]_i_4__1_n_0 ,\cnt_q[0]_i_5__0_n_0 ,\cnt_q[0]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[1] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[1]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[1] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[1]_i_2__0 (.CI(1'b0), .CO({\cnt_q_reg[1]_i_2__0_n_0 ,\cnt_q_reg[1]_i_2__0_n_1 ,\cnt_q_reg[1]_i_2__0_n_2 ,\cnt_q_reg[1]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({\cnt_q_reg_n_0_[3] ,1'b0,\cnt_q_reg_n_0_[1] ,1'b0}), .O({\cnt_q_reg[1]_i_2__0_n_4 ,\cnt_q_reg[1]_i_2__0_n_5 ,\cnt_q_reg[1]_i_2__0_n_6 ,\cnt_q_reg[1]_i_2__0_n_7 }), .S({\cnt_q[1]_i_3_n_0 ,\cnt_q[1]_i_4__0_n_0 ,\cnt_q[1]_i_5_n_0 ,\cnt_q[1]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[2] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[2]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[2] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[3] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[3]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[3] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[4] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[4]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[4] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[4]_i_2__0 (.CI(\cnt_q_reg[0]_i_2__0_n_0 ), .CO({\cnt_q_reg[4]_i_2__0_n_0 ,\cnt_q_reg[4]_i_2__0_n_1 ,\cnt_q_reg[4]_i_2__0_n_2 ,\cnt_q_reg[4]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({\cnt_q_reg_n_0_[7] ,\cnt_q_reg_n_0_[6] ,\cnt_q_reg_n_0_[5] ,\cnt_q_reg_n_0_[4] }), .O({\cnt_q_reg[4]_i_2__0_n_4 ,\cnt_q_reg[4]_i_2__0_n_5 ,\cnt_q_reg[4]_i_2__0_n_6 ,\cnt_q_reg[4]_i_2__0_n_7 }), .S({\cnt_q[4]_i_3__0_n_0 ,\cnt_q[4]_i_4__0_n_0 ,\cnt_q[4]_i_5__0_n_0 ,\cnt_q[4]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[5] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[5]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[5] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[5]_i_2__0 (.CI(\cnt_q_reg[1]_i_2__0_n_0 ), .CO({\NLW_cnt_q_reg[5]_i_2__0_CO_UNCONNECTED [3],\cnt_q_reg[5]_i_2__0_n_1 ,\cnt_q_reg[5]_i_2__0_n_2 ,\cnt_q_reg[5]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\cnt_q_reg[5]_i_2__0_n_4 ,\cnt_q_reg[5]_i_2__0_n_5 ,\cnt_q_reg[5]_i_2__0_n_6 ,\cnt_q_reg[5]_i_2__0_n_7 }), .S({\cnt_q[5]_i_3__0_n_0 ,\cnt_q[5]_i_4__0_n_0 ,\cnt_q[5]_i_5__0_n_0 ,\cnt_q[5]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[6] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[6]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[6] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[7] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[7]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[7] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[8] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[8]_i_1__0_n_0 ), .Q(\cnt_q_reg_n_0_[8] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[8]_i_2__0 (.CI(\cnt_q_reg[4]_i_2__0_n_0 ), .CO(\NLW_cnt_q_reg[8]_i_2__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_cnt_q_reg[8]_i_2__0_O_UNCONNECTED [3:1],\cnt_q_reg[8]_i_2__0_n_7 }), .S({1'b0,1'b0,1'b0,\cnt_q[8]_i_3__0_n_0 })); CARRY4 q_out2_carry (.CI(1'b0), .CO({NLW_q_out2_carry_CO_UNCONNECTED[3],q_out23_in,q_out2_carry_n_2,q_out2_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_q_out2_carry_O_UNCONNECTED[3:0]), .S({1'b0,q_out2_carry_i_1__0_n_0,q_out2_carry_i_2__0_n_0,q_out2_carry_i_3__0_n_0})); LUT3 #( .INIT(8'h01)) q_out2_carry_i_1__0 (.I0(\cnt_q_reg_n_0_[6] ), .I1(\cnt_q_reg_n_0_[7] ), .I2(\cnt_q_reg_n_0_[8] ), .O(q_out2_carry_i_1__0_n_0)); LUT3 #( .INIT(8'h01)) q_out2_carry_i_2__0 (.I0(\cnt_q_reg_n_0_[3] ), .I1(\cnt_q_reg_n_0_[4] ), .I2(\cnt_q_reg_n_0_[5] ), .O(q_out2_carry_i_2__0_n_0)); LUT3 #( .INIT(8'h01)) q_out2_carry_i_3__0 (.I0(\cnt_q_reg_n_0_[2] ), .I1(\cnt_q_reg_n_0_[1] ), .I2(\cnt_q_reg_n_0_[0] ), .O(q_out2_carry_i_3__0_n_0)); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'h40)) \tmds[0]_i_1__0 (.I0(q_out23_in), .I1(\cnt_q_reg_n_0_[8] ), .I2(den_lat), .O(\tmds[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'h4F)) \tmds[2]_i_1__0 (.I0(q_out23_in), .I1(\cnt_q_reg_n_0_[8] ), .I2(den_lat), .O(\tmds[2]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \tmds_reg[0] (.C(pixel_clock), .CE(1'b1), .D(\tmds[0]_i_1__0_n_0 ), .Q(tmds_enc_10[0]), .R(SR)); FDRE #( .INIT(1'b0)) \tmds_reg[2] (.C(pixel_clock), .CE(1'b1), .D(\tmds[2]_i_1__0_n_0 ), .Q(tmds_enc_10[1]), .R(SR)); FDRE #( .INIT(1'b0)) \tmds_reg[8] (.C(pixel_clock), .CE(1'b1), .D(1'b1), .Q(tmds_enc_10[2]), .R(SR)); endmodule (* ORIG_REF_NAME = "dvi_tx_tmds_enc" *) module dvi_tx_tmds_enc_2 (Q, den_lat_reg, pixel_clock, den_lat, SR); output [1:0]Q; input den_lat_reg; input pixel_clock; input den_lat; input [0:0]SR; wire [1:0]Q; wire [0:0]SR; wire \cnt_q[0]_i_2_n_0 ; wire \cnt_q[0]_i_4_n_0 ; wire \cnt_q[0]_i_5__1_n_0 ; wire \cnt_q[0]_i_6__1_n_0 ; wire \cnt_q[0]_i_7_n_0 ; wire \cnt_q[1]_i_1__1_n_0 ; wire \cnt_q[1]_i_3_n_0 ; wire \cnt_q[1]_i_4__1_n_0 ; wire \cnt_q[1]_i_5_n_0 ; wire \cnt_q[1]_i_6__1_n_0 ; wire \cnt_q[2]_i_1__1_n_0 ; wire \cnt_q[3]_i_1__1_n_0 ; wire \cnt_q[4]_i_1__1_n_0 ; wire \cnt_q[4]_i_3__1_n_0 ; wire \cnt_q[4]_i_4__1_n_0 ; wire \cnt_q[4]_i_5__1_n_0 ; wire \cnt_q[4]_i_6__1_n_0 ; wire \cnt_q[5]_i_1__1_n_0 ; wire \cnt_q[5]_i_3__1_n_0 ; wire \cnt_q[5]_i_4__1_n_0 ; wire \cnt_q[5]_i_5__1_n_0 ; wire \cnt_q[5]_i_6__1_n_0 ; wire \cnt_q[6]_i_1__1_n_0 ; wire \cnt_q[7]_i_1__1_n_0 ; wire \cnt_q[8]_i_1__1_n_0 ; wire \cnt_q[8]_i_3__1_n_0 ; wire \cnt_q_reg[0]_i_3_n_0 ; wire \cnt_q_reg[0]_i_3_n_1 ; wire \cnt_q_reg[0]_i_3_n_2 ; wire \cnt_q_reg[0]_i_3_n_3 ; wire \cnt_q_reg[0]_i_3_n_4 ; wire \cnt_q_reg[0]_i_3_n_5 ; wire \cnt_q_reg[0]_i_3_n_6 ; wire \cnt_q_reg[0]_i_3_n_7 ; wire \cnt_q_reg[1]_i_2__1_n_0 ; wire \cnt_q_reg[1]_i_2__1_n_1 ; wire \cnt_q_reg[1]_i_2__1_n_2 ; wire \cnt_q_reg[1]_i_2__1_n_3 ; wire \cnt_q_reg[1]_i_2__1_n_4 ; wire \cnt_q_reg[1]_i_2__1_n_5 ; wire \cnt_q_reg[1]_i_2__1_n_6 ; wire \cnt_q_reg[1]_i_2__1_n_7 ; wire \cnt_q_reg[4]_i_2__1_n_0 ; wire \cnt_q_reg[4]_i_2__1_n_1 ; wire \cnt_q_reg[4]_i_2__1_n_2 ; wire \cnt_q_reg[4]_i_2__1_n_3 ; wire \cnt_q_reg[4]_i_2__1_n_4 ; wire \cnt_q_reg[4]_i_2__1_n_5 ; wire \cnt_q_reg[4]_i_2__1_n_6 ; wire \cnt_q_reg[4]_i_2__1_n_7 ; wire \cnt_q_reg[5]_i_2__1_n_1 ; wire \cnt_q_reg[5]_i_2__1_n_2 ; wire \cnt_q_reg[5]_i_2__1_n_3 ; wire \cnt_q_reg[5]_i_2__1_n_4 ; wire \cnt_q_reg[5]_i_2__1_n_5 ; wire \cnt_q_reg[5]_i_2__1_n_6 ; wire \cnt_q_reg[5]_i_2__1_n_7 ; wire \cnt_q_reg[8]_i_2__1_n_7 ; wire \cnt_q_reg_n_0_[0] ; wire \cnt_q_reg_n_0_[1] ; wire \cnt_q_reg_n_0_[2] ; wire \cnt_q_reg_n_0_[3] ; wire \cnt_q_reg_n_0_[4] ; wire \cnt_q_reg_n_0_[5] ; wire \cnt_q_reg_n_0_[6] ; wire \cnt_q_reg_n_0_[7] ; wire \cnt_q_reg_n_0_[8] ; wire den_lat; wire den_lat_reg; wire pixel_clock; wire q_out23_in; wire q_out2_carry_i_1__1_n_0; wire q_out2_carry_i_2__1_n_0; wire q_out2_carry_i_3__1_n_0; wire q_out2_carry_n_2; wire q_out2_carry_n_3; wire \tmds[0]_i_1__1_n_0 ; wire \tmds[2]_i_1__1_n_0 ; wire [3:3]\NLW_cnt_q_reg[5]_i_2__1_CO_UNCONNECTED ; wire [3:0]\NLW_cnt_q_reg[8]_i_2__1_CO_UNCONNECTED ; wire [3:1]\NLW_cnt_q_reg[8]_i_2__1_O_UNCONNECTED ; wire [3:3]NLW_q_out2_carry_CO_UNCONNECTED; wire [3:0]NLW_q_out2_carry_O_UNCONNECTED; LUT4 #( .INIT(16'hFB08)) \cnt_q[0]_i_2 (.I0(\cnt_q_reg_n_0_[0] ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_3_n_7 ), .O(\cnt_q[0]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[0]_i_4 (.I0(\cnt_q_reg_n_0_[3] ), .O(\cnt_q[0]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_5__1 (.I0(\cnt_q_reg_n_0_[2] ), .O(\cnt_q[0]_i_5__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_6__1 (.I0(\cnt_q_reg_n_0_[1] ), .O(\cnt_q[0]_i_6__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[0]_i_7 (.I0(\cnt_q_reg_n_0_[0] ), .O(\cnt_q[0]_i_7_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[1]_i_1__1 (.I0(\cnt_q_reg[1]_i_2__1_n_7 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_3_n_6 ), .O(\cnt_q[1]_i_1__1_n_0 )); LUT2 #( .INIT(4'h6)) \cnt_q[1]_i_3 (.I0(\cnt_q_reg_n_0_[3] ), .I1(\cnt_q_reg_n_0_[4] ), .O(\cnt_q[1]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[1]_i_4__1 (.I0(\cnt_q_reg_n_0_[3] ), .O(\cnt_q[1]_i_4__1_n_0 )); LUT2 #( .INIT(4'h6)) \cnt_q[1]_i_5 (.I0(\cnt_q_reg_n_0_[1] ), .I1(\cnt_q_reg_n_0_[2] ), .O(\cnt_q[1]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[1]_i_6__1 (.I0(\cnt_q_reg_n_0_[1] ), .O(\cnt_q[1]_i_6__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[2]_i_1__1 (.I0(\cnt_q_reg[1]_i_2__1_n_6 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_3_n_5 ), .O(\cnt_q[2]_i_1__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[3]_i_1__1 (.I0(\cnt_q_reg[1]_i_2__1_n_5 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[0]_i_3_n_4 ), .O(\cnt_q[3]_i_1__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[4]_i_1__1 (.I0(\cnt_q_reg[1]_i_2__1_n_4 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__1_n_7 ), .O(\cnt_q[4]_i_1__1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_3__1 (.I0(\cnt_q_reg_n_0_[7] ), .O(\cnt_q[4]_i_3__1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_4__1 (.I0(\cnt_q_reg_n_0_[6] ), .O(\cnt_q[4]_i_4__1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_5__1 (.I0(\cnt_q_reg_n_0_[5] ), .O(\cnt_q[4]_i_5__1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[4]_i_6__1 (.I0(\cnt_q_reg_n_0_[4] ), .O(\cnt_q[4]_i_6__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[5]_i_1__1 (.I0(\cnt_q_reg[5]_i_2__1_n_7 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__1_n_6 ), .O(\cnt_q[5]_i_1__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_3__1 (.I0(\cnt_q_reg_n_0_[8] ), .O(\cnt_q[5]_i_3__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_4__1 (.I0(\cnt_q_reg_n_0_[7] ), .O(\cnt_q[5]_i_4__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_5__1 (.I0(\cnt_q_reg_n_0_[6] ), .O(\cnt_q[5]_i_5__1_n_0 )); LUT1 #( .INIT(2'h2)) \cnt_q[5]_i_6__1 (.I0(\cnt_q_reg_n_0_[5] ), .O(\cnt_q[5]_i_6__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[6]_i_1__1 (.I0(\cnt_q_reg[5]_i_2__1_n_6 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__1_n_5 ), .O(\cnt_q[6]_i_1__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[7]_i_1__1 (.I0(\cnt_q_reg[5]_i_2__1_n_5 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[4]_i_2__1_n_4 ), .O(\cnt_q[7]_i_1__1_n_0 )); LUT4 #( .INIT(16'hFB08)) \cnt_q[8]_i_1__1 (.I0(\cnt_q_reg[5]_i_2__1_n_4 ), .I1(\cnt_q_reg_n_0_[8] ), .I2(q_out23_in), .I3(\cnt_q_reg[8]_i_2__1_n_7 ), .O(\cnt_q[8]_i_1__1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_q[8]_i_3__1 (.I0(\cnt_q_reg_n_0_[8] ), .O(\cnt_q[8]_i_3__1_n_0 )); FDRE #( .INIT(1'b0)) \cnt_q_reg[0] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[0]_i_2_n_0 ), .Q(\cnt_q_reg_n_0_[0] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[0]_i_3 (.CI(1'b0), .CO({\cnt_q_reg[0]_i_3_n_0 ,\cnt_q_reg[0]_i_3_n_1 ,\cnt_q_reg[0]_i_3_n_2 ,\cnt_q_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({\cnt_q_reg_n_0_[3] ,\cnt_q_reg_n_0_[2] ,\cnt_q_reg_n_0_[1] ,1'b0}), .O({\cnt_q_reg[0]_i_3_n_4 ,\cnt_q_reg[0]_i_3_n_5 ,\cnt_q_reg[0]_i_3_n_6 ,\cnt_q_reg[0]_i_3_n_7 }), .S({\cnt_q[0]_i_4_n_0 ,\cnt_q[0]_i_5__1_n_0 ,\cnt_q[0]_i_6__1_n_0 ,\cnt_q[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[1] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[1]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[1] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[1]_i_2__1 (.CI(1'b0), .CO({\cnt_q_reg[1]_i_2__1_n_0 ,\cnt_q_reg[1]_i_2__1_n_1 ,\cnt_q_reg[1]_i_2__1_n_2 ,\cnt_q_reg[1]_i_2__1_n_3 }), .CYINIT(1'b0), .DI({\cnt_q_reg_n_0_[3] ,1'b0,\cnt_q_reg_n_0_[1] ,1'b0}), .O({\cnt_q_reg[1]_i_2__1_n_4 ,\cnt_q_reg[1]_i_2__1_n_5 ,\cnt_q_reg[1]_i_2__1_n_6 ,\cnt_q_reg[1]_i_2__1_n_7 }), .S({\cnt_q[1]_i_3_n_0 ,\cnt_q[1]_i_4__1_n_0 ,\cnt_q[1]_i_5_n_0 ,\cnt_q[1]_i_6__1_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[2] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[2]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[2] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[3] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[3]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[3] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[4] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[4]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[4] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[4]_i_2__1 (.CI(\cnt_q_reg[0]_i_3_n_0 ), .CO({\cnt_q_reg[4]_i_2__1_n_0 ,\cnt_q_reg[4]_i_2__1_n_1 ,\cnt_q_reg[4]_i_2__1_n_2 ,\cnt_q_reg[4]_i_2__1_n_3 }), .CYINIT(1'b0), .DI({\cnt_q_reg_n_0_[7] ,\cnt_q_reg_n_0_[6] ,\cnt_q_reg_n_0_[5] ,\cnt_q_reg_n_0_[4] }), .O({\cnt_q_reg[4]_i_2__1_n_4 ,\cnt_q_reg[4]_i_2__1_n_5 ,\cnt_q_reg[4]_i_2__1_n_6 ,\cnt_q_reg[4]_i_2__1_n_7 }), .S({\cnt_q[4]_i_3__1_n_0 ,\cnt_q[4]_i_4__1_n_0 ,\cnt_q[4]_i_5__1_n_0 ,\cnt_q[4]_i_6__1_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[5] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[5]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[5] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[5]_i_2__1 (.CI(\cnt_q_reg[1]_i_2__1_n_0 ), .CO({\NLW_cnt_q_reg[5]_i_2__1_CO_UNCONNECTED [3],\cnt_q_reg[5]_i_2__1_n_1 ,\cnt_q_reg[5]_i_2__1_n_2 ,\cnt_q_reg[5]_i_2__1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\cnt_q_reg[5]_i_2__1_n_4 ,\cnt_q_reg[5]_i_2__1_n_5 ,\cnt_q_reg[5]_i_2__1_n_6 ,\cnt_q_reg[5]_i_2__1_n_7 }), .S({\cnt_q[5]_i_3__1_n_0 ,\cnt_q[5]_i_4__1_n_0 ,\cnt_q[5]_i_5__1_n_0 ,\cnt_q[5]_i_6__1_n_0 })); FDRE #( .INIT(1'b0)) \cnt_q_reg[6] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[6]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[6] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[7] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[7]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[7] ), .R(den_lat_reg)); FDRE #( .INIT(1'b0)) \cnt_q_reg[8] (.C(pixel_clock), .CE(1'b1), .D(\cnt_q[8]_i_1__1_n_0 ), .Q(\cnt_q_reg_n_0_[8] ), .R(den_lat_reg)); CARRY4 \cnt_q_reg[8]_i_2__1 (.CI(\cnt_q_reg[4]_i_2__1_n_0 ), .CO(\NLW_cnt_q_reg[8]_i_2__1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_cnt_q_reg[8]_i_2__1_O_UNCONNECTED [3:1],\cnt_q_reg[8]_i_2__1_n_7 }), .S({1'b0,1'b0,1'b0,\cnt_q[8]_i_3__1_n_0 })); CARRY4 q_out2_carry (.CI(1'b0), .CO({NLW_q_out2_carry_CO_UNCONNECTED[3],q_out23_in,q_out2_carry_n_2,q_out2_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_q_out2_carry_O_UNCONNECTED[3:0]), .S({1'b0,q_out2_carry_i_1__1_n_0,q_out2_carry_i_2__1_n_0,q_out2_carry_i_3__1_n_0})); LUT3 #( .INIT(8'h01)) q_out2_carry_i_1__1 (.I0(\cnt_q_reg_n_0_[6] ), .I1(\cnt_q_reg_n_0_[7] ), .I2(\cnt_q_reg_n_0_[8] ), .O(q_out2_carry_i_1__1_n_0)); LUT3 #( .INIT(8'h01)) q_out2_carry_i_2__1 (.I0(\cnt_q_reg_n_0_[3] ), .I1(\cnt_q_reg_n_0_[4] ), .I2(\cnt_q_reg_n_0_[5] ), .O(q_out2_carry_i_2__1_n_0)); LUT3 #( .INIT(8'h01)) q_out2_carry_i_3__1 (.I0(\cnt_q_reg_n_0_[2] ), .I1(\cnt_q_reg_n_0_[1] ), .I2(\cnt_q_reg_n_0_[0] ), .O(q_out2_carry_i_3__1_n_0)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( .INIT(8'h40)) \tmds[0]_i_1__1 (.I0(q_out23_in), .I1(\cnt_q_reg_n_0_[8] ), .I2(den_lat), .O(\tmds[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( .INIT(8'h4F)) \tmds[2]_i_1__1 (.I0(q_out23_in), .I1(\cnt_q_reg_n_0_[8] ), .I2(den_lat), .O(\tmds[2]_i_1__1_n_0 )); FDRE #( .INIT(1'b0)) \tmds_reg[0] (.C(pixel_clock), .CE(1'b1), .D(\tmds[0]_i_1__1_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \tmds_reg[2] (.C(pixel_clock), .CE(1'b1), .D(\tmds[2]_i_1__1_n_0 ), .Q(Q[1]), .R(SR)); endmodule module dvi_tx_tmds_phy (RST, hdmi_d0, dvi_bit_clock, pixel_clock, Q, SR); output RST; output [1:0]hdmi_d0; input dvi_bit_clock; input pixel_clock; input [3:0]Q; input [0:0]SR; wire [3:0]Q; wire RST; wire SHIFTIN1; wire SHIFTIN2; wire [0:0]SR; wire data_se; wire dvi_bit_clock; wire [1:0]hdmi_d0; wire pixel_clock; wire NLW_master_oserdes_OFB_UNCONNECTED; wire NLW_master_oserdes_SHIFTOUT1_UNCONNECTED; wire NLW_master_oserdes_SHIFTOUT2_UNCONNECTED; wire NLW_master_oserdes_TBYTEOUT_UNCONNECTED; wire NLW_master_oserdes_TFB_UNCONNECTED; wire NLW_master_oserdes_TQ_UNCONNECTED; wire NLW_slave_oserdes_OFB_UNCONNECTED; wire NLW_slave_oserdes_OQ_UNCONNECTED; wire NLW_slave_oserdes_TBYTEOUT_UNCONNECTED; wire NLW_slave_oserdes_TFB_UNCONNECTED; wire NLW_slave_oserdes_TQ_UNCONNECTED; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(10), .INIT_OQ(1'b0), .INIT_TQ(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b0), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) master_oserdes (.CLK(dvi_bit_clock), .CLKDIV(pixel_clock), .D1(Q[0]), .D2(Q[0]), .D3(Q[1]), .D4(Q[0]), .D5(Q[1]), .D6(Q[0]), .D7(Q[1]), .D8(Q[0]), .OCE(1'b1), .OFB(NLW_master_oserdes_OFB_UNCONNECTED), .OQ(data_se), .RST(RST), .SHIFTIN1(SHIFTIN1), .SHIFTIN2(SHIFTIN2), .SHIFTOUT1(NLW_master_oserdes_SHIFTOUT1_UNCONNECTED), .SHIFTOUT2(NLW_master_oserdes_SHIFTOUT2_UNCONNECTED), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(NLW_master_oserdes_TBYTEOUT_UNCONNECTED), .TCE(1'b1), .TFB(NLW_master_oserdes_TFB_UNCONNECTED), .TQ(NLW_master_oserdes_TQ_UNCONNECTED)); (* CAPACITANCE = "DONT_CARE" *) (* XILINX_LEGACY_PRIM = "OBUFDS" *) (* box_type = "PRIMITIVE" *) OBUFDS #( .IOSTANDARD("DEFAULT")) outbuf (.I(data_se), .O(hdmi_d0[1]), .OB(hdmi_d0[0])); FDRE #( .INIT(1'b0)) reset_lat_reg (.C(pixel_clock), .CE(1'b1), .D(SR), .Q(RST), .R(1'b0)); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(10), .INIT_OQ(1'b0), .INIT_TQ(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("SLAVE"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b0), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) slave_oserdes (.CLK(dvi_bit_clock), .CLKDIV(pixel_clock), .D1(1'b0), .D2(1'b0), .D3(Q[2]), .D4(Q[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(NLW_slave_oserdes_OFB_UNCONNECTED), .OQ(NLW_slave_oserdes_OQ_UNCONNECTED), .RST(RST), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(SHIFTIN1), .SHIFTOUT2(SHIFTIN2), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(NLW_slave_oserdes_TBYTEOUT_UNCONNECTED), .TCE(1'b1), .TFB(NLW_slave_oserdes_TFB_UNCONNECTED), .TQ(NLW_slave_oserdes_TQ_UNCONNECTED)); endmodule (* ORIG_REF_NAME = "dvi_tx_tmds_phy" *) module dvi_tx_tmds_phy_1 (hdmi_d1, dvi_bit_clock, pixel_clock, tmds_enc_10, RST); output [1:0]hdmi_d1; input dvi_bit_clock; input pixel_clock; input [2:0]tmds_enc_10; input RST; wire RST; wire SHIFTIN1; wire SHIFTIN2; wire data_se; wire dvi_bit_clock; wire [1:0]hdmi_d1; wire pixel_clock; wire [2:0]tmds_enc_10; wire NLW_master_oserdes_OFB_UNCONNECTED; wire NLW_master_oserdes_SHIFTOUT1_UNCONNECTED; wire NLW_master_oserdes_SHIFTOUT2_UNCONNECTED; wire NLW_master_oserdes_TBYTEOUT_UNCONNECTED; wire NLW_master_oserdes_TFB_UNCONNECTED; wire NLW_master_oserdes_TQ_UNCONNECTED; wire NLW_slave_oserdes_OFB_UNCONNECTED; wire NLW_slave_oserdes_OQ_UNCONNECTED; wire NLW_slave_oserdes_TBYTEOUT_UNCONNECTED; wire NLW_slave_oserdes_TFB_UNCONNECTED; wire NLW_slave_oserdes_TQ_UNCONNECTED; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(10), .INIT_OQ(1'b0), .INIT_TQ(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b0), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) master_oserdes (.CLK(dvi_bit_clock), .CLKDIV(pixel_clock), .D1(tmds_enc_10[0]), .D2(tmds_enc_10[0]), .D3(tmds_enc_10[1]), .D4(tmds_enc_10[0]), .D5(tmds_enc_10[1]), .D6(tmds_enc_10[0]), .D7(tmds_enc_10[1]), .D8(tmds_enc_10[0]), .OCE(1'b1), .OFB(NLW_master_oserdes_OFB_UNCONNECTED), .OQ(data_se), .RST(RST), .SHIFTIN1(SHIFTIN1), .SHIFTIN2(SHIFTIN2), .SHIFTOUT1(NLW_master_oserdes_SHIFTOUT1_UNCONNECTED), .SHIFTOUT2(NLW_master_oserdes_SHIFTOUT2_UNCONNECTED), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(NLW_master_oserdes_TBYTEOUT_UNCONNECTED), .TCE(1'b1), .TFB(NLW_master_oserdes_TFB_UNCONNECTED), .TQ(NLW_master_oserdes_TQ_UNCONNECTED)); (* CAPACITANCE = "DONT_CARE" *) (* XILINX_LEGACY_PRIM = "OBUFDS" *) (* box_type = "PRIMITIVE" *) OBUFDS #( .IOSTANDARD("DEFAULT")) outbuf (.I(data_se), .O(hdmi_d1[1]), .OB(hdmi_d1[0])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(10), .INIT_OQ(1'b0), .INIT_TQ(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("SLAVE"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b0), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) slave_oserdes (.CLK(dvi_bit_clock), .CLKDIV(pixel_clock), .D1(1'b0), .D2(1'b0), .D3(tmds_enc_10[2]), .D4(tmds_enc_10[1]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(NLW_slave_oserdes_OFB_UNCONNECTED), .OQ(NLW_slave_oserdes_OQ_UNCONNECTED), .RST(RST), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(SHIFTIN1), .SHIFTOUT2(SHIFTIN2), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(NLW_slave_oserdes_TBYTEOUT_UNCONNECTED), .TCE(1'b1), .TFB(NLW_slave_oserdes_TFB_UNCONNECTED), .TQ(NLW_slave_oserdes_TQ_UNCONNECTED)); endmodule (* ORIG_REF_NAME = "dvi_tx_tmds_phy" *) module dvi_tx_tmds_phy_3 (hdmi_d2, dvi_bit_clock, pixel_clock, Q, RST, tmds_enc_10); output [1:0]hdmi_d2; input dvi_bit_clock; input pixel_clock; input [1:0]Q; input RST; input [0:0]tmds_enc_10; wire [1:0]Q; wire RST; wire SHIFTIN1; wire SHIFTIN2; wire data_se; wire dvi_bit_clock; wire [1:0]hdmi_d2; wire pixel_clock; wire [0:0]tmds_enc_10; wire NLW_master_oserdes_OFB_UNCONNECTED; wire NLW_master_oserdes_SHIFTOUT1_UNCONNECTED; wire NLW_master_oserdes_SHIFTOUT2_UNCONNECTED; wire NLW_master_oserdes_TBYTEOUT_UNCONNECTED; wire NLW_master_oserdes_TFB_UNCONNECTED; wire NLW_master_oserdes_TQ_UNCONNECTED; wire NLW_slave_oserdes_OFB_UNCONNECTED; wire NLW_slave_oserdes_OQ_UNCONNECTED; wire NLW_slave_oserdes_TBYTEOUT_UNCONNECTED; wire NLW_slave_oserdes_TFB_UNCONNECTED; wire NLW_slave_oserdes_TQ_UNCONNECTED; (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(10), .INIT_OQ(1'b0), .INIT_TQ(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b0), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) master_oserdes (.CLK(dvi_bit_clock), .CLKDIV(pixel_clock), .D1(Q[0]), .D2(Q[0]), .D3(Q[1]), .D4(Q[0]), .D5(Q[1]), .D6(Q[0]), .D7(Q[1]), .D8(Q[0]), .OCE(1'b1), .OFB(NLW_master_oserdes_OFB_UNCONNECTED), .OQ(data_se), .RST(RST), .SHIFTIN1(SHIFTIN1), .SHIFTIN2(SHIFTIN2), .SHIFTOUT1(NLW_master_oserdes_SHIFTOUT1_UNCONNECTED), .SHIFTOUT2(NLW_master_oserdes_SHIFTOUT2_UNCONNECTED), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(NLW_master_oserdes_TBYTEOUT_UNCONNECTED), .TCE(1'b1), .TFB(NLW_master_oserdes_TFB_UNCONNECTED), .TQ(NLW_master_oserdes_TQ_UNCONNECTED)); (* CAPACITANCE = "DONT_CARE" *) (* XILINX_LEGACY_PRIM = "OBUFDS" *) (* box_type = "PRIMITIVE" *) OBUFDS #( .IOSTANDARD("DEFAULT")) outbuf (.I(data_se), .O(hdmi_d2[1]), .OB(hdmi_d2[0])); (* box_type = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(10), .INIT_OQ(1'b0), .INIT_TQ(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("SLAVE"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b0), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) slave_oserdes (.CLK(dvi_bit_clock), .CLKDIV(pixel_clock), .D1(1'b0), .D2(1'b0), .D3(tmds_enc_10), .D4(Q[1]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(NLW_slave_oserdes_OFB_UNCONNECTED), .OQ(NLW_slave_oserdes_OQ_UNCONNECTED), .RST(RST), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(SHIFTIN1), .SHIFTOUT2(SHIFTIN2), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(NLW_slave_oserdes_TBYTEOUT_UNCONNECTED), .TCE(1'b1), .TFB(NLW_slave_oserdes_TFB_UNCONNECTED), .TQ(NLW_slave_oserdes_TQ_UNCONNECTED)); endmodule (* CHECK_LICENSE_TYPE = "fb_input_fifo,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) module fb_input_fifo (rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_empty); input rst; (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk; (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [255:0]dout; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; output prog_empty; wire [63:0]din; wire [255:0]dout; wire empty; wire full; wire prog_empty; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; wire NLW_U0_almost_empty_UNCONNECTED; wire NLW_U0_almost_full_UNCONNECTED; wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; wire NLW_U0_axi_ar_overflow_UNCONNECTED; wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; wire NLW_U0_axi_ar_prog_full_UNCONNECTED; wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; wire NLW_U0_axi_ar_underflow_UNCONNECTED; wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; wire NLW_U0_axi_aw_overflow_UNCONNECTED; wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; wire NLW_U0_axi_aw_prog_full_UNCONNECTED; wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; wire NLW_U0_axi_aw_underflow_UNCONNECTED; wire NLW_U0_axi_b_dbiterr_UNCONNECTED; wire NLW_U0_axi_b_overflow_UNCONNECTED; wire NLW_U0_axi_b_prog_empty_UNCONNECTED; wire NLW_U0_axi_b_prog_full_UNCONNECTED; wire NLW_U0_axi_b_sbiterr_UNCONNECTED; wire NLW_U0_axi_b_underflow_UNCONNECTED; wire NLW_U0_axi_r_dbiterr_UNCONNECTED; wire NLW_U0_axi_r_overflow_UNCONNECTED; wire NLW_U0_axi_r_prog_empty_UNCONNECTED; wire NLW_U0_axi_r_prog_full_UNCONNECTED; wire NLW_U0_axi_r_sbiterr_UNCONNECTED; wire NLW_U0_axi_r_underflow_UNCONNECTED; wire NLW_U0_axi_w_dbiterr_UNCONNECTED; wire NLW_U0_axi_w_overflow_UNCONNECTED; wire NLW_U0_axi_w_prog_empty_UNCONNECTED; wire NLW_U0_axi_w_prog_full_UNCONNECTED; wire NLW_U0_axi_w_sbiterr_UNCONNECTED; wire NLW_U0_axi_w_underflow_UNCONNECTED; wire NLW_U0_axis_dbiterr_UNCONNECTED; wire NLW_U0_axis_overflow_UNCONNECTED; wire NLW_U0_axis_prog_empty_UNCONNECTED; wire NLW_U0_axis_prog_full_UNCONNECTED; wire NLW_U0_axis_sbiterr_UNCONNECTED; wire NLW_U0_axis_underflow_UNCONNECTED; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_m_axi_arvalid_UNCONNECTED; wire NLW_U0_m_axi_awvalid_UNCONNECTED; wire NLW_U0_m_axi_bready_UNCONNECTED; wire NLW_U0_m_axi_rready_UNCONNECTED; wire NLW_U0_m_axi_wlast_UNCONNECTED; wire NLW_U0_m_axi_wvalid_UNCONNECTED; wire NLW_U0_m_axis_tlast_UNCONNECTED; wire NLW_U0_m_axis_tvalid_UNCONNECTED; wire NLW_U0_overflow_UNCONNECTED; wire NLW_U0_prog_full_UNCONNECTED; wire NLW_U0_rd_rst_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_s_axis_tready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire NLW_U0_underflow_UNCONNECTED; wire NLW_U0_valid_UNCONNECTED; wire NLW_U0_wr_ack_UNCONNECTED; wire NLW_U0_wr_rst_busy_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; wire [8:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; wire [10:0]NLW_U0_wr_data_count_UNCONNECTED; (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "11" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "256" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "2kx18" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "15" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "16" *) (* C_PROG_EMPTY_TYPE = "1" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "2045" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "2044" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *) (* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "9" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "11" *) (* C_WR_DEPTH = "2048" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "11" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) fb_input_fifo_fifo_generator_v13_1_2 U0 (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), .almost_full(NLW_U0_almost_full_UNCONNECTED), .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), .axi_ar_injectdbiterr(1'b0), .axi_ar_injectsbiterr(1'b0), .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), .axi_aw_injectdbiterr(1'b0), .axi_aw_injectsbiterr(1'b0), .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), .axi_b_injectdbiterr(1'b0), .axi_b_injectsbiterr(1'b0), .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), .axi_r_injectdbiterr(1'b0), .axi_r_injectsbiterr(1'b0), .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), .axi_w_injectdbiterr(1'b0), .axi_w_injectsbiterr(1'b0), .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), .axis_injectdbiterr(1'b0), .axis_injectsbiterr(1'b0), .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), .data_count(NLW_U0_data_count_UNCONNECTED[10:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), .empty(empty), .full(full), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .int_clk(1'b0), .m_aclk(1'b0), .m_aclk_en(1'b0), .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), .m_axi_arready(1'b0), .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), .m_axi_bid(1'b0), .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), .m_axi_bresp({1'b0,1'b0}), .m_axi_buser(1'b0), .m_axi_bvalid(1'b0), .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rid(1'b0), .m_axi_rlast(1'b0), .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), .m_axi_rresp({1'b0,1'b0}), .m_axi_ruser(1'b0), .m_axi_rvalid(1'b0), .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), .m_axi_wready(1'b0), .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), .m_axis_tready(1'b0), .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(prog_empty), .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full(NLW_U0_prog_full_UNCONNECTED), .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]), .rd_en(rd_en), .rd_rst(1'b0), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), .rst(rst), .s_aclk(1'b0), .s_aclk_en(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_arid(1'b0), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_aruser(1'b0), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awuser(1'b0), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wid(1'b0), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser(1'b0), .s_axi_wvalid(1'b0), .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axis_tdest(1'b0), .s_axis_tid(1'b0), .s_axis_tkeep(1'b0), .s_axis_tlast(1'b0), .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), .s_axis_tstrb(1'b0), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .sleep(1'b0), .srst(1'b0), .underflow(NLW_U0_underflow_UNCONNECTED), .valid(NLW_U0_valid_UNCONNECTED), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[10:0]), .wr_en(wr_en), .wr_rst(1'b0), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule (* CHECK_LICENSE_TYPE = "fb_output_fifo,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) module fb_output_fifo (rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_full); input rst; (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk; (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [127:0]din; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; output prog_full; wire [127:0]din; wire [31:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; wire NLW_U0_almost_empty_UNCONNECTED; wire NLW_U0_almost_full_UNCONNECTED; wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; wire NLW_U0_axi_ar_overflow_UNCONNECTED; wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; wire NLW_U0_axi_ar_prog_full_UNCONNECTED; wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; wire NLW_U0_axi_ar_underflow_UNCONNECTED; wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; wire NLW_U0_axi_aw_overflow_UNCONNECTED; wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; wire NLW_U0_axi_aw_prog_full_UNCONNECTED; wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; wire NLW_U0_axi_aw_underflow_UNCONNECTED; wire NLW_U0_axi_b_dbiterr_UNCONNECTED; wire NLW_U0_axi_b_overflow_UNCONNECTED; wire NLW_U0_axi_b_prog_empty_UNCONNECTED; wire NLW_U0_axi_b_prog_full_UNCONNECTED; wire NLW_U0_axi_b_sbiterr_UNCONNECTED; wire NLW_U0_axi_b_underflow_UNCONNECTED; wire NLW_U0_axi_r_dbiterr_UNCONNECTED; wire NLW_U0_axi_r_overflow_UNCONNECTED; wire NLW_U0_axi_r_prog_empty_UNCONNECTED; wire NLW_U0_axi_r_prog_full_UNCONNECTED; wire NLW_U0_axi_r_sbiterr_UNCONNECTED; wire NLW_U0_axi_r_underflow_UNCONNECTED; wire NLW_U0_axi_w_dbiterr_UNCONNECTED; wire NLW_U0_axi_w_overflow_UNCONNECTED; wire NLW_U0_axi_w_prog_empty_UNCONNECTED; wire NLW_U0_axi_w_prog_full_UNCONNECTED; wire NLW_U0_axi_w_sbiterr_UNCONNECTED; wire NLW_U0_axi_w_underflow_UNCONNECTED; wire NLW_U0_axis_dbiterr_UNCONNECTED; wire NLW_U0_axis_overflow_UNCONNECTED; wire NLW_U0_axis_prog_empty_UNCONNECTED; wire NLW_U0_axis_prog_full_UNCONNECTED; wire NLW_U0_axis_sbiterr_UNCONNECTED; wire NLW_U0_axis_underflow_UNCONNECTED; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_m_axi_arvalid_UNCONNECTED; wire NLW_U0_m_axi_awvalid_UNCONNECTED; wire NLW_U0_m_axi_bready_UNCONNECTED; wire NLW_U0_m_axi_rready_UNCONNECTED; wire NLW_U0_m_axi_wlast_UNCONNECTED; wire NLW_U0_m_axi_wvalid_UNCONNECTED; wire NLW_U0_m_axis_tlast_UNCONNECTED; wire NLW_U0_m_axis_tvalid_UNCONNECTED; wire NLW_U0_overflow_UNCONNECTED; wire NLW_U0_prog_empty_UNCONNECTED; wire NLW_U0_rd_rst_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_s_axis_tready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire NLW_U0_underflow_UNCONNECTED; wire NLW_U0_valid_UNCONNECTED; wire NLW_U0_wr_ack_UNCONNECTED; wire NLW_U0_wr_rst_busy_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; wire [8:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; wire [10:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; wire [8:0]NLW_U0_wr_data_count_UNCONNECTED; (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "128" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x72" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "496" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "495" *) (* C_PROG_FULL_TYPE = "1" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "11" *) (* C_RD_DEPTH = "2048" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "11" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *) (* C_WR_DEPTH = "512" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) fb_output_fifo_fifo_generator_v13_1_2 U0 (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), .almost_full(NLW_U0_almost_full_UNCONNECTED), .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), .axi_ar_injectdbiterr(1'b0), .axi_ar_injectsbiterr(1'b0), .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), .axi_aw_injectdbiterr(1'b0), .axi_aw_injectsbiterr(1'b0), .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), .axi_b_injectdbiterr(1'b0), .axi_b_injectsbiterr(1'b0), .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), .axi_r_injectdbiterr(1'b0), .axi_r_injectsbiterr(1'b0), .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), .axi_w_injectdbiterr(1'b0), .axi_w_injectsbiterr(1'b0), .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), .axis_injectdbiterr(1'b0), .axis_injectsbiterr(1'b0), .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), .data_count(NLW_U0_data_count_UNCONNECTED[8:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), .empty(empty), .full(full), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .int_clk(1'b0), .m_aclk(1'b0), .m_aclk_en(1'b0), .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), .m_axi_arready(1'b0), .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), .m_axi_bid(1'b0), .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), .m_axi_bresp({1'b0,1'b0}), .m_axi_buser(1'b0), .m_axi_bvalid(1'b0), .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rid(1'b0), .m_axi_rlast(1'b0), .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), .m_axi_rresp({1'b0,1'b0}), .m_axi_ruser(1'b0), .m_axi_rvalid(1'b0), .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), .m_axi_wready(1'b0), .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), .m_axis_tready(1'b0), .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(NLW_U0_prog_empty_UNCONNECTED), .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full(prog_full), .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[10:0]), .rd_en(rd_en), .rd_rst(1'b0), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), .rst(rst), .s_aclk(1'b0), .s_aclk_en(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_arid(1'b0), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_aruser(1'b0), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awuser(1'b0), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wid(1'b0), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser(1'b0), .s_axi_wvalid(1'b0), .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axis_tdest(1'b0), .s_axis_tid(1'b0), .s_axis_tkeep(1'b0), .s_axis_tlast(1'b0), .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), .s_axis_tstrb(1'b0), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .sleep(1'b0), .srst(1'b0), .underflow(NLW_U0_underflow_UNCONNECTED), .valid(NLW_U0_valid_UNCONNECTED), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[8:0]), .wr_en(wr_en), .wr_rst(1'b0), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule module framebuffer_addr_ctrl (s_axi_awaddr, \FSM_sequential_write_state_reg[0] , \FSM_sequential_write_state_reg[0]_0 , ui_clk, rst, out); output [16:0]s_axi_awaddr; output \FSM_sequential_write_state_reg[0] ; output \FSM_sequential_write_state_reg[0]_0 ; input ui_clk; input rst; input [2:0]out; wire \FSM_sequential_write_state[2]_i_6_n_0 ; wire \FSM_sequential_write_state_reg[0] ; wire \FSM_sequential_write_state_reg[0]_0 ; wire fb_xpos_q; wire \fb_xpos_q[11]_i_2_n_0 ; wire \fb_xpos_q[7]_i_3_n_0 ; wire \fb_xpos_q[7]_i_4_n_0 ; wire \fb_xpos_q[7]_i_5_n_0 ; wire \fb_xpos_q[7]_i_6_n_0 ; wire [11:7]fb_xpos_q_reg; wire \fb_xpos_q_reg[11]_i_1_n_7 ; wire \fb_xpos_q_reg[7]_i_2_n_0 ; wire \fb_xpos_q_reg[7]_i_2_n_1 ; wire \fb_xpos_q_reg[7]_i_2_n_2 ; wire \fb_xpos_q_reg[7]_i_2_n_3 ; wire \fb_xpos_q_reg[7]_i_2_n_4 ; wire \fb_xpos_q_reg[7]_i_2_n_5 ; wire \fb_xpos_q_reg[7]_i_2_n_6 ; wire \fb_xpos_q_reg[7]_i_2_n_7 ; wire \fb_ypos_q[0]_i_10_n_0 ; wire \fb_ypos_q[0]_i_1_n_0 ; wire \fb_ypos_q[0]_i_3_n_0 ; wire \fb_ypos_q[0]_i_4_n_0 ; wire \fb_ypos_q[0]_i_5_n_0 ; wire \fb_ypos_q[0]_i_6_n_0 ; wire \fb_ypos_q[0]_i_7_n_0 ; wire \fb_ypos_q[0]_i_8_n_0 ; wire \fb_ypos_q[0]_i_9_n_0 ; wire \fb_ypos_q[4]_i_2_n_0 ; wire \fb_ypos_q[4]_i_3_n_0 ; wire \fb_ypos_q[4]_i_4_n_0 ; wire \fb_ypos_q[4]_i_5_n_0 ; wire \fb_ypos_q[8]_i_2_n_0 ; wire \fb_ypos_q[8]_i_3_n_0 ; wire \fb_ypos_q[8]_i_4_n_0 ; wire \fb_ypos_q[8]_i_5_n_0 ; wire [11:0]fb_ypos_q_reg; wire \fb_ypos_q_reg[0]_i_2_n_0 ; wire \fb_ypos_q_reg[0]_i_2_n_1 ; wire \fb_ypos_q_reg[0]_i_2_n_2 ; wire \fb_ypos_q_reg[0]_i_2_n_3 ; wire \fb_ypos_q_reg[0]_i_2_n_4 ; wire \fb_ypos_q_reg[0]_i_2_n_5 ; wire \fb_ypos_q_reg[0]_i_2_n_6 ; wire \fb_ypos_q_reg[0]_i_2_n_7 ; wire \fb_ypos_q_reg[4]_i_1_n_0 ; wire \fb_ypos_q_reg[4]_i_1_n_1 ; wire \fb_ypos_q_reg[4]_i_1_n_2 ; wire \fb_ypos_q_reg[4]_i_1_n_3 ; wire \fb_ypos_q_reg[4]_i_1_n_4 ; wire \fb_ypos_q_reg[4]_i_1_n_5 ; wire \fb_ypos_q_reg[4]_i_1_n_6 ; wire \fb_ypos_q_reg[4]_i_1_n_7 ; wire \fb_ypos_q_reg[8]_i_1_n_1 ; wire \fb_ypos_q_reg[8]_i_1_n_2 ; wire \fb_ypos_q_reg[8]_i_1_n_3 ; wire \fb_ypos_q_reg[8]_i_1_n_4 ; wire \fb_ypos_q_reg[8]_i_1_n_5 ; wire \fb_ypos_q_reg[8]_i_1_n_6 ; wire \fb_ypos_q_reg[8]_i_1_n_7 ; wire int_address_q; wire \int_address_q[11]_i_2_n_0 ; wire \int_address_q[11]_i_3_n_0 ; wire \int_address_q[11]_i_4_n_0 ; wire \int_address_q[11]_i_5__0_n_0 ; wire \int_address_q[15]_i_2_n_0 ; wire \int_address_q[15]_i_3_n_0 ; wire \int_address_q[15]_i_4_n_0 ; wire \int_address_q[15]_i_5_n_0 ; wire \int_address_q[19]_i_2_n_0 ; wire \int_address_q[19]_i_3_n_0 ; wire \int_address_q[19]_i_4_n_0 ; wire \int_address_q[19]_i_5_n_0 ; wire \int_address_q[23]_i_2_n_0 ; wire \int_address_q[7]_i_3__0_n_0 ; wire \int_address_q[7]_i_4__0_n_0 ; wire \int_address_q[7]_i_5__0_n_0 ; wire \int_address_q[7]_i_6_n_0 ; wire \int_address_q_reg[11]_i_1_n_0 ; wire \int_address_q_reg[11]_i_1_n_1 ; wire \int_address_q_reg[11]_i_1_n_2 ; wire \int_address_q_reg[11]_i_1_n_3 ; wire \int_address_q_reg[11]_i_1_n_4 ; wire \int_address_q_reg[11]_i_1_n_5 ; wire \int_address_q_reg[11]_i_1_n_6 ; wire \int_address_q_reg[11]_i_1_n_7 ; wire \int_address_q_reg[15]_i_1_n_0 ; wire \int_address_q_reg[15]_i_1_n_1 ; wire \int_address_q_reg[15]_i_1_n_2 ; wire \int_address_q_reg[15]_i_1_n_3 ; wire \int_address_q_reg[15]_i_1_n_4 ; wire \int_address_q_reg[15]_i_1_n_5 ; wire \int_address_q_reg[15]_i_1_n_6 ; wire \int_address_q_reg[15]_i_1_n_7 ; wire \int_address_q_reg[19]_i_1_n_0 ; wire \int_address_q_reg[19]_i_1_n_1 ; wire \int_address_q_reg[19]_i_1_n_2 ; wire \int_address_q_reg[19]_i_1_n_3 ; wire \int_address_q_reg[19]_i_1_n_4 ; wire \int_address_q_reg[19]_i_1_n_5 ; wire \int_address_q_reg[19]_i_1_n_6 ; wire \int_address_q_reg[19]_i_1_n_7 ; wire \int_address_q_reg[23]_i_1_n_7 ; wire \int_address_q_reg[7]_i_2_n_0 ; wire \int_address_q_reg[7]_i_2_n_1 ; wire \int_address_q_reg[7]_i_2_n_2 ; wire \int_address_q_reg[7]_i_2_n_3 ; wire \int_address_q_reg[7]_i_2_n_4 ; wire \int_address_q_reg[7]_i_2_n_5 ; wire \int_address_q_reg[7]_i_2_n_6 ; wire \int_address_q_reg[7]_i_2_n_7 ; wire [2:0]out; wire rst; wire [16:0]s_axi_awaddr; wire ui_clk; wire [3:0]\NLW_fb_xpos_q_reg[11]_i_1_CO_UNCONNECTED ; wire [3:1]\NLW_fb_xpos_q_reg[11]_i_1_O_UNCONNECTED ; wire [3:3]\NLW_fb_ypos_q_reg[8]_i_1_CO_UNCONNECTED ; wire [3:0]\NLW_int_address_q_reg[23]_i_1_CO_UNCONNECTED ; wire [3:1]\NLW_int_address_q_reg[23]_i_1_O_UNCONNECTED ; LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \FSM_sequential_write_state[2]_i_3 (.I0(s_axi_awaddr[12]), .I1(s_axi_awaddr[10]), .I2(s_axi_awaddr[15]), .I3(s_axi_awaddr[11]), .I4(s_axi_awaddr[14]), .I5(s_axi_awaddr[13]), .O(\FSM_sequential_write_state_reg[0] )); LUT6 #( .INIT(64'h000000005555555D)) \FSM_sequential_write_state[2]_i_4 (.I0(s_axi_awaddr[8]), .I1(\FSM_sequential_write_state[2]_i_6_n_0 ), .I2(s_axi_awaddr[6]), .I3(s_axi_awaddr[5]), .I4(s_axi_awaddr[7]), .I5(s_axi_awaddr[9]), .O(\FSM_sequential_write_state_reg[0]_0 )); LUT4 #( .INIT(16'h7FFF)) \FSM_sequential_write_state[2]_i_6 (.I0(s_axi_awaddr[2]), .I1(s_axi_awaddr[3]), .I2(s_axi_awaddr[4]), .I3(s_axi_awaddr[1]), .O(\FSM_sequential_write_state[2]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[11]_i_2 (.I0(fb_xpos_q_reg[11]), .O(\fb_xpos_q[11]_i_2_n_0 )); LUT5 #( .INIT(32'h00000004)) \fb_xpos_q[7]_i_1 (.I0(rst), .I1(out[2]), .I2(out[0]), .I3(out[1]), .I4(\fb_ypos_q[0]_i_3_n_0 ), .O(fb_xpos_q)); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_3 (.I0(fb_xpos_q_reg[10]), .O(\fb_xpos_q[7]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_4 (.I0(fb_xpos_q_reg[9]), .O(\fb_xpos_q[7]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_5 (.I0(fb_xpos_q_reg[8]), .O(\fb_xpos_q[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \fb_xpos_q[7]_i_6 (.I0(fb_xpos_q_reg[7]), .O(\fb_xpos_q[7]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[10] (.C(ui_clk), .CE(fb_xpos_q), .D(\fb_xpos_q_reg[7]_i_2_n_4 ), .Q(fb_xpos_q_reg[10]), .R(\fb_ypos_q[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[11] (.C(ui_clk), .CE(fb_xpos_q), .D(\fb_xpos_q_reg[11]_i_1_n_7 ), .Q(fb_xpos_q_reg[11]), .R(\fb_ypos_q[0]_i_1_n_0 )); CARRY4 \fb_xpos_q_reg[11]_i_1 (.CI(\fb_xpos_q_reg[7]_i_2_n_0 ), .CO(\NLW_fb_xpos_q_reg[11]_i_1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_fb_xpos_q_reg[11]_i_1_O_UNCONNECTED [3:1],\fb_xpos_q_reg[11]_i_1_n_7 }), .S({1'b0,1'b0,1'b0,\fb_xpos_q[11]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[7] (.C(ui_clk), .CE(fb_xpos_q), .D(\fb_xpos_q_reg[7]_i_2_n_7 ), .Q(fb_xpos_q_reg[7]), .R(\fb_ypos_q[0]_i_1_n_0 )); CARRY4 \fb_xpos_q_reg[7]_i_2 (.CI(1'b0), .CO({\fb_xpos_q_reg[7]_i_2_n_0 ,\fb_xpos_q_reg[7]_i_2_n_1 ,\fb_xpos_q_reg[7]_i_2_n_2 ,\fb_xpos_q_reg[7]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\fb_xpos_q_reg[7]_i_2_n_4 ,\fb_xpos_q_reg[7]_i_2_n_5 ,\fb_xpos_q_reg[7]_i_2_n_6 ,\fb_xpos_q_reg[7]_i_2_n_7 }), .S({\fb_xpos_q[7]_i_3_n_0 ,\fb_xpos_q[7]_i_4_n_0 ,\fb_xpos_q[7]_i_5_n_0 ,\fb_xpos_q[7]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[8] (.C(ui_clk), .CE(fb_xpos_q), .D(\fb_xpos_q_reg[7]_i_2_n_6 ), .Q(fb_xpos_q_reg[8]), .R(\fb_ypos_q[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[9] (.C(ui_clk), .CE(fb_xpos_q), .D(\fb_xpos_q_reg[7]_i_2_n_5 ), .Q(fb_xpos_q_reg[9]), .R(\fb_ypos_q[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000040000)) \fb_ypos_q[0]_i_1 (.I0(rst), .I1(out[2]), .I2(out[0]), .I3(out[1]), .I4(\fb_ypos_q[0]_i_3_n_0 ), .I5(\fb_ypos_q[0]_i_4_n_0 ), .O(\fb_ypos_q[0]_i_1_n_0 )); LUT5 #( .INIT(32'h00007FFF)) \fb_ypos_q[0]_i_10 (.I0(fb_ypos_q_reg[0]), .I1(fb_ypos_q_reg[1]), .I2(fb_ypos_q_reg[3]), .I3(fb_ypos_q_reg[2]), .I4(fb_ypos_q_reg[4]), .O(\fb_ypos_q[0]_i_10_n_0 )); LUT5 #( .INIT(32'hE0000000)) \fb_ypos_q[0]_i_3 (.I0(fb_xpos_q_reg[7]), .I1(fb_xpos_q_reg[8]), .I2(fb_xpos_q_reg[9]), .I3(fb_xpos_q_reg[10]), .I4(fb_xpos_q_reg[11]), .O(\fb_ypos_q[0]_i_3_n_0 )); LUT5 #( .INIT(32'h8A888888)) \fb_ypos_q[0]_i_4 (.I0(fb_ypos_q_reg[11]), .I1(\fb_ypos_q[0]_i_9_n_0 ), .I2(\fb_ypos_q[0]_i_10_n_0 ), .I3(fb_ypos_q_reg[5]), .I4(fb_ypos_q_reg[6]), .O(\fb_ypos_q[0]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[0]_i_5 (.I0(fb_ypos_q_reg[3]), .O(\fb_ypos_q[0]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[0]_i_6 (.I0(fb_ypos_q_reg[2]), .O(\fb_ypos_q[0]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[0]_i_7 (.I0(fb_ypos_q_reg[1]), .O(\fb_ypos_q[0]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \fb_ypos_q[0]_i_8 (.I0(fb_ypos_q_reg[0]), .O(\fb_ypos_q[0]_i_8_n_0 )); LUT4 #( .INIT(16'hFFFE)) \fb_ypos_q[0]_i_9 (.I0(fb_ypos_q_reg[7]), .I1(fb_ypos_q_reg[10]), .I2(fb_ypos_q_reg[9]), .I3(fb_ypos_q_reg[8]), .O(\fb_ypos_q[0]_i_9_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_2 (.I0(fb_ypos_q_reg[7]), .O(\fb_ypos_q[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_3 (.I0(fb_ypos_q_reg[6]), .O(\fb_ypos_q[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_4 (.I0(fb_ypos_q_reg[5]), .O(\fb_ypos_q[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_5 (.I0(fb_ypos_q_reg[4]), .O(\fb_ypos_q[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_2 (.I0(fb_ypos_q_reg[11]), .O(\fb_ypos_q[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_3 (.I0(fb_ypos_q_reg[10]), .O(\fb_ypos_q[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_4 (.I0(fb_ypos_q_reg[9]), .O(\fb_ypos_q[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_5 (.I0(fb_ypos_q_reg[8]), .O(\fb_ypos_q[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[0] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[0]_i_2_n_7 ), .Q(fb_ypos_q_reg[0]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[0]_i_2 (.CI(1'b0), .CO({\fb_ypos_q_reg[0]_i_2_n_0 ,\fb_ypos_q_reg[0]_i_2_n_1 ,\fb_ypos_q_reg[0]_i_2_n_2 ,\fb_ypos_q_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\fb_ypos_q_reg[0]_i_2_n_4 ,\fb_ypos_q_reg[0]_i_2_n_5 ,\fb_ypos_q_reg[0]_i_2_n_6 ,\fb_ypos_q_reg[0]_i_2_n_7 }), .S({\fb_ypos_q[0]_i_5_n_0 ,\fb_ypos_q[0]_i_6_n_0 ,\fb_ypos_q[0]_i_7_n_0 ,\fb_ypos_q[0]_i_8_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[10] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[8]_i_1_n_5 ), .Q(fb_ypos_q_reg[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[11] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[8]_i_1_n_4 ), .Q(fb_ypos_q_reg[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[1] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[0]_i_2_n_6 ), .Q(fb_ypos_q_reg[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[2] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[0]_i_2_n_5 ), .Q(fb_ypos_q_reg[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[3] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[0]_i_2_n_4 ), .Q(fb_ypos_q_reg[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[4] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[4]_i_1_n_7 ), .Q(fb_ypos_q_reg[4]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[4]_i_1 (.CI(\fb_ypos_q_reg[0]_i_2_n_0 ), .CO({\fb_ypos_q_reg[4]_i_1_n_0 ,\fb_ypos_q_reg[4]_i_1_n_1 ,\fb_ypos_q_reg[4]_i_1_n_2 ,\fb_ypos_q_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\fb_ypos_q_reg[4]_i_1_n_4 ,\fb_ypos_q_reg[4]_i_1_n_5 ,\fb_ypos_q_reg[4]_i_1_n_6 ,\fb_ypos_q_reg[4]_i_1_n_7 }), .S({\fb_ypos_q[4]_i_2_n_0 ,\fb_ypos_q[4]_i_3_n_0 ,\fb_ypos_q[4]_i_4_n_0 ,\fb_ypos_q[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[5] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[4]_i_1_n_6 ), .Q(fb_ypos_q_reg[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[6] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[4]_i_1_n_5 ), .Q(fb_ypos_q_reg[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[7] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[4]_i_1_n_4 ), .Q(fb_ypos_q_reg[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[8] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[8]_i_1_n_7 ), .Q(fb_ypos_q_reg[8]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[8]_i_1 (.CI(\fb_ypos_q_reg[4]_i_1_n_0 ), .CO({\NLW_fb_ypos_q_reg[8]_i_1_CO_UNCONNECTED [3],\fb_ypos_q_reg[8]_i_1_n_1 ,\fb_ypos_q_reg[8]_i_1_n_2 ,\fb_ypos_q_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\fb_ypos_q_reg[8]_i_1_n_4 ,\fb_ypos_q_reg[8]_i_1_n_5 ,\fb_ypos_q_reg[8]_i_1_n_6 ,\fb_ypos_q_reg[8]_i_1_n_7 }), .S({\fb_ypos_q[8]_i_2_n_0 ,\fb_ypos_q[8]_i_3_n_0 ,\fb_ypos_q[8]_i_4_n_0 ,\fb_ypos_q[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[9] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1_n_0 ), .D(\fb_ypos_q_reg[8]_i_1_n_6 ), .Q(fb_ypos_q_reg[9]), .R(1'b0)); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_2 (.I0(s_axi_awaddr[7]), .O(\int_address_q[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_3 (.I0(s_axi_awaddr[6]), .O(\int_address_q[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_4 (.I0(s_axi_awaddr[5]), .O(\int_address_q[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_5__0 (.I0(s_axi_awaddr[4]), .O(\int_address_q[11]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_2 (.I0(s_axi_awaddr[11]), .O(\int_address_q[15]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_3 (.I0(s_axi_awaddr[10]), .O(\int_address_q[15]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_4 (.I0(s_axi_awaddr[9]), .O(\int_address_q[15]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_5 (.I0(s_axi_awaddr[8]), .O(\int_address_q[15]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_2 (.I0(s_axi_awaddr[15]), .O(\int_address_q[19]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_3 (.I0(s_axi_awaddr[14]), .O(\int_address_q[19]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_4 (.I0(s_axi_awaddr[13]), .O(\int_address_q[19]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_5 (.I0(s_axi_awaddr[12]), .O(\int_address_q[19]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[23]_i_2 (.I0(s_axi_awaddr[16]), .O(\int_address_q[23]_i_2_n_0 )); LUT5 #( .INIT(32'h00101010)) \int_address_q[7]_i_1 (.I0(out[1]), .I1(out[0]), .I2(out[2]), .I3(\fb_ypos_q[0]_i_3_n_0 ), .I4(\fb_ypos_q[0]_i_4_n_0 ), .O(int_address_q)); LUT1 #( .INIT(2'h2)) \int_address_q[7]_i_3__0 (.I0(s_axi_awaddr[3]), .O(\int_address_q[7]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[7]_i_4__0 (.I0(s_axi_awaddr[2]), .O(\int_address_q[7]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[7]_i_5__0 (.I0(s_axi_awaddr[1]), .O(\int_address_q[7]_i_5__0_n_0 )); LUT1 #( .INIT(2'h1)) \int_address_q[7]_i_6 (.I0(s_axi_awaddr[0]), .O(\int_address_q[7]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \int_address_q_reg[10] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2_n_4 ), .Q(s_axi_awaddr[3]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[11] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1_n_7 ), .Q(s_axi_awaddr[4]), .R(rst)); CARRY4 \int_address_q_reg[11]_i_1 (.CI(\int_address_q_reg[7]_i_2_n_0 ), .CO({\int_address_q_reg[11]_i_1_n_0 ,\int_address_q_reg[11]_i_1_n_1 ,\int_address_q_reg[11]_i_1_n_2 ,\int_address_q_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[11]_i_1_n_4 ,\int_address_q_reg[11]_i_1_n_5 ,\int_address_q_reg[11]_i_1_n_6 ,\int_address_q_reg[11]_i_1_n_7 }), .S({\int_address_q[11]_i_2_n_0 ,\int_address_q[11]_i_3_n_0 ,\int_address_q[11]_i_4_n_0 ,\int_address_q[11]_i_5__0_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[12] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1_n_6 ), .Q(s_axi_awaddr[5]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[13] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1_n_5 ), .Q(s_axi_awaddr[6]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[14] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1_n_4 ), .Q(s_axi_awaddr[7]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[15] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1_n_7 ), .Q(s_axi_awaddr[8]), .R(rst)); CARRY4 \int_address_q_reg[15]_i_1 (.CI(\int_address_q_reg[11]_i_1_n_0 ), .CO({\int_address_q_reg[15]_i_1_n_0 ,\int_address_q_reg[15]_i_1_n_1 ,\int_address_q_reg[15]_i_1_n_2 ,\int_address_q_reg[15]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[15]_i_1_n_4 ,\int_address_q_reg[15]_i_1_n_5 ,\int_address_q_reg[15]_i_1_n_6 ,\int_address_q_reg[15]_i_1_n_7 }), .S({\int_address_q[15]_i_2_n_0 ,\int_address_q[15]_i_3_n_0 ,\int_address_q[15]_i_4_n_0 ,\int_address_q[15]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[16] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1_n_6 ), .Q(s_axi_awaddr[9]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[17] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1_n_5 ), .Q(s_axi_awaddr[10]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[18] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1_n_4 ), .Q(s_axi_awaddr[11]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[19] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1_n_7 ), .Q(s_axi_awaddr[12]), .R(rst)); CARRY4 \int_address_q_reg[19]_i_1 (.CI(\int_address_q_reg[15]_i_1_n_0 ), .CO({\int_address_q_reg[19]_i_1_n_0 ,\int_address_q_reg[19]_i_1_n_1 ,\int_address_q_reg[19]_i_1_n_2 ,\int_address_q_reg[19]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[19]_i_1_n_4 ,\int_address_q_reg[19]_i_1_n_5 ,\int_address_q_reg[19]_i_1_n_6 ,\int_address_q_reg[19]_i_1_n_7 }), .S({\int_address_q[19]_i_2_n_0 ,\int_address_q[19]_i_3_n_0 ,\int_address_q[19]_i_4_n_0 ,\int_address_q[19]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[20] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1_n_6 ), .Q(s_axi_awaddr[13]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[21] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1_n_5 ), .Q(s_axi_awaddr[14]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[22] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1_n_4 ), .Q(s_axi_awaddr[15]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[23] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[23]_i_1_n_7 ), .Q(s_axi_awaddr[16]), .R(rst)); CARRY4 \int_address_q_reg[23]_i_1 (.CI(\int_address_q_reg[19]_i_1_n_0 ), .CO(\NLW_int_address_q_reg[23]_i_1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_int_address_q_reg[23]_i_1_O_UNCONNECTED [3:1],\int_address_q_reg[23]_i_1_n_7 }), .S({1'b0,1'b0,1'b0,\int_address_q[23]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[7] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2_n_7 ), .Q(s_axi_awaddr[0]), .R(rst)); CARRY4 \int_address_q_reg[7]_i_2 (.CI(1'b0), .CO({\int_address_q_reg[7]_i_2_n_0 ,\int_address_q_reg[7]_i_2_n_1 ,\int_address_q_reg[7]_i_2_n_2 ,\int_address_q_reg[7]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\int_address_q_reg[7]_i_2_n_4 ,\int_address_q_reg[7]_i_2_n_5 ,\int_address_q_reg[7]_i_2_n_6 ,\int_address_q_reg[7]_i_2_n_7 }), .S({\int_address_q[7]_i_3__0_n_0 ,\int_address_q[7]_i_4__0_n_0 ,\int_address_q[7]_i_5__0_n_0 ,\int_address_q[7]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[8] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2_n_6 ), .Q(s_axi_awaddr[1]), .R(rst)); FDRE #( .INIT(1'b0)) \int_address_q_reg[9] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2_n_5 ), .Q(s_axi_awaddr[2]), .R(rst)); endmodule (* ORIG_REF_NAME = "framebuffer_addr_ctrl" *) module framebuffer_addr_ctrl__parameterized0 (int_address_q_reg, \read_state_reg[0] , ui_clk, \v_pos_reg[4] , Q, zoom_mode_IBUF, prog_full); output [16:0]int_address_q_reg; output \read_state_reg[0] ; input ui_clk; input \v_pos_reg[4] ; input [1:0]Q; input zoom_mode_IBUF; input prog_full; wire [1:0]Q; wire \fb_xpos_q[11]_i_2__0_n_0 ; wire \fb_xpos_q[7]_i_1__1_n_0 ; wire \fb_xpos_q[7]_i_3__0_n_0 ; wire \fb_xpos_q[7]_i_4__0_n_0 ; wire \fb_xpos_q[7]_i_5__0_n_0 ; wire \fb_xpos_q[7]_i_6__0_n_0 ; wire [11:7]fb_xpos_q_reg; wire \fb_xpos_q_reg[11]_i_1__0_n_7 ; wire \fb_xpos_q_reg[7]_i_2__0_n_0 ; wire \fb_xpos_q_reg[7]_i_2__0_n_1 ; wire \fb_xpos_q_reg[7]_i_2__0_n_2 ; wire \fb_xpos_q_reg[7]_i_2__0_n_3 ; wire \fb_xpos_q_reg[7]_i_2__0_n_4 ; wire \fb_xpos_q_reg[7]_i_2__0_n_5 ; wire \fb_xpos_q_reg[7]_i_2__0_n_6 ; wire \fb_xpos_q_reg[7]_i_2__0_n_7 ; wire \fb_ypos_q[1]_i_1_n_0 ; wire \fb_ypos_q[1]_i_3_n_0 ; wire \fb_ypos_q[1]_i_4_n_0 ; wire \fb_ypos_q[1]_i_5_n_0 ; wire \fb_ypos_q[1]_i_6_n_0 ; wire \fb_ypos_q[1]_i_7_n_0 ; wire \fb_ypos_q[1]_i_8_n_0 ; wire \fb_ypos_q[1]_i_9_n_0 ; wire \fb_ypos_q[5]_i_2_n_0 ; wire \fb_ypos_q[5]_i_3_n_0 ; wire \fb_ypos_q[5]_i_4_n_0 ; wire \fb_ypos_q[5]_i_5_n_0 ; wire \fb_ypos_q[9]_i_2_n_0 ; wire \fb_ypos_q[9]_i_3_n_0 ; wire \fb_ypos_q[9]_i_4_n_0 ; wire [11:1]fb_ypos_q_reg; wire \fb_ypos_q_reg[1]_i_2_n_0 ; wire \fb_ypos_q_reg[1]_i_2_n_1 ; wire \fb_ypos_q_reg[1]_i_2_n_2 ; wire \fb_ypos_q_reg[1]_i_2_n_3 ; wire \fb_ypos_q_reg[1]_i_2_n_4 ; wire \fb_ypos_q_reg[1]_i_2_n_5 ; wire \fb_ypos_q_reg[1]_i_2_n_6 ; wire \fb_ypos_q_reg[1]_i_2_n_7 ; wire \fb_ypos_q_reg[5]_i_1_n_0 ; wire \fb_ypos_q_reg[5]_i_1_n_1 ; wire \fb_ypos_q_reg[5]_i_1_n_2 ; wire \fb_ypos_q_reg[5]_i_1_n_3 ; wire \fb_ypos_q_reg[5]_i_1_n_4 ; wire \fb_ypos_q_reg[5]_i_1_n_5 ; wire \fb_ypos_q_reg[5]_i_1_n_6 ; wire \fb_ypos_q_reg[5]_i_1_n_7 ; wire \fb_ypos_q_reg[9]_i_1_n_2 ; wire \fb_ypos_q_reg[9]_i_1_n_3 ; wire \fb_ypos_q_reg[9]_i_1_n_5 ; wire \fb_ypos_q_reg[9]_i_1_n_6 ; wire \fb_ypos_q_reg[9]_i_1_n_7 ; wire int_address_q; wire \int_address_q[11]_i_2__0_n_0 ; wire \int_address_q[11]_i_3__0_n_0 ; wire \int_address_q[11]_i_4__0_n_0 ; wire \int_address_q[11]_i_5_n_0 ; wire \int_address_q[15]_i_2__0_n_0 ; wire \int_address_q[15]_i_3__0_n_0 ; wire \int_address_q[15]_i_4__0_n_0 ; wire \int_address_q[15]_i_5__0_n_0 ; wire \int_address_q[19]_i_2__0_n_0 ; wire \int_address_q[19]_i_3__0_n_0 ; wire \int_address_q[19]_i_4__0_n_0 ; wire \int_address_q[19]_i_5__0_n_0 ; wire \int_address_q[23]_i_2__0_n_0 ; wire \int_address_q[7]_i_3_n_0 ; wire \int_address_q[7]_i_4_n_0 ; wire \int_address_q[7]_i_5_n_0 ; wire \int_address_q[7]_i_6__0_n_0 ; wire [16:0]int_address_q_reg; wire \int_address_q_reg[11]_i_1__0_n_0 ; wire \int_address_q_reg[11]_i_1__0_n_1 ; wire \int_address_q_reg[11]_i_1__0_n_2 ; wire \int_address_q_reg[11]_i_1__0_n_3 ; wire \int_address_q_reg[11]_i_1__0_n_4 ; wire \int_address_q_reg[11]_i_1__0_n_5 ; wire \int_address_q_reg[11]_i_1__0_n_6 ; wire \int_address_q_reg[11]_i_1__0_n_7 ; wire \int_address_q_reg[15]_i_1__0_n_0 ; wire \int_address_q_reg[15]_i_1__0_n_1 ; wire \int_address_q_reg[15]_i_1__0_n_2 ; wire \int_address_q_reg[15]_i_1__0_n_3 ; wire \int_address_q_reg[15]_i_1__0_n_4 ; wire \int_address_q_reg[15]_i_1__0_n_5 ; wire \int_address_q_reg[15]_i_1__0_n_6 ; wire \int_address_q_reg[15]_i_1__0_n_7 ; wire \int_address_q_reg[19]_i_1__0_n_0 ; wire \int_address_q_reg[19]_i_1__0_n_1 ; wire \int_address_q_reg[19]_i_1__0_n_2 ; wire \int_address_q_reg[19]_i_1__0_n_3 ; wire \int_address_q_reg[19]_i_1__0_n_4 ; wire \int_address_q_reg[19]_i_1__0_n_5 ; wire \int_address_q_reg[19]_i_1__0_n_6 ; wire \int_address_q_reg[19]_i_1__0_n_7 ; wire \int_address_q_reg[23]_i_1__0_n_7 ; wire \int_address_q_reg[7]_i_2__0_n_0 ; wire \int_address_q_reg[7]_i_2__0_n_1 ; wire \int_address_q_reg[7]_i_2__0_n_2 ; wire \int_address_q_reg[7]_i_2__0_n_3 ; wire \int_address_q_reg[7]_i_2__0_n_4 ; wire \int_address_q_reg[7]_i_2__0_n_5 ; wire \int_address_q_reg[7]_i_2__0_n_6 ; wire \int_address_q_reg[7]_i_2__0_n_7 ; wire prog_full; wire \read_state[1]_i_8_n_0 ; wire \read_state[1]_i_9_n_0 ; wire \read_state_reg[0] ; wire ui_clk; wire \v_pos_reg[4] ; wire zoom_mode_IBUF; wire [3:0]\NLW_fb_xpos_q_reg[11]_i_1__0_CO_UNCONNECTED ; wire [3:1]\NLW_fb_xpos_q_reg[11]_i_1__0_O_UNCONNECTED ; wire [3:2]\NLW_fb_ypos_q_reg[9]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_fb_ypos_q_reg[9]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_int_address_q_reg[23]_i_1__0_CO_UNCONNECTED ; wire [3:1]\NLW_int_address_q_reg[23]_i_1__0_O_UNCONNECTED ; LUT1 #( .INIT(2'h2)) \fb_xpos_q[11]_i_2__0 (.I0(fb_xpos_q_reg[11]), .O(\fb_xpos_q[11]_i_2__0_n_0 )); LUT4 #( .INIT(16'h0040)) \fb_xpos_q[7]_i_1__1 (.I0(\fb_ypos_q[1]_i_3_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(\v_pos_reg[4] ), .O(\fb_xpos_q[7]_i_1__1_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_3__0 (.I0(fb_xpos_q_reg[10]), .O(\fb_xpos_q[7]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_4__0 (.I0(fb_xpos_q_reg[9]), .O(\fb_xpos_q[7]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_5__0 (.I0(fb_xpos_q_reg[8]), .O(\fb_xpos_q[7]_i_5__0_n_0 )); LUT1 #( .INIT(2'h1)) \fb_xpos_q[7]_i_6__0 (.I0(fb_xpos_q_reg[7]), .O(\fb_xpos_q[7]_i_6__0_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[10] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__1_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__0_n_4 ), .Q(fb_xpos_q_reg[10]), .R(\fb_ypos_q[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[11] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__1_n_0 ), .D(\fb_xpos_q_reg[11]_i_1__0_n_7 ), .Q(fb_xpos_q_reg[11]), .R(\fb_ypos_q[1]_i_1_n_0 )); CARRY4 \fb_xpos_q_reg[11]_i_1__0 (.CI(\fb_xpos_q_reg[7]_i_2__0_n_0 ), .CO(\NLW_fb_xpos_q_reg[11]_i_1__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_fb_xpos_q_reg[11]_i_1__0_O_UNCONNECTED [3:1],\fb_xpos_q_reg[11]_i_1__0_n_7 }), .S({1'b0,1'b0,1'b0,\fb_xpos_q[11]_i_2__0_n_0 })); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[7] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__1_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__0_n_7 ), .Q(fb_xpos_q_reg[7]), .R(\fb_ypos_q[1]_i_1_n_0 )); CARRY4 \fb_xpos_q_reg[7]_i_2__0 (.CI(1'b0), .CO({\fb_xpos_q_reg[7]_i_2__0_n_0 ,\fb_xpos_q_reg[7]_i_2__0_n_1 ,\fb_xpos_q_reg[7]_i_2__0_n_2 ,\fb_xpos_q_reg[7]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\fb_xpos_q_reg[7]_i_2__0_n_4 ,\fb_xpos_q_reg[7]_i_2__0_n_5 ,\fb_xpos_q_reg[7]_i_2__0_n_6 ,\fb_xpos_q_reg[7]_i_2__0_n_7 }), .S({\fb_xpos_q[7]_i_3__0_n_0 ,\fb_xpos_q[7]_i_4__0_n_0 ,\fb_xpos_q[7]_i_5__0_n_0 ,\fb_xpos_q[7]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[8] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__1_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__0_n_6 ), .Q(fb_xpos_q_reg[8]), .R(\fb_ypos_q[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[9] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__1_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__0_n_5 ), .Q(fb_xpos_q_reg[9]), .R(\fb_ypos_q[1]_i_1_n_0 )); LUT5 #( .INIT(32'h00000800)) \fb_ypos_q[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(\v_pos_reg[4] ), .I3(\fb_ypos_q[1]_i_3_n_0 ), .I4(\fb_ypos_q[1]_i_4_n_0 ), .O(\fb_ypos_q[1]_i_1_n_0 )); LUT5 #( .INIT(32'hE0000000)) \fb_ypos_q[1]_i_3 (.I0(fb_xpos_q_reg[7]), .I1(fb_xpos_q_reg[8]), .I2(fb_xpos_q_reg[9]), .I3(fb_xpos_q_reg[10]), .I4(fb_xpos_q_reg[11]), .O(\fb_ypos_q[1]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAA8AAAAAAAA)) \fb_ypos_q[1]_i_4 (.I0(fb_ypos_q_reg[11]), .I1(fb_ypos_q_reg[8]), .I2(fb_ypos_q_reg[7]), .I3(fb_ypos_q_reg[9]), .I4(fb_ypos_q_reg[10]), .I5(\fb_ypos_q[1]_i_9_n_0 ), .O(\fb_ypos_q[1]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[1]_i_5 (.I0(fb_ypos_q_reg[4]), .O(\fb_ypos_q[1]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[1]_i_6 (.I0(fb_ypos_q_reg[3]), .O(\fb_ypos_q[1]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[1]_i_7 (.I0(fb_ypos_q_reg[2]), .O(\fb_ypos_q[1]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \fb_ypos_q[1]_i_8 (.I0(fb_ypos_q_reg[1]), .O(\fb_ypos_q[1]_i_8_n_0 )); LUT6 #( .INIT(64'h1555FFFFFFFFFFFF)) \fb_ypos_q[1]_i_9 (.I0(fb_ypos_q_reg[4]), .I1(fb_ypos_q_reg[1]), .I2(fb_ypos_q_reg[2]), .I3(fb_ypos_q_reg[3]), .I4(fb_ypos_q_reg[5]), .I5(fb_ypos_q_reg[6]), .O(\fb_ypos_q[1]_i_9_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[5]_i_2 (.I0(fb_ypos_q_reg[8]), .O(\fb_ypos_q[5]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[5]_i_3 (.I0(fb_ypos_q_reg[7]), .O(\fb_ypos_q[5]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[5]_i_4 (.I0(fb_ypos_q_reg[6]), .O(\fb_ypos_q[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[5]_i_5 (.I0(fb_ypos_q_reg[5]), .O(\fb_ypos_q[5]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[9]_i_2 (.I0(fb_ypos_q_reg[11]), .O(\fb_ypos_q[9]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[9]_i_3 (.I0(fb_ypos_q_reg[10]), .O(\fb_ypos_q[9]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[9]_i_4 (.I0(fb_ypos_q_reg[9]), .O(\fb_ypos_q[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[10] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[9]_i_1_n_6 ), .Q(fb_ypos_q_reg[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[11] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[9]_i_1_n_5 ), .Q(fb_ypos_q_reg[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[1] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[1]_i_2_n_7 ), .Q(fb_ypos_q_reg[1]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[1]_i_2 (.CI(1'b0), .CO({\fb_ypos_q_reg[1]_i_2_n_0 ,\fb_ypos_q_reg[1]_i_2_n_1 ,\fb_ypos_q_reg[1]_i_2_n_2 ,\fb_ypos_q_reg[1]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\fb_ypos_q_reg[1]_i_2_n_4 ,\fb_ypos_q_reg[1]_i_2_n_5 ,\fb_ypos_q_reg[1]_i_2_n_6 ,\fb_ypos_q_reg[1]_i_2_n_7 }), .S({\fb_ypos_q[1]_i_5_n_0 ,\fb_ypos_q[1]_i_6_n_0 ,\fb_ypos_q[1]_i_7_n_0 ,\fb_ypos_q[1]_i_8_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[2] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[1]_i_2_n_6 ), .Q(fb_ypos_q_reg[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[3] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[1]_i_2_n_5 ), .Q(fb_ypos_q_reg[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[4] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[1]_i_2_n_4 ), .Q(fb_ypos_q_reg[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[5] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[5]_i_1_n_7 ), .Q(fb_ypos_q_reg[5]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[5]_i_1 (.CI(\fb_ypos_q_reg[1]_i_2_n_0 ), .CO({\fb_ypos_q_reg[5]_i_1_n_0 ,\fb_ypos_q_reg[5]_i_1_n_1 ,\fb_ypos_q_reg[5]_i_1_n_2 ,\fb_ypos_q_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\fb_ypos_q_reg[5]_i_1_n_4 ,\fb_ypos_q_reg[5]_i_1_n_5 ,\fb_ypos_q_reg[5]_i_1_n_6 ,\fb_ypos_q_reg[5]_i_1_n_7 }), .S({\fb_ypos_q[5]_i_2_n_0 ,\fb_ypos_q[5]_i_3_n_0 ,\fb_ypos_q[5]_i_4_n_0 ,\fb_ypos_q[5]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[6] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[5]_i_1_n_6 ), .Q(fb_ypos_q_reg[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[7] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[5]_i_1_n_5 ), .Q(fb_ypos_q_reg[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[8] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[5]_i_1_n_4 ), .Q(fb_ypos_q_reg[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[9] (.C(ui_clk), .CE(\fb_ypos_q[1]_i_1_n_0 ), .D(\fb_ypos_q_reg[9]_i_1_n_7 ), .Q(fb_ypos_q_reg[9]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[9]_i_1 (.CI(\fb_ypos_q_reg[5]_i_1_n_0 ), .CO({\NLW_fb_ypos_q_reg[9]_i_1_CO_UNCONNECTED [3:2],\fb_ypos_q_reg[9]_i_1_n_2 ,\fb_ypos_q_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_fb_ypos_q_reg[9]_i_1_O_UNCONNECTED [3],\fb_ypos_q_reg[9]_i_1_n_5 ,\fb_ypos_q_reg[9]_i_1_n_6 ,\fb_ypos_q_reg[9]_i_1_n_7 }), .S({1'b0,\fb_ypos_q[9]_i_2_n_0 ,\fb_ypos_q[9]_i_3_n_0 ,\fb_ypos_q[9]_i_4_n_0 })); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_2__0 (.I0(int_address_q_reg[7]), .O(\int_address_q[11]_i_2__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_3__0 (.I0(int_address_q_reg[6]), .O(\int_address_q[11]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[11]_i_4__0 (.I0(int_address_q_reg[5]), .O(\int_address_q[11]_i_4__0_n_0 )); LUT6 #( .INIT(64'h7F7F7FFF80808000)) \int_address_q[11]_i_5 (.I0(fb_xpos_q_reg[11]), .I1(fb_xpos_q_reg[10]), .I2(fb_xpos_q_reg[9]), .I3(fb_xpos_q_reg[8]), .I4(fb_xpos_q_reg[7]), .I5(int_address_q_reg[4]), .O(\int_address_q[11]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_2__0 (.I0(int_address_q_reg[11]), .O(\int_address_q[15]_i_2__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_3__0 (.I0(int_address_q_reg[10]), .O(\int_address_q[15]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_4__0 (.I0(int_address_q_reg[9]), .O(\int_address_q[15]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[15]_i_5__0 (.I0(int_address_q_reg[8]), .O(\int_address_q[15]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_2__0 (.I0(int_address_q_reg[15]), .O(\int_address_q[19]_i_2__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_3__0 (.I0(int_address_q_reg[14]), .O(\int_address_q[19]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_4__0 (.I0(int_address_q_reg[13]), .O(\int_address_q[19]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[19]_i_5__0 (.I0(int_address_q_reg[12]), .O(\int_address_q[19]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[23]_i_2__0 (.I0(int_address_q_reg[16]), .O(\int_address_q[23]_i_2__0_n_0 )); LUT4 #( .INIT(16'h0888)) \int_address_q[7]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(\fb_ypos_q[1]_i_3_n_0 ), .I3(\fb_ypos_q[1]_i_4_n_0 ), .O(int_address_q)); LUT6 #( .INIT(64'h7F7F7FFF80808000)) \int_address_q[7]_i_3 (.I0(fb_xpos_q_reg[11]), .I1(fb_xpos_q_reg[10]), .I2(fb_xpos_q_reg[9]), .I3(fb_xpos_q_reg[8]), .I4(fb_xpos_q_reg[7]), .I5(int_address_q_reg[3]), .O(\int_address_q[7]_i_3_n_0 )); LUT6 #( .INIT(64'h7F7F7FFF80808000)) \int_address_q[7]_i_4 (.I0(fb_xpos_q_reg[11]), .I1(fb_xpos_q_reg[10]), .I2(fb_xpos_q_reg[9]), .I3(fb_xpos_q_reg[8]), .I4(fb_xpos_q_reg[7]), .I5(int_address_q_reg[2]), .O(\int_address_q[7]_i_4_n_0 )); LUT6 #( .INIT(64'h7F7F7FFF80808000)) \int_address_q[7]_i_5 (.I0(fb_xpos_q_reg[11]), .I1(fb_xpos_q_reg[10]), .I2(fb_xpos_q_reg[9]), .I3(fb_xpos_q_reg[8]), .I4(fb_xpos_q_reg[7]), .I5(int_address_q_reg[1]), .O(\int_address_q[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \int_address_q[7]_i_6__0 (.I0(int_address_q_reg[0]), .O(\int_address_q[7]_i_6__0_n_0 )); FDRE #( .INIT(1'b0)) \int_address_q_reg[10] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2__0_n_4 ), .Q(int_address_q_reg[3]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[11] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1__0_n_7 ), .Q(int_address_q_reg[4]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[11]_i_1__0 (.CI(\int_address_q_reg[7]_i_2__0_n_0 ), .CO({\int_address_q_reg[11]_i_1__0_n_0 ,\int_address_q_reg[11]_i_1__0_n_1 ,\int_address_q_reg[11]_i_1__0_n_2 ,\int_address_q_reg[11]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\fb_ypos_q[1]_i_3_n_0 }), .O({\int_address_q_reg[11]_i_1__0_n_4 ,\int_address_q_reg[11]_i_1__0_n_5 ,\int_address_q_reg[11]_i_1__0_n_6 ,\int_address_q_reg[11]_i_1__0_n_7 }), .S({\int_address_q[11]_i_2__0_n_0 ,\int_address_q[11]_i_3__0_n_0 ,\int_address_q[11]_i_4__0_n_0 ,\int_address_q[11]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[12] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1__0_n_6 ), .Q(int_address_q_reg[5]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[13] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1__0_n_5 ), .Q(int_address_q_reg[6]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[14] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[11]_i_1__0_n_4 ), .Q(int_address_q_reg[7]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[15] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1__0_n_7 ), .Q(int_address_q_reg[8]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[15]_i_1__0 (.CI(\int_address_q_reg[11]_i_1__0_n_0 ), .CO({\int_address_q_reg[15]_i_1__0_n_0 ,\int_address_q_reg[15]_i_1__0_n_1 ,\int_address_q_reg[15]_i_1__0_n_2 ,\int_address_q_reg[15]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[15]_i_1__0_n_4 ,\int_address_q_reg[15]_i_1__0_n_5 ,\int_address_q_reg[15]_i_1__0_n_6 ,\int_address_q_reg[15]_i_1__0_n_7 }), .S({\int_address_q[15]_i_2__0_n_0 ,\int_address_q[15]_i_3__0_n_0 ,\int_address_q[15]_i_4__0_n_0 ,\int_address_q[15]_i_5__0_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[16] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1__0_n_6 ), .Q(int_address_q_reg[9]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[17] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1__0_n_5 ), .Q(int_address_q_reg[10]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[18] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[15]_i_1__0_n_4 ), .Q(int_address_q_reg[11]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[19] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1__0_n_7 ), .Q(int_address_q_reg[12]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[19]_i_1__0 (.CI(\int_address_q_reg[15]_i_1__0_n_0 ), .CO({\int_address_q_reg[19]_i_1__0_n_0 ,\int_address_q_reg[19]_i_1__0_n_1 ,\int_address_q_reg[19]_i_1__0_n_2 ,\int_address_q_reg[19]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[19]_i_1__0_n_4 ,\int_address_q_reg[19]_i_1__0_n_5 ,\int_address_q_reg[19]_i_1__0_n_6 ,\int_address_q_reg[19]_i_1__0_n_7 }), .S({\int_address_q[19]_i_2__0_n_0 ,\int_address_q[19]_i_3__0_n_0 ,\int_address_q[19]_i_4__0_n_0 ,\int_address_q[19]_i_5__0_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[20] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1__0_n_6 ), .Q(int_address_q_reg[13]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[21] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1__0_n_5 ), .Q(int_address_q_reg[14]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[22] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[19]_i_1__0_n_4 ), .Q(int_address_q_reg[15]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[23] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[23]_i_1__0_n_7 ), .Q(int_address_q_reg[16]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[23]_i_1__0 (.CI(\int_address_q_reg[19]_i_1__0_n_0 ), .CO(\NLW_int_address_q_reg[23]_i_1__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_int_address_q_reg[23]_i_1__0_O_UNCONNECTED [3:1],\int_address_q_reg[23]_i_1__0_n_7 }), .S({1'b0,1'b0,1'b0,\int_address_q[23]_i_2__0_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[7] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2__0_n_7 ), .Q(int_address_q_reg[0]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[7]_i_2__0 (.CI(1'b0), .CO({\int_address_q_reg[7]_i_2__0_n_0 ,\int_address_q_reg[7]_i_2__0_n_1 ,\int_address_q_reg[7]_i_2__0_n_2 ,\int_address_q_reg[7]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({\fb_ypos_q[1]_i_3_n_0 ,\fb_ypos_q[1]_i_3_n_0 ,\fb_ypos_q[1]_i_3_n_0 ,1'b1}), .O({\int_address_q_reg[7]_i_2__0_n_4 ,\int_address_q_reg[7]_i_2__0_n_5 ,\int_address_q_reg[7]_i_2__0_n_6 ,\int_address_q_reg[7]_i_2__0_n_7 }), .S({\int_address_q[7]_i_3_n_0 ,\int_address_q[7]_i_4_n_0 ,\int_address_q[7]_i_5_n_0 ,\int_address_q[7]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[8] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2__0_n_6 ), .Q(int_address_q_reg[1]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[9] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[7]_i_2__0_n_5 ), .Q(int_address_q_reg[2]), .R(\v_pos_reg[4] )); LUT5 #( .INIT(32'hFFFF0054)) \read_state[1]_i_4 (.I0(\read_state[1]_i_8_n_0 ), .I1(int_address_q_reg[8]), .I2(int_address_q_reg[9]), .I3(zoom_mode_IBUF), .I4(\read_state[1]_i_9_n_0 ), .O(\read_state_reg[0] )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \read_state[1]_i_8 (.I0(int_address_q_reg[14]), .I1(int_address_q_reg[10]), .I2(int_address_q_reg[12]), .I3(int_address_q_reg[15]), .I4(int_address_q_reg[11]), .I5(int_address_q_reg[13]), .O(\read_state[1]_i_8_n_0 )); LUT4 #( .INIT(16'hFFF4)) \read_state[1]_i_9 (.I0(zoom_mode_IBUF), .I1(int_address_q_reg[16]), .I2(prog_full), .I3(Q[1]), .O(\read_state[1]_i_9_n_0 )); endmodule (* ORIG_REF_NAME = "framebuffer_addr_ctrl" *) module framebuffer_addr_ctrl__parameterized1 (E, s_axi_araddr, ui_clk, \v_pos_reg[4] , Q, \read_state_reg[1] , \int_address_q_reg[15]_0 , \read_state_reg[1]_0 , zoom_mode_IBUF, int_address_q_reg); output [0:0]E; output [17:0]s_axi_araddr; input ui_clk; input \v_pos_reg[4] ; input [1:0]Q; input \read_state_reg[1] ; input \int_address_q_reg[15]_0 ; input \read_state_reg[1]_0 ; input zoom_mode_IBUF; input [16:0]int_address_q_reg; wire [0:0]E; wire [1:0]Q; wire \fb_xpos_q[11]_i_2__1_n_0 ; wire \fb_xpos_q[7]_i_1__0_n_0 ; wire \fb_xpos_q[7]_i_3__1_n_0 ; wire \fb_xpos_q[7]_i_4__1_n_0 ; wire \fb_xpos_q[7]_i_5__1_n_0 ; wire \fb_xpos_q[7]_i_6__1_n_0 ; wire [11:7]fb_xpos_q_reg; wire \fb_xpos_q_reg[11]_i_1__1_n_7 ; wire \fb_xpos_q_reg[7]_i_2__1_n_0 ; wire \fb_xpos_q_reg[7]_i_2__1_n_1 ; wire \fb_xpos_q_reg[7]_i_2__1_n_2 ; wire \fb_xpos_q_reg[7]_i_2__1_n_3 ; wire \fb_xpos_q_reg[7]_i_2__1_n_4 ; wire \fb_xpos_q_reg[7]_i_2__1_n_5 ; wire \fb_xpos_q_reg[7]_i_2__1_n_6 ; wire \fb_xpos_q_reg[7]_i_2__1_n_7 ; wire \fb_ypos_q[0]_i_10__0_n_0 ; wire \fb_ypos_q[0]_i_1__0_n_0 ; wire \fb_ypos_q[0]_i_3__0_n_0 ; wire \fb_ypos_q[0]_i_4__0_n_0 ; wire \fb_ypos_q[0]_i_5__0_n_0 ; wire \fb_ypos_q[0]_i_6__0_n_0 ; wire \fb_ypos_q[0]_i_7__0_n_0 ; wire \fb_ypos_q[0]_i_8__0_n_0 ; wire \fb_ypos_q[0]_i_9__0_n_0 ; wire \fb_ypos_q[4]_i_2__0_n_0 ; wire \fb_ypos_q[4]_i_3__0_n_0 ; wire \fb_ypos_q[4]_i_4__0_n_0 ; wire \fb_ypos_q[4]_i_5__0_n_0 ; wire \fb_ypos_q[8]_i_2__0_n_0 ; wire \fb_ypos_q[8]_i_3__0_n_0 ; wire \fb_ypos_q[8]_i_4__0_n_0 ; wire \fb_ypos_q[8]_i_5__0_n_0 ; wire [11:0]fb_ypos_q_reg; wire \fb_ypos_q_reg[0]_i_2__0_n_0 ; wire \fb_ypos_q_reg[0]_i_2__0_n_1 ; wire \fb_ypos_q_reg[0]_i_2__0_n_2 ; wire \fb_ypos_q_reg[0]_i_2__0_n_3 ; wire \fb_ypos_q_reg[0]_i_2__0_n_4 ; wire \fb_ypos_q_reg[0]_i_2__0_n_5 ; wire \fb_ypos_q_reg[0]_i_2__0_n_6 ; wire \fb_ypos_q_reg[0]_i_2__0_n_7 ; wire \fb_ypos_q_reg[4]_i_1__0_n_0 ; wire \fb_ypos_q_reg[4]_i_1__0_n_1 ; wire \fb_ypos_q_reg[4]_i_1__0_n_2 ; wire \fb_ypos_q_reg[4]_i_1__0_n_3 ; wire \fb_ypos_q_reg[4]_i_1__0_n_4 ; wire \fb_ypos_q_reg[4]_i_1__0_n_5 ; wire \fb_ypos_q_reg[4]_i_1__0_n_6 ; wire \fb_ypos_q_reg[4]_i_1__0_n_7 ; wire \fb_ypos_q_reg[8]_i_1__0_n_1 ; wire \fb_ypos_q_reg[8]_i_1__0_n_2 ; wire \fb_ypos_q_reg[8]_i_1__0_n_3 ; wire \fb_ypos_q_reg[8]_i_1__0_n_4 ; wire \fb_ypos_q_reg[8]_i_1__0_n_5 ; wire \fb_ypos_q_reg[8]_i_1__0_n_6 ; wire \fb_ypos_q_reg[8]_i_1__0_n_7 ; wire int_address_q; wire \int_address_q[10]_i_2_n_0 ; wire \int_address_q[10]_i_3_n_0 ; wire \int_address_q[10]_i_4_n_0 ; wire \int_address_q[10]_i_5_n_0 ; wire \int_address_q[14]_i_2_n_0 ; wire \int_address_q[14]_i_3_n_0 ; wire \int_address_q[14]_i_4_n_0 ; wire \int_address_q[14]_i_5_n_0 ; wire \int_address_q[18]_i_2_n_0 ; wire \int_address_q[18]_i_3_n_0 ; wire \int_address_q[18]_i_4_n_0 ; wire \int_address_q[18]_i_5_n_0 ; wire \int_address_q[22]_i_2_n_0 ; wire \int_address_q[22]_i_3_n_0 ; wire \int_address_q[6]_i_3_n_0 ; wire \int_address_q[6]_i_4_n_0 ; wire \int_address_q[6]_i_5_n_0 ; wire \int_address_q[6]_i_6_n_0 ; wire \int_address_q[6]_i_7_n_0 ; wire [16:0]int_address_q_reg; wire \int_address_q_reg[10]_i_1_n_0 ; wire \int_address_q_reg[10]_i_1_n_1 ; wire \int_address_q_reg[10]_i_1_n_2 ; wire \int_address_q_reg[10]_i_1_n_3 ; wire \int_address_q_reg[10]_i_1_n_4 ; wire \int_address_q_reg[10]_i_1_n_5 ; wire \int_address_q_reg[10]_i_1_n_6 ; wire \int_address_q_reg[10]_i_1_n_7 ; wire \int_address_q_reg[14]_i_1_n_0 ; wire \int_address_q_reg[14]_i_1_n_1 ; wire \int_address_q_reg[14]_i_1_n_2 ; wire \int_address_q_reg[14]_i_1_n_3 ; wire \int_address_q_reg[14]_i_1_n_4 ; wire \int_address_q_reg[14]_i_1_n_5 ; wire \int_address_q_reg[14]_i_1_n_6 ; wire \int_address_q_reg[14]_i_1_n_7 ; wire \int_address_q_reg[15]_0 ; wire \int_address_q_reg[18]_i_1_n_0 ; wire \int_address_q_reg[18]_i_1_n_1 ; wire \int_address_q_reg[18]_i_1_n_2 ; wire \int_address_q_reg[18]_i_1_n_3 ; wire \int_address_q_reg[18]_i_1_n_4 ; wire \int_address_q_reg[18]_i_1_n_5 ; wire \int_address_q_reg[18]_i_1_n_6 ; wire \int_address_q_reg[18]_i_1_n_7 ; wire \int_address_q_reg[22]_i_1_n_3 ; wire \int_address_q_reg[22]_i_1_n_6 ; wire \int_address_q_reg[22]_i_1_n_7 ; wire \int_address_q_reg[6]_i_2_n_0 ; wire \int_address_q_reg[6]_i_2_n_1 ; wire \int_address_q_reg[6]_i_2_n_2 ; wire \int_address_q_reg[6]_i_2_n_3 ; wire \int_address_q_reg[6]_i_2_n_4 ; wire \int_address_q_reg[6]_i_2_n_5 ; wire \int_address_q_reg[6]_i_2_n_6 ; wire \int_address_q_reg[6]_i_2_n_7 ; wire [23:6]int_address_q_reg_0; wire \read_state[1]_i_10_n_0 ; wire \read_state[1]_i_11_n_0 ; wire \read_state[1]_i_12_n_0 ; wire \read_state[1]_i_13_n_0 ; wire \read_state[1]_i_5_n_0 ; wire \read_state[1]_i_6_n_0 ; wire \read_state_reg[1] ; wire \read_state_reg[1]_0 ; wire [17:0]s_axi_araddr; wire ui_clk; wire \v_pos_reg[4] ; wire zoom_mode_IBUF; wire [3:0]\NLW_fb_xpos_q_reg[11]_i_1__1_CO_UNCONNECTED ; wire [3:1]\NLW_fb_xpos_q_reg[11]_i_1__1_O_UNCONNECTED ; wire [3:3]\NLW_fb_ypos_q_reg[8]_i_1__0_CO_UNCONNECTED ; wire [3:1]\NLW_int_address_q_reg[22]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_int_address_q_reg[22]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h2)) \fb_xpos_q[11]_i_2__1 (.I0(fb_xpos_q_reg[11]), .O(\fb_xpos_q[11]_i_2__1_n_0 )); LUT4 #( .INIT(16'h0040)) \fb_xpos_q[7]_i_1__0 (.I0(\fb_ypos_q[0]_i_4__0_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(\v_pos_reg[4] ), .O(\fb_xpos_q[7]_i_1__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_3__1 (.I0(fb_xpos_q_reg[10]), .O(\fb_xpos_q[7]_i_3__1_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_4__1 (.I0(fb_xpos_q_reg[9]), .O(\fb_xpos_q[7]_i_4__1_n_0 )); LUT1 #( .INIT(2'h2)) \fb_xpos_q[7]_i_5__1 (.I0(fb_xpos_q_reg[8]), .O(\fb_xpos_q[7]_i_5__1_n_0 )); LUT1 #( .INIT(2'h1)) \fb_xpos_q[7]_i_6__1 (.I0(fb_xpos_q_reg[7]), .O(\fb_xpos_q[7]_i_6__1_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[10] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__0_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__1_n_4 ), .Q(fb_xpos_q_reg[10]), .R(\fb_ypos_q[0]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \fb_xpos_q_reg[11] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__0_n_0 ), .D(\fb_xpos_q_reg[11]_i_1__1_n_7 ), .Q(fb_xpos_q_reg[11]), .R(\fb_ypos_q[0]_i_1__0_n_0 )); CARRY4 \fb_xpos_q_reg[11]_i_1__1 (.CI(\fb_xpos_q_reg[7]_i_2__1_n_0 ), .CO(\NLW_fb_xpos_q_reg[11]_i_1__1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_fb_xpos_q_reg[11]_i_1__1_O_UNCONNECTED [3:1],\fb_xpos_q_reg[11]_i_1__1_n_7 }), .S({1'b0,1'b0,1'b0,\fb_xpos_q[11]_i_2__1_n_0 })); FDSE #( .INIT(1'b1)) \fb_xpos_q_reg[7] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__0_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__1_n_7 ), .Q(fb_xpos_q_reg[7]), .S(\fb_ypos_q[0]_i_1__0_n_0 )); CARRY4 \fb_xpos_q_reg[7]_i_2__1 (.CI(1'b0), .CO({\fb_xpos_q_reg[7]_i_2__1_n_0 ,\fb_xpos_q_reg[7]_i_2__1_n_1 ,\fb_xpos_q_reg[7]_i_2__1_n_2 ,\fb_xpos_q_reg[7]_i_2__1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\fb_xpos_q_reg[7]_i_2__1_n_4 ,\fb_xpos_q_reg[7]_i_2__1_n_5 ,\fb_xpos_q_reg[7]_i_2__1_n_6 ,\fb_xpos_q_reg[7]_i_2__1_n_7 }), .S({\fb_xpos_q[7]_i_3__1_n_0 ,\fb_xpos_q[7]_i_4__1_n_0 ,\fb_xpos_q[7]_i_5__1_n_0 ,\fb_xpos_q[7]_i_6__1_n_0 })); FDSE #( .INIT(1'b1)) \fb_xpos_q_reg[8] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__0_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__1_n_6 ), .Q(fb_xpos_q_reg[8]), .S(\fb_ypos_q[0]_i_1__0_n_0 )); FDSE #( .INIT(1'b1)) \fb_xpos_q_reg[9] (.C(ui_clk), .CE(\fb_xpos_q[7]_i_1__0_n_0 ), .D(\fb_xpos_q_reg[7]_i_2__1_n_5 ), .Q(fb_xpos_q_reg[9]), .S(\fb_ypos_q[0]_i_1__0_n_0 )); LUT2 #( .INIT(4'hE)) \fb_ypos_q[0]_i_10__0 (.I0(fb_ypos_q_reg[8]), .I1(fb_ypos_q_reg[7]), .O(\fb_ypos_q[0]_i_10__0_n_0 )); LUT5 #( .INIT(32'h08000000)) \fb_ypos_q[0]_i_1__0 (.I0(\fb_ypos_q[0]_i_3__0_n_0 ), .I1(\fb_ypos_q[0]_i_4__0_n_0 ), .I2(\v_pos_reg[4] ), .I3(Q[1]), .I4(Q[0]), .O(\fb_ypos_q[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'h000000000BFFFFFF)) \fb_ypos_q[0]_i_3__0 (.I0(\fb_ypos_q[0]_i_9__0_n_0 ), .I1(fb_ypos_q_reg[6]), .I2(\fb_ypos_q[0]_i_10__0_n_0 ), .I3(fb_ypos_q_reg[10]), .I4(fb_ypos_q_reg[9]), .I5(fb_ypos_q_reg[11]), .O(\fb_ypos_q[0]_i_3__0_n_0 )); LUT5 #( .INIT(32'hAAA88888)) \fb_ypos_q[0]_i_4__0 (.I0(fb_xpos_q_reg[11]), .I1(fb_xpos_q_reg[10]), .I2(fb_xpos_q_reg[7]), .I3(fb_xpos_q_reg[8]), .I4(fb_xpos_q_reg[9]), .O(\fb_ypos_q[0]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[0]_i_5__0 (.I0(fb_ypos_q_reg[3]), .O(\fb_ypos_q[0]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[0]_i_6__0 (.I0(fb_ypos_q_reg[2]), .O(\fb_ypos_q[0]_i_6__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[0]_i_7__0 (.I0(fb_ypos_q_reg[1]), .O(\fb_ypos_q[0]_i_7__0_n_0 )); LUT1 #( .INIT(2'h1)) \fb_ypos_q[0]_i_8__0 (.I0(fb_ypos_q_reg[0]), .O(\fb_ypos_q[0]_i_8__0_n_0 )); LUT6 #( .INIT(64'h000000005555557F)) \fb_ypos_q[0]_i_9__0 (.I0(fb_ypos_q_reg[4]), .I1(fb_ypos_q_reg[0]), .I2(fb_ypos_q_reg[1]), .I3(fb_ypos_q_reg[2]), .I4(fb_ypos_q_reg[3]), .I5(fb_ypos_q_reg[5]), .O(\fb_ypos_q[0]_i_9__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_2__0 (.I0(fb_ypos_q_reg[7]), .O(\fb_ypos_q[4]_i_2__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_3__0 (.I0(fb_ypos_q_reg[6]), .O(\fb_ypos_q[4]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_4__0 (.I0(fb_ypos_q_reg[5]), .O(\fb_ypos_q[4]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[4]_i_5__0 (.I0(fb_ypos_q_reg[4]), .O(\fb_ypos_q[4]_i_5__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_2__0 (.I0(fb_ypos_q_reg[11]), .O(\fb_ypos_q[8]_i_2__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_3__0 (.I0(fb_ypos_q_reg[10]), .O(\fb_ypos_q[8]_i_3__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_4__0 (.I0(fb_ypos_q_reg[9]), .O(\fb_ypos_q[8]_i_4__0_n_0 )); LUT1 #( .INIT(2'h2)) \fb_ypos_q[8]_i_5__0 (.I0(fb_ypos_q_reg[8]), .O(\fb_ypos_q[8]_i_5__0_n_0 )); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[0] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[0]_i_2__0_n_7 ), .Q(fb_ypos_q_reg[0]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[0]_i_2__0 (.CI(1'b0), .CO({\fb_ypos_q_reg[0]_i_2__0_n_0 ,\fb_ypos_q_reg[0]_i_2__0_n_1 ,\fb_ypos_q_reg[0]_i_2__0_n_2 ,\fb_ypos_q_reg[0]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\fb_ypos_q_reg[0]_i_2__0_n_4 ,\fb_ypos_q_reg[0]_i_2__0_n_5 ,\fb_ypos_q_reg[0]_i_2__0_n_6 ,\fb_ypos_q_reg[0]_i_2__0_n_7 }), .S({\fb_ypos_q[0]_i_5__0_n_0 ,\fb_ypos_q[0]_i_6__0_n_0 ,\fb_ypos_q[0]_i_7__0_n_0 ,\fb_ypos_q[0]_i_8__0_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[10] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[8]_i_1__0_n_5 ), .Q(fb_ypos_q_reg[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[11] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[8]_i_1__0_n_4 ), .Q(fb_ypos_q_reg[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[1] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[0]_i_2__0_n_6 ), .Q(fb_ypos_q_reg[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[2] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[0]_i_2__0_n_5 ), .Q(fb_ypos_q_reg[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[3] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[0]_i_2__0_n_4 ), .Q(fb_ypos_q_reg[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[4] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[4]_i_1__0_n_7 ), .Q(fb_ypos_q_reg[4]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[4]_i_1__0 (.CI(\fb_ypos_q_reg[0]_i_2__0_n_0 ), .CO({\fb_ypos_q_reg[4]_i_1__0_n_0 ,\fb_ypos_q_reg[4]_i_1__0_n_1 ,\fb_ypos_q_reg[4]_i_1__0_n_2 ,\fb_ypos_q_reg[4]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\fb_ypos_q_reg[4]_i_1__0_n_4 ,\fb_ypos_q_reg[4]_i_1__0_n_5 ,\fb_ypos_q_reg[4]_i_1__0_n_6 ,\fb_ypos_q_reg[4]_i_1__0_n_7 }), .S({\fb_ypos_q[4]_i_2__0_n_0 ,\fb_ypos_q[4]_i_3__0_n_0 ,\fb_ypos_q[4]_i_4__0_n_0 ,\fb_ypos_q[4]_i_5__0_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[5] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[4]_i_1__0_n_6 ), .Q(fb_ypos_q_reg[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[6] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[4]_i_1__0_n_5 ), .Q(fb_ypos_q_reg[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[7] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[4]_i_1__0_n_4 ), .Q(fb_ypos_q_reg[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[8] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[8]_i_1__0_n_7 ), .Q(fb_ypos_q_reg[8]), .R(1'b0)); CARRY4 \fb_ypos_q_reg[8]_i_1__0 (.CI(\fb_ypos_q_reg[4]_i_1__0_n_0 ), .CO({\NLW_fb_ypos_q_reg[8]_i_1__0_CO_UNCONNECTED [3],\fb_ypos_q_reg[8]_i_1__0_n_1 ,\fb_ypos_q_reg[8]_i_1__0_n_2 ,\fb_ypos_q_reg[8]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\fb_ypos_q_reg[8]_i_1__0_n_4 ,\fb_ypos_q_reg[8]_i_1__0_n_5 ,\fb_ypos_q_reg[8]_i_1__0_n_6 ,\fb_ypos_q_reg[8]_i_1__0_n_7 }), .S({\fb_ypos_q[8]_i_2__0_n_0 ,\fb_ypos_q[8]_i_3__0_n_0 ,\fb_ypos_q[8]_i_4__0_n_0 ,\fb_ypos_q[8]_i_5__0_n_0 })); FDRE #( .INIT(1'b0)) \fb_ypos_q_reg[9] (.C(ui_clk), .CE(\fb_ypos_q[0]_i_1__0_n_0 ), .D(\fb_ypos_q_reg[8]_i_1__0_n_6 ), .Q(fb_ypos_q_reg[9]), .R(1'b0)); LUT1 #( .INIT(2'h2)) \int_address_q[10]_i_2 (.I0(int_address_q_reg_0[13]), .O(\int_address_q[10]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[10]_i_3 (.I0(int_address_q_reg_0[12]), .O(\int_address_q[10]_i_3_n_0 )); LUT6 #( .INIT(64'h0057FFFFFFA80000)) \int_address_q[10]_i_4 (.I0(fb_xpos_q_reg[9]), .I1(fb_xpos_q_reg[8]), .I2(fb_xpos_q_reg[7]), .I3(fb_xpos_q_reg[10]), .I4(fb_xpos_q_reg[11]), .I5(int_address_q_reg_0[11]), .O(\int_address_q[10]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[10]_i_5 (.I0(int_address_q_reg_0[10]), .O(\int_address_q[10]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[14]_i_2 (.I0(int_address_q_reg_0[17]), .O(\int_address_q[14]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[14]_i_3 (.I0(int_address_q_reg_0[16]), .O(\int_address_q[14]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[14]_i_4 (.I0(int_address_q_reg_0[15]), .O(\int_address_q[14]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[14]_i_5 (.I0(int_address_q_reg_0[14]), .O(\int_address_q[14]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[18]_i_2 (.I0(int_address_q_reg_0[21]), .O(\int_address_q[18]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[18]_i_3 (.I0(int_address_q_reg_0[20]), .O(\int_address_q[18]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[18]_i_4 (.I0(int_address_q_reg_0[19]), .O(\int_address_q[18]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[18]_i_5 (.I0(int_address_q_reg_0[18]), .O(\int_address_q[18]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[22]_i_2 (.I0(int_address_q_reg_0[23]), .O(\int_address_q[22]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[22]_i_3 (.I0(int_address_q_reg_0[22]), .O(\int_address_q[22]_i_3_n_0 )); LUT4 #( .INIT(16'h8088)) \int_address_q[6]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(\fb_ypos_q[0]_i_3__0_n_0 ), .I3(\fb_ypos_q[0]_i_4__0_n_0 ), .O(int_address_q)); LUT5 #( .INIT(32'h0057FFFF)) \int_address_q[6]_i_3 (.I0(fb_xpos_q_reg[9]), .I1(fb_xpos_q_reg[8]), .I2(fb_xpos_q_reg[7]), .I3(fb_xpos_q_reg[10]), .I4(fb_xpos_q_reg[11]), .O(\int_address_q[6]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[6]_i_4 (.I0(int_address_q_reg_0[9]), .O(\int_address_q[6]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[6]_i_5 (.I0(int_address_q_reg_0[8]), .O(\int_address_q[6]_i_5_n_0 )); LUT6 #( .INIT(64'hFFA800000057FFFF)) \int_address_q[6]_i_6 (.I0(fb_xpos_q_reg[9]), .I1(fb_xpos_q_reg[8]), .I2(fb_xpos_q_reg[7]), .I3(fb_xpos_q_reg[10]), .I4(fb_xpos_q_reg[11]), .I5(int_address_q_reg_0[7]), .O(\int_address_q[6]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \int_address_q[6]_i_7 (.I0(int_address_q_reg_0[6]), .O(\int_address_q[6]_i_7_n_0 )); FDSE #( .INIT(1'b1)) \int_address_q_reg[10] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[10]_i_1_n_7 ), .Q(int_address_q_reg_0[10]), .S(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[10]_i_1 (.CI(\int_address_q_reg[6]_i_2_n_0 ), .CO({\int_address_q_reg[10]_i_1_n_0 ,\int_address_q_reg[10]_i_1_n_1 ,\int_address_q_reg[10]_i_1_n_2 ,\int_address_q_reg[10]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,\fb_ypos_q[0]_i_4__0_n_0 ,1'b0}), .O({\int_address_q_reg[10]_i_1_n_4 ,\int_address_q_reg[10]_i_1_n_5 ,\int_address_q_reg[10]_i_1_n_6 ,\int_address_q_reg[10]_i_1_n_7 }), .S({\int_address_q[10]_i_2_n_0 ,\int_address_q[10]_i_3_n_0 ,\int_address_q[10]_i_4_n_0 ,\int_address_q[10]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[11] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[10]_i_1_n_6 ), .Q(int_address_q_reg_0[11]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[12] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[10]_i_1_n_5 ), .Q(int_address_q_reg_0[12]), .R(\v_pos_reg[4] )); FDSE #( .INIT(1'b1)) \int_address_q_reg[13] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[10]_i_1_n_4 ), .Q(int_address_q_reg_0[13]), .S(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[14] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[14]_i_1_n_7 ), .Q(int_address_q_reg_0[14]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[14]_i_1 (.CI(\int_address_q_reg[10]_i_1_n_0 ), .CO({\int_address_q_reg[14]_i_1_n_0 ,\int_address_q_reg[14]_i_1_n_1 ,\int_address_q_reg[14]_i_1_n_2 ,\int_address_q_reg[14]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[14]_i_1_n_4 ,\int_address_q_reg[14]_i_1_n_5 ,\int_address_q_reg[14]_i_1_n_6 ,\int_address_q_reg[14]_i_1_n_7 }), .S({\int_address_q[14]_i_2_n_0 ,\int_address_q[14]_i_3_n_0 ,\int_address_q[14]_i_4_n_0 ,\int_address_q[14]_i_5_n_0 })); FDSE #( .INIT(1'b1)) \int_address_q_reg[15] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[14]_i_1_n_6 ), .Q(int_address_q_reg_0[15]), .S(\v_pos_reg[4] )); FDSE #( .INIT(1'b1)) \int_address_q_reg[16] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[14]_i_1_n_5 ), .Q(int_address_q_reg_0[16]), .S(\v_pos_reg[4] )); FDSE #( .INIT(1'b1)) \int_address_q_reg[17] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[14]_i_1_n_4 ), .Q(int_address_q_reg_0[17]), .S(\v_pos_reg[4] )); FDSE #( .INIT(1'b1)) \int_address_q_reg[18] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[18]_i_1_n_7 ), .Q(int_address_q_reg_0[18]), .S(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[18]_i_1 (.CI(\int_address_q_reg[14]_i_1_n_0 ), .CO({\int_address_q_reg[18]_i_1_n_0 ,\int_address_q_reg[18]_i_1_n_1 ,\int_address_q_reg[18]_i_1_n_2 ,\int_address_q_reg[18]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\int_address_q_reg[18]_i_1_n_4 ,\int_address_q_reg[18]_i_1_n_5 ,\int_address_q_reg[18]_i_1_n_6 ,\int_address_q_reg[18]_i_1_n_7 }), .S({\int_address_q[18]_i_2_n_0 ,\int_address_q[18]_i_3_n_0 ,\int_address_q[18]_i_4_n_0 ,\int_address_q[18]_i_5_n_0 })); FDSE #( .INIT(1'b1)) \int_address_q_reg[19] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[18]_i_1_n_6 ), .Q(int_address_q_reg_0[19]), .S(\v_pos_reg[4] )); FDSE #( .INIT(1'b1)) \int_address_q_reg[20] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[18]_i_1_n_5 ), .Q(int_address_q_reg_0[20]), .S(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[21] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[18]_i_1_n_4 ), .Q(int_address_q_reg_0[21]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[22] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[22]_i_1_n_7 ), .Q(int_address_q_reg_0[22]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[22]_i_1 (.CI(\int_address_q_reg[18]_i_1_n_0 ), .CO({\NLW_int_address_q_reg[22]_i_1_CO_UNCONNECTED [3:1],\int_address_q_reg[22]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_int_address_q_reg[22]_i_1_O_UNCONNECTED [3:2],\int_address_q_reg[22]_i_1_n_6 ,\int_address_q_reg[22]_i_1_n_7 }), .S({1'b0,1'b0,\int_address_q[22]_i_2_n_0 ,\int_address_q[22]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[23] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[22]_i_1_n_6 ), .Q(int_address_q_reg_0[23]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[6] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[6]_i_2_n_7 ), .Q(int_address_q_reg_0[6]), .R(\v_pos_reg[4] )); CARRY4 \int_address_q_reg[6]_i_2 (.CI(1'b0), .CO({\int_address_q_reg[6]_i_2_n_0 ,\int_address_q_reg[6]_i_2_n_1 ,\int_address_q_reg[6]_i_2_n_2 ,\int_address_q_reg[6]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,\int_address_q[6]_i_3_n_0 ,1'b0}), .O({\int_address_q_reg[6]_i_2_n_4 ,\int_address_q_reg[6]_i_2_n_5 ,\int_address_q_reg[6]_i_2_n_6 ,\int_address_q_reg[6]_i_2_n_7 }), .S({\int_address_q[6]_i_4_n_0 ,\int_address_q[6]_i_5_n_0 ,\int_address_q[6]_i_6_n_0 ,\int_address_q[6]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \int_address_q_reg[7] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[6]_i_2_n_6 ), .Q(int_address_q_reg_0[7]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[8] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[6]_i_2_n_5 ), .Q(int_address_q_reg_0[8]), .R(\v_pos_reg[4] )); FDRE #( .INIT(1'b0)) \int_address_q_reg[9] (.C(ui_clk), .CE(int_address_q), .D(\int_address_q_reg[6]_i_2_n_4 ), .Q(int_address_q_reg_0[9]), .R(\v_pos_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) memctl_i_10 (.I0(int_address_q_reg_0[15]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[8]), .O(s_axi_araddr[9])); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) memctl_i_11 (.I0(int_address_q_reg_0[14]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[7]), .O(s_axi_araddr[8])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'hB8)) memctl_i_12 (.I0(int_address_q_reg_0[13]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[6]), .O(s_axi_araddr[7])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'hB8)) memctl_i_13 (.I0(int_address_q_reg_0[12]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[5]), .O(s_axi_araddr[6])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'hB8)) memctl_i_14 (.I0(int_address_q_reg_0[11]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[4]), .O(s_axi_araddr[5])); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'hB8)) memctl_i_15 (.I0(int_address_q_reg_0[10]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[3]), .O(s_axi_araddr[4])); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'hB8)) memctl_i_16 (.I0(int_address_q_reg_0[9]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[2]), .O(s_axi_araddr[3])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hB8)) memctl_i_17 (.I0(int_address_q_reg_0[8]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[1]), .O(s_axi_araddr[2])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hB8)) memctl_i_18 (.I0(int_address_q_reg_0[7]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[0]), .O(s_axi_araddr[1])); LUT2 #( .INIT(4'h8)) memctl_i_19 (.I0(zoom_mode_IBUF), .I1(int_address_q_reg_0[6]), .O(s_axi_araddr[0])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT3 #( .INIT(8'hB8)) memctl_i_2 (.I0(int_address_q_reg_0[23]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[16]), .O(s_axi_araddr[17])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) memctl_i_3 (.I0(int_address_q_reg_0[22]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[15]), .O(s_axi_araddr[16])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) memctl_i_4 (.I0(int_address_q_reg_0[21]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[14]), .O(s_axi_araddr[15])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) memctl_i_5 (.I0(int_address_q_reg_0[20]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[13]), .O(s_axi_araddr[14])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT3 #( .INIT(8'hB8)) memctl_i_6 (.I0(int_address_q_reg_0[19]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[12]), .O(s_axi_araddr[13])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) memctl_i_7 (.I0(int_address_q_reg_0[18]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[11]), .O(s_axi_araddr[12])); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) memctl_i_8 (.I0(int_address_q_reg_0[17]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[10]), .O(s_axi_araddr[11])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) memctl_i_9 (.I0(int_address_q_reg_0[16]), .I1(zoom_mode_IBUF), .I2(int_address_q_reg[9]), .O(s_axi_araddr[10])); LUT6 #( .INIT(64'hFFFFBBBAAAAABBBA)) \read_state[1]_i_1 (.I0(\read_state_reg[1] ), .I1(\int_address_q_reg[15]_0 ), .I2(\read_state[1]_i_5_n_0 ), .I3(\read_state[1]_i_6_n_0 ), .I4(Q[0]), .I5(\read_state_reg[1]_0 ), .O(E)); LUT4 #( .INIT(16'h007F)) \read_state[1]_i_10 (.I0(int_address_q_reg_0[13]), .I1(int_address_q_reg_0[15]), .I2(int_address_q_reg_0[14]), .I3(int_address_q_reg_0[16]), .O(\read_state[1]_i_10_n_0 )); LUT5 #( .INIT(32'h7FFFFFFF)) \read_state[1]_i_11 (.I0(int_address_q_reg_0[17]), .I1(int_address_q_reg_0[18]), .I2(int_address_q_reg_0[22]), .I3(int_address_q_reg_0[20]), .I4(int_address_q_reg_0[19]), .O(\read_state[1]_i_11_n_0 )); LUT6 #( .INIT(64'h0001010101010101)) \read_state[1]_i_12 (.I0(int_address_q_reg_0[11]), .I1(int_address_q_reg_0[16]), .I2(int_address_q_reg_0[12]), .I3(int_address_q_reg_0[8]), .I4(int_address_q_reg_0[10]), .I5(int_address_q_reg_0[9]), .O(\read_state[1]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h01)) \read_state[1]_i_13 (.I0(int_address_q_reg_0[12]), .I1(int_address_q_reg_0[16]), .I2(int_address_q_reg_0[11]), .O(\read_state[1]_i_13_n_0 )); LUT6 #( .INIT(64'h0000000000FEFEFE)) \read_state[1]_i_5 (.I0(\read_state[1]_i_10_n_0 ), .I1(\read_state[1]_i_11_n_0 ), .I2(\read_state[1]_i_12_n_0 ), .I3(int_address_q_reg_0[21]), .I4(int_address_q_reg_0[22]), .I5(int_address_q_reg_0[23]), .O(\read_state[1]_i_5_n_0 )); LUT6 #( .INIT(64'h555555555555555D)) \read_state[1]_i_6 (.I0(zoom_mode_IBUF), .I1(\read_state[1]_i_13_n_0 ), .I2(int_address_q_reg_0[6]), .I3(int_address_q_reg_0[21]), .I4(int_address_q_reg_0[7]), .I5(int_address_q_reg_0[23]), .O(\read_state[1]_i_6_n_0 )); endmodule module framebuffer_ctrl_crop_scale (dout, s_axi_awaddr, odd_pixel, s_axi_arvalid, s_axi_araddr, s_axi_wlast, D, s_axi_awvalid, rst, CLK, ui_clk, wr_en, \v_pos_reg[4] , bbstub_pixel_clock, s_axi_rdata, rd_en, odd_pixel_reg_0, odd_pixel_reg_1, fbc_ovsync, s_axi_arready, zoom_mode_IBUF, s_axi_rlast, s_axi_rvalid, s_axi_wready, s_axi_awready); output [255:0]dout; output [16:0]s_axi_awaddr; output odd_pixel; output s_axi_arvalid; output [17:0]s_axi_araddr; output s_axi_wlast; output [0:0]D; output s_axi_awvalid; input rst; input CLK; input ui_clk; input wr_en; input \v_pos_reg[4] ; input bbstub_pixel_clock; input [255:0]s_axi_rdata; input rd_en; input odd_pixel_reg_0; input odd_pixel_reg_1; input fbc_ovsync; input s_axi_arready; input zoom_mode_IBUF; input s_axi_rlast; input s_axi_rvalid; input s_axi_wready; input s_axi_awready; wire CLK; wire [0:0]D; wire \FSM_sequential_write_state[0]_i_1_n_0 ; wire \FSM_sequential_write_state[1]_i_1_n_0 ; wire \FSM_sequential_write_state[2]_i_1_n_0 ; wire \FSM_sequential_write_state[2]_i_2_n_0 ; wire \FSM_sequential_write_state[2]_i_5_n_0 ; wire bbstub_pixel_clock; wire [255:0]dout; wire fbc_ovsync; wire i__i_1_n_0; wire [23:7]int_address_q_reg; wire odd_pixel; wire odd_pixel_reg_0; wire odd_pixel_reg_1; wire output_fifo1_i_2_n_0; wire prog_empty; wire prog_full; wire rd_adctrl_crop_n_0; wire rd_adctrl_scale_n_17; wire rd_en; wire rd_en_0; wire [1:1]read_state; wire \read_state[0]_i_1_n_0 ; wire \read_state[1]_i_3_n_0 ; wire \read_state[1]_i_7_n_0 ; wire \read_state_reg_n_0_[0] ; wire \read_state_reg_n_0_[1] ; wire rst; wire [17:0]s_axi_araddr; wire s_axi_arready; wire s_axi_arvalid; wire [16:0]s_axi_awaddr; wire s_axi_awready; wire s_axi_awvalid; wire [255:0]s_axi_rdata; wire s_axi_rlast; wire s_axi_rvalid; wire s_axi_wlast; wire s_axi_wready; wire ui_clk; wire \v_pos_reg[4] ; wire wr_adctrl_n_17; wire wr_adctrl_n_18; wire wr_en; wire write_count; wire \write_count[0]_i_1_n_0 ; wire \write_count[1]_i_1_n_0 ; wire \write_count[2]_i_1_n_0 ; wire \write_count[3]_i_1_n_0 ; wire \write_count_reg_n_0_[0] ; wire \write_count_reg_n_0_[1] ; wire \write_count_reg_n_0_[2] ; wire \write_count_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire [2:0]write_state; wire zoom_mode_IBUF; wire NLW_input_fifo_empty_UNCONNECTED; wire NLW_input_fifo_full_UNCONNECTED; wire NLW_output_fifo1_empty_UNCONNECTED; wire NLW_output_fifo1_full_UNCONNECTED; wire [31:0]NLW_output_fifo1_dout_UNCONNECTED; wire NLW_output_fifo2_empty_UNCONNECTED; wire NLW_output_fifo2_full_UNCONNECTED; wire NLW_output_fifo2_prog_full_UNCONNECTED; wire [31:0]NLW_output_fifo2_dout_UNCONNECTED; LUT6 #( .INIT(64'h4440004000400040)) \/i_ (.I0(write_state[2]), .I1(write_state[0]), .I2(s_axi_awready), .I3(write_state[1]), .I4(i__i_1_n_0), .I5(s_axi_wready), .O(write_count)); LUT2 #( .INIT(4'h1)) \FSM_sequential_write_state[0]_i_1 (.I0(write_state[0]), .I1(write_state[2]), .O(\FSM_sequential_write_state[0]_i_1_n_0 )); LUT3 #( .INIT(8'h06)) \FSM_sequential_write_state[1]_i_1 (.I0(write_state[1]), .I1(write_state[0]), .I2(write_state[2]), .O(\FSM_sequential_write_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF000000A8)) \FSM_sequential_write_state[2]_i_1 (.I0(\FSM_sequential_write_state[2]_i_2_n_0 ), .I1(wr_adctrl_n_17), .I2(wr_adctrl_n_18), .I3(prog_empty), .I4(s_axi_awaddr[16]), .I5(\FSM_sequential_write_state[2]_i_5_n_0 ), .O(\FSM_sequential_write_state[2]_i_1_n_0 )); LUT2 #( .INIT(4'h1)) \FSM_sequential_write_state[2]_i_2 (.I0(write_state[1]), .I1(write_state[0]), .O(\FSM_sequential_write_state[2]_i_2_n_0 )); LUT6 #( .INIT(64'h105555AA100055AA)) \FSM_sequential_write_state[2]_i_5 (.I0(write_state[2]), .I1(i__i_1_n_0), .I2(s_axi_wready), .I3(write_state[1]), .I4(write_state[0]), .I5(s_axi_awready), .O(\FSM_sequential_write_state[2]_i_5_n_0 )); (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \FSM_sequential_write_state_reg[0] (.C(ui_clk), .CE(\FSM_sequential_write_state[2]_i_1_n_0 ), .CLR(rst), .D(\FSM_sequential_write_state[0]_i_1_n_0 ), .Q(write_state[0])); (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \FSM_sequential_write_state_reg[1] (.C(ui_clk), .CE(\FSM_sequential_write_state[2]_i_1_n_0 ), .CLR(rst), .D(\FSM_sequential_write_state[1]_i_1_n_0 ), .Q(write_state[1])); (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \FSM_sequential_write_state_reg[2] (.C(ui_clk), .CE(\FSM_sequential_write_state[2]_i_1_n_0 ), .CLR(rst), .D(D), .Q(write_state[2])); LUT3 #( .INIT(8'h02)) axi_awvalid (.I0(write_state[0]), .I1(write_state[2]), .I2(write_state[1]), .O(s_axi_awvalid)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT5 #( .INIT(32'h80000000)) axi_wlast0 (.I0(\write_count_reg_n_0_[2] ), .I1(\write_count_reg_n_0_[0] ), .I2(D), .I3(\write_count_reg_n_0_[3] ), .I4(\write_count_reg_n_0_[1] ), .O(s_axi_wlast)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h7FFF)) i__i_1 (.I0(\write_count_reg_n_0_[3] ), .I1(\write_count_reg_n_0_[2] ), .I2(\write_count_reg_n_0_[0] ), .I3(\write_count_reg_n_0_[1] ), .O(i__i_1_n_0)); (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) fb_input_fifo input_fifo (.din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .dout(dout), .empty(NLW_input_fifo_empty_UNCONNECTED), .full(NLW_input_fifo_full_UNCONNECTED), .prog_empty(prog_empty), .rd_clk(ui_clk), .rd_en(rd_en_0), .rst(rst), .wr_clk(CLK), .wr_en(wr_en)); LUT3 #( .INIT(8'h40)) memctl_i_1 (.I0(write_state[2]), .I1(write_state[0]), .I2(write_state[1]), .O(D)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h2)) memctl_i_20 (.I0(\read_state_reg_n_0_[0] ), .I1(\read_state_reg_n_0_[1] ), .O(s_axi_arvalid)); FDPE #( .INIT(1'b1)) odd_pixel_reg (.C(bbstub_pixel_clock), .CE(1'b1), .D(odd_pixel_reg_1), .PRE(fbc_ovsync), .Q(odd_pixel)); (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) fb_output_fifo output_fifo1 (.din({s_axi_rdata[223:192],s_axi_rdata[159:128],s_axi_rdata[95:64],s_axi_rdata[31:0]}), .dout(NLW_output_fifo1_dout_UNCONNECTED[31:0]), .empty(NLW_output_fifo1_empty_UNCONNECTED), .full(NLW_output_fifo1_full_UNCONNECTED), .prog_full(prog_full), .rd_clk(bbstub_pixel_clock), .rd_en(rd_en), .rst(\v_pos_reg[4] ), .wr_clk(ui_clk), .wr_en(output_fifo1_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h40)) output_fifo1_i_2 (.I0(\read_state_reg_n_0_[0] ), .I1(s_axi_rvalid), .I2(\read_state_reg_n_0_[1] ), .O(output_fifo1_i_2_n_0)); (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) fb_output_fifo output_fifo2 (.din({s_axi_rdata[255:224],s_axi_rdata[191:160],s_axi_rdata[127:96],s_axi_rdata[63:32]}), .dout(NLW_output_fifo2_dout_UNCONNECTED[31:0]), .empty(NLW_output_fifo2_empty_UNCONNECTED), .full(NLW_output_fifo2_full_UNCONNECTED), .prog_full(NLW_output_fifo2_prog_full_UNCONNECTED), .rd_clk(bbstub_pixel_clock), .rd_en(odd_pixel_reg_0), .rst(\v_pos_reg[4] ), .wr_clk(ui_clk), .wr_en(output_fifo1_i_2_n_0)); framebuffer_addr_ctrl__parameterized1 rd_adctrl_crop (.E(rd_adctrl_crop_n_0), .Q({\read_state_reg_n_0_[1] ,\read_state_reg_n_0_[0] }), .int_address_q_reg(int_address_q_reg), .\int_address_q_reg[15]_0 (rd_adctrl_scale_n_17), .\read_state_reg[1] (\read_state[1]_i_3_n_0 ), .\read_state_reg[1]_0 (\read_state[1]_i_7_n_0 ), .s_axi_araddr(s_axi_araddr), .ui_clk(ui_clk), .\v_pos_reg[4] (\v_pos_reg[4] ), .zoom_mode_IBUF(zoom_mode_IBUF)); framebuffer_addr_ctrl__parameterized0 rd_adctrl_scale (.Q({\read_state_reg_n_0_[1] ,\read_state_reg_n_0_[0] }), .int_address_q_reg(int_address_q_reg), .prog_full(prog_full), .\read_state_reg[0] (rd_adctrl_scale_n_17), .ui_clk(ui_clk), .\v_pos_reg[4] (\v_pos_reg[4] ), .zoom_mode_IBUF(zoom_mode_IBUF)); LUT4 #( .INIT(16'h2300)) rd_en0 (.I0(s_axi_wready), .I1(write_state[2]), .I2(write_state[0]), .I3(write_state[1]), .O(rd_en_0)); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h4055)) \read_state[0]_i_1 (.I0(\read_state_reg_n_0_[0] ), .I1(s_axi_rvalid), .I2(s_axi_rlast), .I3(\read_state_reg_n_0_[1] ), .O(\read_state[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h40AA)) \read_state[1]_i_2 (.I0(\read_state_reg_n_0_[0] ), .I1(s_axi_rlast), .I2(s_axi_rvalid), .I3(\read_state_reg_n_0_[1] ), .O(read_state)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h80)) \read_state[1]_i_3 (.I0(s_axi_rlast), .I1(s_axi_rvalid), .I2(\read_state_reg_n_0_[1] ), .O(\read_state[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'hE)) \read_state[1]_i_7 (.I0(\read_state_reg_n_0_[1] ), .I1(s_axi_arready), .O(\read_state[1]_i_7_n_0 )); FDCE #( .INIT(1'b0)) \read_state_reg[0] (.C(ui_clk), .CE(rd_adctrl_crop_n_0), .CLR(\v_pos_reg[4] ), .D(\read_state[0]_i_1_n_0 ), .Q(\read_state_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \read_state_reg[1] (.C(ui_clk), .CE(rd_adctrl_crop_n_0), .CLR(\v_pos_reg[4] ), .D(read_state), .Q(\read_state_reg_n_0_[1] )); framebuffer_addr_ctrl wr_adctrl (.\FSM_sequential_write_state_reg[0] (wr_adctrl_n_17), .\FSM_sequential_write_state_reg[0]_0 (wr_adctrl_n_18), .out(write_state), .rst(rst), .s_axi_awaddr(s_axi_awaddr), .ui_clk(ui_clk)); LUT3 #( .INIT(8'h04)) \write_count[0]_i_1 (.I0(write_state[2]), .I1(write_state[1]), .I2(\write_count_reg_n_0_[0] ), .O(\write_count[0]_i_1_n_0 )); LUT4 #( .INIT(16'h0440)) \write_count[1]_i_1 (.I0(write_state[2]), .I1(write_state[1]), .I2(\write_count_reg_n_0_[0] ), .I3(\write_count_reg_n_0_[1] ), .O(\write_count[1]_i_1_n_0 )); LUT5 #( .INIT(32'h04444000)) \write_count[2]_i_1 (.I0(write_state[2]), .I1(write_state[1]), .I2(\write_count_reg_n_0_[0] ), .I3(\write_count_reg_n_0_[1] ), .I4(\write_count_reg_n_0_[2] ), .O(\write_count[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0444444440000000)) \write_count[3]_i_1 (.I0(write_state[2]), .I1(write_state[1]), .I2(\write_count_reg_n_0_[1] ), .I3(\write_count_reg_n_0_[0] ), .I4(\write_count_reg_n_0_[2] ), .I5(\write_count_reg_n_0_[3] ), .O(\write_count[3]_i_1_n_0 )); FDCE #( .INIT(1'b0)) \write_count_reg[0] (.C(ui_clk), .CE(write_count), .CLR(rst), .D(\write_count[0]_i_1_n_0 ), .Q(\write_count_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \write_count_reg[1] (.C(ui_clk), .CE(write_count), .CLR(rst), .D(\write_count[1]_i_1_n_0 ), .Q(\write_count_reg_n_0_[1] )); FDCE #( .INIT(1'b0)) \write_count_reg[2] (.C(ui_clk), .CE(write_count), .CLR(rst), .D(\write_count[2]_i_1_n_0 ), .Q(\write_count_reg_n_0_[2] )); FDCE #( .INIT(1'b0)) \write_count_reg[3] (.C(ui_clk), .CE(write_count), .CLR(rst), .D(\write_count[3]_i_1_n_0 ), .Q(\write_count_reg_n_0_[3] )); endmodule module framebuffer_top (ddr3_addr, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_dm, ddr3_odt, AR, dvi_den, D, ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, rst, CLK, wr_en, bbstub_pixel_clock, sys_clk_i, reset_n_IBUF, zoom_mode_IBUF); output [14:0]ddr3_addr; output [2:0]ddr3_ba; output ddr3_ras_n; output ddr3_cas_n; output ddr3_we_n; output ddr3_reset_n; output [0:0]ddr3_ck_p; output [0:0]ddr3_ck_n; output [0:0]ddr3_cke; output [0:0]ddr3_cs_n; output [3:0]ddr3_dm; output [0:0]ddr3_odt; output [0:0]AR; output dvi_den; output [1:0]D; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_n; inout [3:0]ddr3_dqs_p; input rst; input CLK; input wr_en; input bbstub_pixel_clock; input sys_clk_i; input reset_n_IBUF; input zoom_mode_IBUF; wire [0:0]AR; wire CLK; wire [1:0]D; wire [25:8]axi_araddr; wire axi_arready; wire axi_arvalid; wire [25:9]axi_awaddr; wire axi_awready; wire axi_awvalid; wire axi_bid; wire [1:0]axi_bresp; wire axi_bvalid; wire [255:0]axi_rdata; wire axi_rid; wire axi_rlast; wire [1:0]axi_rresp; wire axi_rvalid; wire [255:0]axi_wdata; wire axi_wlast; wire axi_wready; wire bbstub_pixel_clock; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_ck_n; wire [0:0]ddr3_ck_p; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire dvi_den; wire fbc_ovsync; wire fbctl_n_294; wire odd_pixel; wire output_n_2; wire output_n_3; wire output_n_7; wire output_n_8; wire reset_n_IBUF; wire rst; wire sys_clk_i; wire ui_clock; wire wr_en; wire zoom_mode_IBUF; wire NLW_memctl_app_ref_ack_UNCONNECTED; wire NLW_memctl_app_sr_active_UNCONNECTED; wire NLW_memctl_app_zq_ack_UNCONNECTED; wire NLW_memctl_init_calib_complete_UNCONNECTED; wire NLW_memctl_mmcm_locked_UNCONNECTED; wire NLW_memctl_ui_clk_sync_rst_UNCONNECTED; wire [11:0]NLW_memctl_device_temp_UNCONNECTED; framebuffer_ctrl_crop_scale fbctl (.CLK(CLK), .D(fbctl_n_294), .bbstub_pixel_clock(bbstub_pixel_clock), .dout(axi_wdata), .fbc_ovsync(fbc_ovsync), .odd_pixel(odd_pixel), .odd_pixel_reg_0(output_n_3), .odd_pixel_reg_1(output_n_7), .rd_en(output_n_2), .rst(rst), .s_axi_araddr(axi_araddr), .s_axi_arready(axi_arready), .s_axi_arvalid(axi_arvalid), .s_axi_awaddr(axi_awaddr), .s_axi_awready(axi_awready), .s_axi_awvalid(axi_awvalid), .s_axi_rdata(axi_rdata), .s_axi_rlast(axi_rlast), .s_axi_rvalid(axi_rvalid), .s_axi_wlast(axi_wlast), .s_axi_wready(axi_wready), .ui_clk(ui_clock), .\v_pos_reg[4] (output_n_8), .wr_en(wr_en), .zoom_mode_IBUF(zoom_mode_IBUF)); ddr3_if memctl (.app_ref_ack(NLW_memctl_app_ref_ack_UNCONNECTED), .app_ref_req(1'b0), .app_sr_active(NLW_memctl_app_sr_active_UNCONNECTED), .app_sr_req(1'b0), .app_zq_ack(NLW_memctl_app_zq_ack_UNCONNECTED), .app_zq_req(1'b0), .aresetn(reset_n_IBUF), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_ck_n(ddr3_ck_n), .ddr3_ck_p(ddr3_ck_p), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .device_temp(NLW_memctl_device_temp_UNCONNECTED[11:0]), .init_calib_complete(NLW_memctl_init_calib_complete_UNCONNECTED), .mmcm_locked(NLW_memctl_mmcm_locked_UNCONNECTED), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,axi_araddr,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b1}), .s_axi_arcache({1'b0,1'b0,1'b1,1'b1}), .s_axi_arid(1'b1), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(axi_arready), .s_axi_arsize({1'b0,1'b1,1'b0}), .s_axi_arvalid(axi_arvalid), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,axi_awaddr,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b1}), .s_axi_awcache({1'b0,1'b0,1'b1,1'b1}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(axi_awready), .s_axi_awsize({1'b0,1'b1,1'b0}), .s_axi_awvalid(axi_awvalid), .s_axi_bid(axi_bid), .s_axi_bready(1'b1), .s_axi_bresp(axi_bresp), .s_axi_bvalid(axi_bvalid), .s_axi_rdata(axi_rdata), .s_axi_rid(axi_rid), .s_axi_rlast(axi_rlast), .s_axi_rready(1'b1), .s_axi_rresp(axi_rresp), .s_axi_rvalid(axi_rvalid), .s_axi_wdata(axi_wdata), .s_axi_wlast(axi_wlast), .s_axi_wready(axi_wready), .s_axi_wstrb({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .s_axi_wvalid(fbctl_n_294), .sys_clk_i(sys_clk_i), .sys_rst(AR), .ui_clk(ui_clock), .ui_clk_sync_rst(NLW_memctl_ui_clk_sync_rst_UNCONNECTED)); video_fb_output \output (.AR(AR), .D(D), .bbstub_pixel_clock(bbstub_pixel_clock), .dvi_den(dvi_den), .fbc_ovsync(fbc_ovsync), .\int_address_q_reg[23] (output_n_8), .odd_pixel(odd_pixel), .odd_pixel_reg(output_n_7), .output_fifo2(output_n_3), .rd_en(output_n_2), .reset_n_IBUF(reset_n_IBUF), .zoom_mode_IBUF(zoom_mode_IBUF)); endmodule (* NotValidForBitStream *) module genesys2_fbtest (clock_p, clock_n, reset_n, hdmi_clk, hdmi_d0, hdmi_d1, hdmi_d2, zoom_mode, ddr3_addr, ddr3_ba, ddr3_cas_n, ddr3_ck_n, ddr3_ck_p, ddr3_cke, ddr3_ras_n, ddr3_reset_n, ddr3_we_n, ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_cs_n, ddr3_dm, ddr3_odt); input clock_p; input clock_n; input reset_n; output [1:0]hdmi_clk; output [1:0]hdmi_d0; output [1:0]hdmi_d1; output [1:0]hdmi_d2; input zoom_mode; (* CLOCK_BUFFER_TYPE = "none" *) output [14:0]ddr3_addr; (* CLOCK_BUFFER_TYPE = "none" *) output [2:0]ddr3_ba; (* CLOCK_BUFFER_TYPE = "none" *) output ddr3_cas_n; output [0:0]ddr3_ck_n; output [0:0]ddr3_ck_p; (* CLOCK_BUFFER_TYPE = "none" *) output [0:0]ddr3_cke; (* CLOCK_BUFFER_TYPE = "none" *) output ddr3_ras_n; (* CLOCK_BUFFER_TYPE = "none" *) output ddr3_reset_n; (* CLOCK_BUFFER_TYPE = "none" *) output ddr3_we_n; (* CLOCK_BUFFER_TYPE = "none" *) inout [31:0]ddr3_dq; (* CLOCK_BUFFER_TYPE = "none" *) inout [3:0]ddr3_dqs_n; (* CLOCK_BUFFER_TYPE = "none" *) inout [3:0]ddr3_dqs_p; (* CLOCK_BUFFER_TYPE = "none" *) output [0:0]ddr3_cs_n; (* CLOCK_BUFFER_TYPE = "none" *) output [3:0]ddr3_dm; (* CLOCK_BUFFER_TYPE = "none" *) output [0:0]ddr3_odt; (* DIFF_TERM *) (* IBUF_LOW_PWR = 0 *) wire clock_n; (* DIFF_TERM *) (* IBUF_LOW_PWR = 0 *) wire clock_p; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_ck_n; wire [0:0]ddr3_ck_p; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; (* IBUF_LOW_PWR = 0 *) wire [31:0]ddr3_dq; (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_n; (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; (* DRIVE = "12" *) wire ddr3_reset_n; wire ddr3_we_n; wire dvi_bit_clock; wire dvi_den; wire dvi_pixel_clock; wire [1:0]hdmi_clk; wire [1:0]hdmi_d0; wire [1:0]hdmi_d1; wire [1:0]hdmi_d2; wire hsync_pos; wire input_den; wire input_pixel_clock; wire reset; wire reset_n; wire reset_n_IBUF; wire sys_clock; wire tp_n_1; wire vsync_pos; wire zoom_mode; wire zoom_mode_IBUF; (* CAPACITANCE = "DONT_CARE" *) (* IBUF_DELAY_VALUE = "0" *) (* XILINX_LEGACY_PRIM = "IBUFGDS" *) (* box_type = "PRIMITIVE" *) IBUFDS #( .DQS_BIAS("FALSE"), .IOSTANDARD("DEFAULT")) clkbuf (.I(clock_p), .IB(clock_n), .O(sys_clock)); dvi_tx dvi_tx (.D({vsync_pos,hsync_pos}), .SR(reset), .dvi_bit_clock(dvi_bit_clock), .dvi_den(dvi_den), .hdmi_clk(hdmi_clk), .hdmi_d0(hdmi_d0), .hdmi_d1(hdmi_d1), .hdmi_d2(hdmi_d2), .pixel_clock(dvi_pixel_clock), .reset_n_IBUF(reset_n_IBUF)); framebuffer_top fbtest (.AR(reset), .CLK(input_pixel_clock), .D({vsync_pos,hsync_pos}), .bbstub_pixel_clock(dvi_pixel_clock), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_ck_n(ddr3_ck_n), .ddr3_ck_p(ddr3_ck_p), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .dvi_den(dvi_den), .reset_n_IBUF(reset_n_IBUF), .rst(tp_n_1), .sys_clk_i(sys_clock), .wr_en(input_den), .zoom_mode_IBUF(zoom_mode_IBUF)); dvi_pll pll1 (.dvi_bit_clock(dvi_bit_clock), .pixel_clock(dvi_pixel_clock), .sysclk(sys_clock)); camera_pll pll2 (.camera_pixel_clock(input_pixel_clock), .sysclk(sys_clock)); IBUF reset_n_IBUF_inst (.I(reset_n), .O(reset_n_IBUF)); test_pattern_gen tp (.AR(reset), .CLK(input_pixel_clock), .reset_n_IBUF(reset_n_IBUF), .rst(tp_n_1), .wr_en(input_den)); IBUF zoom_mode_IBUF_inst (.I(zoom_mode), .O(zoom_mode_IBUF)); endmodule module test_pattern_gen (wr_en, rst, reset_n_IBUF, CLK, AR); output wr_en; output rst; input reset_n_IBUF; input CLK; input [0:0]AR; wire [0:0]AR; wire CLK; wire reset_n_IBUF; wire rst; wire wr_en; video_timing_ctrl__parameterized0 tmg_gen (.AR(AR), .CLK(CLK), .reset_n_IBUF(reset_n_IBUF), .rst(rst), .wr_en(wr_en)); endmodule module video_fb_output (AR, dvi_den, rd_en, output_fifo2, D, fbc_ovsync, odd_pixel_reg, \int_address_q_reg[23] , reset_n_IBUF, odd_pixel, zoom_mode_IBUF, bbstub_pixel_clock); output [0:0]AR; output dvi_den; output rd_en; output output_fifo2; output [1:0]D; output fbc_ovsync; output odd_pixel_reg; output \int_address_q_reg[23] ; input reset_n_IBUF; input odd_pixel; input zoom_mode_IBUF; input bbstub_pixel_clock; wire [0:0]AR; wire [1:0]D; wire bbstub_pixel_clock; wire dvi_den; wire fbc_ovsync; wire \int_address_q_reg[23] ; wire odd_pixel; wire odd_pixel_reg; wire output_fifo2; wire rd_en; wire reset_n_IBUF; wire zoom_mode_IBUF; video_timing_ctrl tmg_gen (.AR(AR), .D(D), .bbstub_pixel_clock(bbstub_pixel_clock), .dvi_den(dvi_den), .fbc_ovsync(fbc_ovsync), .\int_address_q_reg[23] (\int_address_q_reg[23] ), .odd_pixel(odd_pixel), .odd_pixel_reg(odd_pixel_reg), .output_fifo2(output_fifo2), .rd_en(rd_en), .reset_n_IBUF(reset_n_IBUF), .zoom_mode_IBUF(zoom_mode_IBUF)); endmodule module video_timing_ctrl (AR, dvi_den, rd_en, output_fifo2, D, fbc_ovsync, odd_pixel_reg, \int_address_q_reg[23] , reset_n_IBUF, odd_pixel, zoom_mode_IBUF, bbstub_pixel_clock); output [0:0]AR; output dvi_den; output rd_en; output output_fifo2; output [1:0]D; output fbc_ovsync; output odd_pixel_reg; output \int_address_q_reg[23] ; input reset_n_IBUF; input odd_pixel; input zoom_mode_IBUF; input bbstub_pixel_clock; wire [0:0]AR; wire [1:0]D; wire bbstub_pixel_clock; wire \ctrl_lat[0]_i_2_n_0 ; wire \ctrl_lat[1]_i_2_n_0 ; wire [11:1]data0; wire den_lat_i_2_n_0; wire den_lat_i_3_n_0; wire dvi_den; wire fbc_ovsync; wire [11:0]h_pos; wire \h_pos[11]_i_2_n_0 ; wire \h_pos[11]_i_3_n_0 ; wire \h_pos[11]_i_5_n_0 ; wire \h_pos[11]_i_6_n_0 ; wire \h_pos[11]_i_7_n_0 ; wire \h_pos[4]_i_3_n_0 ; wire \h_pos[4]_i_4_n_0 ; wire \h_pos[4]_i_5_n_0 ; wire \h_pos[4]_i_6_n_0 ; wire \h_pos[8]_i_3_n_0 ; wire \h_pos[8]_i_4_n_0 ; wire \h_pos[8]_i_5_n_0 ; wire \h_pos[8]_i_6_n_0 ; wire \h_pos_reg[11]_i_4_n_2 ; wire \h_pos_reg[11]_i_4_n_3 ; wire \h_pos_reg[4]_i_2_n_0 ; wire \h_pos_reg[4]_i_2_n_1 ; wire \h_pos_reg[4]_i_2_n_2 ; wire \h_pos_reg[4]_i_2_n_3 ; wire \h_pos_reg[8]_i_2_n_0 ; wire \h_pos_reg[8]_i_2_n_1 ; wire \h_pos_reg[8]_i_2_n_2 ; wire \h_pos_reg[8]_i_2_n_3 ; wire \int_address_q_reg[23] ; wire odd_pixel; wire odd_pixel_i_3_n_0; wire odd_pixel_reg; wire output_fifo1_i_10_n_0; wire output_fifo1_i_4_n_0; wire output_fifo1_i_5_n_0; wire output_fifo1_i_6_n_0; wire output_fifo1_i_7_n_0; wire output_fifo1_i_8_n_0; wire output_fifo1_i_9_n_0; wire output_fifo2; wire rd_en; wire reset_n_IBUF; wire [11:0]timing_h_pos; wire [10:0]timing_v_pos; wire [10:0]v_pos; wire v_pos0; wire \v_pos[10]_i_3_n_0 ; wire \v_pos[10]_i_4_n_0 ; wire \v_pos[10]_i_5_n_0 ; wire \v_pos[10]_i_6_n_0 ; wire \v_pos[2]_i_2_n_0 ; wire \v_pos[2]_i_3_n_0 ; wire \v_pos[9]_i_2_n_0 ; wire zoom_mode_IBUF; wire [3:2]\NLW_h_pos_reg[11]_i_4_CO_UNCONNECTED ; wire [3:3]\NLW_h_pos_reg[11]_i_4_O_UNCONNECTED ; LUT5 #( .INIT(32'h000015FF)) \ctrl_lat[0]_i_1 (.I0(timing_h_pos[4]), .I1(timing_h_pos[3]), .I2(timing_h_pos[2]), .I3(timing_h_pos[5]), .I4(\ctrl_lat[0]_i_2_n_0 ), .O(D[0])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \ctrl_lat[0]_i_2 (.I0(timing_h_pos[9]), .I1(timing_h_pos[8]), .I2(timing_h_pos[10]), .I3(timing_h_pos[6]), .I4(timing_h_pos[11]), .I5(timing_h_pos[7]), .O(\ctrl_lat[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT4 #( .INIT(16'h001F)) \ctrl_lat[1]_i_1 (.I0(timing_v_pos[1]), .I1(timing_v_pos[0]), .I2(timing_v_pos[2]), .I3(\ctrl_lat[1]_i_2_n_0 ), .O(D[1])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \ctrl_lat[1]_i_2 (.I0(timing_v_pos[6]), .I1(\v_pos[2]_i_2_n_0 ), .I2(timing_v_pos[10]), .I3(timing_v_pos[4]), .I4(timing_v_pos[3]), .I5(timing_v_pos[5]), .O(\ctrl_lat[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0C0C04040C0C0040)) den_lat_i_1 (.I0(den_lat_i_2_n_0), .I1(output_fifo1_i_7_n_0), .I2(timing_h_pos[11]), .I3(timing_h_pos[2]), .I4(den_lat_i_3_n_0), .I5(timing_h_pos[3]), .O(dvi_den)); LUT4 #( .INIT(16'h0010)) den_lat_i_2 (.I0(timing_h_pos[0]), .I1(timing_h_pos[2]), .I2(timing_h_pos[3]), .I3(timing_h_pos[1]), .O(den_lat_i_2_n_0)); LUT5 #( .INIT(32'hFFFFFFFE)) den_lat_i_3 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[7]), .I2(timing_h_pos[4]), .I3(timing_h_pos[6]), .I4(timing_h_pos[5]), .O(den_lat_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT1 #( .INIT(2'h1)) \h_pos[0]_i_1 (.I0(timing_h_pos[0]), .O(h_pos[0])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[10]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[10]), .O(h_pos[10])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[11]_i_1 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[11]), .O(h_pos[11])); LUT3 #( .INIT(8'hFE)) \h_pos[11]_i_2 (.I0(timing_h_pos[10]), .I1(timing_h_pos[8]), .I2(timing_h_pos[9]), .O(\h_pos[11]_i_2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \h_pos[11]_i_3 (.I0(timing_h_pos[0]), .I1(timing_h_pos[1]), .I2(timing_h_pos[4]), .I3(timing_h_pos[11]), .I4(timing_h_pos[7]), .I5(timing_h_pos[2]), .O(\h_pos[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[11]_i_5 (.I0(timing_h_pos[11]), .O(\h_pos[11]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[11]_i_6 (.I0(timing_h_pos[10]), .O(\h_pos[11]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[11]_i_7 (.I0(timing_h_pos[9]), .O(\h_pos[11]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[1]_i_1 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[1]), .O(h_pos[1])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[2]_i_1 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[2]), .O(h_pos[2])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[3]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[3]), .O(h_pos[3])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[4]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[4]), .O(h_pos[4])); LUT1 #( .INIT(2'h2)) \h_pos[4]_i_3 (.I0(timing_h_pos[4]), .O(\h_pos[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[4]_i_4 (.I0(timing_h_pos[3]), .O(\h_pos[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[4]_i_5 (.I0(timing_h_pos[2]), .O(\h_pos[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[4]_i_6 (.I0(timing_h_pos[1]), .O(\h_pos[4]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[5]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[5]), .O(h_pos[5])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[6]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[6]), .O(h_pos[6])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[7]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[7]), .O(h_pos[7])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[8]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[8]), .O(h_pos[8])); LUT1 #( .INIT(2'h2)) \h_pos[8]_i_3 (.I0(timing_h_pos[8]), .O(\h_pos[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[8]_i_4 (.I0(timing_h_pos[7]), .O(\h_pos[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[8]_i_5 (.I0(timing_h_pos[6]), .O(\h_pos[8]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \h_pos[8]_i_6 (.I0(timing_h_pos[5]), .O(\h_pos[8]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \h_pos[9]_i_1__0 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .I5(data0[9]), .O(h_pos[9])); FDCE #( .INIT(1'b0)) \h_pos_reg[0] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[0]), .Q(timing_h_pos[0])); FDCE #( .INIT(1'b0)) \h_pos_reg[10] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[10]), .Q(timing_h_pos[10])); FDCE #( .INIT(1'b0)) \h_pos_reg[11] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[11]), .Q(timing_h_pos[11])); CARRY4 \h_pos_reg[11]_i_4 (.CI(\h_pos_reg[8]_i_2_n_0 ), .CO({\NLW_h_pos_reg[11]_i_4_CO_UNCONNECTED [3:2],\h_pos_reg[11]_i_4_n_2 ,\h_pos_reg[11]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_h_pos_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}), .S({1'b0,\h_pos[11]_i_5_n_0 ,\h_pos[11]_i_6_n_0 ,\h_pos[11]_i_7_n_0 })); FDCE #( .INIT(1'b0)) \h_pos_reg[1] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[1]), .Q(timing_h_pos[1])); FDCE #( .INIT(1'b0)) \h_pos_reg[2] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[2]), .Q(timing_h_pos[2])); FDCE #( .INIT(1'b0)) \h_pos_reg[3] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[3]), .Q(timing_h_pos[3])); FDCE #( .INIT(1'b0)) \h_pos_reg[4] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[4]), .Q(timing_h_pos[4])); CARRY4 \h_pos_reg[4]_i_2 (.CI(1'b0), .CO({\h_pos_reg[4]_i_2_n_0 ,\h_pos_reg[4]_i_2_n_1 ,\h_pos_reg[4]_i_2_n_2 ,\h_pos_reg[4]_i_2_n_3 }), .CYINIT(timing_h_pos[0]), .DI({1'b0,1'b0,1'b0,1'b0}), .O(data0[4:1]), .S({\h_pos[4]_i_3_n_0 ,\h_pos[4]_i_4_n_0 ,\h_pos[4]_i_5_n_0 ,\h_pos[4]_i_6_n_0 })); FDCE #( .INIT(1'b0)) \h_pos_reg[5] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[5]), .Q(timing_h_pos[5])); FDCE #( .INIT(1'b0)) \h_pos_reg[6] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[6]), .Q(timing_h_pos[6])); FDCE #( .INIT(1'b0)) \h_pos_reg[7] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[7]), .Q(timing_h_pos[7])); FDCE #( .INIT(1'b0)) \h_pos_reg[8] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[8]), .Q(timing_h_pos[8])); CARRY4 \h_pos_reg[8]_i_2 (.CI(\h_pos_reg[4]_i_2_n_0 ), .CO({\h_pos_reg[8]_i_2_n_0 ,\h_pos_reg[8]_i_2_n_1 ,\h_pos_reg[8]_i_2_n_2 ,\h_pos_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(data0[8:5]), .S({\h_pos[8]_i_3_n_0 ,\h_pos[8]_i_4_n_0 ,\h_pos[8]_i_5_n_0 ,\h_pos[8]_i_6_n_0 })); FDCE #( .INIT(1'b0)) \h_pos_reg[9] (.C(bbstub_pixel_clock), .CE(1'b1), .CLR(AR), .D(h_pos[9]), .Q(timing_h_pos[9])); LUT1 #( .INIT(2'h1)) memctl_i_21 (.I0(reset_n_IBUF), .O(AR)); LUT3 #( .INIT(8'hB4)) odd_pixel_i_1 (.I0(output_fifo1_i_6_n_0), .I1(output_fifo1_i_7_n_0), .I2(odd_pixel), .O(odd_pixel_reg)); LUT6 #( .INIT(64'h0000000000000001)) odd_pixel_i_2 (.I0(odd_pixel_i_3_n_0), .I1(timing_v_pos[2]), .I2(timing_v_pos[5]), .I3(timing_v_pos[3]), .I4(timing_v_pos[4]), .I5(output_fifo1_i_4_n_0), .O(fbc_ovsync)); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'hE)) odd_pixel_i_3 (.I0(timing_v_pos[1]), .I1(timing_v_pos[0]), .O(odd_pixel_i_3_n_0)); LUT6 #( .INIT(64'h00010000FFFFFFFF)) output_fifo1_i_1 (.I0(output_fifo1_i_4_n_0), .I1(timing_v_pos[4]), .I2(timing_v_pos[3]), .I3(timing_v_pos[5]), .I4(output_fifo1_i_5_n_0), .I5(reset_n_IBUF), .O(\int_address_q_reg[23] )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hFE)) output_fifo1_i_10 (.I0(timing_v_pos[5]), .I1(timing_v_pos[3]), .I2(timing_v_pos[4]), .O(output_fifo1_i_10_n_0)); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT4 #( .INIT(16'h4044)) output_fifo1_i_3 (.I0(output_fifo1_i_6_n_0), .I1(output_fifo1_i_7_n_0), .I2(odd_pixel), .I3(zoom_mode_IBUF), .O(rd_en)); LUT5 #( .INIT(32'hFFFFFFFE)) output_fifo1_i_4 (.I0(timing_v_pos[10]), .I1(timing_v_pos[7]), .I2(timing_v_pos[9]), .I3(timing_v_pos[8]), .I4(timing_v_pos[6]), .O(output_fifo1_i_4_n_0)); LUT3 #( .INIT(8'h01)) output_fifo1_i_5 (.I0(timing_v_pos[2]), .I1(timing_v_pos[0]), .I2(timing_v_pos[1]), .O(output_fifo1_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFEFF05051505)) output_fifo1_i_6 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[2]), .I2(timing_h_pos[7]), .I3(output_fifo1_i_8_n_0), .I4(timing_h_pos[4]), .I5(timing_h_pos[11]), .O(output_fifo1_i_6_n_0)); LUT6 #( .INIT(64'h333E333E3F3E333E)) output_fifo1_i_7 (.I0(output_fifo1_i_9_n_0), .I1(timing_v_pos[10]), .I2(\v_pos[2]_i_2_n_0 ), .I3(timing_v_pos[6]), .I4(output_fifo1_i_5_n_0), .I5(output_fifo1_i_10_n_0), .O(output_fifo1_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT5 #( .INIT(32'h00010101)) output_fifo1_i_8 (.I0(timing_h_pos[6]), .I1(timing_h_pos[5]), .I2(timing_h_pos[3]), .I3(timing_h_pos[0]), .I4(timing_h_pos[1]), .O(output_fifo1_i_8_n_0)); LUT6 #( .INIT(64'hFFFFFFFEEEEEEEEE)) output_fifo1_i_9 (.I0(timing_v_pos[4]), .I1(timing_v_pos[5]), .I2(timing_v_pos[2]), .I3(timing_v_pos[0]), .I4(timing_v_pos[1]), .I5(timing_v_pos[3]), .O(output_fifo1_i_9_n_0)); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT4 #( .INIT(16'h0444)) output_fifo2_i_1 (.I0(output_fifo1_i_6_n_0), .I1(output_fifo1_i_7_n_0), .I2(odd_pixel), .I3(zoom_mode_IBUF), .O(output_fifo2)); LUT6 #( .INIT(64'h0F0E0F0F0F0F0F0F)) \v_pos[0]_i_1__0 (.I0(\v_pos[2]_i_2_n_0 ), .I1(\v_pos[2]_i_3_n_0 ), .I2(timing_v_pos[0]), .I3(timing_v_pos[1]), .I4(timing_v_pos[2]), .I5(timing_v_pos[10]), .O(v_pos[0])); LUT5 #( .INIT(32'h00000001)) \v_pos[10]_i_1 (.I0(\h_pos[11]_i_2_n_0 ), .I1(timing_h_pos[3]), .I2(timing_h_pos[5]), .I3(timing_h_pos[6]), .I4(\h_pos[11]_i_3_n_0 ), .O(v_pos0)); LUT4 #( .INIT(16'h0078)) \v_pos[10]_i_2 (.I0(timing_v_pos[9]), .I1(\v_pos[10]_i_3_n_0 ), .I2(timing_v_pos[10]), .I3(\v_pos[10]_i_4_n_0 ), .O(v_pos[10])); LUT5 #( .INIT(32'h80000000)) \v_pos[10]_i_3 (.I0(timing_v_pos[8]), .I1(\v_pos[9]_i_2_n_0 ), .I2(timing_v_pos[5]), .I3(timing_v_pos[6]), .I4(timing_v_pos[7]), .O(\v_pos[10]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \v_pos[10]_i_4 (.I0(\v_pos[10]_i_5_n_0 ), .I1(timing_v_pos[6]), .I2(odd_pixel_i_3_n_0), .I3(timing_v_pos[3]), .I4(timing_v_pos[8]), .I5(\v_pos[10]_i_6_n_0 ), .O(\v_pos[10]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h7)) \v_pos[10]_i_5 (.I0(timing_v_pos[10]), .I1(timing_v_pos[2]), .O(\v_pos[10]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT4 #( .INIT(16'hFFFD)) \v_pos[10]_i_6 (.I0(timing_v_pos[5]), .I1(timing_v_pos[9]), .I2(timing_v_pos[4]), .I3(timing_v_pos[7]), .O(\v_pos[10]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \v_pos[1]_i_1 (.I0(timing_v_pos[1]), .I1(timing_v_pos[0]), .O(v_pos[1])); LUT6 #( .INIT(64'h0FFEF0000FFFF000)) \v_pos[2]_i_1__0 (.I0(\v_pos[2]_i_2_n_0 ), .I1(\v_pos[2]_i_3_n_0 ), .I2(timing_v_pos[0]), .I3(timing_v_pos[1]), .I4(timing_v_pos[2]), .I5(timing_v_pos[10]), .O(v_pos[2])); LUT3 #( .INIT(8'hFE)) \v_pos[2]_i_2 (.I0(timing_v_pos[7]), .I1(timing_v_pos[9]), .I2(timing_v_pos[8]), .O(\v_pos[2]_i_2_n_0 )); LUT4 #( .INIT(16'hEFFF)) \v_pos[2]_i_3 (.I0(timing_v_pos[3]), .I1(timing_v_pos[4]), .I2(timing_v_pos[5]), .I3(timing_v_pos[6]), .O(\v_pos[2]_i_3_n_0 )); LUT4 #( .INIT(16'h6AAA)) \v_pos[3]_i_1 (.I0(timing_v_pos[3]), .I1(timing_v_pos[0]), .I2(timing_v_pos[1]), .I3(timing_v_pos[2]), .O(v_pos[3])); LUT5 #( .INIT(32'h7FFF8000)) \v_pos[4]_i_1 (.I0(timing_v_pos[2]), .I1(timing_v_pos[1]), .I2(timing_v_pos[0]), .I3(timing_v_pos[3]), .I4(timing_v_pos[4]), .O(v_pos[4])); LUT3 #( .INIT(8'h06)) \v_pos[5]_i_1 (.I0(\v_pos[9]_i_2_n_0 ), .I1(timing_v_pos[5]), .I2(\v_pos[10]_i_4_n_0 ), .O(v_pos[5])); LUT4 #( .INIT(16'h0078)) \v_pos[6]_i_1 (.I0(timing_v_pos[5]), .I1(\v_pos[9]_i_2_n_0 ), .I2(timing_v_pos[6]), .I3(\v_pos[10]_i_4_n_0 ), .O(v_pos[6])); LUT4 #( .INIT(16'h6AAA)) \v_pos[7]_i_1 (.I0(timing_v_pos[7]), .I1(timing_v_pos[6]), .I2(timing_v_pos[5]), .I3(\v_pos[9]_i_2_n_0 ), .O(v_pos[7])); LUT5 #( .INIT(32'h6AAAAAAA)) \v_pos[8]_i_1 (.I0(timing_v_pos[8]), .I1(\v_pos[9]_i_2_n_0 ), .I2(timing_v_pos[5]), .I3(timing_v_pos[6]), .I4(timing_v_pos[7]), .O(v_pos[8])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \v_pos[9]_i_1 (.I0(timing_v_pos[9]), .I1(timing_v_pos[7]), .I2(timing_v_pos[6]), .I3(timing_v_pos[5]), .I4(\v_pos[9]_i_2_n_0 ), .I5(timing_v_pos[8]), .O(v_pos[9])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT5 #( .INIT(32'h80000000)) \v_pos[9]_i_2 (.I0(timing_v_pos[4]), .I1(timing_v_pos[3]), .I2(timing_v_pos[0]), .I3(timing_v_pos[1]), .I4(timing_v_pos[2]), .O(\v_pos[9]_i_2_n_0 )); FDCE #( .INIT(1'b0)) \v_pos_reg[0] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[0]), .Q(timing_v_pos[0])); FDCE #( .INIT(1'b0)) \v_pos_reg[10] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[10]), .Q(timing_v_pos[10])); FDCE #( .INIT(1'b0)) \v_pos_reg[1] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[1]), .Q(timing_v_pos[1])); FDCE #( .INIT(1'b0)) \v_pos_reg[2] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[2]), .Q(timing_v_pos[2])); FDCE #( .INIT(1'b0)) \v_pos_reg[3] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[3]), .Q(timing_v_pos[3])); FDCE #( .INIT(1'b0)) \v_pos_reg[4] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[4]), .Q(timing_v_pos[4])); FDCE #( .INIT(1'b0)) \v_pos_reg[5] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[5]), .Q(timing_v_pos[5])); FDCE #( .INIT(1'b0)) \v_pos_reg[6] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[6]), .Q(timing_v_pos[6])); FDCE #( .INIT(1'b0)) \v_pos_reg[7] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[7]), .Q(timing_v_pos[7])); FDCE #( .INIT(1'b0)) \v_pos_reg[8] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[8]), .Q(timing_v_pos[8])); FDCE #( .INIT(1'b0)) \v_pos_reg[9] (.C(bbstub_pixel_clock), .CE(v_pos0), .CLR(AR), .D(v_pos[9]), .Q(timing_v_pos[9])); endmodule (* ORIG_REF_NAME = "video_timing_ctrl" *) module video_timing_ctrl__parameterized0 (wr_en, rst, reset_n_IBUF, CLK, AR); output wr_en; output rst; input reset_n_IBUF; input CLK; input [0:0]AR; wire [0:0]AR; wire CLK; wire [10:0]h_pos; wire \h_pos[10]_i_2_n_0 ; wire \h_pos[10]_i_3_n_0 ; wire \h_pos[10]_i_4_n_0 ; wire \h_pos[2]_i_2_n_0 ; wire \h_pos[2]_i_3_n_0 ; wire \h_pos[8]_i_2_n_0 ; wire \h_pos_reg_n_0_[0] ; wire \h_pos_reg_n_0_[10] ; wire \h_pos_reg_n_0_[1] ; wire \h_pos_reg_n_0_[2] ; wire \h_pos_reg_n_0_[3] ; wire \h_pos_reg_n_0_[4] ; wire \h_pos_reg_n_0_[5] ; wire \h_pos_reg_n_0_[6] ; wire \h_pos_reg_n_0_[7] ; wire \h_pos_reg_n_0_[8] ; wire \h_pos_reg_n_0_[9] ; wire input_fifo_i_10_n_0; wire input_fifo_i_11_n_0; wire input_fifo_i_12_n_0; wire input_fifo_i_3_n_0; wire input_fifo_i_4_n_0; wire input_fifo_i_5_n_0; wire input_fifo_i_6_n_0; wire input_fifo_i_7_n_0; wire input_fifo_i_8_n_0; wire input_fifo_i_9_n_0; wire reset_n_IBUF; wire rst; wire [11:0]v_pos; wire \v_pos[11]_i_1_n_0 ; wire \v_pos[11]_i_3_n_0 ; wire \v_pos[11]_i_4_n_0 ; wire \v_pos[11]_i_6_n_0 ; wire \v_pos[11]_i_7_n_0 ; wire \v_pos[11]_i_8_n_0 ; wire \v_pos[4]_i_3_n_0 ; wire \v_pos[4]_i_4_n_0 ; wire \v_pos[4]_i_5_n_0 ; wire \v_pos[4]_i_6_n_0 ; wire \v_pos[8]_i_3_n_0 ; wire \v_pos[8]_i_4_n_0 ; wire \v_pos[8]_i_5_n_0 ; wire \v_pos[8]_i_6_n_0 ; wire \v_pos_reg[11]_i_5_n_2 ; wire \v_pos_reg[11]_i_5_n_3 ; wire \v_pos_reg[11]_i_5_n_5 ; wire \v_pos_reg[11]_i_5_n_6 ; wire \v_pos_reg[11]_i_5_n_7 ; wire \v_pos_reg[4]_i_2_n_0 ; wire \v_pos_reg[4]_i_2_n_1 ; wire \v_pos_reg[4]_i_2_n_2 ; wire \v_pos_reg[4]_i_2_n_3 ; wire \v_pos_reg[4]_i_2_n_4 ; wire \v_pos_reg[4]_i_2_n_5 ; wire \v_pos_reg[4]_i_2_n_6 ; wire \v_pos_reg[4]_i_2_n_7 ; wire \v_pos_reg[8]_i_2_n_0 ; wire \v_pos_reg[8]_i_2_n_1 ; wire \v_pos_reg[8]_i_2_n_2 ; wire \v_pos_reg[8]_i_2_n_3 ; wire \v_pos_reg[8]_i_2_n_4 ; wire \v_pos_reg[8]_i_2_n_5 ; wire \v_pos_reg[8]_i_2_n_6 ; wire \v_pos_reg[8]_i_2_n_7 ; wire \v_pos_reg_n_0_[0] ; wire \v_pos_reg_n_0_[10] ; wire \v_pos_reg_n_0_[11] ; wire \v_pos_reg_n_0_[1] ; wire \v_pos_reg_n_0_[2] ; wire \v_pos_reg_n_0_[3] ; wire \v_pos_reg_n_0_[4] ; wire \v_pos_reg_n_0_[5] ; wire \v_pos_reg_n_0_[6] ; wire \v_pos_reg_n_0_[7] ; wire \v_pos_reg_n_0_[8] ; wire \v_pos_reg_n_0_[9] ; wire wr_en; wire [3:2]\NLW_v_pos_reg[11]_i_5_CO_UNCONNECTED ; wire [3:3]\NLW_v_pos_reg[11]_i_5_O_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair24" *) LUT4 #( .INIT(16'h0D0F)) \h_pos[0]_i_1__0 (.I0(\h_pos[2]_i_2_n_0 ), .I1(\h_pos[2]_i_3_n_0 ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos_reg_n_0_[5] ), .O(h_pos[0])); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT4 #( .INIT(16'h2A80)) \h_pos[10]_i_1 (.I0(\h_pos[10]_i_2_n_0 ), .I1(\h_pos[10]_i_3_n_0 ), .I2(\h_pos_reg_n_0_[9] ), .I3(\h_pos_reg_n_0_[10] ), .O(h_pos[10])); LUT5 #( .INIT(32'hFFFFFFF7)) \h_pos[10]_i_2 (.I0(\h_pos_reg_n_0_[9] ), .I1(\h_pos_reg_n_0_[10] ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos[10]_i_4_n_0 ), .I4(\h_pos[2]_i_3_n_0 ), .O(\h_pos[10]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT5 #( .INIT(32'h08000000)) \h_pos[10]_i_3 (.I0(\h_pos_reg_n_0_[8] ), .I1(\h_pos_reg_n_0_[7] ), .I2(\h_pos[8]_i_2_n_0 ), .I3(\h_pos_reg_n_0_[5] ), .I4(\h_pos_reg_n_0_[6] ), .O(\h_pos[10]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT4 #( .INIT(16'h7FFF)) \h_pos[10]_i_4 (.I0(\h_pos_reg_n_0_[7] ), .I1(\h_pos_reg_n_0_[8] ), .I2(\h_pos_reg_n_0_[5] ), .I3(\h_pos_reg_n_0_[6] ), .O(\h_pos[10]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'h0D0FF0F0)) \h_pos[1]_i_1__0 (.I0(\h_pos[2]_i_2_n_0 ), .I1(\h_pos[2]_i_3_n_0 ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos_reg_n_0_[5] ), .I4(\h_pos_reg_n_0_[1] ), .O(h_pos[1])); LUT6 #( .INIT(64'h0D0FFDFFF0F00000)) \h_pos[2]_i_1__0 (.I0(\h_pos[2]_i_2_n_0 ), .I1(\h_pos[2]_i_3_n_0 ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos_reg_n_0_[5] ), .I4(\h_pos_reg_n_0_[1] ), .I5(\h_pos_reg_n_0_[2] ), .O(h_pos[2])); LUT5 #( .INIT(32'h80000000)) \h_pos[2]_i_2 (.I0(\h_pos_reg_n_0_[6] ), .I1(\h_pos_reg_n_0_[9] ), .I2(\h_pos_reg_n_0_[7] ), .I3(\h_pos_reg_n_0_[8] ), .I4(\h_pos_reg_n_0_[10] ), .O(\h_pos[2]_i_2_n_0 )); LUT4 #( .INIT(16'hFFF7)) \h_pos[2]_i_3 (.I0(\h_pos_reg_n_0_[2] ), .I1(\h_pos_reg_n_0_[1] ), .I2(\h_pos_reg_n_0_[3] ), .I3(\h_pos_reg_n_0_[4] ), .O(\h_pos[2]_i_3_n_0 )); LUT4 #( .INIT(16'h7F80)) \h_pos[3]_i_1 (.I0(\h_pos_reg_n_0_[0] ), .I1(\h_pos_reg_n_0_[1] ), .I2(\h_pos_reg_n_0_[2] ), .I3(\h_pos_reg_n_0_[3] ), .O(h_pos[3])); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'h6AAAAAAA)) \h_pos[4]_i_1 (.I0(\h_pos_reg_n_0_[4] ), .I1(\h_pos_reg_n_0_[0] ), .I2(\h_pos_reg_n_0_[1] ), .I3(\h_pos_reg_n_0_[2] ), .I4(\h_pos_reg_n_0_[3] ), .O(h_pos[4])); LUT3 #( .INIT(8'h82)) \h_pos[5]_i_1 (.I0(\h_pos[10]_i_2_n_0 ), .I1(\h_pos[8]_i_2_n_0 ), .I2(\h_pos_reg_n_0_[5] ), .O(h_pos[5])); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT4 #( .INIT(16'hA208)) \h_pos[6]_i_1 (.I0(\h_pos[10]_i_2_n_0 ), .I1(\h_pos_reg_n_0_[5] ), .I2(\h_pos[8]_i_2_n_0 ), .I3(\h_pos_reg_n_0_[6] ), .O(h_pos[6])); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT5 #( .INIT(32'h8AAA2000)) \h_pos[7]_i_1 (.I0(\h_pos[10]_i_2_n_0 ), .I1(\h_pos[8]_i_2_n_0 ), .I2(\h_pos_reg_n_0_[5] ), .I3(\h_pos_reg_n_0_[6] ), .I4(\h_pos_reg_n_0_[7] ), .O(h_pos[7])); LUT6 #( .INIT(64'hAA2AAAAA00800000)) \h_pos[8]_i_1 (.I0(\h_pos[10]_i_2_n_0 ), .I1(\h_pos_reg_n_0_[6] ), .I2(\h_pos_reg_n_0_[5] ), .I3(\h_pos[8]_i_2_n_0 ), .I4(\h_pos_reg_n_0_[7] ), .I5(\h_pos_reg_n_0_[8] ), .O(h_pos[8])); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'h7FFFFFFF)) \h_pos[8]_i_2 (.I0(\h_pos_reg_n_0_[2] ), .I1(\h_pos_reg_n_0_[1] ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos_reg_n_0_[3] ), .I4(\h_pos_reg_n_0_[4] ), .O(\h_pos[8]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h28)) \h_pos[9]_i_1 (.I0(\h_pos[10]_i_2_n_0 ), .I1(\h_pos[10]_i_3_n_0 ), .I2(\h_pos_reg_n_0_[9] ), .O(h_pos[9])); FDCE #( .INIT(1'b0)) \h_pos_reg[0] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[0]), .Q(\h_pos_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \h_pos_reg[10] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[10]), .Q(\h_pos_reg_n_0_[10] )); FDCE #( .INIT(1'b0)) \h_pos_reg[1] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[1]), .Q(\h_pos_reg_n_0_[1] )); FDCE #( .INIT(1'b0)) \h_pos_reg[2] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[2]), .Q(\h_pos_reg_n_0_[2] )); FDCE #( .INIT(1'b0)) \h_pos_reg[3] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[3]), .Q(\h_pos_reg_n_0_[3] )); FDCE #( .INIT(1'b0)) \h_pos_reg[4] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[4]), .Q(\h_pos_reg_n_0_[4] )); FDCE #( .INIT(1'b0)) \h_pos_reg[5] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[5]), .Q(\h_pos_reg_n_0_[5] )); FDCE #( .INIT(1'b0)) \h_pos_reg[6] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[6]), .Q(\h_pos_reg_n_0_[6] )); FDCE #( .INIT(1'b0)) \h_pos_reg[7] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[7]), .Q(\h_pos_reg_n_0_[7] )); FDCE #( .INIT(1'b0)) \h_pos_reg[8] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[8]), .Q(\h_pos_reg_n_0_[8] )); FDCE #( .INIT(1'b0)) \h_pos_reg[9] (.C(CLK), .CE(1'b1), .CLR(AR), .D(h_pos[9]), .Q(\h_pos_reg_n_0_[9] )); LUT6 #( .INIT(64'h00010000FFFFFFFF)) input_fifo_i_1 (.I0(input_fifo_i_3_n_0), .I1(\v_pos_reg_n_0_[5] ), .I2(\v_pos_reg_n_0_[6] ), .I3(\v_pos_reg_n_0_[4] ), .I4(input_fifo_i_4_n_0), .I5(reset_n_IBUF), .O(rst)); LUT6 #( .INIT(64'h0000000000FF57FF)) input_fifo_i_10 (.I0(\h_pos_reg_n_0_[2] ), .I1(\h_pos_reg_n_0_[1] ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos_reg_n_0_[4] ), .I4(\h_pos_reg_n_0_[3] ), .I5(\h_pos_reg_n_0_[5] ), .O(input_fifo_i_10_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFE000)) input_fifo_i_11 (.I0(\h_pos_reg_n_0_[1] ), .I1(\h_pos_reg_n_0_[2] ), .I2(\h_pos_reg_n_0_[4] ), .I3(\h_pos_reg_n_0_[3] ), .I4(\h_pos_reg_n_0_[10] ), .I5(\h_pos_reg_n_0_[9] ), .O(input_fifo_i_11_n_0)); LUT4 #( .INIT(16'h0001)) input_fifo_i_12 (.I0(\h_pos_reg_n_0_[7] ), .I1(\h_pos_reg_n_0_[8] ), .I2(\h_pos_reg_n_0_[5] ), .I3(\h_pos_reg_n_0_[6] ), .O(input_fifo_i_12_n_0)); LUT6 #( .INIT(64'h000000001111FFFB)) input_fifo_i_2 (.I0(input_fifo_i_5_n_0), .I1(input_fifo_i_6_n_0), .I2(\v_pos_reg_n_0_[10] ), .I3(\v_pos_reg_n_0_[7] ), .I4(\v_pos_reg_n_0_[11] ), .I5(input_fifo_i_7_n_0), .O(wr_en)); LUT4 #( .INIT(16'hFFFE)) input_fifo_i_3 (.I0(\v_pos_reg_n_0_[7] ), .I1(\v_pos_reg_n_0_[10] ), .I2(\v_pos_reg_n_0_[9] ), .I3(\v_pos_reg_n_0_[8] ), .O(input_fifo_i_3_n_0)); LUT5 #( .INIT(32'h00000007)) input_fifo_i_4 (.I0(\v_pos_reg_n_0_[0] ), .I1(\v_pos_reg_n_0_[1] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos_reg_n_0_[2] ), .O(input_fifo_i_4_n_0)); LUT2 #( .INIT(4'hE)) input_fifo_i_5 (.I0(\v_pos_reg_n_0_[8] ), .I1(\v_pos_reg_n_0_[9] ), .O(input_fifo_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFC11FFFFFF01)) input_fifo_i_6 (.I0(\v_pos_reg_n_0_[11] ), .I1(input_fifo_i_8_n_0), .I2(\v_pos_reg_n_0_[4] ), .I3(\v_pos_reg_n_0_[7] ), .I4(\v_pos_reg_n_0_[10] ), .I5(input_fifo_i_9_n_0), .O(input_fifo_i_6_n_0)); LUT4 #( .INIT(16'h4F44)) input_fifo_i_7 (.I0(input_fifo_i_10_n_0), .I1(\h_pos[2]_i_2_n_0 ), .I2(input_fifo_i_11_n_0), .I3(input_fifo_i_12_n_0), .O(input_fifo_i_7_n_0)); LUT2 #( .INIT(4'hE)) input_fifo_i_8 (.I0(\v_pos_reg_n_0_[5] ), .I1(\v_pos_reg_n_0_[6] ), .O(input_fifo_i_8_n_0)); LUT3 #( .INIT(8'h1F)) input_fifo_i_9 (.I0(\v_pos_reg_n_0_[2] ), .I1(\v_pos_reg_n_0_[1] ), .I2(\v_pos_reg_n_0_[3] ), .O(input_fifo_i_9_n_0)); LUT1 #( .INIT(2'h1)) \v_pos[0]_i_1 (.I0(\v_pos_reg_n_0_[0] ), .O(v_pos[0])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[10]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[11]_i_5_n_6 ), .O(v_pos[10])); LUT4 #( .INIT(16'h0200)) \v_pos[11]_i_1 (.I0(\h_pos[2]_i_2_n_0 ), .I1(\h_pos[2]_i_3_n_0 ), .I2(\h_pos_reg_n_0_[0] ), .I3(\h_pos_reg_n_0_[5] ), .O(\v_pos[11]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[11]_i_2 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[11]_i_5_n_5 ), .O(v_pos[11])); LUT4 #( .INIT(16'hFFEF)) \v_pos[11]_i_3 (.I0(\v_pos_reg_n_0_[9] ), .I1(\v_pos_reg_n_0_[8] ), .I2(\v_pos_reg_n_0_[0] ), .I3(\v_pos_reg_n_0_[1] ), .O(\v_pos[11]_i_3_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \v_pos[11]_i_4 (.I0(\v_pos_reg_n_0_[5] ), .I1(\v_pos_reg_n_0_[6] ), .I2(\v_pos_reg_n_0_[4] ), .I3(\v_pos_reg_n_0_[7] ), .I4(\v_pos_reg_n_0_[10] ), .O(\v_pos[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[11]_i_6 (.I0(\v_pos_reg_n_0_[11] ), .O(\v_pos[11]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[11]_i_7 (.I0(\v_pos_reg_n_0_[10] ), .O(\v_pos[11]_i_7_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[11]_i_8 (.I0(\v_pos_reg_n_0_[9] ), .O(\v_pos[11]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[1]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[4]_i_2_n_7 ), .O(v_pos[1])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[2]_i_1 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[4]_i_2_n_6 ), .O(v_pos[2])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[3]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[4]_i_2_n_5 ), .O(v_pos[3])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[4]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[4]_i_2_n_4 ), .O(v_pos[4])); LUT1 #( .INIT(2'h2)) \v_pos[4]_i_3 (.I0(\v_pos_reg_n_0_[4] ), .O(\v_pos[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[4]_i_4 (.I0(\v_pos_reg_n_0_[3] ), .O(\v_pos[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[4]_i_5 (.I0(\v_pos_reg_n_0_[2] ), .O(\v_pos[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[4]_i_6 (.I0(\v_pos_reg_n_0_[1] ), .O(\v_pos[4]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[5]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[8]_i_2_n_7 ), .O(v_pos[5])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[6]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[8]_i_2_n_6 ), .O(v_pos[6])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[7]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[8]_i_2_n_5 ), .O(v_pos[7])); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[8]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[8]_i_2_n_4 ), .O(v_pos[8])); LUT1 #( .INIT(2'h2)) \v_pos[8]_i_3 (.I0(\v_pos_reg_n_0_[8] ), .O(\v_pos[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[8]_i_4 (.I0(\v_pos_reg_n_0_[7] ), .O(\v_pos[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[8]_i_5 (.I0(\v_pos_reg_n_0_[6] ), .O(\v_pos[8]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \v_pos[8]_i_6 (.I0(\v_pos_reg_n_0_[5] ), .O(\v_pos[8]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFBFFF00000000)) \v_pos[9]_i_1__0 (.I0(\v_pos[11]_i_3_n_0 ), .I1(\v_pos_reg_n_0_[2] ), .I2(\v_pos_reg_n_0_[11] ), .I3(\v_pos_reg_n_0_[3] ), .I4(\v_pos[11]_i_4_n_0 ), .I5(\v_pos_reg[11]_i_5_n_7 ), .O(v_pos[9])); FDCE #( .INIT(1'b0)) \v_pos_reg[0] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[0]), .Q(\v_pos_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \v_pos_reg[10] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[10]), .Q(\v_pos_reg_n_0_[10] )); FDCE #( .INIT(1'b0)) \v_pos_reg[11] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[11]), .Q(\v_pos_reg_n_0_[11] )); CARRY4 \v_pos_reg[11]_i_5 (.CI(\v_pos_reg[8]_i_2_n_0 ), .CO({\NLW_v_pos_reg[11]_i_5_CO_UNCONNECTED [3:2],\v_pos_reg[11]_i_5_n_2 ,\v_pos_reg[11]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_v_pos_reg[11]_i_5_O_UNCONNECTED [3],\v_pos_reg[11]_i_5_n_5 ,\v_pos_reg[11]_i_5_n_6 ,\v_pos_reg[11]_i_5_n_7 }), .S({1'b0,\v_pos[11]_i_6_n_0 ,\v_pos[11]_i_7_n_0 ,\v_pos[11]_i_8_n_0 })); FDCE #( .INIT(1'b0)) \v_pos_reg[1] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[1]), .Q(\v_pos_reg_n_0_[1] )); FDCE #( .INIT(1'b0)) \v_pos_reg[2] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[2]), .Q(\v_pos_reg_n_0_[2] )); FDCE #( .INIT(1'b0)) \v_pos_reg[3] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[3]), .Q(\v_pos_reg_n_0_[3] )); FDCE #( .INIT(1'b0)) \v_pos_reg[4] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[4]), .Q(\v_pos_reg_n_0_[4] )); CARRY4 \v_pos_reg[4]_i_2 (.CI(1'b0), .CO({\v_pos_reg[4]_i_2_n_0 ,\v_pos_reg[4]_i_2_n_1 ,\v_pos_reg[4]_i_2_n_2 ,\v_pos_reg[4]_i_2_n_3 }), .CYINIT(\v_pos_reg_n_0_[0] ), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\v_pos_reg[4]_i_2_n_4 ,\v_pos_reg[4]_i_2_n_5 ,\v_pos_reg[4]_i_2_n_6 ,\v_pos_reg[4]_i_2_n_7 }), .S({\v_pos[4]_i_3_n_0 ,\v_pos[4]_i_4_n_0 ,\v_pos[4]_i_5_n_0 ,\v_pos[4]_i_6_n_0 })); FDCE #( .INIT(1'b0)) \v_pos_reg[5] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[5]), .Q(\v_pos_reg_n_0_[5] )); FDCE #( .INIT(1'b0)) \v_pos_reg[6] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[6]), .Q(\v_pos_reg_n_0_[6] )); FDCE #( .INIT(1'b0)) \v_pos_reg[7] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[7]), .Q(\v_pos_reg_n_0_[7] )); FDCE #( .INIT(1'b0)) \v_pos_reg[8] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[8]), .Q(\v_pos_reg_n_0_[8] )); CARRY4 \v_pos_reg[8]_i_2 (.CI(\v_pos_reg[4]_i_2_n_0 ), .CO({\v_pos_reg[8]_i_2_n_0 ,\v_pos_reg[8]_i_2_n_1 ,\v_pos_reg[8]_i_2_n_2 ,\v_pos_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\v_pos_reg[8]_i_2_n_4 ,\v_pos_reg[8]_i_2_n_5 ,\v_pos_reg[8]_i_2_n_6 ,\v_pos_reg[8]_i_2_n_7 }), .S({\v_pos[8]_i_3_n_0 ,\v_pos[8]_i_4_n_0 ,\v_pos[8]_i_5_n_0 ,\v_pos[8]_i_6_n_0 })); FDCE #( .INIT(1'b0)) \v_pos_reg[9] (.C(CLK), .CE(\v_pos[11]_i_1_n_0 ), .CLR(AR), .D(v_pos[9]), .Q(\v_pos_reg_n_0_[9] )); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module fb_input_fifo_blk_mem_gen_generic_cstr (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [255:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [63:0]din; wire [8:0]Q; wire [63:0]din; wire [255:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r (.Q(Q), .din(din[17:0]), .dout({dout[209:192],dout[145:128],dout[81:64],dout[17:0]}), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fb_input_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.Q(Q), .din(din[35:18]), .dout({dout[227:210],dout[163:146],dout[99:82],dout[35:18]}), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fb_input_fifo_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r (.Q(Q), .din(din[53:36]), .dout({dout[245:228],dout[181:164],dout[117:100],dout[53:36]}), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fb_input_fifo_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r (.Q(Q), .din(din[63:54]), .dout({dout[255:246],dout[191:182],dout[127:118],dout[63:54]}), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fb_input_fifo_blk_mem_gen_prim_width (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [71:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [17:0]din; wire [8:0]Q; wire [17:0]din; wire [71:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fb_input_fifo_blk_mem_gen_prim_width__parameterized0 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [71:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [17:0]din; wire [8:0]Q; wire [17:0]din; wire [71:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fb_input_fifo_blk_mem_gen_prim_width__parameterized1 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [71:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [17:0]din; wire [8:0]Q; wire [17:0]din; wire [71:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fb_input_fifo_blk_mem_gen_prim_width__parameterized2 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [39:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [9:0]din; wire [8:0]Q; wire [9:0]din; wire [39:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fb_input_fifo_blk_mem_gen_prim_wrapper (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [71:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [17:0]din; wire [8:0]Q; wire [17:0]din; wire [71:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(18)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,din[17],din[8]}), .DOADO({dout[52:45],dout[43:36],dout[70:63],dout[61:54]}), .DOBDO({dout[16:9],dout[7:0],dout[34:27],dout[25:18]}), .DOPADOP({dout[53],dout[44],dout[71],dout[62]}), .DOPBDOP({dout[17],dout[8],dout[35],dout[26]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(tmp_ram_rd_en), .ENBWREN(ram_full_fb_i_reg), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(out), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized0 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [71:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [17:0]din; wire [8:0]Q; wire [17:0]din; wire [71:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(18)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,din[17],din[8]}), .DOADO({dout[52:45],dout[43:36],dout[70:63],dout[61:54]}), .DOBDO({dout[16:9],dout[7:0],dout[34:27],dout[25:18]}), .DOPADOP({dout[53],dout[44],dout[71],dout[62]}), .DOPBDOP({dout[17],dout[8],dout[35],dout[26]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(tmp_ram_rd_en), .ENBWREN(ram_full_fb_i_reg), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(out), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized1 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [71:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [17:0]din; wire [8:0]Q; wire [17:0]din; wire [71:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(18)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,din[17],din[8]}), .DOADO({dout[52:45],dout[43:36],dout[70:63],dout[61:54]}), .DOBDO({dout[16:9],dout[7:0],dout[34:27],dout[25:18]}), .DOPADOP({dout[53],dout[44],dout[71],dout[62]}), .DOPBDOP({dout[17],dout[8],dout[35],dout[26]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(tmp_ram_rd_en), .ENBWREN(ram_full_fb_i_reg), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(out), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized2 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [39:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [9:0]din; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_21 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_22 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_23 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_29 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_30 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_31 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_37 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_38 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_39 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_45 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_46 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_47 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_53 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_54 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_55 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_61 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_62 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_63 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_69 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_70 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_71 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_77 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_78 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_79 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_85 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_86 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_87 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_88 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_89 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_90 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_91 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_92 ; wire [8:0]Q; wire [9:0]din; wire [39:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(18)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[9:5],1'b0,1'b0,1'b0,din[4:0]}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_23 ,dout[29:25],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_31 ,dout[24:20],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_39 ,dout[39:35],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_47 ,dout[34:30]}), .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_53 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_54 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_55 ,dout[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_61 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_62 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_63 ,dout[4:0],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_69 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_70 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_71 ,dout[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_78 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_79 ,dout[14:10]}), .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_88 }), .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_92 }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(tmp_ram_rd_en), .ENBWREN(ram_full_fb_i_reg), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(out), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module fb_input_fifo_blk_mem_gen_top (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [255:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [63:0]din; wire [8:0]Q; wire [63:0]din; wire [255:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_generic_cstr \valid.cstr (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *) module fb_input_fifo_blk_mem_gen_v8_3_4 (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [255:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [63:0]din; wire [8:0]Q; wire [63:0]din; wire [255:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *) module fb_input_fifo_blk_mem_gen_v8_3_4_synth (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [255:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [63:0]din; wire [8:0]Q; wire [63:0]din; wire [255:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "clk_x_pntrs" *) module fb_input_fifo_clk_x_pntrs (S, WR_PNTR_RD, \gdiff.diff_pntr_pad_reg[8] , \gdiff.diff_pntr_pad_reg[9] , ram_full_fb_i_reg, RD_PNTR_WR, ram_full_fb_i_reg_0, v1_reg, v1_reg_0, Q, \gic0.gc0.count_d1_reg[10] , D, \gc0.count_reg[7] , \gic0.gc0.count_d2_reg[10] , wr_clk, AR, rd_clk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); output [3:0]S; output [8:0]WR_PNTR_RD; output [3:0]\gdiff.diff_pntr_pad_reg[8] ; output [0:0]\gdiff.diff_pntr_pad_reg[9] ; output ram_full_fb_i_reg; output [7:0]RD_PNTR_WR; output ram_full_fb_i_reg_0; output [3:0]v1_reg; output [3:0]v1_reg_0; input [8:0]Q; input [0:0]\gic0.gc0.count_d1_reg[10] ; input [0:0]D; input [7:0]\gc0.count_reg[7] ; input [10:0]\gic0.gc0.count_d2_reg[10] ; input wr_clk; input [0:0]AR; input rd_clk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire [0:0]AR; wire [0:0]D; wire [8:0]Q; wire [7:0]RD_PNTR_WR; wire [3:0]S; wire [8:0]WR_PNTR_RD; wire [9:0]bin2gray; wire [7:0]\gc0.count_reg[7] ; wire [3:0]\gdiff.diff_pntr_pad_reg[8] ; wire [0:0]\gdiff.diff_pntr_pad_reg[9] ; wire [0:0]\gic0.gc0.count_d1_reg[10] ; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ; wire [8:2]gray2bin; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire p_0_out; wire [8:8]p_23_out; wire [10:0]p_3_out; wire [8:0]p_4_out; wire [10:10]p_5_out; wire [8:8]p_6_out; wire ram_full_fb_i_reg; wire ram_full_fb_i_reg_0; wire rd_clk; wire [8:0]rd_pntr_gc; wire [3:0]v1_reg; wire [3:0]v1_reg_0; wire wr_clk; wire [10:0]wr_pntr_gc; LUT4 #( .INIT(16'h9009)) \gmux.gm[0].gm1.m1_i_1 (.I0(WR_PNTR_RD[0]), .I1(Q[0]), .I2(WR_PNTR_RD[1]), .I3(Q[1]), .O(v1_reg[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[0].gm1.m1_i_1__0 (.I0(WR_PNTR_RD[0]), .I1(\gc0.count_reg[7] [0]), .I2(WR_PNTR_RD[1]), .I3(\gc0.count_reg[7] [1]), .O(v1_reg_0[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1 (.I0(WR_PNTR_RD[2]), .I1(Q[2]), .I2(WR_PNTR_RD[3]), .I3(Q[3]), .O(v1_reg[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__0 (.I0(WR_PNTR_RD[2]), .I1(\gc0.count_reg[7] [2]), .I2(WR_PNTR_RD[3]), .I3(\gc0.count_reg[7] [3]), .O(v1_reg_0[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1 (.I0(WR_PNTR_RD[4]), .I1(Q[4]), .I2(WR_PNTR_RD[5]), .I3(Q[5]), .O(v1_reg[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__0 (.I0(WR_PNTR_RD[4]), .I1(\gc0.count_reg[7] [4]), .I2(WR_PNTR_RD[5]), .I3(\gc0.count_reg[7] [5]), .O(v1_reg_0[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1 (.I0(WR_PNTR_RD[6]), .I1(Q[6]), .I2(WR_PNTR_RD[7]), .I3(Q[7]), .O(v1_reg[3])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__0 (.I0(WR_PNTR_RD[6]), .I1(\gc0.count_reg[7] [6]), .I2(WR_PNTR_RD[7]), .I3(\gc0.count_reg[7] [7]), .O(v1_reg_0[3])); LUT2 #( .INIT(4'h9)) \gmux.gm[5].gms.ms_i_1 (.I0(p_23_out), .I1(\gic0.gc0.count_d1_reg[10] ), .O(ram_full_fb_i_reg)); LUT2 #( .INIT(4'h9)) \gmux.gm[5].gms.ms_i_1__0 (.I0(p_23_out), .I1(D), .O(ram_full_fb_i_reg_0)); fb_input_fifo_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst (.D(p_3_out), .Q(wr_pntr_gc), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .rd_clk(rd_clk)); fb_input_fifo_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst (.AR(AR), .D(p_4_out), .Q(rd_pntr_gc), .wr_clk(wr_clk)); fb_input_fifo_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst (.D(p_3_out), .\gnxpm_cdc.wr_pntr_bin_reg[9] ({p_0_out,gray2bin}), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .out(p_5_out), .rd_clk(rd_clk)); fb_input_fifo_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst (.AR(AR), .D(p_4_out), .\gnxpm_cdc.rd_pntr_bin_reg[7] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 }), .out(p_6_out), .wr_clk(wr_clk)); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), .Q(RD_PNTR_WR[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), .Q(RD_PNTR_WR[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), .Q(RD_PNTR_WR[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), .Q(RD_PNTR_WR[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), .Q(RD_PNTR_WR[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), .Q(RD_PNTR_WR[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), .Q(RD_PNTR_WR[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), .Q(RD_PNTR_WR[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(p_6_out), .Q(p_23_out)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[0]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[1]_i_1 (.I0(Q[1]), .I1(Q[2]), .O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[2]_i_1 (.I0(Q[2]), .I1(Q[3]), .O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[3]_i_1 (.I0(Q[3]), .I1(Q[4]), .O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[4]_i_1 (.I0(Q[4]), .I1(Q[5]), .O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[5]_i_1 (.I0(Q[5]), .I1(Q[6]), .O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[6]_i_1 (.I0(Q[6]), .I1(Q[7]), .O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[7]_i_1 (.I0(Q[7]), .I1(Q[8]), .O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 )); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ), .Q(rd_pntr_gc[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ), .Q(rd_pntr_gc[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ), .Q(rd_pntr_gc[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ), .Q(rd_pntr_gc[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ), .Q(rd_pntr_gc[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ), .Q(rd_pntr_gc[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ), .Q(rd_pntr_gc[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ), .Q(rd_pntr_gc[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[8]), .Q(rd_pntr_gc[8])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[10] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(p_5_out), .Q(WR_PNTR_RD[8])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[2]), .Q(WR_PNTR_RD[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[3]), .Q(WR_PNTR_RD[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[4]), .Q(WR_PNTR_RD[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[5]), .Q(WR_PNTR_RD[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[6]), .Q(WR_PNTR_RD[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[7]), .Q(WR_PNTR_RD[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[8]), .Q(WR_PNTR_RD[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[9] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(p_0_out), .Q(WR_PNTR_RD[7])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[0]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [0]), .I1(\gic0.gc0.count_d2_reg[10] [1]), .O(bin2gray[0])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[1]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [1]), .I1(\gic0.gc0.count_d2_reg[10] [2]), .O(bin2gray[1])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[2]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [2]), .I1(\gic0.gc0.count_d2_reg[10] [3]), .O(bin2gray[2])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[3]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [3]), .I1(\gic0.gc0.count_d2_reg[10] [4]), .O(bin2gray[3])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[4]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [4]), .I1(\gic0.gc0.count_d2_reg[10] [5]), .O(bin2gray[4])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[5]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [5]), .I1(\gic0.gc0.count_d2_reg[10] [6]), .O(bin2gray[5])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[6]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [6]), .I1(\gic0.gc0.count_d2_reg[10] [7]), .O(bin2gray[6])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[7]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [7]), .I1(\gic0.gc0.count_d2_reg[10] [8]), .O(bin2gray[7])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[8]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [8]), .I1(\gic0.gc0.count_d2_reg[10] [9]), .O(bin2gray[8])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[9]_i_1 (.I0(\gic0.gc0.count_d2_reg[10] [9]), .I1(\gic0.gc0.count_d2_reg[10] [10]), .O(bin2gray[9])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[0]), .Q(wr_pntr_gc[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[10] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gic0.gc0.count_d2_reg[10] [10]), .Q(wr_pntr_gc[10])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[1]), .Q(wr_pntr_gc[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[2]), .Q(wr_pntr_gc[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[3]), .Q(wr_pntr_gc[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[4]), .Q(wr_pntr_gc[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[5]), .Q(wr_pntr_gc[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[6]), .Q(wr_pntr_gc[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[7]), .Q(wr_pntr_gc[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[8]), .Q(wr_pntr_gc[8])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[9] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[9]), .Q(wr_pntr_gc[9])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_1 (.I0(WR_PNTR_RD[7]), .I1(Q[7]), .O(\gdiff.diff_pntr_pad_reg[8] [3])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_2 (.I0(WR_PNTR_RD[6]), .I1(Q[6]), .O(\gdiff.diff_pntr_pad_reg[8] [2])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_3 (.I0(WR_PNTR_RD[5]), .I1(Q[5]), .O(\gdiff.diff_pntr_pad_reg[8] [1])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_4 (.I0(WR_PNTR_RD[4]), .I1(Q[4]), .O(\gdiff.diff_pntr_pad_reg[8] [0])); LUT2 #( .INIT(4'h9)) plusOp_carry__1_i_1 (.I0(WR_PNTR_RD[8]), .I1(Q[8]), .O(\gdiff.diff_pntr_pad_reg[9] )); LUT2 #( .INIT(4'h9)) plusOp_carry_i_2 (.I0(WR_PNTR_RD[3]), .I1(Q[3]), .O(S[3])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_3 (.I0(WR_PNTR_RD[2]), .I1(Q[2]), .O(S[2])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_4 (.I0(WR_PNTR_RD[1]), .I1(Q[1]), .O(S[1])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_5 (.I0(WR_PNTR_RD[0]), .I1(Q[0]), .O(S[0])); endmodule (* ORIG_REF_NAME = "compare" *) module fb_input_fifo_compare (ram_empty_fb_i_reg, v1_reg, \gc0.count_d1_reg[8] , rd_en, out, comp1); output ram_empty_fb_i_reg; input [3:0]v1_reg; input \gc0.count_d1_reg[8] ; input rd_en; input out; input comp1; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire comp0; wire comp1; wire \gc0.count_d1_reg[8] ; wire out; wire ram_empty_fb_i_reg; wire rd_en; wire [3:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] })); LUT4 #( .INIT(16'hAEAA)) ram_empty_i_i_1 (.I0(comp0), .I1(rd_en), .I2(out), .I3(comp1), .O(ram_empty_fb_i_reg)); endmodule (* ORIG_REF_NAME = "compare" *) module fb_input_fifo_compare_3 (comp1, v1_reg_0, \gc0.count_reg[8] ); output comp1; input [3:0]v1_reg_0; input \gc0.count_reg[8] ; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire comp1; wire \gc0.count_reg[8] ; wire [3:0]v1_reg_0; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg_0)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_reg[8] })); endmodule (* ORIG_REF_NAME = "compare" *) module fb_input_fifo_compare__parameterized0 (comp1, v1_reg, \gnxpm_cdc.rd_pntr_bin_reg[8] ); output comp1; input [4:0]v1_reg; input \gnxpm_cdc.rd_pntr_bin_reg[8] ; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire carrynet_4; wire comp1; wire \gnxpm_cdc.rd_pntr_bin_reg[8] ; wire [4:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg[3:0])); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gnxpm_cdc.rd_pntr_bin_reg[8] ,v1_reg[4]})); endmodule (* ORIG_REF_NAME = "compare" *) module fb_input_fifo_compare__parameterized1 (ram_full_fb_i_reg, v1_reg_0, \gnxpm_cdc.rd_pntr_bin_reg[8] , wr_rst_busy, out, wr_en, comp1); output ram_full_fb_i_reg; input [4:0]v1_reg_0; input \gnxpm_cdc.rd_pntr_bin_reg[8] ; input wr_rst_busy; input out; input wr_en; input comp1; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire carrynet_4; wire comp1; wire comp2; wire \gnxpm_cdc.rd_pntr_bin_reg[8] ; wire out; wire ram_full_fb_i_reg; wire [4:0]v1_reg_0; wire wr_en; wire wr_rst_busy; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg_0[3:0])); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp2,carrynet_4}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gnxpm_cdc.rd_pntr_bin_reg[8] ,v1_reg_0[4]})); LUT5 #( .INIT(32'h55550400)) ram_full_i_i_1 (.I0(wr_rst_busy), .I1(comp2), .I2(out), .I3(wr_en), .I4(comp1), .O(ram_full_fb_i_reg)); endmodule (* ORIG_REF_NAME = "fifo_generator_ramfifo" *) module fb_input_fifo_fifo_generator_ramfifo (wr_rst_busy, dout, empty, full, prog_empty, rd_en, wr_en, rd_clk, wr_clk, din, rst); output wr_rst_busy; output [255:0]dout; output empty; output full; output prog_empty; input rd_en; input wr_en; input rd_clk; input wr_clk; input [63:0]din; input rst; wire [63:0]din; wire [255:0]dout; wire empty; wire full; wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; wire \gntv_or_sync_fifo.gcx.clkx_n_1 ; wire \gntv_or_sync_fifo.gcx.clkx_n_13 ; wire \gntv_or_sync_fifo.gcx.clkx_n_14 ; wire \gntv_or_sync_fifo.gcx.clkx_n_15 ; wire \gntv_or_sync_fifo.gcx.clkx_n_16 ; wire \gntv_or_sync_fifo.gcx.clkx_n_17 ; wire \gntv_or_sync_fifo.gcx.clkx_n_18 ; wire \gntv_or_sync_fifo.gcx.clkx_n_2 ; wire \gntv_or_sync_fifo.gcx.clkx_n_27 ; wire \gntv_or_sync_fifo.gcx.clkx_n_3 ; wire \gntv_or_sync_fifo.gl0.wr_n_1 ; wire [3:0]\gras.rsts/c0/v1_reg ; wire [3:0]\gras.rsts/c1/v1_reg ; wire [8:0]p_0_out_0; wire [10:0]p_12_out; wire [10:10]p_13_out; wire [10:2]p_22_out; wire [7:0]p_23_out; wire p_2_out; wire prog_empty; wire rd_clk; wire rd_en; wire [7:0]rd_pntr_plus1; wire [2:0]rd_rst_i; wire rst; wire rst_full_ff_i; wire tmp_ram_rd_en; wire wr_clk; wire wr_en; wire [10:10]wr_pntr_plus2; wire wr_rst_busy; wire [1:0]wr_rst_i; fb_input_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx (.AR(wr_rst_i[0]), .D(wr_pntr_plus2), .Q(p_0_out_0), .RD_PNTR_WR(p_23_out), .S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 ,\gntv_or_sync_fifo.gcx.clkx_n_2 ,\gntv_or_sync_fifo.gcx.clkx_n_3 }), .WR_PNTR_RD(p_22_out), .\gc0.count_reg[7] (rd_pntr_plus1), .\gdiff.diff_pntr_pad_reg[8] ({\gntv_or_sync_fifo.gcx.clkx_n_13 ,\gntv_or_sync_fifo.gcx.clkx_n_14 ,\gntv_or_sync_fifo.gcx.clkx_n_15 ,\gntv_or_sync_fifo.gcx.clkx_n_16 }), .\gdiff.diff_pntr_pad_reg[9] (\gntv_or_sync_fifo.gcx.clkx_n_17 ), .\gic0.gc0.count_d1_reg[10] (p_13_out), .\gic0.gc0.count_d2_reg[10] (p_12_out), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]), .ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_18 ), .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_27 ), .rd_clk(rd_clk), .v1_reg(\gras.rsts/c0/v1_reg ), .v1_reg_0(\gras.rsts/c1/v1_reg ), .wr_clk(wr_clk)); fb_input_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd (.AR(rd_rst_i[2]), .Q(p_0_out_0), .S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 ,\gntv_or_sync_fifo.gcx.clkx_n_2 ,\gntv_or_sync_fifo.gcx.clkx_n_3 }), .WR_PNTR_RD(p_22_out), .empty(empty), .\gc0.count_d1_reg[7] (rd_pntr_plus1), .\gnxpm_cdc.wr_pntr_bin_reg[10] (\gntv_or_sync_fifo.gcx.clkx_n_17 ), .\gnxpm_cdc.wr_pntr_bin_reg[9] ({\gntv_or_sync_fifo.gcx.clkx_n_13 ,\gntv_or_sync_fifo.gcx.clkx_n_14 ,\gntv_or_sync_fifo.gcx.clkx_n_15 ,\gntv_or_sync_fifo.gcx.clkx_n_16 }), .out(p_2_out), .prog_empty(prog_empty), .rd_clk(rd_clk), .rd_en(rd_en), .v1_reg(\gras.rsts/c0/v1_reg ), .v1_reg_0(\gras.rsts/c1/v1_reg )); fb_input_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr (.AR(wr_rst_i[1]), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (p_12_out), .Q(p_13_out), .RD_PNTR_WR(p_23_out), .full(full), .\gic0.gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.wr_n_1 ), .\gic0.gc0.count_d1_reg[10]_0 (wr_pntr_plus2), .\gnxpm_cdc.rd_pntr_bin_reg[8] (\gntv_or_sync_fifo.gcx.clkx_n_18 ), .\gnxpm_cdc.rd_pntr_bin_reg[8]_0 (\gntv_or_sync_fifo.gcx.clkx_n_27 ), .out(rst_full_ff_i), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); fb_input_fifo_memory \gntv_or_sync_fifo.mem (.Q(p_0_out_0), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (p_12_out), .out(rd_rst_i[0]), .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_1 ), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fb_input_fifo_reset_blk_ramfifo rstblk (.\gc0.count_reg[1] (rd_rst_i), .\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i), .out(wr_rst_i), .ram_empty_fb_i_reg(p_2_out), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk), .wr_rst_busy(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "fifo_generator_top" *) module fb_input_fifo_fifo_generator_top (wr_rst_busy, dout, empty, full, prog_empty, rd_en, wr_en, rd_clk, wr_clk, din, rst); output wr_rst_busy; output [255:0]dout; output empty; output full; output prog_empty; input rd_en; input wr_en; input rd_clk; input wr_clk; input [63:0]din; input rst; wire [63:0]din; wire [255:0]dout; wire empty; wire full; wire prog_empty; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; wire wr_rst_busy; fb_input_fifo_fifo_generator_ramfifo \grf.rf (.din(din), .dout(dout), .empty(empty), .full(full), .prog_empty(prog_empty), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "11" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "256" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "2kx18" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "15" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "16" *) (* C_PROG_EMPTY_TYPE = "1" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "2045" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "2044" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *) (* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "9" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "11" *) (* C_WR_DEPTH = "2048" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "11" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_2" *) module fb_input_fifo_fifo_generator_v13_1_2 (backup, backup_marker, clk, rst, srst, wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, prog_empty_thresh, prog_empty_thresh_assert, prog_empty_thresh_negate, prog_full_thresh, prog_full_thresh_assert, prog_full_thresh_negate, int_clk, injectdbiterr, injectsbiterr, sleep, dout, full, almost_full, wr_ack, overflow, empty, almost_empty, valid, underflow, data_count, rd_data_count, wr_data_count, prog_full, prog_empty, sbiterr, dbiterr, wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, s_aresetn, m_aclk_en, s_aclk_en, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awregion, s_axi_awuser, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wuser, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_buser, s_axi_bvalid, s_axi_bready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awregion, m_axi_awuser, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wuser, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_buser, m_axi_bvalid, m_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arregion, s_axi_aruser, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_ruser, s_axi_rvalid, s_axi_rready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arregion, m_axi_aruser, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_ruser, m_axi_rvalid, m_axi_rready, s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tstrb, s_axis_tkeep, s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tstrb, m_axis_tkeep, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser, axi_aw_injectsbiterr, axi_aw_injectdbiterr, axi_aw_prog_full_thresh, axi_aw_prog_empty_thresh, axi_aw_data_count, axi_aw_wr_data_count, axi_aw_rd_data_count, axi_aw_sbiterr, axi_aw_dbiterr, axi_aw_overflow, axi_aw_underflow, axi_aw_prog_full, axi_aw_prog_empty, axi_w_injectsbiterr, axi_w_injectdbiterr, axi_w_prog_full_thresh, axi_w_prog_empty_thresh, axi_w_data_count, axi_w_wr_data_count, axi_w_rd_data_count, axi_w_sbiterr, axi_w_dbiterr, axi_w_overflow, axi_w_underflow, axi_w_prog_full, axi_w_prog_empty, axi_b_injectsbiterr, axi_b_injectdbiterr, axi_b_prog_full_thresh, axi_b_prog_empty_thresh, axi_b_data_count, axi_b_wr_data_count, axi_b_rd_data_count, axi_b_sbiterr, axi_b_dbiterr, axi_b_overflow, axi_b_underflow, axi_b_prog_full, axi_b_prog_empty, axi_ar_injectsbiterr, axi_ar_injectdbiterr, axi_ar_prog_full_thresh, axi_ar_prog_empty_thresh, axi_ar_data_count, axi_ar_wr_data_count, axi_ar_rd_data_count, axi_ar_sbiterr, axi_ar_dbiterr, axi_ar_overflow, axi_ar_underflow, axi_ar_prog_full, axi_ar_prog_empty, axi_r_injectsbiterr, axi_r_injectdbiterr, axi_r_prog_full_thresh, axi_r_prog_empty_thresh, axi_r_data_count, axi_r_wr_data_count, axi_r_rd_data_count, axi_r_sbiterr, axi_r_dbiterr, axi_r_overflow, axi_r_underflow, axi_r_prog_full, axi_r_prog_empty, axis_injectsbiterr, axis_injectdbiterr, axis_prog_full_thresh, axis_prog_empty_thresh, axis_data_count, axis_wr_data_count, axis_rd_data_count, axis_sbiterr, axis_dbiterr, axis_overflow, axis_underflow, axis_prog_full, axis_prog_empty); input backup; input backup_marker; input clk; input rst; input srst; input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [63:0]din; input wr_en; input rd_en; input [8:0]prog_empty_thresh; input [8:0]prog_empty_thresh_assert; input [8:0]prog_empty_thresh_negate; input [10:0]prog_full_thresh; input [10:0]prog_full_thresh_assert; input [10:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; input sleep; output [255:0]dout; output full; output almost_full; output wr_ack; output overflow; output empty; output almost_empty; output valid; output underflow; output [10:0]data_count; output [8:0]rd_data_count; output [10:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; output dbiterr; output wr_rst_busy; output rd_rst_busy; input m_aclk; input s_aclk; input s_aresetn; input m_aclk_en; input s_aclk_en; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input [3:0]s_axi_awregion; input [0:0]s_axi_awuser; input s_axi_awvalid; output s_axi_awready; input [0:0]s_axi_wid; input [63:0]s_axi_wdata; input [7:0]s_axi_wstrb; input s_axi_wlast; input [0:0]s_axi_wuser; input s_axi_wvalid; output s_axi_wready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output [0:0]s_axi_buser; output s_axi_bvalid; input s_axi_bready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awqos; output [3:0]m_axi_awregion; output [0:0]m_axi_awuser; output m_axi_awvalid; input m_axi_awready; output [0:0]m_axi_wid; output [63:0]m_axi_wdata; output [7:0]m_axi_wstrb; output m_axi_wlast; output [0:0]m_axi_wuser; output m_axi_wvalid; input m_axi_wready; input [0:0]m_axi_bid; input [1:0]m_axi_bresp; input [0:0]m_axi_buser; input m_axi_bvalid; output m_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input [3:0]s_axi_arregion; input [0:0]s_axi_aruser; input s_axi_arvalid; output s_axi_arready; output [0:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output [0:0]s_axi_ruser; output s_axi_rvalid; input s_axi_rready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; output [3:0]m_axi_arregion; output [0:0]m_axi_aruser; output m_axi_arvalid; input m_axi_arready; input [0:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; input [0:0]m_axi_ruser; input m_axi_rvalid; output m_axi_rready; input s_axis_tvalid; output s_axis_tready; input [7:0]s_axis_tdata; input [0:0]s_axis_tstrb; input [0:0]s_axis_tkeep; input s_axis_tlast; input [0:0]s_axis_tid; input [0:0]s_axis_tdest; input [3:0]s_axis_tuser; output m_axis_tvalid; input m_axis_tready; output [7:0]m_axis_tdata; output [0:0]m_axis_tstrb; output [0:0]m_axis_tkeep; output m_axis_tlast; output [0:0]m_axis_tid; output [0:0]m_axis_tdest; output [3:0]m_axis_tuser; input axi_aw_injectsbiterr; input axi_aw_injectdbiterr; input [3:0]axi_aw_prog_full_thresh; input [3:0]axi_aw_prog_empty_thresh; output [4:0]axi_aw_data_count; output [4:0]axi_aw_wr_data_count; output [4:0]axi_aw_rd_data_count; output axi_aw_sbiterr; output axi_aw_dbiterr; output axi_aw_overflow; output axi_aw_underflow; output axi_aw_prog_full; output axi_aw_prog_empty; input axi_w_injectsbiterr; input axi_w_injectdbiterr; input [9:0]axi_w_prog_full_thresh; input [9:0]axi_w_prog_empty_thresh; output [10:0]axi_w_data_count; output [10:0]axi_w_wr_data_count; output [10:0]axi_w_rd_data_count; output axi_w_sbiterr; output axi_w_dbiterr; output axi_w_overflow; output axi_w_underflow; output axi_w_prog_full; output axi_w_prog_empty; input axi_b_injectsbiterr; input axi_b_injectdbiterr; input [3:0]axi_b_prog_full_thresh; input [3:0]axi_b_prog_empty_thresh; output [4:0]axi_b_data_count; output [4:0]axi_b_wr_data_count; output [4:0]axi_b_rd_data_count; output axi_b_sbiterr; output axi_b_dbiterr; output axi_b_overflow; output axi_b_underflow; output axi_b_prog_full; output axi_b_prog_empty; input axi_ar_injectsbiterr; input axi_ar_injectdbiterr; input [3:0]axi_ar_prog_full_thresh; input [3:0]axi_ar_prog_empty_thresh; output [4:0]axi_ar_data_count; output [4:0]axi_ar_wr_data_count; output [4:0]axi_ar_rd_data_count; output axi_ar_sbiterr; output axi_ar_dbiterr; output axi_ar_overflow; output axi_ar_underflow; output axi_ar_prog_full; output axi_ar_prog_empty; input axi_r_injectsbiterr; input axi_r_injectdbiterr; input [9:0]axi_r_prog_full_thresh; input [9:0]axi_r_prog_empty_thresh; output [10:0]axi_r_data_count; output [10:0]axi_r_wr_data_count; output [10:0]axi_r_rd_data_count; output axi_r_sbiterr; output axi_r_dbiterr; output axi_r_overflow; output axi_r_underflow; output axi_r_prog_full; output axi_r_prog_empty; input axis_injectsbiterr; input axis_injectdbiterr; input [9:0]axis_prog_full_thresh; input [9:0]axis_prog_empty_thresh; output [10:0]axis_data_count; output [10:0]axis_wr_data_count; output [10:0]axis_rd_data_count; output axis_sbiterr; output axis_dbiterr; output axis_overflow; output axis_underflow; output axis_prog_full; output axis_prog_empty; wire \ ; wire \ ; wire [63:0]din; wire [255:0]dout; wire empty; wire full; wire prog_empty; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; wire wr_rst_busy; assign almost_empty = \ ; assign almost_full = \ ; assign axi_ar_data_count[4] = \ ; assign axi_ar_data_count[3] = \ ; assign axi_ar_data_count[2] = \ ; assign axi_ar_data_count[1] = \ ; assign axi_ar_data_count[0] = \ ; assign axi_ar_dbiterr = \ ; assign axi_ar_overflow = \ ; assign axi_ar_prog_empty = \ ; assign axi_ar_prog_full = \ ; assign axi_ar_rd_data_count[4] = \ ; assign axi_ar_rd_data_count[3] = \ ; assign axi_ar_rd_data_count[2] = \ ; assign axi_ar_rd_data_count[1] = \ ; assign axi_ar_rd_data_count[0] = \ ; assign axi_ar_sbiterr = \ ; assign axi_ar_underflow = \ ; assign axi_ar_wr_data_count[4] = \ ; assign axi_ar_wr_data_count[3] = \ ; assign axi_ar_wr_data_count[2] = \ ; assign axi_ar_wr_data_count[1] = \ ; assign axi_ar_wr_data_count[0] = \ ; assign axi_aw_data_count[4] = \ ; assign axi_aw_data_count[3] = \ ; assign axi_aw_data_count[2] = \ ; assign axi_aw_data_count[1] = \ ; assign axi_aw_data_count[0] = \ ; assign axi_aw_dbiterr = \ ; assign axi_aw_overflow = \ ; assign axi_aw_prog_empty = \ ; assign axi_aw_prog_full = \ ; assign axi_aw_rd_data_count[4] = \ ; assign axi_aw_rd_data_count[3] = \ ; assign axi_aw_rd_data_count[2] = \ ; assign axi_aw_rd_data_count[1] = \ ; assign axi_aw_rd_data_count[0] = \ ; assign axi_aw_sbiterr = \ ; assign axi_aw_underflow = \ ; assign axi_aw_wr_data_count[4] = \ ; assign axi_aw_wr_data_count[3] = \ ; assign axi_aw_wr_data_count[2] = \ ; assign axi_aw_wr_data_count[1] = \ ; assign axi_aw_wr_data_count[0] = \ ; assign axi_b_data_count[4] = \ ; assign axi_b_data_count[3] = \ ; assign axi_b_data_count[2] = \ ; assign axi_b_data_count[1] = \ ; assign axi_b_data_count[0] = \ ; assign axi_b_dbiterr = \ ; assign axi_b_overflow = \ ; assign axi_b_prog_empty = \ ; assign axi_b_prog_full = \ ; assign axi_b_rd_data_count[4] = \ ; assign axi_b_rd_data_count[3] = \ ; assign axi_b_rd_data_count[2] = \ ; assign axi_b_rd_data_count[1] = \ ; assign axi_b_rd_data_count[0] = \ ; assign axi_b_sbiterr = \ ; assign axi_b_underflow = \ ; assign axi_b_wr_data_count[4] = \ ; assign axi_b_wr_data_count[3] = \ ; assign axi_b_wr_data_count[2] = \ ; assign axi_b_wr_data_count[1] = \ ; assign axi_b_wr_data_count[0] = \ ; assign axi_r_data_count[10] = \ ; assign axi_r_data_count[9] = \ ; assign axi_r_data_count[8] = \ ; assign axi_r_data_count[7] = \ ; assign axi_r_data_count[6] = \ ; assign axi_r_data_count[5] = \ ; assign axi_r_data_count[4] = \ ; assign axi_r_data_count[3] = \ ; assign axi_r_data_count[2] = \ ; assign axi_r_data_count[1] = \ ; assign axi_r_data_count[0] = \ ; assign axi_r_dbiterr = \ ; assign axi_r_overflow = \ ; assign axi_r_prog_empty = \ ; assign axi_r_prog_full = \ ; assign axi_r_rd_data_count[10] = \ ; assign axi_r_rd_data_count[9] = \ ; assign axi_r_rd_data_count[8] = \ ; assign axi_r_rd_data_count[7] = \ ; assign axi_r_rd_data_count[6] = \ ; assign axi_r_rd_data_count[5] = \ ; assign axi_r_rd_data_count[4] = \ ; assign axi_r_rd_data_count[3] = \ ; assign axi_r_rd_data_count[2] = \ ; assign axi_r_rd_data_count[1] = \ ; assign axi_r_rd_data_count[0] = \ ; assign axi_r_sbiterr = \ ; assign axi_r_underflow = \ ; assign axi_r_wr_data_count[10] = \ ; assign axi_r_wr_data_count[9] = \ ; assign axi_r_wr_data_count[8] = \ ; assign axi_r_wr_data_count[7] = \ ; assign axi_r_wr_data_count[6] = \ ; assign axi_r_wr_data_count[5] = \ ; assign axi_r_wr_data_count[4] = \ ; assign axi_r_wr_data_count[3] = \ ; assign axi_r_wr_data_count[2] = \ ; assign axi_r_wr_data_count[1] = \ ; assign axi_r_wr_data_count[0] = \ ; assign axi_w_data_count[10] = \ ; assign axi_w_data_count[9] = \ ; assign axi_w_data_count[8] = \ ; assign axi_w_data_count[7] = \ ; assign axi_w_data_count[6] = \ ; assign axi_w_data_count[5] = \ ; assign axi_w_data_count[4] = \ ; assign axi_w_data_count[3] = \ ; assign axi_w_data_count[2] = \ ; assign axi_w_data_count[1] = \ ; assign axi_w_data_count[0] = \ ; assign axi_w_dbiterr = \ ; assign axi_w_overflow = \ ; assign axi_w_prog_empty = \ ; assign axi_w_prog_full = \ ; assign axi_w_rd_data_count[10] = \ ; assign axi_w_rd_data_count[9] = \ ; assign axi_w_rd_data_count[8] = \ ; assign axi_w_rd_data_count[7] = \ ; assign axi_w_rd_data_count[6] = \ ; assign axi_w_rd_data_count[5] = \ ; assign axi_w_rd_data_count[4] = \ ; assign axi_w_rd_data_count[3] = \ ; assign axi_w_rd_data_count[2] = \ ; assign axi_w_rd_data_count[1] = \ ; assign axi_w_rd_data_count[0] = \ ; assign axi_w_sbiterr = \ ; assign axi_w_underflow = \ ; assign axi_w_wr_data_count[10] = \ ; assign axi_w_wr_data_count[9] = \ ; assign axi_w_wr_data_count[8] = \ ; assign axi_w_wr_data_count[7] = \ ; assign axi_w_wr_data_count[6] = \ ; assign axi_w_wr_data_count[5] = \ ; assign axi_w_wr_data_count[4] = \ ; assign axi_w_wr_data_count[3] = \ ; assign axi_w_wr_data_count[2] = \ ; assign axi_w_wr_data_count[1] = \ ; assign axi_w_wr_data_count[0] = \ ; assign axis_data_count[10] = \ ; assign axis_data_count[9] = \ ; assign axis_data_count[8] = \ ; assign axis_data_count[7] = \ ; assign axis_data_count[6] = \ ; assign axis_data_count[5] = \ ; assign axis_data_count[4] = \ ; assign axis_data_count[3] = \ ; assign axis_data_count[2] = \ ; assign axis_data_count[1] = \ ; assign axis_data_count[0] = \ ; assign axis_dbiterr = \ ; assign axis_overflow = \ ; assign axis_prog_empty = \ ; assign axis_prog_full = \ ; assign axis_rd_data_count[10] = \ ; assign axis_rd_data_count[9] = \ ; assign axis_rd_data_count[8] = \ ; assign axis_rd_data_count[7] = \ ; assign axis_rd_data_count[6] = \ ; assign axis_rd_data_count[5] = \ ; assign axis_rd_data_count[4] = \ ; assign axis_rd_data_count[3] = \ ; assign axis_rd_data_count[2] = \ ; assign axis_rd_data_count[1] = \ ; assign axis_rd_data_count[0] = \ ; assign axis_sbiterr = \ ; assign axis_underflow = \ ; assign axis_wr_data_count[10] = \ ; assign axis_wr_data_count[9] = \ ; assign axis_wr_data_count[8] = \ ; assign axis_wr_data_count[7] = \ ; assign axis_wr_data_count[6] = \ ; assign axis_wr_data_count[5] = \ ; assign axis_wr_data_count[4] = \ ; assign axis_wr_data_count[3] = \ ; assign axis_wr_data_count[2] = \ ; assign axis_wr_data_count[1] = \ ; assign axis_wr_data_count[0] = \ ; assign data_count[10] = \ ; assign data_count[9] = \ ; assign data_count[8] = \ ; assign data_count[7] = \ ; assign data_count[6] = \ ; assign data_count[5] = \ ; assign data_count[4] = \ ; assign data_count[3] = \ ; assign data_count[2] = \ ; assign data_count[1] = \ ; assign data_count[0] = \ ; assign dbiterr = \ ; assign m_axi_araddr[31] = \ ; assign m_axi_araddr[30] = \ ; assign m_axi_araddr[29] = \ ; assign m_axi_araddr[28] = \ ; assign m_axi_araddr[27] = \ ; assign m_axi_araddr[26] = \ ; assign m_axi_araddr[25] = \ ; assign m_axi_araddr[24] = \ ; assign m_axi_araddr[23] = \ ; assign m_axi_araddr[22] = \ ; assign m_axi_araddr[21] = \ ; assign m_axi_araddr[20] = \ ; assign m_axi_araddr[19] = \ ; assign m_axi_araddr[18] = \ ; assign m_axi_araddr[17] = \ ; assign m_axi_araddr[16] = \ ; assign m_axi_araddr[15] = \ ; assign m_axi_araddr[14] = \ ; assign m_axi_araddr[13] = \ ; assign m_axi_araddr[12] = \ ; assign m_axi_araddr[11] = \ ; assign m_axi_araddr[10] = \ ; assign m_axi_araddr[9] = \ ; assign m_axi_araddr[8] = \ ; assign m_axi_araddr[7] = \ ; assign m_axi_araddr[6] = \ ; assign m_axi_araddr[5] = \ ; assign m_axi_araddr[4] = \ ; assign m_axi_araddr[3] = \ ; assign m_axi_araddr[2] = \ ; assign m_axi_araddr[1] = \ ; assign m_axi_araddr[0] = \ ; assign m_axi_arburst[1] = \ ; assign m_axi_arburst[0] = \ ; assign m_axi_arcache[3] = \ ; assign m_axi_arcache[2] = \ ; assign m_axi_arcache[1] = \ ; assign m_axi_arcache[0] = \ ; assign m_axi_arid[0] = \ ; assign m_axi_arlen[7] = \ ; assign m_axi_arlen[6] = \ ; assign m_axi_arlen[5] = \ ; assign m_axi_arlen[4] = \ ; assign m_axi_arlen[3] = \ ; assign m_axi_arlen[2] = \ ; assign m_axi_arlen[1] = \ ; assign m_axi_arlen[0] = \ ; assign m_axi_arlock[0] = \ ; assign m_axi_arprot[2] = \ ; assign m_axi_arprot[1] = \ ; assign m_axi_arprot[0] = \ ; assign m_axi_arqos[3] = \ ; assign m_axi_arqos[2] = \ ; assign m_axi_arqos[1] = \ ; assign m_axi_arqos[0] = \ ; assign m_axi_arregion[3] = \ ; assign m_axi_arregion[2] = \ ; assign m_axi_arregion[1] = \ ; assign m_axi_arregion[0] = \ ; assign m_axi_arsize[2] = \ ; assign m_axi_arsize[1] = \ ; assign m_axi_arsize[0] = \ ; assign m_axi_aruser[0] = \ ; assign m_axi_arvalid = \ ; assign m_axi_awaddr[31] = \ ; assign m_axi_awaddr[30] = \ ; assign m_axi_awaddr[29] = \ ; assign m_axi_awaddr[28] = \ ; assign m_axi_awaddr[27] = \ ; assign m_axi_awaddr[26] = \ ; assign m_axi_awaddr[25] = \ ; assign m_axi_awaddr[24] = \ ; assign m_axi_awaddr[23] = \ ; assign m_axi_awaddr[22] = \ ; assign m_axi_awaddr[21] = \ ; assign m_axi_awaddr[20] = \ ; assign m_axi_awaddr[19] = \ ; assign m_axi_awaddr[18] = \ ; assign m_axi_awaddr[17] = \ ; assign m_axi_awaddr[16] = \ ; assign m_axi_awaddr[15] = \ ; assign m_axi_awaddr[14] = \ ; assign m_axi_awaddr[13] = \ ; assign m_axi_awaddr[12] = \ ; assign m_axi_awaddr[11] = \ ; assign m_axi_awaddr[10] = \ ; assign m_axi_awaddr[9] = \ ; assign m_axi_awaddr[8] = \ ; assign m_axi_awaddr[7] = \ ; assign m_axi_awaddr[6] = \ ; assign m_axi_awaddr[5] = \ ; assign m_axi_awaddr[4] = \ ; assign m_axi_awaddr[3] = \ ; assign m_axi_awaddr[2] = \ ; assign m_axi_awaddr[1] = \ ; assign m_axi_awaddr[0] = \ ; assign m_axi_awburst[1] = \ ; assign m_axi_awburst[0] = \ ; assign m_axi_awcache[3] = \ ; assign m_axi_awcache[2] = \ ; assign m_axi_awcache[1] = \ ; assign m_axi_awcache[0] = \ ; assign m_axi_awid[0] = \ ; assign m_axi_awlen[7] = \ ; assign m_axi_awlen[6] = \ ; assign m_axi_awlen[5] = \ ; assign m_axi_awlen[4] = \ ; assign m_axi_awlen[3] = \ ; assign m_axi_awlen[2] = \ ; assign m_axi_awlen[1] = \ ; assign m_axi_awlen[0] = \ ; assign m_axi_awlock[0] = \ ; assign m_axi_awprot[2] = \ ; assign m_axi_awprot[1] = \ ; assign m_axi_awprot[0] = \ ; assign m_axi_awqos[3] = \ ; assign m_axi_awqos[2] = \ ; assign m_axi_awqos[1] = \ ; assign m_axi_awqos[0] = \ ; assign m_axi_awregion[3] = \ ; assign m_axi_awregion[2] = \ ; assign m_axi_awregion[1] = \ ; assign m_axi_awregion[0] = \ ; assign m_axi_awsize[2] = \ ; assign m_axi_awsize[1] = \ ; assign m_axi_awsize[0] = \ ; assign m_axi_awuser[0] = \ ; assign m_axi_awvalid = \ ; assign m_axi_bready = \ ; assign m_axi_rready = \ ; assign m_axi_wdata[63] = \ ; assign m_axi_wdata[62] = \ ; assign m_axi_wdata[61] = \ ; assign m_axi_wdata[60] = \ ; assign m_axi_wdata[59] = \ ; assign m_axi_wdata[58] = \ ; assign m_axi_wdata[57] = \ ; assign m_axi_wdata[56] = \ ; assign m_axi_wdata[55] = \ ; assign m_axi_wdata[54] = \ ; assign m_axi_wdata[53] = \ ; assign m_axi_wdata[52] = \ ; assign m_axi_wdata[51] = \ ; assign m_axi_wdata[50] = \ ; assign m_axi_wdata[49] = \ ; assign m_axi_wdata[48] = \ ; assign m_axi_wdata[47] = \ ; assign m_axi_wdata[46] = \ ; assign m_axi_wdata[45] = \ ; assign m_axi_wdata[44] = \ ; assign m_axi_wdata[43] = \ ; assign m_axi_wdata[42] = \ ; assign m_axi_wdata[41] = \ ; assign m_axi_wdata[40] = \ ; assign m_axi_wdata[39] = \ ; assign m_axi_wdata[38] = \ ; assign m_axi_wdata[37] = \ ; assign m_axi_wdata[36] = \ ; assign m_axi_wdata[35] = \ ; assign m_axi_wdata[34] = \ ; assign m_axi_wdata[33] = \ ; assign m_axi_wdata[32] = \ ; assign m_axi_wdata[31] = \ ; assign m_axi_wdata[30] = \ ; assign m_axi_wdata[29] = \ ; assign m_axi_wdata[28] = \ ; assign m_axi_wdata[27] = \ ; assign m_axi_wdata[26] = \ ; assign m_axi_wdata[25] = \ ; assign m_axi_wdata[24] = \ ; assign m_axi_wdata[23] = \ ; assign m_axi_wdata[22] = \ ; assign m_axi_wdata[21] = \ ; assign m_axi_wdata[20] = \ ; assign m_axi_wdata[19] = \ ; assign m_axi_wdata[18] = \ ; assign m_axi_wdata[17] = \ ; assign m_axi_wdata[16] = \ ; assign m_axi_wdata[15] = \ ; assign m_axi_wdata[14] = \ ; assign m_axi_wdata[13] = \ ; assign m_axi_wdata[12] = \ ; assign m_axi_wdata[11] = \ ; assign m_axi_wdata[10] = \ ; assign m_axi_wdata[9] = \ ; assign m_axi_wdata[8] = \ ; assign m_axi_wdata[7] = \ ; assign m_axi_wdata[6] = \ ; assign m_axi_wdata[5] = \ ; assign m_axi_wdata[4] = \ ; assign m_axi_wdata[3] = \ ; assign m_axi_wdata[2] = \ ; assign m_axi_wdata[1] = \ ; assign m_axi_wdata[0] = \ ; assign m_axi_wid[0] = \ ; assign m_axi_wlast = \ ; assign m_axi_wstrb[7] = \ ; assign m_axi_wstrb[6] = \ ; assign m_axi_wstrb[5] = \ ; assign m_axi_wstrb[4] = \ ; assign m_axi_wstrb[3] = \ ; assign m_axi_wstrb[2] = \ ; assign m_axi_wstrb[1] = \ ; assign m_axi_wstrb[0] = \ ; assign m_axi_wuser[0] = \ ; assign m_axi_wvalid = \ ; assign m_axis_tdata[7] = \ ; assign m_axis_tdata[6] = \ ; assign m_axis_tdata[5] = \ ; assign m_axis_tdata[4] = \ ; assign m_axis_tdata[3] = \ ; assign m_axis_tdata[2] = \ ; assign m_axis_tdata[1] = \ ; assign m_axis_tdata[0] = \ ; assign m_axis_tdest[0] = \ ; assign m_axis_tid[0] = \ ; assign m_axis_tkeep[0] = \ ; assign m_axis_tlast = \ ; assign m_axis_tstrb[0] = \ ; assign m_axis_tuser[3] = \ ; assign m_axis_tuser[2] = \ ; assign m_axis_tuser[1] = \ ; assign m_axis_tuser[0] = \ ; assign m_axis_tvalid = \ ; assign overflow = \ ; assign prog_full = \ ; assign rd_data_count[8] = \ ; assign rd_data_count[7] = \ ; assign rd_data_count[6] = \ ; assign rd_data_count[5] = \ ; assign rd_data_count[4] = \ ; assign rd_data_count[3] = \ ; assign rd_data_count[2] = \ ; assign rd_data_count[1] = \ ; assign rd_data_count[0] = \ ; assign rd_rst_busy = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_buser[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_ruser[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_wready = \ ; assign s_axis_tready = \ ; assign sbiterr = \ ; assign underflow = \ ; assign valid = \ ; assign wr_ack = \ ; assign wr_data_count[10] = \ ; assign wr_data_count[9] = \ ; assign wr_data_count[8] = \ ; assign wr_data_count[7] = \ ; assign wr_data_count[6] = \ ; assign wr_data_count[5] = \ ; assign wr_data_count[4] = \ ; assign wr_data_count[3] = \ ; assign wr_data_count[2] = \ ; assign wr_data_count[1] = \ ; assign wr_data_count[0] = \ ; GND GND (.G(\ )); VCC VCC (.P(\ )); fb_input_fifo_fifo_generator_v13_1_2_synth inst_fifo_gen (.din(din), .dout(dout), .empty(empty), .full(full), .prog_empty(prog_empty), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_1_2_synth" *) module fb_input_fifo_fifo_generator_v13_1_2_synth (wr_rst_busy, dout, empty, full, prog_empty, rd_en, wr_en, rd_clk, wr_clk, din, rst); output wr_rst_busy; output [255:0]dout; output empty; output full; output prog_empty; input rd_en; input wr_en; input rd_clk; input wr_clk; input [63:0]din; input rst; wire [63:0]din; wire [255:0]dout; wire empty; wire full; wire prog_empty; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; wire wr_rst_busy; fb_input_fifo_fifo_generator_top \gconvfifo.rf (.din(din), .dout(dout), .empty(empty), .full(full), .prog_empty(prog_empty), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "memory" *) module fb_input_fifo_memory (dout, rd_clk, wr_clk, tmp_ram_rd_en, ram_full_fb_i_reg, out, Q, \gic0.gc0.count_d2_reg[10] , din); output [255:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input ram_full_fb_i_reg; input [0:0]out; input [8:0]Q; input [10:0]\gic0.gc0.count_d2_reg[10] ; input [63:0]din; wire [8:0]Q; wire [63:0]din; wire [255:0]dout; wire [10:0]\gic0.gc0.count_d2_reg[10] ; wire [0:0]out; wire ram_full_fb_i_reg; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_input_fifo_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg (.Q(Q), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[10] (\gic0.gc0.count_d2_reg[10] ), .out(out), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module fb_input_fifo_rd_bin_cntr (ram_empty_fb_i_reg, Q, ram_empty_fb_i_reg_0, \gc0.count_d1_reg[7]_0 , WR_PNTR_RD, E, rd_clk, AR); output ram_empty_fb_i_reg; output [8:0]Q; output ram_empty_fb_i_reg_0; output [7:0]\gc0.count_d1_reg[7]_0 ; input [0:0]WR_PNTR_RD; input [0:0]E; input rd_clk; input [0:0]AR; wire [0:0]AR; wire [0:0]E; wire [8:0]Q; wire [0:0]WR_PNTR_RD; wire \gc0.count[8]_i_2_n_0 ; wire [7:0]\gc0.count_d1_reg[7]_0 ; wire [8:0]plusOp__0; wire ram_empty_fb_i_reg; wire ram_empty_fb_i_reg_0; wire rd_clk; wire [8:8]rd_pntr_plus1; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [0]), .O(plusOp__0[0])); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [0]), .I1(\gc0.count_d1_reg[7]_0 [1]), .O(plusOp__0[1])); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'h78)) \gc0.count[2]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [0]), .I1(\gc0.count_d1_reg[7]_0 [1]), .I2(\gc0.count_d1_reg[7]_0 [2]), .O(plusOp__0[2])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[3]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [1]), .I1(\gc0.count_d1_reg[7]_0 [0]), .I2(\gc0.count_d1_reg[7]_0 [2]), .I3(\gc0.count_d1_reg[7]_0 [3]), .O(plusOp__0[3])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT5 #( .INIT(32'h7FFF8000)) \gc0.count[4]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [2]), .I1(\gc0.count_d1_reg[7]_0 [0]), .I2(\gc0.count_d1_reg[7]_0 [1]), .I3(\gc0.count_d1_reg[7]_0 [3]), .I4(\gc0.count_d1_reg[7]_0 [4]), .O(plusOp__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gc0.count[5]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [3]), .I1(\gc0.count_d1_reg[7]_0 [1]), .I2(\gc0.count_d1_reg[7]_0 [0]), .I3(\gc0.count_d1_reg[7]_0 [2]), .I4(\gc0.count_d1_reg[7]_0 [4]), .I5(\gc0.count_d1_reg[7]_0 [5]), .O(plusOp__0[5])); LUT2 #( .INIT(4'h6)) \gc0.count[6]_i_1 (.I0(\gc0.count[8]_i_2_n_0 ), .I1(\gc0.count_d1_reg[7]_0 [6]), .O(plusOp__0[6])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'h78)) \gc0.count[7]_i_1 (.I0(\gc0.count[8]_i_2_n_0 ), .I1(\gc0.count_d1_reg[7]_0 [6]), .I2(\gc0.count_d1_reg[7]_0 [7]), .O(plusOp__0[7])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[8]_i_1 (.I0(\gc0.count_d1_reg[7]_0 [6]), .I1(\gc0.count[8]_i_2_n_0 ), .I2(\gc0.count_d1_reg[7]_0 [7]), .I3(rd_pntr_plus1), .O(plusOp__0[8])); LUT6 #( .INIT(64'h8000000000000000)) \gc0.count[8]_i_2 (.I0(\gc0.count_d1_reg[7]_0 [5]), .I1(\gc0.count_d1_reg[7]_0 [3]), .I2(\gc0.count_d1_reg[7]_0 [1]), .I3(\gc0.count_d1_reg[7]_0 [0]), .I4(\gc0.count_d1_reg[7]_0 [2]), .I5(\gc0.count_d1_reg[7]_0 [4]), .O(\gc0.count[8]_i_2_n_0 )); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [0]), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [1]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [2]), .Q(Q[2])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [3]), .Q(Q[3])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[4] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [4]), .Q(Q[4])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[5] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [5]), .Q(Q[5])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[6] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [6]), .Q(Q[6])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[7] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[7]_0 [7]), .Q(Q[7])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[8] (.C(rd_clk), .CE(E), .CLR(AR), .D(rd_pntr_plus1), .Q(Q[8])); FDPE #( .INIT(1'b1)) \gc0.count_reg[0] (.C(rd_clk), .CE(E), .D(plusOp__0[0]), .PRE(AR), .Q(\gc0.count_d1_reg[7]_0 [0])); FDCE #( .INIT(1'b0)) \gc0.count_reg[1] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[1]), .Q(\gc0.count_d1_reg[7]_0 [1])); FDCE #( .INIT(1'b0)) \gc0.count_reg[2] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[2]), .Q(\gc0.count_d1_reg[7]_0 [2])); FDCE #( .INIT(1'b0)) \gc0.count_reg[3] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[3]), .Q(\gc0.count_d1_reg[7]_0 [3])); FDCE #( .INIT(1'b0)) \gc0.count_reg[4] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[4]), .Q(\gc0.count_d1_reg[7]_0 [4])); FDCE #( .INIT(1'b0)) \gc0.count_reg[5] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[5]), .Q(\gc0.count_d1_reg[7]_0 [5])); FDCE #( .INIT(1'b0)) \gc0.count_reg[6] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[6]), .Q(\gc0.count_d1_reg[7]_0 [6])); FDCE #( .INIT(1'b0)) \gc0.count_reg[7] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[7]), .Q(\gc0.count_d1_reg[7]_0 [7])); FDCE #( .INIT(1'b0)) \gc0.count_reg[8] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[8]), .Q(rd_pntr_plus1)); LUT2 #( .INIT(4'h9)) \gmux.gm[4].gms.ms_i_1__1 (.I0(Q[8]), .I1(WR_PNTR_RD), .O(ram_empty_fb_i_reg)); LUT2 #( .INIT(4'h9)) \gmux.gm[4].gms.ms_i_1__2 (.I0(rd_pntr_plus1), .I1(WR_PNTR_RD), .O(ram_empty_fb_i_reg_0)); endmodule (* ORIG_REF_NAME = "rd_logic" *) module fb_input_fifo_rd_logic (empty, out, prog_empty, Q, \gc0.count_d1_reg[7] , v1_reg, v1_reg_0, rd_clk, AR, WR_PNTR_RD, S, \gnxpm_cdc.wr_pntr_bin_reg[9] , \gnxpm_cdc.wr_pntr_bin_reg[10] , rd_en); output empty; output out; output prog_empty; output [8:0]Q; output [7:0]\gc0.count_d1_reg[7] ; input [3:0]v1_reg; input [3:0]v1_reg_0; input rd_clk; input [0:0]AR; input [8:0]WR_PNTR_RD; input [3:0]S; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[10] ; input rd_en; wire [0:0]AR; wire [8:0]Q; wire [3:0]S; wire [8:0]WR_PNTR_RD; wire empty; wire [7:0]\gc0.count_d1_reg[7] ; wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[10] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; wire \gras.rsts_n_2 ; wire out; wire p_0_out; wire prog_empty; wire rd_clk; wire rd_en; wire rpntr_n_0; wire rpntr_n_10; wire [3:0]v1_reg; wire [3:0]v1_reg_0; fb_input_fifo_rd_pe_as \gras.gpe.rdpe (.AR(AR), .S(S), .WR_PNTR_RD(WR_PNTR_RD[7:0]), .\gnxpm_cdc.wr_pntr_bin_reg[10] (\gnxpm_cdc.wr_pntr_bin_reg[10] ), .\gnxpm_cdc.wr_pntr_bin_reg[9] (\gnxpm_cdc.wr_pntr_bin_reg[9] ), .out(out), .p_0_out(p_0_out), .prog_empty(prog_empty), .rd_clk(rd_clk)); fb_input_fifo_rd_status_flags_as \gras.rsts (.AR(AR), .E(\gras.rsts_n_2 ), .empty(empty), .\gc0.count_d1_reg[8] (rpntr_n_0), .\gc0.count_reg[8] (rpntr_n_10), .out(out), .p_0_out(p_0_out), .rd_clk(rd_clk), .rd_en(rd_en), .v1_reg(v1_reg), .v1_reg_0(v1_reg_0)); fb_input_fifo_rd_bin_cntr rpntr (.AR(AR), .E(\gras.rsts_n_2 ), .Q(Q), .WR_PNTR_RD(WR_PNTR_RD[8]), .\gc0.count_d1_reg[7]_0 (\gc0.count_d1_reg[7] ), .ram_empty_fb_i_reg(rpntr_n_0), .ram_empty_fb_i_reg_0(rpntr_n_10), .rd_clk(rd_clk)); endmodule (* ORIG_REF_NAME = "rd_pe_as" *) module fb_input_fifo_rd_pe_as (prog_empty, p_0_out, WR_PNTR_RD, S, \gnxpm_cdc.wr_pntr_bin_reg[9] , \gnxpm_cdc.wr_pntr_bin_reg[10] , rd_clk, AR, out); output prog_empty; input p_0_out; input [7:0]WR_PNTR_RD; input [3:0]S; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[10] ; input rd_clk; input [0:0]AR; input out; wire [0:0]AR; wire [3:0]S; wire [7:0]WR_PNTR_RD; wire [9:5]diff_pntr_pad; wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[10] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; wire \gpe1.prog_empty_i_i_1_n_0 ; wire leqOp__0; wire out; wire p_0_out; wire [9:5]plusOp; wire plusOp_carry__0_n_0; wire plusOp_carry__0_n_1; wire plusOp_carry__0_n_2; wire plusOp_carry__0_n_3; wire plusOp_carry_n_0; wire plusOp_carry_n_1; wire plusOp_carry_n_2; wire plusOp_carry_n_3; wire prog_empty; wire rd_clk; wire [3:0]NLW_plusOp_carry_O_UNCONNECTED; wire [3:0]NLW_plusOp_carry__1_CO_UNCONNECTED; wire [3:1]NLW_plusOp_carry__1_O_UNCONNECTED; FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(AR), .D(plusOp[5]), .Q(diff_pntr_pad[5])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(AR), .D(plusOp[6]), .Q(diff_pntr_pad[6])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(AR), .D(plusOp[7]), .Q(diff_pntr_pad[7])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(AR), .D(plusOp[8]), .Q(diff_pntr_pad[8])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[9] (.C(rd_clk), .CE(1'b1), .CLR(AR), .D(plusOp[9]), .Q(diff_pntr_pad[9])); LUT3 #( .INIT(8'hB8)) \gpe1.prog_empty_i_i_1 (.I0(prog_empty), .I1(out), .I2(leqOp__0), .O(\gpe1.prog_empty_i_i_1_n_0 )); FDPE #( .INIT(1'b1)) \gpe1.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gpe1.prog_empty_i_i_1_n_0 ), .PRE(AR), .Q(prog_empty)); LUT5 #( .INIT(32'h00000001)) leqOp (.I0(diff_pntr_pad[8]), .I1(diff_pntr_pad[9]), .I2(diff_pntr_pad[5]), .I3(diff_pntr_pad[6]), .I4(diff_pntr_pad[7]), .O(leqOp__0)); CARRY4 plusOp_carry (.CI(1'b0), .CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}), .CYINIT(p_0_out), .DI(WR_PNTR_RD[3:0]), .O(NLW_plusOp_carry_O_UNCONNECTED[3:0]), .S(S)); CARRY4 plusOp_carry__0 (.CI(plusOp_carry_n_0), .CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}), .CYINIT(1'b0), .DI(WR_PNTR_RD[7:4]), .O(plusOp[8:5]), .S(\gnxpm_cdc.wr_pntr_bin_reg[9] )); CARRY4 plusOp_carry__1 (.CI(plusOp_carry__0_n_0), .CO(NLW_plusOp_carry__1_CO_UNCONNECTED[3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_plusOp_carry__1_O_UNCONNECTED[3:1],plusOp[9]}), .S({1'b0,1'b0,1'b0,\gnxpm_cdc.wr_pntr_bin_reg[10] })); endmodule (* ORIG_REF_NAME = "rd_status_flags_as" *) module fb_input_fifo_rd_status_flags_as (empty, out, E, p_0_out, v1_reg, \gc0.count_d1_reg[8] , v1_reg_0, \gc0.count_reg[8] , rd_clk, AR, rd_en); output empty; output out; output [0:0]E; output p_0_out; input [3:0]v1_reg; input \gc0.count_d1_reg[8] ; input [3:0]v1_reg_0; input \gc0.count_reg[8] ; input rd_clk; input [0:0]AR; input rd_en; wire [0:0]AR; wire [0:0]E; wire c0_n_0; wire comp1; wire \gc0.count_d1_reg[8] ; wire \gc0.count_reg[8] ; wire p_0_out; (* DONT_TOUCH *) wire ram_empty_fb_i; (* DONT_TOUCH *) wire ram_empty_i; wire rd_clk; wire rd_en; wire [3:0]v1_reg; wire [3:0]v1_reg_0; assign empty = ram_empty_i; assign out = ram_empty_fb_i; fb_input_fifo_compare c0 (.comp1(comp1), .\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ), .out(ram_empty_fb_i), .ram_empty_fb_i_reg(c0_n_0), .rd_en(rd_en), .v1_reg(v1_reg)); fb_input_fifo_compare_3 c1 (.comp1(comp1), .\gc0.count_reg[8] (\gc0.count_reg[8] ), .v1_reg_0(v1_reg_0)); LUT2 #( .INIT(4'h2)) \gc0.count_d1[8]_i_1 (.I0(rd_en), .I1(ram_empty_fb_i), .O(E)); LUT2 #( .INIT(4'hB)) plusOp_carry_i_1 (.I0(ram_empty_fb_i), .I1(rd_en), .O(p_0_out)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_fb_i_reg (.C(rd_clk), .CE(1'b1), .D(c0_n_0), .PRE(AR), .Q(ram_empty_fb_i)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(c0_n_0), .PRE(AR), .Q(ram_empty_i)); endmodule (* ORIG_REF_NAME = "reset_blk_ramfifo" *) module fb_input_fifo_reset_blk_ramfifo (out, \gc0.count_reg[1] , \grstd1.grst_full.grst_f.rst_d3_reg_0 , wr_rst_busy, tmp_ram_rd_en, rd_clk, wr_clk, rst, ram_empty_fb_i_reg, rd_en); output [1:0]out; output [2:0]\gc0.count_reg[1] ; output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; output wr_rst_busy; output tmp_ram_rd_en; input rd_clk; input wr_clk; input rst; input ram_empty_fb_i_reg; input rd_en; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ; wire p_7_out; wire p_8_out; wire ram_empty_fb_i_reg; wire rd_clk; wire rd_en; wire rd_rst_asreg; (* DONT_TOUCH *) wire [2:0]rd_rst_reg; wire rst; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d2; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d3; (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; wire tmp_ram_rd_en; wire wr_clk; wire wr_rst_asreg; (* DONT_TOUCH *) wire [2:0]wr_rst_reg; assign \gc0.count_reg[1] [2:0] = rd_rst_reg; assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2; assign out[1:0] = wr_rst_reg[1:0]; assign wr_rst_busy = rst_d3; LUT3 #( .INIT(8'hBA)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_i_1 (.I0(rd_rst_reg[0]), .I1(ram_empty_fb_i_reg), .I2(rd_en), .O(tmp_ram_rd_en)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d1_reg (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(rst_wr_reg2), .Q(rst_d1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d2_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1), .PRE(rst_wr_reg2), .Q(rst_d2)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d3_reg (.C(wr_clk), .CE(1'b1), .D(rst_d2), .PRE(rst_wr_reg2), .Q(rst_d3)); fb_input_fifo_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst (.in0(rd_rst_asreg), .\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ), .out(p_7_out), .rd_clk(rd_clk)); fb_input_fifo_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst (.in0(wr_rst_asreg), .\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ), .out(p_8_out), .wr_clk(wr_clk)); fb_input_fifo_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .in0(rd_rst_asreg), .out(p_7_out), .rd_clk(rd_clk)); fb_input_fifo_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .in0(wr_rst_asreg), .out(p_8_out), .wr_clk(wr_clk)); FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (.C(rd_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ), .PRE(rst_rd_reg2), .Q(rd_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .Q(rd_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .Q(rd_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .Q(rd_rst_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(rst), .Q(rst_rd_reg1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg (.C(rd_clk), .CE(1'b1), .D(rst_rd_reg1), .PRE(rst), .Q(rst_rd_reg2)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(rst), .Q(rst_wr_reg1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg (.C(wr_clk), .CE(1'b1), .D(rst_wr_reg1), .PRE(rst), .Q(rst_wr_reg2)); FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (.C(wr_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ), .PRE(rst_wr_reg2), .Q(wr_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .Q(wr_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .Q(wr_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .Q(wr_rst_reg[2])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff (out, \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg , in0, rd_clk); output out; output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ; input [0:0]in0; input rd_clk; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ; wire rd_clk; assign out = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .D(in0), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1 (.I0(in0), .I1(Q_reg), .O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg )); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff_0 (out, \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg , in0, wr_clk); output out; output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ; input [0:0]in0; input wr_clk; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ; wire wr_clk; assign out = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .D(in0), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1 (.I0(in0), .I1(Q_reg), .O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg )); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff_1 (AS, out, rd_clk, in0); output [0:0]AS; input out; input rd_clk; input [0:0]in0; wire [0:0]AS; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire out; wire rd_clk; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .D(out), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 (.I0(in0), .I1(Q_reg), .O(AS)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff_2 (AS, out, wr_clk, in0); output [0:0]AS; input out; input wr_clk; input [0:0]in0; wire [0:0]AS; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire out; wire wr_clk; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .D(out), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 (.I0(in0), .I1(Q_reg), .O(AS)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff__parameterized0 (D, Q, rd_clk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); output [10:0]D; input [10:0]Q; input rd_clk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire [10:0]Q; (* async_reg = "true" *) (* msgon = "true" *) wire [10:0]Q_reg; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire rd_clk; assign D[10:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[10] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[10]), .Q(Q_reg[10])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[8]), .Q(Q_reg[8])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[9] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[9]), .Q(Q_reg[9])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff__parameterized1 (D, Q, wr_clk, AR); output [8:0]D; input [8:0]Q; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [8:0]Q; (* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg; wire wr_clk; assign D[8:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[8]), .Q(Q_reg[8])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff__parameterized2 (out, \gnxpm_cdc.wr_pntr_bin_reg[9] , D, rd_clk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); output [0:0]out; output [7:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; input [10:0]D; input rd_clk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire [10:0]D; (* async_reg = "true" *) (* msgon = "true" *) wire [10:0]Q_reg; wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ; wire \gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ; wire [7:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire rd_clk; assign out[0] = Q_reg[10]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[10] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[10]), .Q(Q_reg[10])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[8]), .Q(Q_reg[8])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[9] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[9]), .Q(Q_reg[9])); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[2]_i_1 (.I0(Q_reg[3]), .I1(Q_reg[2]), .I2(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ), .I3(Q_reg[5]), .I4(Q_reg[4]), .I5(Q_reg[10]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [0])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[3]_i_1 (.I0(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ), .I1(Q_reg[5]), .I2(Q_reg[4]), .I3(Q_reg[10]), .I4(Q_reg[3]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [1])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.wr_pntr_bin[3]_i_2 (.I0(Q_reg[9]), .I1(Q_reg[8]), .I2(Q_reg[7]), .I3(Q_reg[6]), .O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[4]_i_1 (.I0(Q_reg[10]), .I1(Q_reg[4]), .I2(Q_reg[5]), .I3(\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ), .I4(Q_reg[8]), .I5(Q_reg[9]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [2])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_bin[4]_i_2 (.I0(Q_reg[6]), .I1(Q_reg[7]), .O(\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[5]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[5]), .I2(Q_reg[6]), .I3(Q_reg[10]), .I4(Q_reg[8]), .I5(Q_reg[9]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [3])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[6]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[6]), .I2(Q_reg[7]), .I3(Q_reg[10]), .I4(Q_reg[9]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [4])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.wr_pntr_bin[7]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[7]), .I2(Q_reg[10]), .I3(Q_reg[9]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [5])); LUT3 #( .INIT(8'h96)) \gnxpm_cdc.wr_pntr_bin[8]_i_1 (.I0(Q_reg[9]), .I1(Q_reg[8]), .I2(Q_reg[10]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [6])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_bin[9]_i_1 (.I0(Q_reg[9]), .I1(Q_reg[10]), .O(\gnxpm_cdc.wr_pntr_bin_reg[9] [7])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_input_fifo_synchronizer_ff__parameterized3 (out, \gnxpm_cdc.rd_pntr_bin_reg[7] , D, wr_clk, AR); output [0:0]out; output [7:0]\gnxpm_cdc.rd_pntr_bin_reg[7] ; input [8:0]D; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [8:0]D; (* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg; wire \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ; wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ; wire [7:0]\gnxpm_cdc.rd_pntr_bin_reg[7] ; wire wr_clk; assign out[0] = Q_reg[8]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[8]), .Q(Q_reg[8])); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[0]_i_1 (.I0(Q_reg[1]), .I1(Q_reg[0]), .I2(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), .I3(Q_reg[3]), .I4(Q_reg[2]), .I5(Q_reg[8]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [0])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[1]_i_1 (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), .I1(Q_reg[3]), .I2(Q_reg[2]), .I3(Q_reg[8]), .I4(Q_reg[1]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [1])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.rd_pntr_bin[1]_i_2 (.I0(Q_reg[7]), .I1(Q_reg[6]), .I2(Q_reg[5]), .I3(Q_reg[4]), .O(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[2]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[2]), .I2(Q_reg[3]), .I3(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ), .I4(Q_reg[6]), .I5(Q_reg[7]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [2])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_bin[2]_i_2 (.I0(Q_reg[4]), .I1(Q_reg[5]), .O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[3]_i_1 (.I0(Q_reg[5]), .I1(Q_reg[3]), .I2(Q_reg[4]), .I3(Q_reg[8]), .I4(Q_reg[6]), .I5(Q_reg[7]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [3])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[4]_i_1 (.I0(Q_reg[6]), .I1(Q_reg[4]), .I2(Q_reg[5]), .I3(Q_reg[8]), .I4(Q_reg[7]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [4])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.rd_pntr_bin[5]_i_1 (.I0(Q_reg[6]), .I1(Q_reg[5]), .I2(Q_reg[8]), .I3(Q_reg[7]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [5])); LUT3 #( .INIT(8'h96)) \gnxpm_cdc.rd_pntr_bin[6]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[6]), .I2(Q_reg[8]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [6])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_bin[7]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[8]), .O(\gnxpm_cdc.rd_pntr_bin_reg[7] [7])); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module fb_input_fifo_wr_bin_cntr (\gic0.gc0.count_d1_reg[10]_0 , v1_reg, v1_reg_0, Q, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram , RD_PNTR_WR, E, wr_clk, AR); output [0:0]\gic0.gc0.count_d1_reg[10]_0 ; output [4:0]v1_reg; output [4:0]v1_reg_0; output [0:0]Q; output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ; input [7:0]RD_PNTR_WR; input [0:0]E; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ; wire [0:0]E; wire [0:0]Q; wire [7:0]RD_PNTR_WR; wire \gic0.gc0.count[10]_i_2_n_0 ; wire [0:0]\gic0.gc0.count_d1_reg[10]_0 ; wire [9:0]p_13_out; wire [10:0]plusOp__1; wire [4:0]v1_reg; wire [4:0]v1_reg_0; wire wr_clk; wire [9:0]wr_pntr_plus2; (* SOFT_HLUTNM = "soft_lutpair15" *) LUT1 #( .INIT(2'h1)) \gic0.gc0.count[0]_i_1 (.I0(wr_pntr_plus2[0]), .O(plusOp__1[0])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gic0.gc0.count[10]_i_1 (.I0(wr_pntr_plus2[8]), .I1(wr_pntr_plus2[6]), .I2(\gic0.gc0.count[10]_i_2_n_0 ), .I3(wr_pntr_plus2[7]), .I4(wr_pntr_plus2[9]), .I5(\gic0.gc0.count_d1_reg[10]_0 ), .O(plusOp__1[10])); LUT6 #( .INIT(64'h8000000000000000)) \gic0.gc0.count[10]_i_2 (.I0(wr_pntr_plus2[5]), .I1(wr_pntr_plus2[3]), .I2(wr_pntr_plus2[1]), .I3(wr_pntr_plus2[0]), .I4(wr_pntr_plus2[2]), .I5(wr_pntr_plus2[4]), .O(\gic0.gc0.count[10]_i_2_n_0 )); LUT2 #( .INIT(4'h6)) \gic0.gc0.count[1]_i_1 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .O(plusOp__1[1])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[2]_i_1 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .I2(wr_pntr_plus2[2]), .O(plusOp__1[2])); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[3]_i_1 (.I0(wr_pntr_plus2[1]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[2]), .I3(wr_pntr_plus2[3]), .O(plusOp__1[3])); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT5 #( .INIT(32'h7FFF8000)) \gic0.gc0.count[4]_i_1 (.I0(wr_pntr_plus2[2]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[1]), .I3(wr_pntr_plus2[3]), .I4(wr_pntr_plus2[4]), .O(plusOp__1[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gic0.gc0.count[5]_i_1 (.I0(wr_pntr_plus2[3]), .I1(wr_pntr_plus2[1]), .I2(wr_pntr_plus2[0]), .I3(wr_pntr_plus2[2]), .I4(wr_pntr_plus2[4]), .I5(wr_pntr_plus2[5]), .O(plusOp__1[5])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h6)) \gic0.gc0.count[6]_i_1 (.I0(\gic0.gc0.count[10]_i_2_n_0 ), .I1(wr_pntr_plus2[6]), .O(plusOp__1[6])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[7]_i_1 (.I0(\gic0.gc0.count[10]_i_2_n_0 ), .I1(wr_pntr_plus2[6]), .I2(wr_pntr_plus2[7]), .O(plusOp__1[7])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[8]_i_1 (.I0(wr_pntr_plus2[6]), .I1(\gic0.gc0.count[10]_i_2_n_0 ), .I2(wr_pntr_plus2[7]), .I3(wr_pntr_plus2[8]), .O(plusOp__1[8])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT5 #( .INIT(32'h7FFF8000)) \gic0.gc0.count[9]_i_1 (.I0(wr_pntr_plus2[7]), .I1(\gic0.gc0.count[10]_i_2_n_0 ), .I2(wr_pntr_plus2[6]), .I3(wr_pntr_plus2[8]), .I4(wr_pntr_plus2[9]), .O(plusOp__1[9])); FDPE #( .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), .CE(E), .D(wr_pntr_plus2[0]), .PRE(AR), .Q(p_13_out[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[10] (.C(wr_clk), .CE(E), .CLR(AR), .D(\gic0.gc0.count_d1_reg[10]_0 ), .Q(Q)); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[1]), .Q(p_13_out[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[2]), .Q(p_13_out[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[3]), .Q(p_13_out[3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[4]), .Q(p_13_out[4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[5] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[5]), .Q(p_13_out[5])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[6] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[6]), .Q(p_13_out[6])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[7] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[7]), .Q(p_13_out[7])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[8] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[8]), .Q(p_13_out[8])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[9] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[9]), .Q(p_13_out[9])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[0]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[10] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [10])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[1]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[2]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[3]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[4]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[5] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[5]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [5])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[6] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[6]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [6])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[7] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[7]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [7])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[8] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[8]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [8])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[9] (.C(wr_clk), .CE(E), .CLR(AR), .D(p_13_out[9]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [9])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[0]), .Q(wr_pntr_plus2[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[10] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[10]), .Q(\gic0.gc0.count_d1_reg[10]_0 )); FDPE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), .CE(E), .D(plusOp__1[1]), .PRE(AR), .Q(wr_pntr_plus2[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[2]), .Q(wr_pntr_plus2[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[3]), .Q(wr_pntr_plus2[3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[4]), .Q(wr_pntr_plus2[4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[5] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[5]), .Q(wr_pntr_plus2[5])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[6] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[6]), .Q(wr_pntr_plus2[6])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[7] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[7]), .Q(wr_pntr_plus2[7])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[8] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[8]), .Q(wr_pntr_plus2[8])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[9] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[9]), .Q(wr_pntr_plus2[9])); LUT2 #( .INIT(4'h1)) \gmux.gm[0].gm1.m1_i_1__1 (.I0(p_13_out[0]), .I1(p_13_out[1]), .O(v1_reg[0])); LUT2 #( .INIT(4'h1)) \gmux.gm[0].gm1.m1_i_1__2 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .O(v1_reg_0[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__1 (.I0(p_13_out[2]), .I1(RD_PNTR_WR[0]), .I2(p_13_out[3]), .I3(RD_PNTR_WR[1]), .O(v1_reg[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__2 (.I0(wr_pntr_plus2[2]), .I1(RD_PNTR_WR[0]), .I2(wr_pntr_plus2[3]), .I3(RD_PNTR_WR[1]), .O(v1_reg_0[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__1 (.I0(p_13_out[4]), .I1(RD_PNTR_WR[2]), .I2(p_13_out[5]), .I3(RD_PNTR_WR[3]), .O(v1_reg[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__2 (.I0(wr_pntr_plus2[4]), .I1(RD_PNTR_WR[2]), .I2(wr_pntr_plus2[5]), .I3(RD_PNTR_WR[3]), .O(v1_reg_0[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__1 (.I0(p_13_out[6]), .I1(RD_PNTR_WR[4]), .I2(p_13_out[7]), .I3(RD_PNTR_WR[5]), .O(v1_reg[3])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__2 (.I0(wr_pntr_plus2[6]), .I1(RD_PNTR_WR[4]), .I2(wr_pntr_plus2[7]), .I3(RD_PNTR_WR[5]), .O(v1_reg_0[3])); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1 (.I0(p_13_out[8]), .I1(RD_PNTR_WR[6]), .I2(p_13_out[9]), .I3(RD_PNTR_WR[7]), .O(v1_reg[4])); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1__0 (.I0(wr_pntr_plus2[8]), .I1(RD_PNTR_WR[6]), .I2(wr_pntr_plus2[9]), .I3(RD_PNTR_WR[7]), .O(v1_reg_0[4])); endmodule (* ORIG_REF_NAME = "wr_logic" *) module fb_input_fifo_wr_logic (full, \gic0.gc0.count_d1_reg[10] , Q, \gic0.gc0.count_d1_reg[10]_0 , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram , \gnxpm_cdc.rd_pntr_bin_reg[8] , \gnxpm_cdc.rd_pntr_bin_reg[8]_0 , wr_clk, out, wr_en, AR, RD_PNTR_WR, wr_rst_busy); output full; output \gic0.gc0.count_d1_reg[10] ; output [0:0]Q; output [0:0]\gic0.gc0.count_d1_reg[10]_0 ; output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ; input \gnxpm_cdc.rd_pntr_bin_reg[8] ; input \gnxpm_cdc.rd_pntr_bin_reg[8]_0 ; input wr_clk; input out; input wr_en; input [0:0]AR; input [7:0]RD_PNTR_WR; input wr_rst_busy; wire [0:0]AR; wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ; wire [0:0]Q; wire [7:0]RD_PNTR_WR; wire [4:0]\c1/v1_reg ; wire [4:0]\c2/v1_reg ; wire full; wire \gic0.gc0.count_d1_reg[10] ; wire [0:0]\gic0.gc0.count_d1_reg[10]_0 ; wire \gnxpm_cdc.rd_pntr_bin_reg[8] ; wire \gnxpm_cdc.rd_pntr_bin_reg[8]_0 ; wire out; wire wr_clk; wire wr_en; wire wr_rst_busy; fb_input_fifo_wr_status_flags_as \gwas.wsts (.E(\gic0.gc0.count_d1_reg[10] ), .full(full), .\gnxpm_cdc.rd_pntr_bin_reg[8] (\gnxpm_cdc.rd_pntr_bin_reg[8] ), .\gnxpm_cdc.rd_pntr_bin_reg[8]_0 (\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ), .out(out), .v1_reg(\c1/v1_reg ), .v1_reg_0(\c2/v1_reg ), .wr_clk(wr_clk), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); fb_input_fifo_wr_bin_cntr wpntr (.AR(AR), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ), .E(\gic0.gc0.count_d1_reg[10] ), .Q(Q), .RD_PNTR_WR(RD_PNTR_WR), .\gic0.gc0.count_d1_reg[10]_0 (\gic0.gc0.count_d1_reg[10]_0 ), .v1_reg(\c1/v1_reg ), .v1_reg_0(\c2/v1_reg ), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "wr_status_flags_as" *) module fb_input_fifo_wr_status_flags_as (full, E, v1_reg, \gnxpm_cdc.rd_pntr_bin_reg[8] , v1_reg_0, \gnxpm_cdc.rd_pntr_bin_reg[8]_0 , wr_clk, out, wr_en, wr_rst_busy); output full; output [0:0]E; input [4:0]v1_reg; input \gnxpm_cdc.rd_pntr_bin_reg[8] ; input [4:0]v1_reg_0; input \gnxpm_cdc.rd_pntr_bin_reg[8]_0 ; input wr_clk; input out; input wr_en; input wr_rst_busy; wire [0:0]E; wire c2_n_0; wire comp1; wire \gnxpm_cdc.rd_pntr_bin_reg[8] ; wire \gnxpm_cdc.rd_pntr_bin_reg[8]_0 ; wire out; (* DONT_TOUCH *) wire ram_full_fb_i; (* DONT_TOUCH *) wire ram_full_i; wire [4:0]v1_reg; wire [4:0]v1_reg_0; wire wr_clk; wire wr_en; wire wr_rst_busy; assign full = ram_full_i; LUT2 #( .INIT(4'h2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_i_2 (.I0(wr_en), .I1(ram_full_fb_i), .O(E)); fb_input_fifo_compare__parameterized0 c1 (.comp1(comp1), .\gnxpm_cdc.rd_pntr_bin_reg[8] (\gnxpm_cdc.rd_pntr_bin_reg[8] ), .v1_reg(v1_reg)); fb_input_fifo_compare__parameterized1 c2 (.comp1(comp1), .\gnxpm_cdc.rd_pntr_bin_reg[8] (\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ), .out(ram_full_fb_i), .ram_full_fb_i_reg(c2_n_0), .v1_reg_0(v1_reg_0), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_fb_i_reg (.C(wr_clk), .CE(1'b1), .D(c2_n_0), .PRE(out), .Q(ram_full_fb_i)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(c2_n_0), .PRE(out), .Q(ram_full_i)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module fb_output_fifo_blk_mem_gen_generic_cstr (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [31:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [127:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [127:0]din; wire [31:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r (.Q(Q), .WEBWE(WEBWE), .din({din[113:96],din[81:64],din[49:32],din[17:0]}), .dout(dout[17:0]), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fb_output_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.Q(Q), .WEBWE(WEBWE), .din({din[127:114],din[95:82],din[63:50],din[31:18]}), .dout(dout[31:18]), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fb_output_fifo_blk_mem_gen_prim_width (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [17:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [71:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [71:0]din; wire [17:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram (.Q(Q), .WEBWE(WEBWE), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fb_output_fifo_blk_mem_gen_prim_width__parameterized0 (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [13:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [55:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [55:0]din; wire [13:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.Q(Q), .WEBWE(WEBWE), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fb_output_fifo_blk_mem_gen_prim_wrapper (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [17:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [71:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [71:0]din; wire [17:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ; wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED ; wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(18), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ), .DIADI({din[52:45],din[43:36],din[70:63],din[61:54]}), .DIBDI({din[16:9],din[7:0],din[34:27],din[25:18]}), .DIPADIP({din[53],din[44],din[71],din[62]}), .DIPBDIP({din[17],din[8],din[35],din[26]}), .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}), .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED [31:0]), .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED [3:2],dout[17],dout[8]}), .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(tmp_ram_rd_en), .ENBWREN(WEBWE), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(out), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fb_output_fifo_blk_mem_gen_prim_wrapper__parameterized0 (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [13:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [55:0]din; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 ; wire [10:0]Q; wire [0:0]WEBWE; wire [55:0]din; wire [13:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ; wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED ; wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(18), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gic0.gc0.count_d2_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,din[41:35],1'b0,din[34:28],1'b0,din[55:49],1'b0,din[48:42]}), .DIBDI({1'b0,din[13:7],1'b0,din[6:0],1'b0,din[27:21],1'b0,din[20:14]}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ,dout[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ,dout[6:0]}), .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED [31:0]), .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 }), .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(tmp_ram_rd_en), .ENBWREN(WEBWE), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(out), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module fb_output_fifo_blk_mem_gen_top (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [31:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [127:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [127:0]din; wire [31:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_generic_cstr \valid.cstr (.Q(Q), .WEBWE(WEBWE), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *) module fb_output_fifo_blk_mem_gen_v8_3_4 (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [31:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [127:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [127:0]din; wire [31:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.Q(Q), .WEBWE(WEBWE), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *) module fb_output_fifo_blk_mem_gen_v8_3_4_synth (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [31:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [127:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [127:0]din; wire [31:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.Q(Q), .WEBWE(WEBWE), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "clk_x_pntrs" *) module fb_output_fifo_clk_x_pntrs (ram_full_fb_i_reg, RD_PNTR_WR, ram_full_fb_i_reg_0, v1_reg, WR_PNTR_RD, v1_reg_0, Q, D, \gc0.count_d1_reg[10] , \gc0.count_reg[9] , \gic0.gc0.count_d2_reg[8] , wr_clk, AR, rd_clk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); output ram_full_fb_i_reg; output [8:0]RD_PNTR_WR; output ram_full_fb_i_reg_0; output [3:0]v1_reg; output [0:0]WR_PNTR_RD; output [3:0]v1_reg_0; input [0:0]Q; input [0:0]D; input [10:0]\gc0.count_d1_reg[10] ; input [7:0]\gc0.count_reg[9] ; input [8:0]\gic0.gc0.count_d2_reg[8] ; input wr_clk; input [0:0]AR; input rd_clk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire [0:0]AR; wire [0:0]D; wire [0:0]Q; wire [8:0]RD_PNTR_WR; wire [0:0]WR_PNTR_RD; wire [7:0]bin2gray; wire [10:0]\gc0.count_d1_reg[10] ; wire [7:0]\gc0.count_reg[9] ; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ; wire \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ; wire [6:0]gray2bin; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire p_0_out; wire [7:0]p_22_out; wire [8:0]p_3_out; wire [10:0]p_4_out; wire [8:8]p_5_out; wire [10:10]p_6_out; wire ram_full_fb_i_reg; wire ram_full_fb_i_reg_0; wire rd_clk; wire [10:0]rd_pntr_gc; wire [3:0]v1_reg; wire [3:0]v1_reg_0; wire wr_clk; wire [8:0]wr_pntr_gc; LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1 (.I0(p_22_out[0]), .I1(\gc0.count_d1_reg[10] [2]), .I2(p_22_out[1]), .I3(\gc0.count_d1_reg[10] [3]), .O(v1_reg[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__0 (.I0(p_22_out[0]), .I1(\gc0.count_reg[9] [0]), .I2(p_22_out[1]), .I3(\gc0.count_reg[9] [1]), .O(v1_reg_0[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1 (.I0(p_22_out[2]), .I1(\gc0.count_d1_reg[10] [4]), .I2(p_22_out[3]), .I3(\gc0.count_d1_reg[10] [5]), .O(v1_reg[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__0 (.I0(p_22_out[2]), .I1(\gc0.count_reg[9] [2]), .I2(p_22_out[3]), .I3(\gc0.count_reg[9] [3]), .O(v1_reg_0[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1 (.I0(p_22_out[4]), .I1(\gc0.count_d1_reg[10] [6]), .I2(p_22_out[5]), .I3(\gc0.count_d1_reg[10] [7]), .O(v1_reg[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__0 (.I0(p_22_out[4]), .I1(\gc0.count_reg[9] [4]), .I2(p_22_out[5]), .I3(\gc0.count_reg[9] [5]), .O(v1_reg_0[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1 (.I0(p_22_out[6]), .I1(\gc0.count_d1_reg[10] [8]), .I2(p_22_out[7]), .I3(\gc0.count_d1_reg[10] [9]), .O(v1_reg[3])); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1__0 (.I0(p_22_out[6]), .I1(\gc0.count_reg[9] [6]), .I2(p_22_out[7]), .I3(\gc0.count_reg[9] [7]), .O(v1_reg_0[3])); LUT2 #( .INIT(4'h9)) \gmux.gm[4].gms.ms_i_1__1 (.I0(RD_PNTR_WR[8]), .I1(Q), .O(ram_full_fb_i_reg)); LUT2 #( .INIT(4'h9)) \gmux.gm[4].gms.ms_i_1__2 (.I0(RD_PNTR_WR[8]), .I1(D), .O(ram_full_fb_i_reg_0)); fb_output_fifo_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst (.D(p_3_out), .Q(wr_pntr_gc), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .rd_clk(rd_clk)); fb_output_fifo_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst (.AR(AR), .D(p_4_out), .Q(rd_pntr_gc), .wr_clk(wr_clk)); fb_output_fifo_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst (.D(p_3_out), .\gnxpm_cdc.wr_pntr_bin_reg[7] ({p_0_out,gray2bin}), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .out(p_5_out), .rd_clk(rd_clk)); fb_output_fifo_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst (.AR(AR), .D(p_4_out), .\gnxpm_cdc.rd_pntr_bin_reg[9] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 }), .out(p_6_out), .wr_clk(wr_clk)); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[10] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(p_6_out), .Q(RD_PNTR_WR[8])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), .Q(RD_PNTR_WR[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), .Q(RD_PNTR_WR[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), .Q(RD_PNTR_WR[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), .Q(RD_PNTR_WR[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), .Q(RD_PNTR_WR[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), .Q(RD_PNTR_WR[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), .Q(RD_PNTR_WR[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[9] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), .Q(RD_PNTR_WR[7])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[0]_i_1 (.I0(\gc0.count_d1_reg[10] [0]), .I1(\gc0.count_d1_reg[10] [1]), .O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[1]_i_1 (.I0(\gc0.count_d1_reg[10] [1]), .I1(\gc0.count_d1_reg[10] [2]), .O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[2]_i_1 (.I0(\gc0.count_d1_reg[10] [2]), .I1(\gc0.count_d1_reg[10] [3]), .O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[3]_i_1 (.I0(\gc0.count_d1_reg[10] [3]), .I1(\gc0.count_d1_reg[10] [4]), .O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[4]_i_1 (.I0(\gc0.count_d1_reg[10] [4]), .I1(\gc0.count_d1_reg[10] [5]), .O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[5]_i_1 (.I0(\gc0.count_d1_reg[10] [5]), .I1(\gc0.count_d1_reg[10] [6]), .O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[6]_i_1 (.I0(\gc0.count_d1_reg[10] [6]), .I1(\gc0.count_d1_reg[10] [7]), .O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[7]_i_1 (.I0(\gc0.count_d1_reg[10] [7]), .I1(\gc0.count_d1_reg[10] [8]), .O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[8]_i_1 (.I0(\gc0.count_d1_reg[10] [8]), .I1(\gc0.count_d1_reg[10] [9]), .O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_gc[9]_i_1 (.I0(\gc0.count_d1_reg[10] [9]), .I1(\gc0.count_d1_reg[10] [10]), .O(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 )); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ), .Q(rd_pntr_gc[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[10] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gc0.count_d1_reg[10] [10]), .Q(rd_pntr_gc[10])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ), .Q(rd_pntr_gc[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ), .Q(rd_pntr_gc[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ), .Q(rd_pntr_gc[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ), .Q(rd_pntr_gc[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ), .Q(rd_pntr_gc[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ), .Q(rd_pntr_gc[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ), .Q(rd_pntr_gc[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ), .Q(rd_pntr_gc[8])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[9] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ), .Q(rd_pntr_gc[9])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[0]), .Q(p_22_out[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[1]), .Q(p_22_out[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[2]), .Q(p_22_out[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[3]), .Q(p_22_out[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[4]), .Q(p_22_out[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[5]), .Q(p_22_out[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(gray2bin[6]), .Q(p_22_out[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(p_0_out), .Q(p_22_out[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(p_5_out), .Q(WR_PNTR_RD)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[0]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [0]), .I1(\gic0.gc0.count_d2_reg[8] [1]), .O(bin2gray[0])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[1]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [1]), .I1(\gic0.gc0.count_d2_reg[8] [2]), .O(bin2gray[1])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[2]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [2]), .I1(\gic0.gc0.count_d2_reg[8] [3]), .O(bin2gray[2])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[3]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [3]), .I1(\gic0.gc0.count_d2_reg[8] [4]), .O(bin2gray[3])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[4]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [4]), .I1(\gic0.gc0.count_d2_reg[8] [5]), .O(bin2gray[4])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[5]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [5]), .I1(\gic0.gc0.count_d2_reg[8] [6]), .O(bin2gray[5])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[6]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [6]), .I1(\gic0.gc0.count_d2_reg[8] [7]), .O(bin2gray[6])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_gc[7]_i_1 (.I0(\gic0.gc0.count_d2_reg[8] [7]), .I1(\gic0.gc0.count_d2_reg[8] [8]), .O(bin2gray[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[0]), .Q(wr_pntr_gc[0])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[1]), .Q(wr_pntr_gc[1])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[2]), .Q(wr_pntr_gc[2])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[3]), .Q(wr_pntr_gc[3])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[4]), .Q(wr_pntr_gc[4])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[5]), .Q(wr_pntr_gc[5])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[6]), .Q(wr_pntr_gc[6])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(bin2gray[7]), .Q(wr_pntr_gc[7])); FDCE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(\gic0.gc0.count_d2_reg[8] [8]), .Q(wr_pntr_gc[8])); endmodule (* ORIG_REF_NAME = "compare" *) module fb_output_fifo_compare (ram_empty_fb_i_reg, v1_reg, \gnxpm_cdc.wr_pntr_bin_reg[6] , \gc0.count_d1_reg[10] , rd_en, out, comp1); output ram_empty_fb_i_reg; input [0:0]v1_reg; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; input \gc0.count_d1_reg[10] ; input rd_en; input out; input comp1; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire carrynet_4; wire comp0; wire comp1; wire \gc0.count_d1_reg[10] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; wire out; wire ram_empty_fb_i_reg; wire rd_en; wire [0:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S({\gnxpm_cdc.wr_pntr_bin_reg[6] [2:0],v1_reg})); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,\gnxpm_cdc.wr_pntr_bin_reg[6] [3]})); LUT4 #( .INIT(16'hAEAA)) ram_empty_i_i_1 (.I0(comp0), .I1(rd_en), .I2(out), .I3(comp1), .O(ram_empty_fb_i_reg)); endmodule (* ORIG_REF_NAME = "compare" *) module fb_output_fifo_compare_3 (comp1, v1_reg_0, \gnxpm_cdc.wr_pntr_bin_reg[6] , \gc0.count_reg[10] ); output comp1; input [0:0]v1_reg_0; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; input \gc0.count_reg[10] ; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire carrynet_4; wire comp1; wire \gc0.count_reg[10] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; wire [0:0]v1_reg_0; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S({\gnxpm_cdc.wr_pntr_bin_reg[6] [2:0],v1_reg_0})); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_reg[10] ,\gnxpm_cdc.wr_pntr_bin_reg[6] [3]})); endmodule (* ORIG_REF_NAME = "compare" *) module fb_output_fifo_compare__parameterized0 (comp1, v1_reg, \gnxpm_cdc.rd_pntr_bin_reg[10] ); output comp1; input [3:0]v1_reg; input \gnxpm_cdc.rd_pntr_bin_reg[10] ; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire comp1; wire \gnxpm_cdc.rd_pntr_bin_reg[10] ; wire [3:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gnxpm_cdc.rd_pntr_bin_reg[10] })); endmodule (* ORIG_REF_NAME = "compare" *) module fb_output_fifo_compare__parameterized1 (ram_full_fb_i_reg, v1_reg_0, \gnxpm_cdc.rd_pntr_bin_reg[10] , \grstd1.grst_full.grst_f.rst_d3_reg , out, wr_en, comp1); output ram_full_fb_i_reg; input [3:0]v1_reg_0; input \gnxpm_cdc.rd_pntr_bin_reg[10] ; input \grstd1.grst_full.grst_f.rst_d3_reg ; input out; input wr_en; input comp1; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire comp1; wire comp2; wire \gnxpm_cdc.rd_pntr_bin_reg[10] ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire out; wire ram_full_fb_i_reg; wire [3:0]v1_reg_0; wire wr_en; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[0].gm1.m1_CARRY4 (.CI(1'b0), .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg_0)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}), .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gnxpm_cdc.rd_pntr_bin_reg[10] })); LUT5 #( .INIT(32'h55550400)) ram_full_i_i_1 (.I0(\grstd1.grst_full.grst_f.rst_d3_reg ), .I1(comp2), .I2(out), .I3(wr_en), .I4(comp1), .O(ram_full_fb_i_reg)); endmodule (* ORIG_REF_NAME = "fifo_generator_ramfifo" *) module fb_output_fifo_fifo_generator_ramfifo (WR_RST_BUSY, dout, empty, full, prog_full, rd_en, wr_en, rd_clk, wr_clk, din, rst); output WR_RST_BUSY; output [31:0]dout; output empty; output full; output prog_full; input rd_en; input wr_en; input rd_clk; input wr_clk; input [127:0]din; input rst; wire WR_RST_BUSY; wire [127:0]din; wire [31:0]dout; wire empty; wire full; wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; wire \gntv_or_sync_fifo.gcx.clkx_n_10 ; wire \gntv_or_sync_fifo.gl0.wr_n_3 ; wire [4:1]\gras.rsts/c0/v1_reg ; wire [4:1]\gras.rsts/c1/v1_reg ; wire [10:0]p_0_out; wire [8:0]p_12_out; wire [8:8]p_13_out; wire [8:8]p_22_out; wire [10:2]p_23_out; wire p_2_out; wire prog_full; wire rd_clk; wire rd_en; wire [9:2]rd_pntr_plus1; wire [2:0]rd_rst_i; wire rst; wire rst_full_ff_i; wire tmp_ram_rd_en; wire wr_clk; wire wr_en; wire [8:8]wr_pntr_plus2; wire [1:0]wr_rst_i; fb_output_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx (.AR(wr_rst_i[0]), .D(wr_pntr_plus2), .Q(p_13_out), .RD_PNTR_WR(p_23_out), .WR_PNTR_RD(p_22_out), .\gc0.count_d1_reg[10] (p_0_out), .\gc0.count_reg[9] (rd_pntr_plus1), .\gic0.gc0.count_d2_reg[8] (p_12_out), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]), .ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ), .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_10 ), .rd_clk(rd_clk), .v1_reg(\gras.rsts/c0/v1_reg ), .v1_reg_0(\gras.rsts/c1/v1_reg ), .wr_clk(wr_clk)); fb_output_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd (.AR(rd_rst_i[2]), .Q(p_0_out), .WR_PNTR_RD(p_22_out), .empty(empty), .\gc0.count_d1_reg[9] (rd_pntr_plus1), .\gnxpm_cdc.wr_pntr_bin_reg[6] (\gras.rsts/c0/v1_reg ), .\gnxpm_cdc.wr_pntr_bin_reg[6]_0 (\gras.rsts/c1/v1_reg ), .out(p_2_out), .rd_clk(rd_clk), .rd_en(rd_en)); fb_output_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr (.AR(wr_rst_i[1]), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_12_out), .Q(p_13_out), .RD_PNTR_WR(p_23_out), .WEBWE(\gntv_or_sync_fifo.gl0.wr_n_3 ), .full(full), .\gic0.gc0.count_d1_reg[8] (wr_pntr_plus2), .\gnxpm_cdc.rd_pntr_bin_reg[10] (\gntv_or_sync_fifo.gcx.clkx_n_0 ), .\gnxpm_cdc.rd_pntr_bin_reg[10]_0 (\gntv_or_sync_fifo.gcx.clkx_n_10 ), .\grstd1.grst_full.grst_f.rst_d3_reg (WR_RST_BUSY), .out(rst_full_ff_i), .prog_full(prog_full), .wr_clk(wr_clk), .wr_en(wr_en)); fb_output_fifo_memory \gntv_or_sync_fifo.mem (.Q(p_0_out), .WEBWE(\gntv_or_sync_fifo.gl0.wr_n_3 ), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (p_12_out), .out(rd_rst_i[0]), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fb_output_fifo_reset_blk_ramfifo rstblk (.WR_RST_BUSY(WR_RST_BUSY), .\gc0.count_reg[1] (rd_rst_i), .\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i), .out(wr_rst_i), .ram_empty_fb_i_reg(p_2_out), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "fifo_generator_top" *) module fb_output_fifo_fifo_generator_top (WR_RST_BUSY, dout, empty, full, prog_full, rd_en, wr_en, rd_clk, wr_clk, din, rst); output WR_RST_BUSY; output [31:0]dout; output empty; output full; output prog_full; input rd_en; input wr_en; input rd_clk; input wr_clk; input [127:0]din; input rst; wire WR_RST_BUSY; wire [127:0]din; wire [31:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; fb_output_fifo_fifo_generator_ramfifo \grf.rf (.WR_RST_BUSY(WR_RST_BUSY), .din(din), .dout(dout), .empty(empty), .full(full), .prog_full(prog_full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en)); endmodule (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "128" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x72" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "496" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "495" *) (* C_PROG_FULL_TYPE = "1" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "11" *) (* C_RD_DEPTH = "2048" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "11" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *) (* C_WR_DEPTH = "512" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_2" *) module fb_output_fifo_fifo_generator_v13_1_2 (backup, backup_marker, clk, rst, srst, wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, prog_empty_thresh, prog_empty_thresh_assert, prog_empty_thresh_negate, prog_full_thresh, prog_full_thresh_assert, prog_full_thresh_negate, int_clk, injectdbiterr, injectsbiterr, sleep, dout, full, almost_full, wr_ack, overflow, empty, almost_empty, valid, underflow, data_count, rd_data_count, wr_data_count, prog_full, prog_empty, sbiterr, dbiterr, wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, s_aresetn, m_aclk_en, s_aclk_en, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awregion, s_axi_awuser, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wuser, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_buser, s_axi_bvalid, s_axi_bready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awregion, m_axi_awuser, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wuser, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_buser, m_axi_bvalid, m_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arregion, s_axi_aruser, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_ruser, s_axi_rvalid, s_axi_rready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arregion, m_axi_aruser, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_ruser, m_axi_rvalid, m_axi_rready, s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tstrb, s_axis_tkeep, s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tstrb, m_axis_tkeep, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser, axi_aw_injectsbiterr, axi_aw_injectdbiterr, axi_aw_prog_full_thresh, axi_aw_prog_empty_thresh, axi_aw_data_count, axi_aw_wr_data_count, axi_aw_rd_data_count, axi_aw_sbiterr, axi_aw_dbiterr, axi_aw_overflow, axi_aw_underflow, axi_aw_prog_full, axi_aw_prog_empty, axi_w_injectsbiterr, axi_w_injectdbiterr, axi_w_prog_full_thresh, axi_w_prog_empty_thresh, axi_w_data_count, axi_w_wr_data_count, axi_w_rd_data_count, axi_w_sbiterr, axi_w_dbiterr, axi_w_overflow, axi_w_underflow, axi_w_prog_full, axi_w_prog_empty, axi_b_injectsbiterr, axi_b_injectdbiterr, axi_b_prog_full_thresh, axi_b_prog_empty_thresh, axi_b_data_count, axi_b_wr_data_count, axi_b_rd_data_count, axi_b_sbiterr, axi_b_dbiterr, axi_b_overflow, axi_b_underflow, axi_b_prog_full, axi_b_prog_empty, axi_ar_injectsbiterr, axi_ar_injectdbiterr, axi_ar_prog_full_thresh, axi_ar_prog_empty_thresh, axi_ar_data_count, axi_ar_wr_data_count, axi_ar_rd_data_count, axi_ar_sbiterr, axi_ar_dbiterr, axi_ar_overflow, axi_ar_underflow, axi_ar_prog_full, axi_ar_prog_empty, axi_r_injectsbiterr, axi_r_injectdbiterr, axi_r_prog_full_thresh, axi_r_prog_empty_thresh, axi_r_data_count, axi_r_wr_data_count, axi_r_rd_data_count, axi_r_sbiterr, axi_r_dbiterr, axi_r_overflow, axi_r_underflow, axi_r_prog_full, axi_r_prog_empty, axis_injectsbiterr, axis_injectdbiterr, axis_prog_full_thresh, axis_prog_empty_thresh, axis_data_count, axis_wr_data_count, axis_rd_data_count, axis_sbiterr, axis_dbiterr, axis_overflow, axis_underflow, axis_prog_full, axis_prog_empty); input backup; input backup_marker; input clk; input rst; input srst; input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [127:0]din; input wr_en; input rd_en; input [10:0]prog_empty_thresh; input [10:0]prog_empty_thresh_assert; input [10:0]prog_empty_thresh_negate; input [8:0]prog_full_thresh; input [8:0]prog_full_thresh_assert; input [8:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; input sleep; output [31:0]dout; output full; output almost_full; output wr_ack; output overflow; output empty; output almost_empty; output valid; output underflow; output [8:0]data_count; output [10:0]rd_data_count; output [8:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; output dbiterr; output wr_rst_busy; output rd_rst_busy; input m_aclk; input s_aclk; input s_aresetn; input m_aclk_en; input s_aclk_en; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input [3:0]s_axi_awregion; input [0:0]s_axi_awuser; input s_axi_awvalid; output s_axi_awready; input [0:0]s_axi_wid; input [63:0]s_axi_wdata; input [7:0]s_axi_wstrb; input s_axi_wlast; input [0:0]s_axi_wuser; input s_axi_wvalid; output s_axi_wready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output [0:0]s_axi_buser; output s_axi_bvalid; input s_axi_bready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awqos; output [3:0]m_axi_awregion; output [0:0]m_axi_awuser; output m_axi_awvalid; input m_axi_awready; output [0:0]m_axi_wid; output [63:0]m_axi_wdata; output [7:0]m_axi_wstrb; output m_axi_wlast; output [0:0]m_axi_wuser; output m_axi_wvalid; input m_axi_wready; input [0:0]m_axi_bid; input [1:0]m_axi_bresp; input [0:0]m_axi_buser; input m_axi_bvalid; output m_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input [3:0]s_axi_arregion; input [0:0]s_axi_aruser; input s_axi_arvalid; output s_axi_arready; output [0:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output [0:0]s_axi_ruser; output s_axi_rvalid; input s_axi_rready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; output [3:0]m_axi_arregion; output [0:0]m_axi_aruser; output m_axi_arvalid; input m_axi_arready; input [0:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; input [0:0]m_axi_ruser; input m_axi_rvalid; output m_axi_rready; input s_axis_tvalid; output s_axis_tready; input [7:0]s_axis_tdata; input [0:0]s_axis_tstrb; input [0:0]s_axis_tkeep; input s_axis_tlast; input [0:0]s_axis_tid; input [0:0]s_axis_tdest; input [3:0]s_axis_tuser; output m_axis_tvalid; input m_axis_tready; output [7:0]m_axis_tdata; output [0:0]m_axis_tstrb; output [0:0]m_axis_tkeep; output m_axis_tlast; output [0:0]m_axis_tid; output [0:0]m_axis_tdest; output [3:0]m_axis_tuser; input axi_aw_injectsbiterr; input axi_aw_injectdbiterr; input [3:0]axi_aw_prog_full_thresh; input [3:0]axi_aw_prog_empty_thresh; output [4:0]axi_aw_data_count; output [4:0]axi_aw_wr_data_count; output [4:0]axi_aw_rd_data_count; output axi_aw_sbiterr; output axi_aw_dbiterr; output axi_aw_overflow; output axi_aw_underflow; output axi_aw_prog_full; output axi_aw_prog_empty; input axi_w_injectsbiterr; input axi_w_injectdbiterr; input [9:0]axi_w_prog_full_thresh; input [9:0]axi_w_prog_empty_thresh; output [10:0]axi_w_data_count; output [10:0]axi_w_wr_data_count; output [10:0]axi_w_rd_data_count; output axi_w_sbiterr; output axi_w_dbiterr; output axi_w_overflow; output axi_w_underflow; output axi_w_prog_full; output axi_w_prog_empty; input axi_b_injectsbiterr; input axi_b_injectdbiterr; input [3:0]axi_b_prog_full_thresh; input [3:0]axi_b_prog_empty_thresh; output [4:0]axi_b_data_count; output [4:0]axi_b_wr_data_count; output [4:0]axi_b_rd_data_count; output axi_b_sbiterr; output axi_b_dbiterr; output axi_b_overflow; output axi_b_underflow; output axi_b_prog_full; output axi_b_prog_empty; input axi_ar_injectsbiterr; input axi_ar_injectdbiterr; input [3:0]axi_ar_prog_full_thresh; input [3:0]axi_ar_prog_empty_thresh; output [4:0]axi_ar_data_count; output [4:0]axi_ar_wr_data_count; output [4:0]axi_ar_rd_data_count; output axi_ar_sbiterr; output axi_ar_dbiterr; output axi_ar_overflow; output axi_ar_underflow; output axi_ar_prog_full; output axi_ar_prog_empty; input axi_r_injectsbiterr; input axi_r_injectdbiterr; input [9:0]axi_r_prog_full_thresh; input [9:0]axi_r_prog_empty_thresh; output [10:0]axi_r_data_count; output [10:0]axi_r_wr_data_count; output [10:0]axi_r_rd_data_count; output axi_r_sbiterr; output axi_r_dbiterr; output axi_r_overflow; output axi_r_underflow; output axi_r_prog_full; output axi_r_prog_empty; input axis_injectsbiterr; input axis_injectdbiterr; input [9:0]axis_prog_full_thresh; input [9:0]axis_prog_empty_thresh; output [10:0]axis_data_count; output [10:0]axis_wr_data_count; output [10:0]axis_rd_data_count; output axis_sbiterr; output axis_dbiterr; output axis_overflow; output axis_underflow; output axis_prog_full; output axis_prog_empty; wire \ ; wire \ ; wire [127:0]din; wire [31:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; wire wr_rst_busy; assign almost_empty = \ ; assign almost_full = \ ; assign axi_ar_data_count[4] = \ ; assign axi_ar_data_count[3] = \ ; assign axi_ar_data_count[2] = \ ; assign axi_ar_data_count[1] = \ ; assign axi_ar_data_count[0] = \ ; assign axi_ar_dbiterr = \ ; assign axi_ar_overflow = \ ; assign axi_ar_prog_empty = \ ; assign axi_ar_prog_full = \ ; assign axi_ar_rd_data_count[4] = \ ; assign axi_ar_rd_data_count[3] = \ ; assign axi_ar_rd_data_count[2] = \ ; assign axi_ar_rd_data_count[1] = \ ; assign axi_ar_rd_data_count[0] = \ ; assign axi_ar_sbiterr = \ ; assign axi_ar_underflow = \ ; assign axi_ar_wr_data_count[4] = \ ; assign axi_ar_wr_data_count[3] = \ ; assign axi_ar_wr_data_count[2] = \ ; assign axi_ar_wr_data_count[1] = \ ; assign axi_ar_wr_data_count[0] = \ ; assign axi_aw_data_count[4] = \ ; assign axi_aw_data_count[3] = \ ; assign axi_aw_data_count[2] = \ ; assign axi_aw_data_count[1] = \ ; assign axi_aw_data_count[0] = \ ; assign axi_aw_dbiterr = \ ; assign axi_aw_overflow = \ ; assign axi_aw_prog_empty = \ ; assign axi_aw_prog_full = \ ; assign axi_aw_rd_data_count[4] = \ ; assign axi_aw_rd_data_count[3] = \ ; assign axi_aw_rd_data_count[2] = \ ; assign axi_aw_rd_data_count[1] = \ ; assign axi_aw_rd_data_count[0] = \ ; assign axi_aw_sbiterr = \ ; assign axi_aw_underflow = \ ; assign axi_aw_wr_data_count[4] = \ ; assign axi_aw_wr_data_count[3] = \ ; assign axi_aw_wr_data_count[2] = \ ; assign axi_aw_wr_data_count[1] = \ ; assign axi_aw_wr_data_count[0] = \ ; assign axi_b_data_count[4] = \ ; assign axi_b_data_count[3] = \ ; assign axi_b_data_count[2] = \ ; assign axi_b_data_count[1] = \ ; assign axi_b_data_count[0] = \ ; assign axi_b_dbiterr = \ ; assign axi_b_overflow = \ ; assign axi_b_prog_empty = \ ; assign axi_b_prog_full = \ ; assign axi_b_rd_data_count[4] = \ ; assign axi_b_rd_data_count[3] = \ ; assign axi_b_rd_data_count[2] = \ ; assign axi_b_rd_data_count[1] = \ ; assign axi_b_rd_data_count[0] = \ ; assign axi_b_sbiterr = \ ; assign axi_b_underflow = \ ; assign axi_b_wr_data_count[4] = \ ; assign axi_b_wr_data_count[3] = \ ; assign axi_b_wr_data_count[2] = \ ; assign axi_b_wr_data_count[1] = \ ; assign axi_b_wr_data_count[0] = \ ; assign axi_r_data_count[10] = \ ; assign axi_r_data_count[9] = \ ; assign axi_r_data_count[8] = \ ; assign axi_r_data_count[7] = \ ; assign axi_r_data_count[6] = \ ; assign axi_r_data_count[5] = \ ; assign axi_r_data_count[4] = \ ; assign axi_r_data_count[3] = \ ; assign axi_r_data_count[2] = \ ; assign axi_r_data_count[1] = \ ; assign axi_r_data_count[0] = \ ; assign axi_r_dbiterr = \ ; assign axi_r_overflow = \ ; assign axi_r_prog_empty = \ ; assign axi_r_prog_full = \ ; assign axi_r_rd_data_count[10] = \ ; assign axi_r_rd_data_count[9] = \ ; assign axi_r_rd_data_count[8] = \ ; assign axi_r_rd_data_count[7] = \ ; assign axi_r_rd_data_count[6] = \ ; assign axi_r_rd_data_count[5] = \ ; assign axi_r_rd_data_count[4] = \ ; assign axi_r_rd_data_count[3] = \ ; assign axi_r_rd_data_count[2] = \ ; assign axi_r_rd_data_count[1] = \ ; assign axi_r_rd_data_count[0] = \ ; assign axi_r_sbiterr = \ ; assign axi_r_underflow = \ ; assign axi_r_wr_data_count[10] = \ ; assign axi_r_wr_data_count[9] = \ ; assign axi_r_wr_data_count[8] = \ ; assign axi_r_wr_data_count[7] = \ ; assign axi_r_wr_data_count[6] = \ ; assign axi_r_wr_data_count[5] = \ ; assign axi_r_wr_data_count[4] = \ ; assign axi_r_wr_data_count[3] = \ ; assign axi_r_wr_data_count[2] = \ ; assign axi_r_wr_data_count[1] = \ ; assign axi_r_wr_data_count[0] = \ ; assign axi_w_data_count[10] = \ ; assign axi_w_data_count[9] = \ ; assign axi_w_data_count[8] = \ ; assign axi_w_data_count[7] = \ ; assign axi_w_data_count[6] = \ ; assign axi_w_data_count[5] = \ ; assign axi_w_data_count[4] = \ ; assign axi_w_data_count[3] = \ ; assign axi_w_data_count[2] = \ ; assign axi_w_data_count[1] = \ ; assign axi_w_data_count[0] = \ ; assign axi_w_dbiterr = \ ; assign axi_w_overflow = \ ; assign axi_w_prog_empty = \ ; assign axi_w_prog_full = \ ; assign axi_w_rd_data_count[10] = \ ; assign axi_w_rd_data_count[9] = \ ; assign axi_w_rd_data_count[8] = \ ; assign axi_w_rd_data_count[7] = \ ; assign axi_w_rd_data_count[6] = \ ; assign axi_w_rd_data_count[5] = \ ; assign axi_w_rd_data_count[4] = \ ; assign axi_w_rd_data_count[3] = \ ; assign axi_w_rd_data_count[2] = \ ; assign axi_w_rd_data_count[1] = \ ; assign axi_w_rd_data_count[0] = \ ; assign axi_w_sbiterr = \ ; assign axi_w_underflow = \ ; assign axi_w_wr_data_count[10] = \ ; assign axi_w_wr_data_count[9] = \ ; assign axi_w_wr_data_count[8] = \ ; assign axi_w_wr_data_count[7] = \ ; assign axi_w_wr_data_count[6] = \ ; assign axi_w_wr_data_count[5] = \ ; assign axi_w_wr_data_count[4] = \ ; assign axi_w_wr_data_count[3] = \ ; assign axi_w_wr_data_count[2] = \ ; assign axi_w_wr_data_count[1] = \ ; assign axi_w_wr_data_count[0] = \ ; assign axis_data_count[10] = \ ; assign axis_data_count[9] = \ ; assign axis_data_count[8] = \ ; assign axis_data_count[7] = \ ; assign axis_data_count[6] = \ ; assign axis_data_count[5] = \ ; assign axis_data_count[4] = \ ; assign axis_data_count[3] = \ ; assign axis_data_count[2] = \ ; assign axis_data_count[1] = \ ; assign axis_data_count[0] = \ ; assign axis_dbiterr = \ ; assign axis_overflow = \ ; assign axis_prog_empty = \ ; assign axis_prog_full = \ ; assign axis_rd_data_count[10] = \ ; assign axis_rd_data_count[9] = \ ; assign axis_rd_data_count[8] = \ ; assign axis_rd_data_count[7] = \ ; assign axis_rd_data_count[6] = \ ; assign axis_rd_data_count[5] = \ ; assign axis_rd_data_count[4] = \ ; assign axis_rd_data_count[3] = \ ; assign axis_rd_data_count[2] = \ ; assign axis_rd_data_count[1] = \ ; assign axis_rd_data_count[0] = \ ; assign axis_sbiterr = \ ; assign axis_underflow = \ ; assign axis_wr_data_count[10] = \ ; assign axis_wr_data_count[9] = \ ; assign axis_wr_data_count[8] = \ ; assign axis_wr_data_count[7] = \ ; assign axis_wr_data_count[6] = \ ; assign axis_wr_data_count[5] = \ ; assign axis_wr_data_count[4] = \ ; assign axis_wr_data_count[3] = \ ; assign axis_wr_data_count[2] = \ ; assign axis_wr_data_count[1] = \ ; assign axis_wr_data_count[0] = \ ; assign data_count[8] = \ ; assign data_count[7] = \ ; assign data_count[6] = \ ; assign data_count[5] = \ ; assign data_count[4] = \ ; assign data_count[3] = \ ; assign data_count[2] = \ ; assign data_count[1] = \ ; assign data_count[0] = \ ; assign dbiterr = \ ; assign m_axi_araddr[31] = \ ; assign m_axi_araddr[30] = \ ; assign m_axi_araddr[29] = \ ; assign m_axi_araddr[28] = \ ; assign m_axi_araddr[27] = \ ; assign m_axi_araddr[26] = \ ; assign m_axi_araddr[25] = \ ; assign m_axi_araddr[24] = \ ; assign m_axi_araddr[23] = \ ; assign m_axi_araddr[22] = \ ; assign m_axi_araddr[21] = \ ; assign m_axi_araddr[20] = \ ; assign m_axi_araddr[19] = \ ; assign m_axi_araddr[18] = \ ; assign m_axi_araddr[17] = \ ; assign m_axi_araddr[16] = \ ; assign m_axi_araddr[15] = \ ; assign m_axi_araddr[14] = \ ; assign m_axi_araddr[13] = \ ; assign m_axi_araddr[12] = \ ; assign m_axi_araddr[11] = \ ; assign m_axi_araddr[10] = \ ; assign m_axi_araddr[9] = \ ; assign m_axi_araddr[8] = \ ; assign m_axi_araddr[7] = \ ; assign m_axi_araddr[6] = \ ; assign m_axi_araddr[5] = \ ; assign m_axi_araddr[4] = \ ; assign m_axi_araddr[3] = \ ; assign m_axi_araddr[2] = \ ; assign m_axi_araddr[1] = \ ; assign m_axi_araddr[0] = \ ; assign m_axi_arburst[1] = \ ; assign m_axi_arburst[0] = \ ; assign m_axi_arcache[3] = \ ; assign m_axi_arcache[2] = \ ; assign m_axi_arcache[1] = \ ; assign m_axi_arcache[0] = \ ; assign m_axi_arid[0] = \ ; assign m_axi_arlen[7] = \ ; assign m_axi_arlen[6] = \ ; assign m_axi_arlen[5] = \ ; assign m_axi_arlen[4] = \ ; assign m_axi_arlen[3] = \ ; assign m_axi_arlen[2] = \ ; assign m_axi_arlen[1] = \ ; assign m_axi_arlen[0] = \ ; assign m_axi_arlock[0] = \ ; assign m_axi_arprot[2] = \ ; assign m_axi_arprot[1] = \ ; assign m_axi_arprot[0] = \ ; assign m_axi_arqos[3] = \ ; assign m_axi_arqos[2] = \ ; assign m_axi_arqos[1] = \ ; assign m_axi_arqos[0] = \ ; assign m_axi_arregion[3] = \ ; assign m_axi_arregion[2] = \ ; assign m_axi_arregion[1] = \ ; assign m_axi_arregion[0] = \ ; assign m_axi_arsize[2] = \ ; assign m_axi_arsize[1] = \ ; assign m_axi_arsize[0] = \ ; assign m_axi_aruser[0] = \ ; assign m_axi_arvalid = \ ; assign m_axi_awaddr[31] = \ ; assign m_axi_awaddr[30] = \ ; assign m_axi_awaddr[29] = \ ; assign m_axi_awaddr[28] = \ ; assign m_axi_awaddr[27] = \ ; assign m_axi_awaddr[26] = \ ; assign m_axi_awaddr[25] = \ ; assign m_axi_awaddr[24] = \ ; assign m_axi_awaddr[23] = \ ; assign m_axi_awaddr[22] = \ ; assign m_axi_awaddr[21] = \ ; assign m_axi_awaddr[20] = \ ; assign m_axi_awaddr[19] = \ ; assign m_axi_awaddr[18] = \ ; assign m_axi_awaddr[17] = \ ; assign m_axi_awaddr[16] = \ ; assign m_axi_awaddr[15] = \ ; assign m_axi_awaddr[14] = \ ; assign m_axi_awaddr[13] = \ ; assign m_axi_awaddr[12] = \ ; assign m_axi_awaddr[11] = \ ; assign m_axi_awaddr[10] = \ ; assign m_axi_awaddr[9] = \ ; assign m_axi_awaddr[8] = \ ; assign m_axi_awaddr[7] = \ ; assign m_axi_awaddr[6] = \ ; assign m_axi_awaddr[5] = \ ; assign m_axi_awaddr[4] = \ ; assign m_axi_awaddr[3] = \ ; assign m_axi_awaddr[2] = \ ; assign m_axi_awaddr[1] = \ ; assign m_axi_awaddr[0] = \ ; assign m_axi_awburst[1] = \ ; assign m_axi_awburst[0] = \ ; assign m_axi_awcache[3] = \ ; assign m_axi_awcache[2] = \ ; assign m_axi_awcache[1] = \ ; assign m_axi_awcache[0] = \ ; assign m_axi_awid[0] = \ ; assign m_axi_awlen[7] = \ ; assign m_axi_awlen[6] = \ ; assign m_axi_awlen[5] = \ ; assign m_axi_awlen[4] = \ ; assign m_axi_awlen[3] = \ ; assign m_axi_awlen[2] = \ ; assign m_axi_awlen[1] = \ ; assign m_axi_awlen[0] = \ ; assign m_axi_awlock[0] = \ ; assign m_axi_awprot[2] = \ ; assign m_axi_awprot[1] = \ ; assign m_axi_awprot[0] = \ ; assign m_axi_awqos[3] = \ ; assign m_axi_awqos[2] = \ ; assign m_axi_awqos[1] = \ ; assign m_axi_awqos[0] = \ ; assign m_axi_awregion[3] = \ ; assign m_axi_awregion[2] = \ ; assign m_axi_awregion[1] = \ ; assign m_axi_awregion[0] = \ ; assign m_axi_awsize[2] = \ ; assign m_axi_awsize[1] = \ ; assign m_axi_awsize[0] = \ ; assign m_axi_awuser[0] = \ ; assign m_axi_awvalid = \ ; assign m_axi_bready = \ ; assign m_axi_rready = \ ; assign m_axi_wdata[63] = \ ; assign m_axi_wdata[62] = \ ; assign m_axi_wdata[61] = \ ; assign m_axi_wdata[60] = \ ; assign m_axi_wdata[59] = \ ; assign m_axi_wdata[58] = \ ; assign m_axi_wdata[57] = \ ; assign m_axi_wdata[56] = \ ; assign m_axi_wdata[55] = \ ; assign m_axi_wdata[54] = \ ; assign m_axi_wdata[53] = \ ; assign m_axi_wdata[52] = \ ; assign m_axi_wdata[51] = \ ; assign m_axi_wdata[50] = \ ; assign m_axi_wdata[49] = \ ; assign m_axi_wdata[48] = \ ; assign m_axi_wdata[47] = \ ; assign m_axi_wdata[46] = \ ; assign m_axi_wdata[45] = \ ; assign m_axi_wdata[44] = \ ; assign m_axi_wdata[43] = \ ; assign m_axi_wdata[42] = \ ; assign m_axi_wdata[41] = \ ; assign m_axi_wdata[40] = \ ; assign m_axi_wdata[39] = \ ; assign m_axi_wdata[38] = \ ; assign m_axi_wdata[37] = \ ; assign m_axi_wdata[36] = \ ; assign m_axi_wdata[35] = \ ; assign m_axi_wdata[34] = \ ; assign m_axi_wdata[33] = \ ; assign m_axi_wdata[32] = \ ; assign m_axi_wdata[31] = \ ; assign m_axi_wdata[30] = \ ; assign m_axi_wdata[29] = \ ; assign m_axi_wdata[28] = \ ; assign m_axi_wdata[27] = \ ; assign m_axi_wdata[26] = \ ; assign m_axi_wdata[25] = \ ; assign m_axi_wdata[24] = \ ; assign m_axi_wdata[23] = \ ; assign m_axi_wdata[22] = \ ; assign m_axi_wdata[21] = \ ; assign m_axi_wdata[20] = \ ; assign m_axi_wdata[19] = \ ; assign m_axi_wdata[18] = \ ; assign m_axi_wdata[17] = \ ; assign m_axi_wdata[16] = \ ; assign m_axi_wdata[15] = \ ; assign m_axi_wdata[14] = \ ; assign m_axi_wdata[13] = \ ; assign m_axi_wdata[12] = \ ; assign m_axi_wdata[11] = \ ; assign m_axi_wdata[10] = \ ; assign m_axi_wdata[9] = \ ; assign m_axi_wdata[8] = \ ; assign m_axi_wdata[7] = \ ; assign m_axi_wdata[6] = \ ; assign m_axi_wdata[5] = \ ; assign m_axi_wdata[4] = \ ; assign m_axi_wdata[3] = \ ; assign m_axi_wdata[2] = \ ; assign m_axi_wdata[1] = \ ; assign m_axi_wdata[0] = \ ; assign m_axi_wid[0] = \ ; assign m_axi_wlast = \ ; assign m_axi_wstrb[7] = \ ; assign m_axi_wstrb[6] = \ ; assign m_axi_wstrb[5] = \ ; assign m_axi_wstrb[4] = \ ; assign m_axi_wstrb[3] = \ ; assign m_axi_wstrb[2] = \ ; assign m_axi_wstrb[1] = \ ; assign m_axi_wstrb[0] = \ ; assign m_axi_wuser[0] = \ ; assign m_axi_wvalid = \ ; assign m_axis_tdata[7] = \ ; assign m_axis_tdata[6] = \ ; assign m_axis_tdata[5] = \ ; assign m_axis_tdata[4] = \ ; assign m_axis_tdata[3] = \ ; assign m_axis_tdata[2] = \ ; assign m_axis_tdata[1] = \ ; assign m_axis_tdata[0] = \ ; assign m_axis_tdest[0] = \ ; assign m_axis_tid[0] = \ ; assign m_axis_tkeep[0] = \ ; assign m_axis_tlast = \ ; assign m_axis_tstrb[0] = \ ; assign m_axis_tuser[3] = \ ; assign m_axis_tuser[2] = \ ; assign m_axis_tuser[1] = \ ; assign m_axis_tuser[0] = \ ; assign m_axis_tvalid = \ ; assign overflow = \ ; assign prog_empty = \ ; assign rd_data_count[10] = \ ; assign rd_data_count[9] = \ ; assign rd_data_count[8] = \ ; assign rd_data_count[7] = \ ; assign rd_data_count[6] = \ ; assign rd_data_count[5] = \ ; assign rd_data_count[4] = \ ; assign rd_data_count[3] = \ ; assign rd_data_count[2] = \ ; assign rd_data_count[1] = \ ; assign rd_data_count[0] = \ ; assign rd_rst_busy = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_buser[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_ruser[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_wready = \ ; assign s_axis_tready = \ ; assign sbiterr = \ ; assign underflow = \ ; assign valid = \ ; assign wr_ack = \ ; assign wr_data_count[8] = \ ; assign wr_data_count[7] = \ ; assign wr_data_count[6] = \ ; assign wr_data_count[5] = \ ; assign wr_data_count[4] = \ ; assign wr_data_count[3] = \ ; assign wr_data_count[2] = \ ; assign wr_data_count[1] = \ ; assign wr_data_count[0] = \ ; GND GND (.G(\ )); VCC VCC (.P(\ )); fb_output_fifo_fifo_generator_v13_1_2_synth inst_fifo_gen (.WR_RST_BUSY(wr_rst_busy), .din(din), .dout(dout), .empty(empty), .full(full), .prog_full(prog_full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_1_2_synth" *) module fb_output_fifo_fifo_generator_v13_1_2_synth (WR_RST_BUSY, dout, empty, full, prog_full, rd_en, wr_en, rd_clk, wr_clk, din, rst); output WR_RST_BUSY; output [31:0]dout; output empty; output full; output prog_full; input rd_en; input wr_en; input rd_clk; input wr_clk; input [127:0]din; input rst; wire WR_RST_BUSY; wire [127:0]din; wire [31:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire wr_en; fb_output_fifo_fifo_generator_top \gconvfifo.rf (.WR_RST_BUSY(WR_RST_BUSY), .din(din), .dout(dout), .empty(empty), .full(full), .prog_full(prog_full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "memory" *) module fb_output_fifo_memory (dout, rd_clk, wr_clk, tmp_ram_rd_en, WEBWE, out, Q, \gic0.gc0.count_d2_reg[8] , din); output [31:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]WEBWE; input [0:0]out; input [10:0]Q; input [8:0]\gic0.gc0.count_d2_reg[8] ; input [127:0]din; wire [10:0]Q; wire [0:0]WEBWE; wire [127:0]din; wire [31:0]dout; wire [8:0]\gic0.gc0.count_d2_reg[8] ; wire [0:0]out; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fb_output_fifo_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg (.Q(Q), .WEBWE(WEBWE), .din(din), .dout(dout), .\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ), .out(out), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module fb_output_fifo_rd_bin_cntr (ram_empty_fb_i_reg, Q, ram_empty_fb_i_reg_0, \gc0.count_d1_reg[9]_0 , v1_reg, v1_reg_0, WR_PNTR_RD, E, rd_clk, AR); output ram_empty_fb_i_reg; output [10:0]Q; output ram_empty_fb_i_reg_0; output [7:0]\gc0.count_d1_reg[9]_0 ; output [0:0]v1_reg; output [0:0]v1_reg_0; input [0:0]WR_PNTR_RD; input [0:0]E; input rd_clk; input [0:0]AR; wire [0:0]AR; wire [0:0]E; wire [10:0]Q; wire [0:0]WR_PNTR_RD; wire \gc0.count[10]_i_2_n_0 ; wire [7:0]\gc0.count_d1_reg[9]_0 ; wire [10:0]plusOp__0; wire ram_empty_fb_i_reg; wire ram_empty_fb_i_reg_0; wire rd_clk; wire [10:0]rd_pntr_plus1; wire [0:0]v1_reg; wire [0:0]v1_reg_0; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1 (.I0(rd_pntr_plus1[0]), .O(plusOp__0[0])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gc0.count[10]_i_1 (.I0(\gc0.count_d1_reg[9]_0 [6]), .I1(\gc0.count_d1_reg[9]_0 [4]), .I2(\gc0.count[10]_i_2_n_0 ), .I3(\gc0.count_d1_reg[9]_0 [5]), .I4(\gc0.count_d1_reg[9]_0 [7]), .I5(rd_pntr_plus1[10]), .O(plusOp__0[10])); LUT6 #( .INIT(64'h8000000000000000)) \gc0.count[10]_i_2 (.I0(\gc0.count_d1_reg[9]_0 [3]), .I1(\gc0.count_d1_reg[9]_0 [1]), .I2(rd_pntr_plus1[1]), .I3(rd_pntr_plus1[0]), .I4(\gc0.count_d1_reg[9]_0 [0]), .I5(\gc0.count_d1_reg[9]_0 [2]), .O(\gc0.count[10]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1 (.I0(rd_pntr_plus1[0]), .I1(rd_pntr_plus1[1]), .O(plusOp__0[1])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'h78)) \gc0.count[2]_i_1 (.I0(rd_pntr_plus1[0]), .I1(rd_pntr_plus1[1]), .I2(\gc0.count_d1_reg[9]_0 [0]), .O(plusOp__0[2])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[3]_i_1 (.I0(rd_pntr_plus1[1]), .I1(rd_pntr_plus1[0]), .I2(\gc0.count_d1_reg[9]_0 [0]), .I3(\gc0.count_d1_reg[9]_0 [1]), .O(plusOp__0[3])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT5 #( .INIT(32'h7FFF8000)) \gc0.count[4]_i_1 (.I0(\gc0.count_d1_reg[9]_0 [0]), .I1(rd_pntr_plus1[0]), .I2(rd_pntr_plus1[1]), .I3(\gc0.count_d1_reg[9]_0 [1]), .I4(\gc0.count_d1_reg[9]_0 [2]), .O(plusOp__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gc0.count[5]_i_1 (.I0(\gc0.count_d1_reg[9]_0 [1]), .I1(rd_pntr_plus1[1]), .I2(rd_pntr_plus1[0]), .I3(\gc0.count_d1_reg[9]_0 [0]), .I4(\gc0.count_d1_reg[9]_0 [2]), .I5(\gc0.count_d1_reg[9]_0 [3]), .O(plusOp__0[5])); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h6)) \gc0.count[6]_i_1 (.I0(\gc0.count[10]_i_2_n_0 ), .I1(\gc0.count_d1_reg[9]_0 [4]), .O(plusOp__0[6])); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'h78)) \gc0.count[7]_i_1 (.I0(\gc0.count[10]_i_2_n_0 ), .I1(\gc0.count_d1_reg[9]_0 [4]), .I2(\gc0.count_d1_reg[9]_0 [5]), .O(plusOp__0[7])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[8]_i_1 (.I0(\gc0.count_d1_reg[9]_0 [4]), .I1(\gc0.count[10]_i_2_n_0 ), .I2(\gc0.count_d1_reg[9]_0 [5]), .I3(\gc0.count_d1_reg[9]_0 [6]), .O(plusOp__0[8])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT5 #( .INIT(32'h7FFF8000)) \gc0.count[9]_i_1 (.I0(\gc0.count_d1_reg[9]_0 [5]), .I1(\gc0.count[10]_i_2_n_0 ), .I2(\gc0.count_d1_reg[9]_0 [4]), .I3(\gc0.count_d1_reg[9]_0 [6]), .I4(\gc0.count_d1_reg[9]_0 [7]), .O(plusOp__0[9])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(rd_clk), .CE(E), .CLR(AR), .D(rd_pntr_plus1[0]), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[10] (.C(rd_clk), .CE(E), .CLR(AR), .D(rd_pntr_plus1[10]), .Q(Q[10])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(rd_clk), .CE(E), .CLR(AR), .D(rd_pntr_plus1[1]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [0]), .Q(Q[2])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [1]), .Q(Q[3])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[4] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [2]), .Q(Q[4])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[5] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [3]), .Q(Q[5])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[6] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [4]), .Q(Q[6])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[7] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [5]), .Q(Q[7])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[8] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [6]), .Q(Q[8])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[9] (.C(rd_clk), .CE(E), .CLR(AR), .D(\gc0.count_d1_reg[9]_0 [7]), .Q(Q[9])); FDPE #( .INIT(1'b1)) \gc0.count_reg[0] (.C(rd_clk), .CE(E), .D(plusOp__0[0]), .PRE(AR), .Q(rd_pntr_plus1[0])); FDCE #( .INIT(1'b0)) \gc0.count_reg[10] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[10]), .Q(rd_pntr_plus1[10])); FDCE #( .INIT(1'b0)) \gc0.count_reg[1] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[1]), .Q(rd_pntr_plus1[1])); FDCE #( .INIT(1'b0)) \gc0.count_reg[2] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[2]), .Q(\gc0.count_d1_reg[9]_0 [0])); FDCE #( .INIT(1'b0)) \gc0.count_reg[3] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[3]), .Q(\gc0.count_d1_reg[9]_0 [1])); FDCE #( .INIT(1'b0)) \gc0.count_reg[4] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[4]), .Q(\gc0.count_d1_reg[9]_0 [2])); FDCE #( .INIT(1'b0)) \gc0.count_reg[5] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[5]), .Q(\gc0.count_d1_reg[9]_0 [3])); FDCE #( .INIT(1'b0)) \gc0.count_reg[6] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[6]), .Q(\gc0.count_d1_reg[9]_0 [4])); FDCE #( .INIT(1'b0)) \gc0.count_reg[7] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[7]), .Q(\gc0.count_d1_reg[9]_0 [5])); FDCE #( .INIT(1'b0)) \gc0.count_reg[8] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[8]), .Q(\gc0.count_d1_reg[9]_0 [6])); FDCE #( .INIT(1'b0)) \gc0.count_reg[9] (.C(rd_clk), .CE(E), .CLR(AR), .D(plusOp__0[9]), .Q(\gc0.count_d1_reg[9]_0 [7])); LUT2 #( .INIT(4'h1)) \gmux.gm[0].gm1.m1_i_1 (.I0(Q[0]), .I1(Q[1]), .O(v1_reg)); LUT2 #( .INIT(4'h1)) \gmux.gm[0].gm1.m1_i_1__0 (.I0(rd_pntr_plus1[0]), .I1(rd_pntr_plus1[1]), .O(v1_reg_0)); LUT2 #( .INIT(4'h9)) \gmux.gm[5].gms.ms_i_1 (.I0(Q[10]), .I1(WR_PNTR_RD), .O(ram_empty_fb_i_reg)); LUT2 #( .INIT(4'h9)) \gmux.gm[5].gms.ms_i_1__0 (.I0(rd_pntr_plus1[10]), .I1(WR_PNTR_RD), .O(ram_empty_fb_i_reg_0)); endmodule (* ORIG_REF_NAME = "rd_logic" *) module fb_output_fifo_rd_logic (empty, out, Q, \gc0.count_d1_reg[9] , \gnxpm_cdc.wr_pntr_bin_reg[6] , \gnxpm_cdc.wr_pntr_bin_reg[6]_0 , rd_clk, AR, rd_en, WR_PNTR_RD); output empty; output out; output [10:0]Q; output [7:0]\gc0.count_d1_reg[9] ; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ; input rd_clk; input [0:0]AR; input rd_en; input [0:0]WR_PNTR_RD; wire [0:0]AR; wire [10:0]Q; wire [0:0]WR_PNTR_RD; wire [0:0]\c0/v1_reg ; wire [0:0]\c1/v1_reg ; wire empty; wire [7:0]\gc0.count_d1_reg[9] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ; wire \gras.rsts_n_2 ; wire out; wire rd_clk; wire rd_en; wire rpntr_n_0; wire rpntr_n_12; fb_output_fifo_rd_status_flags_as \gras.rsts (.AR(AR), .E(\gras.rsts_n_2 ), .empty(empty), .\gc0.count_d1_reg[10] (rpntr_n_0), .\gc0.count_reg[10] (rpntr_n_12), .\gnxpm_cdc.wr_pntr_bin_reg[6] (\gnxpm_cdc.wr_pntr_bin_reg[6] ), .\gnxpm_cdc.wr_pntr_bin_reg[6]_0 (\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ), .out(out), .rd_clk(rd_clk), .rd_en(rd_en), .v1_reg(\c0/v1_reg ), .v1_reg_0(\c1/v1_reg )); fb_output_fifo_rd_bin_cntr rpntr (.AR(AR), .E(\gras.rsts_n_2 ), .Q(Q), .WR_PNTR_RD(WR_PNTR_RD), .\gc0.count_d1_reg[9]_0 (\gc0.count_d1_reg[9] ), .ram_empty_fb_i_reg(rpntr_n_0), .ram_empty_fb_i_reg_0(rpntr_n_12), .rd_clk(rd_clk), .v1_reg(\c0/v1_reg ), .v1_reg_0(\c1/v1_reg )); endmodule (* ORIG_REF_NAME = "rd_status_flags_as" *) module fb_output_fifo_rd_status_flags_as (empty, out, E, v1_reg, \gnxpm_cdc.wr_pntr_bin_reg[6] , \gc0.count_d1_reg[10] , v1_reg_0, \gnxpm_cdc.wr_pntr_bin_reg[6]_0 , \gc0.count_reg[10] , rd_clk, AR, rd_en); output empty; output out; output [0:0]E; input [0:0]v1_reg; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; input \gc0.count_d1_reg[10] ; input [0:0]v1_reg_0; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ; input \gc0.count_reg[10] ; input rd_clk; input [0:0]AR; input rd_en; wire [0:0]AR; wire [0:0]E; wire c0_n_0; wire comp1; wire \gc0.count_d1_reg[10] ; wire \gc0.count_reg[10] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ; (* DONT_TOUCH *) wire ram_empty_fb_i; (* DONT_TOUCH *) wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]v1_reg; wire [0:0]v1_reg_0; assign empty = ram_empty_i; assign out = ram_empty_fb_i; fb_output_fifo_compare c0 (.comp1(comp1), .\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ), .\gnxpm_cdc.wr_pntr_bin_reg[6] (\gnxpm_cdc.wr_pntr_bin_reg[6] ), .out(ram_empty_fb_i), .ram_empty_fb_i_reg(c0_n_0), .rd_en(rd_en), .v1_reg(v1_reg)); fb_output_fifo_compare_3 c1 (.comp1(comp1), .\gc0.count_reg[10] (\gc0.count_reg[10] ), .\gnxpm_cdc.wr_pntr_bin_reg[6] (\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ), .v1_reg_0(v1_reg_0)); LUT2 #( .INIT(4'h2)) \gc0.count_d1[10]_i_1 (.I0(rd_en), .I1(ram_empty_fb_i), .O(E)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_fb_i_reg (.C(rd_clk), .CE(1'b1), .D(c0_n_0), .PRE(AR), .Q(ram_empty_fb_i)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(c0_n_0), .PRE(AR), .Q(ram_empty_i)); endmodule (* ORIG_REF_NAME = "reset_blk_ramfifo" *) module fb_output_fifo_reset_blk_ramfifo (out, \gc0.count_reg[1] , \grstd1.grst_full.grst_f.rst_d3_reg_0 , WR_RST_BUSY, tmp_ram_rd_en, rd_clk, wr_clk, rst, ram_empty_fb_i_reg, rd_en); output [1:0]out; output [2:0]\gc0.count_reg[1] ; output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; output WR_RST_BUSY; output tmp_ram_rd_en; input rd_clk; input wr_clk; input rst; input ram_empty_fb_i_reg; input rd_en; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ; wire p_7_out; wire p_8_out; wire ram_empty_fb_i_reg; wire rd_clk; wire rd_en; wire rd_rst_asreg; (* DONT_TOUCH *) wire [2:0]rd_rst_reg; wire rst; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d2; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d3; (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; wire tmp_ram_rd_en; wire wr_clk; wire wr_rst_asreg; (* DONT_TOUCH *) wire [2:0]wr_rst_reg; assign WR_RST_BUSY = rst_d3; assign \gc0.count_reg[1] [2:0] = rd_rst_reg; assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2; assign out[1:0] = wr_rst_reg[1:0]; LUT3 #( .INIT(8'hBA)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 (.I0(rd_rst_reg[0]), .I1(ram_empty_fb_i_reg), .I2(rd_en), .O(tmp_ram_rd_en)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d1_reg (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(rst_wr_reg2), .Q(rst_d1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d2_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1), .PRE(rst_wr_reg2), .Q(rst_d2)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d3_reg (.C(wr_clk), .CE(1'b1), .D(rst_d2), .PRE(rst_wr_reg2), .Q(rst_d3)); fb_output_fifo_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst (.in0(rd_rst_asreg), .\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ), .out(p_7_out), .rd_clk(rd_clk)); fb_output_fifo_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst (.in0(wr_rst_asreg), .\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ), .out(p_8_out), .wr_clk(wr_clk)); fb_output_fifo_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .in0(rd_rst_asreg), .out(p_7_out), .rd_clk(rd_clk)); fb_output_fifo_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .in0(wr_rst_asreg), .out(p_8_out), .wr_clk(wr_clk)); FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (.C(rd_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ), .PRE(rst_rd_reg2), .Q(rd_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .Q(rd_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .Q(rd_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), .Q(rd_rst_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg (.C(rd_clk), .CE(1'b1), .D(1'b0), .PRE(rst), .Q(rst_rd_reg1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg (.C(rd_clk), .CE(1'b1), .D(rst_rd_reg1), .PRE(rst), .Q(rst_rd_reg2)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(rst), .Q(rst_wr_reg1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg (.C(wr_clk), .CE(1'b1), .D(rst_wr_reg1), .PRE(rst), .Q(rst_wr_reg2)); FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (.C(wr_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ), .PRE(rst_wr_reg2), .Q(wr_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .Q(wr_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .Q(wr_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] (.C(wr_clk), .CE(1'b1), .D(1'b0), .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), .Q(wr_rst_reg[2])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff (out, \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg , in0, rd_clk); output out; output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ; input [0:0]in0; input rd_clk; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ; wire rd_clk; assign out = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .D(in0), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1 (.I0(in0), .I1(Q_reg), .O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg )); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff_0 (out, \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg , in0, wr_clk); output out; output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ; input [0:0]in0; input wr_clk; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ; wire wr_clk; assign out = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .D(in0), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1 (.I0(in0), .I1(Q_reg), .O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg )); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff_1 (AS, out, rd_clk, in0); output [0:0]AS; input out; input rd_clk; input [0:0]in0; wire [0:0]AS; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire out; wire rd_clk; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .D(out), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 (.I0(in0), .I1(Q_reg), .O(AS)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff_2 (AS, out, wr_clk, in0); output [0:0]AS; input out; input wr_clk; input [0:0]in0; wire [0:0]AS; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire [0:0]in0; wire out; wire wr_clk; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .D(out), .Q(Q_reg), .R(1'b0)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 (.I0(in0), .I1(Q_reg), .O(AS)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff__parameterized0 (D, Q, rd_clk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); output [8:0]D; input [8:0]Q; input rd_clk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire [8:0]Q; (* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire rd_clk; assign D[8:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(Q[8]), .Q(Q_reg[8])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff__parameterized1 (D, Q, wr_clk, AR); output [10:0]D; input [10:0]Q; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [10:0]Q; (* async_reg = "true" *) (* msgon = "true" *) wire [10:0]Q_reg; wire wr_clk; assign D[10:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[10] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[10]), .Q(Q_reg[10])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[8]), .Q(Q_reg[8])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[9] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(Q[9]), .Q(Q_reg[9])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff__parameterized2 (out, \gnxpm_cdc.wr_pntr_bin_reg[7] , D, rd_clk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); output [0:0]out; output [7:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; input [8:0]D; input rd_clk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire [8:0]D; (* async_reg = "true" *) (* msgon = "true" *) wire [8:0]Q_reg; wire \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ; wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ; wire [7:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; wire rd_clk; assign out[0] = Q_reg[8]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(rd_clk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), .D(D[8]), .Q(Q_reg[8])); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[0]_i_1 (.I0(Q_reg[1]), .I1(Q_reg[0]), .I2(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), .I3(Q_reg[3]), .I4(Q_reg[2]), .I5(Q_reg[8]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [0])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[1]_i_1 (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), .I1(Q_reg[3]), .I2(Q_reg[2]), .I3(Q_reg[8]), .I4(Q_reg[1]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [1])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.wr_pntr_bin[1]_i_2 (.I0(Q_reg[7]), .I1(Q_reg[6]), .I2(Q_reg[5]), .I3(Q_reg[4]), .O(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[2]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[2]), .I2(Q_reg[3]), .I3(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), .I4(Q_reg[6]), .I5(Q_reg[7]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [2])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_bin[2]_i_2 (.I0(Q_reg[4]), .I1(Q_reg[5]), .O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[3]_i_1 (.I0(Q_reg[5]), .I1(Q_reg[3]), .I2(Q_reg[4]), .I3(Q_reg[8]), .I4(Q_reg[6]), .I5(Q_reg[7]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [3])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[4]_i_1 (.I0(Q_reg[6]), .I1(Q_reg[4]), .I2(Q_reg[5]), .I3(Q_reg[8]), .I4(Q_reg[7]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [4])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.wr_pntr_bin[5]_i_1 (.I0(Q_reg[6]), .I1(Q_reg[5]), .I2(Q_reg[8]), .I3(Q_reg[7]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [5])); LUT3 #( .INIT(8'h96)) \gnxpm_cdc.wr_pntr_bin[6]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[6]), .I2(Q_reg[8]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [6])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_bin[7]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[8]), .O(\gnxpm_cdc.wr_pntr_bin_reg[7] [7])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module fb_output_fifo_synchronizer_ff__parameterized3 (out, \gnxpm_cdc.rd_pntr_bin_reg[9] , D, wr_clk, AR); output [0:0]out; output [7:0]\gnxpm_cdc.rd_pntr_bin_reg[9] ; input [10:0]D; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [10:0]D; (* async_reg = "true" *) (* msgon = "true" *) wire [10:0]Q_reg; wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ; wire \gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ; wire [7:0]\gnxpm_cdc.rd_pntr_bin_reg[9] ; wire wr_clk; assign out[0] = Q_reg[10]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[0]), .Q(Q_reg[0])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[10] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[10]), .Q(Q_reg[10])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[1]), .Q(Q_reg[1])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[2]), .Q(Q_reg[2])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[3]), .Q(Q_reg[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[4]), .Q(Q_reg[4])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[5]), .Q(Q_reg[5])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[6]), .Q(Q_reg[6])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[7]), .Q(Q_reg[7])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[8]), .Q(Q_reg[8])); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDCE #( .INIT(1'b0)) \Q_reg_reg[9] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[9]), .Q(Q_reg[9])); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[2]_i_1 (.I0(Q_reg[3]), .I1(Q_reg[2]), .I2(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ), .I3(Q_reg[5]), .I4(Q_reg[4]), .I5(Q_reg[10]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [0])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[3]_i_1 (.I0(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ), .I1(Q_reg[5]), .I2(Q_reg[4]), .I3(Q_reg[10]), .I4(Q_reg[3]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [1])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.rd_pntr_bin[3]_i_2 (.I0(Q_reg[9]), .I1(Q_reg[8]), .I2(Q_reg[7]), .I3(Q_reg[6]), .O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[4]_i_1 (.I0(Q_reg[10]), .I1(Q_reg[4]), .I2(Q_reg[5]), .I3(\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ), .I4(Q_reg[8]), .I5(Q_reg[9]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [2])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_bin[4]_i_2 (.I0(Q_reg[6]), .I1(Q_reg[7]), .O(\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[5]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[5]), .I2(Q_reg[6]), .I3(Q_reg[10]), .I4(Q_reg[8]), .I5(Q_reg[9]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [3])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[6]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[6]), .I2(Q_reg[7]), .I3(Q_reg[10]), .I4(Q_reg[9]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [4])); LUT4 #( .INIT(16'h6996)) \gnxpm_cdc.rd_pntr_bin[7]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[7]), .I2(Q_reg[10]), .I3(Q_reg[9]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [5])); LUT3 #( .INIT(8'h96)) \gnxpm_cdc.rd_pntr_bin[8]_i_1 (.I0(Q_reg[9]), .I1(Q_reg[8]), .I2(Q_reg[10]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [6])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.rd_pntr_bin[9]_i_1 (.I0(Q_reg[9]), .I1(Q_reg[10]), .O(\gnxpm_cdc.rd_pntr_bin_reg[9] [7])); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module fb_output_fifo_wr_bin_cntr (S, Q, \gdiff.diff_pntr_pad_reg[8] , \gdiff.diff_pntr_pad_reg[9] , \gic0.gc0.count_d1_reg[8]_0 , v1_reg, v1_reg_0, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , RD_PNTR_WR, E, wr_clk, AR); output [3:0]S; output [8:0]Q; output [3:0]\gdiff.diff_pntr_pad_reg[8] ; output [0:0]\gdiff.diff_pntr_pad_reg[9] ; output [0:0]\gic0.gc0.count_d1_reg[8]_0 ; output [3:0]v1_reg; output [3:0]v1_reg_0; output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; input [8:0]RD_PNTR_WR; input [0:0]E; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; wire [8:0]Q; wire [8:0]RD_PNTR_WR; wire [3:0]S; wire [3:0]\gdiff.diff_pntr_pad_reg[8] ; wire [0:0]\gdiff.diff_pntr_pad_reg[9] ; wire \gic0.gc0.count[8]_i_2_n_0 ; wire [0:0]\gic0.gc0.count_d1_reg[8]_0 ; wire [8:0]plusOp__1; wire [3:0]v1_reg; wire [3:0]v1_reg_0; wire wr_clk; wire [7:0]wr_pntr_plus2; (* SOFT_HLUTNM = "soft_lutpair15" *) LUT1 #( .INIT(2'h1)) \gic0.gc0.count[0]_i_1 (.I0(wr_pntr_plus2[0]), .O(plusOp__1[0])); LUT2 #( .INIT(4'h6)) \gic0.gc0.count[1]_i_1 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .O(plusOp__1[1])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[2]_i_1 (.I0(wr_pntr_plus2[0]), .I1(wr_pntr_plus2[1]), .I2(wr_pntr_plus2[2]), .O(plusOp__1[2])); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[3]_i_1 (.I0(wr_pntr_plus2[1]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[2]), .I3(wr_pntr_plus2[3]), .O(plusOp__1[3])); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT5 #( .INIT(32'h7FFF8000)) \gic0.gc0.count[4]_i_1 (.I0(wr_pntr_plus2[2]), .I1(wr_pntr_plus2[0]), .I2(wr_pntr_plus2[1]), .I3(wr_pntr_plus2[3]), .I4(wr_pntr_plus2[4]), .O(plusOp__1[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gic0.gc0.count[5]_i_1 (.I0(wr_pntr_plus2[3]), .I1(wr_pntr_plus2[1]), .I2(wr_pntr_plus2[0]), .I3(wr_pntr_plus2[2]), .I4(wr_pntr_plus2[4]), .I5(wr_pntr_plus2[5]), .O(plusOp__1[5])); LUT2 #( .INIT(4'h6)) \gic0.gc0.count[6]_i_1 (.I0(\gic0.gc0.count[8]_i_2_n_0 ), .I1(wr_pntr_plus2[6]), .O(plusOp__1[6])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[7]_i_1 (.I0(\gic0.gc0.count[8]_i_2_n_0 ), .I1(wr_pntr_plus2[6]), .I2(wr_pntr_plus2[7]), .O(plusOp__1[7])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[8]_i_1 (.I0(wr_pntr_plus2[6]), .I1(\gic0.gc0.count[8]_i_2_n_0 ), .I2(wr_pntr_plus2[7]), .I3(\gic0.gc0.count_d1_reg[8]_0 ), .O(plusOp__1[8])); LUT6 #( .INIT(64'h8000000000000000)) \gic0.gc0.count[8]_i_2 (.I0(wr_pntr_plus2[5]), .I1(wr_pntr_plus2[3]), .I2(wr_pntr_plus2[1]), .I3(wr_pntr_plus2[0]), .I4(wr_pntr_plus2[2]), .I5(wr_pntr_plus2[4]), .O(\gic0.gc0.count[8]_i_2_n_0 )); FDPE #( .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), .CE(E), .D(wr_pntr_plus2[0]), .PRE(AR), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[1]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[2]), .Q(Q[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[3]), .Q(Q[3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[4]), .Q(Q[4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[5] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[5]), .Q(Q[5])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[6] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[6]), .Q(Q[6])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[7] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[7]), .Q(Q[7])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[8] (.C(wr_clk), .CE(E), .CLR(AR), .D(\gic0.gc0.count_d1_reg[8]_0 ), .Q(Q[8])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[0]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[1]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[2]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[3]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[4]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[5] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[5]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[6] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[6]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[7] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[7]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[8] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[8]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[0]), .Q(wr_pntr_plus2[0])); FDPE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), .CE(E), .D(plusOp__1[1]), .PRE(AR), .Q(wr_pntr_plus2[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[2]), .Q(wr_pntr_plus2[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[3]), .Q(wr_pntr_plus2[3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[4]), .Q(wr_pntr_plus2[4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[5] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[5]), .Q(wr_pntr_plus2[5])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[6] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[6]), .Q(wr_pntr_plus2[6])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[7] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[7]), .Q(wr_pntr_plus2[7])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[8] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__1[8]), .Q(\gic0.gc0.count_d1_reg[8]_0 )); LUT4 #( .INIT(16'h9009)) \gmux.gm[0].gm1.m1_i_1__1 (.I0(Q[0]), .I1(RD_PNTR_WR[0]), .I2(Q[1]), .I3(RD_PNTR_WR[1]), .O(v1_reg[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[0].gm1.m1_i_1__2 (.I0(wr_pntr_plus2[0]), .I1(RD_PNTR_WR[0]), .I2(wr_pntr_plus2[1]), .I3(RD_PNTR_WR[1]), .O(v1_reg_0[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__1 (.I0(Q[2]), .I1(RD_PNTR_WR[2]), .I2(Q[3]), .I3(RD_PNTR_WR[3]), .O(v1_reg[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__2 (.I0(wr_pntr_plus2[2]), .I1(RD_PNTR_WR[2]), .I2(wr_pntr_plus2[3]), .I3(RD_PNTR_WR[3]), .O(v1_reg_0[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__1 (.I0(Q[4]), .I1(RD_PNTR_WR[4]), .I2(Q[5]), .I3(RD_PNTR_WR[5]), .O(v1_reg[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__2 (.I0(wr_pntr_plus2[4]), .I1(RD_PNTR_WR[4]), .I2(wr_pntr_plus2[5]), .I3(RD_PNTR_WR[5]), .O(v1_reg_0[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__1 (.I0(Q[6]), .I1(RD_PNTR_WR[6]), .I2(Q[7]), .I3(RD_PNTR_WR[7]), .O(v1_reg[3])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__2 (.I0(wr_pntr_plus2[6]), .I1(RD_PNTR_WR[6]), .I2(wr_pntr_plus2[7]), .I3(RD_PNTR_WR[7]), .O(v1_reg_0[3])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_1 (.I0(Q[7]), .I1(RD_PNTR_WR[7]), .O(\gdiff.diff_pntr_pad_reg[8] [3])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_2 (.I0(Q[6]), .I1(RD_PNTR_WR[6]), .O(\gdiff.diff_pntr_pad_reg[8] [2])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_3 (.I0(Q[5]), .I1(RD_PNTR_WR[5]), .O(\gdiff.diff_pntr_pad_reg[8] [1])); LUT2 #( .INIT(4'h9)) plusOp_carry__0_i_4 (.I0(Q[4]), .I1(RD_PNTR_WR[4]), .O(\gdiff.diff_pntr_pad_reg[8] [0])); LUT2 #( .INIT(4'h9)) plusOp_carry__1_i_1 (.I0(Q[8]), .I1(RD_PNTR_WR[8]), .O(\gdiff.diff_pntr_pad_reg[9] )); LUT2 #( .INIT(4'h9)) plusOp_carry_i_1 (.I0(Q[3]), .I1(RD_PNTR_WR[3]), .O(S[3])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_2 (.I0(Q[2]), .I1(RD_PNTR_WR[2]), .O(S[2])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_3 (.I0(Q[1]), .I1(RD_PNTR_WR[1]), .O(S[1])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_4 (.I0(Q[0]), .I1(RD_PNTR_WR[0]), .O(S[0])); endmodule (* ORIG_REF_NAME = "wr_logic" *) module fb_output_fifo_wr_logic (full, prog_full, Q, WEBWE, \gic0.gc0.count_d1_reg[8] , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , \gnxpm_cdc.rd_pntr_bin_reg[10] , \gnxpm_cdc.rd_pntr_bin_reg[10]_0 , wr_clk, out, RD_PNTR_WR, wr_en, \grstd1.grst_full.grst_f.rst_d3_reg , AR); output full; output prog_full; output [0:0]Q; output [0:0]WEBWE; output [0:0]\gic0.gc0.count_d1_reg[8] ; output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; input \gnxpm_cdc.rd_pntr_bin_reg[10] ; input \gnxpm_cdc.rd_pntr_bin_reg[10]_0 ; input wr_clk; input out; input [8:0]RD_PNTR_WR; input wr_en; input \grstd1.grst_full.grst_f.rst_d3_reg ; input [0:0]AR; wire [0:0]AR; wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]Q; wire [8:0]RD_PNTR_WR; wire [0:0]WEBWE; wire [3:0]\c1/v1_reg ; wire [3:0]\c2/v1_reg ; wire full; wire [0:0]\gic0.gc0.count_d1_reg[8] ; wire \gnxpm_cdc.rd_pntr_bin_reg[10] ; wire \gnxpm_cdc.rd_pntr_bin_reg[10]_0 ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire \gwas.wsts_n_1 ; wire out; wire [7:0]p_13_out; wire prog_full; wire wpntr_n_0; wire wpntr_n_1; wire wpntr_n_13; wire wpntr_n_14; wire wpntr_n_15; wire wpntr_n_16; wire wpntr_n_17; wire wpntr_n_2; wire wpntr_n_3; wire wr_clk; wire wr_en; fb_output_fifo_wr_pf_as \gwas.gpf.wrpf (.AR(AR), .E(WEBWE), .Q(p_13_out), .S({wpntr_n_0,wpntr_n_1,wpntr_n_2,wpntr_n_3}), .\gic0.gc0.count_d1_reg[7] ({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}), .\gic0.gc0.count_d1_reg[8] (wpntr_n_17), .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), .out(out), .prog_full(prog_full), .ram_full_fb_i_reg(\gwas.wsts_n_1 ), .wr_clk(wr_clk)); fb_output_fifo_wr_status_flags_as \gwas.wsts (.E(WEBWE), .full(full), .\gnxpm_cdc.rd_pntr_bin_reg[10] (\gnxpm_cdc.rd_pntr_bin_reg[10] ), .\gnxpm_cdc.rd_pntr_bin_reg[10]_0 (\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ), .\grstd1.grst_full.grst_f.rst_d2_reg (out), .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), .out(\gwas.wsts_n_1 ), .v1_reg(\c1/v1_reg ), .v1_reg_0(\c2/v1_reg ), .wr_clk(wr_clk), .wr_en(wr_en)); fb_output_fifo_wr_bin_cntr wpntr (.AR(AR), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), .E(WEBWE), .Q({Q,p_13_out}), .RD_PNTR_WR(RD_PNTR_WR), .S({wpntr_n_0,wpntr_n_1,wpntr_n_2,wpntr_n_3}), .\gdiff.diff_pntr_pad_reg[8] ({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}), .\gdiff.diff_pntr_pad_reg[9] (wpntr_n_17), .\gic0.gc0.count_d1_reg[8]_0 (\gic0.gc0.count_d1_reg[8] ), .v1_reg(\c1/v1_reg ), .v1_reg_0(\c2/v1_reg ), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "wr_pf_as" *) module fb_output_fifo_wr_pf_as (prog_full, wr_clk, out, E, Q, S, \gic0.gc0.count_d1_reg[7] , \gic0.gc0.count_d1_reg[8] , \grstd1.grst_full.grst_f.rst_d3_reg , ram_full_fb_i_reg, AR); output prog_full; input wr_clk; input out; input [0:0]E; input [7:0]Q; input [3:0]S; input [3:0]\gic0.gc0.count_d1_reg[7] ; input [0:0]\gic0.gc0.count_d1_reg[8] ; input \grstd1.grst_full.grst_f.rst_d3_reg ; input ram_full_fb_i_reg; input [0:0]AR; wire [0:0]AR; wire [0:0]E; wire [7:0]Q; wire [3:0]S; wire [8:4]diff_pntr; wire [3:0]\gic0.gc0.count_d1_reg[7] ; wire [0:0]\gic0.gc0.count_d1_reg[8] ; wire \gpf1.prog_full_i_i_1_n_0 ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire out; wire [9:5]plusOp; wire plusOp_carry__0_n_0; wire plusOp_carry__0_n_1; wire plusOp_carry__0_n_2; wire plusOp_carry__0_n_3; wire plusOp_carry_n_0; wire plusOp_carry_n_1; wire plusOp_carry_n_2; wire plusOp_carry_n_3; wire prog_full; wire prog_full_i; wire ram_full_fb_i_reg; wire wr_clk; wire [3:0]NLW_plusOp_carry_O_UNCONNECTED; wire [3:0]NLW_plusOp_carry__1_CO_UNCONNECTED; wire [3:1]NLW_plusOp_carry__1_O_UNCONNECTED; FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(plusOp[5]), .Q(diff_pntr[4])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[6] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(plusOp[6]), .Q(diff_pntr[5])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[7] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(plusOp[7]), .Q(diff_pntr[6])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[8] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(plusOp[8]), .Q(diff_pntr[7])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[9] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(plusOp[9]), .Q(diff_pntr[8])); LUT4 #( .INIT(16'hBA8A)) \gpf1.prog_full_i_i_1 (.I0(prog_full_i), .I1(\grstd1.grst_full.grst_f.rst_d3_reg ), .I2(ram_full_fb_i_reg), .I3(prog_full), .O(\gpf1.prog_full_i_i_1_n_0 )); LUT6 #( .INIT(64'h2000000000000000)) \gpf1.prog_full_i_i_2 (.I0(diff_pntr[7]), .I1(\grstd1.grst_full.grst_f.rst_d3_reg ), .I2(diff_pntr[4]), .I3(diff_pntr[8]), .I4(diff_pntr[6]), .I5(diff_pntr[5]), .O(prog_full_i)); FDPE #( .INIT(1'b1)) \gpf1.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gpf1.prog_full_i_i_1_n_0 ), .PRE(out), .Q(prog_full)); CARRY4 plusOp_carry (.CI(1'b0), .CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}), .CYINIT(E), .DI(Q[3:0]), .O(NLW_plusOp_carry_O_UNCONNECTED[3:0]), .S(S)); CARRY4 plusOp_carry__0 (.CI(plusOp_carry_n_0), .CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}), .CYINIT(1'b0), .DI(Q[7:4]), .O(plusOp[8:5]), .S(\gic0.gc0.count_d1_reg[7] )); CARRY4 plusOp_carry__1 (.CI(plusOp_carry__0_n_0), .CO(NLW_plusOp_carry__1_CO_UNCONNECTED[3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_plusOp_carry__1_O_UNCONNECTED[3:1],plusOp[9]}), .S({1'b0,1'b0,1'b0,\gic0.gc0.count_d1_reg[8] })); endmodule (* ORIG_REF_NAME = "wr_status_flags_as" *) module fb_output_fifo_wr_status_flags_as (full, out, E, v1_reg, \gnxpm_cdc.rd_pntr_bin_reg[10] , v1_reg_0, \gnxpm_cdc.rd_pntr_bin_reg[10]_0 , wr_clk, \grstd1.grst_full.grst_f.rst_d2_reg , wr_en, \grstd1.grst_full.grst_f.rst_d3_reg ); output full; output out; output [0:0]E; input [3:0]v1_reg; input \gnxpm_cdc.rd_pntr_bin_reg[10] ; input [3:0]v1_reg_0; input \gnxpm_cdc.rd_pntr_bin_reg[10]_0 ; input wr_clk; input \grstd1.grst_full.grst_f.rst_d2_reg ; input wr_en; input \grstd1.grst_full.grst_f.rst_d3_reg ; wire [0:0]E; wire c2_n_0; wire comp1; wire \gnxpm_cdc.rd_pntr_bin_reg[10] ; wire \gnxpm_cdc.rd_pntr_bin_reg[10]_0 ; wire \grstd1.grst_full.grst_f.rst_d2_reg ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; (* DONT_TOUCH *) wire ram_full_fb_i; (* DONT_TOUCH *) wire ram_full_i; wire [3:0]v1_reg; wire [3:0]v1_reg_0; wire wr_clk; wire wr_en; assign full = ram_full_i; assign out = ram_full_fb_i; LUT2 #( .INIT(4'h2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2 (.I0(wr_en), .I1(ram_full_fb_i), .O(E)); fb_output_fifo_compare__parameterized0 c1 (.comp1(comp1), .\gnxpm_cdc.rd_pntr_bin_reg[10] (\gnxpm_cdc.rd_pntr_bin_reg[10] ), .v1_reg(v1_reg)); fb_output_fifo_compare__parameterized1 c2 (.comp1(comp1), .\gnxpm_cdc.rd_pntr_bin_reg[10] (\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ), .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), .out(ram_full_fb_i), .ram_full_fb_i_reg(c2_n_0), .v1_reg_0(v1_reg_0), .wr_en(wr_en)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_fb_i_reg (.C(wr_clk), .CE(1'b1), .D(c2_n_0), .PRE(\grstd1.grst_full.grst_f.rst_d2_reg ), .Q(ram_full_fb_i)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(c2_n_0), .PRE(\grstd1.grst_full.grst_f.rst_d2_reg ), .Q(ram_full_i)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest_vlog.prj ================================================ # compile verilog/system verilog design source files verilog xil_defaultlib "genesys2_fbtest_func_synth.v" --include "../../../../framebuffer_test.srcs/sources_1/ip/dvi_pll" --include "../../../../framebuffer_test.srcs/sources_1/ip/camera_pll" # Do not sort compile order nosort ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc ================================================ ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com ## Sat Nov 12 10:25:17 2016 ## Generated by MIG Version 4.0 ## ################################################################################################## ## File name : ddr3_if.xdc ## Details : Constraints file ## FPGA Family: KINTEX7 ## FPGA Part: XC7K325T-FFG900 ## Speedgrade: -2 ## Design Entry: VERILOG ## Frequency: 0 MHz ## Time Period: 1112 ps ################################################################################################## ################################################################################################## ## Controller 0 ## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107 ## Data Width: 32 ## Time Period: 1112 ## Data Mask: 1 ################################################################################################## #create_clock -period 5.004 [get_ports sys_clk_i] ############## NET - IOSTANDARD ################## # PadFunction: IO_L1N_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[0]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}] set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}] # PadFunction: IO_L2P_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[1]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}] set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}] # PadFunction: IO_L2N_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[2]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}] set_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}] # PadFunction: IO_L4P_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[3]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}] set_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}] # PadFunction: IO_L4N_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[4]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}] set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}] # PadFunction: IO_L5P_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[5]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}] set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}] # PadFunction: IO_L5N_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[6]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}] set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}] # PadFunction: IO_L6P_T0_34 set_property SLEW FAST [get_ports {ddr3_dq[7]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}] set_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}] # PadFunction: IO_L7N_T1_34 set_property SLEW FAST [get_ports {ddr3_dq[8]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}] set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}] # PadFunction: IO_L8P_T1_34 set_property SLEW FAST [get_ports {ddr3_dq[9]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}] set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}] # PadFunction: IO_L8N_T1_34 set_property SLEW FAST [get_ports {ddr3_dq[10]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}] set_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}] # PadFunction: IO_L10P_T1_34 set_property SLEW FAST [get_ports {ddr3_dq[11]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}] set_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}] # PadFunction: IO_L10N_T1_34 set_property SLEW FAST [get_ports {ddr3_dq[12]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}] set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}] # PadFunction: IO_L11P_T1_SRCC_34 set_property SLEW FAST [get_ports {ddr3_dq[13]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}] set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}] # PadFunction: IO_L11N_T1_SRCC_34 set_property SLEW FAST [get_ports {ddr3_dq[14]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}] set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}] # PadFunction: IO_L12P_T1_MRCC_34 set_property SLEW FAST [get_ports {ddr3_dq[15]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}] set_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}] # PadFunction: IO_L13N_T2_MRCC_34 set_property SLEW FAST [get_ports {ddr3_dq[16]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}] set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}] # PadFunction: IO_L14P_T2_SRCC_34 set_property SLEW FAST [get_ports {ddr3_dq[17]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}] set_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}] # PadFunction: IO_L14N_T2_SRCC_34 set_property SLEW FAST [get_ports {ddr3_dq[18]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}] set_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}] # PadFunction: IO_L16P_T2_34 set_property SLEW FAST [get_ports {ddr3_dq[19]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}] set_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}] # PadFunction: IO_L16N_T2_34 set_property SLEW FAST [get_ports {ddr3_dq[20]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}] set_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}] # PadFunction: IO_L17P_T2_34 set_property SLEW FAST [get_ports {ddr3_dq[21]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}] set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}] # PadFunction: IO_L17N_T2_34 set_property SLEW FAST [get_ports {ddr3_dq[22]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}] set_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}] # PadFunction: IO_L18P_T2_34 set_property SLEW FAST [get_ports {ddr3_dq[23]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}] set_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}] # PadFunction: IO_L20P_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[24]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}] set_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}] # PadFunction: IO_L20N_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[25]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}] set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}] # PadFunction: IO_L22P_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[26]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}] set_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}] # PadFunction: IO_L22N_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[27]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}] set_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}] # PadFunction: IO_L23P_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[28]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}] set_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}] # PadFunction: IO_L23N_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[29]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}] set_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}] # PadFunction: IO_L24P_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[30]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}] set_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}] # PadFunction: IO_L24N_T3_34 set_property SLEW FAST [get_ports {ddr3_dq[31]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}] set_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}] # PadFunction: IO_L16N_T2_33 set_property SLEW FAST [get_ports {ddr3_addr[14]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] set_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}] # PadFunction: IO_L1P_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[13]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] set_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}] # PadFunction: IO_L1N_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[12]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] set_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}] # PadFunction: IO_L2P_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[11]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}] # PadFunction: IO_L2N_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[10]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] set_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}] # PadFunction: IO_L4P_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[9]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] set_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}] # PadFunction: IO_L4N_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[8]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}] # PadFunction: IO_L5P_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[7]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] set_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}] # PadFunction: IO_L5N_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[6]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}] # PadFunction: IO_L6P_T0_33 set_property SLEW FAST [get_ports {ddr3_addr[5]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] set_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}] # PadFunction: IO_L10P_T1_33 set_property SLEW FAST [get_ports {ddr3_addr[4]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] set_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}] # PadFunction: IO_L7N_T1_33 set_property SLEW FAST [get_ports {ddr3_addr[3]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] set_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}] # PadFunction: IO_L8P_T1_33 set_property SLEW FAST [get_ports {ddr3_addr[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}] # PadFunction: IO_L8N_T1_33 set_property SLEW FAST [get_ports {ddr3_addr[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}] # PadFunction: IO_L9P_T1_DQS_33 set_property SLEW FAST [get_ports {ddr3_addr[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] set_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}] # PadFunction: IO_L9N_T1_DQS_33 set_property SLEW FAST [get_ports {ddr3_ba[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] set_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}] # PadFunction: IO_L7P_T1_33 set_property SLEW FAST [get_ports {ddr3_ba[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] set_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}] # PadFunction: IO_L10N_T1_33 set_property SLEW FAST [get_ports {ddr3_ba[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] set_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}] # PadFunction: IO_L11P_T1_SRCC_33 set_property SLEW FAST [get_ports ddr3_ras_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n] set_property PACKAGE_PIN AE11 [get_ports ddr3_ras_n] # PadFunction: IO_L11N_T1_SRCC_33 set_property SLEW FAST [get_ports ddr3_cas_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n] set_property PACKAGE_PIN AF11 [get_ports ddr3_cas_n] # PadFunction: IO_L24P_T3_33 set_property SLEW FAST [get_ports ddr3_we_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n] set_property PACKAGE_PIN AG13 [get_ports ddr3_we_n] # PadFunction: IO_L12N_T1_MRCC_34 set_property SLEW FAST [get_ports ddr3_reset_n] set_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n] set_property PACKAGE_PIN AG5 [get_ports ddr3_reset_n] # PadFunction: IO_L15P_T2_DQS_33 set_property SLEW FAST [get_ports {ddr3_cke[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] set_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}] # PadFunction: IO_L15N_T2_DQS_33 set_property SLEW FAST [get_ports {ddr3_odt[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] set_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}] # PadFunction: IO_L24N_T3_33 set_property SLEW FAST [get_ports {ddr3_cs_n[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}] set_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}] # PadFunction: IO_L1P_T0_34 set_property SLEW FAST [get_ports {ddr3_dm[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}] # PadFunction: IO_L7P_T1_34 set_property SLEW FAST [get_ports {ddr3_dm[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] set_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}] # PadFunction: IO_L13P_T2_MRCC_34 set_property SLEW FAST [get_ports {ddr3_dm[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}] set_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}] # PadFunction: IO_L19P_T3_34 set_property SLEW FAST [get_ports {ddr3_dm[3]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}] set_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}] # PadFunction: IO_L3P_T0_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}] # PadFunction: IO_L3N_T0_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}] set_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}] set_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}] # PadFunction: IO_L9P_T1_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}] # PadFunction: IO_L9N_T1_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}] set_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}] set_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}] # PadFunction: IO_L15P_T2_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}] # PadFunction: IO_L15N_T2_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}] set_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}] set_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}] # PadFunction: IO_L21P_T3_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}] # PadFunction: IO_L21N_T3_DQS_34 set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}] set_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}] set_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}] # PadFunction: IO_L3P_T0_DQS_33 set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] # PadFunction: IO_L3N_T0_DQS_33 set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] set_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}] set_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}] set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] ## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] ## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] ## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] ## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}] set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}] set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] set_multicycle_path -setup -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 6 set_multicycle_path -hold -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 5 set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] set_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2 set_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1 set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000 set_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000 set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc ================================================ set_property PACKAGE_PIN AA20 [get_ports {hdmi_clk[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_clk[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_clk[0]}] set_property PACKAGE_PIN AC20 [get_ports {hdmi_d0[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d0[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d0[0]}] set_property PACKAGE_PIN AA22 [get_ports {hdmi_d1[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d1[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d1[0]}] set_property PACKAGE_PIN AB24 [get_ports {hdmi_d2[1]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d2[0]}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d2[1]}] set_property PACKAGE_PIN R19 [get_ports reset_n] set_property IOSTANDARD LVCMOS33 [get_ports reset_n] set_property PACKAGE_PIN AD12 [get_ports clock_p] set_property IOSTANDARD DIFF_SSTL15 [get_ports clock_p] create_clock -period 5.000 -waveform {0.000 2.500} [get_ports clock_p] create_clock -period 5.000 -waveform {2.500 5.000} [get_ports clock_n] set_property PACKAGE_PIN P27 [get_ports zoom_mode] set_property IOSTANDARD LVCMOS33 [get_ports zoom_mode] set_property PACKAGE_PIN P26 [get_ports freeze] set_property IOSTANDARD LVCMOS33 [get_ports freeze] set_property PACKAGE_PIN D26 [get_ports {csi0_clk[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_clk[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_clk[0]}] set_property PACKAGE_PIN B30 [get_ports {csi0_d1[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d1[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d1[0]}] set_property PACKAGE_PIN B28 [get_ports {csi0_d3[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d3[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d3[0]}] set_property PACKAGE_PIN D29 [get_ports {csi0_d0[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d0[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d0[0]}] set_property PACKAGE_PIN B27 [get_ports {csi0_d2[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d2[1]}] set_property IOSTANDARD LVDS_25 [get_ports {csi0_d2[0]}] set_property PACKAGE_PIN M28 [get_ports cam_mclk] set_property IOSTANDARD LVCMOS25 [get_ports cam_mclk] set_property PACKAGE_PIN L28 [get_ports cam_i2c_sck] set_property IOSTANDARD LVCMOS25 [get_ports cam_i2c_sck] set_property PACKAGE_PIN J29 [get_ports cam_i2c_sda] set_property IOSTANDARD LVCMOS25 [get_ports cam_i2c_sda] set_property PACKAGE_PIN N21 [get_ports cam_rstn] set_property IOSTANDARD LVCMOS25 [get_ports cam_rstn] create_clock -period 2.500 -name csi -waveform {0.000 1.250} [get_ports {csi0_clk[1]}] create_clock -period 2.500 -name csi2 -waveform {1.250 2.500} [get_ports {csi0_clk[0]}] set_input_delay -clock [get_clocks csi] 1.000 [get_ports {{csi0_d0[0]} {csi0_d0[1]} {csi0_d1[0]} {csi0_d1[1]} {csi0_d2[0]} {csi0_d2[1]} {csi0_d3[0]} {csi0_d3[1]}}] set_input_delay -clock [get_clocks csi] -clock_fall 1.000 [get_ports {{csi0_d0[0]} {csi0_d0[1]} {csi0_d1[0]} {csi0_d1[1]} {csi0_d2[0]} {csi0_d2[1]} {csi0_d3[0]} {csi0_d3[1]}}] set_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}] set_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] -clock_fall 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}] set_property PACKAGE_PIN AH20 [get_ports {vga_b[0]}] set_property PACKAGE_PIN AG20 [get_ports {vga_b[1]}] set_property PACKAGE_PIN AF21 [get_ports {vga_b[2]}] set_property PACKAGE_PIN AK20 [get_ports {vga_b[3]}] set_property PACKAGE_PIN AG22 [get_ports {vga_b[4]}] set_property PACKAGE_PIN AJ23 [get_ports {vga_g[0]}] set_property PACKAGE_PIN AJ22 [get_ports {vga_g[1]}] set_property PACKAGE_PIN AH22 [get_ports {vga_g[2]}] set_property PACKAGE_PIN AK21 [get_ports {vga_g[3]}] set_property PACKAGE_PIN AJ21 [get_ports {vga_g[4]}] set_property PACKAGE_PIN AK23 [get_ports {vga_g[5]}] set_property PACKAGE_PIN AF20 [get_ports vga_hsync] set_property PACKAGE_PIN AK25 [get_ports {vga_r[0]}] set_property PACKAGE_PIN AG25 [get_ports {vga_r[1]}] set_property PACKAGE_PIN AH25 [get_ports {vga_r[2]}] set_property PACKAGE_PIN AK24 [get_ports {vga_r[3]}] set_property PACKAGE_PIN AJ24 [get_ports {vga_r[4]}] set_property PACKAGE_PIN AG23 [get_ports vga_vsync] set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[5]}] set_property IOSTANDARD LVCMOS33 [get_ports vga_hsync] set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[4]}] set_property IOSTANDARD LVCMOS33 [get_ports vga_vsync] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.v ================================================ // file: camera_pll.v // // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //---------------------------------------------------------------------------- // User entered comments //---------------------------------------------------------------------------- // None // //---------------------------------------------------------------------------- // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // camera_pixel_clock___145.000______0.000______50.0______280.569____321.802 // camera_mclk____24.399______0.000______50.0______391.507____321.802 // i2c_clkin_____4.995______0.000______50.0______519.540____321.802 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) //---------------------------------------------------------------------------- // __primary_____________200____________0.010 `timescale 1ps/1ps (* CORE_GENERATION_INFO = "camera_pll,clk_wiz_v5_3_2_0,{component_name=camera_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) module camera_pll ( // Clock out ports output camera_pixel_clock, output camera_mclk, output i2c_clkin, // Clock in ports input sysclk ); camera_pll_clk_wiz inst ( // Clock out ports .camera_pixel_clock(camera_pixel_clock), .camera_mclk(camera_mclk), .i2c_clkin(i2c_clkin), // Clock in ports .sysclk(sysclk) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci ================================================ xilinx.com xci unknown 1.0 camera_pll MMCM cddcdone cddcreq 0000 3800 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 100.0 1041 3c00 145.000 134d 0000 24.399 BUFG 50.0 false 145.000 0.000 50.000 145 0.000 1 1fc0 0080 4.995 BUFG 50.0 false 24.399 0.000 50.000 24.4 0.000 1 1 1041 00c0 100.000 BUFG 50.0 false 4.995 0.000 50.000 5 0.000 1 1 1041 00c0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 1041 0cc0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 1041 28c0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO clk_in_sel camera_pixel_clock camera_mclk i2c_clkin clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0104 1 5.942622950819673 29.0 1.45 1.45 1.45 1.45 dout drdy dwe 0 0 0 0 0 0 0 0 FDBK_AUTO 0800 0190 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_____________200____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0190 7c01 7fe9 false false false false false false false false OPTIMIZED 25.375 0.000 FALSE 5.0 10.0 4.375 0.500 0.000 FALSE 26 0.500 0.000 FALSE 127 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE ZHOLD 8 None 0.010 0.010 FALSE 3 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) camera_pixel_clock___145.000______0.000______50.0______280.569____321.802 camera_mclk____24.399______0.000______50.0______391.507____321.802 i2c_clkin_____4.995______0.000______50.0______519.540____321.802 no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 0 0 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down FFFF 1 sysclk MMCM AUTO 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 camera_pll MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 0.010 100.0 0.010 BUFG 280.569 false 321.802 50.000 145 0.000 1 true BUFG 391.507 false 321.802 50.000 24.4 0.000 1 true BUFG 519.540 false 321.802 50.000 5 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel camera_pixel_clock false camera_mclk false i2c_clkin false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto camera_pll daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 25.375 0.000 false 5.0 10.0 4.375 0.500 0.000 false 26 0.500 0.000 false 127 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 8 None 0.010 0.010 false 3 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 sysclk MMCM mmcm_adv 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false false false false false true false false false false false kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 2 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc ================================================ # file: camera_pll.xdc # # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and # international copyright and other intellectual property # laws. # # DISCLAIMER # This disclaimer is not a license and does not grant any # rights to the materials distributed herewith. Except as # otherwise provided in a valid license issued to you by # Xilinx, and to the maximum extent permitted by applicable # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and # (2) Xilinx shall not be liable (whether in contract or tort, # including negligence, or under any other theory of # liability) for any loss or damage of any kind or nature # related to, arising under or in connection with these # materials, including for any direct, or any indirect, # special, incidental, or consequential loss or damage # (including loss of data, profits, goodwill, or any type of # loss or damage suffered as a result of any action brought # by a third party) even if such damage or loss was # reasonably foreseeable or Xilinx had been advised of the # possibility of the same. # # CRITICAL APPLICATIONS # Xilinx products are not designed or intended to be fail- # safe, or for use in any application requiring fail-safe # performance, such as life-support or safety devices or # systems, Class III medical devices, nuclear facilities, # applications related to the deployment of airbags, or any # other applications that could lead to death, personal # injury, or severe property or environmental damage # (individually and collectively, "Critical # Applications"). Customer assumes the sole risk and # liability of any use of Xilinx products in Critical # Applications, subject only to applicable laws and # regulations governing limitations on product liability. # # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS # PART OF THIS FILE AT ALL TIMES. # # Input clock periods. These duplicate the values entered for the # input clocks. You can use these to time your system. If required # commented constraints can be used in the top level xdc #---------------------------------------------------------------- #create_clock -period 5.0 [get_ports sysclk] #set_input_jitter [get_clocks -of_objects [get_ports sysclk]] 0.05 set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc ================================================ #--------------------Physical Constraints----------------- ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_clk_wiz.v ================================================ // file: camera_pll.v // // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //---------------------------------------------------------------------------- // User entered comments //---------------------------------------------------------------------------- // None // //---------------------------------------------------------------------------- // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // camera_pixel_clock___145.000______0.000______50.0______280.569____321.802 // camera_mclk____24.399______0.000______50.0______391.507____321.802 // i2c_clkin_____4.995______0.000______50.0______519.540____321.802 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) //---------------------------------------------------------------------------- // __primary_____________200____________0.010 `timescale 1ps/1ps module camera_pll_clk_wiz (// Clock in ports // Clock out ports output camera_pixel_clock, output camera_mclk, output i2c_clkin, input sysclk ); // Input buffering //------------------------------------ wire sysclk_camera_pll; wire clk_in2_camera_pll; BUFG clkin1_bufg (.O (sysclk_camera_pll), .I (sysclk)); // Clocking PRIMITIVE //------------------------------------ // Instantiation of the MMCM PRIMITIVE // * Unused inputs are tied off // * Unused outputs are labeled unused wire camera_pixel_clock_camera_pll; wire camera_mclk_camera_pll; wire i2c_clkin_camera_pll; wire clk_out4_camera_pll; wire clk_out5_camera_pll; wire clk_out6_camera_pll; wire clk_out7_camera_pll; wire [15:0] do_unused; wire drdy_unused; wire psdone_unused; wire locked_int; wire clkfbout_camera_pll; wire clkfbout_buf_camera_pll; wire clkfboutb_unused; wire clkout0b_unused; wire clkout1b_unused; wire clkout2b_unused; wire clkout3_unused; wire clkout3b_unused; wire clkout4_unused; wire clkout5_unused; wire clkout6_unused; wire clkfbstopped_unused; wire clkinstopped_unused; MMCME2_ADV #(.BANDWIDTH ("OPTIMIZED"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("ZHOLD"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (8), .CLKFBOUT_MULT_F (25.375), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (4.375), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (26), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (127), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (5.0)) mmcm_adv_inst // Output clocks ( .CLKFBOUT (clkfbout_camera_pll), .CLKFBOUTB (clkfboutb_unused), .CLKOUT0 (camera_pixel_clock_camera_pll), .CLKOUT0B (clkout0b_unused), .CLKOUT1 (camera_mclk_camera_pll), .CLKOUT1B (clkout1b_unused), .CLKOUT2 (i2c_clkin_camera_pll), .CLKOUT2B (clkout2b_unused), .CLKOUT3 (clkout3_unused), .CLKOUT3B (clkout3b_unused), .CLKOUT4 (clkout4_unused), .CLKOUT5 (clkout5_unused), .CLKOUT6 (clkout6_unused), // Input clock control .CLKFBIN (clkfbout_buf_camera_pll), .CLKIN1 (sysclk_camera_pll), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (do_unused), .DRDY (drdy_unused), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (psdone_unused), // Other control and status signals .LOCKED (locked_int), .CLKINSTOPPED (clkinstopped_unused), .CLKFBSTOPPED (clkfbstopped_unused), .PWRDWN (1'b0), .RST (1'b0)); // Clock Monitor clock assigning //-------------------------------------- // Output buffering //----------------------------------- BUFG clkf_buf (.O (clkfbout_buf_camera_pll), .I (clkfbout_camera_pll)); BUFG clkout1_buf (.O (camera_pixel_clock), .I (camera_pixel_clock_camera_pll)); BUFG clkout2_buf (.O (camera_mclk), .I (camera_mclk_camera_pll)); BUFG clkout3_buf (.O (i2c_clkin), .I (i2c_clkin_camera_pll)); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc ================================================ # file: camera_pll_ooc.xdc # # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and # international copyright and other intellectual property # laws. # # DISCLAIMER # This disclaimer is not a license and does not grant any # rights to the materials distributed herewith. Except as # otherwise provided in a valid license issued to you by # Xilinx, and to the maximum extent permitted by applicable # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and # (2) Xilinx shall not be liable (whether in contract or tort, # including negligence, or under any other theory of # liability) for any loss or damage of any kind or nature # related to, arising under or in connection with these # materials, including for any direct, or any indirect, # special, incidental, or consequential loss or damage # (including loss of data, profits, goodwill, or any type of # loss or damage suffered as a result of any action brought # by a third party) even if such damage or loss was # reasonably foreseeable or Xilinx had been advised of the # possibility of the same. # # CRITICAL APPLICATIONS # Xilinx products are not designed or intended to be fail- # safe, or for use in any application requiring fail-safe # performance, such as life-support or safety devices or # systems, Class III medical devices, nuclear facilities, # applications related to the deployment of airbags, or any # other applications that could lead to death, personal # injury, or severe property or environmental damage # (individually and collectively, "Critical # Applications"). Customer assumes the sole risk and # liability of any use of Xilinx products in Critical # Applications, subject only to applicable laws and # regulations governing limitations on product liability. # # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS # PART OF THIS FILE AT ALL TIMES. # ################# #DEFAULT CLOCK CONSTRAINTS ############################################################ # Clock Period Constraints # ############################################################ create_clock -period 5.0 [get_ports sysclk] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 14:32:35 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top camera_pll -prefix // camera_pll_ camera_pll_sim_netlist.v // Design : camera_pll // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module camera_pll (camera_pixel_clock, camera_mclk, i2c_clkin, sysclk); output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; wire camera_mclk; wire camera_pixel_clock; wire i2c_clkin; wire sysclk; camera_pll_camera_pll_clk_wiz inst (.camera_mclk(camera_mclk), .camera_pixel_clock(camera_pixel_clock), .i2c_clkin(i2c_clkin), .sysclk(sysclk)); endmodule module camera_pll_camera_pll_clk_wiz (camera_pixel_clock, camera_mclk, i2c_clkin, sysclk); output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; wire camera_mclk; wire camera_mclk_camera_pll; wire camera_pixel_clock; wire camera_pixel_clock_camera_pll; wire clkfbout_buf_camera_pll; wire clkfbout_camera_pll; wire i2c_clkin; wire i2c_clkin_camera_pll; wire sysclk; wire sysclk_camera_pll; wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED; wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_camera_pll), .O(clkfbout_buf_camera_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_camera_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout1_buf (.I(camera_pixel_clock_camera_pll), .O(camera_pixel_clock)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout2_buf (.I(camera_mclk_camera_pll), .O(camera_mclk)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout3_buf (.I(i2c_clkin_camera_pll), .O(i2c_clkin)); (* BOX_TYPE = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT_F(25.375000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(4.375000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), .CLKOUT1_DIVIDE(26), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(127), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(8), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) mmcm_adv_inst (.CLKFBIN(clkfbout_buf_camera_pll), .CLKFBOUT(clkfbout_camera_pll), .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), .CLKIN1(sysclk_camera_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), .CLKOUT0(camera_pixel_clock_camera_pll), .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), .CLKOUT1(camera_mclk_camera_pll), .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), .CLKOUT2(i2c_clkin_camera_pll), .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED), .PSCLK(1'b0), .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), .PSEN(1'b0), .PSINCDEC(1'b0), .PWRDWN(1'b0), .RST(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 14:32:35 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top camera_pll -prefix // camera_pll_ camera_pll_stub.v // Design : camera_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module camera_pll(camera_pixel_clock, camera_mclk, i2c_clkin, sysclk) /* synthesis syn_black_box black_box_pad_pin="camera_pixel_clock,camera_mclk,i2c_clkin,sysclk" */; output camera_pixel_clock; output camera_mclk; output i2c_clkin; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1250 2.0V 4:1 200 0 800 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 11 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 8 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if/mig_b.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1875 1.8V 4:1 200 0 1066 1.000 1 1 1 1 32 1 1 Disabled Normal 2 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 7 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 6 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/constraints/ddr3_if.xdc ================================================ ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com ## Tue Nov 15 09:39:56 2016 ## Generated by MIG Version 4.0 ## ################################################################################################## ## File name : ddr3_if.xdc ## Details : Constraints file ## FPGA Family: KINTEX7 ## FPGA Part: XC7K325T-FFG900 ## Speedgrade: -2 ## Design Entry: VERILOG ## Frequency: 0 MHz ## Time Period: 1112 ps ################################################################################################## ################################################################################################## ## Controller 0 ## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107 ## Data Width: 32 ## Time Period: 1112 ## Data Mask: 1 ################################################################################################## #create_clock -period 5.004 [get_ports sys_clk_i] ############## NET - IOSTANDARD ################## # PadFunction: IO_L1N_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}] set_property SLEW FAST [get_ports {ddr3_dq[0]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}] set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}] # PadFunction: IO_L2P_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}] set_property SLEW FAST [get_ports {ddr3_dq[1]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}] set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}] # PadFunction: IO_L2N_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}] set_property SLEW FAST [get_ports {ddr3_dq[2]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}] set_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}] # PadFunction: IO_L4P_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}] set_property SLEW FAST [get_ports {ddr3_dq[3]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}] set_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}] # PadFunction: IO_L4N_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}] set_property SLEW FAST [get_ports {ddr3_dq[4]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}] set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}] # PadFunction: IO_L5P_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}] set_property SLEW FAST [get_ports {ddr3_dq[5]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}] set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}] # PadFunction: IO_L5N_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}] set_property SLEW FAST [get_ports {ddr3_dq[6]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}] set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}] # PadFunction: IO_L6P_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}] set_property SLEW FAST [get_ports {ddr3_dq[7]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}] set_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}] # PadFunction: IO_L7N_T1_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}] set_property SLEW FAST [get_ports {ddr3_dq[8]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}] set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}] # PadFunction: IO_L8P_T1_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}] set_property SLEW FAST [get_ports {ddr3_dq[9]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}] set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}] # PadFunction: IO_L8N_T1_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}] set_property SLEW FAST [get_ports {ddr3_dq[10]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}] set_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}] # PadFunction: IO_L10P_T1_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}] set_property SLEW FAST [get_ports {ddr3_dq[11]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}] set_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}] # PadFunction: IO_L10N_T1_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}] set_property SLEW FAST [get_ports {ddr3_dq[12]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}] set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}] # PadFunction: IO_L11P_T1_SRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}] set_property SLEW FAST [get_ports {ddr3_dq[13]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}] set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}] # PadFunction: IO_L11N_T1_SRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}] set_property SLEW FAST [get_ports {ddr3_dq[14]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}] set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}] # PadFunction: IO_L12P_T1_MRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}] set_property SLEW FAST [get_ports {ddr3_dq[15]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}] set_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}] # PadFunction: IO_L13N_T2_MRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}] set_property SLEW FAST [get_ports {ddr3_dq[16]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}] set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}] # PadFunction: IO_L14P_T2_SRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}] set_property SLEW FAST [get_ports {ddr3_dq[17]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}] set_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}] # PadFunction: IO_L14N_T2_SRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}] set_property SLEW FAST [get_ports {ddr3_dq[18]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}] set_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}] # PadFunction: IO_L16P_T2_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}] set_property SLEW FAST [get_ports {ddr3_dq[19]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}] set_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}] # PadFunction: IO_L16N_T2_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}] set_property SLEW FAST [get_ports {ddr3_dq[20]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}] set_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}] # PadFunction: IO_L17P_T2_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}] set_property SLEW FAST [get_ports {ddr3_dq[21]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}] set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}] # PadFunction: IO_L17N_T2_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}] set_property SLEW FAST [get_ports {ddr3_dq[22]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}] set_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}] # PadFunction: IO_L18P_T2_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}] set_property SLEW FAST [get_ports {ddr3_dq[23]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}] set_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}] # PadFunction: IO_L20P_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}] set_property SLEW FAST [get_ports {ddr3_dq[24]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}] set_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}] # PadFunction: IO_L20N_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}] set_property SLEW FAST [get_ports {ddr3_dq[25]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}] set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}] # PadFunction: IO_L22P_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}] set_property SLEW FAST [get_ports {ddr3_dq[26]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}] set_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}] # PadFunction: IO_L22N_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}] set_property SLEW FAST [get_ports {ddr3_dq[27]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}] set_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}] # PadFunction: IO_L23P_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}] set_property SLEW FAST [get_ports {ddr3_dq[28]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}] set_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}] # PadFunction: IO_L23N_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}] set_property SLEW FAST [get_ports {ddr3_dq[29]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}] set_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}] # PadFunction: IO_L24P_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}] set_property SLEW FAST [get_ports {ddr3_dq[30]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}] set_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}] # PadFunction: IO_L24N_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}] set_property SLEW FAST [get_ports {ddr3_dq[31]}] set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}] set_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}] # PadFunction: IO_L16N_T2_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}] set_property SLEW FAST [get_ports {ddr3_addr[14]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] set_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}] # PadFunction: IO_L1P_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}] set_property SLEW FAST [get_ports {ddr3_addr[13]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] set_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}] # PadFunction: IO_L1N_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}] set_property SLEW FAST [get_ports {ddr3_addr[12]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] set_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}] # PadFunction: IO_L2P_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}] set_property SLEW FAST [get_ports {ddr3_addr[11]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}] # PadFunction: IO_L2N_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}] set_property SLEW FAST [get_ports {ddr3_addr[10]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] set_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}] # PadFunction: IO_L4P_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}] set_property SLEW FAST [get_ports {ddr3_addr[9]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] set_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}] # PadFunction: IO_L4N_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}] set_property SLEW FAST [get_ports {ddr3_addr[8]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}] # PadFunction: IO_L5P_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}] set_property SLEW FAST [get_ports {ddr3_addr[7]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] set_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}] # PadFunction: IO_L5N_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}] set_property SLEW FAST [get_ports {ddr3_addr[6]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}] # PadFunction: IO_L6P_T0_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}] set_property SLEW FAST [get_ports {ddr3_addr[5]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] set_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}] # PadFunction: IO_L10P_T1_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}] set_property SLEW FAST [get_ports {ddr3_addr[4]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] set_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}] # PadFunction: IO_L7N_T1_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}] set_property SLEW FAST [get_ports {ddr3_addr[3]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] set_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}] # PadFunction: IO_L8P_T1_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}] set_property SLEW FAST [get_ports {ddr3_addr[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}] # PadFunction: IO_L8N_T1_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}] set_property SLEW FAST [get_ports {ddr3_addr[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}] # PadFunction: IO_L9P_T1_DQS_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}] set_property SLEW FAST [get_ports {ddr3_addr[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] set_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}] # PadFunction: IO_L9N_T1_DQS_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}] set_property SLEW FAST [get_ports {ddr3_ba[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] set_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}] # PadFunction: IO_L7P_T1_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}] set_property SLEW FAST [get_ports {ddr3_ba[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] set_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}] # PadFunction: IO_L10N_T1_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}] set_property SLEW FAST [get_ports {ddr3_ba[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] set_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}] # PadFunction: IO_L11P_T1_SRCC_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}] set_property SLEW FAST [get_ports {ddr3_ras_n}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] set_property PACKAGE_PIN AE11 [get_ports {ddr3_ras_n}] # PadFunction: IO_L11N_T1_SRCC_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}] set_property SLEW FAST [get_ports {ddr3_cas_n}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] set_property PACKAGE_PIN AF11 [get_ports {ddr3_cas_n}] # PadFunction: IO_L24P_T3_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}] set_property SLEW FAST [get_ports {ddr3_we_n}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] set_property PACKAGE_PIN AG13 [get_ports {ddr3_we_n}] # PadFunction: IO_L12N_T1_MRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}] set_property SLEW FAST [get_ports {ddr3_reset_n}] set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] set_property PACKAGE_PIN AG5 [get_ports {ddr3_reset_n}] # PadFunction: IO_L15P_T2_DQS_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_cke[0]}] set_property SLEW FAST [get_ports {ddr3_cke[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] set_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}] # PadFunction: IO_L15N_T2_DQS_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_odt[0]}] set_property SLEW FAST [get_ports {ddr3_odt[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] set_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}] # PadFunction: IO_L24N_T3_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n[0]}] set_property SLEW FAST [get_ports {ddr3_cs_n[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}] set_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}] # PadFunction: IO_L1P_T0_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}] set_property SLEW FAST [get_ports {ddr3_dm[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}] # PadFunction: IO_L7P_T1_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}] set_property SLEW FAST [get_ports {ddr3_dm[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] set_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}] # PadFunction: IO_L13P_T2_MRCC_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}] set_property SLEW FAST [get_ports {ddr3_dm[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}] set_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}] # PadFunction: IO_L19P_T3_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}] set_property SLEW FAST [get_ports {ddr3_dm[3]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}] set_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}] # PadFunction: IO_L3P_T0_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}] set_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}] # PadFunction: IO_L3N_T0_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}] set_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}] # PadFunction: IO_L9P_T1_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}] set_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}] # PadFunction: IO_L9N_T1_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}] set_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}] # PadFunction: IO_L15P_T2_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}] set_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}] # PadFunction: IO_L15N_T2_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}] set_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}] # PadFunction: IO_L21P_T3_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}] set_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}] # PadFunction: IO_L21N_T3_DQS_34 set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}] set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}] set_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}] # PadFunction: IO_L3P_T0_DQS_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_ck_p[0]}] set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] set_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}] # PadFunction: IO_L3N_T0_DQS_33 set_property VCCAUX_IO HIGH [get_ports {ddr3_ck_n[0]}] set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] set_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}] set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] ## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] ## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] ## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] ## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}] set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}] set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ -setup 6 set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ -hold 5 set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/constraints/ddr3_if_ooc.xdc ================================================ ################################################################################################### ## This constraints file contains default clock frequencies to be used during creation of a ## Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified ## to match the target frequencies. ## This constraints file is not used in top-down/global synthesis (not the default flow of Vivado). ################################################################################################### ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com ## Tue Nov 15 09:39:56 2016 ## Generated by MIG Version 4.0 ## ################################################################################################## ## File name : ddr3_if.xdc ## Details : Constraints file ## FPGA Family: KINTEX7 ## FPGA Part: XC7K325T-FFG900 ## Speedgrade: -2 ## Design Entry: VERILOG ## Frequency: 0 MHz ## Time Period: 1112 ps ################################################################################################## ################################################################################################## ## Controller 0 ## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107 ## Data Width: 32 ## Time Period: 1112 ## Data Mask: 1 ################################################################################################## create_clock -period 5.004 [get_ports sys_clk_i] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_addr_decode.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_ctrl_ecc_top.v // // Description: // // Specifications: // // Structure: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_ctrl_addr_decode # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AXI-4-Lite address bus parameter integer C_ADDR_WIDTH = 32, // Number of Registers parameter integer C_NUM_REG = 5, parameter integer C_NUM_REG_WIDTH = 3, // Number of Registers parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF, parameter C_REG_RDWR_ARRAY = 5'b00101 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI4-Lite Slave Interface // Slave Interface System Signals input wire [C_ADDR_WIDTH-1:0] axaddr , // Slave Interface Write Data Ports output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// function [C_ADDR_WIDTH-1:0] calc_bit_mask ( input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array ); begin : func_calc_bit_mask integer i; reg [C_ADDR_WIDTH-1:0] first_addr; reg [C_ADDR_WIDTH-1:0] bit_mask; calc_bit_mask = {C_ADDR_WIDTH{1'b0}}; first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH]; for (i = 2; i < C_NUM_REG; i = i + 1) begin bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH]; calc_bit_mask = calc_bit_mask | bit_mask; end end endfunction function integer lsb_mask_index ( input [C_ADDR_WIDTH-1:0] mask ); begin : my_lsb_mask_index lsb_mask_index = 0; while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin lsb_mask_index = lsb_mask_index + 1; end end endfunction function integer msb_mask_index ( input [C_ADDR_WIDTH-1:0] mask ); begin : my_msb_mask_index msb_mask_index = C_ADDR_WIDTH-1; while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin msb_mask_index = msb_mask_index - 1; end end endfunction //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY); localparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK); localparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK); localparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// integer i; (* rom_extract = "no" *) reg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// always @(*) begin reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}}; for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH]) && C_REG_RDWR_ARRAY[i] ) begin reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0]; end end end assign reg_decode_num = reg_decode_num_i; endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_ctrl_read.v // // Description: // // Specifications: // // Structure: // axi_ctrl_top // axi_ctrl_write // axi_ctrl_addr_decode // axi_ctrl_read // axi_ctrl_addr_decode // axi_ctrl_reg_bank // axi_ctrl_reg // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_ctrl_read # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AXI-4-Lite address bus parameter integer C_ADDR_WIDTH = 32, // Width of AXI-4-Lite data buses parameter integer C_DATA_WIDTH = 32, // Number of Registers parameter integer C_NUM_REG = 5, parameter integer C_NUM_REG_WIDTH = 3, // Number of Registers parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF, parameter C_REG_RDAC_ARRAY = 5'b11111 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI4-Lite Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Read Address Ports input wire [C_ADDR_WIDTH-1:0] araddr , // Slave Interface Read Data Ports output wire rvalid , input wire rready , output wire [C_DATA_WIDTH-1:0] rdata , output wire [1:0] rresp , input wire pending , // MC Internal Signals input wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_bank_array ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire [C_NUM_REG_WIDTH-1:0] reg_decode_num; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// mig_7series_v4_0_axi_ctrl_addr_decode # ( .C_ADDR_WIDTH ( C_ADDR_WIDTH ) , .C_NUM_REG ( C_NUM_REG ) , .C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) , .C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) , .C_REG_RDWR_ARRAY ( C_REG_RDAC_ARRAY ) ) axi_ctrl_addr_decode_0 ( .axaddr ( araddr ) , .reg_decode_num ( reg_decode_num ) ); assign rdata = reg_bank_array[ reg_decode_num*32+:32]; assign rresp = 2'b0; // Okay assign rvalid = pending; endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_ctrl_reg.v // // Description: // This is just a general register. It has two write enables and two data ins // to simplify the operation. Typically one write enable (we) comes from the // external interface and the second write enable is used for internal writing // to the register. A mask parameter is used to only write to the bits that // are used in the register. // // Specifications: // // Structure: // axi_ctrl_top // axi_ctrl_write // axi_ctrl_addr_decode // axi_ctrl_read // axi_ctrl_addr_decode // axi_ctrl_reg_bank // axi_ctrl_reg // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_ctrl_reg # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_REG_WIDTH = 32, parameter integer C_DATA_WIDTH = 32, parameter C_INIT = 32'h0, parameter C_MASK = 32'h1 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_REG_WIDTH-1:0] data_in , input wire we , input wire we_int , input wire [C_REG_WIDTH-1:0] data_in_int , output wire [C_DATA_WIDTH-1:0] data_out ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [C_REG_WIDTH-1:0] data; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// always @(posedge clk) begin if (reset) begin data <= C_INIT[0+:C_REG_WIDTH]; end else if (we) begin data <= data_in; end else if (we_int) begin data <= data_in_int; end else begin data <= data; end end // Does not supprot case where P_MASK_LSB > 0 generate if (C_REG_WIDTH == C_DATA_WIDTH) begin : assign_no_zero_pad assign data_out = data; end else begin : assign_zero_pad assign data_out = {{C_DATA_WIDTH-C_REG_WIDTH{1'b0}}, data}; end endgenerate endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg_bank.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_ctrl_ecc_top.v // // Description: // // Specifications: // // Structure: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_ctrl_reg_bank # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AXI-4-Lite address bus parameter C_ADDR_WIDTH = 32, parameter C_DATA_WIDTH = 32, parameter C_DQ_WIDTH = 72, parameter C_ECC_CE_COUNTER_WIDTH = 8, parameter C_ECC_ONOFF_RESET_VALUE = 1, parameter C_ECC_TEST = "ON", parameter C_ECC_WIDTH = 8, parameter C_MC_ERR_ADDR_WIDTH = 28, parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN", // # of memory Bank Address bits. parameter C_BANK_WIDTH = 3, // # of memory Row Address bits. parameter C_ROW_WIDTH = 14, // # of memory Column Address bits. parameter C_COL_WIDTH = 10, parameter C_NCK_PER_CLK = 2, parameter C_NUM_REG = 24, parameter C_NUM_REG_WIDTH = 5, parameter C_S_AXI_ADDR_WIDTH = 32, parameter C_S_AXI_BASEADDR = 32'h0000_0000, // Register arrays parameter C_REG_WIDTH_ARRAY = 160'h0, parameter C_REG_RDAC_ARRAY = 5'b0, parameter C_REG_WRAC_ARRAY = 5'b0, parameter C_REG_INIT_ARRAY = 160'h0, parameter C_REG_MASK_ARRAY = 160'h0, parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF, // Register Indices parameter integer C_REG_FI_ECC_INDX = 23, parameter integer C_REG_FI_D_127_96_INDX = 22, parameter integer C_REG_FI_D_95_64_INDX = 21, parameter integer C_REG_FI_D_63_32_INDX = 20, parameter integer C_REG_FI_D_31_00_INDX = 19, parameter integer C_REG_UE_FFA_63_32_INDX = 18, parameter integer C_REG_UE_FFA_31_00_INDX = 17, parameter integer C_REG_UE_FFE_INDX = 16, parameter integer C_REG_UE_FFD_127_96_INDX = 15, parameter integer C_REG_UE_FFD_95_64_INDX = 14, parameter integer C_REG_UE_FFD_63_32_INDX = 13, parameter integer C_REG_UE_FFD_31_00_INDX = 12, parameter integer C_REG_CE_FFA_63_32_INDX = 11, parameter integer C_REG_CE_FFA_31_00_INDX = 10, parameter integer C_REG_CE_FFE_INDX = 9 , parameter integer C_REG_CE_FFD_127_96_INDX = 8 , parameter integer C_REG_CE_FFD_95_64_INDX = 7 , parameter integer C_REG_CE_FFD_63_32_INDX = 6 , parameter integer C_REG_CE_FFD_31_00_INDX = 5 , parameter integer C_REG_CE_CNT_INDX = 4 , parameter integer C_REG_ECC_ON_OFF_INDX = 3 , parameter integer C_REG_ECC_EN_IRQ_INDX = 2 , parameter integer C_REG_ECC_STATUS_INDX = 1 , parameter integer C_REG_DUMMY_INDX = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI4-Lite Slave Interface // Slave Interface System Signals input wire clk , input wire reset , input wire [C_NUM_REG_WIDTH-1:0] reg_data_sel , input wire reg_data_write , input wire [C_DATA_WIDTH-1:0] reg_data_in , output wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_data_out , output wire interrupt , input wire [2*C_NCK_PER_CLK-1:0] ecc_single , input wire [2*C_NCK_PER_CLK-1:0] ecc_multiple , input wire [C_MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr , output wire app_correct_en , input wire [2*C_NCK_PER_CLK*C_DQ_WIDTH-1:0] dfi_rddata , output wire [C_DQ_WIDTH/8-1:0] fi_xor_we , output wire [C_DQ_WIDTH-1:0] fi_xor_wrdata ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_FI_XOR_WE_WIDTH = (C_DQ_WIDTH%C_DATA_WIDTH)/8; localparam P_SHIFT_BY = C_DQ_WIDTH == 72 ? 3 : 4; localparam P_CS_WIDTH = C_MC_ERR_ADDR_WIDTH - C_COL_WIDTH - C_ROW_WIDTH - C_BANK_WIDTH - 1; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// integer beat; reg [C_DQ_WIDTH-1:0] ffs; reg [C_DQ_WIDTH-1:0] ffm; wire [7:0] ecc_single_expanded; wire [7:0] ecc_multiple_expanded; reg [C_S_AXI_ADDR_WIDTH-1:0] ffas; reg [C_S_AXI_ADDR_WIDTH-1:0] ffam; reg [2:0] ffas_lsb; reg [2:0] ffam_lsb; wire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_real; wire ecc_err_addr_offset; wire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_swap_row_bank; wire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_swapped; wire [C_NUM_REG-1:0] we; wire [C_DATA_WIDTH*C_NUM_REG-1:0] data_in; wire [C_NUM_REG-1:0] we_int; wire [C_DATA_WIDTH*C_NUM_REG-1:0] data_in_int; wire [C_DATA_WIDTH*C_NUM_REG-1:0] data_out; reg interrupt_r; reg ecc_on_off_r; reg ce_clr_r; reg ue_clr_r; wire ce_set_i; wire ue_set_i; reg [C_DQ_WIDTH/8-1:0] fi_xor_we_r; reg [C_DQ_WIDTH-1:0] fi_xor_wrdata_r; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // Assign outputs assign reg_data_out = data_out; assign interrupt = interrupt_r & ecc_on_off_r; assign app_correct_en = ecc_on_off_r; assign fi_xor_wrdata = fi_xor_wrdata_r; assign fi_xor_we = fi_xor_we_r & {C_DQ_WIDTH/8{ecc_on_off_r}}; // Calculate inputs // Always block selects the first failing beat out C_NCK_PER_CLK*2 beats. If // no failing beats, default to last beat. always @(*) begin ffs = dfi_rddata[(C_NCK_PER_CLK*2-1)*C_DQ_WIDTH+:C_DQ_WIDTH]; ffm = dfi_rddata[(C_NCK_PER_CLK*2-1)*C_DQ_WIDTH+:C_DQ_WIDTH]; for( beat = C_NCK_PER_CLK*2-2; beat >= 0 ; beat = beat - 1) begin : find_first_failing_beat if (ecc_single[beat]) begin ffs = dfi_rddata[beat*C_DQ_WIDTH+:C_DQ_WIDTH]; // ffas_lsb = beat[2:0]; // | {ecc_err_addr_offset| ecc_err_addr_real[2], 2'b0}; end if (ecc_multiple[beat]) begin ffm = dfi_rddata[beat*C_DQ_WIDTH+:C_DQ_WIDTH]; // ffam_lsb = beat[2:0]; // | {ecc_err_addr_offset| ecc_err_addr_real[2], 2'b0}; end end end generate if (C_NCK_PER_CLK == 2) begin : ecc_zero_extened assign ecc_single_expanded = {4'b0, ecc_single[3:0]}; assign ecc_multiple_expanded = {4'b0, ecc_multiple[3:0]}; end else begin : no_ecc_zero_extend assign ecc_single_expanded = ecc_single[7:0]; assign ecc_multiple_expanded = ecc_multiple[7:0]; end endgenerate always @(*) begin (* full_case *) (* parallel_case *) casex (ecc_single_expanded) 8'bxxxx_xxx1: ffas_lsb = 3'o0; 8'bxxxx_xx10: ffas_lsb = 3'o1; 8'bxxxx_x100: ffas_lsb = 3'o2; 8'bxxxx_1000: ffas_lsb = 3'o3; 8'bxxx1_0000: ffas_lsb = 3'o4; 8'bxx10_0000: ffas_lsb = 3'o5; 8'bx100_0000: ffas_lsb = 3'o6; 8'b1000_0000: ffas_lsb = 3'o7; default: ffas_lsb = 3'o0; endcase end always @(*) begin (* full_case *) (* parallel_case *) casex (ecc_multiple_expanded) 8'bxxxx_xxx1: ffam_lsb = 3'o0; 8'bxxxx_xx10: ffam_lsb = 3'o1; 8'bxxxx_x100: ffam_lsb = 3'o2; 8'bxxxx_1000: ffam_lsb = 3'o3; 8'bxxx1_0000: ffam_lsb = 3'o4; 8'bxx10_0000: ffam_lsb = 3'o5; 8'bx100_0000: ffam_lsb = 3'o6; 8'b1000_0000: ffam_lsb = 3'o7; default: ffam_lsb = 3'o0; endcase end // Calculate first failing address // Split ecc_err_addr, lower bit of ecc_err_addr is the offset, and not part // of the column address. assign ecc_err_addr_real[C_MC_ERR_ADDR_WIDTH-2:3] = ecc_err_addr[C_MC_ERR_ADDR_WIDTH-1:4]; // if ecc_err_addr[0] == 1, then the error is on the 2nd 4 beats of BL8. assign ecc_err_addr_real[2] = ecc_err_addr[3] | ecc_err_addr[0]; // Lower two bits always expected to be 0b00 assign ecc_err_addr_real[1:0] = ecc_err_addr[2:1]; // Swap Row Bank bits if we need it. Special case for no cs bits. assign ecc_err_addr_swap_row_bank[C_COL_WIDTH+:C_ROW_WIDTH+C_BANK_WIDTH] = {ecc_err_addr_real[C_COL_WIDTH+:C_ROW_WIDTH], ecc_err_addr_real[C_COL_WIDTH+C_ROW_WIDTH+:C_BANK_WIDTH]}; assign ecc_err_addr_swap_row_bank[0+:C_COL_WIDTH] = ecc_err_addr_real[0+:C_COL_WIDTH]; generate begin if (P_CS_WIDTH > 0) begin : CS_WIDTH_ASSIGN assign ecc_err_addr_swap_row_bank[C_COL_WIDTH+C_ROW_WIDTH+C_BANK_WIDTH+:P_CS_WIDTH] = ecc_err_addr_real[C_COL_WIDTH+C_ROW_WIDTH+C_BANK_WIDTH+:P_CS_WIDTH]; end end endgenerate // swap row/bank if necessary assign ecc_err_addr_swapped = (C_MEM_ADDR_ORDER == "BANK_ROW_COLUMN") ? ecc_err_addr_real : ecc_err_addr_swap_row_bank; // Assign final result always @(*) begin ffas = ({ecc_err_addr_swapped[3+:C_MC_ERR_ADDR_WIDTH-4], (ffas_lsb[2] | ecc_err_addr_real[2]), ffas_lsb[1:0]} << P_SHIFT_BY) | C_S_AXI_BASEADDR; ffam = ({ecc_err_addr_swapped[3+:C_MC_ERR_ADDR_WIDTH-4], (ffam_lsb[2] | ecc_err_addr_real[2]), ffam_lsb[1:0]} << P_SHIFT_BY) | C_S_AXI_BASEADDR; end generate genvar i; genvar j; for (i = 0; i < C_NUM_REG; i = i + 1) begin : inst_reg if (C_REG_MASK_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] > 0) begin mig_7series_v4_0_axi_ctrl_reg # ( .C_DATA_WIDTH ( C_DATA_WIDTH ) , .C_REG_WIDTH ( C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]) , .C_INIT ( C_REG_INIT_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) , .C_MASK ( C_REG_MASK_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) ) axi_ctrl_reg ( .clk ( clk ) , .reset ( reset ) , .data_in ( data_in[i*C_DATA_WIDTH+:C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]] ) , .we ( we[i] ) , .data_in_int ( data_in_int[i*C_DATA_WIDTH+:C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]] ) , .we_int ( we_int[i] ) , .data_out ( data_out[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) ); end else begin : no_reg assign data_out[i*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end // Determine write logic for each register for (j = 0; j < C_NUM_REG; j = j + 1) begin : inst_reg_logic_ case (j) C_REG_ECC_STATUS_INDX: begin // Bit Name Desc // 1 CE_STATUS If '1' a correctable error has occurred. Cleared when '1' is written to this bit // position. // 0 UE_STATUS If '1' a uncorrectable error has occurred. Cleared when '1' is written to this bit // position. assign we[j] = (reg_data_sel == j) && reg_data_write; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ~reg_data_in & data_out[j*C_DATA_WIDTH+:C_DATA_WIDTH]; assign we_int[j] = ecc_on_off_r; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {30'b0, (|ecc_single | data_out[j*C_DATA_WIDTH + 1]), (|ecc_multiple | data_out[j*C_DATA_WIDTH + 0])}; // Drive internal signals to write to other registers always @(posedge clk) begin ce_clr_r <= ~data_in[j*C_DATA_WIDTH + 1] & we[j]; ue_clr_r <= ~data_in[j*C_DATA_WIDTH + 0] & we[j]; end assign ce_set_i = data_in_int[j*C_DATA_WIDTH + 1] & we_int[j] & ~data_out[j*C_DATA_WIDTH + 1]; assign ue_set_i = data_in_int[j*C_DATA_WIDTH + 0] & we_int[j] & ~data_out[j*C_DATA_WIDTH + 0]; end C_REG_ECC_EN_IRQ_INDX: begin // Bit Name Desc // 1 CE_EN_IRQ If '1' the value of the CE_STATUS bit of ECC Status Register will be propagated to the // Interrupt signal. If '0' the value of the CE_STATUS bit of ECC Status Register will not // be propagated to the Interrupt signal. // position. // 0 UE_EN_IRQ See above // assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; always @(posedge clk) begin interrupt_r <= |(data_out[j*C_DATA_WIDTH+:C_DATA_WIDTH] & data_out[C_REG_ECC_STATUS_INDX*C_DATA_WIDTH+:C_DATA_WIDTH]); end end C_REG_ECC_ON_OFF_INDX: begin // Bit Name Desc // 0 ECC_ON_OFF If '0', ECC checking is disable on read operations. If '1', ECC checking is enabled on // read operations. All correctable and uncorrectable error condtions will be captured // and status updated. assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; always @(posedge clk) begin ecc_on_off_r <= data_out[j*C_DATA_WIDTH+0]; end end C_REG_CE_CNT_INDX: begin // Bit Name Desc // 7:0 CE_CNT Register holds number of correctable errors encountered. assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in; assign data_in_int[j*C_DATA_WIDTH+:C_ECC_CE_COUNTER_WIDTH+1] = data_out[j*C_DATA_WIDTH+:C_ECC_CE_COUNTER_WIDTH+1] + 1'b1; assign data_in_int[j*C_DATA_WIDTH+C_ECC_CE_COUNTER_WIDTH+1+:C_DATA_WIDTH-(C_ECC_CE_COUNTER_WIDTH+1)] = {C_DATA_WIDTH-(C_ECC_CE_COUNTER_WIDTH+1){1'b0}}; // Only write if there is an error and it will not cause an overflow assign we_int[j] = ecc_on_off_r & (|ecc_single) & ~data_in_int[j*C_DATA_WIDTH + C_ECC_CE_COUNTER_WIDTH]; end C_REG_CE_FFD_31_00_INDX: begin assign we[j] = ce_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ce_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[0*C_DATA_WIDTH+:C_DATA_WIDTH]; end C_REG_CE_FFD_63_32_INDX: begin assign we[j] = ce_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ce_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[1*C_DATA_WIDTH+:C_DATA_WIDTH]; end C_REG_CE_FFD_95_64_INDX: begin if (C_DQ_WIDTH == 144) begin assign we[j] = ce_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ce_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[2*C_DATA_WIDTH+:C_DATA_WIDTH]; end else begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end C_REG_CE_FFD_127_96_INDX: begin if (C_DQ_WIDTH == 144) begin assign we[j] = ce_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ce_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[3*C_DATA_WIDTH+:C_DATA_WIDTH]; end else begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end C_REG_CE_FFE_INDX: begin assign we[j] = ce_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ce_set_i; if (C_DQ_WIDTH == 144) begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffs[128+:C_ECC_WIDTH] }; end else begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffs[ 64+:C_ECC_WIDTH] }; end end C_REG_CE_FFA_31_00_INDX: begin assign we[j] = ce_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ce_set_i; if (C_S_AXI_ADDR_WIDTH < C_DATA_WIDTH) begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{(C_DATA_WIDTH-C_S_AXI_ADDR_WIDTH){1'b0}}, ffas[0*C_DATA_WIDTH+:C_S_AXI_ADDR_WIDTH]}; end else begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffas[0*C_DATA_WIDTH+:C_DATA_WIDTH]; end end C_REG_CE_FFA_63_32_INDX: begin assign we[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ce_clr_r : 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ce_set_i : 1'b0; if (C_S_AXI_ADDR_WIDTH > C_DATA_WIDTH) begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{((2*C_DATA_WIDTH)-C_S_AXI_ADDR_WIDTH){1'b0}}, ffas[C_DATA_WIDTH+:(C_S_AXI_ADDR_WIDTH-C_DATA_WIDTH)]}; end else begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end C_REG_UE_FFD_31_00_INDX: begin assign we[j] = ue_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ue_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[0*C_DATA_WIDTH+:C_DATA_WIDTH]; end C_REG_UE_FFD_63_32_INDX: begin assign we[j] = ue_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ue_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[1*C_DATA_WIDTH+:C_DATA_WIDTH]; end C_REG_UE_FFD_95_64_INDX: begin if (C_DQ_WIDTH == 144) begin assign we[j] = ue_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ue_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[2*C_DATA_WIDTH+:C_DATA_WIDTH]; end else begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end C_REG_UE_FFD_127_96_INDX: begin if (C_DQ_WIDTH == 144) begin assign we[j] = ue_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ue_set_i; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[3*C_DATA_WIDTH+:C_DATA_WIDTH]; end else begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end C_REG_UE_FFE_INDX: begin assign we[j] = ue_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ue_set_i; if (C_DQ_WIDTH == 144) begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffm[128+:C_ECC_WIDTH] }; end else begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffm[ 64+:C_ECC_WIDTH] }; end end C_REG_UE_FFA_31_00_INDX: begin assign we[j] = ue_clr_r; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = ue_set_i; if (C_S_AXI_ADDR_WIDTH < C_DATA_WIDTH) begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{(C_DATA_WIDTH-C_S_AXI_ADDR_WIDTH){1'b0}}, ffam[0*C_DATA_WIDTH+:C_S_AXI_ADDR_WIDTH]}; end else begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffam[0*C_DATA_WIDTH+:C_DATA_WIDTH]; end end C_REG_UE_FFA_63_32_INDX: begin assign we[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ue_clr_r : 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ue_set_i : 1'b0; if (C_S_AXI_ADDR_WIDTH > C_DATA_WIDTH) begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{((2*C_DATA_WIDTH)-C_S_AXI_ADDR_WIDTH){1'b0}}, ffam[C_DATA_WIDTH+:(C_S_AXI_ADDR_WIDTH-C_DATA_WIDTH)]}; end else begin assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end end C_REG_FI_D_31_00_INDX: begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; //if (C_ECC_TEST == "ON") begin always @(posedge clk) begin fi_xor_we_r[0*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} : {C_DATA_WIDTH/8{1'b0}}; fi_xor_wrdata_r[0*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0]; end //end end C_REG_FI_D_63_32_INDX: begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; //if (C_ECC_TEST == "ON") begin always @(posedge clk) begin fi_xor_we_r[1*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} : {C_DATA_WIDTH/8{1'b0}}; fi_xor_wrdata_r[1*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0]; end //end end C_REG_FI_D_95_64_INDX: begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == "ON"*/) begin always @(posedge clk) begin fi_xor_we_r[2*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} : {C_DATA_WIDTH/8{1'b0}}; fi_xor_wrdata_r[2*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0]; end end end C_REG_FI_D_127_96_INDX: begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == "ON"*/) begin always @(posedge clk) begin fi_xor_we_r[3*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} : {C_DATA_WIDTH/8{1'b0}}; fi_xor_wrdata_r[3*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0]; end end end C_REG_FI_ECC_INDX: begin assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; if (C_DQ_WIDTH == 72 /*&& C_ECC_TEST == "ON"*/) begin always @(posedge clk) begin fi_xor_we_r[2*C_DATA_WIDTH/8+:P_FI_XOR_WE_WIDTH] <= (reg_data_sel == j) ? {P_FI_XOR_WE_WIDTH{reg_data_write}} : {P_FI_XOR_WE_WIDTH{1'b0}}; fi_xor_wrdata_r[2*C_DATA_WIDTH+:C_DQ_WIDTH%C_DATA_WIDTH] <= reg_data_in[C_DQ_WIDTH%C_DATA_WIDTH-1:0]; end end if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == "ON"*/) begin always @(posedge clk) begin fi_xor_we_r[4*C_DATA_WIDTH/8+:P_FI_XOR_WE_WIDTH] <= (reg_data_sel == j) ? {P_FI_XOR_WE_WIDTH{reg_data_write}} : {P_FI_XOR_WE_WIDTH{1'b0}}; fi_xor_wrdata_r[4*C_DATA_WIDTH+:C_DQ_WIDTH%C_DATA_WIDTH] <= reg_data_in[C_DQ_WIDTH%C_DATA_WIDTH-1:0]; end end end default: begin // Tie off reg inputs assign we[j] = 1'b0; assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; assign we_int[j] = 1'b0; assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}}; end endcase end endgenerate endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_top.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_ctrl_top.v // // Description: // // Specifications: // // Structure: // axi_ctrl_top // axi_ctrl_write // axi_ctrl_addr_decode // axi_ctrl_read // axi_ctrl_addr_decode // axi_ctrl_reg_bank // axi_ctrl_reg // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_ctrl_top # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AXI-4-Lite address bus parameter integer C_S_AXI_CTRL_ADDR_WIDTH = 32, // Width of AXI-4-Lite data buses parameter integer C_S_AXI_CTRL_DATA_WIDTH = 32, // Width of AXI-4 Memory Mapped address bus parameter integer C_S_AXI_ADDR_WIDTH = 32, // Width of AXI-4 Memory Mapped address bus parameter integer C_S_AXI_BASEADDR = 32'h0000_0000, // Enable or disable fault injection logic test hardware. parameter C_ECC_TEST = "ON", // External Memory Data Width parameter integer C_DQ_WIDTH = 72, // Memory ECC Width parameter integer C_ECC_WIDTH = 8, // Memory Address Order parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN", // # of memory Bank Address bits. parameter C_BANK_WIDTH = 3, // # of memory Row Address bits. parameter C_ROW_WIDTH = 14, // # of memory Column Address bits. parameter C_COL_WIDTH = 10, // Controls ECC on/off value at startup/reset parameter integer C_ECC_ONOFF_RESET_VALUE = 1, // Controls CE counter width parameter integer C_ECC_CE_COUNTER_WIDTH = 8, // The external memory to controller clock ratio. parameter integer C_NCK_PER_CLK = 2, parameter C_MC_ERR_ADDR_WIDTH = 28 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI4-Lite Slave Interface // Slave Interface System Signals input wire aclk , input wire aresetn , // Slave Interface Write Address Ports input wire s_axi_awvalid , output wire s_axi_awready , input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_awaddr , // Slave Interface Write Data Ports input wire s_axi_wvalid , output wire s_axi_wready , input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_wdata , // Slave Interface Write Response Ports output wire s_axi_bvalid , input wire s_axi_bready , output wire [1:0] s_axi_bresp , // Slave Interface Read Address Ports input wire s_axi_arvalid , output wire s_axi_arready , input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_araddr , // Slave Interface Read Data Ports output wire s_axi_rvalid , input wire s_axi_rready , output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_rdata , output wire [1:0] s_axi_rresp , // Interrupt output output wire interrupt , // MC Internal Signals input wire init_complete , input wire [2*C_NCK_PER_CLK-1:0] ecc_single , input wire [2*C_NCK_PER_CLK-1:0] ecc_multiple , input wire [C_MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr , output wire app_correct_en , input wire [2*C_NCK_PER_CLK*C_DQ_WIDTH-1:0] dfi_rddata , output wire [C_DQ_WIDTH/8-1:0] fi_xor_we , output wire [C_DQ_WIDTH-1:0] fi_xor_wrdata ); ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// function integer lsb_mask_index ( input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask ); begin : my_lsb_mask_index lsb_mask_index = 0; while ((lsb_mask_index < C_S_AXI_CTRL_DATA_WIDTH-1) && ~mask[lsb_mask_index]) begin lsb_mask_index = lsb_mask_index + 1; end end endfunction function integer msb_mask_index ( input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask ); begin : my_msb_mask_index msb_mask_index = C_S_AXI_CTRL_DATA_WIDTH-1; while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin msb_mask_index = msb_mask_index - 1; end end endfunction function integer mask_width ( input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask ); begin : my_mask_width if (msb_mask_index(mask) > lsb_mask_index(mask)) begin mask_width = msb_mask_index(mask) - lsb_mask_index(mask) + 1; end else begin mask_width = 1; end end endfunction // clog2. function integer clog2; // Value to calculate clog2 on input integer value; begin for (clog2=0; value>0; clog2=clog2+1) begin value = value >> 1; end end endfunction //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // BEGIN Auto-generated Register Mapping localparam P_NUM_REG = 24; localparam P_NUM_REG_WIDTH = clog2(P_NUM_REG); localparam P_REG_FI_ECC_RDAC = 1'b0; localparam P_REG_FI_ECC_INDX = 23; localparam P_REG_FI_ECC_INIT = 32'h0000_0000; localparam P_REG_FI_ECC_WRAC = (C_ECC_TEST == "ON") ? 1'b1 : 1'b0; localparam P_REG_FI_ECC_ADDR = 32'h0000_0380; localparam P_REG_FI_ECC_MASK = 32'h0000_0000; localparam P_REG_FI_D_127_96_RDAC = 1'b0; localparam P_REG_FI_D_127_96_INDX = 22; localparam P_REG_FI_D_127_96_INIT = 32'h0000_0000; localparam P_REG_FI_D_127_96_WRAC = (C_ECC_TEST == "ON") && (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0; localparam P_REG_FI_D_127_96_ADDR = 32'h0000_030C; localparam P_REG_FI_D_127_96_MASK = 32'h0000_0000; localparam P_REG_FI_D_95_64_RDAC = 1'b0; localparam P_REG_FI_D_95_64_INDX = 21; localparam P_REG_FI_D_95_64_INIT = 32'h0000_0000; localparam P_REG_FI_D_95_64_WRAC = (C_ECC_TEST == "ON") && (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0; localparam P_REG_FI_D_95_64_ADDR = 32'h0000_0308; localparam P_REG_FI_D_95_64_MASK = 32'h0000_0000; localparam P_REG_FI_D_63_32_RDAC = 1'b0; localparam P_REG_FI_D_63_32_INDX = 20; localparam P_REG_FI_D_63_32_INIT = 32'h0000_0000; localparam P_REG_FI_D_63_32_WRAC = (C_ECC_TEST == "ON") ? 1'b1 : 1'b0; localparam P_REG_FI_D_63_32_ADDR = 32'h0000_0304; localparam P_REG_FI_D_63_32_MASK = 32'h0000_0000; localparam P_REG_FI_D_31_00_RDAC = 1'b0; localparam P_REG_FI_D_31_00_INDX = 19; localparam P_REG_FI_D_31_00_INIT = 32'h0000_0000; localparam P_REG_FI_D_31_00_WRAC = (C_ECC_TEST == "ON") ? 1'b1 : 1'b0; localparam P_REG_FI_D_31_00_ADDR = 32'h0000_0300; localparam P_REG_FI_D_31_00_MASK = 32'h0000_0000; localparam P_REG_UE_FFA_63_32_RDAC = (C_S_AXI_ADDR_WIDTH > 32) ? 1'b1 : 1'b0; localparam P_REG_UE_FFA_63_32_INDX = 18; localparam P_REG_UE_FFA_63_32_INIT = 32'h0000_0000; localparam P_REG_UE_FFA_63_32_WRAC = 1'b0; localparam P_REG_UE_FFA_63_32_ADDR = 32'h0000_02C4; localparam P_REG_UE_FFA_63_32_MASK = 32'hFFFF_FFFF; localparam P_REG_UE_FFA_31_00_RDAC = 1'b1; localparam P_REG_UE_FFA_31_00_INDX = 17; localparam P_REG_UE_FFA_31_00_INIT = 32'h0000_0000; localparam P_REG_UE_FFA_31_00_WRAC = 1'b0; localparam P_REG_UE_FFA_31_00_ADDR = 32'h0000_02C0; localparam P_REG_UE_FFA_31_00_MASK = 32'hFFFF_FFFF; localparam P_REG_UE_FFE_RDAC = 1'b1; localparam P_REG_UE_FFE_INDX = 16; localparam P_REG_UE_FFE_INIT = 32'h0000_0000; localparam P_REG_UE_FFE_WRAC = 1'b0; localparam P_REG_UE_FFE_ADDR = 32'h0000_0280; localparam P_REG_UE_FFE_MASK = 32'h0000_FFFF; localparam P_REG_UE_FFD_127_96_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ; localparam P_REG_UE_FFD_127_96_INDX = 15; localparam P_REG_UE_FFD_127_96_INIT = 32'h0000_0000; localparam P_REG_UE_FFD_127_96_WRAC = 1'b0; localparam P_REG_UE_FFD_127_96_ADDR = 32'h0000_020C; localparam P_REG_UE_FFD_127_96_MASK = 32'hFFFF_FFFF; localparam P_REG_UE_FFD_95_64_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ; localparam P_REG_UE_FFD_95_64_INDX = 14; localparam P_REG_UE_FFD_95_64_INIT = 32'h0000_0000; localparam P_REG_UE_FFD_95_64_WRAC = 1'b0; localparam P_REG_UE_FFD_95_64_ADDR = 32'h0000_0208; localparam P_REG_UE_FFD_95_64_MASK = 32'hFFFF_FFFF; localparam P_REG_UE_FFD_63_32_RDAC = 1'b1; localparam P_REG_UE_FFD_63_32_INDX = 13; localparam P_REG_UE_FFD_63_32_INIT = 32'h0000_0000; localparam P_REG_UE_FFD_63_32_WRAC = 1'b0; localparam P_REG_UE_FFD_63_32_ADDR = 32'h0000_0204; localparam P_REG_UE_FFD_63_32_MASK = 32'hFFFF_FFFF; localparam P_REG_UE_FFD_31_00_RDAC = 1'b1; localparam P_REG_UE_FFD_31_00_INDX = 12; localparam P_REG_UE_FFD_31_00_INIT = 32'h0000_0000; localparam P_REG_UE_FFD_31_00_WRAC = 1'b0; localparam P_REG_UE_FFD_31_00_ADDR = 32'h0000_0200; localparam P_REG_UE_FFD_31_00_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_FFA_63_32_RDAC = (C_S_AXI_ADDR_WIDTH > 32) ? 1'b1 : 1'b0; localparam P_REG_CE_FFA_63_32_INDX = 11; localparam P_REG_CE_FFA_63_32_INIT = 32'h0000_0000; localparam P_REG_CE_FFA_63_32_WRAC = 1'b0; localparam P_REG_CE_FFA_63_32_ADDR = 32'h0000_01C4; localparam P_REG_CE_FFA_63_32_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_FFA_31_00_RDAC = 1'b1; localparam P_REG_CE_FFA_31_00_INDX = 10; localparam P_REG_CE_FFA_31_00_INIT = 32'h0000_0000; localparam P_REG_CE_FFA_31_00_WRAC = 1'b0; localparam P_REG_CE_FFA_31_00_ADDR = 32'h0000_01C0; localparam P_REG_CE_FFA_31_00_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_FFE_RDAC = 1'b1; localparam P_REG_CE_FFE_INDX = 9; localparam P_REG_CE_FFE_INIT = 32'h0000_0000; localparam P_REG_CE_FFE_WRAC = 1'b0; localparam P_REG_CE_FFE_ADDR = 32'h0000_0180; localparam P_REG_CE_FFE_MASK = 32'h0000_FFFF; localparam P_REG_CE_FFD_127_96_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ; localparam P_REG_CE_FFD_127_96_INDX = 8; localparam P_REG_CE_FFD_127_96_INIT = 32'h0000_0000; localparam P_REG_CE_FFD_127_96_WRAC = 1'b0; localparam P_REG_CE_FFD_127_96_ADDR = 32'h0000_010C; localparam P_REG_CE_FFD_127_96_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_FFD_95_64_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ; localparam P_REG_CE_FFD_95_64_INDX = 7; localparam P_REG_CE_FFD_95_64_INIT = 32'h0000_0000; localparam P_REG_CE_FFD_95_64_WRAC = 1'b0; localparam P_REG_CE_FFD_95_64_ADDR = 32'h0000_0108; localparam P_REG_CE_FFD_95_64_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_FFD_63_32_RDAC = 1'b1; localparam P_REG_CE_FFD_63_32_INDX = 6; localparam P_REG_CE_FFD_63_32_INIT = 32'h0000_0000; localparam P_REG_CE_FFD_63_32_WRAC = 1'b0; localparam P_REG_CE_FFD_63_32_ADDR = 32'h0000_0104; localparam P_REG_CE_FFD_63_32_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_FFD_31_00_RDAC = 1'b1; localparam P_REG_CE_FFD_31_00_INDX = 5; localparam P_REG_CE_FFD_31_00_INIT = 32'h0000_0000; localparam P_REG_CE_FFD_31_00_WRAC = 1'b0; localparam P_REG_CE_FFD_31_00_ADDR = 32'h0000_0100; localparam P_REG_CE_FFD_31_00_MASK = 32'hFFFF_FFFF; localparam P_REG_CE_CNT_RDAC = 1'b1; localparam P_REG_CE_CNT_INDX = 4; localparam P_REG_CE_CNT_INIT = 32'h0000_0000; localparam P_REG_CE_CNT_WRAC = 1'b1; localparam P_REG_CE_CNT_ADDR = 32'h0000_000C; localparam P_REG_CE_CNT_MASK = {{C_S_AXI_CTRL_DATA_WIDTH-C_ECC_CE_COUNTER_WIDTH{1'b0}}, {C_ECC_CE_COUNTER_WIDTH{1'b1}}}; localparam P_REG_ECC_ON_OFF_RDAC = 1'b1; localparam P_REG_ECC_ON_OFF_INDX = 3; localparam P_REG_ECC_ON_OFF_INIT = {{31{1'b0}}, C_ECC_ONOFF_RESET_VALUE[0]}; localparam P_REG_ECC_ON_OFF_WRAC = 1'b1; localparam P_REG_ECC_ON_OFF_ADDR = 32'h0000_0008; localparam P_REG_ECC_ON_OFF_MASK = 32'h0000_0001; localparam P_REG_ECC_EN_IRQ_RDAC = 1'b1; localparam P_REG_ECC_EN_IRQ_INDX = 2; localparam P_REG_ECC_EN_IRQ_INIT = 32'h0000_0000; localparam P_REG_ECC_EN_IRQ_WRAC = 1'b1; localparam P_REG_ECC_EN_IRQ_ADDR = 32'h0000_0004; localparam P_REG_ECC_EN_IRQ_MASK = 32'h0000_0003; localparam P_REG_ECC_STATUS_RDAC = 1'b1; localparam P_REG_ECC_STATUS_INDX = 1; localparam P_REG_ECC_STATUS_INIT = 32'h0000_0000; localparam P_REG_ECC_STATUS_WRAC = 1'b1; localparam P_REG_ECC_STATUS_ADDR = 32'h0000_0000; localparam P_REG_ECC_STATUS_MASK = 32'h0000_0003; localparam P_REG_DUMMY_RDAC = 1'b1; localparam P_REG_DUMMY_INDX = 0; localparam P_REG_DUMMY_INIT = 32'hDEAD_DEAD; localparam P_REG_DUMMY_WRAC = 1'b1; localparam P_REG_DUMMY_ADDR = 32'hFFFF_FFFF; localparam P_REG_DUMMY_MASK = 32'hFFFF_FFFF; localparam P_REG_INDX_ARRAY = { P_REG_FI_ECC_INDX, P_REG_FI_D_127_96_INDX, P_REG_FI_D_95_64_INDX, P_REG_FI_D_63_32_INDX, P_REG_FI_D_31_00_INDX, P_REG_UE_FFA_63_32_INDX, P_REG_UE_FFA_31_00_INDX, P_REG_UE_FFE_INDX, P_REG_UE_FFD_127_96_INDX, P_REG_UE_FFD_95_64_INDX, P_REG_UE_FFD_63_32_INDX, P_REG_UE_FFD_31_00_INDX, P_REG_CE_FFA_63_32_INDX, P_REG_CE_FFA_31_00_INDX, P_REG_CE_FFE_INDX, P_REG_CE_FFD_127_96_INDX, P_REG_CE_FFD_95_64_INDX, P_REG_CE_FFD_63_32_INDX, P_REG_CE_FFD_31_00_INDX, P_REG_CE_CNT_INDX, P_REG_ECC_ON_OFF_INDX, P_REG_ECC_EN_IRQ_INDX, P_REG_ECC_STATUS_INDX, P_REG_DUMMY_INDX }; localparam P_REG_RDAC_ARRAY = { P_REG_FI_ECC_RDAC, P_REG_FI_D_127_96_RDAC, P_REG_FI_D_95_64_RDAC, P_REG_FI_D_63_32_RDAC, P_REG_FI_D_31_00_RDAC, P_REG_UE_FFA_63_32_RDAC, P_REG_UE_FFA_31_00_RDAC, P_REG_UE_FFE_RDAC, P_REG_UE_FFD_127_96_RDAC, P_REG_UE_FFD_95_64_RDAC, P_REG_UE_FFD_63_32_RDAC, P_REG_UE_FFD_31_00_RDAC, P_REG_CE_FFA_63_32_RDAC, P_REG_CE_FFA_31_00_RDAC, P_REG_CE_FFE_RDAC, P_REG_CE_FFD_127_96_RDAC, P_REG_CE_FFD_95_64_RDAC, P_REG_CE_FFD_63_32_RDAC, P_REG_CE_FFD_31_00_RDAC, P_REG_CE_CNT_RDAC, P_REG_ECC_ON_OFF_RDAC, P_REG_ECC_EN_IRQ_RDAC, P_REG_ECC_STATUS_RDAC, P_REG_DUMMY_RDAC }; localparam P_REG_INIT_ARRAY = { P_REG_FI_ECC_INIT, P_REG_FI_D_127_96_INIT, P_REG_FI_D_95_64_INIT, P_REG_FI_D_63_32_INIT, P_REG_FI_D_31_00_INIT, P_REG_UE_FFA_63_32_INIT, P_REG_UE_FFA_31_00_INIT, P_REG_UE_FFE_INIT, P_REG_UE_FFD_127_96_INIT, P_REG_UE_FFD_95_64_INIT, P_REG_UE_FFD_63_32_INIT, P_REG_UE_FFD_31_00_INIT, P_REG_CE_FFA_63_32_INIT, P_REG_CE_FFA_31_00_INIT, P_REG_CE_FFE_INIT, P_REG_CE_FFD_127_96_INIT, P_REG_CE_FFD_95_64_INIT, P_REG_CE_FFD_63_32_INIT, P_REG_CE_FFD_31_00_INIT, P_REG_CE_CNT_INIT, P_REG_ECC_ON_OFF_INIT, P_REG_ECC_EN_IRQ_INIT, P_REG_ECC_STATUS_INIT, P_REG_DUMMY_INIT }; localparam P_REG_ADDR_ARRAY = { P_REG_FI_ECC_ADDR, P_REG_FI_D_127_96_ADDR, P_REG_FI_D_95_64_ADDR, P_REG_FI_D_63_32_ADDR, P_REG_FI_D_31_00_ADDR, P_REG_UE_FFA_63_32_ADDR, P_REG_UE_FFA_31_00_ADDR, P_REG_UE_FFE_ADDR, P_REG_UE_FFD_127_96_ADDR, P_REG_UE_FFD_95_64_ADDR, P_REG_UE_FFD_63_32_ADDR, P_REG_UE_FFD_31_00_ADDR, P_REG_CE_FFA_63_32_ADDR, P_REG_CE_FFA_31_00_ADDR, P_REG_CE_FFE_ADDR, P_REG_CE_FFD_127_96_ADDR, P_REG_CE_FFD_95_64_ADDR, P_REG_CE_FFD_63_32_ADDR, P_REG_CE_FFD_31_00_ADDR, P_REG_CE_CNT_ADDR, P_REG_ECC_ON_OFF_ADDR, P_REG_ECC_EN_IRQ_ADDR, P_REG_ECC_STATUS_ADDR, P_REG_DUMMY_ADDR }; localparam P_REG_WRAC_ARRAY = { P_REG_FI_ECC_WRAC, P_REG_FI_D_127_96_WRAC, P_REG_FI_D_95_64_WRAC, P_REG_FI_D_63_32_WRAC, P_REG_FI_D_31_00_WRAC, P_REG_UE_FFA_63_32_WRAC, P_REG_UE_FFA_31_00_WRAC, P_REG_UE_FFE_WRAC, P_REG_UE_FFD_127_96_WRAC, P_REG_UE_FFD_95_64_WRAC, P_REG_UE_FFD_63_32_WRAC, P_REG_UE_FFD_31_00_WRAC, P_REG_CE_FFA_63_32_WRAC, P_REG_CE_FFA_31_00_WRAC, P_REG_CE_FFE_WRAC, P_REG_CE_FFD_127_96_WRAC, P_REG_CE_FFD_95_64_WRAC, P_REG_CE_FFD_63_32_WRAC, P_REG_CE_FFD_31_00_WRAC, P_REG_CE_CNT_WRAC, P_REG_ECC_ON_OFF_WRAC, P_REG_ECC_EN_IRQ_WRAC, P_REG_ECC_STATUS_WRAC, P_REG_DUMMY_WRAC }; localparam P_REG_WIDTH_ARRAY = { mask_width(P_REG_FI_ECC_MASK), mask_width(P_REG_FI_D_127_96_MASK), mask_width(P_REG_FI_D_95_64_MASK), mask_width(P_REG_FI_D_63_32_MASK), mask_width(P_REG_FI_D_31_00_MASK), mask_width(P_REG_UE_FFA_63_32_MASK), mask_width(P_REG_UE_FFA_31_00_MASK), mask_width(P_REG_UE_FFE_MASK), mask_width(P_REG_UE_FFD_127_96_MASK), mask_width(P_REG_UE_FFD_95_64_MASK), mask_width(P_REG_UE_FFD_63_32_MASK), mask_width(P_REG_UE_FFD_31_00_MASK), mask_width(P_REG_CE_FFA_63_32_MASK), mask_width(P_REG_CE_FFA_31_00_MASK), mask_width(P_REG_CE_FFE_MASK), mask_width(P_REG_CE_FFD_127_96_MASK), mask_width(P_REG_CE_FFD_95_64_MASK), mask_width(P_REG_CE_FFD_63_32_MASK), mask_width(P_REG_CE_FFD_31_00_MASK), mask_width(P_REG_CE_CNT_MASK), mask_width(P_REG_ECC_ON_OFF_MASK), mask_width(P_REG_ECC_EN_IRQ_MASK), mask_width(P_REG_ECC_STATUS_MASK), mask_width(P_REG_DUMMY_MASK) }; localparam P_REG_MASK_ARRAY = { P_REG_FI_ECC_MASK, P_REG_FI_D_127_96_MASK, P_REG_FI_D_95_64_MASK, P_REG_FI_D_63_32_MASK, P_REG_FI_D_31_00_MASK, P_REG_UE_FFA_63_32_MASK, P_REG_UE_FFA_31_00_MASK, P_REG_UE_FFE_MASK, P_REG_UE_FFD_127_96_MASK, P_REG_UE_FFD_95_64_MASK, P_REG_UE_FFD_63_32_MASK, P_REG_UE_FFD_31_00_MASK, P_REG_CE_FFA_63_32_MASK, P_REG_CE_FFA_31_00_MASK, P_REG_CE_FFE_MASK, P_REG_CE_FFD_127_96_MASK, P_REG_CE_FFD_95_64_MASK, P_REG_CE_FFD_63_32_MASK, P_REG_CE_FFD_31_00_MASK, P_REG_CE_CNT_MASK, P_REG_ECC_ON_OFF_MASK, P_REG_ECC_EN_IRQ_MASK, P_REG_ECC_STATUS_MASK, P_REG_DUMMY_MASK }; // END Auto-generated Register Mapping //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire [ P_NUM_REG_WIDTH-1:0 ] reg_data_sel; wire reg_data_write; wire [ C_S_AXI_CTRL_DATA_WIDTH-1:0 ] reg_data_in; wire [ C_S_AXI_CTRL_DATA_WIDTH*P_NUM_REG-1:0 ] reg_data_out; wire reset; wire arhandshake; wire rhandshake; wire awhandshake; wire bhandshake; reg wr_pending; reg rd_pending; reg arready_r; reg awready_r; reg [ C_S_AXI_ADDR_WIDTH-1:0 ] addr; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// assign reset = ~aresetn; assign arhandshake = s_axi_arvalid & s_axi_arready; assign awhandshake = s_axi_awvalid & s_axi_awready; assign rhandshake = s_axi_rvalid & s_axi_rready; assign bhandshake = s_axi_bvalid & s_axi_bready; assign s_axi_awready = awready_r; assign s_axi_arready = arready_r; always @(posedge aclk) begin if (reset) begin wr_pending <= 1'b0; end else begin wr_pending <= (awhandshake | wr_pending) & ~bhandshake; end end always @(posedge aclk) begin if (reset) begin rd_pending <= 1'b0; end else begin rd_pending <= (arhandshake | rd_pending) & ~rhandshake; end end always @(posedge aclk) begin if (reset | ~init_complete) begin awready_r <= 1'b0; end else begin awready_r <= s_axi_awvalid & ~rd_pending & ~wr_pending & ~awready_r; end end always @(posedge aclk) begin if (reset | ~init_complete) begin arready_r <= 1'b0; end else begin arready_r <= s_axi_arvalid & ~rd_pending & ~wr_pending & ~s_axi_awvalid & ~arready_r; end end always @(posedge aclk) begin if (awhandshake) begin addr <= s_axi_awaddr; end else if (arhandshake) begin addr <= s_axi_araddr; end end // Instantiate AXI4-Lite write channel module mig_7series_v4_0_axi_ctrl_write # ( .C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) , .C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) , .C_NUM_REG ( P_NUM_REG ) , .C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) , .C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) , .C_REG_WRAC_ARRAY ( P_REG_WRAC_ARRAY ) ) axi_ctrl_write_0 ( .clk ( aclk ) , .reset ( reset ) , .awvalid ( s_axi_awvalid ) , .awready ( s_axi_awready ) , .awaddr ( addr ) , .wvalid ( s_axi_wvalid ) , .wready ( s_axi_wready ) , .wdata ( s_axi_wdata ) , .bvalid ( s_axi_bvalid ) , .bready ( s_axi_bready ) , .bresp ( s_axi_bresp ) , .reg_data_sel ( reg_data_sel ) , .reg_data_write ( reg_data_write ) , .reg_data ( reg_data_in ) ); // Instantiate AXI4-Lite write channel module mig_7series_v4_0_axi_ctrl_read # ( .C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) , .C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) , .C_NUM_REG ( P_NUM_REG ) , .C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) , .C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) , .C_REG_RDAC_ARRAY ( P_REG_RDAC_ARRAY ) ) axi_ctrl_read_0 ( .clk ( aclk ) , .reset ( reset ) , .araddr ( addr ) , .rvalid ( s_axi_rvalid ) , .rready ( s_axi_rready ) , .rresp ( s_axi_rresp ) , .rdata ( s_axi_rdata ) , .pending ( rd_pending ) , .reg_bank_array ( reg_data_out ) ); mig_7series_v4_0_axi_ctrl_reg_bank # ( .C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) , .C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) , .C_DQ_WIDTH ( C_DQ_WIDTH ) , .C_ECC_CE_COUNTER_WIDTH ( C_ECC_CE_COUNTER_WIDTH ) , .C_ECC_ONOFF_RESET_VALUE ( C_ECC_ONOFF_RESET_VALUE ) , .C_ECC_TEST ( C_ECC_TEST ) , .C_ECC_WIDTH ( C_ECC_WIDTH ) , .C_MC_ERR_ADDR_WIDTH ( C_MC_ERR_ADDR_WIDTH ) , .C_MEM_ADDR_ORDER ( C_MEM_ADDR_ORDER ) , .C_BANK_WIDTH ( C_BANK_WIDTH ) , .C_ROW_WIDTH ( C_ROW_WIDTH ) , .C_COL_WIDTH ( C_COL_WIDTH ) , .C_NCK_PER_CLK ( C_NCK_PER_CLK ) , .C_NUM_REG ( P_NUM_REG ) , .C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) , .C_S_AXI_BASEADDR ( C_S_AXI_BASEADDR ) , // Register arrays .C_REG_RDAC_ARRAY ( P_REG_RDAC_ARRAY ) , .C_REG_WRAC_ARRAY ( P_REG_WRAC_ARRAY ) , .C_REG_INIT_ARRAY ( P_REG_INIT_ARRAY ) , .C_REG_MASK_ARRAY ( P_REG_MASK_ARRAY ) , .C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) , .C_REG_WIDTH_ARRAY ( P_REG_WIDTH_ARRAY ) , // Register Indices .C_REG_FI_ECC_INDX ( P_REG_FI_ECC_INDX ) , .C_REG_FI_D_127_96_INDX ( P_REG_FI_D_127_96_INDX ) , .C_REG_FI_D_95_64_INDX ( P_REG_FI_D_95_64_INDX ) , .C_REG_FI_D_63_32_INDX ( P_REG_FI_D_63_32_INDX ) , .C_REG_FI_D_31_00_INDX ( P_REG_FI_D_31_00_INDX ) , .C_REG_UE_FFA_63_32_INDX ( P_REG_UE_FFA_63_32_INDX ) , .C_REG_UE_FFA_31_00_INDX ( P_REG_UE_FFA_31_00_INDX ) , .C_REG_UE_FFE_INDX ( P_REG_UE_FFE_INDX ) , .C_REG_UE_FFD_127_96_INDX ( P_REG_UE_FFD_127_96_INDX ) , .C_REG_UE_FFD_95_64_INDX ( P_REG_UE_FFD_95_64_INDX ) , .C_REG_UE_FFD_63_32_INDX ( P_REG_UE_FFD_63_32_INDX ) , .C_REG_UE_FFD_31_00_INDX ( P_REG_UE_FFD_31_00_INDX ) , .C_REG_CE_FFA_63_32_INDX ( P_REG_CE_FFA_63_32_INDX ) , .C_REG_CE_FFA_31_00_INDX ( P_REG_CE_FFA_31_00_INDX ) , .C_REG_CE_FFE_INDX ( P_REG_CE_FFE_INDX ) , .C_REG_CE_FFD_127_96_INDX ( P_REG_CE_FFD_127_96_INDX ) , .C_REG_CE_FFD_95_64_INDX ( P_REG_CE_FFD_95_64_INDX ) , .C_REG_CE_FFD_63_32_INDX ( P_REG_CE_FFD_63_32_INDX ) , .C_REG_CE_FFD_31_00_INDX ( P_REG_CE_FFD_31_00_INDX ) , .C_REG_CE_CNT_INDX ( P_REG_CE_CNT_INDX ) , .C_REG_ECC_ON_OFF_INDX ( P_REG_ECC_ON_OFF_INDX ) , .C_REG_ECC_EN_IRQ_INDX ( P_REG_ECC_EN_IRQ_INDX ) , .C_REG_ECC_STATUS_INDX ( P_REG_ECC_STATUS_INDX ) , .C_REG_DUMMY_INDX ( P_REG_DUMMY_INDX ) ) axi_ctrl_reg_bank_0 ( .clk ( aclk ) , .reset ( reset ) , .reg_data_sel ( reg_data_sel ) , .reg_data_write ( reg_data_write ) , .reg_data_in ( reg_data_in ) , .reg_data_out ( reg_data_out ) , .interrupt ( interrupt ) , .ecc_single ( ecc_single ) , .ecc_multiple ( ecc_multiple ) , .ecc_err_addr ( ecc_err_addr ) , .app_correct_en ( app_correct_en ) , .dfi_rddata ( dfi_rddata ) , .fi_xor_we ( fi_xor_we ) , .fi_xor_wrdata ( fi_xor_wrdata ) ); endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_ctrl_write.v // // Description: // // Specifications: // // Structure: // axi_ctrl_top // axi_ctrl_write // axi_ctrl_addr_decode // axi_ctrl_read // axi_ctrl_addr_decode // axi_ctrl_reg_bank // axi_ctrl_reg // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_ctrl_write # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AXI-4-Lite address bus parameter integer C_ADDR_WIDTH = 32, // Width of AXI-4-Lite data buses parameter integer C_DATA_WIDTH = 32, // Number of Registers parameter integer C_NUM_REG = 5, parameter integer C_NUM_REG_WIDTH = 3, // Number of Registers parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF, parameter C_REG_WRAC_ARRAY = 5'b11111 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI4-Lite Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Read Address Ports input wire awvalid , input wire awready , input wire [C_ADDR_WIDTH-1:0] awaddr , // Slave Interface Read Data Ports input wire wvalid , output wire wready , input wire [C_DATA_WIDTH-1:0] wdata , output wire bvalid , input wire bready , output wire [1:0] bresp , // Internal Signals output wire [C_NUM_REG_WIDTH-1:0] reg_data_sel , output wire reg_data_write , output wire [C_DATA_WIDTH-1:0] reg_data ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire awhandshake; wire whandshake; reg whandshake_d1; wire bhandshake; wire [C_NUM_REG_WIDTH-1:0] reg_decode_num; reg awready_i; reg wready_i; reg bvalid_i; reg [C_DATA_WIDTH-1:0] data; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // Handshake signals assign awhandshake = awvalid & awready; assign whandshake = wvalid & wready; assign bhandshake = bvalid & bready; mig_7series_v4_0_axi_ctrl_addr_decode # ( .C_ADDR_WIDTH ( C_ADDR_WIDTH ) , .C_NUM_REG ( C_NUM_REG ) , .C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) , .C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) , .C_REG_RDWR_ARRAY ( C_REG_WRAC_ARRAY ) ) axi_ctrl_addr_decode_0 ( .axaddr ( awaddr ) , .reg_decode_num ( reg_decode_num ) ); // wchannel only accepts data after aw handshake assign wready = wready_i; always @(posedge clk) begin if (reset) begin wready_i <= 1'b0; end else begin wready_i <= (awhandshake | wready_i) & ~whandshake; end end // Data is registered but not latched (like awaddr) since it used a cycle later always @(posedge clk) begin data <= wdata; end // bresponse is sent after successful w handshake assign bvalid = bvalid_i; assign bresp = 2'b0; // Okay always @(posedge clk) begin if (reset) begin bvalid_i <= 1'b0; end else begin bvalid_i <= (whandshake | bvalid_i) & ~bhandshake; end end // Assign internal signals assign reg_data = data; assign reg_data_write = whandshake_d1; assign reg_data_sel = reg_decode_num; always @(posedge clk) begin whandshake_d1 <= whandshake; end endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc.v // // Description: // To handle AXI4 transactions to external memory on Virtex-6 architectures // requires a bridge to convert the AXI4 transactions to the memory // controller(MC) user interface. The MC user interface has bidirectional // data path and supports data width of 256/128/64/32 bits. // The bridge is designed to allow AXI4 IP masters to communicate with // the MC user interface. // // // Specifications: // AXI4 Slave Side: // Configurable data width of 32, 64, 128, 256 // Read acceptance depth is: // Write acceptance depth is: // // Structure: // axi_mc // axi_register_slice_d1 // USE_UPSIZER // upsizer_d2 // axi_register_slice_d3 // WRITE_BUNDLE // axi_mc_aw_channel_0 // axi_mc_cmd_translator_0 // rd_cmd_fsm_0 // axi_mc_w_channel_0 // axi_mc_b_channel_0 // READ_BUNDLE // axi_mc_ar_channel_0 // axi_mc_cmd_translator_0 // rd_cmd_fsm_0 // axi_mc_r_channel_0 // USE_CMD_ARBITER // axi_mc_cmd_arbiter_0 // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // FPGA Family. Current version: virtex6. parameter C_FAMILY = "virtex6", // Width of all master and slave ID signals. // Range: >= 1. parameter integer C_S_AXI_ID_WIDTH = 4, // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and // M_AXI_ARADDR for all SI/MI slots. // Range: 32. parameter integer C_S_AXI_ADDR_WIDTH = 30, // Width of WDATA and RDATA on SI slot. // Must be <= C_MC_DATA_WIDTH // Range: 32, 64, 128, 256. parameter integer C_S_AXI_DATA_WIDTH = 32, // Memory controller address width, range 28-32 parameter integer C_MC_ADDR_WIDTH = 30, // Width of wr_data and rd_data. // Range: 32, 64, 128, 256. parameter integer C_MC_DATA_WIDTH = 32, // Memory controller burst mode, // values "8", "4" & "OTF" parameter C_MC_BURST_MODE = "8", // Number of memory clocks per fabric clock // = 2 for DDR2 or low frequency designs // = 4 for DDR3 or high frequency designs parameter C_MC_nCK_PER_CLK = 2, // Indicates whether to instatiate upsizer // Range: 0, 1 parameter integer C_S_AXI_SUPPORTS_NARROW_BURST = 1, // C_S_AXI_REG_EN0[00] = Reserved // C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE parameter C_S_AXI_REG_EN0 = 20'h00000, // Instatiates register slices after the upsizer. // The type of register is specified for each channel // in a vector. 4 bits per channel are used. // C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE // Possible values for each channel are: // // 0 => BYPASS = The channel is just wired through the // module. // 1 => FWD = The master VALID and payload signals // are registrated. // 2 => REV = The slave ready signal is registrated // 3 => FWD_REV = Both FWD and REV // 4 => SLAVE_FWD = All slave side signals and master // VALID and payload are registrated. // 5 => SLAVE_RDY = All slave side signals and master // READY are registrated. // 6 => INPUTS = Slave and Master side inputs are // registrated. // 7 => ADDRESS = Optimized for address channel // A A // RRBWW parameter C_S_AXI_REG_EN1 = 20'h00000, parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG", // Indicates the Arbitration // Allowed values - "TDM", "ROUND_ROBIN", // "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT" parameter C_ECC = "OFF" // Output RMW if ECC is on. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire aclk , input wire aresetn , // Slave Interface Write Address Ports input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid , input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr , input wire [7:0] s_axi_awlen , input wire [2:0] s_axi_awsize , input wire [1:0] s_axi_awburst , input wire [0:0] s_axi_awlock , input wire [3:0] s_axi_awcache , input wire [2:0] s_axi_awprot , input wire [3:0] s_axi_awqos , input wire s_axi_awvalid , output wire s_axi_awready , // Slave Interface Write Data Ports input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata , input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb , input wire s_axi_wlast , input wire s_axi_wvalid , output wire s_axi_wready , // Slave Interface Write Response Ports output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid , output wire [1:0] s_axi_bresp , output wire s_axi_bvalid , input wire s_axi_bready , // Slave Interface Read Address Ports input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid , input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr , input wire [7:0] s_axi_arlen , input wire [2:0] s_axi_arsize , input wire [1:0] s_axi_arburst , input wire [0:0] s_axi_arlock , input wire [3:0] s_axi_arcache , input wire [2:0] s_axi_arprot , input wire [3:0] s_axi_arqos , input wire s_axi_arvalid , output wire s_axi_arready , // Slave Interface Read Data Ports output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid , output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata , output wire [1:0] s_axi_rresp , output wire s_axi_rlast , output wire s_axi_rvalid , input wire s_axi_rready , // MC Master Interface //CMD PORT output wire mc_app_en , output wire [2:0] mc_app_cmd , output wire mc_app_sz , output wire [C_MC_ADDR_WIDTH-1:0] mc_app_addr , output wire mc_app_hi_pri , input wire mc_app_rdy , input wire mc_init_complete , //DATA PORT output wire mc_app_wdf_wren , output wire [C_MC_DATA_WIDTH/8-1:0] mc_app_wdf_mask , output wire [C_MC_DATA_WIDTH-1:0] mc_app_wdf_data , output wire mc_app_wdf_end , input wire mc_app_wdf_rdy , input wire mc_app_rd_valid , input wire [C_MC_DATA_WIDTH-1:0] mc_app_rd_data , input wire mc_app_rd_end , input wire [2*C_MC_nCK_PER_CLK-1:0] mc_app_ecc_multiple_err ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer P_AXSIZE = (C_MC_DATA_WIDTH == 32) ? 3'd2 : (C_MC_DATA_WIDTH == 64) ? 3'd3 : (C_MC_DATA_WIDTH == 128)? 3'd4 : (C_MC_DATA_WIDTH == 256)? 3'd5 : (C_MC_DATA_WIDTH == 512)? 3'd6 : 3'd7; // C_D?_REG_CONFIG_*: // 0 => BYPASS = The channel is just wired through the module. // 1 => FWD = The master VALID and payload signals are registrated. // 2 => REV = The slave ready signal is registrated // 3 => FWD_REV = Both FWD and REV // 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated. // 5 => SLAVE_RDY = All slave side signals and master READY are registrated. // 6 => INPUTS = Slave and Master side inputs are registrated. localparam integer P_D1_REG_CONFIG_AW = 0; localparam integer P_D1_REG_CONFIG_W = 0; localparam integer P_D1_REG_CONFIG_B = 0; localparam integer P_D1_REG_CONFIG_AR = 0; localparam integer P_D1_REG_CONFIG_R = 0; // Upsizer localparam integer P_USE_UPSIZER = ( C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH) ? 1'b1 : C_S_AXI_SUPPORTS_NARROW_BURST; localparam integer P_D2_REG_CONFIG_AW = P_USE_UPSIZER ? 1 : C_S_AXI_REG_EN0[8]; localparam integer P_D2_REG_CONFIG_W = C_S_AXI_REG_EN0[9]; localparam integer P_D2_REG_CONFIG_AR = P_USE_UPSIZER ? 1 : C_S_AXI_REG_EN0[10]; localparam integer P_D2_REG_CONFIG_R = C_S_AXI_REG_EN0[11]; // localparam integer P_D3_REG_CONFIG_AW = (C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH)? // (C_S_AXI_REG_EN0[4] ? 1 : C_S_AXI_REG_EN1[ 0 +: 4]) : 1; // localparam integer P_D3_REG_CONFIG_W = C_S_AXI_REG_EN0[5] ? 2 : C_S_AXI_REG_EN1[ 4 +: 4]; // localparam integer P_D3_REG_CONFIG_B = C_S_AXI_REG_EN0[6] ? 7 : C_S_AXI_REG_EN1[ 8 +: 4]; // // AR channel must always have a register slice. // localparam integer P_D3_REG_CONFIG_AR = (C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH)? 0 : 1; // localparam integer P_D3_REG_CONFIG_R = C_S_AXI_REG_EN0[7] ? 6 : C_S_AXI_REG_EN1[16 +: 4]; localparam integer P_D3_REG_CONFIG_AW = 0; localparam integer P_D3_REG_CONFIG_W = 0; localparam integer P_D3_REG_CONFIG_B = 0; localparam integer P_D3_REG_CONFIG_AR = 0; localparam integer P_D3_REG_CONFIG_R = 0; localparam integer P_UPSIZER_PACKING_LEVEL = 2; localparam integer P_SUPPORTS_USER_SIGNALS = 0; // Set this parameter to 1 if data can be returned out of order localparam integer P_SINGLE_THREAD = 0; // BURST LENGTH // In 4:1 mode the only burst mode that is supported is BL8. // The BL8 in 4:1 mode will be treated as BL4 by the shim. // In 2:1 mode both the burst modes BL4 & BL8 are supported. localparam integer C_MC_BURST_LEN = (C_MC_nCK_PER_CLK == 4) ? 1: (C_MC_BURST_MODE == "4") ? 1 : 2; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// // AXI Slave signals from Reg Slice, Upsizer, at MC data width, internal signals //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // First reg slice slave side output/inputs wire [C_S_AXI_ID_WIDTH-1:0] awid_d1 ; wire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d1 ; wire [7:0] awlen_d1 ; wire [2:0] awsize_d1 ; wire [1:0] awburst_d1 ; wire [1:0] awlock_d1 ; wire [3:0] awcache_d1 ; wire [2:0] awprot_d1 ; wire [3:0] awqos_d1 ; wire awvalid_d1 ; wire awready_d1 ; wire [C_S_AXI_DATA_WIDTH-1:0] wdata_d1 ; wire [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_d1 ; wire wlast_d1 ; wire wvalid_d1 ; wire wready_d1 ; wire [C_S_AXI_ID_WIDTH-1:0] bid_d1 ; wire [1:0] bresp_d1 ; wire bvalid_d1 ; wire bready_d1 ; wire [C_S_AXI_ID_WIDTH-1:0] arid_d1 ; wire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d1 ; wire [7:0] arlen_d1 ; wire [2:0] arsize_d1 ; wire [1:0] arburst_d1 ; wire [1:0] arlock_d1 ; wire [3:0] arcache_d1 ; wire [2:0] arprot_d1 ; wire [3:0] arqos_d1 ; wire arvalid_d1 ; wire arready_d1 ; wire [C_S_AXI_ID_WIDTH-1:0] rid_d1 ; wire [C_S_AXI_DATA_WIDTH-1:0] rdata_d1 ; wire [1:0] rresp_d1 ; wire rlast_d1 ; wire rvalid_d1 ; wire rready_d1 ; // Upsizer slave side outputs/inputs wire [C_S_AXI_ID_WIDTH-1:0] awid_d2 ; wire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d2 ; wire [7:0] awlen_d2 ; wire [2:0] awsize_d2 ; wire [1:0] awburst_d2 ; wire [1:0] awlock_d2 ; wire [3:0] awcache_d2 ; wire [2:0] awprot_d2 ; wire [3:0] awqos_d2 ; wire awvalid_d2 ; wire awready_d2 ; wire [C_MC_DATA_WIDTH-1:0] wdata_d2 ; wire [C_MC_DATA_WIDTH/8-1:0] wstrb_d2 ; wire wlast_d2 ; wire wvalid_d2 ; wire wready_d2 ; wire [C_S_AXI_ID_WIDTH-1:0] bid_d2 ; wire [1:0] bresp_d2 ; wire bvalid_d2 ; wire bready_d2 ; wire [C_S_AXI_ID_WIDTH-1:0] arid_d2 ; wire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d2 ; wire [7:0] arlen_d2 ; wire [2:0] arsize_d2 ; wire [1:0] arburst_d2 ; wire [1:0] arlock_d2 ; wire [3:0] arcache_d2 ; wire [2:0] arprot_d2 ; wire [3:0] arqos_d2 ; wire arvalid_d2 ; wire arready_d2 ; wire [C_S_AXI_ID_WIDTH-1:0] rid_d2 ; wire [C_MC_DATA_WIDTH-1:0] rdata_d2 ; wire [1:0] rresp_d2 ; wire rlast_d2 ; wire rvalid_d2 ; wire rready_d2 ; // Registe Slice 2 slave side outputs/inputs wire [C_S_AXI_ID_WIDTH-1:0] awid_d3 ; wire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d3 ; wire [7:0] awlen_d3 ; // AxSIZE hardcoded with static value // wire [2:0] awsize_d3 ; wire [1:0] awburst_d3 ; wire [1:0] awlock_d3 ; wire [3:0] awcache_d3 ; wire [2:0] awprot_d3 ; wire [3:0] awqos_d3 ; wire awvalid_d3 ; wire awready_d3 ; wire [C_MC_DATA_WIDTH-1:0] wdata_d3 ; wire [C_MC_DATA_WIDTH/8-1:0] wstrb_d3 ; wire wlast_d3 ; wire wvalid_d3 ; wire wready_d3 ; wire [C_S_AXI_ID_WIDTH-1:0] bid_d3 ; wire [1:0] bresp_d3 ; wire bvalid_d3 ; wire bready_d3 ; wire [C_S_AXI_ID_WIDTH-1:0] arid_d3 ; wire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d3 ; wire [7:0] arlen_d3 ; // AxSIZE hardcoded with static value // wire [2:0] arsize_d3 ; wire [1:0] arburst_d3 ; wire [1:0] arlock_d3 ; wire [3:0] arcache_d3 ; wire [2:0] arprot_d3 ; wire [3:0] arqos_d3 ; wire arvalid_d3 ; wire arready_d3 ; wire [C_S_AXI_ID_WIDTH-1:0] rid_d3 ; wire [C_MC_DATA_WIDTH-1:0] rdata_d3 ; wire [1:0] rresp_d3 ; wire rlast_d3 ; wire rvalid_d3 ; wire rready_d3 ; // AW/AR module outputs to arbiter. wire wr_cmd_en ; wire wr_cmd_en_last ; wire [2:0] wr_cmd_instr ; wire [C_MC_ADDR_WIDTH-1:0] wr_cmd_byte_addr ; wire wr_cmd_full ; wire rd_cmd_en ; wire rd_cmd_en_last ; wire [2:0] rd_cmd_instr ; wire [C_MC_ADDR_WIDTH-1:0] rd_cmd_byte_addr ; wire rd_cmd_full ; wire aresetn_int ; wire cmd_wr_bytes; reg areset_d1; reg mc_init_complete_r; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// assign aresetn_int = aresetn & mc_init_complete_r; always @(posedge aclk) areset_d1 <= ~aresetn_int; always @(posedge aclk) mc_init_complete_r <= mc_init_complete ; mig_7series_v4_0_ddr_axi_register_slice # ( .C_FAMILY ( C_FAMILY ) , .C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) , .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) , .C_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) , .C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) , .C_AXI_AWUSER_WIDTH ( 1 ) , .C_AXI_ARUSER_WIDTH ( 1 ) , .C_AXI_WUSER_WIDTH ( 1 ) , .C_AXI_RUSER_WIDTH ( 1 ) , .C_AXI_BUSER_WIDTH ( 1 ) , .C_REG_CONFIG_AW ( P_D1_REG_CONFIG_AW ) , .C_REG_CONFIG_W ( P_D1_REG_CONFIG_W ) , .C_REG_CONFIG_B ( P_D1_REG_CONFIG_B ) , .C_REG_CONFIG_AR ( P_D1_REG_CONFIG_AR ) , .C_REG_CONFIG_R ( P_D1_REG_CONFIG_R ) ) axi_register_slice_d1 ( .ACLK ( aclk ) , .ARESETN ( aresetn_int ) , .S_AXI_AWID ( s_axi_awid ) , .S_AXI_AWADDR ( s_axi_awaddr ) , .S_AXI_AWLEN ( s_axi_awlen ) , .S_AXI_AWSIZE ( s_axi_awsize ) , .S_AXI_AWBURST ( s_axi_awburst ) , .S_AXI_AWLOCK ( {1'b0, s_axi_awlock}) , .S_AXI_AWCACHE ( s_axi_awcache ) , .S_AXI_AWPROT ( s_axi_awprot ) , .S_AXI_AWREGION( 4'b0 ) , .S_AXI_AWQOS ( s_axi_awqos ) , .S_AXI_AWUSER ( 1'b0 ) , .S_AXI_AWVALID ( s_axi_awvalid ) , .S_AXI_AWREADY ( s_axi_awready ) , .S_AXI_WDATA ( s_axi_wdata ) , .S_AXI_WID ( {C_S_AXI_ID_WIDTH{1'b0}} ) , .S_AXI_WSTRB ( s_axi_wstrb ) , .S_AXI_WLAST ( s_axi_wlast ) , .S_AXI_WUSER ( 1'b0 ) , .S_AXI_WVALID ( s_axi_wvalid ) , .S_AXI_WREADY ( s_axi_wready ) , .S_AXI_BID ( s_axi_bid ) , .S_AXI_BRESP ( s_axi_bresp ) , .S_AXI_BUSER ( ) , .S_AXI_BVALID ( s_axi_bvalid ) , .S_AXI_BREADY ( s_axi_bready ) , .S_AXI_ARID ( s_axi_arid ) , .S_AXI_ARADDR ( s_axi_araddr ) , .S_AXI_ARLEN ( s_axi_arlen ) , .S_AXI_ARSIZE ( s_axi_arsize ) , .S_AXI_ARBURST ( s_axi_arburst ) , .S_AXI_ARLOCK ( {1'b0, s_axi_arlock}) , .S_AXI_ARCACHE ( s_axi_arcache ) , .S_AXI_ARPROT ( s_axi_arprot ) , .S_AXI_ARREGION( 4'b0 ) , .S_AXI_ARQOS ( s_axi_arqos ) , .S_AXI_ARUSER ( 1'b0 ) , .S_AXI_ARVALID ( s_axi_arvalid ) , .S_AXI_ARREADY ( s_axi_arready ) , .S_AXI_RID ( s_axi_rid ) , .S_AXI_RDATA ( s_axi_rdata ) , .S_AXI_RRESP ( s_axi_rresp ) , .S_AXI_RLAST ( s_axi_rlast ) , .S_AXI_RUSER ( ) , .S_AXI_RVALID ( s_axi_rvalid ) , .S_AXI_RREADY ( s_axi_rready ) , .M_AXI_AWID ( awid_d1 ) , .M_AXI_AWADDR ( awaddr_d1 ) , .M_AXI_AWLEN ( awlen_d1 ) , .M_AXI_AWSIZE ( awsize_d1 ) , .M_AXI_AWBURST ( awburst_d1 ) , .M_AXI_AWLOCK ( awlock_d1 ) , .M_AXI_AWCACHE ( awcache_d1 ) , .M_AXI_AWREGION( ) , .M_AXI_AWPROT ( awprot_d1 ) , .M_AXI_AWQOS ( awqos_d1 ) , .M_AXI_AWUSER ( ) , .M_AXI_AWVALID ( awvalid_d1 ) , .M_AXI_AWREADY ( awready_d1 ) , .M_AXI_WID ( ) , .M_AXI_WDATA ( wdata_d1 ) , .M_AXI_WSTRB ( wstrb_d1 ) , .M_AXI_WLAST ( wlast_d1 ) , .M_AXI_WUSER ( ) , .M_AXI_WVALID ( wvalid_d1 ) , .M_AXI_WREADY ( wready_d1 ) , .M_AXI_BID ( bid_d1 ) , .M_AXI_BRESP ( bresp_d1 ) , .M_AXI_BUSER ( 1'b0 ) , .M_AXI_BVALID ( bvalid_d1 ) , .M_AXI_BREADY ( bready_d1 ) , .M_AXI_ARID ( arid_d1 ) , .M_AXI_ARADDR ( araddr_d1 ) , .M_AXI_ARLEN ( arlen_d1 ) , .M_AXI_ARSIZE ( arsize_d1 ) , .M_AXI_ARBURST ( arburst_d1 ) , .M_AXI_ARLOCK ( arlock_d1 ) , .M_AXI_ARCACHE ( arcache_d1 ) , .M_AXI_ARPROT ( arprot_d1 ) , .M_AXI_ARREGION( ) , .M_AXI_ARQOS ( arqos_d1 ) , .M_AXI_ARUSER ( ) , .M_AXI_ARVALID ( arvalid_d1 ) , .M_AXI_ARREADY ( arready_d1 ) , .M_AXI_RID ( rid_d1 ) , .M_AXI_RDATA ( rdata_d1 ) , .M_AXI_RRESP ( rresp_d1 ) , .M_AXI_RLAST ( rlast_d1 ) , .M_AXI_RUSER ( 1'b0 ) , .M_AXI_RVALID ( rvalid_d1 ) , .M_AXI_RREADY ( rready_d1 ) ); generate if (P_USE_UPSIZER) begin : USE_UPSIZER mig_7series_v4_0_ddr_axi_upsizer # ( .C_FAMILY ( C_FAMILY ) , .C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) , .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) , .C_M_AXI_DATA_WIDTH ( C_MC_DATA_WIDTH ) , .C_M_AXI_AW_REGISTER ( P_D2_REG_CONFIG_AW ) , .C_M_AXI_W_REGISTER ( P_D2_REG_CONFIG_W ) , .C_M_AXI_AR_REGISTER ( P_D2_REG_CONFIG_AR ) , .C_S_AXI_R_REGISTER ( P_D2_REG_CONFIG_R ) , .C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) , .C_AXI_AWUSER_WIDTH ( 1 ) , .C_AXI_ARUSER_WIDTH ( 1 ) , .C_AXI_WUSER_WIDTH ( 1 ) , .C_AXI_RUSER_WIDTH ( 1 ) , .C_AXI_BUSER_WIDTH ( 1 ) , .C_AXI_SUPPORTS_WRITE ( 1 ) , .C_AXI_SUPPORTS_READ ( 1 ) , .C_PACKING_LEVEL ( P_UPSIZER_PACKING_LEVEL ) , .C_SUPPORT_BURSTS ( 1 ) , .C_SINGLE_THREAD ( P_SINGLE_THREAD ) ) upsizer_d2 ( .ACLK ( aclk ) , .ARESETN ( aresetn_int ) , .S_AXI_AWID ( awid_d1 ) , .S_AXI_AWADDR ( awaddr_d1 ) , .S_AXI_AWLEN ( awlen_d1 ) , .S_AXI_AWSIZE ( awsize_d1 ) , .S_AXI_AWBURST ( awburst_d1 ) , .S_AXI_AWLOCK ( awlock_d1 ) , .S_AXI_AWCACHE ( awcache_d1 ) , .S_AXI_AWPROT ( awprot_d1 ) , .S_AXI_AWREGION( 4'b0 ) , .S_AXI_AWQOS ( awqos_d1 ) , .S_AXI_AWUSER ( 1'b0 ) , .S_AXI_AWVALID ( awvalid_d1 ) , .S_AXI_AWREADY ( awready_d1 ) , .S_AXI_WDATA ( wdata_d1 ) , .S_AXI_WSTRB ( wstrb_d1 ) , .S_AXI_WLAST ( wlast_d1 ) , .S_AXI_WUSER ( 1'b0 ) , .S_AXI_WVALID ( wvalid_d1 ) , .S_AXI_WREADY ( wready_d1 ) , .S_AXI_BID ( bid_d1 ) , .S_AXI_BRESP ( bresp_d1 ) , .S_AXI_BUSER ( ) , .S_AXI_BVALID ( bvalid_d1 ) , .S_AXI_BREADY ( bready_d1 ) , .S_AXI_ARID ( arid_d1 ) , .S_AXI_ARADDR ( araddr_d1 ) , .S_AXI_ARLEN ( arlen_d1 ) , .S_AXI_ARSIZE ( arsize_d1 ) , .S_AXI_ARBURST ( arburst_d1 ) , .S_AXI_ARLOCK ( arlock_d1 ) , .S_AXI_ARCACHE ( arcache_d1 ) , .S_AXI_ARPROT ( arprot_d1 ) , .S_AXI_ARREGION( 4'b0 ) , .S_AXI_ARQOS ( arqos_d1 ) , .S_AXI_ARUSER ( 1'b0 ) , .S_AXI_ARVALID ( arvalid_d1 ) , .S_AXI_ARREADY ( arready_d1 ) , .S_AXI_RID ( rid_d1 ) , .S_AXI_RDATA ( rdata_d1 ) , .S_AXI_RRESP ( rresp_d1 ) , .S_AXI_RLAST ( rlast_d1 ) , .S_AXI_RUSER ( ) , .S_AXI_RVALID ( rvalid_d1 ) , .S_AXI_RREADY ( rready_d1 ) , .M_AXI_AWID ( awid_d2 ) , .M_AXI_AWADDR ( awaddr_d2 ) , .M_AXI_AWLEN ( awlen_d2 ) , .M_AXI_AWSIZE ( awsize_d2 ) , .M_AXI_AWBURST ( awburst_d2 ) , .M_AXI_AWLOCK ( awlock_d2 ) , .M_AXI_AWCACHE ( awcache_d2 ) , .M_AXI_AWPROT ( awprot_d2 ) , .M_AXI_AWREGION( ) , .M_AXI_AWQOS ( awqos_d2 ) , .M_AXI_AWUSER ( ) , .M_AXI_AWVALID ( awvalid_d2 ) , .M_AXI_AWREADY ( awready_d2 ) , .M_AXI_WDATA ( wdata_d2 ) , .M_AXI_WSTRB ( wstrb_d2 ) , .M_AXI_WLAST ( wlast_d2 ) , .M_AXI_WUSER ( ) , .M_AXI_WVALID ( wvalid_d2 ) , .M_AXI_WREADY ( wready_d2 ) , .M_AXI_BID ( bid_d2 ) , .M_AXI_BRESP ( bresp_d2 ) , .M_AXI_BUSER ( 1'b0 ) , .M_AXI_BVALID ( bvalid_d2 ) , .M_AXI_BREADY ( bready_d2 ) , .M_AXI_ARID ( arid_d2 ) , .M_AXI_ARADDR ( araddr_d2 ) , .M_AXI_ARLEN ( arlen_d2 ) , .M_AXI_ARSIZE ( arsize_d2 ) , .M_AXI_ARBURST ( arburst_d2 ) , .M_AXI_ARLOCK ( arlock_d2 ) , .M_AXI_ARCACHE ( arcache_d2 ) , .M_AXI_ARPROT ( arprot_d2 ) , .M_AXI_ARREGION( ) , .M_AXI_ARQOS ( arqos_d2 ) , .M_AXI_ARUSER ( ) , .M_AXI_ARVALID ( arvalid_d2 ) , .M_AXI_ARREADY ( arready_d2 ) , .M_AXI_RID ( rid_d2 ) , .M_AXI_RDATA ( rdata_d2 ) , .M_AXI_RRESP ( rresp_d2 ) , .M_AXI_RLAST ( rlast_d2 ) , .M_AXI_RUSER ( 1'b0 ) , .M_AXI_RVALID ( rvalid_d2 ) , .M_AXI_RREADY ( rready_d2 ) ); end else begin : NO_UPSIZER assign awid_d2 = awid_d1 ; assign awaddr_d2 = awaddr_d1 ; assign awlen_d2 = awlen_d1 ; assign awsize_d2 = awsize_d1 ; assign awburst_d2 = awburst_d1 ; assign awlock_d2 = awlock_d1 ; assign awcache_d2 = awcache_d1 ; assign awprot_d2 = awprot_d1 ; assign awqos_d2 = awqos_d1 ; assign awvalid_d2 = awvalid_d1 ; assign awready_d1 = awready_d2 ; assign wdata_d2 = wdata_d1 ; assign wstrb_d2 = wstrb_d1 ; assign wlast_d2 = wlast_d1 ; assign wvalid_d2 = wvalid_d1 ; assign wready_d1 = wready_d2 ; assign bid_d1 = bid_d2 ; assign bresp_d1 = bresp_d2 ; assign bvalid_d1 = bvalid_d2 ; assign bready_d2 = bready_d1 ; assign arid_d2 = arid_d1 ; assign araddr_d2 = araddr_d1 ; assign arlen_d2 = arlen_d1 ; assign arsize_d2 = arsize_d1 ; assign arburst_d2 = arburst_d1 ; assign arlock_d2 = arlock_d1 ; assign arcache_d2 = arcache_d1 ; assign arprot_d2 = arprot_d1 ; assign arqos_d2 = arqos_d1 ; assign arvalid_d2 = arvalid_d1 ; assign arready_d1 = arready_d2 ; assign rid_d1 = rid_d2 ; assign rdata_d1 = rdata_d2 ; assign rresp_d1 = rresp_d2 ; assign rlast_d1 = rlast_d2 ; assign rvalid_d1 = rvalid_d2 ; assign rready_d2 = rready_d1 ; end endgenerate mig_7series_v4_0_ddr_axi_register_slice # ( .C_FAMILY ( C_FAMILY ) , .C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) , .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) , .C_AXI_DATA_WIDTH ( C_MC_DATA_WIDTH ) , .C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) , .C_AXI_AWUSER_WIDTH ( 1 ) , .C_AXI_ARUSER_WIDTH ( 1 ) , .C_AXI_WUSER_WIDTH ( 1 ) , .C_AXI_RUSER_WIDTH ( 1 ) , .C_AXI_BUSER_WIDTH ( 1 ) , .C_REG_CONFIG_AW ( P_D3_REG_CONFIG_AW ) , .C_REG_CONFIG_W ( P_D3_REG_CONFIG_W ) , .C_REG_CONFIG_B ( P_D3_REG_CONFIG_B ) , .C_REG_CONFIG_AR ( P_D3_REG_CONFIG_AR ) , .C_REG_CONFIG_R ( P_D3_REG_CONFIG_R ) ) axi_register_slice_d3 ( .ACLK ( aclk ) , .ARESETN ( aresetn_int ) , .S_AXI_AWID ( awid_d2 ) , .S_AXI_AWADDR ( awaddr_d2 ) , .S_AXI_AWLEN ( awlen_d2 ) , .S_AXI_AWSIZE ( P_AXSIZE[2:0] ) , .S_AXI_AWBURST ( awburst_d2 ) , .S_AXI_AWLOCK ( awlock_d2 ) , .S_AXI_AWCACHE ( awcache_d2 ) , .S_AXI_AWPROT ( awprot_d2 ) , .S_AXI_AWREGION( 4'b0 ) , .S_AXI_AWQOS ( awqos_d2 ) , .S_AXI_AWUSER ( 1'b0 ) , .S_AXI_AWVALID ( awvalid_d2 ) , .S_AXI_AWREADY ( awready_d2 ) , .S_AXI_WID ( {C_S_AXI_ID_WIDTH{1'b0}} ) , .S_AXI_WDATA ( wdata_d2 ) , .S_AXI_WSTRB ( wstrb_d2 ) , .S_AXI_WLAST ( wlast_d2 ) , .S_AXI_WUSER ( 1'b0 ) , .S_AXI_WVALID ( wvalid_d2 ) , .S_AXI_WREADY ( wready_d2 ) , .S_AXI_BID ( bid_d2 ) , .S_AXI_BRESP ( bresp_d2 ) , .S_AXI_BUSER ( ) , .S_AXI_BVALID ( bvalid_d2 ) , .S_AXI_BREADY ( bready_d2 ) , .S_AXI_ARID ( arid_d2 ) , .S_AXI_ARADDR ( araddr_d2 ) , .S_AXI_ARLEN ( arlen_d2 ) , .S_AXI_ARSIZE ( P_AXSIZE[2:0] ) , .S_AXI_ARBURST ( arburst_d2 ) , .S_AXI_ARLOCK ( arlock_d2 ) , .S_AXI_ARCACHE ( arcache_d2 ) , .S_AXI_ARPROT ( arprot_d2 ) , .S_AXI_ARREGION( 4'b0 ) , .S_AXI_ARQOS ( arqos_d2 ) , .S_AXI_ARUSER ( 1'b0 ) , .S_AXI_ARVALID ( arvalid_d2 ) , .S_AXI_ARREADY ( arready_d2 ) , .S_AXI_RID ( rid_d2 ) , .S_AXI_RDATA ( rdata_d2 ) , .S_AXI_RRESP ( rresp_d2 ) , .S_AXI_RLAST ( rlast_d2 ) , .S_AXI_RUSER ( ) , .S_AXI_RVALID ( rvalid_d2 ) , .S_AXI_RREADY ( rready_d2 ) , .M_AXI_AWID ( awid_d3 ) , .M_AXI_AWADDR ( awaddr_d3 ) , .M_AXI_AWLEN ( awlen_d3 ) , // AxSIZE hardcoded with static value // .M_AXI_AWSIZE ( awsize_d3 ) , .M_AXI_AWSIZE ( ) , .M_AXI_AWBURST ( awburst_d3 ) , .M_AXI_AWLOCK ( awlock_d3 ) , .M_AXI_AWCACHE ( awcache_d3 ) , .M_AXI_AWPROT ( awprot_d3 ) , .M_AXI_AWREGION( ) , .M_AXI_AWQOS ( awqos_d3 ) , .M_AXI_AWUSER ( ) , .M_AXI_AWVALID ( awvalid_d3 ) , .M_AXI_AWREADY ( awready_d3 ) , .M_AXI_WID ( ) , .M_AXI_WDATA ( wdata_d3 ) , .M_AXI_WSTRB ( wstrb_d3 ) , .M_AXI_WLAST ( wlast_d3 ) , .M_AXI_WUSER ( ) , .M_AXI_WVALID ( wvalid_d3 ) , .M_AXI_WREADY ( wready_d3 ) , .M_AXI_BID ( bid_d3 ) , .M_AXI_BRESP ( bresp_d3 ) , .M_AXI_BUSER ( 1'b0 ) , .M_AXI_BVALID ( bvalid_d3 ) , .M_AXI_BREADY ( bready_d3 ) , .M_AXI_ARID ( arid_d3 ) , .M_AXI_ARADDR ( araddr_d3 ) , .M_AXI_ARLEN ( arlen_d3 ) , // AxSIZE hardcoded with static value // .M_AXI_ARSIZE ( arsize_d3 ) , .M_AXI_ARSIZE ( ) , .M_AXI_ARBURST ( arburst_d3 ) , .M_AXI_ARLOCK ( arlock_d3 ) , .M_AXI_ARCACHE ( arcache_d3 ) , .M_AXI_ARPROT ( arprot_d3 ) , .M_AXI_ARREGION( ) , .M_AXI_ARQOS ( arqos_d3 ) , .M_AXI_ARUSER ( ) , .M_AXI_ARVALID ( arvalid_d3 ) , .M_AXI_ARREADY ( arready_d3 ) , .M_AXI_RID ( rid_d3 ) , .M_AXI_RDATA ( rdata_d3 ) , .M_AXI_RRESP ( rresp_d3 ) , .M_AXI_RLAST ( rlast_d3 ) , .M_AXI_RUSER ( 1'b0 ) , .M_AXI_RVALID ( rvalid_d3 ) , .M_AXI_RREADY ( rready_d3 ) ); // AW/W/B channel internal communication wire w_ignore_begin; wire w_ignore_end; wire w_cmd_rdy; wire awvalid_int; wire [3:0] awqos_int ; wire w_data_rdy ; wire b_push; wire [C_S_AXI_ID_WIDTH-1:0] b_awid; wire b_full; mig_7series_v4_0_axi_mc_aw_channel # ( .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ), .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ), .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ), .C_DATA_WIDTH ( C_MC_DATA_WIDTH ), .C_AXSIZE ( P_AXSIZE ), .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ), .C_MC_BURST_LEN ( C_MC_BURST_LEN ), .C_ECC ( C_ECC ) ) axi_mc_aw_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .awid ( awid_d3 ) , .awaddr ( awaddr_d3 ) , .awlen ( awlen_d3 ) , .awsize ( P_AXSIZE[2:0] ) , .awburst ( awburst_d3 ) , .awlock ( awlock_d3 ) , .awcache ( awcache_d3 ) , .awprot ( awprot_d3 ) , .awqos ( awqos_d3 ) , .awvalid ( awvalid_d3 ) , .awready ( awready_d3 ) , .cmd_en ( wr_cmd_en ) , .cmd_instr ( wr_cmd_instr ) , .cmd_byte_addr ( wr_cmd_byte_addr ) , .cmd_full ( wr_cmd_full ) , .cmd_en_last ( wr_cmd_en_last ) , .w_ignore_begin ( w_ignore_begin ) , .w_ignore_end ( w_ignore_end ) , .w_cmd_rdy ( w_cmd_rdy ) , .awvalid_int ( awvalid_int ) , .awqos_int ( awqos_int ) , .w_data_rdy ( w_data_rdy ) , .cmd_wr_bytes ( cmd_wr_bytes ) , .b_push ( b_push ) , .b_awid ( b_awid ) , .b_full ( b_full ) ); mig_7series_v4_0_axi_mc_w_channel # ( .C_DATA_WIDTH ( C_MC_DATA_WIDTH ), .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ), .C_MC_BURST_LEN ( C_MC_BURST_LEN ), .C_ECC ( C_ECC ) ) axi_mc_w_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .wdata ( wdata_d3 ) , .wstrb ( wstrb_d3 ) , .wvalid ( wvalid_d3 ) , .wready ( wready_d3 ) , .awvalid ( awvalid_int ) , .w_ignore_begin ( w_ignore_begin ) , .w_ignore_end ( w_ignore_end ) , .w_cmd_rdy ( w_cmd_rdy ) , .cmd_wr_bytes ( cmd_wr_bytes ) , .mc_app_wdf_wren ( mc_app_wdf_wren ) , .mc_app_wdf_mask ( mc_app_wdf_mask ) , .mc_app_wdf_data ( mc_app_wdf_data ) , .mc_app_wdf_last ( mc_app_wdf_end ) , .mc_app_wdf_rdy ( mc_app_wdf_rdy ) , .w_data_rdy ( w_data_rdy ) ); mig_7series_v4_0_axi_mc_b_channel # ( .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ) axi_mc_b_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .bid ( bid_d3 ) , .bresp ( bresp_d3 ) , .bvalid ( bvalid_d3 ) , .bready ( bready_d3 ) , .b_push ( b_push ) , .b_awid ( b_awid ) , .b_full ( b_full ) , .b_resp_rdy ( awready_d3 ) ); // AR/R channel communication wire r_push ; wire [C_S_AXI_ID_WIDTH-1:0] r_arid ; wire r_rlast ; wire r_data_rdy ; wire r_ignore_begin; wire r_ignore_end ; wire arvalid_int ; wire [3:0] arqos_int ; mig_7series_v4_0_axi_mc_ar_channel # ( .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ), .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ), .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ), .C_DATA_WIDTH ( C_MC_DATA_WIDTH ), .C_AXSIZE ( P_AXSIZE ), .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ), .C_MC_BURST_LEN ( C_MC_BURST_LEN ) ) axi_mc_ar_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .arid ( arid_d3 ) , .araddr ( araddr_d3 ) , .arlen ( arlen_d3 ) , .arsize ( P_AXSIZE[2:0] ) , .arburst ( arburst_d3 ) , .arlock ( arlock_d3 ) , .arcache ( arcache_d3 ) , .arprot ( arprot_d3 ) , .arqos ( arqos_d3 ) , .arvalid ( arvalid_d3 ) , .arready ( arready_d3 ) , .cmd_en ( rd_cmd_en ) , .cmd_instr ( rd_cmd_instr ) , .cmd_byte_addr ( rd_cmd_byte_addr ) , .cmd_full ( rd_cmd_full ) , .cmd_en_last ( rd_cmd_en_last ) , .r_push ( r_push ) , .r_arid ( r_arid ) , .r_rlast ( r_rlast ) , .r_data_rdy ( r_data_rdy ) , .r_ignore_begin ( r_ignore_begin ) , .r_ignore_end ( r_ignore_end ) , .arvalid_int ( arvalid_int ) , .arqos_int ( arqos_int ) ); mig_7series_v4_0_axi_mc_r_channel # ( .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ), .C_DATA_WIDTH ( C_MC_DATA_WIDTH ), .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ), .C_MC_BURST_MODE ( C_MC_BURST_MODE ), .C_MC_BURST_LEN ( C_MC_BURST_LEN ) ) axi_mc_r_channel_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , .rid ( rid_d3 ) , .rdata ( rdata_d3 ) , .rresp ( rresp_d3 ) , .rlast ( rlast_d3 ) , .rvalid ( rvalid_d3 ) , .rready ( rready_d3 ) , .mc_app_rd_valid ( mc_app_rd_valid ) , .mc_app_rd_data ( mc_app_rd_data ) , .mc_app_rd_last ( mc_app_rd_end ) , .mc_app_ecc_multiple_err ( |mc_app_ecc_multiple_err ) , .r_push ( r_push ) , .r_data_rdy ( r_data_rdy ) , .r_arid ( r_arid ) , .r_rlast ( r_rlast ) , .r_ignore_begin ( r_ignore_begin ) , .r_ignore_end ( r_ignore_end ) ); // Arbiter mig_7series_v4_0_axi_mc_cmd_arbiter # ( .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) , .C_MC_BURST_LEN ( C_MC_BURST_LEN ) , .C_RD_WR_ARB_ALGORITHM ( C_RD_WR_ARB_ALGORITHM ) ) axi_mc_cmd_arbiter_0 ( .clk ( aclk ) , .reset ( areset_d1 ) , // Write commands from AXI .wr_cmd_en ( wr_cmd_en ) , .wr_cmd_en_last ( wr_cmd_en_last ) , .wr_cmd_instr ( wr_cmd_instr ) , .wr_cmd_byte_addr ( wr_cmd_byte_addr ) , .wr_cmd_full ( wr_cmd_full ) , // Read commands from AXI .rd_cmd_en ( rd_cmd_en ) , .rd_cmd_en_last ( rd_cmd_en_last ) , .rd_cmd_instr ( rd_cmd_instr ) , .rd_cmd_byte_addr ( rd_cmd_byte_addr ) , .rd_cmd_full ( rd_cmd_full ) , // Next Command info .arvalid ( arvalid_int ) , .arqos ( arqos_int ) , .awvalid ( awvalid_int ) , .awqos ( awqos_int ) , // To MC .mc_app_en ( mc_app_en ) , .mc_app_cmd ( mc_app_cmd ) , .mc_app_size ( mc_app_sz ) , .mc_app_addr ( mc_app_addr ) , .mc_app_hi_pri ( mc_app_hi_pri ) , .mc_app_rdy ( mc_app_rdy ) ); endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_ar_channel.v // // Description: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_ar_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of cmd_byte_addr // Range: 30 parameter integer C_MC_ADDR_WIDTH = 30, // Width of AXI xDATA and MC xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // DRAM clock to AXI clock ratio // supported values 2, 4 parameter integer C_MC_nCK_PER_CLK = 2, // Static value of axsize // Range: 2-4 parameter integer C_AXSIZE = 2 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Read Address Ports input wire [C_ID_WIDTH-1:0] arid , input wire [C_AXI_ADDR_WIDTH-1:0] araddr , input wire [7:0] arlen , input wire [2:0] arsize , input wire [1:0] arburst , input wire [1:0] arlock , input wire [3:0] arcache , input wire [2:0] arprot , input wire [3:0] arqos , input wire arvalid , output wire arready , // MC Master Interface //CMD PORT output wire cmd_en , output wire cmd_en_last , output wire [2:0] cmd_instr , output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr , input wire cmd_full , // Connections to/from axi_mc_r_channel module input wire r_data_rdy , output reg r_push , output wire[C_ID_WIDTH-1:0] r_arid , output reg r_rlast , output wire r_ignore_begin , output wire r_ignore_end , output wire arvalid_int , output wire [3:0] arqos_int ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_CMD_WRITE = 3'b000; localparam P_CMD_READ = 3'b001; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire next ; wire next_pending ; reg [C_ID_WIDTH-1:0] axid ; reg [C_AXI_ADDR_WIDTH-1:0] axaddr ; reg [7:0] axlen ; reg [3:0] axqos ; reg [1:0] axburst ; reg axvalid ; wire [C_ID_WIDTH-1:0] axid_int ; wire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ; wire [7:0] axlen_int ; wire [3:0] axqos_int ; wire [1:0] axburst_int ; wire axvalid_int ; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign arvalid_int = axvalid_int; assign arqos_int = axqos_int; assign axid_int = arready ? arid : axid; assign axlen_int = arready ? arlen : axlen; assign axqos_int = arready ? arqos : axqos; assign axaddr_int = arready ? araddr : axaddr; assign axburst_int = arready ? arburst : axburst; assign axvalid_int = arready ? arvalid : axvalid; always @(posedge clk) begin if(reset) axvalid <= 1'b0; else axvalid <= axvalid_int; end always @(posedge clk) begin axid <= axid_int; axlen <= axlen_int; axqos <= axqos_int; axaddr <= axaddr_int; axburst <= axburst_int; end // Translate the AXI transaction to the MC transaction(s) mig_7series_v4_0_axi_mc_cmd_translator # ( .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) , .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) , .C_DATA_WIDTH ( C_DATA_WIDTH ) , .C_MC_BURST_LEN ( C_MC_BURST_LEN ) , .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) , .C_AXSIZE ( C_AXSIZE ) , .C_MC_RD_INST ( 1 ) ) axi_mc_cmd_translator_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( axaddr_int ) , .axlen ( axlen_int ) , .axsize ( arsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations. .axburst ( axburst_int ) , .axvalid ( axvalid_int ) , .axready ( arready ) , .cmd_byte_addr ( cmd_byte_addr ) , .ignore_begin ( r_ignore_begin ) , .ignore_end ( r_ignore_end ) , .next ( next ) , .next_pending ( next_pending ) ); mig_7series_v4_0_axi_mc_cmd_fsm # ( .C_MC_BURST_LEN (C_MC_BURST_LEN ), .C_MC_RD_INST (1 ) ) ar_cmd_fsm_0 ( .clk ( clk ) , .reset ( reset ) , .axready ( arready ) , .axvalid ( axvalid_int ) , .cmd_en ( cmd_en ) , .cmd_full ( cmd_full ) , .next ( next ) , .next_pending ( next_pending ) , .data_rdy ( r_data_rdy ) , .cmd_en_last ( cmd_en_last ) ); assign cmd_instr = P_CMD_READ; // these signals can be moved out of this block to the top level. assign r_arid = axid; always @(posedge clk) begin r_push <= next; r_rlast <= ~next_pending; end endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_aw_channel.v // // Description: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_aw_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of cmd_byte_addr // Range: 30 parameter integer C_MC_ADDR_WIDTH = 30, // Width of AXI xDATA and MC xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // DRAM clock to AXI clock ratio // supported values 2, 4 parameter integer C_MC_nCK_PER_CLK = 2, // Static value of axsize // Range: 2-4 parameter integer C_AXSIZE = 2, parameter C_ECC = "OFF" ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire clk , input wire reset , // Slave Interface Write Address Ports input wire [C_ID_WIDTH-1:0] awid , input wire [C_AXI_ADDR_WIDTH-1:0] awaddr , input wire [7:0] awlen , input wire [2:0] awsize , input wire [1:0] awburst , input wire [1:0] awlock , input wire [3:0] awcache , input wire [2:0] awprot , input wire [3:0] awqos , input wire awvalid , output wire awready , // MC Master Interface //CMD PORT output wire cmd_en , output wire cmd_en_last , output wire [2:0] cmd_instr , output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr , input wire cmd_full , // Connections to/from axi_mc_w_channel module input wire w_data_rdy , input wire cmd_wr_bytes , output wire w_cmd_rdy , output wire w_ignore_begin , output wire w_ignore_end , output wire awvalid_int , output wire [3:0] awqos_int , // Connections to/from axi_mc_b_channel module output wire b_push , output wire [C_ID_WIDTH-1:0] b_awid , input wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_CMD_WRITE = 3'b000; localparam P_CMD_READ = 3'b001; localparam P_CMD_WRITE_BYTES = 3'b011; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire next ; wire next_pending ; reg [C_ID_WIDTH-1:0] axid ; reg [C_AXI_ADDR_WIDTH-1:0] axaddr ; reg [7:0] axlen ; reg [3:0] axqos ; reg [1:0] axburst ; reg axvalid ; wire [C_ID_WIDTH-1:0] axid_int ; wire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ; wire [7:0] axlen_int ; wire [3:0] axqos_int ; wire [1:0] axburst_int ; wire axvalid_int ; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign awvalid_int = axvalid_int; assign awqos_int = axqos_int; assign axid_int = awready ? awid : axid; assign axlen_int = awready ? awlen : axlen; assign axqos_int = awready ? awqos : axqos; assign axaddr_int = awready ? awaddr : axaddr; assign axburst_int = awready ? awburst : axburst; assign axvalid_int = awready ? awvalid : axvalid; always @(posedge clk) begin if(reset) axvalid <= 1'b0; else axvalid <= axvalid_int; end always @(posedge clk) begin axid <= axid_int; axlen <= axlen_int; axqos <= axqos_int; axaddr <= axaddr_int; axburst <= axburst_int; end // Translate the AXI transaction to the MC transaction(s) mig_7series_v4_0_axi_mc_cmd_translator # ( .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) , .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) , .C_DATA_WIDTH ( C_DATA_WIDTH ) , .C_MC_BURST_LEN ( C_MC_BURST_LEN ) , .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) , .C_AXSIZE ( C_AXSIZE ) , .C_MC_RD_INST ( 0 ) ) axi_mc_cmd_translator_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( axaddr_int ) , .axlen ( axlen_int ) , .axsize ( awsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations. .axburst ( axburst_int ) , .axvalid ( axvalid_int ) , .axready ( awready ) , .cmd_byte_addr ( cmd_byte_addr ) , .ignore_begin ( w_ignore_begin ) , .ignore_end ( w_ignore_end ) , .next ( next ) , .next_pending ( next_pending ) ); mig_7series_v4_0_axi_mc_wr_cmd_fsm # ( .C_MC_BURST_LEN (C_MC_BURST_LEN ), .C_MC_RD_INST (0 ) ) aw_cmd_fsm_0 ( .clk ( clk ) , .reset ( reset ) , .axready ( awready ) , .axvalid ( axvalid_int ) , .cmd_en ( cmd_en ) , .cmd_full ( cmd_full ) , .next ( next ) , .next_pending ( next_pending ) , .data_rdy ( w_data_rdy ) , .b_push ( b_push ) , .b_full ( b_full ) , .cmd_en_last ( cmd_en_last ) ); // assign cmd_instr = (C_ECC == "ON") ? P_CMD_WRITE_BYTES : P_CMD_WRITE; assign cmd_instr = ((C_ECC == "ON") & cmd_wr_bytes) ? P_CMD_WRITE_BYTES : P_CMD_WRITE; assign b_awid = axid_int; assign w_cmd_rdy = next; endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_b_channel.v // // Description: // This module is responsible for returning the write response to the master // that initiated the write. The write address channel module will push the // transaction ID into a FIFO in the write response module after the // completion of the address write phase of the transaction. If strict // coherency is enabled (C_STRICT_COHERENCY == 1), then this module will // monitor the MCB command/write FIFOs to determine when to send back the // response. It will not send the response until it is guaranteed that the // write has been committed completely to memory. // // ERROR RESPONSE // If the MCB write channel indicates there is an error or write FIFO under // run then the AXI SLVERR response is returned otherwise the OKAY response // is returned. // // WRITE COHERENCY CHECKING // The MCB hard block can have up to 6 independent ports to memory. If the // MCB block is configured as single port or as multi-port with separate // regions then write coherency logic is not required. In all other cases, // once a transaction has been sent to the MCB CMD channel, it is not // guaranteed that it will commit to memory before a transaction on another // port. To ensure that the response is only sent after the data has been // written to external memory the write response will not be sent until // either the write data FIFO is empty or that the command FIFO is empty. // // Assertions: // 1. Standard FIFO assertions on bid_fifo_0. // 2. bvalid == 0, when C_STRICT_COHERENCY == 1 and mcb_empty == 0. /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_b_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk, input wire reset, // AXI signals output wire [C_ID_WIDTH-1:0] bid, output wire [1:0] bresp, output wire bvalid, input wire bready, // Signals to/from the axi_mc_aw_channel modules input wire b_push, input wire [C_ID_WIDTH-1:0] b_awid, input wire b_resp_rdy, output wire b_full ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // FIFO settings localparam P_WIDTH = C_ID_WIDTH; localparam P_DEPTH = 8; localparam P_AWIDTH = 3; // AXI protocol responses: localparam P_OKAY = 2'b00; localparam P_EXOKAY = 2'b01; localparam P_SLVERR = 2'b10; localparam P_DECERR = 2'b11; localparam B_RESP_PERF = 1'b1; // Set to 1 to increase the write response performance for back to back single beats. // Set to 0 in case of timing issues, but performance degrades for back to back single beats. wire empty; wire bhandshake; wire [C_ID_WIDTH-1:0] bid_i; reg b_pop; reg bvalid_i; reg [C_ID_WIDTH-1:0] bid_t; assign bresp = P_OKAY; generate if (B_RESP_PERF == 1) begin assign bid = bid_t; assign bvalid = bvalid_i; assign bhandshake = ~bvalid | bready; always @(*) b_pop = bhandshake & ~empty; always @(posedge clk) begin if(reset) begin bid_t <= 'b0; bvalid_i <= 1'b0; end else if(bhandshake) begin bid_t <= bid_i; bvalid_i <= ~empty; end end end else begin // B_RESP_PERF assign bid = bid_i; assign bvalid = bvalid_i; assign bhandshake = bvalid & bready; always @(posedge clk) b_pop <= bhandshake; always @(posedge clk) begin if (reset | bhandshake) begin bvalid_i <= 1'b0; end else if (~empty & (~b_pop)) begin bvalid_i <= 1'b1; end end end // B_RESP_PERF endgenerate mig_7series_v4_0_axi_mc_fifo # ( .C_WIDTH (P_WIDTH), .C_AWIDTH (P_AWIDTH), .C_DEPTH (P_DEPTH) ) bid_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( b_push ) , .rd_en ( b_pop ) , .din ( b_awid ) , .dout ( bid_i ) , .a_full ( ) , .full ( b_full ) , .a_empty ( ) , .empty ( empty ) ); endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_arbiter.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_cmd_arbiter.v // // Description: // This arbiter arbitrates commands from the read and write address channels // of AXI to the single CMD channel of the MC interface. The inputs are the // read and write commands that have already been translated to the MC // format. // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_cmd_arbiter # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of cmd_byte_addr // Range: 30 parameter integer C_MC_ADDR_WIDTH = 30, // write command starve limit in read priority reg mode // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, parameter integer C_AXI_WR_STARVE_LIMIT = 256, // log2 of C_AXI_WR_STARVE_LIMIT ceil (log2(C_AXI_WR_STARVE_LIMIT)) parameter integer C_AXI_STARVE_CNT_WIDTH = 8, parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG" // Indicates the Arbitration // Allowed values - "TDM", "ROUND_ROBIN", // "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT" ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // AXI Slave Interface // Slave Interface System Signals input wire clk , input wire reset , input wire awvalid , input wire [3:0] awqos , input wire wr_cmd_en , input wire wr_cmd_en_last , input wire [2:0] wr_cmd_instr , input wire [C_MC_ADDR_WIDTH-1:0] wr_cmd_byte_addr , output wire wr_cmd_full , input wire arvalid , input wire [3:0] arqos , input wire rd_cmd_en , input wire rd_cmd_en_last , input wire [2:0] rd_cmd_instr , input wire [C_MC_ADDR_WIDTH-1:0] rd_cmd_byte_addr , output wire rd_cmd_full , output wire mc_app_en , output wire [2:0] mc_app_cmd , output wire mc_app_size , output wire [C_MC_ADDR_WIDTH-1:0] mc_app_addr , output wire mc_app_hi_pri , input wire mc_app_rdy ); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire rnw; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign mc_app_en = rnw ? rd_cmd_en : wr_cmd_en; assign mc_app_cmd = rnw ? rd_cmd_instr : wr_cmd_instr; assign mc_app_addr = rnw ? rd_cmd_byte_addr : wr_cmd_byte_addr; assign mc_app_size = 1'b0; assign wr_cmd_full = rnw ? 1'b1 : ~mc_app_rdy; assign rd_cmd_full = ~rnw ? 1'b1 : ~mc_app_rdy; assign mc_app_hi_pri = 1'b0; generate // TDM Arbitration scheme if (C_RD_WR_ARB_ALGORITHM == "TDM") begin : TDM reg rnw_i; always @(posedge clk) begin if (reset) begin rnw_i <= 1'b0; end else begin rnw_i <= ~rnw_i; end end assign rnw = rnw_i; end else if (C_RD_WR_ARB_ALGORITHM == "ROUND_ROBIN") begin : ROUND_ROBIN reg rnw_i; always @(posedge clk) begin if (reset) begin rnw_i <= 1'b0; end else begin rnw_i <= ~rnw; end end assign rnw = (rnw_i & rd_cmd_en) | (~rnw_i & rd_cmd_en & ~wr_cmd_en); end else if (C_RD_WR_ARB_ALGORITHM == "RD_PRI_REG") begin : RD_PRI_REG reg rnw_i; reg rd_cmd_hold; reg wr_cmd_hold; reg [4:0] rd_wait_limit; reg [4:0] wr_wait_limit; reg [9:0] rd_starve_cnt; reg [9:0] wr_starve_cnt; always @(posedge clk) begin if (~rnw | ~rd_cmd_hold) begin rd_wait_limit <= 5'b0; rd_starve_cnt <= (C_MC_BURST_LEN * 2); end else if (mc_app_rdy) begin if (~arvalid | rd_cmd_en) rd_wait_limit <= 5'b0; else rd_wait_limit <= rd_wait_limit + C_MC_BURST_LEN; if (rd_cmd_en & ~rd_starve_cnt[8]) rd_starve_cnt <= rd_starve_cnt + C_MC_BURST_LEN; end end always @(posedge clk) begin if (rnw | ~wr_cmd_hold) begin wr_wait_limit <= 5'b0; wr_starve_cnt <= (C_MC_BURST_LEN * 2); end else if (mc_app_rdy) begin if (~awvalid | wr_cmd_en) wr_wait_limit <= 5'b0; else wr_wait_limit <= wr_wait_limit + C_MC_BURST_LEN; if (wr_cmd_en & ~wr_starve_cnt[8]) wr_starve_cnt <= wr_starve_cnt + C_MC_BURST_LEN; end end always @(posedge clk) begin if (reset) begin rd_cmd_hold <= 1'b0; wr_cmd_hold <= 1'b0; end else begin rd_cmd_hold <= (rnw | rd_cmd_hold) & ~(rd_cmd_en_last & ((awvalid & (|awqos)) | rd_starve_cnt[8])) & ~rd_wait_limit[4]; wr_cmd_hold <= (~rnw | wr_cmd_hold) & ~(wr_cmd_en_last & ((arvalid & (|arqos)) | wr_starve_cnt[8])) & ~wr_wait_limit[4]; end end always @(posedge clk) begin if (reset) rnw_i <= 1'b1; else rnw_i <= rnw; end assign rnw = (rnw_i & ~(rd_cmd_hold & arvalid) & awvalid) ? 1'b0 : // RD -> WR (~rnw_i & ~(wr_cmd_hold & awvalid) & arvalid) ? 1'b1 : // WR -> RD rnw_i; end // block: RD_PRI_REG else if (C_RD_WR_ARB_ALGORITHM == "RD_PRI_REG_STARVE_LIMIT") begin : RD_PRI_REG_STARVE reg rnw_i; reg rd_cmd_en_d1; reg wr_cmd_en_d1; reg [C_AXI_STARVE_CNT_WIDTH-1:0] wr_starve_cnt; reg wr_enable; reg [8:0] rd_starve_cnt; // write starve count logic. // wr_enable to give priority to write commands will be set // when the write commands have been starved till the starve // limit. The wr_enable will be de-asserted when the pending write // command is processed or if the rd has been starved for 256 clock // cycles. always @(posedge clk) begin if(reset | ( ~(wr_cmd_en | wr_cmd_en_d1)) | rd_starve_cnt[8])begin wr_starve_cnt <= 'b0; wr_enable <= 'b0; end else if(wr_cmd_en & (mc_app_rdy)) begin if(wr_starve_cnt < (C_AXI_WR_STARVE_LIMIT-1)) wr_starve_cnt <= wr_starve_cnt + rnw_i; else wr_enable <= 1'b1; end // if (wr_cmd_en & (mc_app_rdy) end // always @ (posedge clk) // The rd command should not be starved for ever in this mode. // The maximum the read will starve is 256 clocks. always @(posedge clk) begin if(reset | rnw_i)begin rd_starve_cnt <= 'b0; end else if(rd_cmd_en & (mc_app_rdy)) begin rd_starve_cnt <= rd_starve_cnt + 1; end // if (wr_cmd_en & (mc_app_rdy) end // always @ (posedge clk) always @(posedge clk) begin if (reset) begin rd_cmd_en_d1 <= 1'b0; wr_cmd_en_d1 <= 1'b0; end else begin if (mc_app_rdy) begin rd_cmd_en_d1 <= rd_cmd_en & rnw; wr_cmd_en_d1 <= wr_cmd_en & ~rnw; end end end always @(posedge clk) begin if (reset) begin rnw_i <= 1'b1; end else begin // Only set RNW to 0 if there is a write pending and read is idle // rnw_i <= ~((wr_cmd_en | wr_cmd_en_d1) & (~rd_cmd_en) & (~rd_cmd_en_d1)); rnw_i <= ~(((wr_cmd_en | wr_cmd_en_d1) & (~rd_cmd_en) & (~rd_cmd_en_d1)) | wr_enable); end end assign rnw = rnw_i; end else if (C_RD_WR_ARB_ALGORITHM == "RD_PRI") begin : RD_PRI assign rnw = ~(wr_cmd_en & ~rd_cmd_en); end else if (C_RD_WR_ARB_ALGORITHM == "WR_PR_REG") begin : WR_PR_REG reg rnw_i; always @(posedge clk) begin if (reset) begin rnw_i <= 1'b0; end else begin // Only set RNW to 1 if there is a read pending and write is idle // rnw_i <= (~wr_cmd_en & rd_cmd_en); rnw_i <= (~awvalid & arvalid); end end assign rnw = rnw_i; end else begin : WR_PR // if (C_RD_WR_ARB_ALGORITHM == "WR_PR") begin // assign rnw = (~wr_cmd_en & rd_cmd_en); assign rnw = (~awvalid & arvalid); end endgenerate endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_cmd_fsm.v // // Description: // Simple state machine to handle sending commands from AXI to MC. The flow: // 1. A transaction can only be initiaited when axvalid is true and data_rdy // is true. For writes, data_rdy means that one completed BL8 or BL4 write // data has been pushed into the MC write FIFOs. For read operations, // data_rdy indicates that there is enough room to push the transaction into // the read FIF & read transaction fifo in the shim. If the FIFO's in the // read channel module is full, then the state machine waits for the // FIFO's to drain out. // // 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in // a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command // has been accepted. When the command is accepted, if the next_pending // signal is high we will incremented to the next transaction and issue the // cmd_en again when data_rdy is high. Otherwise we will go to the done // state. // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_cmd_fsm #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // parameter to identify rd or wr instantation // = 1 rd , = 0 wr parameter integer C_MC_RD_INST = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , output reg axready , input wire axvalid , output wire cmd_en , input wire cmd_full , // signal to increment to the next mc transaction output wire next , // signal to the fsm there is another transaction required input wire next_pending , // Write Data portion has completed or Read FIFO has a slot available (not // full) input wire data_rdy , // status signal for w_channel when command is written. output wire cmd_en_last ); //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// assign cmd_en = (axvalid & data_rdy); assign next = (~cmd_full & cmd_en); assign cmd_en_last = next & ~next_pending; always @(posedge clk) begin if (reset) axready <= 1'b0; else axready <= ~axvalid | cmd_en_last; end endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_cmd_translator.v // // Description: // INCR and WRAP burst modes are decoded in parallel and then the output is // chosen based on the AxBURST value. FIXED burst mode is not supported and // is mapped to the INCR command instead. // // Specifications: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_cmd_translator # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of cmd_byte_addr // Range: 30 parameter integer C_MC_ADDR_WIDTH = 30, // Width of AXI xDATA and MC xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // DRAM clock to AXI clock ratio // supported values 2, 4 parameter integer C_MC_nCK_PER_CLK = 2, // Static value of axsize // Range: 2-5 parameter integer C_AXSIZE = 2, // Instance for Read channel or write channel parameter integer C_MC_RD_INST = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , input wire [7:0] axlen , input wire [2:0] axsize , input wire [1:0] axburst , input wire axvalid , input wire axready , output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr , output wire ignore_begin , output wire ignore_end , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output wire next_pending ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_MC_BURST_MASK = {C_MC_ADDR_WIDTH{1'b1}} ^ {C_MC_BURST_LEN+(C_MC_nCK_PER_CLK/2){1'b1}}; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr_i; wire [C_AXI_ADDR_WIDTH-1:0] axi_mc_incr_cmd_byte_addr; wire incr_next_pending; wire [C_AXI_ADDR_WIDTH-1:0] axi_mc_wrap_cmd_byte_addr; wire wrap_next_pending; wire incr_ignore_begin; wire incr_ignore_end; wire wrap_ignore_begin; wire wrap_ignore_end; wire axhandshake; wire incr_axhandshake; wire wrap_axhandshake; wire incr_next; wire wrap_next; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign axhandshake = axvalid & axready; // INCR and WRAP translations are calcuated in independently, select the one // for our transactions // right shift by the UI width to the DRAM width ratio assign cmd_byte_addr = (C_MC_nCK_PER_CLK == 4) ? (cmd_byte_addr_i >> C_AXSIZE-3) & P_MC_BURST_MASK : (cmd_byte_addr_i >> C_AXSIZE-2) & P_MC_BURST_MASK; assign cmd_byte_addr_i = (axburst[1]) ? axi_mc_wrap_cmd_byte_addr : axi_mc_incr_cmd_byte_addr; assign ignore_begin = (axburst[1]) ? wrap_ignore_begin : incr_ignore_begin; assign ignore_end = (axburst[1]) ? wrap_ignore_end : incr_ignore_end; assign next_pending = (axburst[1]) ? wrap_next_pending : incr_next_pending; assign incr_axhandshake = (axburst[1]) ? 1'b0 : axhandshake; assign wrap_axhandshake = (axburst[1]) ? axhandshake : 1'b0; assign incr_next = (axburst[1]) ? 1'b0 : next; assign wrap_next = (axburst[1]) ? next : 1'b0; mig_7series_v4_0_axi_mc_incr_cmd # ( .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH), .C_DATA_WIDTH (C_DATA_WIDTH), .C_MC_BURST_LEN (C_MC_BURST_LEN), .C_AXSIZE (C_AXSIZE), .C_MC_RD_INST (C_MC_RD_INST) ) axi_mc_incr_cmd_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( axaddr ) , .axlen ( axlen ) , .axsize ( axsize ) , .axhandshake ( incr_axhandshake ) , .cmd_byte_addr ( axi_mc_incr_cmd_byte_addr ) , .ignore_begin ( incr_ignore_begin ) , .ignore_end ( incr_ignore_end ) , .next ( incr_next ) , .next_pending ( incr_next_pending ) ); mig_7series_v4_0_axi_mc_wrap_cmd # ( .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH), .C_MC_BURST_LEN (C_MC_BURST_LEN), .C_DATA_WIDTH (C_DATA_WIDTH), .C_AXSIZE (C_AXSIZE), .C_MC_RD_INST (C_MC_RD_INST) ) axi_mc_wrap_cmd_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( axaddr ) , .axlen ( axlen ) , .axsize ( axsize ) , .axhandshake ( wrap_axhandshake ) , .ignore_begin ( wrap_ignore_begin ) , .ignore_end ( wrap_ignore_end ) , .cmd_byte_addr ( axi_mc_wrap_cmd_byte_addr ) , .next ( wrap_next ) , .next_pending ( wrap_next_pending ) ); endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v ================================================ //----------------------------------------------------------------------------- //-- (c) Copyright 2013 Xilinx, Inc. All rights reserved. //-- //-- This file contains confidential and proprietary information //-- of Xilinx, Inc. and is protected under U.S. and //-- international copyright and other intellectual property //-- laws. //-- //-- DISCLAIMER //-- This disclaimer is not a license and does not grant any //-- rights to the materials distributed herewith. Except as //-- otherwise provided in a valid license issued to you by //-- Xilinx, and to the maximum extent permitted by applicable //-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND //-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES //-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING //-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- //-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and //-- (2) Xilinx shall not be liable (whether in contract or tort, //-- including negligence, or under any other theory of //-- liability) for any loss or damage of any kind or nature //-- related to, arising under or in connection with these //-- materials, including for any direct, or any indirect, //-- special, incidental, or consequential loss or damage //-- (including loss of data, profits, goodwill, or any type of //-- loss or damage suffered as a result of any action brought //-- by a third party) even if such damage or loss was //-- reasonably foreseeable or Xilinx had been advised of the //-- possibility of the same. //-- //-- CRITICAL APPLICATIONS //-- Xilinx products are not designed or intended to be fail- //-- safe, or for use in any application requiring fail-safe //-- performance, such as life-support or safety devices or //-- systems, Class III medical devices, nuclear facilities, //-- applications related to the deployment of airbags, or any //-- other applications that could lead to death, personal //-- injury, or severe property or environmental damage //-- (individually and collectively, "Critical //-- Applications"). Customer assumes the sole risk and //-- liability of any use of Xilinx products in Critical //-- Applications, subject only to applicable laws and //-- regulations governing limitations on product liability. //-- //-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS //-- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- //Purpose: // Synchronous, shallow FIFO that uses simple as a DP Memory. // This requires about 1/2 the resources as a Distributed RAM DPRAM // implementation. // // This FIFO will have the current data on the output when data is contained // in the FIFO. When the FIFO is empty, the output data is invalid. // //Reference: //Revision History: // //----------------------------------------------- // // MODULE: axi_mc_fifo // // This is the simplest form of inferring the // simple/SRL(16/32)CE in a Xilinx FPGA. // //----------------------------------------------- `timescale 1ns / 100ps `default_nettype none module mig_7series_v4_0_axi_mc_fifo # ( parameter C_WIDTH = 8, parameter C_AWIDTH = 4, parameter C_DEPTH = 16 ) ( input wire clk, // Main System Clock (Sync FIFO) input wire rst, // FIFO Counter Reset (Clk input wire wr_en, // FIFO Write Enable (Clk) input wire rd_en, // FIFO Read Enable (Clk) input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk) output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk) output wire a_full, output wire full, // FIFO FULL Status (Clk) output wire a_empty, output wire empty // FIFO EMPTY Status (Clk) ); /////////////////////////////////////// // FIFO Local Parameters /////////////////////////////////////// localparam [C_AWIDTH:0] C_EMPTY = ~(0); localparam [C_AWIDTH-1:0] C_EMPTY_PRE = 0; localparam [C_AWIDTH-1:0] C_FULL = C_DEPTH - 1; localparam [C_AWIDTH-1:0] C_FULL_PRE = C_DEPTH -2; /////////////////////////////////////// // FIFO Internal Signals /////////////////////////////////////// reg [C_WIDTH-1:0] memory [C_DEPTH-1:0]; reg [C_AWIDTH:0] cnt_read; reg [C_AWIDTH:0] next_cnt_read; wire [C_AWIDTH:0] cnt_read_plus1; wire [C_AWIDTH:0] cnt_read_minus1; wire [C_AWIDTH-1:0] read_addr; /////////////////////////////////////// // Main FIFO Array /////////////////////////////////////// assign read_addr = cnt_read; assign dout = memory[read_addr]; always @(posedge clk) begin : BLKSRL integer i; if (wr_en) begin for (i = 0; i < C_DEPTH-1; i = i + 1) begin memory[i+1] <= memory[i]; end memory[0] <= din; end end /////////////////////////////////////// // Read Index Counter // Up/Down Counter // *** Notice that there is no *** // *** OVERRUN protection. *** /////////////////////////////////////// always @(posedge clk) begin if (rst) cnt_read <= C_EMPTY; else cnt_read <= next_cnt_read; end assign cnt_read_plus1 = cnt_read + 1'b1; assign cnt_read_minus1 = cnt_read - 1'b1; always @(*) begin next_cnt_read = cnt_read; if ( wr_en & !rd_en) next_cnt_read = cnt_read_plus1; else if (!wr_en & rd_en) next_cnt_read = cnt_read_minus1; end /////////////////////////////////////// // Status Flags / Outputs // These could be registered, but would // increase logic in order to pre-decode // FULL/EMPTY status. /////////////////////////////////////// assign full = (cnt_read == C_FULL); assign empty = (cnt_read == C_EMPTY); assign a_full = (cnt_read == C_FULL_PRE); assign a_empty = (cnt_read == C_EMPTY_PRE); endmodule // axi_mc_fifo `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_incr_cmd.v // // Description: // MC does not support up to 256 beats per transaction to support an AXI INCR // command directly. Additionally for QOS purposes, larger transactions // issued as many smaller transactions should improve QoS for the system. // In the BL8 mode depending on the address offset ragged head or ragged tail // need to be inserted into the data stream for writes and ignored for reads. // In BL8 mode for transactions with odd length and even length transactions // with an address offset an extra BL8 transaction will be issued. /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_incr_cmd # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of cmd_byte_addr // Range: 30 parameter integer C_MC_ADDR_WIDTH = 30, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // Width of AXI xDATA and MC xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // Static value of axsize // Range: 2-4 parameter integer C_AXSIZE = 2, // Instance for Read channel or write channel parameter integer C_MC_RD_INST = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , input wire [7:0] axlen , input wire [2:0] axsize , // axhandshake = axvalid & axready input wire axhandshake , output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr , output wire ignore_begin , output wire ignore_end , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output wire next_pending ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_AXLEN_WIDTH = 8; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg sel_first_r; reg [7:0] axlen_cnt; reg [C_AXI_ADDR_WIDTH-1:0] axaddr_incr; reg int_next_pending_r; wire sel_first; wire addr_offset; wire length_even; wire [7:0] axlen_cnt_t; wire [7:0] axlen_cnt_p; wire [7:0] axlen_cnt_i; wire [C_AXI_ADDR_WIDTH-1:0] axaddr_incr_t; (* keep = "true" *) reg [C_AXI_ADDR_WIDTH-1:0] axaddr_incr_p; wire [7:0] incr_cnt; wire int_next_pending; wire extra_cmd; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign cmd_byte_addr = axaddr_incr_t; generate if(C_MC_BURST_LEN == 1) begin assign addr_offset = 1'b0; assign length_even = 1'b1; assign axaddr_incr_t = axhandshake ? axaddr : axaddr_incr; end else begin // Figuring out if the address have an offset for padding data in BL8 case assign addr_offset = axaddr[C_AXSIZE]; // The length could be odd which is an issue in BL8 assign length_even = axlen[0]; if(C_MC_RD_INST == 0) // axhandshake & next won't occur in same cycle in Write channel 2:1 mode assign axaddr_incr_t = axaddr_incr; else assign axaddr_incr_t = axhandshake ? axaddr : axaddr_incr; end endgenerate always @(*) begin axaddr_incr_p = axaddr_incr_t + (incr_cnt * C_MC_BURST_LEN); end always @(posedge clk) begin if(reset) axaddr_incr <= {C_AXI_ADDR_WIDTH{1'b0}}; else if (axhandshake & ~next) axaddr_incr <= axaddr; else if(next) axaddr_incr <= axaddr_incr_p; end // figuring out how much to much to incr based on AXSIZE assign incr_cnt = (C_AXSIZE == 2) ? 8'd4 : (C_AXSIZE == 3) ? 8'd8 : (C_AXSIZE == 4)? 8'd16 :(C_AXSIZE == 5) ? 8'd32 : (C_AXSIZE == 6) ? 8'd64 : (C_AXSIZE == 7) ? 8'd128 :8'd0; // assign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen : (extra_cmd ? ((axlen >> 1) + 1'b1) : (axlen >> 1)); assign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen : (axlen >> 1); assign axlen_cnt_t = axhandshake ? axlen_cnt_i : axlen_cnt; assign axlen_cnt_p = (axlen_cnt_t - 1'b1); always @(posedge clk) begin if(reset) axlen_cnt <= 4'hf; else if (axhandshake & ~next) axlen_cnt <= axlen_cnt_i; else if(next) axlen_cnt <= axlen_cnt_p; end assign extra_cmd = addr_offset & length_even; assign next_pending = extra_cmd ? int_next_pending_r : int_next_pending; assign int_next_pending = |axlen_cnt_t; always @(posedge clk) begin if(reset) int_next_pending_r <= 1'b1; else if(extra_cmd & next) int_next_pending_r <= int_next_pending; end // last and ignore signals to data channel. These signals are used for // BL8 to ignore and insert data for even len transactions with offset // and odd len transactions // For odd len transactions with no offset the last read is ignored and // last write is masked // For odd len transactions with offset the first read is ignored and // first write is masked // For even len transactions with offset the last & first read is ignored and // last& first write is masked // For even len transactions no ingnores or masks. // Ignore logic for first transaction assign ignore_begin = sel_first ? addr_offset : 1'b0; // Ignore logic for second transaction. assign ignore_end = next_pending ? 1'b0 : ~(length_even ^ addr_offset); // Indicates if we are on the first transaction of a mc translation with more than 1 transaction. assign sel_first = (axhandshake | sel_first_r); always @(posedge clk) begin if (reset) sel_first_r <= 1'b0; else if(axhandshake & ~next) sel_first_r <= 1'b1; else if(next) sel_first_r <= 1'b0; end endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_r_channel.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_r_channel.v // // Description: // Read data channel module to buffer read data from MC, ignore // extra data in case of BL8 and send the data to AXI. // The MC will send out the read data as it is ready and it has to be // accepted. The read data FIFO in the axi_mc_r_channel module will buffer // the data before being sent to AXI. The address channel module will // send the transaction information for every command that is sent to the // MC. The transaction information will be buffered in a transaction FIFO. // Based on the transaction FIFO information data will be ignored in // BL8 mode and the last signal to the AXI will be asserted. /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_r_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of ID signals. // Range: >= 1. parameter integer C_ID_WIDTH = 4, // Width of AXI xDATA and MCB xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // axi addr width parameter integer C_AXI_ADDR_WIDTH = 32, // Number of memory clocks per fabric clock // = 2 for DDR2 or low frequency designs // = 4 for DDR3 or high frequency designs parameter C_MC_nCK_PER_CLK = 2, // memory controller burst mode, // values "8", "4" & "OTF" parameter C_MC_BURST_MODE = "8" ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , output wire [C_ID_WIDTH-1:0] rid , output wire [C_DATA_WIDTH-1:0] rdata , output wire [1:0] rresp , output wire rlast , output wire rvalid , input wire rready , input wire [C_DATA_WIDTH-1:0] mc_app_rd_data , input wire mc_app_rd_valid , input wire mc_app_rd_last , input wire mc_app_ecc_multiple_err , // Connections to/from axi_mc_ar_channel module input wire r_push , output wire r_data_rdy , // length not needed. Can be removed. input wire [C_ID_WIDTH-1:0] r_arid , input wire r_rlast , input wire r_ignore_begin , input wire r_ignore_end ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_WIDTH = 3+C_ID_WIDTH; localparam P_DEPTH = 30; localparam P_AWIDTH = 5; localparam P_D_WIDTH = C_DATA_WIDTH+1; // rd data FIFO depth varies based on burst length. // For Bl8 it is two times the size of transaction FIFO. // Only in 2:1 mode BL8 transactions will happen which results in // two beats of read data per read transaction. localparam P_D_DEPTH = (C_MC_BURST_LEN == 2)? 64 : 32; localparam P_D_AWIDTH = (C_MC_BURST_LEN == 2)? 6: 5; // AXI protocol responses: localparam P_OKAY = 2'b00; localparam P_EXOKAY = 2'b01; localparam P_SLVERR = 2'b10; localparam P_DECERR = 2'b11; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// wire done; wire [C_ID_WIDTH+3-1:0] trans_in; wire [C_ID_WIDTH+3-1:0] trans_out; reg [C_ID_WIDTH+3-1:0] trans_buf_out_r1; reg [C_ID_WIDTH+3-1:0] trans_buf_out_r; wire tr_empty; wire tr_rden; reg [1:0] state; wire [C_ID_WIDTH-1:0] rid_i; wire assert_rlast; wire ignore_begin; wire ignore_end; reg load_stage1; wire load_stage2; wire load_stage1_from_stage2; wire rhandshake; wire rlast_i; wire r_valid_i; wire [C_DATA_WIDTH:0] rd_data_fifo_in; wire [C_DATA_WIDTH:0] rd_data_fifo_out; wire rd_en; wire rd_full; wire rd_empty; wire rd_a_full; reg rd_last_r; wire fifo_rd_last; wire trans_a_full; wire trans_full; reg r_ignore_begin_r; reg r_ignore_end_r; wire fifo_full; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // localparam for 2 deep skid buffer localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01; assign rresp = (rd_data_fifo_out[C_DATA_WIDTH] === 1) ? P_SLVERR : P_OKAY; assign rid = rid_i; assign rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0]; assign rlast = assert_rlast & ((~fifo_rd_last & ignore_end) | (fifo_rd_last & ~ignore_end)); assign rvalid = ~rd_empty & ((~fifo_rd_last & ~ignore_begin) | (fifo_rd_last & ~ignore_end )); // assign MCB outputs assign rd_en = rhandshake & (~rd_empty); assign rhandshake =(rvalid & rready) | (((~fifo_rd_last & ignore_begin) | (fifo_rd_last & ignore_end )) & (~rd_empty)); // register for timing always @(posedge clk) begin r_ignore_begin_r <= r_ignore_begin; r_ignore_end_r <= r_ignore_end; end assign trans_in[0] = r_ignore_end_r; assign trans_in[1] = r_ignore_begin_r; assign trans_in[2] = r_rlast; assign trans_in[3+:C_ID_WIDTH] = r_arid; always @(posedge clk) begin if (reset) begin rd_last_r <= 1'b0; end else if (rhandshake) begin rd_last_r <= ~rd_last_r; end end assign fifo_rd_last = (C_MC_BURST_LEN == 1) ? 1'b1 : rd_last_r; // rd data fifo mig_7series_v4_0_axi_mc_fifo # ( .C_WIDTH (P_D_WIDTH), .C_AWIDTH (P_D_AWIDTH), .C_DEPTH (P_D_DEPTH) ) rd_data_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( mc_app_rd_valid ) , .rd_en ( rd_en ) , .din ( rd_data_fifo_in ) , .dout ( rd_data_fifo_out ) , .a_full ( rd_a_full ) , .full ( rd_full ) , .a_empty ( ) , .empty ( rd_empty ) ); assign rd_data_fifo_in = {mc_app_ecc_multiple_err, mc_app_rd_data}; mig_7series_v4_0_axi_mc_fifo # ( .C_WIDTH (P_WIDTH), .C_AWIDTH (P_AWIDTH), .C_DEPTH (P_DEPTH) ) transaction_fifo_0 ( .clk ( clk ) , .rst ( reset ) , .wr_en ( r_push ) , .rd_en ( tr_rden ) , .din ( trans_in ) , .dout ( trans_out ) , .a_full ( trans_a_full) , .full ( trans_full ) , .a_empty ( ) , .empty ( tr_empty ) ); assign rid_i = trans_buf_out_r[3+:C_ID_WIDTH]; assign assert_rlast = trans_buf_out_r[2]; assign ignore_begin = trans_buf_out_r[1]; assign ignore_end = trans_buf_out_r[0]; assign done = fifo_rd_last & rhandshake; assign fifo_full = (trans_a_full | trans_full) | (rd_a_full | rd_full); assign r_data_rdy = ~fifo_full ; // logic for 2 deep skid buffer for storing transaction data for timing // loading the output of the buffer always @(posedge clk) begin if(load_stage1) if(load_stage1_from_stage2) trans_buf_out_r <= trans_buf_out_r1; else trans_buf_out_r <= trans_out; end // store data into the optional second stage always @(posedge clk) begin if(load_stage2) trans_buf_out_r1 <= trans_out; end // condition to store data for the second stage assign load_stage2 = ~tr_empty & state[1]; // Loading stage one conditions always @ (*) begin if( ((state == ZERO) && (~tr_empty)) || ((state == ONE) && (~tr_empty) && (done)) || ((state == TWO) && (done))) load_stage1 = 1'b1; else load_stage1 = 1'b0; end // always @ * assign load_stage1_from_stage2 = (state == TWO); always @(posedge clk) begin if(reset) state <= ZERO; else case (state) ZERO: if (~tr_empty) state <= ONE; ONE: begin if (done & tr_empty) state <= ZERO; // if (~done & (~tr_empty)) state <= TWO; else if (~done & (~tr_empty)) state <= TWO; end TWO: if (done) state <= ONE; endcase end assign tr_rden = ((state == ZERO) || (state == ONE)) && (~tr_empty); endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_simple_fifo.v ================================================ //----------------------------------------------------------------------------- //-- (c) Copyright 2013 Xilinx, Inc. All rights reserved. //-- //-- This file contains confidential and proprietary information //-- of Xilinx, Inc. and is protected under U.S. and //-- international copyright and other intellectual property //-- laws. //-- //-- DISCLAIMER //-- This disclaimer is not a license and does not grant any //-- rights to the materials distributed herewith. Except as //-- otherwise provided in a valid license issued to you by //-- Xilinx, and to the maximum extent permitted by applicable //-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND //-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES //-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING //-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- //-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and //-- (2) Xilinx shall not be liable (whether in contract or tort, //-- including negligence, or under any other theory of //-- liability) for any loss or damage of any kind or nature //-- related to, arising under or in connection with these //-- materials, including for any direct, or any indirect, //-- special, incidental, or consequential loss or damage //-- (including loss of data, profits, goodwill, or any type of //-- loss or damage suffered as a result of any action brought //-- by a third party) even if such damage or loss was //-- reasonably foreseeable or Xilinx had been advised of the //-- possibility of the same. //-- //-- CRITICAL APPLICATIONS //-- Xilinx products are not designed or intended to be fail- //-- safe, or for use in any application requiring fail-safe //-- performance, such as life-support or safety devices or //-- systems, Class III medical devices, nuclear facilities, //-- applications related to the deployment of airbags, or any //-- other applications that could lead to death, personal //-- injury, or severe property or environmental damage //-- (individually and collectively, "Critical //-- Applications"). Customer assumes the sole risk and //-- liability of any use of Xilinx products in Critical //-- Applications, subject only to applicable laws and //-- regulations governing limitations on product liability. //-- //-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS //-- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- //Purpose: // Synchronous, shallow FIFO that uses simple as a DP Memory. // This requires about 1/2 the resources as a Distributed RAM DPRAM // implementation. // // This FIFO will have the current data on the output when data is contained // in the FIFO. When the FIFO is empty, the output data is invalid. // //Reference: //Revision History: // //----------------------------------------------- // // MODULE: axi_mc_simple_fifo // // This is the simplest form of inferring the // simple/SRL(16/32)CE in a Xilinx FPGA. // //----------------------------------------------- `timescale 1ns / 100ps `default_nettype none module mig_7series_v4_0_axi_mc_simple_fifo # ( parameter C_WIDTH = 8, parameter C_AWIDTH = 4, parameter C_DEPTH = 16 ) ( input wire clk, // Main System Clock (Sync FIFO) input wire rst, // FIFO Counter Reset (Clk input wire wr_en, // FIFO Write Enable (Clk) input wire rd_en, // FIFO Read Enable (Clk) input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk) output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk) output wire a_full, output wire full, // FIFO FULL Status (Clk) output wire a_empty, output wire empty // FIFO EMPTY Status (Clk) ); /////////////////////////////////////// // FIFO Local Parameters /////////////////////////////////////// localparam [C_AWIDTH-1:0] C_EMPTY = ~(0); localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0); localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1; localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8); /////////////////////////////////////// // FIFO Internal Signals /////////////////////////////////////// reg [C_WIDTH-1:0] memory [C_DEPTH-1:0]; reg [C_AWIDTH-1:0] cnt_read; /////////////////////////////////////// // Main simple FIFO Array /////////////////////////////////////// always @(posedge clk) begin : BLKSRL integer i; if (wr_en) begin for (i = 0; i < C_DEPTH-1; i = i + 1) begin memory[i+1] <= memory[i]; end memory[0] <= din; end end /////////////////////////////////////// // Read Index Counter // Up/Down Counter // *** Notice that there is no *** // *** OVERRUN protection. *** /////////////////////////////////////// always @(posedge clk) begin if (rst) cnt_read <= C_EMPTY; else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1; else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1; end /////////////////////////////////////// // Status Flags / Outputs // These could be registered, but would // increase logic in order to pre-decode // FULL/EMPTY status. /////////////////////////////////////// assign full = (cnt_read == C_FULL); assign empty = (cnt_read == C_EMPTY); assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY)); assign a_empty = (cnt_read == C_EMPTY_PRE); assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read]; endmodule // axi_mc_simple_fifo `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_w_channel.v // // Description: // write data channel module is used to buffer the write data from AXI, mask extra transactions // that are not needed in BL8 mode and send them to the MC write data FIFO. // The use of register slice could result in write data arriving to this modules well before the // the commands are processed by the address modules. The data from AXI will be buffered // in the write data FIFO before being sent to the MC. // The address channel modules will send signals to mask appropriate data to before being sent // to the MC. // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_w_channel # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AXI xDATA and MCB xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // axi addr width parameter integer C_AXI_ADDR_WIDTH = 32, // ECC parameter C_ECC = "OFF" ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_DATA_WIDTH-1:0] wdata, input wire [C_DATA_WIDTH/8-1:0] wstrb, input wire wvalid, output reg wready, input wire awvalid, input wire w_cmd_rdy, input wire w_ignore_begin, input wire w_ignore_end, output wire cmd_wr_bytes, output wire mc_app_wdf_wren, output wire [C_DATA_WIDTH/8-1:0] mc_app_wdf_mask, output wire [C_DATA_WIDTH-1:0] mc_app_wdf_data, output wire mc_app_wdf_last, input wire mc_app_wdf_rdy, output wire w_data_rdy ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //states localparam SM_FIRST_DATA = 1'b0; localparam SM_SECOND_DATA = 1'b1; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg [C_DATA_WIDTH/8-1:0] wdf_mask; reg [C_DATA_WIDTH-1:0] wdf_data; reg valid; wire wdf_last; wire assert_wren; wire disable_data; wire [C_DATA_WIDTH/8-1:0] next_wdf_mask; wire [C_DATA_WIDTH-1:0] next_wdf_data; wire fsm_ready; wire wvalid_int; wire [C_DATA_WIDTH-1:0] next_mc_app_wdf_data; wire next_mc_app_wdf_wren; wire [C_DATA_WIDTH/8-1:0] next_mc_app_wdf_mask; wire next_mc_app_wdf_last; reg mc_app_wdf_wren_reg; reg [C_DATA_WIDTH/8-1:0] mc_app_wdf_mask_reg; reg [C_DATA_WIDTH-1:0] mc_app_wdf_data_reg; reg mc_app_wdf_last_reg; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign wvalid_int = wready ? wvalid : valid; always @(posedge clk) begin if(reset) begin valid <= 1'b0; wready <= 1'b0; end else begin valid <= wvalid_int; wready <= ~wvalid_int | fsm_ready; end end assign fsm_ready = (assert_wren & ~disable_data); assign mc_app_wdf_wren = next_mc_app_wdf_wren; assign mc_app_wdf_last = next_mc_app_wdf_last; assign mc_app_wdf_mask = next_mc_app_wdf_mask; assign mc_app_wdf_data = next_mc_app_wdf_data; assign next_mc_app_wdf_wren = mc_app_wdf_rdy ? assert_wren : mc_app_wdf_wren_reg; assign next_mc_app_wdf_last = mc_app_wdf_rdy ? wdf_last : mc_app_wdf_last_reg; assign next_mc_app_wdf_mask = mc_app_wdf_rdy ? ((disable_data)? {C_DATA_WIDTH/8{1'b1}} : next_wdf_mask) : mc_app_wdf_mask_reg; assign next_mc_app_wdf_data = mc_app_wdf_rdy ? next_wdf_data : mc_app_wdf_data_reg; always @(posedge clk) begin if(reset) begin mc_app_wdf_wren_reg <= 1'b0; mc_app_wdf_last_reg <= 1'b0; mc_app_wdf_mask_reg <= {C_DATA_WIDTH/8{1'b0}}; end else begin mc_app_wdf_wren_reg <= next_mc_app_wdf_wren; mc_app_wdf_last_reg <= next_mc_app_wdf_last; mc_app_wdf_mask_reg <= next_mc_app_wdf_mask; end end always @(posedge clk) begin mc_app_wdf_data_reg <= next_mc_app_wdf_data; end assign next_wdf_mask = wready ? ~wstrb : wdf_mask; assign next_wdf_data = wready ? wdata : wdf_data; always @(posedge clk) begin wdf_mask <= next_wdf_mask; wdf_data <= next_wdf_data; end generate if(C_MC_BURST_LEN == 1) begin : gen_bc1 // w_data_rdy to axi_mc_cmd_fsm when one Bl8 or Bl4 worth of write data // is pumped into to MC WDF. assign w_data_rdy = wvalid_int & mc_app_wdf_rdy; // write enable signal to WDF assign assert_wren = w_cmd_rdy; assign wdf_last = w_cmd_rdy; assign disable_data = 1'b0; end else begin : gen_bc2 // Declaration of signals used only in BC2 mode reg state; reg next_state; reg w_ignore_end_r; always @(posedge clk) begin if (reset) state <= SM_FIRST_DATA; else state <= next_state; end // Next state transitions. // Simple state machine to push data into the MC write data FIFO(WDF). // For BL4 only one data will be written into the WDF. For BL8 two // beats of data will be written into the WDF. always @(*) begin next_state = state; case (state) SM_FIRST_DATA: if(awvalid & wvalid_int & mc_app_wdf_rdy) next_state = SM_SECOND_DATA; else next_state = state; SM_SECOND_DATA: if(w_cmd_rdy) next_state = SM_FIRST_DATA; else next_state = state; default: next_state = SM_FIRST_DATA; endcase // case(state) end // always @ (*) // w_data_rdy to axi_mc_cmd_fsm when one Bl8 or Bl4 worth of write data // is pumped into to MC WDF. assign w_data_rdy = ((state == SM_SECOND_DATA) & (wvalid_int | w_ignore_end_r) & mc_app_wdf_rdy); // write enable signal to WDF assign assert_wren = ((state == SM_FIRST_DATA) & (next_state == SM_SECOND_DATA)) | ((state == SM_SECOND_DATA) & (next_state == SM_FIRST_DATA)); assign wdf_last = w_cmd_rdy; always @(posedge clk) begin w_ignore_end_r <= w_ignore_end; end // Disable data by asserting all the MASK signals based on the // ignore signals from the address modules assign disable_data = (((state == SM_FIRST_DATA) & w_ignore_begin) | ((state == SM_SECOND_DATA) & w_ignore_end_r)); end // if (C_MC_BURST_LEN == 1) endgenerate generate if(C_ECC == "ON") begin : gen_ecc if(C_MC_BURST_LEN == 1) begin : gen_ecc1 assign cmd_wr_bytes = |next_mc_app_wdf_mask; end else begin : gen_ecc2 wire mask_or; reg pre_mask_or; assign cmd_wr_bytes = (pre_mask_or | mask_or); assign mask_or = |next_mc_app_wdf_mask; always @(posedge clk) if (next_mc_app_wdf_wren & mc_app_wdf_rdy) pre_mask_or <= mask_or; end // if (C_MC_BURST_LEN == 1) end // if (C_ECC == "ON") endgenerate endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wr_cmd_fsm.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_wr_cmd_fsm.v // // Description: // Simple state machine to handle sending commands from AXI to MC. The flow: // 1. A transaction can only be initiaited when axvalid is true and data_rdy // is true. For writes, data_rdy means that one completed BL8 or BL4 write // data has been pushed into the MC write FIFOs. For read operations, // data_rdy indicates that there is enough room to push the transaction into // the read FIF & read transaction fifo in the shim. If the FIFO's in the // read channel module is full, then the state machine waits for the // FIFO's to drain out. // // 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in // a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command // has been accepted. When the command is accepted, if the next_pending // signal is high we will incremented to the next transaction and issue the // cmd_en again when data_rdy is high. Otherwise we will go to the done // state. // // 3. The AXI transaction can only complete when b_full is not true (for writes) // and no more mc transactions need to be issued. The AXREADY will be // asserted and the state machine will progress back to the the IDLE state. // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_wr_cmd_fsm #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // parameter to identify rd or wr instantation // = 1 rd , = 0 wr parameter integer C_MC_RD_INST = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , output reg axready , input wire axvalid , output wire cmd_en , input wire cmd_full , // signal to increment to the next mc transaction output wire next , // signal to the fsm there is another transaction required input wire next_pending , // Write Data portion has completed or Read FIFO has a slot available (not // full) input wire data_rdy , // status signal for w_channel when command is written. output wire b_push , input wire b_full , output wire cmd_en_last ); //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// assign cmd_en = (~b_full & axvalid & data_rdy); assign next = (~cmd_full & cmd_en); assign cmd_en_last = next & ~next_pending; assign b_push = cmd_en_last; always @(posedge clk) begin if (reset) axready <= 1'b0; else axready <= ~axvalid | cmd_en_last; end endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v ================================================ // -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. // -- /////////////////////////////////////////////////////////////////////////////// // // File name: axi_mc_wrap_cmd.v // // Description: // MC does not support an AXI WRAP command directly. // To complete an AXI WRAP transaction we will issue one transaction if the // address is wrap boundary aligned, otherwise two transactions are issued. // The first transaction is from the starting offset to the wrap address upper // boundary. The second transaction is from the wrap boundary lowest address // to the address offset. WRAP burst types will never exceed 16 beats. // // Calculates the number of MC beats for each axi transaction for WRAP // burst type ( for all axsize values = C_DATA_WIDTH ): // AR_SIZE | AR_LEN | OFFSET | NUM_BEATS 1 | NUM_BEATS 2 // b010( 4) | b0001( 2) | b0000 | 2 | 0 // b010( 4) | b0001( 2) | b0001 | 1 | 1 // b010( 4) | b0011( 4) | b0000 | 4 | 0 // b010( 4) | b0011( 4) | b0001 | 3 | 1 // b010( 4) | b0011( 4) | b0010 | 2 | 2 // b010( 4) | b0011( 4) | b0011 | 1 | 3 // b010( 4) | b0111( 8) | b0000 | 8 | 0 // b010( 4) | b0111( 8) | b0001 | 7 | 1 // b010( 4) | b0111( 8) | b0010 | 6 | 2 // b010( 4) | b0111( 8) | b0011 | 5 | 3 // b010( 4) | b0111( 8) | b0100 | 4 | 4 // b010( 4) | b0111( 8) | b0101 | 3 | 5 // b010( 4) | b0111( 8) | b0110 | 2 | 6 // b010( 4) | b0111( 8) | b0111 | 1 | 7 // b010( 4) | b1111( 16) | b0000 | 16 | 0 // b010( 4) | b1111( 16) | b0001 | 15 | 1 // b010( 4) | b1111( 16) | b0010 | 14 | 2 // b010( 4) | b1111( 16) | b0011 | 13 | 3 // b010( 4) | b1111( 16) | b0100 | 12 | 4 // b010( 4) | b1111( 16) | b0101 | 11 | 5 // b010( 4) | b1111( 16) | b0110 | 10 | 6 // b010( 4) | b1111( 16) | b0111 | 9 | 7 // b010( 4) | b1111( 16) | b1000 | 8 | 8 // b010( 4) | b1111( 16) | b1001 | 7 | 9 // b010( 4) | b1111( 16) | b1010 | 6 | 10 // b010( 4) | b1111( 16) | b1011 | 5 | 11 // b010( 4) | b1111( 16) | b1100 | 4 | 12 // b010( 4) | b1111( 16) | b1101 | 3 | 13 // b010( 4) | b1111( 16) | b1110 | 2 | 14 // b010( 4) | b1111( 16) | b1111 | 1 | 15 /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_axi_mc_wrap_cmd # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of cmd_byte_addr // Range: 30 parameter integer C_MC_ADDR_WIDTH = 30, // MC burst length. = 1 for BL4 or BC4, = 2 for BL8 parameter integer C_MC_BURST_LEN = 1, // Width of AXI xDATA and MC xx_data // Range: 32, 64, 128. parameter integer C_DATA_WIDTH = 32, // Static value of axsize // Range: 2-5 parameter integer C_AXSIZE = 2, // Instance for Read channel or write channel parameter integer C_MC_RD_INST = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , input wire [7:0] axlen , input wire [2:0] axsize , // C_AXSIZE parameter is used instead // axhandshake = axvalid & axready input wire axhandshake , output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr , output wire ignore_begin , output wire ignore_end , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output wire next_pending ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam P_AXLEN_WIDTH = 4; //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg sel_first_r; reg [3:0] axlen_cnt; reg [3:0] int_addr; reg int_next_pending_r; wire sel_first; wire [3:0] axlen_i; wire [3:0] axlen_cnt_i; wire [3:0] axlen_cnt_t; wire [3:0] axlen_cnt_p; wire addr_offset; wire [C_AXI_ADDR_WIDTH-1:0] axaddr_wrap; wire [3:0] int_addr_t; wire [3:0] int_addr_p; wire [3:0] int_addr_t_inc; wire int_next_pending; wire extra_cmd; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// assign cmd_byte_addr = axaddr_wrap; assign axlen_i = axlen[3:0]; assign axaddr_wrap = {axaddr[C_AXI_ADDR_WIDTH-1:C_AXSIZE+4], int_addr_t[3:0], axaddr[C_AXSIZE-1:0]}; generate if(C_MC_BURST_LEN == 1) begin assign addr_offset = 1'b0; assign int_addr_t = axhandshake ? (axaddr[C_AXSIZE+: 4]) : int_addr; end else begin // Figuring out if the address have an offset for padding data in BL8 case assign addr_offset = axaddr[C_AXSIZE]; if(C_MC_RD_INST == 0) // axhandshake & next won't occur in same cycle in Write channel 2:1 mode assign int_addr_t = int_addr; else assign int_addr_t = axhandshake ? (axaddr[C_AXSIZE+: 4]) : int_addr; end endgenerate assign int_addr_t_inc = int_addr_t + C_MC_BURST_LEN; assign int_addr_p = ((int_addr_t & ~axlen_i) | (int_addr_t_inc & axlen_i)); always @(posedge clk) begin if(reset) int_addr <= 4'h0; else if (axhandshake & ~next) int_addr <= (axaddr[C_AXSIZE+: 4]); else if(next) int_addr <= int_addr_p; end // assign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen_i : (extra_cmd ? ((axlen_i >> 1) + 1'b1) : (axlen_i >> 1)); assign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen_i : (axlen_i >> 1); assign axlen_cnt_t = axhandshake ? axlen_cnt_i : axlen_cnt; assign axlen_cnt_p = (axlen_cnt_t - 1'b1); always @(posedge clk) begin if(reset) axlen_cnt <= 4'hf; else if (axhandshake & ~next) axlen_cnt <= axlen_cnt_i; else if(next) axlen_cnt <= axlen_cnt_p; end assign extra_cmd = addr_offset; assign next_pending = extra_cmd ? int_next_pending_r : int_next_pending; assign int_next_pending = |axlen_cnt_t; always @(posedge clk) begin if(reset) int_next_pending_r <= 1'b1; else if(extra_cmd & next) int_next_pending_r <= int_next_pending; end // Ignore logic for first transaction assign ignore_begin = sel_first ? addr_offset : 1'b0; // Ignore logic for second transaction. assign ignore_end = next_pending ? 1'b0 : addr_offset; // Indicates if we are on the first transaction of a mc translation with more than 1 transaction. assign sel_first = (axhandshake | sel_first_r); always @(posedge clk) begin if (reset) sel_first_r <= 1'b0; else if(axhandshake & ~next) sel_first_r <= 1'b1; else if(next) sel_first_r <= 1'b0; end endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_a_upsizer.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Up-Sizer // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // ddr_a_upsizer // generic_baseblocks/* // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_a_upsizer # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of converter. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of converter. // Range: 32. parameter C_S_AXI_DATA_WIDTH = 32'h00000020, // Width of S_AXI_WDATA and S_AXI_RDATA. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter C_M_AXI_DATA_WIDTH = 32'h00000040, // Width of M_AXI_WDATA and M_AXI_RDATA. // Assume greater than or equal to C_S_AXI_DATA_WIDTH. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter integer C_M_AXI_REGISTER = 0, // Clock output data. // Range: 0, 1 parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AUSER_WIDTH = 1, // Width of AWUSER/ARUSER signals. // Range: >= 1. parameter integer C_AXI_CHANNEL = 0, // 0 = AXI AW Channel. // 1 = AXI AR Channel. parameter integer C_PACKING_LEVEL = 1, // 0 = Never pack (expander only); packing logic is omitted. // 1 = Pack only when CACHE[1] (Modifiable) is high. // 2 = Always pack, regardless of sub-size transaction or Modifiable bit. // (Required when used as helper-core by mem-con.) parameter integer C_SUPPORT_BURSTS = 1, // Disabled when all connected masters and slaves are AxiLite, // allowing logic to be simplified. parameter integer C_SINGLE_THREAD = 1, // 0 = Ignore ID when propagating transactions (assume all responses are in order). // 1 = Allow multiple outstanding transactions only if the IDs are the same // to prevent response reordering. // (If ID mismatches, stall until outstanding transaction counter = 0.) parameter integer C_S_AXI_BYTES_LOG = 3, // Log2 of number of 32bit word on SI-side. parameter integer C_M_AXI_BYTES_LOG = 3 // Log2 of number of 32bit word on MI-side. ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output wire cmd_valid, output wire cmd_fix, output wire cmd_modified, output wire cmd_complete_wrap, output wire cmd_packed_wrap, output wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word, output wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word, output wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word, output wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset, output wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask, output wire [C_S_AXI_BYTES_LOG:0] cmd_step, output wire [8-1:0] cmd_length, input wire cmd_ready, // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR, input wire [8-1:0] S_AXI_ALEN, input wire [3-1:0] S_AXI_ASIZE, input wire [2-1:0] S_AXI_ABURST, input wire [2-1:0] S_AXI_ALOCK, input wire [4-1:0] S_AXI_ACACHE, input wire [3-1:0] S_AXI_APROT, input wire [4-1:0] S_AXI_AREGION, input wire [4-1:0] S_AXI_AQOS, input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER, input wire S_AXI_AVALID, output wire S_AXI_AREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR, output wire [8-1:0] M_AXI_ALEN, output wire [3-1:0] M_AXI_ASIZE, output wire [2-1:0] M_AXI_ABURST, output wire [2-1:0] M_AXI_ALOCK, output wire [4-1:0] M_AXI_ACACHE, output wire [3-1:0] M_AXI_APROT, output wire [4-1:0] M_AXI_AREGION, output wire [4-1:0] M_AXI_AQOS, output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER, output wire M_AXI_AVALID, input wire M_AXI_AREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Decode the native transaction size on the SI-side interface. localparam [3-1:0] C_S_AXI_NATIVE_SIZE = (C_S_AXI_DATA_WIDTH == 1024) ? 3'b111 : (C_S_AXI_DATA_WIDTH == 512) ? 3'b110 : (C_S_AXI_DATA_WIDTH == 256) ? 3'b101 : (C_S_AXI_DATA_WIDTH == 128) ? 3'b100 : (C_S_AXI_DATA_WIDTH == 64) ? 3'b011 : (C_S_AXI_DATA_WIDTH == 32) ? 3'b010 : (C_S_AXI_DATA_WIDTH == 16) ? 3'b001 : 3'b000; // Decode the native transaction size on the MI-side interface. localparam [3-1:0] C_M_AXI_NATIVE_SIZE = (C_M_AXI_DATA_WIDTH == 1024) ? 3'b111 : (C_M_AXI_DATA_WIDTH == 512) ? 3'b110 : (C_M_AXI_DATA_WIDTH == 256) ? 3'b101 : (C_M_AXI_DATA_WIDTH == 128) ? 3'b100 : (C_M_AXI_DATA_WIDTH == 64) ? 3'b011 : (C_M_AXI_DATA_WIDTH == 32) ? 3'b010 : (C_M_AXI_DATA_WIDTH == 16) ? 3'b001 : 3'b000; // Constants used to generate maximum length on SI-side for complete wrap. localparam [24-1:0] C_DOUBLE_LEN = 24'b0000_0000_0000_0000_1111_1111; // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2'b00; localparam [2-1:0] C_INCR_BURST = 2'b01; localparam [2-1:0] C_WRAP_BURST = 2'b10; // Constants for packing levels. localparam integer C_NEVER_PACK = 0; localparam integer C_DEFAULT_PACK = 1; localparam integer C_ALWAYS_PACK = 2; // Depth for command FIFO. localparam integer C_FIFO_DEPTH_LOG = 5; // Maximum address bit coverage by WRAP. localparam integer C_BURST_BYTES_LOG = 4 + C_S_AXI_BYTES_LOG; // Calculate unused address bits. localparam integer C_SI_UNUSED_LOG = C_AXI_ADDR_WIDTH-C_S_AXI_BYTES_LOG; localparam integer C_MI_UNUSED_LOG = C_AXI_ADDR_WIDTH-C_M_AXI_BYTES_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Access decoding related signals. wire access_is_fix; wire access_is_incr; wire access_is_wrap; wire access_is_modifiable; wire access_is_unaligned; reg [8-1:0] si_maximum_length; wire [16-1:0] mi_word_intra_len_complete; wire [20-1:0] mask_help_vector; reg [C_M_AXI_BYTES_LOG-1:0] mi_word_intra_len; reg [8-1:0] upsized_length; wire sub_sized_wrap; reg [C_M_AXI_BYTES_LOG-1:0] size_mask; reg [C_BURST_BYTES_LOG-1:0] burst_mask; // Translation related signals. wire access_need_extra_word; wire [8-1:0] adjusted_length; wire [C_BURST_BYTES_LOG-1:0] wrap_addr_aligned; // Command buffer help signals. wire cmd_empty; reg [C_AXI_ID_WIDTH-1:0] queue_id; wire id_match; wire cmd_id_check; wire s_ready; wire cmd_full; wire allow_new_cmd; wire cmd_push; reg cmd_push_block; // Internal Command Interface signals. wire cmd_valid_i; wire cmd_fix_i; wire cmd_modified_i; wire cmd_complete_wrap_i; wire cmd_packed_wrap_i; wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_ii; wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_i; wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word_ii; wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word_i; wire [C_M_AXI_BYTES_LOG:0] cmd_last_word_ii; wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word_i; wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset_i; reg [C_M_AXI_BYTES_LOG-1:0] cmd_mask_i; wire [3-1:0] cmd_size_i; wire [3-1:0] cmd_size; reg [8-1:0] cmd_step_ii; wire [C_S_AXI_BYTES_LOG:0] cmd_step_i; reg [8-1:0] cmd_length_i; // Internal SI-side signals. wire S_AXI_AREADY_I; // Internal MI-side signals. wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I; reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I; reg [8-1:0] M_AXI_ALEN_I; reg [3-1:0] M_AXI_ASIZE_I; reg [2-1:0] M_AXI_ABURST_I; wire [2-1:0] M_AXI_ALOCK_I; wire [4-1:0] M_AXI_ACACHE_I; wire [3-1:0] M_AXI_APROT_I; wire [4-1:0] M_AXI_AREGION_I; wire [4-1:0] M_AXI_AQOS_I; wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I; wire M_AXI_AVALID_I; wire M_AXI_AREADY_I; ///////////////////////////////////////////////////////////////////////////// // Decode the incoming transaction: // // Determine the burst type sucha as FIX, INCR and WRAP. Only WRAP and INCR // transactions can be upsized to the MI-side data width. // Detect if the transaction is modifiable and if it is of native size. Only // native sized transaction are upsized when allowed, unless forced by // parameter. FIX can never be upsized (packed) regardless if force is // turned on. However the FIX data will be steered to the correct // byte lane(s) and the transaction will be native on MI-side when // applicable. // // Calculate the MI-side length for the SI-side transaction. // // Decode the affected address bits in the MI-side. Used to determine last // word for a burst and if necassarily adjust the length of the upsized // transaction. Length adjustment only occurs when the trasaction is longer // than can fit in MI-side and there is an unalignment for the first word // (and the last word crosses MI-word boundary and wraps). // // The maximum allowed SI-side length is calculated to be able to determine // if a WRAP transaction can fit inside a single MI-side data word. // // Determine address bits mask for the SI-side transaction size, i.e. address // bits that shall be removed for unalignment when managing data in W and // R channels. For example: the two least significant bits are not used // for data packing in a 32-bit SI-side transaction (address 1-3 will appear // as 0 for the W and R channels, but the untouched address is still forwarded // to the MI-side). // // Determine the Mask bits for the address bits that are affected by a // sub-sized WRAP transaction (up to and including complete WRAP). The Mask // is used to generate the correct data mapping for a sub-sized and // complete WRAP, i.e. having a local wrap in a partial MI-side word. // // Detect any SI-side address unalignment when used on the MI-side. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_fix = ( S_AXI_ABURST == C_FIX_BURST ); assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_ABURST == C_WRAP_BURST ); assign cmd_fix_i = access_is_fix; // Get if it is allowed to modify transaction. assign access_is_modifiable = S_AXI_ACACHE[1]; // Get SI-side maximum length to fit MI-side. always @ * begin case (S_AXI_ASIZE) 3'b000: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b000 ? C_DOUBLE_LEN[ 8-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b001: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b001 ? C_DOUBLE_LEN[ 9-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b010: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b010 ? C_DOUBLE_LEN[10-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b011: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b011 ? C_DOUBLE_LEN[11-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b100: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b100 ? C_DOUBLE_LEN[12-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b101: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b101 ? C_DOUBLE_LEN[13-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b110: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b110 ? C_DOUBLE_LEN[14-C_M_AXI_BYTES_LOG +: 8] : 8'b0; 3'b111: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b111 ? C_DOUBLE_LEN[15-C_M_AXI_BYTES_LOG +: 8] : 8'b0; endcase end // Help vector to determine the length of thransaction in the MI-side domain. assign mi_word_intra_len_complete = {S_AXI_ALEN, 8'b0}; // Get intra MI-side word length bits (in bytes). always @ * begin if ( C_SUPPORT_BURSTS == 1 ) begin if ( ~cmd_fix_i ) begin case (S_AXI_ASIZE) 3'b000: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mi_word_intra_len_complete[8-0 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b001: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b001 ? mi_word_intra_len_complete[8-1 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b010: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b010 ? mi_word_intra_len_complete[8-2 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b011: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b011 ? mi_word_intra_len_complete[8-3 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b100: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b100 ? mi_word_intra_len_complete[8-4 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b101: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b101 ? mi_word_intra_len_complete[8-5 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b110: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b110 ? mi_word_intra_len_complete[8-6 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b111: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b111 ? mi_word_intra_len_complete[8-7 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; // Illegal setting. endcase end else begin mi_word_intra_len = {C_M_AXI_BYTES_LOG{1'b0}}; end end else begin mi_word_intra_len = {C_M_AXI_BYTES_LOG{1'b0}}; end end // Get MI-side length after upsizing. always @ * begin if ( C_SUPPORT_BURSTS == 1 ) begin if ( cmd_fix_i | ~cmd_modified_i ) begin // Fix has to maintain length even if forced packing. upsized_length = S_AXI_ALEN; end else begin case (S_AXI_ASIZE) 3'b000: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b000 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-0) : 8'b0; 3'b001: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b001 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-1) : 8'b0; 3'b010: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b010 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-2) : 8'b0; 3'b011: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b011 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-3) : 8'b0; 3'b100: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b100 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-4) : 8'b0; 3'b101: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b101 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-5) : 8'b0; 3'b110: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b110 ? (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-6) : 8'b0; 3'b111: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b111 ? (S_AXI_ALEN ) : 8'b0; // Illegal setting. endcase end end else begin upsized_length = 8'b0; end end // Generate address bits used for SI-side transaction size. always @ * begin case (S_AXI_ASIZE) 3'b000: size_mask = ~C_DOUBLE_LEN[8 +: C_S_AXI_BYTES_LOG]; 3'b001: size_mask = ~C_DOUBLE_LEN[7 +: C_S_AXI_BYTES_LOG]; 3'b010: size_mask = ~C_DOUBLE_LEN[6 +: C_S_AXI_BYTES_LOG]; 3'b011: size_mask = ~C_DOUBLE_LEN[5 +: C_S_AXI_BYTES_LOG]; 3'b100: size_mask = ~C_DOUBLE_LEN[4 +: C_S_AXI_BYTES_LOG]; 3'b101: size_mask = ~C_DOUBLE_LEN[3 +: C_S_AXI_BYTES_LOG]; 3'b110: size_mask = ~C_DOUBLE_LEN[2 +: C_S_AXI_BYTES_LOG]; 3'b111: size_mask = ~C_DOUBLE_LEN[1 +: C_S_AXI_BYTES_LOG]; // Illegal setting. endcase end // Help vector to determine the length of thransaction in the MI-side domain. assign mask_help_vector = {4'b0, S_AXI_ALEN, 8'b1}; // Calculate the address bits that are affected when a complete wrap is detected. always @ * begin if ( sub_sized_wrap & ( C_SUPPORT_BURSTS == 1 ) ) begin case (S_AXI_ASIZE) 3'b000: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-0 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b001: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-1 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b010: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-2 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b011: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-3 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b100: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-4 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b101: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-5 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b110: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-6 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; 3'b111: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-7 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; // Illegal setting. endcase end else begin cmd_mask_i = {C_M_AXI_BYTES_LOG{1'b1}}; end end // Calculate the address bits that are affected when a complete wrap is detected. always @ * begin case (S_AXI_ASIZE) 3'b000: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-0 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b001: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-1 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b010: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-2 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b011: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-3 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b100: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-4 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b101: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-5 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b110: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-6 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; 3'b111: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? mask_help_vector[8-7 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; // Illegal setting. endcase end // Propagate the SI-side size of the transaction. assign cmd_size_i = S_AXI_ASIZE; // Detect if there is any unalignment in regards to the MI-side. assign access_is_unaligned = ( S_AXI_AADDR[0 +: C_M_AXI_BYTES_LOG] != {C_M_AXI_BYTES_LOG{1'b0}} ); ///////////////////////////////////////////////////////////////////////////// // Evaluate if transaction is to be translated: // * Forcefully translate when C_PACKING_LEVEL is set to C_ALWAYS_PACK. // * When SI-side transaction size is native, it is allowed and default // packing is set. (Expander mode never packs). // ///////////////////////////////////////////////////////////////////////////// // Modify transaction forcefully or when transaction allows it assign cmd_modified_i = ~access_is_fix & ( ( C_PACKING_LEVEL == C_ALWAYS_PACK ) | ( access_is_modifiable & ( S_AXI_ALEN != 8'b0 ) & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) ); ///////////////////////////////////////////////////////////////////////////// // Translate SI-side access to MI-side: // // Detemine if this is a complete WRAP. Conditions are that it must fit // inside a single MI-side data word, it must be a WRAP access and that // bursts are allowed. Without burst there can never be a WRAP access. // // Determine if this ia a packed WRAP, i.e. a WRAP that is to large to // be a complete wrap and it is unaligned SI-side address relative to // the native MI-side data width. // // The address for the First SI-side data word is adjusted to when there // is a complete WRAP, otherwise it only the least significant bits of the // SI-side address. // For complete WRAP access the Offset is generated as the most significant // bits that are left by the Mask. // Last address is calculated with the adjusted First word address. // // The Adjusted MI-side burst length is calculated as the Upsized length // plus one when the SI-side data must wrap on the MI-side (unless it is // a complete or packed WRAP). // // Depending on the conditions some of the forwarded MI-side tranaction // and Command Queue parameters has to be adjusted: // * For unmodified transaction the parameter are left un affected. // (M_AXI_AADDR, M_AXI_ASIZE, M_AXI_ABURST, M_AXI_ALEN and cmd_length // are untouched) // * For complete WRAP transactions the burst type is changed to INCR // and the address is adjusted to the sub-size affected by the transaction // (the sub-size can be 2 bytes up to a full MI-side data word). // The size is set to the native MI-side transaction size. And the length // is set to the calculated upsized length. // * For all other modified transations the address and burst type remains // the same. The length is adjusted to the previosly described length // and size is set to native MI-side transaction size. // ///////////////////////////////////////////////////////////////////////////// // Detemine if this is a sub-sized transaction. assign sub_sized_wrap = access_is_wrap & ( S_AXI_ALEN <= si_maximum_length ) & ( C_SUPPORT_BURSTS == 1); // See if entite burst can fit inside one MI-side word. assign cmd_complete_wrap_i = cmd_modified_i & sub_sized_wrap; // Detect if this is a packed WRAP (multiple MI-side words). assign cmd_packed_wrap_i = cmd_modified_i & access_is_wrap & ( S_AXI_ALEN > si_maximum_length ) & access_is_unaligned & ( C_SUPPORT_BURSTS == 1); // Get unalignment address bits (including aligning it inside covered area). assign cmd_first_word_ii = S_AXI_AADDR[C_M_AXI_BYTES_LOG-1:0]; assign cmd_first_word_i = cmd_first_word_ii & cmd_mask_i & size_mask; // Generate next word address. assign cmd_next_word_ii = cmd_first_word_ii + cmd_step_ii[C_M_AXI_BYTES_LOG-1:0]; assign cmd_next_word_i = cmd_next_word_ii & cmd_mask_i & size_mask; // Offset is the bits that is outside of the Mask. assign cmd_offset_i = cmd_first_word_ii & ~cmd_mask_i; // Select RTL or Optimized implementation. generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADJUSTED_LEN // Calculate Last word on MI-side. assign cmd_last_word_ii = cmd_first_word_i + mi_word_intra_len; assign cmd_last_word_i = cmd_last_word_ii[C_M_AXI_BYTES_LOG-1:0] & cmd_mask_i & size_mask; // Detect if extra word on MI-side is needed. assign access_need_extra_word = cmd_last_word_ii[C_M_AXI_BYTES_LOG] & access_is_incr & cmd_modified_i; // Calculate true length of modified transaction. assign adjusted_length = upsized_length + access_need_extra_word; end else begin : USE_FPGA_ADJUSTED_LEN wire [C_M_AXI_BYTES_LOG:0] last_word_local_carry; wire [C_M_AXI_BYTES_LOG-1:0] last_word_sel; wire [C_M_AXI_BYTES_LOG:0] last_word_for_mask_local_carry; wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry1; wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry2; wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry3; wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_sel; wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask; wire [C_M_AXI_BYTES_LOG-1:0] last_word_mask; wire sel_access_need_extra_word; wire [8:0] adjusted_length_local_carry; wire [8-1:0] adjusted_length_sel; assign last_word_local_carry[0] = 1'b0; assign last_word_for_mask_local_carry[0] = 1'b0; for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LAST_MASK assign last_word_for_mask_sel[bit_cnt] = cmd_first_word_ii[bit_cnt] ^ mi_word_intra_len[bit_cnt]; assign last_word_mask[bit_cnt] = cmd_mask_i[bit_cnt] & size_mask[bit_cnt]; MUXCY and_inst1 ( .O (last_word_for_mask_dummy_carry1[bit_cnt]), .CI (last_word_for_mask_local_carry[bit_cnt]), .DI (mi_word_intra_len[bit_cnt]), .S (last_word_for_mask_sel[bit_cnt]) ); MUXCY and_inst2 ( .O (last_word_for_mask_dummy_carry2[bit_cnt]), .CI (last_word_for_mask_dummy_carry1[bit_cnt]), .DI (1'b0), .S (1'b1) ); MUXCY and_inst3 ( .O (last_word_for_mask_dummy_carry3[bit_cnt]), .CI (last_word_for_mask_dummy_carry2[bit_cnt]), .DI (1'b0), .S (1'b1) ); MUXCY and_inst4 ( .O (last_word_for_mask_local_carry[bit_cnt+1]), .CI (last_word_for_mask_dummy_carry3[bit_cnt]), .DI (1'b0), .S (1'b1) ); XORCY xorcy_inst ( .O(last_word_for_mask[bit_cnt]), .CI(last_word_for_mask_local_carry[bit_cnt]), .LI(last_word_for_mask_sel[bit_cnt]) ); mig_7series_v4_0_ddr_carry_latch_and # ( .C_FAMILY(C_FAMILY) ) last_mask_inst ( .CIN(last_word_for_mask[bit_cnt]), .I(last_word_mask[bit_cnt]), .O(cmd_last_word_i[bit_cnt]) ); end // end for bit_cnt for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LAST assign last_word_sel[bit_cnt] = cmd_first_word_ii[bit_cnt] ^ mi_word_intra_len[bit_cnt]; MUXCY and_inst ( .O (last_word_local_carry[bit_cnt+1]), .CI (last_word_local_carry[bit_cnt]), .DI (mi_word_intra_len[bit_cnt]), .S (last_word_sel[bit_cnt]) ); XORCY xorcy_inst ( .O(cmd_last_word_ii[bit_cnt]), .CI(last_word_local_carry[bit_cnt]), .LI(last_word_sel[bit_cnt]) ); end // end for bit_cnt assign sel_access_need_extra_word = access_is_incr & cmd_modified_i; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) access_need_extra_word_inst ( .CIN(last_word_local_carry[C_M_AXI_BYTES_LOG]), .S(sel_access_need_extra_word), .COUT(adjusted_length_local_carry[0]) ); for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : LUT_ADJUST assign adjusted_length_sel[bit_cnt] = ( upsized_length[bit_cnt] & cmd_modified_i) | ( S_AXI_ALEN[bit_cnt] & ~cmd_modified_i); MUXCY and_inst ( .O (adjusted_length_local_carry[bit_cnt+1]), .CI (adjusted_length_local_carry[bit_cnt]), .DI (1'b0), .S (adjusted_length_sel[bit_cnt]) ); XORCY xorcy_inst ( .O(adjusted_length[bit_cnt]), .CI(adjusted_length_local_carry[bit_cnt]), .LI(adjusted_length_sel[bit_cnt]) ); end // end for bit_cnt end endgenerate // Generate adjusted wrap address. assign wrap_addr_aligned = ( C_AXI_CHANNEL != 0 ) ? ( S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] ) : ( S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] + ( 2 ** C_M_AXI_BYTES_LOG ) ); // Select directly forwarded or modified transaction. always @ * begin if ( cmd_modified_i ) begin // SI to MI-side transaction translation. if ( cmd_complete_wrap_i ) begin // Complete wrap is turned into incr M_AXI_AADDR_I = S_AXI_AADDR & {{C_MI_UNUSED_LOG{1'b1}}, ~cmd_mask_i}; M_AXI_ABURST_I = C_INCR_BURST; end else begin // Retain the currenent if ( cmd_packed_wrap_i ) begin M_AXI_AADDR_I = {S_AXI_AADDR[C_BURST_BYTES_LOG +: C_AXI_ADDR_WIDTH-C_BURST_BYTES_LOG], (S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] & ~burst_mask) | (wrap_addr_aligned & burst_mask) } & {{C_MI_UNUSED_LOG{1'b1}}, ~cmd_mask_i}; end else begin M_AXI_AADDR_I = S_AXI_AADDR; end M_AXI_ABURST_I = S_AXI_ABURST; end M_AXI_ASIZE_I = C_M_AXI_NATIVE_SIZE; end else begin // SI to MI-side transaction forwarding. M_AXI_AADDR_I = S_AXI_AADDR; M_AXI_ASIZE_I = S_AXI_ASIZE; M_AXI_ABURST_I = S_AXI_ABURST; end M_AXI_ALEN_I = adjusted_length; cmd_length_i = adjusted_length; end ///////////////////////////////////////////////////////////////////////////// // Forward the command to the MI-side interface. // // It is determined that this is an allowed command/access when there is // room in the command queue (and it passes any ID checks as required). // ///////////////////////////////////////////////////////////////////////////// // Select RTL or Optimized implementation. generate if ( C_FAMILY == "rtl" || ( C_SINGLE_THREAD == 0 ) ) begin : USE_RTL_AVALID // Only allowed to forward translated command when command queue is ok with it. assign M_AXI_AVALID_I = allow_new_cmd & S_AXI_AVALID; end else begin : USE_FPGA_AVALID wire sel_s_axi_avalid; assign sel_s_axi_avalid = S_AXI_AVALID & ~ARESET; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) avalid_inst ( .CIN(allow_new_cmd), .S(sel_s_axi_avalid), .COUT(M_AXI_AVALID_I) ); end endgenerate ///////////////////////////////////////////////////////////////////////////// // Simple transfer of paramters that doesn't need to be adjusted. // // ID - Transaction still recognized with the same ID. // LOCK - No need to change exclusive or barrier transactions. // CACHE - No need to change the chache features. Even if the modyfiable // bit is overridden (forcefully) there is no need to let downstream // component beleive it is ok to modify it further. // PROT - Security level of access is not changed when upsizing. // REGION - Address region stays the same. // QOS - Quality of Service remains the same. // USER - User bits remains the same. // ///////////////////////////////////////////////////////////////////////////// assign M_AXI_AID_I = S_AXI_AID; assign M_AXI_ALOCK_I = S_AXI_ALOCK; assign M_AXI_ACACHE_I = S_AXI_ACACHE; assign M_AXI_APROT_I = S_AXI_APROT; assign M_AXI_AREGION_I = S_AXI_AREGION; assign M_AXI_AQOS_I = S_AXI_AQOS; assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER : {C_AXI_AUSER_WIDTH{1'b0}}; ///////////////////////////////////////////////////////////////////////////// // Command queue to W/R channel. // // Commands can be pushed into the Cmd FIFO even if MI-side is stalling. // A flag is set if MI-side is stalling when Command is pushed to the // Cmd FIFO. This will prevent multiple push of the same Command as well as // keeping the MI-side Valid signal if the Allow Cmd requirement has been // updated to disable furter Commands (I.e. it is made sure that the SI-side // Command has been forwarded to both Cmd FIFO and MI-side). // // It is allowed to continue pushing new commands as long as // * There is room in the queue // * The ID is the same as previously queued. Since data is not reordered // for the same ID it is ok to let them proceed. // ///////////////////////////////////////////////////////////////////////////// // Keep track of current ID in queue. always @ (posedge ACLK) begin if (ARESET) begin queue_id <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( cmd_push ) begin // Store ID (it will be matching ID or a "new beginning"). queue_id <= S_AXI_AID; end end end // Select RTL or Optimized implementation. generate if ( C_FAMILY == "rtl" || ( C_SINGLE_THREAD == 0 ) ) begin : USE_RTL_ID_MATCH // Check ID to make sure this command is allowed. assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID); assign cmd_id_check = cmd_empty | ( id_match & ~cmd_empty ); // Check if it is allowed to push more commands (ID is allowed and there is room in the queue). assign allow_new_cmd = (~cmd_full & cmd_id_check) | cmd_push_block; // Push new command when allowed and MI-side is able to receive the command. assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block; end else begin : USE_FPGA_ID_MATCH wire cmd_id_check_i; wire allow_new_cmd_i; wire sel_cmd_id_check; wire sel_cmd_push; mig_7series_v4_0_ddr_comparator # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_AXI_ID_WIDTH) ) id_match_inst ( .CIN(1'b1), .A(queue_id), .B(S_AXI_AID), .COUT(id_match) ); assign sel_cmd_id_check = ~cmd_empty; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) cmd_id_check_inst_1 ( .CIN(id_match), .S(sel_cmd_id_check), .COUT(cmd_id_check_i) ); mig_7series_v4_0_ddr_carry_or # ( .C_FAMILY(C_FAMILY) ) cmd_id_check_inst_2 ( .CIN(cmd_id_check_i), .S(cmd_empty), .COUT(cmd_id_check) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) allow_new_cmd_inst_1 ( .CIN(cmd_id_check), .S(s_ready), .COUT(allow_new_cmd_i) ); mig_7series_v4_0_ddr_carry_or # ( .C_FAMILY(C_FAMILY) ) allow_new_cmd_inst_2 ( .CIN(allow_new_cmd_i), .S(cmd_push_block), .COUT(allow_new_cmd) ); assign sel_cmd_push = ~cmd_push_block; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) cmd_push_inst ( .CIN(M_AXI_AVALID_I), .S(sel_cmd_push), .COUT(cmd_push) ); end endgenerate // Block furter push until command has been forwarded to MI-side. always @ (posedge ACLK) begin if (ARESET) begin cmd_push_block <= 1'b0; end else begin cmd_push_block <= M_AXI_AVALID_I & ~M_AXI_AREADY_I; end end // Acknowledge command when we can push it into queue (and forward it). assign S_AXI_AREADY_I = M_AXI_AREADY_I & allow_new_cmd & ~ARESET; assign S_AXI_AREADY = S_AXI_AREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Instantiate a FIFO as the queue and adjust the control signals. // // Decode size to step before passing it along. // // When there is no need for bursts the command FIFO can be greatly reduced // becase the following is always true: // * first = last // * length = 0 // * nothing can be packed (i.e. no WRAP at all) // * never any sub-size wraping => static offset (0) and mask (1) // ///////////////////////////////////////////////////////////////////////////// // Translate SI-side size to step for upsizer function. always @ * begin case (cmd_size_i) 3'b000: cmd_step_ii = 8'b00000001; 3'b001: cmd_step_ii = 8'b00000010; 3'b010: cmd_step_ii = 8'b00000100; 3'b011: cmd_step_ii = 8'b00001000; 3'b100: cmd_step_ii = 8'b00010000; 3'b101: cmd_step_ii = 8'b00100000; 3'b110: cmd_step_ii = 8'b01000000; 3'b111: cmd_step_ii = 8'b10000000; // Illegal setting. endcase end // Get only the applicable bits in step. assign cmd_step_i = cmd_step_ii[C_S_AXI_BYTES_LOG:0]; // Instantiated queue. generate if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS mig_7series_v4_0_ddr_command_fifo # ( .C_FAMILY (C_FAMILY), .C_ENABLE_S_VALID_CARRY (1), .C_ENABLE_REGISTERED_OUTPUT (1), .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG), .C_FIFO_WIDTH (1+1+1+1+C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+ C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+C_S_AXI_BYTES_LOG+1+8) ) cmd_queue ( .ACLK (ACLK), .ARESET (ARESET), .EMPTY (cmd_empty), .S_MESG ({cmd_fix_i, cmd_modified_i, cmd_complete_wrap_i, cmd_packed_wrap_i, cmd_first_word_i, cmd_next_word_i, cmd_last_word_i, cmd_offset_i, cmd_mask_i, cmd_step_i, cmd_length_i}), .S_VALID (cmd_push), .S_READY (s_ready), .M_MESG ({cmd_fix, cmd_modified, cmd_complete_wrap, cmd_packed_wrap, cmd_first_word, cmd_next_word, cmd_last_word, cmd_offset, cmd_mask, cmd_step, cmd_length}), .M_VALID (cmd_valid_i), .M_READY (cmd_ready) ); end else begin : NO_BURSTS wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_out; mig_7series_v4_0_ddr_command_fifo # ( .C_FAMILY (C_FAMILY), .C_ENABLE_S_VALID_CARRY (1), .C_ENABLE_REGISTERED_OUTPUT (1), .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG), .C_FIFO_WIDTH (1+C_M_AXI_BYTES_LOG+C_S_AXI_BYTES_LOG+1) ) cmd_queue ( .ACLK (ACLK), .ARESET (ARESET), .EMPTY (cmd_empty), .S_MESG ({cmd_fix_i, cmd_first_word_i, cmd_step_i}), .S_VALID (cmd_push), .S_READY (s_ready), .M_MESG ({cmd_fix, cmd_first_word_out, cmd_step}), .M_VALID (cmd_valid_i), .M_READY (cmd_ready) ); assign cmd_modified = ( C_PACKING_LEVEL == C_ALWAYS_PACK ) ? 1'b1 : 1'b0; assign cmd_complete_wrap = 1'b0; assign cmd_packed_wrap = 1'b0; assign cmd_first_word = cmd_first_word_out; assign cmd_next_word = cmd_first_word_out; assign cmd_last_word = cmd_first_word_out; assign cmd_offset = {C_M_AXI_BYTES_LOG{1'b0}}; assign cmd_mask = {C_M_AXI_BYTES_LOG{1'b1}}; assign cmd_length = 8'b0; end endgenerate // Queue is concidered full when not ready. assign cmd_full = ~s_ready; // Assign external signal. assign cmd_valid = cmd_valid_i; ///////////////////////////////////////////////////////////////////////////// // MI-side output handling ///////////////////////////////////////////////////////////////////////////// generate if ( C_M_AXI_REGISTER ) begin : USE_REGISTER reg [C_AXI_ID_WIDTH-1:0] M_AXI_AID_q; reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_q; reg [8-1:0] M_AXI_ALEN_q; reg [3-1:0] M_AXI_ASIZE_q; reg [2-1:0] M_AXI_ABURST_q; reg [2-1:0] M_AXI_ALOCK_q; reg [4-1:0] M_AXI_ACACHE_q; reg [3-1:0] M_AXI_APROT_q; reg [4-1:0] M_AXI_AREGION_q; reg [4-1:0] M_AXI_AQOS_q; reg [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_q; reg M_AXI_AVALID_q; // Register MI-side Data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_AVALID_q <= 1'b0; end else if ( M_AXI_AREADY_I ) begin M_AXI_AVALID_q <= M_AXI_AVALID_I; end if ( M_AXI_AREADY_I ) begin M_AXI_AID_q <= M_AXI_AID_I; M_AXI_AADDR_q <= M_AXI_AADDR_I; M_AXI_ALEN_q <= M_AXI_ALEN_I; M_AXI_ASIZE_q <= M_AXI_ASIZE_I; M_AXI_ABURST_q <= M_AXI_ABURST_I; M_AXI_ALOCK_q <= M_AXI_ALOCK_I; M_AXI_ACACHE_q <= M_AXI_ACACHE_I; M_AXI_APROT_q <= M_AXI_APROT_I; M_AXI_AREGION_q <= M_AXI_AREGION_I; M_AXI_AQOS_q <= M_AXI_AQOS_I; M_AXI_AUSER_q <= M_AXI_AUSER_I; end end assign M_AXI_AID = M_AXI_AID_q; assign M_AXI_AADDR = M_AXI_AADDR_q; assign M_AXI_ALEN = M_AXI_ALEN_q; assign M_AXI_ASIZE = M_AXI_ASIZE_q; assign M_AXI_ABURST = M_AXI_ABURST_q; assign M_AXI_ALOCK = M_AXI_ALOCK_q; assign M_AXI_ACACHE = M_AXI_ACACHE_q; assign M_AXI_APROT = M_AXI_APROT_q; assign M_AXI_AREGION = M_AXI_AREGION_q; assign M_AXI_AQOS = M_AXI_AQOS_q; assign M_AXI_AUSER = M_AXI_AUSER_q; assign M_AXI_AVALID = M_AXI_AVALID_q; assign M_AXI_AREADY_I = ( M_AXI_AVALID_q & M_AXI_AREADY) | ~M_AXI_AVALID_q; end else begin : NO_REGISTER // Combinatorial MI-side Data. assign M_AXI_AID = M_AXI_AID_I; assign M_AXI_AADDR = M_AXI_AADDR_I; assign M_AXI_ALEN = M_AXI_ALEN_I; assign M_AXI_ASIZE = M_AXI_ASIZE_I; assign M_AXI_ABURST = M_AXI_ABURST_I; assign M_AXI_ALOCK = M_AXI_ALOCK_I; assign M_AXI_ACACHE = M_AXI_ACACHE_I; assign M_AXI_APROT = M_AXI_APROT_I; assign M_AXI_AREGION = M_AXI_AREGION_I; assign M_AXI_AQOS = M_AXI_AQOS_I; assign M_AXI_AUSER = M_AXI_AUSER_I; assign M_AXI_AVALID = M_AXI_AVALID_I; assign M_AXI_AREADY_I = M_AXI_AREADY; end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_register_slice.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // AXI Register Slice // Register selected channels on the forward and/or reverse signal paths. // 5-channel memory-mapped AXI4 interfaces. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // ddr_axi_register_slice // ddr_axic_register_slice // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_axi_register_slice # ( parameter C_FAMILY = "virtex6", parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, // C_REG_CONFIG_*: // 0 => BYPASS = The channel is just wired through the module. // 1 => FWD_REV = Both FWD and REV (fully-registered) // 2 => FWD = The master VALID and payload signals are registrated. // 3 => REV = The slave ready signal is registrated // 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated. // 5 => SLAVE_RDY = All slave side signals and master READY are registrated. // 6 => INPUTS = Slave and Master side inputs are registrated. // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining parameter C_REG_CONFIG_AW = 32'h00000000, parameter C_REG_CONFIG_W = 32'h00000000, parameter C_REG_CONFIG_B = 32'h00000000, parameter C_REG_CONFIG_AR = 32'h00000000, parameter C_REG_CONFIG_R = 32'h00000000 ) ( // System Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [8-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [4-1:0] S_AXI_AWREGION, input wire [4-1:0] S_AXI_AWQOS, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [8-1:0] S_AXI_ARLEN, input wire [3-1:0] S_AXI_ARSIZE, input wire [2-1:0] S_AXI_ARBURST, input wire [2-1:0] S_AXI_ARLOCK, input wire [4-1:0] S_AXI_ARCACHE, input wire [3-1:0] S_AXI_ARPROT, input wire [4-1:0] S_AXI_ARREGION, input wire [4-1:0] S_AXI_ARQOS, input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [8-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [4-1:0] M_AXI_AWREGION, output wire [4-1:0] M_AXI_AWQOS, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Master Interface Read Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [8-1:0] M_AXI_ARLEN, output wire [3-1:0] M_AXI_ARSIZE, output wire [2-1:0] M_AXI_ARBURST, output wire [2-1:0] M_AXI_ARLOCK, output wire [4-1:0] M_AXI_ARCACHE, output wire [3-1:0] M_AXI_ARPROT, output wire [4-1:0] M_AXI_ARREGION, output wire [4-1:0] M_AXI_ARQOS, output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire M_AXI_ARVALID, input wire M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); (* shift_extract="no", iob="false", equivalent_register_removal = "no" *) reg reset; always @(posedge ACLK) begin reset <= ~ARESETN; end // Write Address Port bit positions localparam C_AWUSER_RIGHT = 0; localparam C_AWUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_AWUSER_WIDTH; localparam C_AWQOS_RIGHT = C_AWUSER_RIGHT + C_AWUSER_LEN; localparam C_AWQOS_LEN = 4; localparam C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_LEN; localparam C_AWREGION_LEN = 4; localparam C_AWPROT_RIGHT = C_AWREGION_RIGHT + C_AWREGION_LEN; localparam C_AWPROT_LEN = 3; localparam C_AWCACHE_RIGHT = C_AWPROT_RIGHT + C_AWPROT_LEN; localparam C_AWCACHE_LEN = 4; localparam C_AWLOCK_RIGHT = C_AWCACHE_RIGHT + C_AWCACHE_LEN; localparam C_AWLOCK_LEN = 2; localparam C_AWBURST_RIGHT = C_AWLOCK_RIGHT + C_AWLOCK_LEN; localparam C_AWBURST_LEN = 2; localparam C_AWSIZE_RIGHT = C_AWBURST_RIGHT + C_AWBURST_LEN; localparam C_AWSIZE_LEN = 3; localparam C_AWLEN_RIGHT = C_AWSIZE_RIGHT + C_AWSIZE_LEN; localparam C_AWLEN_LEN = 8; localparam C_AWADDR_RIGHT = C_AWLEN_RIGHT + C_AWLEN_LEN; localparam C_AWADDR_LEN = C_AXI_ADDR_WIDTH; localparam C_AWID_RIGHT = C_AWADDR_RIGHT + C_AWADDR_LEN; localparam C_AWID_LEN = C_AXI_ID_WIDTH; localparam C_AW_SIZE = C_AWID_RIGHT+C_AWID_LEN; // Write Address Port FIFO data read and write wire [C_AW_SIZE-1:0] s_aw_data ; wire [C_AW_SIZE-1:0] m_aw_data ; // Write Data Port bit positions localparam C_WUSER_RIGHT = 0; localparam C_WUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_WUSER_WIDTH; localparam C_WLAST_RIGHT = C_WUSER_RIGHT + C_WUSER_LEN; localparam C_WLAST_LEN = 1; localparam C_WSTRB_RIGHT = C_WLAST_RIGHT + C_WLAST_LEN; localparam C_WSTRB_LEN = C_AXI_DATA_WIDTH/8; localparam C_WDATA_RIGHT = C_WSTRB_RIGHT + C_WSTRB_LEN; localparam C_WDATA_LEN = C_AXI_DATA_WIDTH; localparam C_WID_RIGHT = C_WDATA_RIGHT + C_WDATA_LEN; localparam C_WID_LEN = C_AXI_ID_WIDTH; localparam C_W_SIZE = C_WID_RIGHT+C_WID_LEN; // Write Data Port FIFO data read and write wire [C_W_SIZE-1:0] s_w_data; wire [C_W_SIZE-1:0] m_w_data; // Write Response Port bit positions localparam C_BUSER_RIGHT = 0; localparam C_BUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_BUSER_WIDTH; localparam C_BRESP_RIGHT = C_BUSER_RIGHT + C_BUSER_LEN; localparam C_BRESP_LEN = 2; localparam C_BID_RIGHT = C_BRESP_RIGHT + C_BRESP_LEN; localparam C_BID_LEN = C_AXI_ID_WIDTH; localparam C_B_SIZE = C_BID_RIGHT+C_BID_LEN; // Write Response Port FIFO data read and write wire [C_B_SIZE-1:0] s_b_data; wire [C_B_SIZE-1:0] m_b_data; // Read Address Port bit positions localparam C_ARUSER_RIGHT = 0; localparam C_ARUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_ARUSER_WIDTH; localparam C_ARQOS_RIGHT = C_ARUSER_RIGHT + C_ARUSER_LEN; localparam C_ARQOS_LEN = 4; localparam C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_LEN; localparam C_ARREGION_LEN = 4; localparam C_ARPROT_RIGHT = C_ARREGION_RIGHT + C_ARREGION_LEN; localparam C_ARPROT_LEN = 3; localparam C_ARCACHE_RIGHT = C_ARPROT_RIGHT + C_ARPROT_LEN; localparam C_ARCACHE_LEN = 4; localparam C_ARLOCK_RIGHT = C_ARCACHE_RIGHT + C_ARCACHE_LEN; localparam C_ARLOCK_LEN = 2; localparam C_ARBURST_RIGHT = C_ARLOCK_RIGHT + C_ARLOCK_LEN; localparam C_ARBURST_LEN = 2; localparam C_ARSIZE_RIGHT = C_ARBURST_RIGHT + C_ARBURST_LEN; localparam C_ARSIZE_LEN = 3; localparam C_ARLEN_RIGHT = C_ARSIZE_RIGHT + C_ARSIZE_LEN; localparam C_ARLEN_LEN = 8; localparam C_ARADDR_RIGHT = C_ARLEN_RIGHT + C_ARLEN_LEN; localparam C_ARADDR_LEN = C_AXI_ADDR_WIDTH; localparam C_ARID_RIGHT = C_ARADDR_RIGHT + C_ARADDR_LEN; localparam C_ARID_LEN = C_AXI_ID_WIDTH; localparam C_AR_SIZE = C_ARID_RIGHT+C_ARID_LEN; // Read Address Port FIFO data read and write wire [C_AR_SIZE-1:0] s_ar_data; wire [C_AR_SIZE-1:0] m_ar_data; // Read Data Ports bit positions localparam C_RUSER_RIGHT = 0; localparam C_RUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_RUSER_WIDTH; localparam C_RLAST_RIGHT = C_RUSER_RIGHT + C_RUSER_LEN; localparam C_RLAST_LEN = 1; localparam C_RRESP_RIGHT = C_RLAST_RIGHT + C_RLAST_LEN; localparam C_RRESP_LEN = 2; localparam C_RDATA_RIGHT = C_RRESP_RIGHT + C_RRESP_LEN; localparam C_RDATA_LEN = C_AXI_DATA_WIDTH; localparam C_RID_RIGHT = C_RDATA_RIGHT + C_RDATA_LEN; localparam C_RID_LEN = C_AXI_ID_WIDTH; localparam C_R_SIZE = C_RID_RIGHT+C_RID_LEN; // Read Data Ports FIFO data read and write wire [C_R_SIZE-1:0] s_r_data; wire [C_R_SIZE-1:0] m_r_data; generate /////////////////////////////////////////////////////// // // AW PIPE // /////////////////////////////////////////////////////// if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_aw_user assign s_aw_data = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE, S_AXI_AWBURST, S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT, S_AXI_AWREGION, S_AXI_AWQOS, S_AXI_AWUSER}; assign M_AXI_AWUSER = m_aw_data[C_AWUSER_RIGHT+:C_AWUSER_LEN]; end else begin : gen_asynch_aw_no_user assign s_aw_data = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE, S_AXI_AWBURST, S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT, S_AXI_AWREGION, S_AXI_AWQOS}; assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}}; end assign M_AXI_AWID = m_aw_data[C_AWID_RIGHT+:C_AWID_LEN]; assign M_AXI_AWADDR = m_aw_data[C_AWADDR_RIGHT+:C_AWADDR_LEN]; assign M_AXI_AWLEN = m_aw_data[C_AWLEN_RIGHT+:C_AWLEN_LEN]; assign M_AXI_AWSIZE = m_aw_data[C_AWSIZE_RIGHT+:C_AWSIZE_LEN]; assign M_AXI_AWBURST = m_aw_data[C_AWBURST_RIGHT+:C_AWBURST_LEN]; assign M_AXI_AWLOCK = m_aw_data[C_AWLOCK_RIGHT+:C_AWLOCK_LEN]; assign M_AXI_AWCACHE = m_aw_data[C_AWCACHE_RIGHT+:C_AWCACHE_LEN]; assign M_AXI_AWPROT = m_aw_data[C_AWPROT_RIGHT+:C_AWPROT_LEN]; assign M_AXI_AWREGION = m_aw_data[C_AWREGION_RIGHT+:C_AWREGION_LEN]; assign M_AXI_AWQOS = m_aw_data[C_AWQOS_RIGHT+:C_AWQOS_LEN]; mig_7series_v4_0_ddr_axic_register_slice # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_AW_SIZE), .C_REG_CONFIG(C_REG_CONFIG_AW) ) aw_pipe ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(s_aw_data), .S_VALID(S_AXI_AWVALID), .S_READY(S_AXI_AWREADY), // Master side .M_PAYLOAD_DATA(m_aw_data), .M_VALID(M_AXI_AWVALID), .M_READY(M_AXI_AWREADY) ); /////////////////////////////////////////////////////// // // Data Write PIPE // /////////////////////////////////////////////////////// if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_w_user assign s_w_data = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST, S_AXI_WUSER}; assign M_AXI_WUSER = m_w_data[C_WUSER_RIGHT+:C_WUSER_LEN]; end else begin : gen_asynch_w_no_user assign s_w_data = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST}; assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}}; end assign M_AXI_WID = m_w_data[C_WID_RIGHT+:C_WID_LEN]; assign M_AXI_WDATA = m_w_data[C_WDATA_RIGHT+:C_WDATA_LEN]; assign M_AXI_WSTRB = m_w_data[C_WSTRB_RIGHT+:C_WSTRB_LEN]; assign M_AXI_WLAST = m_w_data[C_WLAST_RIGHT+:C_WLAST_LEN]; mig_7series_v4_0_ddr_axic_register_slice # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_W_SIZE), .C_REG_CONFIG(C_REG_CONFIG_W) ) w_pipe ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(s_w_data), .S_VALID(S_AXI_WVALID), .S_READY(S_AXI_WREADY), // Master side .M_PAYLOAD_DATA(m_w_data), .M_VALID(M_AXI_WVALID), .M_READY(M_AXI_WREADY) ); /////////////////////////////////////////////////////// // // Write Response PIPE // /////////////////////////////////////////////////////// if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_b_user assign m_b_data = {M_AXI_BID, M_AXI_BRESP, M_AXI_BUSER}; assign S_AXI_BUSER = s_b_data[C_BUSER_RIGHT+:C_BUSER_LEN]; end else begin : gen_asynch_b_no_user assign m_b_data = {M_AXI_BID, M_AXI_BRESP}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; end assign S_AXI_BID = s_b_data[C_BID_RIGHT+:C_BID_LEN]; assign S_AXI_BRESP = s_b_data[C_BRESP_RIGHT+:C_BRESP_LEN]; mig_7series_v4_0_ddr_axic_register_slice # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_B_SIZE), .C_REG_CONFIG(C_REG_CONFIG_B) ) b_pipe ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(m_b_data), .S_VALID(M_AXI_BVALID), .S_READY(M_AXI_BREADY), // Master side .M_PAYLOAD_DATA(s_b_data), .M_VALID(S_AXI_BVALID), .M_READY(S_AXI_BREADY) ); /////////////////////////////////////////////////////// // // Address Read PIPE // /////////////////////////////////////////////////////// if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_ar_user assign s_ar_data = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE, S_AXI_ARBURST, S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT, S_AXI_ARREGION, S_AXI_ARQOS, S_AXI_ARUSER}; assign M_AXI_ARUSER = m_ar_data[C_ARUSER_RIGHT+:C_ARUSER_LEN]; end else begin : gen_asynch_ar_no_user assign s_ar_data = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE, S_AXI_ARBURST, S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT, S_AXI_ARREGION, S_AXI_ARQOS}; assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}}; end assign M_AXI_ARID = m_ar_data[C_ARID_RIGHT+:C_ARID_LEN]; assign M_AXI_ARADDR = m_ar_data[C_ARADDR_RIGHT+:C_ARADDR_LEN]; assign M_AXI_ARLEN = m_ar_data[C_ARLEN_RIGHT+:C_ARLEN_LEN]; assign M_AXI_ARSIZE = m_ar_data[C_ARSIZE_RIGHT+:C_ARSIZE_LEN]; assign M_AXI_ARBURST = m_ar_data[C_ARBURST_RIGHT+:C_ARBURST_LEN]; assign M_AXI_ARLOCK = m_ar_data[C_ARLOCK_RIGHT+:C_ARLOCK_LEN]; assign M_AXI_ARCACHE = m_ar_data[C_ARCACHE_RIGHT+:C_ARCACHE_LEN]; assign M_AXI_ARPROT = m_ar_data[C_ARPROT_RIGHT+:C_ARPROT_LEN]; assign M_AXI_ARREGION = m_ar_data[C_ARREGION_RIGHT+:C_ARREGION_LEN]; assign M_AXI_ARQOS = m_ar_data[C_ARQOS_RIGHT+:C_ARQOS_LEN]; mig_7series_v4_0_ddr_axic_register_slice # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_AR_SIZE), .C_REG_CONFIG(C_REG_CONFIG_AR) ) ar_pipe ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(s_ar_data), .S_VALID(S_AXI_ARVALID), .S_READY(S_AXI_ARREADY), // Master side .M_PAYLOAD_DATA(m_ar_data), .M_VALID(M_AXI_ARVALID), .M_READY(M_AXI_ARREADY) ); /////////////////////////////////////////////////////// // // Data Read PIPE // /////////////////////////////////////////////////////// if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_r_user assign m_r_data = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST, M_AXI_RUSER}; assign S_AXI_RUSER = s_r_data[C_RUSER_RIGHT+:C_RUSER_LEN]; end else begin : gen_asynch_r_no_user assign m_r_data = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; end assign S_AXI_RID = s_r_data[C_RID_RIGHT+:C_RID_LEN]; assign S_AXI_RDATA = s_r_data[C_RDATA_RIGHT+:C_RDATA_LEN]; assign S_AXI_RRESP = s_r_data[C_RRESP_RIGHT+:C_RRESP_LEN]; assign S_AXI_RLAST = s_r_data[C_RLAST_RIGHT+:C_RLAST_LEN]; mig_7series_v4_0_ddr_axic_register_slice # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_R_SIZE), .C_REG_CONFIG(C_REG_CONFIG_R) ) r_pipe ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(m_r_data), .S_VALID(M_AXI_RVALID), .S_READY(M_AXI_RREADY), // Master side .M_PAYLOAD_DATA(s_r_data), .M_VALID(S_AXI_RVALID), .M_READY(S_AXI_RREADY) ); endgenerate endmodule // ddr_axi_register_slice ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_upsizer.v ================================================ //----------------------------------------------------------------------------- //-- (c) Copyright 2013 Xilinx, Inc. All rights reserved. //-- //-- This file contains confidential and proprietary information //-- of Xilinx, Inc. and is protected under U.S. and //-- international copyright and other intellectual property //-- laws. //-- //-- DISCLAIMER //-- This disclaimer is not a license and does not grant any //-- rights to the materials distributed herewith. Except as //-- otherwise provided in a valid license issued to you by //-- Xilinx, and to the maximum extent permitted by applicable //-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND //-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES //-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING //-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- //-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and //-- (2) Xilinx shall not be liable (whether in contract or tort, //-- including negligence, or under any other theory of //-- liability) for any loss or damage of any kind or nature //-- related to, arising under or in connection with these //-- materials, including for any direct, or any indirect, //-- special, incidental, or consequential loss or damage //-- (including loss of data, profits, goodwill, or any type of //-- loss or damage suffered as a result of any action brought //-- by a third party) even if such damage or loss was //-- reasonably foreseeable or Xilinx had been advised of the //-- possibility of the same. //-- //-- CRITICAL APPLICATIONS //-- Xilinx products are not designed or intended to be fail- //-- safe, or for use in any application requiring fail-safe //-- performance, such as life-support or safety devices or //-- systems, Class III medical devices, nuclear facilities, //-- applications related to the deployment of airbags, or any //-- other applications that could lead to death, personal //-- injury, or severe property or environmental damage //-- (individually and collectively, "Critical //-- Applications"). Customer assumes the sole risk and //-- liability of any use of Xilinx products in Critical //-- Applications, subject only to applicable laws and //-- regulations governing limitations on product liability. //-- //-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS //-- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Up-Sizer // Up-Sizer for generic SI- and MI-side data widths. This module instantiates // Address, Write Data and Read Data Up-Sizer modules, each one taking care // of the channel specific tasks. // The Address Up-Sizer can handle both AR and AW channels. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // ddr_axi_upsizer // ddr_a_upsizer // fifo // fifo_gen // fifo_coregen // ddr_w_upsizer // ddr_r_upsizer // //-------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none module mig_7series_v4_0_ddr_axi_upsizer # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of converter. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of converter. // Range: 32. parameter C_S_AXI_DATA_WIDTH = 32'h00000020, // Width of S_AXI_WDATA and S_AXI_RDATA. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter C_M_AXI_DATA_WIDTH = 32'h00000040, // Width of M_AXI_WDATA and M_AXI_RDATA. // Assume greater than or equal to C_S_AXI_DATA_WIDTH. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter integer C_M_AXI_AW_REGISTER = 0, // Simple register AW output. // Range: 0, 1 parameter integer C_M_AXI_W_REGISTER = 1, // Parameter not used; W reg always implemented. parameter integer C_M_AXI_AR_REGISTER = 0, // Simple register AR output. // Range: 0, 1 parameter integer C_S_AXI_R_REGISTER = 0, // Simple register R output (SI). // Range: 0, 1 parameter integer C_M_AXI_R_REGISTER = 1, // Register slice on R input (MI) side. // 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path) // 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio) // 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect) parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals. // Range: >= 1. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals. // Range: >= 1. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals. // Range: >= 1. parameter integer C_AXI_SUPPORTS_WRITE = 1, parameter integer C_AXI_SUPPORTS_READ = 1, parameter integer C_PACKING_LEVEL = 1, // 0 = Never pack (expander only); packing logic is omitted. // 1 = Pack only when CACHE[1] (Modifiable) is high. // 2 = Always pack, regardless of sub-size transaction or Modifiable bit. // (Required when used as helper-core by mem-con. Same size AXI interfaces // should only be used when always packing) parameter integer C_SUPPORT_BURSTS = 1, // Disabled when all connected masters and slaves are AxiLite, // allowing logic to be simplified. parameter integer C_SINGLE_THREAD = 1 // 0 = Ignore ID when propagating transactions (assume all responses are in order). // 1 = Allow multiple outstanding transactions only if the IDs are the same // to prevent response reordering. // (If ID mismatches, stall until outstanding transaction counter = 0.) ) ( // Global Signals input wire ARESETN, input wire ACLK, // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [8-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [4-1:0] S_AXI_AWREGION, input wire [4-1:0] S_AXI_AWQOS, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [8-1:0] S_AXI_ARLEN, input wire [3-1:0] S_AXI_ARSIZE, input wire [2-1:0] S_AXI_ARBURST, input wire [2-1:0] S_AXI_ARLOCK, input wire [4-1:0] S_AXI_ARCACHE, input wire [3-1:0] S_AXI_ARPROT, input wire [4-1:0] S_AXI_ARREGION, input wire [4-1:0] S_AXI_ARQOS, input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [8-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [4-1:0] M_AXI_AWREGION, output wire [4-1:0] M_AXI_AWQOS, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Master Interface Read Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [8-1:0] M_AXI_ARLEN, output wire [3-1:0] M_AXI_ARSIZE, output wire [2-1:0] M_AXI_ARBURST, output wire [2-1:0] M_AXI_ARLOCK, output wire [4-1:0] M_AXI_ARCACHE, output wire [3-1:0] M_AXI_ARPROT, output wire [4-1:0] M_AXI_ARREGION, output wire [4-1:0] M_AXI_ARQOS, output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire M_AXI_ARVALID, input wire M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// // Log2. function integer log2; input integer value; begin for (log2=0; value>1; log2=log2+1) begin value = value >> 1; end end endfunction ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Log2 of number of 32bit word on SI-side. localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8); // Log2 of number of 32bit word on MI-side. localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8); // Log2 of Up-Sizing ratio for data. localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH; localparam integer C_RATIO_LOG = log2(C_RATIO); localparam P_BYPASS = 32'h0; localparam P_LIGHTWT = 32'h7; localparam P_FWD_REV = 32'h1; ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_AXI_ID_WIDTH-1:0] sr_AWID ; wire [C_AXI_ADDR_WIDTH-1:0] sr_AWADDR ; wire [8-1:0] sr_AWLEN ; wire [3-1:0] sr_AWSIZE ; wire [2-1:0] sr_AWBURST ; wire [2-1:0] sr_AWLOCK ; wire [4-1:0] sr_AWCACHE ; wire [3-1:0] sr_AWPROT ; wire [4-1:0] sr_AWREGION ; wire [4-1:0] sr_AWQOS ; wire [C_AXI_AWUSER_WIDTH-1:0] sr_AWUSER ; wire sr_AWVALID ; wire sr_AWREADY ; wire [C_AXI_ID_WIDTH-1:0] sr_ARID ; wire [C_AXI_ADDR_WIDTH-1:0] sr_ARADDR ; wire [8-1:0] sr_ARLEN ; wire [3-1:0] sr_ARSIZE ; wire [2-1:0] sr_ARBURST ; wire [2-1:0] sr_ARLOCK ; wire [4-1:0] sr_ARCACHE ; wire [3-1:0] sr_ARPROT ; wire [4-1:0] sr_ARREGION ; wire [4-1:0] sr_ARQOS ; wire [C_AXI_ARUSER_WIDTH-1:0] sr_ARUSER ; wire sr_ARVALID ; wire sr_ARREADY ; wire [C_S_AXI_DATA_WIDTH-1:0] sr_WDATA ; wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_WSTRB ; wire sr_WLAST ; wire sr_WVALID ; wire sr_WREADY ; wire [C_AXI_ID_WIDTH-1:0] mr_RID ; wire [C_M_AXI_DATA_WIDTH-1:0] mr_RDATA ; wire [2-1:0] mr_RRESP ; wire mr_RLAST ; wire [C_AXI_RUSER_WIDTH-1:0] mr_RUSER ; wire mr_RVALID ; wire mr_RREADY ; (* max_fanout = 100 *) reg ARESET ; assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; mig_7series_v4_0_ddr_axi_register_slice # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS), .C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS) ) si_register_slice_inst ( .ARESETN (ARESETN), .ACLK (ACLK), .S_AXI_AWID (S_AXI_AWID ), .S_AXI_AWADDR (S_AXI_AWADDR ), .S_AXI_AWLEN (S_AXI_AWLEN ), .S_AXI_AWSIZE (S_AXI_AWSIZE ), .S_AXI_AWBURST (S_AXI_AWBURST ), .S_AXI_AWLOCK (S_AXI_AWLOCK ), .S_AXI_AWCACHE (S_AXI_AWCACHE ), .S_AXI_AWPROT (S_AXI_AWPROT ), .S_AXI_AWREGION (S_AXI_AWREGION ), .S_AXI_AWQOS (S_AXI_AWQOS ), .S_AXI_AWUSER (S_AXI_AWUSER ), .S_AXI_AWVALID (S_AXI_AWVALID ), .S_AXI_AWREADY (S_AXI_AWREADY ), .S_AXI_WID ( {C_AXI_ID_WIDTH{1'b0}}), .S_AXI_WDATA ( {C_S_AXI_DATA_WIDTH{1'b0}} ), .S_AXI_WSTRB ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ), .S_AXI_WLAST ( 1'b0 ), .S_AXI_WUSER ( 1'b0 ), .S_AXI_WVALID ( 1'b0 ), .S_AXI_WREADY ( ), .S_AXI_BID ( ), .S_AXI_BRESP ( ), .S_AXI_BUSER ( ), .S_AXI_BVALID ( ), .S_AXI_BREADY ( 1'b0 ), .S_AXI_ARID (S_AXI_ARID ), .S_AXI_ARADDR (S_AXI_ARADDR ), .S_AXI_ARLEN (S_AXI_ARLEN ), .S_AXI_ARSIZE (S_AXI_ARSIZE ), .S_AXI_ARBURST (S_AXI_ARBURST ), .S_AXI_ARLOCK (S_AXI_ARLOCK ), .S_AXI_ARCACHE (S_AXI_ARCACHE ), .S_AXI_ARPROT (S_AXI_ARPROT ), .S_AXI_ARREGION (S_AXI_ARREGION ), .S_AXI_ARQOS (S_AXI_ARQOS ), .S_AXI_ARUSER (S_AXI_ARUSER ), .S_AXI_ARVALID (S_AXI_ARVALID ), .S_AXI_ARREADY (S_AXI_ARREADY ), .S_AXI_RID ( ) , .S_AXI_RDATA ( ) , .S_AXI_RRESP ( ) , .S_AXI_RLAST ( ) , .S_AXI_RUSER ( ) , .S_AXI_RVALID ( ) , .S_AXI_RREADY ( 1'b0 ) , .M_AXI_AWID (sr_AWID ), .M_AXI_AWADDR (sr_AWADDR ), .M_AXI_AWLEN (sr_AWLEN ), .M_AXI_AWSIZE (sr_AWSIZE ), .M_AXI_AWBURST (sr_AWBURST ), .M_AXI_AWLOCK (sr_AWLOCK ), .M_AXI_AWCACHE (sr_AWCACHE ), .M_AXI_AWPROT (sr_AWPROT ), .M_AXI_AWREGION (sr_AWREGION ), .M_AXI_AWQOS (sr_AWQOS ), .M_AXI_AWUSER (sr_AWUSER ), .M_AXI_AWVALID (sr_AWVALID ), .M_AXI_AWREADY (sr_AWREADY ), .M_AXI_WID () , .M_AXI_WDATA (), .M_AXI_WSTRB (), .M_AXI_WLAST (), .M_AXI_WUSER (), .M_AXI_WVALID (), .M_AXI_WREADY (1'b0), .M_AXI_BID ( {C_AXI_ID_WIDTH{1'b0}} ) , .M_AXI_BRESP ( 2'b0 ) , .M_AXI_BUSER ( 1'b0 ) , .M_AXI_BVALID ( 1'b0 ) , .M_AXI_BREADY ( ) , .M_AXI_ARID (sr_ARID ), .M_AXI_ARADDR (sr_ARADDR ), .M_AXI_ARLEN (sr_ARLEN ), .M_AXI_ARSIZE (sr_ARSIZE ), .M_AXI_ARBURST (sr_ARBURST ), .M_AXI_ARLOCK (sr_ARLOCK ), .M_AXI_ARCACHE (sr_ARCACHE ), .M_AXI_ARPROT (sr_ARPROT ), .M_AXI_ARREGION (sr_ARREGION ), .M_AXI_ARQOS (sr_ARQOS ), .M_AXI_ARUSER (sr_ARUSER ), .M_AXI_ARVALID (sr_ARVALID ), .M_AXI_ARREADY (sr_ARREADY ), .M_AXI_RID ( {C_AXI_ID_WIDTH{1'b0}}), .M_AXI_RDATA ( {C_S_AXI_DATA_WIDTH{1'b0}} ), .M_AXI_RRESP ( 2'b00 ), .M_AXI_RLAST ( 1'b0 ), .M_AXI_RUSER ( 1'b0 ), .M_AXI_RVALID ( 1'b0 ), .M_AXI_RREADY ( ) ); mig_7series_v4_0_ddr_axi_register_slice # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_REG_CONFIG_R (C_AXI_SUPPORTS_READ ? C_M_AXI_R_REGISTER : P_BYPASS) ) mi_register_slice_inst ( .ARESETN (ARESETN), .ACLK (ACLK), .S_AXI_AWID ({C_AXI_ID_WIDTH{1'b0}} ), .S_AXI_AWADDR ( {C_AXI_ADDR_WIDTH{1'b0}} ), .S_AXI_AWLEN ( 8'b0 ), .S_AXI_AWSIZE ( 3'b0 ), .S_AXI_AWBURST ( 2'b0 ), .S_AXI_AWLOCK ( 2'b0 ), .S_AXI_AWCACHE ( 4'b0 ), .S_AXI_AWPROT ( 3'b0 ), .S_AXI_AWREGION ( 4'b0 ), .S_AXI_AWQOS ( 4'b0 ), .S_AXI_AWUSER ( 1'b0 ), .S_AXI_AWVALID ( 1'b0 ), .S_AXI_AWREADY ( ), .S_AXI_WID ( {C_AXI_ID_WIDTH{1'b0}}), .S_AXI_WDATA ( {C_M_AXI_DATA_WIDTH{1'b0}} ), .S_AXI_WSTRB ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ), .S_AXI_WLAST ( 1'b0 ), .S_AXI_WUSER ( 1'b0 ), .S_AXI_WVALID ( 1'b0 ), .S_AXI_WREADY ( ), .S_AXI_BID ( ), .S_AXI_BRESP ( ), .S_AXI_BUSER ( ), .S_AXI_BVALID ( ), .S_AXI_BREADY ( 1'b0 ), .S_AXI_ARID ({C_AXI_ID_WIDTH{1'b0}} ), .S_AXI_ARADDR ( {C_AXI_ADDR_WIDTH{1'b0}} ), .S_AXI_ARLEN ( 8'b0 ), .S_AXI_ARSIZE ( 3'b0 ), .S_AXI_ARBURST ( 2'b0 ), .S_AXI_ARLOCK ( 2'b0 ), .S_AXI_ARCACHE ( 4'b0 ), .S_AXI_ARPROT ( 3'b0 ), .S_AXI_ARREGION ( 4'b0 ), .S_AXI_ARQOS ( 4'b0 ), .S_AXI_ARUSER ( 1'b0 ), .S_AXI_ARVALID ( 1'b0 ), .S_AXI_ARREADY ( ), .S_AXI_RID (mr_RID ), .S_AXI_RDATA (mr_RDATA ), .S_AXI_RRESP (mr_RRESP ), .S_AXI_RLAST (mr_RLAST ), .S_AXI_RUSER (mr_RUSER ), .S_AXI_RVALID (mr_RVALID ), .S_AXI_RREADY (mr_RREADY ), .M_AXI_AWID (), .M_AXI_AWADDR (), .M_AXI_AWLEN (), .M_AXI_AWSIZE (), .M_AXI_AWBURST (), .M_AXI_AWLOCK (), .M_AXI_AWCACHE (), .M_AXI_AWPROT (), .M_AXI_AWREGION (), .M_AXI_AWQOS (), .M_AXI_AWUSER (), .M_AXI_AWVALID (), .M_AXI_AWREADY (1'b0), .M_AXI_WID () , .M_AXI_WDATA (), .M_AXI_WSTRB (), .M_AXI_WLAST (), .M_AXI_WUSER (), .M_AXI_WVALID (), .M_AXI_WREADY (1'b0), .M_AXI_BID ( {C_AXI_ID_WIDTH{1'b0}} ) , .M_AXI_BRESP ( 2'b0 ) , .M_AXI_BUSER ( 1'b0 ) , .M_AXI_BVALID ( 1'b0 ) , .M_AXI_BREADY ( ) , .M_AXI_ARID (), .M_AXI_ARADDR (), .M_AXI_ARLEN (), .M_AXI_ARSIZE (), .M_AXI_ARBURST (), .M_AXI_ARLOCK (), .M_AXI_ARCACHE (), .M_AXI_ARPROT (), .M_AXI_ARREGION (), .M_AXI_ARQOS (), .M_AXI_ARUSER (), .M_AXI_ARVALID (), .M_AXI_ARREADY (1'b0), .M_AXI_RID (M_AXI_RID ), .M_AXI_RDATA (M_AXI_RDATA ), .M_AXI_RRESP (M_AXI_RRESP ), .M_AXI_RLAST (M_AXI_RLAST ), .M_AXI_RUSER (M_AXI_RUSER ), .M_AXI_RVALID (M_AXI_RVALID ), .M_AXI_RREADY (M_AXI_RREADY ) ); ///////////////////////////////////////////////////////////////////////////// // Handle Internal Reset ///////////////////////////////////////////////////////////////////////////// always @ (posedge ACLK) begin ARESET <= !ARESETN; end ///////////////////////////////////////////////////////////////////////////// // Handle Write Channels (AW/W/B) ///////////////////////////////////////////////////////////////////////////// generate if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE // Write Channel Signals for Commands Queue Interface. wire wr_cmd_valid; wire wr_cmd_fix; wire wr_cmd_modified; wire wr_cmd_complete_wrap; wire wr_cmd_packed_wrap; wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word; wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word; wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word; wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset; wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask; wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step; wire [8-1:0] wr_cmd_length; wire wr_cmd_ready; // Write Address Channel. mig_7series_v4_0_ddr_a_upsizer # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH), .C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_CHANNEL (0), .C_PACKING_LEVEL (C_PACKING_LEVEL), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS), .C_SINGLE_THREAD (C_SINGLE_THREAD), .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG), .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG) ) write_addr_inst ( // Global Signals .ARESET (ARESET), .ACLK (ACLK), // Command Interface .cmd_valid (wr_cmd_valid), .cmd_fix (wr_cmd_fix), .cmd_modified (wr_cmd_modified), .cmd_complete_wrap (wr_cmd_complete_wrap), .cmd_packed_wrap (wr_cmd_packed_wrap), .cmd_first_word (wr_cmd_first_word), .cmd_next_word (wr_cmd_next_word), .cmd_last_word (wr_cmd_last_word), .cmd_offset (wr_cmd_offset), .cmd_mask (wr_cmd_mask), .cmd_step (wr_cmd_step), .cmd_length (wr_cmd_length), .cmd_ready (wr_cmd_ready), // Slave Interface Write Address Ports .S_AXI_AID (sr_AWID), .S_AXI_AADDR (sr_AWADDR), .S_AXI_ALEN (sr_AWLEN), .S_AXI_ASIZE (sr_AWSIZE), .S_AXI_ABURST (sr_AWBURST), .S_AXI_ALOCK (sr_AWLOCK), .S_AXI_ACACHE (sr_AWCACHE), .S_AXI_APROT (sr_AWPROT), .S_AXI_AREGION (sr_AWREGION), .S_AXI_AQOS (sr_AWQOS), .S_AXI_AUSER (sr_AWUSER), .S_AXI_AVALID (sr_AWVALID), .S_AXI_AREADY (sr_AWREADY), // Master Interface Write Address Port .M_AXI_AID (M_AXI_AWID), .M_AXI_AADDR (M_AXI_AWADDR), .M_AXI_ALEN (M_AXI_AWLEN), .M_AXI_ASIZE (M_AXI_AWSIZE), .M_AXI_ABURST (M_AXI_AWBURST), .M_AXI_ALOCK (M_AXI_AWLOCK), .M_AXI_ACACHE (M_AXI_AWCACHE), .M_AXI_APROT (M_AXI_AWPROT), .M_AXI_AREGION (M_AXI_AWREGION), .M_AXI_AQOS (M_AXI_AWQOS), .M_AXI_AUSER (M_AXI_AWUSER), .M_AXI_AVALID (M_AXI_AWVALID), .M_AXI_AREADY (M_AXI_AWREADY) ); // Write Data channel. mig_7series_v4_0_ddr_w_upsizer # ( .C_FAMILY (C_FAMILY), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH), .C_M_AXI_REGISTER (1), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_PACKING_LEVEL (C_PACKING_LEVEL), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS), .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG), .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG), .C_RATIO (C_RATIO), .C_RATIO_LOG (C_RATIO_LOG) ) write_data_inst ( // Global Signals .ARESET (ARESET), .ACLK (ACLK), // Command Interface .cmd_valid (wr_cmd_valid), .cmd_fix (wr_cmd_fix), .cmd_modified (wr_cmd_modified), .cmd_complete_wrap (wr_cmd_complete_wrap), .cmd_packed_wrap (wr_cmd_packed_wrap), .cmd_first_word (wr_cmd_first_word), .cmd_next_word (wr_cmd_next_word), .cmd_last_word (wr_cmd_last_word), .cmd_offset (wr_cmd_offset), .cmd_mask (wr_cmd_mask), .cmd_step (wr_cmd_step), .cmd_length (wr_cmd_length), .cmd_ready (wr_cmd_ready), // Slave Interface Write Data Ports .S_AXI_WDATA (S_AXI_WDATA), .S_AXI_WSTRB (S_AXI_WSTRB), .S_AXI_WLAST (S_AXI_WLAST), .S_AXI_WUSER (S_AXI_WUSER), .S_AXI_WVALID (S_AXI_WVALID), .S_AXI_WREADY (S_AXI_WREADY), // Master Interface Write Data Ports .M_AXI_WDATA (M_AXI_WDATA), .M_AXI_WSTRB (M_AXI_WSTRB), .M_AXI_WLAST (M_AXI_WLAST), .M_AXI_WUSER (), .M_AXI_WVALID (M_AXI_WVALID), .M_AXI_WREADY (M_AXI_WREADY) ); // Write Response channel. assign S_AXI_BID = M_AXI_BID; assign S_AXI_BRESP = M_AXI_BRESP; assign S_AXI_BUSER = M_AXI_BUSER; assign S_AXI_BVALID = M_AXI_BVALID; assign M_AXI_BREADY = S_AXI_BREADY; end else begin : NO_WRITE assign sr_AWREADY = 1'b0; assign S_AXI_WREADY = 1'b0; assign S_AXI_BID = {C_AXI_ID_WIDTH{1'b0}}; assign S_AXI_BRESP = 2'b0; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_BVALID = 1'b0; assign M_AXI_AWID = {C_AXI_ID_WIDTH{1'b0}}; assign M_AXI_AWADDR = {C_AXI_ADDR_WIDTH{1'b0}}; assign M_AXI_AWLEN = 8'b0; assign M_AXI_AWSIZE = 3'b0; assign M_AXI_AWBURST = 2'b0; assign M_AXI_AWLOCK = 2'b0; assign M_AXI_AWCACHE = 4'b0; assign M_AXI_AWPROT = 3'b0; assign M_AXI_AWQOS = 4'b0; assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}}; assign M_AXI_AWVALID = 1'b0; assign M_AXI_WDATA = {C_M_AXI_DATA_WIDTH{1'b0}}; assign M_AXI_WSTRB = {C_M_AXI_DATA_WIDTH/8{1'b0}}; assign M_AXI_WLAST = 1'b0; assign M_AXI_WVALID = 1'b0; assign M_AXI_BREADY = 1'b0; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Handle Read Channels (AR/R) ///////////////////////////////////////////////////////////////////////////// generate if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ // Read Channel Signals for Commands Queue Interface. wire rd_cmd_valid; wire rd_cmd_fix; wire rd_cmd_modified; wire rd_cmd_complete_wrap; wire rd_cmd_packed_wrap; wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word; wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word; wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word; wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset; wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask; wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step; wire [8-1:0] rd_cmd_length; wire rd_cmd_ready; // Write Address Channel. mig_7series_v4_0_ddr_a_upsizer # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH), .C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_CHANNEL (1), .C_PACKING_LEVEL (C_PACKING_LEVEL), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS), .C_SINGLE_THREAD (C_SINGLE_THREAD), .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG), .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG) ) read_addr_inst ( // Global Signals .ARESET (ARESET), .ACLK (ACLK), // Command Interface .cmd_valid (rd_cmd_valid), .cmd_fix (rd_cmd_fix), .cmd_modified (rd_cmd_modified), .cmd_complete_wrap (rd_cmd_complete_wrap), .cmd_packed_wrap (rd_cmd_packed_wrap), .cmd_first_word (rd_cmd_first_word), .cmd_next_word (rd_cmd_next_word), .cmd_last_word (rd_cmd_last_word), .cmd_offset (rd_cmd_offset), .cmd_mask (rd_cmd_mask), .cmd_step (rd_cmd_step), .cmd_length (rd_cmd_length), .cmd_ready (rd_cmd_ready), // Slave Interface Write Address Ports .S_AXI_AID (sr_ARID), .S_AXI_AADDR (sr_ARADDR), .S_AXI_ALEN (sr_ARLEN), .S_AXI_ASIZE (sr_ARSIZE), .S_AXI_ABURST (sr_ARBURST), .S_AXI_ALOCK (sr_ARLOCK), .S_AXI_ACACHE (sr_ARCACHE), .S_AXI_APROT (sr_ARPROT), .S_AXI_AREGION (sr_ARREGION), .S_AXI_AQOS (sr_ARQOS), .S_AXI_AUSER (sr_ARUSER), .S_AXI_AVALID (sr_ARVALID), .S_AXI_AREADY (sr_ARREADY), // Master Interface Write Address Port .M_AXI_AID (M_AXI_ARID), .M_AXI_AADDR (M_AXI_ARADDR), .M_AXI_ALEN (M_AXI_ARLEN), .M_AXI_ASIZE (M_AXI_ARSIZE), .M_AXI_ABURST (M_AXI_ARBURST), .M_AXI_ALOCK (M_AXI_ARLOCK), .M_AXI_ACACHE (M_AXI_ARCACHE), .M_AXI_APROT (M_AXI_ARPROT), .M_AXI_AREGION (M_AXI_ARREGION), .M_AXI_AQOS (M_AXI_ARQOS), .M_AXI_AUSER (M_AXI_ARUSER), .M_AXI_AVALID (M_AXI_ARVALID), .M_AXI_AREADY (M_AXI_ARREADY) ); // Read Data channel. mig_7series_v4_0_ddr_r_upsizer # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH), .C_S_AXI_REGISTER (C_S_AXI_R_REGISTER), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_PACKING_LEVEL (C_PACKING_LEVEL), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS), .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG), .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG), .C_RATIO (C_RATIO), .C_RATIO_LOG (C_RATIO_LOG) ) read_data_inst ( // Global Signals .ARESET (ARESET), .ACLK (ACLK), // Command Interface .cmd_valid (rd_cmd_valid), .cmd_fix (rd_cmd_fix), .cmd_modified (rd_cmd_modified), .cmd_complete_wrap (rd_cmd_complete_wrap), .cmd_packed_wrap (rd_cmd_packed_wrap), .cmd_first_word (rd_cmd_first_word), .cmd_next_word (rd_cmd_next_word), .cmd_last_word (rd_cmd_last_word), .cmd_offset (rd_cmd_offset), .cmd_mask (rd_cmd_mask), .cmd_step (rd_cmd_step), .cmd_length (rd_cmd_length), .cmd_ready (rd_cmd_ready), // Slave Interface Read Data Ports .S_AXI_RID (S_AXI_RID), .S_AXI_RDATA (S_AXI_RDATA), .S_AXI_RRESP (S_AXI_RRESP), .S_AXI_RLAST (S_AXI_RLAST), .S_AXI_RUSER (), .S_AXI_RVALID (S_AXI_RVALID), .S_AXI_RREADY (S_AXI_RREADY), // Master Interface Read Data Ports .M_AXI_RID (mr_RID), .M_AXI_RDATA (mr_RDATA), .M_AXI_RRESP (mr_RRESP), .M_AXI_RLAST (mr_RLAST), .M_AXI_RUSER (mr_RUSER), .M_AXI_RVALID (mr_RVALID), .M_AXI_RREADY (mr_RREADY) ); end else begin : NO_READ assign sr_ARREADY = 1'b0; assign S_AXI_RID = {C_AXI_ID_WIDTH{1'b0}}; assign S_AXI_RDATA = {C_S_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_RRESP = 2'b0; assign S_AXI_RLAST = 1'b0; assign S_AXI_RVALID = 1'b0; assign M_AXI_ARID = {C_AXI_ID_WIDTH{1'b0}}; assign M_AXI_ARADDR = {C_AXI_ADDR_WIDTH{1'b0}}; assign M_AXI_ARLEN = 8'b0; assign M_AXI_ARSIZE = 3'b0; assign M_AXI_ARBURST = 2'b0; assign M_AXI_ARLOCK = 2'b0; assign M_AXI_ARCACHE = 4'b0; assign M_AXI_ARPROT = 3'b0; assign M_AXI_ARQOS = 4'b0; assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}}; assign M_AXI_ARVALID = 1'b0; assign mr_RREADY = 1'b0; end endgenerate endmodule `default_nettype wire ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Register Slice // Generic single-channel AXI pipeline register on forward and/or reverse signal path // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // ddr_axic_register_slice // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_axic_register_slice # ( parameter C_FAMILY = "virtex6", parameter C_DATA_WIDTH = 32, parameter C_REG_CONFIG = 32'h00000000 // C_REG_CONFIG: // 0 => BYPASS = The channel is just wired through the module. // 1 => FWD_REV = Both FWD and REV (fully-registered) // 2 => FWD = The master VALID and payload signals are registrated. // 3 => REV = The slave ready signal is registrated // 4 => RESERVED (all outputs driven to 0). // 5 => RESERVED (all outputs driven to 0). // 6 => INPUTS = Slave and Master side inputs are registrated. // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining ) ( // System Signals input wire ACLK, input wire ARESET, // Slave side input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, input wire S_VALID, output wire S_READY, // Master side output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, output wire M_VALID, input wire M_READY ); (* use_clock_enable = "yes" *) generate //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 0 // Bypass mode // //////////////////////////////////////////////////////////////////// if (C_REG_CONFIG == 32'h00000000) begin assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; assign M_VALID = S_VALID; assign S_READY = M_READY; end //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 1 (or 8) // Both FWD and REV mode // //////////////////////////////////////////////////////////////////// else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin (* max_fanout = 50 *) reg [1:0] state /* synthesis syn_maxfan = 30 */; localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01; reg [C_DATA_WIDTH-1:0] storage_data1; reg [C_DATA_WIDTH-1:0] storage_data2; reg load_s1; wire load_s2; wire load_s1_from_s2; reg s_ready_i; //local signal of output wire m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg [1:0] areset_d; // Reset delay register always @(posedge ACLK) begin areset_d <= {areset_d[0], ARESET}; end // Load storage1 with either slave side data or from storage2 always @(posedge ACLK) begin if (load_s1) if (load_s1_from_s2) storage_data1 <= storage_data2; else storage_data1 <= S_PAYLOAD_DATA; end // Load storage2 with slave side data always @(posedge ACLK) begin if (load_s2) storage_data2 <= S_PAYLOAD_DATA; end assign M_PAYLOAD_DATA = storage_data1; // Always load s2 on a valid transaction even if it's unnecessary assign load_s2 = S_VALID & s_ready_i; // Loading s1 always @ * begin if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction // Load when ONE if we both have read and write at the same time ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || // Load when TWO and we have a transaction on Master side ((state == TWO) && (M_READY == 1))) load_s1 = 1'b1; else load_s1 = 1'b0; end // always @ * assign load_s1_from_s2 = (state == TWO); // State Machine for handling output signals always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; state <= ZERO; end else if (areset_d == 2'b10) begin s_ready_i <= 1'b1; end else if (areset_d == 2'b00) begin case (state) // No transaction stored locally ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE // One transaction stored locally ONE: begin if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO // if (~M_READY & S_VALID) begin else if (~M_READY & S_VALID) begin state <= TWO; // Got another one so move to TWO s_ready_i <= 1'b0; end end // TWO transaction stored locally TWO: if (M_READY) begin state <= ONE; // Read out one so move to ONE s_ready_i <= 1'b1; end endcase // case (state) end end // always @ (posedge ACLK) assign m_valid_i = state[0]; end // if (C_REG_CONFIG == 1) //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 2 // Only FWD mode // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000002) begin reg [C_DATA_WIDTH-1:0] storage_data; wire s_ready_i; //local signal of output reg m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register always @(posedge ACLK) begin areset_d <= {areset_d[0], ARESET}; end // Save payload data whenever we have a transaction on the slave side always @(posedge ACLK) begin if (S_VALID & s_ready_i) storage_data <= S_PAYLOAD_DATA; end assign M_PAYLOAD_DATA = storage_data; // M_Valid set to high when we have a completed transfer on slave side // Is removed on a M_READY except if we have a new transfer on the slave side always @(posedge ACLK) begin if (areset_d) m_valid_i <= 1'b0; else if (S_VALID) // Always set m_valid_i when slave side is valid m_valid_i <= 1'b1; else if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready m_valid_i <= 1'b0; end // always @ (posedge ACLK) // Slave Ready is either when Master side drives M_Ready or we have space in our storage data assign s_ready_i = (M_READY | ~m_valid_i) & ~|areset_d; end // if (C_REG_CONFIG == 2) //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 3 // Only REV mode // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000003) begin reg [C_DATA_WIDTH-1:0] storage_data; reg s_ready_i; //local signal of output reg has_valid_storage_i; reg has_valid_storage; (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register always @(posedge ACLK) begin areset_d <= ARESET; end // Save payload data whenever we have a transaction on the slave side always @(posedge ACLK) begin if (S_VALID & s_ready_i) storage_data <= S_PAYLOAD_DATA; end assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA; // Need to determine when we need to save a payload // Need a combinatorial signals since it will also effect S_READY always @ * begin // Set the value if we have a slave transaction but master side is not ready if (S_VALID & s_ready_i & ~M_READY) has_valid_storage_i = 1'b1; // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side // transaction else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0))) has_valid_storage_i = 1'b0; else has_valid_storage_i = has_valid_storage; end // always @ * always @(posedge ACLK) begin if (ARESET) has_valid_storage <= 1'b0; else has_valid_storage <= has_valid_storage_i; end // S_READY is either clocked M_READY or that we have room in local storage always @(posedge ACLK) begin if (ARESET) s_ready_i <= 1'b0; else s_ready_i <= M_READY | ~has_valid_storage_i; end // assign local signal to its output signal assign S_READY = s_ready_i; // M_READY is either combinatorial S_READY or that we have valid data in local storage assign M_VALID = (S_VALID | has_valid_storage) & ~areset_d; end // if (C_REG_CONFIG == 3) //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED // //////////////////////////////////////////////////////////////////// else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005)) begin // synthesis translate_off initial begin $display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED."); end // synthesis translate_on assign M_PAYLOAD_DATA = 0; assign M_VALID = 1'b0; assign S_READY = 1'b0; end //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 6 // INPUTS mode // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000006) begin reg [1:0] state; reg [1:0] next_state; localparam [1:0] ZERO = 2'b00, ONE = 2'b01, TWO = 2'b11; reg [C_DATA_WIDTH-1:0] storage_data1; reg [C_DATA_WIDTH-1:0] storage_data2; reg s_valid_d; reg s_ready_d; reg m_ready_d; reg m_valid_d; reg load_s2; reg sel_s2; wire new_access; wire access_done; wire s_ready_i; //local signal of output reg s_ready_ii; reg m_valid_i; //local signal of output (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register always @(posedge ACLK) begin areset_d <= ARESET; end // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; assign s_ready_i = s_ready_ii & ~areset_d; // Registrate input control signals always @(posedge ACLK) begin if (ARESET) begin s_valid_d <= 1'b0; s_ready_d <= 1'b0; m_ready_d <= 1'b0; end else begin s_valid_d <= S_VALID; s_ready_d <= s_ready_i; m_ready_d <= M_READY; end end // always @ (posedge ACLK) // Load storage1 with slave side payload data when slave side ready is high always @(posedge ACLK) begin if (s_ready_i) storage_data1 <= S_PAYLOAD_DATA; end // Load storage2 with storage data always @(posedge ACLK) begin if (load_s2) storage_data2 <= storage_data1; end always @(posedge ACLK) begin if (ARESET) m_valid_d <= 1'b0; else m_valid_d <= m_valid_i; end // Local help signals assign new_access = s_ready_d & s_valid_d; assign access_done = m_ready_d & m_valid_d; // State Machine for handling output signals always @* begin next_state = state; // Stay in the same state unless we need to move to another state load_s2 = 0; sel_s2 = 0; m_valid_i = 0; s_ready_ii = 0; case (state) // No transaction stored locally ZERO: begin load_s2 = 0; sel_s2 = 0; m_valid_i = 0; s_ready_ii = 1; if (new_access) begin next_state = ONE; // Got one so move to ONE load_s2 = 1; m_valid_i = 0; end else begin next_state = next_state; load_s2 = load_s2; m_valid_i = m_valid_i; end end // case: ZERO // One transaction stored locally ONE: begin load_s2 = 0; sel_s2 = 1; m_valid_i = 1; s_ready_ii = 1; if (~new_access & access_done) begin next_state = ZERO; // Read out one so move to ZERO m_valid_i = 0; end else if (new_access & ~access_done) begin next_state = TWO; // Got another one so move to TWO s_ready_ii = 0; end else if (new_access & access_done) begin load_s2 = 1; sel_s2 = 0; end else begin load_s2 = load_s2; sel_s2 = sel_s2; end end // case: ONE // TWO transaction stored locally TWO: begin load_s2 = 0; sel_s2 = 1; m_valid_i = 1; s_ready_ii = 0; if (access_done) begin next_state = ONE; // Read out one so move to ONE s_ready_ii = 1; load_s2 = 1; sel_s2 = 0; end else begin next_state = next_state; s_ready_ii = s_ready_ii; load_s2 = load_s2; sel_s2 = sel_s2; end end // case: TWO endcase // case (state) end // always @ * // State Machine for handling output signals always @(posedge ACLK) begin if (ARESET) state <= ZERO; else state <= next_state; // Stay in the same state unless we need to move to another state end // Master Payload mux assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1; end // if (C_REG_CONFIG == 6) //////////////////////////////////////////////////////////////////// // // C_REG_CONFIG = 7 // Light-weight mode. // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining // Operates same as 1-deep FIFO // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000007) begin reg [C_DATA_WIDTH-1:0] storage_data1; reg s_ready_i; //local signal of output reg m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg [1:0] areset_d; // Reset delay register always @(posedge ACLK) begin areset_d <= {areset_d[0], ARESET}; end // Load storage1 with slave side data always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; m_valid_i <= 1'b0; end else if (areset_d == 2'b10) begin s_ready_i <= 1'b1; end else if (areset_d == 2'b00) begin if (m_valid_i & M_READY) begin s_ready_i <= 1'b1; m_valid_i <= 1'b0; end else if (S_VALID & s_ready_i) begin s_ready_i <= 1'b0; m_valid_i <= 1'b1; end end if (~m_valid_i) begin storage_data1 <= S_PAYLOAD_DATA; end end assign M_PAYLOAD_DATA = storage_data1; end // if (C_REG_CONFIG == 7) else begin : default_case // Passthrough assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; assign M_VALID = S_VALID; assign S_READY = M_READY; end endgenerate endmodule // reg_slice ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_and.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized AND with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_carry_and # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire S, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign COUT = CIN & S; end else begin : USE_FPGA MUXCY and_inst ( .O (COUT), .CI (CIN), .DI (1'b0), .S (S) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized AND with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_carry_latch_and # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire I, output wire O ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign O = CIN & ~I; end else begin : USE_FPGA wire I_n; assign I_n = ~I; AND2B1L and2b1l_inst ( .O(O), .DI(CIN), .SRI(I_n) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized OR with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_carry_latch_or # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire I, output wire O ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign O = CIN | I; end else begin : USE_FPGA OR2L or2l_inst1 ( .O(O), .DI(CIN), .SRI(I) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized OR with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_carry_or # ( parameter C_FAMILY = "virtex6" // FPGA Family. Current version: virtex6 or spartan6. ) ( input wire CIN, input wire S, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL assign COUT = CIN | S; end else begin : USE_FPGA wire S_n; assign S_n = ~S; MUXCY and_inst ( .O (COUT), .CI (CIN), .DI (1'b1), .S (S_n) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized 16/32 word deep FIFO. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_command_fifo # ( parameter C_FAMILY = "virtex6", parameter integer C_ENABLE_S_VALID_CARRY = 0, parameter integer C_ENABLE_REGISTERED_OUTPUT = 0, parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG // Range = [4:5]. parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512] ) ( // Global inputs input wire ACLK, // Clock input wire ARESET, // Reset // Information output wire EMPTY, // FIFO empty (all stages) // Slave Port input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals) input wire S_VALID, // FIFO push output wire S_READY, // FIFO not full // Master Port output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload output wire M_VALID, // FIFO not empty input wire M_READY // FIFO pop ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for data vector. genvar addr_cnt; genvar bit_cnt; integer index; ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIFO_DEPTH_LOG-1:0] addr; wire buffer_Full; wire buffer_Empty; wire next_Data_Exists; reg data_Exists_I; wire valid_Write; wire new_write; wire [C_FIFO_DEPTH_LOG-1:0] hsum_A; wire [C_FIFO_DEPTH_LOG-1:0] sum_A; wire [C_FIFO_DEPTH_LOG-1:0] addr_cy; wire buffer_full_early; wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload wire M_VALID_I; // FIFO not empty wire M_READY_I; // FIFO pop ///////////////////////////////////////////////////////////////////////////// // Create Flags ///////////////////////////////////////////////////////////////////////////// assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) | ( buffer_Full & ~M_READY_I ); assign S_READY = ~buffer_Full; assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}}); assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) | (buffer_Empty & S_VALID) | (data_Exists_I & ~(M_READY_I & data_Exists_I)); always @ (posedge ACLK) begin if (ARESET) begin data_Exists_I <= 1'b0; end else begin data_Exists_I <= next_Data_Exists; end end assign M_VALID_I = data_Exists_I; // Select RTL or FPGA optimized instatiations for critical parts. generate if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE reg buffer_Full_q; assign valid_Write = S_VALID & ~buffer_Full; assign new_write = (S_VALID | ~buffer_Empty); assign addr_cy[0] = valid_Write; always @ (posedge ACLK) begin if (ARESET) begin buffer_Full_q <= 1'b0; end else if ( data_Exists_I ) begin buffer_Full_q <= buffer_full_early; end end assign buffer_Full = buffer_Full_q; end else begin : USE_FPGA_VALID_WRITE wire s_valid_dummy1; wire s_valid_dummy2; wire sel_s_valid; wire sel_new_write; wire valid_Write_dummy1; wire valid_Write_dummy2; assign sel_s_valid = ~buffer_Full; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) s_valid_dummy_inst1 ( .CIN(S_VALID), .S(1'b1), .COUT(s_valid_dummy1) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) s_valid_dummy_inst2 ( .CIN(s_valid_dummy1), .S(1'b1), .COUT(s_valid_dummy2) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_inst ( .CIN(s_valid_dummy2), .S(sel_s_valid), .COUT(valid_Write) ); assign sel_new_write = ~buffer_Empty; mig_7series_v4_0_ddr_carry_latch_or # ( .C_FAMILY(C_FAMILY) ) new_write_inst ( .CIN(valid_Write), .I(sel_new_write), .O(new_write) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst1 ( .CIN(valid_Write), .S(1'b1), .COUT(valid_Write_dummy1) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst2 ( .CIN(valid_Write_dummy1), .S(1'b1), .COUT(valid_Write_dummy2) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst3 ( .CIN(valid_Write_dummy2), .S(1'b1), .COUT(addr_cy[0]) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_I1 ( .Q(buffer_Full), // Data output .C(ACLK), // Clock input .CE(data_Exists_I), // Clock enable input .R(ARESET), // Synchronous reset input .D(buffer_full_early) // Data input ); end endgenerate ///////////////////////////////////////////////////////////////////////////// // Create address pointer ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR reg [C_FIFO_DEPTH_LOG-1:0] addr_q; always @ (posedge ACLK) begin if (ARESET) begin addr_q <= {C_FIFO_DEPTH_LOG{1'b0}}; end else if ( data_Exists_I ) begin if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin addr_q <= addr_q + 1'b1; end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin addr_q <= addr_q - 1'b1; end else begin addr_q <= addr_q; end end else begin addr_q <= addr_q; end end assign addr = addr_q; end else begin : USE_FPGA_ADDR for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write; // Don't need the last muxcy, addr_cy(last) is not used anywhere if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY MUXCY MUXCY_inst ( .DI(addr[addr_cnt]), .CI(addr_cy[addr_cnt]), .S(hsum_A[addr_cnt]), .O(addr_cy[addr_cnt+1]) ); end else begin : NO_MUXCY end XORCY XORCY_inst ( .LI(hsum_A[addr_cnt]), .CI(addr_cy[addr_cnt]), .O(sum_A[addr_cnt]) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(addr[addr_cnt]), // Data output .C(ACLK), // Clock input .CE(data_Exists_I), // Clock enable input .R(ARESET), // Synchronous reset input .D(sum_A[addr_cnt]) // Data input ); end // end for bit_cnt end // C_FAMILY endgenerate ///////////////////////////////////////////////////////////////////////////// // Data storage ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0]; always @ (posedge ACLK) begin if ( valid_Write ) begin for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= S_MESG; end end assign M_MESG_I = data_srl[addr]; end else begin : USE_FPGA_FIFO for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32 SRLC32E # ( .INIT(32'h00000000) // Initial Value of Shift Register ) SRLC32E_inst ( .Q(M_MESG_I[bit_cnt]), // SRL data output .Q31(), // SRL cascade output pin .A(addr), // 5-bit shift depth select input .CE(valid_Write), // Clock enable input .CLK(ACLK), // Clock input .D(S_MESG[bit_cnt]) // SRL data input ); end else begin : USE_16 SRLC16E # ( .INIT(32'h00000000) // Initial Value of Shift Register ) SRLC16E_inst ( .Q(M_MESG_I[bit_cnt]), // SRL data output .Q15(), // SRL cascade output pin .A0(addr[0]), // 4-bit shift depth select input 0 .A1(addr[1]), // 4-bit shift depth select input 1 .A2(addr[2]), // 4-bit shift depth select input 2 .A3(addr[3]), // 4-bit shift depth select input 3 .CE(valid_Write), // Clock enable input .CLK(ACLK), // Clock input .D(S_MESG[bit_cnt]) // SRL data input ); end // C_FIFO_DEPTH_LOG end // end for bit_cnt end // C_FAMILY endgenerate ///////////////////////////////////////////////////////////////////////////// // Pipeline stage ///////////////////////////////////////////////////////////////////////////// generate if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload wire M_VALID_FF; // FIFO not empty // Select RTL or FPGA optimized instatiations for critical parts. if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload reg M_VALID_Q; // FIFO not empty always @ (posedge ACLK) begin if (ARESET) begin M_MESG_Q <= {C_FIFO_WIDTH{1'b0}}; M_VALID_Q <= 1'b0; end else begin if ( M_READY_I ) begin M_MESG_Q <= M_MESG_I; M_VALID_Q <= M_VALID_I; end end end assign M_MESG_FF = M_MESG_Q; assign M_VALID_FF = M_VALID_Q; end else begin : USE_FPGA_OUTPUT_PIPELINE reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload reg M_VALID_CMB; // FIFO not empty always @ * begin if ( M_READY_I ) begin M_MESG_CMB <= M_MESG_I; M_VALID_CMB <= M_VALID_I; end else begin M_MESG_CMB <= M_MESG_FF; M_VALID_CMB <= M_VALID_FF; end end for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(M_MESG_FF[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_MESG_CMB[bit_cnt]) // Data input ); end // end for bit_cnt FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(M_VALID_FF), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_VALID_CMB) // Data input ); end assign EMPTY = ~M_VALID_I & ~M_VALID_FF; assign M_MESG = M_MESG_FF; assign M_VALID = M_VALID_FF; assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF; end else begin : NO_FF_OUT assign EMPTY = ~M_VALID_I; assign M_MESG = M_MESG_I; assign M_VALID = M_VALID_I; assign M_READY_I = M_READY; end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_comparator # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 3; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; end // Instantiate one carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ); // Instantiate each LUT level. mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_comparator_sel # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = V; end // Instantiate one carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel_static.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: // Optimized COMPARATOR (against constant) with carry logic. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_comparator_sel_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = C_VALUE; end // Instantiate one carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_r_upsizer.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Read Data Response Up-Sizer // Extract SI-side Data from packed and unpacked MI-side data. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // ddr_r_upsizer // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_r_upsizer # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of converter. // Range: >= 1. parameter C_S_AXI_DATA_WIDTH = 32'h00000020, // Width of S_AXI_WDATA and S_AXI_RDATA. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter C_M_AXI_DATA_WIDTH = 32'h00000040, // Width of M_AXI_WDATA and M_AXI_RDATA. // Assume greater than or equal to C_S_AXI_DATA_WIDTH. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter integer C_S_AXI_REGISTER = 0, // Clock output data. // Range: 0, 1 parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals. // Range: >= 1. parameter integer C_PACKING_LEVEL = 1, // 0 = Never pack (expander only); packing logic is omitted. // 1 = Pack only when CACHE[1] (Modifiable) is high. // 2 = Always pack, regardless of sub-size transaction or Modifiable bit. // (Required when used as helper-core by mem-con.) parameter integer C_SUPPORT_BURSTS = 1, // Disabled when all connected masters and slaves are AxiLite, // allowing logic to be simplified. parameter integer C_S_AXI_BYTES_LOG = 3, // Log2 of number of 32bit word on SI-side. parameter integer C_M_AXI_BYTES_LOG = 3, // Log2 of number of 32bit word on MI-side. parameter integer C_RATIO = 2, // Up-Sizing ratio for data. parameter integer C_RATIO_LOG = 1 // Log2 of Up-Sizing ratio for data. ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_valid, input wire cmd_fix, input wire cmd_modified, input wire cmd_complete_wrap, input wire cmd_packed_wrap, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask, input wire [C_S_AXI_BYTES_LOG:0] cmd_step, input wire [8-1:0] cmd_length, output wire cmd_ready, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam integer C_NEVER_PACK = 0; localparam integer C_DEFAULT_PACK = 1; localparam integer C_ALWAYS_PACK = 2; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Sub-word handling. wire sel_first_word; reg first_word; reg [C_M_AXI_BYTES_LOG-1:0] current_word_1; reg [C_M_AXI_BYTES_LOG-1:0] current_word_cmb; wire [C_M_AXI_BYTES_LOG-1:0] current_word; wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted; wire last_beat; wire last_word; wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i; // Sub-word handling for the next cycle. wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i; wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word; reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1; wire [C_M_AXI_BYTES_LOG-1:0] next_word_i; wire [C_M_AXI_BYTES_LOG-1:0] next_word; // Burst length handling. wire first_mi_word; wire [8-1:0] length_counter_1; reg [8-1:0] length_counter; wire [8-1:0] next_length_counter; // Handle wrap buffering. wire store_in_wrap_buffer; reg use_wrap_buffer; reg wrap_buffer_available; reg [C_AXI_ID_WIDTH-1:0] rid_wrap_buffer; reg [2-1:0] rresp_wrap_buffer; reg [C_AXI_RUSER_WIDTH-1:0] ruser_wrap_buffer; // Throttling help signals. wire next_word_wrap; wire word_complete_next_wrap; wire word_complete_next_wrap_ready; wire word_complete_next_wrap_pop; wire word_complete_last_word; wire word_complete_rest; wire word_complete_rest_ready; wire word_complete_rest_pop; wire word_completed; wire cmd_ready_i; wire pop_si_data; wire pop_mi_data; wire si_stalling; // Internal signals for MI-side. reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA_I; wire M_AXI_RLAST_I; wire M_AXI_RVALID_I; wire M_AXI_RREADY_I; // Internal signals for SI-side. wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I; wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I; wire [2-1:0] S_AXI_RRESP_I; wire S_AXI_RLAST_I; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I; wire S_AXI_RVALID_I; wire S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Determine if a MI side word has been completely used. For FIX transactions // the MI-side word is used to extract a single data word. This is also true // for for an upsizer in Expander mode (Never Pack). Unmodified burst also // only use the MI word to extract a single SI-side word (although with // different offsets). // Otherwise is the MI-side word considered to be used when last SI-side beat // has been extracted or when the last (most significant) SI-side word has // been extracted from ti MI word. // // Data on the SI-side is available when data is being taken from MI-side or // from wrap buffer. // // The command is popped from the command queue once the last beat on the // SI-side has been ackowledged. // ///////////////////////////////////////////////////////////////////////////// generate if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step}; end else begin : NO_LARGE_UPSIZING assign cmd_step_i = cmd_step; end endgenerate generate if ( C_FAMILY == "rtl" || ( C_SUPPORT_BURSTS == 0 ) || ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED // Detect when MI-side word is completely used. assign word_completed = cmd_valid & ( ( cmd_fix ) | ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | ( ~cmd_fix & last_word & ~use_wrap_buffer ) | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) | ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ) ); // RTL equivalent of optimized partial extressions (address wrap for next word). assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ); assign word_complete_next_wrap_ready = word_complete_next_wrap & M_AXI_RVALID_I & ~si_stalling; assign word_complete_next_wrap_pop = word_complete_next_wrap_ready & M_AXI_RVALID_I; // RTL equivalent of optimized partial extressions (last word and the remaining). assign word_complete_last_word = last_word & (~cmd_fix & ~use_wrap_buffer); assign word_complete_rest = word_complete_last_word | cmd_fix | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ); assign word_complete_rest_ready = word_complete_rest & M_AXI_RVALID_I & ~si_stalling; assign word_complete_rest_pop = word_complete_rest_ready & M_AXI_RVALID_I; end else begin : USE_FPGA_WORD_COMPLETED wire sel_word_complete_next_wrap; wire sel_word_completed; wire sel_m_axi_rready; wire sel_word_complete_last_word; wire sel_word_complete_rest; // Optimize next word address wrap branch of expression. // mig_7series_v4_0_ddr_comparator_sel_static # ( .C_FAMILY(C_FAMILY), .C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}), .C_DATA_WIDTH(C_M_AXI_BYTES_LOG) ) next_word_wrap_inst ( .CIN(1'b1), .S(sel_first_word), .A(pre_next_word_1), .B(cmd_next_word), .COUT(next_word_wrap) ); assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_inst ( .CIN(next_word_wrap), .S(sel_word_complete_next_wrap), .COUT(word_complete_next_wrap) ); assign sel_m_axi_rready = cmd_valid & S_AXI_RREADY_I; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_ready_inst ( .CIN(word_complete_next_wrap), .S(sel_m_axi_rready), .COUT(word_complete_next_wrap_ready) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_pop_inst ( .CIN(word_complete_next_wrap_ready), .S(M_AXI_RVALID_I), .COUT(word_complete_next_wrap_pop) ); // Optimize last word and "rest" branch of expression. // assign sel_word_complete_last_word = ~cmd_fix & ~use_wrap_buffer; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_last_word_inst ( .CIN(last_word), .S(sel_word_complete_last_word), .COUT(word_complete_last_word) ); assign sel_word_complete_rest = cmd_fix | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ); mig_7series_v4_0_ddr_carry_or # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_inst ( .CIN(word_complete_last_word), .S(sel_word_complete_rest), .COUT(word_complete_rest) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_ready_inst ( .CIN(word_complete_rest), .S(sel_m_axi_rready), .COUT(word_complete_rest_ready) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_pop_inst ( .CIN(word_complete_rest_ready), .S(M_AXI_RVALID_I), .COUT(word_complete_rest_pop) ); // Combine the two branches to generate the full signal. assign word_completed = word_complete_next_wrap | word_complete_rest; end endgenerate // Only propagate Valid when there is command information available. assign M_AXI_RVALID_I = M_AXI_RVALID & cmd_valid; generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_CTRL // Pop word from MI-side. assign M_AXI_RREADY_I = word_completed & S_AXI_RREADY_I; // Get MI-side data. assign pop_mi_data = M_AXI_RVALID_I & M_AXI_RREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & S_AXI_RLAST_I & pop_si_data; end else begin : USE_FPGA_CTRL wire sel_cmd_ready; assign M_AXI_RREADY_I = word_complete_next_wrap_ready | word_complete_rest_ready; assign pop_mi_data = word_complete_next_wrap_pop | word_complete_rest_pop; assign sel_cmd_ready = cmd_valid & pop_si_data; mig_7series_v4_0_ddr_carry_latch_and # ( .C_FAMILY(C_FAMILY) ) cmd_ready_inst ( .CIN(S_AXI_RLAST_I), .I(sel_cmd_ready), .O(cmd_ready_i) ); end endgenerate // Indicate when there is data available @ SI-side. assign S_AXI_RVALID_I = ( M_AXI_RVALID_I | use_wrap_buffer ); // Get SI-side data. assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I; // Assign external signals. assign M_AXI_RREADY = M_AXI_RREADY_I; assign cmd_ready = cmd_ready_i; // Detect when SI-side is stalling. assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I; ///////////////////////////////////////////////////////////////////////////// // Keep track of data extraction: // // Current address is taken form the command buffer for the first data beat // to handle unaligned Read transactions. After this is the extraction // address usually calculated from this point. // FIX transactions uses the same word address for all data beats. // // Next word address is generated as current word plus the current step // size, with masking to facilitate sub-sized wraping. The Mask is all ones // for normal wraping, and less when sub-sized wraping is used. // // The calculated word addresses (current and next) is offseted by the // current Offset. For sub-sized transaction the Offset points to the least // significant address of the included data beats. (The least significant // word is not necessarily the first data to be extracted, consider WRAP). // Offset is only used for sub-sized WRAP transcation that are Complete. // // First word is active during the first SI-side data beat. // // First MI is set while the entire first MI-side word is processed. // // The transaction length is taken from the command buffer combinatorialy // during the First MI cycle. For each used MI word it is decreased until // Last beat is reached. // // Last word is determined depending on the current command, i.e. modified // burst has to scale since multiple words could be packed into one MI-side // word. // Last word is 1:1 for: // FIX, when burst support is disabled or unmodified for Normal Pack. // Last word is scaled for all other transactions. // ///////////////////////////////////////////////////////////////////////////// // Select if the offset comes from command queue directly or // from a counter while when extracting multiple SI words per MI word assign sel_first_word = first_word | cmd_fix; assign current_word = sel_first_word ? cmd_first_word : current_word_1; generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD // Calculate next word. assign pre_next_word_i = ( next_word_i + cmd_step_i ); // Calculate next word. assign next_word_i = sel_first_word ? cmd_next_word : pre_next_word_1; end else begin : USE_FPGA_NEXT_WORD wire [C_M_AXI_BYTES_LOG-1:0] next_sel; wire [C_M_AXI_BYTES_LOG:0] next_carry_local; // Assign input to local vectors. assign next_carry_local[0] = 1'b0; // Instantiate one carry and per level. for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL LUT6_2 # ( .INIT(64'h5A5A_5A66_F0F0_F0CC) ) LUT6_2_inst ( .O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit) .O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit) .I0(cmd_step_i[bit_cnt]), // LUT input (1-bit) .I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit) .I2(cmd_next_word[bit_cnt]), // LUT input (1-bit) .I3(first_word), // LUT input (1-bit) .I4(cmd_fix), // LUT input (1-bit) .I5(1'b1) // LUT input (1-bit) ); MUXCY next_carry_inst ( .O (next_carry_local[bit_cnt+1]), .CI (next_carry_local[bit_cnt]), .DI (cmd_step_i[bit_cnt]), .S (next_sel[bit_cnt]) ); XORCY next_xorcy_inst ( .O(pre_next_word_i[bit_cnt]), .CI(next_carry_local[bit_cnt]), .LI(next_sel[bit_cnt]) ); end // end for bit_cnt end endgenerate // Calculate next word. assign next_word = next_word_i & cmd_mask; assign pre_next_word = pre_next_word_i & cmd_mask; // Calculate the word address with offset. assign current_word_adjusted = current_word | cmd_offset; // Prepare next word address. always @ (posedge ACLK) begin if (ARESET) begin first_word <= 1'b1; current_word_1 <= 'b0; pre_next_word_1 <= {C_M_AXI_BYTES_LOG{1'b0}}; end else begin if ( pop_si_data ) begin if ( last_word ) begin // Prepare for next access. first_word <= 1'b1; end else begin first_word <= 1'b0; end current_word_1 <= next_word; pre_next_word_1 <= pre_next_word; end end end // Select command length or counted length. always @ * begin if ( first_mi_word ) length_counter = cmd_length; else length_counter = length_counter_1; end // Calculate next length counter value. assign next_length_counter = length_counter - 1'b1; generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH reg [8-1:0] length_counter_q; reg first_mi_word_q; always @ (posedge ACLK) begin if (ARESET) begin first_mi_word_q <= 1'b1; length_counter_q <= 8'b0; end else begin if ( pop_mi_data ) begin if ( M_AXI_RLAST ) begin first_mi_word_q <= 1'b1; end else begin first_mi_word_q <= 1'b0; end length_counter_q <= next_length_counter; end end end assign first_mi_word = first_mi_word_q; assign length_counter_1 = length_counter_q; end else begin : USE_FPGA_LENGTH wire [8-1:0] length_counter_i; wire [8-1:0] length_sel; wire [8-1:0] length_di; wire [8:0] length_local_carry; // Assign input to local vectors. assign length_local_carry[0] = 1'b0; for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE LUT6_2 # ( .INIT(64'h333C_555A_FFF0_FFF0) ) LUT6_2_inst ( .O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit) .O5(length_di[bit_cnt]), // 5-LUT output (1-bit) .I0(length_counter_1[bit_cnt]), // LUT input (1-bit) .I1(cmd_length[bit_cnt]), // LUT input (1-bit) .I2(word_complete_next_wrap_pop), // LUT input (1-bit) .I3(word_complete_rest_pop), // LUT input (1-bit) .I4(first_mi_word), // LUT input (1-bit) .I5(1'b1) // LUT input (1-bit) ); MUXCY and_inst ( .O (length_local_carry[bit_cnt+1]), .CI (length_local_carry[bit_cnt]), .DI (length_di[bit_cnt]), .S (length_sel[bit_cnt]) ); XORCY xorcy_inst ( .O(length_counter_i[bit_cnt]), .CI(length_local_carry[bit_cnt]), .LI(length_sel[bit_cnt]) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(length_counter_1[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(length_counter_i[bit_cnt]) // Data input ); end // end for bit_cnt wire first_mi_word_i; LUT6 # ( .INIT(64'hAAAC_AAAC_AAAC_AAAC) ) LUT6_cnt_inst ( .O(first_mi_word_i), // 6-LUT output (1-bit) .I0(M_AXI_RLAST), // LUT input (1-bit) .I1(first_mi_word), // LUT input (1-bit) .I2(word_complete_next_wrap_pop), // LUT input (1-bit) .I3(word_complete_rest_pop), // LUT input (1-bit) .I4(1'b1), // LUT input (1-bit) .I5(1'b1) // LUT input (1-bit) ); FDSE #( .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(first_mi_word), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .S(ARESET), // Synchronous reset input .D(first_mi_word_i) // Data input ); end endgenerate generate if ( C_FAMILY == "rtl" || C_SUPPORT_BURSTS == 0 ) begin : USE_RTL_LAST_WORD // Detect last beat in a burst. assign last_beat = ( length_counter == 8'b0 ); // Determine if this last word that shall be extracted from this MI-side word. assign last_word = ( last_beat & ( current_word == cmd_last_word ) & ~wrap_buffer_available & ( current_word == cmd_last_word ) ) | ( use_wrap_buffer & ( current_word == cmd_last_word ) ) | ( last_beat & ( current_word == cmd_last_word ) & ( C_PACKING_LEVEL == C_NEVER_PACK ) ) | ( C_SUPPORT_BURSTS == 0 ); end else begin : USE_FPGA_LAST_WORD wire sel_last_word; wire last_beat_ii; mig_7series_v4_0_ddr_comparator_sel_static # ( .C_FAMILY(C_FAMILY), .C_VALUE(8'b0), .C_DATA_WIDTH(8) ) last_beat_inst ( .CIN(1'b1), .S(first_mi_word), .A(length_counter_1), .B(cmd_length), .COUT(last_beat) ); if ( C_PACKING_LEVEL != C_NEVER_PACK ) begin : USE_FPGA_PACK // // wire sel_last_beat; wire last_beat_i; assign sel_last_beat = ~wrap_buffer_available; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) last_beat_inst_1 ( .CIN(last_beat), .S(sel_last_beat), .COUT(last_beat_i) ); mig_7series_v4_0_ddr_carry_or # ( .C_FAMILY(C_FAMILY) ) last_beat_wrap_inst ( .CIN(last_beat_i), .S(use_wrap_buffer), .COUT(last_beat_ii) ); end else begin : NO_PACK assign last_beat_ii = last_beat; end mig_7series_v4_0_ddr_comparator_sel # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_M_AXI_BYTES_LOG) ) last_beat_curr_word_inst ( .CIN(last_beat_ii), .S(sel_first_word), .A(current_word_1), .B(cmd_first_word), .V(cmd_last_word), .COUT(last_word) ); end endgenerate ///////////////////////////////////////////////////////////////////////////// // Handle wrap buffer: // // The wrap buffer is used to move data around in an unaligned WRAP // transaction. The requested read address has been rounded down, meaning // that parts of the first MI-side data beat has to be delayed for later use. // The extraction starts at the origian unaligned address, the remaining data // is stored in the wrap buffer to be extracted after the last MI-side data // beat has been fully processed. // For example: an 32bit to 64bit read upsizing @ 0x4 will request a MI-side // read WRAP transaction 0x0. The 0x4 data word is used at once and the 0x0 // word is delayed to be used after all data in the last MI-side beat has // arrived. // ///////////////////////////////////////////////////////////////////////////// // Save data to be able to perform buffer wraping. assign store_in_wrap_buffer = M_AXI_RVALID_I & cmd_packed_wrap & first_mi_word & ~use_wrap_buffer; // Mark that there are data available for wrap buffering. always @ (posedge ACLK) begin if (ARESET) begin wrap_buffer_available <= 1'b0; end else begin if ( store_in_wrap_buffer & word_completed & pop_si_data ) begin wrap_buffer_available <= 1'b1; end else if ( last_beat & word_completed & pop_si_data ) begin wrap_buffer_available <= 1'b0; end end end // Start using the wrap buffer. always @ (posedge ACLK) begin if (ARESET) begin use_wrap_buffer <= 1'b0; end else begin if ( wrap_buffer_available & last_beat & word_completed & pop_si_data ) begin use_wrap_buffer <= 1'b1; end else if ( cmd_ready_i ) begin use_wrap_buffer <= 1'b0; end end end // Store data in wrap buffer. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_RDATA_I <= {C_M_AXI_DATA_WIDTH{1'b0}}; rid_wrap_buffer <= {C_AXI_ID_WIDTH{1'b0}}; rresp_wrap_buffer <= 2'b0; ruser_wrap_buffer <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( store_in_wrap_buffer ) begin M_AXI_RDATA_I <= M_AXI_RDATA; rid_wrap_buffer <= M_AXI_RID; rresp_wrap_buffer <= M_AXI_RRESP; ruser_wrap_buffer <= M_AXI_RUSER; end end end ///////////////////////////////////////////////////////////////////////////// // Select the SI-side word to read. // // Everything must be multiplexed since the next transfer can be arriving // with a different set of signals while the wrap buffer is still being // processed for the current transaction. // // Non modifiable word has a 1:1 ratio, i.e. only one SI-side word is // generated per MI-side word. // Data is taken either directly from the incomming MI-side data or the // wrap buffer (for packed WRAP). // // Last need special handling since it is the last SI-side word generated // from the MI-side word. // ///////////////////////////////////////////////////////////////////////////// // ID, RESP and USER has to be multiplexed. assign S_AXI_RID_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? rid_wrap_buffer : M_AXI_RID; assign S_AXI_RRESP_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? rresp_wrap_buffer : M_AXI_RRESP; assign S_AXI_RUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? ruser_wrap_buffer : M_AXI_RUSER : {C_AXI_RUSER_WIDTH{1'b0}}; // Data has to be multiplexed. generate if ( C_RATIO == 1 ) begin : SINGLE_WORD assign S_AXI_RDATA_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? M_AXI_RDATA_I : M_AXI_RDATA; end else begin : MULTIPLE_WORD // Get the ratio bits (MI-side words vs SI-side words). wire [C_RATIO_LOG-1:0] current_index; assign current_index = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG]; assign S_AXI_RDATA_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? M_AXI_RDATA_I[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] : M_AXI_RDATA[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH]; end endgenerate // Generate the true last flag including "keep" while using wrap buffer. assign M_AXI_RLAST_I = ( M_AXI_RLAST | use_wrap_buffer ); // Handle last flag, i.e. set for SI-side last word. assign S_AXI_RLAST_I = last_word; ///////////////////////////////////////////////////////////////////////////// // SI-side output handling ///////////////////////////////////////////////////////////////////////////// generate if ( C_S_AXI_REGISTER ) begin : USE_REGISTER reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID_q; reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_q; reg [2-1:0] S_AXI_RRESP_q; reg S_AXI_RLAST_q; reg [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_q; reg S_AXI_RVALID_q; reg S_AXI_RREADY_q; // Register SI-side Data. always @ (posedge ACLK) begin if (ARESET) begin S_AXI_RID_q <= {C_AXI_ID_WIDTH{1'b0}}; S_AXI_RDATA_q <= {C_S_AXI_DATA_WIDTH{1'b0}}; S_AXI_RRESP_q <= 2'b0; S_AXI_RLAST_q <= 1'b0; S_AXI_RUSER_q <= {C_AXI_RUSER_WIDTH{1'b0}}; S_AXI_RVALID_q <= 1'b0; end else begin if ( S_AXI_RREADY_I ) begin S_AXI_RID_q <= S_AXI_RID_I; S_AXI_RDATA_q <= S_AXI_RDATA_I; S_AXI_RRESP_q <= S_AXI_RRESP_I; S_AXI_RLAST_q <= S_AXI_RLAST_I; S_AXI_RUSER_q <= S_AXI_RUSER_I; S_AXI_RVALID_q <= S_AXI_RVALID_I; end end end assign S_AXI_RID = S_AXI_RID_q; assign S_AXI_RDATA = S_AXI_RDATA_q; assign S_AXI_RRESP = S_AXI_RRESP_q; assign S_AXI_RLAST = S_AXI_RLAST_q; assign S_AXI_RUSER = S_AXI_RUSER_q; assign S_AXI_RVALID = S_AXI_RVALID_q; assign S_AXI_RREADY_I = ( S_AXI_RVALID_q & S_AXI_RREADY) | ~S_AXI_RVALID_q; end else begin : NO_REGISTER // Combinatorial SI-side Data. assign S_AXI_RREADY_I = S_AXI_RREADY; assign S_AXI_RVALID = S_AXI_RVALID_I; assign S_AXI_RID = S_AXI_RID_I; assign S_AXI_RDATA = S_AXI_RDATA_I; assign S_AXI_RRESP = S_AXI_RRESP_I; assign S_AXI_RLAST = S_AXI_RLAST_I; assign S_AXI_RUSER = S_AXI_RUSER_I; end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_w_upsizer.v ================================================ // -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Data Up-Sizer // Mirror data for simple accesses. // Merge data for burst. // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // ddr_w_upsizer // //-------------------------------------------------------------------------- `timescale 1ps/1ps module mig_7series_v4_0_ddr_w_upsizer # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter C_S_AXI_DATA_WIDTH = 32'h00000020, // Width of S_AXI_WDATA and S_AXI_RDATA. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter C_M_AXI_DATA_WIDTH = 32'h00000040, // Width of M_AXI_WDATA and M_AXI_RDATA. // Assume greater than or equal to C_S_AXI_DATA_WIDTH. // Format: Bit32; // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100. parameter integer C_M_AXI_REGISTER = 0, // Clock output data. // Range: 0, 1 parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals. // Range: >= 1. parameter integer C_PACKING_LEVEL = 1, // 0 = Never pack (expander only); packing logic is omitted. // 1 = Pack only when CACHE[1] (Modifiable) is high. // 2 = Always pack, regardless of sub-size transaction or Modifiable bit. // (Required when used as helper-core by mem-con.) parameter integer C_SUPPORT_BURSTS = 1, // Disabled when all connected masters and slaves are AxiLite, // allowing logic to be simplified. parameter integer C_S_AXI_BYTES_LOG = 3, // Log2 of number of 32bit word on SI-side. parameter integer C_M_AXI_BYTES_LOG = 3, // Log2 of number of 32bit word on MI-side. parameter integer C_RATIO = 2, // Up-Sizing ratio for data. parameter integer C_RATIO_LOG = 1 // Log2 of Up-Sizing ratio for data. ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_valid, input wire cmd_fix, input wire cmd_modified, input wire cmd_complete_wrap, input wire cmd_packed_wrap, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset, input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask, input wire [C_S_AXI_BYTES_LOG:0] cmd_step, input wire [8-1:0] cmd_length, output wire cmd_ready, // Slave Interface Write Data Ports input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Master Interface Write Data Ports output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for SI-side word lanes on MI-side. genvar word_cnt; // Generate variable for intra SI-word byte control (on MI-side) for always pack. genvar byte_cnt; genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam integer C_NEVER_PACK = 0; localparam integer C_DEFAULT_PACK = 1; localparam integer C_ALWAYS_PACK = 2; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Sub-word handling. wire sel_first_word; wire first_word; wire [C_M_AXI_BYTES_LOG-1:0] current_word_1; wire [C_M_AXI_BYTES_LOG-1:0] current_word; wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted; wire [C_RATIO-1:0] current_word_idx; wire last_beat; wire last_word; wire last_word_extra_carry; wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i; // Sub-word handling for the next cycle. wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i; wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word; wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1; wire [C_M_AXI_BYTES_LOG-1:0] next_word_i; wire [C_M_AXI_BYTES_LOG-1:0] next_word; // Burst length handling. wire first_mi_word; wire [8-1:0] length_counter_1; reg [8-1:0] length_counter; wire [8-1:0] next_length_counter; // Handle wrap buffering. wire store_in_wrap_buffer_enabled; wire store_in_wrap_buffer; wire ARESET_or_store_in_wrap_buffer; wire use_wrap_buffer; reg wrap_buffer_available; // Detect start of MI word. wire first_si_in_mi; // Throttling help signals. wire word_complete_next_wrap; wire word_complete_next_wrap_qual; wire word_complete_next_wrap_valid; wire word_complete_next_wrap_pop; wire word_complete_next_wrap_last; wire word_complete_next_wrap_stall; wire word_complete_last_word; wire word_complete_rest; wire word_complete_rest_qual; wire word_complete_rest_valid; wire word_complete_rest_pop; wire word_complete_rest_last; wire word_complete_rest_stall; wire word_completed; wire word_completed_qualified; wire cmd_ready_i; wire pop_si_data; wire pop_mi_data_i; wire pop_mi_data; wire mi_stalling; // Internal SI side control signals. wire S_AXI_WREADY_I; // Internal packed write data. wire use_expander_data; wire [C_M_AXI_DATA_WIDTH/8-1:0] wdata_qualifier; // For FPGA only wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_qualifier; // For FPGA only wire [C_M_AXI_DATA_WIDTH/8-1:0] wrap_qualifier; // For FPGA only wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_i; // For FPGA only wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_i; // For FPGA only reg [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_q; // For RTL only reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_q; // For RTL only wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer; wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer; reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_II; reg [C_M_AXI_DATA_WIDTH-1:0] wdata_last_word_mux; reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_last_word_mux; reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_cmb; // For FPGA only reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_cmb; // For FPGA only reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_q; // For RTL only reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_q; // For RTL only wire [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer; wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer; // Internal signals for MI-side. wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_cmb; // For FPGA only wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_q; // For FPGA only reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I; wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_cmb; // For FPGA only wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_q; // For FPGA only reg [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I; wire M_AXI_WLAST_I; reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I; wire M_AXI_WVALID_I; wire M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Data on the MI-side is available when data a complete word has been // assembled from the data on SI-side (and potentially from any remainder in // the wrap buffer). // No data is produced on the MI-side when a unaligned packed wrap is // encountered, instead it stored in the wrap buffer to be used when the // last SI-side data beat is received. // // The command is popped from the command queue once the last beat on the // SI-side has been ackowledged. // // The packing process is stalled when a new MI-side is completed but not // yet acknowledged (by ready). // ///////////////////////////////////////////////////////////////////////////// generate if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step}; end else begin : NO_LARGE_UPSIZING assign cmd_step_i = cmd_step; end endgenerate generate if ( C_FAMILY == "rtl" || ( C_SUPPORT_BURSTS == 0 ) || ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED // Detect when MI-side word is completely assembled. assign word_completed = ( cmd_fix ) | ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | ( ~cmd_fix & last_word ) | ( ~cmd_modified ) | ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ); assign word_completed_qualified = word_completed & cmd_valid & ~store_in_wrap_buffer_enabled; // RTL equivalent of optimized partial extressions (address wrap for next word). assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ); assign word_complete_next_wrap_qual = word_complete_next_wrap & cmd_valid & ~store_in_wrap_buffer_enabled; assign word_complete_next_wrap_valid = word_complete_next_wrap_qual & S_AXI_WVALID; assign word_complete_next_wrap_pop = word_complete_next_wrap_valid & M_AXI_WREADY_I; assign word_complete_next_wrap_last = word_complete_next_wrap_pop & M_AXI_WLAST_I; assign word_complete_next_wrap_stall = word_complete_next_wrap_valid & ~M_AXI_WREADY_I; // RTL equivalent of optimized partial extressions (last word and the remaining). assign word_complete_last_word = last_word & ~cmd_fix; assign word_complete_rest = word_complete_last_word | cmd_fix | ~cmd_modified; assign word_complete_rest_qual = word_complete_rest & cmd_valid & ~store_in_wrap_buffer_enabled; assign word_complete_rest_valid = word_complete_rest_qual & S_AXI_WVALID; assign word_complete_rest_pop = word_complete_rest_valid & M_AXI_WREADY_I; assign word_complete_rest_last = word_complete_rest_pop & M_AXI_WLAST_I; assign word_complete_rest_stall = word_complete_rest_valid & ~M_AXI_WREADY_I; end else begin : USE_FPGA_WORD_COMPLETED wire next_word_wrap; wire sel_word_complete_next_wrap; wire sel_word_complete_next_wrap_qual; wire sel_word_complete_next_wrap_stall; wire sel_last_word; wire sel_word_complete_rest; wire sel_word_complete_rest_qual; wire sel_word_complete_rest_stall; // Optimize next word address wrap branch of expression. // mig_7series_v4_0_ddr_comparator_sel_static # ( .C_FAMILY(C_FAMILY), .C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}), .C_DATA_WIDTH(C_M_AXI_BYTES_LOG) ) next_word_wrap_inst ( .CIN(1'b1), .S(sel_first_word), .A(pre_next_word_1), .B(cmd_next_word), .COUT(next_word_wrap) ); assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_inst ( .CIN(next_word_wrap), .S(sel_word_complete_next_wrap), .COUT(word_complete_next_wrap) ); assign sel_word_complete_next_wrap_qual = cmd_valid & ~store_in_wrap_buffer_enabled; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_valid_inst ( .CIN(word_complete_next_wrap), .S(sel_word_complete_next_wrap_qual), .COUT(word_complete_next_wrap_qual) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_qual_inst ( .CIN(word_complete_next_wrap_qual), .S(S_AXI_WVALID), .COUT(word_complete_next_wrap_valid) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_pop_inst ( .CIN(word_complete_next_wrap_valid), .S(M_AXI_WREADY_I), .COUT(word_complete_next_wrap_pop) ); assign sel_word_complete_next_wrap_stall = ~M_AXI_WREADY_I; mig_7series_v4_0_ddr_carry_latch_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_stall_inst ( .CIN(word_complete_next_wrap_valid), .I(sel_word_complete_next_wrap_stall), .O(word_complete_next_wrap_stall) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_last_inst ( .CIN(word_complete_next_wrap_pop), .S(M_AXI_WLAST_I), .COUT(word_complete_next_wrap_last) ); // Optimize last word and "rest" branch of expression. // assign sel_last_word = ~cmd_fix; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) last_word_inst_2 ( .CIN(last_word_extra_carry), .S(sel_last_word), .COUT(word_complete_last_word) ); assign sel_word_complete_rest = cmd_fix | ~cmd_modified; mig_7series_v4_0_ddr_carry_or # ( .C_FAMILY(C_FAMILY) ) pop_si_data_inst ( .CIN(word_complete_last_word), .S(sel_word_complete_rest), .COUT(word_complete_rest) ); assign sel_word_complete_rest_qual = cmd_valid & ~store_in_wrap_buffer_enabled; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_valid_inst ( .CIN(word_complete_rest), .S(sel_word_complete_rest_qual), .COUT(word_complete_rest_qual) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_qual_inst ( .CIN(word_complete_rest_qual), .S(S_AXI_WVALID), .COUT(word_complete_rest_valid) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_pop_inst ( .CIN(word_complete_rest_valid), .S(M_AXI_WREADY_I), .COUT(word_complete_rest_pop) ); assign sel_word_complete_rest_stall = ~M_AXI_WREADY_I; mig_7series_v4_0_ddr_carry_latch_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_stall_inst ( .CIN(word_complete_rest_valid), .I(sel_word_complete_rest_stall), .O(word_complete_rest_stall) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) word_complete_rest_last_inst ( .CIN(word_complete_rest_pop), .S(M_AXI_WLAST_I), .COUT(word_complete_rest_last) ); // Combine the two branches to generate the full signal. assign word_completed = word_complete_next_wrap | word_complete_rest; assign word_completed_qualified = word_complete_next_wrap_qual | word_complete_rest_qual; end endgenerate // Pop word from SI-side. assign S_AXI_WREADY_I = ~mi_stalling & cmd_valid; assign S_AXI_WREADY = S_AXI_WREADY_I; // Indicate when there is data available @ MI-side. generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_M_WVALID assign M_AXI_WVALID_I = S_AXI_WVALID & word_completed_qualified; end else begin : USE_FPGA_M_WVALID assign M_AXI_WVALID_I = ( word_complete_next_wrap_valid | word_complete_rest_valid); end endgenerate // Get SI-side data. generate if ( C_M_AXI_REGISTER ) begin : USE_REGISTER_SI_POP assign pop_si_data = S_AXI_WVALID & ~mi_stalling & cmd_valid; end else begin : NO_REGISTER_SI_POP if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_SI assign pop_si_data = S_AXI_WVALID & S_AXI_WREADY_I; end else begin : USE_FPGA_POP_SI assign pop_si_data = ~( word_complete_next_wrap_stall | word_complete_rest_stall ) & cmd_valid & S_AXI_WVALID; end end endgenerate // Signal that the command is done (so that it can be poped from command queue). generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_CMD_READY assign cmd_ready_i = cmd_valid & M_AXI_WLAST_I & pop_mi_data_i; end else begin : USE_FPGA_CMD_READY assign cmd_ready_i = ( word_complete_next_wrap_last | word_complete_rest_last); end endgenerate assign cmd_ready = cmd_ready_i; // Set last upsized word. assign M_AXI_WLAST_I = S_AXI_WLAST; ///////////////////////////////////////////////////////////////////////////// // Keep track of data extraction: // // Current address is taken form the command buffer for the first data beat // to handle unaligned Write transactions. After this is the extraction // address usually calculated from this point. // FIX transactions uses the same word address for all data beats. // // Next word address is generated as current word plus the current step // size, with masking to facilitate sub-sized wraping. The Mask is all ones // for normal wraping, and less when sub-sized wraping is used. // // The calculated word addresses (current and next) is offseted by the // current Offset. For sub-sized transaction the Offest points to the least // significant address of the included data beats. (The least significant // word is not necessarily the first data to be packed, consider WRAP). // Offset is only used for sub-sized WRAP transcation that are Complete. // // First word is active during the first SI-side data beat. // // First MI is set while the entire first MI-side word is processed. // // The transaction length is taken from the command buffer combinatorialy // during the First MI cycle. For each generated MI word it is decreased // until Last beat is reached. // ///////////////////////////////////////////////////////////////////////////// // Select if the offset comes from command queue directly or // from a counter while when extracting multiple SI words per MI word assign sel_first_word = first_word | cmd_fix; assign current_word = sel_first_word ? cmd_first_word : current_word_1; generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD // Calculate next word. assign pre_next_word_i = ( next_word_i + cmd_step_i ); // Calculate next word. assign next_word_i = sel_first_word ? cmd_next_word : pre_next_word_1; end else begin : USE_FPGA_NEXT_WORD wire [C_M_AXI_BYTES_LOG-1:0] next_sel; wire [C_M_AXI_BYTES_LOG:0] next_carry_local; // Assign input to local vectors. assign next_carry_local[0] = 1'b0; // Instantiate one carry and per level. for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL LUT6_2 # ( .INIT(64'h5A5A_5A66_F0F0_F0CC) ) LUT6_2_inst ( .O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit) .O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit) .I0(cmd_step_i[bit_cnt]), // LUT input (1-bit) .I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit) .I2(cmd_next_word[bit_cnt]), // LUT input (1-bit) .I3(first_word), // LUT input (1-bit) .I4(cmd_fix), // LUT input (1-bit) .I5(1'b1) // LUT input (1-bit) ); MUXCY next_carry_inst ( .O (next_carry_local[bit_cnt+1]), .CI (next_carry_local[bit_cnt]), .DI (cmd_step_i[bit_cnt]), .S (next_sel[bit_cnt]) ); XORCY next_xorcy_inst ( .O(pre_next_word_i[bit_cnt]), .CI(next_carry_local[bit_cnt]), .LI(next_sel[bit_cnt]) ); end // end for bit_cnt end endgenerate // Calculate next word. assign next_word = next_word_i & cmd_mask; assign pre_next_word = pre_next_word_i & cmd_mask; // Calculate the word address with offset. assign current_word_adjusted = sel_first_word ? ( cmd_first_word | cmd_offset ) : ( current_word_1 | cmd_offset ); // Prepare next word address. generate if ( C_FAMILY == "rtl" || C_M_AXI_REGISTER ) begin : USE_RTL_CURR_WORD reg [C_M_AXI_BYTES_LOG-1:0] current_word_q; reg first_word_q; reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_q; always @ (posedge ACLK) begin if (ARESET) begin first_word_q <= 1'b1; current_word_q <= {C_M_AXI_BYTES_LOG{1'b0}}; pre_next_word_q <= {C_M_AXI_BYTES_LOG{1'b0}}; end else begin if ( pop_si_data ) begin if ( S_AXI_WLAST ) begin // Prepare for next access. first_word_q <= 1'b1; end else begin first_word_q <= 1'b0; end current_word_q <= next_word; pre_next_word_q <= pre_next_word; end end end assign first_word = first_word_q; assign current_word_1 = current_word_q; assign pre_next_word_1 = pre_next_word_q; end else begin : USE_FPGA_CURR_WORD reg first_word_cmb; wire first_word_i; wire [C_M_AXI_BYTES_LOG-1:0] current_word_i; wire [C_M_AXI_BYTES_LOG-1:0] local_pre_next_word_i; always @ * begin if ( S_AXI_WLAST ) begin // Prepare for next access. first_word_cmb = 1'b1; end else begin first_word_cmb = 1'b0; end end for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : BIT_LANE LUT6 # ( .INIT(64'hCCCA_CCCC_CCCC_CCCC) ) LUT6_current_inst ( .O(current_word_i[bit_cnt]), // 6-LUT output (1-bit) .I0(next_word[bit_cnt]), // LUT input (1-bit) .I1(current_word_1[bit_cnt]), // LUT input (1-bit) .I2(word_complete_rest_stall), // LUT input (1-bit) .I3(word_complete_next_wrap_stall), // LUT input (1-bit) .I4(cmd_valid), // LUT input (1-bit) .I5(S_AXI_WVALID) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_current_inst ( .Q(current_word_1[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(current_word_i[bit_cnt]) // Data input ); LUT6 # ( .INIT(64'hCCCA_CCCC_CCCC_CCCC) ) LUT6_next_inst ( .O(local_pre_next_word_i[bit_cnt]), // 6-LUT output (1-bit) .I0(pre_next_word[bit_cnt]), // LUT input (1-bit) .I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit) .I2(word_complete_rest_stall), // LUT input (1-bit) .I3(word_complete_next_wrap_stall), // LUT input (1-bit) .I4(cmd_valid), // LUT input (1-bit) .I5(S_AXI_WVALID) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_next_inst ( .Q(pre_next_word_1[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(local_pre_next_word_i[bit_cnt]) // Data input ); end // end for bit_cnt LUT6 # ( .INIT(64'hCCCA_CCCC_CCCC_CCCC) ) LUT6_first_inst ( .O(first_word_i), // 6-LUT output (1-bit) .I0(first_word_cmb), // LUT input (1-bit) .I1(first_word), // LUT input (1-bit) .I2(word_complete_rest_stall), // LUT input (1-bit) .I3(word_complete_next_wrap_stall), // LUT input (1-bit) .I4(cmd_valid), // LUT input (1-bit) .I5(S_AXI_WVALID) // LUT input (1-bit) ); FDSE #( .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) ) FDSE_first_inst ( .Q(first_word), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .S(ARESET), // Synchronous reset input .D(first_word_i) // Data input ); end endgenerate // Select command length or counted length. always @ * begin if ( first_mi_word ) length_counter = cmd_length; else length_counter = length_counter_1; end generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH reg [8-1:0] length_counter_q; reg first_mi_word_q; // Calculate next length counter value. assign next_length_counter = length_counter - 1'b1; // Keep track of burst length. always @ (posedge ACLK) begin if (ARESET) begin first_mi_word_q <= 1'b1; length_counter_q <= 8'b0; end else begin if ( pop_mi_data_i ) begin if ( M_AXI_WLAST_I ) begin first_mi_word_q <= 1'b1; end else begin first_mi_word_q <= 1'b0; end length_counter_q <= next_length_counter; end end end assign first_mi_word = first_mi_word_q; assign length_counter_1 = length_counter_q; end else begin : USE_FPGA_LENGTH wire [8-1:0] length_counter_i; wire [8-1:0] length_counter_ii; wire [8-1:0] length_sel; wire [8-1:0] length_di; wire [8:0] length_local_carry; // Assign input to local vectors. assign length_local_carry[0] = 1'b0; for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE LUT6_2 # ( .INIT(64'h333C_555A_FFF0_FFF0) ) LUT6_length_inst ( .O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit) .O5(length_di[bit_cnt]), // 5-LUT output (1-bit) .I0(length_counter_1[bit_cnt]), // LUT input (1-bit) .I1(cmd_length[bit_cnt]), // LUT input (1-bit) .I2(1'b1), // LUT input (1-bit) .I3(1'b1), // LUT input (1-bit) .I4(first_mi_word), // LUT input (1-bit) .I5(1'b1) // LUT input (1-bit) ); MUXCY carry_inst ( .O (length_local_carry[bit_cnt+1]), .CI (length_local_carry[bit_cnt]), .DI (length_di[bit_cnt]), .S (length_sel[bit_cnt]) ); XORCY xorcy_inst ( .O(length_counter_ii[bit_cnt]), .CI(length_local_carry[bit_cnt]), .LI(length_sel[bit_cnt]) ); LUT4 # ( .INIT(16'hCCCA) ) LUT4_inst ( .O(length_counter_i[bit_cnt]), // 5-LUT output (1-bit) .I0(length_counter_1[bit_cnt]), // LUT input (1-bit) .I1(length_counter_ii[bit_cnt]), // LUT input (1-bit) .I2(word_complete_rest_pop), // LUT input (1-bit) .I3(word_complete_next_wrap_pop) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_length_inst ( .Q(length_counter_1[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(length_counter_i[bit_cnt]) // Data input ); end // end for bit_cnt wire first_mi_word_i; LUT6 # ( .INIT(64'hAAAC_AAAC_AAAC_AAAC) ) LUT6_first_mi_inst ( .O(first_mi_word_i), // 6-LUT output (1-bit) .I0(M_AXI_WLAST_I), // LUT input (1-bit) .I1(first_mi_word), // LUT input (1-bit) .I2(word_complete_rest_pop), // LUT input (1-bit) .I3(word_complete_next_wrap_pop), // LUT input (1-bit) .I4(1'b1), // LUT input (1-bit) .I5(1'b1) // LUT input (1-bit) ); FDSE #( .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) ) FDSE_inst ( .Q(first_mi_word), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .S(ARESET), // Synchronous reset input .D(first_mi_word_i) // Data input ); end endgenerate generate if ( C_FAMILY == "rtl" || C_SUPPORT_BURSTS == 0 ) begin : USE_RTL_LAST_WORD // Detect last beat in a burst. assign last_beat = ( length_counter == 8'b0 ); // Determine if this last word that shall be assembled into this MI-side word. assign last_word = ( cmd_modified & last_beat & ( current_word == cmd_last_word ) ) | ( C_SUPPORT_BURSTS == 0 ); end else begin : USE_FPGA_LAST_WORD wire last_beat_curr_word; mig_7series_v4_0_ddr_comparator_sel_static # ( .C_FAMILY(C_FAMILY), .C_VALUE(8'b0), .C_DATA_WIDTH(8) ) last_beat_inst ( .CIN(1'b1), .S(first_mi_word), .A(length_counter_1), .B(cmd_length), .COUT(last_beat) ); mig_7series_v4_0_ddr_comparator_sel # ( .C_FAMILY(C_FAMILY), .C_DATA_WIDTH(C_M_AXI_BYTES_LOG) ) last_beat_curr_word_inst ( .CIN(last_beat), .S(sel_first_word), .A(current_word_1), .B(cmd_first_word), .V(cmd_last_word), .COUT(last_beat_curr_word) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) last_word_inst ( .CIN(last_beat_curr_word), .S(cmd_modified), .COUT(last_word) ); end endgenerate ///////////////////////////////////////////////////////////////////////////// // Handle wrap buffer: // // The wrap buffer is used to move data around in an unaligned WRAP // transaction. SI-side data word(s) for an unaligned accesses are delay // to be packed with with the tail of the transaction to make it a WRAP // transaction that is aligned to native MI-side data with. // For example: an 32bit to 64bit write upsizing @ 0x4 will delay the first // word until the 0x0 data arrives in the last data beat. This will make the // Upsized transaction be WRAP at 0x8 on the MI-side // (was WRAP @ 0x4 on SI-side). // ///////////////////////////////////////////////////////////////////////////// // The unaligned SI-side words are pushed into the wrap buffer. assign store_in_wrap_buffer_enabled = cmd_packed_wrap & ~wrap_buffer_available & cmd_valid; assign store_in_wrap_buffer = store_in_wrap_buffer_enabled & S_AXI_WVALID; assign ARESET_or_store_in_wrap_buffer = store_in_wrap_buffer | ARESET; // The wrap buffer is used to complete last word. generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_USE_WRAP assign use_wrap_buffer = wrap_buffer_available & last_word; end else begin : USE_FPGA_USE_WRAP wire last_word_carry; mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) last_word_inst2 ( .CIN(last_word), .S(1'b1), .COUT(last_word_carry) ); mig_7series_v4_0_ddr_carry_and # ( .C_FAMILY(C_FAMILY) ) last_word_inst3 ( .CIN(last_word_carry), .S(1'b1), .COUT(last_word_extra_carry) ); mig_7series_v4_0_ddr_carry_latch_and # ( .C_FAMILY(C_FAMILY) ) word_complete_next_wrap_stall_inst ( .CIN(last_word_carry), .I(wrap_buffer_available), .O(use_wrap_buffer) ); end endgenerate // Wrap buffer becomes available when the unaligned wrap words has been taken care of. always @ (posedge ACLK) begin if (ARESET) begin wrap_buffer_available <= 1'b0; end else begin if ( store_in_wrap_buffer & word_completed ) begin wrap_buffer_available <= 1'b1; end else if ( cmd_ready_i ) begin wrap_buffer_available <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Handle USER bits: // // The USER bits are always propagated from the least significant SI-side // beat to the Up-Sized MI-side data beat. That means: // * FIX transactions propagate all USER data (1:1 SI- vs MI-side beat ratio). // * INCR transactions uses the first SI-side beat that goes into a MI-side // data word. // * WRAP always propagates the USER bits from the most zero aligned SI-side // data word, regardless if the data is packed or not. For unpacked data // this would be a 1:1 ratio. ///////////////////////////////////////////////////////////////////////////// // Detect first SI-side word per MI-side word. assign first_si_in_mi = cmd_fix | first_word | ~cmd_modified | (cmd_modified & current_word == {C_M_AXI_BYTES_LOG{1'b0}}) | ( C_SUPPORT_BURSTS == 0 ); // Select USER bits combinatorially when expanding or fix. always @ * begin if ( C_AXI_SUPPORTS_USER_SIGNALS ) begin if ( first_si_in_mi ) begin M_AXI_WUSER_I = S_AXI_WUSER; end else begin M_AXI_WUSER_I = M_AXI_WUSER_II; end end else begin M_AXI_WUSER_I = {C_AXI_WUSER_WIDTH{1'b0}}; end end // Capture user bits. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_WUSER_II <= {C_AXI_WUSER_WIDTH{1'b0}}; end else begin if ( first_si_in_mi & pop_si_data ) begin M_AXI_WUSER_II <= S_AXI_WUSER; end end end ///////////////////////////////////////////////////////////////////////////// // Pack multiple data SI-side words into fewer MI-side data word. // Data is only packed when modify is set. Granularity is SI-side word for // the combinatorial data mux. // // Expander: // WDATA is expanded to all SI-word lane on the MI-side. // WSTRB is activted to the correct SI-word lane on the MI-side. // // Packer: // The WDATA and WSTRB registers are always cleared before a new word is // assembled. // WDATA is (SI-side word granularity) // * Combinatorial WDATA is used for current word line or when expanding. // * All other is taken from registers. // WSTRB is // * Combinatorial for single data to matching word lane // * Zero for single data to mismatched word lane // * Register data when multiple data // // To support sub-sized packing during Always Pack is the combinatorial // information packed with "or" instead of multiplexing. // ///////////////////////////////////////////////////////////////////////////// // Determine if expander data should be used. assign use_expander_data = ~cmd_modified & cmd_valid; // Registers and combinatorial data word mux. generate for (word_cnt = 0; word_cnt < C_RATIO ; word_cnt = word_cnt + 1) begin : WORD_LANE // Generate select signal per SI-side word. if ( C_RATIO == 1 ) begin : SINGLE_WORD assign current_word_idx[word_cnt] = 1'b1; end else begin : MULTIPLE_WORD assign current_word_idx[word_cnt] = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG] == word_cnt; end if ( ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ) ) begin : USE_EXPANDER // Expander only functionality. if ( C_M_AXI_REGISTER ) begin : USE_REGISTER always @ (posedge ACLK) begin if (ARESET) begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = {C_S_AXI_DATA_WIDTH{1'b0}}; M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}}; end else begin if ( pop_si_data ) begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA; // Multiplex write strobe. if ( current_word_idx[word_cnt] ) begin // Combinatorial for last word to MI-side (only word for single). M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB; end else begin // Use registered strobes. Registers are zero until valid data is written. // I.e. zero when used for mismatched lanes while expanding. M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}}; end end end end end else begin : NO_REGISTER always @ * begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA; // Multiplex write strobe. if ( current_word_idx[word_cnt] ) begin // Combinatorial for last word to MI-side (only word for single). M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB; end else begin // Use registered strobes. Registers are zero until valid data is written. // I.e. zero when used for mismatched lanes while expanding. M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}}; end end end // end if C_M_AXI_REGISTER end else begin : USE_ALWAYS_PACKER // Packer functionality for (byte_cnt = 0; byte_cnt < C_S_AXI_DATA_WIDTH / 8 ; byte_cnt = byte_cnt + 1) begin : BYTE_LANE if ( C_FAMILY == "rtl" ) begin : USE_RTL_DATA // Generate extended write data and strobe in wrap buffer. always @ (posedge ACLK) begin if (ARESET) begin wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0; wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0; end else begin if ( cmd_ready_i ) begin wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0; wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0; end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8]; wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt]; end end end assign wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8]; assign wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1]; if ( C_M_AXI_REGISTER ) begin : USE_REGISTER always @ (posedge ACLK) begin if (ARESET) begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0; M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0; end else begin if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer ) begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8]; end else if ( use_wrap_buffer & pop_si_data & wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8]; end else if ( pop_mi_data ) begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0; end if ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer ) begin M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt]; end else if ( use_wrap_buffer & pop_si_data & wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b1; end else if ( pop_mi_data ) begin M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0; end end end end else begin : NO_REGISTER // Generate extended write data and strobe. always @ (posedge ACLK) begin if (ARESET) begin wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0; wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0; end else begin if ( pop_mi_data | store_in_wrap_buffer_enabled ) begin wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0; wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0; end else if ( current_word_idx[word_cnt] & pop_si_data & S_AXI_WSTRB[byte_cnt] ) begin wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8]; wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt]; end end end assign wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8]; assign wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1]; // Select packed or extended data. always @ * begin // Multiplex data. if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8]; end else begin wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0; end // Multiplex write strobe. if ( current_word_idx[word_cnt] ) begin // Combinatorial for last word to MI-side (only word for single). wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt]; end else begin // Use registered strobes. Registers are zero until valid data is written. // I.e. zero when used for mismatched lanes while expanding. wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0; end end // Merge previous with current data. always @ * begin M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = ( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) | ( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) | ( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer ); M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = ( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) | ( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) | ( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} ); end end // end if C_M_AXI_REGISTER end else begin : USE_FPGA_DATA always @ * begin if ( cmd_ready_i ) begin wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0; wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0; end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8]; wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b1; end else begin wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8]; wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1]; end end for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_wdata_inst ( .Q(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input ); end // end for bit_cnt FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_wstrb_inst ( .Q(wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input ); if ( C_M_AXI_REGISTER ) begin : USE_REGISTER assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer_enabled; assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer_enabled; assign wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = use_wrap_buffer & pop_si_data & wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1]; for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE LUT6 # ( .INIT(64'hF0F0_F0F0_CCCC_00AA) ) LUT6_data_inst ( .O(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit) .I0(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit) .I1(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit) .I2(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit) .I3(pop_mi_data), // LUT input (1-bit) .I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I5(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_wdata_inst ( .Q(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input ); end // end for bit_cnt LUT6 # ( .INIT(64'hF0F0_F0F0_CCCC_00AA) ) LUT6_strb_inst ( .O(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit) .I0(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I1(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I2(S_AXI_WSTRB[byte_cnt]), // LUT input (1-bit) .I3(pop_mi_data), // LUT input (1-bit) .I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I5(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_wstrb_inst ( .Q(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input ); always @ * begin M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8]; M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1]; end end else begin : NO_REGISTER assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & cmd_valid & S_AXI_WSTRB[byte_cnt]; assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & cmd_valid & S_AXI_WVALID; for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE LUT6 # ( .INIT(64'hCCCA_CCCC_CCCC_CCCC) ) LUT6_data_inst ( .O(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit) .I0(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit) .I1(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit) .I2(word_complete_rest_stall), // LUT input (1-bit) .I3(word_complete_next_wrap_stall), // LUT input (1-bit) .I4(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I5(S_AXI_WVALID) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_wdata_inst ( .Q(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input ); end // end for bit_cnt LUT6 # ( .INIT(64'h0000_0000_0000_AAAE) ) LUT6_strb_inst ( .O(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit) .I0(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I1(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit) .I2(word_complete_rest_stall), // LUT input (1-bit) .I3(word_complete_next_wrap_stall), // LUT input (1-bit) .I4(word_complete_rest_pop), // LUT input (1-bit) .I5(word_complete_next_wrap_pop) // LUT input (1-bit) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_wstrb_inst ( .Q(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET_or_store_in_wrap_buffer), // Synchronous reset input .D(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input ); // Select packed or extended data. always @ * begin // Multiplex data. if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8]; end else begin wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = ( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]}} ) | ( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} ); end // Multiplex write strobe. if ( current_word_idx[word_cnt] ) begin // Combinatorial for last word to MI-side (only word for single). wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt] | ( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) | ( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer ); end else begin // Use registered strobes. Registers are zero until valid data is written. // I.e. zero when used for mismatched lanes while expanding. wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = ( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) | ( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer ); end end // Merge previous with current data. always @ * begin M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = ( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ); M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = ( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ); end end // end if C_M_AXI_REGISTER end // end if C_FAMILY end // end for byte_cnt end // end if USE_ALWAYS_PACKER end // end for word_cnt endgenerate ///////////////////////////////////////////////////////////////////////////// // MI-side output handling ///////////////////////////////////////////////////////////////////////////// generate if ( C_M_AXI_REGISTER ) begin : USE_REGISTER reg M_AXI_WLAST_q; reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_q; reg M_AXI_WVALID_q; // Register MI-side Data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_WLAST_q <= 1'b0; M_AXI_WUSER_q <= {C_AXI_WUSER_WIDTH{1'b0}}; M_AXI_WVALID_q <= 1'b0; end else begin if ( M_AXI_WREADY_I ) begin M_AXI_WLAST_q <= M_AXI_WLAST_I; M_AXI_WUSER_q <= M_AXI_WUSER_I; M_AXI_WVALID_q <= M_AXI_WVALID_I; end end end assign M_AXI_WDATA = M_AXI_WDATA_I; assign M_AXI_WSTRB = M_AXI_WSTRB_I; assign M_AXI_WLAST = M_AXI_WLAST_q; assign M_AXI_WUSER = M_AXI_WUSER_q; assign M_AXI_WVALID = M_AXI_WVALID_q; assign M_AXI_WREADY_I = ( M_AXI_WVALID_q & M_AXI_WREADY) | ~M_AXI_WVALID_q; // Get MI-side data. assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I; assign pop_mi_data = M_AXI_WVALID_q & M_AXI_WREADY_I; // Detect when MI-side is stalling. assign mi_stalling = ( M_AXI_WVALID_q & ~M_AXI_WREADY_I ) & ~store_in_wrap_buffer_enabled; end else begin : NO_REGISTER // Combinatorial MI-side Data. assign M_AXI_WDATA = M_AXI_WDATA_I; assign M_AXI_WSTRB = M_AXI_WSTRB_I; assign M_AXI_WLAST = M_AXI_WLAST_I; assign M_AXI_WUSER = M_AXI_WUSER_I; assign M_AXI_WVALID = M_AXI_WVALID_I; assign M_AXI_WREADY_I = M_AXI_WREADY; // Get MI-side data. if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_MI assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I; end else begin : USE_FPGA_POP_MI assign pop_mi_data_i = ( word_complete_next_wrap_pop | word_complete_rest_pop); end assign pop_mi_data = pop_mi_data_i; // Detect when MI-side is stalling. assign mi_stalling = word_completed_qualified & ~M_AXI_WREADY_I; end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: clk_ibuf.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Mon Aug 3 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** `timescale 1ns/1ps module mig_7series_v4_0_clk_ibuf # ( parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type parameter DIFF_TERM_SYSCLK = "TRUE" // Differential Termination ) ( // Clock inputs input sys_clk_p, // System clock diff input input sys_clk_n, input sys_clk_i, output mmcm_clk ); (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */; generate if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk //*********************************************************************** // Differential input clock input buffers //*********************************************************************** IBUFGDS # ( .DIFF_TERM (DIFF_TERM_SYSCLK), .IBUF_LOW_PWR ("FALSE") ) u_ibufg_sys_clk ( .I (sys_clk_p), .IB (sys_clk_n), .O (sys_clk_ibufg) ); end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk //*********************************************************************** // SINGLE_ENDED input clock input buffers //*********************************************************************** IBUFG # ( .IBUF_LOW_PWR ("FALSE") ) u_ibufg_sys_clk ( .I (sys_clk_i), .O (sys_clk_ibufg) ); end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk //*********************************************************************** // System clock is driven from FPGA internal clock (clock from fabric) //*********************************************************************** assign sys_clk_ibufg = sys_clk_i; end endgenerate assign mmcm_clk = sys_clk_ibufg; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: infrastructure.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Tue Jun 30 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_infrastructure # ( parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and // FALSE during implementations parameter TCQ = 100, // clk->out delay (sim only) parameter CLKIN_PERIOD = 3000, // Memory clock period parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // "DIFFERENTIAL","SINGLE_ENDED" parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 parameter RST_ACT_LOW = 1, parameter tCK = 1250, // memory tCK paramter. // # = Clock Period in pS. parameter MEM_TYPE = "DDR3" ) ( // Clock inputs input mmcm_clk, // System clock diff input // System reset input input sys_rst, // core reset from user application // PLLE2/IDELAYCTRL Lock status input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status // Clock outputs output clk, // fabric clock freq ; either half rate or quarter rate and is // determined by PLL parameters settings. output clk_div2, // mem_refclk divided by 2 for PI incdec output rst_div2, // reset in clk_div2 domain output mem_refclk, // equal to memory clock output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; // to hard PHY for phaser output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide // output auxout_clk, // IO clk used to clock out Aux_Out ports output mmcm_ps_clk, // Phase shift clock output poc_sample_pd, // Tell POC when to sample phase detector output. output ui_addn_clk_0, // MMCM out0 clk output ui_addn_clk_1, // MMCM out1 clk output ui_addn_clk_2, // MMCM out2 clk output ui_addn_clk_3, // MMCM out3 clk output ui_addn_clk_4, // MMCM out4 clk output pll_locked, // locked output from PLLE2_ADV output mmcm_locked, // locked output from MMCME2_ADV // Reset outputs output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), output iddr_rst ,output rst_phaser_ref ,input ref_dll_lock ,input psen ,input psincdec ,output psdone ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) localparam RST_SYNC_NUM = 25; // Round up for clk reset delay to ensure that CLKDIV reset deassertion // occurs at same time or after CLK reset deassertion (still need to // consider route delay - add one or two extra cycles to be sure!) localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; // Input clock is assumed to be equal to the memory clock frequency // User should change the parameter as necessary if a different input // clock frequency is used localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; localparam integer VCO_PERIOD = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; //synthesis translate_off initial begin $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); $display("############################################################\n"); end //synthesis translate_on wire clk_bufg; wire clk_pll; wire clkfbout_pll; wire mmcm_clkfbout; wire pll_locked_i /* synthesis syn_maxfan = 10 */; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; wire rst_tmp; (* max_fanout = 50 *) reg rstdiv0_sync_r1 /* synthesis syn_maxfan = 50 */; reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; (* max_fanout = 10 *) reg rst_sync_r1 /* synthesis syn_maxfan = 10 */; reg [RST_DIV_SYNC_NUM-2:0] rstdiv2_sync_r; (* max_fanout = 10 *) reg rstdiv2_sync_r1 /* synthesis syn_maxfan = 10 */; wire sys_rst_act_hi; wire rst_tmp_phaser_ref; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r /* synthesis syn_maxfan = 10 */; // Instantiation of the MMCM primitive wire clkfbout; wire MMCM_Locked_i; wire mmcm_clkout0; wire mmcm_clkout1; wire mmcm_clkout2; wire mmcm_clkout3; wire mmcm_clkout4; wire mmcm_ps_clk_bufg_in; wire clk_div2_bufg_in; wire pll_clk3_out; wire pll_clk3; assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; //*************************************************************************** // Assign global clocks: // 2. clk : Half rate / Quarter rate(used for majority of internal logic) //*************************************************************************** assign clk = clk_bufg; assign pll_locked = pll_locked_i & MMCM_Locked_i; assign mmcm_locked = MMCM_Locked_i; //*************************************************************************** // Global base clock generation and distribution //*************************************************************************** //***************************************************************** // NOTES ON CALCULTING PROPER VCO FREQUENCY // 1. VCO frequency = // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) // 2. VCO frequency must be in the range [TBD, TBD] //***************************************************************** PLLE2_ADV # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), .CLKOUT5_DIVIDE (), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_PHASE (0.000), .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), .CLKIN2_PERIOD (), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (1.0/16.0), .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_PHASE (CLKOUT4_PHASE), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_PHASE (0.000), .REF_JITTER1 (0.010), .REF_JITTER2 (0.010) ) plle2_i ( .CLKFBOUT (pll_clkfbout), .CLKOUT0 (freq_refclk), .CLKOUT1 (mem_refclk), .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk .CLKOUT3 (pll_clk3_out), // .CLKOUT4 (auxout_clk_i), .CLKOUT4 (), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (pll_locked_i), .CLKFBIN (pll_clkfbout), .CLKIN1 (mmcm_clk), .CLKIN2 (), .CLKINSEL (1'b1), .DADDR (7'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .PWRDWN (1'b0), .RST ( sys_rst_act_hi) ); // BUFH u_bufh_auxout_clk // ( // .O (auxout_clk), // .I (auxout_clk_i) // ); BUFG u_bufg_clkdiv0 ( .O (clk_bufg), .I (clk_pll_i) ); BUFH u_bufh_pll_clk3 ( .O (pll_clk3), .I (pll_clk3_out) ); localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; //synthesis translate_off initial begin $display("############# MMCME2_ADV Parameters #############\n"); $display("MMCM_MULT_F = %d", MMCM_MULT_F); // $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1.000); $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); $display("#################################################\n"); end //synthesis translate_on generate if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_USE_FINE_PS ("FALSE"), .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT5_PHASE (0.000), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_USE_FINE_PS ("TRUE"), .CLKOUT6_DIVIDE (MMCM_MULT_F/2), .CLKOUT6_PHASE (0.000), .CLKOUT6_DUTY_CYCLE (0.500), .CLKOUT6_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_clkout0), .CLKOUT0B (), .CLKOUT1 (mmcm_clkout1), .CLKOUT1B (), .CLKOUT2 (mmcm_clkout2), .CLKOUT2B (), .CLKOUT3 (mmcm_clkout3), .CLKOUT3B (), .CLKOUT4 (mmcm_clkout4), .CLKOUT5 (mmcm_ps_clk_bufg_in), .CLKOUT6 (clk_div2_bufg_in), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_ui_addn_clk_0 ( .O (ui_addn_clk_0), .I (mmcm_clkout0) ); BUFG u_bufg_ui_addn_clk_1 ( .O (ui_addn_clk_1), .I (mmcm_clkout1) ); BUFG u_bufg_ui_addn_clk_2 ( .O (ui_addn_clk_2), .I (mmcm_clkout2) ); BUFG u_bufg_ui_addn_clk_3 ( .O (ui_addn_clk_3), .I (mmcm_clkout3) ); BUFG u_bufg_ui_addn_clk_4 ( .O (ui_addn_clk_4), .I (mmcm_clkout4) ); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); BUFG u_bufg_clk_div2 ( .O (clk_div2), .I (clk_div2_bufg_in) ); end else begin: gen_mmcm MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT1_DIVIDE (MMCM_MULT_F/2), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_ps_clk_bufg_in), .CLKOUT0B (), .CLKOUT1 (clk_div2_bufg_in), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); BUFG u_bufg_clk_div2 ( .O (clk_div2), .I (clk_div2_bufg_in) ); end // block: gen_mmcm endgenerate //*************************************************************************** // Generate poc_sample_pd. // // As the phase shift clocks precesses around kclk, it also precesses // around the fabric clock. Noise may be generated as output of the // IDDR is registered into the fabric clock domain. // // The mmcm_ps_clk signal runs at half the rate of the fabric clock. // This means that there are two rising edges of fabric clock per mmcm_ps_clk. // If we can guarantee that the POC uses the data sampled on the second // fabric clock, then we are certain that the setup time to the second // fabric clock is greater than 1 fabric clock cycle. // // To predict when the phase detctor output is from this second edge, we // need to know two things. The initial phase of fabric clock and mmcm_ps_clk // and the number of phase offsets set into the mmcm. The later is a // trivial count of the PSEN signal. // // The former is a bit tricky because latching a clock with a clock is // not well defined. This problem is solved by generating a signal // the goes high on the first rising edge of mmcm_ps_clk. Logic in // the fabric domain can look at this signal and then develop an analog // the mmcm_ps_clk with zero offset. // // This all depends on the timing tools making the timing work when // when the mmcm phase offset is zero. // // poc_sample_pd tells the POC when to sample the phase detector output. // Setup from the IDDR to the fabric clock is always one plus some // fraction of the fabric clock. //*************************************************************************** localparam ONE = 1; localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; reg inv_poc_sample_ns, inv_poc_sample_r; always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; always @(*) begin qcntr_ns = qcntr_r; inv_poc_sample_ns = inv_poc_sample_r; if (rstdiv0) begin qcntr_ns = 'b0; inv_poc_sample_ns = 'b0; end else if (psen) begin if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); else begin qcntr_ns = {QCNTR_WIDTH{1'b0}}; inv_poc_sample_ns = ~inv_poc_sample_r; end end end // Be vewy vewy careful to make sure this path is aligned with the // phase detector out pipeline. reg first_rising_ps_clk_ns, first_rising_ps_clk_r; always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; always @(*) first_rising_ps_clk_ns = ~rstdiv0; reg mmcm_hi0_ns, mmcm_hi0_r; always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; reg poc_sample_pd_ns, poc_sample_pd_r; always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; assign poc_sample_pd = poc_sample_pd_r; //*************************************************************************** // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk // to the appropriate edge of fabric clock //*************************************************************************** //synthesis translate_off generate if ( tCK <= 2500 ) begin : check_ocal_timing localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; time rising_mmcm_ps_clk; always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); time pdiff; // Not used, except in waveform plots. always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; end endgenerate //synthesis translate_on //*************************************************************************** // RESET SYNCHRONIZATION DESCRIPTION: // Various resets are generated to ensure that: // 1. All resets are synchronously deasserted with respect to the clock // domain they are interfacing to. There are several different clock // domains - each one will receive a synchronized reset. // 2. The reset deassertion order starts with deassertion of SYS_RST, // followed by deassertion of resets for various parts of the design // (see "RESET ORDER" below) based on the lock status of PLLE2s. // RESET ORDER: // 1. User deasserts SYS_RST // 2. Reset PLLE2 and IDELAYCTRL // 3. Wait for PLLE2 and IDELAYCTRL to lock // 4. Release reset for all I/O primitives and internal logic // OTHER NOTES: // 1. Asynchronously assert reset. This way we can assert reset even if // there is no clock (needed for things like 3-stating output buffers // to prevent initial bus contention). Reset deassertion is synchronous. //*************************************************************************** //***************************************************************** // CLKDIV logic reset //***************************************************************** // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset // current O,25.0 unisim phaser_ref never locks. Need to find out why . generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | ~ref_dll_lock | ~MMCM_Locked_i; end else begin: rst_tmp_200 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | ~ref_dll_lock | ~MMCM_Locked_i; end endgenerate always @(posedge clk_bufg or posedge rst_tmp) begin if (rst_tmp) begin rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv0_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rstdiv0 = rstdiv0_sync_r1 ; //IDDR rest always @(posedge mmcm_ps_clk or posedge rst_tmp) begin if (rst_tmp) begin rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rst_sync_r1 <= #TCQ 1'b1 ; end else begin rst_sync_r <= #TCQ rst_sync_r << 1; rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; end end assign iddr_rst = rst_sync_r1 ; // Sync reset in the clk_div2 domain always @(posedge clk_div2 or posedge rst_tmp) begin if (rst_tmp) begin rstdiv2_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv2_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv2_sync_r <= #TCQ rstdiv2_sync_r << 1; rstdiv2_sync_r1 <= #TCQ rstdiv2_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rst_div2 = rstdiv2_sync_r1 ; generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; end else begin: rst_tmp_phaser_ref_200 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; end endgenerate always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) if (rst_tmp_phaser_ref) rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; else rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: iodelay_ctrl.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // This module instantiates the IDELAYCTRL primitive, which continously // calibrates the IODELAY elements in the region to account for varying // environmental conditions. A 200MHz or 300MHz reference clock (depending // on the desired IODELAY tap resolution) must be supplied //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_iodelay_ctrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter IODELAY_GRP0 = "IODELAY_MIG0", // May be assigned unique name when // multiple IP cores used in design parameter IODELAY_GRP1 = "IODELAY_MIG1", // May be assigned unique name when // multiple IP cores used in design parameter REFCLK_TYPE = "DIFFERENTIAL", // Reference clock type // "DIFFERENTIAL","SINGLE_ENDED" // NO_BUFFER, USE_SYSTEM_CLOCK parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER parameter SYS_RST_PORT = "FALSE", // "TRUE" - if pin is selected for sys_rst // and IBUF will be instantiated. // "FALSE" - if pin is not selected for sys_rst parameter RST_ACT_LOW = 1, // Reset input polarity // (0 = active high, 1 = active low) parameter DIFF_TERM_REFCLK = "TRUE", // Differential Termination parameter FPGA_SPEED_GRADE = 1, // FPGA speed grade parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" ) ( input clk_ref_p, input clk_ref_n, input clk_ref_i, input sys_rst, output [1:0] clk_ref, output sys_rst_o, output [1:0] iodelay_ctrl_rdy ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # localparam RST_SYNC_NUM = 15; // localparam RST_SYNC_NUM = 25; wire clk_ref_ibufg; wire clk_ref_mmcm_300; wire clk_ref_mmcm_400; wire mmcm_clkfbout; wire mmcm_Locked; wire [1:0] rst_ref; reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; wire rst_tmp_idelay; wire sys_rst_act_hi; //*************************************************************************** // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. // If the pin is not selected in GUI, sys_rst signal is expected to be // driven internally. generate if (SYS_RST_PORT == "TRUE") IBUF u_sys_rst_ibuf ( .I (sys_rst), .O (sys_rst_o) ); else assign sys_rst_o = sys_rst; endgenerate // Possible inversion of system reset as appropriate assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o; //*************************************************************************** // 1) Input buffer for IDELAYCTRL reference clock - handle either a // differential or single-ended input. Global clock buffer is used to // drive the rest of FPGA logic. // 2) For NO_BUFFER option, Reference clock will be driven from internal // clock i.e., clock is driven from fabric. Input buffers and Global // clock buffers will not be instaitaed. // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used // as the input reference clock. Global clock buffer is used to drive // the rest of FPGA logic. //*************************************************************************** generate if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref IBUFGDS # ( .DIFF_TERM (DIFF_TERM_REFCLK), .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_p), .IB (clk_ref_n), .O (clk_ref_ibufg) ); end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref IBUFG # ( .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_i), .O (clk_ref_ibufg) ); end else if ((REFCLK_TYPE == "NO_BUFFER") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf assign clk_ref_ibufg = clk_ref_i; end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf assign clk_ref_ibufg = clk_ref_i; end endgenerate // reference clock 300MHz and 400MHz generation with MMCM generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), .CLKFBOUT_MULT_F (6), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (4), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (3), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (5), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (mmcm_clkfbout), .CLKFBOUTB (), .CLKOUT0 (clk_ref_mmcm_300), .CLKOUT0B (), .CLKOUT1 (clk_ref_mmcm_400), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (mmcm_clkfbout), .CLKIN1 (clk_ref_ibufg), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (mmcm_Locked), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (sys_rst_act_hi)); end endgenerate generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 BUFG u_bufg_clk_ref_300 ( .O (clk_ref[1]), .I (clk_ref_mmcm_300) ); end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 BUFG u_bufg_clk_ref_400 ( .O (clk_ref[1]), .I (clk_ref_mmcm_400) ); end end endgenerate generate if ((REFCLK_TYPE == "DIFFERENTIAL") || (REFCLK_TYPE == "SINGLE_ENDED") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 BUFG u_bufg_clk_ref ( .O (clk_ref[0]), .I (clk_ref_ibufg) ); end else begin: clk_ref_200_no_buffer assign clk_ref[0] = clk_ref_i; end endgenerate //***************************************************************** // IDELAYCTRL reset // This assumes an external clock signal driving the IDELAYCTRL // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL // lock signal will need to be incorporated in this. //***************************************************************** // Add PLL lock if PLL drives IDELAYCTRL in user design assign rst_tmp_idelay = sys_rst_act_hi; generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 always @(posedge clk_ref[1] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; end endgenerate always @(posedge clk_ref[0] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; //***************************************************************** generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 ( .RDY (iodelay_ctrl_rdy[1]), .REFCLK (clk_ref[1]), .RST (rst_ref[1]) ); end endgenerate (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 ( .RDY (iodelay_ctrl_rdy[0]), .REFCLK (clk_ref[0]), .RST (rst_ref[0]) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v4_0_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Jul 25 2012 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_tempmon # ( parameter TCQ = 100, // Register delay (sim only) parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) parameter tTEMPSAMPLE = 10000000 // ps (10 us) ) ( input clk, // Fabric clock input xadc_clk, input rst, // System reset input [11:0] device_temp_i, // User device temperature output [11:0] device_temp // Sampled temperature ); //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 // Synchronization registers (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; // Output register (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; wire [11:0] device_temp_lcl; reg [3:0] sync_cntr = 4'b0000; reg device_temp_sync_r4_neq_r3; // (* ASYNC_REG = "TRUE" *) reg rst_r1; // (* ASYNC_REG = "TRUE" *) reg rst_r2; // // Synchronization rst to XADC clock domain // always @(posedge xadc_clk) begin // rst_r1 <= rst; // rst_r2 <= rst_r1; // end // Synchronization counter always @(posedge clk) begin device_temp_sync_r1 <= #TCQ device_temp_lcl; device_temp_sync_r2 <= #TCQ device_temp_sync_r1; device_temp_sync_r3 <= #TCQ device_temp_sync_r2; device_temp_sync_r4 <= #TCQ device_temp_sync_r3; device_temp_sync_r5 <= #TCQ device_temp_sync_r4; device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; end always @(posedge clk) if(rst || (device_temp_sync_r4_neq_r3)) sync_cntr <= #TCQ 4'b0000; else if(~&sync_cntr) sync_cntr <= #TCQ sync_cntr + 4'b0001; always @(posedge clk) if(&sync_cntr) device_temp_r <= #TCQ device_temp_sync_r5; assign device_temp = device_temp_r; generate if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature assign device_temp_lcl = device_temp_i; end else begin : xadc_supplied_temperature // calculate polling timer width and limit localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); localparam nTEMPSAMP_CLKS = nTEMPSAMP; localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); // Temperature sampler FSM encoding localparam INIT_IDLE = 2'b00; localparam REQUEST_READ_TEMP = 2'b01; localparam WAIT_FOR_READ = 2'b10; localparam READ = 2'b11; // polling timer and tick reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; reg sample_timer_en = 1'b0; reg sample_timer_clr = 1'b0; reg sample_en = 1'b0; // Temperature sampler state reg [2:0] tempmon_state = INIT_IDLE; reg [2:0] tempmon_next_state = INIT_IDLE; // XADC interfacing reg xadc_den = 1'b0; wire xadc_drdy; wire [15:0] xadc_do; reg xadc_drdy_r = 1'b0; reg [15:0] xadc_do_r = 1'b0; // Temperature storage reg [11:0] temperature = 12'b0; // Reset sync (* ASYNC_REG = "TRUE" *) reg rst_r1; (* ASYNC_REG = "TRUE" *) reg rst_r2; // Synchronization rst to XADC clock domain always @(posedge xadc_clk) begin rst_r1 <= rst; rst_r2 <= rst_r1; end // XADC polling interval timer always @ (posedge xadc_clk) if(rst_r2 || sample_timer_clr) sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; else if(sample_timer_en) sample_timer <= #TCQ sample_timer + 1'b1; // XADC sampler state transition always @(posedge xadc_clk) if(rst_r2) tempmon_state <= #TCQ INIT_IDLE; else tempmon_state <= #TCQ tempmon_next_state; // Sample enable always @(posedge xadc_clk) sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; // XADC sampler next state transition always @(tempmon_state or sample_en or xadc_drdy_r) begin tempmon_next_state = tempmon_state; case(tempmon_state) INIT_IDLE: if(sample_en) tempmon_next_state = REQUEST_READ_TEMP; REQUEST_READ_TEMP: tempmon_next_state = WAIT_FOR_READ; WAIT_FOR_READ: if(xadc_drdy_r) tempmon_next_state = READ; READ: tempmon_next_state = INIT_IDLE; default: tempmon_next_state = INIT_IDLE; endcase end // Sample timer clear always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) sample_timer_clr <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) sample_timer_clr <= #TCQ 1'b1; // Sample timer enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) sample_timer_en <= #TCQ 1'b0; else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) sample_timer_en <= #TCQ 1'b1; // XADC enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) xadc_den <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) xadc_den <= #TCQ 1'b1; // Register XADC outputs always @(posedge xadc_clk) if(rst_r2) begin xadc_drdy_r <= #TCQ 1'b0; xadc_do_r <= #TCQ 16'b0; end else begin xadc_drdy_r <= #TCQ xadc_drdy; xadc_do_r <= #TCQ xadc_do; end // Store current read value always @(posedge xadc_clk) if(rst_r2) temperature <= #TCQ 12'b0; else if(tempmon_state == READ) temperature <= #TCQ xadc_do_r[15:4]; assign device_temp_lcl = temperature; // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter // 7 Series // Xilinx HDL Libraries Guide, version 14.1 XADC #( // INIT_40 - INIT_42: XADC configuration registers .INIT_40(16'h1000), // config reg 0 .INIT_41(16'h2fff), // config reg 1 .INIT_42(16'h0800), // config reg 2 // INIT_48 - INIT_4F: Sequence Registers .INIT_48(16'h0101), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0100), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers .INIT_50(16'hb5ed), // Temp alarm trigger .INIT_51(16'h57e4), // Vccint upper alarm limit .INIT_52(16'ha147), // Vccaux upper alarm limit .INIT_53(16'hca33), // Temp alarm OT upper .INIT_54(16'ha93a), // Temp alarm reset .INIT_55(16'h52c6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hae4e), // Temp alarm OT reset .INIT_58(16'h5999), // VBRAM upper alarm limit .INIT_5C(16'h5111), // VBRAM lower alarm limit // Simulation attributes: Set for proepr simulation behavior .SIM_DEVICE("7SERIES") // Select target device (values) ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(), // 1-bit output: Over-Temperature alarm // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports .DO(xadc_do), // 16-bit output: DRP output data bus .DRDY(xadc_drdy), // 1-bit output: DRP data ready // STATUS: 1-bit (each) output: XADC status ports .BUSY(), // 1-bit output: ADC busy output .CHANNEL(), // 5-bit output: Channel selection outputs .EOC(), // 1-bit output: End of Conversion .EOS(), // 1-bit output: End of Sequence .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred .MUXADDR(), // 5-bit output: External MUX channel decode // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs .CONVST(1'b0), // 1-bit input: Convert start input .CONVSTCLK(1'b0), // 1-bit input: Convert start input .RESET(1'b0), // 1-bit input: Active-high reset // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN .VN(1'b0), // 1-bit input: N-side analog input .VP(1'b0), // 1-bit input: P-side analog input // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports .DADDR(7'b0), // 7-bit input: DRP address bus .DCLK(xadc_clk), // 1-bit input: DRP clock .DEN(xadc_den), // 1-bit input: DRP enable signal .DI(16'b0), // 16-bit input: DRP input data bus .DWE(1'b0) // 1-bit input: DRP write enable ); // End of XADC_inst instantiation end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. 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Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_mux.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_arb_mux # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_VECT_INDX = 11, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_VECT_INDX = 31, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs parameter nCS_PER_RANK = 1, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nSLOTS = 2, parameter nWR = 6, // Write recovery (CKs) parameter RANKS = 1, parameter RANK_VECT_INDX = 15, parameter RANK_WIDTH = 2, parameter ROW_VECT_INDX = 63, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010 ) (/*AUTOARG*/ // Outputs output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v output col_periodic_rd, // From arb_select0 of arb_select.v output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v output col_rmw, // From arb_select0 of arb_select.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v output col_size, // From arb_select0 of arb_select.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_pre, output sent_col, // From arb_row_col0 of arb_row_col.v output sent_col_r, // From arb_row_col0 of arb_row_col.v output sent_row, // From arb_row_col0 of arb_row_col.v output [nBANK_MACHS-1:0] sending_col, output rnk_config_strobe, output insert_maint_r1, output rnk_config_kill_rts_col, // Inputs input clk, input rst, input init_calib_complete, input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v input insert_maint_r, // To arb_row_col0 of arb_row_col.v input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v input maint_zq_r, // To arb_select0 of arb_select.v input maint_sre_r, // To arb_select0 of arb_select.v input maint_srx_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v input [7:0] slot_0_present, // To arb_select0 of arb_select.v input [7:0] slot_1_present // To arb_select0 of arb_select.v ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire cs_en0; // From arb_row_col0 of arb_row_col.v wire cs_en1; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v wire send_cmd1_col; wire send_cmd2_row; wire send_cmd2_col; wire send_cmd2_pre; wire send_cmd3_col; wire [5:0] col_channel_offset; // End of automatics wire sent_col_i; wire cs_en2; wire cs_en3; assign sent_col = sent_col_i; mig_7series_v4_0_arb_row_col # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .CWL (CWL), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nRAS (nRAS), .nRCD (nRCD), .nWR (nWR)) arb_row_col0 (/*AUTOINST*/ // Outputs .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), .sent_row (sent_row), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col_i), .sent_col_r (sent_col_r), .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), .send_cmd0_row (send_cmd0_row), .send_cmd0_col (send_cmd0_col), .send_cmd1_row (send_cmd1_row), .send_cmd1_col (send_cmd1_col), .send_cmd2_row (send_cmd2_row), .send_cmd2_col (send_cmd2_col), .send_cmd2_pre (send_cmd2_pre), .send_cmd3_col (send_cmd3_col), .col_channel_offset (col_channel_offset), .cs_en0 (cs_en0), .cs_en1 (cs_en1), .cs_en2 (cs_en2), .cs_en3 (cs_en3), .insert_maint_r1 (insert_maint_r1), // Inputs .clk (clk), .rst (rst), .rts_row (rts_row[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .rts_col (rts_col[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0])); mig_7series_v4_0_arb_select # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .CKE_ODT_AUX (CKE_ODT_AUX), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nSLOTS (nSLOTS), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_select0 (/*AUTOINST*/ // Outputs .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_size (col_size), .col_row (col_row[ROW_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .mc_cas_slot (mc_cas_slot), .col_channel_offset (col_channel_offset), .rnk_config (rnk_config), // Inputs .clk (clk), .rst (rst), .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .insert_maint_r1 (insert_maint_r1), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .col_addr (col_addr[ROW_VECT_INDX:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), .send_cmd0_row (send_cmd0_row), .send_cmd0_col (send_cmd0_col), .send_cmd1_row (send_cmd1_row), .send_cmd1_col (send_cmd1_col), .send_cmd2_row (send_cmd2_row), .send_cmd2_col (send_cmd2_col), .send_cmd2_pre (send_cmd2_pre), .send_cmd3_col (send_cmd3_col), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col), .cs_en0 (cs_en0), .cs_en1 (cs_en1), .cs_en2 (cs_en2), .cs_en3 (cs_en3), .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_row_col.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // This block receives request to send row and column commands. These requests // come the individual bank machines. The arbitration winner is selected // and driven back to the bank machines. // // The CS enables are generated. For 2:1 mode, row commands are sent // in the "0" phase, and column commands are sent in the "1" phase. // // In 2T mode, a further arbitration is performed between the row // and column commands. The winner of this arbitration inhibits // arbitration by the loser. The winner is allowed to arbitrate, the loser is // blocked until the next state. The winning address command // is repeated on both the "0" and the "1" phases and the CS // is asserted for just the "1" phase. `timescale 1 ps / 1 ps module mig_7series_v4_0_arb_row_col # ( parameter TCQ = 100, parameter ADDR_CMD_MODE = "1T", parameter CWL = 5, parameter EARLY_WR_DATA_ADDR = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nWR = 6 // Write recovery (CKs) ) (/*AUTOARG*/ // Outputs grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r, rnk_config_strobe, rnk_config_valid_r, grant_col_r, sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col, send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre, send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3, insert_maint_r1, rnk_config_kill_rts_col, // Inputs clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr ); // Create a delay when switching ranks localparam RNK2RNK_DLY = 12; localparam RNK2RNK_DLY_CLKS = (RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0); input clk; input rst; input [nBANK_MACHS-1:0] rts_row; input insert_maint_r; input [nBANK_MACHS-1:0] rts_col; reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r; wire block_grant_row; wire block_grant_col; wire rnk_config_kill_rts_col_lcl = RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0; output rnk_config_kill_rts_col; assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl; wire [nBANK_MACHS-1:0] col_request; wire granted_col_ns = |col_request; wire [nBANK_MACHS-1:0] row_request = rts_row & {nBANK_MACHS{~insert_maint_r}}; wire granted_row_ns = |row_request; generate if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb assign col_request = rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}}; // Give column command priority whenever previous state has no row request. wire [1:0] row_col_grant; wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant; wire upd_last_master = ~granted_row_ns || |row_col_grant; mig_7series_v4_0_round_robin_arb # (.WIDTH (2)) row_col_arb0 (.grant_ns (), .grant_r (row_col_grant), .upd_last_master (upd_last_master), .current_master (current_master), .clk (clk), .rst (rst), .req ({granted_row_ns, granted_col_ns}), .disable_grant (1'b0)); assign {block_grant_col, block_grant_row} = row_col_grant; end else begin : row_col_1T_arb assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}}; assign block_grant_row = 1'b0; assign block_grant_col = 1'b0; end endgenerate // Row address/command arbitration. wire[nBANK_MACHS-1:0] grant_row_r_lcl; output wire[nBANK_MACHS-1:0] grant_row_r; assign grant_row_r = grant_row_r_lcl; reg granted_row_r; always @(posedge clk) granted_row_r <= #TCQ granted_row_ns; wire sent_row_lcl = granted_row_r && ~block_grant_row; output wire sent_row; assign sent_row = sent_row_lcl; mig_7series_v4_0_round_robin_arb # (.WIDTH (nBANK_MACHS)) row_arb0 (.grant_ns (), .grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_row_lcl), .current_master (grant_row_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (row_request), .disable_grant (1'b0)); output wire [nBANK_MACHS-1:0] sending_row; assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}}; // Precharge arbitration for 4:1 mode input [nBANK_MACHS-1:0] rts_pre; output wire[nBANK_MACHS-1:0] grant_pre_r; output wire [nBANK_MACHS-1:0] sending_pre; wire sent_pre_lcl; generate if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb reg granted_pre_r; wire[nBANK_MACHS-1:0] grant_pre_r_lcl; wire granted_pre_ns = |rts_pre; assign grant_pre_r = grant_pre_r_lcl; always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns; assign sent_pre_lcl = granted_pre_r; assign sending_pre = grant_pre_r_lcl; mig_7series_v4_0_round_robin_arb # (.WIDTH (nBANK_MACHS)) pre_arb0 (.grant_ns (), .grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_pre_lcl), .current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rts_pre), .disable_grant (1'b0)); end endgenerate `ifdef MC_SVA all_bank_machines_row_arb: cover property (@(posedge clk) (~rst && &rts_row)); `endif // Rank config arbitration. input [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] grant_config_r_lcl; output wire [nBANK_MACHS-1:0] grant_config_r; assign grant_config_r = grant_config_r_lcl; wire upd_rnk_config_last_master; mig_7series_v4_0_round_robin_arb # (.WIDTH (nBANK_MACHS)) config_arb0 (.grant_ns (), .grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (upd_rnk_config_last_master), .current_master (grant_config_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rtc[nBANK_MACHS-1:0]), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc)); `endif wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns; always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns; genvar i; generate for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1) always @(posedge clk) rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1]; endgenerate output wire rnk_config_strobe; assign rnk_config_strobe = rnk_config_strobe_r[0]; assign upd_rnk_config_last_master = rnk_config_strobe_r[0]; // Generate rnk_config_valid. reg rnk_config_valid_r_lcl; wire rnk_config_valid_ns; assign rnk_config_valid_ns = ~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns); always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns; output wire rnk_config_valid_r; assign rnk_config_valid_r = rnk_config_valid_r_lcl; // Column address/command arbitration. wire [nBANK_MACHS-1:0] grant_col_r_lcl; output wire [nBANK_MACHS-1:0] grant_col_r; assign grant_col_r = grant_col_r_lcl; reg granted_col_r; always @(posedge clk) granted_col_r <= #TCQ granted_col_ns; wire sent_col_lcl; mig_7series_v4_0_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (), .grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_request), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_col_arb: cover property (@(posedge clk) (~rst && &rts_col)); `endif output wire [nBANK_MACHS-1:0] sending_col; assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}}; assign sent_col_lcl = granted_col_r && ~block_grant_col; reg sent_col_lcl_r = 1'b0; always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl; output wire sent_col; assign sent_col = sent_col_lcl; output wire sent_col_r; assign sent_col_r = sent_col_lcl_r; // If we need early wr_data_addr because ECC is on, arbitrate // to see which bank machine might sent the next wr_data_addr; input [nBANK_MACHS-1:0] col_rdy_wr; output wire [nBANK_MACHS-1:0] grant_col_wr; generate if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off assign grant_col_wr = {nBANK_MACHS{1'b0}}; end else begin : early_wr_addr_arb_on wire [nBANK_MACHS-1:0] grant_col_wr_raw; mig_7series_v4_0_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (grant_col_wr_raw), .grant_r (), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_rdy_wr), .disable_grant (1'b0)); reg [nBANK_MACHS-1:0] grant_col_wr_r; wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns ? grant_col_wr_raw : grant_col_wr_r; always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns; assign grant_col_wr = grant_col_wr_ns; end // block: early_wr_addr_arb_on endgenerate output reg send_cmd0_row = 1'b0; output reg send_cmd0_col = 1'b0; output reg send_cmd1_row = 1'b0; output reg send_cmd1_col = 1'b0; output reg send_cmd2_row = 1'b0; output reg send_cmd2_col = 1'b0; output reg send_cmd2_pre = 1'b0; output reg send_cmd3_col = 1'b0; output reg cs_en0 = 1'b0; output reg cs_en1 = 1'b0; output reg cs_en2 = 1'b0; output reg cs_en3 = 1'b0; output wire [5:0] col_channel_offset; reg insert_maint_r1_lcl; always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r; output wire insert_maint_r1; assign insert_maint_r1 = insert_maint_r1_lcl; wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl; reg sent_row_or_maint_r = 1'b0; always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint; generate case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")}) 3'b000 : begin : one_one_not2T end 3'b001 : begin : one_one_2T end 3'b010 : begin : two_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b011 : begin : two_one_2T if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL always @(sent_row_or_maint_r or sent_col_lcl_r) cs_en0 = sent_row_or_maint_r || sent_col_lcl_r; always @(sent_row_or_maint or sent_row_or_maint_r) begin send_cmd0_row = sent_row_or_maint_r; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl or sent_col_lcl_r) begin send_cmd0_col = sent_col_lcl_r; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 0; end else begin // Place column commands on slot 0->1 for odd CWL always @(sent_col_lcl or sent_row_or_maint) cs_en1 = sent_row_or_maint || sent_col_lcl; always @(sent_row_or_maint) begin send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin send_cmd0_col = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b100 : begin : four_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end always @(sent_pre_lcl) begin cs_en2 = sent_pre_lcl; send_cmd2_pre = sent_pre_lcl; end end 3'b101 : begin : four_one_2T if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL always @(sent_col_lcl or sent_col_lcl_r) begin cs_en0 = sent_col_lcl_r; send_cmd0_col = sent_col_lcl_r; send_cmd3_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en2 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; send_cmd2_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 2->3 for odd CWL always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en3 = sent_col_lcl; send_cmd2_col = sent_col_lcl; send_cmd3_col = sent_col_lcl; end assign col_channel_offset = 3; end end endcase endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_select.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_select.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Based on granta_r and grantc_r, this module selects a // row and column command from the request information // provided by the bank machines. // // Depending on address mode configuration, nCL and nCWL, a column // command pipeline of up to three states will be created. `timescale 1 ps / 1 ps module mig_7series_v4_0_arb_select # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_VECT_INDX = 11, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_VECT_INDX = 31, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nCS_PER_RANK = 1, parameter CKE_ODT_AUX = "FALSE", parameter nSLOTS = 2, parameter RANKS = 1, parameter RANK_VECT_INDX = 15, parameter RANK_WIDTH = 2, parameter ROW_VECT_INDX = 63, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010 ) ( // Outputs output wire col_periodic_rd, output wire [RANK_WIDTH-1:0] col_ra, output wire [BANK_WIDTH-1:0] col_ba, output wire [ROW_WIDTH-1:0] col_a, output wire col_rmw, output wire col_rd_wr, output wire col_size, output wire [ROW_WIDTH-1:0] col_row, output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr, output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr, output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output wire [5:0] mc_data_offset, output wire [5:0] mc_data_offset_1, output wire [5:0] mc_data_offset_2, output wire [1:0] mc_cas_slot, output wire [RANK_WIDTH-1:0] rnk_config, // Inputs input clk, input rst, input init_calib_complete, input [RANK_VECT_INDX:0] req_rank_r, input [BANK_VECT_INDX:0] req_bank_r, input [nBANK_MACHS-1:0] req_ras, input [nBANK_MACHS-1:0] req_cas, input [nBANK_MACHS-1:0] req_wr_r, input [nBANK_MACHS-1:0] grant_row_r, input [nBANK_MACHS-1:0] grant_pre_r, input [ROW_VECT_INDX:0] row_addr, input [nBANK_MACHS-1:0] row_cmd_wr, input insert_maint_r1, input maint_zq_r, input maint_sre_r, input maint_srx_r, input [RANK_WIDTH-1:0] maint_rank_r, input [nBANK_MACHS-1:0] req_periodic_rd_r, input [nBANK_MACHS-1:0] req_size_r, input [nBANK_MACHS-1:0] rd_wr_r, input [ROW_VECT_INDX:0] req_row_r, input [ROW_VECT_INDX:0] col_addr, input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r, input [nBANK_MACHS-1:0] grant_col_r, input [nBANK_MACHS-1:0] grant_col_wr, input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input [5:0] col_channel_offset, input [nBANK_MACHS-1:0] grant_config_r, input rnk_config_strobe, input [7:0] slot_0_present, input [7:0] slot_1_present, input send_cmd0_row, input send_cmd0_col, input send_cmd1_row, input send_cmd1_col, input send_cmd2_row, input send_cmd2_col, input send_cmd2_pre, input send_cmd3_col, input sent_col, input cs_en0, input cs_en1, input cs_en2, input cs_en3 ); localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1; reg col_rd_wr_ns; reg col_rd_wr_r = 1'b0; reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}}; reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}}; // calib_rd_data_offset for currently targeted rank reg [5:0] rank_rddata_offset_0; reg [5:0] rank_rddata_offset_1; reg [5:0] rank_rddata_offset_2; // Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1] assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1; assign mc_aux_out0[2] = 1'b0; reg cke_r; reg cke_ns; generate if(CKE_ODT_AUX == "FALSE")begin always @(posedge clk) begin if (rst) cke_r = 1'b1; else cke_r = cke_ns; end always @(*) begin cke_ns = 1'b1; if (maint_sre_r & insert_maint_r1) cke_ns = 1'b0; else if (cke_r==1'b0) begin if (maint_srx_r & insert_maint_r1) cke_ns = 1'b1; else cke_ns = 1'b0; end end end endgenerate // Disable ODT & CKE toggle enable high bits assign mc_aux_out1 = 4'b0; // implement PHY command word assign mc_cmd[0] = sent_col; assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ? sent_col && col_rd_wr_r : sent_col && col_rd_wr_ns; assign mc_cmd[2] = ~sent_col; // generate calib_rd_data_offset for current rank - only use rank 0 values for now always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin rank_rddata_offset_0 = calib_rddata_offset[5:0]; rank_rddata_offset_1 = calib_rddata_offset_1[5:0]; rank_rddata_offset_2 = calib_rddata_offset_2[5:0]; end // generate data offset generate if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t assign mc_data_offset = ~sent_col ? 6'b0 : col_rd_wr_r ? rank_rddata_offset_0 + col_channel_offset : nCK_PER_CLK == 2 ? CWL - 2 + col_channel_offset : // nCK_PER_CLK == 4 CWL + 2 + col_channel_offset; assign mc_data_offset_1 = ~sent_col ? 6'b0 : col_rd_wr_r ? rank_rddata_offset_1 + col_channel_offset : nCK_PER_CLK == 2 ? CWL - 2 + col_channel_offset : // nCK_PER_CLK == 4 CWL + 2 + col_channel_offset; assign mc_data_offset_2 = ~sent_col ? 6'b0 : col_rd_wr_r ? rank_rddata_offset_2 + col_channel_offset : nCK_PER_CLK == 2 ? CWL - 2 + col_channel_offset : // nCK_PER_CLK == 4 CWL + 2 + col_channel_offset; end else begin : gen_mc_data_offset_not_even_cwl_2t assign mc_data_offset = ~sent_col ? 6'b0 : col_rd_wr_ns ? rank_rddata_offset_0 + col_channel_offset : nCK_PER_CLK == 2 ? CWL - 2 + col_channel_offset : // nCK_PER_CLK == 4 CWL + 2 + col_channel_offset; assign mc_data_offset_1 = ~sent_col ? 6'b0 : col_rd_wr_ns ? rank_rddata_offset_1 + col_channel_offset : nCK_PER_CLK == 2 ? CWL - 2 + col_channel_offset : // nCK_PER_CLK == 4 CWL + 2 + col_channel_offset; assign mc_data_offset_2 = ~sent_col ? 6'b0 : col_rd_wr_ns ? rank_rddata_offset_2 + col_channel_offset : nCK_PER_CLK == 2 ? CWL - 2 + col_channel_offset : // nCK_PER_CLK == 4 CWL + 2 + col_channel_offset; end endgenerate assign mc_cas_slot = col_channel_offset[1:0]; // Based on arbitration results, select the row and column commands. integer i; reg [OUT_CMD_WIDTH-1:0] row_cmd_ns; generate begin : row_mux wire [OUT_CMD_WIDTH-1:0] maint_cmd = {maint_rank_r, // maintenance rank row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)], // bank plus upper address bits 1'b0, // A10 = 0 for ZQCS row_cmd_r[3+:10], // address bits [9:0] // ZQ, SRX or SRE/REFRESH (maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001) }; always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd or req_bank_r or req_cas or req_rank_r or req_ras or row_addr or row_cmd_r or row_cmd_wr or rst) begin row_cmd_ns = rst ? {RANK_WIDTH{1'b0}} : insert_maint_r1 ? maint_cmd : row_cmd_r; for (i=0; i 1) begin : slot_1_configured wire slot_1_select = (slot_1_present[3] & slot_1_present[1])? |({col_ra_one_hot[slot_0_population+1], col_ra_one_hot[slot_0_population]}) : (slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0; wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ? slot_1_select && col_rd_wr_r : slot_1_select && col_rd_wr_ns; wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ? slot_1_select && ~col_rd_wr_r : slot_1_select && ~col_rd_wr_ns; // ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3) wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write; assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds end // if (nSLOTS > 1) else begin // Disable slot 1 ODT when not present assign mc_aux_out0[3] = 1'b0; end // else: !if(nSLOTS > 1) endgenerate generate if(CKE_ODT_AUX == "FALSE")begin reg[1:0] mc_aux_out_r ; reg[1:0] mc_aux_out_r_1 ; reg[1:0] mc_aux_out_r_2 ; always@(posedge clk) begin mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ; mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ; mc_aux_out_r_1 <= #TCQ mc_aux_out_r ; mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ; end if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0]; assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1]; end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1 assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ; assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ; end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1 assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ; assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ; end end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_cntrl.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Structural block instantiating the three sub blocks that make up // a bank machine. `timescale 1ps/1ps module mig_7series_v4_0_bank_cntrl # ( parameter TCQ = 100, parameter ADDR_CMD_MODE = "1T", parameter BANK_WIDTH = 3, parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter ECC = "OFF", parameter ID = 4, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nOP_WAIT = 0, parameter nRAS_CLKS = 10, parameter nRCD = 5, parameter nRTP = 4, parameter nRP = 10, parameter nWTP_CLKS = 5, parameter ORDERING = "NORM", parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter RAS_TIMER_WIDTH = 5, parameter ROW_WIDTH = 16, parameter STARVE_LIMIT = 2 ) (/*AUTOARG*/ // Outputs wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc, row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras, req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r, rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r, ordered_issued, op_exit_req, end_rtp, demand_priority, demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns, req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r, rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r, // Inputs was_wr, was_priority, use_addr, start_rcd_in, size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row, req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in, rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r, periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in, order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r, maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr, rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority, dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in, data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q, accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full, phy_mc_cmd_full, phy_mc_data_full ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input accept_internal_r; // To bank_queue0 of bank_queue.v input accept_req; // To bank_queue0 of bank_queue.v input adv_order_q; // To bank_queue0 of bank_queue.v input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v input clk; // To bank_compare0 of bank_compare.v, ... input [2:0] cmd; // To bank_compare0 of bank_compare.v input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v input phy_rddata_valid; // To bank_state0 of bank_state.v input dq_busy_data; // To bank_state0 of bank_state.v input hi_priority; // To bank_compare0 of bank_compare.v input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v input rnk_config_strobe; // To bank_state0 of bank_state.v input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v input rnk_config_valid_r; // To bank_state0 of bank_state.v input low_idle_cnt_r; // To bank_state0 of bank_state.v input maint_idle; // To bank_queue0 of bank_queue.v input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v input maint_req_r; // To bank_queue0 of bank_queue.v input maint_zq_r; // To bank_compare0 of bank_compare.v input maint_sre_r; // To bank_compare0 of bank_compare.v input op_exit_grant; // To bank_state0 of bank_state.v input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v input periodic_rd_insert; // To bank_compare0 of bank_compare.v input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v input phy_mc_ctl_full; input phy_mc_cmd_full; input phy_mc_data_full; input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v input rd_rmw; // To bank_state0 of bank_state.v input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v input rst; // To bank_state0 of bank_state.v, ... input sending_col; // To bank_compare0 of bank_compare.v, ... input sending_row; // To bank_state0 of bank_state.v input sending_pre; input sent_col; // To bank_state0 of bank_state.v input sent_row; // To bank_state0 of bank_state.v input size; // To bank_compare0 of bank_compare.v input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v input use_addr; // To bank_queue0 of bank_queue.v input was_priority; // To bank_queue0 of bank_queue.v input was_wr; // To bank_queue0 of bank_queue.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v output col_rdy_wr; // From bank_state0 of bank_state.v output demand_act_priority; // From bank_state0 of bank_state.v output demand_priority; // From bank_state0 of bank_state.v output end_rtp; // From bank_state0 of bank_state.v output op_exit_req; // From bank_state0 of bank_state.v output ordered_issued; // From bank_queue0 of bank_queue.v output ordered_r; // From bank_queue0 of bank_queue.v output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v output req_cas; // From bank_compare0 of bank_compare.v output req_periodic_rd_r; // From bank_compare0 of bank_compare.v output req_ras; // From bank_compare0 of bank_compare.v output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v output req_size_r; // From bank_compare0 of bank_compare.v output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v output row_cmd_wr; // From bank_compare0 of bank_compare.v output rtc; // From bank_state0 of bank_state.v output rts_col; // From bank_state0 of bank_state.v output rts_row; // From bank_state0 of bank_state.v output rts_pre; output start_pre_wait; // From bank_state0 of bank_state.v output start_rcd; // From bank_state0 of bank_state.v output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire act_wait_r; // From bank_state0 of bank_state.v wire allow_auto_pre; // From bank_state0 of bank_state.v wire auto_pre_r; // From bank_queue0 of bank_queue.v wire bank_wait_in_progress; // From bank_state0 of bank_state.v wire order_q_zero; // From bank_queue0 of bank_queue.v wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v wire pass_open_bank_r; // From bank_queue0 of bank_queue.v wire pre_wait_r; // From bank_state0 of bank_state.v wire precharge_bm_end; // From bank_state0 of bank_state.v wire q_has_priority; // From bank_queue0 of bank_queue.v wire q_has_rd; // From bank_queue0 of bank_queue.v wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v wire rcv_open_bank; // From bank_queue0 of bank_queue.v wire rd_half_rmw; // From bank_state0 of bank_state.v wire req_priority_r; // From bank_compare0 of bank_compare.v wire row_hit_r; // From bank_compare0 of bank_compare.v wire tail_r; // From bank_queue0 of bank_queue.v wire wait_for_maint_r; // From bank_queue0 of bank_queue.v // End of automatics output idle_ns; output req_wr_r; output rd_wr_r; output bm_end; output idle_r; output head_r; output [RANK_WIDTH-1:0] req_rank_r; output rb_hit_busy_r; output passing_open_bank; output maint_hit; output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; mig_7series_v4_0_bank_compare # (/*AUTOINSTPARAM*/ // Parameters .BANK_WIDTH (BANK_WIDTH), .TCQ (TCQ), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .ECC (ECC), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ROW_WIDTH (ROW_WIDTH)) bank_compare0 (/*AUTOINST*/ // Outputs .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]), .req_periodic_rd_r (req_periodic_rd_r), .req_size_r (req_size_r), .rd_wr_r (rd_wr_r), .req_rank_r (req_rank_r[RANK_WIDTH-1:0]), .req_bank_r (req_bank_r[BANK_WIDTH-1:0]), .req_row_r (req_row_r[ROW_WIDTH-1:0]), .req_wr_r (req_wr_r), .req_priority_r (req_priority_r), .rb_hit_busy_r (rb_hit_busy_r), .rb_hit_busy_ns (rb_hit_busy_ns), .row_hit_r (row_hit_r), .maint_hit (maint_hit), .col_addr (col_addr[ROW_WIDTH-1:0]), .req_ras (req_ras), .req_cas (req_cas), .row_cmd_wr (row_cmd_wr), .row_addr (row_addr[ROW_WIDTH-1:0]), .rank_busy_r (rank_busy_r[RANKS-1:0]), // Inputs .clk (clk), .idle_ns (idle_ns), .idle_r (idle_r), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .periodic_rd_insert (periodic_rd_insert), .size (size), .cmd (cmd[2:0]), .sending_col (sending_col), .rank (rank[RANK_WIDTH-1:0]), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .bank (bank[BANK_WIDTH-1:0]), .row (row[ROW_WIDTH-1:0]), .col (col[COL_WIDTH-1:0]), .hi_priority (hi_priority), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .auto_pre_r (auto_pre_r), .rd_half_rmw (rd_half_rmw), .act_wait_r (act_wait_r)); mig_7series_v4_0_bank_state # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .ECC (ECC), .ID (ID), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRAS_CLKS (nRAS_CLKS), .nRP (nRP), .nRTP (nRTP), .nRCD (nRCD), .nWTP_CLKS (nWTP_CLKS), .ORDERING (ORDERING), .RANKS (RANKS), .RANK_WIDTH (RANK_WIDTH), .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH), .STARVE_LIMIT (STARVE_LIMIT)) bank_state0 (/*AUTOINST*/ // Outputs .start_rcd (start_rcd), .act_wait_r (act_wait_r), .rd_half_rmw (rd_half_rmw), .ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]), .end_rtp (end_rtp), .bank_wait_in_progress (bank_wait_in_progress), .start_pre_wait (start_pre_wait), .op_exit_req (op_exit_req), .pre_wait_r (pre_wait_r), .allow_auto_pre (allow_auto_pre), .precharge_bm_end (precharge_bm_end), .demand_act_priority (demand_act_priority), .rts_row (rts_row), .rts_pre (rts_pre), .act_this_rank_r (act_this_rank_r[RANKS-1:0]), .demand_priority (demand_priority), .col_rdy_wr (col_rdy_wr), .rts_col (rts_col), .wr_this_rank_r (wr_this_rank_r[RANKS-1:0]), .rd_this_rank_r (rd_this_rank_r[RANKS-1:0]), // Inputs .clk (clk), .rst (rst), .bm_end (bm_end), .pass_open_bank_r (pass_open_bank_r), .sending_row (sending_row), .sending_pre (sending_pre), .rcv_open_bank (rcv_open_bank), .sending_col (sending_col), .rd_wr_r (rd_wr_r), .req_wr_r (req_wr_r), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .rd_rmw (rd_rmw), .ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]), .rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]), .idle_r (idle_r), .passing_open_bank (passing_open_bank), .low_idle_cnt_r (low_idle_cnt_r), .op_exit_grant (op_exit_grant), .tail_r (tail_r), .auto_pre_r (auto_pre_r), .pass_open_bank_ns (pass_open_bank_ns), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .rtc (rtc), .req_rank_r (req_rank_r[RANK_WIDTH-1:0]), .req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]), .start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .wait_for_maint_r (wait_for_maint_r), .head_r (head_r), .sent_row (sent_row), .demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]), .order_q_zero (order_q_zero), .sent_col (sent_col), .q_has_rd (q_has_rd), .q_has_priority (q_has_priority), .req_priority_r (req_priority_r), .idle_ns (idle_ns), .demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .dq_busy_data (dq_busy_data)); mig_7series_v4_0_bank_queue # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .BM_CNT_WIDTH (BM_CNT_WIDTH), .nBANK_MACHS (nBANK_MACHS), .ORDERING (ORDERING), .ID (ID)) bank_queue0 (/*AUTOINST*/ // Outputs .head_r (head_r), .tail_r (tail_r), .idle_ns (idle_ns), .idle_r (idle_r), .pass_open_bank_ns (pass_open_bank_ns), .pass_open_bank_r (pass_open_bank_r), .auto_pre_r (auto_pre_r), .bm_end (bm_end), .passing_open_bank (passing_open_bank), .ordered_issued (ordered_issued), .ordered_r (ordered_r), .order_q_zero (order_q_zero), .rcv_open_bank (rcv_open_bank), .rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]), .q_has_rd (q_has_rd), .q_has_priority (q_has_priority), .wait_for_maint_r (wait_for_maint_r), // Inputs .clk (clk), .rst (rst), .accept_internal_r (accept_internal_r), .use_addr (use_addr), .periodic_rd_ack_r (periodic_rd_ack_r), .bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .accept_req (accept_req), .rb_hit_busy_r (rb_hit_busy_r), .maint_idle (maint_idle), .maint_hit (maint_hit), .row_hit_r (row_hit_r), .pre_wait_r (pre_wait_r), .allow_auto_pre (allow_auto_pre), .sending_col (sending_col), .req_wr_r (req_wr_r), .rd_wr_r (rd_wr_r), .bank_wait_in_progress (bank_wait_in_progress), .precharge_bm_end (precharge_bm_end), .adv_order_q (adv_order_q), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]), .passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]), .was_wr (was_wr), .maint_req_r (maint_req_r), .was_priority (was_priority)); endmodule // bank_cntrl ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_common.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. 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Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_common.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Common block for the bank machines. Bank_common computes various // items that cross all of the bank machines. These values are then // fed back to all of the bank machines. Most of these values have // to do with a row machine figuring out where it belongs in a queue. `timescale 1 ps / 1 ps module mig_7series_v4_0_bank_common # ( parameter TCQ = 100, parameter BM_CNT_WIDTH = 2, parameter LOW_IDLE_CNT = 1, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nOP_WAIT = 0, parameter nRFC = 44, parameter nXSDLL = 512, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter CWL = 5, parameter tZQCS = 64 ) (/*AUTOARG*/ // Outputs accept_internal_r, accept_ns, accept, periodic_rd_insert, periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt, adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr, was_priority, maint_wip_r, maint_idle, insert_maint_r, // Inputs clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr, rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp, passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r, maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end, slot_0_present, slot_1_present ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam ZERO = 0; localparam ONE = 1; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH]; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH]; input clk; input rst; input [nBANK_MACHS-1:0] idle_ns; input init_calib_complete; wire accept_internal_ns = init_calib_complete && |idle_ns; output reg accept_internal_r; always @(posedge clk) accept_internal_r <= accept_internal_ns; wire periodic_rd_ack_ns; wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns; output wire accept_ns; assign accept_ns = accept_ns_lcl; reg accept_r; always @(posedge clk) accept_r <= #TCQ accept_ns_lcl; // Wire to user interface informing user that the request has been accepted. output wire accept; assign accept = accept_r; `ifdef MC_SVA property none_idle; @(posedge clk) (init_calib_complete && ~|idle_r); endproperty all_bank_machines_busy: cover property (none_idle); `endif // periodic_rd_insert tells everyone to mux in the periodic read. input periodic_rd_r; reg periodic_rd_ack_r_lcl; reg periodic_rd_cntr_r ; always @(posedge clk) begin if (rst) periodic_rd_cntr_r <= #TCQ 1'b0; else if (periodic_rd_r && periodic_rd_ack_r_lcl) periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r; end wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl); // wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl; wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl; output wire periodic_rd_insert; assign periodic_rd_insert = periodic_rd_insert_lcl; // periodic_rd_ack_r acknowledges that the read has been accepted // into the queue. assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns; always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns; output wire periodic_rd_ack_r; assign periodic_rd_ack_r = periodic_rd_ack_r_lcl; // accept_req tells all q entries that a request has been accepted. input use_addr; wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr); output wire accept_req; assign accept_req = accept_req_lcl; // Count how many non idle bank machines hit on the rank and bank. input [nBANK_MACHS-1:0] rb_hit_busy_r; output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; integer i; always @(/*AS*/rb_hit_busy_r) begin rb_hit_busy_cnt = BM_CNT_ZERO; for (i = 0; i < nBANK_MACHS; i = i + 1) if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE; end // Count the number of idle bank machines. input [nBANK_MACHS-1:0] idle_r; output reg [BM_CNT_WIDTH-1:0] idle_cnt; always @(/*AS*/idle_r) begin idle_cnt = BM_CNT_ZERO; for (i = 0; i < nBANK_MACHS; i = i + 1) if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE; end // Report an overall idle status output idle; assign idle = init_calib_complete && &idle_r; // Count the number of bank machines in the ordering queue. input [nBANK_MACHS-1:0] ordered_r; output reg [BM_CNT_WIDTH-1:0] order_cnt; always @(/*AS*/ordered_r) begin order_cnt = BM_CNT_ZERO; for (i = 0; i < nBANK_MACHS; i = i + 1) if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE; end input [nBANK_MACHS-1:0] ordered_issued; output wire adv_order_q; assign adv_order_q = |ordered_issued; // Figure out which bank machine is going to accept the next request. input [nBANK_MACHS-1:0] head_r; wire [nBANK_MACHS-1:0] next = idle_r & head_r; output reg[BM_CNT_WIDTH-1:0] bank_mach_next; always @(/*AS*/next) begin bank_mach_next = BM_CNT_ZERO; for (i = 0; i <= nBANK_MACHS-1; i = i + 1) if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0]; end input [nBANK_MACHS-1:0] end_rtp; input [nBANK_MACHS-1:0] passing_open_bank; input [nBANK_MACHS-1:0] op_exit_req; output wire [nBANK_MACHS-1:0] op_exit_grant; output reg low_idle_cnt_r = 1'b0; input [nBANK_MACHS-1:0] start_pre_wait; generate // In support of open page mode, the following logic // keeps track of how many "idle" bank machines there // are. In this case, idle means a bank machine is on // the idle list, or is in the process of precharging and // will soon be idle. if (nOP_WAIT == 0) begin : op_mode_disabled assign op_exit_grant = {nBANK_MACHS{1'b0}}; end else begin : op_mode_enabled reg [BM_CNT_WIDTH:0] idle_cnt_r; reg [BM_CNT_WIDTH:0] idle_cnt_ns; always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank or rst or start_pre_wait) if (rst) idle_cnt_ns = nBANK_MACHS; else begin idle_cnt_ns = idle_cnt_r - accept_req_lcl; for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin idle_cnt_ns = idle_cnt_ns + passing_open_bank[i]; end idle_cnt_ns = idle_cnt_ns + |start_pre_wait; end always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns; wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]); always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns; // This arbiter determines which bank machine should transition // from open page wait to precharge. Ideally, this process // would take the oldest waiter, but don't have any reasonable // way to implement that. Instead, just use simple round robin // arb with the small enhancement that the most recent bank machine // to enter open page wait is given lowest priority in the arbiter. wire upd_last_master = |end_rtp; // should be one bit set at most mig_7series_v4_0_round_robin_arb # (.WIDTH (nBANK_MACHS)) op_arb0 (.grant_ns (op_exit_grant[nBANK_MACHS-1:0]), .grant_r (), .upd_last_master (upd_last_master), .current_master (end_rtp[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (op_exit_req[nBANK_MACHS-1:0]), .disable_grant (1'b0)); end endgenerate // Register some command information. This information will be used // by the bank machines to figure out if there is something behind it // in the queue that require hi priority. input [2:0] cmd; output reg was_wr; always @(posedge clk) was_wr <= #TCQ cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl); input hi_priority; output reg was_priority; always @(posedge clk) begin if (hi_priority) was_priority <= #TCQ 1'b1; else was_priority <= #TCQ 1'b0; end // DRAM maintenance (refresh and ZQ) and self-refresh controller input maint_req_r; reg maint_wip_r_lcl; output wire maint_wip_r; assign maint_wip_r = maint_wip_r_lcl; wire maint_idle_lcl; output wire maint_idle; assign maint_idle = maint_idle_lcl; input maint_zq_r; input maint_sre_r; input maint_srx_r; input [nBANK_MACHS-1:0] maint_hit; input [nBANK_MACHS-1:0] bm_end; wire start_maint; wire maint_end; generate begin : maint_controller // Idle when not (maintenance work in progress (wip), OR maintenance // starting tick). assign maint_idle_lcl = ~(maint_req_r && ~periodic_rd_cntr_r) && ~maint_wip_r_lcl; // Maintenance work in progress starts with maint_reg_r tick, terminated // with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer // below. wire maint_wip_ns = ~rst && ~maint_end && (maint_wip_r_lcl || (maint_req_r && ~periodic_rd_cntr_r)); always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns; // Keep track of which bank machines hit on the maintenance request // when the request is made. As bank machines complete, an assertion // of the bm_end signal clears the correspoding bit in the // maint_hit_busies_r vector. Eventually, all bits should clear and // the maintenance operation will proceed. ZQ and self-refresh hit on all // non idle banks. Refresh hits only on non idle banks with the same rank as // the refresh request. wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end; wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} & (maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns; wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} & (maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns; reg [nBANK_MACHS-1:0] maint_hit_busies_r; wire [nBANK_MACHS-1:0] maint_hit_busies_ns = ~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits); always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns; // Queue is clear of requests conflicting with maintenance. wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns; // Ready to start sending maintenance commands. wire maint_rdy = maint_clear; reg maint_rdy_r1; reg maint_srx_r1; always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy; always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r; assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1; end // block: maint_controller endgenerate // Figure out how many maintenance commands to send, and send them. input [7:0] slot_0_present; input [7:0] slot_1_present; reg insert_maint_r_lcl; output wire insert_maint_r; assign insert_maint_r = insert_maint_r_lcl; generate begin : generate_maint_cmds // Count up how many slots are occupied. This tells // us how many ZQ, SRE or SRX commands to send out. reg [RANK_WIDTH:0] present_count; wire [7:0] present = slot_0_present | slot_1_present; always @(/*AS*/present) begin present_count = {RANK_WIDTH{1'b0}}; for (i=0; i<8; i=i+1) present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]}; end // For refresh, there is only a single command sent. For // ZQ, SRE and SRX, each rank present will receive a command. The counter // below counts down the number of ranks present. reg [RANK_WIDTH:0] send_cnt_ns; reg [RANK_WIDTH:0] send_cnt_r; always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count or rst or send_cnt_r or start_maint) if (rst) send_cnt_ns = 4'b0; else begin send_cnt_ns = send_cnt_r; if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count; if (|send_cnt_ns) send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0]; end always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns; // Insert a maintenance command for start_maint, or when the sent count // is not zero. wire insert_maint_ns = start_maint || |send_cnt_r; always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns; end // block: generate_maint_cmds endgenerate // RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ // command until the end of the maintenance operation. // Compute values for RFC, ZQ and XSDLL periods. localparam nRFC_CLKS = (nCK_PER_CLK == 1) ? nRFC : (nCK_PER_CLK == 2) ? ((nRFC/2) + (nRFC%2)) : // (nCK_PER_CLK == 4) ((nRFC/4) + ((nRFC%4) ? 1 : 0)); localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ? tZQCS : (nCK_PER_CLK == 2) ? ((tZQCS/2) + (tZQCS%2)) : // (nCK_PER_CLK == 4) ((tZQCS/4) + ((tZQCS%4) ? 1 : 0)); localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ? nXSDLL : (nCK_PER_CLK == 2) ? ((nXSDLL/2) + (nXSDLL%2)) : // (nCK_PER_CLK == 4) ((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0)); localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1); localparam THREE = 3; generate begin : rfc_zq_xsdll_timer reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns; reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r; always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r or rfc_zq_xsdll_timer_r or rst) begin rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r; if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}}; else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ? nZQCS_CLKS : maint_sre_r ? {RFC_ZQ_TIMER_WIDTH{1'b0}} : maint_srx_r ? nXSDLL_CLKS : nRFC_CLKS; else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0]; end always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns; // Based on rfc_zq_xsdll_timer_r, figure out when to release any bank // machines waiting to send an activate. Need to add two to the end count. // One because the counter starts a state after the insert_refresh_r, and // one more because bm_end to insert_refresh_r is one state shorter // than bm_end to rts_row. assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]); end // block: rfc_zq_xsdll_timer endgenerate endmodule // bank_common ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_compare.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // This block stores the request for this bank machine. // // All possible new requests are compared against the request stored // here. The compare results are shared with the bank machines and // is used to determine where to enqueue a new request. `timescale 1ps/1ps module mig_7series_v4_0_bank_compare # (parameter BANK_WIDTH = 3, parameter TCQ = 100, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter DATA_BUF_ADDR_WIDTH = 8, parameter ECC = "OFF", parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16) (/*AUTOARG*/ // Outputs req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r, req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r, rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr, req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r, // Inputs clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd, sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority, maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r ); input clk; input idle_ns; input idle_r; input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr; output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns = idle_r ? data_buf_addr : req_data_buf_addr_r; always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns; input periodic_rd_insert; reg req_periodic_rd_r_lcl; wire req_periodic_rd_ns = idle_ns ? periodic_rd_insert : req_periodic_rd_r_lcl; always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns; output wire req_periodic_rd_r; assign req_periodic_rd_r = req_periodic_rd_r_lcl; input size; wire req_size_r_lcl; generate if (BURST_MODE == "4") begin : burst_mode_4 assign req_size_r_lcl = 1'b0; end else if (BURST_MODE == "8") begin : burst_mode_8 assign req_size_r_lcl = 1'b1; end else if (BURST_MODE == "OTF") begin : burst_mode_otf reg req_size; wire req_size_ns = idle_ns ? (periodic_rd_insert || size) : req_size; always @(posedge clk) req_size <= #TCQ req_size_ns; assign req_size_r_lcl = req_size; end endgenerate output wire req_size_r; assign req_size_r = req_size_r_lcl; input [2:0] cmd; reg [2:0] req_cmd_r; wire [2:0] req_cmd_ns = idle_ns ? (periodic_rd_insert ? 3'b001 : cmd) : req_cmd_r; always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns; `ifdef MC_SVA rd_wr_only_wo_ecc: assert property (@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1])); `endif input sending_col; reg rd_wr_r_lcl; wire rd_wr_ns = idle_ns ? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0]) : ~sending_col && rd_wr_r_lcl; always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns; output wire rd_wr_r; assign rd_wr_r = rd_wr_r_lcl; input [RANK_WIDTH-1:0] rank; input [RANK_WIDTH-1:0] periodic_rd_rank_r; reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}}; reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}}; generate if (RANKS != 1) begin always @(/*AS*/idle_ns or periodic_rd_insert or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns ? periodic_rd_insert ? periodic_rd_rank_r : rank : req_rank_r_lcl; always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns; end endgenerate output wire [RANK_WIDTH-1:0] req_rank_r; assign req_rank_r = req_rank_r_lcl; input [BANK_WIDTH-1:0] bank; reg [BANK_WIDTH-1:0] req_bank_r_lcl; wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl; always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns; output wire[BANK_WIDTH-1:0] req_bank_r; assign req_bank_r = req_bank_r_lcl; input [ROW_WIDTH-1:0] row; reg [ROW_WIDTH-1:0] req_row_r_lcl; wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl; always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns; output wire [ROW_WIDTH-1:0] req_row_r; assign req_row_r = req_row_r_lcl; // Make req_col_r as wide as the max row address. This // makes it easier to deal with indexing different column widths. input [COL_WIDTH-1:0] col; reg [15:0] req_col_r = 16'b0; wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0]; always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns; reg req_wr_r_lcl; wire req_wr_ns = idle_ns ? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0]) : req_wr_r_lcl; always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns; output wire req_wr_r; assign req_wr_r = req_wr_r_lcl; input hi_priority; output reg req_priority_r; wire req_priority_ns = idle_ns ? hi_priority : req_priority_r; always @(posedge clk) req_priority_r <= #TCQ req_priority_ns; wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert ? periodic_rd_rank_r : rank)); wire bank_hit = (req_bank_r_lcl == bank); wire rank_bank_hit = rank_hit && bank_hit; output reg rb_hit_busy_r; // rank-bank hit on non idle row machine wire rb_hit_busy_ns_lcl; assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns; output wire rb_hit_busy_ns; assign rb_hit_busy_ns = rb_hit_busy_ns_lcl; wire row_hit_ns = (req_row_r_lcl == row); output reg row_hit_r; always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl; always @(posedge clk) row_hit_r <= #TCQ row_hit_ns; input [RANK_WIDTH-1:0] maint_rank_r; input maint_zq_r; input maint_sre_r; output wire maint_hit; assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r; // Assemble column address. Structure to be the same // width as the row address. This makes it easier // for the downstream muxing. Depending on the sizes // of the row and column addresses, fill in as appropriate. input auto_pre_r; input rd_half_rmw; reg [15:0] col_addr_template = 16'b0; always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r or req_size_r_lcl) begin col_addr_template = req_col_r; col_addr_template[10] = auto_pre_r && ~rd_half_rmw; col_addr_template[11] = req_col_r[10]; col_addr_template[12] = req_size_r_lcl; col_addr_template[13] = req_col_r[11]; end output wire [ROW_WIDTH-1:0] col_addr; assign col_addr = col_addr_template[ROW_WIDTH-1:0]; output wire req_ras; output wire req_cas; output wire row_cmd_wr; input act_wait_r; assign req_ras = 1'b0; assign req_cas = 1'b1; assign row_cmd_wr = act_wait_r; output reg [ROW_WIDTH-1:0] row_addr; always @(/*AS*/act_wait_r or req_row_r_lcl) begin row_addr = req_row_r_lcl; // This causes all precharges to be precharge single bank command. if (~act_wait_r) row_addr[10] = 1'b0; end // Indicate which, if any, rank this bank machine is busy with. // Not registering the result would probably be more accurate, but // would create timing issues. This is used for refresh banking, perfect // accuracy is not required. localparam ONE = 1; output reg [RANKS-1:0] rank_busy_r; wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns); always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns; endmodule // bank_compare ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level bank machine block. A structural block instantiating the configured // individual bank machines, and a common block that computes various items shared // by all bank machines. `timescale 1ps/1ps module mig_7series_v4_0_bank_mach # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_WIDTH = 3, parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter LOW_IDLE_CNT = 1, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nCS_PER_RANK = 1, parameter nOP_WAIT = 0, parameter nRAS = 20, parameter nRCD = 5, parameter nRFC = 44, parameter nRTP = 4, parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter nRP = 10, parameter nSLOTS = 2, parameter nWR = 6, parameter nXSDLL = 512, parameter ORDERING = "NORM", parameter RANK_BM_BV_WIDTH = 16, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010, parameter tZQCS = 64 ) (/*AUTOARG*/ // Outputs output accept, // From bank_common0 of bank_common.v output accept_ns, // From bank_common0 of bank_common.v output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v output col_periodic_rd, // From arb_mux0 of arb_mux.v output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v output col_rmw, // From arb_mux0 of arb_mux.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v output col_size, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output insert_maint_r1, // From arb_mux0 of arb_mux.v output maint_wip_r, // From bank_common0 of bank_common.v output wire [nBANK_MACHS-1:0] sending_row, output wire [nBANK_MACHS-1:0] sending_col, output wire sent_col, output wire sent_col_r, output periodic_rd_ack_r, output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, output idle, // Inputs input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input clk, // To bank0 of bank_cntrl.v, ... input [2:0] cmd, // To bank0 of bank_cntrl.v, ... input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v input init_calib_complete, // To bank_common0 of bank_common.v input phy_rddata_valid, // To bank0 of bank_cntrl.v input dq_busy_data, // To bank0 of bank_cntrl.v input hi_priority, // To bank0 of bank_cntrl.v, ... input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ... input maint_req_r, // To bank0 of bank_cntrl.v, ... input maint_zq_r, // To bank0 of bank_cntrl.v, ... input maint_sre_r, // To bank0 of bank_cntrl.v, ... input maint_srx_r, // To bank0 of bank_cntrl.v, ... input periodic_rd_r, // To bank_common0 of bank_common.v input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v input rd_rmw, // To bank0 of bank_cntrl.v input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v input rst, // To bank0 of bank_cntrl.v, ... input size, // To bank0 of bank_cntrl.v input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ... input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ... input use_addr ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1; localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1; localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1; localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1; localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0)); localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR; // Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of // one DRAM CK due to column command to row command fixed offset. In 2T mode, // Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T // mode, in which case we add 1 if the remainder exceeds the fixed offset. localparam nWTP_CLKS = (nCK_PER_CLK == 1) ? nWTP : (nCK_PER_CLK == 2) ? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) : (nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2); localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS) ? nRAS_CLKS : nWTP_CLKS) - 1); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire accept_internal_r; // From bank_common0 of bank_common.v wire accept_req; // From bank_common0 of bank_common.v wire adv_order_q; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v wire insert_maint_r; // From bank_common0 of bank_common.v wire low_idle_cnt_r; // From bank_common0 of bank_common.v wire maint_idle; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v wire periodic_rd_insert; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v wire sent_row; // From arb_mux0 of arb_mux.v wire was_priority; // From bank_common0 of bank_common.v wire was_wr; // From bank_common0 of bank_common.v // End of automatics wire [RANK_WIDTH-1:0] rnk_config; wire rnk_config_strobe; wire rnk_config_kill_rts_col; wire rnk_config_valid_r; wire [nBANK_MACHS-1:0] rts_row; wire [nBANK_MACHS-1:0] rts_col; wire [nBANK_MACHS-1:0] rts_pre; wire [nBANK_MACHS-1:0] col_rdy_wr; wire [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] sending_pre; wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r; wire [nBANK_MACHS-1:0] req_size_r; wire [RANK_VECT_INDX:0] req_rank_r; wire [BANK_VECT_INDX:0] req_bank_r; wire [ROW_VECT_INDX:0] req_row_r; wire [ROW_VECT_INDX:0] col_addr; wire [nBANK_MACHS-1:0] req_periodic_rd_r; wire [nBANK_MACHS-1:0] req_wr_r; wire [nBANK_MACHS-1:0] rd_wr_r; wire [nBANK_MACHS-1:0] req_ras; wire [nBANK_MACHS-1:0] req_cas; wire [ROW_VECT_INDX:0] row_addr; wire [nBANK_MACHS-1:0] row_cmd_wr; wire [nBANK_MACHS-1:0] demand_priority; wire [nBANK_MACHS-1:0] demand_act_priority; wire [nBANK_MACHS-1:0] idle_ns; wire [nBANK_MACHS-1:0] rb_hit_busy_r; wire [nBANK_MACHS-1:0] bm_end; wire [nBANK_MACHS-1:0] passing_open_bank; wire [nBANK_MACHS-1:0] ordered_r; wire [nBANK_MACHS-1:0] ordered_issued; wire [nBANK_MACHS-1:0] rb_hit_busy_ns; wire [nBANK_MACHS-1:0] maint_hit; wire [nBANK_MACHS-1:0] idle_r; wire [nBANK_MACHS-1:0] head_r; wire [nBANK_MACHS-1:0] start_rcd; wire [nBANK_MACHS-1:0] end_rtp; wire [nBANK_MACHS-1:0] op_exit_req; wire [nBANK_MACHS-1:0] op_exit_grant; wire [nBANK_MACHS-1:0] start_pre_wait; wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns; genvar ID; generate for (ID=0; ID 1) begin : compute_tail reg tail_ns; always @(accept_req or accept_this_bm or bm_end_in or bm_end_lcl or idle_r_lcl or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin if (rst) tail_ns = (ID == nBANK_MACHS); // The order of the statements below is important in the case where // another bank machine is retiring and this bank machine is accepting. else begin tail_ns = tail_r_lcl; if ((accept_req && rb_hit_busy_r) || (|bm_end_in[`BM_SHARED_BV] && idle_r_lcl)) tail_ns = 1'b0; if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1; end end always @(posedge clk) tail_r_lcl <= #TCQ tail_ns; end // if (nBANK_MACHS > 1) endgenerate output wire tail_r; assign tail_r = tail_r_lcl; wire clear_req = bm_end_lcl || rst; // Is this entry in the idle queue? reg idle_ns_lcl; always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin idle_ns_lcl = idle_r_lcl; if (accept_this_bm) idle_ns_lcl = 1'b0; if (clear_req) idle_ns_lcl = 1'b1; end always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl; output wire idle_ns; assign idle_ns = idle_ns_lcl; output wire idle_r; assign idle_r = idle_r_lcl; // Maintenance hitting on this active bank machine is in progress. input maint_idle; input maint_hit; wire maint_hit_this_bm = ~maint_idle && maint_hit; // Does new request hit on this bank machine while it is able to pass the // open bank? input row_hit_r; input pre_wait_r; wire pass_open_bank_eligible = tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r; // Set pass open bank bit, but not if request preceded active maintenance. reg wait_for_maint_r_lcl; reg pass_open_bank_r_lcl; wire pass_open_bank_ns_lcl = ~clear_req && (pass_open_bank_r_lcl || (accept_req && pass_open_bank_eligible && (~maint_hit_this_bm || wait_for_maint_r_lcl))); always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl; output wire pass_open_bank_ns; assign pass_open_bank_ns = pass_open_bank_ns_lcl; output wire pass_open_bank_r; assign pass_open_bank_r = pass_open_bank_r_lcl; `ifdef MC_SVA pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns)); pass_open_bank_killed_by_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && ~wait_for_maint_r_lcl)); pass_open_bank_following_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && wait_for_maint_r_lcl)); `endif // Should the column command be sent with the auto precharge bit set? This // will happen when it is detected that next request is to a different row, // or the next reqest is the next request is refresh to this rank. reg auto_pre_r_lcl; reg auto_pre_ns; input allow_auto_pre; always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl or clear_req or maint_hit_this_bm or rb_hit_busy_r or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin auto_pre_ns = auto_pre_r_lcl; if (clear_req) auto_pre_ns = 1'b0; else if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r && (~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl))) auto_pre_ns = 1'b1; end always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns; output wire auto_pre_r; assign auto_pre_r = auto_pre_r_lcl; `ifdef MC_SVA auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns)); maint_triggers_auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns && ~auto_pre_r && row_hit_r)); `endif // Determine when the current request is finished. input sending_col; input req_wr_r; input rd_wr_r; wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r); input bank_wait_in_progress; input precharge_bm_end; reg pre_bm_end_r; wire pre_bm_end_ns = precharge_bm_end || (bank_wait_in_progress && pass_open_bank_ns_lcl); always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns; assign bm_end_lcl = pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); output wire bm_end; assign bm_end = bm_end_lcl; // Determine that the open bank should be passed to the successor bank machine. reg pre_passing_open_bank_r; wire pre_passing_open_bank_ns = bank_wait_in_progress && pass_open_bank_ns_lcl; always @(posedge clk) pre_passing_open_bank_r <= #TCQ pre_passing_open_bank_ns; output wire passing_open_bank; assign passing_open_bank = pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); reg ordered_ns; wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)) && accept_this_bm; wire ordered_issued_lcl = sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) && ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)); output wire ordered_issued; assign ordered_issued = ordered_issued_lcl; reg ordered_r_lcl; always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst or set_order_q) begin if (rst) ordered_ns = 1'b0; else begin ordered_ns = ordered_r_lcl; // Should never see accept_this_bm and adv_order_q at the same time. if (set_order_q) ordered_ns = 1'b1; if (ordered_issued_lcl) ordered_ns = 1'b0; end end always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns; output wire ordered_r; assign ordered_r = ordered_r_lcl; // Figure out when to advance the ordering queue. input adv_order_q; input [BM_CNT_WIDTH-1:0] order_cnt; reg [BM_CNT_WIDTH-1:0] order_q_r; reg [BM_CNT_WIDTH-1:0] order_q_ns; always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst or set_order_q) begin order_q_ns = order_q_r; if (rst) order_q_ns = BM_CNT_ZERO; if (set_order_q) if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE; else order_q_ns = order_cnt; if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE; end always @(posedge clk) order_q_r <= #TCQ order_q_ns; output wire order_q_zero; assign order_q_zero = ~|order_q_r || (adv_order_q && (order_q_r == BM_CNT_ONE)) || ((ORDERING == "NORM") && rd_wr_r); // Keep track of which other bank machine are ahead of this one in a // rank-bank queue. This is necessary to know when to advance this bank // machine in the queue, and when to update bank state machine counter upon // passing a bank. input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in; reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}}; input [(nBANK_MACHS*2)-1:0] passing_open_bank_in; output reg rcv_open_bank = 1'b0; generate if (nBANK_MACHS > 1) begin : rb_hit_busies // The clear_vector resets bits in the rb_hit_busies vector as bank machines // completes requests. rst also resets all the bits. wire [nBANK_MACHS-2:0] clear_vector = ({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]); // As this bank machine takes on a new request, capture the vector of // which other bank machines are in the same queue. wire [`BM_SHARED_BV] rb_hit_busies_ns = ~clear_vector & (idle_ns_lcl ? rb_hit_busy_ns_in[`BM_SHARED_BV] : rb_hit_busies_r_lcl[`BM_SHARED_BV]); always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <= #TCQ rb_hit_busies_ns; // Compute when to advance this queue entry based on seeing other bank machines // in the same queue finish. always @(bm_end_in or rb_hit_busies_r_lcl) adv_queue = |(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]); // Decide when to receive an open bank based on knowing this bank machine is // one entry from the head, and a passing_open_bank hits on the // rb_hit_busies vector. always @(idle_r_lcl or passing_open_bank_in or q_entry_r or rb_hit_busies_r_lcl) rcv_open_bank = |(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV]) && (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl; end endgenerate output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; assign rb_hit_busies_r = rb_hit_busies_r_lcl; // Keep track if the queue this entry is in has priority content. input was_wr; input maint_req_r; reg q_has_rd_r; wire q_has_rd_ns = ~clear_req && (q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) || (maint_req_r && maint_hit && ~idle_r_lcl)); always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns; output wire q_has_rd; assign q_has_rd = q_has_rd_r; input was_priority; reg q_has_priority_r; wire q_has_priority_ns = ~clear_req && (q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority)); always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns; output wire q_has_priority; assign q_has_priority = q_has_priority_r; // Figure out if this entry should wait for maintenance to end. wire wait_for_maint_ns = ~rst && ~maint_idle && (wait_for_maint_r_lcl || (maint_hit && accept_this_bm)); always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns; output wire wait_for_maint_r; assign wait_for_maint_r = wait_for_maint_r_lcl; endmodule // bank_queue ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_state.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. 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Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_state.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Primary bank state machine. All bank specific timing is generated here. // // Conceptually, when a bank machine is assigned a request, conflicts are // checked. If there is a conflict, then the new request is added // to the queue for that rank-bank. // // Eventually, that request will find itself at the head of the queue for // its rank-bank. Forthwith, the bank machine will begin arbitration to send an // activate command to the DRAM. Once arbitration is successful and the // activate is sent, the row state machine waits the RCD delay. The RAS // counter is also started when the activate is sent. // // Upon completion of the RCD delay, the bank state machine will begin // arbitration for sending out the column command. Once the column // command has been sent, the bank state machine waits the RTP latency, and // if the command is a write, the RAS counter is loaded with the WR latency. // // When the RTP counter reaches zero, the pre charge wait state is entered. // Once the RAS timer reaches zero, arbitration to send a precharge command // begins. // // Upon successful transmission of the precharge command, the bank state // machine waits the precharge period and then rejoins the idle list. // // For an open rank-bank hit, a bank machine passes management of the rank-bank to // a bank machine that is managing the subsequent request to the same page. A bank // machine can either be a "passer" or a "passee" in this handoff. There // are two conditions that have to occur before an open bank can be passed. // A spatial condition, ie same rank-bank and row address. And a temporal condition, // ie the passee has completed it work with the bank, but has not issued a precharge. // // The spatial condition is signalled by pass_open_bank_ns. The temporal condition // is when the column command is issued, or when the bank_wait_in_progress // signal is true. Bank_wait_in_progress is true when the RTP timer is not // zero, or when the RAS/WR timer is not zero and the state machine is waiting // to send out a precharge command. // // On an open bank pass, the passer transitions from the temporal condition // noted above and performs the end of request processing and eventually lands // in the act_wait_r state. // // On an open bank pass, the passee lands in the col_wait_r state and waits // for its chance to send out a column command. // // Since there is a single data bus shared by all columns in all ranks, there // is a single column machine. The column machine is primarily in charge of // managing the timing on the DQ data bus. It reserves states for data transfer, // driver turnaround states, and preambles. It also has the ability to add // additional programmable delay for read to write changeovers. This read to write // delay is generated in the column machine which inhibits writes via the // inhbt_wr signal. // // There is a rank machine for every rank. The rank machines are responsible // for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed // in the bank machine since it is closely coupled to the operation of the // bank machine and is timing critical. // // Since a bank machine can be working on a request for any rank, all rank machines // inhibits are input to all bank machines. Based on the rank of the current // request, each bank machine selects the rank information corresponding // to the rank of its current request. // // Since driver turnaround states and WTR delays are so severe with DDRIII, the // memory interface has the ability to promote requests that use the same // driver as the most recent request. There is logic in this block that // detects when the driver for its request is the same as the driver for // the most recent request. In such a case, this block will send out special // "same" request early enough to eliminate dead states when there is no // driver changeover. `timescale 1ps/1ps `define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1) module mig_7series_v4_0_bank_state # ( parameter TCQ = 100, parameter ADDR_CMD_MODE = "1T", parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter ECC = "OFF", parameter ID = 0, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nOP_WAIT = 0, parameter nRAS_CLKS = 10, parameter nRP = 10, parameter nRTP = 4, parameter nRCD = 5, parameter nWTP_CLKS = 5, parameter ORDERING = "NORM", parameter RANKS = 4, parameter RANK_WIDTH = 4, parameter RAS_TIMER_WIDTH = 5, parameter STARVE_LIMIT = 2 ) (/*AUTOARG*/ // Outputs start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp, bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r, allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row, act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r, rd_this_rank_r, rts_pre, rtc, // Inputs clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank, sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r, phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r, passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r, auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in, start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row, demand_act_priority_in, order_q_zero, sent_col, q_has_rd, q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd, inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config, rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; // Activate wait state machine. input bm_end; reg bm_end_r1; always @(posedge clk) bm_end_r1 <= #TCQ bm_end; reg col_wait_r; input pass_open_bank_r; input sending_row; reg act_wait_r_lcl; input rcv_open_bank; wire start_rcd_lcl = act_wait_r_lcl && sending_row; output wire start_rcd; assign start_rcd = start_rcd_lcl; wire act_wait_ns = rst || ((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) || bm_end_r1 || (pass_open_bank_r && bm_end)); always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns; output wire act_wait_r; assign act_wait_r = act_wait_r_lcl; // RCD timer // // When CWL is even, CAS commands are issued on slot 0 and RAS commands are // issued on slot 1. This implies that the RCD can never expire in the same // cycle as the RAS (otherwise the CAS for a given transaction would precede // the RAS). Similarly, this can also cause premature expiration for longer // RCD. An offset must be added to RCD before translating it to the FPGA clock // domain. In this mode, CAS are on the first DRAM clock cycle corresponding to // a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to // the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode. // // When CWL is odd, RAS commands are issued on slot 0 and CAS commands are // issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS // in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the // RAS command. In 2:1 mode, there are only 2 slots so direct translation // correctly places the CAS with respect to the corresponding RAS. In 4:1 mode, // there are two slots after CAS, so 2 is added to shift the timer into the // next FPGA cycle for cases that can't expire in the current cycle. // // In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode, // It is sufficient to translate to the half-rate domain and add the remainder. // In 4:1 mode, we must translate to the quarter-rate domain and add an // additional fabric cycle only if the remainder exceeds the fixed offset of 2 localparam nRCD_CLKS = nCK_PER_CLK == 1 ? nRCD : nCK_PER_CLK == 2 ? ADDR_CMD_MODE == "2T" ? (nRCD/2) + (nRCD%2) : CWL % 2 ? (nRCD/2) : (nRCD+2) / 2 : // (nCK_PER_CLK == 4) ADDR_CMD_MODE == "2T" ? (nRCD/4) + (nRCD%4 > 2 ? 1 : 0) : CWL % 2 ? (nRCD-2 ? (nRCD-2) / 4 + 1 : 1) : nRCD/4 + 1; localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2; localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1); localparam ZERO = 0; localparam ONE = 1; reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}}; reg end_rcd; reg rcd_active_r = 1'b0; generate if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2 always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl; end else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2 reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns; always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0]; else begin rcd_timer_ns = rcd_timer_r; if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0]; else if (|rcd_timer_r) rcd_timer_ns = rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0]; end end always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns; wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]); always @(posedge clk) end_rcd = end_rcd_ns; wire rcd_active_ns = |rcd_timer_ns; always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns; end endgenerate // Figure out if the read that's completing is for an RMW for // this bank machine. Delay by a state if CWL != 8 since the // data is not ready in the RMW buffer for the early write // data fetch that happens with ECC and CWL != 8. // Create a state bit indicating we're waiting for the read // half of the rmw to complete. input sending_col; input rd_wr_r; input req_wr_r; input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; input phy_rddata_valid; input rd_rmw; reg rmw_rd_done = 1'b0; reg rd_half_rmw_lcl = 1'b0; output wire rd_half_rmw; assign rd_half_rmw = rd_half_rmw_lcl; reg rmw_wait_r = 1'b0; generate if (ECC != "OFF") begin : rmw_on // Delay phy_rddata_valid and rd_rmw by one cycle to align them // to req_data_buf_addr_r so that rmw_wait_r clears properly reg phy_rddata_valid_r; reg rd_rmw_r; always @(posedge clk) begin phy_rddata_valid_r <= #TCQ phy_rddata_valid; rd_rmw_r <= #TCQ rd_rmw; end wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r && (rd_data_addr == req_data_buf_addr_r); if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns; else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns; always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r; wire rmw_wait_ns = ~rst && ((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col)); always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns; end endgenerate // column wait state machine. wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd || rcv_open_bank || (rmw_rd_done && rmw_wait_r)); always @(posedge clk) col_wait_r <= #TCQ col_wait_ns; // Set up various RAS timer parameters, wires, etc. localparam TWO = 2; output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns; reg [RAS_TIMER_WIDTH-1:0] ras_timer_r; input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in; input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r; // On a bank pass, select the RAS timer from the passing bank machine. reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer; integer i; always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}}; for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1) if (rb_hit_busies_r[i]) passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH]; end // RAS and (reused for) WTP timer. When an open bank is passed, this // timer is passed to the new owner. The existing RAS prevents // an activate from occuring too early. wire start_wtp_timer = sending_col && ~rd_wr_r; input idle_r; always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl or start_wtp_timer) begin if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0]; else begin ras_timer_ns = ras_timer_r; if (start_rcd_lcl) ras_timer_ns = nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]; if (start_wtp_timer) ras_timer_ns = // As the timer is being reused, it is essential to compare // before new value is loaded. (ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0] : ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0]; if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns = ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0]; end end // always @ (... wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank ? passed_ras_timer : ras_timer_ns; always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns; wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]); reg ras_timer_zero_r; always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns; // RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of // one DRAM CK due to column command to row command fixed offset. In 2T mode, // Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T // mode, in which case we add 1 if the remainder exceeds the fixed offset. localparam nRTP_CLKS = (nCK_PER_CLK == 1) ? nRTP : (nCK_PER_CLK == 2) ? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) : (nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2); localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1; localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1); reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns; reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r; wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl; always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r or sending_col_not_rmw_rd) begin rtp_timer_ns = rtp_timer_r; if (rst || pass_open_bank_r) rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0]; else begin if (sending_col_not_rmw_rd) rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0]; if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0]; end end always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns; wire end_rtp_lcl = ~pass_open_bank_r && ((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) || ((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd)); output wire end_rtp; assign end_rtp = end_rtp_lcl; // Optionally implement open page mode timer. localparam OP_WIDTH = clogb2(nOP_WAIT + 1); output wire bank_wait_in_progress; output wire start_pre_wait; input passing_open_bank; input low_idle_cnt_r; output wire op_exit_req; input op_exit_grant; input tail_r; output reg pre_wait_r; generate if (nOP_WAIT == 0) begin : op_mode_disabled assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r || (pre_wait_r && ~ras_timer_zero_r); assign start_pre_wait = end_rtp_lcl; assign op_exit_req = 1'b0; end else begin : op_mode_enabled reg op_wait_r; assign bank_wait_in_progress = sending_col || |rtp_timer_r || (pre_wait_r && ~ras_timer_zero_r) || op_wait_r; wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r) || op_wait_r); wire op_wait_ns = ~op_exit_grant && op_active; always @(posedge clk) op_wait_r <= #TCQ op_wait_ns; assign start_pre_wait = op_exit_grant || (end_rtp_lcl && ~tail_r && ~passing_open_bank); if (nOP_WAIT == -1) assign op_exit_req = (low_idle_cnt_r && op_active); else begin : op_cnt reg [OP_WIDTH-1:0] op_cnt_r; wire [OP_WIDTH-1:0] op_cnt_ns = (passing_open_bank || op_exit_grant || rst) ? ZERO[OP_WIDTH-1:0] : end_rtp_lcl ? nOP_WAIT[OP_WIDTH-1:0] : |op_cnt_r ? op_cnt_r - ONE[OP_WIDTH-1:0] : op_cnt_r; always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns; assign op_exit_req = (low_idle_cnt_r && op_active) || (op_wait_r && ~|op_cnt_r); end end endgenerate output allow_auto_pre; wire allow_auto_pre = act_wait_r_lcl || rcd_active_r || (col_wait_r && ~sending_col); // precharge wait state machine. input auto_pre_r; wire start_pre; input pass_open_bank_ns; wire pre_wait_ns = ~rst && (~pass_open_bank_ns && (start_pre_wait || (pre_wait_r && ~start_pre))); always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns; wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r; // precharge timer. localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP : (nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) : /*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0)); // Subtract two because there are a minimum of two fabric states from // end of RP timer until earliest possible arb to send act. localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2; localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1); input sending_pre; output rts_pre; generate if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin assign start_pre = pre_wait_r && ras_timer_zero_r && (sending_pre || auto_pre_r); assign rts_pre = ~sending_pre && pre_request; end else begin assign start_pre = pre_wait_r && ras_timer_zero_r && (sending_row || auto_pre_r); assign rts_pre = 1'b0; end endgenerate reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0]; generate if (nRP_CLKS_M2 > ZERO) begin : rp_timer reg [RP_TIMER_WIDTH-1:0] rp_timer_ns; always @(/*AS*/rp_timer_r or rst or start_pre) if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0]; else begin rp_timer_ns = rp_timer_r; if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0]; else if (|rp_timer_r) rp_timer_ns = rp_timer_r - ONE[RP_TIMER_WIDTH-1:0]; end always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns; end // block: rp_timer endgenerate output wire precharge_bm_end; assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) || (start_pre && (nRP_CLKS_M2 == ZERO)); // Compute RRD related activate inhibit. // Compare this bank machine's rank with others, then // select result based on grant. An alternative is to // select the just issued rank with the grant and simply // compare against this bank machine's rank. However, this // serializes the selection of the rank and the compare processes. // As implemented below, the compare occurs first, then the // selection based on grant. This is faster. input [RANK_WIDTH-1:0] req_rank_r; input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in; reg inhbt_act_rrd; input [(nBANK_MACHS*2)-1:0] start_rcd_in; generate integer j; if (RANKS == 1) always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin inhbt_act_rrd = 1'b0; for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1) inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j]; end else begin always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin inhbt_act_rrd = 1'b0; for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1) inhbt_act_rrd = inhbt_act_rrd || (start_rcd_in[j] && (req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r)); end end endgenerate // Extract the activate command inhibit for the rank associated // with this request. FAW and RRD are computed separately so that // gate level timing can be carefully managed. input [RANKS-1:0] inhbt_act_faw_r; wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r]; input wait_for_maint_r; input head_r; wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r && ~wait_for_maint_r; // Implement simple starvation avoidance for act requests. Precharge // requests don't need this because they are never gated off by // timing events such as inhbt_act_rrd. Priority request timeout // is fixed at a single trip around the round robin arbiter. input sent_row; wire rts_act_denied = act_req && sent_row && ~sending_row; reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns; reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r; generate if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2 begin :BM_MORE_THAN_2 always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied) begin act_starve_limit_cntr_ns = act_starve_limit_cntr_r; if (~act_req) act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}}; else if (rts_act_denied && &act_starve_limit_cntr_r) act_starve_limit_cntr_ns = act_starve_limit_cntr_r + {{BM_CNT_WIDTH-1{1'b0}}, 1'b1}; end end else // Number of Bank Machs == 2 begin :BM_EQUAL_2 always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied) begin act_starve_limit_cntr_ns = act_starve_limit_cntr_r; if (~act_req) act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}}; else if (rts_act_denied && &act_starve_limit_cntr_r) act_starve_limit_cntr_ns = act_starve_limit_cntr_r + {1'b1}; end end endgenerate always @(posedge clk) act_starve_limit_cntr_r <= #TCQ act_starve_limit_cntr_ns; reg demand_act_priority_r; wire demand_act_priority_ns = act_req && (demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r)); always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns; `ifdef MC_SVA cover_demand_act_priority: cover property (@(posedge clk) (~rst && demand_act_priority_r)); `endif output wire demand_act_priority; assign demand_act_priority = demand_act_priority_r && ~sending_row; // compute act_demanded from other demand_act_priorities input [(nBANK_MACHS*2)-1:0] demand_act_priority_in; reg act_demanded = 1'b0; generate if (nBANK_MACHS > 1) begin : compute_act_demanded always @(demand_act_priority_in[`BM_SHARED_BV]) act_demanded = |demand_act_priority_in[`BM_SHARED_BV]; end endgenerate wire row_demand_ok = demand_act_priority_r || ~act_demanded; // Generate the Request To Send row arbitation signal. output wire rts_row; generate if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) assign rts_row = ~sending_row && row_demand_ok && (act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd); else assign rts_row = ~sending_row && row_demand_ok && ((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) || pre_request); endgenerate `ifdef MC_SVA four_activate_window_wait: cover property (@(posedge clk) (~rst && ~sending_row && act_req && my_inhbt_act_faw)); ras_ras_delay_wait: cover property (@(posedge clk) (~rst && ~sending_row && act_req && inhbt_act_rrd)); `endif // Provide rank machines early knowledge that this bank machine is // going to send an activate to the rank. In this way, the rank // machines just need to use the sending_row wire to figure out if // they need to keep track of the activate. output reg [RANKS-1:0] act_this_rank_r; reg [RANKS-1:0] act_this_rank_ns; always @(/*AS*/act_wait_r or req_rank_r) begin act_this_rank_ns = {RANKS{1'b0}}; for (i = 0; i < RANKS; i = i + 1) act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r); end always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns; // Generate request to send column command signal. input order_q_zero; wire req_bank_rdy_ns = order_q_zero && col_wait_r; reg req_bank_rdy_r; always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns; // Determine is we have been denied a column command request. input sent_col; wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col; // Implement a starvation limit counter. Count the number of times a // request to send a column command has been denied. localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS; localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT); reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r; reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns; always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r) if (~col_wait_r) starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}}; else if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1)) starve_limit_cntr_ns = starve_limit_cntr_r + {{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1}; else starve_limit_cntr_ns = starve_limit_cntr_r; always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns; input q_has_rd; input q_has_priority; // Decide if this bank machine should demand priority. Priority is demanded // when starvation limit counter is reached, or a bit in the request. wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) && rts_col_denied); input req_priority_r; input idle_ns; reg demand_priority_r; wire demand_priority_ns = ~idle_ns && col_wait_ns && (demand_priority_r || (order_q_zero && (req_priority_r || q_has_priority)) || (starved && (q_has_rd || ~req_wr_r))); always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns; `ifdef MC_SVA wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns && col_wait_ns; req_triggers_demand_priority: cover property (@(posedge clk) (rdy_for_priority && req_priority_r && ~q_has_priority && ~starved)); q_priority_triggers_demand_priority: cover property (@(posedge clk) (rdy_for_priority && ~req_priority_r && q_has_priority && ~starved)); wire not_req_or_q_rdy_for_priority = rdy_for_priority && ~req_priority_r && ~q_has_priority; starved_req_triggers_demand_priority: cover property (@(posedge clk) (not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r)); starved_q_triggers_demand_priority: cover property (@(posedge clk) (not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r)); `endif // compute demanded from other demand_priorities input [(nBANK_MACHS*2)-1:0] demand_priority_in; reg demanded = 1'b0; generate if (nBANK_MACHS > 1) begin : compute_demanded always @(demand_priority_in[`BM_SHARED_BV]) demanded = |demand_priority_in[`BM_SHARED_BV]; end endgenerate // In order to make sure that there is no starvation amongst a possibly // unlimited stream of priority requests, add a second stage to the demand // priority signal. If there are no other requests demanding priority, then // go ahead and assert demand_priority. If any other requests are asserting // demand_priority, hold off asserting demand_priority until these clear, then // assert demand priority. Its possible to get multiple requests asserting // demand priority simultaneously, but that's OK. Those requests will be // serviced, demanded will fall, and another group of requests will be // allowed to assert demand_priority. reg demanded_prior_r; wire demanded_prior_ns = demanded && (demanded_prior_r || ~demand_priority_r); always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns; output wire demand_priority; assign demand_priority = demand_priority_r && ~demanded_prior_r && ~sending_col; `ifdef MC_SVA demand_priority_gated: cover property (@(posedge clk) (demand_priority_r && ~demand_priority)); generate if (nBANK_MACHS >1) multiple_demand_priority: cover property (@(posedge clk) ($countones(demand_priority_in[`BM_SHARED_BV]) > 1)); endgenerate `endif wire demand_ok = demand_priority_r || ~demanded; // Figure out if the request in this bank machine matches the current rank // configuration. input rnk_config_strobe; input rnk_config_kill_rts_col; input rnk_config_valid_r; input [RANK_WIDTH-1:0] rnk_config; output wire rtc; wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r); assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok; // Using rank state provided by the rank machines, figure out if // a read requests should wait for WTR or RTW. input [RANKS-1:0] inhbt_rd; wire my_inhbt_rd = inhbt_rd[req_rank_r]; input [RANKS-1:0] inhbt_wr; wire my_inhbt_wr = inhbt_wr[req_rank_r]; wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd; // DQ bus timing constraints. input dq_busy_data; // Column command is ready to arbitrate, except for databus restrictions. wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) || (rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") || (rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) && order_q_zero; // Column command is ready to arbitrate for sending a write. Used // to generate early wr_data_addr for ECC mode. output wire col_rdy_wr; assign col_rdy_wr = col_rdy && ~rd_wr_r; // Figure out if we're ready to send a column command based on all timing // constraints. // if timing is an issue. wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match; `ifdef MC_SVA col_wait_for_order_q: cover property (@(posedge clk) (~rst && col_wait_r && ~order_q_zero && ~dq_busy_data && allow_rw)); col_wait_for_dq_busy: cover property (@(posedge clk) (~rst && col_wait_r && order_q_zero && dq_busy_data && allow_rw)); col_wait_for_allow_rw: cover property (@(posedge clk) (~rst && col_wait_r && order_q_zero && ~dq_busy_data && ~allow_rw)); `endif // Implement flow control for the command and control FIFOs and for the data // FIFO during writes input phy_mc_ctl_full; input phy_mc_cmd_full; input phy_mc_data_full; // Register ctl_full and cmd_full reg phy_mc_ctl_full_r = 1'b0; reg phy_mc_cmd_full_r = 1'b0; always @(posedge clk) if(rst) begin phy_mc_ctl_full_r <= #TCQ 1'b0; phy_mc_cmd_full_r <= #TCQ 1'b0; end else begin phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full; phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full; end // register output data pre-fifo almost full condition and fold in WR status reg ofs_rdy_r = 1'b0; always @(posedge clk) if(rst) ofs_rdy_r <= #TCQ 1'b0; else ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r); // Disable priority feature for one state after a config to insure // forward progress on the just installed io config. reg override_demand_r; wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col; always @(posedge clk) override_demand_r <= override_demand_ns; output wire rts_col; assign rts_col = ~sending_col && (demand_ok || override_demand_r) && col_cmd_rts && ofs_rdy_r; // As in act_this_rank, wr/rd_this_rank informs rank machines // that this bank machine is doing a write/rd. Removes logic // after the grant. reg [RANKS-1:0] wr_this_rank_ns; reg [RANKS-1:0] rd_this_rank_ns; always @(/*AS*/rd_wr_r or req_rank_r) begin wr_this_rank_ns = {RANKS{1'b0}}; rd_this_rank_ns = {RANKS{1'b0}}; for (i=0; i= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0 always @(posedge clk) offset_r1 <= #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr; end if(nPHY_WRLAT == 2) begin : offset_pipe_1 always @(posedge clk) offset_r2 <= #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1; end endgenerate output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1) ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0] : (EARLY_WR_DATA_ADDR == "OFF") ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0] : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0]; reg sent_col_r1; reg sent_col_r2; always @(posedge clk) sent_col_r1 <= #TCQ sent_col; always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1; wire wrdata_en = (nPHY_WRLAT == 0) ? (sent_col || |offset_r) & ~col_rd_wr : (nPHY_WRLAT == 1) ? (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 : //(nPHY_WRLAT >= 2) ? (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2; output wire mc_wrdata_en; assign mc_wrdata_en = wrdata_en; output wire wr_data_en; assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1) ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1) : ((sent_col || |offset_r) && ~col_rd_wr); input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; generate if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1 reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r; always @(posedge clk) col_wr_data_buf_addr_r <= #TCQ col_wr_data_buf_addr; assign wr_data_addr = col_wr_data_buf_addr_r; end else begin : delay_wr_data_cntrl_ne_1 assign wr_data_addr = col_wr_data_buf_addr; end endgenerate // CAS-RD to mc_rddata_en wire read_data_valid = (sent_col || |offset_r) && col_rd_wr; function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 // Implement FIFO that records reads as they are sent to the DRAM. // When phy_rddata_valid is returned some unknown time later, the // FIFO output is used to control how the data is interpreted. input phy_rddata_valid; output wire rd_rmw; output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; output reg ecc_status_valid; output reg wr_ecc_buf; output reg rd_data_end; output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; output reg rd_data_en /* synthesis syn_maxfan = 10 */; output col_read_fifo_empty; input col_periodic_rd; input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; input col_rmw; input [RANK_WIDTH-1:0] col_ra; input [BANK_WIDTH-1:0] col_ba; input [ROW_WIDTH-1:0] col_row; input [ROW_WIDTH-1:0] col_a; // Real column address (skip A10/AP and A12/BC#). The maximum width is 12; // the width will be tailored for the target DRAM downstream. wire [11:0] col_a_full; // Minimum row width is 12; take remaining 11 bits after omitting A10/AP assign col_a_full[10:0] = {col_a[11], col_a[9:0]}; // Get the 12th bit when row address width accommodates it; omit A12/BC# generate if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1 assign col_a_full[11] = col_a[13]; end else begin : COL_A_FULL_11_0 assign col_a_full[11] = 0; end endgenerate // Extract only the width of the target DRAM wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0]; localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH; localparam FIFO_WIDTH = 1 /*data_end*/ + 1 /*periodic_rd*/ + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + ((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH); localparam FULL_RAM_CNT = (FIFO_WIDTH/6); localparam REMAINDER = FIFO_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate begin : read_fifo wire [MC_ERR_LINE_WIDTH:0] ecc_line; if (CS_WIDTH == 1) assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted}; else assign ecc_line = {col_rmw, col_ra, col_ba, col_row, col_a_extracted}; wire [FIFO_WIDTH-1:0] real_fifo_data; if (ECC == "OFF") assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0]}; else assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0], ecc_line}; wire [RAM_WIDTH-1:0] fifo_in_data; if (REMAINDER == 0) assign fifo_in_data = real_fifo_data; else assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data}; wire [RAM_WIDTH-1:0] fifo_out_data_ns; reg [4:0] head_r; wire [4:0] head_ns = rst ? 5'b0 : read_data_valid ? (head_r + 5'b1) : head_r; always @(posedge clk) head_r <= #TCQ head_ns; reg [4:0] tail_r; wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid ? (tail_r + 5'b1) : tail_r; always @(posedge clk) tail_r <= #TCQ tail_ns; assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0; genvar i; for (i=0; iout delay(sim only) parameter ADDR_CMD_MODE = "1T", // registered or // 1Tfered mem? parameter BANK_WIDTH = 3, // bank address width parameter BM_CNT_WIDTH = 2, // # BM counter width // i.e., log2(nBANK_MACHS) parameter BURST_MODE = "8", // Burst length parameter CL = 5, // Read CAS latency // (in clk cyc) parameter CMD_PIPE_PLUS1 = "ON", // add register stage // between MC and PHY parameter COL_WIDTH = 12, // column address width parameter CS_WIDTH = 4, // # of unique CS outputs parameter CWL = 5, // Write CAS latency // (in clk cyc) parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g. // user src/dest buf addr) parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width parameter DATA_WIDTH = 64, // Data bus width parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", // Memory I/F type: // "DDR3", "DDR2" parameter ECC = "OFF", // ECC ON/OFF? parameter ECC_WIDTH = 8, // # of ECC bits parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps) parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits parameter nBANK_MACHS = 4, // # of bank machines (BM) parameter nCK_PER_CLK = 4, // DRAM clock : MC clock // frequency ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs // per rank parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in parameter nSLOTS = 1, // # DIMM slots in system parameter ORDERING = "NORM", // request ordering mode parameter PAYLOAD_WIDTH = 64, // Width of data payload // from PHY parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // row address width parameter RTT_NOM = "40", // Nominal ODT value parameter RTT_WR = "120", // Write ODT value parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0 parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1 parameter STARVE_LIMIT = 2, // max # of times a user // request is allowed to // lose arbitration when // reordering is enabled parameter tCK = 2500, // memory clk period(ps) parameter tCKE = 10000, // CKE minimum pulse (ps) parameter tFAW = 40000, // four activate window(ps) parameter tRAS = 37500, // ACT->PRE cmd period (ps) parameter tRCD = 12500, // ACT->R/W delay (ps) parameter tREFI = 7800000, // average periodic // refresh interval(ps) parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter tRFC = 110000, // REF->ACT/REF delay (ps) parameter tRP = 12500, // PRE cmd period (ps) parameter tRRD = 10000, // ACT->ACT period (ps) parameter tRTP = 7500, // Read->PRE cmd delay (ps) parameter tWTR = 7500, // Internal write->read // delay (ps) // requiring DLL lock (CKs) parameter tZQCS = 64, // ZQCS cmd period (CKs) parameter tZQI = 128_000_000, // ZQCS interval (ps) parameter tPRDI = 1_000_000, // pS parameter USER_REFRESH = "OFF" // Whether user manages REF ) ( // System inputs input clk, input rst, // Physical memory slot presence input [7:0] slot_0_present, input [7:0] slot_1_present, // Native Interface input [2:0] cmd, input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, input hi_priority, input size, input [BANK_WIDTH-1:0] bank, input [COL_WIDTH-1:0] col, input [RANK_WIDTH-1:0] rank, input [ROW_WIDTH-1:0] row, input use_addr, input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data, input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask, output accept, output accept_ns, output [BM_CNT_WIDTH-1:0] bank_mach_next, output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data, output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, output rd_data_en, output rd_data_end, output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */, output reg wr_data_en, output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */, output mc_read_idle, output mc_ref_zq_wip, // ECC interface input correct_en, input [2*nCK_PER_CLK-1:0] raw_not_ecc, input [DQS_WIDTH - 1:0] fi_xor_we, input [DQ_WIDTH -1 :0 ] fi_xor_wrdata, output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr, output [2*nCK_PER_CLK-1:0] ecc_single, output [2*nCK_PER_CLK-1:0] ecc_multiple, // User maintenance requests input app_periodic_rd_req, input app_ref_req, input app_zq_req, input app_sr_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // MC <==> PHY Interface output reg [nCK_PER_CLK-1:0] mc_ras_n, output reg [nCK_PER_CLK-1:0] mc_cas_n, output reg [nCK_PER_CLK-1:0] mc_we_n, output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output reg [1:0] mc_odt, output reg [nCK_PER_CLK-1:0] mc_cke, output wire mc_reset_n, output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask, output reg mc_wrdata_en, output wire mc_cmd_wren, output wire mc_ctl_wren, output reg [2:0] mc_cmd, output reg [5:0] mc_data_offset, output reg [5:0] mc_data_offset_1, output reg [5:0] mc_data_offset_2, output reg [1:0] mc_cas_slot, output reg [3:0] mc_aux_out0, output reg [3:0] mc_aux_out1, output reg [1:0] mc_rank_cnt, input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, input phy_rddata_valid, input init_calib_complete, input [6*RANKS-1:0] calib_rd_data_offset, input [6*RANKS-1:0] calib_rd_data_offset_1, input [6*RANKS-1:0] calib_rd_data_offset_2 ); assign mc_reset_n = 1'b1; // never reset memory assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle) assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle) // Ensure there is always at least one rank present during operation `ifdef MC_SVA ranks_present: assert property (@(posedge clk) (rst || (|(slot_0_present | slot_1_present)))); `endif // Reserved. Do not change. localparam nPHY_WRLAT = 2; // always delay write data control unless ECC mode is enabled localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1; // Ensure that write control is delayed for appropriate CWL /*`ifdef MC_SVA delay_wr_data_zero_CWL_le_6: assert property (@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0))); `endif*/ // Never retrieve WR_DATA_ADDR early localparam EARLY_WR_DATA_ADDR = "OFF"; //*************************************************************************** // Convert timing parameters from time to clock cycles //*************************************************************************** localparam nCKE = cdiv(tCKE, tCK); localparam nRP = cdiv(tRP, tCK); localparam nRCD = cdiv(tRCD, tCK); localparam nRAS = cdiv(tRAS, tCK); localparam nFAW = cdiv(tFAW, tCK); localparam nRFC = cdiv(tRFC, tCK); // Convert tWR. As per specification, write recover for autoprecharge // cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12 localparam nWR_CK = cdiv(15000, tCK) ; localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK; // tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2 localparam nRRD_CK = cdiv(tRRD, tCK); localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK : (nRRD_CK < 2) ? 2 : nRRD_CK; localparam nWTR_CK = cdiv(tWTR, tCK); localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK : (nWTR_CK < 2) ? 2 : nWTR_CK; localparam nRTP_CK = cdiv(tRTP, tCK); localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK : (nRTP_CK < 2) ? 2 : nRTP_CK; // Add a cycle to CL/CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL; // Tuneable delay between read and write data on the DQ bus localparam DQRD2DQWR_DLY = 4; // CKE minimum pulse width for self-refresh (SRE->SRX minimum time) localparam nCKESR = nCKE + 1; // Delay from SRE to command requiring locked DLL. Currently fixed at 512 for // all devices per JEDEC spec. localparam tXSDLL = 512; //*************************************************************************** // Set up maintenance counter dividers //*************************************************************************** // CK clock divisor to generate maintenance prescaler period (round down) localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK); // Maintenance prescaler divisor for refresh timer. Essentially, this is // just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst // case delay from the time we get a tick from the refresh counter to the // time that we can actually issue the REF command. Thus, subtract tRCD, CL, // data burst time and tRP for each implemented bank machine to ensure that // all transactions can complete before tREFI expires localparam REFRESH_TIMER_DIV = USER_REFRESH == "ON" ? 0 : (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD; // Periodic read (RESERVED - not currently required or supported in 7 series) // tPRDI should only be set to 0 // localparam tPRDI = 0; // Do NOT change. localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD; // Convert maintenance prescaler from ps to ns localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000; // Maintenance prescaler divisor for ZQ calibration (ZQCS) timer localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS; // Bus width required to broadcast a single bit rank signal among all the // bank machines - 1 bit per rank, per bank localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS; //*************************************************************************** // Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands //*************************************************************************** localparam EVEN_CWL_2T_MODE = ((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF"; //*************************************************************************** // Reserved feature control. //*************************************************************************** // Open page wait mode is reserved. // nOP_WAIT is the number of states a bank machine will park itself // on an otherwise inactive open page before closing the page. If // nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1, // the bank machine will remain parked until the pool of idle bank machines // are less than LOW_IDLE_CNT. At which point parked bank machines // are selected to exit until the number of idle bank machines exceeds the // LOW_IDLE_CNT. localparam nOP_WAIT = 0; // Open page mode localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold //*************************************************************************** // Internal wires //*************************************************************************** wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; wire [ROW_WIDTH-1:0] col_a; wire [BANK_WIDTH-1:0] col_ba; wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; wire col_periodic_rd; wire [RANK_WIDTH-1:0] col_ra; wire col_rmw; wire col_rd_wr; wire [ROW_WIDTH-1:0] col_row; wire col_size; wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; wire dq_busy_data; wire ecc_status_valid; wire [RANKS-1:0] inhbt_act_faw_r; wire [RANKS-1:0] inhbt_rd; wire [RANKS-1:0] inhbt_wr; wire insert_maint_r1; wire [RANK_WIDTH-1:0] maint_rank_r; wire maint_req_r; wire maint_wip_r; wire maint_zq_r; wire maint_sre_r; wire maint_srx_r; wire periodic_rd_ack_r; wire periodic_rd_r; wire [RANK_WIDTH-1:0] periodic_rd_rank_r; wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; wire rd_rmw; wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; wire [nBANK_MACHS-1:0] sending_col; wire [nBANK_MACHS-1:0] sending_row; wire sent_col; wire sent_col_r; wire wr_ecc_buf; wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // MC/PHY optional pipeline stage support wire [nCK_PER_CLK-1:0] mc_ras_n_ns; wire [nCK_PER_CLK-1:0] mc_cas_n_ns; wire [nCK_PER_CLK-1:0] mc_we_n_ns; wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns; wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns; wire [1:0] mc_odt_ns; wire [nCK_PER_CLK-1:0] mc_cke_ns; wire [3:0] mc_aux_out0_ns; wire [3:0] mc_aux_out1_ns; wire [1:0] mc_rank_cnt_ns = col_ra; wire [2:0] mc_cmd_ns; wire [5:0] mc_data_offset_ns; wire [5:0] mc_data_offset_1_ns; wire [5:0] mc_data_offset_2_ns; wire [1:0] mc_cas_slot_ns; wire mc_wrdata_en_ns; wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns; wire wr_data_en_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns; integer i; // MC Read idle support wire col_read_fifo_empty; wire mc_read_idle_ns; reg mc_read_idle_r; // MC Maintenance in progress with bus idle indication wire maint_ref_zq_wip; wire mc_ref_zq_wip_ns; reg mc_ref_zq_wip_r; //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Optional pipeline register stage on MC/PHY interface //*************************************************************************** generate if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface always @(posedge clk) begin mc_address <= #TCQ mc_address_ns; mc_bank <= #TCQ mc_bank_ns; mc_cas_n <= #TCQ mc_cas_n_ns; mc_cs_n <= #TCQ mc_cs_n_ns; mc_odt <= #TCQ mc_odt_ns; mc_cke <= #TCQ mc_cke_ns; mc_aux_out0 <= #TCQ mc_aux_out0_ns; mc_aux_out1 <= #TCQ mc_aux_out1_ns; mc_cmd <= #TCQ mc_cmd_ns; mc_ras_n <= #TCQ mc_ras_n_ns; mc_we_n <= #TCQ mc_we_n_ns; mc_data_offset <= #TCQ mc_data_offset_ns; mc_data_offset_1 <= #TCQ mc_data_offset_1_ns; mc_data_offset_2 <= #TCQ mc_data_offset_2_ns; mc_cas_slot <= #TCQ mc_cas_slot_ns; mc_wrdata_en <= #TCQ mc_wrdata_en_ns; mc_rank_cnt <= #TCQ mc_rank_cnt_ns; wr_data_addr <= #TCQ wr_data_addr_ns; wr_data_en <= #TCQ wr_data_en_ns; wr_data_offset <= #TCQ wr_data_offset_ns; end // always @ (posedge clk) end // block: cmd_pipe_plus else begin : cmd_pipe_plus0 // don't register interface always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or mc_odt_ns or mc_cke_ns or mc_data_offset_ns or mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or mc_cas_slot_ns) begin mc_address = #TCQ mc_address_ns; mc_bank = #TCQ mc_bank_ns; mc_cas_n = #TCQ mc_cas_n_ns; mc_cs_n = #TCQ mc_cs_n_ns; mc_odt = #TCQ mc_odt_ns; mc_cke = #TCQ mc_cke_ns; mc_aux_out0 = #TCQ mc_aux_out0_ns; mc_aux_out1 = #TCQ mc_aux_out1_ns; mc_cmd = #TCQ mc_cmd_ns; mc_ras_n = #TCQ mc_ras_n_ns; mc_we_n = #TCQ mc_we_n_ns; mc_data_offset = #TCQ mc_data_offset_ns; mc_data_offset_1 = #TCQ mc_data_offset_1_ns; mc_data_offset_2 = #TCQ mc_data_offset_2_ns; mc_cas_slot = #TCQ mc_cas_slot_ns; mc_wrdata_en = #TCQ mc_wrdata_en_ns; mc_rank_cnt = #TCQ mc_rank_cnt_ns; wr_data_addr = #TCQ wr_data_addr_ns; wr_data_en = #TCQ wr_data_en_ns; wr_data_offset = #TCQ wr_data_offset_ns; end // always @ (... end // block: cmd_pipe_plus0 endgenerate //*************************************************************************** // Indicate when there are no pending reads so that input features can be // powered down //*************************************************************************** assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete; always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns; assign mc_read_idle = mc_read_idle_r; //*************************************************************************** // Indicate when there is a refresh in progress and the bus is idle so that // tap adjustments can be made //*************************************************************************** assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty; always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns; assign mc_ref_zq_wip = mc_ref_zq_wip_r; //*************************************************************************** // Manage rank-level timing and maintanence //*************************************************************************** mig_7series_v4_0_rank_mach # ( // Parameters .BURST_MODE (BURST_MODE), .CL (CL), .CWL (CWL), .CS_WIDTH (CS_WIDTH), .DQRD2DQWR_DLY (DQRD2DQWR_DLY), .DRAM_TYPE (DRAM_TYPE), .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV), .nBANK_MACHS (nBANK_MACHS), .nCKESR (nCKESR), .nCK_PER_CLK (nCK_PER_CLK), .nFAW (nFAW), .nREFRESH_BANK (nREFRESH_BANK), .nRRD (nRRD), .nWTR (nWTR), .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV), .ZQ_TIMER_DIV (ZQ_TIMER_DIV) ) rank_mach0 ( // Outputs .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_ref_zq_wip (maint_ref_zq_wip), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), // Inputs .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .app_periodic_rd_req (app_periodic_rd_req), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .col_rd_wr (col_rd_wr), .clk (clk), .init_calib_complete (init_calib_complete), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .rst (rst), .sending_col (sending_col[nBANK_MACHS-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]) ); //*************************************************************************** // Manage requests, reordering and bank timing //*************************************************************************** mig_7series_v4_0_bank_mach # ( // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .CL (CL_M), .CWL (CWL_M), .CKE_ODT_AUX (CKE_ODT_AUX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nOP_WAIT (nOP_WAIT), .nRAS (nRAS), .nRCD (nRCD), .nRFC (nRFC), .nRP (nRP), .nRTP (nRTP), .nSLOTS (nSLOTS), .nWR (nWR), .nXSDLL (tXSDLL), .ORDERING (ORDERING), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .STARVE_LIMIT (STARVE_LIMIT), .tZQCS (tZQCS) ) bank_mach0 ( // Outputs .accept (accept), .accept_ns (accept_ns), .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank_ns), .mc_address (mc_address_ns), .mc_ras_n (mc_ras_n_ns), .mc_cas_n (mc_cas_n_ns), .mc_we_n (mc_we_n_ns), .mc_cs_n (mc_cs_n_ns), .mc_odt (mc_odt_ns), .mc_cke (mc_cke_ns), .mc_aux_out0 (mc_aux_out0_ns), .mc_aux_out1 (mc_aux_out1_ns), .mc_cmd (mc_cmd_ns), .mc_data_offset (mc_data_offset_ns), .mc_data_offset_1 (mc_data_offset_1_ns), .mc_data_offset_2 (mc_data_offset_2_ns), .mc_cas_slot (mc_cas_slot_ns), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]), // Inputs .bank (bank[BANK_WIDTH-1:0]), .calib_rddata_offset (calib_rd_data_offset), .calib_rddata_offset_1 (calib_rd_data_offset_1), .calib_rddata_offset_2 (calib_rd_data_offset_2), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .init_calib_complete (init_calib_complete), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .size (size), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .use_addr (use_addr) ); //*************************************************************************** // Manage DQ bus //*************************************************************************** mig_7series_v4_0_col_mach # ( // Parameters .TCQ (TCQ), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .nPHY_WRLAT (nPHY_WRLAT), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH) ) col_mach0 ( // Outputs .mc_wrdata_en (mc_wrdata_en_ns), .dq_busy_data (dq_busy_data), .ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]), .ecc_status_valid (ecc_status_valid), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_data_en (rd_data_en), .rd_data_end (rd_data_end), .rd_data_offset (rd_data_offset), .rd_rmw (rd_rmw), .wr_data_addr (wr_data_addr_ns), .wr_data_en (wr_data_en_ns), .wr_data_offset (wr_data_offset_ns), .wr_ecc_buf (wr_ecc_buf), .col_read_fifo_empty (col_read_fifo_empty), // Inputs .clk (clk), .rst (rst), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col) ); //*************************************************************************** // Implement ECC //*************************************************************************** // Total ECC word length = ECC code width + Data width localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH; generate if (ECC == "OFF") begin : ecc_off assign rd_data = phy_rd_data; assign mc_wrdata = wr_data; assign mc_wrdata_mask = wr_data_mask; assign ecc_single = 4'b0; assign ecc_multiple = 4'b0; end else begin : ecc_on wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i; // Merge and encode mig_7series_v4_0_ecc_merge_enc # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_merge_enc0 ( // Outputs .mc_wrdata (mc_wrdata_i), .mc_wrdata_mask (mc_wrdata_mask), // Inputs .clk (clk), .rst (rst), .h_rows (h_rows), .rd_merge_data (rd_merge_data), .raw_not_ecc (raw_not_ecc), .wr_data (wr_data), .wr_data_mask (wr_data_mask) ); // Decode and fix mig_7series_v4_0_ecc_dec_fix # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_dec_fix0 ( // Outputs .ecc_multiple (ecc_multiple), .ecc_single (ecc_single), .rd_data (rd_data), // Inputs .clk (clk), .rst (rst), .correct_en (correct_en), .phy_rddata (phy_rd_data), .ecc_status_valid (ecc_status_valid), .h_rows (h_rows) ); // ECC Buffer mig_7series_v4_0_ecc_buf # ( // Parameters .TCQ (TCQ), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DATA_WIDTH (DATA_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_buf0 ( // Outputs .rd_merge_data (rd_merge_data), // Inputs .clk (clk), .rst (rst), .rd_data (rd_data), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .wr_data_addr (wr_data_addr), .wr_data_offset (wr_data_offset), .wr_ecc_buf (wr_ecc_buf) ); // Generate ECC table mig_7series_v4_0_ecc_gen # ( // Parameters .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .ECC_WIDTH (ECC_WIDTH) ) ecc_gen0 ( // Outputs .h_rows (h_rows) ); if (ECC == "ON") begin : gen_fi_xor_inst reg mc_wrdata_en_r; wire mc_wrdata_en_i; always @(posedge clk) begin mc_wrdata_en_r <= mc_wrdata_en; end assign mc_wrdata_en_i = mc_wrdata_en_r; mig_7series_v4_0_fi_xor #( .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) fi_xor0 ( .clk (clk), .wrdata_in (mc_wrdata_i), .wrdata_out (mc_wrdata), .wrdata_en (mc_wrdata_en_i), .fi_xor_we (fi_xor_we), .fi_xor_wrdata (fi_xor_wrdata) ); end else begin : gen_wrdata_passthru assign mc_wrdata = mc_wrdata_i; end `ifdef DISPLAY_H_MATRIX integer i; always @(negedge rst) begin $display ("**********************************************"); $display ("H Matrix:"); for (i=0; iout delay (sim only) parameter BURST_MODE = "8", // Burst length parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay parameter CL = 5, // Read CAS latency parameter CWL = 5, // Write CAS latency parameter ID = 0, // Unique ID for each instance parameter nBANK_MACHS = 4, // # bank machines in MC parameter nCK_PER_CLK = 2, // DRAM clock : MC clock parameter nFAW = 30, // four activate window (CKs) parameter nREFRESH_BANK = 8, // # REF commands to pull-in parameter nRRD = 4, // ACT->ACT period (CKs) parameter nWTR = 4, // Internal write->read // delay (CKs) parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor // for periodic read timer parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a // single bit rank signal among // all the bank machines parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor // for refresh timer ) ( // Maintenance requests output periodic_rd_request, output wire refresh_request, // Inhibit signals output reg inhbt_act_faw_r, output reg inhbt_rd, output reg inhbt_wr, // System Inputs input clk, input rst, // User maintenance requests input app_periodic_rd_req, input app_ref_req, // Inputs input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, input clear_periodic_rd_request, input col_rd_wr, input init_calib_complete, input insert_maint_r1, input maint_prescaler_tick_r, input [RANK_WIDTH-1:0] maint_rank_r, input maint_zq_r, input maint_sre_r, input maint_srx_r, input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, input refresh_tick, input [nBANK_MACHS-1:0] sending_col, input [nBANK_MACHS-1:0] sending_row, input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r ); //*************************************************************************** // RRD configuration. The bank machines have a mechanism to prevent RAS to // RAS on adjacent fabric CLK states to the same rank. When // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit // is worked into the inhbt_faw signal. //*************************************************************************** localparam nADD_RRD = nRRD - ( (nCK_PER_CLK == 1) ? 2 : (nCK_PER_CLK == 2) ? 4 : /*(nCK_PER_CLK == 4)*/ 8 ); // divide by nCK_PER_CLK and add a cycle if there's a remainder localparam nRRD_CLKS = (nCK_PER_CLK == 1) ? nADD_RRD : (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) : /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0)); // take binary log to obtain counter width and add a tick for the idle cycle localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1); //*************************************************************************** // Internal signals //*************************************************************************** reg act_this_rank; integer i; // loop invariant //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 //*************************************************************************** // Determine if this rank has been activated. act_this_rank_r is a // registered bit vector from individual bank machines indicating the // corresponding bank machine is sending // an activate. Timing is improved with this method. //*************************************************************************** always @(/*AS*/act_this_rank_r or sending_row) begin act_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) act_this_rank = act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]); end reg add_rrd_inhbt = 1'b0; generate if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd1 else if (nADD_RRD > 0) begin :add_rdd0 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd0 endgenerate // Compute inhbt_act_faw_r. Only allow a limited number of activates // in a window. Both the number of activates and the window are // configurable. This depends on the RRD mechanism to prevent // two consecutive activates to the same rank. // // Subtract three from the specified nFAW. Subtract three because: // -Zero for the delay into the SRL is really one state. // -Sending_row is used to trigger the delay. Sending_row is one // state delayed from the arb. // -inhbt_act_faw_r is registered to make timing work, hence the // generation needs to be one state early. localparam nFAW_CLKS = (nCK_PER_CLK == 1) ? nFAW : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : ((nFAW/4) + ((nFAW%4) ? 1 : 0)); generate begin : inhbt_act_faw wire act_delayed; wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3; SRLC32E #(.INIT(32'h00000000) ) SRLC32E0 (.Q(act_delayed), // SRL data output .Q31(), // SRL cascade output pin .A(shift_depth), // 5-bit shift depth select input .CE(1'b1), // Clock enable input .CLK(clk), // Clock input .D(act_this_rank) // SRL data input ); reg [2:0] faw_cnt_ns; reg [2:0] faw_cnt_r; reg inhbt_act_faw_ns; always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt or faw_cnt_r or rst) begin if (rst) faw_cnt_ns = 3'b0; else begin faw_cnt_ns = faw_cnt_r; if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1; if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1; end inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt; end always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns; always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns; end // block: inhbt_act_faw endgenerate // In the DRAM spec, tWTR starts from CK following the end of the data // burst. Since we don't directly have that spec, the wtr timer is // based on when the CAS write command is sent to the DRAM. // // To compute the wtr timer value, first compute the time from the write command // to the read command. This is CWL + data_time + nWTR. // // Two is subtracted from the required wtr time since the timer // starts two states after the arbitration cycle. localparam ONE = 1; localparam TWO = 2; localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR; localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1) ? CASWR2CASRD : (nCK_PER_CLK == 2) ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) : ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0)); localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS); generate begin : wtr_timer reg write_this_rank; always @(/*AS*/sending_col or wr_this_rank_r) begin write_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) write_this_rank = write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]); end reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r; reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns; always @(/*AS*/rst or write_this_rank or wtr_cnt_r) if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}}; else begin wtr_cnt_ns = wtr_cnt_r; if (write_this_rank) wtr_cnt_ns = CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0]; else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0]; end wire inhbt_rd_ns = |wtr_cnt_ns; always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns; always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns; end endgenerate // In the DRAM spec (with AL = 0), the read-to-write command delay is implied to // be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the // read and write data do not collide on the DQ bus. The 2 tCK ensures a gap // between them. Here, we allow the user to tune this fixed term via the // DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating // this to the rank_common module, since this is a DQ/DQS bus-level requirement, // not a per-rank requirement. localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL; localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1) ? CASRD2CASWR : (nCK_PER_CLK == 2) ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) : ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0)); localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS); generate begin : rtw_timer reg read_this_rank; always @(/*AS*/sending_col or rd_this_rank_r) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r; reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns; always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r) if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}}; else begin rtw_cnt_ns = rtw_cnt_r; if (col_rd_wr && |sending_col) rtw_cnt_ns = CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0]; else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0]; end wire inhbt_wr_ns = |rtw_cnt_ns; always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns; always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns; end endgenerate // Refresh request generation. Implement a "refresh bank". Referred // to as pullin-in refresh in the JEDEC spec. // The refresh_rank_r counter increments when a refresh to this // rank has been decoded. In the up direction, the count saturates // at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK // is normally eight. The counter decrements with each refresh_tick, // saturating at zero. A refresh will be requests when the rank is // not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r // equals zero. localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1); generate begin : refresh_generation reg my_rank_busy; always @(/*AS*/rank_busy_r) begin my_rank_busy = 1'b0; for (i=0; i < nBANK_MACHS; i=i+1) my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID]; end wire my_refresh = insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r && (maint_rank_r == ID[RANK_WIDTH-1:0]); reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r; reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns; always @(/*AS*/app_ref_req or init_calib_complete or my_refresh or refresh_bank_r or refresh_tick) if (~init_calib_complete) if (REFRESH_TIMER_DIV == 0) refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]; else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}}; else case ({my_refresh, refresh_tick, app_ref_req}) 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r; 3'b010, 3'b001, 3'b011 : refresh_bank_ns = (|refresh_bank_r)? refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]: refresh_bank_r; 3'b100 : refresh_bank_ns = refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH]; endcase // case ({my_refresh, refresh_tick}) always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns; `ifdef MC_SVA refresh_bank_overflow: assert property (@(posedge clk) (rst || (refresh_bank_r <= nREFRESH_BANK))); refresh_bank_underflow: assert property (@(posedge clk) (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick))); refresh_hi_priority: cover property (@(posedge clk) (rst && ~|refresh_bank_ns && (refresh_bank_r == ONE[0+:REFRESH_BANK_WIDTH]))); refresh_bank_full: cover property (@(posedge clk) (rst && (refresh_bank_r == nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]))); `endif assign refresh_request = init_calib_complete && (~|refresh_bank_r || ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy)); end endgenerate // Periodic read request generation. localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1); generate begin : periodic_rd_generation if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads reg read_this_rank; always @(/*AS*/rd_this_rank_r or sending_col) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg read_this_rank_r; reg read_this_rank_r1; always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank; always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r; wire int_read_this_rank = read_this_rank && (((nCK_PER_CLK == 4) && read_this_rank_r) || ((nCK_PER_CLK != 4) && read_this_rank_r1)); reg periodic_rd_cntr1_ns; reg periodic_rd_cntr1_r; always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin periodic_rd_cntr1_ns = periodic_rd_cntr1_r; if (clear_periodic_rd_request) periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1; end always @(posedge clk) begin if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0; else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns; end reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r; reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns; wire periodic_rd_timer_one = maint_prescaler_tick_r && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); always @(/*AS*/init_calib_complete or maint_prescaler_tick_r or periodic_rd_timer_r or int_read_this_rank) begin periodic_rd_timer_ns = periodic_rd_timer_r; if (~init_calib_complete) periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; //periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}}; else if (int_read_this_rank || periodic_rd_timer_one) periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; else if (|periodic_rd_timer_r && maint_prescaler_tick_r) periodic_rd_timer_ns = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH]; end always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns; reg periodic_rd_request_r; wire periodic_rd_request_ns = ~rst && ((app_periodic_rd_req && init_calib_complete) || ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) || // (~(read_this_rank || clear_periodic_rd_request) && (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) && (periodic_rd_request_r || periodic_rd_timer_one))); always @(posedge clk) periodic_rd_request_r <= #TCQ periodic_rd_request_ns; `ifdef MC_SVA read_clears_periodic_rd_request: cover property (@(posedge clk) (rst && (periodic_rd_request_r && read_this_rank))); `endif assign periodic_rd_request = init_calib_complete && periodic_rd_request_r; end else assign periodic_rd_request = 1'b0; //to disable periodic reads end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_common.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_common.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Block for logic common to all rank machines. Contains // a clock prescaler, and arbiters for refresh and periodic // read functions. `timescale 1 ps / 1 ps module mig_7series_v4_0_rank_common # ( parameter TCQ = 100, parameter DRAM_TYPE = "DDR3", parameter MAINT_PRESCALER_DIV = 40, parameter nBANK_MACHS = 4, parameter nCKESR = 4, parameter nCK_PER_CLK = 2, parameter PERIODIC_RD_TIMER_DIV = 20, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter REFRESH_TIMER_DIV = 39, parameter ZQ_TIMER_DIV = 640000 ) (/*AUTOARG*/ // Outputs maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r, maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r, periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip, // Inputs clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req, insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present, periodic_rd_request, periodic_rd_ack_r ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; // Maintenance and periodic read prescaler. Nominally 200 nS. localparam ONE = 1; localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1); input init_calib_complete; reg maint_prescaler_tick_r_lcl; generate begin : maint_prescaler reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r; reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns; wire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]); always @(/*AS*/init_calib_complete or maint_prescaler_r or maint_prescaler_tick_ns) begin maint_prescaler_ns = maint_prescaler_r; if (~init_calib_complete || maint_prescaler_tick_ns) maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0]; else if (|maint_prescaler_r) maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0]; end always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns; always @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns; end endgenerate output wire maint_prescaler_tick_r; assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl; // Refresh timebase. Nominically 7800 nS. localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1); wire refresh_tick_lcl; generate begin : refresh_timer reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r; reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or refresh_tick_lcl or refresh_timer_r) begin refresh_timer_ns = refresh_timer_r; if (~init_calib_complete || refresh_tick_lcl) refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0]; else if (|refresh_timer_r && maint_prescaler_tick_r_lcl) refresh_timer_ns = refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0]; end always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns; assign refresh_tick_lcl = (refresh_timer_r == ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl; end endgenerate output wire refresh_tick; assign refresh_tick = refresh_tick_lcl; // ZQ timebase. Nominally 128 mS localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1); input app_zq_req; input insert_maint_r1; reg maint_zq_r_lcl; reg zq_request = 1'b0; generate if (DRAM_TYPE == "DDR3") begin : zq_cntrl reg zq_tick = 1'b0; if (ZQ_TIMER_DIV !=0) begin : zq_timer reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r; reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or zq_tick or zq_timer_r) begin zq_timer_ns = zq_timer_r; if (~init_calib_complete || zq_tick) zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0]; else if (|zq_timer_r && maint_prescaler_tick_r_lcl) zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0]; end always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns; always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r) zq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl); end // zq_timer // ZQ request. Set request with timer tick, and when exiting PHY init. Never // request if ZQ_TIMER_DIV == 0. begin : zq_request_logic wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl; reg zq_request_r; wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") && ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) || (zq_request_r && ~zq_clears_zq_request) || zq_tick || (app_zq_req && init_calib_complete)); always @(posedge clk) zq_request_r <= #TCQ zq_request_ns; always @(/*AS*/init_calib_complete or zq_request_r) zq_request = init_calib_complete && zq_request_r; end // zq_request_logic end endgenerate // Self-refresh control localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0); localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1); input app_sr_req; reg maint_sre_r_lcl; reg maint_srx_r_lcl; reg sre_request = 1'b0; wire inhbt_srx; generate begin : sr_cntrl // SRE request. Set request with user request. begin : sre_request_logic reg sre_request_r; wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl; wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request) || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl)); always @(posedge clk) sre_request_r <= #TCQ sre_request_ns; always @(init_calib_complete or sre_request_r) sre_request = init_calib_complete && sre_request_r; end // sre_request_logic // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR begin : ckesr_timer reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}}; reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}}; always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin ckesr_timer_ns = ckesr_timer_r; if (insert_maint_r1 && maint_sre_r_lcl) ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0]; else if(|ckesr_timer_r) ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0]; end always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns; assign inhbt_srx = |ckesr_timer_r; end // ckesr_timer end endgenerate // DRAM maintenance operations of refresh and ZQ calibration, and self-refresh // DRAM maintenance operations and self-refresh have their own channel in the // queue. There is also a single, very simple bank machine // dedicated to these operations. Its assumed that the // maintenance operations can be completed quickly enough // to avoid any queuing. // // ZQ, refresh and self-refresh requests share a channel into controller. // Self-refresh is appended to the uppermost bit of the request bus and ZQ is // appended just below that. input[RANKS-1:0] refresh_request; input maint_wip_r; reg maint_req_r_lcl; reg [RANK_WIDTH-1:0] maint_rank_r_lcl; input [7:0] slot_0_present; input [7:0] slot_1_present; generate begin : maintenance_request // Maintenance request pipeline. reg upd_last_master_r; reg new_maint_rank_r; wire maint_busy = upd_last_master_r || new_maint_rank_r || maint_req_r_lcl || maint_wip_r; wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]}; //wire upd_last_master_ns = |maint_request && ~maint_busy; wire upd_last_master_ns = |maint_request && ~maint_wip_r; always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r; always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r; wire upd_last_master_pls = upd_last_master_r & (~new_maint_rank_r); // Arbitrate maintenance requests. wire [RANKS+1:0] maint_grant_ns; wire [RANKS+1:0] maint_grant_r; mig_7series_v4_0_round_robin_arb # (.WIDTH (RANKS+2)) maint_arb0 (.grant_ns (maint_grant_ns), .grant_r (maint_grant_r), .upd_last_master (upd_last_master_pls), .current_master (maint_grant_r), .req (maint_request), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // Look at arbitration results. Decide if ZQ, refresh or self-refresh. // If refresh select the maintenance rank from the winning rank controller. // If ZQ or self-refresh, generate a sequence of rank numbers corresponding to // slots populated maint_rank_r is not used for comparisons in the queue for ZQ // or self-refresh requests. The bank machine will enable CS for the number of // states equal to the the number of occupied slots. This will produce a // command to every occupied slot, but not in any particular order. wire [7:0] present = slot_0_present | slot_1_present; integer i; reg [RANK_WIDTH-1:0] maint_rank_ns; wire maint_zq_ns = ~rst && (upd_last_master_pls ? maint_grant_r[RANKS] : maint_zq_r_lcl); wire maint_srx_ns = ~rst && (maint_sre_r_lcl ? ~app_sr_req & ~inhbt_srx : maint_srx_r_lcl && upd_last_master_pls ? maint_grant_r[RANKS+1] : maint_srx_r_lcl); wire maint_sre_ns = ~rst && (upd_last_master_pls ? maint_grant_r[RANKS+1] : maint_sre_r_lcl && ~maint_srx_ns); always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns or maint_sre_ns or maint_srx_ns or present or rst or upd_last_master_pls) begin if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}}; else begin maint_rank_ns = maint_rank_r_lcl; if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0]; for (i=0; i<8; i=i+1) if (~present[maint_rank_ns]) maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0]; end else if (upd_last_master_pls) for (i=0; i= 1. parameter C_S_AXI_MEM_SIZE = "1073741824", // Address Space required for this component parameter C_S_AXI_ADDR_WIDTH = 30, // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and // M_AXI_ARADDR for all SI/MI slots. // # = 32. parameter C_S_AXI_DATA_WIDTH = 256, // Width of WDATA and RDATA on SI slot. // Must be <= APP_DATA_WIDTH. // # = 32, 64, 128, 256. parameter C_MC_nCK_PER_CLK = 4, // Indicates whether to instatiate upsizer // Range: 0, 1 parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0, // Indicates whether to instatiate upsizer // Range: 0, 1 parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG_STARVE_LIMIT", // Indicates the Arbitration // Allowed values - "TDM", "ROUND_ROBIN", // "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT" // "WRITE_PRIORITY", "WRITE_PRIORITY_REG" parameter C_S_AXI_REG_EN0 = 20'h00000, // C_S_AXI_REG_EN0[00] = Reserved // C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE parameter C_S_AXI_REG_EN1 = 20'h00000, // Instatiates register slices after the upsizer. // The type of register is specified for each channel // in a vector. 4 bits per channel are used. // C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE // Possible values for each channel are: // // 0 => BYPASS = The channel is just wired through the // module. // 1 => FWD = The master VALID and payload signals // are registrated. // 2 => REV = The slave ready signal is registrated // 3 => FWD_REV = Both FWD and REV // 4 => SLAVE_FWD = All slave side signals and master // VALID and payload are registrated. // 5 => SLAVE_RDY = All slave side signals and master // READY are registrated. // 6 => INPUTS = Slave and Master side inputs are // registrated. // 7 => ADDRESS = Optimized for address channel parameter C_S_AXI_CTRL_ADDR_WIDTH = 32, // Width of AXI-4-Lite address bus parameter C_S_AXI_CTRL_DATA_WIDTH = 32, // Width of AXI-4-Lite data buses parameter C_S_AXI_BASEADDR = 32'h0000_0000, // Base address of AXI4 Memory Mapped bus. parameter C_ECC_ONOFF_RESET_VALUE = 1, // Controls ECC on/off value at startup/reset parameter C_ECC_CE_COUNTER_WIDTH = 8, // The external memory to controller clock ratio. //*************************************************************************** // Debug parameters //*************************************************************************** parameter DEBUG_PORT = "OFF", // # = "ON" Enable debug signals/controls. // = "OFF" Disable debug signals/controls. //*************************************************************************** // Temparature monitor parameter //*************************************************************************** parameter TEMP_MON_CONTROL = "INTERNAL", // # = "INTERNAL", "EXTERNAL" //*************************************************************************** // FPGA Voltage Type parameter //*************************************************************************** parameter FPGA_VOLT_TYPE = "N", // # = "L", "N". When FPGA VccINT is 0.9v, // the value is "L", else it is "N" parameter RST_ACT_LOW = 1 // =1 for active low reset, // =0 for active high. ) ( // Inouts inout [DQ_WIDTH-1:0] ddr3_dq, inout [DQS_WIDTH-1:0] ddr3_dqs_n, inout [DQS_WIDTH-1:0] ddr3_dqs_p, // Outputs output [ROW_WIDTH-1:0] ddr3_addr, output [BANK_WIDTH-1:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [CK_WIDTH-1:0] ddr3_ck_p, output [CK_WIDTH-1:0] ddr3_ck_n, output [CKE_WIDTH-1:0] ddr3_cke, output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n, output [DM_WIDTH-1:0] ddr3_dm, output [ODT_WIDTH-1:0] ddr3_odt, // Inputs // Single-ended system clock input sys_clk_i, // user interface signals output ui_clk, output ui_clk_sync_rst, output mmcm_locked, input aresetn, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // Slave Interface Write Address Ports input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid, input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input [0:0] s_axi_awlock, input [3:0] s_axi_awcache, input [2:0] s_axi_awprot, input [3:0] s_axi_awqos, input s_axi_awvalid, output s_axi_awready, // Slave Interface Write Data Ports input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata, input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, // Slave Interface Write Response Ports input s_axi_bready, output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, // Slave Interface Read Address Ports input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid, input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input [0:0] s_axi_arlock, input [3:0] s_axi_arcache, input [2:0] s_axi_arprot, input [3:0] s_axi_arqos, input s_axi_arvalid, output s_axi_arready, // Slave Interface Read Data Ports input s_axi_rready, output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, output init_calib_complete, output [11:0] device_temp, `ifdef SKIP_CALIB output calib_tap_req, input calib_tap_load, input [6:0] calib_tap_addr, input [7:0] calib_tap_val, input calib_tap_load_done, `endif // System reset - Default polarity of sys_rst pin is Active Low. // System reset polarity will change based on the option // selected in GUI. input sys_rst ); function integer clogb2 (input integer size); begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS); localparam RANK_WIDTH = clogb2(RANKS); localparam ECC_WIDTH = (ECC == "OFF")? 0 : (DATA_WIDTH <= 4)? 4 : (DATA_WIDTH <= 10)? 5 : (DATA_WIDTH <= 26)? 6 : (DATA_WIDTH <= 57)? 7 : (DATA_WIDTH <= 120)? 8 : (DATA_WIDTH <= 247)? 9 : 10; localparam DATA_BUF_OFFSET_WIDTH = 1; localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + BANK_WIDTH + ROW_WIDTH + COL_WIDTH + DATA_BUF_OFFSET_WIDTH; localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH; localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8; localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF"; // Enable or disable the temp monitor module localparam tTEMPSAMPLE = 10000000; // sample every 10 us localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock `ifdef SKIP_CALIB localparam SKIP_CALIB = "TRUE"; `else localparam SKIP_CALIB = "FALSE"; `endif localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK; // Wire declarations wire [BM_CNT_WIDTH-1:0] bank_mach_next; wire clk; wire [1:0] clk_ref; wire [1:0] iodelay_ctrl_rdy; wire clk_ref_in; wire sys_rst_o; wire clk_div2; wire rst_div2; wire freq_refclk ; wire mem_refclk ; wire pll_lock ; wire sync_pulse; wire mmcm_ps_clk; wire poc_sample_pd; wire psen; wire psincdec; wire psdone; wire iddr_rst; wire ref_dll_lock; wire rst_phaser_ref; wire pll_locked; wire rst; wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; wire ddr3_parity; // AXI CTRL port wire s_axi_ctrl_awvalid; wire s_axi_ctrl_awready; wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr; // Slave Interface Write Data Ports wire s_axi_ctrl_wvalid; wire s_axi_ctrl_wready; wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata; // Slave Interface Write Response Ports wire s_axi_ctrl_bvalid; wire s_axi_ctrl_bready; wire [1:0] s_axi_ctrl_bresp; // Slave Interface Read Address Ports wire s_axi_ctrl_arvalid; wire s_axi_ctrl_arready; wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr; // Slave Interface Read Data Ports wire s_axi_ctrl_rvalid; wire s_axi_ctrl_rready; wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata; wire [1:0] s_axi_ctrl_rresp; // Interrupt output wire interrupt; wire sys_clk_p; wire sys_clk_n; wire mmcm_clk; wire clk_ref_p; wire clk_ref_n; wire clk_ref_i; wire [11:0] device_temp_i; // Debug port signals wire dbg_idel_down_all; wire dbg_idel_down_cpt; wire dbg_idel_up_all; wire dbg_idel_up_cpt; wire dbg_sel_all_idel_cpt; wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt; wire dbg_sel_pi_incdec; wire [DQS_CNT_WIDTH:0] dbg_byte_sel; wire dbg_pi_f_inc; wire dbg_pi_f_dec; wire [5:0] dbg_pi_counter_read_val; wire [8:0] dbg_po_counter_read_val; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt; wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt; wire [255:0] dbg_calib_top; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt; wire [(6*RANKS)-1:0] dbg_rd_data_offset; wire [255:0] dbg_phy_rdlvl; wire [99:0] dbg_phy_wrcal; wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt; wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt; wire [255:0] dbg_phy_wrlvl; wire [255:0] dbg_phy_init; wire [255:0] dbg_prbs_rdlvl; wire [255:0] dbg_dqs_found_cal; wire dbg_pi_phaselock_start; wire dbg_pi_phaselocked_done; wire dbg_pi_phaselock_err; wire dbg_pi_dqsfound_start; wire dbg_pi_dqsfound_done; wire dbg_pi_dqsfound_err; wire dbg_wrcal_start; wire dbg_wrcal_done; wire dbg_wrcal_err; wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes; wire [11:0] dbg_pi_phase_locked_phy4lanes; wire dbg_oclkdelay_calib_start; wire dbg_oclkdelay_calib_done; wire [255:0] dbg_phy_oclkdelay_cal; wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data; wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect; wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata; wire dbg_rddata_valid; wire [1:0] dbg_rdlvl_done; wire [1:0] dbg_rdlvl_err; wire [1:0] dbg_rdlvl_start; wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt; wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt; wire [5:0] dbg_tap_cnt_during_wrlvl; wire dbg_wl_edge_detect_valid; wire dbg_wrlvl_done; wire dbg_wrlvl_err; wire dbg_wrlvl_start; reg [63:0] dbg_rddata_r; reg dbg_rddata_valid_r; wire [53:0] ocal_tap_cnt; wire [4:0] dbg_dqs; wire [8:0] dbg_bit; wire [8:0] rd_data_edge_detect_r; wire [53:0] wl_po_fine_cnt; wire [26:0] wl_po_coarse_cnt; wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1; wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2; wire [5:0] dbg_data_offset; wire [5:0] dbg_data_offset_1; wire [5:0] dbg_data_offset_2; wire [390:0] ddr3_ila_wrpath_int; wire [1023:0] ddr3_ila_rdpath_int; wire [119:0] ddr3_ila_basic_int; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int; //*************************************************************************** assign ui_clk = clk; assign ui_clk_sync_rst = rst; assign sys_clk_p = 1'b0; assign sys_clk_n = 1'b0; assign clk_ref_i = 1'b0; generate if (REFCLK_TYPE == "USE_SYSTEM_CLOCK") assign clk_ref_in = mmcm_clk; else assign clk_ref_in = clk_ref_i; endgenerate mig_7series_v4_0_iodelay_ctrl # ( .TCQ (TCQ), .IODELAY_GRP0 (IODELAY_GRP0), .IODELAY_GRP1 (IODELAY_GRP1), .REFCLK_TYPE (REFCLK_TYPE), .SYSCLK_TYPE (SYSCLK_TYPE), .SYS_RST_PORT (SYS_RST_PORT), .RST_ACT_LOW (RST_ACT_LOW), .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL) ) u_iodelay_ctrl ( // Outputs .iodelay_ctrl_rdy (iodelay_ctrl_rdy), .sys_rst_o (sys_rst_o), .clk_ref (clk_ref), // Inputs .clk_ref_p (clk_ref_p), .clk_ref_n (clk_ref_n), .clk_ref_i (clk_ref_in), .sys_rst (sys_rst) ); mig_7series_v4_0_clk_ibuf # ( .SYSCLK_TYPE (SYSCLK_TYPE), .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK) ) u_ddr3_clk_ibuf ( .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .sys_clk_i (sys_clk_i), .mmcm_clk (mmcm_clk) ); // Temperature monitoring logic generate if (TEMP_MON_EN == "ON") begin: temp_mon_enabled mig_7series_v4_0_tempmon # ( .TCQ (TCQ), .TEMP_MON_CONTROL (TEMP_MON_CONTROL), .XADC_CLK_PERIOD (XADC_CLK_PERIOD), .tTEMPSAMPLE (tTEMPSAMPLE) ) u_tempmon ( .clk (clk), .xadc_clk (clk_ref[0]), .rst (rst), .device_temp_i (device_temp_i), .device_temp (device_temp) ); end else begin: temp_mon_disabled assign device_temp = 'b0; end endgenerate mig_7series_v4_0_infrastructure # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLKIN_PERIOD (CLKIN_PERIOD), .SYSCLK_TYPE (SYSCLK_TYPE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), .MMCM_VCO (MMCM_VCO), .MMCM_MULT_F (MMCM_MULT_F), .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .RST_ACT_LOW (RST_ACT_LOW), .tCK (tCK), .MEM_TYPE (DRAM_TYPE) ) u_ddr3_infrastructure ( // Outputs .rstdiv0 (rst), .clk (clk), .clk_div2 (clk_div2), .rst_div2 (rst_div2), .mem_refclk (mem_refclk), .freq_refclk (freq_refclk), .sync_pulse (sync_pulse), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .iddr_rst (iddr_rst), // .auxout_clk (), .ui_addn_clk_0 (), .ui_addn_clk_1 (), .ui_addn_clk_2 (), .ui_addn_clk_3 (), .ui_addn_clk_4 (), .pll_locked (pll_locked), .mmcm_locked (mmcm_locked), .rst_phaser_ref (rst_phaser_ref), // Inputs .psen (psen), .psincdec (psincdec), .mmcm_clk (mmcm_clk), .sys_rst (sys_rst_o), .iodelay_ctrl_rdy (iodelay_ctrl_rdy), .ref_dll_lock (ref_dll_lock) ); mig_7series_v4_0_memc_ui_top_axi # ( .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .AL (AL), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .CA_MIRROR (CA_MIRROR), .DDR3_VDD_OP_VOLT (VDD_OP_VOLT), .CK_WIDTH (CK_WIDTH), .COL_WIDTH (COL_WIDTH), .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), .CS_WIDTH (CS_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .CKE_WIDTH (CKE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DM_WIDTH (DM_WIDTH), .DQ_CNT_WIDTH (DQ_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), .ECC (ECC), .ECC_WIDTH (ECC_WIDTH), .ECC_TEST (ECC_TEST), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .REFCLK_FREQ (REFCLK_FREQ), .nAL (nAL), .nBANK_MACHS (nBANK_MACHS), .CKE_ODT_AUX (CKE_ODT_AUX), .nCK_PER_CLK (nCK_PER_CLK), .ORDERING (ORDERING), .OUTPUT_DRV (OUTPUT_DRV), .IBUF_LPWR_MODE (IBUF_LPWR_MODE), .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .IODELAY_GRP0 (IODELAY_GRP0), .IODELAY_GRP1 (IODELAY_GRP1), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .REG_CTRL (REG_CTRL), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .CL (CL), .CWL (CWL), .tCK (tCK), .tCKE (tCKE), .tFAW (tFAW), .tPRDI (tPRDI), .tRAS (tRAS), .tRCD (tRCD), .tREFI (tREFI), .tRFC (tRFC), .tRP (tRP), .tRRD (tRRD), .tRTP (tRTP), .tWTR (tWTR), .tZQI (tZQI), .tZQCS (tZQCS), .USER_REFRESH (USER_REFRESH), .TEMP_MON_EN (TEMP_MON_EN), .WRLVL (WRLVL), .DEBUG_PORT (DEBUG_PORT), .CAL_WIDTH (CAL_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .ADDR_WIDTH (ADDR_WIDTH), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .MEM_ADDR_ORDER (MEM_ADDR_ORDER), .STARVE_LIMIT (STARVE_LIMIT), .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH), .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST), .C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM), .C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0), .C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1), .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH), .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH), .C_S_AXI_BASEADDR (C_S_AXI_BASEADDR), .C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE), .C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH), .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK), .TAPSPERKCLK (TAPSPERKCLK), .SKIP_CALIB (SKIP_CALIB), .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) ) u_memc_ui_top_axi ( .clk (clk), .clk_div2 (clk_div2), .rst_div2 (rst_div2), .clk_ref (clk_ref), .mem_refclk (mem_refclk), //memory clock .freq_refclk (freq_refclk), .pll_lock (pll_locked), .sync_pulse (sync_pulse), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .iddr_rst (iddr_rst), .psen (psen), .psincdec (psincdec), .rst (rst), .rst_phaser_ref (rst_phaser_ref), .ref_dll_lock (ref_dll_lock), // Memory interface ports .ddr_dq (ddr3_dq), .ddr_dqs_n (ddr3_dqs_n), .ddr_dqs (ddr3_dqs_p), .ddr_addr (ddr3_addr), .ddr_ba (ddr3_ba), .ddr_cas_n (ddr3_cas_n), .ddr_ck_n (ddr3_ck_n), .ddr_ck (ddr3_ck_p), .ddr_cke (ddr3_cke), .ddr_cs_n (ddr3_cs_n), .ddr_dm (ddr3_dm), .ddr_odt (ddr3_odt), .ddr_ras_n (ddr3_ras_n), .ddr_reset_n (ddr3_reset_n), .ddr_parity (ddr3_parity), .ddr_we_n (ddr3_we_n), .bank_mach_next (bank_mach_next), // Application interface ports .app_ecc_multiple_err_o (), .app_ecc_single_err (), .device_temp (device_temp), // skip calibration ports `ifdef SKIP_CALIB .calib_tap_req (calib_tap_req), .calib_tap_load (calib_tap_load), .calib_tap_addr (calib_tap_addr), .calib_tap_val (calib_tap_val), .calib_tap_load_done (calib_tap_load_done), `else .calib_tap_req (), .calib_tap_load (1'b0), .calib_tap_addr (7'b0), .calib_tap_val (8'b0), .calib_tap_load_done (1'b0), `endif // Debug logic ports .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_sel_pi_incdec (dbg_sel_pi_incdec), .dbg_sel_po_incdec (dbg_sel_po_incdec), .dbg_byte_sel (dbg_byte_sel), .dbg_pi_f_inc (dbg_pi_f_inc), .dbg_pi_f_dec (dbg_pi_f_dec), .dbg_po_f_inc (dbg_po_f_inc), .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), .dbg_po_f_dec (dbg_po_f_dec), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_calib_top (dbg_calib_top), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_rd_data_offset (dbg_rd_data_offset), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_rddata (dbg_rddata), .dbg_rddata_valid (dbg_rddata_valid), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_phy_wrlvl (dbg_phy_wrlvl), .dbg_phy_init (dbg_phy_init), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .dbg_pi_counter_read_val (dbg_pi_counter_read_val), .dbg_po_counter_read_val (dbg_po_counter_read_val), .dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int), .dbg_pi_phaselock_start (dbg_pi_phaselock_start), .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), .dbg_pi_phaselock_err (dbg_pi_phaselock_err), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), .dbg_data_offset (dbg_data_offset), .dbg_data_offset_1 (dbg_data_offset_1), .dbg_data_offset_2 (dbg_data_offset_2), .dbg_wrcal_start (dbg_wrcal_start), .dbg_wrcal_done (dbg_wrcal_done), .dbg_wrcal_err (dbg_wrcal_err), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), .dbg_dqs_found_cal (dbg_dqs_found_cal), .aresetn (aresetn), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), // Slave Interface Write Address Ports .s_axi_awid (s_axi_awid), .s_axi_awaddr (s_axi_awaddr), .s_axi_awlen (s_axi_awlen), .s_axi_awsize (s_axi_awsize), .s_axi_awburst (s_axi_awburst), .s_axi_awlock (s_axi_awlock), .s_axi_awcache (s_axi_awcache), .s_axi_awprot (s_axi_awprot), .s_axi_awqos (s_axi_awqos), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), // Slave Interface Write Data Ports .s_axi_wdata (s_axi_wdata), .s_axi_wstrb (s_axi_wstrb), .s_axi_wlast (s_axi_wlast), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), // Slave Interface Write Response Ports .s_axi_bid (s_axi_bid), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), // Slave Interface Read Address Ports .s_axi_arid (s_axi_arid), .s_axi_araddr (s_axi_araddr), .s_axi_arlen (s_axi_arlen), .s_axi_arsize (s_axi_arsize), .s_axi_arburst (s_axi_arburst), .s_axi_arlock (s_axi_arlock), .s_axi_arcache (s_axi_arcache), .s_axi_arprot (s_axi_arprot), .s_axi_arqos (s_axi_arqos), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), // Slave Interface Read Data Ports .s_axi_rid (s_axi_rid), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rlast (s_axi_rlast), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready), // AXI CTRL port .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid), .s_axi_ctrl_awready (s_axi_ctrl_awready), .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr), // Slave Interface Write Data Ports .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid), .s_axi_ctrl_wready (s_axi_ctrl_wready), .s_axi_ctrl_wdata (s_axi_ctrl_wdata), // Slave Interface Write Response Ports .s_axi_ctrl_bvalid (s_axi_ctrl_bvalid), .s_axi_ctrl_bready (s_axi_ctrl_bready), .s_axi_ctrl_bresp (s_axi_ctrl_bresp), // Slave Interface Read Address Ports .s_axi_ctrl_arvalid (s_axi_ctrl_arvalid), .s_axi_ctrl_arready (s_axi_ctrl_arready), .s_axi_ctrl_araddr (s_axi_ctrl_araddr), // Slave Interface Read Data Ports .s_axi_ctrl_rvalid (s_axi_ctrl_rvalid), .s_axi_ctrl_rready (s_axi_ctrl_rready), .s_axi_ctrl_rdata (s_axi_ctrl_rdata), .s_axi_ctrl_rresp (s_axi_ctrl_rresp), // Interrupt output .interrupt (interrupt), .init_calib_complete (init_calib_complete), .dbg_poc () ); //********************************************************************* // Resetting all RTL debug inputs as the debug ports are not enabled //********************************************************************* assign dbg_idel_down_all = 1'b0; assign dbg_idel_down_cpt = 1'b0; assign dbg_idel_up_all = 1'b0; assign dbg_idel_up_cpt = 1'b0; assign dbg_sel_all_idel_cpt = 1'b0; assign dbg_sel_idel_cpt = 'b0; assign dbg_byte_sel = 'd0; assign dbg_sel_pi_incdec = 1'b0; assign dbg_pi_f_inc = 1'b0; assign dbg_pi_f_dec = 1'b0; assign dbg_po_f_inc = 'b0; assign dbg_po_f_dec = 'b0; assign dbg_po_f_stg23_sel = 'b0; assign dbg_sel_po_incdec = 'b0; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ddr3_if_mig_sim.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 4.0 // \ \ Application : MIG // / / Filename : ddr3_if_mig.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Tue Sept 21 2010 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Top-level module. This module can be instantiated in the // system and interconnect as shown in user design wrapper file (user top module). // In addition to the memory controller, the module instantiates: // 1. Clock generation/distribution, reset logic // 2. IDELAY control block // 3. Debug logic // Reference : // Revision History : //***************************************************************************** //`define SKIP_CALIB `timescale 1ps/1ps module ddr3_if_mig # ( //*************************************************************************** // The following parameters refer to width of various ports //*************************************************************************** parameter BANK_WIDTH = 3, // # of memory Bank Address bits. parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory. parameter COL_WIDTH = 10, // # of memory Column Address bits. parameter CS_WIDTH = 1, // # of unique CS outputs to memory. parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank for phy parameter CKE_WIDTH = 1, // # of CKE outputs to memory. parameter DATA_BUF_ADDR_WIDTH = 5, parameter DQ_CNT_WIDTH = 5, // = ceil(log2(DQ_WIDTH)) parameter DQ_PER_DM = 8, parameter DM_WIDTH = 4, // # of DM (data mask) parameter DQ_WIDTH = 32, // # of DQ (data) parameter DQS_WIDTH = 4, parameter DQS_CNT_WIDTH = 2, // = ceil(log2(DQS_WIDTH)) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter ECC = "OFF", parameter DATA_WIDTH = 32, parameter ECC_TEST = "OFF", parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH, parameter MEM_ADDR_ORDER = "ROW_BANK_COLUMN", //Possible Parameters //1.BANK_ROW_COLUMN : Address mapping is // in form of Bank Row Column. //2.ROW_BANK_COLUMN : Address mapping is // in the form of Row Bank Column. //3.TG_TEST : Scrambles Address bits // for distributed Addressing. //parameter nBANK_MACHS = 4, parameter nBANK_MACHS = 4, parameter RANKS = 1, // # of Ranks. parameter ODT_WIDTH = 1, // # of ODT outputs to memory. parameter ROW_WIDTH = 15, // # of memory Row Address bits. parameter ADDR_WIDTH = 29, // # = RANK_WIDTH + BANK_WIDTH // + ROW_WIDTH + COL_WIDTH; // Chip Select is always tied to low for // single rank devices parameter USE_CS_PORT = 1, // # = 1, When Chip Select (CS#) output is enabled // = 0, When Chip Select (CS#) output is disabled // If CS_N disabled, user must connect // DRAM CS_N input(s) to ground parameter USE_DM_PORT = 1, // # = 1, When Data Mask option is enabled // = 0, When Data Mask option is disbaled // When Data Mask option is disabled in // MIG Controller Options page, the logic // related to Data Mask should not get // synthesized parameter USE_ODT_PORT = 1, // # = 1, When ODT output is enabled // = 0, When ODT output is disabled // Parameter configuration for Dynamic ODT support: // USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120". // This configuration allows to save ODT pin mapping from FPGA. // The user can tie the ODT input of DRAM to HIGH. parameter IS_CLK_SHARED = "FALSE", // # = "true" when clock is shared // = "false" when clock is not shared parameter PHY_CONTROL_MASTER_BANK = 1, // The bank index where master PHY_CONTROL resides, // equal to the PLL residing bank parameter MEM_DENSITY = "4Gb", // Indicates the density of the Memory part // Added for the sake of Vivado simulations parameter MEM_SPEEDGRADE = "107E", // Indicates the Speed grade of Memory Part // Added for the sake of Vivado simulations parameter MEM_DEVICE_WIDTH = 16, // Indicates the device width of the Memory Part // Added for the sake of Vivado simulations //*************************************************************************** // The following parameters are mode register settings //*************************************************************************** parameter AL = "0", // DDR3 SDRAM: // Additive Latency (Mode Register 1). // # = "0", "CL-1", "CL-2". // DDR2 SDRAM: // Additive Latency (Extended Mode Register). parameter nAL = 0, // # Additive Latency in number of clock // cycles. parameter BURST_MODE = "8", // DDR3 SDRAM: // Burst Length (Mode Register 0). // # = "8", "4", "OTF". // DDR2 SDRAM: // Burst Length (Mode Register). // # = "8", "4". parameter BURST_TYPE = "SEQ", // DDR3 SDRAM: Burst Type (Mode Register 0). // DDR2 SDRAM: Burst Type (Mode Register). // # = "SEQ" - (Sequential), // = "INT" - (Interleaved). parameter CL = 13, // in number of clock cycles // DDR3 SDRAM: CAS Latency (Mode Register 0). // DDR2 SDRAM: CAS Latency (Mode Register). parameter CWL = 9, // in number of clock cycles // DDR3 SDRAM: CAS Write Latency (Mode Register 2). // DDR2 SDRAM: Can be ignored parameter OUTPUT_DRV = "HIGH", // Output Driver Impedance Control (Mode Register 1). // # = "HIGH" - RZQ/7, // = "LOW" - RZQ/6. parameter RTT_NOM = "40", // RTT_NOM (ODT) (Mode Register 1). // = "120" - RZQ/2, // = "60" - RZQ/4, // = "40" - RZQ/6. parameter RTT_WR = "OFF", // RTT_WR (ODT) (Mode Register 2). // # = "OFF" - Dynamic ODT off, // = "120" - RZQ/2, // = "60" - RZQ/4, parameter ADDR_CMD_MODE = "1T" , // # = "1T", "2T". parameter REG_CTRL = "OFF", // # = "ON" - RDIMMs, // = "OFF" - Components, SODIMMs, UDIMMs. parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter VDD_OP_VOLT = "150", // # = "150" - 1.5V Vdd Memory part // = "135" - 1.35V Vdd Memory part //*************************************************************************** // The following parameters are multiplier and divisor factors for PLLE2. // Based on the selected design frequency these parameters vary. //*************************************************************************** parameter CLKIN_PERIOD = 5004, // Input Clock Period parameter CLKFBOUT_MULT = 9, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 337.5, // Phase for PLL output clock (CLKOUT0) parameter CLKOUT0_DIVIDE = 2, // VCO output divisor for PLL output clock (CLKOUT0) parameter CLKOUT1_DIVIDE = 2, // VCO output divisor for PLL output clock (CLKOUT1) parameter CLKOUT2_DIVIDE = 32, // VCO output divisor for PLL output clock (CLKOUT2) parameter CLKOUT3_DIVIDE = 8, // VCO output divisor for PLL output clock (CLKOUT3) parameter MMCM_VCO = 899, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor //*************************************************************************** // Memory Timing Parameters. These parameters varies based on the selected // memory part. //*************************************************************************** parameter tCKE = 5000, // memory tCKE paramter in pS parameter tFAW = 35000, // memory tRAW paramter in pS. parameter tPRDI = 1_000_000, // memory tPRDI paramter in pS. parameter tRAS = 34000, // memory tRAS paramter in pS. parameter tRCD = 13910, // memory tRCD paramter in pS. parameter tREFI = 7800000, // memory tREFI paramter in pS. parameter tRFC = 260000, // memory tRFC paramter in pS. parameter tRP = 13910, // memory tRP paramter in pS. parameter tRRD = 6000, // memory tRRD paramter in pS. parameter tRTP = 7500, // memory tRTP paramter in pS. parameter tWTR = 7500, // memory tWTR paramter in pS. parameter tZQI = 128_000_000, // memory tZQI paramter in nS. parameter tZQCS = 72,//64, // memory tZQCS paramter in clock cycles. //*************************************************************************** // Simulation parameters //*************************************************************************** parameter SIM_BYPASS_INIT_CAL = "FAST", // # = "OFF" - Complete memory init & // calibration sequence // # = "SKIP" - Not supported // # = "FAST" - Complete memory init & use // abbreviated calib sequence parameter SIMULATION = "TRUE", // Should be TRUE during design simulations and // FALSE during implementations //*************************************************************************** // The following parameters varies based on the pin out entered in MIG GUI. // Do not change any of these parameters directly by editing the RTL. // Any changes required should be done through GUI and the design regenerated. //*************************************************************************** parameter BYTE_LANES_B0 = 4'b1111, // Byte lanes used in an IO column. parameter BYTE_LANES_B1 = 4'b1111, // Byte lanes used in an IO column. parameter BYTE_LANES_B2 = 4'b0000, // Byte lanes used in an IO column. parameter BYTE_LANES_B3 = 4'b0000, // Byte lanes used in an IO column. parameter BYTE_LANES_B4 = 4'b0000, // Byte lanes used in an IO column. parameter DATA_CTL_B0 = 4'b1111, // Indicates Byte lane is data byte lane // or control Byte lane. '1' in a bit // position indicates a data byte lane and // a '0' indicates a control byte lane parameter DATA_CTL_B1 = 4'b0000, // Indicates Byte lane is data byte lane // or control Byte lane. '1' in a bit // position indicates a data byte lane and // a '0' indicates a control byte lane parameter DATA_CTL_B2 = 4'b0000, // Indicates Byte lane is data byte lane // or control Byte lane. '1' in a bit // position indicates a data byte lane and // a '0' indicates a control byte lane parameter DATA_CTL_B3 = 4'b0000, // Indicates Byte lane is data byte lane // or control Byte lane. '1' in a bit // position indicates a data byte lane and // a '0' indicates a control byte lane parameter DATA_CTL_B4 = 4'b0000, // Indicates Byte lane is data byte lane // or control Byte lane. '1' in a bit // position indicates a data byte lane and // a '0' indicates a control byte lane parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF, parameter PHY_1_BITLANES = 48'h3FE_FFC_C10_003, parameter PHY_2_BITLANES = 48'h000_000_000_000, // control/address/data pin mapping parameters parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13, parameter ADDR_MAP = 192'h000_114_139_138_137_136_135_134_133_132_131_125_128_127_126_12B, parameter BANK_MAP = 36'h12A_129_124, parameter CAS_MAP = 12'h122, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_11B, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_11A, parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_100, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h123, parameter WE_MAP = 12'h101, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01_02_03, parameter DATA0_MAP = 96'h031_032_033_034_035_036_037_038, parameter DATA1_MAP = 96'h021_022_023_024_025_026_027_028, parameter DATA2_MAP = 96'h011_012_013_014_015_016_017_018, parameter DATA3_MAP = 96'h000_001_002_003_004_005_006_007, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, parameter MASK0_MAP = 108'h000_000_000_000_000_009_019_029_039, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter SLOT_0_CONFIG = 8'b0000_0001, // Mapping of Ranks. parameter SLOT_1_CONFIG = 8'b0000_0000, // Mapping of Ranks. //*************************************************************************** // IODELAY and PHY related parameters //*************************************************************************** parameter IBUF_LPWR_MODE = "OFF", // to phy_top parameter DATA_IO_IDLE_PWRDWN = "ON", // # = "ON", "OFF" parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "HP_LP", // # = "HP_LP", "HR_LP", "DEFAULT" parameter CKE_ODT_AUX = "FALSE", parameter USER_REFRESH = "OFF", parameter WRLVL = "ON", // # = "ON" - DDR3 SDRAM // = "OFF" - DDR2 SDRAM. parameter ORDERING = "NORM", // # = "NORM", "STRICT", "RELAXED". parameter CALIB_ROW_ADD = 16'h0000, // Calibration row address will be used for // calibration read and write operations parameter CALIB_COL_ADD = 12'h000, // Calibration column address will be used for // calibration read and write operations parameter CALIB_BA_ADD = 3'h0, // Calibration bank address will be used for // calibration read and write operations parameter TCQ = 100, parameter IDELAY_ADJ = "ON", parameter FINE_PER_BIT = "ON", parameter CENTER_COMP_MODE = "ON", parameter PI_VAL_ADJ = "ON", parameter IODELAY_GRP0 = "DDR3_IF_IODELAY_MIG0", // It is associated to a set of IODELAYs with // an IDELAYCTRL that have same IODELAY CONTROLLER // clock frequency (200MHz). parameter IODELAY_GRP1 = "DDR3_IF_IODELAY_MIG1", // It is associated to a set of IODELAYs with // an IDELAYCTRL that have same IODELAY CONTROLLER // clock frequency (300MHz/400MHz). parameter SYSCLK_TYPE = "NO_BUFFER", // System clock type DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK", // Reference clock type DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER, USE_SYSTEM_CLOCK parameter SYS_RST_PORT = "FALSE", // "TRUE" - if pin is selected for sys_rst // and IBUF will be instantiated. // "FALSE" - if pin is not selected for sys_rst parameter FPGA_SPEED_GRADE = 2, // FPGA speed grade parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY parameter DRAM_TYPE = "DDR3", parameter CAL_WIDTH = "HALF", parameter STARVE_LIMIT = 2, // # = 2,3,4. parameter REF_CLK_MMCM_IODELAY_CTRL = "TRUE", //*************************************************************************** // Referece clock frequency parameters //*************************************************************************** parameter REFCLK_FREQ = 200.0, // IODELAYCTRL reference clock frequency parameter DIFF_TERM_REFCLK = "TRUE", // Differential Termination for idelay // reference clock input pins //*************************************************************************** // System clock frequency parameters //*************************************************************************** parameter tCK = 1112, // memory tCK paramter. // # = Clock Period in pS. parameter nCK_PER_CLK = 4, // # of memory CKs per fabric CLK parameter DIFF_TERM_SYSCLK = "TRUE", // Differential Termination for System // clock input pins //*************************************************************************** // AXI4 Shim parameters //*************************************************************************** parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter C_S_AXI_ID_WIDTH = 1, // Width of all master and slave ID signals. // # = >= 1. parameter C_S_AXI_MEM_SIZE = "1073741824", // Address Space required for this component parameter C_S_AXI_ADDR_WIDTH = 30, // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and // M_AXI_ARADDR for all SI/MI slots. // # = 32. parameter C_S_AXI_DATA_WIDTH = 256, // Width of WDATA and RDATA on SI slot. // Must be <= APP_DATA_WIDTH. // # = 32, 64, 128, 256. parameter C_MC_nCK_PER_CLK = 4, // Indicates whether to instatiate upsizer // Range: 0, 1 parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0, // Indicates whether to instatiate upsizer // Range: 0, 1 parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG_STARVE_LIMIT", // Indicates the Arbitration // Allowed values - "TDM", "ROUND_ROBIN", // "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT" // "WRITE_PRIORITY", "WRITE_PRIORITY_REG" parameter C_S_AXI_REG_EN0 = 20'h00000, // C_S_AXI_REG_EN0[00] = Reserved // C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE // C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE parameter C_S_AXI_REG_EN1 = 20'h00000, // Instatiates register slices after the upsizer. // The type of register is specified for each channel // in a vector. 4 bits per channel are used. // C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE // C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE // Possible values for each channel are: // // 0 => BYPASS = The channel is just wired through the // module. // 1 => FWD = The master VALID and payload signals // are registrated. // 2 => REV = The slave ready signal is registrated // 3 => FWD_REV = Both FWD and REV // 4 => SLAVE_FWD = All slave side signals and master // VALID and payload are registrated. // 5 => SLAVE_RDY = All slave side signals and master // READY are registrated. // 6 => INPUTS = Slave and Master side inputs are // registrated. // 7 => ADDRESS = Optimized for address channel parameter C_S_AXI_CTRL_ADDR_WIDTH = 32, // Width of AXI-4-Lite address bus parameter C_S_AXI_CTRL_DATA_WIDTH = 32, // Width of AXI-4-Lite data buses parameter C_S_AXI_BASEADDR = 32'h0000_0000, // Base address of AXI4 Memory Mapped bus. parameter C_ECC_ONOFF_RESET_VALUE = 1, // Controls ECC on/off value at startup/reset parameter C_ECC_CE_COUNTER_WIDTH = 8, // The external memory to controller clock ratio. //*************************************************************************** // Debug parameters //*************************************************************************** parameter DEBUG_PORT = "OFF", // # = "ON" Enable debug signals/controls. // = "OFF" Disable debug signals/controls. //*************************************************************************** // Temparature monitor parameter //*************************************************************************** parameter TEMP_MON_CONTROL = "INTERNAL", // # = "INTERNAL", "EXTERNAL" //*************************************************************************** // FPGA Voltage Type parameter //*************************************************************************** parameter FPGA_VOLT_TYPE = "N", // # = "L", "N". When FPGA VccINT is 0.9v, // the value is "L", else it is "N" parameter RST_ACT_LOW = 1 // =1 for active low reset, // =0 for active high. ) ( // Inouts inout [DQ_WIDTH-1:0] ddr3_dq, inout [DQS_WIDTH-1:0] ddr3_dqs_n, inout [DQS_WIDTH-1:0] ddr3_dqs_p, // Outputs output [ROW_WIDTH-1:0] ddr3_addr, output [BANK_WIDTH-1:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [CK_WIDTH-1:0] ddr3_ck_p, output [CK_WIDTH-1:0] ddr3_ck_n, output [CKE_WIDTH-1:0] ddr3_cke, output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n, output [DM_WIDTH-1:0] ddr3_dm, output [ODT_WIDTH-1:0] ddr3_odt, // Inputs // Single-ended system clock input sys_clk_i, // user interface signals output ui_clk, output ui_clk_sync_rst, output mmcm_locked, input aresetn, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // Slave Interface Write Address Ports input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid, input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input [0:0] s_axi_awlock, input [3:0] s_axi_awcache, input [2:0] s_axi_awprot, input [3:0] s_axi_awqos, input s_axi_awvalid, output s_axi_awready, // Slave Interface Write Data Ports input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata, input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, // Slave Interface Write Response Ports input s_axi_bready, output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, // Slave Interface Read Address Ports input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid, input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input [0:0] s_axi_arlock, input [3:0] s_axi_arcache, input [2:0] s_axi_arprot, input [3:0] s_axi_arqos, input s_axi_arvalid, output s_axi_arready, // Slave Interface Read Data Ports input s_axi_rready, output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, output init_calib_complete, output [11:0] device_temp, `ifdef SKIP_CALIB output calib_tap_req, input calib_tap_load, input [6:0] calib_tap_addr, input [7:0] calib_tap_val, input calib_tap_load_done, `endif // System reset - Default polarity of sys_rst pin is Active Low. // System reset polarity will change based on the option // selected in GUI. input sys_rst ); function integer clogb2 (input integer size); begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS); localparam RANK_WIDTH = clogb2(RANKS); localparam ECC_WIDTH = (ECC == "OFF")? 0 : (DATA_WIDTH <= 4)? 4 : (DATA_WIDTH <= 10)? 5 : (DATA_WIDTH <= 26)? 6 : (DATA_WIDTH <= 57)? 7 : (DATA_WIDTH <= 120)? 8 : (DATA_WIDTH <= 247)? 9 : 10; localparam DATA_BUF_OFFSET_WIDTH = 1; localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + BANK_WIDTH + ROW_WIDTH + COL_WIDTH + DATA_BUF_OFFSET_WIDTH; localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH; localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8; localparam TEMP_MON_EN = (SIMULATION == "TRUE") ? "ON" : "OFF"; // Enable or disable the temp monitor module localparam tTEMPSAMPLE = 10000000; // sample every 10 us localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock `ifdef SKIP_CALIB localparam SKIP_CALIB = "TRUE"; `else localparam SKIP_CALIB = "FALSE"; `endif localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK; // Wire declarations wire [BM_CNT_WIDTH-1:0] bank_mach_next; wire clk; wire [1:0] clk_ref; wire [1:0] iodelay_ctrl_rdy; wire clk_ref_in; wire sys_rst_o; wire clk_div2; wire rst_div2; wire freq_refclk ; wire mem_refclk ; wire pll_lock ; wire sync_pulse; wire mmcm_ps_clk; wire poc_sample_pd; wire psen; wire psincdec; wire psdone; wire iddr_rst; wire ref_dll_lock; wire rst_phaser_ref; wire pll_locked; wire rst; wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; wire ddr3_parity; // AXI CTRL port wire s_axi_ctrl_awvalid; wire s_axi_ctrl_awready; wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr; // Slave Interface Write Data Ports wire s_axi_ctrl_wvalid; wire s_axi_ctrl_wready; wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata; // Slave Interface Write Response Ports wire s_axi_ctrl_bvalid; wire s_axi_ctrl_bready; wire [1:0] s_axi_ctrl_bresp; // Slave Interface Read Address Ports wire s_axi_ctrl_arvalid; wire s_axi_ctrl_arready; wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr; // Slave Interface Read Data Ports wire s_axi_ctrl_rvalid; wire s_axi_ctrl_rready; wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata; wire [1:0] s_axi_ctrl_rresp; // Interrupt output wire interrupt; wire sys_clk_p; wire sys_clk_n; wire mmcm_clk; wire clk_ref_p; wire clk_ref_n; wire clk_ref_i; wire [11:0] device_temp_i; // Debug port signals wire dbg_idel_down_all; wire dbg_idel_down_cpt; wire dbg_idel_up_all; wire dbg_idel_up_cpt; wire dbg_sel_all_idel_cpt; wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt; wire dbg_sel_pi_incdec; wire [DQS_CNT_WIDTH:0] dbg_byte_sel; wire dbg_pi_f_inc; wire dbg_pi_f_dec; wire [5:0] dbg_pi_counter_read_val; wire [8:0] dbg_po_counter_read_val; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt; wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt; wire [255:0] dbg_calib_top; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt; wire [(6*RANKS)-1:0] dbg_rd_data_offset; wire [255:0] dbg_phy_rdlvl; wire [99:0] dbg_phy_wrcal; wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt; wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt; wire [255:0] dbg_phy_wrlvl; wire [255:0] dbg_phy_init; wire [255:0] dbg_prbs_rdlvl; wire [255:0] dbg_dqs_found_cal; wire dbg_pi_phaselock_start; wire dbg_pi_phaselocked_done; wire dbg_pi_phaselock_err; wire dbg_pi_dqsfound_start; wire dbg_pi_dqsfound_done; wire dbg_pi_dqsfound_err; wire dbg_wrcal_start; wire dbg_wrcal_done; wire dbg_wrcal_err; wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes; wire [11:0] dbg_pi_phase_locked_phy4lanes; wire dbg_oclkdelay_calib_start; wire dbg_oclkdelay_calib_done; wire [255:0] dbg_phy_oclkdelay_cal; wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data; wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect; wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata; wire dbg_rddata_valid; wire [1:0] dbg_rdlvl_done; wire [1:0] dbg_rdlvl_err; wire [1:0] dbg_rdlvl_start; wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt; wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt; wire [5:0] dbg_tap_cnt_during_wrlvl; wire dbg_wl_edge_detect_valid; wire dbg_wrlvl_done; wire dbg_wrlvl_err; wire dbg_wrlvl_start; reg [63:0] dbg_rddata_r; reg dbg_rddata_valid_r; wire [53:0] ocal_tap_cnt; wire [4:0] dbg_dqs; wire [8:0] dbg_bit; wire [8:0] rd_data_edge_detect_r; wire [53:0] wl_po_fine_cnt; wire [26:0] wl_po_coarse_cnt; wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1; wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2; wire [5:0] dbg_data_offset; wire [5:0] dbg_data_offset_1; wire [5:0] dbg_data_offset_2; wire [390:0] ddr3_ila_wrpath_int; wire [1023:0] ddr3_ila_rdpath_int; wire [119:0] ddr3_ila_basic_int; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int; wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int; //*************************************************************************** assign ui_clk = clk; assign ui_clk_sync_rst = rst; assign sys_clk_p = 1'b0; assign sys_clk_n = 1'b0; assign clk_ref_i = 1'b0; generate if (REFCLK_TYPE == "USE_SYSTEM_CLOCK") assign clk_ref_in = mmcm_clk; else assign clk_ref_in = clk_ref_i; endgenerate mig_7series_v4_0_iodelay_ctrl # ( .TCQ (TCQ), .IODELAY_GRP0 (IODELAY_GRP0), .IODELAY_GRP1 (IODELAY_GRP1), .REFCLK_TYPE (REFCLK_TYPE), .SYSCLK_TYPE (SYSCLK_TYPE), .SYS_RST_PORT (SYS_RST_PORT), .RST_ACT_LOW (RST_ACT_LOW), .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL) ) u_iodelay_ctrl ( // Outputs .iodelay_ctrl_rdy (iodelay_ctrl_rdy), .sys_rst_o (sys_rst_o), .clk_ref (clk_ref), // Inputs .clk_ref_p (clk_ref_p), .clk_ref_n (clk_ref_n), .clk_ref_i (clk_ref_in), .sys_rst (sys_rst) ); mig_7series_v4_0_clk_ibuf # ( .SYSCLK_TYPE (SYSCLK_TYPE), .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK) ) u_ddr3_clk_ibuf ( .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .sys_clk_i (sys_clk_i), .mmcm_clk (mmcm_clk) ); // Temperature monitoring logic generate if (TEMP_MON_EN == "ON") begin: temp_mon_enabled mig_7series_v4_0_tempmon # ( .TCQ (TCQ), .TEMP_MON_CONTROL (TEMP_MON_CONTROL), .XADC_CLK_PERIOD (XADC_CLK_PERIOD), .tTEMPSAMPLE (tTEMPSAMPLE) ) u_tempmon ( .clk (clk), .xadc_clk (clk_ref[0]), .rst (rst), .device_temp_i (device_temp_i), .device_temp (device_temp) ); end else begin: temp_mon_disabled assign device_temp = 'b0; end endgenerate mig_7series_v4_0_infrastructure # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLKIN_PERIOD (CLKIN_PERIOD), .SYSCLK_TYPE (SYSCLK_TYPE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), .MMCM_VCO (MMCM_VCO), .MMCM_MULT_F (MMCM_MULT_F), .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .RST_ACT_LOW (RST_ACT_LOW), .tCK (tCK), .MEM_TYPE (DRAM_TYPE) ) u_ddr3_infrastructure ( // Outputs .rstdiv0 (rst), .clk (clk), .clk_div2 (clk_div2), .rst_div2 (rst_div2), .mem_refclk (mem_refclk), .freq_refclk (freq_refclk), .sync_pulse (sync_pulse), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .iddr_rst (iddr_rst), // .auxout_clk (), .ui_addn_clk_0 (), .ui_addn_clk_1 (), .ui_addn_clk_2 (), .ui_addn_clk_3 (), .ui_addn_clk_4 (), .pll_locked (pll_locked), .mmcm_locked (mmcm_locked), .rst_phaser_ref (rst_phaser_ref), // Inputs .psen (psen), .psincdec (psincdec), .mmcm_clk (mmcm_clk), .sys_rst (sys_rst_o), .iodelay_ctrl_rdy (iodelay_ctrl_rdy), .ref_dll_lock (ref_dll_lock) ); mig_7series_v4_0_memc_ui_top_axi # ( .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .AL (AL), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .CA_MIRROR (CA_MIRROR), .DDR3_VDD_OP_VOLT (VDD_OP_VOLT), .CK_WIDTH (CK_WIDTH), .COL_WIDTH (COL_WIDTH), .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), .CS_WIDTH (CS_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .CKE_WIDTH (CKE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DM_WIDTH (DM_WIDTH), .DQ_CNT_WIDTH (DQ_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), .ECC (ECC), .ECC_WIDTH (ECC_WIDTH), .ECC_TEST (ECC_TEST), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .REFCLK_FREQ (REFCLK_FREQ), .nAL (nAL), .nBANK_MACHS (nBANK_MACHS), .CKE_ODT_AUX (CKE_ODT_AUX), .nCK_PER_CLK (nCK_PER_CLK), .ORDERING (ORDERING), .OUTPUT_DRV (OUTPUT_DRV), .IBUF_LPWR_MODE (IBUF_LPWR_MODE), .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .IODELAY_GRP0 (IODELAY_GRP0), .IODELAY_GRP1 (IODELAY_GRP1), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .REG_CTRL (REG_CTRL), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .CL (CL), .CWL (CWL), .tCK (tCK), .tCKE (tCKE), .tFAW (tFAW), .tPRDI (tPRDI), .tRAS (tRAS), .tRCD (tRCD), .tREFI (tREFI), .tRFC (tRFC), .tRP (tRP), .tRRD (tRRD), .tRTP (tRTP), .tWTR (tWTR), .tZQI (tZQI), .tZQCS (tZQCS), .USER_REFRESH (USER_REFRESH), .TEMP_MON_EN (TEMP_MON_EN), .WRLVL (WRLVL), .DEBUG_PORT (DEBUG_PORT), .CAL_WIDTH (CAL_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .ADDR_WIDTH (ADDR_WIDTH), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .MEM_ADDR_ORDER (MEM_ADDR_ORDER), .STARVE_LIMIT (STARVE_LIMIT), .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH), .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST), .C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM), .C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0), .C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1), .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH), .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH), .C_S_AXI_BASEADDR (C_S_AXI_BASEADDR), .C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE), .C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH), .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK), .TAPSPERKCLK (TAPSPERKCLK), .SKIP_CALIB (SKIP_CALIB), .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) ) u_memc_ui_top_axi ( .clk (clk), .clk_div2 (clk_div2), .rst_div2 (rst_div2), .clk_ref (clk_ref), .mem_refclk (mem_refclk), //memory clock .freq_refclk (freq_refclk), .pll_lock (pll_locked), .sync_pulse (sync_pulse), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .iddr_rst (iddr_rst), .psen (psen), .psincdec (psincdec), .rst (rst), .rst_phaser_ref (rst_phaser_ref), .ref_dll_lock (ref_dll_lock), // Memory interface ports .ddr_dq (ddr3_dq), .ddr_dqs_n (ddr3_dqs_n), .ddr_dqs (ddr3_dqs_p), .ddr_addr (ddr3_addr), .ddr_ba (ddr3_ba), .ddr_cas_n (ddr3_cas_n), .ddr_ck_n (ddr3_ck_n), .ddr_ck (ddr3_ck_p), .ddr_cke (ddr3_cke), .ddr_cs_n (ddr3_cs_n), .ddr_dm (ddr3_dm), .ddr_odt (ddr3_odt), .ddr_ras_n (ddr3_ras_n), .ddr_reset_n (ddr3_reset_n), .ddr_parity (ddr3_parity), .ddr_we_n (ddr3_we_n), .bank_mach_next (bank_mach_next), // Application interface ports .app_ecc_multiple_err_o (), .app_ecc_single_err (), .device_temp (device_temp), // skip calibration ports `ifdef SKIP_CALIB .calib_tap_req (calib_tap_req), .calib_tap_load (calib_tap_load), .calib_tap_addr (calib_tap_addr), .calib_tap_val (calib_tap_val), .calib_tap_load_done (calib_tap_load_done), `else .calib_tap_req (), .calib_tap_load (1'b0), .calib_tap_addr (7'b0), .calib_tap_val (8'b0), .calib_tap_load_done (1'b0), `endif // Debug logic ports .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_sel_pi_incdec (dbg_sel_pi_incdec), .dbg_sel_po_incdec (dbg_sel_po_incdec), .dbg_byte_sel (dbg_byte_sel), .dbg_pi_f_inc (dbg_pi_f_inc), .dbg_pi_f_dec (dbg_pi_f_dec), .dbg_po_f_inc (dbg_po_f_inc), .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), .dbg_po_f_dec (dbg_po_f_dec), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_calib_top (dbg_calib_top), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_rd_data_offset (dbg_rd_data_offset), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_rddata (dbg_rddata), .dbg_rddata_valid (dbg_rddata_valid), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_phy_wrlvl (dbg_phy_wrlvl), .dbg_phy_init (dbg_phy_init), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .dbg_pi_counter_read_val (dbg_pi_counter_read_val), .dbg_po_counter_read_val (dbg_po_counter_read_val), .dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int), .dbg_pi_phaselock_start (dbg_pi_phaselock_start), .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), .dbg_pi_phaselock_err (dbg_pi_phaselock_err), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), .dbg_data_offset (dbg_data_offset), .dbg_data_offset_1 (dbg_data_offset_1), .dbg_data_offset_2 (dbg_data_offset_2), .dbg_wrcal_start (dbg_wrcal_start), .dbg_wrcal_done (dbg_wrcal_done), .dbg_wrcal_err (dbg_wrcal_err), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), .dbg_dqs_found_cal (dbg_dqs_found_cal), .aresetn (aresetn), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), // Slave Interface Write Address Ports .s_axi_awid (s_axi_awid), .s_axi_awaddr (s_axi_awaddr), .s_axi_awlen (s_axi_awlen), .s_axi_awsize (s_axi_awsize), .s_axi_awburst (s_axi_awburst), .s_axi_awlock (s_axi_awlock), .s_axi_awcache (s_axi_awcache), .s_axi_awprot (s_axi_awprot), .s_axi_awqos (s_axi_awqos), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), // Slave Interface Write Data Ports .s_axi_wdata (s_axi_wdata), .s_axi_wstrb (s_axi_wstrb), .s_axi_wlast (s_axi_wlast), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), // Slave Interface Write Response Ports .s_axi_bid (s_axi_bid), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), // Slave Interface Read Address Ports .s_axi_arid (s_axi_arid), .s_axi_araddr (s_axi_araddr), .s_axi_arlen (s_axi_arlen), .s_axi_arsize (s_axi_arsize), .s_axi_arburst (s_axi_arburst), .s_axi_arlock (s_axi_arlock), .s_axi_arcache (s_axi_arcache), .s_axi_arprot (s_axi_arprot), .s_axi_arqos (s_axi_arqos), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), // Slave Interface Read Data Ports .s_axi_rid (s_axi_rid), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rlast (s_axi_rlast), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready), // AXI CTRL port .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid), .s_axi_ctrl_awready (s_axi_ctrl_awready), .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr), // Slave Interface Write Data Ports .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid), .s_axi_ctrl_wready (s_axi_ctrl_wready), .s_axi_ctrl_wdata (s_axi_ctrl_wdata), // Slave Interface Write Response Ports .s_axi_ctrl_bvalid (s_axi_ctrl_bvalid), .s_axi_ctrl_bready (s_axi_ctrl_bready), .s_axi_ctrl_bresp (s_axi_ctrl_bresp), // Slave Interface Read Address Ports .s_axi_ctrl_arvalid (s_axi_ctrl_arvalid), .s_axi_ctrl_arready (s_axi_ctrl_arready), .s_axi_ctrl_araddr (s_axi_ctrl_araddr), // Slave Interface Read Data Ports .s_axi_ctrl_rvalid (s_axi_ctrl_rvalid), .s_axi_ctrl_rready (s_axi_ctrl_rready), .s_axi_ctrl_rdata (s_axi_ctrl_rdata), .s_axi_ctrl_rresp (s_axi_ctrl_rresp), // Interrupt output .interrupt (interrupt), .init_calib_complete (init_calib_complete), .dbg_poc () ); //********************************************************************* // Resetting all RTL debug inputs as the debug ports are not enabled //********************************************************************* assign dbg_idel_down_all = 1'b0; assign dbg_idel_down_cpt = 1'b0; assign dbg_idel_up_all = 1'b0; assign dbg_idel_up_cpt = 1'b0; assign dbg_sel_all_idel_cpt = 1'b0; assign dbg_sel_idel_cpt = 'b0; assign dbg_byte_sel = 'd0; assign dbg_sel_pi_incdec = 1'b0; assign dbg_pi_f_inc = 1'b0; assign dbg_pi_f_dec = 1'b0; assign dbg_po_f_inc = 'b0; assign dbg_po_f_dec = 'b0; assign dbg_po_f_stg23_sel = 'b0; assign dbg_sel_po_incdec = 'b0; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_buf.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ecc_buf #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter DATA_BUF_ADDR_WIDTH = 4, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DATA_WIDTH = 64, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs rd_merge_data, // Inputs clk, rst, rd_data_addr, rd_data_offset, wr_data_addr, wr_data_offset, rd_data, wr_ecc_buf ); input clk; input rst; // RMW architecture supports only 16 data buffer entries. // Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but // assume the upper bits are used for tagging. input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; wire [4:0] buf_wr_addr; input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; reg [4:0] buf_rd_addr_r; generate if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits always @(posedge clk) buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset}; assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset}; end else begin : lt_4_addr_bits always @(posedge clk) buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}}, wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0], wr_data_offset}; assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}}, rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0], rd_data_offset}; end endgenerate input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload; integer h; always @(/*AS*/rd_data) for (h=0; h<2*nCK_PER_CLK; h=h+1) payload[h*DATA_WIDTH+:DATA_WIDTH] = rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH]; input wr_ecc_buf; localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH; localparam FULL_RAM_CNT = (BUF_WIDTH/6); localparam REMAINDER = BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); wire [RAM_WIDTH-1:0] buf_out_data; generate begin : ram_buf wire [RAM_WIDTH-1:0] buf_in_data; if (REMAINDER == 0) assign buf_in_data = payload; else assign buf_in_data = {{6-REMAINDER{1'b0}}, payload}; genvar i; for (i=0; i 0) for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits always @(/*AS*/ecc_rddata_r) rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] = ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH]; end endgenerate // Generate status information. input ecc_status_valid; output wire [2*nCK_PER_CLK-1:0] ecc_single; output wire [2*nCK_PER_CLK-1:0] ecc_multiple; genvar v; generate for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; assign ecc_single[v] = ecc_status_valid && ~zero && odd; assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd; end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_gen.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps // Generate the ecc code. Note that the synthesizer should // generate this as a static logic. Code in this block should // never run during simulation phase, or directly impact timing. // // The code generated is a single correct, double detect code. // It is the classic Hamming code. Instead, the code is // optimized for minimal/balanced tree depth and size. See // Hsiao IBM Technial Journal 1970. // // The code is returned as a single bit vector, h_rows. This was // the only way to "subroutinize" this with the restrictions of // disallowed include files and that matrices cannot be passed // in ports. // // Factorial and the combos functions are defined. Combos // simply computes the number of combinations from the set // size and elements at a time. // // The function next_combo computes the next combination in // lexicographical order given the "current" combination. Its // output is undefined if given the last combination in the // lexicographical order. // // next_combo is insensitive to the number of elements in the // combinations. // // An H transpose matrix is generated because that's the easiest // way to do it. The H transpose matrix is generated by taking // the one at a time combinations, then the 3 at a time, then // the 5 at a time. The number combinations used is equal to // the width of the code (CODE_WIDTH). The boundaries between // the 1, 3 and 5 groups are hardcoded in the for loop. // // At the same time the h_rows vector is generated from the // H transpose matrix. module mig_7series_v4_0_ecc_gen #( parameter CODE_WIDTH = 72, parameter ECC_WIDTH = 8, parameter DATA_WIDTH = 64 ) ( /*AUTOARG*/ // Outputs h_rows ); function integer factorial (input integer i); integer index; if (i == 1) factorial = 1; else begin factorial = 1; for (index=2; index<=i; index=index+1) factorial = factorial * index; end endfunction // factorial function integer combos (input integer n, k); combos = factorial(n)/(factorial(k)*factorial(n-k)); endfunction // combinations // function next_combo // Given a combination, return the next combo in lexicographical // order. Scans from right to left. Assumes the first combination // is k ones all of the way to the left. // // Upon entry, initialize seen0, trig1, and ones. "seen0" means // that a zero has been observed while scanning from right to left. // "trig1" means that a one have been observed _after_ seen0 is set. // "ones" counts the number of ones observed while scanning the input. // // If trig1 is one, just copy the input bit to the output and increment // to the next bit. Otherwise set the the output bit to zero, if the // input is a one, increment ones. If the input bit is a one and seen0 // is true, dump out the accumulated ones. Set seen0 to the complement // of the input bit. Note that seen0 is not used subsequent to trig1 // getting set. function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i); integer index; integer dump_index; reg seen0; reg trig1; // integer ones; reg [ECC_WIDTH-1:0] ones; begin seen0 = 1'b0; trig1 = 1'b0; ones = 0; for (index=0; index=0;dump_index=dump_index-1) if (dump_index>=index-ones) next_combo[dump_index] = 1'b1; end seen0 = ~i[index]; end // else: !if(trig1) end end // function endfunction // next_combo wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0]; output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; localparam COMBOS_3 = combos(ECC_WIDTH, 3); localparam COMBOS_5 = combos(ECC_WIDTH, 5); genvar n; genvar s; generate for (n=0; n DATA_WIDTH) assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; end endgenerate // Generate ECC and overlay onto mc_wrdata. input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; input [2*nCK_PER_CLK-1:0] raw_not_ecc; reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; genvar j; integer k; generate for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; for (k=0; k 6) || (CL < 3))))); // Not needed after the CWL fix for DDR2 // ddr2_improper_CWL: assert property // (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1)))); `endif mig_7series_v4_0_ddr_phy_top # ( .TCQ (TCQ), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .REFCLK_FREQ (REFCLK_FREQ), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .CA_MIRROR (CA_MIRROR), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CKE_ODT_AUX (CKE_ODT_AUX), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .nCS_PER_RANK (nCS_PER_RANK), .CS_WIDTH (CS_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .PRE_REV3ES (PRE_REV3ES), .CKE_WIDTH (CKE_WIDTH), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .DRAM_TYPE (DRAM_TYPE), .BANK_WIDTH (BANK_WIDTH), .CK_WIDTH (CK_WIDTH), .COL_WIDTH (COL_WIDTH), .DM_WIDTH (DM_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), .ROW_WIDTH (ROW_WIDTH), .AL (AL), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .CL (nCL), .CWL (nCWL), .tRFC (tRFC), .tREFI (tREFI), .tCK (tCK), .OUTPUT_DRV (OUTPUT_DRV), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .REG_CTRL (REG_CTRL), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_1_CONFIG (SLOT_1_CONFIG), .WRLVL (WRLVL), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), // Prevent the following simulation-related parameters from // being overridden for synthesis - for synthesis only the // default values of these parameters should be used // synthesis translate_off .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), // synthesis translate_on .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .MASTER_PHY_CTL (MASTER_PHY_CTL), .DEBUG_PORT (DEBUG_PORT), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .TAPSPERKCLK (TAPSPERKCLK), .SKIP_CALIB (SKIP_CALIB), .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) ) ddr_phy_top0 ( // Outputs .calib_rd_data_offset_0 (calib_rd_data_offset_0), .calib_rd_data_offset_1 (calib_rd_data_offset_1), .calib_rd_data_offset_2 (calib_rd_data_offset_2), .ddr_ck (ddr_ck), .ddr_ck_n (ddr_ck_n), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_ras_n (ddr_ras_n), .ddr_cas_n (ddr_cas_n), .ddr_we_n (ddr_we_n), .ddr_cs_n (ddr_cs_n), .ddr_cke (ddr_cke), .ddr_odt (ddr_odt), .ddr_reset_n (ddr_reset_n), .ddr_parity (ddr_parity), .ddr_dm (ddr_dm), .dbg_calib_top (dbg_calib_top), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_rddata (dbg_rddata), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .init_calib_complete (init_calib_complete_w), .init_wrcal_complete (init_wrcal_complete_w), .mc_address (mc_address), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_bank (mc_bank), .mc_cke (mc_cke), .mc_odt (mc_odt), .mc_cas_n (mc_cas_n), .mc_cmd (mc_cmd), .mc_cmd_wren (mc_cmd_wren), .mc_cas_slot (mc_cas_slot), .mc_cs_n (mc_cs_n), .mc_ctl_wren (mc_ctl_wren), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .mc_rank_cnt (mc_rank_cnt), .mc_ras_n (mc_ras_n), .mc_reset_n (mc_reset_n), .mc_we_n (mc_we_n), .mc_wrdata (mc_wrdata), .mc_wrdata_en (mc_wrdata_en), .mc_wrdata_mask (mc_wrdata_mask), .idle (idle), .mem_refclk (mem_refclk), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_data_full (phy_mc_data_full), .phy_rd_data (phy_rd_data), .phy_rddata_valid (phy_rddata_valid), .pll_lock (pll_lock), .sync_pulse (sync_pulse), // Inouts .ddr_dqs (ddr_dqs), .ddr_dqs_n (ddr_dqs_n), .ddr_dq (ddr_dq), // Inputs .clk_ref (clk_ref), .freq_refclk (freq_refclk), .clk (clk), .clk_div2 (clk_div2), .rst_div2 (rst_div2), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .rst (rst), .error (error), .rst_tg_mc (rst_tg_mc), .slot_0_present (slot_0_present), .slot_1_present (slot_1_present), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt) ,.device_temp (device_temp) ,.tempmon_sample_en (tempmon_sample_en) ,.psen (psen) ,.psincdec (psincdec) ,.psdone (psdone) ,.calib_tap_req (calib_tap_req) ,.calib_tap_addr (calib_tap_addr) ,.calib_tap_load (calib_tap_load) ,.calib_tap_val (calib_tap_val) ,.calib_tap_load_done (calib_tap_load_done) ,.dbg_sel_pi_incdec (dbg_sel_pi_incdec) ,.dbg_sel_po_incdec (dbg_sel_po_incdec) ,.dbg_byte_sel (dbg_byte_sel) ,.dbg_pi_f_inc (dbg_pi_f_inc) ,.dbg_po_f_inc (dbg_po_f_inc) ,.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel) ,.dbg_pi_f_dec (dbg_pi_f_dec) ,.dbg_po_f_dec (dbg_po_f_dec) ,.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt) ,.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt) ,.dbg_rddata_valid (dbg_rddata_valid) ,.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt) ,.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt) ,.dbg_phy_wrlvl (dbg_phy_wrlvl) ,.ref_dll_lock (ref_dll_lock) ,.rst_phaser_ref (rst_phaser_ref) ,.iddr_rst (iddr_rst) ,.dbg_rd_data_offset (dbg_rd_data_offset) ,.dbg_phy_init (dbg_phy_init) ,.dbg_prbs_rdlvl (dbg_prbs_rdlvl) ,.dbg_dqs_found_cal (dbg_dqs_found_cal) ,.dbg_po_counter_read_val (dbg_po_counter_read_val) ,.dbg_pi_counter_read_val (dbg_pi_counter_read_val) ,.dbg_pi_phaselock_start (dbg_pi_phaselock_start) ,.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done) ,.dbg_pi_phaselock_err (dbg_pi_phaselock_err) ,.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start) ,.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done) ,.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err) ,.dbg_wrcal_start (dbg_wrcal_start) ,.dbg_wrcal_done (dbg_wrcal_done) ,.dbg_wrcal_err (dbg_wrcal_err) ,.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal) ,.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data) ,.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start) ,.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done) ,.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r) ,.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps) ,.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps) ,.dbg_poc (dbg_poc[1023:0]) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 3.6 // \ \ Application : MIG // / / Filename : memc_ui_top_axi.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:04 $ // \ \ / \ Date Created : Fri Oct 08 2010 // \___\/\___\ // // Device : 7 Series // Design Name : DDR2 SDRAM & DDR3 SDRAM // Purpose : // Top level memory interface block. Instantiates a clock and // reset generator, the memory controller, the phy and the // user interface blocks. // Reference : // Revision History : //***************************************************************************** `timescale 1 ps / 1 ps (* X_CORE_INFO = "mig_7series_v4_0_ddr3_7Series, ddr3_if, 2016.2" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v4_0,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=1, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=1, CLK_PERIOD=1112, PHY_RATIO=4, CLKIN_PERIOD=5004, VCCAUX_IO=2.0V, MEMORY_TYPE=COMP, MEMORY_PART=mt41j256m16xx-107, DQ_WIDTH=32, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=ROW_BANK_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *) module mig_7series_v4_0_memc_ui_top_axi # ( parameter TCQ = 100, parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 parameter PAYLOAD_WIDTH = 64, parameter ADDR_CMD_MODE = "UNBUF", parameter AL = "0", // Additive Latency option parameter BANK_WIDTH = 3, // # of bank bits parameter BM_CNT_WIDTH = 2, // Bank machine counter width parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory parameter CL = 5, parameter COL_WIDTH = 12, // column address width parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY parameter CS_WIDTH = 1, // # of unique CS outputs parameter CKE_WIDTH = 1, // # of cke outputs parameter CWL = 5, parameter DATA_WIDTH = 64, parameter DATA_BUF_ADDR_WIDTH = 5, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of DM (data mask) parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH)) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter ECC = "OFF", parameter ECC_WIDTH = 8, parameter ECC_TEST = "OFF", parameter MC_ERR_ADDR_WIDTH = 31, parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides parameter nAL = 0, // Additive latency (in clk cyc) parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter ORDERING = "NORM", parameter IBUF_LPWR_MODE = "OFF", parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP0 = "IODELAY_MIG0", parameter IODELAY_GRP1 = "IODELAY_MIG1", parameter FPGA_SPEED_GRADE = 1, parameter OUTPUT_DRV = "HIGH", parameter REG_CTRL = "OFF", parameter RTT_NOM = "60", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter tCK = 2500, // pS parameter tCKE = 10000, // pS parameter tFAW = 40000, // pS parameter tPRDI = 1_000_000, // pS parameter tRAS = 37500, // pS parameter tRCD = 12500, // pS parameter tREFI = 7800000, // pS parameter tRFC = 110000, // pS parameter tRP = 12500, // pS parameter tRRD = 10000, // pS parameter tRTP = 7500, // pS parameter tWTR = 7500, // pS parameter tZQI = 128_000_000, // nS parameter tZQCS = 64, // CKs parameter USER_REFRESH = "OFF", // Whether user manages REF parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon parameter WRLVL = "OFF", parameter DEBUG_PORT = "OFF", parameter CAL_WIDTH = "HALF", parameter RANK_WIDTH = 1, parameter RANKS = 4, parameter ODT_WIDTH = 1, parameter ROW_WIDTH = 16, // DRAM address bus width parameter ADDR_WIDTH = 32, parameter APP_MASK_WIDTH = 8, parameter APP_DATA_WIDTH = 64, parameter [3:0] BYTE_LANES_B0 = 4'b1111, parameter [3:0] BYTE_LANES_B1 = 4'b1111, parameter [3:0] BYTE_LANES_B2 = 4'b1111, parameter [3:0] BYTE_LANES_B3 = 4'b1111, parameter [3:0] BYTE_LANES_B4 = 4'b1111, parameter [3:0] DATA_CTL_B0 = 4'hc, parameter [3:0] DATA_CTL_B1 = 4'hf, parameter [3:0] DATA_CTL_B2 = 4'hf, parameter [3:0] DATA_CTL_B3 = 4'h0, parameter [3:0] DATA_CTL_B4 = 4'h0, parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000, parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000, parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000, // control/address/data pin mapping parameters parameter [143:0] CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter [191:0] ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter [35:0] BANK_MAP = 36'h000_000_000, parameter [11:0] CAS_MAP = 12'h000, parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00, parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter [11:0] PARITY_MAP = 12'h000, parameter [11:0] RAS_MAP = 12'h000, parameter [11:0] WE_MAP = 12'h000, parameter [143:0] DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000, parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001, parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN", // calibration Address. The address given below will be used for calibration // read and write operations. parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address parameter SIM_BYPASS_INIT_CAL = "OFF", parameter REFCLK_FREQ = 300.0, parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering parameter SKIP_CALIB = "FALSE", parameter TAPSPERKCLK = 56, parameter C_S_AXI_ID_WIDTH = 4, // Width of all master and slave ID signals. // # = >= 1. parameter C_S_AXI_ADDR_WIDTH = 30, // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and // M_AXI_ARADDR for all SI/MI slots. // # = 32. parameter C_S_AXI_DATA_WIDTH = 32, // Width of WDATA and RDATA on SI slot. // Must be <= APP_DATA_WIDTH. // # = 32, 64, 128, 256. parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1, // Indicates whether to instatiate upsizer // Range: 0, 1 parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG", // Indicates the Arbitration // Allowed values - "TDM", "ROUND_ROBIN", // "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT" parameter C_S_AXI_REG_EN0 = 20'h00000, // Instatiates register slices before upsizer. // The type of register is specified for each channel // in a vector. 4 bits per channel are used. // C_S_AXI_REG_EN0[03:00] = AW CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[07:04] = W CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[11:08] = B CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[15:12] = AR CHANNEL REGISTER SLICE // C_S_AXI_REG_EN0[20:16] = R CHANNEL REGISTER SLICE // Possible values for each channel are: // // 0 => BYPASS = The channel is just wired through the // module. // 1 => FWD = The master VALID and payload signals // are registrated. // 2 => REV = The slave ready signal is registrated // 3 => FWD_REV = Both FWD and REV // 4 => SLAVE_FWD = All slave side signals and master // VALID and payload are registrated. // 5 => SLAVE_RDY = All slave side signals and master // READY are registrated. // 6 => INPUTS = Slave and Master side inputs are // registrated. parameter C_S_AXI_REG_EN1 = 20'h00000, // Same as C_S_AXI_REG_EN0, but this register is after // the upsizer parameter C_S_AXI_CTRL_ADDR_WIDTH = 32, // Width of AXI-4-Lite address bus parameter C_S_AXI_CTRL_DATA_WIDTH = 32, // Width of AXI-4-Lite data buses parameter C_S_AXI_BASEADDR = 32'h0000_0000, // Base address of AXI4 Memory Mapped bus. parameter C_ECC_ONOFF_RESET_VALUE = 1, // Controls ECC on/off value at startup/reset parameter C_ECC_CE_COUNTER_WIDTH = 8, // The external memory to controller clock ratio. parameter FPGA_VOLT_TYPE = "N" ) ( // Clock and reset ports input clk, input clk_div2, input rst_div2, input [1:0] clk_ref, input mem_refclk , input freq_refclk , input pll_lock, input sync_pulse , input mmcm_ps_clk, input poc_sample_pd, input rst, // memory interface ports inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs_n, inout [DQS_WIDTH-1:0] ddr_dqs, output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CK_WIDTH-1:0] ddr_ck_n, output [CK_WIDTH-1:0] ddr_ck, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_ras_n, output ddr_reset_n, output ddr_parity, output ddr_we_n, output [BM_CNT_WIDTH-1:0] bank_mach_next, output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_o, output [2*nCK_PER_CLK-1:0] app_ecc_single_err, input app_sr_req, output app_sr_active, input app_ref_req, output app_ref_ack, input app_zq_req, output app_zq_ack, // Ports to be used with SKIP_CALIB defined output calib_tap_req, input [6:0] calib_tap_addr, input calib_tap_load, input [7:0] calib_tap_val, input calib_tap_load_done, // temperature monitor ports input [11:0] device_temp, //phase shift clock control output psen, output psincdec, input psdone, // debug logic ports input dbg_idel_down_all, input dbg_idel_down_cpt, input dbg_idel_up_all, input dbg_idel_up_cpt, input dbg_sel_all_idel_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [1:0] dbg_rdlvl_start, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output dbg_wrlvl_done, output dbg_wrlvl_err, output dbg_wrlvl_start, output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, input aresetn, // Slave Interface Write Address Ports input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid, input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input [0:0] s_axi_awlock, input [3:0] s_axi_awcache, input [2:0] s_axi_awprot, input [3:0] s_axi_awqos, input s_axi_awvalid, output s_axi_awready, // Slave Interface Write Data Ports input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata, input [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, // Slave Interface Write Response Ports input s_axi_bready, output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, // Slave Interface Read Address Ports input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid, input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input [0:0] s_axi_arlock, input [3:0] s_axi_arcache, input [2:0] s_axi_arprot, input [3:0] s_axi_arqos, input s_axi_arvalid, output s_axi_arready, // Slave Interface Read Data Ports input s_axi_rready, output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, // AXI CTRL port input s_axi_ctrl_awvalid, output s_axi_ctrl_awready, input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr, // Slave Interface Write Data Ports input s_axi_ctrl_wvalid, output s_axi_ctrl_wready, input [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata, // Slave Interface Write Response Ports output s_axi_ctrl_bvalid, input s_axi_ctrl_bready, output [1:0] s_axi_ctrl_bresp, // Slave Interface Read Address Ports input s_axi_ctrl_arvalid, output s_axi_ctrl_arready, input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr, // Slave Interface Read Data Ports output s_axi_ctrl_rvalid, input s_axi_ctrl_rready, output [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata, output [1:0] s_axi_ctrl_rresp, // Interrupt output output interrupt, output init_calib_complete, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, output dbg_rddata_valid, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output ref_dll_lock, input rst_phaser_ref, input iddr_rst, output [6*RANKS-1:0] dbg_rd_data_offset, output [255:0] dbg_calib_top, output [255:0] dbg_phy_wrlvl, output [255:0] dbg_phy_rdlvl, output [99:0] dbg_phy_wrcal, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [5:0] dbg_pi_counter_read_val, output [8:0] dbg_po_counter_read_val, output dbg_pi_phaselock_start, output dbg_pi_phaselocked_done, output dbg_pi_phaselock_err, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_pi_dqsfound_err, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrcal_err, output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, output [11:0] dbg_pi_phase_locked_phy4lanes, output [6*RANKS-1:0] dbg_calib_rd_data_offset_1, output [6*RANKS-1:0] dbg_calib_rd_data_offset_2, output [5:0] dbg_data_offset, output [5:0] dbg_data_offset_1, output [5:0] dbg_data_offset_2, output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, output [1023:0] dbg_poc ); localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0; localparam INTERFACE = "AXI4"; // Port Interface. // # = UI - User Interface, // = AXI4 - AXI4 Interface. localparam C_FAMILY = "virtex7"; localparam C_MC_DATA_WIDTH_LCL = 2*nCK_PER_CLK*DATA_WIDTH ; // wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; // wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; // wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; wire correct_en; wire [2*nCK_PER_CLK-1:0] raw_not_ecc; wire [2*nCK_PER_CLK-1:0] ecc_single; wire [2*nCK_PER_CLK-1:0] ecc_multiple; wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; wire app_correct_en; wire app_correct_en_i; wire [2*nCK_PER_CLK-1:0] app_raw_not_ecc; wire [DQ_WIDTH/8-1:0] fi_xor_we; wire [DQ_WIDTH-1:0] fi_xor_wrdata; wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; wire wr_data_en; wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; wire rd_data_en; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; wire accept; wire accept_ns; wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; wire rd_data_end; wire use_addr; wire size; wire [ROW_WIDTH-1:0] row; wire [RANK_WIDTH-1:0] rank; wire hi_priority; wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr; wire [COL_WIDTH-1:0] col; wire [2:0] cmd; wire [BANK_WIDTH-1:0] bank; wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask; wire [APP_DATA_WIDTH-1:0] app_rd_data; wire app_rd_data_end; wire app_rd_data_valid; wire app_rdy; wire app_wdf_rdy; wire [ADDR_WIDTH-1:0] app_addr; wire [2:0] app_cmd; wire app_en; wire app_hi_pri; wire app_sz; wire [APP_DATA_WIDTH-1:0] app_wdf_data; wire [C_MC_DATA_WIDTH_LCL-1:0] app_wdf_data_axi_o; wire app_wdf_end; wire [APP_MASK_WIDTH-1:0] app_wdf_mask; wire [C_MC_DATA_WIDTH_LCL/8-1:0] app_wdf_mask_axi_o; wire app_wdf_wren; wire app_sr_req_i; wire app_sr_active_i; wire app_ref_req_i; wire app_ref_ack_i; wire app_zq_req_i; wire app_zq_ack_i; wire rst_tg_mc; wire error; wire init_wrcal_complete; reg reset /* synthesis syn_maxfan = 10 */; reg init_calib_complete_r; //*************************************************************************** // Added a single register stage for the calib_done to fix timing //*************************************************************************** always @(posedge clk) init_calib_complete_r <= init_calib_complete; always @(posedge clk) reset <= #TCQ (rst | rst_tg_mc); mig_7series_v4_0_mem_intfc # ( .TCQ (TCQ), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .ADDR_CMD_MODE (ADDR_CMD_MODE), .AL (AL), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .CA_MIRROR (CA_MIRROR), .CK_WIDTH (CK_WIDTH), .COL_WIDTH (COL_WIDTH), .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), .CS_WIDTH (CS_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .CKE_WIDTH (CKE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .MASTER_PHY_CTL (MASTER_PHY_CTL), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .DM_WIDTH (DM_WIDTH), .DQ_CNT_WIDTH (DQ_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), .ECC (ECC), .ECC_WIDTH (ECC_WIDTH), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .REFCLK_FREQ (REFCLK_FREQ), .nAL (nAL), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .ORDERING (ORDERING), .OUTPUT_DRV (OUTPUT_DRV), .IBUF_LPWR_MODE (IBUF_LPWR_MODE), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .REG_CTRL (REG_CTRL), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .CL (CL), .CWL (CWL), .tCK (tCK), .tCKE (tCKE), .tFAW (tFAW), .tPRDI (tPRDI), .tRAS (tRAS), .tRCD (tRCD), .tREFI (tREFI), .tRFC (tRFC), .tRP (tRP), .tRRD (tRRD), .tRTP (tRTP), .tWTR (tWTR), .tZQI (tZQI), .tZQCS (tZQCS), .USER_REFRESH (USER_REFRESH), .TEMP_MON_EN (TEMP_MON_EN), .WRLVL (WRLVL), .DEBUG_PORT (DEBUG_PORT), .CAL_WIDTH (CAL_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CKE_ODT_AUX (CKE_ODT_AUX), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .STARVE_LIMIT (STARVE_LIMIT), .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .TAPSPERKCLK (TAPSPERKCLK), .SKIP_CALIB (SKIP_CALIB), .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) ) mem_intfc0 ( .clk (clk), .clk_div2 (clk_div2), .rst_div2 (rst_div2), .clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]), .mem_refclk (mem_refclk), //memory clock .freq_refclk (freq_refclk), .pll_lock (pll_lock), .sync_pulse (sync_pulse), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .rst (rst), .error (error), .reset (reset), .rst_tg_mc (rst_tg_mc), .ddr_dq (ddr_dq), .ddr_dqs_n (ddr_dqs_n), .ddr_dqs (ddr_dqs), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_ck_n (ddr_ck_n), .ddr_ck (ddr_ck), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_odt (ddr_odt), .ddr_ras_n (ddr_ras_n), .ddr_reset_n (ddr_reset_n), .ddr_parity (ddr_parity), .ddr_we_n (ddr_we_n), .slot_0_present (SLOT_0_CONFIG), .slot_1_present (SLOT_1_CONFIG), .correct_en (correct_en), .bank (bank), .cmd (cmd), .col (col), .data_buf_addr (data_buf_addr), .wr_data (wr_data), .wr_data_mask (wr_data_mask), .rank (rank), .raw_not_ecc (raw_not_ecc), .row (row), .hi_priority (hi_priority), .size (size), .use_addr (use_addr), .accept (accept), .accept_ns (accept_ns), .ecc_single (ecc_single), .ecc_multiple (ecc_multiple), .ecc_err_addr (ecc_err_addr), .rd_data (rd_data), .rd_data_addr (rd_data_addr), .rd_data_en (rd_data_en), .rd_data_end (rd_data_end), .rd_data_offset (rd_data_offset), .wr_data_addr (wr_data_addr), .wr_data_en (wr_data_en), .wr_data_offset (wr_data_offset), .bank_mach_next (bank_mach_next), .init_calib_complete (init_calib_complete), .init_wrcal_complete (init_wrcal_complete), .app_sr_req (app_sr_req_i), .app_sr_active (app_sr_active_i), .app_ref_req (app_ref_req_i), .app_ref_ack (app_ref_ack_i), .app_zq_req (app_zq_req_i), .app_zq_ack (app_zq_ack_i), // skip calibration i/f .calib_tap_req (calib_tap_req), .calib_tap_load (calib_tap_load), .calib_tap_addr (calib_tap_addr), .calib_tap_val (calib_tap_val), .calib_tap_load_done (calib_tap_load_done), .device_temp (device_temp), .psen (psen), .psincdec (psincdec), .psdone (psdone), .fi_xor_we (fi_xor_we), .fi_xor_wrdata (fi_xor_wrdata), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_calib_top (dbg_calib_top), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_rddata (dbg_rddata), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_sel_pi_incdec (dbg_sel_pi_incdec), .dbg_sel_po_incdec (dbg_sel_po_incdec), .dbg_byte_sel (dbg_byte_sel), .dbg_pi_f_inc (dbg_pi_f_inc), .dbg_pi_f_dec (dbg_pi_f_dec), .dbg_po_f_inc (dbg_po_f_inc), .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), .dbg_po_f_dec (dbg_po_f_dec), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_rddata_valid (dbg_rddata_valid), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl), .dbg_pi_counter_read_val (dbg_pi_counter_read_val), .dbg_po_counter_read_val (dbg_po_counter_read_val), .ref_dll_lock (ref_dll_lock), .rst_phaser_ref (rst_phaser_ref), .iddr_rst (iddr_rst), .dbg_rd_data_offset (dbg_rd_data_offset), .dbg_phy_init (dbg_phy_init), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .dbg_dqs_found_cal (dbg_dqs_found_cal), .dbg_pi_phaselock_start (dbg_pi_phaselock_start), .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), .dbg_pi_phaselock_err (dbg_pi_phaselock_err), .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), .dbg_wrcal_start (dbg_wrcal_start), .dbg_wrcal_done (dbg_wrcal_done), .dbg_wrcal_err (dbg_wrcal_err), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), .dbg_data_offset (dbg_data_offset), .dbg_data_offset_1 (dbg_data_offset_1), .dbg_data_offset_2 (dbg_data_offset_2), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), .prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), .dbg_poc (dbg_poc[1023:0]) ); generate if(ECC_TEST == "ON") begin if(DQ_WIDTH == 72) begin assign app_wdf_data = {app_wdf_data_axi_o[0+:(8*2*nCK_PER_CLK)],app_wdf_data_axi_o} ; assign app_wdf_mask = {app_wdf_mask_axi_o[0+:(2*nCK_PER_CLK)],app_wdf_mask_axi_o} ; end else begin end end else begin assign app_wdf_data = app_wdf_data_axi_o ; assign app_wdf_mask = app_wdf_mask_axi_o ; end endgenerate mig_7series_v4_0_ui_top # ( .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .BANK_WIDTH (BANK_WIDTH), .COL_WIDTH (COL_WIDTH), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .ECC (ECC), .ECC_TEST (ECC_TEST), .nCK_PER_CLK (nCK_PER_CLK), .ORDERING (ORDERING), .RANKS (RANKS), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH), .MEM_ADDR_ORDER (MEM_ADDR_ORDER) ) u_ui_top ( .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), .wr_data (wr_data[APP_DATA_WIDTH-1:0]), .use_addr (use_addr), .size (size), .row (row), .raw_not_ecc (raw_not_ecc), .rank (rank), .hi_priority (hi_priority), .data_buf_addr (data_buf_addr), .col (col), .cmd (cmd), .bank (bank), .app_wdf_rdy (app_wdf_rdy), .app_rdy (app_rdy), .app_rd_data_valid (app_rd_data_valid), .app_rd_data_end (app_rd_data_end), .app_rd_data (app_rd_data), .correct_en (correct_en), .wr_data_offset (wr_data_offset), .wr_data_en (wr_data_en), .wr_data_addr (wr_data_addr), .rst (reset), .rd_data_offset (rd_data_offset), .rd_data_end (rd_data_end), .rd_data_en (rd_data_en), .rd_data_addr (rd_data_addr), .rd_data (rd_data[APP_DATA_WIDTH-1:0]), .ecc_multiple (ecc_multiple), .ecc_single (ecc_single), .clk (clk), .app_wdf_wren (app_wdf_wren), .app_wdf_mask (app_wdf_mask), .app_wdf_end (app_wdf_end), .app_wdf_data (app_wdf_data), .app_sz (app_sz), .app_hi_pri (app_hi_pri), .app_en (app_en), .app_cmd (app_cmd), .app_addr (app_addr), .accept_ns (accept_ns), .accept (accept), // ECC ports .app_raw_not_ecc (app_raw_not_ecc), .app_ecc_multiple_err (app_ecc_multiple_err_o), .app_ecc_single_err (app_ecc_single_err), .app_correct_en (app_correct_en_i), .app_sr_req (app_sr_req), .sr_req (app_sr_req_i), .sr_active (app_sr_active_i), .app_sr_active (app_sr_active), .app_ref_req (app_ref_req), .ref_req (app_ref_req_i), .ref_ack (app_ref_ack_i), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .zq_req (app_zq_req_i), .zq_ack (app_zq_ack_i), .app_zq_ack (app_zq_ack) ); mig_7series_v4_0_axi_mc # ( .C_FAMILY (C_FAMILY), .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH), .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH), .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), .C_MC_DATA_WIDTH (C_MC_DATA_WIDTH_LCL), .C_MC_ADDR_WIDTH (ADDR_WIDTH), .C_MC_BURST_MODE (BURST_MODE), .C_MC_nCK_PER_CLK (nCK_PER_CLK), .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST), .C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM), .C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0), .C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1), .C_ECC (ECC) ) u_axi_mc ( .aclk (clk), .aresetn (aresetn), // Slave Interface Write Address Ports .s_axi_awid (s_axi_awid), .s_axi_awaddr (s_axi_awaddr), .s_axi_awlen (s_axi_awlen), .s_axi_awsize (s_axi_awsize), .s_axi_awburst (s_axi_awburst), .s_axi_awlock (s_axi_awlock), .s_axi_awcache (s_axi_awcache), .s_axi_awprot (s_axi_awprot), .s_axi_awqos (s_axi_awqos), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), // Slave Interface Write Data Ports .s_axi_wdata (s_axi_wdata), .s_axi_wstrb (s_axi_wstrb), .s_axi_wlast (s_axi_wlast), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), // Slave Interface Write Response Ports .s_axi_bid (s_axi_bid), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), // Slave Interface Read Address Ports .s_axi_arid (s_axi_arid), .s_axi_araddr (s_axi_araddr), .s_axi_arlen (s_axi_arlen), .s_axi_arsize (s_axi_arsize), .s_axi_arburst (s_axi_arburst), .s_axi_arlock (s_axi_arlock), .s_axi_arcache (s_axi_arcache), .s_axi_arprot (s_axi_arprot), .s_axi_arqos (s_axi_arqos), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), // Slave Interface Read Data Ports .s_axi_rid (s_axi_rid), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rlast (s_axi_rlast), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready), // MC Master Interface //CMD PORT .mc_app_en (app_en), .mc_app_cmd (app_cmd), .mc_app_sz (app_sz), .mc_app_addr (app_addr), .mc_app_hi_pri (app_hi_pri), .mc_app_rdy (app_rdy), .mc_init_complete (init_calib_complete_r), //DATA PORT .mc_app_wdf_wren (app_wdf_wren), .mc_app_wdf_mask (app_wdf_mask_axi_o), .mc_app_wdf_data (app_wdf_data_axi_o), .mc_app_wdf_end (app_wdf_end), .mc_app_wdf_rdy (app_wdf_rdy), .mc_app_rd_valid (app_rd_data_valid), .mc_app_rd_data (app_rd_data), .mc_app_rd_end (app_rd_data_end), .mc_app_ecc_multiple_err (app_ecc_multiple_err_o) ); generate if (ECC == "ON") begin : gen_axi_ctrl_top reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata_r; mig_7series_v4_0_axi_ctrl_top # ( .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH) , .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) , .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH) , .C_S_AXI_BASEADDR (C_S_AXI_BASEADDR) , .C_ECC_TEST (ECC_TEST) , .C_DQ_WIDTH (DQ_WIDTH) , .C_ECC_WIDTH (ECC_WIDTH) , .C_MEM_ADDR_ORDER (MEM_ADDR_ORDER) , .C_BANK_WIDTH (BANK_WIDTH) , .C_ROW_WIDTH (ROW_WIDTH) , .C_COL_WIDTH (COL_WIDTH) , .C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE) , .C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH) , .C_NCK_PER_CLK (nCK_PER_CLK) , .C_MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH) ) axi_ctrl_top_0 ( .aclk (clk) , .aresetn (aresetn) , .s_axi_awvalid (s_axi_ctrl_awvalid) , .s_axi_awready (s_axi_ctrl_awready) , .s_axi_awaddr (s_axi_ctrl_awaddr) , .s_axi_wvalid (s_axi_ctrl_wvalid) , .s_axi_wready (s_axi_ctrl_wready) , .s_axi_wdata (s_axi_ctrl_wdata) , .s_axi_bvalid (s_axi_ctrl_bvalid) , .s_axi_bready (s_axi_ctrl_bready) , .s_axi_bresp (s_axi_ctrl_bresp) , .s_axi_arvalid (s_axi_ctrl_arvalid) , .s_axi_arready (s_axi_ctrl_arready) , .s_axi_araddr (s_axi_ctrl_araddr) , .s_axi_rvalid (s_axi_ctrl_rvalid) , .s_axi_rready (s_axi_ctrl_rready) , .s_axi_rdata (s_axi_ctrl_rdata) , .s_axi_rresp (s_axi_ctrl_rresp) , .interrupt (interrupt) , .init_complete (init_calib_complete_r) , .ecc_single (ecc_single) , .ecc_multiple (ecc_multiple) , .ecc_err_addr (ecc_err_addr) , .app_correct_en (app_correct_en) , .dfi_rddata (dbg_rddata_r) , .fi_xor_we (fi_xor_we) , .fi_xor_wrdata (fi_xor_wrdata) ); // dbg_rddata delayed one cycle to match ecc_* always @(posedge clk) begin dbg_rddata_r <= dbg_rddata; end if(ECC_TEST == "ON") begin assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b1}}; assign app_correct_en_i = 'b0 ; end else begin assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}}; assign app_correct_en_i = app_correct_en ; end end else begin : gen_no_axi_ctrl_top assign s_axi_ctrl_awready = 1'b0; assign s_axi_ctrl_wready = 1'b0; assign s_axi_ctrl_bvalid = 1'b0; assign s_axi_ctrl_bresp = 2'b0; assign s_axi_ctrl_arready = 1'b0; assign s_axi_ctrl_rvalid = 1'b0; assign s_axi_ctrl_rdata = {C_S_AXI_CTRL_DATA_WIDTH{1'b0}}; assign s_axi_ctrl_rresp = 2'b0; assign interrupt = 1'b0; assign app_correct_en = 1'b1; assign app_raw_not_ecc = 4'b0; assign fi_xor_we = {DQ_WIDTH/8{1'b0}}; assign fi_xor_wrdata = {DQ_WIDTH{1'b0}}; end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v ================================================ /***************************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $ // $Author: $ // $DateTime: $ // $Change: $ // Description: // This verilog file is a paramertizable I/O termination for // the single byte lane. // to create a N byte-lane wide phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // ////////////////////////////////////////////////////////////////// *****************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_byte_group_io #( // bit lane existance parameter BITLANES = 12'b1111_1111_1111, parameter BITLANES_OUTONLY = 12'b0000_0000_0000, parameter PO_DATA_CTL = "FALSE", parameter OSERDES_DATA_RATE = "DDR", parameter OSERDES_DATA_WIDTH = 4, parameter IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter IDELAYE2_IDELAY_VALUE = 00, parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter real TCK = 2500.0, // local usage only, don't pass down parameter BUS_WIDTH = 12, parameter SYNTHESIS = "FALSE" ) ( input [9:0] mem_dq_in, output [BUS_WIDTH-1:0] mem_dq_out, output [BUS_WIDTH-1:0] mem_dq_ts, input mem_dqs_in, output mem_dqs_out, output mem_dqs_ts, output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used output dqs_to_phaser, input iserdes_clk, input iserdes_clkb, input iserdes_clkdiv, input phy_clk, input rst, input oserdes_rst, input iserdes_rst, input [1:0] oserdes_dqs, input [1:0] oserdes_dqsts, input [(4*BUS_WIDTH)-1:0] oserdes_dq, input [1:0] oserdes_dqts, input oserdes_clk, input oserdes_clk_delayed, input oserdes_clkdiv, input idelay_inc, input idelay_ce, input idelay_ld, input idelayctrl_refclk, input [29:0] fine_delay , input fine_delay_sel ); /// INSTANCES localparam ISERDES_DQ_DATA_RATE = "DDR"; localparam ISERDES_DQ_DATA_WIDTH = 4; localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE"; localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE"; localparam ISERDES_DQ_INIT_Q1 = 1'b0; localparam ISERDES_DQ_INIT_Q2 = 1'b0; localparam ISERDES_DQ_INIT_Q3 = 1'b0; localparam ISERDES_DQ_INIT_Q4 = 1'b0; localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3"; localparam ISERDES_NUM_CE = 2; localparam ISERDES_DQ_IOBDELAY = "IFD"; localparam ISERDES_DQ_OFB_USED = "FALSE"; localparam ISERDES_DQ_SERDES_MODE = "MASTER"; localparam ISERDES_DQ_SRVAL_Q1 = 1'b0; localparam ISERDES_DQ_SRVAL_Q2 = 1'b0; localparam ISERDES_DQ_SRVAL_Q3 = 1'b0; localparam ISERDES_DQ_SRVAL_Q4 = 1'b0; localparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? "FALSE" : "TRUE"; wire [BUS_WIDTH-1:0] data_in_dly; wire [BUS_WIDTH-1:0] oserdes_dq_buf; wire [BUS_WIDTH-1:0] oserdes_dqts_buf; wire oserdes_dqs_buf; wire oserdes_dqsts_buf; wire [9:0] data_in; wire tbyte_out; reg [29:0] fine_delay_r; assign mem_dq_out = oserdes_dq_buf; assign mem_dq_ts = oserdes_dqts_buf; assign data_in = mem_dq_in; assign mem_dqs_out = oserdes_dqs_buf; assign mem_dqs_ts = oserdes_dqsts_buf; assign dqs_to_phaser = mem_dqs_in; reg iserdes_clk_d; always @(*) iserdes_clk_d = iserdes_clk; reg idelay_ld_rst; reg rst_r1; reg rst_r2; reg rst_r3; reg rst_r4; always @(posedge phy_clk) begin rst_r1 <= #1 rst; rst_r2 <= #1 rst_r1; rst_r3 <= #1 rst_r2; rst_r4 <= #1 rst_r3; end always @(posedge phy_clk) begin if (rst) idelay_ld_rst <= #1 1'b1; else if (rst_r4) idelay_ld_rst <= #1 1'b0; end always @ (posedge phy_clk) begin if(rst) fine_delay_r <= #1 1'b0; else if(fine_delay_sel) fine_delay_r <= #1 fine_delay; end genvar i; generate for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_ if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_ ISERDESE2 #( .DATA_RATE ( ISERDES_DQ_DATA_RATE), .DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH), .DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN), .DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN), .INIT_Q1 ( ISERDES_DQ_INIT_Q1), .INIT_Q2 ( ISERDES_DQ_INIT_Q2), .INIT_Q3 ( ISERDES_DQ_INIT_Q3), .INIT_Q4 ( ISERDES_DQ_INIT_Q4), .INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE), .NUM_CE ( ISERDES_NUM_CE), .IOBDELAY ( ISERDES_DQ_IOBDELAY), .OFB_USED ( ISERDES_DQ_OFB_USED), .SERDES_MODE ( ISERDES_DQ_SERDES_MODE), .SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1), .SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2), .SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3), .SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4) ) iserdesdq ( .O (), .Q1 (iserdes_dout[4*i + 3]), .Q2 (iserdes_dout[4*i + 2]), .Q3 (iserdes_dout[4*i + 1]), .Q4 (iserdes_dout[4*i + 0]), .Q5 (), .Q6 (), .Q7 (), .Q8 (), .SHIFTOUT1 (), .SHIFTOUT2 (), .BITSLIP (1'b0), .CE1 (1'b1), .CE2 (1'b1), .CLK (iserdes_clk_d), .CLKB (!iserdes_clk_d), .CLKDIVP (iserdes_clkdiv), .CLKDIV (), .DDLY (data_in_dly[i]), .D (data_in[i]), // dedicated route to iob for debugging // or as needed, select with IOBDELAY .DYNCLKDIVSEL (1'b0), .DYNCLKSEL (1'b0), // NOTE: OCLK is not used in this design, but is required to meet // a design rule check in map and bitgen. Do not disconnect it. .OCLK (oserdes_clk), .OCLKB (), .OFB (), .RST (1'b0), // .RST (iserdes_rst), .SHIFTIN1 (1'b0), .SHIFTIN2 (1'b0) ); localparam IDELAYE2_CINVCTRL_SEL = "FALSE"; localparam IDELAYE2_DELAY_SRC = "IDATAIN"; localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE"; localparam IDELAYE2_PIPE_SEL = "FALSE"; localparam IDELAYE2_ODELAY_TYPE = "FIXED"; localparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 : (FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0; localparam IDELAYE2_SIGNAL_PATTERN = "DATA"; localparam IDELAYE2_FINEDELAY_IN = "ADD_DLY"; if(IDELAY_FINEDELAY_USE == "TRUE") begin: idelay_finedelay_dq (* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL), .DELAY_SRC ( IDELAYE2_DELAY_SRC), .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE), .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE), .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE), .PIPE_SEL ( IDELAYE2_PIPE_SEL), .FINEDELAY ( IDELAYE2_FINEDELAY_IN), .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ), .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN) ) idelaye2 ( .CNTVALUEOUT (), .DATAOUT (data_in_dly[i]), .C (phy_clk), // automatically wired by ISE .CE (idelay_ce), .CINVCTRL (), .CNTVALUEIN (5'b00000), .DATAIN (1'b0), .IDATAIN (data_in[i]), .IFDLY (fine_delay_r[i*3+:3]), .INC (idelay_inc), .LD (idelay_ld | idelay_ld_rst), .LDPIPEEN (1'b0), .REGRST (rst) ); end else begin : idelay_dq (* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2 #( .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL), .DELAY_SRC ( IDELAYE2_DELAY_SRC), .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE), .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE), .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE), .PIPE_SEL ( IDELAYE2_PIPE_SEL), .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ), .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN) ) idelaye2 ( .CNTVALUEOUT (), .DATAOUT (data_in_dly[i]), .C (phy_clk), // automatically wired by ISE .CE (idelay_ce), .CINVCTRL (), .CNTVALUEIN (5'b00000), .DATAIN (1'b0), .IDATAIN (data_in[i]), .INC (idelay_inc), .LD (idelay_ld | idelay_ld_rst), .LDPIPEEN (1'b0), .REGRST (rst) ); end end // iserdes_dq else begin assign iserdes_dout[4*i + 3] = 0; assign iserdes_dout[4*i + 2] = 0; assign iserdes_dout[4*i + 1] = 0; assign iserdes_dout[4*i + 0] = 0; end end // input_ endgenerate // iserdes_dq_ localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE; localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ; localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH; localparam OSERDES_DQ_INIT_OQ = 1'b1; localparam OSERDES_DQ_INIT_TQ = 1'b1; localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT"; localparam OSERDES_DQ_ODELAY_USED = 0; localparam OSERDES_DQ_SERDES_MODE = "MASTER"; localparam OSERDES_DQ_SRVAL_OQ = 1'b1; localparam OSERDES_DQ_SRVAL_TQ = 1'b1; // note: obuf used in control path case, no ts input so width irrelevant localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1; localparam OSERDES_DQS_DATA_RATE_OQ = "DDR"; localparam OSERDES_DQS_DATA_RATE_TQ = "DDR"; localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr localparam OSERDES_DQS_DATA_WIDTH = 4; localparam ODDR_CLK_EDGE = "SAME_EDGE"; localparam OSERDES_TBYTE_CTL = "TRUE"; generate localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH; if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts OSERDESE2 #( .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), .INIT_OQ (OSERDES_DQ_INIT_OQ), .INIT_TQ (OSERDES_DQ_INIT_TQ), .SERDES_MODE (OSERDES_DQ_SERDES_MODE), .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ), .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH), .TBYTE_CTL ("TRUE"), .TBYTE_SRC ("TRUE") ) oserdes_slave_ts ( .OFB (), .OQ (), .SHIFTOUT1 (), // not extended .SHIFTOUT2 (), // not extended .TFB (), .TQ (), .CLK (oserdes_clk), .CLKDIV (oserdes_clkdiv), .D1 (), .D2 (), .D3 (), .D4 (), .D5 (), .D6 (), .D7 (), .D8 (), .OCE (1'b1), .RST (oserdes_rst), .SHIFTIN1 (), // not extended .SHIFTIN2 (), // not extended .T1 (oserdes_dqts[0]), .T2 (oserdes_dqts[0]), .T3 (oserdes_dqts[1]), .T4 (oserdes_dqts[1]), .TCE (1'b1), .TBYTEOUT (tbyte_out), .TBYTEIN (tbyte_out) ); end // slave_ts for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_ if ( BITLANES[i]) begin : oserdes_dq_ if ( PO_DATA_CTL == "TRUE" ) begin : ddr OSERDESE2 #( .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), .INIT_OQ (OSERDES_DQ_INIT_OQ), .INIT_TQ (OSERDES_DQ_INIT_TQ), .SERDES_MODE (OSERDES_DQ_SERDES_MODE), .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ), .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH), .TBYTE_CTL (OSERDES_TBYTE_CTL), .TBYTE_SRC ("FALSE") ) oserdes_dq_i ( .OFB (), .OQ (oserdes_dq_buf[i]), .SHIFTOUT1 (), // not extended .SHIFTOUT2 (), // not extended .TBYTEOUT (), .TFB (), .TQ (oserdes_dqts_buf[i]), .CLK (oserdes_clk), .CLKDIV (oserdes_clkdiv), .D1 (oserdes_dq[4 * i + 0]), .D2 (oserdes_dq[4 * i + 1]), .D3 (oserdes_dq[4 * i + 2]), .D4 (oserdes_dq[4 * i + 3]), .D5 (), .D6 (), .D7 (), .D8 (), .OCE (1'b1), .RST (oserdes_rst), .SHIFTIN1 (), // not extended .SHIFTIN2 (), // not extended .T1 (/*oserdes_dqts[0]*/), .T2 (/*oserdes_dqts[0]*/), .T3 (/*oserdes_dqts[1]*/), .T4 (/*oserdes_dqts[1]*/), .TCE (1'b1), .TBYTEIN (tbyte_out) ); end else begin : sdr OSERDESE2 #( .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), .INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/), .INIT_TQ (OSERDES_DQ_INIT_TQ), .SERDES_MODE (OSERDES_DQ_SERDES_MODE), .SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/), .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH) ) oserdes_dq_i ( .OFB (), .OQ (oserdes_dq_buf[i]), .SHIFTOUT1 (), // not extended .SHIFTOUT2 (), // not extended .TBYTEOUT (), .TFB (), .TQ (), .CLK (oserdes_clk), .CLKDIV (oserdes_clkdiv), .D1 (oserdes_dq[4 * i + 0]), .D2 (oserdes_dq[4 * i + 1]), .D3 (oserdes_dq[4 * i + 2]), .D4 (oserdes_dq[4 * i + 3]), .D5 (), .D6 (), .D7 (), .D8 (), .OCE (1'b1), .RST (oserdes_rst), .SHIFTIN1 (), // not extended .SHIFTIN2 (), // not extended .T1 (), .T2 (), .T3 (), .T4 (), .TCE (1'b1), .TBYTEIN () ); end // ddr end // oserdes_dq_ end // output_ endgenerate generate if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) oddr_dqs ( .Q (oserdes_dqs_buf), .D1 (oserdes_dqs[0]), .D2 (oserdes_dqs[1]), .C (oserdes_clk_delayed), .R (1'b0), .S (), .CE (1'b1) ); ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) oddr_dqsts ( .Q (oserdes_dqsts_buf), .D1 (oserdes_dqsts[0]), .D2 (oserdes_dqsts[0]), .C (oserdes_clk_delayed), .R (), .S (1'b0), .CE (1'b1) ); end // sdr rate else begin:null_dqs end endgenerate endmodule // byte_group_io ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v ================================================ /*********************************************************** -- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is a parameterizable single 10 or 12 bit byte lane. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // //////////////////////////////////////////////////////////// ***********************************************************/ `timescale 1ps/1ps //`include "phy.vh" module mig_7series_v4_0_ddr_byte_lane #( // these are used to scale the index into phaser,calib,scan,mc vectors // to access fields used in this instance parameter ABCD = "A", // A,B,C, or D parameter PO_DATA_CTL = "FALSE", parameter BITLANES = 12'b1111_1111_1111, parameter BITLANES_OUTONLY = 12'b1111_1111_1111, parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter RCLK_SELECT_LANE = "B", parameter PC_CLK_RATIO = 4, parameter USE_PRE_POST_FIFO = "FALSE", //OUT_FIFO parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_ARRAY_MODE = "UNDECLARED", parameter OF_OUTPUT_DISABLE = "FALSE", parameter OF_SYNCHRONOUS_MODE = "TRUE", //IN_FIFO parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_ARRAY_MODE = "UNDECLARED", parameter IF_SYNCHRONOUS_MODE = "TRUE", //PHASER_IN parameter PI_BURST_MODE = "TRUE", parameter PI_CLKOUT_DIV = 2, parameter PI_FREQ_REF_DIV = "NONE", parameter PI_FINE_DELAY = 1, parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter PI_SEL_CLK_OFFSET = 0, parameter PI_SYNC_IN_DIV_RST = "FALSE", //PHASER_OUT parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2, parameter PO_FINE_DELAY = 0, parameter PO_COARSE_BYPASS = "FALSE", parameter PO_COARSE_DELAY = 0, parameter PO_OCLK_DELAY = 0, parameter PO_OCLKDELAY_INV = "TRUE", parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter PO_SYNC_IN_DIV_RST = "FALSE", // OSERDES parameter OSERDES_DATA_RATE = "DDR", parameter OSERDES_DATA_WIDTH = 4, //IDELAY parameter IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter IDELAYE2_IDELAY_VALUE = 00, parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", // local constants, do not pass in from above parameter BUS_WIDTH = 12, parameter MSB_BURST_PEND_PO = 3, parameter MSB_BURST_PEND_PI = 7, parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8, parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1 ,parameter CKE_ODT_AUX = "FALSE" ,parameter PI_DIV2_INCDEC = "FALSE" )( input rst, input phy_clk, input rst_pi_div2, input clk_div2, input freq_refclk, input mem_refclk, input idelayctrl_refclk, input sync_pulse, output [BUS_WIDTH-1:0] mem_dq_out, output [BUS_WIDTH-1:0] mem_dq_ts, input [9:0] mem_dq_in, output mem_dqs_out, output mem_dqs_ts, input mem_dqs_in, output [11:0] ddr_ck_out, output rclk, input if_empty_def, output if_a_empty, output if_empty, output if_a_full, output if_full, output of_a_empty, output of_empty, output of_a_full, output of_full, output pre_fifo_a_full, output [79:0] phy_din, input [79:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus, input idelay_inc, input idelay_ce, input idelay_ld, input if_rst, input [2:0] byte_rd_en_oth_lanes, input [1:0] byte_rd_en_oth_banks, output byte_rd_en, output po_coarse_overflow, output po_fine_overflow, output [8:0] po_counter_read_val, input po_fine_enable, input po_coarse_enable, input [1:0] po_en_calib, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, input [1:0] pi_en_calib, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output wire pi_iserdes_rst, output pi_phase_locked, output pi_fine_overflow, output [5:0] pi_counter_read_val, output wire pi_dqs_found, output dqs_out_of_range, input [29:0] fine_delay, input fine_delay_sel ); localparam PHASER_INDEX = (ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0)); localparam L_OF_ARRAY_MODE = (OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE : (PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4"; localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE : (PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8"; localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ; localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4; localparam real L_FREQ_REF_PERIOD_NS = (TCK >= 2500.0) ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0; // DIV2 change localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0; localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0; localparam ODDR_CLK_EDGE = "SAME_EDGE"; localparam PO_DCD_CORRECTION = "ON"; localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000; localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK >= 2500)) ? 1 : 0; // DIV2 change localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK >= 2500)) ? "001" : "000"; // DIV2 change wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [3:0] of_q9; wire [3:0] of_q8; wire [3:0] of_q7; wire [7:0] of_q6; wire [7:0] of_q5; wire [3:0] of_q4; wire [3:0] of_q3; wire [3:0] of_q2; wire [3:0] of_q1; wire [3:0] of_q0; wire [7:0] of_d9; wire [7:0] of_d8; wire [7:0] of_d7; wire [7:0] of_d6; wire [7:0] of_d5; wire [7:0] of_d4; wire [7:0] of_d3; wire [7:0] of_d2; wire [7:0] of_d1; wire [7:0] of_d0; wire [7:0] if_q9; wire [7:0] if_q8; wire [7:0] if_q7; wire [7:0] if_q6; wire [7:0] if_q5; wire [7:0] if_q4; wire [7:0] if_q3; wire [7:0] if_q2; wire [7:0] if_q1; wire [7:0] if_q0; wire [3:0] if_d9; wire [3:0] if_d8; wire [3:0] if_d7; wire [3:0] if_d6; wire [3:0] if_d5; wire [3:0] if_d4; wire [3:0] if_d3; wire [3:0] if_d2; wire [3:0] if_d1; wire [3:0] if_d0; wire [3:0] dummy_i5; wire [3:0] dummy_i6; wire [48-1:0] of_dqbus; wire [10*4-1:0] iserdes_dout; wire iserdes_clk; wire iserdes_clkdiv; wire ififo_wr_enable; wire phy_rd_en_; wire dqs_to_phaser; wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en; wire if_empty_; wire if_a_empty_; wire if_full_; wire if_a_full_; wire po_oserdes_rst; wire empty_post_fifo; reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */; wire [79:0] rd_data; reg [79:0] rd_data_r; reg ififo_rst = 1'b1; reg ofifo_rst = 1'b1; wire of_wren_pre; wire [79:0] pre_fifo_dout; wire pre_fifo_full; wire pre_fifo_rden; wire [5:0] ddr_ck_out_q; wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */; wire oserdes_clkdiv; wire oserdes_clk_delayed; wire po_rd_enable; always @(posedge phy_clk) begin ififo_rst <= #1 pi_rst_dqs_find | if_rst ; // reset only data o-fifos on reset of dqs_found ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst; end // IN_FIFO EMPTY->RDEN TIMING FIX: // Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO // since the IN_FIFO read pointers are not incr'ed when the FIFO is empty assign #(25) phy_rd_en_ = 1'b1; //assign #(25) phy_rd_en_ = phy_rd_en; generate if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null assign if_empty = 0; assign if_a_empty = 0; assign if_full = 0; assign if_a_full = 0; end else begin : if_empty_gen assign if_empty = empty_post_fifo; assign if_a_empty = if_a_empty_; assign if_full = if_full_; assign if_a_full = if_a_full_; end endgenerate generate if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48 assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0}; assign phy_din = 80'h0; assign byte_rd_en = 1'b1; end else begin : dq_gen_40 assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0}; assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) : ((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en); if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen // IN_FIFO EMPTY->RDEN TIMING FIX: assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0}; always @(posedge phy_clk) begin rd_data_r <= #(025) rd_data; if_empty_r[0] <= #(025) if_empty_; if_empty_r[1] <= #(025) if_empty_; if_empty_r[2] <= #(025) if_empty_; if_empty_r[3] <= #(025) if_empty_; end mig_7series_v4_0_ddr_if_post_fifo # ( .TCQ (25), // simulation CK->Q delay .DEPTH (4), //2 // depth - account for up to 2 cycles of skew .WIDTH (80) // width ) u_ddr_if_post_fifo ( .clk (phy_clk), .rst (ififo_rst), .empty_in (if_empty_r), .rd_en_in (ififo_rd_en_in), .d_in (rd_data_r), .empty_out (empty_post_fifo), .byte_rd_en (byte_rd_en), .d_out (phy_din) ); end else begin : phy_din_gen assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0}; assign empty_post_fifo = if_empty_; end end endgenerate assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout; wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11); generate if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout; mig_7series_v4_0_ddr_of_pre_fifo # ( .TCQ (25), // simulation CK->Q delay .DEPTH (9), // depth - set to 9 to accommodate flow control .WIDTH (80) // width ) u_ddr_of_pre_fifo ( .clk (phy_clk), .rst (ofifo_rst), .full_in (of_full), .wr_en_in (phy_wr_en), .d_in (phy_dout), .wr_en_out (of_wren_pre), .d_out (pre_fifo_dout), .afull (pre_fifo_a_full) ); end else begin // wire direct to ofifo assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout; assign of_wren_pre = phy_wr_en; end endgenerate /////////////////////////////////////////////////////////////////////////////// // Synchronize pi_phase_locked to phy_clk domain /////////////////////////////////////////////////////////////////////////////// wire pi_phase_locked_w; wire pi_dqs_found_w; wire [5:0] pi_counter_read_val_w; generate if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_clk (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r3; reg pi_phase_locked_r4; (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r1; (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r2; (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r3; reg pi_dqs_found_r4; (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r1; (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r2; (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r3; reg [5:0] pi_counter_read_val_r4; always @ (posedge phy_clk) begin pi_phase_locked_r1 <= pi_phase_locked_w; pi_phase_locked_r2 <= pi_phase_locked_r1; pi_phase_locked_r3 <= pi_phase_locked_r2; pi_dqs_found_r1 <= pi_dqs_found_w; pi_dqs_found_r2 <= pi_dqs_found_r1; pi_dqs_found_r3 <= pi_dqs_found_r2; pi_counter_read_val_r1 <= pi_counter_read_val_w; pi_counter_read_val_r2 <= pi_counter_read_val_r1; pi_counter_read_val_r3 <= pi_counter_read_val_r2; end always @ (posedge phy_clk) begin if (rst) pi_phase_locked_r4 <= 1'b0; else if (pi_phase_locked_r2 == pi_phase_locked_r3) pi_phase_locked_r4 <= pi_phase_locked_r3; end always @ (posedge phy_clk) begin if (rst) pi_dqs_found_r4 <= 1'b0; else if (pi_dqs_found_r2 == pi_dqs_found_r3) pi_dqs_found_r4 <= pi_dqs_found_r3; end always @ (posedge phy_clk) begin if (rst) pi_counter_read_val_r4 <= 1'b0; else if (pi_counter_read_val_r2 == pi_counter_read_val_r3) pi_counter_read_val_r4 <= pi_counter_read_val_r3; end assign pi_phase_locked = pi_phase_locked_r4; assign pi_dqs_found = pi_dqs_found_r4; assign pi_counter_read_val = pi_counter_read_val_r4; end else begin: pahser_in_div4_clk assign pi_phase_locked = pi_phase_locked_w; assign pi_dqs_found = pi_dqs_found_w; assign pi_counter_read_val = pi_counter_read_val_w; end endgenerate generate if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen //if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_sys_clk if (PI_DIV2_INCDEC == "TRUE") begin PHASER_IN_PHY #( .BURST_MODE ( PI_BURST_MODE), .CLKOUT_DIV ( PI_CLKOUT_DIV), .DQS_AUTO_RECAL ( DQS_AUTO_RECAL), .DQS_FIND_PATTERN ( DQS_FIND_PATTERN), .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET), .FINE_DELAY ( PI_FINE_DELAY), .FREQ_REF_DIV ( PI_FREQ_REF_DIV), .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC), .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST), .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS), .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS) ) phaser_in ( .DQSFOUND (pi_dqs_found_w), .DQSOUTOFRANGE (dqs_out_of_range), .FINEOVERFLOW (pi_fine_overflow), .PHASELOCKED (pi_phase_locked_w), .ISERDESRST (pi_iserdes_rst), .ICLKDIV (iserdes_clkdiv), .ICLK (iserdes_clk), .COUNTERREADVAL (pi_counter_read_val_w), .RCLK (rclk), .WRENABLE (ififo_wr_enable), .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]), .ENCALIBPHY (pi_en_calib), .FINEENABLE (pi_fine_enable), .FREQREFCLK (freq_refclk), .MEMREFCLK (mem_refclk), .RANKSELPHY (rank_sel_i), .PHASEREFCLK (dqs_to_phaser), .RSTDQSFIND (pi_rst_dqs_find), .RST (rst_pi_div2), .FINEINC (pi_fine_inc), .COUNTERLOADEN (pi_counter_load_en), .COUNTERREADEN (pi_counter_read_en), .COUNTERLOADVAL (pi_counter_load_val), .SYNCIN (sync_pulse), .SYSCLK (clk_div2) ); end else begin PHASER_IN_PHY #( .BURST_MODE ( PI_BURST_MODE), .CLKOUT_DIV ( PI_CLKOUT_DIV), .DQS_AUTO_RECAL ( DQS_AUTO_RECAL), .DQS_FIND_PATTERN ( DQS_FIND_PATTERN), .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET), .FINE_DELAY ( PI_FINE_DELAY), .FREQ_REF_DIV ( PI_FREQ_REF_DIV), .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC), .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST), .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS), .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS) ) phaser_in ( .DQSFOUND (pi_dqs_found_w), .DQSOUTOFRANGE (dqs_out_of_range), .FINEOVERFLOW (pi_fine_overflow), .PHASELOCKED (pi_phase_locked_w), .ISERDESRST (pi_iserdes_rst), .ICLKDIV (iserdes_clkdiv), .ICLK (iserdes_clk), .COUNTERREADVAL (pi_counter_read_val_w), .RCLK (rclk), .WRENABLE (ififo_wr_enable), .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]), .ENCALIBPHY (pi_en_calib), .FINEENABLE (pi_fine_enable), .FREQREFCLK (freq_refclk), .MEMREFCLK (mem_refclk), .RANKSELPHY (rank_sel_i), .PHASEREFCLK (dqs_to_phaser), .RSTDQSFIND (pi_rst_dqs_find), .RST (rst), .FINEINC (pi_fine_inc), .COUNTERLOADEN (pi_counter_load_en), .COUNTERREADEN (pi_counter_read_en), .COUNTERLOADVAL (pi_counter_load_val), .SYNCIN (sync_pulse), .SYSCLK (phy_clk) ); end end else begin assign pi_dqs_found_w = 1'b1; // assign pi_dqs_out_of_range = 1'b0; assign pi_phase_locked_w = 1'b1; end endgenerate wire #0 phase_ref = freq_refclk; wire oserdes_clk; PHASER_OUT_PHY #( .CLKOUT_DIV ( PO_CLKOUT_DIV), .DATA_CTL_N ( PO_DATA_CTL ), .FINE_DELAY ( PO_FINE_DELAY), .COARSE_BYPASS ( PO_COARSE_BYPASS ), .COARSE_DELAY ( PO_COARSE_DELAY), .OCLK_DELAY ( PO_OCLK_DELAY), .OCLKDELAY_INV ( PO_OCLKDELAY_INV), .OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC), .SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST), .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), .PHASEREFCLK_PERIOD ( 1), // dummy, not used .PO ( PO_DCD_SETTING ), .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS) ) phaser_out ( .COARSEOVERFLOW (po_coarse_overflow), .CTSBUS (oserdes_dqs_ts), .DQSBUS (oserdes_dqs), .DTSBUS (oserdes_dq_ts), .FINEOVERFLOW (po_fine_overflow), .OCLKDIV (oserdes_clkdiv), .OCLK (oserdes_clk), .OCLKDELAYED (oserdes_clk_delayed), .COUNTERREADVAL (po_counter_read_val), .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]), .ENCALIBPHY (po_en_calib), .RDENABLE (po_rd_enable), .FREQREFCLK (freq_refclk), .MEMREFCLK (mem_refclk), .PHASEREFCLK (/*phase_ref*/), .RST (rst), .OSERDESRST (po_oserdes_rst), .COARSEENABLE (po_coarse_enable), .FINEENABLE (po_fine_enable), .COARSEINC (po_coarse_inc), .FINEINC (po_fine_inc), .SELFINEOCLKDELAY (po_sel_fine_oclk_delay), .COUNTERLOADEN (po_counter_load_en), .COUNTERREADEN (po_counter_read_en), .COUNTERLOADVAL (po_counter_load_val), .SYNCIN (sync_pulse), .SYSCLK (phy_clk) ); generate if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen IN_FIFO #( .ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ), .ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ), .ARRAY_MODE ( L_IF_ARRAY_MODE), .SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE) ) in_fifo ( .ALMOSTEMPTY (if_a_empty_), .ALMOSTFULL (if_a_full_), .EMPTY (if_empty_), .FULL (if_full_), .Q0 (if_q0), .Q1 (if_q1), .Q2 (if_q2), .Q3 (if_q3), .Q4 (if_q4), .Q5 (if_q5), .Q6 (if_q6), .Q7 (if_q7), .Q8 (if_q8), .Q9 (if_q9), //=== .D0 (if_d0), .D1 (if_d1), .D2 (if_d2), .D3 (if_d3), .D4 (if_d4), .D5 ({dummy_i5,if_d5}), .D6 ({dummy_i6,if_d6}), .D7 (if_d7), .D8 (if_d8), .D9 (if_d9), .RDCLK (phy_clk), .RDEN (phy_rd_en_), .RESET (ififo_rst), .WRCLK (iserdes_clkdiv), .WREN (ififo_wr_enable) ); end endgenerate OUT_FIFO #( .ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .ARRAY_MODE (L_OF_ARRAY_MODE), .OUTPUT_DISABLE (OF_OUTPUT_DISABLE), .SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE) ) out_fifo ( .ALMOSTEMPTY (of_a_empty), .ALMOSTFULL (of_a_full), .EMPTY (of_empty), .FULL (of_full), .Q0 (of_q0), .Q1 (of_q1), .Q2 (of_q2), .Q3 (of_q3), .Q4 (of_q4), .Q5 (of_q5), .Q6 (of_q6), .Q7 (of_q7), .Q8 (of_q8), .Q9 (of_q9), .D0 (of_d0), .D1 (of_d1), .D2 (of_d2), .D3 (of_d3), .D4 (of_d4), .D5 (of_d5), .D6 (of_d6), .D7 (of_d7), .D8 (of_d8), .D9 (of_d9), .RDCLK (oserdes_clkdiv), .RDEN (po_rd_enable), .RESET (ofifo_rst), .WRCLK (phy_clk), .WREN (of_wren_pre) ); mig_7series_v4_0_ddr_byte_group_io # ( .PO_DATA_CTL (PO_DATA_CTL), .BITLANES (BITLANES), .BITLANES_OUTONLY (BITLANES_OUTONLY), .OSERDES_DATA_RATE (L_OSERDES_DATA_RATE), .OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE), .TCK (TCK), .SYNTHESIS (SYNTHESIS) ) ddr_byte_group_io ( .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_in (mem_dqs_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .rst (rst), .oserdes_rst (po_oserdes_rst), .iserdes_rst (pi_iserdes_rst ), .iserdes_dout (iserdes_dout), .dqs_to_phaser (dqs_to_phaser), .phy_clk (phy_clk), .iserdes_clk (iserdes_clk), .iserdes_clkb (!iserdes_clk), .iserdes_clkdiv (iserdes_clkdiv), .idelay_inc (idelay_inc), .idelay_ce (idelay_ce), .idelay_ld (idelay_ld), .idelayctrl_refclk (idelayctrl_refclk), .oserdes_clk (oserdes_clk), .oserdes_clk_delayed (oserdes_clk_delayed), .oserdes_clkdiv (oserdes_clkdiv), .oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}), .oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}), .oserdes_dq (of_dqbus), .oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}), .fine_delay (fine_delay), .fine_delay_sel (fine_delay_sel) ); genvar i; generate for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) ddr_ck ( .C (oserdes_clk), .R (1'b0), .S (), .D1 (1'b0), .D2 (1'b1), .CE (1'b1), .Q (ddr_ck_out_q[i]) ); OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1])); end // ddr_ck_gen else begin : ddr_ck_null assign ddr_ck_out[i*2+1:i*2] = 2'b0; end end // ddr_ck_gen_loop endgenerate endmodule // byte_lane ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_calib_top.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: //Purpose: // Top-level for memory physical layer (PHY) interface // NOTES: // 1. Need to support multiple copies of CS outputs // 2. DFI_DRAM_CKE_DISABLE not supported // //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $ **$Date: 2011/06/02 08:35:06 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_calib_top # ( parameter TCQ = 100, parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter tCK = 2500, // DDR3 SDRAM clock period parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH parameter HIGHEST_LANE = 4, parameter HIGHEST_BANK = 3, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" // five fields, one per possible I/O bank, 4 bits in each field, // 1 per lane data=1/ctl=0 parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, // defines the byte lanes in I/O banks being used in the interface // 1- Used, 0- Unused parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map parameter CTL_BANK = 3'b000, // Bank used for control byte lanes // Slot Conifg parameters parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, // DRAM bus widths parameter BANK_WIDTH = 2, // # of bank bits parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, // column address width parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter ROW_WIDTH = 14, // DRAM address bus width parameter RANKS = 1, // # of memory ranks in the interface parameter CS_WIDTH = 1, // # of CS# signals in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter PER_BIT_DESKEW = "ON", // calibration Address. The address given below will be used for calibration // read and write operations. parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter TEST_AL = "0", // Additive Latency for internal use parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay parameter tREFI = 7800000, // pS Refresh-to-Refresh delay parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter RTT_NOM = "60", // ODT Nominal termination value parameter RTT_WR = "60", // ODT Write termination value parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter WRLVL = "OFF", // Enable write leveling parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter POC_USE_METASTABLE_SAMP = "FALSE", // Simulation /debug options parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter CKE_ODT_AUX = "FALSE", parameter IDELAY_ADJ = "ON", parameter FINE_PER_BIT = "ON", parameter CENTER_COMP_MODE = "ON", parameter PI_VAL_ADJ = "ON", parameter TAPSPERKCLK = 56, parameter DEBUG_PORT = "OFF", // Enable debug port parameter SKIP_CALIB = "FALSE", parameter PI_DIV2_INCDEC = "TRUE" ) ( input clk, // Internal (logic) clock input rst, // Reset sync'ed to CLK // Slot present inputs input [7:0] slot_0_present, input [7:0] slot_1_present, // Hard PHY signals // From PHY Ctrl Block input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, // To PHY Ctrl Block output write_calib, output read_calib, output calib_ctl_wren, output calib_cmd_wren, output [1:0] calib_seq, output [3:0] calib_aux_out, output [nCK_PER_CLK -1:0] calib_cke, output [1:0] calib_odt, output [2:0] calib_cmd, output calib_wrdata_en, output [1:0] calib_rank_cnt, output [1:0] calib_cas_slot, output [5:0] calib_data_offset_0, output [5:0] calib_data_offset_1, output [5:0] calib_data_offset_2, output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, output [nCK_PER_CLK-1:0] phy_ras_n, output [nCK_PER_CLK-1:0] phy_cas_n, output [nCK_PER_CLK-1:0] phy_we_n, output phy_reset_n, // To hard PHY wrapper output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */, output reg calib_in_common/* synthesis syn_maxfan = 10 */, output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */, output reg [HIGHEST_BANK-1:0] calib_zero_ctrl, output phy_if_empty_def, output reg phy_if_reset, // output reg ck_addr_ctl_delay_done, // From DQS Phaser_In input pi_phaselocked, input pi_phase_locked_all, input pi_found_dqs, input pi_dqs_found_all, input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, input [5:0] pi_counter_read_val, // To DQS Phaser_In output [HIGHEST_BANK-1:0] pi_rst_stg1_cal, output pi_en_stg2_f, output pi_stg2_f_incdec, output pi_stg2_load, output [5:0] pi_stg2_reg_l, // To DQ IDELAY output idelay_ce, output idelay_inc, output idelay_ld, // To DQS Phaser_Out output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */, output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */, output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */, output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */, output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */, output po_counter_load_en, input [8:0] po_counter_read_val, // To command Phaser_Out input phy_if_empty, input [4:0] idelaye2_init_val, input [5:0] oclkdelay_init_val, input tg_err, output rst_tg_mc, // Write data to OUT_FIFO output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata, // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // IN_FIFO read enable during write leveling, write calibration, // and read leveling // Read data from hard PHY fans out to mc and calib logic input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata, // To MC output [6*RANKS-1:0] calib_rd_data_offset_0, output [6*RANKS-1:0] calib_rd_data_offset_1, output [6*RANKS-1:0] calib_rd_data_offset_2, output phy_rddata_valid, output calib_writes, (* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */, output init_wrcal_complete, output pi_phase_locked_err, output pi_dqsfound_err, output wrcal_err, input pd_out, // input mmcm_ps_clk, //phase shift clock // input oclkdelay_fb_clk, //Write DQS feedback clk //phase shift clock control output psen, output psincdec, input psdone, input poc_sample_pd, // Ports to be used when SKIP_CALIB="TRUE" output reg calib_tap_req, input [6:0] calib_tap_addr, input calib_tap_load, input [7:0] calib_tap_val, input calib_tap_load_done, // Debug Port output dbg_pi_phaselock_start, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrlvl_start, output dbg_wrlvl_done, output dbg_wrlvl_err, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, // Write Calibration Logic output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal, // Read leveling logic output [1:0] dbg_rdlvl_start, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, // Delay control input [11:0] device_temp, input tempmon_sample_en, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl, // Read leveling calibration output [255:0] dbg_calib_top, // General PHY debug output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [1023:0] dbg_poc, output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, output reg [DQS_CNT_WIDTH:0] byte_sel_cnt, output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit output fine_delay_sel ); function integer clogb2 (input integer size); begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center // align DQ and DQS on writes. Round (up or down) value to nearest integer // localparam integer SHIFT_TBY4_TAP // = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) / // (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4); // Calculate number of slots in the system localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK >= 2500) || (SKIP_CALIB == "TRUE")) ? "OFF" : "ON"; //DIV2 change // Different CTL_LANES value for DDR2. In DDR2 during DQS found all // the add,ctl & data phaser out fine delays will be adjusted. // In DDR3 only the add/ctrl lane delays will be adjusted localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1; localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK >= 2500)) ? "LEFT" : "RIGHT"; // DIV2 change IO Bank used for Memory I/F: "LEFT", "RIGHT" localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE"; localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration //Per-bit deskew for higher freqency (>800Mhz) //localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF"; //BYPASS localparam BYPASS_COMPLEX_RDLVL = ((tCK > 2500) || (SKIP_CALIB == "TRUE")) ? "TRUE": "FALSE"; //"TRUE"; localparam BYPASS_COMPLEX_OCAL = "TRUE"; //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE"; // 8*tREFI in ps is divided by the fabric clock period in ps // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270; localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER); wire [2*8*nCK_PER_CLK-1:0] prbs_seed; //wire [2*8*nCK_PER_CLK-1:0] prbs_out; wire [8*DQ_WIDTH-1:0] prbs_out; wire [7:0] prbs_rise0; wire [7:0] prbs_fall0; wire [7:0] prbs_rise1; wire [7:0] prbs_fall1; wire [7:0] prbs_rise2; wire [7:0] prbs_fall2; wire [7:0] prbs_rise3; wire [7:0] prbs_fall3; //wire [2*8*nCK_PER_CLK-1:0] prbs_o; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; wire dqsfound_retry; wire dqsfound_retry_done; wire phy_rddata_en; wire prech_done; wire rdlvl_stg1_done; reg rdlvl_stg1_done_r1; wire pi_dqs_found_done; wire rdlvl_stg1_err; wire pi_dqs_found_err; wire wrcal_pat_resume; wire wrcal_resume_w; wire rdlvl_prech_req; wire rdlvl_last_byte_done; wire rdlvl_stg1_start; wire rdlvl_stg1_rank_done; wire rdlvl_assrt_common; wire pi_dqs_found_start; wire pi_dqs_found_rank_done; wire wl_sm_start; wire wrcal_start; wire wrcal_rd_wait; wire wrcal_prech_req; wire wrcal_pat_err; wire wrcal_done; wire wrlvl_done; wire wrlvl_err; wire wrlvl_start; wire ck_addr_cmd_delay_done; wire po_ck_addr_cmd_delay_done; wire pi_calib_done; wire detect_pi_found_dqs; wire [5:0] rd_data_offset_0; wire [5:0] rd_data_offset_1; wire [5:0] rd_data_offset_2; wire [6*RANKS-1:0] rd_data_offset_ranks_0; wire [6*RANKS-1:0] rd_data_offset_ranks_1; wire [6*RANKS-1:0] rd_data_offset_ranks_2; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2; wire cmd_po_stg2_f_incdec; wire cmd_po_stg2_incdec_ddr2_c; wire cmd_po_en_stg2_f; wire cmd_po_en_stg2_ddr2_c; wire cmd_po_stg2_c_incdec; wire cmd_po_en_stg2_c; wire po_stg2_ddr2_incdec; wire po_en_stg2_ddr2; wire dqs_po_stg2_f_incdec; wire dqs_po_en_stg2_f; wire dqs_wl_po_stg2_c_incdec; wire wrcal_po_stg2_c_incdec; wire dqs_wl_po_en_stg2_c; wire wrcal_po_en_stg2_c; wire [N_CTL_LANES-1:0] ctl_lane_cnt; reg [N_CTL_LANES-1:0] ctl_lane_sel; wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt; wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt; wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt; wire [8:0] dqs_wl_po_stg2_reg_l; wire dqs_wl_po_stg2_load; wire [8:0] dqs_po_stg2_reg_l; wire dqs_po_stg2_load; wire dqs_po_dec_done; wire pi_fine_dly_dec_done; wire rdlvl_pi_stg2_f_incdec; wire rdlvl_pi_stg2_f_en; wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt; //reg [DQS_CNT_WIDTH:0] byte_sel_cnt; wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt; wire phase_locked_err; wire phy_ctl_rdy_dly; wire idelay_ce_int; wire idelay_inc_int; reg idelay_ce_r1; reg idelay_ce_r2; reg idelay_inc_r1; reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */; reg po_dly_req_r; wire wrcal_read_req; wire wrcal_act_req; wire temp_wrcal_done; wire tg_timer_done; wire no_rst_tg_mc; wire calib_complete; reg reset_if_r1; reg reset_if_r2; reg reset_if_r3; reg reset_if_r4; reg reset_if_r5; reg reset_if_r6; reg reset_if_r7; reg reset_if_r8; reg reset_if_r9; reg reset_if; wire phy_if_reset_w; wire pi_phaselock_start; reg dbg_pi_f_inc_r; reg dbg_pi_f_en_r; reg dbg_sel_pi_incdec_r; reg dbg_po_f_inc_r; reg dbg_po_f_stg23_sel_r; reg dbg_po_f_en_r; reg dbg_sel_po_incdec_r; reg tempmon_pi_f_inc_r; reg tempmon_pi_f_en_r; reg tempmon_sel_pi_incdec_r; reg ck_addr_cmd_delay_done_r1; reg ck_addr_cmd_delay_done_r2; reg ck_addr_cmd_delay_done_r3; reg ck_addr_cmd_delay_done_r4; reg ck_addr_cmd_delay_done_r5; reg ck_addr_cmd_delay_done_r6; // wire oclk_init_delay_start; wire oclk_prech_req; wire oclk_calib_resume; wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt; wire oclkdelay_calib_start; wire oclkdelay_calib_done; wire complex_oclk_prech_req; wire complex_oclk_calib_resume; wire complex_oclkdelay_calib_start; wire complex_oclkdelay_calib_done; wire complex_ocal_num_samples_inc; wire complex_ocal_num_samples_done_r; wire [2:0] complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_ref_done; wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val; wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val; wire wrlvl_final; wire complex_wrlvl_final; reg wrlvl_final_mux; wire wrlvl_final_if_rst; wire wrlvl_byte_redo; wire wrlvl_byte_done; wire early1_data; wire early2_data; wire po_stg23_sel; wire po_stg23_incdec; wire po_en_stg23; wire complex_po_stg23_sel; wire complex_po_stg23_incdec; wire complex_po_en_stg23; wire mpr_rdlvl_done; wire mpr_rdlvl_start; wire mpr_last_byte_done; wire mpr_rnk_done; wire mpr_end_if_reset; wire mpr_rdlvl_err; wire rdlvl_err; wire prbs_rdlvl_start; wire prbs_rdlvl_done; wire prbs_rdlvl_done_complex; reg prbs_rdlvl_done_r1; wire prbs_last_byte_done; wire prbs_rdlvl_prech_req; wire prbs_pi_stg2_f_incdec; wire prbs_pi_stg2_f_en; wire complex_sample_cnt_inc; wire complex_sample_cnt_inc_ocal; wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt; wire prbs_gen_clk_en; wire prbs_gen_oclk_clk_en; wire rd_data_offset_cal_done; wire fine_adjust_done; wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt; wire ck_po_stg2_f_indec; wire ck_po_stg2_f_en; wire dqs_found_prech_req; wire tempmon_pi_f_inc; wire tempmon_pi_f_dec; wire tempmon_sel_pi_incdec; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done; wire wrlvl_done_w; wire wrlvl_rank_done; wire done_dqs_tap_inc; wire [2:0] rd_victim_sel; wire [2:0] victim_sel; wire [DQS_CNT_WIDTH:0] victim_byte_cnt; wire complex_wr_done; wire complex_victim_inc; wire reset_rd_addr; wire complex_ocal_reset_rd_addr; wire oclkdelay_center_calib_start; wire poc_error; wire prbs_ignore_first_byte; wire prbs_ignore_last_bytes; //stg3 tap values // wire [6*DQS_WIDTH-1:0] oclkdelay_center_val; //byte selection // wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt; //INC/DEC for stg3 taps // wire ocal_ctr_po_stg23_sel; // wire ocal_ctr_po_stg23_incdec; // wire ocal_ctr_po_en_stg23; //Write resume for DQS toggling wire oclk_center_write_resume; wire oclkdelay_center_calib_done; //Write request to toggle DQS for limit module wire lim2init_write_request; wire lim_done; // Bypass complex ocal wire complex_oclkdelay_calib_start_w; wire complex_oclkdelay_calib_done_w; wire [2:0] complex_ocal_rd_victim_sel_w; wire complex_wrlvl_final_w; wire [255:0] dbg_ocd_lim; //with MMCM phase detect logic //wire mmcm_edge_detect_rdy; // ready for MMCM detect //wire ktap_at_rightedge; // stg3 tap at right edge //wire ktap_at_leftedge; // stg3 tap at left edge //wire mmcm_tap_at_center; // indicate stg3 tap at center //wire mmcm_ps_clkphase_ok; // ps clkphase is OK //wire mmcm_edge_detect_done; // mmcm edge detect is done //wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done //wire reset_mmcm; //mmcm detect logic reset per byte // wire [255:0] dbg_phy_oclkdelay_center_cal; //PI inc/dec prevention during READ wire rdlvl_pi_incdec; wire complex_act_start; wire complex_pi_incdec_done; wire num_samples_done_r; wire complex_init_pi_dec_done; wire calib_tap_inc_start; wire calib_tap_inc_done; wire calib_tap_end_if_reset; wire [5:0] calib_tap_inc_byte_cnt; wire calib_po_f_en; wire calib_po_f_incdec; wire calib_po_sel_stg2stg3; wire calib_po_c_en; wire calib_po_c_inc; wire calib_pi_f_en; wire calib_pi_f_incdec; wire calib_idelay_ce; wire calib_idelay_inc; wire coarse_dec_err; reg skip_cal_tempmon_samp_en; wire tempmon_done_skip; wire skip_cal_po_pi_dec_done; reg [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt; reg [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt; reg [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt; reg [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt; reg [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt; reg [11:0] calib_device_temp; wire [127:0] dbg_skip_cal; //***************************************************************************** // Assertions to check correctness of parameter values //***************************************************************************** // synthesis translate_off initial begin if (RANKS == 0) begin $display ("Error: Invalid RANKS parameter. Must be 1 or greater"); $finish; end if (phy_ctl_full == 1'b1) begin $display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode"); $finish; end end // synthesis translate_on //*************************************************************************** // Debug //*************************************************************************** reg if_empty_reg; reg pi_stg2_en_reg; assign prbs_rdlvl_done = (SIM_CAL_OPTION == "FAST_CAL")? rdlvl_stg1_done : prbs_rdlvl_done_complex; assign dbg_pi_phaselock_start = pi_phaselock_start; assign dbg_pi_dqsfound_start = pi_dqs_found_start; assign dbg_pi_dqsfound_done = pi_dqs_found_done; assign dbg_wrcal_start = wrcal_start; assign dbg_wrcal_done = wrcal_done; // Unused for now - use these as needed to bring up lower level signals //assign dbg_calib_top = dbg_ocd_lim; assign dbg_calib_top[0] = pi_stg2_en_reg ; assign dbg_calib_top[1] = if_empty_reg ; assign dbg_calib_top[3] = coarse_dec_err; assign dbg_calib_top[4] = calib_tap_inc_start; assign dbg_calib_top[5] = calib_tap_inc_done; assign dbg_calib_top[6+:63] = dbg_skip_cal; always @ (posedge clk) begin if_empty_reg <= #TCQ phy_if_empty; pi_stg2_en_reg <= #TCQ pi_en_stg2_f; end // Write Level and write calibration debug observation ports assign dbg_wrlvl_start = wrlvl_start; assign dbg_wrlvl_done = wrlvl_done; assign dbg_wrlvl_err = wrlvl_err; // Read Level debug observation ports assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start}; assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done}; assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err}; assign dbg_oclkdelay_calib_done = oclkdelay_calib_done; assign dbg_oclkdelay_calib_start = oclkdelay_calib_start; //*************************************************************************** // Write leveling dependent signals //*************************************************************************** assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0; assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1; assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done : (po_ck_addr_cmd_delay_done && pi_fine_dly_dec_done) ; generate if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start; assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done; assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel; assign complex_wrlvl_final_w = complex_wrlvl_final; end else begin: bypass_complex_ocal assign complex_oclkdelay_calib_start_w = 1'b0; assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done; assign complex_ocal_rd_victim_sel_w = 'd0; assign complex_wrlvl_final_w = 1'b0; end endgenerate generate genvar i; for (i = 0; i <= 2; i = i+1) begin : bankwise_signal assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel : (complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 ) // (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0)) ) || calib_po_sel_stg2stg3 || dbg_po_f_stg23_sel_r; assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec || cmd_po_stg2_incdec_ddr2_c || calib_po_c_inc || dqs_wl_po_stg2_c_incdec; assign po_en_stg2_c[i] = cmd_po_en_stg2_c || cmd_po_en_stg2_ddr2_c || calib_po_c_en || dqs_wl_po_en_stg2_c; assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec || cmd_po_stg2_f_incdec || ck_po_stg2_f_indec || po_stg23_incdec || calib_po_f_incdec || // complex_po_stg23_incdec || // ocal_ctr_po_stg23_incdec || dbg_po_f_inc_r; assign po_en_stg2_f[i] = dqs_po_en_stg2_f || cmd_po_en_stg2_f || ck_po_stg2_f_en || po_en_stg23 || calib_po_f_en || // complex_po_en_stg23 || // ocal_ctr_po_en_stg23 || dbg_po_f_en_r; end endgenerate assign pi_stg2_f_incdec = (calib_pi_f_incdec | dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r); assign pi_en_stg2_f = (calib_pi_f_en | dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r); assign idelay_ce = (idelay_ce_r2 | calib_idelay_ce); assign idelay_inc = (idelay_inc_r2 | calib_idelay_inc); assign po_counter_load_en = 1'b0; assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt; assign complex_oclk_calib_resume = oclk_calib_resume; assign complex_ocal_ref_req = oclk_prech_req; // Added single stage flop to meet timing always @(posedge clk) begin if (SKIP_CALIB == "FALSE") init_calib_complete <= calib_complete; else init_calib_complete <= tempmon_done_skip; end assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0; assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1; assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2; //*************************************************************************** // Hard PHY signals //*************************************************************************** assign pi_phase_locked_err = phase_locked_err; assign pi_dqsfound_err = pi_dqs_found_err; assign wrcal_err = wrcal_pat_err; assign rst_tg_mc = 1'b0; //Restart WRLVL after oclkdealy cal always @ (posedge clk) wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final; always @(posedge clk) phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset | reset_if | wrlvl_final_if_rst | calib_tap_end_if_reset); //*************************************************************************** // Phaser_IN inc dec control for debug //*************************************************************************** always @(posedge clk) begin if (rst) begin dbg_pi_f_inc_r <= #TCQ 1'b0; dbg_pi_f_en_r <= #TCQ 1'b0; dbg_sel_pi_incdec_r <= #TCQ 1'b0; end else begin dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc; dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec); dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec; end end //*************************************************************************** // Phaser_OUT inc dec control for debug //*************************************************************************** always @(posedge clk) begin if (rst) begin dbg_po_f_inc_r <= #TCQ 1'b0; dbg_po_f_stg23_sel_r<= #TCQ 1'b0; dbg_po_f_en_r <= #TCQ 1'b0; dbg_sel_po_incdec_r <= #TCQ 1'b0; end else begin dbg_po_f_inc_r <= #TCQ dbg_po_f_inc; dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel; dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec); dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec; end end //*************************************************************************** // Phaser_IN inc dec control for temperature tracking //*************************************************************************** always @(posedge clk) begin if (rst) begin tempmon_pi_f_inc_r <= #TCQ 1'b0; tempmon_pi_f_en_r <= #TCQ 1'b0; tempmon_sel_pi_incdec_r <= #TCQ 1'b0; end else begin tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc; tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec); tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec; end end //*************************************************************************** // OCLKDELAY calibration signals //*************************************************************************** // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3 // and increment/decrement of Phaser_Out stage 3 delay always @(posedge clk) begin ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done; ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1; ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2; ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3; ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4; ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5; end //*************************************************************************** // MUX select logic to select current byte undergoing calibration // Use DQS_CAL_MAP to determine the correlation between the physical // byte numbering, and the byte numbering within the hard PHY //*************************************************************************** generate if (SKIP_CALIB == "TRUE") begin: gen_byte_sel_skip_calib always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~skip_cal_po_pi_dec_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~calib_tap_inc_done) begin byte_sel_cnt <= #TCQ calib_tap_inc_byte_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end else if (tCK >= 2500) begin: gen_byte_sel_div2 // DIV2 change always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~wrlvl_done_w) begin if (SIM_CAL_OPTION != "FAST_CAL") begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b0; end else begin // Special case for FAST_CAL simulation only to ensure that // calib_in_common isn't asserted too soon if (!phy_ctl_rdy_dly) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b1; end end end else if (~mpr_rdlvl_done) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~oclkdelay_calib_done) begin byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (~rdlvl_stg1_done && pi_calib_done) begin if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if ((~wrcal_done) && (DRAM_TYPE == "DDR3")) begin byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end else begin: gen_byte_sel_div1 always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~wrlvl_done_w) begin if (SIM_CAL_OPTION != "FAST_CAL") begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b0; end else begin // Special case for FAST_CAL simulation only to ensure that // calib_in_common isn't asserted too soon if (!phy_ctl_rdy_dly) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b1; end end end else if (~mpr_rdlvl_done) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~oclkdelay_calib_done) begin byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; calib_in_common <= #TCQ 1'b0; end else if (~rdlvl_stg1_done && pi_calib_done) begin if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.2.3.3 off always @(posedge clk) begin if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin calib_sel <= #TCQ 6'b000100; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done) || ~skip_cal_po_pi_dec_done) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; if (~dqs_po_dec_done && (WRLVL != "ON")) //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON"))) calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; else calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin if(WRLVL =="ON") begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2]; calib_sel[5:3] <= #TCQ CTL_BANK; if (|pi_rst_stg1_cal) begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; end else begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0; end calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else begin // if (WRLVL =="ON") calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; if(~ck_addr_cmd_delay_done) calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; else calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; end // else: !if(WRLVL =="ON") end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (tempmon_sel_pi_incdec) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; if (~calib_in_common) begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0; end else calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; end end // verilint STARC-2.2.3.3 on // Logic to reset IN_FIFO flags to account for the possibility that // one or more PHASER_IN's have not correctly found the DQS preamble // If this happens, we can still complete read leveling, but the # of // words written into the IN_FIFO's may be an odd #, so that if the // IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word // of data left that can only be flushed out by reseting the IN_FIFO always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; reset_if_r1 <= #TCQ reset_if; reset_if_r2 <= #TCQ reset_if_r1; reset_if_r3 <= #TCQ reset_if_r2; reset_if_r4 <= #TCQ reset_if_r3; reset_if_r5 <= #TCQ reset_if_r4; reset_if_r6 <= #TCQ reset_if_r5; reset_if_r7 <= #TCQ reset_if_r6; reset_if_r8 <= #TCQ reset_if_r7; reset_if_r9 <= #TCQ reset_if_r8; end always @(posedge clk) begin if (rst || reset_if_r9) reset_if <= #TCQ 1'b0; else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) reset_if <= #TCQ 1'b1; end assign phy_if_empty_def = 1'b0; // DQ IDELAY tap inc and ce signals registered to control calib_in_common // signal during read leveling in FAST_CAL mode. The calib_in_common signal // is only asserted for IDELAY tap increments not Phaser_IN tap increments // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load // inputs are used. always @(posedge clk) begin if (rst) begin idelay_ce_r1 <= #TCQ 1'b0; idelay_ce_r2 <= #TCQ 1'b0; idelay_inc_r1 <= #TCQ 1'b0; idelay_inc_r2 <= #TCQ 1'b0; end else begin idelay_ce_r1 <= #TCQ idelay_ce_int; idelay_ce_r2 <= #TCQ idelay_ce_r1; idelay_inc_r1 <= #TCQ idelay_inc_int; idelay_inc_r2 <= #TCQ idelay_inc_r1; end end //*************************************************************************** // Delay all Outputs using Phaser_Out fine taps //*************************************************************************** assign init_wrcal_complete = 1'b0; //*************************************************************************** // PRBS Generator for Read Leveling Stage 1 - read window detection and // DQS Centering //*************************************************************************** // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat assign prbs_seed = 64'h9966aa559966aa55; // A single PRBS generator // writes 64-bits every 4to1 fabric clock cycle and // write 32-bits every 2to1 fabric clock cycle // used for complex read leveling and complex oclkdealy calib mig_7series_v4_0_ddr_prbs_gen # ( .TCQ (TCQ), .PRBS_WIDTH (2*8*nCK_PER_CLK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .VCCO_PAT_EN (VCCO_PAT_EN), .VCCAUX_PAT_EN (VCCAUX_PAT_EN), .ISI_PAT_EN (ISI_PAT_EN), .FIXED_VICTIM (FIXED_VICTIM) ) u_ddr_prbs_gen (.prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .clk_i (clk), .clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en), .rst_i (rst), .prbs_o (prbs_out), .prbs_seed_i (prbs_seed), .phy_if_empty (phy_if_empty), .prbs_rdlvl_start (prbs_rdlvl_start), .prbs_rdlvl_done (prbs_rdlvl_done), .complex_wr_done (complex_wr_done), .victim_sel (victim_sel), .byte_cnt (victim_byte_cnt), .dbg_prbs_gen (), .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr) ); // PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1, // Rise2, Fall2, Rise3, Fall3 data generate if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 assign prbs_o = prbs_out; /*assign prbs_rise0 = prbs_out[7:0]; assign prbs_fall0 = prbs_out[15:8]; assign prbs_rise1 = prbs_out[23:16]; assign prbs_fall1 = prbs_out[31:24]; assign prbs_rise2 = prbs_out[39:32]; assign prbs_fall2 = prbs_out[47:40]; assign prbs_rise3 = prbs_out[55:48]; assign prbs_fall3 = prbs_out[63:56]; assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2, prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ end else begin :gen_ck_per_clk2 assign prbs_o = prbs_out[4*DQ_WIDTH-1:0]; /*assign prbs_rise0 = prbs_out[7:0]; assign prbs_fall0 = prbs_out[15:8]; assign prbs_rise1 = prbs_out[23:16]; assign prbs_fall1 = prbs_out[31:24]; assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ end endgenerate //*************************************************************************** // Initialization / Master PHY state logic (overall control during memory // init, timing leveling) //*************************************************************************** mig_7series_v4_0_ddr_phy_init # ( .tCK (tCK), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DRAM_TYPE (DRAM_TYPE), .PRBS_WIDTH (PRBS_WIDTH), .BANK_WIDTH (BANK_WIDTH), .CA_MIRROR (CA_MIRROR), .COL_WIDTH (COL_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .CS_WIDTH (CS_WIDTH), .RANKS (RANKS), .CKE_WIDTH (CKE_WIDTH), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .AL (AL), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .nCL (nCL), .nCWL (nCWL), .tRFC (tRFC), .REFRESH_TIMER (REFRESH_TIMER), .REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH), .OUTPUT_DRV (OUTPUT_DRV), .REG_CTRL (REG_CTRL), .ADDR_CMD_MODE (ADDR_CMD_MODE), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .WRLVL (WRLVL), .USE_ODT_PORT (USE_ODT_PORT), .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE), .nSLOTS (nSLOTS), .SIM_INIT_OPTION (SIM_INIT_OPTION), .SIM_CAL_OPTION (SIM_CAL_OPTION), .CKE_ODT_AUX (CKE_ODT_AUX), .PRE_REV3ES (PRE_REV3ES), .TEST_AL (TEST_AL), .FIXED_VICTIM (FIXED_VICTIM), .BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL), .SKIP_CALIB (SKIP_CALIB) ) u_ddr_phy_init ( .clk (clk), .rst (rst), .prbs_o (prbs_o), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .delay_incdec_done (ck_addr_cmd_delay_done), .pi_phase_locked_all (pi_phase_locked_all), .pi_phaselock_start (pi_phaselock_start), .pi_phase_locked_err (phase_locked_err), .pi_calib_done (pi_calib_done), .phy_if_empty (phy_if_empty), .phy_ctl_ready (phy_ctl_ready), .phy_ctl_full (phy_ctl_full), .phy_cmd_full (phy_cmd_full), .phy_data_full (phy_data_full), .calib_ctl_wren (calib_ctl_wren), .calib_cmd_wren (calib_cmd_wren), .calib_wrdata_en (calib_wrdata_en), .calib_seq (calib_seq), .calib_aux_out (calib_aux_out), .calib_rank_cnt (calib_rank_cnt), .calib_cas_slot (calib_cas_slot), .calib_data_offset_0 (calib_data_offset_0), .calib_data_offset_1 (calib_data_offset_1), .calib_data_offset_2 (calib_data_offset_2), .calib_cmd (calib_cmd), .calib_cke (calib_cke), .calib_odt (calib_odt), .write_calib (write_calib), .read_calib (read_calib), .wrlvl_done (wrlvl_done), .wrlvl_rank_done (wrlvl_rank_done), .wrlvl_byte_done (wrlvl_byte_done), .wrlvl_byte_redo (wrlvl_byte_redo), .wrlvl_final (wrlvl_final_mux), .wrlvl_final_if_rst (wrlvl_final_if_rst), .oclkdelay_calib_start (oclkdelay_calib_start), .oclkdelay_calib_done (oclkdelay_calib_done), .oclk_prech_req (oclk_prech_req), .oclk_calib_resume (oclk_calib_resume), .lim_wr_req (lim2init_write_request), .lim_done (lim_done), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w), .complex_oclk_calib_resume (complex_oclk_calib_resume), .complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt), .complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal), .complex_ocal_num_samples_inc (complex_ocal_num_samples_inc), .complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r), .complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr), .complex_ocal_ref_req (complex_ocal_ref_req), .complex_ocal_ref_done (complex_ocal_ref_done), .done_dqs_tap_inc (done_dqs_tap_inc), .wl_sm_start (wl_sm_start), .wr_lvl_start (wrlvl_start), .slot_0_present (slot_0_present), .slot_1_present (slot_1_present), .mpr_rdlvl_done (mpr_rdlvl_done), .mpr_rdlvl_start (mpr_rdlvl_start), .mpr_last_byte_done (mpr_last_byte_done), .mpr_rnk_done (mpr_rnk_done), .mpr_end_if_reset (mpr_end_if_reset), .rdlvl_stg1_done (rdlvl_stg1_done), .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done), .rdlvl_stg1_start (rdlvl_stg1_start), .rdlvl_prech_req (rdlvl_prech_req), .rdlvl_last_byte_done (rdlvl_last_byte_done), .prbs_rdlvl_start (prbs_rdlvl_start), .complex_wr_done (complex_wr_done), .prbs_rdlvl_done (prbs_rdlvl_done), .prbs_last_byte_done (prbs_last_byte_done), .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), .complex_victim_inc (complex_victim_inc), .rd_victim_sel (rd_victim_sel), .complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel), .pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt), .victim_sel (victim_sel), .victim_byte_cnt (victim_byte_cnt), .prbs_gen_clk_en (prbs_gen_clk_en), .prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en), .complex_sample_cnt_inc(complex_sample_cnt_inc), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .detect_pi_found_dqs (detect_pi_found_dqs), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .rd_data_offset_ranks_0(rd_data_offset_ranks_0), .rd_data_offset_ranks_1(rd_data_offset_ranks_1), .rd_data_offset_ranks_2(rd_data_offset_ranks_2), .wrcal_start (wrcal_start), .wrcal_rd_wait (wrcal_rd_wait), .wrcal_prech_req (wrcal_prech_req), .wrcal_resume (wrcal_resume_w), .wrcal_read_req (wrcal_read_req), .wrcal_act_req (wrcal_act_req), .wrcal_sanity_chk (wrcal_sanity_chk), .temp_wrcal_done (temp_wrcal_done), .wrcal_sanity_chk_done (wrcal_sanity_chk_done), .tg_timer_done (tg_timer_done), .no_rst_tg_mc (no_rst_tg_mc), .wrcal_done (wrcal_done), .prech_done (prech_done), .calib_writes (calib_writes), .init_calib_complete (calib_complete), .phy_address (phy_address), .phy_bank (phy_bank), .phy_cas_n (phy_cas_n), .phy_cs_n (phy_cs_n), .phy_ras_n (phy_ras_n), .phy_reset_n (phy_reset_n), .phy_we_n (phy_we_n), .phy_wrdata (phy_wrdata), .phy_rddata_en (phy_rddata_en), .phy_rddata_valid (phy_rddata_valid), .dbg_phy_init (dbg_phy_init), .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .rdlvl_pi_incdec (rdlvl_pi_incdec), .complex_act_start (complex_act_start), .complex_pi_incdec_done (complex_pi_incdec_done), .complex_init_pi_dec_done (complex_init_pi_dec_done), .num_samples_done_r (num_samples_done_r), .calib_tap_inc_start (calib_tap_inc_start), .calib_tap_end_if_reset (calib_tap_end_if_reset), .calib_tap_inc_done (calib_tap_inc_done) ); //***************************************************************** // Write Calibration //***************************************************************** mig_7series_v4_0_ddr_phy_wrcal # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .SIM_CAL_OPTION (SIM_CAL_OPTION) ) u_ddr_phy_wrcal ( .clk (clk), .rst (rst), .wrcal_start (wrcal_start), .wrcal_rd_wait (wrcal_rd_wait), .wrcal_sanity_chk (wrcal_sanity_chk), .dqsfound_retry_done (pi_dqs_found_done), .dqsfound_retry (dqsfound_retry), .wrcal_read_req (wrcal_read_req), .wrcal_act_req (wrcal_act_req), .phy_rddata_en (phy_rddata_en), .wrcal_done (wrcal_done), .wrcal_pat_err (wrcal_pat_err), .wrcal_prech_req (wrcal_prech_req), .temp_wrcal_done (temp_wrcal_done), .wrcal_sanity_chk_done (wrcal_sanity_chk_done), .prech_done (prech_done), .rd_data (phy_rddata), .wrcal_pat_resume (wrcal_pat_resume), .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt), .phy_if_reset (phy_if_reset_w), .wl_po_coarse_cnt (wl_po_coarse_cnt), .wl_po_fine_cnt (wl_po_fine_cnt), .wrlvl_byte_redo (wrlvl_byte_redo), .wrlvl_byte_done (wrlvl_byte_done), .early1_data (early1_data), .early2_data (early2_data), .idelay_ld (idelay_ld), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt) ); //*************************************************************************** // Write-leveling calibration logic //*************************************************************************** generate if ((WRLVL == "ON") && (SKIP_CALIB == "FALSE")) begin: mb_wrlvl_inst mig_7series_v4_0_ddr_phy_wrlvl # ( .TCQ (TCQ), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .CLK_PERIOD (CLK_PERIOD), .nCK_PER_CLK (nCK_PER_CLK), .SIM_CAL_OPTION (SIM_CAL_OPTION) ) u_ddr_phy_wrlvl ( .clk (clk), .rst (rst), .phy_ctl_ready (phy_ctl_ready), .wr_level_start (wrlvl_start), .wl_sm_start (wl_sm_start), .wrlvl_byte_redo (wrlvl_byte_redo), .wrcal_cnt (po_stg2_wrcal_cnt), .early1_data (early1_data), .early2_data (early2_data), .wrlvl_final (wrlvl_final_mux), .oclkdelay_calib_cnt (oclkdelay_calib_cnt), .wrlvl_byte_done (wrlvl_byte_done), .oclkdelay_calib_done (oclkdelay_calib_done), .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]), .dqs_po_dec_done (dqs_po_dec_done), .phy_ctl_rdy_dly (phy_ctl_rdy_dly), .wr_level_done (wrlvl_done), .wrlvl_rank_done (wrlvl_rank_done), .done_dqs_tap_inc (done_dqs_tap_inc), .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec), .dqs_po_en_stg2_f (dqs_po_en_stg2_f), .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec), .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c), .po_counter_read_val (po_counter_read_val), .po_stg2_wl_cnt (po_stg2_wl_cnt), .wrlvl_err (wrlvl_err), .wl_po_coarse_cnt (wl_po_coarse_cnt), .wl_po_fine_cnt (wl_po_fine_cnt), .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_dqs_count (), .dbg_wl_state (), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl) ); mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay # ( .TCQ (TCQ), .tCK (tCK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .N_CTL_LANES (N_CTL_LANES), .SIM_CAL_OPTION(SIM_CAL_OPTION) ) u_ddr_phy_ck_addr_cmd_delay ( .clk (clk), .rst (rst), .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done), .ctl_lane_cnt (ctl_lane_cnt), .po_stg2_f_incdec (cmd_po_stg2_f_incdec), .po_en_stg2_f (cmd_po_en_stg2_f), .po_stg2_c_incdec (cmd_po_stg2_c_incdec), .po_en_stg2_c (cmd_po_en_stg2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) ); assign cmd_po_stg2_incdec_ddr2_c = 1'b0; assign cmd_po_en_stg2_ddr2_c = 1'b0; end else if ((WRLVL == "ON") && (SKIP_CALIB == "TRUE")) begin: wrlvl_on_skip_calib mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay # ( .TCQ (TCQ), .tCK (tCK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .N_CTL_LANES (N_CTL_LANES), .SIM_CAL_OPTION(SIM_CAL_OPTION) ) u_ddr_phy_ck_addr_cmd_delay ( .clk (clk), .rst (rst), .cmd_delay_start (skip_cal_po_pi_dec_done), .ctl_lane_cnt (ctl_lane_cnt), .po_stg2_f_incdec (cmd_po_stg2_f_incdec), .po_en_stg2_f (cmd_po_en_stg2_f), .po_stg2_c_incdec (cmd_po_stg2_c_incdec), .po_en_stg2_c (cmd_po_en_stg2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) ); assign dqs_po_dec_done = 1'b1; assign wrlvl_byte_done = 1'b1; assign wrlvl_rank_done = 1'b1; assign phy_ctl_rdy_dly = 1'b1; assign done_dqs_tap_inc = 1'b1; assign po_stg2_wl_cnt = 'h0; assign wl_po_coarse_cnt = 'h0; assign wl_po_fine_cnt = 'h0; assign dbg_tap_cnt_during_wrlvl = 'h0; assign dbg_wl_edge_detect_valid = 'h0; assign dbg_rd_data_edge_detect = 'h0; assign dbg_wrlvl_fine_tap_cnt = 'h0; assign dbg_wrlvl_coarse_tap_cnt = 'h0; assign dbg_phy_wrlvl = 'h0; assign wrlvl_done = 1'b1; assign wrlvl_err = 1'b0; assign dqs_po_stg2_f_incdec = 1'b0; assign dqs_po_en_stg2_f = 1'b0; assign dqs_wl_po_en_stg2_c = 1'b0; assign dqs_wl_po_stg2_c_incdec = 1'b0; assign cmd_po_stg2_incdec_ddr2_c = 1'b0; assign cmd_po_en_stg2_ddr2_c = 1'b0; end else begin: mb_wrlvl_off mig_7series_v4_0_ddr_phy_wrlvl_off_delay # ( .TCQ (TCQ), .tCK (tCK), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .PO_INITIAL_DLY(60), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .N_CTL_LANES (N_CTL_LANES) ) u_phy_wrlvl_off_delay ( .clk (clk), .rst (rst), .pi_fine_dly_dec_done (pi_fine_dly_dec_done), .cmd_delay_start (phy_ctl_ready), .ctl_lane_cnt (ctl_lane_cnt), .po_s2_incdec_f (cmd_po_stg2_f_incdec), .po_en_s2_f (cmd_po_en_stg2_f), .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c), .po_en_s2_c (cmd_po_en_stg2_ddr2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done), .po_dec_done (dqs_po_dec_done), .phy_ctl_rdy_dly (phy_ctl_rdy_dly) ); assign wrlvl_byte_done = 1'b1; assign wrlvl_rank_done = 1'b1; assign po_stg2_wl_cnt = 'h0; assign wl_po_coarse_cnt = 'h0; assign wl_po_fine_cnt = 'h0; assign dbg_tap_cnt_during_wrlvl = 'h0; assign dbg_wl_edge_detect_valid = 'h0; assign dbg_rd_data_edge_detect = 'h0; assign dbg_wrlvl_fine_tap_cnt = 'h0; assign dbg_wrlvl_coarse_tap_cnt = 'h0; assign dbg_phy_wrlvl = 'h0; assign wrlvl_done = 1'b1; assign wrlvl_err = 1'b0; assign dqs_po_stg2_f_incdec = 1'b0; assign dqs_po_en_stg2_f = 1'b0; assign dqs_wl_po_en_stg2_c = 1'b0; assign cmd_po_stg2_c_incdec = 1'b0; assign dqs_wl_po_stg2_c_incdec = 1'b0; assign cmd_po_en_stg2_c = 1'b0; end endgenerate generate if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib localparam SAMPCNTRWIDTH = 17; localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 512 : 4; //MG from 2048 localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK); localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10; localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 512 : 1; //MG from 2048 localparam POC_PCT_SAMPS_SOLID = 80; localparam SCAN_PCT_SAMPS_SOLID = 95; mig_7series_v4_0_ddr_phy_oclkdelay_cal # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DQ_WIDTH (DQ_WIDTH), //.DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), //.OCAL_EN (OCAL_EN), .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), .PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .SIM_CAL_OPTION (SIM_CAL_OPTION), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL) //.tCK (tCK) ) u_ddr_phy_oclkdelay_cal (/*AUTOINST*/ // Outputs .prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]), .lim2init_write_request (lim2init_write_request), .lim_done (lim_done), .oclk_calib_resume (oclk_calib_resume), .oclk_prech_req (oclk_prech_req), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .po_en_stg23 (po_en_stg23), .po_stg23_incdec (po_stg23_incdec), .po_stg23_sel (po_stg23_sel), .psen (psen), .psincdec (psincdec), .wrlvl_final (wrlvl_final), .rd_victim_sel (complex_ocal_rd_victim_sel), .ocal_num_samples_done_r (complex_ocal_num_samples_done_r), .complex_wrlvl_final (complex_wrlvl_final), .poc_error (poc_error), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w), .metaQ (pd_out), //.oclk_init_delay_start (oclk_init_delay_start), .po_counter_read_val (po_counter_read_val), .oclkdelay_calib_start (oclkdelay_calib_start), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .poc_sample_pd (poc_sample_pd), .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .phy_rddata_en (phy_rddata_en), .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .prech_done (prech_done), .psdone (psdone), .rst (rst), .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]), .ocal_num_samples_inc (complex_ocal_num_samples_inc), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .dbg_ocd_lim (dbg_ocd_lim), .dbg_poc (dbg_poc[1023:0]) ); end else begin : oclk_calib_disabled assign wrlvl_final = 'b0; assign psen = 'b0; assign psincdec = 'b0; assign po_stg23_sel = 'b0; assign po_stg23_incdec = 'b0; assign po_en_stg23 = 'b0; assign oclkdelay_calib_cnt = 'b0; assign oclk_prech_req = 'b0; assign oclk_calib_resume = 'b0; assign oclkdelay_calib_done = 1'b1; assign dbg_phy_oclkdelay_cal = 'h0; assign dbg_oclkdelay_rd_data = 'h0; end endgenerate //*************************************************************************** // Read data-offset calibration required for Phaser_In //*************************************************************************** generate if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right mig_7series_v4_0_ddr_phy_dqs_found_cal # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .nCL (nCL), .AL (AL), .nCWL (nCWL), //.RANKS (RANKS), .RANKS (1), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .REG_CTRL (REG_CTRL), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DRAM_TYPE (DRAM_TYPE), .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), .HIGHEST_LANE (HIGHEST_LANE), .HIGHEST_BANK (HIGHEST_BANK), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4) ) u_ddr_phy_dqs_found_cal ( .clk (clk), .rst (rst), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .detect_pi_found_dqs (detect_pi_found_dqs), .prech_done (prech_done), .pi_dqs_found_lanes (pi_dqs_found_lanes), .pi_rst_stg1_cal (pi_rst_stg1_cal), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .pi_dqs_found_rank_done (pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .dqsfound_retry_done (dqsfound_retry_done), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_err (pi_dqs_found_err), .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), .po_counter_read_val (po_counter_read_val), .rd_data_offset_cal_done (rd_data_offset_cal_done), .fine_adjust_done (fine_adjust_done), .fine_adjust_lane_cnt (fine_adjust_lane_cnt), .ck_po_stg2_f_indec (ck_po_stg2_f_indec), .ck_po_stg2_f_en (ck_po_stg2_f_en), .dbg_dqs_found_cal (dbg_dqs_found_cal) ); end else begin: dqsfind_calib_left mig_7series_v4_0_ddr_phy_dqs_found_cal_hr # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .nCL (nCL), .AL (AL), .nCWL (nCWL), //.RANKS (RANKS), .RANKS (1), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .REG_CTRL (REG_CTRL), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DRAM_TYPE (DRAM_TYPE), .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), .HIGHEST_LANE (HIGHEST_LANE), .HIGHEST_BANK (HIGHEST_BANK), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4) ) u_ddr_phy_dqs_found_cal_hr ( .clk (clk), .rst (rst), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .detect_pi_found_dqs (detect_pi_found_dqs), .prech_done (prech_done), .pi_dqs_found_lanes (pi_dqs_found_lanes), .pi_rst_stg1_cal (pi_rst_stg1_cal), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .pi_dqs_found_rank_done (pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .dqsfound_retry_done (dqsfound_retry_done), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_err (pi_dqs_found_err), .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), .po_counter_read_val (po_counter_read_val), .rd_data_offset_cal_done (rd_data_offset_cal_done), .fine_adjust_done (fine_adjust_done), .fine_adjust_lane_cnt (fine_adjust_lane_cnt), .ck_po_stg2_f_indec (ck_po_stg2_f_indec), .ck_po_stg2_f_en (ck_po_stg2_f_en), .dbg_dqs_found_cal (dbg_dqs_found_cal) ); end endgenerate //*************************************************************************** // Read-leveling calibration logic //*************************************************************************** generate if (SKIP_CALIB == "FALSE") begin:ddr_phy_rdlvl_gen mig_7series_v4_0_ddr_phy_rdlvl # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .PER_BIT_DESKEW (PER_BIT_DESKEW), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DEBUG_PORT (DEBUG_PORT), .DRAM_TYPE (DRAM_TYPE), .OCAL_EN (OCAL_EN), .IDELAY_ADJ (IDELAY_ADJ), .PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_phy_rdlvl ( .clk (clk), .rst (rst), .mpr_rdlvl_done (mpr_rdlvl_done), .mpr_rdlvl_start (mpr_rdlvl_start), .mpr_last_byte_done (mpr_last_byte_done), .mpr_rnk_done (mpr_rnk_done), .rdlvl_stg1_start (rdlvl_stg1_start), .rdlvl_stg1_done (rdlvl_stg1_done), .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done), .rdlvl_stg1_err (rdlvl_stg1_err), .mpr_rdlvl_err (mpr_rdlvl_err), .rdlvl_err (rdlvl_err), .rdlvl_prech_req (rdlvl_prech_req), .rdlvl_last_byte_done (rdlvl_last_byte_done), .rdlvl_assrt_common (rdlvl_assrt_common), .prech_done (prech_done), .phy_if_empty (phy_if_empty), .idelaye2_init_val (idelaye2_init_val), .rd_data (phy_rddata), .pi_en_stg2_f (rdlvl_pi_stg2_f_en), .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec), .pi_stg2_load (pi_stg2_load), .pi_stg2_reg_l (pi_stg2_reg_l), .dqs_po_dec_done (dqs_po_dec_done), .pi_counter_read_val (pi_counter_read_val), .pi_fine_dly_dec_done (pi_fine_dly_dec_done), .idelay_ce (idelay_ce_int), .idelay_inc (idelay_inc_int), .idelay_ld (idelay_ld), .wrcal_cnt (po_stg2_wrcal_cnt), .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt), .dlyval_dq (dlyval_dq), .rdlvl_pi_incdec (rdlvl_pi_incdec), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_phy_rdlvl (dbg_phy_rdlvl) ); end else begin:ddr_phy_rdlvl_off assign mpr_rdlvl_done = 1'b1; assign mpr_last_byte_done = 1'b1; assign mpr_rnk_done = 1'b1; assign rdlvl_stg1_done = 1'b1; assign rdlvl_stg1_rank_done = 1'b1; assign rdlvl_last_byte_done = 1'b1; assign pi_fine_dly_dec_done = 1'b1; assign rdlvl_prech_req = 1'b0; assign rdlvl_stg1_err = 1'b0; assign mpr_rdlvl_err = 1'b0; assign rdlvl_err = 1'b0; assign rdlvl_assrt_common = 1'b0; assign rdlvl_pi_stg2_f_en = 1'b0; assign rdlvl_pi_stg2_f_incdec = 1'b0; assign pi_stg2_rdlvl_cnt = 'h0; assign idelay_ce_int = 1'b0; assign idelay_inc_int = 1'b0; assign rdlvl_pi_incdec = 1'b0; assign dbg_phy_rdlvl = 'h0; assign dbg_cpt_first_edge_cnt = 'h0; assign dbg_cpt_second_edge_cnt = 'h0; assign dbg_cpt_tap_cnt = 'h0; assign dbg_dq_idelay_tap_cnt = 'h0; end endgenerate generate if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen mig_7series_v4_0_ddr_phy_prbs_rdlvl # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .SIM_CAL_OPTION (SIM_CAL_OPTION), .PRBS_WIDTH (PRBS_WIDTH), .FIXED_VICTIM (FIXED_VICTIM), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ) ) u_ddr_phy_prbs_rdlvl ( .clk (clk), .rst (rst), .prbs_rdlvl_start (prbs_rdlvl_start), .prbs_rdlvl_done (prbs_rdlvl_done_complex), .prbs_last_byte_done (prbs_last_byte_done), .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), .complex_sample_cnt_inc (complex_sample_cnt_inc), .prech_done (prech_done), .phy_if_empty (phy_if_empty), .rd_data (phy_rddata), .compare_data (prbs_o), .pi_counter_read_val (pi_counter_read_val), .pi_en_stg2_f (prbs_pi_stg2_f_en), .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt), .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), .rd_victim_sel (rd_victim_sel), .complex_victim_inc (complex_victim_inc), .reset_rd_addr (reset_rd_addr), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel), .complex_act_start (complex_act_start), .num_samples_done_r (num_samples_done_r), .complex_pi_incdec_done (complex_pi_incdec_done), .complex_init_pi_dec_done (complex_init_pi_dec_done) ); end else begin:ddr_phy_prbs_rdlvl_off assign prbs_rdlvl_done_complex = rdlvl_stg1_done ; //assign prbs_last_byte_done = rdlvl_stg1_rank_done ; assign prbs_last_byte_done = rdlvl_stg1_done; assign reset_rd_addr = 1'b0; assign prbs_rdlvl_prech_req = 1'b0 ; assign prbs_pi_stg2_f_en = 1'b0 ; assign prbs_pi_stg2_f_incdec = 1'b0 ; assign pi_stg2_prbs_rdlvl_cnt = 'b0 ; assign dbg_prbs_rdlvl = 'h0 ; assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}}; assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; assign complex_pi_incdec_done = 'b0; assign complex_init_pi_dec_done = 'b1; assign num_samples_done_r = 'b0; end endgenerate //*************************************************************************** // Inc/Dec Phaser_Out, Phaser_In, and IDELAY taps to match calibration values //*************************************************************************** generate if (SKIP_CALIB == "TRUE") begin: gen_skip_calib_tap // Generate request to get calibration tap values per byte always @(posedge clk) begin if (rst) calib_tap_req <= #TCQ 1'b0; else if (phy_ctl_ready) calib_tap_req <= #TCQ 1'b1; end // Store calibration values to registers always @(posedge clk) begin if (rst) begin calib_po_coarse_tap_cnt <= #TCQ 'd0; calib_po_stage3_tap_cnt <= #TCQ 'd0; calib_po_stage2_tap_cnt <= #TCQ 'd0; calib_pi_stage2_tap_cnt <= #TCQ 'd0; calib_idelay_tap_cnt <= #TCQ 'd0; calib_device_temp <= #TCQ 'd0; end else if (calib_tap_load) begin case (calib_tap_addr[2:0]) 3'b000: calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0]; 3'b001: calib_po_stage3_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; 3'b010: calib_po_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; 3'b011: calib_pi_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; 3'b100: calib_idelay_tap_cnt[5*calib_tap_addr[6:3]+:5] <= #TCQ calib_tap_val[4:0]; 3'b110: if (&calib_tap_addr[6:3]) calib_device_temp[7:0] <= #TCQ calib_tap_val[7:0]; 3'b111: if (&calib_tap_addr[6:3]) calib_device_temp[11:8] <= #TCQ calib_tap_val[3:0]; default: calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0]; endcase end end mig_7series_v4_0_ddr_skip_calib_tap # ( .TCQ (TCQ), .DQS_WIDTH (DQS_WIDTH) ) u_ddr_skip_calib_tap ( .rst (rst), .clk (clk), .phy_ctl_ready (phy_ctl_ready), .load_done (calib_tap_load_done), .calib_tap_inc_start (calib_tap_inc_start), .calib_tap_inc_done (calib_tap_inc_done), .calib_tap_inc_byte_cnt (calib_tap_inc_byte_cnt), .calib_po_stage2_tap_cnt (calib_po_stage2_tap_cnt), .calib_po_stage3_tap_cnt (calib_po_stage3_tap_cnt), .calib_po_coarse_tap_cnt (calib_po_coarse_tap_cnt), .calib_pi_stage2_tap_cnt (calib_pi_stage2_tap_cnt), .calib_idelay_tap_cnt (calib_idelay_tap_cnt), .po_counter_read_val (po_counter_read_val), .pi_counter_read_val (pi_counter_read_val), .calib_po_f_en (calib_po_f_en), .calib_po_f_incdec (calib_po_f_incdec), .calib_po_sel_stg2stg3 (calib_po_sel_stg2stg3), .calib_po_c_en (calib_po_c_en), .calib_po_c_inc (calib_po_c_inc), .calib_pi_f_en (calib_pi_f_en), .calib_pi_f_incdec (calib_pi_f_incdec), .calib_idelay_ce (calib_idelay_ce), .calib_idelay_inc (calib_idelay_inc), .skip_cal_po_pi_dec_done (skip_cal_po_pi_dec_done), .coarse_dec_err (coarse_dec_err), .dbg_skip_cal (dbg_skip_cal) ); // Generate tempmon_sample_en pulses for temperature adjustment reg [8:0] samp_en_cnt; always @ (posedge clk) begin if (rst || tempmon_done_skip || (samp_en_cnt == 'd0)) samp_en_cnt <= #TCQ 'd267; else if (calib_complete && (samp_en_cnt > 'd0)) samp_en_cnt <= #TCQ samp_en_cnt - 1; end always @ (posedge clk) begin if (rst || tempmon_done_skip) skip_cal_tempmon_samp_en <= #TCQ 1'b0; else if (samp_en_cnt == 'd260) skip_cal_tempmon_samp_en <= #TCQ 1'b1; else skip_cal_tempmon_samp_en <= #TCQ 1'b0; end end else begin: skip_calib_tap_off assign calib_po_f_en = 1'b0; assign calib_po_f_incdec = 1'b0; assign calib_po_sel_stg2stg3 = 1'b0; assign calib_po_c_en = 1'b0; assign calib_po_c_inc = 1'b0; assign calib_pi_f_en = 1'b0; assign calib_pi_f_incdec = 1'b0; assign calib_idelay_ce = 1'b0; assign calib_idelay_inc = 1'b0; assign calib_tap_inc_done = 1'b0; assign calib_tap_inc_byte_cnt = 'd0; assign skip_cal_po_pi_dec_done = 1'b1; always @(posedge clk) begin calib_tap_req <= #TCQ 1'b0; calib_device_temp <= #TCQ 'd0; skip_cal_tempmon_samp_en <= #TCQ 1'b0; end end endgenerate //*************************************************************************** // Temperature induced PI tap adjustment logic //*************************************************************************** mig_7series_v4_0_ddr_phy_tempmon # ( .SKIP_CALIB (SKIP_CALIB), .TCQ (TCQ) ) ddr_phy_tempmon_0 ( .rst (rst), .clk (clk), .calib_complete (calib_complete), .tempmon_pi_f_inc (tempmon_pi_f_inc), .tempmon_pi_f_dec (tempmon_pi_f_dec), .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec), .device_temp (device_temp), .calib_device_temp (calib_device_temp), .tempmon_sample_en (tempmon_sample_en | skip_cal_tempmon_samp_en), .tempmon_done_skip (tempmon_done_skip) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Feb 08 2011 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_ddr_if_post_fifo # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DEPTH = 4, // # of entries parameter WIDTH = 32 // data bus width ) ( input clk, // clock input rst, // synchronous reset input [3:0] empty_in, input rd_en_in, input [WIDTH-1:0] d_in, // write data from controller output empty_out, output byte_rd_en, output [WIDTH-1:0] d_out // write data to OUT_FIFO ); // # of bits used to represent read/write pointers localparam PTR_BITS = (DEPTH == 2) ? 1 : (((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx); integer i; reg [WIDTH-1:0] mem[0:DEPTH-1]; (* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */; (* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */; reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; // Register duplication to reduce the fan out (* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; wire [WIDTH-1:0] mem_out; (* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */; task updt_ptrs; input rd; input wr; reg [1:0] next_rd_ptr; reg [1:0] next_wr_ptr; begin next_rd_ptr = (rd_ptr + 1'b1)%DEPTH; next_wr_ptr = (wr_ptr + 1'b1)%DEPTH; casez ({rd, wr, my_empty[1], my_full[1]}) 4'b00zz: ; // No access, do nothing 4'b0100: begin // Write when neither empty, nor full; check for full wr_ptr <= #TCQ next_wr_ptr; my_full[0] <= #TCQ (next_wr_ptr == rd_ptr); my_full[1] <= #TCQ (next_wr_ptr == rd_ptr); //mem[wr_ptr] <= #TCQ d_in; end 4'b0110: begin // Write when empty; no need to check for full wr_ptr <= #TCQ next_wr_ptr; my_empty <= #TCQ 5'b00000; //mem[wr_ptr] <= #TCQ d_in; end 4'b1000: begin // Read when neither empty, nor full; check for empty rd_ptr <= #TCQ next_rd_ptr; rd_ptr_timing <= #TCQ next_rd_ptr; my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr); end 4'b1001: begin // Read when full; no need to check for empty rd_ptr <= #TCQ next_rd_ptr; rd_ptr_timing <= #TCQ next_rd_ptr; my_full[0] <= #TCQ 1'b0; my_full[1] <= #TCQ 1'b0; end 4'b1100, 4'b1101, 4'b1110: begin // Read and write when empty, full, or neither empty/full; no need // to check for empty or full conditions rd_ptr <= #TCQ next_rd_ptr; rd_ptr_timing <= #TCQ next_rd_ptr; wr_ptr <= #TCQ next_wr_ptr; //mem[wr_ptr] <= #TCQ d_in; end 4'b0101, 4'b1010: ; // Read when empty, Write when full; Keep all pointers the same // and don't change any of the flags (i.e. ignore the read/write). // This might happen because a faulty DQS_FOUND calibration could // result in excessive skew between when the various IN_FIFO's // first become not empty. In this case, the data going to each // post-FIFO/IN_FIFO should be read out and discarded // synthesis translate_off default: begin // Covers any other cases, in particular for simulation if // any signals are X's $display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b", $time, rd, wr, my_empty[1], my_full[1]); rd_ptr <= #TCQ 2'bxx; rd_ptr_timing <= #TCQ 2'bxx; wr_ptr <= #TCQ 2'bxx; end // synthesis translate_on endcase end endtask assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr]; // The combined IN_FIFO + post FIFO is only "empty" when both are empty assign empty_out = empty_in[0] & my_empty[0]; assign byte_rd_en = !empty_in[3] || !my_empty[3]; always @(posedge clk) if (rst) begin my_empty <= #TCQ 5'b11111; my_full <= #TCQ 2'b00; rd_ptr <= #TCQ 'b0; rd_ptr_timing <= #TCQ 'b0; wr_ptr <= #TCQ 'b0; end else begin // Special mode: If IN_FIFO has data, and controller is reading at // the same time, then operate post-FIFO in "passthrough" mode (i.e. // don't update any of the read/write pointers, and route IN_FIFO // data to post-FIFO data) if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ; else // Otherwise, we're writing to FIFO when IN_FIFO is not empty, // and reading from the FIFO based on the rd_en_in signal (read // enable from controller). The functino updt_ptrs should catch // an illegal conditions. updt_ptrs(rd_en_in, !empty_in[1]); end assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) | (rd_en_in & !my_empty[2]))); always @ (posedge clk) begin if (wr_en) mem[wr_ptr] <= #TCQ d_in; end assign mem_out = mem[rd_ptr_timing]; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v ================================================ /*********************************************************** -- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is a parameterizable wrapper instantiating // up to 5 memory banks of 4-lane phy primitives. There // There are always 2 control banks leaving 18 lanes for data. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // //////////////////////////////////////////////////////////// ***********************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_mc_phy #( // five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0 parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter RCLK_SELECT_BANK = 0, parameter RCLK_SELECT_LANE = "B", parameter RCLK_SELECT_EDGE = 4'b1111, parameter GENERATE_DDR_CK_MAP = "0B", parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002, parameter USE_PRE_POST_FIFO = "TRUE", parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PI_SEL_CLK_OFFSET = 6, parameter PHYCTL_CMD_FIFO = "FALSE", parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio // common to all i/o banks parameter PHY_FOUR_WINDOW_CLOCKS = 63, parameter PHY_EVENTS_DELAY = 18, parameter PHY_COUNT_EN = "TRUE", parameter PHY_SYNC_MODE = "TRUE", parameter PHY_DISABLE_SEQ_MATCH = "FALSE", parameter MASTER_PHY_CTL = 0, // common to instance 0 parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff, parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000, parameter PHY_0_LANE_REMAP = 16'h3210, parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE", parameter PHY_0_IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter NUM_DDR_CK = 1, parameter PHY_0_DATA_CTL = DATA_CTL_B0, parameter PHY_0_CMD_OFFSET = 0, parameter PHY_0_RD_CMD_OFFSET_0 = 0, parameter PHY_0_RD_CMD_OFFSET_1 = 0, parameter PHY_0_RD_CMD_OFFSET_2 = 0, parameter PHY_0_RD_CMD_OFFSET_3 = 0, parameter PHY_0_RD_DURATION_0 = 0, parameter PHY_0_RD_DURATION_1 = 0, parameter PHY_0_RD_DURATION_2 = 0, parameter PHY_0_RD_DURATION_3 = 0, parameter PHY_0_WR_CMD_OFFSET_0 = 0, parameter PHY_0_WR_CMD_OFFSET_1 = 0, parameter PHY_0_WR_CMD_OFFSET_2 = 0, parameter PHY_0_WR_CMD_OFFSET_3 = 0, parameter PHY_0_WR_DURATION_0 = 0, parameter PHY_0_WR_DURATION_1 = 0, parameter PHY_0_WR_DURATION_2 = 0, parameter PHY_0_WR_DURATION_3 = 0, parameter PHY_0_AO_WRLVL_EN = 0, parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PHY_0_OF_ALMOST_FULL_VALUE = 1, parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1, // per lane parameters parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE", parameter PHY_0_A_PI_CLKOUT_DIV = 2, parameter PHY_0_A_PO_CLKOUT_DIV = 2, parameter PHY_0_A_BURST_MODE = "TRUE", parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF", parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter PHY_0_A_PO_OCLK_DELAY = 25, parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE", parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4", parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4", parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED", parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED", parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00, parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, // common to instance 1 parameter PHY_1_BITLANES = PHY_0_BITLANES, parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000, parameter PHY_1_LANE_REMAP = 16'h3210, parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE", parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP, parameter PHY_1_DATA_CTL = DATA_CTL_B1, parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET, parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0, parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1, parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2, parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3, parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0, parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1, parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2, parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3, parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0, parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1, parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2, parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3, parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0, parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1, parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2, parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3, parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN, parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE) parameter PHY_1_OF_ALMOST_FULL_VALUE = 1, parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1, // per lane parameters parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV, parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV, parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV, parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE, parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC, parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC , parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV, parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE, parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, // common to instance 2 parameter PHY_2_BITLANES = PHY_0_BITLANES, parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000, parameter PHY_2_LANE_REMAP = 16'h3210, parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE", parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP, parameter PHY_2_DATA_CTL = DATA_CTL_B2, parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET, parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0, parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1, parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2, parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3, parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0, parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1, parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2, parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3, parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0, parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1, parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2, parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3, parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0, parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1, parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2, parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3, parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN, parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE) parameter PHY_2_OF_ALMOST_FULL_VALUE = 1, parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1, // per lane parameters parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV, parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV , parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV, parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE , parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC, parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC, parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE, parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV, parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE", parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"), parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"), parameter TCK = 2500, // local computational use, do not pass down parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3]) + (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3]) , // must not delete comma for syntax parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))), parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) , parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) , parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) , parameter HIGHEST_LANE_B3 = 0, parameter HIGHEST_LANE_B4 = 0, parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))), parameter LP_DDR_CK_WIDTH = 2, parameter GENERATE_SIGNAL_SPLIT = "FALSE" ,parameter CKE_ODT_AUX = "FALSE" ,parameter PI_DIV2_INCDEC = "FALSE" ) ( input rst, input ddr_rst_in_n , input phy_clk, input clk_div2, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input auxout_clk, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input [31:0] phy_ctl_wd, input [3:0] aux_in_1, input [3:0] aux_in_2, input [5:0] data_offset_1, input [5:0] data_offset_2, input phy_ctl_wr, input if_rst, input if_empty_def, input cke_in, input idelay_ce, input idelay_ld, input idelay_inc, input phyGo, input input_sink, output if_a_empty, output if_empty /* synthesis syn_maxfan = 3 */, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0] phy_din, output phy_ctl_a_full, output wire [3:0] phy_ctl_full, output [HIGHEST_LANE*12-1:0] mem_dq_out, output [HIGHEST_LANE*12-1:0] mem_dq_ts, input [HIGHEST_LANE*10-1:0] mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, (* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller output phy_ctl_ready, // to fabric output reg rst_out, // to memory output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk, // output rclk, output mcGo, output ref_dll_lock, // calibration signals input phy_write_calib, input phy_read_calib, input [5:0] calib_sel, input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane input calib_in_common, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, input po_counter_read_en, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_phase_locked, output pi_phase_locked_all, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, input [29:0] fine_delay, input fine_delay_sel ); wire [7:0] calib_zero_inputs_int ; wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ; //Added the temporary variable for concadination operation wire [2:0] calib_sel_byte0 ; wire [2:0] calib_sel_byte1 ; wire [2:0] calib_sel_byte2 ; wire [4:0] po_coarse_overflow_w; wire [4:0] po_fine_overflow_w; wire [8:0] po_counter_read_val_w[4:0]; wire [4:0] pi_fine_overflow_w; wire [5:0] pi_counter_read_val_w[4:0]; wire [4:0] pi_dqs_found_w; wire [4:0] pi_dqs_found_all_w; wire [4:0] pi_dqs_found_any_w; wire [4:0] pi_dqs_out_of_range_w; wire [4:0] pi_phase_locked_w; wire [4:0] pi_phase_locked_all_w; wire [4:0] rclk_w; wire [HIGHEST_BANK-1:0] phy_ctl_ready_w; wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0]; wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_; wire [3:0] if_q0; wire [3:0] if_q1; wire [3:0] if_q2; wire [3:0] if_q3; wire [3:0] if_q4; wire [7:0] if_q5; wire [7:0] if_q6; wire [3:0] if_q7; wire [3:0] if_q8; wire [3:0] if_q9; wire [31:0] _phy_ctl_wd; wire [3:0] aux_in_[4:1]; wire [3:0] rst_out_w; wire freq_refclk_split; wire mem_refclk_split; wire mem_refclk_div4_split; wire sync_pulse_split; wire phy_clk_split0; wire phy_ctl_clk_split0; wire [31:0] phy_ctl_wd_split0; wire phy_ctl_wr_split0; wire phy_ctl_clk_split1; wire phy_clk_split1; wire [31:0] phy_ctl_wd_split1; wire phy_ctl_wr_split1; wire [5:0] phy_data_offset_1_split1; wire phy_ctl_clk_split2; wire phy_clk_split2; wire [31:0] phy_ctl_wd_split2; wire phy_ctl_wr_split2; wire [5:0] phy_data_offset_2_split2; wire [HIGHEST_LANE*80-1:0] phy_dout_split0; wire phy_cmd_wr_en_split0; wire phy_data_wr_en_split0; wire phy_rd_en_split0; wire [HIGHEST_LANE*80-1:0] phy_dout_split1; wire phy_cmd_wr_en_split1; wire phy_data_wr_en_split1; wire phy_rd_en_split1; wire [HIGHEST_LANE*80-1:0] phy_dout_split2; wire phy_cmd_wr_en_split2; wire phy_data_wr_en_split2; wire phy_rd_en_split2; wire phy_ctl_mstr_empty; wire [HIGHEST_BANK-1:0] phy_ctl_empty; wire _phy_ctl_a_full_f; wire _phy_ctl_a_empty_f; wire _phy_ctl_full_f; wire _phy_ctl_empty_f; wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p; wire [HIGHEST_BANK-1:0] _phy_ctl_full_p; wire [HIGHEST_BANK-1:0] of_ctl_a_full_v; wire [HIGHEST_BANK-1:0] of_ctl_full_v; wire [HIGHEST_BANK-1:0] of_data_a_full_v; wire [HIGHEST_BANK-1:0] of_data_full_v; wire [HIGHEST_BANK-1:0] pre_data_a_full_v; wire [HIGHEST_BANK-1:0] if_empty_v; wire [HIGHEST_BANK-1:0] byte_rd_en_v; wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks; wire [HIGHEST_BANK-1:0] if_empty_or_v; wire [HIGHEST_BANK-1:0] if_empty_and_v; wire [HIGHEST_BANK-1:0] if_a_empty_v; localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4"; localparam IF_SYNCHRONOUS_MODE = "FALSE"; localparam IF_SLOW_WR_CLK = "FALSE"; localparam IF_SLOW_RD_CLK = "FALSE"; localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE"; localparam RCLK_NEG_EDGE = 3'b000; localparam RCLK_POS_EDGE = 3'b111; localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF; localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF; localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF; // hi, lo positions for data offset field, MIG doesn't allow defines localparam PC_DATA_OFFSET_RANGE_HI = 22; localparam PC_DATA_OFFSET_RANGE_LO = 17; /* Phaser_In Output source coding table "PHASE_REF" : 4'b0000; "DELAYED_MEM_REF" : 4'b0101; "DELAYED_PHASE_REF" : 4'b0011; "DELAYED_REF" : 4'b0001; "FREQ_REF" : 4'b1000; "MEM_REF" : 4'b0010; */ localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF"; localparam DDR_TCK = TCK; localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0; localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta /* Intrinsic delay of Phaser In Stage 1 @3300ps - 1.939ns - 58.8% @2500ps - 1.657ns - 66.3% @1875ps - 1.263ns - 67.4% @1500ps - 1.021ns - 68.1% @1250ps - 0.868ns - 69.4% @1072ps - 0.752ns - 70.1% @938ps - 0.667ns - 71.1% */ // If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0 // Fraction of a full DDR_TCK period localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 : ((DDR_TCK < 1005) ? 0.667 : (DDR_TCK < 1160) ? 0.752 : (DDR_TCK < 1375) ? 0.868 : (DDR_TCK < 1685) ? 1.021 : (DDR_TCK < 2185) ? 1.263 : (DDR_TCK < 2900) ? 1.657 : (DDR_TCK < 3100) ? 1.771 : 1.939)*1000; /* Intrinsic delay of Phaser In Stage 2 @3300ps - 0.912ns - 27.6% - single tap - 13ps @3000ps - 0.848ns - 28.3% - single tap - 11ps @2500ps - 1.264ns - 50.6% - single tap - 19ps @1875ps - 1.000ns - 53.3% - single tap - 15ps @1500ps - 0.848ns - 56.5% - single tap - 11ps @1250ps - 0.736ns - 58.9% - single tap - 9ps @1072ps - 0.664ns - 61.9% - single tap - 8ps @938ps - 0.608ns - 64.8% - single tap - 7ps */ // Intrinsic delay = (.4218 + .0002freq(MHz))period(ps) localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor /* Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1 @3300ps - 1.294ns - 39.2% @2500ps - 1.294ns - 51.8% @1875ps - 1.030ns - 54.9% @1500ps - 0.878ns - 58.5% @1250ps - 0.766ns - 61.3% @1072ps - 0.694ns - 64.7% @938ps - 0.638ns - 68.0% Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0 @3300ps - 2.084ns - 63.2% - single tap - 20ps @2500ps - 2.084ns - 81.9% - single tap - 19ps @1875ps - 1.676ns - 89.4% - single tap - 15ps @1500ps - 1.444ns - 96.3% - single tap - 11ps @1250ps - 1.276ns - 102.1% - single tap - 9ps @1072ps - 1.164ns - 108.6% - single tap - 8ps @938ps - 1.076ns - 114.7% - single tap - 7ps */ // Fraction of a full DDR_TCK period localparam real PO_STG1_INTRINSIC_DELAY = 0; localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY + (PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY); // When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can // go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this, // a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments // to the stage 2 delay can be made after reset is removed. localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line localparam real PO_CIRC_BUF_META_ZONE = 200.0; localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0; localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK; // If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold // If it is not more than the threshold than we must push the delay after the clock period plus a guardband. //A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated. localparam integer PO_CIRC_BUF_DELAY = 60; //localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 : // (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE : // (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE; localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE; localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY; localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY; localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE); localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi // The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path // of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the // oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment // is within the range of the stage 2 delay line in the Phaser_In. localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY); localparam integer PO_DELAY_INT = PO_DELAY; localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK); // if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is // if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge. // note that in this case PI_OFFSET is negative so invert before subtracting. localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0 ? PI_OFFSET : ((-PI_OFFSET) < DDR_TCK/2) ? (DDR_TCK/2 - (- PI_OFFSET)) : (DDR_TCK - (- PI_OFFSET)) ; localparam real PI_STG2_DELAY = (PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ? PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND); localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE; localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE)); localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ; localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; wire _phy_clk; wire [2:0] mcGo_w; wire [HIGHEST_BANK-1:0] ref_dll_lock_w; reg [15:0] mcGo_r; assign ref_dll_lock = & ref_dll_lock_w; initial begin if ( SYNTHESIS == "FALSE" ) begin $display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1); $display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1); $display("%m : HIGHEST_BANK = %d", HIGHEST_BANK); $display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD); $display("%m : DDR_TCK = %0d ", DDR_TCK); $display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE); $display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY); $display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET); $display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE); $display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY); $display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY); $display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY); $display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY); $display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY); $display("%m : PO_DELAY = %0.2f ", PO_DELAY); $display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY); $display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY); $display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY); $display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY); $display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY); $display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY); $display("%m : PI_OFFSET = %0.2f ", PI_OFFSET); if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used."); $display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY); $display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND); $display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY); $display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE); end // SYNTHESIS if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY); end assign sync_pulse_split = sync_pulse; assign mem_refclk_split = mem_refclk; assign freq_refclk_split = freq_refclk; assign mem_refclk_div4_split = mem_refclk_div4; assign phy_ctl_clk_split0 = _phy_clk; assign phy_ctl_wd_split0 = phy_ctl_wd; assign phy_ctl_wr_split0 = phy_ctl_wr; assign phy_clk_split0 = phy_clk; assign phy_cmd_wr_en_split0 = phy_cmd_wr_en; assign phy_data_wr_en_split0 = phy_data_wr_en; assign phy_rd_en_split0 = phy_rd_en; assign phy_dout_split0 = phy_dout; assign phy_ctl_clk_split1 = phy_clk; assign phy_ctl_wd_split1 = phy_ctl_wd; assign phy_data_offset_1_split1 = data_offset_1; assign phy_ctl_wr_split1 = phy_ctl_wr; assign phy_clk_split1 = phy_clk; assign phy_cmd_wr_en_split1 = phy_cmd_wr_en; assign phy_data_wr_en_split1 = phy_data_wr_en; assign phy_rd_en_split1 = phy_rd_en; assign phy_dout_split1 = phy_dout; assign phy_ctl_clk_split2 = phy_clk; assign phy_ctl_wd_split2 = phy_ctl_wd; assign phy_data_offset_2_split2 = data_offset_2; assign phy_ctl_wr_split2 = phy_ctl_wr; assign phy_clk_split2 = phy_clk; assign phy_cmd_wr_en_split2 = phy_cmd_wr_en; assign phy_data_wr_en_split2 = phy_data_wr_en; assign phy_rd_en_split2 = phy_rd_en; assign phy_dout_split2 = phy_dout; // these wires are needed to coerce correct synthesis // the synthesizer did not always see the widths of the // parameters as 4 bits. wire [3:0] blb0 = BYTE_LANES_B0; wire [3:0] blb1 = BYTE_LANES_B1; wire [3:0] blb2 = BYTE_LANES_B2; wire [3:0] dcb0 = DATA_CTL_B0; wire [3:0] dcb1 = DATA_CTL_B1; wire [3:0] dcb2 = DATA_CTL_B2; assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0}); assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0}); assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0]; assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs}; //Added to remove concadination in the instantiation assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ; assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ; assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ; assign calib_zero_lanes_int = calib_zero_lanes; assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0]; assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL]; assign of_ctl_a_full = |of_ctl_a_full_v; assign of_ctl_full = |of_ctl_full_v; assign of_data_a_full = |of_data_a_full_v; assign of_data_full = |of_data_full_v; assign pre_data_a_full= |pre_data_a_full_v; // if if_empty_def == 1, empty is asserted only if all are empty; // this allows the user to detect a skewed fifo depth and self-clear // if desired. It avoids a reset to clear the flags. assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v; assign if_empty_or = |if_empty_or_v; assign if_empty_and = &if_empty_and_v; assign if_a_empty = |if_a_empty_v; generate genvar i; for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff) 16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; 16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; 16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; 16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; 16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; 16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; 16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; 16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; 16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; 16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; 16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; 16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff )); endcase end endgenerate //assign rclk = rclk_w[RCLK_SELECT_BANK]; reg rst_auxout; reg rst_auxout_r; reg rst_auxout_rr; always @(posedge auxout_clk or posedge rst) begin if ( rst) begin rst_auxout_r <= #(1) 1'b1; rst_auxout_rr <= #(1) 1'b1; end else begin rst_auxout_r <= #(1) rst; rst_auxout_rr <= #(1) rst_auxout_r; end end if ( LP_RCLK_SELECT_EDGE[0]) begin always @(posedge auxout_clk or posedge rst) begin if ( rst) begin rst_auxout <= #(1) 1'b1; end else begin rst_auxout <= #(1) rst_auxout_rr; end end end else begin always @(negedge auxout_clk or posedge rst) begin if ( rst) begin rst_auxout <= #(1) 1'b1; end else begin rst_auxout <= #(1) rst_auxout_rr; end end end localparam L_RESET_SELECT_BANK = (BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK; always @(*) begin rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n; end always @(posedge phy_clk) begin if ( rst) mcGo_r <= #(1) 0; else mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w; end assign mcGo = mcGo_r[15]; generate // this is an optional 1 clock delay to add latency to the phy_control programming path if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft reg [31:0] phy_wd_reg = 0; reg [3:0] aux_in1_reg = 0; reg [3:0] aux_in2_reg = 0; reg sfifo_ready = 0; assign _phy_ctl_wd = phy_wd_reg; assign aux_in_[1] = aux_in1_reg; assign aux_in_[2] = aux_in2_reg; assign phy_ctl_a_full = |_phy_ctl_a_full_p; assign phy_ctl_full[0] = |_phy_ctl_full_p; assign phy_ctl_full[1] = |_phy_ctl_full_p; assign phy_ctl_full[2] = |_phy_ctl_full_p; assign phy_ctl_full[3] = |_phy_ctl_full_p; assign _phy_clk = phy_clk; always @(posedge phy_clk) begin phy_wd_reg <= #1 phy_ctl_wd; aux_in1_reg <= #1 aux_in_1; aux_in2_reg <= #1 aux_in_2; sfifo_ready <= #1 phy_ctl_wr; end end else if (PHYCTL_CMD_FIFO == "FALSE") begin assign _phy_ctl_wd = phy_ctl_wd; assign aux_in_[1] = aux_in_1; assign aux_in_[2] = aux_in_2; assign phy_ctl_a_full = |_phy_ctl_a_full_p; assign phy_ctl_full[0] = |_phy_ctl_full_p; assign phy_ctl_full[3:1] = 3'b000; assign _phy_clk = phy_clk; end endgenerate // instance of four-lane phy generate if (HIGHEST_BANK == 3) begin : banks_3 assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]}; assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]}; assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]}; end else if (HIGHEST_BANK == 2) begin : banks_2 assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1}; assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1}; end else begin : banks_1 assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1}; end if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0 mig_7series_v4_0_ddr_phy_4lanes # ( .BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */ .DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */ .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), .PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY), .BITLANES (PHY_0_BITLANES), .BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK), .LAST_BANK (PHY_0_IS_LAST_BANK), .LANE_REMAP (PHY_0_LANE_REMAP), .OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE), .IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE), .GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL), .IODELAY_GRP (PHY_0_IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .NUM_DDR_CK (NUM_DDR_CK), .TCK (TCK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .PC_CLK_RATIO (PHY_CLK_RATIO), .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), .PC_BURST_MODE (PHY_0_A_BURST_MODE), .PC_SYNC_MODE (PHY_SYNC_MODE), .PC_MULTI_REGION (PHY_MULTI_REGION), .PC_PHY_COUNT_EN (PHY_COUNT_EN), .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), .PC_CMD_OFFSET (PHY_0_CMD_OFFSET), .PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PC_RD_DURATION_0 (PHY_0_RD_DURATION_0), .PC_RD_DURATION_1 (PHY_0_RD_DURATION_1), .PC_RD_DURATION_2 (PHY_0_RD_DURATION_2), .PC_RD_DURATION_3 (PHY_0_RD_DURATION_3), .PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PC_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PC_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PC_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PC_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN), .PC_AO_TOGGLE (PHY_0_AO_TOGGLE), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY), .B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY), .C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY), .D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY), .A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .A_PI_BURST_MODE (PHY_0_A_BURST_MODE), .A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC), .B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC), .C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC), .D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC), .A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC), .A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV), .A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE), .B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE), .C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE), .D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE), .A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE), .B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE), .C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE), .D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE), .A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE), .A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH), .B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE), .B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH), .C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE), .C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH), .D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE), .D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH), .A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE), .A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_phy_4lanes ( .rst (rst), .phy_clk (phy_clk_split0), .clk_div2 (clk_div2), .phy_ctl_clk (phy_ctl_clk_split0), .phy_ctl_wd (phy_ctl_wd_split0), .data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]), .phy_ctl_wr (phy_ctl_wr_split0), .mem_refclk (mem_refclk_split), .freq_refclk (freq_refclk_split), .mem_refclk_div4 (mem_refclk_div4_split), .sync_pulse (sync_pulse_split), .phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]), .phy_cmd_wr_en (phy_cmd_wr_en_split0), .phy_data_wr_en (phy_data_wr_en_split0), .phy_rd_en (phy_rd_en_split0), .pll_lock (pll_lock), .ddr_clk (ddr_clk_w[0]), .rclk (), .rst_out (rst_out_w[0]), .mcGo (mcGo_w[0]), .ref_dll_lock (ref_dll_lock_w[0]), .idelayctrl_refclk (idelayctrl_refclk), .idelay_inc (idelay_inc), .idelay_ce (idelay_ce), .idelay_ld (idelay_ld), .phy_ctl_mstr_empty (phy_ctl_mstr_empty), .if_rst (if_rst), .if_empty_def (if_empty_def), .byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]), .if_a_empty (if_a_empty_v[0]), .if_empty (if_empty_v[0]), .byte_rd_en (byte_rd_en_v[0]), .if_empty_or (if_empty_or_v[0]), .if_empty_and (if_empty_and_v[0]), .of_ctl_a_full (of_ctl_a_full_v[0]), .of_data_a_full (of_data_a_full_v[0]), .of_ctl_full (of_ctl_full_v[0]), .of_data_full (of_data_full_v[0]), .pre_data_a_full (pre_data_a_full_v[0]), .phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]), .phy_ctl_a_full (_phy_ctl_a_full_p[0]), .phy_ctl_full (_phy_ctl_full_p[0]), .phy_ctl_empty (phy_ctl_empty[0]), .mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]), .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]), .mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]), .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]), .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]), .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]), .aux_out (aux_out_[3:0]), .phy_ctl_ready (phy_ctl_ready_w[0]), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), // .scan_test_bus_A (scan_test_bus_A), // .scan_test_bus_B (), // .scan_test_bus_C (), // .scan_test_bus_D (), .phyGo (phyGo), .input_sink (input_sink), .calib_sel (calib_sel_byte0), .calib_zero_ctrl (calib_zero_ctrl[0]), .calib_zero_lanes (calib_zero_lanes_int[3:0]), .calib_in_common (calib_in_common), .po_coarse_enable (po_coarse_enable[0]), .po_fine_enable (po_fine_enable[0]), .po_fine_inc (po_fine_inc[0]), .po_coarse_inc (po_coarse_inc[0]), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (po_coarse_overflow_w[0]), .po_fine_overflow (po_fine_overflow_w[0]), .po_counter_read_val (po_counter_read_val_w[0]), .pi_rst_dqs_find (pi_rst_dqs_find[0]), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (pi_fine_overflow_w[0]), .pi_counter_read_val (pi_counter_read_val_w[0]), .pi_dqs_found (pi_dqs_found_w[0]), .pi_dqs_found_all (pi_dqs_found_all_w[0]), .pi_dqs_found_any (pi_dqs_found_any_w[0]), .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]), .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]), .pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]), .pi_phase_locked (pi_phase_locked_w[0]), .pi_phase_locked_all (pi_phase_locked_all_w[0]), .fine_delay (fine_delay), .fine_delay_sel (fine_delay_sel) ); always @(posedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[0] <= #100 0; aux_out[2] <= #100 0; end else begin aux_out[0] <= #100 aux_out_[0]; aux_out[2] <= #100 aux_out_[2]; end end if ( LP_RCLK_SELECT_EDGE[0]) begin always @(posedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[1] <= #100 0; aux_out[3] <= #100 0; end else begin aux_out[1] <= #100 aux_out_[1]; aux_out[3] <= #100 aux_out_[3]; end end end else begin always @(negedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[1] <= #100 0; aux_out[3] <= #100 0; end else begin aux_out[1] <= #100 aux_out_[1]; aux_out[3] <= #100 aux_out_[3]; end end end end else begin if ( HIGHEST_BANK > 0) begin assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0; assign _phy_ctl_a_full_p[0] = 0; assign of_ctl_a_full_v[0] = 0; assign of_ctl_full_v[0] = 0; assign of_data_a_full_v[0] = 0; assign of_data_full_v[0] = 0; assign pre_data_a_full_v[0] = 0; assign if_empty_v[0] = 0; assign byte_rd_en_v[0] = 1; always @(*) aux_out[3:0] = 0; end assign pi_dqs_found_w[0] = 1; assign pi_dqs_found_all_w[0] = 1; assign pi_dqs_found_any_w[0] = 0; assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111; assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111; assign pi_dqs_out_of_range_w[0] = 0; assign pi_phase_locked_w[0] = 1; assign po_fine_overflow_w[0] = 0; assign po_coarse_overflow_w[0] = 0; assign po_fine_overflow_w[0] = 0; assign pi_fine_overflow_w[0] = 0; assign po_counter_read_val_w[0] = 0; assign pi_counter_read_val_w[0] = 0; assign mcGo_w[0] = 1; if ( RCLK_SELECT_BANK == 0) always @(*) aux_out[3:0] = 0; end if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1 mig_7series_v4_0_ddr_phy_4lanes # ( .BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */ .DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */ .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), .PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY), .BITLANES (PHY_1_BITLANES), .BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK), .LAST_BANK (PHY_1_IS_LAST_BANK ), .LANE_REMAP (PHY_1_LANE_REMAP), .OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE), .IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE), .GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL), .IODELAY_GRP (PHY_1_IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .NUM_DDR_CK (NUM_DDR_CK), .TCK (TCK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .PC_CLK_RATIO (PHY_CLK_RATIO), .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), .PC_BURST_MODE (PHY_1_A_BURST_MODE), .PC_SYNC_MODE (PHY_SYNC_MODE), .PC_MULTI_REGION (PHY_MULTI_REGION), .PC_PHY_COUNT_EN (PHY_COUNT_EN), .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), .PC_CMD_OFFSET (PHY_1_CMD_OFFSET), .PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0), .PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1), .PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2), .PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3), .PC_RD_DURATION_0 (PHY_1_RD_DURATION_0), .PC_RD_DURATION_1 (PHY_1_RD_DURATION_1), .PC_RD_DURATION_2 (PHY_1_RD_DURATION_2), .PC_RD_DURATION_3 (PHY_1_RD_DURATION_3), .PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0), .PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1), .PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2), .PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3), .PC_WR_DURATION_0 (PHY_1_WR_DURATION_0), .PC_WR_DURATION_1 (PHY_1_WR_DURATION_1), .PC_WR_DURATION_2 (PHY_1_WR_DURATION_2), .PC_WR_DURATION_3 (PHY_1_WR_DURATION_3), .PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN), .PC_AO_TOGGLE (PHY_1_AO_TOGGLE), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY), .B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY), .C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY), .D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY), .A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV), .A_PI_BURST_MODE (PHY_1_A_BURST_MODE), .A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC), .B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC), .C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC), .D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC), .A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC), .A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY), .A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV), .A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE), .B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE), .C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE), .D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE), .A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE), .B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE), .C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE), .D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE), .A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE), .A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH), .B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE), .B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH), .C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE), .C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH), .D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE), .D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH), .A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE), .A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_phy_4lanes ( .rst (rst), .phy_clk (phy_clk_split1), .clk_div2 (clk_div2), .phy_ctl_clk (phy_ctl_clk_split1), .phy_ctl_wd (phy_ctl_wd_split1), .data_offset (phy_data_offset_1_split1), .phy_ctl_wr (phy_ctl_wr_split1), .mem_refclk (mem_refclk_split), .freq_refclk (freq_refclk_split), .mem_refclk_div4 (mem_refclk_div4_split), .sync_pulse (sync_pulse_split), .phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]), .phy_cmd_wr_en (phy_cmd_wr_en_split1), .phy_data_wr_en (phy_data_wr_en_split1), .phy_rd_en (phy_rd_en_split1), .pll_lock (pll_lock), .ddr_clk (ddr_clk_w[1]), .rclk (), .rst_out (rst_out_w[1]), .mcGo (mcGo_w[1]), .ref_dll_lock (ref_dll_lock_w[1]), .idelayctrl_refclk (idelayctrl_refclk), .idelay_inc (idelay_inc), .idelay_ce (idelay_ce), .idelay_ld (idelay_ld), .phy_ctl_mstr_empty (phy_ctl_mstr_empty), .if_rst (if_rst), .if_empty_def (if_empty_def), .byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]), .if_a_empty (if_a_empty_v[1]), .if_empty (if_empty_v[1]), .byte_rd_en (byte_rd_en_v[1]), .if_empty_or (if_empty_or_v[1]), .if_empty_and (if_empty_and_v[1]), .of_ctl_a_full (of_ctl_a_full_v[1]), .of_data_a_full (of_data_a_full_v[1]), .of_ctl_full (of_ctl_full_v[1]), .of_data_full (of_data_full_v[1]), .pre_data_a_full (pre_data_a_full_v[1]), .phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]), .phy_ctl_a_full (_phy_ctl_a_full_p[1]), .phy_ctl_full (_phy_ctl_full_p[1]), .phy_ctl_empty (phy_ctl_empty[1]), .mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]), .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]), .mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]), .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]), .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]), .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]), .aux_out (aux_out_[7:4]), .phy_ctl_ready (phy_ctl_ready_w[1]), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), // .scan_test_bus_A (scan_test_bus_A), // .scan_test_bus_B (), // .scan_test_bus_C (), // .scan_test_bus_D (), .phyGo (phyGo), .input_sink (input_sink), .calib_sel (calib_sel_byte1), .calib_zero_ctrl (calib_zero_ctrl[1]), .calib_zero_lanes (calib_zero_lanes_int[7:4]), .calib_in_common (calib_in_common), .po_coarse_enable (po_coarse_enable[1]), .po_fine_enable (po_fine_enable[1]), .po_fine_inc (po_fine_inc[1]), .po_coarse_inc (po_coarse_inc[1]), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (po_coarse_overflow_w[1]), .po_fine_overflow (po_fine_overflow_w[1]), .po_counter_read_val (po_counter_read_val_w[1]), .pi_rst_dqs_find (pi_rst_dqs_find[1]), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (pi_fine_overflow_w[1]), .pi_counter_read_val (pi_counter_read_val_w[1]), .pi_dqs_found (pi_dqs_found_w[1]), .pi_dqs_found_all (pi_dqs_found_all_w[1]), .pi_dqs_found_any (pi_dqs_found_any_w[1]), .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]), .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]), .pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]), .pi_phase_locked (pi_phase_locked_w[1]), .pi_phase_locked_all (pi_phase_locked_all_w[1]), .fine_delay (fine_delay), .fine_delay_sel (fine_delay_sel) ); always @(posedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[4] <= #100 0; aux_out[6] <= #100 0; end else begin aux_out[4] <= #100 aux_out_[4]; aux_out[6] <= #100 aux_out_[6]; end end if ( LP_RCLK_SELECT_EDGE[1]) begin always @(posedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[5] <= #100 0; aux_out[7] <= #100 0; end else begin aux_out[5] <= #100 aux_out_[5]; aux_out[7] <= #100 aux_out_[7]; end end end else begin always @(negedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[5] <= #100 0; aux_out[7] <= #100 0; end else begin aux_out[5] <= #100 aux_out_[5]; aux_out[7] <= #100 aux_out_[7]; end end end end else begin if ( HIGHEST_BANK > 1) begin assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0; assign _phy_ctl_a_full_p[1] = 0; assign of_ctl_a_full_v[1] = 0; assign of_ctl_full_v[1] = 0; assign of_data_a_full_v[1] = 0; assign of_data_full_v[1] = 0; assign pre_data_a_full_v[1] = 0; assign if_empty_v[1] = 0; assign byte_rd_en_v[1] = 1; assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111; assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111; always @(*) aux_out[7:4] = 0; end assign pi_dqs_found_w[1] = 1; assign pi_dqs_found_all_w[1] = 1; assign pi_dqs_found_any_w[1] = 0; assign pi_dqs_out_of_range_w[1] = 0; assign pi_phase_locked_w[1] = 1; assign po_coarse_overflow_w[1] = 0; assign po_fine_overflow_w[1] = 0; assign pi_fine_overflow_w[1] = 0; assign po_counter_read_val_w[1] = 0; assign pi_counter_read_val_w[1] = 0; assign mcGo_w[1] = 1; end if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2 mig_7series_v4_0_ddr_phy_4lanes # ( .BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */ .DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */ .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), .PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY), .BITLANES (PHY_2_BITLANES), .BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK), .LAST_BANK (PHY_2_IS_LAST_BANK ), .LANE_REMAP (PHY_2_LANE_REMAP), .OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE), .IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE), .GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL), .IODELAY_GRP (PHY_2_IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .NUM_DDR_CK (NUM_DDR_CK), .TCK (TCK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .PC_CLK_RATIO (PHY_CLK_RATIO), .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), .PC_BURST_MODE (PHY_2_A_BURST_MODE), .PC_SYNC_MODE (PHY_SYNC_MODE), .PC_MULTI_REGION (PHY_MULTI_REGION), .PC_PHY_COUNT_EN (PHY_COUNT_EN), .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), .PC_CMD_OFFSET (PHY_2_CMD_OFFSET), .PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0), .PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1), .PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2), .PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3), .PC_RD_DURATION_0 (PHY_2_RD_DURATION_0), .PC_RD_DURATION_1 (PHY_2_RD_DURATION_1), .PC_RD_DURATION_2 (PHY_2_RD_DURATION_2), .PC_RD_DURATION_3 (PHY_2_RD_DURATION_3), .PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0), .PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1), .PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2), .PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3), .PC_WR_DURATION_0 (PHY_2_WR_DURATION_0), .PC_WR_DURATION_1 (PHY_2_WR_DURATION_1), .PC_WR_DURATION_2 (PHY_2_WR_DURATION_2), .PC_WR_DURATION_3 (PHY_2_WR_DURATION_3), .PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN), .PC_AO_TOGGLE (PHY_2_AO_TOGGLE), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY), .B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY), .C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY), .D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY), .A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV), .A_PI_BURST_MODE (PHY_2_A_BURST_MODE), .A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC), .B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC), .C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC), .D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC), .A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC), .A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY), .A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV), .A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE), .B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE), .C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE), .D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE), .A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE), .B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE), .C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE), .D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE), .A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE), .A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH), .B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE), .B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH), .C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE), .C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH), .D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE), .D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH), .A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE), .A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_phy_4lanes ( .rst (rst), .phy_clk (phy_clk_split2), .clk_div2 (clk_div2), .phy_ctl_clk (phy_ctl_clk_split2), .phy_ctl_wd (phy_ctl_wd_split2), .data_offset (phy_data_offset_2_split2), .phy_ctl_wr (phy_ctl_wr_split2), .mem_refclk (mem_refclk_split), .freq_refclk (freq_refclk_split), .mem_refclk_div4 (mem_refclk_div4_split), .sync_pulse (sync_pulse_split), .phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]), .phy_cmd_wr_en (phy_cmd_wr_en_split2), .phy_data_wr_en (phy_data_wr_en_split2), .phy_rd_en (phy_rd_en_split2), .pll_lock (pll_lock), .ddr_clk (ddr_clk_w[2]), .rclk (), .rst_out (rst_out_w[2]), .mcGo (mcGo_w[2]), .ref_dll_lock (ref_dll_lock_w[2]), .idelayctrl_refclk (idelayctrl_refclk), .idelay_inc (idelay_inc), .idelay_ce (idelay_ce), .idelay_ld (idelay_ld), .phy_ctl_mstr_empty (phy_ctl_mstr_empty), .if_rst (if_rst), .if_empty_def (if_empty_def), .byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]), .if_a_empty (if_a_empty_v[2]), .if_empty (if_empty_v[2]), .byte_rd_en (byte_rd_en_v[2]), .if_empty_or (if_empty_or_v[2]), .if_empty_and (if_empty_and_v[2]), .of_ctl_a_full (of_ctl_a_full_v[2]), .of_data_a_full (of_data_a_full_v[2]), .of_ctl_full (of_ctl_full_v[2]), .of_data_full (of_data_full_v[2]), .pre_data_a_full (pre_data_a_full_v[2]), .phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]), .phy_ctl_a_full (_phy_ctl_a_full_p[2]), .phy_ctl_full (_phy_ctl_full_p[2]), .phy_ctl_empty (phy_ctl_empty[2]), .mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]), .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]), .mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]), .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]), .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]), .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]), .aux_out (aux_out_[11:8]), .phy_ctl_ready (phy_ctl_ready_w[2]), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), // .scan_test_bus_A (scan_test_bus_A), // .scan_test_bus_B (), // .scan_test_bus_C (), // .scan_test_bus_D (), .phyGo (phyGo), .input_sink (input_sink), .calib_sel (calib_sel_byte2), .calib_zero_ctrl (calib_zero_ctrl[2]), .calib_zero_lanes (calib_zero_lanes_int[11:8]), .calib_in_common (calib_in_common), .po_coarse_enable (po_coarse_enable[2]), .po_fine_enable (po_fine_enable[2]), .po_fine_inc (po_fine_inc[2]), .po_coarse_inc (po_coarse_inc[2]), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (po_coarse_overflow_w[2]), .po_fine_overflow (po_fine_overflow_w[2]), .po_counter_read_val (po_counter_read_val_w[2]), .pi_rst_dqs_find (pi_rst_dqs_find[2]), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (pi_fine_overflow_w[2]), .pi_counter_read_val (pi_counter_read_val_w[2]), .pi_dqs_found (pi_dqs_found_w[2]), .pi_dqs_found_all (pi_dqs_found_all_w[2]), .pi_dqs_found_any (pi_dqs_found_any_w[2]), .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]), .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]), .pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]), .pi_phase_locked (pi_phase_locked_w[2]), .pi_phase_locked_all (pi_phase_locked_all_w[2]), .fine_delay (fine_delay), .fine_delay_sel (fine_delay_sel) ); always @(posedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[8] <= #100 0; aux_out[10] <= #100 0; end else begin aux_out[8] <= #100 aux_out_[8]; aux_out[10] <= #100 aux_out_[10]; end end if ( LP_RCLK_SELECT_EDGE[1]) begin always @(posedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[9] <= #100 0; aux_out[11] <= #100 0; end else begin aux_out[9] <= #100 aux_out_[9]; aux_out[11] <= #100 aux_out_[11]; end end end else begin always @(negedge auxout_clk or posedge rst_auxout) begin if (rst_auxout) begin aux_out[9] <= #100 0; aux_out[11] <= #100 0; end else begin aux_out[9] <= #100 aux_out_[9]; aux_out[11] <= #100 aux_out_[11]; end end end end else begin if ( HIGHEST_BANK > 2) begin assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0; assign _phy_ctl_a_full_p[2] = 0; assign of_ctl_a_full_v[2] = 0; assign of_ctl_full_v[2] = 0; assign of_data_a_full_v[2] = 0; assign of_data_full_v[2] = 0; assign pre_data_a_full_v[2] = 0; assign if_empty_v[2] = 0; assign byte_rd_en_v[2] = 1; assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111; assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111; always @(*) aux_out[11:8] = 0; end assign pi_dqs_found_w[2] = 1; assign pi_dqs_found_all_w[2] = 1; assign pi_dqs_found_any_w[2] = 0; assign pi_dqs_out_of_range_w[2] = 0; assign pi_phase_locked_w[2] = 1; assign po_coarse_overflow_w[2] = 0; assign po_fine_overflow_w[2] = 0; assign po_counter_read_val_w[2] = 0; assign pi_counter_read_val_w[2] = 0; assign mcGo_w[2] = 1; end endgenerate generate // for single bank , emit an extra phaser_in to generate rclk // so that auxout can be placed in another region // if desired if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0) begin : phaser_in_rclk localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY; PHASER_IN_PHY #( .BURST_MODE ( PHY_0_A_BURST_MODE), .CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV), .FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV), .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), .FINE_DELAY ( L_EXTRA_PI_FINE_DELAY), .OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC) ) phaser_in_rclk ( .DQSFOUND (), .DQSOUTOFRANGE (), .FINEOVERFLOW (), .PHASELOCKED (), .ISERDESRST (), .ICLKDIV (), .ICLK (), .COUNTERREADVAL (), .RCLK (), .WRENABLE (), .BURSTPENDINGPHY (), .ENCALIBPHY (), .FINEENABLE (0), .FREQREFCLK (freq_refclk), .MEMREFCLK (mem_refclk), .RANKSELPHY (0), .PHASEREFCLK (), .RSTDQSFIND (0), .RST (rst), .FINEINC (), .COUNTERLOADEN (), .COUNTERREADEN (), .COUNTERLOADVAL (), .SYNCIN (sync_pulse), .SYSCLK (phy_clk) ); end endgenerate always @(*) begin case (calib_sel[5:3]) 3'b000: begin po_coarse_overflow = po_coarse_overflow_w[0]; po_fine_overflow = po_fine_overflow_w[0]; po_counter_read_val = po_counter_read_val_w[0]; pi_fine_overflow = pi_fine_overflow_w[0]; pi_counter_read_val = pi_counter_read_val_w[0]; pi_phase_locked = pi_phase_locked_w[0]; if ( calib_in_common) pi_dqs_found = pi_dqs_found_any; else pi_dqs_found = pi_dqs_found_w[0]; pi_dqs_out_of_range = pi_dqs_out_of_range_w[0]; end 3'b001: begin po_coarse_overflow = po_coarse_overflow_w[1]; po_fine_overflow = po_fine_overflow_w[1]; po_counter_read_val = po_counter_read_val_w[1]; pi_fine_overflow = pi_fine_overflow_w[1]; pi_counter_read_val = pi_counter_read_val_w[1]; pi_phase_locked = pi_phase_locked_w[1]; if ( calib_in_common) pi_dqs_found = pi_dqs_found_any; else pi_dqs_found = pi_dqs_found_w[1]; pi_dqs_out_of_range = pi_dqs_out_of_range_w[1]; end 3'b010: begin po_coarse_overflow = po_coarse_overflow_w[2]; po_fine_overflow = po_fine_overflow_w[2]; po_counter_read_val = po_counter_read_val_w[2]; pi_fine_overflow = pi_fine_overflow_w[2]; pi_counter_read_val = pi_counter_read_val_w[2]; pi_phase_locked = pi_phase_locked_w[2]; if ( calib_in_common) pi_dqs_found = pi_dqs_found_any; else pi_dqs_found = pi_dqs_found_w[2]; pi_dqs_out_of_range = pi_dqs_out_of_range_w[2]; end default: begin po_coarse_overflow = 0; po_fine_overflow = 0; po_counter_read_val = 0; pi_fine_overflow = 0; pi_counter_read_val = 0; pi_phase_locked = 0; pi_dqs_found = 0; pi_dqs_out_of_range = 0; end endcase end endmodule // mc_phy ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // ** Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1, parameter DRAM_WIDTH = 8, parameter PI_DIV2_INCDEC = "FALSE" ) ( input rst, input iddr_rst, input clk, input clk_div2, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input mmcm_ps_clk, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [DQS_CNT_WIDTH:0] byte_sel_cnt, input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, input fine_delay_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n, //output iodelay_ctrl_rdy, output pd_out ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; end end endfunction function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2*nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], DATA16_MAP[12*DQ_PER_DQS-1:0], DATA15_MAP[12*DQ_PER_DQS-1:0], DATA14_MAP[12*DQ_PER_DQS-1:0], DATA13_MAP[12*DQ_PER_DQS-1:0], DATA12_MAP[12*DQ_PER_DQS-1:0], DATA11_MAP[12*DQ_PER_DQS-1:0], DATA10_MAP[12*DQ_PER_DQS-1:0], DATA9_MAP[12*DQ_PER_DQS-1:0], DATA8_MAP[12*DQ_PER_DQS-1:0], DATA7_MAP[12*DQ_PER_DQS-1:0], DATA6_MAP[12*DQ_PER_DQS-1:0], DATA5_MAP[12*DQ_PER_DQS-1:0], DATA4_MAP[12*DQ_PER_DQS-1:0], DATA3_MAP[12*DQ_PER_DQS-1:0], DATA2_MAP[12*DQ_PER_DQS-1:0], DATA1_MAP[12*DQ_PER_DQS-1:0], DATA0_MAP[12*DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + 12*data_mask_in[(12*z+4)+:2] + data_mask_in[12*z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //*************************************************************************** // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //*************************************************************************** //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz //localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK >= 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";//DIV2 change localparam PO_OCLKDELAY_INV = (tCK >= 2500) ? "FALSE" : "TRUE";//DIV2 change //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK >= 2500 ? "DIV2": "NONE";//DIV2 change localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? // DIV2 change ((tCK >= 2500) ? 0 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : (tCK >= 2500) ? 0 : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE*10-1:0] mem_dq_in; wire [HIGHEST_LANE*12-1:0] mem_dq_out; wire [HIGHEST_LANE*12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; wire [DQS_WIDTH-1:0] pd_out_pre; //wire metaQ; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; reg [29:0] fine_delay_mod; //3 bit per DQ reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb wire iddr_rst_i; (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; assign iddr_rst_i = iddr_rst; //*************************************************************************** // Auxiliary output steering //*************************************************************************** // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //*************************************************************************** // Read data bit steering //*************************************************************************** // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTH*j + i] = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ 80*FULL_DATA_MAP[(12*i+4)+:2] + 8*FULL_DATA_MAP[12*i+:4]) + j]; end end endgenerate //generage idelay_inc per bits reg [11:0] cal_tmp; reg [95:0] byte_sel_data_map; assign byte_sel_cnt_w1 = byte_sel_cnt; always @ (posedge clk) begin byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; end always @ (posedge clk) begin fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; fine_delay_sel_r <= #TCQ fine_delay_sel; end //*************************************************************************** // Control/address //*************************************************************************** assign out_cas_n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //***************************************************************** generate genvar m, n,x; //***************************************************************** // Control/address (multi-bit) buses //***************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + 12*ADDR_MAP[(12*m+4)+:2] + ADDR_MAP[12*m+:4]]; if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*ADDR_MAP[12*m+:4] + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + 12*BANK_MAP[(12*m+4)+:2] + BANK_MAP[12*m+:4]]; if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*BANK_MAP[12*m+:4] + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + 12*CS_MAP[(12*m+4)+:2] + CS_MAP[12*m+:4]]; if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*CS_MAP[12*m+:4] + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*(CS_MAP[12*m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + 12*ODT_MAP[(12*m+4)+:2] + ODT_MAP[12*m+:4]]; if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*ODT_MAP[12*m+:4] + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + 12*CKE_MAP[(12*m+4)+:2] + CKE_MAP[12*m+:4]]; if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*CKE_MAP[12*m+:4] + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end end end //***************************************************************** // Data mask //***************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; assign ts_dm[m] = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + 80*FULL_MASK_MAP[(12*m+4)+:2] + 8*FULL_MASK_MAP[12*m+:4] + n] = mux_wrdata_mask[DM_WIDTH*n + m]; end end end //***************************************************************** // Input and output DQ //***************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + 10*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; assign ts_dq[m] = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + 80*FULL_DATA_MAP[(12*m+4)+:2] + 8*FULL_DATA_MAP[12*m+:4] + n] = mux_wrdata[DQ_WIDTH*n + m]; end end //***************************************************************** // Input and output DQS //***************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; end endgenerate assign pd_out = pd_out_pre[byte_sel_cnt_w1]; //*************************************************************************** // Memory I/F output and I/O buffer instantiation //*************************************************************************** // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v4_0_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst_i), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), //.IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v4_0_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst_i), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v4_0_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v4_0_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v4_0_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //*************************************************************************** // Hard PHY instantiation //*************************************************************************** assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v4_0_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP), .PHY_1_IODELAY_GRP (IODELAY_GRP), .PHY_2_IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .CKE_ODT_AUX (CKE_ODT_AUX), .PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .clk_div2 (clk_div2), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) ,.fine_delay (fine_delay_mod) ,.fine_delay_sel (fine_delay_sel_r) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_of_pre_fifo.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Feb 08 2011 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries //Reference : //Revision History : //***************************************************************************** /****************************************************************************** **$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $ **$Date: 2011/06/02 08:35:07 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $ ******************************************************************************/ `timescale 1 ps / 1 ps module mig_7series_v4_0_ddr_of_pre_fifo # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DEPTH = 4, // # of entries parameter WIDTH = 32 // data bus width ) ( input clk, // clock input rst, // synchronous reset input full_in, // FULL flag from OUT_FIFO input wr_en_in, // write enable from controller input [WIDTH-1:0] d_in, // write data from controller output wr_en_out, // write enable to OUT_FIFO output [WIDTH-1:0] d_out, // write data to OUT_FIFO output afull // almost full signal to controller ); // # of bits used to represent read/write pointers localparam PTR_BITS = (DEPTH == 2) ? 1 : ((DEPTH == 3) || (DEPTH == 4)) ? 2 : (((DEPTH == 5) || (DEPTH == 6) || (DEPTH == 7) || (DEPTH == 8)) ? 3 : DEPTH == 9 ? 4 : 'bx); // Set watermark. Always give the MC 5 cycles to engage flow control. localparam ALMOST_FULL_VALUE = DEPTH - 5; integer i; reg [WIDTH-1:0] mem[0:DEPTH-1] ; reg [8:0] my_empty /* synthesis syn_maxfan = 3 */; reg [5:0] my_full /* synthesis syn_maxfan = 3 */; reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */; reg [PTR_BITS:0] entry_cnt; wire [PTR_BITS-1:0] nxt_rd_ptr; wire [PTR_BITS-1:0] nxt_wr_ptr; wire [WIDTH-1:0] mem_out; (* max_fanout = 50 *) wire wr_en; assign d_out = my_empty[0] ? d_in : mem_out; assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in); assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in)); always @ (posedge clk) if (wr_en) mem[wr_ptr] <= #TCQ d_in; assign mem_out = mem[rd_ptr]; assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin rd_ptr <= 'b0; rd_ptr_timing <= 'b0; end else if ((!my_empty[4]) & (!full_in)) begin rd_ptr <= nxt_rd_ptr; rd_ptr_timing <= nxt_rd_ptr; end end always @ (posedge clk) begin if (rst) my_empty <= 9'h1ff; else begin if (my_empty[2] & !my_full[3] & full_in & wr_en_in) my_empty[3:0] <= 4'b0000; else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing); end if (my_empty[8] & !my_full[5] & full_in & wr_en_in) my_empty[8:4] <= 5'b00000; else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing); end end end assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin wr_ptr <= 'b0; wr_ptr_timing <= 'b0; end else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin wr_ptr <= nxt_wr_ptr; wr_ptr_timing <= nxt_wr_ptr; end end always @ (posedge clk) begin if (rst) my_full <= 6'b000000; else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in) my_full <= 6'b000000; else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin my_full[0] <= (nxt_wr_ptr == rd_ptr_timing); my_full[1] <= (nxt_wr_ptr == rd_ptr_timing); my_full[2] <= (nxt_wr_ptr == rd_ptr_timing); my_full[3] <= (nxt_wr_ptr == rd_ptr_timing); my_full[4] <= (nxt_wr_ptr == rd_ptr_timing); my_full[5] <= (nxt_wr_ptr == rd_ptr_timing); end end always @ (posedge clk) begin if (rst) entry_cnt <= 'b0; else if (wr_en_in & full_in & !my_full[4]) entry_cnt <= entry_cnt + 1'b1; else if (!wr_en_in & !full_in & !my_empty[7]) entry_cnt <= entry_cnt - 1'b1; end assign afull = (entry_cnt >= ALMOST_FULL_VALUE); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v ================================================ /********************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is the parameterizable 4-byte lane phy primitive top // This module may be ganged to create an N-lane phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // /////////////////////////////////////////////////////////// **********************************************************/ `timescale 1ps/1ps `define PC_DATA_OFFSET_RANGE 22:17 module mig_7series_v4_0_ddr_phy_4lanes #( parameter GENERATE_IDELAYCTRL = "TRUE", parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter NUM_DDR_CK = 1, // next three parameter fields correspond to byte lanes for lane order DCBA parameter BYTE_LANES = 4'b1111, // lane existence, one per lane parameter DATA_CTL_N = 4'b1111, // data or control, per lane parameter BITLANES = 48'hffff_ffff_ffff, parameter BITLANES_OUTONLY = 48'h0000_0000_0000, parameter LANE_REMAP = 16'h3210,// 4-bit index // used to rewire to one of four // input/output buss lanes // example: 0321 remaps lanes as: // D->A // C->D // B->C // A->B parameter LAST_BANK = "FALSE", parameter USE_PRE_POST_FIFO = "FALSE", parameter RCLK_SELECT_LANE = "B", parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PO_FINE_DELAY = 0, parameter PI_SEL_CLK_OFFSET = 0, // phy_control paramter used in other paramsters parameter PC_CLK_RATIO = 4, //phaser_in parameters parameter A_PI_FREQ_REF_DIV = "NONE", parameter A_PI_CLKOUT_DIV = 2, parameter A_PI_BURST_MODE = "TRUE", parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter A_PI_FINE_DELAY = 60, parameter A_PI_SYNC_IN_DIV_RST = "TRUE", parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter B_PI_BURST_MODE = A_PI_BURST_MODE, parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter C_PI_BURST_MODE = A_PI_BURST_MODE, parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter C_PI_FINE_DELAY = 0, parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter D_PI_BURST_MODE = A_PI_BURST_MODE, parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter D_PI_FINE_DELAY = 0, parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, //phaser_out parameters parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, parameter A_PO_FINE_DELAY = PO_FINE_DELAY, parameter A_PO_COARSE_DELAY = 0, parameter A_PO_OCLK_DELAY = 0, parameter A_PO_OCLKDELAY_INV = "FALSE", parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter A_PO_SYNC_IN_DIV_RST = "TRUE", //parameter A_PO_SYNC_IN_DIV_RST = "FALSE", parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, parameter B_PO_FINE_DELAY = PO_FINE_DELAY, parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, parameter C_PO_FINE_DELAY = PO_FINE_DELAY, parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, parameter D_PO_FINE_DELAY = PO_FINE_DELAY, parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter A_IDELAYE2_IDELAY_VALUE = 00, parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, // phy_control parameters parameter PC_BURST_MODE = "TRUE", parameter PC_DATA_CTL_N = DATA_CTL_N, parameter PC_CMD_OFFSET = 0, parameter PC_RD_CMD_OFFSET_0 = 0, parameter PC_RD_CMD_OFFSET_1 = 0, parameter PC_RD_CMD_OFFSET_2 = 0, parameter PC_RD_CMD_OFFSET_3 = 0, parameter PC_CO_DURATION = 1, parameter PC_DI_DURATION = 1, parameter PC_DO_DURATION = 1, parameter PC_RD_DURATION_0 = 0, parameter PC_RD_DURATION_1 = 0, parameter PC_RD_DURATION_2 = 0, parameter PC_RD_DURATION_3 = 0, parameter PC_WR_CMD_OFFSET_0 = 5, parameter PC_WR_CMD_OFFSET_1 = 5, parameter PC_WR_CMD_OFFSET_2 = 5, parameter PC_WR_CMD_OFFSET_3 = 5, parameter PC_WR_DURATION_0 = 6, parameter PC_WR_DURATION_1 = 6, parameter PC_WR_DURATION_2 = 6, parameter PC_WR_DURATION_3 = 6, parameter PC_AO_WRLVL_EN = 0, parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PC_FOUR_WINDOW_CLOCKS = 63, parameter PC_EVENTS_DELAY = 18, parameter PC_PHY_COUNT_EN = "TRUE", parameter PC_SYNC_MODE = "TRUE", parameter PC_DISABLE_SEQ_MATCH = "TRUE", parameter PC_MULTI_REGION = "FALSE", // io fifo parameters parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_OUTPUT_DISABLE = "TRUE", parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, parameter A_OS_DATA_RATE = "DDR", parameter A_OS_DATA_WIDTH = 4, parameter B_OS_DATA_RATE = A_OS_DATA_RATE, parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter C_OS_DATA_RATE = A_OS_DATA_RATE, parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter D_OS_DATA_RATE = A_OS_DATA_RATE, parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, // this is used locally, not for external pushdown // NOTE: the 0+ is needed in each to coerce to integer for addition. // otherwise 4x 1'b values are added producing a 1'b value. parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, // assume odt per rank + any declared cke's parameter AUXOUT_WIDTH = 4, parameter LP_DDR_CK_WIDTH = 2 ,parameter CKE_ODT_AUX = "FALSE" ,parameter PI_DIV2_INCDEC = "FALSE" ) ( //`include "phy.vh" input rst, input phy_clk, input clk_div2, input phy_ctl_clk, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input phy_ctl_mstr_empty, input [31:0] phy_ctl_wd, input [`PC_DATA_OFFSET_RANGE] data_offset, input phy_ctl_wr, input if_empty_def, input phyGo, input input_sink, output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory output rclk, output if_a_empty, output if_empty, output byte_rd_en, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus output phy_ctl_empty, output phy_ctl_a_full, output phy_ctl_full, output [HIGHEST_LANE*12-1:0]mem_dq_out, output [HIGHEST_LANE*12-1:0]mem_dq_ts, input [HIGHEST_LANE*10-1:0]mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, input [1:0] byte_rd_en_oth_banks, output [AUXOUT_WIDTH-1:0] aux_out, output reg rst_out = 0, output reg mcGo=0, output phy_ctl_ready, output ref_dll_lock, input if_rst, input phy_read_calib, input phy_write_calib, input idelay_inc, input idelay_ce, input idelay_ld, input [2:0] calib_sel, input calib_zero_ctrl, input [HIGHEST_LANE-1:0] calib_zero_lanes, input calib_in_common, input po_fine_enable, input po_coarse_enable, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [8:0] po_counter_load_val, input po_sel_fine_oclk_delay, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, output reg pi_phase_locked, output pi_phase_locked_all, input [29:0] fine_delay, input fine_delay_sel ); localparam DATA_CTL_A = (~DATA_CTL_N[0]); localparam DATA_CTL_B = (~DATA_CTL_N[1]); localparam DATA_CTL_C = (~DATA_CTL_N[2]); localparam DATA_CTL_D = (~DATA_CTL_N[3]); localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam IO_A_START = 41; localparam IO_A_END = 40; localparam IO_B_START = 43; localparam IO_B_END = 42; localparam IO_C_START = 45; localparam IO_C_END = 44; localparam IO_D_START = 47; localparam IO_D_END = 46; localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; localparam IO_A_X_END = (IO_A_X_START-1); localparam IO_B_X_START = (IO_A_X_START + 2); localparam IO_B_X_END = (IO_B_X_START -1); localparam IO_C_X_START = (IO_B_X_START + 2); localparam IO_C_X_END = (IO_C_X_START -1); localparam IO_D_X_START = (IO_C_X_START + 2); localparam IO_D_X_END = (IO_D_X_START -1); localparam MSB_BURST_PEND_PO = 3; localparam MSB_BURST_PEND_PI = 7; localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; wire [7:0] in_rank; wire [11:0] IO_A; wire [11:0] IO_B; wire [11:0] IO_C; wire [11:0] IO_D; wire [319:0] phy_din_remap; reg A_po_counter_read_en; wire [8:0] A_po_counter_read_val; reg A_pi_counter_read_en; wire [5:0] A_pi_counter_read_val; wire A_pi_fine_overflow; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_pi_dqs_found; wire A_pi_dqs_out_of_range; wire A_pi_phase_locked; wire A_pi_iserdes_rst; reg A_pi_fine_enable; reg A_pi_fine_inc; reg A_pi_counter_load_en; reg [5:0] A_pi_counter_load_val; reg A_pi_rst_dqs_find; reg A_po_fine_enable; reg A_po_coarse_enable; reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; reg A_po_sel_fine_oclk_delay; reg A_po_coarse_inc; reg A_po_counter_load_en; reg [8:0] A_po_counter_load_val; wire A_rclk; reg A_idelay_ce; reg A_idelay_ld; reg [29:0] A_fine_delay; reg A_fine_delay_sel; reg B_po_counter_read_en; wire [8:0] B_po_counter_read_val; reg B_pi_counter_read_en; wire [5:0] B_pi_counter_read_val; wire B_pi_fine_overflow; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire B_pi_phase_locked; wire B_pi_iserdes_rst; wire B_pi_dqs_found; wire B_pi_dqs_out_of_range; reg B_pi_fine_enable; reg B_pi_fine_inc; reg B_pi_counter_load_en; reg [5:0] B_pi_counter_load_val; reg B_pi_rst_dqs_find; reg B_po_fine_enable; reg B_po_coarse_enable; reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; reg B_po_coarse_inc; reg B_po_sel_fine_oclk_delay; reg B_po_counter_load_en; reg [8:0] B_po_counter_load_val; wire B_rclk; reg B_idelay_ce; reg B_idelay_ld; reg [29:0] B_fine_delay; reg B_fine_delay_sel; reg C_pi_fine_inc; reg D_pi_fine_inc; reg C_pi_fine_enable; reg D_pi_fine_enable; reg C_po_counter_load_en; reg D_po_counter_load_en; reg C_po_coarse_inc; reg D_po_coarse_inc; reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; reg C_po_sel_fine_oclk_delay; reg D_po_sel_fine_oclk_delay; reg [5:0] C_pi_counter_load_val; reg [5:0] D_pi_counter_load_val; reg [8:0] C_po_counter_load_val; reg [8:0] D_po_counter_load_val; reg C_po_coarse_enable; reg D_po_coarse_enable; reg C_po_fine_enable; reg D_po_fine_enable; wire C_po_coarse_overflow; wire D_po_coarse_overflow; wire C_po_fine_overflow; wire D_po_fine_overflow; wire [8:0] C_po_counter_read_val; wire [8:0] D_po_counter_read_val; reg C_po_counter_read_en; reg D_po_counter_read_en; wire C_pi_dqs_found; wire D_pi_dqs_found; wire C_pi_fine_overflow; wire D_pi_fine_overflow; reg C_pi_counter_read_en; reg D_pi_counter_read_en; reg C_pi_counter_load_en; reg D_pi_counter_load_en; wire C_pi_phase_locked; wire C_pi_iserdes_rst; wire D_pi_phase_locked; wire D_pi_iserdes_rst; wire C_pi_dqs_out_of_range; wire D_pi_dqs_out_of_range; wire [5:0] C_pi_counter_read_val; wire [5:0] D_pi_counter_read_val; wire C_rclk; wire D_rclk; reg C_idelay_ce; reg D_idelay_ce; reg C_idelay_ld; reg D_idelay_ld; reg C_pi_rst_dqs_find; reg D_pi_rst_dqs_find; reg [29:0] C_fine_delay; reg [29:0] D_fine_delay; reg C_fine_delay_sel; reg D_fine_delay_sel; wire pi_iserdes_rst; wire A_if_empty; wire B_if_empty; wire C_if_empty; wire D_if_empty; wire A_byte_rd_en; wire B_byte_rd_en; wire C_byte_rd_en; wire D_byte_rd_en; wire A_if_a_empty; wire B_if_a_empty; wire C_if_a_empty; wire D_if_a_empty; //wire A_if_full; //wire B_if_full; //wire C_if_full; //wire D_if_full; //wire A_of_empty; //wire B_of_empty; //wire C_of_empty; //wire D_of_empty; wire A_of_full; wire B_of_full; wire C_of_full; wire D_of_full; wire A_of_ctl_full; wire B_of_ctl_full; wire C_of_ctl_full; wire D_of_ctl_full; wire A_of_data_full; wire B_of_data_full; wire C_of_data_full; wire D_of_data_full; wire A_of_a_full; wire B_of_a_full; wire C_of_a_full; wire D_of_a_full; wire A_pre_fifo_a_full; wire B_pre_fifo_a_full; wire C_pre_fifo_a_full; wire D_pre_fifo_a_full; wire A_of_ctl_a_full; wire B_of_ctl_a_full; wire C_of_ctl_a_full; wire D_of_ctl_a_full; wire A_of_data_a_full; wire B_of_data_a_full; wire C_of_data_a_full; wire D_of_data_a_full; wire A_pre_data_a_full; wire B_pre_data_a_full; wire C_pre_data_a_full; wire D_pre_data_a_full; wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // wire [3:0] dummy_data; wire [31:0] _phy_ctl_wd; wire [1:0] phy_encalib; assign pi_dqs_found_all = (! PRESENT_DATA_A | A_pi_dqs_found) & (! PRESENT_DATA_B | B_pi_dqs_found) & (! PRESENT_DATA_C | C_pi_dqs_found) & (! PRESENT_DATA_D | D_pi_dqs_found) ; assign pi_dqs_found_any = ( PRESENT_DATA_A & A_pi_dqs_found) | ( PRESENT_DATA_B & B_pi_dqs_found) | ( PRESENT_DATA_C & C_pi_dqs_found) | ( PRESENT_DATA_D & D_pi_dqs_found) ; assign pi_phase_locked_all = (! PRESENT_DATA_A | A_pi_phase_locked) & (! PRESENT_DATA_B | B_pi_phase_locked) & (! PRESENT_DATA_C | C_pi_phase_locked) & (! PRESENT_DATA_D | D_pi_phase_locked); wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal // which is combined into another signals such that // the other signal isn't changed. The purpose // is to fake the tools into ignoring dangling inputs. // Because it is anded with 1'b0, the contributing signals // are folded as constants or trimmed. assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; //assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; //assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; function [79:0] part_select_80; input [319:0] vector; input [1:0] select; begin case (select) 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; endcase end endfunction wire [319:0] phy_dout_remap; reg rst_out_trig = 1'b0; reg [31:0] rclk_delay; reg rst_edge1 = 1'b0; reg rst_edge2 = 1'b0; reg rst_edge3 = 1'b0; reg rst_edge_detect = 1'b0; wire rclk_; reg rst_out_start = 1'b0 ; reg rst_primitives=0; reg A_rst_primitives=0; reg B_rst_primitives=0; reg C_rst_primitives=0; reg D_rst_primitives=0; `ifdef USE_PHY_CONTROL_TEST wire [15:0] test_output; wire [15:0] test_input; wire [2:0] test_select=0; wire scan_enable = 0; `endif generate genvar i; if (RCLK_SELECT_LANE == "A") begin assign rclk_ = A_rclk; assign pi_iserdes_rst = A_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "B") begin assign rclk_ = B_rclk; assign pi_iserdes_rst = B_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "C") begin assign rclk_ = C_rclk; assign pi_iserdes_rst = C_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "D") begin assign rclk_ = D_rclk; assign pi_iserdes_rst = D_pi_iserdes_rst; end else begin assign rclk_ = B_rclk; // default end endgenerate assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; assign pi_phase_locked_lanes = {(! PRESENT_DATA_D[0] | D_pi_phase_locked), (! PRESENT_DATA_C[0] | C_pi_phase_locked) , (! PRESENT_DATA_B[0] | B_pi_phase_locked) , (! PRESENT_DATA_A[0] | A_pi_phase_locked)}; assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; // this block scrubs X from rclk_delay[11] reg rclk_delay_11; always @(rclk_delay[11]) begin : rclk_delay_11_blk if ( rclk_delay[11]) rclk_delay_11 = 1; else rclk_delay_11 = 0; end always @(posedge phy_clk or posedge rst ) begin // scrub 4-state values from rclk_delay[11] if ( rst) begin rst_out <= #1 0; end else begin if ( rclk_delay_11) rst_out <= #1 1; end end always @(posedge phy_clk ) begin // phy_ctl_ready drives reset of the system rst_primitives <= !phy_ctl_ready ; A_rst_primitives <= rst_primitives ; B_rst_primitives <= rst_primitives ; C_rst_primitives <= rst_primitives ; D_rst_primitives <= rst_primitives ; rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); mcGo <= #1 rst_out ; end //reset synchronized to clk_div2 (* ASYNC_REG = "TRUE" *) reg A_pi_rst_div2; (* ASYNC_REG = "TRUE" *) reg B_pi_rst_div2; (* ASYNC_REG = "TRUE" *) reg C_pi_rst_div2; (* ASYNC_REG = "TRUE" *) reg D_pi_rst_div2; generate if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2 (* ASYNC_REG = "TRUE" *) reg pi_rst_div2r1; (* ASYNC_REG = "TRUE" *) reg pi_rst_div2r2; always @(posedge clk_div2) begin pi_rst_div2r1 <= rst_primitives; pi_rst_div2r2 <= pi_rst_div2r1; A_pi_rst_div2 <= pi_rst_div2r2; B_pi_rst_div2 <= pi_rst_div2r2; C_pi_rst_div2 <= pi_rst_div2r2; D_pi_rst_div2 <= pi_rst_div2r2; end end else begin: phaser_in_div4 always @ (*) begin A_pi_rst_div2 <= 1'b0; B_pi_rst_div2 <= 1'b0; C_pi_rst_div2 <= 1'b0; D_pi_rst_div2 <= 1'b0; end end endgenerate generate if (BYTE_LANES[0]) begin assign dummy_data[0] = 0; end else begin assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; end if (BYTE_LANES[1]) begin assign dummy_data[1] = 0; end else begin assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; end if (BYTE_LANES[2]) begin assign dummy_data[2] = 0; end else begin assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; end if (BYTE_LANES[3]) begin assign dummy_data[3] = 0; end else begin assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; end if (PRESENT_DATA_A) begin assign A_of_data_full = A_of_full; assign A_of_ctl_full = 0; assign A_of_data_a_full = A_of_a_full; assign A_of_ctl_a_full = 0; assign A_pre_data_a_full = A_pre_fifo_a_full; end else begin assign A_of_ctl_full = A_of_full; assign A_of_data_full = 0; assign A_of_ctl_a_full = A_of_a_full; assign A_of_data_a_full = 0; assign A_pre_data_a_full = 0; end if (PRESENT_DATA_B) begin assign B_of_data_full = B_of_full; assign B_of_ctl_full = 0; assign B_of_data_a_full = B_of_a_full; assign B_of_ctl_a_full = 0; assign B_pre_data_a_full = B_pre_fifo_a_full; end else begin assign B_of_ctl_full = B_of_full; assign B_of_data_full = 0; assign B_of_ctl_a_full = B_of_a_full; assign B_of_data_a_full = 0; assign B_pre_data_a_full = 0; end if (PRESENT_DATA_C) begin assign C_of_data_full = C_of_full; assign C_of_ctl_full = 0; assign C_of_data_a_full = C_of_a_full; assign C_of_ctl_a_full = 0; assign C_pre_data_a_full = C_pre_fifo_a_full; end else begin assign C_of_ctl_full = C_of_full; assign C_of_data_full = 0; assign C_of_ctl_a_full = C_of_a_full; assign C_of_data_a_full = 0; assign C_pre_data_a_full = 0; end if (PRESENT_DATA_D) begin assign D_of_data_full = D_of_full; assign D_of_ctl_full = 0; assign D_of_data_a_full = D_of_a_full; assign D_of_ctl_a_full = 0; assign D_pre_data_a_full = D_pre_fifo_a_full; end else begin assign D_of_ctl_full = D_of_full; assign D_of_data_full = 0; assign D_of_ctl_a_full = D_of_a_full; assign D_of_data_a_full = 0; assign D_pre_data_a_full = 0; end // byte lane must exist and be data lane. if (PRESENT_DATA_A ) case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; endcase else case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_B ) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; endcase else if (HIGHEST_LANE > 1) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_C) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; endcase else if (HIGHEST_LANE > 2) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_D ) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; endcase else if (HIGHEST_LANE > 3) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (HIGHEST_LANE > 1) assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; if (HIGHEST_LANE == 1) assign _phy_ctl_wd = phy_ctl_wd; //BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); BUFIO rclk_buf(.I(rclk_), .O(rclk) ); if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); mig_7series_v4_0_ddr_byte_lane # ( .ABCD ("A"), .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[11:0]), .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (A_PI_BURST_MODE), .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), .PI_FINE_DELAY (A_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), .PO_FINE_DELAY (A_PO_FINE_DELAY), .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), .PO_COARSE_DELAY (A_PO_COARSE_DELAY), .PO_OCLK_DELAY (A_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (A_OS_DATA_RATE), .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) ddr_byte_lane_A( .mem_dq_out (mem_dq_out[11:0]), .mem_dq_ts (mem_dq_ts[11:0]), .mem_dq_in (mem_dq_in[9:0]), .mem_dqs_out (mem_dqs_out[0]), .mem_dqs_ts (mem_dqs_ts[0]), .mem_dqs_in (mem_dqs_in[0]), .rst (A_rst_primitives), .rst_pi_div2 (A_pi_rst_div2), .phy_clk (phy_clk), .clk_div2 (clk_div2), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (A_ddr_clk), .rclk (A_rclk), .pi_dqs_found (A_pi_dqs_found), .dqs_out_of_range (A_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (A_if_a_empty), .if_empty (A_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*A_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*A_of_empty*/), .of_a_full (A_of_a_full), .of_full (A_of_full), .pre_fifo_a_full (A_pre_fifo_a_full), .phy_din (phy_din_remap[79:0]), .phy_dout (phy_dout_remap[79:0]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (A_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (A_idelay_ce), .idelay_ld (A_idelay_ld), .pi_rst_dqs_find (A_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (A_po_fine_enable), .po_coarse_enable (A_po_coarse_enable), .po_fine_inc (A_po_fine_inc), .po_coarse_inc (A_po_coarse_inc), .po_counter_load_en (A_po_counter_load_en), .po_counter_read_en (A_po_counter_read_en), .po_counter_load_val (A_po_counter_load_val), .po_coarse_overflow (A_po_coarse_overflow), .po_fine_overflow (A_po_fine_overflow), .po_counter_read_val (A_po_counter_read_val), .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (A_pi_fine_enable), .pi_fine_inc (A_pi_fine_inc), .pi_counter_load_en (A_pi_counter_load_en), .pi_counter_read_en (A_pi_counter_read_en), .pi_counter_load_val (A_pi_counter_load_val), .pi_fine_overflow (A_pi_fine_overflow), .pi_counter_read_val (A_pi_counter_read_val), .pi_iserdes_rst (A_pi_iserdes_rst), .pi_phase_locked (A_pi_phase_locked), .fine_delay (A_fine_delay), .fine_delay_sel (A_fine_delay_sel) ); end else begin : no_ddr_byte_lane_A assign A_of_a_full = 1'b0; assign A_of_full = 1'b0; assign A_pre_fifo_a_full = 1'b0; assign A_if_empty = 1'b0; assign A_byte_rd_en = 1'b1; assign A_if_a_empty = 1'b0; assign A_pi_phase_locked = 1; assign A_pi_dqs_found = 1; assign A_rclk = 0; assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign A_pi_counter_read_val = 0; assign A_po_counter_read_val = 0; assign A_pi_fine_overflow = 0; assign A_po_coarse_overflow = 0; assign A_po_fine_overflow = 0; end if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); mig_7series_v4_0_ddr_byte_lane # ( .ABCD ("B"), .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[23:12]), .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (B_PI_BURST_MODE), .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), .PI_FINE_DELAY (B_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), .PO_FINE_DELAY (B_PO_FINE_DELAY), .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), .PO_COARSE_DELAY (B_PO_COARSE_DELAY), .PO_OCLK_DELAY (B_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (B_OS_DATA_RATE), .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) ddr_byte_lane_B( .mem_dq_out (mem_dq_out[23:12]), .mem_dq_ts (mem_dq_ts[23:12]), .mem_dq_in (mem_dq_in[19:10]), .mem_dqs_out (mem_dqs_out[1]), .mem_dqs_ts (mem_dqs_ts[1]), .mem_dqs_in (mem_dqs_in[1]), .rst (B_rst_primitives), .rst_pi_div2 (B_pi_rst_div2), .phy_clk (phy_clk), .clk_div2 (clk_div2), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (B_ddr_clk), .rclk (B_rclk), .pi_dqs_found (B_pi_dqs_found), .dqs_out_of_range (B_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (B_if_a_empty), .if_empty (B_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*B_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*B_of_empty*/), .of_a_full (B_of_a_full), .of_full (B_of_full), .pre_fifo_a_full (B_pre_fifo_a_full), .phy_din (phy_din_remap[159:80]), .phy_dout (phy_dout_remap[159:80]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (B_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (B_idelay_ce), .idelay_ld (B_idelay_ld), .pi_rst_dqs_find (B_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (B_po_fine_enable), .po_coarse_enable (B_po_coarse_enable), .po_fine_inc (B_po_fine_inc), .po_coarse_inc (B_po_coarse_inc), .po_counter_load_en (B_po_counter_load_en), .po_counter_read_en (B_po_counter_read_en), .po_counter_load_val (B_po_counter_load_val), .po_coarse_overflow (B_po_coarse_overflow), .po_fine_overflow (B_po_fine_overflow), .po_counter_read_val (B_po_counter_read_val), .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (B_pi_fine_enable), .pi_fine_inc (B_pi_fine_inc), .pi_counter_load_en (B_pi_counter_load_en), .pi_counter_read_en (B_pi_counter_read_en), .pi_counter_load_val (B_pi_counter_load_val), .pi_fine_overflow (B_pi_fine_overflow), .pi_counter_read_val (B_pi_counter_read_val), .pi_iserdes_rst (B_pi_iserdes_rst), .pi_phase_locked (B_pi_phase_locked), .fine_delay (B_fine_delay), .fine_delay_sel (B_fine_delay_sel) ); end else begin : no_ddr_byte_lane_B assign B_of_a_full = 1'b0; assign B_of_full = 1'b0; assign B_pre_fifo_a_full = 1'b0; assign B_if_empty = 1'b0; assign B_if_a_empty = 1'b0; assign B_byte_rd_en = 1'b1; assign B_pi_phase_locked = 1; assign B_pi_dqs_found = 1; assign B_rclk = 0; assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign B_pi_counter_read_val = 0; assign B_po_counter_read_val = 0; assign B_pi_fine_overflow = 0; assign B_po_coarse_overflow = 0; assign B_po_fine_overflow = 0; end if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); mig_7series_v4_0_ddr_byte_lane # ( .ABCD ("C"), .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[35:24]), .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (C_PI_BURST_MODE), .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), .PI_FINE_DELAY (C_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), .PO_FINE_DELAY (C_PO_FINE_DELAY), .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), .PO_COARSE_DELAY (C_PO_COARSE_DELAY), .PO_OCLK_DELAY (C_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (C_OS_DATA_RATE), .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) ddr_byte_lane_C( .mem_dq_out (mem_dq_out[35:24]), .mem_dq_ts (mem_dq_ts[35:24]), .mem_dq_in (mem_dq_in[29:20]), .mem_dqs_out (mem_dqs_out[2]), .mem_dqs_ts (mem_dqs_ts[2]), .mem_dqs_in (mem_dqs_in[2]), .rst (C_rst_primitives), .rst_pi_div2 (C_pi_rst_div2), .phy_clk (phy_clk), .clk_div2 (clk_div2), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (C_ddr_clk), .rclk (C_rclk), .pi_dqs_found (C_pi_dqs_found), .dqs_out_of_range (C_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (C_if_a_empty), .if_empty (C_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*C_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*C_of_empty*/), .of_a_full (C_of_a_full), .of_full (C_of_full), .pre_fifo_a_full (C_pre_fifo_a_full), .phy_din (phy_din_remap[239:160]), .phy_dout (phy_dout_remap[239:160]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (C_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (C_idelay_ce), .idelay_ld (C_idelay_ld), .pi_rst_dqs_find (C_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (C_po_fine_enable), .po_coarse_enable (C_po_coarse_enable), .po_fine_inc (C_po_fine_inc), .po_coarse_inc (C_po_coarse_inc), .po_counter_load_en (C_po_counter_load_en), .po_counter_read_en (C_po_counter_read_en), .po_counter_load_val (C_po_counter_load_val), .po_coarse_overflow (C_po_coarse_overflow), .po_fine_overflow (C_po_fine_overflow), .po_counter_read_val (C_po_counter_read_val), .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (C_pi_fine_enable), .pi_fine_inc (C_pi_fine_inc), .pi_counter_load_en (C_pi_counter_load_en), .pi_counter_read_en (C_pi_counter_read_en), .pi_counter_load_val (C_pi_counter_load_val), .pi_fine_overflow (C_pi_fine_overflow), .pi_counter_read_val (C_pi_counter_read_val), .pi_iserdes_rst (C_pi_iserdes_rst), .pi_phase_locked (C_pi_phase_locked), .fine_delay (C_fine_delay), .fine_delay_sel (C_fine_delay_sel) ); end else begin : no_ddr_byte_lane_C assign C_of_a_full = 1'b0; assign C_of_full = 1'b0; assign C_pre_fifo_a_full = 1'b0; assign C_if_empty = 1'b0; assign C_byte_rd_en = 1'b1; assign C_if_a_empty = 1'b0; assign C_pi_phase_locked = 1; assign C_pi_dqs_found = 1; assign C_rclk = 0; assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign C_pi_counter_read_val = 0; assign C_po_counter_read_val = 0; assign C_pi_fine_overflow = 0; assign C_po_coarse_overflow = 0; assign C_po_fine_overflow = 0; end if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); mig_7series_v4_0_ddr_byte_lane # ( .ABCD ("D"), .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[47:36]), .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (D_PI_BURST_MODE), .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), .PI_FINE_DELAY (D_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), .PO_FINE_DELAY (D_PO_FINE_DELAY), .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), .PO_COARSE_DELAY (D_PO_COARSE_DELAY), .PO_OCLK_DELAY (D_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (D_OS_DATA_RATE), .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) ddr_byte_lane_D( .mem_dq_out (mem_dq_out[47:36]), .mem_dq_ts (mem_dq_ts[47:36]), .mem_dq_in (mem_dq_in[39:30]), .mem_dqs_out (mem_dqs_out[3]), .mem_dqs_ts (mem_dqs_ts[3]), .mem_dqs_in (mem_dqs_in[3]), .rst (D_rst_primitives), .rst_pi_div2 (D_pi_rst_div2), .phy_clk (phy_clk), .clk_div2 (clk_div2), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (D_ddr_clk), .rclk (D_rclk), .pi_dqs_found (D_pi_dqs_found), .dqs_out_of_range (D_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (D_if_a_empty), .if_empty (D_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*D_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*D_of_empty*/), .of_a_full (D_of_a_full), .of_full (D_of_full), .pre_fifo_a_full (D_pre_fifo_a_full), .phy_din (phy_din_remap[319:240]), .phy_dout (phy_dout_remap[319:240]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .idelay_inc (idelay_inc), .idelay_ce (D_idelay_ce), .idelay_ld (D_idelay_ld), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (D_byte_rd_en), // calibration signals .pi_rst_dqs_find (D_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (D_po_fine_enable), .po_coarse_enable (D_po_coarse_enable), .po_fine_inc (D_po_fine_inc), .po_coarse_inc (D_po_coarse_inc), .po_counter_load_en (D_po_counter_load_en), .po_counter_read_en (D_po_counter_read_en), .po_counter_load_val (D_po_counter_load_val), .po_coarse_overflow (D_po_coarse_overflow), .po_fine_overflow (D_po_fine_overflow), .po_counter_read_val (D_po_counter_read_val), .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (D_pi_fine_enable), .pi_fine_inc (D_pi_fine_inc), .pi_counter_load_en (D_pi_counter_load_en), .pi_counter_read_en (D_pi_counter_read_en), .pi_counter_load_val (D_pi_counter_load_val), .pi_fine_overflow (D_pi_fine_overflow), .pi_counter_read_val (D_pi_counter_read_val), .pi_iserdes_rst (D_pi_iserdes_rst), .pi_phase_locked (D_pi_phase_locked), .fine_delay (D_fine_delay), .fine_delay_sel (D_fine_delay_sel) ); end else begin : no_ddr_byte_lane_D assign D_of_a_full = 1'b0; assign D_of_full = 1'b0; assign D_pre_fifo_a_full = 1'b0; assign D_if_empty = 1'b0; assign D_byte_rd_en = 1'b1; assign D_if_a_empty = 1'b0; assign D_rclk = 0; assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign D_pi_dqs_found = 1; assign D_pi_phase_locked = 1; assign D_pi_counter_read_val = 0; assign D_po_counter_read_val = 0; assign D_pi_fine_overflow = 0; assign D_po_coarse_overflow = 0; assign D_po_fine_overflow = 0; end endgenerate assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; PHY_CONTROL #( .AO_WRLVL_EN ( PC_AO_WRLVL_EN), .AO_TOGGLE ( PC_AO_TOGGLE), .BURST_MODE ( PC_BURST_MODE), .CO_DURATION ( PC_CO_DURATION ), .CLK_RATIO ( PC_CLK_RATIO), .DATA_CTL_A_N ( PC_DATA_CTL_A), .DATA_CTL_B_N ( PC_DATA_CTL_B), .DATA_CTL_C_N ( PC_DATA_CTL_C), .DATA_CTL_D_N ( PC_DATA_CTL_D), .DI_DURATION ( PC_DI_DURATION ), .DO_DURATION ( PC_DO_DURATION ), .EVENTS_DELAY ( PC_EVENTS_DELAY), .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), .MULTI_REGION ( PC_MULTI_REGION ), .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), .SYNC_MODE ( PC_SYNC_MODE), .CMD_OFFSET ( PC_CMD_OFFSET), .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), .RD_DURATION_0 ( PC_RD_DURATION_0), .RD_DURATION_1 ( PC_RD_DURATION_1), .RD_DURATION_2 ( PC_RD_DURATION_2), .RD_DURATION_3 ( PC_RD_DURATION_3), .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), .WR_DURATION_0 ( PC_WR_DURATION_0), .WR_DURATION_1 ( PC_WR_DURATION_1), .WR_DURATION_2 ( PC_WR_DURATION_2), .WR_DURATION_3 ( PC_WR_DURATION_3) ) phy_control_i ( .AUXOUTPUT (aux_out), .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), .INRANKA (in_rank[1:0]), .INRANKB (in_rank[3:2]), .INRANKC (in_rank[5:4]), .INRANKD (in_rank[7:6]), .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), .PCENABLECALIB (phy_encalib), .PHYCTLALMOSTFULL (phy_ctl_a_full), .PHYCTLEMPTY (phy_ctl_empty), .PHYCTLFULL (phy_ctl_full), .PHYCTLREADY (phy_ctl_ready), .MEMREFCLK (mem_refclk), .PHYCLK (phy_ctl_clk), .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), .PHYCTLWD (_phy_ctl_wd), .PHYCTLWRENABLE (phy_ctl_wr), .PLLLOCK (pll_lock), .REFDLLLOCK (ref_dll_lock), // is reset while !locked .RESET (rst), .SYNCIN (sync_pulse), .READCALIBENABLE (phy_read_calib), .WRITECALIBENABLE (phy_write_calib) `ifdef USE_PHY_CONTROL_TEST , .TESTINPUT (16'b0), .TESTOUTPUT (test_output), .TESTSELECT (test_select), .SCANENABLEN (scan_enable) `endif ); // register outputs to give extra slack in timing always @(posedge phy_clk ) begin case (calib_sel[1:0]) 2'h0: begin po_coarse_overflow <= #1 A_po_coarse_overflow; po_fine_overflow <= #1 A_po_fine_overflow; po_counter_read_val <= #1 A_po_counter_read_val; pi_fine_overflow <= #1 A_pi_fine_overflow; pi_counter_read_val<= #1 A_pi_counter_read_val; pi_phase_locked <= #1 A_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 A_pi_dqs_found; pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; end 2'h1: begin po_coarse_overflow <= #1 B_po_coarse_overflow; po_fine_overflow <= #1 B_po_fine_overflow; po_counter_read_val <= #1 B_po_counter_read_val; pi_fine_overflow <= #1 B_pi_fine_overflow; pi_counter_read_val <= #1 B_pi_counter_read_val; pi_phase_locked <= #1 B_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 B_pi_dqs_found; pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; end 2'h2: begin po_coarse_overflow <= #1 C_po_coarse_overflow; po_fine_overflow <= #1 C_po_fine_overflow; po_counter_read_val <= #1 C_po_counter_read_val; pi_fine_overflow <= #1 C_pi_fine_overflow; pi_counter_read_val <= #1 C_pi_counter_read_val; pi_phase_locked <= #1 C_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 C_pi_dqs_found; pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; end 2'h3: begin po_coarse_overflow <= #1 D_po_coarse_overflow; po_fine_overflow <= #1 D_po_fine_overflow; po_counter_read_val <= #1 D_po_counter_read_val; pi_fine_overflow <= #1 D_pi_fine_overflow; pi_counter_read_val <= #1 D_pi_counter_read_val; pi_phase_locked <= #1 D_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 D_pi_dqs_found; pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; end default: begin po_coarse_overflow <= po_coarse_overflow; end endcase end wire B_mux_ctrl; wire C_mux_ctrl; wire D_mux_ctrl; generate if (HIGHEST_LANE > 1) assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); else assign B_mux_ctrl = 0; if (HIGHEST_LANE > 2) assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); else assign C_mux_ctrl = 0; if (HIGHEST_LANE > 3) assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); else assign D_mux_ctrl = 0; endgenerate always @(*) begin A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; if ( calib_sel[2]) begin // if this is asserted, all calib signals are deasserted A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; end else if (calib_in_common) begin // if this is asserted, each signal is broadcast to all phasers // in common if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end if ( B_mux_ctrl) begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end if ( C_mux_ctrl) begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end if ( D_mux_ctrl) begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_read_en = po_counter_read_en; D_po_counter_load_val = po_counter_load_val; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end end else begin // otherwise, only a single phaser is selected case (calib_sel[1:0]) 0: begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end 1: begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end 2: begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end 3: begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_load_val = po_counter_load_val; D_po_counter_read_en = po_counter_read_en; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end endcase end end //obligatory phaser-ref PHASER_REF phaser_ref_i( .LOCKED (ref_dll_lock), .CLKIN (freq_refclk), .PWRDWN (1'b0), .RST ( ! pll_lock) ); // optional idelay_ctrl generate if ( GENERATE_IDELAYCTRL == "TRUE") IDELAYCTRL idelayctrl ( .RDY (/*idelayctrl_rdy*/), .REFCLK (idelayctrl_refclk), .RST (rst) ); endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Shift CK/Address/Commands/Controls //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter DQS_CNT_WIDTH = 3, parameter N_CTL_LANES = 3, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, // Start only after PO_CIRC_BUF_DELAY decremented input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [N_CTL_LANES-1:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_stg2_f_incdec, output reg po_en_stg2_f, output reg po_stg2_c_incdec, output reg po_en_stg2_c, // Completed delaying CK/Address/Commands/Controls output po_ck_addr_cmd_delay_done ); localparam TAP_CNT_LIMIT = 63; //Calculate the tap resolution of the PHASER based on the clock period localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : tCK > 2500 ? 2 : 1); localparam integer PHASER_TAP_RES = ((tCK/2)/64); // Determine whether 300 ps or 350 ps delay required localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; // Determine the number of Phaser_Out taps required to delay by 300 ps // 300 ps is the PCB trace uncertainty between CK and DQS byte groups // Increment control byte lanes localparam TAP_CNT = 0; //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; //Decrement control byte lanes localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; reg delay_dec_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4 /* synthesis syn_maxfan = 10 */; reg [5:0] delay_cnt_r; reg [5:0] delaydec_cnt_r; reg po_cnt_inc; reg po_cnt_dec; reg [3:0] wait_cnt_r; assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; always @(posedge clk) begin if (rst || po_cnt_dec || po_cnt_inc) wait_cnt_r <= #TCQ 'd8; else if (cmd_delay_start && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) po_cnt_inc <= #TCQ 1'b0; else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_inc <= #TCQ 1'b1; else po_cnt_inc <= #TCQ 1'b0; end //Tap decrement always @(posedge clk) begin if (rst || (delaydec_cnt_r == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane //the alignment is started once the always @(posedge clk) begin if (rst) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end else begin if (po_cnt_dec) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b1; end else begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end if (po_cnt_inc) begin po_stg2_c_incdec <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b1; end else begin po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end end end // delay counter to count 2 cycles // Increment coarse taps by 2 for all control byte lanes // to mitigate late writes always @(posedge clk) begin // load delay counter with init value if (rst || (tCK >= 2500) || (SIM_CAL_OPTION == "FAST_CAL")) delay_cnt_r <= #TCQ 'd0; else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delay_cnt_r <= #TCQ 'd1; else if (po_cnt_inc && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; end // delay counter to count TAP_DEC cycles always @(posedge clk) begin // load delay counter with init value of TAP_DEC if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delaydec_cnt_r <= #TCQ TAP_DEC; else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; end //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle //This ensures all ctrl byte lanes have had their output phase shifted. always @(posedge clk) begin if (rst || ~cmd_delay_start ) ctl_lane_cnt <= #TCQ 6'b0; else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) ctl_lane_cnt <= #TCQ ctl_lane_cnt; else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; end // All control lanes have decremented to 31 fine taps from 46 always @(posedge clk) begin if (rst || ~cmd_delay_start) begin delay_dec_done <= #TCQ 1'b0; end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin delay_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin delay_done_r1 <= #TCQ delay_dec_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_dqs_found_cal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling calibration logic // NOTES: // 1. Phaser_In DQSFOUND calibration //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ **$Date: 2011/06/02 08:35:08 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_dqs_found_cal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter nCL = 5, // Read CAS latency parameter AL = "0", parameter nCWL = 5, // Write CAS latency parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter RANKS = 1, // # of memory ranks in the system parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate parameter N_CTL_LANES = 3, // Number of control byte lanes parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) parameter HIGHEST_BANK = 3, // Sum of I/O Banks parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf ) ( input clk, input rst, input dqsfound_retry, // From phy_init input pi_dqs_found_start, input detect_pi_found_dqs, input prech_done, // DQSFOUND per Phaser_IN input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, // To phy_init output [5:0] rd_data_offset_0, output [5:0] rd_data_offset_1, output [5:0] rd_data_offset_2, output pi_dqs_found_rank_done, output pi_dqs_found_done, output reg pi_dqs_found_err, output [6*RANKS-1:0] rd_data_offset_ranks_0, output [6*RANKS-1:0] rd_data_offset_ranks_1, output [6*RANKS-1:0] rd_data_offset_ranks_2, output reg dqsfound_retry_done, output reg dqs_found_prech_req, //To MC output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, input [8:0] po_counter_read_val, output rd_data_offset_cal_done, output fine_adjust_done, output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, output reg ck_po_stg2_f_indec, output reg ck_po_stg2_f_en, output [255:0] dbg_dqs_found_cal ); // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Added to reduce simulation time localparam LATENCY_FACTOR = 13; localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; localparam FINE_ADJ_IDLE = 4'h0; localparam RST_POSTWAIT = 4'h1; localparam RST_POSTWAIT1 = 4'h2; localparam RST_WAIT = 4'h3; localparam FINE_ADJ_INIT = 4'h4; localparam FINE_INC = 4'h5; localparam FINE_INC_WAIT = 4'h6; localparam FINE_INC_PREWAIT = 4'h7; localparam DETECT_PREWAIT = 4'h8; localparam DETECT_DQSFOUND = 4'h9; localparam PRECH_WAIT = 4'hA; localparam FINE_DEC = 4'hB; localparam FINE_DEC_WAIT = 4'hC; localparam FINE_DEC_PREWAIT = 4'hD; localparam FINAL_WAIT = 4'hE; localparam FINE_ADJ_DONE = 4'hF; integer k,l,m,n,p,q,r,s; reg dqs_found_start_r; reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; reg rank_done_r; reg rank_done_r1; reg dqs_found_done_r; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; reg init_dqsfound_done_r; reg init_dqsfound_done_r1; reg init_dqsfound_done_r2; reg init_dqsfound_done_r3; reg init_dqsfound_done_r4; reg init_dqsfound_done_r5; reg [1:0] rnk_cnt_r; reg [2:0 ] final_do_index[0:RANKS-1]; reg [5:0 ] final_do_max[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; reg [10*HIGHEST_BANK-1:0] retry_cnt; reg dqsfound_retry_r1; wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; // CK/Control byte lanes fine adjust stage reg fine_adjust; reg [N_CTL_LANES-1:0] ctl_lane_cnt; reg [3:0] fine_adj_state_r; reg fine_adjust_done_r; reg rst_dqs_find; reg rst_dqs_find_r1; reg rst_dqs_find_r2; reg [5:0] init_dec_cnt; reg [5:0] dec_cnt; reg [5:0] inc_cnt; reg final_dec_done; reg init_dec_done; reg first_fail_detect; reg second_fail_detect; reg [5:0] first_fail_taps; reg [5:0] second_fail_taps; reg [5:0] stable_pass_cnt; reg [3:0] detect_rd_cnt; //*************************************************************************** // Debug signals // //*************************************************************************** assign dbg_dqs_found_cal[5:0] = first_fail_taps; assign dbg_dqs_found_cal[11:6] = second_fail_taps; assign dbg_dqs_found_cal[12] = first_fail_detect; assign dbg_dqs_found_cal[13] = second_fail_detect; assign dbg_dqs_found_cal[14] = fine_adjust_done_r; assign pi_dqs_found_rank_done = rank_done_r; assign pi_dqs_found_done = dqs_found_done_r; generate genvar rnk_cnt; if (HIGHEST_BANK == 3) begin // Three Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; end end else if (HIGHEST_BANK == 2) begin // Two Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end else begin // Single Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end endgenerate // final_data_offset is used during write calibration and during // normal operation. One rd_data_offset value per rank for entire // interface generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : final_data_offset[rnk_cnt_r][12+:6]; end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = 'd0; end else begin assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = 'd0; assign rd_data_offset_2 = 'd0; end endgenerate assign rd_data_offset_cal_done = init_dqsfound_done_r; assign fine_adjust_lane_cnt = ctl_lane_cnt; //************************************************************************** // DQSFOUND all and any generation // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are // asserted // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx // is asserted //************************************************************************** generate if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; endgenerate always @(posedge clk) begin if (rst) begin for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found pi_dqs_found_all_bank[k] <= #TCQ 'b0; pi_dqs_found_any_bank[k] <= #TCQ 'b0; end end else if (pi_dqs_found_start) begin for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); end end end always @(posedge clk) begin pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; end //***************************************************************************** // Counter to increase number of 4 back-to-back reads per rd_data_offset and // per CK/A/C tap value //***************************************************************************** always @(posedge clk) begin if (rst || (detect_rd_cnt == 'd0)) detect_rd_cnt <= #TCQ NUM_READS; else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) detect_rd_cnt <= #TCQ detect_rd_cnt - 1; end //************************************************************************** // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls // //************************************************************************** assign fine_adjust_done = fine_adjust_done_r; always @(posedge clk) begin rst_dqs_find_r1 <= #TCQ rst_dqs_find; rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; end always @(posedge clk) begin if(rst)begin fine_adjust <= #TCQ 1'b0; ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; fine_adjust_done_r <= #TCQ 1'b0; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b0; init_dec_cnt <= #TCQ 'd31; dec_cnt <= #TCQ 'd0; inc_cnt <= #TCQ 'd0; init_dec_done <= #TCQ 1'b0; final_dec_done <= #TCQ 1'b0; first_fail_detect <= #TCQ 1'b0; second_fail_detect <= #TCQ 1'b0; first_fail_taps <= #TCQ 'd0; second_fail_taps <= #TCQ 'd0; stable_pass_cnt <= #TCQ 'd0; dqs_found_prech_req<= #TCQ 1'b0; end else begin case (fine_adj_state_r) FINE_ADJ_IDLE: begin if (init_dqsfound_done_r5) begin if (SIM_CAL_OPTION == "FAST_CAL") begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; rst_dqs_find <= #TCQ 1'b0; end else begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; rst_dqs_find <= #TCQ 1'b1; end end end RST_WAIT: begin if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin rst_dqs_find <= #TCQ 1'b0; if (|init_dec_cnt) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else if (final_dec_done) fine_adj_state_r <= #TCQ FINE_ADJ_DONE; else fine_adj_state_r <= #TCQ RST_POSTWAIT; end end RST_POSTWAIT: begin fine_adj_state_r <= #TCQ RST_POSTWAIT1; end RST_POSTWAIT1: begin fine_adj_state_r <= #TCQ FINE_ADJ_INIT; end FINE_ADJ_INIT: begin //if (detect_pi_found_dqs && (inc_cnt < 'd63)) fine_adj_state_r <= #TCQ FINE_INC; end FINE_INC: begin fine_adj_state_r <= #TCQ FINE_INC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b1; ck_po_stg2_f_en <= #TCQ 1'b1; if (ctl_lane_cnt == N_CTL_LANES-1) inc_cnt <= #TCQ inc_cnt + 1; end FINE_INC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ DETECT_PREWAIT; end end FINE_INC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_INC; end DETECT_PREWAIT: begin if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) fine_adj_state_r <= #TCQ DETECT_DQSFOUND; else fine_adj_state_r <= #TCQ DETECT_PREWAIT; end DETECT_DQSFOUND: begin if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ 'd0; if (~first_fail_detect && (inc_cnt == 'd63)) begin // First failing tap detected at 63 taps // then decrement to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin // First failing tap detected at greater than 30 taps // then stop looking for second edge and decrement first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ (inc_cnt>>1) + 1; end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin // First failing tap detected, continue incrementing // until either second failing tap detected or 63 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin // Consecutive 30 taps of passing region was not found // continue incrementing first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt == 'd63)) begin if (stable_pass_cnt < 'd30) begin // Consecutive 30 taps of passing region was not found // from tap 0 to 63 so decrement back to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else begin // Consecutive 30 taps of passing region was found // between first_fail_taps and 63 fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end else begin // Second failing tap detected, decrement to center of // failing taps second_fail_detect <= #TCQ 1'b1; second_fail_taps <= #TCQ inc_cnt; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); fine_adj_state_r <= #TCQ FINE_DEC; end end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ stable_pass_cnt + 1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else if (inc_cnt < 'd63) begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end else begin fine_adj_state_r <= #TCQ FINE_DEC; if (~first_fail_detect || (first_fail_taps > 'd33)) // No failing taps detected, decrement by 31 dec_cnt <= #TCQ 'd32; //else if (first_fail_detect && (stable_pass_cnt > 'd28)) // // First failing tap detected between 0 and 34 // // decrement midpoint between 63 and failing tap // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); else // First failing tap detected // decrement to midpoint between 63 and failing tap dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end end PRECH_WAIT: begin if (prech_done) begin dqs_found_prech_req <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end end FINE_DEC: begin fine_adj_state_r <= #TCQ FINE_DEC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b1; if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) init_dec_cnt <= #TCQ init_dec_cnt - 1; else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) dec_cnt <= #TCQ dec_cnt - 1; end FINE_DEC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else begin fine_adj_state_r <= #TCQ FINAL_WAIT; if ((init_dec_cnt == 'd0) && ~init_dec_done) init_dec_done <= #TCQ 1'b1; else final_dec_done <= #TCQ 1'b1; end end end FINE_DEC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_DEC; end FINAL_WAIT: begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end FINE_ADJ_DONE: begin if (&pi_dqs_found_all_bank) begin fine_adjust_done_r <= #TCQ 1'b1; rst_dqs_find <= #TCQ 1'b0; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; end end endcase end end //***************************************************************************** always@(posedge clk) dqs_found_start_r <= #TCQ pi_dqs_found_start; always @(posedge clk) begin if (rst) rnk_cnt_r <= #TCQ 2'b00; else if (init_dqsfound_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r; else if (rank_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r + 1; end //***************************************************************** // Read data_offset calibration done signal //***************************************************************** always @(posedge clk) begin if (rst || (|pi_rst_stg1_cal_r)) init_dqsfound_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank) begin if (rnk_cnt_r == RANKS-1) init_dqsfound_done_r <= #TCQ 1'b1; else init_dqsfound_done_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst || (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) rank_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) rank_done_r <= #TCQ 1'b1; else rank_done_r <= #TCQ 1'b0; end always @(posedge clk) begin pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; rank_done_r1 <= #TCQ rank_done_r; dqsfound_retry_r1 <= #TCQ dqsfound_retry; end always @(posedge clk) begin if (rst) dqs_found_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && (fine_adj_state_r == FINE_ADJ_DONE)) dqs_found_done_r <= #TCQ 1'b1; else dqs_found_done_r <= #TCQ 1'b0; end generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[2]) || (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[20+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[2]) retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; else retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[2] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[2] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; end always @(posedge clk) begin if (rst) begin for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && //(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1; end //***************************************************************************** // Two I/O Bank Interface //***************************************************************************** end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; end //***************************************************************************** // One I/O Bank Interface //***************************************************************************** end else begin // One I/O Bank Interface // Read data offset value for all DQS in Bank0 always @(posedge clk) begin if (rst) begin for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r] <= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1; end // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted even with 3 dqfound retries always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end end endgenerate always @(posedge clk) begin if (rst) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; else if (rst_dqs_find) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; else pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; end // Final read data offset value to be used during write calibration and // normal operation generate genvar i; genvar j; for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop reg [5:0] final_do_cand [RANKS-1:0]; // combinatorially select the candidate offset for the bank // indexed by final_do_index if (HIGHEST_BANK == 3) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; default: final_do_cand[i] = 'd0; endcase end end else if (HIGHEST_BANK == 2) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end else begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = 'd0; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end always @(posedge clk) begin if (rst) final_do_max[i] <= #TCQ 0; else begin final_do_max[i] <= #TCQ final_do_max[i]; // default case (final_do_index[i]) 3'b000: if ( | DATA_PRESENT[3:0]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b001: if ( | DATA_PRESENT[7:4]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b010: if ( | DATA_PRESENT[11:8]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; default: final_do_max[i] <= #TCQ final_do_max[i]; endcase end end always @(posedge clk) if (rst) begin final_do_index[i] <= #TCQ 0; end else begin final_do_index[i] <= #TCQ final_do_index[i] + 1; end for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop always @(posedge clk) begin if (rst) begin final_data_offset[i][6*j+:6] <= #TCQ 'b0; end else begin //if (dqsfound_retry[j]) // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; //else if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; if (CWL_M % 2) // odd latency CAS slot 1 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; else // even latency CAS slot 0 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; end end else if (init_dqsfound_done_r5 ) begin if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; end end end end end end endgenerate // Error generation in case pi_found_dqs signal from Phaser_IN // is not asserted when a common rddata_offset value is used always @(posedge clk) begin pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; end endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_dqs_found_cal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling calibration logic // NOTES: // 1. Phaser_In DQSFOUND calibration //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ **$Date: 2011/06/02 08:35:08 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_dqs_found_cal_hr # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter nCL = 5, // Read CAS latency parameter AL = "0", parameter nCWL = 5, // Write CAS latency parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter RANKS = 1, // # of memory ranks in the system parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate parameter N_CTL_LANES = 3, // Number of control byte lanes parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) parameter HIGHEST_BANK = 3, // Sum of I/O Banks parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf ) ( input clk, input rst, input dqsfound_retry, // From phy_init input pi_dqs_found_start, input detect_pi_found_dqs, input prech_done, // DQSFOUND per Phaser_IN input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, // To phy_init output [5:0] rd_data_offset_0, output [5:0] rd_data_offset_1, output [5:0] rd_data_offset_2, output pi_dqs_found_rank_done, output pi_dqs_found_done, output reg pi_dqs_found_err, output [6*RANKS-1:0] rd_data_offset_ranks_0, output [6*RANKS-1:0] rd_data_offset_ranks_1, output [6*RANKS-1:0] rd_data_offset_ranks_2, output reg dqsfound_retry_done, output reg dqs_found_prech_req, //To MC output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, input [8:0] po_counter_read_val, output rd_data_offset_cal_done, output fine_adjust_done, output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, output reg ck_po_stg2_f_indec, output reg ck_po_stg2_f_en, output [255:0] dbg_dqs_found_cal ); // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Added to reduce simulation time localparam LATENCY_FACTOR = 13; localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; localparam FINE_ADJ_IDLE = 4'h0; localparam RST_POSTWAIT = 4'h1; localparam RST_POSTWAIT1 = 4'h2; localparam RST_WAIT = 4'h3; localparam FINE_ADJ_INIT = 4'h4; localparam FINE_INC = 4'h5; localparam FINE_INC_WAIT = 4'h6; localparam FINE_INC_PREWAIT = 4'h7; localparam DETECT_PREWAIT = 4'h8; localparam DETECT_DQSFOUND = 4'h9; localparam PRECH_WAIT = 4'hA; localparam FINE_DEC = 4'hB; localparam FINE_DEC_WAIT = 4'hC; localparam FINE_DEC_PREWAIT = 4'hD; localparam FINAL_WAIT = 4'hE; localparam FINE_ADJ_DONE = 4'hF; integer k,l,m,n,p,q,r,s; reg dqs_found_start_r; reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; reg rank_done_r; reg rank_done_r1; reg dqs_found_done_r; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; reg init_dqsfound_done_r; reg init_dqsfound_done_r1; reg init_dqsfound_done_r2; reg init_dqsfound_done_r3; reg init_dqsfound_done_r4; reg init_dqsfound_done_r5; reg [1:0] rnk_cnt_r; reg [2:0 ] final_do_index[0:RANKS-1]; reg [5:0 ] final_do_max[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; reg [10*HIGHEST_BANK-1:0] retry_cnt; reg dqsfound_retry_r1; wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; // CK/Control byte lanes fine adjust stage reg fine_adjust; reg [N_CTL_LANES-1:0] ctl_lane_cnt; reg [3:0] fine_adj_state_r; reg fine_adjust_done_r; reg rst_dqs_find; reg rst_dqs_find_r1; reg rst_dqs_find_r2; reg [5:0] init_dec_cnt; reg [5:0] dec_cnt; reg [5:0] inc_cnt; reg final_dec_done; reg init_dec_done; reg first_fail_detect; reg second_fail_detect; reg [5:0] first_fail_taps; reg [5:0] second_fail_taps; reg [5:0] stable_pass_cnt; reg [3:0] detect_rd_cnt; //*************************************************************************** // Debug signals // //*************************************************************************** assign dbg_dqs_found_cal[5:0] = first_fail_taps; assign dbg_dqs_found_cal[11:6] = second_fail_taps; assign dbg_dqs_found_cal[12] = first_fail_detect; assign dbg_dqs_found_cal[13] = second_fail_detect; assign dbg_dqs_found_cal[14] = fine_adjust_done_r; assign pi_dqs_found_rank_done = rank_done_r; assign pi_dqs_found_done = dqs_found_done_r; generate genvar rnk_cnt; if (HIGHEST_BANK == 3) begin // Three Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; end end else if (HIGHEST_BANK == 2) begin // Two Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end else begin // Single Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end endgenerate // final_data_offset is used during write calibration and during // normal operation. One rd_data_offset value per rank for entire // interface generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : final_data_offset[rnk_cnt_r][12+:6]; end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = 'd0; end else begin assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = 'd0; assign rd_data_offset_2 = 'd0; end endgenerate assign rd_data_offset_cal_done = init_dqsfound_done_r; assign fine_adjust_lane_cnt = ctl_lane_cnt; //************************************************************************** // DQSFOUND all and any generation // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are // asserted // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx // is asserted //************************************************************************** generate if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; endgenerate always @(posedge clk) begin if (rst) begin for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found pi_dqs_found_all_bank[k] <= #TCQ 'b0; pi_dqs_found_any_bank[k] <= #TCQ 'b0; end end else if (pi_dqs_found_start) begin for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); end end end always @(posedge clk) begin pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; end //***************************************************************************** // Counter to increase number of 4 back-to-back reads per rd_data_offset and // per CK/A/C tap value //***************************************************************************** always @(posedge clk) begin if (rst || (detect_rd_cnt == 'd0)) detect_rd_cnt <= #TCQ NUM_READS; else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) detect_rd_cnt <= #TCQ detect_rd_cnt - 1; end //************************************************************************** // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls // //************************************************************************** assign fine_adjust_done = fine_adjust_done_r; always @(posedge clk) begin rst_dqs_find_r1 <= #TCQ rst_dqs_find; rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; end always @(posedge clk) begin if(rst)begin fine_adjust <= #TCQ 1'b0; ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; fine_adjust_done_r <= #TCQ 1'b0; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b0; init_dec_cnt <= #TCQ 'd31; dec_cnt <= #TCQ 'd0; inc_cnt <= #TCQ 'd0; init_dec_done <= #TCQ 1'b0; final_dec_done <= #TCQ 1'b0; first_fail_detect <= #TCQ 1'b0; second_fail_detect <= #TCQ 1'b0; first_fail_taps <= #TCQ 'd0; second_fail_taps <= #TCQ 'd0; stable_pass_cnt <= #TCQ 'd0; dqs_found_prech_req<= #TCQ 1'b0; end else begin case (fine_adj_state_r) FINE_ADJ_IDLE: begin if (init_dqsfound_done_r5) begin if (SIM_CAL_OPTION == "FAST_CAL") begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; rst_dqs_find <= #TCQ 1'b0; end else begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; rst_dqs_find <= #TCQ 1'b1; end end end RST_WAIT: begin if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin rst_dqs_find <= #TCQ 1'b0; if (|init_dec_cnt) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else if (final_dec_done) fine_adj_state_r <= #TCQ FINE_ADJ_DONE; else fine_adj_state_r <= #TCQ RST_POSTWAIT; end end RST_POSTWAIT: begin fine_adj_state_r <= #TCQ RST_POSTWAIT1; end RST_POSTWAIT1: begin fine_adj_state_r <= #TCQ FINE_ADJ_INIT; end FINE_ADJ_INIT: begin //if (detect_pi_found_dqs && (inc_cnt < 'd63)) fine_adj_state_r <= #TCQ FINE_INC; end FINE_INC: begin fine_adj_state_r <= #TCQ FINE_INC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b1; ck_po_stg2_f_en <= #TCQ 1'b1; if (ctl_lane_cnt == N_CTL_LANES-1) inc_cnt <= #TCQ inc_cnt + 1; end FINE_INC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ DETECT_PREWAIT; end end FINE_INC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_INC; end DETECT_PREWAIT: begin if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) fine_adj_state_r <= #TCQ DETECT_DQSFOUND; else fine_adj_state_r <= #TCQ DETECT_PREWAIT; end DETECT_DQSFOUND: begin if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ 'd0; if (~first_fail_detect && (inc_cnt == 'd63)) begin // First failing tap detected at 63 taps // then decrement to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin // First failing tap detected at greater than 30 taps // then stop looking for second edge and decrement first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ (inc_cnt>>1) + 1; end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin // First failing tap detected, continue incrementing // until either second failing tap detected or 63 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin // Consecutive 30 taps of passing region was not found // continue incrementing first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt == 'd63)) begin if (stable_pass_cnt < 'd30) begin // Consecutive 30 taps of passing region was not found // from tap 0 to 63 so decrement back to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else begin // Consecutive 30 taps of passing region was found // between first_fail_taps and 63 fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end else begin // Second failing tap detected, decrement to center of // failing taps second_fail_detect <= #TCQ 1'b1; second_fail_taps <= #TCQ inc_cnt; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); fine_adj_state_r <= #TCQ FINE_DEC; end end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ stable_pass_cnt + 1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else if (inc_cnt < 'd63) begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end else begin fine_adj_state_r <= #TCQ FINE_DEC; if (~first_fail_detect || (first_fail_taps > 'd33)) // No failing taps detected, decrement by 31 dec_cnt <= #TCQ 'd32; //else if (first_fail_detect && (stable_pass_cnt > 'd28)) // // First failing tap detected between 0 and 34 // // decrement midpoint between 63 and failing tap // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); else // First failing tap detected // decrement to midpoint between 63 and failing tap dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end end PRECH_WAIT: begin if (prech_done) begin dqs_found_prech_req <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end end FINE_DEC: begin fine_adj_state_r <= #TCQ FINE_DEC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b1; if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) init_dec_cnt <= #TCQ init_dec_cnt - 1; else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) dec_cnt <= #TCQ dec_cnt - 1; end FINE_DEC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else begin fine_adj_state_r <= #TCQ FINAL_WAIT; if ((init_dec_cnt == 'd0) && ~init_dec_done) init_dec_done <= #TCQ 1'b1; else final_dec_done <= #TCQ 1'b1; end end end FINE_DEC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_DEC; end FINAL_WAIT: begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end FINE_ADJ_DONE: begin if (&pi_dqs_found_all_bank) begin fine_adjust_done_r <= #TCQ 1'b1; rst_dqs_find <= #TCQ 1'b0; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; end end endcase end end //***************************************************************************** always@(posedge clk) dqs_found_start_r <= #TCQ pi_dqs_found_start; always @(posedge clk) begin if (rst) rnk_cnt_r <= #TCQ 2'b00; else if (init_dqsfound_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r; else if (rank_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r + 1; end //***************************************************************** // Read data_offset calibration done signal //***************************************************************** always @(posedge clk) begin if (rst || (|pi_rst_stg1_cal_r)) init_dqsfound_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank) begin if (rnk_cnt_r == RANKS-1) init_dqsfound_done_r <= #TCQ 1'b1; else init_dqsfound_done_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst || (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) rank_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) rank_done_r <= #TCQ 1'b1; else rank_done_r <= #TCQ 1'b0; end always @(posedge clk) begin pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; rank_done_r1 <= #TCQ rank_done_r; dqsfound_retry_r1 <= #TCQ dqsfound_retry; end always @(posedge clk) begin if (rst) dqs_found_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && (fine_adj_state_r == FINE_ADJ_DONE)) dqs_found_done_r <= #TCQ 1'b1; else dqs_found_done_r <= #TCQ 1'b0; end generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[2]) || (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[20+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[2]) retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; else retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[2] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[2] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; end always @(posedge clk) begin if (rst) begin for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && //(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1; end //***************************************************************************** // Two I/O Bank Interface //***************************************************************************** end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; end //***************************************************************************** // One I/O Bank Interface //***************************************************************************** end else begin // One I/O Bank Interface // Read data offset value for all DQS in Bank0 always @(posedge clk) begin if (rst) begin for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r] <= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1; end // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted even with 3 dqfound retries always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end end endgenerate always @(posedge clk) begin if (rst) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; else if (rst_dqs_find) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; else pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; end // Final read data offset value to be used during write calibration and // normal operation generate genvar i; genvar j; for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop reg [5:0] final_do_cand [RANKS-1:0]; // combinatorially select the candidate offset for the bank // indexed by final_do_index if (HIGHEST_BANK == 3) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; default: final_do_cand[i] = 'd0; endcase end end else if (HIGHEST_BANK == 2) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end else begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = 'd0; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end always @(posedge clk) begin if (rst) final_do_max[i] <= #TCQ 0; else begin final_do_max[i] <= #TCQ final_do_max[i]; // default case (final_do_index[i]) 3'b000: if ( | DATA_PRESENT[3:0]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b001: if ( | DATA_PRESENT[7:4]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b010: if ( | DATA_PRESENT[11:8]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; default: final_do_max[i] <= #TCQ final_do_max[i]; endcase end end always @(posedge clk) if (rst) begin final_do_index[i] <= #TCQ 0; end else begin final_do_index[i] <= #TCQ final_do_index[i] + 1; end for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop always @(posedge clk) begin if (rst) begin final_data_offset[i][6*j+:6] <= #TCQ 'b0; end else begin //if (dqsfound_retry[j]) // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; //else if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; if (CWL_M % 2) // odd latency CAS slot 1 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; else // even latency CAS slot 0 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; end end else if (init_dqsfound_done_r5 ) begin if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; end end end end end end endgenerate // Error generation in case pi_found_dqs signal from Phaser_IN // is not asserted when a common rddata_offset value is used always @(posedge clk) begin pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; end endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_init.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has an interface for providing control/address and write // data to the PHY Control Block during initialization/calibration. // Once initialization and calibration are complete, control is passed to the MC. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_init # ( parameter tCK = 1500, // DDRx SDRAM clock period parameter TCQ = 100, parameter nCK_PER_CLK = 4, // # of memory clocks per CLK parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 // 150 - 1.50 V // 135 - 1.35 V // 125 - 1.25 V parameter VREF = "EXTERNAL", // Internal or external Vref parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH parameter BANK_WIDTH = 2, parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for // component I/F with CS_WIDTH=1, // nCS_PER_RANK=# of components parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter ROW_WIDTH = 14, parameter CS_WIDTH = 1, parameter RANKS = 1, // # of memory ranks in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DRAM_TYPE = "DDR3", parameter REG_CTRL = "ON", parameter ADDR_CMD_MODE= "1T", // calibration Address parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type // parameter nAL = 0, // Additive latency (in clk cyc) parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay (in ps) parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes parameter REFRESH_TIMER_WIDTH = 8, parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter RTT_NOM = "60", // Nominal ODT termination value parameter RTT_WR = "60", // Write ODT termination value parameter WRLVL = "ON", // Enable write leveling // parameter PHASE_DETECT = "ON", // Enable read phase detector parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter nSLOTS = 1, // Number of DIMM SLOTs in the system parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" parameter CKE_ODT_AUX = "FALSE", parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration parameter TEST_AL = "0", // Internal use for ICM verification parameter FIXED_VICTIM = "TRUE", parameter BYPASS_COMPLEX_OCAL = "FALSE", parameter SKIP_CALIB = "FALSE" ) ( input clk, input rst, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, input delay_incdec_done, input ck_addr_cmd_delay_done, input pi_phase_locked_all, input pi_dqs_found_done, input dqsfound_retry, input dqs_found_prech_req, output reg pi_phaselock_start, output pi_phase_locked_err, output pi_calib_done, input phy_if_empty, // Read/write calibration interface input wrlvl_done, input wrlvl_rank_done, input wrlvl_byte_done, input wrlvl_byte_redo, input wrlvl_final, output reg wrlvl_final_if_rst, input oclkdelay_calib_done, input oclk_prech_req, input oclk_calib_resume, input lim_done, input lim_wr_req, output reg oclkdelay_calib_start, //complex oclkdelay calibration input complex_oclkdelay_calib_done, input complex_oclk_prech_req, input complex_oclk_calib_resume, output reg complex_oclkdelay_calib_start, input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt output reg complex_ocal_num_samples_inc, input complex_ocal_num_samples_done_r, input [2:0] complex_ocal_rd_victim_sel, output reg complex_ocal_reset_rd_addr, input complex_ocal_ref_req, output reg complex_ocal_ref_done, input done_dqs_tap_inc, input [5:0] rd_data_offset_0, input [5:0] rd_data_offset_1, input [5:0] rd_data_offset_2, input [6*RANKS-1:0] rd_data_offset_ranks_0, input [6*RANKS-1:0] rd_data_offset_ranks_1, input [6*RANKS-1:0] rd_data_offset_ranks_2, input pi_dqs_found_rank_done, input wrcal_done, input wrcal_prech_req, input wrcal_read_req, input wrcal_act_req, input temp_wrcal_done, input [7:0] slot_0_present, input [7:0] slot_1_present, output reg wl_sm_start, output reg wr_lvl_start, output reg wrcal_start, output reg wrcal_rd_wait, output reg wrcal_sanity_chk, output reg tg_timer_done, output reg no_rst_tg_mc, input rdlvl_stg1_done, input rdlvl_stg1_rank_done, output reg rdlvl_stg1_start, output reg pi_dqs_found_start, output reg detect_pi_found_dqs, // rdlvl stage 1 precharge requested after each DQS input rdlvl_prech_req, input rdlvl_last_byte_done, input wrcal_resume, input wrcal_sanity_chk_done, // MPR read leveling input mpr_rdlvl_done, input mpr_rnk_done, input mpr_last_byte_done, output reg mpr_rdlvl_start, output reg mpr_end_if_reset, // PRBS Read Leveling input prbs_rdlvl_done, input prbs_last_byte_done, input prbs_rdlvl_prech_req, input complex_victim_inc, input [2:0] rd_victim_sel, input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] victim_sel, output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, output reg prbs_rdlvl_start, output reg prbs_gen_clk_en, output reg prbs_gen_oclk_clk_en, output reg complex_sample_cnt_inc, output reg complex_sample_cnt_inc_ocal, output reg complex_wr_done, // Signals shared btw multiple calibration stages output reg prech_done, // Data select / status output reg init_calib_complete, // Signal to mask memory model error for Invalid latching edge output reg calib_writes, // PHY address/control // 2 commands to PHY Control Block per div 2 clock in 2:1 mode // 4 commands to PHY Control Block per div 4 clock in 4:1 mode output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output reg [nCK_PER_CLK-1:0] phy_ras_n, output reg [nCK_PER_CLK-1:0] phy_cas_n, output reg [nCK_PER_CLK-1:0] phy_we_n, output reg phy_reset_n, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, // Hard PHY Interface signals input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, output reg calib_ctl_wren, output reg calib_cmd_wren, output reg [1:0] calib_seq, output reg write_calib, output reg read_calib, // PHY_Ctl_Wd output reg [2:0] calib_cmd, // calib_aux_out used for CKE and ODT output reg [3:0] calib_aux_out, output reg [1:0] calib_odt , output reg [nCK_PER_CLK-1:0] calib_cke , output [1:0] calib_rank_cnt, output reg [1:0] calib_cas_slot, output reg [5:0] calib_data_offset_0, output reg [5:0] calib_data_offset_1, output reg [5:0] calib_data_offset_2, // PHY OUT_FIFO output reg calib_wrdata_en, output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, // PHY Read output phy_rddata_en, output phy_rddata_valid, output [255:0] dbg_phy_init, input reset_rd_addr, //OCAL centering calibration input oclkdelay_center_calib_start, input oclk_center_write_resume, input oclkdelay_center_calib_done, input rdlvl_pi_incdec, //rdlvl pi dec input complex_pi_incdec_done, input num_samples_done_r, input complex_init_pi_dec_done, output reg complex_act_start, output reg calib_tap_inc_start, output reg calib_tap_end_if_reset, input calib_tap_inc_done ); //***************************************************************************** // Assertions to be added //***************************************************************************** // The phy_ctl_full signal must never be asserted in synchronous mode of // operation either 4:1 or 2:1 // // The RANKS parameter must never be set to '0' by the user // valid values: 1 to 4 // //***************************************************************************** //*************************************************************************** // Number of Read level stage 1 writes limited to a SDRAM row // The address of Read Level stage 1 reads must also be limited // to a single SDRAM row // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : (BURST_MODE == "4") ? 8 : 4; localparam ADDR_INC = (BURST_MODE == "8") ? 8 : (BURST_MODE == "4") ? 4 : 8; // In a 2 slot dual rank per system RTT_NOM values // for Rank2 and Rank3 default to 40 ohms localparam RTT_NOM2 = "40"; localparam RTT_NOM3 = "40"; localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; // Specifically for use with half-frequency controller (nCK_PER_CLK=2) // = 1 if burst length = 4, = 0 if burst length = 8. Determines how // often row command needs to be issued during read-leveling // For DDR3 the burst length is fixed during calibration localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : (BURST_MODE == "8") ? 1'b0 : ((BURST_MODE == "4") ? 1'b1 : 1'b0); //*************************************************************************** // Counter values used to determine bus timing // NOTE on all counter terminal counts - these can/should be one less than // the actual delay to take into account extra clock cycle delay in // generating the corresponding "done" signal //*************************************************************************** localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; // Calculate initial delay required in number of CLK clock cycles // to delay initially. The counter is clocked by [CLK/1024] - which // is approximately division by 1000 - note that the formulas below will // result in more than the minimum wait time because of this approximation. // NOTE: For DDR3 JEDEC specifies to delay reset // by 200us, and CKE by an additional 500us after power-up // For DDR2 CKE is delayed by 200us after power up. localparam DDR3_RESET_DELAY_NS = 200000; localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; localparam DDR2_CKE_DELAY_NS = 200000; localparam PWRON_RESET_DELAY_CNT = ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation // needs to be reworked. localparam DDR2_INIT_PRE_DELAY_PS = 400000; localparam DDR2_INIT_PRE_CNT = ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; // Calculate tXPR time: reset from CKE HIGH to valid command after power-up // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock // cycles because this counter actually starts up before CKE is asserted // to memory. localparam TXPR_DELAY_CNT = (5*CLK_MEM_PERIOD > tRFC+10000) ? (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV localparam TDLLK_TZQINIT_DELAY_CNT = 255; // TWR values in ns. Both DDR2 and DDR3 have the same value. // 15000ns/tCK localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; // time to wait between consecutive commands in PHY_INIT - this is a // generic number, and must be large enough to account for worst case // timing parameter (tRFC - refresh-to-active) across all memory speed // grades and operating frequencies. Expressed in clk // (Divided by 4 or Divided by 2) clock cycles. localparam CNTNEXT_CMD = 7'b1111111; // Counter values to keep track of which MR register to load during init // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode // register configured during initialization. // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init localparam INIT_CNT_MR2 = 2'b00; localparam INIT_CNT_MR3 = 2'b01; localparam INIT_CNT_MR1 = 2'b10; localparam INIT_CNT_MR0 = 2'b11; localparam INIT_CNT_MR_DONE = 2'b11; // Register chip programmable values for DDR3 // The register chip for the registered DIMM needs to be programmed // before the initialization of the registered DIMM. // Address for the control word is in : DBA2, DA2, DA1, DA0 // Data for the control word is in: DBA1 DBA0, DA4, DA3 // The values will be stored in the local param in the following format // {DBA[2:0], DA[4:0]} // RC0 is global features control word. Address == 000 localparam REG_RC0 = 8'b00000000; // RC1 Clock driver enable control word. Enables or disables the four // output clocks in the register chip. For single rank and dual rank // two clocks will be enabled and for quad rank all the four clocks // will be enabled. Address == 000. Data = 0110 for single and dual rank. // = 0000 for quad rank localparam REG_RC1 = 8'b00000001; // RC2 timing control word. Set in 1T timing mode // Address = 010. Data = 0000 localparam REG_RC2 = 8'b00000010; // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; // RC10 timing control work. Setting the data to 0000 localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : (tCK >= 1250 && tCK < 1500) ? 4'b0011 : (tCK >= 1500 && tCK < 1875) ? 4'b0010 : (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : {1'b0,VREF_ENCODING,2'b00} ; localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Count value to generate pi_phase_locked_err signal localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; // Timeout interval for detecting error with Traffic Generator localparam [13:0] TG_TIMER_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; //bit num per DQS localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; //COMPLEX_ROW_CNT_BYTE localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; // Master state machine encoding localparam INIT_IDLE = 7'b0000000; //0 localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 localparam INIT_LOAD_MR = 7'b0000010; //2 localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 localparam INIT_ZQCL = 7'b0000100; //4 localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 localparam INIT_WRLVL_START = 7'b0000110; //6 localparam INIT_WRLVL_WAIT = 7'b0000111; //7 localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B localparam INIT_RDLVL_ACT = 7'b0001100; //C localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 localparam INIT_PRECHARGE = 7'b0010100; //14 localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 localparam INIT_DONE = 7'b0010110; //16 localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 localparam INIT_REFRESH = 7'b0011001; //19 localparam INIT_REFRESH_WAIT = 7'b0011010; //1A localparam INIT_REG_WRITE = 7'b0011011; //1B localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E localparam INIT_WRCAL_ACT = 7'b0011111; //1F localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 localparam INIT_WRCAL_WRITE = 7'b0100001; //21 localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 localparam INIT_WRCAL_READ = 7'b0100011; //23 localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 localparam INIT_MPR_RDEN = 7'b0100111; //27 localparam INIT_MPR_WAIT = 7'b0101000; //28 localparam INIT_MPR_READ = 7'b0101001; //29 localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A localparam INIT_MPR_DISABLE = 7'b0101011; //2B localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 localparam INIT_RDLVL_COMPLEX_PI_WAIT = 7'b1000011; //43 localparam INIT_SKIP_CALIB_WAIT = 7'b1000100; //44 integer i, j, k, l, m, n, p, q; reg pi_dqs_found_all_r; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; reg pi_calib_rank_done_r; reg [13:0] pi_phaselock_timer; reg stg1_wr_done; reg rnk_ref_cnt; reg pi_dqs_found_done_r1; reg pi_dqs_found_rank_done_r; reg read_calib_int; reg read_calib_r; reg pi_calib_done_r; reg pi_calib_done_r1; reg burst_addr_r; reg [1:0] chip_cnt_r; reg [6:0] cnt_cmd_r; reg cnt_cmd_done_r; reg cnt_cmd_done_m7_r; reg [7:0] cnt_dllk_zqinit_r; reg cnt_dllk_zqinit_done_r; reg cnt_init_af_done_r; reg [1:0] cnt_init_af_r; reg [1:0] cnt_init_data_r; reg [1:0] cnt_init_mr_r; reg cnt_init_mr_done_r; reg cnt_init_pre_wait_done_r; reg [7:0] cnt_init_pre_wait_r; reg [9:0] cnt_pwron_ce_r; reg cnt_pwron_cke_done_r; reg cnt_pwron_cke_done_r1; reg [8:0] cnt_pwron_r; reg cnt_pwron_reset_done_r; reg cnt_txpr_done_r; reg [7:0] cnt_txpr_r; reg ddr2_pre_flag_r; reg ddr2_refresh_flag_r; reg ddr3_lm_done_r; reg [4:0] enable_wrlvl_cnt; reg init_complete_r; reg init_complete_r1; reg init_complete_r2; (* keep = "true" *) reg init_complete_r_timing; (* keep = "true" *) reg init_complete_r1_timing; reg [6:0] init_next_state; reg [6:0] init_state_r; reg [6:0] init_state_r1; wire [15:0] load_mr0; wire [15:0] load_mr1; wire [15:0] load_mr2; wire [15:0] load_mr3; reg mem_init_done_r; reg [1:0] mr2_r [0:3]; reg [2:0] mr1_r [0:3]; reg new_burst_r; reg [15:0] wrcal_start_dly_r; wire wrcal_start_pre; reg wrcal_resume_r; // Only one ODT signal per rank in PHY Control Block reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; wire prech_done_pre; reg [15:0] prech_done_dly_r; reg prech_pending_r; reg prech_req_posedge_r; reg prech_req_r; reg pwron_ce_r; reg first_rdlvl_pat_r; reg first_wrcal_pat_r; reg phy_wrdata_en; reg phy_wrdata_en_r1; reg [1:0] wrdata_pat_cnt; reg [1:0] wrcal_pat_cnt; reg [ROW_WIDTH-1:0] address_w; reg [BANK_WIDTH-1:0] bank_w; reg rdlvl_stg1_done_r1; reg rdlvl_stg1_start_int; reg [15:0] rdlvl_start_dly0_r; reg rdlvl_start_pre; reg rdlvl_last_byte_done_r; wire rdlvl_rd; wire rdlvl_wr; reg rdlvl_wr_r; wire rdlvl_wr_rd; reg [3:0] reg_ctrl_cnt_r; reg [1:0] tmp_mr2_r [0:3]; reg [2:0] tmp_mr1_r [0:3]; reg wrlvl_done_r; reg wrlvl_done_r1; reg wrlvl_rank_done_r1; reg wrlvl_rank_done_r2; reg wrlvl_rank_done_r3; reg wrlvl_rank_done_r4; reg wrlvl_rank_done_r5; reg wrlvl_rank_done_r6; reg wrlvl_rank_done_r7; reg [2:0] wrlvl_rank_cntr; reg wrlvl_odt_ctl; reg wrlvl_odt; reg wrlvl_active; reg wrlvl_active_r1; reg [2:0] num_reads; reg temp_wrcal_done_r; reg temp_lmr_done; reg extend_cal_pat; reg [13:0] tg_timer; reg tg_timer_go; reg cnt_wrcal_rd; reg [3:0] cnt_wait; reg [7:0] wrcal_reads; reg [8:0] stg1_wr_rd_cnt; reg phy_data_full_r; reg wr_level_dqs_asrt; reg wr_level_dqs_asrt_r1; reg [1:0] dqs_asrt_cnt; reg [3:0] num_refresh; wire oclkdelay_calib_start_pre; reg [15:0] oclkdelay_start_dly_r; reg [3:0] oclk_wr_cnt; reg [3:0] wrcal_wr_cnt; reg wrlvl_final_r; reg prbs_rdlvl_done_r1; reg prbs_rdlvl_done_r2; reg prbs_rdlvl_done_r3; reg prbs_last_byte_done_r; reg phy_if_empty_r; reg prbs_pat_resume_int; reg complex_row0_wr_done; reg complex_row1_wr_done; reg complex_row0_rd_done; reg complex_row1_rd_done; reg complex_row0_rd_done_r1; reg [3:0] complex_wait_cnt; reg [3:0] complex_num_reads; reg [3:0] complex_num_reads_dec; reg [ROW_WIDTH-1:0] complex_address; reg wr_victim_inc; reg [2:0] wr_victim_sel; reg [7:0] complex_row_cnt; reg complex_sample_cnt_inc_r1; reg complex_sample_cnt_inc_r2; reg complex_odt_ext; reg complex_ocal_odt_ext; reg wrcal_final_chk; wire prech_req; reg reset_rd_addr_r1; reg complex_rdlvl_int_ref_req; reg ext_int_ref_req; //complex OCLK delay calibration reg [7:0] complex_row_cnt_ocal; reg [4:0] complex_num_writes; reg [4:0] complex_num_writes_dec; reg complex_oclkdelay_calib_start_int; reg complex_oclkdelay_calib_start_r1; reg complex_oclkdelay_calib_start_r2; reg complex_oclkdelay_calib_done_r1; // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; reg [2:0] wr_victim_sel_ocal; reg complex_row1_rd_done_r1; //time for switch to write reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) reg complex_byte_rd_done; //read for the byte is done reg complex_byte_rd_done_r1; // reg complex_row_change; //every 16 rows of read, it is set to "0" for write reg ocal_num_samples_inc; //1 read/write is done reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining reg prech_done_r1, prech_done_r2, prech_done_r3; reg mask_lim_done; reg complex_mask_lim_done; reg oclkdelay_calib_start_int; reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; reg oclkdelay_int_ref_req; reg [3:0] ocal_act_wait_cnt; reg oclk_calib_resume_level; reg ocal_last_byte_done; wire mmcm_wr; //MMCM centering write. no CS will be set wire exit_ocal_complex_resume_wait = init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; reg calib_tap_inc_done_r1; //*************************************************************************** // Debug //*************************************************************************** //synthesis translate_off always @(posedge mem_init_done_r) begin if (!rst) $display ("PHY_INIT: Memory Initialization completed at %t", $time); end always @(posedge wrlvl_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Leveling completed at %t", $time); end always @(posedge rdlvl_stg1_done) begin if (!rst) $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); end always @(posedge mpr_rdlvl_done) begin if (!rst) $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); end always @(posedge oclkdelay_calib_done) begin if (!rst) $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); end always @(posedge pi_calib_done_r1) begin if (!rst) $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); end always @(posedge pi_dqs_found_done) begin if (!rst) $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); end always @(posedge wrcal_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Calibration completed at %t", $time); end always@(posedge prbs_rdlvl_done)begin if(!rst) $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); end always@(posedge complex_oclkdelay_calib_done)begin if(!rst) $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); end always@(posedge oclkdelay_center_calib_done)begin if(!rst) $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); end //synthesis translate_on assign dbg_phy_init[5:0] = init_state_r; assign dbg_phy_init[6+:8] = complex_row_cnt; assign dbg_phy_init[14+:3] = victim_sel; assign dbg_phy_init[17+:4] = victim_byte_cnt; assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; assign dbg_phy_init[30+:15] = complex_address; assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; assign dbg_phy_init[61] =prech_req_posedge_r ; //*************************************************************************** // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage //*************************************************************************** // assign pi_phaselock_calib_cnt = dqs_cnt_r; assign pi_calib_done = pi_calib_done_r1; //prevent PI incdec during complex read always @ (posedge clk) complex_act_start <= #TCQ (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT); //detect rising edge of prbs_rdlvl_done to reset all control sighals always @ (posedge clk) begin prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; end always @(posedge clk) begin if (rst) wrcal_final_chk <= #TCQ 1'b0; else if ((init_next_state == INIT_WRCAL_ACT) && (wrcal_done || (SKIP_CALIB == "TRUE")) && (DRAM_TYPE == "DDR3")) wrcal_final_chk <= #TCQ 1'b1; end always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; wrcal_resume_r <= #TCQ wrcal_resume; wrcal_sanity_chk <= #TCQ wrcal_final_chk; end always @(posedge clk) begin if (rst) mpr_end_if_reset <= #TCQ 1'b0; else if (mpr_last_byte_done && (num_refresh != 'd0)) mpr_end_if_reset <= #TCQ 1'b1; else mpr_end_if_reset <= #TCQ 1'b0; end // Siganl to mask memory model error for Invalid latching edge always @(posedge clk) if (rst) calib_writes <= #TCQ 1'b0; else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ)) calib_writes <= #TCQ 1'b1; else calib_writes <= #TCQ 1'b0; always @(posedge clk) if (rst) wrcal_rd_wait <= #TCQ 1'b0; else if (init_state_r == INIT_WRCAL_READ_WAIT) wrcal_rd_wait <= #TCQ 1'b1; else wrcal_rd_wait <= #TCQ 1'b0; //*************************************************************************** // Signal PHY completion when calibration is finished // Signal assertion is delayed by four clock cycles to account for the // multi cycle path constraint to (phy_init_data_sel) signal. //*************************************************************************** always @(posedge clk) if (rst) begin init_complete_r <= #TCQ 1'b0; init_complete_r_timing <= #TCQ 1'b0; init_complete_r1 <= #TCQ 1'b0; init_complete_r1_timing <= #TCQ 1'b0; init_complete_r2 <= #TCQ 1'b0; init_calib_complete <= #TCQ 1'b0; end else begin if (init_state_r == INIT_DONE) begin init_complete_r <= #TCQ 1'b1; init_complete_r_timing <= #TCQ 1'b1; end init_complete_r1 <= #TCQ init_complete_r; init_complete_r1_timing <= #TCQ init_complete_r_timing; init_complete_r2 <= #TCQ init_complete_r1; init_calib_complete <= #TCQ init_complete_r2; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; else complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; //reset read address for starting complex ocaldealy calib always @ (posedge clk) begin complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); end //first write for complex oclkdealy calib always @ (posedge clk) begin if (rst) complex_ocal_wr_start <= #TCQ 'b0; else complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; end //ocal stg3 centering start // always @ (posedge clk) // if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; // else // oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; //*************************************************************************** // Instantiate FF for the phy_init_data_sel signal. A multi cycle path // constraint will be assigned to this signal. This signal will only be // used within the PHY //*************************************************************************** // FDRSE u_ff_phy_init_data_sel // ( // .Q (phy_init_data_sel), // .C (clk), // .CE (1'b1), // .D (init_complete_r), // .R (1'b0), // .S (1'b0) // ) /* synthesis syn_preserve=1 */ // /* synthesis syn_replicate = 0 */; //*************************************************************************** // Mode register programming //*************************************************************************** //***************************************************************** // DDR3 Load mode reg0 // Mode Register (MR0): // [15:13] - unused - 000 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), // 1 (DLL maintained) // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4],[2] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [1:0] - Burst Length - BURST_LEN // DDR2 Load mode register // Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - Power-down mode - 0 (normal) // [11:9] - write recovery - write recovery for Auto Precharge // (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [2:0] - Burst Length - BURST_LEN //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : (BURST_MODE == "OTF") ? 2'b01 : (BURST_MODE == "4") ? 2'b10 : 2'b11; assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : ((nCL == 6) || (nCL == 14)) ? 3'b010 : (nCL == 7) ? 3'b011 : (nCL == 8) ? 3'b100 : (nCL == 9) ? 3'b101 : (nCL == 10) ? 3'b110 : (nCL == 11) ? 3'b111 : (nCL == 12) ? 3'b000 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : (TWR_CYC == 6) ? 3'b010 : (TWR_CYC == 7) ? 3'b011 : (TWR_CYC == 8) ? 3'b100 : (TWR_CYC == 9) ? 3'b101 : (TWR_CYC == 10) ? 3'b101 : (TWR_CYC == 11) ? 3'b110 : (TWR_CYC == 12) ? 3'b110 : (TWR_CYC == 13) ? 3'b111 : (TWR_CYC == 14) ? 3'b111 : (TWR_CYC == 15) ? 3'b000 : (TWR_CYC == 16) ? 3'b000 : 3'b010; assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' assign load_mr0[15:13] = 3'b000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : (BURST_MODE == "4") ? 3'b010 : 3'b111; assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : (nCL == 4) ? 3'b100 : (nCL == 5) ? 3'b101 : (nCL == 6) ? 3'b110 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : (TWR_CYC == 3) ? 3'b010 : (TWR_CYC == 4) ? 3'b011 : (TWR_CYC == 5) ? 3'b100 : (TWR_CYC == 6) ? 3'b101 : 3'b010; assign load_mr0[15:12]= 4'b0000; // Reserved end endgenerate //***************************************************************** // DDR3 Load mode reg1 // Mode Register (MR1): // [15:13] - unused - 00 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) // [10] - reserved - 0 (must be '0') // [9] - RTT[2] - 0 // [8] - reserved - 0 (must be '0') // [7] - write leveling - 0 (disabled), 1 (enabled) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) // [4:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) // [0] - DLL enable - 0 (normal) // DDR2 ext mode register // Extended Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - output enable - 0 (enabled) // [11] - RDQS enable - 0 (disabled) // [10] - DQS# enable - 0 (enabled) // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) // [0] - DLL enable - 0 (normal) //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; assign load_mr1[4:3] = (AL == "0") ? 2'b00 : (AL == "CL-1") ? 2'b01 : (AL == "CL-2") ? 2'b10 : 2'b11; assign load_mr1[5] = 1'b0; assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? 1'b1 : 1'b0; assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence assign load_mr1[8] = 1'b0; assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? 1'b1 : 1'b0; assign load_mr1[10] = 1'b0; assign load_mr1[15:11] = 5'b00000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? 1'b1 : 1'b0; assign load_mr1[5:3] = (AL == "0") ? 3'b000 : (AL == "1") ? 3'b001 : (AL == "2") ? 3'b010 : (AL == "3") ? 3'b011 : (AL == "4") ? 3'b100 : 3'b111; assign load_mr1[6] = ((RTT_NOM_int == "50") || (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; assign load_mr1[9:7] = 3'b000; assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; assign load_mr1[15:11] = 5'b00000; end endgenerate //***************************************************************** // DDR3 Load mode reg2 // Mode Register (MR2): // [15:11] - unused - 00 // [10:9] - RTT_WR - 00 (Dynamic ODT off) // [8] - reserved - 0 (must be '0') // [7] - self-refresh temperature range - // 0 (normal), 1 (extended) // [6] - Auto Self-Refresh - 0 (manual), 1(auto) // [5:3] - CAS Write Latency (CWL) - // 000 (5 for 400 MHz device), // 001 (6 for 400 MHz to 533 MHz devices), // 010 (7 for 533 MHz to 667 MHz devices), // 011 (8 for 667 MHz to 800 MHz) // [2:0] - Partial Array Self-Refresh (Optional) - // 000 (full array) // Not used for DDR2 //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 assign load_mr2[2:0] = 3'b000; assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : (nCWL == 6) ? 3'b001 : (nCWL == 7) ? 3'b010 : (nCWL == 8) ? 3'b011 : (nCWL == 9) ? 3'b100 : (nCWL == 10) ? 3'b101 : (nCWL == 11) ? 3'b110 : 3'b111; assign load_mr2[6] = 1'b0; assign load_mr2[7] = 1'b0; assign load_mr2[8] = 1'b0; // Dynamic ODT disabled assign load_mr2[10:9] = 2'b00; assign load_mr2[15:11] = 5'b00000; end else begin: gen_load_mr2_DDR2 assign load_mr2[15:0] = 16'd0; end endgenerate //***************************************************************** // DDR3 Load mode reg3 // Mode Register (MR3): // [15:3] - unused - All zeros // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) // [1:0] - MPR location - 00 (Predefined pattern) //***************************************************************** assign load_mr3[1:0] = 2'b00; assign load_mr3[2] = 1'b0; assign load_mr3[15:3] = 13'b0000000000000; // For multi-rank systems the rank being accessed during writes in // Read Leveling must be sent to phy_write for the bitslip logic assign calib_rank_cnt = chip_cnt_r; //*************************************************************************** // Logic to begin initial calibration, and to handle precharge requests // during read-leveling (to avoid tRAS violations if individual read // levelling calibration stages take more than max{tRAS) to complete). //*************************************************************************** // Assert when readback for each stage of read-leveling begins. However, // note this indicates only when the read command is issued and when // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not // indicate when the read data is present on the bus (when this happens // after the read command is issued depends on CAS LATENCY) - there will // need to be some delay before valid data is present on the bus. // assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); // Assert when read back for oclkdelay calibration begins assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); // Assert when read back for write calibration begins assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); // Common precharge signal done signal - pulses only when there has been // a precharge issued as a result of a PRECH_REQ pulse. Note also a common // PRECH_DONE signal is used for all blocks assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_MPR_RDEN) || ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || (init_state_r == INIT_OCAL_CENTER_ACT) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && prech_pending_r && !prech_req_posedge_r); always @(posedge clk) if (rst) calib_tap_inc_start <= #TCQ 1'b0; else if (init_state_r == INIT_SKIP_CALIB_WAIT) calib_tap_inc_start <= #TCQ 1'b1; always @(posedge clk) calib_tap_inc_done_r1 <= #TCQ calib_tap_inc_done; always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE)) calib_tap_end_if_reset <= #TCQ 1'b0; else if (calib_tap_inc_done && ~calib_tap_inc_done_r1) calib_tap_end_if_reset <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_phaselock_start <= #TCQ 1'b0; else if (init_state_r == INIT_PI_PHASELOCK_READS) pi_phaselock_start <= #TCQ 1'b1; // Delay start of each calibration by 16 clock cycles to ensure that when // calibration logic begins, read data is already appearing on the bus. // Each circuit should synthesize using an SRL16. Assume that reset is // long enough to clear contents of SRL16. always @(posedge clk) begin rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], rdlvl_start_pre}; wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], wrcal_start_pre}; oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], oclkdelay_calib_start_pre}; prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], prech_done_pre}; end always @(posedge clk) if (rst) oclkdelay_calib_start_int <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start_int <= #TCQ 1'b1; always @(posedge clk) begin if (rst) ocal_last_byte_done <= #TCQ 1'b0; else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) ocal_last_byte_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; else if (oclkdelay_calib_start_int) begin if (oclkdelay_ref_cnt > 'd0) oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; else oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; end end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) oclkdelay_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) ocal_act_wait_cnt <= #TCQ 'd0; else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; else ocal_act_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCLKDELAY_READ)) oclk_calib_resume_level <= #TCQ 1'b0; else if (oclk_calib_resume) oclk_calib_resume_level <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) complex_rdlvl_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) // complex_rdlvl_int_ref_req <= #TCQ 1'b1; complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) ext_int_ref_req <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) ext_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin prech_done <= #TCQ prech_done_dly_r[15]; prech_done_r1 <= #TCQ prech_done_dly_r[15]; prech_done_r2 <= #TCQ prech_done_r1; prech_done_r3 <= #TCQ prech_done_r2; end always @(posedge clk) if (rst) mpr_rdlvl_start <= #TCQ 1'b0; else if (pi_dqs_found_done && (init_state_r == INIT_MPR_READ)) mpr_rdlvl_start <= #TCQ 1'b1; always @(posedge clk) phy_if_empty_r <= #TCQ phy_if_empty; always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) prbs_gen_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) prbs_gen_clk_en <= #TCQ 1'b1; //Enable for complex oclkdelay - used in prbs gen always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT)) prbs_gen_oclk_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || exit_ocal_complex_resume_wait || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) prbs_gen_oclk_clk_en <= #TCQ 1'b1; generate if (RANKS < 2) begin always @(posedge clk) if (rst) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end else begin always @(posedge clk) if (rst || rdlvl_stg1_rank_done) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end endgenerate always @(posedge clk) begin if (rst || dqsfound_retry || wrlvl_byte_redo) begin pi_dqs_found_start <= #TCQ 1'b0; wrcal_start <= #TCQ 1'b0; end else begin if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) pi_dqs_found_start <= #TCQ 1'b1; if (wrcal_start_dly_r[5]) wrcal_start <= #TCQ 1'b1; end end // else: !if(rst) always @(posedge clk) if (rst) oclkdelay_calib_start <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_dqs_found_done_r1 <= #TCQ 1'b0; else pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final; // Reset IN_FIFO after final write leveling to make sure the FIFO // pointers are initialized always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) wrlvl_final_if_rst <= #TCQ 1'b0; else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && (init_state_r == INIT_WRLVL_LOAD_MR2)) wrlvl_final_if_rst <= #TCQ 1'b1; // Constantly enable DQS while write leveling is enabled in the memory // This is more to get rid of warnings in simulation, can later change // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted always @(posedge clk) if (rst || ((init_state_r1 != INIT_WRLVL_START) && (init_state_r == INIT_WRLVL_START))) wrlvl_odt_ctl <= #TCQ 1'b0; else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) wrlvl_odt_ctl <= #TCQ 1'b1; generate if (nCK_PER_CLK == 4) begin: en_cnt_div4 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd12; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end else begin: en_cnt_div2 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd21; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst || wrlvl_rank_done || done_dqs_tap_inc) wrlvl_active <= #TCQ 1'b0; else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) wrlvl_active <= #TCQ 1'b1; // signal used to assert DQS for write leveling. // the DQS will be asserted once every 16 clock cycles. always @(posedge clk)begin if(rst || (enable_wrlvl_cnt != 5'd1)) begin wr_level_dqs_asrt <= #TCQ 1'd0; end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin wr_level_dqs_asrt <= #TCQ 1'd1; end end always @ (posedge clk) begin if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) dqs_asrt_cnt <= #TCQ 2'd0; else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); end always @ (posedge clk) begin if (rst || ~wrlvl_active) wr_lvl_start <= #TCQ 1'd0; else if (dqs_asrt_cnt == 2'd3) wr_lvl_start <= #TCQ 1'd1; end always @(posedge clk) begin if (rst) wl_sm_start <= #TCQ 1'b0; else wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; end always @(posedge clk) begin wrlvl_active_r1 <= #TCQ wrlvl_active; wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; wrlvl_done_r <= #TCQ wrlvl_done; wrlvl_done_r1 <= #TCQ wrlvl_done_r; wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; end always @ (posedge clk) begin //if (rst) wrlvl_rank_cntr <= #TCQ 3'd0; //else if (wrlvl_rank_done) // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; end //***************************************************************** // Precharge request logic - those calibration logic blocks // that require greater than tRAS(max) to finish must break up // their calibration into smaller units of time, with precharges // issued in between. This is done using the XXX_PRECH_REQ and // PRECH_DONE handshaking between PHY_INIT and those blocks //***************************************************************** // Shared request from multiple sources assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); // Handshaking logic to force precharge during read leveling, and to // notify read leveling logic when precharge has been initiated and // it's okay to proceed with leveling again always @(posedge clk) if (rst) begin prech_req_r <= #TCQ 1'b0; prech_req_posedge_r <= #TCQ 1'b0; prech_pending_r <= #TCQ 1'b0; end else begin prech_req_r <= #TCQ prech_req; prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; if (prech_req_posedge_r) prech_pending_r <= #TCQ 1'b1; // Clear after we've finished with the precharge and have // returned to issuing read leveling calibration reads else if (prech_done_pre) prech_pending_r <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || prech_done_r3) mask_lim_done <= #TCQ 1'b0; else if (prech_pending_r) mask_lim_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || prbs_rdlvl_done_r3) complex_mask_lim_done <= #TCQ 1'b0; else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) complex_mask_lim_done <= #TCQ 1'b1; end //Complex oclkdelay calibrration //*************************************************************************** // Various timing counters //*************************************************************************** //***************************************************************** // Generic delay for various states that require it (e.g. for turnaround // between read and write). Make this a sufficiently large number of clock // cycles to cover all possible frequencies and memory components) // Requirements for this counter: // 1. Greater than tMRD // 2. tRFC (refresh-active) for DDR2 // 3. (list the other requirements, slacker...) //***************************************************************** always @(posedge clk) begin case (init_state_r) INIT_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR2_WAIT, INIT_MPR_WAIT, INIT_MPR_DISABLE_PREWAIT, INIT_MPR_DISABLE_WAIT, INIT_OCLKDELAY_ACT_WAIT, INIT_OCLKDELAY_WRITE_WAIT, INIT_RDLVL_ACT_WAIT, INIT_RDLVL_STG1_WRITE_READ, INIT_RDLVL_STG2_READ_WAIT, INIT_WRCAL_ACT_WAIT, INIT_WRCAL_WRITE_READ, INIT_WRCAL_READ_WAIT, INIT_PRECHARGE_PREWAIT, INIT_PRECHARGE_WAIT, INIT_DDR2_PRECHARGE_WAIT, INIT_REG_WRITE_WAIT, INIT_REFRESH_WAIT, INIT_REFRESH_RNK2_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_cmd_r <= #TCQ cnt_cmd_r; else cnt_cmd_r <= #TCQ cnt_cmd_r + 1; end INIT_WRLVL_WAIT: cnt_cmd_r <= #TCQ 'b0; default: cnt_cmd_r <= #TCQ 'b0; endcase end // pulse when count reaches terminal count always @(posedge clk) cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); // For ODT deassertion - hold throughout post read/write wait stage, but // deassert before next command. The post read/write stage is very long, so // we simply address the longest case here plus some margin. always @(posedge clk) cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); //************************************************************************ // Added to support PO fine delay inc when TG errors always @(posedge clk) begin case (init_state_r) INIT_WRCAL_READ_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_wait <= #TCQ cnt_wait; else cnt_wait <= #TCQ cnt_wait + 1; end default: cnt_wait <= #TCQ 'b0; endcase end always @(posedge clk) cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); always @(posedge clk) begin if (rst || ~temp_wrcal_done) temp_lmr_done <= #TCQ 1'b0; else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) temp_lmr_done <= #TCQ 1'b1; end always @(posedge clk) temp_wrcal_done_r <= #TCQ temp_wrcal_done; always @(posedge clk) if (rst) begin tg_timer_go <= #TCQ 1'b0; end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && (init_state_r == INIT_WRCAL_READ_WAIT)) begin tg_timer_go <= #TCQ 1'b1; end else begin tg_timer_go <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || (init_state_r == INIT_PRECHARGE_PREWAIT)) tg_timer <= #TCQ 'd0; else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && tg_timer_go && (tg_timer != TG_TIMER_TIMEOUT)) tg_timer <= #TCQ tg_timer + 1; end always @(posedge clk) begin if (rst) tg_timer_done <= #TCQ 1'b0; else if (tg_timer == TG_TIMER_TIMEOUT) tg_timer_done <= #TCQ 1'b1; else tg_timer_done <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) no_rst_tg_mc <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) no_rst_tg_mc <= #TCQ 1'b1; else no_rst_tg_mc <= #TCQ 1'b0; end //************************************************************************ always @(posedge clk) begin if (rst) detect_pi_found_dqs <= #TCQ 1'b0; else if ((cnt_cmd_r == 7'b0111111) && (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) detect_pi_found_dqs <= #TCQ 1'b1; else detect_pi_found_dqs <= #TCQ 1'b0; end //***************************************************************** // Initial delay after power-on for RESET, CKE // NOTE: Could reduce power consumption by turning off these counters // after initial power-up (at expense of more logic) // NOTE: Likely can combine multiple counters into single counter //***************************************************************** // Create divided by 1024 version of clock always @(posedge clk) if (rst) begin cnt_pwron_ce_r <= #TCQ 10'h000; pwron_ce_r <= #TCQ 1'b0; end else begin cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); end // "Main" power-on counter - ticks every CLKDIV/1024 cycles always @(posedge clk) if (rst) cnt_pwron_r <= #TCQ 'b0; else if (pwron_ce_r) cnt_pwron_r <= #TCQ cnt_pwron_r + 1; always @(posedge clk) if (rst || ~phy_ctl_ready) begin cnt_pwron_reset_done_r <= #TCQ 1'b0; cnt_pwron_cke_done_r <= #TCQ 1'b0; end else begin // skip power-up count for simulation purposes only if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || (SIM_INIT_OPTION == "SKIP_INIT")) begin cnt_pwron_reset_done_r <= #TCQ 1'b1; cnt_pwron_cke_done_r <= #TCQ 1'b1; end else begin // otherwise, create latched version of done signal for RESET, CKE if (DRAM_TYPE == "DDR3") begin if (!cnt_pwron_reset_done_r) cnt_pwron_reset_done_r <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end else begin // DDR2 cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end end end // else: !if(rst || ~phy_ctl_ready) always @(posedge clk) cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; // Keep RESET asserted and CKE deasserted until after power-on delay always @(posedge clk or posedge rst) begin if (rst) phy_reset_n <= #TCQ 1'b0; else phy_reset_n <= #TCQ cnt_pwron_reset_done_r; // phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; end //***************************************************************** // Counter for tXPR (pronouned "Tax-Payer") - wait time after // CKE deassertion before first MRS command can be asserted //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_txpr_r <= #TCQ 'b0; cnt_txpr_done_r <= #TCQ 1'b0; end else begin cnt_txpr_r <= #TCQ cnt_txpr_r + 1; if (!cnt_txpr_done_r) cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); end //***************************************************************** // Counter for the initial 400ns wait for issuing precharge all // command after CKE assertion. Only for DDR2. //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_init_pre_wait_r <= #TCQ 'b0; cnt_init_pre_wait_done_r <= #TCQ 1'b0; end else begin cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; if (!cnt_init_pre_wait_done_r) cnt_init_pre_wait_done_r <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); end //***************************************************************** // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish // (tZQINIT). Both take the same amount of time (512*tCK) //***************************************************************** always @(posedge clk) if (init_state_r == INIT_ZQCL) begin cnt_dllk_zqinit_r <= #TCQ 'b0; cnt_dllk_zqinit_done_r <= #TCQ 1'b0; end else if (~(phy_ctl_full || phy_cmd_full)) begin cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; if (!cnt_dllk_zqinit_done_r) cnt_dllk_zqinit_done_r <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); end //***************************************************************** // Keep track of which MRS counter needs to be programmed during // memory initialization // The counter and the done signal are reset an additional time // for DDR2. The same signals are used for the additional DDR2 // initialization sequence. //***************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE)|| ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))) begin cnt_init_mr_r <= #TCQ 'b0; cnt_init_mr_done_r <= #TCQ 1'b0; end else if (init_state_r == INIT_LOAD_MR) begin cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); end //***************************************************************** // Flag to tell if the first precharge for DDR2 init sequence is // done //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_pre_flag_r<= #TCQ 'b0; else if (init_state_r == INIT_LOAD_MR) ddr2_pre_flag_r<= #TCQ 1'b1; // reset the flag for multi rank case else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_pre_flag_r <= #TCQ 'b0; //***************************************************************** // Flag to tell if the refresh stat for DDR2 init sequence is // reached //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_refresh_flag_r<= #TCQ 'b0; else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) // reset the flag for multi rank case ddr2_refresh_flag_r<= #TCQ 1'b1; else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_refresh_flag_r <= #TCQ 'b0; //***************************************************************** // Keep track of the number of auto refreshes for DDR2 // initialization. The spec asks for a minimum of two refreshes. // Four refreshes are performed here. The two extra refreshes is to // account for the 200 clock cycle wait between step h and l. // Without the two extra refreshes we would have to have a // wait state. //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) begin cnt_init_af_r <= #TCQ 'b0; cnt_init_af_done_r <= #TCQ 1'b0; end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin cnt_init_af_r <= #TCQ cnt_init_af_r + 1; cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); end //***************************************************************** // Keep track of the register control word programming for // DDR3 RDIMM //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) reg_ctrl_cnt_r <= #TCQ 'b0; else if (init_state_r == INIT_REG_WRITE) reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; generate if (RANKS < 2) begin: one_rank always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end else begin: two_ranks always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse || (rdlvl_stg1_rank_done )) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) rnk_ref_cnt <= #TCQ 1'b0; else if (stg1_wr_done && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; always @(posedge clk) if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) num_refresh <= #TCQ 'd0; else if ((init_state_r == INIT_REFRESH) && (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || (rdlvl_stg1_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) num_refresh <= #TCQ num_refresh + 1; //*************************************************************************** // Initialization state machine //*************************************************************************** //***************************************************************** // Next-state logic //***************************************************************** always @(posedge clk) if (rst)begin init_state_r <= #TCQ INIT_IDLE; init_state_r1 <= #TCQ INIT_IDLE; end else begin init_state_r <= #TCQ init_next_state; init_state_r1 <= #TCQ init_state_r; end always @(*) begin init_next_state = init_state_r; (* full_case, parallel_case *) case (init_state_r) //******************************************************* // DRAM initialization //******************************************************* // Initial state - wait for: // 1. Power-on delays to pass // 2. PHY Control Block to assert phy_ctl_ready // 3. PHY Control FIFO must not be FULL // 4. Read path initialization to finish INIT_IDLE: if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done && ~(phy_ctl_full || phy_cmd_full) ) begin // If skipping memory initialization (simulation only) if (SIM_INIT_OPTION == "SKIP_INIT") //if (WRLVL == "ON") // Proceed to write leveling // init_next_state = INIT_WRLVL_START; //else //if (SIM_CAL_OPTION != "SKIP_CAL") // Proceed to Phaser_In phase lock init_next_state = INIT_RDLVL_ACT; // else // Skip read leveling //init_next_state = INIT_DONE; else init_next_state = INIT_WAIT_CKE_EXIT; end // Wait minimum of Reset CKE exit time (tXPR = max(tXS, INIT_WAIT_CKE_EXIT: if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") && ~(phy_ctl_full || phy_cmd_full)) begin if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || (RANKS > 1))) //register write for reg dimm. Some register chips // have the register chip in a pre-programmed state // in that case the nCS_PER_RANK == 1 && RANKS == 1 init_next_state = INIT_REG_WRITE; else // Load mode register - this state is repeated multiple times init_next_state = INIT_LOAD_MR; end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") && ~(phy_ctl_full || phy_cmd_full)) // DDR2 start with a precharge all command init_next_state = INIT_DDR2_PRECHARGE; INIT_REG_WRITE: init_next_state = INIT_REG_WRITE_WAIT; INIT_REG_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if(reg_ctrl_cnt_r == 4'd8) init_next_state = INIT_LOAD_MR; else init_next_state = INIT_REG_WRITE; end INIT_LOAD_MR: init_next_state = INIT_LOAD_MR_WAIT; // After loading MR, wait at least tMRD INIT_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // If finished loading all mode registers, proceed to next step if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) // for ddr3 when the correct burst length is writtern at end init_next_state = INIT_PRECHARGE; else if (~wrcal_done && temp_lmr_done) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_init_mr_done_r)begin if(DRAM_TYPE == "DDR3") init_next_state = INIT_ZQCL; else begin //DDR2 if(ddr2_refresh_flag_r)begin // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_DDR2_MULTI_RANK; else init_next_state = INIT_RDLVL_ACT; // ddr2 initialization done.load mode state after refresh end else init_next_state = INIT_DDR2_PRECHARGE; end end else init_next_state = INIT_LOAD_MR; end // DDR2 multi rank transition state INIT_DDR2_MULTI_RANK: init_next_state = INIT_DDR2_MULTI_RANK_WAIT; INIT_DDR2_MULTI_RANK_WAIT: init_next_state = INIT_DDR2_PRECHARGE; // Initial ZQ calibration INIT_ZQCL: init_next_state = INIT_WAIT_DLLK_ZQINIT; // Wait until both DLL have locked, and ZQ calibration done INIT_WAIT_DLLK_ZQINIT: if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_LOAD_MR; //else if (WRLVL == "ON") // init_next_state = INIT_WRLVL_START; else // skip write-leveling (e.g. for DDR2 interface) init_next_state = INIT_RDLVL_ACT; // Initial precharge for DDR2 INIT_DDR2_PRECHARGE: init_next_state = INIT_DDR2_PRECHARGE_WAIT; INIT_DDR2_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (ddr2_pre_flag_r) init_next_state = INIT_REFRESH; else // from precharge state initially go to load mode init_next_state = INIT_LOAD_MR; end INIT_REFRESH: if ((SKIP_CALIB == "TRUE") && ~calib_tap_inc_done && pi_dqs_found_done) init_next_state = INIT_SKIP_CALIB_WAIT; else if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) init_next_state = INIT_REFRESH_RNK2_WAIT; else init_next_state = INIT_REFRESH_WAIT; INIT_REFRESH_RNK2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; INIT_REFRESH_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if(cnt_init_af_done_r && (~mem_init_done_r)) // go to lm state as part of DDR2 init sequence init_next_state = INIT_LOAD_MR; // Go to state to issue back-to-back writes during limit check and centering else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin if (num_refresh == 'd8) init_next_state = INIT_OCAL_CENTER_ACT; else init_next_state = INIT_REFRESH; end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 && mem_init_done_r) begin if (num_refresh == 'd8) begin if (BYPASS_COMPLEX_OCAL == "FALSE") init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_WRCAL_ACT; end else init_next_state = INIT_REFRESH; end else if (~pi_dqs_found_done || (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin if (num_refresh == 'd8) init_next_state = INIT_RDLVL_ACT; else init_next_state = INIT_REFRESH; end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRLVL_LOAD_MR2; else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT; else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin if (num_refresh == 'd8) init_next_state = INIT_MPR_RDEN; else init_next_state = INIT_REFRESH; end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) init_next_state = INIT_WRLVL_LOAD_MR2; else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) && pi_dqs_found_done) init_next_state = INIT_WRCAL_ACT; else if (mem_init_done_r) begin if (RANKS < 2) init_next_state = INIT_RDLVL_ACT; else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) init_next_state = INIT_PRECHARGE; else init_next_state = INIT_RDLVL_ACT; end else // to DDR2 init state as part of DDR2 init sequence init_next_state = INIT_REFRESH; end INIT_SKIP_CALIB_WAIT: if (calib_tap_inc_done) init_next_state = INIT_WRCAL_ACT; //****************************************************** // Write Leveling //******************************************************* // Enable write leveling in MR1 and start write leveling // for current rank INIT_WRLVL_START: init_next_state = INIT_WRLVL_WAIT; // Wait for both MR load and write leveling to complete // (write leveling should take much longer than MR load..) INIT_WRLVL_WAIT: if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR; // Disable write leveling in MR1 for current rank INIT_WRLVL_LOAD_MR: init_next_state = INIT_WRLVL_LOAD_MR_WAIT; INIT_WRLVL_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR2; // Load MR2 to set ODT: Dynamic ODT for single rank case // And ODTs for multi-rank case as well INIT_WRLVL_LOAD_MR2: init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; // Wait tMRD before proceeding INIT_WRLVL_LOAD_MR2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin //if (wrlvl_byte_done) // init_next_state = INIT_PRECHARGE_PREWAIT; // else if ((RANKS == 2) && wrlvl_rank_done_r2) // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; if (~wrlvl_done_r1) init_next_state = INIT_WRLVL_START; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skip rdlvl, then we're done init_next_state = INIT_DONE; else // Otherwise, proceed to read leveling //init_next_state = INIT_RDLVL_ACT; init_next_state = INIT_PRECHARGE_PREWAIT; end //******************************************************* // Read Leveling //******************************************************* // single row activate. All subsequent read leveling writes and // read will take place in this row INIT_RDLVL_ACT: init_next_state = INIT_RDLVL_ACT_WAIT; // hang out for awhile before issuing subsequent column commands // it's also possible to reach this state at various points // during read leveling - determine what the current stage is INIT_RDLVL_ACT_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // Just finished an activate. Now either write, read, or precharge // depending on where we are in the training sequence if (!pi_calib_done_r1) init_next_state = INIT_PI_PHASELOCK_READS; else if (!pi_dqs_found_done) // (!pi_dqs_found_start || pi_dqs_found_rank_done)) init_next_state = INIT_RDLVL_STG2_READ; else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) init_next_state = INIT_RDLVL_ACT_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin if (rdlvl_last_byte_done || prbs_last_byte_done) // Added to avoid extra reads at the end of read leveling init_next_state = INIT_RDLVL_ACT_WAIT; else begin // Case 2: If in stage 1, and just precharged after training // previous byte, then continue reading if (rdlvl_stg1_done) init_next_state = INIT_RDLVL_STG1_WRITE_READ; else init_next_state = INIT_RDLVL_STG1_READ; end end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else // Otherwise, if we're finished with calibration, then precharge // the row - silly, because we just opened it - possible to take // this out by adding logic to avoid the ACT in first place. Make // sure that cnt_cmd_done will handle tRAS(min) init_next_state = INIT_PRECHARGE_PREWAIT; end //************************************************** // Back-to-back reads for Phaser_IN Phase locking // DQS to FREQ_REF clock //************************************************** INIT_PI_PHASELOCK_READS: if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) init_next_state = INIT_PRECHARGE_PREWAIT; //********************************************* // Stage 1 read-leveling (write and continuous read) //********************************************* // Write training pattern for stage 1 // PRBS pattern of TBD length INIT_RDLVL_STG1_WRITE: // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words // An entire row worth of writes issued before proceeding to reads // The number of write is (2^column width)/burst length to accomodate // PRBS pattern for window detection. //VCCO/VCCAUX write is not done if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; //back to back write from row1 else if (stg1_wr_rd_cnt == 9'd1) begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) //At the end of the byte, it goes to REFRESH init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; INIT_RDLVL_COMPLEX_PRECHARGE: init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 else if (lim_done && complex_oclkdelay_calib_start_r2) init_next_state = INIT_RDLVL_COMPLEX_ACT; else init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; end else init_next_state = INIT_RDLVL_COMPLEX_ACT; end INIT_RDLVL_COMPLEX_ACT: //only for sampling boundary it need to wait //when initial pi dec is not done in complex per-bit, it need to wait if(prbs_rdlvl_start && (num_samples_done_r || ~complex_init_pi_dec_done)) init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; else init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; //wait PI movement is done before proceeding read INIT_RDLVL_COMPLEX_PI_WAIT: if(complex_pi_incdec_done) init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; INIT_RDLVL_COMPLEX_ACT_WAIT: if (complex_rdlvl_int_ref_req || prech_req_posedge_r) //prech req always happen in this state init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; else if (stg1_wr_done) init_next_state = INIT_RDLVL_COMPLEX_READ; else if (~complex_row1_wr_done) if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end // Write-read turnaround INIT_RDLVL_STG1_WRITE_READ: if (reset_rd_addr_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if (rdlvl_stg1_done_r1) //before going to read, wait for PI inc/dec done init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; else init_next_state = INIT_RDLVL_STG1_READ; end // Continuous read, where interruptible by precharge request from // calibration logic. Also precharges when stage 1 is complete // No precharges when reads provided to Phaser_IN for phase locking // FREQ_REF to read DQS since data integrity is not important. INIT_RDLVL_STG1_READ: if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ: if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; //For back-to-back reads from row1 (ISI pattern) else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_COMPLEX_READ; //********************************************* // DQSFOUND calibration (set of 4 reads with gaps) //********************************************* // Read of training data. Note that Stage 2 is not a constant read, // instead there is a large gap between each set of back-to-back reads INIT_RDLVL_STG2_READ: // 4 read commands issued back-to-back if (num_reads == 'b1) init_next_state = INIT_RDLVL_STG2_READ_WAIT; // Wait before issuing the next set of reads. If a precharge request // comes in then handle - this can occur after stage 2 calibration is // completed for a DQS group INIT_RDLVL_STG2_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (pi_dqs_found_rank_done || pi_dqs_found_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r) init_next_state = INIT_RDLVL_STG2_READ; end //****************************************************************** // MPR Read Leveling for DDR3 OCLK_DELAYED calibration //****************************************************************** // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 // to enable Multi Purpose Register (MPR) Read INIT_MPR_RDEN: init_next_state = INIT_MPR_WAIT; //Wait tMRD, tMOD INIT_MPR_WAIT: if (cnt_cmd_done_r) begin init_next_state = INIT_MPR_READ; end // Issue back-to-back read commands to read from MPR with // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) INIT_MPR_READ: if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) init_next_state = INIT_MPR_DISABLE_PREWAIT; INIT_MPR_DISABLE_PREWAIT: if (cnt_cmd_done_r) init_next_state = INIT_MPR_DISABLE; // Issue Load Mode Register 3 command with A[2]=0 to disable // MPR read INIT_MPR_DISABLE: init_next_state = INIT_MPR_DISABLE_WAIT; INIT_MPR_DISABLE_WAIT: init_next_state = INIT_PRECHARGE_PREWAIT; //*********************************************************************** // OCLKDELAY Calibration //*********************************************************************** // This calibration requires single write followed by single read to // determine the Phaser_Out stage 3 delay required to center write DQS // in write DQ valid window. // Single Row Activate command before issuing Write command INIT_OCLKDELAY_ACT: init_next_state = INIT_OCLKDELAY_ACT_WAIT; INIT_OCLKDELAY_ACT_WAIT: if (cnt_cmd_done_r && ~oclk_prech_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_OCLKDELAY_WRITE: if (oclk_wr_cnt == 4'd1) init_next_state = INIT_OCLKDELAY_WRITE_WAIT; INIT_OCLKDELAY_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else init_next_state = INIT_OCLKDELAY_READ; end INIT_OCLKDELAY_READ: init_next_state = INIT_OCLKDELAY_READ_WAIT; INIT_OCLKDELAY_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r || wrlvl_final || oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; end //********************************************* // Write calibration //********************************************* // single row activate INIT_WRCAL_ACT: init_next_state = INIT_WRCAL_ACT_WAIT; // hang out for awhile before issuing subsequent column command INIT_WRCAL_ACT_WAIT: if (cnt_cmd_done_r && ~wrcal_prech_req) init_next_state = INIT_WRCAL_WRITE; else if (wrcal_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; // Write training pattern for write calibration INIT_WRCAL_WRITE: // Once we've issued enough commands for 8 words - proceed to reads //if (burst_addr_r == 1'b1) if (wrcal_wr_cnt == 4'd1) init_next_state = INIT_WRCAL_WRITE_READ; // Write-read turnaround INIT_WRCAL_WRITE_READ: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRCAL_READ; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; INIT_WRCAL_READ: if (burst_addr_r == 1'b1) init_next_state = INIT_WRCAL_READ_WAIT; INIT_WRCAL_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (wrcal_resume_r) begin if (wrcal_final_chk) init_next_state = INIT_WRCAL_READ; else init_next_state = INIT_WRCAL_WRITE; end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || // Added to support PO fine delay inc when TG errors wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; else if (wrcal_read_req && cnt_wrcal_rd) init_next_state = INIT_WRCAL_MULT_READS; end INIT_WRCAL_MULT_READS: // multiple read commands issued back-to-back if (wrcal_reads == 'b1) init_next_state = INIT_WRCAL_READ_WAIT; //********************************************* // Handling of precharge during and in between read-level stages //********************************************* // Make sure we aren't violating any timing specs by precharging // immediately INIT_PRECHARGE_PREWAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; // Initiate precharge INIT_PRECHARGE: init_next_state = INIT_PRECHARGE_WAIT; INIT_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && (DRAM_TYPE == "DDR2"))) init_next_state = INIT_DONE; else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) init_next_state = INIT_WRCAL_ACT; else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin // after all calibration program the correct burst length init_next_state = INIT_LOAD_MR; // Added to support PO fine delay inc when TG errors end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) init_next_state = INIT_WRCAL_READ_WAIT; else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) // If read leveling finished, proceed to write calibration init_next_state = INIT_REFRESH; else // Otherwise, open row for read-leveling purposes init_next_state = INIT_REFRESH; end //******************************************************* // COMPLEX OCLK calibration - for fragmented write //******************************************************* INIT_OCAL_COMPLEX_ACT: init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; INIT_OCAL_COMPLEX_ACT_WAIT: if (complex_wait_cnt =='d15) init_next_state = INIT_RDLVL_STG1_WRITE; INIT_OCAL_COMPLEX_WRITE_WAIT: if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_STG1_WRITE; //wait for all srg2/stg3 tap movement is done and go back to write again INIT_OCAL_COMPLEX_RESUME_WAIT: if (complex_oclk_calib_resume) init_next_state = INIT_RDLVL_STG1_WRITE; else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) init_next_state = INIT_PRECHARGE_PREWAIT; //******************************************************* // OCAL STG3 Centering calibration //******************************************************* INIT_OCAL_CENTER_ACT: init_next_state = INIT_OCAL_CENTER_ACT_WAIT; INIT_OCAL_CENTER_ACT_WAIT: if (ocal_act_wait_cnt == 'd15) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE: if(!oclk_center_write_resume && !lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE_WAIT: //if (oclkdelay_center_calib_done || prech_req_posedge_r) if (prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCLKDELAY_READ_WAIT; else if (oclk_center_write_resume || lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE; //******************************************************* // Initialization/Calibration done. Take a long rest, relax //******************************************************* INIT_DONE: init_next_state = INIT_DONE; endcase end //***************************************************************** // Initialization done signal - asserted before leveling starts //***************************************************************** always @(posedge clk) if (rst) mem_init_done_r <= #TCQ 1'b0; else if ((!cnt_dllk_zqinit_done_r && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) || ( (init_state_r == INIT_LOAD_MR_WAIT) && (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) mem_init_done_r <= #TCQ 1'b1; //***************************************************************** // Write Calibration signal to PHY Control Block - asserted before // Write Leveling starts //***************************************************************** //generate //if (RANKS < 2) begin: ranks_one always @(posedge clk) begin if (rst || (done_dqs_tap_inc && (init_state_r == INIT_WRLVL_LOAD_MR2))) write_calib <= #TCQ 1'b0; else if (wrlvl_active_r1) write_calib <= #TCQ 1'b1; end //end else begin: ranks_two // always @(posedge clk) begin // if (rst || // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || // (SIM_CAL_OPTION == "FAST_CAL")))) // write_calib <= #TCQ 1'b0; // else if (wrlvl_active_r1) // write_calib <= #TCQ 1'b1; // end //end //endgenerate //***************************************************************** // Read Calibration signal to PHY Control Block - asserted after // Write Leveling during PHASER_IN phase locking stage. // Must be de-asserted before Read Leveling //***************************************************************** always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib_int <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && (cnt_cmd_r == CNTNEXT_CMD)) read_calib_int <= #TCQ 1'b1; end always @(posedge clk) read_calib_r <= #TCQ read_calib_int; always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) read_calib <= #TCQ 1'b1; end always @(posedge clk) if (rst) pi_calib_done_r <= #TCQ 1'b0; else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) pi_calib_done_r <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_calib_rank_done_r <= #TCQ 1'b0; else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) pi_calib_rank_done_r <= #TCQ 1'b1; else pi_calib_rank_done_r <= #TCQ 1'b0; always @(posedge clk) begin if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) pi_phaselock_timer <= #TCQ 'd0; else if (((init_state_r == INIT_PI_PHASELOCK_READS) && (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || tg_timer_go) pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; else pi_phaselock_timer <= #TCQ pi_phaselock_timer; end assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; //***************************************************************** // DDR3 final burst length programming done. For DDR3 during // calibration the burst length is fixed to BL8. After calibration // the correct burst length is programmed. //***************************************************************** always @(posedge clk) if (rst) ddr3_lm_done_r <= #TCQ 1'b0; else if ((init_state_r == INIT_LOAD_MR_WAIT) && (chip_cnt_r == RANKS-1) && wrcal_done) ddr3_lm_done_r <= #TCQ 1'b1; always @(posedge clk) begin pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; pi_calib_done_r1 <= #TCQ pi_calib_done_r; end //*************************************************************************** // Logic for deep memory (multi-rank) configurations //*************************************************************************** // For DDR3 asserted when generate if (RANKS < 2) begin: single_rank always @(posedge clk) chip_cnt_r <= #TCQ 2'b00; end else begin: dual_rank always @(posedge clk) if (rst || // Set chip_cnt_r to 2'b00 after both Ranks are read leveled (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done && (SKIP_CALIB == "FALSE")) || // Set chip_cnt_r to 2'b00 after both Ranks are write leveled (wrlvl_done_r && (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin chip_cnt_r <= #TCQ 2'b00; end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && (DRAM_TYPE == "DDR3")) || ((init_state_r==INIT_REFRESH_RNK2_WAIT) && (cnt_cmd_r=='d36)) || //mpr_rnk_done || //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || //(stg1_wr_done && (init_state_r == INIT_REFRESH) && //~(rnk_ref_cnt && rdlvl_last_byte_done)) || // Increment chip_cnt_r to issue Refresh to second rank (~pi_dqs_found_all_r && (init_state_r==INIT_PRECHARGE_PREWAIT) && (cnt_cmd_r=='d36) && (SKIP_CALIB == "FALSE")) || // Increment chip_cnt_r when DQSFOUND done for the Rank (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r && (SKIP_CALIB == "FALSE")) || ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r && wrcal_done) || ((init_state_r == INIT_DDR2_MULTI_RANK) && (DRAM_TYPE == "DDR2"))) begin if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || // condition to increment chip_cnt during // final burst length programming for DDR3 ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || && (chip_cnt_r != RANKS-1)) chip_cnt_r <= #TCQ chip_cnt_r + 1; else chip_cnt_r <= #TCQ 2'b00; end end endgenerate // verilint STARC-2.2.3.3 off generate if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if (RANKS == 1) begin: DDR3_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin //odd CWL for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[1] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end end else if (RANKS == 2) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin // odd CWL for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin phy_int_cs_n[q] <= #TCQ 1'b0; end end else begin // odd CWL for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin phy_int_cs_n[m] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end // always @ (posedge clk) end // verilint STARC-2.2.3.3 on // commented out for now. Need it for DDR2 2T timing /* end else begin: DDR2 always @(posedge clk) if (rst) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end else begin if (init_state_r == INIT_REG_WRITE) begin // All ranks selected simultaneously phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; end else if ((wrlvl_odt) || (init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH)) begin phy_int_cs_n[0] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end // else: !if(rst) end // block: DDR2 */ endgenerate assign phy_cs_n = phy_int_cs_n; //*************************************************************************** // Write/read burst logic for calibration //*************************************************************************** assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE); assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || ((init_state_r == INIT_RDLVL_STG1_READ) && ~rdlvl_pi_incdec) || //rdlvl pi dec (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || ((init_state_r == INIT_MPR_READ) && ~rdlvl_pi_incdec) || (init_state_r == INIT_WRCAL_MULT_READS); assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering // assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); //*************************************************************************** // Address generation and logic to count # of writes/reads issued during // certain stages of calibration //*************************************************************************** // Column address generation logic: // Keep track of the current column address - since all bursts are in // increments of 8 only during calibration, we need to keep track of // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 always @(posedge clk) if (rst || wrcal_done) burst_addr_r <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_WRCAL_READ_WAIT)) burst_addr_r <= #TCQ 1'b1; else if (rdlvl_wr_rd && new_burst_r) burst_addr_r <= #TCQ ~burst_addr_r; else burst_addr_r <= #TCQ 1'b0; // Read Level Stage 1 requires writes to the entire row since // a PRBS pattern is being written. This counter keeps track // of the number of writes which depends on the column width // The (stg1_wr_rd_cnt==9'd0) condition was added so the col // address wraps around during stage1 reads always @(posedge clk) if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ~rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin if (~complex_row0_wr_done || wr_victim_inc || (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) stg1_wr_rd_cnt <= #TCQ 'd127; else stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; always @(posedge clk) if (rst) wr_victim_inc <= #TCQ 1'b0; else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) wr_victim_inc <= #TCQ 1'b1; else wr_victim_inc <= #TCQ 1'b0; always @(posedge clk) reset_rd_addr_r1 <= #TCQ reset_rd_addr; generate if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if ((complex_row_cnt < DQ_PER_DQS*2-1) && ~stg1_wr_done) complex_row_cnt <= #TCQ complex_row_cnt + 1; // During reads row count requires different conditions for increments else if (stg1_wr_done) begin if (reset_rd_addr_r1) complex_row_cnt <= #TCQ 'd0; // When looping multiple times in the same victim bit in a byte else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) complex_row_cnt <= #TCQ rd_victim_sel*2; // When looping through victim bits within a byte else if (complex_row_cnt < DQ_PER_DQS*2-1) complex_row_cnt <= #TCQ complex_row_cnt + 1; // When the number of samples is done and tap is incremented within a byte else complex_row_cnt <= #TCQ 'd0; end end end else begin: row_cnt_victim_fixed always @(posedge clk) if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) complex_row_cnt <= #TCQ 'd1; else complex_row_cnt <= #TCQ 'd0; end endgenerate //row count always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) complex_row_cnt_ocal <= #TCQ 'd0; else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; end end always @(posedge clk) if (rst) complex_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_odt_ext <= #TCQ 1'b0; else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) complex_odt_ext <= #TCQ 1'b1; always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1))) begin wr_victim_sel <= #TCQ 'd0; end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin wr_victim_sel <= #TCQ wr_victim_sel + 1; end always @(posedge clk) if (rst) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (prbs_rdlvl_done && wr_victim_inc) begin wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; end always @(posedge clk) if (rst) begin victim_sel <= #TCQ 'd0; victim_byte_cnt <= #TCQ 'd0; end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; victim_byte_cnt <= #TCQ 'd0; end else begin if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; victim_byte_cnt <= #TCQ 'd0; end generate if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_PER_DQS*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal 'd85) begin if (complex_num_reads < 'd6) complex_num_reads <= #TCQ complex_num_reads + 1; else complex_num_reads <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_reads <= #TCQ 'd3; else if (complex_num_reads < 'd5) complex_num_reads <= #TCQ complex_num_reads + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_reads <= #TCQ 'd7; else if (complex_num_reads < 'd10) complex_num_reads <= #TCQ complex_num_reads + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_reads <= #TCQ 'd12; else if (complex_num_reads < 'd14) complex_num_reads <= #TCQ complex_num_reads + 1; end // Initialize to 1 at the start of reads or after precharge and activate end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) complex_num_reads <= #TCQ 'd1; always @(posedge clk) if (rst) complex_num_reads_dec <= #TCQ 'd1; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_reads_dec <= #TCQ complex_num_reads; else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; always @(posedge clk) if (rst) complex_address <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; always @ (posedge clk) if (rst) complex_oclkdelay_calib_start_int <= #TCQ 'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 complex_oclkdelay_calib_start_int <= #TCQ 'b1; always @(posedge clk) begin complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_start <= #TCQ 'b0; else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 complex_oclkdelay_calib_start <= #TCQ 'b1; //packet fragmentation for complex oclkdealy calib write always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) begin complex_num_writes <= #TCQ 'd1; end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_writes < 'd6) complex_num_writes <= #TCQ complex_num_writes + 1; else complex_num_writes <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_writes <= #TCQ 'd3; else if (complex_num_writes < 'd5) complex_num_writes <= #TCQ complex_num_writes + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_writes <= #TCQ 'd7; else if (complex_num_writes < 'd10) complex_num_writes <= #TCQ complex_num_writes + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_writes <= #TCQ 'd12; else if (complex_num_writes < 'd14) complex_num_writes <= #TCQ complex_num_writes + 1; end // Initialize to 1 at the start of write or after precharge and activate end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) complex_num_writes <= #TCQ 'd30; else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) complex_num_writes <= #TCQ 'd1; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_num_writes_dec <= #TCQ 'd1; else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_writes_dec <= #TCQ complex_num_writes; else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; always @(posedge clk) if (rst) complex_sample_cnt_inc_ocal <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) complex_sample_cnt_inc_ocal <= #TCQ 1'b1; else complex_sample_cnt_inc_ocal <= #TCQ 1'b0; always @(posedge clk) if (rst) complex_sample_cnt_inc <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) complex_sample_cnt_inc <= #TCQ 1'b1; else complex_sample_cnt_inc <= #TCQ 1'b0; always @(posedge clk) begin complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; end //complex refresh req always @ (posedge clk) begin if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) complex_ocal_ref_done <= #TCQ 1'b1; else if (init_state_r == INIT_RDLVL_STG1_WRITE) complex_ocal_ref_done <= #TCQ 1'b0; end //complex ocal odt extention always @(posedge clk) if (rst) complex_ocal_odt_ext <= #TCQ 1'b0; else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b1; // OCLKDELAY calibration requires multiple writes because // write can be up to 2 cycles early since OCLKDELAY tap // can go down to 0 always @(posedge clk) if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || (oclk_wr_cnt == 4'd0)) oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_OCLKDELAY_WRITE) && new_burst_r && ~phy_data_full) oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; // Write calibration requires multiple writes because // write can be up to 2 cycles early due to new write // leveling algorithm to avoid late writes always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || (wrcal_wr_cnt == 4'd0)) wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_WRCAL_WRITE) && new_burst_r && ~phy_data_full) wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; generate if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b011; end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b111; end endgenerate // back-to-back reads during write calibration always @(posedge clk) if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) wrcal_reads <= #TCQ 2'b00; else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) wrcal_reads <= #TCQ wrcal_reads - 1; else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || phy_cmd_full && new_burst_r) wrcal_reads <= #TCQ 'd255; // determine how often to issue row command during read leveling writes // and reads always @(posedge clk) if (rdlvl_wr_rd) begin // 2:1 mode - every other command issued is a data command // 4:1 mode - every command issued is a data command if (nCK_PER_CLK == 2) begin if (!phy_ctl_full) new_burst_r <= #TCQ ~new_burst_r; end else new_burst_r <= #TCQ 1'b1; end else new_burst_r <= #TCQ 1'b1; // indicate when a write is occurring. PHY_WRDATA_EN must be asserted // simultaneous with the corresponding command/address for CWL = 5,6 always @(posedge clk) begin rdlvl_wr_r <= #TCQ rdlvl_wr; calib_wrdata_en <= #TCQ phy_wrdata_en; end always @(posedge clk) begin if (rst || wrcal_done) extend_cal_pat <= #TCQ 1'b0; else if (temp_lmr_done && (PRE_REV3ES == "ON")) extend_cal_pat <= #TCQ 1'b1; end generate if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 // Write data enable asserted for one DIV4 clock cycle // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. always @(*) begin if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_WRCAL_WRITE))) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; end end else begin: wrdqen_div2 // block: wrdqen_div4 always @(*) if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) | phy_wrdata_en_r1) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; always @(posedge clk) phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full; always @(posedge clk) begin if (!phy_wrdata_en & first_rdlvl_pat_r) wrdata_pat_cnt <= #TCQ 2'b00; else if (wrdata_pat_cnt == 2'b11) wrdata_pat_cnt <= #TCQ 2'b10; else wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; end always @(posedge clk) begin if (!phy_wrdata_en & first_wrcal_pat_r) wrcal_pat_cnt <= #TCQ 2'b00; else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) wrcal_pat_cnt <= #TCQ 2'b00; else if (wrcal_pat_cnt == 2'b11) wrcal_pat_cnt <= #TCQ 2'b10; else wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; end end endgenerate // indicate when a write is occurring. PHY_RDDATA_EN must be asserted // simultaneous with the corresponding command/address. PHY_RDDATA_EN // is used during read-leveling to determine read latency assign phy_rddata_en = ~phy_if_empty; // Read data valid generation for MC and User Interface after calibration is // complete assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; //*************************************************************************** // Generate training data written at start of each read-leveling stage // For every stage of read leveling, 8 words are written into memory // The format is as follows (shown as {rise,fall}): // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 //*************************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE) || (init_state_r == INIT_RDLVL_STG1_WRITE)) cnt_init_data_r <= #TCQ 2'b00; else if (phy_wrdata_en) cnt_init_data_r <= #TCQ cnt_init_data_r + 1; else if (init_state_r == INIT_WRCAL_WRITE) cnt_init_data_r <= #TCQ 2'b10; // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling always @(posedge clk) if (rst || rdlvl_stg1_rank_done) first_rdlvl_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) first_rdlvl_pat_r <= #TCQ 1'b0; always @(posedge clk) if (rst || wrcal_resume || (init_state_r == INIT_WRCAL_ACT_WAIT)) first_wrcal_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) first_wrcal_pat_r <= #TCQ 1'b0; generate if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!wrcal_done) begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done && ~phy_data_full) // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!wrcal_done) if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin if (extend_cal_pat) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!rdlvl_stg1_done && ~phy_data_full) begin // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!prbs_rdlvl_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!complex_oclkdelay_calib_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; end else begin: wrdq_div1_2to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; end end endgenerate //*************************************************************************** // Memory control/address //*************************************************************************** // Phases [2] and [3] are always deasserted for 4:1 mode generate if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff always @(posedge clk) begin phy_ras_n[3:2] <= #TCQ 3'b11; phy_cas_n[3:2] <= #TCQ 3'b11; phy_we_n[3:2] <= #TCQ 3'b11; end end endgenerate // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging // (4) auto refresh // verilint STARC-2.7.3.3b off generate if (!(CWL_M % 2)) begin: even_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin phy_ras_n[0] <= #TCQ 1'b0; phy_ras_n[1] <= #TCQ 1'b1; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b0; phy_cas_n[1] <= #TCQ 1'b1; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b0; phy_we_n[1] <= #TCQ 1'b1; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end else begin: odd_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_REFRESH))begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b0; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b0; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b0; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.7.3.3b on // Assign calib_cmd for the command field in PHY_Ctl_Word always @(posedge clk) begin if (wr_level_dqs_asrt) begin // Request to toggle DQS during write leveling calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ CWL_M + 3; calib_data_offset_1 <= #TCQ CWL_M + 3; calib_data_offset_2 <= #TCQ CWL_M + 3; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ CWL_M + 2; calib_data_offset_1 <= #TCQ CWL_M + 2; calib_data_offset_2 <= #TCQ CWL_M + 2; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_wr && new_burst_r) begin // Write Command calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_rd && new_burst_r) begin // Read Command calib_cmd <= #TCQ 3'b011; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; if (~pi_calib_done_r1) begin calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; end else if (~pi_dqs_found_done_r1) begin calib_data_offset_0 <= #TCQ rd_data_offset_0; calib_data_offset_1 <= #TCQ rd_data_offset_1; calib_data_offset_2 <= #TCQ rd_data_offset_2; end else begin calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; end end else begin // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, // Active, Refresh calib_cmd <= #TCQ 3'b100; calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; end end // Write Enable to PHY_Control FIFO always asserted // No danger of this FIFO being Full with 4:1 sync clock ratio // This is also the write enable to the command OUT_FIFO always @(posedge clk) begin if (rst) begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ 2'b00; end else if (cnt_pwron_cke_done_r && phy_ctl_ready && ~(phy_ctl_full || phy_cmd_full )) begin calib_ctl_wren <= #TCQ 1'b1; calib_cmd_wren <= #TCQ 1'b1; calib_seq <= #TCQ calib_seq + 1; end else begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ calib_seq; end end generate genvar rnk_i; for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk always @(posedge clk) begin if (rst) begin mr2_r[rnk_i] <= #TCQ 2'b00; mr1_r[rnk_i] <= #TCQ 3'b000; end else begin mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; end end end endgenerate // ODT assignment based on slot config and slot present // For single slot systems slot_1_present input will be ignored // Assuming component interfaces to be single slot systems generate if (nSLOTS == 1) begin: gen_single_slot_odt always @(posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_0_present[2],slot_0_present[3]}) // Single slot configuration with quad rank // Assuming same behavior as single slot dual rank for now // DDR2 does not have quad rank parts 4'b1111: begin if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; end // Single slot configuration with single rank 4'b1000: begin phy_tmp_odt_r <= #TCQ 4'b0001; if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; end else begin phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; end if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Single slot configuration with dual rank 4'b1100: begin phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end default: begin phy_tmp_odt_r <= #TCQ 4'b0001; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end endcase end end end else if (nSLOTS == 2) begin: gen_dual_slot_odt always @ (posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_1_present[0],slot_1_present[1]}) // Two slot configuration, one slot present, single rank 4'b10_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b00_10: begin //Rank1 ODT enabled if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM defaults to 120 ohms tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one slot present, dual rank 4'b00_11: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b11_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one rank per slot 4'b10_10: begin if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; //bit0 for rank0 end else begin phy_tmp_odt_r <= #TCQ 4'b0001; //bit0 for rank0 end end else begin if((init_state_r == INIT_WRLVL_WAIT) || (init_next_state == INIT_RDLVL_STG1_WRITE) || (init_next_state == INIT_WRCAL_WRITE) || (init_next_state == INIT_OCAL_CENTER_WRITE) || (init_next_state == INIT_OCLKDELAY_WRITE)) phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) else if ((init_next_state == INIT_PI_PHASELOCK_READS) || (init_next_state == INIT_MPR_READ) || (init_next_state == INIT_RDLVL_STG1_READ) || (init_next_state == INIT_RDLVL_COMPLEX_READ) || (init_next_state == INIT_RDLVL_STG2_READ) || (init_next_state == INIT_OCLKDELAY_READ) || (init_next_state == INIT_WRCAL_READ) || (init_next_state == INIT_WRCAL_MULT_READS)) phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : (RTT_WR == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end // Two Slots - One slot with dual rank and other with single rank 4'b10_11: begin //Rank3 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; end //Slot1 Rank1 or Rank3 is being written if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0011; //Slot0 Rank0 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin if (chip_cnt_r == 2'b00) begin phy_tmp_odt_r <= #TCQ 4'b0100; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - One slot with dual rank and other with single rank 4'b11_10: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011: 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011: 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; // rank 2 ODT asserted end end else begin if (// wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; end else begin phy_tmp_odt_r <= #TCQ 4'b0101; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - two ranks per slot 4'b11_11: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011 : 3'b000; //Rank3 Rtt_NOM tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : (RTT_NOM3 == "120") ? 3'b010 : (RTT_NOM3 == "20") ? 3'b100 : (RTT_NOM3 == "30") ? 3'b101 : (RTT_NOM3 == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin //Slot1 Rank1 or Rank3 is being written if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; //Slot0 Rank0 or Rank2 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b1001; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin //Slot1 Rank1 or Rank3 is being read if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0100; //Slot0 Rank0 or Rank2 is being read end else begin phy_tmp_odt_r <= #TCQ 4'b1000; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end default: begin phy_tmp_odt_r <= #TCQ 4'b1111; // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "60") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end endcase end end end endgenerate // PHY only supports two ranks. // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 generate if(CKE_ODT_AUX == "FALSE") begin if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Quad rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Dual rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || ((DRAM_TYPE == "DDR3") && (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))) begin if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // disable well before next command and before disabling write leveling end else if(cnt_cmd_done_m7_r || (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) calib_odt <= #TCQ 2'b00; end end end else begin//USE AUX OUTPUT for routing CKE and ODT. if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Dual rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst) calib_aux_out <= #TCQ 4'b0000; else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_aux_out[1] <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; calib_aux_out[3] <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end end endgenerate //***************************************************************** // memory address during init //***************************************************************** always @(posedge clk) phy_data_full_r <= #TCQ phy_data_full; // verilint STARC-2.7.3.3b off always @(*)begin // Bus 0 for address/bank never used address_w = 'b0; bank_w = 'b0; if ((init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_DDR2_PRECHARGE)) begin // Set A10=1 for ZQ long calibration or Precharge All address_w = 'b0; address_w[10] = 1'b1; bank_w = 'b0; end else if (init_state_r == INIT_WRLVL_START) begin // Enable wrlvl in MR1 bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; address_w[7] = 1'b1; end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin // Finished with write leveling, disable wrlvl in MR1 // For single rank disable Rtt_Nom bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin // Set RTT_WR in MR2 after write leveling disabled bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end else if (init_state_r == INIT_MPR_READ) begin address_w = 'b0; bank_w = 'b0; end else if (init_state_r == INIT_MPR_RDEN) begin // Enable MPR read with LMR3 and A2=1 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; address_w[2] = 1'b1; end else if (init_state_r == INIT_MPR_DISABLE) begin // Disable MPR read with LMR3 and A2=0 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; end else if ((init_state_r == INIT_REG_WRITE)& (DRAM_TYPE == "DDR3"))begin // bank_w is assigned a 3 bit value. In some // DDR2 cases there will be only two bank bits. //Qualifying the condition with DDR3 bank_w = 'b0; address_w = 'b0; case (reg_ctrl_cnt_r) 4'h1:begin address_w[4:0] = REG_RC1[4:0]; bank_w = REG_RC1[7:5]; end 4'h2: address_w[4:0] = REG_RC2[4:0]; 4'h3: begin address_w[4:0] = REG_RC3[4:0]; bank_w = REG_RC3[7:5]; end 4'h4: begin address_w[4:0] = REG_RC4[4:0]; bank_w = REG_RC4[7:5]; end 4'h5: begin address_w[4:0] = REG_RC5[4:0]; bank_w = REG_RC5[7:5]; end 4'h6: begin address_w[4:0] = REG_RC10[4:0]; bank_w = REG_RC10[7:5]; end 4'h7: begin address_w[4:0] = REG_RC11[4:0]; bank_w = REG_RC11[7:5]; end default: address_w[4:0] = REG_RC0[4:0]; endcase end else if (init_state_r == INIT_LOAD_MR) begin // If loading mode register, look at cnt_init_mr to determine // which MR is currently being programmed address_w = 'b0; bank_w = 'b0; if(DRAM_TYPE == "DDR3")begin if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin // end of the calibration programming correct // burst length if (TEST_AL == "0") begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //Don't reset DLL end else begin // programming correct AL value bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if (TEST_AL == "CL-1") address_w[4:3]= 2'b01; // AL="CL-1" else address_w[4:3]= 2'b10; // AL="CL-2" end end else begin case (cnt_init_mr_r) INIT_CNT_MR2: begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end INIT_CNT_MR3: begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end INIT_CNT_MR0: begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; // fixing it to BL8 for calibration address_w[1:0] = 2'b00; end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else begin // DDR2 case (cnt_init_mr_r) INIT_CNT_MR2: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL end end INIT_CNT_MR3: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL. Repeted again // because there is an extra state. end end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; if(~ddr2_refresh_flag_r)begin address_w = load_mr1[ROW_WIDTH-1:0]; end else begin // second set of lm commands address_w = load_mr1[ROW_WIDTH-1:0]; address_w[9:7] = 3'b111; //OCD default state end end INIT_CNT_MR0: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin // always disable odt for rank 1 and rank 3 as per SPEC address_w[2] = 'b0; address_w[6] = 'b0; end //OCD exit end end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin // Writing and reading PRBS pattern for read leveling stage 1 // Need to support burst length 4 or 8. PRBS pattern will be // written to entire row and read back from the same row repeatedly bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end //need to add address for complex oclkdelay calib end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (oclk_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (wrcal_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_RDLVL_STG2_READ)) begin // when writing or reading back training pattern for read leveling stage2 // need to support burst length of 4 or 8. This may mean issuing // multiple commands to cover the entire range of addresses accessed // during read leveling. // Hard coding A[12] to 1 so that it will always be burst length of 8 // for DDR3. Does not have any effect on DDR2. bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; address_w[COL_WIDTH-1:0] = {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; address_w[12] = 1'b1; end else if ((init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; //if (stg1_wr_rd_cnt == 'd22) // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; //else address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; end else begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end end // verilint STARC-2.7.3.3b on // registring before sending out generate genvar r,s; if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop always @(posedge clk) begin phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; end end end else begin: gen_mirror // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) // Mirror for the 2nd rank only. Logic needs to be enhanced to account // for multiple slots, currently only supports one slot, 2-rank config for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; end else begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; end end end for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; end else begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ (s == 3) ? 4 : ((s == 4) ? 3 : ((s == 5) ? 6 : ((s == 6) ? 5 : ((s == 7) ? 8 : ((s == 8) ? 7 : s)))))]; end end end end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Steps through the major sections of the output clock // delay algorithm. Enabling various subblocks at the right time. // // Steps through each byte of the interface. // // Implements both the simple and complex data pattern. // // for each byte in interface // begin // Limit // Scan - which includes DQS centering // Precharge // end // set _wrlvl and _done equal to one // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_cntlr # (parameter TCQ = 100, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8) (/*AUTOARG*/ // Outputs wrlvl_final, complex_wrlvl_final, oclk_init_delay_done, ocd_prech_req, lim_start, complex_oclkdelay_calib_done, oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt, reset_scan, // Inputs clk, rst, prech_done, oclkdelay_calib_start, complex_oclkdelay_calib_start, lim_done, phy_rddata_en, po_counter_read_val, po_rdy, scan_done ); localparam ONE = 1; input clk; input rst; output wrlvl_final, complex_wrlvl_final; reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns; always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns; assign wrlvl_final = wrlvl_final_r; assign complex_wrlvl_final = complex_wrlvl_final_r; // Completed initial delay increment output oclk_init_delay_done; // may not need this... maybe for fast cal mode. assign oclk_init_delay_done = 1'b1; // Precharge done status from ddr_phy_init input prech_done; reg ocd_prech_req_ns, ocd_prech_req_r; always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns; output ocd_prech_req; assign ocd_prech_req = ocd_prech_req_r; input oclkdelay_calib_start, complex_oclkdelay_calib_start; input lim_done; reg lim_start_ns, lim_start_r; always @(posedge clk) lim_start_r <= #TCQ lim_start_ns; output lim_start; assign lim_start = lim_start_r; reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r; always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns; output complex_oclkdelay_calib_done; assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r; reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r; always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns; output oclkdelay_calib_done; assign oclkdelay_calib_done = oclkdelay_calib_done_r; input phy_rddata_en; reg prde_r1, prde_r2; always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en; always @(posedge clk) prde_r2 <= #TCQ prde_r1; wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en; reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3; always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde; always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1; always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2; output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3; assign phy_rddata_en_1 = phy_rddata_en_r1; assign phy_rddata_en_2 = phy_rddata_en_r2; assign phy_rddata_en_3 = phy_rddata_en_r3; input [8:0] po_counter_read_val; reg ocd_cntlr2stg2_dec_r; output ocd_cntlr2stg2_dec; assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r; input po_rdy; reg [3:0] po_rd_wait_ns, po_rd_wait_r; always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns; reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r; always @(posedge clk) byte_r <= #TCQ byte_ns; output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; assign oclkdelay_calib_cnt = {1'b0, byte_r}; reg reset_scan_ns, reset_scan_r; always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns; output reset_scan; assign reset_scan = reset_scan_r; input scan_done; reg [2:0] sm_ns, sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; // Primary state machine. always @(*) begin // Default next state assignments. byte_ns = byte_r; complex_wrlvl_final_ns = complex_wrlvl_final_r; lim_start_ns = lim_start_r; oclkdelay_calib_done_ns = oclkdelay_calib_done_r; complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r; ocd_cntlr2stg2_dec_r = 1'b0; po_rd_wait_ns = po_rd_wait_r; if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1; reset_scan_ns = reset_scan_r; wrlvl_final_ns = wrlvl_final_r; sm_ns = sm_r; ocd_prech_req_ns= 1'b0; if (rst == 1'b1) begin // RESET next states complex_oclkdelay_calib_done_ns = 1'b0; complex_wrlvl_final_ns = 1'b0; sm_ns = /*AK("READY")*/3'd0; lim_start_ns = 1'b0; oclkdelay_calib_done_ns = 1'b0; reset_scan_ns = 1'b1; wrlvl_final_ns = 1'b0; end else // State based actions and next states. case (sm_r) /*AL("READY")*/3'd0: begin byte_ns = {DQS_CNT_WIDTH{1'b0}}; if (oclkdelay_calib_start && ~oclkdelay_calib_done_r || complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r) begin sm_ns = /*AK("LIMIT_START")*/3'd1; lim_start_ns = 1'b1; end end /*AL("LIMIT_START")*/3'd1: sm_ns = /*AK("LIMIT_WAIT")*/3'd2; /*AL("LIMIT_WAIT")*/3'd2:begin if (lim_done) begin lim_start_ns = 1'b0; sm_ns = /*AK("SCAN")*/3'd3; reset_scan_ns = 1'b0; end end /*AL("SCAN")*/3'd3:begin if (scan_done) begin reset_scan_ns = 1'b1; sm_ns = /*AK("COMPUTE")*/3'd4; end end /*AL("COMPUTE")*/3'd4:begin sm_ns = /*AK("PRECHARGE")*/3'd5; ocd_prech_req_ns = 1'b1; end /*AL("PRECHARGE")*/3'd5:begin if (prech_done) sm_ns = /*AK("DONE")*/3'd6; end /*AL("DONE")*/3'd6:begin byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0]; if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin byte_ns = {DQS_CNT_WIDTH{1'b0}}; po_rd_wait_ns = 4'd8; sm_ns = /*AK("STG2_2_ZERO")*/3'd7; end else begin sm_ns = /*AK("LIMIT_START")*/3'd1; lim_start_ns = 1'b1; end end /*AL("STG2_2_ZERO")*/3'd7: if (~|po_rd_wait_r && po_rdy) if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1; else begin if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin sm_ns = /*AK("READY")*/3'd0; oclkdelay_calib_done_ns= 1'b1; wrlvl_final_ns = 1'b1; if (complex_oclkdelay_calib_start) begin complex_oclkdelay_calib_done_ns = 1'b1; complex_wrlvl_final_ns = 1'b1; end end else begin byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0]; po_rd_wait_ns = 4'd8; end end // else: !if(|po_counter_read_val[5:0]) endcase // case (sm_r) end // always @ begin endmodule // mig_7series_v4_0_ddr_phy_ocd_cntlr // Local Variables: // verilog-autolabel-prefix: "3'd" // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v4_0_phy_ocd_data.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Data comparison for both "non-complex" and "complex" data. // // Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata // bus is compared against a fixed ones and zeros pattern, or against data // provided on the prob_o bus. // // In the case of complex data, the phy_rddata data is delayed by two // clocks to match up with the prbs_o data. // // For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered. // A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ // bus, 64 bytes are delivered on each clock. // // In 2:1 mode the DRAM burst is delivered on two fabric clocks. For // an 8 byte bus, 32 bytes are delivered with each fabric clock. // // For the most part, this block does not use phy_rddata_en. It delivers // its results and depends on downstream logic to know when its valid. // // phy_rddata_en is used for the PRBS compares when the last line of data // needs to be carried over to a subsequent line. // // Since we work on a byte at a time, the comparison only works on // one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to // select the proper 8 bytes out of both the phy_rddata and prob_o streams. // // Comparisons are computed for "zero" or "rise" data, and "oneeighty" or // "fall" data. The "oneeighty" compares assumes the rising edge clock is // landing in the oneeighty data. // // For the simple data, we don't need to worry about first byte or last // byte conditions because the sampled data is taken from the middle // of a 4 burst segment. // // The complex (or PRBS) data starts and stops. And we need to be // careful about ignoring compares that might be using invalid latched // data. The PRBS generator provides prbs_ignore_first_byte and // prbs_ignore_last_bytes. The comparison block is procedural. It // first compares across the entire line, then comes back and overwrites // any byte compare results as indicated by the _ignore_ wires. // // The compares generate an eight bit vector, one for each byte. The // final step is to bitwise AND this eight bit vector. We end up // with two sets of two bits. Zero and oneeighty for the fixed pattern // and the prbs. // // complex_oclkdelay_calib_start is used to // select between the fixed and prbs compares. The final output // is a two bit match bus. // // There is a deprecated feature to mask the compare for any byte. // // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_data # (parameter TCQ = 100, parameter nCK_PER_CLK = 4, parameter DQS_CNT_WIDTH = 3, parameter DQ_WIDTH = 64) (/*AUTOARG*/ // Outputs match, // Inputs clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o, oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes, phy_rddata_en_1 ); localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000; input clk; input rst; input complex_oclkdelay_calib_start; input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata; input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; reg [DQ_WIDTH-1:0] word, word_shifted; reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r; always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns; always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r; always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1; always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns; input prbs_ignore_first_byte, prbs_ignore_last_bytes; reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r; always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte; always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes; input phy_rddata_en_1; reg [7:0] last_byte_r; wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r; wire [7:0] last_byte_ns; generate if (nCK_PER_CLK == 4) begin assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r; end else begin assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r; end endgenerate always @(posedge clk) last_byte_r <= #TCQ last_byte_ns; reg second_half_ns, second_half_r; always @(posedge clk) second_half_r <= #TCQ second_half_ns; always @(*) begin second_half_ns = second_half_r; if (rst) second_half_ns = 1'b0; else second_half_ns = phy_rddata_en_1 ^ second_half_r; end reg [7:0] comp0, comp180, prbs0, prbs180; integer ii; always @(*) begin comp0 = 8'hff; comp180 = 8'hff; prbs0 = 8'hff; prbs180 = 8'hff; data_bytes_ns = 64'b0; prbs_bytes_ns = 64'b0; for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) begin word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH]; word_shifted = word >> oclkdelay_calib_cnt*8; data_bytes_ns[ii*8+:8] = word_shifted[7:0]; word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH]; word_shifted = word >> oclkdelay_calib_cnt*8; prbs_bytes_ns[ii*8+:8] = word_shifted[7:0]; comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00); comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff); prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8]; end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) prbs180[0] = last_byte_r == prbs_bytes_r[7:0]; for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1) prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8]; if (nCK_PER_CLK == 4) begin if (prbs_ignore_last_bytes_r) begin prbs0[7:6] = 2'b11; prbs180[7] = 1'b1; end if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; end else begin if (second_half_r) begin if (prbs_ignore_last_bytes_r) begin prbs0[3:2] = 2'b11; prbs180[3] = 1'b1; end end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; end // else: !if(nCK_PER_CLK == 4) end // always @ (*) wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK; wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK; wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK; wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK; output [1:0] match; assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked}; endmodule // mig_7series_v4_0_ddr_phy_ocd_data ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v4_0_phy_ocd_edge.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Detects and stores edges as the test pattern is scanned via // manipulating the phaser out stage 3 taps. // // Scanning always proceeds from the left to the right. For more // on the scanning algorithm, see the _po_cntlr block. // // Four scan results are reported. The edges at fuzz2zero, // zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge // has a 6 bit stg3 tap value and a valid bit. The valid bits // are reset before the scan starts. // // Once reset_scan is set low, this block waits for the first // samp_done while scanning_right. This marks the left end // of the scan, and initializes prev_samp_r with samp_result and // sets the prev_samp_r valid bit to one. // // At each subesquent samp_done, the previous samp is compared // to the current samp_result. The case statement details how // edges are identified. // // Original design assumed fuzz between valid regions. Design // has been updated to tolerate transitions from zero to oneeight // and vice-versa without fuzz in between. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_edge # (parameter TCQ = 100) (/*AUTOARG*/ // Outputs scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, // Inputs clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right, samp_result, stg3 ); localparam [1:0] NULL = 2'b11, FUZZ = 2'b00, ONEEIGHTY = 2'b10, ZERO = 2'b01; input clk; input samp_done; input phy_rddata_en_2; wire samp_valid = samp_done && phy_rddata_en_2; input reset_scan; input scanning_right; reg prev_samp_valid_ns, prev_samp_valid_r; always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns; always @(*) begin prev_samp_valid_ns = prev_samp_valid_r; if (reset_scan) prev_samp_valid_ns = 1'b0; else if (samp_valid) prev_samp_valid_ns = 1'b1; end input [1:0] samp_result; reg [1:0] prev_samp_ns, prev_samp_r; always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns; always @(*) if (samp_valid) prev_samp_ns = samp_result; else prev_samp_ns = prev_samp_r; reg scan_right_ns, scan_right_r; always @(posedge clk) scan_right_r <= #TCQ scan_right_ns; output scan_right; assign scan_right = scan_right_r; input [5:0] stg3; reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r; always @(posedge clk) z2f_r <= #TCQ z2f_ns; always @(posedge clk) f2z_r <= #TCQ f2z_ns; always @(posedge clk) o2f_r <= #TCQ o2f_ns; always @(posedge clk) f2o_r <= #TCQ f2o_ns; output z2f, f2z, o2f, f2o; assign z2f = z2f_r; assign f2z = f2z_r; assign o2f = o2f_r; assign f2o = f2o_r; reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r, oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r; always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns; always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns; always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns; always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns; output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; assign zero2fuzz = zero2fuzz_r; assign fuzz2zero = fuzz2zero_r; assign oneeighty2fuzz = oneeighty2fuzz_r; assign fuzz2oneeighty = fuzz2oneeighty_r; always @(*) begin z2f_ns = z2f_r; f2z_ns = f2z_r; o2f_ns = o2f_r; f2o_ns = f2o_r; zero2fuzz_ns = zero2fuzz_r; fuzz2zero_ns = fuzz2zero_r; oneeighty2fuzz_ns = oneeighty2fuzz_r; fuzz2oneeighty_ns = fuzz2oneeighty_r; scan_right_ns = 1'b0; if (reset_scan) begin z2f_ns = 1'b0; f2z_ns = 1'b0; o2f_ns = 1'b0; f2o_ns = 1'b0; end else if (samp_valid && prev_samp_valid_r) case (prev_samp_r) FUZZ : if (scanning_right) begin if (samp_result == ZERO) begin fuzz2zero_ns = stg3; f2z_ns = 1'b1; end if (samp_result == ONEEIGHTY) begin fuzz2oneeighty_ns = stg3; f2o_ns = 1'b1; end end ZERO : begin if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right; if (scanning_right) begin if (samp_result == FUZZ) begin zero2fuzz_ns = stg3 - 6'b1; z2f_ns = 1'b1; end if (samp_result == ONEEIGHTY) begin zero2fuzz_ns = stg3 - 6'b1; z2f_ns = 1'b1; fuzz2oneeighty_ns = stg3; f2o_ns = 1'b1; end end end ONEEIGHTY : if (scanning_right) begin if (samp_result == FUZZ) begin oneeighty2fuzz_ns = stg3 - 6'b1; o2f_ns = 1'b1; end if (samp_result == ZERO) if (f2o_r) begin oneeighty2fuzz_ns = stg3 - 6'b1; o2f_ns = 1'b1; end else begin fuzz2zero_ns = stg3; f2z_ns = 1'b1; end end // if (scanning_right) // NULL : // Should never happen endcase end endmodule // mig_7series_v4_0_ddr_phy_ocd_edge ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_oclkdelay_cal.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 // delay //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_lim # (parameter TAPCNTRWIDTH = 7, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 9, parameter TCQ = 100, parameter TAPSPERKCLK = 56, parameter TDQSS_DEGREES = 60, parameter BYPASS_COMPLEX_OCAL = "FALSE") (/*AUTOARG*/ // Outputs lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right, lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done, lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim, // Inputs clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead, poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead, poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt, simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done, prech_done, oclkdelay_calib_cnt ); function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, input [TAPCNTRWIDTH-1:0] b, input integer base); begin mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b; end endfunction // mod_sub input clk; input rst; input lim_start; input po_rdy; input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead; input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail; input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead; input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail; input [5:0] oclkdelay_init_val; input [5:0] wl_po_fine_cnt; input [5:0] simp_stg3_final_sel; input oclkdelay_calib_done; input poc2lim_detect_done; input prech_done; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; output lim2init_write_request; output lim2init_prech_req; output lim2poc_rdy; output lim2poc_ktap_right; // I think this can be defaulted. output lim2stg3_inc; output lim2stg3_dec; output lim2stg2_inc; output lim2stg2_dec; output lim_done; output [5:0] lim2ocal_stg3_right_lim; output [5:0] lim2ocal_stg3_left_lim; output [255:0] dbg_ocd_lim; // Stage 3 taps can move an additional + or - 60 degrees from the write level position // Convert 60 degrees to MMCM taps. 360/60=6. //localparam real DIV_FACTOR = 360/TDQSS_DEGREES; //localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; localparam DIV_FACTOR = 360/TDQSS_DEGREES; localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; localparam WAIT_CNT = 15; localparam IDLE = 14'b00_0000_0000_0001; localparam INIT = 14'b00_0000_0000_0010; localparam WAIT_WR_REQ = 14'b00_0000_0000_0100; localparam WAIT_POC_DONE = 14'b00_0000_0000_1000; localparam WAIT_STG3 = 14'b00_0000_0001_0000; localparam STAGE3_INC = 14'b00_0000_0010_0000; localparam STAGE3_DEC = 14'b00_0000_0100_0000; localparam STAGE2_INC = 14'b00_0000_1000_0000; localparam STAGE2_DEC = 14'b00_0001_0000_0000; localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000; localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000; localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000; localparam PRECH_REQUEST = 14'b01_0000_0000_0000; localparam LIMIT_DONE = 14'b10_0000_0000_0000; // Flip-flops reg [5:0] stg3_init_val; reg [13:0] lim_state; reg lim_start_r; reg ktap_right_r; reg write_request_r; reg prech_req_r; reg poc_ready_r; reg wait_cnt_en_r; reg wait_cnt_done; reg [3:0] wait_cnt_r; reg [5:0] stg3_tap_cnt; reg [5:0] stg2_tap_cnt; reg [5:0] stg3_left_lim; reg [5:0] stg3_right_lim; reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim; reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim; reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim; reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim; reg [5:0] stg3_dec_val; reg [5:0] stg3_inc_val; reg detect_done_r; reg stg3_dec_r; reg stg2_inc_r; reg stg3_inc2init_val_r; reg stg3_inc2init_val_r1; reg stg3_dec2init_val_r; reg stg3_dec2init_val_r1; reg stg3_dec_req_r; reg stg3_inc_req_r; reg stg2_dec_req_r; reg stg2_inc_req_r; reg stg3_init_dec_r; reg [TAPCNTRWIDTH:0] mmcm_current; reg [TAPCNTRWIDTH:0] mmcm_init_trail; reg [TAPCNTRWIDTH:0] mmcm_init_lead; reg done_r; reg [13:0] lim_nxt_state; reg ktap_right; reg write_request; reg prech_req; reg poc_ready; reg stg3_dec; reg stg2_inc; reg stg3_inc2init_val; reg stg3_dec2init_val; reg stg3_dec_req; reg stg3_inc_req; reg stg2_dec_req; reg stg2_inc_req; reg stg3_init_dec; reg done; reg oclkdelay_calib_done_r; wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK); wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK); /***************************************************************************/ // Debug signals /***************************************************************************/ assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0]; assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0]; assign dbg_ocd_lim[255:108] = 'd0; assign lim2init_write_request = write_request_r; assign lim2init_prech_req = prech_req_r; assign lim2poc_ktap_right = ktap_right_r; assign lim2poc_rdy = poc_ready_r; assign lim2ocal_stg3_left_lim = stg3_left_lim; assign lim2ocal_stg3_right_lim = stg3_right_lim; assign lim2stg3_dec = stg3_dec_req_r; assign lim2stg3_inc = stg3_inc_req_r; assign lim2stg2_dec = stg2_dec_req_r; assign lim2stg2_inc = stg2_inc_req_r; assign lim_done = done_r; /**************************Wait Counter Start*********************************/ // Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3 // To avoid DQS toggling when stage2 and 3 taps are moving always @(posedge clk) begin if ((lim_state == WAIT_WR_REQ) || (lim_state == WAIT_STG3) || (lim_state == INIT)) wait_cnt_en_r <= #TCQ 1'b1; else wait_cnt_en_r <= #TCQ 1'b0; end // Wait counter for wait states WAIT_WR_REQ and WAIT_STG3 // To avoid DQS toggling when stage2 and 3 taps are moving always @(posedge clk) begin if (!wait_cnt_en_r) begin wait_cnt_r <= #TCQ 'b0; wait_cnt_done <= #TCQ 1'b0; end else begin if (wait_cnt_r != WAIT_CNT - 1) begin wait_cnt_r <= #TCQ wait_cnt_r + 1; wait_cnt_done <= #TCQ 1'b0; end else begin wait_cnt_r <= #TCQ 'b0; wait_cnt_done <= #TCQ 1'b1; end end end /**************************Wait Counter End***********************************/ // Flip-flops always @(posedge clk) begin if (rst) oclkdelay_calib_done_r <= #TCQ 1'b0; else oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done; end always @(posedge clk) begin if (rst) stg3_init_val <= #TCQ oclkdelay_init_val; else if (oclkdelay_calib_done) stg3_init_val <= #TCQ simp_stg3_final_sel; else stg3_init_val <= #TCQ oclkdelay_init_val; end always @(posedge clk) begin if (rst) begin lim_state <= #TCQ IDLE; lim_start_r <= #TCQ 1'b0; ktap_right_r <= #TCQ 1'b0; write_request_r <= #TCQ 1'b0; prech_req_r <= #TCQ 1'b0; poc_ready_r <= #TCQ 1'b0; detect_done_r <= #TCQ 1'b0; stg3_dec_r <= #TCQ 1'b0; stg2_inc_r <= #TCQ 1'b0; stg3_inc2init_val_r <= #TCQ 1'b0; stg3_inc2init_val_r1<= #TCQ 1'b0; stg3_dec2init_val_r <= #TCQ 1'b0; stg3_dec2init_val_r1<= #TCQ 1'b0; stg3_dec_req_r <= #TCQ 1'b0; stg3_inc_req_r <= #TCQ 1'b0; stg2_dec_req_r <= #TCQ 1'b0; stg2_inc_req_r <= #TCQ 1'b0; done_r <= #TCQ 1'b0; stg3_dec_val <= #TCQ 'd0; stg3_inc_val <= #TCQ 'd0; stg3_init_dec_r <= #TCQ 1'b0; end else begin lim_state <= #TCQ lim_nxt_state; lim_start_r <= #TCQ lim_start; ktap_right_r <= #TCQ ktap_right; write_request_r <= #TCQ write_request; prech_req_r <= #TCQ prech_req; poc_ready_r <= #TCQ poc_ready; detect_done_r <= #TCQ poc2lim_detect_done; stg3_dec_r <= #TCQ stg3_dec; stg2_inc_r <= #TCQ stg2_inc; stg3_inc2init_val_r <= #TCQ stg3_inc2init_val; stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r; stg3_dec2init_val_r <= #TCQ stg3_dec2init_val; stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r; stg3_dec_req_r <= #TCQ stg3_dec_req; stg3_inc_req_r <= #TCQ stg3_inc_req; stg2_dec_req_r <= #TCQ stg2_dec_req; stg2_inc_req_r <= #TCQ stg2_inc_req; stg3_init_dec_r <= #TCQ stg3_init_dec; done_r <= #TCQ done; if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2)) stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2); else stg3_dec_val <= #TCQ 'd0; if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2)) stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2); else stg3_inc_val <= #TCQ 'd63; end end // Keeping track of stage 3 tap count always @(posedge clk) begin if (rst) stg3_tap_cnt <= #TCQ stg3_init_val; else if ((lim_state == IDLE) || (lim_state == INIT)) stg3_tap_cnt <= #TCQ stg3_init_val; else if (lim_state == STAGE3_INC) stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1; else if (lim_state == STAGE3_DEC) stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1; end // Keeping track of stage 2 tap count always @(posedge clk) begin if (rst) stg2_tap_cnt <= #TCQ 'd0; else if ((lim_state == IDLE) || (lim_state == INIT)) stg2_tap_cnt <= #TCQ wl_po_fine_cnt; else if (lim_state == STAGE2_INC) stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1; else if (lim_state == STAGE2_DEC) stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1; end // Keeping track of MMCM tap count always @(posedge clk) begin if (rst) begin mmcm_init_trail <= #TCQ 'd0; mmcm_init_lead <= #TCQ 'd0; end else if (poc2lim_detect_done && !detect_done_r) begin if (stg3_tap_cnt == stg3_dec_val) mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail; if (stg3_tap_cnt == stg3_inc_val) mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead; end end always @(posedge clk) begin if (rst) begin mmcm_current <= #TCQ 'd0; end else if (stg3_dec_r) begin if (stg3_tap_cnt == stg3_dec_val) mmcm_current <= #TCQ mmcm_init_trail; else mmcm_current <= #TCQ poc2lim_rise_align_taps_lead; end else begin if (stg3_tap_cnt == stg3_inc_val) mmcm_current <= #TCQ mmcm_init_lead; else mmcm_current <= #TCQ poc2lim_rise_align_taps_trail; end end // Record Stage3 Left Limit always @(posedge clk) begin if (rst) begin stg3_left_lim <= #TCQ 'd0; simp_stg3_left_lim <= #TCQ 'd0; cmplx_stg3_left_lim <= #TCQ 'd0; end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin stg3_left_lim <= #TCQ stg3_tap_cnt; if (oclkdelay_calib_done) cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; else simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; end else if (lim_start && !lim_start_r) stg3_left_lim <= #TCQ 'd0; end // Record Stage3 Right Limit always @(posedge clk) begin if (rst) begin stg3_right_lim <= #TCQ 'd0; cmplx_stg3_right_lim <= #TCQ 'd0; simp_stg3_right_lim <= #TCQ 'd0; end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin stg3_right_lim <= #TCQ stg3_tap_cnt; if (oclkdelay_calib_done) cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; else simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; end else if (lim_start && !lim_start_r) stg3_right_lim <= #TCQ 'd0; end always @(*) begin lim_nxt_state = lim_state; ktap_right = ktap_right_r; write_request = write_request_r; prech_req = prech_req_r; poc_ready = poc_ready_r; stg3_dec = stg3_dec_r; stg2_inc = stg2_inc_r; stg3_inc2init_val = stg3_inc2init_val_r; stg3_dec2init_val = stg3_dec2init_val_r; stg3_dec_req = stg3_dec_req_r; stg3_inc_req = stg3_inc_req_r; stg2_inc_req = stg2_inc_req_r; stg2_dec_req = stg2_dec_req_r; stg3_init_dec = stg3_init_dec_r; done = done_r; case(lim_state) IDLE: begin if (lim_start && !lim_start_r) begin lim_nxt_state = INIT; stg3_dec = 1'b1; stg2_inc = 1'b1; stg3_init_dec = 1'b1; done = 1'b0; end //New start of limit module for complex oclkdelay calib else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin done = 1'b0; end end INIT: begin ktap_right = 1'b1; // Initial stage 2 increment to 63 for left limit if (wait_cnt_done) lim_nxt_state = STAGE2_TAP_CHK; end // Wait for DQS to toggle before asserting poc_ready WAIT_WR_REQ: begin write_request = 1'b1; if (wait_cnt_done) begin poc_ready = 1'b1; lim_nxt_state = WAIT_POC_DONE; end end // Wait for POC detect done signal WAIT_POC_DONE: begin if (poc2lim_detect_done) begin write_request = 1'b0; poc_ready = 1'b0; lim_nxt_state = WAIT_STG3; end end // Wait for DQS to stop toggling before stage3 inc/dec WAIT_STG3: begin if (wait_cnt_done) begin if (stg3_dec_r) begin // Check for Stage 3 underflow and MMCM tap limit if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS)) lim_nxt_state = STAGE3_DEC; else begin stg3_dec = 1'b0; stg3_inc2init_val = 1'b1; lim_nxt_state = STAGE3_INC; end end else begin // Stage 3 being incremented // Check for Stage 3 overflow and MMCM tap limit if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS)) lim_nxt_state = STAGE3_INC; else begin stg3_dec2init_val = 1'b1; lim_nxt_state = STAGE3_DEC; end end end end STAGE3_INC: begin stg3_inc_req = 1'b1; lim_nxt_state = STG3_INCDEC_WAIT; end STAGE3_DEC: begin stg3_dec_req = 1'b1; lim_nxt_state = STG3_INCDEC_WAIT; end // Wait for stage3 inc/dec to complete (po_rdy) STG3_INCDEC_WAIT: begin stg3_dec_req = 1'b0; stg3_inc_req = 1'b0; if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin if (stg3_init_dec_r) begin // Initial decrement of stage 3 if (stg3_tap_cnt > stg3_dec_val) lim_nxt_state = STAGE3_DEC; else begin lim_nxt_state = WAIT_WR_REQ; stg3_init_dec = 1'b0; end end else if (stg3_dec2init_val_r) begin if (stg3_tap_cnt > stg3_init_val) lim_nxt_state = STAGE3_DEC; else lim_nxt_state = STAGE2_TAP_CHK; end else if (stg3_inc2init_val_r) begin if (stg3_tap_cnt < stg3_inc_val) lim_nxt_state = STAGE3_INC; else lim_nxt_state = STAGE2_TAP_CHK; end else begin lim_nxt_state = WAIT_WR_REQ; end end end // Check for overflow and underflow of stage2 taps STAGE2_TAP_CHK: begin if (stg3_dec2init_val_r) begin // Increment stage 2 to write level tap value at the end of limit detection if (stg2_tap_cnt < wl_po_fine_cnt) lim_nxt_state = STAGE2_INC; else begin lim_nxt_state = PRECH_REQUEST; end end else if (stg3_inc2init_val_r) begin // Decrement stage 2 to '0' to determine right limit if (stg2_tap_cnt > 'd0) lim_nxt_state = STAGE2_DEC; else begin lim_nxt_state = PRECH_REQUEST; stg3_inc2init_val = 1'b0; end end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin // Initial increment to 63 lim_nxt_state = STAGE2_INC; end else begin lim_nxt_state = STG3_INCDEC_WAIT; stg2_inc = 1'b0; end end STAGE2_INC: begin stg2_inc_req = 1'b1; lim_nxt_state = STG2_INCDEC_WAIT; end STAGE2_DEC: begin stg2_dec_req = 1'b1; lim_nxt_state = STG2_INCDEC_WAIT; end // Wait for stage3 inc/dec to complete (po_rdy) STG2_INCDEC_WAIT: begin stg2_inc_req = 1'b0; stg2_dec_req = 1'b0; if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy) lim_nxt_state = STAGE2_TAP_CHK; end PRECH_REQUEST: begin prech_req = 1'b1; if (prech_done) begin prech_req = 1'b0; if (stg3_dec2init_val_r) lim_nxt_state = LIMIT_DONE; else lim_nxt_state = WAIT_WR_REQ; end end LIMIT_DONE: begin done = 1'b1; ktap_right = 1'b0; stg3_dec2init_val = 1'b0; lim_nxt_state = IDLE; end default: begin lim_nxt_state = IDLE; end endcase end endmodule //mig_7_series_v4_0_ddr_phy_ocd_lim ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v4_0_phy_ocd_mux.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: The limit block and the _po_cntlr block both manipulate // the phaser out and the POC. This block muxes those commands // together, and encapsulates logic required for meeting phaser // setup and wait times. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_mux # (parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter TCQ = 100) (/*AUTOARG*/ // Outputs ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy, po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel, po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req, // Inputs clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right, lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec, lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec, ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt, oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam PO_WAIT = 15; localparam POW_WIDTH = clogb2(PO_WAIT); localparam ONE = 1; localparam TWO = 2; input clk; input rst; input ocd_ktap_right, ocd_ktap_left; input lim2poc_ktap_right; output ktap_at_left_edge, ktap_at_right_edge; assign ktap_at_left_edge = ocd_ktap_left; assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right; input lim2poc_rdy; input ocd_edge_detect_rdy; output mmcm_edge_detect_rdy; assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy; // po_stg3_incdec and po_en_stg3 are deprecated and should be removed. output po_stg3_incdec; output po_en_stg3; assign po_stg3_incdec = 1'b0; assign po_en_stg3 = 1'b0; reg [1:0] po_setup_ns, po_setup_r; always @(posedge clk) po_setup_r <= #TCQ po_setup_ns; input lim2stg2_inc; input lim2stg2_dec; input lim2stg3_inc; input lim2stg3_dec; input ocd2stg2_inc; input ocd2stg2_dec; input ocd_cntlr2stg2_dec; input ocd2stg3_inc; input ocd2stg3_dec; wire setup_po = lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec || ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec; always @(*) begin po_setup_ns = po_setup_r; if (rst) po_setup_ns = 2'b00; else if (setup_po) po_setup_ns = 2'b11; else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01; end reg po_en_stg23_r; wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01; always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns; output po_en_stg23; assign po_en_stg23 = po_en_stg23_r; wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec; reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns; reg po_stg23_sel_r; // Reset to zero at the end. Makes adjust stg2 at end of centering // get the correct value of po_counter_read_val. wire po_stg23_sel_ns = ~rst && (setup_po ? sel_stg3 ? 1'b1 : 1'b0 : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0])); always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns; output po_stg23_sel; assign po_stg23_sel = po_stg23_sel_r; wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc; reg po_stg23_incdec_r; wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r); always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns; output po_stg23_incdec; assign po_stg23_incdec = po_stg23_incdec_r; always @(posedge clk) po_wait_r <= #TCQ po_wait_ns; always @(*) begin po_wait_ns = po_wait_r; if (rst) po_wait_ns = {POW_WIDTH{1'b0}}; else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0]; else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0]; end wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns); reg po_rdy_r; always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns; output po_rdy; assign po_rdy = po_rdy_r; input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6; output [5:0] wl_po_fine_cnt_sel; assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0]; input lim2init_prech_req; input ocd_prech_req; output oclk_prech_req; assign oclk_prech_req = ocd_prech_req || lim2init_prech_req; endmodule // mig_7series_v4_0_ddr_phy_ocd_mux ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v4_0_phy_ocd_po_cntlr.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Manipulates phaser out stg2f and stg3 on behalf of // scan and DQS centering. // // Maintains a shadow of the phaser out stg2f and stg3 tap settings. // The stg3 shadow is 6 bits, just like the phaser out. stg2f is // 8 bits. This allows the po_cntlr to track how far past the stg2f // saturation points we have gone when stepping to the limits of stg3. // This way we're can stay in sync when we step back from the saturation // limits. // // Looks at the edge values and determines which case has been // detected by the scan. Uses the results to drive the centering. // // Main state machine waits until it sees reset_scan go to zero. While // waiting it is writing the initialzation values to the stg2 and stg3 // shadows. When reset_scan goes low, taps_set is pulsed. This // tells the sampling block to begin sampling. When the sampling // block has finished sampling this setting of the phaser out taps, // is signals by setting samp_done. When the main state machine // sees samp_done it sets the next value in the phaser out and // waits for the phaser out to be ready before beginning the next // sample. // // Turns out phy_init is sensitive to the length of the ocal_num_samples_done // pulse. Something like a precharge and activate time. Added feature // to resume_wait to wait at least 32 cycles between assertion and // subsequent deassertion of ocal_num_samples_done. // // Also turns out phy_init needs help to get into consistent // starting state for complex cal. This can be done by preseting // ocal_num_samples_done to one. Then waiting for 32 fabric clocks, // turn off _done and then assert _resume. // // Scanning algorithm. // // Phaser manipulation algoritm. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_po_cntlr # (parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter nCK_PER_CLK = 4, parameter SAMPLES = 128, parameter TCQ = 100) (/*AUTOARG*/ // Outputs scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start, oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final, cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets, scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy, taps_set, use_noise_window, ocal_scan_win_not_found, // Inputs clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start, po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o, scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; input reset_scan; reg scan_done_r; output scan_done; assign scan_done = scan_done_r; output [5:0] simp_stg3_final_sel; reg cmplx_samples_done_ns, cmplx_samples_done_r; always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns; output ocal_num_samples_done_r; assign ocal_num_samples_done_r = cmplx_samples_done_r; // Write Level signals during OCLKDELAY calibration input [5:0] oclkdelay_init_val; input [5:0] lim2ocal_stg3_right_lim; input [5:0] lim2ocal_stg3_left_lim; input complex_oclkdelay_calib_start; reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r; always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns; output oclkdelay_center_calib_start; assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r; reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r; always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns; output oclkdelay_center_calib_done; assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r; reg oclk_center_write_resume_ns, oclk_center_write_resume_r; always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns; output oclk_center_write_resume; assign oclk_center_write_resume = oclk_center_write_resume_r; reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r; output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec; assign ocd2stg2_inc = ocd2stg2_inc_r; assign ocd2stg2_dec = ocd2stg2_dec_r; assign ocd2stg3_inc = ocd2stg3_inc_r; assign ocd2stg3_dec = ocd2stg3_dec_r; // Remember, two stage 2 steps for every stg 3 step. And we need a sign bit. reg [8:0] stg2_ns, stg2_r; always @(posedge clk) stg2_r <= #TCQ stg2_ns; reg [5:0] stg3_ns, stg3_r; always @(posedge clk) stg3_r <= #TCQ stg3_ns; output [5:0] stg3; assign stg3 = stg3_r; input [5:0] wl_po_fine_cnt_sel; input [8:0] po_counter_read_val; reg [5:0] po_counter_read_val_r; always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0]; reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r; always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns; always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns; output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; assign simp_stg3_final = simp_stg3_final_r; assign cmplx_stg3_final = cmplx_stg3_final_r; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6; assign simp_stg3_final_sel = simp_stg3_final_shft[5:0]; wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val; wire signed [8:0] stg2_steps = stg3_r > stg3_init ? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)}) : 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)}); wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps; reg signed [8:0] stg2_target_r; always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns; reg [5:0] stg2_final_ns, stg2_final_r; always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns; always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1 ? 6'd0 : stg2_target_r > 9'd63 ? 6'd63 : stg2_target_r[5:0]; wire final_stg2_inc = stg2_final_r > po_counter_read_val_r; wire final_stg2_dec = stg2_final_r < po_counter_read_val_r; wire left_lim = stg3_r == lim2ocal_stg3_left_lim; wire right_lim = stg3_r == lim2ocal_stg3_right_lim; reg [1:0] ninety_offsets_ns, ninety_offsets_r; always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns; output [1:0] ninety_offsets; assign ninety_offsets = ninety_offsets_r; reg scanning_right_ns, scanning_right_r; always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns; output scanning_right; assign scanning_right = scanning_right_r; reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r; always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns; always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns; output ocd_ktap_left, ocd_ktap_right; assign ocd_ktap_left = ocd_ktap_left_r; assign ocd_ktap_right = ocd_ktap_right_r; reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r; always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns; output ocd_edge_detect_rdy; assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r; input mmcm_edge_detect_done; input mmcm_lbclk_edge_aligned; input poc_backup; reg poc_backup_ns, poc_backup_r; always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; reg taps_set_r; output taps_set; assign taps_set = taps_set_r; input phy_rddata_en_3; input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; input z2f, f2z, o2f, f2o; wire zero = f2z && z2f; wire noise = z2f && f2o; wire oneeighty = f2o && o2f; reg win_not_found; reg [1:0] ninety_offsets_final_ns, ninety_offsets_final_r; always @(posedge clk) ninety_offsets_final_r <= #TCQ ninety_offsets_final_ns; reg [5:0] left, right, current_edge; always @(*) begin left = lim2ocal_stg3_left_lim; right = lim2ocal_stg3_right_lim; ninety_offsets_final_ns = 2'd0; win_not_found = 1'b0; if (zero) begin left = fuzz2zero; right = zero2fuzz; end else if (noise) begin left = zero2fuzz; right = fuzz2oneeighty; ninety_offsets_final_ns = 2'd1; end else if (oneeighty) begin left = fuzz2oneeighty; right = oneeighty2fuzz; ninety_offsets_final_ns = 2'd2; end else if (z2f) begin right = zero2fuzz; end else if (f2o) begin left = fuzz2oneeighty; ninety_offsets_final_ns = 2'd2; end else if (f2z) begin left = fuzz2zero; end else win_not_found = 1'b1; current_edge = ocd_ktap_left_r ? left : right; end // always @ begin output use_noise_window; assign use_noise_window = ninety_offsets == 2'd1; reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r; always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns; output ocal_scan_win_not_found; assign ocal_scan_win_not_found = ocal_scan_win_not_found_r; wire inc_po_ns = current_edge > stg3_r; wire dec_po_ns = current_edge < stg3_r; reg inc_po_r, dec_po_r; always @(posedge clk) inc_po_r <= #TCQ inc_po_ns; always @(posedge clk) dec_po_r <= #TCQ dec_po_ns; input scan_right; wire left_stop = left_lim || scan_right; wire right_stop = right_lim || o2f; // POC samples every other fabric clock. localparam POC_SAMPLE_CLEAR_WAIT = SAMPLES * 2 > 15 ? SAMPLES * 2 : 15; localparam MAX_RESUME_WAIT = POC_SAMPLE_CLEAR_WAIT > 31 ? POC_SAMPLE_CLEAR_WAIT : 31; localparam RESUME_WAIT_WIDTH = clogb2(MAX_RESUME_WAIT + 1); reg [RESUME_WAIT_WIDTH-1:0] resume_wait_ns, resume_wait_r; always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns; wire resume_wait = |resume_wait_r; reg po_done_ns, po_done_r; always @(posedge clk) po_done_r <= #TCQ po_done_ns; input samp_done; input po_rdy; reg up_ns, up_r; always @(posedge clk) up_r <= #TCQ up_ns; reg [1:0] two_ns, two_r; always @(posedge clk) two_r <= #TCQ two_ns; /* wire stg2_zero = ~|stg2_r; wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0 : stg2_r > 9'd63 ? 9'd63 : stg2_r; */ reg [3:0] sm_ns, sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r; always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns; always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3 ? ~phy_rddata_en_3_second_r : phy_rddata_en_3_second_r); wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3; reg po_center_wait; reg po_slew; reg po_finish_scan; always @(*) begin // Default next state assignments. cmplx_samples_done_ns = cmplx_samples_done_r; cmplx_stg3_final_ns = cmplx_stg3_final_r; scanning_right_ns = scanning_right_r; ninety_offsets_ns = ninety_offsets_r; ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r; ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r; ocd_ktap_left_ns = ocd_ktap_left_r; ocd_ktap_right_ns = ocd_ktap_right_r; ocd2stg2_inc_r = 1'b0; ocd2stg2_dec_r = 1'b0; ocd2stg3_inc_r = 1'b0; ocd2stg3_dec_r = 1'b0; oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r; oclkdelay_center_calib_done_ns = 1'b0; oclk_center_write_resume_ns = oclk_center_write_resume_r; po_center_wait = 1'b0; po_done_ns = po_done_r; po_finish_scan = 1'b0; po_slew = 1'b0; poc_backup_ns = poc_backup_r; scan_done_r = 1'b0; simp_stg3_final_ns = simp_stg3_final_r; sm_ns = sm_r; taps_set_r = 1'b0; up_ns = up_r; stg2_ns = stg2_r; stg3_ns = stg3_r; two_ns = two_r; resume_wait_ns = resume_wait_r; if (rst == 1'b1) begin // RESET next states cmplx_samples_done_ns = 1'b0; ocal_scan_win_not_found_ns = 1'b0; ocd_ktap_left_ns = 1'b0; ocd_ktap_right_ns = 1'b0; ocd_edge_detect_rdy_ns = 1'b0; oclk_center_write_resume_ns = 1'b0; oclkdelay_center_calib_start_ns = 1'b0; po_done_ns = 1'b1; resume_wait_ns = 5'd0; sm_ns = /*AK("READY")*/4'd0; end else // State based actions and next states. case (sm_r) /*AL("READY")*/4'd0:begin poc_backup_ns = 1'b0; stg2_ns = {3'b0, wl_po_fine_cnt_sel}; stg3_ns = stg3_init; scanning_right_ns = 1'b0; if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; if (!reset_scan && ~resume_wait) begin cmplx_samples_done_ns = 1'b0; ocal_scan_win_not_found_ns = 1'b0; taps_set_r = 1'b1; sm_ns = /*AK("SAMPLING")*/4'd1; end end /*AL("SAMPLING")*/4'd1:begin if (samp_done && use_samp_done) begin if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; scanning_right_ns = scanning_right_r || left_stop; if (right_stop && scanning_right_r) begin oclkdelay_center_calib_start_ns = 1'b1; ocd_ktap_left_ns = 1'b1; ocal_scan_win_not_found_ns = win_not_found; sm_ns = /*AK("SLEW_PO")*/4'd3; end else begin if (scanning_right_ns) ocd2stg3_inc_r = 1'b1; else ocd2stg3_dec_r = 1'b1; sm_ns = /*AK("PO_WAIT")*/4'd2; end end end /*AL("PO_WAIT")*/4'd2:begin if (po_done_r && ~resume_wait) begin taps_set_r = 1'b1; sm_ns = /*AK("SAMPLING")*/4'd1; cmplx_samples_done_ns = 1'b0; end end /*AL("SLEW_PO")*/4'd3:begin po_slew = 1'b1; ninety_offsets_ns = |ninety_offsets_final_r ? 2'b01 : 2'b00; if (~resume_wait) begin if (po_done_r) begin if (inc_po_r) ocd2stg3_inc_r = 1'b1; else if (dec_po_r) ocd2stg3_dec_r = 1'b1; else if (~resume_wait) begin cmplx_samples_done_ns = 1'b0; sm_ns = /*AK("ALIGN_EDGES")*/4'd4; oclk_center_write_resume_ns = 1'b1; end end // if (po_done) end end // case: 3'd3 /*AL("ALIGN_EDGES")*/4'd4: if (~resume_wait) begin if (mmcm_edge_detect_done) begin ocd_edge_detect_rdy_ns = 1'b0; if (ocd_ktap_left_r) begin ocd_ktap_left_ns = 1'b0; ocd_ktap_right_ns = 1'b1; oclk_center_write_resume_ns = 1'b0; sm_ns = /*AK("SLEW_PO")*/4'd3; end else if (ocd_ktap_right_r) begin ocd_ktap_right_ns = 1'b0; sm_ns = /*AK("WAIT_ONE")*/4'd5; end else if (~mmcm_lbclk_edge_aligned) begin sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6; oclk_center_write_resume_ns = 1'b0; end else begin if (ninety_offsets_r != ninety_offsets_final_r && ocd_edge_detect_rdy_r) begin ninety_offsets_ns = ninety_offsets_r + 2'b01; sm_ns = /*AK("WAIT_ONE")*/4'd5; end else begin oclk_center_write_resume_ns = 1'b0; poc_backup_ns = poc_backup; // stg2_ns = stg2_2_zero; sm_ns = /*AK("FINISH_SCAN")*/4'd8; end end // else: !if(~mmcm_lbclk_edge_aligned) end else ocd_edge_detect_rdy_ns = 1'b1; end // if (~resume_wait) /*AL("WAIT_ONE")*/4'd5: sm_ns = /*AK("ALIGN_EDGES")*/4'd4; /*AL("DQS_STOP_WAIT")*/4'd6: if (~resume_wait) begin ocd2stg3_dec_r = 1'b1; sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7; end /*AL("CENTER_PO_WAIT")*/4'd7: begin po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols. if (po_done_r) begin sm_ns = /*AK("ALIGN_EDGES")*/4'd4; oclk_center_write_resume_ns = 1'b1; end end /*AL("FINISH_SCAN")*/4'd8: begin po_finish_scan = 1'b1; if (resume_wait_r == 5'd1) begin if (~poc_backup_r) begin oclkdelay_center_calib_done_ns = 1'b1; oclkdelay_center_calib_start_ns = 1'b0; end end if (~resume_wait) begin if (po_rdy) if (poc_backup_r) begin ocd2stg3_inc_r = 1'b1; poc_backup_ns = 1'b0; end else if (~final_stg2_inc && ~final_stg2_dec) begin if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; sm_ns = /*AK("READY")*/4'd0; scan_done_r = 1'b1; end else begin ocd2stg2_inc_r = final_stg2_inc; ocd2stg2_dec_r = final_stg2_dec; end end // if (~resume_wait) end // case: 4'd8 endcase // case (sm_r) if (ocd2stg3_inc_r) begin stg3_ns = stg3_r + 6'h1; up_ns = 1'b0; end if (ocd2stg3_dec_r) begin stg3_ns = stg3_r - 6'h1; up_ns = 1'b1; end if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin po_done_ns = 1'b0; two_ns = 2'b00; end if (~po_done_r) if (po_rdy) if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1; else begin two_ns = two_r + 2'b1; if (up_r) begin stg2_ns = stg2_r + 9'b1; if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1; end else begin stg2_ns = stg2_r - 9'b1; if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1; end end // else: !if(two_r == 2'b10) if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 'b1; else if (oclk_center_write_resume_ns && ~oclk_center_write_resume_r) resume_wait_ns = POC_SAMPLE_CLEAR_WAIT[RESUME_WAIT_WIDTH-1:0]; else if (~oclk_center_write_resume_ns && oclk_center_write_resume_r) resume_wait_ns = 'd15; else if (cmplx_samples_done_ns & ~cmplx_samples_done_r || complex_oclkdelay_calib_start & reset_scan || poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 'd31; else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 'd1; end // always @ begin endmodule // mig_7series_v4_0_ddr_phy_ocd_po_cntlr // Local Variables: // verilog-autolabel-prefix: "4'd" // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v4_0_phy_ocd_samp.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Controls the number of samples and generates an aggregate //sampling result. // // The following shows the nesting of the sampling loop. Nominally built // to accomodate the "complex" sampling protocol. Adapted for use with // "simple" samplng. // // simple complex // // samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION // rd_victim_sel 0 0 to 7 // data_cnt 1 157 // // First it collects comparison results provided on the // two bit "match" bus. A particular phaser tap setting may be recorded one // or many times depending on various parameter settings. // The two bit match bus corresponds to comparisons for the // zero or rising phase, and the oneeighty or falling phase. The "aggregate" // starts out as NULL and then begins collecting comparison results // when phy_rddata_en_1 is high. The first result is always set into // the aggregate result. Subsequent results that match aggregate, don't // make any change. Subsequent compare results that don't match cause the aggregate // to turn to FUZZ. // // A "sample" is defined as a single DRAM burst for the simple step, and // an entire 157 DRAM data bursts across the 8 victim bits for complex. // // Once all samples have been taken, the samp_result is computed by // comparing the number of successful compares against the threshold. // // The second function is to track and control the number of samples. For // "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS. // For "complex" data, nominally // the complex data pattern consists of a sequence of 157 DRAM chunks. This // sequence is run with each bit in the byte designated as the "victim". This sequence // is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only // repeated once. // // This block generates oclk_calib_resume. For the simple pattern, a single DRAM // burst is returned For complex its 157 which indicates the start of the 157*50 // sequence for a bit. samp_done is pulsed. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_ocd_samp # (parameter nCK_PER_CLK = 4, parameter OCAL_SIMPLE_SCAN_SAMPS = 2, parameter SCAN_PCT_SAMPS_SOLID = 95, parameter TCQ = 100, parameter SIM_CAL_OPTION = "NONE") (/*AUTOARG*/ // Outputs samp_done, oclk_calib_resume, rd_victim_sel, samp_result, // Inputs complex_oclkdelay_calib_start, clk, rst, reset_scan, ocal_num_samples_inc, match, phy_rddata_en_1, taps_set, phy_rddata_en_2 ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam ONE = 1; localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157; localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1; localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8; localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1; // Plus one because were counting in natural numbers. localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS ? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1; // Remember SAMPLES is natural number counting. One corresponds to one sample. localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; localparam integer SIMP_SAMPS_HALF_THRESH = SIMP_SAMPS_SOLID_THRESH/2; localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; localparam integer CMPLX_SAMPS_HALF_THRESH = CMPLX_SAMPS_SOLID_THRESH/2; input complex_oclkdelay_calib_start; wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; localparam [1:0] NULL = 2'b11, FUZZ = 2'b00, ONEEIGHTY = 2'b10, ZERO = 2'b01; input clk; input rst; input reset_scan; // Given the need to count phy_data_en, this is not useful. input ocal_num_samples_inc; input [1:0] match; input phy_rddata_en_1; input taps_set; reg samp_done_ns, samp_done_r; always @(posedge clk) samp_done_r <= #TCQ samp_done_ns; output samp_done; assign samp_done = samp_done_r; input phy_rddata_en_2; wire samp_valid = samp_done_r && phy_rddata_en_2; reg [1:0] agg_samp_ns, agg_samp_r; always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns; reg oclk_calib_resume_ns, oclk_calib_resume_r; always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns; output oclk_calib_resume; assign oclk_calib_resume = oclk_calib_resume_r; // Complex data counting. // Inner most loop. 157 phy_data_en. reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r; always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns; // Nominally, 50 samples of the above 157 phy_data_en. reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r; always @(posedge clk) samps_r <= #TCQ samps_ns; // Step through the 8 bits in the byte. reg [2:0] rd_victim_sel_ns, rd_victim_sel_r; always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns; output [2:0] rd_victim_sel; assign rd_victim_sel = rd_victim_sel_r; reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r; always @(posedge clk) zero_r <= #TCQ zero_ns; always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns; wire [SAMP_CNT_WIDTH-1:0] samp_thresh = (complex_oclkdelay_calib_start ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); wire [SAMP_CNT_WIDTH-1:0] samp_half_thresh = (complex_oclkdelay_calib_start ? CMPLX_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0] : SIMP_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]); wire zero_ge_thresh = zero_r >= samp_thresh; wire zero_le_half_thresh = zero_r <= samp_half_thresh; wire oneeighty_ge_thresh = oneeighty_r >= samp_thresh; wire oneeighty_le_half_thresh = oneeighty_r <= samp_half_thresh; reg [1:0] samp_result_ns, samp_result_r; always @(posedge clk) samp_result_r <= #TCQ samp_result_ns; always @(*) if (rst) samp_result_ns = 'b0; else begin samp_result_ns = samp_result_r; if (samp_valid) begin if (~samp_result_r[0] && zero_ge_thresh) samp_result_ns[0] = 'b1; if (samp_result_r[0] && zero_le_half_thresh) samp_result_ns[0] = 'b0; if (~samp_result_r[1] && oneeighty_ge_thresh) samp_result_ns[1] = 'b1; if (samp_result_r[1] && oneeighty_le_half_thresh) samp_result_ns[1] = 'b0; end end output [1:0] samp_result; assign samp_result = samp_result_ns; reg [0:0] sm_ns, sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start ? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0] : SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0]; wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0; wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0]; wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0]; // Primary state machine. always @(*) begin // Default next state assignments. agg_samp_ns = agg_samp_r; data_cnt_ns = data_cnt_r; oclk_calib_resume_ns = 1'b0; oneeighty_ns = oneeighty_r; rd_victim_sel_ns = rd_victim_sel_r; samp_done_ns = samp_done_r; samps_ns = samps_r; sm_ns = sm_r; zero_ns = zero_r; if (rst == 1'b1) begin // RESET next states sm_ns = /*AK("READY")*/1'd0; end else // State based actions and next states. case (sm_r) /*AL("READY")*/1'd0:begin agg_samp_ns = NULL; data_cnt_ns = data_cnt; oneeighty_ns = 'b0; zero_ns = 'b0; rd_victim_sel_ns = 3'b0; samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; if (taps_set) begin samp_done_ns = 1'b0; sm_ns = /*AK("AWAITING_DATA")*/1'd1; oclk_calib_resume_ns = 1'b1; end end /*AL("AWAITING_DATA")*/1'd1:begin if (phy_rddata_en_1) begin case (agg_samp_r) NULL : if (~&match) agg_samp_ns = match; ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ; FUZZ : ; endcase // case (agg_samp_r) if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0]; else begin data_cnt_ns = data_cnt; if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1; else begin rd_victim_sel_ns = 3'h0; if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0]; if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0]; agg_samp_ns = NULL; if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0]; else samp_done_ns = 1'b1; end end if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0; else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end; end end endcase // case (sm_r) end // always @ begin endmodule // mig_7series_v4_0_ddr_phy_ocd_samp // Local Variables: // verilog-autolabel-prefix: "1'd" // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_oclkdelay_cal.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 // delay //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_oclkdelay_cal # (parameter TCQ = 100, parameter nCK_PER_CLK = 4, parameter DRAM_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter DQ_WIDTH = 64, parameter MMCM_SAMP_WAIT = 10, parameter OCAL_SIMPLE_SCAN_SAMPS = 2, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SCAN_PCT_SAMPS_SOLID = 95, parameter SIM_CAL_OPTION = "NONE", parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 56, parameter BYPASS_COMPLEX_OCAL = "FALSE") (/*AUTOARG*/ // Outputs wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg23_sel, po_stg23_incdec, po_en_stg23, oclkdelay_center_calib_start, oclkdelay_center_calib_done, oclk_prech_req, oclk_center_write_resume, oclk_calib_resume, ocal_num_samples_done_r, lim2init_write_request, dbg_poc, complex_wrlvl_final, complex_oclkdelay_calib_done, oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data, oclkdelay_calib_done, lim_done, dbg_ocd_lim, // Inputs wl_po_fine_cnt, rst, psdone, prech_done, prbs_o, prbs_ignore_last_bytes, prbs_ignore_first_byte, poc_sample_pd, po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val, oclkdelay_calib_start, ocal_num_samples_inc, metaQ, complex_oclkdelay_calib_start, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v, ... input metaQ; // To u_poc of mig_7series_v4_0_poc_top.v input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v, ... input poc_sample_pd; // To u_poc of mig_7series_v4_0_poc_top.v input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v input prech_done; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... input psdone; // To u_poc of mig_7series_v4_0_poc_top.v input rst; // To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ... input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v output [1023:0] dbg_poc; // From u_poc of mig_7series_v4_0_poc_top.v output lim2init_write_request; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v output oclk_calib_resume; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v output oclk_prech_req; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v output po_en_stg23; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v output po_stg23_incdec; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v output po_stg23_sel; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v output poc_error; // From u_poc of mig_7series_v4_0_poc_top.v output psen; // From u_poc of mig_7series_v4_0_poc_top.v output psincdec; // From u_poc of mig_7series_v4_0_poc_top.v output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v output wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire f2o; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire f2z; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire [5:0] fuzz2oneeighty; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire [5:0] fuzz2zero; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v wire lim_start; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire [1:0] match; // From u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v wire mmcm_edge_detect_done; // From u_poc of mig_7series_v4_0_poc_top.v wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v4_0_poc_top.v wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire o2f; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire [5:0] oneeighty2fuzz; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire po_rdy; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v wire poc_backup; // From u_poc of mig_7series_v4_0_poc_top.v wire reset_scan; // From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v4_0_poc_top.v wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v4_0_poc_top.v wire samp_done; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v wire scan_done; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire scan_right; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire taps_set; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v wire z2f; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v wire [5:0] zero2fuzz; // From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v // End of automatics wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; wire ocal_scan_win_not_found; output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; output [255:0] dbg_phy_oclkdelay_cal; output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data; output oclkdelay_calib_done; output lim_done; output [255:0] dbg_ocd_lim; // Debug signals assign dbg_phy_oclkdelay_cal[0] = f2o; assign dbg_phy_oclkdelay_cal[1] = f2z; assign dbg_phy_oclkdelay_cal[2] = o2f; assign dbg_phy_oclkdelay_cal[3] = z2f; assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty; assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero; assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz; assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz; assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt; assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start; assign dbg_phy_oclkdelay_cal[32] = lim_done; assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ; assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ; assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0]; assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0]; assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found; assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start; assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done; assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0]; /*mig_7series_v4_0_ddr_phy_ocd_lim AUTO_TEMPLATE( .TDQSS_DEGREES (), .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]), .poc2lim_detect_done (mmcm_edge_detect_done), .poc2lim_fall_align_taps_.* ({TAPCNTRWIDTH{1'b0}}), .poc2lim_rise_align_taps_lead (rise_lead_right), .poc2lim_rise_align_taps_trail (rise_trail_right),); */ mig_7series_v4_0_ddr_phy_ocd_lim # (/*AUTOINSTPARAM*/ // Parameters .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ), .TDQSS_DEGREES ()) // Templated u_ocd_lim (/*AUTOINST*/ // Outputs .dbg_ocd_lim (dbg_ocd_lim[255:0]), .lim2init_prech_req (lim2init_prech_req), .lim2init_write_request (lim2init_write_request), .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), .lim2poc_ktap_right (lim2poc_ktap_right), .lim2poc_rdy (lim2poc_rdy), .lim2stg2_dec (lim2stg2_dec), .lim2stg2_inc (lim2stg2_inc), .lim2stg3_dec (lim2stg3_dec), .lim2stg3_inc (lim2stg3_inc), .lim_done (lim_done), // Inputs .clk (clk), .lim_start (lim_start), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .po_rdy (po_rdy), .poc2lim_detect_done (mmcm_edge_detect_done), // Templated .poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated .poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated .poc2lim_rise_align_taps_lead (rise_lead_right), // Templated .poc2lim_rise_align_taps_trail (rise_trail_right), // Templated .prech_done (prech_done), .rst (rst), .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0])); // Templated /*mig_7series_v4_0_poc_top AUTO_TEMPLATE( .CCENABLE (0), .LANE_CNT_WIDTH (DQS_CNT_WIDTH), .SCANFROMRIGHT (1), .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), .pd_out (metaQ),); */ mig_7series_v4_0_poc_top # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (0), // Templated .LANE_CNT_WIDTH (DQS_CNT_WIDTH), // Templated .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .SCANFROMRIGHT (1), // Templated .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc (/*AUTOINST*/ // Outputs .dbg_poc (dbg_poc[1023:0]), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), .poc_error (poc_error), .psen (psen), .psincdec (psincdec), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), // Templated .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .pd_out (metaQ), // Templated .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .use_noise_window (use_noise_window)); /*mig_7series_v4_0_ddr_phy_ocd_mux AUTO_TEMPLATE( .po_stg3_incdec (), .po_en_stg3 (),); */ mig_7series_v4_0_ddr_phy_ocd_mux # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ)) u_ocd_mux (/*AUTOINST*/ // Outputs .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .oclk_prech_req (oclk_prech_req), .po_en_stg23 (po_en_stg23), .po_en_stg3 (), // Templated .po_rdy (po_rdy), .po_stg23_incdec (po_stg23_incdec), .po_stg23_sel (po_stg23_sel), .po_stg3_incdec (), // Templated .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), // Inputs .clk (clk), .lim2init_prech_req (lim2init_prech_req), .lim2poc_ktap_right (lim2poc_ktap_right), .lim2poc_rdy (lim2poc_rdy), .lim2stg2_dec (lim2stg2_dec), .lim2stg2_inc (lim2stg2_inc), .lim2stg3_dec (lim2stg3_dec), .lim2stg3_inc (lim2stg3_inc), .ocd2stg2_dec (ocd2stg2_dec), .ocd2stg2_inc (ocd2stg2_inc), .ocd2stg3_dec (ocd2stg3_dec), .ocd2stg3_inc (ocd2stg3_inc), .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), .ocd_edge_detect_rdy (ocd_edge_detect_rdy), .ocd_ktap_left (ocd_ktap_left), .ocd_ktap_right (ocd_ktap_right), .ocd_prech_req (ocd_prech_req), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .rst (rst), .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0])); mig_7series_v4_0_ddr_phy_ocd_data # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_data (/*AUTOINST*/ // Outputs .match (match[1:0]), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .phy_rddata_en_1 (phy_rddata_en_1), .prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .rst (rst)); mig_7series_v4_0_ddr_phy_ocd_samp # (/*AUTOINSTPARAM*/ // Parameters .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), .SIM_CAL_OPTION (SIM_CAL_OPTION), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_samp (/*AUTOINST*/ // Outputs .oclk_calib_resume (oclk_calib_resume), .rd_victim_sel (rd_victim_sel[2:0]), .samp_done (samp_done), .samp_result (samp_result[1:0]), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .match (match[1:0]), .ocal_num_samples_inc (ocal_num_samples_inc), .phy_rddata_en_1 (phy_rddata_en_1), .phy_rddata_en_2 (phy_rddata_en_2), .reset_scan (reset_scan), .rst (rst), .taps_set (taps_set)); mig_7series_v4_0_ddr_phy_ocd_edge # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ)) u_ocd_edge (/*AUTOINST*/ // Outputs .f2o (f2o), .f2z (f2z), .fuzz2oneeighty (fuzz2oneeighty[5:0]), .fuzz2zero (fuzz2zero[5:0]), .o2f (o2f), .oneeighty2fuzz (oneeighty2fuzz[5:0]), .scan_right (scan_right), .z2f (z2f), .zero2fuzz (zero2fuzz[5:0]), // Inputs .clk (clk), .phy_rddata_en_2 (phy_rddata_en_2), .reset_scan (reset_scan), .samp_done (samp_done), .samp_result (samp_result[1:0]), .scanning_right (scanning_right), .stg3 (stg3[5:0])); /*mig_7series_v4_0_ddr_phy_ocd_cntlr AUTO_TEMPLATE( .oclk_init_delay_done (),); */ mig_7series_v4_0_ddr_phy_ocd_cntlr # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ)) u_ocd_cntlr (/*AUTOINST*/ // Outputs .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), .complex_wrlvl_final (complex_wrlvl_final), .lim_start (lim_start), .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), .ocd_prech_req (ocd_prech_req), .oclk_init_delay_done (), // Templated .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .phy_rddata_en_1 (phy_rddata_en_1), .phy_rddata_en_2 (phy_rddata_en_2), .phy_rddata_en_3 (phy_rddata_en_3), .reset_scan (reset_scan), .wrlvl_final (wrlvl_final), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .lim_done (lim_done), .oclkdelay_calib_start (oclkdelay_calib_start), .phy_rddata_en (phy_rddata_en), .po_counter_read_val (po_counter_read_val[8:0]), .po_rdy (po_rdy), .prech_done (prech_done), .rst (rst), .scan_done (scan_done)); mig_7series_v4_0_ddr_phy_ocd_po_cntlr # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .SAMPLES (SAMPLES), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_po_cntlr (.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]), .ocal_scan_win_not_found (ocal_scan_win_not_found), .simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]), /*AUTOINST*/ // Outputs .ninety_offsets (ninety_offsets[1:0]), .ocal_num_samples_done_r (ocal_num_samples_done_r), .ocd2stg2_dec (ocd2stg2_dec), .ocd2stg2_inc (ocd2stg2_inc), .ocd2stg3_dec (ocd2stg3_dec), .ocd2stg3_inc (ocd2stg3_inc), .ocd_edge_detect_rdy (ocd_edge_detect_rdy), .ocd_ktap_left (ocd_ktap_left), .ocd_ktap_right (ocd_ktap_right), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .scan_done (scan_done), .scanning_right (scanning_right), .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), .stg3 (stg3[5:0]), .taps_set (taps_set), .use_noise_window (use_noise_window), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .f2o (f2o), .f2z (f2z), .fuzz2oneeighty (fuzz2oneeighty[5:0]), .fuzz2zero (fuzz2zero[5:0]), .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .o2f (o2f), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .oneeighty2fuzz (oneeighty2fuzz[5:0]), .phy_rddata_en_3 (phy_rddata_en_3), .po_counter_read_val (po_counter_read_val[8:0]), .po_rdy (po_rdy), .poc_backup (poc_backup), .reset_scan (reset_scan), .rst (rst), .samp_done (samp_done), .scan_right (scan_right), .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), .z2f (z2f), .zero2fuzz (zero2fuzz[5:0])); endmodule // mig_7series_v4_0_ddr_phy_oclkdelay_cal // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_prbs_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // PRBS Read leveling calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_prbs_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter PRBS_WIDTH = 8, // PRBS generator output width parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE" parameter FINE_PER_BIT = "ON", parameter CENTER_COMP_MODE = "ON", parameter PI_VAL_ADJ = "ON" ) ( input clk, input rst, // Calibration status, control signals input prbs_rdlvl_start, (* max_fanout = 100 *) output reg prbs_rdlvl_done, output reg prbs_last_byte_done, output reg prbs_rdlvl_prech_req, input complex_sample_cnt_inc, input prech_done, input phy_if_empty, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, //Expected data from PRBS generator input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data, // Decrement initial Phaser_IN Fine tap delay input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output [255:0] dbg_prbs_rdlvl, output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] rd_victim_sel, output reg complex_victim_inc, output reg reset_rd_addr, output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit output reg fine_delay_sel, //fine delay selection - actual update of fine delay output reg num_samples_done_r, input complex_act_start, //read is done. ready for PI movement output complex_init_pi_dec_done, //Initial PI incdec is done. ready for start output reg complex_pi_incdec_done //PI incdec is done. ready for Read ); localparam [5:0] PRBS_IDLE = 6'h00; localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01; localparam [5:0] PRBS_PAT_COMPARE = 6'h02; localparam [5:0] PRBS_DEC_DQS = 6'h03; localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04; localparam [5:0] PRBS_INC_DQS = 6'h05; localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06; localparam [5:0] PRBS_CALC_TAPS = 6'h07; localparam [5:0] PRBS_NEXT_DQS = 6'h08; localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09; localparam [5:0] PRBS_DONE = 6'h0A; localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B; localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C; localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_INC = 6'h14; //wait for read is done before PI inc localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_DEC = 6'h15; //wait for read is done before PI dec localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd12 : 12'h001; //MG from 50 localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001; localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001; //minimum valid window for centering localparam MIN_WIN = 8; localparam [MIN_WIN-1:0] MATCH_ALL_ONE = {MIN_WIN{1'b1}}; localparam [MIN_WIN-1:0] MIN_PASS = {MIN_WIN{1'b0}}; //8'b00000000 localparam [MIN_WIN-1:0] MIN_LEFT = {1'b1,{{MIN_WIN-1}{1'b0}}}; //8'b10000000 wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing; reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r; reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r; reg prbs_prech_req_r; reg [5:0] prbs_state_r; reg [5:0] prbs_state_r1; reg wait_state_cnt_en_r; reg [3:0] wait_state_cnt_r; reg cnt_wait_state; reg err_chk_invalid; // reg found_edge_r; reg prbs_found_1st_edge_r; reg prbs_found_2nd_edge_r; reg [5:0] prbs_1st_edge_taps_r; // reg found_stable_eye_r; reg [5:0] prbs_dqs_tap_cnt_r; reg [5:0] prbs_dec_tap_calc_plus_3; reg [5:0] prbs_dec_tap_calc_minus_3; reg prbs_dqs_tap_limit_r; reg [5:0] prbs_inc_tap_cnt; reg [5:0] prbs_dec_tap_cnt; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4; reg mux_rd_valid_r; reg rd_valid_r1; reg rd_valid_r2; reg rd_valid_r3; reg new_cnt_dqs_r; reg prbs_tap_en_r; reg prbs_tap_inc_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; wire [DQ_WIDTH-1:0] compare_data_r0; wire [DQ_WIDTH-1:0] compare_data_f0; wire [DQ_WIDTH-1:0] compare_data_r1; wire [DQ_WIDTH-1:0] compare_data_f1; wire [DQ_WIDTH-1:0] compare_data_r2; wire [DQ_WIDTH-1:0] compare_data_f2; wire [DQ_WIDTH-1:0] compare_data_r3; wire [DQ_WIDTH-1:0] compare_data_f3; reg [DRAM_WIDTH-1:0] compare_data_rise0_r1; reg [DRAM_WIDTH-1:0] compare_data_fall0_r1; reg [DRAM_WIDTH-1:0] compare_data_rise1_r1; reg [DRAM_WIDTH-1:0] compare_data_fall1_r1; reg [DRAM_WIDTH-1:0] compare_data_rise2_r1; reg [DRAM_WIDTH-1:0] compare_data_fall2_r1; reg [DRAM_WIDTH-1:0] compare_data_rise3_r1; reg [DRAM_WIDTH-1:0] compare_data_fall3_r1; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] prbs_2nd_edge_taps_r; // reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; reg [5:0] rdlvl_cpt_tap_cnt; reg prbs_rdlvl_start_r; reg compare_err; reg compare_err_r0; reg compare_err_f0; reg compare_err_r1; reg compare_err_f1; reg compare_err_r2; reg compare_err_f2; reg compare_err_r3; reg compare_err_f3; reg compare_err_latch; reg samples_cnt1_en_r; reg samples_cnt2_en_r; reg [11:0] samples_cnt_r; reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync reg [DQS_WIDTH-1:0] prbs_tap_mod; //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; //************************************************************************** // signals for per-bit algorithm of fine_delay calculations //************************************************************************** reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit reg [MIN_WIN*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit reg [MIN_WIN-1:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail) reg [MIN_WIN-1:0] match_flag_or; //5 consecute match flag of all bits (1: any bit fail) reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update reg right_edge_found; //smallest right_edge found reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge) reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center) reg [6:0] center_calc; //used for calculate the dec tap for centering reg [5:0] right_edge_ref; //ref_bit right edge reg [5:0] left_edge_ref; //ref_bit left edge reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge reg compare_err_pb_and; //indicate all bit fail reg compare_err_pb_or; //indicate any bit fail reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit) reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage) wire fine_calib; //turn on/off fine delay calibration reg [5:0] mem_out_dec; reg [5:0] dec_cnt; reg fine_dly_error; //indicate it has wrong left/right edge reg edge_det_error; //indicate it has wrong left/right edge wire center_comp; wire pi_adj; reg no_err_win_detected; reg no_err_win_detected_latch; reg [1:0] valid_window_cnt; //number of valid window in the scan reg double_window_ind; //indication of double window //if inital PI dec is not done, init SM should wait until it is done reg complex_init_pi_dec_done_r; //if inital PI dec is not done, init SM should wait until it is done wire complex_rdlvl_err; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r; //fine delay turn on assign fine_calib = (FINE_PER_BIT=="ON")? 1:0; assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0; assign pi_adj = (PI_VAL_ADJ == "ON")?1:0; //Debug error flag assign complex_rdlvl_err = fine_dly_error | edge_det_error; //initial dec is only happening for per-bit assign complex_init_pi_dec_done = fine_calib? complex_init_pi_dec_done_r : 1'b1; assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6]; assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2]; assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6]; assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2]; assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ; assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2]; assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ; assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2]; assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6]; assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2]; assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6]; assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2]; assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6]; assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2]; assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6]; assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2]; assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6]; assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2]; assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ; assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2]; assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6]; assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2]; assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6]; assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2]; assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6]; assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2]; assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6]; assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2]; assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6]; assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2]; assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6]; assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2]; assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val; assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r; assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r; assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r; assign dbg_prbs_rdlvl[142] = compare_err; assign dbg_prbs_rdlvl[143] = phy_if_empty; assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start; assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done; assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r; assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ; assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6]; assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]}; assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ; assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0]; assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0]; assign dbg_prbs_rdlvl[184] = rd_valid_r2; assign dbg_prbs_rdlvl[185] = compare_err_r0; assign dbg_prbs_rdlvl[186] = compare_err_f0; assign dbg_prbs_rdlvl[187] = compare_err_r1; assign dbg_prbs_rdlvl[188] = compare_err_f1; assign dbg_prbs_rdlvl[189] = compare_err_r2; assign dbg_prbs_rdlvl[190] = compare_err_f2; assign dbg_prbs_rdlvl[191] = compare_err_r3; assign dbg_prbs_rdlvl[192] = compare_err_f3; assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb; assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb; assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ; assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ; assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb; assign dbg_prbs_rdlvl[229] = fine_delay_sel; assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r; assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt; assign dbg_prbs_rdlvl[244+:5] = match_flag_and[4:0]; assign dbg_prbs_rdlvl[249+:2] = stage_cnt; assign dbg_prbs_rdlvl[251] = fine_inc_stage; assign dbg_prbs_rdlvl[252] = compare_err_pb_and; assign dbg_prbs_rdlvl[253] = right_edge_found; assign dbg_prbs_rdlvl[254] = complex_rdlvl_err; assign dbg_prbs_rdlvl[255] = double_window_ind; //************************************************************************** // Record first and second edges found during calibration //************************************************************************** generate always @(posedge clk) if (rst) begin dbg_prbs_first_edge_taps <= #TCQ 'b0; dbg_prbs_second_edge_taps <= #TCQ 'b0; end else if (prbs_state_r == PRBS_CALC_TAPS) begin // Record tap counts of first and second edge edges during // calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (prbs_found_1st_edge_r) dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ prbs_1st_edge_taps_r; if (prbs_found_2nd_edge_r) dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ prbs_2nd_edge_taps_r; end else if (prbs_state_r == FINE_CALC_TAPS) begin if(stage_cnt == 'd2) begin dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ largest_left_edge; dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ smallest_right_edge; end end endgenerate //double window indication flag always @ (posedge clk) if (rst) double_window_ind <= #TCQ 1'd0; else double_window_ind <= #TCQ double_window_ind? 1'b1: (valid_window_cnt > 1); //padded calculation always @ (smallest_right_edge or largest_left_edge) center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge}; //*************************************************************************** //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign compare_data_r2 = 'h0; assign compare_data_f2 = 'h0; assign compare_data_r3 = 'h0; assign compare_data_f3 = 'h0; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; //Compare data compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate generate genvar muxr2_i; if (nCK_PER_CLK == 4) begin: gen_mux_div4 for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4 always @(posedge clk) begin if (mux_rd_valid_r) begin mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i]; mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i]; mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i]; mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i]; end //pipeline stage mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i]; mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i]; mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i]; mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i]; //pipeline stage mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i]; mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i]; mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i]; mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_div2 for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2 always @(posedge clk) begin if (mux_rd_valid_r) begin mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; mux_rd_rise2_r2[muxr2_i] <= 'h0; mux_rd_fall2_r2[muxr2_i] <= 'h0; mux_rd_rise3_r2[muxr2_i] <= 'h0; mux_rd_fall3_r2[muxr2_i] <= 'h0; end mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; mux_rd_rise2_r3[muxr2_i] <= 'h0; mux_rd_fall2_r3[muxr2_i] <= 'h0; mux_rd_rise3_r3[muxr2_i] <= 'h0; mux_rd_fall3_r3[muxr2_i] <= 'h0; //pipeline stage mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; mux_rd_rise2_r4[muxr2_i] <= 'h0; mux_rd_fall2_r4[muxr2_i] <= 'h0; mux_rd_rise3_r4[muxr2_i] <= 'h0; mux_rd_fall3_r4[muxr2_i] <= 'h0; end end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) begin mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start; rd_valid_r1 <= #TCQ mux_rd_valid_r; rd_valid_r2 <= #TCQ rd_valid_r1; rd_valid_r3 <= #TCQ rd_valid_r2; end // Counter counts # of samples compared // Reset sample counter when not "sampling" // Otherwise, count # of samples compared // Same counter is shared for three samples checked always @(posedge clk) if (rst) samples_cnt_r <= #TCQ 'b0; else if (samples_cnt_r == NUM_SAMPLES_CNT) begin samples_cnt_r <= #TCQ 'b0; end else if (complex_sample_cnt_inc) begin samples_cnt_r <= #TCQ samples_cnt_r + 1; /*if (!rd_valid_r1 || (prbs_state_r == PRBS_DEC_DQS_WAIT) || (prbs_state_r == PRBS_INC_DQS_WAIT) || (prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS) || (samples_cnt_r == NUM_SAMPLES_CNT) || (samples_cnt_r == NUM_SAMPLES_CNT1)) samples_cnt_r <= #TCQ 'b0; else if (rd_valid_r1 && (((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) || ((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) || ((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r))) samples_cnt_r <= #TCQ samples_cnt_r + 1;*/ end // Count #2 enable generation // Assert when correct number of samples compared always @(posedge clk) if (rst) samples_cnt1_en_r <= #TCQ 1'b0; else begin if ((prbs_state_r == PRBS_IDLE) || (prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) samples_cnt1_en_r <= #TCQ 1'b0; else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1) samples_cnt1_en_r <= #TCQ 1'b1; end // Counter #3 enable generation // Assert when correct number of samples compared always @(posedge clk) if (rst) samples_cnt2_en_r <= #TCQ 1'b0; else begin if ((prbs_state_r == PRBS_IDLE) || (prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) samples_cnt2_en_r <= #TCQ 1'b0; else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r) samples_cnt2_en_r <= #TCQ 1'b1; end // Victim selection logic always @(posedge clk) if (rst) rd_victim_sel <= #TCQ 'd0; else if (num_samples_done_r) rd_victim_sel <= #TCQ 'd0; else if (samples_cnt_r == NUM_SAMPLES_CNT) begin if (rd_victim_sel < 'd7) rd_victim_sel <= #TCQ rd_victim_sel + 1; end // Output row count increment pulse to phy_init always @(posedge clk) if (rst) complex_victim_inc <= #TCQ 1'b0; else if (samples_cnt_r == NUM_SAMPLES_CNT) complex_victim_inc <= #TCQ 1'b1; else complex_victim_inc <= #TCQ 1'b0; generate if (FIXED_VICTIM == "TRUE") begin: victim_fixed always @(posedge clk) if (rst) num_samples_done_r <= #TCQ 1'b0; else if ((prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS)|| (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC)) num_samples_done_r <= #TCQ 'b0; else if (samples_cnt_r == NUM_SAMPLES_CNT) num_samples_done_r <= #TCQ 1'b1; end else begin: victim_not_fixed always @(posedge clk) if (rst) num_samples_done_r <= #TCQ 1'b0; else if ((prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS)|| (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC)) num_samples_done_r <= #TCQ 'b0; else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7)) num_samples_done_r <= #TCQ 1'b1; end endgenerate //*************************************************************************** // Compare Read Data for the byte being Leveled with Expected data from PRBS // generator. Resulting compare_err signal used to determine read data valid // edge. //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: cmp_err_4to1 always @ (posedge clk) begin if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin compare_err <= #TCQ 1'b0; compare_err_r0 <= #TCQ 1'b0; compare_err_f0 <= #TCQ 1'b0; compare_err_r1 <= #TCQ 1'b0; compare_err_f1 <= #TCQ 1'b0; compare_err_r2 <= #TCQ 1'b0; compare_err_f2 <= #TCQ 1'b0; compare_err_r3 <= #TCQ 1'b0; compare_err_f3 <= #TCQ 1'b0; end else if (rd_valid_r2) begin compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1); compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1); compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1); compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1); compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | compare_err_r1 | compare_err_f1 | compare_err_r2 | compare_err_f2 | compare_err_r3 | compare_err_f3); end end end else begin: cmp_err_2to1 always @ (posedge clk) begin if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin compare_err <= #TCQ 1'b0; compare_err_r0 <= #TCQ 1'b0; compare_err_f0 <= #TCQ 1'b0; compare_err_r1 <= #TCQ 1'b0; compare_err_f1 <= #TCQ 1'b0; end else if (rd_valid_r2) begin compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | compare_err_r1 | compare_err_f1); end end end endgenerate //Sticky bit compare_err always @ (posedge clk) if (prbs_state_r == PRBS_PAT_COMPARE) compare_err_latch <= #TCQ compare_err? 1'b1: compare_err_latch; else compare_err_latch <= #TCQ 1'b0; //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (prbs_tap_en_r) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r; end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) prbs_rdlvl_prech_req <= #TCQ 1'b0; else prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst) begin prbs_dqs_tap_cnt_r <= #TCQ 'b0; rdlvl_cpt_tap_cnt <= #TCQ 'b0; end else if (new_cnt_dqs_r) begin prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val; rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val; end else if (prbs_tap_en_r) begin if (prbs_tap_inc_r) prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1; else if (prbs_dqs_tap_cnt_r != 'd0) prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1; end always @(posedge clk) if (rst) begin prbs_dec_tap_calc_plus_3 <= #TCQ 'b0; prbs_dec_tap_calc_minus_3 <= #TCQ 'b0; end else if (new_cnt_dqs_r) begin prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011; prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100; end else begin prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3); prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3); end always @(posedge clk) if (rst || new_cnt_dqs_r) prbs_dqs_tap_limit_r <= #TCQ 1'b0; else if (prbs_dqs_tap_cnt_r == 6'd63) prbs_dqs_tap_limit_r <= #TCQ 1'b1; else prbs_dqs_tap_limit_r <= #TCQ 1'b0; // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*prbs_dqs_cnt_r. // replacing this with two left shifts + one left shift to avoid // DSP multiplier. assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r}; always @(posedge clk) prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin prbs_final_dqs_tap_cnt_r <= #TCQ 'b0; end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ prbs_dqs_tap_cnt_r; end end //***************************************************************** always @(posedge clk) begin prbs_state_r1 <= #TCQ prbs_state_r; prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start; end // Wait counter for wait states always @(posedge clk) if ((prbs_state_r == PRBS_NEW_DQS_WAIT) || (prbs_state_r == PRBS_INC_DQS_WAIT) || (prbs_state_r == PRBS_DEC_DQS_WAIT) || (prbs_state_r == FINE_PI_DEC_WAIT) || (prbs_state_r == FINE_PI_INC_WAIT) || (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) wait_state_cnt_en_r <= #TCQ 1'b1; else wait_state_cnt_en_r <= #TCQ 1'b0; always @(posedge clk) if (!wait_state_cnt_en_r) begin wait_state_cnt_r <= #TCQ 'b0; cnt_wait_state <= #TCQ 1'b0; end else begin if (wait_state_cnt_r < 'd15) begin wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1; cnt_wait_state <= #TCQ 1'b0; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back wait_state_cnt_r <= #TCQ 'b0; cnt_wait_state <= #TCQ 1'b1; end end always @ (posedge clk) err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14); //***************************************************************** // compare error checking per-bit //**************************************************************** generate genvar pb_i; if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1 for(pb_i=0 ; pb_i prbs_dqs_tap_cnt_r -(MIN_WIN-1))? 'd0 : prbs_dqs_tap_cnt_r-(MIN_WIN-1)-left_edge_ref; //right edge is updated when match flag becomes 000000001 (8 success, 1 fail) end else if (match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_PASS && compare_err_pb_latch_r[eg]) begin right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1; right_edge_found_pb[eg] <= #TCQ 1'b1; //check the gain of bit - update only for right edge found if(~right_edge_found_pb[eg]) right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)? ((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]): ((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]); //no right edge found end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin right_edge_pb[eg*6+:6] <= #TCQ 6'h3f; right_edge_found_pb[eg] <= #TCQ 1'b1; //right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge) right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])? (right_edge_ref - right_edge_pb[eg*6+:6]) : 0; end //update match flag - shift and update match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ {match_flag_pb[(eg*MIN_WIN)+:(MIN_WIN-1)],compare_err_pb_latch_r[eg]}; end else if (prbs_state_r == FINE_PI_DEC) begin left_edge_found_pb[eg] <= #TCQ 1'b0; right_edge_found_pb[eg] <= #TCQ 1'b0; left_loss_pb[eg*6+:6] <= #TCQ 'b0; right_gain_pb[eg*6+:6] <= #TCQ 'b0; match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE ; //new fix left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge end else if (prbs_state_r == FINE_PI_INC) begin left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge end end end //always end //for endgenerate //update fine_delay according to loss/gain value per bit generate genvar f_pb; for(f_pb=0; f_pbleft_loss_pb[f_pb*6+:6])?1'b1:1'b0; end end end endgenerate //fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3) always @ (posedge clk) begin if (rst) fine_inc_stage <= #TCQ 'b1; else fine_inc_stage <= #TCQ (stage_cnt!='d3); end //***************************************************************** always @(posedge clk) if (rst) begin prbs_dqs_cnt_r <= #TCQ 'b0; prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; prbs_prech_req_r <= #TCQ 1'b0; prbs_state_r <= #TCQ PRBS_IDLE; prbs_found_1st_edge_r <= #TCQ 1'b0; prbs_found_2nd_edge_r <= #TCQ 1'b0; prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx; prbs_inc_tap_cnt <= #TCQ 'b0; prbs_dec_tap_cnt <= #TCQ 'b0; new_cnt_dqs_r <= #TCQ 1'b0; if (SIM_CAL_OPTION == "FAST_CAL") prbs_rdlvl_done <= #TCQ 1'b1; else prbs_rdlvl_done <= #TCQ 1'b0; prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx; prbs_last_byte_done <= #TCQ 1'b0; prbs_tap_mod <= #TCQ 'd0; reset_rd_addr <= #TCQ 'b0; fine_pi_dec_cnt <= #TCQ 'b0; match_flag_and <= #TCQ MATCH_ALL_ONE; match_flag_or <= #TCQ MATCH_ALL_ONE; no_err_win_detected <= #TCQ 1'b0; no_err_win_detected_latch <= #TCQ 1'b0; valid_window_cnt <= 2'd0; stage_cnt <= #TCQ 2'b00; right_edge_found <= #TCQ 1'b0; largest_left_edge <= #TCQ 6'b000000; smallest_right_edge <= #TCQ 6'b111111; num_samples_done_ind <= #TCQ 'b0; fine_delay_sel <= #TCQ 'b0; fine_dly_error <= #TCQ 'b0; edge_det_error <= #TCQ 'b0; complex_pi_incdec_done <= #TCQ 1'b0; complex_init_pi_dec_done_r <= #TCQ 1'b0; end else begin case (prbs_state_r) PRBS_IDLE: begin prbs_last_byte_done <= #TCQ 1'b0; prbs_prech_req_r <= #TCQ 1'b0; if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin prbs_state_r <= #TCQ PRBS_DONE; reset_rd_addr <= #TCQ 1'b1; end else begin new_cnt_dqs_r <= #TCQ 1'b1; prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. end end end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group PRBS_NEW_DQS_WAIT: begin reset_rd_addr <= #TCQ 'b0; prbs_last_byte_done <= #TCQ 1'b0; prbs_prech_req_r <= #TCQ 1'b0; stage_cnt <= #TCQ 2'b0; match_flag_and <= #TCQ MATCH_ALL_ONE; match_flag_or <= #TCQ MATCH_ALL_ONE; no_err_win_detected <= #TCQ 1'b0; no_err_win_detected_latch <= #TCQ 1'b0; if (cnt_wait_state) begin new_cnt_dqs_r <= #TCQ 1'b0; prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE; //For normal, it doesn't have initial pi incdec complex_pi_incdec_done <= #TCQ fine_calib? complex_pi_incdec_done: 1'b1; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in PRBS_PAT_COMPARE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change PRBS_PAT_COMPARE: begin // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed //comparision started - wait for next PI movement after read complex_pi_incdec_done <= #TCQ 1'b0; //need to be wait for new incdec done if (num_samples_done_r) begin if (prbs_dqs_tap_limit_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; else if (compare_err_latch || (prbs_dqs_tap_cnt_r == 'd0)) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge prbs_found_1st_edge_r <= #TCQ 1'b1; // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (prbs_found_1st_edge_r) begin prbs_found_2nd_edge_r <= #TCQ 1'b1; prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1; prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! if (compare_err_latch) prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1; else prbs_1st_edge_taps_r <= #TCQ 'd0; prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r; prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; end end else begin // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing if (prbs_found_1st_edge_r) //prbs_state_r <= #TCQ PRBS_INC_DQS; prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; else //prbs_state_r <= #TCQ PRBS_DEC_DQS; prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; end end end // Increment Phaser_IN delay for DQS PRBS_INC_DQS: begin prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT; if (prbs_inc_tap_cnt > 'd0) prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1; if (~prbs_dqs_tap_limit_r) begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b1; end end // Wait for Phaser_In to settle, before checking again for an edge // only all INC is done, incdec done is asserted PRBS_INC_DQS_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if (cnt_wait_state) begin if (prbs_inc_tap_cnt > 'd0) prbs_state_r <= #TCQ PRBS_INC_DQS; //centering else begin prbs_state_r <= #TCQ PRBS_PAT_COMPARE; complex_pi_incdec_done <= #TCQ 1'b1; end end end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: The amount to be decrement by is calculated, not the // absolute setting for DQS. // CENTER compensation with shift by 1 //wait finishing the read before PI dec to center PRBS_CALC_TAPS: begin if (center_comp) begin prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj; fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; end else begin //No center compensation if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin // Both edges detected prbs_dec_tap_cnt <= #TCQ ((prbs_2nd_edge_taps_r - prbs_1st_edge_taps_r)>>1) + 1 + pi_adj; edge_det_error <= #TCQ edge_det_error? 1'b1: (prbs_1st_edge_taps_r >= prbs_2nd_edge_taps_r); end else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin // Only left edge detected prbs_dec_tap_cnt <= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj; end else begin // No edges detected edge_det_error <= #TCQ 1'b1; prbs_dec_tap_cnt <= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj; end // Now use the value we just calculated to decrement CPT taps // to the desired calibration point //wait finishing the read before PI dec to center prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; end end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) PRBS_DEC_DQS: begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS if (prbs_dec_tap_cnt > 'd0) prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1; if (prbs_dec_tap_cnt == 6'b000001) begin prbs_state_r <= #TCQ PRBS_NEXT_DQS; //only all DEC is done, incdec done is asserted complex_pi_incdec_done <= #TCQ 1'b1; end else prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT; end PRBS_DEC_DQS_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if (cnt_wait_state) begin if (prbs_dec_tap_cnt > 'd0) prbs_state_r <= #TCQ PRBS_DEC_DQS; else begin //PI movement is done, go to read and compare complex_pi_incdec_done <= #TCQ 1'b1; prbs_state_r <= #TCQ PRBS_PAT_COMPARE; end end end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate PRBS_NEXT_DQS: begin //Need to do initial dec for per-bit algorithm complex_init_pi_dec_done_r <= #TCQ 1'b0; reset_rd_addr <= #TCQ 'b1; prbs_prech_req_r <= #TCQ 1'b1; prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group prbs_found_1st_edge_r <= #TCQ 1'b0; prbs_found_2nd_edge_r <= #TCQ 1'b0; prbs_1st_edge_taps_r <= #TCQ 'd0; prbs_2nd_edge_taps_r <= #TCQ 'd0; largest_left_edge <= #TCQ 6'b000000; smallest_right_edge <= #TCQ 6'b111111; if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin prbs_last_byte_done <= #TCQ 1'b1; end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin prbs_prech_req_r <= #TCQ 1'b0; if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin // All DQS groups done prbs_state_r <= #TCQ PRBS_DONE; end else begin // Process next DQS group new_cnt_dqs_r <= #TCQ 1'b1; prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1; prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT; end end end PRBS_NEW_DQS_PREWAIT: begin if (cnt_wait_state) begin prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. end end PRBS_CALC_TAPS_PRE: begin //Wait for new PI movement complex_pi_incdec_done <= #TCQ 1'b0; prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT; if(center_comp && ~fine_calib) begin if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r; else largest_left_edge <= #TCQ 6'd0; if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r; else smallest_right_edge <= #TCQ 6'd63; end end //wait for center compensation PRBS_CALC_TAPS_WAIT: begin prbs_state_r <= #TCQ PRBS_CALC_TAPS; end //if it is fine_inc stage (first/second stage): dec to 0 //if it is fine_dec stage (third stage): dec to center FINE_PI_DEC: begin fine_delay_sel <= #TCQ 'b0; if(fine_pi_dec_cnt > 0) begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b0; fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1; end prbs_state_r <= #TCQ FINE_PI_DEC_WAIT; end //wait for phaser_in tap decrement. //if first/second stage is done, goes to FINE_PI_INC //if last stage is done, goes to NEXT_DQS //All PI DEC is done, incdec done is asserted FINE_PI_DEC_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if(cnt_wait_state) begin if(fine_pi_dec_cnt >0) prbs_state_r <= #TCQ FINE_PI_DEC; else begin complex_pi_incdec_done <= #TCQ 1'b1; if(fine_inc_stage) prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0" else prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS end end end //finish the read before PI increament RD_DONE_WAIT_FOR_PI_INC_INC: begin if(complex_act_start) prbs_state_r <= #TCQ fine_calib? FINE_PI_INC: PRBS_INC_DQS; end FINE_PI_INC: begin //prevent left edge update after valid window found if(|left_edge_updated && ~no_err_win_detected_latch) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1); if (no_err_win_detected) begin //ignore previous right edge updated if valid window shown after right_edge_found <= #TCQ 'b0; end else if(|right_edge_found_pb && ~right_edge_found) begin smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ; right_edge_found <= #TCQ 'b1; end //until minimum window is detected, left edge can be updated //once minimum window is detected, no further left edge update will be done if(no_err_win_detected) no_err_win_detected_latch <= #TCQ 1'b1; prbs_state_r <= #TCQ FINE_PI_INC_WAIT; if(~prbs_dqs_tap_limit_r) begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b1; end end //wait for phase_in tap increment //need to do pattern compare for every bit FINE_PI_INC_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if (cnt_wait_state) begin prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //PI movement is done, go to read and compare complex_pi_incdec_done <= #TCQ 1'b1; end end //compare per bit data and update flags,left/right edge FINE_PAT_COMPARE_PER_BIT: begin //comparision started - initial pi dec is done, wait for another pi movement after read complex_init_pi_dec_done_r <= #TCQ 1'b1; complex_pi_incdec_done <= #TCQ 1'b0; if(num_samples_done_r) begin //sampling boundary //update and_flag - shift and add match_flag_and <= #TCQ {match_flag_and[MIN_WIN-2:0],compare_err_pb_and}; match_flag_or <= #TCQ {match_flag_or[MIN_WIN-2:0],compare_err_pb_or}; //to solve false left/right edge detection if({match_flag_or[MIN_WIN-2:0],compare_err_pb_or} == MIN_PASS) begin //if it detect minimum window no_err_win_detected <= #TCQ 1'b1; valid_window_cnt <= #TCQ valid_window_cnt + 'd1; end else begin no_err_win_detected <= #TCQ 1'b0; end //if it is consecutive 8 passing taps followed by fail or tap limit (finish the search) //don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage //Or if all right edge are found if((match_flag_and == MIN_PASS && compare_err_pb_and && (prbs_dqs_tap_cnt_r > MIN_WIN )) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin prbs_state_r <= #TCQ FINE_CALC_TAPS; //if all right edge are alined (all right edge found at the same time), update smallest right edge in here //doesnt need to set right_edge_found to 1 since it is not used after this stage if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1; end else begin prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; //keep increase until all fail end num_samples_done_ind <= num_samples_done_r; end end //for fine_inc stage, inc all fine delay //for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain) // put phaser_in taps to the center FINE_CALC_TAPS: begin if(num_samples_done_ind || num_samples_done_r) begin num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set right_edge_found <= #TCQ 1'b0; //reset right edge found match_flag_and <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits match_flag_or <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits no_err_win_detected <= #TCQ 1'b0; no_err_win_detected_latch <= #TCQ 1'b0; prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT; valid_window_cnt <= #TCQ 2'd0; //reset valid window counter end end FINE_CALC_TAPS_WAIT: begin //wait for ROM read out if(stage_cnt == 'd2) begin //last stage : back to center if(center_comp) begin fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1 fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error; end else begin fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1 fine_dly_error <= #TCQ 1'b0; end end else begin fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r; end if (bit_cnt == DRAM_WIDTH) begin fine_delay_sel <= #TCQ 'b1; stage_cnt <= #TCQ stage_cnt + 1; prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; end end //wait for finishing the read before PI movement RD_DONE_WAIT_FOR_PI_INC_DEC: begin if (complex_act_start & ~complex_rdlvl_err) prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC: PRBS_DEC_DQS; end // Done with this stage of calibration PRBS_DONE: begin prbs_prech_req_r <= #TCQ 1'b0; prbs_last_byte_done <= #TCQ 1'b0; prbs_rdlvl_done <= #TCQ ~complex_rdlvl_err; reset_rd_addr <= #TCQ 1'b0; end endcase end //ROM generation for dec counter always @ (largest_left_edge or smallest_right_edge) begin case ({largest_left_edge, smallest_right_edge}) 12'd0 : mem_out_dec = 6'b111111; 12'd1 : mem_out_dec = 6'b111111; 12'd2 : mem_out_dec = 6'b111111; 12'd3 : mem_out_dec = 6'b111111; 12'd4 : mem_out_dec = 6'b111111; 12'd5 : mem_out_dec = 6'b111111; 12'd6 : mem_out_dec = 6'b000100; 12'd7 : mem_out_dec = 6'b000101; 12'd8 : mem_out_dec = 6'b000101; 12'd9 : mem_out_dec = 6'b000110; 12'd10 : mem_out_dec = 6'b000110; 12'd11 : mem_out_dec = 6'b000111; 12'd12 : mem_out_dec = 6'b001000; 12'd13 : mem_out_dec = 6'b001000; 12'd14 : mem_out_dec = 6'b001001; 12'd15 : mem_out_dec = 6'b001010; 12'd16 : mem_out_dec = 6'b001010; 12'd17 : mem_out_dec = 6'b001011; 12'd18 : mem_out_dec = 6'b001011; 12'd19 : mem_out_dec = 6'b001100; 12'd20 : mem_out_dec = 6'b001100; 12'd21 : mem_out_dec = 6'b001100; 12'd22 : mem_out_dec = 6'b001100; 12'd23 : mem_out_dec = 6'b001101; 12'd24 : mem_out_dec = 6'b001100; 12'd25 : mem_out_dec = 6'b001100; 12'd26 : mem_out_dec = 6'b001101; 12'd27 : mem_out_dec = 6'b001110; 12'd28 : mem_out_dec = 6'b001110; 12'd29 : mem_out_dec = 6'b001111; 12'd30 : mem_out_dec = 6'b010000; 12'd31 : mem_out_dec = 6'b010001; 12'd32 : mem_out_dec = 6'b010001; 12'd33 : mem_out_dec = 6'b010010; 12'd34 : mem_out_dec = 6'b010010; 12'd35 : mem_out_dec = 6'b010010; 12'd36 : mem_out_dec = 6'b010011; 12'd37 : mem_out_dec = 6'b010100; 12'd38 : mem_out_dec = 6'b010100; 12'd39 : mem_out_dec = 6'b010101; 12'd40 : mem_out_dec = 6'b010101; 12'd41 : mem_out_dec = 6'b010110; 12'd42 : mem_out_dec = 6'b010110; 12'd43 : mem_out_dec = 6'b010111; 12'd44 : mem_out_dec = 6'b011000; 12'd45 : mem_out_dec = 6'b011001; 12'd46 : mem_out_dec = 6'b011001; 12'd47 : mem_out_dec = 6'b011010; 12'd48 : mem_out_dec = 6'b011010; 12'd49 : mem_out_dec = 6'b011011; 12'd50 : mem_out_dec = 6'b011011; 12'd51 : mem_out_dec = 6'b011100; 12'd52 : mem_out_dec = 6'b011100; 12'd53 : mem_out_dec = 6'b011100; 12'd54 : mem_out_dec = 6'b011100; 12'd55 : mem_out_dec = 6'b011100; 12'd56 : mem_out_dec = 6'b011100; 12'd57 : mem_out_dec = 6'b011100; 12'd58 : mem_out_dec = 6'b011100; 12'd59 : mem_out_dec = 6'b011101; 12'd60 : mem_out_dec = 6'b011110; 12'd61 : mem_out_dec = 6'b011111; 12'd62 : mem_out_dec = 6'b100000; 12'd63 : mem_out_dec = 6'b100000; 12'd64 : mem_out_dec = 6'b111111; 12'd65 : mem_out_dec = 6'b111111; 12'd66 : mem_out_dec = 6'b111111; 12'd67 : mem_out_dec = 6'b111111; 12'd68 : mem_out_dec = 6'b111111; 12'd69 : mem_out_dec = 6'b111111; 12'd70 : mem_out_dec = 6'b111111; 12'd71 : mem_out_dec = 6'b000100; 12'd72 : mem_out_dec = 6'b000100; 12'd73 : mem_out_dec = 6'b000101; 12'd74 : mem_out_dec = 6'b000110; 12'd75 : mem_out_dec = 6'b000111; 12'd76 : mem_out_dec = 6'b000111; 12'd77 : mem_out_dec = 6'b001000; 12'd78 : mem_out_dec = 6'b001001; 12'd79 : mem_out_dec = 6'b001001; 12'd80 : mem_out_dec = 6'b001010; 12'd81 : mem_out_dec = 6'b001010; 12'd82 : mem_out_dec = 6'b001011; 12'd83 : mem_out_dec = 6'b001011; 12'd84 : mem_out_dec = 6'b001011; 12'd85 : mem_out_dec = 6'b001011; 12'd86 : mem_out_dec = 6'b001011; 12'd87 : mem_out_dec = 6'b001100; 12'd88 : mem_out_dec = 6'b001011; 12'd89 : mem_out_dec = 6'b001100; 12'd90 : mem_out_dec = 6'b001100; 12'd91 : mem_out_dec = 6'b001101; 12'd92 : mem_out_dec = 6'b001110; 12'd93 : mem_out_dec = 6'b001111; 12'd94 : mem_out_dec = 6'b001111; 12'd95 : mem_out_dec = 6'b010000; 12'd96 : mem_out_dec = 6'b010001; 12'd97 : mem_out_dec = 6'b010001; 12'd98 : mem_out_dec = 6'b010010; 12'd99 : mem_out_dec = 6'b010010; 12'd100 : mem_out_dec = 6'b010011; 12'd101 : mem_out_dec = 6'b010011; 12'd102 : mem_out_dec = 6'b010100; 12'd103 : mem_out_dec = 6'b010100; 12'd104 : mem_out_dec = 6'b010100; 12'd105 : mem_out_dec = 6'b010101; 12'd106 : mem_out_dec = 6'b010110; 12'd107 : mem_out_dec = 6'b010111; 12'd108 : mem_out_dec = 6'b010111; 12'd109 : mem_out_dec = 6'b011000; 12'd110 : mem_out_dec = 6'b011001; 12'd111 : mem_out_dec = 6'b011001; 12'd112 : mem_out_dec = 6'b011010; 12'd113 : mem_out_dec = 6'b011010; 12'd114 : mem_out_dec = 6'b011011; 12'd115 : mem_out_dec = 6'b011011; 12'd116 : mem_out_dec = 6'b011011; 12'd117 : mem_out_dec = 6'b011011; 12'd118 : mem_out_dec = 6'b011011; 12'd119 : mem_out_dec = 6'b011011; 12'd120 : mem_out_dec = 6'b011011; 12'd121 : mem_out_dec = 6'b011011; 12'd122 : mem_out_dec = 6'b011100; 12'd123 : mem_out_dec = 6'b011101; 12'd124 : mem_out_dec = 6'b011110; 12'd125 : mem_out_dec = 6'b011110; 12'd126 : mem_out_dec = 6'b011111; 12'd127 : mem_out_dec = 6'b100000; 12'd128 : mem_out_dec = 6'b111111; 12'd129 : mem_out_dec = 6'b111111; 12'd130 : mem_out_dec = 6'b111111; 12'd131 : mem_out_dec = 6'b111111; 12'd132 : mem_out_dec = 6'b111111; 12'd133 : mem_out_dec = 6'b111111; 12'd134 : mem_out_dec = 6'b111111; 12'd135 : mem_out_dec = 6'b111111; 12'd136 : mem_out_dec = 6'b000100; 12'd137 : mem_out_dec = 6'b000101; 12'd138 : mem_out_dec = 6'b000101; 12'd139 : mem_out_dec = 6'b000110; 12'd140 : mem_out_dec = 6'b000110; 12'd141 : mem_out_dec = 6'b000111; 12'd142 : mem_out_dec = 6'b001000; 12'd143 : mem_out_dec = 6'b001001; 12'd144 : mem_out_dec = 6'b001001; 12'd145 : mem_out_dec = 6'b001010; 12'd146 : mem_out_dec = 6'b001010; 12'd147 : mem_out_dec = 6'b001010; 12'd148 : mem_out_dec = 6'b001010; 12'd149 : mem_out_dec = 6'b001010; 12'd150 : mem_out_dec = 6'b001010; 12'd151 : mem_out_dec = 6'b001011; 12'd152 : mem_out_dec = 6'b001010; 12'd153 : mem_out_dec = 6'b001011; 12'd154 : mem_out_dec = 6'b001100; 12'd155 : mem_out_dec = 6'b001101; 12'd156 : mem_out_dec = 6'b001101; 12'd157 : mem_out_dec = 6'b001110; 12'd158 : mem_out_dec = 6'b001111; 12'd159 : mem_out_dec = 6'b010000; 12'd160 : mem_out_dec = 6'b010000; 12'd161 : mem_out_dec = 6'b010001; 12'd162 : mem_out_dec = 6'b010001; 12'd163 : mem_out_dec = 6'b010010; 12'd164 : mem_out_dec = 6'b010010; 12'd165 : mem_out_dec = 6'b010011; 12'd166 : mem_out_dec = 6'b010011; 12'd167 : mem_out_dec = 6'b010100; 12'd168 : mem_out_dec = 6'b010100; 12'd169 : mem_out_dec = 6'b010101; 12'd170 : mem_out_dec = 6'b010101; 12'd171 : mem_out_dec = 6'b010110; 12'd172 : mem_out_dec = 6'b010111; 12'd173 : mem_out_dec = 6'b010111; 12'd174 : mem_out_dec = 6'b011000; 12'd175 : mem_out_dec = 6'b011001; 12'd176 : mem_out_dec = 6'b011001; 12'd177 : mem_out_dec = 6'b011010; 12'd178 : mem_out_dec = 6'b011010; 12'd179 : mem_out_dec = 6'b011010; 12'd180 : mem_out_dec = 6'b011010; 12'd181 : mem_out_dec = 6'b011010; 12'd182 : mem_out_dec = 6'b011010; 12'd183 : mem_out_dec = 6'b011010; 12'd184 : mem_out_dec = 6'b011010; 12'd185 : mem_out_dec = 6'b011011; 12'd186 : mem_out_dec = 6'b011100; 12'd187 : mem_out_dec = 6'b011100; 12'd188 : mem_out_dec = 6'b011101; 12'd189 : mem_out_dec = 6'b011110; 12'd190 : mem_out_dec = 6'b011111; 12'd191 : mem_out_dec = 6'b100000; 12'd192 : mem_out_dec = 6'b111111; 12'd193 : mem_out_dec = 6'b111111; 12'd194 : mem_out_dec = 6'b111111; 12'd195 : mem_out_dec = 6'b111111; 12'd196 : mem_out_dec = 6'b111111; 12'd197 : mem_out_dec = 6'b111111; 12'd198 : mem_out_dec = 6'b111111; 12'd199 : mem_out_dec = 6'b111111; 12'd200 : mem_out_dec = 6'b111111; 12'd201 : mem_out_dec = 6'b000100; 12'd202 : mem_out_dec = 6'b000100; 12'd203 : mem_out_dec = 6'b000101; 12'd204 : mem_out_dec = 6'b000110; 12'd205 : mem_out_dec = 6'b000111; 12'd206 : mem_out_dec = 6'b001000; 12'd207 : mem_out_dec = 6'b001000; 12'd208 : mem_out_dec = 6'b001001; 12'd209 : mem_out_dec = 6'b001001; 12'd210 : mem_out_dec = 6'b001001; 12'd211 : mem_out_dec = 6'b001001; 12'd212 : mem_out_dec = 6'b001001; 12'd213 : mem_out_dec = 6'b001001; 12'd214 : mem_out_dec = 6'b001001; 12'd215 : mem_out_dec = 6'b001010; 12'd216 : mem_out_dec = 6'b001010; 12'd217 : mem_out_dec = 6'b001011; 12'd218 : mem_out_dec = 6'b001011; 12'd219 : mem_out_dec = 6'b001100; 12'd220 : mem_out_dec = 6'b001101; 12'd221 : mem_out_dec = 6'b001110; 12'd222 : mem_out_dec = 6'b001111; 12'd223 : mem_out_dec = 6'b001111; 12'd224 : mem_out_dec = 6'b010000; 12'd225 : mem_out_dec = 6'b010000; 12'd226 : mem_out_dec = 6'b010001; 12'd227 : mem_out_dec = 6'b010001; 12'd228 : mem_out_dec = 6'b010010; 12'd229 : mem_out_dec = 6'b010010; 12'd230 : mem_out_dec = 6'b010011; 12'd231 : mem_out_dec = 6'b010011; 12'd232 : mem_out_dec = 6'b010011; 12'd233 : mem_out_dec = 6'b010100; 12'd234 : mem_out_dec = 6'b010100; 12'd235 : mem_out_dec = 6'b010101; 12'd236 : mem_out_dec = 6'b010110; 12'd237 : mem_out_dec = 6'b010111; 12'd238 : mem_out_dec = 6'b011000; 12'd239 : mem_out_dec = 6'b011000; 12'd240 : mem_out_dec = 6'b011001; 12'd241 : mem_out_dec = 6'b011001; 12'd242 : mem_out_dec = 6'b011001; 12'd243 : mem_out_dec = 6'b011001; 12'd244 : mem_out_dec = 6'b011001; 12'd245 : mem_out_dec = 6'b011001; 12'd246 : mem_out_dec = 6'b011001; 12'd247 : mem_out_dec = 6'b011001; 12'd248 : mem_out_dec = 6'b011010; 12'd249 : mem_out_dec = 6'b011010; 12'd250 : mem_out_dec = 6'b011011; 12'd251 : mem_out_dec = 6'b011100; 12'd252 : mem_out_dec = 6'b011101; 12'd253 : mem_out_dec = 6'b011110; 12'd254 : mem_out_dec = 6'b011110; 12'd255 : mem_out_dec = 6'b011111; 12'd256 : mem_out_dec = 6'b111111; 12'd257 : mem_out_dec = 6'b111111; 12'd258 : mem_out_dec = 6'b111111; 12'd259 : mem_out_dec = 6'b111111; 12'd260 : mem_out_dec = 6'b111111; 12'd261 : mem_out_dec = 6'b111111; 12'd262 : mem_out_dec = 6'b111111; 12'd263 : mem_out_dec = 6'b111111; 12'd264 : mem_out_dec = 6'b111111; 12'd265 : mem_out_dec = 6'b111111; 12'd266 : mem_out_dec = 6'b000100; 12'd267 : mem_out_dec = 6'b000101; 12'd268 : mem_out_dec = 6'b000110; 12'd269 : mem_out_dec = 6'b000110; 12'd270 : mem_out_dec = 6'b000111; 12'd271 : mem_out_dec = 6'b001000; 12'd272 : mem_out_dec = 6'b001000; 12'd273 : mem_out_dec = 6'b001000; 12'd274 : mem_out_dec = 6'b001000; 12'd275 : mem_out_dec = 6'b001000; 12'd276 : mem_out_dec = 6'b001000; 12'd277 : mem_out_dec = 6'b001000; 12'd278 : mem_out_dec = 6'b001000; 12'd279 : mem_out_dec = 6'b001001; 12'd280 : mem_out_dec = 6'b001001; 12'd281 : mem_out_dec = 6'b001010; 12'd282 : mem_out_dec = 6'b001011; 12'd283 : mem_out_dec = 6'b001100; 12'd284 : mem_out_dec = 6'b001101; 12'd285 : mem_out_dec = 6'b001101; 12'd286 : mem_out_dec = 6'b001110; 12'd287 : mem_out_dec = 6'b001111; 12'd288 : mem_out_dec = 6'b001111; 12'd289 : mem_out_dec = 6'b010000; 12'd290 : mem_out_dec = 6'b010000; 12'd291 : mem_out_dec = 6'b010001; 12'd292 : mem_out_dec = 6'b010001; 12'd293 : mem_out_dec = 6'b010010; 12'd294 : mem_out_dec = 6'b010010; 12'd295 : mem_out_dec = 6'b010011; 12'd296 : mem_out_dec = 6'b010010; 12'd297 : mem_out_dec = 6'b010011; 12'd298 : mem_out_dec = 6'b010100; 12'd299 : mem_out_dec = 6'b010101; 12'd300 : mem_out_dec = 6'b010110; 12'd301 : mem_out_dec = 6'b010110; 12'd302 : mem_out_dec = 6'b010111; 12'd303 : mem_out_dec = 6'b011000; 12'd304 : mem_out_dec = 6'b011000; 12'd305 : mem_out_dec = 6'b011000; 12'd306 : mem_out_dec = 6'b011000; 12'd307 : mem_out_dec = 6'b011000; 12'd308 : mem_out_dec = 6'b011000; 12'd309 : mem_out_dec = 6'b011000; 12'd310 : mem_out_dec = 6'b011000; 12'd311 : mem_out_dec = 6'b011001; 12'd312 : mem_out_dec = 6'b011001; 12'd313 : mem_out_dec = 6'b011010; 12'd314 : mem_out_dec = 6'b011011; 12'd315 : mem_out_dec = 6'b011100; 12'd316 : mem_out_dec = 6'b011100; 12'd317 : mem_out_dec = 6'b011101; 12'd318 : mem_out_dec = 6'b011110; 12'd319 : mem_out_dec = 6'b011111; 12'd320 : mem_out_dec = 6'b111111; 12'd321 : mem_out_dec = 6'b111111; 12'd322 : mem_out_dec = 6'b111111; 12'd323 : mem_out_dec = 6'b111111; 12'd324 : mem_out_dec = 6'b111111; 12'd325 : mem_out_dec = 6'b111111; 12'd326 : mem_out_dec = 6'b111111; 12'd327 : mem_out_dec = 6'b111111; 12'd328 : mem_out_dec = 6'b111111; 12'd329 : mem_out_dec = 6'b111111; 12'd330 : mem_out_dec = 6'b111111; 12'd331 : mem_out_dec = 6'b000100; 12'd332 : mem_out_dec = 6'b000101; 12'd333 : mem_out_dec = 6'b000110; 12'd334 : mem_out_dec = 6'b000111; 12'd335 : mem_out_dec = 6'b001000; 12'd336 : mem_out_dec = 6'b000111; 12'd337 : mem_out_dec = 6'b000111; 12'd338 : mem_out_dec = 6'b000111; 12'd339 : mem_out_dec = 6'b000111; 12'd340 : mem_out_dec = 6'b000111; 12'd341 : mem_out_dec = 6'b000111; 12'd342 : mem_out_dec = 6'b001000; 12'd343 : mem_out_dec = 6'b001001; 12'd344 : mem_out_dec = 6'b001001; 12'd345 : mem_out_dec = 6'b001010; 12'd346 : mem_out_dec = 6'b001011; 12'd347 : mem_out_dec = 6'b001011; 12'd348 : mem_out_dec = 6'b001100; 12'd349 : mem_out_dec = 6'b001101; 12'd350 : mem_out_dec = 6'b001110; 12'd351 : mem_out_dec = 6'b001110; 12'd352 : mem_out_dec = 6'b001111; 12'd353 : mem_out_dec = 6'b001111; 12'd354 : mem_out_dec = 6'b010000; 12'd355 : mem_out_dec = 6'b010000; 12'd356 : mem_out_dec = 6'b010001; 12'd357 : mem_out_dec = 6'b010001; 12'd358 : mem_out_dec = 6'b010001; 12'd359 : mem_out_dec = 6'b010010; 12'd360 : mem_out_dec = 6'b010010; 12'd361 : mem_out_dec = 6'b010011; 12'd362 : mem_out_dec = 6'b010100; 12'd363 : mem_out_dec = 6'b010100; 12'd364 : mem_out_dec = 6'b010101; 12'd365 : mem_out_dec = 6'b010110; 12'd366 : mem_out_dec = 6'b010111; 12'd367 : mem_out_dec = 6'b011000; 12'd368 : mem_out_dec = 6'b010111; 12'd369 : mem_out_dec = 6'b010111; 12'd370 : mem_out_dec = 6'b010111; 12'd371 : mem_out_dec = 6'b010111; 12'd372 : mem_out_dec = 6'b010111; 12'd373 : mem_out_dec = 6'b010111; 12'd374 : mem_out_dec = 6'b011000; 12'd375 : mem_out_dec = 6'b011001; 12'd376 : mem_out_dec = 6'b011001; 12'd377 : mem_out_dec = 6'b011010; 12'd378 : mem_out_dec = 6'b011010; 12'd379 : mem_out_dec = 6'b011011; 12'd380 : mem_out_dec = 6'b011100; 12'd381 : mem_out_dec = 6'b011101; 12'd382 : mem_out_dec = 6'b011101; 12'd383 : mem_out_dec = 6'b011110; 12'd384 : mem_out_dec = 6'b111111; 12'd385 : mem_out_dec = 6'b111111; 12'd386 : mem_out_dec = 6'b111111; 12'd387 : mem_out_dec = 6'b111111; 12'd388 : mem_out_dec = 6'b111111; 12'd389 : mem_out_dec = 6'b111111; 12'd390 : mem_out_dec = 6'b111111; 12'd391 : mem_out_dec = 6'b111111; 12'd392 : mem_out_dec = 6'b111111; 12'd393 : mem_out_dec = 6'b111111; 12'd394 : mem_out_dec = 6'b111111; 12'd395 : mem_out_dec = 6'b111111; 12'd396 : mem_out_dec = 6'b000101; 12'd397 : mem_out_dec = 6'b000110; 12'd398 : mem_out_dec = 6'b000110; 12'd399 : mem_out_dec = 6'b000111; 12'd400 : mem_out_dec = 6'b000110; 12'd401 : mem_out_dec = 6'b000110; 12'd402 : mem_out_dec = 6'b000110; 12'd403 : mem_out_dec = 6'b000110; 12'd404 : mem_out_dec = 6'b000110; 12'd405 : mem_out_dec = 6'b000111; 12'd406 : mem_out_dec = 6'b001000; 12'd407 : mem_out_dec = 6'b001000; 12'd408 : mem_out_dec = 6'b001001; 12'd409 : mem_out_dec = 6'b001001; 12'd410 : mem_out_dec = 6'b001010; 12'd411 : mem_out_dec = 6'b001011; 12'd412 : mem_out_dec = 6'b001100; 12'd413 : mem_out_dec = 6'b001100; 12'd414 : mem_out_dec = 6'b001101; 12'd415 : mem_out_dec = 6'b001110; 12'd416 : mem_out_dec = 6'b001110; 12'd417 : mem_out_dec = 6'b001111; 12'd418 : mem_out_dec = 6'b001111; 12'd419 : mem_out_dec = 6'b010000; 12'd420 : mem_out_dec = 6'b010000; 12'd421 : mem_out_dec = 6'b010000; 12'd422 : mem_out_dec = 6'b010001; 12'd423 : mem_out_dec = 6'b010001; 12'd424 : mem_out_dec = 6'b010010; 12'd425 : mem_out_dec = 6'b010011; 12'd426 : mem_out_dec = 6'b010011; 12'd427 : mem_out_dec = 6'b010100; 12'd428 : mem_out_dec = 6'b010101; 12'd429 : mem_out_dec = 6'b010110; 12'd430 : mem_out_dec = 6'b010111; 12'd431 : mem_out_dec = 6'b010111; 12'd432 : mem_out_dec = 6'b010110; 12'd433 : mem_out_dec = 6'b010110; 12'd434 : mem_out_dec = 6'b010110; 12'd435 : mem_out_dec = 6'b010110; 12'd436 : mem_out_dec = 6'b010110; 12'd437 : mem_out_dec = 6'b010111; 12'd438 : mem_out_dec = 6'b010111; 12'd439 : mem_out_dec = 6'b011000; 12'd440 : mem_out_dec = 6'b011001; 12'd441 : mem_out_dec = 6'b011001; 12'd442 : mem_out_dec = 6'b011010; 12'd443 : mem_out_dec = 6'b011011; 12'd444 : mem_out_dec = 6'b011011; 12'd445 : mem_out_dec = 6'b011100; 12'd446 : mem_out_dec = 6'b011101; 12'd447 : mem_out_dec = 6'b011110; 12'd448 : mem_out_dec = 6'b111111; 12'd449 : mem_out_dec = 6'b111111; 12'd450 : mem_out_dec = 6'b111111; 12'd451 : mem_out_dec = 6'b111111; 12'd452 : mem_out_dec = 6'b111111; 12'd453 : mem_out_dec = 6'b111111; 12'd454 : mem_out_dec = 6'b111111; 12'd455 : mem_out_dec = 6'b111111; 12'd456 : mem_out_dec = 6'b111111; 12'd457 : mem_out_dec = 6'b111111; 12'd458 : mem_out_dec = 6'b111111; 12'd459 : mem_out_dec = 6'b111111; 12'd460 : mem_out_dec = 6'b111111; 12'd461 : mem_out_dec = 6'b000101; 12'd462 : mem_out_dec = 6'b000110; 12'd463 : mem_out_dec = 6'b000110; 12'd464 : mem_out_dec = 6'b000110; 12'd465 : mem_out_dec = 6'b000110; 12'd466 : mem_out_dec = 6'b000110; 12'd467 : mem_out_dec = 6'b000110; 12'd468 : mem_out_dec = 6'b000110; 12'd469 : mem_out_dec = 6'b000111; 12'd470 : mem_out_dec = 6'b000111; 12'd471 : mem_out_dec = 6'b001000; 12'd472 : mem_out_dec = 6'b001000; 12'd473 : mem_out_dec = 6'b001001; 12'd474 : mem_out_dec = 6'b001010; 12'd475 : mem_out_dec = 6'b001011; 12'd476 : mem_out_dec = 6'b001011; 12'd477 : mem_out_dec = 6'b001100; 12'd478 : mem_out_dec = 6'b001101; 12'd479 : mem_out_dec = 6'b001110; 12'd480 : mem_out_dec = 6'b001110; 12'd481 : mem_out_dec = 6'b001110; 12'd482 : mem_out_dec = 6'b001111; 12'd483 : mem_out_dec = 6'b001111; 12'd484 : mem_out_dec = 6'b010000; 12'd485 : mem_out_dec = 6'b010000; 12'd486 : mem_out_dec = 6'b010000; 12'd487 : mem_out_dec = 6'b010001; 12'd488 : mem_out_dec = 6'b010001; 12'd489 : mem_out_dec = 6'b010010; 12'd490 : mem_out_dec = 6'b010011; 12'd491 : mem_out_dec = 6'b010100; 12'd492 : mem_out_dec = 6'b010101; 12'd493 : mem_out_dec = 6'b010101; 12'd494 : mem_out_dec = 6'b010110; 12'd495 : mem_out_dec = 6'b010110; 12'd496 : mem_out_dec = 6'b010110; 12'd497 : mem_out_dec = 6'b010110; 12'd498 : mem_out_dec = 6'b010101; 12'd499 : mem_out_dec = 6'b010101; 12'd500 : mem_out_dec = 6'b010110; 12'd501 : mem_out_dec = 6'b010111; 12'd502 : mem_out_dec = 6'b010111; 12'd503 : mem_out_dec = 6'b011000; 12'd504 : mem_out_dec = 6'b011000; 12'd505 : mem_out_dec = 6'b011001; 12'd506 : mem_out_dec = 6'b011010; 12'd507 : mem_out_dec = 6'b011010; 12'd508 : mem_out_dec = 6'b011011; 12'd509 : mem_out_dec = 6'b011100; 12'd510 : mem_out_dec = 6'b011101; 12'd511 : mem_out_dec = 6'b011101; 12'd512 : mem_out_dec = 6'b111111; 12'd513 : mem_out_dec = 6'b111111; 12'd514 : mem_out_dec = 6'b111111; 12'd515 : mem_out_dec = 6'b111111; 12'd516 : mem_out_dec = 6'b111111; 12'd517 : mem_out_dec = 6'b111111; 12'd518 : mem_out_dec = 6'b111111; 12'd519 : mem_out_dec = 6'b111111; 12'd520 : mem_out_dec = 6'b111111; 12'd521 : mem_out_dec = 6'b111111; 12'd522 : mem_out_dec = 6'b111111; 12'd523 : mem_out_dec = 6'b111111; 12'd524 : mem_out_dec = 6'b111111; 12'd525 : mem_out_dec = 6'b111111; 12'd526 : mem_out_dec = 6'b000100; 12'd527 : mem_out_dec = 6'b000101; 12'd528 : mem_out_dec = 6'b000100; 12'd529 : mem_out_dec = 6'b000100; 12'd530 : mem_out_dec = 6'b000100; 12'd531 : mem_out_dec = 6'b000101; 12'd532 : mem_out_dec = 6'b000101; 12'd533 : mem_out_dec = 6'b000110; 12'd534 : mem_out_dec = 6'b000111; 12'd535 : mem_out_dec = 6'b000111; 12'd536 : mem_out_dec = 6'b000111; 12'd537 : mem_out_dec = 6'b001000; 12'd538 : mem_out_dec = 6'b001001; 12'd539 : mem_out_dec = 6'b001010; 12'd540 : mem_out_dec = 6'b001011; 12'd541 : mem_out_dec = 6'b001011; 12'd542 : mem_out_dec = 6'b001100; 12'd543 : mem_out_dec = 6'b001101; 12'd544 : mem_out_dec = 6'b001101; 12'd545 : mem_out_dec = 6'b001101; 12'd546 : mem_out_dec = 6'b001110; 12'd547 : mem_out_dec = 6'b001110; 12'd548 : mem_out_dec = 6'b001110; 12'd549 : mem_out_dec = 6'b001111; 12'd550 : mem_out_dec = 6'b010000; 12'd551 : mem_out_dec = 6'b010000; 12'd552 : mem_out_dec = 6'b010001; 12'd553 : mem_out_dec = 6'b010001; 12'd554 : mem_out_dec = 6'b010010; 12'd555 : mem_out_dec = 6'b010010; 12'd556 : mem_out_dec = 6'b010011; 12'd557 : mem_out_dec = 6'b010100; 12'd558 : mem_out_dec = 6'b010100; 12'd559 : mem_out_dec = 6'b010100; 12'd560 : mem_out_dec = 6'b010100; 12'd561 : mem_out_dec = 6'b010100; 12'd562 : mem_out_dec = 6'b010100; 12'd563 : mem_out_dec = 6'b010101; 12'd564 : mem_out_dec = 6'b010101; 12'd565 : mem_out_dec = 6'b010110; 12'd566 : mem_out_dec = 6'b010111; 12'd567 : mem_out_dec = 6'b010111; 12'd568 : mem_out_dec = 6'b010111; 12'd569 : mem_out_dec = 6'b011000; 12'd570 : mem_out_dec = 6'b011001; 12'd571 : mem_out_dec = 6'b011010; 12'd572 : mem_out_dec = 6'b011010; 12'd573 : mem_out_dec = 6'b011011; 12'd574 : mem_out_dec = 6'b011100; 12'd575 : mem_out_dec = 6'b011101; 12'd576 : mem_out_dec = 6'b111111; 12'd577 : mem_out_dec = 6'b111111; 12'd578 : mem_out_dec = 6'b111111; 12'd579 : mem_out_dec = 6'b111111; 12'd580 : mem_out_dec = 6'b111111; 12'd581 : mem_out_dec = 6'b111111; 12'd582 : mem_out_dec = 6'b111111; 12'd583 : mem_out_dec = 6'b111111; 12'd584 : mem_out_dec = 6'b111111; 12'd585 : mem_out_dec = 6'b111111; 12'd586 : mem_out_dec = 6'b111111; 12'd587 : mem_out_dec = 6'b111111; 12'd588 : mem_out_dec = 6'b111111; 12'd589 : mem_out_dec = 6'b111111; 12'd590 : mem_out_dec = 6'b111111; 12'd591 : mem_out_dec = 6'b000100; 12'd592 : mem_out_dec = 6'b000011; 12'd593 : mem_out_dec = 6'b000011; 12'd594 : mem_out_dec = 6'b000100; 12'd595 : mem_out_dec = 6'b000101; 12'd596 : mem_out_dec = 6'b000101; 12'd597 : mem_out_dec = 6'b000110; 12'd598 : mem_out_dec = 6'b000110; 12'd599 : mem_out_dec = 6'b000111; 12'd600 : mem_out_dec = 6'b000111; 12'd601 : mem_out_dec = 6'b001000; 12'd602 : mem_out_dec = 6'b001001; 12'd603 : mem_out_dec = 6'b001010; 12'd604 : mem_out_dec = 6'b001010; 12'd605 : mem_out_dec = 6'b001011; 12'd606 : mem_out_dec = 6'b001100; 12'd607 : mem_out_dec = 6'b001101; 12'd608 : mem_out_dec = 6'b001101; 12'd609 : mem_out_dec = 6'b001101; 12'd610 : mem_out_dec = 6'b001110; 12'd611 : mem_out_dec = 6'b001110; 12'd612 : mem_out_dec = 6'b001110; 12'd613 : mem_out_dec = 6'b001111; 12'd614 : mem_out_dec = 6'b010000; 12'd615 : mem_out_dec = 6'b010000; 12'd616 : mem_out_dec = 6'b010000; 12'd617 : mem_out_dec = 6'b010001; 12'd618 : mem_out_dec = 6'b010001; 12'd619 : mem_out_dec = 6'b010010; 12'd620 : mem_out_dec = 6'b010010; 12'd621 : mem_out_dec = 6'b010011; 12'd622 : mem_out_dec = 6'b010011; 12'd623 : mem_out_dec = 6'b010100; 12'd624 : mem_out_dec = 6'b010011; 12'd625 : mem_out_dec = 6'b010011; 12'd626 : mem_out_dec = 6'b010100; 12'd627 : mem_out_dec = 6'b010100; 12'd628 : mem_out_dec = 6'b010101; 12'd629 : mem_out_dec = 6'b010110; 12'd630 : mem_out_dec = 6'b010110; 12'd631 : mem_out_dec = 6'b010111; 12'd632 : mem_out_dec = 6'b010111; 12'd633 : mem_out_dec = 6'b011000; 12'd634 : mem_out_dec = 6'b011001; 12'd635 : mem_out_dec = 6'b011001; 12'd636 : mem_out_dec = 6'b011010; 12'd637 : mem_out_dec = 6'b011011; 12'd638 : mem_out_dec = 6'b011100; 12'd639 : mem_out_dec = 6'b011100; 12'd640 : mem_out_dec = 6'b111111; 12'd641 : mem_out_dec = 6'b111111; 12'd642 : mem_out_dec = 6'b111111; 12'd643 : mem_out_dec = 6'b111111; 12'd644 : mem_out_dec = 6'b111111; 12'd645 : mem_out_dec = 6'b111111; 12'd646 : mem_out_dec = 6'b111111; 12'd647 : mem_out_dec = 6'b111111; 12'd648 : mem_out_dec = 6'b111111; 12'd649 : mem_out_dec = 6'b111111; 12'd650 : mem_out_dec = 6'b111111; 12'd651 : mem_out_dec = 6'b111111; 12'd652 : mem_out_dec = 6'b111111; 12'd653 : mem_out_dec = 6'b111111; 12'd654 : mem_out_dec = 6'b111111; 12'd655 : mem_out_dec = 6'b111111; 12'd656 : mem_out_dec = 6'b000011; 12'd657 : mem_out_dec = 6'b000011; 12'd658 : mem_out_dec = 6'b000100; 12'd659 : mem_out_dec = 6'b000100; 12'd660 : mem_out_dec = 6'b000101; 12'd661 : mem_out_dec = 6'b000110; 12'd662 : mem_out_dec = 6'b000110; 12'd663 : mem_out_dec = 6'b000111; 12'd664 : mem_out_dec = 6'b000111; 12'd665 : mem_out_dec = 6'b001000; 12'd666 : mem_out_dec = 6'b001001; 12'd667 : mem_out_dec = 6'b001001; 12'd668 : mem_out_dec = 6'b001010; 12'd669 : mem_out_dec = 6'b001011; 12'd670 : mem_out_dec = 6'b001100; 12'd671 : mem_out_dec = 6'b001100; 12'd672 : mem_out_dec = 6'b001100; 12'd673 : mem_out_dec = 6'b001101; 12'd674 : mem_out_dec = 6'b001101; 12'd675 : mem_out_dec = 6'b001101; 12'd676 : mem_out_dec = 6'b001110; 12'd677 : mem_out_dec = 6'b001111; 12'd678 : mem_out_dec = 6'b001111; 12'd679 : mem_out_dec = 6'b010000; 12'd680 : mem_out_dec = 6'b010000; 12'd681 : mem_out_dec = 6'b010000; 12'd682 : mem_out_dec = 6'b010001; 12'd683 : mem_out_dec = 6'b010001; 12'd684 : mem_out_dec = 6'b010010; 12'd685 : mem_out_dec = 6'b010010; 12'd686 : mem_out_dec = 6'b010011; 12'd687 : mem_out_dec = 6'b010011; 12'd688 : mem_out_dec = 6'b010011; 12'd689 : mem_out_dec = 6'b010011; 12'd690 : mem_out_dec = 6'b010100; 12'd691 : mem_out_dec = 6'b010100; 12'd692 : mem_out_dec = 6'b010101; 12'd693 : mem_out_dec = 6'b010101; 12'd694 : mem_out_dec = 6'b010110; 12'd695 : mem_out_dec = 6'b010111; 12'd696 : mem_out_dec = 6'b010111; 12'd697 : mem_out_dec = 6'b011000; 12'd698 : mem_out_dec = 6'b011000; 12'd699 : mem_out_dec = 6'b011001; 12'd700 : mem_out_dec = 6'b011010; 12'd701 : mem_out_dec = 6'b011011; 12'd702 : mem_out_dec = 6'b011011; 12'd703 : mem_out_dec = 6'b011100; 12'd704 : mem_out_dec = 6'b111111; 12'd705 : mem_out_dec = 6'b111111; 12'd706 : mem_out_dec = 6'b111111; 12'd707 : mem_out_dec = 6'b111111; 12'd708 : mem_out_dec = 6'b111111; 12'd709 : mem_out_dec = 6'b111111; 12'd710 : mem_out_dec = 6'b111111; 12'd711 : mem_out_dec = 6'b111111; 12'd712 : mem_out_dec = 6'b111111; 12'd713 : mem_out_dec = 6'b111111; 12'd714 : mem_out_dec = 6'b111111; 12'd715 : mem_out_dec = 6'b111111; 12'd716 : mem_out_dec = 6'b111111; 12'd717 : mem_out_dec = 6'b111111; 12'd718 : mem_out_dec = 6'b111111; 12'd719 : mem_out_dec = 6'b111111; 12'd720 : mem_out_dec = 6'b111111; 12'd721 : mem_out_dec = 6'b000011; 12'd722 : mem_out_dec = 6'b000100; 12'd723 : mem_out_dec = 6'b000100; 12'd724 : mem_out_dec = 6'b000101; 12'd725 : mem_out_dec = 6'b000101; 12'd726 : mem_out_dec = 6'b000110; 12'd727 : mem_out_dec = 6'b000111; 12'd728 : mem_out_dec = 6'b000111; 12'd729 : mem_out_dec = 6'b000111; 12'd730 : mem_out_dec = 6'b001000; 12'd731 : mem_out_dec = 6'b001001; 12'd732 : mem_out_dec = 6'b001010; 12'd733 : mem_out_dec = 6'b001011; 12'd734 : mem_out_dec = 6'b001011; 12'd735 : mem_out_dec = 6'b001100; 12'd736 : mem_out_dec = 6'b001100; 12'd737 : mem_out_dec = 6'b001101; 12'd738 : mem_out_dec = 6'b001101; 12'd739 : mem_out_dec = 6'b001101; 12'd740 : mem_out_dec = 6'b001110; 12'd741 : mem_out_dec = 6'b001110; 12'd742 : mem_out_dec = 6'b001111; 12'd743 : mem_out_dec = 6'b010000; 12'd744 : mem_out_dec = 6'b001111; 12'd745 : mem_out_dec = 6'b010000; 12'd746 : mem_out_dec = 6'b010000; 12'd747 : mem_out_dec = 6'b010001; 12'd748 : mem_out_dec = 6'b010001; 12'd749 : mem_out_dec = 6'b010010; 12'd750 : mem_out_dec = 6'b010010; 12'd751 : mem_out_dec = 6'b010011; 12'd752 : mem_out_dec = 6'b010010; 12'd753 : mem_out_dec = 6'b010011; 12'd754 : mem_out_dec = 6'b010011; 12'd755 : mem_out_dec = 6'b010100; 12'd756 : mem_out_dec = 6'b010101; 12'd757 : mem_out_dec = 6'b010101; 12'd758 : mem_out_dec = 6'b010110; 12'd759 : mem_out_dec = 6'b010110; 12'd760 : mem_out_dec = 6'b010111; 12'd761 : mem_out_dec = 6'b010111; 12'd762 : mem_out_dec = 6'b011000; 12'd763 : mem_out_dec = 6'b011001; 12'd764 : mem_out_dec = 6'b011010; 12'd765 : mem_out_dec = 6'b011010; 12'd766 : mem_out_dec = 6'b011011; 12'd767 : mem_out_dec = 6'b011100; 12'd768 : mem_out_dec = 6'b111111; 12'd769 : mem_out_dec = 6'b111111; 12'd770 : mem_out_dec = 6'b111111; 12'd771 : mem_out_dec = 6'b111111; 12'd772 : mem_out_dec = 6'b111111; 12'd773 : mem_out_dec = 6'b111111; 12'd774 : mem_out_dec = 6'b111111; 12'd775 : mem_out_dec = 6'b111111; 12'd776 : mem_out_dec = 6'b111111; 12'd777 : mem_out_dec = 6'b111111; 12'd778 : mem_out_dec = 6'b111111; 12'd779 : mem_out_dec = 6'b111111; 12'd780 : mem_out_dec = 6'b111111; 12'd781 : mem_out_dec = 6'b111111; 12'd782 : mem_out_dec = 6'b111111; 12'd783 : mem_out_dec = 6'b111111; 12'd784 : mem_out_dec = 6'b111111; 12'd785 : mem_out_dec = 6'b111111; 12'd786 : mem_out_dec = 6'b000011; 12'd787 : mem_out_dec = 6'b000100; 12'd788 : mem_out_dec = 6'b000101; 12'd789 : mem_out_dec = 6'b000101; 12'd790 : mem_out_dec = 6'b000110; 12'd791 : mem_out_dec = 6'b000110; 12'd792 : mem_out_dec = 6'b000110; 12'd793 : mem_out_dec = 6'b000111; 12'd794 : mem_out_dec = 6'b001000; 12'd795 : mem_out_dec = 6'b001001; 12'd796 : mem_out_dec = 6'b001010; 12'd797 : mem_out_dec = 6'b001010; 12'd798 : mem_out_dec = 6'b001011; 12'd799 : mem_out_dec = 6'b001100; 12'd800 : mem_out_dec = 6'b001100; 12'd801 : mem_out_dec = 6'b001100; 12'd802 : mem_out_dec = 6'b001101; 12'd803 : mem_out_dec = 6'b001101; 12'd804 : mem_out_dec = 6'b001110; 12'd805 : mem_out_dec = 6'b001110; 12'd806 : mem_out_dec = 6'b001111; 12'd807 : mem_out_dec = 6'b010000; 12'd808 : mem_out_dec = 6'b001111; 12'd809 : mem_out_dec = 6'b001111; 12'd810 : mem_out_dec = 6'b010000; 12'd811 : mem_out_dec = 6'b010000; 12'd812 : mem_out_dec = 6'b010001; 12'd813 : mem_out_dec = 6'b010001; 12'd814 : mem_out_dec = 6'b010010; 12'd815 : mem_out_dec = 6'b010010; 12'd816 : mem_out_dec = 6'b010010; 12'd817 : mem_out_dec = 6'b010011; 12'd818 : mem_out_dec = 6'b010011; 12'd819 : mem_out_dec = 6'b010100; 12'd820 : mem_out_dec = 6'b010100; 12'd821 : mem_out_dec = 6'b010101; 12'd822 : mem_out_dec = 6'b010110; 12'd823 : mem_out_dec = 6'b010110; 12'd824 : mem_out_dec = 6'b010110; 12'd825 : mem_out_dec = 6'b010111; 12'd826 : mem_out_dec = 6'b011000; 12'd827 : mem_out_dec = 6'b011001; 12'd828 : mem_out_dec = 6'b011001; 12'd829 : mem_out_dec = 6'b011010; 12'd830 : mem_out_dec = 6'b011011; 12'd831 : mem_out_dec = 6'b011100; 12'd832 : mem_out_dec = 6'b111111; 12'd833 : mem_out_dec = 6'b111111; 12'd834 : mem_out_dec = 6'b111111; 12'd835 : mem_out_dec = 6'b111111; 12'd836 : mem_out_dec = 6'b111111; 12'd837 : mem_out_dec = 6'b111111; 12'd838 : mem_out_dec = 6'b111111; 12'd839 : mem_out_dec = 6'b111111; 12'd840 : mem_out_dec = 6'b111111; 12'd841 : mem_out_dec = 6'b111111; 12'd842 : mem_out_dec = 6'b111111; 12'd843 : mem_out_dec = 6'b111111; 12'd844 : mem_out_dec = 6'b111111; 12'd845 : mem_out_dec = 6'b111111; 12'd846 : mem_out_dec = 6'b111111; 12'd847 : mem_out_dec = 6'b111111; 12'd848 : mem_out_dec = 6'b111111; 12'd849 : mem_out_dec = 6'b111111; 12'd850 : mem_out_dec = 6'b111111; 12'd851 : mem_out_dec = 6'b000100; 12'd852 : mem_out_dec = 6'b000100; 12'd853 : mem_out_dec = 6'b000101; 12'd854 : mem_out_dec = 6'b000101; 12'd855 : mem_out_dec = 6'b000110; 12'd856 : mem_out_dec = 6'b000110; 12'd857 : mem_out_dec = 6'b000111; 12'd858 : mem_out_dec = 6'b001000; 12'd859 : mem_out_dec = 6'b001001; 12'd860 : mem_out_dec = 6'b001001; 12'd861 : mem_out_dec = 6'b001010; 12'd862 : mem_out_dec = 6'b001011; 12'd863 : mem_out_dec = 6'b001100; 12'd864 : mem_out_dec = 6'b001100; 12'd865 : mem_out_dec = 6'b001100; 12'd866 : mem_out_dec = 6'b001100; 12'd867 : mem_out_dec = 6'b001101; 12'd868 : mem_out_dec = 6'b001101; 12'd869 : mem_out_dec = 6'b001110; 12'd870 : mem_out_dec = 6'b001111; 12'd871 : mem_out_dec = 6'b001111; 12'd872 : mem_out_dec = 6'b001110; 12'd873 : mem_out_dec = 6'b001111; 12'd874 : mem_out_dec = 6'b001111; 12'd875 : mem_out_dec = 6'b010000; 12'd876 : mem_out_dec = 6'b010000; 12'd877 : mem_out_dec = 6'b010001; 12'd878 : mem_out_dec = 6'b010001; 12'd879 : mem_out_dec = 6'b010010; 12'd880 : mem_out_dec = 6'b010010; 12'd881 : mem_out_dec = 6'b010010; 12'd882 : mem_out_dec = 6'b010011; 12'd883 : mem_out_dec = 6'b010100; 12'd884 : mem_out_dec = 6'b010100; 12'd885 : mem_out_dec = 6'b010101; 12'd886 : mem_out_dec = 6'b010101; 12'd887 : mem_out_dec = 6'b010110; 12'd888 : mem_out_dec = 6'b010110; 12'd889 : mem_out_dec = 6'b010111; 12'd890 : mem_out_dec = 6'b011000; 12'd891 : mem_out_dec = 6'b011000; 12'd892 : mem_out_dec = 6'b011001; 12'd893 : mem_out_dec = 6'b011010; 12'd894 : mem_out_dec = 6'b011011; 12'd895 : mem_out_dec = 6'b011011; 12'd896 : mem_out_dec = 6'b111111; 12'd897 : mem_out_dec = 6'b111111; 12'd898 : mem_out_dec = 6'b111111; 12'd899 : mem_out_dec = 6'b111111; 12'd900 : mem_out_dec = 6'b111111; 12'd901 : mem_out_dec = 6'b111111; 12'd902 : mem_out_dec = 6'b111111; 12'd903 : mem_out_dec = 6'b111111; 12'd904 : mem_out_dec = 6'b111111; 12'd905 : mem_out_dec = 6'b111111; 12'd906 : mem_out_dec = 6'b111111; 12'd907 : mem_out_dec = 6'b111111; 12'd908 : mem_out_dec = 6'b111111; 12'd909 : mem_out_dec = 6'b111111; 12'd910 : mem_out_dec = 6'b111111; 12'd911 : mem_out_dec = 6'b111111; 12'd912 : mem_out_dec = 6'b111111; 12'd913 : mem_out_dec = 6'b111111; 12'd914 : mem_out_dec = 6'b111111; 12'd915 : mem_out_dec = 6'b111111; 12'd916 : mem_out_dec = 6'b000100; 12'd917 : mem_out_dec = 6'b000101; 12'd918 : mem_out_dec = 6'b000101; 12'd919 : mem_out_dec = 6'b000110; 12'd920 : mem_out_dec = 6'b000110; 12'd921 : mem_out_dec = 6'b000111; 12'd922 : mem_out_dec = 6'b001000; 12'd923 : mem_out_dec = 6'b001000; 12'd924 : mem_out_dec = 6'b001001; 12'd925 : mem_out_dec = 6'b001010; 12'd926 : mem_out_dec = 6'b001011; 12'd927 : mem_out_dec = 6'b001011; 12'd928 : mem_out_dec = 6'b001011; 12'd929 : mem_out_dec = 6'b001100; 12'd930 : mem_out_dec = 6'b001100; 12'd931 : mem_out_dec = 6'b001101; 12'd932 : mem_out_dec = 6'b001101; 12'd933 : mem_out_dec = 6'b001110; 12'd934 : mem_out_dec = 6'b001110; 12'd935 : mem_out_dec = 6'b001111; 12'd936 : mem_out_dec = 6'b001110; 12'd937 : mem_out_dec = 6'b001110; 12'd938 : mem_out_dec = 6'b001111; 12'd939 : mem_out_dec = 6'b001111; 12'd940 : mem_out_dec = 6'b010000; 12'd941 : mem_out_dec = 6'b010000; 12'd942 : mem_out_dec = 6'b010001; 12'd943 : mem_out_dec = 6'b010001; 12'd944 : mem_out_dec = 6'b010010; 12'd945 : mem_out_dec = 6'b010010; 12'd946 : mem_out_dec = 6'b010011; 12'd947 : mem_out_dec = 6'b010011; 12'd948 : mem_out_dec = 6'b010100; 12'd949 : mem_out_dec = 6'b010100; 12'd950 : mem_out_dec = 6'b010101; 12'd951 : mem_out_dec = 6'b010110; 12'd952 : mem_out_dec = 6'b010110; 12'd953 : mem_out_dec = 6'b010111; 12'd954 : mem_out_dec = 6'b010111; 12'd955 : mem_out_dec = 6'b011000; 12'd956 : mem_out_dec = 6'b011001; 12'd957 : mem_out_dec = 6'b011010; 12'd958 : mem_out_dec = 6'b011010; 12'd959 : mem_out_dec = 6'b011011; 12'd960 : mem_out_dec = 6'b111111; 12'd961 : mem_out_dec = 6'b111111; 12'd962 : mem_out_dec = 6'b111111; 12'd963 : mem_out_dec = 6'b111111; 12'd964 : mem_out_dec = 6'b111111; 12'd965 : mem_out_dec = 6'b111111; 12'd966 : mem_out_dec = 6'b111111; 12'd967 : mem_out_dec = 6'b111111; 12'd968 : mem_out_dec = 6'b111111; 12'd969 : mem_out_dec = 6'b111111; 12'd970 : mem_out_dec = 6'b111111; 12'd971 : mem_out_dec = 6'b111111; 12'd972 : mem_out_dec = 6'b111111; 12'd973 : mem_out_dec = 6'b111111; 12'd974 : mem_out_dec = 6'b111111; 12'd975 : mem_out_dec = 6'b111111; 12'd976 : mem_out_dec = 6'b111111; 12'd977 : mem_out_dec = 6'b111111; 12'd978 : mem_out_dec = 6'b111111; 12'd979 : mem_out_dec = 6'b111111; 12'd980 : mem_out_dec = 6'b111111; 12'd981 : mem_out_dec = 6'b000100; 12'd982 : mem_out_dec = 6'b000101; 12'd983 : mem_out_dec = 6'b000110; 12'd984 : mem_out_dec = 6'b000110; 12'd985 : mem_out_dec = 6'b000111; 12'd986 : mem_out_dec = 6'b000111; 12'd987 : mem_out_dec = 6'b001000; 12'd988 : mem_out_dec = 6'b001001; 12'd989 : mem_out_dec = 6'b001010; 12'd990 : mem_out_dec = 6'b001010; 12'd991 : mem_out_dec = 6'b001011; 12'd992 : mem_out_dec = 6'b001011; 12'd993 : mem_out_dec = 6'b001011; 12'd994 : mem_out_dec = 6'b001100; 12'd995 : mem_out_dec = 6'b001100; 12'd996 : mem_out_dec = 6'b001101; 12'd997 : mem_out_dec = 6'b001110; 12'd998 : mem_out_dec = 6'b001110; 12'd999 : mem_out_dec = 6'b001110; 12'd1000 : mem_out_dec = 6'b001101; 12'd1001 : mem_out_dec = 6'b001110; 12'd1002 : mem_out_dec = 6'b001110; 12'd1003 : mem_out_dec = 6'b001111; 12'd1004 : mem_out_dec = 6'b001111; 12'd1005 : mem_out_dec = 6'b010000; 12'd1006 : mem_out_dec = 6'b010000; 12'd1007 : mem_out_dec = 6'b010001; 12'd1008 : mem_out_dec = 6'b010001; 12'd1009 : mem_out_dec = 6'b010010; 12'd1010 : mem_out_dec = 6'b010011; 12'd1011 : mem_out_dec = 6'b010011; 12'd1012 : mem_out_dec = 6'b010100; 12'd1013 : mem_out_dec = 6'b010100; 12'd1014 : mem_out_dec = 6'b010101; 12'd1015 : mem_out_dec = 6'b010110; 12'd1016 : mem_out_dec = 6'b010110; 12'd1017 : mem_out_dec = 6'b010110; 12'd1018 : mem_out_dec = 6'b010111; 12'd1019 : mem_out_dec = 6'b011000; 12'd1020 : mem_out_dec = 6'b011001; 12'd1021 : mem_out_dec = 6'b011001; 12'd1022 : mem_out_dec = 6'b011010; 12'd1023 : mem_out_dec = 6'b011011; 12'd1024 : mem_out_dec = 6'b111111; 12'd1025 : mem_out_dec = 6'b111111; 12'd1026 : mem_out_dec = 6'b111111; 12'd1027 : mem_out_dec = 6'b111111; 12'd1028 : mem_out_dec = 6'b111111; 12'd1029 : mem_out_dec = 6'b111111; 12'd1030 : mem_out_dec = 6'b111111; 12'd1031 : mem_out_dec = 6'b111111; 12'd1032 : mem_out_dec = 6'b111111; 12'd1033 : mem_out_dec = 6'b111111; 12'd1034 : mem_out_dec = 6'b111111; 12'd1035 : mem_out_dec = 6'b111111; 12'd1036 : mem_out_dec = 6'b111111; 12'd1037 : mem_out_dec = 6'b111111; 12'd1038 : mem_out_dec = 6'b111111; 12'd1039 : mem_out_dec = 6'b111111; 12'd1040 : mem_out_dec = 6'b111111; 12'd1041 : mem_out_dec = 6'b111111; 12'd1042 : mem_out_dec = 6'b111111; 12'd1043 : mem_out_dec = 6'b111111; 12'd1044 : mem_out_dec = 6'b111111; 12'd1045 : mem_out_dec = 6'b111111; 12'd1046 : mem_out_dec = 6'b000100; 12'd1047 : mem_out_dec = 6'b000101; 12'd1048 : mem_out_dec = 6'b000101; 12'd1049 : mem_out_dec = 6'b000110; 12'd1050 : mem_out_dec = 6'b000110; 12'd1051 : mem_out_dec = 6'b000111; 12'd1052 : mem_out_dec = 6'b001000; 12'd1053 : mem_out_dec = 6'b001001; 12'd1054 : mem_out_dec = 6'b001001; 12'd1055 : mem_out_dec = 6'b001010; 12'd1056 : mem_out_dec = 6'b001010; 12'd1057 : mem_out_dec = 6'b001011; 12'd1058 : mem_out_dec = 6'b001011; 12'd1059 : mem_out_dec = 6'b001100; 12'd1060 : mem_out_dec = 6'b001100; 12'd1061 : mem_out_dec = 6'b001100; 12'd1062 : mem_out_dec = 6'b001100; 12'd1063 : mem_out_dec = 6'b001100; 12'd1064 : mem_out_dec = 6'b001100; 12'd1065 : mem_out_dec = 6'b001100; 12'd1066 : mem_out_dec = 6'b001101; 12'd1067 : mem_out_dec = 6'b001101; 12'd1068 : mem_out_dec = 6'b001110; 12'd1069 : mem_out_dec = 6'b001111; 12'd1070 : mem_out_dec = 6'b010000; 12'd1071 : mem_out_dec = 6'b010000; 12'd1072 : mem_out_dec = 6'b010001; 12'd1073 : mem_out_dec = 6'b010001; 12'd1074 : mem_out_dec = 6'b010010; 12'd1075 : mem_out_dec = 6'b010010; 12'd1076 : mem_out_dec = 6'b010011; 12'd1077 : mem_out_dec = 6'b010011; 12'd1078 : mem_out_dec = 6'b010100; 12'd1079 : mem_out_dec = 6'b010101; 12'd1080 : mem_out_dec = 6'b010101; 12'd1081 : mem_out_dec = 6'b010110; 12'd1082 : mem_out_dec = 6'b010110; 12'd1083 : mem_out_dec = 6'b010111; 12'd1084 : mem_out_dec = 6'b011000; 12'd1085 : mem_out_dec = 6'b011000; 12'd1086 : mem_out_dec = 6'b011001; 12'd1087 : mem_out_dec = 6'b011010; 12'd1088 : mem_out_dec = 6'b111111; 12'd1089 : mem_out_dec = 6'b111111; 12'd1090 : mem_out_dec = 6'b111111; 12'd1091 : mem_out_dec = 6'b111111; 12'd1092 : mem_out_dec = 6'b111111; 12'd1093 : mem_out_dec = 6'b111111; 12'd1094 : mem_out_dec = 6'b111111; 12'd1095 : mem_out_dec = 6'b111111; 12'd1096 : mem_out_dec = 6'b111111; 12'd1097 : mem_out_dec = 6'b111111; 12'd1098 : mem_out_dec = 6'b111111; 12'd1099 : mem_out_dec = 6'b111111; 12'd1100 : mem_out_dec = 6'b111111; 12'd1101 : mem_out_dec = 6'b111111; 12'd1102 : mem_out_dec = 6'b111111; 12'd1103 : mem_out_dec = 6'b111111; 12'd1104 : mem_out_dec = 6'b111111; 12'd1105 : mem_out_dec = 6'b111111; 12'd1106 : mem_out_dec = 6'b111111; 12'd1107 : mem_out_dec = 6'b111111; 12'd1108 : mem_out_dec = 6'b111111; 12'd1109 : mem_out_dec = 6'b111111; 12'd1110 : mem_out_dec = 6'b111111; 12'd1111 : mem_out_dec = 6'b000100; 12'd1112 : mem_out_dec = 6'b000100; 12'd1113 : mem_out_dec = 6'b000101; 12'd1114 : mem_out_dec = 6'b000110; 12'd1115 : mem_out_dec = 6'b000111; 12'd1116 : mem_out_dec = 6'b000111; 12'd1117 : mem_out_dec = 6'b001000; 12'd1118 : mem_out_dec = 6'b001001; 12'd1119 : mem_out_dec = 6'b001001; 12'd1120 : mem_out_dec = 6'b001010; 12'd1121 : mem_out_dec = 6'b001010; 12'd1122 : mem_out_dec = 6'b001011; 12'd1123 : mem_out_dec = 6'b001011; 12'd1124 : mem_out_dec = 6'b001011; 12'd1125 : mem_out_dec = 6'b001011; 12'd1126 : mem_out_dec = 6'b001011; 12'd1127 : mem_out_dec = 6'b001011; 12'd1128 : mem_out_dec = 6'b001011; 12'd1129 : mem_out_dec = 6'b001011; 12'd1130 : mem_out_dec = 6'b001100; 12'd1131 : mem_out_dec = 6'b001101; 12'd1132 : mem_out_dec = 6'b001110; 12'd1133 : mem_out_dec = 6'b001110; 12'd1134 : mem_out_dec = 6'b001111; 12'd1135 : mem_out_dec = 6'b010000; 12'd1136 : mem_out_dec = 6'b010000; 12'd1137 : mem_out_dec = 6'b010001; 12'd1138 : mem_out_dec = 6'b010001; 12'd1139 : mem_out_dec = 6'b010010; 12'd1140 : mem_out_dec = 6'b010010; 12'd1141 : mem_out_dec = 6'b010011; 12'd1142 : mem_out_dec = 6'b010100; 12'd1143 : mem_out_dec = 6'b010100; 12'd1144 : mem_out_dec = 6'b010100; 12'd1145 : mem_out_dec = 6'b010101; 12'd1146 : mem_out_dec = 6'b010110; 12'd1147 : mem_out_dec = 6'b010110; 12'd1148 : mem_out_dec = 6'b010111; 12'd1149 : mem_out_dec = 6'b011000; 12'd1150 : mem_out_dec = 6'b011000; 12'd1151 : mem_out_dec = 6'b011001; 12'd1152 : mem_out_dec = 6'b111111; 12'd1153 : mem_out_dec = 6'b111111; 12'd1154 : mem_out_dec = 6'b111111; 12'd1155 : mem_out_dec = 6'b111111; 12'd1156 : mem_out_dec = 6'b111111; 12'd1157 : mem_out_dec = 6'b111111; 12'd1158 : mem_out_dec = 6'b111111; 12'd1159 : mem_out_dec = 6'b111111; 12'd1160 : mem_out_dec = 6'b111111; 12'd1161 : mem_out_dec = 6'b111111; 12'd1162 : mem_out_dec = 6'b111111; 12'd1163 : mem_out_dec = 6'b111111; 12'd1164 : mem_out_dec = 6'b111111; 12'd1165 : mem_out_dec = 6'b111111; 12'd1166 : mem_out_dec = 6'b111111; 12'd1167 : mem_out_dec = 6'b111111; 12'd1168 : mem_out_dec = 6'b111111; 12'd1169 : mem_out_dec = 6'b111111; 12'd1170 : mem_out_dec = 6'b111111; 12'd1171 : mem_out_dec = 6'b111111; 12'd1172 : mem_out_dec = 6'b111111; 12'd1173 : mem_out_dec = 6'b111111; 12'd1174 : mem_out_dec = 6'b111111; 12'd1175 : mem_out_dec = 6'b111111; 12'd1176 : mem_out_dec = 6'b000100; 12'd1177 : mem_out_dec = 6'b000101; 12'd1178 : mem_out_dec = 6'b000101; 12'd1179 : mem_out_dec = 6'b000110; 12'd1180 : mem_out_dec = 6'b000111; 12'd1181 : mem_out_dec = 6'b000111; 12'd1182 : mem_out_dec = 6'b001000; 12'd1183 : mem_out_dec = 6'b001001; 12'd1184 : mem_out_dec = 6'b001001; 12'd1185 : mem_out_dec = 6'b001010; 12'd1186 : mem_out_dec = 6'b001010; 12'd1187 : mem_out_dec = 6'b001010; 12'd1188 : mem_out_dec = 6'b001010; 12'd1189 : mem_out_dec = 6'b001010; 12'd1190 : mem_out_dec = 6'b001010; 12'd1191 : mem_out_dec = 6'b001010; 12'd1192 : mem_out_dec = 6'b001010; 12'd1193 : mem_out_dec = 6'b001011; 12'd1194 : mem_out_dec = 6'b001100; 12'd1195 : mem_out_dec = 6'b001100; 12'd1196 : mem_out_dec = 6'b001101; 12'd1197 : mem_out_dec = 6'b001110; 12'd1198 : mem_out_dec = 6'b001111; 12'd1199 : mem_out_dec = 6'b010000; 12'd1200 : mem_out_dec = 6'b010000; 12'd1201 : mem_out_dec = 6'b010000; 12'd1202 : mem_out_dec = 6'b010001; 12'd1203 : mem_out_dec = 6'b010001; 12'd1204 : mem_out_dec = 6'b010010; 12'd1205 : mem_out_dec = 6'b010011; 12'd1206 : mem_out_dec = 6'b010011; 12'd1207 : mem_out_dec = 6'b010100; 12'd1208 : mem_out_dec = 6'b010100; 12'd1209 : mem_out_dec = 6'b010100; 12'd1210 : mem_out_dec = 6'b010101; 12'd1211 : mem_out_dec = 6'b010110; 12'd1212 : mem_out_dec = 6'b010110; 12'd1213 : mem_out_dec = 6'b010111; 12'd1214 : mem_out_dec = 6'b011000; 12'd1215 : mem_out_dec = 6'b011001; 12'd1216 : mem_out_dec = 6'b111111; 12'd1217 : mem_out_dec = 6'b111111; 12'd1218 : mem_out_dec = 6'b111111; 12'd1219 : mem_out_dec = 6'b111111; 12'd1220 : mem_out_dec = 6'b111111; 12'd1221 : mem_out_dec = 6'b111111; 12'd1222 : mem_out_dec = 6'b111111; 12'd1223 : mem_out_dec = 6'b111111; 12'd1224 : mem_out_dec = 6'b111111; 12'd1225 : mem_out_dec = 6'b111111; 12'd1226 : mem_out_dec = 6'b111111; 12'd1227 : mem_out_dec = 6'b111111; 12'd1228 : mem_out_dec = 6'b111111; 12'd1229 : mem_out_dec = 6'b111111; 12'd1230 : mem_out_dec = 6'b111111; 12'd1231 : mem_out_dec = 6'b111111; 12'd1232 : mem_out_dec = 6'b111111; 12'd1233 : mem_out_dec = 6'b111111; 12'd1234 : mem_out_dec = 6'b111111; 12'd1235 : mem_out_dec = 6'b111111; 12'd1236 : mem_out_dec = 6'b111111; 12'd1237 : mem_out_dec = 6'b111111; 12'd1238 : mem_out_dec = 6'b111111; 12'd1239 : mem_out_dec = 6'b111111; 12'd1240 : mem_out_dec = 6'b111111; 12'd1241 : mem_out_dec = 6'b000100; 12'd1242 : mem_out_dec = 6'b000100; 12'd1243 : mem_out_dec = 6'b000101; 12'd1244 : mem_out_dec = 6'b000110; 12'd1245 : mem_out_dec = 6'b000111; 12'd1246 : mem_out_dec = 6'b001000; 12'd1247 : mem_out_dec = 6'b001000; 12'd1248 : mem_out_dec = 6'b001001; 12'd1249 : mem_out_dec = 6'b001001; 12'd1250 : mem_out_dec = 6'b001001; 12'd1251 : mem_out_dec = 6'b001001; 12'd1252 : mem_out_dec = 6'b001001; 12'd1253 : mem_out_dec = 6'b001001; 12'd1254 : mem_out_dec = 6'b001001; 12'd1255 : mem_out_dec = 6'b001001; 12'd1256 : mem_out_dec = 6'b001010; 12'd1257 : mem_out_dec = 6'b001010; 12'd1258 : mem_out_dec = 6'b001011; 12'd1259 : mem_out_dec = 6'b001100; 12'd1260 : mem_out_dec = 6'b001101; 12'd1261 : mem_out_dec = 6'b001110; 12'd1262 : mem_out_dec = 6'b001110; 12'd1263 : mem_out_dec = 6'b001111; 12'd1264 : mem_out_dec = 6'b001111; 12'd1265 : mem_out_dec = 6'b010000; 12'd1266 : mem_out_dec = 6'b010000; 12'd1267 : mem_out_dec = 6'b010001; 12'd1268 : mem_out_dec = 6'b010001; 12'd1269 : mem_out_dec = 6'b010010; 12'd1270 : mem_out_dec = 6'b010011; 12'd1271 : mem_out_dec = 6'b010011; 12'd1272 : mem_out_dec = 6'b010011; 12'd1273 : mem_out_dec = 6'b010100; 12'd1274 : mem_out_dec = 6'b010100; 12'd1275 : mem_out_dec = 6'b010101; 12'd1276 : mem_out_dec = 6'b010110; 12'd1277 : mem_out_dec = 6'b010111; 12'd1278 : mem_out_dec = 6'b011000; 12'd1279 : mem_out_dec = 6'b011000; 12'd1280 : mem_out_dec = 6'b111111; 12'd1281 : mem_out_dec = 6'b111111; 12'd1282 : mem_out_dec = 6'b111111; 12'd1283 : mem_out_dec = 6'b111111; 12'd1284 : mem_out_dec = 6'b111111; 12'd1285 : mem_out_dec = 6'b111111; 12'd1286 : mem_out_dec = 6'b111111; 12'd1287 : mem_out_dec = 6'b111111; 12'd1288 : mem_out_dec = 6'b111111; 12'd1289 : mem_out_dec = 6'b111111; 12'd1290 : mem_out_dec = 6'b111111; 12'd1291 : mem_out_dec = 6'b111111; 12'd1292 : mem_out_dec = 6'b111111; 12'd1293 : mem_out_dec = 6'b111111; 12'd1294 : mem_out_dec = 6'b111111; 12'd1295 : mem_out_dec = 6'b111111; 12'd1296 : mem_out_dec = 6'b111111; 12'd1297 : mem_out_dec = 6'b111111; 12'd1298 : mem_out_dec = 6'b111111; 12'd1299 : mem_out_dec = 6'b111111; 12'd1300 : mem_out_dec = 6'b111111; 12'd1301 : mem_out_dec = 6'b111111; 12'd1302 : mem_out_dec = 6'b111111; 12'd1303 : mem_out_dec = 6'b111111; 12'd1304 : mem_out_dec = 6'b111111; 12'd1305 : mem_out_dec = 6'b111111; 12'd1306 : mem_out_dec = 6'b000100; 12'd1307 : mem_out_dec = 6'b000101; 12'd1308 : mem_out_dec = 6'b000110; 12'd1309 : mem_out_dec = 6'b000110; 12'd1310 : mem_out_dec = 6'b000111; 12'd1311 : mem_out_dec = 6'b001000; 12'd1312 : mem_out_dec = 6'b001000; 12'd1313 : mem_out_dec = 6'b001000; 12'd1314 : mem_out_dec = 6'b001000; 12'd1315 : mem_out_dec = 6'b001000; 12'd1316 : mem_out_dec = 6'b001000; 12'd1317 : mem_out_dec = 6'b001000; 12'd1318 : mem_out_dec = 6'b001000; 12'd1319 : mem_out_dec = 6'b001001; 12'd1320 : mem_out_dec = 6'b001001; 12'd1321 : mem_out_dec = 6'b001010; 12'd1322 : mem_out_dec = 6'b001011; 12'd1323 : mem_out_dec = 6'b001100; 12'd1324 : mem_out_dec = 6'b001100; 12'd1325 : mem_out_dec = 6'b001101; 12'd1326 : mem_out_dec = 6'b001110; 12'd1327 : mem_out_dec = 6'b001111; 12'd1328 : mem_out_dec = 6'b001111; 12'd1329 : mem_out_dec = 6'b001111; 12'd1330 : mem_out_dec = 6'b010000; 12'd1331 : mem_out_dec = 6'b010000; 12'd1332 : mem_out_dec = 6'b010001; 12'd1333 : mem_out_dec = 6'b010001; 12'd1334 : mem_out_dec = 6'b010010; 12'd1335 : mem_out_dec = 6'b010011; 12'd1336 : mem_out_dec = 6'b010010; 12'd1337 : mem_out_dec = 6'b010011; 12'd1338 : mem_out_dec = 6'b010100; 12'd1339 : mem_out_dec = 6'b010101; 12'd1340 : mem_out_dec = 6'b010110; 12'd1341 : mem_out_dec = 6'b010110; 12'd1342 : mem_out_dec = 6'b010111; 12'd1343 : mem_out_dec = 6'b011000; 12'd1344 : mem_out_dec = 6'b111111; 12'd1345 : mem_out_dec = 6'b111111; 12'd1346 : mem_out_dec = 6'b111111; 12'd1347 : mem_out_dec = 6'b111111; 12'd1348 : mem_out_dec = 6'b111111; 12'd1349 : mem_out_dec = 6'b111111; 12'd1350 : mem_out_dec = 6'b111111; 12'd1351 : mem_out_dec = 6'b111111; 12'd1352 : mem_out_dec = 6'b111111; 12'd1353 : mem_out_dec = 6'b111111; 12'd1354 : mem_out_dec = 6'b111111; 12'd1355 : mem_out_dec = 6'b111111; 12'd1356 : mem_out_dec = 6'b111111; 12'd1357 : mem_out_dec = 6'b111111; 12'd1358 : mem_out_dec = 6'b111111; 12'd1359 : mem_out_dec = 6'b111111; 12'd1360 : mem_out_dec = 6'b111111; 12'd1361 : mem_out_dec = 6'b111111; 12'd1362 : mem_out_dec = 6'b111111; 12'd1363 : mem_out_dec = 6'b111111; 12'd1364 : mem_out_dec = 6'b111111; 12'd1365 : mem_out_dec = 6'b111111; 12'd1366 : mem_out_dec = 6'b111111; 12'd1367 : mem_out_dec = 6'b111111; 12'd1368 : mem_out_dec = 6'b111111; 12'd1369 : mem_out_dec = 6'b111111; 12'd1370 : mem_out_dec = 6'b111111; 12'd1371 : mem_out_dec = 6'b000101; 12'd1372 : mem_out_dec = 6'b000101; 12'd1373 : mem_out_dec = 6'b000110; 12'd1374 : mem_out_dec = 6'b000111; 12'd1375 : mem_out_dec = 6'b001000; 12'd1376 : mem_out_dec = 6'b000111; 12'd1377 : mem_out_dec = 6'b000111; 12'd1378 : mem_out_dec = 6'b000111; 12'd1379 : mem_out_dec = 6'b000111; 12'd1380 : mem_out_dec = 6'b000111; 12'd1381 : mem_out_dec = 6'b000111; 12'd1382 : mem_out_dec = 6'b001000; 12'd1383 : mem_out_dec = 6'b001001; 12'd1384 : mem_out_dec = 6'b001001; 12'd1385 : mem_out_dec = 6'b001010; 12'd1386 : mem_out_dec = 6'b001010; 12'd1387 : mem_out_dec = 6'b001011; 12'd1388 : mem_out_dec = 6'b001100; 12'd1389 : mem_out_dec = 6'b001101; 12'd1390 : mem_out_dec = 6'b001110; 12'd1391 : mem_out_dec = 6'b001110; 12'd1392 : mem_out_dec = 6'b001111; 12'd1393 : mem_out_dec = 6'b001111; 12'd1394 : mem_out_dec = 6'b010000; 12'd1395 : mem_out_dec = 6'b010000; 12'd1396 : mem_out_dec = 6'b010001; 12'd1397 : mem_out_dec = 6'b010001; 12'd1398 : mem_out_dec = 6'b010010; 12'd1399 : mem_out_dec = 6'b010010; 12'd1400 : mem_out_dec = 6'b010010; 12'd1401 : mem_out_dec = 6'b010011; 12'd1402 : mem_out_dec = 6'b010100; 12'd1403 : mem_out_dec = 6'b010100; 12'd1404 : mem_out_dec = 6'b010101; 12'd1405 : mem_out_dec = 6'b010110; 12'd1406 : mem_out_dec = 6'b010111; 12'd1407 : mem_out_dec = 6'b010111; 12'd1408 : mem_out_dec = 6'b111111; 12'd1409 : mem_out_dec = 6'b111111; 12'd1410 : mem_out_dec = 6'b111111; 12'd1411 : mem_out_dec = 6'b111111; 12'd1412 : mem_out_dec = 6'b111111; 12'd1413 : mem_out_dec = 6'b111111; 12'd1414 : mem_out_dec = 6'b111111; 12'd1415 : mem_out_dec = 6'b111111; 12'd1416 : mem_out_dec = 6'b111111; 12'd1417 : mem_out_dec = 6'b111111; 12'd1418 : mem_out_dec = 6'b111111; 12'd1419 : mem_out_dec = 6'b111111; 12'd1420 : mem_out_dec = 6'b111111; 12'd1421 : mem_out_dec = 6'b111111; 12'd1422 : mem_out_dec = 6'b111111; 12'd1423 : mem_out_dec = 6'b111111; 12'd1424 : mem_out_dec = 6'b111111; 12'd1425 : mem_out_dec = 6'b111111; 12'd1426 : mem_out_dec = 6'b111111; 12'd1427 : mem_out_dec = 6'b111111; 12'd1428 : mem_out_dec = 6'b111111; 12'd1429 : mem_out_dec = 6'b111111; 12'd1430 : mem_out_dec = 6'b111111; 12'd1431 : mem_out_dec = 6'b111111; 12'd1432 : mem_out_dec = 6'b111111; 12'd1433 : mem_out_dec = 6'b111111; 12'd1434 : mem_out_dec = 6'b111111; 12'd1435 : mem_out_dec = 6'b111111; 12'd1436 : mem_out_dec = 6'b000101; 12'd1437 : mem_out_dec = 6'b000110; 12'd1438 : mem_out_dec = 6'b000111; 12'd1439 : mem_out_dec = 6'b000111; 12'd1440 : mem_out_dec = 6'b000110; 12'd1441 : mem_out_dec = 6'b000110; 12'd1442 : mem_out_dec = 6'b000110; 12'd1443 : mem_out_dec = 6'b000110; 12'd1444 : mem_out_dec = 6'b000110; 12'd1445 : mem_out_dec = 6'b000111; 12'd1446 : mem_out_dec = 6'b000111; 12'd1447 : mem_out_dec = 6'b001000; 12'd1448 : mem_out_dec = 6'b001001; 12'd1449 : mem_out_dec = 6'b001001; 12'd1450 : mem_out_dec = 6'b001010; 12'd1451 : mem_out_dec = 6'b001011; 12'd1452 : mem_out_dec = 6'b001100; 12'd1453 : mem_out_dec = 6'b001100; 12'd1454 : mem_out_dec = 6'b001101; 12'd1455 : mem_out_dec = 6'b001110; 12'd1456 : mem_out_dec = 6'b001110; 12'd1457 : mem_out_dec = 6'b001111; 12'd1458 : mem_out_dec = 6'b001111; 12'd1459 : mem_out_dec = 6'b010000; 12'd1460 : mem_out_dec = 6'b010000; 12'd1461 : mem_out_dec = 6'b010001; 12'd1462 : mem_out_dec = 6'b010001; 12'd1463 : mem_out_dec = 6'b010010; 12'd1464 : mem_out_dec = 6'b010010; 12'd1465 : mem_out_dec = 6'b010011; 12'd1466 : mem_out_dec = 6'b010011; 12'd1467 : mem_out_dec = 6'b010100; 12'd1468 : mem_out_dec = 6'b010101; 12'd1469 : mem_out_dec = 6'b010110; 12'd1470 : mem_out_dec = 6'b010110; 12'd1471 : mem_out_dec = 6'b010111; 12'd1472 : mem_out_dec = 6'b111111; 12'd1473 : mem_out_dec = 6'b111111; 12'd1474 : mem_out_dec = 6'b111111; 12'd1475 : mem_out_dec = 6'b111111; 12'd1476 : mem_out_dec = 6'b111111; 12'd1477 : mem_out_dec = 6'b111111; 12'd1478 : mem_out_dec = 6'b111111; 12'd1479 : mem_out_dec = 6'b111111; 12'd1480 : mem_out_dec = 6'b111111; 12'd1481 : mem_out_dec = 6'b111111; 12'd1482 : mem_out_dec = 6'b111111; 12'd1483 : mem_out_dec = 6'b111111; 12'd1484 : mem_out_dec = 6'b111111; 12'd1485 : mem_out_dec = 6'b111111; 12'd1486 : mem_out_dec = 6'b111111; 12'd1487 : mem_out_dec = 6'b111111; 12'd1488 : mem_out_dec = 6'b111111; 12'd1489 : mem_out_dec = 6'b111111; 12'd1490 : mem_out_dec = 6'b111111; 12'd1491 : mem_out_dec = 6'b111111; 12'd1492 : mem_out_dec = 6'b111111; 12'd1493 : mem_out_dec = 6'b111111; 12'd1494 : mem_out_dec = 6'b111111; 12'd1495 : mem_out_dec = 6'b111111; 12'd1496 : mem_out_dec = 6'b111111; 12'd1497 : mem_out_dec = 6'b111111; 12'd1498 : mem_out_dec = 6'b111111; 12'd1499 : mem_out_dec = 6'b111111; 12'd1500 : mem_out_dec = 6'b111111; 12'd1501 : mem_out_dec = 6'b000101; 12'd1502 : mem_out_dec = 6'b000110; 12'd1503 : mem_out_dec = 6'b000110; 12'd1504 : mem_out_dec = 6'b000110; 12'd1505 : mem_out_dec = 6'b000110; 12'd1506 : mem_out_dec = 6'b000101; 12'd1507 : mem_out_dec = 6'b000101; 12'd1508 : mem_out_dec = 6'b000110; 12'd1509 : mem_out_dec = 6'b000111; 12'd1510 : mem_out_dec = 6'b000111; 12'd1511 : mem_out_dec = 6'b001000; 12'd1512 : mem_out_dec = 6'b001000; 12'd1513 : mem_out_dec = 6'b001001; 12'd1514 : mem_out_dec = 6'b001010; 12'd1515 : mem_out_dec = 6'b001011; 12'd1516 : mem_out_dec = 6'b001011; 12'd1517 : mem_out_dec = 6'b001100; 12'd1518 : mem_out_dec = 6'b001101; 12'd1519 : mem_out_dec = 6'b001110; 12'd1520 : mem_out_dec = 6'b001110; 12'd1521 : mem_out_dec = 6'b001110; 12'd1522 : mem_out_dec = 6'b001111; 12'd1523 : mem_out_dec = 6'b001111; 12'd1524 : mem_out_dec = 6'b010000; 12'd1525 : mem_out_dec = 6'b010000; 12'd1526 : mem_out_dec = 6'b010001; 12'd1527 : mem_out_dec = 6'b010001; 12'd1528 : mem_out_dec = 6'b010001; 12'd1529 : mem_out_dec = 6'b010010; 12'd1530 : mem_out_dec = 6'b010011; 12'd1531 : mem_out_dec = 6'b010100; 12'd1532 : mem_out_dec = 6'b010101; 12'd1533 : mem_out_dec = 6'b010101; 12'd1534 : mem_out_dec = 6'b010110; 12'd1535 : mem_out_dec = 6'b010110; 12'd1536 : mem_out_dec = 6'b111111; 12'd1537 : mem_out_dec = 6'b111111; 12'd1538 : mem_out_dec = 6'b111111; 12'd1539 : mem_out_dec = 6'b111111; 12'd1540 : mem_out_dec = 6'b111111; 12'd1541 : mem_out_dec = 6'b111111; 12'd1542 : mem_out_dec = 6'b111111; 12'd1543 : mem_out_dec = 6'b111111; 12'd1544 : mem_out_dec = 6'b111111; 12'd1545 : mem_out_dec = 6'b111111; 12'd1546 : mem_out_dec = 6'b111111; 12'd1547 : mem_out_dec = 6'b111111; 12'd1548 : mem_out_dec = 6'b111111; 12'd1549 : mem_out_dec = 6'b111111; 12'd1550 : mem_out_dec = 6'b111111; 12'd1551 : mem_out_dec = 6'b111111; 12'd1552 : mem_out_dec = 6'b111111; 12'd1553 : mem_out_dec = 6'b111111; 12'd1554 : mem_out_dec = 6'b111111; 12'd1555 : mem_out_dec = 6'b111111; 12'd1556 : mem_out_dec = 6'b111111; 12'd1557 : mem_out_dec = 6'b111111; 12'd1558 : mem_out_dec = 6'b111111; 12'd1559 : mem_out_dec = 6'b111111; 12'd1560 : mem_out_dec = 6'b111111; 12'd1561 : mem_out_dec = 6'b111111; 12'd1562 : mem_out_dec = 6'b111111; 12'd1563 : mem_out_dec = 6'b111111; 12'd1564 : mem_out_dec = 6'b111111; 12'd1565 : mem_out_dec = 6'b111111; 12'd1566 : mem_out_dec = 6'b000100; 12'd1567 : mem_out_dec = 6'b000100; 12'd1568 : mem_out_dec = 6'b000100; 12'd1569 : mem_out_dec = 6'b000100; 12'd1570 : mem_out_dec = 6'b000100; 12'd1571 : mem_out_dec = 6'b000101; 12'd1572 : mem_out_dec = 6'b000101; 12'd1573 : mem_out_dec = 6'b000110; 12'd1574 : mem_out_dec = 6'b000111; 12'd1575 : mem_out_dec = 6'b000111; 12'd1576 : mem_out_dec = 6'b000111; 12'd1577 : mem_out_dec = 6'b001000; 12'd1578 : mem_out_dec = 6'b001001; 12'd1579 : mem_out_dec = 6'b001010; 12'd1580 : mem_out_dec = 6'b001010; 12'd1581 : mem_out_dec = 6'b001011; 12'd1582 : mem_out_dec = 6'b001100; 12'd1583 : mem_out_dec = 6'b001101; 12'd1584 : mem_out_dec = 6'b001101; 12'd1585 : mem_out_dec = 6'b001101; 12'd1586 : mem_out_dec = 6'b001110; 12'd1587 : mem_out_dec = 6'b001110; 12'd1588 : mem_out_dec = 6'b001111; 12'd1589 : mem_out_dec = 6'b001111; 12'd1590 : mem_out_dec = 6'b010000; 12'd1591 : mem_out_dec = 6'b010001; 12'd1592 : mem_out_dec = 6'b010001; 12'd1593 : mem_out_dec = 6'b010001; 12'd1594 : mem_out_dec = 6'b010010; 12'd1595 : mem_out_dec = 6'b010010; 12'd1596 : mem_out_dec = 6'b010011; 12'd1597 : mem_out_dec = 6'b010011; 12'd1598 : mem_out_dec = 6'b010100; 12'd1599 : mem_out_dec = 6'b010100; 12'd1600 : mem_out_dec = 6'b111111; 12'd1601 : mem_out_dec = 6'b111111; 12'd1602 : mem_out_dec = 6'b111111; 12'd1603 : mem_out_dec = 6'b111111; 12'd1604 : mem_out_dec = 6'b111111; 12'd1605 : mem_out_dec = 6'b111111; 12'd1606 : mem_out_dec = 6'b111111; 12'd1607 : mem_out_dec = 6'b111111; 12'd1608 : mem_out_dec = 6'b111111; 12'd1609 : mem_out_dec = 6'b111111; 12'd1610 : mem_out_dec = 6'b111111; 12'd1611 : mem_out_dec = 6'b111111; 12'd1612 : mem_out_dec = 6'b111111; 12'd1613 : mem_out_dec = 6'b111111; 12'd1614 : mem_out_dec = 6'b111111; 12'd1615 : mem_out_dec = 6'b111111; 12'd1616 : mem_out_dec = 6'b111111; 12'd1617 : mem_out_dec = 6'b111111; 12'd1618 : mem_out_dec = 6'b111111; 12'd1619 : mem_out_dec = 6'b111111; 12'd1620 : mem_out_dec = 6'b111111; 12'd1621 : mem_out_dec = 6'b111111; 12'd1622 : mem_out_dec = 6'b111111; 12'd1623 : mem_out_dec = 6'b111111; 12'd1624 : mem_out_dec = 6'b111111; 12'd1625 : mem_out_dec = 6'b111111; 12'd1626 : mem_out_dec = 6'b111111; 12'd1627 : mem_out_dec = 6'b111111; 12'd1628 : mem_out_dec = 6'b111111; 12'd1629 : mem_out_dec = 6'b111111; 12'd1630 : mem_out_dec = 6'b111111; 12'd1631 : mem_out_dec = 6'b000100; 12'd1632 : mem_out_dec = 6'b000011; 12'd1633 : mem_out_dec = 6'b000011; 12'd1634 : mem_out_dec = 6'b000100; 12'd1635 : mem_out_dec = 6'b000100; 12'd1636 : mem_out_dec = 6'b000101; 12'd1637 : mem_out_dec = 6'b000110; 12'd1638 : mem_out_dec = 6'b000110; 12'd1639 : mem_out_dec = 6'b000111; 12'd1640 : mem_out_dec = 6'b000111; 12'd1641 : mem_out_dec = 6'b001000; 12'd1642 : mem_out_dec = 6'b001001; 12'd1643 : mem_out_dec = 6'b001001; 12'd1644 : mem_out_dec = 6'b001010; 12'd1645 : mem_out_dec = 6'b001011; 12'd1646 : mem_out_dec = 6'b001100; 12'd1647 : mem_out_dec = 6'b001101; 12'd1648 : mem_out_dec = 6'b001101; 12'd1649 : mem_out_dec = 6'b001101; 12'd1650 : mem_out_dec = 6'b001110; 12'd1651 : mem_out_dec = 6'b001110; 12'd1652 : mem_out_dec = 6'b001110; 12'd1653 : mem_out_dec = 6'b001111; 12'd1654 : mem_out_dec = 6'b010000; 12'd1655 : mem_out_dec = 6'b010000; 12'd1656 : mem_out_dec = 6'b010001; 12'd1657 : mem_out_dec = 6'b010001; 12'd1658 : mem_out_dec = 6'b010001; 12'd1659 : mem_out_dec = 6'b010010; 12'd1660 : mem_out_dec = 6'b010010; 12'd1661 : mem_out_dec = 6'b010011; 12'd1662 : mem_out_dec = 6'b010011; 12'd1663 : mem_out_dec = 6'b010100; 12'd1664 : mem_out_dec = 6'b111111; 12'd1665 : mem_out_dec = 6'b111111; 12'd1666 : mem_out_dec = 6'b111111; 12'd1667 : mem_out_dec = 6'b111111; 12'd1668 : mem_out_dec = 6'b111111; 12'd1669 : mem_out_dec = 6'b111111; 12'd1670 : mem_out_dec = 6'b111111; 12'd1671 : mem_out_dec = 6'b111111; 12'd1672 : mem_out_dec = 6'b111111; 12'd1673 : mem_out_dec = 6'b111111; 12'd1674 : mem_out_dec = 6'b111111; 12'd1675 : mem_out_dec = 6'b111111; 12'd1676 : mem_out_dec = 6'b111111; 12'd1677 : mem_out_dec = 6'b111111; 12'd1678 : mem_out_dec = 6'b111111; 12'd1679 : mem_out_dec = 6'b111111; 12'd1680 : mem_out_dec = 6'b111111; 12'd1681 : mem_out_dec = 6'b111111; 12'd1682 : mem_out_dec = 6'b111111; 12'd1683 : mem_out_dec = 6'b111111; 12'd1684 : mem_out_dec = 6'b111111; 12'd1685 : mem_out_dec = 6'b111111; 12'd1686 : mem_out_dec = 6'b111111; 12'd1687 : mem_out_dec = 6'b111111; 12'd1688 : mem_out_dec = 6'b111111; 12'd1689 : mem_out_dec = 6'b111111; 12'd1690 : mem_out_dec = 6'b111111; 12'd1691 : mem_out_dec = 6'b111111; 12'd1692 : mem_out_dec = 6'b111111; 12'd1693 : mem_out_dec = 6'b111111; 12'd1694 : mem_out_dec = 6'b111111; 12'd1695 : mem_out_dec = 6'b111111; 12'd1696 : mem_out_dec = 6'b000011; 12'd1697 : mem_out_dec = 6'b000011; 12'd1698 : mem_out_dec = 6'b000100; 12'd1699 : mem_out_dec = 6'b000100; 12'd1700 : mem_out_dec = 6'b000101; 12'd1701 : mem_out_dec = 6'b000101; 12'd1702 : mem_out_dec = 6'b000110; 12'd1703 : mem_out_dec = 6'b000111; 12'd1704 : mem_out_dec = 6'b000111; 12'd1705 : mem_out_dec = 6'b001000; 12'd1706 : mem_out_dec = 6'b001000; 12'd1707 : mem_out_dec = 6'b001001; 12'd1708 : mem_out_dec = 6'b001010; 12'd1709 : mem_out_dec = 6'b001011; 12'd1710 : mem_out_dec = 6'b001100; 12'd1711 : mem_out_dec = 6'b001100; 12'd1712 : mem_out_dec = 6'b001100; 12'd1713 : mem_out_dec = 6'b001101; 12'd1714 : mem_out_dec = 6'b001101; 12'd1715 : mem_out_dec = 6'b001110; 12'd1716 : mem_out_dec = 6'b001110; 12'd1717 : mem_out_dec = 6'b001111; 12'd1718 : mem_out_dec = 6'b001111; 12'd1719 : mem_out_dec = 6'b010000; 12'd1720 : mem_out_dec = 6'b010000; 12'd1721 : mem_out_dec = 6'b010000; 12'd1722 : mem_out_dec = 6'b010001; 12'd1723 : mem_out_dec = 6'b010001; 12'd1724 : mem_out_dec = 6'b010010; 12'd1725 : mem_out_dec = 6'b010010; 12'd1726 : mem_out_dec = 6'b010011; 12'd1727 : mem_out_dec = 6'b010011; 12'd1728 : mem_out_dec = 6'b111111; 12'd1729 : mem_out_dec = 6'b111111; 12'd1730 : mem_out_dec = 6'b111111; 12'd1731 : mem_out_dec = 6'b111111; 12'd1732 : mem_out_dec = 6'b111111; 12'd1733 : mem_out_dec = 6'b111111; 12'd1734 : mem_out_dec = 6'b111111; 12'd1735 : mem_out_dec = 6'b111111; 12'd1736 : mem_out_dec = 6'b111111; 12'd1737 : mem_out_dec = 6'b111111; 12'd1738 : mem_out_dec = 6'b111111; 12'd1739 : mem_out_dec = 6'b111111; 12'd1740 : mem_out_dec = 6'b111111; 12'd1741 : mem_out_dec = 6'b111111; 12'd1742 : mem_out_dec = 6'b111111; 12'd1743 : mem_out_dec = 6'b111111; 12'd1744 : mem_out_dec = 6'b111111; 12'd1745 : mem_out_dec = 6'b111111; 12'd1746 : mem_out_dec = 6'b111111; 12'd1747 : mem_out_dec = 6'b111111; 12'd1748 : mem_out_dec = 6'b111111; 12'd1749 : mem_out_dec = 6'b111111; 12'd1750 : mem_out_dec = 6'b111111; 12'd1751 : mem_out_dec = 6'b111111; 12'd1752 : mem_out_dec = 6'b111111; 12'd1753 : mem_out_dec = 6'b111111; 12'd1754 : mem_out_dec = 6'b111111; 12'd1755 : mem_out_dec = 6'b111111; 12'd1756 : mem_out_dec = 6'b111111; 12'd1757 : mem_out_dec = 6'b111111; 12'd1758 : mem_out_dec = 6'b111111; 12'd1759 : mem_out_dec = 6'b111111; 12'd1760 : mem_out_dec = 6'b111111; 12'd1761 : mem_out_dec = 6'b000011; 12'd1762 : mem_out_dec = 6'b000011; 12'd1763 : mem_out_dec = 6'b000100; 12'd1764 : mem_out_dec = 6'b000101; 12'd1765 : mem_out_dec = 6'b000101; 12'd1766 : mem_out_dec = 6'b000110; 12'd1767 : mem_out_dec = 6'b000111; 12'd1768 : mem_out_dec = 6'b000111; 12'd1769 : mem_out_dec = 6'b000111; 12'd1770 : mem_out_dec = 6'b001000; 12'd1771 : mem_out_dec = 6'b001001; 12'd1772 : mem_out_dec = 6'b001010; 12'd1773 : mem_out_dec = 6'b001011; 12'd1774 : mem_out_dec = 6'b001011; 12'd1775 : mem_out_dec = 6'b001100; 12'd1776 : mem_out_dec = 6'b001100; 12'd1777 : mem_out_dec = 6'b001101; 12'd1778 : mem_out_dec = 6'b001101; 12'd1779 : mem_out_dec = 6'b001101; 12'd1780 : mem_out_dec = 6'b001110; 12'd1781 : mem_out_dec = 6'b001111; 12'd1782 : mem_out_dec = 6'b001111; 12'd1783 : mem_out_dec = 6'b010000; 12'd1784 : mem_out_dec = 6'b010000; 12'd1785 : mem_out_dec = 6'b010000; 12'd1786 : mem_out_dec = 6'b010000; 12'd1787 : mem_out_dec = 6'b010001; 12'd1788 : mem_out_dec = 6'b010001; 12'd1789 : mem_out_dec = 6'b010010; 12'd1790 : mem_out_dec = 6'b010010; 12'd1791 : mem_out_dec = 6'b010011; 12'd1792 : mem_out_dec = 6'b111111; 12'd1793 : mem_out_dec = 6'b111111; 12'd1794 : mem_out_dec = 6'b111111; 12'd1795 : mem_out_dec = 6'b111111; 12'd1796 : mem_out_dec = 6'b111111; 12'd1797 : mem_out_dec = 6'b111111; 12'd1798 : mem_out_dec = 6'b111111; 12'd1799 : mem_out_dec = 6'b111111; 12'd1800 : mem_out_dec = 6'b111111; 12'd1801 : mem_out_dec = 6'b111111; 12'd1802 : mem_out_dec = 6'b111111; 12'd1803 : mem_out_dec = 6'b111111; 12'd1804 : mem_out_dec = 6'b111111; 12'd1805 : mem_out_dec = 6'b111111; 12'd1806 : mem_out_dec = 6'b111111; 12'd1807 : mem_out_dec = 6'b111111; 12'd1808 : mem_out_dec = 6'b111111; 12'd1809 : mem_out_dec = 6'b111111; 12'd1810 : mem_out_dec = 6'b111111; 12'd1811 : mem_out_dec = 6'b111111; 12'd1812 : mem_out_dec = 6'b111111; 12'd1813 : mem_out_dec = 6'b111111; 12'd1814 : mem_out_dec = 6'b111111; 12'd1815 : mem_out_dec = 6'b111111; 12'd1816 : mem_out_dec = 6'b111111; 12'd1817 : mem_out_dec = 6'b111111; 12'd1818 : mem_out_dec = 6'b111111; 12'd1819 : mem_out_dec = 6'b111111; 12'd1820 : mem_out_dec = 6'b111111; 12'd1821 : mem_out_dec = 6'b111111; 12'd1822 : mem_out_dec = 6'b111111; 12'd1823 : mem_out_dec = 6'b111111; 12'd1824 : mem_out_dec = 6'b111111; 12'd1825 : mem_out_dec = 6'b111111; 12'd1826 : mem_out_dec = 6'b000011; 12'd1827 : mem_out_dec = 6'b000100; 12'd1828 : mem_out_dec = 6'b000100; 12'd1829 : mem_out_dec = 6'b000101; 12'd1830 : mem_out_dec = 6'b000110; 12'd1831 : mem_out_dec = 6'b000110; 12'd1832 : mem_out_dec = 6'b000110; 12'd1833 : mem_out_dec = 6'b000111; 12'd1834 : mem_out_dec = 6'b001000; 12'd1835 : mem_out_dec = 6'b001001; 12'd1836 : mem_out_dec = 6'b001010; 12'd1837 : mem_out_dec = 6'b001010; 12'd1838 : mem_out_dec = 6'b001011; 12'd1839 : mem_out_dec = 6'b001100; 12'd1840 : mem_out_dec = 6'b001100; 12'd1841 : mem_out_dec = 6'b001100; 12'd1842 : mem_out_dec = 6'b001101; 12'd1843 : mem_out_dec = 6'b001101; 12'd1844 : mem_out_dec = 6'b001110; 12'd1845 : mem_out_dec = 6'b001110; 12'd1846 : mem_out_dec = 6'b001111; 12'd1847 : mem_out_dec = 6'b010000; 12'd1848 : mem_out_dec = 6'b001111; 12'd1849 : mem_out_dec = 6'b001111; 12'd1850 : mem_out_dec = 6'b010000; 12'd1851 : mem_out_dec = 6'b010000; 12'd1852 : mem_out_dec = 6'b010001; 12'd1853 : mem_out_dec = 6'b010001; 12'd1854 : mem_out_dec = 6'b010010; 12'd1855 : mem_out_dec = 6'b010010; 12'd1856 : mem_out_dec = 6'b111111; 12'd1857 : mem_out_dec = 6'b111111; 12'd1858 : mem_out_dec = 6'b111111; 12'd1859 : mem_out_dec = 6'b111111; 12'd1860 : mem_out_dec = 6'b111111; 12'd1861 : mem_out_dec = 6'b111111; 12'd1862 : mem_out_dec = 6'b111111; 12'd1863 : mem_out_dec = 6'b111111; 12'd1864 : mem_out_dec = 6'b111111; 12'd1865 : mem_out_dec = 6'b111111; 12'd1866 : mem_out_dec = 6'b111111; 12'd1867 : mem_out_dec = 6'b111111; 12'd1868 : mem_out_dec = 6'b111111; 12'd1869 : mem_out_dec = 6'b111111; 12'd1870 : mem_out_dec = 6'b111111; 12'd1871 : mem_out_dec = 6'b111111; 12'd1872 : mem_out_dec = 6'b111111; 12'd1873 : mem_out_dec = 6'b111111; 12'd1874 : mem_out_dec = 6'b111111; 12'd1875 : mem_out_dec = 6'b111111; 12'd1876 : mem_out_dec = 6'b111111; 12'd1877 : mem_out_dec = 6'b111111; 12'd1878 : mem_out_dec = 6'b111111; 12'd1879 : mem_out_dec = 6'b111111; 12'd1880 : mem_out_dec = 6'b111111; 12'd1881 : mem_out_dec = 6'b111111; 12'd1882 : mem_out_dec = 6'b111111; 12'd1883 : mem_out_dec = 6'b111111; 12'd1884 : mem_out_dec = 6'b111111; 12'd1885 : mem_out_dec = 6'b111111; 12'd1886 : mem_out_dec = 6'b111111; 12'd1887 : mem_out_dec = 6'b111111; 12'd1888 : mem_out_dec = 6'b111111; 12'd1889 : mem_out_dec = 6'b111111; 12'd1890 : mem_out_dec = 6'b111111; 12'd1891 : mem_out_dec = 6'b000100; 12'd1892 : mem_out_dec = 6'b000100; 12'd1893 : mem_out_dec = 6'b000101; 12'd1894 : mem_out_dec = 6'b000101; 12'd1895 : mem_out_dec = 6'b000110; 12'd1896 : mem_out_dec = 6'b000110; 12'd1897 : mem_out_dec = 6'b000111; 12'd1898 : mem_out_dec = 6'b001000; 12'd1899 : mem_out_dec = 6'b001001; 12'd1900 : mem_out_dec = 6'b001001; 12'd1901 : mem_out_dec = 6'b001010; 12'd1902 : mem_out_dec = 6'b001011; 12'd1903 : mem_out_dec = 6'b001100; 12'd1904 : mem_out_dec = 6'b001100; 12'd1905 : mem_out_dec = 6'b001100; 12'd1906 : mem_out_dec = 6'b001100; 12'd1907 : mem_out_dec = 6'b001101; 12'd1908 : mem_out_dec = 6'b001110; 12'd1909 : mem_out_dec = 6'b001110; 12'd1910 : mem_out_dec = 6'b001111; 12'd1911 : mem_out_dec = 6'b001111; 12'd1912 : mem_out_dec = 6'b001111; 12'd1913 : mem_out_dec = 6'b001111; 12'd1914 : mem_out_dec = 6'b001111; 12'd1915 : mem_out_dec = 6'b010000; 12'd1916 : mem_out_dec = 6'b010000; 12'd1917 : mem_out_dec = 6'b010001; 12'd1918 : mem_out_dec = 6'b010001; 12'd1919 : mem_out_dec = 6'b010010; 12'd1920 : mem_out_dec = 6'b111111; 12'd1921 : mem_out_dec = 6'b111111; 12'd1922 : mem_out_dec = 6'b111111; 12'd1923 : mem_out_dec = 6'b111111; 12'd1924 : mem_out_dec = 6'b111111; 12'd1925 : mem_out_dec = 6'b111111; 12'd1926 : mem_out_dec = 6'b111111; 12'd1927 : mem_out_dec = 6'b111111; 12'd1928 : mem_out_dec = 6'b111111; 12'd1929 : mem_out_dec = 6'b111111; 12'd1930 : mem_out_dec = 6'b111111; 12'd1931 : mem_out_dec = 6'b111111; 12'd1932 : mem_out_dec = 6'b111111; 12'd1933 : mem_out_dec = 6'b111111; 12'd1934 : mem_out_dec = 6'b111111; 12'd1935 : mem_out_dec = 6'b111111; 12'd1936 : mem_out_dec = 6'b111111; 12'd1937 : mem_out_dec = 6'b111111; 12'd1938 : mem_out_dec = 6'b111111; 12'd1939 : mem_out_dec = 6'b111111; 12'd1940 : mem_out_dec = 6'b111111; 12'd1941 : mem_out_dec = 6'b111111; 12'd1942 : mem_out_dec = 6'b111111; 12'd1943 : mem_out_dec = 6'b111111; 12'd1944 : mem_out_dec = 6'b111111; 12'd1945 : mem_out_dec = 6'b111111; 12'd1946 : mem_out_dec = 6'b111111; 12'd1947 : mem_out_dec = 6'b111111; 12'd1948 : mem_out_dec = 6'b111111; 12'd1949 : mem_out_dec = 6'b111111; 12'd1950 : mem_out_dec = 6'b111111; 12'd1951 : mem_out_dec = 6'b111111; 12'd1952 : mem_out_dec = 6'b111111; 12'd1953 : mem_out_dec = 6'b111111; 12'd1954 : mem_out_dec = 6'b111111; 12'd1955 : mem_out_dec = 6'b111111; 12'd1956 : mem_out_dec = 6'b000100; 12'd1957 : mem_out_dec = 6'b000101; 12'd1958 : mem_out_dec = 6'b000101; 12'd1959 : mem_out_dec = 6'b000110; 12'd1960 : mem_out_dec = 6'b000110; 12'd1961 : mem_out_dec = 6'b000111; 12'd1962 : mem_out_dec = 6'b001000; 12'd1963 : mem_out_dec = 6'b001000; 12'd1964 : mem_out_dec = 6'b001001; 12'd1965 : mem_out_dec = 6'b001010; 12'd1966 : mem_out_dec = 6'b001011; 12'd1967 : mem_out_dec = 6'b001011; 12'd1968 : mem_out_dec = 6'b001011; 12'd1969 : mem_out_dec = 6'b001100; 12'd1970 : mem_out_dec = 6'b001100; 12'd1971 : mem_out_dec = 6'b001101; 12'd1972 : mem_out_dec = 6'b001101; 12'd1973 : mem_out_dec = 6'b001110; 12'd1974 : mem_out_dec = 6'b001111; 12'd1975 : mem_out_dec = 6'b001111; 12'd1976 : mem_out_dec = 6'b001110; 12'd1977 : mem_out_dec = 6'b001110; 12'd1978 : mem_out_dec = 6'b001111; 12'd1979 : mem_out_dec = 6'b001111; 12'd1980 : mem_out_dec = 6'b010000; 12'd1981 : mem_out_dec = 6'b010000; 12'd1982 : mem_out_dec = 6'b010001; 12'd1983 : mem_out_dec = 6'b010001; 12'd1984 : mem_out_dec = 6'b111111; 12'd1985 : mem_out_dec = 6'b111111; 12'd1986 : mem_out_dec = 6'b111111; 12'd1987 : mem_out_dec = 6'b111111; 12'd1988 : mem_out_dec = 6'b111111; 12'd1989 : mem_out_dec = 6'b111111; 12'd1990 : mem_out_dec = 6'b111111; 12'd1991 : mem_out_dec = 6'b111111; 12'd1992 : mem_out_dec = 6'b111111; 12'd1993 : mem_out_dec = 6'b111111; 12'd1994 : mem_out_dec = 6'b111111; 12'd1995 : mem_out_dec = 6'b111111; 12'd1996 : mem_out_dec = 6'b111111; 12'd1997 : mem_out_dec = 6'b111111; 12'd1998 : mem_out_dec = 6'b111111; 12'd1999 : mem_out_dec = 6'b111111; 12'd2000 : mem_out_dec = 6'b111111; 12'd2001 : mem_out_dec = 6'b111111; 12'd2002 : mem_out_dec = 6'b111111; 12'd2003 : mem_out_dec = 6'b111111; 12'd2004 : mem_out_dec = 6'b111111; 12'd2005 : mem_out_dec = 6'b111111; 12'd2006 : mem_out_dec = 6'b111111; 12'd2007 : mem_out_dec = 6'b111111; 12'd2008 : mem_out_dec = 6'b111111; 12'd2009 : mem_out_dec = 6'b111111; 12'd2010 : mem_out_dec = 6'b111111; 12'd2011 : mem_out_dec = 6'b111111; 12'd2012 : mem_out_dec = 6'b111111; 12'd2013 : mem_out_dec = 6'b111111; 12'd2014 : mem_out_dec = 6'b111111; 12'd2015 : mem_out_dec = 6'b111111; 12'd2016 : mem_out_dec = 6'b111111; 12'd2017 : mem_out_dec = 6'b111111; 12'd2018 : mem_out_dec = 6'b111111; 12'd2019 : mem_out_dec = 6'b111111; 12'd2020 : mem_out_dec = 6'b111111; 12'd2021 : mem_out_dec = 6'b000100; 12'd2022 : mem_out_dec = 6'b000101; 12'd2023 : mem_out_dec = 6'b000110; 12'd2024 : mem_out_dec = 6'b000110; 12'd2025 : mem_out_dec = 6'b000111; 12'd2026 : mem_out_dec = 6'b000111; 12'd2027 : mem_out_dec = 6'b001000; 12'd2028 : mem_out_dec = 6'b001001; 12'd2029 : mem_out_dec = 6'b001010; 12'd2030 : mem_out_dec = 6'b001010; 12'd2031 : mem_out_dec = 6'b001011; 12'd2032 : mem_out_dec = 6'b001011; 12'd2033 : mem_out_dec = 6'b001011; 12'd2034 : mem_out_dec = 6'b001100; 12'd2035 : mem_out_dec = 6'b001101; 12'd2036 : mem_out_dec = 6'b001101; 12'd2037 : mem_out_dec = 6'b001110; 12'd2038 : mem_out_dec = 6'b001110; 12'd2039 : mem_out_dec = 6'b001110; 12'd2040 : mem_out_dec = 6'b001101; 12'd2041 : mem_out_dec = 6'b001110; 12'd2042 : mem_out_dec = 6'b001110; 12'd2043 : mem_out_dec = 6'b001111; 12'd2044 : mem_out_dec = 6'b001111; 12'd2045 : mem_out_dec = 6'b010000; 12'd2046 : mem_out_dec = 6'b010000; 12'd2047 : mem_out_dec = 6'b010001; 12'd2048 : mem_out_dec = 6'b111111; 12'd2049 : mem_out_dec = 6'b111111; 12'd2050 : mem_out_dec = 6'b111111; 12'd2051 : mem_out_dec = 6'b111111; 12'd2052 : mem_out_dec = 6'b111111; 12'd2053 : mem_out_dec = 6'b111111; 12'd2054 : mem_out_dec = 6'b111111; 12'd2055 : mem_out_dec = 6'b111111; 12'd2056 : mem_out_dec = 6'b111111; 12'd2057 : mem_out_dec = 6'b111111; 12'd2058 : mem_out_dec = 6'b111111; 12'd2059 : mem_out_dec = 6'b111111; 12'd2060 : mem_out_dec = 6'b111111; 12'd2061 : mem_out_dec = 6'b111111; 12'd2062 : mem_out_dec = 6'b111111; 12'd2063 : mem_out_dec = 6'b111111; 12'd2064 : mem_out_dec = 6'b111111; 12'd2065 : mem_out_dec = 6'b111111; 12'd2066 : mem_out_dec = 6'b111111; 12'd2067 : mem_out_dec = 6'b111111; 12'd2068 : mem_out_dec = 6'b111111; 12'd2069 : mem_out_dec = 6'b111111; 12'd2070 : mem_out_dec = 6'b111111; 12'd2071 : mem_out_dec = 6'b111111; 12'd2072 : mem_out_dec = 6'b111111; 12'd2073 : mem_out_dec = 6'b111111; 12'd2074 : mem_out_dec = 6'b111111; 12'd2075 : mem_out_dec = 6'b111111; 12'd2076 : mem_out_dec = 6'b111111; 12'd2077 : mem_out_dec = 6'b111111; 12'd2078 : mem_out_dec = 6'b111111; 12'd2079 : mem_out_dec = 6'b111111; 12'd2080 : mem_out_dec = 6'b111111; 12'd2081 : mem_out_dec = 6'b111111; 12'd2082 : mem_out_dec = 6'b111111; 12'd2083 : mem_out_dec = 6'b111111; 12'd2084 : mem_out_dec = 6'b111111; 12'd2085 : mem_out_dec = 6'b111111; 12'd2086 : mem_out_dec = 6'b000100; 12'd2087 : mem_out_dec = 6'b000101; 12'd2088 : mem_out_dec = 6'b000101; 12'd2089 : mem_out_dec = 6'b000110; 12'd2090 : mem_out_dec = 6'b000110; 12'd2091 : mem_out_dec = 6'b000111; 12'd2092 : mem_out_dec = 6'b001000; 12'd2093 : mem_out_dec = 6'b001001; 12'd2094 : mem_out_dec = 6'b001001; 12'd2095 : mem_out_dec = 6'b001010; 12'd2096 : mem_out_dec = 6'b001010; 12'd2097 : mem_out_dec = 6'b001011; 12'd2098 : mem_out_dec = 6'b001011; 12'd2099 : mem_out_dec = 6'b001100; 12'd2100 : mem_out_dec = 6'b001100; 12'd2101 : mem_out_dec = 6'b001100; 12'd2102 : mem_out_dec = 6'b001100; 12'd2103 : mem_out_dec = 6'b001101; 12'd2104 : mem_out_dec = 6'b001100; 12'd2105 : mem_out_dec = 6'b001100; 12'd2106 : mem_out_dec = 6'b001101; 12'd2107 : mem_out_dec = 6'b001101; 12'd2108 : mem_out_dec = 6'b001110; 12'd2109 : mem_out_dec = 6'b001111; 12'd2110 : mem_out_dec = 6'b010000; 12'd2111 : mem_out_dec = 6'b010000; 12'd2112 : mem_out_dec = 6'b111111; 12'd2113 : mem_out_dec = 6'b111111; 12'd2114 : mem_out_dec = 6'b111111; 12'd2115 : mem_out_dec = 6'b111111; 12'd2116 : mem_out_dec = 6'b111111; 12'd2117 : mem_out_dec = 6'b111111; 12'd2118 : mem_out_dec = 6'b111111; 12'd2119 : mem_out_dec = 6'b111111; 12'd2120 : mem_out_dec = 6'b111111; 12'd2121 : mem_out_dec = 6'b111111; 12'd2122 : mem_out_dec = 6'b111111; 12'd2123 : mem_out_dec = 6'b111111; 12'd2124 : mem_out_dec = 6'b111111; 12'd2125 : mem_out_dec = 6'b111111; 12'd2126 : mem_out_dec = 6'b111111; 12'd2127 : mem_out_dec = 6'b111111; 12'd2128 : mem_out_dec = 6'b111111; 12'd2129 : mem_out_dec = 6'b111111; 12'd2130 : mem_out_dec = 6'b111111; 12'd2131 : mem_out_dec = 6'b111111; 12'd2132 : mem_out_dec = 6'b111111; 12'd2133 : mem_out_dec = 6'b111111; 12'd2134 : mem_out_dec = 6'b111111; 12'd2135 : mem_out_dec = 6'b111111; 12'd2136 : mem_out_dec = 6'b111111; 12'd2137 : mem_out_dec = 6'b111111; 12'd2138 : mem_out_dec = 6'b111111; 12'd2139 : mem_out_dec = 6'b111111; 12'd2140 : mem_out_dec = 6'b111111; 12'd2141 : mem_out_dec = 6'b111111; 12'd2142 : mem_out_dec = 6'b111111; 12'd2143 : mem_out_dec = 6'b111111; 12'd2144 : mem_out_dec = 6'b111111; 12'd2145 : mem_out_dec = 6'b111111; 12'd2146 : mem_out_dec = 6'b111111; 12'd2147 : mem_out_dec = 6'b111111; 12'd2148 : mem_out_dec = 6'b111111; 12'd2149 : mem_out_dec = 6'b111111; 12'd2150 : mem_out_dec = 6'b111111; 12'd2151 : mem_out_dec = 6'b000100; 12'd2152 : mem_out_dec = 6'b000100; 12'd2153 : mem_out_dec = 6'b000101; 12'd2154 : mem_out_dec = 6'b000110; 12'd2155 : mem_out_dec = 6'b000111; 12'd2156 : mem_out_dec = 6'b000111; 12'd2157 : mem_out_dec = 6'b001000; 12'd2158 : mem_out_dec = 6'b001001; 12'd2159 : mem_out_dec = 6'b001001; 12'd2160 : mem_out_dec = 6'b001010; 12'd2161 : mem_out_dec = 6'b001010; 12'd2162 : mem_out_dec = 6'b001011; 12'd2163 : mem_out_dec = 6'b001011; 12'd2164 : mem_out_dec = 6'b001011; 12'd2165 : mem_out_dec = 6'b001011; 12'd2166 : mem_out_dec = 6'b001011; 12'd2167 : mem_out_dec = 6'b001100; 12'd2168 : mem_out_dec = 6'b001011; 12'd2169 : mem_out_dec = 6'b001011; 12'd2170 : mem_out_dec = 6'b001100; 12'd2171 : mem_out_dec = 6'b001101; 12'd2172 : mem_out_dec = 6'b001110; 12'd2173 : mem_out_dec = 6'b001110; 12'd2174 : mem_out_dec = 6'b001111; 12'd2175 : mem_out_dec = 6'b010000; 12'd2176 : mem_out_dec = 6'b111111; 12'd2177 : mem_out_dec = 6'b111111; 12'd2178 : mem_out_dec = 6'b111111; 12'd2179 : mem_out_dec = 6'b111111; 12'd2180 : mem_out_dec = 6'b111111; 12'd2181 : mem_out_dec = 6'b111111; 12'd2182 : mem_out_dec = 6'b111111; 12'd2183 : mem_out_dec = 6'b111111; 12'd2184 : mem_out_dec = 6'b111111; 12'd2185 : mem_out_dec = 6'b111111; 12'd2186 : mem_out_dec = 6'b111111; 12'd2187 : mem_out_dec = 6'b111111; 12'd2188 : mem_out_dec = 6'b111111; 12'd2189 : mem_out_dec = 6'b111111; 12'd2190 : mem_out_dec = 6'b111111; 12'd2191 : mem_out_dec = 6'b111111; 12'd2192 : mem_out_dec = 6'b111111; 12'd2193 : mem_out_dec = 6'b111111; 12'd2194 : mem_out_dec = 6'b111111; 12'd2195 : mem_out_dec = 6'b111111; 12'd2196 : mem_out_dec = 6'b111111; 12'd2197 : mem_out_dec = 6'b111111; 12'd2198 : mem_out_dec = 6'b111111; 12'd2199 : mem_out_dec = 6'b111111; 12'd2200 : mem_out_dec = 6'b111111; 12'd2201 : mem_out_dec = 6'b111111; 12'd2202 : mem_out_dec = 6'b111111; 12'd2203 : mem_out_dec = 6'b111111; 12'd2204 : mem_out_dec = 6'b111111; 12'd2205 : mem_out_dec = 6'b111111; 12'd2206 : mem_out_dec = 6'b111111; 12'd2207 : mem_out_dec = 6'b111111; 12'd2208 : mem_out_dec = 6'b111111; 12'd2209 : mem_out_dec = 6'b111111; 12'd2210 : mem_out_dec = 6'b111111; 12'd2211 : mem_out_dec = 6'b111111; 12'd2212 : mem_out_dec = 6'b111111; 12'd2213 : mem_out_dec = 6'b111111; 12'd2214 : mem_out_dec = 6'b111111; 12'd2215 : mem_out_dec = 6'b111111; 12'd2216 : mem_out_dec = 6'b000100; 12'd2217 : mem_out_dec = 6'b000101; 12'd2218 : mem_out_dec = 6'b000101; 12'd2219 : mem_out_dec = 6'b000110; 12'd2220 : mem_out_dec = 6'b000111; 12'd2221 : mem_out_dec = 6'b000111; 12'd2222 : mem_out_dec = 6'b001000; 12'd2223 : mem_out_dec = 6'b001001; 12'd2224 : mem_out_dec = 6'b001001; 12'd2225 : mem_out_dec = 6'b001010; 12'd2226 : mem_out_dec = 6'b001010; 12'd2227 : mem_out_dec = 6'b001010; 12'd2228 : mem_out_dec = 6'b001010; 12'd2229 : mem_out_dec = 6'b001010; 12'd2230 : mem_out_dec = 6'b001010; 12'd2231 : mem_out_dec = 6'b001010; 12'd2232 : mem_out_dec = 6'b001010; 12'd2233 : mem_out_dec = 6'b001011; 12'd2234 : mem_out_dec = 6'b001100; 12'd2235 : mem_out_dec = 6'b001100; 12'd2236 : mem_out_dec = 6'b001101; 12'd2237 : mem_out_dec = 6'b001110; 12'd2238 : mem_out_dec = 6'b001111; 12'd2239 : mem_out_dec = 6'b010000; 12'd2240 : mem_out_dec = 6'b111111; 12'd2241 : mem_out_dec = 6'b111111; 12'd2242 : mem_out_dec = 6'b111111; 12'd2243 : mem_out_dec = 6'b111111; 12'd2244 : mem_out_dec = 6'b111111; 12'd2245 : mem_out_dec = 6'b111111; 12'd2246 : mem_out_dec = 6'b111111; 12'd2247 : mem_out_dec = 6'b111111; 12'd2248 : mem_out_dec = 6'b111111; 12'd2249 : mem_out_dec = 6'b111111; 12'd2250 : mem_out_dec = 6'b111111; 12'd2251 : mem_out_dec = 6'b111111; 12'd2252 : mem_out_dec = 6'b111111; 12'd2253 : mem_out_dec = 6'b111111; 12'd2254 : mem_out_dec = 6'b111111; 12'd2255 : mem_out_dec = 6'b111111; 12'd2256 : mem_out_dec = 6'b111111; 12'd2257 : mem_out_dec = 6'b111111; 12'd2258 : mem_out_dec = 6'b111111; 12'd2259 : mem_out_dec = 6'b111111; 12'd2260 : mem_out_dec = 6'b111111; 12'd2261 : mem_out_dec = 6'b111111; 12'd2262 : mem_out_dec = 6'b111111; 12'd2263 : mem_out_dec = 6'b111111; 12'd2264 : mem_out_dec = 6'b111111; 12'd2265 : mem_out_dec = 6'b111111; 12'd2266 : mem_out_dec = 6'b111111; 12'd2267 : mem_out_dec = 6'b111111; 12'd2268 : mem_out_dec = 6'b111111; 12'd2269 : mem_out_dec = 6'b111111; 12'd2270 : mem_out_dec = 6'b111111; 12'd2271 : mem_out_dec = 6'b111111; 12'd2272 : mem_out_dec = 6'b111111; 12'd2273 : mem_out_dec = 6'b111111; 12'd2274 : mem_out_dec = 6'b111111; 12'd2275 : mem_out_dec = 6'b111111; 12'd2276 : mem_out_dec = 6'b111111; 12'd2277 : mem_out_dec = 6'b111111; 12'd2278 : mem_out_dec = 6'b111111; 12'd2279 : mem_out_dec = 6'b111111; 12'd2280 : mem_out_dec = 6'b111111; 12'd2281 : mem_out_dec = 6'b000100; 12'd2282 : mem_out_dec = 6'b000101; 12'd2283 : mem_out_dec = 6'b000101; 12'd2284 : mem_out_dec = 6'b000110; 12'd2285 : mem_out_dec = 6'b000111; 12'd2286 : mem_out_dec = 6'b001000; 12'd2287 : mem_out_dec = 6'b001001; 12'd2288 : mem_out_dec = 6'b001001; 12'd2289 : mem_out_dec = 6'b001001; 12'd2290 : mem_out_dec = 6'b001001; 12'd2291 : mem_out_dec = 6'b001001; 12'd2292 : mem_out_dec = 6'b001001; 12'd2293 : mem_out_dec = 6'b001001; 12'd2294 : mem_out_dec = 6'b001001; 12'd2295 : mem_out_dec = 6'b001001; 12'd2296 : mem_out_dec = 6'b001010; 12'd2297 : mem_out_dec = 6'b001010; 12'd2298 : mem_out_dec = 6'b001011; 12'd2299 : mem_out_dec = 6'b001100; 12'd2300 : mem_out_dec = 6'b001101; 12'd2301 : mem_out_dec = 6'b001110; 12'd2302 : mem_out_dec = 6'b001110; 12'd2303 : mem_out_dec = 6'b001111; 12'd2304 : mem_out_dec = 6'b111111; 12'd2305 : mem_out_dec = 6'b111111; 12'd2306 : mem_out_dec = 6'b111111; 12'd2307 : mem_out_dec = 6'b111111; 12'd2308 : mem_out_dec = 6'b111111; 12'd2309 : mem_out_dec = 6'b111111; 12'd2310 : mem_out_dec = 6'b111111; 12'd2311 : mem_out_dec = 6'b111111; 12'd2312 : mem_out_dec = 6'b111111; 12'd2313 : mem_out_dec = 6'b111111; 12'd2314 : mem_out_dec = 6'b111111; 12'd2315 : mem_out_dec = 6'b111111; 12'd2316 : mem_out_dec = 6'b111111; 12'd2317 : mem_out_dec = 6'b111111; 12'd2318 : mem_out_dec = 6'b111111; 12'd2319 : mem_out_dec = 6'b111111; 12'd2320 : mem_out_dec = 6'b111111; 12'd2321 : mem_out_dec = 6'b111111; 12'd2322 : mem_out_dec = 6'b111111; 12'd2323 : mem_out_dec = 6'b111111; 12'd2324 : mem_out_dec = 6'b111111; 12'd2325 : mem_out_dec = 6'b111111; 12'd2326 : mem_out_dec = 6'b111111; 12'd2327 : mem_out_dec = 6'b111111; 12'd2328 : mem_out_dec = 6'b111111; 12'd2329 : mem_out_dec = 6'b111111; 12'd2330 : mem_out_dec = 6'b111111; 12'd2331 : mem_out_dec = 6'b111111; 12'd2332 : mem_out_dec = 6'b111111; 12'd2333 : mem_out_dec = 6'b111111; 12'd2334 : mem_out_dec = 6'b111111; 12'd2335 : mem_out_dec = 6'b111111; 12'd2336 : mem_out_dec = 6'b111111; 12'd2337 : mem_out_dec = 6'b111111; 12'd2338 : mem_out_dec = 6'b111111; 12'd2339 : mem_out_dec = 6'b111111; 12'd2340 : mem_out_dec = 6'b111111; 12'd2341 : mem_out_dec = 6'b111111; 12'd2342 : mem_out_dec = 6'b111111; 12'd2343 : mem_out_dec = 6'b111111; 12'd2344 : mem_out_dec = 6'b111111; 12'd2345 : mem_out_dec = 6'b111111; 12'd2346 : mem_out_dec = 6'b000100; 12'd2347 : mem_out_dec = 6'b000101; 12'd2348 : mem_out_dec = 6'b000110; 12'd2349 : mem_out_dec = 6'b000111; 12'd2350 : mem_out_dec = 6'b000111; 12'd2351 : mem_out_dec = 6'b001000; 12'd2352 : mem_out_dec = 6'b001000; 12'd2353 : mem_out_dec = 6'b001000; 12'd2354 : mem_out_dec = 6'b001000; 12'd2355 : mem_out_dec = 6'b001000; 12'd2356 : mem_out_dec = 6'b001000; 12'd2357 : mem_out_dec = 6'b001000; 12'd2358 : mem_out_dec = 6'b001000; 12'd2359 : mem_out_dec = 6'b001001; 12'd2360 : mem_out_dec = 6'b001001; 12'd2361 : mem_out_dec = 6'b001010; 12'd2362 : mem_out_dec = 6'b001011; 12'd2363 : mem_out_dec = 6'b001100; 12'd2364 : mem_out_dec = 6'b001100; 12'd2365 : mem_out_dec = 6'b001101; 12'd2366 : mem_out_dec = 6'b001110; 12'd2367 : mem_out_dec = 6'b001111; 12'd2368 : mem_out_dec = 6'b111111; 12'd2369 : mem_out_dec = 6'b111111; 12'd2370 : mem_out_dec = 6'b111111; 12'd2371 : mem_out_dec = 6'b111111; 12'd2372 : mem_out_dec = 6'b111111; 12'd2373 : mem_out_dec = 6'b111111; 12'd2374 : mem_out_dec = 6'b111111; 12'd2375 : mem_out_dec = 6'b111111; 12'd2376 : mem_out_dec = 6'b111111; 12'd2377 : mem_out_dec = 6'b111111; 12'd2378 : mem_out_dec = 6'b111111; 12'd2379 : mem_out_dec = 6'b111111; 12'd2380 : mem_out_dec = 6'b111111; 12'd2381 : mem_out_dec = 6'b111111; 12'd2382 : mem_out_dec = 6'b111111; 12'd2383 : mem_out_dec = 6'b111111; 12'd2384 : mem_out_dec = 6'b111111; 12'd2385 : mem_out_dec = 6'b111111; 12'd2386 : mem_out_dec = 6'b111111; 12'd2387 : mem_out_dec = 6'b111111; 12'd2388 : mem_out_dec = 6'b111111; 12'd2389 : mem_out_dec = 6'b111111; 12'd2390 : mem_out_dec = 6'b111111; 12'd2391 : mem_out_dec = 6'b111111; 12'd2392 : mem_out_dec = 6'b111111; 12'd2393 : mem_out_dec = 6'b111111; 12'd2394 : mem_out_dec = 6'b111111; 12'd2395 : mem_out_dec = 6'b111111; 12'd2396 : mem_out_dec = 6'b111111; 12'd2397 : mem_out_dec = 6'b111111; 12'd2398 : mem_out_dec = 6'b111111; 12'd2399 : mem_out_dec = 6'b111111; 12'd2400 : mem_out_dec = 6'b111111; 12'd2401 : mem_out_dec = 6'b111111; 12'd2402 : mem_out_dec = 6'b111111; 12'd2403 : mem_out_dec = 6'b111111; 12'd2404 : mem_out_dec = 6'b111111; 12'd2405 : mem_out_dec = 6'b111111; 12'd2406 : mem_out_dec = 6'b111111; 12'd2407 : mem_out_dec = 6'b111111; 12'd2408 : mem_out_dec = 6'b111111; 12'd2409 : mem_out_dec = 6'b111111; 12'd2410 : mem_out_dec = 6'b111111; 12'd2411 : mem_out_dec = 6'b000101; 12'd2412 : mem_out_dec = 6'b000101; 12'd2413 : mem_out_dec = 6'b000110; 12'd2414 : mem_out_dec = 6'b000111; 12'd2415 : mem_out_dec = 6'b001000; 12'd2416 : mem_out_dec = 6'b000111; 12'd2417 : mem_out_dec = 6'b000111; 12'd2418 : mem_out_dec = 6'b000111; 12'd2419 : mem_out_dec = 6'b000111; 12'd2420 : mem_out_dec = 6'b000111; 12'd2421 : mem_out_dec = 6'b000111; 12'd2422 : mem_out_dec = 6'b001000; 12'd2423 : mem_out_dec = 6'b001001; 12'd2424 : mem_out_dec = 6'b001001; 12'd2425 : mem_out_dec = 6'b001010; 12'd2426 : mem_out_dec = 6'b001010; 12'd2427 : mem_out_dec = 6'b001011; 12'd2428 : mem_out_dec = 6'b001100; 12'd2429 : mem_out_dec = 6'b001101; 12'd2430 : mem_out_dec = 6'b001101; 12'd2431 : mem_out_dec = 6'b001110; 12'd2432 : mem_out_dec = 6'b111111; 12'd2433 : mem_out_dec = 6'b111111; 12'd2434 : mem_out_dec = 6'b111111; 12'd2435 : mem_out_dec = 6'b111111; 12'd2436 : mem_out_dec = 6'b111111; 12'd2437 : mem_out_dec = 6'b111111; 12'd2438 : mem_out_dec = 6'b111111; 12'd2439 : mem_out_dec = 6'b111111; 12'd2440 : mem_out_dec = 6'b111111; 12'd2441 : mem_out_dec = 6'b111111; 12'd2442 : mem_out_dec = 6'b111111; 12'd2443 : mem_out_dec = 6'b111111; 12'd2444 : mem_out_dec = 6'b111111; 12'd2445 : mem_out_dec = 6'b111111; 12'd2446 : mem_out_dec = 6'b111111; 12'd2447 : mem_out_dec = 6'b111111; 12'd2448 : mem_out_dec = 6'b111111; 12'd2449 : mem_out_dec = 6'b111111; 12'd2450 : mem_out_dec = 6'b111111; 12'd2451 : mem_out_dec = 6'b111111; 12'd2452 : mem_out_dec = 6'b111111; 12'd2453 : mem_out_dec = 6'b111111; 12'd2454 : mem_out_dec = 6'b111111; 12'd2455 : mem_out_dec = 6'b111111; 12'd2456 : mem_out_dec = 6'b111111; 12'd2457 : mem_out_dec = 6'b111111; 12'd2458 : mem_out_dec = 6'b111111; 12'd2459 : mem_out_dec = 6'b111111; 12'd2460 : mem_out_dec = 6'b111111; 12'd2461 : mem_out_dec = 6'b111111; 12'd2462 : mem_out_dec = 6'b111111; 12'd2463 : mem_out_dec = 6'b111111; 12'd2464 : mem_out_dec = 6'b111111; 12'd2465 : mem_out_dec = 6'b111111; 12'd2466 : mem_out_dec = 6'b111111; 12'd2467 : mem_out_dec = 6'b111111; 12'd2468 : mem_out_dec = 6'b111111; 12'd2469 : mem_out_dec = 6'b111111; 12'd2470 : mem_out_dec = 6'b111111; 12'd2471 : mem_out_dec = 6'b111111; 12'd2472 : mem_out_dec = 6'b111111; 12'd2473 : mem_out_dec = 6'b111111; 12'd2474 : mem_out_dec = 6'b111111; 12'd2475 : mem_out_dec = 6'b111111; 12'd2476 : mem_out_dec = 6'b000101; 12'd2477 : mem_out_dec = 6'b000110; 12'd2478 : mem_out_dec = 6'b000111; 12'd2479 : mem_out_dec = 6'b000111; 12'd2480 : mem_out_dec = 6'b000110; 12'd2481 : mem_out_dec = 6'b000110; 12'd2482 : mem_out_dec = 6'b000110; 12'd2483 : mem_out_dec = 6'b000110; 12'd2484 : mem_out_dec = 6'b000110; 12'd2485 : mem_out_dec = 6'b000111; 12'd2486 : mem_out_dec = 6'b000111; 12'd2487 : mem_out_dec = 6'b001000; 12'd2488 : mem_out_dec = 6'b001001; 12'd2489 : mem_out_dec = 6'b001001; 12'd2490 : mem_out_dec = 6'b001010; 12'd2491 : mem_out_dec = 6'b001011; 12'd2492 : mem_out_dec = 6'b001011; 12'd2493 : mem_out_dec = 6'b001100; 12'd2494 : mem_out_dec = 6'b001101; 12'd2495 : mem_out_dec = 6'b001110; 12'd2496 : mem_out_dec = 6'b111111; 12'd2497 : mem_out_dec = 6'b111111; 12'd2498 : mem_out_dec = 6'b111111; 12'd2499 : mem_out_dec = 6'b111111; 12'd2500 : mem_out_dec = 6'b111111; 12'd2501 : mem_out_dec = 6'b111111; 12'd2502 : mem_out_dec = 6'b111111; 12'd2503 : mem_out_dec = 6'b111111; 12'd2504 : mem_out_dec = 6'b111111; 12'd2505 : mem_out_dec = 6'b111111; 12'd2506 : mem_out_dec = 6'b111111; 12'd2507 : mem_out_dec = 6'b111111; 12'd2508 : mem_out_dec = 6'b111111; 12'd2509 : mem_out_dec = 6'b111111; 12'd2510 : mem_out_dec = 6'b111111; 12'd2511 : mem_out_dec = 6'b111111; 12'd2512 : mem_out_dec = 6'b111111; 12'd2513 : mem_out_dec = 6'b111111; 12'd2514 : mem_out_dec = 6'b111111; 12'd2515 : mem_out_dec = 6'b111111; 12'd2516 : mem_out_dec = 6'b111111; 12'd2517 : mem_out_dec = 6'b111111; 12'd2518 : mem_out_dec = 6'b111111; 12'd2519 : mem_out_dec = 6'b111111; 12'd2520 : mem_out_dec = 6'b111111; 12'd2521 : mem_out_dec = 6'b111111; 12'd2522 : mem_out_dec = 6'b111111; 12'd2523 : mem_out_dec = 6'b111111; 12'd2524 : mem_out_dec = 6'b111111; 12'd2525 : mem_out_dec = 6'b111111; 12'd2526 : mem_out_dec = 6'b111111; 12'd2527 : mem_out_dec = 6'b111111; 12'd2528 : mem_out_dec = 6'b111111; 12'd2529 : mem_out_dec = 6'b111111; 12'd2530 : mem_out_dec = 6'b111111; 12'd2531 : mem_out_dec = 6'b111111; 12'd2532 : mem_out_dec = 6'b111111; 12'd2533 : mem_out_dec = 6'b111111; 12'd2534 : mem_out_dec = 6'b111111; 12'd2535 : mem_out_dec = 6'b111111; 12'd2536 : mem_out_dec = 6'b111111; 12'd2537 : mem_out_dec = 6'b111111; 12'd2538 : mem_out_dec = 6'b111111; 12'd2539 : mem_out_dec = 6'b111111; 12'd2540 : mem_out_dec = 6'b111111; 12'd2541 : mem_out_dec = 6'b000101; 12'd2542 : mem_out_dec = 6'b000110; 12'd2543 : mem_out_dec = 6'b000110; 12'd2544 : mem_out_dec = 6'b000110; 12'd2545 : mem_out_dec = 6'b000110; 12'd2546 : mem_out_dec = 6'b000101; 12'd2547 : mem_out_dec = 6'b000101; 12'd2548 : mem_out_dec = 6'b000110; 12'd2549 : mem_out_dec = 6'b000111; 12'd2550 : mem_out_dec = 6'b000111; 12'd2551 : mem_out_dec = 6'b001000; 12'd2552 : mem_out_dec = 6'b001000; 12'd2553 : mem_out_dec = 6'b001001; 12'd2554 : mem_out_dec = 6'b001010; 12'd2555 : mem_out_dec = 6'b001010; 12'd2556 : mem_out_dec = 6'b001011; 12'd2557 : mem_out_dec = 6'b001100; 12'd2558 : mem_out_dec = 6'b001101; 12'd2559 : mem_out_dec = 6'b001101; 12'd2560 : mem_out_dec = 6'b111111; 12'd2561 : mem_out_dec = 6'b111111; 12'd2562 : mem_out_dec = 6'b111111; 12'd2563 : mem_out_dec = 6'b111111; 12'd2564 : mem_out_dec = 6'b111111; 12'd2565 : mem_out_dec = 6'b111111; 12'd2566 : mem_out_dec = 6'b111111; 12'd2567 : mem_out_dec = 6'b111111; 12'd2568 : mem_out_dec = 6'b111111; 12'd2569 : mem_out_dec = 6'b111111; 12'd2570 : mem_out_dec = 6'b111111; 12'd2571 : mem_out_dec = 6'b111111; 12'd2572 : mem_out_dec = 6'b111111; 12'd2573 : mem_out_dec = 6'b111111; 12'd2574 : mem_out_dec = 6'b111111; 12'd2575 : mem_out_dec = 6'b111111; 12'd2576 : mem_out_dec = 6'b111111; 12'd2577 : mem_out_dec = 6'b111111; 12'd2578 : mem_out_dec = 6'b111111; 12'd2579 : mem_out_dec = 6'b111111; 12'd2580 : mem_out_dec = 6'b111111; 12'd2581 : mem_out_dec = 6'b111111; 12'd2582 : mem_out_dec = 6'b111111; 12'd2583 : mem_out_dec = 6'b111111; 12'd2584 : mem_out_dec = 6'b111111; 12'd2585 : mem_out_dec = 6'b111111; 12'd2586 : mem_out_dec = 6'b111111; 12'd2587 : mem_out_dec = 6'b111111; 12'd2588 : mem_out_dec = 6'b111111; 12'd2589 : mem_out_dec = 6'b111111; 12'd2590 : mem_out_dec = 6'b111111; 12'd2591 : mem_out_dec = 6'b111111; 12'd2592 : mem_out_dec = 6'b111111; 12'd2593 : mem_out_dec = 6'b111111; 12'd2594 : mem_out_dec = 6'b111111; 12'd2595 : mem_out_dec = 6'b111111; 12'd2596 : mem_out_dec = 6'b111111; 12'd2597 : mem_out_dec = 6'b111111; 12'd2598 : mem_out_dec = 6'b111111; 12'd2599 : mem_out_dec = 6'b111111; 12'd2600 : mem_out_dec = 6'b111111; 12'd2601 : mem_out_dec = 6'b111111; 12'd2602 : mem_out_dec = 6'b111111; 12'd2603 : mem_out_dec = 6'b111111; 12'd2604 : mem_out_dec = 6'b111111; 12'd2605 : mem_out_dec = 6'b111111; 12'd2606 : mem_out_dec = 6'b000100; 12'd2607 : mem_out_dec = 6'b000101; 12'd2608 : mem_out_dec = 6'b000100; 12'd2609 : mem_out_dec = 6'b000100; 12'd2610 : mem_out_dec = 6'b000100; 12'd2611 : mem_out_dec = 6'b000101; 12'd2612 : mem_out_dec = 6'b000101; 12'd2613 : mem_out_dec = 6'b000110; 12'd2614 : mem_out_dec = 6'b000111; 12'd2615 : mem_out_dec = 6'b000111; 12'd2616 : mem_out_dec = 6'b000111; 12'd2617 : mem_out_dec = 6'b001000; 12'd2618 : mem_out_dec = 6'b001001; 12'd2619 : mem_out_dec = 6'b001010; 12'd2620 : mem_out_dec = 6'b001010; 12'd2621 : mem_out_dec = 6'b001011; 12'd2622 : mem_out_dec = 6'b001100; 12'd2623 : mem_out_dec = 6'b001101; 12'd2624 : mem_out_dec = 6'b111111; 12'd2625 : mem_out_dec = 6'b111111; 12'd2626 : mem_out_dec = 6'b111111; 12'd2627 : mem_out_dec = 6'b111111; 12'd2628 : mem_out_dec = 6'b111111; 12'd2629 : mem_out_dec = 6'b111111; 12'd2630 : mem_out_dec = 6'b111111; 12'd2631 : mem_out_dec = 6'b111111; 12'd2632 : mem_out_dec = 6'b111111; 12'd2633 : mem_out_dec = 6'b111111; 12'd2634 : mem_out_dec = 6'b111111; 12'd2635 : mem_out_dec = 6'b111111; 12'd2636 : mem_out_dec = 6'b111111; 12'd2637 : mem_out_dec = 6'b111111; 12'd2638 : mem_out_dec = 6'b111111; 12'd2639 : mem_out_dec = 6'b111111; 12'd2640 : mem_out_dec = 6'b111111; 12'd2641 : mem_out_dec = 6'b111111; 12'd2642 : mem_out_dec = 6'b111111; 12'd2643 : mem_out_dec = 6'b111111; 12'd2644 : mem_out_dec = 6'b111111; 12'd2645 : mem_out_dec = 6'b111111; 12'd2646 : mem_out_dec = 6'b111111; 12'd2647 : mem_out_dec = 6'b111111; 12'd2648 : mem_out_dec = 6'b111111; 12'd2649 : mem_out_dec = 6'b111111; 12'd2650 : mem_out_dec = 6'b111111; 12'd2651 : mem_out_dec = 6'b111111; 12'd2652 : mem_out_dec = 6'b111111; 12'd2653 : mem_out_dec = 6'b111111; 12'd2654 : mem_out_dec = 6'b111111; 12'd2655 : mem_out_dec = 6'b111111; 12'd2656 : mem_out_dec = 6'b111111; 12'd2657 : mem_out_dec = 6'b111111; 12'd2658 : mem_out_dec = 6'b111111; 12'd2659 : mem_out_dec = 6'b111111; 12'd2660 : mem_out_dec = 6'b111111; 12'd2661 : mem_out_dec = 6'b111111; 12'd2662 : mem_out_dec = 6'b111111; 12'd2663 : mem_out_dec = 6'b111111; 12'd2664 : mem_out_dec = 6'b111111; 12'd2665 : mem_out_dec = 6'b111111; 12'd2666 : mem_out_dec = 6'b111111; 12'd2667 : mem_out_dec = 6'b111111; 12'd2668 : mem_out_dec = 6'b111111; 12'd2669 : mem_out_dec = 6'b111111; 12'd2670 : mem_out_dec = 6'b111111; 12'd2671 : mem_out_dec = 6'b000100; 12'd2672 : mem_out_dec = 6'b000011; 12'd2673 : mem_out_dec = 6'b000011; 12'd2674 : mem_out_dec = 6'b000100; 12'd2675 : mem_out_dec = 6'b000100; 12'd2676 : mem_out_dec = 6'b000101; 12'd2677 : mem_out_dec = 6'b000110; 12'd2678 : mem_out_dec = 6'b000110; 12'd2679 : mem_out_dec = 6'b000111; 12'd2680 : mem_out_dec = 6'b000111; 12'd2681 : mem_out_dec = 6'b001000; 12'd2682 : mem_out_dec = 6'b001001; 12'd2683 : mem_out_dec = 6'b001001; 12'd2684 : mem_out_dec = 6'b001010; 12'd2685 : mem_out_dec = 6'b001011; 12'd2686 : mem_out_dec = 6'b001100; 12'd2687 : mem_out_dec = 6'b001100; 12'd2688 : mem_out_dec = 6'b111111; 12'd2689 : mem_out_dec = 6'b111111; 12'd2690 : mem_out_dec = 6'b111111; 12'd2691 : mem_out_dec = 6'b111111; 12'd2692 : mem_out_dec = 6'b111111; 12'd2693 : mem_out_dec = 6'b111111; 12'd2694 : mem_out_dec = 6'b111111; 12'd2695 : mem_out_dec = 6'b111111; 12'd2696 : mem_out_dec = 6'b111111; 12'd2697 : mem_out_dec = 6'b111111; 12'd2698 : mem_out_dec = 6'b111111; 12'd2699 : mem_out_dec = 6'b111111; 12'd2700 : mem_out_dec = 6'b111111; 12'd2701 : mem_out_dec = 6'b111111; 12'd2702 : mem_out_dec = 6'b111111; 12'd2703 : mem_out_dec = 6'b111111; 12'd2704 : mem_out_dec = 6'b111111; 12'd2705 : mem_out_dec = 6'b111111; 12'd2706 : mem_out_dec = 6'b111111; 12'd2707 : mem_out_dec = 6'b111111; 12'd2708 : mem_out_dec = 6'b111111; 12'd2709 : mem_out_dec = 6'b111111; 12'd2710 : mem_out_dec = 6'b111111; 12'd2711 : mem_out_dec = 6'b111111; 12'd2712 : mem_out_dec = 6'b111111; 12'd2713 : mem_out_dec = 6'b111111; 12'd2714 : mem_out_dec = 6'b111111; 12'd2715 : mem_out_dec = 6'b111111; 12'd2716 : mem_out_dec = 6'b111111; 12'd2717 : mem_out_dec = 6'b111111; 12'd2718 : mem_out_dec = 6'b111111; 12'd2719 : mem_out_dec = 6'b111111; 12'd2720 : mem_out_dec = 6'b111111; 12'd2721 : mem_out_dec = 6'b111111; 12'd2722 : mem_out_dec = 6'b111111; 12'd2723 : mem_out_dec = 6'b111111; 12'd2724 : mem_out_dec = 6'b111111; 12'd2725 : mem_out_dec = 6'b111111; 12'd2726 : mem_out_dec = 6'b111111; 12'd2727 : mem_out_dec = 6'b111111; 12'd2728 : mem_out_dec = 6'b111111; 12'd2729 : mem_out_dec = 6'b111111; 12'd2730 : mem_out_dec = 6'b111111; 12'd2731 : mem_out_dec = 6'b111111; 12'd2732 : mem_out_dec = 6'b111111; 12'd2733 : mem_out_dec = 6'b111111; 12'd2734 : mem_out_dec = 6'b111111; 12'd2735 : mem_out_dec = 6'b111111; 12'd2736 : mem_out_dec = 6'b000011; 12'd2737 : mem_out_dec = 6'b000011; 12'd2738 : mem_out_dec = 6'b000100; 12'd2739 : mem_out_dec = 6'b000100; 12'd2740 : mem_out_dec = 6'b000101; 12'd2741 : mem_out_dec = 6'b000101; 12'd2742 : mem_out_dec = 6'b000110; 12'd2743 : mem_out_dec = 6'b000111; 12'd2744 : mem_out_dec = 6'b000111; 12'd2745 : mem_out_dec = 6'b001000; 12'd2746 : mem_out_dec = 6'b001000; 12'd2747 : mem_out_dec = 6'b001001; 12'd2748 : mem_out_dec = 6'b001010; 12'd2749 : mem_out_dec = 6'b001011; 12'd2750 : mem_out_dec = 6'b001011; 12'd2751 : mem_out_dec = 6'b001100; 12'd2752 : mem_out_dec = 6'b111111; 12'd2753 : mem_out_dec = 6'b111111; 12'd2754 : mem_out_dec = 6'b111111; 12'd2755 : mem_out_dec = 6'b111111; 12'd2756 : mem_out_dec = 6'b111111; 12'd2757 : mem_out_dec = 6'b111111; 12'd2758 : mem_out_dec = 6'b111111; 12'd2759 : mem_out_dec = 6'b111111; 12'd2760 : mem_out_dec = 6'b111111; 12'd2761 : mem_out_dec = 6'b111111; 12'd2762 : mem_out_dec = 6'b111111; 12'd2763 : mem_out_dec = 6'b111111; 12'd2764 : mem_out_dec = 6'b111111; 12'd2765 : mem_out_dec = 6'b111111; 12'd2766 : mem_out_dec = 6'b111111; 12'd2767 : mem_out_dec = 6'b111111; 12'd2768 : mem_out_dec = 6'b111111; 12'd2769 : mem_out_dec = 6'b111111; 12'd2770 : mem_out_dec = 6'b111111; 12'd2771 : mem_out_dec = 6'b111111; 12'd2772 : mem_out_dec = 6'b111111; 12'd2773 : mem_out_dec = 6'b111111; 12'd2774 : mem_out_dec = 6'b111111; 12'd2775 : mem_out_dec = 6'b111111; 12'd2776 : mem_out_dec = 6'b111111; 12'd2777 : mem_out_dec = 6'b111111; 12'd2778 : mem_out_dec = 6'b111111; 12'd2779 : mem_out_dec = 6'b111111; 12'd2780 : mem_out_dec = 6'b111111; 12'd2781 : mem_out_dec = 6'b111111; 12'd2782 : mem_out_dec = 6'b111111; 12'd2783 : mem_out_dec = 6'b111111; 12'd2784 : mem_out_dec = 6'b111111; 12'd2785 : mem_out_dec = 6'b111111; 12'd2786 : mem_out_dec = 6'b111111; 12'd2787 : mem_out_dec = 6'b111111; 12'd2788 : mem_out_dec = 6'b111111; 12'd2789 : mem_out_dec = 6'b111111; 12'd2790 : mem_out_dec = 6'b111111; 12'd2791 : mem_out_dec = 6'b111111; 12'd2792 : mem_out_dec = 6'b111111; 12'd2793 : mem_out_dec = 6'b111111; 12'd2794 : mem_out_dec = 6'b111111; 12'd2795 : mem_out_dec = 6'b111111; 12'd2796 : mem_out_dec = 6'b111111; 12'd2797 : mem_out_dec = 6'b111111; 12'd2798 : mem_out_dec = 6'b111111; 12'd2799 : mem_out_dec = 6'b111111; 12'd2800 : mem_out_dec = 6'b111111; 12'd2801 : mem_out_dec = 6'b000011; 12'd2802 : mem_out_dec = 6'b000011; 12'd2803 : mem_out_dec = 6'b000100; 12'd2804 : mem_out_dec = 6'b000101; 12'd2805 : mem_out_dec = 6'b000101; 12'd2806 : mem_out_dec = 6'b000110; 12'd2807 : mem_out_dec = 6'b000111; 12'd2808 : mem_out_dec = 6'b000111; 12'd2809 : mem_out_dec = 6'b000111; 12'd2810 : mem_out_dec = 6'b001000; 12'd2811 : mem_out_dec = 6'b001001; 12'd2812 : mem_out_dec = 6'b001010; 12'd2813 : mem_out_dec = 6'b001010; 12'd2814 : mem_out_dec = 6'b001011; 12'd2815 : mem_out_dec = 6'b001100; 12'd2816 : mem_out_dec = 6'b111111; 12'd2817 : mem_out_dec = 6'b111111; 12'd2818 : mem_out_dec = 6'b111111; 12'd2819 : mem_out_dec = 6'b111111; 12'd2820 : mem_out_dec = 6'b111111; 12'd2821 : mem_out_dec = 6'b111111; 12'd2822 : mem_out_dec = 6'b111111; 12'd2823 : mem_out_dec = 6'b111111; 12'd2824 : mem_out_dec = 6'b111111; 12'd2825 : mem_out_dec = 6'b111111; 12'd2826 : mem_out_dec = 6'b111111; 12'd2827 : mem_out_dec = 6'b111111; 12'd2828 : mem_out_dec = 6'b111111; 12'd2829 : mem_out_dec = 6'b111111; 12'd2830 : mem_out_dec = 6'b111111; 12'd2831 : mem_out_dec = 6'b111111; 12'd2832 : mem_out_dec = 6'b111111; 12'd2833 : mem_out_dec = 6'b111111; 12'd2834 : mem_out_dec = 6'b111111; 12'd2835 : mem_out_dec = 6'b111111; 12'd2836 : mem_out_dec = 6'b111111; 12'd2837 : mem_out_dec = 6'b111111; 12'd2838 : mem_out_dec = 6'b111111; 12'd2839 : mem_out_dec = 6'b111111; 12'd2840 : mem_out_dec = 6'b111111; 12'd2841 : mem_out_dec = 6'b111111; 12'd2842 : mem_out_dec = 6'b111111; 12'd2843 : mem_out_dec = 6'b111111; 12'd2844 : mem_out_dec = 6'b111111; 12'd2845 : mem_out_dec = 6'b111111; 12'd2846 : mem_out_dec = 6'b111111; 12'd2847 : mem_out_dec = 6'b111111; 12'd2848 : mem_out_dec = 6'b111111; 12'd2849 : mem_out_dec = 6'b111111; 12'd2850 : mem_out_dec = 6'b111111; 12'd2851 : mem_out_dec = 6'b111111; 12'd2852 : mem_out_dec = 6'b111111; 12'd2853 : mem_out_dec = 6'b111111; 12'd2854 : mem_out_dec = 6'b111111; 12'd2855 : mem_out_dec = 6'b111111; 12'd2856 : mem_out_dec = 6'b111111; 12'd2857 : mem_out_dec = 6'b111111; 12'd2858 : mem_out_dec = 6'b111111; 12'd2859 : mem_out_dec = 6'b111111; 12'd2860 : mem_out_dec = 6'b111111; 12'd2861 : mem_out_dec = 6'b111111; 12'd2862 : mem_out_dec = 6'b111111; 12'd2863 : mem_out_dec = 6'b111111; 12'd2864 : mem_out_dec = 6'b111111; 12'd2865 : mem_out_dec = 6'b111111; 12'd2866 : mem_out_dec = 6'b000011; 12'd2867 : mem_out_dec = 6'b000100; 12'd2868 : mem_out_dec = 6'b000100; 12'd2869 : mem_out_dec = 6'b000101; 12'd2870 : mem_out_dec = 6'b000110; 12'd2871 : mem_out_dec = 6'b000110; 12'd2872 : mem_out_dec = 6'b000110; 12'd2873 : mem_out_dec = 6'b000111; 12'd2874 : mem_out_dec = 6'b001000; 12'd2875 : mem_out_dec = 6'b001001; 12'd2876 : mem_out_dec = 6'b001001; 12'd2877 : mem_out_dec = 6'b001010; 12'd2878 : mem_out_dec = 6'b001011; 12'd2879 : mem_out_dec = 6'b001100; 12'd2880 : mem_out_dec = 6'b111111; 12'd2881 : mem_out_dec = 6'b111111; 12'd2882 : mem_out_dec = 6'b111111; 12'd2883 : mem_out_dec = 6'b111111; 12'd2884 : mem_out_dec = 6'b111111; 12'd2885 : mem_out_dec = 6'b111111; 12'd2886 : mem_out_dec = 6'b111111; 12'd2887 : mem_out_dec = 6'b111111; 12'd2888 : mem_out_dec = 6'b111111; 12'd2889 : mem_out_dec = 6'b111111; 12'd2890 : mem_out_dec = 6'b111111; 12'd2891 : mem_out_dec = 6'b111111; 12'd2892 : mem_out_dec = 6'b111111; 12'd2893 : mem_out_dec = 6'b111111; 12'd2894 : mem_out_dec = 6'b111111; 12'd2895 : mem_out_dec = 6'b111111; 12'd2896 : mem_out_dec = 6'b111111; 12'd2897 : mem_out_dec = 6'b111111; 12'd2898 : mem_out_dec = 6'b111111; 12'd2899 : mem_out_dec = 6'b111111; 12'd2900 : mem_out_dec = 6'b111111; 12'd2901 : mem_out_dec = 6'b111111; 12'd2902 : mem_out_dec = 6'b111111; 12'd2903 : mem_out_dec = 6'b111111; 12'd2904 : mem_out_dec = 6'b111111; 12'd2905 : mem_out_dec = 6'b111111; 12'd2906 : mem_out_dec = 6'b111111; 12'd2907 : mem_out_dec = 6'b111111; 12'd2908 : mem_out_dec = 6'b111111; 12'd2909 : mem_out_dec = 6'b111111; 12'd2910 : mem_out_dec = 6'b111111; 12'd2911 : mem_out_dec = 6'b111111; 12'd2912 : mem_out_dec = 6'b111111; 12'd2913 : mem_out_dec = 6'b111111; 12'd2914 : mem_out_dec = 6'b111111; 12'd2915 : mem_out_dec = 6'b111111; 12'd2916 : mem_out_dec = 6'b111111; 12'd2917 : mem_out_dec = 6'b111111; 12'd2918 : mem_out_dec = 6'b111111; 12'd2919 : mem_out_dec = 6'b111111; 12'd2920 : mem_out_dec = 6'b111111; 12'd2921 : mem_out_dec = 6'b111111; 12'd2922 : mem_out_dec = 6'b111111; 12'd2923 : mem_out_dec = 6'b111111; 12'd2924 : mem_out_dec = 6'b111111; 12'd2925 : mem_out_dec = 6'b111111; 12'd2926 : mem_out_dec = 6'b111111; 12'd2927 : mem_out_dec = 6'b111111; 12'd2928 : mem_out_dec = 6'b111111; 12'd2929 : mem_out_dec = 6'b111111; 12'd2930 : mem_out_dec = 6'b111111; 12'd2931 : mem_out_dec = 6'b000100; 12'd2932 : mem_out_dec = 6'b000100; 12'd2933 : mem_out_dec = 6'b000101; 12'd2934 : mem_out_dec = 6'b000101; 12'd2935 : mem_out_dec = 6'b000110; 12'd2936 : mem_out_dec = 6'b000110; 12'd2937 : mem_out_dec = 6'b000111; 12'd2938 : mem_out_dec = 6'b001000; 12'd2939 : mem_out_dec = 6'b001000; 12'd2940 : mem_out_dec = 6'b001001; 12'd2941 : mem_out_dec = 6'b001010; 12'd2942 : mem_out_dec = 6'b001011; 12'd2943 : mem_out_dec = 6'b001011; 12'd2944 : mem_out_dec = 6'b111111; 12'd2945 : mem_out_dec = 6'b111111; 12'd2946 : mem_out_dec = 6'b111111; 12'd2947 : mem_out_dec = 6'b111111; 12'd2948 : mem_out_dec = 6'b111111; 12'd2949 : mem_out_dec = 6'b111111; 12'd2950 : mem_out_dec = 6'b111111; 12'd2951 : mem_out_dec = 6'b111111; 12'd2952 : mem_out_dec = 6'b111111; 12'd2953 : mem_out_dec = 6'b111111; 12'd2954 : mem_out_dec = 6'b111111; 12'd2955 : mem_out_dec = 6'b111111; 12'd2956 : mem_out_dec = 6'b111111; 12'd2957 : mem_out_dec = 6'b111111; 12'd2958 : mem_out_dec = 6'b111111; 12'd2959 : mem_out_dec = 6'b111111; 12'd2960 : mem_out_dec = 6'b111111; 12'd2961 : mem_out_dec = 6'b111111; 12'd2962 : mem_out_dec = 6'b111111; 12'd2963 : mem_out_dec = 6'b111111; 12'd2964 : mem_out_dec = 6'b111111; 12'd2965 : mem_out_dec = 6'b111111; 12'd2966 : mem_out_dec = 6'b111111; 12'd2967 : mem_out_dec = 6'b111111; 12'd2968 : mem_out_dec = 6'b111111; 12'd2969 : mem_out_dec = 6'b111111; 12'd2970 : mem_out_dec = 6'b111111; 12'd2971 : mem_out_dec = 6'b111111; 12'd2972 : mem_out_dec = 6'b111111; 12'd2973 : mem_out_dec = 6'b111111; 12'd2974 : mem_out_dec = 6'b111111; 12'd2975 : mem_out_dec = 6'b111111; 12'd2976 : mem_out_dec = 6'b111111; 12'd2977 : mem_out_dec = 6'b111111; 12'd2978 : mem_out_dec = 6'b111111; 12'd2979 : mem_out_dec = 6'b111111; 12'd2980 : mem_out_dec = 6'b111111; 12'd2981 : mem_out_dec = 6'b111111; 12'd2982 : mem_out_dec = 6'b111111; 12'd2983 : mem_out_dec = 6'b111111; 12'd2984 : mem_out_dec = 6'b111111; 12'd2985 : mem_out_dec = 6'b111111; 12'd2986 : mem_out_dec = 6'b111111; 12'd2987 : mem_out_dec = 6'b111111; 12'd2988 : mem_out_dec = 6'b111111; 12'd2989 : mem_out_dec = 6'b111111; 12'd2990 : mem_out_dec = 6'b111111; 12'd2991 : mem_out_dec = 6'b111111; 12'd2992 : mem_out_dec = 6'b111111; 12'd2993 : mem_out_dec = 6'b111111; 12'd2994 : mem_out_dec = 6'b111111; 12'd2995 : mem_out_dec = 6'b111111; 12'd2996 : mem_out_dec = 6'b000100; 12'd2997 : mem_out_dec = 6'b000101; 12'd2998 : mem_out_dec = 6'b000101; 12'd2999 : mem_out_dec = 6'b000110; 12'd3000 : mem_out_dec = 6'b000110; 12'd3001 : mem_out_dec = 6'b000111; 12'd3002 : mem_out_dec = 6'b000111; 12'd3003 : mem_out_dec = 6'b001000; 12'd3004 : mem_out_dec = 6'b001001; 12'd3005 : mem_out_dec = 6'b001010; 12'd3006 : mem_out_dec = 6'b001010; 12'd3007 : mem_out_dec = 6'b001011; 12'd3008 : mem_out_dec = 6'b111111; 12'd3009 : mem_out_dec = 6'b111111; 12'd3010 : mem_out_dec = 6'b111111; 12'd3011 : mem_out_dec = 6'b111111; 12'd3012 : mem_out_dec = 6'b111111; 12'd3013 : mem_out_dec = 6'b111111; 12'd3014 : mem_out_dec = 6'b111111; 12'd3015 : mem_out_dec = 6'b111111; 12'd3016 : mem_out_dec = 6'b111111; 12'd3017 : mem_out_dec = 6'b111111; 12'd3018 : mem_out_dec = 6'b111111; 12'd3019 : mem_out_dec = 6'b111111; 12'd3020 : mem_out_dec = 6'b111111; 12'd3021 : mem_out_dec = 6'b111111; 12'd3022 : mem_out_dec = 6'b111111; 12'd3023 : mem_out_dec = 6'b111111; 12'd3024 : mem_out_dec = 6'b111111; 12'd3025 : mem_out_dec = 6'b111111; 12'd3026 : mem_out_dec = 6'b111111; 12'd3027 : mem_out_dec = 6'b111111; 12'd3028 : mem_out_dec = 6'b111111; 12'd3029 : mem_out_dec = 6'b111111; 12'd3030 : mem_out_dec = 6'b111111; 12'd3031 : mem_out_dec = 6'b111111; 12'd3032 : mem_out_dec = 6'b111111; 12'd3033 : mem_out_dec = 6'b111111; 12'd3034 : mem_out_dec = 6'b111111; 12'd3035 : mem_out_dec = 6'b111111; 12'd3036 : mem_out_dec = 6'b111111; 12'd3037 : mem_out_dec = 6'b111111; 12'd3038 : mem_out_dec = 6'b111111; 12'd3039 : mem_out_dec = 6'b111111; 12'd3040 : mem_out_dec = 6'b111111; 12'd3041 : mem_out_dec = 6'b111111; 12'd3042 : mem_out_dec = 6'b111111; 12'd3043 : mem_out_dec = 6'b111111; 12'd3044 : mem_out_dec = 6'b111111; 12'd3045 : mem_out_dec = 6'b111111; 12'd3046 : mem_out_dec = 6'b111111; 12'd3047 : mem_out_dec = 6'b111111; 12'd3048 : mem_out_dec = 6'b111111; 12'd3049 : mem_out_dec = 6'b111111; 12'd3050 : mem_out_dec = 6'b111111; 12'd3051 : mem_out_dec = 6'b111111; 12'd3052 : mem_out_dec = 6'b111111; 12'd3053 : mem_out_dec = 6'b111111; 12'd3054 : mem_out_dec = 6'b111111; 12'd3055 : mem_out_dec = 6'b111111; 12'd3056 : mem_out_dec = 6'b111111; 12'd3057 : mem_out_dec = 6'b111111; 12'd3058 : mem_out_dec = 6'b111111; 12'd3059 : mem_out_dec = 6'b111111; 12'd3060 : mem_out_dec = 6'b111111; 12'd3061 : mem_out_dec = 6'b000100; 12'd3062 : mem_out_dec = 6'b000101; 12'd3063 : mem_out_dec = 6'b000110; 12'd3064 : mem_out_dec = 6'b000110; 12'd3065 : mem_out_dec = 6'b000111; 12'd3066 : mem_out_dec = 6'b000111; 12'd3067 : mem_out_dec = 6'b001000; 12'd3068 : mem_out_dec = 6'b001001; 12'd3069 : mem_out_dec = 6'b001001; 12'd3070 : mem_out_dec = 6'b001010; 12'd3071 : mem_out_dec = 6'b001011; 12'd3072 : mem_out_dec = 6'b111111; 12'd3073 : mem_out_dec = 6'b111111; 12'd3074 : mem_out_dec = 6'b111111; 12'd3075 : mem_out_dec = 6'b111111; 12'd3076 : mem_out_dec = 6'b111111; 12'd3077 : mem_out_dec = 6'b111111; 12'd3078 : mem_out_dec = 6'b111111; 12'd3079 : mem_out_dec = 6'b111111; 12'd3080 : mem_out_dec = 6'b111111; 12'd3081 : mem_out_dec = 6'b111111; 12'd3082 : mem_out_dec = 6'b111111; 12'd3083 : mem_out_dec = 6'b111111; 12'd3084 : mem_out_dec = 6'b111111; 12'd3085 : mem_out_dec = 6'b111111; 12'd3086 : mem_out_dec = 6'b111111; 12'd3087 : mem_out_dec = 6'b111111; 12'd3088 : mem_out_dec = 6'b111111; 12'd3089 : mem_out_dec = 6'b111111; 12'd3090 : mem_out_dec = 6'b111111; 12'd3091 : mem_out_dec = 6'b111111; 12'd3092 : mem_out_dec = 6'b111111; 12'd3093 : mem_out_dec = 6'b111111; 12'd3094 : mem_out_dec = 6'b111111; 12'd3095 : mem_out_dec = 6'b111111; 12'd3096 : mem_out_dec = 6'b111111; 12'd3097 : mem_out_dec = 6'b111111; 12'd3098 : mem_out_dec = 6'b111111; 12'd3099 : mem_out_dec = 6'b111111; 12'd3100 : mem_out_dec = 6'b111111; 12'd3101 : mem_out_dec = 6'b111111; 12'd3102 : mem_out_dec = 6'b111111; 12'd3103 : mem_out_dec = 6'b111111; 12'd3104 : mem_out_dec = 6'b111111; 12'd3105 : mem_out_dec = 6'b111111; 12'd3106 : mem_out_dec = 6'b111111; 12'd3107 : mem_out_dec = 6'b111111; 12'd3108 : mem_out_dec = 6'b111111; 12'd3109 : mem_out_dec = 6'b111111; 12'd3110 : mem_out_dec = 6'b111111; 12'd3111 : mem_out_dec = 6'b111111; 12'd3112 : mem_out_dec = 6'b111111; 12'd3113 : mem_out_dec = 6'b111111; 12'd3114 : mem_out_dec = 6'b111111; 12'd3115 : mem_out_dec = 6'b111111; 12'd3116 : mem_out_dec = 6'b111111; 12'd3117 : mem_out_dec = 6'b111111; 12'd3118 : mem_out_dec = 6'b111111; 12'd3119 : mem_out_dec = 6'b111111; 12'd3120 : mem_out_dec = 6'b111111; 12'd3121 : mem_out_dec = 6'b111111; 12'd3122 : mem_out_dec = 6'b111111; 12'd3123 : mem_out_dec = 6'b111111; 12'd3124 : mem_out_dec = 6'b111111; 12'd3125 : mem_out_dec = 6'b111111; 12'd3126 : mem_out_dec = 6'b000100; 12'd3127 : mem_out_dec = 6'b000101; 12'd3128 : mem_out_dec = 6'b000101; 12'd3129 : mem_out_dec = 6'b000110; 12'd3130 : mem_out_dec = 6'b000110; 12'd3131 : mem_out_dec = 6'b000111; 12'd3132 : mem_out_dec = 6'b001000; 12'd3133 : mem_out_dec = 6'b001000; 12'd3134 : mem_out_dec = 6'b001001; 12'd3135 : mem_out_dec = 6'b001010; 12'd3136 : mem_out_dec = 6'b111111; 12'd3137 : mem_out_dec = 6'b111111; 12'd3138 : mem_out_dec = 6'b111111; 12'd3139 : mem_out_dec = 6'b111111; 12'd3140 : mem_out_dec = 6'b111111; 12'd3141 : mem_out_dec = 6'b111111; 12'd3142 : mem_out_dec = 6'b111111; 12'd3143 : mem_out_dec = 6'b111111; 12'd3144 : mem_out_dec = 6'b111111; 12'd3145 : mem_out_dec = 6'b111111; 12'd3146 : mem_out_dec = 6'b111111; 12'd3147 : mem_out_dec = 6'b111111; 12'd3148 : mem_out_dec = 6'b111111; 12'd3149 : mem_out_dec = 6'b111111; 12'd3150 : mem_out_dec = 6'b111111; 12'd3151 : mem_out_dec = 6'b111111; 12'd3152 : mem_out_dec = 6'b111111; 12'd3153 : mem_out_dec = 6'b111111; 12'd3154 : mem_out_dec = 6'b111111; 12'd3155 : mem_out_dec = 6'b111111; 12'd3156 : mem_out_dec = 6'b111111; 12'd3157 : mem_out_dec = 6'b111111; 12'd3158 : mem_out_dec = 6'b111111; 12'd3159 : mem_out_dec = 6'b111111; 12'd3160 : mem_out_dec = 6'b111111; 12'd3161 : mem_out_dec = 6'b111111; 12'd3162 : mem_out_dec = 6'b111111; 12'd3163 : mem_out_dec = 6'b111111; 12'd3164 : mem_out_dec = 6'b111111; 12'd3165 : mem_out_dec = 6'b111111; 12'd3166 : mem_out_dec = 6'b111111; 12'd3167 : mem_out_dec = 6'b111111; 12'd3168 : mem_out_dec = 6'b111111; 12'd3169 : mem_out_dec = 6'b111111; 12'd3170 : mem_out_dec = 6'b111111; 12'd3171 : mem_out_dec = 6'b111111; 12'd3172 : mem_out_dec = 6'b111111; 12'd3173 : mem_out_dec = 6'b111111; 12'd3174 : mem_out_dec = 6'b111111; 12'd3175 : mem_out_dec = 6'b111111; 12'd3176 : mem_out_dec = 6'b111111; 12'd3177 : mem_out_dec = 6'b111111; 12'd3178 : mem_out_dec = 6'b111111; 12'd3179 : mem_out_dec = 6'b111111; 12'd3180 : mem_out_dec = 6'b111111; 12'd3181 : mem_out_dec = 6'b111111; 12'd3182 : mem_out_dec = 6'b111111; 12'd3183 : mem_out_dec = 6'b111111; 12'd3184 : mem_out_dec = 6'b111111; 12'd3185 : mem_out_dec = 6'b111111; 12'd3186 : mem_out_dec = 6'b111111; 12'd3187 : mem_out_dec = 6'b111111; 12'd3188 : mem_out_dec = 6'b111111; 12'd3189 : mem_out_dec = 6'b111111; 12'd3190 : mem_out_dec = 6'b111111; 12'd3191 : mem_out_dec = 6'b000100; 12'd3192 : mem_out_dec = 6'b000100; 12'd3193 : mem_out_dec = 6'b000101; 12'd3194 : mem_out_dec = 6'b000110; 12'd3195 : mem_out_dec = 6'b000110; 12'd3196 : mem_out_dec = 6'b000111; 12'd3197 : mem_out_dec = 6'b001000; 12'd3198 : mem_out_dec = 6'b001000; 12'd3199 : mem_out_dec = 6'b001001; 12'd3200 : mem_out_dec = 6'b111111; 12'd3201 : mem_out_dec = 6'b111111; 12'd3202 : mem_out_dec = 6'b111111; 12'd3203 : mem_out_dec = 6'b111111; 12'd3204 : mem_out_dec = 6'b111111; 12'd3205 : mem_out_dec = 6'b111111; 12'd3206 : mem_out_dec = 6'b111111; 12'd3207 : mem_out_dec = 6'b111111; 12'd3208 : mem_out_dec = 6'b111111; 12'd3209 : mem_out_dec = 6'b111111; 12'd3210 : mem_out_dec = 6'b111111; 12'd3211 : mem_out_dec = 6'b111111; 12'd3212 : mem_out_dec = 6'b111111; 12'd3213 : mem_out_dec = 6'b111111; 12'd3214 : mem_out_dec = 6'b111111; 12'd3215 : mem_out_dec = 6'b111111; 12'd3216 : mem_out_dec = 6'b111111; 12'd3217 : mem_out_dec = 6'b111111; 12'd3218 : mem_out_dec = 6'b111111; 12'd3219 : mem_out_dec = 6'b111111; 12'd3220 : mem_out_dec = 6'b111111; 12'd3221 : mem_out_dec = 6'b111111; 12'd3222 : mem_out_dec = 6'b111111; 12'd3223 : mem_out_dec = 6'b111111; 12'd3224 : mem_out_dec = 6'b111111; 12'd3225 : mem_out_dec = 6'b111111; 12'd3226 : mem_out_dec = 6'b111111; 12'd3227 : mem_out_dec = 6'b111111; 12'd3228 : mem_out_dec = 6'b111111; 12'd3229 : mem_out_dec = 6'b111111; 12'd3230 : mem_out_dec = 6'b111111; 12'd3231 : mem_out_dec = 6'b111111; 12'd3232 : mem_out_dec = 6'b111111; 12'd3233 : mem_out_dec = 6'b111111; 12'd3234 : mem_out_dec = 6'b111111; 12'd3235 : mem_out_dec = 6'b111111; 12'd3236 : mem_out_dec = 6'b111111; 12'd3237 : mem_out_dec = 6'b111111; 12'd3238 : mem_out_dec = 6'b111111; 12'd3239 : mem_out_dec = 6'b111111; 12'd3240 : mem_out_dec = 6'b111111; 12'd3241 : mem_out_dec = 6'b111111; 12'd3242 : mem_out_dec = 6'b111111; 12'd3243 : mem_out_dec = 6'b111111; 12'd3244 : mem_out_dec = 6'b111111; 12'd3245 : mem_out_dec = 6'b111111; 12'd3246 : mem_out_dec = 6'b111111; 12'd3247 : mem_out_dec = 6'b111111; 12'd3248 : mem_out_dec = 6'b111111; 12'd3249 : mem_out_dec = 6'b111111; 12'd3250 : mem_out_dec = 6'b111111; 12'd3251 : mem_out_dec = 6'b111111; 12'd3252 : mem_out_dec = 6'b111111; 12'd3253 : mem_out_dec = 6'b111111; 12'd3254 : mem_out_dec = 6'b111111; 12'd3255 : mem_out_dec = 6'b111111; 12'd3256 : mem_out_dec = 6'b000100; 12'd3257 : mem_out_dec = 6'b000100; 12'd3258 : mem_out_dec = 6'b000101; 12'd3259 : mem_out_dec = 6'b000110; 12'd3260 : mem_out_dec = 6'b000110; 12'd3261 : mem_out_dec = 6'b000111; 12'd3262 : mem_out_dec = 6'b001000; 12'd3263 : mem_out_dec = 6'b001001; 12'd3264 : mem_out_dec = 6'b111111; 12'd3265 : mem_out_dec = 6'b111111; 12'd3266 : mem_out_dec = 6'b111111; 12'd3267 : mem_out_dec = 6'b111111; 12'd3268 : mem_out_dec = 6'b111111; 12'd3269 : mem_out_dec = 6'b111111; 12'd3270 : mem_out_dec = 6'b111111; 12'd3271 : mem_out_dec = 6'b111111; 12'd3272 : mem_out_dec = 6'b111111; 12'd3273 : mem_out_dec = 6'b111111; 12'd3274 : mem_out_dec = 6'b111111; 12'd3275 : mem_out_dec = 6'b111111; 12'd3276 : mem_out_dec = 6'b111111; 12'd3277 : mem_out_dec = 6'b111111; 12'd3278 : mem_out_dec = 6'b111111; 12'd3279 : mem_out_dec = 6'b111111; 12'd3280 : mem_out_dec = 6'b111111; 12'd3281 : mem_out_dec = 6'b111111; 12'd3282 : mem_out_dec = 6'b111111; 12'd3283 : mem_out_dec = 6'b111111; 12'd3284 : mem_out_dec = 6'b111111; 12'd3285 : mem_out_dec = 6'b111111; 12'd3286 : mem_out_dec = 6'b111111; 12'd3287 : mem_out_dec = 6'b111111; 12'd3288 : mem_out_dec = 6'b111111; 12'd3289 : mem_out_dec = 6'b111111; 12'd3290 : mem_out_dec = 6'b111111; 12'd3291 : mem_out_dec = 6'b111111; 12'd3292 : mem_out_dec = 6'b111111; 12'd3293 : mem_out_dec = 6'b111111; 12'd3294 : mem_out_dec = 6'b111111; 12'd3295 : mem_out_dec = 6'b111111; 12'd3296 : mem_out_dec = 6'b111111; 12'd3297 : mem_out_dec = 6'b111111; 12'd3298 : mem_out_dec = 6'b111111; 12'd3299 : mem_out_dec = 6'b111111; 12'd3300 : mem_out_dec = 6'b111111; 12'd3301 : mem_out_dec = 6'b111111; 12'd3302 : mem_out_dec = 6'b111111; 12'd3303 : mem_out_dec = 6'b111111; 12'd3304 : mem_out_dec = 6'b111111; 12'd3305 : mem_out_dec = 6'b111111; 12'd3306 : mem_out_dec = 6'b111111; 12'd3307 : mem_out_dec = 6'b111111; 12'd3308 : mem_out_dec = 6'b111111; 12'd3309 : mem_out_dec = 6'b111111; 12'd3310 : mem_out_dec = 6'b111111; 12'd3311 : mem_out_dec = 6'b111111; 12'd3312 : mem_out_dec = 6'b111111; 12'd3313 : mem_out_dec = 6'b111111; 12'd3314 : mem_out_dec = 6'b111111; 12'd3315 : mem_out_dec = 6'b111111; 12'd3316 : mem_out_dec = 6'b111111; 12'd3317 : mem_out_dec = 6'b111111; 12'd3318 : mem_out_dec = 6'b111111; 12'd3319 : mem_out_dec = 6'b111111; 12'd3320 : mem_out_dec = 6'b111111; 12'd3321 : mem_out_dec = 6'b000100; 12'd3322 : mem_out_dec = 6'b000100; 12'd3323 : mem_out_dec = 6'b000101; 12'd3324 : mem_out_dec = 6'b000110; 12'd3325 : mem_out_dec = 6'b000111; 12'd3326 : mem_out_dec = 6'b001000; 12'd3327 : mem_out_dec = 6'b001000; 12'd3328 : mem_out_dec = 6'b111111; 12'd3329 : mem_out_dec = 6'b111111; 12'd3330 : mem_out_dec = 6'b111111; 12'd3331 : mem_out_dec = 6'b111111; 12'd3332 : mem_out_dec = 6'b111111; 12'd3333 : mem_out_dec = 6'b111111; 12'd3334 : mem_out_dec = 6'b111111; 12'd3335 : mem_out_dec = 6'b111111; 12'd3336 : mem_out_dec = 6'b111111; 12'd3337 : mem_out_dec = 6'b111111; 12'd3338 : mem_out_dec = 6'b111111; 12'd3339 : mem_out_dec = 6'b111111; 12'd3340 : mem_out_dec = 6'b111111; 12'd3341 : mem_out_dec = 6'b111111; 12'd3342 : mem_out_dec = 6'b111111; 12'd3343 : mem_out_dec = 6'b111111; 12'd3344 : mem_out_dec = 6'b111111; 12'd3345 : mem_out_dec = 6'b111111; 12'd3346 : mem_out_dec = 6'b111111; 12'd3347 : mem_out_dec = 6'b111111; 12'd3348 : mem_out_dec = 6'b111111; 12'd3349 : mem_out_dec = 6'b111111; 12'd3350 : mem_out_dec = 6'b111111; 12'd3351 : mem_out_dec = 6'b111111; 12'd3352 : mem_out_dec = 6'b111111; 12'd3353 : mem_out_dec = 6'b111111; 12'd3354 : mem_out_dec = 6'b111111; 12'd3355 : mem_out_dec = 6'b111111; 12'd3356 : mem_out_dec = 6'b111111; 12'd3357 : mem_out_dec = 6'b111111; 12'd3358 : mem_out_dec = 6'b111111; 12'd3359 : mem_out_dec = 6'b111111; 12'd3360 : mem_out_dec = 6'b111111; 12'd3361 : mem_out_dec = 6'b111111; 12'd3362 : mem_out_dec = 6'b111111; 12'd3363 : mem_out_dec = 6'b111111; 12'd3364 : mem_out_dec = 6'b111111; 12'd3365 : mem_out_dec = 6'b111111; 12'd3366 : mem_out_dec = 6'b111111; 12'd3367 : mem_out_dec = 6'b111111; 12'd3368 : mem_out_dec = 6'b111111; 12'd3369 : mem_out_dec = 6'b111111; 12'd3370 : mem_out_dec = 6'b111111; 12'd3371 : mem_out_dec = 6'b111111; 12'd3372 : mem_out_dec = 6'b111111; 12'd3373 : mem_out_dec = 6'b111111; 12'd3374 : mem_out_dec = 6'b111111; 12'd3375 : mem_out_dec = 6'b111111; 12'd3376 : mem_out_dec = 6'b111111; 12'd3377 : mem_out_dec = 6'b111111; 12'd3378 : mem_out_dec = 6'b111111; 12'd3379 : mem_out_dec = 6'b111111; 12'd3380 : mem_out_dec = 6'b111111; 12'd3381 : mem_out_dec = 6'b111111; 12'd3382 : mem_out_dec = 6'b111111; 12'd3383 : mem_out_dec = 6'b111111; 12'd3384 : mem_out_dec = 6'b111111; 12'd3385 : mem_out_dec = 6'b111111; 12'd3386 : mem_out_dec = 6'b000100; 12'd3387 : mem_out_dec = 6'b000101; 12'd3388 : mem_out_dec = 6'b000110; 12'd3389 : mem_out_dec = 6'b000110; 12'd3390 : mem_out_dec = 6'b000111; 12'd3391 : mem_out_dec = 6'b001000; 12'd3392 : mem_out_dec = 6'b111111; 12'd3393 : mem_out_dec = 6'b111111; 12'd3394 : mem_out_dec = 6'b111111; 12'd3395 : mem_out_dec = 6'b111111; 12'd3396 : mem_out_dec = 6'b111111; 12'd3397 : mem_out_dec = 6'b111111; 12'd3398 : mem_out_dec = 6'b111111; 12'd3399 : mem_out_dec = 6'b111111; 12'd3400 : mem_out_dec = 6'b111111; 12'd3401 : mem_out_dec = 6'b111111; 12'd3402 : mem_out_dec = 6'b111111; 12'd3403 : mem_out_dec = 6'b111111; 12'd3404 : mem_out_dec = 6'b111111; 12'd3405 : mem_out_dec = 6'b111111; 12'd3406 : mem_out_dec = 6'b111111; 12'd3407 : mem_out_dec = 6'b111111; 12'd3408 : mem_out_dec = 6'b111111; 12'd3409 : mem_out_dec = 6'b111111; 12'd3410 : mem_out_dec = 6'b111111; 12'd3411 : mem_out_dec = 6'b111111; 12'd3412 : mem_out_dec = 6'b111111; 12'd3413 : mem_out_dec = 6'b111111; 12'd3414 : mem_out_dec = 6'b111111; 12'd3415 : mem_out_dec = 6'b111111; 12'd3416 : mem_out_dec = 6'b111111; 12'd3417 : mem_out_dec = 6'b111111; 12'd3418 : mem_out_dec = 6'b111111; 12'd3419 : mem_out_dec = 6'b111111; 12'd3420 : mem_out_dec = 6'b111111; 12'd3421 : mem_out_dec = 6'b111111; 12'd3422 : mem_out_dec = 6'b111111; 12'd3423 : mem_out_dec = 6'b111111; 12'd3424 : mem_out_dec = 6'b111111; 12'd3425 : mem_out_dec = 6'b111111; 12'd3426 : mem_out_dec = 6'b111111; 12'd3427 : mem_out_dec = 6'b111111; 12'd3428 : mem_out_dec = 6'b111111; 12'd3429 : mem_out_dec = 6'b111111; 12'd3430 : mem_out_dec = 6'b111111; 12'd3431 : mem_out_dec = 6'b111111; 12'd3432 : mem_out_dec = 6'b111111; 12'd3433 : mem_out_dec = 6'b111111; 12'd3434 : mem_out_dec = 6'b111111; 12'd3435 : mem_out_dec = 6'b111111; 12'd3436 : mem_out_dec = 6'b111111; 12'd3437 : mem_out_dec = 6'b111111; 12'd3438 : mem_out_dec = 6'b111111; 12'd3439 : mem_out_dec = 6'b111111; 12'd3440 : mem_out_dec = 6'b111111; 12'd3441 : mem_out_dec = 6'b111111; 12'd3442 : mem_out_dec = 6'b111111; 12'd3443 : mem_out_dec = 6'b111111; 12'd3444 : mem_out_dec = 6'b111111; 12'd3445 : mem_out_dec = 6'b111111; 12'd3446 : mem_out_dec = 6'b111111; 12'd3447 : mem_out_dec = 6'b111111; 12'd3448 : mem_out_dec = 6'b111111; 12'd3449 : mem_out_dec = 6'b111111; 12'd3450 : mem_out_dec = 6'b111111; 12'd3451 : mem_out_dec = 6'b000100; 12'd3452 : mem_out_dec = 6'b000101; 12'd3453 : mem_out_dec = 6'b000110; 12'd3454 : mem_out_dec = 6'b000111; 12'd3455 : mem_out_dec = 6'b001000; 12'd3456 : mem_out_dec = 6'b111111; 12'd3457 : mem_out_dec = 6'b111111; 12'd3458 : mem_out_dec = 6'b111111; 12'd3459 : mem_out_dec = 6'b111111; 12'd3460 : mem_out_dec = 6'b111111; 12'd3461 : mem_out_dec = 6'b111111; 12'd3462 : mem_out_dec = 6'b111111; 12'd3463 : mem_out_dec = 6'b111111; 12'd3464 : mem_out_dec = 6'b111111; 12'd3465 : mem_out_dec = 6'b111111; 12'd3466 : mem_out_dec = 6'b111111; 12'd3467 : mem_out_dec = 6'b111111; 12'd3468 : mem_out_dec = 6'b111111; 12'd3469 : mem_out_dec = 6'b111111; 12'd3470 : mem_out_dec = 6'b111111; 12'd3471 : mem_out_dec = 6'b111111; 12'd3472 : mem_out_dec = 6'b111111; 12'd3473 : mem_out_dec = 6'b111111; 12'd3474 : mem_out_dec = 6'b111111; 12'd3475 : mem_out_dec = 6'b111111; 12'd3476 : mem_out_dec = 6'b111111; 12'd3477 : mem_out_dec = 6'b111111; 12'd3478 : mem_out_dec = 6'b111111; 12'd3479 : mem_out_dec = 6'b111111; 12'd3480 : mem_out_dec = 6'b111111; 12'd3481 : mem_out_dec = 6'b111111; 12'd3482 : mem_out_dec = 6'b111111; 12'd3483 : mem_out_dec = 6'b111111; 12'd3484 : mem_out_dec = 6'b111111; 12'd3485 : mem_out_dec = 6'b111111; 12'd3486 : mem_out_dec = 6'b111111; 12'd3487 : mem_out_dec = 6'b111111; 12'd3488 : mem_out_dec = 6'b111111; 12'd3489 : mem_out_dec = 6'b111111; 12'd3490 : mem_out_dec = 6'b111111; 12'd3491 : mem_out_dec = 6'b111111; 12'd3492 : mem_out_dec = 6'b111111; 12'd3493 : mem_out_dec = 6'b111111; 12'd3494 : mem_out_dec = 6'b111111; 12'd3495 : mem_out_dec = 6'b111111; 12'd3496 : mem_out_dec = 6'b111111; 12'd3497 : mem_out_dec = 6'b111111; 12'd3498 : mem_out_dec = 6'b111111; 12'd3499 : mem_out_dec = 6'b111111; 12'd3500 : mem_out_dec = 6'b111111; 12'd3501 : mem_out_dec = 6'b111111; 12'd3502 : mem_out_dec = 6'b111111; 12'd3503 : mem_out_dec = 6'b111111; 12'd3504 : mem_out_dec = 6'b111111; 12'd3505 : mem_out_dec = 6'b111111; 12'd3506 : mem_out_dec = 6'b111111; 12'd3507 : mem_out_dec = 6'b111111; 12'd3508 : mem_out_dec = 6'b111111; 12'd3509 : mem_out_dec = 6'b111111; 12'd3510 : mem_out_dec = 6'b111111; 12'd3511 : mem_out_dec = 6'b111111; 12'd3512 : mem_out_dec = 6'b111111; 12'd3513 : mem_out_dec = 6'b111111; 12'd3514 : mem_out_dec = 6'b111111; 12'd3515 : mem_out_dec = 6'b111111; 12'd3516 : mem_out_dec = 6'b000101; 12'd3517 : mem_out_dec = 6'b000110; 12'd3518 : mem_out_dec = 6'b000110; 12'd3519 : mem_out_dec = 6'b000111; 12'd3520 : mem_out_dec = 6'b111111; 12'd3521 : mem_out_dec = 6'b111111; 12'd3522 : mem_out_dec = 6'b111111; 12'd3523 : mem_out_dec = 6'b111111; 12'd3524 : mem_out_dec = 6'b111111; 12'd3525 : mem_out_dec = 6'b111111; 12'd3526 : mem_out_dec = 6'b111111; 12'd3527 : mem_out_dec = 6'b111111; 12'd3528 : mem_out_dec = 6'b111111; 12'd3529 : mem_out_dec = 6'b111111; 12'd3530 : mem_out_dec = 6'b111111; 12'd3531 : mem_out_dec = 6'b111111; 12'd3532 : mem_out_dec = 6'b111111; 12'd3533 : mem_out_dec = 6'b111111; 12'd3534 : mem_out_dec = 6'b111111; 12'd3535 : mem_out_dec = 6'b111111; 12'd3536 : mem_out_dec = 6'b111111; 12'd3537 : mem_out_dec = 6'b111111; 12'd3538 : mem_out_dec = 6'b111111; 12'd3539 : mem_out_dec = 6'b111111; 12'd3540 : mem_out_dec = 6'b111111; 12'd3541 : mem_out_dec = 6'b111111; 12'd3542 : mem_out_dec = 6'b111111; 12'd3543 : mem_out_dec = 6'b111111; 12'd3544 : mem_out_dec = 6'b111111; 12'd3545 : mem_out_dec = 6'b111111; 12'd3546 : mem_out_dec = 6'b111111; 12'd3547 : mem_out_dec = 6'b111111; 12'd3548 : mem_out_dec = 6'b111111; 12'd3549 : mem_out_dec = 6'b111111; 12'd3550 : mem_out_dec = 6'b111111; 12'd3551 : mem_out_dec = 6'b111111; 12'd3552 : mem_out_dec = 6'b111111; 12'd3553 : mem_out_dec = 6'b111111; 12'd3554 : mem_out_dec = 6'b111111; 12'd3555 : mem_out_dec = 6'b111111; 12'd3556 : mem_out_dec = 6'b111111; 12'd3557 : mem_out_dec = 6'b111111; 12'd3558 : mem_out_dec = 6'b111111; 12'd3559 : mem_out_dec = 6'b111111; 12'd3560 : mem_out_dec = 6'b111111; 12'd3561 : mem_out_dec = 6'b111111; 12'd3562 : mem_out_dec = 6'b111111; 12'd3563 : mem_out_dec = 6'b111111; 12'd3564 : mem_out_dec = 6'b111111; 12'd3565 : mem_out_dec = 6'b111111; 12'd3566 : mem_out_dec = 6'b111111; 12'd3567 : mem_out_dec = 6'b111111; 12'd3568 : mem_out_dec = 6'b111111; 12'd3569 : mem_out_dec = 6'b111111; 12'd3570 : mem_out_dec = 6'b111111; 12'd3571 : mem_out_dec = 6'b111111; 12'd3572 : mem_out_dec = 6'b111111; 12'd3573 : mem_out_dec = 6'b111111; 12'd3574 : mem_out_dec = 6'b111111; 12'd3575 : mem_out_dec = 6'b111111; 12'd3576 : mem_out_dec = 6'b111111; 12'd3577 : mem_out_dec = 6'b111111; 12'd3578 : mem_out_dec = 6'b111111; 12'd3579 : mem_out_dec = 6'b111111; 12'd3580 : mem_out_dec = 6'b111111; 12'd3581 : mem_out_dec = 6'b000101; 12'd3582 : mem_out_dec = 6'b000110; 12'd3583 : mem_out_dec = 6'b000110; 12'd3584 : mem_out_dec = 6'b111111; 12'd3585 : mem_out_dec = 6'b111111; 12'd3586 : mem_out_dec = 6'b111111; 12'd3587 : mem_out_dec = 6'b111111; 12'd3588 : mem_out_dec = 6'b111111; 12'd3589 : mem_out_dec = 6'b111111; 12'd3590 : mem_out_dec = 6'b111111; 12'd3591 : mem_out_dec = 6'b111111; 12'd3592 : mem_out_dec = 6'b111111; 12'd3593 : mem_out_dec = 6'b111111; 12'd3594 : mem_out_dec = 6'b111111; 12'd3595 : mem_out_dec = 6'b111111; 12'd3596 : mem_out_dec = 6'b111111; 12'd3597 : mem_out_dec = 6'b111111; 12'd3598 : mem_out_dec = 6'b111111; 12'd3599 : mem_out_dec = 6'b111111; 12'd3600 : mem_out_dec = 6'b111111; 12'd3601 : mem_out_dec = 6'b111111; 12'd3602 : mem_out_dec = 6'b111111; 12'd3603 : mem_out_dec = 6'b111111; 12'd3604 : mem_out_dec = 6'b111111; 12'd3605 : mem_out_dec = 6'b111111; 12'd3606 : mem_out_dec = 6'b111111; 12'd3607 : mem_out_dec = 6'b111111; 12'd3608 : mem_out_dec = 6'b111111; 12'd3609 : mem_out_dec = 6'b111111; 12'd3610 : mem_out_dec = 6'b111111; 12'd3611 : mem_out_dec = 6'b111111; 12'd3612 : mem_out_dec = 6'b111111; 12'd3613 : mem_out_dec = 6'b111111; 12'd3614 : mem_out_dec = 6'b111111; 12'd3615 : mem_out_dec = 6'b111111; 12'd3616 : mem_out_dec = 6'b111111; 12'd3617 : mem_out_dec = 6'b111111; 12'd3618 : mem_out_dec = 6'b111111; 12'd3619 : mem_out_dec = 6'b111111; 12'd3620 : mem_out_dec = 6'b111111; 12'd3621 : mem_out_dec = 6'b111111; 12'd3622 : mem_out_dec = 6'b111111; 12'd3623 : mem_out_dec = 6'b111111; 12'd3624 : mem_out_dec = 6'b111111; 12'd3625 : mem_out_dec = 6'b111111; 12'd3626 : mem_out_dec = 6'b111111; 12'd3627 : mem_out_dec = 6'b111111; 12'd3628 : mem_out_dec = 6'b111111; 12'd3629 : mem_out_dec = 6'b111111; 12'd3630 : mem_out_dec = 6'b111111; 12'd3631 : mem_out_dec = 6'b111111; 12'd3632 : mem_out_dec = 6'b111111; 12'd3633 : mem_out_dec = 6'b111111; 12'd3634 : mem_out_dec = 6'b111111; 12'd3635 : mem_out_dec = 6'b111111; 12'd3636 : mem_out_dec = 6'b111111; 12'd3637 : mem_out_dec = 6'b111111; 12'd3638 : mem_out_dec = 6'b111111; 12'd3639 : mem_out_dec = 6'b111111; 12'd3640 : mem_out_dec = 6'b111111; 12'd3641 : mem_out_dec = 6'b111111; 12'd3642 : mem_out_dec = 6'b111111; 12'd3643 : mem_out_dec = 6'b111111; 12'd3644 : mem_out_dec = 6'b111111; 12'd3645 : mem_out_dec = 6'b111111; 12'd3646 : mem_out_dec = 6'b000100; 12'd3647 : mem_out_dec = 6'b000101; 12'd3648 : mem_out_dec = 6'b111111; 12'd3649 : mem_out_dec = 6'b111111; 12'd3650 : mem_out_dec = 6'b111111; 12'd3651 : mem_out_dec = 6'b111111; 12'd3652 : mem_out_dec = 6'b111111; 12'd3653 : mem_out_dec = 6'b111111; 12'd3654 : mem_out_dec = 6'b111111; 12'd3655 : mem_out_dec = 6'b111111; 12'd3656 : mem_out_dec = 6'b111111; 12'd3657 : mem_out_dec = 6'b111111; 12'd3658 : mem_out_dec = 6'b111111; 12'd3659 : mem_out_dec = 6'b111111; 12'd3660 : mem_out_dec = 6'b111111; 12'd3661 : mem_out_dec = 6'b111111; 12'd3662 : mem_out_dec = 6'b111111; 12'd3663 : mem_out_dec = 6'b111111; 12'd3664 : mem_out_dec = 6'b111111; 12'd3665 : mem_out_dec = 6'b111111; 12'd3666 : mem_out_dec = 6'b111111; 12'd3667 : mem_out_dec = 6'b111111; 12'd3668 : mem_out_dec = 6'b111111; 12'd3669 : mem_out_dec = 6'b111111; 12'd3670 : mem_out_dec = 6'b111111; 12'd3671 : mem_out_dec = 6'b111111; 12'd3672 : mem_out_dec = 6'b111111; 12'd3673 : mem_out_dec = 6'b111111; 12'd3674 : mem_out_dec = 6'b111111; 12'd3675 : mem_out_dec = 6'b111111; 12'd3676 : mem_out_dec = 6'b111111; 12'd3677 : mem_out_dec = 6'b111111; 12'd3678 : mem_out_dec = 6'b111111; 12'd3679 : mem_out_dec = 6'b111111; 12'd3680 : mem_out_dec = 6'b111111; 12'd3681 : mem_out_dec = 6'b111111; 12'd3682 : mem_out_dec = 6'b111111; 12'd3683 : mem_out_dec = 6'b111111; 12'd3684 : mem_out_dec = 6'b111111; 12'd3685 : mem_out_dec = 6'b111111; 12'd3686 : mem_out_dec = 6'b111111; 12'd3687 : mem_out_dec = 6'b111111; 12'd3688 : mem_out_dec = 6'b111111; 12'd3689 : mem_out_dec = 6'b111111; 12'd3690 : mem_out_dec = 6'b111111; 12'd3691 : mem_out_dec = 6'b111111; 12'd3692 : mem_out_dec = 6'b111111; 12'd3693 : mem_out_dec = 6'b111111; 12'd3694 : mem_out_dec = 6'b111111; 12'd3695 : mem_out_dec = 6'b111111; 12'd3696 : mem_out_dec = 6'b111111; 12'd3697 : mem_out_dec = 6'b111111; 12'd3698 : mem_out_dec = 6'b111111; 12'd3699 : mem_out_dec = 6'b111111; 12'd3700 : mem_out_dec = 6'b111111; 12'd3701 : mem_out_dec = 6'b111111; 12'd3702 : mem_out_dec = 6'b111111; 12'd3703 : mem_out_dec = 6'b111111; 12'd3704 : mem_out_dec = 6'b111111; 12'd3705 : mem_out_dec = 6'b111111; 12'd3706 : mem_out_dec = 6'b111111; 12'd3707 : mem_out_dec = 6'b111111; 12'd3708 : mem_out_dec = 6'b111111; 12'd3709 : mem_out_dec = 6'b111111; 12'd3710 : mem_out_dec = 6'b111111; 12'd3711 : mem_out_dec = 6'b000100; 12'd3712 : mem_out_dec = 6'b111111; 12'd3713 : mem_out_dec = 6'b111111; 12'd3714 : mem_out_dec = 6'b111111; 12'd3715 : mem_out_dec = 6'b111111; 12'd3716 : mem_out_dec = 6'b111111; 12'd3717 : mem_out_dec = 6'b111111; 12'd3718 : mem_out_dec = 6'b111111; 12'd3719 : mem_out_dec = 6'b111111; 12'd3720 : mem_out_dec = 6'b111111; 12'd3721 : mem_out_dec = 6'b111111; 12'd3722 : mem_out_dec = 6'b111111; 12'd3723 : mem_out_dec = 6'b111111; 12'd3724 : mem_out_dec = 6'b111111; 12'd3725 : mem_out_dec = 6'b111111; 12'd3726 : mem_out_dec = 6'b111111; 12'd3727 : mem_out_dec = 6'b111111; 12'd3728 : mem_out_dec = 6'b111111; 12'd3729 : mem_out_dec = 6'b111111; 12'd3730 : mem_out_dec = 6'b111111; 12'd3731 : mem_out_dec = 6'b111111; 12'd3732 : mem_out_dec = 6'b111111; 12'd3733 : mem_out_dec = 6'b111111; 12'd3734 : mem_out_dec = 6'b111111; 12'd3735 : mem_out_dec = 6'b111111; 12'd3736 : mem_out_dec = 6'b111111; 12'd3737 : mem_out_dec = 6'b111111; 12'd3738 : mem_out_dec = 6'b111111; 12'd3739 : mem_out_dec = 6'b111111; 12'd3740 : mem_out_dec = 6'b111111; 12'd3741 : mem_out_dec = 6'b111111; 12'd3742 : mem_out_dec = 6'b111111; 12'd3743 : mem_out_dec = 6'b111111; 12'd3744 : mem_out_dec = 6'b111111; 12'd3745 : mem_out_dec = 6'b111111; 12'd3746 : mem_out_dec = 6'b111111; 12'd3747 : mem_out_dec = 6'b111111; 12'd3748 : mem_out_dec = 6'b111111; 12'd3749 : mem_out_dec = 6'b111111; 12'd3750 : mem_out_dec = 6'b111111; 12'd3751 : mem_out_dec = 6'b111111; 12'd3752 : mem_out_dec = 6'b111111; 12'd3753 : mem_out_dec = 6'b111111; 12'd3754 : mem_out_dec = 6'b111111; 12'd3755 : mem_out_dec = 6'b111111; 12'd3756 : mem_out_dec = 6'b111111; 12'd3757 : mem_out_dec = 6'b111111; 12'd3758 : mem_out_dec = 6'b111111; 12'd3759 : mem_out_dec = 6'b111111; 12'd3760 : mem_out_dec = 6'b111111; 12'd3761 : mem_out_dec = 6'b111111; 12'd3762 : mem_out_dec = 6'b111111; 12'd3763 : mem_out_dec = 6'b111111; 12'd3764 : mem_out_dec = 6'b111111; 12'd3765 : mem_out_dec = 6'b111111; 12'd3766 : mem_out_dec = 6'b111111; 12'd3767 : mem_out_dec = 6'b111111; 12'd3768 : mem_out_dec = 6'b111111; 12'd3769 : mem_out_dec = 6'b111111; 12'd3770 : mem_out_dec = 6'b111111; 12'd3771 : mem_out_dec = 6'b111111; 12'd3772 : mem_out_dec = 6'b111111; 12'd3773 : mem_out_dec = 6'b111111; 12'd3774 : mem_out_dec = 6'b111111; 12'd3775 : mem_out_dec = 6'b111111; 12'd3776 : mem_out_dec = 6'b111111; 12'd3777 : mem_out_dec = 6'b111111; 12'd3778 : mem_out_dec = 6'b111111; 12'd3779 : mem_out_dec = 6'b111111; 12'd3780 : mem_out_dec = 6'b111111; 12'd3781 : mem_out_dec = 6'b111111; 12'd3782 : mem_out_dec = 6'b111111; 12'd3783 : mem_out_dec = 6'b111111; 12'd3784 : mem_out_dec = 6'b111111; 12'd3785 : mem_out_dec = 6'b111111; 12'd3786 : mem_out_dec = 6'b111111; 12'd3787 : mem_out_dec = 6'b111111; 12'd3788 : mem_out_dec = 6'b111111; 12'd3789 : mem_out_dec = 6'b111111; 12'd3790 : mem_out_dec = 6'b111111; 12'd3791 : mem_out_dec = 6'b111111; 12'd3792 : mem_out_dec = 6'b111111; 12'd3793 : mem_out_dec = 6'b111111; 12'd3794 : mem_out_dec = 6'b111111; 12'd3795 : mem_out_dec = 6'b111111; 12'd3796 : mem_out_dec = 6'b111111; 12'd3797 : mem_out_dec = 6'b111111; 12'd3798 : mem_out_dec = 6'b111111; 12'd3799 : mem_out_dec = 6'b111111; 12'd3800 : mem_out_dec = 6'b111111; 12'd3801 : mem_out_dec = 6'b111111; 12'd3802 : mem_out_dec = 6'b111111; 12'd3803 : mem_out_dec = 6'b111111; 12'd3804 : mem_out_dec = 6'b111111; 12'd3805 : mem_out_dec = 6'b111111; 12'd3806 : mem_out_dec = 6'b111111; 12'd3807 : mem_out_dec = 6'b111111; 12'd3808 : mem_out_dec = 6'b111111; 12'd3809 : mem_out_dec = 6'b111111; 12'd3810 : mem_out_dec = 6'b111111; 12'd3811 : mem_out_dec = 6'b111111; 12'd3812 : mem_out_dec = 6'b111111; 12'd3813 : mem_out_dec = 6'b111111; 12'd3814 : mem_out_dec = 6'b111111; 12'd3815 : mem_out_dec = 6'b111111; 12'd3816 : mem_out_dec = 6'b111111; 12'd3817 : mem_out_dec = 6'b111111; 12'd3818 : mem_out_dec = 6'b111111; 12'd3819 : mem_out_dec = 6'b111111; 12'd3820 : mem_out_dec = 6'b111111; 12'd3821 : mem_out_dec = 6'b111111; 12'd3822 : mem_out_dec = 6'b111111; 12'd3823 : mem_out_dec = 6'b111111; 12'd3824 : mem_out_dec = 6'b111111; 12'd3825 : mem_out_dec = 6'b111111; 12'd3826 : mem_out_dec = 6'b111111; 12'd3827 : mem_out_dec = 6'b111111; 12'd3828 : mem_out_dec = 6'b111111; 12'd3829 : mem_out_dec = 6'b111111; 12'd3830 : mem_out_dec = 6'b111111; 12'd3831 : mem_out_dec = 6'b111111; 12'd3832 : mem_out_dec = 6'b111111; 12'd3833 : mem_out_dec = 6'b111111; 12'd3834 : mem_out_dec = 6'b111111; 12'd3835 : mem_out_dec = 6'b111111; 12'd3836 : mem_out_dec = 6'b111111; 12'd3837 : mem_out_dec = 6'b111111; 12'd3838 : mem_out_dec = 6'b111111; 12'd3839 : mem_out_dec = 6'b111111; 12'd3840 : mem_out_dec = 6'b111111; 12'd3841 : mem_out_dec = 6'b111111; 12'd3842 : mem_out_dec = 6'b111111; 12'd3843 : mem_out_dec = 6'b111111; 12'd3844 : mem_out_dec = 6'b111111; 12'd3845 : mem_out_dec = 6'b111111; 12'd3846 : mem_out_dec = 6'b111111; 12'd3847 : mem_out_dec = 6'b111111; 12'd3848 : mem_out_dec = 6'b111111; 12'd3849 : mem_out_dec = 6'b111111; 12'd3850 : mem_out_dec = 6'b111111; 12'd3851 : mem_out_dec = 6'b111111; 12'd3852 : mem_out_dec = 6'b111111; 12'd3853 : mem_out_dec = 6'b111111; 12'd3854 : mem_out_dec = 6'b111111; 12'd3855 : mem_out_dec = 6'b111111; 12'd3856 : mem_out_dec = 6'b111111; 12'd3857 : mem_out_dec = 6'b111111; 12'd3858 : mem_out_dec = 6'b111111; 12'd3859 : mem_out_dec = 6'b111111; 12'd3860 : mem_out_dec = 6'b111111; 12'd3861 : mem_out_dec = 6'b111111; 12'd3862 : mem_out_dec = 6'b111111; 12'd3863 : mem_out_dec = 6'b111111; 12'd3864 : mem_out_dec = 6'b111111; 12'd3865 : mem_out_dec = 6'b111111; 12'd3866 : mem_out_dec = 6'b111111; 12'd3867 : mem_out_dec = 6'b111111; 12'd3868 : mem_out_dec = 6'b111111; 12'd3869 : mem_out_dec = 6'b111111; 12'd3870 : mem_out_dec = 6'b111111; 12'd3871 : mem_out_dec = 6'b111111; 12'd3872 : mem_out_dec = 6'b111111; 12'd3873 : mem_out_dec = 6'b111111; 12'd3874 : mem_out_dec = 6'b111111; 12'd3875 : mem_out_dec = 6'b111111; 12'd3876 : mem_out_dec = 6'b111111; 12'd3877 : mem_out_dec = 6'b111111; 12'd3878 : mem_out_dec = 6'b111111; 12'd3879 : mem_out_dec = 6'b111111; 12'd3880 : mem_out_dec = 6'b111111; 12'd3881 : mem_out_dec = 6'b111111; 12'd3882 : mem_out_dec = 6'b111111; 12'd3883 : mem_out_dec = 6'b111111; 12'd3884 : mem_out_dec = 6'b111111; 12'd3885 : mem_out_dec = 6'b111111; 12'd3886 : mem_out_dec = 6'b111111; 12'd3887 : mem_out_dec = 6'b111111; 12'd3888 : mem_out_dec = 6'b111111; 12'd3889 : mem_out_dec = 6'b111111; 12'd3890 : mem_out_dec = 6'b111111; 12'd3891 : mem_out_dec = 6'b111111; 12'd3892 : mem_out_dec = 6'b111111; 12'd3893 : mem_out_dec = 6'b111111; 12'd3894 : mem_out_dec = 6'b111111; 12'd3895 : mem_out_dec = 6'b111111; 12'd3896 : mem_out_dec = 6'b111111; 12'd3897 : mem_out_dec = 6'b111111; 12'd3898 : mem_out_dec = 6'b111111; 12'd3899 : mem_out_dec = 6'b111111; 12'd3900 : mem_out_dec = 6'b111111; 12'd3901 : mem_out_dec = 6'b111111; 12'd3902 : mem_out_dec = 6'b111111; 12'd3903 : mem_out_dec = 6'b111111; 12'd3904 : mem_out_dec = 6'b111111; 12'd3905 : mem_out_dec = 6'b111111; 12'd3906 : mem_out_dec = 6'b111111; 12'd3907 : mem_out_dec = 6'b111111; 12'd3908 : mem_out_dec = 6'b111111; 12'd3909 : mem_out_dec = 6'b111111; 12'd3910 : mem_out_dec = 6'b111111; 12'd3911 : mem_out_dec = 6'b111111; 12'd3912 : mem_out_dec = 6'b111111; 12'd3913 : mem_out_dec = 6'b111111; 12'd3914 : mem_out_dec = 6'b111111; 12'd3915 : mem_out_dec = 6'b111111; 12'd3916 : mem_out_dec = 6'b111111; 12'd3917 : mem_out_dec = 6'b111111; 12'd3918 : mem_out_dec = 6'b111111; 12'd3919 : mem_out_dec = 6'b111111; 12'd3920 : mem_out_dec = 6'b111111; 12'd3921 : mem_out_dec = 6'b111111; 12'd3922 : mem_out_dec = 6'b111111; 12'd3923 : mem_out_dec = 6'b111111; 12'd3924 : mem_out_dec = 6'b111111; 12'd3925 : mem_out_dec = 6'b111111; 12'd3926 : mem_out_dec = 6'b111111; 12'd3927 : mem_out_dec = 6'b111111; 12'd3928 : mem_out_dec = 6'b111111; 12'd3929 : mem_out_dec = 6'b111111; 12'd3930 : mem_out_dec = 6'b111111; 12'd3931 : mem_out_dec = 6'b111111; 12'd3932 : mem_out_dec = 6'b111111; 12'd3933 : mem_out_dec = 6'b111111; 12'd3934 : mem_out_dec = 6'b111111; 12'd3935 : mem_out_dec = 6'b111111; 12'd3936 : mem_out_dec = 6'b111111; 12'd3937 : mem_out_dec = 6'b111111; 12'd3938 : mem_out_dec = 6'b111111; 12'd3939 : mem_out_dec = 6'b111111; 12'd3940 : mem_out_dec = 6'b111111; 12'd3941 : mem_out_dec = 6'b111111; 12'd3942 : mem_out_dec = 6'b111111; 12'd3943 : mem_out_dec = 6'b111111; 12'd3944 : mem_out_dec = 6'b111111; 12'd3945 : mem_out_dec = 6'b111111; 12'd3946 : mem_out_dec = 6'b111111; 12'd3947 : mem_out_dec = 6'b111111; 12'd3948 : mem_out_dec = 6'b111111; 12'd3949 : mem_out_dec = 6'b111111; 12'd3950 : mem_out_dec = 6'b111111; 12'd3951 : mem_out_dec = 6'b111111; 12'd3952 : mem_out_dec = 6'b111111; 12'd3953 : mem_out_dec = 6'b111111; 12'd3954 : mem_out_dec = 6'b111111; 12'd3955 : mem_out_dec = 6'b111111; 12'd3956 : mem_out_dec = 6'b111111; 12'd3957 : mem_out_dec = 6'b111111; 12'd3958 : mem_out_dec = 6'b111111; 12'd3959 : mem_out_dec = 6'b111111; 12'd3960 : mem_out_dec = 6'b111111; 12'd3961 : mem_out_dec = 6'b111111; 12'd3962 : mem_out_dec = 6'b111111; 12'd3963 : mem_out_dec = 6'b111111; 12'd3964 : mem_out_dec = 6'b111111; 12'd3965 : mem_out_dec = 6'b111111; 12'd3966 : mem_out_dec = 6'b111111; 12'd3967 : mem_out_dec = 6'b111111; 12'd3968 : mem_out_dec = 6'b111111; 12'd3969 : mem_out_dec = 6'b111111; 12'd3970 : mem_out_dec = 6'b111111; 12'd3971 : mem_out_dec = 6'b111111; 12'd3972 : mem_out_dec = 6'b111111; 12'd3973 : mem_out_dec = 6'b111111; 12'd3974 : mem_out_dec = 6'b111111; 12'd3975 : mem_out_dec = 6'b111111; 12'd3976 : mem_out_dec = 6'b111111; 12'd3977 : mem_out_dec = 6'b111111; 12'd3978 : mem_out_dec = 6'b111111; 12'd3979 : mem_out_dec = 6'b111111; 12'd3980 : mem_out_dec = 6'b111111; 12'd3981 : mem_out_dec = 6'b111111; 12'd3982 : mem_out_dec = 6'b111111; 12'd3983 : mem_out_dec = 6'b111111; 12'd3984 : mem_out_dec = 6'b111111; 12'd3985 : mem_out_dec = 6'b111111; 12'd3986 : mem_out_dec = 6'b111111; 12'd3987 : mem_out_dec = 6'b111111; 12'd3988 : mem_out_dec = 6'b111111; 12'd3989 : mem_out_dec = 6'b111111; 12'd3990 : mem_out_dec = 6'b111111; 12'd3991 : mem_out_dec = 6'b111111; 12'd3992 : mem_out_dec = 6'b111111; 12'd3993 : mem_out_dec = 6'b111111; 12'd3994 : mem_out_dec = 6'b111111; 12'd3995 : mem_out_dec = 6'b111111; 12'd3996 : mem_out_dec = 6'b111111; 12'd3997 : mem_out_dec = 6'b111111; 12'd3998 : mem_out_dec = 6'b111111; 12'd3999 : mem_out_dec = 6'b111111; 12'd4000 : mem_out_dec = 6'b111111; 12'd4001 : mem_out_dec = 6'b111111; 12'd4002 : mem_out_dec = 6'b111111; 12'd4003 : mem_out_dec = 6'b111111; 12'd4004 : mem_out_dec = 6'b111111; 12'd4005 : mem_out_dec = 6'b111111; 12'd4006 : mem_out_dec = 6'b111111; 12'd4007 : mem_out_dec = 6'b111111; 12'd4008 : mem_out_dec = 6'b111111; 12'd4009 : mem_out_dec = 6'b111111; 12'd4010 : mem_out_dec = 6'b111111; 12'd4011 : mem_out_dec = 6'b111111; 12'd4012 : mem_out_dec = 6'b111111; 12'd4013 : mem_out_dec = 6'b111111; 12'd4014 : mem_out_dec = 6'b111111; 12'd4015 : mem_out_dec = 6'b111111; 12'd4016 : mem_out_dec = 6'b111111; 12'd4017 : mem_out_dec = 6'b111111; 12'd4018 : mem_out_dec = 6'b111111; 12'd4019 : mem_out_dec = 6'b111111; 12'd4020 : mem_out_dec = 6'b111111; 12'd4021 : mem_out_dec = 6'b111111; 12'd4022 : mem_out_dec = 6'b111111; 12'd4023 : mem_out_dec = 6'b111111; 12'd4024 : mem_out_dec = 6'b111111; 12'd4025 : mem_out_dec = 6'b111111; 12'd4026 : mem_out_dec = 6'b111111; 12'd4027 : mem_out_dec = 6'b111111; 12'd4028 : mem_out_dec = 6'b111111; 12'd4029 : mem_out_dec = 6'b111111; 12'd4030 : mem_out_dec = 6'b111111; 12'd4031 : mem_out_dec = 6'b111111; 12'd4032 : mem_out_dec = 6'b111111; 12'd4033 : mem_out_dec = 6'b111111; 12'd4034 : mem_out_dec = 6'b111111; 12'd4035 : mem_out_dec = 6'b111111; 12'd4036 : mem_out_dec = 6'b111111; 12'd4037 : mem_out_dec = 6'b111111; 12'd4038 : mem_out_dec = 6'b111111; 12'd4039 : mem_out_dec = 6'b111111; 12'd4040 : mem_out_dec = 6'b111111; 12'd4041 : mem_out_dec = 6'b111111; 12'd4042 : mem_out_dec = 6'b111111; 12'd4043 : mem_out_dec = 6'b111111; 12'd4044 : mem_out_dec = 6'b111111; 12'd4045 : mem_out_dec = 6'b111111; 12'd4046 : mem_out_dec = 6'b111111; 12'd4047 : mem_out_dec = 6'b111111; 12'd4048 : mem_out_dec = 6'b111111; 12'd4049 : mem_out_dec = 6'b111111; 12'd4050 : mem_out_dec = 6'b111111; 12'd4051 : mem_out_dec = 6'b111111; 12'd4052 : mem_out_dec = 6'b111111; 12'd4053 : mem_out_dec = 6'b111111; 12'd4054 : mem_out_dec = 6'b111111; 12'd4055 : mem_out_dec = 6'b111111; 12'd4056 : mem_out_dec = 6'b111111; 12'd4057 : mem_out_dec = 6'b111111; 12'd4058 : mem_out_dec = 6'b111111; 12'd4059 : mem_out_dec = 6'b111111; 12'd4060 : mem_out_dec = 6'b111111; 12'd4061 : mem_out_dec = 6'b111111; 12'd4062 : mem_out_dec = 6'b111111; 12'd4063 : mem_out_dec = 6'b111111; 12'd4064 : mem_out_dec = 6'b111111; 12'd4065 : mem_out_dec = 6'b111111; 12'd4066 : mem_out_dec = 6'b111111; 12'd4067 : mem_out_dec = 6'b111111; 12'd4068 : mem_out_dec = 6'b111111; 12'd4069 : mem_out_dec = 6'b111111; 12'd4070 : mem_out_dec = 6'b111111; 12'd4071 : mem_out_dec = 6'b111111; 12'd4072 : mem_out_dec = 6'b111111; 12'd4073 : mem_out_dec = 6'b111111; 12'd4074 : mem_out_dec = 6'b111111; 12'd4075 : mem_out_dec = 6'b111111; 12'd4076 : mem_out_dec = 6'b111111; 12'd4077 : mem_out_dec = 6'b111111; 12'd4078 : mem_out_dec = 6'b111111; 12'd4079 : mem_out_dec = 6'b111111; 12'd4080 : mem_out_dec = 6'b111111; 12'd4081 : mem_out_dec = 6'b111111; 12'd4082 : mem_out_dec = 6'b111111; 12'd4083 : mem_out_dec = 6'b111111; 12'd4084 : mem_out_dec = 6'b111111; 12'd4085 : mem_out_dec = 6'b111111; 12'd4086 : mem_out_dec = 6'b111111; 12'd4087 : mem_out_dec = 6'b111111; 12'd4088 : mem_out_dec = 6'b111111; 12'd4089 : mem_out_dec = 6'b111111; 12'd4090 : mem_out_dec = 6'b111111; 12'd4091 : mem_out_dec = 6'b111111; 12'd4092 : mem_out_dec = 6'b111111; 12'd4093 : mem_out_dec = 6'b111111; 12'd4094 : mem_out_dec = 6'b111111; 12'd4095 : mem_out_dec = 6'b111111; endcase end always @ (posedge clk) begin dec_cnt <= #TCQ mem_out_dec; end endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling Stage1 calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps (* use_dsp48 = "no" *) module mig_7series_v4_0_ddr_phy_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter DEBUG_PORT = "OFF", // Enable debug port parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter OCAL_EN = "ON", parameter IDELAY_ADJ = "ON", parameter PI_DIV2_INCDEC = "TRUE" ) ( input clk, input rst, // Calibration status, control signals input mpr_rdlvl_start, output mpr_rdlvl_done, output reg mpr_last_byte_done, output mpr_rnk_done, input rdlvl_stg1_start, output rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, output rdlvl_stg1_rnk_done, output reg rdlvl_stg1_err, output mpr_rdlvl_err, output rdlvl_err, output reg rdlvl_prech_req, output rdlvl_last_byte_done, output reg rdlvl_assrt_common, input prech_done, input phy_if_empty, input [4:0] idelaye2_init_val, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Decrement initial Phaser_IN Fine tap delay input dqs_po_dec_done, input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_fine_dly_dec_done, output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output reg pi_stg2_load, output reg [5:0] pi_stg2_reg_l, output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, // To DQ IDELAY required to find left edge of // valid window output idelay_ce, output idelay_inc, input idelay_ld, input [DQS_CNT_WIDTH:0] wrcal_cnt, // Only output if Per-bit de-skew enabled output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, //output to prevent read during PI movement output reg rdlvl_pi_incdec, // Debug Port output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl ); // minimum time (in IDELAY taps) for which capture data must be stable for // algorithm to consider a valid data eye to be found. The read leveling // logic will ignore any window found smaller than this value. Limitations // on how small this number can be is determined by: (1) the algorithmic // limitation of how many taps wide the data eye can be (3 taps), and (2) // how wide regions of "instability" that occur around the edges of the // read valid window can be (i.e. need to be able to filter out "false" // windows that occur for a short # of taps around the edges of the true // data window, although with multi-sampling during read leveling, this is // not as much a concern) - the larger the value, the more protection // against "false" windows localparam MIN_EYE_SIZE = 16; // Length of calibration sequence (in # of words) localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); // # of cycles required to perform read data shift register compare // This is defined as from the cycle the new data is loaded until // signal found_edge_r is valid localparam RD_SHIFT_COMP_DELAY = 5; // worst-case # of cycles to wait to ensure that both the SR and // PREV_SR shift registers have valid data, and that the comparison // of the two shift register values is valid. The "+1" at the end of // this equation is a fudge factor, I freely admit that localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; // # of clock cycles to wait after changing tap value or read data MUX // to allow: (1) tap chain to settle, (2) for delayed input to propagate // thru ISERDES, (3) for the read data comparison logic to have time to // output the comparison of two consecutive samples of the settled read data // The minimum delay is 16 cycles, which should be good enough to handle all // three of the above conditions for the simulation-only case with a short // training pattern. For H/W (or for simulation with longer training // pattern), it will take longer to store and compare two consecutive // samples, and the value of this parameter will reflect that // put the maximum number for 2:1 mode localparam PIPE_WAIT_CNT = (nCK_PER_CLK == 2) ? 31 : (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8); // # of read data samples to examine when detecting whether an edge has // occured during stage 1 calibration. Width of local param must be // changed as appropriate. Note that there are two counters used, each // counter can be changed independently of the other - they are used in // cascade to create a larger counter localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 localparam [5:0] CAL1_IDLE = 6'h00; localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; localparam [5:0] CAL1_PAT_DETECT = 6'h03; localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; localparam [5:0] CAL1_DETECT_EDGE = 6'h08; localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; localparam [5:0] CAL1_CALC_IDEL = 6'h0B; localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; localparam [5:0] CAL1_NEXT_DQS = 6'h0E; localparam [5:0] CAL1_DONE = 6'h0F; localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; localparam [5:0] CAL1_PB_INC_CPT = 6'h12; localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; localparam [5:0] CAL1_PB_INC_DQ = 6'h17; localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; localparam [5:0] CAL1_REGL_LOAD = 6'h1B; localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; localparam [5:0] CAL1_VALID_WAIT = 6'h1E; localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; localparam [5:0] CAL1_RD_STOP_FOR_PI_INC = 6'h21; localparam [5:0] CAL1_CENTER_WAIT = 6'h22; integer a; integer b; integer d; integer e; integer f; integer h; integer g; integer i; integer j; integer k; integer l; integer m; integer n; integer r; integer p; integer q; integer s; integer t; integer u; integer w; integer ce_i; integer ce_rnk_i; integer aa; integer bb; integer cc; integer dd; genvar x; genvar z; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; reg cal1_dq_idel_ce; reg cal1_dq_idel_inc; reg cal1_dlyce_cpt_r; reg cal1_dlyinc_cpt_r; reg cal1_dlyce_dq_r; reg cal1_dlyinc_dq_r; reg cal1_wait_cnt_en_r; reg [4:0] cal1_wait_cnt_r; reg cal1_wait_r; reg [DQ_WIDTH-1:0] dlyce_dq_r; reg dlyinc_dq_r; reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; reg cal1_prech_req_r; reg [5:0] cal1_state_r; reg [5:0] cal1_state_r1; reg [5:0] cal1_state_r2; reg [5:0] cal1_state_r3; reg [5:0] cnt_idel_dec_cpt_r; reg [3:0] cnt_shift_r; reg detect_edge_done_r; reg [5:0] right_edge_taps_r; reg [5:0] first_edge_taps_r; reg found_edge_r; reg found_first_edge_r; reg found_second_edge_r; reg found_stable_eye_r; reg found_stable_eye_last_r; reg found_edge_all_r; reg [5:0] tap_cnt_cpt_r; reg tap_limit_cpt_r; reg [4:0] idel_tap_cnt_dq_pb_r; reg idel_tap_limit_dq_pb_r; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg mux_rd_valid_r; reg new_cnt_cpt_r; reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; reg [DRAM_WIDTH-1:0] pb_found_edge_r; reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; reg pi_stg2_load_timing; reg [5:0] pi_stg2_reg_l_timing; reg [DRAM_WIDTH-1:0] prev_sr_diff_r; reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg samp_cnt_done_r; reg samp_edge_cnt0_en_r; reg [11:0] samp_edge_cnt0_r; reg samp_edge_cnt1_en_r; reg [11:0] samp_edge_cnt1_r; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] second_edge_taps_r; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg store_sr_r; reg store_sr_req_pulsed_r; reg store_sr_req_r; reg sr_valid_r; reg sr_valid_r1; reg sr_valid_r2; reg [DRAM_WIDTH-1:0] old_sr_diff_r; reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; reg pat0_data_match_r; reg pat1_data_match_r; wire pat_data_match_r; wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; reg pat0_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; reg pat0_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; reg pat0_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; reg pat0_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; reg pat0_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; reg pat0_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; reg pat0_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; reg pat0_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg pat1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg pat1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; reg pat1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; reg pat1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg pat1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg pat1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; reg pat1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; reg pat1_match_rise3_and_r; reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; reg [4:0] idelay_tap_cnt_slice_r; reg idelay_tap_limit_r; wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; reg idel_pat0_match_rise0_and_r; reg idel_pat0_match_fall0_and_r; reg idel_pat0_match_rise1_and_r; reg idel_pat0_match_fall1_and_r; reg idel_pat0_match_rise2_and_r; reg idel_pat0_match_fall2_and_r; reg idel_pat0_match_rise3_and_r; reg idel_pat0_match_fall3_and_r; reg idel_pat1_match_rise0_and_r; reg idel_pat1_match_fall0_and_r; reg idel_pat1_match_rise1_and_r; reg idel_pat1_match_fall1_and_r; reg idel_pat1_match_rise2_and_r; reg idel_pat1_match_fall2_and_r; reg idel_pat1_match_rise3_and_r; reg idel_pat1_match_fall3_and_r; reg idel_pat0_data_match_r; reg idel_pat1_data_match_r; reg idel_pat_data_match; reg idel_pat_data_match_r; reg [4:0] idel_dec_cnt; reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [1:0] rnk_cnt_r; reg rdlvl_rank_done_r; reg [3:0] done_cnt; reg [1:0] regl_rank_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; reg regl_rank_done_r; reg rdlvl_stg1_start_r; reg dqs_po_dec_done_r1; reg dqs_po_dec_done_r2; reg fine_dly_dec_done_r1; reg fine_dly_dec_done_r2; reg fine_dly_dec_done_r3; reg fine_dly_dec_done_r4; reg [3:0] wait_cnt_r; reg [5:0] pi_rdval_cnt; reg pi_cnt_dec; reg mpr_valid_r; reg mpr_valid_r1; reg mpr_valid_r2; reg mpr_rd_rise0_prev_r; reg mpr_rd_fall0_prev_r; reg mpr_rd_rise1_prev_r; reg mpr_rd_fall1_prev_r; reg mpr_rd_rise2_prev_r; reg mpr_rd_fall2_prev_r; reg mpr_rd_rise3_prev_r; reg mpr_rd_fall3_prev_r; reg mpr_rdlvl_done_r; reg mpr_rdlvl_done_r1; reg mpr_rdlvl_done_r2; reg mpr_rdlvl_start_r; reg mpr_rank_done_r; reg [2:0] stable_idel_cnt; reg inhibit_edge_detect_r; reg idel_pat_detect_valid_r; reg idel_mpr_pat_detect_r; reg mpr_pat_detect_r; reg mpr_dec_cpt_r; reg idel_adj_inc; //IDELAY adjustment wire [1:0] idelay_adj; wire pb_detect_edge_setup; wire pb_detect_edge; // Debug reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; reg rdlvl_stg1_done_int; reg rdlvl_stg1_done_int_r1, rdlvl_stg1_done_int_r2, rdlvl_stg1_done_int_r3; reg rdlvl_last_byte_done_int; reg rdlvl_last_byte_done_int_r1, rdlvl_last_byte_done_int_r2, rdlvl_last_byte_done_int_r3; //IDELAY adjustment setting for -1 //2'b10 : IDELAY - 1 //2'b01 : IDELAY + 1 //2'b00 : No IDELAY adjustment assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < RANKS; d = d + 1) begin for (e = 0; e < DQS_WIDTH; e = e + 1) begin idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; end end end assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; assign dbg_phy_rdlvl[1] = pat_data_match_r; assign dbg_phy_rdlvl[2] = mux_rd_valid_r; assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; assign dbg_phy_rdlvl[8:4] = 'b0; assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; assign dbg_phy_rdlvl[21] = found_first_edge_r; assign dbg_phy_rdlvl[22] = found_second_edge_r; assign dbg_phy_rdlvl[23] = found_edge_r; assign dbg_phy_rdlvl[24] = store_sr_r; // [40:25] previously used for sr, old_sr shift registers. If connecting // these signals again, don't forget to parameterize based on RD_SHIFT_LEN assign dbg_phy_rdlvl[40:25] = 'b0; assign dbg_phy_rdlvl[41] = sr_valid_r; assign dbg_phy_rdlvl[42] = found_stable_eye_r; assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; assign dbg_phy_rdlvl[67] = found_edge_r; assign dbg_phy_rdlvl[68] = found_first_edge_r; assign dbg_phy_rdlvl[73:69] = 'b0; assign dbg_phy_rdlvl[74] = idel_pat_data_match; assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; assign dbg_phy_rdlvl[77] = pat0_data_match_r; assign dbg_phy_rdlvl[78] = pat1_data_match_r; assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; //*************************************************************************** // Debug output //*************************************************************************** // CPT taps assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; // Record first and second edges found during CPT calibration generate always @(posedge clk) if (rst || (rdlvl_stg1_start && ~rdlvl_stg1_start_r)) begin dbg_cpt_first_edge_taps <= #TCQ 'b0; dbg_cpt_second_edge_taps <= #TCQ 'b0; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge if (found_first_edge_r) dbg_cpt_first_edge_taps[(6*ce_i)+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[(6*ce_i)+:6] <= #TCQ second_edge_taps_r; end //end end else if (cal1_state_r == CAL1_CALC_IDEL) begin // Record tap counts of first and second edge edges during // CPT calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (found_first_edge_r) dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ second_edge_taps_r; end endgenerate assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; assign mpr_rnk_done = mpr_rank_done_r; assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") mpr_rdlvl_done_r : 1'b1; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_rdlvl_cnt = (((PI_DIV2_INCDEC == "TRUE") && (cal1_state_r3 == CAL1_REGL_LOAD)) || ((PI_DIV2_INCDEC == "FALSE") && (cal1_state_r == CAL1_REGL_LOAD))) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; assign rdlvl_stg1_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_stg1_done_int_r3 : rdlvl_stg1_done_int; assign rdlvl_last_byte_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_last_byte_done_int_r3 : rdlvl_last_byte_done_int; always @ (posedge clk) begin rdlvl_stg1_done_int_r1 <= #TCQ rdlvl_stg1_done_int; rdlvl_stg1_done_int_r2 <= #TCQ rdlvl_stg1_done_int_r1; rdlvl_stg1_done_int_r3 <= #TCQ rdlvl_stg1_done_int_r2; rdlvl_last_byte_done_int_r1 <= #TCQ rdlvl_last_byte_done_int; rdlvl_last_byte_done_int_r2 <= #TCQ rdlvl_last_byte_done_int_r1; rdlvl_last_byte_done_int_r3 <= #TCQ rdlvl_last_byte_done_int_r2; end assign idelay_ce = cal1_dq_idel_ce; assign idelay_inc = cal1_dq_idel_inc; //*************************************************************************** // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all // DQs simultaneously //*************************************************************************** always @(posedge clk) begin if (rst) rdlvl_assrt_common <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & !rdlvl_stg1_start_r) rdlvl_assrt_common <= #TCQ 1'b1; else if (!idel_pat_data_match_r & idel_pat_data_match) rdlvl_assrt_common <= #TCQ 1'b0; end //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate //*************************************************************************** // MPR Read Leveling //*************************************************************************** // storing the previous read data for checking later. Only bit 0 is used // since MPR contents (01010101) are available generally on DQ[0] per // JEDEC spec. always @(posedge clk)begin if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; end end generate if (nCK_PER_CLK == 4) begin: mpr_4to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | //(cal1_state_r == CAL1_DETECT_EDGE) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b1; // Wait for settling time after idelay tap increment before // de-asserting inhibit_edge_detect_r else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 10101010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r))) //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 01010101 to 10101010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end else if (nCK_PER_CLK == 2) begin: mpr_2to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b1; else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 1010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 0101 to 1010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) mux_rd_valid_r <= #TCQ ~phy_if_empty; //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** always @(posedge clk) begin dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2; fine_dly_dec_done_r4 <= #TCQ fine_dly_dec_done_r3; if (PI_DIV2_INCDEC == "TRUE") pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r4; else pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; end always @(posedge clk) begin if (rst || pi_cnt_dec) wait_cnt_r <= #TCQ 'd8; else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst) begin pi_rdval_cnt <= #TCQ 'd0; end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin pi_rdval_cnt <= #TCQ pi_counter_read_val; end else if (pi_rdval_cnt > 'd0) begin if (pi_cnt_dec) pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; else pi_rdval_cnt <= #TCQ pi_rdval_cnt; end else if (pi_rdval_cnt == 'd0) begin pi_rdval_cnt <= #TCQ pi_rdval_cnt; end end always @(posedge clk) begin if (rst || (pi_rdval_cnt == 'd0)) pi_cnt_dec <= #TCQ 1'b0; else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) && (wait_cnt_r == 'd1)) pi_cnt_dec <= #TCQ 1'b1; else pi_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) begin fine_dly_dec_done_r1 <= #TCQ 1'b0; end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin fine_dly_dec_done_r1 <= #TCQ 1'b1; end end //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (pi_cnt_dec) begin pi_en_stg2_f_timing <= #TCQ 'b1; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (cal1_dlyce_cpt_r) begin if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end else if (SIM_CAL_OPTION == "FAST_CAL") begin // if simulating, and "shortcuts" for calibration enabled, apply // results to all DQSs (i.e. assume same delay on all // DQSs). pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end // This counter used to implement settling time between // Phaser_IN rank register loads to different DQSs always @(posedge clk) begin if (rst) done_cnt <= #TCQ 'b0; else if (((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_NEXT_DQS)) || ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) done_cnt <= #TCQ 4'b1010; else if (done_cnt > 'b0) done_cnt <= #TCQ done_cnt - 1; end // During rank register loading the rank count must be sent to // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to // issue NOPs during rank register loading with the appropriate // rank count always @(posedge clk) begin if (rst || (regl_rank_done_r == 1'b1)) regl_rank_done_r <= #TCQ 1'b0; else if ((regl_dqs_cnt == DQS_WIDTH-1) && (regl_rank_cnt != RANKS-1) && (done_cnt == 4'd1)) regl_rank_done_r <= #TCQ 1'b1; end // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*regl_dqs_cnt. // replacing this with two left shifts + 1 left shift to avoid // DSP multiplier. assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; // Load Phaser_OUT rank register with rdlvl delay value // for each DQS per rank. always @(posedge clk) begin if (rst || (done_cnt == 4'd0)) begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin pi_stg2_load_timing <= #TCQ 'b1; pi_stg2_reg_l_timing <= #TCQ rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; end else begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_stg2_load <= #TCQ pi_stg2_load_timing; pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_rank_cnt <= #TCQ 2'b00; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_rank_cnt <= #TCQ regl_rank_cnt; else regl_rank_cnt <= #TCQ regl_rank_cnt + 1; end end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_dqs_cnt <= #TCQ regl_dqs_cnt; else regl_dqs_cnt <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) && (done_cnt == 4'd1)) regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; else regl_dqs_cnt <= #TCQ regl_dqs_cnt; end always @(posedge clk) regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; //***************************************************************** // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: // The actual IDELAY elements for each of the DQ bits is set via the // DLYVAL parallel load port. However, the stage 1 calibration // algorithm (well most of it) only needs to increment or decrement the DQ // IDELAY value by 1 at any one time. //***************************************************************** // Chip-select generation for each of the individual counters tracking // IDELAY tap values for each DQ generate for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq always @(posedge clk) if (rst) dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skipping calibration altogether (only for simulation), no // need to set DQ IODELAY values - they are hardcoded dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "FAST_CAL") begin // If fast calibration option (simulation only) selected, DQ // IODELAYs across all bytes are updated simultaneously // (although per-bit deskew within DQS[0] is still supported) for (h = 0; h < DRAM_WIDTH; h = h + 1) begin dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; end end else if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (cal1_cnt_cpt_r == z) begin for (g = 0; g < DRAM_WIDTH; g = g + 1) begin dlyce_dq_r[DRAM_WIDTH*z + g] <= #TCQ cal1_dlyce_dq_r; end end else dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; end end endgenerate // Also delay increment/decrement control to match delay on DLYCE always @(posedge clk) if (rst) dlyinc_dq_r <= #TCQ 1'b0; else dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; // Each DQ has a counter associated with it to record current read-leveling // delay value always @(posedge clk) // Reset or skipping calibration all together if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg if (dlyce_dq_r[r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; else dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; end end end end else begin if (dlyce_dq_r[cal1_cnt_cpt_r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; else dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; end end // Register for timing (help with logic placement) always @(posedge clk) begin for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; end end //*************************************************************************** // Generate signal used to delay calibration state machine - used when: // (1) IDELAY value changed // (2) RD_MUX_SEL value changed // Use when a delay is necessary to give the change time to propagate // through the data pipeline (through IDELAY and ISERDES, and fabric // pipeline stages) //*************************************************************************** // List all the stage 1 calibration wait states here. // verilint STARC-2.7.3.3b off always @(posedge clk) if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || (cal1_state_r == CAL1_VALID_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT) || (cal1_state_r == CAL1_CENTER_WAIT) || (cal1_state_r == CAL1_RD_STOP_FOR_PI_INC)) cal1_wait_cnt_en_r <= #TCQ 1'b1; else cal1_wait_cnt_en_r <= #TCQ 1'b0; // verilint STARC-2.7.3.3b on always @(posedge clk) if (!cal1_wait_cnt_en_r) begin cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b1; end else begin if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; cal1_wait_r <= #TCQ 1'b1; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b0; end end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) rdlvl_prech_req <= #TCQ 1'b0; else rdlvl_prech_req <= #TCQ cal1_prech_req_r; //*************************************************************************** // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of // data from ISERDES. The value of this register is also stored, so that // previous and current values of the ISERDES data can be compared while // varying the IODELAY taps to see if an "edge" of the data valid window // has been encountered since the last IODELAY tap adjustment //*************************************************************************** //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise2_r[rd_i]}; sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall2_r[rd_i]}; sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise3_r[rd_i]}; sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall3_r[rd_i]}; end end end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; end end end end end endgenerate //*************************************************************************** // Conversion to pattern calibration //*************************************************************************** // Pattern for DQ IDELAY calibration //***************************************************************** // Expected data pattern when DQ shifted to the right such that // DQS before the left edge of the DVW: // Based on pattern of ({rise,fall}) = // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 // Each nibble will look like: // bit3: 0, 1, 0, 0, 1, 1 // bit2: 0, 0, 1, 1, 0, 0 // bit1: 0, 1, 0, 0, 1, 0 // bit0: 1, 1, 0, 0, 1, 1 // Or if the write is early it could look like: // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE // bit3: 0, 0, 1, 1, 0, 1 // bit2: 1, 1, 0, 0, 1, 1 // bit1: 0, 0, 1, 0, 1, 1 // bit0: 0, 0, 1, 1, 0, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign {idel_pat0_rise0[3], idel_pat0_rise0[2], idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; assign {idel_pat0_fall0[3], idel_pat0_fall0[2], idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; assign {idel_pat0_rise1[3], idel_pat0_rise1[2], idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; assign {idel_pat0_fall1[3], idel_pat0_fall1[2], idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; assign {idel_pat0_rise2[3], idel_pat0_rise2[2], idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; assign {idel_pat0_fall2[3], idel_pat0_fall2[2], idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; assign {idel_pat0_rise3[3], idel_pat0_rise3[2], idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; assign {idel_pat0_fall3[3], idel_pat0_fall3[2], idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; // Target pattern for "on-time write" assign {idel_pat1_rise0[3], idel_pat1_rise0[2], idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; assign {idel_pat1_fall0[3], idel_pat1_fall0[2], idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; assign {idel_pat1_rise1[3], idel_pat1_rise1[2], idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; assign {idel_pat1_fall1[3], idel_pat1_fall1[2], idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; assign {idel_pat1_rise2[3], idel_pat1_rise2[2], idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; assign {idel_pat1_fall2[3], idel_pat1_fall2[2], idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; assign {idel_pat1_rise3[3], idel_pat1_rise3[2], idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; assign {idel_pat1_fall3[3], idel_pat1_fall3[2], idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; // Correct data valid window for "early write" assign {pat0_rise0[3], pat0_rise0[2], pat0_rise0[1], pat0_rise0[0]} = 4'h7; assign {pat0_fall0[3], pat0_fall0[2], pat0_fall0[1], pat0_fall0[0]} = 4'hE; assign {pat0_rise1[3], pat0_rise1[2], pat0_rise1[1], pat0_rise1[0]} = 4'hC; assign {pat0_fall1[3], pat0_fall1[2], pat0_fall1[1], pat0_fall1[0]} = 4'h9; assign {pat0_rise2[3], pat0_rise2[2], pat0_rise2[1], pat0_rise2[0]} = 4'h2; assign {pat0_fall2[3], pat0_fall2[2], pat0_fall2[1], pat0_fall2[0]} = 4'h4; assign {pat0_rise3[3], pat0_rise3[2], pat0_rise3[1], pat0_rise3[0]} = 4'hB; assign {pat0_fall3[3], pat0_fall3[2], pat0_fall3[1], pat0_fall3[0]} = 4'h1; // Correct data valid window for "on-time write" assign {pat1_rise0[3], pat1_rise0[2], pat1_rise0[1], pat1_rise0[0]} = 4'h9; assign {pat1_fall0[3], pat1_fall0[2], pat1_fall0[1], pat1_fall0[0]} = 4'h3; assign {pat1_rise1[3], pat1_rise1[2], pat1_rise1[1], pat1_rise1[0]} = 4'h7; assign {pat1_fall1[3], pat1_fall1[2], pat1_fall1[1], pat1_fall1[0]} = 4'hE; assign {pat1_rise2[3], pat1_rise2[2], pat1_rise2[1], pat1_rise2[0]} = 4'hC; assign {pat1_fall2[3], pat1_fall2[2], pat1_fall2[1], pat1_fall2[0]} = 4'h9; assign {pat1_rise3[3], pat1_rise3[2], pat1_rise3[1], pat1_rise3[0]} = 4'h2; assign {pat1_fall3[3], pat1_fall3[2], pat1_fall3[1], pat1_fall3[0]} = 4'h4; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign idel_pat0_rise0[3] = 2'b01; assign idel_pat0_fall0[3] = 2'b00; assign idel_pat0_rise1[3] = 2'b10; assign idel_pat0_fall1[3] = 2'b11; assign idel_pat0_rise0[2] = 2'b00; assign idel_pat0_fall0[2] = 2'b10; assign idel_pat0_rise1[2] = 2'b11; assign idel_pat0_fall1[2] = 2'b10; assign idel_pat0_rise0[1] = 2'b00; assign idel_pat0_fall0[1] = 2'b11; assign idel_pat0_rise1[1] = 2'b10; assign idel_pat0_fall1[1] = 2'b01; assign idel_pat0_rise0[0] = 2'b11; assign idel_pat0_fall0[0] = 2'b10; assign idel_pat0_rise1[0] = 2'b00; assign idel_pat0_fall1[0] = 2'b01; // Target pattern for "on-time write" assign idel_pat1_rise0[3] = 2'b01; assign idel_pat1_fall0[3] = 2'b11; assign idel_pat1_rise1[3] = 2'b01; assign idel_pat1_fall1[3] = 2'b00; assign idel_pat1_rise0[2] = 2'b11; assign idel_pat1_fall0[2] = 2'b01; assign idel_pat1_rise1[2] = 2'b00; assign idel_pat1_fall1[2] = 2'b10; assign idel_pat1_rise0[1] = 2'b01; assign idel_pat1_fall0[1] = 2'b00; assign idel_pat1_rise1[1] = 2'b10; assign idel_pat1_fall1[1] = 2'b11; assign idel_pat1_rise0[0] = 2'b00; assign idel_pat1_fall0[0] = 2'b10; assign idel_pat1_rise1[0] = 2'b11; assign idel_pat1_fall1[0] = 2'b10; // Correct data valid window for "early write" assign pat0_rise0[3] = 2'b00; assign pat0_fall0[3] = 2'b10; assign pat0_rise1[3] = 2'b11; assign pat0_fall1[3] = 2'b10; assign pat0_rise0[2] = 2'b10; assign pat0_fall0[2] = 2'b11; assign pat0_rise1[2] = 2'b10; assign pat0_fall1[2] = 2'b00; assign pat0_rise0[1] = 2'b11; assign pat0_fall0[1] = 2'b10; assign pat0_rise1[1] = 2'b01; assign pat0_fall1[1] = 2'b00; assign pat0_rise0[0] = 2'b10; assign pat0_fall0[0] = 2'b00; assign pat0_rise1[0] = 2'b01; assign pat0_fall1[0] = 2'b11; // Correct data valid window for "on-time write" assign pat1_rise0[3] = 2'b11; assign pat1_fall0[3] = 2'b01; assign pat1_rise1[3] = 2'b00; assign pat1_fall1[3] = 2'b10; assign pat1_rise0[2] = 2'b01; assign pat1_fall0[2] = 2'b00; assign pat1_rise1[2] = 2'b10; assign pat1_fall1[2] = 2'b11; assign pat1_rise0[1] = 2'b00; assign pat1_fall0[1] = 2'b10; assign pat1_rise1[1] = 2'b11; assign pat1_fall1[1] = 2'b10; assign pat1_rise0[0] = 2'b10; assign pat1_fall0[0] = 2'b11; assign pat1_rise1[0] = 2'b10; assign pat1_fall1[0] = 2'b00; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r && idel_pat0_match_rise2_and_r && idel_pat0_match_fall2_and_r && idel_pat0_match_rise3_and_r && idel_pat0_match_fall3_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r && idel_pat1_match_rise2_and_r && idel_pat1_match_fall2_and_r && idel_pat1_match_rise3_and_r && idel_pat1_match_fall3_and_r); end always @(*) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r && pat0_match_rise2_and_r && pat0_match_fall2_and_r && pat0_match_rise3_and_r && pat0_match_fall3_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r && pat1_match_rise2_and_r && pat1_match_fall2_and_r && pat1_match_rise3_and_r && pat1_match_fall3_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r); end always @(posedge clk) begin if (sr_valid_r2) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; end //assign idel_pat_data_match = idel_pat0_data_match_r | // idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end endgenerate always @(posedge clk) begin rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; end //*************************************************************************** // First stage calibration: Capture clock //*************************************************************************** //***************************************************************** // Keep track of how many samples have been written to shift registers // Every time RD_SHIFT_LEN samples have been written, then we have a // full read training pattern loaded into the sr_* registers. Then assert // sr_valid_r to indicate that: (1) comparison between the sr_* and // old_sr_* and prev_sr_* registers can take place, (2) transfer of // the contents of sr_* to old_sr_* and prev_sr_* registers can also // take place //***************************************************************** // verilint STARC-2.2.3.3 off always @(posedge clk) if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin cnt_shift_r <= #TCQ 'b1; sr_valid_r <= #TCQ 1'b0; mpr_valid_r <= #TCQ 1'b0; end else begin if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin if (cnt_shift_r == 'b0) mpr_valid_r <= #TCQ 1'b1; else begin mpr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else mpr_valid_r <= #TCQ 1'b0; if (mux_rd_valid_r && rdlvl_stg1_start) begin if (cnt_shift_r == RD_SHIFT_LEN-1) begin sr_valid_r <= #TCQ 1'b1; cnt_shift_r <= #TCQ 'b0; end else begin sr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else // When the current mux_rd_* contents are not valid, then // retain the current value of cnt_shift_r, and make sure // that sr_valid_r = 0 to prevent any downstream loads or // comparisons sr_valid_r <= #TCQ 1'b0; end // verilint STARC-2.2.3.3 on //***************************************************************** // Logic to determine when either edge of the data eye encountered // Pre- and post-IDELAY update data pattern is compared, if they // differ, than an edge has been encountered. Currently no attempt // made to determine if the data pattern itself is "correct", only // whether it changes after incrementing the IDELAY (possible // future enhancement) //***************************************************************** // One-way control for ensuring that state machine request to store // current read data into OLD SR shift register only occurs on a // valid clock cycle. The FSM provides a one-cycle request pulse. // It is the responsibility of the FSM to wait the worst-case time // before relying on any downstream results of this load. always @(posedge clk) if (rst) store_sr_r <= #TCQ 1'b0; else begin if (store_sr_req_r) store_sr_r <= #TCQ 1'b1; else if ((sr_valid_r || mpr_valid_r) && store_sr_r) store_sr_r <= #TCQ 1'b0; end // Transfer current data to old data, prior to incrementing delay // Also store data from current sampling window - so that we can detect // if the current delay tap yields data that is "jittery" generate if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin // Load last sample (i.e. from current sampling interval) prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end end end end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end end end end endgenerate //******************************************************* // Match determination occurs over 3 cycles - pipelined for better timing //******************************************************* // Match valid with # of cycles of pipelining in match determination always @(posedge clk) begin sr_valid_r1 <= #TCQ sr_valid_r; sr_valid_r2 <= #TCQ sr_valid_r1; mpr_valid_r1 <= #TCQ mpr_valid_r; mpr_valid_r2 <= #TCQ mpr_valid_r1; end generate if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin // CYCLE1: Compare all bits in DQS grp, generate separate term for // each bit over four bit times. For example, if there are 8-bits // per DQS group, 32 terms are generated on cycle 1 // NOTE: Structure HDL such that X on data bus will result in a // mismatch. This is required for memory models that can drive the // bus with X's to model uncertainty regions (e.g. Denali) if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) old_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; else old_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) old_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; else old_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) old_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; else old_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) old_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; else old_sr_match_fall3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) prev_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; else prev_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) prev_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; else prev_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) prev_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; else prev_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) prev_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; else prev_sr_match_fall3_r[z] <= #TCQ 1'b0; // CYCLE2: Combine all the comparisons for every 8 words (rise0, // fall0,rise1, fall1) in the calibration sequence. Now we're down // to DRAM_WIDTH terms old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z] & old_sr_match_rise2_r[z] & old_sr_match_fall2_r[z] & old_sr_match_rise3_r[z] & old_sr_match_fall3_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z] & prev_sr_match_rise2_r[z] & prev_sr_match_fall2_r[z] & prev_sr_match_rise3_r[z] & prev_sr_match_fall3_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end endgenerate //*************************************************************************** // First stage calibration: DQS Capture //*************************************************************************** //******************************************************* // Counters for tracking # of samples compared // For each comparision point (i.e. to determine if an edge has // occurred after each IODELAY increment when read leveling), // multiple samples are compared in order to average out the effects // of jitter. If any one of these samples is different than the "old" // sample corresponding to the previous IODELAY value, then an edge // is declared to be detected. //******************************************************* // Two cascaded counters are used to keep track of # of samples compared, // in order to make it easier to meeting timing on these paths. Once // optimal sampling interval is determined, it may be possible to remove // the second counter always @(posedge clk) samp_edge_cnt0_en_r <= #TCQ (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); // First counter counts # of samples compared always @(posedge clk) if (rst) samp_edge_cnt0_r <= #TCQ 'b0; else begin if (!samp_edge_cnt0_en_r) // Reset sample counter when not in any of the "sampling" states samp_edge_cnt0_r <= #TCQ 'b0; else if (sr_valid_r2 || mpr_valid_r2) // Otherwise, count # of samples compared samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; end // Counter #2 enable generation always @(posedge clk) if (rst) samp_edge_cnt1_en_r <= #TCQ 1'b0; else begin // Assert pulse when correct number of samples compared if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && (sr_valid_r2 || mpr_valid_r2)) samp_edge_cnt1_en_r <= #TCQ 1'b1; else samp_edge_cnt1_en_r <= #TCQ 1'b0; end // Counter #2 always @(posedge clk) if (rst) samp_edge_cnt1_r <= #TCQ 'b0; else if (!samp_edge_cnt0_en_r) samp_edge_cnt1_r <= #TCQ 'b0; else if (samp_edge_cnt1_en_r) samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; always @(posedge clk) if (rst) samp_cnt_done_r <= #TCQ 1'b0; else begin if (!samp_edge_cnt0_en_r) samp_cnt_done_r <= #TCQ 'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (samp_edge_cnt0_r == SR_VALID_DELAY-1) // For simulation only, stay in edge detection mode a minimum // amount of time - just enough for two data compares to finish samp_cnt_done_r <= #TCQ 1'b1; end else begin if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) samp_cnt_done_r <= #TCQ 1'b1; end end //***************************************************************** // Logic to keep track of (on per-bit basis): // 1. When a region of stability preceded by a known edge occurs // 2. If for the current tap, the read data jitters // 3. If an edge occured between the current and previous tap // 4. When the current edge detection/sampling interval can end // Essentially, these are a series of status bits - the stage 1 // calibration FSM monitors these to determine when an edge is // found. Additional information is provided to help the FSM // determine if a left or right edge has been found. //**************************************************************** assign pb_detect_edge_setup = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); assign pb_detect_edge = (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); generate for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge always @(posedge clk) begin if (pb_detect_edge_setup) begin // Reset eye size, stable eye marker, and jitter marker before // starting new edge detection iteration pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_found_edge_last_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b0; pb_found_first_edge_r[z] <= #TCQ 1'b0; end else if (pb_detect_edge) begin // Save information on which DQ bits are already out of the // data valid window - those DQ bits will later not have their // IDELAY tap value incremented pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; if (!pb_detect_edge_done_r[z]) begin if (samp_cnt_done_r) begin // If we've reached end of sampling interval, no jitter on // current tap has been found (although an edge could have // been found between the current and previous taps), and // the sampling interval is complete. Increment the stable // eye counter if no edge found, and always clear the jitter // flag in preparation for the next tap. pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b1; if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin // If the data was completely stable during this tap and // no edge was found between this and the previous tap // then increment the stable eye counter "as appropriate" if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; else //if (pb_found_first_edge_r[z]) // We've reached minimum stable eye width pb_found_stable_eye_r[z] <= #TCQ 1'b1; end else begin // Otherwise, an edge was found, either because of a // difference between this and the previous tap's read // data, and/or because the previous tap's data jittered // (but not the current tap's data), then just set the // edge found flag, and enable the stable eye counter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end end else if (prev_sr_diff_r[z]) begin // If we find that the current tap read data jitters, then // set edge and jitter found flags, "enable" the eye size // counter, and stop sampling interval for this bit pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b1; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin // If either an edge was found (i.e. difference between // current tap and previous tap read data), or the previous // tap exhibited jitter (which means by definition that the // current tap cannot match the previous tap because the // previous tap gave unstable data), then set the edge found // flag, and "enable" eye size counter. But do not stop // sampling interval - we still need to check if the current // tap exhibits jitter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; end end end else begin // Before every edge detection interval, reset "intra-tap" flags pb_found_edge_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; end end end endgenerate // Combine the above per-bit status flags into combined terms when // performing deskew on the aggregate data window always @(posedge clk) begin detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; found_edge_r <= #TCQ |pb_found_edge_r; found_edge_all_r <= #TCQ &pb_found_edge_r; found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; end // last IODELAY "stable eye" indicator is updated only after // detect_edge_done_r is asserted - so that when we do find the "right edge" // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates // immediately, then it never possible to have found_stable_eye_r = 1 // when we detect an edge - and we'll never know whether we've found // a "right edge") always @(posedge clk) if (pb_detect_edge_setup) found_stable_eye_last_r <= #TCQ 1'b0; else if (detect_edge_done_r) found_stable_eye_last_r <= #TCQ found_stable_eye_r; //***************************************************************** // Keep track of DQ IDELAYE2 taps used //***************************************************************** // Added additional register stage to improve timing always @(posedge clk) if (rst) idelay_tap_cnt_slice_r <= 5'h0; else idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; always @(posedge clk) if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r for (s = 0; s < RANKS; s = s + 1) begin for (t = 0; t < DQS_WIDTH; t = t + 1) begin idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; end end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (u = 0; u < RANKS; u = u + 1) begin for (w = 0; w < DQS_WIDTH; w = w + 1) begin if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; else idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; end end end end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin for (f = 0; f < DQS_WIDTH; f = f + 1) begin idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; end end else if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; else idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; end else if (idelay_ld) idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; always @(posedge clk) if (rst || new_cnt_cpt_r) idelay_tap_limit_r <= #TCQ 1'b0; else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) idelay_tap_limit_r <= #TCQ 1'b1; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst || new_cnt_cpt_r || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_cnt_cpt_r <= #TCQ 'b0; else if (cal1_dlyce_cpt_r) begin if (cal1_dlyinc_cpt_r) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; else if (tap_cnt_cpt_r != 'd0) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; end always @(posedge clk) if (rst || new_cnt_cpt_r || (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_limit_cpt_r <= #TCQ 1'b0; else if (tap_cnt_cpt_r == 6'd63) tap_limit_cpt_r <= #TCQ 1'b1; always @(posedge clk) cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop for (b = 0; b < DQS_WIDTH; b = b + 1) rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; end end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; end end end else if (SIM_CAL_OPTION == "SKIP_CAL") begin for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; end end end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; end end // Counter to track maximum DQ IODELAY tap usage during the per-bit // deskew portion of stage 1 calibration always @(posedge clk) if (rst) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (new_cnt_cpt_r) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (|cal1_dlyce_dq_r) begin if (cal1_dlyinc_dq_r) idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; else idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; if (idel_tap_cnt_dq_pb_r == 31) idel_tap_limit_dq_pb_r <= #TCQ 1'b1; else idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end //***************************************************************** always @(posedge clk) begin cal1_state_r1 <= #TCQ cal1_state_r; cal1_state_r2 <= #TCQ cal1_state_r1; cal1_state_r3 <= #TCQ cal1_state_r2; end always @(posedge clk) if (rst) begin cal1_cnt_cpt_r <= #TCQ 'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; right_edge_taps_r <= #TCQ 6'b000000; first_edge_taps_r <= #TCQ 6'bxxxxxx; new_cnt_cpt_r <= #TCQ 1'b0; rdlvl_stg1_done_int <= #TCQ 1'b0; rdlvl_stg1_err <= #TCQ 1'b0; second_edge_taps_r <= #TCQ 6'bxxxxxx; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; rnk_cnt_r <= #TCQ 2'b00; rdlvl_rank_done_r <= #TCQ 1'b0; idel_dec_cnt <= #TCQ 'd0; rdlvl_last_byte_done_int <= #TCQ 1'b0; idel_pat_detect_valid_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; if (OCAL_EN == "ON") mpr_rdlvl_done_r <= #TCQ 1'b0; else mpr_rdlvl_done_r <= #TCQ 1'b1; mpr_dec_cpt_r <= #TCQ 1'b0; rdlvl_pi_incdec <= #TCQ 1'b0; end else begin // default (inactive) states for all "pulse" outputs // verilint STARC-2.2.3.3 off cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; new_cnt_cpt_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; case (cal1_state_r) CAL1_IDLE: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done_int <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin rdlvl_pi_incdec <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; end else begin rdlvl_pi_incdec <= #TCQ 1'b1; if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL") cal1_state_r <= #TCQ CAL1_REGL_LOAD; else if (SIM_CAL_OPTION == "FAST_CAL") cal1_state_r <= #TCQ CAL1_NEXT_DQS; else begin new_cnt_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end end end CAL1_MPR_NEW_DQS_WAIT: begin cal1_prech_req_r <= #TCQ 1'b0; if (!cal1_wait_r && mpr_valid_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group CAL1_NEW_DQS_WAIT: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done_int <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; if (|pi_counter_read_val) begin //VK_REVIEW mpr_dec_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed end else if (!cal1_wait_r) begin rdlvl_pi_incdec <= #TCQ 1'b0; // Store "previous tap" read data. Technically there is no // "previous" read data, since we are starting a new DQS // group, so we'll never find an edge at tap 0 unless the // data is fluctuating/jittering store_sr_req_r <= #TCQ 1'b1; // If per-bit deskew is disabled, then skip the first // portion of stage 1 calibration if (PER_BIT_DESKEW == "OFF") cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else if (PER_BIT_DESKEW == "ON") cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; end else rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed end //***************************************************************** // Per-bit deskew states //***************************************************************** // Wait state following storage of initial read data CAL1_PB_STORE_FIRST_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; // Look for an edge on all DQ bits in current DQS group CAL1_PB_DETECT_EDGE: if (detect_edge_done_r) begin if (found_stable_eye_r) begin // If we've found the left edge for all bits (or more precisely, // we've found the left edge, and then part of the stable // window thereafter), then proceed to positioning the CPT clock // right before the left margin cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; end else begin // If we've reached the end of the sampling time, and haven't // yet found the left margin of all the DQ bits, then: if (!tap_limit_cpt_r) begin // If we still have taps left to use, then store current value // of read data, increment the capture clock, and continue to // look for (left) edges store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT; end else begin // If we ran out of taps moving the capture clock, and we // haven't finished edge detection, then reset the capture // clock taps to 0 (gradually, one tap at a time... // then exit the per-bit portion of the algorithm - // i.e. proceed to adjust the capture clock and DQ IODELAYs as cnt_idel_dec_cpt_r <= #TCQ 6'd63; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end end end // Increment delay for DQS CAL1_PB_INC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; end // Wait for IODELAY for both capture and internal nodes within // ISERDES to settle, before checking again for an edge CAL1_PB_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) begin cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; end end // We've found the left edges of the windows for all DQ bits // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture // clock IDELAY to position just outside left edge of data window CAL1_PB_DEC_CPT_LEFT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end CAL1_PB_DEC_CPT_LEFT_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // If there is skew between individual DQ bits, then after we've // positioned the CPT clock, we will be "in the window" for some // DQ bits ("early" DQ bits), and "out of the window" for others // ("late" DQ bits). Increase DQ taps until we are out of the // window for all DQ bits CAL1_PB_DETECT_EDGE_DQ: if (detect_edge_done_r) if (found_edge_all_r) begin // We're out of the window for all DQ bits in this DQS group // We're done with per-bit deskew for this group - now decr // capture clock IODELAY tap count back to 0, and proceed // with the rest of stage 1 calibration for this DQS group cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end else if (!idel_tap_limit_dq_pb_r) // If we still have DQ taps available for deskew, keep // incrementing IODELAY tap count for the appropriate DQ bits cal1_state_r <= #TCQ CAL1_PB_INC_DQ; else begin // Otherwise, stop immediately (we've done the best we can) // and proceed with rest of stage 1 calibration cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end CAL1_PB_INC_DQ: begin // Increment only those DQ for which an edge hasn't been found yet cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; cal1_dlyinc_dq_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; end CAL1_PB_INC_DQ_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // Decrement capture clock taps back to initial value CAL1_PB_DEC_CPT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end // Wait for capture clock to settle, then proceed to rest of // state 1 calibration for this DQS group CAL1_PB_DEC_CPT_WAIT: if (!cal1_wait_r) begin store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end // When first starting calibration for a DQS group, save the // current value of the read data shift register, and use this // as a reference. Note that for the first iteration of the // edge detection loop, we will in effect be checking for an edge // at IODELAY taps = 0 - normally, we are comparing the read data // for IODELAY taps = N, with the read data for IODELAY taps = N-1 // An edge can only be found at IODELAY taps = 0 if the read data // is changing during this time (possible due to jitter) CAL1_STORE_FIRST_WAIT: begin mpr_dec_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PAT_DETECT; end CAL1_VALID_WAIT: begin if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end CAL1_MPR_PAT_DETECT: begin rdlvl_pi_incdec <= #TCQ 1'b0; // MPR read leveling for centering DQS in valid window before // OCLKDELAYED calibration begins in order to eliminate read issues if (idel_pat_detect_valid_r == 1'b0) begin cal1_state_r <= #TCQ CAL1_VALID_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b1; end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 'd0; end else if (!idelay_tap_limit_r) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; else cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end CAL1_PAT_DETECT: begin // All DQ bits associated with a DQS are pushed to the right one IDELAY // tap at a time until first rising DQS is in the tri-state region // before first rising edge window. // The detect_edge_done_r condition included to support averaging // during IDELAY tap increments rdlvl_pi_incdec <= #TCQ 1'b0; if (detect_edge_done_r) begin if (idel_pat_data_match) begin case (idelay_adj) 2'b01: begin cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; idel_dec_cnt <= #TCQ 5'd0; idel_adj_inc <= #TCQ 1'b1; end 2'b10: begin //DEC by 1 cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; idel_dec_cnt <= #TCQ 5'd1; idel_adj_inc <= #TCQ 1'b0; end default: begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 5'd0; idel_adj_inc <= #TCQ 1'b0; end endcase end else if (!idelay_tap_limit_r) begin cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; end else begin cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end end end // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated // until left edge of valid window detected CAL1_DQ_IDEL_TAP_INC: begin cal1_dq_idel_ce <= #TCQ 1'b1; cal1_dq_idel_inc <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b0; end CAL1_DQ_IDEL_TAP_INC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin idel_adj_inc <= #TCQ 1'b0; if (idel_adj_inc) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; else cal1_state_r <= #TCQ CAL1_PAT_DETECT; end end // Decrement by 2 IDELAY taps once idel_pat_data_match detected CAL1_DQ_IDEL_TAP_DEC: begin cal1_dq_idel_inc <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; if (idel_dec_cnt >= 'd0) cal1_dq_idel_ce <= #TCQ 1'b1; else cal1_dq_idel_ce <= #TCQ 1'b0; if (idel_dec_cnt > 'd0) idel_dec_cnt <= #TCQ idel_dec_cnt - 1; else idel_dec_cnt <= #TCQ idel_dec_cnt; end CAL1_DQ_IDEL_TAP_DEC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; else if (mpr_dec_cpt_r) cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in CAL1_DETECT_EDGE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change CAL1_DETECT_EDGE: begin // Essentially wait for the first comparision to finish, then // store current data into "old" data register. This store // happens now, rather than later (e.g. when we've have already // left this state) in order to avoid the situation the data that // is stored as "old" data has not been used in an "active // comparison" - i.e. data is stored after the last comparison // of this state. In this case, we can miss an edge if the // following sequence occurs: // 1. Comparison completes in this state - no edge found // 2. "Momentary jitter" occurs which "pushes" the data out the // equivalent of one delay tap // 3. We store this jittered data as the "old" data // 4. "Jitter" no longer present // 5. We increment the delay tap by one // 6. Now we compare the current with the "old" data - they're // the same, and no edge is detected // NOTE: Given the large # of comparisons done in this state, it's // highly unlikely the above sequence will occur in actual H/W // Wait for the first load of read data into the comparison // shift register to finish, then load the current read data // into the "old" data register. This allows us to do one // initial comparision between the current read data, and // stored data corresponding to the previous delay tap idel_pat_detect_valid_r <= #TCQ 1'b0; if (!store_sr_req_pulsed_r) begin // Pulse store_sr_req_r only once in this state store_sr_req_r <= #TCQ 1'b1; store_sr_req_pulsed_r <= #TCQ 1'b1; end else begin store_sr_req_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b1; end // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed if (detect_edge_done_r) begin if (tap_limit_cpt_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. cal1_state_r <= #TCQ CAL1_CALC_IDEL; else if (found_edge_r) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge found_first_edge_r <= #TCQ 1'b1; // Only the right edge of the data valid window is found // Record the inner right edge tap value if (!found_first_edge_r && found_stable_eye_last_r) begin if (tap_cnt_cpt_r == 'd0) right_edge_taps_r <= #TCQ 'd0; else right_edge_taps_r <= #TCQ tap_cnt_cpt_r; end // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (found_first_edge_r && found_stable_eye_last_r) begin found_second_edge_r <= #TCQ 1'b1; second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; cal1_state_r <= #TCQ CAL1_CALC_IDEL; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! first_edge_taps_r <= #TCQ tap_cnt_cpt_r; //wait for read stop before PI increament cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC; end end else // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing //wait for read stop before PI increament cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC; end end //before increment PI, read command sending should be stopped. //Also need to wait existing read is finished CAL1_RD_STOP_FOR_PI_INC: begin rdlvl_pi_incdec <= #TCQ 1'b1; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end // Increment Phaser_IN delay for DQS CAL1_IDEL_INC_CPT: begin cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; if (~tap_limit_cpt_r) begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; end else begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; end end // Wait for Phaser_In to settle, before checking again for an edge CAL1_IDEL_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; rdlvl_pi_incdec <= #TCQ 1'b0; //return to normal read end end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: We're calculating the amount to decrement by, not the // absolute setting for DQS. CAL1_CALC_IDEL: begin // CASE1: If 2 edges found. if (found_second_edge_r) cnt_idel_dec_cpt_r <= #TCQ ((second_edge_taps_r - first_edge_taps_r)>>1) + 1; else if (right_edge_taps_r > 6'd0) // Only right edge detected // right_edge_taps_r is the inner right edge tap value // hence used for calculation cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); else if (found_first_edge_r) // Only left edge detected cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); else cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r>>1); // Now use the value we just calculated to decrement CPT taps // to the desired calibration point //cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; cal1_state_r <= #TCQ CAL1_CENTER_WAIT; rdlvl_pi_incdec <= #TCQ 1'b1; end CAL1_CENTER_WAIT: begin if(!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) CAL1_IDEL_DEC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; if (cnt_idel_dec_cpt_r == 6'b000001) begin if (mpr_dec_cpt_r) begin if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; end else cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end else cal1_state_r <= #TCQ CAL1_NEXT_DQS; end else cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; end CAL1_IDEL_DEC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate CAL1_NEXT_DQS: begin //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) cal1_prech_req_r <= #TCQ 1'b1; //else // cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; first_edge_taps_r <= #TCQ 'd0; second_edge_taps_r <= #TCQ 'd0; right_edge_taps_r <= #TCQ 'd0; if ((SIM_CAL_OPTION == "FAST_CAL") || (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin if (mpr_rdlvl_done_r) begin rdlvl_last_byte_done_int <= #TCQ 1'b1; mpr_last_byte_done <= #TCQ 1'b0; end else begin rdlvl_last_byte_done_int <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b1; end end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin if (SIM_CAL_OPTION == "FAST_CAL") begin //rdlvl_rank_done_r <= #TCQ 1'b1; rdlvl_last_byte_done_int <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin if (~mpr_rdlvl_done_r) begin mpr_rank_done_r <= #TCQ 1'b1; // if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_DONE; cal1_cnt_cpt_r <= #TCQ 'b0; // end else begin // // Process DQS groups in next rank // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; // new_cnt_cpt_r <= #TCQ 1'b1; // cal1_cnt_cpt_r <= #TCQ 'b0; // cal1_state_r <= #TCQ CAL1_IDLE; // end end else begin // All DQS groups in a rank done rdlvl_rank_done_r <= #TCQ 1'b1; if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_REGL_LOAD; end else begin // Process DQS groups in next rank rnk_cnt_r <= #TCQ rnk_cnt_r + 1; new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ 'b0; cal1_state_r <= #TCQ CAL1_IDLE; end end end else begin // Process next DQS group new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; end end end CAL1_NEW_DQS_PREWAIT: begin if (!cal1_wait_r) begin rdlvl_pi_incdec <= #TCQ 1'b0; if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; else cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end // Load rank registers in Phaser_IN CAL1_REGL_LOAD: begin rdlvl_rank_done_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_cnt_cpt_r <= #TCQ 'b0; rnk_cnt_r <= #TCQ 2'b00; if ((regl_rank_cnt == RANKS-1) && ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin cal1_state_r <= #TCQ CAL1_DONE; rdlvl_last_byte_done_int <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; end else cal1_state_r <= #TCQ CAL1_REGL_LOAD; end CAL1_RDLVL_ERR: begin rdlvl_stg1_err <= #TCQ 1'b1; end // Done with this stage of calibration // if used, allow DEBUG_PORT to control taps CAL1_DONE: begin mpr_rdlvl_done_r <= #TCQ 1'b1; cal1_prech_req_r <= #TCQ 1'b0; if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin rdlvl_stg1_done_int <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; end else rdlvl_stg1_done_int <= #TCQ 1'b1; end endcase end // verilint STARC-2.2.3.3 on endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v4_0_ddr_phy_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Dec 20 2013 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_ddr_phy_tempmon # ( parameter SKIP_CALIB = "FALSE", parameter TCQ = 100, // Register delay (simulation only) // Temperature bands must be in order. To disable bands, set to extreme. parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) parameter TEMP_HYST = 1, parameter TEMP_MIN_LIMIT = 12'h8ac, parameter TEMP_MAX_LIMIT = 12'hca4 ) ( input clk, // Fabric clock input rst, // System reset input calib_complete, // Calibration complete input tempmon_sample_en, // Signal to enable sampling input [11:0] device_temp, // Current device temperature input [11:0] calib_device_temp, // Calibration device temperature output tempmon_pi_f_inc, // Increment PHASER_IN taps output tempmon_pi_f_dec, // Decrement PHASER_IN taps output tempmon_sel_pi_incdec, // Assume control of PHASER_IN taps output tempmon_done_skip ); // translate hysteresis into XADC units localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504; localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ; // Temperature sampler FSM encoding localparam IDLE = 11'b000_0000_0001; localparam INIT = 11'b000_0000_0010; localparam FOUR_INC = 11'b000_0000_0100; localparam THREE_INC = 11'b000_0000_1000; localparam TWO_INC = 11'b000_0001_0000; localparam ONE_INC = 11'b000_0010_0000; localparam NEUTRAL = 11'b000_0100_0000; localparam ONE_DEC = 11'b000_1000_0000; localparam TWO_DEC = 11'b001_0000_0000; localparam THREE_DEC = 11'b010_0000_0000; localparam FOUR_DEC = 11'b100_0000_0000; //=========================================================================== // Reg declarations //=========================================================================== // Output port flops. Inc and dec are mutex. reg pi_f_dec; // Flop output reg pi_f_inc; // Flop output reg pi_f_dec_nxt; // FSM output reg pi_f_inc_nxt; // FSM output // FSM state reg [10:0] tempmon_state; reg [10:0] tempmon_state_nxt; // FSM output used to capture the initial device termperature reg tempmon_state_init; // Flag to indicate the initial device temperature is captured and normal operation can begin reg tempmon_init_complete; // Temperature band/state boundaries reg [11:0] four_inc_max_limit; reg [11:0] three_inc_max_limit; reg [11:0] two_inc_max_limit; reg [11:0] one_inc_max_limit; reg [11:0] neutral_max_limit; reg [11:0] one_dec_max_limit; reg [11:0] two_dec_max_limit; reg [11:0] three_dec_max_limit; reg [11:0] three_inc_min_limit; reg [11:0] two_inc_min_limit; reg [11:0] one_inc_min_limit; reg [11:0] neutral_min_limit; reg [11:0] one_dec_min_limit; reg [11:0] two_dec_min_limit; reg [11:0] three_dec_min_limit; reg [11:0] four_dec_min_limit; reg [11:0] device_temp_init; // Flops for capturing and storing the current device temperature reg tempmon_sample_en_101; reg tempmon_sample_en_102; reg [11:0] device_temp_101; reg [11:0] device_temp_capture_102; reg update_temp_102; // Flops for comparing temperature to max limits reg temp_cmp_four_inc_max_102; reg temp_cmp_three_inc_max_102; reg temp_cmp_two_inc_max_102; reg temp_cmp_one_inc_max_102; reg temp_cmp_neutral_max_102; reg temp_cmp_one_dec_max_102; reg temp_cmp_two_dec_max_102; reg temp_cmp_three_dec_max_102; // Flops for comparing temperature to min limits reg temp_cmp_three_inc_min_102; reg temp_cmp_two_inc_min_102; reg temp_cmp_one_inc_min_102; reg temp_cmp_neutral_min_102; reg temp_cmp_one_dec_min_102; reg temp_cmp_two_dec_min_102; reg temp_cmp_three_dec_min_102; reg temp_cmp_four_dec_min_102; reg calib_complete_r; reg tempmon_done; reg [2:0] sample_en_cnt; always @ (posedge clk) calib_complete_r <= #TCQ calib_complete; wire [11:0] device_temp_in = ((tempmon_state_init | ~calib_complete_r) & (SKIP_CALIB == "TRUE")) ? calib_device_temp : device_temp; always @ (posedge clk) begin if (rst) sample_en_cnt <= #TCQ 'd0; else if ((tempmon_sample_en & ~tempmon_sample_en_101) & ((SKIP_CALIB == "TRUE")) & (sample_en_cnt < 'd5)) sample_en_cnt <= #TCQ sample_en_cnt + 1; end always @ (posedge clk) begin if (rst) tempmon_done <= #TCQ 1'b0; else if ((sample_en_cnt == 'd5) & ((SKIP_CALIB == "TRUE"))) tempmon_done <= #TCQ 1'b1; end assign tempmon_done_skip = tempmon_done; //=========================================================================== // Overview and temperature band limits //=========================================================================== // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above // 125C will never be entered. // Temperature lowest highest // <------------------------------------------------------------------------------------------------------------------------------------------------> // // Temp four three two one neutral one two three four // band/state inc inc inc inc dec dec dec dec // // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| | // | | | | | | | // | | | | | | | // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit | // | device_temp_init | // four_inc_max_limit three_dec_max_limit // Boundaries for moving from lower temp bands to higher temp bands. // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C, // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range. wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET; wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET; wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET; wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET; wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0]; // Boundaries for moving from higher temp bands to lower temp bands wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET; wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET; wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET; wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET; wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET; wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band //=========================================================================== // Capture device temperature //=========================================================================== // There is a three stage pipeline used to capture temperature, calculate the next state // of the FSM, and update the tempmon outputs. // // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped. // Input device_temp is compared to ADC codes for 0C and 125C and limited // at the flop input if needed. // // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries // to determine if a state change is needed. State changes are only enabled on the // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser // increment or decrement signal is generated and flopped. // // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs. // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100 // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15 wire device_temp_high = device_temp_in > TEMP_MAX_LIMIT; wire device_temp_low = device_temp_in < TEMP_MIN_LIMIT; wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT ) | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT ) | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp_in ); // Capture/hold the initial temperature used in setting temperature bands and set init complete flag // to enable normal sample operation. wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init; wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete; // Capture/hold the current temperature on the sample enable signal rising edge after init is complete. // The captured current temp is not used functionaly. It is just useful for debug and waveform review. wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101; wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102; //=========================================================================== // Generate FSM arc signals //=========================================================================== // Temperature comparisons for increasing temperature. wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ; wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ; wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ; wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ; wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ; wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ; wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ; wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ; // Temperature comparisons for decreasing temperature. wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ; wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ; wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ; wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ; wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ; wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ; wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ; wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ; // FSM arcs for increasing temperature. wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102; wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102; wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102; wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102; wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102; wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102; wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102; wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102; // FSM arcs for decreasing temperature. wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102; wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102; wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102; wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102; wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102; wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102; wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102; wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102; //=========================================================================== // Implement FSM //=========================================================================== // In addition to the nine temperature states, there are also IDLE and INIT states. // The INIT state triggers the calculation of the temperature boundaries between the // other states. After INIT, the FSM will always go to the NEUTRAL state. There is // no timing restriction required between calib_complete and tempmon_sample_en. always @(*) begin tempmon_state_nxt = tempmon_state; tempmon_state_init = 1'b0; pi_f_inc_nxt = 1'b0; pi_f_dec_nxt = 1'b0; casez (tempmon_state) IDLE: begin if (calib_complete) tempmon_state_nxt = INIT; end INIT: begin tempmon_state_nxt = NEUTRAL; tempmon_state_init = 1'b1; end FOUR_INC: begin if (temp_gte_four_inc_max) begin tempmon_state_nxt = THREE_INC; pi_f_dec_nxt = 1'b1; end end THREE_INC: begin if (temp_gte_three_inc_max) begin tempmon_state_nxt = TWO_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_inc_min) begin tempmon_state_nxt = FOUR_INC; pi_f_inc_nxt = 1'b1; end end TWO_INC: begin if (temp_gte_two_inc_max) begin tempmon_state_nxt = ONE_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_inc_min) begin tempmon_state_nxt = THREE_INC; pi_f_inc_nxt = 1'b1; end end ONE_INC: begin if (temp_gte_one_inc_max) begin tempmon_state_nxt = NEUTRAL; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_inc_min) begin tempmon_state_nxt = TWO_INC; pi_f_inc_nxt = 1'b1; end end NEUTRAL: begin if (temp_gte_neutral_max) begin tempmon_state_nxt = ONE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_neutral_min) begin tempmon_state_nxt = ONE_INC; pi_f_inc_nxt = 1'b1; end end ONE_DEC: begin if (temp_gte_one_dec_max) begin tempmon_state_nxt = TWO_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_dec_min) begin tempmon_state_nxt = NEUTRAL; pi_f_inc_nxt = 1'b1; end end TWO_DEC: begin if (temp_gte_two_dec_max) begin tempmon_state_nxt = THREE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_dec_min) begin tempmon_state_nxt = ONE_DEC; pi_f_inc_nxt = 1'b1; end end THREE_DEC: begin if (temp_gte_three_dec_max) begin tempmon_state_nxt = FOUR_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_dec_min) begin tempmon_state_nxt = TWO_DEC; pi_f_inc_nxt = 1'b1; end end FOUR_DEC: begin if (temp_lte_four_dec_min) begin tempmon_state_nxt = THREE_DEC; pi_f_inc_nxt = 1'b1; end end default: begin tempmon_state_nxt = IDLE; end endcase end //always //synopsys translate_off reg [71:0] tempmon_state_name; always @(*) casez (tempmon_state) IDLE : tempmon_state_name = "IDLE"; INIT : tempmon_state_name = "INIT"; FOUR_INC : tempmon_state_name = "FOUR_INC"; THREE_INC : tempmon_state_name = "THREE_INC"; TWO_INC : tempmon_state_name = "TWO_INC"; ONE_INC : tempmon_state_name = "ONE_INC"; NEUTRAL : tempmon_state_name = "NEUTRAL"; ONE_DEC : tempmon_state_name = "ONE_DEC"; TWO_DEC : tempmon_state_name = "TWO_DEC"; THREE_DEC : tempmon_state_name = "THREE_DEC"; FOUR_DEC : tempmon_state_name = "FOUR_DEC"; default : tempmon_state_name = "BAD_STATE"; endcase //synopsys translate_on //=========================================================================== // Generate final output and implement flops //=========================================================================== // Generate output assign tempmon_pi_f_inc = pi_f_inc; assign tempmon_pi_f_dec = pi_f_dec; assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec; // Implement reset flops always @(posedge clk) begin if(rst) begin tempmon_state <= #TCQ 11'b000_0000_0001; pi_f_inc <= #TCQ 1'b0; pi_f_dec <= #TCQ 1'b0; four_inc_max_limit <= #TCQ 12'b0; three_inc_max_limit <= #TCQ 12'b0; two_inc_max_limit <= #TCQ 12'b0; one_inc_max_limit <= #TCQ 12'b0; neutral_max_limit <= #TCQ 12'b0; one_dec_max_limit <= #TCQ 12'b0; two_dec_max_limit <= #TCQ 12'b0; three_dec_max_limit <= #TCQ 12'b0; three_inc_min_limit <= #TCQ 12'b0; two_inc_min_limit <= #TCQ 12'b0; one_inc_min_limit <= #TCQ 12'b0; neutral_min_limit <= #TCQ 12'b0; one_dec_min_limit <= #TCQ 12'b0; two_dec_min_limit <= #TCQ 12'b0; three_dec_min_limit <= #TCQ 12'b0; four_dec_min_limit <= #TCQ 12'b0; device_temp_init <= #TCQ 12'b0; tempmon_init_complete <= #TCQ 1'b0; tempmon_sample_en_101 <= #TCQ 1'b0; tempmon_sample_en_102 <= #TCQ 1'b0; device_temp_101 <= #TCQ 12'b0; device_temp_capture_102 <= #TCQ 12'b0; end else begin tempmon_state <= #TCQ tempmon_state_nxt; pi_f_inc <= #TCQ pi_f_inc_nxt; pi_f_dec <= #TCQ pi_f_dec_nxt; four_inc_max_limit <= #TCQ four_inc_max_limit_nxt; three_inc_max_limit <= #TCQ three_inc_max_limit_nxt; two_inc_max_limit <= #TCQ two_inc_max_limit_nxt; one_inc_max_limit <= #TCQ one_inc_max_limit_nxt; neutral_max_limit <= #TCQ neutral_max_limit_nxt; one_dec_max_limit <= #TCQ one_dec_max_limit_nxt; two_dec_max_limit <= #TCQ two_dec_max_limit_nxt; three_dec_max_limit <= #TCQ three_dec_max_limit_nxt; three_inc_min_limit <= #TCQ three_inc_min_limit_nxt; two_inc_min_limit <= #TCQ two_inc_min_limit_nxt; one_inc_min_limit <= #TCQ one_inc_min_limit_nxt; neutral_min_limit <= #TCQ neutral_min_limit_nxt; one_dec_min_limit <= #TCQ one_dec_min_limit_nxt; two_dec_min_limit <= #TCQ two_dec_min_limit_nxt; three_dec_min_limit <= #TCQ three_dec_min_limit_nxt; four_dec_min_limit <= #TCQ four_dec_min_limit_nxt; device_temp_init <= #TCQ device_temp_init_nxt; tempmon_init_complete <= #TCQ tempmon_init_complete_nxt; tempmon_sample_en_101 <= #TCQ tempmon_sample_en; tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101; device_temp_101 <= #TCQ device_temp_100; device_temp_capture_102 <= #TCQ device_temp_capture_101; end end // Implement non-reset flops always @(posedge clk) begin temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101; temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101; temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101; temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101; temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101; temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101; temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101; temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101; temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101; temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101; temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101; temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101; temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101; temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101; temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101; temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101; update_temp_102 <= #TCQ update_temp_101; end endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 4.0 // \ \ Application : MIG // / / Filename : ddr_phy_top.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Aug 03 2009 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Top level memory interface block. Instantiates a clock // and reset generator, the memory controller, the phy and // the user interface blocks. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_ddr_phy_top # ( parameter TCQ = 100, // Register delay (simulation only) parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3 parameter AL = "0", // Additive Latency option parameter BANK_WIDTH = 3, // # of bank bits parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory parameter CL = 5, parameter COL_WIDTH = 12, // column address width parameter CS_WIDTH = 1, // # of unique CS outputs parameter CKE_WIDTH = 1, // # of cke outputs parameter CWL = 5, parameter DM_WIDTH = 8, // # of DM (data mask) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", // five fields, one per possible I/O bank, 4 bits in each field, // 1 per lane data=1/ctl=0 parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, // defines the byte lanes in I/O banks being used in the interface // 1- Used, 0- Unused parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, // defines the bit lanes in I/O banks being used in the interface. Each // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // control/address/data pin mapping parameters parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // This parameter must be set based on memory clock frequency // It must be set to 4 for frequencies above 533 MHz?? (undecided) // and set to 2 for 533 MHz and below parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter OUTPUT_DRV = "HIGH", // to calib_top parameter REG_CTRL = "OFF", // to calib_top parameter RTT_NOM = "60", // to calib_top parameter RTT_WR = "120", // to calib_top parameter tCK = 2500, // pS parameter tRFC = 110000, // pS parameter tREFI = 7800000, // pS parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter WRLVL = "OFF", // to calib_top parameter DEBUG_PORT = "OFF", // to calib_top parameter RANKS = 4, parameter ODT_WIDTH = 1, parameter ROW_WIDTH = 16, // DRAM address bus width parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, // calibration Address. The address given below will be used for calibration // read and write operations. parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // Simulation /debug options parameter SIM_BYPASS_INIT_CAL = "OFF", // Parameter used to force skipping // or abbreviation of initialization // and calibration. Overrides // SIM_INIT_OPTION, SIM_CAL_OPTION, // and disables various other blocks //parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps //parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz) parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter RD_PATH_REG = 0, // optional registers in the read path // to MC for timing improvement. // =1 enabled, = 0 disabled parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering parameter TAPSPERKCLK = 56, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SKIP_CALIB = "FALSE", parameter FPGA_VOLT_TYPE = "N" ) ( input clk, // Fabric logic clock // To MC, calib_top, hard PHY input clk_div2, // mem_refclk divided by 2 for PI incdec input rst_div2, // reset in clk_div2 domain input clk_ref, // Idelay_ctrl reference clock // To hard PHY (external source) input freq_refclk, // To hard PHY for Phasers input mem_refclk, // Memory clock to hard PHY input pll_lock, // System PLL lock signal input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering input poc_sample_pd, // Tell POC how to avoid metastability. input error, // Support for TG error detect output rst_tg_mc, // Support for TG error detect input [11:0] device_temp, input tempmon_sample_en, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, input dbg_idel_down_all, input dbg_idel_down_cpt, input dbg_idel_up_all, input dbg_idel_up_cpt, input dbg_sel_all_idel_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input rst, input iddr_rst, input [7:0] slot_0_present, input [7:0] slot_1_present, // From MC input [nCK_PER_CLK-1:0] mc_ras_n, input [nCK_PER_CLK-1:0] mc_cas_n, input [nCK_PER_CLK-1:0] mc_we_n, input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, input mc_reset_n, input [1:0] mc_odt, input [nCK_PER_CLK-1:0] mc_cke, // AUX - For ODT and CKE assertion during reads and writes input [3:0] mc_aux_out0, input [3:0] mc_aux_out1, input mc_cmd_wren, input mc_ctl_wren, input [2:0] mc_cmd, input [1:0] mc_cas_slot, input [5:0] mc_data_offset, input [5:0] mc_data_offset_1, input [5:0] mc_data_offset_2, input [1:0] mc_rank_cnt, // Write input mc_wrdata_en, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask, input idle, // DDR bus signals output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CK_WIDTH-1:0] ddr_ck_n, output [CK_WIDTH-1:0] ddr_ck, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_ras_n, output ddr_reset_n, output ddr_parity, output ddr_we_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs_n, inout [DQS_WIDTH-1:0] ddr_dqs, // Ports to be used when SKIP_CALIB="TRUE" output calib_tap_req, input [6:0] calib_tap_addr, input calib_tap_load, input [7:0] calib_tap_val, input calib_tap_load_done, //phase shift clock control output psen, output psincdec, input psdone, // Debug Port Outputs output [255:0] dbg_calib_top, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, output [255:0] dbg_phy_rdlvl, output [99:0] dbg_phy_wrcal, output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, output dbg_rddata_valid, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [1:0] dbg_rdlvl_start, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output dbg_wrlvl_done, output dbg_wrlvl_err, output dbg_wrlvl_start, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl, output dbg_pi_phaselock_start, output dbg_pi_phaselocked_done, output dbg_pi_phaselock_err, output [11:0] dbg_pi_phase_locked_phy4lanes, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_pi_dqsfound_err, output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrcal_err, output [1023:0] dbg_poc, // FIFO status flags output phy_mc_ctl_full, output phy_mc_cmd_full, output phy_mc_data_full, // Calibration status and resultant outputs output init_calib_complete, output init_wrcal_complete, output [6*RANKS-1:0] calib_rd_data_offset_0, output [6*RANKS-1:0] calib_rd_data_offset_1, output [6*RANKS-1:0] calib_rd_data_offset_2, output phy_rddata_valid, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, output ref_dll_lock, input rst_phaser_ref, output [6*RANKS-1:0] dbg_rd_data_offset, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [5:0] dbg_pi_counter_read_val, output [8:0] dbg_po_counter_read_val, output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps ); // Calculate number of slots in the system localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Parameter used to force skipping or abbreviation of initialization // and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and // disables various other blocks depending on the option selected // This option should only be used during simulation. In the case of // the "SKIP" option, the testbench used should also not be modeling // propagation delays. // Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"} // "NONE" = options determined by the individual parameter settings // "SIM_FULL" = skip power-up delay. FULL calibration performed without // averaging algorithm turned ON during window detection. // "SKIP" = skip power-up delay. Skip calibration not yet supported. // "FAST" = skip power-up delay, and calibrate (read leveling, write // leveling, and phase detector) only using one DQS group, and // apply the results to all other DQS groups. localparam SIM_INIT_OPTION = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" : ((SIM_BYPASS_INIT_CAL == "FAST") || (SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" : "NONE"); localparam SIM_CAL_OPTION = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" : (SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" : ((SIM_BYPASS_INIT_CAL == "SIM_FULL") || (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" : "NONE"); localparam WRLVL_W = (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL; localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))); localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0; localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0; localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0; localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 : BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 : 0; localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 : BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 : 0; localparam HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))); localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) + (0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) + (0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) + (0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) + ((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) + (0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) + (0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) + (0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) + ((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) + (0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) + (0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) + (0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) + ((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) + (0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) + (0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) + (0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) + ((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) + (0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) + (0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) + (0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])); // Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank // This should be the case since the PLL should be placed adjacent // to the same IO Bank as Ck/Addr/Cmd and Control localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) | ((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | ((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ? 3'b000 : (((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ? 3'b001 : (((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ? 3'b010 : (((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ? 3'b011 : (((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) | ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) | ((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ? 3'b100 : 3'b000; localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? 8'b00_10_01_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_11_01_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_11_10_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_11_10_01 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ? 8'b00_00_01_00 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_00_11_00 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_00_11_10 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? 8'b00_00_10_01 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_00_11_01 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? 8'b00_00_10_00 : 8'b11_10_01_00; localparam PI_DIV2_INCDEC = (DRAM_TYPE == "DDR2") ? "FALSE" : (((FPGA_VOLT_TYPE == "L") && (nCK_PER_CLK == 4)) ? "TRUE" : "FALSE"); wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data; wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out; wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk; wire phy_mc_go; wire phy_ctl_full; wire phy_cmd_full; wire phy_data_full; wire phy_pre_data_a_full; wire if_empty /* synthesis syn_maxfan = 3 */; wire phy_write_calib; wire phy_read_calib; wire [HIGHEST_BANK-1:0] rst_stg1_cal; wire [5:0] calib_sel; wire calib_in_common /* synthesis syn_maxfan = 10 */; wire [HIGHEST_BANK-1:0] calib_zero_inputs; wire [HIGHEST_BANK-1:0] calib_zero_ctrl; wire pi_phase_locked; wire pi_phase_locked_all; wire pi_found_dqs; wire pi_dqs_found_all; wire pi_dqs_out_of_range; wire pi_enstg2_f; wire pi_stg2_fincdec; wire pi_stg2_load; wire [5:0] pi_stg2_reg_l; wire idelay_ce; wire idelay_inc; wire idelay_ld; wire [2:0] po_sel_stg2stg3; wire [2:0] po_stg2_cincdec; wire [2:0] po_enstg2_c; wire [2:0] po_stg2_fincdec; wire [2:0] po_enstg2_f; wire [8:0] po_counter_read_val; wire [5:0] pi_counter_read_val; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata; reg [nCK_PER_CLK-1:0] parity; wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address; wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n; wire [nCK_PER_CLK-1:0] phy_ras_n; wire [nCK_PER_CLK-1:0] phy_cas_n; wire [nCK_PER_CLK-1:0] phy_we_n; wire phy_reset_n; wire [3:0] calib_aux_out; wire [nCK_PER_CLK-1:0] calib_cke; wire [1:0] calib_odt; wire calib_ctl_wren; wire calib_cmd_wren; wire calib_wrdata_en; wire [2:0] calib_cmd; wire [1:0] calib_seq; wire [5:0] calib_data_offset_0; wire [5:0] calib_data_offset_1; wire [5:0] calib_data_offset_2; wire [1:0] calib_rank_cnt; wire [1:0] calib_cas_slot; wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address; wire [3:0] mux_aux_out; wire [3:0] aux_out_map; wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank; wire [2:0] mux_cmd; wire mux_cmd_wren; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n; wire mux_ctl_wren; wire [1:0] mux_cas_slot; wire [5:0] mux_data_offset; wire [5:0] mux_data_offset_1; wire [5:0] mux_data_offset_2; wire [nCK_PER_CLK-1:0] mux_ras_n; wire [nCK_PER_CLK-1:0] mux_cas_n; wire [1:0] mux_rank_cnt; wire mux_reset_n; wire [nCK_PER_CLK-1:0] mux_we_n; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata; wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask; wire mux_wrdata_en; wire [nCK_PER_CLK-1:0] mux_cke ; wire [1:0] mux_odt ; wire phy_if_empty_def; wire phy_if_reset; wire phy_init_data_sel; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map; wire phy_rddata_valid_w; reg rddata_valid_reg; reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg; wire [4:0] idelaye2_init_val; wire [5:0] oclkdelay_init_val; wire po_counter_load_en; wire [DQS_CNT_WIDTH:0] byte_sel_cnt; wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb; wire fine_delay_sel; wire pd_out; //*************************************************************************** assign dbg_rddata_valid = rddata_valid_reg; assign dbg_rddata = rd_data_reg; assign dbg_rd_data_offset = calib_rd_data_offset_0; assign dbg_pi_phaselocked_done = pi_phase_locked_all; assign dbg_po_counter_read_val = po_counter_read_val; assign dbg_pi_counter_read_val = pi_counter_read_val; //*************************************************************************** //*************************************************************************** // Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec //*************************************************************************** //localparam PI_DIV2_INCDEC = "TRUE"; wire pi_fine_enable; wire pi_fine_inc; wire pi_counter_load_en; wire [5:0] pi_counter_load_val; wire [HIGHEST_BANK-1:0] pi_rst_dqs_find; generate if (PI_DIV2_INCDEC == "TRUE") begin: div2_incdec // 3-stage synchronizer registers (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r1; (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r2; (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r3; (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r1; (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r2; (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r3; (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r1; (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r2; (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r3; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r1; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r2; (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r1; (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r2; (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r3; reg pi_stg2_fine_enable, pi_stg2_fine_enable_r1; reg pi_stg2_fine_inc, pi_stg2_fine_inc_r1; reg pi_stg2_load_en, pi_stg2_load_en_r1; reg [5:0] pi_stg2_load_val; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] pi_dqs_find_rst; // 3-stage synchronizer always @(posedge clk_div2) begin //Phaser_In fine enable pi_enstg2_f_div2r1 <= #TCQ pi_enstg2_f; pi_enstg2_f_div2r2 <= #TCQ pi_enstg2_f_div2r1; pi_enstg2_f_div2r3 <= #TCQ pi_enstg2_f_div2r2; //Phaser_In fine incdec pi_stg2_fincdec_div2r1 <= #TCQ pi_stg2_fincdec; pi_stg2_fincdec_div2r2 <= #TCQ pi_stg2_fincdec_div2r1; pi_stg2_fincdec_div2r3 <= #TCQ pi_stg2_fincdec_div2r2; //Phaser_In stage2 load pi_stg2_load_div2r1 <= #TCQ pi_stg2_load; pi_stg2_load_div2r2 <= #TCQ pi_stg2_load_div2r1; pi_stg2_load_div2r3 <= #TCQ pi_stg2_load_div2r2; //Phaser_In stage2 load value pi_stg2_reg_l_div2r1 <= #TCQ pi_stg2_reg_l; pi_stg2_reg_l_div2r2 <= #TCQ pi_stg2_reg_l_div2r1; pi_stg2_reg_l_div2r3 <= #TCQ pi_stg2_reg_l_div2r2; //Phaser_In reset DQSFOUND rst_stg1_cal_div2r1 <= #TCQ rst_stg1_cal; rst_stg1_cal_div2r2 <= #TCQ rst_stg1_cal_div2r1; pi_dqs_find_rst <= #TCQ rst_stg1_cal_div2r2; end always @(posedge clk_div2) begin pi_stg2_fine_enable_r1 <= #TCQ pi_stg2_fine_enable; pi_stg2_fine_inc_r1 <= #TCQ pi_stg2_fine_inc; pi_stg2_load_en_r1 <= #TCQ pi_stg2_load_en; end always @(posedge clk_div2) begin if (rst_div2 || pi_stg2_fine_enable || pi_stg2_fine_enable_r1) pi_stg2_fine_enable <= #TCQ 1'b0; else if (pi_enstg2_f_div2r3) pi_stg2_fine_enable <= #TCQ 1'b1; end always @(posedge clk_div2) begin if (rst_div2 || pi_stg2_fine_inc || pi_stg2_fine_inc_r1) pi_stg2_fine_inc <= #TCQ 1'b0; else if (pi_stg2_fincdec_div2r3) pi_stg2_fine_inc <= #TCQ 1'b1; end always @(posedge clk_div2) begin if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1) pi_stg2_load_en <= #TCQ 1'b0; else if (pi_stg2_load_div2r3) pi_stg2_load_en <= #TCQ 1'b1; end always @(posedge clk_div2) begin if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1) pi_stg2_load_val <= #TCQ 6'd0; else if (pi_stg2_load_div2r3) pi_stg2_load_val <= #TCQ pi_stg2_reg_l_div2r3; end assign pi_fine_enable = pi_stg2_fine_enable; assign pi_fine_inc = pi_stg2_fine_inc; assign pi_counter_load_en = pi_stg2_load_en; assign pi_counter_load_val = pi_stg2_load_val; assign pi_rst_dqs_find = pi_dqs_find_rst; end else begin: div4_incdec assign pi_fine_enable = pi_enstg2_f; assign pi_fine_inc = pi_stg2_fincdec; assign pi_counter_load_en = pi_stg2_load; assign pi_counter_load_val = pi_stg2_reg_l; assign pi_rst_dqs_find = rst_stg1_cal; end endgenerate genvar i; generate for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i]; assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1]; end endgenerate //*************************************************************************** // During memory initialization and calibration the calibration logic drives // the memory signals. After calibration is complete the memory controller // drives the memory signals. // Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps //*************************************************************************** wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ; genvar v ; generate if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin assign mc_cs_n_temp[v] = mc_cs_n[v] ; end else begin assign mc_cs_n_temp[v] = 'b1 ; end end end else begin assign mc_cs_n_temp = mc_cs_n ; end endgenerate assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata; assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0; assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address; assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank; assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n; assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n; assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n; assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n; assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n; assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out; assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ; assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ; assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren : calib_cmd_wren; assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren : calib_ctl_wren; assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en : calib_wrdata_en; assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd; assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot; assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset : calib_data_offset_0; assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 : calib_data_offset_1; assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 : calib_data_offset_2; // Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601 assign mux_rank_cnt = 2'b00; // Assigning cke & odt for DDR2 & DDR3 // No changes for DDR3 & DDR2 dual rank // DDR2 single rank systems might potentially need 3 odt signals. // Aux_out[2] will have the odt toggled by phy and controller // wiring aux_out[2] to 0 & 3. Depending upon the odt parameter // all of the three odt bits or some of them might be used. // mapping done in mc_phy_wrapper module generate if(CKE_ODT_AUX == "TRUE") begin assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ? {mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} : mux_aux_out; end else begin assign aux_out_map = 4'b0000 ; end endgenerate assign init_calib_complete = phy_init_data_sel; assign phy_mc_ctl_full = phy_ctl_full; assign phy_mc_cmd_full = phy_cmd_full; assign phy_mc_data_full = phy_pre_data_a_full; //*************************************************************************** // Generate parity for DDR3 RDIMM. //*************************************************************************** generate if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity if (nCK_PER_CLK == 4) begin always @(posedge clk) begin parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3], mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3], mux_cas_n[3], mux_ras_n[3], mux_we_n[3]}); end always @(*) begin parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0], mux_cas_n[0],mux_ras_n[0], mux_we_n[0]}); parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2], mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2], mux_cas_n[2],mux_ras_n[2], mux_we_n[2]}); end end else begin always @(posedge clk) begin parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); end always @(*) begin parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0], mux_cas_n[0], mux_ras_n[0], mux_we_n[0]}); end end end else begin: gen_ddr3_noparity if (nCK_PER_CLK == 4) begin always @(posedge clk) begin parity[0] <= #TCQ 1'b0; parity[1] <= #TCQ 1'b0; parity[2] <= #TCQ 1'b0; parity[3] <= #TCQ 1'b0; end end else begin always @(posedge clk) begin parity[0] <= #TCQ 1'b0; parity[1] <= #TCQ 1'b0; end end end endgenerate //*************************************************************************** // Code for optional register stage in read path to MC for timing //*************************************************************************** generate if(RD_PATH_REG == 1)begin:RD_REG_TIMING always @(posedge clk)begin rddata_valid_reg <= #TCQ phy_rddata_valid_w; rd_data_reg <= #TCQ rd_data_map; end // always @ (posedge clk) end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING always @(phy_rddata_valid_w or rd_data_map)begin rddata_valid_reg = phy_rddata_valid_w; rd_data_reg = rd_data_map; end end endgenerate assign phy_rddata_valid = rddata_valid_reg; assign phy_rd_data = rd_data_reg; //*************************************************************************** // Hard PHY and accompanying bit mapping logic //*************************************************************************** mig_7series_v4_0_ddr_mc_phy_wrapper # ( .TCQ (TCQ), .tCK (tCK), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .BANK_WIDTH (BANK_WIDTH), .CKE_WIDTH (CKE_WIDTH), .CS_WIDTH (CS_WIDTH), .CK_WIDTH (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .CWL (CWL), .DM_WIDTH (DM_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .REG_CTRL (REG_CTRL), .ROW_WIDTH (ROW_WIDTH), .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .IBUF_LPWR_MODE (IBUF_LPWR_MODE), .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .HIGHEST_BANK (HIGHEST_BANK), .HIGHEST_LANE (HIGHEST_LANE), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CKE_ODT_AUX (CKE_ODT_AUX), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .SIM_CAL_OPTION (SIM_CAL_OPTION), .MASTER_PHY_CTL (MASTER_PHY_CTL), .DRAM_WIDTH (DRAM_WIDTH), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_mc_phy_wrapper ( .rst (rst), .iddr_rst (iddr_rst), .clk (clk), .clk_div2 (clk_div2), // For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk // For memory frequencies below 400 MHz mem_refclk = mem_refclk and // freq_refclk = 2x or 4x mem_refclk such that it remains in the // 400~1066 MHz range .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .mmcm_ps_clk (mmcm_ps_clk), .pll_lock (pll_lock), .sync_pulse (sync_pulse), .idelayctrl_refclk (clk_ref), .phy_cmd_wr_en (mux_cmd_wren), .phy_data_wr_en (mux_wrdata_en), // phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23], // DataOffset[22:17],HiIndex[16:15],LowIndex[14:12], // AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]} // The fields ACTPRE, and BankCount are only used // when the hard PHY counters are used by the MC. .phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset, mux_rank_cnt, 3'd0, aux_out_map, 5'd0, mux_cmd}), .phy_ctl_wr (mux_ctl_wren), .phy_if_empty_def (phy_if_empty_def), .phy_if_reset (phy_if_reset), .data_offset_1 (mux_data_offset_1), .data_offset_2 (mux_data_offset_2), .aux_in_1 (aux_out_map), .aux_in_2 (aux_out_map), .idelaye2_init_val (idelaye2_init_val), .oclkdelay_init_val (oclkdelay_init_val), .if_empty (if_empty), .phy_ctl_full (phy_ctl_full), .phy_cmd_full (phy_cmd_full), .phy_data_full (phy_data_full), .phy_pre_data_a_full (phy_pre_data_a_full), .ddr_clk (ddr_clk), .phy_mc_go (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .po_fine_enable (po_enstg2_f), .po_coarse_enable (po_enstg2_c), .po_fine_inc (po_stg2_fincdec), .po_coarse_inc (po_stg2_cincdec), .po_counter_load_en (po_counter_load_en), .po_counter_read_en (1'b1), .po_sel_fine_oclk_delay (po_sel_stg2stg3), .po_counter_load_val (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_load_val (pi_counter_load_val), .pi_counter_read_val (pi_counter_read_val), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .idelay_ld (idelay_ld), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (pi_found_dqs), .pi_dqs_found_all (pi_dqs_found_all), // Currently not being used. May be used in future if periodic reads // become a requirement. This output could also be used to signal a // catastrophic failure in read capture and the need for re-cal .pi_dqs_out_of_range (pi_dqs_out_of_range), .phy_init_data_sel (phy_init_data_sel), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .mux_address (mux_address), .mux_bank (mux_bank), .mux_cs_n (mux_cs_n), .mux_ras_n (mux_ras_n), .mux_cas_n (mux_cas_n), .mux_we_n (mux_we_n), .mux_reset_n (mux_reset_n), .parity_in (parity), .mux_wrdata (mux_wrdata), .mux_wrdata_mask (mux_wrdata_mask), .mux_odt (mux_odt), .mux_cke (mux_cke), .idle (idle), .rd_data (rd_data_map), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_odt (ddr_odt), .ddr_parity (ddr_parity), .ddr_ras_n (ddr_ras_n), .ddr_we_n (ddr_we_n), .ddr_dq (ddr_dq), .ddr_dqs (ddr_dqs), .ddr_dqs_n (ddr_dqs_n), .ddr_reset_n (ddr_reset_n), .dbg_pi_counter_read_en (1'b1), .ref_dll_lock (ref_dll_lock), .rst_phaser_ref (rst_phaser_ref), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .byte_sel_cnt (byte_sel_cnt), .pd_out (pd_out), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel) ); //*************************************************************************** // Soft memory initialization and calibration logic //*************************************************************************** mig_7series_v4_0_ddr_calib_top # ( .TCQ (TCQ), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .nCK_PER_CLK (nCK_PER_CLK), .PRE_REV3ES (PRE_REV3ES), .tCK (tCK), .CLK_PERIOD (CLK_PERIOD), .N_CTL_LANES (N_CTL_LANES), .CTL_BYTE_LANE (CTL_BYTE_LANE), .CTL_BANK (CTL_BANK), .DRAM_TYPE (DRAM_TYPE), .PRBS_WIDTH (8), .DQS_BYTE_MAP (DQS_BYTE_MAP), .HIGHEST_BANK (HIGHEST_BANK), .BANK_TYPE (BANK_TYPE), .HIGHEST_LANE (HIGHEST_LANE), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .SLOT_1_CONFIG (SLOT_1_CONFIG), .BANK_WIDTH (BANK_WIDTH), .CA_MIRROR (CA_MIRROR), .COL_WIDTH (COL_WIDTH), .CKE_ODT_AUX (CKE_ODT_AUX), .nCS_PER_RANK (nCS_PER_RANK), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .ROW_WIDTH (ROW_WIDTH), .RANKS (RANKS), .CS_WIDTH (CS_WIDTH), .CKE_WIDTH (CKE_WIDTH), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .PER_BIT_DESKEW ("OFF"), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .AL (AL), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .nCL (CL), .nCWL (CWL), .tRFC (tRFC), .tREFI (tREFI), .OUTPUT_DRV (OUTPUT_DRV), .REG_CTRL (REG_CTRL), .ADDR_CMD_MODE (ADDR_CMD_MODE), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .WRLVL (WRLVL_W), .USE_ODT_PORT (USE_ODT_PORT), .SIM_INIT_OPTION (SIM_INIT_OPTION), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DEBUG_PORT (DEBUG_PORT), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .TAPSPERKCLK (TAPSPERKCLK), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SKIP_CALIB (SKIP_CALIB), .PI_DIV2_INCDEC (PI_DIV2_INCDEC) ) u_ddr_calib_top ( .clk (clk), .rst (rst), .tg_err (error), .rst_tg_mc (rst_tg_mc), .slot_0_present (slot_0_present), .slot_1_present (slot_1_present), // PHY Control Block and IN_FIFO status .phy_ctl_ready (phy_mc_go), .phy_ctl_full (1'b0), .phy_cmd_full (1'b0), .phy_data_full (1'b0), .phy_if_empty (if_empty), .idelaye2_init_val (idelaye2_init_val), .oclkdelay_init_val (oclkdelay_init_val), // From calib logic To data IN_FIFO // DQ IDELAY tap value from Calib logic // port to be added to mc_phy by Gary .dlyval_dq (), // hard PHY calibration modes .write_calib (phy_write_calib), .read_calib (phy_read_calib), // DQS count and ck/addr/cmd to be mapped to calib_sel // based on parameter that defines placement of ctl lanes // and DQS byte groups in each bank. When phy_write_calib // is de-asserted calib_sel should select CK/addr/cmd/ctl. .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .phy_if_empty_def (phy_if_empty_def), .phy_if_reset (phy_if_reset), // Signals from calib logic to be MUXED with MC // signals before sending to hard PHY .calib_ctl_wren (calib_ctl_wren), .calib_cmd_wren (calib_cmd_wren), .calib_seq (calib_seq), .calib_aux_out (calib_aux_out), .calib_odt (calib_odt), .calib_cke (calib_cke), .calib_cmd (calib_cmd), .calib_wrdata_en (calib_wrdata_en), .calib_rank_cnt (calib_rank_cnt), .calib_cas_slot (calib_cas_slot), .calib_data_offset_0 (calib_data_offset_0), .calib_data_offset_1 (calib_data_offset_1), .calib_data_offset_2 (calib_data_offset_2), .phy_reset_n (phy_reset_n), .phy_address (phy_address), .phy_bank (phy_bank), .phy_cs_n (phy_cs_n), .phy_ras_n (phy_ras_n), .phy_cas_n (phy_cas_n), .phy_we_n (phy_we_n), .phy_wrdata (phy_wrdata), // DQS Phaser_IN calibration/status signals .pi_phaselocked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_found_dqs (pi_found_dqs), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), .pi_rst_stg1_cal (rst_stg1_cal), .pi_en_stg2_f (pi_enstg2_f), .pi_stg2_f_incdec (pi_stg2_fincdec), .pi_stg2_load (pi_stg2_load), .pi_stg2_reg_l (pi_stg2_reg_l), .pi_counter_read_val (pi_counter_read_val), .device_temp (device_temp), .tempmon_sample_en (tempmon_sample_en), // IDELAY tap enable and inc signals .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .idelay_ld (idelay_ld), // DQS Phaser_OUT calibration/status signals .po_sel_stg2stg3 (po_sel_stg2stg3), .po_stg2_c_incdec (po_stg2_cincdec), .po_en_stg2_c (po_enstg2_c), .po_stg2_f_incdec (po_stg2_fincdec), .po_en_stg2_f (po_enstg2_f), .po_counter_load_en (po_counter_load_en), .po_counter_read_val (po_counter_read_val), // From data IN_FIFO To Calib logic and MC/UI .phy_rddata (rd_data_map), // From calib logic To MC .phy_rddata_valid (phy_rddata_valid_w), .calib_rd_data_offset_0 (calib_rd_data_offset_0), .calib_rd_data_offset_1 (calib_rd_data_offset_1), .calib_rd_data_offset_2 (calib_rd_data_offset_2), .calib_writes (), // Mem Init and Calibration status To MC .init_calib_complete (phy_init_data_sel), .init_wrcal_complete (init_wrcal_complete), // Debug Error signals .pi_phase_locked_err (dbg_pi_phaselock_err), .pi_dqsfound_err (dbg_pi_dqsfound_err), .wrcal_err (dbg_wrcal_err), //used for oclk stg3 centering .pd_out (pd_out), .psen (psen), .psincdec (psincdec), .psdone (psdone), .poc_sample_pd (poc_sample_pd), .calib_tap_req (calib_tap_req), .calib_tap_addr (calib_tap_addr), .calib_tap_load (calib_tap_load), .calib_tap_val (calib_tap_val), .calib_tap_load_done (calib_tap_load_done), // Debug Signals .dbg_pi_phaselock_start (dbg_pi_phaselock_start), .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_wrcal_start (dbg_wrcal_start), .dbg_wrcal_done (dbg_wrcal_done), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_sel_pi_incdec (dbg_sel_pi_incdec), .dbg_sel_po_incdec (dbg_sel_po_incdec), .dbg_byte_sel (dbg_byte_sel), .dbg_pi_f_inc (dbg_pi_f_inc), .dbg_pi_f_dec (dbg_pi_f_dec), .dbg_po_f_inc (dbg_po_f_inc), .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), .dbg_po_f_dec (dbg_po_f_dec), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_calib_top (dbg_calib_top), .dbg_phy_init (dbg_phy_init), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .dbg_dqs_found_cal (dbg_dqs_found_cal), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), .dbg_poc (dbg_poc[1023:0]), .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), .byte_sel_cnt (byte_sel_cnt), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_wrcal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Write calibration logic to align DQS to correct CK edge //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_wrcal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 2500, parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps ) ( input clk, input rst, // Calibration status, control signals input wrcal_start, input wrcal_rd_wait, input wrcal_sanity_chk, input dqsfound_retry_done, input phy_rddata_en, output dqsfound_retry, output wrcal_read_req, output reg wrcal_act_req, output reg wrcal_done, output reg wrcal_pat_err, output reg wrcal_prech_req, output reg temp_wrcal_done, output reg wrcal_sanity_chk_done, input prech_done, // Captured data in resync clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Write level values of Phaser_Out coarse and fine // delay taps required to load Phaser_Out register input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, input wrlvl_byte_done, output reg wrlvl_byte_redo, output reg early1_data, output reg early2_data, // DQ IDELAY output reg idelay_ld, output reg wrcal_pat_resume, // to phy_init for write output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, output phy_if_reset, // Debug Port output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal ); // Length of calibration sequence (in # of words) //localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; // # of reads for reliable read capture localparam NUM_READS = 2; // # of cycles to wait after changing RDEN count value localparam RDEN_WAIT_CNT = 12; localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; localparam CAL2_IDLE = 4'h0; localparam CAL2_READ_WAIT = 4'h1; localparam CAL2_NEXT_DQS = 4'h2; localparam CAL2_WRLVL_WAIT = 4'h3; localparam CAL2_IFIFO_RESET = 4'h4; localparam CAL2_DQ_IDEL_DEC = 4'h5; localparam CAL2_DONE = 4'h6; localparam CAL2_SANITY_WAIT = 4'h7; localparam CAL2_ERR = 4'h8; integer i,j,k,l,m,p,q,d; reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; reg [4:0] not_empty_wait_cnt; reg [3:0] tap_inc_wait_cnt; reg cal2_done_r; reg cal2_done_r1; reg cal2_prech_req_r; reg [3:0] cal2_state_r; reg [3:0] cal2_state_r1; reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; reg cal2_if_reset; reg wrcal_pat_resume_r; reg wrcal_pat_resume_r1; reg wrcal_pat_resume_r2; reg wrcal_pat_resume_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg pat_data_match_r; reg pat1_data_match_r; reg pat1_data_match_r1; reg pat2_data_match_r; reg pat_data_match_valid_r; wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; reg [DRAM_WIDTH-1:0] pat_match_fall0_r; reg pat_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall1_r; reg pat_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall2_r; reg pat_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall3_r; reg pat_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise0_r; reg pat_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise1_r; reg pat_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise2_r; reg pat_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise3_r; reg pat_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; reg pat1_match_rise0_and_r; reg pat1_match_rise1_and_r; reg pat1_match_fall0_and_r; reg pat1_match_fall1_and_r; reg pat2_match_rise0_and_r; reg pat2_match_rise1_and_r; reg pat2_match_fall0_and_r; reg pat2_match_fall1_and_r; reg early1_data_match_r; reg early1_data_match_r1; reg [DRAM_WIDTH-1:0] early1_match_fall0_r; reg early1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall1_r; reg early1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall2_r; reg early1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall3_r; reg early1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise0_r; reg early1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise1_r; reg early1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise2_r; reg early1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise3_r; reg early1_match_rise3_and_r; reg early2_data_match_r; reg [DRAM_WIDTH-1:0] early2_match_fall0_r; reg early2_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall1_r; reg early2_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall2_r; reg early2_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall3_r; reg early2_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise0_r; reg early2_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise1_r; reg early2_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise2_r; reg early2_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise3_r; reg early2_match_rise3_and_r; wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg rd_active_posedge_r; reg rd_active_r; reg rd_active_r1; reg rd_active_r2; reg rd_active_r3; reg rd_active_r4; reg rd_active_r5; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg wrlvl_byte_done_r; reg idelay_ld_done; reg pat1_detect; reg early1_detect; reg wrcal_sanity_chk_r; reg wrcal_sanity_chk_err; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < DQS_WIDTH; d = d + 1) begin po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; end end assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; assign dbg_phy_wrcal[0] = pat_data_match_r; assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; assign dbg_phy_wrcal[6] = wrcal_start; assign dbg_phy_wrcal[7] = wrcal_done; assign dbg_phy_wrcal[8] = pat_data_match_valid_r; assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; assign dbg_phy_wrcal[22] = early1_data; assign dbg_phy_wrcal[23] = early2_data; assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; assign dbg_phy_wrcal[88] = early1_data_match_r; assign dbg_phy_wrcal[89] = early2_data_match_r; assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; assign dqsfound_retry = 1'b0; assign wrcal_read_req = 1'b0; assign phy_if_reset = cal2_if_reset; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** always @(posedge clk) begin po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; end //*************************************************************************** // Data mux to route appropriate byte to calibration logic - i.e. calibration // is done sequentially, one byte (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate //************************************************************************** // Final Phaser OUT coarse and fine delay taps after write calibration // Sum of taps used during write leveling taps and write calibration //************************************************************************** always @(*) begin for (m = 0; m < DQS_WIDTH; m = m + 1) begin wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; end end always @(posedge clk) begin if (rst) begin for (p = 0; p < DQS_WIDTH; p = p + 1) begin po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; end end else if (cal2_done_r && ~cal2_done_r1) begin for (q = 0; q < DQS_WIDTH; q = q + 1) begin po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; end end end always @(posedge clk) begin rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end endgenerate //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) wrcal_prech_req <= #TCQ 1'b0; else // Combine requests from all stages here wrcal_prech_req <= #TCQ cal2_prech_req_r; //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; end end end endgenerate //*************************************************************************** // Write calibration: // During write leveling DQS is aligned to the nearest CK edge that may not // be the correct CK edge. Write calibration is required to align the DQS to // the correct CK edge that clocks the write command. // The Phaser_Out coarse delay line is adjusted if required to add a memory // clock cycle of delay in order to read back the expected pattern. //*************************************************************************** always @(posedge clk) begin rd_active_r <= #TCQ phy_rddata_en; rd_active_r1 <= #TCQ rd_active_r; rd_active_r2 <= #TCQ rd_active_r1; rd_active_r3 <= #TCQ rd_active_r2; rd_active_r4 <= #TCQ rd_active_r3; rd_active_r5 <= #TCQ rd_active_r4; end //***************************************************************** // Expected data pattern when properly received by read capture // logic: // Based on pattern of ({rise,fall}) = // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 // Each nibble will look like: // bit3: 1, 0, 1, 0, 0, 1, 1, 0 // bit2: 1, 0, 0, 1, 1, 0, 0, 1 // bit1: 1, 0, 1, 0, 0, 1, 0, 1 // bit0: 1, 0, 0, 1, 1, 0, 1, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // FF00AA5555AA9966 assign pat_rise0[3] = 1'b1; assign pat_fall0[3] = 1'b0; assign pat_rise1[3] = 1'b1; assign pat_fall1[3] = 1'b0; assign pat_rise2[3] = 1'b0; assign pat_fall2[3] = 1'b1; assign pat_rise3[3] = 1'b1; assign pat_fall3[3] = 1'b0; assign pat_rise0[2] = 1'b1; assign pat_fall0[2] = 1'b0; assign pat_rise1[2] = 1'b0; assign pat_fall1[2] = 1'b1; assign pat_rise2[2] = 1'b1; assign pat_fall2[2] = 1'b0; assign pat_rise3[2] = 1'b0; assign pat_fall3[2] = 1'b1; assign pat_rise0[1] = 1'b1; assign pat_fall0[1] = 1'b0; assign pat_rise1[1] = 1'b1; assign pat_fall1[1] = 1'b0; assign pat_rise2[1] = 1'b0; assign pat_fall2[1] = 1'b1; assign pat_rise3[1] = 1'b0; assign pat_fall3[1] = 1'b1; assign pat_rise0[0] = 1'b1; assign pat_fall0[0] = 1'b0; assign pat_rise1[0] = 1'b0; assign pat_fall1[0] = 1'b1; assign pat_rise2[0] = 1'b1; assign pat_fall2[0] = 1'b0; assign pat_rise3[0] = 1'b1; assign pat_fall3[0] = 1'b0; // Pattern to distinguish between early write and incorrect read // BB11EE4444EEDD88 assign early_rise0[3] = 1'b1; assign early_fall0[3] = 1'b0; assign early_rise1[3] = 1'b1; assign early_fall1[3] = 1'b0; assign early_rise2[3] = 1'b0; assign early_fall2[3] = 1'b1; assign early_rise3[3] = 1'b1; assign early_fall3[3] = 1'b1; assign early_rise0[2] = 1'b0; assign early_fall0[2] = 1'b0; assign early_rise1[2] = 1'b1; assign early_fall1[2] = 1'b1; assign early_rise2[2] = 1'b1; assign early_fall2[2] = 1'b1; assign early_rise3[2] = 1'b1; assign early_fall3[2] = 1'b0; assign early_rise0[1] = 1'b1; assign early_fall0[1] = 1'b0; assign early_rise1[1] = 1'b1; assign early_fall1[1] = 1'b0; assign early_rise2[1] = 1'b0; assign early_fall2[1] = 1'b1; assign early_rise3[1] = 1'b0; assign early_fall3[1] = 1'b0; assign early_rise0[0] = 1'b1; assign early_fall0[0] = 1'b1; assign early_rise1[0] = 1'b0; assign early_fall1[0] = 1'b0; assign early_rise2[0] = 1'b0; assign early_fall2[0] = 1'b0; assign early_rise3[0] = 1'b1; assign early_fall3[0] = 1'b0; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // First cycle pattern FF00AA55 assign pat1_rise0[3] = 1'b1; assign pat1_fall0[3] = 1'b0; assign pat1_rise1[3] = 1'b1; assign pat1_fall1[3] = 1'b0; assign pat1_rise0[2] = 1'b1; assign pat1_fall0[2] = 1'b0; assign pat1_rise1[2] = 1'b0; assign pat1_fall1[2] = 1'b1; assign pat1_rise0[1] = 1'b1; assign pat1_fall0[1] = 1'b0; assign pat1_rise1[1] = 1'b1; assign pat1_fall1[1] = 1'b0; assign pat1_rise0[0] = 1'b1; assign pat1_fall0[0] = 1'b0; assign pat1_rise1[0] = 1'b0; assign pat1_fall1[0] = 1'b1; // Second cycle pattern 55AA9966 assign pat2_rise0[3] = 1'b0; assign pat2_fall0[3] = 1'b1; assign pat2_rise1[3] = 1'b1; assign pat2_fall1[3] = 1'b0; assign pat2_rise0[2] = 1'b1; assign pat2_fall0[2] = 1'b0; assign pat2_rise1[2] = 1'b0; assign pat2_fall1[2] = 1'b1; assign pat2_rise0[1] = 1'b0; assign pat2_fall0[1] = 1'b1; assign pat2_rise1[1] = 1'b0; assign pat2_fall1[1] = 1'b1; assign pat2_rise0[0] = 1'b1; assign pat2_fall0[0] = 1'b0; assign pat2_rise1[0] = 1'b1; assign pat2_fall1[0] = 1'b0; //Pattern to distinguish between early write and incorrect read // First cycle pattern AA5555AA assign early1_rise0[3] = 2'b1; assign early1_fall0[3] = 2'b0; assign early1_rise1[3] = 2'b0; assign early1_fall1[3] = 2'b1; assign early1_rise0[2] = 2'b0; assign early1_fall0[2] = 2'b1; assign early1_rise1[2] = 2'b1; assign early1_fall1[2] = 2'b0; assign early1_rise0[1] = 2'b1; assign early1_fall0[1] = 2'b0; assign early1_rise1[1] = 2'b0; assign early1_fall1[1] = 2'b1; assign early1_rise0[0] = 2'b0; assign early1_fall0[0] = 2'b1; assign early1_rise1[0] = 2'b1; assign early1_fall1[0] = 2'b0; // Second cycle pattern 9966BB11 assign early2_rise0[3] = 2'b1; assign early2_fall0[3] = 2'b0; assign early2_rise1[3] = 2'b1; assign early2_fall1[3] = 2'b0; assign early2_rise0[2] = 2'b0; assign early2_fall0[2] = 2'b1; assign early2_rise1[2] = 2'b0; assign early2_fall1[2] = 2'b0; assign early2_rise0[1] = 2'b0; assign early2_fall0[1] = 2'b1; assign early2_rise1[1] = 2'b1; assign early2_fall1[1] = 2'b0; assign early2_rise0[0] = 2'b1; assign early2_fall0[0] = 2'b0; assign early2_rise1[0] = 2'b1; assign early2_fall1[0] = 2'b1; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) pat_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) pat_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) pat_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) pat_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) pat_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) pat_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) pat_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) pat_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) early1_match_rise2_r[pt_i] <= #TCQ 1'b1; else early1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) early1_match_fall2_r[pt_i] <= #TCQ 1'b1; else early1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) early1_match_rise3_r[pt_i] <= #TCQ 1'b1; else early1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) early1_match_fall3_r[pt_i] <= #TCQ 1'b1; else early1_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) early2_match_rise2_r[pt_i] <= #TCQ 1'b1; else early2_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) early2_match_fall2_r[pt_i] <= #TCQ 1'b1; else early2_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) early2_match_rise3_r[pt_i] <= #TCQ 1'b1; else early2_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) early2_match_fall3_r[pt_i] <= #TCQ 1'b1; else early2_match_fall3_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; pat_data_match_r <= #TCQ (pat_match_rise0_and_r && pat_match_fall0_and_r && pat_match_rise1_and_r && pat_match_fall1_and_r && pat_match_rise2_and_r && pat_match_fall2_and_r && pat_match_rise3_and_r && pat_match_fall3_and_r); pat_data_match_valid_r <= #TCQ rd_active_r3; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r && early1_match_rise2_and_r && early1_match_fall2_and_r && early1_match_rise3_and_r && early1_match_fall3_and_r); end always @(posedge clk) begin early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r && early2_match_rise2_and_r && early2_match_fall2_and_r && early2_match_rise3_and_r && early2_match_fall3_and_r); end end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // early2 in this case does not mean 2 cycles early but // the second cycle of read data in 2:1 mode always @(posedge clk) begin if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); pat1_data_match_r1 <= #TCQ pat1_data_match_r; pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && pat2_match_fall0_and_r && pat2_match_rise1_and_r && pat2_match_fall1_and_r); // For 2:1 mode, read valid is asserted for 2 clock cycles - // here we generate a "match valid" pulse that is only 1 clock // cycle wide that is simulatenous when the match calculation // is complete pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r); early1_data_match_r1 <= #TCQ early1_data_match_r; early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r); end end endgenerate // Need to delay it by 3 cycles in order to wait for Phaser_Out // coarse delay to take effect before issuing a write command always @(posedge clk) begin wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; end always @(posedge clk) begin if (rst) tap_inc_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || (cal2_state_r == CAL2_IFIFO_RESET) || (cal2_state_r == CAL2_SANITY_WAIT)) tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; else tap_inc_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst) not_empty_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; else not_empty_wait_cnt <= #TCQ 'd0; end always @(posedge clk) cal2_state_r1 <= #TCQ cal2_state_r; //***************************************************************** // Write Calibration state machine //***************************************************************** // when calibrating, check to see if the expected pattern is received. // Otherwise delay DQS to align to correct CK edge. // NOTES: // 1. An error condition can occur due to two reasons: // a. If the matching logic does not receive the expected data // pattern. However, the error may be "recoverable" because // the write calibration is still in progress. If an error is // found the write calibration logic delays DQS by an additional // clock cycle and restarts the pattern detection process. // By design, if the write path timing is incorrect, the correct // data pattern will never be detected. // b. Valid data not found even after incrementing Phaser_Out // coarse delay line. always @(posedge clk) begin if (rst) begin wrcal_dqs_cnt_r <= #TCQ 'b0; cal2_done_r <= #TCQ 1'b0; cal2_prech_req_r <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IDLE; wrcal_pat_err <= #TCQ 1'b0; wrcal_pat_resume_r <= #TCQ 1'b0; wrcal_act_req <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; temp_wrcal_done <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b0; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; idelay_ld <= #TCQ 1'b0; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; early1_detect <= #TCQ 1'b0; wrcal_sanity_chk_done <= #TCQ 1'b0; wrcal_sanity_chk_err <= #TCQ 1'b0; end else begin cal2_prech_req_r <= #TCQ 1'b0; case (cal2_state_r) CAL2_IDLE: begin wrcal_pat_err <= #TCQ 1'b0; if (wrcal_start) begin cal2_if_reset <= #TCQ 1'b0; if (SIM_CAL_OPTION == "SKIP_CAL") // If skip write calibration, then proceed to end. cal2_state_r <= #TCQ CAL2_DONE; else cal2_state_r <= #TCQ CAL2_READ_WAIT; end end // General wait state to wait for read data to be output by the // IN_FIFO CAL2_READ_WAIT: begin wrcal_pat_resume_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; // Wait until read data is received, and pattern matching // calculation is complete. NOTE: Need to add a timeout here // in case for some reason data is never received (or rather // the PHASER_IN and IN_FIFO think they never receives data) if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin if (pat_data_match_r) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else begin if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; // If writes are one or two cycles early then redo // write leveling for the byte else if (early1_data_match_r) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early2_data_match_r) begin early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b1; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin if ((pat1_data_match_r1 && pat2_data_match_r) || (pat1_detect && pat2_data_match_r)) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else if (pat1_data_match_r1 && ~pat2_data_match_r) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; pat1_detect <= #TCQ 1'b1; end else begin // If writes are one or two cycles early then redo // write leveling for the byte if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; else if ((early1_data_match_r1 && early2_data_match_r) || (early1_detect && early2_data_match_r)) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early1_data_match_r1 && ~early2_data_match_r) begin early1_detect <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (not_empty_wait_cnt == 'd31) cal2_state_r <= #TCQ CAL2_ERR; end CAL2_WRLVL_WAIT: begin early1_detect <= #TCQ 1'b0; if (wrlvl_byte_done && ~wrlvl_byte_done_r) wrlvl_byte_redo <= #TCQ 1'b0; if (wrlvl_byte_done) begin if (rd_active_r1 && ~rd_active_r) begin cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; end end end CAL2_DQ_IDEL_DEC: begin if (tap_inc_wait_cnt == 'd4) begin idelay_ld <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b1; end end CAL2_IFIFO_RESET: begin if (tap_inc_wait_cnt == 'd15) begin cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_DONE; else if (idelay_ld_done) begin wrcal_pat_resume_r <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end else cal2_state_r <= #TCQ CAL2_IDLE; end end // Final processing for current DQS group. Move on to next group CAL2_NEXT_DQS: begin // At this point, we've just found the correct pattern for the // current DQS group. // Request bank/row precharge, and wait for its completion. Always // precharge after each DQS group to avoid tRAS(max) violation //verilint STARC-2.2.3.3 off if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin cal2_prech_req_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_SANITY_WAIT; end else cal2_prech_req_r <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; if (prech_done) if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin // If either FAST_CAL is enabled and first DQS group is // finished, or if the last DQS group was just finished, // then end of write calibration if (wrcal_sanity_chk_r) begin cal2_if_reset <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; end else cal2_state_r <= #TCQ CAL2_DONE; end else begin // Continue to next DQS group wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end end //verilint STARC-2.2.3.3 on CAL2_SANITY_WAIT: begin if (tap_inc_wait_cnt == 'd15) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; wrcal_pat_resume_r <= #TCQ 1'b1; end end // Finished with read enable calibration CAL2_DONE: begin if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin cal2_done_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ 'd0; cal2_state_r <= #TCQ CAL2_IDLE; end else cal2_done_r <= #TCQ 1'b1; cal2_prech_req_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_done <= #TCQ 1'b1; end // Assert error signal indicating that writes timing is incorrect CAL2_ERR: begin wrcal_pat_resume_r <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_err <= #TCQ 1'b1; else wrcal_pat_err <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_ERR; end endcase end end // Delay assertion of wrcal_done for write calibration by a few cycles after // we've reached CAL2_DONE always @(posedge clk) if (rst) cal2_done_r1 <= #TCQ 1'b0; else cal2_done_r1 <= #TCQ cal2_done_r; always @(posedge clk) if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) wrcal_done <= #TCQ 1'b0; else if (cal2_done_r) wrcal_done <= #TCQ 1'b1; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_wrlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: Mon Jun 23 2008 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has a DFI interface for providing control/address and write // data to the rest of the PHY datapath during initialization/calibration. // Once initialization is complete, control is passed to the MC. // NOTES: // 1. Multiple CS (multi-rank) not supported // 2. DDR2 not supported // 3. ODT not supported //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.3 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_wrlvl # ( parameter TCQ = 100, parameter DQS_CNT_WIDTH = 3, parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 2, parameter DRAM_WIDTH = 8, parameter RANKS = 1, parameter nCK_PER_CLK = 4, parameter CLK_PERIOD = 4, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, input phy_ctl_ready, input wr_level_start, input wl_sm_start, input wrlvl_final, input wrlvl_byte_redo, input [DQS_CNT_WIDTH:0] wrcal_cnt, input early1_data, input early2_data, input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt, input oclkdelay_calib_done, input [(DQ_WIDTH)-1:0] rd_data_rise0, output reg wrlvl_byte_done, output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */, output phy_ctl_rdy_dly, output reg wr_level_done /* synthesis syn_maxfan = 2 */, // to phy_init for cs logic output wrlvl_rank_done, output done_dqs_tap_inc, output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt, // Fine delay line used only during write leveling // Inc/dec Phaser_Out fine delay line output reg dqs_po_stg2_f_incdec, // Enable Phaser_Out fine delay inc/dec output reg dqs_po_en_stg2_f, // Coarse delay line used during write leveling // only if 64 taps of fine delay line were not // sufficient to detect a 0->1 transition // Inc Phaser_Out coarse delay line output reg dqs_wl_po_stg2_c_incdec, // Enable Phaser_Out coarse delay inc/dec output reg dqs_wl_po_en_stg2_c, // Read Phaser_Out delay value input [8:0] po_counter_read_val, // output reg dqs_wl_po_stg2_load, // output reg [8:0] dqs_wl_po_stg2_reg_l, // CK edge undetected output reg wrlvl_err, output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt, // Debug ports output [5:0] dbg_wl_tap_cnt, output dbg_wl_edge_detect_valid, output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect, output [DQS_CNT_WIDTH:0] dbg_dqs_count, output [4:0] dbg_wl_state, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl ); localparam WL_IDLE = 5'h0; localparam WL_INIT = 5'h1; localparam WL_INIT_FINE_INC = 5'h2; localparam WL_INIT_FINE_INC_WAIT1= 5'h3; localparam WL_INIT_FINE_INC_WAIT = 5'h4; localparam WL_INIT_FINE_DEC = 5'h5; localparam WL_INIT_FINE_DEC_WAIT = 5'h6; localparam WL_FINE_INC = 5'h7; localparam WL_WAIT = 5'h8; localparam WL_EDGE_CHECK = 5'h9; localparam WL_DQS_CHECK = 5'hA; localparam WL_DQS_CNT = 5'hB; localparam WL_2RANK_TAP_DEC = 5'hC; localparam WL_2RANK_DQS_CNT = 5'hD; localparam WL_FINE_DEC = 5'hE; localparam WL_FINE_DEC_WAIT = 5'hF; localparam WL_CORSE_INC = 5'h10; localparam WL_CORSE_INC_WAIT = 5'h11; localparam WL_CORSE_INC_WAIT1 = 5'h12; localparam WL_CORSE_INC_WAIT2 = 5'h13; localparam WL_CORSE_DEC = 5'h14; localparam WL_CORSE_DEC_WAIT = 5'h15; localparam WL_CORSE_DEC_WAIT1 = 5'h16; localparam WL_FINE_INC_WAIT = 5'h17; localparam WL_2RANK_FINAL_TAP = 5'h18; localparam WL_INIT_FINE_DEC_WAIT1= 5'h19; localparam WL_FINE_DEC_WAIT1 = 5'h1A; localparam WL_CORSE_INC_WAIT_TMP = 5'h1B; localparam COARSE_TAPS = 7; localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48; localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2; localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5; integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y; reg phy_ctl_ready_r1; reg phy_ctl_ready_r2; reg phy_ctl_ready_r3; reg phy_ctl_ready_r4; reg phy_ctl_ready_r5; reg phy_ctl_ready_r6; (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r; reg [1:0] rank_cnt_r; reg [DQS_WIDTH-1:0] rd_data_rise_wl_r; reg [DQS_WIDTH-1:0] rd_data_previous_r; reg [DQS_WIDTH-1:0] rd_data_edge_detect_r; reg wr_level_done_r; reg wrlvl_rank_done_r; reg wr_level_start_r; reg [4:0] wl_state_r, wl_state_r1; reg inhibit_edge_detect_r; reg wl_edge_detect_valid_r; reg [5:0] wl_tap_count_r; reg [5:0] fine_dec_cnt; reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each reg [2:0] corse_dec[0:DQS_WIDTH-1]; reg [2:0] corse_inc[0:DQS_WIDTH-1]; reg dq_cnt_inc; reg [3:0] stable_cnt; reg flag_ck_negedge; //reg past_negedge; reg flag_init; reg [2:0] corse_cnt[0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] corse_cnt_dbg; reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1]; //reg [3*DQS_WIDTH-1:0] coarse_tap_inc; reg [2:0] final_coarse_tap[0:DQS_WIDTH-1]; reg [5:0] add_smallest[0:DQS_WIDTH-1]; reg [5:0] add_largest[0:DQS_WIDTH-1]; //reg [6*DQS_WIDTH-1:0] fine_tap_inc; //reg [6*DQS_WIDTH-1:0] fine_tap_dec; reg wr_level_done_r1; reg wr_level_done_r2; reg wr_level_done_r3; reg wr_level_done_r4; reg wr_level_done_r5; reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1]; reg [5:0] smallest[0:DQS_WIDTH-1]; reg [5:0] largest[0:DQS_WIDTH-1]; reg [5:0] final_val[0:DQS_WIDTH-1]; reg [5:0] po_dec_cnt[0:DQS_WIDTH-1]; reg done_dqs_dec; reg [8:0] po_rdval_cnt; reg po_cnt_dec; reg po_dec_done; reg dual_rnk_dec; wire [DQS_CNT_WIDTH+2:0] dqs_count_w; reg [5:0] fast_cal_fine_cnt; reg [2:0] fast_cal_coarse_cnt; reg wrlvl_byte_redo_r; reg [2:0] wrlvl_redo_corse_inc; reg wrlvl_final_r; reg final_corse_dec; wire [DQS_CNT_WIDTH+2:0] oclk_count_w; reg wrlvl_tap_done_r ; reg [3:0] wait_cnt; reg [3:0] incdec_wait_cnt; // Debug ports assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r; assign dbg_rd_data_edge_detect = rd_data_edge_detect_r; assign dbg_wl_tap_cnt = wl_tap_count_r; assign dbg_dqs_count = dqs_count_r; assign dbg_wl_state = wl_state_r; assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt; assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt; always @(*) begin for (v = 0; v < DQS_WIDTH; v = v + 1) corse_cnt_dbg[3*v+:3] = corse_cnt[v]; end assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg; assign dbg_phy_wrlvl[27+:5] = wl_state_r; assign dbg_phy_wrlvl[32+:4] = dqs_count_r; assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r; assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r; assign dbg_phy_wrlvl[54+:4] = stable_cnt; assign dbg_phy_wrlvl[58] = 'd0; assign dbg_phy_wrlvl[59] = flag_ck_negedge; assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r; assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r; assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r; assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt; assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt; //************************************************************************** // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay //************************************************************************** assign po_stg2_wl_cnt = dqs_count_r; assign wrlvl_rank_done = wrlvl_rank_done_r; assign done_dqs_tap_inc = done_dqs_dec; assign phy_ctl_rdy_dly = phy_ctl_ready_r6; always @(posedge clk) begin phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo; wrlvl_final_r <= #TCQ wrlvl_final; if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) wr_level_done <= #TCQ 1'b0; else wr_level_done <= #TCQ done_dqs_dec; end // Status signal that will be asserted once the first // pass of write leveling is done. always @(posedge clk) begin if(rst) begin wrlvl_tap_done_r <= #TCQ 1'b0 ; end else begin if(wrlvl_tap_done_r == 1'b0) begin if(oclkdelay_calib_done) begin wrlvl_tap_done_r <= #TCQ 1'b1 ; end end end end always @(posedge clk) begin if (rst || po_cnt_dec) wait_cnt <= #TCQ 'd8; else if (phy_ctl_ready_r6 && (wait_cnt > 'd0)) wait_cnt <= #TCQ wait_cnt - 1; end always @(posedge clk) begin if (rst) begin po_rdval_cnt <= #TCQ 'd0; end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin po_rdval_cnt <= #TCQ po_counter_read_val; end else if (po_rdval_cnt > 'd0) begin if (po_cnt_dec) po_rdval_cnt <= #TCQ po_rdval_cnt - 1; else po_rdval_cnt <= #TCQ po_rdval_cnt; end else if (po_rdval_cnt == 'd0) begin po_rdval_cnt <= #TCQ po_rdval_cnt; end end always @(posedge clk) begin if (rst || (po_rdval_cnt == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) po_dec_done <= #TCQ 1'b0; else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin po_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin dqs_po_dec_done <= #TCQ po_dec_done; wr_level_done_r1 <= #TCQ wr_level_done_r; wr_level_done_r2 <= #TCQ wr_level_done_r1; wr_level_done_r3 <= #TCQ wr_level_done_r2; wr_level_done_r4 <= #TCQ wr_level_done_r3; wr_level_done_r5 <= #TCQ wr_level_done_r4; for (l = 0; l < DQS_WIDTH; l = l + 1) begin wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l]; if ((RANKS == 1) || ~oclkdelay_calib_done) wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l]; else wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l]; end end generate if (RANKS == 2) begin: dual_rank always @(posedge clk) begin if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) done_dqs_dec <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done) done_dqs_dec <= #TCQ wr_level_done_r; else if (wr_level_done_r5 && (wl_state_r == WL_IDLE)) done_dqs_dec <= #TCQ 1'b1; end end else begin: single_rank always @(posedge clk) begin if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) done_dqs_dec <= #TCQ 1'b0; else if (~oclkdelay_calib_done) done_dqs_dec <= #TCQ wr_level_done_r; else if (wr_level_done_r3 && ~wr_level_done_r4) done_dqs_dec <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r)) wrlvl_byte_done <= #TCQ 1'b0; else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4) wrlvl_byte_done <= #TCQ 1'b1; // Storing DQS tap values at the end of each DQS write leveling always @(posedge clk) begin if (rst) begin for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop for (n = 0; n < DQS_WIDTH; n = n + 1) begin wl_corse_cnt[k][n] <= #TCQ 'b0; wl_dqs_tap_count_r[k][n] <= #TCQ 'b0; end end end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1) | (wl_state_r == WL_2RANK_TAP_DEC)) begin wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r; wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r]; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r; wl_corse_cnt[p][q] <= #TCQ corse_cnt[0]; end end end end // Convert coarse delay to fine taps in case of unequal number of coarse // taps between ranks. Assuming a difference of 1 coarse tap counts // between ranks. A common fine and coarse tap value must be used for both ranks // because Phaser_Out has only one rank register. // Coarse tap1 = period(ps)*93/360 = 34 fine taps // Other coarse taps = period(ps)*103/360 = 38 fine taps generate genvar cnt; if (RANKS == 2) begin // Dual rank for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt always @(posedge clk) begin if (rst) begin //coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0; add_smallest[cnt] <= #TCQ 'd0; add_largest[cnt] <= #TCQ 'd0; final_coarse_tap[cnt] <= #TCQ 'd0; end else if (wr_level_done_r1 & ~wr_level_done_r2) begin if (~oclkdelay_calib_done) begin for(y = 0 ; y < DQS_WIDTH; y = y+1) begin final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y]; add_smallest[y] <= #TCQ 'd0; add_largest[y] <= #TCQ 'd0; end end else if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin // Both ranks have use the same number of coarse delay taps. // No conversion of coarse tap to fine taps required. //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3]; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; add_smallest[cnt] <= #TCQ 'd0; add_largest[cnt] <= #TCQ 'd0; end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin // Rank 0 uses fewer coarse delay taps than rank1. // conversion of coarse tap to fine taps required for rank1. // The final coarse count will the smaller value. //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1; if (|wl_corse_cnt[0][cnt]) // Coarse tap 2 or higher being converted to fine taps // This will be added to 'largest' value in final_val // computation add_largest[cnt] <= #TCQ 'd38; else // Coarse tap 1 being converted to fine taps // This will be added to 'largest' value in final_val // computation add_largest[cnt] <= #TCQ 'd34; end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin // This may be an unlikely scenario in a real system. // Rank 0 uses more coarse delay taps than rank1. // conversion of coarse tap to fine taps required. //coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; if (|wl_corse_cnt[1][cnt]) // Coarse tap 2 or higher being converted to fine taps // This will be added to 'smallest' value in final_val // computation add_smallest[cnt] <= #TCQ 'd38; else // Coarse tap 1 being converted to fine taps // This will be added to 'smallest' value in // final_val computation add_smallest[cnt] <= #TCQ 'd34; end end end end end else begin // Single rank always @(posedge clk) begin //coarse_tap_inc <= #TCQ 'd0; for(w = 0; w < DQS_WIDTH; w = w + 1) begin final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w]; add_smallest[w] <= #TCQ 'd0; add_largest[w] <= #TCQ 'd0; end end end endgenerate // Determine delay value for DQS in multirank system // Assuming delay value is the smallest for rank 0 DQS // and largest delay value for rank 4 DQS // Set to smallest + ((largest-smallest)/2) always @(posedge clk) begin if (rst) begin for(x = 0; x < DQS_WIDTH; x = x +1) begin smallest[x] <= #TCQ 'b0; largest[x] <= #TCQ 'b0; end end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_2RANK_TAP_DEC)) begin smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r]; end else if (((SIM_CAL_OPTION == "FAST_CAL") | (~oclkdelay_calib_done & ~wrlvl_byte_redo)) & wr_level_done_r1 & ~wr_level_done_r2) begin for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; largest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; end end end // final_val to be used for all DQSs in all ranks genvar wr_i; generate for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap always @(posedge clk) begin if (rst) final_val[wr_i] <= #TCQ 'b0; else if (wr_level_done_r2 && ~wr_level_done_r3) begin if (~oclkdelay_calib_done) final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]); else if ((smallest[wr_i] + add_smallest[wr_i]) < (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) + (((largest[wr_i] + add_largest[wr_i]) - (smallest[wr_i] + add_smallest[wr_i]))/2)); else if ((smallest[wr_i] + add_smallest[wr_i]) > (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) + (((smallest[wr_i] + add_smallest[wr_i]) - (largest[wr_i] + add_largest[wr_i]))/2)); else if ((smallest[wr_i] + add_smallest[wr_i]) == (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]); end end end endgenerate // // fine tap inc/dec value for all DQSs in all ranks // genvar dqs_i; // generate // for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap // always @(posedge clk) begin // if (rst) // fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0; // //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; // else if (wr_level_done_r3 && ~wr_level_done_r4) begin // fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6]; // //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; // end // end // endgenerate // Inc/Dec Phaser_Out stage 2 fine delay line always @(posedge clk) begin if (rst) begin // Fine delay line used only during write leveling dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b0; // Dec Phaser_Out fine delay (1)before write leveling, // (2)if no 0 to 1 transition detected with 63 fine delay taps, or // (3)dual rank case where fine taps for the first rank need to be 0 end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) || (wl_state_r == WL_FINE_DEC)) begin dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b1; // Inc Phaser_Out fine delay during write leveling end else if ((wl_state_r == WL_INIT_FINE_INC) || (wl_state_r == WL_FINE_INC)) begin dqs_po_stg2_f_incdec <= #TCQ 1'b1; dqs_po_en_stg2_f <= #TCQ 1'b1; end else begin dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b0; end end // Inc Phaser_Out stage 2 Coarse delay line always @(posedge clk) begin if (rst) begin // Coarse delay line used during write leveling // only if no 0->1 transition undetected with 64 // fine delay line taps dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; dqs_wl_po_en_stg2_c <= #TCQ 1'b0; end else if (wl_state_r == WL_CORSE_INC) begin // Inc Phaser_Out coarse delay during write leveling dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1; dqs_wl_po_en_stg2_c <= #TCQ 1'b1; end else begin dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; dqs_wl_po_en_stg2_c <= #TCQ 1'b0; end end // only storing the rise data for checking. The data comming back during // write leveling will be a static value. Just checking for rise data is // enough. genvar rd_i; generate for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd always @(posedge clk) rd_data_rise_wl_r[rd_i] <= #TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH]; end endgenerate // storing the previous data for checking later. always @(posedge clk)begin if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT1) || ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) || (wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) || ((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r))) rd_data_previous_r <= #TCQ rd_data_rise_wl_r; end // changed stable count from 3 to 7 because of fine tap resolution always @(posedge clk)begin if (rst | (wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_2RANK_TAP_DEC) | (wl_state_r == WL_FINE_DEC) | (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) | (wl_state_r1 == WL_INIT_FINE_DEC)) stable_cnt <= #TCQ 'd0; else if ((wl_tap_count_r > 6'd0) & (((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) | ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r]) & (stable_cnt < 'd14)) stable_cnt <= #TCQ stable_cnt + 1; end end // Signal to ensure that flag_ck_negedge does not incorrectly assert // when DQS is very close to CK rising edge //always @(posedge clk) begin // if (rst | (wl_state_r == WL_DQS_CNT) | // (wl_state_r == WL_DQS_CHECK) | wr_level_done_r) // past_negedge <= #TCQ 1'b0; // else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] && // (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) | // (wl_state_r == WL_CORSE_INC_WAIT2))) // past_negedge <= #TCQ 1'b1; //end // Flag to indicate negedge of CK detected and ignore 0->1 transitions // in this region always @(posedge clk)begin if (rst | (wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_DQS_CHECK) | wr_level_done_r | (wl_state_r1 == WL_INIT_FINE_DEC)) flag_ck_negedge <= #TCQ 1'd0; else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) | (wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) | (wl_state_r == WL_CORSE_INC)) flag_ck_negedge <= #TCQ 1'd1; else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14)) //&& flag_ck_negedge) flag_ck_negedge <= #TCQ 1'd0; end // Flag to inhibit rd_data_edge_detect_r before stable DQ always @(posedge clk) begin if (rst) flag_init <= #TCQ 1'b1; else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) || (wl_state_r1 == WL_INIT_FINE_DEC_WAIT))) flag_init <= #TCQ 1'b0; end //checking for transition from 0 to 1 always @(posedge clk)begin if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) | inhibit_edge_detect_r) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2)) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r; end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14)) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r); end // registring the write level start signal always@(posedge clk) begin wr_level_start_r <= #TCQ wr_level_start; end // Assign dqs_count_r to dqs_count_w to perform the shift operation // instead of multiply operation assign dqs_count_w = {2'b00, dqs_count_r}; assign oclk_count_w = {2'b00, oclkdelay_calib_cnt}; always @(posedge clk) begin if (rst) incdec_wait_cnt <= #TCQ 'd0; else if ((wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_INIT_FINE_DEC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT_TMP)) incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1; else incdec_wait_cnt <= #TCQ 'd0; end // state machine to initiate the write leveling sequence // The state machine operates on one byte at a time. // It will increment the delays to the DQS OSERDES // and sample the DQ from the memory. When it detects // a transition from 1 to 0 then the write leveling is considered // done. always @(posedge clk) begin if(rst)begin wrlvl_err <= #TCQ 1'b0; wr_level_done_r <= #TCQ 1'b0; wrlvl_rank_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; dq_cnt_inc <= #TCQ 1'b1; rank_cnt_r <= #TCQ 2'b00; wl_state_r <= #TCQ WL_IDLE; wl_state_r1 <= #TCQ WL_IDLE; inhibit_edge_detect_r <= #TCQ 1'b1; wl_edge_detect_valid_r <= #TCQ 1'b0; wl_tap_count_r <= #TCQ 6'd0; fine_dec_cnt <= #TCQ 6'd0; for (r = 0; r < DQS_WIDTH; r = r + 1) begin fine_inc[r] <= #TCQ 6'b0; corse_dec[r] <= #TCQ 3'b0; corse_inc[r] <= #TCQ 3'b0; corse_cnt[r] <= #TCQ 3'b0; end dual_rnk_dec <= #TCQ 1'b0; fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE; fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE; final_corse_dec <= #TCQ 1'b0; //zero_tran_r <= #TCQ 1'b0; wrlvl_redo_corse_inc <= #TCQ 'd0; end else begin wl_state_r1 <= #TCQ wl_state_r; case (wl_state_r) WL_IDLE: begin wrlvl_rank_done_r <= #TCQ 1'd0; inhibit_edge_detect_r <= #TCQ 1'b1; if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin wr_level_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ wrcal_cnt; corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt]; wl_tap_count_r <= #TCQ smallest[wrcal_cnt]; if (early1_data && (((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) || ((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500)))) wrlvl_redo_corse_inc <= #TCQ REDO_COARSE; else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2)) wrlvl_redo_corse_inc <= #TCQ 3'd6; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else if (wrlvl_final && ~wrlvl_final_r) begin wr_level_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ 'd0; end // verilint STARC-2.2.3.3 off if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin if (SIM_CAL_OPTION == "FAST_CAL") wl_state_r <= #TCQ WL_FINE_INC; else wl_state_r <= #TCQ WL_INIT; end end // verilint STARC-2.2.3.3 on WL_INIT: begin wl_edge_detect_valid_r <= #TCQ 1'b0; inhibit_edge_detect_r <= #TCQ 1'b1; wrlvl_rank_done_r <= #TCQ 1'd0; //zero_tran_r <= #TCQ 1'b0; if (wrlvl_final) corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ]; if (wrlvl_byte_redo) begin if (|wl_tap_count_r) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else if(wl_sm_start) wl_state_r <= #TCQ WL_INIT_FINE_INC; end // Initially Phaser_Out fine delay taps incremented // until stable_cnt=14. A stable_cnt of 14 indicates // that rd_data_rise_wl_r=rd_data_previous_r for 14 fine // tap increments. This is done to inhibit false 0->1 // edge detection when DQS is initially aligned to the // negedge of CK WL_INIT_FINE_INC: begin wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1; wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; final_corse_dec <= #TCQ 1'b0; end WL_INIT_FINE_INC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT; end // Case1: stable value of rd_data_previous_r=0 then // proceed to 0->1 edge detection. // Case2: stable value of rd_data_previous_r=1 then // decrement fine taps to '0' and proceed to 0->1 // edge detection. Need to decrement in this case to // make sure a valid 0->1 transition was not left // undetected. WL_INIT_FINE_INC_WAIT: begin if (wl_sm_start) begin if (stable_cnt < 'd14) wl_state_r <= #TCQ WL_INIT_FINE_INC; else if (~rd_data_previous_r[dqs_count_r]) begin wl_state_r <= #TCQ WL_WAIT; inhibit_edge_detect_r <= #TCQ 1'b0; end else begin wl_state_r <= #TCQ WL_INIT_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end end end // Case2: stable value of rd_data_previous_r=1 then // decrement fine taps to '0' and proceed to 0->1 // edge detection. Need to decrement in this case to // make sure a valid 0->1 transition was not left // undetected. WL_INIT_FINE_DEC: begin wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1; if (fine_dec_cnt > 6'd0) fine_dec_cnt <= #TCQ fine_dec_cnt - 1; else fine_dec_cnt <= #TCQ fine_dec_cnt; end WL_INIT_FINE_DEC_WAIT1: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT; end WL_INIT_FINE_DEC_WAIT: begin if (fine_dec_cnt > 6'd0) begin wl_state_r <= #TCQ WL_INIT_FINE_DEC; inhibit_edge_detect_r <= #TCQ 1'b1; end else begin wl_state_r <= #TCQ WL_WAIT; inhibit_edge_detect_r <= #TCQ 1'b0; end end // Inc DQS Phaser_Out Stage2 Fine Delay line WL_FINE_INC: begin wl_edge_detect_valid_r <= #TCQ 1'b0; if (SIM_CAL_OPTION == "FAST_CAL") begin wl_state_r <= #TCQ WL_FINE_INC_WAIT; if (fast_cal_fine_cnt > 'd0) fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1; else fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt; end else if (wr_level_done_r5) begin wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_FINE_INC_WAIT; if (|fine_inc[dqs_count_w]) fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1; end else begin wl_state_r <= #TCQ WL_WAIT; wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; end end WL_FINE_INC_WAIT: begin if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_fine_cnt > 'd0) wl_state_r <= #TCQ WL_FINE_INC; else if (fast_cal_coarse_cnt > 'd0) wl_state_r <= #TCQ WL_CORSE_INC; else wl_state_r <= #TCQ WL_DQS_CNT; end else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; else if (dqs_count_r == (DQS_WIDTH-1)) wl_state_r <= #TCQ WL_IDLE; else begin wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; dqs_count_r <= #TCQ dqs_count_r + 1; end end WL_FINE_DEC: begin wl_edge_detect_valid_r <= #TCQ 1'b0; wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_FINE_DEC_WAIT1; if (fine_dec_cnt > 6'd0) fine_dec_cnt <= #TCQ fine_dec_cnt - 1; else fine_dec_cnt <= #TCQ fine_dec_cnt; end WL_FINE_DEC_WAIT1: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_FINE_DEC_WAIT; end WL_FINE_DEC_WAIT: begin if (fine_dec_cnt > 6'd0) wl_state_r <= #TCQ WL_FINE_DEC; //else if (zero_tran_r) // wl_state_r <= #TCQ WL_DQS_CNT; else if (dual_rnk_dec) begin if (|corse_dec[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_DEC; else wl_state_r <= #TCQ WL_2RANK_DQS_CNT; end else if (wrlvl_byte_redo) begin if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else wl_state_r <= #TCQ WL_CORSE_INC; end WL_CORSE_DEC: begin wl_state_r <= #TCQ WL_CORSE_DEC_WAIT; dual_rnk_dec <= #TCQ 1'b0; if (|corse_dec[dqs_count_r]) corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1; else corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r]; end WL_CORSE_DEC_WAIT: begin if (wl_sm_start) begin //if (|corse_dec[dqs_count_r]) // wl_state_r <= #TCQ WL_CORSE_DEC; if (|corse_dec[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1; else wl_state_r <= #TCQ WL_2RANK_DQS_CNT; end end WL_CORSE_DEC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_CORSE_DEC; end WL_CORSE_INC: begin wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP; if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_coarse_cnt > 'd0) fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1; else fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt; end else if (wrlvl_byte_redo) begin corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1; if (|wrlvl_redo_corse_inc) wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1; end else if (~wr_level_done_r5) corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1; else if (|corse_inc[dqs_count_w]) corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1; end WL_CORSE_INC_WAIT_TMP: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_CORSE_INC_WAIT; end WL_CORSE_INC_WAIT: begin if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_coarse_cnt > 'd0) wl_state_r <= #TCQ WL_CORSE_INC; else wl_state_r <= #TCQ WL_DQS_CNT; end else if (wrlvl_byte_redo) begin if (|wrlvl_redo_corse_inc) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_INIT_FINE_INC; inhibit_edge_detect_r <= #TCQ 1'b1; end end else if (~wr_level_done_r5 && wl_sm_start) wl_state_r <= #TCQ WL_CORSE_INC_WAIT1; else if (wr_level_done_r5) begin if (|corse_inc[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_INC; else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; else if (dqs_count_r == (DQS_WIDTH-1)) wl_state_r <= #TCQ WL_IDLE; else begin wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; dqs_count_r <= #TCQ dqs_count_r + 1; end end end WL_CORSE_INC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_CORSE_INC_WAIT2; end WL_CORSE_INC_WAIT2: begin if (wl_sm_start) wl_state_r <= #TCQ WL_WAIT; end WL_WAIT: begin if (wl_sm_start) wl_state_r <= #TCQ WL_EDGE_CHECK; end WL_EDGE_CHECK: begin // Look for the edge if (wl_edge_detect_valid_r == 1'b0) begin wl_state_r <= #TCQ WL_WAIT; wl_edge_detect_valid_r <= #TCQ 1'b1; end // 0->1 transition detected with DQS else if(rd_data_edge_detect_r[dqs_count_r] && wl_edge_detect_valid_r) begin wl_tap_count_r <= #TCQ wl_tap_count_r; if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) wl_state_r <= #TCQ WL_DQS_CNT; else wl_state_r <= #TCQ WL_2RANK_TAP_DEC; end // For initial writes check only upto 56 taps. Reserving the // remaining taps for OCLK calibration. else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else begin wrlvl_err <= #TCQ 1'b1; wl_state_r <= #TCQ WL_IDLE; end end else begin if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal wl_state_r <= #TCQ WL_FINE_INC; else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else begin wrlvl_err <= #TCQ 1'b1; wl_state_r <= #TCQ WL_IDLE; end end end WL_2RANK_TAP_DEC: begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; for (m = 0; m < DQS_WIDTH; m = m + 1) corse_dec[m] <= #TCQ corse_cnt[m]; wl_edge_detect_valid_r <= #TCQ 1'b0; dual_rnk_dec <= #TCQ 1'b1; end WL_DQS_CNT: begin if ((SIM_CAL_OPTION == "FAST_CAL") || (dqs_count_r == (DQS_WIDTH-1)) || wrlvl_byte_redo) begin dqs_count_r <= #TCQ dqs_count_r; dq_cnt_inc <= #TCQ 1'b0; end else begin dqs_count_r <= #TCQ dqs_count_r + 1'b1; dq_cnt_inc <= #TCQ 1'b1; end wl_state_r <= #TCQ WL_DQS_CHECK; wl_edge_detect_valid_r <= #TCQ 1'b0; end WL_2RANK_DQS_CNT: begin if ((SIM_CAL_OPTION == "FAST_CAL") || (dqs_count_r == (DQS_WIDTH-1))) begin dqs_count_r <= #TCQ dqs_count_r; dq_cnt_inc <= #TCQ 1'b0; end else begin dqs_count_r <= #TCQ dqs_count_r + 1'b1; dq_cnt_inc <= #TCQ 1'b1; end wl_state_r <= #TCQ WL_DQS_CHECK; wl_edge_detect_valid_r <= #TCQ 1'b0; dual_rnk_dec <= #TCQ 1'b0; end WL_DQS_CHECK: begin // check if all DQS have been calibrated wl_tap_count_r <= #TCQ 'd0; if (dq_cnt_inc == 1'b0)begin wrlvl_rank_done_r <= #TCQ 1'd1; for (t = 0; t < DQS_WIDTH; t = t + 1) corse_cnt[t] <= #TCQ 3'b0; if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin wl_state_r <= #TCQ WL_IDLE; if (wrlvl_byte_redo) dqs_count_r <= #TCQ dqs_count_r; else dqs_count_r <= #TCQ 'd0; end else if (rank_cnt_r == RANKS-1) begin dqs_count_r <= #TCQ dqs_count_r; if (RANKS > 1) wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; else wl_state_r <= #TCQ WL_IDLE; end else begin wl_state_r <= #TCQ WL_INIT; dqs_count_r <= #TCQ 'd0; end if ((SIM_CAL_OPTION == "FAST_CAL") || (rank_cnt_r == RANKS-1)) begin wr_level_done_r <= #TCQ 1'd1; rank_cnt_r <= #TCQ 2'b00; end else begin wr_level_done_r <= #TCQ 1'd0; rank_cnt_r <= #TCQ rank_cnt_r + 1'b1; end end else wl_state_r <= #TCQ WL_INIT; end WL_2RANK_FINAL_TAP: begin if (wr_level_done_r4 && ~wr_level_done_r5) begin for(u = 0; u < DQS_WIDTH; u = u + 1) begin corse_inc[u] <= #TCQ final_coarse_tap[u]; fine_inc[u] <= #TCQ final_val[u]; end dqs_count_r <= #TCQ 'd0; end else if (wr_level_done_r5) begin if (|corse_inc[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_INC; else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; end end endcase end end // always @ (posedge clk) endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_wrlvl_off_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter nCK_PER_CLK = 2, parameter CLK_PERIOD = 4, parameter PO_INITIAL_DLY= 46, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter N_CTL_LANES = 3 ) ( input clk, input rst, input pi_fine_dly_dec_done, input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_s2_incdec_f, output reg po_en_s2_f, // Inc/dec Phaser_Out coarse delay line output reg po_s2_incdec_c, output reg po_en_s2_c, // Completed adjusting delays for dq, dqs for tdqss output po_ck_addr_cmd_delay_done, // completed decrementing initialPO delays output po_dec_done, output phy_ctl_rdy_dly ); localparam TAP_LIMIT = 63; // PO fine delay tap resolution change by frequency. tCK > 2500, need // twice the amount of taps // localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY; // coarse delay tap is added DQ/DQS to meet the TDQSS specification. //localparam TDQSS_DLY = (tCK > 2500 )? 2: 1; localparam TDQSS_DLY = 2; // DIV2 change reg delay_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4; reg [5:0] po_delay_cnt_r; reg po_cnt_inc; reg cmd_delay_start_r1; reg cmd_delay_start_r2; reg cmd_delay_start_r3; reg cmd_delay_start_r4; reg cmd_delay_start_r5; reg cmd_delay_start_r6; reg po_delay_done; reg po_delay_done_r1; reg po_delay_done_r2; reg po_delay_done_r3; reg po_delay_done_r4; reg pi_fine_dly_dec_done_r; reg po_en_stg2_c; reg po_en_stg2_f; reg po_stg2_incdec_c; reg po_stg2_f_incdec; reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r; reg [DQS_CNT_WIDTH:0] lane_cnt_po_r; reg [5:0] delay_cnt_r; always @(posedge clk) begin cmd_delay_start_r1 <= #TCQ cmd_delay_start; cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1; cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2; cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3; cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4; cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5; pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done; end assign phy_ctl_rdy_dly = cmd_delay_start_r6; // logic for decrementing initial fine delay taps for all PO // Decrement done for add, ctrl and data phaser outs assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4; always @(posedge clk) if (rst || ~cmd_delay_start_r6 || po_delay_done) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end else if (po_delay_cnt_r > 6'd0) begin po_en_stg2_f <= #TCQ ~po_en_stg2_f; end always @(posedge clk) if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0)) // set all the PO delays to 31. Decrement from 46 to 31. // Requirement comes from dqs_found logic po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31); else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0)) po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1; always @(posedge clk) if (rst) lane_cnt_po_r <= #TCQ 'd0; else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1)) lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1; always @(posedge clk) if (rst || ~cmd_delay_start_r6 ) po_delay_done <= #TCQ 1'b0; else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0)) po_delay_done <= #TCQ 1'b1; always @(posedge clk) begin po_delay_done_r1 <= #TCQ po_delay_done; po_delay_done_r2 <= #TCQ po_delay_done_r1; po_delay_done_r3 <= #TCQ po_delay_done_r2; po_delay_done_r4 <= #TCQ po_delay_done_r3; end // logic to select between all PO delays and data path delay. always @(posedge clk) begin po_s2_incdec_f <= #TCQ po_stg2_f_incdec; po_en_s2_f <= #TCQ po_en_stg2_f; end // Logic to add 1/4 taps amount of delay to data path for tdqss. // After all the initial PO delays are decremented the 1/4 delay will // be added. Coarse delay taps will be added here . // Delay added only to data path assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r : delay_done_r4; always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin po_stg2_incdec_c <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b0; end else if (delay_cnt_r > 6'd0) begin po_en_stg2_c <= #TCQ ~po_en_stg2_c; end always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0)) delay_cnt_r <= #TCQ TDQSS_DLY; else if ( po_en_stg2_c && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; always @(posedge clk) if (rst) lane_cnt_dqs_c_r <= #TCQ 'd0; else if ( po_en_stg2_c && (delay_cnt_r == 6'd1)) lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1; always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r) delay_done <= #TCQ 1'b0; else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0)) delay_done <= #TCQ 1'b1; always @(posedge clk) begin delay_done_r1 <= #TCQ delay_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end always @(posedge clk) begin po_s2_incdec_c <= #TCQ po_stg2_incdec_c; po_en_s2_c <= #TCQ po_en_stg2_c; ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r; end endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_prbs_gen.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $ // \ \ / \ Date Created: 05/12/10 // \___\/\___\ // //Device: 7 Series //Design Name: ddr_prbs_gen // Overview: // Implements a "pseudo-PRBS" generator. Basically this is a standard // PRBS generator (using an linear feedback shift register) along with // logic to force the repetition of the sequence after 2^PRBS_WIDTH // samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design // from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains // are supported in this code // Parameter Requirements: // 1. PRBS_WIDTH = 8 or 10 // 2. PRBS_WIDTH >= 2*nCK_PER_CLK // Output notes: // The output of this module consists of 2*nCK_PER_CLK bits, these contain // the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note // that prbs_o[0] contains the bit value for the "earliest" bit time. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $ **$Date: 2011/06/02 08:35:10 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_prbs_gen # ( parameter TCQ = 100, // clk->out delay (sim only) parameter PRBS_WIDTH = 64, // LFSR shift register length parameter DQS_CNT_WIDTH = 5, parameter DQ_WIDTH = 72, parameter VCCO_PAT_EN = 1, parameter VCCAUX_PAT_EN = 1, parameter ISI_PAT_EN = 1, parameter FIXED_VICTIM = "TRUE" ) ( input clk_i, // input clock input clk_en_i, // clock enable input rst_i, // synchronous reset input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed input phy_if_empty, // IN_FIFO empty flag input prbs_rdlvl_start, // PRBS read lveling start input prbs_rdlvl_done, input complex_wr_done, input [2:0] victim_sel, input [DQS_CNT_WIDTH:0] byte_cnt, //output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data output [8*DQ_WIDTH-1:0] prbs_o, output [9:0] dbg_prbs_gen, input reset_rd_addr, output prbs_ignore_first_byte, output prbs_ignore_last_bytes ); //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // Number of internal clock cycles before the PRBS sequence will repeat localparam PRBS_SEQ_LEN_CYCLES = 128; localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES); reg phy_if_empty_r; reg reseed_prbs_r; reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r; reg [PRBS_WIDTH - 1 :0] prbs; reg [PRBS_WIDTH :1] lfsr_q; //*************************************************************************** always @(posedge clk_i) begin phy_if_empty_r <= #TCQ phy_if_empty; end //*************************************************************************** // Generate PRBS reset signal to ensure that PRBS sequence repeats after // every 2**PRBS_WIDTH samples. Basically what happens is that we let the // LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1 // samples have past. Once that extra cycle is finished, we reseed the LFSR always @(posedge clk_i) begin if (rst_i || ~clk_en_i) begin sample_cnt_r <= #TCQ 'b0; reseed_prbs_r <= #TCQ 1'b0; end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin // The rollver count should always be [(power of 2) - 1] sample_cnt_r <= #TCQ sample_cnt_r + 1; // Assert PRBS reset signal so that it is simultaneously with the // last sample of the sequence if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2) reseed_prbs_r <= #TCQ 1'b1; else reseed_prbs_r <= #TCQ 1'b0; end end always @ (posedge clk_i) begin //reset it to a known good state to prevent it locks up if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4]; end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30]; lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1]; lfsr_q[29:9] <= #TCQ lfsr_q[28:8]; lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; lfsr_q[2] <= #TCQ lfsr_q[1] ; lfsr_q[1] <= #TCQ lfsr_q[32]; end end always @ (lfsr_q[PRBS_WIDTH:1]) begin prbs = lfsr_q[PRBS_WIDTH:1]; end //****************************************************************************** // Complex pattern BRAM //****************************************************************************** localparam BRAM_ADDR_WIDTH = 8; localparam BRAM_DATA_WIDTH = 18; localparam BRAM_DEPTH = 256; integer i,j; (* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr; //reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1]; (* RAM_STYLE = "distributed" *) reg [BRAM_DATA_WIDTH - 1:0] mem_out; reg [BRAM_DATA_WIDTH - 3:0] dout_o; reg [DQ_WIDTH-1:0] sel; reg [DQ_WIDTH-1:0] dout_rise0; reg [DQ_WIDTH-1:0] dout_fall0; reg [DQ_WIDTH-1:0] dout_rise1; reg [DQ_WIDTH-1:0] dout_fall1; reg [DQ_WIDTH-1:0] dout_rise2; reg [DQ_WIDTH-1:0] dout_fall2; reg [DQ_WIDTH-1:0] dout_rise3; reg [DQ_WIDTH-1:0] dout_fall3; // VCCO noise injection pattern with matching victim (reads with gaps) // content format // {aggressor pattern, victim pattern} always @ (rd_addr) begin case (rd_addr) 8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read 8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads 8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads 8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads 8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads 8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads 8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads 8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads 8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads 8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads 8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads 8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads 8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads 8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads 8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads 8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads 8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads 8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads 8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads 8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads 8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads // VCCO noise injection pattern with non-matching victim (reads with gaps) // content format // {aggressor pattern, victim pattern} 8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read 8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads 8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads 8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads 8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads 8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads 8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads 8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads 8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads 8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads 8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads 8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads 8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads 8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads 8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads 8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads 8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads 8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads 8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads 8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads 8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads // VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps) // content format // {aggressor pattern, victim pattern} 8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads 8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads 8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads 8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads 8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads 8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads 8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads 8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads 8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads 8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads 8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads 8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads 8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads 8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads 8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads 8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads 8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads 8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads 8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads 8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads 8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads 8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads 8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads 8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads 8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads 8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads 8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads 8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads 8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads 8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads 8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads 8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads 8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads 8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads 8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads 8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads 8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads 8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads 8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads 8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads 8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads 8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads 8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads 8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads 8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads 8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads 8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads 8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads 8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads 8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads 8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads 8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads 8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads 8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads 8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads 8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads 8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads 8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads 8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads 8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads 8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads 8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads 8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads 8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads 8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads 8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads 8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads 8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads 8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads 8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads 8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads 8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads 8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads 8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads 8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads 8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads 8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads 8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads 8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads 8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads 8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads 8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads 8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads 8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads 8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads // ISI pattern (Back-to-back reads) // content format // {aggressor pattern, victim pattern} 8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111}; 8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111}; 8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000}; 8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100}; 8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001}; 8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111}; 8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101}; 8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011}; 8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101}; 8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101}; 8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000}; 8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100}; 8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101}; 8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011}; 8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111}; 8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000}; 8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011}; 8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100}; 8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011}; 8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100}; 8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101}; 8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000}; //Additional for ISI 8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000}; 8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101}; 8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101}; 8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000}; 8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000}; 8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010}; 8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010}; 8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000}; //Available 8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001}; 8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001}; endcase end always @ (posedge clk_i) begin if (rst_i | reset_rd_addr) rd_addr <= #TCQ 'b0; //rd_addr for complex oclkdelay calib else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin if (rd_addr == 'd156) rd_addr <= #TCQ 'b0; else rd_addr <= #TCQ rd_addr + 1; end //rd_addr for complex rdlvl else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin if (rd_addr == 'd148) rd_addr <= #TCQ 'b0; else rd_addr <= #TCQ rd_addr+1; end end // Each pattern can be disabled independently // When disabled zeros are written to and read from the DRAM always @ (posedge clk_i) begin if ((rd_addr < 42) && VCCO_PAT_EN) dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; else if ((rd_addr < 127) && VCCAUX_PAT_EN) dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; else if (ISI_PAT_EN && (rd_addr > 126)) dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; else dout_o <= #TCQ 'd0; end reg prbs_ignore_first_byte_r; always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16]; assign prbs_ignore_first_byte = prbs_ignore_first_byte_r; reg prbs_ignore_last_bytes_r; always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17]; assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r; generate if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed // Fixed victim bit 3 always @(posedge clk_i) sel <= #TCQ {DQ_WIDTH/8{8'h08}}; end else begin: victim_sel_rotate // One-hot victim select always @(posedge clk_i) if (rst_i) sel <= #TCQ 'd0; else begin for (i = 0; i < DQ_WIDTH/8; i = i+1) begin for (j=0; j <8 ; j = j+1) begin if (j == victim_sel) sel[i*8+j] <= #TCQ 1'b1; else sel[i*8+j] <= #TCQ 1'b0; end end end end endgenerate // construct 8 X DATA_WIDTH output bus always @(*) for (i = 0; i < DQ_WIDTH; i = i+1) begin dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]); dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]); dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]); dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]); dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]); dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]); dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]); dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]); end assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0}; assign dbg_prbs_gen[9] = phy_if_empty_r; assign dbg_prbs_gen[8] = clk_en_i; assign dbg_prbs_gen[7:0] = rd_addr[7:0]; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_skip_calib_tap.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_skip_calib_tap.v // /___/ /\ Date Last Modified: $Date: 2015/05/06 02:07:40 $ // \ \ / \ Date Created: May 06 2015 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Phaser_Out, Phaser_In, and IDELAY tap adjustments to match // calibration values when SKIP_CALIB=="TRUE" //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v4_0_ddr_skip_calib_tap # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DQS_WIDTH = 8 // number of bytes ) ( input clk, input rst, input phy_ctl_ready, // Completed loading calib tap values into registers input load_done, // Tap adjustment status input calib_tap_inc_start, output calib_tap_inc_done, // Calibration tap values input [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt, input [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt, input [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt, input [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt, input [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt, // Phaser_Out and Phaser_In tap count input [8:0] po_counter_read_val, input [5:0] pi_counter_read_val, // Phaser_Out and Phaser_In tap inc/dec control signals output [5:0] calib_tap_inc_byte_cnt, output calib_po_f_en, output calib_po_f_incdec, output calib_po_sel_stg2stg3, output calib_po_c_en, output calib_po_c_inc, output calib_pi_f_en, output calib_pi_f_incdec, output calib_idelay_ce, output calib_idelay_inc, output skip_cal_po_pi_dec_done, output reg coarse_dec_err, output [127:0] dbg_skip_cal ); //*************************************************************************** // Decrement initial Phaser_OUT fine delay value before proceeding with // calibration //*************************************************************************** reg phy_ctl_ready_r1, phy_ctl_ready_r2, phy_ctl_ready_r3, phy_ctl_ready_r4, phy_ctl_ready_r5, phy_ctl_ready_r6; reg po_cnt_dec; reg [3:0] dec_wait_cnt; reg [8:0] po_rdval_cnt; reg po_dec_done; reg dec_po_f_en_r; reg dec_po_f_incdec_r; reg dqs_po_dec_done_r1, dqs_po_dec_done_r2; reg fine_dly_dec_done_r1, fine_dly_dec_done_r2, fine_dly_dec_done_r3; reg [5:0] pi_rdval_cnt; reg pi_cnt_dec; reg dec_pi_f_en_r; reg dec_pi_f_incdec_r; always @(posedge clk) begin phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; end always @(posedge clk) begin if (rst || po_cnt_dec || pi_cnt_dec) dec_wait_cnt <= #TCQ 'd8; else if (phy_ctl_ready_r6 && (dec_wait_cnt > 'd0)) dec_wait_cnt <= #TCQ dec_wait_cnt - 1; end always @(posedge clk) begin if (rst) begin po_rdval_cnt <= #TCQ 'd0; end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin po_rdval_cnt <= #TCQ po_counter_read_val; end else if (po_rdval_cnt > 'd0) begin if (po_cnt_dec) po_rdval_cnt <= #TCQ po_rdval_cnt - 1; else po_rdval_cnt <= #TCQ po_rdval_cnt; end else if (po_rdval_cnt == 'd0) begin po_rdval_cnt <= #TCQ po_rdval_cnt; end end always @(posedge clk) begin if (rst || (po_rdval_cnt == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (dec_wait_cnt == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end // Inc/Dec Phaser_Out stage 2 fine delay line always @(posedge clk) begin if (rst) begin dec_po_f_incdec_r <= #TCQ 1'b0; dec_po_f_en_r <= #TCQ 1'b0; end else if (po_cnt_dec) begin dec_po_f_incdec_r <= #TCQ 1'b0; dec_po_f_en_r <= #TCQ 1'b1; end else begin dec_po_f_incdec_r <= #TCQ 1'b0; dec_po_f_en_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst) po_dec_done <= #TCQ 1'b0; else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin po_dec_done <= #TCQ 1'b1; end end //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // calibration //*************************************************************************** always @(posedge clk) begin dqs_po_dec_done_r1 <= #TCQ po_dec_done; dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2; end always @(posedge clk) begin if (rst) begin pi_rdval_cnt <= #TCQ 'd0; end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin pi_rdval_cnt <= #TCQ pi_counter_read_val; end else if (pi_rdval_cnt > 'd0) begin if (pi_cnt_dec) pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; else pi_rdval_cnt <= #TCQ pi_rdval_cnt; end else if (pi_rdval_cnt == 'd0) begin pi_rdval_cnt <= #TCQ pi_rdval_cnt; end end always @(posedge clk) begin if (rst || (pi_rdval_cnt == 'd0)) pi_cnt_dec <= #TCQ 1'b0; else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) && (dec_wait_cnt == 'd1)) pi_cnt_dec <= #TCQ 1'b1; else pi_cnt_dec <= #TCQ 1'b0; end // Inc/Dec Phaser_In stage 2 fine delay line always @(posedge clk) begin if (rst) begin dec_pi_f_incdec_r <= #TCQ 1'b0; dec_pi_f_en_r <= #TCQ 1'b0; end else if (pi_cnt_dec) begin dec_pi_f_incdec_r <= #TCQ 1'b0; dec_pi_f_en_r <= #TCQ 1'b1; end else begin dec_pi_f_incdec_r <= #TCQ 1'b0; dec_pi_f_en_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst) begin fine_dly_dec_done_r1 <= #TCQ 1'b0; end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin fine_dly_dec_done_r1 <= #TCQ 1'b1; end end assign skip_cal_po_pi_dec_done = fine_dly_dec_done_r3; //*************************end Phaser_Out and Phaser_In decrement to zero******* localparam WAIT_CNT = 15; // State Machine localparam [4:0] IDLE = 5'h00; localparam [4:0] READ_PO_PI_COUNTER_VAL = 5'h01; localparam [4:0] CALC_INC_DEC_CNT_VAL = 5'h02; localparam [4:0] WAIT_STG3_SEL = 5'h03; localparam [4:0] PO_COARSE_CNT_CHECK = 5'h04; localparam [4:0] PO_COARSE_INC = 5'h05; localparam [4:0] PO_STG3_SEL = 5'h06; localparam [4:0] PO_STG3_INC_CNT_CHECK = 5'h07; localparam [4:0] PO_STG3_INC = 5'h08; localparam [4:0] PO_STG3_DEC_CNT_CHECK = 5'h09; localparam [4:0] PO_STG3_DEC = 5'h0A; localparam [4:0] PO_STG2_INC_CNT_CHECK = 5'h0B; localparam [4:0] PO_STG2_INC = 5'h0C; localparam [4:0] PO_STG2_DEC_CNT_CHECK = 5'h0D; localparam [4:0] PO_STG2_DEC = 5'h0E; localparam [4:0] PI_STG2_INC_CNT_CHECK = 5'h0F; localparam [4:0] PI_STG2_INC = 5'h10; localparam [4:0] PI_STG2_DEC_CNT_CHECK = 5'h11; localparam [4:0] PI_STG2_DEC = 5'h12; localparam [4:0] IDELAY_CNT_CHECK = 5'h13; localparam [4:0] IDELAY_TAP_INC = 5'h14; localparam [4:0] WAIT_TAP_INC_DEC = 5'h15; localparam [4:0] NEXT_BYTE = 5'h16; localparam [4:0] WAIT_PO_PI_COUNTER_VAL = 5'h17; localparam [4:0] PO_PI_TAP_ADJ_DONE = 5'h18; reg calib_tap_inc_start_r; reg [4:0] skip_state_r; reg wait_cnt_en_r; reg wait_cnt_done; reg [3:0] wait_cnt_r; reg po_sel_stg23_r; reg po_f_en_r; reg po_f_incdec_r; reg po_c_en_r; reg po_c_inc_r; reg pi_f_en_r; reg pi_f_incdec_r; reg idelay_ce_r; reg idelay_inc_r; reg [2:0] po_c_inc_cnt; reg [5:0] po_stg3_inc_cnt; reg [5:0] po_stg3_dec_cnt; reg [5:0] po_stg2_inc_cnt; reg [5:0] po_stg2_dec_cnt; reg [5:0] pi_stg2_inc_cnt; reg [5:0] pi_stg2_dec_cnt; reg [4:0] idelay_inc_cnt; reg po_stg3_cnt_load_r; reg po_c_inc_active_r; reg po_stg3_inc_active_r; reg po_stg3_dec_active_r; reg po_stg2_inc_active_r; reg po_stg2_dec_active_r; reg pi_stg2_inc_active_r; reg pi_stg2_dec_active_r; reg idelay_inc_active_r; reg [5:0] byte_cnt_r; reg tap_adj_done_r; reg [2:0] calib_byte_po_c_cnt; reg [5:0] calib_byte_po_stg2_cnt; reg [5:0] calib_byte_po_stg3_cnt; reg [5:0] calib_byte_pi_stg2_cnt; reg [4:0] calib_byte_idelay_cnt; reg [4:0] skip_next_state; reg [5:0] byte_cnt; reg tap_adj_done; reg po_sel_stg23; reg po_f_en; reg po_f_incdec; reg po_c_en; reg po_c_inc; reg pi_f_en; reg pi_f_incdec; reg idelay_ce; reg idelay_inc; reg po_stg3_cnt_load; reg po_c_inc_active; reg po_stg3_inc_active; reg po_stg3_dec_active; reg po_stg2_inc_active; reg po_stg2_dec_active; reg pi_stg2_inc_active; reg pi_stg2_dec_active; reg idelay_inc_active; // Output assignments assign calib_tap_inc_byte_cnt = byte_cnt_r; assign calib_po_f_en = fine_dly_dec_done_r3 ? po_f_en_r : dec_po_f_en_r; assign calib_po_f_incdec = fine_dly_dec_done_r3 ? po_f_incdec_r : dec_po_f_incdec_r; assign calib_po_sel_stg2stg3 = po_sel_stg23_r; assign calib_po_c_en = po_c_en_r; assign calib_po_c_inc = po_c_inc_r; assign calib_pi_f_en = fine_dly_dec_done_r3 ? pi_f_en_r : dec_pi_f_en_r; assign calib_pi_f_incdec = fine_dly_dec_done_r3 ? pi_f_incdec_r : dec_pi_f_incdec_r; assign calib_idelay_ce = idelay_ce_r; assign calib_idelay_inc = idelay_inc_r; assign calib_tap_inc_done = tap_adj_done_r; // Register input calib_tap_inc_start always @(posedge clk) calib_tap_inc_start_r <= #TCQ calib_tap_inc_start; /**************************Wait Counter Start*********************************/ // Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and // WAIT_PO_PI_COUNTER_VAL always @(posedge clk) begin if ((skip_state_r == WAIT_STG3_SEL) || (skip_state_r == WAIT_TAP_INC_DEC) || (skip_state_r == WAIT_PO_PI_COUNTER_VAL)) wait_cnt_en_r <= #TCQ 1'b1; else wait_cnt_en_r <= #TCQ 1'b0; end // Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and // WAIT_PO_PI_COUNTER_VAL always @(posedge clk) begin if (!wait_cnt_en_r) begin wait_cnt_r <= #TCQ 'b0; wait_cnt_done <= #TCQ 1'b0; end else begin if (wait_cnt_r != WAIT_CNT - 1) begin wait_cnt_r <= #TCQ wait_cnt_r + 1; wait_cnt_done <= #TCQ 1'b0; end else begin wait_cnt_r <= #TCQ 'b0; wait_cnt_done <= #TCQ 1'b1; end end end /**************************Wait Counter End***********************************/ // Calibration tap values for current byte being adjusted always @(posedge clk) begin if (rst) begin calib_byte_po_c_cnt <= #TCQ 'd0; calib_byte_po_stg2_cnt <= #TCQ 'd0; calib_byte_po_stg3_cnt <= #TCQ 'd0; calib_byte_pi_stg2_cnt <= #TCQ 'd0; calib_byte_idelay_cnt <= #TCQ 'd0; end else begin calib_byte_po_c_cnt <= #TCQ calib_po_coarse_tap_cnt[3*byte_cnt_r+:3]; calib_byte_po_stg2_cnt <= #TCQ calib_po_stage2_tap_cnt[6*byte_cnt_r+:6]; calib_byte_po_stg3_cnt <= #TCQ calib_po_stage3_tap_cnt[6*byte_cnt_r+:6]; calib_byte_pi_stg2_cnt <= #TCQ calib_pi_stage2_tap_cnt[6*byte_cnt_r+:6]; calib_byte_idelay_cnt <= #TCQ calib_idelay_tap_cnt[5*byte_cnt_r+:5]; end end // Phaser_Out, Phaser_In, and IDELAY inc/dec counters always @(posedge clk) begin if (rst) begin po_c_inc_cnt <= #TCQ 'd0; po_stg2_inc_cnt <= #TCQ 'd0; po_stg2_dec_cnt <= #TCQ 'd0; pi_stg2_inc_cnt <= #TCQ 'd0; pi_stg2_dec_cnt <= #TCQ 'd0; idelay_inc_cnt <= #TCQ 'd0; end else if (skip_state_r == READ_PO_PI_COUNTER_VAL) begin // IDELAY tap count setting idelay_inc_cnt <= #TCQ calib_byte_idelay_cnt; // Phaser_Out coarse tap setting if (po_counter_read_val[8:6] == 'd0) begin coarse_dec_err <= #TCQ 1'b0; po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt; end else if (po_counter_read_val[8:6] < calib_byte_po_c_cnt) begin coarse_dec_err <= #TCQ 1'b0; po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt - po_counter_read_val[8:6]; end else begin // Phaser_Out coarse taps cannot be decremented coarse_dec_err <= #TCQ 1'b1; po_c_inc_cnt <= #TCQ 'd0; end // Phaser_Out stage2 tap count setting when po_sel_stg23_r=0 if (po_counter_read_val[5:0] == 'd0) begin po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt; po_stg2_dec_cnt <= #TCQ 'd0; end else if (po_counter_read_val[5:0] > calib_byte_po_stg2_cnt) begin po_stg2_inc_cnt <= #TCQ 'd0; po_stg2_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg2_cnt; end else if (po_counter_read_val[5:0] < calib_byte_po_stg2_cnt) begin po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt - po_counter_read_val[5:0]; po_stg2_dec_cnt <= #TCQ 'd0; end else if (po_counter_read_val[5:0] == calib_byte_po_stg2_cnt) begin po_stg2_inc_cnt <= #TCQ 'd0; po_stg2_dec_cnt <= #TCQ 'd0; end //Phaser_In stgae2 tap count setting if (pi_counter_read_val == 'd0) begin pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt; pi_stg2_dec_cnt <= #TCQ 'd0; end else if (pi_counter_read_val > calib_byte_pi_stg2_cnt) begin pi_stg2_inc_cnt <= #TCQ 'd0; pi_stg2_dec_cnt <= #TCQ pi_counter_read_val - calib_byte_pi_stg2_cnt; end else if (pi_counter_read_val < calib_byte_pi_stg2_cnt) begin pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt - pi_counter_read_val; pi_stg2_dec_cnt <= #TCQ 'd0; end else if (pi_counter_read_val == calib_byte_pi_stg2_cnt) begin pi_stg2_inc_cnt <= #TCQ 'd0; pi_stg2_dec_cnt <= #TCQ 'd0; end end else begin if (skip_state_r == IDELAY_TAP_INC) idelay_inc_cnt <= #TCQ idelay_inc_cnt - 1; if (skip_state_r == PO_COARSE_INC) po_c_inc_cnt <= #TCQ po_c_inc_cnt - 1; if (skip_state_r == PO_STG2_INC) po_stg2_inc_cnt <= #TCQ po_stg2_inc_cnt - 1; if (skip_state_r == PO_STG2_DEC) po_stg2_dec_cnt <= #TCQ po_stg2_dec_cnt - 1; if (skip_state_r == PI_STG2_INC) pi_stg2_inc_cnt <= #TCQ pi_stg2_inc_cnt - 1; if (skip_state_r == PI_STG2_DEC) pi_stg2_dec_cnt <= #TCQ pi_stg2_dec_cnt - 1; end end // Phaser_Out stage 3 tap count setting when po_sel_stg23_r=1 always @(posedge clk) begin if (rst) begin po_stg3_inc_cnt <= #TCQ 'd0; po_stg3_dec_cnt <= #TCQ 'd0; end else if ((skip_state_r == WAIT_STG3_SEL) && wait_cnt_done && po_stg3_cnt_load_r) begin if (po_counter_read_val[5:0] == 'd0) begin po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt; po_stg3_dec_cnt <= #TCQ 'd0; end else if (po_counter_read_val[5:0] > calib_byte_po_stg3_cnt) begin po_stg3_inc_cnt <= #TCQ 'd0; po_stg3_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg3_cnt; end else if (po_counter_read_val[5:0] < calib_byte_po_stg3_cnt) begin po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt - po_counter_read_val[5:0]; po_stg3_dec_cnt <= #TCQ 'd0; end else if (po_counter_read_val[5:0] == calib_byte_po_stg3_cnt) begin po_stg3_inc_cnt <= #TCQ 'd0; po_stg3_dec_cnt <= #TCQ 'd0; end end else begin if (skip_state_r == PO_STG3_INC) po_stg3_inc_cnt <= #TCQ po_stg3_inc_cnt - 1; if (skip_state_r == PO_STG3_DEC) po_stg3_dec_cnt <= #TCQ po_stg3_dec_cnt - 1; end end always @(posedge clk) begin if (rst) begin skip_state_r <= #TCQ IDLE; byte_cnt_r <= #TCQ 'd0; tap_adj_done_r <= #TCQ 1'b0; po_sel_stg23_r <= #TCQ 1'b0; po_f_en_r <= #TCQ 1'b0; po_f_incdec_r <= #TCQ 1'b0; po_c_en_r <= #TCQ 1'b0; po_c_inc_r <= #TCQ 1'b0; pi_f_en_r <= #TCQ 1'b0; pi_f_incdec_r <= #TCQ 1'b0; idelay_ce_r <= #TCQ 1'b0; idelay_inc_r <= #TCQ 1'b0; po_stg3_cnt_load_r <= #TCQ 1'b0; po_c_inc_active_r <= #TCQ 1'b0; po_stg3_inc_active_r <= #TCQ 1'b0; po_stg3_dec_active_r <= #TCQ 1'b0; po_stg2_inc_active_r <= #TCQ 1'b0; po_stg2_dec_active_r <= #TCQ 1'b0; pi_stg2_inc_active_r <= #TCQ 1'b0; pi_stg2_dec_active_r <= #TCQ 1'b0; idelay_inc_active_r <= #TCQ 1'b0; end else begin skip_state_r <= #TCQ skip_next_state; byte_cnt_r <= #TCQ byte_cnt; tap_adj_done_r <= #TCQ tap_adj_done; po_sel_stg23_r <= #TCQ po_sel_stg23; po_f_en_r <= #TCQ po_f_en; po_f_incdec_r <= #TCQ po_f_incdec; po_c_en_r <= #TCQ po_c_en; po_c_inc_r <= #TCQ po_c_inc; pi_f_en_r <= #TCQ pi_f_en; pi_f_incdec_r <= #TCQ pi_f_incdec; idelay_ce_r <= #TCQ idelay_ce; idelay_inc_r <= #TCQ idelay_inc; po_stg3_cnt_load_r <= #TCQ po_stg3_cnt_load; po_c_inc_active_r <= #TCQ po_c_inc_active; po_stg3_inc_active_r <= #TCQ po_stg3_inc_active; po_stg3_dec_active_r <= #TCQ po_stg3_dec_active; po_stg2_inc_active_r <= #TCQ po_stg2_inc_active; po_stg2_dec_active_r <= #TCQ po_stg2_dec_active; pi_stg2_inc_active_r <= #TCQ pi_stg2_inc_active; pi_stg2_dec_active_r <= #TCQ pi_stg2_dec_active; idelay_inc_active_r <= #TCQ idelay_inc_active; end end // State Machine always @(*) begin skip_next_state = skip_state_r; byte_cnt = byte_cnt_r; tap_adj_done = tap_adj_done_r; po_sel_stg23 = po_sel_stg23_r; po_f_en = po_f_en_r; po_f_incdec = po_f_incdec_r; po_c_en = po_c_en_r; po_c_inc = po_c_inc_r; pi_f_en = pi_f_en_r; pi_f_incdec = pi_f_incdec_r; idelay_ce = idelay_ce_r; idelay_inc = idelay_inc_r; po_stg3_cnt_load = po_stg3_cnt_load_r; po_c_inc_active = po_c_inc_active_r; po_stg3_inc_active = po_stg3_inc_active_r; po_stg3_dec_active = po_stg3_dec_active_r; po_stg2_inc_active = po_stg2_inc_active_r; po_stg2_dec_active = po_stg2_dec_active_r; pi_stg2_inc_active = pi_stg2_inc_active_r; pi_stg2_dec_active = pi_stg2_dec_active_r; idelay_inc_active = idelay_inc_active_r; case(skip_state_r) IDLE: begin // Begin tap adjustment on the rising edge of calib_tap_inc_start // This logic assumes that load_done is asserted before calib_tap_inc_start // If this is not the case this logic will have to change if (calib_tap_inc_start && ~calib_tap_inc_start_r && load_done) begin skip_next_state = READ_PO_PI_COUNTER_VAL; end end READ_PO_PI_COUNTER_VAL: begin skip_next_state = CALC_INC_DEC_CNT_VAL; end CALC_INC_DEC_CNT_VAL: begin skip_next_state = WAIT_STG3_SEL; po_sel_stg23 = 1'b1; po_stg3_cnt_load = 1'b1; end WAIT_STG3_SEL: begin if (wait_cnt_done) begin if (po_stg3_cnt_load) skip_next_state = PO_STG3_SEL; else skip_next_state = PO_COARSE_CNT_CHECK; end end PO_COARSE_CNT_CHECK: begin if (po_c_inc_cnt > 'd0) begin po_c_inc_active = 1'b1; skip_next_state = PO_COARSE_INC; end else begin po_c_inc_active = 1'b0; skip_next_state = PO_STG2_DEC_CNT_CHECK; end end PO_COARSE_INC: begin po_c_en = 1'b1; po_c_inc = 1'b1; skip_next_state = WAIT_TAP_INC_DEC; end PO_STG3_SEL: begin po_stg3_cnt_load = 1'b0; if (po_stg3_inc_cnt > 'd0) begin po_stg3_inc_active = 1'b1; skip_next_state = PO_STG3_INC; end else if (po_stg3_dec_cnt > 'd0) begin po_stg3_dec_active = 1'b1; skip_next_state = PO_STG3_DEC; end else begin po_sel_stg23 = 1'b0; skip_next_state = WAIT_STG3_SEL; end end PO_STG3_INC_CNT_CHECK: begin if (po_stg3_inc_cnt > 'd0) begin po_stg3_inc_active = 1'b1; skip_next_state = PO_STG3_INC; end else begin po_stg3_inc_active = 1'b0; po_sel_stg23 = 1'b0; skip_next_state = WAIT_STG3_SEL; end end PO_STG3_INC: begin po_f_en = 1'b1; po_f_incdec = 1'b1; skip_next_state = WAIT_TAP_INC_DEC; end PO_STG3_DEC_CNT_CHECK: begin if (po_stg3_dec_cnt > 'd0) begin po_stg3_dec_active = 1'b1; skip_next_state = PO_STG3_DEC; end else begin po_stg3_dec_active = 1'b0; po_sel_stg23 = 1'b0; skip_next_state = WAIT_STG3_SEL; end end PO_STG3_DEC: begin po_f_en = 1'b1; po_f_incdec = 1'b0; skip_next_state = WAIT_TAP_INC_DEC; end PO_STG2_DEC_CNT_CHECK: begin if (po_stg2_dec_cnt > 'd0) begin po_stg2_dec_active = 1'b1; skip_next_state = PO_STG2_DEC; end else if (po_stg2_inc_cnt > 'd0) begin po_stg2_dec_active = 1'b0; skip_next_state = PO_STG2_INC_CNT_CHECK; end else begin po_stg2_dec_active = 1'b0; skip_next_state = PI_STG2_DEC_CNT_CHECK; end end PO_STG2_DEC: begin po_f_en = 1'b1; po_f_incdec = 1'b0; skip_next_state = WAIT_TAP_INC_DEC; end PO_STG2_INC_CNT_CHECK: begin if (po_stg2_inc_cnt > 'd0) begin po_stg2_inc_active = 1'b1; skip_next_state = PO_STG2_INC; end else begin po_stg2_inc_active = 1'b0; skip_next_state = PI_STG2_DEC_CNT_CHECK; end end PO_STG2_INC: begin po_f_en = 1'b1; po_f_incdec = 1'b1; skip_next_state = WAIT_TAP_INC_DEC; end PI_STG2_DEC_CNT_CHECK: begin if (pi_stg2_dec_cnt > 'd0) begin pi_stg2_dec_active = 1'b1; skip_next_state = PI_STG2_DEC; end else if (pi_stg2_inc_cnt > 'd0) begin pi_stg2_dec_active = 1'b0; skip_next_state = PI_STG2_INC_CNT_CHECK; end else begin pi_stg2_dec_active = 1'b0; skip_next_state = IDELAY_CNT_CHECK; end end PI_STG2_DEC: begin pi_f_en = 1'b1; pi_f_incdec = 1'b0; skip_next_state = WAIT_TAP_INC_DEC; end PI_STG2_INC_CNT_CHECK: begin if (pi_stg2_inc_cnt > 'd0) begin pi_stg2_inc_active = 1'b1; skip_next_state = PI_STG2_INC; end else begin pi_stg2_inc_active = 1'b0; skip_next_state = IDELAY_CNT_CHECK; end end PI_STG2_INC: begin pi_f_en = 1'b1; pi_f_incdec = 1'b1; skip_next_state = WAIT_TAP_INC_DEC; end IDELAY_CNT_CHECK: begin if (idelay_inc_cnt > 'd0) begin idelay_inc_active = 1'b1; skip_next_state = IDELAY_TAP_INC; end else begin idelay_inc_active = 1'b0; skip_next_state = NEXT_BYTE; end end IDELAY_TAP_INC: begin idelay_ce = 1'b1; idelay_inc = 1'b1; skip_next_state = WAIT_TAP_INC_DEC; end WAIT_TAP_INC_DEC: begin po_c_en = 1'b0; po_c_inc = 1'b0; po_f_en = 1'b0; po_f_incdec = 1'b0; pi_f_en = 1'b0; pi_f_incdec = 1'b0; idelay_ce = 1'b0; idelay_inc = 1'b0; if (wait_cnt_done) begin if (po_c_inc_active_r) skip_next_state = PO_COARSE_CNT_CHECK; else if (po_stg3_inc_active_r) skip_next_state = PO_STG3_INC_CNT_CHECK; else if (po_stg3_dec_active_r) skip_next_state = PO_STG3_DEC_CNT_CHECK; else if (po_stg2_dec_active_r) skip_next_state = PO_STG2_DEC_CNT_CHECK; else if (po_stg2_inc_active_r) skip_next_state = PO_STG2_INC_CNT_CHECK; else if (pi_stg2_dec_active_r) skip_next_state = PI_STG2_DEC_CNT_CHECK; else if (pi_stg2_inc_active_r) skip_next_state = PI_STG2_INC_CNT_CHECK; else if (idelay_inc_active_r) skip_next_state = IDELAY_CNT_CHECK; end end NEXT_BYTE: begin if (byte_cnt_r >= DQS_WIDTH-1) begin skip_next_state = PO_PI_TAP_ADJ_DONE; end else begin byte_cnt = byte_cnt + 1; skip_next_state = WAIT_PO_PI_COUNTER_VAL; end end WAIT_PO_PI_COUNTER_VAL: begin if (wait_cnt_done) skip_next_state = READ_PO_PI_COUNTER_VAL; end PO_PI_TAP_ADJ_DONE: begin tap_adj_done = 1'b1; end default: begin skip_next_state = IDLE; end endcase end //Debug assign dbg_skip_cal[4:0] = skip_state_r; assign dbg_skip_cal[7:5] = po_c_inc_cnt; assign dbg_skip_cal[13:8] = po_stg3_inc_cnt; assign dbg_skip_cal[19:14] = po_stg3_dec_cnt; assign dbg_skip_cal[25:20] = po_stg2_inc_cnt; assign dbg_skip_cal[31:26] = po_stg2_dec_cnt; assign dbg_skip_cal[37:32] = pi_stg2_inc_cnt; assign dbg_skip_cal[43:38] = pi_stg2_dec_cnt; assign dbg_skip_cal[48:44] = idelay_inc_cnt; assign dbg_skip_cal[54:49] = byte_cnt_r; assign dbg_skip_cal[55] = po_c_inc_active; assign dbg_skip_cal[56] = po_stg3_inc_active; assign dbg_skip_cal[57] = po_stg3_dec_active; assign dbg_skip_cal[58] = po_stg2_inc_active; assign dbg_skip_cal[59] = po_stg2_dec_active; assign dbg_skip_cal[60] = pi_stg2_inc_active; assign dbg_skip_cal[61] = pi_stg2_dec_active; assign dbg_skip_cal[62] = idelay_inc_active; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v4_0_poc_cc.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 20 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out characterization and control. Logic to interface with // Chipscope and control. Intended to support real time observation. Largely // not generated for production implementations. // // Also generates debug bus. Concept is a dynamic portion that can be used // to examine the POC while it is operating, and a logging portion that // stores per lane results. // //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_poc_cc # (parameter TCQ = 100, parameter CCENABLE = 0, parameter LANE_CNT_WIDTH = 2, parameter PCT_SAMPS_SOLID = 95, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter SMWIDTH = 2, parameter TAPCNTRWIDTH = 7) (/*AUTOARG*/ // Outputs samples, samps_solid_thresh, poc_error, dbg_poc, // Inputs psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge, mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center, lane, mmcm_edge_detect_rdy, poc_backup, sm, tap, run, run_end, run_polarity, run_too_small, samp_cntr, samps_hi, samps_hi_held, samps_zero, samps_one, run_ends, diff, left, right, window_center, edge_center ); // Remember SAMPLES is whole number counting. Zero corresponds to one sample. localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01; output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; input psen; input clk, rst; input ktap_at_right_edge, ktap_at_left_edge; input mmcm_lbclk_edge_aligned; wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned; input mmcm_edge_detect_done; reg mmcm_edge_detect_done_r; always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done; wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r; reg [6:0] aligned_cnt_r; wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done}; always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns; reg poc_error_r; wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r); always @(posedge clk) poc_error_r <= #TCQ poc_error_ns; output poc_error; assign poc_error = poc_error_r; input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right; input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left; input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center; generate if (CCENABLE == 0) begin : no_characterization assign samples = SAMPLES[SAMPCNTRWIDTH:0]; assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0]; end else begin : characterization end endgenerate reg [1023:0] dbg_poc_r; output [1023:0] dbg_poc; assign dbg_poc = dbg_poc_r; input [LANE_CNT_WIDTH-1:0] lane; input mmcm_edge_detect_rdy; input poc_backup; input [SMWIDTH-1:0] sm; input [TAPCNTRWIDTH-1:0] tap; input [TAPCNTRWIDTH-1:0] run; input run_end; input run_polarity; input run_too_small; input [SAMPCNTRWIDTH-1:0] samp_cntr; input [SAMPCNTRWIDTH:0] samps_hi; input [SAMPCNTRWIDTH:0] samps_hi_held; input samps_zero, samps_one; input [1:0] run_ends; input [TAPCNTRWIDTH+1:0] diff; always @(*) begin dbg_poc_r[99:0] = 'b0; dbg_poc_r[1023:900] = 'b0; dbg_poc_r[0] = mmcm_edge_detect_rdy; dbg_poc_r[1] = mmcm_edge_detect_done; dbg_poc_r[2] = ktap_at_right_edge; dbg_poc_r[3] = ktap_at_left_edge; dbg_poc_r[4] = mmcm_lbclk_edge_aligned; dbg_poc_r[5] = poc_backup; dbg_poc_r[6+:SMWIDTH] = sm; dbg_poc_r[10+:TAPCNTRWIDTH] = tap; dbg_poc_r[20+:TAPCNTRWIDTH] = run; dbg_poc_r[30] = run_end; dbg_poc_r[31] = run_polarity; dbg_poc_r[32] = run_too_small; dbg_poc_r[33+:SAMPCNTRWIDTH] = samp_cntr; dbg_poc_r[49+:SAMPCNTRWIDTH+1] = samps_hi; dbg_poc_r[66+:SAMPCNTRWIDTH+1] = samps_hi_held; dbg_poc_r[83] = samps_zero; dbg_poc_r[84] = samps_one; dbg_poc_r[86:85] = run_ends; dbg_poc_r[87+:TAPCNTRWIDTH+2] = diff; end // always @ (*) input [TAPCNTRWIDTH-1:0] left, right; input [TAPCNTRWIDTH:0] window_center, edge_center; reg [899:100] dbg_poc_ns; always @(posedge clk) dbg_poc_r[899:100] <= #TCQ dbg_poc_ns; always @(*) begin if (rst) dbg_poc_ns = 'b0; else begin dbg_poc_ns = dbg_poc_r[899:100]; if (mmcm_edge_detect_rdy && lane < 8) begin dbg_poc_ns[(lane+1)*100] = poc_backup; dbg_poc_ns[(lane+1)*100+1] = dbg_poc_ns[(lane+1)*100+1] || run_too_small; dbg_poc_ns[(lane+1)*100+10+:TAPCNTRWIDTH] = left; dbg_poc_ns[(lane+1)*100+20+:TAPCNTRWIDTH] = right; dbg_poc_ns[(lane+1)*100+30+:TAPCNTRWIDTH+1] = window_center; dbg_poc_ns[(lane+1)*100+41+:TAPCNTRWIDTH+1] = edge_center; end end end endmodule // mig_7series_v4_0_poc_cc ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v4_0_poc_meta.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Fri 24 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser output calibration edge store. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_poc_edge_store # (parameter TCQ = 100, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 112) (/*AUTOARG*/ // Outputs fall_lead, fall_trail, rise_lead, rise_trail, // Inputs clk, run_polarity, run_end, select0, select1, tap, run ); input clk; input run_polarity; input run_end; input select0; input select1; input [TAPCNTRWIDTH-1:0] tap; input [TAPCNTRWIDTH-1:0] run; wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run : tap - run; wire run_end_this = run_end && select0 && select1; reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r; output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail; assign fall_lead = fall_lead_r; assign fall_trail = fall_trail_r; assign rise_lead = rise_lead_r; assign rise_trail = rise_trail_r; wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r; wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] : rise_trail_r; wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r; wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] : fall_trail_r; always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns; always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns; always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns; always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns; endmodule // mig_7series_v4_0_poc_edge_store // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_meta.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v4_0_poc_meta.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser output calibration meta controller. // // Compute center of the window set up with with the ktap_left, // ktap_right dance (hereafter "the window"). Also compute center of the // edge (hereafter "the edge") to be aligned in the center // of this window. // // Following the ktap_left/right dance, the to be centered edge is // always left at the right edge of the window // if SCANFROMRIGHT == 1, and the left edge otherwise. // // An assumption is the rise(0) case has a window wider than the noise on the // edge. The noise case with the possibly narrow window // will always be shifted by 90. And the fall(180) case is shifted by // 90 twice. Hence when we start, we can assume the center of the // edge is to the right/left of the the window center. // // The actual hardware does not necessarily monotonically appear to // move the window centers. Because of noise, it is possible for the // centered edge to move opposite the expected direction with a tap increment. // // This problem is solved by computing the absolute difference between // the centers and the circular distance between the centers. These will // be the same until the difference transits through zero. Then the circular // difference will jump to almost the value of TAPSPERKCLK. // // The window center computation is done at 1/2 tap increments to maintain // resolution through the divide by 2 for centering. // // There is a corner case of when the shift is greater than 180 degress. In // this case the absolute difference and the circular difference will be // unequal at the beginning of the alignment. This is solved by latching // if they are equal at the end of each cycle. The completion must see // that they were equal in the previous cycle, but are not equal in this cycle. // // Since the phaser out steps are of unknown size, it is possible to overshoot // the center. The previous difference is recorded and if its less than the current // difference, poc_backup is driven high. // //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_poc_meta # (parameter SCANFROMRIGHT = 0, parameter TCQ = 100, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 112) (/*AUTOARG*/ // Outputs run_ends, mmcm_edge_detect_done, edge_center, left, right, window_center, diff, poc_backup, mmcm_lbclk_edge_aligned, // Inputs rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end, run_polarity, rise_lead_right, rise_trail_left, rise_lead_center, rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets, use_noise_window, ktap_at_right_edge, ktap_at_left_edge ); localparam NINETY = TAPSPERKCLK/4; function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a, input [1:0] b, input integer base); integer offset_ii; begin offset_ii = (a + b * NINETY) < base ? (a + b * NINETY) : (a + b * NINETY - base); offset = offset_ii[TAPCNTRWIDTH-1:0]; end endfunction // offset function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, input [TAPCNTRWIDTH-1:0] b, input integer base); begin mod_sub = (a>=b) ? a-b : a+base-b; end endfunction // mod_sub function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left, input [TAPCNTRWIDTH-1:0] diff, input integer base); integer center_ii; begin center_ii = ({left, 1'b0} + diff < base * 2) ? {left, 1'b0} + diff + 32'h0 : {left, 1'b0} + diff - base * 2; center = center_ii[TAPCNTRWIDTH:0]; end endfunction // center input rst; input clk; input mmcm_edge_detect_rdy; reg [1:0] run_ends_r; input run_too_small; reg run_too_small_r1, run_too_small_r2, run_too_small_r3; always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1; always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1; always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2; wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ; // This input used only for the SVA. input [TAPCNTRWIDTH-1:0] run; input run_end; reg run_end_r, run_end_r1, run_end_r2, run_end_r3; always @(posedge clk) run_end_r <= #TCQ run_end; always @(posedge clk) run_end_r1 <= #TCQ run_end_r; always @(posedge clk) run_end_r2 <= #TCQ run_end_r1; always @(posedge clk) run_end_r3 <= #TCQ run_end_r2; input run_polarity; reg run_polarity_held_ns, run_polarity_held_r; always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns; always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r; reg [1:0] run_ends_ns; always @(posedge clk) run_ends_r <= #TCQ run_ends_ns; always @(*) begin run_ends_ns = run_ends_r; if (reset_run_ends) run_ends_ns = 2'b0; else case (run_ends_r) 2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r}; 2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3}; endcase // case (run_ends_r) end // always @ begin output [1:0] run_ends; assign run_ends = run_ends_r; reg done_r; wire done_ns = mmcm_edge_detect_rdy && &run_ends_r; always @(posedge clk) done_r <= #TCQ done_ns; output mmcm_edge_detect_done; assign mmcm_edge_detect_done = done_r; input [TAPCNTRWIDTH-1:0] rise_lead_right; input [TAPCNTRWIDTH-1:0] rise_trail_left; input [TAPCNTRWIDTH-1:0] rise_lead_center; input [TAPCNTRWIDTH-1:0] rise_trail_center; input [TAPCNTRWIDTH-1:0] rise_trail_right; input [TAPCNTRWIDTH-1:0] rise_lead_left; input [1:0] ninety_offsets; wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets; wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK); wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK); reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r; always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns; always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns; wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK); reg [TAPCNTRWIDTH-1:0] edge_diff_r; always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns; wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK); reg [TAPCNTRWIDTH:0] edge_center_r; always @(posedge clk) edge_center_r <= #TCQ edge_center_ns; output [TAPCNTRWIDTH:0] edge_center; assign edge_center = edge_center_r; input use_noise_window; output [TAPCNTRWIDTH-1:0] left, right; assign left = use_noise_window ? rise_lead_left : rise_trail_left; assign right = use_noise_window ? rise_trail_right : rise_lead_right; wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK); reg [TAPCNTRWIDTH-1:0] center_diff_r; always @(posedge clk) center_diff_r <= #TCQ center_diff_ns; wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK); reg [TAPCNTRWIDTH:0] window_center_r; always @(posedge clk) window_center_r <= #TCQ window_center_ns; output [TAPCNTRWIDTH:0] window_center; assign window_center = window_center_r; localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2; wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r}; wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r}; wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center ? right_center - left_center : right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center; reg [TAPCNTRWIDTH+1:0] diff_r; always @(posedge clk) diff_r <= #TCQ diff_ns; output [TAPCNTRWIDTH+1:0] diff; assign diff = diff_r; wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2 ? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r : diff_r; reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r; always @(posedge clk) prev_r <= #TCQ prev_ns; always @(*) prev_ns = done_ns ? diff_r : prev_r; input ktap_at_right_edge; input ktap_at_left_edge; wire centering = !(ktap_at_right_edge || ktap_at_left_edge); wire diffs_eq = abs_diff == diff_r; reg diffs_eq_ns, diffs_eq_r; always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r); always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns; reg edge_aligned_r; reg prev_valid_ns, prev_valid_r; always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns; always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns; wire indicate_alignment = ~rst && centering && done_ns; wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r); always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns; reg poc_backup_r; wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r; always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; output poc_backup; assign poc_backup = poc_backup_r; output mmcm_lbclk_edge_aligned; assign mmcm_lbclk_edge_aligned = edge_aligned_r; endmodule // mig_7series_v4_0_poc_meta // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v4_0_poc_pd.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff // prevents any noise that could happen when the phase shift clock is very // nearly aligned to the fabric clock. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_poc_pd # (parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SIM_CAL_OPTION = "NONE", parameter TCQ = 100) (/*AUTOARG*/ // Outputs pd_out, // Inputs iddr_rst, clk, kclk, mmcm_ps_clk ); input iddr_rst; input clk; input kclk; input mmcm_ps_clk; wire q1; IDDR # (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), .INIT_Q1 (1'b0), .INIT_Q2 (1'b0), .SRTYPE ("SYNC")) u_phase_detector (.Q1 (q1), .Q2 (), .C (mmcm_ps_clk), .CE (1'b1), .D (kclk), .R (iddr_rst), .S (1'b0)); // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME reg pos_edge_samp; generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes always @(posedge clk) pos_edge_samp <= #TCQ q1; end else begin : eXes reg q1_delayed; reg rising_clk_seen; always @(posedge mmcm_ps_clk) begin rising_clk_seen <= 1'b0; q1_delayed <= 1'bx; end always @(posedge clk) begin rising_clk_seen = 1'b1; if (rising_clk_seen) q1_delayed <= q1; end always @(posedge clk) begin pos_edge_samp <= q1_delayed; end end endgenerate reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; output pd_out; assign pd_out = pd_out_r; endmodule // mic_7series_v4_0_poc_pd ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v4_0_poc_tap_base.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: All your taps are belong to us. // //In general, this block should be able to start up with a random initialization of //the various counters. But its probably easier, more normative and quicker time to solution //to just initialize to zero with rst. // // Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For // each MMCM tap it samples the phase detector output a programmable number of times. // When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM // tap begins. // // Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround // for a bug in the MMCM where its output may have noise for a period following // the PSEN. // // Samples are taken every other fabric clock. This is because the MMCM phase shift // clock operates at half the fabric clock. The reason for this is unknown. // // At the end of the sampling period, a filtering step is implemented. samps_solid_thresh // is the minumum number of samples that must be seen to declare a solid zero or one. If // neithr the one and zero samples cross this threshold, then the sampple is declared fuzz. // // A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample // is observed. // // A "run" counter is maintained. If the current sample is fuzz, or opposite polarity // from a previous sample, then the run counter is reset. If the current sample is the // same polarity run_polarity, then the run counter is incremented. // // If a run_polarity reversal or fuzz is observed and the run counter is not zero // then the run_end strobe is pulsed. // //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_poc_tap_base # (parameter MMCM_SAMP_WAIT = 10, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter SAMPCNTRWIDTH = 8, parameter SMWIDTH = 2, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 112) (/*AUTOARG*/ // Outputs psincdec, psen, run, run_end, run_too_small, run_polarity, samp_cntr, samps_hi, samps_hi_held, tap, sm, samps_zero, samps_one, // Inputs pd_out, clk, samples, samps_solid_thresh, psdone, rst, poc_sample_pd ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input pd_out; input clk; input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; input psdone; input rst; localparam ONE = 1; localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT); reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r; always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns; reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pd_out; wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out; output psincdec; assign psincdec = 1'b1; output psen; reg psen_int; assign psen = psen_int; reg [TAPCNTRWIDTH-1:0] run_r; reg [TAPCNTRWIDTH-1:0] run_ns; always @(posedge clk) run_r <= #TCQ run_ns; output [TAPCNTRWIDTH-1:0] run; assign run = run_r; output run_end; reg run_end_int; assign run_end = run_end_int; output run_too_small; reg run_too_small_r, run_too_small_ns; always @(*) run_too_small_ns = run_end && (run < TAPSPERKCLK/4); always @(posedge clk) run_too_small_r <= #TCQ run_too_small_ns; assign run_too_small = run_too_small_r; reg run_polarity_r; reg run_polarity_ns; always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns; output run_polarity; assign run_polarity = run_polarity_r; reg [SAMPCNTRWIDTH-1:0] samp_cntr_r; reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns; always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns; output [SAMPCNTRWIDTH-1:0] samp_cntr; assign samp_cntr = samp_cntr_r; reg [SAMPCNTRWIDTH:0] samps_hi_r; reg [SAMPCNTRWIDTH:0] samps_hi_ns; always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns; output [SAMPCNTRWIDTH:0] samps_hi; assign samps_hi = samps_hi_r; reg [SAMPCNTRWIDTH:0] samps_hi_held_r; reg [SAMPCNTRWIDTH:0] samps_hi_held_ns; always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns; output [SAMPCNTRWIDTH:0] samps_hi_held; assign samps_hi_held = samps_hi_held_r; reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r; always @(posedge clk) tap_r <= #TCQ tap_ns; output [TAPCNTRWIDTH-1:0] tap; assign tap = tap_r; reg [SMWIDTH-1:0] sm_ns; reg [SMWIDTH-1:0] sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; output [SMWIDTH-1:0] sm; assign sm = sm_r; reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r; always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns; always @(posedge clk) samps_one_r <= #TCQ samps_one_ns; output samps_zero, samps_one; assign samps_zero = samps_zero_r; assign samps_one = samps_one_r; // Interesting corner case... what if both samps_zero and samps_one are // hi? Could happen for small sample counts and reasonable values of // PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment // consistently breaks tie with samps_one_r. wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r; always @(*) begin samps_zero_ns = samps_zero_r; samps_one_ns = samps_one_r; samps_zero_ns = samps_lo >= samps_solid_thresh; samps_one_ns = samps_hi_r >= samps_solid_thresh; end // always @ begin wire new_polarity = run_polarity_ns ^ run_polarity_r; input poc_sample_pd; always @(*) begin if (rst == 1'b1) begin // RESET next states psen_int = 1'b0; sm_ns = /*AUTOLINK("SAMPLE")*/2'd0; run_polarity_ns = 1'b0; run_ns = {TAPCNTRWIDTH{1'b0}}; run_end_int = 1'b0; samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; tap_ns = {TAPCNTRWIDTH{1'b0}}; samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0]; samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}}; end else begin // Default next states; psen_int = 1'b0; sm_ns = sm_r; run_polarity_ns = run_polarity_r; run_ns = run_r; run_end_int = 1'b0; samp_cntr_ns = samp_cntr_r; samps_hi_ns = samps_hi_r; tap_ns = tap_r; samp_wait_ns = samp_wait_r; if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0]; samps_hi_held_ns = samps_hi_held_r; // State based actions and next states. case (sm_r) /*AL("SAMPLE")*/2'd0: begin if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0]; if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1; samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel}; samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0]; end end /*AL("COMPUTE")*/2'd1:begin sm_ns = /*AK("PSEN")*/2'd2; end /*AL("PSEN")*/2'd2:begin sm_ns = /*AK("PSDONE_WAIT")*/2'd3; psen_int = 1'b1; samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; samps_hi_held_ns = samps_hi_r; tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0]) ? tap_r + ONE[TAPCNTRWIDTH-1:0] : {TAPCNTRWIDTH{1'b0}}; if (run_polarity_r) begin if (samps_zero_r) run_polarity_ns = 1'b0; end else begin if (samps_one_r) run_polarity_ns = 1'b1; end if (new_polarity) begin run_ns ={TAPCNTRWIDTH{1'b0}}; run_end_int = 1'b1; end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0]; end /*AL("PSDONE_WAIT")*/2'd3:begin samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0]; if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0; end endcase // case (sm_r) end // else: !if(rst == 1'b1) end // always @ (*) endmodule // mig_7series_v4_0_poc_tap_base // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // verilog-autolabel-prefix: "2'd" // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_top.v ================================================ //***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v4_0_poc_top.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out calibration top. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_poc_top # (parameter LANE_CNT_WIDTH = 2, parameter MMCM_SAMP_WAIT = 10, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter CCENABLE = 0, parameter SCANFROMRIGHT = 0, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK =112) (/*AUTOARG*/ // Outputs psincdec, poc_error, dbg_poc, psen, rise_lead_right, rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, poc_backup, // Inputs use_noise_window, rst, psdone, poc_sample_pd, pd_out, ninety_offsets, mmcm_edge_detect_rdy, lane, ktap_at_right_edge, ktap_at_left_edge, clk ); localparam SMWIDTH = 2; /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ... input ktap_at_left_edge; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ... input ktap_at_right_edge; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ... input [LANE_CNT_WIDTH-1:0] lane; // To u_poc_cc of mig_7series_v4_0_poc_cc.v input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ... input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v4_0_poc_meta.v input pd_out; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v input poc_sample_pd; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v input psdone; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v input rst; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ... input use_noise_window; // To u_poc_meta of mig_7series_v4_0_poc_meta.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [1023:0] dbg_poc; // From u_poc_cc of mig_7series_v4_0_poc_cc.v output poc_error; // From u_poc_cc of mig_7series_v4_0_poc_cc.v output psincdec; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v // End of automatics /*AUTOwire*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [TAPCNTRWIDTH+1:0] diff; // From u_poc_meta of mig_7series_v4_0_poc_meta.v wire [TAPCNTRWIDTH:0] edge_center; // From u_poc_meta of mig_7series_v4_0_poc_meta.v wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] left; // From u_poc_meta of mig_7series_v4_0_poc_meta.v wire [TAPCNTRWIDTH-1:0] right; // From u_poc_meta of mig_7series_v4_0_poc_meta.v wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire run_end; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [1:0] run_ends; // From u_poc_meta of mig_7series_v4_0_poc_meta.v wire run_polarity; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire run_too_small; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [SAMPCNTRWIDTH-1:0] samp_cntr; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v4_0_poc_cc.v wire [SAMPCNTRWIDTH:0] samps_hi; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire samps_one; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v4_0_poc_cc.v wire samps_zero; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [SMWIDTH-1:0] sm; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v wire [TAPCNTRWIDTH:0] window_center; // From u_poc_meta of mig_7series_v4_0_poc_meta.v // End of automatics output psen; output [TAPCNTRWIDTH-1:0] rise_lead_right; output [TAPCNTRWIDTH-1:0] rise_trail_right; output mmcm_edge_detect_done; output mmcm_lbclk_edge_aligned; output poc_backup; mig_7series_v4_0_poc_tap_base # (/*AUTOINSTPARAM*/ // Parameters .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SMWIDTH (SMWIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_tap_base (/*AUTOINST*/ // Outputs .psen (psen), .psincdec (psincdec), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .run_too_small (run_too_small), .samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]), .samps_hi (samps_hi[SAMPCNTRWIDTH:0]), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .samps_one (samps_one), .samps_zero (samps_zero), .sm (sm[SMWIDTH-1:0]), .tap (tap[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .pd_out (pd_out), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); mig_7series_v4_0_poc_meta # (/*AUTOINSTPARAM*/ // Parameters .SCANFROMRIGHT (SCANFROMRIGHT), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_meta (/*AUTOINST*/ // Outputs .diff (diff[TAPCNTRWIDTH+1:0]), .edge_center (edge_center[TAPCNTRWIDTH:0]), .left (left[TAPCNTRWIDTH-1:0]), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), .right (right[TAPCNTRWIDTH-1:0]), .run_ends (run_ends[1:0]), .window_center (window_center[TAPCNTRWIDTH:0]), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .run_too_small (run_too_small), .use_noise_window (use_noise_window)); /*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (ktap_at_@_edge), .select1 (1'b1),)*/ mig_7series_v4_0_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_right (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_right_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v4_0_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_left (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_left_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); wire not_ktap_at_right_edge = ~ktap_at_right_edge; wire not_ktap_at_left_edge = ~ktap_at_left_edge; /*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (not_ktap_at_right_edge), .select1 (not_ktap_at_left_edge),)*/ mig_7series_v4_0_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_center (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (not_ktap_at_right_edge), // Templated .select1 (not_ktap_at_left_edge), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v4_0_poc_cc # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (CCENABLE), .LANE_CNT_WIDTH (LANE_CNT_WIDTH), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .SMWIDTH (SMWIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TCQ (TCQ)) u_poc_cc (/*AUTOINST*/ // Outputs .dbg_poc (dbg_poc[1023:0]), .poc_error (poc_error), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), // Inputs .clk (clk), .diff (diff[TAPCNTRWIDTH+1:0]), .edge_center (edge_center[TAPCNTRWIDTH:0]), .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .lane (lane[LANE_CNT_WIDTH-1:0]), .left (left[TAPCNTRWIDTH-1:0]), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), .psen (psen), .right (right[TAPCNTRWIDTH-1:0]), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_ends (run_ends[1:0]), .run_polarity (run_polarity), .run_too_small (run_too_small), .samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]), .samps_hi (samps_hi[SAMPCNTRWIDTH:0]), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .samps_one (samps_one), .samps_zero (samps_zero), .sm (sm[SMWIDTH-1:0]), .tap (tap[TAPCNTRWIDTH-1:0]), .window_center (window_center[TAPCNTRWIDTH:0])); endmodule // mig_7series_v4_0_poc_top // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_cmd.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps // User interface command port. module mig_7series_v4_0_ui_cmd # ( parameter TCQ = 100, parameter ADDR_WIDTH = 33, parameter BANK_WIDTH = 3, parameter COL_WIDTH = 12, parameter DATA_BUF_ADDR_WIDTH = 5, parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16, parameter RANKS = 4, parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN" ) (/*AUTOARG*/ // Outputs app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority, rd_accepted, wr_accepted, data_buf_addr, // Inputs rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd, app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r ); input rst; input clk; input accept_ns; input rd_buf_full; input wr_req_16; wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16; reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */; always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns; output wire app_rdy; assign app_rdy = app_rdy_r; input [ADDR_WIDTH-1:0] app_addr; input [2:0] app_cmd; input app_sz; input app_hi_pri; input app_en; reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}}; reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}}; reg [2:0] app_cmd_r1; reg [2:0] app_cmd_r2; reg app_sz_r1; reg app_sz_r2; reg app_hi_pri_r1; reg app_hi_pri_r2; reg app_en_r1; reg app_en_r2; wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1; wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2; wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1; wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2; wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1; wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2; wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1; wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2; wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1); wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2); always @(posedge clk) begin if (rst) begin app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}}; app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}}; end else begin app_addr_r1 <= #TCQ app_addr_ns1; app_addr_r2 <= #TCQ app_addr_ns2; end app_cmd_r1 <= #TCQ app_cmd_ns1; app_cmd_r2 <= #TCQ app_cmd_ns2; app_sz_r1 <= #TCQ app_sz_ns1; app_sz_r2 <= #TCQ app_sz_ns2; app_hi_pri_r1 <= #TCQ app_hi_pri_ns1; app_hi_pri_r2 <= #TCQ app_hi_pri_ns2; app_en_r1 <= #TCQ app_en_ns1; app_en_r2 <= #TCQ app_en_ns2; end // always @ (posedge clk) wire use_addr_lcl = app_en_r2 && app_rdy_r; output wire use_addr; assign use_addr = use_addr_lcl; output wire [RANK_WIDTH-1:0] rank; output wire [BANK_WIDTH-1:0] bank; output wire [ROW_WIDTH-1:0] row; output wire [COL_WIDTH-1:0] col; output wire size; output wire [2:0] cmd; output wire hi_priority; /* assign col = app_rdy_r ? app_addr_r1[0+:COL_WIDTH] : app_addr_r2[0+:COL_WIDTH];*/ generate begin if (MEM_ADDR_ORDER == "TG_TEST") begin assign col[4:0] = app_rdy_r ? app_addr_r1[0+:5] : app_addr_r2[0+:5]; if (RANKS==1) begin assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+:2] : app_addr_r2[5+3+BANK_WIDTH+:2]; assign col[COL_WIDTH-3:5] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7] : app_addr_r2[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7]; end else begin assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+:2] : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+:2]; assign col[COL_WIDTH-3:5] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7] : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7]; end assign row[2:0] = app_rdy_r ? app_addr_r1[5+:3] : app_addr_r2[5+:3]; if (RANKS==1) begin assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+2+:2] : app_addr_r2[5+3+BANK_WIDTH+2+:2]; assign row[ROW_WIDTH-3:3] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5] : app_addr_r2[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]; end else begin assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+:2] : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+:2]; assign row[ROW_WIDTH-3:3] = app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5] : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]; end assign bank = app_rdy_r ? app_addr_r1[5+3+:BANK_WIDTH] : app_addr_r2[5+3+:BANK_WIDTH]; assign rank = (RANKS == 1) ? 1'b0 : app_rdy_r ? app_addr_r1[5+3+BANK_WIDTH+:RANK_WIDTH] : app_addr_r2[5+3+BANK_WIDTH+:RANK_WIDTH]; end else if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin assign col = app_rdy_r ? app_addr_r1[0+:COL_WIDTH] : app_addr_r2[0+:COL_WIDTH]; assign row = app_rdy_r ? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH] : app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]; assign bank = app_rdy_r ? app_addr_r1[COL_WIDTH+:BANK_WIDTH] : app_addr_r2[COL_WIDTH+:BANK_WIDTH]; assign rank = (RANKS == 1) ? 1'b0 : app_rdy_r ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH] : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]; end else begin assign col = app_rdy_r ? app_addr_r1[0+:COL_WIDTH] : app_addr_r2[0+:COL_WIDTH]; assign row = app_rdy_r ? app_addr_r1[COL_WIDTH+:ROW_WIDTH] : app_addr_r2[COL_WIDTH+:ROW_WIDTH]; assign bank = app_rdy_r ? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH] : app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]; assign rank = (RANKS == 1) ? 1'b0 : app_rdy_r ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH] : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]; end end endgenerate /* assign rank = (RANKS == 1) ? 1'b0 : app_rdy_r ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH] : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];*/ assign size = app_rdy_r ? app_sz_r1 : app_sz_r2; assign cmd = app_rdy_r ? app_cmd_r1 : app_cmd_r2; assign hi_priority = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2; wire request_accepted = use_addr_lcl && app_rdy_r; wire rd = app_cmd_r2[1:0] == 2'b01; wire wr = app_cmd_r2[1:0] == 2'b00; wire wr_bytes = app_cmd_r2[1:0] == 2'b11; wire write = wr || wr_bytes; output wire rd_accepted; assign rd_accepted = request_accepted && rd; output wire wr_accepted; assign wr_accepted = request_accepted && write; input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr; input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr; assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr; endmodule // ui_cmd // Local Variables: // verilog-library-directories:(".") // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_rd_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface read buffer. Re orders read data returned from the // memory controller back to the request order. // // Consists of a large buffer for the data, a status RAM and two counters. // // The large buffer is implemented with distributed RAM in 6 bit wide, // 1 read, 1 write mode. The status RAM is implemented with a distributed // RAM configured as 2 bits wide 1 read/write, 1 read mode. // // As read requests are received from the application, the data_buf_addr // counter supplies the data_buf_addr sent into the memory controller. // With each read request, the counter is incremented, eventually rolling // over. This mechanism labels each read request with an incrementing number. // // When the memory controller returns read data, it echos the original // data_buf_addr with the read data. // // The status RAM is indexed with the same address as the data buffer // RAM. Each word of the data buffer RAM has an associated status bit // and "end" bit. Requests of size 1 return a data burst on two consecutive // states. Requests of size zero return with a single assertion of rd_data_en. // // Upon returning data, the status and end bits are updated for each // corresponding location in the status RAM indexed by the data_buf_addr // echoed on the rd_data_addr field. // // The other side of the status and data RAMs is indexed by the rd_buf_indx. // The rd_buf_indx constantly monitors the status bit it is currently // pointing to. When the status becomes set to the proper state (more on // this later) read data is returned to the application, and the rd_buf_indx // is incremented. // // At rst the rd_buf_indx is initialized to zero. Data will not have been // returned from the memory controller yet, so there is nothing to return // to the application. Evenutally, read requests will be made, and the // memory controller will return the corresponding data. The memory // controller may not return this data in the request order. In which // case, the status bit at location zero, will not indicate // the data for request zero is ready. Eventually, the memory controller // will return data for request zero. The data is forwarded on to the // application, and rd_buf_indx is incremented to point to the next status // bits and data in the buffers. The status bit will be examined, and if // data is valid, this data will be returned as well. This process // continues until the status bit indexed by rd_buf_indx indicates data // is not ready. This may be because the rd_data_buf // is empty, or that some data was returned out of order. Since rd_buf_indx // always increments sequentially, data is always returned to the application // in request order. // // Some further discussion of the status bit is in order. The rd_data_buf // is a circular buffer. The status bit is a single bit. Distributed RAM // supports only a single write port. The write port is consumed by // memory controller read data updates. If a simple '1' were used to // indicate the status, when rd_data_indx rolled over it would immediately // encounter a one for a request that may not be ready. // // This problem is solved by causing read data returns to flip the // status bit, and adding hi order bit beyond the size required to // index the rd_data_buf. Data is considered ready when the status bit // and this hi order bit are equal. // // The status RAM needs to be initialized to zero after reset. This is // accomplished by cycling through all rd_buf_indx valus and writing a // zero to the status bits directly following deassertion of reset. This // mechanism is used for similar purposes // for the wr_data_buf. // // When ORDERING == "STRICT", read data reordering is unnecessary. For thi // case, most of the logic in the block is not generated. `timescale 1 ps / 1 ps // User interface read data. module mig_7series_v4_0_ui_rd_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ORDERING = "NORM" ) (/*AUTOARG*/ // Outputs ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r, app_ecc_single_err, // Inputs rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end, rd_data, ecc_multiple, ecc_single, rd_accepted ); input rst; input clk; output wire ram_init_done_r; output wire [3:0] ram_init_addr; // rd_buf_indx points to the status and data storage rams for // reading data out to the app. reg [5:0] rd_buf_indx_r; reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */; assign ram_init_done_r = ram_init_done_r_lcl; wire app_rd_data_valid_ns; wire single_data; reg [5:0] rd_buf_indx_ns; generate begin : rd_buf_indx wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns; // Loop through all status write addresses once after rst. Initializes // the status and pointer RAMs. wire ram_init_done_ns = ~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f)); always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns; always @(/*AS*/rd_buf_indx_r or rst or single_data or upd_rd_buf_indx) begin rd_buf_indx_ns = rd_buf_indx_r; if (rst) rd_buf_indx_ns = 6'b0; else if (upd_rd_buf_indx) rd_buf_indx_ns = // need to use every slot of RAMB32 if all address bits are used rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data); end always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns; end endgenerate assign ram_init_addr = rd_buf_indx_r[3:0]; input rd_data_en; input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input rd_data_offset; input rd_data_end; input [APP_DATA_WIDTH-1:0] rd_data; output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */; output reg app_rd_data_end; output reg [APP_DATA_WIDTH-1:0] app_rd_data; input [(2*nCK_PER_CLK)-1:0] ecc_multiple; input [(2*nCK_PER_CLK)-1:0] ecc_single; reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0; reg [2*nCK_PER_CLK-1:0] app_ecc_single_err_r = 'b0; output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; output wire [2*nCK_PER_CLK-1:0] app_ecc_single_err; assign app_ecc_multiple_err = app_ecc_multiple_err_r; assign app_ecc_single_err = app_ecc_single_err_r; input rd_accepted; output wire rd_buf_full; output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; // Compute dimensions of read data buffer. Depending on width of // DQ bus and DRAM CK // to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in // single write, single read, 6 bit wide mode. localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*2*nCK_PER_CLK); localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6); localparam REMAINDER = RD_BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate if (ORDERING == "STRICT") begin : strict_mode assign app_rd_data_valid_ns = 1'b0; assign single_data = 1'b0; assign rd_buf_full = 1'b0; reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns = rst ? 0 : rd_data_buf_addr_r_lcl + rd_accepted; always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; assign rd_data_buf_addr_r = rd_data_buf_addr_ns; // app_* signals required to be registered. if (ECC == "OFF") begin : ecc_off always @(/*AS*/rd_data) app_rd_data = rd_data; always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en; always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end; end else begin : ecc_on always @(posedge clk) app_rd_data <= #TCQ rd_data; always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en; always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple; always @(posedge clk) app_ecc_single_err_r <= #TCQ ecc_single; end end else begin : not_strict_mode wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */; // In configurations where read data is returned in a single fabric cycle // the offset is always zero and we can use the bit to get a deeper // FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH // is set to use them all, discard the offset. Otherwise, include the // offset. wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ? rd_data_addr : {rd_data_addr, rd_data_offset}; wire [1:0] rd_status; // Instantiate status RAM. One bit for status and one for "end". begin : status_ram // Turns out read to write back status is a timing path. Update // the status in the ram on the state following the read. Bypass // the write data into the status read path. wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl ? rd_buf_wr_addr : rd_buf_indx_r[4:0]; reg [4:0] status_ram_wr_addr_r; always @(posedge clk) status_ram_wr_addr_r <= #TCQ status_ram_wr_addr_ns; wire [1:0] wr_status; // Not guaranteed to write second status bit. If it is written, always // copy in the first status bit. reg wr_status_r1; always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0]; wire [1:0] status_ram_wr_data_ns = ram_init_done_r_lcl ? {rd_data_end, ~(rd_data_offset ? wr_status_r1 : wr_status[0])} : 2'b0; reg [1:0] status_ram_wr_data_r; always @(posedge clk) status_ram_wr_data_r <= #TCQ status_ram_wr_data_ns; reg rd_buf_we_r1; always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we; RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_status), .DOB(), .DOC(wr_status), .DOD(), .DIA(status_ram_wr_data_r), .DIB(2'b0), .DIC(status_ram_wr_data_r), .DID(status_ram_wr_data_r), .ADDRA(rd_buf_indx_r[4:0]), .ADDRB(5'b0), .ADDRC(status_ram_wr_addr_ns), .ADDRD(status_ram_wr_addr_r), .WE(rd_buf_we_r1), .WCLK(clk) ); end // block: status_ram wire [RAM_WIDTH-1:0] rd_buf_out_data; begin : rd_buf wire [RAM_WIDTH-1:0] rd_buf_in_data; if (REMAINDER == 0) if (ECC == "OFF") assign rd_buf_in_data = rd_data; else assign rd_buf_in_data = {ecc_single, ecc_multiple, rd_data}; else if (ECC == "OFF") assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data}; else assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, ecc_single, ecc_multiple, rd_data}; // Dedicated copy for driving distributed RAM. (* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */; always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0]; genvar i; for (i=0; i 4) begin assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0; end endgenerate mig_7series_v4_0_ui_cmd # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_WIDTH (ADDR_WIDTH), .BANK_WIDTH (BANK_WIDTH), .COL_WIDTH (COL_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH), .RANKS (RANKS), .MEM_ADDR_ORDER (MEM_ADDR_ORDER)) ui_cmd0 (/*AUTOINST*/ // Outputs .app_rdy (app_rdy), .use_addr (use_addr), .rank (rank[RANK_WIDTH-1:0]), .bank (bank[BANK_WIDTH-1:0]), .row (row[ROW_WIDTH-1:0]), .col (col[COL_WIDTH-1:0]), .size (size), .cmd (cmd[2:0]), .hi_priority (hi_priority), .rd_accepted (rd_accepted), .wr_accepted (wr_accepted), .data_buf_addr (data_buf_addr), // Inputs .rst (rst), .clk (clk), .accept_ns (accept_ns), .rd_buf_full (rd_buf_full), .wr_req_16 (wr_req_16), .app_addr (app_addr[ADDR_WIDTH-1:0]), .app_cmd (app_cmd[2:0]), .app_sz (app_sz), .app_hi_pri (app_hi_pri), .app_en (app_en), .wr_data_buf_addr (wr_data_buf_addr), .rd_data_buf_addr_r (rd_data_buf_addr_r)); mig_7series_v4_0_ui_wr_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ECC_TEST (ECC_TEST), .CWL (CWL_M)) ui_wr_data0 (/*AUTOINST*/ // Outputs .app_wdf_rdy (app_wdf_rdy), .wr_req_16 (wr_req_16), .wr_data_buf_addr (wr_data_buf_addr[3:0]), .wr_data (wr_data[APP_DATA_WIDTH-1:0]), .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), .raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]), // Inputs .rst (rst), .clk (clk), .app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]), .app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]), .app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]), .app_wdf_wren (app_wdf_wren), .app_wdf_end (app_wdf_end), .wr_data_offset (wr_data_offset), .wr_data_addr (wr_data_addr[3:0]), .wr_data_en (wr_data_en), .wr_accepted (wr_accepted), .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr)); mig_7series_v4_0_ui_rd_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ORDERING (ORDERING)) ui_rd_data0 (/*AUTOINST*/ // Outputs .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr), .app_rd_data_valid (app_rd_data_valid), .app_rd_data_end (app_rd_data_end), .app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]), .app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]), .app_ecc_single_err (app_ecc_single_err[2*nCK_PER_CLK-1:0]), .rd_buf_full (rd_buf_full), .rd_data_buf_addr_r (rd_data_buf_addr_r), // Inputs .rst (rst), .clk (clk), .rd_data_en (rd_data_en), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .rd_data_end (rd_data_end), .rd_data (rd_data[APP_DATA_WIDTH-1:0]), .ecc_multiple (ecc_multiple), .ecc_single (ecc_single), .rd_accepted (rd_accepted)); endmodule // ui_top // Local Variables: // verilog-library-directories:("." "../mc") // End: ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v ================================================ //***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_wr_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface write data buffer. Consists of four counters, // a pointer RAM and the write data storage RAM. // // All RAMs are implemented with distributed RAM. // // Whe ordering is set to STRICT or NORM, data moves through // the write data buffer in strictly FIFO order. In RELAXED // mode, data may be retired from the write data RAM in any // order relative to the input order. This implementation // supports all ordering modes. // // The pointer RAM stores a list of pointers to the write data storage RAM. // This is a list of vacant entries. As data is written into the RAM, a // pointer is pulled from the pointer RAM and used to index the write // operation. In a semi autonomously manner, pointers are also pulled, in // the same order, and provided to the command port as the data_buf_addr. // // When the MC reads data from the write data buffer, it uses the // data_buf_addr provided with the command to extract the data from the // write data buffer. It also writes this pointer into the end // of the pointer RAM. // // The occupancy counter keeps track of how many entries are valid // in the write data storage RAM. app_wdf_rdy and app_rdy will be // de-asserted when there is no more storage in the write data buffer. // // Three sequentially incrementing counters/indexes are used to maintain // and use the contents of the pointer RAM. // // The write buffer write data address index generates the pointer // used to extract the write data address from the pointer RAM. It // is incremented with each buffer write. The counter is actually one // ahead of the current write address so that the actual data buffer // write address can be registered to give a full state to propagate to // the write data distributed RAMs. // // The data_buf_addr counter is used to extract the data_buf_addr for // the command port. It is incremented as each command is written // into the MC. // // The read data index points to the end of the list of free // buffers. When the MC fetches data from the write data buffer, it // provides the buffer address. The buffer address is used to fetch // the data, but is also written into the pointer at the location indicated // by the read data index. // // Enter and exiting a buffer full condition generates corner cases. Upon // entering a full condition, incrementing the write buffer write data // address index must be inhibited. When exiting the full condition, // the just arrived pointer must propagate through the pointer RAM, then // indexed by the current value of the write buffer write data // address counter, the value is registered in the write buffer write // data address register, then the counter can be advanced. // // The pointer RAM must be initialized with valid data after reset. This is // accomplished by stepping through each pointer RAM entry and writing // the locations address into the pointer RAM. For the FIFO modes, this means // that buffer address will always proceed in a sequential order. In the // RELAXED mode, the original write traversal will be in sequential // order, but once the MC begins to retire out of order, the entries in // the pointer RAM will become randomized. The ui_rd_data module provides // the control information for the initialization process. `timescale 1 ps / 1 ps module mig_7series_v4_0_ui_wr_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter APP_MASK_WIDTH = 32, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ECC_TEST = "OFF", parameter CWL = 5 ) (/*AUTOARG*/ // Outputs app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask, raw_not_ecc, // Inputs rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren, app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted, ram_init_done_r, ram_init_addr ); input rst; input clk; input [APP_DATA_WIDTH-1:0] app_wdf_data; input [APP_MASK_WIDTH-1:0] app_wdf_mask; input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; input app_wdf_wren; input app_wdf_end; reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1; reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1; reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0; reg app_wdf_wren_r1; reg app_wdf_end_r1; reg app_wdf_rdy_r; //Adding few copies of the app_wdf_rdy_r signal in order to meet //timing. This is signal has a very high fanout. So grouped into //few functional groups and alloted one copy per group. (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy1; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy2; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy3; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy4; wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 = ~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data; wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 = ~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask; wire app_wdf_wren_ns1 = ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren); wire app_wdf_end_ns1 = ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end); generate if (ECC_TEST != "OFF") begin : ecc_on always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc; end endgenerate // Be explicit about the latch enable on these registers. always @(posedge clk) begin app_wdf_data_r1 <= #TCQ app_wdf_data_ns1; app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1; app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1; app_wdf_end_r1 <= #TCQ app_wdf_end_ns1; end // The signals wr_data_addr and wr_data_offset come at different // times depending on ECC and the value of CWL. The data portion // always needs to look a the raw wires, the control portion needs // to look at a delayed version when ECC is on and CWL != 8. The // currently supported write data delays do not require this // functionality, but preserve for future use. input wr_data_offset; input [3:0] wr_data_addr; reg wr_data_offset_r; reg [3:0] wr_data_addr_r; generate if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr always @(wr_data_offset) wr_data_offset_r = wr_data_offset; always @(wr_data_addr) wr_data_addr_r = wr_data_addr; end else begin : delay_wr_addr always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset; always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr; end endgenerate // rd_data_cnt is the pointer RAM index for data read from the write data // buffer. Ie, its the data on its way out to the DRAM. input wr_data_en; wire new_rd_data = wr_data_en && ~wr_data_offset_r; reg [3:0] rd_data_indx_r; reg rd_data_upd_indx_r; generate begin : read_data_indx reg [3:0] rd_data_indx_ns; always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin rd_data_indx_ns = rd_data_indx_r; if (rst) rd_data_indx_ns = 5'b0; else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1; end always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns; always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data; end endgenerate // data_buf_addr_cnt generates the pointer for the pointer RAM on behalf // of data buf address that comes with the wr_data_en. // The data buf address is written into the memory // controller along with the command and address. input wr_accepted; reg [3:0] data_buf_addr_cnt_r; generate begin : data_buf_address_counter reg [3:0] data_buf_addr_cnt_ns; always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin data_buf_addr_cnt_ns = data_buf_addr_cnt_r; if (rst) data_buf_addr_cnt_ns = 4'b0; else if (wr_accepted) data_buf_addr_cnt_ns = data_buf_addr_cnt_r + 4'h1; end always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns; end endgenerate // Control writing data into the write data buffer. wire wdf_rdy_ns; always @( posedge clk ) begin app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns; end wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1; wire [3:0] wr_data_pntr; wire [4:0] wb_wr_data_addr; wire [4:0] wb_wr_data_addr_w; reg [3:0] wr_data_indx_r; generate begin : write_data_control wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) || (rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1); // For pointer RAM. Initialize to one since this is one ahead of // what's being registered in wb_wr_data_addr. Assumes pointer RAM // has been initialized such that address equals contents. reg [3:0] wr_data_indx_ns; always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin wr_data_indx_ns = wr_data_indx_r; if (rst) wr_data_indx_ns = 4'b1; else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1; end always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns; // Take pointer from pointer RAM and set into the write data address. // Needs to be split into zeroth bit and everything else because synthesis // tools don't always allow assigning bit vectors seperately. Bit zero of the // address is computed via an entirely different algorithm. reg [4:1] wb_wr_data_addr_ns; reg [4:1] wb_wr_data_addr_r; always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le or wr_data_pntr) begin wb_wr_data_addr_ns = wb_wr_data_addr_r; if (rst) wb_wr_data_addr_ns = 4'b0; else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr; end always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns; // If we see the first getting accepted, then // second half is unconditionally accepted. reg wb_wr_data_addr0_r; wire wb_wr_data_addr0_ns = ~rst && ((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) || (wb_wr_data_addr0_r && ~app_wdf_wren_r1)); always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns; assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r}; assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns}; end endgenerate // Keep track of how many entries in the queue hold data. input ram_init_done_r; output wire app_wdf_rdy; generate begin : occupied_counter //reg [4:0] occ_cnt_ns; //reg [4:0] occ_cnt_r; //always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst // or wr_data_end) begin // occ_cnt_ns = occ_cnt_r; // if (rst) occ_cnt_ns = 5'b0; // else case ({wr_data_end, rd_data_upd_indx_r}) // 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1; // 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1; // endcase // case ({wr_data_end, rd_data_upd_indx_r}) //end //always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; //assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]); //always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; //assign app_wdf_rdy = app_wdf_rdy_r; reg [15:0] occ_cnt; always @(posedge clk) begin if ( rst ) occ_cnt <= #TCQ 16'h0000; else case ({wr_data_end, rd_data_upd_indx_r}) 2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]}; 2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1}; endcase // case ({wr_data_end, rd_data_upd_indx_r}) end assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r)); always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; assign app_wdf_rdy = app_wdf_rdy_r; `ifdef MC_SVA wr_data_buffer_full: cover property (@(posedge clk) (~rst && ~app_wdf_rdy_r)); // wr_data_buffer_inc_dec_15: cover property (@(posedge clk) // (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf))); // wr_data_underflow: assert property (@(posedge clk) // (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f)))); // wr_data_overflow: assert property (@(posedge clk) // (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11)))); `endif end // block: occupied_counter endgenerate // Keep track of how many write requests are in the memory controller. We // must limit this to 16 because we only have that many data_buf_addrs to // hand out. Since the memory controller queue and the write data buffer // queue are distinct, the number of valid entries can be different. // Throttle request acceptance once there are sixteen write requests in // the memory controller. Note that there is still a requirement // for a write reqeusts corresponding write data to be written into the // write data queue with two states of the request. output wire wr_req_16; generate begin : wr_req_counter reg [4:0] wr_req_cnt_ns; reg [4:0] wr_req_cnt_r; always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted or wr_req_cnt_r) begin wr_req_cnt_ns = wr_req_cnt_r; if (rst) wr_req_cnt_ns = 5'b0; else case ({wr_accepted, rd_data_upd_indx_r}) 2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1; 2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1; endcase // case ({wr_accepted, rd_data_upd_indx_r}) end always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns; assign wr_req_16 = (wr_req_cnt_ns == 5'h10); `ifdef MC_SVA wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16)); wr_req_mc_full_inc_dec_15: cover property (@(posedge clk) (~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf))); wr_req_underflow: assert property (@(posedge clk) (rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f)))); wr_req_overflow: assert property (@(posedge clk) (rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11)))); `endif end // block: wr_req_counter endgenerate // Instantiate pointer RAM. Made up of RAM32M in single write, two read // port mode, 2 bit wide mode. input [3:0] ram_init_addr; output wire [3:0] wr_data_buf_addr; localparam PNTR_RAM_CNT = 2; generate begin : pointer_ram wire pointer_we = new_rd_data || ~ram_init_done_r; wire [3:0] pointer_wr_data = ram_init_done_r ? wr_data_addr_r : ram_init_addr; wire [3:0] pointer_wr_addr = ram_init_done_r ? rd_data_indx_r : ram_init_addr; genvar i; for (i=0; i xilinx.com xci unknown 1.0 ddr3_if 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 32 32 32 4 1048576 32 4 1048576 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 8 8 2 OFF 1 OFF 100.0 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 1200.0 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 DIFF FALSE 0 0 30 32 32 4 1048576 256 1 1073741824 8 3 1 1 1 8 OFF 1 1 1 8 1 OFF 14 1 1 1 2 1 29 3 1 1 1 32 OFF 4 2 4 32 1 OFF 15 1 1 1 4 1 8 8 2 OFF 1 OFF 224820144 FALSE 8 3 1 1 1 8 OFF 1 1 1 8 OFF 14 1 1 1 2 1 DDR3 FALSE 10.0 FALSE 10 FALSE 10 FALSE 10 FALSE 10 899 1 0.000 ACTIVE_LOW 29 1 8 18 OFF 1 NONE 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 1 18 OFF 1 1 1 8 1 29 1 29 2 1 18 1 1 NOBUF INTERNAL FALSE 1 Custom ddr3_if Custom Custom mig_a.prj kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 1 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:09:09 2016 // Host : david-xilinx-vm running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top ddr3_if -prefix // ddr3_if_ ddr3_if_sim_netlist.v // Design : ddr3_if // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module ddr3_if (ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, init_calib_complete, device_temp, sys_rst); inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_n; inout [3:0]ddr3_dqs_p; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output ddr3_ras_n; output ddr3_cas_n; output ddr3_we_n; output ddr3_reset_n; output [0:0]ddr3_ck_p; output [0:0]ddr3_ck_n; output [0:0]ddr3_cke; output [0:0]ddr3_cs_n; output [3:0]ddr3_dm; output [0:0]ddr3_odt; input sys_clk_i; output ui_clk; output ui_clk_sync_rst; output mmcm_locked; input aresetn; input app_sr_req; input app_ref_req; input app_zq_req; output app_sr_active; output app_ref_ack; output app_zq_ack; input [0:0]s_axi_awid; input [29:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input s_axi_awvalid; output s_axi_awready; input [255:0]s_axi_wdata; input [31:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; input s_axi_bready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input [0:0]s_axi_arid; input [29:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input s_axi_arvalid; output s_axi_arready; input s_axi_rready; output [0:0]s_axi_rid; output [255:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; output init_calib_complete; output [11:0]device_temp; input sys_rst; wire \ ; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire aresetn; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_ck_n; wire [0:0]ddr3_ck_p; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; (* IBUF_LOW_PWR = 0 *) wire [31:0]ddr3_dq; (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_n; (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; (* DRIVE = "12" *) wire ddr3_reset_n; wire ddr3_we_n; wire [11:0]device_temp; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete; wire \lim_state_reg[6]_i_23_n_0 ; wire mmcm_locked; wire [29:0]s_axi_araddr; wire [1:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [1:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [255:0]s_axi_rdata; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire [1:1]\^s_axi_rresp ; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire \stg2_target_r_reg[1]_i_2_n_0 ; wire stg3_dec2init_val_r_reg_i_11_n_0; wire sys_clk_i; wire sys_rst; wire u_ddr3_if_mig_n_112; wire u_ddr3_if_mig_n_113; wire u_ddr3_if_mig_n_127; wire [49:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address ; wire [11:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank ; wire [2:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n ; wire [3:3]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ; wire [2:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n ; wire [0:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ; wire [1:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ; wire [2:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ; wire [23:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ; wire [59:2]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ; wire [77:2]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ; wire [3:0]\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ; wire ui_clk; wire ui_clk_sync_rst; wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ; wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_rresp[1] = \^s_axi_rresp [1]; assign s_axi_rresp[0] = \ ; GND GND (.G(\ )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]), .DIB({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [1:0]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:2]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [5:4]), .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [13:12]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:14]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22]), .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [1:0]), .DIC({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [2]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [7:6]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [9:8]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [11:10]), .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}), .DIC({init_calib_complete,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [31:30]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [33:32]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:34]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [43:42]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [45:44]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [47:46]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:2]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:4]), .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [1:0]), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [13:12]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [15:14]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [2]}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ), .DIB({1'b1,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2]}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3]}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [65:64]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33]}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:66]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [69:68]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [71:70]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [3:2]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:4]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 (.ADDRA({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRB({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRC({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }), .ADDRD({1'b0,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }), .DIA({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1]}), .DIB({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7]}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [73:72]), .DOB(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:74]), .DOC(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:76]), .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]), .WCLK(ui_clk), .WE(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en )); LUT1 #( .INIT(2'h1)) \lim_state_reg[6]_i_23 (.I0(u_ddr3_if_mig_n_113), .O(\lim_state_reg[6]_i_23_n_0 )); LUT1 #( .INIT(2'h1)) \stg2_target_r_reg[1]_i_2 (.I0(u_ddr3_if_mig_n_127), .O(\stg2_target_r_reg[1]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) stg3_dec2init_val_r_reg_i_11 (.I0(u_ddr3_if_mig_n_112), .O(stg3_dec2init_val_r_reg_i_11_n_0)); ddr3_if_ddr3_if_mig u_ddr3_if_mig (.CLKB0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ), .CLKB0_7(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ), .CLKB0_8(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ), .CLKB0_9(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ), .D(u_ddr3_if_mig_n_127), .Q(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .aresetn(aresetn), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}), .iserdes_clk(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ), .iserdes_clk_2(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ), .iserdes_clk_3(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ), .iserdes_clk_4(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ), .mem_out({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:0]}), .\mmcm_current_reg[0] (stg3_dec2init_val_r_reg_i_11_n_0), .\mmcm_init_trail_reg[0] (\lim_state_reg[6]_i_23_n_0 ), .mmcm_locked(mmcm_locked), .out(device_temp), .phy_dout({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,init_calib_complete,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}), .rd_ptr(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ), .rd_ptr_0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ), .rd_ptr_1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ), .\rd_ptr_reg[3] ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:12],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]}), .\rd_ptr_reg[3]_0 ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:42],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:30],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]}), .\rd_ptr_timing_reg[0] ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2],\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n }), .\rd_ptr_timing_reg[0]_0 ({\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ,\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]}), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst[1]), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst[1]), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .s_axi_rdata(s_axi_rdata), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rresp(\^s_axi_rresp ), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .stg3_dec2init_val_r_reg(u_ddr3_if_mig_n_112), .stg3_inc2init_val_r_reg(u_ddr3_if_mig_n_113), .\stg3_r_reg[0] (\stg2_target_r_reg[1]_i_2_n_0 ), .sys_clk_i(sys_clk_i), .sys_rst(sys_rst), .ui_clk(ui_clk), .ui_clk_sync_rst(ui_clk_sync_rst), .wr_en(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ), .wr_en_5(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ), .wr_en_6(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ), .\wr_ptr_timing_reg[2] (\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ), .\wr_ptr_timing_reg[2]_0 (\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr )); endmodule module ddr3_if_ddr3_if_mig (ui_clk, app_ref_ack, app_zq_ack, app_sr_active, ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, rd_ptr, rd_ptr_0, rd_ptr_1, ui_clk_sync_rst, iserdes_clk, iserdes_clk_2, iserdes_clk_3, iserdes_clk_4, phy_dout, out, mmcm_locked, \rd_ptr_timing_reg[0] , \rd_ptr_timing_reg[0]_0 , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, s_axi_arready, Q, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , D, wr_en, wr_en_5, wr_en_6, ddr_ck_out, s_axi_awready, s_axi_wready, s_axi_rdata, s_axi_rresp, s_axi_rid, s_axi_bid, s_axi_bvalid, s_axi_rvalid, s_axi_rlast, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, app_ref_req, app_zq_req, app_sr_req, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, mem_out, \rd_ptr_reg[3] , \rd_ptr_reg[3]_0 , sys_rst, s_axi_arvalid, sys_clk_i, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , \stg3_r_reg[0] , s_axi_awlen, s_axi_bready, s_axi_awvalid, s_axi_awaddr, s_axi_awburst, s_axi_wvalid, s_axi_awid, s_axi_arlen, s_axi_araddr, s_axi_arburst, s_axi_rready, s_axi_wstrb, s_axi_wdata, aresetn, s_axi_arid); output ui_clk; output app_ref_ack; output app_zq_ack; output app_sr_active; output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output [3:0]rd_ptr; output [3:0]rd_ptr_0; output [3:0]rd_ptr_1; output ui_clk_sync_rst; output iserdes_clk; output iserdes_clk_2; output iserdes_clk_3; output iserdes_clk_4; output [5:0]phy_dout; output [11:0]out; output mmcm_locked; output [37:0]\rd_ptr_timing_reg[0] ; output [4:0]\rd_ptr_timing_reg[0]_0 ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output s_axi_arready; output [3:0]Q; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [0:0]D; output wr_en; output wr_en_5; output wr_en_6; output [1:0]ddr_ck_out; output s_axi_awready; output s_axi_wready; output [255:0]s_axi_rdata; output [0:0]s_axi_rresp; output [0:0]s_axi_rid; output [0:0]s_axi_bid; output s_axi_bvalid; output s_axi_rvalid; output s_axi_rlast; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input app_ref_req; input app_zq_req; input app_sr_req; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input [29:0]\rd_ptr_reg[3]_0 ; input sys_rst; input s_axi_arvalid; input sys_clk_i; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input \stg3_r_reg[0] ; input [7:0]s_axi_awlen; input s_axi_bready; input s_axi_awvalid; input [29:0]s_axi_awaddr; input [0:0]s_axi_awburst; input s_axi_wvalid; input [0:0]s_axi_awid; input [7:0]s_axi_arlen; input [29:0]s_axi_araddr; input [0:0]s_axi_arburst; input s_axi_rready; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; input aresetn; input [0:0]s_axi_arid; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [3:0]Q; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire aresetn; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire freq_refclk; wire [1:1]iodelay_ctrl_rdy; wire iserdes_clk; wire iserdes_clk_2; wire iserdes_clk_3; wire iserdes_clk_4; wire \mem_intfc0/ddr_phy_top0/phy_mc_go ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ; wire [11:0]\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ; wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ; wire \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/rtp_timer_ns1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/rtp_timer_ns1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/rtp_timer_ns1 ; wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r ; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [11:0]out; wire [5:0]phy_dout; wire pll_locked; wire poc_sample_pd; wire psdone; wire psen; wire [3:0]rd_ptr; wire [3:0]rd_ptr_0; wire [3:0]rd_ptr_1; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [37:0]\rd_ptr_timing_reg[0] ; wire [4:0]\rd_ptr_timing_reg[0]_0 ; (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rst_sync_r1; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [255:0]s_axi_rdata; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire [0:0]s_axi_rresp; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_clk_i; wire sys_rst; wire sys_rst_act_hi; wire u_ddr3_clk_ibuf_n_0; wire u_ddr3_infrastructure_n_10; wire u_ddr3_infrastructure_n_11; wire u_ddr3_infrastructure_n_13; wire u_ddr3_infrastructure_n_14; wire u_ddr3_infrastructure_n_15; wire u_ddr3_infrastructure_n_16; wire u_ddr3_infrastructure_n_17; wire u_ddr3_infrastructure_n_18; wire u_ddr3_infrastructure_n_19; wire u_ddr3_infrastructure_n_20; wire u_ddr3_infrastructure_n_21; wire u_ddr3_infrastructure_n_22; wire u_ddr3_infrastructure_n_23; wire u_ddr3_infrastructure_n_24; wire u_ddr3_infrastructure_n_25; wire u_ddr3_infrastructure_n_26; wire u_ddr3_infrastructure_n_27; wire u_ddr3_infrastructure_n_28; wire u_ddr3_infrastructure_n_29; wire u_ddr3_infrastructure_n_30; wire u_ddr3_infrastructure_n_31; wire u_ddr3_infrastructure_n_32; wire u_ddr3_infrastructure_n_33; wire u_ddr3_infrastructure_n_34; wire u_ddr3_infrastructure_n_35; wire u_ddr3_infrastructure_n_36; wire u_ddr3_infrastructure_n_37; wire u_ddr3_infrastructure_n_38; wire u_ddr3_infrastructure_n_40; wire u_ddr3_infrastructure_n_41; wire u_ddr3_infrastructure_n_44; wire u_ddr3_infrastructure_n_47; wire u_ddr3_infrastructure_n_48; wire u_ddr3_infrastructure_n_49; wire u_ddr3_infrastructure_n_50; wire u_ddr3_infrastructure_n_51; wire u_ddr3_infrastructure_n_52; wire u_ddr3_infrastructure_n_53; wire u_ddr3_infrastructure_n_54; wire u_ddr3_infrastructure_n_56; wire u_ddr3_infrastructure_n_58; wire u_ddr3_infrastructure_n_9; wire u_memc_ui_top_axi_n_111; wire u_memc_ui_top_axi_n_114; wire u_memc_ui_top_axi_n_116; wire u_memc_ui_top_axi_n_117; wire u_memc_ui_top_axi_n_119; wire u_memc_ui_top_axi_n_120; wire u_memc_ui_top_axi_n_121; wire u_memc_ui_top_axi_n_64; wire ui_clk; wire ui_clk_sync_rst; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; ddr3_if_mig_7series_v4_0_tempmon \temp_mon_enabled.u_tempmon (.CLK(ui_clk), .D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ), .in0(ui_clk_sync_rst), .mmcm_clk(u_ddr3_clk_ibuf_n_0), .out(out)); ddr3_if_mig_7series_v4_0_clk_ibuf u_ddr3_clk_ibuf (.mmcm_clk(u_ddr3_clk_ibuf_n_0), .sys_clk_i(sys_clk_i)); ddr3_if_mig_7series_v4_0_infrastructure u_ddr3_infrastructure (.AS(sys_rst_act_hi), .CLK(ui_clk), .E(psen), .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ), .SR(u_ddr3_infrastructure_n_14), .SS(u_ddr3_infrastructure_n_16), .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_5(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_6(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_7(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ), .cal2_done_r_reg(u_ddr3_infrastructure_n_18), .cal2_if_reset_reg(u_ddr3_infrastructure_n_17), .cnt_pwron_reset_done_r0(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ), .\complex_address_reg[0] (u_ddr3_infrastructure_n_24), .\complex_num_reads_dec_reg[0] (u_ddr3_infrastructure_n_31), .complex_sample_cnt_inc_reg(u_ddr3_infrastructure_n_25), .\dec_cnt_reg[0] (u_ddr3_infrastructure_n_26), .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (u_ddr3_infrastructure_n_23), .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_ddr3_infrastructure_n_54), .\en_cnt_div4.wrlvl_odt_reg (u_memc_ui_top_axi_n_119), .fine_adjust_reg(u_memc_ui_top_axi_n_64), .\fine_pi_dec_cnt_reg[0] (u_ddr3_infrastructure_n_21), .freq_refclk(freq_refclk), .\gen_final_tap[2].final_val_reg[2][0] (u_ddr3_infrastructure_n_29), .in0(ui_clk_sync_rst), .\last_master_r_reg[2] (u_ddr3_infrastructure_n_34), .\lim_state_reg[0] (u_memc_ui_top_axi_n_116), .mem_refclk(mem_refclk), .mmcm_clk(u_ddr3_clk_ibuf_n_0), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .mpr_rank_done_r_reg({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}), .\oneeighty_r_reg[0] (u_ddr3_infrastructure_n_38), .\oneeighty_r_reg[0]_0 (u_ddr3_infrastructure_n_41), .p_81_in(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ), .pass_open_bank_r(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ), .pass_open_bank_r_2(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ), .pass_open_bank_r_3(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r ), .pass_open_bank_r_4(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r ), .phy_mc_go(\mem_intfc0/ddr_phy_top0/phy_mc_go ), .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ), .\pi_rst_stg1_cal_r_reg[1] (u_ddr3_infrastructure_n_51), .pll_locked(pll_locked), .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ), .poc_backup_r_reg(u_memc_ui_top_axi_n_117), .poc_sample_pd(poc_sample_pd), .pre_wait_r_reg(u_ddr3_infrastructure_n_44), .psdone(psdone), .ras_timer_zero_r_reg(u_ddr3_infrastructure_n_47), .ras_timer_zero_r_reg_0(u_ddr3_infrastructure_n_48), .ras_timer_zero_r_reg_1(u_ddr3_infrastructure_n_49), .ras_timer_zero_r_reg_2(u_ddr3_infrastructure_n_50), .\rd_ptr_timing_reg[2] (u_ddr3_infrastructure_n_15), .\read_fifo.head_r_reg[0] (u_ddr3_infrastructure_n_13), .reset_reg(u_ddr3_infrastructure_n_10), .\resume_wait_r_reg[10] (u_memc_ui_top_axi_n_111), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (u_ddr3_infrastructure_n_35), .\row_cnt_victim_rotate.complex_row_cnt_reg[7] (u_memc_ui_top_axi_n_121), .rst_out_reg(u_ddr3_infrastructure_n_22), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (u_memc_ui_top_axi_n_114), .rst_sync_r1(rst_sync_r1), .rtp_timer_ns1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/rtp_timer_ns1 ), .rtp_timer_ns1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/rtp_timer_ns1 ), .rtp_timer_ns1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/rtp_timer_ns1 ), .\rtp_timer_r_reg[0] (u_ddr3_infrastructure_n_33), .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ), .\samp_edge_cnt0_r_reg[11] (u_ddr3_infrastructure_n_52), .\simp_stg3_final_r_reg[17] (u_ddr3_infrastructure_n_11), .sm_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ), .\stg3_r_reg[1] (u_ddr3_infrastructure_n_40), .\stg3_tap_cnt_reg[0] (u_ddr3_infrastructure_n_9), .sync_pulse(sync_pulse), .\two_dec_max_limit_reg[11] (u_ddr3_infrastructure_n_20), .\victim_sel_rotate.sel_reg[31] (u_ddr3_infrastructure_n_32), .\wait_cnt_r_reg[3] (u_ddr3_infrastructure_n_53), .\wait_cnt_reg[3] (u_ddr3_infrastructure_n_36), .\wait_cnt_reg[3]_0 (u_ddr3_infrastructure_n_58), .\wl_tap_count_r_reg[0] (u_ddr3_infrastructure_n_30), .wr_victim_inc_reg(u_memc_ui_top_axi_n_120), .\wr_victim_sel_ocal_reg[2] (u_ddr3_infrastructure_n_56), .\wrcal_dqs_cnt_r_reg[2] (u_ddr3_infrastructure_n_19), .\wrcal_reads_reg[0] (u_ddr3_infrastructure_n_37)); ddr3_if_mig_7series_v4_0_iodelay_ctrl u_iodelay_ctrl (.AS(sys_rst_act_hi), .mmcm_clk(u_ddr3_clk_ibuf_n_0), .rst_sync_r1_reg(iodelay_ctrl_rdy), .sys_rst(sys_rst)); (* X_CORE_INFO = "mig_7series_v4_0_ddr3_7Series, ddr3_if, 2016.2" *) ddr3_if_mig_7series_v4_0_memc_ui_top_axi u_memc_ui_top_axi (.CLK(ui_clk), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .D(D), .E(psen), .Q(Q), .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ), .SR(u_ddr3_infrastructure_n_14), .SS(u_ddr3_infrastructure_n_16), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .aresetn(aresetn), .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_2(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_4(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ), .bm_end_r1_reg(u_ddr3_infrastructure_n_49), .bm_end_r1_reg_0(u_ddr3_infrastructure_n_48), .bm_end_r1_reg_1(u_ddr3_infrastructure_n_47), .bm_end_r1_reg_2(u_ddr3_infrastructure_n_50), .cnt_pwron_reset_done_r0(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ), .\complex_row_cnt_ocal_reg[0] (u_memc_ui_top_axi_n_120), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .\device_temp_r_reg[11] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (iserdes_clk), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (iserdes_clk_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (iserdes_clk_3), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (iserdes_clk_4), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (u_memc_ui_top_axi_n_119), .fine_adjust_reg(u_ddr3_infrastructure_n_51), .freq_refclk(freq_refclk), .in0(ui_clk_sync_rst), .mem_out(mem_out), .mem_refclk(mem_refclk), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .out({s_axi_rresp,s_axi_rdata}), .p_81_in(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ), .pass_open_bank_r(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ), .pass_open_bank_r_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ), .pass_open_bank_r_3(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r ), .pass_open_bank_r_5(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r ), .pass_open_bank_r_lcl_reg(u_ddr3_infrastructure_n_44), .phy_dout(phy_dout), .phy_mc_go(\mem_intfc0/ddr_phy_top0/phy_mc_go ), .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ), .pi_cnt_dec_reg(u_ddr3_infrastructure_n_53), .\pi_rst_stg1_cal_r_reg[0] (u_memc_ui_top_axi_n_64), .pll_locked(pll_locked), .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ), .po_cnt_dec_reg(u_ddr3_infrastructure_n_58), .poc_sample_pd(poc_sample_pd), .psdone(psdone), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[0] (\rd_ptr_timing_reg[0] ), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0]_0 ), .\rd_ptr_timing_reg[2] (rd_ptr[3]), .\rd_ptr_timing_reg[2]_0 (rd_ptr[2]), .\rd_ptr_timing_reg[2]_1 (rd_ptr[1]), .\rd_ptr_timing_reg[2]_10 (rd_ptr_1[3]), .\rd_ptr_timing_reg[2]_2 (rd_ptr[0]), .\rd_ptr_timing_reg[2]_3 (rd_ptr_0[3]), .\rd_ptr_timing_reg[2]_4 (rd_ptr_0[2]), .\rd_ptr_timing_reg[2]_5 (rd_ptr_0[1]), .\rd_ptr_timing_reg[2]_6 (rd_ptr_0[0]), .\rd_ptr_timing_reg[2]_7 (rd_ptr_1[0]), .\rd_ptr_timing_reg[2]_8 (rd_ptr_1[1]), .\rd_ptr_timing_reg[2]_9 (rd_ptr_1[2]), .\resume_wait_r_reg[5] (u_memc_ui_top_axi_n_111), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (u_memc_ui_top_axi_n_121), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (iodelay_ctrl_rdy), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(u_memc_ui_top_axi_n_114), .rstdiv0_sync_r1_reg_rep__0(u_ddr3_infrastructure_n_13), .rstdiv0_sync_r1_reg_rep__10(u_ddr3_infrastructure_n_23), .rstdiv0_sync_r1_reg_rep__11(u_ddr3_infrastructure_n_24), .rstdiv0_sync_r1_reg_rep__12(u_ddr3_infrastructure_n_25), .rstdiv0_sync_r1_reg_rep__13(u_ddr3_infrastructure_n_26), .rstdiv0_sync_r1_reg_rep__14({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}), .rstdiv0_sync_r1_reg_rep__16(u_ddr3_infrastructure_n_29), .rstdiv0_sync_r1_reg_rep__17(u_ddr3_infrastructure_n_30), .rstdiv0_sync_r1_reg_rep__18(u_ddr3_infrastructure_n_31), .rstdiv0_sync_r1_reg_rep__19(u_ddr3_infrastructure_n_32), .rstdiv0_sync_r1_reg_rep__2(u_ddr3_infrastructure_n_15), .rstdiv0_sync_r1_reg_rep__20(u_ddr3_infrastructure_n_33), .rstdiv0_sync_r1_reg_rep__21(u_ddr3_infrastructure_n_34), .rstdiv0_sync_r1_reg_rep__22(u_ddr3_infrastructure_n_35), .rstdiv0_sync_r1_reg_rep__23(u_ddr3_infrastructure_n_36), .rstdiv0_sync_r1_reg_rep__24(u_ddr3_infrastructure_n_37), .rstdiv0_sync_r1_reg_rep__24_0(u_ddr3_infrastructure_n_54), .rstdiv0_sync_r1_reg_rep__24_1(u_ddr3_infrastructure_n_56), .rstdiv0_sync_r1_reg_rep__25(u_ddr3_infrastructure_n_38), .rstdiv0_sync_r1_reg_rep__26(u_ddr3_infrastructure_n_10), .rstdiv0_sync_r1_reg_rep__26_0(u_ddr3_infrastructure_n_11), .rstdiv0_sync_r1_reg_rep__26_1(u_ddr3_infrastructure_n_9), .rstdiv0_sync_r1_reg_rep__26_2(u_ddr3_infrastructure_n_40), .rstdiv0_sync_r1_reg_rep__4(u_ddr3_infrastructure_n_17), .rstdiv0_sync_r1_reg_rep__5(u_ddr3_infrastructure_n_18), .rstdiv0_sync_r1_reg_rep__6(u_ddr3_infrastructure_n_19), .rstdiv0_sync_r1_reg_rep__7(u_ddr3_infrastructure_n_20), .rstdiv0_sync_r1_reg_rep__8(u_ddr3_infrastructure_n_21), .rstdiv0_sync_r1_reg_rep__9(u_ddr3_infrastructure_n_22), .rtp_timer_ns1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/rtp_timer_ns1 ), .rtp_timer_ns1_6(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/rtp_timer_ns1 ), .rtp_timer_ns1_7(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/rtp_timer_ns1 ), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ), .samp_edge_cnt0_en_r_reg(u_ddr3_infrastructure_n_52), .sm_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ), .\sm_r_reg[0] (u_memc_ui_top_axi_n_117), .\sm_r_reg[0]_0 (u_ddr3_infrastructure_n_41), .\stg2_tap_cnt_reg[0] (u_memc_ui_top_axi_n_116), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 )); endmodule module ddr3_if_mig_7series_v4_0_arb_mux (\last_master_r_reg[2] , \cmd_pipe_plus.mc_cmd_reg[0] , \cmd_pipe_plus.mc_ras_n_reg[0] , \cmd_pipe_plus.mc_bank_reg[7] , DIC, col_rd_wr, col_data_buf_addr, cke_r, rnk_config_valid_r_lcl_reg, \cmd_pipe_plus.mc_data_offset_1_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \rtw_timer.rtw_cnt_r_reg[1] , Q, \periodic_rd_generation.periodic_rd_timer_r_reg[2] , read_this_rank, \grant_r_reg[3] , E, \rnk_config_strobe_r_reg[0] , override_demand_ns, rnk_config_valid_r_lcl_reg_0, mc_we_n_ns, \last_master_r_reg[3] , mc_cas_n_ns, mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[1] , \cmd_pipe_plus.mc_address_reg[44] , mc_cs_n_ns, \grant_r_reg[2] , \grant_r_reg[3]_0 , \grant_r_reg[3]_1 , \last_master_r_reg[2]_0 , \last_master_r_reg[0] , \last_master_r_reg[3]_0 , \cmd_pipe_plus.mc_bank_reg[7]_0 , \grant_r_reg[1] , \grant_r_reg[3]_2 , \grant_r_reg[1]_0 , \grant_r_reg[1]_1 , \grant_r_reg[2]_0 , \last_master_r_reg[3]_1 , act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , \wtr_timer.wtr_cnt_r_reg[0] , \wtr_timer.wtr_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1]_0 , demand_priority_r_reg, \cmd_pipe_plus.mc_we_n_reg[1] , granted_row_ns, CLK, granted_col_ns, \generate_maint_cmds.insert_maint_r_lcl_reg , granted_pre_ns, rstdiv0_sync_r1_reg_rep__0, mc_cke_ns, SR, rnk_config_valid_r_lcl_reg_1, rd_wr_r_lcl_reg, read_this_rank_r, rd_this_rank_r, rd_wr_r_lcl_reg_0, rd_wr_r_lcl_reg_1, rd_wr_r_lcl_reg_2, rd_wr_r_lcl_reg_3, rd_wr_r_lcl_reg_4, rstdiv0_sync_r1_reg_rep__21, rd_wr_r_lcl_reg_5, \rtw_timer.rtw_cnt_r_reg[1]_0 , rd_wr_r_lcl_reg_6, rd_wr_r_lcl_reg_7, demand_priority_r_reg_0, req_bank_rdy_ns, req_bank_rdy_ns_0, demand_priority_r_reg_1, demand_priority_r_reg_2, req_bank_rdy_ns_1, demand_priority_r_reg_3, req_bank_rdy_ns_2, req_periodic_rd_r, row_cmd_wr, maint_zq_r, act_wait_r_lcl_reg, granted_row_r_reg, maint_srx_r, \req_bank_r_lcl_reg[2] , granted_row_r_reg_0, \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , \req_bank_r_lcl_reg[2]_2 , \req_row_r_lcl_reg[14] , req_row_r, act_wait_r_lcl_reg_0, act_wait_r_lcl_reg_1, act_wait_r_lcl_reg_2, ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, ras_timer_zero_r_reg_1, \last_master_r_reg[3]_2 , ras_timer_zero_r_reg_2, ras_timer_zero_r_reg_3, inhbt_act_faw_r, \last_master_r_reg[3]_3 , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, ras_timer_zero_r_reg_4, ras_timer_zero_r_reg_5, ras_timer_zero_r_reg_6, auto_pre_r_lcl_reg_1, ras_timer_zero_r_reg_7, auto_pre_r_lcl_reg_2, rstdiv0_sync_r1_reg_rep__22, ofs_rdy_r, ofs_rdy_r_3, ofs_rdy_r_4, ofs_rdy_r_5, req_data_buf_addr_r, \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , act_this_rank_r, wr_this_rank_r, \req_col_r_reg[9] , \req_col_r_reg[9]_0 , \req_col_r_reg[9]_1 , \req_col_r_reg[9]_2 , auto_pre_r_lcl_reg_3, auto_pre_r_lcl_reg_4, auto_pre_r_lcl_reg_5, auto_pre_r_lcl_reg_6, \req_bank_r_lcl_reg[2]_3 , \grant_r_reg[0] , \grant_r_reg[0]_0 , \grant_r_reg[0]_1 , \grant_r_reg[0]_2 , \grant_r_reg[0]_3 , \grant_r_reg[0]_4 , \grant_r_reg[0]_5 , \grant_r_reg[0]_6 , \grant_r_reg[0]_7 , \grant_r_reg[0]_8 , \grant_r_reg[0]_9 , \grant_r_reg[0]_10 , \grant_r_reg[0]_11 , \grant_r_reg[0]_12 , \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[1] , req_bank_rdy_r); output \last_master_r_reg[2] ; output \cmd_pipe_plus.mc_cmd_reg[0] ; output \cmd_pipe_plus.mc_ras_n_reg[0] ; output \cmd_pipe_plus.mc_bank_reg[7] ; output [0:0]DIC; output col_rd_wr; output [4:0]col_data_buf_addr; output cke_r; output rnk_config_valid_r_lcl_reg; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; output \rtw_timer.rtw_cnt_r_reg[1] ; output [3:0]Q; output \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; output read_this_rank; output \grant_r_reg[3] ; output [0:0]E; output \rnk_config_strobe_r_reg[0] ; output override_demand_ns; output rnk_config_valid_r_lcl_reg_0; output [1:0]mc_we_n_ns; output [3:0]\last_master_r_reg[3] ; output [1:0]mc_cas_n_ns; output [1:0]mc_ras_n_ns; output [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; output \cmd_pipe_plus.mc_bank_reg[1] ; output [36:0]\cmd_pipe_plus.mc_address_reg[44] ; output [0:0]mc_cs_n_ns; output \grant_r_reg[2] ; output \grant_r_reg[3]_0 ; output \grant_r_reg[3]_1 ; output \last_master_r_reg[2]_0 ; output \last_master_r_reg[0] ; output [0:0]\last_master_r_reg[3]_0 ; output [3:0]\cmd_pipe_plus.mc_bank_reg[7]_0 ; output \grant_r_reg[1] ; output \grant_r_reg[3]_2 ; output \grant_r_reg[1]_0 ; output \grant_r_reg[1]_1 ; output \grant_r_reg[2]_0 ; output [0:0]\last_master_r_reg[3]_1 ; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output \wtr_timer.wtr_cnt_r_reg[0] ; output \wtr_timer.wtr_cnt_r_reg[1] ; output \wtr_timer.wtr_cnt_r_reg[1]_0 ; output demand_priority_r_reg; output \cmd_pipe_plus.mc_we_n_reg[1] ; input granted_row_ns; input CLK; input granted_col_ns; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input granted_pre_ns; input rstdiv0_sync_r1_reg_rep__0; input [0:0]mc_cke_ns; input [0:0]SR; input rnk_config_valid_r_lcl_reg_1; input rd_wr_r_lcl_reg; input read_this_rank_r; input [3:0]rd_this_rank_r; input rd_wr_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input rd_wr_r_lcl_reg_2; input rd_wr_r_lcl_reg_3; input rd_wr_r_lcl_reg_4; input rstdiv0_sync_r1_reg_rep__21; input rd_wr_r_lcl_reg_5; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input rd_wr_r_lcl_reg_6; input rd_wr_r_lcl_reg_7; input demand_priority_r_reg_0; input req_bank_rdy_ns; input req_bank_rdy_ns_0; input demand_priority_r_reg_1; input demand_priority_r_reg_2; input req_bank_rdy_ns_1; input demand_priority_r_reg_3; input req_bank_rdy_ns_2; input [3:0]req_periodic_rd_r; input [0:0]row_cmd_wr; input maint_zq_r; input act_wait_r_lcl_reg; input granted_row_r_reg; input maint_srx_r; input [2:0]\req_bank_r_lcl_reg[2] ; input granted_row_r_reg_0; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input [2:0]\req_bank_r_lcl_reg[2]_2 ; input [27:0]\req_row_r_lcl_reg[14] ; input [29:0]req_row_r; input act_wait_r_lcl_reg_0; input act_wait_r_lcl_reg_1; input act_wait_r_lcl_reg_2; input ras_timer_zero_r_reg; input ras_timer_zero_r_reg_0; input ras_timer_zero_r_reg_1; input \last_master_r_reg[3]_2 ; input ras_timer_zero_r_reg_2; input ras_timer_zero_r_reg_3; input inhbt_act_faw_r; input \last_master_r_reg[3]_3 ; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input ras_timer_zero_r_reg_4; input ras_timer_zero_r_reg_5; input ras_timer_zero_r_reg_6; input auto_pre_r_lcl_reg_1; input ras_timer_zero_r_reg_7; input auto_pre_r_lcl_reg_2; input rstdiv0_sync_r1_reg_rep__22; input ofs_rdy_r; input ofs_rdy_r_3; input ofs_rdy_r_4; input ofs_rdy_r_5; input [19:0]req_data_buf_addr_r; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [3:0]act_this_rank_r; input [3:0]wr_this_rank_r; input [6:0]\req_col_r_reg[9] ; input [6:0]\req_col_r_reg[9]_0 ; input [6:0]\req_col_r_reg[9]_1 ; input [6:0]\req_col_r_reg[9]_2 ; input auto_pre_r_lcl_reg_3; input auto_pre_r_lcl_reg_4; input auto_pre_r_lcl_reg_5; input auto_pre_r_lcl_reg_6; input \req_bank_r_lcl_reg[2]_3 ; input \grant_r_reg[0] ; input \grant_r_reg[0]_0 ; input \grant_r_reg[0]_1 ; input \grant_r_reg[0]_2 ; input \grant_r_reg[0]_3 ; input \grant_r_reg[0]_4 ; input \grant_r_reg[0]_5 ; input \grant_r_reg[0]_6 ; input \grant_r_reg[0]_7 ; input \grant_r_reg[0]_8 ; input \grant_r_reg[0]_9 ; input \grant_r_reg[0]_10 ; input \grant_r_reg[0]_11 ; input \grant_r_reg[0]_12 ; input \req_bank_r_lcl_reg[0] ; input \req_bank_r_lcl_reg[1] ; input req_bank_rdy_r; wire CLK; wire [0:0]DIC; wire [0:0]E; wire [3:0]Q; wire [0:0]SR; wire act_this_rank; wire [3:0]act_this_rank_r; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire act_wait_r_lcl_reg_2; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire auto_pre_r_lcl_reg_3; wire auto_pre_r_lcl_reg_4; wire auto_pre_r_lcl_reg_5; wire auto_pre_r_lcl_reg_6; wire cke_r; wire [36:0]\cmd_pipe_plus.mc_address_reg[44] ; wire \cmd_pipe_plus.mc_bank_reg[1] ; wire \cmd_pipe_plus.mc_bank_reg[7] ; wire [3:0]\cmd_pipe_plus.mc_bank_reg[7]_0 ; wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_cmd_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_ras_n_reg[0] ; wire \cmd_pipe_plus.mc_we_n_reg[1] ; wire [4:0]col_data_buf_addr; wire [4:4]col_data_buf_addr_r; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire demand_priority_r_reg_1; wire demand_priority_r_reg_2; wire demand_priority_r_reg_3; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[0]_1 ; wire \grant_r_reg[0]_10 ; wire \grant_r_reg[0]_11 ; wire \grant_r_reg[0]_12 ; wire \grant_r_reg[0]_2 ; wire \grant_r_reg[0]_3 ; wire \grant_r_reg[0]_4 ; wire \grant_r_reg[0]_5 ; wire \grant_r_reg[0]_6 ; wire \grant_r_reg[0]_7 ; wire \grant_r_reg[0]_8 ; wire \grant_r_reg[0]_9 ; wire \grant_r_reg[1] ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[1]_1 ; wire \grant_r_reg[2] ; wire \grant_r_reg[2]_0 ; wire \grant_r_reg[3] ; wire \grant_r_reg[3]_0 ; wire \grant_r_reg[3]_1 ; wire \grant_r_reg[3]_2 ; wire granted_col_ns; wire granted_pre_ns; wire granted_row_ns; wire granted_row_r_reg; wire granted_row_r_reg_0; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire \last_master_r_reg[0] ; wire \last_master_r_reg[2] ; wire \last_master_r_reg[2]_0 ; wire [3:0]\last_master_r_reg[3] ; wire [0:0]\last_master_r_reg[3]_0 ; wire [0:0]\last_master_r_reg[3]_1 ; wire \last_master_r_reg[3]_2 ; wire \last_master_r_reg[3]_3 ; wire maint_srx_r; wire maint_zq_r; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cke_ns; wire [0:0]mc_cs_n_ns; wire [1:0]mc_ras_n_ns; wire [1:0]mc_we_n_ns; wire ofs_rdy_r; wire ofs_rdy_r_3; wire ofs_rdy_r_4; wire ofs_rdy_r_5; wire override_demand_ns; wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire ras_timer_zero_r_reg_1; wire ras_timer_zero_r_reg_2; wire ras_timer_zero_r_reg_3; wire ras_timer_zero_r_reg_4; wire ras_timer_zero_r_reg_5; wire ras_timer_zero_r_reg_6; wire ras_timer_zero_r_reg_7; wire [3:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire rd_wr_r_lcl_reg_3; wire rd_wr_r_lcl_reg_4; wire rd_wr_r_lcl_reg_5; wire rd_wr_r_lcl_reg_6; wire rd_wr_r_lcl_reg_7; wire read_this_rank; wire read_this_rank_r; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[1] ; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [2:0]\req_bank_r_lcl_reg[2]_2 ; wire \req_bank_r_lcl_reg[2]_3 ; wire req_bank_rdy_ns; wire req_bank_rdy_ns_0; wire req_bank_rdy_ns_1; wire req_bank_rdy_ns_2; wire req_bank_rdy_r; wire [6:0]\req_col_r_reg[9] ; wire [6:0]\req_col_r_reg[9]_0 ; wire [6:0]\req_col_r_reg[9]_1 ; wire [6:0]\req_col_r_reg[9]_2 ; wire [19:0]req_data_buf_addr_r; wire [3:0]req_periodic_rd_r; wire [29:0]req_row_r; wire [27:0]\req_row_r_lcl_reg[14] ; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire rnk_config_valid_r_lcl_reg_0; wire rnk_config_valid_r_lcl_reg_1; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [3:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[0] ; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire \wtr_timer.wtr_cnt_r_reg[1]_0 ; ddr3_if_mig_7series_v4_0_arb_row_col arb_row_col0 (.CLK(CLK), .D({\last_master_r_reg[2]_0 ,\last_master_r_reg[0] }), .DIC(DIC), .E(E), .Q(Q), .SR(SR), .act_this_rank(act_this_rank), .act_this_rank_r(act_this_rank_r), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0), .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1), .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2), .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_3), .auto_pre_r_lcl_reg_4(auto_pre_r_lcl_reg_4), .auto_pre_r_lcl_reg_5(auto_pre_r_lcl_reg_5), .auto_pre_r_lcl_reg_6(auto_pre_r_lcl_reg_6), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] ), .\cmd_pipe_plus.mc_bank_reg[1] (\cmd_pipe_plus.mc_bank_reg[1] ), .\cmd_pipe_plus.mc_bank_reg[7] (\cmd_pipe_plus.mc_bank_reg[7] ), .\cmd_pipe_plus.mc_bank_reg[7]_0 (\cmd_pipe_plus.mc_bank_reg[7]_0 ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_cmd_reg[0] (\cmd_pipe_plus.mc_cmd_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_ras_n_reg[0] (\cmd_pipe_plus.mc_ras_n_reg[0] ), .\cmd_pipe_plus.mc_we_n_reg[1] (\cmd_pipe_plus.mc_we_n_reg[1] ), .col_data_buf_addr(col_data_buf_addr), .col_data_buf_addr_r(col_data_buf_addr_r), .col_periodic_rd_r(col_periodic_rd_r), .col_rd_wr(col_rd_wr), .col_rd_wr_r(col_rd_wr_r), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ), .demand_priority_r_reg(demand_priority_r_reg), .demand_priority_r_reg_0(demand_priority_r_reg_0), .demand_priority_r_reg_1(demand_priority_r_reg_1), .demand_priority_r_reg_2(demand_priority_r_reg_2), .demand_priority_r_reg_3(demand_priority_r_reg_3), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ), .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ), .\grant_r_reg[0]_10 (\grant_r_reg[0]_10 ), .\grant_r_reg[0]_11 (\grant_r_reg[0]_11 ), .\grant_r_reg[0]_12 (\grant_r_reg[0]_12 ), .\grant_r_reg[0]_2 (\grant_r_reg[0]_2 ), .\grant_r_reg[0]_3 (\grant_r_reg[0]_3 ), .\grant_r_reg[0]_4 (\grant_r_reg[0]_4 ), .\grant_r_reg[0]_5 (\grant_r_reg[0]_5 ), .\grant_r_reg[0]_6 (\grant_r_reg[0]_6 ), .\grant_r_reg[0]_7 (\grant_r_reg[0]_7 ), .\grant_r_reg[0]_8 (\grant_r_reg[0]_8 ), .\grant_r_reg[0]_9 (\grant_r_reg[0]_9 ), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ), .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ), .\grant_r_reg[2] (\grant_r_reg[2] ), .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ), .\grant_r_reg[3] (\grant_r_reg[3] ), .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 ), .\grant_r_reg[3]_1 (\grant_r_reg[3]_1 ), .\grant_r_reg[3]_2 (\grant_r_reg[3]_2 ), .granted_col_ns(granted_col_ns), .granted_pre_ns(granted_pre_ns), .granted_row_ns(granted_row_ns), .granted_row_r_reg_0(granted_row_r_reg), .granted_row_r_reg_1(granted_row_r_reg_0), .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .\last_master_r_reg[2] (\last_master_r_reg[2] ), .\last_master_r_reg[3] (\last_master_r_reg[3] ), .\last_master_r_reg[3]_0 (\last_master_r_reg[3]_0 ), .\last_master_r_reg[3]_1 (\last_master_r_reg[3]_1 ), .\last_master_r_reg[3]_2 (\last_master_r_reg[3]_2 ), .\last_master_r_reg[3]_3 (\last_master_r_reg[3]_3 ), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .mc_cas_n_ns(mc_cas_n_ns), .mc_cs_n_ns(mc_cs_n_ns), .mc_ras_n_ns(mc_ras_n_ns), .mc_we_n_ns(mc_we_n_ns), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r_3(ofs_rdy_r_3), .ofs_rdy_r_4(ofs_rdy_r_4), .ofs_rdy_r_5(ofs_rdy_r_5), .override_demand_ns(override_demand_ns), .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ), .ras_timer_zero_r_reg(ras_timer_zero_r_reg), .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0), .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1), .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2), .ras_timer_zero_r_reg_3(ras_timer_zero_r_reg_3), .ras_timer_zero_r_reg_4(ras_timer_zero_r_reg_4), .ras_timer_zero_r_reg_5(ras_timer_zero_r_reg_5), .ras_timer_zero_r_reg_6(ras_timer_zero_r_reg_6), .ras_timer_zero_r_reg_7(ras_timer_zero_r_reg_7), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1), .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_2), .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_3), .rd_wr_r_lcl_reg_4(rd_wr_r_lcl_reg_4), .rd_wr_r_lcl_reg_5(rd_wr_r_lcl_reg_5), .rd_wr_r_lcl_reg_6(rd_wr_r_lcl_reg_6), .rd_wr_r_lcl_reg_7(rd_wr_r_lcl_reg_7), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .\req_bank_r_lcl_reg[1] (\req_bank_r_lcl_reg[1] ), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ), .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ), .\req_bank_r_lcl_reg[2]_3 (\req_bank_r_lcl_reg[2]_3 ), .req_bank_rdy_ns(req_bank_rdy_ns), .req_bank_rdy_ns_0(req_bank_rdy_ns_0), .req_bank_rdy_ns_1(req_bank_rdy_ns_1), .req_bank_rdy_ns_2(req_bank_rdy_ns_2), .req_bank_rdy_r(req_bank_rdy_r), .\req_col_r_reg[9] (\req_col_r_reg[9] ), .\req_col_r_reg[9]_0 (\req_col_r_reg[9]_0 ), .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_1 ), .\req_col_r_reg[9]_2 (\req_col_r_reg[9]_2 ), .req_data_buf_addr_r(req_data_buf_addr_r), .req_periodic_rd_r(req_periodic_rd_r), .req_row_r(req_row_r), .\req_row_r_lcl_reg[14] (\req_row_r_lcl_reg[14] ), .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0] ), .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg), .rnk_config_valid_r_lcl_reg_1(rnk_config_valid_r_lcl_reg_0), .rnk_config_valid_r_lcl_reg_2(rnk_config_valid_r_lcl_reg_1), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[0] (\wtr_timer.wtr_cnt_r_reg[0] ), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ), .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1]_0 )); ddr3_if_mig_7series_v4_0_arb_select arb_select0 (.CLK(CLK), .DIC(DIC), .cke_r(cke_r), .col_data_buf_addr(col_data_buf_addr[4]), .col_data_buf_addr_r(col_data_buf_addr_r), .col_periodic_rd_r(col_periodic_rd_r), .col_rd_wr(col_rd_wr), .col_rd_wr_r(col_rd_wr_r), .mc_cke_ns(mc_cke_ns), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0)); endmodule module ddr3_if_mig_7series_v4_0_arb_row_col (\last_master_r_reg[2] , \cmd_pipe_plus.mc_cmd_reg[0] , \cmd_pipe_plus.mc_ras_n_reg[0] , \cmd_pipe_plus.mc_bank_reg[7] , rnk_config_valid_r_lcl_reg_0, \cmd_pipe_plus.mc_data_offset_1_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \rtw_timer.rtw_cnt_r_reg[1] , Q, \periodic_rd_generation.periodic_rd_timer_r_reg[2] , read_this_rank, \grant_r_reg[3] , E, col_rd_wr, \rnk_config_strobe_r_reg[0]_0 , override_demand_ns, rnk_config_valid_r_lcl_reg_1, DIC, mc_we_n_ns, \last_master_r_reg[3] , mc_cas_n_ns, mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[1] , \cmd_pipe_plus.mc_address_reg[44] , mc_cs_n_ns, \grant_r_reg[2] , \grant_r_reg[3]_0 , \grant_r_reg[3]_1 , D, \last_master_r_reg[3]_0 , \cmd_pipe_plus.mc_bank_reg[7]_0 , \grant_r_reg[1] , \grant_r_reg[3]_2 , \grant_r_reg[1]_0 , \grant_r_reg[1]_1 , \grant_r_reg[2]_0 , col_data_buf_addr, \last_master_r_reg[3]_1 , act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , \wtr_timer.wtr_cnt_r_reg[0] , \wtr_timer.wtr_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1]_0 , demand_priority_r_reg, \cmd_pipe_plus.mc_we_n_reg[1] , granted_row_ns, CLK, granted_col_ns, \generate_maint_cmds.insert_maint_r_lcl_reg , granted_pre_ns, SR, rnk_config_valid_r_lcl_reg_2, rd_wr_r_lcl_reg, read_this_rank_r, rd_this_rank_r, rd_wr_r_lcl_reg_0, rd_wr_r_lcl_reg_1, rd_wr_r_lcl_reg_2, rd_wr_r_lcl_reg_3, rd_wr_r_lcl_reg_4, rstdiv0_sync_r1_reg_rep__21, rd_wr_r_lcl_reg_5, \rtw_timer.rtw_cnt_r_reg[1]_0 , rd_wr_r_lcl_reg_6, rd_wr_r_lcl_reg_7, demand_priority_r_reg_0, req_bank_rdy_ns, req_bank_rdy_ns_0, demand_priority_r_reg_1, demand_priority_r_reg_2, req_bank_rdy_ns_1, demand_priority_r_reg_3, req_bank_rdy_ns_2, req_periodic_rd_r, col_periodic_rd_r, col_rd_wr_r, row_cmd_wr, maint_zq_r, act_wait_r_lcl_reg, granted_row_r_reg_0, maint_srx_r, \req_bank_r_lcl_reg[2] , granted_row_r_reg_1, \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , \req_bank_r_lcl_reg[2]_2 , \req_row_r_lcl_reg[14] , req_row_r, act_wait_r_lcl_reg_0, act_wait_r_lcl_reg_1, act_wait_r_lcl_reg_2, ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, ras_timer_zero_r_reg_1, \last_master_r_reg[3]_2 , ras_timer_zero_r_reg_2, ras_timer_zero_r_reg_3, inhbt_act_faw_r, \last_master_r_reg[3]_3 , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, ras_timer_zero_r_reg_4, ras_timer_zero_r_reg_5, ras_timer_zero_r_reg_6, auto_pre_r_lcl_reg_1, ras_timer_zero_r_reg_7, auto_pre_r_lcl_reg_2, rstdiv0_sync_r1_reg_rep__22, ofs_rdy_r, ofs_rdy_r_3, ofs_rdy_r_4, ofs_rdy_r_5, req_data_buf_addr_r, col_data_buf_addr_r, \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , act_this_rank_r, wr_this_rank_r, \req_col_r_reg[9] , \req_col_r_reg[9]_0 , \req_col_r_reg[9]_1 , \req_col_r_reg[9]_2 , auto_pre_r_lcl_reg_3, auto_pre_r_lcl_reg_4, auto_pre_r_lcl_reg_5, auto_pre_r_lcl_reg_6, \req_bank_r_lcl_reg[2]_3 , \grant_r_reg[0] , \grant_r_reg[0]_0 , \grant_r_reg[0]_1 , \grant_r_reg[0]_2 , \grant_r_reg[0]_3 , \grant_r_reg[0]_4 , \grant_r_reg[0]_5 , \grant_r_reg[0]_6 , \grant_r_reg[0]_7 , \grant_r_reg[0]_8 , \grant_r_reg[0]_9 , \grant_r_reg[0]_10 , \grant_r_reg[0]_11 , \grant_r_reg[0]_12 , \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[1] , req_bank_rdy_r); output \last_master_r_reg[2] ; output \cmd_pipe_plus.mc_cmd_reg[0] ; output \cmd_pipe_plus.mc_ras_n_reg[0] ; output \cmd_pipe_plus.mc_bank_reg[7] ; output rnk_config_valid_r_lcl_reg_0; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; output \rtw_timer.rtw_cnt_r_reg[1] ; output [3:0]Q; output \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; output read_this_rank; output \grant_r_reg[3] ; output [0:0]E; output col_rd_wr; output \rnk_config_strobe_r_reg[0]_0 ; output override_demand_ns; output rnk_config_valid_r_lcl_reg_1; output [0:0]DIC; output [1:0]mc_we_n_ns; output [3:0]\last_master_r_reg[3] ; output [1:0]mc_cas_n_ns; output [1:0]mc_ras_n_ns; output [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; output \cmd_pipe_plus.mc_bank_reg[1] ; output [36:0]\cmd_pipe_plus.mc_address_reg[44] ; output [0:0]mc_cs_n_ns; output \grant_r_reg[2] ; output \grant_r_reg[3]_0 ; output \grant_r_reg[3]_1 ; output [1:0]D; output [0:0]\last_master_r_reg[3]_0 ; output [3:0]\cmd_pipe_plus.mc_bank_reg[7]_0 ; output \grant_r_reg[1] ; output \grant_r_reg[3]_2 ; output \grant_r_reg[1]_0 ; output \grant_r_reg[1]_1 ; output \grant_r_reg[2]_0 ; output [4:0]col_data_buf_addr; output [0:0]\last_master_r_reg[3]_1 ; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output \wtr_timer.wtr_cnt_r_reg[0] ; output \wtr_timer.wtr_cnt_r_reg[1] ; output \wtr_timer.wtr_cnt_r_reg[1]_0 ; output demand_priority_r_reg; output \cmd_pipe_plus.mc_we_n_reg[1] ; input granted_row_ns; input CLK; input granted_col_ns; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input granted_pre_ns; input [0:0]SR; input rnk_config_valid_r_lcl_reg_2; input rd_wr_r_lcl_reg; input read_this_rank_r; input [3:0]rd_this_rank_r; input rd_wr_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input rd_wr_r_lcl_reg_2; input rd_wr_r_lcl_reg_3; input rd_wr_r_lcl_reg_4; input rstdiv0_sync_r1_reg_rep__21; input rd_wr_r_lcl_reg_5; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input rd_wr_r_lcl_reg_6; input rd_wr_r_lcl_reg_7; input demand_priority_r_reg_0; input req_bank_rdy_ns; input req_bank_rdy_ns_0; input demand_priority_r_reg_1; input demand_priority_r_reg_2; input req_bank_rdy_ns_1; input demand_priority_r_reg_3; input req_bank_rdy_ns_2; input [3:0]req_periodic_rd_r; input col_periodic_rd_r; input col_rd_wr_r; input [0:0]row_cmd_wr; input maint_zq_r; input act_wait_r_lcl_reg; input granted_row_r_reg_0; input maint_srx_r; input [2:0]\req_bank_r_lcl_reg[2] ; input granted_row_r_reg_1; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input [2:0]\req_bank_r_lcl_reg[2]_2 ; input [27:0]\req_row_r_lcl_reg[14] ; input [29:0]req_row_r; input act_wait_r_lcl_reg_0; input act_wait_r_lcl_reg_1; input act_wait_r_lcl_reg_2; input ras_timer_zero_r_reg; input ras_timer_zero_r_reg_0; input ras_timer_zero_r_reg_1; input \last_master_r_reg[3]_2 ; input ras_timer_zero_r_reg_2; input ras_timer_zero_r_reg_3; input inhbt_act_faw_r; input \last_master_r_reg[3]_3 ; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input ras_timer_zero_r_reg_4; input ras_timer_zero_r_reg_5; input ras_timer_zero_r_reg_6; input auto_pre_r_lcl_reg_1; input ras_timer_zero_r_reg_7; input auto_pre_r_lcl_reg_2; input rstdiv0_sync_r1_reg_rep__22; input ofs_rdy_r; input ofs_rdy_r_3; input ofs_rdy_r_4; input ofs_rdy_r_5; input [19:0]req_data_buf_addr_r; input [0:0]col_data_buf_addr_r; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [3:0]act_this_rank_r; input [3:0]wr_this_rank_r; input [6:0]\req_col_r_reg[9] ; input [6:0]\req_col_r_reg[9]_0 ; input [6:0]\req_col_r_reg[9]_1 ; input [6:0]\req_col_r_reg[9]_2 ; input auto_pre_r_lcl_reg_3; input auto_pre_r_lcl_reg_4; input auto_pre_r_lcl_reg_5; input auto_pre_r_lcl_reg_6; input \req_bank_r_lcl_reg[2]_3 ; input \grant_r_reg[0] ; input \grant_r_reg[0]_0 ; input \grant_r_reg[0]_1 ; input \grant_r_reg[0]_2 ; input \grant_r_reg[0]_3 ; input \grant_r_reg[0]_4 ; input \grant_r_reg[0]_5 ; input \grant_r_reg[0]_6 ; input \grant_r_reg[0]_7 ; input \grant_r_reg[0]_8 ; input \grant_r_reg[0]_9 ; input \grant_r_reg[0]_10 ; input \grant_r_reg[0]_11 ; input \grant_r_reg[0]_12 ; input \req_bank_r_lcl_reg[0] ; input \req_bank_r_lcl_reg[1] ; input req_bank_rdy_r; wire CLK; wire [1:0]D; wire [0:0]DIC; wire [0:0]E; wire [3:0]Q; wire [0:0]SR; wire act_this_rank; wire [3:0]act_this_rank_r; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire act_wait_r_lcl_reg_2; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire auto_pre_r_lcl_reg_3; wire auto_pre_r_lcl_reg_4; wire auto_pre_r_lcl_reg_5; wire auto_pre_r_lcl_reg_6; wire [36:0]\cmd_pipe_plus.mc_address_reg[44] ; wire \cmd_pipe_plus.mc_bank_reg[1] ; wire \cmd_pipe_plus.mc_bank_reg[7] ; wire [3:0]\cmd_pipe_plus.mc_bank_reg[7]_0 ; wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_cmd_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_ras_n_reg[0] ; wire \cmd_pipe_plus.mc_we_n_reg[1] ; wire [4:0]col_data_buf_addr; wire [0:0]col_data_buf_addr_r; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire demand_priority_r_reg_1; wire demand_priority_r_reg_2; wire demand_priority_r_reg_3; wire \genblk3[1].rnk_config_strobe_r_reg ; wire \genblk3[2].rnk_config_strobe_r_reg ; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[0]_1 ; wire \grant_r_reg[0]_10 ; wire \grant_r_reg[0]_11 ; wire \grant_r_reg[0]_12 ; wire \grant_r_reg[0]_2 ; wire \grant_r_reg[0]_3 ; wire \grant_r_reg[0]_4 ; wire \grant_r_reg[0]_5 ; wire \grant_r_reg[0]_6 ; wire \grant_r_reg[0]_7 ; wire \grant_r_reg[0]_8 ; wire \grant_r_reg[0]_9 ; wire \grant_r_reg[1] ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[1]_1 ; wire \grant_r_reg[2] ; wire \grant_r_reg[2]_0 ; wire \grant_r_reg[3] ; wire \grant_r_reg[3]_0 ; wire \grant_r_reg[3]_1 ; wire \grant_r_reg[3]_2 ; wire granted_col_ns; wire granted_pre_ns; wire granted_row_ns; wire granted_row_r_reg_0; wire granted_row_r_reg_1; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire \last_master_r_reg[2] ; wire [3:0]\last_master_r_reg[3] ; wire [0:0]\last_master_r_reg[3]_0 ; wire [0:0]\last_master_r_reg[3]_1 ; wire \last_master_r_reg[3]_2 ; wire \last_master_r_reg[3]_3 ; wire maint_srx_r; wire maint_zq_r; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cs_n_ns; wire [1:0]mc_ras_n_ns; wire [1:0]mc_we_n_ns; wire ofs_rdy_r; wire ofs_rdy_r_3; wire ofs_rdy_r_4; wire ofs_rdy_r_5; wire override_demand_ns; wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire ras_timer_zero_r_reg_1; wire ras_timer_zero_r_reg_2; wire ras_timer_zero_r_reg_3; wire ras_timer_zero_r_reg_4; wire ras_timer_zero_r_reg_5; wire ras_timer_zero_r_reg_6; wire ras_timer_zero_r_reg_7; wire [3:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire rd_wr_r_lcl_reg_3; wire rd_wr_r_lcl_reg_4; wire rd_wr_r_lcl_reg_5; wire rd_wr_r_lcl_reg_6; wire rd_wr_r_lcl_reg_7; wire read_this_rank; wire read_this_rank_r; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[1] ; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [2:0]\req_bank_r_lcl_reg[2]_2 ; wire \req_bank_r_lcl_reg[2]_3 ; wire req_bank_rdy_ns; wire req_bank_rdy_ns_0; wire req_bank_rdy_ns_1; wire req_bank_rdy_ns_2; wire req_bank_rdy_r; wire [6:0]\req_col_r_reg[9] ; wire [6:0]\req_col_r_reg[9]_0 ; wire [6:0]\req_col_r_reg[9]_1 ; wire [6:0]\req_col_r_reg[9]_2 ; wire [19:0]req_data_buf_addr_r; wire [3:0]req_periodic_rd_r; wire [29:0]req_row_r; wire [27:0]\req_row_r_lcl_reg[14] ; wire rnk_config_strobe; wire rnk_config_strobe_ns; wire \rnk_config_strobe_r[0]_i_3_n_0 ; wire \rnk_config_strobe_r_reg[0]_0 ; wire rnk_config_valid_r_lcl_reg_0; wire rnk_config_valid_r_lcl_reg_1; wire rnk_config_valid_r_lcl_reg_2; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [3:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[0] ; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire \wtr_timer.wtr_cnt_r_reg[1]_0 ; LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_cas_n[1]_i_1 (.I0(\cmd_pipe_plus.mc_cmd_reg[0] ), .O(mc_cas_n_ns[1])); LUT2 #( .INIT(4'h1)) \cmd_pipe_plus.mc_cs_n[0]_i_1 (.I0(\cmd_pipe_plus.mc_ras_n_reg[0] ), .I1(\last_master_r_reg[2] ), .O(mc_cs_n_ns)); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_ras_n[2]_i_1 (.I0(\cmd_pipe_plus.mc_bank_reg[7] ), .O(mc_ras_n_ns[1])); ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized4 col_arb0 (.CLK(CLK), .DIC(DIC), .E(E), .Q(Q), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_3), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_4), .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_5), .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_6), .\cmd_pipe_plus.mc_address_reg[25] (\cmd_pipe_plus.mc_address_reg[44] [22:15]), .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[8] [5:3]), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_we_n_reg[1] (\cmd_pipe_plus.mc_we_n_reg[1] ), .col_data_buf_addr(col_data_buf_addr), .col_data_buf_addr_r(col_data_buf_addr_r), .col_periodic_rd_r(col_periodic_rd_r), .col_rd_wr(col_rd_wr), .col_rd_wr_r(col_rd_wr_r), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ), .demand_priority_r_reg(demand_priority_r_reg), .\genblk3[1].rnk_config_strobe_r_reg (\genblk3[1].rnk_config_strobe_r_reg ), .\genblk3[2].rnk_config_strobe_r_reg (\genblk3[2].rnk_config_strobe_r_reg ), .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ), .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ), .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ), .\grant_r_reg[3]_0 (\grant_r_reg[3] ), .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 ), .granted_col_r_reg(\cmd_pipe_plus.mc_cmd_reg[0] ), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r_3(ofs_rdy_r_3), .ofs_rdy_r_4(ofs_rdy_r_4), .ofs_rdy_r_5(ofs_rdy_r_5), .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1), .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_2), .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_3), .rd_wr_r_lcl_reg_4(rd_wr_r_lcl_reg_4), .rd_wr_r_lcl_reg_5(rd_wr_r_lcl_reg_5), .rd_wr_r_lcl_reg_6(rd_wr_r_lcl_reg_6), .rd_wr_r_lcl_reg_7(rd_wr_r_lcl_reg_7), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_2 ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_1 ), .req_bank_rdy_r(req_bank_rdy_r), .\req_col_r_reg[9] (\req_col_r_reg[9] ), .\req_col_r_reg[9]_0 (\req_col_r_reg[9]_0 ), .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_1 ), .\req_col_r_reg[9]_2 (\req_col_r_reg[9]_2 ), .req_data_buf_addr_r(req_data_buf_addr_r), .req_periodic_rd_r(req_periodic_rd_r), .rnk_config_strobe(rnk_config_strobe), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg_0), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[0] (\wtr_timer.wtr_cnt_r_reg[0] ), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ), .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1]_0 )); FDRE \genblk3[1].rnk_config_strobe_r_reg[1] (.C(CLK), .CE(1'b1), .D(rnk_config_strobe), .Q(\genblk3[1].rnk_config_strobe_r_reg ), .R(1'b0)); FDRE \genblk3[2].rnk_config_strobe_r_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk3[1].rnk_config_strobe_r_reg ), .Q(\genblk3[2].rnk_config_strobe_r_reg ), .R(1'b0)); FDRE #( .INIT(1'b0)) granted_col_r_reg (.C(CLK), .CE(1'b1), .D(granted_col_ns), .Q(\cmd_pipe_plus.mc_cmd_reg[0] ), .R(1'b0)); FDRE granted_row_r_reg (.C(CLK), .CE(1'b1), .D(granted_row_ns), .Q(\last_master_r_reg[2] ), .R(1'b0)); LUT6 #( .INIT(64'hFFF0FFF7FFF7FFF7)) i___34_i_1 (.I0(demand_priority_r_reg_2), .I1(req_bank_rdy_ns_1), .I2(rnk_config_valid_r_lcl_reg_0), .I3(override_demand_ns), .I4(demand_priority_r_reg_3), .I5(req_bank_rdy_ns_2), .O(\rnk_config_strobe_r_reg[0]_0 )); LUT6 #( .INIT(64'h000000F800000088)) i___34_i_2 (.I0(demand_priority_r_reg_1), .I1(req_bank_rdy_ns_0), .I2(req_bank_rdy_ns), .I3(rnk_config_valid_r_lcl_reg_0), .I4(override_demand_ns), .I5(demand_priority_r_reg_0), .O(rnk_config_valid_r_lcl_reg_1)); FDRE insert_maint_r1_lcl_reg (.C(CLK), .CE(1'b1), .D(\generate_maint_cmds.insert_maint_r_lcl_reg ), .Q(\cmd_pipe_plus.mc_ras_n_reg[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1049" *) LUT3 #( .INIT(8'hFE)) override_demand_r_i_1 (.I0(\genblk3[1].rnk_config_strobe_r_reg ), .I1(\genblk3[2].rnk_config_strobe_r_reg ), .I2(rnk_config_strobe), .O(override_demand_ns)); FDRE #( .INIT(1'b0)) \pre_4_1_1T_arb.granted_pre_r_reg (.C(CLK), .CE(1'b1), .D(granted_pre_ns), .Q(\cmd_pipe_plus.mc_bank_reg[7] ), .R(1'b0)); ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized1 \pre_4_1_1T_arb.pre_arb0 (.CLK(CLK), .D(D), .Q(\cmd_pipe_plus.mc_bank_reg[7]_0 ), .act_wait_r_lcl_reg(act_wait_r_lcl_reg_2), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_1), .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] [36:23]), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] [8:6]), .\grant_r_reg[0]_0 (\grant_r_reg[0] ), .\grant_r_reg[0]_1 (\grant_r_reg[0]_0 ), .\grant_r_reg[0]_10 (\grant_r_reg[0]_9 ), .\grant_r_reg[0]_11 (\grant_r_reg[0]_10 ), .\grant_r_reg[0]_12 (\grant_r_reg[0]_11 ), .\grant_r_reg[0]_13 (\grant_r_reg[0]_12 ), .\grant_r_reg[0]_2 (\grant_r_reg[0]_1 ), .\grant_r_reg[0]_3 (\grant_r_reg[0]_2 ), .\grant_r_reg[0]_4 (\grant_r_reg[0]_3 ), .\grant_r_reg[0]_5 (\grant_r_reg[0]_4 ), .\grant_r_reg[0]_6 (\grant_r_reg[0]_5 ), .\grant_r_reg[0]_7 (\grant_r_reg[0]_6 ), .\grant_r_reg[0]_8 (\grant_r_reg[0]_7 ), .\grant_r_reg[0]_9 (\grant_r_reg[0]_8 ), .\last_master_r_reg[3]_0 (\last_master_r_reg[3]_0 ), .\last_master_r_reg[3]_1 (\last_master_r_reg[3]_3 ), .mc_we_n_ns(mc_we_n_ns[1]), .\pre_4_1_1T_arb.granted_pre_r_reg (\cmd_pipe_plus.mc_bank_reg[7] ), .ras_timer_zero_r_reg(ras_timer_zero_r_reg_4), .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_5), .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_6), .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_7), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .\req_bank_r_lcl_reg[1] (\req_bank_r_lcl_reg[1] ), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_3 ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_2 ), .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ), .req_row_r({req_row_r[29:12],req_row_r[10:1]}), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22)); LUT6 #( .INIT(64'h33202020FFFFFFFF)) \rnk_config_strobe_r[0]_i_1 (.I0(demand_priority_r_reg_0), .I1(\rnk_config_strobe_r[0]_i_3_n_0 ), .I2(req_bank_rdy_ns), .I3(req_bank_rdy_ns_0), .I4(demand_priority_r_reg_1), .I5(\rnk_config_strobe_r_reg[0]_0 ), .O(rnk_config_strobe_ns)); (* SOFT_HLUTNM = "soft_lutpair1049" *) LUT4 #( .INIT(16'hFFFE)) \rnk_config_strobe_r[0]_i_3 (.I0(rnk_config_strobe), .I1(\genblk3[2].rnk_config_strobe_r_reg ), .I2(\genblk3[1].rnk_config_strobe_r_reg ), .I3(rnk_config_valid_r_lcl_reg_0), .O(\rnk_config_strobe_r[0]_i_3_n_0 )); FDRE \rnk_config_strobe_r_reg[0] (.C(CLK), .CE(1'b1), .D(rnk_config_strobe_ns), .Q(rnk_config_strobe), .R(1'b0)); FDRE rnk_config_valid_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rnk_config_valid_r_lcl_reg_2), .Q(rnk_config_valid_r_lcl_reg_0), .R(SR)); ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized2 row_arb0 (.CLK(CLK), .Q(\last_master_r_reg[3] ), .act_this_rank(act_this_rank), .act_this_rank_r(act_this_rank_r), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0), .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1), .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2), .\cmd_pipe_plus.mc_address_reg[14] (\cmd_pipe_plus.mc_address_reg[44] [14:0]), .\cmd_pipe_plus.mc_bank_reg[1] (\cmd_pipe_plus.mc_bank_reg[1] ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[8] [2:0]), .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ), .\grant_r_reg[1]_0 (\grant_r_reg[1] ), .\grant_r_reg[2]_0 (\grant_r_reg[2] ), .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 ), .\grant_r_reg[3]_1 (\grant_r_reg[3]_1 ), .granted_row_r_reg(granted_row_r_reg_0), .granted_row_r_reg_0(\last_master_r_reg[2] ), .granted_row_r_reg_1(granted_row_r_reg_1), .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .insert_maint_r1_lcl_reg(\cmd_pipe_plus.mc_ras_n_reg[0] ), .\last_master_r_reg[3]_0 (\last_master_r_reg[3]_1 ), .\last_master_r_reg[3]_1 (\last_master_r_reg[3]_2 ), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .mc_cas_n_ns(mc_cas_n_ns[0]), .mc_ras_n_ns(mc_ras_n_ns[0]), .mc_we_n_ns(mc_we_n_ns[0]), .ras_timer_zero_r_reg(ras_timer_zero_r_reg), .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0), .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1), .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2), .ras_timer_zero_r_reg_3(ras_timer_zero_r_reg_3), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ), .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ), .req_row_r(req_row_r), .\req_row_r_lcl_reg[14] (\req_row_r_lcl_reg[14] ), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22)); endmodule module ddr3_if_mig_7series_v4_0_arb_select (col_periodic_rd_r, col_rd_wr_r, col_data_buf_addr_r, cke_r, DIC, CLK, col_rd_wr, col_data_buf_addr, rstdiv0_sync_r1_reg_rep__0, mc_cke_ns); output col_periodic_rd_r; output col_rd_wr_r; output [0:0]col_data_buf_addr_r; output cke_r; input [0:0]DIC; input CLK; input col_rd_wr; input [0:0]col_data_buf_addr; input rstdiv0_sync_r1_reg_rep__0; input [0:0]mc_cke_ns; wire CLK; wire [0:0]DIC; wire cke_r; wire [0:0]col_data_buf_addr; wire [0:0]col_data_buf_addr_r; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r; wire [0:0]mc_cke_ns; wire rstdiv0_sync_r1_reg_rep__0; FDSE cke_r_reg (.C(CLK), .CE(1'b1), .D(mc_cke_ns), .Q(cke_r), .S(rstdiv0_sync_r1_reg_rep__0)); FDRE \col_mux.col_data_buf_addr_r_reg[4] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr), .Q(col_data_buf_addr_r), .R(1'b0)); FDRE \col_mux.col_periodic_rd_r_reg (.C(CLK), .CE(1'b1), .D(DIC), .Q(col_periodic_rd_r), .R(1'b0)); FDRE #( .INIT(1'b0)) \col_mux.col_rd_wr_r_reg (.C(CLK), .CE(1'b1), .D(col_rd_wr), .Q(col_rd_wr_r), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc (s_axi_arready, app_en_ns1, mc_app_cmd, E, s_axi_awready, s_axi_wready, mc_app_wdf_mask_reg, D, mc_app_wdf_data_reg, \mc_app_wdf_data_reg_reg[255] , out, s_axi_rid, s_axi_bid, s_axi_bvalid, w_cmd_rdy, \app_addr_r1_reg[27] , s_axi_rvalid, s_axi_rlast, app_wdf_mask, app_wdf_data, mc_app_wdf_wren_reg, s_axi_arvalid, app_rdy, reset_reg, app_en_r1, CLK, app_wdf_rdy, app_rd_data_valid, Q, mc_init_complete, s_axi_awlen, s_axi_bready, s_axi_awvalid, s_axi_awaddr, s_axi_awburst, s_axi_wvalid, s_axi_awid, s_axi_arlen, s_axi_araddr, s_axi_arburst, s_axi_rready, s_axi_wstrb, s_axi_wdata, aresetn, s_axi_arid); output s_axi_arready; output app_en_ns1; output [0:0]mc_app_cmd; output [0:0]E; output s_axi_awready; output s_axi_wready; output [31:0]mc_app_wdf_mask_reg; output [31:0]D; output [255:0]mc_app_wdf_data_reg; output [255:0]\mc_app_wdf_data_reg_reg[255] ; output [256:0]out; output [0:0]s_axi_rid; output [0:0]s_axi_bid; output s_axi_bvalid; output w_cmd_rdy; output [24:0]\app_addr_r1_reg[27] ; output s_axi_rvalid; output s_axi_rlast; output [31:0]app_wdf_mask; output [255:0]app_wdf_data; output mc_app_wdf_wren_reg; input s_axi_arvalid; input app_rdy; input reset_reg; input app_en_r1; input CLK; input app_wdf_rdy; input app_rd_data_valid; input [255:0]Q; input mc_init_complete; input [7:0]s_axi_awlen; input s_axi_bready; input s_axi_awvalid; input [29:0]s_axi_awaddr; input [0:0]s_axi_awburst; input s_axi_wvalid; input [0:0]s_axi_awid; input [7:0]s_axi_arlen; input [29:0]s_axi_araddr; input [0:0]s_axi_arburst; input s_axi_rready; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; input aresetn; input [0:0]s_axi_arid; wire CLK; wire [31:0]D; wire [0:0]E; wire [255:0]Q; wire [24:0]\app_addr_r1_reg[27] ; wire app_en_ns1; wire app_en_r1; wire app_rd_data_valid; wire app_rdy; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire areset_d1; wire aresetn; wire awvalid_int; wire axi_mc_ar_channel_0_n_29; wire axi_mc_aw_channel_0_n_10; wire axi_mc_aw_channel_0_n_11; wire axi_mc_aw_channel_0_n_12; wire axi_mc_aw_channel_0_n_13; wire axi_mc_aw_channel_0_n_14; wire axi_mc_aw_channel_0_n_15; wire axi_mc_aw_channel_0_n_16; wire axi_mc_aw_channel_0_n_17; wire axi_mc_aw_channel_0_n_18; wire axi_mc_aw_channel_0_n_19; wire axi_mc_aw_channel_0_n_20; wire axi_mc_aw_channel_0_n_21; wire axi_mc_aw_channel_0_n_22; wire axi_mc_aw_channel_0_n_23; wire axi_mc_aw_channel_0_n_24; wire axi_mc_aw_channel_0_n_25; wire axi_mc_aw_channel_0_n_26; wire axi_mc_aw_channel_0_n_27; wire axi_mc_aw_channel_0_n_28; wire axi_mc_aw_channel_0_n_4; wire axi_mc_aw_channel_0_n_5; wire axi_mc_aw_channel_0_n_7; wire axi_mc_aw_channel_0_n_8; wire axi_mc_aw_channel_0_n_9; wire axi_mc_cmd_arbiter_0_n_3; wire axi_mc_cmd_arbiter_0_n_4; wire axi_mc_cmd_arbiter_0_n_5; wire axi_mc_cmd_arbiter_0_n_6; wire axvalid; wire b_awid; wire b_push; wire [0:0]mc_app_cmd; wire [255:0]mc_app_wdf_data_reg; wire [255:0]\mc_app_wdf_data_reg_reg[255] ; wire [31:0]mc_app_wdf_mask_reg; wire mc_app_wdf_wren_reg; wire mc_init_complete; wire mc_init_complete_r; wire next; wire [256:0]out; wire p_0_in; wire r_arid; wire r_push; wire r_rlast; wire rd_cmd_en; wire rd_starve_cnt0; wire reset_reg; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire w_cmd_rdy; wire wr_cmd_en; wire wvalid_int; LUT2 #( .INIT(4'h7)) areset_d1_i_1 (.I0(mc_init_complete_r), .I1(aresetn), .O(p_0_in)); (* equivalent_register_removal = "no" *) FDRE areset_d1_reg (.C(CLK), .CE(1'b1), .D(p_0_in), .Q(areset_d1), .R(1'b0)); ddr3_if_mig_7series_v4_0_axi_mc_ar_channel axi_mc_ar_channel_0 (.CLK(CLK), .\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd), .\app_addr_r1_reg[27] ({\app_addr_r1_reg[27] [24:4],\app_addr_r1_reg[27] [2:0]}), .\app_addr_r1_reg[6] (axi_mc_ar_channel_0_n_29), .areset_d1(areset_d1), .\axaddr_incr_reg[10] (axi_mc_aw_channel_0_n_8), .\axaddr_incr_reg[11] (axi_mc_aw_channel_0_n_9), .\axaddr_incr_reg[12] (axi_mc_aw_channel_0_n_10), .\axaddr_incr_reg[13] (axi_mc_aw_channel_0_n_11), .\axaddr_incr_reg[14] (axi_mc_aw_channel_0_n_12), .\axaddr_incr_reg[15] (axi_mc_aw_channel_0_n_13), .\axaddr_incr_reg[16] (axi_mc_aw_channel_0_n_14), .\axaddr_incr_reg[17] (axi_mc_aw_channel_0_n_15), .\axaddr_incr_reg[18] (axi_mc_aw_channel_0_n_16), .\axaddr_incr_reg[19] (axi_mc_aw_channel_0_n_17), .\axaddr_incr_reg[20] (axi_mc_aw_channel_0_n_18), .\axaddr_incr_reg[21] (axi_mc_aw_channel_0_n_19), .\axaddr_incr_reg[22] (axi_mc_aw_channel_0_n_20), .\axaddr_incr_reg[23] (axi_mc_aw_channel_0_n_21), .\axaddr_incr_reg[24] (axi_mc_aw_channel_0_n_22), .\axaddr_incr_reg[25] (axi_mc_aw_channel_0_n_23), .\axaddr_incr_reg[26] (axi_mc_aw_channel_0_n_24), .\axaddr_incr_reg[27] (axi_mc_aw_channel_0_n_25), .\axaddr_incr_reg[28] (axi_mc_aw_channel_0_n_26), .\axaddr_incr_reg[29] (axi_mc_aw_channel_0_n_27), .\axaddr_incr_reg[5] (axi_mc_aw_channel_0_n_28), .\axaddr_incr_reg[6] (axi_mc_aw_channel_0_n_4), .\axaddr_incr_reg[7] (axi_mc_aw_channel_0_n_5), .\axaddr_incr_reg[9] (axi_mc_aw_channel_0_n_7), .axready_reg(axi_mc_cmd_arbiter_0_n_5), .axready_reg_0(axi_mc_cmd_arbiter_0_n_6), .axvalid(axvalid), .in({r_arid,r_rlast}), .next(next), .r_push(r_push), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid)); ddr3_if_mig_7series_v4_0_axi_mc_aw_channel axi_mc_aw_channel_0 (.CLK(CLK), .\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy), .\RD_PRI_REG_STARVE.rnw_i_reg_0 (mc_app_cmd), .\app_addr_r1_reg[10] (axi_mc_aw_channel_0_n_10), .\app_addr_r1_reg[11] (axi_mc_aw_channel_0_n_11), .\app_addr_r1_reg[12] (axi_mc_aw_channel_0_n_12), .\app_addr_r1_reg[13] (axi_mc_aw_channel_0_n_13), .\app_addr_r1_reg[14] (axi_mc_aw_channel_0_n_14), .\app_addr_r1_reg[15] (axi_mc_aw_channel_0_n_15), .\app_addr_r1_reg[16] (axi_mc_aw_channel_0_n_16), .\app_addr_r1_reg[17] (axi_mc_aw_channel_0_n_17), .\app_addr_r1_reg[18] (axi_mc_aw_channel_0_n_18), .\app_addr_r1_reg[19] (axi_mc_aw_channel_0_n_19), .\app_addr_r1_reg[20] (axi_mc_aw_channel_0_n_20), .\app_addr_r1_reg[21] (axi_mc_aw_channel_0_n_21), .\app_addr_r1_reg[22] (axi_mc_aw_channel_0_n_22), .\app_addr_r1_reg[23] (axi_mc_aw_channel_0_n_23), .\app_addr_r1_reg[24] (axi_mc_aw_channel_0_n_24), .\app_addr_r1_reg[25] (axi_mc_aw_channel_0_n_25), .\app_addr_r1_reg[26] (axi_mc_aw_channel_0_n_26), .\app_addr_r1_reg[27] (axi_mc_aw_channel_0_n_27), .\app_addr_r1_reg[3] (axi_mc_aw_channel_0_n_28), .\app_addr_r1_reg[4] (axi_mc_aw_channel_0_n_4), .\app_addr_r1_reg[5] (axi_mc_aw_channel_0_n_5), .\app_addr_r1_reg[6] (\app_addr_r1_reg[27] [3]), .\app_addr_r1_reg[7] (axi_mc_aw_channel_0_n_7), .\app_addr_r1_reg[8] (axi_mc_aw_channel_0_n_8), .\app_addr_r1_reg[9] (axi_mc_aw_channel_0_n_9), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .axready_reg(axi_mc_cmd_arbiter_0_n_3), .axready_reg_0(axi_mc_cmd_arbiter_0_n_4), .b_awid(b_awid), .b_push(b_push), .\int_addr_reg[3] (axi_mc_ar_channel_0_n_29), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid)); ddr3_if_mig_7series_v4_0_axi_mc_b_channel axi_mc_b_channel_0 (.CLK(CLK), .E(E), .\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd), .app_en_ns1(app_en_ns1), .app_en_r1(app_en_r1), .app_rdy(app_rdy), .app_wdf_rdy(app_wdf_rdy), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .b_awid(b_awid), .b_push(b_push), .rd_cmd_en(rd_cmd_en), .reset_reg(reset_reg), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .wr_cmd_en(wr_cmd_en), .wvalid_int(wvalid_int)); ddr3_if_mig_7series_v4_0_axi_mc_cmd_arbiter axi_mc_cmd_arbiter_0 (.CLK(CLK), .E(rd_starve_cnt0), .\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 (mc_app_cmd), .app_rdy(app_rdy), .areset_d1(areset_d1), .\axaddr_incr_reg[29] (axi_mc_cmd_arbiter_0_n_3), .\axaddr_incr_reg[29]_0 (axi_mc_cmd_arbiter_0_n_5), .\axlen_cnt_reg[1] (axi_mc_cmd_arbiter_0_n_4), .\axlen_cnt_reg[1]_0 (axi_mc_cmd_arbiter_0_n_6), .axready_reg(s_axi_arready), .mc_app_wdf_wren_reg_reg(w_cmd_rdy), .next(next), .rd_cmd_en(rd_cmd_en), .s_axi_arburst(s_axi_arburst), .s_axi_arvalid(s_axi_arvalid), .s_axi_awburst(s_axi_awburst), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .wr_cmd_en(wr_cmd_en)); ddr3_if_mig_7series_v4_0_axi_mc_r_channel axi_mc_r_channel_0 (.CLK(CLK), .E(rd_starve_cnt0), .Q(Q), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .areset_d1(areset_d1), .axvalid(axvalid), .in({r_arid,r_rlast}), .out(out), .r_push(r_push), .rd_cmd_en(rd_cmd_en), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid)); ddr3_if_mig_7series_v4_0_axi_mc_w_channel axi_mc_w_channel_0 (.CLK(CLK), .D(D), .\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .app_wdf_rdy(app_wdf_rdy), .areset_d1(areset_d1), .mc_app_wdf_data_reg(mc_app_wdf_data_reg), .\mc_app_wdf_data_reg_reg[255]_0 (\mc_app_wdf_data_reg_reg[255] ), .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg), .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .wvalid_int(wvalid_int)); FDRE mc_init_complete_r_reg (.C(CLK), .CE(1'b1), .D(mc_init_complete), .Q(mc_init_complete_r), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_ar_channel (s_axi_arready, r_push, in, axvalid, \app_addr_r1_reg[27] , \app_addr_r1_reg[6] , areset_d1, CLK, next, \axaddr_incr_reg[6] , \axaddr_incr_reg[7] , \axaddr_incr_reg[9] , \axaddr_incr_reg[10] , \axaddr_incr_reg[11] , \axaddr_incr_reg[12] , \axaddr_incr_reg[13] , \axaddr_incr_reg[14] , \axaddr_incr_reg[15] , \axaddr_incr_reg[16] , \axaddr_incr_reg[17] , \axaddr_incr_reg[18] , \axaddr_incr_reg[19] , \axaddr_incr_reg[20] , \axaddr_incr_reg[21] , \axaddr_incr_reg[22] , \axaddr_incr_reg[23] , \axaddr_incr_reg[24] , \axaddr_incr_reg[25] , \axaddr_incr_reg[26] , \axaddr_incr_reg[27] , \axaddr_incr_reg[28] , \axaddr_incr_reg[29] , \axaddr_incr_reg[5] , axready_reg, s_axi_arlen, s_axi_arvalid, s_axi_araddr, \RD_PRI_REG_STARVE.rnw_i_reg , axready_reg_0, s_axi_arburst, s_axi_arid); output s_axi_arready; output r_push; output [1:0]in; output axvalid; output [23:0]\app_addr_r1_reg[27] ; output \app_addr_r1_reg[6] ; input areset_d1; input CLK; input next; input \axaddr_incr_reg[6] ; input \axaddr_incr_reg[7] ; input \axaddr_incr_reg[9] ; input \axaddr_incr_reg[10] ; input \axaddr_incr_reg[11] ; input \axaddr_incr_reg[12] ; input \axaddr_incr_reg[13] ; input \axaddr_incr_reg[14] ; input \axaddr_incr_reg[15] ; input \axaddr_incr_reg[16] ; input \axaddr_incr_reg[17] ; input \axaddr_incr_reg[18] ; input \axaddr_incr_reg[19] ; input \axaddr_incr_reg[20] ; input \axaddr_incr_reg[21] ; input \axaddr_incr_reg[22] ; input \axaddr_incr_reg[23] ; input \axaddr_incr_reg[24] ; input \axaddr_incr_reg[25] ; input \axaddr_incr_reg[26] ; input \axaddr_incr_reg[27] ; input \axaddr_incr_reg[28] ; input \axaddr_incr_reg[29] ; input \axaddr_incr_reg[5] ; input axready_reg; input [7:0]s_axi_arlen; input s_axi_arvalid; input [29:0]s_axi_araddr; input \RD_PRI_REG_STARVE.rnw_i_reg ; input axready_reg_0; input [0:0]s_axi_arburst; input [0:0]s_axi_arid; wire CLK; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire [23:0]\app_addr_r1_reg[27] ; wire \app_addr_r1_reg[6] ; wire ar_cmd_fsm_0_n_101; wire ar_cmd_fsm_0_n_102; wire ar_cmd_fsm_0_n_103; wire ar_cmd_fsm_0_n_134; wire ar_cmd_fsm_0_n_135; wire ar_cmd_fsm_0_n_136; wire ar_cmd_fsm_0_n_137; wire ar_cmd_fsm_0_n_138; wire ar_cmd_fsm_0_n_139; wire ar_cmd_fsm_0_n_140; wire ar_cmd_fsm_0_n_141; wire ar_cmd_fsm_0_n_145; wire ar_cmd_fsm_0_n_146; wire ar_cmd_fsm_0_n_86; wire ar_cmd_fsm_0_n_87; wire ar_cmd_fsm_0_n_88; wire ar_cmd_fsm_0_n_89; wire ar_cmd_fsm_0_n_90; wire ar_cmd_fsm_0_n_91; wire ar_cmd_fsm_0_n_92; wire ar_cmd_fsm_0_n_93; wire ar_cmd_fsm_0_n_94; wire ar_cmd_fsm_0_n_95; wire areset_d1; wire arvalid_int; wire [29:0]axaddr; wire [29:0]axaddr_incr; wire \axaddr_incr_reg[10] ; wire \axaddr_incr_reg[11] ; wire \axaddr_incr_reg[12] ; wire \axaddr_incr_reg[13] ; wire \axaddr_incr_reg[14] ; wire \axaddr_incr_reg[15] ; wire \axaddr_incr_reg[16] ; wire \axaddr_incr_reg[17] ; wire \axaddr_incr_reg[18] ; wire \axaddr_incr_reg[19] ; wire \axaddr_incr_reg[20] ; wire \axaddr_incr_reg[21] ; wire \axaddr_incr_reg[22] ; wire \axaddr_incr_reg[23] ; wire \axaddr_incr_reg[24] ; wire \axaddr_incr_reg[25] ; wire \axaddr_incr_reg[26] ; wire \axaddr_incr_reg[27] ; wire \axaddr_incr_reg[28] ; wire \axaddr_incr_reg[29] ; wire \axaddr_incr_reg[5] ; wire \axaddr_incr_reg[6] ; wire \axaddr_incr_reg[7] ; wire \axaddr_incr_reg[9] ; wire [8:5]axaddr_int; wire [29:0]axaddr_int__0; wire [1:1]axburst; wire axi_mc_cmd_translator_0_n_30; wire axi_mc_cmd_translator_0_n_31; wire axi_mc_cmd_translator_0_n_32; wire axi_mc_cmd_translator_0_n_33; wire axi_mc_cmd_translator_0_n_34; wire axi_mc_cmd_translator_0_n_35; wire axi_mc_cmd_translator_0_n_36; wire axi_mc_cmd_translator_0_n_37; wire axi_mc_cmd_translator_0_n_72; wire axi_mc_cmd_translator_0_n_73; wire axi_mc_cmd_translator_0_n_74; wire axi_mc_cmd_translator_0_n_75; wire \axi_mc_incr_cmd_0/axlen_cnt ; wire [29:0]\axi_mc_incr_cmd_0/p_0_in ; wire [3:0]axi_mc_incr_cmd_byte_addr; wire [29:4]axi_mc_incr_cmd_byte_addr__0; wire \axi_mc_wrap_cmd_0/axlen_cnt ; wire [3:0]\axi_mc_wrap_cmd_0/int_addr ; wire [7:0]axlen; wire [3:0]axlen_int; wire [7:4]axlen_int__0; wire axready_reg; wire axready_reg_0; wire axvalid; wire [1:0]in; wire next; wire [29:0]p_0_in; wire r_push; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; ddr3_if_mig_7series_v4_0_axi_mc_cmd_fsm ar_cmd_fsm_0 (.CLK(CLK), .D({axlen_int__0,axlen_int}), .DI(ar_cmd_fsm_0_n_145), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .\RD_PRI_REG_STARVE.rnw_i_reg (\RD_PRI_REG_STARVE.rnw_i_reg ), .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103}), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[6] (\app_addr_r1_reg[6] ), .areset_d1(areset_d1), .arvalid_int(arvalid_int), .\axaddr_incr_reg[10] (\axaddr_incr_reg[10] ), .\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ), .\axaddr_incr_reg[12] (\axaddr_incr_reg[12] ), .\axaddr_incr_reg[13] (\axaddr_incr_reg[13] ), .\axaddr_incr_reg[14] (\axaddr_incr_reg[14] ), .\axaddr_incr_reg[15] (\axaddr_incr_reg[15] ), .\axaddr_incr_reg[16] (\axaddr_incr_reg[16] ), .\axaddr_incr_reg[17] (\axaddr_incr_reg[17] ), .\axaddr_incr_reg[18] (\axaddr_incr_reg[18] ), .\axaddr_incr_reg[19] (\axaddr_incr_reg[19] ), .\axaddr_incr_reg[20] (\axaddr_incr_reg[20] ), .\axaddr_incr_reg[21] (\axaddr_incr_reg[21] ), .\axaddr_incr_reg[22] (\axaddr_incr_reg[22] ), .\axaddr_incr_reg[23] (\axaddr_incr_reg[23] ), .\axaddr_incr_reg[24] (\axaddr_incr_reg[24] ), .\axaddr_incr_reg[25] (\axaddr_incr_reg[25] ), .\axaddr_incr_reg[26] (\axaddr_incr_reg[26] ), .\axaddr_incr_reg[27] (\axaddr_incr_reg[27] ), .\axaddr_incr_reg[28] (\axaddr_incr_reg[28] ), .\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:8],axi_mc_incr_cmd_byte_addr__0[4]}), .\axaddr_incr_reg[29]_0 (p_0_in), .\axaddr_incr_reg[29]_1 (axaddr_incr), .\axaddr_incr_reg[29]_2 (\axaddr_incr_reg[29] ), .\axaddr_incr_reg[5] (\axaddr_incr_reg[5] ), .\axaddr_incr_reg[6] (\axaddr_incr_reg[6] ), .\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ), .\axaddr_incr_reg[9] (\axaddr_incr_reg[9] ), .\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}), .\axaddr_reg[29]_0 (axaddr), .axburst(axburst), .\axburst_reg[1] (ar_cmd_fsm_0_n_95), .\axid_reg[0] (ar_cmd_fsm_0_n_146), .\axlen_cnt_reg[0] (\axi_mc_wrap_cmd_0/axlen_cnt ), .\axlen_cnt_reg[3] ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}), .\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .\axlen_cnt_reg[7] ({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}), .\axlen_reg[7] (axlen), .axready_reg_0(axready_reg), .axready_reg_1(axready_reg_0), .axvalid(axvalid), .in(in[1]), .in0(axi_mc_incr_cmd_byte_addr), .\int_addr_reg[3] ({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}), .\int_addr_reg[3]_0 (\axi_mc_wrap_cmd_0/int_addr ), .next(next), .out(\axi_mc_incr_cmd_0/p_0_in ), .r_rlast_reg(ar_cmd_fsm_0_n_94), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid)); FDRE \axaddr_reg[0] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[0]), .Q(axaddr[0]), .R(1'b0)); FDRE \axaddr_reg[10] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[10]), .Q(axaddr[10]), .R(1'b0)); FDRE \axaddr_reg[11] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[11]), .Q(axaddr[11]), .R(1'b0)); FDRE \axaddr_reg[12] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[12]), .Q(axaddr[12]), .R(1'b0)); FDRE \axaddr_reg[13] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[13]), .Q(axaddr[13]), .R(1'b0)); FDRE \axaddr_reg[14] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[14]), .Q(axaddr[14]), .R(1'b0)); FDRE \axaddr_reg[15] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[15]), .Q(axaddr[15]), .R(1'b0)); FDRE \axaddr_reg[16] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[16]), .Q(axaddr[16]), .R(1'b0)); FDRE \axaddr_reg[17] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[17]), .Q(axaddr[17]), .R(1'b0)); FDRE \axaddr_reg[18] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[18]), .Q(axaddr[18]), .R(1'b0)); FDRE \axaddr_reg[19] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[19]), .Q(axaddr[19]), .R(1'b0)); FDRE \axaddr_reg[1] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[1]), .Q(axaddr[1]), .R(1'b0)); FDRE \axaddr_reg[20] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[20]), .Q(axaddr[20]), .R(1'b0)); FDRE \axaddr_reg[21] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[21]), .Q(axaddr[21]), .R(1'b0)); FDRE \axaddr_reg[22] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[22]), .Q(axaddr[22]), .R(1'b0)); FDRE \axaddr_reg[23] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[23]), .Q(axaddr[23]), .R(1'b0)); FDRE \axaddr_reg[24] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[24]), .Q(axaddr[24]), .R(1'b0)); FDRE \axaddr_reg[25] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[25]), .Q(axaddr[25]), .R(1'b0)); FDRE \axaddr_reg[26] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[26]), .Q(axaddr[26]), .R(1'b0)); FDRE \axaddr_reg[27] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[27]), .Q(axaddr[27]), .R(1'b0)); FDRE \axaddr_reg[28] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[28]), .Q(axaddr[28]), .R(1'b0)); FDRE \axaddr_reg[29] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[29]), .Q(axaddr[29]), .R(1'b0)); FDRE \axaddr_reg[2] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[2]), .Q(axaddr[2]), .R(1'b0)); FDRE \axaddr_reg[3] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[3]), .Q(axaddr[3]), .R(1'b0)); FDRE \axaddr_reg[4] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[4]), .Q(axaddr[4]), .R(1'b0)); FDRE \axaddr_reg[5] (.C(CLK), .CE(1'b1), .D(axaddr_int[5]), .Q(axaddr[5]), .R(1'b0)); FDRE \axaddr_reg[6] (.C(CLK), .CE(1'b1), .D(axaddr_int[6]), .Q(axaddr[6]), .R(1'b0)); FDRE \axaddr_reg[7] (.C(CLK), .CE(1'b1), .D(axaddr_int[7]), .Q(axaddr[7]), .R(1'b0)); FDRE \axaddr_reg[8] (.C(CLK), .CE(1'b1), .D(axaddr_int[8]), .Q(axaddr[8]), .R(1'b0)); FDRE \axaddr_reg[9] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[9]), .Q(axaddr[9]), .R(1'b0)); FDRE \axburst_reg[1] (.C(CLK), .CE(1'b1), .D(ar_cmd_fsm_0_n_95), .Q(axburst), .R(1'b0)); ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator__parameterized0 axi_mc_cmd_translator_0 (.CLK(CLK), .D({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}), .DI(ar_cmd_fsm_0_n_145), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103,axi_mc_incr_cmd_byte_addr__0[4]}), .\app_addr_r1_reg[27] (axaddr_incr), .\app_addr_r1_reg[6] (\axi_mc_wrap_cmd_0/int_addr ), .areset_d1(areset_d1), .\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .\axlen_cnt_reg[3]_0 ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}), .axready_reg(axi_mc_incr_cmd_byte_addr__0[29:8]), .axready_reg_0(p_0_in), .axready_reg_1(\axi_mc_wrap_cmd_0/axlen_cnt ), .axready_reg_2({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}), .in0(axi_mc_incr_cmd_byte_addr), .out(\axi_mc_incr_cmd_0/p_0_in )); FDRE \axid_reg[0] (.C(CLK), .CE(1'b1), .D(ar_cmd_fsm_0_n_146), .Q(in[1]), .R(1'b0)); FDRE \axlen_reg[0] (.C(CLK), .CE(1'b1), .D(axlen_int[0]), .Q(axlen[0]), .R(1'b0)); FDRE \axlen_reg[1] (.C(CLK), .CE(1'b1), .D(axlen_int[1]), .Q(axlen[1]), .R(1'b0)); FDRE \axlen_reg[2] (.C(CLK), .CE(1'b1), .D(axlen_int[2]), .Q(axlen[2]), .R(1'b0)); FDRE \axlen_reg[3] (.C(CLK), .CE(1'b1), .D(axlen_int[3]), .Q(axlen[3]), .R(1'b0)); FDRE \axlen_reg[4] (.C(CLK), .CE(1'b1), .D(axlen_int__0[4]), .Q(axlen[4]), .R(1'b0)); FDRE \axlen_reg[5] (.C(CLK), .CE(1'b1), .D(axlen_int__0[5]), .Q(axlen[5]), .R(1'b0)); FDRE \axlen_reg[6] (.C(CLK), .CE(1'b1), .D(axlen_int__0[6]), .Q(axlen[6]), .R(1'b0)); FDRE \axlen_reg[7] (.C(CLK), .CE(1'b1), .D(axlen_int__0[7]), .Q(axlen[7]), .R(1'b0)); FDRE axvalid_reg (.C(CLK), .CE(1'b1), .D(arvalid_int), .Q(axvalid), .R(areset_d1)); FDRE r_push_reg (.C(CLK), .CE(1'b1), .D(next), .Q(r_push), .R(1'b0)); FDRE r_rlast_reg (.C(CLK), .CE(1'b1), .D(ar_cmd_fsm_0_n_94), .Q(in[0]), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_aw_channel (s_axi_awready, awvalid_int, b_awid, b_push, \app_addr_r1_reg[4] , \app_addr_r1_reg[5] , \app_addr_r1_reg[6] , \app_addr_r1_reg[7] , \app_addr_r1_reg[8] , \app_addr_r1_reg[9] , \app_addr_r1_reg[10] , \app_addr_r1_reg[11] , \app_addr_r1_reg[12] , \app_addr_r1_reg[13] , \app_addr_r1_reg[14] , \app_addr_r1_reg[15] , \app_addr_r1_reg[16] , \app_addr_r1_reg[17] , \app_addr_r1_reg[18] , \app_addr_r1_reg[19] , \app_addr_r1_reg[20] , \app_addr_r1_reg[21] , \app_addr_r1_reg[22] , \app_addr_r1_reg[23] , \app_addr_r1_reg[24] , \app_addr_r1_reg[25] , \app_addr_r1_reg[26] , \app_addr_r1_reg[27] , \app_addr_r1_reg[3] , areset_d1, CLK, axready_reg, s_axi_awlen, s_axi_awvalid, \RD_PRI_REG_STARVE.rnw_i_reg , s_axi_awaddr, \int_addr_reg[3] , axready_reg_0, s_axi_awburst, \RD_PRI_REG_STARVE.rnw_i_reg_0 , s_axi_awid); output s_axi_awready; output awvalid_int; output b_awid; output b_push; output \app_addr_r1_reg[4] ; output \app_addr_r1_reg[5] ; output [0:0]\app_addr_r1_reg[6] ; output \app_addr_r1_reg[7] ; output \app_addr_r1_reg[8] ; output \app_addr_r1_reg[9] ; output \app_addr_r1_reg[10] ; output \app_addr_r1_reg[11] ; output \app_addr_r1_reg[12] ; output \app_addr_r1_reg[13] ; output \app_addr_r1_reg[14] ; output \app_addr_r1_reg[15] ; output \app_addr_r1_reg[16] ; output \app_addr_r1_reg[17] ; output \app_addr_r1_reg[18] ; output \app_addr_r1_reg[19] ; output \app_addr_r1_reg[20] ; output \app_addr_r1_reg[21] ; output \app_addr_r1_reg[22] ; output \app_addr_r1_reg[23] ; output \app_addr_r1_reg[24] ; output \app_addr_r1_reg[25] ; output \app_addr_r1_reg[26] ; output \app_addr_r1_reg[27] ; output \app_addr_r1_reg[3] ; input areset_d1; input CLK; input axready_reg; input [7:0]s_axi_awlen; input s_axi_awvalid; input \RD_PRI_REG_STARVE.rnw_i_reg ; input [29:0]s_axi_awaddr; input \int_addr_reg[3] ; input axready_reg_0; input [0:0]s_axi_awburst; input \RD_PRI_REG_STARVE.rnw_i_reg_0 ; input [0:0]s_axi_awid; wire CLK; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire \RD_PRI_REG_STARVE.rnw_i_reg_0 ; wire \app_addr_r1_reg[10] ; wire \app_addr_r1_reg[11] ; wire \app_addr_r1_reg[12] ; wire \app_addr_r1_reg[13] ; wire \app_addr_r1_reg[14] ; wire \app_addr_r1_reg[15] ; wire \app_addr_r1_reg[16] ; wire \app_addr_r1_reg[17] ; wire \app_addr_r1_reg[18] ; wire \app_addr_r1_reg[19] ; wire \app_addr_r1_reg[20] ; wire \app_addr_r1_reg[21] ; wire \app_addr_r1_reg[22] ; wire \app_addr_r1_reg[23] ; wire \app_addr_r1_reg[24] ; wire \app_addr_r1_reg[25] ; wire \app_addr_r1_reg[26] ; wire \app_addr_r1_reg[27] ; wire \app_addr_r1_reg[3] ; wire \app_addr_r1_reg[4] ; wire \app_addr_r1_reg[5] ; wire [0:0]\app_addr_r1_reg[6] ; wire \app_addr_r1_reg[7] ; wire \app_addr_r1_reg[8] ; wire \app_addr_r1_reg[9] ; wire areset_d1; wire aw_cmd_fsm_0_n_10; wire aw_cmd_fsm_0_n_102; wire aw_cmd_fsm_0_n_11; wire aw_cmd_fsm_0_n_12; wire aw_cmd_fsm_0_n_134; wire aw_cmd_fsm_0_n_135; wire aw_cmd_fsm_0_n_136; wire aw_cmd_fsm_0_n_137; wire aw_cmd_fsm_0_n_138; wire aw_cmd_fsm_0_n_139; wire aw_cmd_fsm_0_n_14; wire aw_cmd_fsm_0_n_140; wire aw_cmd_fsm_0_n_141; wire aw_cmd_fsm_0_n_146; wire aw_cmd_fsm_0_n_5; wire aw_cmd_fsm_0_n_6; wire aw_cmd_fsm_0_n_7; wire aw_cmd_fsm_0_n_8; wire aw_cmd_fsm_0_n_9; wire awvalid_int; wire [29:0]axaddr; wire [29:0]axaddr_incr; wire [8:5]axaddr_int; wire [29:0]axaddr_int__0; wire [1:1]axburst; wire axi_mc_cmd_translator_0_n_30; wire axi_mc_cmd_translator_0_n_31; wire axi_mc_cmd_translator_0_n_32; wire axi_mc_cmd_translator_0_n_33; wire axi_mc_cmd_translator_0_n_34; wire axi_mc_cmd_translator_0_n_35; wire axi_mc_cmd_translator_0_n_36; wire axi_mc_cmd_translator_0_n_37; wire axi_mc_cmd_translator_0_n_72; wire axi_mc_cmd_translator_0_n_73; wire axi_mc_cmd_translator_0_n_74; wire axi_mc_cmd_translator_0_n_75; wire \axi_mc_incr_cmd_0/axlen_cnt ; wire [29:0]\axi_mc_incr_cmd_0/p_0_in ; wire [3:0]axi_mc_incr_cmd_byte_addr; wire [29:4]axi_mc_incr_cmd_byte_addr__0; wire \axi_mc_wrap_cmd_0/axlen_cnt ; wire [3:0]\axi_mc_wrap_cmd_0/int_addr ; wire axid; wire [7:0]axlen; wire [3:0]axlen_int; wire [7:4]axlen_int__0; wire axready_reg; wire axready_reg_0; wire axvalid; wire b_awid; wire b_push; wire \int_addr_reg[3] ; wire [29:0]p_0_in; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; ddr3_if_mig_7series_v4_0_axi_mc_wr_cmd_fsm aw_cmd_fsm_0 (.CLK(CLK), .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .\RD_PRI_REG_STARVE.rnw_i_reg (\RD_PRI_REG_STARVE.rnw_i_reg ), .\RD_PRI_REG_STARVE.rnw_i_reg_0 (\RD_PRI_REG_STARVE.rnw_i_reg_0 ), .S(aw_cmd_fsm_0_n_102), .\app_addr_r1_reg[10] (\app_addr_r1_reg[10] ), .\app_addr_r1_reg[11] (\app_addr_r1_reg[11] ), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[13] (\app_addr_r1_reg[13] ), .\app_addr_r1_reg[14] (\app_addr_r1_reg[14] ), .\app_addr_r1_reg[15] (\app_addr_r1_reg[15] ), .\app_addr_r1_reg[16] (\app_addr_r1_reg[16] ), .\app_addr_r1_reg[17] (\app_addr_r1_reg[17] ), .\app_addr_r1_reg[18] (\app_addr_r1_reg[18] ), .\app_addr_r1_reg[19] (\app_addr_r1_reg[19] ), .\app_addr_r1_reg[20] (\app_addr_r1_reg[20] ), .\app_addr_r1_reg[21] (\app_addr_r1_reg[21] ), .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ), .\app_addr_r1_reg[23] (\app_addr_r1_reg[23] ), .\app_addr_r1_reg[24] (\app_addr_r1_reg[24] ), .\app_addr_r1_reg[25] (\app_addr_r1_reg[25] ), .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[3] (\app_addr_r1_reg[3] ), .\app_addr_r1_reg[4] (\app_addr_r1_reg[4] ), .\app_addr_r1_reg[5] (\app_addr_r1_reg[5] ), .\app_addr_r1_reg[6] (\app_addr_r1_reg[6] ), .\app_addr_r1_reg[7] (\app_addr_r1_reg[7] ), .\app_addr_r1_reg[8] (\app_addr_r1_reg[8] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_146), .\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}), .\axaddr_incr_reg[29]_0 (p_0_in), .\axaddr_incr_reg[29]_1 (axaddr_incr), .\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}), .\axaddr_reg[29]_0 (axaddr), .axburst(axburst), .\axburst_reg[1] (aw_cmd_fsm_0_n_14), .axid(axid), .\axlen_cnt_reg[0] (\axi_mc_wrap_cmd_0/axlen_cnt ), .\axlen_cnt_reg[3] ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}), .\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .axlen_int(axlen_int), .\axlen_reg[7] (axlen_int__0), .\axlen_reg[7]_0 (axlen), .axready_reg_0(axready_reg), .axready_reg_1(axready_reg_0), .axvalid(axvalid), .b_awid(b_awid), .b_push(b_push), .in0(axi_mc_incr_cmd_byte_addr), .\int_addr_reg[3] ({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}), .\int_addr_reg[3]_0 (\int_addr_reg[3] ), .\int_addr_reg[3]_1 (\axi_mc_wrap_cmd_0/int_addr ), .out(\axi_mc_incr_cmd_0/p_0_in ), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid)); FDRE \axaddr_reg[0] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[0]), .Q(axaddr[0]), .R(1'b0)); FDRE \axaddr_reg[10] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[10]), .Q(axaddr[10]), .R(1'b0)); FDRE \axaddr_reg[11] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[11]), .Q(axaddr[11]), .R(1'b0)); FDRE \axaddr_reg[12] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[12]), .Q(axaddr[12]), .R(1'b0)); FDRE \axaddr_reg[13] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[13]), .Q(axaddr[13]), .R(1'b0)); FDRE \axaddr_reg[14] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[14]), .Q(axaddr[14]), .R(1'b0)); FDRE \axaddr_reg[15] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[15]), .Q(axaddr[15]), .R(1'b0)); FDRE \axaddr_reg[16] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[16]), .Q(axaddr[16]), .R(1'b0)); FDRE \axaddr_reg[17] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[17]), .Q(axaddr[17]), .R(1'b0)); FDRE \axaddr_reg[18] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[18]), .Q(axaddr[18]), .R(1'b0)); FDRE \axaddr_reg[19] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[19]), .Q(axaddr[19]), .R(1'b0)); FDRE \axaddr_reg[1] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[1]), .Q(axaddr[1]), .R(1'b0)); FDRE \axaddr_reg[20] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[20]), .Q(axaddr[20]), .R(1'b0)); FDRE \axaddr_reg[21] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[21]), .Q(axaddr[21]), .R(1'b0)); FDRE \axaddr_reg[22] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[22]), .Q(axaddr[22]), .R(1'b0)); FDRE \axaddr_reg[23] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[23]), .Q(axaddr[23]), .R(1'b0)); FDRE \axaddr_reg[24] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[24]), .Q(axaddr[24]), .R(1'b0)); FDRE \axaddr_reg[25] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[25]), .Q(axaddr[25]), .R(1'b0)); FDRE \axaddr_reg[26] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[26]), .Q(axaddr[26]), .R(1'b0)); FDRE \axaddr_reg[27] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[27]), .Q(axaddr[27]), .R(1'b0)); FDRE \axaddr_reg[28] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[28]), .Q(axaddr[28]), .R(1'b0)); FDRE \axaddr_reg[29] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[29]), .Q(axaddr[29]), .R(1'b0)); FDRE \axaddr_reg[2] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[2]), .Q(axaddr[2]), .R(1'b0)); FDRE \axaddr_reg[3] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[3]), .Q(axaddr[3]), .R(1'b0)); FDRE \axaddr_reg[4] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[4]), .Q(axaddr[4]), .R(1'b0)); FDRE \axaddr_reg[5] (.C(CLK), .CE(1'b1), .D(axaddr_int[5]), .Q(axaddr[5]), .R(1'b0)); FDRE \axaddr_reg[6] (.C(CLK), .CE(1'b1), .D(axaddr_int[6]), .Q(axaddr[6]), .R(1'b0)); FDRE \axaddr_reg[7] (.C(CLK), .CE(1'b1), .D(axaddr_int[7]), .Q(axaddr[7]), .R(1'b0)); FDRE \axaddr_reg[8] (.C(CLK), .CE(1'b1), .D(axaddr_int[8]), .Q(axaddr[8]), .R(1'b0)); FDRE \axaddr_reg[9] (.C(CLK), .CE(1'b1), .D(axaddr_int__0[9]), .Q(axaddr[9]), .R(1'b0)); FDRE \axburst_reg[1] (.C(CLK), .CE(1'b1), .D(aw_cmd_fsm_0_n_14), .Q(axburst), .R(1'b0)); ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator axi_mc_cmd_translator_0 (.CLK(CLK), .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}), .E(\axi_mc_incr_cmd_0/axlen_cnt ), .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}), .S(aw_cmd_fsm_0_n_102), .\app_addr_r1_reg[27] (axaddr_incr), .areset_d1(areset_d1), .\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}), .\axlen_cnt_reg[3]_0 ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}), .axready_reg({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}), .axready_reg_0(aw_cmd_fsm_0_n_146), .axready_reg_1(p_0_in), .axready_reg_2(\axi_mc_wrap_cmd_0/axlen_cnt ), .axready_reg_3({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}), .in0(axi_mc_incr_cmd_byte_addr), .\int_addr_reg[3] (\axi_mc_wrap_cmd_0/int_addr ), .out(\axi_mc_incr_cmd_0/p_0_in )); FDRE \axid_reg[0] (.C(CLK), .CE(1'b1), .D(b_awid), .Q(axid), .R(1'b0)); FDRE \axlen_reg[0] (.C(CLK), .CE(1'b1), .D(axlen_int[0]), .Q(axlen[0]), .R(1'b0)); FDRE \axlen_reg[1] (.C(CLK), .CE(1'b1), .D(axlen_int[1]), .Q(axlen[1]), .R(1'b0)); FDRE \axlen_reg[2] (.C(CLK), .CE(1'b1), .D(axlen_int[2]), .Q(axlen[2]), .R(1'b0)); FDRE \axlen_reg[3] (.C(CLK), .CE(1'b1), .D(axlen_int[3]), .Q(axlen[3]), .R(1'b0)); FDRE \axlen_reg[4] (.C(CLK), .CE(1'b1), .D(axlen_int__0[4]), .Q(axlen[4]), .R(1'b0)); FDRE \axlen_reg[5] (.C(CLK), .CE(1'b1), .D(axlen_int__0[5]), .Q(axlen[5]), .R(1'b0)); FDRE \axlen_reg[6] (.C(CLK), .CE(1'b1), .D(axlen_int__0[6]), .Q(axlen[6]), .R(1'b0)); FDRE \axlen_reg[7] (.C(CLK), .CE(1'b1), .D(axlen_int__0[7]), .Q(axlen[7]), .R(1'b0)); FDRE axvalid_reg (.C(CLK), .CE(1'b1), .D(awvalid_int), .Q(axvalid), .R(areset_d1)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_b_channel (s_axi_bid, s_axi_bvalid, app_en_ns1, wr_cmd_en, E, b_push, b_awid, CLK, areset_d1, app_rdy, \RD_PRI_REG_STARVE.rnw_i_reg , rd_cmd_en, reset_reg, app_en_r1, s_axi_bready, wvalid_int, awvalid_int, app_wdf_rdy); output [0:0]s_axi_bid; output s_axi_bvalid; output app_en_ns1; output wr_cmd_en; output [0:0]E; input b_push; input b_awid; input CLK; input areset_d1; input app_rdy; input \RD_PRI_REG_STARVE.rnw_i_reg ; input rd_cmd_en; input reset_reg; input app_en_r1; input s_axi_bready; input wvalid_int; input awvalid_int; input app_wdf_rdy; wire CLK; wire [0:0]E; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire app_en_ns1; wire app_en_r1; wire app_rdy; wire app_wdf_rdy; wire areset_d1; wire awvalid_int; wire b_awid; wire b_push; wire bhandshake; wire bid_fifo_0_n_5; wire bid_i; wire rd_cmd_en; wire reset_reg; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire wr_cmd_en; wire wvalid_int; ddr3_if_mig_7series_v4_0_axi_mc_fifo bid_fifo_0 (.CLK(CLK), .E(E), .\RD_PRI_REG_STARVE.rnw_i_reg (\RD_PRI_REG_STARVE.rnw_i_reg ), .app_en_ns1(app_en_ns1), .app_en_r1(app_en_r1), .app_rdy(app_rdy), .app_wdf_rdy(app_wdf_rdy), .areset_d1(areset_d1), .awvalid_int(awvalid_int), .b_awid(b_awid), .b_push(b_push), .bhandshake(bhandshake), .bid_i(bid_i), .bvalid_i_reg(bid_fifo_0_n_5), .bvalid_i_reg_0(s_axi_bvalid), .rd_cmd_en(rd_cmd_en), .reset_reg(reset_reg), .s_axi_bready(s_axi_bready), .wr_cmd_en(wr_cmd_en), .wvalid_int(wvalid_int)); FDRE \bid_t_reg[0] (.C(CLK), .CE(bhandshake), .D(bid_i), .Q(s_axi_bid), .R(areset_d1)); FDRE bvalid_i_reg (.C(CLK), .CE(1'b1), .D(bid_fifo_0_n_5), .Q(s_axi_bvalid), .R(areset_d1)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_cmd_arbiter (\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 , mc_app_wdf_wren_reg_reg, next, \axaddr_incr_reg[29] , \axlen_cnt_reg[1] , \axaddr_incr_reg[29]_0 , \axlen_cnt_reg[1]_0 , areset_d1, CLK, rd_cmd_en, wr_cmd_en, app_rdy, s_axi_awburst, s_axi_awready, s_axi_awvalid, s_axi_arburst, axready_reg, s_axi_arvalid, E); output \RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ; output mc_app_wdf_wren_reg_reg; output next; output \axaddr_incr_reg[29] ; output \axlen_cnt_reg[1] ; output \axaddr_incr_reg[29]_0 ; output \axlen_cnt_reg[1]_0 ; input areset_d1; input CLK; input rd_cmd_en; input wr_cmd_en; input app_rdy; input [0:0]s_axi_awburst; input s_axi_awready; input s_axi_awvalid; input [0:0]s_axi_arburst; input axready_reg; input s_axi_arvalid; input [0:0]E; wire CLK; wire [0:0]E; wire \RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ; wire \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ; wire \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ; wire [8:8]\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ; wire \RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ; wire \RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ; wire \RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ; wire \RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ; wire \RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ; wire \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ; wire \RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ; wire [7:0]\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 ; wire app_rdy; wire areset_d1; wire \axaddr_incr_reg[29] ; wire \axaddr_incr_reg[29]_0 ; wire \axlen_cnt_reg[1] ; wire \axlen_cnt_reg[1]_0 ; wire axready_reg; wire mc_app_wdf_wren_reg_reg; wire next; wire [8:0]p_0_in__0; wire [7:0]p_0_in__1; wire rd_cmd_en; wire rd_cmd_en_d1; wire [0:0]s_axi_arburst; wire s_axi_arvalid; wire [0:0]s_axi_awburst; wire s_axi_awready; wire s_axi_awvalid; wire wr_cmd_en; wire wr_cmd_en_d1; wire wr_enable; wire wr_starve_cnt; wire wr_starve_cnt0; (* SOFT_HLUTNM = "soft_lutpair1187" *) LUT4 #( .INIT(16'h8F80)) \RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1 (.I0(rd_cmd_en), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(app_rdy), .I3(rd_cmd_en_d1), .O(\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_cmd_en_d1_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ), .Q(rd_cmd_en_d1), .R(areset_d1)); LUT1 #( .INIT(2'h1)) \RD_PRI_REG_STARVE.rd_starve_cnt[0]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair1191" *) LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.rd_starve_cnt[1]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair1191" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.rd_starve_cnt[2]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair1184" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.rd_starve_cnt[3]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair1184" *) LUT5 #( .INIT(32'h7FFF8000)) \RD_PRI_REG_STARVE.rd_starve_cnt[4]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .I4(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \RD_PRI_REG_STARVE.rd_starve_cnt[5]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I4(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .I5(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ), .O(p_0_in__0[5])); LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.rd_starve_cnt[6]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair1189" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.rd_starve_cnt[7]_i_1 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ), .O(p_0_in__0[7])); LUT2 #( .INIT(4'hE)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1 (.I0(areset_d1), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .O(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1189" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_3 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ), .O(p_0_in__0[8])); LUT6 #( .INIT(64'h8000000000000000)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4 (.I0(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .I2(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .I3(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .I4(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .I5(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .O(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[0] (.C(CLK), .CE(E), .D(p_0_in__0[0]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[1] (.C(CLK), .CE(E), .D(p_0_in__0[1]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[2] (.C(CLK), .CE(E), .D(p_0_in__0[2]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[3] (.C(CLK), .CE(E), .D(p_0_in__0[3]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[4] (.C(CLK), .CE(E), .D(p_0_in__0[4]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[5] (.C(CLK), .CE(E), .D(p_0_in__0[5]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[6] (.C(CLK), .CE(E), .D(p_0_in__0[6]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[7] (.C(CLK), .CE(E), .D(p_0_in__0[7]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] (.C(CLK), .CE(E), .D(p_0_in__0[8]), .Q(\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ), .R(\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 )); LUT5 #( .INIT(32'h55554445)) \RD_PRI_REG_STARVE.rnw_i_i_1 (.I0(wr_enable), .I1(rd_cmd_en), .I2(wr_cmd_en_d1), .I3(wr_cmd_en), .I4(rd_cmd_en_d1), .O(\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 )); FDSE \RD_PRI_REG_STARVE.rnw_i_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .S(areset_d1)); LUT4 #( .INIT(16'h2F20)) \RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1 (.I0(wr_cmd_en), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(app_rdy), .I3(wr_cmd_en_d1), .O(\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 )); FDRE \RD_PRI_REG_STARVE.wr_cmd_en_d1_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ), .Q(wr_cmd_en_d1), .R(areset_d1)); LUT5 #( .INIT(32'h0000BAAA)) \RD_PRI_REG_STARVE.wr_enable_i_1 (.I0(wr_enable), .I1(\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ), .I2(app_rdy), .I3(wr_cmd_en), .I4(wr_starve_cnt0), .O(\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \RD_PRI_REG_STARVE.wr_enable_i_2 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .I4(\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ), .O(\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1188" *) LUT4 #( .INIT(16'h7FFF)) \RD_PRI_REG_STARVE.wr_enable_i_3 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .O(\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 )); FDRE \RD_PRI_REG_STARVE.wr_enable_reg (.C(CLK), .CE(1'b1), .D(\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ), .Q(wr_enable), .R(1'b0)); LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.wr_starve_cnt[0]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair1188" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.wr_starve_cnt[1]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair1185" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.wr_starve_cnt[2]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair1185" *) LUT5 #( .INIT(32'h7FFF8000)) \RD_PRI_REG_STARVE.wr_starve_cnt[3]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I4(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .O(p_0_in__1[3])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \RD_PRI_REG_STARVE.wr_starve_cnt[4]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I4(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .I5(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .O(p_0_in__1[4])); LUT2 #( .INIT(4'h6)) \RD_PRI_REG_STARVE.wr_starve_cnt[5]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .O(p_0_in__1[5])); (* SOFT_HLUTNM = "soft_lutpair1190" *) LUT3 #( .INIT(8'h78)) \RD_PRI_REG_STARVE.wr_starve_cnt[6]_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .O(p_0_in__1[6])); LUT4 #( .INIT(16'hEEEF)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_1 (.I0(areset_d1), .I1(\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ), .I2(wr_cmd_en_d1), .I3(wr_cmd_en), .O(wr_starve_cnt0)); LUT3 #( .INIT(8'h80)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_2 (.I0(app_rdy), .I1(\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ), .I2(wr_cmd_en), .O(wr_starve_cnt)); (* SOFT_HLUTNM = "soft_lutpair1190" *) LUT4 #( .INIT(16'h7F80)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_3 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]), .O(p_0_in__1[7])); LUT6 #( .INIT(64'h8000000000000000)) \RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .I1(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .I2(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I3(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .I4(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .I5(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .O(\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 )); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[0] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[0]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[1] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[1]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[2] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[2]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[3] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[3]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[4] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[4]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[5] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[5]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[6] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[6]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]), .R(wr_starve_cnt0)); FDRE \RD_PRI_REG_STARVE.wr_starve_cnt_reg[7] (.C(CLK), .CE(wr_starve_cnt), .D(p_0_in__1[7]), .Q(\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]), .R(wr_starve_cnt0)); LUT4 #( .INIT(16'h1000)) \axlen_cnt[7]_i_5 (.I0(mc_app_wdf_wren_reg_reg), .I1(s_axi_awburst), .I2(s_axi_awready), .I3(s_axi_awvalid), .O(\axaddr_incr_reg[29] )); (* SOFT_HLUTNM = "soft_lutpair1186" *) LUT4 #( .INIT(16'h1000)) \axlen_cnt[7]_i_5__0 (.I0(next), .I1(s_axi_arburst), .I2(axready_reg), .I3(s_axi_arvalid), .O(\axaddr_incr_reg[29]_0 )); LUT4 #( .INIT(16'h4000)) \int_addr[3]_i_3 (.I0(mc_app_wdf_wren_reg_reg), .I1(s_axi_awburst), .I2(s_axi_awready), .I3(s_axi_awvalid), .O(\axlen_cnt_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1186" *) LUT4 #( .INIT(16'h4000)) \int_addr[3]_i_3__0 (.I0(next), .I1(s_axi_arburst), .I2(axready_reg), .I3(s_axi_arvalid), .O(\axlen_cnt_reg[1]_0 )); LUT3 #( .INIT(8'h40)) mc_app_wdf_wren_reg_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I1(app_rdy), .I2(wr_cmd_en), .O(mc_app_wdf_wren_reg_reg)); (* SOFT_HLUTNM = "soft_lutpair1187" *) LUT3 #( .INIT(8'h80)) r_push_i_1 (.I0(\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ), .I1(app_rdy), .I2(rd_cmd_en), .O(next)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_cmd_fsm (s_axi_arready, D, \app_addr_r1_reg[27] , \axaddr_incr_reg[29] , \axaddr_reg[29] , \axlen_cnt_reg[7] , r_rlast_reg, \axburst_reg[1] , in0, \app_addr_r1_reg[6] , S, \axaddr_incr_reg[29]_0 , \int_addr_reg[3] , \axlen_cnt_reg[3] , arvalid_int, E, \axlen_cnt_reg[0] , DI, \axid_reg[0] , areset_d1, CLK, Q, \axaddr_incr_reg[6] , \axaddr_incr_reg[7] , \axaddr_incr_reg[29]_1 , \axaddr_incr_reg[9] , \axaddr_incr_reg[10] , \axaddr_incr_reg[11] , \axaddr_incr_reg[12] , \axaddr_incr_reg[13] , \axaddr_incr_reg[14] , \axaddr_incr_reg[15] , \axaddr_incr_reg[16] , \axaddr_incr_reg[17] , \axaddr_incr_reg[18] , \axaddr_incr_reg[19] , \axaddr_incr_reg[20] , \axaddr_incr_reg[21] , \axaddr_incr_reg[22] , \axaddr_incr_reg[23] , \axaddr_incr_reg[24] , \axaddr_incr_reg[25] , \axaddr_incr_reg[26] , \axaddr_incr_reg[27] , \axaddr_incr_reg[28] , \axaddr_incr_reg[29]_2 , \axaddr_incr_reg[5] , axready_reg_0, s_axi_arlen, \axlen_reg[7] , next, axvalid, s_axi_arvalid, s_axi_araddr, \axaddr_reg[29]_0 , \int_addr_reg[3]_0 , \RD_PRI_REG_STARVE.rnw_i_reg , out, axready_reg_1, \axlen_cnt_reg[3]_0 , axburst, s_axi_arburst, s_axi_arid, in); output s_axi_arready; output [7:0]D; output [23:0]\app_addr_r1_reg[27] ; output [22:0]\axaddr_incr_reg[29] ; output [29:0]\axaddr_reg[29] ; output [7:0]\axlen_cnt_reg[7] ; output r_rlast_reg; output \axburst_reg[1] ; output [3:0]in0; output \app_addr_r1_reg[6] ; output [2:0]S; output [29:0]\axaddr_incr_reg[29]_0 ; output [3:0]\int_addr_reg[3] ; output [3:0]\axlen_cnt_reg[3] ; output arvalid_int; output [0:0]E; output [0:0]\axlen_cnt_reg[0] ; output [0:0]DI; output \axid_reg[0] ; input areset_d1; input CLK; input [7:0]Q; input \axaddr_incr_reg[6] ; input \axaddr_incr_reg[7] ; input [29:0]\axaddr_incr_reg[29]_1 ; input \axaddr_incr_reg[9] ; input \axaddr_incr_reg[10] ; input \axaddr_incr_reg[11] ; input \axaddr_incr_reg[12] ; input \axaddr_incr_reg[13] ; input \axaddr_incr_reg[14] ; input \axaddr_incr_reg[15] ; input \axaddr_incr_reg[16] ; input \axaddr_incr_reg[17] ; input \axaddr_incr_reg[18] ; input \axaddr_incr_reg[19] ; input \axaddr_incr_reg[20] ; input \axaddr_incr_reg[21] ; input \axaddr_incr_reg[22] ; input \axaddr_incr_reg[23] ; input \axaddr_incr_reg[24] ; input \axaddr_incr_reg[25] ; input \axaddr_incr_reg[26] ; input \axaddr_incr_reg[27] ; input \axaddr_incr_reg[28] ; input \axaddr_incr_reg[29]_2 ; input \axaddr_incr_reg[5] ; input axready_reg_0; input [7:0]s_axi_arlen; input [7:0]\axlen_reg[7] ; input next; input axvalid; input s_axi_arvalid; input [29:0]s_axi_araddr; input [29:0]\axaddr_reg[29]_0 ; input [3:0]\int_addr_reg[3]_0 ; input \RD_PRI_REG_STARVE.rnw_i_reg ; input [29:0]out; input axready_reg_1; input [3:0]\axlen_cnt_reg[3]_0 ; input [0:0]axburst; input [0:0]s_axi_arburst; input [0:0]s_axi_arid; input [0:0]in; wire CLK; wire [7:0]D; wire [0:0]DI; wire [0:0]E; wire [7:0]Q; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire [2:0]S; wire \app_addr_r1[27]_i_3_n_0 ; wire \app_addr_r1[27]_i_4_n_0 ; wire \app_addr_r1[6]_i_6_n_0 ; wire [23:0]\app_addr_r1_reg[27] ; wire \app_addr_r1_reg[6] ; wire areset_d1; wire arvalid_int; wire \axaddr_incr_reg[10] ; wire \axaddr_incr_reg[11] ; wire \axaddr_incr_reg[12] ; wire \axaddr_incr_reg[13] ; wire \axaddr_incr_reg[14] ; wire \axaddr_incr_reg[15] ; wire \axaddr_incr_reg[16] ; wire \axaddr_incr_reg[17] ; wire \axaddr_incr_reg[18] ; wire \axaddr_incr_reg[19] ; wire \axaddr_incr_reg[20] ; wire \axaddr_incr_reg[21] ; wire \axaddr_incr_reg[22] ; wire \axaddr_incr_reg[23] ; wire \axaddr_incr_reg[24] ; wire \axaddr_incr_reg[25] ; wire \axaddr_incr_reg[26] ; wire \axaddr_incr_reg[27] ; wire \axaddr_incr_reg[28] ; wire [22:0]\axaddr_incr_reg[29] ; wire [29:0]\axaddr_incr_reg[29]_0 ; wire [29:0]\axaddr_incr_reg[29]_1 ; wire \axaddr_incr_reg[29]_2 ; wire \axaddr_incr_reg[5] ; wire \axaddr_incr_reg[6] ; wire \axaddr_incr_reg[7] ; wire \axaddr_incr_reg[9] ; wire [29:0]\axaddr_reg[29] ; wire [29:0]\axaddr_reg[29]_0 ; wire [0:0]axburst; wire \axburst_reg[1] ; wire [3:2]\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 ; wire [8:5]\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ; wire \axi_mc_cmd_translator_0/incr_axhandshake ; wire \axi_mc_cmd_translator_0/wrap_axhandshake ; wire [7:5]axi_mc_incr_cmd_byte_addr__0; wire \axid_reg[0] ; wire \axlen_cnt[2]_i_2__1_n_0 ; wire \axlen_cnt[2]_i_2__2_n_0 ; wire \axlen_cnt[3]_i_2__1_n_0 ; wire \axlen_cnt[3]_i_2__2_n_0 ; wire \axlen_cnt[4]_i_2__0_n_0 ; wire \axlen_cnt[4]_i_3__0_n_0 ; wire \axlen_cnt[5]_i_2__0_n_0 ; wire \axlen_cnt[5]_i_3__0_n_0 ; wire \axlen_cnt[7]_i_3__0_n_0 ; wire \axlen_cnt[7]_i_4__0_n_0 ; wire [0:0]\axlen_cnt_reg[0] ; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [7:0]\axlen_cnt_reg[7] ; wire [7:0]\axlen_reg[7] ; wire axready_i_1__0_n_0; wire axready_reg_0; wire axready_reg_1; wire axvalid; wire [0:0]in; wire [3:0]in0; wire \int_addr[3]_i_5__0_n_0 ; wire [3:0]\int_addr_reg[3] ; wire [3:0]\int_addr_reg[3]_0 ; wire next; wire [29:0]out; wire r_rlast_i_4_n_0; wire r_rlast_i_5_n_0; wire r_rlast_i_6_n_0; wire r_rlast_reg; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[10]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [12]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [12]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[12] ), .O(\app_addr_r1_reg[27] [6])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[11]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [13]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [13]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[13] ), .O(\app_addr_r1_reg[27] [7])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[12]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [14]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [14]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[14] ), .O(\app_addr_r1_reg[27] [8])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[13]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [15]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [15]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[15] ), .O(\app_addr_r1_reg[27] [9])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[14]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [16]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [16]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[16] ), .O(\app_addr_r1_reg[27] [10])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[15]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [17]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [17]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[17] ), .O(\app_addr_r1_reg[27] [11])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[16]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [18]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [18]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[18] ), .O(\app_addr_r1_reg[27] [12])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[17]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [19]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [19]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[19] ), .O(\app_addr_r1_reg[27] [13])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[18]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [20]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [20]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[20] ), .O(\app_addr_r1_reg[27] [14])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[19]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [21]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [21]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[21] ), .O(\app_addr_r1_reg[27] [15])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[20]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [22]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [22]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[22] ), .O(\app_addr_r1_reg[27] [16])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[21]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [23]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [23]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[23] ), .O(\app_addr_r1_reg[27] [17])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[22]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [24]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [24]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[24] ), .O(\app_addr_r1_reg[27] [18])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[23]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [25]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [25]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[25] ), .O(\app_addr_r1_reg[27] [19])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[24]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [26]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [26]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[26] ), .O(\app_addr_r1_reg[27] [20])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[25]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [27]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [27]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[27] ), .O(\app_addr_r1_reg[27] [21])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[26]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [28]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [28]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[28] ), .O(\app_addr_r1_reg[27] [22])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[27]_i_2 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [29]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [29]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[29]_2 ), .O(\app_addr_r1_reg[27] [23])); (* SOFT_HLUTNM = "soft_lutpair1157" *) LUT4 #( .INIT(16'h02A2)) \app_addr_r1[27]_i_3 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(axburst), .I2(s_axi_arready), .I3(s_axi_arburst), .O(\app_addr_r1[27]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1157" *) LUT4 #( .INIT(16'hE200)) \app_addr_r1[27]_i_4 (.I0(axburst), .I1(s_axi_arready), .I2(s_axi_arburst), .I3(\RD_PRI_REG_STARVE.rnw_i_reg ), .O(\app_addr_r1[27]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFF888)) \app_addr_r1[3]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(axi_mc_incr_cmd_byte_addr__0[5]), .I2(\app_addr_r1[27]_i_4_n_0 ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I4(\axaddr_incr_reg[5] ), .O(\app_addr_r1_reg[27] [0])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[3]_i_2 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .O(axi_mc_incr_cmd_byte_addr__0[5])); LUT5 #( .INIT(32'hFFFFF888)) \app_addr_r1[4]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(axi_mc_incr_cmd_byte_addr__0[6]), .I2(\app_addr_r1[27]_i_4_n_0 ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]), .I4(\axaddr_incr_reg[6] ), .O(\app_addr_r1_reg[27] [1])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[4]_i_2 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .O(axi_mc_incr_cmd_byte_addr__0[6])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[4]_i_3 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [1]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6])); LUT5 #( .INIT(32'hFFFFF888)) \app_addr_r1[5]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(axi_mc_incr_cmd_byte_addr__0[7]), .I2(\app_addr_r1[27]_i_4_n_0 ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I4(\axaddr_incr_reg[7] ), .O(\app_addr_r1_reg[27] [2])); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[5]_i_2 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .O(axi_mc_incr_cmd_byte_addr__0[7])); LUT6 #( .INIT(64'hCACFCAC000000000)) \app_addr_r1[6]_i_2 (.I0(\int_addr_reg[3]_0 [3]), .I1(\axaddr_reg[29] [8]), .I2(\app_addr_r1[6]_i_6_n_0 ), .I3(\axburst_reg[1] ), .I4(\axaddr_incr_reg[29]_1 [8]), .I5(\RD_PRI_REG_STARVE.rnw_i_reg ), .O(\app_addr_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair1160" *) LUT2 #( .INIT(4'h8)) \app_addr_r1[6]_i_6 (.I0(s_axi_arvalid), .I1(s_axi_arready), .O(\app_addr_r1[6]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[7]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [9]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [9]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[9] ), .O(\app_addr_r1_reg[27] [3])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[8]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [10]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [10]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[10] ), .O(\app_addr_r1_reg[27] [4])); LUT6 #( .INIT(64'hFFFFFFFFFF08A808)) \app_addr_r1[9]_i_1 (.I0(\app_addr_r1[27]_i_3_n_0 ), .I1(\axaddr_incr_reg[29]_1 [11]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_reg[29] [11]), .I4(\app_addr_r1[27]_i_4_n_0 ), .I5(\axaddr_incr_reg[11] ), .O(\app_addr_r1_reg[27] [5])); (* SOFT_HLUTNM = "soft_lutpair1125" *) LUT3 #( .INIT(8'hB8)) \axaddr[0]_i_1__0 (.I0(s_axi_araddr[0]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [0]), .O(\axaddr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1137" *) LUT3 #( .INIT(8'hB8)) \axaddr[10]_i_1__0 (.I0(s_axi_araddr[10]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [10]), .O(\axaddr_reg[29] [10])); (* SOFT_HLUTNM = "soft_lutpair1138" *) LUT3 #( .INIT(8'hB8)) \axaddr[11]_i_1__0 (.I0(s_axi_araddr[11]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [11]), .O(\axaddr_reg[29] [11])); (* SOFT_HLUTNM = "soft_lutpair1139" *) LUT3 #( .INIT(8'hB8)) \axaddr[12]_i_1__0 (.I0(s_axi_araddr[12]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [12]), .O(\axaddr_reg[29] [12])); (* SOFT_HLUTNM = "soft_lutpair1145" *) LUT3 #( .INIT(8'hB8)) \axaddr[13]_i_1__0 (.I0(s_axi_araddr[13]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [13]), .O(\axaddr_reg[29] [13])); (* SOFT_HLUTNM = "soft_lutpair1140" *) LUT3 #( .INIT(8'hB8)) \axaddr[14]_i_1__0 (.I0(s_axi_araddr[14]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [14]), .O(\axaddr_reg[29] [14])); (* SOFT_HLUTNM = "soft_lutpair1142" *) LUT3 #( .INIT(8'hB8)) \axaddr[15]_i_1__0 (.I0(s_axi_araddr[15]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [15]), .O(\axaddr_reg[29] [15])); (* SOFT_HLUTNM = "soft_lutpair1143" *) LUT3 #( .INIT(8'hB8)) \axaddr[16]_i_1__0 (.I0(s_axi_araddr[16]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [16]), .O(\axaddr_reg[29] [16])); (* SOFT_HLUTNM = "soft_lutpair1149" *) LUT3 #( .INIT(8'hB8)) \axaddr[17]_i_1__0 (.I0(s_axi_araddr[17]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [17]), .O(\axaddr_reg[29] [17])); (* SOFT_HLUTNM = "soft_lutpair1144" *) LUT3 #( .INIT(8'hB8)) \axaddr[18]_i_1__0 (.I0(s_axi_araddr[18]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [18]), .O(\axaddr_reg[29] [18])); (* SOFT_HLUTNM = "soft_lutpair1146" *) LUT3 #( .INIT(8'hB8)) \axaddr[19]_i_1__0 (.I0(s_axi_araddr[19]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [19]), .O(\axaddr_reg[29] [19])); (* SOFT_HLUTNM = "soft_lutpair1126" *) LUT3 #( .INIT(8'hB8)) \axaddr[1]_i_1__0 (.I0(s_axi_araddr[1]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [1]), .O(\axaddr_reg[29] [1])); (* SOFT_HLUTNM = "soft_lutpair1147" *) LUT3 #( .INIT(8'hB8)) \axaddr[20]_i_1__0 (.I0(s_axi_araddr[20]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [20]), .O(\axaddr_reg[29] [20])); (* SOFT_HLUTNM = "soft_lutpair1153" *) LUT3 #( .INIT(8'hB8)) \axaddr[21]_i_1__0 (.I0(s_axi_araddr[21]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [21]), .O(\axaddr_reg[29] [21])); (* SOFT_HLUTNM = "soft_lutpair1148" *) LUT3 #( .INIT(8'hB8)) \axaddr[22]_i_1__0 (.I0(s_axi_araddr[22]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [22]), .O(\axaddr_reg[29] [22])); (* SOFT_HLUTNM = "soft_lutpair1150" *) LUT3 #( .INIT(8'hB8)) \axaddr[23]_i_1__0 (.I0(s_axi_araddr[23]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [23]), .O(\axaddr_reg[29] [23])); (* SOFT_HLUTNM = "soft_lutpair1151" *) LUT3 #( .INIT(8'hB8)) \axaddr[24]_i_1__0 (.I0(s_axi_araddr[24]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [24]), .O(\axaddr_reg[29] [24])); (* SOFT_HLUTNM = "soft_lutpair1133" *) LUT3 #( .INIT(8'hB8)) \axaddr[25]_i_1__0 (.I0(s_axi_araddr[25]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [25]), .O(\axaddr_reg[29] [25])); (* SOFT_HLUTNM = "soft_lutpair1152" *) LUT3 #( .INIT(8'hB8)) \axaddr[26]_i_1__0 (.I0(s_axi_araddr[26]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [26]), .O(\axaddr_reg[29] [26])); (* SOFT_HLUTNM = "soft_lutpair1154" *) LUT3 #( .INIT(8'hB8)) \axaddr[27]_i_1__0 (.I0(s_axi_araddr[27]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [27]), .O(\axaddr_reg[29] [27])); (* SOFT_HLUTNM = "soft_lutpair1155" *) LUT3 #( .INIT(8'hB8)) \axaddr[28]_i_1__0 (.I0(s_axi_araddr[28]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [28]), .O(\axaddr_reg[29] [28])); (* SOFT_HLUTNM = "soft_lutpair1156" *) LUT3 #( .INIT(8'hB8)) \axaddr[29]_i_1__0 (.I0(s_axi_araddr[29]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [29]), .O(\axaddr_reg[29] [29])); (* SOFT_HLUTNM = "soft_lutpair1127" *) LUT3 #( .INIT(8'hB8)) \axaddr[2]_i_1__0 (.I0(s_axi_araddr[2]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [2]), .O(\axaddr_reg[29] [2])); (* SOFT_HLUTNM = "soft_lutpair1128" *) LUT3 #( .INIT(8'hB8)) \axaddr[3]_i_1__0 (.I0(s_axi_araddr[3]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [3]), .O(\axaddr_reg[29] [3])); (* SOFT_HLUTNM = "soft_lutpair1131" *) LUT3 #( .INIT(8'hB8)) \axaddr[4]_i_1__0 (.I0(s_axi_araddr[4]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [4]), .O(\axaddr_reg[29] [4])); (* SOFT_HLUTNM = "soft_lutpair1130" *) LUT3 #( .INIT(8'hB8)) \axaddr[5]_i_1__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .O(\axaddr_reg[29] [5])); (* SOFT_HLUTNM = "soft_lutpair1132" *) LUT3 #( .INIT(8'hB8)) \axaddr[6]_i_1__0 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .O(\axaddr_reg[29] [6])); (* SOFT_HLUTNM = "soft_lutpair1135" *) LUT3 #( .INIT(8'hB8)) \axaddr[7]_i_1__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .O(\axaddr_reg[29] [7])); (* SOFT_HLUTNM = "soft_lutpair1136" *) LUT3 #( .INIT(8'hB8)) \axaddr[8]_i_1__0 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .O(\axaddr_reg[29] [8])); (* SOFT_HLUTNM = "soft_lutpair1141" *) LUT3 #( .INIT(8'hB8)) \axaddr[9]_i_1__0 (.I0(s_axi_araddr[9]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [9]), .O(\axaddr_reg[29] [9])); (* SOFT_HLUTNM = "soft_lutpair1125" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[0]_i_1__0 (.I0(s_axi_araddr[0]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [0]), .I3(axready_reg_0), .I4(out[0]), .O(\axaddr_incr_reg[29]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair1137" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[10]_i_1__0 (.I0(s_axi_araddr[10]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [10]), .I3(axready_reg_0), .I4(out[10]), .O(\axaddr_incr_reg[29]_0 [10])); (* SOFT_HLUTNM = "soft_lutpair1138" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[11]_i_1__0 (.I0(s_axi_araddr[11]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [11]), .I3(axready_reg_0), .I4(out[11]), .O(\axaddr_incr_reg[29]_0 [11])); (* SOFT_HLUTNM = "soft_lutpair1139" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[12]_i_1__0 (.I0(s_axi_araddr[12]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [12]), .I3(axready_reg_0), .I4(out[12]), .O(\axaddr_incr_reg[29]_0 [12])); (* SOFT_HLUTNM = "soft_lutpair1145" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[13]_i_1__0 (.I0(s_axi_araddr[13]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [13]), .I3(axready_reg_0), .I4(out[13]), .O(\axaddr_incr_reg[29]_0 [13])); (* SOFT_HLUTNM = "soft_lutpair1140" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[14]_i_1__0 (.I0(s_axi_araddr[14]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [14]), .I3(axready_reg_0), .I4(out[14]), .O(\axaddr_incr_reg[29]_0 [14])); (* SOFT_HLUTNM = "soft_lutpair1142" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[15]_i_1__0 (.I0(s_axi_araddr[15]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [15]), .I3(axready_reg_0), .I4(out[15]), .O(\axaddr_incr_reg[29]_0 [15])); (* SOFT_HLUTNM = "soft_lutpair1143" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[16]_i_1__0 (.I0(s_axi_araddr[16]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [16]), .I3(axready_reg_0), .I4(out[16]), .O(\axaddr_incr_reg[29]_0 [16])); (* SOFT_HLUTNM = "soft_lutpair1149" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[17]_i_1__0 (.I0(s_axi_araddr[17]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [17]), .I3(axready_reg_0), .I4(out[17]), .O(\axaddr_incr_reg[29]_0 [17])); (* SOFT_HLUTNM = "soft_lutpair1144" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[18]_i_1__0 (.I0(s_axi_araddr[18]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [18]), .I3(axready_reg_0), .I4(out[18]), .O(\axaddr_incr_reg[29]_0 [18])); (* SOFT_HLUTNM = "soft_lutpair1146" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[19]_i_1__0 (.I0(s_axi_araddr[19]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [19]), .I3(axready_reg_0), .I4(out[19]), .O(\axaddr_incr_reg[29]_0 [19])); (* SOFT_HLUTNM = "soft_lutpair1126" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[1]_i_1__0 (.I0(s_axi_araddr[1]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [1]), .I3(axready_reg_0), .I4(out[1]), .O(\axaddr_incr_reg[29]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair1147" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[20]_i_1__0 (.I0(s_axi_araddr[20]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [20]), .I3(axready_reg_0), .I4(out[20]), .O(\axaddr_incr_reg[29]_0 [20])); (* SOFT_HLUTNM = "soft_lutpair1153" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[21]_i_1__0 (.I0(s_axi_araddr[21]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [21]), .I3(axready_reg_0), .I4(out[21]), .O(\axaddr_incr_reg[29]_0 [21])); (* SOFT_HLUTNM = "soft_lutpair1148" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[22]_i_1__0 (.I0(s_axi_araddr[22]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [22]), .I3(axready_reg_0), .I4(out[22]), .O(\axaddr_incr_reg[29]_0 [22])); (* SOFT_HLUTNM = "soft_lutpair1150" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[23]_i_1__0 (.I0(s_axi_araddr[23]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [23]), .I3(axready_reg_0), .I4(out[23]), .O(\axaddr_incr_reg[29]_0 [23])); (* SOFT_HLUTNM = "soft_lutpair1151" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[24]_i_1__0 (.I0(s_axi_araddr[24]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [24]), .I3(axready_reg_0), .I4(out[24]), .O(\axaddr_incr_reg[29]_0 [24])); (* SOFT_HLUTNM = "soft_lutpair1133" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[25]_i_1__0 (.I0(s_axi_araddr[25]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [25]), .I3(axready_reg_0), .I4(out[25]), .O(\axaddr_incr_reg[29]_0 [25])); (* SOFT_HLUTNM = "soft_lutpair1152" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[26]_i_1__0 (.I0(s_axi_araddr[26]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [26]), .I3(axready_reg_0), .I4(out[26]), .O(\axaddr_incr_reg[29]_0 [26])); (* SOFT_HLUTNM = "soft_lutpair1154" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[27]_i_1__0 (.I0(s_axi_araddr[27]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [27]), .I3(axready_reg_0), .I4(out[27]), .O(\axaddr_incr_reg[29]_0 [27])); (* SOFT_HLUTNM = "soft_lutpair1155" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[28]_i_1__0 (.I0(s_axi_araddr[28]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [28]), .I3(axready_reg_0), .I4(out[28]), .O(\axaddr_incr_reg[29]_0 [28])); (* SOFT_HLUTNM = "soft_lutpair1156" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[29]_i_1__0 (.I0(s_axi_araddr[29]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [29]), .I3(axready_reg_0), .I4(out[29]), .O(\axaddr_incr_reg[29]_0 [29])); (* SOFT_HLUTNM = "soft_lutpair1127" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[2]_i_1__0 (.I0(s_axi_araddr[2]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [2]), .I3(axready_reg_0), .I4(out[2]), .O(\axaddr_incr_reg[29]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair1128" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[3]_i_1__0 (.I0(s_axi_araddr[3]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [3]), .I3(axready_reg_0), .I4(out[3]), .O(\axaddr_incr_reg[29]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair1131" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[4]_i_1__0 (.I0(s_axi_araddr[4]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [4]), .I3(axready_reg_0), .I4(out[4]), .O(\axaddr_incr_reg[29]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair1130" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[5]_i_1__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(axready_reg_0), .I4(out[5]), .O(\axaddr_incr_reg[29]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair1132" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[6]_i_1__0 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(axready_reg_0), .I4(out[6]), .O(\axaddr_incr_reg[29]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair1135" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[7]_i_1__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(axready_reg_0), .I4(out[7]), .O(\axaddr_incr_reg[29]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair1136" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[8]_i_1__0 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .I3(axready_reg_0), .I4(out[8]), .O(\axaddr_incr_reg[29]_0 [8])); (* SOFT_HLUTNM = "soft_lutpair1141" *) LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[9]_i_1__0 (.I0(s_axi_araddr[9]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [9]), .I3(axready_reg_0), .I4(out[9]), .O(\axaddr_incr_reg[29]_0 [9])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_1__0 (.I0(s_axi_araddr[3]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [3]), .O(in0[3])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_2__0 (.I0(s_axi_araddr[2]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [2]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [2]), .O(in0[2])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_3__0 (.I0(s_axi_araddr[1]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [1]), .O(in0[1])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_4__0 (.I0(s_axi_araddr[0]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [0]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [0]), .O(in0[0])); LUT3 #( .INIT(8'h08)) axaddr_incr_p_inferred_i_5__0 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(s_axi_arburst), .O(\axi_mc_cmd_translator_0/incr_axhandshake )); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_1__0 (.I0(s_axi_araddr[11]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [11]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [11]), .O(\axaddr_incr_reg[29] [4])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_2__0 (.I0(s_axi_araddr[10]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [10]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [10]), .O(\axaddr_incr_reg[29] [3])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_3__0 (.I0(s_axi_araddr[9]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [9]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [9]), .O(\axaddr_incr_reg[29] [2])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_4 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [8]), .O(\axaddr_incr_reg[29] [1])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_1__0 (.I0(s_axi_araddr[15]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [15]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [15]), .O(\axaddr_incr_reg[29] [8])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_2__0 (.I0(s_axi_araddr[14]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [14]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [14]), .O(\axaddr_incr_reg[29] [7])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_3__0 (.I0(s_axi_araddr[13]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [13]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [13]), .O(\axaddr_incr_reg[29] [6])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_4__0 (.I0(s_axi_araddr[12]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [12]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [12]), .O(\axaddr_incr_reg[29] [5])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_1__0 (.I0(s_axi_araddr[19]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [19]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [19]), .O(\axaddr_incr_reg[29] [12])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_2__0 (.I0(s_axi_araddr[18]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [18]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [18]), .O(\axaddr_incr_reg[29] [11])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_3__0 (.I0(s_axi_araddr[17]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [17]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [17]), .O(\axaddr_incr_reg[29] [10])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_4__0 (.I0(s_axi_araddr[16]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [16]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [16]), .O(\axaddr_incr_reg[29] [9])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_1__0 (.I0(s_axi_araddr[23]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [23]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [23]), .O(\axaddr_incr_reg[29] [16])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_2__0 (.I0(s_axi_araddr[22]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [22]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [22]), .O(\axaddr_incr_reg[29] [15])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_3__0 (.I0(s_axi_araddr[21]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [21]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [21]), .O(\axaddr_incr_reg[29] [14])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_4__0 (.I0(s_axi_araddr[20]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [20]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [20]), .O(\axaddr_incr_reg[29] [13])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_1__0 (.I0(s_axi_araddr[27]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [27]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [27]), .O(\axaddr_incr_reg[29] [20])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_2__0 (.I0(s_axi_araddr[26]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [26]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [26]), .O(\axaddr_incr_reg[29] [19])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_3__0 (.I0(s_axi_araddr[25]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [25]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [25]), .O(\axaddr_incr_reg[29] [18])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_4__0 (.I0(s_axi_araddr[24]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [24]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [24]), .O(\axaddr_incr_reg[29] [17])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_1__0 (.I0(s_axi_araddr[29]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [29]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [29]), .O(\axaddr_incr_reg[29] [22])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_2__0 (.I0(s_axi_araddr[28]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [28]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [28]), .O(\axaddr_incr_reg[29] [21])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_1__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .O(DI)); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_2__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .O(S[2])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_3__0 (.I0(s_axi_araddr[6]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .O(S[1])); LUT5 #( .INIT(32'h111DDD1D)) axaddr_incr_p_reg0_carry_i_4__0 (.I0(\axaddr_incr_reg[29]_1 [5]), .I1(\axi_mc_cmd_translator_0/incr_axhandshake ), .I2(\axaddr_reg[29]_0 [5]), .I3(s_axi_arready), .I4(s_axi_araddr[5]), .O(S[0])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_5__0 (.I0(s_axi_araddr[4]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [4]), .O(\axaddr_incr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1159" *) LUT3 #( .INIT(8'hB8)) \axburst[1]_i_1__0 (.I0(s_axi_arburst), .I1(s_axi_arready), .I2(axburst), .O(\axburst_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1160" *) LUT3 #( .INIT(8'hB8)) \axid[0]_i_1__0 (.I0(s_axi_arid), .I1(s_axi_arready), .I2(in), .O(\axid_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1158" *) LUT3 #( .INIT(8'hB8)) \axlen[0]_i_1__0 (.I0(s_axi_arlen[0]), .I1(s_axi_arready), .I2(\axlen_reg[7] [0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair1159" *) LUT3 #( .INIT(8'hB8)) \axlen[1]_i_1__0 (.I0(s_axi_arlen[1]), .I1(s_axi_arready), .I2(\axlen_reg[7] [1]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair1134" *) LUT3 #( .INIT(8'hB8)) \axlen[2]_i_1__0 (.I0(s_axi_arlen[2]), .I1(s_axi_arready), .I2(\axlen_reg[7] [2]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair1122" *) LUT3 #( .INIT(8'hB8)) \axlen[3]_i_1__0 (.I0(s_axi_arlen[3]), .I1(s_axi_arready), .I2(\axlen_reg[7] [3]), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair1119" *) LUT3 #( .INIT(8'hB8)) \axlen[4]_i_1__0 (.I0(s_axi_arlen[4]), .I1(s_axi_arready), .I2(\axlen_reg[7] [4]), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair1121" *) LUT3 #( .INIT(8'hB8)) \axlen[5]_i_1__0 (.I0(s_axi_arlen[5]), .I1(s_axi_arready), .I2(\axlen_reg[7] [5]), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair1124" *) LUT3 #( .INIT(8'hB8)) \axlen[6]_i_1__0 (.I0(s_axi_arlen[6]), .I1(s_axi_arready), .I2(\axlen_reg[7] [6]), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair1123" *) LUT3 #( .INIT(8'hB8)) \axlen[7]_i_1__0 (.I0(s_axi_arlen[7]), .I1(s_axi_arready), .I2(\axlen_reg[7] [7]), .O(D[7])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1__1 (.I0(axready_reg_0), .I1(Q[0]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7] [0]), .I4(s_axi_arready), .I5(s_axi_arlen[0]), .O(\axlen_cnt_reg[7] [0])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1__2 (.I0(axready_reg_1), .I1(\axlen_cnt_reg[3]_0 [0]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7] [0]), .I4(s_axi_arready), .I5(s_axi_arlen[0]), .O(\axlen_cnt_reg[3] [0])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1__1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[1]), .I2(D[0]), .I3(Q[0]), .I4(axready_reg_0), .I5(D[1]), .O(\axlen_cnt_reg[7] [1])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1__2 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [1]), .I2(D[0]), .I3(\axlen_cnt_reg[3]_0 [0]), .I4(axready_reg_1), .I5(D[1]), .O(\axlen_cnt_reg[3] [1])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1__1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[2]), .I2(\axlen_cnt[2]_i_2__1_n_0 ), .I3(axready_reg_0), .I4(D[2]), .O(\axlen_cnt_reg[7] [2])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1__2 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axlen_cnt[2]_i_2__2_n_0 ), .I3(axready_reg_1), .I4(D[2]), .O(\axlen_cnt_reg[3] [2])); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2__1 (.I0(Q[0]), .I1(D[0]), .I2(Q[1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(D[1]), .O(\axlen_cnt[2]_i_2__1_n_0 )); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2__2 (.I0(\axlen_cnt_reg[3]_0 [0]), .I1(D[0]), .I2(\axlen_cnt_reg[3]_0 [1]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(D[1]), .O(\axlen_cnt[2]_i_2__2_n_0 )); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[3]_i_1__1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[3]), .I2(\axlen_cnt[3]_i_2__1_n_0 ), .I3(axready_reg_0), .I4(D[3]), .O(\axlen_cnt_reg[7] [3])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[3]_i_1__2 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [3]), .I2(\axlen_cnt[3]_i_2__2_n_0 ), .I3(axready_reg_1), .I4(D[3]), .O(\axlen_cnt_reg[3] [3])); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \axlen_cnt[3]_i_2__1 (.I0(\axlen_cnt[2]_i_2__1_n_0 ), .I1(Q[2]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7] [2]), .I4(s_axi_arready), .I5(s_axi_arlen[2]), .O(\axlen_cnt[3]_i_2__1_n_0 )); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \axlen_cnt[3]_i_2__2 (.I0(\axlen_cnt[2]_i_2__2_n_0 ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7] [2]), .I4(s_axi_arready), .I5(s_axi_arlen[2]), .O(\axlen_cnt[3]_i_2__2_n_0 )); LUT6 #( .INIT(64'hF606F6F6F6060606)) \axlen_cnt[4]_i_1__0 (.I0(\axlen_cnt[4]_i_2__0_n_0 ), .I1(\axlen_cnt[4]_i_3__0_n_0 ), .I2(axready_reg_0), .I3(s_axi_arlen[4]), .I4(s_axi_arready), .I5(\axlen_reg[7] [4]), .O(\axlen_cnt_reg[7] [4])); LUT6 #( .INIT(64'h0101015151510151)) \axlen_cnt[4]_i_2__0 (.I0(\axlen_cnt[3]_i_2__1_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7] [3]), .I4(s_axi_arready), .I5(s_axi_arlen[3]), .O(\axlen_cnt[4]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1119" *) LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[4]_i_3__0 (.I0(s_axi_arlen[4]), .I1(s_axi_arready), .I2(\axlen_reg[7] [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[4]), .O(\axlen_cnt[4]_i_3__0_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[5]_i_1__0 (.I0(\axlen_cnt[5]_i_2__0_n_0 ), .I1(\axlen_cnt[5]_i_3__0_n_0 ), .I2(axready_reg_0), .I3(s_axi_arlen[5]), .I4(s_axi_arready), .I5(\axlen_reg[7] [5]), .O(\axlen_cnt_reg[7] [5])); (* SOFT_HLUTNM = "soft_lutpair1121" *) LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[5]_i_2__0 (.I0(s_axi_arlen[5]), .I1(s_axi_arready), .I2(\axlen_reg[7] [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[5]), .O(\axlen_cnt[5]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFCFFFCAA)) \axlen_cnt[5]_i_3__0 (.I0(Q[4]), .I1(D[4]), .I2(D[3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[3]), .I5(\axlen_cnt[3]_i_2__1_n_0 ), .O(\axlen_cnt[5]_i_3__0_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[6]_i_1__0 (.I0(\axlen_cnt[7]_i_3__0_n_0 ), .I1(\axlen_cnt[7]_i_4__0_n_0 ), .I2(axready_reg_0), .I3(s_axi_arlen[6]), .I4(s_axi_arready), .I5(\axlen_reg[7] [6]), .O(\axlen_cnt_reg[7] [6])); (* SOFT_HLUTNM = "soft_lutpair1129" *) LUT5 #( .INIT(32'h0E000ECC)) \axlen_cnt[7]_i_1__0 (.I0(s_axi_arvalid), .I1(next), .I2(s_axi_arburst), .I3(s_axi_arready), .I4(axburst), .O(E)); LUT6 #( .INIT(64'hFFFFEEE10000444B)) \axlen_cnt[7]_i_2__0 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[7]), .I2(\axlen_cnt[7]_i_3__0_n_0 ), .I3(\axlen_cnt[7]_i_4__0_n_0 ), .I4(axready_reg_0), .I5(D[7]), .O(\axlen_cnt_reg[7] [7])); (* SOFT_HLUTNM = "soft_lutpair1124" *) LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[7]_i_3__0 (.I0(s_axi_arlen[6]), .I1(s_axi_arready), .I2(\axlen_reg[7] [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[6]), .O(\axlen_cnt[7]_i_3__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEAE)) \axlen_cnt[7]_i_4__0 (.I0(\axlen_cnt[3]_i_2__1_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(D[3]), .I4(\axlen_cnt[4]_i_3__0_n_0 ), .I5(\axlen_cnt[5]_i_2__0_n_0 ), .O(\axlen_cnt[7]_i_4__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1120" *) LUT5 #( .INIT(32'h888FFF8F)) axready_i_1__0 (.I0(next), .I1(r_rlast_reg), .I2(axvalid), .I3(s_axi_arready), .I4(s_axi_arvalid), .O(axready_i_1__0_n_0)); FDRE axready_reg (.C(CLK), .CE(1'b1), .D(axready_i_1__0_n_0), .Q(s_axi_arready), .R(areset_d1)); (* SOFT_HLUTNM = "soft_lutpair1120" *) LUT3 #( .INIT(8'hB8)) axvalid_i_1__0 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(axvalid), .O(arvalid_int)); LUT6 #( .INIT(64'hF606F6F6F6060606)) \int_addr[0]_i_1__0 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I1(D[0]), .I2(axready_reg_1), .I3(s_axi_araddr[5]), .I4(s_axi_arready), .I5(\axaddr_reg[29]_0 [5]), .O(\int_addr_reg[3] [0])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[1]_i_1__0 (.I0(axready_reg_1), .I1(D[1]), .I2(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I3(\int_addr_reg[3]_0 [1]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [6]), .O(\int_addr_reg[3] [1])); LUT5 #( .INIT(32'hB8FFB800)) \int_addr[1]_i_2__0 (.I0(s_axi_araddr[5]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [0]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[2]_i_1__0 (.I0(axready_reg_1), .I1(D[2]), .I2(\int_addr[3]_i_5__0_n_0 ), .I3(\int_addr_reg[3]_0 [2]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [7]), .O(\int_addr_reg[3] [2])); (* SOFT_HLUTNM = "soft_lutpair1158" *) LUT3 #( .INIT(8'h80)) \int_addr[2]_i_2__0 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(s_axi_arburst), .O(\axi_mc_cmd_translator_0/wrap_axhandshake )); (* SOFT_HLUTNM = "soft_lutpair1129" *) LUT5 #( .INIT(32'hCFC08080)) \int_addr[3]_i_1__0 (.I0(s_axi_arvalid), .I1(s_axi_arburst), .I2(s_axi_arready), .I3(axburst), .I4(next), .O(\axlen_cnt_reg[0] )); LUT6 #( .INIT(64'h8BBBBBBBB8888888)) \int_addr[3]_i_2__0 (.I0(\axaddr_reg[29] [8]), .I1(axready_reg_1), .I2(D[3]), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I4(\int_addr[3]_i_5__0_n_0 ), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]), .O(\int_addr_reg[3] [3])); LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_4__0 (.I0(s_axi_araddr[7]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [2]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7])); LUT6 #( .INIT(64'hEEE222E200000000)) \int_addr[3]_i_5__0 (.I0(\int_addr_reg[3]_0 [1]), .I1(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I2(\axaddr_reg[29]_0 [6]), .I3(s_axi_arready), .I4(s_axi_araddr[6]), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .O(\int_addr[3]_i_5__0_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_6__0 (.I0(s_axi_araddr[8]), .I1(s_axi_arready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_0 [3]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8])); LUT6 #( .INIT(64'h0010FFFF00100010)) r_rlast_i_1 (.I0(\axlen_cnt[2]_i_2__2_n_0 ), .I1(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2]), .I2(\axburst_reg[1] ), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3]), .I4(\axlen_cnt[3]_i_2__1_n_0 ), .I5(r_rlast_i_4_n_0), .O(r_rlast_reg)); (* SOFT_HLUTNM = "soft_lutpair1134" *) LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_2 (.I0(s_axi_arlen[2]), .I1(s_axi_arready), .I2(\axlen_reg[7] [2]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\axlen_cnt_reg[3]_0 [2]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2])); LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_3 (.I0(s_axi_arlen[3]), .I1(s_axi_arready), .I2(\axlen_reg[7] [3]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\axlen_cnt_reg[3]_0 [3]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3])); LUT6 #( .INIT(64'h0000000000000001)) r_rlast_i_4 (.I0(r_rlast_i_5_n_0), .I1(\axlen_cnt[7]_i_3__0_n_0 ), .I2(\axlen_cnt[4]_i_3__0_n_0 ), .I3(\axlen_cnt[5]_i_2__0_n_0 ), .I4(\axburst_reg[1] ), .I5(r_rlast_i_6_n_0), .O(r_rlast_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair1123" *) LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_5 (.I0(s_axi_arlen[7]), .I1(s_axi_arready), .I2(\axlen_reg[7] [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[7]), .O(r_rlast_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair1122" *) LUT5 #( .INIT(32'hB8FFB800)) r_rlast_i_6 (.I0(s_axi_arlen[3]), .I1(s_axi_arready), .I2(\axlen_reg[7] [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[3]), .O(r_rlast_i_6_n_0)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator (out, Q, \app_addr_r1_reg[27] , \int_addr_reg[3] , \axlen_cnt_reg[3] , in0, axready_reg, S, axready_reg_0, areset_d1, E, D, CLK, axready_reg_1, axready_reg_2, axready_reg_3, \axlen_cnt_reg[3]_0 ); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; output [3:0]\int_addr_reg[3] ; output [3:0]\axlen_cnt_reg[3] ; input [3:0]in0; input [24:0]axready_reg; input [0:0]S; input [0:0]axready_reg_0; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_1; input [0:0]axready_reg_2; input [3:0]axready_reg_3; input [3:0]\axlen_cnt_reg[3]_0 ; wire CLK; wire [7:0]D; wire [0:0]E; wire [7:0]Q; wire [0:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire areset_d1; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [24:0]axready_reg; wire [0:0]axready_reg_0; wire [29:0]axready_reg_1; wire [0:0]axready_reg_2; wire [3:0]axready_reg_3; wire [3:0]in0; wire [3:0]\int_addr_reg[3] ; wire [29:0]out; ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd axi_mc_incr_cmd_0 (.CLK(CLK), .D(D), .E(E), .Q(Q), .S(S), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .areset_d1(areset_d1), .axready_reg(axready_reg), .axready_reg_0(axready_reg_0), .axready_reg_1(axready_reg_1), .in0(in0), .out(out)); ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd axi_mc_wrap_cmd_0 (.CLK(CLK), .areset_d1(areset_d1), .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ), .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_0 ), .axready_reg(axready_reg_2), .axready_reg_0(axready_reg_3), .\int_addr_reg[3]_0 (\int_addr_reg[3] )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_cmd_translator" *) module ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator__parameterized0 (out, Q, \app_addr_r1_reg[27] , \app_addr_r1_reg[6] , \axlen_cnt_reg[3] , in0, DI, S, axready_reg, areset_d1, E, D, CLK, axready_reg_0, axready_reg_1, axready_reg_2, \axlen_cnt_reg[3]_0 ); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; output [3:0]\app_addr_r1_reg[6] ; output [3:0]\axlen_cnt_reg[3] ; input [3:0]in0; input [0:0]DI; input [3:0]S; input [21:0]axready_reg; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_0; input [0:0]axready_reg_1; input [3:0]axready_reg_2; input [3:0]\axlen_cnt_reg[3]_0 ; wire CLK; wire [7:0]D; wire [0:0]DI; wire [0:0]E; wire [7:0]Q; wire [3:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire [3:0]\app_addr_r1_reg[6] ; wire areset_d1; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [21:0]axready_reg; wire [29:0]axready_reg_0; wire [0:0]axready_reg_1; wire [3:0]axready_reg_2; wire [3:0]in0; wire [29:0]out; ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd__parameterized0 axi_mc_incr_cmd_0 (.CLK(CLK), .D(D), .DI(DI), .E(E), .Q(Q), .S(S), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .areset_d1(areset_d1), .axready_reg(axready_reg), .axready_reg_0(axready_reg_0), .in0(in0), .out(out)); ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd__parameterized0 axi_mc_wrap_cmd_0 (.CLK(CLK), .\app_addr_r1_reg[6] (\app_addr_r1_reg[6] ), .areset_d1(areset_d1), .\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3] ), .\axlen_cnt_reg[3]_1 (\axlen_cnt_reg[3]_0 ), .axready_reg(axready_reg_1), .axready_reg_0(axready_reg_2)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_fifo (bid_i, app_en_ns1, wr_cmd_en, E, bhandshake, bvalid_i_reg, b_push, b_awid, CLK, app_rdy, \RD_PRI_REG_STARVE.rnw_i_reg , rd_cmd_en, reset_reg, app_en_r1, bvalid_i_reg_0, s_axi_bready, wvalid_int, awvalid_int, app_wdf_rdy, areset_d1); output bid_i; output app_en_ns1; output wr_cmd_en; output [0:0]E; output bhandshake; output bvalid_i_reg; input b_push; input b_awid; input CLK; input app_rdy; input \RD_PRI_REG_STARVE.rnw_i_reg ; input rd_cmd_en; input reset_reg; input app_en_r1; input bvalid_i_reg_0; input s_axi_bready; input wvalid_int; input awvalid_int; input app_wdf_rdy; input areset_d1; wire CLK; wire [0:0]E; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire app_en_ns1; wire app_en_r1; wire app_rdy; wire app_wdf_rdy; wire areset_d1; wire awvalid_int; wire b_awid; wire b_push; wire bhandshake; wire bid_i; wire bvalid_i_reg; wire bvalid_i_reg_0; wire \cnt_read[0]_i_1__1_n_0 ; wire \cnt_read[1]_i_1_n_0 ; wire \cnt_read[2]_i_1__0_n_0 ; wire \cnt_read[3]_i_1__0_n_0 ; wire \cnt_read[3]_i_2_n_0 ; wire \cnt_read[3]_i_3_n_0 ; wire [2:0]cnt_read_reg__0; wire [3:3]cnt_read_reg__0__0; wire rd_cmd_en; wire reset_reg; wire s_axi_bready; wire wr_cmd_en; wire wvalid_int; LUT6 #( .INIT(64'h8080808080008080)) \RD_PRI_REG_STARVE.rnw_i_i_2 (.I0(wvalid_int), .I1(awvalid_int), .I2(app_wdf_rdy), .I3(\cnt_read[3]_i_3_n_0 ), .I4(cnt_read_reg__0[0]), .I5(cnt_read_reg__0__0), .O(wr_cmd_en)); LUT4 #( .INIT(16'hA808)) \app_addr_r1[27]_i_1 (.I0(app_rdy), .I1(wr_cmd_en), .I2(\RD_PRI_REG_STARVE.rnw_i_reg ), .I3(rd_cmd_en), .O(E)); LUT6 #( .INIT(64'h0000FD5D0000A808)) app_en_r1_i_1 (.I0(app_rdy), .I1(wr_cmd_en), .I2(\RD_PRI_REG_STARVE.rnw_i_reg ), .I3(rd_cmd_en), .I4(reset_reg), .I5(app_en_r1), .O(app_en_ns1)); LUT2 #( .INIT(4'hB)) \bid_t[0]_i_1 (.I0(s_axi_bready), .I1(bvalid_i_reg_0), .O(bhandshake)); LUT6 #( .INIT(64'h7FFFFFFF7FFF7FFF)) bvalid_i_i_1 (.I0(cnt_read_reg__0__0), .I1(cnt_read_reg__0[1]), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[0]), .I4(s_axi_bready), .I5(bvalid_i_reg_0), .O(bvalid_i_reg)); LUT1 #( .INIT(2'h1)) \cnt_read[0]_i_1__1 (.I0(cnt_read_reg__0[0]), .O(\cnt_read[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'h52D2D2D22D2D2D2D)) \cnt_read[1]_i_1 (.I0(b_push), .I1(bhandshake), .I2(cnt_read_reg__0[0]), .I3(cnt_read_reg__0[2]), .I4(cnt_read_reg__0__0), .I5(cnt_read_reg__0[1]), .O(\cnt_read[1]_i_1_n_0 )); LUT6 #( .INIT(64'h4FFFFF30300000CF)) \cnt_read[2]_i_1__0 (.I0(cnt_read_reg__0__0), .I1(bhandshake), .I2(b_push), .I3(cnt_read_reg__0[0]), .I4(cnt_read_reg__0[1]), .I5(cnt_read_reg__0[2]), .O(\cnt_read[2]_i_1__0_n_0 )); LUT6 #( .INIT(64'h5959AA5959595959)) \cnt_read[3]_i_1__0 (.I0(b_push), .I1(bvalid_i_reg_0), .I2(s_axi_bready), .I3(cnt_read_reg__0[0]), .I4(\cnt_read[3]_i_3_n_0 ), .I5(cnt_read_reg__0__0), .O(\cnt_read[3]_i_1__0_n_0 )); LUT6 #( .INIT(64'h5FFF2000FFBA0045)) \cnt_read[3]_i_2 (.I0(cnt_read_reg__0[1]), .I1(bhandshake), .I2(b_push), .I3(cnt_read_reg__0[0]), .I4(cnt_read_reg__0__0), .I5(cnt_read_reg__0[2]), .O(\cnt_read[3]_i_2_n_0 )); LUT2 #( .INIT(4'h7)) \cnt_read[3]_i_3 (.I0(cnt_read_reg__0[1]), .I1(cnt_read_reg__0[2]), .O(\cnt_read[3]_i_3_n_0 )); FDSE \cnt_read_reg[0] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[0]_i_1__1_n_0 ), .Q(cnt_read_reg__0[0]), .S(areset_d1)); FDSE \cnt_read_reg[1] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[1]_i_1_n_0 ), .Q(cnt_read_reg__0[1]), .S(areset_d1)); FDSE \cnt_read_reg[2] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[2]_i_1__0_n_0 ), .Q(cnt_read_reg__0[2]), .S(areset_d1)); FDSE \cnt_read_reg[3] (.C(CLK), .CE(\cnt_read[3]_i_1__0_n_0 ), .D(\cnt_read[3]_i_2_n_0 ), .Q(cnt_read_reg__0__0), .S(areset_d1)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7][0]_srl8 " *) SRL16E #( .INIT(16'h0000)) \memory_reg[7][0]_srl8 (.A0(cnt_read_reg__0[0]), .A1(cnt_read_reg__0[1]), .A2(cnt_read_reg__0[2]), .A3(1'b0), .CE(b_push), .CLK(CLK), .D(b_awid), .Q(bid_i)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_fifo" *) module ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized0 (rd_cmd_en, E, s_axi_rvalid, p_0_in, \FSM_sequential_state_reg[1] , \FSM_sequential_state_reg[0] , \s_axi_rresp[1] , s_axi_arvalid, s_axi_arready, axvalid, \cnt_read_reg[5]_0 , app_rdy, \trans_buf_out_r_reg[0] , app_rd_data_valid, s_axi_rready, out, tr_empty, in0, Q, CLK, areset_d1); output rd_cmd_en; output [0:0]E; output s_axi_rvalid; output p_0_in; output \FSM_sequential_state_reg[1] ; output \FSM_sequential_state_reg[0] ; output [256:0]\s_axi_rresp[1] ; input s_axi_arvalid; input s_axi_arready; input axvalid; input \cnt_read_reg[5]_0 ; input app_rdy; input \trans_buf_out_r_reg[0] ; input app_rd_data_valid; input s_axi_rready; input [1:0]out; input tr_empty; input [1:0]in0; input [255:0]Q; input CLK; input areset_d1; wire CLK; wire [0:0]E; wire \FSM_sequential_state_reg[0] ; wire \FSM_sequential_state_reg[1] ; wire [255:0]Q; wire app_rd_data_valid; wire app_rdy; wire areset_d1; wire axvalid; wire \cnt_read[0]_i_1_n_0 ; wire \cnt_read[0]_rep_i_1_n_0 ; wire \cnt_read[1]_i_1__0_n_0 ; wire \cnt_read[1]_rep_i_1_n_0 ; wire \cnt_read[2]_i_1__1_n_0 ; wire \cnt_read[2]_rep_i_1_n_0 ; wire \cnt_read[3]_i_1__1_n_0 ; wire \cnt_read[3]_rep_i_1_n_0 ; wire \cnt_read[4]_i_1__0_n_0 ; wire \cnt_read[4]_rep_i_1_n_0 ; wire \cnt_read[5]_i_1_n_0 ; wire \cnt_read[5]_i_2__0_n_0 ; wire \cnt_read[5]_i_3_n_0 ; wire \cnt_read_reg[0]_rep_n_0 ; wire \cnt_read_reg[1]_rep_n_0 ; wire \cnt_read_reg[2]_rep_n_0 ; wire \cnt_read_reg[3]_rep_n_0 ; wire \cnt_read_reg[4]_rep_n_0 ; wire \cnt_read_reg[5]_0 ; wire [5:5]cnt_read_reg__0; wire [4:0]cnt_read_reg__1; wire [1:0]in0; wire [1:0]out; wire p_0_in; wire r_push_i_4_n_0; wire rd_cmd_en; wire rvalid04_in; wire s_axi_arready; wire s_axi_arvalid; wire s_axi_rready; wire [256:0]\s_axi_rresp[1] ; wire s_axi_rvalid; wire tr_empty; wire \trans_buf_out_r_reg[0] ; wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED ; wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ; LUT5 #( .INIT(32'hF7FD4045)) \FSM_sequential_state[0]_i_1 (.I0(out[0]), .I1(p_0_in), .I2(out[1]), .I3(tr_empty), .I4(in0[0]), .O(\FSM_sequential_state_reg[0] )); LUT5 #( .INIT(32'hB7BA0002)) \FSM_sequential_state[1]_i_1 (.I0(out[0]), .I1(p_0_in), .I2(out[1]), .I3(tr_empty), .I4(in0[1]), .O(\FSM_sequential_state_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1194" *) LUT3 #( .INIT(8'hC8)) \FSM_sequential_state[1]_i_2 (.I0(\trans_buf_out_r_reg[0] ), .I1(rvalid04_in), .I2(s_axi_rready), .O(p_0_in)); LUT2 #( .INIT(4'h8)) \RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_2 (.I0(rd_cmd_en), .I1(app_rdy), .O(E)); LUT1 #( .INIT(2'h1)) \cnt_read[0]_i_1 (.I0(cnt_read_reg__1[0]), .O(\cnt_read[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \cnt_read[0]_rep_i_1 (.I0(cnt_read_reg__1[0]), .O(\cnt_read[0]_rep_i_1_n_0 )); LUT6 #( .INIT(64'hAAA6666655599999)) \cnt_read[1]_i_1__0 (.I0(cnt_read_reg__1[0]), .I1(app_rd_data_valid), .I2(s_axi_rready), .I3(\trans_buf_out_r_reg[0] ), .I4(rvalid04_in), .I5(cnt_read_reg__1[1]), .O(\cnt_read[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hAAA6666655599999)) \cnt_read[1]_rep_i_1 (.I0(cnt_read_reg__1[0]), .I1(app_rd_data_valid), .I2(s_axi_rready), .I3(\trans_buf_out_r_reg[0] ), .I4(rvalid04_in), .I5(cnt_read_reg__1[1]), .O(\cnt_read[1]_rep_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1193" *) LUT3 #( .INIT(8'h69)) \cnt_read[2]_i_1__1 (.I0(\cnt_read[5]_i_3_n_0 ), .I1(cnt_read_reg__1[2]), .I2(cnt_read_reg__1[1]), .O(\cnt_read[2]_i_1__1_n_0 )); LUT3 #( .INIT(8'h69)) \cnt_read[2]_rep_i_1 (.I0(\cnt_read[5]_i_3_n_0 ), .I1(cnt_read_reg__1[2]), .I2(cnt_read_reg__1[1]), .O(\cnt_read[2]_rep_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1193" *) LUT4 #( .INIT(16'h78E1)) \cnt_read[3]_i_1__1 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[3]), .I3(cnt_read_reg__1[2]), .O(\cnt_read[3]_i_1__1_n_0 )); LUT4 #( .INIT(16'h78E1)) \cnt_read[3]_rep_i_1 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[3]), .I3(cnt_read_reg__1[2]), .O(\cnt_read[3]_rep_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1192" *) LUT5 #( .INIT(32'h7F80FE01)) \cnt_read[4]_i_1__0 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[2]), .I3(cnt_read_reg__1[4]), .I4(cnt_read_reg__1[3]), .O(\cnt_read[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7F80FE01)) \cnt_read[4]_rep_i_1 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[2]), .I3(cnt_read_reg__1[4]), .I4(cnt_read_reg__1[3]), .O(\cnt_read[4]_rep_i_1_n_0 )); LUT4 #( .INIT(16'h56AA)) \cnt_read[5]_i_1 (.I0(app_rd_data_valid), .I1(s_axi_rready), .I2(\trans_buf_out_r_reg[0] ), .I3(rvalid04_in), .O(\cnt_read[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \cnt_read[5]_i_2__0 (.I0(cnt_read_reg__1[1]), .I1(\cnt_read[5]_i_3_n_0 ), .I2(cnt_read_reg__1[2]), .I3(cnt_read_reg__1[3]), .I4(cnt_read_reg__0), .I5(cnt_read_reg__1[4]), .O(\cnt_read[5]_i_2__0_n_0 )); LUT6 #( .INIT(64'h00088888AAAEEEEE)) \cnt_read[5]_i_3 (.I0(cnt_read_reg__1[0]), .I1(app_rd_data_valid), .I2(s_axi_rready), .I3(\trans_buf_out_r_reg[0] ), .I4(rvalid04_in), .I5(cnt_read_reg__1[1]), .O(\cnt_read[5]_i_3_n_0 )); (* ORIG_CELL_NAME = "cnt_read_reg[0]" *) FDSE \cnt_read_reg[0] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[0]_i_1_n_0 ), .Q(cnt_read_reg__1[0]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[0]" *) FDSE \cnt_read_reg[0]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[0]_rep_i_1_n_0 ), .Q(\cnt_read_reg[0]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[1]" *) FDSE \cnt_read_reg[1] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[1]_i_1__0_n_0 ), .Q(cnt_read_reg__1[1]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[1]" *) FDSE \cnt_read_reg[1]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[1]_rep_i_1_n_0 ), .Q(\cnt_read_reg[1]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[2]" *) FDSE \cnt_read_reg[2] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[2]_i_1__1_n_0 ), .Q(cnt_read_reg__1[2]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[2]" *) FDSE \cnt_read_reg[2]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[2]_rep_i_1_n_0 ), .Q(\cnt_read_reg[2]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[3]" *) FDSE \cnt_read_reg[3] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[3]_i_1__1_n_0 ), .Q(cnt_read_reg__1[3]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[3]" *) FDSE \cnt_read_reg[3]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[3]_rep_i_1_n_0 ), .Q(\cnt_read_reg[3]_rep_n_0 ), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[4]" *) FDSE \cnt_read_reg[4] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[4]_i_1__0_n_0 ), .Q(cnt_read_reg__1[4]), .S(areset_d1)); (* ORIG_CELL_NAME = "cnt_read_reg[4]" *) FDSE \cnt_read_reg[4]_rep (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[4]_rep_i_1_n_0 ), .Q(\cnt_read_reg[4]_rep_n_0 ), .S(areset_d1)); FDSE \cnt_read_reg[5] (.C(CLK), .CE(\cnt_read[5]_i_1_n_0 ), .D(\cnt_read[5]_i_2__0_n_0 ), .Q(cnt_read_reg__0), .S(areset_d1)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][0]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[0]), .Q(\s_axi_rresp[1] [0]), .Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][100]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][100]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[100]), .Q(\s_axi_rresp[1] [100]), .Q31(\NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][101]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][101]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[101]), .Q(\s_axi_rresp[1] [101]), .Q31(\NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][102]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][102]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[102]), .Q(\s_axi_rresp[1] [102]), .Q31(\NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][103]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][103]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[103]), .Q(\s_axi_rresp[1] [103]), .Q31(\NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][104]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][104]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[104]), .Q(\s_axi_rresp[1] [104]), .Q31(\NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][105]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][105]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[105]), .Q(\s_axi_rresp[1] [105]), .Q31(\NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][106]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][106]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[106]), .Q(\s_axi_rresp[1] [106]), .Q31(\NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][107]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][107]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[107]), .Q(\s_axi_rresp[1] [107]), .Q31(\NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][108]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][108]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[108]), .Q(\s_axi_rresp[1] [108]), .Q31(\NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][109]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][109]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[109]), .Q(\s_axi_rresp[1] [109]), .Q31(\NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][10]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[10]), .Q(\s_axi_rresp[1] [10]), .Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][110]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][110]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[110]), .Q(\s_axi_rresp[1] [110]), .Q31(\NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][111]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][111]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[111]), .Q(\s_axi_rresp[1] [111]), .Q31(\NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][112]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][112]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[112]), .Q(\s_axi_rresp[1] [112]), .Q31(\NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][113]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][113]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[113]), .Q(\s_axi_rresp[1] [113]), .Q31(\NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][114]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][114]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[114]), .Q(\s_axi_rresp[1] [114]), .Q31(\NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][115]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][115]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[115]), .Q(\s_axi_rresp[1] [115]), .Q31(\NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][116]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][116]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[116]), .Q(\s_axi_rresp[1] [116]), .Q31(\NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][117]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][117]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[117]), .Q(\s_axi_rresp[1] [117]), .Q31(\NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][118]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][118]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[118]), .Q(\s_axi_rresp[1] [118]), .Q31(\NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][119]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][119]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[119]), .Q(\s_axi_rresp[1] [119]), .Q31(\NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][11]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[11]), .Q(\s_axi_rresp[1] [11]), .Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][120]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][120]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[120]), .Q(\s_axi_rresp[1] [120]), .Q31(\NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][121]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][121]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[121]), .Q(\s_axi_rresp[1] [121]), .Q31(\NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][122]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][122]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[122]), .Q(\s_axi_rresp[1] [122]), .Q31(\NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][123]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][123]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[123]), .Q(\s_axi_rresp[1] [123]), .Q31(\NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][124]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][124]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[124]), .Q(\s_axi_rresp[1] [124]), .Q31(\NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][125]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][125]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[125]), .Q(\s_axi_rresp[1] [125]), .Q31(\NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][126]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][126]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[126]), .Q(\s_axi_rresp[1] [126]), .Q31(\NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][127]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][127]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[127]), .Q(\s_axi_rresp[1] [127]), .Q31(\NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][128]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][128]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[128]), .Q(\s_axi_rresp[1] [128]), .Q31(\NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][129]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][129]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[129]), .Q(\s_axi_rresp[1] [129]), .Q31(\NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][12]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[12]), .Q(\s_axi_rresp[1] [12]), .Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][130]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][130]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[130]), .Q(\s_axi_rresp[1] [130]), .Q31(\NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][131]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][131]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[131]), .Q(\s_axi_rresp[1] [131]), .Q31(\NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][132]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][132]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[132]), .Q(\s_axi_rresp[1] [132]), .Q31(\NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][133]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][133]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[133]), .Q(\s_axi_rresp[1] [133]), .Q31(\NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][134]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][134]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[134]), .Q(\s_axi_rresp[1] [134]), .Q31(\NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][135]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][135]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[135]), .Q(\s_axi_rresp[1] [135]), .Q31(\NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][136]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][136]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[136]), .Q(\s_axi_rresp[1] [136]), .Q31(\NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][137]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][137]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[137]), .Q(\s_axi_rresp[1] [137]), .Q31(\NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][138]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][138]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[138]), .Q(\s_axi_rresp[1] [138]), .Q31(\NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][139]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][139]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[139]), .Q(\s_axi_rresp[1] [139]), .Q31(\NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][13]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[13]), .Q(\s_axi_rresp[1] [13]), .Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][140]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][140]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[140]), .Q(\s_axi_rresp[1] [140]), .Q31(\NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][141]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][141]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[141]), .Q(\s_axi_rresp[1] [141]), .Q31(\NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][142]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][142]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[142]), .Q(\s_axi_rresp[1] [142]), .Q31(\NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][143]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][143]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[143]), .Q(\s_axi_rresp[1] [143]), .Q31(\NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][144]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][144]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[144]), .Q(\s_axi_rresp[1] [144]), .Q31(\NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][145]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][145]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[145]), .Q(\s_axi_rresp[1] [145]), .Q31(\NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][146]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][146]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[146]), .Q(\s_axi_rresp[1] [146]), .Q31(\NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][147]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][147]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[147]), .Q(\s_axi_rresp[1] [147]), .Q31(\NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][148]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][148]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[148]), .Q(\s_axi_rresp[1] [148]), .Q31(\NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][149]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][149]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[149]), .Q(\s_axi_rresp[1] [149]), .Q31(\NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][14]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[14]), .Q(\s_axi_rresp[1] [14]), .Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][150]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][150]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[150]), .Q(\s_axi_rresp[1] [150]), .Q31(\NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][151]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][151]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[151]), .Q(\s_axi_rresp[1] [151]), .Q31(\NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][152]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][152]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[152]), .Q(\s_axi_rresp[1] [152]), .Q31(\NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][153]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][153]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[153]), .Q(\s_axi_rresp[1] [153]), .Q31(\NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][154]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][154]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[154]), .Q(\s_axi_rresp[1] [154]), .Q31(\NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][155]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][155]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[155]), .Q(\s_axi_rresp[1] [155]), .Q31(\NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][156]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][156]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[156]), .Q(\s_axi_rresp[1] [156]), .Q31(\NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][157]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][157]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[157]), .Q(\s_axi_rresp[1] [157]), .Q31(\NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][158]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][158]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[158]), .Q(\s_axi_rresp[1] [158]), .Q31(\NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][159]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][159]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[159]), .Q(\s_axi_rresp[1] [159]), .Q31(\NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][15]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[15]), .Q(\s_axi_rresp[1] [15]), .Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][160]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][160]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[160]), .Q(\s_axi_rresp[1] [160]), .Q31(\NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][161]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][161]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[161]), .Q(\s_axi_rresp[1] [161]), .Q31(\NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][162]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][162]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[162]), .Q(\s_axi_rresp[1] [162]), .Q31(\NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][163]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][163]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[163]), .Q(\s_axi_rresp[1] [163]), .Q31(\NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][164]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][164]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[164]), .Q(\s_axi_rresp[1] [164]), .Q31(\NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][165]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][165]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[165]), .Q(\s_axi_rresp[1] [165]), .Q31(\NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][166]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][166]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[166]), .Q(\s_axi_rresp[1] [166]), .Q31(\NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][167]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][167]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[167]), .Q(\s_axi_rresp[1] [167]), .Q31(\NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][168]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][168]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[168]), .Q(\s_axi_rresp[1] [168]), .Q31(\NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][169]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][169]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[169]), .Q(\s_axi_rresp[1] [169]), .Q31(\NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][16]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[16]), .Q(\s_axi_rresp[1] [16]), .Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][170]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][170]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[170]), .Q(\s_axi_rresp[1] [170]), .Q31(\NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][171]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][171]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[171]), .Q(\s_axi_rresp[1] [171]), .Q31(\NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][172]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][172]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[172]), .Q(\s_axi_rresp[1] [172]), .Q31(\NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][173]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][173]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[173]), .Q(\s_axi_rresp[1] [173]), .Q31(\NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][174]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][174]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[174]), .Q(\s_axi_rresp[1] [174]), .Q31(\NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][175]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][175]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[175]), .Q(\s_axi_rresp[1] [175]), .Q31(\NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][176]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][176]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[176]), .Q(\s_axi_rresp[1] [176]), .Q31(\NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][177]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][177]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[177]), .Q(\s_axi_rresp[1] [177]), .Q31(\NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][178]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][178]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[178]), .Q(\s_axi_rresp[1] [178]), .Q31(\NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][179]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][179]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[179]), .Q(\s_axi_rresp[1] [179]), .Q31(\NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][17]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[17]), .Q(\s_axi_rresp[1] [17]), .Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][180]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][180]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[180]), .Q(\s_axi_rresp[1] [180]), .Q31(\NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][181]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][181]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[181]), .Q(\s_axi_rresp[1] [181]), .Q31(\NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][182]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][182]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[182]), .Q(\s_axi_rresp[1] [182]), .Q31(\NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][183]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][183]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[183]), .Q(\s_axi_rresp[1] [183]), .Q31(\NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][184]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][184]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[184]), .Q(\s_axi_rresp[1] [184]), .Q31(\NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][185]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][185]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[185]), .Q(\s_axi_rresp[1] [185]), .Q31(\NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][186]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][186]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[186]), .Q(\s_axi_rresp[1] [186]), .Q31(\NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][187]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][187]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[187]), .Q(\s_axi_rresp[1] [187]), .Q31(\NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][188]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][188]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[188]), .Q(\s_axi_rresp[1] [188]), .Q31(\NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][189]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][189]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[189]), .Q(\s_axi_rresp[1] [189]), .Q31(\NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][18]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[18]), .Q(\s_axi_rresp[1] [18]), .Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][190]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][190]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[190]), .Q(\s_axi_rresp[1] [190]), .Q31(\NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][191]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][191]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[191]), .Q(\s_axi_rresp[1] [191]), .Q31(\NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][192]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][192]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[192]), .Q(\s_axi_rresp[1] [192]), .Q31(\NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][193]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][193]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[193]), .Q(\s_axi_rresp[1] [193]), .Q31(\NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][194]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][194]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[194]), .Q(\s_axi_rresp[1] [194]), .Q31(\NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][195]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][195]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[195]), .Q(\s_axi_rresp[1] [195]), .Q31(\NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][196]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][196]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[196]), .Q(\s_axi_rresp[1] [196]), .Q31(\NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][197]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][197]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[197]), .Q(\s_axi_rresp[1] [197]), .Q31(\NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][198]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][198]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[198]), .Q(\s_axi_rresp[1] [198]), .Q31(\NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][199]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][199]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[199]), .Q(\s_axi_rresp[1] [199]), .Q31(\NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][19]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[19]), .Q(\s_axi_rresp[1] [19]), .Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][1]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[1]), .Q(\s_axi_rresp[1] [1]), .Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][200]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][200]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[200]), .Q(\s_axi_rresp[1] [200]), .Q31(\NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][201]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][201]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[201]), .Q(\s_axi_rresp[1] [201]), .Q31(\NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][202]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][202]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[202]), .Q(\s_axi_rresp[1] [202]), .Q31(\NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][203]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][203]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[203]), .Q(\s_axi_rresp[1] [203]), .Q31(\NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][204]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][204]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[204]), .Q(\s_axi_rresp[1] [204]), .Q31(\NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][205]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][205]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[205]), .Q(\s_axi_rresp[1] [205]), .Q31(\NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][206]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][206]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[206]), .Q(\s_axi_rresp[1] [206]), .Q31(\NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][207]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][207]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[207]), .Q(\s_axi_rresp[1] [207]), .Q31(\NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][208]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][208]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[208]), .Q(\s_axi_rresp[1] [208]), .Q31(\NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][209]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][209]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[209]), .Q(\s_axi_rresp[1] [209]), .Q31(\NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][20]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[20]), .Q(\s_axi_rresp[1] [20]), .Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][210]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][210]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[210]), .Q(\s_axi_rresp[1] [210]), .Q31(\NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][211]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][211]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[211]), .Q(\s_axi_rresp[1] [211]), .Q31(\NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][212]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][212]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[212]), .Q(\s_axi_rresp[1] [212]), .Q31(\NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][213]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][213]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[213]), .Q(\s_axi_rresp[1] [213]), .Q31(\NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][214]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][214]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[214]), .Q(\s_axi_rresp[1] [214]), .Q31(\NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][215]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][215]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[215]), .Q(\s_axi_rresp[1] [215]), .Q31(\NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][216]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][216]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[216]), .Q(\s_axi_rresp[1] [216]), .Q31(\NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][217]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][217]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[217]), .Q(\s_axi_rresp[1] [217]), .Q31(\NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][218]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][218]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[218]), .Q(\s_axi_rresp[1] [218]), .Q31(\NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][219]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][219]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[219]), .Q(\s_axi_rresp[1] [219]), .Q31(\NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][21]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[21]), .Q(\s_axi_rresp[1] [21]), .Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][220]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][220]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[220]), .Q(\s_axi_rresp[1] [220]), .Q31(\NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][221]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][221]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[221]), .Q(\s_axi_rresp[1] [221]), .Q31(\NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][222]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][222]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[222]), .Q(\s_axi_rresp[1] [222]), .Q31(\NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][223]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][223]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[223]), .Q(\s_axi_rresp[1] [223]), .Q31(\NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][224]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][224]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[224]), .Q(\s_axi_rresp[1] [224]), .Q31(\NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][225]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][225]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[225]), .Q(\s_axi_rresp[1] [225]), .Q31(\NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][226]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][226]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[226]), .Q(\s_axi_rresp[1] [226]), .Q31(\NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][227]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][227]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[227]), .Q(\s_axi_rresp[1] [227]), .Q31(\NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][228]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][228]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[228]), .Q(\s_axi_rresp[1] [228]), .Q31(\NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][229]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][229]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[229]), .Q(\s_axi_rresp[1] [229]), .Q31(\NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][22]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[22]), .Q(\s_axi_rresp[1] [22]), .Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][230]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][230]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[230]), .Q(\s_axi_rresp[1] [230]), .Q31(\NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][231]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][231]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[231]), .Q(\s_axi_rresp[1] [231]), .Q31(\NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][232]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][232]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[232]), .Q(\s_axi_rresp[1] [232]), .Q31(\NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][233]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][233]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[233]), .Q(\s_axi_rresp[1] [233]), .Q31(\NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][234]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][234]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[234]), .Q(\s_axi_rresp[1] [234]), .Q31(\NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][235]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][235]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[235]), .Q(\s_axi_rresp[1] [235]), .Q31(\NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][236]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][236]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[236]), .Q(\s_axi_rresp[1] [236]), .Q31(\NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][237]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][237]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[237]), .Q(\s_axi_rresp[1] [237]), .Q31(\NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][238]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][238]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[238]), .Q(\s_axi_rresp[1] [238]), .Q31(\NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][239]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][239]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[239]), .Q(\s_axi_rresp[1] [239]), .Q31(\NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][23]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[23]), .Q(\s_axi_rresp[1] [23]), .Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][240]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][240]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[240]), .Q(\s_axi_rresp[1] [240]), .Q31(\NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][241]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][241]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[241]), .Q(\s_axi_rresp[1] [241]), .Q31(\NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][242]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][242]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[242]), .Q(\s_axi_rresp[1] [242]), .Q31(\NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][243]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][243]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[243]), .Q(\s_axi_rresp[1] [243]), .Q31(\NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][244]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][244]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[244]), .Q(\s_axi_rresp[1] [244]), .Q31(\NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][245]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][245]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[245]), .Q(\s_axi_rresp[1] [245]), .Q31(\NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][246]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][246]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[246]), .Q(\s_axi_rresp[1] [246]), .Q31(\NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][247]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][247]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[247]), .Q(\s_axi_rresp[1] [247]), .Q31(\NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][248]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][248]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[248]), .Q(\s_axi_rresp[1] [248]), .Q31(\NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][249]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][249]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[249]), .Q(\s_axi_rresp[1] [249]), .Q31(\NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][24]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[24]), .Q(\s_axi_rresp[1] [24]), .Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][250]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][250]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[250]), .Q(\s_axi_rresp[1] [250]), .Q31(\NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][251]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][251]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[251]), .Q(\s_axi_rresp[1] [251]), .Q31(\NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][252]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][252]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[252]), .Q(\s_axi_rresp[1] [252]), .Q31(\NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][253]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][253]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[253]), .Q(\s_axi_rresp[1] [253]), .Q31(\NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][254]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][254]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[254]), .Q(\s_axi_rresp[1] [254]), .Q31(\NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][255]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][255]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[255]), .Q(\s_axi_rresp[1] [255]), .Q31(\NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][256]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][256]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(1'b0), .Q(\s_axi_rresp[1] [256]), .Q31(\NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][25]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[25]), .Q(\s_axi_rresp[1] [25]), .Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][26]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[26]), .Q(\s_axi_rresp[1] [26]), .Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][27]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[27]), .Q(\s_axi_rresp[1] [27]), .Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][28]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[28]), .Q(\s_axi_rresp[1] [28]), .Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][29]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[29]), .Q(\s_axi_rresp[1] [29]), .Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][2]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[2]), .Q(\s_axi_rresp[1] [2]), .Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][30]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[30]), .Q(\s_axi_rresp[1] [30]), .Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][31]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[31]), .Q(\s_axi_rresp[1] [31]), .Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][32]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[32]), .Q(\s_axi_rresp[1] [32]), .Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][33]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[33]), .Q(\s_axi_rresp[1] [33]), .Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][34]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][34]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[34]), .Q(\s_axi_rresp[1] [34]), .Q31(\NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][35]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][35]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[35]), .Q(\s_axi_rresp[1] [35]), .Q31(\NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][36]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][36]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[36]), .Q(\s_axi_rresp[1] [36]), .Q31(\NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][37]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][37]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[37]), .Q(\s_axi_rresp[1] [37]), .Q31(\NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][38]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][38]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[38]), .Q(\s_axi_rresp[1] [38]), .Q31(\NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][39]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][39]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[39]), .Q(\s_axi_rresp[1] [39]), .Q31(\NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][3]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[3]), .Q(\s_axi_rresp[1] [3]), .Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][40]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][40]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[40]), .Q(\s_axi_rresp[1] [40]), .Q31(\NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][41]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][41]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[41]), .Q(\s_axi_rresp[1] [41]), .Q31(\NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][42]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][42]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[42]), .Q(\s_axi_rresp[1] [42]), .Q31(\NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][43]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][43]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[43]), .Q(\s_axi_rresp[1] [43]), .Q31(\NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][44]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][44]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[44]), .Q(\s_axi_rresp[1] [44]), .Q31(\NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][45]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][45]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[45]), .Q(\s_axi_rresp[1] [45]), .Q31(\NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][46]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][46]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[46]), .Q(\s_axi_rresp[1] [46]), .Q31(\NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][47]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][47]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[47]), .Q(\s_axi_rresp[1] [47]), .Q31(\NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][48]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][48]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[48]), .Q(\s_axi_rresp[1] [48]), .Q31(\NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][49]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][49]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[49]), .Q(\s_axi_rresp[1] [49]), .Q31(\NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][4]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[4]), .Q(\s_axi_rresp[1] [4]), .Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][50]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][50]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[50]), .Q(\s_axi_rresp[1] [50]), .Q31(\NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][51]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][51]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[51]), .Q(\s_axi_rresp[1] [51]), .Q31(\NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][52]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][52]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[52]), .Q(\s_axi_rresp[1] [52]), .Q31(\NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][53]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][53]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[53]), .Q(\s_axi_rresp[1] [53]), .Q31(\NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][54]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][54]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[54]), .Q(\s_axi_rresp[1] [54]), .Q31(\NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][55]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][55]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[55]), .Q(\s_axi_rresp[1] [55]), .Q31(\NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][56]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][56]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[56]), .Q(\s_axi_rresp[1] [56]), .Q31(\NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][57]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][57]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[57]), .Q(\s_axi_rresp[1] [57]), .Q31(\NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][58]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][58]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[58]), .Q(\s_axi_rresp[1] [58]), .Q31(\NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][59]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][59]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[59]), .Q(\s_axi_rresp[1] [59]), .Q31(\NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][5]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[5]), .Q(\s_axi_rresp[1] [5]), .Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][60]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][60]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[60]), .Q(\s_axi_rresp[1] [60]), .Q31(\NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][61]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][61]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[61]), .Q(\s_axi_rresp[1] [61]), .Q31(\NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][62]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][62]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[62]), .Q(\s_axi_rresp[1] [62]), .Q31(\NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][63]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][63]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[63]), .Q(\s_axi_rresp[1] [63]), .Q31(\NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][64]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][64]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[64]), .Q(\s_axi_rresp[1] [64]), .Q31(\NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][65]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][65]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[65]), .Q(\s_axi_rresp[1] [65]), .Q31(\NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][66]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][66]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[66]), .Q(\s_axi_rresp[1] [66]), .Q31(\NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][67]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][67]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[67]), .Q(\s_axi_rresp[1] [67]), .Q31(\NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][68]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][68]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[68]), .Q(\s_axi_rresp[1] [68]), .Q31(\NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][69]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][69]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[69]), .Q(\s_axi_rresp[1] [69]), .Q31(\NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][6]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[6]), .Q(\s_axi_rresp[1] [6]), .Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][70]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][70]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[70]), .Q(\s_axi_rresp[1] [70]), .Q31(\NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][71]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][71]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[71]), .Q(\s_axi_rresp[1] [71]), .Q31(\NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][72]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][72]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[72]), .Q(\s_axi_rresp[1] [72]), .Q31(\NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][73]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][73]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[73]), .Q(\s_axi_rresp[1] [73]), .Q31(\NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][74]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][74]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[74]), .Q(\s_axi_rresp[1] [74]), .Q31(\NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][75]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][75]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[75]), .Q(\s_axi_rresp[1] [75]), .Q31(\NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][76]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][76]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[76]), .Q(\s_axi_rresp[1] [76]), .Q31(\NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][77]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][77]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[77]), .Q(\s_axi_rresp[1] [77]), .Q31(\NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][78]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][78]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[78]), .Q(\s_axi_rresp[1] [78]), .Q31(\NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][79]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][79]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[79]), .Q(\s_axi_rresp[1] [79]), .Q31(\NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][7]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[7]), .Q(\s_axi_rresp[1] [7]), .Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][80]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][80]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[80]), .Q(\s_axi_rresp[1] [80]), .Q31(\NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][81]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][81]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[81]), .Q(\s_axi_rresp[1] [81]), .Q31(\NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][82]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][82]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[82]), .Q(\s_axi_rresp[1] [82]), .Q31(\NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][83]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][83]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[83]), .Q(\s_axi_rresp[1] [83]), .Q31(\NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][84]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][84]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[84]), .Q(\s_axi_rresp[1] [84]), .Q31(\NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][85]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[85]), .Q(\s_axi_rresp[1] [85]), .Q31(\NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][86]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][86]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[86]), .Q(\s_axi_rresp[1] [86]), .Q31(\NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][87]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][87]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[87]), .Q(\s_axi_rresp[1] [87]), .Q31(\NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][88]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][88]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[88]), .Q(\s_axi_rresp[1] [88]), .Q31(\NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][89]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][89]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[89]), .Q(\s_axi_rresp[1] [89]), .Q31(\NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][8]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[8]), .Q(\s_axi_rresp[1] [8]), .Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][90]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][90]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[90]), .Q(\s_axi_rresp[1] [90]), .Q31(\NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][91]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][91]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[91]), .Q(\s_axi_rresp[1] [91]), .Q31(\NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][92]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][92]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[92]), .Q(\s_axi_rresp[1] [92]), .Q31(\NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][93]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][93]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[93]), .Q(\s_axi_rresp[1] [93]), .Q31(\NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][94]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][94]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[94]), .Q(\s_axi_rresp[1] [94]), .Q31(\NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][95]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][95]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[95]), .Q(\s_axi_rresp[1] [95]), .Q31(\NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][96]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][96]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[96]), .Q(\s_axi_rresp[1] [96]), .Q31(\NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][97]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][97]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[97]), .Q(\s_axi_rresp[1] [97]), .Q31(\NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][98]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][98]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[98]), .Q(\s_axi_rresp[1] [98]), .Q31(\NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][99]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][99]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[99]), .Q(\s_axi_rresp[1] [99]), .Q31(\NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[31][9]_srl32 (.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }), .CE(app_rd_data_valid), .CLK(CLK), .D(Q[9]), .Q(\s_axi_rresp[1] [9]), .Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED )); LUT6 #( .INIT(64'h00B8000000B800B8)) r_push_i_2 (.I0(s_axi_arvalid), .I1(s_axi_arready), .I2(axvalid), .I3(\cnt_read_reg[5]_0 ), .I4(cnt_read_reg__0), .I5(r_push_i_4_n_0), .O(rd_cmd_en)); (* SOFT_HLUTNM = "soft_lutpair1192" *) LUT4 #( .INIT(16'h8000)) r_push_i_4 (.I0(cnt_read_reg__1[2]), .I1(cnt_read_reg__1[1]), .I2(cnt_read_reg__1[4]), .I3(cnt_read_reg__1[3]), .O(r_push_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair1194" *) LUT2 #( .INIT(4'h2)) s_axi_rvalid_INST_0 (.I0(rvalid04_in), .I1(\trans_buf_out_r_reg[0] ), .O(s_axi_rvalid)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) s_axi_rvalid_INST_0_i_1 (.I0(cnt_read_reg__1[2]), .I1(cnt_read_reg__1[1]), .I2(cnt_read_reg__1[4]), .I3(cnt_read_reg__1[3]), .I4(cnt_read_reg__0), .I5(cnt_read_reg__1[0]), .O(rvalid04_in)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_fifo" *) module ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized1 (E, tr_empty, \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] , \trans_buf_out_r_reg[0] , \trans_buf_out_r1_reg[3] , \trans_buf_out_r_reg[2] , \trans_buf_out_r_reg[3] , out, p_0_in, r_push, Q, \trans_buf_out_r_reg[0]_0 , assert_rlast, s_axi_rid, CLK, in, areset_d1); output [0:0]E; output tr_empty; output \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ; output \trans_buf_out_r_reg[0] ; output [2:0]\trans_buf_out_r1_reg[3] ; output \trans_buf_out_r_reg[2] ; output \trans_buf_out_r_reg[3] ; input [1:0]out; input p_0_in; input r_push; input [2:0]Q; input \trans_buf_out_r_reg[0]_0 ; input assert_rlast; input [0:0]s_axi_rid; input CLK; input [1:0]in; input areset_d1; wire CLK; wire [0:0]E; wire [2:0]Q; wire \RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ; wire areset_d1; wire assert_rlast; wire \cnt_read[0]_i_1__0_n_0 ; wire \cnt_read[1]_i_1__1_n_0 ; wire \cnt_read[2]_i_1_n_0 ; wire \cnt_read[3]_i_1_n_0 ; wire \cnt_read[4]_i_1_n_0 ; wire \cnt_read[5]_i_1__0_n_0 ; wire \cnt_read[5]_i_2_n_0 ; wire \cnt_read[5]_i_3__0_n_0 ; wire [4:0]cnt_read_reg__0; wire [5:5]cnt_read_reg__0__0; wire [1:0]in; wire load_stage1; wire [1:0]out; wire p_0_in; wire r_push; wire [0:0]s_axi_rid; wire tr_empty; wire [2:0]\trans_buf_out_r1_reg[3] ; wire \trans_buf_out_r_reg[0] ; wire \trans_buf_out_r_reg[0]_0 ; wire \trans_buf_out_r_reg[2] ; wire \trans_buf_out_r_reg[3] ; wire \NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED ; wire \NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED ; wire \NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED ; LUT6 #( .INIT(64'h8000000000000000)) \FSM_sequential_state[1]_i_3 (.I0(cnt_read_reg__0[0]), .I1(cnt_read_reg__0[1]), .I2(cnt_read_reg__0__0), .I3(cnt_read_reg__0[2]), .I4(cnt_read_reg__0[3]), .I5(cnt_read_reg__0[4]), .O(tr_empty)); LUT1 #( .INIT(2'h1)) \cnt_read[0]_i_1__0 (.I0(cnt_read_reg__0[0]), .O(\cnt_read[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1195" *) LUT5 #( .INIT(32'h56AAA955)) \cnt_read[1]_i_1__1 (.I0(cnt_read_reg__0[0]), .I1(tr_empty), .I2(out[1]), .I3(r_push), .I4(cnt_read_reg__0[1]), .O(\cnt_read[1]_i_1__1_n_0 )); LUT3 #( .INIT(8'h69)) \cnt_read[2]_i_1 (.I0(\cnt_read[5]_i_3__0_n_0 ), .I1(cnt_read_reg__0[2]), .I2(cnt_read_reg__0[1]), .O(\cnt_read[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1196" *) LUT4 #( .INIT(16'h78E1)) \cnt_read[3]_i_1 (.I0(cnt_read_reg__0[1]), .I1(\cnt_read[5]_i_3__0_n_0 ), .I2(cnt_read_reg__0[3]), .I3(cnt_read_reg__0[2]), .O(\cnt_read[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1196" *) LUT5 #( .INIT(32'h7F80FE01)) \cnt_read[4]_i_1 (.I0(cnt_read_reg__0[1]), .I1(\cnt_read[5]_i_3__0_n_0 ), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[4]), .I4(cnt_read_reg__0[3]), .O(\cnt_read[4]_i_1_n_0 )); LUT3 #( .INIT(8'hE1)) \cnt_read[5]_i_1__0 (.I0(tr_empty), .I1(out[1]), .I2(r_push), .O(\cnt_read[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \cnt_read[5]_i_2 (.I0(cnt_read_reg__0[1]), .I1(\cnt_read[5]_i_3__0_n_0 ), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[3]), .I4(cnt_read_reg__0__0), .I5(cnt_read_reg__0[4]), .O(\cnt_read[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1195" *) LUT5 #( .INIT(32'hA800FEAA)) \cnt_read[5]_i_3__0 (.I0(cnt_read_reg__0[0]), .I1(tr_empty), .I2(out[1]), .I3(r_push), .I4(cnt_read_reg__0[1]), .O(\cnt_read[5]_i_3__0_n_0 )); FDSE \cnt_read_reg[0] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[0]_i_1__0_n_0 ), .Q(cnt_read_reg__0[0]), .S(areset_d1)); FDSE \cnt_read_reg[1] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[1]_i_1__1_n_0 ), .Q(cnt_read_reg__0[1]), .S(areset_d1)); FDSE \cnt_read_reg[2] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[2]_i_1_n_0 ), .Q(cnt_read_reg__0[2]), .S(areset_d1)); FDSE \cnt_read_reg[3] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[3]_i_1_n_0 ), .Q(cnt_read_reg__0[3]), .S(areset_d1)); FDSE \cnt_read_reg[4] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[4]_i_1_n_0 ), .Q(cnt_read_reg__0[4]), .S(areset_d1)); FDSE \cnt_read_reg[5] (.C(CLK), .CE(\cnt_read[5]_i_1__0_n_0 ), .D(\cnt_read[5]_i_2_n_0 ), .Q(cnt_read_reg__0__0), .S(areset_d1)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][0]_srl30 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[29][0]_srl30 (.A(cnt_read_reg__0), .CE(r_push), .CLK(CLK), .D(1'b0), .Q(\trans_buf_out_r1_reg[3] [0]), .Q31(\NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][2]_srl30 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[29][2]_srl30 (.A(cnt_read_reg__0), .CE(r_push), .CLK(CLK), .D(in[0]), .Q(\trans_buf_out_r1_reg[3] [1]), .Q31(\NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][3]_srl30 " *) SRLC32E #( .INIT(32'h00000000)) \memory_reg[29][3]_srl30 (.A(cnt_read_reg__0), .CE(r_push), .CLK(CLK), .D(in[1]), .Q(\trans_buf_out_r1_reg[3] [2]), .Q31(\NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED )); LUT5 #( .INIT(32'h10000000)) r_push_i_3 (.I0(cnt_read_reg__0__0), .I1(cnt_read_reg__0[1]), .I2(cnt_read_reg__0[2]), .I3(cnt_read_reg__0[3]), .I4(cnt_read_reg__0[4]), .O(\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair1197" *) LUT2 #( .INIT(4'h1)) \trans_buf_out_r1[3]_i_1 (.I0(out[1]), .I1(tr_empty), .O(E)); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \trans_buf_out_r[0]_i_1 (.I0(Q[0]), .I1(out[1]), .I2(out[0]), .I3(\trans_buf_out_r1_reg[3] [0]), .I4(load_stage1), .I5(\trans_buf_out_r_reg[0]_0 ), .O(\trans_buf_out_r_reg[0] )); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \trans_buf_out_r[2]_i_1 (.I0(Q[1]), .I1(out[1]), .I2(out[0]), .I3(\trans_buf_out_r1_reg[3] [1]), .I4(load_stage1), .I5(assert_rlast), .O(\trans_buf_out_r_reg[2] )); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \trans_buf_out_r[3]_i_1 (.I0(Q[2]), .I1(out[1]), .I2(out[0]), .I3(\trans_buf_out_r1_reg[3] [2]), .I4(load_stage1), .I5(s_axi_rid), .O(\trans_buf_out_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair1197" *) LUT4 #( .INIT(16'h1D01)) \trans_buf_out_r[3]_i_2 (.I0(tr_empty), .I1(out[1]), .I2(out[0]), .I3(p_0_in), .O(load_stage1)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd (out, Q, \app_addr_r1_reg[27] , in0, axready_reg, S, axready_reg_0, areset_d1, E, D, CLK, axready_reg_1); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; input [3:0]in0; input [24:0]axready_reg; input [0:0]S; input [0:0]axready_reg_0; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_1; wire CLK; wire [7:0]D; wire [0:0]E; wire [7:0]Q; wire [0:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire areset_d1; (* RTL_KEEP = "true" *) wire [29:0]axaddr_incr_p; wire axaddr_incr_p_reg0_carry__0_n_0; wire axaddr_incr_p_reg0_carry__0_n_1; wire axaddr_incr_p_reg0_carry__0_n_2; wire axaddr_incr_p_reg0_carry__0_n_3; wire axaddr_incr_p_reg0_carry__1_n_0; wire axaddr_incr_p_reg0_carry__1_n_1; wire axaddr_incr_p_reg0_carry__1_n_2; wire axaddr_incr_p_reg0_carry__1_n_3; wire axaddr_incr_p_reg0_carry__2_n_0; wire axaddr_incr_p_reg0_carry__2_n_1; wire axaddr_incr_p_reg0_carry__2_n_2; wire axaddr_incr_p_reg0_carry__2_n_3; wire axaddr_incr_p_reg0_carry__3_n_0; wire axaddr_incr_p_reg0_carry__3_n_1; wire axaddr_incr_p_reg0_carry__3_n_2; wire axaddr_incr_p_reg0_carry__3_n_3; wire axaddr_incr_p_reg0_carry__4_n_0; wire axaddr_incr_p_reg0_carry__4_n_1; wire axaddr_incr_p_reg0_carry__4_n_2; wire axaddr_incr_p_reg0_carry__4_n_3; wire axaddr_incr_p_reg0_carry__5_n_3; wire axaddr_incr_p_reg0_carry_n_0; wire axaddr_incr_p_reg0_carry_n_1; wire axaddr_incr_p_reg0_carry_n_2; wire axaddr_incr_p_reg0_carry_n_3; wire [24:0]axready_reg; wire [0:0]axready_reg_0; wire [29:0]axready_reg_1; wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED; wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED; assign axaddr_incr_p[3:0] = in0[3:0]; assign out[29:0] = axaddr_incr_p; CARRY4 axaddr_incr_p_reg0_carry (.CI(1'b0), .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,axready_reg[1],1'b0}), .O(axaddr_incr_p[7:4]), .S({axready_reg[3:2],S,axready_reg[0]})); CARRY4 axaddr_incr_p_reg0_carry__0 (.CI(axaddr_incr_p_reg0_carry_n_0), .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[11:8]), .S({axready_reg[6:4],axready_reg_0})); CARRY4 axaddr_incr_p_reg0_carry__1 (.CI(axaddr_incr_p_reg0_carry__0_n_0), .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[15:12]), .S(axready_reg[10:7])); CARRY4 axaddr_incr_p_reg0_carry__2 (.CI(axaddr_incr_p_reg0_carry__1_n_0), .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[19:16]), .S(axready_reg[14:11])); CARRY4 axaddr_incr_p_reg0_carry__3 (.CI(axaddr_incr_p_reg0_carry__2_n_0), .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[23:20]), .S(axready_reg[18:15])); CARRY4 axaddr_incr_p_reg0_carry__4 (.CI(axaddr_incr_p_reg0_carry__3_n_0), .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[27:24]), .S(axready_reg[22:19])); CARRY4 axaddr_incr_p_reg0_carry__5 (.CI(axaddr_incr_p_reg0_carry__4_n_0), .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}), .S({1'b0,1'b0,axready_reg[24:23]})); FDRE \axaddr_incr_reg[0] (.C(CLK), .CE(E), .D(axready_reg_1[0]), .Q(\app_addr_r1_reg[27] [0]), .R(areset_d1)); FDRE \axaddr_incr_reg[10] (.C(CLK), .CE(E), .D(axready_reg_1[10]), .Q(\app_addr_r1_reg[27] [10]), .R(areset_d1)); FDRE \axaddr_incr_reg[11] (.C(CLK), .CE(E), .D(axready_reg_1[11]), .Q(\app_addr_r1_reg[27] [11]), .R(areset_d1)); FDRE \axaddr_incr_reg[12] (.C(CLK), .CE(E), .D(axready_reg_1[12]), .Q(\app_addr_r1_reg[27] [12]), .R(areset_d1)); FDRE \axaddr_incr_reg[13] (.C(CLK), .CE(E), .D(axready_reg_1[13]), .Q(\app_addr_r1_reg[27] [13]), .R(areset_d1)); FDRE \axaddr_incr_reg[14] (.C(CLK), .CE(E), .D(axready_reg_1[14]), .Q(\app_addr_r1_reg[27] [14]), .R(areset_d1)); FDRE \axaddr_incr_reg[15] (.C(CLK), .CE(E), .D(axready_reg_1[15]), .Q(\app_addr_r1_reg[27] [15]), .R(areset_d1)); FDRE \axaddr_incr_reg[16] (.C(CLK), .CE(E), .D(axready_reg_1[16]), .Q(\app_addr_r1_reg[27] [16]), .R(areset_d1)); FDRE \axaddr_incr_reg[17] (.C(CLK), .CE(E), .D(axready_reg_1[17]), .Q(\app_addr_r1_reg[27] [17]), .R(areset_d1)); FDRE \axaddr_incr_reg[18] (.C(CLK), .CE(E), .D(axready_reg_1[18]), .Q(\app_addr_r1_reg[27] [18]), .R(areset_d1)); FDRE \axaddr_incr_reg[19] (.C(CLK), .CE(E), .D(axready_reg_1[19]), .Q(\app_addr_r1_reg[27] [19]), .R(areset_d1)); FDRE \axaddr_incr_reg[1] (.C(CLK), .CE(E), .D(axready_reg_1[1]), .Q(\app_addr_r1_reg[27] [1]), .R(areset_d1)); FDRE \axaddr_incr_reg[20] (.C(CLK), .CE(E), .D(axready_reg_1[20]), .Q(\app_addr_r1_reg[27] [20]), .R(areset_d1)); FDRE \axaddr_incr_reg[21] (.C(CLK), .CE(E), .D(axready_reg_1[21]), .Q(\app_addr_r1_reg[27] [21]), .R(areset_d1)); FDRE \axaddr_incr_reg[22] (.C(CLK), .CE(E), .D(axready_reg_1[22]), .Q(\app_addr_r1_reg[27] [22]), .R(areset_d1)); FDRE \axaddr_incr_reg[23] (.C(CLK), .CE(E), .D(axready_reg_1[23]), .Q(\app_addr_r1_reg[27] [23]), .R(areset_d1)); FDRE \axaddr_incr_reg[24] (.C(CLK), .CE(E), .D(axready_reg_1[24]), .Q(\app_addr_r1_reg[27] [24]), .R(areset_d1)); FDRE \axaddr_incr_reg[25] (.C(CLK), .CE(E), .D(axready_reg_1[25]), .Q(\app_addr_r1_reg[27] [25]), .R(areset_d1)); FDRE \axaddr_incr_reg[26] (.C(CLK), .CE(E), .D(axready_reg_1[26]), .Q(\app_addr_r1_reg[27] [26]), .R(areset_d1)); FDRE \axaddr_incr_reg[27] (.C(CLK), .CE(E), .D(axready_reg_1[27]), .Q(\app_addr_r1_reg[27] [27]), .R(areset_d1)); FDRE \axaddr_incr_reg[28] (.C(CLK), .CE(E), .D(axready_reg_1[28]), .Q(\app_addr_r1_reg[27] [28]), .R(areset_d1)); FDRE \axaddr_incr_reg[29] (.C(CLK), .CE(E), .D(axready_reg_1[29]), .Q(\app_addr_r1_reg[27] [29]), .R(areset_d1)); FDRE \axaddr_incr_reg[2] (.C(CLK), .CE(E), .D(axready_reg_1[2]), .Q(\app_addr_r1_reg[27] [2]), .R(areset_d1)); FDRE \axaddr_incr_reg[3] (.C(CLK), .CE(E), .D(axready_reg_1[3]), .Q(\app_addr_r1_reg[27] [3]), .R(areset_d1)); FDRE \axaddr_incr_reg[4] (.C(CLK), .CE(E), .D(axready_reg_1[4]), .Q(\app_addr_r1_reg[27] [4]), .R(areset_d1)); FDRE \axaddr_incr_reg[5] (.C(CLK), .CE(E), .D(axready_reg_1[5]), .Q(\app_addr_r1_reg[27] [5]), .R(areset_d1)); FDRE \axaddr_incr_reg[6] (.C(CLK), .CE(E), .D(axready_reg_1[6]), .Q(\app_addr_r1_reg[27] [6]), .R(areset_d1)); FDRE \axaddr_incr_reg[7] (.C(CLK), .CE(E), .D(axready_reg_1[7]), .Q(\app_addr_r1_reg[27] [7]), .R(areset_d1)); FDRE \axaddr_incr_reg[8] (.C(CLK), .CE(E), .D(axready_reg_1[8]), .Q(\app_addr_r1_reg[27] [8]), .R(areset_d1)); FDRE \axaddr_incr_reg[9] (.C(CLK), .CE(E), .D(axready_reg_1[9]), .Q(\app_addr_r1_reg[27] [9]), .R(areset_d1)); FDSE \axlen_cnt_reg[0] (.C(CLK), .CE(E), .D(D[0]), .Q(Q[0]), .S(areset_d1)); FDSE \axlen_cnt_reg[1] (.C(CLK), .CE(E), .D(D[1]), .Q(Q[1]), .S(areset_d1)); FDSE \axlen_cnt_reg[2] (.C(CLK), .CE(E), .D(D[2]), .Q(Q[2]), .S(areset_d1)); FDSE \axlen_cnt_reg[3] (.C(CLK), .CE(E), .D(D[3]), .Q(Q[3]), .S(areset_d1)); FDRE \axlen_cnt_reg[4] (.C(CLK), .CE(E), .D(D[4]), .Q(Q[4]), .R(areset_d1)); FDRE \axlen_cnt_reg[5] (.C(CLK), .CE(E), .D(D[5]), .Q(Q[5]), .R(areset_d1)); FDRE \axlen_cnt_reg[6] (.C(CLK), .CE(E), .D(D[6]), .Q(Q[6]), .R(areset_d1)); FDRE \axlen_cnt_reg[7] (.C(CLK), .CE(E), .D(D[7]), .Q(Q[7]), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_incr_cmd" *) module ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd__parameterized0 (out, Q, \app_addr_r1_reg[27] , in0, DI, S, axready_reg, areset_d1, E, D, CLK, axready_reg_0); output [29:0]out; output [7:0]Q; output [29:0]\app_addr_r1_reg[27] ; input [3:0]in0; input [0:0]DI; input [3:0]S; input [21:0]axready_reg; input areset_d1; input [0:0]E; input [7:0]D; input CLK; input [29:0]axready_reg_0; wire CLK; wire [7:0]D; wire [0:0]DI; wire [0:0]E; wire [7:0]Q; wire [3:0]S; wire [29:0]\app_addr_r1_reg[27] ; wire areset_d1; (* RTL_KEEP = "true" *) wire [29:0]axaddr_incr_p; wire axaddr_incr_p_reg0_carry__0_n_0; wire axaddr_incr_p_reg0_carry__0_n_1; wire axaddr_incr_p_reg0_carry__0_n_2; wire axaddr_incr_p_reg0_carry__0_n_3; wire axaddr_incr_p_reg0_carry__1_n_0; wire axaddr_incr_p_reg0_carry__1_n_1; wire axaddr_incr_p_reg0_carry__1_n_2; wire axaddr_incr_p_reg0_carry__1_n_3; wire axaddr_incr_p_reg0_carry__2_n_0; wire axaddr_incr_p_reg0_carry__2_n_1; wire axaddr_incr_p_reg0_carry__2_n_2; wire axaddr_incr_p_reg0_carry__2_n_3; wire axaddr_incr_p_reg0_carry__3_n_0; wire axaddr_incr_p_reg0_carry__3_n_1; wire axaddr_incr_p_reg0_carry__3_n_2; wire axaddr_incr_p_reg0_carry__3_n_3; wire axaddr_incr_p_reg0_carry__4_n_0; wire axaddr_incr_p_reg0_carry__4_n_1; wire axaddr_incr_p_reg0_carry__4_n_2; wire axaddr_incr_p_reg0_carry__4_n_3; wire axaddr_incr_p_reg0_carry__5_n_3; wire axaddr_incr_p_reg0_carry_n_0; wire axaddr_incr_p_reg0_carry_n_1; wire axaddr_incr_p_reg0_carry_n_2; wire axaddr_incr_p_reg0_carry_n_3; wire [21:0]axready_reg; wire [29:0]axready_reg_0; wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED; wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED; assign axaddr_incr_p[3:0] = in0[3:0]; assign out[29:0] = axaddr_incr_p; CARRY4 axaddr_incr_p_reg0_carry (.CI(1'b0), .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,DI,1'b0}), .O(axaddr_incr_p[7:4]), .S(S)); CARRY4 axaddr_incr_p_reg0_carry__0 (.CI(axaddr_incr_p_reg0_carry_n_0), .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[11:8]), .S(axready_reg[3:0])); CARRY4 axaddr_incr_p_reg0_carry__1 (.CI(axaddr_incr_p_reg0_carry__0_n_0), .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[15:12]), .S(axready_reg[7:4])); CARRY4 axaddr_incr_p_reg0_carry__2 (.CI(axaddr_incr_p_reg0_carry__1_n_0), .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[19:16]), .S(axready_reg[11:8])); CARRY4 axaddr_incr_p_reg0_carry__3 (.CI(axaddr_incr_p_reg0_carry__2_n_0), .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[23:20]), .S(axready_reg[15:12])); CARRY4 axaddr_incr_p_reg0_carry__4 (.CI(axaddr_incr_p_reg0_carry__3_n_0), .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(axaddr_incr_p[27:24]), .S(axready_reg[19:16])); CARRY4 axaddr_incr_p_reg0_carry__5 (.CI(axaddr_incr_p_reg0_carry__4_n_0), .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}), .S({1'b0,1'b0,axready_reg[21:20]})); FDRE \axaddr_incr_reg[0] (.C(CLK), .CE(E), .D(axready_reg_0[0]), .Q(\app_addr_r1_reg[27] [0]), .R(areset_d1)); FDRE \axaddr_incr_reg[10] (.C(CLK), .CE(E), .D(axready_reg_0[10]), .Q(\app_addr_r1_reg[27] [10]), .R(areset_d1)); FDRE \axaddr_incr_reg[11] (.C(CLK), .CE(E), .D(axready_reg_0[11]), .Q(\app_addr_r1_reg[27] [11]), .R(areset_d1)); FDRE \axaddr_incr_reg[12] (.C(CLK), .CE(E), .D(axready_reg_0[12]), .Q(\app_addr_r1_reg[27] [12]), .R(areset_d1)); FDRE \axaddr_incr_reg[13] (.C(CLK), .CE(E), .D(axready_reg_0[13]), .Q(\app_addr_r1_reg[27] [13]), .R(areset_d1)); FDRE \axaddr_incr_reg[14] (.C(CLK), .CE(E), .D(axready_reg_0[14]), .Q(\app_addr_r1_reg[27] [14]), .R(areset_d1)); FDRE \axaddr_incr_reg[15] (.C(CLK), .CE(E), .D(axready_reg_0[15]), .Q(\app_addr_r1_reg[27] [15]), .R(areset_d1)); FDRE \axaddr_incr_reg[16] (.C(CLK), .CE(E), .D(axready_reg_0[16]), .Q(\app_addr_r1_reg[27] [16]), .R(areset_d1)); FDRE \axaddr_incr_reg[17] (.C(CLK), .CE(E), .D(axready_reg_0[17]), .Q(\app_addr_r1_reg[27] [17]), .R(areset_d1)); FDRE \axaddr_incr_reg[18] (.C(CLK), .CE(E), .D(axready_reg_0[18]), .Q(\app_addr_r1_reg[27] [18]), .R(areset_d1)); FDRE \axaddr_incr_reg[19] (.C(CLK), .CE(E), .D(axready_reg_0[19]), .Q(\app_addr_r1_reg[27] [19]), .R(areset_d1)); FDRE \axaddr_incr_reg[1] (.C(CLK), .CE(E), .D(axready_reg_0[1]), .Q(\app_addr_r1_reg[27] [1]), .R(areset_d1)); FDRE \axaddr_incr_reg[20] (.C(CLK), .CE(E), .D(axready_reg_0[20]), .Q(\app_addr_r1_reg[27] [20]), .R(areset_d1)); FDRE \axaddr_incr_reg[21] (.C(CLK), .CE(E), .D(axready_reg_0[21]), .Q(\app_addr_r1_reg[27] [21]), .R(areset_d1)); FDRE \axaddr_incr_reg[22] (.C(CLK), .CE(E), .D(axready_reg_0[22]), .Q(\app_addr_r1_reg[27] [22]), .R(areset_d1)); FDRE \axaddr_incr_reg[23] (.C(CLK), .CE(E), .D(axready_reg_0[23]), .Q(\app_addr_r1_reg[27] [23]), .R(areset_d1)); FDRE \axaddr_incr_reg[24] (.C(CLK), .CE(E), .D(axready_reg_0[24]), .Q(\app_addr_r1_reg[27] [24]), .R(areset_d1)); FDRE \axaddr_incr_reg[25] (.C(CLK), .CE(E), .D(axready_reg_0[25]), .Q(\app_addr_r1_reg[27] [25]), .R(areset_d1)); FDRE \axaddr_incr_reg[26] (.C(CLK), .CE(E), .D(axready_reg_0[26]), .Q(\app_addr_r1_reg[27] [26]), .R(areset_d1)); FDRE \axaddr_incr_reg[27] (.C(CLK), .CE(E), .D(axready_reg_0[27]), .Q(\app_addr_r1_reg[27] [27]), .R(areset_d1)); FDRE \axaddr_incr_reg[28] (.C(CLK), .CE(E), .D(axready_reg_0[28]), .Q(\app_addr_r1_reg[27] [28]), .R(areset_d1)); FDRE \axaddr_incr_reg[29] (.C(CLK), .CE(E), .D(axready_reg_0[29]), .Q(\app_addr_r1_reg[27] [29]), .R(areset_d1)); FDRE \axaddr_incr_reg[2] (.C(CLK), .CE(E), .D(axready_reg_0[2]), .Q(\app_addr_r1_reg[27] [2]), .R(areset_d1)); FDRE \axaddr_incr_reg[3] (.C(CLK), .CE(E), .D(axready_reg_0[3]), .Q(\app_addr_r1_reg[27] [3]), .R(areset_d1)); FDRE \axaddr_incr_reg[4] (.C(CLK), .CE(E), .D(axready_reg_0[4]), .Q(\app_addr_r1_reg[27] [4]), .R(areset_d1)); FDRE \axaddr_incr_reg[5] (.C(CLK), .CE(E), .D(axready_reg_0[5]), .Q(\app_addr_r1_reg[27] [5]), .R(areset_d1)); FDRE \axaddr_incr_reg[6] (.C(CLK), .CE(E), .D(axready_reg_0[6]), .Q(\app_addr_r1_reg[27] [6]), .R(areset_d1)); FDRE \axaddr_incr_reg[7] (.C(CLK), .CE(E), .D(axready_reg_0[7]), .Q(\app_addr_r1_reg[27] [7]), .R(areset_d1)); FDRE \axaddr_incr_reg[8] (.C(CLK), .CE(E), .D(axready_reg_0[8]), .Q(\app_addr_r1_reg[27] [8]), .R(areset_d1)); FDRE \axaddr_incr_reg[9] (.C(CLK), .CE(E), .D(axready_reg_0[9]), .Q(\app_addr_r1_reg[27] [9]), .R(areset_d1)); FDSE \axlen_cnt_reg[0] (.C(CLK), .CE(E), .D(D[0]), .Q(Q[0]), .S(areset_d1)); FDSE \axlen_cnt_reg[1] (.C(CLK), .CE(E), .D(D[1]), .Q(Q[1]), .S(areset_d1)); FDSE \axlen_cnt_reg[2] (.C(CLK), .CE(E), .D(D[2]), .Q(Q[2]), .S(areset_d1)); FDSE \axlen_cnt_reg[3] (.C(CLK), .CE(E), .D(D[3]), .Q(Q[3]), .S(areset_d1)); FDRE \axlen_cnt_reg[4] (.C(CLK), .CE(E), .D(D[4]), .Q(Q[4]), .R(areset_d1)); FDRE \axlen_cnt_reg[5] (.C(CLK), .CE(E), .D(D[5]), .Q(Q[5]), .R(areset_d1)); FDRE \axlen_cnt_reg[6] (.C(CLK), .CE(E), .D(D[6]), .Q(Q[6]), .R(areset_d1)); FDRE \axlen_cnt_reg[7] (.C(CLK), .CE(E), .D(D[7]), .Q(Q[7]), .R(areset_d1)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_r_channel (rd_cmd_en, E, s_axi_rvalid, s_axi_rlast, out, s_axi_rid, s_axi_arvalid, s_axi_arready, axvalid, app_rdy, app_rd_data_valid, s_axi_rready, r_push, Q, CLK, in, areset_d1); output rd_cmd_en; output [0:0]E; output s_axi_rvalid; output s_axi_rlast; output [256:0]out; output [0:0]s_axi_rid; input s_axi_arvalid; input s_axi_arready; input axvalid; input app_rdy; input app_rd_data_valid; input s_axi_rready; input r_push; input [255:0]Q; input CLK; input [1:0]in; input areset_d1; wire CLK; wire [0:0]E; wire [255:0]Q; wire app_rd_data_valid; wire app_rdy; wire areset_d1; wire assert_rlast; wire axvalid; wire [1:0]in; wire [256:0]out; wire p_0_in; wire r_push; wire rd_cmd_en; wire rd_data_fifo_0_n_4; wire rd_data_fifo_0_n_5; wire s_axi_arready; wire s_axi_arvalid; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; (* RTL_KEEP = "yes" *) wire [1:0]state; wire tr_empty; wire [3:0]trans_buf_out_r1; wire \trans_buf_out_r_reg_n_0_[0] ; wire [3:0]trans_out; wire transaction_fifo_0_n_0; wire transaction_fifo_0_n_2; wire transaction_fifo_0_n_3; wire transaction_fifo_0_n_7; wire transaction_fifo_0_n_8; (* KEEP = "yes" *) FDRE \FSM_sequential_state_reg[0] (.C(CLK), .CE(1'b1), .D(rd_data_fifo_0_n_5), .Q(state[0]), .R(areset_d1)); (* KEEP = "yes" *) FDRE \FSM_sequential_state_reg[1] (.C(CLK), .CE(1'b1), .D(rd_data_fifo_0_n_4), .Q(state[1]), .R(areset_d1)); ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized0 rd_data_fifo_0 (.CLK(CLK), .E(E), .\FSM_sequential_state_reg[0] (rd_data_fifo_0_n_5), .\FSM_sequential_state_reg[1] (rd_data_fifo_0_n_4), .Q(Q), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .areset_d1(areset_d1), .axvalid(axvalid), .\cnt_read_reg[5]_0 (transaction_fifo_0_n_2), .in0(state), .out(state), .p_0_in(p_0_in), .rd_cmd_en(rd_cmd_en), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_rready(s_axi_rready), .\s_axi_rresp[1] (out), .s_axi_rvalid(s_axi_rvalid), .tr_empty(tr_empty), .\trans_buf_out_r_reg[0] (\trans_buf_out_r_reg_n_0_[0] )); LUT2 #( .INIT(4'h2)) s_axi_rlast_INST_0 (.I0(assert_rlast), .I1(\trans_buf_out_r_reg_n_0_[0] ), .O(s_axi_rlast)); FDRE \trans_buf_out_r1_reg[0] (.C(CLK), .CE(transaction_fifo_0_n_0), .D(trans_out[0]), .Q(trans_buf_out_r1[0]), .R(1'b0)); FDRE \trans_buf_out_r1_reg[2] (.C(CLK), .CE(transaction_fifo_0_n_0), .D(trans_out[2]), .Q(trans_buf_out_r1[2]), .R(1'b0)); FDRE \trans_buf_out_r1_reg[3] (.C(CLK), .CE(transaction_fifo_0_n_0), .D(trans_out[3]), .Q(trans_buf_out_r1[3]), .R(1'b0)); FDRE \trans_buf_out_r_reg[0] (.C(CLK), .CE(1'b1), .D(transaction_fifo_0_n_3), .Q(\trans_buf_out_r_reg_n_0_[0] ), .R(1'b0)); FDRE \trans_buf_out_r_reg[2] (.C(CLK), .CE(1'b1), .D(transaction_fifo_0_n_7), .Q(assert_rlast), .R(1'b0)); FDRE \trans_buf_out_r_reg[3] (.C(CLK), .CE(1'b1), .D(transaction_fifo_0_n_8), .Q(s_axi_rid), .R(1'b0)); ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized1 transaction_fifo_0 (.CLK(CLK), .E(transaction_fifo_0_n_0), .Q({trans_buf_out_r1[3:2],trans_buf_out_r1[0]}), .\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] (transaction_fifo_0_n_2), .areset_d1(areset_d1), .assert_rlast(assert_rlast), .in(in), .out(state), .p_0_in(p_0_in), .r_push(r_push), .s_axi_rid(s_axi_rid), .tr_empty(tr_empty), .\trans_buf_out_r1_reg[3] ({trans_out[3:2],trans_out[0]}), .\trans_buf_out_r_reg[0] (transaction_fifo_0_n_3), .\trans_buf_out_r_reg[0]_0 (\trans_buf_out_r_reg_n_0_[0] ), .\trans_buf_out_r_reg[2] (transaction_fifo_0_n_7), .\trans_buf_out_r_reg[3] (transaction_fifo_0_n_8)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_w_channel (wvalid_int, s_axi_wready, mc_app_wdf_wren_reg, app_wdf_mask, mc_app_wdf_mask_reg, D, app_wdf_data, mc_app_wdf_data_reg, \mc_app_wdf_data_reg_reg[255]_0 , areset_d1, CLK, app_wdf_rdy, \RD_PRI_REG_STARVE.rnw_i_reg , s_axi_wvalid, s_axi_wstrb, s_axi_wdata); output wvalid_int; output s_axi_wready; output mc_app_wdf_wren_reg; output [31:0]app_wdf_mask; output [31:0]mc_app_wdf_mask_reg; output [31:0]D; output [255:0]app_wdf_data; output [255:0]mc_app_wdf_data_reg; output [255:0]\mc_app_wdf_data_reg_reg[255]_0 ; input areset_d1; input CLK; input app_wdf_rdy; input \RD_PRI_REG_STARVE.rnw_i_reg ; input s_axi_wvalid; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; wire CLK; wire [31:0]D; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire areset_d1; wire [255:0]mc_app_wdf_data_reg; wire [255:0]\mc_app_wdf_data_reg_reg[255]_0 ; wire [31:0]mc_app_wdf_mask_reg; wire mc_app_wdf_wren_reg; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire valid; wire [255:0]wdf_data; wire [31:0]wdf_mask; wire wready_i_1_n_0; wire wready_reg_rep__0_n_0; wire wready_reg_rep__1_n_0; wire wready_reg_rep__2_n_0; wire wready_reg_rep_n_0; wire wready_rep__0_i_1_n_0; wire wready_rep__1_i_1_n_0; wire wready_rep__2_i_1_n_0; wire wready_rep_i_1_n_0; wire wvalid_int; (* SOFT_HLUTNM = "soft_lutpair1485" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[0]_i_1 (.I0(s_axi_wdata[0]), .I1(s_axi_wready), .I2(wdf_data[0]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[0]), .O(app_wdf_data[0])); (* SOFT_HLUTNM = "soft_lutpair1297" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[100]_i_1 (.I0(s_axi_wdata[100]), .I1(wready_reg_rep_n_0), .I2(wdf_data[100]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[100]), .O(app_wdf_data[100])); (* SOFT_HLUTNM = "soft_lutpair1298" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[101]_i_1 (.I0(s_axi_wdata[101]), .I1(wready_reg_rep_n_0), .I2(wdf_data[101]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[101]), .O(app_wdf_data[101])); (* SOFT_HLUTNM = "soft_lutpair1299" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[102]_i_1 (.I0(s_axi_wdata[102]), .I1(wready_reg_rep_n_0), .I2(wdf_data[102]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[102]), .O(app_wdf_data[102])); (* SOFT_HLUTNM = "soft_lutpair1300" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[103]_i_1 (.I0(s_axi_wdata[103]), .I1(wready_reg_rep_n_0), .I2(wdf_data[103]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[103]), .O(app_wdf_data[103])); (* SOFT_HLUTNM = "soft_lutpair1301" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[104]_i_1 (.I0(s_axi_wdata[104]), .I1(wready_reg_rep_n_0), .I2(wdf_data[104]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[104]), .O(app_wdf_data[104])); (* SOFT_HLUTNM = "soft_lutpair1302" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[105]_i_1 (.I0(s_axi_wdata[105]), .I1(wready_reg_rep_n_0), .I2(wdf_data[105]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[105]), .O(app_wdf_data[105])); (* SOFT_HLUTNM = "soft_lutpair1303" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[106]_i_1 (.I0(s_axi_wdata[106]), .I1(wready_reg_rep_n_0), .I2(wdf_data[106]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[106]), .O(app_wdf_data[106])); (* SOFT_HLUTNM = "soft_lutpair1304" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[107]_i_1 (.I0(s_axi_wdata[107]), .I1(wready_reg_rep_n_0), .I2(wdf_data[107]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[107]), .O(app_wdf_data[107])); (* SOFT_HLUTNM = "soft_lutpair1305" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[108]_i_1 (.I0(s_axi_wdata[108]), .I1(wready_reg_rep_n_0), .I2(wdf_data[108]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[108]), .O(app_wdf_data[108])); (* SOFT_HLUTNM = "soft_lutpair1306" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[109]_i_1 (.I0(s_axi_wdata[109]), .I1(wready_reg_rep_n_0), .I2(wdf_data[109]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[109]), .O(app_wdf_data[109])); (* SOFT_HLUTNM = "soft_lutpair1207" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[10]_i_1 (.I0(s_axi_wdata[10]), .I1(s_axi_wready), .I2(wdf_data[10]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[10]), .O(app_wdf_data[10])); (* SOFT_HLUTNM = "soft_lutpair1307" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[110]_i_1 (.I0(s_axi_wdata[110]), .I1(wready_reg_rep_n_0), .I2(wdf_data[110]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[110]), .O(app_wdf_data[110])); (* SOFT_HLUTNM = "soft_lutpair1308" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[111]_i_1 (.I0(s_axi_wdata[111]), .I1(wready_reg_rep_n_0), .I2(wdf_data[111]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[111]), .O(app_wdf_data[111])); (* SOFT_HLUTNM = "soft_lutpair1309" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[112]_i_1 (.I0(s_axi_wdata[112]), .I1(wready_reg_rep_n_0), .I2(wdf_data[112]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[112]), .O(app_wdf_data[112])); (* SOFT_HLUTNM = "soft_lutpair1310" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[113]_i_1 (.I0(s_axi_wdata[113]), .I1(wready_reg_rep_n_0), .I2(wdf_data[113]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[113]), .O(app_wdf_data[113])); (* SOFT_HLUTNM = "soft_lutpair1311" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[114]_i_1 (.I0(s_axi_wdata[114]), .I1(wready_reg_rep_n_0), .I2(wdf_data[114]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[114]), .O(app_wdf_data[114])); (* SOFT_HLUTNM = "soft_lutpair1312" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[115]_i_1 (.I0(s_axi_wdata[115]), .I1(wready_reg_rep_n_0), .I2(wdf_data[115]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[115]), .O(app_wdf_data[115])); (* SOFT_HLUTNM = "soft_lutpair1313" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[116]_i_1 (.I0(s_axi_wdata[116]), .I1(wready_reg_rep_n_0), .I2(wdf_data[116]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[116]), .O(app_wdf_data[116])); (* SOFT_HLUTNM = "soft_lutpair1314" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[117]_i_1 (.I0(s_axi_wdata[117]), .I1(wready_reg_rep_n_0), .I2(wdf_data[117]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[117]), .O(app_wdf_data[117])); (* SOFT_HLUTNM = "soft_lutpair1315" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[118]_i_1 (.I0(s_axi_wdata[118]), .I1(wready_reg_rep_n_0), .I2(wdf_data[118]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[118]), .O(app_wdf_data[118])); (* SOFT_HLUTNM = "soft_lutpair1316" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[119]_i_1 (.I0(s_axi_wdata[119]), .I1(wready_reg_rep_n_0), .I2(wdf_data[119]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[119]), .O(app_wdf_data[119])); (* SOFT_HLUTNM = "soft_lutpair1208" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[11]_i_1 (.I0(s_axi_wdata[11]), .I1(s_axi_wready), .I2(wdf_data[11]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[11]), .O(app_wdf_data[11])); (* SOFT_HLUTNM = "soft_lutpair1317" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[120]_i_1 (.I0(s_axi_wdata[120]), .I1(wready_reg_rep_n_0), .I2(wdf_data[120]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[120]), .O(app_wdf_data[120])); (* SOFT_HLUTNM = "soft_lutpair1318" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[121]_i_1 (.I0(s_axi_wdata[121]), .I1(wready_reg_rep_n_0), .I2(wdf_data[121]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[121]), .O(app_wdf_data[121])); (* SOFT_HLUTNM = "soft_lutpair1319" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[122]_i_1 (.I0(s_axi_wdata[122]), .I1(wready_reg_rep_n_0), .I2(wdf_data[122]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[122]), .O(app_wdf_data[122])); (* SOFT_HLUTNM = "soft_lutpair1320" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[123]_i_1 (.I0(s_axi_wdata[123]), .I1(wready_reg_rep_n_0), .I2(wdf_data[123]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[123]), .O(app_wdf_data[123])); (* SOFT_HLUTNM = "soft_lutpair1321" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[124]_i_1 (.I0(s_axi_wdata[124]), .I1(wready_reg_rep_n_0), .I2(wdf_data[124]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[124]), .O(app_wdf_data[124])); (* SOFT_HLUTNM = "soft_lutpair1322" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[125]_i_1 (.I0(s_axi_wdata[125]), .I1(wready_reg_rep_n_0), .I2(wdf_data[125]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[125]), .O(app_wdf_data[125])); (* SOFT_HLUTNM = "soft_lutpair1323" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[126]_i_1 (.I0(s_axi_wdata[126]), .I1(wready_reg_rep_n_0), .I2(wdf_data[126]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[126]), .O(app_wdf_data[126])); (* SOFT_HLUTNM = "soft_lutpair1324" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[127]_i_1 (.I0(s_axi_wdata[127]), .I1(wready_reg_rep_n_0), .I2(wdf_data[127]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[127]), .O(app_wdf_data[127])); (* SOFT_HLUTNM = "soft_lutpair1325" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[128]_i_1 (.I0(s_axi_wdata[128]), .I1(wready_reg_rep_n_0), .I2(wdf_data[128]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[128]), .O(app_wdf_data[128])); (* SOFT_HLUTNM = "soft_lutpair1326" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[129]_i_1 (.I0(s_axi_wdata[129]), .I1(wready_reg_rep_n_0), .I2(wdf_data[129]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[129]), .O(app_wdf_data[129])); (* SOFT_HLUTNM = "soft_lutpair1209" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[12]_i_1 (.I0(s_axi_wdata[12]), .I1(s_axi_wready), .I2(wdf_data[12]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[12]), .O(app_wdf_data[12])); (* SOFT_HLUTNM = "soft_lutpair1327" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[130]_i_1 (.I0(s_axi_wdata[130]), .I1(wready_reg_rep_n_0), .I2(wdf_data[130]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[130]), .O(app_wdf_data[130])); (* SOFT_HLUTNM = "soft_lutpair1328" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[131]_i_1 (.I0(s_axi_wdata[131]), .I1(wready_reg_rep_n_0), .I2(wdf_data[131]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[131]), .O(app_wdf_data[131])); (* SOFT_HLUTNM = "soft_lutpair1329" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[132]_i_1 (.I0(s_axi_wdata[132]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[132]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[132]), .O(app_wdf_data[132])); (* SOFT_HLUTNM = "soft_lutpair1330" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[133]_i_1 (.I0(s_axi_wdata[133]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[133]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[133]), .O(app_wdf_data[133])); (* SOFT_HLUTNM = "soft_lutpair1331" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[134]_i_1 (.I0(s_axi_wdata[134]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[134]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[134]), .O(app_wdf_data[134])); (* SOFT_HLUTNM = "soft_lutpair1332" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[135]_i_1 (.I0(s_axi_wdata[135]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[135]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[135]), .O(app_wdf_data[135])); (* SOFT_HLUTNM = "soft_lutpair1333" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[136]_i_1 (.I0(s_axi_wdata[136]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[136]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[136]), .O(app_wdf_data[136])); (* SOFT_HLUTNM = "soft_lutpair1334" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[137]_i_1 (.I0(s_axi_wdata[137]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[137]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[137]), .O(app_wdf_data[137])); (* SOFT_HLUTNM = "soft_lutpair1335" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[138]_i_1 (.I0(s_axi_wdata[138]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[138]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[138]), .O(app_wdf_data[138])); (* SOFT_HLUTNM = "soft_lutpair1336" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[139]_i_1 (.I0(s_axi_wdata[139]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[139]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[139]), .O(app_wdf_data[139])); (* SOFT_HLUTNM = "soft_lutpair1210" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[13]_i_1 (.I0(s_axi_wdata[13]), .I1(s_axi_wready), .I2(wdf_data[13]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[13]), .O(app_wdf_data[13])); (* SOFT_HLUTNM = "soft_lutpair1337" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[140]_i_1 (.I0(s_axi_wdata[140]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[140]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[140]), .O(app_wdf_data[140])); (* SOFT_HLUTNM = "soft_lutpair1338" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[141]_i_1 (.I0(s_axi_wdata[141]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[141]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[141]), .O(app_wdf_data[141])); (* SOFT_HLUTNM = "soft_lutpair1339" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[142]_i_1 (.I0(s_axi_wdata[142]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[142]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[142]), .O(app_wdf_data[142])); (* SOFT_HLUTNM = "soft_lutpair1340" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[143]_i_1 (.I0(s_axi_wdata[143]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[143]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[143]), .O(app_wdf_data[143])); (* SOFT_HLUTNM = "soft_lutpair1341" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[144]_i_1 (.I0(s_axi_wdata[144]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[144]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[144]), .O(app_wdf_data[144])); (* SOFT_HLUTNM = "soft_lutpair1342" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[145]_i_1 (.I0(s_axi_wdata[145]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[145]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[145]), .O(app_wdf_data[145])); (* SOFT_HLUTNM = "soft_lutpair1343" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[146]_i_1 (.I0(s_axi_wdata[146]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[146]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[146]), .O(app_wdf_data[146])); (* SOFT_HLUTNM = "soft_lutpair1344" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[147]_i_1 (.I0(s_axi_wdata[147]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[147]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[147]), .O(app_wdf_data[147])); (* SOFT_HLUTNM = "soft_lutpair1345" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[148]_i_1 (.I0(s_axi_wdata[148]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[148]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[148]), .O(app_wdf_data[148])); (* SOFT_HLUTNM = "soft_lutpair1346" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[149]_i_1 (.I0(s_axi_wdata[149]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[149]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[149]), .O(app_wdf_data[149])); (* SOFT_HLUTNM = "soft_lutpair1211" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[14]_i_1 (.I0(s_axi_wdata[14]), .I1(s_axi_wready), .I2(wdf_data[14]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[14]), .O(app_wdf_data[14])); (* SOFT_HLUTNM = "soft_lutpair1347" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[150]_i_1 (.I0(s_axi_wdata[150]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[150]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[150]), .O(app_wdf_data[150])); (* SOFT_HLUTNM = "soft_lutpair1348" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[151]_i_1 (.I0(s_axi_wdata[151]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[151]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[151]), .O(app_wdf_data[151])); (* SOFT_HLUTNM = "soft_lutpair1349" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[152]_i_1 (.I0(s_axi_wdata[152]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[152]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[152]), .O(app_wdf_data[152])); (* SOFT_HLUTNM = "soft_lutpair1350" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[153]_i_1 (.I0(s_axi_wdata[153]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[153]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[153]), .O(app_wdf_data[153])); (* SOFT_HLUTNM = "soft_lutpair1351" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[154]_i_1 (.I0(s_axi_wdata[154]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[154]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[154]), .O(app_wdf_data[154])); (* SOFT_HLUTNM = "soft_lutpair1352" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[155]_i_1 (.I0(s_axi_wdata[155]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[155]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[155]), .O(app_wdf_data[155])); (* SOFT_HLUTNM = "soft_lutpair1353" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[156]_i_1 (.I0(s_axi_wdata[156]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[156]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[156]), .O(app_wdf_data[156])); (* SOFT_HLUTNM = "soft_lutpair1354" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[157]_i_1 (.I0(s_axi_wdata[157]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[157]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[157]), .O(app_wdf_data[157])); (* SOFT_HLUTNM = "soft_lutpair1355" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[158]_i_1 (.I0(s_axi_wdata[158]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[158]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[158]), .O(app_wdf_data[158])); (* SOFT_HLUTNM = "soft_lutpair1356" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[159]_i_1 (.I0(s_axi_wdata[159]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[159]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[159]), .O(app_wdf_data[159])); (* SOFT_HLUTNM = "soft_lutpair1212" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[15]_i_1 (.I0(s_axi_wdata[15]), .I1(s_axi_wready), .I2(wdf_data[15]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[15]), .O(app_wdf_data[15])); (* SOFT_HLUTNM = "soft_lutpair1357" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[160]_i_1 (.I0(s_axi_wdata[160]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[160]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[160]), .O(app_wdf_data[160])); (* SOFT_HLUTNM = "soft_lutpair1358" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[161]_i_1 (.I0(s_axi_wdata[161]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[161]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[161]), .O(app_wdf_data[161])); (* SOFT_HLUTNM = "soft_lutpair1359" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[162]_i_1 (.I0(s_axi_wdata[162]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[162]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[162]), .O(app_wdf_data[162])); (* SOFT_HLUTNM = "soft_lutpair1360" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[163]_i_1 (.I0(s_axi_wdata[163]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[163]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[163]), .O(app_wdf_data[163])); (* SOFT_HLUTNM = "soft_lutpair1361" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[164]_i_1 (.I0(s_axi_wdata[164]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[164]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[164]), .O(app_wdf_data[164])); (* SOFT_HLUTNM = "soft_lutpair1362" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[165]_i_1 (.I0(s_axi_wdata[165]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[165]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[165]), .O(app_wdf_data[165])); (* SOFT_HLUTNM = "soft_lutpair1363" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[166]_i_1 (.I0(s_axi_wdata[166]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[166]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[166]), .O(app_wdf_data[166])); (* SOFT_HLUTNM = "soft_lutpair1364" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[167]_i_1 (.I0(s_axi_wdata[167]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[167]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[167]), .O(app_wdf_data[167])); (* SOFT_HLUTNM = "soft_lutpair1365" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[168]_i_1 (.I0(s_axi_wdata[168]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[168]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[168]), .O(app_wdf_data[168])); (* SOFT_HLUTNM = "soft_lutpair1366" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[169]_i_1 (.I0(s_axi_wdata[169]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[169]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[169]), .O(app_wdf_data[169])); (* SOFT_HLUTNM = "soft_lutpair1213" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[16]_i_1 (.I0(s_axi_wdata[16]), .I1(s_axi_wready), .I2(wdf_data[16]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[16]), .O(app_wdf_data[16])); (* SOFT_HLUTNM = "soft_lutpair1367" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[170]_i_1 (.I0(s_axi_wdata[170]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[170]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[170]), .O(app_wdf_data[170])); (* SOFT_HLUTNM = "soft_lutpair1368" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[171]_i_1 (.I0(s_axi_wdata[171]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[171]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[171]), .O(app_wdf_data[171])); (* SOFT_HLUTNM = "soft_lutpair1369" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[172]_i_1 (.I0(s_axi_wdata[172]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[172]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[172]), .O(app_wdf_data[172])); (* SOFT_HLUTNM = "soft_lutpair1370" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[173]_i_1 (.I0(s_axi_wdata[173]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[173]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[173]), .O(app_wdf_data[173])); (* SOFT_HLUTNM = "soft_lutpair1371" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[174]_i_1 (.I0(s_axi_wdata[174]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[174]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[174]), .O(app_wdf_data[174])); (* SOFT_HLUTNM = "soft_lutpair1372" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[175]_i_1 (.I0(s_axi_wdata[175]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[175]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[175]), .O(app_wdf_data[175])); (* SOFT_HLUTNM = "soft_lutpair1373" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[176]_i_1 (.I0(s_axi_wdata[176]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[176]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[176]), .O(app_wdf_data[176])); (* SOFT_HLUTNM = "soft_lutpair1374" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[177]_i_1 (.I0(s_axi_wdata[177]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[177]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[177]), .O(app_wdf_data[177])); (* SOFT_HLUTNM = "soft_lutpair1375" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[178]_i_1 (.I0(s_axi_wdata[178]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[178]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[178]), .O(app_wdf_data[178])); (* SOFT_HLUTNM = "soft_lutpair1376" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[179]_i_1 (.I0(s_axi_wdata[179]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[179]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[179]), .O(app_wdf_data[179])); (* SOFT_HLUTNM = "soft_lutpair1214" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[17]_i_1 (.I0(s_axi_wdata[17]), .I1(s_axi_wready), .I2(wdf_data[17]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[17]), .O(app_wdf_data[17])); (* SOFT_HLUTNM = "soft_lutpair1377" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[180]_i_1 (.I0(s_axi_wdata[180]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[180]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[180]), .O(app_wdf_data[180])); (* SOFT_HLUTNM = "soft_lutpair1378" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[181]_i_1 (.I0(s_axi_wdata[181]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[181]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[181]), .O(app_wdf_data[181])); (* SOFT_HLUTNM = "soft_lutpair1379" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[182]_i_1 (.I0(s_axi_wdata[182]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[182]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[182]), .O(app_wdf_data[182])); (* SOFT_HLUTNM = "soft_lutpair1380" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[183]_i_1 (.I0(s_axi_wdata[183]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[183]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[183]), .O(app_wdf_data[183])); (* SOFT_HLUTNM = "soft_lutpair1381" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[184]_i_1 (.I0(s_axi_wdata[184]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[184]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[184]), .O(app_wdf_data[184])); (* SOFT_HLUTNM = "soft_lutpair1382" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[185]_i_1 (.I0(s_axi_wdata[185]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[185]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[185]), .O(app_wdf_data[185])); (* SOFT_HLUTNM = "soft_lutpair1383" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[186]_i_1 (.I0(s_axi_wdata[186]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[186]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[186]), .O(app_wdf_data[186])); (* SOFT_HLUTNM = "soft_lutpair1384" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[187]_i_1 (.I0(s_axi_wdata[187]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[187]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[187]), .O(app_wdf_data[187])); (* SOFT_HLUTNM = "soft_lutpair1385" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[188]_i_1 (.I0(s_axi_wdata[188]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[188]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[188]), .O(app_wdf_data[188])); (* SOFT_HLUTNM = "soft_lutpair1386" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[189]_i_1 (.I0(s_axi_wdata[189]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[189]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[189]), .O(app_wdf_data[189])); (* SOFT_HLUTNM = "soft_lutpair1215" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[18]_i_1 (.I0(s_axi_wdata[18]), .I1(s_axi_wready), .I2(wdf_data[18]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[18]), .O(app_wdf_data[18])); (* SOFT_HLUTNM = "soft_lutpair1387" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[190]_i_1 (.I0(s_axi_wdata[190]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[190]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[190]), .O(app_wdf_data[190])); (* SOFT_HLUTNM = "soft_lutpair1388" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[191]_i_1 (.I0(s_axi_wdata[191]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[191]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[191]), .O(app_wdf_data[191])); (* SOFT_HLUTNM = "soft_lutpair1389" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[192]_i_1 (.I0(s_axi_wdata[192]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[192]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[192]), .O(app_wdf_data[192])); (* SOFT_HLUTNM = "soft_lutpair1390" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[193]_i_1 (.I0(s_axi_wdata[193]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[193]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[193]), .O(app_wdf_data[193])); (* SOFT_HLUTNM = "soft_lutpair1391" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[194]_i_1 (.I0(s_axi_wdata[194]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[194]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[194]), .O(app_wdf_data[194])); (* SOFT_HLUTNM = "soft_lutpair1392" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[195]_i_1 (.I0(s_axi_wdata[195]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[195]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[195]), .O(app_wdf_data[195])); (* SOFT_HLUTNM = "soft_lutpair1393" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[196]_i_1 (.I0(s_axi_wdata[196]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[196]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[196]), .O(app_wdf_data[196])); (* SOFT_HLUTNM = "soft_lutpair1394" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[197]_i_1 (.I0(s_axi_wdata[197]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[197]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[197]), .O(app_wdf_data[197])); (* SOFT_HLUTNM = "soft_lutpair1395" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[198]_i_1 (.I0(s_axi_wdata[198]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[198]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[198]), .O(app_wdf_data[198])); (* SOFT_HLUTNM = "soft_lutpair1396" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[199]_i_1 (.I0(s_axi_wdata[199]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[199]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[199]), .O(app_wdf_data[199])); (* SOFT_HLUTNM = "soft_lutpair1216" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[19]_i_1 (.I0(s_axi_wdata[19]), .I1(s_axi_wready), .I2(wdf_data[19]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[19]), .O(app_wdf_data[19])); (* SOFT_HLUTNM = "soft_lutpair1198" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[1]_i_1 (.I0(s_axi_wdata[1]), .I1(s_axi_wready), .I2(wdf_data[1]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[1]), .O(app_wdf_data[1])); (* SOFT_HLUTNM = "soft_lutpair1397" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[200]_i_1 (.I0(s_axi_wdata[200]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[200]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[200]), .O(app_wdf_data[200])); (* SOFT_HLUTNM = "soft_lutpair1398" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[201]_i_1 (.I0(s_axi_wdata[201]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[201]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[201]), .O(app_wdf_data[201])); (* SOFT_HLUTNM = "soft_lutpair1399" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[202]_i_1 (.I0(s_axi_wdata[202]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[202]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[202]), .O(app_wdf_data[202])); (* SOFT_HLUTNM = "soft_lutpair1400" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[203]_i_1 (.I0(s_axi_wdata[203]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[203]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[203]), .O(app_wdf_data[203])); (* SOFT_HLUTNM = "soft_lutpair1401" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[204]_i_1 (.I0(s_axi_wdata[204]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[204]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[204]), .O(app_wdf_data[204])); (* SOFT_HLUTNM = "soft_lutpair1402" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[205]_i_1 (.I0(s_axi_wdata[205]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[205]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[205]), .O(app_wdf_data[205])); (* SOFT_HLUTNM = "soft_lutpair1403" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[206]_i_1 (.I0(s_axi_wdata[206]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[206]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[206]), .O(app_wdf_data[206])); (* SOFT_HLUTNM = "soft_lutpair1404" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[207]_i_1 (.I0(s_axi_wdata[207]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[207]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[207]), .O(app_wdf_data[207])); (* SOFT_HLUTNM = "soft_lutpair1405" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[208]_i_1 (.I0(s_axi_wdata[208]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[208]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[208]), .O(app_wdf_data[208])); (* SOFT_HLUTNM = "soft_lutpair1406" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[209]_i_1 (.I0(s_axi_wdata[209]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[209]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[209]), .O(app_wdf_data[209])); (* SOFT_HLUTNM = "soft_lutpair1217" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[20]_i_1 (.I0(s_axi_wdata[20]), .I1(s_axi_wready), .I2(wdf_data[20]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[20]), .O(app_wdf_data[20])); (* SOFT_HLUTNM = "soft_lutpair1407" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[210]_i_1 (.I0(s_axi_wdata[210]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[210]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[210]), .O(app_wdf_data[210])); (* SOFT_HLUTNM = "soft_lutpair1408" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[211]_i_1 (.I0(s_axi_wdata[211]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[211]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[211]), .O(app_wdf_data[211])); (* SOFT_HLUTNM = "soft_lutpair1409" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[212]_i_1 (.I0(s_axi_wdata[212]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[212]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[212]), .O(app_wdf_data[212])); (* SOFT_HLUTNM = "soft_lutpair1410" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[213]_i_1 (.I0(s_axi_wdata[213]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[213]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[213]), .O(app_wdf_data[213])); (* SOFT_HLUTNM = "soft_lutpair1411" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[214]_i_1 (.I0(s_axi_wdata[214]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[214]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[214]), .O(app_wdf_data[214])); (* SOFT_HLUTNM = "soft_lutpair1412" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[215]_i_1 (.I0(s_axi_wdata[215]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[215]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[215]), .O(app_wdf_data[215])); (* SOFT_HLUTNM = "soft_lutpair1413" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[216]_i_1 (.I0(s_axi_wdata[216]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[216]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[216]), .O(app_wdf_data[216])); (* SOFT_HLUTNM = "soft_lutpair1414" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[217]_i_1 (.I0(s_axi_wdata[217]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[217]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[217]), .O(app_wdf_data[217])); (* SOFT_HLUTNM = "soft_lutpair1415" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[218]_i_1 (.I0(s_axi_wdata[218]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[218]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[218]), .O(app_wdf_data[218])); (* SOFT_HLUTNM = "soft_lutpair1416" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[219]_i_1 (.I0(s_axi_wdata[219]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[219]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[219]), .O(app_wdf_data[219])); (* SOFT_HLUTNM = "soft_lutpair1218" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[21]_i_1 (.I0(s_axi_wdata[21]), .I1(s_axi_wready), .I2(wdf_data[21]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[21]), .O(app_wdf_data[21])); (* SOFT_HLUTNM = "soft_lutpair1417" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[220]_i_1 (.I0(s_axi_wdata[220]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[220]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[220]), .O(app_wdf_data[220])); (* SOFT_HLUTNM = "soft_lutpair1418" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[221]_i_1 (.I0(s_axi_wdata[221]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[221]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[221]), .O(app_wdf_data[221])); (* SOFT_HLUTNM = "soft_lutpair1419" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[222]_i_1 (.I0(s_axi_wdata[222]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[222]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[222]), .O(app_wdf_data[222])); (* SOFT_HLUTNM = "soft_lutpair1420" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[223]_i_1 (.I0(s_axi_wdata[223]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[223]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[223]), .O(app_wdf_data[223])); (* SOFT_HLUTNM = "soft_lutpair1421" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[224]_i_1 (.I0(s_axi_wdata[224]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[224]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[224]), .O(app_wdf_data[224])); (* SOFT_HLUTNM = "soft_lutpair1422" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[225]_i_1 (.I0(s_axi_wdata[225]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[225]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[225]), .O(app_wdf_data[225])); (* SOFT_HLUTNM = "soft_lutpair1423" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[226]_i_1 (.I0(s_axi_wdata[226]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[226]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[226]), .O(app_wdf_data[226])); (* SOFT_HLUTNM = "soft_lutpair1424" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[227]_i_1 (.I0(s_axi_wdata[227]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[227]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[227]), .O(app_wdf_data[227])); (* SOFT_HLUTNM = "soft_lutpair1425" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[228]_i_1 (.I0(s_axi_wdata[228]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[228]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[228]), .O(app_wdf_data[228])); (* SOFT_HLUTNM = "soft_lutpair1426" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[229]_i_1 (.I0(s_axi_wdata[229]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[229]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[229]), .O(app_wdf_data[229])); (* SOFT_HLUTNM = "soft_lutpair1219" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[22]_i_1 (.I0(s_axi_wdata[22]), .I1(s_axi_wready), .I2(wdf_data[22]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[22]), .O(app_wdf_data[22])); (* SOFT_HLUTNM = "soft_lutpair1427" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[230]_i_1 (.I0(s_axi_wdata[230]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[230]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[230]), .O(app_wdf_data[230])); (* SOFT_HLUTNM = "soft_lutpair1428" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[231]_i_1 (.I0(s_axi_wdata[231]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[231]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[231]), .O(app_wdf_data[231])); (* SOFT_HLUTNM = "soft_lutpair1429" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[232]_i_1 (.I0(s_axi_wdata[232]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[232]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[232]), .O(app_wdf_data[232])); (* SOFT_HLUTNM = "soft_lutpair1430" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[233]_i_1 (.I0(s_axi_wdata[233]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[233]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[233]), .O(app_wdf_data[233])); (* SOFT_HLUTNM = "soft_lutpair1431" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[234]_i_1 (.I0(s_axi_wdata[234]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[234]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[234]), .O(app_wdf_data[234])); (* SOFT_HLUTNM = "soft_lutpair1432" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[235]_i_1 (.I0(s_axi_wdata[235]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[235]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[235]), .O(app_wdf_data[235])); (* SOFT_HLUTNM = "soft_lutpair1433" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[236]_i_1 (.I0(s_axi_wdata[236]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[236]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[236]), .O(app_wdf_data[236])); (* SOFT_HLUTNM = "soft_lutpair1434" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[237]_i_1 (.I0(s_axi_wdata[237]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[237]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[237]), .O(app_wdf_data[237])); (* SOFT_HLUTNM = "soft_lutpair1435" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[238]_i_1 (.I0(s_axi_wdata[238]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[238]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[238]), .O(app_wdf_data[238])); (* SOFT_HLUTNM = "soft_lutpair1436" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[239]_i_1 (.I0(s_axi_wdata[239]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[239]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[239]), .O(app_wdf_data[239])); (* SOFT_HLUTNM = "soft_lutpair1220" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[23]_i_1 (.I0(s_axi_wdata[23]), .I1(s_axi_wready), .I2(wdf_data[23]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[23]), .O(app_wdf_data[23])); (* SOFT_HLUTNM = "soft_lutpair1437" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[240]_i_1 (.I0(s_axi_wdata[240]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[240]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[240]), .O(app_wdf_data[240])); (* SOFT_HLUTNM = "soft_lutpair1438" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[241]_i_1 (.I0(s_axi_wdata[241]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[241]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[241]), .O(app_wdf_data[241])); (* SOFT_HLUTNM = "soft_lutpair1439" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[242]_i_1 (.I0(s_axi_wdata[242]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[242]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[242]), .O(app_wdf_data[242])); (* SOFT_HLUTNM = "soft_lutpair1440" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[243]_i_1 (.I0(s_axi_wdata[243]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[243]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[243]), .O(app_wdf_data[243])); (* SOFT_HLUTNM = "soft_lutpair1441" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[244]_i_1 (.I0(s_axi_wdata[244]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[244]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[244]), .O(app_wdf_data[244])); (* SOFT_HLUTNM = "soft_lutpair1442" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[245]_i_1 (.I0(s_axi_wdata[245]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[245]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[245]), .O(app_wdf_data[245])); (* SOFT_HLUTNM = "soft_lutpair1443" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[246]_i_1 (.I0(s_axi_wdata[246]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[246]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[246]), .O(app_wdf_data[246])); (* SOFT_HLUTNM = "soft_lutpair1444" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[247]_i_1 (.I0(s_axi_wdata[247]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[247]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[247]), .O(app_wdf_data[247])); (* SOFT_HLUTNM = "soft_lutpair1445" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[248]_i_1 (.I0(s_axi_wdata[248]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[248]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[248]), .O(app_wdf_data[248])); (* SOFT_HLUTNM = "soft_lutpair1446" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[249]_i_1 (.I0(s_axi_wdata[249]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[249]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[249]), .O(app_wdf_data[249])); (* SOFT_HLUTNM = "soft_lutpair1221" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[24]_i_1 (.I0(s_axi_wdata[24]), .I1(s_axi_wready), .I2(wdf_data[24]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[24]), .O(app_wdf_data[24])); (* SOFT_HLUTNM = "soft_lutpair1447" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[250]_i_1 (.I0(s_axi_wdata[250]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[250]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[250]), .O(app_wdf_data[250])); (* SOFT_HLUTNM = "soft_lutpair1448" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[251]_i_1 (.I0(s_axi_wdata[251]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[251]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[251]), .O(app_wdf_data[251])); (* SOFT_HLUTNM = "soft_lutpair1449" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[252]_i_1 (.I0(s_axi_wdata[252]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[252]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[252]), .O(app_wdf_data[252])); (* SOFT_HLUTNM = "soft_lutpair1450" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[253]_i_1 (.I0(s_axi_wdata[253]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[253]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[253]), .O(app_wdf_data[253])); (* SOFT_HLUTNM = "soft_lutpair1451" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[254]_i_1 (.I0(s_axi_wdata[254]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[254]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[254]), .O(app_wdf_data[254])); (* SOFT_HLUTNM = "soft_lutpair1452" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[255]_i_1 (.I0(s_axi_wdata[255]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[255]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[255]), .O(app_wdf_data[255])); (* SOFT_HLUTNM = "soft_lutpair1222" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[25]_i_1 (.I0(s_axi_wdata[25]), .I1(s_axi_wready), .I2(wdf_data[25]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[25]), .O(app_wdf_data[25])); (* SOFT_HLUTNM = "soft_lutpair1223" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[26]_i_1 (.I0(s_axi_wdata[26]), .I1(s_axi_wready), .I2(wdf_data[26]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[26]), .O(app_wdf_data[26])); (* SOFT_HLUTNM = "soft_lutpair1224" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[27]_i_1 (.I0(s_axi_wdata[27]), .I1(s_axi_wready), .I2(wdf_data[27]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[27]), .O(app_wdf_data[27])); (* SOFT_HLUTNM = "soft_lutpair1225" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[28]_i_1 (.I0(s_axi_wdata[28]), .I1(s_axi_wready), .I2(wdf_data[28]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[28]), .O(app_wdf_data[28])); (* SOFT_HLUTNM = "soft_lutpair1226" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[29]_i_1 (.I0(s_axi_wdata[29]), .I1(s_axi_wready), .I2(wdf_data[29]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[29]), .O(app_wdf_data[29])); (* SOFT_HLUTNM = "soft_lutpair1199" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[2]_i_1 (.I0(s_axi_wdata[2]), .I1(s_axi_wready), .I2(wdf_data[2]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[2]), .O(app_wdf_data[2])); (* SOFT_HLUTNM = "soft_lutpair1227" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[30]_i_1 (.I0(s_axi_wdata[30]), .I1(s_axi_wready), .I2(wdf_data[30]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[30]), .O(app_wdf_data[30])); (* SOFT_HLUTNM = "soft_lutpair1228" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[31]_i_1 (.I0(s_axi_wdata[31]), .I1(s_axi_wready), .I2(wdf_data[31]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[31]), .O(app_wdf_data[31])); (* SOFT_HLUTNM = "soft_lutpair1229" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[32]_i_1 (.I0(s_axi_wdata[32]), .I1(s_axi_wready), .I2(wdf_data[32]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[32]), .O(app_wdf_data[32])); (* SOFT_HLUTNM = "soft_lutpair1230" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[33]_i_1 (.I0(s_axi_wdata[33]), .I1(s_axi_wready), .I2(wdf_data[33]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[33]), .O(app_wdf_data[33])); (* SOFT_HLUTNM = "soft_lutpair1231" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[34]_i_1 (.I0(s_axi_wdata[34]), .I1(s_axi_wready), .I2(wdf_data[34]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[34]), .O(app_wdf_data[34])); (* SOFT_HLUTNM = "soft_lutpair1232" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[35]_i_1 (.I0(s_axi_wdata[35]), .I1(s_axi_wready), .I2(wdf_data[35]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[35]), .O(app_wdf_data[35])); (* SOFT_HLUTNM = "soft_lutpair1233" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[36]_i_1 (.I0(s_axi_wdata[36]), .I1(s_axi_wready), .I2(wdf_data[36]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[36]), .O(app_wdf_data[36])); (* SOFT_HLUTNM = "soft_lutpair1234" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[37]_i_1 (.I0(s_axi_wdata[37]), .I1(s_axi_wready), .I2(wdf_data[37]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[37]), .O(app_wdf_data[37])); (* SOFT_HLUTNM = "soft_lutpair1235" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[38]_i_1 (.I0(s_axi_wdata[38]), .I1(s_axi_wready), .I2(wdf_data[38]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[38]), .O(app_wdf_data[38])); (* SOFT_HLUTNM = "soft_lutpair1236" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[39]_i_1 (.I0(s_axi_wdata[39]), .I1(s_axi_wready), .I2(wdf_data[39]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[39]), .O(app_wdf_data[39])); (* SOFT_HLUTNM = "soft_lutpair1200" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[3]_i_1 (.I0(s_axi_wdata[3]), .I1(s_axi_wready), .I2(wdf_data[3]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[3]), .O(app_wdf_data[3])); (* SOFT_HLUTNM = "soft_lutpair1237" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[40]_i_1 (.I0(s_axi_wdata[40]), .I1(s_axi_wready), .I2(wdf_data[40]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[40]), .O(app_wdf_data[40])); (* SOFT_HLUTNM = "soft_lutpair1238" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[41]_i_1 (.I0(s_axi_wdata[41]), .I1(s_axi_wready), .I2(wdf_data[41]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[41]), .O(app_wdf_data[41])); (* SOFT_HLUTNM = "soft_lutpair1239" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[42]_i_1 (.I0(s_axi_wdata[42]), .I1(s_axi_wready), .I2(wdf_data[42]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[42]), .O(app_wdf_data[42])); (* SOFT_HLUTNM = "soft_lutpair1240" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[43]_i_1 (.I0(s_axi_wdata[43]), .I1(s_axi_wready), .I2(wdf_data[43]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[43]), .O(app_wdf_data[43])); (* SOFT_HLUTNM = "soft_lutpair1241" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[44]_i_1 (.I0(s_axi_wdata[44]), .I1(s_axi_wready), .I2(wdf_data[44]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[44]), .O(app_wdf_data[44])); (* SOFT_HLUTNM = "soft_lutpair1242" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[45]_i_1 (.I0(s_axi_wdata[45]), .I1(s_axi_wready), .I2(wdf_data[45]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[45]), .O(app_wdf_data[45])); (* SOFT_HLUTNM = "soft_lutpair1243" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[46]_i_1 (.I0(s_axi_wdata[46]), .I1(s_axi_wready), .I2(wdf_data[46]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[46]), .O(app_wdf_data[46])); (* SOFT_HLUTNM = "soft_lutpair1244" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[47]_i_1 (.I0(s_axi_wdata[47]), .I1(s_axi_wready), .I2(wdf_data[47]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[47]), .O(app_wdf_data[47])); (* SOFT_HLUTNM = "soft_lutpair1245" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[48]_i_1 (.I0(s_axi_wdata[48]), .I1(s_axi_wready), .I2(wdf_data[48]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[48]), .O(app_wdf_data[48])); (* SOFT_HLUTNM = "soft_lutpair1246" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[49]_i_1 (.I0(s_axi_wdata[49]), .I1(s_axi_wready), .I2(wdf_data[49]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[49]), .O(app_wdf_data[49])); (* SOFT_HLUTNM = "soft_lutpair1201" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[4]_i_1 (.I0(s_axi_wdata[4]), .I1(s_axi_wready), .I2(wdf_data[4]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[4]), .O(app_wdf_data[4])); (* SOFT_HLUTNM = "soft_lutpair1247" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[50]_i_1 (.I0(s_axi_wdata[50]), .I1(s_axi_wready), .I2(wdf_data[50]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[50]), .O(app_wdf_data[50])); (* SOFT_HLUTNM = "soft_lutpair1248" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[51]_i_1 (.I0(s_axi_wdata[51]), .I1(s_axi_wready), .I2(wdf_data[51]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[51]), .O(app_wdf_data[51])); (* SOFT_HLUTNM = "soft_lutpair1249" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[52]_i_1 (.I0(s_axi_wdata[52]), .I1(s_axi_wready), .I2(wdf_data[52]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[52]), .O(app_wdf_data[52])); (* SOFT_HLUTNM = "soft_lutpair1250" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[53]_i_1 (.I0(s_axi_wdata[53]), .I1(s_axi_wready), .I2(wdf_data[53]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[53]), .O(app_wdf_data[53])); (* SOFT_HLUTNM = "soft_lutpair1251" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[54]_i_1 (.I0(s_axi_wdata[54]), .I1(s_axi_wready), .I2(wdf_data[54]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[54]), .O(app_wdf_data[54])); (* SOFT_HLUTNM = "soft_lutpair1252" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[55]_i_1 (.I0(s_axi_wdata[55]), .I1(s_axi_wready), .I2(wdf_data[55]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[55]), .O(app_wdf_data[55])); (* SOFT_HLUTNM = "soft_lutpair1253" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[56]_i_1 (.I0(s_axi_wdata[56]), .I1(s_axi_wready), .I2(wdf_data[56]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[56]), .O(app_wdf_data[56])); (* SOFT_HLUTNM = "soft_lutpair1254" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[57]_i_1 (.I0(s_axi_wdata[57]), .I1(s_axi_wready), .I2(wdf_data[57]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[57]), .O(app_wdf_data[57])); (* SOFT_HLUTNM = "soft_lutpair1255" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[58]_i_1 (.I0(s_axi_wdata[58]), .I1(s_axi_wready), .I2(wdf_data[58]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[58]), .O(app_wdf_data[58])); (* SOFT_HLUTNM = "soft_lutpair1256" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[59]_i_1 (.I0(s_axi_wdata[59]), .I1(s_axi_wready), .I2(wdf_data[59]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[59]), .O(app_wdf_data[59])); (* SOFT_HLUTNM = "soft_lutpair1202" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[5]_i_1 (.I0(s_axi_wdata[5]), .I1(s_axi_wready), .I2(wdf_data[5]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[5]), .O(app_wdf_data[5])); (* SOFT_HLUTNM = "soft_lutpair1257" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[60]_i_1 (.I0(s_axi_wdata[60]), .I1(s_axi_wready), .I2(wdf_data[60]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[60]), .O(app_wdf_data[60])); (* SOFT_HLUTNM = "soft_lutpair1258" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[61]_i_1 (.I0(s_axi_wdata[61]), .I1(s_axi_wready), .I2(wdf_data[61]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[61]), .O(app_wdf_data[61])); (* SOFT_HLUTNM = "soft_lutpair1259" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[62]_i_1 (.I0(s_axi_wdata[62]), .I1(s_axi_wready), .I2(wdf_data[62]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[62]), .O(app_wdf_data[62])); (* SOFT_HLUTNM = "soft_lutpair1260" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[63]_i_1 (.I0(s_axi_wdata[63]), .I1(s_axi_wready), .I2(wdf_data[63]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[63]), .O(app_wdf_data[63])); (* SOFT_HLUTNM = "soft_lutpair1261" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[64]_i_1 (.I0(s_axi_wdata[64]), .I1(s_axi_wready), .I2(wdf_data[64]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[64]), .O(app_wdf_data[64])); (* SOFT_HLUTNM = "soft_lutpair1262" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[65]_i_1 (.I0(s_axi_wdata[65]), .I1(s_axi_wready), .I2(wdf_data[65]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[65]), .O(app_wdf_data[65])); (* SOFT_HLUTNM = "soft_lutpair1263" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[66]_i_1 (.I0(s_axi_wdata[66]), .I1(wready_reg_rep_n_0), .I2(wdf_data[66]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[66]), .O(app_wdf_data[66])); (* SOFT_HLUTNM = "soft_lutpair1264" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[67]_i_1 (.I0(s_axi_wdata[67]), .I1(wready_reg_rep_n_0), .I2(wdf_data[67]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[67]), .O(app_wdf_data[67])); (* SOFT_HLUTNM = "soft_lutpair1265" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[68]_i_1 (.I0(s_axi_wdata[68]), .I1(wready_reg_rep_n_0), .I2(wdf_data[68]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[68]), .O(app_wdf_data[68])); (* SOFT_HLUTNM = "soft_lutpair1266" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[69]_i_1 (.I0(s_axi_wdata[69]), .I1(wready_reg_rep_n_0), .I2(wdf_data[69]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[69]), .O(app_wdf_data[69])); (* SOFT_HLUTNM = "soft_lutpair1203" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[6]_i_1 (.I0(s_axi_wdata[6]), .I1(s_axi_wready), .I2(wdf_data[6]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[6]), .O(app_wdf_data[6])); (* SOFT_HLUTNM = "soft_lutpair1267" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[70]_i_1 (.I0(s_axi_wdata[70]), .I1(wready_reg_rep_n_0), .I2(wdf_data[70]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[70]), .O(app_wdf_data[70])); (* SOFT_HLUTNM = "soft_lutpair1268" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[71]_i_1 (.I0(s_axi_wdata[71]), .I1(wready_reg_rep_n_0), .I2(wdf_data[71]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[71]), .O(app_wdf_data[71])); (* SOFT_HLUTNM = "soft_lutpair1269" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[72]_i_1 (.I0(s_axi_wdata[72]), .I1(wready_reg_rep_n_0), .I2(wdf_data[72]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[72]), .O(app_wdf_data[72])); (* SOFT_HLUTNM = "soft_lutpair1270" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[73]_i_1 (.I0(s_axi_wdata[73]), .I1(wready_reg_rep_n_0), .I2(wdf_data[73]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[73]), .O(app_wdf_data[73])); (* SOFT_HLUTNM = "soft_lutpair1271" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[74]_i_1 (.I0(s_axi_wdata[74]), .I1(wready_reg_rep_n_0), .I2(wdf_data[74]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[74]), .O(app_wdf_data[74])); (* SOFT_HLUTNM = "soft_lutpair1272" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[75]_i_1 (.I0(s_axi_wdata[75]), .I1(wready_reg_rep_n_0), .I2(wdf_data[75]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[75]), .O(app_wdf_data[75])); (* SOFT_HLUTNM = "soft_lutpair1273" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[76]_i_1 (.I0(s_axi_wdata[76]), .I1(wready_reg_rep_n_0), .I2(wdf_data[76]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[76]), .O(app_wdf_data[76])); (* SOFT_HLUTNM = "soft_lutpair1274" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[77]_i_1 (.I0(s_axi_wdata[77]), .I1(wready_reg_rep_n_0), .I2(wdf_data[77]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[77]), .O(app_wdf_data[77])); (* SOFT_HLUTNM = "soft_lutpair1275" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[78]_i_1 (.I0(s_axi_wdata[78]), .I1(wready_reg_rep_n_0), .I2(wdf_data[78]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[78]), .O(app_wdf_data[78])); (* SOFT_HLUTNM = "soft_lutpair1276" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[79]_i_1 (.I0(s_axi_wdata[79]), .I1(wready_reg_rep_n_0), .I2(wdf_data[79]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[79]), .O(app_wdf_data[79])); (* SOFT_HLUTNM = "soft_lutpair1204" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[7]_i_1 (.I0(s_axi_wdata[7]), .I1(s_axi_wready), .I2(wdf_data[7]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[7]), .O(app_wdf_data[7])); (* SOFT_HLUTNM = "soft_lutpair1277" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[80]_i_1 (.I0(s_axi_wdata[80]), .I1(wready_reg_rep_n_0), .I2(wdf_data[80]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[80]), .O(app_wdf_data[80])); (* SOFT_HLUTNM = "soft_lutpair1278" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[81]_i_1 (.I0(s_axi_wdata[81]), .I1(wready_reg_rep_n_0), .I2(wdf_data[81]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[81]), .O(app_wdf_data[81])); (* SOFT_HLUTNM = "soft_lutpair1279" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[82]_i_1 (.I0(s_axi_wdata[82]), .I1(wready_reg_rep_n_0), .I2(wdf_data[82]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[82]), .O(app_wdf_data[82])); (* SOFT_HLUTNM = "soft_lutpair1280" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[83]_i_1 (.I0(s_axi_wdata[83]), .I1(wready_reg_rep_n_0), .I2(wdf_data[83]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[83]), .O(app_wdf_data[83])); (* SOFT_HLUTNM = "soft_lutpair1281" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[84]_i_1 (.I0(s_axi_wdata[84]), .I1(wready_reg_rep_n_0), .I2(wdf_data[84]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[84]), .O(app_wdf_data[84])); (* SOFT_HLUTNM = "soft_lutpair1282" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[85]_i_1 (.I0(s_axi_wdata[85]), .I1(wready_reg_rep_n_0), .I2(wdf_data[85]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[85]), .O(app_wdf_data[85])); (* SOFT_HLUTNM = "soft_lutpair1283" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[86]_i_1 (.I0(s_axi_wdata[86]), .I1(wready_reg_rep_n_0), .I2(wdf_data[86]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[86]), .O(app_wdf_data[86])); (* SOFT_HLUTNM = "soft_lutpair1284" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[87]_i_1 (.I0(s_axi_wdata[87]), .I1(wready_reg_rep_n_0), .I2(wdf_data[87]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[87]), .O(app_wdf_data[87])); (* SOFT_HLUTNM = "soft_lutpair1285" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[88]_i_1 (.I0(s_axi_wdata[88]), .I1(wready_reg_rep_n_0), .I2(wdf_data[88]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[88]), .O(app_wdf_data[88])); (* SOFT_HLUTNM = "soft_lutpair1286" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[89]_i_1 (.I0(s_axi_wdata[89]), .I1(wready_reg_rep_n_0), .I2(wdf_data[89]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[89]), .O(app_wdf_data[89])); (* SOFT_HLUTNM = "soft_lutpair1205" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[8]_i_1 (.I0(s_axi_wdata[8]), .I1(s_axi_wready), .I2(wdf_data[8]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[8]), .O(app_wdf_data[8])); (* SOFT_HLUTNM = "soft_lutpair1287" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[90]_i_1 (.I0(s_axi_wdata[90]), .I1(wready_reg_rep_n_0), .I2(wdf_data[90]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[90]), .O(app_wdf_data[90])); (* SOFT_HLUTNM = "soft_lutpair1288" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[91]_i_1 (.I0(s_axi_wdata[91]), .I1(wready_reg_rep_n_0), .I2(wdf_data[91]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[91]), .O(app_wdf_data[91])); (* SOFT_HLUTNM = "soft_lutpair1289" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[92]_i_1 (.I0(s_axi_wdata[92]), .I1(wready_reg_rep_n_0), .I2(wdf_data[92]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[92]), .O(app_wdf_data[92])); (* SOFT_HLUTNM = "soft_lutpair1290" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[93]_i_1 (.I0(s_axi_wdata[93]), .I1(wready_reg_rep_n_0), .I2(wdf_data[93]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[93]), .O(app_wdf_data[93])); (* SOFT_HLUTNM = "soft_lutpair1291" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[94]_i_1 (.I0(s_axi_wdata[94]), .I1(wready_reg_rep_n_0), .I2(wdf_data[94]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[94]), .O(app_wdf_data[94])); (* SOFT_HLUTNM = "soft_lutpair1292" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[95]_i_1 (.I0(s_axi_wdata[95]), .I1(wready_reg_rep_n_0), .I2(wdf_data[95]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[95]), .O(app_wdf_data[95])); (* SOFT_HLUTNM = "soft_lutpair1293" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[96]_i_1 (.I0(s_axi_wdata[96]), .I1(wready_reg_rep_n_0), .I2(wdf_data[96]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[96]), .O(app_wdf_data[96])); (* SOFT_HLUTNM = "soft_lutpair1294" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[97]_i_1 (.I0(s_axi_wdata[97]), .I1(wready_reg_rep_n_0), .I2(wdf_data[97]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[97]), .O(app_wdf_data[97])); (* SOFT_HLUTNM = "soft_lutpair1295" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[98]_i_1 (.I0(s_axi_wdata[98]), .I1(wready_reg_rep_n_0), .I2(wdf_data[98]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[98]), .O(app_wdf_data[98])); (* SOFT_HLUTNM = "soft_lutpair1296" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[99]_i_1 (.I0(s_axi_wdata[99]), .I1(wready_reg_rep_n_0), .I2(wdf_data[99]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[99]), .O(app_wdf_data[99])); (* SOFT_HLUTNM = "soft_lutpair1206" *) LUT5 #( .INIT(32'hB8FFB800)) \app_wdf_data_r1[9]_i_1 (.I0(s_axi_wdata[9]), .I1(s_axi_wready), .I2(wdf_data[9]), .I3(app_wdf_rdy), .I4(mc_app_wdf_data_reg[9]), .O(app_wdf_data[9])); (* SOFT_HLUTNM = "soft_lutpair1453" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[0]_i_1 (.I0(s_axi_wstrb[0]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[0]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[0]), .O(app_wdf_mask[0])); (* SOFT_HLUTNM = "soft_lutpair1463" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[10]_i_1 (.I0(s_axi_wstrb[10]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[10]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[10]), .O(app_wdf_mask[10])); (* SOFT_HLUTNM = "soft_lutpair1464" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[11]_i_1 (.I0(s_axi_wstrb[11]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[11]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[11]), .O(app_wdf_mask[11])); (* SOFT_HLUTNM = "soft_lutpair1465" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[12]_i_1 (.I0(s_axi_wstrb[12]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[12]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[12]), .O(app_wdf_mask[12])); (* SOFT_HLUTNM = "soft_lutpair1466" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[13]_i_1 (.I0(s_axi_wstrb[13]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[13]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[13]), .O(app_wdf_mask[13])); (* SOFT_HLUTNM = "soft_lutpair1467" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[14]_i_1 (.I0(s_axi_wstrb[14]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[14]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[14]), .O(app_wdf_mask[14])); (* SOFT_HLUTNM = "soft_lutpair1468" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[15]_i_1 (.I0(s_axi_wstrb[15]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[15]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[15]), .O(app_wdf_mask[15])); (* SOFT_HLUTNM = "soft_lutpair1469" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[16]_i_1 (.I0(s_axi_wstrb[16]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[16]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[16]), .O(app_wdf_mask[16])); (* SOFT_HLUTNM = "soft_lutpair1470" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[17]_i_1 (.I0(s_axi_wstrb[17]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[17]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[17]), .O(app_wdf_mask[17])); (* SOFT_HLUTNM = "soft_lutpair1471" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[18]_i_1 (.I0(s_axi_wstrb[18]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[18]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[18]), .O(app_wdf_mask[18])); (* SOFT_HLUTNM = "soft_lutpair1472" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[19]_i_1 (.I0(s_axi_wstrb[19]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[19]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[19]), .O(app_wdf_mask[19])); (* SOFT_HLUTNM = "soft_lutpair1454" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[1]_i_1 (.I0(s_axi_wstrb[1]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[1]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[1]), .O(app_wdf_mask[1])); (* SOFT_HLUTNM = "soft_lutpair1473" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[20]_i_1 (.I0(s_axi_wstrb[20]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[20]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[20]), .O(app_wdf_mask[20])); (* SOFT_HLUTNM = "soft_lutpair1474" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[21]_i_1 (.I0(s_axi_wstrb[21]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[21]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[21]), .O(app_wdf_mask[21])); (* SOFT_HLUTNM = "soft_lutpair1475" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[22]_i_1 (.I0(s_axi_wstrb[22]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[22]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[22]), .O(app_wdf_mask[22])); (* SOFT_HLUTNM = "soft_lutpair1476" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[23]_i_1 (.I0(s_axi_wstrb[23]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[23]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[23]), .O(app_wdf_mask[23])); (* SOFT_HLUTNM = "soft_lutpair1477" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[24]_i_1 (.I0(s_axi_wstrb[24]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[24]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[24]), .O(app_wdf_mask[24])); (* SOFT_HLUTNM = "soft_lutpair1478" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[25]_i_1 (.I0(s_axi_wstrb[25]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[25]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[25]), .O(app_wdf_mask[25])); (* SOFT_HLUTNM = "soft_lutpair1479" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[26]_i_1 (.I0(s_axi_wstrb[26]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[26]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[26]), .O(app_wdf_mask[26])); (* SOFT_HLUTNM = "soft_lutpair1480" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[27]_i_1 (.I0(s_axi_wstrb[27]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[27]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[27]), .O(app_wdf_mask[27])); (* SOFT_HLUTNM = "soft_lutpair1481" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[28]_i_1 (.I0(s_axi_wstrb[28]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[28]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[28]), .O(app_wdf_mask[28])); (* SOFT_HLUTNM = "soft_lutpair1482" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[29]_i_1 (.I0(s_axi_wstrb[29]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[29]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[29]), .O(app_wdf_mask[29])); (* SOFT_HLUTNM = "soft_lutpair1455" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[2]_i_1 (.I0(s_axi_wstrb[2]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[2]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[2]), .O(app_wdf_mask[2])); (* SOFT_HLUTNM = "soft_lutpair1483" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[30]_i_1 (.I0(s_axi_wstrb[30]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[30]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[30]), .O(app_wdf_mask[30])); (* SOFT_HLUTNM = "soft_lutpair1484" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[31]_i_1 (.I0(s_axi_wstrb[31]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[31]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[31]), .O(app_wdf_mask[31])); (* SOFT_HLUTNM = "soft_lutpair1456" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[3]_i_1 (.I0(s_axi_wstrb[3]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[3]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[3]), .O(app_wdf_mask[3])); (* SOFT_HLUTNM = "soft_lutpair1457" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[4]_i_1 (.I0(s_axi_wstrb[4]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[4]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[4]), .O(app_wdf_mask[4])); (* SOFT_HLUTNM = "soft_lutpair1458" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[5]_i_1 (.I0(s_axi_wstrb[5]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[5]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[5]), .O(app_wdf_mask[5])); (* SOFT_HLUTNM = "soft_lutpair1459" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[6]_i_1 (.I0(s_axi_wstrb[6]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[6]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[6]), .O(app_wdf_mask[6])); (* SOFT_HLUTNM = "soft_lutpair1460" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[7]_i_1 (.I0(s_axi_wstrb[7]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[7]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[7]), .O(app_wdf_mask[7])); (* SOFT_HLUTNM = "soft_lutpair1461" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[8]_i_1 (.I0(s_axi_wstrb[8]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[8]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[8]), .O(app_wdf_mask[8])); (* SOFT_HLUTNM = "soft_lutpair1462" *) LUT5 #( .INIT(32'h74FF7400)) \app_wdf_mask_r1[9]_i_1 (.I0(s_axi_wstrb[9]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[9]), .I3(app_wdf_rdy), .I4(mc_app_wdf_mask_reg[9]), .O(app_wdf_mask[9])); (* SOFT_HLUTNM = "soft_lutpair1485" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[0]_i_1 (.I0(s_axi_wdata[0]), .I1(s_axi_wready), .I2(wdf_data[0]), .O(\mc_app_wdf_data_reg_reg[255]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair1297" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[100]_i_1 (.I0(s_axi_wdata[100]), .I1(wready_reg_rep_n_0), .I2(wdf_data[100]), .O(\mc_app_wdf_data_reg_reg[255]_0 [100])); (* SOFT_HLUTNM = "soft_lutpair1298" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[101]_i_1 (.I0(s_axi_wdata[101]), .I1(wready_reg_rep_n_0), .I2(wdf_data[101]), .O(\mc_app_wdf_data_reg_reg[255]_0 [101])); (* SOFT_HLUTNM = "soft_lutpair1299" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[102]_i_1 (.I0(s_axi_wdata[102]), .I1(wready_reg_rep_n_0), .I2(wdf_data[102]), .O(\mc_app_wdf_data_reg_reg[255]_0 [102])); (* SOFT_HLUTNM = "soft_lutpair1300" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[103]_i_1 (.I0(s_axi_wdata[103]), .I1(wready_reg_rep_n_0), .I2(wdf_data[103]), .O(\mc_app_wdf_data_reg_reg[255]_0 [103])); (* SOFT_HLUTNM = "soft_lutpair1301" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[104]_i_1 (.I0(s_axi_wdata[104]), .I1(wready_reg_rep_n_0), .I2(wdf_data[104]), .O(\mc_app_wdf_data_reg_reg[255]_0 [104])); (* SOFT_HLUTNM = "soft_lutpair1302" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[105]_i_1 (.I0(s_axi_wdata[105]), .I1(wready_reg_rep_n_0), .I2(wdf_data[105]), .O(\mc_app_wdf_data_reg_reg[255]_0 [105])); (* SOFT_HLUTNM = "soft_lutpair1303" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[106]_i_1 (.I0(s_axi_wdata[106]), .I1(wready_reg_rep_n_0), .I2(wdf_data[106]), .O(\mc_app_wdf_data_reg_reg[255]_0 [106])); (* SOFT_HLUTNM = "soft_lutpair1304" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[107]_i_1 (.I0(s_axi_wdata[107]), .I1(wready_reg_rep_n_0), .I2(wdf_data[107]), .O(\mc_app_wdf_data_reg_reg[255]_0 [107])); (* SOFT_HLUTNM = "soft_lutpair1305" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[108]_i_1 (.I0(s_axi_wdata[108]), .I1(wready_reg_rep_n_0), .I2(wdf_data[108]), .O(\mc_app_wdf_data_reg_reg[255]_0 [108])); (* SOFT_HLUTNM = "soft_lutpair1306" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[109]_i_1 (.I0(s_axi_wdata[109]), .I1(wready_reg_rep_n_0), .I2(wdf_data[109]), .O(\mc_app_wdf_data_reg_reg[255]_0 [109])); (* SOFT_HLUTNM = "soft_lutpair1207" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[10]_i_1 (.I0(s_axi_wdata[10]), .I1(s_axi_wready), .I2(wdf_data[10]), .O(\mc_app_wdf_data_reg_reg[255]_0 [10])); (* SOFT_HLUTNM = "soft_lutpair1307" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[110]_i_1 (.I0(s_axi_wdata[110]), .I1(wready_reg_rep_n_0), .I2(wdf_data[110]), .O(\mc_app_wdf_data_reg_reg[255]_0 [110])); (* SOFT_HLUTNM = "soft_lutpair1308" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[111]_i_1 (.I0(s_axi_wdata[111]), .I1(wready_reg_rep_n_0), .I2(wdf_data[111]), .O(\mc_app_wdf_data_reg_reg[255]_0 [111])); (* SOFT_HLUTNM = "soft_lutpair1309" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[112]_i_1 (.I0(s_axi_wdata[112]), .I1(wready_reg_rep_n_0), .I2(wdf_data[112]), .O(\mc_app_wdf_data_reg_reg[255]_0 [112])); (* SOFT_HLUTNM = "soft_lutpair1310" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[113]_i_1 (.I0(s_axi_wdata[113]), .I1(wready_reg_rep_n_0), .I2(wdf_data[113]), .O(\mc_app_wdf_data_reg_reg[255]_0 [113])); (* SOFT_HLUTNM = "soft_lutpair1311" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[114]_i_1 (.I0(s_axi_wdata[114]), .I1(wready_reg_rep_n_0), .I2(wdf_data[114]), .O(\mc_app_wdf_data_reg_reg[255]_0 [114])); (* SOFT_HLUTNM = "soft_lutpair1312" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[115]_i_1 (.I0(s_axi_wdata[115]), .I1(wready_reg_rep_n_0), .I2(wdf_data[115]), .O(\mc_app_wdf_data_reg_reg[255]_0 [115])); (* SOFT_HLUTNM = "soft_lutpair1313" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[116]_i_1 (.I0(s_axi_wdata[116]), .I1(wready_reg_rep_n_0), .I2(wdf_data[116]), .O(\mc_app_wdf_data_reg_reg[255]_0 [116])); (* SOFT_HLUTNM = "soft_lutpair1314" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[117]_i_1 (.I0(s_axi_wdata[117]), .I1(wready_reg_rep_n_0), .I2(wdf_data[117]), .O(\mc_app_wdf_data_reg_reg[255]_0 [117])); (* SOFT_HLUTNM = "soft_lutpair1315" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[118]_i_1 (.I0(s_axi_wdata[118]), .I1(wready_reg_rep_n_0), .I2(wdf_data[118]), .O(\mc_app_wdf_data_reg_reg[255]_0 [118])); (* SOFT_HLUTNM = "soft_lutpair1316" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[119]_i_1 (.I0(s_axi_wdata[119]), .I1(wready_reg_rep_n_0), .I2(wdf_data[119]), .O(\mc_app_wdf_data_reg_reg[255]_0 [119])); (* SOFT_HLUTNM = "soft_lutpair1208" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[11]_i_1 (.I0(s_axi_wdata[11]), .I1(s_axi_wready), .I2(wdf_data[11]), .O(\mc_app_wdf_data_reg_reg[255]_0 [11])); (* SOFT_HLUTNM = "soft_lutpair1317" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[120]_i_1 (.I0(s_axi_wdata[120]), .I1(wready_reg_rep_n_0), .I2(wdf_data[120]), .O(\mc_app_wdf_data_reg_reg[255]_0 [120])); (* SOFT_HLUTNM = "soft_lutpair1318" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[121]_i_1 (.I0(s_axi_wdata[121]), .I1(wready_reg_rep_n_0), .I2(wdf_data[121]), .O(\mc_app_wdf_data_reg_reg[255]_0 [121])); (* SOFT_HLUTNM = "soft_lutpair1319" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[122]_i_1 (.I0(s_axi_wdata[122]), .I1(wready_reg_rep_n_0), .I2(wdf_data[122]), .O(\mc_app_wdf_data_reg_reg[255]_0 [122])); (* SOFT_HLUTNM = "soft_lutpair1320" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[123]_i_1 (.I0(s_axi_wdata[123]), .I1(wready_reg_rep_n_0), .I2(wdf_data[123]), .O(\mc_app_wdf_data_reg_reg[255]_0 [123])); (* SOFT_HLUTNM = "soft_lutpair1321" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[124]_i_1 (.I0(s_axi_wdata[124]), .I1(wready_reg_rep_n_0), .I2(wdf_data[124]), .O(\mc_app_wdf_data_reg_reg[255]_0 [124])); (* SOFT_HLUTNM = "soft_lutpair1322" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[125]_i_1 (.I0(s_axi_wdata[125]), .I1(wready_reg_rep_n_0), .I2(wdf_data[125]), .O(\mc_app_wdf_data_reg_reg[255]_0 [125])); (* SOFT_HLUTNM = "soft_lutpair1323" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[126]_i_1 (.I0(s_axi_wdata[126]), .I1(wready_reg_rep_n_0), .I2(wdf_data[126]), .O(\mc_app_wdf_data_reg_reg[255]_0 [126])); (* SOFT_HLUTNM = "soft_lutpair1324" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[127]_i_1 (.I0(s_axi_wdata[127]), .I1(wready_reg_rep_n_0), .I2(wdf_data[127]), .O(\mc_app_wdf_data_reg_reg[255]_0 [127])); (* SOFT_HLUTNM = "soft_lutpair1325" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[128]_i_1 (.I0(s_axi_wdata[128]), .I1(wready_reg_rep_n_0), .I2(wdf_data[128]), .O(\mc_app_wdf_data_reg_reg[255]_0 [128])); (* SOFT_HLUTNM = "soft_lutpair1326" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[129]_i_1 (.I0(s_axi_wdata[129]), .I1(wready_reg_rep_n_0), .I2(wdf_data[129]), .O(\mc_app_wdf_data_reg_reg[255]_0 [129])); (* SOFT_HLUTNM = "soft_lutpair1209" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[12]_i_1 (.I0(s_axi_wdata[12]), .I1(s_axi_wready), .I2(wdf_data[12]), .O(\mc_app_wdf_data_reg_reg[255]_0 [12])); (* SOFT_HLUTNM = "soft_lutpair1327" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[130]_i_1 (.I0(s_axi_wdata[130]), .I1(wready_reg_rep_n_0), .I2(wdf_data[130]), .O(\mc_app_wdf_data_reg_reg[255]_0 [130])); (* SOFT_HLUTNM = "soft_lutpair1328" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[131]_i_1 (.I0(s_axi_wdata[131]), .I1(wready_reg_rep_n_0), .I2(wdf_data[131]), .O(\mc_app_wdf_data_reg_reg[255]_0 [131])); (* SOFT_HLUTNM = "soft_lutpair1329" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[132]_i_1 (.I0(s_axi_wdata[132]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[132]), .O(\mc_app_wdf_data_reg_reg[255]_0 [132])); (* SOFT_HLUTNM = "soft_lutpair1330" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[133]_i_1 (.I0(s_axi_wdata[133]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[133]), .O(\mc_app_wdf_data_reg_reg[255]_0 [133])); (* SOFT_HLUTNM = "soft_lutpair1331" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[134]_i_1 (.I0(s_axi_wdata[134]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[134]), .O(\mc_app_wdf_data_reg_reg[255]_0 [134])); (* SOFT_HLUTNM = "soft_lutpair1332" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[135]_i_1 (.I0(s_axi_wdata[135]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[135]), .O(\mc_app_wdf_data_reg_reg[255]_0 [135])); (* SOFT_HLUTNM = "soft_lutpair1333" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[136]_i_1 (.I0(s_axi_wdata[136]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[136]), .O(\mc_app_wdf_data_reg_reg[255]_0 [136])); (* SOFT_HLUTNM = "soft_lutpair1334" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[137]_i_1 (.I0(s_axi_wdata[137]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[137]), .O(\mc_app_wdf_data_reg_reg[255]_0 [137])); (* SOFT_HLUTNM = "soft_lutpair1335" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[138]_i_1 (.I0(s_axi_wdata[138]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[138]), .O(\mc_app_wdf_data_reg_reg[255]_0 [138])); (* SOFT_HLUTNM = "soft_lutpair1336" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[139]_i_1 (.I0(s_axi_wdata[139]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[139]), .O(\mc_app_wdf_data_reg_reg[255]_0 [139])); (* SOFT_HLUTNM = "soft_lutpair1210" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[13]_i_1 (.I0(s_axi_wdata[13]), .I1(s_axi_wready), .I2(wdf_data[13]), .O(\mc_app_wdf_data_reg_reg[255]_0 [13])); (* SOFT_HLUTNM = "soft_lutpair1337" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[140]_i_1 (.I0(s_axi_wdata[140]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[140]), .O(\mc_app_wdf_data_reg_reg[255]_0 [140])); (* SOFT_HLUTNM = "soft_lutpair1338" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[141]_i_1 (.I0(s_axi_wdata[141]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[141]), .O(\mc_app_wdf_data_reg_reg[255]_0 [141])); (* SOFT_HLUTNM = "soft_lutpair1339" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[142]_i_1 (.I0(s_axi_wdata[142]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[142]), .O(\mc_app_wdf_data_reg_reg[255]_0 [142])); (* SOFT_HLUTNM = "soft_lutpair1340" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[143]_i_1 (.I0(s_axi_wdata[143]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[143]), .O(\mc_app_wdf_data_reg_reg[255]_0 [143])); (* SOFT_HLUTNM = "soft_lutpair1341" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[144]_i_1 (.I0(s_axi_wdata[144]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[144]), .O(\mc_app_wdf_data_reg_reg[255]_0 [144])); (* SOFT_HLUTNM = "soft_lutpair1342" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[145]_i_1 (.I0(s_axi_wdata[145]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[145]), .O(\mc_app_wdf_data_reg_reg[255]_0 [145])); (* SOFT_HLUTNM = "soft_lutpair1343" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[146]_i_1 (.I0(s_axi_wdata[146]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[146]), .O(\mc_app_wdf_data_reg_reg[255]_0 [146])); (* SOFT_HLUTNM = "soft_lutpair1344" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[147]_i_1 (.I0(s_axi_wdata[147]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[147]), .O(\mc_app_wdf_data_reg_reg[255]_0 [147])); (* SOFT_HLUTNM = "soft_lutpair1345" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[148]_i_1 (.I0(s_axi_wdata[148]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[148]), .O(\mc_app_wdf_data_reg_reg[255]_0 [148])); (* SOFT_HLUTNM = "soft_lutpair1346" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[149]_i_1 (.I0(s_axi_wdata[149]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[149]), .O(\mc_app_wdf_data_reg_reg[255]_0 [149])); (* SOFT_HLUTNM = "soft_lutpair1211" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[14]_i_1 (.I0(s_axi_wdata[14]), .I1(s_axi_wready), .I2(wdf_data[14]), .O(\mc_app_wdf_data_reg_reg[255]_0 [14])); (* SOFT_HLUTNM = "soft_lutpair1347" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[150]_i_1 (.I0(s_axi_wdata[150]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[150]), .O(\mc_app_wdf_data_reg_reg[255]_0 [150])); (* SOFT_HLUTNM = "soft_lutpair1348" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[151]_i_1 (.I0(s_axi_wdata[151]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[151]), .O(\mc_app_wdf_data_reg_reg[255]_0 [151])); (* SOFT_HLUTNM = "soft_lutpair1349" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[152]_i_1 (.I0(s_axi_wdata[152]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[152]), .O(\mc_app_wdf_data_reg_reg[255]_0 [152])); (* SOFT_HLUTNM = "soft_lutpair1350" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[153]_i_1 (.I0(s_axi_wdata[153]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[153]), .O(\mc_app_wdf_data_reg_reg[255]_0 [153])); (* SOFT_HLUTNM = "soft_lutpair1351" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[154]_i_1 (.I0(s_axi_wdata[154]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[154]), .O(\mc_app_wdf_data_reg_reg[255]_0 [154])); (* SOFT_HLUTNM = "soft_lutpair1352" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[155]_i_1 (.I0(s_axi_wdata[155]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[155]), .O(\mc_app_wdf_data_reg_reg[255]_0 [155])); (* SOFT_HLUTNM = "soft_lutpair1353" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[156]_i_1 (.I0(s_axi_wdata[156]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[156]), .O(\mc_app_wdf_data_reg_reg[255]_0 [156])); (* SOFT_HLUTNM = "soft_lutpair1354" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[157]_i_1 (.I0(s_axi_wdata[157]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[157]), .O(\mc_app_wdf_data_reg_reg[255]_0 [157])); (* SOFT_HLUTNM = "soft_lutpair1355" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[158]_i_1 (.I0(s_axi_wdata[158]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[158]), .O(\mc_app_wdf_data_reg_reg[255]_0 [158])); (* SOFT_HLUTNM = "soft_lutpair1356" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[159]_i_1 (.I0(s_axi_wdata[159]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[159]), .O(\mc_app_wdf_data_reg_reg[255]_0 [159])); (* SOFT_HLUTNM = "soft_lutpair1212" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[15]_i_1 (.I0(s_axi_wdata[15]), .I1(s_axi_wready), .I2(wdf_data[15]), .O(\mc_app_wdf_data_reg_reg[255]_0 [15])); (* SOFT_HLUTNM = "soft_lutpair1357" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[160]_i_1 (.I0(s_axi_wdata[160]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[160]), .O(\mc_app_wdf_data_reg_reg[255]_0 [160])); (* SOFT_HLUTNM = "soft_lutpair1358" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[161]_i_1 (.I0(s_axi_wdata[161]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[161]), .O(\mc_app_wdf_data_reg_reg[255]_0 [161])); (* SOFT_HLUTNM = "soft_lutpair1359" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[162]_i_1 (.I0(s_axi_wdata[162]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[162]), .O(\mc_app_wdf_data_reg_reg[255]_0 [162])); (* SOFT_HLUTNM = "soft_lutpair1360" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[163]_i_1 (.I0(s_axi_wdata[163]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[163]), .O(\mc_app_wdf_data_reg_reg[255]_0 [163])); (* SOFT_HLUTNM = "soft_lutpair1361" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[164]_i_1 (.I0(s_axi_wdata[164]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[164]), .O(\mc_app_wdf_data_reg_reg[255]_0 [164])); (* SOFT_HLUTNM = "soft_lutpair1362" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[165]_i_1 (.I0(s_axi_wdata[165]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[165]), .O(\mc_app_wdf_data_reg_reg[255]_0 [165])); (* SOFT_HLUTNM = "soft_lutpair1363" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[166]_i_1 (.I0(s_axi_wdata[166]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[166]), .O(\mc_app_wdf_data_reg_reg[255]_0 [166])); (* SOFT_HLUTNM = "soft_lutpair1364" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[167]_i_1 (.I0(s_axi_wdata[167]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[167]), .O(\mc_app_wdf_data_reg_reg[255]_0 [167])); (* SOFT_HLUTNM = "soft_lutpair1365" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[168]_i_1 (.I0(s_axi_wdata[168]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[168]), .O(\mc_app_wdf_data_reg_reg[255]_0 [168])); (* SOFT_HLUTNM = "soft_lutpair1366" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[169]_i_1 (.I0(s_axi_wdata[169]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[169]), .O(\mc_app_wdf_data_reg_reg[255]_0 [169])); (* SOFT_HLUTNM = "soft_lutpair1213" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[16]_i_1 (.I0(s_axi_wdata[16]), .I1(s_axi_wready), .I2(wdf_data[16]), .O(\mc_app_wdf_data_reg_reg[255]_0 [16])); (* SOFT_HLUTNM = "soft_lutpair1367" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[170]_i_1 (.I0(s_axi_wdata[170]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[170]), .O(\mc_app_wdf_data_reg_reg[255]_0 [170])); (* SOFT_HLUTNM = "soft_lutpair1368" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[171]_i_1 (.I0(s_axi_wdata[171]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[171]), .O(\mc_app_wdf_data_reg_reg[255]_0 [171])); (* SOFT_HLUTNM = "soft_lutpair1369" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[172]_i_1 (.I0(s_axi_wdata[172]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[172]), .O(\mc_app_wdf_data_reg_reg[255]_0 [172])); (* SOFT_HLUTNM = "soft_lutpair1370" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[173]_i_1 (.I0(s_axi_wdata[173]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[173]), .O(\mc_app_wdf_data_reg_reg[255]_0 [173])); (* SOFT_HLUTNM = "soft_lutpair1371" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[174]_i_1 (.I0(s_axi_wdata[174]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[174]), .O(\mc_app_wdf_data_reg_reg[255]_0 [174])); (* SOFT_HLUTNM = "soft_lutpair1372" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[175]_i_1 (.I0(s_axi_wdata[175]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[175]), .O(\mc_app_wdf_data_reg_reg[255]_0 [175])); (* SOFT_HLUTNM = "soft_lutpair1373" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[176]_i_1 (.I0(s_axi_wdata[176]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[176]), .O(\mc_app_wdf_data_reg_reg[255]_0 [176])); (* SOFT_HLUTNM = "soft_lutpair1374" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[177]_i_1 (.I0(s_axi_wdata[177]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[177]), .O(\mc_app_wdf_data_reg_reg[255]_0 [177])); (* SOFT_HLUTNM = "soft_lutpair1375" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[178]_i_1 (.I0(s_axi_wdata[178]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[178]), .O(\mc_app_wdf_data_reg_reg[255]_0 [178])); (* SOFT_HLUTNM = "soft_lutpair1376" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[179]_i_1 (.I0(s_axi_wdata[179]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[179]), .O(\mc_app_wdf_data_reg_reg[255]_0 [179])); (* SOFT_HLUTNM = "soft_lutpair1214" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[17]_i_1 (.I0(s_axi_wdata[17]), .I1(s_axi_wready), .I2(wdf_data[17]), .O(\mc_app_wdf_data_reg_reg[255]_0 [17])); (* SOFT_HLUTNM = "soft_lutpair1377" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[180]_i_1 (.I0(s_axi_wdata[180]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[180]), .O(\mc_app_wdf_data_reg_reg[255]_0 [180])); (* SOFT_HLUTNM = "soft_lutpair1378" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[181]_i_1 (.I0(s_axi_wdata[181]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[181]), .O(\mc_app_wdf_data_reg_reg[255]_0 [181])); (* SOFT_HLUTNM = "soft_lutpair1379" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[182]_i_1 (.I0(s_axi_wdata[182]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[182]), .O(\mc_app_wdf_data_reg_reg[255]_0 [182])); (* SOFT_HLUTNM = "soft_lutpair1380" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[183]_i_1 (.I0(s_axi_wdata[183]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[183]), .O(\mc_app_wdf_data_reg_reg[255]_0 [183])); (* SOFT_HLUTNM = "soft_lutpair1381" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[184]_i_1 (.I0(s_axi_wdata[184]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[184]), .O(\mc_app_wdf_data_reg_reg[255]_0 [184])); (* SOFT_HLUTNM = "soft_lutpair1382" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[185]_i_1 (.I0(s_axi_wdata[185]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[185]), .O(\mc_app_wdf_data_reg_reg[255]_0 [185])); (* SOFT_HLUTNM = "soft_lutpair1383" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[186]_i_1 (.I0(s_axi_wdata[186]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[186]), .O(\mc_app_wdf_data_reg_reg[255]_0 [186])); (* SOFT_HLUTNM = "soft_lutpair1384" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[187]_i_1 (.I0(s_axi_wdata[187]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[187]), .O(\mc_app_wdf_data_reg_reg[255]_0 [187])); (* SOFT_HLUTNM = "soft_lutpair1385" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[188]_i_1 (.I0(s_axi_wdata[188]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[188]), .O(\mc_app_wdf_data_reg_reg[255]_0 [188])); (* SOFT_HLUTNM = "soft_lutpair1386" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[189]_i_1 (.I0(s_axi_wdata[189]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[189]), .O(\mc_app_wdf_data_reg_reg[255]_0 [189])); (* SOFT_HLUTNM = "soft_lutpair1215" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[18]_i_1 (.I0(s_axi_wdata[18]), .I1(s_axi_wready), .I2(wdf_data[18]), .O(\mc_app_wdf_data_reg_reg[255]_0 [18])); (* SOFT_HLUTNM = "soft_lutpair1387" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[190]_i_1 (.I0(s_axi_wdata[190]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[190]), .O(\mc_app_wdf_data_reg_reg[255]_0 [190])); (* SOFT_HLUTNM = "soft_lutpair1388" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[191]_i_1 (.I0(s_axi_wdata[191]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[191]), .O(\mc_app_wdf_data_reg_reg[255]_0 [191])); (* SOFT_HLUTNM = "soft_lutpair1389" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[192]_i_1 (.I0(s_axi_wdata[192]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[192]), .O(\mc_app_wdf_data_reg_reg[255]_0 [192])); (* SOFT_HLUTNM = "soft_lutpair1390" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[193]_i_1 (.I0(s_axi_wdata[193]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[193]), .O(\mc_app_wdf_data_reg_reg[255]_0 [193])); (* SOFT_HLUTNM = "soft_lutpair1391" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[194]_i_1 (.I0(s_axi_wdata[194]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[194]), .O(\mc_app_wdf_data_reg_reg[255]_0 [194])); (* SOFT_HLUTNM = "soft_lutpair1392" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[195]_i_1 (.I0(s_axi_wdata[195]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[195]), .O(\mc_app_wdf_data_reg_reg[255]_0 [195])); (* SOFT_HLUTNM = "soft_lutpair1393" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[196]_i_1 (.I0(s_axi_wdata[196]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[196]), .O(\mc_app_wdf_data_reg_reg[255]_0 [196])); (* SOFT_HLUTNM = "soft_lutpair1394" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[197]_i_1 (.I0(s_axi_wdata[197]), .I1(wready_reg_rep__0_n_0), .I2(wdf_data[197]), .O(\mc_app_wdf_data_reg_reg[255]_0 [197])); (* SOFT_HLUTNM = "soft_lutpair1395" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[198]_i_1 (.I0(s_axi_wdata[198]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[198]), .O(\mc_app_wdf_data_reg_reg[255]_0 [198])); (* SOFT_HLUTNM = "soft_lutpair1396" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[199]_i_1 (.I0(s_axi_wdata[199]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[199]), .O(\mc_app_wdf_data_reg_reg[255]_0 [199])); (* SOFT_HLUTNM = "soft_lutpair1216" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[19]_i_1 (.I0(s_axi_wdata[19]), .I1(s_axi_wready), .I2(wdf_data[19]), .O(\mc_app_wdf_data_reg_reg[255]_0 [19])); (* SOFT_HLUTNM = "soft_lutpair1198" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[1]_i_1 (.I0(s_axi_wdata[1]), .I1(s_axi_wready), .I2(wdf_data[1]), .O(\mc_app_wdf_data_reg_reg[255]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair1397" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[200]_i_1 (.I0(s_axi_wdata[200]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[200]), .O(\mc_app_wdf_data_reg_reg[255]_0 [200])); (* SOFT_HLUTNM = "soft_lutpair1398" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[201]_i_1 (.I0(s_axi_wdata[201]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[201]), .O(\mc_app_wdf_data_reg_reg[255]_0 [201])); (* SOFT_HLUTNM = "soft_lutpair1399" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[202]_i_1 (.I0(s_axi_wdata[202]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[202]), .O(\mc_app_wdf_data_reg_reg[255]_0 [202])); (* SOFT_HLUTNM = "soft_lutpair1400" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[203]_i_1 (.I0(s_axi_wdata[203]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[203]), .O(\mc_app_wdf_data_reg_reg[255]_0 [203])); (* SOFT_HLUTNM = "soft_lutpair1401" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[204]_i_1 (.I0(s_axi_wdata[204]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[204]), .O(\mc_app_wdf_data_reg_reg[255]_0 [204])); (* SOFT_HLUTNM = "soft_lutpair1402" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[205]_i_1 (.I0(s_axi_wdata[205]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[205]), .O(\mc_app_wdf_data_reg_reg[255]_0 [205])); (* SOFT_HLUTNM = "soft_lutpair1403" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[206]_i_1 (.I0(s_axi_wdata[206]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[206]), .O(\mc_app_wdf_data_reg_reg[255]_0 [206])); (* SOFT_HLUTNM = "soft_lutpair1404" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[207]_i_1 (.I0(s_axi_wdata[207]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[207]), .O(\mc_app_wdf_data_reg_reg[255]_0 [207])); (* SOFT_HLUTNM = "soft_lutpair1405" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[208]_i_1 (.I0(s_axi_wdata[208]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[208]), .O(\mc_app_wdf_data_reg_reg[255]_0 [208])); (* SOFT_HLUTNM = "soft_lutpair1406" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[209]_i_1 (.I0(s_axi_wdata[209]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[209]), .O(\mc_app_wdf_data_reg_reg[255]_0 [209])); (* SOFT_HLUTNM = "soft_lutpair1217" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[20]_i_1 (.I0(s_axi_wdata[20]), .I1(s_axi_wready), .I2(wdf_data[20]), .O(\mc_app_wdf_data_reg_reg[255]_0 [20])); (* SOFT_HLUTNM = "soft_lutpair1407" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[210]_i_1 (.I0(s_axi_wdata[210]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[210]), .O(\mc_app_wdf_data_reg_reg[255]_0 [210])); (* SOFT_HLUTNM = "soft_lutpair1408" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[211]_i_1 (.I0(s_axi_wdata[211]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[211]), .O(\mc_app_wdf_data_reg_reg[255]_0 [211])); (* SOFT_HLUTNM = "soft_lutpair1409" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[212]_i_1 (.I0(s_axi_wdata[212]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[212]), .O(\mc_app_wdf_data_reg_reg[255]_0 [212])); (* SOFT_HLUTNM = "soft_lutpair1410" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[213]_i_1 (.I0(s_axi_wdata[213]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[213]), .O(\mc_app_wdf_data_reg_reg[255]_0 [213])); (* SOFT_HLUTNM = "soft_lutpair1411" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[214]_i_1 (.I0(s_axi_wdata[214]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[214]), .O(\mc_app_wdf_data_reg_reg[255]_0 [214])); (* SOFT_HLUTNM = "soft_lutpair1412" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[215]_i_1 (.I0(s_axi_wdata[215]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[215]), .O(\mc_app_wdf_data_reg_reg[255]_0 [215])); (* SOFT_HLUTNM = "soft_lutpair1413" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[216]_i_1 (.I0(s_axi_wdata[216]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[216]), .O(\mc_app_wdf_data_reg_reg[255]_0 [216])); (* SOFT_HLUTNM = "soft_lutpair1414" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[217]_i_1 (.I0(s_axi_wdata[217]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[217]), .O(\mc_app_wdf_data_reg_reg[255]_0 [217])); (* SOFT_HLUTNM = "soft_lutpair1415" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[218]_i_1 (.I0(s_axi_wdata[218]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[218]), .O(\mc_app_wdf_data_reg_reg[255]_0 [218])); (* SOFT_HLUTNM = "soft_lutpair1416" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[219]_i_1 (.I0(s_axi_wdata[219]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[219]), .O(\mc_app_wdf_data_reg_reg[255]_0 [219])); (* SOFT_HLUTNM = "soft_lutpair1218" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[21]_i_1 (.I0(s_axi_wdata[21]), .I1(s_axi_wready), .I2(wdf_data[21]), .O(\mc_app_wdf_data_reg_reg[255]_0 [21])); (* SOFT_HLUTNM = "soft_lutpair1417" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[220]_i_1 (.I0(s_axi_wdata[220]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[220]), .O(\mc_app_wdf_data_reg_reg[255]_0 [220])); (* SOFT_HLUTNM = "soft_lutpair1418" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[221]_i_1 (.I0(s_axi_wdata[221]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[221]), .O(\mc_app_wdf_data_reg_reg[255]_0 [221])); (* SOFT_HLUTNM = "soft_lutpair1419" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[222]_i_1 (.I0(s_axi_wdata[222]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[222]), .O(\mc_app_wdf_data_reg_reg[255]_0 [222])); (* SOFT_HLUTNM = "soft_lutpair1420" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[223]_i_1 (.I0(s_axi_wdata[223]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[223]), .O(\mc_app_wdf_data_reg_reg[255]_0 [223])); (* SOFT_HLUTNM = "soft_lutpair1421" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[224]_i_1 (.I0(s_axi_wdata[224]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[224]), .O(\mc_app_wdf_data_reg_reg[255]_0 [224])); (* SOFT_HLUTNM = "soft_lutpair1422" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[225]_i_1 (.I0(s_axi_wdata[225]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[225]), .O(\mc_app_wdf_data_reg_reg[255]_0 [225])); (* SOFT_HLUTNM = "soft_lutpair1423" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[226]_i_1 (.I0(s_axi_wdata[226]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[226]), .O(\mc_app_wdf_data_reg_reg[255]_0 [226])); (* SOFT_HLUTNM = "soft_lutpair1424" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[227]_i_1 (.I0(s_axi_wdata[227]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[227]), .O(\mc_app_wdf_data_reg_reg[255]_0 [227])); (* SOFT_HLUTNM = "soft_lutpair1425" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[228]_i_1 (.I0(s_axi_wdata[228]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[228]), .O(\mc_app_wdf_data_reg_reg[255]_0 [228])); (* SOFT_HLUTNM = "soft_lutpair1426" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[229]_i_1 (.I0(s_axi_wdata[229]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[229]), .O(\mc_app_wdf_data_reg_reg[255]_0 [229])); (* SOFT_HLUTNM = "soft_lutpair1219" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[22]_i_1 (.I0(s_axi_wdata[22]), .I1(s_axi_wready), .I2(wdf_data[22]), .O(\mc_app_wdf_data_reg_reg[255]_0 [22])); (* SOFT_HLUTNM = "soft_lutpair1427" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[230]_i_1 (.I0(s_axi_wdata[230]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[230]), .O(\mc_app_wdf_data_reg_reg[255]_0 [230])); (* SOFT_HLUTNM = "soft_lutpair1428" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[231]_i_1 (.I0(s_axi_wdata[231]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[231]), .O(\mc_app_wdf_data_reg_reg[255]_0 [231])); (* SOFT_HLUTNM = "soft_lutpair1429" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[232]_i_1 (.I0(s_axi_wdata[232]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[232]), .O(\mc_app_wdf_data_reg_reg[255]_0 [232])); (* SOFT_HLUTNM = "soft_lutpair1430" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[233]_i_1 (.I0(s_axi_wdata[233]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[233]), .O(\mc_app_wdf_data_reg_reg[255]_0 [233])); (* SOFT_HLUTNM = "soft_lutpair1431" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[234]_i_1 (.I0(s_axi_wdata[234]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[234]), .O(\mc_app_wdf_data_reg_reg[255]_0 [234])); (* SOFT_HLUTNM = "soft_lutpair1432" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[235]_i_1 (.I0(s_axi_wdata[235]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[235]), .O(\mc_app_wdf_data_reg_reg[255]_0 [235])); (* SOFT_HLUTNM = "soft_lutpair1433" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[236]_i_1 (.I0(s_axi_wdata[236]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[236]), .O(\mc_app_wdf_data_reg_reg[255]_0 [236])); (* SOFT_HLUTNM = "soft_lutpair1434" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[237]_i_1 (.I0(s_axi_wdata[237]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[237]), .O(\mc_app_wdf_data_reg_reg[255]_0 [237])); (* SOFT_HLUTNM = "soft_lutpair1435" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[238]_i_1 (.I0(s_axi_wdata[238]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[238]), .O(\mc_app_wdf_data_reg_reg[255]_0 [238])); (* SOFT_HLUTNM = "soft_lutpair1436" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[239]_i_1 (.I0(s_axi_wdata[239]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[239]), .O(\mc_app_wdf_data_reg_reg[255]_0 [239])); (* SOFT_HLUTNM = "soft_lutpair1220" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[23]_i_1 (.I0(s_axi_wdata[23]), .I1(s_axi_wready), .I2(wdf_data[23]), .O(\mc_app_wdf_data_reg_reg[255]_0 [23])); (* SOFT_HLUTNM = "soft_lutpair1437" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[240]_i_1 (.I0(s_axi_wdata[240]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[240]), .O(\mc_app_wdf_data_reg_reg[255]_0 [240])); (* SOFT_HLUTNM = "soft_lutpair1438" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[241]_i_1 (.I0(s_axi_wdata[241]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[241]), .O(\mc_app_wdf_data_reg_reg[255]_0 [241])); (* SOFT_HLUTNM = "soft_lutpair1439" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[242]_i_1 (.I0(s_axi_wdata[242]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[242]), .O(\mc_app_wdf_data_reg_reg[255]_0 [242])); (* SOFT_HLUTNM = "soft_lutpair1440" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[243]_i_1 (.I0(s_axi_wdata[243]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[243]), .O(\mc_app_wdf_data_reg_reg[255]_0 [243])); (* SOFT_HLUTNM = "soft_lutpair1441" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[244]_i_1 (.I0(s_axi_wdata[244]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[244]), .O(\mc_app_wdf_data_reg_reg[255]_0 [244])); (* SOFT_HLUTNM = "soft_lutpair1442" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[245]_i_1 (.I0(s_axi_wdata[245]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[245]), .O(\mc_app_wdf_data_reg_reg[255]_0 [245])); (* SOFT_HLUTNM = "soft_lutpair1443" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[246]_i_1 (.I0(s_axi_wdata[246]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[246]), .O(\mc_app_wdf_data_reg_reg[255]_0 [246])); (* SOFT_HLUTNM = "soft_lutpair1444" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[247]_i_1 (.I0(s_axi_wdata[247]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[247]), .O(\mc_app_wdf_data_reg_reg[255]_0 [247])); (* SOFT_HLUTNM = "soft_lutpair1445" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[248]_i_1 (.I0(s_axi_wdata[248]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[248]), .O(\mc_app_wdf_data_reg_reg[255]_0 [248])); (* SOFT_HLUTNM = "soft_lutpair1446" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[249]_i_1 (.I0(s_axi_wdata[249]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[249]), .O(\mc_app_wdf_data_reg_reg[255]_0 [249])); (* SOFT_HLUTNM = "soft_lutpair1221" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[24]_i_1 (.I0(s_axi_wdata[24]), .I1(s_axi_wready), .I2(wdf_data[24]), .O(\mc_app_wdf_data_reg_reg[255]_0 [24])); (* SOFT_HLUTNM = "soft_lutpair1447" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[250]_i_1 (.I0(s_axi_wdata[250]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[250]), .O(\mc_app_wdf_data_reg_reg[255]_0 [250])); (* SOFT_HLUTNM = "soft_lutpair1448" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[251]_i_1 (.I0(s_axi_wdata[251]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[251]), .O(\mc_app_wdf_data_reg_reg[255]_0 [251])); (* SOFT_HLUTNM = "soft_lutpair1449" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[252]_i_1 (.I0(s_axi_wdata[252]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[252]), .O(\mc_app_wdf_data_reg_reg[255]_0 [252])); (* SOFT_HLUTNM = "soft_lutpair1450" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[253]_i_1 (.I0(s_axi_wdata[253]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[253]), .O(\mc_app_wdf_data_reg_reg[255]_0 [253])); (* SOFT_HLUTNM = "soft_lutpair1451" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[254]_i_1 (.I0(s_axi_wdata[254]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[254]), .O(\mc_app_wdf_data_reg_reg[255]_0 [254])); (* SOFT_HLUTNM = "soft_lutpair1452" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[255]_i_1 (.I0(s_axi_wdata[255]), .I1(wready_reg_rep__1_n_0), .I2(wdf_data[255]), .O(\mc_app_wdf_data_reg_reg[255]_0 [255])); (* SOFT_HLUTNM = "soft_lutpair1222" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[25]_i_1 (.I0(s_axi_wdata[25]), .I1(s_axi_wready), .I2(wdf_data[25]), .O(\mc_app_wdf_data_reg_reg[255]_0 [25])); (* SOFT_HLUTNM = "soft_lutpair1223" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[26]_i_1 (.I0(s_axi_wdata[26]), .I1(s_axi_wready), .I2(wdf_data[26]), .O(\mc_app_wdf_data_reg_reg[255]_0 [26])); (* SOFT_HLUTNM = "soft_lutpair1224" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[27]_i_1 (.I0(s_axi_wdata[27]), .I1(s_axi_wready), .I2(wdf_data[27]), .O(\mc_app_wdf_data_reg_reg[255]_0 [27])); (* SOFT_HLUTNM = "soft_lutpair1225" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[28]_i_1 (.I0(s_axi_wdata[28]), .I1(s_axi_wready), .I2(wdf_data[28]), .O(\mc_app_wdf_data_reg_reg[255]_0 [28])); (* SOFT_HLUTNM = "soft_lutpair1226" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[29]_i_1 (.I0(s_axi_wdata[29]), .I1(s_axi_wready), .I2(wdf_data[29]), .O(\mc_app_wdf_data_reg_reg[255]_0 [29])); (* SOFT_HLUTNM = "soft_lutpair1199" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[2]_i_1 (.I0(s_axi_wdata[2]), .I1(s_axi_wready), .I2(wdf_data[2]), .O(\mc_app_wdf_data_reg_reg[255]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair1227" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[30]_i_1 (.I0(s_axi_wdata[30]), .I1(s_axi_wready), .I2(wdf_data[30]), .O(\mc_app_wdf_data_reg_reg[255]_0 [30])); (* SOFT_HLUTNM = "soft_lutpair1228" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[31]_i_1 (.I0(s_axi_wdata[31]), .I1(s_axi_wready), .I2(wdf_data[31]), .O(\mc_app_wdf_data_reg_reg[255]_0 [31])); (* SOFT_HLUTNM = "soft_lutpair1229" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[32]_i_1 (.I0(s_axi_wdata[32]), .I1(s_axi_wready), .I2(wdf_data[32]), .O(\mc_app_wdf_data_reg_reg[255]_0 [32])); (* SOFT_HLUTNM = "soft_lutpair1230" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[33]_i_1 (.I0(s_axi_wdata[33]), .I1(s_axi_wready), .I2(wdf_data[33]), .O(\mc_app_wdf_data_reg_reg[255]_0 [33])); (* SOFT_HLUTNM = "soft_lutpair1231" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[34]_i_1 (.I0(s_axi_wdata[34]), .I1(s_axi_wready), .I2(wdf_data[34]), .O(\mc_app_wdf_data_reg_reg[255]_0 [34])); (* SOFT_HLUTNM = "soft_lutpair1232" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[35]_i_1 (.I0(s_axi_wdata[35]), .I1(s_axi_wready), .I2(wdf_data[35]), .O(\mc_app_wdf_data_reg_reg[255]_0 [35])); (* SOFT_HLUTNM = "soft_lutpair1233" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[36]_i_1 (.I0(s_axi_wdata[36]), .I1(s_axi_wready), .I2(wdf_data[36]), .O(\mc_app_wdf_data_reg_reg[255]_0 [36])); (* SOFT_HLUTNM = "soft_lutpair1234" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[37]_i_1 (.I0(s_axi_wdata[37]), .I1(s_axi_wready), .I2(wdf_data[37]), .O(\mc_app_wdf_data_reg_reg[255]_0 [37])); (* SOFT_HLUTNM = "soft_lutpair1235" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[38]_i_1 (.I0(s_axi_wdata[38]), .I1(s_axi_wready), .I2(wdf_data[38]), .O(\mc_app_wdf_data_reg_reg[255]_0 [38])); (* SOFT_HLUTNM = "soft_lutpair1236" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[39]_i_1 (.I0(s_axi_wdata[39]), .I1(s_axi_wready), .I2(wdf_data[39]), .O(\mc_app_wdf_data_reg_reg[255]_0 [39])); (* SOFT_HLUTNM = "soft_lutpair1200" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[3]_i_1 (.I0(s_axi_wdata[3]), .I1(s_axi_wready), .I2(wdf_data[3]), .O(\mc_app_wdf_data_reg_reg[255]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair1237" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[40]_i_1 (.I0(s_axi_wdata[40]), .I1(s_axi_wready), .I2(wdf_data[40]), .O(\mc_app_wdf_data_reg_reg[255]_0 [40])); (* SOFT_HLUTNM = "soft_lutpair1238" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[41]_i_1 (.I0(s_axi_wdata[41]), .I1(s_axi_wready), .I2(wdf_data[41]), .O(\mc_app_wdf_data_reg_reg[255]_0 [41])); (* SOFT_HLUTNM = "soft_lutpair1239" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[42]_i_1 (.I0(s_axi_wdata[42]), .I1(s_axi_wready), .I2(wdf_data[42]), .O(\mc_app_wdf_data_reg_reg[255]_0 [42])); (* SOFT_HLUTNM = "soft_lutpair1240" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[43]_i_1 (.I0(s_axi_wdata[43]), .I1(s_axi_wready), .I2(wdf_data[43]), .O(\mc_app_wdf_data_reg_reg[255]_0 [43])); (* SOFT_HLUTNM = "soft_lutpair1241" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[44]_i_1 (.I0(s_axi_wdata[44]), .I1(s_axi_wready), .I2(wdf_data[44]), .O(\mc_app_wdf_data_reg_reg[255]_0 [44])); (* SOFT_HLUTNM = "soft_lutpair1242" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[45]_i_1 (.I0(s_axi_wdata[45]), .I1(s_axi_wready), .I2(wdf_data[45]), .O(\mc_app_wdf_data_reg_reg[255]_0 [45])); (* SOFT_HLUTNM = "soft_lutpair1243" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[46]_i_1 (.I0(s_axi_wdata[46]), .I1(s_axi_wready), .I2(wdf_data[46]), .O(\mc_app_wdf_data_reg_reg[255]_0 [46])); (* SOFT_HLUTNM = "soft_lutpair1244" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[47]_i_1 (.I0(s_axi_wdata[47]), .I1(s_axi_wready), .I2(wdf_data[47]), .O(\mc_app_wdf_data_reg_reg[255]_0 [47])); (* SOFT_HLUTNM = "soft_lutpair1245" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[48]_i_1 (.I0(s_axi_wdata[48]), .I1(s_axi_wready), .I2(wdf_data[48]), .O(\mc_app_wdf_data_reg_reg[255]_0 [48])); (* SOFT_HLUTNM = "soft_lutpair1246" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[49]_i_1 (.I0(s_axi_wdata[49]), .I1(s_axi_wready), .I2(wdf_data[49]), .O(\mc_app_wdf_data_reg_reg[255]_0 [49])); (* SOFT_HLUTNM = "soft_lutpair1201" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[4]_i_1 (.I0(s_axi_wdata[4]), .I1(s_axi_wready), .I2(wdf_data[4]), .O(\mc_app_wdf_data_reg_reg[255]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair1247" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[50]_i_1 (.I0(s_axi_wdata[50]), .I1(s_axi_wready), .I2(wdf_data[50]), .O(\mc_app_wdf_data_reg_reg[255]_0 [50])); (* SOFT_HLUTNM = "soft_lutpair1248" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[51]_i_1 (.I0(s_axi_wdata[51]), .I1(s_axi_wready), .I2(wdf_data[51]), .O(\mc_app_wdf_data_reg_reg[255]_0 [51])); (* SOFT_HLUTNM = "soft_lutpair1249" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[52]_i_1 (.I0(s_axi_wdata[52]), .I1(s_axi_wready), .I2(wdf_data[52]), .O(\mc_app_wdf_data_reg_reg[255]_0 [52])); (* SOFT_HLUTNM = "soft_lutpair1250" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[53]_i_1 (.I0(s_axi_wdata[53]), .I1(s_axi_wready), .I2(wdf_data[53]), .O(\mc_app_wdf_data_reg_reg[255]_0 [53])); (* SOFT_HLUTNM = "soft_lutpair1251" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[54]_i_1 (.I0(s_axi_wdata[54]), .I1(s_axi_wready), .I2(wdf_data[54]), .O(\mc_app_wdf_data_reg_reg[255]_0 [54])); (* SOFT_HLUTNM = "soft_lutpair1252" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[55]_i_1 (.I0(s_axi_wdata[55]), .I1(s_axi_wready), .I2(wdf_data[55]), .O(\mc_app_wdf_data_reg_reg[255]_0 [55])); (* SOFT_HLUTNM = "soft_lutpair1253" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[56]_i_1 (.I0(s_axi_wdata[56]), .I1(s_axi_wready), .I2(wdf_data[56]), .O(\mc_app_wdf_data_reg_reg[255]_0 [56])); (* SOFT_HLUTNM = "soft_lutpair1254" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[57]_i_1 (.I0(s_axi_wdata[57]), .I1(s_axi_wready), .I2(wdf_data[57]), .O(\mc_app_wdf_data_reg_reg[255]_0 [57])); (* SOFT_HLUTNM = "soft_lutpair1255" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[58]_i_1 (.I0(s_axi_wdata[58]), .I1(s_axi_wready), .I2(wdf_data[58]), .O(\mc_app_wdf_data_reg_reg[255]_0 [58])); (* SOFT_HLUTNM = "soft_lutpair1256" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[59]_i_1 (.I0(s_axi_wdata[59]), .I1(s_axi_wready), .I2(wdf_data[59]), .O(\mc_app_wdf_data_reg_reg[255]_0 [59])); (* SOFT_HLUTNM = "soft_lutpair1202" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[5]_i_1 (.I0(s_axi_wdata[5]), .I1(s_axi_wready), .I2(wdf_data[5]), .O(\mc_app_wdf_data_reg_reg[255]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair1257" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[60]_i_1 (.I0(s_axi_wdata[60]), .I1(s_axi_wready), .I2(wdf_data[60]), .O(\mc_app_wdf_data_reg_reg[255]_0 [60])); (* SOFT_HLUTNM = "soft_lutpair1258" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[61]_i_1 (.I0(s_axi_wdata[61]), .I1(s_axi_wready), .I2(wdf_data[61]), .O(\mc_app_wdf_data_reg_reg[255]_0 [61])); (* SOFT_HLUTNM = "soft_lutpair1259" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[62]_i_1 (.I0(s_axi_wdata[62]), .I1(s_axi_wready), .I2(wdf_data[62]), .O(\mc_app_wdf_data_reg_reg[255]_0 [62])); (* SOFT_HLUTNM = "soft_lutpair1260" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[63]_i_1 (.I0(s_axi_wdata[63]), .I1(s_axi_wready), .I2(wdf_data[63]), .O(\mc_app_wdf_data_reg_reg[255]_0 [63])); (* SOFT_HLUTNM = "soft_lutpair1261" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[64]_i_1 (.I0(s_axi_wdata[64]), .I1(s_axi_wready), .I2(wdf_data[64]), .O(\mc_app_wdf_data_reg_reg[255]_0 [64])); (* SOFT_HLUTNM = "soft_lutpair1262" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[65]_i_1 (.I0(s_axi_wdata[65]), .I1(s_axi_wready), .I2(wdf_data[65]), .O(\mc_app_wdf_data_reg_reg[255]_0 [65])); (* SOFT_HLUTNM = "soft_lutpair1263" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[66]_i_1 (.I0(s_axi_wdata[66]), .I1(wready_reg_rep_n_0), .I2(wdf_data[66]), .O(\mc_app_wdf_data_reg_reg[255]_0 [66])); (* SOFT_HLUTNM = "soft_lutpair1264" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[67]_i_1 (.I0(s_axi_wdata[67]), .I1(wready_reg_rep_n_0), .I2(wdf_data[67]), .O(\mc_app_wdf_data_reg_reg[255]_0 [67])); (* SOFT_HLUTNM = "soft_lutpair1265" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[68]_i_1 (.I0(s_axi_wdata[68]), .I1(wready_reg_rep_n_0), .I2(wdf_data[68]), .O(\mc_app_wdf_data_reg_reg[255]_0 [68])); (* SOFT_HLUTNM = "soft_lutpair1266" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[69]_i_1 (.I0(s_axi_wdata[69]), .I1(wready_reg_rep_n_0), .I2(wdf_data[69]), .O(\mc_app_wdf_data_reg_reg[255]_0 [69])); (* SOFT_HLUTNM = "soft_lutpair1203" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[6]_i_1 (.I0(s_axi_wdata[6]), .I1(s_axi_wready), .I2(wdf_data[6]), .O(\mc_app_wdf_data_reg_reg[255]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair1267" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[70]_i_1 (.I0(s_axi_wdata[70]), .I1(wready_reg_rep_n_0), .I2(wdf_data[70]), .O(\mc_app_wdf_data_reg_reg[255]_0 [70])); (* SOFT_HLUTNM = "soft_lutpair1268" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[71]_i_1 (.I0(s_axi_wdata[71]), .I1(wready_reg_rep_n_0), .I2(wdf_data[71]), .O(\mc_app_wdf_data_reg_reg[255]_0 [71])); (* SOFT_HLUTNM = "soft_lutpair1269" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[72]_i_1 (.I0(s_axi_wdata[72]), .I1(wready_reg_rep_n_0), .I2(wdf_data[72]), .O(\mc_app_wdf_data_reg_reg[255]_0 [72])); (* SOFT_HLUTNM = "soft_lutpair1270" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[73]_i_1 (.I0(s_axi_wdata[73]), .I1(wready_reg_rep_n_0), .I2(wdf_data[73]), .O(\mc_app_wdf_data_reg_reg[255]_0 [73])); (* SOFT_HLUTNM = "soft_lutpair1271" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[74]_i_1 (.I0(s_axi_wdata[74]), .I1(wready_reg_rep_n_0), .I2(wdf_data[74]), .O(\mc_app_wdf_data_reg_reg[255]_0 [74])); (* SOFT_HLUTNM = "soft_lutpair1272" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[75]_i_1 (.I0(s_axi_wdata[75]), .I1(wready_reg_rep_n_0), .I2(wdf_data[75]), .O(\mc_app_wdf_data_reg_reg[255]_0 [75])); (* SOFT_HLUTNM = "soft_lutpair1273" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[76]_i_1 (.I0(s_axi_wdata[76]), .I1(wready_reg_rep_n_0), .I2(wdf_data[76]), .O(\mc_app_wdf_data_reg_reg[255]_0 [76])); (* SOFT_HLUTNM = "soft_lutpair1274" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[77]_i_1 (.I0(s_axi_wdata[77]), .I1(wready_reg_rep_n_0), .I2(wdf_data[77]), .O(\mc_app_wdf_data_reg_reg[255]_0 [77])); (* SOFT_HLUTNM = "soft_lutpair1275" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[78]_i_1 (.I0(s_axi_wdata[78]), .I1(wready_reg_rep_n_0), .I2(wdf_data[78]), .O(\mc_app_wdf_data_reg_reg[255]_0 [78])); (* SOFT_HLUTNM = "soft_lutpair1276" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[79]_i_1 (.I0(s_axi_wdata[79]), .I1(wready_reg_rep_n_0), .I2(wdf_data[79]), .O(\mc_app_wdf_data_reg_reg[255]_0 [79])); (* SOFT_HLUTNM = "soft_lutpair1204" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[7]_i_1 (.I0(s_axi_wdata[7]), .I1(s_axi_wready), .I2(wdf_data[7]), .O(\mc_app_wdf_data_reg_reg[255]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair1277" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[80]_i_1 (.I0(s_axi_wdata[80]), .I1(wready_reg_rep_n_0), .I2(wdf_data[80]), .O(\mc_app_wdf_data_reg_reg[255]_0 [80])); (* SOFT_HLUTNM = "soft_lutpair1278" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[81]_i_1 (.I0(s_axi_wdata[81]), .I1(wready_reg_rep_n_0), .I2(wdf_data[81]), .O(\mc_app_wdf_data_reg_reg[255]_0 [81])); (* SOFT_HLUTNM = "soft_lutpair1279" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[82]_i_1 (.I0(s_axi_wdata[82]), .I1(wready_reg_rep_n_0), .I2(wdf_data[82]), .O(\mc_app_wdf_data_reg_reg[255]_0 [82])); (* SOFT_HLUTNM = "soft_lutpair1280" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[83]_i_1 (.I0(s_axi_wdata[83]), .I1(wready_reg_rep_n_0), .I2(wdf_data[83]), .O(\mc_app_wdf_data_reg_reg[255]_0 [83])); (* SOFT_HLUTNM = "soft_lutpair1281" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[84]_i_1 (.I0(s_axi_wdata[84]), .I1(wready_reg_rep_n_0), .I2(wdf_data[84]), .O(\mc_app_wdf_data_reg_reg[255]_0 [84])); (* SOFT_HLUTNM = "soft_lutpair1282" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[85]_i_1 (.I0(s_axi_wdata[85]), .I1(wready_reg_rep_n_0), .I2(wdf_data[85]), .O(\mc_app_wdf_data_reg_reg[255]_0 [85])); (* SOFT_HLUTNM = "soft_lutpair1283" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[86]_i_1 (.I0(s_axi_wdata[86]), .I1(wready_reg_rep_n_0), .I2(wdf_data[86]), .O(\mc_app_wdf_data_reg_reg[255]_0 [86])); (* SOFT_HLUTNM = "soft_lutpair1284" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[87]_i_1 (.I0(s_axi_wdata[87]), .I1(wready_reg_rep_n_0), .I2(wdf_data[87]), .O(\mc_app_wdf_data_reg_reg[255]_0 [87])); (* SOFT_HLUTNM = "soft_lutpair1285" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[88]_i_1 (.I0(s_axi_wdata[88]), .I1(wready_reg_rep_n_0), .I2(wdf_data[88]), .O(\mc_app_wdf_data_reg_reg[255]_0 [88])); (* SOFT_HLUTNM = "soft_lutpair1286" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[89]_i_1 (.I0(s_axi_wdata[89]), .I1(wready_reg_rep_n_0), .I2(wdf_data[89]), .O(\mc_app_wdf_data_reg_reg[255]_0 [89])); (* SOFT_HLUTNM = "soft_lutpair1205" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[8]_i_1 (.I0(s_axi_wdata[8]), .I1(s_axi_wready), .I2(wdf_data[8]), .O(\mc_app_wdf_data_reg_reg[255]_0 [8])); (* SOFT_HLUTNM = "soft_lutpair1287" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[90]_i_1 (.I0(s_axi_wdata[90]), .I1(wready_reg_rep_n_0), .I2(wdf_data[90]), .O(\mc_app_wdf_data_reg_reg[255]_0 [90])); (* SOFT_HLUTNM = "soft_lutpair1288" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[91]_i_1 (.I0(s_axi_wdata[91]), .I1(wready_reg_rep_n_0), .I2(wdf_data[91]), .O(\mc_app_wdf_data_reg_reg[255]_0 [91])); (* SOFT_HLUTNM = "soft_lutpair1289" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[92]_i_1 (.I0(s_axi_wdata[92]), .I1(wready_reg_rep_n_0), .I2(wdf_data[92]), .O(\mc_app_wdf_data_reg_reg[255]_0 [92])); (* SOFT_HLUTNM = "soft_lutpair1290" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[93]_i_1 (.I0(s_axi_wdata[93]), .I1(wready_reg_rep_n_0), .I2(wdf_data[93]), .O(\mc_app_wdf_data_reg_reg[255]_0 [93])); (* SOFT_HLUTNM = "soft_lutpair1291" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[94]_i_1 (.I0(s_axi_wdata[94]), .I1(wready_reg_rep_n_0), .I2(wdf_data[94]), .O(\mc_app_wdf_data_reg_reg[255]_0 [94])); (* SOFT_HLUTNM = "soft_lutpair1292" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[95]_i_1 (.I0(s_axi_wdata[95]), .I1(wready_reg_rep_n_0), .I2(wdf_data[95]), .O(\mc_app_wdf_data_reg_reg[255]_0 [95])); (* SOFT_HLUTNM = "soft_lutpair1293" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[96]_i_1 (.I0(s_axi_wdata[96]), .I1(wready_reg_rep_n_0), .I2(wdf_data[96]), .O(\mc_app_wdf_data_reg_reg[255]_0 [96])); (* SOFT_HLUTNM = "soft_lutpair1294" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[97]_i_1 (.I0(s_axi_wdata[97]), .I1(wready_reg_rep_n_0), .I2(wdf_data[97]), .O(\mc_app_wdf_data_reg_reg[255]_0 [97])); (* SOFT_HLUTNM = "soft_lutpair1295" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[98]_i_1 (.I0(s_axi_wdata[98]), .I1(wready_reg_rep_n_0), .I2(wdf_data[98]), .O(\mc_app_wdf_data_reg_reg[255]_0 [98])); (* SOFT_HLUTNM = "soft_lutpair1296" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[99]_i_1 (.I0(s_axi_wdata[99]), .I1(wready_reg_rep_n_0), .I2(wdf_data[99]), .O(\mc_app_wdf_data_reg_reg[255]_0 [99])); (* SOFT_HLUTNM = "soft_lutpair1206" *) LUT3 #( .INIT(8'hB8)) \mc_app_wdf_data_reg[9]_i_1 (.I0(s_axi_wdata[9]), .I1(s_axi_wready), .I2(wdf_data[9]), .O(\mc_app_wdf_data_reg_reg[255]_0 [9])); FDRE \mc_app_wdf_data_reg_reg[0] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [0]), .Q(mc_app_wdf_data_reg[0]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[100] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [100]), .Q(mc_app_wdf_data_reg[100]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[101] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [101]), .Q(mc_app_wdf_data_reg[101]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[102] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [102]), .Q(mc_app_wdf_data_reg[102]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[103] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [103]), .Q(mc_app_wdf_data_reg[103]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[104] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [104]), .Q(mc_app_wdf_data_reg[104]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[105] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [105]), .Q(mc_app_wdf_data_reg[105]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[106] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [106]), .Q(mc_app_wdf_data_reg[106]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[107] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [107]), .Q(mc_app_wdf_data_reg[107]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[108] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [108]), .Q(mc_app_wdf_data_reg[108]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[109] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [109]), .Q(mc_app_wdf_data_reg[109]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[10] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [10]), .Q(mc_app_wdf_data_reg[10]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[110] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [110]), .Q(mc_app_wdf_data_reg[110]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[111] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [111]), .Q(mc_app_wdf_data_reg[111]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[112] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [112]), .Q(mc_app_wdf_data_reg[112]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[113] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [113]), .Q(mc_app_wdf_data_reg[113]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[114] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [114]), .Q(mc_app_wdf_data_reg[114]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[115] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [115]), .Q(mc_app_wdf_data_reg[115]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[116] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [116]), .Q(mc_app_wdf_data_reg[116]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[117] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [117]), .Q(mc_app_wdf_data_reg[117]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[118] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [118]), .Q(mc_app_wdf_data_reg[118]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[119] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [119]), .Q(mc_app_wdf_data_reg[119]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[11] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [11]), .Q(mc_app_wdf_data_reg[11]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[120] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [120]), .Q(mc_app_wdf_data_reg[120]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[121] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [121]), .Q(mc_app_wdf_data_reg[121]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[122] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [122]), .Q(mc_app_wdf_data_reg[122]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[123] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [123]), .Q(mc_app_wdf_data_reg[123]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[124] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [124]), .Q(mc_app_wdf_data_reg[124]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[125] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [125]), .Q(mc_app_wdf_data_reg[125]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[126] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [126]), .Q(mc_app_wdf_data_reg[126]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[127] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [127]), .Q(mc_app_wdf_data_reg[127]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[128] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [128]), .Q(mc_app_wdf_data_reg[128]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[129] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [129]), .Q(mc_app_wdf_data_reg[129]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[12] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [12]), .Q(mc_app_wdf_data_reg[12]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[130] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [130]), .Q(mc_app_wdf_data_reg[130]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[131] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [131]), .Q(mc_app_wdf_data_reg[131]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[132] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [132]), .Q(mc_app_wdf_data_reg[132]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[133] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [133]), .Q(mc_app_wdf_data_reg[133]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[134] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [134]), .Q(mc_app_wdf_data_reg[134]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[135] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [135]), .Q(mc_app_wdf_data_reg[135]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[136] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [136]), .Q(mc_app_wdf_data_reg[136]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[137] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [137]), .Q(mc_app_wdf_data_reg[137]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[138] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [138]), .Q(mc_app_wdf_data_reg[138]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[139] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [139]), .Q(mc_app_wdf_data_reg[139]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[13] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [13]), .Q(mc_app_wdf_data_reg[13]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[140] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [140]), .Q(mc_app_wdf_data_reg[140]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[141] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [141]), .Q(mc_app_wdf_data_reg[141]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[142] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [142]), .Q(mc_app_wdf_data_reg[142]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[143] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [143]), .Q(mc_app_wdf_data_reg[143]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[144] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [144]), .Q(mc_app_wdf_data_reg[144]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[145] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [145]), .Q(mc_app_wdf_data_reg[145]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[146] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [146]), .Q(mc_app_wdf_data_reg[146]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[147] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [147]), .Q(mc_app_wdf_data_reg[147]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[148] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [148]), .Q(mc_app_wdf_data_reg[148]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[149] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [149]), .Q(mc_app_wdf_data_reg[149]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[14] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [14]), .Q(mc_app_wdf_data_reg[14]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[150] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [150]), .Q(mc_app_wdf_data_reg[150]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[151] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [151]), .Q(mc_app_wdf_data_reg[151]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[152] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [152]), .Q(mc_app_wdf_data_reg[152]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[153] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [153]), .Q(mc_app_wdf_data_reg[153]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[154] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [154]), .Q(mc_app_wdf_data_reg[154]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[155] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [155]), .Q(mc_app_wdf_data_reg[155]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[156] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [156]), .Q(mc_app_wdf_data_reg[156]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[157] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [157]), .Q(mc_app_wdf_data_reg[157]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[158] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [158]), .Q(mc_app_wdf_data_reg[158]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[159] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [159]), .Q(mc_app_wdf_data_reg[159]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[15] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [15]), .Q(mc_app_wdf_data_reg[15]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[160] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [160]), .Q(mc_app_wdf_data_reg[160]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[161] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [161]), .Q(mc_app_wdf_data_reg[161]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[162] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [162]), .Q(mc_app_wdf_data_reg[162]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[163] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [163]), .Q(mc_app_wdf_data_reg[163]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[164] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [164]), .Q(mc_app_wdf_data_reg[164]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[165] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [165]), .Q(mc_app_wdf_data_reg[165]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[166] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [166]), .Q(mc_app_wdf_data_reg[166]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[167] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [167]), .Q(mc_app_wdf_data_reg[167]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[168] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [168]), .Q(mc_app_wdf_data_reg[168]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[169] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [169]), .Q(mc_app_wdf_data_reg[169]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[16] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [16]), .Q(mc_app_wdf_data_reg[16]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[170] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [170]), .Q(mc_app_wdf_data_reg[170]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[171] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [171]), .Q(mc_app_wdf_data_reg[171]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[172] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [172]), .Q(mc_app_wdf_data_reg[172]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[173] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [173]), .Q(mc_app_wdf_data_reg[173]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[174] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [174]), .Q(mc_app_wdf_data_reg[174]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[175] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [175]), .Q(mc_app_wdf_data_reg[175]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[176] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [176]), .Q(mc_app_wdf_data_reg[176]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[177] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [177]), .Q(mc_app_wdf_data_reg[177]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[178] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [178]), .Q(mc_app_wdf_data_reg[178]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[179] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [179]), .Q(mc_app_wdf_data_reg[179]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[17] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [17]), .Q(mc_app_wdf_data_reg[17]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[180] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [180]), .Q(mc_app_wdf_data_reg[180]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[181] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [181]), .Q(mc_app_wdf_data_reg[181]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[182] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [182]), .Q(mc_app_wdf_data_reg[182]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[183] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [183]), .Q(mc_app_wdf_data_reg[183]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[184] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [184]), .Q(mc_app_wdf_data_reg[184]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[185] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [185]), .Q(mc_app_wdf_data_reg[185]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[186] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [186]), .Q(mc_app_wdf_data_reg[186]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[187] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [187]), .Q(mc_app_wdf_data_reg[187]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[188] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [188]), .Q(mc_app_wdf_data_reg[188]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[189] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [189]), .Q(mc_app_wdf_data_reg[189]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[18] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [18]), .Q(mc_app_wdf_data_reg[18]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[190] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [190]), .Q(mc_app_wdf_data_reg[190]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[191] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [191]), .Q(mc_app_wdf_data_reg[191]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[192] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [192]), .Q(mc_app_wdf_data_reg[192]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[193] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [193]), .Q(mc_app_wdf_data_reg[193]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[194] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [194]), .Q(mc_app_wdf_data_reg[194]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[195] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [195]), .Q(mc_app_wdf_data_reg[195]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[196] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [196]), .Q(mc_app_wdf_data_reg[196]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[197] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [197]), .Q(mc_app_wdf_data_reg[197]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[198] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [198]), .Q(mc_app_wdf_data_reg[198]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[199] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [199]), .Q(mc_app_wdf_data_reg[199]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[19] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [19]), .Q(mc_app_wdf_data_reg[19]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[1] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [1]), .Q(mc_app_wdf_data_reg[1]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[200] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [200]), .Q(mc_app_wdf_data_reg[200]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[201] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [201]), .Q(mc_app_wdf_data_reg[201]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[202] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [202]), .Q(mc_app_wdf_data_reg[202]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[203] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [203]), .Q(mc_app_wdf_data_reg[203]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[204] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [204]), .Q(mc_app_wdf_data_reg[204]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[205] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [205]), .Q(mc_app_wdf_data_reg[205]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[206] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [206]), .Q(mc_app_wdf_data_reg[206]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[207] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [207]), .Q(mc_app_wdf_data_reg[207]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[208] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [208]), .Q(mc_app_wdf_data_reg[208]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[209] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [209]), .Q(mc_app_wdf_data_reg[209]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[20] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [20]), .Q(mc_app_wdf_data_reg[20]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[210] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [210]), .Q(mc_app_wdf_data_reg[210]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[211] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [211]), .Q(mc_app_wdf_data_reg[211]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[212] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [212]), .Q(mc_app_wdf_data_reg[212]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[213] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [213]), .Q(mc_app_wdf_data_reg[213]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[214] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [214]), .Q(mc_app_wdf_data_reg[214]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[215] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [215]), .Q(mc_app_wdf_data_reg[215]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[216] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [216]), .Q(mc_app_wdf_data_reg[216]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[217] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [217]), .Q(mc_app_wdf_data_reg[217]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[218] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [218]), .Q(mc_app_wdf_data_reg[218]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[219] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [219]), .Q(mc_app_wdf_data_reg[219]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[21] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [21]), .Q(mc_app_wdf_data_reg[21]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[220] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [220]), .Q(mc_app_wdf_data_reg[220]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[221] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [221]), .Q(mc_app_wdf_data_reg[221]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[222] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [222]), .Q(mc_app_wdf_data_reg[222]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[223] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [223]), .Q(mc_app_wdf_data_reg[223]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[224] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [224]), .Q(mc_app_wdf_data_reg[224]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[225] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [225]), .Q(mc_app_wdf_data_reg[225]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[226] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [226]), .Q(mc_app_wdf_data_reg[226]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[227] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [227]), .Q(mc_app_wdf_data_reg[227]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[228] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [228]), .Q(mc_app_wdf_data_reg[228]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[229] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [229]), .Q(mc_app_wdf_data_reg[229]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[22] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [22]), .Q(mc_app_wdf_data_reg[22]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[230] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [230]), .Q(mc_app_wdf_data_reg[230]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[231] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [231]), .Q(mc_app_wdf_data_reg[231]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[232] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [232]), .Q(mc_app_wdf_data_reg[232]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[233] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [233]), .Q(mc_app_wdf_data_reg[233]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[234] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [234]), .Q(mc_app_wdf_data_reg[234]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[235] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [235]), .Q(mc_app_wdf_data_reg[235]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[236] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [236]), .Q(mc_app_wdf_data_reg[236]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[237] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [237]), .Q(mc_app_wdf_data_reg[237]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[238] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [238]), .Q(mc_app_wdf_data_reg[238]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[239] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [239]), .Q(mc_app_wdf_data_reg[239]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[23] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [23]), .Q(mc_app_wdf_data_reg[23]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[240] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [240]), .Q(mc_app_wdf_data_reg[240]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[241] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [241]), .Q(mc_app_wdf_data_reg[241]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[242] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [242]), .Q(mc_app_wdf_data_reg[242]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[243] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [243]), .Q(mc_app_wdf_data_reg[243]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[244] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [244]), .Q(mc_app_wdf_data_reg[244]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[245] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [245]), .Q(mc_app_wdf_data_reg[245]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[246] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [246]), .Q(mc_app_wdf_data_reg[246]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[247] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [247]), .Q(mc_app_wdf_data_reg[247]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[248] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [248]), .Q(mc_app_wdf_data_reg[248]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[249] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [249]), .Q(mc_app_wdf_data_reg[249]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[24] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [24]), .Q(mc_app_wdf_data_reg[24]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[250] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [250]), .Q(mc_app_wdf_data_reg[250]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[251] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [251]), .Q(mc_app_wdf_data_reg[251]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[252] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [252]), .Q(mc_app_wdf_data_reg[252]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[253] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [253]), .Q(mc_app_wdf_data_reg[253]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[254] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [254]), .Q(mc_app_wdf_data_reg[254]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[255] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [255]), .Q(mc_app_wdf_data_reg[255]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[25] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [25]), .Q(mc_app_wdf_data_reg[25]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[26] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [26]), .Q(mc_app_wdf_data_reg[26]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[27] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [27]), .Q(mc_app_wdf_data_reg[27]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[28] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [28]), .Q(mc_app_wdf_data_reg[28]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[29] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [29]), .Q(mc_app_wdf_data_reg[29]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[2] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [2]), .Q(mc_app_wdf_data_reg[2]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[30] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [30]), .Q(mc_app_wdf_data_reg[30]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[31] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [31]), .Q(mc_app_wdf_data_reg[31]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[32] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [32]), .Q(mc_app_wdf_data_reg[32]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[33] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [33]), .Q(mc_app_wdf_data_reg[33]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[34] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [34]), .Q(mc_app_wdf_data_reg[34]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[35] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [35]), .Q(mc_app_wdf_data_reg[35]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[36] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [36]), .Q(mc_app_wdf_data_reg[36]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[37] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [37]), .Q(mc_app_wdf_data_reg[37]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[38] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [38]), .Q(mc_app_wdf_data_reg[38]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[39] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [39]), .Q(mc_app_wdf_data_reg[39]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[3] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [3]), .Q(mc_app_wdf_data_reg[3]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[40] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [40]), .Q(mc_app_wdf_data_reg[40]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[41] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [41]), .Q(mc_app_wdf_data_reg[41]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[42] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [42]), .Q(mc_app_wdf_data_reg[42]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[43] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [43]), .Q(mc_app_wdf_data_reg[43]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[44] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [44]), .Q(mc_app_wdf_data_reg[44]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[45] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [45]), .Q(mc_app_wdf_data_reg[45]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[46] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [46]), .Q(mc_app_wdf_data_reg[46]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[47] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [47]), .Q(mc_app_wdf_data_reg[47]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[48] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [48]), .Q(mc_app_wdf_data_reg[48]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[49] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [49]), .Q(mc_app_wdf_data_reg[49]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[4] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [4]), .Q(mc_app_wdf_data_reg[4]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[50] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [50]), .Q(mc_app_wdf_data_reg[50]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[51] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [51]), .Q(mc_app_wdf_data_reg[51]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[52] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [52]), .Q(mc_app_wdf_data_reg[52]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[53] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [53]), .Q(mc_app_wdf_data_reg[53]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[54] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [54]), .Q(mc_app_wdf_data_reg[54]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[55] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [55]), .Q(mc_app_wdf_data_reg[55]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[56] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [56]), .Q(mc_app_wdf_data_reg[56]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[57] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [57]), .Q(mc_app_wdf_data_reg[57]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[58] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [58]), .Q(mc_app_wdf_data_reg[58]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[59] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [59]), .Q(mc_app_wdf_data_reg[59]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[5] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [5]), .Q(mc_app_wdf_data_reg[5]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[60] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [60]), .Q(mc_app_wdf_data_reg[60]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[61] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [61]), .Q(mc_app_wdf_data_reg[61]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[62] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [62]), .Q(mc_app_wdf_data_reg[62]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[63] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [63]), .Q(mc_app_wdf_data_reg[63]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[64] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [64]), .Q(mc_app_wdf_data_reg[64]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[65] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [65]), .Q(mc_app_wdf_data_reg[65]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[66] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [66]), .Q(mc_app_wdf_data_reg[66]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[67] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [67]), .Q(mc_app_wdf_data_reg[67]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[68] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [68]), .Q(mc_app_wdf_data_reg[68]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[69] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [69]), .Q(mc_app_wdf_data_reg[69]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[6] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [6]), .Q(mc_app_wdf_data_reg[6]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[70] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [70]), .Q(mc_app_wdf_data_reg[70]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[71] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [71]), .Q(mc_app_wdf_data_reg[71]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[72] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [72]), .Q(mc_app_wdf_data_reg[72]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[73] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [73]), .Q(mc_app_wdf_data_reg[73]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[74] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [74]), .Q(mc_app_wdf_data_reg[74]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[75] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [75]), .Q(mc_app_wdf_data_reg[75]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[76] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [76]), .Q(mc_app_wdf_data_reg[76]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[77] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [77]), .Q(mc_app_wdf_data_reg[77]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[78] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [78]), .Q(mc_app_wdf_data_reg[78]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[79] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [79]), .Q(mc_app_wdf_data_reg[79]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[7] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [7]), .Q(mc_app_wdf_data_reg[7]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[80] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [80]), .Q(mc_app_wdf_data_reg[80]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[81] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [81]), .Q(mc_app_wdf_data_reg[81]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[82] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [82]), .Q(mc_app_wdf_data_reg[82]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[83] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [83]), .Q(mc_app_wdf_data_reg[83]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[84] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [84]), .Q(mc_app_wdf_data_reg[84]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[85] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [85]), .Q(mc_app_wdf_data_reg[85]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[86] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [86]), .Q(mc_app_wdf_data_reg[86]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[87] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [87]), .Q(mc_app_wdf_data_reg[87]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[88] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [88]), .Q(mc_app_wdf_data_reg[88]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[89] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [89]), .Q(mc_app_wdf_data_reg[89]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[8] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [8]), .Q(mc_app_wdf_data_reg[8]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[90] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [90]), .Q(mc_app_wdf_data_reg[90]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[91] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [91]), .Q(mc_app_wdf_data_reg[91]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[92] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [92]), .Q(mc_app_wdf_data_reg[92]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[93] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [93]), .Q(mc_app_wdf_data_reg[93]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[94] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [94]), .Q(mc_app_wdf_data_reg[94]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[95] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [95]), .Q(mc_app_wdf_data_reg[95]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[96] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [96]), .Q(mc_app_wdf_data_reg[96]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[97] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [97]), .Q(mc_app_wdf_data_reg[97]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[98] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [98]), .Q(mc_app_wdf_data_reg[98]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[99] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [99]), .Q(mc_app_wdf_data_reg[99]), .R(1'b0)); FDRE \mc_app_wdf_data_reg_reg[9] (.C(CLK), .CE(app_wdf_rdy), .D(\mc_app_wdf_data_reg_reg[255]_0 [9]), .Q(mc_app_wdf_data_reg[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1453" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[0]_i_1 (.I0(s_axi_wstrb[0]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair1463" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[10]_i_1 (.I0(s_axi_wstrb[10]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[10]), .O(D[10])); (* SOFT_HLUTNM = "soft_lutpair1464" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[11]_i_1 (.I0(s_axi_wstrb[11]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[11]), .O(D[11])); (* SOFT_HLUTNM = "soft_lutpair1465" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[12]_i_1 (.I0(s_axi_wstrb[12]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[12]), .O(D[12])); (* SOFT_HLUTNM = "soft_lutpair1466" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[13]_i_1 (.I0(s_axi_wstrb[13]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[13]), .O(D[13])); (* SOFT_HLUTNM = "soft_lutpair1467" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[14]_i_1 (.I0(s_axi_wstrb[14]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[14]), .O(D[14])); (* SOFT_HLUTNM = "soft_lutpair1468" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[15]_i_1 (.I0(s_axi_wstrb[15]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[15]), .O(D[15])); (* SOFT_HLUTNM = "soft_lutpair1469" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[16]_i_1 (.I0(s_axi_wstrb[16]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[16]), .O(D[16])); (* SOFT_HLUTNM = "soft_lutpair1470" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[17]_i_1 (.I0(s_axi_wstrb[17]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[17]), .O(D[17])); (* SOFT_HLUTNM = "soft_lutpair1471" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[18]_i_1 (.I0(s_axi_wstrb[18]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[18]), .O(D[18])); (* SOFT_HLUTNM = "soft_lutpair1472" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[19]_i_1 (.I0(s_axi_wstrb[19]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[19]), .O(D[19])); (* SOFT_HLUTNM = "soft_lutpair1454" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[1]_i_1 (.I0(s_axi_wstrb[1]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[1]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair1473" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[20]_i_1 (.I0(s_axi_wstrb[20]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[20]), .O(D[20])); (* SOFT_HLUTNM = "soft_lutpair1474" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[21]_i_1 (.I0(s_axi_wstrb[21]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[21]), .O(D[21])); (* SOFT_HLUTNM = "soft_lutpair1475" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[22]_i_1 (.I0(s_axi_wstrb[22]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[22]), .O(D[22])); (* SOFT_HLUTNM = "soft_lutpair1476" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[23]_i_1 (.I0(s_axi_wstrb[23]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[23]), .O(D[23])); (* SOFT_HLUTNM = "soft_lutpair1477" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[24]_i_1 (.I0(s_axi_wstrb[24]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[24]), .O(D[24])); (* SOFT_HLUTNM = "soft_lutpair1478" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[25]_i_1 (.I0(s_axi_wstrb[25]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[25]), .O(D[25])); (* SOFT_HLUTNM = "soft_lutpair1479" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[26]_i_1 (.I0(s_axi_wstrb[26]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[26]), .O(D[26])); (* SOFT_HLUTNM = "soft_lutpair1480" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[27]_i_1 (.I0(s_axi_wstrb[27]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[27]), .O(D[27])); (* SOFT_HLUTNM = "soft_lutpair1481" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[28]_i_1 (.I0(s_axi_wstrb[28]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[28]), .O(D[28])); (* SOFT_HLUTNM = "soft_lutpair1482" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[29]_i_1 (.I0(s_axi_wstrb[29]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[29]), .O(D[29])); (* SOFT_HLUTNM = "soft_lutpair1455" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[2]_i_1 (.I0(s_axi_wstrb[2]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[2]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair1483" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[30]_i_1 (.I0(s_axi_wstrb[30]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[30]), .O(D[30])); (* SOFT_HLUTNM = "soft_lutpair1484" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[31]_i_1 (.I0(s_axi_wstrb[31]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[31]), .O(D[31])); (* SOFT_HLUTNM = "soft_lutpair1456" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[3]_i_1 (.I0(s_axi_wstrb[3]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[3]), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair1457" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[4]_i_1 (.I0(s_axi_wstrb[4]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[4]), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair1458" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[5]_i_1 (.I0(s_axi_wstrb[5]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[5]), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair1459" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[6]_i_1 (.I0(s_axi_wstrb[6]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[6]), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair1460" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[7]_i_1 (.I0(s_axi_wstrb[7]), .I1(wready_reg_rep__1_n_0), .I2(wdf_mask[7]), .O(D[7])); (* SOFT_HLUTNM = "soft_lutpair1461" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[8]_i_1 (.I0(s_axi_wstrb[8]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[8]), .O(D[8])); (* SOFT_HLUTNM = "soft_lutpair1462" *) LUT3 #( .INIT(8'h74)) \mc_app_wdf_mask_reg[9]_i_1 (.I0(s_axi_wstrb[9]), .I1(wready_reg_rep__2_n_0), .I2(wdf_mask[9]), .O(D[9])); FDRE \mc_app_wdf_mask_reg_reg[0] (.C(CLK), .CE(app_wdf_rdy), .D(D[0]), .Q(mc_app_wdf_mask_reg[0]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[10] (.C(CLK), .CE(app_wdf_rdy), .D(D[10]), .Q(mc_app_wdf_mask_reg[10]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[11] (.C(CLK), .CE(app_wdf_rdy), .D(D[11]), .Q(mc_app_wdf_mask_reg[11]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[12] (.C(CLK), .CE(app_wdf_rdy), .D(D[12]), .Q(mc_app_wdf_mask_reg[12]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[13] (.C(CLK), .CE(app_wdf_rdy), .D(D[13]), .Q(mc_app_wdf_mask_reg[13]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[14] (.C(CLK), .CE(app_wdf_rdy), .D(D[14]), .Q(mc_app_wdf_mask_reg[14]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[15] (.C(CLK), .CE(app_wdf_rdy), .D(D[15]), .Q(mc_app_wdf_mask_reg[15]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[16] (.C(CLK), .CE(app_wdf_rdy), .D(D[16]), .Q(mc_app_wdf_mask_reg[16]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[17] (.C(CLK), .CE(app_wdf_rdy), .D(D[17]), .Q(mc_app_wdf_mask_reg[17]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[18] (.C(CLK), .CE(app_wdf_rdy), .D(D[18]), .Q(mc_app_wdf_mask_reg[18]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[19] (.C(CLK), .CE(app_wdf_rdy), .D(D[19]), .Q(mc_app_wdf_mask_reg[19]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[1] (.C(CLK), .CE(app_wdf_rdy), .D(D[1]), .Q(mc_app_wdf_mask_reg[1]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[20] (.C(CLK), .CE(app_wdf_rdy), .D(D[20]), .Q(mc_app_wdf_mask_reg[20]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[21] (.C(CLK), .CE(app_wdf_rdy), .D(D[21]), .Q(mc_app_wdf_mask_reg[21]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[22] (.C(CLK), .CE(app_wdf_rdy), .D(D[22]), .Q(mc_app_wdf_mask_reg[22]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[23] (.C(CLK), .CE(app_wdf_rdy), .D(D[23]), .Q(mc_app_wdf_mask_reg[23]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[24] (.C(CLK), .CE(app_wdf_rdy), .D(D[24]), .Q(mc_app_wdf_mask_reg[24]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[25] (.C(CLK), .CE(app_wdf_rdy), .D(D[25]), .Q(mc_app_wdf_mask_reg[25]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[26] (.C(CLK), .CE(app_wdf_rdy), .D(D[26]), .Q(mc_app_wdf_mask_reg[26]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[27] (.C(CLK), .CE(app_wdf_rdy), .D(D[27]), .Q(mc_app_wdf_mask_reg[27]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[28] (.C(CLK), .CE(app_wdf_rdy), .D(D[28]), .Q(mc_app_wdf_mask_reg[28]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[29] (.C(CLK), .CE(app_wdf_rdy), .D(D[29]), .Q(mc_app_wdf_mask_reg[29]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[2] (.C(CLK), .CE(app_wdf_rdy), .D(D[2]), .Q(mc_app_wdf_mask_reg[2]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[30] (.C(CLK), .CE(app_wdf_rdy), .D(D[30]), .Q(mc_app_wdf_mask_reg[30]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[31] (.C(CLK), .CE(app_wdf_rdy), .D(D[31]), .Q(mc_app_wdf_mask_reg[31]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[3] (.C(CLK), .CE(app_wdf_rdy), .D(D[3]), .Q(mc_app_wdf_mask_reg[3]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[4] (.C(CLK), .CE(app_wdf_rdy), .D(D[4]), .Q(mc_app_wdf_mask_reg[4]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[5] (.C(CLK), .CE(app_wdf_rdy), .D(D[5]), .Q(mc_app_wdf_mask_reg[5]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[6] (.C(CLK), .CE(app_wdf_rdy), .D(D[6]), .Q(mc_app_wdf_mask_reg[6]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[7] (.C(CLK), .CE(app_wdf_rdy), .D(D[7]), .Q(mc_app_wdf_mask_reg[7]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[8] (.C(CLK), .CE(app_wdf_rdy), .D(D[8]), .Q(mc_app_wdf_mask_reg[8]), .R(areset_d1)); FDRE \mc_app_wdf_mask_reg_reg[9] (.C(CLK), .CE(app_wdf_rdy), .D(D[9]), .Q(mc_app_wdf_mask_reg[9]), .R(areset_d1)); FDRE mc_app_wdf_wren_reg_reg (.C(CLK), .CE(app_wdf_rdy), .D(\RD_PRI_REG_STARVE.rnw_i_reg ), .Q(mc_app_wdf_wren_reg), .R(areset_d1)); LUT3 #( .INIT(8'hB8)) valid_i_1 (.I0(s_axi_wvalid), .I1(s_axi_wready), .I2(valid), .O(wvalid_int)); FDRE valid_reg (.C(CLK), .CE(1'b1), .D(wvalid_int), .Q(valid), .R(areset_d1)); FDRE \wdf_data_reg[0] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [0]), .Q(wdf_data[0]), .R(1'b0)); FDRE \wdf_data_reg[100] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [100]), .Q(wdf_data[100]), .R(1'b0)); FDRE \wdf_data_reg[101] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [101]), .Q(wdf_data[101]), .R(1'b0)); FDRE \wdf_data_reg[102] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [102]), .Q(wdf_data[102]), .R(1'b0)); FDRE \wdf_data_reg[103] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [103]), .Q(wdf_data[103]), .R(1'b0)); FDRE \wdf_data_reg[104] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [104]), .Q(wdf_data[104]), .R(1'b0)); FDRE \wdf_data_reg[105] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [105]), .Q(wdf_data[105]), .R(1'b0)); FDRE \wdf_data_reg[106] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [106]), .Q(wdf_data[106]), .R(1'b0)); FDRE \wdf_data_reg[107] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [107]), .Q(wdf_data[107]), .R(1'b0)); FDRE \wdf_data_reg[108] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [108]), .Q(wdf_data[108]), .R(1'b0)); FDRE \wdf_data_reg[109] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [109]), .Q(wdf_data[109]), .R(1'b0)); FDRE \wdf_data_reg[10] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [10]), .Q(wdf_data[10]), .R(1'b0)); FDRE \wdf_data_reg[110] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [110]), .Q(wdf_data[110]), .R(1'b0)); FDRE \wdf_data_reg[111] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [111]), .Q(wdf_data[111]), .R(1'b0)); FDRE \wdf_data_reg[112] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [112]), .Q(wdf_data[112]), .R(1'b0)); FDRE \wdf_data_reg[113] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [113]), .Q(wdf_data[113]), .R(1'b0)); FDRE \wdf_data_reg[114] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [114]), .Q(wdf_data[114]), .R(1'b0)); FDRE \wdf_data_reg[115] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [115]), .Q(wdf_data[115]), .R(1'b0)); FDRE \wdf_data_reg[116] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [116]), .Q(wdf_data[116]), .R(1'b0)); FDRE \wdf_data_reg[117] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [117]), .Q(wdf_data[117]), .R(1'b0)); FDRE \wdf_data_reg[118] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [118]), .Q(wdf_data[118]), .R(1'b0)); FDRE \wdf_data_reg[119] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [119]), .Q(wdf_data[119]), .R(1'b0)); FDRE \wdf_data_reg[11] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [11]), .Q(wdf_data[11]), .R(1'b0)); FDRE \wdf_data_reg[120] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [120]), .Q(wdf_data[120]), .R(1'b0)); FDRE \wdf_data_reg[121] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [121]), .Q(wdf_data[121]), .R(1'b0)); FDRE \wdf_data_reg[122] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [122]), .Q(wdf_data[122]), .R(1'b0)); FDRE \wdf_data_reg[123] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [123]), .Q(wdf_data[123]), .R(1'b0)); FDRE \wdf_data_reg[124] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [124]), .Q(wdf_data[124]), .R(1'b0)); FDRE \wdf_data_reg[125] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [125]), .Q(wdf_data[125]), .R(1'b0)); FDRE \wdf_data_reg[126] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [126]), .Q(wdf_data[126]), .R(1'b0)); FDRE \wdf_data_reg[127] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [127]), .Q(wdf_data[127]), .R(1'b0)); FDRE \wdf_data_reg[128] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [128]), .Q(wdf_data[128]), .R(1'b0)); FDRE \wdf_data_reg[129] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [129]), .Q(wdf_data[129]), .R(1'b0)); FDRE \wdf_data_reg[12] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [12]), .Q(wdf_data[12]), .R(1'b0)); FDRE \wdf_data_reg[130] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [130]), .Q(wdf_data[130]), .R(1'b0)); FDRE \wdf_data_reg[131] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [131]), .Q(wdf_data[131]), .R(1'b0)); FDRE \wdf_data_reg[132] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [132]), .Q(wdf_data[132]), .R(1'b0)); FDRE \wdf_data_reg[133] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [133]), .Q(wdf_data[133]), .R(1'b0)); FDRE \wdf_data_reg[134] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [134]), .Q(wdf_data[134]), .R(1'b0)); FDRE \wdf_data_reg[135] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [135]), .Q(wdf_data[135]), .R(1'b0)); FDRE \wdf_data_reg[136] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [136]), .Q(wdf_data[136]), .R(1'b0)); FDRE \wdf_data_reg[137] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [137]), .Q(wdf_data[137]), .R(1'b0)); FDRE \wdf_data_reg[138] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [138]), .Q(wdf_data[138]), .R(1'b0)); FDRE \wdf_data_reg[139] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [139]), .Q(wdf_data[139]), .R(1'b0)); FDRE \wdf_data_reg[13] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [13]), .Q(wdf_data[13]), .R(1'b0)); FDRE \wdf_data_reg[140] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [140]), .Q(wdf_data[140]), .R(1'b0)); FDRE \wdf_data_reg[141] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [141]), .Q(wdf_data[141]), .R(1'b0)); FDRE \wdf_data_reg[142] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [142]), .Q(wdf_data[142]), .R(1'b0)); FDRE \wdf_data_reg[143] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [143]), .Q(wdf_data[143]), .R(1'b0)); FDRE \wdf_data_reg[144] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [144]), .Q(wdf_data[144]), .R(1'b0)); FDRE \wdf_data_reg[145] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [145]), .Q(wdf_data[145]), .R(1'b0)); FDRE \wdf_data_reg[146] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [146]), .Q(wdf_data[146]), .R(1'b0)); FDRE \wdf_data_reg[147] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [147]), .Q(wdf_data[147]), .R(1'b0)); FDRE \wdf_data_reg[148] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [148]), .Q(wdf_data[148]), .R(1'b0)); FDRE \wdf_data_reg[149] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [149]), .Q(wdf_data[149]), .R(1'b0)); FDRE \wdf_data_reg[14] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [14]), .Q(wdf_data[14]), .R(1'b0)); FDRE \wdf_data_reg[150] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [150]), .Q(wdf_data[150]), .R(1'b0)); FDRE \wdf_data_reg[151] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [151]), .Q(wdf_data[151]), .R(1'b0)); FDRE \wdf_data_reg[152] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [152]), .Q(wdf_data[152]), .R(1'b0)); FDRE \wdf_data_reg[153] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [153]), .Q(wdf_data[153]), .R(1'b0)); FDRE \wdf_data_reg[154] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [154]), .Q(wdf_data[154]), .R(1'b0)); FDRE \wdf_data_reg[155] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [155]), .Q(wdf_data[155]), .R(1'b0)); FDRE \wdf_data_reg[156] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [156]), .Q(wdf_data[156]), .R(1'b0)); FDRE \wdf_data_reg[157] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [157]), .Q(wdf_data[157]), .R(1'b0)); FDRE \wdf_data_reg[158] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [158]), .Q(wdf_data[158]), .R(1'b0)); FDRE \wdf_data_reg[159] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [159]), .Q(wdf_data[159]), .R(1'b0)); FDRE \wdf_data_reg[15] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [15]), .Q(wdf_data[15]), .R(1'b0)); FDRE \wdf_data_reg[160] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [160]), .Q(wdf_data[160]), .R(1'b0)); FDRE \wdf_data_reg[161] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [161]), .Q(wdf_data[161]), .R(1'b0)); FDRE \wdf_data_reg[162] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [162]), .Q(wdf_data[162]), .R(1'b0)); FDRE \wdf_data_reg[163] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [163]), .Q(wdf_data[163]), .R(1'b0)); FDRE \wdf_data_reg[164] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [164]), .Q(wdf_data[164]), .R(1'b0)); FDRE \wdf_data_reg[165] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [165]), .Q(wdf_data[165]), .R(1'b0)); FDRE \wdf_data_reg[166] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [166]), .Q(wdf_data[166]), .R(1'b0)); FDRE \wdf_data_reg[167] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [167]), .Q(wdf_data[167]), .R(1'b0)); FDRE \wdf_data_reg[168] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [168]), .Q(wdf_data[168]), .R(1'b0)); FDRE \wdf_data_reg[169] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [169]), .Q(wdf_data[169]), .R(1'b0)); FDRE \wdf_data_reg[16] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [16]), .Q(wdf_data[16]), .R(1'b0)); FDRE \wdf_data_reg[170] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [170]), .Q(wdf_data[170]), .R(1'b0)); FDRE \wdf_data_reg[171] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [171]), .Q(wdf_data[171]), .R(1'b0)); FDRE \wdf_data_reg[172] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [172]), .Q(wdf_data[172]), .R(1'b0)); FDRE \wdf_data_reg[173] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [173]), .Q(wdf_data[173]), .R(1'b0)); FDRE \wdf_data_reg[174] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [174]), .Q(wdf_data[174]), .R(1'b0)); FDRE \wdf_data_reg[175] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [175]), .Q(wdf_data[175]), .R(1'b0)); FDRE \wdf_data_reg[176] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [176]), .Q(wdf_data[176]), .R(1'b0)); FDRE \wdf_data_reg[177] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [177]), .Q(wdf_data[177]), .R(1'b0)); FDRE \wdf_data_reg[178] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [178]), .Q(wdf_data[178]), .R(1'b0)); FDRE \wdf_data_reg[179] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [179]), .Q(wdf_data[179]), .R(1'b0)); FDRE \wdf_data_reg[17] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [17]), .Q(wdf_data[17]), .R(1'b0)); FDRE \wdf_data_reg[180] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [180]), .Q(wdf_data[180]), .R(1'b0)); FDRE \wdf_data_reg[181] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [181]), .Q(wdf_data[181]), .R(1'b0)); FDRE \wdf_data_reg[182] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [182]), .Q(wdf_data[182]), .R(1'b0)); FDRE \wdf_data_reg[183] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [183]), .Q(wdf_data[183]), .R(1'b0)); FDRE \wdf_data_reg[184] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [184]), .Q(wdf_data[184]), .R(1'b0)); FDRE \wdf_data_reg[185] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [185]), .Q(wdf_data[185]), .R(1'b0)); FDRE \wdf_data_reg[186] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [186]), .Q(wdf_data[186]), .R(1'b0)); FDRE \wdf_data_reg[187] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [187]), .Q(wdf_data[187]), .R(1'b0)); FDRE \wdf_data_reg[188] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [188]), .Q(wdf_data[188]), .R(1'b0)); FDRE \wdf_data_reg[189] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [189]), .Q(wdf_data[189]), .R(1'b0)); FDRE \wdf_data_reg[18] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [18]), .Q(wdf_data[18]), .R(1'b0)); FDRE \wdf_data_reg[190] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [190]), .Q(wdf_data[190]), .R(1'b0)); FDRE \wdf_data_reg[191] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [191]), .Q(wdf_data[191]), .R(1'b0)); FDRE \wdf_data_reg[192] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [192]), .Q(wdf_data[192]), .R(1'b0)); FDRE \wdf_data_reg[193] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [193]), .Q(wdf_data[193]), .R(1'b0)); FDRE \wdf_data_reg[194] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [194]), .Q(wdf_data[194]), .R(1'b0)); FDRE \wdf_data_reg[195] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [195]), .Q(wdf_data[195]), .R(1'b0)); FDRE \wdf_data_reg[196] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [196]), .Q(wdf_data[196]), .R(1'b0)); FDRE \wdf_data_reg[197] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [197]), .Q(wdf_data[197]), .R(1'b0)); FDRE \wdf_data_reg[198] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [198]), .Q(wdf_data[198]), .R(1'b0)); FDRE \wdf_data_reg[199] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [199]), .Q(wdf_data[199]), .R(1'b0)); FDRE \wdf_data_reg[19] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [19]), .Q(wdf_data[19]), .R(1'b0)); FDRE \wdf_data_reg[1] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [1]), .Q(wdf_data[1]), .R(1'b0)); FDRE \wdf_data_reg[200] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [200]), .Q(wdf_data[200]), .R(1'b0)); FDRE \wdf_data_reg[201] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [201]), .Q(wdf_data[201]), .R(1'b0)); FDRE \wdf_data_reg[202] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [202]), .Q(wdf_data[202]), .R(1'b0)); FDRE \wdf_data_reg[203] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [203]), .Q(wdf_data[203]), .R(1'b0)); FDRE \wdf_data_reg[204] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [204]), .Q(wdf_data[204]), .R(1'b0)); FDRE \wdf_data_reg[205] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [205]), .Q(wdf_data[205]), .R(1'b0)); FDRE \wdf_data_reg[206] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [206]), .Q(wdf_data[206]), .R(1'b0)); FDRE \wdf_data_reg[207] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [207]), .Q(wdf_data[207]), .R(1'b0)); FDRE \wdf_data_reg[208] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [208]), .Q(wdf_data[208]), .R(1'b0)); FDRE \wdf_data_reg[209] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [209]), .Q(wdf_data[209]), .R(1'b0)); FDRE \wdf_data_reg[20] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [20]), .Q(wdf_data[20]), .R(1'b0)); FDRE \wdf_data_reg[210] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [210]), .Q(wdf_data[210]), .R(1'b0)); FDRE \wdf_data_reg[211] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [211]), .Q(wdf_data[211]), .R(1'b0)); FDRE \wdf_data_reg[212] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [212]), .Q(wdf_data[212]), .R(1'b0)); FDRE \wdf_data_reg[213] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [213]), .Q(wdf_data[213]), .R(1'b0)); FDRE \wdf_data_reg[214] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [214]), .Q(wdf_data[214]), .R(1'b0)); FDRE \wdf_data_reg[215] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [215]), .Q(wdf_data[215]), .R(1'b0)); FDRE \wdf_data_reg[216] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [216]), .Q(wdf_data[216]), .R(1'b0)); FDRE \wdf_data_reg[217] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [217]), .Q(wdf_data[217]), .R(1'b0)); FDRE \wdf_data_reg[218] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [218]), .Q(wdf_data[218]), .R(1'b0)); FDRE \wdf_data_reg[219] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [219]), .Q(wdf_data[219]), .R(1'b0)); FDRE \wdf_data_reg[21] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [21]), .Q(wdf_data[21]), .R(1'b0)); FDRE \wdf_data_reg[220] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [220]), .Q(wdf_data[220]), .R(1'b0)); FDRE \wdf_data_reg[221] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [221]), .Q(wdf_data[221]), .R(1'b0)); FDRE \wdf_data_reg[222] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [222]), .Q(wdf_data[222]), .R(1'b0)); FDRE \wdf_data_reg[223] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [223]), .Q(wdf_data[223]), .R(1'b0)); FDRE \wdf_data_reg[224] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [224]), .Q(wdf_data[224]), .R(1'b0)); FDRE \wdf_data_reg[225] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [225]), .Q(wdf_data[225]), .R(1'b0)); FDRE \wdf_data_reg[226] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [226]), .Q(wdf_data[226]), .R(1'b0)); FDRE \wdf_data_reg[227] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [227]), .Q(wdf_data[227]), .R(1'b0)); FDRE \wdf_data_reg[228] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [228]), .Q(wdf_data[228]), .R(1'b0)); FDRE \wdf_data_reg[229] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [229]), .Q(wdf_data[229]), .R(1'b0)); FDRE \wdf_data_reg[22] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [22]), .Q(wdf_data[22]), .R(1'b0)); FDRE \wdf_data_reg[230] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [230]), .Q(wdf_data[230]), .R(1'b0)); FDRE \wdf_data_reg[231] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [231]), .Q(wdf_data[231]), .R(1'b0)); FDRE \wdf_data_reg[232] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [232]), .Q(wdf_data[232]), .R(1'b0)); FDRE \wdf_data_reg[233] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [233]), .Q(wdf_data[233]), .R(1'b0)); FDRE \wdf_data_reg[234] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [234]), .Q(wdf_data[234]), .R(1'b0)); FDRE \wdf_data_reg[235] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [235]), .Q(wdf_data[235]), .R(1'b0)); FDRE \wdf_data_reg[236] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [236]), .Q(wdf_data[236]), .R(1'b0)); FDRE \wdf_data_reg[237] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [237]), .Q(wdf_data[237]), .R(1'b0)); FDRE \wdf_data_reg[238] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [238]), .Q(wdf_data[238]), .R(1'b0)); FDRE \wdf_data_reg[239] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [239]), .Q(wdf_data[239]), .R(1'b0)); FDRE \wdf_data_reg[23] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [23]), .Q(wdf_data[23]), .R(1'b0)); FDRE \wdf_data_reg[240] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [240]), .Q(wdf_data[240]), .R(1'b0)); FDRE \wdf_data_reg[241] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [241]), .Q(wdf_data[241]), .R(1'b0)); FDRE \wdf_data_reg[242] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [242]), .Q(wdf_data[242]), .R(1'b0)); FDRE \wdf_data_reg[243] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [243]), .Q(wdf_data[243]), .R(1'b0)); FDRE \wdf_data_reg[244] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [244]), .Q(wdf_data[244]), .R(1'b0)); FDRE \wdf_data_reg[245] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [245]), .Q(wdf_data[245]), .R(1'b0)); FDRE \wdf_data_reg[246] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [246]), .Q(wdf_data[246]), .R(1'b0)); FDRE \wdf_data_reg[247] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [247]), .Q(wdf_data[247]), .R(1'b0)); FDRE \wdf_data_reg[248] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [248]), .Q(wdf_data[248]), .R(1'b0)); FDRE \wdf_data_reg[249] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [249]), .Q(wdf_data[249]), .R(1'b0)); FDRE \wdf_data_reg[24] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [24]), .Q(wdf_data[24]), .R(1'b0)); FDRE \wdf_data_reg[250] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [250]), .Q(wdf_data[250]), .R(1'b0)); FDRE \wdf_data_reg[251] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [251]), .Q(wdf_data[251]), .R(1'b0)); FDRE \wdf_data_reg[252] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [252]), .Q(wdf_data[252]), .R(1'b0)); FDRE \wdf_data_reg[253] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [253]), .Q(wdf_data[253]), .R(1'b0)); FDRE \wdf_data_reg[254] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [254]), .Q(wdf_data[254]), .R(1'b0)); FDRE \wdf_data_reg[255] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [255]), .Q(wdf_data[255]), .R(1'b0)); FDRE \wdf_data_reg[25] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [25]), .Q(wdf_data[25]), .R(1'b0)); FDRE \wdf_data_reg[26] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [26]), .Q(wdf_data[26]), .R(1'b0)); FDRE \wdf_data_reg[27] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [27]), .Q(wdf_data[27]), .R(1'b0)); FDRE \wdf_data_reg[28] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [28]), .Q(wdf_data[28]), .R(1'b0)); FDRE \wdf_data_reg[29] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [29]), .Q(wdf_data[29]), .R(1'b0)); FDRE \wdf_data_reg[2] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [2]), .Q(wdf_data[2]), .R(1'b0)); FDRE \wdf_data_reg[30] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [30]), .Q(wdf_data[30]), .R(1'b0)); FDRE \wdf_data_reg[31] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [31]), .Q(wdf_data[31]), .R(1'b0)); FDRE \wdf_data_reg[32] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [32]), .Q(wdf_data[32]), .R(1'b0)); FDRE \wdf_data_reg[33] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [33]), .Q(wdf_data[33]), .R(1'b0)); FDRE \wdf_data_reg[34] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [34]), .Q(wdf_data[34]), .R(1'b0)); FDRE \wdf_data_reg[35] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [35]), .Q(wdf_data[35]), .R(1'b0)); FDRE \wdf_data_reg[36] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [36]), .Q(wdf_data[36]), .R(1'b0)); FDRE \wdf_data_reg[37] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [37]), .Q(wdf_data[37]), .R(1'b0)); FDRE \wdf_data_reg[38] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [38]), .Q(wdf_data[38]), .R(1'b0)); FDRE \wdf_data_reg[39] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [39]), .Q(wdf_data[39]), .R(1'b0)); FDRE \wdf_data_reg[3] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [3]), .Q(wdf_data[3]), .R(1'b0)); FDRE \wdf_data_reg[40] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [40]), .Q(wdf_data[40]), .R(1'b0)); FDRE \wdf_data_reg[41] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [41]), .Q(wdf_data[41]), .R(1'b0)); FDRE \wdf_data_reg[42] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [42]), .Q(wdf_data[42]), .R(1'b0)); FDRE \wdf_data_reg[43] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [43]), .Q(wdf_data[43]), .R(1'b0)); FDRE \wdf_data_reg[44] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [44]), .Q(wdf_data[44]), .R(1'b0)); FDRE \wdf_data_reg[45] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [45]), .Q(wdf_data[45]), .R(1'b0)); FDRE \wdf_data_reg[46] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [46]), .Q(wdf_data[46]), .R(1'b0)); FDRE \wdf_data_reg[47] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [47]), .Q(wdf_data[47]), .R(1'b0)); FDRE \wdf_data_reg[48] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [48]), .Q(wdf_data[48]), .R(1'b0)); FDRE \wdf_data_reg[49] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [49]), .Q(wdf_data[49]), .R(1'b0)); FDRE \wdf_data_reg[4] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [4]), .Q(wdf_data[4]), .R(1'b0)); FDRE \wdf_data_reg[50] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [50]), .Q(wdf_data[50]), .R(1'b0)); FDRE \wdf_data_reg[51] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [51]), .Q(wdf_data[51]), .R(1'b0)); FDRE \wdf_data_reg[52] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [52]), .Q(wdf_data[52]), .R(1'b0)); FDRE \wdf_data_reg[53] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [53]), .Q(wdf_data[53]), .R(1'b0)); FDRE \wdf_data_reg[54] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [54]), .Q(wdf_data[54]), .R(1'b0)); FDRE \wdf_data_reg[55] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [55]), .Q(wdf_data[55]), .R(1'b0)); FDRE \wdf_data_reg[56] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [56]), .Q(wdf_data[56]), .R(1'b0)); FDRE \wdf_data_reg[57] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [57]), .Q(wdf_data[57]), .R(1'b0)); FDRE \wdf_data_reg[58] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [58]), .Q(wdf_data[58]), .R(1'b0)); FDRE \wdf_data_reg[59] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [59]), .Q(wdf_data[59]), .R(1'b0)); FDRE \wdf_data_reg[5] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [5]), .Q(wdf_data[5]), .R(1'b0)); FDRE \wdf_data_reg[60] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [60]), .Q(wdf_data[60]), .R(1'b0)); FDRE \wdf_data_reg[61] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [61]), .Q(wdf_data[61]), .R(1'b0)); FDRE \wdf_data_reg[62] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [62]), .Q(wdf_data[62]), .R(1'b0)); FDRE \wdf_data_reg[63] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [63]), .Q(wdf_data[63]), .R(1'b0)); FDRE \wdf_data_reg[64] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [64]), .Q(wdf_data[64]), .R(1'b0)); FDRE \wdf_data_reg[65] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [65]), .Q(wdf_data[65]), .R(1'b0)); FDRE \wdf_data_reg[66] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [66]), .Q(wdf_data[66]), .R(1'b0)); FDRE \wdf_data_reg[67] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [67]), .Q(wdf_data[67]), .R(1'b0)); FDRE \wdf_data_reg[68] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [68]), .Q(wdf_data[68]), .R(1'b0)); FDRE \wdf_data_reg[69] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [69]), .Q(wdf_data[69]), .R(1'b0)); FDRE \wdf_data_reg[6] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [6]), .Q(wdf_data[6]), .R(1'b0)); FDRE \wdf_data_reg[70] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [70]), .Q(wdf_data[70]), .R(1'b0)); FDRE \wdf_data_reg[71] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [71]), .Q(wdf_data[71]), .R(1'b0)); FDRE \wdf_data_reg[72] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [72]), .Q(wdf_data[72]), .R(1'b0)); FDRE \wdf_data_reg[73] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [73]), .Q(wdf_data[73]), .R(1'b0)); FDRE \wdf_data_reg[74] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [74]), .Q(wdf_data[74]), .R(1'b0)); FDRE \wdf_data_reg[75] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [75]), .Q(wdf_data[75]), .R(1'b0)); FDRE \wdf_data_reg[76] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [76]), .Q(wdf_data[76]), .R(1'b0)); FDRE \wdf_data_reg[77] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [77]), .Q(wdf_data[77]), .R(1'b0)); FDRE \wdf_data_reg[78] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [78]), .Q(wdf_data[78]), .R(1'b0)); FDRE \wdf_data_reg[79] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [79]), .Q(wdf_data[79]), .R(1'b0)); FDRE \wdf_data_reg[7] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [7]), .Q(wdf_data[7]), .R(1'b0)); FDRE \wdf_data_reg[80] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [80]), .Q(wdf_data[80]), .R(1'b0)); FDRE \wdf_data_reg[81] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [81]), .Q(wdf_data[81]), .R(1'b0)); FDRE \wdf_data_reg[82] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [82]), .Q(wdf_data[82]), .R(1'b0)); FDRE \wdf_data_reg[83] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [83]), .Q(wdf_data[83]), .R(1'b0)); FDRE \wdf_data_reg[84] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [84]), .Q(wdf_data[84]), .R(1'b0)); FDRE \wdf_data_reg[85] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [85]), .Q(wdf_data[85]), .R(1'b0)); FDRE \wdf_data_reg[86] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [86]), .Q(wdf_data[86]), .R(1'b0)); FDRE \wdf_data_reg[87] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [87]), .Q(wdf_data[87]), .R(1'b0)); FDRE \wdf_data_reg[88] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [88]), .Q(wdf_data[88]), .R(1'b0)); FDRE \wdf_data_reg[89] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [89]), .Q(wdf_data[89]), .R(1'b0)); FDRE \wdf_data_reg[8] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [8]), .Q(wdf_data[8]), .R(1'b0)); FDRE \wdf_data_reg[90] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [90]), .Q(wdf_data[90]), .R(1'b0)); FDRE \wdf_data_reg[91] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [91]), .Q(wdf_data[91]), .R(1'b0)); FDRE \wdf_data_reg[92] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [92]), .Q(wdf_data[92]), .R(1'b0)); FDRE \wdf_data_reg[93] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [93]), .Q(wdf_data[93]), .R(1'b0)); FDRE \wdf_data_reg[94] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [94]), .Q(wdf_data[94]), .R(1'b0)); FDRE \wdf_data_reg[95] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [95]), .Q(wdf_data[95]), .R(1'b0)); FDRE \wdf_data_reg[96] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [96]), .Q(wdf_data[96]), .R(1'b0)); FDRE \wdf_data_reg[97] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [97]), .Q(wdf_data[97]), .R(1'b0)); FDRE \wdf_data_reg[98] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [98]), .Q(wdf_data[98]), .R(1'b0)); FDRE \wdf_data_reg[99] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [99]), .Q(wdf_data[99]), .R(1'b0)); FDRE \wdf_data_reg[9] (.C(CLK), .CE(1'b1), .D(\mc_app_wdf_data_reg_reg[255]_0 [9]), .Q(wdf_data[9]), .R(1'b0)); FDRE \wdf_mask_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(wdf_mask[0]), .R(1'b0)); FDRE \wdf_mask_reg[10] (.C(CLK), .CE(1'b1), .D(D[10]), .Q(wdf_mask[10]), .R(1'b0)); FDRE \wdf_mask_reg[11] (.C(CLK), .CE(1'b1), .D(D[11]), .Q(wdf_mask[11]), .R(1'b0)); FDRE \wdf_mask_reg[12] (.C(CLK), .CE(1'b1), .D(D[12]), .Q(wdf_mask[12]), .R(1'b0)); FDRE \wdf_mask_reg[13] (.C(CLK), .CE(1'b1), .D(D[13]), .Q(wdf_mask[13]), .R(1'b0)); FDRE \wdf_mask_reg[14] (.C(CLK), .CE(1'b1), .D(D[14]), .Q(wdf_mask[14]), .R(1'b0)); FDRE \wdf_mask_reg[15] (.C(CLK), .CE(1'b1), .D(D[15]), .Q(wdf_mask[15]), .R(1'b0)); FDRE \wdf_mask_reg[16] (.C(CLK), .CE(1'b1), .D(D[16]), .Q(wdf_mask[16]), .R(1'b0)); FDRE \wdf_mask_reg[17] (.C(CLK), .CE(1'b1), .D(D[17]), .Q(wdf_mask[17]), .R(1'b0)); FDRE \wdf_mask_reg[18] (.C(CLK), .CE(1'b1), .D(D[18]), .Q(wdf_mask[18]), .R(1'b0)); FDRE \wdf_mask_reg[19] (.C(CLK), .CE(1'b1), .D(D[19]), .Q(wdf_mask[19]), .R(1'b0)); FDRE \wdf_mask_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(wdf_mask[1]), .R(1'b0)); FDRE \wdf_mask_reg[20] (.C(CLK), .CE(1'b1), .D(D[20]), .Q(wdf_mask[20]), .R(1'b0)); FDRE \wdf_mask_reg[21] (.C(CLK), .CE(1'b1), .D(D[21]), .Q(wdf_mask[21]), .R(1'b0)); FDRE \wdf_mask_reg[22] (.C(CLK), .CE(1'b1), .D(D[22]), .Q(wdf_mask[22]), .R(1'b0)); FDRE \wdf_mask_reg[23] (.C(CLK), .CE(1'b1), .D(D[23]), .Q(wdf_mask[23]), .R(1'b0)); FDRE \wdf_mask_reg[24] (.C(CLK), .CE(1'b1), .D(D[24]), .Q(wdf_mask[24]), .R(1'b0)); FDRE \wdf_mask_reg[25] (.C(CLK), .CE(1'b1), .D(D[25]), .Q(wdf_mask[25]), .R(1'b0)); FDRE \wdf_mask_reg[26] (.C(CLK), .CE(1'b1), .D(D[26]), .Q(wdf_mask[26]), .R(1'b0)); FDRE \wdf_mask_reg[27] (.C(CLK), .CE(1'b1), .D(D[27]), .Q(wdf_mask[27]), .R(1'b0)); FDRE \wdf_mask_reg[28] (.C(CLK), .CE(1'b1), .D(D[28]), .Q(wdf_mask[28]), .R(1'b0)); FDRE \wdf_mask_reg[29] (.C(CLK), .CE(1'b1), .D(D[29]), .Q(wdf_mask[29]), .R(1'b0)); FDRE \wdf_mask_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(wdf_mask[2]), .R(1'b0)); FDRE \wdf_mask_reg[30] (.C(CLK), .CE(1'b1), .D(D[30]), .Q(wdf_mask[30]), .R(1'b0)); FDRE \wdf_mask_reg[31] (.C(CLK), .CE(1'b1), .D(D[31]), .Q(wdf_mask[31]), .R(1'b0)); FDRE \wdf_mask_reg[3] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(wdf_mask[3]), .R(1'b0)); FDRE \wdf_mask_reg[4] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(wdf_mask[4]), .R(1'b0)); FDRE \wdf_mask_reg[5] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(wdf_mask[5]), .R(1'b0)); FDRE \wdf_mask_reg[6] (.C(CLK), .CE(1'b1), .D(D[6]), .Q(wdf_mask[6]), .R(1'b0)); FDRE \wdf_mask_reg[7] (.C(CLK), .CE(1'b1), .D(D[7]), .Q(wdf_mask[7]), .R(1'b0)); FDRE \wdf_mask_reg[8] (.C(CLK), .CE(1'b1), .D(D[8]), .Q(wdf_mask[8]), .R(1'b0)); FDRE \wdf_mask_reg[9] (.C(CLK), .CE(1'b1), .D(D[9]), .Q(wdf_mask[9]), .R(1'b0)); LUT4 #( .INIT(16'hABFB)) wready_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_i_1_n_0)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE wready_reg (.C(CLK), .CE(1'b1), .D(wready_i_1_n_0), .Q(s_axi_wready), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE wready_reg_rep (.C(CLK), .CE(1'b1), .D(wready_rep_i_1_n_0), .Q(wready_reg_rep_n_0), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE wready_reg_rep__0 (.C(CLK), .CE(1'b1), .D(wready_rep__0_i_1_n_0), .Q(wready_reg_rep__0_n_0), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE wready_reg_rep__1 (.C(CLK), .CE(1'b1), .D(wready_rep__1_i_1_n_0), .Q(wready_reg_rep__1_n_0), .R(areset_d1)); (* ORIG_CELL_NAME = "wready_reg" *) FDRE wready_reg_rep__2 (.C(CLK), .CE(1'b1), .D(wready_rep__2_i_1_n_0), .Q(wready_reg_rep__2_n_0), .R(areset_d1)); LUT4 #( .INIT(16'hABFB)) wready_rep__0_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep__0_i_1_n_0)); LUT4 #( .INIT(16'hABFB)) wready_rep__1_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep__1_i_1_n_0)); LUT4 #( .INIT(16'hABFB)) wready_rep__2_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep__2_i_1_n_0)); LUT4 #( .INIT(16'hABFB)) wready_rep_i_1 (.I0(\RD_PRI_REG_STARVE.rnw_i_reg ), .I1(valid), .I2(s_axi_wready), .I3(s_axi_wvalid), .O(wready_rep_i_1_n_0)); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_wr_cmd_fsm (s_axi_awready, axlen_int, D, b_push, \axburst_reg[1] , \axlen_reg[7] , in0, \axaddr_incr_reg[29] , \app_addr_r1_reg[4] , \axaddr_reg[29] , \app_addr_r1_reg[5] , \app_addr_r1_reg[6] , \app_addr_r1_reg[7] , \app_addr_r1_reg[8] , \app_addr_r1_reg[9] , \app_addr_r1_reg[10] , \app_addr_r1_reg[11] , \app_addr_r1_reg[12] , \app_addr_r1_reg[13] , \app_addr_r1_reg[14] , \app_addr_r1_reg[15] , \app_addr_r1_reg[16] , \app_addr_r1_reg[17] , \app_addr_r1_reg[18] , \app_addr_r1_reg[19] , \app_addr_r1_reg[20] , \app_addr_r1_reg[21] , \app_addr_r1_reg[22] , \app_addr_r1_reg[23] , \app_addr_r1_reg[24] , \app_addr_r1_reg[25] , \app_addr_r1_reg[26] , \app_addr_r1_reg[27] , S, \app_addr_r1_reg[3] , \axaddr_incr_reg[29]_0 , \int_addr_reg[3] , \axlen_cnt_reg[3] , awvalid_int, b_awid, E, \axlen_cnt_reg[0] , \axaddr_incr_reg[11] , areset_d1, CLK, Q, axready_reg_0, \axlen_reg[7]_0 , s_axi_awlen, axvalid, s_axi_awvalid, \RD_PRI_REG_STARVE.rnw_i_reg , s_axi_awaddr, \axaddr_reg[29]_0 , \axaddr_incr_reg[29]_1 , \int_addr_reg[3]_0 , out, axready_reg_1, \int_addr_reg[3]_1 , \axlen_cnt_reg[3]_0 , axburst, s_axi_awburst, \RD_PRI_REG_STARVE.rnw_i_reg_0 , s_axi_awid, axid); output s_axi_awready; output [3:0]axlen_int; output [7:0]D; output b_push; output \axburst_reg[1] ; output [3:0]\axlen_reg[7] ; output [3:0]in0; output [24:0]\axaddr_incr_reg[29] ; output \app_addr_r1_reg[4] ; output [29:0]\axaddr_reg[29] ; output \app_addr_r1_reg[5] ; output [0:0]\app_addr_r1_reg[6] ; output \app_addr_r1_reg[7] ; output \app_addr_r1_reg[8] ; output \app_addr_r1_reg[9] ; output \app_addr_r1_reg[10] ; output \app_addr_r1_reg[11] ; output \app_addr_r1_reg[12] ; output \app_addr_r1_reg[13] ; output \app_addr_r1_reg[14] ; output \app_addr_r1_reg[15] ; output \app_addr_r1_reg[16] ; output \app_addr_r1_reg[17] ; output \app_addr_r1_reg[18] ; output \app_addr_r1_reg[19] ; output \app_addr_r1_reg[20] ; output \app_addr_r1_reg[21] ; output \app_addr_r1_reg[22] ; output \app_addr_r1_reg[23] ; output \app_addr_r1_reg[24] ; output \app_addr_r1_reg[25] ; output \app_addr_r1_reg[26] ; output \app_addr_r1_reg[27] ; output [0:0]S; output \app_addr_r1_reg[3] ; output [29:0]\axaddr_incr_reg[29]_0 ; output [3:0]\int_addr_reg[3] ; output [3:0]\axlen_cnt_reg[3] ; output awvalid_int; output b_awid; output [0:0]E; output [0:0]\axlen_cnt_reg[0] ; output [0:0]\axaddr_incr_reg[11] ; input areset_d1; input CLK; input [7:0]Q; input axready_reg_0; input [7:0]\axlen_reg[7]_0 ; input [7:0]s_axi_awlen; input axvalid; input s_axi_awvalid; input \RD_PRI_REG_STARVE.rnw_i_reg ; input [29:0]s_axi_awaddr; input [29:0]\axaddr_reg[29]_0 ; input [29:0]\axaddr_incr_reg[29]_1 ; input \int_addr_reg[3]_0 ; input [29:0]out; input axready_reg_1; input [3:0]\int_addr_reg[3]_1 ; input [3:0]\axlen_cnt_reg[3]_0 ; input [0:0]axburst; input [0:0]s_axi_awburst; input \RD_PRI_REG_STARVE.rnw_i_reg_0 ; input [0:0]s_axi_awid; input axid; wire CLK; wire [7:0]D; wire [0:0]E; wire [7:0]Q; wire \RD_PRI_REG_STARVE.rnw_i_reg ; wire \RD_PRI_REG_STARVE.rnw_i_reg_0 ; wire [0:0]S; wire \app_addr_r1[6]_i_3_n_0 ; wire \app_addr_r1[6]_i_5_n_0 ; wire \app_addr_r1_reg[10] ; wire \app_addr_r1_reg[11] ; wire \app_addr_r1_reg[12] ; wire \app_addr_r1_reg[13] ; wire \app_addr_r1_reg[14] ; wire \app_addr_r1_reg[15] ; wire \app_addr_r1_reg[16] ; wire \app_addr_r1_reg[17] ; wire \app_addr_r1_reg[18] ; wire \app_addr_r1_reg[19] ; wire \app_addr_r1_reg[20] ; wire \app_addr_r1_reg[21] ; wire \app_addr_r1_reg[22] ; wire \app_addr_r1_reg[23] ; wire \app_addr_r1_reg[24] ; wire \app_addr_r1_reg[25] ; wire \app_addr_r1_reg[26] ; wire \app_addr_r1_reg[27] ; wire \app_addr_r1_reg[3] ; wire \app_addr_r1_reg[4] ; wire \app_addr_r1_reg[5] ; wire [0:0]\app_addr_r1_reg[6] ; wire \app_addr_r1_reg[7] ; wire \app_addr_r1_reg[8] ; wire \app_addr_r1_reg[9] ; wire areset_d1; wire awvalid_int; wire [0:0]\axaddr_incr_reg[11] ; wire [24:0]\axaddr_incr_reg[29] ; wire [29:0]\axaddr_incr_reg[29]_0 ; wire [29:0]\axaddr_incr_reg[29]_1 ; wire [29:0]\axaddr_reg[29] ; wire [29:0]\axaddr_reg[29]_0 ; wire [0:0]axburst; wire \axburst_reg[1] ; wire [8:5]\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ; wire \axi_mc_cmd_translator_0/incr_axhandshake ; wire \axi_mc_cmd_translator_0/wrap_axhandshake ; wire [8:8]axi_mc_incr_cmd_byte_addr__0; wire axid; wire \axlen_cnt[2]_i_2__0_n_0 ; wire \axlen_cnt[2]_i_2_n_0 ; wire \axlen_cnt[3]_i_2__0_n_0 ; wire \axlen_cnt[3]_i_2_n_0 ; wire \axlen_cnt[4]_i_2_n_0 ; wire \axlen_cnt[4]_i_3_n_0 ; wire \axlen_cnt[5]_i_2_n_0 ; wire \axlen_cnt[5]_i_3_n_0 ; wire \axlen_cnt[7]_i_3_n_0 ; wire \axlen_cnt[7]_i_4_n_0 ; wire [0:0]\axlen_cnt_reg[0] ; wire [3:0]\axlen_cnt_reg[3] ; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [3:0]axlen_int; wire [3:0]\axlen_reg[7] ; wire [7:0]\axlen_reg[7]_0 ; wire axready_i_1_n_0; wire axready_reg_0; wire axready_reg_1; wire axvalid; wire b_awid; wire b_push; wire [3:0]in0; wire \int_addr[3]_i_5_n_0 ; wire [3:0]\int_addr_reg[3] ; wire \int_addr_reg[3]_0 ; wire [3:0]\int_addr_reg[3]_1 ; wire \memory_reg[7][0]_srl8_i_2_n_0 ; wire \memory_reg[7][0]_srl8_i_3_n_0 ; wire \memory_reg[7][0]_srl8_i_4_n_0 ; wire \memory_reg[7][0]_srl8_i_5_n_0 ; wire [29:0]out; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[10]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [12]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [12]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[10] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[11]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [13]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [13]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[11] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[12]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [14]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [14]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[12] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[13]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [15]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [15]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[13] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[14]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [16]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [16]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[14] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[15]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [17]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [17]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[15] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[16]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [18]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [18]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[16] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[17]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [19]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [19]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[17] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[18]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [20]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [20]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[18] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[19]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [21]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [21]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[19] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[20]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [22]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [22]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[20] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[21]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [23]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [23]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[21] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[22]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [24]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [24]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[22] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[23]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [25]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [25]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[23] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[24]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [26]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [26]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[24] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[25]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [27]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [27]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[25] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[26]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [28]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [28]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[26] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[27]_i_5 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [29]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [29]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[27] )); LUT6 #( .INIT(64'hF8FFF88888888888)) \app_addr_r1[3]_i_3 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I1(\app_addr_r1[6]_i_5_n_0 ), .I2(\axaddr_reg[29] [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .I5(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[3] )); LUT6 #( .INIT(64'hF8FFF88888888888)) \app_addr_r1[4]_i_4 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]), .I1(\app_addr_r1[6]_i_5_n_0 ), .I2(\axaddr_reg[29] [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .I5(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair1163" *) LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[4]_i_5 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [1]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6])); LUT6 #( .INIT(64'hF8FFF88888888888)) \app_addr_r1[5]_i_3 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I1(\app_addr_r1[6]_i_5_n_0 ), .I2(\axaddr_reg[29] [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .I5(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[5] )); LUT5 #( .INIT(32'hFFEAEAEA)) \app_addr_r1[6]_i_1 (.I0(\int_addr_reg[3]_0 ), .I1(\app_addr_r1[6]_i_3_n_0 ), .I2(axi_mc_incr_cmd_byte_addr__0), .I3(\app_addr_r1[6]_i_5_n_0 ), .I4(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]), .O(\app_addr_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair1169" *) LUT4 #( .INIT(16'h001D)) \app_addr_r1[6]_i_3 (.I0(axburst), .I1(s_axi_awready), .I2(s_axi_awburst), .I3(\RD_PRI_REG_STARVE.rnw_i_reg_0 ), .O(\app_addr_r1[6]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \app_addr_r1[6]_i_4 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [8]), .O(axi_mc_incr_cmd_byte_addr__0)); (* SOFT_HLUTNM = "soft_lutpair1169" *) LUT4 #( .INIT(16'h00E2)) \app_addr_r1[6]_i_5 (.I0(axburst), .I1(s_axi_awready), .I2(s_axi_awburst), .I3(\RD_PRI_REG_STARVE.rnw_i_reg_0 ), .O(\app_addr_r1[6]_i_5_n_0 )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[7]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [9]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [9]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[7] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[8]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [10]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [10]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[8] )); LUT5 #( .INIT(32'hCFC88888)) \app_addr_r1[9]_i_2 (.I0(\app_addr_r1[6]_i_5_n_0 ), .I1(\axaddr_reg[29] [11]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axaddr_incr_reg[29]_1 [11]), .I4(\app_addr_r1[6]_i_3_n_0 ), .O(\app_addr_r1_reg[9] )); (* SOFT_HLUTNM = "soft_lutpair1165" *) LUT3 #( .INIT(8'hB8)) \axaddr[0]_i_1 (.I0(s_axi_awaddr[0]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [0]), .O(\axaddr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1180" *) LUT3 #( .INIT(8'hB8)) \axaddr[10]_i_1 (.I0(s_axi_awaddr[10]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [10]), .O(\axaddr_reg[29] [10])); (* SOFT_HLUTNM = "soft_lutpair1180" *) LUT3 #( .INIT(8'hB8)) \axaddr[11]_i_1 (.I0(s_axi_awaddr[11]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [11]), .O(\axaddr_reg[29] [11])); (* SOFT_HLUTNM = "soft_lutpair1179" *) LUT3 #( .INIT(8'hB8)) \axaddr[12]_i_1 (.I0(s_axi_awaddr[12]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [12]), .O(\axaddr_reg[29] [12])); (* SOFT_HLUTNM = "soft_lutpair1179" *) LUT3 #( .INIT(8'hB8)) \axaddr[13]_i_1 (.I0(s_axi_awaddr[13]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [13]), .O(\axaddr_reg[29] [13])); (* SOFT_HLUTNM = "soft_lutpair1178" *) LUT3 #( .INIT(8'hB8)) \axaddr[14]_i_1 (.I0(s_axi_awaddr[14]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [14]), .O(\axaddr_reg[29] [14])); (* SOFT_HLUTNM = "soft_lutpair1178" *) LUT3 #( .INIT(8'hB8)) \axaddr[15]_i_1 (.I0(s_axi_awaddr[15]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [15]), .O(\axaddr_reg[29] [15])); (* SOFT_HLUTNM = "soft_lutpair1177" *) LUT3 #( .INIT(8'hB8)) \axaddr[16]_i_1 (.I0(s_axi_awaddr[16]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [16]), .O(\axaddr_reg[29] [16])); (* SOFT_HLUTNM = "soft_lutpair1177" *) LUT3 #( .INIT(8'hB8)) \axaddr[17]_i_1 (.I0(s_axi_awaddr[17]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [17]), .O(\axaddr_reg[29] [17])); (* SOFT_HLUTNM = "soft_lutpair1176" *) LUT3 #( .INIT(8'hB8)) \axaddr[18]_i_1 (.I0(s_axi_awaddr[18]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [18]), .O(\axaddr_reg[29] [18])); (* SOFT_HLUTNM = "soft_lutpair1176" *) LUT3 #( .INIT(8'hB8)) \axaddr[19]_i_1 (.I0(s_axi_awaddr[19]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [19]), .O(\axaddr_reg[29] [19])); (* SOFT_HLUTNM = "soft_lutpair1166" *) LUT3 #( .INIT(8'hB8)) \axaddr[1]_i_1 (.I0(s_axi_awaddr[1]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [1]), .O(\axaddr_reg[29] [1])); (* SOFT_HLUTNM = "soft_lutpair1175" *) LUT3 #( .INIT(8'hB8)) \axaddr[20]_i_1 (.I0(s_axi_awaddr[20]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [20]), .O(\axaddr_reg[29] [20])); (* SOFT_HLUTNM = "soft_lutpair1175" *) LUT3 #( .INIT(8'hB8)) \axaddr[21]_i_1 (.I0(s_axi_awaddr[21]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [21]), .O(\axaddr_reg[29] [21])); (* SOFT_HLUTNM = "soft_lutpair1174" *) LUT3 #( .INIT(8'hB8)) \axaddr[22]_i_1 (.I0(s_axi_awaddr[22]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [22]), .O(\axaddr_reg[29] [22])); (* SOFT_HLUTNM = "soft_lutpair1174" *) LUT3 #( .INIT(8'hB8)) \axaddr[23]_i_1 (.I0(s_axi_awaddr[23]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [23]), .O(\axaddr_reg[29] [23])); (* SOFT_HLUTNM = "soft_lutpair1173" *) LUT3 #( .INIT(8'hB8)) \axaddr[24]_i_1 (.I0(s_axi_awaddr[24]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [24]), .O(\axaddr_reg[29] [24])); (* SOFT_HLUTNM = "soft_lutpair1173" *) LUT3 #( .INIT(8'hB8)) \axaddr[25]_i_1 (.I0(s_axi_awaddr[25]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [25]), .O(\axaddr_reg[29] [25])); (* SOFT_HLUTNM = "soft_lutpair1172" *) LUT3 #( .INIT(8'hB8)) \axaddr[26]_i_1 (.I0(s_axi_awaddr[26]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [26]), .O(\axaddr_reg[29] [26])); (* SOFT_HLUTNM = "soft_lutpair1172" *) LUT3 #( .INIT(8'hB8)) \axaddr[27]_i_1 (.I0(s_axi_awaddr[27]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [27]), .O(\axaddr_reg[29] [27])); (* SOFT_HLUTNM = "soft_lutpair1171" *) LUT3 #( .INIT(8'hB8)) \axaddr[28]_i_1 (.I0(s_axi_awaddr[28]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [28]), .O(\axaddr_reg[29] [28])); (* SOFT_HLUTNM = "soft_lutpair1171" *) LUT3 #( .INIT(8'hB8)) \axaddr[29]_i_1 (.I0(s_axi_awaddr[29]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [29]), .O(\axaddr_reg[29] [29])); (* SOFT_HLUTNM = "soft_lutpair1167" *) LUT3 #( .INIT(8'hB8)) \axaddr[2]_i_1 (.I0(s_axi_awaddr[2]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [2]), .O(\axaddr_reg[29] [2])); (* SOFT_HLUTNM = "soft_lutpair1168" *) LUT3 #( .INIT(8'hB8)) \axaddr[3]_i_1 (.I0(s_axi_awaddr[3]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [3]), .O(\axaddr_reg[29] [3])); (* SOFT_HLUTNM = "soft_lutpair1182" *) LUT3 #( .INIT(8'hB8)) \axaddr[4]_i_1 (.I0(s_axi_awaddr[4]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [4]), .O(\axaddr_reg[29] [4])); (* SOFT_HLUTNM = "soft_lutpair1164" *) LUT3 #( .INIT(8'hB8)) \axaddr[5]_i_1 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .O(\axaddr_reg[29] [5])); (* SOFT_HLUTNM = "soft_lutpair1163" *) LUT3 #( .INIT(8'hB8)) \axaddr[6]_i_1 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .O(\axaddr_reg[29] [6])); (* SOFT_HLUTNM = "soft_lutpair1162" *) LUT3 #( .INIT(8'hB8)) \axaddr[7]_i_1 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .O(\axaddr_reg[29] [7])); (* SOFT_HLUTNM = "soft_lutpair1161" *) LUT3 #( .INIT(8'hB8)) \axaddr[8]_i_1 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .O(\axaddr_reg[29] [8])); (* SOFT_HLUTNM = "soft_lutpair1181" *) LUT3 #( .INIT(8'hB8)) \axaddr[9]_i_1 (.I0(s_axi_awaddr[9]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [9]), .O(\axaddr_reg[29] [9])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[0]_i_1 (.I0(s_axi_awaddr[0]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [0]), .I3(axready_reg_0), .I4(out[0]), .O(\axaddr_incr_reg[29]_0 [0])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[10]_i_1 (.I0(s_axi_awaddr[10]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [10]), .I3(axready_reg_0), .I4(out[10]), .O(\axaddr_incr_reg[29]_0 [10])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[11]_i_1 (.I0(s_axi_awaddr[11]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [11]), .I3(axready_reg_0), .I4(out[11]), .O(\axaddr_incr_reg[29]_0 [11])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[12]_i_1 (.I0(s_axi_awaddr[12]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [12]), .I3(axready_reg_0), .I4(out[12]), .O(\axaddr_incr_reg[29]_0 [12])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[13]_i_1 (.I0(s_axi_awaddr[13]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [13]), .I3(axready_reg_0), .I4(out[13]), .O(\axaddr_incr_reg[29]_0 [13])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[14]_i_1 (.I0(s_axi_awaddr[14]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [14]), .I3(axready_reg_0), .I4(out[14]), .O(\axaddr_incr_reg[29]_0 [14])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[15]_i_1 (.I0(s_axi_awaddr[15]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [15]), .I3(axready_reg_0), .I4(out[15]), .O(\axaddr_incr_reg[29]_0 [15])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[16]_i_1 (.I0(s_axi_awaddr[16]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [16]), .I3(axready_reg_0), .I4(out[16]), .O(\axaddr_incr_reg[29]_0 [16])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[17]_i_1 (.I0(s_axi_awaddr[17]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [17]), .I3(axready_reg_0), .I4(out[17]), .O(\axaddr_incr_reg[29]_0 [17])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[18]_i_1 (.I0(s_axi_awaddr[18]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [18]), .I3(axready_reg_0), .I4(out[18]), .O(\axaddr_incr_reg[29]_0 [18])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[19]_i_1 (.I0(s_axi_awaddr[19]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [19]), .I3(axready_reg_0), .I4(out[19]), .O(\axaddr_incr_reg[29]_0 [19])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[1]_i_1 (.I0(s_axi_awaddr[1]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [1]), .I3(axready_reg_0), .I4(out[1]), .O(\axaddr_incr_reg[29]_0 [1])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[20]_i_1 (.I0(s_axi_awaddr[20]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [20]), .I3(axready_reg_0), .I4(out[20]), .O(\axaddr_incr_reg[29]_0 [20])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[21]_i_1 (.I0(s_axi_awaddr[21]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [21]), .I3(axready_reg_0), .I4(out[21]), .O(\axaddr_incr_reg[29]_0 [21])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[22]_i_1 (.I0(s_axi_awaddr[22]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [22]), .I3(axready_reg_0), .I4(out[22]), .O(\axaddr_incr_reg[29]_0 [22])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[23]_i_1 (.I0(s_axi_awaddr[23]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [23]), .I3(axready_reg_0), .I4(out[23]), .O(\axaddr_incr_reg[29]_0 [23])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[24]_i_1 (.I0(s_axi_awaddr[24]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [24]), .I3(axready_reg_0), .I4(out[24]), .O(\axaddr_incr_reg[29]_0 [24])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[25]_i_1 (.I0(s_axi_awaddr[25]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [25]), .I3(axready_reg_0), .I4(out[25]), .O(\axaddr_incr_reg[29]_0 [25])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[26]_i_1 (.I0(s_axi_awaddr[26]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [26]), .I3(axready_reg_0), .I4(out[26]), .O(\axaddr_incr_reg[29]_0 [26])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[27]_i_1 (.I0(s_axi_awaddr[27]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [27]), .I3(axready_reg_0), .I4(out[27]), .O(\axaddr_incr_reg[29]_0 [27])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[28]_i_1 (.I0(s_axi_awaddr[28]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [28]), .I3(axready_reg_0), .I4(out[28]), .O(\axaddr_incr_reg[29]_0 [28])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[29]_i_1 (.I0(s_axi_awaddr[29]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [29]), .I3(axready_reg_0), .I4(out[29]), .O(\axaddr_incr_reg[29]_0 [29])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[2]_i_1 (.I0(s_axi_awaddr[2]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [2]), .I3(axready_reg_0), .I4(out[2]), .O(\axaddr_incr_reg[29]_0 [2])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[3]_i_1 (.I0(s_axi_awaddr[3]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [3]), .I3(axready_reg_0), .I4(out[3]), .O(\axaddr_incr_reg[29]_0 [3])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[4]_i_1 (.I0(s_axi_awaddr[4]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [4]), .I3(axready_reg_0), .I4(out[4]), .O(\axaddr_incr_reg[29]_0 [4])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[5]_i_1 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .I3(axready_reg_0), .I4(out[5]), .O(\axaddr_incr_reg[29]_0 [5])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[6]_i_1 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .I3(axready_reg_0), .I4(out[6]), .O(\axaddr_incr_reg[29]_0 [6])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[7]_i_1 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .I3(axready_reg_0), .I4(out[7]), .O(\axaddr_incr_reg[29]_0 [7])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[8]_i_1 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(axready_reg_0), .I4(out[8]), .O(\axaddr_incr_reg[29]_0 [8])); LUT5 #( .INIT(32'hB8FFB800)) \axaddr_incr[9]_i_1 (.I0(s_axi_awaddr[9]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [9]), .I3(axready_reg_0), .I4(out[9]), .O(\axaddr_incr_reg[29]_0 [9])); (* SOFT_HLUTNM = "soft_lutpair1168" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_1 (.I0(s_axi_awaddr[3]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [3]), .O(in0[3])); (* SOFT_HLUTNM = "soft_lutpair1167" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_2 (.I0(s_axi_awaddr[2]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [2]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [2]), .O(in0[2])); (* SOFT_HLUTNM = "soft_lutpair1166" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_3 (.I0(s_axi_awaddr[1]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [1]), .O(in0[1])); (* SOFT_HLUTNM = "soft_lutpair1165" *) LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_inferred_i_4 (.I0(s_axi_awaddr[0]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [0]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [0]), .O(in0[0])); LUT3 #( .INIT(8'h08)) axaddr_incr_p_inferred_i_5 (.I0(s_axi_awvalid), .I1(s_axi_awready), .I2(s_axi_awburst), .O(\axi_mc_cmd_translator_0/incr_axhandshake )); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_1 (.I0(s_axi_awaddr[11]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [11]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [11]), .O(\axaddr_incr_reg[29] [6])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_2 (.I0(s_axi_awaddr[10]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [10]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [10]), .O(\axaddr_incr_reg[29] [5])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_3 (.I0(s_axi_awaddr[9]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [9]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [9]), .O(\axaddr_incr_reg[29] [4])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__0_i_4__0 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [8]), .O(\axaddr_incr_reg[11] )); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_1 (.I0(s_axi_awaddr[15]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [15]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [15]), .O(\axaddr_incr_reg[29] [10])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_2 (.I0(s_axi_awaddr[14]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [14]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [14]), .O(\axaddr_incr_reg[29] [9])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_3 (.I0(s_axi_awaddr[13]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [13]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [13]), .O(\axaddr_incr_reg[29] [8])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__1_i_4 (.I0(s_axi_awaddr[12]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [12]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [12]), .O(\axaddr_incr_reg[29] [7])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_1 (.I0(s_axi_awaddr[19]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [19]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [19]), .O(\axaddr_incr_reg[29] [14])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_2 (.I0(s_axi_awaddr[18]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [18]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [18]), .O(\axaddr_incr_reg[29] [13])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_3 (.I0(s_axi_awaddr[17]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [17]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [17]), .O(\axaddr_incr_reg[29] [12])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__2_i_4 (.I0(s_axi_awaddr[16]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [16]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [16]), .O(\axaddr_incr_reg[29] [11])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_1 (.I0(s_axi_awaddr[23]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [23]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [23]), .O(\axaddr_incr_reg[29] [18])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_2 (.I0(s_axi_awaddr[22]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [22]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [22]), .O(\axaddr_incr_reg[29] [17])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_3 (.I0(s_axi_awaddr[21]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [21]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [21]), .O(\axaddr_incr_reg[29] [16])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__3_i_4 (.I0(s_axi_awaddr[20]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [20]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [20]), .O(\axaddr_incr_reg[29] [15])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_1 (.I0(s_axi_awaddr[27]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [27]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [27]), .O(\axaddr_incr_reg[29] [22])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_2 (.I0(s_axi_awaddr[26]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [26]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [26]), .O(\axaddr_incr_reg[29] [21])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_3 (.I0(s_axi_awaddr[25]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [25]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [25]), .O(\axaddr_incr_reg[29] [20])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__4_i_4 (.I0(s_axi_awaddr[24]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [24]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [24]), .O(\axaddr_incr_reg[29] [19])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_1 (.I0(s_axi_awaddr[29]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [29]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [29]), .O(\axaddr_incr_reg[29] [24])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry__5_i_2 (.I0(s_axi_awaddr[28]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [28]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [28]), .O(\axaddr_incr_reg[29] [23])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_1 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [5]), .O(\axaddr_incr_reg[29] [1])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_2 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [7]), .O(\axaddr_incr_reg[29] [3])); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_3 (.I0(s_axi_awaddr[6]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [6]), .O(\axaddr_incr_reg[29] [2])); LUT5 #( .INIT(32'h111DDD1D)) axaddr_incr_p_reg0_carry_i_4 (.I0(\axaddr_incr_reg[29]_1 [5]), .I1(\axi_mc_cmd_translator_0/incr_axhandshake ), .I2(\axaddr_reg[29]_0 [5]), .I3(s_axi_awready), .I4(s_axi_awaddr[5]), .O(S)); LUT5 #( .INIT(32'hB8FFB800)) axaddr_incr_p_reg0_carry_i_5 (.I0(s_axi_awaddr[4]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(\axaddr_incr_reg[29]_1 [4]), .O(\axaddr_incr_reg[29] [0])); (* SOFT_HLUTNM = "soft_lutpair1170" *) LUT3 #( .INIT(8'hB8)) \axburst[1]_i_1 (.I0(s_axi_awburst), .I1(s_axi_awready), .I2(axburst), .O(\axburst_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1170" *) LUT3 #( .INIT(8'hB8)) \axid[0]_i_1 (.I0(s_axi_awid), .I1(s_axi_awready), .I2(axid), .O(b_awid)); LUT3 #( .INIT(8'hB8)) \axlen[0]_i_1 (.I0(s_axi_awlen[0]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [0]), .O(axlen_int[0])); LUT3 #( .INIT(8'hB8)) \axlen[1]_i_1 (.I0(s_axi_awlen[1]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [1]), .O(axlen_int[1])); LUT3 #( .INIT(8'hB8)) \axlen[2]_i_1 (.I0(s_axi_awlen[2]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [2]), .O(axlen_int[2])); LUT3 #( .INIT(8'hB8)) \axlen[3]_i_1 (.I0(s_axi_awlen[3]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [3]), .O(axlen_int[3])); (* SOFT_HLUTNM = "soft_lutpair1183" *) LUT3 #( .INIT(8'hB8)) \axlen[4]_i_1 (.I0(s_axi_awlen[4]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [4]), .O(\axlen_reg[7] [0])); (* SOFT_HLUTNM = "soft_lutpair1183" *) LUT3 #( .INIT(8'hB8)) \axlen[5]_i_1 (.I0(s_axi_awlen[5]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [5]), .O(\axlen_reg[7] [1])); (* SOFT_HLUTNM = "soft_lutpair1182" *) LUT3 #( .INIT(8'hB8)) \axlen[6]_i_1 (.I0(s_axi_awlen[6]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [6]), .O(\axlen_reg[7] [2])); (* SOFT_HLUTNM = "soft_lutpair1181" *) LUT3 #( .INIT(8'hB8)) \axlen[7]_i_1 (.I0(s_axi_awlen[7]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [7]), .O(\axlen_reg[7] [3])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1 (.I0(axready_reg_0), .I1(Q[0]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7]_0 [0]), .I4(s_axi_awready), .I5(s_axi_awlen[0]), .O(D[0])); LUT6 #( .INIT(64'hABABAB515151AB51)) \axlen_cnt[0]_i_1__0 (.I0(axready_reg_1), .I1(\axlen_cnt_reg[3]_0 [0]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7]_0 [0]), .I4(s_axi_awready), .I5(s_axi_awlen[0]), .O(\axlen_cnt_reg[3] [0])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[1]), .I2(axlen_int[0]), .I3(Q[0]), .I4(axready_reg_0), .I5(axlen_int[1]), .O(D[1])); LUT6 #( .INIT(64'hFFFFE4B100004E1B)) \axlen_cnt[1]_i_1__0 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [1]), .I2(axlen_int[0]), .I3(\axlen_cnt_reg[3]_0 [0]), .I4(axready_reg_1), .I5(axlen_int[1]), .O(\axlen_cnt_reg[3] [1])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[2]), .I2(\axlen_cnt[2]_i_2_n_0 ), .I3(axready_reg_0), .I4(axlen_int[2]), .O(D[2])); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[2]_i_1__0 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axlen_cnt[2]_i_2__0_n_0 ), .I3(axready_reg_1), .I4(axlen_int[2]), .O(\axlen_cnt_reg[3] [2])); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2 (.I0(Q[0]), .I1(axlen_int[0]), .I2(Q[1]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(axlen_int[1]), .O(\axlen_cnt[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFACCFA)) \axlen_cnt[2]_i_2__0 (.I0(\axlen_cnt_reg[3]_0 [0]), .I1(axlen_int[0]), .I2(\axlen_cnt_reg[3]_0 [1]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(axlen_int[1]), .O(\axlen_cnt[2]_i_2__0_n_0 )); LUT5 #( .INIT(32'hFFE1004B)) \axlen_cnt[3]_i_1 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[3]), .I2(\axlen_cnt[3]_i_2_n_0 ), .I3(axready_reg_0), .I4(axlen_int[3]), .O(D[3])); LUT5 #( .INIT(32'hFF1E00B4)) \axlen_cnt[3]_i_1__0 (.I0(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I1(\axlen_cnt_reg[3]_0 [3]), .I2(\axlen_cnt[3]_i_2__0_n_0 ), .I3(axready_reg_1), .I4(axlen_int[3]), .O(\axlen_cnt_reg[3] [3])); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \axlen_cnt[3]_i_2 (.I0(\axlen_cnt[2]_i_2_n_0 ), .I1(Q[2]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7]_0 [2]), .I4(s_axi_awready), .I5(s_axi_awlen[2]), .O(\axlen_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h0101015151510151)) \axlen_cnt[3]_i_2__0 (.I0(\axlen_cnt[2]_i_2__0_n_0 ), .I1(\axlen_cnt_reg[3]_0 [2]), .I2(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I3(\axlen_reg[7]_0 [2]), .I4(s_axi_awready), .I5(s_axi_awlen[2]), .O(\axlen_cnt[3]_i_2__0_n_0 )); LUT6 #( .INIT(64'hF606F6F6F6060606)) \axlen_cnt[4]_i_1 (.I0(\axlen_cnt[4]_i_2_n_0 ), .I1(\axlen_cnt[4]_i_3_n_0 ), .I2(axready_reg_0), .I3(s_axi_awlen[4]), .I4(s_axi_awready), .I5(\axlen_reg[7]_0 [4]), .O(D[4])); LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[4]_i_2 (.I0(s_axi_awlen[4]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [4]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[4]), .O(\axlen_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'h0101015151510151)) \axlen_cnt[4]_i_3 (.I0(\axlen_cnt[3]_i_2_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(\axlen_reg[7]_0 [3]), .I4(s_axi_awready), .I5(s_axi_awlen[3]), .O(\axlen_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[5]_i_1 (.I0(\axlen_cnt[5]_i_2_n_0 ), .I1(\axlen_cnt[5]_i_3_n_0 ), .I2(axready_reg_0), .I3(s_axi_awlen[5]), .I4(s_axi_awready), .I5(\axlen_reg[7]_0 [5]), .O(D[5])); LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[5]_i_2 (.I0(s_axi_awlen[5]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [5]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[5]), .O(\axlen_cnt[5]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFEFEA)) \axlen_cnt[5]_i_3 (.I0(\axlen_cnt[4]_i_2_n_0 ), .I1(axlen_int[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(Q[3]), .I4(\axlen_cnt[3]_i_2_n_0 ), .O(\axlen_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'hF909F9F9F9090909)) \axlen_cnt[6]_i_1 (.I0(\axlen_cnt[7]_i_3_n_0 ), .I1(\axlen_cnt[7]_i_4_n_0 ), .I2(axready_reg_0), .I3(s_axi_awlen[6]), .I4(s_axi_awready), .I5(\axlen_reg[7]_0 [6]), .O(D[6])); LUT5 #( .INIT(32'h0E000ECC)) \axlen_cnt[7]_i_1 (.I0(s_axi_awvalid), .I1(\RD_PRI_REG_STARVE.rnw_i_reg ), .I2(s_axi_awburst), .I3(s_axi_awready), .I4(axburst), .O(E)); LUT6 #( .INIT(64'hFFFFEEE10000444B)) \axlen_cnt[7]_i_2 (.I0(\axi_mc_cmd_translator_0/incr_axhandshake ), .I1(Q[7]), .I2(\axlen_cnt[7]_i_3_n_0 ), .I3(\axlen_cnt[7]_i_4_n_0 ), .I4(axready_reg_0), .I5(\axlen_reg[7] [3]), .O(D[7])); LUT5 #( .INIT(32'hB8FFB800)) \axlen_cnt[7]_i_3 (.I0(s_axi_awlen[6]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [6]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[6]), .O(\axlen_cnt[7]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEAE)) \axlen_cnt[7]_i_4 (.I0(\axlen_cnt[3]_i_2_n_0 ), .I1(Q[3]), .I2(\axi_mc_cmd_translator_0/incr_axhandshake ), .I3(axlen_int[3]), .I4(\axlen_cnt[4]_i_2_n_0 ), .I5(\axlen_cnt[5]_i_2_n_0 ), .O(\axlen_cnt[7]_i_4_n_0 )); LUT4 #( .INIT(16'hABFB)) axready_i_1 (.I0(b_push), .I1(axvalid), .I2(s_axi_awready), .I3(s_axi_awvalid), .O(axready_i_1_n_0)); FDRE axready_reg (.C(CLK), .CE(1'b1), .D(axready_i_1_n_0), .Q(s_axi_awready), .R(areset_d1)); LUT3 #( .INIT(8'hB8)) axvalid_i_1 (.I0(s_axi_awvalid), .I1(s_axi_awready), .I2(axvalid), .O(awvalid_int)); LUT6 #( .INIT(64'hF606F6F6F6060606)) \int_addr[0]_i_1 (.I0(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I1(axlen_int[0]), .I2(axready_reg_1), .I3(s_axi_awaddr[5]), .I4(s_axi_awready), .I5(\axaddr_reg[29]_0 [5]), .O(\int_addr_reg[3] [0])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[1]_i_1 (.I0(axready_reg_1), .I1(axlen_int[1]), .I2(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .I3(\int_addr_reg[3]_1 [1]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [6]), .O(\int_addr_reg[3] [1])); (* SOFT_HLUTNM = "soft_lutpair1164" *) LUT5 #( .INIT(32'hB8FFB800)) \int_addr[1]_i_2 (.I0(s_axi_awaddr[5]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [5]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [0]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5])); LUT6 #( .INIT(64'hBFBFBFEA40401540)) \int_addr[2]_i_1 (.I0(axready_reg_1), .I1(axlen_int[2]), .I2(\int_addr[3]_i_5_n_0 ), .I3(\int_addr_reg[3]_1 [2]), .I4(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I5(\axaddr_reg[29] [7]), .O(\int_addr_reg[3] [2])); LUT3 #( .INIT(8'h80)) \int_addr[2]_i_2 (.I0(s_axi_awvalid), .I1(s_axi_awready), .I2(s_axi_awburst), .O(\axi_mc_cmd_translator_0/wrap_axhandshake )); LUT5 #( .INIT(32'hCFC08080)) \int_addr[3]_i_1 (.I0(s_axi_awvalid), .I1(s_axi_awburst), .I2(s_axi_awready), .I3(axburst), .I4(\RD_PRI_REG_STARVE.rnw_i_reg ), .O(\axlen_cnt_reg[0] )); LUT6 #( .INIT(64'h8BBBBBBBB8888888)) \int_addr[3]_i_2 (.I0(\axaddr_reg[29] [8]), .I1(axready_reg_1), .I2(axlen_int[3]), .I3(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]), .I4(\int_addr[3]_i_5_n_0 ), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]), .O(\int_addr_reg[3] [3])); (* SOFT_HLUTNM = "soft_lutpair1162" *) LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_4 (.I0(s_axi_awaddr[7]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [7]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [2]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7])); LUT6 #( .INIT(64'hEEE222E200000000)) \int_addr[3]_i_5 (.I0(\int_addr_reg[3]_1 [1]), .I1(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I2(\axaddr_reg[29]_0 [6]), .I3(s_axi_awready), .I4(s_axi_awaddr[6]), .I5(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]), .O(\int_addr[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1161" *) LUT5 #( .INIT(32'hB8FFB800)) \int_addr[3]_i_6 (.I0(s_axi_awaddr[8]), .I1(s_axi_awready), .I2(\axaddr_reg[29]_0 [8]), .I3(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I4(\int_addr_reg[3]_1 [3]), .O(\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8])); LUT5 #( .INIT(32'hAA000C00)) \memory_reg[7][0]_srl8_i_1 (.I0(\memory_reg[7][0]_srl8_i_2_n_0 ), .I1(\memory_reg[7][0]_srl8_i_3_n_0 ), .I2(\axlen_cnt[3]_i_2_n_0 ), .I3(\RD_PRI_REG_STARVE.rnw_i_reg ), .I4(\axburst_reg[1] ), .O(b_push)); LUT6 #( .INIT(64'h0000000000440347)) \memory_reg[7][0]_srl8_i_2 (.I0(axlen_int[2]), .I1(\axi_mc_cmd_translator_0/wrap_axhandshake ), .I2(\axlen_cnt_reg[3]_0 [2]), .I3(axlen_int[3]), .I4(\axlen_cnt_reg[3]_0 [3]), .I5(\axlen_cnt[2]_i_2__0_n_0 ), .O(\memory_reg[7][0]_srl8_i_2_n_0 )); LUT5 #( .INIT(32'h00000001)) \memory_reg[7][0]_srl8_i_3 (.I0(\axlen_cnt[4]_i_2_n_0 ), .I1(\axlen_cnt[5]_i_2_n_0 ), .I2(\memory_reg[7][0]_srl8_i_4_n_0 ), .I3(\memory_reg[7][0]_srl8_i_5_n_0 ), .I4(\axlen_cnt[7]_i_3_n_0 ), .O(\memory_reg[7][0]_srl8_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \memory_reg[7][0]_srl8_i_4 (.I0(s_axi_awlen[7]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [7]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[7]), .O(\memory_reg[7][0]_srl8_i_4_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \memory_reg[7][0]_srl8_i_5 (.I0(s_axi_awlen[3]), .I1(s_axi_awready), .I2(\axlen_reg[7]_0 [3]), .I3(\axi_mc_cmd_translator_0/incr_axhandshake ), .I4(Q[3]), .O(\memory_reg[7][0]_srl8_i_5_n_0 )); endmodule module ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd (\int_addr_reg[3]_0 , \axlen_cnt_reg[3]_0 , areset_d1, axready_reg, axready_reg_0, CLK, \axlen_cnt_reg[3]_1 ); output [3:0]\int_addr_reg[3]_0 ; output [3:0]\axlen_cnt_reg[3]_0 ; input areset_d1; input [0:0]axready_reg; input [3:0]axready_reg_0; input CLK; input [3:0]\axlen_cnt_reg[3]_1 ; wire CLK; wire areset_d1; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [3:0]\axlen_cnt_reg[3]_1 ; wire [0:0]axready_reg; wire [3:0]axready_reg_0; wire [3:0]\int_addr_reg[3]_0 ; FDSE \axlen_cnt_reg[0] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [0]), .Q(\axlen_cnt_reg[3]_0 [0]), .S(areset_d1)); FDSE \axlen_cnt_reg[1] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [1]), .Q(\axlen_cnt_reg[3]_0 [1]), .S(areset_d1)); FDSE \axlen_cnt_reg[2] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [2]), .Q(\axlen_cnt_reg[3]_0 [2]), .S(areset_d1)); FDSE \axlen_cnt_reg[3] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [3]), .Q(\axlen_cnt_reg[3]_0 [3]), .S(areset_d1)); FDRE \int_addr_reg[0] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[0]), .Q(\int_addr_reg[3]_0 [0]), .R(areset_d1)); FDRE \int_addr_reg[1] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[1]), .Q(\int_addr_reg[3]_0 [1]), .R(areset_d1)); FDRE \int_addr_reg[2] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[2]), .Q(\int_addr_reg[3]_0 [2]), .R(areset_d1)); FDRE \int_addr_reg[3] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[3]), .Q(\int_addr_reg[3]_0 [3]), .R(areset_d1)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_axi_mc_wrap_cmd" *) module ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd__parameterized0 (\app_addr_r1_reg[6] , \axlen_cnt_reg[3]_0 , areset_d1, axready_reg, axready_reg_0, CLK, \axlen_cnt_reg[3]_1 ); output [3:0]\app_addr_r1_reg[6] ; output [3:0]\axlen_cnt_reg[3]_0 ; input areset_d1; input [0:0]axready_reg; input [3:0]axready_reg_0; input CLK; input [3:0]\axlen_cnt_reg[3]_1 ; wire CLK; wire [3:0]\app_addr_r1_reg[6] ; wire areset_d1; wire [3:0]\axlen_cnt_reg[3]_0 ; wire [3:0]\axlen_cnt_reg[3]_1 ; wire [0:0]axready_reg; wire [3:0]axready_reg_0; FDSE \axlen_cnt_reg[0] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [0]), .Q(\axlen_cnt_reg[3]_0 [0]), .S(areset_d1)); FDSE \axlen_cnt_reg[1] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [1]), .Q(\axlen_cnt_reg[3]_0 [1]), .S(areset_d1)); FDSE \axlen_cnt_reg[2] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [2]), .Q(\axlen_cnt_reg[3]_0 [2]), .S(areset_d1)); FDSE \axlen_cnt_reg[3] (.C(CLK), .CE(axready_reg), .D(\axlen_cnt_reg[3]_1 [3]), .Q(\axlen_cnt_reg[3]_0 [3]), .S(areset_d1)); FDRE \int_addr_reg[0] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[0]), .Q(\app_addr_r1_reg[6] [0]), .R(areset_d1)); FDRE \int_addr_reg[1] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[1]), .Q(\app_addr_r1_reg[6] [1]), .R(areset_d1)); FDRE \int_addr_reg[2] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[2]), .Q(\app_addr_r1_reg[6] [2]), .R(areset_d1)); FDRE \int_addr_reg[3] (.C(CLK), .CE(axready_reg), .D(axready_reg_0[3]), .Q(\app_addr_r1_reg[6] [3]), .R(areset_d1)); endmodule module ddr3_if_mig_7series_v4_0_bank_cntrl (E, req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, q_has_priority_r_reg, row_hit_r, bm_end_r1, \act_this_rank_r_reg[0] , \rp_timer.rp_timer_r_reg[1] , act_this_rank_r, req_bank_rdy_ns, demand_priority_r_reg, demanded_prior_r_reg, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, act_wait_r_lcl_reg, pre_bm_end_r, q_has_rd, q_has_priority, wait_for_maint_r, \starve_limit_cntr_r_reg[2] , tail_r, wait_for_maint_r_lcl_reg, \rp_timer.rp_timer_r_reg[1]_0 , ordered_r, D, accept_internal_r_reg, \q_entry_r_reg[0] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 , granted_col_ns, granted_col_r_reg, \grant_r_reg[1] , \ras_timer_r_reg[0] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , \ras_timer_r_reg[1] , \ras_timer_r_reg[2] , \ras_timer_r_reg[0]_0 , \q_entry_r_reg[1] , q_entry_ns, \q_entry_r_reg[1]_0 , \q_entry_r_reg[1]_1 , \q_entry_r_reg[0]_0 , p_9_in, head_r_lcl_reg, head_r_lcl_reg_0, head_r_lcl_reg_1, head_r_lcl_reg_2, \q_entry_r_reg[1]_2 , \grant_r_reg[2] , \ras_timer_r_reg[0]_1 , \ras_timer_r_reg[0]_2 , \ras_timer_r_reg[0]_3 , \pre_4_1_1T_arb.granted_pre_r_reg , auto_pre_r_lcl_reg, head_r_lcl_reg_3, \cmd_pipe_plus.mc_address_reg[14] , \rnk_config_strobe_r_reg[0] , demanded_prior_r_reg_0, \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_address_reg[24] , CLK, periodic_rd_insert, hi_priority, SR, ofs_rdy_r0, q_has_rd_r_reg, q_has_priority_r_reg_0, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_0, idle_r_lcl_reg, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_4, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg, \req_bank_r_lcl_reg[0] , idle_r_lcl_reg_0, Q, rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 , idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 , rd_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, \rtw_timer.rtw_cnt_r_reg[1] , col_wait_r_reg, override_demand_r_reg, \wtr_timer.wtr_cnt_r_reg[1] , rd_wr_r_lcl_reg_1, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[1]_1 , bm_end_r1_reg_0, bm_end_r1_reg_1, bm_end_r1_reg_2, \ras_timer_r_reg[2]_0 , \ras_timer_r_reg[2]_1 , \ras_timer_r_reg[2]_2 , req_wr_r_lcl_reg, rd_wr_r_lcl_reg_2, req_wr_r_lcl_reg_0, rnk_config_valid_r_lcl_reg, \grant_r_reg[2]_0 , \grant_r_reg[0] , bm_end_r1_reg_3, pre_passing_open_bank_r_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , pre_passing_open_bank_r_reg_0, \q_entry_r_reg[1]_3 , pre_bm_end_r_reg, pre_bm_end_r_reg_0, \q_entry_r_reg[1]_4 , periodic_rd_ack_r_lcl_reg, init_calib_complete_reg_rep__6, accept_r_reg, periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg_1, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , periodic_rd_ack_r_lcl_reg_1, periodic_rd_cntr_r_reg, periodic_rd_r, periodic_rd_ack_r_lcl_reg_2, use_addr, accept_internal_r_reg_0, req_wr_r_lcl_reg_1, rtp_timer_ns1, accept_r_reg_0, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__22, idle_r_lcl_reg_3, idle_r_lcl_reg_4, idle_r_lcl_reg_5, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , \app_addr_r1_reg[27] , demand_priority_r_reg_0, demanded_prior_r_reg_1, demanded_prior_r_reg_2, granted_col_r_reg_0, rb_hit_busy_r_reg, rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 , rb_hit_busy_r_reg_2, idle_r_lcl_reg_6, ordered_r_lcl_reg_0, ordered_r_lcl_reg_1); output [0:0]E; output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output q_has_priority_r_reg; output row_hit_r; output bm_end_r1; output \act_this_rank_r_reg[0] ; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]act_this_rank_r; output req_bank_rdy_ns; output demand_priority_r_reg; output demanded_prior_r_reg; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output act_wait_r_lcl_reg; output pre_bm_end_r; output q_has_rd; output q_has_priority; output wait_for_maint_r; output \starve_limit_cntr_r_reg[2] ; output tail_r; output wait_for_maint_r_lcl_reg; output \rp_timer.rp_timer_r_reg[1]_0 ; output [0:0]ordered_r; output [0:0]D; output accept_internal_r_reg; output \q_entry_r_reg[0] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; output granted_col_ns; output granted_col_r_reg; output \grant_r_reg[1] ; output \ras_timer_r_reg[0] ; output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; output \ras_timer_r_reg[1] ; output \ras_timer_r_reg[2] ; output \ras_timer_r_reg[0]_0 ; output \q_entry_r_reg[1] ; output [0:0]q_entry_ns; output \q_entry_r_reg[1]_0 ; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[0]_0 ; output p_9_in; output head_r_lcl_reg; output head_r_lcl_reg_0; output head_r_lcl_reg_1; output head_r_lcl_reg_2; output \q_entry_r_reg[1]_2 ; output \grant_r_reg[2] ; output \ras_timer_r_reg[0]_1 ; output \ras_timer_r_reg[0]_2 ; output \ras_timer_r_reg[0]_3 ; output \pre_4_1_1T_arb.granted_pre_r_reg ; output auto_pre_r_lcl_reg; output head_r_lcl_reg_3; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output \rnk_config_strobe_r_reg[0] ; output demanded_prior_r_reg_0; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input CLK; input periodic_rd_insert; input hi_priority; input [0:0]SR; input ofs_rdy_r0; input q_has_rd_r_reg; input q_has_priority_r_reg_0; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_0; input idle_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_4; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg; input \req_bank_r_lcl_reg[0] ; input idle_r_lcl_reg_0; input [0:0]Q; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_1; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ; input rd_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input \rtw_timer.rtw_cnt_r_reg[1] ; input col_wait_r_reg; input override_demand_r_reg; input \wtr_timer.wtr_cnt_r_reg[1] ; input rd_wr_r_lcl_reg_1; input \ras_timer_r_reg[1]_0 ; input \ras_timer_r_reg[1]_1 ; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input \ras_timer_r_reg[2]_0 ; input \ras_timer_r_reg[2]_1 ; input \ras_timer_r_reg[2]_2 ; input req_wr_r_lcl_reg; input rd_wr_r_lcl_reg_2; input req_wr_r_lcl_reg_0; input rnk_config_valid_r_lcl_reg; input [1:0]\grant_r_reg[2]_0 ; input [0:0]\grant_r_reg[0] ; input bm_end_r1_reg_3; input pre_passing_open_bank_r_reg; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; input pre_passing_open_bank_r_reg_0; input \q_entry_r_reg[1]_3 ; input pre_bm_end_r_reg; input pre_bm_end_r_reg_0; input \q_entry_r_reg[1]_4 ; input periodic_rd_ack_r_lcl_reg; input init_calib_complete_reg_rep__6; input accept_r_reg; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg_1; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input periodic_rd_ack_r_lcl_reg_1; input periodic_rd_cntr_r_reg; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg_2; input use_addr; input accept_internal_r_reg_0; input req_wr_r_lcl_reg_1; input rtp_timer_ns1; input accept_r_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\grant_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__22; input [0:0]idle_r_lcl_reg_3; input [0:0]idle_r_lcl_reg_4; input [0:0]idle_r_lcl_reg_5; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input [14:0]\app_addr_r1_reg[27] ; input demand_priority_r_reg_0; input demanded_prior_r_reg_1; input demanded_prior_r_reg_2; input granted_col_r_reg_0; input rb_hit_busy_r_reg; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; input rb_hit_busy_r_reg_2; input idle_r_lcl_reg_6; input ordered_r_lcl_reg_0; input ordered_r_lcl_reg_1; wire CLK; wire [0:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_internal_r_reg_0; wire accept_r_reg; wire accept_r_reg_0; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0] ; wire act_wait_ns; wire act_wait_r_lcl_reg; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire bank_compare0_n_12; wire bank_queue0_n_23; wire bank_queue0_n_27; wire bm_end_r1; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire demanded_prior_r_reg; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire demanded_prior_r_reg_2; wire [0:0]\grant_r_reg[0] ; wire [0:0]\grant_r_reg[0]_0 ; wire \grant_r_reg[1] ; wire \grant_r_reg[2] ; wire [1:0]\grant_r_reg[2]_0 ; wire granted_col_ns; wire granted_col_r_reg; wire granted_col_r_reg_0; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire head_r_lcl_reg_3; wire head_r_lcl_reg_4; wire hi_priority; wire [0:0]idle_ns; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire [0:0]idle_r_lcl_reg_3; wire [0:0]idle_r_lcl_reg_4; wire [0:0]idle_r_lcl_reg_5; wire idle_r_lcl_reg_6; wire init_calib_complete_reg_rep__6; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire \maintenance_request.maint_req_r_lcl_reg ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire ofs_rdy_r; wire ofs_rdy_r0; wire [0:0]ordered_r; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire override_demand_r_reg; wire p_130_out; wire p_145_out; wire p_9_in; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_ack_r_lcl_reg_2; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire pre_bm_end_ns; wire pre_bm_end_r; wire pre_bm_end_r_reg; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg; wire pre_passing_open_bank_r_reg_0; wire pre_wait_r; wire [0:0]q_entry_ns; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[1] ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire \q_entry_r_reg[1]_3 ; wire \q_entry_r_reg[1]_4 ; wire q_has_priority; wire q_has_priority_r_reg; wire q_has_priority_r_reg_0; wire q_has_rd; wire q_has_rd_r_reg; wire [2:0]ras_timer_passed_ns; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[0]_2 ; wire \ras_timer_r_reg[0]_3 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire \ras_timer_r_reg[2]_2 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire [0:0]rd_this_rank_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_ns; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire row_hit_r; wire \rp_timer.rp_timer_r_reg[1] ; wire \rp_timer.rp_timer_r_reg[1]_0 ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire start_wtp_timer0; wire \starve_limit_cntr_r_reg[2] ; wire tail_r; wire use_addr; wire wait_for_maint_r; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire [0:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; ddr3_if_mig_7series_v4_0_bank_compare_2 bank_compare0 (.CLK(CLK), .E(idle_ns), .Q(Q), .accept_r_reg(accept_r_reg_0), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .bm_end_r1_reg(bm_end_r1_reg), .\cmd_pipe_plus.mc_address_reg[14] (\cmd_pipe_plus.mc_address_reg[14] ), .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\col_mux.col_data_buf_addr_r_reg[4] (\col_mux.col_data_buf_addr_r_reg[4] ), .\grant_r_reg[0] (\grant_r_reg[2]_0 [0]), .\grant_r_reg[2] (\grant_r_reg[2] ), .head_r_lcl_reg(head_r_lcl_reg_0), .head_r_lcl_reg_0(head_r_lcl_reg_1), .hi_priority(hi_priority), .idle_r_lcl_reg(accept_internal_r_reg), .idle_r_lcl_reg_0(E), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .p_130_out(p_130_out), .p_145_out(p_145_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_2), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .pre_bm_end_r(pre_bm_end_r), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_wait_r(pre_wait_r), .q_has_priority_r_reg(q_has_priority_r_reg), .\ras_timer_r_reg[0] (\ras_timer_r_reg[0]_1 ), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_2 ), .ras_timer_zero_r_reg(bank_compare0_n_12), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_0), .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_1), .\rd_this_rank_r_reg[0] (\rd_this_rank_r_reg[0] ), .req_periodic_rd_r(req_periodic_rd_r), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1), .row_hit_r(row_hit_r), .start_wtp_timer0(start_wtp_timer0), .tail_r(tail_r), .wait_for_maint_r(wait_for_maint_r)); ddr3_if_mig_7series_v4_0_bank_queue bank_queue0 (.CLK(CLK), .D(D), .E(idle_ns), .Q(Q), .SR(SR), .accept_internal_r_reg(accept_internal_r_reg), .accept_internal_r_reg_0(accept_internal_r_reg_0), .accept_r_reg(accept_r_reg), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(\act_this_rank_r_reg[0] ), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .bm_end_r1_reg(\ras_timer_r_reg[1] ), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bm_end_r1_reg_3(\ras_timer_r_reg[2] ), .bm_end_r1_reg_4(bm_end_r1_reg_3), .col_wait_r_reg(col_wait_r_reg), .col_wait_r_reg_0(\starve_limit_cntr_r_reg[2] ), .demand_priority_r_reg(bank_queue0_n_27), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[0]_0 (\grant_r_reg[2]_0 [0]), .\grant_r_reg[1] (\grant_r_reg[1] ), .granted_col_ns(granted_col_ns), .granted_col_r_reg(granted_col_r_reg), .head_r_lcl_reg_0(head_r_lcl_reg), .head_r_lcl_reg_1(head_r_lcl_reg_2), .head_r_lcl_reg_2(head_r_lcl_reg_3), .head_r_lcl_reg_3(head_r_lcl_reg_4), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(idle_r_lcl_reg_0), .idle_r_lcl_reg_2(idle_r_lcl_reg_1), .idle_r_lcl_reg_3(idle_r_lcl_reg_2), .idle_r_lcl_reg_4(idle_r_lcl_reg_3), .idle_r_lcl_reg_5(idle_r_lcl_reg_4), .idle_r_lcl_reg_6(idle_r_lcl_reg_5), .idle_r_lcl_reg_7(idle_r_lcl_reg_6), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .ordered_r(ordered_r), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0), .ordered_r_lcl_reg_2(ordered_r_lcl_reg_1), .override_demand_r_reg(override_demand_r_reg), .p_145_out(p_145_out), .p_9_in(p_9_in), .pass_open_bank_ns(pass_open_bank_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r(pre_bm_end_r), .pre_bm_end_r_reg_0(pre_bm_end_r_reg), .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0), .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg), .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0), .q_entry_ns(q_entry_ns), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ), .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ), .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ), .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ), .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ), .\q_entry_r_reg[1]_3 (\q_entry_r_reg[1]_2 ), .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_3 ), .\q_entry_r_reg[1]_5 (\q_entry_r_reg[1]_4 ), .q_has_priority(q_has_priority), .q_has_priority_r_reg_0(q_has_priority_r_reg_0), .q_has_rd(q_has_rd), .q_has_rd_r_reg_0(q_has_rd_r_reg), .\ras_timer_r_reg[0] (bank_queue0_n_23), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ), .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_3 ), .\ras_timer_r_reg[1] (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ), .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ), .\ras_timer_r_reg[2] (ras_timer_passed_ns), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2]_0 ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2]_1 ), .\ras_timer_r_reg[2]_2 (\ras_timer_r_reg[2]_2 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ), .rb_hit_busy_r_reg(head_r_lcl_reg_0), .rb_hit_busy_r_reg_0(head_r_lcl_reg_1), .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_2), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .rd_wr_r_lcl_reg_1(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_1), .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_2), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .req_bank_rdy_ns(req_bank_rdy_ns), .\req_data_buf_addr_r_reg[4] (E), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1), .req_wr_r_lcl_reg_2(bm_end_r1_reg), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg), .\rp_timer.rp_timer_r_reg[1] (\rp_timer.rp_timer_r_reg[1]_0 ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .tail_r(tail_r), .use_addr(use_addr), .wait_for_maint_r(wait_for_maint_r), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_if_mig_7series_v4_0_bank_state bank_state0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .accept_r_reg(accept_r_reg_0), .act_this_rank_r(act_this_rank_r), .\act_this_rank_r_reg[0]_0 (\act_this_rank_r_reg[0] ), .act_wait_ns(act_wait_ns), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(\rp_timer.rp_timer_r_reg[1]_0 ), .bm_end_r1(bm_end_r1), .bm_end_r1_reg_0(bm_end_r1_reg_3), .demand_priority_r_reg_0(demand_priority_r_reg), .demand_priority_r_reg_1(demand_priority_r_reg_0), .demanded_prior_r_reg_0(demanded_prior_r_reg), .demanded_prior_r_reg_1(demanded_prior_r_reg_0), .demanded_prior_r_reg_2(demanded_prior_r_reg_1), .demanded_prior_r_reg_3(demanded_prior_r_reg_2), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ), .\grant_r_reg[2] (\grant_r_reg[2]_0 ), .granted_col_r_reg(granted_col_r_reg_0), .idle_r_lcl_reg(accept_internal_r_reg), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r0(ofs_rdy_r0), .p_130_out(p_130_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ), .pre_bm_end_ns(pre_bm_end_ns), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_wait_r(pre_wait_r), .q_has_rd(q_has_rd), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (bank_queue0_n_23), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(bank_compare0_n_12), .req_bank_rdy_ns(req_bank_rdy_ns), .req_priority_r_reg(bank_queue0_n_27), .req_wr_r_lcl_reg(bm_end_r1_reg), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .\rp_timer.rp_timer_r_reg[1]_0 (\rp_timer.rp_timer_r_reg[1] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1(rtp_timer_ns1), .start_wtp_timer0(start_wtp_timer0), .\starve_limit_cntr_r_reg[2]_0 (\starve_limit_cntr_r_reg[2] ), .tail_r(tail_r), .wr_this_rank_r(wr_this_rank_r)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_cntrl" *) module ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized0 (E, req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, rb_hit_busy_r, row_hit_r_0, bm_end_r1_0, row_cmd_wr, act_this_rank_r, req_bank_rdy_ns, demand_priority_r_reg, demanded_prior_r, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, act_wait_r_lcl_reg, bm_end_r1_reg_0, q_has_rd_3, q_has_priority_4, wait_for_maint_r_18, \starve_limit_cntr_r_reg[2] , tail_r_24, wait_for_maint_r_lcl_reg, \rp_timer.rp_timer_r_reg[1] , ordered_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] , rb_hit_busy_r_reg, \q_entry_r_reg[0] , D, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] , \grant_r_reg[1] , \ras_timer_r_reg[0] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] , \ras_timer_r_reg[1] , \ras_timer_r_reg[2] , req_bank_rdy_r_reg, \ras_timer_r_reg[0]_0 , pre_passing_open_bank_r_reg, pre_passing_open_bank_r_reg_0, \q_entry_r_reg[1] , \q_entry_r_reg[1]_0 , \q_entry_r_reg[0]_0 , head_r_lcl_reg, head_r_lcl_reg_0, \q_entry_r_reg[1]_1 , \ras_timer_r_reg[0]_1 , granted_pre_ns, \grant_r_reg[2] , auto_pre_r_lcl_reg, \grant_r_reg[2]_0 , \grant_r_reg[1]_0 , \grant_r_reg[1]_1 , \cmd_pipe_plus.mc_address_reg[14] , \rnk_config_strobe_r_reg[0] , \grant_r_reg[3] , \cmd_pipe_plus.mc_address_reg[40] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_address_reg[24] , CLK, periodic_rd_insert, hi_priority, SR, ofs_rdy_r0, q_has_rd_r_reg, q_has_priority_r_reg, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_0, idle_r_lcl_reg, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_1, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg, \req_bank_r_lcl_reg[2] , idle_r_lcl_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 , rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_1, Q, idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 , \rtw_timer.rtw_cnt_r_reg[1] , col_wait_r_reg, override_demand_r_reg, \wtr_timer.wtr_cnt_r_reg[1] , \ras_timer_r_reg[1]_0 , rd_wr_r_lcl_reg, \ras_timer_r_reg[1]_1 , bm_end_r1_reg_1, bm_end_r1_reg_2, bm_end_r1_reg_3, bm_end_r1_reg_4, \ras_timer_r_reg[2]_0 , \ras_timer_r_reg[2]_1 , req_wr_r_lcl_reg, req_wr_r_lcl_reg_0, rnk_config_valid_r_lcl_reg, \grant_r_reg[3]_0 , pass_open_bank_r_lcl_reg, req_wr_r_lcl_reg_1, accept_r_reg, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , periodic_rd_ack_r_lcl_reg, periodic_rd_cntr_r_reg, periodic_rd_r, periodic_rd_ack_r_lcl_reg_0, use_addr, accept_internal_r_reg, pre_bm_end_r_reg, idle_r_lcl_reg_3, idle_r_lcl_reg_4, idle_r_lcl_reg_5, periodic_rd_ack_r_lcl_reg_1, periodic_rd_ack_r_lcl_reg_2, \grant_r_reg[1]_2 , bm_end_r1_reg_5, rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, accept_r_reg_0, pre_passing_open_bank_r_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 , pre_passing_open_bank_r_reg_2, pre_bm_end_r_reg_0, pre_bm_end_r_reg_1, auto_pre_r_lcl_reg_1, \grant_r_reg[1]_3 , ras_timer_zero_r_reg, rd_wr_r_lcl_reg_0, req_wr_r, rstdiv0_sync_r1_reg_rep__22, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , \last_master_r_reg[0] , \app_addr_r1_reg[27] , demanded_prior_r_reg, demand_priority_r_reg_0, demanded_prior_r_reg_0, act_wait_r_lcl_reg_0, \req_row_r_lcl_reg[10] , granted_col_r_reg, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , pass_open_bank_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__21, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 , q_entry_ns, idle_r_lcl_reg_6, ordered_r_lcl_reg_0, ordered_r_lcl_reg_1); output [0:0]E; output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output [0:0]rb_hit_busy_r; output row_hit_r_0; output bm_end_r1_0; output [0:0]row_cmd_wr; output [0:0]act_this_rank_r; output req_bank_rdy_ns; output demand_priority_r_reg; output demanded_prior_r; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output act_wait_r_lcl_reg; output bm_end_r1_reg_0; output q_has_rd_3; output q_has_priority_4; output wait_for_maint_r_18; output \starve_limit_cntr_r_reg[2] ; output tail_r_24; output wait_for_maint_r_lcl_reg; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]ordered_r; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ; output rb_hit_busy_r_reg; output \q_entry_r_reg[0] ; output [0:0]D; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; output \grant_r_reg[1] ; output \ras_timer_r_reg[0] ; output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; output \ras_timer_r_reg[1] ; output \ras_timer_r_reg[2] ; output req_bank_rdy_r_reg; output \ras_timer_r_reg[0]_0 ; output pre_passing_open_bank_r_reg; output pre_passing_open_bank_r_reg_0; output \q_entry_r_reg[1] ; output \q_entry_r_reg[1]_0 ; output \q_entry_r_reg[0]_0 ; output head_r_lcl_reg; output head_r_lcl_reg_0; output \q_entry_r_reg[1]_1 ; output \ras_timer_r_reg[0]_1 ; output granted_pre_ns; output \grant_r_reg[2] ; output auto_pre_r_lcl_reg; output \grant_r_reg[2]_0 ; output \grant_r_reg[1]_0 ; output \grant_r_reg[1]_1 ; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output \rnk_config_strobe_r_reg[0] ; output \grant_r_reg[3] ; output \cmd_pipe_plus.mc_address_reg[40] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input CLK; input periodic_rd_insert; input hi_priority; input [0:0]SR; input ofs_rdy_r0; input q_has_rd_r_reg; input q_has_priority_r_reg; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_0; input idle_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_1; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg; input \req_bank_r_lcl_reg[2] ; input idle_r_lcl_reg_0; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_1; input [0:0]Q; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; input \rtw_timer.rtw_cnt_r_reg[1] ; input col_wait_r_reg; input override_demand_r_reg; input \wtr_timer.wtr_cnt_r_reg[1] ; input \ras_timer_r_reg[1]_0 ; input rd_wr_r_lcl_reg; input \ras_timer_r_reg[1]_1 ; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input bm_end_r1_reg_3; input bm_end_r1_reg_4; input \ras_timer_r_reg[2]_0 ; input \ras_timer_r_reg[2]_1 ; input req_wr_r_lcl_reg; input req_wr_r_lcl_reg_0; input rnk_config_valid_r_lcl_reg; input [2:0]\grant_r_reg[3]_0 ; input pass_open_bank_r_lcl_reg; input req_wr_r_lcl_reg_1; input accept_r_reg; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input periodic_rd_ack_r_lcl_reg; input periodic_rd_cntr_r_reg; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg_0; input use_addr; input accept_internal_r_reg; input pre_bm_end_r_reg; input [0:0]idle_r_lcl_reg_3; input [0:0]idle_r_lcl_reg_4; input [0:0]idle_r_lcl_reg_5; input periodic_rd_ack_r_lcl_reg_1; input periodic_rd_ack_r_lcl_reg_2; input [0:0]\grant_r_reg[1]_2 ; input bm_end_r1_reg_5; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input accept_r_reg_0; input pre_passing_open_bank_r_reg_1; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; input pre_passing_open_bank_r_reg_2; input pre_bm_end_r_reg_0; input pre_bm_end_r_reg_1; input auto_pre_r_lcl_reg_1; input [1:0]\grant_r_reg[1]_3 ; input ras_timer_zero_r_reg; input rd_wr_r_lcl_reg_0; input [0:0]req_wr_r; input rstdiv0_sync_r1_reg_rep__22; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input \last_master_r_reg[0] ; input [14:0]\app_addr_r1_reg[27] ; input demanded_prior_r_reg; input demand_priority_r_reg_0; input demanded_prior_r_reg_0; input [0:0]act_wait_r_lcl_reg_0; input [0:0]\req_row_r_lcl_reg[10] ; input granted_col_r_reg; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input pass_open_bank_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; input [0:0]q_entry_ns; input idle_r_lcl_reg_6; input ordered_r_lcl_reg_0; input ordered_r_lcl_reg_1; wire CLK; wire [0:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_r_reg; wire accept_r_reg_0; wire [0:0]act_this_rank_r; wire act_wait_ns; wire act_wait_r_lcl_reg; wire [0:0]act_wait_r_lcl_reg_0; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire bank_compare0_n_11; wire bank_queue0_n_19; wire bank_queue0_n_23; wire bm_end_r1_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire bm_end_r1_reg_5; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire \cmd_pipe_plus.mc_address_reg[40] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire demanded_prior_r; wire demanded_prior_r_reg; wire demanded_prior_r_reg_0; wire \grant_r_reg[1] ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[1]_1 ; wire [0:0]\grant_r_reg[1]_2 ; wire [1:0]\grant_r_reg[1]_3 ; wire \grant_r_reg[2] ; wire \grant_r_reg[2]_0 ; wire \grant_r_reg[3] ; wire [2:0]\grant_r_reg[3]_0 ; wire granted_col_r_reg; wire granted_pre_ns; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire hi_priority; wire [1:1]idle_ns; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire [0:0]idle_r_lcl_reg_3; wire [0:0]idle_r_lcl_reg_4; wire [0:0]idle_r_lcl_reg_5; wire idle_r_lcl_reg_6; wire \last_master_r_reg[0] ; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire \maintenance_request.maint_req_r_lcl_reg ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire ofs_rdy_r; wire ofs_rdy_r0; wire [1:0]order_q_r; wire [0:0]ordered_r; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire override_demand_r_reg; wire p_106_out; wire p_91_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_ack_r_lcl_reg_2; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire pre_bm_end_ns; wire pre_bm_end_r_reg; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r_reg; wire pre_passing_open_bank_r_reg_0; wire pre_passing_open_bank_r_reg_1; wire pre_passing_open_bank_r_reg_2; wire pre_wait_r; wire [0:0]q_entry_ns; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[1] ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire q_has_priority_4; wire q_has_priority_r_reg; wire q_has_rd_3; wire q_has_rd_r_reg; wire [2:0]ras_timer_passed_ns; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire ras_timer_zero_r; wire ras_timer_zero_r_reg; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; wire [0:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire [0:0]rd_this_rank_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire \req_bank_r_lcl_reg[2] ; wire req_bank_rdy_ns; wire req_bank_rdy_r_reg; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire [0:0]\req_row_r_lcl_reg[10] ; wire [0:0]req_wr_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire [0:0]row_cmd_wr; wire row_hit_r_0; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire start_wtp_timer0; wire \starve_limit_cntr_r_reg[2] ; wire tail_r_24; wire use_addr; wire wait_for_maint_r_18; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire [0:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; ddr3_if_mig_7series_v4_0_bank_compare_1 bank_compare0 (.CLK(CLK), .E(idle_ns), .accept_r_reg(accept_r_reg), .act_wait_r_lcl_reg(row_cmd_wr), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .bm_end_r1_reg(bm_end_r1_reg), .\cmd_pipe_plus.mc_address_reg[14] (\cmd_pipe_plus.mc_address_reg[14] ), .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ), .\cmd_pipe_plus.mc_address_reg[40] (\cmd_pipe_plus.mc_address_reg[40] ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\col_mux.col_data_buf_addr_r_reg[4] (\col_mux.col_data_buf_addr_r_reg[4] ), .col_wait_r_reg(col_wait_r_reg), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[1]_0 (\grant_r_reg[3]_0 [1:0]), .\grant_r_reg[1]_1 (\grant_r_reg[1]_3 ), .head_r_lcl_reg(head_r_lcl_reg), .hi_priority(hi_priority), .idle_r_lcl_reg(rb_hit_busy_r_reg), .idle_r_lcl_reg_0(E), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .order_q_r(order_q_r), .override_demand_r_reg(override_demand_r_reg), .p_106_out(p_106_out), .p_91_out(p_91_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .pre_bm_end_r_reg(pre_bm_end_r_reg), .pre_bm_end_r_reg_0(bm_end_r1_reg_0), .pre_wait_r(pre_wait_r), .ras_timer_zero_r_reg(bank_compare0_n_11), .rb_hit_busy_r(rb_hit_busy_r), .\rd_this_rank_r_reg[0] (\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .req_bank_rdy_r_reg(req_bank_rdy_r_reg), .req_periodic_rd_r(req_periodic_rd_r), .req_priority_r(req_priority_r), .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ), .req_wr_r(req_wr_r), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg), .row_hit_r_0(row_hit_r_0), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .start_wtp_timer0(start_wtp_timer0), .tail_r_24(tail_r_24), .wait_for_maint_r_18(wait_for_maint_r_18), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_if_mig_7series_v4_0_bank_queue__parameterized0 bank_queue0 (.CLK(CLK), .D(D), .E(idle_ns), .Q(Q), .SR(SR), .accept_internal_r_reg(accept_internal_r_reg), .accept_r_reg(accept_r_reg_0), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(row_cmd_wr), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .bm_end_r1_reg(bm_end_r1_reg_0), .bm_end_r1_reg_0(\ras_timer_r_reg[1] ), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bm_end_r1_reg_3(bm_end_r1_reg_3), .bm_end_r1_reg_4(bm_end_r1_reg_4), .bm_end_r1_reg_5(bm_end_r1_reg_5), .col_wait_r_reg(\starve_limit_cntr_r_reg[2] ), .demand_priority_r_reg(bank_queue0_n_23), .\grant_r_reg[1] (\grant_r_reg[1]_1 ), .\grant_r_reg[1]_0 (\grant_r_reg[3]_0 [1]), .\grant_r_reg[1]_1 (\grant_r_reg[1]_2 ), .head_r_lcl_reg_0(head_r_lcl_reg_0), .head_r_lcl_reg_1(head_r_lcl_reg_1), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(idle_r_lcl_reg_0), .idle_r_lcl_reg_2(idle_r_lcl_reg_1), .idle_r_lcl_reg_3(idle_r_lcl_reg_2), .idle_r_lcl_reg_4(idle_r_lcl_reg_3), .idle_r_lcl_reg_5(idle_r_lcl_reg_4), .idle_r_lcl_reg_6(idle_r_lcl_reg_5), .idle_r_lcl_reg_7(idle_r_lcl_reg_6), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .order_q_r(order_q_r), .ordered_r(ordered_r), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0), .ordered_r_lcl_reg_2(ordered_r_lcl_reg_1), .p_106_out(p_106_out), .pass_open_bank_ns(pass_open_bank_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_1), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_2), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r_reg_0(pre_bm_end_r_reg), .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0), .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg_1), .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_2), .q_entry_ns(q_entry_ns), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ), .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ), .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ), .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ), .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ), .q_has_priority_4(q_has_priority_4), .q_has_priority_r_reg_0(q_has_priority_r_reg), .q_has_rd_3(q_has_rd_3), .q_has_rd_r_reg_0(q_has_rd_r_reg), .\ras_timer_r_reg[0] (bank_queue0_n_19), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ), .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_1 ), .\ras_timer_r_reg[1] (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ), .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ), .\ras_timer_r_reg[2] (ras_timer_passed_ns), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2] ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2]_0 ), .\ras_timer_r_reg[2]_2 (\ras_timer_r_reg[2]_1 ), .ras_timer_zero_r(ras_timer_zero_r), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0), .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(\rd_this_rank_r_reg[0] ), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .req_bank_rdy_ns(req_bank_rdy_ns), .\req_data_buf_addr_r_reg[4] (E), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .req_wr_r_lcl_reg_0(bm_end_r1_reg), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1), .\rp_timer.rp_timer_r_reg[1] (\rp_timer.rp_timer_r_reg[1] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .tail_r_24(tail_r_24), .use_addr(use_addr), .wait_for_maint_r_18(wait_for_maint_r_18), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0)); ddr3_if_mig_7series_v4_0_bank_state__parameterized0 bank_state0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .accept_r_reg(accept_r_reg), .act_this_rank_r(act_this_rank_r), .\act_this_rank_r_reg[0]_0 (row_cmd_wr), .act_wait_ns(act_wait_ns), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_1(\rp_timer.rp_timer_r_reg[1] ), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg_0(bm_end_r1_reg_5), .demand_priority_r_reg_0(demand_priority_r_reg), .demand_priority_r_reg_1(demand_priority_r_reg_0), .demanded_prior_r_reg_0(demanded_prior_r), .demanded_prior_r_reg_1(demanded_prior_r_reg), .demanded_prior_r_reg_2(demanded_prior_r_reg_0), .\grant_r_reg[1] (\grant_r_reg[1]_0 ), .\grant_r_reg[1]_0 (\grant_r_reg[1]_3 [1]), .\grant_r_reg[1]_1 (\grant_r_reg[1]_2 ), .\grant_r_reg[2] (\grant_r_reg[2] ), .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ), .\grant_r_reg[3] (\grant_r_reg[3] ), .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 [2:1]), .granted_col_r_reg(granted_col_r_reg), .granted_pre_ns(granted_pre_ns), .idle_r_lcl_reg(rb_hit_busy_r_reg), .\last_master_r_reg[0] (\last_master_r_reg[0] ), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r0(ofs_rdy_r0), .p_91_out(p_91_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .pass_open_bank_r_lcl_reg_0(act_wait_r_lcl_reg), .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0), .pre_bm_end_ns(pre_bm_end_ns), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r_reg(pre_passing_open_bank_r_reg), .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg_0), .pre_wait_r(pre_wait_r), .q_has_rd_3(q_has_rd_3), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2] ), .ras_timer_zero_r(ras_timer_zero_r), .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (bank_queue0_n_19), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(bank_compare0_n_11), .req_bank_rdy_ns(req_bank_rdy_ns), .req_priority_r_reg(bank_queue0_n_23), .req_wr_r_lcl_reg(bm_end_r1_reg), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .start_wtp_timer0(start_wtp_timer0), .\starve_limit_cntr_r_reg[2]_0 (\starve_limit_cntr_r_reg[2] ), .tail_r_24(tail_r_24), .wr_this_rank_r(wr_this_rank_r)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_cntrl" *) module ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized1 (E, req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, q_has_priority_r_reg, row_hit_r_5, \ras_timer_r_reg[2] , \act_this_rank_r_reg[0] , \rp_timer.rp_timer_r_reg[1] , act_this_rank_r, req_bank_rdy_ns, demand_priority_r_reg, demanded_prior_r_reg, override_demand_r, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, act_wait_r_lcl_reg, pre_bm_end_r_9, q_has_rd_10, q_has_priority_11, wait_for_maint_r_19, \starve_limit_cntr_r_reg[2] , tail_r_26, wait_for_maint_r_lcl_reg, \rp_timer.rp_timer_r_reg[1]_0 , ordered_r, D, rb_hit_busy_r_reg, \q_entry_r_reg[1] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 , ofs_rdy_r0, ofs_rdy_r0_0, ofs_rdy_r0_1, \grant_r_reg[2] , \ras_timer_r_reg[0] , \ras_timer_r_reg[1] , \ras_timer_r_reg[2]_0 , \order_q_r_reg[0] , req_bank_rdy_r_reg, \order_q_r_reg[1] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] , \q_entry_r_reg[1]_0 , \q_entry_r_reg[1]_1 , \q_entry_r_reg[0] , head_r_lcl_reg, \q_entry_r_reg[1]_2 , \compute_tail.tail_r_lcl_reg , \ras_timer_r_reg[0]_0 , \grant_r_reg[1] , \grant_r_reg[3] , \ras_timer_r_reg[0]_1 , granted_row_ns, granted_row_r_reg, auto_pre_r_lcl_reg, \grant_r_reg[2]_0 , \cmd_pipe_plus.mc_address_reg[44] , \rnk_config_strobe_r_reg[0] , \cmd_pipe_plus.mc_address_reg[40] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_address_reg[24] , CLK, periodic_rd_insert, hi_priority, override_demand_ns, SR, q_has_rd_r_reg, q_has_priority_r_reg_0, rstdiv0_sync_r1_reg_rep__0, of_ctl_full_v, phy_mc_ctl_full, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_0, idle_r_lcl_reg, head_r_lcl_reg_0, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg, \req_bank_r_lcl_reg[2] , idle_r_lcl_reg_0, Q, rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 , idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 , \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , rd_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, rd_wr_r, \rtw_timer.rtw_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1] , override_demand_r_reg, col_wait_r_reg, bm_end_r1_reg_0, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[3]_0 , ordered_r_lcl_reg_0, rd_wr_r_lcl_reg_1, req_wr_r_lcl_reg, rnk_config_valid_r_lcl_reg, req_wr_r_lcl_reg_0, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[1]_1 , rd_wr_r_lcl_reg_2, bm_end_r1_reg_1, bm_end_r1_reg_2, bm_end_r1_reg_3, \ras_timer_r_reg[2]_1 , bm_end_r1_reg_4, \ras_timer_r_reg[2]_2 , \grant_r_reg[2]_1 , pre_passing_open_bank_r_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , pre_passing_open_bank_r_reg_0, idle_r_lcl_reg_3, rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, periodic_rd_ack_r_lcl_reg, accept_r_reg, periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg, pre_bm_end_r_reg_0, pre_bm_end_r_reg_1, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , periodic_rd_ack_r_lcl_reg_1, periodic_rd_cntr_r_reg, periodic_rd_r, periodic_rd_ack_r_lcl_reg_2, use_addr, accept_internal_r_reg, req_wr_r_lcl_reg_1, rtp_timer_ns1_7, rb_hit_busy_r_reg_2, \grant_r_reg[1]_0 , ras_timer_zero_r_reg, \grant_r_reg[3]_1 , maint_req_r, \maint_controller.maint_wip_r_lcl_reg , \grant_r_reg[3]_2 , rstdiv0_sync_r1_reg_rep__22, \app_addr_r1_reg[27] , demand_priority_r, demanded_prior_r_reg_0, demanded_prior_r, \req_row_r_lcl_reg[10] , act_wait_r_lcl_reg_0, granted_col_r_reg, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 , idle_r_lcl_reg_4, \q_entry_r_reg[1]_3 , idle_r_lcl_reg_5); output [0:0]E; output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output q_has_priority_r_reg; output row_hit_r_5; output \ras_timer_r_reg[2] ; output \act_this_rank_r_reg[0] ; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]act_this_rank_r; output req_bank_rdy_ns; output demand_priority_r_reg; output demanded_prior_r_reg; output override_demand_r; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output act_wait_r_lcl_reg; output pre_bm_end_r_9; output q_has_rd_10; output q_has_priority_11; output wait_for_maint_r_19; output \starve_limit_cntr_r_reg[2] ; output tail_r_26; output wait_for_maint_r_lcl_reg; output \rp_timer.rp_timer_r_reg[1]_0 ; output [0:0]ordered_r; output [0:0]D; output rb_hit_busy_r_reg; output \q_entry_r_reg[1] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; output ofs_rdy_r0; output ofs_rdy_r0_0; output ofs_rdy_r0_1; output \grant_r_reg[2] ; output \ras_timer_r_reg[0] ; output \ras_timer_r_reg[1] ; output \ras_timer_r_reg[2]_0 ; output \order_q_r_reg[0] ; output req_bank_rdy_r_reg; output \order_q_r_reg[1] ; output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; output \q_entry_r_reg[1]_0 ; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[0] ; output head_r_lcl_reg; output \q_entry_r_reg[1]_2 ; output \compute_tail.tail_r_lcl_reg ; output \ras_timer_r_reg[0]_0 ; output \grant_r_reg[1] ; output \grant_r_reg[3] ; output \ras_timer_r_reg[0]_1 ; output granted_row_ns; output granted_row_r_reg; output auto_pre_r_lcl_reg; output \grant_r_reg[2]_0 ; output [14:0]\cmd_pipe_plus.mc_address_reg[44] ; output \rnk_config_strobe_r_reg[0] ; output [0:0]\cmd_pipe_plus.mc_address_reg[40] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input CLK; input periodic_rd_insert; input hi_priority; input override_demand_ns; input [0:0]SR; input q_has_rd_r_reg; input q_has_priority_r_reg_0; input rstdiv0_sync_r1_reg_rep__0; input [0:0]of_ctl_full_v; input phy_mc_ctl_full; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_0; input idle_r_lcl_reg; input head_r_lcl_reg_0; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg; input \req_bank_r_lcl_reg[2] ; input idle_r_lcl_reg_0; input [0:0]Q; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_1; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input rd_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input [0:0]rd_wr_r; input \rtw_timer.rtw_cnt_r_reg[1] ; input \wtr_timer.wtr_cnt_r_reg[1] ; input override_demand_r_reg; input col_wait_r_reg; input bm_end_r1_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [2:0]\grant_r_reg[3]_0 ; input [2:0]ordered_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input req_wr_r_lcl_reg; input rnk_config_valid_r_lcl_reg; input req_wr_r_lcl_reg_0; input \ras_timer_r_reg[1]_0 ; input \ras_timer_r_reg[1]_1 ; input rd_wr_r_lcl_reg_2; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input bm_end_r1_reg_3; input \ras_timer_r_reg[2]_1 ; input bm_end_r1_reg_4; input \ras_timer_r_reg[2]_2 ; input [0:0]\grant_r_reg[2]_1 ; input pre_passing_open_bank_r_reg; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; input pre_passing_open_bank_r_reg_0; input idle_r_lcl_reg_3; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input periodic_rd_ack_r_lcl_reg; input accept_r_reg; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg; input pre_bm_end_r_reg_0; input pre_bm_end_r_reg_1; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input periodic_rd_ack_r_lcl_reg_1; input periodic_rd_cntr_r_reg; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg_2; input use_addr; input accept_internal_r_reg; input req_wr_r_lcl_reg_1; input rtp_timer_ns1_7; input rb_hit_busy_r_reg_2; input \grant_r_reg[1]_0 ; input ras_timer_zero_r_reg; input \grant_r_reg[3]_1 ; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input [1:0]\grant_r_reg[3]_2 ; input rstdiv0_sync_r1_reg_rep__22; input [14:0]\app_addr_r1_reg[27] ; input demand_priority_r; input demanded_prior_r_reg_0; input demanded_prior_r; input \req_row_r_lcl_reg[10] ; input act_wait_r_lcl_reg_0; input granted_col_r_reg; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; input idle_r_lcl_reg_4; input \q_entry_r_reg[1]_3 ; input idle_r_lcl_reg_5; wire CLK; wire [0:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_r_reg; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0] ; wire act_wait_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire bank_compare0_n_10; wire bank_compare0_n_8; wire bank_queue0_n_21; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [0:0]\cmd_pipe_plus.mc_address_reg[40] ; wire [14:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire \compute_tail.tail_r_lcl_reg ; wire demand_priority_r; wire demand_priority_r_reg; wire demanded_prior_r; wire demanded_prior_r_reg; wire demanded_prior_r_reg_0; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire \grant_r_reg[1] ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[2] ; wire \grant_r_reg[2]_0 ; wire [0:0]\grant_r_reg[2]_1 ; wire \grant_r_reg[3] ; wire [2:0]\grant_r_reg[3]_0 ; wire \grant_r_reg[3]_1 ; wire [1:0]\grant_r_reg[3]_2 ; wire granted_col_r_reg; wire granted_row_ns; wire granted_row_r_reg; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire hi_priority; wire [2:2]idle_ns; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire idle_r_lcl_reg_4; wire idle_r_lcl_reg_5; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire \maintenance_request.maint_req_r_lcl_reg ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r; wire ofs_rdy_r0; wire ofs_rdy_r0_0; wire ofs_rdy_r0_1; wire [1:0]order_q_r; wire \order_q_r_reg[0] ; wire \order_q_r_reg[1] ; wire [0:0]ordered_r; wire ordered_r_lcl_reg; wire [2:0]ordered_r_lcl_reg_0; wire override_demand_ns; wire override_demand_r; wire override_demand_r_reg; wire p_52_out; wire p_67_out; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_ack_r_lcl_reg_2; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire phy_mc_ctl_full; wire pre_bm_end_ns; wire pre_bm_end_r_9; wire pre_bm_end_r_reg; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg; wire pre_passing_open_bank_r_reg_0; wire pre_wait_r; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[1] ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire \q_entry_r_reg[1]_3 ; wire q_has_priority_11; wire q_has_priority_r_reg; wire q_has_priority_r_reg_0; wire q_has_rd_10; wire q_has_rd_r_reg; wire [2:0]ras_timer_passed_ns; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire \ras_timer_r_reg[2]_2 ; wire ras_timer_zero_r_reg; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire [0:0]rd_this_rank_r; wire \rd_this_rank_r_reg[0] ; wire [0:0]rd_wr_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire \req_bank_r_lcl_reg[2] ; wire req_bank_rdy_ns; wire req_bank_rdy_r_reg; wire [0:0]req_periodic_rd_r; wire \req_row_r_lcl_reg[10] ; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire row_hit_r_5; wire \rp_timer.rp_timer_r_reg[1] ; wire \rp_timer.rp_timer_r_reg[1]_0 ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1_7; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire start_wtp_timer0; wire \starve_limit_cntr_r_reg[2] ; wire tail_r_26; wire use_addr; wire wait_for_maint_r_19; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire [0:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; ddr3_if_mig_7series_v4_0_bank_compare_0 bank_compare0 (.CLK(CLK), .E(idle_ns), .Q(Q), .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0), .act_wait_r_lcl_reg_0(\act_this_rank_r_reg[0] ), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .bm_end_r1_reg(bm_end_r1_reg), .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ), .\cmd_pipe_plus.mc_address_reg[40] (\cmd_pipe_plus.mc_address_reg[40] ), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\col_mux.col_data_buf_addr_r_reg[4] (\col_mux.col_data_buf_addr_r_reg[4] ), .col_wait_r_reg(\starve_limit_cntr_r_reg[2] ), .demand_priority_r_reg(bank_compare0_n_8), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[3] (\grant_r_reg[3] ), .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 [2:1]), .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 ), .hi_priority(hi_priority), .idle_r_lcl_reg(rb_hit_busy_r_reg), .idle_r_lcl_reg_0(E), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .order_q_r(order_q_r), .\order_q_r_reg[0] (\order_q_r_reg[0] ), .\order_q_r_reg[1] (\order_q_r_reg[1] ), .ordered_r(ordered_r), .ordered_r_lcl_reg(ordered_r_lcl_reg_0), .p_52_out(p_52_out), .p_67_out(p_67_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_2), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .pre_bm_end_r_9(pre_bm_end_r_9), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_wait_r(pre_wait_r), .q_has_priority_11(q_has_priority_11), .q_has_priority_r_reg(q_has_priority_r_reg), .\ras_timer_r_reg[0] (\ras_timer_r_reg[0]_0 ), .ras_timer_zero_r_reg(bank_compare0_n_10), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_2), .\rd_this_rank_r_reg[0] (\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1), .req_bank_rdy_ns(req_bank_rdy_ns), .req_bank_rdy_r_reg(req_bank_rdy_r_reg), .req_periodic_rd_r(req_periodic_rd_r), .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1), .row_hit_r_5(row_hit_r_5), .start_wtp_timer0(start_wtp_timer0), .tail_r_26(tail_r_26), .wait_for_maint_r_19(wait_for_maint_r_19)); ddr3_if_mig_7series_v4_0_bank_queue__parameterized1 bank_queue0 (.CLK(CLK), .D(D), .E(idle_ns), .Q(Q), .SR(SR), .accept_internal_r_reg(accept_internal_r_reg), .accept_r_reg(accept_r_reg), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(\act_this_rank_r_reg[0] ), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .bm_end_r1_reg(\ras_timer_r_reg[1] ), .bm_end_r1_reg_0(bm_end_r1_reg_1), .bm_end_r1_reg_1(bm_end_r1_reg_2), .bm_end_r1_reg_2(bm_end_r1_reg_3), .bm_end_r1_reg_3(bm_end_r1_reg_4), .bm_end_r1_reg_4(bm_end_r1_reg_0), .col_wait_r_reg(col_wait_r_reg), .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ), .\grant_r_reg[1] (\grant_r_reg[1]_0 ), .\grant_r_reg[2] (\grant_r_reg[2] ), .\grant_r_reg[2]_0 (\grant_r_reg[2]_1 ), .\grant_r_reg[2]_1 (\grant_r_reg[3]_0 [1]), .\grant_r_reg[3] (\grant_r_reg[3]_1 ), .granted_row_ns(granted_row_ns), .granted_row_r_reg(granted_row_r_reg), .head_r_lcl_reg_0(head_r_lcl_reg), .head_r_lcl_reg_1(head_r_lcl_reg_0), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(idle_r_lcl_reg_0), .idle_r_lcl_reg_2(idle_r_lcl_reg_1), .idle_r_lcl_reg_3(idle_r_lcl_reg_2), .idle_r_lcl_reg_4(idle_r_lcl_reg_3), .idle_r_lcl_reg_5(idle_r_lcl_reg_4), .idle_r_lcl_reg_6(idle_r_lcl_reg_5), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .order_q_r(order_q_r), .ordered_r(ordered_r), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(\order_q_r_reg[1] ), .ordered_r_lcl_reg_2(\order_q_r_reg[0] ), .override_demand_r_reg(override_demand_r_reg), .p_67_out(p_67_out), .pass_open_bank_ns(pass_open_bank_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r_9(pre_bm_end_r_9), .pre_bm_end_r_reg_0(pre_bm_end_r_reg), .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0), .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg), .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ), .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ), .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ), .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ), .\q_entry_r_reg[1]_3 (\q_entry_r_reg[1]_2 ), .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_3 ), .q_has_priority_11(q_has_priority_11), .q_has_priority_r_reg_0(q_has_priority_r_reg_0), .q_has_rd_10(q_has_rd_10), .q_has_rd_r_reg_0(q_has_rd_r_reg), .\ras_timer_r_reg[0] (bank_queue0_n_21), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_1 ), .\ras_timer_r_reg[1] (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ), .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ), .\ras_timer_r_reg[2] (ras_timer_passed_ns), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2]_0 ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2]_1 ), .\ras_timer_r_reg[2]_2 (\ras_timer_r_reg[2]_2 ), .ras_timer_zero_r_reg(ras_timer_zero_r_reg), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0), .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_1), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_2), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_data_buf_addr_r_reg[4] (E), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1), .req_wr_r_lcl_reg_1(bm_end_r1_reg), .req_wr_r_lcl_reg_2(req_bank_rdy_r_reg), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg), .\rp_timer.rp_timer_r_reg[1] (\rp_timer.rp_timer_r_reg[1]_0 ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .tail_r_26(tail_r_26), .use_addr(use_addr), .wait_for_maint_r_19(wait_for_maint_r_19), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_if_mig_7series_v4_0_bank_state__parameterized1 bank_state0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .act_this_rank_r(act_this_rank_r), .\act_this_rank_r_reg[0]_0 (\act_this_rank_r_reg[0] ), .act_wait_ns(act_wait_ns), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(\rp_timer.rp_timer_r_reg[1]_0 ), .bm_end_r1_reg_0(bm_end_r1_reg_0), .demand_priority_r(demand_priority_r), .demand_priority_r_reg_0(demand_priority_r_reg), .demanded_prior_r(demanded_prior_r), .demanded_prior_r_reg_0(demanded_prior_r_reg), .demanded_prior_r_reg_1(demanded_prior_r_reg_0), .\entry_cnt_reg[2] (\entry_cnt_reg[2] ), .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2]_0 ), .\grant_r_reg[2] (\grant_r_reg[2]_0 ), .\grant_r_reg[2]_0 (\grant_r_reg[3]_0 [1:0]), .\grant_r_reg[2]_1 (\grant_r_reg[2]_1 ), .\grant_r_reg[2]_2 (\grant_r_reg[3]_2 [0]), .granted_col_r_reg(granted_col_r_reg), .idle_r_lcl_reg(rb_hit_busy_r_reg), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r0(ofs_rdy_r0), .ofs_rdy_r0_0(ofs_rdy_r0_0), .ofs_rdy_r0_1(ofs_rdy_r0_1), .override_demand_ns(override_demand_ns), .override_demand_r(override_demand_r), .p_52_out(p_52_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .phy_mc_ctl_full(phy_mc_ctl_full), .pre_bm_end_ns(pre_bm_end_ns), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_wait_r(pre_wait_r), .q_has_rd_10(q_has_rd_10), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2] ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (bank_queue0_n_21), .rb_hit_busy_r_reg(rb_hit_busy_r_reg_2), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r(rd_wr_r), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0), .rd_wr_r_lcl_reg_2(bank_compare0_n_10), .req_bank_rdy_ns(req_bank_rdy_ns), .req_priority_r_reg(bank_compare0_n_8), .req_wr_r_lcl_reg(bm_end_r1_reg), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .\rp_timer.rp_timer_r_reg[1]_0 (\rp_timer.rp_timer_r_reg[1] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1_7(rtp_timer_ns1_7), .start_wtp_timer0(start_wtp_timer0), .\starve_limit_cntr_r_reg[2]_0 (\starve_limit_cntr_r_reg[2] ), .tail_r_26(tail_r_26), .wr_this_rank_r(wr_this_rank_r)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_cntrl" *) module ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized2 (E, req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, q_has_priority_r_reg, row_hit_r_12, bm_end_r1_4, \act_this_rank_r_reg[0] , act_this_rank_r, req_bank_rdy_r, req_bank_rdy_ns, demand_priority_r_reg, demanded_prior_r_reg, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, act_wait_r_lcl_reg, pre_bm_end_r_15, q_has_rd_16, q_has_priority_17, wait_for_maint_r_20, \starve_limit_cntr_r_reg[2] , tail_r_28, wait_for_maint_r_lcl_reg, \rp_timer.rp_timer_r_reg[1] , ordered_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , rb_hit_busy_r_reg, \q_entry_r_reg[1] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 , granted_col_r_reg, \grant_r_reg[3] , \ras_timer_r_reg[0] , Q, \ras_timer_r_reg[1] , \ras_timer_r_reg[2] , \grant_r_reg[3]_0 , \q_entry_r_reg[1]_0 , \q_entry_r_reg[0] , head_r_lcl_reg, \q_entry_r_reg[1]_1 , \ras_timer_r_reg[0]_0 , \grant_r_reg[1] , \ras_timer_r_reg[0]_1 , auto_pre_r_lcl_reg, \pre_4_1_1T_arb.granted_pre_r_reg , \cmd_pipe_plus.mc_address_reg[10] , \cmd_pipe_plus.mc_address_reg[44] , \grant_r_reg[0] , \grant_r_reg[2] , \grant_r_reg[3]_1 , demanded_prior_r_reg_0, \rnk_config_strobe_r_reg[0] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_address_reg[24] , CLK, periodic_rd_insert, hi_priority, SR, ofs_rdy_r0, q_has_rd_r_reg, q_has_priority_r_reg_0, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_0, idle_r_lcl_reg, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_0, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg, \req_bank_r_lcl_reg[0] , idle_r_lcl_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 , rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 , idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 , rd_wr_r_lcl_reg, \rtw_timer.rtw_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1] , col_wait_r_reg, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[1]_1 , \ras_timer_r_reg[1]_2 , bm_end_r1_reg_0, bm_end_r1_reg_1, bm_end_r1_reg_2, \ras_timer_r_reg[2]_0 , \ras_timer_r_reg[2]_1 , bm_end_r1_reg_3, req_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, \grant_r_reg[3]_2 , rd_wr_r, req_wr_r, bm_end_r1_reg_4, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[3]_3 , pre_passing_open_bank_r_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] , pre_passing_open_bank_r_reg_0, idle_r_lcl_reg_3, periodic_rd_ack_r_lcl_reg, idle_r_lcl_reg_4, rb_hit_busy_r, accept_r_reg, rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg, pre_bm_end_r_reg_0, pre_bm_end_r_reg_1, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , periodic_rd_ack_r_lcl_reg_1, periodic_rd_cntr_r_reg, periodic_rd_r, periodic_rd_ack_r_lcl_reg_2, use_addr, accept_internal_r_reg, req_wr_r_lcl_reg_0, rtp_timer_ns1_6, rb_hit_busy_r_reg_2, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , \grant_r_reg[3]_4 , auto_pre_r_lcl_reg_1, demanded_prior_r_reg_1, \grant_r_reg[1]_0 , override_demand_r, rnk_config_valid_r_lcl_reg, \req_row_r_lcl_reg[10] , row_cmd_wr, \grant_r_reg[3]_5 , \last_master_r_reg[2] , rstdiv0_sync_r1_reg_rep__22, \app_addr_r1_reg[27] , demand_priority_r_reg_0, demanded_prior_r, req_bank_rdy_r_reg, granted_col_r_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , D, idle_r_lcl_reg_5, pre_bm_end_r_reg_2, ordered_r_lcl_reg_0, idle_r_lcl_reg_6, ordered_r_lcl_reg_1); output [0:0]E; output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output q_has_priority_r_reg; output row_hit_r_12; output bm_end_r1_4; output \act_this_rank_r_reg[0] ; output [0:0]act_this_rank_r; output req_bank_rdy_r; output req_bank_rdy_ns; output demand_priority_r_reg; output demanded_prior_r_reg; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output act_wait_r_lcl_reg; output pre_bm_end_r_15; output q_has_rd_16; output q_has_priority_17; output wait_for_maint_r_20; output \starve_limit_cntr_r_reg[2] ; output tail_r_28; output wait_for_maint_r_lcl_reg; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]ordered_r; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; output rb_hit_busy_r_reg; output \q_entry_r_reg[1] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ; output granted_col_r_reg; output \grant_r_reg[3] ; output \ras_timer_r_reg[0] ; output [2:0]Q; output \ras_timer_r_reg[1] ; output \ras_timer_r_reg[2] ; output \grant_r_reg[3]_0 ; output \q_entry_r_reg[1]_0 ; output \q_entry_r_reg[0] ; output head_r_lcl_reg; output \q_entry_r_reg[1]_1 ; output \ras_timer_r_reg[0]_0 ; output \grant_r_reg[1] ; output \ras_timer_r_reg[0]_1 ; output auto_pre_r_lcl_reg; output \pre_4_1_1T_arb.granted_pre_r_reg ; output \cmd_pipe_plus.mc_address_reg[10] ; output [14:0]\cmd_pipe_plus.mc_address_reg[44] ; output \grant_r_reg[0] ; output \grant_r_reg[2] ; output \grant_r_reg[3]_1 ; output demanded_prior_r_reg_0; output \rnk_config_strobe_r_reg[0] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input CLK; input periodic_rd_insert; input hi_priority; input [0:0]SR; input ofs_rdy_r0; input q_has_rd_r_reg; input q_has_priority_r_reg_0; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_0; input idle_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_0; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg; input \req_bank_r_lcl_reg[0] ; input idle_r_lcl_reg_0; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_1; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ; input rd_wr_r_lcl_reg; input \rtw_timer.rtw_cnt_r_reg[1] ; input \wtr_timer.wtr_cnt_r_reg[1] ; input col_wait_r_reg; input \ras_timer_r_reg[1]_0 ; input \ras_timer_r_reg[1]_1 ; input \ras_timer_r_reg[1]_2 ; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input \ras_timer_r_reg[2]_0 ; input \ras_timer_r_reg[2]_1 ; input bm_end_r1_reg_3; input req_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input [2:0]\grant_r_reg[3]_2 ; input [0:0]rd_wr_r; input [0:0]req_wr_r; input bm_end_r1_reg_4; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\grant_r_reg[3]_3 ; input pre_passing_open_bank_r_reg; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; input pre_passing_open_bank_r_reg_0; input idle_r_lcl_reg_3; input periodic_rd_ack_r_lcl_reg; input idle_r_lcl_reg_4; input [2:0]rb_hit_busy_r; input accept_r_reg; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg; input pre_bm_end_r_reg_0; input pre_bm_end_r_reg_1; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input periodic_rd_ack_r_lcl_reg_1; input periodic_rd_cntr_r_reg; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg_2; input use_addr; input accept_internal_r_reg; input req_wr_r_lcl_reg_0; input rtp_timer_ns1_6; input rb_hit_busy_r_reg_2; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input [0:0]\grant_r_reg[3]_4 ; input auto_pre_r_lcl_reg_1; input demanded_prior_r_reg_1; input \grant_r_reg[1]_0 ; input override_demand_r; input rnk_config_valid_r_lcl_reg; input [0:0]\req_row_r_lcl_reg[10] ; input [0:0]row_cmd_wr; input \grant_r_reg[3]_5 ; input \last_master_r_reg[2] ; input rstdiv0_sync_r1_reg_rep__22; input [14:0]\app_addr_r1_reg[27] ; input demand_priority_r_reg_0; input demanded_prior_r; input req_bank_rdy_r_reg; input granted_col_r_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input [2:0]D; input idle_r_lcl_reg_5; input pre_bm_end_r_reg_2; input ordered_r_lcl_reg_0; input idle_r_lcl_reg_6; input ordered_r_lcl_reg_1; wire CLK; wire [2:0]D; wire [0:0]E; wire [2:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_r_reg; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0] ; wire act_wait_ns; wire act_wait_r_lcl_reg; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire bank_compare0_n_9; wire bank_queue0_n_20; wire bank_queue0_n_24; wire bank_state0_n_19; wire bm_end_r1_4; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire \cmd_pipe_plus.mc_address_reg[10] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [14:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire demand_priority_r_reg; wire demand_priority_r_reg_0; wire demanded_prior_r; wire demanded_prior_r_reg; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire \grant_r_reg[0] ; wire \grant_r_reg[1] ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[2] ; wire \grant_r_reg[3] ; wire \grant_r_reg[3]_0 ; wire \grant_r_reg[3]_1 ; wire [2:0]\grant_r_reg[3]_2 ; wire [0:0]\grant_r_reg[3]_3 ; wire [0:0]\grant_r_reg[3]_4 ; wire \grant_r_reg[3]_5 ; wire granted_col_r_reg; wire granted_col_r_reg_0; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire hi_priority; wire [3:3]idle_ns; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire idle_r_lcl_reg_4; wire idle_r_lcl_reg_5; wire idle_r_lcl_reg_6; wire \last_master_r_reg[2] ; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire \maintenance_request.maint_req_r_lcl_reg ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire ofs_rdy_r; wire ofs_rdy_r0; wire [1:0]order_q_r; wire [0:0]ordered_r; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire override_demand_r; wire p_13_out; wire p_28_out; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire periodic_rd_ack_r_lcl_reg_2; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire pre_bm_end_ns; wire pre_bm_end_r_15; wire pre_bm_end_r_reg; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_bm_end_r_reg_2; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg; wire pre_passing_open_bank_r_reg_0; wire pre_wait_r; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[1] ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire q_has_priority_17; wire q_has_priority_r_reg; wire q_has_priority_r_reg_0; wire q_has_rd_16; wire q_has_rd_r_reg; wire [2:0]ras_timer_passed_ns; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire \ras_timer_r_reg[1]_2 ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire ras_timer_zero_r; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; wire [2:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire [0:0]rd_this_rank_r; wire \rd_this_rank_r_reg[0] ; wire [0:0]rd_wr_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_ns; wire req_bank_rdy_r; wire req_bank_rdy_r_reg; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire [0:0]\req_row_r_lcl_reg[10] ; wire [0:0]req_wr_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire [0:0]row_cmd_wr; wire row_hit_r_12; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1_6; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire start_wtp_timer0; wire \starve_limit_cntr_r_reg[2] ; wire tail_r_28; wire use_addr; wire wait_for_maint_r_20; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire [0:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[1] ; ddr3_if_mig_7series_v4_0_bank_compare bank_compare0 (.CLK(CLK), .E(idle_ns), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .bm_end_r1_reg(bm_end_r1_reg), .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ), .\cmd_pipe_plus.mc_address_reg[44] (\cmd_pipe_plus.mc_address_reg[44] ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\col_mux.col_data_buf_addr_r_reg[4] (\col_mux.col_data_buf_addr_r_reg[4] ), .col_wait_r_reg(col_wait_r_reg), .demand_priority_r_reg(bank_state0_n_19), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[3] (\grant_r_reg[3] ), .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 ), .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 [2:1]), .granted_col_r_reg(granted_col_r_reg), .hi_priority(hi_priority), .idle_r_lcl_reg(rb_hit_busy_r_reg), .idle_r_lcl_reg_0(E), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .maint_req_r(maint_req_r), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .order_q_r(order_q_r), .p_13_out(p_13_out), .p_28_out(p_28_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_2), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .pre_bm_end_r_15(pre_bm_end_r_15), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_wait_r(pre_wait_r), .q_has_priority_r_reg(q_has_priority_r_reg), .\ras_timer_r_reg[0] (\ras_timer_r_reg[0]_0 ), .ras_timer_zero_r_reg(bank_compare0_n_9), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_2), .\rd_this_rank_r_reg[0] (\rd_this_rank_r_reg[0] ), .rd_wr_r(rd_wr_r), .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0), .req_periodic_rd_r(req_periodic_rd_r), .req_priority_r(req_priority_r), .req_wr_r(req_wr_r), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0), .row_hit_r_12(row_hit_r_12), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .start_wtp_timer0(start_wtp_timer0), .tail_r_28(tail_r_28), .wait_for_maint_r_20(wait_for_maint_r_20), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] )); ddr3_if_mig_7series_v4_0_bank_queue__parameterized2 bank_queue0 (.CLK(CLK), .D(ras_timer_passed_ns), .E(idle_ns), .Q(Q), .SR(SR), .accept_internal_r_reg(accept_internal_r_reg), .accept_r_reg(accept_r_reg), .act_wait_ns(act_wait_ns), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(\act_this_rank_r_reg[0] ), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0), .bm_end_r1_reg(\ras_timer_r_reg[1] ), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bm_end_r1_reg_3(bm_end_r1_reg_3), .bm_end_r1_reg_4(bm_end_r1_reg_4), .col_wait_r_reg(\starve_limit_cntr_r_reg[2] ), .demand_priority_r_reg(bank_queue0_n_24), .\grant_r_reg[3] (\grant_r_reg[3]_1 ), .\grant_r_reg[3]_0 (\grant_r_reg[3]_3 ), .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 [2]), .head_r_lcl_reg_0(head_r_lcl_reg), .head_r_lcl_reg_1(head_r_lcl_reg_0), .idle_r_lcl_reg_0(idle_r_lcl_reg), .idle_r_lcl_reg_1(idle_r_lcl_reg_0), .idle_r_lcl_reg_2(idle_r_lcl_reg_1), .idle_r_lcl_reg_3(idle_r_lcl_reg_2), .idle_r_lcl_reg_4(idle_r_lcl_reg_3), .idle_r_lcl_reg_5(idle_r_lcl_reg_4), .idle_r_lcl_reg_6(idle_r_lcl_reg_5), .idle_r_lcl_reg_7(idle_r_lcl_reg_6), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .order_q_r(order_q_r), .ordered_r(ordered_r), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0), .ordered_r_lcl_reg_2(ordered_r_lcl_reg_1), .p_28_out(p_28_out), .pass_open_bank_ns(pass_open_bank_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1), .pre_bm_end_ns(pre_bm_end_ns), .pre_bm_end_r_15(pre_bm_end_r_15), .pre_bm_end_r_reg_0(pre_bm_end_r_reg), .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0), .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1), .pre_bm_end_r_reg_3(pre_bm_end_r_reg_2), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_passing_open_bank_r(pre_passing_open_bank_r), .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg), .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0), .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ), .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ), .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ), .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ), .q_has_priority_17(q_has_priority_17), .q_has_priority_r_reg_0(q_has_priority_r_reg_0), .q_has_rd_16(q_has_rd_16), .q_has_rd_r_reg_0(q_has_rd_r_reg), .\ras_timer_r_reg[0] (bank_queue0_n_20), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_1 ), .\ras_timer_r_reg[1] (\ras_timer_r_reg[1]_0 ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_1 ), .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_2 ), .\ras_timer_r_reg[2] (\ras_timer_r_reg[2] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2]_0 ), .\ras_timer_r_reg[2]_1 (\ras_timer_r_reg[2]_1 ), .ras_timer_zero_r(ras_timer_zero_r), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (D), .rb_hit_busy_r(rb_hit_busy_r), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_0(q_has_priority_r_reg), .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_0), .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_1), .rd_wr_r_lcl_reg(\ras_timer_r_reg[0] ), .rd_wr_r_lcl_reg_0(\rd_this_rank_r_reg[0] ), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .req_bank_rdy_ns(req_bank_rdy_ns), .\req_data_buf_addr_r_reg[4] (E), .req_priority_r(req_priority_r), .req_wr_r_lcl_reg(req_wr_r_lcl_reg), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0), .req_wr_r_lcl_reg_1(bm_end_r1_reg), .\rp_timer.rp_timer_r_reg[1] (\rp_timer.rp_timer_r_reg[1] ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .tail_r_28(tail_r_28), .use_addr(use_addr), .wait_for_maint_r_20(wait_for_maint_r_20), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0)); ddr3_if_mig_7series_v4_0_bank_state__parameterized2 bank_state0 (.CLK(CLK), .D(ras_timer_passed_ns), .SR(SR), .act_this_rank_r(act_this_rank_r), .\act_this_rank_r_reg[0]_0 (\act_this_rank_r_reg[0] ), .act_wait_ns(act_wait_ns), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(\rp_timer.rp_timer_r_reg[1] ), .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1), .bm_end_r1_4(bm_end_r1_4), .bm_end_r1_reg_0(bm_end_r1_reg_4), .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ), .demand_priority_r_reg_0(demand_priority_r_reg), .demand_priority_r_reg_1(demand_priority_r_reg_0), .demanded_prior_r(demanded_prior_r), .demanded_prior_r_reg_0(demanded_prior_r_reg), .demanded_prior_r_reg_1(demanded_prior_r_reg_0), .demanded_prior_r_reg_2(demanded_prior_r_reg_1), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[1] (\grant_r_reg[1]_0 ), .\grant_r_reg[2] (\grant_r_reg[2] ), .\grant_r_reg[3] (bank_state0_n_19), .\grant_r_reg[3]_0 ({\grant_r_reg[3]_2 [2],\grant_r_reg[3]_2 [0]}), .\grant_r_reg[3]_1 (\grant_r_reg[3]_4 ), .\grant_r_reg[3]_2 (\grant_r_reg[3]_3 ), .\grant_r_reg[3]_3 (\grant_r_reg[3]_5 ), .granted_col_r_reg(granted_col_r_reg_0), .idle_r_lcl_reg(rb_hit_busy_r_reg), .\last_master_r_reg[2] (\last_master_r_reg[2] ), .ofs_rdy_r(ofs_rdy_r), .ofs_rdy_r0(ofs_rdy_r0), .override_demand_r(override_demand_r), .p_13_out(p_13_out), .pass_open_bank_ns(pass_open_bank_ns), .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg), .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ), .pre_bm_end_ns(pre_bm_end_ns), .pre_passing_open_bank_ns(pre_passing_open_bank_ns), .pre_wait_r(pre_wait_r), .q_has_rd_16(q_has_rd_16), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ), .\ras_timer_r_reg[2]_0 (\ras_timer_r_reg[2] ), .ras_timer_zero_r(ras_timer_zero_r), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (bank_queue0_n_20), .rb_hit_busy_r_reg(rb_hit_busy_r_reg_2), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(\rd_this_rank_r_reg[0] ), .rd_wr_r_lcl_reg_0(bank_compare0_n_9), .req_bank_rdy_ns(req_bank_rdy_ns), .req_bank_rdy_r(req_bank_rdy_r), .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg), .req_priority_r_reg(bank_queue0_n_24), .\req_row_r_lcl_reg[10] (\cmd_pipe_plus.mc_address_reg[44] [10]), .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ), .req_wr_r_lcl_reg(bm_end_r1_reg), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1_6(rtp_timer_ns1_6), .start_wtp_timer0(start_wtp_timer0), .\starve_limit_cntr_r_reg[2]_0 (\starve_limit_cntr_r_reg[2] ), .tail_r_28(tail_r_28), .wr_this_rank_r(wr_this_rank_r)); endmodule module ddr3_if_mig_7series_v4_0_bank_common (wait_for_maint_r_lcl_reg, was_wr_reg_0, \q_entry_r_reg[1] , accept_ns, was_wr, insert_maint_r1_lcl_reg, \maint_controller.maint_wip_r_lcl_reg_0 , req_periodic_rd_r_lcl_reg, clear_periodic_rd_request, \maint_controller.maint_rdy_r1_reg_0 , head_r_lcl_reg, \q_entry_r_reg[0] , head_r_lcl_reg_0, ordered_r_lcl_reg, head_r_lcl_reg_1, ordered_r_lcl_reg_0, head_r_lcl_reg_2, ordered_r_lcl_reg_1, periodic_rd_insert, \q_entry_r_reg[0]_0 , \q_entry_r_reg[1]_0 , pass_open_bank_r_lcl_reg, pass_open_bank_r_lcl_reg_0, Q, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 , \maint_controller.maint_hit_busies_r_reg[3]_0 , p_9_in, CLK, maint_srx_r, \maintenance_request.maint_req_r_lcl_reg , SR, \periodic_read_request.periodic_rd_r_lcl_reg , periodic_rd_grant_r, D, periodic_rd_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , use_addr, E, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , idle_r_lcl_reg, head_r, idle_r_lcl_reg_0, idle_r_lcl_reg_1, rb_hit_busy_r, maint_req_r, rstdiv0_sync_r1_reg_rep__22, \generate_maint_cmds.insert_maint_r_lcl_reg_0 , \maintenance_request.maint_zq_r_lcl_reg , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 , \app_cmd_r1_reg[0] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ); output wait_for_maint_r_lcl_reg; output was_wr_reg_0; output \q_entry_r_reg[1] ; output accept_ns; output was_wr; output insert_maint_r1_lcl_reg; output \maint_controller.maint_wip_r_lcl_reg_0 ; output req_periodic_rd_r_lcl_reg; output clear_periodic_rd_request; output \maint_controller.maint_rdy_r1_reg_0 ; output head_r_lcl_reg; output \q_entry_r_reg[0] ; output head_r_lcl_reg_0; output ordered_r_lcl_reg; output head_r_lcl_reg_1; output ordered_r_lcl_reg_0; output head_r_lcl_reg_2; output ordered_r_lcl_reg_1; output periodic_rd_insert; output \q_entry_r_reg[0]_0 ; output \q_entry_r_reg[1]_0 ; output pass_open_bank_r_lcl_reg; output pass_open_bank_r_lcl_reg_0; output [4:0]Q; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; output [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ; input p_9_in; input CLK; input maint_srx_r; input \maintenance_request.maint_req_r_lcl_reg ; input [0:0]SR; input \periodic_read_request.periodic_rd_r_lcl_reg ; input periodic_rd_grant_r; input [3:0]D; input periodic_rd_r; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; input use_addr; input [0:0]E; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; input [0:0]idle_r_lcl_reg; input [3:0]head_r; input [0:0]idle_r_lcl_reg_0; input [0:0]idle_r_lcl_reg_1; input [1:0]rb_hit_busy_r; input maint_req_r; input rstdiv0_sync_r1_reg_rep__22; input \generate_maint_cmds.insert_maint_r_lcl_reg_0 ; input \maintenance_request.maint_zq_r_lcl_reg ; input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ; input \app_cmd_r1_reg[0] ; input [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ; wire CLK; wire [3:0]D; wire [0:0]E; wire [4:0]Q; wire [0:0]SR; wire accept_ns; wire \app_cmd_r1_reg[0] ; wire clear_periodic_rd_request; wire \generate_maint_cmds.insert_maint_r_lcl_reg_0 ; wire [3:0]head_r; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire [0:0]idle_r_lcl_reg; wire [0:0]idle_r_lcl_reg_0; wire [0:0]idle_r_lcl_reg_1; wire insert_maint_ns; wire insert_maint_r1_lcl_reg; wire [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ; wire \maint_controller.maint_rdy_r1_reg_0 ; wire \maint_controller.maint_wip_r_lcl_i_1_n_0 ; wire \maint_controller.maint_wip_r_lcl_reg_0 ; wire maint_rdy; wire maint_rdy_r1; wire maint_req_r; wire maint_srx_r; wire maint_srx_r1; wire \maintenance_request.maint_req_r_lcl_reg ; wire \maintenance_request.maint_zq_r_lcl_reg ; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire p_9_in; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire periodic_rd_ack_ns; wire periodic_rd_grant_r; wire periodic_rd_insert; wire periodic_rd_r; wire \periodic_read_request.periodic_rd_r_lcl_reg ; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[1] ; wire \q_entry_r_reg[1]_0 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [1:0]rb_hit_busy_r; wire req_periodic_rd_r_lcl_reg; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ; wire [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ; wire [7:2]rfc_zq_xsdll_timer_ns; wire [7:5]rfc_zq_xsdll_timer_r; wire rstdiv0_sync_r1_reg_rep__22; wire use_addr; wire wait_for_maint_r_lcl_reg; wire was_wr; wire was_wr0; wire was_wr_reg_0; FDRE accept_internal_r_reg (.C(CLK), .CE(1'b1), .D(p_9_in), .Q(wait_for_maint_r_lcl_reg), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1096" *) LUT4 #( .INIT(16'h80AA)) accept_r_i_1 (.I0(p_9_in), .I1(was_wr_reg_0), .I2(req_periodic_rd_r_lcl_reg), .I3(periodic_rd_r), .O(accept_ns)); FDRE accept_r_reg (.C(CLK), .CE(1'b1), .D(accept_ns), .Q(\q_entry_r_reg[1] ), .R(1'b0)); LUT4 #( .INIT(16'h4F44)) \generate_maint_cmds.insert_maint_r_lcl_i_1 (.I0(maint_srx_r1), .I1(maint_srx_r), .I2(maint_rdy_r1), .I3(maint_rdy), .O(insert_maint_ns)); FDRE \generate_maint_cmds.insert_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(insert_maint_ns), .Q(insert_maint_r1_lcl_reg), .R(1'b0)); LUT5 #( .INIT(32'hE0000000)) i___0_i_2 (.I0(was_wr_reg_0), .I1(use_addr), .I2(wait_for_maint_r_lcl_reg), .I3(head_r[0]), .I4(E), .O(\q_entry_r_reg[0] )); LUT6 #( .INIT(64'h0CCC0CCC08880000)) i___10_i_6 (.I0(\q_entry_r_reg[1] ), .I1(idle_r_lcl_reg_0), .I2(head_r[2]), .I3(wait_for_maint_r_lcl_reg), .I4(use_addr), .I5(was_wr_reg_0), .O(head_r_lcl_reg_1)); LUT5 #( .INIT(32'hE0000000)) i___13_i_2 (.I0(was_wr_reg_0), .I1(use_addr), .I2(wait_for_maint_r_lcl_reg), .I3(head_r[3]), .I4(idle_r_lcl_reg_1), .O(ordered_r_lcl_reg_1)); (* SOFT_HLUTNM = "soft_lutpair1097" *) LUT4 #( .INIT(16'hAA80)) i___13_i_3 (.I0(rb_hit_busy_r[1]), .I1(use_addr), .I2(\q_entry_r_reg[1] ), .I3(was_wr_reg_0), .O(pass_open_bank_r_lcl_reg)); LUT6 #( .INIT(64'h0CCC0CCC08880000)) i___14_i_5 (.I0(\q_entry_r_reg[1] ), .I1(idle_r_lcl_reg_1), .I2(head_r[3]), .I3(wait_for_maint_r_lcl_reg), .I4(use_addr), .I5(was_wr_reg_0), .O(head_r_lcl_reg_2)); LUT6 #( .INIT(64'h3333300055555555)) i___1_i_6 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .I1(\q_entry_r_reg[0] ), .I2(use_addr), .I3(\q_entry_r_reg[1] ), .I4(was_wr_reg_0), .I5(E), .O(head_r_lcl_reg)); (* SOFT_HLUTNM = "soft_lutpair1099" *) LUT3 #( .INIT(8'hBA)) i___2_i_2 (.I0(\maint_controller.maint_wip_r_lcl_reg_0 ), .I1(req_periodic_rd_r_lcl_reg), .I2(maint_req_r), .O(\maint_controller.maint_rdy_r1_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair1098" *) LUT2 #( .INIT(4'h8)) i___30_i_3 (.I0(was_wr_reg_0), .I1(periodic_rd_grant_r), .O(clear_periodic_rd_request)); (* SOFT_HLUTNM = "soft_lutpair1097" *) LUT3 #( .INIT(8'hEA)) i___42_i_1 (.I0(was_wr_reg_0), .I1(\q_entry_r_reg[1] ), .I2(use_addr), .O(\q_entry_r_reg[1]_0 )); LUT5 #( .INIT(32'hE0000000)) i___5_i_2 (.I0(was_wr_reg_0), .I1(use_addr), .I2(wait_for_maint_r_lcl_reg), .I3(head_r[1]), .I4(idle_r_lcl_reg), .O(ordered_r_lcl_reg)); LUT6 #( .INIT(64'h3333300055555555)) i___6_i_4 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .I1(ordered_r_lcl_reg), .I2(use_addr), .I3(\q_entry_r_reg[1] ), .I4(was_wr_reg_0), .I5(idle_r_lcl_reg), .O(head_r_lcl_reg_0)); LUT5 #( .INIT(32'hE0000000)) i___9_i_2 (.I0(was_wr_reg_0), .I1(use_addr), .I2(wait_for_maint_r_lcl_reg), .I3(head_r[2]), .I4(idle_r_lcl_reg_0), .O(ordered_r_lcl_reg_0)); (* SOFT_HLUTNM = "soft_lutpair1098" *) LUT4 #( .INIT(16'hAA80)) i___9_i_3 (.I0(rb_hit_busy_r[0]), .I1(use_addr), .I2(\q_entry_r_reg[1] ), .I3(was_wr_reg_0), .O(pass_open_bank_r_lcl_reg_0)); FDRE \maint_controller.maint_hit_busies_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [0]), .R(1'b0)); FDRE \maint_controller.maint_hit_busies_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [1]), .R(1'b0)); FDRE \maint_controller.maint_hit_busies_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [2]), .R(1'b0)); FDRE \maint_controller.maint_hit_busies_r_reg[3] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [3]), .R(1'b0)); LUT5 #( .INIT(32'h00000002)) \maint_controller.maint_rdy_r1_i_1 (.I0(\maint_controller.maint_rdy_r1_reg_0 ), .I1(D[2]), .I2(D[1]), .I3(D[0]), .I4(D[3]), .O(maint_rdy)); FDRE \maint_controller.maint_rdy_r1_reg (.C(CLK), .CE(1'b1), .D(maint_rdy), .Q(maint_rdy_r1), .R(1'b0)); FDRE \maint_controller.maint_srx_r1_reg (.C(CLK), .CE(1'b1), .D(maint_srx_r), .Q(maint_srx_r1), .R(1'b0)); LUT4 #( .INIT(16'hFFBF)) \maint_controller.maint_wip_r_lcl_i_1 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .O(\maint_controller.maint_wip_r_lcl_i_1_n_0 )); FDRE \maint_controller.maint_wip_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maint_controller.maint_wip_r_lcl_i_1_n_0 ), .Q(\maint_controller.maint_wip_r_lcl_reg_0 ), .R(\maintenance_request.maint_req_r_lcl_reg )); (* SOFT_HLUTNM = "soft_lutpair1096" *) LUT4 #( .INIT(16'h2A00)) periodic_rd_ack_r_lcl_i_1 (.I0(p_9_in), .I1(was_wr_reg_0), .I2(req_periodic_rd_r_lcl_reg), .I3(periodic_rd_r), .O(periodic_rd_ack_ns)); FDRE periodic_rd_ack_r_lcl_reg (.C(CLK), .CE(1'b1), .D(periodic_rd_ack_ns), .Q(was_wr_reg_0), .R(1'b0)); FDRE periodic_rd_cntr_r_reg (.C(CLK), .CE(1'b1), .D(\periodic_read_request.periodic_rd_r_lcl_reg ), .Q(req_periodic_rd_r_lcl_reg), .R(SR)); LUT5 #( .INIT(32'h96696996)) \q_entry_r[0]_i_2__2 (.I0(\q_entry_r_reg[1]_0 ), .I1(idle_r_lcl_reg_1), .I2(idle_r_lcl_reg_0), .I3(idle_r_lcl_reg), .I4(E), .O(\q_entry_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair1099" *) LUT3 #( .INIT(8'h2A)) req_periodic_rd_r_lcl_i_1 (.I0(periodic_rd_r), .I1(req_periodic_rd_r_lcl_reg), .I2(was_wr_reg_0), .O(periodic_rd_insert)); (* SOFT_HLUTNM = "soft_lutpair1095" *) LUT5 #( .INIT(32'h11100001)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(insert_maint_r1_lcl_reg), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .O(rfc_zq_xsdll_timer_ns[2])); LUT6 #( .INIT(64'hEEEEEEEBAAAAAAAA)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg ), .I1(Q[3]), .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ), .O(rfc_zq_xsdll_timer_ns[3])); (* SOFT_HLUTNM = "soft_lutpair1095" *) LUT2 #( .INIT(4'h1)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 (.I0(insert_maint_r1_lcl_reg), .I1(rstdiv0_sync_r1_reg_rep__22), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAEEEB)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg ), .I1(rfc_zq_xsdll_timer_r[5]), .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ), .I3(Q[4]), .I4(insert_maint_r1_lcl_reg), .I5(rstdiv0_sync_r1_reg_rep__22), .O(rfc_zq_xsdll_timer_ns[5])); LUT6 #( .INIT(64'h1111111000000001)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(insert_maint_r1_lcl_reg), .I2(Q[4]), .I3(rfc_zq_xsdll_timer_r[5]), .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ), .I5(rfc_zq_xsdll_timer_r[6]), .O(rfc_zq_xsdll_timer_ns[6])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .I4(insert_maint_r1_lcl_reg), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'hFFFFFFFF02000202)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2 (.I0(rfc_zq_xsdll_timer_r[7]), .I1(rstdiv0_sync_r1_reg_rep__22), .I2(insert_maint_r1_lcl_reg), .I3(rfc_zq_xsdll_timer_r[6]), .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ), .I5(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ), .O(rfc_zq_xsdll_timer_ns[7])); LUT5 #( .INIT(32'hFFFFFFFE)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3 (.I0(Q[4]), .I1(rfc_zq_xsdll_timer_r[5]), .I2(rfc_zq_xsdll_timer_r[7]), .I3(Q[3]), .I4(rfc_zq_xsdll_timer_r[6]), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4 (.I0(Q[4]), .I1(rfc_zq_xsdll_timer_r[5]), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(Q[3]), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 )); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [0]), .Q(Q[0]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [1]), .Q(Q[1]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[2]), .Q(Q[2]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[3]), .Q(Q[3]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [2]), .Q(Q[4]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[5]), .Q(rfc_zq_xsdll_timer_r[5]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[6]), .Q(rfc_zq_xsdll_timer_r[6]), .R(1'b0)); FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (.C(CLK), .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .D(rfc_zq_xsdll_timer_ns[7]), .Q(rfc_zq_xsdll_timer_r[7]), .R(1'b0)); LUT3 #( .INIT(8'h8A)) was_wr_i_1 (.I0(\app_cmd_r1_reg[0] ), .I1(was_wr_reg_0), .I2(periodic_rd_r), .O(was_wr0)); FDRE was_wr_reg (.C(CLK), .CE(1'b1), .D(was_wr0), .Q(was_wr), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_bank_compare (req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, req_priority_r, q_has_priority_r_reg, row_hit_r_12, granted_col_r_reg, \grant_r_reg[3] , \grant_r_reg[3]_0 , ras_timer_zero_r_reg, \ras_timer_r_reg[0] , \grant_r_reg[1] , pass_open_bank_ns, p_13_out, start_wtp_timer0, \cmd_pipe_plus.mc_address_reg[44] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_address_reg[24] , E, periodic_rd_insert, CLK, hi_priority, p_28_out, rd_wr_r_lcl_reg_0, \rtw_timer.rtw_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1] , demand_priority_r_reg, col_wait_r_reg, rd_wr_r_lcl_reg_1, order_q_r, \grant_r_reg[3]_1 , rd_wr_r, req_wr_r, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , idle_r_lcl_reg, periodic_rd_ack_r_lcl_reg, periodic_rd_cntr_r_reg, periodic_rd_r, periodic_rd_ack_r_lcl_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , pass_open_bank_r_lcl_reg, pre_passing_open_bank_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 , req_wr_r_lcl_reg_0, tail_r_28, rb_hit_busy_r_reg_0, pre_wait_r, pre_bm_end_r_15, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , wait_for_maint_r_20, \app_addr_r1_reg[27] , idle_r_lcl_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] ); output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output req_priority_r; output q_has_priority_r_reg; output row_hit_r_12; output granted_col_r_reg; output \grant_r_reg[3] ; output \grant_r_reg[3]_0 ; output ras_timer_zero_r_reg; output \ras_timer_r_reg[0] ; output \grant_r_reg[1] ; output pass_open_bank_ns; output p_13_out; output start_wtp_timer0; output [14:0]\cmd_pipe_plus.mc_address_reg[44] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input [0:0]E; input periodic_rd_insert; input CLK; input hi_priority; input p_28_out; input rd_wr_r_lcl_reg_0; input \rtw_timer.rtw_cnt_r_reg[1] ; input \wtr_timer.wtr_cnt_r_reg[1] ; input demand_priority_r_reg; input col_wait_r_reg; input rd_wr_r_lcl_reg_1; input [1:0]order_q_r; input [1:0]\grant_r_reg[3]_1 ; input [0:0]rd_wr_r; input [0:0]req_wr_r; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input idle_r_lcl_reg; input periodic_rd_ack_r_lcl_reg; input periodic_rd_cntr_r_reg; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg_0; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; input pass_open_bank_r_lcl_reg; input pre_passing_open_bank_r; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; input req_wr_r_lcl_reg_0; input tail_r_28; input rb_hit_busy_r_reg_0; input pre_wait_r; input pre_bm_end_r_15; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input wait_for_maint_r_20; input [14:0]\app_addr_r1_reg[27] ; input idle_r_lcl_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; wire CLK; wire [0:0]E; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire bm_end_r1_reg; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [14:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire demand_priority_r_reg; wire \grant_r[3]_i_11_n_0 ; wire \grant_r_reg[1] ; wire \grant_r_reg[3] ; wire \grant_r_reg[3]_0 ; wire [1:0]\grant_r_reg[3]_1 ; wire granted_col_r_reg; wire hi_priority; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [1:0]order_q_r; wire p_13_out; wire p_28_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_i_2__2_n_0; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire pre_bm_end_r_15; wire pre_passing_open_bank_r; wire pre_wait_r; wire q_has_priority_r_reg; wire \ras_timer_r_reg[0] ; wire ras_timer_zero_r_reg; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; wire rb_hit_busy_r_reg_0; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire [0:0]rd_wr_r; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire [1:0]req_cmd_r; wire \req_cmd_r[0]_i_1__1_n_0 ; wire \req_cmd_r[1]_i_1__1_n_0 ; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire [0:0]req_wr_r; wire req_wr_r_lcl0; wire req_wr_r_lcl_reg_0; wire row_hit_ns; wire row_hit_ns_carry__0_i_1__2_n_0; wire row_hit_ns_carry_i_1__2_n_0; wire row_hit_ns_carry_i_2__2_n_0; wire row_hit_ns_carry_i_3__2_n_0; wire row_hit_ns_carry_i_4__2_n_0; wire row_hit_ns_carry_n_0; wire row_hit_ns_carry_n_1; wire row_hit_ns_carry_n_2; wire row_hit_ns_carry_n_3; wire row_hit_r_12; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire start_wtp_timer0; wire tail_r_28; wire wait_for_maint_r_20; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED; wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED; wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1087" *) LUT5 #( .INIT(32'hFFFF7000)) bm_end_r1_i_1__1 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(pass_open_bank_r_lcl_reg), .I3(\grant_r_reg[3]_1 [1]), .I4(pre_bm_end_r_15), .O(p_13_out)); LUT2 #( .INIT(4'h2)) \grant_r[1]_i_2 (.I0(\grant_r_reg[3] ), .I1(rd_wr_r_lcl_reg_0), .O(granted_col_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1086" *) LUT5 #( .INIT(32'h0000FF20)) \grant_r[3]_i_11 (.I0(\grant_r_reg[3]_0 ), .I1(rd_wr_r_lcl_reg_1), .I2(order_q_r[0]), .I3(order_q_r[1]), .I4(\rd_this_rank_r_reg[0] ), .O(\grant_r[3]_i_11_n_0 )); LUT6 #( .INIT(64'hDF00DFDFDFDFDFDF)) \grant_r[3]_i_13 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(\grant_r_reg[3]_1 [1]), .I3(rd_wr_r), .I4(\grant_r_reg[3]_1 [0]), .I5(req_wr_r), .O(\grant_r_reg[3]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFF35)) \grant_r[3]_i_5 (.I0(\rtw_timer.rtw_cnt_r_reg[1] ), .I1(\wtr_timer.wtr_cnt_r_reg[1] ), .I2(\rd_this_rank_r_reg[0] ), .I3(demand_priority_r_reg), .I4(\grant_r[3]_i_11_n_0 ), .I5(col_wait_r_reg), .O(\grant_r_reg[3] )); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___36_i_2 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[3]_1 [1]), .I5(pre_passing_open_bank_r), .O(\ras_timer_r_reg[0] )); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___37_i_3 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[3]_1 [1]), .I5(pre_passing_open_bank_r), .O(\grant_r_reg[1] )); LUT6 #( .INIT(64'h4444544444444444)) pass_open_bank_r_lcl_i_1__1 (.I0(req_wr_r_lcl_reg_0), .I1(pass_open_bank_r_lcl_reg), .I2(tail_r_28), .I3(rb_hit_busy_r_reg_0), .I4(pre_wait_r), .I5(pass_open_bank_r_lcl_i_2__2_n_0), .O(pass_open_bank_ns)); LUT5 #( .INIT(32'hAAAA00A2)) pass_open_bank_r_lcl_i_2__2 (.I0(row_hit_r_12), .I1(maint_req_r), .I2(periodic_rd_cntr_r_reg), .I3(\maint_controller.maint_wip_r_lcl_reg ), .I4(wait_for_maint_r_20), .O(pass_open_bank_r_lcl_i_2__2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1087" *) LUT2 #( .INIT(4'hB)) ras_timer_zero_r_i_2__0 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[3]_1 [1]), .O(ras_timer_zero_r_reg)); FDRE rb_hit_busy_r_reg (.C(CLK), .CE(1'b1), .D(p_28_out), .Q(q_has_priority_r_reg), .R(1'b0)); LUT4 #( .INIT(16'h2F20)) rd_wr_r_lcl_i_1__1 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[3]_1 [1]), .I2(idle_r_lcl_reg), .I3(periodic_rd_ack_r_lcl_reg_0), .O(rd_wr_ns)); FDRE rd_wr_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rd_wr_ns), .Q(\rd_this_rank_r_reg[0] ), .R(1'b0)); FDRE \req_bank_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [0]), .Q(\cmd_pipe_plus.mc_bank_reg[8] [0]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [1]), .Q(\cmd_pipe_plus.mc_bank_reg[8] [1]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [2]), .Q(\cmd_pipe_plus.mc_bank_reg[8] [2]), .R(1'b0)); LUT6 #( .INIT(64'hB8BBBBBBB8B8B8B8)) \req_cmd_r[0]_i_1__1 (.I0(req_cmd_r[0]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r1_reg[0] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'hB8888888B8B8B8B8)) \req_cmd_r[1]_i_1__1 (.I0(req_cmd_r[1]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r2_reg[1] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[1]_i_1__1_n_0 )); FDRE \req_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[0]_i_1__1_n_0 ), .Q(req_cmd_r[0]), .R(1'b0)); FDRE \req_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[1]_i_1__1_n_0 ), .Q(req_cmd_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [0]), .Q(\cmd_pipe_plus.mc_address_reg[24] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [1]), .Q(\cmd_pipe_plus.mc_address_reg[24] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [2]), .Q(\cmd_pipe_plus.mc_address_reg[24] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [3]), .Q(\cmd_pipe_plus.mc_address_reg[24] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [4]), .Q(\cmd_pipe_plus.mc_address_reg[24] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [5]), .Q(\cmd_pipe_plus.mc_address_reg[24] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [6]), .Q(\cmd_pipe_plus.mc_address_reg[24] [6]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[0] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [0]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[1] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [1]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[2] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [2]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [3]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [4]), .R(1'b0)); FDRE req_periodic_rd_r_lcl_reg (.C(CLK), .CE(E), .D(periodic_rd_insert), .Q(req_periodic_rd_r), .R(1'b0)); FDRE req_priority_r_reg (.C(CLK), .CE(E), .D(hi_priority), .Q(req_priority_r), .R(1'b0)); FDRE \req_row_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [0]), .Q(\cmd_pipe_plus.mc_address_reg[44] [0]), .R(1'b0)); FDRE \req_row_r_lcl_reg[10] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [10]), .Q(\cmd_pipe_plus.mc_address_reg[44] [10]), .R(1'b0)); FDRE \req_row_r_lcl_reg[11] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [11]), .Q(\cmd_pipe_plus.mc_address_reg[44] [11]), .R(1'b0)); FDRE \req_row_r_lcl_reg[12] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [12]), .Q(\cmd_pipe_plus.mc_address_reg[44] [12]), .R(1'b0)); FDRE \req_row_r_lcl_reg[13] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [13]), .Q(\cmd_pipe_plus.mc_address_reg[44] [13]), .R(1'b0)); FDRE \req_row_r_lcl_reg[14] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [14]), .Q(\cmd_pipe_plus.mc_address_reg[44] [14]), .R(1'b0)); FDRE \req_row_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [1]), .Q(\cmd_pipe_plus.mc_address_reg[44] [1]), .R(1'b0)); FDRE \req_row_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [2]), .Q(\cmd_pipe_plus.mc_address_reg[44] [2]), .R(1'b0)); FDRE \req_row_r_lcl_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [3]), .Q(\cmd_pipe_plus.mc_address_reg[44] [3]), .R(1'b0)); FDRE \req_row_r_lcl_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [4]), .Q(\cmd_pipe_plus.mc_address_reg[44] [4]), .R(1'b0)); FDRE \req_row_r_lcl_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [5]), .Q(\cmd_pipe_plus.mc_address_reg[44] [5]), .R(1'b0)); FDRE \req_row_r_lcl_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [6]), .Q(\cmd_pipe_plus.mc_address_reg[44] [6]), .R(1'b0)); FDRE \req_row_r_lcl_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [7]), .Q(\cmd_pipe_plus.mc_address_reg[44] [7]), .R(1'b0)); FDRE \req_row_r_lcl_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [8]), .Q(\cmd_pipe_plus.mc_address_reg[44] [8]), .R(1'b0)); FDRE \req_row_r_lcl_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [9]), .Q(\cmd_pipe_plus.mc_address_reg[44] [9]), .R(1'b0)); LUT6 #( .INIT(64'hCCCC0A0FFFFF0A0F)) req_wr_r_lcl_i_1__1 (.I0(\app_cmd_r2_reg[1] ), .I1(req_cmd_r[1]), .I2(periodic_rd_insert), .I3(\app_cmd_r1_reg[0] ), .I4(idle_r_lcl_reg), .I5(req_cmd_r[0]), .O(req_wr_r_lcl0)); FDRE req_wr_r_lcl_reg (.C(CLK), .CE(E), .D(req_wr_r_lcl0), .Q(bm_end_r1_reg), .R(1'b0)); CARRY4 row_hit_ns_carry (.CI(1'b0), .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]), .S({row_hit_ns_carry_i_1__2_n_0,row_hit_ns_carry_i_2__2_n_0,row_hit_ns_carry_i_3__2_n_0,row_hit_ns_carry_i_4__2_n_0})); CARRY4 row_hit_ns_carry__0 (.CI(row_hit_ns_carry_n_0), .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__2_n_0})); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry__0_i_1__2 (.I0(\cmd_pipe_plus.mc_address_reg[44] [14]), .I1(\app_addr_r1_reg[27] [14]), .I2(\cmd_pipe_plus.mc_address_reg[44] [13]), .I3(\app_addr_r1_reg[27] [13]), .I4(\app_addr_r1_reg[27] [12]), .I5(\cmd_pipe_plus.mc_address_reg[44] [12]), .O(row_hit_ns_carry__0_i_1__2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_1__2 (.I0(\cmd_pipe_plus.mc_address_reg[44] [11]), .I1(\app_addr_r1_reg[27] [11]), .I2(\cmd_pipe_plus.mc_address_reg[44] [10]), .I3(\app_addr_r1_reg[27] [10]), .I4(\app_addr_r1_reg[27] [9]), .I5(\cmd_pipe_plus.mc_address_reg[44] [9]), .O(row_hit_ns_carry_i_1__2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_2__2 (.I0(\cmd_pipe_plus.mc_address_reg[44] [8]), .I1(\app_addr_r1_reg[27] [8]), .I2(\cmd_pipe_plus.mc_address_reg[44] [7]), .I3(\app_addr_r1_reg[27] [7]), .I4(\app_addr_r1_reg[27] [6]), .I5(\cmd_pipe_plus.mc_address_reg[44] [6]), .O(row_hit_ns_carry_i_2__2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_3__2 (.I0(\cmd_pipe_plus.mc_address_reg[44] [5]), .I1(\app_addr_r1_reg[27] [5]), .I2(\cmd_pipe_plus.mc_address_reg[44] [3]), .I3(\app_addr_r1_reg[27] [3]), .I4(\app_addr_r1_reg[27] [4]), .I5(\cmd_pipe_plus.mc_address_reg[44] [4]), .O(row_hit_ns_carry_i_3__2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_4__2 (.I0(\cmd_pipe_plus.mc_address_reg[44] [2]), .I1(\app_addr_r1_reg[27] [2]), .I2(\cmd_pipe_plus.mc_address_reg[44] [1]), .I3(\app_addr_r1_reg[27] [1]), .I4(\app_addr_r1_reg[27] [0]), .I5(\cmd_pipe_plus.mc_address_reg[44] [0]), .O(row_hit_ns_carry_i_4__2_n_0)); FDRE row_hit_r_reg (.C(CLK), .CE(1'b1), .D(row_hit_ns), .Q(row_hit_r_12), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1086" *) LUT1 #( .INIT(2'h1)) \wr_this_rank_r[0]_i_1__2 (.I0(\rd_this_rank_r_reg[0] ), .O(start_wtp_timer0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_compare" *) module ddr3_if_mig_7series_v4_0_bank_compare_0 (req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, q_has_priority_r_reg, row_hit_r_5, \order_q_r_reg[0] , req_bank_rdy_r_reg, \order_q_r_reg[1] , demand_priority_r_reg, req_bank_rdy_ns, ras_timer_zero_r_reg, \ras_timer_r_reg[0] , \grant_r_reg[1] , \grant_r_reg[3] , pass_open_bank_ns, p_52_out, start_wtp_timer0, \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_address_reg[40] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_address_reg[24] , E, periodic_rd_insert, CLK, hi_priority, p_67_out, ordered_r_lcl_reg, ordered_r, q_has_priority_11, order_q_r, col_wait_r_reg, \grant_r_reg[3]_0 , rd_wr_r_lcl_reg_0, req_wr_r_lcl_reg_0, rd_wr_r_lcl_reg_1, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , idle_r_lcl_reg, periodic_rd_ack_r_lcl_reg, periodic_rd_cntr_r_reg, periodic_rd_r, periodic_rd_ack_r_lcl_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , pass_open_bank_r_lcl_reg, pre_passing_open_bank_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 , Q, req_wr_r_lcl_reg_1, tail_r_26, rb_hit_busy_r_reg_0, pre_wait_r, pre_bm_end_r_9, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , wait_for_maint_r_19, \app_addr_r1_reg[27] , \req_row_r_lcl_reg[10]_0 , act_wait_r_lcl_reg, \grant_r_reg[3]_1 , act_wait_r_lcl_reg_0, idle_r_lcl_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] ); output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output q_has_priority_r_reg; output row_hit_r_5; output \order_q_r_reg[0] ; output req_bank_rdy_r_reg; output \order_q_r_reg[1] ; output demand_priority_r_reg; output req_bank_rdy_ns; output ras_timer_zero_r_reg; output \ras_timer_r_reg[0] ; output \grant_r_reg[1] ; output \grant_r_reg[3] ; output pass_open_bank_ns; output p_52_out; output start_wtp_timer0; output [14:0]\cmd_pipe_plus.mc_address_reg[44] ; output [0:0]\cmd_pipe_plus.mc_address_reg[40] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input [0:0]E; input periodic_rd_insert; input CLK; input hi_priority; input p_67_out; input [2:0]ordered_r_lcl_reg; input [0:0]ordered_r; input q_has_priority_11; input [1:0]order_q_r; input col_wait_r_reg; input [1:0]\grant_r_reg[3]_0 ; input rd_wr_r_lcl_reg_0; input req_wr_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input idle_r_lcl_reg; input periodic_rd_ack_r_lcl_reg; input periodic_rd_cntr_r_reg; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg_0; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; input pass_open_bank_r_lcl_reg; input pre_passing_open_bank_r; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; input [0:0]Q; input req_wr_r_lcl_reg_1; input tail_r_26; input rb_hit_busy_r_reg_0; input pre_wait_r; input pre_bm_end_r_9; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input wait_for_maint_r_19; input [14:0]\app_addr_r1_reg[27] ; input \req_row_r_lcl_reg[10]_0 ; input act_wait_r_lcl_reg; input [1:0]\grant_r_reg[3]_1 ; input act_wait_r_lcl_reg_0; input idle_r_lcl_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; wire CLK; wire [0:0]E; wire [0:0]Q; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire bm_end_r1_reg; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [0:0]\cmd_pipe_plus.mc_address_reg[40] ; wire [14:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire demand_priority_r_reg; wire \grant_r_reg[1] ; wire \grant_r_reg[3] ; wire [1:0]\grant_r_reg[3]_0 ; wire [1:0]\grant_r_reg[3]_1 ; wire hi_priority; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [1:0]order_q_r; wire \order_q_r_reg[0] ; wire \order_q_r_reg[1] ; wire [0:0]ordered_r; wire [2:0]ordered_r_lcl_reg; wire p_52_out; wire p_67_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_i_2__1_n_0; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire pre_bm_end_r_9; wire pre_passing_open_bank_r; wire pre_wait_r; wire q_has_priority_11; wire q_has_priority_r_reg; wire \ras_timer_r_reg[0] ; wire ras_timer_zero_r_reg; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; wire rb_hit_busy_r_reg_0; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire req_bank_rdy_ns; wire req_bank_rdy_r_reg; wire [1:0]req_cmd_r; wire \req_cmd_r[0]_i_1__0_n_0 ; wire \req_cmd_r[1]_i_1__0_n_0 ; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire \req_row_r_lcl_reg[10]_0 ; wire req_wr_r_lcl0; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire row_hit_ns; wire row_hit_ns_carry__0_i_1__1_n_0; wire row_hit_ns_carry_i_1__1_n_0; wire row_hit_ns_carry_i_2__1_n_0; wire row_hit_ns_carry_i_3__1_n_0; wire row_hit_ns_carry_i_4__1_n_0; wire row_hit_ns_carry_n_0; wire row_hit_ns_carry_n_1; wire row_hit_ns_carry_n_2; wire row_hit_ns_carry_n_3; wire row_hit_r_5; wire start_wtp_timer0; wire tail_r_26; wire wait_for_maint_r_19; wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED; wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED; wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1078" *) LUT5 #( .INIT(32'hFFFF7000)) bm_end_r1_i_1__2 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(pass_open_bank_r_lcl_reg), .I3(\grant_r_reg[3]_0 [0]), .I4(pre_bm_end_r_9), .O(p_52_out)); LUT6 #( .INIT(64'hCCFCCCDDCCCCCCDD)) \cmd_pipe_plus.mc_address[40]_i_1 (.I0(\req_row_r_lcl_reg[10]_0 ), .I1(act_wait_r_lcl_reg), .I2(\cmd_pipe_plus.mc_address_reg[44] [10]), .I3(\grant_r_reg[3]_1 [1]), .I4(\grant_r_reg[3]_1 [0]), .I5(act_wait_r_lcl_reg_0), .O(\cmd_pipe_plus.mc_address_reg[40] )); LUT6 #( .INIT(64'hE0E0E0EEE0EEE0EE)) demand_priority_r_i_3 (.I0(req_priority_r), .I1(q_has_priority_11), .I2(\rd_this_rank_r_reg[0] ), .I3(order_q_r[1]), .I4(order_q_r[0]), .I5(req_bank_rdy_r_reg), .O(demand_priority_r_reg)); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___37_i_2 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[3]_0 [0]), .I5(pre_passing_open_bank_r), .O(\ras_timer_r_reg[0] )); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___38_i_2 (.I0(Q), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[3]_0 [0]), .I5(pre_passing_open_bank_r), .O(\grant_r_reg[3] )); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___56_i_4 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[3]_0 [0]), .I5(pre_passing_open_bank_r), .O(\grant_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1076" *) LUT5 #( .INIT(32'h96696996)) \order_q_r[0]_i_2 (.I0(req_bank_rdy_r_reg), .I1(ordered_r_lcl_reg[2]), .I2(ordered_r), .I3(ordered_r_lcl_reg[1]), .I4(ordered_r_lcl_reg[0]), .O(\order_q_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1076" *) LUT5 #( .INIT(32'h7EE8E881)) \order_q_r[1]_i_2 (.I0(req_bank_rdy_r_reg), .I1(ordered_r_lcl_reg[0]), .I2(ordered_r_lcl_reg[1]), .I3(ordered_r), .I4(ordered_r_lcl_reg[2]), .O(\order_q_r_reg[1] )); LUT6 #( .INIT(64'h4444544444444444)) pass_open_bank_r_lcl_i_1__2 (.I0(req_wr_r_lcl_reg_1), .I1(pass_open_bank_r_lcl_reg), .I2(tail_r_26), .I3(rb_hit_busy_r_reg_0), .I4(pre_wait_r), .I5(pass_open_bank_r_lcl_i_2__1_n_0), .O(pass_open_bank_ns)); LUT5 #( .INIT(32'hAAAA00A2)) pass_open_bank_r_lcl_i_2__1 (.I0(row_hit_r_5), .I1(maint_req_r), .I2(periodic_rd_cntr_r_reg), .I3(\maint_controller.maint_wip_r_lcl_reg ), .I4(wait_for_maint_r_19), .O(pass_open_bank_r_lcl_i_2__1_n_0)); (* SOFT_HLUTNM = "soft_lutpair1078" *) LUT2 #( .INIT(4'hB)) ras_timer_zero_r_i_2 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[3]_0 [0]), .O(ras_timer_zero_r_reg)); FDRE rb_hit_busy_r_reg (.C(CLK), .CE(1'b1), .D(p_67_out), .Q(q_has_priority_r_reg), .R(1'b0)); LUT4 #( .INIT(16'h2F20)) rd_wr_r_lcl_i_1__0 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[3]_0 [0]), .I2(idle_r_lcl_reg), .I3(periodic_rd_ack_r_lcl_reg_0), .O(rd_wr_ns)); FDRE rd_wr_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rd_wr_ns), .Q(\rd_this_rank_r_reg[0] ), .R(1'b0)); FDRE \req_bank_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [0]), .Q(\cmd_pipe_plus.mc_bank_reg[8] [0]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [1]), .Q(\cmd_pipe_plus.mc_bank_reg[8] [1]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [2]), .Q(\cmd_pipe_plus.mc_bank_reg[8] [2]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1077" *) LUT5 #( .INIT(32'h888A8A8A)) req_bank_rdy_r_i_1__0 (.I0(col_wait_r_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(order_q_r[1]), .I3(order_q_r[0]), .I4(req_bank_rdy_r_reg), .O(req_bank_rdy_ns)); LUT6 #( .INIT(64'h00000000DD0DDDDD)) req_bank_rdy_r_i_2 (.I0(bm_end_r1_reg), .I1(ras_timer_zero_r_reg), .I2(\grant_r_reg[3]_0 [1]), .I3(rd_wr_r_lcl_reg_0), .I4(req_wr_r_lcl_reg_0), .I5(rd_wr_r_lcl_reg_1), .O(req_bank_rdy_r_reg)); LUT6 #( .INIT(64'hB8BBBBBBB8B8B8B8)) \req_cmd_r[0]_i_1__0 (.I0(req_cmd_r[0]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r1_reg[0] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'hB8888888B8B8B8B8)) \req_cmd_r[1]_i_1__0 (.I0(req_cmd_r[1]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r2_reg[1] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[1]_i_1__0_n_0 )); FDRE \req_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[0]_i_1__0_n_0 ), .Q(req_cmd_r[0]), .R(1'b0)); FDRE \req_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[1]_i_1__0_n_0 ), .Q(req_cmd_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [0]), .Q(\cmd_pipe_plus.mc_address_reg[24] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [1]), .Q(\cmd_pipe_plus.mc_address_reg[24] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [2]), .Q(\cmd_pipe_plus.mc_address_reg[24] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [3]), .Q(\cmd_pipe_plus.mc_address_reg[24] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [4]), .Q(\cmd_pipe_plus.mc_address_reg[24] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [5]), .Q(\cmd_pipe_plus.mc_address_reg[24] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [6]), .Q(\cmd_pipe_plus.mc_address_reg[24] [6]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[0] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [0]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[1] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [1]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[2] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [2]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [3]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [4]), .R(1'b0)); FDRE req_periodic_rd_r_lcl_reg (.C(CLK), .CE(E), .D(periodic_rd_insert), .Q(req_periodic_rd_r), .R(1'b0)); FDRE req_priority_r_reg (.C(CLK), .CE(E), .D(hi_priority), .Q(req_priority_r), .R(1'b0)); FDRE \req_row_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [0]), .Q(\cmd_pipe_plus.mc_address_reg[44] [0]), .R(1'b0)); FDRE \req_row_r_lcl_reg[10] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [10]), .Q(\cmd_pipe_plus.mc_address_reg[44] [10]), .R(1'b0)); FDRE \req_row_r_lcl_reg[11] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [11]), .Q(\cmd_pipe_plus.mc_address_reg[44] [11]), .R(1'b0)); FDRE \req_row_r_lcl_reg[12] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [12]), .Q(\cmd_pipe_plus.mc_address_reg[44] [12]), .R(1'b0)); FDRE \req_row_r_lcl_reg[13] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [13]), .Q(\cmd_pipe_plus.mc_address_reg[44] [13]), .R(1'b0)); FDRE \req_row_r_lcl_reg[14] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [14]), .Q(\cmd_pipe_plus.mc_address_reg[44] [14]), .R(1'b0)); FDRE \req_row_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [1]), .Q(\cmd_pipe_plus.mc_address_reg[44] [1]), .R(1'b0)); FDRE \req_row_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [2]), .Q(\cmd_pipe_plus.mc_address_reg[44] [2]), .R(1'b0)); FDRE \req_row_r_lcl_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [3]), .Q(\cmd_pipe_plus.mc_address_reg[44] [3]), .R(1'b0)); FDRE \req_row_r_lcl_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [4]), .Q(\cmd_pipe_plus.mc_address_reg[44] [4]), .R(1'b0)); FDRE \req_row_r_lcl_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [5]), .Q(\cmd_pipe_plus.mc_address_reg[44] [5]), .R(1'b0)); FDRE \req_row_r_lcl_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [6]), .Q(\cmd_pipe_plus.mc_address_reg[44] [6]), .R(1'b0)); FDRE \req_row_r_lcl_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [7]), .Q(\cmd_pipe_plus.mc_address_reg[44] [7]), .R(1'b0)); FDRE \req_row_r_lcl_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [8]), .Q(\cmd_pipe_plus.mc_address_reg[44] [8]), .R(1'b0)); FDRE \req_row_r_lcl_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [9]), .Q(\cmd_pipe_plus.mc_address_reg[44] [9]), .R(1'b0)); LUT6 #( .INIT(64'hCCCC0A0FFFFF0A0F)) req_wr_r_lcl_i_1__0 (.I0(\app_cmd_r2_reg[1] ), .I1(req_cmd_r[1]), .I2(periodic_rd_insert), .I3(\app_cmd_r1_reg[0] ), .I4(idle_r_lcl_reg), .I5(req_cmd_r[0]), .O(req_wr_r_lcl0)); FDRE req_wr_r_lcl_reg (.C(CLK), .CE(E), .D(req_wr_r_lcl0), .Q(bm_end_r1_reg), .R(1'b0)); CARRY4 row_hit_ns_carry (.CI(1'b0), .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]), .S({row_hit_ns_carry_i_1__1_n_0,row_hit_ns_carry_i_2__1_n_0,row_hit_ns_carry_i_3__1_n_0,row_hit_ns_carry_i_4__1_n_0})); CARRY4 row_hit_ns_carry__0 (.CI(row_hit_ns_carry_n_0), .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__1_n_0})); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry__0_i_1__1 (.I0(\cmd_pipe_plus.mc_address_reg[44] [14]), .I1(\app_addr_r1_reg[27] [14]), .I2(\cmd_pipe_plus.mc_address_reg[44] [13]), .I3(\app_addr_r1_reg[27] [13]), .I4(\app_addr_r1_reg[27] [12]), .I5(\cmd_pipe_plus.mc_address_reg[44] [12]), .O(row_hit_ns_carry__0_i_1__1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_1__1 (.I0(\cmd_pipe_plus.mc_address_reg[44] [11]), .I1(\app_addr_r1_reg[27] [11]), .I2(\cmd_pipe_plus.mc_address_reg[44] [10]), .I3(\app_addr_r1_reg[27] [10]), .I4(\app_addr_r1_reg[27] [9]), .I5(\cmd_pipe_plus.mc_address_reg[44] [9]), .O(row_hit_ns_carry_i_1__1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_2__1 (.I0(\cmd_pipe_plus.mc_address_reg[44] [8]), .I1(\app_addr_r1_reg[27] [8]), .I2(\cmd_pipe_plus.mc_address_reg[44] [6]), .I3(\app_addr_r1_reg[27] [6]), .I4(\app_addr_r1_reg[27] [7]), .I5(\cmd_pipe_plus.mc_address_reg[44] [7]), .O(row_hit_ns_carry_i_2__1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_3__1 (.I0(\cmd_pipe_plus.mc_address_reg[44] [5]), .I1(\app_addr_r1_reg[27] [5]), .I2(\cmd_pipe_plus.mc_address_reg[44] [4]), .I3(\app_addr_r1_reg[27] [4]), .I4(\app_addr_r1_reg[27] [3]), .I5(\cmd_pipe_plus.mc_address_reg[44] [3]), .O(row_hit_ns_carry_i_3__1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_4__1 (.I0(\cmd_pipe_plus.mc_address_reg[44] [2]), .I1(\app_addr_r1_reg[27] [2]), .I2(\cmd_pipe_plus.mc_address_reg[44] [1]), .I3(\app_addr_r1_reg[27] [1]), .I4(\app_addr_r1_reg[27] [0]), .I5(\cmd_pipe_plus.mc_address_reg[44] [0]), .O(row_hit_ns_carry_i_4__1_n_0)); FDRE row_hit_r_reg (.C(CLK), .CE(1'b1), .D(row_hit_ns), .Q(row_hit_r_5), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1077" *) LUT1 #( .INIT(2'h1)) \wr_this_rank_r[0]_i_1__1 (.I0(\rd_this_rank_r_reg[0] ), .O(start_wtp_timer0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_compare" *) module ddr3_if_mig_7series_v4_0_bank_compare_1 (req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, req_priority_r, rb_hit_busy_r, row_hit_r_0, \grant_r_reg[1] , req_bank_rdy_r_reg, pass_open_bank_ns, head_r_lcl_reg, p_91_out, ras_timer_zero_r_reg, start_wtp_timer0, \cmd_pipe_plus.mc_address_reg[14] , \cmd_pipe_plus.mc_address_reg[40] , \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_address_reg[24] , E, periodic_rd_insert, CLK, hi_priority, p_106_out, \rtw_timer.rtw_cnt_r_reg[1] , col_wait_r_reg, override_demand_r_reg, \wtr_timer.wtr_cnt_r_reg[1] , order_q_r, req_wr_r_lcl_reg_0, rnk_config_valid_r_lcl_reg, req_wr_r_lcl_reg_1, pass_open_bank_r_lcl_reg, tail_r_24, accept_r_reg, pre_wait_r, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , idle_r_lcl_reg, periodic_rd_ack_r_lcl_reg, periodic_rd_cntr_r_reg, periodic_rd_r, \grant_r_reg[1]_0 , periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg, pre_bm_end_r_reg_0, rd_wr_r_lcl_reg_0, req_wr_r, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , wait_for_maint_r_18, \app_addr_r1_reg[27] , act_wait_r_lcl_reg, \grant_r_reg[1]_1 , act_wait_r_lcl_reg_0, \req_row_r_lcl_reg[10]_0 , idle_r_lcl_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] ); output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output req_priority_r; output [0:0]rb_hit_busy_r; output row_hit_r_0; output \grant_r_reg[1] ; output req_bank_rdy_r_reg; output pass_open_bank_ns; output head_r_lcl_reg; output p_91_out; output ras_timer_zero_r_reg; output start_wtp_timer0; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output \cmd_pipe_plus.mc_address_reg[40] ; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input [0:0]E; input periodic_rd_insert; input CLK; input hi_priority; input p_106_out; input \rtw_timer.rtw_cnt_r_reg[1] ; input col_wait_r_reg; input override_demand_r_reg; input \wtr_timer.wtr_cnt_r_reg[1] ; input [1:0]order_q_r; input req_wr_r_lcl_reg_0; input rnk_config_valid_r_lcl_reg; input req_wr_r_lcl_reg_1; input pass_open_bank_r_lcl_reg; input tail_r_24; input accept_r_reg; input pre_wait_r; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input idle_r_lcl_reg; input periodic_rd_ack_r_lcl_reg; input periodic_rd_cntr_r_reg; input periodic_rd_r; input [1:0]\grant_r_reg[1]_0 ; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg; input pre_bm_end_r_reg_0; input rd_wr_r_lcl_reg_0; input [0:0]req_wr_r; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input wait_for_maint_r_18; input [14:0]\app_addr_r1_reg[27] ; input act_wait_r_lcl_reg; input [1:0]\grant_r_reg[1]_1 ; input [0:0]act_wait_r_lcl_reg_0; input [0:0]\req_row_r_lcl_reg[10]_0 ; input idle_r_lcl_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; wire CLK; wire [0:0]E; wire accept_r_reg; wire act_wait_r_lcl_reg; wire [0:0]act_wait_r_lcl_reg_0; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire bm_end_r1_reg; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire \cmd_pipe_plus.mc_address_reg[40] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire col_wait_r_reg; wire \grant_r[1]_i_5_n_0 ; wire \grant_r_reg[1] ; wire [1:0]\grant_r_reg[1]_0 ; wire [1:0]\grant_r_reg[1]_1 ; wire head_r_lcl_reg; wire hi_priority; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [1:0]order_q_r; wire override_demand_r_reg; wire p_106_out; wire p_91_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_i_2__0_n_0; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire pre_bm_end_r_reg; wire pre_bm_end_r_reg_0; wire pre_wait_r; wire ras_timer_zero_r_reg; wire [0:0]rb_hit_busy_r; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_r_reg; wire [1:0]req_cmd_r; wire \req_cmd_r[0]_i_1_n_0 ; wire \req_cmd_r[1]_i_1_n_0 ; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire [0:0]\req_row_r_lcl_reg[10]_0 ; wire [0:0]req_wr_r; wire req_wr_r_lcl0; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire rnk_config_valid_r_lcl_reg; wire row_hit_ns; wire row_hit_ns_carry__0_i_1__0_n_0; wire row_hit_ns_carry_i_1__0_n_0; wire row_hit_ns_carry_i_2__0_n_0; wire row_hit_ns_carry_i_3__0_n_0; wire row_hit_ns_carry_i_4__0_n_0; wire row_hit_ns_carry_n_0; wire row_hit_ns_carry_n_1; wire row_hit_ns_carry_n_2; wire row_hit_ns_carry_n_3; wire row_hit_r_0; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire start_wtp_timer0; wire tail_r_24; wire wait_for_maint_r_18; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED; wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED; wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1064" *) LUT5 #( .INIT(32'hFFFF7000)) bm_end_r1_i_1 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(pass_open_bank_r_lcl_reg), .I3(\grant_r_reg[1]_0 [1]), .I4(pre_bm_end_r_reg_0), .O(p_91_out)); LUT6 #( .INIT(64'h707F7F7F7F7F7F7F)) \cmd_pipe_plus.mc_address[40]_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[14] [10]), .I1(act_wait_r_lcl_reg), .I2(\grant_r_reg[1]_1 [1]), .I3(\grant_r_reg[1]_1 [0]), .I4(act_wait_r_lcl_reg_0), .I5(\req_row_r_lcl_reg[10]_0 ), .O(\cmd_pipe_plus.mc_address_reg[40] )); LUT6 #( .INIT(64'hFFFCFFFDFFFFFFFD)) \grant_r[1]_i_3 (.I0(\rtw_timer.rtw_cnt_r_reg[1] ), .I1(col_wait_r_reg), .I2(\grant_r[1]_i_5_n_0 ), .I3(override_demand_r_reg), .I4(\rd_this_rank_r_reg[0] ), .I5(\wtr_timer.wtr_cnt_r_reg[1] ), .O(\grant_r_reg[1] )); LUT6 #( .INIT(64'hFFFFFFFF44544444)) \grant_r[1]_i_5 (.I0(\rd_this_rank_r_reg[0] ), .I1(order_q_r[1]), .I2(order_q_r[0]), .I3(req_bank_rdy_r_reg), .I4(req_wr_r_lcl_reg_0), .I5(rnk_config_valid_r_lcl_reg), .O(\grant_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000080AAAAAA)) i___10_i_2 (.I0(pre_bm_end_r_reg), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[1]_0 [1]), .I5(pre_bm_end_r_reg_0), .O(head_r_lcl_reg)); LUT6 #( .INIT(64'h4444544444444444)) pass_open_bank_r_lcl_i_1 (.I0(req_wr_r_lcl_reg_1), .I1(pass_open_bank_r_lcl_reg), .I2(tail_r_24), .I3(accept_r_reg), .I4(pre_wait_r), .I5(pass_open_bank_r_lcl_i_2__0_n_0), .O(pass_open_bank_ns)); LUT5 #( .INIT(32'hAAAA00A2)) pass_open_bank_r_lcl_i_2__0 (.I0(row_hit_r_0), .I1(maint_req_r), .I2(periodic_rd_cntr_r_reg), .I3(\maint_controller.maint_wip_r_lcl_reg ), .I4(wait_for_maint_r_18), .O(pass_open_bank_r_lcl_i_2__0_n_0)); (* SOFT_HLUTNM = "soft_lutpair1064" *) LUT2 #( .INIT(4'hB)) ras_timer_zero_r_i_2__2 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[1]_0 [1]), .O(ras_timer_zero_r_reg)); FDRE rb_hit_busy_r_reg (.C(CLK), .CE(1'b1), .D(p_106_out), .Q(rb_hit_busy_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1065" *) LUT4 #( .INIT(16'h2F20)) rd_wr_r_lcl_i_1 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[1]_0 [1]), .I2(idle_r_lcl_reg), .I3(periodic_rd_ack_r_lcl_reg_0), .O(rd_wr_ns)); FDRE rd_wr_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rd_wr_ns), .Q(\rd_this_rank_r_reg[0] ), .R(1'b0)); FDRE \req_bank_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [0]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [0]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [1]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [1]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [2]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [2]), .R(1'b0)); LUT6 #( .INIT(64'h40FF404040404040)) req_bank_rdy_r_i_3 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[1]_0 [1]), .I2(bm_end_r1_reg), .I3(rd_wr_r_lcl_reg_0), .I4(\grant_r_reg[1]_0 [0]), .I5(req_wr_r), .O(req_bank_rdy_r_reg)); LUT6 #( .INIT(64'hB8BBBBBBB8B8B8B8)) \req_cmd_r[0]_i_1 (.I0(req_cmd_r[0]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r1_reg[0] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hB8888888B8B8B8B8)) \req_cmd_r[1]_i_1 (.I0(req_cmd_r[1]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r2_reg[1] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[1]_i_1_n_0 )); FDRE \req_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[0]_i_1_n_0 ), .Q(req_cmd_r[0]), .R(1'b0)); FDRE \req_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[1]_i_1_n_0 ), .Q(req_cmd_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [0]), .Q(\cmd_pipe_plus.mc_address_reg[24] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [1]), .Q(\cmd_pipe_plus.mc_address_reg[24] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [2]), .Q(\cmd_pipe_plus.mc_address_reg[24] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [3]), .Q(\cmd_pipe_plus.mc_address_reg[24] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [4]), .Q(\cmd_pipe_plus.mc_address_reg[24] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [5]), .Q(\cmd_pipe_plus.mc_address_reg[24] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [6]), .Q(\cmd_pipe_plus.mc_address_reg[24] [6]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[0] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [0]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[1] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [1]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[2] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [2]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [3]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [4]), .R(1'b0)); FDRE req_periodic_rd_r_lcl_reg (.C(CLK), .CE(E), .D(periodic_rd_insert), .Q(req_periodic_rd_r), .R(1'b0)); FDRE req_priority_r_reg (.C(CLK), .CE(E), .D(hi_priority), .Q(req_priority_r), .R(1'b0)); FDRE \req_row_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [0]), .Q(\cmd_pipe_plus.mc_address_reg[14] [0]), .R(1'b0)); FDRE \req_row_r_lcl_reg[10] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [10]), .Q(\cmd_pipe_plus.mc_address_reg[14] [10]), .R(1'b0)); FDRE \req_row_r_lcl_reg[11] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [11]), .Q(\cmd_pipe_plus.mc_address_reg[14] [11]), .R(1'b0)); FDRE \req_row_r_lcl_reg[12] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [12]), .Q(\cmd_pipe_plus.mc_address_reg[14] [12]), .R(1'b0)); FDRE \req_row_r_lcl_reg[13] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [13]), .Q(\cmd_pipe_plus.mc_address_reg[14] [13]), .R(1'b0)); FDRE \req_row_r_lcl_reg[14] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [14]), .Q(\cmd_pipe_plus.mc_address_reg[14] [14]), .R(1'b0)); FDRE \req_row_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [1]), .Q(\cmd_pipe_plus.mc_address_reg[14] [1]), .R(1'b0)); FDRE \req_row_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [2]), .Q(\cmd_pipe_plus.mc_address_reg[14] [2]), .R(1'b0)); FDRE \req_row_r_lcl_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [3]), .Q(\cmd_pipe_plus.mc_address_reg[14] [3]), .R(1'b0)); FDRE \req_row_r_lcl_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [4]), .Q(\cmd_pipe_plus.mc_address_reg[14] [4]), .R(1'b0)); FDRE \req_row_r_lcl_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [5]), .Q(\cmd_pipe_plus.mc_address_reg[14] [5]), .R(1'b0)); FDRE \req_row_r_lcl_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [6]), .Q(\cmd_pipe_plus.mc_address_reg[14] [6]), .R(1'b0)); FDRE \req_row_r_lcl_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [7]), .Q(\cmd_pipe_plus.mc_address_reg[14] [7]), .R(1'b0)); FDRE \req_row_r_lcl_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [8]), .Q(\cmd_pipe_plus.mc_address_reg[14] [8]), .R(1'b0)); FDRE \req_row_r_lcl_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [9]), .Q(\cmd_pipe_plus.mc_address_reg[14] [9]), .R(1'b0)); LUT6 #( .INIT(64'hCCCC0A0FFFFF0A0F)) req_wr_r_lcl_i_1 (.I0(\app_cmd_r2_reg[1] ), .I1(req_cmd_r[1]), .I2(periodic_rd_insert), .I3(\app_cmd_r1_reg[0] ), .I4(idle_r_lcl_reg), .I5(req_cmd_r[0]), .O(req_wr_r_lcl0)); FDRE req_wr_r_lcl_reg (.C(CLK), .CE(E), .D(req_wr_r_lcl0), .Q(bm_end_r1_reg), .R(1'b0)); CARRY4 row_hit_ns_carry (.CI(1'b0), .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]), .S({row_hit_ns_carry_i_1__0_n_0,row_hit_ns_carry_i_2__0_n_0,row_hit_ns_carry_i_3__0_n_0,row_hit_ns_carry_i_4__0_n_0})); CARRY4 row_hit_ns_carry__0 (.CI(row_hit_ns_carry_n_0), .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__0_n_0})); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry__0_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [14]), .I1(\app_addr_r1_reg[27] [14]), .I2(\cmd_pipe_plus.mc_address_reg[14] [13]), .I3(\app_addr_r1_reg[27] [13]), .I4(\app_addr_r1_reg[27] [12]), .I5(\cmd_pipe_plus.mc_address_reg[14] [12]), .O(row_hit_ns_carry__0_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [11]), .I1(\app_addr_r1_reg[27] [11]), .I2(\cmd_pipe_plus.mc_address_reg[14] [9]), .I3(\app_addr_r1_reg[27] [9]), .I4(\app_addr_r1_reg[27] [10]), .I5(\cmd_pipe_plus.mc_address_reg[14] [10]), .O(row_hit_ns_carry_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [8]), .I1(\app_addr_r1_reg[27] [8]), .I2(\cmd_pipe_plus.mc_address_reg[14] [7]), .I3(\app_addr_r1_reg[27] [7]), .I4(\app_addr_r1_reg[27] [6]), .I5(\cmd_pipe_plus.mc_address_reg[14] [6]), .O(row_hit_ns_carry_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_3__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [5]), .I1(\app_addr_r1_reg[27] [5]), .I2(\cmd_pipe_plus.mc_address_reg[14] [3]), .I3(\app_addr_r1_reg[27] [3]), .I4(\app_addr_r1_reg[27] [4]), .I5(\cmd_pipe_plus.mc_address_reg[14] [4]), .O(row_hit_ns_carry_i_3__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_4__0 (.I0(\cmd_pipe_plus.mc_address_reg[14] [2]), .I1(\app_addr_r1_reg[27] [2]), .I2(\cmd_pipe_plus.mc_address_reg[14] [1]), .I3(\app_addr_r1_reg[27] [1]), .I4(\app_addr_r1_reg[27] [0]), .I5(\cmd_pipe_plus.mc_address_reg[14] [0]), .O(row_hit_ns_carry_i_4__0_n_0)); FDRE row_hit_r_reg (.C(CLK), .CE(1'b1), .D(row_hit_ns), .Q(row_hit_r_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1065" *) LUT1 #( .INIT(2'h1)) \wr_this_rank_r[0]_i_1__0 (.I0(\rd_this_rank_r_reg[0] ), .O(start_wtp_timer0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_compare" *) module ddr3_if_mig_7series_v4_0_bank_compare_2 (req_periodic_rd_r, \rd_this_rank_r_reg[0] , bm_end_r1_reg, req_priority_r, q_has_priority_r_reg, row_hit_r, \grant_r_reg[2] , \ras_timer_r_reg[0] , \ras_timer_r_reg[0]_0 , pass_open_bank_ns, p_130_out, start_wtp_timer0, ras_timer_zero_r_reg, \cmd_pipe_plus.mc_address_reg[14] , head_r_lcl_reg, head_r_lcl_reg_0, \col_mux.col_data_buf_addr_r_reg[4] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_address_reg[24] , E, periodic_rd_insert, CLK, hi_priority, p_145_out, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , idle_r_lcl_reg, periodic_rd_ack_r_lcl_reg, periodic_rd_cntr_r_reg, periodic_rd_r, \grant_r_reg[0] , periodic_rd_ack_r_lcl_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] , pass_open_bank_r_lcl_reg, pre_passing_open_bank_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 , Q, req_wr_r_lcl_reg_0, tail_r, accept_r_reg, pre_wait_r, pre_bm_end_r, maint_req_r, \maint_controller.maint_wip_r_lcl_reg , wait_for_maint_r, \app_addr_r1_reg[27] , rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, rb_hit_busy_r_reg_2, idle_r_lcl_reg_0, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] ); output [0:0]req_periodic_rd_r; output \rd_this_rank_r_reg[0] ; output bm_end_r1_reg; output req_priority_r; output q_has_priority_r_reg; output row_hit_r; output \grant_r_reg[2] ; output \ras_timer_r_reg[0] ; output \ras_timer_r_reg[0]_0 ; output pass_open_bank_ns; output p_130_out; output start_wtp_timer0; output ras_timer_zero_r_reg; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output head_r_lcl_reg; output head_r_lcl_reg_0; output [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [6:0]\cmd_pipe_plus.mc_address_reg[24] ; input [0:0]E; input periodic_rd_insert; input CLK; input hi_priority; input p_145_out; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input idle_r_lcl_reg; input periodic_rd_ack_r_lcl_reg; input periodic_rd_cntr_r_reg; input periodic_rd_r; input [0:0]\grant_r_reg[0] ; input periodic_rd_ack_r_lcl_reg_0; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; input pass_open_bank_r_lcl_reg; input pre_passing_open_bank_r; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; input [0:0]Q; input req_wr_r_lcl_reg_0; input tail_r; input accept_r_reg; input pre_wait_r; input pre_bm_end_r; input maint_req_r; input \maint_controller.maint_wip_r_lcl_reg ; input wait_for_maint_r; input [14:0]\app_addr_r1_reg[27] ; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input rb_hit_busy_r_reg_2; input idle_r_lcl_reg_0; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; wire CLK; wire [0:0]E; wire [0:0]Q; wire accept_r_reg; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire bm_end_r1_reg; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire [6:0]\cmd_pipe_plus.mc_address_reg[24] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [4:0]\col_mux.col_data_buf_addr_r_reg[4] ; wire [0:0]\grant_r_reg[0] ; wire \grant_r_reg[2] ; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire hi_priority; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire \maint_controller.maint_wip_r_lcl_reg ; wire maint_req_r; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire p_130_out; wire p_145_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_i_2_n_0; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_cntr_r_reg; wire periodic_rd_insert; wire periodic_rd_r; wire pre_bm_end_r; wire pre_passing_open_bank_r; wire pre_wait_r; wire q_has_priority_r_reg; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire ras_timer_zero_r_reg; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire \rd_this_rank_r_reg[0] ; wire rd_wr_ns; wire [1:0]req_cmd_r; wire \req_cmd_r[0]_i_1__2_n_0 ; wire \req_cmd_r[1]_i_1__2_n_0 ; wire [0:0]req_periodic_rd_r; wire req_priority_r; wire req_wr_r_lcl0; wire req_wr_r_lcl_reg_0; wire row_hit_ns; wire row_hit_ns_carry__0_i_1_n_0; wire row_hit_ns_carry_i_1_n_0; wire row_hit_ns_carry_i_2_n_0; wire row_hit_ns_carry_i_3_n_0; wire row_hit_ns_carry_i_4_n_0; wire row_hit_ns_carry_n_0; wire row_hit_ns_carry_n_1; wire row_hit_ns_carry_n_2; wire row_hit_ns_carry_n_3; wire row_hit_r; wire start_wtp_timer0; wire tail_r; wire wait_for_maint_r; wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED; wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED; wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1050" *) LUT5 #( .INIT(32'hFFFF7000)) bm_end_r1_i_1__0 (.I0(bm_end_r1_reg), .I1(\rd_this_rank_r_reg[0] ), .I2(pass_open_bank_r_lcl_reg), .I3(\grant_r_reg[0] ), .I4(pre_bm_end_r), .O(p_130_out)); (* SOFT_HLUTNM = "soft_lutpair1052" *) LUT4 #( .INIT(16'h7EE8)) i___1_i_4 (.I0(q_has_priority_r_reg), .I1(rb_hit_busy_r_reg_0), .I2(rb_hit_busy_r_reg_1), .I3(rb_hit_busy_r_reg_2), .O(head_r_lcl_reg)); (* SOFT_HLUTNM = "soft_lutpair1052" *) LUT4 #( .INIT(16'h6996)) i___1_i_5 (.I0(q_has_priority_r_reg), .I1(rb_hit_busy_r_reg_2), .I2(rb_hit_busy_r_reg_1), .I3(rb_hit_busy_r_reg_0), .O(head_r_lcl_reg_0)); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___36_i_3 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[0] ), .I5(pre_passing_open_bank_r), .O(\grant_r_reg[2] )); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___38_i_1 (.I0(Q), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[0] ), .I5(pre_passing_open_bank_r), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'hAAAAAAAA2A000000)) i___56_i_3 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ), .I1(bm_end_r1_reg), .I2(\rd_this_rank_r_reg[0] ), .I3(pass_open_bank_r_lcl_reg), .I4(\grant_r_reg[0] ), .I5(pre_passing_open_bank_r), .O(\ras_timer_r_reg[0] )); LUT6 #( .INIT(64'h4444544444444444)) pass_open_bank_r_lcl_i_1__0 (.I0(req_wr_r_lcl_reg_0), .I1(pass_open_bank_r_lcl_reg), .I2(tail_r), .I3(accept_r_reg), .I4(pre_wait_r), .I5(pass_open_bank_r_lcl_i_2_n_0), .O(pass_open_bank_ns)); LUT5 #( .INIT(32'hAAAA00A2)) pass_open_bank_r_lcl_i_2 (.I0(row_hit_r), .I1(maint_req_r), .I2(periodic_rd_cntr_r_reg), .I3(\maint_controller.maint_wip_r_lcl_reg ), .I4(wait_for_maint_r), .O(pass_open_bank_r_lcl_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1050" *) LUT2 #( .INIT(4'hB)) ras_timer_zero_r_i_2__1 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[0] ), .O(ras_timer_zero_r_reg)); FDRE rb_hit_busy_r_reg (.C(CLK), .CE(1'b1), .D(p_145_out), .Q(q_has_priority_r_reg), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1051" *) LUT4 #( .INIT(16'h2F20)) rd_wr_r_lcl_i_1__2 (.I0(\rd_this_rank_r_reg[0] ), .I1(\grant_r_reg[0] ), .I2(idle_r_lcl_reg), .I3(periodic_rd_ack_r_lcl_reg_0), .O(rd_wr_ns)); FDRE rd_wr_r_lcl_reg (.C(CLK), .CE(1'b1), .D(rd_wr_ns), .Q(\rd_this_rank_r_reg[0] ), .R(1'b0)); FDRE \req_bank_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [0]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [0]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [1]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [1]), .R(1'b0)); FDRE \req_bank_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[12] [2]), .Q(\cmd_pipe_plus.mc_bank_reg[2] [2]), .R(1'b0)); LUT6 #( .INIT(64'hB8BBBBBBB8B8B8B8)) \req_cmd_r[0]_i_1__2 (.I0(req_cmd_r[0]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r1_reg[0] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'hB8888888B8B8B8B8)) \req_cmd_r[1]_i_1__2 (.I0(req_cmd_r[1]), .I1(idle_r_lcl_reg), .I2(\app_cmd_r2_reg[1] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(periodic_rd_cntr_r_reg), .I5(periodic_rd_r), .O(\req_cmd_r[1]_i_1__2_n_0 )); FDRE \req_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[0]_i_1__2_n_0 ), .Q(req_cmd_r[0]), .R(1'b0)); FDRE \req_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(\req_cmd_r[1]_i_1__2_n_0 ), .Q(req_cmd_r[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [0]), .Q(\cmd_pipe_plus.mc_address_reg[24] [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [1]), .Q(\cmd_pipe_plus.mc_address_reg[24] [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [2]), .Q(\cmd_pipe_plus.mc_address_reg[24] [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [3]), .Q(\cmd_pipe_plus.mc_address_reg[24] [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [4]), .Q(\cmd_pipe_plus.mc_address_reg[24] [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [5]), .Q(\cmd_pipe_plus.mc_address_reg[24] [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \req_col_r_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[9] [6]), .Q(\cmd_pipe_plus.mc_address_reg[24] [6]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[0] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [0]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[1] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [1]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[2] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [2]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[3] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [3]), .R(1'b0)); FDRE \req_data_buf_addr_r_reg[4] (.C(CLK), .CE(idle_r_lcl_reg_0), .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .Q(\col_mux.col_data_buf_addr_r_reg[4] [4]), .R(1'b0)); FDRE req_periodic_rd_r_lcl_reg (.C(CLK), .CE(E), .D(periodic_rd_insert), .Q(req_periodic_rd_r), .R(1'b0)); FDRE req_priority_r_reg (.C(CLK), .CE(E), .D(hi_priority), .Q(req_priority_r), .R(1'b0)); FDRE \req_row_r_lcl_reg[0] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [0]), .Q(\cmd_pipe_plus.mc_address_reg[14] [0]), .R(1'b0)); FDRE \req_row_r_lcl_reg[10] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [10]), .Q(\cmd_pipe_plus.mc_address_reg[14] [10]), .R(1'b0)); FDRE \req_row_r_lcl_reg[11] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [11]), .Q(\cmd_pipe_plus.mc_address_reg[14] [11]), .R(1'b0)); FDRE \req_row_r_lcl_reg[12] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [12]), .Q(\cmd_pipe_plus.mc_address_reg[14] [12]), .R(1'b0)); FDRE \req_row_r_lcl_reg[13] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [13]), .Q(\cmd_pipe_plus.mc_address_reg[14] [13]), .R(1'b0)); FDRE \req_row_r_lcl_reg[14] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [14]), .Q(\cmd_pipe_plus.mc_address_reg[14] [14]), .R(1'b0)); FDRE \req_row_r_lcl_reg[1] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [1]), .Q(\cmd_pipe_plus.mc_address_reg[14] [1]), .R(1'b0)); FDRE \req_row_r_lcl_reg[2] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [2]), .Q(\cmd_pipe_plus.mc_address_reg[14] [2]), .R(1'b0)); FDRE \req_row_r_lcl_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [3]), .Q(\cmd_pipe_plus.mc_address_reg[14] [3]), .R(1'b0)); FDRE \req_row_r_lcl_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [4]), .Q(\cmd_pipe_plus.mc_address_reg[14] [4]), .R(1'b0)); FDRE \req_row_r_lcl_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [5]), .Q(\cmd_pipe_plus.mc_address_reg[14] [5]), .R(1'b0)); FDRE \req_row_r_lcl_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [6]), .Q(\cmd_pipe_plus.mc_address_reg[14] [6]), .R(1'b0)); FDRE \req_row_r_lcl_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [7]), .Q(\cmd_pipe_plus.mc_address_reg[14] [7]), .R(1'b0)); FDRE \req_row_r_lcl_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [8]), .Q(\cmd_pipe_plus.mc_address_reg[14] [8]), .R(1'b0)); FDRE \req_row_r_lcl_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg[27] [9]), .Q(\cmd_pipe_plus.mc_address_reg[14] [9]), .R(1'b0)); LUT6 #( .INIT(64'hCCCC0A0FFFFF0A0F)) req_wr_r_lcl_i_1__2 (.I0(\app_cmd_r2_reg[1] ), .I1(req_cmd_r[1]), .I2(periodic_rd_insert), .I3(\app_cmd_r1_reg[0] ), .I4(idle_r_lcl_reg), .I5(req_cmd_r[0]), .O(req_wr_r_lcl0)); FDRE req_wr_r_lcl_reg (.C(CLK), .CE(E), .D(req_wr_r_lcl0), .Q(bm_end_r1_reg), .R(1'b0)); CARRY4 row_hit_ns_carry (.CI(1'b0), .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]), .S({row_hit_ns_carry_i_1_n_0,row_hit_ns_carry_i_2_n_0,row_hit_ns_carry_i_3_n_0,row_hit_ns_carry_i_4_n_0})); CARRY4 row_hit_ns_carry__0 (.CI(row_hit_ns_carry_n_0), .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1_n_0})); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry__0_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[14] [14]), .I1(\app_addr_r1_reg[27] [14]), .I2(\cmd_pipe_plus.mc_address_reg[14] [12]), .I3(\app_addr_r1_reg[27] [12]), .I4(\app_addr_r1_reg[27] [13]), .I5(\cmd_pipe_plus.mc_address_reg[14] [13]), .O(row_hit_ns_carry__0_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[14] [11]), .I1(\app_addr_r1_reg[27] [11]), .I2(\cmd_pipe_plus.mc_address_reg[14] [10]), .I3(\app_addr_r1_reg[27] [10]), .I4(\app_addr_r1_reg[27] [9]), .I5(\cmd_pipe_plus.mc_address_reg[14] [9]), .O(row_hit_ns_carry_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[14] [8]), .I1(\app_addr_r1_reg[27] [8]), .I2(\cmd_pipe_plus.mc_address_reg[14] [7]), .I3(\app_addr_r1_reg[27] [7]), .I4(\app_addr_r1_reg[27] [6]), .I5(\cmd_pipe_plus.mc_address_reg[14] [6]), .O(row_hit_ns_carry_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_3 (.I0(\cmd_pipe_plus.mc_address_reg[14] [5]), .I1(\app_addr_r1_reg[27] [5]), .I2(\cmd_pipe_plus.mc_address_reg[14] [4]), .I3(\app_addr_r1_reg[27] [4]), .I4(\app_addr_r1_reg[27] [3]), .I5(\cmd_pipe_plus.mc_address_reg[14] [3]), .O(row_hit_ns_carry_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) row_hit_ns_carry_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[14] [2]), .I1(\app_addr_r1_reg[27] [2]), .I2(\cmd_pipe_plus.mc_address_reg[14] [1]), .I3(\app_addr_r1_reg[27] [1]), .I4(\app_addr_r1_reg[27] [0]), .I5(\cmd_pipe_plus.mc_address_reg[14] [0]), .O(row_hit_ns_carry_i_4_n_0)); FDRE row_hit_r_reg (.C(CLK), .CE(1'b1), .D(row_hit_ns), .Q(row_hit_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1051" *) LUT1 #( .INIT(2'h1)) \wr_this_rank_r[0]_i_1 (.I0(\rd_this_rank_r_reg[0] ), .O(start_wtp_timer0)); endmodule module ddr3_if_mig_7series_v4_0_bank_mach (accept_internal_r, periodic_rd_ack_r, \q_entry_r_reg[1] , accept_ns, was_wr, insert_maint_r, sent_row, \cmd_pipe_plus.mc_cmd_reg[0] , insert_maint_r1, cs_en2, DIC, col_rd_wr, col_data_buf_addr, cke_r, idle_r, rd_wr_r, req_wr_r, rb_hit_busy_r, row_hit_r, bm_end_r1, \act_this_rank_r_reg[0] , ras_timer_zero_r, demand_priority_r, demanded_prior_r, act_wait_r_lcl_reg, pre_bm_end_r, q_has_rd, q_has_priority, row_hit_r_0, bm_end_r1_0, demand_priority_r_1, act_wait_r_lcl_reg_0, pre_bm_end_r_2, q_has_rd_3, q_has_priority_4, row_hit_r_5, \ras_timer_r_reg[2] , ras_timer_zero_r_6, demand_priority_r_7, demanded_prior_r_8, override_demand_r, act_wait_r_lcl_reg_1, pre_bm_end_r_9, q_has_rd_10, q_has_priority_11, row_hit_r_12, bm_end_r1_4, demand_priority_r_13, demanded_prior_r_14, act_wait_r_lcl_reg_2, pre_bm_end_r_15, q_has_rd_16, q_has_priority_17, maint_wip_r, wait_for_maint_r, wait_for_maint_r_18, wait_for_maint_r_19, wait_for_maint_r_20, rnk_config_valid_r, col_wait_r, col_wait_r_21, col_wait_r_22, col_wait_r_23, periodic_rd_cntr_r, tail_r, head_r, auto_pre_r, ordered_r, tail_r_24, auto_pre_r_25, tail_r_26, auto_pre_r_27, tail_r_28, auto_pre_r_29, \cmd_pipe_plus.mc_data_offset_1_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \rtw_timer.rtw_cnt_r_reg[1] , Q, rb_hit_busy_r_reg, accept_internal_r_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] , \q_entry_r_reg[0] , rb_hit_busy_r_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] , rb_hit_busy_r_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 , \q_entry_r_reg[1]_0 , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , \q_entry_r_reg[1]_1 , \q_entry_r_reg[0]_0 , clear_periodic_rd_request, \periodic_rd_generation.periodic_rd_timer_r_reg[2] , read_this_rank, E, \rnk_config_strobe_r_reg[0] , rnk_config_valid_r_lcl_reg, \last_master_r_reg[3] , \ras_timer_r_reg[0] , \ras_timer_r_reg[0]_0 , \ras_timer_r_reg[0]_1 , \ras_timer_r_reg[0]_2 , \ras_timer_r_reg[0]_3 , \ras_timer_r_reg[0]_4 , ordered_r_lcl_reg, q_entry_r, head_r_lcl_reg, \q_entry_r_reg[1]_2 , \q_entry_r_reg[1]_3 , ordered_r_lcl_reg_0, q_entry_r_30, \maint_controller.maint_rdy_r1_reg , rtp_timer_r, head_r_lcl_reg_0, \q_entry_r_reg[1]_4 , \q_entry_r_reg[1]_5 , ordered_r_lcl_reg_1, head_r_lcl_reg_1, head_r_lcl_reg_2, \q_entry_r_reg[1]_6 , \q_entry_r_reg[0]_1 , head_r_lcl_reg_3, head_r_lcl_reg_4, \grant_r_reg[2] , \ras_timer_r_reg[0]_5 , \ras_timer_r_reg[0]_6 , \compute_tail.tail_r_lcl_reg , \grant_r_reg[1] , pass_open_bank_r_lcl_reg, \grant_r_reg[1]_0 , \grant_r_reg[3] , pass_open_bank_r_lcl_reg_0, mc_we_n_ns, mc_cas_n_ns, mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_bank_reg[2]_0 , \cmd_pipe_plus.mc_bank_reg[8]_0 , \cmd_pipe_plus.mc_bank_reg[8]_1 , \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_address_reg[10] , mc_cs_n_ns, \last_master_r_reg[3]_0 , \grant_r_reg[3]_0 , \cmd_pipe_plus.mc_bank_reg[7] , \last_master_r_reg[3]_1 , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, head_r_lcl_reg_5, auto_pre_r_lcl_reg_1, auto_pre_r_lcl_reg_2, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] , \grant_r_reg[1]_1 , demanded_prior_r_reg, act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , \wtr_timer.wtr_cnt_r_reg[0] , \wtr_timer.wtr_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1]_0 , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , demanded_prior_r_reg_0, \cmd_pipe_plus.mc_we_n_reg[1] , \maint_controller.maint_hit_busies_r_reg[3] , CLK, maint_srx_r, rstdiv0_sync_r1_reg_rep__0, mc_cke_ns, hi_priority, SR, q_has_rd_r_reg, q_has_priority_r_reg, q_has_rd_r_reg_0, q_has_priority_r_reg_0, q_has_rd_r_reg_1, q_has_priority_r_reg_1, q_has_rd_r_reg_2, q_has_priority_r_reg_2, of_ctl_full_v, phy_mc_ctl_full, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg, wait_for_maint_r_lcl_reg_0, wait_for_maint_r_lcl_reg_1, wait_for_maint_r_lcl_reg_2, rnk_config_valid_r_lcl_reg_0, \periodic_read_request.periodic_rd_r_lcl_reg , idle_r_lcl_reg, head_r_lcl_reg_6, auto_pre_r_lcl_reg_3, ordered_r_lcl_reg_2, idle_r_lcl_reg_0, head_r_lcl_reg_7, auto_pre_r_lcl_reg_4, ordered_r_lcl_reg_3, idle_r_lcl_reg_1, head_r_lcl_reg_8, auto_pre_r_lcl_reg_5, ordered_r_lcl_reg_4, idle_r_lcl_reg_2, head_r_lcl_reg_9, auto_pre_r_lcl_reg_6, ordered_r_lcl_reg_5, rd_wr_r_lcl_reg, \req_bank_r_lcl_reg[2] , rstdiv0_sync_r1_reg_rep__20, \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[0]_0 , \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , periodic_rd_grant_r, read_this_rank_r, rstdiv0_sync_r1_reg_rep__21, \wtr_timer.wtr_cnt_r_reg[1]_1 , col_wait_r_reg, col_wait_r_reg_0, override_demand_r_reg, override_demand_r_reg_0, col_wait_r_reg_1, col_wait_r_reg_2, override_demand_r_reg_1, \rtw_timer.rtw_cnt_r_reg[1]_0 , bm_end_r1_reg, bm_end_r1_reg_0, idle_r_lcl_reg_3, bm_end_r1_reg_1, idle_r_lcl_reg_4, D, pass_open_bank_r_lcl_reg_1, req_wr_r_lcl_reg, accept_r_reg, \app_cmd_r2_reg[1] , \app_cmd_r1_reg[0] , periodic_rd_r, periodic_rd_ack_r_lcl_reg, init_calib_complete_reg_rep__6, use_addr, bm_end_r1_reg_2, req_wr_r_lcl_reg_0, req_wr_r_lcl_reg_1, req_wr_r_lcl_reg_2, rtp_timer_ns1, accept_r_reg_0, rtp_timer_ns1_6, rtp_timer_ns1_7, maint_zq_r, granted_row_r_reg, granted_row_r_reg_0, ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, \last_master_r_reg[3]_2 , inhbt_act_faw_r, \last_master_r_reg[3]_3 , rstdiv0_sync_r1_reg_rep__22, maint_req_r, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] , \generate_maint_cmds.insert_maint_r_lcl_reg , \maintenance_request.maint_zq_r_lcl_reg , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] , \app_addr_r1_reg[27] , \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , act_wait_r_lcl_reg_3, \req_bank_r_lcl_reg[2]_1 , \grant_r_reg[0] , \grant_r_reg[0]_0 , \grant_r_reg[0]_1 , \grant_r_reg[0]_2 , \grant_r_reg[0]_3 , \grant_r_reg[0]_4 , \grant_r_reg[0]_5 , \grant_r_reg[0]_6 , \grant_r_reg[0]_7 , \grant_r_reg[0]_8 , \grant_r_reg[0]_9 , \grant_r_reg[0]_10 , \grant_r_reg[0]_11 , \grant_r_reg[0]_12 , \req_bank_r_lcl_reg[0]_1 , \req_bank_r_lcl_reg[1] , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , rb_hit_busy_r_reg_2, pass_open_bank_r_lcl_reg_2, idle_r_lcl_reg_5, idle_r_lcl_reg_6, idle_r_lcl_reg_7); output accept_internal_r; output periodic_rd_ack_r; output \q_entry_r_reg[1] ; output accept_ns; output was_wr; output insert_maint_r; output sent_row; output \cmd_pipe_plus.mc_cmd_reg[0] ; output insert_maint_r1; output cs_en2; output [0:0]DIC; output col_rd_wr; output [4:0]col_data_buf_addr; output cke_r; output [3:0]idle_r; output [3:0]rd_wr_r; output [3:0]req_wr_r; output [3:0]rb_hit_busy_r; output row_hit_r; output bm_end_r1; output [2:0]\act_this_rank_r_reg[0] ; output ras_timer_zero_r; output demand_priority_r; output demanded_prior_r; output act_wait_r_lcl_reg; output pre_bm_end_r; output q_has_rd; output q_has_priority; output row_hit_r_0; output bm_end_r1_0; output demand_priority_r_1; output act_wait_r_lcl_reg_0; output pre_bm_end_r_2; output q_has_rd_3; output q_has_priority_4; output row_hit_r_5; output \ras_timer_r_reg[2] ; output ras_timer_zero_r_6; output demand_priority_r_7; output demanded_prior_r_8; output override_demand_r; output act_wait_r_lcl_reg_1; output pre_bm_end_r_9; output q_has_rd_10; output q_has_priority_11; output row_hit_r_12; output bm_end_r1_4; output demand_priority_r_13; output demanded_prior_r_14; output act_wait_r_lcl_reg_2; output pre_bm_end_r_15; output q_has_rd_16; output q_has_priority_17; output maint_wip_r; output wait_for_maint_r; output wait_for_maint_r_18; output wait_for_maint_r_19; output wait_for_maint_r_20; output rnk_config_valid_r; output col_wait_r; output col_wait_r_21; output col_wait_r_22; output col_wait_r_23; output periodic_rd_cntr_r; output tail_r; output [3:0]head_r; output auto_pre_r; output [3:0]ordered_r; output tail_r_24; output auto_pre_r_25; output tail_r_26; output auto_pre_r_27; output tail_r_28; output auto_pre_r_29; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; output \rtw_timer.rtw_cnt_r_reg[1] ; output [3:0]Q; output rb_hit_busy_r_reg; output accept_internal_r_reg; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ; output \q_entry_r_reg[0] ; output rb_hit_busy_r_reg_0; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; output rb_hit_busy_r_reg_1; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; output \q_entry_r_reg[1]_0 ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[0]_0 ; output clear_periodic_rd_request; output \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; output read_this_rank; output [0:0]E; output \rnk_config_strobe_r_reg[0] ; output rnk_config_valid_r_lcl_reg; output [2:0]\last_master_r_reg[3] ; output \ras_timer_r_reg[0] ; output \ras_timer_r_reg[0]_0 ; output \ras_timer_r_reg[0]_1 ; output \ras_timer_r_reg[0]_2 ; output \ras_timer_r_reg[0]_3 ; output \ras_timer_r_reg[0]_4 ; output ordered_r_lcl_reg; output [1:0]q_entry_r; output head_r_lcl_reg; output \q_entry_r_reg[1]_2 ; output \q_entry_r_reg[1]_3 ; output ordered_r_lcl_reg_0; output [1:0]q_entry_r_30; output \maint_controller.maint_rdy_r1_reg ; output [1:0]rtp_timer_r; output head_r_lcl_reg_0; output \q_entry_r_reg[1]_4 ; output \q_entry_r_reg[1]_5 ; output ordered_r_lcl_reg_1; output head_r_lcl_reg_1; output head_r_lcl_reg_2; output \q_entry_r_reg[1]_6 ; output \q_entry_r_reg[0]_1 ; output head_r_lcl_reg_3; output head_r_lcl_reg_4; output \grant_r_reg[2] ; output \ras_timer_r_reg[0]_5 ; output \ras_timer_r_reg[0]_6 ; output \compute_tail.tail_r_lcl_reg ; output \grant_r_reg[1] ; output pass_open_bank_r_lcl_reg; output \grant_r_reg[1]_0 ; output \grant_r_reg[3] ; output pass_open_bank_r_lcl_reg_0; output [1:0]mc_we_n_ns; output [1:0]mc_cas_n_ns; output [1:0]mc_ras_n_ns; output [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ; output [37:0]\cmd_pipe_plus.mc_address_reg[44] ; output [28:0]\cmd_pipe_plus.mc_address_reg[10] ; output [0:0]mc_cs_n_ns; output [0:0]\last_master_r_reg[3]_0 ; output \grant_r_reg[3]_0 ; output [3:0]\cmd_pipe_plus.mc_bank_reg[7] ; output [0:0]\last_master_r_reg[3]_1 ; output auto_pre_r_lcl_reg; output auto_pre_r_lcl_reg_0; output head_r_lcl_reg_5; output auto_pre_r_lcl_reg_1; output auto_pre_r_lcl_reg_2; output [4:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ; output \grant_r_reg[1]_1 ; output demanded_prior_r_reg; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; output \wtr_timer.wtr_cnt_r_reg[0] ; output \wtr_timer.wtr_cnt_r_reg[1] ; output \wtr_timer.wtr_cnt_r_reg[1]_0 ; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output demanded_prior_r_reg_0; output \cmd_pipe_plus.mc_we_n_reg[1] ; output [3:0]\maint_controller.maint_hit_busies_r_reg[3] ; input CLK; input maint_srx_r; input rstdiv0_sync_r1_reg_rep__0; input [0:0]mc_cke_ns; input hi_priority; input [0:0]SR; input q_has_rd_r_reg; input q_has_priority_r_reg; input q_has_rd_r_reg_0; input q_has_priority_r_reg_0; input q_has_rd_r_reg_1; input q_has_priority_r_reg_1; input q_has_rd_r_reg_2; input q_has_priority_r_reg_2; input [0:0]of_ctl_full_v; input phy_mc_ctl_full; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg; input wait_for_maint_r_lcl_reg_0; input wait_for_maint_r_lcl_reg_1; input wait_for_maint_r_lcl_reg_2; input rnk_config_valid_r_lcl_reg_0; input \periodic_read_request.periodic_rd_r_lcl_reg ; input idle_r_lcl_reg; input head_r_lcl_reg_6; input auto_pre_r_lcl_reg_3; input ordered_r_lcl_reg_2; input idle_r_lcl_reg_0; input head_r_lcl_reg_7; input auto_pre_r_lcl_reg_4; input ordered_r_lcl_reg_3; input idle_r_lcl_reg_1; input head_r_lcl_reg_8; input auto_pre_r_lcl_reg_5; input ordered_r_lcl_reg_4; input idle_r_lcl_reg_2; input head_r_lcl_reg_9; input auto_pre_r_lcl_reg_6; input ordered_r_lcl_reg_5; input rd_wr_r_lcl_reg; input \req_bank_r_lcl_reg[2] ; input rstdiv0_sync_r1_reg_rep__20; input \req_bank_r_lcl_reg[2]_0 ; input \req_bank_r_lcl_reg[0] ; input \req_bank_r_lcl_reg[0]_0 ; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input periodic_rd_grant_r; input read_this_rank_r; input rstdiv0_sync_r1_reg_rep__21; input \wtr_timer.wtr_cnt_r_reg[1]_1 ; input col_wait_r_reg; input col_wait_r_reg_0; input override_demand_r_reg; input override_demand_r_reg_0; input col_wait_r_reg_1; input col_wait_r_reg_2; input override_demand_r_reg_1; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input bm_end_r1_reg; input bm_end_r1_reg_0; input idle_r_lcl_reg_3; input bm_end_r1_reg_1; input idle_r_lcl_reg_4; input [3:0]D; input pass_open_bank_r_lcl_reg_1; input req_wr_r_lcl_reg; input accept_r_reg; input [0:0]\app_cmd_r2_reg[1] ; input \app_cmd_r1_reg[0] ; input periodic_rd_r; input periodic_rd_ack_r_lcl_reg; input init_calib_complete_reg_rep__6; input use_addr; input bm_end_r1_reg_2; input req_wr_r_lcl_reg_0; input req_wr_r_lcl_reg_1; input req_wr_r_lcl_reg_2; input rtp_timer_ns1; input accept_r_reg_0; input rtp_timer_ns1_6; input rtp_timer_ns1_7; input maint_zq_r; input granted_row_r_reg; input granted_row_r_reg_0; input ras_timer_zero_r_reg; input ras_timer_zero_r_reg_0; input \last_master_r_reg[3]_2 ; input inhbt_act_faw_r; input \last_master_r_reg[3]_3 ; input rstdiv0_sync_r1_reg_rep__22; input maint_req_r; input [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input \maintenance_request.maint_zq_r_lcl_reg ; input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ; input [14:0]\app_addr_r1_reg[27] ; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input act_wait_r_lcl_reg_3; input \req_bank_r_lcl_reg[2]_1 ; input \grant_r_reg[0] ; input \grant_r_reg[0]_0 ; input \grant_r_reg[0]_1 ; input \grant_r_reg[0]_2 ; input \grant_r_reg[0]_3 ; input \grant_r_reg[0]_4 ; input \grant_r_reg[0]_5 ; input \grant_r_reg[0]_6 ; input \grant_r_reg[0]_7 ; input \grant_r_reg[0]_8 ; input \grant_r_reg[0]_9 ; input \grant_r_reg[0]_10 ; input \grant_r_reg[0]_11 ; input \grant_r_reg[0]_12 ; input \req_bank_r_lcl_reg[0]_1 ; input \req_bank_r_lcl_reg[1] ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input rb_hit_busy_r_reg_2; input pass_open_bank_r_lcl_reg_2; input idle_r_lcl_reg_5; input idle_r_lcl_reg_6; input idle_r_lcl_reg_7; wire CLK; wire [3:0]D; wire [0:0]DIC; wire [0:0]E; wire [3:0]Q; wire [0:0]SR; wire accept_internal_r; wire accept_internal_r_reg; wire accept_ns; wire accept_r_reg; wire accept_r_reg_0; wire act_this_rank; wire [3:0]act_this_rank_r; wire [2:0]\act_this_rank_r_reg[0] ; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire act_wait_r_lcl_reg_2; wire act_wait_r_lcl_reg_3; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire arb_mux0_n_106; wire arb_mux0_n_22; wire arb_mux0_n_46; wire arb_mux0_n_85; wire arb_mux0_n_86; wire arb_mux0_n_88; wire arb_mux0_n_89; wire arb_mux0_n_96; wire arb_mux0_n_97; wire arb_mux0_n_98; wire arb_mux0_n_99; wire \arb_row_col0/granted_col_ns ; wire auto_pre_r; wire auto_pre_r_25; wire auto_pre_r_27; wire auto_pre_r_29; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire auto_pre_r_lcl_reg_3; wire auto_pre_r_lcl_reg_4; wire auto_pre_r_lcl_reg_5; wire auto_pre_r_lcl_reg_6; wire \bank_cntrl[0].bank0_n_32 ; wire \bank_cntrl[0].bank0_n_33 ; wire \bank_cntrl[0].bank0_n_34 ; wire \bank_cntrl[0].bank0_n_38 ; wire \bank_cntrl[0].bank0_n_39 ; wire \bank_cntrl[0].bank0_n_41 ; wire \bank_cntrl[0].bank0_n_43 ; wire \bank_cntrl[0].bank0_n_44 ; wire \bank_cntrl[0].bank0_n_45 ; wire \bank_cntrl[0].bank0_n_48 ; wire \bank_cntrl[0].bank0_n_49 ; wire \bank_cntrl[0].bank0_n_55 ; wire \bank_cntrl[0].bank0_n_56 ; wire \bank_cntrl[0].bank0_n_74 ; wire \bank_cntrl[1].bank0_n_30 ; wire \bank_cntrl[1].bank0_n_31 ; wire \bank_cntrl[1].bank0_n_35 ; wire \bank_cntrl[1].bank0_n_36 ; wire \bank_cntrl[1].bank0_n_37 ; wire \bank_cntrl[1].bank0_n_41 ; wire \bank_cntrl[1].bank0_n_43 ; wire \bank_cntrl[1].bank0_n_46 ; wire \bank_cntrl[1].bank0_n_49 ; wire \bank_cntrl[1].bank0_n_51 ; wire \bank_cntrl[1].bank0_n_52 ; wire \bank_cntrl[1].bank0_n_53 ; wire \bank_cntrl[1].bank0_n_69 ; wire \bank_cntrl[1].bank0_n_70 ; wire \bank_cntrl[1].bank0_n_71 ; wire \bank_cntrl[2].bank0_n_35 ; wire \bank_cntrl[2].bank0_n_36 ; wire \bank_cntrl[2].bank0_n_37 ; wire \bank_cntrl[2].bank0_n_38 ; wire \bank_cntrl[2].bank0_n_39 ; wire \bank_cntrl[2].bank0_n_40 ; wire \bank_cntrl[2].bank0_n_41 ; wire \bank_cntrl[2].bank0_n_45 ; wire \bank_cntrl[2].bank0_n_54 ; wire \bank_cntrl[2].bank0_n_56 ; wire \bank_cntrl[2].bank0_n_58 ; wire \bank_cntrl[2].bank0_n_74 ; wire \bank_cntrl[3].bank0_n_31 ; wire \bank_cntrl[3].bank0_n_32 ; wire \bank_cntrl[3].bank0_n_33 ; wire \bank_cntrl[3].bank0_n_37 ; wire \bank_cntrl[3].bank0_n_38 ; wire \bank_cntrl[3].bank0_n_39 ; wire \bank_cntrl[3].bank0_n_48 ; wire \bank_cntrl[3].bank0_n_49 ; wire \bank_cntrl[3].bank0_n_65 ; wire \bank_cntrl[3].bank0_n_66 ; wire \bank_cntrl[3].bank0_n_67 ; wire \bank_cntrl[3].bank0_n_69 ; wire bank_common0_n_10; wire bank_common0_n_12; wire bank_common0_n_14; wire bank_common0_n_16; wire bank_common0_n_19; wire [9:3]\bank_compare0/req_col_r ; wire [9:3]\bank_compare0/req_col_r_13 ; wire [9:3]\bank_compare0/req_col_r_2 ; wire [9:3]\bank_compare0/req_col_r_7 ; wire [1:1]\bank_queue0/q_entry_ns ; wire [4:2]\bank_queue0/rb_hit_busies_ns ; wire [5:3]\bank_queue0/rb_hit_busies_ns_0 ; wire [6:4]\bank_queue0/rb_hit_busies_ns_1 ; wire [3:1]\bank_queue0/rb_hit_busies_ns_4 ; wire \bank_state0/demanded_prior_r ; wire \bank_state0/ofs_rdy_r ; wire \bank_state0/ofs_rdy_r0 ; wire \bank_state0/ofs_rdy_r0_10 ; wire \bank_state0/ofs_rdy_r0_9 ; wire \bank_state0/ofs_rdy_r_11 ; wire \bank_state0/ofs_rdy_r_15 ; wire \bank_state0/ofs_rdy_r_5 ; wire \bank_state0/override_demand_ns ; wire \bank_state0/req_bank_rdy_ns ; wire \bank_state0/req_bank_rdy_ns_12 ; wire \bank_state0/req_bank_rdy_ns_16 ; wire \bank_state0/req_bank_rdy_ns_6 ; wire \bank_state0/req_bank_rdy_r ; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_4; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire cke_r; wire clear_periodic_rd_request; wire [28:0]\cmd_pipe_plus.mc_address_reg[10] ; wire [37:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; wire [3:0]\cmd_pipe_plus.mc_bank_reg[7] ; wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ; wire \cmd_pipe_plus.mc_cmd_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_we_n_reg[1] ; wire [4:0]col_data_buf_addr; wire col_rd_wr; wire col_wait_r; wire col_wait_r_21; wire col_wait_r_22; wire col_wait_r_23; wire col_wait_r_reg; wire col_wait_r_reg_0; wire col_wait_r_reg_1; wire col_wait_r_reg_2; wire \compute_tail.tail_r_lcl_reg ; wire cs_en2; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r; wire demand_priority_r_1; wire demand_priority_r_13; wire demand_priority_r_7; wire demanded_prior_r; wire demanded_prior_r_14; wire demanded_prior_r_8; wire demanded_prior_r_reg; wire demanded_prior_r_reg_0; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[0]_1 ; wire \grant_r_reg[0]_10 ; wire \grant_r_reg[0]_11 ; wire \grant_r_reg[0]_12 ; wire \grant_r_reg[0]_2 ; wire \grant_r_reg[0]_3 ; wire \grant_r_reg[0]_4 ; wire \grant_r_reg[0]_5 ; wire \grant_r_reg[0]_6 ; wire \grant_r_reg[0]_7 ; wire \grant_r_reg[0]_8 ; wire \grant_r_reg[0]_9 ; wire \grant_r_reg[1] ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[1]_1 ; wire \grant_r_reg[2] ; wire \grant_r_reg[3] ; wire \grant_r_reg[3]_0 ; wire granted_pre_ns; wire granted_row_ns; wire granted_row_r_reg; wire granted_row_r_reg_0; wire [3:0]head_r; wire head_r_lcl_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire head_r_lcl_reg_3; wire head_r_lcl_reg_4; wire head_r_lcl_reg_5; wire head_r_lcl_reg_6; wire head_r_lcl_reg_7; wire head_r_lcl_reg_8; wire head_r_lcl_reg_9; wire hi_priority; wire [3:0]idle_r; wire idle_r_lcl_reg; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire idle_r_lcl_reg_4; wire idle_r_lcl_reg_5; wire idle_r_lcl_reg_6; wire idle_r_lcl_reg_7; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire insert_maint_r; wire insert_maint_r1; wire [2:0]\last_master_r_reg[3] ; wire [0:0]\last_master_r_reg[3]_0 ; wire [0:0]\last_master_r_reg[3]_1 ; wire \last_master_r_reg[3]_2 ; wire \last_master_r_reg[3]_3 ; wire [3:0]\maint_controller.maint_hit_busies_r_reg[3] ; wire \maint_controller.maint_rdy_r1_reg ; wire maint_req_r; wire maint_srx_r; wire maint_wip_r; wire maint_zq_r; wire \maintenance_request.maint_req_r_lcl_reg ; wire \maintenance_request.maint_zq_r_lcl_reg ; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cke_ns; wire [0:0]mc_cs_n_ns; wire [1:0]mc_ras_n_ns; wire [1:0]mc_we_n_ns; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [0:0]of_ctl_full_v; wire [3:0]ordered_r; wire ordered_r_lcl_reg; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire ordered_r_lcl_reg_2; wire ordered_r_lcl_reg_3; wire ordered_r_lcl_reg_4; wire ordered_r_lcl_reg_5; wire override_demand_r; wire override_demand_r_reg; wire override_demand_r_reg_0; wire override_demand_r_reg_1; wire p_9_in; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire pass_open_bank_r_lcl_reg_1; wire pass_open_bank_r_lcl_reg_2; wire periodic_rd_ack_r; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_cntr_r; wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; wire periodic_rd_grant_r; wire periodic_rd_insert; wire periodic_rd_r; wire \periodic_read_request.periodic_rd_r_lcl_reg ; wire phy_mc_ctl_full; wire pre_bm_end_r; wire pre_bm_end_r_15; wire pre_bm_end_r_2; wire pre_bm_end_r_9; wire [1:0]q_entry_r; wire [1:0]q_entry_r_30; wire \q_entry_r_reg[0] ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire \q_entry_r_reg[1] ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire \q_entry_r_reg[1]_3 ; wire \q_entry_r_reg[1]_4 ; wire \q_entry_r_reg[1]_5 ; wire \q_entry_r_reg[1]_6 ; wire q_has_priority; wire q_has_priority_11; wire q_has_priority_17; wire q_has_priority_4; wire q_has_priority_r_reg; wire q_has_priority_r_reg_0; wire q_has_priority_r_reg_1; wire q_has_priority_r_reg_2; wire q_has_rd; wire q_has_rd_10; wire q_has_rd_16; wire q_has_rd_3; wire q_has_rd_r_reg; wire q_has_rd_r_reg_0; wire q_has_rd_r_reg_1; wire q_has_rd_r_reg_2; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[0]_2 ; wire \ras_timer_r_reg[0]_3 ; wire \ras_timer_r_reg[0]_4 ; wire \ras_timer_r_reg[0]_5 ; wire \ras_timer_r_reg[0]_6 ; wire \ras_timer_r_reg[2] ; wire ras_timer_zero_r; wire ras_timer_zero_r_6; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; wire [3:2]rb_hit_busies_r; wire [6:4]rb_hit_busies_r_14; wire [4:2]rb_hit_busies_r_3; wire [4:3]rb_hit_busies_r_8; wire [3:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire [3:0]rd_this_rank_r; wire [3:0]rd_wr_r; wire rd_wr_r_lcl_reg; wire read_this_rank; wire read_this_rank_r; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[0]_0 ; wire \req_bank_r_lcl_reg[0]_1 ; wire \req_bank_r_lcl_reg[1] ; wire \req_bank_r_lcl_reg[2] ; wire \req_bank_r_lcl_reg[2]_0 ; wire \req_bank_r_lcl_reg[2]_1 ; wire [19:0]req_data_buf_addr_r; wire [3:0]req_periodic_rd_r; wire [59:10]req_row_r; wire [3:0]req_wr_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire req_wr_r_lcl_reg_2; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ; wire [2:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; wire [4:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r; wire rnk_config_valid_r_lcl_reg; wire rnk_config_valid_r_lcl_reg_0; wire [1:1]row_cmd_wr; wire row_hit_r; wire row_hit_r_0; wire row_hit_r_12; wire row_hit_r_5; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1; wire rtp_timer_ns1_6; wire rtp_timer_ns1_7; wire [1:0]rtp_timer_r; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [0:0]sending_row; wire sent_row; wire tail_r; wire tail_r_24; wire tail_r_26; wire tail_r_28; wire use_addr; wire wait_for_maint_r; wire wait_for_maint_r_18; wire wait_for_maint_r_19; wire wait_for_maint_r_20; wire wait_for_maint_r_lcl_reg; wire wait_for_maint_r_lcl_reg_0; wire wait_for_maint_r_lcl_reg_1; wire wait_for_maint_r_lcl_reg_2; wire was_wr; wire [3:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[0] ; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire \wtr_timer.wtr_cnt_r_reg[1]_0 ; wire \wtr_timer.wtr_cnt_r_reg[1]_1 ; ddr3_if_mig_7series_v4_0_arb_mux arb_mux0 (.CLK(CLK), .DIC(DIC), .E(E), .Q(Q), .SR(SR), .act_this_rank(act_this_rank), .act_this_rank_r(act_this_rank_r), .act_wait_r_lcl_reg(\act_this_rank_r_reg[0] [0]), .act_wait_r_lcl_reg_0(\bank_cntrl[3].bank0_n_49 ), .act_wait_r_lcl_reg_1(\act_this_rank_r_reg[0] [1]), .act_wait_r_lcl_reg_2(\act_this_rank_r_reg[0] [2]), .auto_pre_r_lcl_reg(\bank_cntrl[0].bank0_n_56 ), .auto_pre_r_lcl_reg_0(\bank_cntrl[1].bank0_n_52 ), .auto_pre_r_lcl_reg_1(\bank_cntrl[2].bank0_n_58 ), .auto_pre_r_lcl_reg_2(\bank_cntrl[3].bank0_n_66 ), .auto_pre_r_lcl_reg_3(auto_pre_r_29), .auto_pre_r_lcl_reg_4(auto_pre_r), .auto_pre_r_lcl_reg_5(auto_pre_r_25), .auto_pre_r_lcl_reg_6(auto_pre_r_27), .cke_r(cke_r), .\cmd_pipe_plus.mc_address_reg[44] ({\cmd_pipe_plus.mc_address_reg[44] [37:34],\cmd_pipe_plus.mc_address_reg[44] [32:0]}), .\cmd_pipe_plus.mc_bank_reg[1] (arb_mux0_n_46), .\cmd_pipe_plus.mc_bank_reg[7] (cs_en2), .\cmd_pipe_plus.mc_bank_reg[7]_0 (\cmd_pipe_plus.mc_bank_reg[7] ), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_cmd_reg[0] (\cmd_pipe_plus.mc_cmd_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_ras_n_reg[0] (insert_maint_r1), .\cmd_pipe_plus.mc_we_n_reg[1] (\cmd_pipe_plus.mc_we_n_reg[1] ), .col_data_buf_addr(col_data_buf_addr), .col_rd_wr(col_rd_wr), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ), .demand_priority_r_reg(arb_mux0_n_106), .demand_priority_r_reg_0(\bank_cntrl[3].bank0_n_69 ), .demand_priority_r_reg_1(\bank_cntrl[2].bank0_n_74 ), .demand_priority_r_reg_2(\bank_cntrl[0].bank0_n_74 ), .demand_priority_r_reg_3(\bank_cntrl[1].bank0_n_69 ), .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r), .\grant_r_reg[0] (\grant_r_reg[0] ), .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ), .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ), .\grant_r_reg[0]_10 (\grant_r_reg[0]_10 ), .\grant_r_reg[0]_11 (\grant_r_reg[0]_11 ), .\grant_r_reg[0]_12 (\grant_r_reg[0]_12 ), .\grant_r_reg[0]_2 (\grant_r_reg[0]_2 ), .\grant_r_reg[0]_3 (\grant_r_reg[0]_3 ), .\grant_r_reg[0]_4 (\grant_r_reg[0]_4 ), .\grant_r_reg[0]_5 (\grant_r_reg[0]_5 ), .\grant_r_reg[0]_6 (\grant_r_reg[0]_6 ), .\grant_r_reg[0]_7 (\grant_r_reg[0]_7 ), .\grant_r_reg[0]_8 (\grant_r_reg[0]_8 ), .\grant_r_reg[0]_9 (\grant_r_reg[0]_9 ), .\grant_r_reg[1] (\grant_r_reg[1]_1 ), .\grant_r_reg[1]_0 (arb_mux0_n_97), .\grant_r_reg[1]_1 (arb_mux0_n_98), .\grant_r_reg[2] (arb_mux0_n_85), .\grant_r_reg[2]_0 (arb_mux0_n_99), .\grant_r_reg[3] (arb_mux0_n_22), .\grant_r_reg[3]_0 (arb_mux0_n_86), .\grant_r_reg[3]_1 (\grant_r_reg[3]_0 ), .\grant_r_reg[3]_2 (arb_mux0_n_96), .granted_col_ns(\arb_row_col0/granted_col_ns ), .granted_pre_ns(granted_pre_ns), .granted_row_ns(granted_row_ns), .granted_row_r_reg(granted_row_r_reg), .granted_row_r_reg_0(granted_row_r_reg_0), .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .\last_master_r_reg[0] (arb_mux0_n_89), .\last_master_r_reg[2] (sent_row), .\last_master_r_reg[2]_0 (arb_mux0_n_88), .\last_master_r_reg[3] ({\last_master_r_reg[3] ,sending_row}), .\last_master_r_reg[3]_0 (\last_master_r_reg[3]_1 ), .\last_master_r_reg[3]_1 (\last_master_r_reg[3]_0 ), .\last_master_r_reg[3]_2 (\last_master_r_reg[3]_2 ), .\last_master_r_reg[3]_3 (\last_master_r_reg[3]_3 ), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .mc_cas_n_ns(mc_cas_n_ns), .mc_cke_ns(mc_cke_ns), .mc_cs_n_ns(mc_cs_n_ns), .mc_ras_n_ns(mc_ras_n_ns), .mc_we_n_ns(mc_we_n_ns), .ofs_rdy_r(\bank_state0/ofs_rdy_r_15 ), .ofs_rdy_r_3(\bank_state0/ofs_rdy_r_5 ), .ofs_rdy_r_4(\bank_state0/ofs_rdy_r ), .ofs_rdy_r_5(\bank_state0/ofs_rdy_r_11 ), .override_demand_ns(\bank_state0/override_demand_ns ), .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ), .ras_timer_zero_r_reg(\bank_cntrl[2].bank0_n_56 ), .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg), .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0), .ras_timer_zero_r_reg_2(\bank_cntrl[1].bank0_n_53 ), .ras_timer_zero_r_reg_3(\bank_cntrl[3].bank0_n_67 ), .ras_timer_zero_r_reg_4(\bank_cntrl[3].bank0_n_65 ), .ras_timer_zero_r_reg_5(\bank_cntrl[3].bank0_n_48 ), .ras_timer_zero_r_reg_6(\bank_cntrl[1].bank0_n_51 ), .ras_timer_zero_r_reg_7(\bank_cntrl[1].bank0_n_49 ), .rd_this_rank_r(rd_this_rank_r), .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg), .rd_wr_r_lcl_reg_0(\bank_cntrl[3].bank0_n_31 ), .rd_wr_r_lcl_reg_1(\bank_cntrl[1].bank0_n_30 ), .rd_wr_r_lcl_reg_2(\bank_cntrl[0].bank0_n_33 ), .rd_wr_r_lcl_reg_3(\bank_cntrl[2].bank0_n_35 ), .rd_wr_r_lcl_reg_4(\bank_cntrl[0].bank0_n_32 ), .rd_wr_r_lcl_reg_5(\bank_cntrl[3].bank0_n_32 ), .rd_wr_r_lcl_reg_6(rd_wr_r[0]), .rd_wr_r_lcl_reg_7(rd_wr_r[1]), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0]_1 ), .\req_bank_r_lcl_reg[1] (\req_bank_r_lcl_reg[1] ), .\req_bank_r_lcl_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[8]_0 ), .\req_bank_r_lcl_reg[2]_2 (\cmd_pipe_plus.mc_bank_reg[8]_1 ), .\req_bank_r_lcl_reg[2]_3 (\req_bank_r_lcl_reg[2]_1 ), .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_6 ), .req_bank_rdy_ns_0(\bank_state0/req_bank_rdy_ns ), .req_bank_rdy_ns_1(\bank_state0/req_bank_rdy_ns_12 ), .req_bank_rdy_ns_2(\bank_state0/req_bank_rdy_ns_16 ), .req_bank_rdy_r(\bank_state0/req_bank_rdy_r ), .\req_col_r_reg[9] (\bank_compare0/req_col_r_13 ), .\req_col_r_reg[9]_0 (\bank_compare0/req_col_r ), .\req_col_r_reg[9]_1 (\bank_compare0/req_col_r_2 ), .\req_col_r_reg[9]_2 (\bank_compare0/req_col_r_7 ), .req_data_buf_addr_r(req_data_buf_addr_r), .req_periodic_rd_r(req_periodic_rd_r), .req_row_r({req_row_r[59:56],req_row_r[54:30],req_row_r[10]}), .\req_row_r_lcl_reg[14] (\cmd_pipe_plus.mc_address_reg[10] [27:0]), .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ), .rnk_config_valid_r_lcl_reg(rnk_config_valid_r), .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg), .rnk_config_valid_r_lcl_reg_1(rnk_config_valid_r_lcl_reg_0), .row_cmd_wr(row_cmd_wr), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ), .wr_this_rank_r(wr_this_rank_r), .\wtr_timer.wtr_cnt_r_reg[0] (\wtr_timer.wtr_cnt_r_reg[0] ), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ), .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1]_0 )); ddr3_if_mig_7series_v4_0_bank_cntrl \bank_cntrl[0].bank0 (.CLK(CLK), .D(\bank_queue0/rb_hit_busies_ns_1 [4]), .E(idle_r[0]), .Q(rb_hit_busies_r_14[4]), .SR(SR), .accept_internal_r_reg(accept_internal_r_reg), .accept_internal_r_reg_0(accept_internal_r), .accept_r_reg(bank_common0_n_10), .accept_r_reg_0(accept_r_reg_0), .act_this_rank_r(act_this_rank_r[0]), .\act_this_rank_r_reg[0] (\act_this_rank_r_reg[0] [0]), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_3), .bm_end_r1(bm_end_r1), .bm_end_r1_reg(req_wr_r[0]), .bm_end_r1_reg_0(\bank_cntrl[3].bank0_n_37 ), .bm_end_r1_reg_1(\bank_cntrl[2].bank0_n_37 ), .bm_end_r1_reg_2(\bank_cntrl[1].bank0_n_35 ), .bm_end_r1_reg_3(bm_end_r1_reg_1), .\cmd_pipe_plus.mc_address_reg[14] ({\cmd_pipe_plus.mc_address_reg[10] [13:10],req_row_r[10],\cmd_pipe_plus.mc_address_reg[10] [9:0]}), .\cmd_pipe_plus.mc_address_reg[24] (\bank_compare0/req_col_r ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ), .\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[4:0]), .col_wait_r_reg(col_wait_r_reg_2), .demand_priority_r_reg(demand_priority_r), .demand_priority_r_reg_0(demand_priority_r_7), .demanded_prior_r_reg(demanded_prior_r), .demanded_prior_r_reg_0(demanded_prior_r_reg), .demanded_prior_r_reg_1(demanded_prior_r_8), .demanded_prior_r_reg_2(demanded_prior_r_reg_0), .\grant_r_reg[0] (sending_row), .\grant_r_reg[0]_0 (\cmd_pipe_plus.mc_bank_reg[7] [0]), .\grant_r_reg[1] (\bank_cntrl[0].bank0_n_33 ), .\grant_r_reg[2] (\grant_r_reg[2] ), .\grant_r_reg[2]_0 ({Q[2],Q[0]}), .granted_col_ns(\arb_row_col0/granted_col_ns ), .granted_col_r_reg(\bank_cntrl[0].bank0_n_32 ), .granted_col_r_reg_0(\cmd_pipe_plus.mc_cmd_reg[0] ), .head_r_lcl_reg(head_r_lcl_reg_1), .head_r_lcl_reg_0(\bank_cntrl[0].bank0_n_48 ), .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_49 ), .head_r_lcl_reg_2(head_r_lcl_reg_2), .head_r_lcl_reg_3(head_r_lcl_reg_5), .head_r_lcl_reg_4(head_r_lcl_reg_6), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg), .idle_r_lcl_reg_0(rb_hit_busy_r_reg_1), .idle_r_lcl_reg_1(rb_hit_busy_r_reg_0), .idle_r_lcl_reg_2(rb_hit_busy_r_reg), .idle_r_lcl_reg_3(idle_r[1]), .idle_r_lcl_reg_4(idle_r[2]), .idle_r_lcl_reg_5(idle_r[3]), .idle_r_lcl_reg_6(bank_common0_n_19), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r), .maint_req_r(maint_req_r), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .ofs_rdy_r(\bank_state0/ofs_rdy_r ), .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_10 ), .ordered_r(ordered_r[0]), .ordered_r_lcl_reg(ordered_r_lcl_reg_2), .ordered_r_lcl_reg_0(\bank_cntrl[2].bank0_n_41 ), .ordered_r_lcl_reg_1(\bank_cntrl[2].bank0_n_39 ), .override_demand_r_reg(override_demand_r_reg_1), .p_9_in(p_9_in), .periodic_rd_ack_r_lcl_reg(\q_entry_r_reg[1]_2 ), .periodic_rd_ack_r_lcl_reg_0(\q_entry_r_reg[0]_1 ), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[0].bank0_n_56 ), .pre_bm_end_r(pre_bm_end_r), .pre_bm_end_r_reg(\q_entry_r_reg[0] ), .pre_bm_end_r_reg_0(\q_entry_r_reg[1]_0 ), .pre_bm_end_r_reg_1(\q_entry_r_reg[1]_1 ), .pre_passing_open_bank_r_reg(\ras_timer_r_reg[0]_1 ), .pre_passing_open_bank_r_reg_0(\ras_timer_r_reg[0]_0 ), .q_entry_ns(\bank_queue0/q_entry_ns ), .\q_entry_r_reg[0] (\q_entry_r_reg[0]_0 ), .\q_entry_r_reg[0]_0 (\bank_cntrl[0].bank0_n_45 ), .\q_entry_r_reg[1] (\bank_cntrl[0].bank0_n_41 ), .\q_entry_r_reg[1]_0 (\bank_cntrl[0].bank0_n_43 ), .\q_entry_r_reg[1]_1 (\bank_cntrl[0].bank0_n_44 ), .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_6 ), .\q_entry_r_reg[1]_3 (\bank_cntrl[2].bank0_n_45 ), .\q_entry_r_reg[1]_4 (\bank_cntrl[1].bank0_n_46 ), .q_has_priority(q_has_priority), .q_has_priority_r_reg(rb_hit_busy_r[0]), .q_has_priority_r_reg_0(q_has_priority_r_reg), .q_has_rd(q_has_rd), .q_has_rd_r_reg(q_has_rd_r_reg), .\ras_timer_r_reg[0] (\bank_cntrl[0].bank0_n_34 ), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_3 ), .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_5 ), .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_4 ), .\ras_timer_r_reg[0]_3 (\bank_cntrl[0].bank0_n_55 ), .\ras_timer_r_reg[1] (\bank_cntrl[0].bank0_n_38 ), .\ras_timer_r_reg[1]_0 (\bank_cntrl[2].bank0_n_36 ), .\ras_timer_r_reg[1]_1 (\bank_cntrl[1].bank0_n_31 ), .\ras_timer_r_reg[2] (\bank_cntrl[0].bank0_n_39 ), .\ras_timer_r_reg[2]_0 (\bank_cntrl[3].bank0_n_38 ), .\ras_timer_r_reg[2]_1 (\bank_cntrl[1].bank0_n_36 ), .\ras_timer_r_reg[2]_2 (\bank_cntrl[2].bank0_n_38 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\ras_timer_r_reg[0]_2 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ({rb_hit_busies_r,\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] }), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\bank_queue0/rb_hit_busies_ns_4 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\bank_queue0/rb_hit_busies_ns_0 [4]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\bank_queue0/rb_hit_busies_ns [4]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (rb_hit_busies_r_8[4]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (rb_hit_busies_r_3[4]), .rb_hit_busy_r_reg(rb_hit_busy_r[3]), .rb_hit_busy_r_reg_0(rb_hit_busy_r[2]), .rb_hit_busy_r_reg_1(rb_hit_busy_r[1]), .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2), .rd_this_rank_r(rd_this_rank_r[0]), .\rd_this_rank_r_reg[0] (rd_wr_r[0]), .rd_wr_r_lcl_reg(\bank_cntrl[3].bank0_n_31 ), .rd_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_30 ), .rd_wr_r_lcl_reg_1(\bank_cntrl[3].bank0_n_33 ), .rd_wr_r_lcl_reg_2(\bank_cntrl[1].bank0_n_37 ), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0]_0 ), .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns ), .req_periodic_rd_r(req_periodic_rd_r[0]), .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_40 ), .req_wr_r_lcl_reg_0(\bank_cntrl[3].bank0_n_39 ), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_2), .\rnk_config_strobe_r_reg[0] (\bank_cntrl[0].bank0_n_74 ), .rnk_config_valid_r_lcl_reg(arb_mux0_n_98), .row_hit_r(row_hit_r), .\rp_timer.rp_timer_r_reg[1] (ras_timer_zero_r), .\rp_timer.rp_timer_r_reg[1]_0 (auto_pre_r), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1(rtp_timer_ns1), .\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22), .\starve_limit_cntr_r_reg[2] (col_wait_r), .tail_r(tail_r), .use_addr(use_addr), .wait_for_maint_r(wait_for_maint_r), .wait_for_maint_r_lcl_reg(head_r[0]), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg), .wr_this_rank_r(wr_this_rank_r[0]), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1]_1 )); ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized0 \bank_cntrl[1].bank0 (.CLK(CLK), .D(\bank_queue0/rb_hit_busies_ns_0 [5]), .E(idle_r[1]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ), .SR(SR), .accept_internal_r_reg(accept_internal_r), .accept_r_reg(accept_r_reg), .accept_r_reg_0(bank_common0_n_12), .act_this_rank_r(act_this_rank_r[1]), .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0), .act_wait_r_lcl_reg_0(\act_this_rank_r_reg[0] [0]), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_4), .auto_pre_r_lcl_reg_1(\bank_cntrl[0].bank0_n_56 ), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_reg(req_wr_r[1]), .bm_end_r1_reg_0(pre_bm_end_r_2), .bm_end_r1_reg_1(\bank_cntrl[0].bank0_n_38 ), .bm_end_r1_reg_2(\bank_cntrl[2].bank0_n_37 ), .bm_end_r1_reg_3(\bank_cntrl[3].bank0_n_37 ), .bm_end_r1_reg_4(\bank_cntrl[0].bank0_n_39 ), .bm_end_r1_reg_5(bm_end_r1_reg_2), .\cmd_pipe_plus.mc_address_reg[14] ({\cmd_pipe_plus.mc_address_reg[10] [27:24],req_row_r[25],\cmd_pipe_plus.mc_address_reg[10] [23:14]}), .\cmd_pipe_plus.mc_address_reg[24] (\bank_compare0/req_col_r_2 ), .\cmd_pipe_plus.mc_address_reg[40] (\bank_cntrl[1].bank0_n_71 ), .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[9:5]), .col_wait_r_reg(col_wait_r_reg_0), .demand_priority_r_reg(demand_priority_r_1), .demand_priority_r_reg_0(demand_priority_r_13), .demanded_prior_r(\bank_state0/demanded_prior_r ), .demanded_prior_r_reg(demanded_prior_r_reg), .demanded_prior_r_reg_0(demanded_prior_r_14), .\grant_r_reg[1] (\bank_cntrl[1].bank0_n_30 ), .\grant_r_reg[1]_0 (\bank_cntrl[1].bank0_n_52 ), .\grant_r_reg[1]_1 (\bank_cntrl[1].bank0_n_53 ), .\grant_r_reg[1]_2 (\last_master_r_reg[3] [0]), .\grant_r_reg[1]_3 (\cmd_pipe_plus.mc_bank_reg[7] [1:0]), .\grant_r_reg[2] (\bank_cntrl[1].bank0_n_49 ), .\grant_r_reg[2]_0 (\bank_cntrl[1].bank0_n_51 ), .\grant_r_reg[3] (\bank_cntrl[1].bank0_n_70 ), .\grant_r_reg[3]_0 ({Q[3],Q[1:0]}), .granted_col_r_reg(\cmd_pipe_plus.mc_cmd_reg[0] ), .granted_pre_ns(granted_pre_ns), .head_r_lcl_reg(head_r_lcl_reg_3), .head_r_lcl_reg_0(head_r_lcl_reg_4), .head_r_lcl_reg_1(head_r_lcl_reg_7), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg_0), .idle_r_lcl_reg_0(accept_internal_r_reg), .idle_r_lcl_reg_1(rb_hit_busy_r_reg_0), .idle_r_lcl_reg_2(rb_hit_busy_r_reg_1), .idle_r_lcl_reg_3(idle_r[3]), .idle_r_lcl_reg_4(idle_r[2]), .idle_r_lcl_reg_5(idle_r[0]), .idle_r_lcl_reg_6(idle_r_lcl_reg_5), .\last_master_r_reg[0] (arb_mux0_n_89), .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r), .maint_req_r(maint_req_r), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .ofs_rdy_r(\bank_state0/ofs_rdy_r_5 ), .ofs_rdy_r0(\bank_state0/ofs_rdy_r0 ), .ordered_r(ordered_r[1]), .ordered_r_lcl_reg(ordered_r_lcl_reg_3), .ordered_r_lcl_reg_0(\bank_cntrl[2].bank0_n_41 ), .ordered_r_lcl_reg_1(\bank_cntrl[2].bank0_n_39 ), .override_demand_r_reg(override_demand_r_reg), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1), .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_1(\q_entry_r_reg[1]_2 ), .periodic_rd_ack_r_lcl_reg_2(ordered_r_lcl_reg_1), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .pre_bm_end_r_reg(\q_entry_r_reg[0]_0 ), .pre_bm_end_r_reg_0(\q_entry_r_reg[1]_1 ), .pre_bm_end_r_reg_1(\q_entry_r_reg[1]_0 ), .pre_passing_open_bank_r_reg(rtp_timer_r[1]), .pre_passing_open_bank_r_reg_0(rtp_timer_r[0]), .pre_passing_open_bank_r_reg_1(\bank_cntrl[2].bank0_n_54 ), .pre_passing_open_bank_r_reg_2(\ras_timer_r_reg[0]_1 ), .q_entry_ns(\bank_queue0/q_entry_ns ), .\q_entry_r_reg[0] (\q_entry_r_reg[0] ), .\q_entry_r_reg[0]_0 (\bank_cntrl[1].bank0_n_43 ), .\q_entry_r_reg[1] (\bank_cntrl[1].bank0_n_41 ), .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1]_5 ), .\q_entry_r_reg[1]_1 (\bank_cntrl[1].bank0_n_46 ), .q_has_priority_4(q_has_priority_4), .q_has_priority_r_reg(q_has_priority_r_reg_0), .q_has_rd_3(q_has_rd_3), .q_has_rd_r_reg(q_has_rd_r_reg_0), .\ras_timer_r_reg[0] (\bank_cntrl[1].bank0_n_31 ), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ), .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_6 ), .\ras_timer_r_reg[1] (\bank_cntrl[1].bank0_n_35 ), .\ras_timer_r_reg[1]_0 (\bank_cntrl[0].bank0_n_34 ), .\ras_timer_r_reg[1]_1 (\bank_cntrl[2].bank0_n_36 ), .\ras_timer_r_reg[2] (\bank_cntrl[1].bank0_n_36 ), .\ras_timer_r_reg[2]_0 (\bank_cntrl[2].bank0_n_38 ), .\ras_timer_r_reg[2]_1 (\bank_cntrl[3].bank0_n_38 ), .ras_timer_zero_r_reg(\bank_cntrl[3].bank0_n_48 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\bank_queue0/rb_hit_busies_ns_4 [1]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ({rb_hit_busies_r_3[4],\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,rb_hit_busies_r_3[2]}), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\ras_timer_r_reg[0]_5 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\bank_queue0/rb_hit_busies_ns ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\bank_queue0/rb_hit_busies_ns_1 [5]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ), .rb_hit_busy_r(rb_hit_busy_r[1]), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_48 ), .rb_hit_busy_r_reg_1(\bank_cntrl[0].bank0_n_49 ), .rd_this_rank_r(rd_this_rank_r[1]), .\rd_this_rank_r_reg[0] (rd_wr_r[1]), .rd_wr_r_lcl_reg(\bank_cntrl[3].bank0_n_33 ), .rd_wr_r_lcl_reg_0(rd_wr_r[0]), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_6 ), .req_bank_rdy_r_reg(\bank_cntrl[1].bank0_n_37 ), .req_periodic_rd_r(req_periodic_rd_r[1]), .\req_row_r_lcl_reg[10] (req_row_r[10]), .req_wr_r(req_wr_r[0]), .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_40 ), .req_wr_r_lcl_reg_0(\bank_cntrl[3].bank0_n_39 ), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg), .\rnk_config_strobe_r_reg[0] (\bank_cntrl[1].bank0_n_69 ), .rnk_config_valid_r_lcl_reg(arb_mux0_n_97), .row_cmd_wr(row_cmd_wr), .row_hit_r_0(row_hit_r_0), .\rp_timer.rp_timer_r_reg[1] (auto_pre_r_25), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22), .\starve_limit_cntr_r_reg[2] (col_wait_r_21), .tail_r_24(tail_r_24), .use_addr(use_addr), .wait_for_maint_r_18(wait_for_maint_r_18), .wait_for_maint_r_lcl_reg(head_r[1]), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0), .wr_this_rank_r(wr_this_rank_r[1]), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1]_1 )); ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized1 \bank_cntrl[2].bank0 (.CLK(CLK), .D(\bank_queue0/rb_hit_busies_ns_1 [6]), .E(idle_r[2]), .Q(rb_hit_busies_r_14[6]), .SR(SR), .accept_internal_r_reg(accept_internal_r), .accept_r_reg(bank_common0_n_14), .act_this_rank_r(act_this_rank_r[2]), .\act_this_rank_r_reg[0] (\act_this_rank_r_reg[0] [1]), .act_wait_r_lcl_reg(act_wait_r_lcl_reg_1), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_3), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_2), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_5), .bm_end_r1_reg(req_wr_r[2]), .bm_end_r1_reg_0(bm_end_r1_reg), .bm_end_r1_reg_1(\bank_cntrl[0].bank0_n_38 ), .bm_end_r1_reg_2(\bank_cntrl[3].bank0_n_37 ), .bm_end_r1_reg_3(\bank_cntrl[1].bank0_n_35 ), .bm_end_r1_reg_4(\bank_cntrl[0].bank0_n_39 ), .\cmd_pipe_plus.mc_address_reg[24] (\bank_compare0/req_col_r_7 ), .\cmd_pipe_plus.mc_address_reg[40] (\cmd_pipe_plus.mc_address_reg[44] [33]), .\cmd_pipe_plus.mc_address_reg[44] (req_row_r[44:30]), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8]_0 ), .\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[14:10]), .col_wait_r_reg(col_wait_r_reg_1), .\compute_tail.tail_r_lcl_reg (\compute_tail.tail_r_lcl_reg ), .demand_priority_r(demand_priority_r), .demand_priority_r_reg(demand_priority_r_7), .demanded_prior_r(demanded_prior_r), .demanded_prior_r_reg(demanded_prior_r_8), .demanded_prior_r_reg_0(demanded_prior_r_reg_0), .\entry_cnt_reg[2] (\entry_cnt_reg[2] ), .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2]_0 ), .\grant_r_reg[1] (\grant_r_reg[1]_0 ), .\grant_r_reg[1]_0 (arb_mux0_n_85), .\grant_r_reg[2] (\bank_cntrl[2].bank0_n_35 ), .\grant_r_reg[2]_0 (\bank_cntrl[2].bank0_n_58 ), .\grant_r_reg[2]_1 (\last_master_r_reg[3] [1]), .\grant_r_reg[3] (\grant_r_reg[3] ), .\grant_r_reg[3]_0 ({Q[3:2],Q[0]}), .\grant_r_reg[3]_1 (arb_mux0_n_86), .\grant_r_reg[3]_2 (\cmd_pipe_plus.mc_bank_reg[7] [3:2]), .granted_col_r_reg(\cmd_pipe_plus.mc_cmd_reg[0] ), .granted_row_ns(granted_row_ns), .granted_row_r_reg(\bank_cntrl[2].bank0_n_56 ), .head_r_lcl_reg(head_r_lcl_reg), .head_r_lcl_reg_0(head_r_lcl_reg_8), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg_1), .idle_r_lcl_reg_0(rb_hit_busy_r_reg_1), .idle_r_lcl_reg_1(accept_internal_r_reg), .idle_r_lcl_reg_2(rb_hit_busy_r_reg), .idle_r_lcl_reg_3(idle_r_lcl_reg_3), .idle_r_lcl_reg_4(\bank_cntrl[1].bank0_n_41 ), .idle_r_lcl_reg_5(idle_r_lcl_reg_6), .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r), .maint_req_r(maint_req_r), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r(\bank_state0/ofs_rdy_r_11 ), .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_10 ), .ofs_rdy_r0_0(\bank_state0/ofs_rdy_r0_9 ), .ofs_rdy_r0_1(\bank_state0/ofs_rdy_r0 ), .\order_q_r_reg[0] (\bank_cntrl[2].bank0_n_39 ), .\order_q_r_reg[1] (\bank_cntrl[2].bank0_n_41 ), .ordered_r(ordered_r[2]), .ordered_r_lcl_reg(ordered_r_lcl_reg_4), .ordered_r_lcl_reg_0({ordered_r[3],ordered_r[1:0]}), .override_demand_ns(\bank_state0/override_demand_ns ), .override_demand_r(override_demand_r), .override_demand_r_reg(override_demand_r_reg_0), .periodic_rd_ack_r_lcl_reg(ordered_r_lcl_reg), .periodic_rd_ack_r_lcl_reg_0(\q_entry_r_reg[1]_2 ), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .phy_mc_ctl_full(phy_mc_ctl_full), .pre_bm_end_r_9(pre_bm_end_r_9), .pre_bm_end_r_reg(\q_entry_r_reg[0] ), .pre_bm_end_r_reg_0(\q_entry_r_reg[0]_0 ), .pre_bm_end_r_reg_1(\q_entry_r_reg[1]_1 ), .pre_passing_open_bank_r_reg(\bank_cntrl[0].bank0_n_55 ), .pre_passing_open_bank_r_reg_0(\ras_timer_r_reg[0]_0 ), .\q_entry_r_reg[0] (q_entry_r[0]), .\q_entry_r_reg[1] (\q_entry_r_reg[1]_0 ), .\q_entry_r_reg[1]_0 (\bank_cntrl[2].bank0_n_45 ), .\q_entry_r_reg[1]_1 (q_entry_r[1]), .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_3 ), .\q_entry_r_reg[1]_3 (\bank_cntrl[0].bank0_n_41 ), .q_has_priority_11(q_has_priority_11), .q_has_priority_r_reg(rb_hit_busy_r[2]), .q_has_priority_r_reg_0(q_has_priority_r_reg_1), .q_has_rd_10(q_has_rd_10), .q_has_rd_r_reg(q_has_rd_r_reg_1), .\ras_timer_r_reg[0] (\bank_cntrl[2].bank0_n_36 ), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_2 ), .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_54 ), .\ras_timer_r_reg[1] (\bank_cntrl[2].bank0_n_37 ), .\ras_timer_r_reg[1]_0 (\bank_cntrl[1].bank0_n_31 ), .\ras_timer_r_reg[1]_1 (\bank_cntrl[0].bank0_n_34 ), .\ras_timer_r_reg[2] (\ras_timer_r_reg[2] ), .\ras_timer_r_reg[2]_0 (\bank_cntrl[2].bank0_n_38 ), .\ras_timer_r_reg[2]_1 (\bank_cntrl[1].bank0_n_36 ), .\ras_timer_r_reg[2]_2 (\bank_cntrl[3].bank0_n_38 ), .ras_timer_zero_r_reg(ras_timer_zero_r_reg_0), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\bank_queue0/rb_hit_busies_ns_4 [2]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\bank_queue0/rb_hit_busies_ns [2]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (rb_hit_busies_r[2]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (rb_hit_busies_r_3[2]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\ras_timer_r_reg[0] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ({\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,rb_hit_busies_r_8}), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\bank_queue0/rb_hit_busies_ns_0 ), .rb_hit_busy_r_reg(rb_hit_busy_r_reg_0), .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_48 ), .rb_hit_busy_r_reg_1(\bank_cntrl[0].bank0_n_49 ), .rb_hit_busy_r_reg_2(pass_open_bank_r_lcl_reg_0), .rd_this_rank_r(rd_this_rank_r[2]), .\rd_this_rank_r_reg[0] (rd_wr_r[2]), .rd_wr_r(rd_wr_r[1]), .rd_wr_r_lcl_reg(rd_wr_r[0]), .rd_wr_r_lcl_reg_0(rd_wr_r[3]), .rd_wr_r_lcl_reg_1(\bank_cntrl[1].bank0_n_37 ), .rd_wr_r_lcl_reg_2(\bank_cntrl[3].bank0_n_33 ), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_0 ), .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_12 ), .req_bank_rdy_r_reg(\bank_cntrl[2].bank0_n_40 ), .req_periodic_rd_r(req_periodic_rd_r[2]), .\req_row_r_lcl_reg[10] (\bank_cntrl[1].bank0_n_71 ), .req_wr_r_lcl_reg(\bank_cntrl[3].bank0_n_39 ), .req_wr_r_lcl_reg_0(req_wr_r[3]), .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_0), .\rnk_config_strobe_r_reg[0] (\bank_cntrl[2].bank0_n_74 ), .rnk_config_valid_r_lcl_reg(arb_mux0_n_99), .row_hit_r_5(row_hit_r_5), .\rp_timer.rp_timer_r_reg[1] (ras_timer_zero_r_6), .\rp_timer.rp_timer_r_reg[1]_0 (auto_pre_r_27), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1_7(rtp_timer_ns1_7), .\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22), .\starve_limit_cntr_r_reg[2] (col_wait_r_22), .tail_r_26(tail_r_26), .use_addr(use_addr), .wait_for_maint_r_19(wait_for_maint_r_19), .wait_for_maint_r_lcl_reg(head_r[2]), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_1), .wr_this_rank_r(wr_this_rank_r[2]), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1]_1 )); ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized2 \bank_cntrl[3].bank0 (.CLK(CLK), .D(\bank_queue0/rb_hit_busies_ns_1 ), .E(idle_r[3]), .Q({rb_hit_busies_r_14[6],\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,rb_hit_busies_r_14[4]}), .SR(SR), .accept_internal_r_reg(accept_internal_r), .accept_r_reg(bank_common0_n_16), .act_this_rank_r(act_this_rank_r[3]), .\act_this_rank_r_reg[0] (\act_this_rank_r_reg[0] [2]), .act_wait_r_lcl_reg(act_wait_r_lcl_reg_2), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_1), .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_6), .auto_pre_r_lcl_reg_1(\bank_cntrl[2].bank0_n_58 ), .bm_end_r1_4(bm_end_r1_4), .bm_end_r1_reg(req_wr_r[3]), .bm_end_r1_reg_0(\bank_cntrl[2].bank0_n_37 ), .bm_end_r1_reg_1(\bank_cntrl[1].bank0_n_35 ), .bm_end_r1_reg_2(\bank_cntrl[0].bank0_n_38 ), .bm_end_r1_reg_3(\bank_cntrl[0].bank0_n_39 ), .bm_end_r1_reg_4(bm_end_r1_reg_0), .\cmd_pipe_plus.mc_address_reg[10] (\bank_cntrl[3].bank0_n_49 ), .\cmd_pipe_plus.mc_address_reg[24] (\bank_compare0/req_col_r_13 ), .\cmd_pipe_plus.mc_address_reg[44] ({req_row_r[59:56],\cmd_pipe_plus.mc_address_reg[10] [28],req_row_r[54:45]}), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8]_1 ), .\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[19:15]), .col_wait_r_reg(col_wait_r_reg), .demand_priority_r_reg(demand_priority_r_13), .demand_priority_r_reg_0(demand_priority_r_1), .demanded_prior_r(\bank_state0/demanded_prior_r ), .demanded_prior_r_reg(demanded_prior_r_14), .demanded_prior_r_reg_0(demanded_prior_r_reg_0), .demanded_prior_r_reg_1(demanded_prior_r_reg), .\grant_r_reg[0] (\bank_cntrl[3].bank0_n_65 ), .\grant_r_reg[1] (\grant_r_reg[1] ), .\grant_r_reg[1]_0 (\bank_cntrl[1].bank0_n_70 ), .\grant_r_reg[2] (\bank_cntrl[3].bank0_n_66 ), .\grant_r_reg[3] (\bank_cntrl[3].bank0_n_32 ), .\grant_r_reg[3]_0 (\bank_cntrl[3].bank0_n_39 ), .\grant_r_reg[3]_1 (\bank_cntrl[3].bank0_n_67 ), .\grant_r_reg[3]_2 (Q[3:1]), .\grant_r_reg[3]_3 (\last_master_r_reg[3] [2]), .\grant_r_reg[3]_4 (\cmd_pipe_plus.mc_bank_reg[7] [3]), .\grant_r_reg[3]_5 (arb_mux0_n_46), .granted_col_r_reg(\bank_cntrl[3].bank0_n_31 ), .granted_col_r_reg_0(\cmd_pipe_plus.mc_cmd_reg[0] ), .head_r_lcl_reg(head_r_lcl_reg_0), .head_r_lcl_reg_0(head_r_lcl_reg_9), .hi_priority(hi_priority), .idle_r_lcl_reg(idle_r_lcl_reg_2), .idle_r_lcl_reg_0(accept_internal_r_reg), .idle_r_lcl_reg_1(rb_hit_busy_r_reg_0), .idle_r_lcl_reg_2(rb_hit_busy_r_reg), .idle_r_lcl_reg_3(idle_r_lcl_reg_4), .idle_r_lcl_reg_4(\bank_cntrl[0].bank0_n_44 ), .idle_r_lcl_reg_5(\bank_cntrl[0].bank0_n_43 ), .idle_r_lcl_reg_6(idle_r_lcl_reg_7), .\last_master_r_reg[2] (arb_mux0_n_88), .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r), .maint_req_r(maint_req_r), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .ofs_rdy_r(\bank_state0/ofs_rdy_r_15 ), .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_9 ), .ordered_r(ordered_r[3]), .ordered_r_lcl_reg(ordered_r_lcl_reg_5), .ordered_r_lcl_reg_0(\bank_cntrl[2].bank0_n_41 ), .ordered_r_lcl_reg_1(\bank_cntrl[2].bank0_n_39 ), .override_demand_r(override_demand_r), .periodic_rd_ack_r_lcl_reg(ordered_r_lcl_reg_0), .periodic_rd_ack_r_lcl_reg_0(\q_entry_r_reg[1]_2 ), .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg), .periodic_rd_cntr_r_reg(periodic_rd_cntr_r), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[3].bank0_n_48 ), .pre_bm_end_r_15(pre_bm_end_r_15), .pre_bm_end_r_reg(\q_entry_r_reg[0]_0 ), .pre_bm_end_r_reg_0(\q_entry_r_reg[1]_0 ), .pre_bm_end_r_reg_1(\q_entry_r_reg[0] ), .pre_bm_end_r_reg_2(\bank_cntrl[0].bank0_n_45 ), .pre_passing_open_bank_r_reg(\bank_cntrl[2].bank0_n_54 ), .pre_passing_open_bank_r_reg_0(\ras_timer_r_reg[0]_0 ), .\q_entry_r_reg[0] (q_entry_r_30[0]), .\q_entry_r_reg[1] (\q_entry_r_reg[1]_1 ), .\q_entry_r_reg[1]_0 (q_entry_r_30[1]), .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_4 ), .q_has_priority_17(q_has_priority_17), .q_has_priority_r_reg(rb_hit_busy_r[3]), .q_has_priority_r_reg_0(q_has_priority_r_reg_2), .q_has_rd_16(q_has_rd_16), .q_has_rd_r_reg(q_has_rd_r_reg_2), .\ras_timer_r_reg[0] (\bank_cntrl[3].bank0_n_33 ), .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ), .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_1 ), .\ras_timer_r_reg[1] (\bank_cntrl[3].bank0_n_37 ), .\ras_timer_r_reg[1]_0 (\bank_cntrl[2].bank0_n_36 ), .\ras_timer_r_reg[1]_1 (\bank_cntrl[1].bank0_n_31 ), .\ras_timer_r_reg[1]_2 (\bank_cntrl[0].bank0_n_34 ), .\ras_timer_r_reg[2] (\bank_cntrl[3].bank0_n_38 ), .\ras_timer_r_reg[2]_0 (\bank_cntrl[2].bank0_n_38 ), .\ras_timer_r_reg[2]_1 (\bank_cntrl[1].bank0_n_36 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\bank_queue0/rb_hit_busies_ns_4 [3]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\bank_queue0/rb_hit_busies_ns_0 [3]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\bank_queue0/rb_hit_busies_ns [3]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (rb_hit_busies_r[3]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (rb_hit_busies_r_8[3]), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\ras_timer_r_reg[0]_4 ), .rb_hit_busy_r(rb_hit_busy_r[2:0]), .rb_hit_busy_r_reg(rb_hit_busy_r_reg_1), .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_48 ), .rb_hit_busy_r_reg_1(\bank_cntrl[0].bank0_n_49 ), .rb_hit_busy_r_reg_2(pass_open_bank_r_lcl_reg), .rd_this_rank_r(rd_this_rank_r[3]), .\rd_this_rank_r_reg[0] (rd_wr_r[3]), .rd_wr_r(rd_wr_r[2]), .rd_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_35 ), .rd_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_37 ), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_16 ), .req_bank_rdy_r(\bank_state0/req_bank_rdy_r ), .req_bank_rdy_r_reg(arb_mux0_n_106), .req_periodic_rd_r(req_periodic_rd_r[3]), .\req_row_r_lcl_reg[10] (req_row_r[25]), .req_wr_r(req_wr_r[2]), .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_40 ), .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1), .\rnk_config_strobe_r_reg[0] (\bank_cntrl[3].bank0_n_69 ), .rnk_config_valid_r_lcl_reg(arb_mux0_n_96), .row_cmd_wr(row_cmd_wr), .row_hit_r_12(row_hit_r_12), .\rp_timer.rp_timer_r_reg[1] (auto_pre_r_29), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1_6(rtp_timer_ns1_6), .\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22), .\starve_limit_cntr_r_reg[2] (col_wait_r_23), .tail_r_28(tail_r_28), .use_addr(use_addr), .wait_for_maint_r_20(wait_for_maint_r_20), .wait_for_maint_r_lcl_reg(head_r[3]), .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_2), .wr_this_rank_r(wr_this_rank_r[3]), .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1]_1 )); ddr3_if_mig_7series_v4_0_bank_common bank_common0 (.CLK(CLK), .D(D), .E(idle_r[0]), .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ), .SR(SR), .accept_ns(accept_ns), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .clear_periodic_rd_request(clear_periodic_rd_request), .\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ), .head_r(head_r), .head_r_lcl_reg(bank_common0_n_10), .head_r_lcl_reg_0(bank_common0_n_12), .head_r_lcl_reg_1(bank_common0_n_14), .head_r_lcl_reg_2(bank_common0_n_16), .idle_r_lcl_reg(idle_r[1]), .idle_r_lcl_reg_0(idle_r[2]), .idle_r_lcl_reg_1(idle_r[3]), .insert_maint_r1_lcl_reg(insert_maint_r), .\maint_controller.maint_hit_busies_r_reg[3]_0 (\maint_controller.maint_hit_busies_r_reg[3] ), .\maint_controller.maint_rdy_r1_reg_0 (\maint_controller.maint_rdy_r1_reg ), .\maint_controller.maint_wip_r_lcl_reg_0 (maint_wip_r), .maint_req_r(maint_req_r), .maint_srx_r(maint_srx_r), .\maintenance_request.maint_req_r_lcl_reg (\maintenance_request.maint_req_r_lcl_reg ), .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ), .ordered_r_lcl_reg(ordered_r_lcl_reg_1), .ordered_r_lcl_reg_0(ordered_r_lcl_reg), .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0), .p_9_in(p_9_in), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_0), .periodic_rd_grant_r(periodic_rd_grant_r), .periodic_rd_insert(periodic_rd_insert), .periodic_rd_r(periodic_rd_r), .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ), .\q_entry_r_reg[0] (\q_entry_r_reg[0]_1 ), .\q_entry_r_reg[0]_0 (bank_common0_n_19), .\q_entry_r_reg[1] (\q_entry_r_reg[1] ), .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1]_2 ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (head_r_lcl_reg_2), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\bank_cntrl[1].bank0_n_43 ), .rb_hit_busy_r(rb_hit_busy_r[3:2]), .req_periodic_rd_r_lcl_reg(periodic_rd_cntr_r), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .use_addr(use_addr), .wait_for_maint_r_lcl_reg(accept_internal_r), .was_wr(was_wr), .was_wr_reg_0(periodic_rd_ack_r)); endmodule module ddr3_if_mig_7series_v4_0_bank_queue (\req_data_buf_addr_r_reg[4] , E, act_wait_r_lcl_reg, pre_bm_end_r, pre_passing_open_bank_r, q_has_rd, q_has_priority, wait_for_maint_r, tail_r, wait_for_maint_r_lcl_reg_0, \rp_timer.rp_timer_r_reg[1] , ordered_r, D, accept_internal_r_reg, \q_entry_r_reg[0]_0 , \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 , granted_col_ns, granted_col_r_reg, \grant_r_reg[1] , \ras_timer_r_reg[2] , \ras_timer_r_reg[0] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 , demand_priority_r_reg, req_bank_rdy_ns, act_wait_ns, \ras_timer_r_reg[0]_0 , \q_entry_r_reg[1]_0 , q_entry_ns, \q_entry_r_reg[1]_1 , \q_entry_r_reg[1]_2 , \q_entry_r_reg[0]_1 , p_9_in, head_r_lcl_reg_0, head_r_lcl_reg_1, \q_entry_r_reg[1]_3 , p_145_out, \ras_timer_r_reg[0]_1 , head_r_lcl_reg_2, CLK, pass_open_bank_ns, pre_bm_end_ns, pre_passing_open_bank_ns, q_has_rd_r_reg_0, q_has_priority_r_reg_0, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_1, SR, idle_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_3, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_0, \req_bank_r_lcl_reg[0] , idle_r_lcl_reg_1, Q, rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 , idle_r_lcl_reg_3, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 , rd_wr_r_lcl_reg, rd_wr_r_lcl_reg_0, \rtw_timer.rtw_cnt_r_reg[1] , col_wait_r_reg, override_demand_r_reg, rd_wr_r_lcl_reg_1, \wtr_timer.wtr_cnt_r_reg[1] , \ras_timer_r_reg[1] , rd_wr_r_lcl_reg_2, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[1]_1 , bm_end_r1_reg, bm_end_r1_reg_0, bm_end_r1_reg_1, bm_end_r1_reg_2, bm_end_r1_reg_3, \ras_timer_r_reg[2]_0 , \ras_timer_r_reg[2]_1 , \ras_timer_r_reg[2]_2 , req_priority_r, req_wr_r_lcl_reg, rd_wr_r_lcl_reg_3, req_wr_r_lcl_reg_0, rnk_config_valid_r_lcl_reg, col_wait_r_reg_0, act_wait_r_lcl_reg_0, \grant_r_reg[0] , bm_end_r1_reg_4, pre_passing_open_bank_r_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 , pre_passing_open_bank_r_reg_1, \q_entry_r_reg[1]_4 , pre_bm_end_r_reg_0, pre_bm_end_r_reg_1, \q_entry_r_reg[1]_5 , periodic_rd_ack_r_lcl_reg, init_calib_complete_reg_rep__6, rb_hit_busy_r_reg, rb_hit_busy_r_reg_0, accept_r_reg, periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg_2, periodic_rd_ack_r_lcl_reg_1, use_addr, accept_internal_r_reg_0, req_wr_r_lcl_reg_1, req_wr_r_lcl_reg_2, \grant_r_reg[0]_0 , idle_r_lcl_reg_4, idle_r_lcl_reg_5, idle_r_lcl_reg_6, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 , rb_hit_busy_r_reg_1, idle_r_lcl_reg_7, ordered_r_lcl_reg_1, ordered_r_lcl_reg_2); output \req_data_buf_addr_r_reg[4] ; output [0:0]E; output act_wait_r_lcl_reg; output pre_bm_end_r; output pre_passing_open_bank_r; output q_has_rd; output q_has_priority; output wait_for_maint_r; output tail_r; output wait_for_maint_r_lcl_reg_0; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]ordered_r; output [0:0]D; output accept_internal_r_reg; output \q_entry_r_reg[0]_0 ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; output granted_col_ns; output granted_col_r_reg; output \grant_r_reg[1] ; output [2:0]\ras_timer_r_reg[2] ; output \ras_timer_r_reg[0] ; output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; output demand_priority_r_reg; output req_bank_rdy_ns; output act_wait_ns; output \ras_timer_r_reg[0]_0 ; output \q_entry_r_reg[1]_0 ; output [0:0]q_entry_ns; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[1]_2 ; output \q_entry_r_reg[0]_1 ; output p_9_in; output head_r_lcl_reg_0; output head_r_lcl_reg_1; output \q_entry_r_reg[1]_3 ; output p_145_out; output \ras_timer_r_reg[0]_1 ; output head_r_lcl_reg_2; input CLK; input pass_open_bank_ns; input pre_bm_end_ns; input pre_passing_open_bank_ns; input q_has_rd_r_reg_0; input q_has_priority_r_reg_0; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_1; input [0:0]SR; input idle_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_3; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_0; input \req_bank_r_lcl_reg[0] ; input idle_r_lcl_reg_1; input [0:0]Q; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; input idle_r_lcl_reg_3; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ; input rd_wr_r_lcl_reg; input rd_wr_r_lcl_reg_0; input \rtw_timer.rtw_cnt_r_reg[1] ; input col_wait_r_reg; input override_demand_r_reg; input rd_wr_r_lcl_reg_1; input \wtr_timer.wtr_cnt_r_reg[1] ; input \ras_timer_r_reg[1] ; input rd_wr_r_lcl_reg_2; input \ras_timer_r_reg[1]_0 ; input \ras_timer_r_reg[1]_1 ; input bm_end_r1_reg; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input bm_end_r1_reg_3; input \ras_timer_r_reg[2]_0 ; input \ras_timer_r_reg[2]_1 ; input \ras_timer_r_reg[2]_2 ; input req_priority_r; input req_wr_r_lcl_reg; input rd_wr_r_lcl_reg_3; input req_wr_r_lcl_reg_0; input rnk_config_valid_r_lcl_reg; input col_wait_r_reg_0; input act_wait_r_lcl_reg_0; input [0:0]\grant_r_reg[0] ; input bm_end_r1_reg_4; input pre_passing_open_bank_r_reg_0; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; input pre_passing_open_bank_r_reg_1; input \q_entry_r_reg[1]_4 ; input pre_bm_end_r_reg_0; input pre_bm_end_r_reg_1; input \q_entry_r_reg[1]_5 ; input periodic_rd_ack_r_lcl_reg; input init_calib_complete_reg_rep__6; input rb_hit_busy_r_reg; input rb_hit_busy_r_reg_0; input accept_r_reg; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg_2; input periodic_rd_ack_r_lcl_reg_1; input use_addr; input accept_internal_r_reg_0; input req_wr_r_lcl_reg_1; input req_wr_r_lcl_reg_2; input [0:0]\grant_r_reg[0]_0 ; input [0:0]idle_r_lcl_reg_4; input [0:0]idle_r_lcl_reg_5; input [0:0]idle_r_lcl_reg_6; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ; input rb_hit_busy_r_reg_1; input idle_r_lcl_reg_7; input ordered_r_lcl_reg_1; input ordered_r_lcl_reg_2; wire CLK; wire [0:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_internal_r_reg_0; wire accept_r_reg; wire act_wait_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire col_wait_r_reg; wire col_wait_r_reg_0; wire demand_priority_r_reg; wire \grant_r[1]_i_6_n_0 ; wire [0:0]\grant_r_reg[0] ; wire [0:0]\grant_r_reg[0]_0 ; wire \grant_r_reg[1] ; wire granted_col_ns; wire granted_col_r_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire head_r_lcl_reg_2; wire head_r_lcl_reg_3; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire [0:0]idle_r_lcl_reg_4; wire [0:0]idle_r_lcl_reg_5; wire [0:0]idle_r_lcl_reg_6; wire idle_r_lcl_reg_7; wire init_calib_complete_reg_rep__6; wire \maintenance_request.maint_req_r_lcl_reg ; wire [1:0]order_q_r; wire \order_q_r[0]_i_1_n_0 ; wire \order_q_r[1]_i_1_n_0 ; wire [0:0]ordered_r; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire ordered_r_lcl_reg_2; wire override_demand_r_reg; wire p_145_out; wire p_9_in; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire pre_bm_end_ns; wire pre_bm_end_r; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_bm_end_r_reg_2; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg_0; wire pre_passing_open_bank_r_reg_1; wire [0:0]q_entry_ns; wire [1:1]q_entry_ns_0; wire [1:0]q_entry_r; wire \q_entry_r[0]_i_1_n_0 ; wire \q_entry_r[1]_i_1_n_0 ; wire \q_entry_r[1]_i_3__2_n_0 ; wire \q_entry_r[1]_i_4__1_n_0 ; wire \q_entry_r[1]_i_5__0_n_0 ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire \q_entry_r_reg[1]_3 ; wire \q_entry_r_reg[1]_4 ; wire \q_entry_r_reg[1]_5 ; wire q_has_priority; wire q_has_priority_r_reg_0; wire q_has_rd; wire q_has_rd_r_reg_0; wire \ras_timer_r[0]_i_2_n_0 ; wire \ras_timer_r[1]_i_2_n_0 ; wire \ras_timer_r[2]_i_2_n_0 ; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire [2:0]\ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire \ras_timer_r_reg[2]_2 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire rd_wr_r_lcl_reg_3; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_ns; wire \req_data_buf_addr_r_reg[4] ; wire req_priority_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire req_wr_r_lcl_reg_2; wire rnk_config_valid_r_lcl_reg; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire set_order_q; wire tail_r; wire use_addr; wire wait_for_maint_r; wire wait_for_maint_r_lcl_reg_0; wire wait_for_maint_r_lcl_reg_1; wire \wtr_timer.wtr_cnt_r_reg[1] ; (* SOFT_HLUTNM = "soft_lutpair1053" *) LUT5 #( .INIT(32'h2AAAAAAA)) accept_internal_r_i_1 (.I0(init_calib_complete_reg_rep__6), .I1(accept_internal_r_reg), .I2(idle_r_lcl_reg_3), .I3(idle_r_lcl_reg_2), .I4(idle_r_lcl_reg_1), .O(p_9_in)); LUT6 #( .INIT(64'hFFFFFFFF0404FF04)) act_wait_r_lcl_i_1__0 (.I0(\ras_timer_r_reg[0] ), .I1(act_wait_r_lcl_reg_0), .I2(\grant_r_reg[0] ), .I3(act_wait_r_lcl_reg), .I4(\q_entry_r_reg[0]_0 ), .I5(bm_end_r1_reg_4), .O(act_wait_ns)); LUT6 #( .INIT(64'h00000000F4F4FFF4)) act_wait_r_lcl_i_2__0 (.I0(pre_passing_open_bank_r_reg_0), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]), .I4(pre_passing_open_bank_r_reg_1), .I5(\ras_timer_r_reg[0]_0 ), .O(\ras_timer_r_reg[0] )); LUT5 #( .INIT(32'h55151515)) act_wait_r_lcl_i_4 (.I0(pre_passing_open_bank_r), .I1(\grant_r_reg[0]_0 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg_1), .I4(req_wr_r_lcl_reg_2), .O(\ras_timer_r_reg[0]_1 )); FDRE auto_pre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(auto_pre_r_lcl_reg_0), .Q(\rp_timer.rp_timer_r_reg[1] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \compute_tail.tail_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_0), .Q(tail_r), .R(SR)); LUT6 #( .INIT(64'hE0E0E0EEE0EEE0EE)) demand_priority_r_i_3__1 (.I0(req_priority_r), .I1(q_has_priority), .I2(rd_wr_r_lcl_reg_1), .I3(order_q_r[1]), .I4(order_q_r[0]), .I5(req_wr_r_lcl_reg), .O(demand_priority_r_reg)); LUT6 #( .INIT(64'h0003000200000002)) \grant_r[1]_i_4 (.I0(\rtw_timer.rtw_cnt_r_reg[1] ), .I1(col_wait_r_reg), .I2(\grant_r[1]_i_6_n_0 ), .I3(override_demand_r_reg), .I4(rd_wr_r_lcl_reg_1), .I5(\wtr_timer.wtr_cnt_r_reg[1] ), .O(\grant_r_reg[1] )); LUT6 #( .INIT(64'hFFFFFFFF44544444)) \grant_r[1]_i_6 (.I0(rd_wr_r_lcl_reg_1), .I1(order_q_r[1]), .I2(order_q_r[0]), .I3(rd_wr_r_lcl_reg_3), .I4(req_wr_r_lcl_reg_0), .I5(rnk_config_valid_r_lcl_reg), .O(\grant_r[1]_i_6_n_0 )); LUT2 #( .INIT(4'hB)) \grant_r[3]_i_3 (.I0(\grant_r_reg[1] ), .I1(rd_wr_r_lcl_reg_0), .O(granted_col_r_reg)); LUT2 #( .INIT(4'hB)) granted_col_r_i_1 (.I0(granted_col_r_reg), .I1(rd_wr_r_lcl_reg), .O(granted_col_ns)); FDSE head_r_lcl_reg (.C(CLK), .CE(1'b1), .D(head_r_lcl_reg_3), .Q(wait_for_maint_r_lcl_reg_0), .S(rstdiv0_sync_r1_reg_rep__0)); LUT5 #( .INIT(32'h55151515)) i___0_i_1 (.I0(pre_bm_end_r), .I1(\grant_r_reg[0]_0 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg_1), .I4(req_wr_r_lcl_reg_2), .O(\q_entry_r_reg[0]_0 )); LUT6 #( .INIT(64'h00FF000014141414)) i___1_i_1 (.I0(rb_hit_busy_r_reg), .I1(rb_hit_busy_r_reg_0), .I2(head_r_lcl_reg_1), .I3(q_entry_r[1]), .I4(q_entry_r[0]), .I5(accept_r_reg), .O(head_r_lcl_reg_0)); (* SOFT_HLUTNM = "soft_lutpair1054" *) LUT5 #( .INIT(32'h01168001)) i___1_i_2 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(idle_r_lcl_reg_4), .I2(idle_r_lcl_reg_5), .I3(idle_r_lcl_reg_6), .I4(periodic_rd_ack_r_lcl_reg), .O(head_r_lcl_reg_2)); LUT5 #( .INIT(32'hFFC5FFFF)) i___1_i_3 (.I0(head_r_lcl_reg_1), .I1(periodic_rd_ack_r_lcl_reg), .I2(\req_data_buf_addr_r_reg[4] ), .I3(periodic_rd_ack_r_lcl_reg_0), .I4(\q_entry_r_reg[0]_0 ), .O(\q_entry_r_reg[1]_3 )); (* SOFT_HLUTNM = "soft_lutpair1057" *) LUT3 #( .INIT(8'hFB)) i___37_i_1 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(q_entry_r[0]), .I2(q_entry_r[1]), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'hBB0BBB0B0000BB0B)) i___44_i_1 (.I0(pre_bm_end_r_reg_1), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]), .I3(pre_bm_end_r_reg_2), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]), .I5(pre_bm_end_r_reg_0), .O(head_r_lcl_reg_1)); LUT6 #( .INIT(64'h00000000FD555555)) i___55_i_1 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(periodic_rd_ack_r_lcl_reg_1), .I2(use_addr), .I3(accept_internal_r_reg_0), .I4(wait_for_maint_r_lcl_reg_0), .I5(req_wr_r_lcl_reg_1), .O(accept_internal_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1053" *) LUT1 #( .INIT(2'h1)) idle_r_lcl_i_1__2 (.I0(accept_internal_r_reg), .O(E)); FDRE idle_r_lcl_reg (.C(CLK), .CE(1'b1), .D(E), .Q(\req_data_buf_addr_r_reg[4] ), .R(1'b0)); LUT6 #( .INIT(64'h553100305531CC30)) \order_q_r[0]_i_1 (.I0(ordered_r_lcl_reg_2), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg), .I4(set_order_q), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\order_q_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAAC200C0AAC2F0C0)) \order_q_r[1]_i_1 (.I0(ordered_r_lcl_reg_1), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg), .I4(set_order_q), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\order_q_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h8000800080000000)) \order_q_r[1]_i_3 (.I0(req_wr_r_lcl_reg_2), .I1(\req_data_buf_addr_r_reg[4] ), .I2(wait_for_maint_r_lcl_reg_0), .I3(accept_internal_r_reg_0), .I4(use_addr), .I5(periodic_rd_ack_r_lcl_reg_1), .O(set_order_q)); FDRE \order_q_r_reg[0] (.C(CLK), .CE(1'b1), .D(\order_q_r[0]_i_1_n_0 ), .Q(order_q_r[0]), .R(1'b0)); FDRE \order_q_r_reg[1] (.C(CLK), .CE(1'b1), .D(\order_q_r[1]_i_1_n_0 ), .Q(order_q_r[1]), .R(1'b0)); FDRE ordered_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_0), .Q(ordered_r), .R(1'b0)); FDRE pass_open_bank_r_lcl_reg (.C(CLK), .CE(1'b1), .D(pass_open_bank_ns), .Q(act_wait_r_lcl_reg), .R(1'b0)); FDRE pre_bm_end_r_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_ns), .Q(pre_bm_end_r), .R(1'b0)); FDRE pre_passing_open_bank_r_reg (.C(CLK), .CE(1'b1), .D(pre_passing_open_bank_ns), .Q(pre_passing_open_bank_r), .R(1'b0)); LUT6 #( .INIT(64'hB380FFFFBF8C0000)) \q_entry_r[0]_i_1 (.I0(rb_hit_busy_r_reg_1), .I1(\q_entry_r_reg[0]_0 ), .I2(periodic_rd_ack_r_lcl_reg_0), .I3(idle_r_lcl_reg_7), .I4(\q_entry_r_reg[1]_3 ), .I5(q_entry_r[0]), .O(\q_entry_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h6996)) \q_entry_r[0]_i_3 (.I0(pre_bm_end_r_reg_1), .I1(\q_entry_r_reg[0]_0 ), .I2(\q_entry_r[1]_i_3__2_n_0 ), .I3(pre_bm_end_r_reg_0), .O(\q_entry_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair1057" *) LUT3 #( .INIT(8'hB8)) \q_entry_r[1]_i_1 (.I0(q_entry_ns_0), .I1(\q_entry_r_reg[1]_3 ), .I2(q_entry_r[1]), .O(\q_entry_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hBB888BB8B88BBB88)) \q_entry_r[1]_i_2 (.I0(\q_entry_r_reg[1]_5 ), .I1(pre_bm_end_r_reg_0), .I2(periodic_rd_ack_r_lcl_reg), .I3(\q_entry_r[1]_i_5__0_n_0 ), .I4(\q_entry_r[1]_i_3__2_n_0 ), .I5(\q_entry_r_reg[0]_0 ), .O(q_entry_ns)); (* SOFT_HLUTNM = "soft_lutpair1055" *) LUT5 #( .INIT(32'hA9956AA9)) \q_entry_r[1]_i_2__0 (.I0(\q_entry_r[1]_i_5__0_n_0 ), .I1(pre_bm_end_r_reg_1), .I2(pre_bm_end_r_reg_0), .I3(\q_entry_r_reg[0]_0 ), .I4(\q_entry_r[1]_i_3__2_n_0 ), .O(\q_entry_r_reg[1]_1 )); LUT5 #( .INIT(32'h0BFB04F4)) \q_entry_r[1]_i_2__2 (.I0(\q_entry_r[1]_i_3__2_n_0 ), .I1(periodic_rd_ack_r_lcl_reg), .I2(\q_entry_r_reg[0]_0 ), .I3(\q_entry_r[1]_i_4__1_n_0 ), .I4(\q_entry_r[1]_i_5__0_n_0 ), .O(q_entry_ns_0)); LUT6 #( .INIT(64'h55555555C3CC33C3)) \q_entry_r[1]_i_3 (.I0(\q_entry_r_reg[1]_4 ), .I1(\q_entry_r[1]_i_5__0_n_0 ), .I2(pre_bm_end_r_reg_0), .I3(\q_entry_r[1]_i_3__2_n_0 ), .I4(\q_entry_r_reg[0]_0 ), .I5(pre_bm_end_r_reg_1), .O(\q_entry_r_reg[1]_0 )); LUT4 #( .INIT(16'h6996)) \q_entry_r[1]_i_3__2 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(idle_r_lcl_reg_4), .I2(idle_r_lcl_reg_5), .I3(idle_r_lcl_reg_6), .O(\q_entry_r[1]_i_3__2_n_0 )); LUT6 #( .INIT(64'h1E001EFF1EFF1E00)) \q_entry_r[1]_i_4__1 (.I0(rb_hit_busy_r_reg_0), .I1(head_r_lcl_reg_1), .I2(rb_hit_busy_r_reg), .I3(periodic_rd_ack_r_lcl_reg_0), .I4(q_entry_r[1]), .I5(q_entry_r[0]), .O(\q_entry_r[1]_i_4__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1055" *) LUT5 #( .INIT(32'hD4422BBD)) \q_entry_r[1]_i_5 (.I0(\q_entry_r[1]_i_3__2_n_0 ), .I1(\q_entry_r_reg[0]_0 ), .I2(pre_bm_end_r_reg_0), .I3(pre_bm_end_r_reg_1), .I4(\q_entry_r[1]_i_5__0_n_0 ), .O(\q_entry_r_reg[1]_2 )); (* SOFT_HLUTNM = "soft_lutpair1054" *) LUT4 #( .INIT(16'h7EE8)) \q_entry_r[1]_i_5__0 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(idle_r_lcl_reg_6), .I2(idle_r_lcl_reg_5), .I3(idle_r_lcl_reg_4), .O(\q_entry_r[1]_i_5__0_n_0 )); FDRE \q_entry_r_reg[0] (.C(CLK), .CE(1'b1), .D(\q_entry_r[0]_i_1_n_0 ), .Q(q_entry_r[0]), .R(SR)); FDRE \q_entry_r_reg[1] (.C(CLK), .CE(1'b1), .D(\q_entry_r[1]_i_1_n_0 ), .Q(q_entry_r[1]), .R(SR)); FDRE q_has_priority_r_reg (.C(CLK), .CE(1'b1), .D(q_has_priority_r_reg_0), .Q(q_has_priority), .R(1'b0)); FDRE q_has_rd_r_reg (.C(CLK), .CE(1'b1), .D(q_has_rd_r_reg_0), .Q(q_has_rd), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1056" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[0]_i_1 (.I0(\ras_timer_r[0]_i_2_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(\ras_timer_r_reg[1] ), .O(\ras_timer_r_reg[2] [0])); LUT6 #( .INIT(64'hB8B8B8B8BB888888)) \ras_timer_r[0]_i_2 (.I0(rd_wr_r_lcl_reg_2), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]), .I2(\ras_timer_r_reg[1]_0 ), .I3(\ras_timer_r_reg[1]_1 ), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]), .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]), .O(\ras_timer_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1056" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[1]_i_1__0 (.I0(\ras_timer_r[1]_i_2_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(bm_end_r1_reg), .O(\ras_timer_r_reg[2] [1])); LUT6 #( .INIT(64'hB8B8B8B888BB8888)) \ras_timer_r[1]_i_2 (.I0(bm_end_r1_reg_0), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]), .I2(bm_end_r1_reg_1), .I3(bm_end_r1_reg_2), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]), .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]), .O(\ras_timer_r[1]_i_2_n_0 )); LUT3 #( .INIT(8'hB8)) \ras_timer_r[2]_i_1__0 (.I0(\ras_timer_r[2]_i_2_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(bm_end_r1_reg_3), .O(\ras_timer_r_reg[2] [2])); LUT6 #( .INIT(64'hBBBBB8888888B888)) \ras_timer_r[2]_i_2 (.I0(\ras_timer_r_reg[2]_0 ), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]), .I3(\ras_timer_r_reg[2]_1 ), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]), .I5(\ras_timer_r_reg[2]_2 ), .O(\ras_timer_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1 (.I0(accept_internal_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .I2(idle_r_lcl_reg_1), .I3(Q), .I4(\q_entry_r_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(D)); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0 (.I0(accept_internal_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .I2(idle_r_lcl_reg_2), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ), .I4(\q_entry_r_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1 (.I0(accept_internal_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .I2(idle_r_lcl_reg_3), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ), .I4(\q_entry_r_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 )); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 [0]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 [1]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 [2]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]), .R(1'b0)); LUT2 #( .INIT(4'h2)) rb_hit_busy_r_i_1__2 (.I0(accept_internal_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .O(p_145_out)); LUT5 #( .INIT(32'h888A8A8A)) req_bank_rdy_r_i_1__2 (.I0(col_wait_r_reg_0), .I1(rd_wr_r_lcl_reg_1), .I2(order_q_r[1]), .I3(order_q_r[0]), .I4(req_wr_r_lcl_reg), .O(req_bank_rdy_ns)); FDRE wait_for_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(wait_for_maint_r_lcl_reg_1), .Q(wait_for_maint_r), .R(\maintenance_request.maint_req_r_lcl_reg )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_queue" *) module ddr3_if_mig_7series_v4_0_bank_queue__parameterized0 (\req_data_buf_addr_r_reg[4] , E, act_wait_r_lcl_reg, bm_end_r1_reg, q_has_rd_3, q_has_priority_4, wait_for_maint_r_18, tail_r_24, wait_for_maint_r_lcl_reg_0, \rp_timer.rp_timer_r_reg[1] , ordered_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] , rb_hit_busy_r_reg, \q_entry_r_reg[0]_0 , D, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] , \ras_timer_r_reg[2] , \ras_timer_r_reg[0] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 , demand_priority_r_reg, order_q_r, req_bank_rdy_ns, \ras_timer_r_reg[0]_0 , p_106_out, \q_entry_r_reg[1]_0 , \q_entry_r_reg[1]_1 , \q_entry_r_reg[0]_1 , act_wait_ns, head_r_lcl_reg_0, \q_entry_r_reg[1]_2 , \ras_timer_r_reg[0]_1 , \grant_r_reg[1] , CLK, pass_open_bank_ns, pre_bm_end_ns, pre_passing_open_bank_ns, q_has_rd_r_reg_0, q_has_priority_r_reg_0, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_1, SR, idle_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_1, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_0, \req_bank_r_lcl_reg[2] , idle_r_lcl_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 , rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_2, Q, idle_r_lcl_reg_3, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 , \ras_timer_r_reg[1] , \ras_timer_r_reg[1]_0 , rd_wr_r_lcl_reg, \ras_timer_r_reg[1]_1 , bm_end_r1_reg_0, bm_end_r1_reg_1, bm_end_r1_reg_2, bm_end_r1_reg_3, \ras_timer_r_reg[2]_0 , bm_end_r1_reg_4, \ras_timer_r_reg[2]_1 , \ras_timer_r_reg[2]_2 , req_priority_r, rd_wr_r_lcl_reg_0, req_wr_r_lcl_reg, col_wait_r_reg, \grant_r_reg[1]_0 , req_wr_r_lcl_reg_0, periodic_rd_ack_r_lcl_reg, use_addr, accept_internal_r_reg, req_wr_r_lcl_reg_1, pre_bm_end_r_reg_0, idle_r_lcl_reg_4, idle_r_lcl_reg_5, idle_r_lcl_reg_6, periodic_rd_ack_r_lcl_reg_0, periodic_rd_ack_r_lcl_reg_1, act_wait_r_lcl_reg_0, \grant_r_reg[1]_1 , bm_end_r1_reg_5, rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, accept_r_reg, pre_passing_open_bank_r_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 , pre_passing_open_bank_r_reg_1, pre_bm_end_r_reg_1, pre_bm_end_r_reg_2, ras_timer_zero_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 , q_entry_ns, idle_r_lcl_reg_7, ordered_r_lcl_reg_1, rstdiv0_sync_r1_reg_rep__21, ordered_r_lcl_reg_2); output \req_data_buf_addr_r_reg[4] ; output [0:0]E; output act_wait_r_lcl_reg; output bm_end_r1_reg; output q_has_rd_3; output q_has_priority_4; output wait_for_maint_r_18; output tail_r_24; output wait_for_maint_r_lcl_reg_0; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]ordered_r; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ; output rb_hit_busy_r_reg; output \q_entry_r_reg[0]_0 ; output [0:0]D; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; output [2:0]\ras_timer_r_reg[2] ; output \ras_timer_r_reg[0] ; output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; output demand_priority_r_reg; output [1:0]order_q_r; output req_bank_rdy_ns; output \ras_timer_r_reg[0]_0 ; output p_106_out; output \q_entry_r_reg[1]_0 ; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[0]_1 ; output act_wait_ns; output head_r_lcl_reg_0; output \q_entry_r_reg[1]_2 ; output \ras_timer_r_reg[0]_1 ; output \grant_r_reg[1] ; input CLK; input pass_open_bank_ns; input pre_bm_end_ns; input pre_passing_open_bank_ns; input q_has_rd_r_reg_0; input q_has_priority_r_reg_0; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_1; input [0:0]SR; input idle_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_1; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_0; input \req_bank_r_lcl_reg[2] ; input idle_r_lcl_reg_1; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_2; input [0:0]Q; input idle_r_lcl_reg_3; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; input \ras_timer_r_reg[1] ; input \ras_timer_r_reg[1]_0 ; input rd_wr_r_lcl_reg; input \ras_timer_r_reg[1]_1 ; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input bm_end_r1_reg_3; input \ras_timer_r_reg[2]_0 ; input bm_end_r1_reg_4; input \ras_timer_r_reg[2]_1 ; input \ras_timer_r_reg[2]_2 ; input req_priority_r; input rd_wr_r_lcl_reg_0; input req_wr_r_lcl_reg; input col_wait_r_reg; input [0:0]\grant_r_reg[1]_0 ; input req_wr_r_lcl_reg_0; input periodic_rd_ack_r_lcl_reg; input use_addr; input accept_internal_r_reg; input req_wr_r_lcl_reg_1; input pre_bm_end_r_reg_0; input [0:0]idle_r_lcl_reg_4; input [0:0]idle_r_lcl_reg_5; input [0:0]idle_r_lcl_reg_6; input periodic_rd_ack_r_lcl_reg_0; input periodic_rd_ack_r_lcl_reg_1; input act_wait_r_lcl_reg_0; input [0:0]\grant_r_reg[1]_1 ; input bm_end_r1_reg_5; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input accept_r_reg; input pre_passing_open_bank_r_reg_0; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; input pre_passing_open_bank_r_reg_1; input pre_bm_end_r_reg_1; input pre_bm_end_r_reg_2; input ras_timer_zero_r; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ; input [0:0]q_entry_ns; input idle_r_lcl_reg_7; input ordered_r_lcl_reg_1; input rstdiv0_sync_r1_reg_rep__21; input ordered_r_lcl_reg_2; wire CLK; wire [0:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_r_reg; wire act_wait_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire bm_end_r1_reg_5; wire col_wait_r_reg; wire demand_priority_r_reg; wire \grant_r_reg[1] ; wire [0:0]\grant_r_reg[1]_0 ; wire [0:0]\grant_r_reg[1]_1 ; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire [0:0]idle_r_lcl_reg_4; wire [0:0]idle_r_lcl_reg_5; wire [0:0]idle_r_lcl_reg_6; wire idle_r_lcl_reg_7; wire \maintenance_request.maint_req_r_lcl_reg ; wire [1:0]order_q_r; wire \order_q_r[0]_i_1__0_n_0 ; wire \order_q_r[1]_i_1__0_n_0 ; wire [0:0]ordered_r; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire ordered_r_lcl_reg_2; wire p_106_out; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire pre_bm_end_ns; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_bm_end_r_reg_2; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg_0; wire pre_passing_open_bank_r_reg_1; wire [0:0]q_entry_ns; wire [1:0]q_entry_r; wire \q_entry_r[0]_i_1__0_n_0 ; wire \q_entry_r[0]_i_2__1_n_0 ; wire \q_entry_r[1]_i_1__0_n_0 ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[0]_1 ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire q_has_priority_4; wire q_has_priority_r_reg_0; wire q_has_rd_3; wire q_has_rd_r_reg_0; wire \ras_timer_r[0]_i_2__1_n_0 ; wire \ras_timer_r[1]_i_3_n_0 ; wire \ras_timer_r[2]_i_2__1_n_0 ; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[0]_1 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire [2:0]\ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire \ras_timer_r_reg[2]_2 ; wire ras_timer_zero_r; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire \req_bank_r_lcl_reg[2] ; wire req_bank_rdy_ns; wire \req_data_buf_addr_r_reg[4] ; wire req_priority_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire set_order_q; wire tail_r_24; wire use_addr; wire wait_for_maint_r_18; wire wait_for_maint_r_lcl_reg_0; wire wait_for_maint_r_lcl_reg_1; LUT6 #( .INIT(64'hFFFFFFFF0404FF04)) act_wait_r_lcl_i_1__2 (.I0(\ras_timer_r_reg[0] ), .I1(act_wait_r_lcl_reg_0), .I2(\grant_r_reg[1]_1 ), .I3(act_wait_r_lcl_reg), .I4(\q_entry_r_reg[0]_0 ), .I5(bm_end_r1_reg_5), .O(act_wait_ns)); LUT6 #( .INIT(64'h00000000F4F4FFF4)) act_wait_r_lcl_i_2__2 (.I0(pre_passing_open_bank_r_reg_0), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]), .I4(pre_passing_open_bank_r_reg_1), .I5(\ras_timer_r_reg[0]_1 ), .O(\ras_timer_r_reg[0] )); FDRE auto_pre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(auto_pre_r_lcl_reg_0), .Q(\rp_timer.rp_timer_r_reg[1] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \compute_tail.tail_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_0), .Q(tail_r_24), .R(SR)); LUT6 #( .INIT(64'hE0E0E0EEE0EEE0EE)) demand_priority_r_i_3__0 (.I0(req_priority_r), .I1(q_has_priority_4), .I2(rd_wr_r_lcl_reg_0), .I3(order_q_r[1]), .I4(order_q_r[0]), .I5(req_wr_r_lcl_reg), .O(demand_priority_r_reg)); LUT5 #( .INIT(32'hFFDFFFFF)) \grant_r[1]_i_4__1 (.I0(ras_timer_zero_r), .I1(\req_data_buf_addr_r_reg[4] ), .I2(act_wait_r_lcl_reg_0), .I3(wait_for_maint_r_18), .I4(wait_for_maint_r_lcl_reg_0), .O(\grant_r_reg[1] )); FDRE head_r_lcl_reg (.C(CLK), .CE(1'b1), .D(head_r_lcl_reg_1), .Q(wait_for_maint_r_lcl_reg_0), .R(rstdiv0_sync_r1_reg_rep__0)); LUT5 #( .INIT(32'h55151515)) i___36_i_1 (.I0(pre_passing_open_bank_r), .I1(\grant_r_reg[1]_0 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg_0), .I4(req_wr_r_lcl_reg_0), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000FD555555)) i___40_i_1 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(periodic_rd_ack_r_lcl_reg), .I2(use_addr), .I3(accept_internal_r_reg), .I4(wait_for_maint_r_lcl_reg_0), .I5(req_wr_r_lcl_reg_1), .O(rb_hit_busy_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1067" *) LUT3 #( .INIT(8'hFB)) i___56_i_1 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(q_entry_r[0]), .I2(q_entry_r[1]), .O(\ras_timer_r_reg[0]_1 )); LUT5 #( .INIT(32'h55151515)) i___5_i_1 (.I0(bm_end_r1_reg), .I1(\grant_r_reg[1]_0 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg_0), .I4(req_wr_r_lcl_reg_0), .O(\q_entry_r_reg[0]_0 )); LUT6 #( .INIT(64'h00FF000014141414)) i___6_i_1 (.I0(rb_hit_busy_r_reg_0), .I1(\q_entry_r_reg[0]_1 ), .I2(rb_hit_busy_r_reg_1), .I3(q_entry_r[1]), .I4(q_entry_r[0]), .I5(accept_r_reg), .O(head_r_lcl_reg_0)); LUT5 #( .INIT(32'hFFC5FFFF)) i___6_i_2 (.I0(\q_entry_r_reg[0]_1 ), .I1(periodic_rd_ack_r_lcl_reg_0), .I2(\req_data_buf_addr_r_reg[4] ), .I3(periodic_rd_ack_r_lcl_reg_1), .I4(\q_entry_r_reg[0]_0 ), .O(\q_entry_r_reg[1]_1 )); LUT6 #( .INIT(64'hDD0DDD0D0000DD0D)) i___6_i_3 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]), .I1(pre_bm_end_r_reg_1), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]), .I3(pre_bm_end_r_reg_2), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]), .I5(pre_bm_end_r_reg_0), .O(\q_entry_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair1068" *) LUT1 #( .INIT(2'h1)) idle_r_lcl_i_1 (.I0(rb_hit_busy_r_reg), .O(E)); FDRE idle_r_lcl_reg (.C(CLK), .CE(1'b1), .D(E), .Q(\req_data_buf_addr_r_reg[4] ), .R(1'b0)); LUT6 #( .INIT(64'h553100305531CC30)) \order_q_r[0]_i_1__0 (.I0(ordered_r_lcl_reg_2), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg), .I4(set_order_q), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\order_q_r[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'hAAC200C0AAC2F0C0)) \order_q_r[1]_i_1__0 (.I0(ordered_r_lcl_reg_1), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg), .I4(set_order_q), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\order_q_r[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000800080000000)) \order_q_r[1]_i_2__0 (.I0(req_wr_r_lcl_reg_0), .I1(\req_data_buf_addr_r_reg[4] ), .I2(wait_for_maint_r_lcl_reg_0), .I3(accept_internal_r_reg), .I4(use_addr), .I5(periodic_rd_ack_r_lcl_reg), .O(set_order_q)); FDRE \order_q_r_reg[0] (.C(CLK), .CE(1'b1), .D(\order_q_r[0]_i_1__0_n_0 ), .Q(order_q_r[0]), .R(1'b0)); FDRE \order_q_r_reg[1] (.C(CLK), .CE(1'b1), .D(\order_q_r[1]_i_1__0_n_0 ), .Q(order_q_r[1]), .R(1'b0)); FDRE ordered_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_0), .Q(ordered_r), .R(1'b0)); FDRE pass_open_bank_r_lcl_reg (.C(CLK), .CE(1'b1), .D(pass_open_bank_ns), .Q(act_wait_r_lcl_reg), .R(1'b0)); FDRE pre_bm_end_r_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_ns), .Q(bm_end_r1_reg), .R(1'b0)); FDRE pre_passing_open_bank_r_reg (.C(CLK), .CE(1'b1), .D(pre_passing_open_bank_ns), .Q(pre_passing_open_bank_r), .R(1'b0)); LUT6 #( .INIT(64'h8BB8FFFF8BB80000)) \q_entry_r[0]_i_1__0 (.I0(\q_entry_r[0]_i_2__1_n_0 ), .I1(\q_entry_r_reg[0]_0 ), .I2(idle_r_lcl_reg_7), .I3(periodic_rd_ack_r_lcl_reg_0), .I4(\q_entry_r_reg[1]_1 ), .I5(q_entry_r[0]), .O(\q_entry_r[0]_i_1__0_n_0 )); LUT4 #( .INIT(16'h909F)) \q_entry_r[0]_i_2__1 (.I0(rb_hit_busy_r_reg_1), .I1(\q_entry_r_reg[0]_1 ), .I2(periodic_rd_ack_r_lcl_reg_1), .I3(q_entry_r[0]), .O(\q_entry_r[0]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1067" *) LUT3 #( .INIT(8'hB8)) \q_entry_r[1]_i_1__0 (.I0(q_entry_ns), .I1(\q_entry_r_reg[1]_1 ), .I2(q_entry_r[1]), .O(\q_entry_r[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8EE7E771E7717118)) \q_entry_r[1]_i_2__1 (.I0(\q_entry_r_reg[0]_0 ), .I1(pre_bm_end_r_reg_0), .I2(idle_r_lcl_reg_4), .I3(idle_r_lcl_reg_5), .I4(\req_data_buf_addr_r_reg[4] ), .I5(idle_r_lcl_reg_6), .O(\q_entry_r_reg[1]_0 )); LUT6 #( .INIT(64'hA9FFA900A900A9FF)) \q_entry_r[1]_i_3__1 (.I0(rb_hit_busy_r_reg_0), .I1(\q_entry_r_reg[0]_1 ), .I2(rb_hit_busy_r_reg_1), .I3(periodic_rd_ack_r_lcl_reg_1), .I4(q_entry_r[1]), .I5(q_entry_r[0]), .O(\q_entry_r_reg[1]_2 )); FDSE \q_entry_r_reg[0] (.C(CLK), .CE(1'b1), .D(\q_entry_r[0]_i_1__0_n_0 ), .Q(q_entry_r[0]), .S(SR)); FDRE \q_entry_r_reg[1] (.C(CLK), .CE(1'b1), .D(\q_entry_r[1]_i_1__0_n_0 ), .Q(q_entry_r[1]), .R(SR)); FDRE q_has_priority_r_reg (.C(CLK), .CE(1'b1), .D(q_has_priority_r_reg_0), .Q(q_has_priority_4), .R(1'b0)); FDRE q_has_rd_r_reg (.C(CLK), .CE(1'b1), .D(q_has_rd_r_reg_0), .Q(q_has_rd_3), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1066" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[0]_i_1__2 (.I0(\ras_timer_r[0]_i_2__1_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(\ras_timer_r_reg[1] ), .O(\ras_timer_r_reg[2] [0])); LUT6 #( .INIT(64'hB8BBB888B888B888)) \ras_timer_r[0]_i_2__1 (.I0(\ras_timer_r_reg[1]_0 ), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]), .I2(rd_wr_r_lcl_reg), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]), .I5(\ras_timer_r_reg[1]_1 ), .O(\ras_timer_r[0]_i_2__1_n_0 )); LUT3 #( .INIT(8'hC5)) \ras_timer_r[1]_i_1__2 (.I0(bm_end_r1_reg_0), .I1(\ras_timer_r[1]_i_3_n_0 ), .I2(\ras_timer_r_reg[0] ), .O(\ras_timer_r_reg[2] [1])); LUT6 #( .INIT(64'hBBBBB8888888B888)) \ras_timer_r[1]_i_3 (.I0(bm_end_r1_reg_1), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]), .I3(bm_end_r1_reg_2), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]), .I5(bm_end_r1_reg_3), .O(\ras_timer_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1066" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[2]_i_1__2 (.I0(\ras_timer_r[2]_i_2__1_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(\ras_timer_r_reg[2]_0 ), .O(\ras_timer_r_reg[2] [2])); LUT6 #( .INIT(64'hBBBBB8888888B888)) \ras_timer_r[2]_i_2__1 (.I0(bm_end_r1_reg_4), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]), .I3(\ras_timer_r_reg[2]_1 ), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]), .I5(\ras_timer_r_reg[2]_2 ), .O(\ras_timer_r[2]_i_2__1_n_0 )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .I2(idle_r_lcl_reg_1), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ), .I4(\q_entry_r_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .I2(idle_r_lcl_reg_2), .I3(Q), .I4(\q_entry_r_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(D)); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .I2(idle_r_lcl_reg_3), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ), .I4(\q_entry_r_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] )); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 [0]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 [1]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 [2]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1068" *) LUT2 #( .INIT(4'h2)) rb_hit_busy_r_i_1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .O(p_106_out)); LUT5 #( .INIT(32'h888A8A8A)) req_bank_rdy_r_i_1__1 (.I0(col_wait_r_reg), .I1(rd_wr_r_lcl_reg_0), .I2(order_q_r[1]), .I3(order_q_r[0]), .I4(req_wr_r_lcl_reg), .O(req_bank_rdy_ns)); FDRE wait_for_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(wait_for_maint_r_lcl_reg_1), .Q(wait_for_maint_r_18), .R(\maintenance_request.maint_req_r_lcl_reg )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_queue" *) module ddr3_if_mig_7series_v4_0_bank_queue__parameterized1 (\req_data_buf_addr_r_reg[4] , E, act_wait_r_lcl_reg, pre_bm_end_r_9, pre_passing_open_bank_r, q_has_rd_10, q_has_priority_11, wait_for_maint_r_19, tail_r_26, wait_for_maint_r_lcl_reg_0, \rp_timer.rp_timer_r_reg[1] , ordered_r, D, rb_hit_busy_r_reg, \q_entry_r_reg[1]_0 , \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 , \grant_r_reg[2] , \ras_timer_r_reg[2] , \ras_timer_r_reg[0] , order_q_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 , act_wait_ns, \q_entry_r_reg[1]_1 , \q_entry_r_reg[1]_2 , \q_entry_r_reg[0]_0 , head_r_lcl_reg_0, \q_entry_r_reg[1]_3 , p_67_out, \compute_tail.tail_r_lcl_reg_0 , \ras_timer_r_reg[0]_0 , granted_row_ns, granted_row_r_reg, CLK, pass_open_bank_ns, pre_bm_end_ns, pre_passing_open_bank_ns, q_has_rd_r_reg_0, q_has_priority_r_reg_0, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_1, SR, idle_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_1, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_0, \req_bank_r_lcl_reg[2] , idle_r_lcl_reg_1, Q, rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 , idle_r_lcl_reg_3, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 , \rtw_timer.rtw_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1] , rd_wr_r_lcl_reg, override_demand_r_reg, col_wait_r_reg, \ras_timer_r_reg[1] , bm_end_r1_reg, \ras_timer_r_reg[2]_0 , rd_wr_r_lcl_reg_0, req_wr_r_lcl_reg, rnk_config_valid_r_lcl_reg, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[1]_1 , rd_wr_r_lcl_reg_1, bm_end_r1_reg_0, bm_end_r1_reg_1, bm_end_r1_reg_2, \ras_timer_r_reg[2]_1 , bm_end_r1_reg_3, \ras_timer_r_reg[2]_2 , act_wait_r_lcl_reg_0, \grant_r_reg[2]_0 , bm_end_r1_reg_4, pre_passing_open_bank_r_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 , pre_passing_open_bank_r_reg_1, idle_r_lcl_reg_4, rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, periodic_rd_ack_r_lcl_reg, accept_r_reg, periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg_0, pre_bm_end_r_reg_1, pre_bm_end_r_reg_2, periodic_rd_ack_r_lcl_reg_1, use_addr, accept_internal_r_reg, req_wr_r_lcl_reg_0, req_wr_r_lcl_reg_1, \grant_r_reg[2]_1 , \grant_r_reg[1] , ras_timer_zero_r_reg, \grant_r_reg[3] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 , idle_r_lcl_reg_5, \q_entry_r_reg[1]_4 , idle_r_lcl_reg_6, ordered_r_lcl_reg_1, req_wr_r_lcl_reg_2, rstdiv0_sync_r1_reg_rep__21, ordered_r_lcl_reg_2); output \req_data_buf_addr_r_reg[4] ; output [0:0]E; output act_wait_r_lcl_reg; output pre_bm_end_r_9; output pre_passing_open_bank_r; output q_has_rd_10; output q_has_priority_11; output wait_for_maint_r_19; output tail_r_26; output wait_for_maint_r_lcl_reg_0; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]ordered_r; output [0:0]D; output rb_hit_busy_r_reg; output \q_entry_r_reg[1]_0 ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; output \grant_r_reg[2] ; output [2:0]\ras_timer_r_reg[2] ; output \ras_timer_r_reg[0] ; output [1:0]order_q_r; output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; output act_wait_ns; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[1]_2 ; output \q_entry_r_reg[0]_0 ; output head_r_lcl_reg_0; output \q_entry_r_reg[1]_3 ; output p_67_out; output \compute_tail.tail_r_lcl_reg_0 ; output \ras_timer_r_reg[0]_0 ; output granted_row_ns; output granted_row_r_reg; input CLK; input pass_open_bank_ns; input pre_bm_end_ns; input pre_passing_open_bank_ns; input q_has_rd_r_reg_0; input q_has_priority_r_reg_0; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_1; input [0:0]SR; input idle_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_1; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_0; input \req_bank_r_lcl_reg[2] ; input idle_r_lcl_reg_1; input [0:0]Q; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ; input idle_r_lcl_reg_3; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ; input \rtw_timer.rtw_cnt_r_reg[1] ; input \wtr_timer.wtr_cnt_r_reg[1] ; input rd_wr_r_lcl_reg; input override_demand_r_reg; input col_wait_r_reg; input \ras_timer_r_reg[1] ; input bm_end_r1_reg; input \ras_timer_r_reg[2]_0 ; input rd_wr_r_lcl_reg_0; input req_wr_r_lcl_reg; input rnk_config_valid_r_lcl_reg; input \ras_timer_r_reg[1]_0 ; input \ras_timer_r_reg[1]_1 ; input rd_wr_r_lcl_reg_1; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input \ras_timer_r_reg[2]_1 ; input bm_end_r1_reg_3; input \ras_timer_r_reg[2]_2 ; input act_wait_r_lcl_reg_0; input [0:0]\grant_r_reg[2]_0 ; input bm_end_r1_reg_4; input pre_passing_open_bank_r_reg_0; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; input pre_passing_open_bank_r_reg_1; input idle_r_lcl_reg_4; input rb_hit_busy_r_reg_0; input rb_hit_busy_r_reg_1; input periodic_rd_ack_r_lcl_reg; input accept_r_reg; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg_0; input pre_bm_end_r_reg_1; input pre_bm_end_r_reg_2; input periodic_rd_ack_r_lcl_reg_1; input use_addr; input accept_internal_r_reg; input req_wr_r_lcl_reg_0; input req_wr_r_lcl_reg_1; input [0:0]\grant_r_reg[2]_1 ; input \grant_r_reg[1] ; input ras_timer_zero_r_reg; input \grant_r_reg[3] ; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ; input idle_r_lcl_reg_5; input \q_entry_r_reg[1]_4 ; input idle_r_lcl_reg_6; input ordered_r_lcl_reg_1; input req_wr_r_lcl_reg_2; input rstdiv0_sync_r1_reg_rep__21; input ordered_r_lcl_reg_2; wire CLK; wire [0:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_r_reg; wire act_wait_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire col_wait_r_reg; wire \compute_tail.tail_r_lcl_reg_0 ; wire \grant_r[3]_i_9_n_0 ; wire \grant_r_reg[1] ; wire \grant_r_reg[2] ; wire [0:0]\grant_r_reg[2]_0 ; wire [0:0]\grant_r_reg[2]_1 ; wire \grant_r_reg[3] ; wire granted_row_ns; wire granted_row_r_reg; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire i___10_i_4_n_0; wire i___10_i_5_n_0; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire idle_r_lcl_reg_4; wire idle_r_lcl_reg_5; wire idle_r_lcl_reg_6; wire \maintenance_request.maint_req_r_lcl_reg ; wire [1:0]order_q_r; wire \order_q_r[0]_i_1__1_n_0 ; wire \order_q_r[1]_i_1__1_n_0 ; wire [0:0]ordered_r; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire ordered_r_lcl_reg_2; wire override_demand_r_reg; wire p_67_out; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire pre_bm_end_ns; wire pre_bm_end_r_9; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_bm_end_r_reg_2; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg_0; wire pre_passing_open_bank_r_reg_1; wire \q_entry_r[0]_i_1__1_n_0 ; wire \q_entry_r[0]_i_2_n_0 ; wire \q_entry_r[1]_i_1__1_n_0 ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire \q_entry_r_reg[1]_3 ; wire \q_entry_r_reg[1]_4 ; wire q_has_priority_11; wire q_has_priority_r_reg_0; wire q_has_rd_10; wire q_has_rd_r_reg_0; wire \ras_timer_r[0]_i_2__2_n_0 ; wire \ras_timer_r[1]_i_2__1_n_0 ; wire \ras_timer_r[2]_i_2__2_n_0 ; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire [2:0]\ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire \ras_timer_r_reg[2]_2 ; wire ras_timer_zero_r_reg; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire \req_bank_r_lcl_reg[2] ; wire \req_data_buf_addr_r_reg[4] ; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire req_wr_r_lcl_reg_2; wire rnk_config_valid_r_lcl_reg; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire set_order_q; wire tail_r_26; wire use_addr; wire wait_for_maint_r_19; wire wait_for_maint_r_lcl_reg_0; wire wait_for_maint_r_lcl_reg_1; wire \wtr_timer.wtr_cnt_r_reg[1] ; LUT6 #( .INIT(64'hFFFFFFFF0404FF04)) act_wait_r_lcl_i_1 (.I0(\ras_timer_r_reg[0] ), .I1(act_wait_r_lcl_reg_0), .I2(\grant_r_reg[2]_0 ), .I3(act_wait_r_lcl_reg), .I4(\q_entry_r_reg[1]_0 ), .I5(bm_end_r1_reg_4), .O(act_wait_ns)); LUT6 #( .INIT(64'h00000000F4F4FFF4)) act_wait_r_lcl_i_2 (.I0(pre_passing_open_bank_r_reg_0), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]), .I4(pre_passing_open_bank_r_reg_1), .I5(idle_r_lcl_reg_4), .O(\ras_timer_r_reg[0] )); LUT5 #( .INIT(32'h55151515)) act_wait_r_lcl_i_4__0 (.I0(pre_passing_open_bank_r), .I1(\grant_r_reg[2]_1 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg), .I4(req_wr_r_lcl_reg_1), .O(\ras_timer_r_reg[0]_0 )); FDRE auto_pre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(auto_pre_r_lcl_reg_0), .Q(\rp_timer.rp_timer_r_reg[1] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \compute_tail.tail_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_0), .Q(tail_r_26), .R(SR)); LUT2 #( .INIT(4'hB)) \grant_r[1]_i_2__0 (.I0(ras_timer_zero_r_reg), .I1(\grant_r_reg[3] ), .O(granted_row_r_reg)); LUT6 #( .INIT(64'h00000000000000CA)) \grant_r[3]_i_2 (.I0(\rtw_timer.rtw_cnt_r_reg[1] ), .I1(\wtr_timer.wtr_cnt_r_reg[1] ), .I2(rd_wr_r_lcl_reg), .I3(\grant_r[3]_i_9_n_0 ), .I4(override_demand_r_reg), .I5(col_wait_r_reg), .O(\grant_r_reg[2] )); LUT6 #( .INIT(64'hFFFFFFFF44544444)) \grant_r[3]_i_9 (.I0(rd_wr_r_lcl_reg), .I1(order_q_r[1]), .I2(order_q_r[0]), .I3(rd_wr_r_lcl_reg_0), .I4(req_wr_r_lcl_reg), .I5(rnk_config_valid_r_lcl_reg), .O(\grant_r[3]_i_9_n_0 )); LUT2 #( .INIT(4'hB)) granted_row_r_i_1 (.I0(granted_row_r_reg), .I1(\grant_r_reg[1] ), .O(granted_row_ns)); FDRE head_r_lcl_reg (.C(CLK), .CE(1'b1), .D(head_r_lcl_reg_1), .Q(wait_for_maint_r_lcl_reg_0), .R(rstdiv0_sync_r1_reg_rep__0)); LUT6 #( .INIT(64'hAA02AA32AA02AACE)) i___10_i_1 (.I0(i___10_i_4_n_0), .I1(i___10_i_5_n_0), .I2(\req_data_buf_addr_r_reg[4] ), .I3(accept_r_reg), .I4(rb_hit_busy_r_reg_0), .I5(rb_hit_busy_r_reg_1), .O(head_r_lcl_reg_0)); LUT5 #( .INIT(32'hFFC5FFFF)) i___10_i_3 (.I0(i___10_i_5_n_0), .I1(periodic_rd_ack_r_lcl_reg_0), .I2(\req_data_buf_addr_r_reg[4] ), .I3(periodic_rd_ack_r_lcl_reg), .I4(\q_entry_r_reg[1]_0 ), .O(\q_entry_r_reg[1]_3 )); LUT2 #( .INIT(4'h2)) i___10_i_4 (.I0(\q_entry_r_reg[0]_0 ), .I1(\q_entry_r_reg[1]_2 ), .O(i___10_i_4_n_0)); LUT6 #( .INIT(64'hDD0DDD0D0000DD0D)) i___10_i_5 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]), .I1(pre_bm_end_r_reg_0), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]), .I3(pre_bm_end_r_reg_1), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]), .I5(pre_bm_end_r_reg_2), .O(i___10_i_5_n_0)); LUT6 #( .INIT(64'h00000000FD555555)) i___50_i_1 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(periodic_rd_ack_r_lcl_reg_1), .I2(use_addr), .I3(accept_internal_r_reg), .I4(wait_for_maint_r_lcl_reg_0), .I5(req_wr_r_lcl_reg_0), .O(rb_hit_busy_r_reg)); LUT3 #( .INIT(8'h80)) i___5_i_3 (.I0(\q_entry_r_reg[1]_0 ), .I1(pre_bm_end_r_reg_1), .I2(pre_bm_end_r_reg_2), .O(\compute_tail.tail_r_lcl_reg_0 )); LUT5 #( .INIT(32'h55151515)) i___9_i_1 (.I0(pre_bm_end_r_9), .I1(\grant_r_reg[2]_1 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg), .I4(req_wr_r_lcl_reg_1), .O(\q_entry_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair1080" *) LUT1 #( .INIT(2'h1)) idle_r_lcl_i_1__0 (.I0(rb_hit_busy_r_reg), .O(E)); FDRE idle_r_lcl_reg (.C(CLK), .CE(1'b1), .D(E), .Q(\req_data_buf_addr_r_reg[4] ), .R(1'b0)); LUT6 #( .INIT(64'h553100305531CC30)) \order_q_r[0]_i_1__1 (.I0(ordered_r_lcl_reg_2), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg_2), .I4(set_order_q), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\order_q_r[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'hAAC200C0AAC2F0C0)) \order_q_r[1]_i_1__1 (.I0(ordered_r_lcl_reg_1), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg_2), .I4(set_order_q), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\order_q_r[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'h8000800080000000)) \order_q_r[1]_i_2__1 (.I0(req_wr_r_lcl_reg_1), .I1(\req_data_buf_addr_r_reg[4] ), .I2(wait_for_maint_r_lcl_reg_0), .I3(accept_internal_r_reg), .I4(use_addr), .I5(periodic_rd_ack_r_lcl_reg_1), .O(set_order_q)); FDRE \order_q_r_reg[0] (.C(CLK), .CE(1'b1), .D(\order_q_r[0]_i_1__1_n_0 ), .Q(order_q_r[0]), .R(1'b0)); FDRE \order_q_r_reg[1] (.C(CLK), .CE(1'b1), .D(\order_q_r[1]_i_1__1_n_0 ), .Q(order_q_r[1]), .R(1'b0)); FDRE ordered_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_0), .Q(ordered_r), .R(1'b0)); FDRE pass_open_bank_r_lcl_reg (.C(CLK), .CE(1'b1), .D(pass_open_bank_ns), .Q(act_wait_r_lcl_reg), .R(1'b0)); FDRE pre_bm_end_r_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_ns), .Q(pre_bm_end_r_9), .R(1'b0)); FDRE pre_passing_open_bank_r_reg (.C(CLK), .CE(1'b1), .D(pre_passing_open_bank_ns), .Q(pre_passing_open_bank_r), .R(1'b0)); LUT6 #( .INIT(64'hF704FFFFF7040000)) \q_entry_r[0]_i_1__1 (.I0(periodic_rd_ack_r_lcl_reg_0), .I1(idle_r_lcl_reg_6), .I2(\q_entry_r_reg[1]_0 ), .I3(\q_entry_r[0]_i_2_n_0 ), .I4(\q_entry_r_reg[1]_3 ), .I5(\q_entry_r_reg[0]_0 ), .O(\q_entry_r[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'h99FF0FFF99000F00)) \q_entry_r[0]_i_2 (.I0(rb_hit_busy_r_reg_1), .I1(i___10_i_5_n_0), .I2(\q_entry_r_reg[0]_0 ), .I3(\q_entry_r_reg[1]_0 ), .I4(periodic_rd_ack_r_lcl_reg), .I5(periodic_rd_ack_r_lcl_reg_0), .O(\q_entry_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \q_entry_r[1]_i_1__1 (.I0(idle_r_lcl_reg_5), .I1(periodic_rd_ack_r_lcl_reg_0), .I2(\q_entry_r_reg[1]_0 ), .I3(\q_entry_r_reg[1]_4 ), .I4(\q_entry_r_reg[1]_3 ), .I5(\q_entry_r_reg[1]_2 ), .O(\q_entry_r[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'h560056FF56FF5600)) \q_entry_r[1]_i_4 (.I0(rb_hit_busy_r_reg_0), .I1(i___10_i_5_n_0), .I2(rb_hit_busy_r_reg_1), .I3(periodic_rd_ack_r_lcl_reg), .I4(\q_entry_r_reg[1]_2 ), .I5(\q_entry_r_reg[0]_0 ), .O(\q_entry_r_reg[1]_1 )); FDRE \q_entry_r_reg[0] (.C(CLK), .CE(1'b1), .D(\q_entry_r[0]_i_1__1_n_0 ), .Q(\q_entry_r_reg[0]_0 ), .R(SR)); FDSE \q_entry_r_reg[1] (.C(CLK), .CE(1'b1), .D(\q_entry_r[1]_i_1__1_n_0 ), .Q(\q_entry_r_reg[1]_2 ), .S(SR)); FDRE q_has_priority_r_reg (.C(CLK), .CE(1'b1), .D(q_has_priority_r_reg_0), .Q(q_has_priority_11), .R(1'b0)); FDRE q_has_rd_r_reg (.C(CLK), .CE(1'b1), .D(q_has_rd_r_reg_0), .Q(q_has_rd_10), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1079" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[0]_i_1__1 (.I0(\ras_timer_r[0]_i_2__2_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(\ras_timer_r_reg[1] ), .O(\ras_timer_r_reg[2] [0])); LUT6 #( .INIT(64'hB8BBB888B888B888)) \ras_timer_r[0]_i_2__2 (.I0(\ras_timer_r_reg[1]_0 ), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]), .I2(\ras_timer_r_reg[1]_1 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]), .I5(rd_wr_r_lcl_reg_1), .O(\ras_timer_r[0]_i_2__2_n_0 )); LUT3 #( .INIT(8'hB8)) \ras_timer_r[1]_i_1 (.I0(\ras_timer_r[1]_i_2__1_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(bm_end_r1_reg), .O(\ras_timer_r_reg[2] [1])); LUT6 #( .INIT(64'h0000B888FFFFB888)) \ras_timer_r[1]_i_2__1 (.I0(bm_end_r1_reg_0), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]), .I3(bm_end_r1_reg_1), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]), .I5(bm_end_r1_reg_2), .O(\ras_timer_r[1]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1079" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[2]_i_1 (.I0(\ras_timer_r[2]_i_2__2_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(\ras_timer_r_reg[2]_0 ), .O(\ras_timer_r_reg[2] [2])); LUT6 #( .INIT(64'hB8B8BB88B8B88888)) \ras_timer_r[2]_i_2__2 (.I0(\ras_timer_r_reg[2]_1 ), .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]), .I2(bm_end_r1_reg_3), .I3(\ras_timer_r_reg[2]_2 ), .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]), .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]), .O(\ras_timer_r[2]_i_2__2_n_0 )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .I2(idle_r_lcl_reg_2), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ), .I4(\q_entry_r_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .I2(idle_r_lcl_reg_3), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ), .I4(\q_entry_r_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .I2(idle_r_lcl_reg_1), .I3(Q), .I4(\q_entry_r_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(D)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 [0]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 [1]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 [2]), .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1080" *) LUT2 #( .INIT(4'h2)) rb_hit_busy_r_i_1__0 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[2] ), .O(p_67_out)); FDRE wait_for_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(wait_for_maint_r_lcl_reg_1), .Q(wait_for_maint_r_19), .R(\maintenance_request.maint_req_r_lcl_reg )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_queue" *) module ddr3_if_mig_7series_v4_0_bank_queue__parameterized2 (\req_data_buf_addr_r_reg[4] , E, act_wait_r_lcl_reg, pre_bm_end_r_15, pre_passing_open_bank_r, q_has_rd_16, q_has_priority_17, wait_for_maint_r_20, tail_r_28, wait_for_maint_r_lcl_reg_0, \rp_timer.rp_timer_r_reg[1] , ordered_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , rb_hit_busy_r_reg, \q_entry_r_reg[1]_0 , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 , D, \ras_timer_r_reg[0] , Q, demand_priority_r_reg, order_q_r, req_bank_rdy_ns, act_wait_ns, \q_entry_r_reg[1]_1 , \q_entry_r_reg[0]_0 , head_r_lcl_reg_0, \q_entry_r_reg[1]_2 , p_28_out, \ras_timer_r_reg[0]_0 , \grant_r_reg[3] , CLK, pass_open_bank_ns, pre_bm_end_ns, pre_passing_open_bank_ns, q_has_rd_r_reg_0, q_has_priority_r_reg_0, \maintenance_request.maint_req_r_lcl_reg , wait_for_maint_r_lcl_reg_1, SR, idle_r_lcl_reg_0, rstdiv0_sync_r1_reg_rep__0, head_r_lcl_reg_1, auto_pre_r_lcl_reg_0, ordered_r_lcl_reg_0, \req_bank_r_lcl_reg[0] , idle_r_lcl_reg_1, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 , rstdiv0_sync_r1_reg_rep__20, idle_r_lcl_reg_2, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 , idle_r_lcl_reg_3, \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 , rd_wr_r_lcl_reg, \ras_timer_r_reg[1] , \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[1]_1 , bm_end_r1_reg, bm_end_r1_reg_0, bm_end_r1_reg_1, bm_end_r1_reg_2, \ras_timer_r_reg[2] , \ras_timer_r_reg[2]_0 , \ras_timer_r_reg[2]_1 , bm_end_r1_reg_3, req_priority_r, rd_wr_r_lcl_reg_0, req_wr_r_lcl_reg, col_wait_r_reg, act_wait_r_lcl_reg_0, \grant_r_reg[3]_0 , bm_end_r1_reg_4, pre_passing_open_bank_r_reg_0, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 , pre_passing_open_bank_r_reg_1, idle_r_lcl_reg_4, periodic_rd_ack_r_lcl_reg, idle_r_lcl_reg_5, rb_hit_busy_r, rb_hit_busy_r_reg_0, accept_r_reg, rb_hit_busy_r_reg_1, rb_hit_busy_r_reg_2, periodic_rd_ack_r_lcl_reg_0, pre_bm_end_r_reg_0, pre_bm_end_r_reg_1, pre_bm_end_r_reg_2, periodic_rd_ack_r_lcl_reg_1, use_addr, accept_internal_r_reg, req_wr_r_lcl_reg_0, \grant_r_reg[3]_1 , req_wr_r_lcl_reg_1, ras_timer_zero_r, \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 , idle_r_lcl_reg_6, pre_bm_end_r_reg_3, ordered_r_lcl_reg_1, idle_r_lcl_reg_7, rstdiv0_sync_r1_reg_rep__21, ordered_r_lcl_reg_2); output \req_data_buf_addr_r_reg[4] ; output [0:0]E; output act_wait_r_lcl_reg; output pre_bm_end_r_15; output pre_passing_open_bank_r; output q_has_rd_16; output q_has_priority_17; output wait_for_maint_r_20; output tail_r_28; output wait_for_maint_r_lcl_reg_0; output \rp_timer.rp_timer_r_reg[1] ; output [0:0]ordered_r; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; output rb_hit_busy_r_reg; output \q_entry_r_reg[1]_0 ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ; output [2:0]D; output \ras_timer_r_reg[0] ; output [2:0]Q; output demand_priority_r_reg; output [1:0]order_q_r; output req_bank_rdy_ns; output act_wait_ns; output \q_entry_r_reg[1]_1 ; output \q_entry_r_reg[0]_0 ; output head_r_lcl_reg_0; output \q_entry_r_reg[1]_2 ; output p_28_out; output \ras_timer_r_reg[0]_0 ; output \grant_r_reg[3] ; input CLK; input pass_open_bank_ns; input pre_bm_end_ns; input pre_passing_open_bank_ns; input q_has_rd_r_reg_0; input q_has_priority_r_reg_0; input \maintenance_request.maint_req_r_lcl_reg ; input wait_for_maint_r_lcl_reg_1; input [0:0]SR; input idle_r_lcl_reg_0; input rstdiv0_sync_r1_reg_rep__0; input head_r_lcl_reg_1; input auto_pre_r_lcl_reg_0; input ordered_r_lcl_reg_0; input \req_bank_r_lcl_reg[0] ; input idle_r_lcl_reg_1; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ; input rstdiv0_sync_r1_reg_rep__20; input idle_r_lcl_reg_2; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ; input idle_r_lcl_reg_3; input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ; input rd_wr_r_lcl_reg; input \ras_timer_r_reg[1] ; input \ras_timer_r_reg[1]_0 ; input \ras_timer_r_reg[1]_1 ; input bm_end_r1_reg; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input bm_end_r1_reg_2; input \ras_timer_r_reg[2] ; input \ras_timer_r_reg[2]_0 ; input \ras_timer_r_reg[2]_1 ; input bm_end_r1_reg_3; input req_priority_r; input rd_wr_r_lcl_reg_0; input req_wr_r_lcl_reg; input col_wait_r_reg; input act_wait_r_lcl_reg_0; input [0:0]\grant_r_reg[3]_0 ; input bm_end_r1_reg_4; input pre_passing_open_bank_r_reg_0; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; input pre_passing_open_bank_r_reg_1; input idle_r_lcl_reg_4; input periodic_rd_ack_r_lcl_reg; input idle_r_lcl_reg_5; input [2:0]rb_hit_busy_r; input rb_hit_busy_r_reg_0; input accept_r_reg; input rb_hit_busy_r_reg_1; input rb_hit_busy_r_reg_2; input periodic_rd_ack_r_lcl_reg_0; input pre_bm_end_r_reg_0; input pre_bm_end_r_reg_1; input pre_bm_end_r_reg_2; input periodic_rd_ack_r_lcl_reg_1; input use_addr; input accept_internal_r_reg; input req_wr_r_lcl_reg_0; input [0:0]\grant_r_reg[3]_1 ; input req_wr_r_lcl_reg_1; input ras_timer_zero_r; input [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ; input idle_r_lcl_reg_6; input pre_bm_end_r_reg_3; input ordered_r_lcl_reg_1; input idle_r_lcl_reg_7; input rstdiv0_sync_r1_reg_rep__21; input ordered_r_lcl_reg_2; wire CLK; wire [2:0]D; wire [0:0]E; wire [2:0]Q; wire [0:0]SR; wire accept_internal_r_reg; wire accept_r_reg; wire act_wait_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bm_end_r1_reg_3; wire bm_end_r1_reg_4; wire col_wait_r_reg; wire demand_priority_r_reg; wire \grant_r_reg[3] ; wire [0:0]\grant_r_reg[3]_0 ; wire [0:0]\grant_r_reg[3]_1 ; wire head_r_lcl_reg_0; wire head_r_lcl_reg_1; wire i___14_i_3_n_0; wire i___14_i_4_n_0; wire idle_r_lcl_reg_0; wire idle_r_lcl_reg_1; wire idle_r_lcl_reg_2; wire idle_r_lcl_reg_3; wire idle_r_lcl_reg_4; wire idle_r_lcl_reg_5; wire idle_r_lcl_reg_6; wire idle_r_lcl_reg_7; wire \maintenance_request.maint_req_r_lcl_reg ; wire [1:0]order_q_r; wire \order_q_r[0]_i_1__2_n_0 ; wire \order_q_r[1]_i_1__2_n_0 ; wire [0:0]ordered_r; wire ordered_r_lcl_reg_0; wire ordered_r_lcl_reg_1; wire ordered_r_lcl_reg_2; wire p_28_out; wire pass_open_bank_ns; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_ack_r_lcl_reg_0; wire periodic_rd_ack_r_lcl_reg_1; wire pre_bm_end_ns; wire pre_bm_end_r_15; wire pre_bm_end_r_reg_0; wire pre_bm_end_r_reg_1; wire pre_bm_end_r_reg_2; wire pre_bm_end_r_reg_3; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r; wire pre_passing_open_bank_r_reg_0; wire pre_passing_open_bank_r_reg_1; wire \q_entry_r[0]_i_1__2_n_0 ; wire \q_entry_r[0]_i_2__0_n_0 ; wire \q_entry_r[1]_i_1__2_n_0 ; wire \q_entry_r[1]_i_3__0_n_0 ; wire \q_entry_r[1]_i_4__0_n_0 ; wire \q_entry_r_reg[0]_0 ; wire \q_entry_r_reg[1]_0 ; wire \q_entry_r_reg[1]_1 ; wire \q_entry_r_reg[1]_2 ; wire q_has_priority_17; wire q_has_priority_r_reg_0; wire q_has_rd_16; wire q_has_rd_r_reg_0; wire \ras_timer_r[0]_i_2__0_n_0 ; wire \ras_timer_r[1]_i_2__0_n_0 ; wire \ras_timer_r[2]_i_2__0_n_0 ; wire \ras_timer_r_reg[0] ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1] ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[1]_1 ; wire \ras_timer_r_reg[2] ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire ras_timer_zero_r; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ; wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ; wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ; wire [2:0]rb_hit_busy_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire \req_bank_r_lcl_reg[0] ; wire req_bank_rdy_ns; wire \req_data_buf_addr_r_reg[4] ; wire req_priority_r; wire req_wr_r_lcl_reg; wire req_wr_r_lcl_reg_0; wire req_wr_r_lcl_reg_1; wire \rp_timer.rp_timer_r_reg[1] ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire tail_r_28; wire use_addr; wire wait_for_maint_r_20; wire wait_for_maint_r_lcl_reg_0; wire wait_for_maint_r_lcl_reg_1; LUT6 #( .INIT(64'hFFFFFFFF0404FF04)) act_wait_r_lcl_i_1__1 (.I0(\ras_timer_r_reg[0] ), .I1(act_wait_r_lcl_reg_0), .I2(\grant_r_reg[3]_0 ), .I3(act_wait_r_lcl_reg), .I4(\q_entry_r_reg[1]_0 ), .I5(bm_end_r1_reg_4), .O(act_wait_ns)); LUT6 #( .INIT(64'h00000000F4F4FFF4)) act_wait_r_lcl_i_2__1 (.I0(pre_passing_open_bank_r_reg_0), .I1(Q[2]), .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ), .I3(Q[1]), .I4(pre_passing_open_bank_r_reg_1), .I5(idle_r_lcl_reg_4), .O(\ras_timer_r_reg[0] )); FDRE auto_pre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(auto_pre_r_lcl_reg_0), .Q(\rp_timer.rp_timer_r_reg[1] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \compute_tail.tail_r_lcl_reg (.C(CLK), .CE(1'b1), .D(idle_r_lcl_reg_0), .Q(tail_r_28), .R(SR)); LUT6 #( .INIT(64'hE0E0E0EEE0EEE0EE)) demand_priority_r_i_2 (.I0(req_priority_r), .I1(q_has_priority_17), .I2(rd_wr_r_lcl_reg_0), .I3(order_q_r[1]), .I4(order_q_r[0]), .I5(req_wr_r_lcl_reg), .O(demand_priority_r_reg)); LUT5 #( .INIT(32'hFFDFFFFF)) \grant_r[3]_i_7__0 (.I0(ras_timer_zero_r), .I1(\req_data_buf_addr_r_reg[4] ), .I2(act_wait_r_lcl_reg_0), .I3(wait_for_maint_r_20), .I4(wait_for_maint_r_lcl_reg_0), .O(\grant_r_reg[3] )); FDRE head_r_lcl_reg (.C(CLK), .CE(1'b1), .D(head_r_lcl_reg_1), .Q(wait_for_maint_r_lcl_reg_0), .R(rstdiv0_sync_r1_reg_rep__0)); LUT5 #( .INIT(32'h55151515)) i___13_i_1 (.I0(pre_bm_end_r_15), .I1(\grant_r_reg[3]_1 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg_0), .I4(req_wr_r_lcl_reg_1), .O(\q_entry_r_reg[1]_0 )); LUT6 #( .INIT(64'hAA02AA32AA02AACE)) i___14_i_1 (.I0(i___14_i_3_n_0), .I1(i___14_i_4_n_0), .I2(\req_data_buf_addr_r_reg[4] ), .I3(accept_r_reg), .I4(rb_hit_busy_r_reg_1), .I5(rb_hit_busy_r_reg_2), .O(head_r_lcl_reg_0)); LUT5 #( .INIT(32'hFFFFD1FF)) i___14_i_2 (.I0(i___14_i_4_n_0), .I1(\req_data_buf_addr_r_reg[4] ), .I2(periodic_rd_ack_r_lcl_reg_0), .I3(\q_entry_r_reg[1]_0 ), .I4(periodic_rd_ack_r_lcl_reg), .O(\q_entry_r_reg[1]_2 )); LUT2 #( .INIT(4'h2)) i___14_i_3 (.I0(\q_entry_r_reg[0]_0 ), .I1(\q_entry_r_reg[1]_1 ), .O(i___14_i_3_n_0)); LUT6 #( .INIT(64'hDD0DDD0D0000DD0D)) i___14_i_4 (.I0(Q[0]), .I1(pre_bm_end_r_reg_0), .I2(Q[2]), .I3(pre_bm_end_r_reg_1), .I4(Q[1]), .I5(pre_bm_end_r_reg_2), .O(i___14_i_4_n_0)); LUT6 #( .INIT(64'h00000000FD555555)) i___53_i_1 (.I0(\req_data_buf_addr_r_reg[4] ), .I1(periodic_rd_ack_r_lcl_reg_1), .I2(use_addr), .I3(accept_internal_r_reg), .I4(wait_for_maint_r_lcl_reg_0), .I5(req_wr_r_lcl_reg_0), .O(rb_hit_busy_r_reg)); LUT5 #( .INIT(32'h55151515)) i___56_i_2 (.I0(pre_passing_open_bank_r), .I1(\grant_r_reg[3]_1 ), .I2(act_wait_r_lcl_reg), .I3(rd_wr_r_lcl_reg_0), .I4(req_wr_r_lcl_reg_1), .O(\ras_timer_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair1089" *) LUT1 #( .INIT(2'h1)) idle_r_lcl_i_1__1 (.I0(rb_hit_busy_r_reg), .O(E)); FDRE idle_r_lcl_reg (.C(CLK), .CE(1'b1), .D(E), .Q(\req_data_buf_addr_r_reg[4] ), .R(1'b0)); LUT6 #( .INIT(64'h553100305531CC30)) \order_q_r[0]_i_1__2 (.I0(ordered_r_lcl_reg_2), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg), .I4(idle_r_lcl_reg_7), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\order_q_r[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'hAAC200C0AAC2F0C0)) \order_q_r[1]_i_1__2 (.I0(ordered_r_lcl_reg_1), .I1(order_q_r[0]), .I2(order_q_r[1]), .I3(req_wr_r_lcl_reg), .I4(idle_r_lcl_reg_7), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\order_q_r[1]_i_1__2_n_0 )); FDRE \order_q_r_reg[0] (.C(CLK), .CE(1'b1), .D(\order_q_r[0]_i_1__2_n_0 ), .Q(order_q_r[0]), .R(1'b0)); FDRE \order_q_r_reg[1] (.C(CLK), .CE(1'b1), .D(\order_q_r[1]_i_1__2_n_0 ), .Q(order_q_r[1]), .R(1'b0)); FDRE ordered_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ordered_r_lcl_reg_0), .Q(ordered_r), .R(1'b0)); FDRE pass_open_bank_r_lcl_reg (.C(CLK), .CE(1'b1), .D(pass_open_bank_ns), .Q(act_wait_r_lcl_reg), .R(1'b0)); FDRE pre_bm_end_r_reg (.C(CLK), .CE(1'b1), .D(pre_bm_end_ns), .Q(pre_bm_end_r_15), .R(1'b0)); FDRE pre_passing_open_bank_r_reg (.C(CLK), .CE(1'b1), .D(pre_passing_open_bank_ns), .Q(pre_passing_open_bank_r), .R(1'b0)); LUT6 #( .INIT(64'hF2D1FFFFF2D10000)) \q_entry_r[0]_i_1__2 (.I0(periodic_rd_ack_r_lcl_reg_0), .I1(\q_entry_r_reg[1]_0 ), .I2(\q_entry_r[0]_i_2__0_n_0 ), .I3(pre_bm_end_r_reg_3), .I4(\q_entry_r_reg[1]_2 ), .I5(\q_entry_r_reg[0]_0 ), .O(\q_entry_r[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h909000F0)) \q_entry_r[0]_i_2__0 (.I0(rb_hit_busy_r_reg_2), .I1(i___14_i_4_n_0), .I2(\q_entry_r_reg[1]_0 ), .I3(\q_entry_r_reg[0]_0 ), .I4(periodic_rd_ack_r_lcl_reg), .O(\q_entry_r[0]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFB08FFFFFB080000)) \q_entry_r[1]_i_1__2 (.I0(idle_r_lcl_reg_6), .I1(periodic_rd_ack_r_lcl_reg_0), .I2(\q_entry_r_reg[1]_0 ), .I3(\q_entry_r[1]_i_3__0_n_0 ), .I4(\q_entry_r_reg[1]_2 ), .I5(\q_entry_r_reg[1]_1 ), .O(\q_entry_r[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hB88BFFFFB88B0000)) \q_entry_r[1]_i_3__0 (.I0(\q_entry_r[1]_i_4__0_n_0 ), .I1(periodic_rd_ack_r_lcl_reg), .I2(\q_entry_r_reg[1]_1 ), .I3(\q_entry_r_reg[0]_0 ), .I4(\q_entry_r_reg[1]_0 ), .I5(idle_r_lcl_reg_5), .O(\q_entry_r[1]_i_3__0_n_0 )); LUT5 #( .INIT(32'h7EE8E881)) \q_entry_r[1]_i_4__0 (.I0(i___14_i_4_n_0), .I1(rb_hit_busy_r[0]), .I2(rb_hit_busy_r[1]), .I3(rb_hit_busy_r[2]), .I4(rb_hit_busy_r_reg_0), .O(\q_entry_r[1]_i_4__0_n_0 )); FDSE \q_entry_r_reg[0] (.C(CLK), .CE(1'b1), .D(\q_entry_r[0]_i_1__2_n_0 ), .Q(\q_entry_r_reg[0]_0 ), .S(SR)); FDSE \q_entry_r_reg[1] (.C(CLK), .CE(1'b1), .D(\q_entry_r[1]_i_1__2_n_0 ), .Q(\q_entry_r_reg[1]_1 ), .S(SR)); FDRE q_has_priority_r_reg (.C(CLK), .CE(1'b1), .D(q_has_priority_r_reg_0), .Q(q_has_priority_17), .R(1'b0)); FDRE q_has_rd_r_reg (.C(CLK), .CE(1'b1), .D(q_has_rd_r_reg_0), .Q(q_has_rd_16), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1088" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[0]_i_1__0 (.I0(\ras_timer_r[0]_i_2__0_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(rd_wr_r_lcl_reg), .O(D[0])); LUT6 #( .INIT(64'hB8BBB888B888B888)) \ras_timer_r[0]_i_2__0 (.I0(\ras_timer_r_reg[1] ), .I1(Q[2]), .I2(\ras_timer_r_reg[1]_0 ), .I3(Q[1]), .I4(Q[0]), .I5(\ras_timer_r_reg[1]_1 ), .O(\ras_timer_r[0]_i_2__0_n_0 )); LUT3 #( .INIT(8'hB8)) \ras_timer_r[1]_i_1__1 (.I0(\ras_timer_r[1]_i_2__0_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(bm_end_r1_reg), .O(D[1])); LUT6 #( .INIT(64'h8BBB8B888B888B88)) \ras_timer_r[1]_i_2__0 (.I0(bm_end_r1_reg_0), .I1(Q[2]), .I2(bm_end_r1_reg_1), .I3(Q[1]), .I4(Q[0]), .I5(bm_end_r1_reg_2), .O(\ras_timer_r[1]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1088" *) LUT3 #( .INIT(8'hB8)) \ras_timer_r[2]_i_1__1 (.I0(\ras_timer_r[2]_i_2__0_n_0 ), .I1(\ras_timer_r_reg[0] ), .I2(\ras_timer_r_reg[2] ), .O(D[2])); LUT6 #( .INIT(64'hB8BBB888B888B888)) \ras_timer_r[2]_i_2__0 (.I0(\ras_timer_r_reg[2]_0 ), .I1(Q[2]), .I2(\ras_timer_r_reg[2]_1 ), .I3(Q[1]), .I4(Q[0]), .I5(bm_end_r1_reg_3), .O(\ras_timer_r[2]_i_2__0_n_0 )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .I2(idle_r_lcl_reg_1), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ), .I4(\q_entry_r_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .I2(idle_r_lcl_reg_2), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ), .I4(\q_entry_r_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 )); LUT6 #( .INIT(64'h00000000F2020000)) \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .I2(idle_r_lcl_reg_3), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ), .I4(\q_entry_r_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 )); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (.C(CLK), .CE(1'b1), .D(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]), .Q(Q[2]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1089" *) LUT2 #( .INIT(4'h2)) rb_hit_busy_r_i_1__1 (.I0(rb_hit_busy_r_reg), .I1(\req_bank_r_lcl_reg[0] ), .O(p_28_out)); LUT5 #( .INIT(32'h888A8A8A)) req_bank_rdy_r_i_1 (.I0(col_wait_r_reg), .I1(rd_wr_r_lcl_reg_0), .I2(order_q_r[1]), .I3(order_q_r[0]), .I4(req_wr_r_lcl_reg), .O(req_bank_rdy_ns)); FDRE wait_for_maint_r_lcl_reg (.C(CLK), .CE(1'b1), .D(wait_for_maint_r_lcl_reg_1), .Q(wait_for_maint_r_20), .R(\maintenance_request.maint_req_r_lcl_reg )); endmodule module ddr3_if_mig_7series_v4_0_bank_state (bm_end_r1, \act_this_rank_r_reg[0]_0 , \rp_timer.rp_timer_r_reg[1]_0 , pre_wait_r, act_this_rank_r, demand_priority_r_reg_0, demanded_prior_r_reg_0, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, \starve_limit_cntr_r_reg[2]_0 , pre_bm_end_ns, pre_passing_open_bank_ns, \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[2]_0 , \pre_4_1_1T_arb.granted_pre_r_reg , \ras_timer_r_reg[0]_0 , auto_pre_r_lcl_reg, \rnk_config_strobe_r_reg[0] , demanded_prior_r_reg_1, p_130_out, CLK, act_wait_ns, req_bank_rdy_ns, SR, ofs_rdy_r0, start_wtp_timer0, rd_wr_r_lcl_reg, req_priority_r_reg, idle_r_lcl_reg, \grant_r_reg[2] , \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] , pass_open_bank_ns, rtp_timer_ns1, rd_wr_r_lcl_reg_0, bm_end_r1_reg_0, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[0] , auto_pre_r_lcl_reg_0, \grant_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__22, accept_r_reg, tail_r, demand_priority_r_reg_1, demanded_prior_r_reg_2, demanded_prior_r_reg_3, req_wr_r_lcl_reg, q_has_rd, granted_col_r_reg, D, pass_open_bank_r_lcl_reg, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__0); output bm_end_r1; output \act_this_rank_r_reg[0]_0 ; output \rp_timer.rp_timer_r_reg[1]_0 ; output pre_wait_r; output [0:0]act_this_rank_r; output demand_priority_r_reg_0; output demanded_prior_r_reg_0; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output \starve_limit_cntr_r_reg[2]_0 ; output pre_bm_end_ns; output pre_passing_open_bank_ns; output \ras_timer_r_reg[1]_0 ; output \ras_timer_r_reg[2]_0 ; output \pre_4_1_1T_arb.granted_pre_r_reg ; output \ras_timer_r_reg[0]_0 ; output auto_pre_r_lcl_reg; output \rnk_config_strobe_r_reg[0] ; output demanded_prior_r_reg_1; input p_130_out; input CLK; input act_wait_ns; input req_bank_rdy_ns; input [0:0]SR; input ofs_rdy_r0; input start_wtp_timer0; input rd_wr_r_lcl_reg; input req_priority_r_reg; input idle_r_lcl_reg; input [1:0]\grant_r_reg[2] ; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; input pass_open_bank_ns; input rtp_timer_ns1; input rd_wr_r_lcl_reg_0; input bm_end_r1_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [0:0]\grant_r_reg[0] ; input auto_pre_r_lcl_reg_0; input [0:0]\grant_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__22; input accept_r_reg; input tail_r; input demand_priority_r_reg_1; input demanded_prior_r_reg_2; input demanded_prior_r_reg_3; input req_wr_r_lcl_reg; input q_has_rd; input granted_col_r_reg; input [2:0]D; input pass_open_bank_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__0; wire CLK; wire [2:0]D; wire [0:0]SR; wire accept_r_reg; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0]_0 ; wire act_wait_ns; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire bm_end_r1; wire bm_end_r1_reg_0; wire col_wait_r_i_1__0_n_0; wire demand_priority_ns; wire demand_priority_r_i_2__0_n_0; wire demand_priority_r_i_4__0_n_0; wire demand_priority_r_i_5_n_0; wire demand_priority_r_reg_0; wire demand_priority_r_reg_1; wire demanded_prior_ns; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire demanded_prior_r_reg_2; wire demanded_prior_r_reg_3; wire [0:0]\grant_r_reg[0] ; wire [0:0]\grant_r_reg[0]_0 ; wire [1:0]\grant_r_reg[2] ; wire granted_col_r_reg; wire idle_r_lcl_reg; wire ofs_rdy_r; wire ofs_rdy_r0; wire p_130_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire pre_bm_end_ns; wire pre_passing_open_bank_ns; wire pre_wait_ns; wire pre_wait_r; wire q_has_rd; wire [2:0]ras_timer_r; wire \ras_timer_r[2]_i_4__1_n_0 ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2]_0 ; wire ras_timer_zero_ns; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ; wire rcd_active_r; wire \rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ; wire [0:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_ns; wire req_bank_rdy_r; wire req_priority_r_reg; wire req_wr_r_lcl_reg; wire \rnk_config_strobe_r_reg[0] ; wire \rp_timer.rp_timer_r[0]_i_1_n_0 ; wire \rp_timer.rp_timer_r[1]_i_1_n_0 ; wire \rp_timer.rp_timer_r_reg[1]_0 ; wire [0:0]rp_timer_ns; wire [1:0]rp_timer_r; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1; wire [1:0]rtp_timer_r; wire \rtp_timer_r[0]_i_1_n_0 ; wire \rtp_timer_r[1]_i_1_n_0 ; wire start_pre; wire start_wtp_timer0; wire [2:0]starve_limit_cntr_r; wire starve_limit_cntr_r0; wire \starve_limit_cntr_r[0]_i_1_n_0 ; wire \starve_limit_cntr_r[1]_i_1_n_0 ; wire \starve_limit_cntr_r[2]_i_1_n_0 ; wire \starve_limit_cntr_r_reg[2]_0 ; wire tail_r; wire [0:0]wr_this_rank_r; FDRE \act_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(\act_this_rank_r_reg[0]_0 ), .Q(act_this_rank_r), .R(1'b0)); FDRE act_wait_r_lcl_reg (.C(CLK), .CE(1'b1), .D(act_wait_ns), .Q(\act_this_rank_r_reg[0]_0 ), .R(1'b0)); FDRE bm_end_r1_reg (.C(CLK), .CE(1'b1), .D(p_130_out), .Q(bm_end_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1061" *) LUT4 #( .INIT(16'hFFBA)) col_wait_r_i_1__0 (.I0(rcd_active_r), .I1(\grant_r_reg[2] [0]), .I2(\starve_limit_cntr_r_reg[2]_0 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .O(col_wait_r_i_1__0_n_0)); FDRE col_wait_r_reg (.C(CLK), .CE(1'b1), .D(col_wait_r_i_1__0_n_0), .Q(\starve_limit_cntr_r_reg[2]_0 ), .R(SR)); LUT5 #( .INIT(32'h0000FB00)) demand_priority_r_i_1__2 (.I0(demand_priority_r_reg_0), .I1(demand_priority_r_i_2__0_n_0), .I2(req_priority_r_reg), .I3(idle_r_lcl_reg), .I4(demand_priority_r_i_4__0_n_0), .O(demand_priority_ns)); LUT6 #( .INIT(64'hFF2FFFFFFFFFFFFF)) demand_priority_r_i_2__0 (.I0(req_wr_r_lcl_reg), .I1(q_has_rd), .I2(req_bank_rdy_r), .I3(\grant_r_reg[2] [0]), .I4(granted_col_r_reg), .I5(demand_priority_r_i_5_n_0), .O(demand_priority_r_i_2__0_n_0)); (* SOFT_HLUTNM = "soft_lutpair1061" *) LUT4 #( .INIT(16'h0051)) demand_priority_r_i_4__0 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ), .I1(\starve_limit_cntr_r_reg[2]_0 ), .I2(\grant_r_reg[2] [0]), .I3(rcd_active_r), .O(demand_priority_r_i_4__0_n_0)); (* SOFT_HLUTNM = "soft_lutpair1063" *) LUT3 #( .INIT(8'h80)) demand_priority_r_i_5 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[0]), .O(demand_priority_r_i_5_n_0)); FDRE demand_priority_r_reg (.C(CLK), .CE(1'b1), .D(demand_priority_ns), .Q(demand_priority_r_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hDDDDDDDD00000D00)) demanded_prior_r_i_1__1 (.I0(demand_priority_r_reg_0), .I1(demanded_prior_r_reg_0), .I2(\grant_r_reg[2] [1]), .I3(demand_priority_r_reg_1), .I4(demanded_prior_r_reg_2), .I5(demanded_prior_r_reg_3), .O(demanded_prior_ns)); FDRE demanded_prior_r_reg (.C(CLK), .CE(1'b1), .D(demanded_prior_ns), .Q(demanded_prior_r_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1058" *) LUT4 #( .INIT(16'h1000)) \grant_r[1]_i_3__1 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[0]_0 ), .I2(pre_wait_r), .I3(\rp_timer.rp_timer_r_reg[1]_0 ), .O(\pre_4_1_1T_arb.granted_pre_r_reg )); LUT6 #( .INIT(64'h8888888880888080)) i___2_i_1 (.I0(accept_r_reg), .I1(tail_r), .I2(rcd_active_r), .I3(\grant_r_reg[2] [0]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .I5(\act_this_rank_r_reg[0]_0 ), .O(auto_pre_r_lcl_reg)); LUT5 #( .INIT(32'hBBBBBABB)) i___34_i_3 (.I0(demand_priority_r_reg_1), .I1(demanded_prior_r_reg_3), .I2(\grant_r_reg[2] [0]), .I3(demand_priority_r_reg_0), .I4(demanded_prior_r_reg_0), .O(\rnk_config_strobe_r_reg[0] )); LUT6 #( .INIT(64'h0404040404FF0404)) i___90_i_1 (.I0(demanded_prior_r_reg_0), .I1(demand_priority_r_reg_0), .I2(\grant_r_reg[2] [0]), .I3(demanded_prior_r_reg_2), .I4(demand_priority_r_reg_1), .I5(\grant_r_reg[2] [1]), .O(demanded_prior_r_reg_1)); FDRE #( .INIT(1'b0)) ofs_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ofs_rdy_r0), .Q(ofs_rdy_r), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair1062" *) LUT3 #( .INIT(8'hBA)) pre_bm_end_r_i_1__0 (.I0(pre_passing_open_bank_ns), .I1(rp_timer_r[1]), .I2(rp_timer_r[0]), .O(pre_bm_end_ns)); LUT6 #( .INIT(64'hAAA8AAAAAAA8AAA8)) pre_passing_open_bank_r_i_1__0 (.I0(pass_open_bank_ns), .I1(\grant_r_reg[2] [0]), .I2(rtp_timer_r[1]), .I3(rtp_timer_r[0]), .I4(\rp_timer.rp_timer_r_reg[1]_0 ), .I5(pre_wait_r), .O(pre_passing_open_bank_ns)); LUT6 #( .INIT(64'h0404040404550404)) pre_wait_r_i_1__0 (.I0(pass_open_bank_ns), .I1(pre_wait_r), .I2(rp_timer_ns), .I3(rtp_timer_ns1), .I4(rtp_timer_r[0]), .I5(rtp_timer_r[1]), .O(pre_wait_ns)); (* SOFT_HLUTNM = "soft_lutpair1058" *) LUT5 #( .INIT(32'hEAEAEAAA)) pre_wait_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\rp_timer.rp_timer_r_reg[1]_0 ), .I2(pre_wait_r), .I3(\grant_r_reg[0]_0 ), .I4(auto_pre_r_lcl_reg_0), .O(rp_timer_ns)); FDRE pre_wait_r_reg (.C(CLK), .CE(1'b1), .D(pre_wait_ns), .Q(pre_wait_r), .R(1'b0)); LUT6 #( .INIT(64'h000000000E0E000E)) \ras_timer_r[0]_i_3__1 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(\grant_r_reg[2] [0]), .I4(rd_wr_r_lcl_reg), .I5(bm_end_r1_reg_0), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'h1100001011111111)) \ras_timer_r[1]_i_3__2 (.I0(bm_end_r1), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\ras_timer_r[2]_i_4__1_n_0 ), .O(\ras_timer_r_reg[1]_0 )); LUT6 #( .INIT(64'h1010100011111111)) \ras_timer_r[2]_i_3__1 (.I0(bm_end_r1), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\ras_timer_r[2]_i_4__1_n_0 ), .O(\ras_timer_r_reg[2]_0 )); LUT6 #( .INIT(64'hDDDDDDD0DDDDDDDD)) \ras_timer_r[2]_i_4__1 (.I0(\grant_r_reg[2] [0]), .I1(rd_wr_r_lcl_reg), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ), .O(\ras_timer_r[2]_i_4__1_n_0 )); FDRE \ras_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(ras_timer_r[0]), .R(1'b0)); FDRE \ras_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(ras_timer_r[1]), .R(1'b0)); FDRE \ras_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(ras_timer_r[2]), .R(1'b0)); LUT6 #( .INIT(64'hFFFF1000FFFF1100)) ras_timer_zero_r_i_1__1 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(rd_wr_r_lcl_reg_0), .I4(bm_end_r1_reg_0), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ), .O(ras_timer_zero_ns)); FDRE ras_timer_zero_r_reg (.C(CLK), .CE(1'b1), .D(ras_timer_zero_ns), .Q(\rp_timer.rp_timer_r_reg[1]_0 ), .R(1'b0)); LUT2 #( .INIT(4'h8)) \rcd_timer_gt_2.rcd_timer_r[0]_i_1 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[0] ), .O(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rcd_timer_gt_2.rcd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ), .Q(rcd_active_r), .R(SR)); FDRE \rd_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_wr_r_lcl_reg), .Q(rd_this_rank_r), .R(1'b0)); FDRE req_bank_rdy_r_reg (.C(CLK), .CE(1'b1), .D(req_bank_rdy_ns), .Q(req_bank_rdy_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1062" *) LUT4 #( .INIT(16'h0004)) \rp_timer.rp_timer_r[0]_i_1 (.I0(rp_timer_r[0]), .I1(rp_timer_r[1]), .I2(start_pre), .I3(rstdiv0_sync_r1_reg_rep__20), .O(\rp_timer.rp_timer_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'hE000)) \rp_timer.rp_timer_r[0]_i_2 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[0]_0 ), .I2(pre_wait_r), .I3(\rp_timer.rp_timer_r_reg[1]_0 ), .O(start_pre)); LUT6 #( .INIT(64'hF888F888F8888888)) \rp_timer.rp_timer_r[1]_i_1 (.I0(rp_timer_r[1]), .I1(rp_timer_r[0]), .I2(\rp_timer.rp_timer_r_reg[1]_0 ), .I3(pre_wait_r), .I4(\grant_r_reg[0]_0 ), .I5(auto_pre_r_lcl_reg_0), .O(\rp_timer.rp_timer_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[0]_i_1_n_0 ), .Q(rp_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[1]_i_1_n_0 ), .Q(rp_timer_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); (* SOFT_HLUTNM = "soft_lutpair1059" *) LUT4 #( .INIT(16'h0002)) \rtp_timer_r[0]_i_1 (.I0(rtp_timer_r[1]), .I1(rtp_timer_r[0]), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(pass_open_bank_r_lcl_reg), .O(\rtp_timer_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1059" *) LUT5 #( .INIT(32'h000000C2)) \rtp_timer_r[1]_i_1 (.I0(\grant_r_reg[2] [0]), .I1(rtp_timer_r[1]), .I2(rtp_timer_r[0]), .I3(pass_open_bank_r_lcl_reg), .I4(rstdiv0_sync_r1_reg_rep__20), .O(\rtp_timer_r[1]_i_1_n_0 )); FDRE \rtp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[0]_i_1_n_0 ), .Q(rtp_timer_r[0]), .R(1'b0)); FDRE \rtp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[1]_i_1_n_0 ), .Q(rtp_timer_r[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1063" *) LUT3 #( .INIT(8'h60)) \starve_limit_cntr_r[0]_i_1 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r0), .I2(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1060" *) LUT4 #( .INIT(16'h6A00)) \starve_limit_cntr_r[1]_i_1 (.I0(starve_limit_cntr_r[1]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1060" *) LUT5 #( .INIT(32'h6AAA0000)) \starve_limit_cntr_r[2]_i_1 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(starve_limit_cntr_r[1]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00007F0000000000)) \starve_limit_cntr_r[2]_i_2 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[2]), .I3(granted_col_r_reg), .I4(\grant_r_reg[2] [0]), .I5(req_bank_rdy_r), .O(starve_limit_cntr_r0)); FDRE \starve_limit_cntr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[0]_i_1_n_0 ), .Q(starve_limit_cntr_r[0]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[1]_i_1_n_0 ), .Q(starve_limit_cntr_r[1]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[2] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[2]_i_1_n_0 ), .Q(starve_limit_cntr_r[2]), .R(1'b0)); FDRE \wr_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(start_wtp_timer0), .Q(wr_this_rank_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_state" *) module ddr3_if_mig_7series_v4_0_bank_state__parameterized0 (bm_end_r1_0, \act_this_rank_r_reg[0]_0 , ras_timer_zero_r, pre_wait_r, act_this_rank_r, demand_priority_r_reg_0, demanded_prior_r_reg_0, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, \starve_limit_cntr_r_reg[2]_0 , pre_bm_end_ns, pre_passing_open_bank_ns, pre_passing_open_bank_r_reg, pre_passing_open_bank_r_reg_0, granted_pre_ns, \grant_r_reg[2] , \ras_timer_r_reg[0]_0 , \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[2]_0 , auto_pre_r_lcl_reg, \grant_r_reg[2]_0 , \grant_r_reg[1] , \rnk_config_strobe_r_reg[0] , \grant_r_reg[3] , p_91_out, CLK, act_wait_ns, req_bank_rdy_ns, SR, ofs_rdy_r0, start_wtp_timer0, rd_wr_r_lcl_reg, req_priority_r_reg, idle_r_lcl_reg, pass_open_bank_ns, \grant_r_reg[3]_0 , pass_open_bank_r_lcl_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] , auto_pre_r_lcl_reg_0, auto_pre_r_lcl_reg_1, \grant_r_reg[1]_0 , ras_timer_zero_r_reg_0, rd_wr_r_lcl_reg_0, bm_end_r1_reg_0, rstdiv0_sync_r1_reg_rep__22, accept_r_reg, tail_r_24, \grant_r_reg[1]_1 , \last_master_r_reg[0] , demanded_prior_r_reg_1, demand_priority_r_reg_1, demanded_prior_r_reg_2, req_wr_r_lcl_reg, q_has_rd_3, granted_col_r_reg, D, rstdiv0_sync_r1_reg_rep__20, pass_open_bank_r_lcl_reg_0, pass_open_bank_r_lcl_reg_1, rstdiv0_sync_r1_reg_rep__21, rstdiv0_sync_r1_reg_rep__0); output bm_end_r1_0; output \act_this_rank_r_reg[0]_0 ; output ras_timer_zero_r; output pre_wait_r; output [0:0]act_this_rank_r; output demand_priority_r_reg_0; output demanded_prior_r_reg_0; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output \starve_limit_cntr_r_reg[2]_0 ; output pre_bm_end_ns; output pre_passing_open_bank_ns; output pre_passing_open_bank_r_reg; output pre_passing_open_bank_r_reg_0; output granted_pre_ns; output \grant_r_reg[2] ; output \ras_timer_r_reg[0]_0 ; output \ras_timer_r_reg[1]_0 ; output \ras_timer_r_reg[2]_0 ; output auto_pre_r_lcl_reg; output \grant_r_reg[2]_0 ; output \grant_r_reg[1] ; output \rnk_config_strobe_r_reg[0] ; output \grant_r_reg[3] ; input p_91_out; input CLK; input act_wait_ns; input req_bank_rdy_ns; input [0:0]SR; input ofs_rdy_r0; input start_wtp_timer0; input rd_wr_r_lcl_reg; input req_priority_r_reg; input idle_r_lcl_reg; input pass_open_bank_ns; input [1:0]\grant_r_reg[3]_0 ; input pass_open_bank_r_lcl_reg; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; input auto_pre_r_lcl_reg_0; input auto_pre_r_lcl_reg_1; input [0:0]\grant_r_reg[1]_0 ; input ras_timer_zero_r_reg_0; input rd_wr_r_lcl_reg_0; input bm_end_r1_reg_0; input rstdiv0_sync_r1_reg_rep__22; input accept_r_reg; input tail_r_24; input [0:0]\grant_r_reg[1]_1 ; input \last_master_r_reg[0] ; input demanded_prior_r_reg_1; input demand_priority_r_reg_1; input demanded_prior_r_reg_2; input req_wr_r_lcl_reg; input q_has_rd_3; input granted_col_r_reg; input [2:0]D; input rstdiv0_sync_r1_reg_rep__20; input pass_open_bank_r_lcl_reg_0; input pass_open_bank_r_lcl_reg_1; input rstdiv0_sync_r1_reg_rep__21; input rstdiv0_sync_r1_reg_rep__0; wire CLK; wire [2:0]D; wire [0:0]SR; wire accept_r_reg; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0]_0 ; wire act_wait_ns; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire bm_end_r1_0; wire bm_end_r1_reg_0; wire col_wait_r_i_1__2_n_0; wire demand_priority_ns; wire demand_priority_r_i_2__1_n_0; wire demand_priority_r_i_4__2_n_0; wire demand_priority_r_i_5__0_n_0; wire demand_priority_r_reg_0; wire demand_priority_r_reg_1; wire demanded_prior_ns; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire demanded_prior_r_reg_2; wire \grant_r_reg[1] ; wire [0:0]\grant_r_reg[1]_0 ; wire [0:0]\grant_r_reg[1]_1 ; wire \grant_r_reg[2] ; wire \grant_r_reg[2]_0 ; wire \grant_r_reg[3] ; wire [1:0]\grant_r_reg[3]_0 ; wire granted_col_r_reg; wire granted_pre_ns; wire idle_r_lcl_reg; wire \last_master_r_reg[0] ; wire ofs_rdy_r; wire ofs_rdy_r0; wire p_91_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire pass_open_bank_r_lcl_reg_0; wire pass_open_bank_r_lcl_reg_1; wire pre_bm_end_ns; wire pre_passing_open_bank_ns; wire pre_passing_open_bank_r_reg; wire pre_passing_open_bank_r_reg_0; wire pre_wait_ns; wire pre_wait_r; wire q_has_rd_3; wire [2:0]ras_timer_r; wire \ras_timer_r[2]_i_4__2_n_0 ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2]_0 ; wire ras_timer_zero_ns; wire ras_timer_zero_r; wire ras_timer_zero_r_reg_0; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ; wire rcd_active_r; wire \rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ; wire [0:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_ns; wire req_bank_rdy_r; wire req_priority_r_reg; wire req_wr_r_lcl_reg; wire \rnk_config_strobe_r_reg[0] ; wire \rp_timer.rp_timer_r[0]_i_1__0_n_0 ; wire \rp_timer.rp_timer_r[1]_i_1__0_n_0 ; wire [0:0]rp_timer_ns; wire [1:0]rp_timer_r; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire \rtp_timer_r[0]_i_1__0_n_0 ; wire start_pre; wire start_wtp_timer0; wire [2:0]starve_limit_cntr_r; wire starve_limit_cntr_r0; wire \starve_limit_cntr_r[0]_i_1__0_n_0 ; wire \starve_limit_cntr_r[1]_i_1__0_n_0 ; wire \starve_limit_cntr_r[2]_i_1__0_n_0 ; wire \starve_limit_cntr_r_reg[2]_0 ; wire tail_r_24; wire [0:0]wr_this_rank_r; FDRE \act_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(\act_this_rank_r_reg[0]_0 ), .Q(act_this_rank_r), .R(1'b0)); FDRE act_wait_r_lcl_reg (.C(CLK), .CE(1'b1), .D(act_wait_ns), .Q(\act_this_rank_r_reg[0]_0 ), .R(1'b0)); FDRE bm_end_r1_reg (.C(CLK), .CE(1'b1), .D(p_91_out), .Q(bm_end_r1_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1073" *) LUT4 #( .INIT(16'hFFBA)) col_wait_r_i_1__2 (.I0(rcd_active_r), .I1(\grant_r_reg[3]_0 [0]), .I2(\starve_limit_cntr_r_reg[2]_0 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .O(col_wait_r_i_1__2_n_0)); FDRE col_wait_r_reg (.C(CLK), .CE(1'b1), .D(col_wait_r_i_1__2_n_0), .Q(\starve_limit_cntr_r_reg[2]_0 ), .R(SR)); LUT5 #( .INIT(32'h0000FB00)) demand_priority_r_i_1__1 (.I0(demand_priority_r_reg_0), .I1(demand_priority_r_i_2__1_n_0), .I2(req_priority_r_reg), .I3(idle_r_lcl_reg), .I4(demand_priority_r_i_4__2_n_0), .O(demand_priority_ns)); LUT6 #( .INIT(64'hFF2FFFFFFFFFFFFF)) demand_priority_r_i_2__1 (.I0(req_wr_r_lcl_reg), .I1(q_has_rd_3), .I2(req_bank_rdy_r), .I3(\grant_r_reg[3]_0 [0]), .I4(granted_col_r_reg), .I5(demand_priority_r_i_5__0_n_0), .O(demand_priority_r_i_2__1_n_0)); (* SOFT_HLUTNM = "soft_lutpair1073" *) LUT4 #( .INIT(16'h0051)) demand_priority_r_i_4__2 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ), .I1(\starve_limit_cntr_r_reg[2]_0 ), .I2(\grant_r_reg[3]_0 [0]), .I3(rcd_active_r), .O(demand_priority_r_i_4__2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1075" *) LUT3 #( .INIT(8'h80)) demand_priority_r_i_5__0 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[0]), .O(demand_priority_r_i_5__0_n_0)); FDRE demand_priority_r_reg (.C(CLK), .CE(1'b1), .D(demand_priority_ns), .Q(demand_priority_r_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hD0D0D0D0D0DDD0D0)) demanded_prior_r_i_1 (.I0(demand_priority_r_reg_0), .I1(demanded_prior_r_reg_0), .I2(demanded_prior_r_reg_1), .I3(\grant_r_reg[3]_0 [1]), .I4(demand_priority_r_reg_1), .I5(demanded_prior_r_reg_2), .O(demanded_prior_ns)); FDRE demanded_prior_r_reg (.C(CLK), .CE(1'b1), .D(demanded_prior_ns), .Q(demanded_prior_r_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1069" *) LUT4 #( .INIT(16'h1000)) \grant_r[1]_i_4__0 (.I0(auto_pre_r_lcl_reg_1), .I1(\grant_r_reg[1]_0 ), .I2(pre_wait_r), .I3(ras_timer_zero_r), .O(\grant_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1070" *) LUT5 #( .INIT(32'h00000080)) \grant_r[2]_i_2__0 (.I0(\last_master_r_reg[0] ), .I1(ras_timer_zero_r), .I2(pre_wait_r), .I3(\grant_r_reg[1]_0 ), .I4(auto_pre_r_lcl_reg_1), .O(\grant_r_reg[2]_0 )); LUT5 #( .INIT(32'h0000FFF7)) \grant_r[2]_i_3__0 (.I0(ras_timer_zero_r), .I1(pre_wait_r), .I2(\grant_r_reg[1]_0 ), .I3(auto_pre_r_lcl_reg_1), .I4(auto_pre_r_lcl_reg_0), .O(\grant_r_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair1071" *) LUT3 #( .INIT(8'hFB)) \grant_r[3]_i_15 (.I0(\grant_r_reg[3]_0 [0]), .I1(demand_priority_r_reg_0), .I2(demanded_prior_r_reg_0), .O(\grant_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair1071" *) LUT5 #( .INIT(32'hBBBBBABB)) i___34_i_4 (.I0(demand_priority_r_reg_1), .I1(demanded_prior_r_reg_1), .I2(\grant_r_reg[3]_0 [0]), .I3(demand_priority_r_reg_0), .I4(demanded_prior_r_reg_0), .O(\rnk_config_strobe_r_reg[0] )); LUT6 #( .INIT(64'h8888888880888080)) i___7_i_1 (.I0(accept_r_reg), .I1(tail_r_24), .I2(rcd_active_r), .I3(\grant_r_reg[3]_0 [0]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .I5(\act_this_rank_r_reg[0]_0 ), .O(auto_pre_r_lcl_reg)); FDRE #( .INIT(1'b0)) ofs_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ofs_rdy_r0), .Q(ofs_rdy_r), .R(SR)); LUT6 #( .INIT(64'hABAAAAAAFFFFFFFF)) \pre_4_1_1T_arb.granted_pre_r_i_1 (.I0(auto_pre_r_lcl_reg_0), .I1(auto_pre_r_lcl_reg_1), .I2(\grant_r_reg[1]_0 ), .I3(pre_wait_r), .I4(ras_timer_zero_r), .I5(ras_timer_zero_r_reg_0), .O(granted_pre_ns)); (* SOFT_HLUTNM = "soft_lutpair1074" *) LUT3 #( .INIT(8'hBA)) pre_bm_end_r_i_1 (.I0(pre_passing_open_bank_ns), .I1(rp_timer_r[1]), .I2(rp_timer_r[0]), .O(pre_bm_end_ns)); LUT6 #( .INIT(64'hAAA8AAAAAAA8AAA8)) pre_passing_open_bank_r_i_1 (.I0(pass_open_bank_ns), .I1(\grant_r_reg[3]_0 [0]), .I2(pre_passing_open_bank_r_reg), .I3(pre_passing_open_bank_r_reg_0), .I4(ras_timer_zero_r), .I5(pre_wait_r), .O(pre_passing_open_bank_ns)); LUT6 #( .INIT(64'h0040555500400040)) pre_wait_r_i_1 (.I0(pass_open_bank_ns), .I1(pass_open_bank_r_lcl_reg), .I2(pre_passing_open_bank_r_reg_0), .I3(pre_passing_open_bank_r_reg), .I4(rp_timer_ns), .I5(pre_wait_r), .O(pre_wait_ns)); (* SOFT_HLUTNM = "soft_lutpair1069" *) LUT5 #( .INIT(32'hEAEAEAAA)) pre_wait_r_i_3__0 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(ras_timer_zero_r), .I2(pre_wait_r), .I3(\grant_r_reg[1]_0 ), .I4(auto_pre_r_lcl_reg_1), .O(rp_timer_ns)); FDRE pre_wait_r_reg (.C(CLK), .CE(1'b1), .D(pre_wait_ns), .Q(pre_wait_r), .R(1'b0)); LUT6 #( .INIT(64'h000000000E0E000E)) \ras_timer_r[0]_i_3__2 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(\grant_r_reg[3]_0 [0]), .I4(rd_wr_r_lcl_reg), .I5(bm_end_r1_reg_0), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'hEEFFFFEFEEEEEEEE)) \ras_timer_r[1]_i_2__2 (.I0(bm_end_r1_0), .I1(rstdiv0_sync_r1_reg_rep__22), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\ras_timer_r[2]_i_4__2_n_0 ), .O(\ras_timer_r_reg[1]_0 )); LUT6 #( .INIT(64'h000000000000DDD5)) \ras_timer_r[2]_i_3__2 (.I0(\ras_timer_r[2]_i_4__2_n_0 ), .I1(ras_timer_r[2]), .I2(ras_timer_r[1]), .I3(ras_timer_r[0]), .I4(bm_end_r1_0), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\ras_timer_r_reg[2]_0 )); LUT6 #( .INIT(64'hDDDDDDD0DDDDDDDD)) \ras_timer_r[2]_i_4__2 (.I0(\grant_r_reg[3]_0 [0]), .I1(rd_wr_r_lcl_reg), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ), .O(\ras_timer_r[2]_i_4__2_n_0 )); FDRE \ras_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(ras_timer_r[0]), .R(1'b0)); FDRE \ras_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(ras_timer_r[1]), .R(1'b0)); FDRE \ras_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(ras_timer_r[2]), .R(1'b0)); LUT6 #( .INIT(64'hFFFF1000FFFF1100)) ras_timer_zero_r_i_1__2 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(rd_wr_r_lcl_reg_0), .I4(bm_end_r1_reg_0), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ), .O(ras_timer_zero_ns)); FDRE ras_timer_zero_r_reg (.C(CLK), .CE(1'b1), .D(ras_timer_zero_ns), .Q(ras_timer_zero_r), .R(1'b0)); LUT2 #( .INIT(4'h8)) \rcd_timer_gt_2.rcd_timer_r[0]_i_1__0 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[1]_1 ), .O(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \rcd_timer_gt_2.rcd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ), .Q(rcd_active_r), .R(SR)); FDRE \rd_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_wr_r_lcl_reg), .Q(rd_this_rank_r), .R(1'b0)); FDRE req_bank_rdy_r_reg (.C(CLK), .CE(1'b1), .D(req_bank_rdy_ns), .Q(req_bank_rdy_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1074" *) LUT4 #( .INIT(16'h0004)) \rp_timer.rp_timer_r[0]_i_1__0 (.I0(rp_timer_r[0]), .I1(rp_timer_r[1]), .I2(start_pre), .I3(rstdiv0_sync_r1_reg_rep__21), .O(\rp_timer.rp_timer_r[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1070" *) LUT4 #( .INIT(16'hE000)) \rp_timer.rp_timer_r[0]_i_2__0 (.I0(auto_pre_r_lcl_reg_1), .I1(\grant_r_reg[1]_0 ), .I2(pre_wait_r), .I3(ras_timer_zero_r), .O(start_pre)); LUT6 #( .INIT(64'hF888F888F8888888)) \rp_timer.rp_timer_r[1]_i_1__0 (.I0(rp_timer_r[1]), .I1(rp_timer_r[0]), .I2(ras_timer_zero_r), .I3(pre_wait_r), .I4(\grant_r_reg[1]_0 ), .I5(auto_pre_r_lcl_reg_1), .O(\rp_timer.rp_timer_r[1]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[0]_i_1__0_n_0 ), .Q(rp_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[1]_i_1__0_n_0 ), .Q(rp_timer_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); LUT4 #( .INIT(16'h0010)) \rtp_timer_r[0]_i_1__0 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(pass_open_bank_r_lcl_reg_0), .I2(pre_passing_open_bank_r_reg), .I3(pre_passing_open_bank_r_reg_0), .O(\rtp_timer_r[0]_i_1__0_n_0 )); FDRE \rtp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[0]_i_1__0_n_0 ), .Q(pre_passing_open_bank_r_reg_0), .R(1'b0)); FDRE \rtp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(pass_open_bank_r_lcl_reg_1), .Q(pre_passing_open_bank_r_reg), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1075" *) LUT3 #( .INIT(8'h60)) \starve_limit_cntr_r[0]_i_1__0 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r0), .I2(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1072" *) LUT4 #( .INIT(16'h6A00)) \starve_limit_cntr_r[1]_i_1__0 (.I0(starve_limit_cntr_r[1]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1072" *) LUT5 #( .INIT(32'h6AAA0000)) \starve_limit_cntr_r[2]_i_1__0 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(starve_limit_cntr_r[1]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[2]_i_1__0_n_0 )); LUT6 #( .INIT(64'h00007F0000000000)) \starve_limit_cntr_r[2]_i_2__0 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[2]), .I3(granted_col_r_reg), .I4(\grant_r_reg[3]_0 [0]), .I5(req_bank_rdy_r), .O(starve_limit_cntr_r0)); FDRE \starve_limit_cntr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[0]_i_1__0_n_0 ), .Q(starve_limit_cntr_r[0]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[1]_i_1__0_n_0 ), .Q(starve_limit_cntr_r[1]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[2] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[2]_i_1__0_n_0 ), .Q(starve_limit_cntr_r[2]), .R(1'b0)); FDRE \wr_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(start_wtp_timer0), .Q(wr_this_rank_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_state" *) module ddr3_if_mig_7series_v4_0_bank_state__parameterized1 (\ras_timer_r_reg[2]_0 , \act_this_rank_r_reg[0]_0 , \rp_timer.rp_timer_r_reg[1]_0 , pre_wait_r, act_this_rank_r, demand_priority_r_reg_0, demanded_prior_r_reg_0, override_demand_r, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, \starve_limit_cntr_r_reg[2]_0 , ofs_rdy_r0, ofs_rdy_r0_0, ofs_rdy_r0_1, \ras_timer_r_reg[0]_0 , \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[2]_1 , pre_bm_end_ns, pre_passing_open_bank_ns, auto_pre_r_lcl_reg, \grant_r_reg[2] , \rnk_config_strobe_r_reg[0] , p_52_out, CLK, act_wait_ns, req_bank_rdy_ns, override_demand_ns, SR, start_wtp_timer0, rd_wr_r_lcl_reg, rstdiv0_sync_r1_reg_rep__0, of_ctl_full_v, phy_mc_ctl_full, \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , rd_wr_r_lcl_reg_0, rd_wr_r_lcl_reg_1, rd_wr_r, rd_wr_r_lcl_reg_2, bm_end_r1_reg_0, rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[2]_0 , req_priority_r_reg, idle_r_lcl_reg, \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] , pass_open_bank_ns, rtp_timer_ns1_7, rb_hit_busy_r_reg, tail_r_26, \grant_r_reg[2]_1 , auto_pre_r_lcl_reg_0, \grant_r_reg[2]_2 , rstdiv0_sync_r1_reg_rep__22, demand_priority_r, demanded_prior_r_reg_1, demanded_prior_r, req_wr_r_lcl_reg, q_has_rd_10, granted_col_r_reg, D, pass_open_bank_r_lcl_reg, rstdiv0_sync_r1_reg_rep__20); output \ras_timer_r_reg[2]_0 ; output \act_this_rank_r_reg[0]_0 ; output \rp_timer.rp_timer_r_reg[1]_0 ; output pre_wait_r; output [0:0]act_this_rank_r; output demand_priority_r_reg_0; output demanded_prior_r_reg_0; output override_demand_r; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output \starve_limit_cntr_r_reg[2]_0 ; output ofs_rdy_r0; output ofs_rdy_r0_0; output ofs_rdy_r0_1; output \ras_timer_r_reg[0]_0 ; output \ras_timer_r_reg[1]_0 ; output \ras_timer_r_reg[2]_1 ; output pre_bm_end_ns; output pre_passing_open_bank_ns; output auto_pre_r_lcl_reg; output \grant_r_reg[2] ; output \rnk_config_strobe_r_reg[0] ; input p_52_out; input CLK; input act_wait_ns; input req_bank_rdy_ns; input override_demand_ns; input [0:0]SR; input start_wtp_timer0; input rd_wr_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__0; input [0:0]of_ctl_full_v; input phy_mc_ctl_full; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input rd_wr_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input [0:0]rd_wr_r; input rd_wr_r_lcl_reg_2; input bm_end_r1_reg_0; input rstdiv0_sync_r1_reg_rep__21; input [1:0]\grant_r_reg[2]_0 ; input req_priority_r_reg; input idle_r_lcl_reg; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; input pass_open_bank_ns; input rtp_timer_ns1_7; input rb_hit_busy_r_reg; input tail_r_26; input [0:0]\grant_r_reg[2]_1 ; input auto_pre_r_lcl_reg_0; input [0:0]\grant_r_reg[2]_2 ; input rstdiv0_sync_r1_reg_rep__22; input demand_priority_r; input demanded_prior_r_reg_1; input demanded_prior_r; input req_wr_r_lcl_reg; input q_has_rd_10; input granted_col_r_reg; input [2:0]D; input pass_open_bank_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__20; wire CLK; wire [2:0]D; wire [0:0]SR; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0]_0 ; wire act_wait_ns; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire bm_end_r1_reg_0; wire col_wait_r_i_1_n_0; wire demand_priority_ns; wire demand_priority_r; wire demand_priority_r_i_2__2_n_0; wire demand_priority_r_i_4_n_0; wire demand_priority_r_i_5__1_n_0; wire demand_priority_r_reg_0; wire demanded_prior_ns; wire demanded_prior_r; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire \grant_r_reg[2] ; wire [1:0]\grant_r_reg[2]_0 ; wire [0:0]\grant_r_reg[2]_1 ; wire [0:0]\grant_r_reg[2]_2 ; wire granted_col_r_reg; wire idle_r_lcl_reg; wire [0:0]of_ctl_full_v; wire ofs_rdy_r; wire ofs_rdy_r0; wire ofs_rdy_r0_0; wire ofs_rdy_r0_1; wire ofs_rdy_r0_2; wire override_demand_ns; wire override_demand_r; wire p_52_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire phy_mc_cmd_full_r; wire phy_mc_ctl_full; wire phy_mc_ctl_full_r; wire pre_bm_end_ns; wire pre_passing_open_bank_ns; wire pre_wait_ns; wire pre_wait_r; wire q_has_rd_10; wire [2:0]ras_timer_r; wire \ras_timer_r[2]_i_4_n_0 ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2]_0 ; wire \ras_timer_r_reg[2]_1 ; wire ras_timer_zero_ns; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ; wire rb_hit_busy_r_reg; wire rcd_active_r; wire \rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ; wire [0:0]rd_this_rank_r; wire [0:0]rd_wr_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire req_bank_rdy_ns; wire req_bank_rdy_r; wire req_priority_r_reg; wire req_wr_r_lcl_reg; wire \rnk_config_strobe_r_reg[0] ; wire \rp_timer.rp_timer_r[0]_i_1__1_n_0 ; wire \rp_timer.rp_timer_r[1]_i_1__1_n_0 ; wire \rp_timer.rp_timer_r_reg[1]_0 ; wire [0:0]rp_timer_ns; wire [1:0]rp_timer_r; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1_7; wire [1:0]rtp_timer_r; wire \rtp_timer_r[0]_i_1__1_n_0 ; wire \rtp_timer_r[1]_i_1__0_n_0 ; wire start_pre; wire start_wtp_timer0; wire [2:0]starve_limit_cntr_r; wire starve_limit_cntr_r0; wire \starve_limit_cntr_r[0]_i_1__1_n_0 ; wire \starve_limit_cntr_r[1]_i_1__1_n_0 ; wire \starve_limit_cntr_r[2]_i_1__1_n_0 ; wire \starve_limit_cntr_r_reg[2]_0 ; wire tail_r_26; wire [0:0]wr_this_rank_r; FDRE \act_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(\act_this_rank_r_reg[0]_0 ), .Q(act_this_rank_r), .R(1'b0)); FDRE act_wait_r_lcl_reg (.C(CLK), .CE(1'b1), .D(act_wait_ns), .Q(\act_this_rank_r_reg[0]_0 ), .R(1'b0)); FDRE bm_end_r1_reg (.C(CLK), .CE(1'b1), .D(p_52_out), .Q(\ras_timer_r_reg[2]_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1084" *) LUT4 #( .INIT(16'hFFBA)) col_wait_r_i_1 (.I0(rcd_active_r), .I1(\grant_r_reg[2]_0 [1]), .I2(\starve_limit_cntr_r_reg[2]_0 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ), .O(col_wait_r_i_1_n_0)); FDRE col_wait_r_reg (.C(CLK), .CE(1'b1), .D(col_wait_r_i_1_n_0), .Q(\starve_limit_cntr_r_reg[2]_0 ), .R(SR)); LUT5 #( .INIT(32'h0000FB00)) demand_priority_r_i_1__0 (.I0(demand_priority_r_reg_0), .I1(demand_priority_r_i_2__2_n_0), .I2(req_priority_r_reg), .I3(idle_r_lcl_reg), .I4(demand_priority_r_i_4_n_0), .O(demand_priority_ns)); LUT6 #( .INIT(64'hFF2FFFFFFFFFFFFF)) demand_priority_r_i_2__2 (.I0(req_wr_r_lcl_reg), .I1(q_has_rd_10), .I2(req_bank_rdy_r), .I3(\grant_r_reg[2]_0 [1]), .I4(granted_col_r_reg), .I5(demand_priority_r_i_5__1_n_0), .O(demand_priority_r_i_2__2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1084" *) LUT4 #( .INIT(16'h0051)) demand_priority_r_i_4 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ), .I1(\starve_limit_cntr_r_reg[2]_0 ), .I2(\grant_r_reg[2]_0 [1]), .I3(rcd_active_r), .O(demand_priority_r_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair1085" *) LUT3 #( .INIT(8'h80)) demand_priority_r_i_5__1 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[0]), .O(demand_priority_r_i_5__1_n_0)); FDRE demand_priority_r_reg (.C(CLK), .CE(1'b1), .D(demand_priority_ns), .Q(demand_priority_r_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hD0D0D0D0D0DDD0D0)) demanded_prior_r_i_1__2 (.I0(demand_priority_r_reg_0), .I1(demanded_prior_r_reg_0), .I2(demanded_prior_r_reg_1), .I3(\grant_r_reg[2]_0 [0]), .I4(demand_priority_r), .I5(demanded_prior_r), .O(demanded_prior_ns)); FDRE demanded_prior_r_reg (.C(CLK), .CE(1'b1), .D(demanded_prior_ns), .Q(demanded_prior_r_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1081" *) LUT4 #( .INIT(16'h1000)) \grant_r[3]_i_3__1 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[2]_2 ), .I2(pre_wait_r), .I3(\rp_timer.rp_timer_r_reg[1]_0 ), .O(\grant_r_reg[2] )); LUT6 #( .INIT(64'h8888888880888080)) i___11_i_1 (.I0(rb_hit_busy_r_reg), .I1(tail_r_26), .I2(rcd_active_r), .I3(\grant_r_reg[2]_0 [1]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .I5(\act_this_rank_r_reg[0]_0 ), .O(auto_pre_r_lcl_reg)); LUT5 #( .INIT(32'h000F0001)) ofs_rdy_r_i_1__0 (.I0(\entry_cnt_reg[2] ), .I1(\entry_cnt_reg[2]_0 ), .I2(phy_mc_ctl_full_r), .I3(phy_mc_cmd_full_r), .I4(rd_wr_r_lcl_reg_1), .O(ofs_rdy_r0_0)); LUT5 #( .INIT(32'h000F0001)) ofs_rdy_r_i_1__1 (.I0(\entry_cnt_reg[2] ), .I1(\entry_cnt_reg[2]_0 ), .I2(phy_mc_ctl_full_r), .I3(phy_mc_cmd_full_r), .I4(rd_wr_r_lcl_reg), .O(ofs_rdy_r0_2)); LUT5 #( .INIT(32'h000F0001)) ofs_rdy_r_i_1__2 (.I0(\entry_cnt_reg[2] ), .I1(\entry_cnt_reg[2]_0 ), .I2(phy_mc_ctl_full_r), .I3(phy_mc_cmd_full_r), .I4(rd_wr_r), .O(ofs_rdy_r0_1)); LUT5 #( .INIT(32'h000F0001)) ofs_rdy_r_i_2 (.I0(\entry_cnt_reg[2] ), .I1(\entry_cnt_reg[2]_0 ), .I2(phy_mc_ctl_full_r), .I3(phy_mc_cmd_full_r), .I4(rd_wr_r_lcl_reg_0), .O(ofs_rdy_r0)); FDRE #( .INIT(1'b0)) ofs_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ofs_rdy_r0_2), .Q(ofs_rdy_r), .R(SR)); FDRE override_demand_r_reg (.C(CLK), .CE(1'b1), .D(override_demand_ns), .Q(override_demand_r), .R(1'b0)); FDRE #( .INIT(1'b0)) phy_mc_cmd_full_r_reg (.C(CLK), .CE(1'b1), .D(of_ctl_full_v), .Q(phy_mc_cmd_full_r), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE #( .INIT(1'b0)) phy_mc_ctl_full_r_reg (.C(CLK), .CE(1'b1), .D(phy_mc_ctl_full), .Q(phy_mc_ctl_full_r), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair1083" *) LUT3 #( .INIT(8'hBA)) pre_bm_end_r_i_1__2 (.I0(pre_passing_open_bank_ns), .I1(rp_timer_r[1]), .I2(rp_timer_r[0]), .O(pre_bm_end_ns)); LUT6 #( .INIT(64'hAAA8AAAAAAA8AAA8)) pre_passing_open_bank_r_i_1__2 (.I0(pass_open_bank_ns), .I1(\grant_r_reg[2]_0 [1]), .I2(rtp_timer_r[1]), .I3(rtp_timer_r[0]), .I4(\rp_timer.rp_timer_r_reg[1]_0 ), .I5(pre_wait_r), .O(pre_passing_open_bank_ns)); LUT6 #( .INIT(64'h0404040404550404)) pre_wait_r_i_1__2 (.I0(pass_open_bank_ns), .I1(pre_wait_r), .I2(rp_timer_ns), .I3(rtp_timer_ns1_7), .I4(rtp_timer_r[0]), .I5(rtp_timer_r[1]), .O(pre_wait_ns)); (* SOFT_HLUTNM = "soft_lutpair1081" *) LUT5 #( .INIT(32'hEAEAEAAA)) pre_wait_r_i_2__1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\rp_timer.rp_timer_r_reg[1]_0 ), .I2(pre_wait_r), .I3(\grant_r_reg[2]_2 ), .I4(auto_pre_r_lcl_reg_0), .O(rp_timer_ns)); FDRE pre_wait_r_reg (.C(CLK), .CE(1'b1), .D(pre_wait_ns), .Q(pre_wait_r), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000E00)) \ras_timer_r[0]_i_3 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(rd_wr_r_lcl_reg_2), .I4(rstdiv0_sync_r1_reg_rep__21), .I5(\ras_timer_r_reg[2]_0 ), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'h1100001011111111)) \ras_timer_r[1]_i_3__0 (.I0(\ras_timer_r_reg[2]_0 ), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\ras_timer_r[2]_i_4_n_0 ), .O(\ras_timer_r_reg[1]_0 )); LUT6 #( .INIT(64'h000000000000DDD5)) \ras_timer_r[2]_i_3 (.I0(\ras_timer_r[2]_i_4_n_0 ), .I1(ras_timer_r[2]), .I2(ras_timer_r[1]), .I3(ras_timer_r[0]), .I4(\ras_timer_r_reg[2]_0 ), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\ras_timer_r_reg[2]_1 )); LUT6 #( .INIT(64'hDDDDDDD0DDDDDDDD)) \ras_timer_r[2]_i_4 (.I0(\grant_r_reg[2]_0 [1]), .I1(rd_wr_r_lcl_reg), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ), .O(\ras_timer_r[2]_i_4_n_0 )); FDRE \ras_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(ras_timer_r[0]), .R(1'b0)); FDRE \ras_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(ras_timer_r[1]), .R(1'b0)); FDRE \ras_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(ras_timer_r[2]), .R(1'b0)); LUT6 #( .INIT(64'hFFFF1000FFFF1100)) ras_timer_zero_r_i_1 (.I0(ras_timer_r[1]), .I1(ras_timer_r[2]), .I2(ras_timer_r[0]), .I3(rd_wr_r_lcl_reg_2), .I4(bm_end_r1_reg_0), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ), .O(ras_timer_zero_ns)); FDRE ras_timer_zero_r_reg (.C(CLK), .CE(1'b1), .D(ras_timer_zero_ns), .Q(\rp_timer.rp_timer_r_reg[1]_0 ), .R(1'b0)); LUT2 #( .INIT(4'h8)) \rcd_timer_gt_2.rcd_timer_r[0]_i_1__1 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[2]_1 ), .O(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 )); FDRE #( .INIT(1'b0)) \rcd_timer_gt_2.rcd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ), .Q(rcd_active_r), .R(SR)); FDRE \rd_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_wr_r_lcl_reg), .Q(rd_this_rank_r), .R(1'b0)); FDRE req_bank_rdy_r_reg (.C(CLK), .CE(1'b1), .D(req_bank_rdy_ns), .Q(req_bank_rdy_r), .R(1'b0)); LUT5 #( .INIT(32'hAAAAFFEF)) \rnk_config_strobe_r[0]_i_4 (.I0(demand_priority_r), .I1(\grant_r_reg[2]_0 [1]), .I2(demand_priority_r_reg_0), .I3(demanded_prior_r_reg_0), .I4(demanded_prior_r_reg_1), .O(\rnk_config_strobe_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1083" *) LUT4 #( .INIT(16'h0004)) \rp_timer.rp_timer_r[0]_i_1__1 (.I0(rp_timer_r[0]), .I1(rp_timer_r[1]), .I2(start_pre), .I3(rstdiv0_sync_r1_reg_rep__21), .O(\rp_timer.rp_timer_r[0]_i_1__1_n_0 )); LUT4 #( .INIT(16'hE000)) \rp_timer.rp_timer_r[0]_i_2__1 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[2]_2 ), .I2(pre_wait_r), .I3(\rp_timer.rp_timer_r_reg[1]_0 ), .O(start_pre)); LUT6 #( .INIT(64'hF888F888F8888888)) \rp_timer.rp_timer_r[1]_i_1__1 (.I0(rp_timer_r[1]), .I1(rp_timer_r[0]), .I2(\rp_timer.rp_timer_r_reg[1]_0 ), .I3(pre_wait_r), .I4(\grant_r_reg[2]_2 ), .I5(auto_pre_r_lcl_reg_0), .O(\rp_timer.rp_timer_r[1]_i_1__1_n_0 )); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[0]_i_1__1_n_0 ), .Q(rp_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[1]_i_1__1_n_0 ), .Q(rp_timer_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); LUT4 #( .INIT(16'h0002)) \rtp_timer_r[0]_i_1__1 (.I0(rtp_timer_r[1]), .I1(rtp_timer_r[0]), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(pass_open_bank_r_lcl_reg), .O(\rtp_timer_r[0]_i_1__1_n_0 )); LUT5 #( .INIT(32'h000000C2)) \rtp_timer_r[1]_i_1__0 (.I0(\grant_r_reg[2]_0 [1]), .I1(rtp_timer_r[1]), .I2(rtp_timer_r[0]), .I3(pass_open_bank_r_lcl_reg), .I4(rstdiv0_sync_r1_reg_rep__21), .O(\rtp_timer_r[1]_i_1__0_n_0 )); FDRE \rtp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[0]_i_1__1_n_0 ), .Q(rtp_timer_r[0]), .R(1'b0)); FDRE \rtp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[1]_i_1__0_n_0 ), .Q(rtp_timer_r[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1085" *) LUT3 #( .INIT(8'h60)) \starve_limit_cntr_r[0]_i_1__1 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r0), .I2(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1082" *) LUT4 #( .INIT(16'h6A00)) \starve_limit_cntr_r[1]_i_1__1 (.I0(starve_limit_cntr_r[1]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1082" *) LUT5 #( .INIT(32'h6AAA0000)) \starve_limit_cntr_r[2]_i_1__1 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(starve_limit_cntr_r[1]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[2]_i_1__1_n_0 )); LUT6 #( .INIT(64'h00007F0000000000)) \starve_limit_cntr_r[2]_i_2__1 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[2]), .I3(granted_col_r_reg), .I4(\grant_r_reg[2]_0 [1]), .I5(req_bank_rdy_r), .O(starve_limit_cntr_r0)); FDRE \starve_limit_cntr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[0]_i_1__1_n_0 ), .Q(starve_limit_cntr_r[0]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[1]_i_1__1_n_0 ), .Q(starve_limit_cntr_r[1]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[2] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[2]_i_1__1_n_0 ), .Q(starve_limit_cntr_r[2]), .R(1'b0)); FDRE \wr_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(start_wtp_timer0), .Q(wr_this_rank_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_bank_state" *) module ddr3_if_mig_7series_v4_0_bank_state__parameterized2 (bm_end_r1_4, \act_this_rank_r_reg[0]_0 , ras_timer_zero_r, pre_wait_r, act_this_rank_r, req_bank_rdy_r, demand_priority_r_reg_0, demanded_prior_r_reg_0, ofs_rdy_r, wr_this_rank_r, rd_this_rank_r, \starve_limit_cntr_r_reg[2]_0 , \ras_timer_r_reg[0]_0 , \ras_timer_r_reg[1]_0 , \ras_timer_r_reg[2]_0 , pre_bm_end_ns, pre_passing_open_bank_ns, auto_pre_r_lcl_reg, \pre_4_1_1T_arb.granted_pre_r_reg , \grant_r_reg[3] , \cmd_pipe_plus.mc_address_reg[10] , \grant_r_reg[0] , \grant_r_reg[2] , demanded_prior_r_reg_1, \rnk_config_strobe_r_reg[0] , p_13_out, CLK, act_wait_ns, req_bank_rdy_ns, SR, ofs_rdy_r0, start_wtp_timer0, rd_wr_r_lcl_reg, req_priority_r_reg, idle_r_lcl_reg, rd_wr_r_lcl_reg_0, bm_end_r1_reg_0, \grant_r_reg[3]_0 , rstdiv0_sync_r1_reg_rep__21, \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] , pass_open_bank_ns, rtp_timer_ns1_6, rb_hit_busy_r_reg, tail_r_28, \grant_r_reg[3]_1 , auto_pre_r_lcl_reg_0, auto_pre_r_lcl_reg_1, demanded_prior_r_reg_2, \grant_r_reg[1] , override_demand_r, rnk_config_valid_r_lcl_reg, \grant_r_reg[3]_2 , \req_row_r_lcl_reg[10] , \req_row_r_lcl_reg[10]_0 , row_cmd_wr, \grant_r_reg[3]_3 , \last_master_r_reg[2] , rstdiv0_sync_r1_reg_rep__22, demand_priority_r_reg_1, demanded_prior_r, req_wr_r_lcl_reg, q_has_rd_16, req_bank_rdy_r_reg_0, granted_col_r_reg, D, pass_open_bank_r_lcl_reg, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__0); output bm_end_r1_4; output \act_this_rank_r_reg[0]_0 ; output ras_timer_zero_r; output pre_wait_r; output [0:0]act_this_rank_r; output req_bank_rdy_r; output demand_priority_r_reg_0; output demanded_prior_r_reg_0; output ofs_rdy_r; output [0:0]wr_this_rank_r; output [0:0]rd_this_rank_r; output \starve_limit_cntr_r_reg[2]_0 ; output \ras_timer_r_reg[0]_0 ; output \ras_timer_r_reg[1]_0 ; output \ras_timer_r_reg[2]_0 ; output pre_bm_end_ns; output pre_passing_open_bank_ns; output auto_pre_r_lcl_reg; output \pre_4_1_1T_arb.granted_pre_r_reg ; output \grant_r_reg[3] ; output \cmd_pipe_plus.mc_address_reg[10] ; output \grant_r_reg[0] ; output \grant_r_reg[2] ; output demanded_prior_r_reg_1; output \rnk_config_strobe_r_reg[0] ; input p_13_out; input CLK; input act_wait_ns; input req_bank_rdy_ns; input [0:0]SR; input ofs_rdy_r0; input start_wtp_timer0; input rd_wr_r_lcl_reg; input req_priority_r_reg; input idle_r_lcl_reg; input rd_wr_r_lcl_reg_0; input bm_end_r1_reg_0; input [1:0]\grant_r_reg[3]_0 ; input rstdiv0_sync_r1_reg_rep__21; input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ; input pass_open_bank_ns; input rtp_timer_ns1_6; input rb_hit_busy_r_reg; input tail_r_28; input [0:0]\grant_r_reg[3]_1 ; input auto_pre_r_lcl_reg_0; input auto_pre_r_lcl_reg_1; input demanded_prior_r_reg_2; input \grant_r_reg[1] ; input override_demand_r; input rnk_config_valid_r_lcl_reg; input [0:0]\grant_r_reg[3]_2 ; input [0:0]\req_row_r_lcl_reg[10] ; input [0:0]\req_row_r_lcl_reg[10]_0 ; input [0:0]row_cmd_wr; input \grant_r_reg[3]_3 ; input \last_master_r_reg[2] ; input rstdiv0_sync_r1_reg_rep__22; input demand_priority_r_reg_1; input demanded_prior_r; input req_wr_r_lcl_reg; input q_has_rd_16; input req_bank_rdy_r_reg_0; input granted_col_r_reg; input [2:0]D; input pass_open_bank_r_lcl_reg; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__0; wire CLK; wire [2:0]D; wire [0:0]SR; wire [0:0]act_this_rank_r; wire \act_this_rank_r_reg[0]_0 ; wire act_wait_ns; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire bm_end_r1_4; wire bm_end_r1_reg_0; wire \cmd_pipe_plus.mc_address_reg[10] ; wire col_wait_r_i_1__1_n_0; wire demand_priority_ns; wire demand_priority_r_i_3__2_n_0; wire demand_priority_r_i_4__1_n_0; wire demand_priority_r_reg_0; wire demand_priority_r_reg_1; wire demanded_prior_ns; wire demanded_prior_r; wire demanded_prior_r_reg_0; wire demanded_prior_r_reg_1; wire demanded_prior_r_reg_2; wire \grant_r_reg[0] ; wire \grant_r_reg[1] ; wire \grant_r_reg[2] ; wire \grant_r_reg[3] ; wire [1:0]\grant_r_reg[3]_0 ; wire [0:0]\grant_r_reg[3]_1 ; wire [0:0]\grant_r_reg[3]_2 ; wire \grant_r_reg[3]_3 ; wire granted_col_r_reg; wire idle_r_lcl_reg; wire \last_master_r_reg[2] ; wire ofs_rdy_r; wire ofs_rdy_r0; wire override_demand_r; wire p_13_out; wire pass_open_bank_ns; wire pass_open_bank_r_lcl_reg; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire pre_bm_end_ns; wire pre_passing_open_bank_ns; wire pre_wait_ns; wire pre_wait_r; wire q_has_rd_16; wire [2:0]ras_timer_r; wire \ras_timer_r[2]_i_4__0_n_0 ; wire \ras_timer_r_reg[0]_0 ; wire \ras_timer_r_reg[1]_0 ; wire \ras_timer_r_reg[2]_0 ; wire ras_timer_zero_ns; wire ras_timer_zero_r; wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ; wire rb_hit_busy_r_reg; wire rcd_active_r; wire \rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ; wire [0:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire req_bank_rdy_ns; wire req_bank_rdy_r; wire req_bank_rdy_r_reg_0; wire req_priority_r_reg; wire [0:0]\req_row_r_lcl_reg[10] ; wire [0:0]\req_row_r_lcl_reg[10]_0 ; wire req_wr_r_lcl_reg; wire \rnk_config_strobe_r_reg[0] ; wire rnk_config_valid_r_lcl_reg; wire [0:0]row_cmd_wr; wire \rp_timer.rp_timer_r[0]_i_1__2_n_0 ; wire \rp_timer.rp_timer_r[1]_i_1__2_n_0 ; wire [0:0]rp_timer_ns; wire [1:0]rp_timer_r; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rtp_timer_ns1_6; wire [1:0]rtp_timer_r; wire \rtp_timer_r[0]_i_1__2_n_0 ; wire \rtp_timer_r[1]_i_1__1_n_0 ; wire start_pre; wire start_wtp_timer0; wire [2:0]starve_limit_cntr_r; wire starve_limit_cntr_r0; wire \starve_limit_cntr_r[0]_i_1__2_n_0 ; wire \starve_limit_cntr_r[1]_i_1__2_n_0 ; wire \starve_limit_cntr_r[2]_i_1__2_n_0 ; wire \starve_limit_cntr_r_reg[2]_0 ; wire tail_r_28; wire [0:0]wr_this_rank_r; FDRE \act_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(\act_this_rank_r_reg[0]_0 ), .Q(act_this_rank_r), .R(1'b0)); FDRE act_wait_r_lcl_reg (.C(CLK), .CE(1'b1), .D(act_wait_ns), .Q(\act_this_rank_r_reg[0]_0 ), .R(1'b0)); FDRE bm_end_r1_reg (.C(CLK), .CE(1'b1), .D(p_13_out), .Q(bm_end_r1_4), .R(1'b0)); LUT6 #( .INIT(64'h7F7F7F7F007F7F7F)) \cmd_pipe_plus.mc_address[10]_i_3 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[3]_2 ), .I2(\req_row_r_lcl_reg[10] ), .I3(\req_row_r_lcl_reg[10]_0 ), .I4(row_cmd_wr), .I5(\grant_r_reg[3]_3 ), .O(\cmd_pipe_plus.mc_address_reg[10] )); (* SOFT_HLUTNM = "soft_lutpair1093" *) LUT4 #( .INIT(16'hFFBA)) col_wait_r_i_1__1 (.I0(rcd_active_r), .I1(\grant_r_reg[3]_0 [1]), .I2(\starve_limit_cntr_r_reg[2]_0 ), .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ), .O(col_wait_r_i_1__1_n_0)); FDRE col_wait_r_reg (.C(CLK), .CE(1'b1), .D(col_wait_r_i_1__1_n_0), .Q(\starve_limit_cntr_r_reg[2]_0 ), .R(SR)); LUT5 #( .INIT(32'h0000FE00)) demand_priority_r_i_1 (.I0(req_priority_r_reg), .I1(demand_priority_r_reg_0), .I2(demand_priority_r_i_3__2_n_0), .I3(idle_r_lcl_reg), .I4(demand_priority_r_i_4__1_n_0), .O(demand_priority_ns)); LUT6 #( .INIT(64'h0000000080800080)) demand_priority_r_i_3__2 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[2]), .I3(req_wr_r_lcl_reg), .I4(q_has_rd_16), .I5(req_bank_rdy_r_reg_0), .O(demand_priority_r_i_3__2_n_0)); (* SOFT_HLUTNM = "soft_lutpair1093" *) LUT4 #( .INIT(16'h0051)) demand_priority_r_i_4__1 (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ), .I1(\starve_limit_cntr_r_reg[2]_0 ), .I2(\grant_r_reg[3]_0 [1]), .I3(rcd_active_r), .O(demand_priority_r_i_4__1_n_0)); FDRE demand_priority_r_reg (.C(CLK), .CE(1'b1), .D(demand_priority_ns), .Q(demand_priority_r_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hD0D0D0D0D0DDD0D0)) demanded_prior_r_i_1__0 (.I0(demand_priority_r_reg_0), .I1(demanded_prior_r_reg_0), .I2(demanded_prior_r_reg_2), .I3(\grant_r_reg[3]_0 [0]), .I4(demand_priority_r_reg_1), .I5(demanded_prior_r), .O(demanded_prior_ns)); FDRE demanded_prior_r_reg (.C(CLK), .CE(1'b1), .D(demanded_prior_ns), .Q(demanded_prior_r_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1091" *) LUT5 #( .INIT(32'h00000080)) \grant_r[0]_i_2 (.I0(\last_master_r_reg[2] ), .I1(ras_timer_zero_r), .I2(pre_wait_r), .I3(\grant_r_reg[3]_1 ), .I4(auto_pre_r_lcl_reg_0), .O(\grant_r_reg[0] )); LUT5 #( .INIT(32'h0000FFF7)) \grant_r[0]_i_3 (.I0(ras_timer_zero_r), .I1(pre_wait_r), .I2(\grant_r_reg[3]_1 ), .I3(auto_pre_r_lcl_reg_0), .I4(auto_pre_r_lcl_reg_1), .O(\pre_4_1_1T_arb.granted_pre_r_reg )); LUT5 #( .INIT(32'hFFFF0045)) \grant_r[3]_i_10 (.I0(demand_priority_r_reg_0), .I1(demanded_prior_r_reg_2), .I2(\grant_r_reg[1] ), .I3(override_demand_r), .I4(rnk_config_valid_r_lcl_reg), .O(\grant_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair1090" *) LUT4 #( .INIT(16'h1000)) \grant_r[3]_i_4 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[3]_1 ), .I2(pre_wait_r), .I3(ras_timer_zero_r), .O(\grant_r_reg[2] )); LUT6 #( .INIT(64'h8888888880888080)) i___15_i_1 (.I0(rb_hit_busy_r_reg), .I1(tail_r_28), .I2(rcd_active_r), .I3(\grant_r_reg[3]_0 [1]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .I5(\act_this_rank_r_reg[0]_0 ), .O(auto_pre_r_lcl_reg)); LUT6 #( .INIT(64'h0404040404FF0404)) i___88_i_1 (.I0(demanded_prior_r_reg_0), .I1(demand_priority_r_reg_0), .I2(\grant_r_reg[3]_0 [1]), .I3(demanded_prior_r), .I4(demand_priority_r_reg_1), .I5(\grant_r_reg[3]_0 [0]), .O(demanded_prior_r_reg_1)); FDRE #( .INIT(1'b0)) ofs_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ofs_rdy_r0), .Q(ofs_rdy_r), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair1094" *) LUT3 #( .INIT(8'hBA)) pre_bm_end_r_i_1__1 (.I0(pre_passing_open_bank_ns), .I1(rp_timer_r[1]), .I2(rp_timer_r[0]), .O(pre_bm_end_ns)); LUT6 #( .INIT(64'hAAA8AAAAAAA8AAA8)) pre_passing_open_bank_r_i_1__1 (.I0(pass_open_bank_ns), .I1(\grant_r_reg[3]_0 [1]), .I2(rtp_timer_r[1]), .I3(rtp_timer_r[0]), .I4(ras_timer_zero_r), .I5(pre_wait_r), .O(pre_passing_open_bank_ns)); LUT6 #( .INIT(64'h0404040404550404)) pre_wait_r_i_1__1 (.I0(pass_open_bank_ns), .I1(pre_wait_r), .I2(rp_timer_ns), .I3(rtp_timer_ns1_6), .I4(rtp_timer_r[0]), .I5(rtp_timer_r[1]), .O(pre_wait_ns)); (* SOFT_HLUTNM = "soft_lutpair1090" *) LUT5 #( .INIT(32'hEAEAEAAA)) pre_wait_r_i_2__2 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(ras_timer_zero_r), .I2(pre_wait_r), .I3(\grant_r_reg[3]_1 ), .I4(auto_pre_r_lcl_reg_0), .O(rp_timer_ns)); FDRE pre_wait_r_reg (.C(CLK), .CE(1'b1), .D(pre_wait_ns), .Q(pre_wait_r), .R(1'b0)); LUT6 #( .INIT(64'h000000000000BBB0)) \ras_timer_r[0]_i_3__0 (.I0(rd_wr_r_lcl_reg), .I1(\grant_r_reg[3]_0 [1]), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(bm_end_r1_reg_0), .I5(ras_timer_r[0]), .O(\ras_timer_r_reg[0]_0 )); LUT6 #( .INIT(64'h1100001011111111)) \ras_timer_r[1]_i_3__1 (.I0(bm_end_r1_4), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\ras_timer_r[2]_i_4__0_n_0 ), .O(\ras_timer_r_reg[1]_0 )); LUT6 #( .INIT(64'h000000000000DDD5)) \ras_timer_r[2]_i_3__0 (.I0(\ras_timer_r[2]_i_4__0_n_0 ), .I1(ras_timer_r[2]), .I2(ras_timer_r[1]), .I3(ras_timer_r[0]), .I4(bm_end_r1_4), .I5(rstdiv0_sync_r1_reg_rep__21), .O(\ras_timer_r_reg[2]_0 )); LUT6 #( .INIT(64'hDDDDDDD0DDDDDDDD)) \ras_timer_r[2]_i_4__0 (.I0(\grant_r_reg[3]_0 [1]), .I1(rd_wr_r_lcl_reg), .I2(ras_timer_r[2]), .I3(ras_timer_r[1]), .I4(ras_timer_r[0]), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ), .O(\ras_timer_r[2]_i_4__0_n_0 )); FDRE \ras_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(ras_timer_r[0]), .R(1'b0)); FDRE \ras_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(ras_timer_r[1]), .R(1'b0)); FDRE \ras_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(ras_timer_r[2]), .R(1'b0)); LUT6 #( .INIT(64'hFF02FF00FF02FF02)) ras_timer_zero_r_i_1__0 (.I0(rd_wr_r_lcl_reg_0), .I1(ras_timer_r[2]), .I2(ras_timer_r[1]), .I3(bm_end_r1_reg_0), .I4(ras_timer_r[0]), .I5(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ), .O(ras_timer_zero_ns)); FDRE ras_timer_zero_r_reg (.C(CLK), .CE(1'b1), .D(ras_timer_zero_ns), .Q(ras_timer_zero_r), .R(1'b0)); LUT2 #( .INIT(4'h8)) \rcd_timer_gt_2.rcd_timer_r[0]_i_1__2 (.I0(\act_this_rank_r_reg[0]_0 ), .I1(\grant_r_reg[3]_2 ), .O(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 )); FDRE #( .INIT(1'b0)) \rcd_timer_gt_2.rcd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ), .Q(rcd_active_r), .R(SR)); FDRE \rd_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_wr_r_lcl_reg), .Q(rd_this_rank_r), .R(1'b0)); FDRE req_bank_rdy_r_reg (.C(CLK), .CE(1'b1), .D(req_bank_rdy_ns), .Q(req_bank_rdy_r), .R(1'b0)); LUT5 #( .INIT(32'hBBBBBABB)) \rnk_config_strobe_r[0]_i_2 (.I0(demand_priority_r_reg_1), .I1(demanded_prior_r_reg_2), .I2(\grant_r_reg[3]_0 [1]), .I3(demand_priority_r_reg_0), .I4(demanded_prior_r_reg_0), .O(\rnk_config_strobe_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1094" *) LUT4 #( .INIT(16'h0004)) \rp_timer.rp_timer_r[0]_i_1__2 (.I0(rp_timer_r[0]), .I1(rp_timer_r[1]), .I2(start_pre), .I3(rstdiv0_sync_r1_reg_rep__21), .O(\rp_timer.rp_timer_r[0]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1091" *) LUT4 #( .INIT(16'hE000)) \rp_timer.rp_timer_r[0]_i_2__2 (.I0(auto_pre_r_lcl_reg_0), .I1(\grant_r_reg[3]_1 ), .I2(pre_wait_r), .I3(ras_timer_zero_r), .O(start_pre)); LUT6 #( .INIT(64'hF888F888F8888888)) \rp_timer.rp_timer_r[1]_i_1__2 (.I0(rp_timer_r[1]), .I1(rp_timer_r[0]), .I2(ras_timer_zero_r), .I3(pre_wait_r), .I4(\grant_r_reg[3]_1 ), .I5(auto_pre_r_lcl_reg_0), .O(\rp_timer.rp_timer_r[1]_i_1__2_n_0 )); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[0]_i_1__2_n_0 ), .Q(rp_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \rp_timer.rp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rp_timer.rp_timer_r[1]_i_1__2_n_0 ), .Q(rp_timer_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); LUT4 #( .INIT(16'h0002)) \rtp_timer_r[0]_i_1__2 (.I0(rtp_timer_r[1]), .I1(rtp_timer_r[0]), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(pass_open_bank_r_lcl_reg), .O(\rtp_timer_r[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h000000C2)) \rtp_timer_r[1]_i_1__1 (.I0(\grant_r_reg[3]_0 [1]), .I1(rtp_timer_r[1]), .I2(rtp_timer_r[0]), .I3(pass_open_bank_r_lcl_reg), .I4(rstdiv0_sync_r1_reg_rep__21), .O(\rtp_timer_r[1]_i_1__1_n_0 )); FDRE \rtp_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[0]_i_1__2_n_0 ), .Q(rtp_timer_r[0]), .R(1'b0)); FDRE \rtp_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rtp_timer_r[1]_i_1__1_n_0 ), .Q(rtp_timer_r[1]), .R(1'b0)); LUT3 #( .INIT(8'h60)) \starve_limit_cntr_r[0]_i_1__2 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r0), .I2(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[0]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1092" *) LUT4 #( .INIT(16'h6A00)) \starve_limit_cntr_r[1]_i_1__2 (.I0(starve_limit_cntr_r[1]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[1]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1092" *) LUT5 #( .INIT(32'h6AAA0000)) \starve_limit_cntr_r[2]_i_1__2 (.I0(starve_limit_cntr_r[2]), .I1(starve_limit_cntr_r0), .I2(starve_limit_cntr_r[0]), .I3(starve_limit_cntr_r[1]), .I4(\starve_limit_cntr_r_reg[2]_0 ), .O(\starve_limit_cntr_r[2]_i_1__2_n_0 )); LUT6 #( .INIT(64'h00007F0000000000)) \starve_limit_cntr_r[2]_i_2__2 (.I0(starve_limit_cntr_r[0]), .I1(starve_limit_cntr_r[1]), .I2(starve_limit_cntr_r[2]), .I3(granted_col_r_reg), .I4(\grant_r_reg[3]_0 [1]), .I5(req_bank_rdy_r), .O(starve_limit_cntr_r0)); FDRE \starve_limit_cntr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[0]_i_1__2_n_0 ), .Q(starve_limit_cntr_r[0]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[1]_i_1__2_n_0 ), .Q(starve_limit_cntr_r[1]), .R(1'b0)); FDRE \starve_limit_cntr_r_reg[2] (.C(CLK), .CE(1'b1), .D(\starve_limit_cntr_r[2]_i_1__2_n_0 ), .Q(starve_limit_cntr_r[2]), .R(1'b0)); FDRE \wr_this_rank_r_reg[0] (.C(CLK), .CE(1'b1), .D(start_wtp_timer0), .Q(wr_this_rank_r), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_clk_ibuf (mmcm_clk, sys_clk_i); output mmcm_clk; input sys_clk_i; (* RTL_KEEP = "true" *) (* syn_keep = "true" *) wire sys_clk_ibufg; assign mmcm_clk = sys_clk_ibufg; assign sys_clk_ibufg = sys_clk_i; endmodule module ddr3_if_mig_7series_v4_0_col_mach (col_rd_wr_r1, col_rd_wr_r2, sent_col_r2, D, bypass__0, \not_strict_mode.app_rd_data_end_reg , mc_read_idle_r_reg, \read_fifo.tail_r_reg[2]_0 , mc_ref_zq_wip_ns, \read_fifo.tail_r_reg[1]_0 , \read_fifo.fifo_out_data_r_reg[7]_0 , app_rd_data_end_ns, CLK, col_data_buf_addr, ADDRA, DIC, col_rd_wr, mc_cmd, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \rd_buf_indx.rd_buf_indx_r_reg[4] , maint_ref_zq_wip, rstdiv0_sync_r1_reg_rep__23, \not_strict_mode.status_ram.rd_buf_we_r1_reg , SR, \read_fifo.tail_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__0, E); output col_rd_wr_r1; output col_rd_wr_r2; output sent_col_r2; output [3:0]D; output bypass__0; output [7:0]\not_strict_mode.app_rd_data_end_reg ; output mc_read_idle_r_reg; output [1:0]\read_fifo.tail_r_reg[2]_0 ; output mc_ref_zq_wip_ns; output \read_fifo.tail_r_reg[1]_0 ; output \read_fifo.fifo_out_data_r_reg[7]_0 ; output app_rd_data_end_ns; input CLK; input [4:0]col_data_buf_addr; input [2:0]ADDRA; input [0:0]DIC; input col_rd_wr; input [0:0]mc_cmd; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; input maint_ref_zq_wip; input rstdiv0_sync_r1_reg_rep__23; input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; input [0:0]SR; input \read_fifo.tail_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__0; input [0:0]E; wire [2:0]ADDRA; wire CLK; wire [3:0]D; wire [0:0]DIC; wire [0:0]E; wire [0:0]SR; wire app_rd_data_end_ns; wire bypass__0; wire [4:0]col_data_buf_addr; wire col_rd_wr; wire col_rd_wr_r1; wire col_rd_wr_r2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire [7:0]fifo_out_data_ns; wire [4:0]head_r; wire maint_ref_zq_wip; wire [0:0]mc_cmd; wire mc_read_idle_r_reg; wire mc_ref_zq_wip_ns; wire mc_ref_zq_wip_r_i_2_n_0; wire [7:0]\not_strict_mode.app_rd_data_end_reg ; wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [4:0]p_0_in; wire \rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ; wire \rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ; wire [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; wire \read_fifo.fifo_out_data_r_reg[7]_0 ; wire \read_fifo.tail_r[1]_i_1_n_0 ; wire \read_fifo.tail_r[2]_i_1_n_0 ; wire \read_fifo.tail_r[3]_i_1_n_0 ; wire \read_fifo.tail_r[4]_i_1_n_0 ; wire \read_fifo.tail_r_reg[0]_0 ; wire \read_fifo.tail_r_reg[1]_0 ; wire [1:0]\read_fifo.tail_r_reg[2]_0 ; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__23; wire sent_col_r2; wire [3:0]tail_ns; wire [4:3]tail_r; wire [1:0]\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ; wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ; FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[0]), .Q(D[0]), .R(1'b0)); FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[1]), .Q(D[1]), .R(1'b0)); FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[2]), .Q(D[2]), .R(1'b0)); FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (.C(CLK), .CE(1'b1), .D(col_data_buf_addr[3]), .Q(D[3]), .R(1'b0)); LUT6 #( .INIT(64'h9555555555555555)) i___115_i_1 (.I0(tail_r[4]), .I1(\read_fifo.tail_r_reg[2]_0 [0]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\read_fifo.tail_r_reg[1]_0 ), .I4(\read_fifo.tail_r_reg[2]_0 [1]), .I5(tail_r[3]), .O(\read_fifo.fifo_out_data_r_reg[7]_0 )); LUT5 #( .INIT(32'h09000009)) mc_read_idle_r_i_1 (.I0(tail_r[4]), .I1(head_r[4]), .I2(mc_ref_zq_wip_r_i_2_n_0), .I3(head_r[3]), .I4(tail_r[3]), .O(mc_read_idle_r_reg)); LUT6 #( .INIT(64'h0082000000000082)) mc_ref_zq_wip_r_i_1 (.I0(maint_ref_zq_wip), .I1(tail_r[4]), .I2(head_r[4]), .I3(mc_ref_zq_wip_r_i_2_n_0), .I4(head_r[3]), .I5(tail_r[3]), .O(mc_ref_zq_wip_ns)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) mc_ref_zq_wip_r_i_2 (.I0(\read_fifo.tail_r_reg[1]_0 ), .I1(head_r[0]), .I2(head_r[1]), .I3(\read_fifo.tail_r_reg[2]_0 [0]), .I4(head_r[2]), .I5(\read_fifo.tail_r_reg[2]_0 [1]), .O(mc_ref_zq_wip_r_i_2_n_0)); LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data_end_i_1 (.I0(\not_strict_mode.app_rd_data_end_reg [7]), .I1(bypass__0), .I2(\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .O(app_rd_data_end_ns)); FDRE \offset_pipe_0.col_rd_wr_r1_reg (.C(CLK), .CE(1'b1), .D(col_rd_wr), .Q(col_rd_wr_r1), .R(1'b0)); FDRE \offset_pipe_1.col_rd_wr_r2_reg (.C(CLK), .CE(1'b1), .D(col_rd_wr_r1), .Q(col_rd_wr_r2), .R(1'b0)); LUT6 #( .INIT(64'h2000000000002000)) \rd_buf_indx.rd_buf_indx_r[0]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\not_strict_mode.app_rd_data_end_reg [6]), .I2(\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ), .I3(\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ), .I4(\rd_buf_indx.rd_buf_indx_r_reg[4] [1]), .I5(\not_strict_mode.app_rd_data_end_reg [2]), .O(bypass__0)); LUT4 #( .INIT(16'h9009)) \rd_buf_indx.rd_buf_indx_r[0]_i_3 (.I0(\not_strict_mode.app_rd_data_end_reg [5]), .I1(\rd_buf_indx.rd_buf_indx_r_reg[4] [4]), .I2(\not_strict_mode.app_rd_data_end_reg [1]), .I3(\rd_buf_indx.rd_buf_indx_r_reg[4] [0]), .O(\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 )); LUT4 #( .INIT(16'h9009)) \rd_buf_indx.rd_buf_indx_r[0]_i_4 (.I0(\not_strict_mode.app_rd_data_end_reg [3]), .I1(\rd_buf_indx.rd_buf_indx_r_reg[4] [2]), .I2(\not_strict_mode.app_rd_data_end_reg [4]), .I3(\rd_buf_indx.rd_buf_indx_r_reg[4] [3]), .O(\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 )); FDRE \read_fifo.fifo_out_data_r_reg[0] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[0]), .Q(\not_strict_mode.app_rd_data_end_reg [0]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[1] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[1]), .Q(\not_strict_mode.app_rd_data_end_reg [1]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[2] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[2]), .Q(\not_strict_mode.app_rd_data_end_reg [2]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[3] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[3]), .Q(\not_strict_mode.app_rd_data_end_reg [3]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[4] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[4]), .Q(\not_strict_mode.app_rd_data_end_reg [4]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[5] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[5]), .Q(\not_strict_mode.app_rd_data_end_reg [5]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[6]), .Q(\not_strict_mode.app_rd_data_end_reg [6]), .R(1'b0)); FDRE \read_fifo.fifo_out_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(fifo_out_data_ns[7]), .Q(\not_strict_mode.app_rd_data_end_reg [7]), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \read_fifo.fifo_ram[0].RAM32M0 (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRD(head_r), .DIA(col_data_buf_addr[4:3]), .DIB(col_data_buf_addr[2:1]), .DIC({col_data_buf_addr[0],1'b0}), .DID({1'b0,1'b0}), .DOA(fifo_out_data_ns[5:4]), .DOB(fifo_out_data_ns[3:2]), .DOC(fifo_out_data_ns[1:0]), .DOD(\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(1'b1)); LUT6 #( .INIT(64'h000000007FFF8000)) \read_fifo.fifo_ram[0].RAM32M0_i_5 (.I0(\read_fifo.tail_r_reg[2]_0 [0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\read_fifo.tail_r_reg[1]_0 ), .I3(\read_fifo.tail_r_reg[2]_0 [1]), .I4(tail_r[3]), .I5(rstdiv0_sync_r1_reg_rep__23), .O(tail_ns[3])); LUT3 #( .INIT(8'h06)) \read_fifo.fifo_ram[0].RAM32M0_i_6 (.I0(\read_fifo.tail_r_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(rstdiv0_sync_r1_reg_rep__23), .O(tail_ns[0])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \read_fifo.fifo_ram[1].RAM32M0 (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}), .ADDRD(head_r), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b1,DIC}), .DID({1'b0,1'b0}), .DOA(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]), .DOC(fifo_out_data_ns[7:6]), .DOD(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(1'b1)); LUT1 #( .INIT(2'h1)) \read_fifo.head_r[0]_i_1 (.I0(head_r[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair1102" *) LUT2 #( .INIT(4'h6)) \read_fifo.head_r[1]_i_1 (.I0(head_r[0]), .I1(head_r[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair1102" *) LUT3 #( .INIT(8'h6A)) \read_fifo.head_r[2]_i_1 (.I0(head_r[2]), .I1(head_r[1]), .I2(head_r[0]), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair1101" *) LUT4 #( .INIT(16'h6AAA)) \read_fifo.head_r[3]_i_1 (.I0(head_r[3]), .I1(head_r[0]), .I2(head_r[1]), .I3(head_r[2]), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair1101" *) LUT5 #( .INIT(32'h6AAAAAAA)) \read_fifo.head_r[4]_i_1 (.I0(head_r[4]), .I1(head_r[2]), .I2(head_r[1]), .I3(head_r[0]), .I4(head_r[3]), .O(p_0_in[4])); FDRE \read_fifo.head_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in[0]), .Q(head_r[0]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \read_fifo.head_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in[1]), .Q(head_r[1]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \read_fifo.head_r_reg[2] (.C(CLK), .CE(E), .D(p_0_in[2]), .Q(head_r[2]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \read_fifo.head_r_reg[3] (.C(CLK), .CE(E), .D(p_0_in[3]), .Q(head_r[3]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \read_fifo.head_r_reg[4] (.C(CLK), .CE(E), .D(p_0_in[4]), .Q(head_r[4]), .R(rstdiv0_sync_r1_reg_rep__0)); LUT3 #( .INIT(8'h78)) \read_fifo.tail_r[1]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\read_fifo.tail_r_reg[1]_0 ), .I2(\read_fifo.tail_r_reg[2]_0 [0]), .O(\read_fifo.tail_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1100" *) LUT4 #( .INIT(16'h7F80)) \read_fifo.tail_r[2]_i_1 (.I0(\read_fifo.tail_r_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\read_fifo.tail_r_reg[2]_0 [0]), .I3(\read_fifo.tail_r_reg[2]_0 [1]), .O(\read_fifo.tail_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1100" *) LUT5 #( .INIT(32'h6AAAAAAA)) \read_fifo.tail_r[3]_i_1 (.I0(tail_r[3]), .I1(\read_fifo.tail_r_reg[2]_0 [1]), .I2(\read_fifo.tail_r_reg[1]_0 ), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\read_fifo.tail_r_reg[2]_0 [0]), .O(\read_fifo.tail_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \read_fifo.tail_r[4]_i_1 (.I0(tail_r[3]), .I1(\read_fifo.tail_r_reg[2]_0 [1]), .I2(\read_fifo.tail_r_reg[1]_0 ), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\read_fifo.tail_r_reg[2]_0 [0]), .I5(tail_r[4]), .O(\read_fifo.tail_r[4]_i_1_n_0 )); FDRE \read_fifo.tail_r_reg[0] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r_reg[0]_0 ), .Q(\read_fifo.tail_r_reg[1]_0 ), .R(SR)); FDRE \read_fifo.tail_r_reg[1] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[1]_i_1_n_0 ), .Q(\read_fifo.tail_r_reg[2]_0 [0]), .R(SR)); FDRE \read_fifo.tail_r_reg[2] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[2]_i_1_n_0 ), .Q(\read_fifo.tail_r_reg[2]_0 [1]), .R(SR)); FDRE \read_fifo.tail_r_reg[3] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[3]_i_1_n_0 ), .Q(tail_r[3]), .R(SR)); FDRE \read_fifo.tail_r_reg[4] (.C(CLK), .CE(1'b1), .D(\read_fifo.tail_r[4]_i_1_n_0 ), .Q(tail_r[4]), .R(SR)); FDRE sent_col_r2_reg (.C(CLK), .CE(1'b1), .D(mc_cmd), .Q(sent_col_r2), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_byte_group_io (mem_dqs_out, mem_dqs_ts, D0, D1, D2, D3, D4, D5, D6, D7, mem_dq_out, mem_dq_ts, idelay_ld_rst, rst_r4, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0, A_rst_primitives, A_rst_primitives_reg, CLKB0, iserdes_clkdiv, of_dqbus, E, \fine_delay_mod_reg[23] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D0; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst; output rst_r4; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0; input iserdes_clkdiv; input [35:0]of_dqbus; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0; wire [0:0]CTSBUS; wire [3:0]D0; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire [0:0]E; wire LD0; wire data_in_dly_0; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire [7:0]\fine_delay_mod_reg[23] ; wire [23:2]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_i_1_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r3_reg_srl3_n_0; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "TRUE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE \fine_delay_r_reg[11] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [3]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[14] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [4]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[17] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [5]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[20] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [6]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[23] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [7]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[2] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [0]), .Q(fine_delay_r[2]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[5] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [1]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[8] (.C(CLK), .CE(E), .D(\fine_delay_mod_reg[23] [2]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1 (.I0(idelay_ld_rst), .I1(rst_r4), .O(idelay_ld_rst_i_1_n_0)); FDSE idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1_n_0), .Q(idelay_ld_rst), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_0), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[2],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[0].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_0), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D0[3]), .Q2(D0[2]), .Q3(D0[1]), .Q4(D0[0]), .Q5(\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[0].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 " *) SRL16E rst_r3_reg_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(A_rst_primitives), .Q(rst_r3_reg_srl3_n_0)); FDRE rst_r4_reg (.C(CLK), .CE(1'b1), .D(rst_r3_reg_srl3_n_0), .Q(rst_r4), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized0 (mem_dqs_out, mem_dqs_ts, D1, D2, D3, D4, D5, D6, D7, D8, mem_dq_out, mem_dq_ts, idelay_ld_rst_0, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0_3, A_rst_primitives, A_rst_primitives_reg, CLKB0_7, iserdes_clkdiv, of_dqbus, rst_r4, \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[0] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_0; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0_3; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0_7; input iserdes_clkdiv; input [35:0]of_dqbus; input rst_r4; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; input [7:0]\calib_sel_reg[0] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0_7; wire [0:0]CTSBUS; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire LD0_3; wire [7:0]\calib_sel_reg[0] ; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire data_in_dly_8; wire [26:5]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; wire idelay_inc; wire idelay_ld_rst_0; wire idelay_ld_rst_i_1__0_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "TRUE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE \fine_delay_r_reg[11] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [2]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[14] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [3]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[17] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [4]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[20] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [5]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[23] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [6]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[26] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [7]), .Q(fine_delay_r[26]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[5] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [0]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[8] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [1]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1__0 (.I0(idelay_ld_rst_0), .I1(rst_r4), .O(idelay_ld_rst_i_1__0_n_0)); FDSE idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1__0_n_0), .Q(idelay_ld_rst_0), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_8), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[26],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_3), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[8].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_7), .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_8), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D8[3]), .Q2(D8[2]), .Q3(D8[1]), .Q4(D8[0]), .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[8].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized1 (mem_dqs_out, mem_dqs_ts, D1, D2, D3, D4, D5, D6, D7, D8, mem_dq_out, mem_dq_ts, idelay_ld_rst_1, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0_4, A_rst_primitives, A_rst_primitives_reg, CLKB0_8, iserdes_clkdiv, of_dqbus, rst_r4, \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_1; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0_4; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0_8; input iserdes_clkdiv; input [35:0]of_dqbus; input rst_r4; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; input [7:0]\calib_sel_reg[1] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0_8; wire [0:0]CTSBUS; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire LD0_4; wire [7:0]\calib_sel_reg[1] ; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire data_in_dly_8; wire [26:5]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; wire idelay_inc; wire idelay_ld_rst_1; wire idelay_ld_rst_i_1__1_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "TRUE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE \fine_delay_r_reg[11] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [2]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[14] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [3]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[17] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [4]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[20] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [5]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[23] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [6]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[26] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [7]), .Q(fine_delay_r[26]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[5] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [0]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[8] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[1] [1]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1__1 (.I0(idelay_ld_rst_1), .I1(rst_r4), .O(idelay_ld_rst_i_1__1_n_0)); FDSE idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1__1_n_0), .Q(idelay_ld_rst_1), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_8), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[26],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_4), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[8].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_8), .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_8), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D8[3]), .Q2(D8[2]), .Q3(D8[1]), .Q4(D8[0]), .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[8].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized2 (mem_dqs_out, mem_dqs_ts, D1, D2, D3, D4, D5, D6, D7, D8, mem_dq_out, mem_dq_ts, idelay_ld_rst_2, oserdes_clk, oserdes_clkdiv, po_oserdes_rst, DTSBUS, oserdes_clk_delayed, DQSBUS, CTSBUS, CLK, \gen_byte_sel_div1.calib_in_common_reg , mem_dq_in, idelay_inc, LD0_5, A_rst_primitives, A_rst_primitives_reg, CLKB0_9, iserdes_clkdiv, of_dqbus, rst_r4, \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[0] ); output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_2; input oserdes_clk; input oserdes_clkdiv; input po_oserdes_rst; input [1:0]DTSBUS; input oserdes_clk_delayed; input [1:0]DQSBUS; input [0:0]CTSBUS; input CLK; input \gen_byte_sel_div1.calib_in_common_reg ; input [7:0]mem_dq_in; input idelay_inc; input LD0_5; input A_rst_primitives; input A_rst_primitives_reg; input CLKB0_9; input iserdes_clkdiv; input [35:0]of_dqbus; input rst_r4; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; input [7:0]\calib_sel_reg[0] ; wire A_rst_primitives; wire A_rst_primitives_reg; wire CLK; wire CLKB0_9; wire [0:0]CTSBUS; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [1:0]DQSBUS; wire [1:0]DTSBUS; wire LD0_5; wire [7:0]\calib_sel_reg[0] ; wire data_in_dly_1; wire data_in_dly_2; wire data_in_dly_3; wire data_in_dly_4; wire data_in_dly_5; wire data_in_dly_6; wire data_in_dly_7; wire data_in_dly_8; wire [26:5]fine_delay_r; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_0 ; wire idelay_inc; wire idelay_ld_rst_2; wire idelay_ld_rst_i_1__2_n_0; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire [35:0]of_dqbus; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire po_oserdes_rst; wire rst_r4; wire tbyte_out; wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ; wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ; wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ; wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ; wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqs (.C(oserdes_clk_delayed), .CE(1'b1), .D1(DQSBUS[0]), .D2(DQSBUS[1]), .Q(mem_dqs_out), .R(1'b0), .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "TRUE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \dqs_gen.oddr_dqsts (.C(oserdes_clk_delayed), .CE(1'b1), .D1(CTSBUS), .D2(CTSBUS), .Q(mem_dqs_ts), .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ), .S(1'b0)); FDRE \fine_delay_r_reg[11] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [2]), .Q(fine_delay_r[11]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[14] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [3]), .Q(fine_delay_r[14]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[17] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [4]), .Q(fine_delay_r[17]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[20] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [5]), .Q(fine_delay_r[20]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[23] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [6]), .Q(fine_delay_r[23]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[26] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [7]), .Q(fine_delay_r[26]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[5] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [0]), .Q(fine_delay_r[5]), .R(A_rst_primitives)); FDRE \fine_delay_r_reg[8] (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg_0 ), .D(\calib_sel_reg[0] [1]), .Q(fine_delay_r[8]), .R(A_rst_primitives)); LUT2 #( .INIT(4'h2)) idelay_ld_rst_i_1__2 (.I0(idelay_ld_rst_2), .I1(rst_r4), .O(idelay_ld_rst_i_1__2_n_0)); FDSE idelay_ld_rst_reg (.C(CLK), .CE(1'b1), .D(idelay_ld_rst_i_1__2_n_0), .Q(idelay_ld_rst_2), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_1), .IDATAIN(mem_dq_in[0]), .IFDLY({fine_delay_r[5],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[1].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[0]), .DDLY(data_in_dly_1), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D1[3]), .Q2(D1[2]), .Q3(D1[1]), .Q4(D1[0]), .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_2), .IDATAIN(mem_dq_in[1]), .IFDLY({fine_delay_r[8],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[2].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[1]), .DDLY(data_in_dly_2), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D2[3]), .Q2(D2[2]), .Q3(D2[1]), .Q4(D2[0]), .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_3), .IDATAIN(mem_dq_in[2]), .IFDLY({fine_delay_r[11],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[3].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[2]), .DDLY(data_in_dly_3), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D3[3]), .Q2(D3[2]), .Q3(D3[1]), .Q4(D3[0]), .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_4), .IDATAIN(mem_dq_in[3]), .IFDLY({fine_delay_r[14],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[4].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[3]), .DDLY(data_in_dly_4), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D4[3]), .Q2(D4[2]), .Q3(D4[1]), .Q4(D4[0]), .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_5), .IDATAIN(mem_dq_in[4]), .IFDLY({fine_delay_r[17],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[5].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[4]), .DDLY(data_in_dly_5), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D5[3]), .Q2(D5[2]), .Q3(D5[1]), .Q4(D5[0]), .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_6), .IDATAIN(mem_dq_in[5]), .IFDLY({fine_delay_r[20],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[6].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[5]), .DDLY(data_in_dly_6), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D6[3]), .Q2(D6[2]), .Q3(D6[1]), .Q4(D6[0]), .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_7), .IDATAIN(mem_dq_in[6]), .IFDLY({fine_delay_r[23],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[7].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[6]), .DDLY(data_in_dly_7), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D7[3]), .Q2(D7[2]), .Q3(D7[1]), .Q4(D7[0]), .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYE2_FINEDELAY #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .FINEDELAY("ADD_DLY"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .IS_C_INVERTED(1'b0), .IS_DATAIN_INVERTED(1'b0), .IS_IDATAIN_INVERTED(1'b0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(400.000000), .SIGNAL_PATTERN("DATA")) \input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 (.C(CLK), .CE(\gen_byte_sel_div1.calib_in_common_reg ), .CINVCTRL(1'b0), .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]), .DATAIN(1'b0), .DATAOUT(data_in_dly_8), .IDATAIN(mem_dq_in[7]), .IFDLY({fine_delay_r[26],1'b0,1'b0}), .INC(idelay_inc), .LD(LD0_5), .LDPIPEEN(1'b0), .REGRST(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4), .DYN_CLKDIV_INV_EN("FALSE"), .DYN_CLK_INV_EN("FALSE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .INIT_Q3(1'b0), .INIT_Q4(1'b0), .INTERFACE_TYPE("MEMORY_DDR3"), .IOBDELAY("IFD"), .IS_CLKB_INVERTED(1'b1), .IS_CLKDIVP_INVERTED(1'b0), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .IS_OCLKB_INVERTED(1'b0), .IS_OCLK_INVERTED(1'b0), .NUM_CE(2), .OFB_USED("FALSE"), .SERDES_MODE("MASTER"), .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0)) \input_[8].iserdes_dq_.iserdesdq (.BITSLIP(1'b0), .CE1(1'b1), .CE2(1'b1), .CLK(A_rst_primitives_reg), .CLKB(CLKB0_9), .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ), .CLKDIVP(iserdes_clkdiv), .D(mem_dq_in[7]), .DDLY(data_in_dly_8), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ), .OCLK(oserdes_clk), .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ), .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ), .Q1(D8[3]), .Q2(D8[2]), .Q3(D8[1]), .Q4(D8[0]), .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ), .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ), .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ), .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ), .RST(1'b0), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[1].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[0]), .D2(of_dqbus[1]), .D3(of_dqbus[2]), .D4(of_dqbus[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[0])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[2].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[4]), .D2(of_dqbus[5]), .D3(of_dqbus[6]), .D4(of_dqbus[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[1])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[3].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[8]), .D2(of_dqbus[9]), .D3(of_dqbus[10]), .D4(of_dqbus[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[2])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[4].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[12]), .D2(of_dqbus[13]), .D3(of_dqbus[14]), .D4(of_dqbus[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[3])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[5].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[16]), .D2(of_dqbus[17]), .D3(of_dqbus[18]), .D4(of_dqbus[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[4])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[6].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[20]), .D2(of_dqbus[21]), .D3(of_dqbus[22]), .D4(of_dqbus[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[5])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[7].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[24]), .D2(of_dqbus[25]), .D3(of_dqbus[26]), .D4(of_dqbus[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[6])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[8].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[28]), .D2(of_dqbus[29]), .D3(of_dqbus[30]), .D4(of_dqbus[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[7])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(4)) \output_[9].oserdes_dq_.ddr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(of_dqbus[32]), .D2(of_dqbus[33]), .D3(of_dqbus[34]), .D4(of_dqbus[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(tbyte_out), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(mem_dq_ts[8])); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("DDR"), .DATA_WIDTH(4), .INIT_OQ(1'b1), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b1), .SRVAL_TQ(1'b1), .TBYTE_CTL("TRUE"), .TBYTE_SRC("TRUE"), .TRISTATE_WIDTH(4)) \slave_ts.oserdes_slave_ts (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(1'b0), .D2(1'b0), .D3(1'b0), .D4(1'b0), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ), .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ), .T1(DTSBUS[0]), .T2(DTSBUS[0]), .T3(DTSBUS[1]), .T4(DTSBUS[1]), .TBYTEIN(tbyte_out), .TBYTEOUT(tbyte_out), .TCE(1'b1), .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ), .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized3 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, oserdes_rst); output [1:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [7:0]oserdes_dq; input oserdes_rst; wire [1:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [7:0]oserdes_dq; wire oserdes_rst; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[0].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[1].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized4 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, oserdes_rst); output [2:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [11:0]oserdes_dq; input oserdes_rst; wire [2:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [11:0]oserdes_dq; wire oserdes_rst; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[10].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[11].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[8]), .D2(oserdes_dq[9]), .D3(oserdes_dq[10]), .D4(oserdes_dq[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[4].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized5 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, po_oserdes_rst); output [9:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [39:0]oserdes_dq; input po_oserdes_rst; wire [9:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [39:0]oserdes_dq; wire po_oserdes_rst; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[10].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[32]), .D2(oserdes_dq[33]), .D3(oserdes_dq[34]), .D4(oserdes_dq[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[11].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[36]), .D2(oserdes_dq[37]), .D3(oserdes_dq[38]), .D4(oserdes_dq[39]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[9]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[2].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[3].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[4].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[8]), .D2(oserdes_dq[9]), .D3(oserdes_dq[10]), .D4(oserdes_dq[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[5].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[12]), .D2(oserdes_dq[13]), .D3(oserdes_dq[14]), .D4(oserdes_dq[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[6].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[16]), .D2(oserdes_dq[17]), .D3(oserdes_dq[18]), .D4(oserdes_dq[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[7].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[20]), .D2(oserdes_dq[21]), .D3(oserdes_dq[22]), .D4(oserdes_dq[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[8].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[24]), .D2(oserdes_dq[25]), .D3(oserdes_dq[26]), .D4(oserdes_dq[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[9].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[28]), .D2(oserdes_dq[29]), .D3(oserdes_dq[30]), .D4(oserdes_dq[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_group_io" *) module ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized6 (mem_dq_out, oserdes_clk, oserdes_clkdiv, oserdes_dq, po_oserdes_rst); output [8:0]mem_dq_out; input oserdes_clk; input oserdes_clkdiv; input [35:0]oserdes_dq; input po_oserdes_rst; wire [8:0]mem_dq_out; wire oserdes_clk; wire oserdes_clkdiv; wire [35:0]oserdes_dq; wire po_oserdes_rst; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ; wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[1].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[0]), .D2(oserdes_dq[1]), .D3(oserdes_dq[2]), .D4(oserdes_dq[3]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[0]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[2].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[4]), .D2(oserdes_dq[5]), .D3(oserdes_dq[6]), .D4(oserdes_dq[7]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[1]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[3].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[8]), .D2(oserdes_dq[9]), .D3(oserdes_dq[10]), .D4(oserdes_dq[11]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[2]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[4].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[12]), .D2(oserdes_dq[13]), .D3(oserdes_dq[14]), .D4(oserdes_dq[15]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[3]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[5].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[16]), .D2(oserdes_dq[17]), .D3(oserdes_dq[18]), .D4(oserdes_dq[19]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[4]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[6].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[20]), .D2(oserdes_dq[21]), .D3(oserdes_dq[22]), .D4(oserdes_dq[23]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[5]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[7].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[24]), .D2(oserdes_dq[25]), .D3(oserdes_dq[26]), .D4(oserdes_dq[27]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[6]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[8].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[28]), .D2(oserdes_dq[29]), .D3(oserdes_dq[30]), .D4(oserdes_dq[31]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[7]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) OSERDESE2 #( .DATA_RATE_OQ("SDR"), .DATA_RATE_TQ("SDR"), .DATA_WIDTH(4), .INIT_OQ(1'b0), .INIT_TQ(1'b1), .IS_CLKDIV_INVERTED(1'b0), .IS_CLK_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .IS_D3_INVERTED(1'b0), .IS_D4_INVERTED(1'b0), .IS_D5_INVERTED(1'b0), .IS_D6_INVERTED(1'b0), .IS_D7_INVERTED(1'b0), .IS_D8_INVERTED(1'b0), .IS_T1_INVERTED(1'b0), .IS_T2_INVERTED(1'b0), .IS_T3_INVERTED(1'b0), .IS_T4_INVERTED(1'b0), .SERDES_MODE("MASTER"), .SRVAL_OQ(1'b0), .SRVAL_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE"), .TRISTATE_WIDTH(1)) \output_[9].oserdes_dq_.sdr.oserdes_dq_i (.CLK(oserdes_clk), .CLKDIV(oserdes_clkdiv), .D1(oserdes_dq[32]), .D2(oserdes_dq[33]), .D3(oserdes_dq[34]), .D4(oserdes_dq[35]), .D5(1'b0), .D6(1'b0), .D7(1'b0), .D8(1'b0), .OCE(1'b1), .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ), .OQ(mem_dq_out[8]), .RST(po_oserdes_rst), .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ), .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ), .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ), .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ), .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ), .TCE(1'b1), .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ), .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED )); endmodule module ddr3_if_mig_7series_v4_0_ddr_byte_lane (\pi_dqs_found_lanes_r1_reg[0] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , pi_phase_locked_all_r1_reg, COUNTERREADVAL, \po_counter_read_val_reg[8] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, if_empty_r, \wr_ptr_reg[1] , idelay_ld_rst, rst_r4, \not_strict_mode.app_rd_data_reg[252] , \my_empty_reg[1] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[24] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7] , A_byte_rd_en, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0, CLKB0, phy_if_reset, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \byte_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \byte_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 , \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , A, phy_dout, E, \fine_delay_mod_reg[23] , D_byte_rd_en, B_byte_rd_en, if_empty_r_0, my_empty, \po_stg2_wrcal_cnt_reg[1] ); output [0:0]\pi_dqs_found_lanes_r1_reg[0] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output pi_phase_locked_all_r1_reg; output [5:0]COUNTERREADVAL; output [8:0]\po_counter_read_val_reg[8] ; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output [0:0]if_empty_r; output [0:0]\wr_ptr_reg[1] ; output idelay_ld_rst; output rst_r4; output \not_strict_mode.app_rd_data_reg[252] ; output \my_empty_reg[1] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[24] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7] ; output A_byte_rd_en; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[287] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input \byte_r_reg[0] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input \byte_r_reg[1] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]A; input [71:0]phy_dout; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; input D_byte_rd_en; input B_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]my_empty; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]A; wire A_byte_rd_en; wire A_rst_primitives; wire B_byte_rd_en; wire CLK; wire CLKB0; wire [5:0]COUNTERLOADVAL; wire [5:0]COUNTERREADVAL; wire D_byte_rd_en; wire [0:0]E; wire LD0; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire \calib_sel_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire [63:0]\data_bytes_r_reg[63] ; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ; wire [7:0]\fine_delay_mod_reg[23] ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire [3:0]if_d0; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_wrdata_en; wire [0:0]my_empty; wire \my_empty_reg[1] ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire p_0_out; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_7 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_reset; wire [0:0]\pi_dqs_found_lanes_r1_reg[0] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [79:0]rd_data; wire [65:1]rd_data_r; wire [1:0]\rd_mux_sel_r_reg[1] ; wire \read_fifo.fifo_out_data_r_reg[6] ; wire rst_r4; wire sync_pulse; wire [0:0]\wr_ptr_reg[1] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[287] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0(CLKB0), .CTSBUS(oserdes_dqs_ts[0]), .D0(if_d0), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .E(E), .LD0(LD0), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23] ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus({of_dqbus[39:36],of_dqbus[31:0]}), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_data[0]), .Q(\not_strict_mode.app_rd_data_reg[31]_0 ), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (.C(CLK), .CE(1'b1), .D(rd_data[1]), .Q(rd_data_r[1]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (.C(CLK), .CE(1'b1), .D(rd_data[2]), .Q(rd_data_r[2]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (.C(CLK), .CE(1'b1), .D(rd_data[3]), .Q(rd_data_r[3]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (.C(CLK), .CE(1'b1), .D(rd_data[4]), .Q(rd_data_r[4]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (.C(CLK), .CE(1'b1), .D(rd_data[5]), .Q(rd_data_r[5]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(rd_data_r[8]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_8 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A(A), .A_byte_rd_en(A_byte_rd_en), .B_byte_rd_en(B_byte_rd_en), .CLK(CLK), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r,\not_strict_mode.app_rd_data_reg[31]_0 }), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .if_empty_r_0(if_empty_r_0), .ififo_rst(ififo_rst), .my_empty(my_empty), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[252]_0 (\not_strict_mode.app_rd_data_reg[252]_0 ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255]_0 ), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31]_1 ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .p_0_out(p_0_out), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] )); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0(if_d0), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8({1'b0,1'b0,1'b0,1'b0}), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized2 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[287] (\write_buffer.wr_buf_out_data_reg[287] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0(\write_buffer.wr_buf_out_data_reg[255] ), .D1(\write_buffer.wr_buf_out_data_reg[254] ), .D2(\write_buffer.wr_buf_out_data_reg[253] ), .D3(\write_buffer.wr_buf_out_data_reg[252] ), .D4(\write_buffer.wr_buf_out_data_reg[251] ), .D5(\write_buffer.wr_buf_out_data_reg[250] ), .D6(\write_buffer.wr_buf_out_data_reg[249] ), .D7(\write_buffer.wr_buf_out_data_reg[248] ), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(COUNTERLOADVAL), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(COUNTERREADVAL), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[0] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(pi_phase_locked_all_r1_reg), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(\phaser_in_gen.phaser_in_n_7 ), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(\po_counter_read_val_reg[8] ), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized0 (\pi_dqs_found_lanes_r1_reg[1] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , B_rclk, COUNTERREADVAL, \po_counter_read_val_reg[8] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, if_empty_r, \rd_ptr_timing_reg[1] , idelay_ld_rst_0, \not_strict_mode.app_rd_data_reg[244] , \my_empty_reg[1] , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , phy_rddata_en, mux_rd_valid_r_reg, \read_fifo.tail_r_reg[0] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[247]_0 , pi_phase_locked_all_r1_reg, phy_if_empty_r_reg, \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7] , B_byte_rd_en, Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0_3, CLKB0_7, phy_if_reset, mux_wrdata_en, rst_r4, \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[286] , if_empty_r_0, my_empty, \my_empty_reg[4] , prbs_rdlvl_start_reg, out, tail_r, \read_fifo.fifo_out_data_r_reg[6]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , A_rst_primitives_reg, A_rst_primitives_reg_0, A_rst_primitives_reg_1, phy_dout, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[0]_0 , D_byte_rd_en, A_byte_rd_en); output [0:0]\pi_dqs_found_lanes_r1_reg[1] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output B_rclk; output [5:0]COUNTERREADVAL; output [8:0]\po_counter_read_val_reg[8] ; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output [0:0]if_empty_r; output [0:0]\rd_ptr_timing_reg[1] ; output idelay_ld_rst_0; output \not_strict_mode.app_rd_data_reg[244] ; output \my_empty_reg[1] ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output phy_rddata_en; output mux_rd_valid_r_reg; output \read_fifo.tail_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[247]_0 ; output pi_phase_locked_all_r1_reg; output phy_if_empty_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7] ; output B_byte_rd_en; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0_3; input CLKB0_7; input phy_if_reset; input mux_wrdata_en; input rst_r4; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[286] ; input [0:0]if_empty_r_0; input [1:0]my_empty; input \my_empty_reg[4] ; input prbs_rdlvl_start_reg; input out; input [0:0]tail_r; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input A_rst_primitives_reg; input A_rst_primitives_reg_0; input A_rst_primitives_reg_1; input [71:0]phy_dout; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; input [7:0]\calib_sel_reg[0]_0 ; input D_byte_rd_en; input A_byte_rd_en; wire A_byte_rd_en; wire A_rst_primitives; wire A_rst_primitives_reg; wire A_rst_primitives_reg_0; wire A_rst_primitives_reg_1; wire B_byte_rd_en; wire B_rclk; wire CLK; wire CLKB0_7; wire [5:0]COUNTERREADVAL; wire D_byte_rd_en; wire LD0_3; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \calib_sel_reg[0] ; wire [7:0]\calib_sel_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; wire idelay_inc; wire idelay_ld_rst_0; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire [3:0]if_d8; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_rd_valid_r_reg; wire mux_wrdata_en; wire [1:0]my_empty; wire \my_empty_reg[1] ; wire \my_empty_reg[4] ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire [63:0]\not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[247]_0 ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_6 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_rddata_en; wire [0:0]\pi_dqs_found_lanes_r1_reg[1] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rd_buf_we; wire [79:0]rd_data; wire [71:6]rd_data_r; wire [0:0]\rd_ptr_timing_reg[1] ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire rst_r4; wire sync_pulse; wire [0:0]tail_r; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[286] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized0 ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0_7(CLKB0_7), .CTSBUS(oserdes_dqs_ts[0]), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .D8(if_d8), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .LD0_3(LD0_3), .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .idelay_inc(idelay_inc), .idelay_ld_rst_0(idelay_ld_rst_0), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus(of_dqbus[39:4]), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (.C(CLK), .CE(1'b1), .D(rd_data[66]), .Q(rd_data_r[66]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (.C(CLK), .CE(1'b1), .D(rd_data[67]), .Q(rd_data_r[67]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (.C(CLK), .CE(1'b1), .D(rd_data[68]), .Q(rd_data_r[68]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (.C(CLK), .CE(1'b1), .D(rd_data[69]), .Q(rd_data_r[69]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (.C(CLK), .CE(1'b1), .D(rd_data[70]), .Q(rd_data_r[70]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (.C(CLK), .CE(1'b1), .D(rd_data[71]), .Q(rd_data_r[71]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(\not_strict_mode.app_rd_data_reg[23]_0 ), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_7 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A_byte_rd_en(A_byte_rd_en), .B_byte_rd_en(B_byte_rd_en), .CLK(CLK), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r[71:9],\not_strict_mode.app_rd_data_reg[23]_0 ,rd_data_r[7:6]}), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r), .if_empty_r_0(if_empty_r_0), .ififo_rst(ififo_rst), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .my_empty(my_empty), .\my_empty_reg[4]_0 (\my_empty_reg[4] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[22] (\not_strict_mode.app_rd_data_reg[22] ), .\not_strict_mode.app_rd_data_reg[23] (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23]_1 ), .\not_strict_mode.app_rd_data_reg[240] (\not_strict_mode.app_rd_data_reg[240] ), .\not_strict_mode.app_rd_data_reg[241] (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[244]_0 (\not_strict_mode.app_rd_data_reg[244]_0 ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247]_0 ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .out(out), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_rddata_en(phy_rddata_en), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .tail_r(tail_r)); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0({1'b0,1'b0,1'b0,1'b0}), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8(if_d8), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized3 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[286] (\write_buffer.wr_buf_out_data_reg[286] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D1(\write_buffer.wr_buf_out_data_reg[247] ), .D2(\write_buffer.wr_buf_out_data_reg[246] ), .D3(\write_buffer.wr_buf_out_data_reg[245] ), .D4(\write_buffer.wr_buf_out_data_reg[244] ), .D5(\write_buffer.wr_buf_out_data_reg[243] ), .D6(\write_buffer.wr_buf_out_data_reg[242] ), .D7(\write_buffer.wr_buf_out_data_reg[241] ), .D8(\write_buffer.wr_buf_out_data_reg[240] ), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(COUNTERREADVAL), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[1] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(B_rclk), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(\po_counter_read_val_reg[8] ), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT4 #( .INIT(16'h8000)) pi_phase_locked_all_inferred_i_1 (.I0(\phaser_in_gen.phaser_in_n_6 ), .I1(A_rst_primitives_reg), .I2(A_rst_primitives_reg_0), .I3(A_rst_primitives_reg_1), .O(pi_phase_locked_all_r1_reg)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized1 (\pi_dqs_found_lanes_r1_reg[2] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , pi_phase_locked_all_r1_reg, COUNTERREADVAL, \po_counter_read_val_reg[8] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, if_empty_r, \rd_ptr_timing_reg[1] , idelay_ld_rst_1, \not_strict_mode.app_rd_data_reg[236] , \my_empty_reg[1] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[239]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7] , C_byte_rd_en, Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[1] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0_4, CLKB0_8, phy_if_reset, mux_wrdata_en, rst_r4, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[285] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , phy_dout, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[1]_0 , D_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4] ); output [0:0]\pi_dqs_found_lanes_r1_reg[2] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output pi_phase_locked_all_r1_reg; output [5:0]COUNTERREADVAL; output [8:0]\po_counter_read_val_reg[8] ; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output [0:0]if_empty_r; output [1:0]\rd_ptr_timing_reg[1] ; output idelay_ld_rst_1; output \not_strict_mode.app_rd_data_reg[236] ; output \my_empty_reg[1] ; output [63:0]\not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[239]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7] ; output C_byte_rd_en; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[1] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0_4; input CLKB0_8; input phy_if_reset; input mux_wrdata_en; input rst_r4; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[285] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [71:0]phy_dout; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; input [7:0]\calib_sel_reg[1]_0 ; input D_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4] ; wire A_byte_rd_en; wire A_rst_primitives; wire CLK; wire CLKB0_8; wire [5:0]COUNTERREADVAL; wire C_byte_rd_en; wire D_byte_rd_en; wire LD0_4; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \calib_sel_reg[1] ; wire [7:0]\calib_sel_reg[1]_0 ; wire [5:0]\calib_zero_inputs_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; wire idelay_inc; wire idelay_ld_rst_1; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire [3:0]if_d8; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_wrdata_en; wire \my_empty_reg[1] ; wire [0:0]\my_empty_reg[4] ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire [63:0]\not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[239]_0 ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_7 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_reset; wire [0:0]\pi_dqs_found_lanes_r1_reg[2] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire [79:0]rd_data; wire [71:6]rd_data_r; wire [1:0]\rd_ptr_timing_reg[1] ; wire \read_fifo.fifo_out_data_r_reg[6] ; wire rst_r4; wire sync_pulse; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[285] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized1 ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0_8(CLKB0_8), .CTSBUS(oserdes_dqs_ts[0]), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .D8(if_d8), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .LD0_4(LD0_4), .\calib_sel_reg[1] (\calib_sel_reg[1]_0 ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .idelay_inc(idelay_inc), .idelay_ld_rst_1(idelay_ld_rst_1), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus(of_dqbus[39:4]), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (.C(CLK), .CE(1'b1), .D(rd_data[66]), .Q(rd_data_r[66]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (.C(CLK), .CE(1'b1), .D(rd_data[67]), .Q(rd_data_r[67]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (.C(CLK), .CE(1'b1), .D(rd_data[68]), .Q(rd_data_r[68]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (.C(CLK), .CE(1'b1), .D(rd_data[69]), .Q(rd_data_r[69]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (.C(CLK), .CE(1'b1), .D(rd_data[70]), .Q(rd_data_r[70]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (.C(CLK), .CE(1'b1), .D(rd_data[71]), .Q(rd_data_r[71]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(\not_strict_mode.app_rd_data_reg[15]_0 ), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_6 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A_byte_rd_en(A_byte_rd_en), .CLK(CLK), .C_byte_rd_en(C_byte_rd_en), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r[71:9],\not_strict_mode.app_rd_data_reg[15]_0 ,rd_data_r[7:6]}), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r), .if_empty_r_0(if_empty_r_0), .ififo_rst(ififo_rst), .\my_empty_reg[4]_0 (\my_empty_reg[4] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15]_1 ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ), .\not_strict_mode.app_rd_data_reg[233] (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[234] (\not_strict_mode.app_rd_data_reg[234] ), .\not_strict_mode.app_rd_data_reg[235] (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[236] (\not_strict_mode.app_rd_data_reg[236] ), .\not_strict_mode.app_rd_data_reg[236]_0 (\not_strict_mode.app_rd_data_reg[236]_0 ), .\not_strict_mode.app_rd_data_reg[237] (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[238] (\not_strict_mode.app_rd_data_reg[238] ), .\not_strict_mode.app_rd_data_reg[239] (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239]_0 ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[72] (\not_strict_mode.app_rd_data_reg[72] ), .\not_strict_mode.app_rd_data_reg[73] (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[74] (\not_strict_mode.app_rd_data_reg[74] ), .\not_strict_mode.app_rd_data_reg[75] (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[76] (\not_strict_mode.app_rd_data_reg[76] ), .\not_strict_mode.app_rd_data_reg[77] (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[78] (\not_strict_mode.app_rd_data_reg[78] ), .\not_strict_mode.app_rd_data_reg[79] (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .phy_if_empty_r_reg(\rd_ptr_timing_reg[1] [0]), .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] [1]), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] )); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0({1'b0,1'b0,1'b0,1'b0}), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8(if_d8), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized4 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[285] (\write_buffer.wr_buf_out_data_reg[285] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D1(\write_buffer.wr_buf_out_data_reg[239] ), .D2(\write_buffer.wr_buf_out_data_reg[238] ), .D3(\write_buffer.wr_buf_out_data_reg[237] ), .D4(\write_buffer.wr_buf_out_data_reg[236] ), .D5(\write_buffer.wr_buf_out_data_reg[235] ), .D6(\write_buffer.wr_buf_out_data_reg[234] ), .D7(\write_buffer.wr_buf_out_data_reg[233] ), .D8(\write_buffer.wr_buf_out_data_reg[232] ), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ), .COUNTERREADEN(\calib_sel_reg[1] ), .COUNTERREADVAL(COUNTERREADVAL), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[2] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(pi_phase_locked_all_r1_reg), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(\phaser_in_gen.phaser_in_n_7 ), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[1] ), .COUNTERREADVAL(\po_counter_read_val_reg[8] ), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized2 (\pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , pi_phase_locked_all_r1_reg, mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, idelay_ld_rst_2, \not_strict_mode.app_rd_data_reg[228] , \my_empty_reg[1] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[0] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[231]_0 , mux_rd_valid_r_reg, \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7] , D_byte_rd_en, D, \po_counter_read_val_reg[8] , Q, phaser_ctl_bus, \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, A_rst_primitives, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, PCENABLECALIB, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0_5, CLKB0_9, phy_if_reset, mux_wrdata_en, rst_r4, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[284] , \read_fifo.fifo_out_data_r_reg[6] , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \my_empty_reg[4] , if_empty_r, phy_dout, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[0]_0 , C_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4]_0 , COUNTERREADVAL, \calib_sel_reg[1] , A_rst_primitives_reg, A_rst_primitives_reg_0, A_rst_primitives_reg_1, A_rst_primitives_reg_2, A_rst_primitives_reg_3); output [0:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output pi_phase_locked_all_r1_reg; output [0:0]mem_dqs_out; output [0:0]mem_dqs_ts; output [8:0]mem_dq_out; output [8:0]mem_dq_ts; output idelay_ld_rst_2; output \not_strict_mode.app_rd_data_reg[228] ; output \my_empty_reg[1] ; output [63:0]\not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[0] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[231]_0 ; output mux_rd_valid_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7] ; output D_byte_rd_en; output [5:0]D; output [8:0]\po_counter_read_val_reg[8] ; output [2:0]Q; input [3:0]phaser_ctl_bus; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [0:0]mem_dqs_in; input A_rst_primitives; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [1:0]PCENABLECALIB; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [7:0]mem_dq_in; input idelay_inc; input LD0_5; input CLKB0_9; input phy_if_reset; input mux_wrdata_en; input rst_r4; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[284] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [0:0]\my_empty_reg[4] ; input [0:0]if_empty_r; input [71:0]phy_dout; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; input [7:0]\calib_sel_reg[0]_0 ; input C_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4]_0 ; input [5:0]COUNTERREADVAL; input [1:0]\calib_sel_reg[1] ; input [5:0]A_rst_primitives_reg; input [5:0]A_rst_primitives_reg_0; input [8:0]A_rst_primitives_reg_1; input [8:0]A_rst_primitives_reg_2; input [8:0]A_rst_primitives_reg_3; wire A_byte_rd_en; wire A_rst_primitives; wire [5:0]A_rst_primitives_reg; wire [5:0]A_rst_primitives_reg_0; wire [8:0]A_rst_primitives_reg_1; wire [8:0]A_rst_primitives_reg_2; wire [8:0]A_rst_primitives_reg_3; wire CLK; wire CLKB0_9; wire [5:0]COUNTERREADVAL; wire C_byte_rd_en; wire [5:0]D; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_byte_rd_en; wire [5:0]D_pi_counter_read_val; wire [8:0]D_po_counter_read_val; wire LD0_5; wire [1:0]PCENABLECALIB; wire [2:0]Q; wire \calib_sel_reg[0] ; wire [7:0]\calib_sel_reg[0]_0 ; wire [1:0]\calib_sel_reg[1] ; wire [5:0]\calib_zero_inputs_reg[0] ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_indec_reg; wire delay_done_r4_reg; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_3 ; wire idelay_inc; wire idelay_ld_rst_2; wire [3:0]if_d1; wire [3:0]if_d2; wire [3:0]if_d3; wire [3:0]if_d4; wire [3:0]if_d5; wire [3:0]if_d6; wire [3:0]if_d7; wire [3:0]if_d8; wire if_empty_; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire [3:3]if_empty_r_1; wire ififo_rst; wire ififo_wr_enable; wire \in_fifo_gen.in_fifo_n_0 ; wire \in_fifo_gen.in_fifo_n_1 ; wire \in_fifo_gen.in_fifo_n_3 ; wire init_calib_complete_reg_rep; wire iserdes_clkdiv; wire [7:0]mem_dq_in; wire [8:0]mem_dq_out; wire [8:0]mem_dq_ts; wire [0:0]mem_dqs_in; wire [0:0]mem_dqs_out; wire [0:0]mem_dqs_ts; wire mem_refclk; wire mux_rd_valid_r_reg; wire mux_wrdata_en; wire \my_empty_reg[1] ; wire [0:0]\my_empty_reg[4] ; wire [0:0]\my_empty_reg[4]_0 ; wire [63:0]\my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire [63:0]\not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[231]_0 ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [7:0]of_d9; wire [39:0]of_dqbus; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire ofifo_rst; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire out_fifo_n_3; wire [3:0]phaser_ctl_bus; wire \phaser_in_gen.phaser_in_n_1 ; wire \phaser_in_gen.phaser_in_n_2 ; wire \phaser_in_gen.phaser_in_n_5 ; wire \phaser_in_gen.phaser_in_n_7 ; wire phaser_out_n_0; wire phaser_out_n_1; wire [71:0]phy_dout; wire phy_if_reset; wire [0:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_phase_locked_all_r1_reg; wire pi_stg2_f_incdec_reg; wire [8:0]\po_counter_read_val_reg[8] ; wire po_oserdes_rst; wire po_rd_enable; wire [79:0]rd_data; wire [71:6]rd_data_r; wire \read_fifo.fifo_out_data_r_reg[6] ; wire rst_r4; wire sync_pulse; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[284] ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ; wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ; wire [7:4]NLW_out_fifo_Q5_UNCONNECTED; wire [7:4]NLW_out_fifo_Q6_UNCONNECTED; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized2 ddr_byte_group_io (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .CLK(CLK), .CLKB0_9(CLKB0_9), .CTSBUS(oserdes_dqs_ts[0]), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5(if_d5), .D6(if_d6), .D7(if_d7), .D8(if_d8), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .LD0_5(LD0_5), .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .idelay_inc(idelay_inc), .idelay_ld_rst_2(idelay_ld_rst_2), .iserdes_clkdiv(iserdes_clkdiv), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out), .mem_dq_ts(mem_dq_ts), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .of_dqbus(of_dqbus[39:4]), .oserdes_clk(oserdes_clk), .oserdes_clk_delayed(oserdes_clk_delayed), .oserdes_clkdiv(oserdes_clkdiv), .po_oserdes_rst(po_oserdes_rst), .rst_r4(rst_r4)); (* syn_maxfan = "3" *) FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (.C(CLK), .CE(1'b1), .D(if_empty_), .Q(if_empty_r_1), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (.C(CLK), .CE(1'b1), .D(rd_data[10]), .Q(rd_data_r[10]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (.C(CLK), .CE(1'b1), .D(rd_data[11]), .Q(rd_data_r[11]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (.C(CLK), .CE(1'b1), .D(rd_data[12]), .Q(rd_data_r[12]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (.C(CLK), .CE(1'b1), .D(rd_data[13]), .Q(rd_data_r[13]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (.C(CLK), .CE(1'b1), .D(rd_data[14]), .Q(rd_data_r[14]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (.C(CLK), .CE(1'b1), .D(rd_data[15]), .Q(rd_data_r[15]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (.C(CLK), .CE(1'b1), .D(rd_data[16]), .Q(rd_data_r[16]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (.C(CLK), .CE(1'b1), .D(rd_data[17]), .Q(rd_data_r[17]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (.C(CLK), .CE(1'b1), .D(rd_data[18]), .Q(rd_data_r[18]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (.C(CLK), .CE(1'b1), .D(rd_data[19]), .Q(rd_data_r[19]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (.C(CLK), .CE(1'b1), .D(rd_data[20]), .Q(rd_data_r[20]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (.C(CLK), .CE(1'b1), .D(rd_data[21]), .Q(rd_data_r[21]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (.C(CLK), .CE(1'b1), .D(rd_data[22]), .Q(rd_data_r[22]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (.C(CLK), .CE(1'b1), .D(rd_data[23]), .Q(rd_data_r[23]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (.C(CLK), .CE(1'b1), .D(rd_data[24]), .Q(rd_data_r[24]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (.C(CLK), .CE(1'b1), .D(rd_data[25]), .Q(rd_data_r[25]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (.C(CLK), .CE(1'b1), .D(rd_data[26]), .Q(rd_data_r[26]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (.C(CLK), .CE(1'b1), .D(rd_data[27]), .Q(rd_data_r[27]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (.C(CLK), .CE(1'b1), .D(rd_data[28]), .Q(rd_data_r[28]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (.C(CLK), .CE(1'b1), .D(rd_data[29]), .Q(rd_data_r[29]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (.C(CLK), .CE(1'b1), .D(rd_data[30]), .Q(rd_data_r[30]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (.C(CLK), .CE(1'b1), .D(rd_data[31]), .Q(rd_data_r[31]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (.C(CLK), .CE(1'b1), .D(rd_data[32]), .Q(rd_data_r[32]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (.C(CLK), .CE(1'b1), .D(rd_data[33]), .Q(rd_data_r[33]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (.C(CLK), .CE(1'b1), .D(rd_data[34]), .Q(rd_data_r[34]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (.C(CLK), .CE(1'b1), .D(rd_data[35]), .Q(rd_data_r[35]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (.C(CLK), .CE(1'b1), .D(rd_data[36]), .Q(rd_data_r[36]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (.C(CLK), .CE(1'b1), .D(rd_data[37]), .Q(rd_data_r[37]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (.C(CLK), .CE(1'b1), .D(rd_data[38]), .Q(rd_data_r[38]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (.C(CLK), .CE(1'b1), .D(rd_data[39]), .Q(rd_data_r[39]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (.C(CLK), .CE(1'b1), .D(rd_data[40]), .Q(rd_data_r[40]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (.C(CLK), .CE(1'b1), .D(rd_data[41]), .Q(rd_data_r[41]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (.C(CLK), .CE(1'b1), .D(rd_data[42]), .Q(rd_data_r[42]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (.C(CLK), .CE(1'b1), .D(rd_data[43]), .Q(rd_data_r[43]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (.C(CLK), .CE(1'b1), .D(rd_data[44]), .Q(rd_data_r[44]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (.C(CLK), .CE(1'b1), .D(rd_data[45]), .Q(rd_data_r[45]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (.C(CLK), .CE(1'b1), .D(rd_data[46]), .Q(rd_data_r[46]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (.C(CLK), .CE(1'b1), .D(rd_data[47]), .Q(rd_data_r[47]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (.C(CLK), .CE(1'b1), .D(rd_data[48]), .Q(rd_data_r[48]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (.C(CLK), .CE(1'b1), .D(rd_data[49]), .Q(rd_data_r[49]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (.C(CLK), .CE(1'b1), .D(rd_data[50]), .Q(rd_data_r[50]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (.C(CLK), .CE(1'b1), .D(rd_data[51]), .Q(rd_data_r[51]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (.C(CLK), .CE(1'b1), .D(rd_data[52]), .Q(rd_data_r[52]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (.C(CLK), .CE(1'b1), .D(rd_data[53]), .Q(rd_data_r[53]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (.C(CLK), .CE(1'b1), .D(rd_data[54]), .Q(rd_data_r[54]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (.C(CLK), .CE(1'b1), .D(rd_data[55]), .Q(rd_data_r[55]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (.C(CLK), .CE(1'b1), .D(rd_data[56]), .Q(rd_data_r[56]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (.C(CLK), .CE(1'b1), .D(rd_data[57]), .Q(rd_data_r[57]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (.C(CLK), .CE(1'b1), .D(rd_data[58]), .Q(rd_data_r[58]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (.C(CLK), .CE(1'b1), .D(rd_data[59]), .Q(rd_data_r[59]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (.C(CLK), .CE(1'b1), .D(rd_data[60]), .Q(rd_data_r[60]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (.C(CLK), .CE(1'b1), .D(rd_data[61]), .Q(rd_data_r[61]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (.C(CLK), .CE(1'b1), .D(rd_data[62]), .Q(rd_data_r[62]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (.C(CLK), .CE(1'b1), .D(rd_data[63]), .Q(rd_data_r[63]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (.C(CLK), .CE(1'b1), .D(rd_data[64]), .Q(rd_data_r[64]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (.C(CLK), .CE(1'b1), .D(rd_data[65]), .Q(rd_data_r[65]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (.C(CLK), .CE(1'b1), .D(rd_data[66]), .Q(rd_data_r[66]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (.C(CLK), .CE(1'b1), .D(rd_data[67]), .Q(rd_data_r[67]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (.C(CLK), .CE(1'b1), .D(rd_data[68]), .Q(rd_data_r[68]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (.C(CLK), .CE(1'b1), .D(rd_data[69]), .Q(rd_data_r[69]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (.C(CLK), .CE(1'b1), .D(rd_data[6]), .Q(rd_data_r[6]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (.C(CLK), .CE(1'b1), .D(rd_data[70]), .Q(rd_data_r[70]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (.C(CLK), .CE(1'b1), .D(rd_data[71]), .Q(rd_data_r[71]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (.C(CLK), .CE(1'b1), .D(rd_data[7]), .Q(rd_data_r[7]), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (.C(CLK), .CE(1'b1), .D(rd_data[8]), .Q(\not_strict_mode.app_rd_data_reg[7]_0 ), .R(1'b0)); FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (.C(CLK), .CE(1'b1), .D(rd_data[9]), .Q(rd_data_r[9]), .R(1'b0)); ddr3_if_mig_7series_v4_0_ddr_if_post_fifo \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo (.A_byte_rd_en(A_byte_rd_en), .CLK(CLK), .C_byte_rd_en(C_byte_rd_en), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_byte_rd_en(D_byte_rd_en), .Q({rd_data_r[71:9],\not_strict_mode.app_rd_data_reg[7]_0 ,rd_data_r[7:6]}), .if_empty_r(if_empty_r), .if_empty_r_0(if_empty_r_0), .if_empty_r_1(if_empty_r_1), .ififo_rst(ififo_rst), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .\my_empty_reg[4]_0 (\my_empty_reg[4] ), .\my_empty_reg[4]_1 (\my_empty_reg[4]_0 ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), .\not_strict_mode.app_rd_data_reg[227] (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[228] (\not_strict_mode.app_rd_data_reg[228] ), .\not_strict_mode.app_rd_data_reg[228]_0 (\not_strict_mode.app_rd_data_reg[228]_0 ), .\not_strict_mode.app_rd_data_reg[229] (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[230] (\not_strict_mode.app_rd_data_reg[230] ), .\not_strict_mode.app_rd_data_reg[231] (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231]_0 ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), .\not_strict_mode.app_rd_data_reg[70] (\not_strict_mode.app_rd_data_reg[70] ), .\not_strict_mode.app_rd_data_reg[71] (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[7] (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7]_1 ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] )); FDSE #( .INIT(1'b1)) ififo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ififo_rst), .S(phy_if_reset)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) IN_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_8"), .SYNCHRONOUS_MODE("FALSE")) \in_fifo_gen.in_fifo (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ), .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ), .D0({1'b0,1'b0,1'b0,1'b0}), .D1(if_d1), .D2(if_d2), .D3(if_d3), .D4(if_d4), .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}), .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}), .D7(if_d7), .D8(if_d8), .D9({1'b0,1'b0,1'b0,1'b0}), .EMPTY(if_empty_), .FULL(\in_fifo_gen.in_fifo_n_3 ), .Q0(rd_data[7:0]), .Q1(rd_data[15:8]), .Q2(rd_data[23:16]), .Q3(rd_data[31:24]), .Q4(rd_data[39:32]), .Q5(rd_data[47:40]), .Q6(rd_data[55:48]), .Q7(rd_data[63:56]), .Q8(rd_data[71:64]), .Q9(rd_data[79:72]), .RDCLK(CLK), .RDEN(1'b1), .RESET(ififo_rst), .WRCLK(iserdes_clkdiv), .WREN(ififo_wr_enable)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized5 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D9(of_d9), .Q(Q), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst(ofifo_rst), .ofifo_rst_reg(out_fifo_n_3), .phy_dout(phy_dout), .\write_buffer.wr_buf_out_data_reg[284] (\write_buffer.wr_buf_out_data_reg[284] )); FDSE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.calib_in_common_reg_0 ), .Q(ofifo_rst), .S(A_rst_primitives)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_8_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }), .D1(\write_buffer.wr_buf_out_data_reg[231] ), .D2(\write_buffer.wr_buf_out_data_reg[230] ), .D3(\write_buffer.wr_buf_out_data_reg[229] ), .D4(\write_buffer.wr_buf_out_data_reg[228] ), .D5(\write_buffer.wr_buf_out_data_reg[227] ), .D6(\write_buffer.wr_buf_out_data_reg[226] ), .D7(\write_buffer.wr_buf_out_data_reg[225] ), .D8(\write_buffer.wr_buf_out_data_reg[224] ), .D9(of_d9), .EMPTY(out_fifo_n_2), .FULL(out_fifo_n_3), .Q0(of_dqbus[3:0]), .Q1(of_dqbus[7:4]), .Q2(of_dqbus[11:8]), .Q3(of_dqbus[15:12]), .Q4(of_dqbus[19:16]), .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}), .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}), .Q7(of_dqbus[31:28]), .Q8(of_dqbus[35:32]), .Q9(of_dqbus[39:36]), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(ofifo_rst), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_IN_PHY #( .BURST_MODE("TRUE"), .CLKOUT_DIV(2), .DQS_BIAS_MODE("FALSE"), .DQS_FIND_PATTERN(3'b000), .FINE_DELAY(33), .FREQ_REF_DIV("NONE"), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.112000), .REFCLK_PERIOD(1.112000), .SEL_CLK_OFFSET(6), .SYNC_IN_DIV_RST("TRUE"), .WR_CYCLES("FALSE")) \phaser_in_gen.phaser_in (.BURSTPENDINGPHY(phaser_ctl_bus[1]), .COUNTERLOADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(D_pi_counter_read_val), .DQSFOUND(\pi_dqs_found_lanes_r1_reg[3] ), .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(pi_en_stg2_f_reg), .FINEINC(pi_stg2_f_incdec_reg), .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ), .FREQREFCLK(freq_refclk), .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .ICLKDIV(iserdes_clkdiv), .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ), .MEMREFCLK(mem_refclk), .PHASELOCKED(pi_phase_locked_all_r1_reg), .PHASEREFCLK(mem_dqs_in), .RANKSELPHY(phaser_ctl_bus[3:2]), .RCLK(\phaser_in_gen.phaser_in_n_7 ), .RST(A_rst_primitives), .RSTDQSFIND(\gen_byte_sel_div1.calib_in_common_reg_0 ), .SYNCIN(sync_pulse), .SYSCLK(CLK), .WRENABLE(ififo_wr_enable)); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(2), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("TRUE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(phaser_ctl_bus[0]), .COARSEENABLE(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEINC(\gen_byte_sel_div1.calib_in_common_reg_1 ), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\calib_sel_reg[0] ), .COUNTERREADVAL(D_po_counter_read_val), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(ck_po_stg2_f_en_reg), .FINEINC(ck_po_stg2_f_indec_reg), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(delay_done_r4_reg), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[0]_i_1 (.I0(D_pi_counter_read_val[0]), .I1(COUNTERREADVAL[0]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[0]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[0]), .O(D[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[1]_i_1 (.I0(D_pi_counter_read_val[1]), .I1(COUNTERREADVAL[1]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[1]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[1]), .O(D[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[2]_i_1 (.I0(D_pi_counter_read_val[2]), .I1(COUNTERREADVAL[2]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[2]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[2]), .O(D[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[3]_i_1 (.I0(D_pi_counter_read_val[3]), .I1(COUNTERREADVAL[3]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[3]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[3]), .O(D[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[4]_i_1 (.I0(D_pi_counter_read_val[4]), .I1(COUNTERREADVAL[4]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[4]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[4]), .O(D[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_counter_read_val[5]_i_1 (.I0(D_pi_counter_read_val[5]), .I1(COUNTERREADVAL[5]), .I2(\calib_sel_reg[1] [0]), .I3(A_rst_primitives_reg[5]), .I4(\calib_sel_reg[1] [1]), .I5(A_rst_primitives_reg_0[5]), .O(D[5])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[0]_i_1__0 (.I0(D_po_counter_read_val[0]), .I1(A_rst_primitives_reg_1[0]), .I2(A_rst_primitives_reg_2[0]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[0]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [0])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[1]_i_1__0 (.I0(D_po_counter_read_val[1]), .I1(A_rst_primitives_reg_1[1]), .I2(A_rst_primitives_reg_2[1]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[1]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [1])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[2]_i_1__0 (.I0(D_po_counter_read_val[2]), .I1(A_rst_primitives_reg_1[2]), .I2(A_rst_primitives_reg_2[2]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[2]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [2])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[3]_i_1__0 (.I0(D_po_counter_read_val[3]), .I1(A_rst_primitives_reg_1[3]), .I2(A_rst_primitives_reg_2[3]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[3]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [3])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[4]_i_1__0 (.I0(D_po_counter_read_val[4]), .I1(A_rst_primitives_reg_1[4]), .I2(A_rst_primitives_reg_2[4]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[4]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [4])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[5]_i_1__0 (.I0(D_po_counter_read_val[5]), .I1(A_rst_primitives_reg_1[5]), .I2(A_rst_primitives_reg_2[5]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[5]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [5])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[6]_i_1__0 (.I0(D_po_counter_read_val[6]), .I1(A_rst_primitives_reg_1[6]), .I2(A_rst_primitives_reg_2[6]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[6]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [6])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[7]_i_1__0 (.I0(D_po_counter_read_val[7]), .I1(A_rst_primitives_reg_1[7]), .I2(A_rst_primitives_reg_2[7]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[7]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [7])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[8]_i_1__0 (.I0(D_po_counter_read_val[8]), .I1(A_rst_primitives_reg_1[8]), .I2(A_rst_primitives_reg_2[8]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_3[8]), .I5(\calib_sel_reg[1] [0]), .O(\po_counter_read_val_reg[8] [8])); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized3 (SR, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , A_of_full, COUNTERREADVAL, wr_en, \my_empty_reg[1] , Q, mem_dq_out, A_rst_primitives, CLK, D0, D1, OUTBURSTPENDING, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , freq_refclk, mem_refclk, \calib_sel_reg[1]_2 , sync_pulse, PCENABLECALIB, mux_cmd_wren, mem_out); output [0:0]SR; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output A_of_full; output [8:0]COUNTERREADVAL; output wr_en; output \my_empty_reg[1] ; output [3:0]Q; output [1:0]mem_dq_out; input A_rst_primitives; input CLK; input [2:0]D0; input [2:0]D1; input [0:0]OUTBURSTPENDING; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[1]_2 ; input sync_pulse; input [1:0]PCENABLECALIB; input mux_cmd_wren; input [11:0]mem_out; wire A_of_a_full; wire A_of_full; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_rst_primitives; wire CLK; wire [8:0]COUNTERREADVAL; wire [2:0]D0; wire [2:0]D1; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [3:0]Q; wire [0:0]SR; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [1:0]mem_dq_out; wire [11:0]mem_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_2; wire po_oserdes_rst; wire po_rd_enable; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire sync_pulse; wire wr_en; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized3 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q1,of_q0}), .oserdes_rst(po_oserdes_rst)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized6 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .Q(Q), .SR(SR), .mem_out(mem_out), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .ofifo_rst_reg(A_of_full), .\rd_ptr_timing_reg[0]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_2 ), .wr_en(wr_en)); FDRE #( .INIT(1'b1)) ofifo_rst_reg (.C(CLK), .CE(1'b1), .D(A_rst_primitives), .Q(SR), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(A_of_a_full), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D0}), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D1}), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .EMPTY(out_fifo_n_2), .FULL(A_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(\calib_sel_reg[1] ), .COARSEINC(\calib_sel_reg[1] ), .COARSEOVERFLOW(A_po_coarse_overflow), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERREADVAL(COUNTERREADVAL), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(\calib_sel_reg[1]_0 ), .FINEINC(\calib_sel_reg[1]_1 ), .FINEOVERFLOW(A_po_fine_overflow), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(\calib_sel_reg[1]_2 ), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized4 (\rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , COUNTERREADVAL, wr_en_5, \my_empty_reg[1] , of_ctl_full_v, Q, mem_dq_out, SR, CLK, init_calib_complete_reg_rep__6, D5, D6, OUTBURSTPENDING, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , freq_refclk, mem_refclk, A_rst_primitives, \calib_sel_reg[1]_2 , sync_pulse, PCENABLECALIB, mux_cmd_wren, \rd_ptr_reg[3] , C_of_full, A_of_full, D_of_full); output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output [8:0]COUNTERREADVAL; output wr_en_5; output \my_empty_reg[1] ; output [0:0]of_ctl_full_v; output [3:0]Q; output [2:0]mem_dq_out; input [0:0]SR; input CLK; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [0:0]OUTBURSTPENDING; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input freq_refclk; input mem_refclk; input A_rst_primitives; input \calib_sel_reg[1]_2 ; input sync_pulse; input [1:0]PCENABLECALIB; input mux_cmd_wren; input [17:0]\rd_ptr_reg[3] ; input C_of_full; input A_of_full; input D_of_full; wire A_of_full; wire A_rst_primitives; wire B_of_a_full; wire B_of_full; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire CLK; wire [8:0]COUNTERREADVAL; wire C_of_full; wire [3:0]D5; wire [3:0]D6; wire D_of_full; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [3:0]Q; wire [0:0]SR; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [3:0]init_calib_complete_reg_rep__6; wire [2:0]mem_dq_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire [0:0]of_ctl_full_v; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_2; wire po_oserdes_rst; wire po_rd_enable; wire [17:0]\rd_ptr_reg[3] ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire sync_pulse; wire wr_en_5; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized4 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q4}), .oserdes_rst(po_oserdes_rst)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized7 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.B_of_full(B_of_full), .CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }), .Q(Q), .SR(SR), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_full_reg[3]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_2 ), .wr_en_5(wr_en_5)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(B_of_a_full), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,init_calib_complete_reg_rep__6}), .D5({D5,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D6({D6,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }), .EMPTY(out_fifo_n_2), .FULL(B_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(\calib_sel_reg[1] ), .COARSEINC(\calib_sel_reg[1] ), .COARSEOVERFLOW(B_po_coarse_overflow), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERREADVAL(COUNTERREADVAL), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(\calib_sel_reg[1]_0 ), .FINEINC(\calib_sel_reg[1]_1 ), .FINEOVERFLOW(B_po_fine_overflow), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(\calib_sel_reg[1]_2 ), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT4 #( .INIT(16'hFFFE)) phy_mc_cmd_full_r_i_1 (.I0(B_of_full), .I1(C_of_full), .I2(A_of_full), .I3(D_of_full), .O(of_ctl_full_v)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized5 (C_of_full, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , COUNTERREADVAL, wr_en_6, \my_empty_reg[1] , Q, mem_dq_out, SR, CLK, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, OUTBURSTPENDING, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, A_rst_primitives, \calib_sel_reg[0]_2 , sync_pulse, PCENABLECALIB, mux_cmd_wren, \rd_ptr_reg[3] ); output C_of_full; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output [8:0]COUNTERREADVAL; output wr_en_6; output \my_empty_reg[1] ; output [3:0]Q; output [9:0]mem_dq_out; input [0:0]SR; input CLK; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [0:0]OUTBURSTPENDING; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input A_rst_primitives; input \calib_sel_reg[0]_2 ; input sync_pulse; input [1:0]PCENABLECALIB; input mux_cmd_wren; input [33:0]\rd_ptr_reg[3] ; wire A_rst_primitives; wire CLK; wire [8:0]COUNTERREADVAL; wire C_of_a_full; wire C_of_full; wire C_po_coarse_overflow; wire C_po_fine_overflow; wire [2:0]D2; wire [2:0]D3; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [3:0]Q; wire [0:0]SR; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire [9:0]mem_dq_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_2; wire po_oserdes_rst; wire po_rd_enable; wire [33:0]\rd_ptr_reg[3] ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire sync_pulse; wire wr_en_6; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized5 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2}), .po_oserdes_rst(po_oserdes_rst)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized8 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }), .Q(Q), .SR(SR), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .ofifo_rst_reg(C_of_full), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ), .\rd_ptr_timing_reg[0]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_2 ), .wr_en_6(wr_en_6)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(C_of_a_full), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D2}), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D3}), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] }), .D5(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .D6(\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,D7}), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,D8}), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,D9}), .EMPTY(out_fifo_n_2), .FULL(C_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(\calib_sel_reg[0] ), .COARSEINC(\calib_sel_reg[0] ), .COARSEOVERFLOW(C_po_coarse_overflow), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(\gen_byte_sel_div1.calib_in_common_reg ), .COUNTERREADVAL(COUNTERREADVAL), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(\calib_sel_reg[0]_0 ), .FINEINC(\calib_sel_reg[0]_1 ), .FINEOVERFLOW(C_po_fine_overflow), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(\calib_sel_reg[0]_2 ), .SYNCIN(sync_pulse), .SYSCLK(CLK)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_byte_lane" *) module ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized6 (\my_empty_reg[1] , D, ddr_ck_out, D_of_full, mem_dq_out, \my_empty_reg[7] , init_calib_complete_reg_rep__5, mc_cas_n, \cmd_pipe_plus.mc_address_reg[43] , init_calib_complete_reg_rep, COUNTERREADVAL, A_rst_primitives_reg, \calib_sel_reg[1] , A_rst_primitives_reg_0, SR, CLK, OUTBURSTPENDING, D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, freq_refclk, mem_refclk, A_rst_primitives, D_po_sel_fine_oclk_delay125_out, sync_pulse, PCENABLECALIB, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , mux_cmd_wren, phy_dout, init_calib_complete_reg_rep__6); output \my_empty_reg[1] ; output [8:0]D; output [1:0]ddr_ck_out; output D_of_full; output [8:0]mem_dq_out; output [31:0]\my_empty_reg[7] ; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input init_calib_complete_reg_rep; input [8:0]COUNTERREADVAL; input [8:0]A_rst_primitives_reg; input [1:0]\calib_sel_reg[1] ; input [8:0]A_rst_primitives_reg_0; input [0:0]SR; input CLK; input [0:0]OUTBURSTPENDING; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input freq_refclk; input mem_refclk; input A_rst_primitives; input D_po_sel_fine_oclk_delay125_out; input sync_pulse; input [1:0]PCENABLECALIB; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input mux_cmd_wren; input [35:0]phy_dout; input init_calib_complete_reg_rep__6; wire A_rst_primitives; wire [8:0]A_rst_primitives_reg; wire [8:0]A_rst_primitives_reg_0; wire CLK; wire [8:0]COUNTERREADVAL; wire [8:0]D; wire [3:0]D4; wire D_of_full; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire [8:0]D_po_counter_read_val; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]OUTBURSTPENDING; wire [1:0]PCENABLECALIB; wire [0:0]SR; wire [1:0]\calib_sel_reg[1] ; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire [1:0]ddr_ck_out; wire [0:0]ddr_ck_out_q; wire freq_refclk; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire init_calib_complete_reg_rep__6; wire [0:0]mc_cas_n; wire [8:0]mem_dq_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire [31:0]\my_empty_reg[7] ; wire [3:0]of_d9; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ; wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ; wire [3:0]of_q0; wire [3:0]of_q1; wire [3:0]of_q2; wire [3:0]of_q3; wire [3:0]of_q4; wire [7:0]of_q5; wire [7:0]of_q6; wire [3:0]of_q7; wire [3:0]of_q8; wire [3:0]of_q9; wire oserdes_clk; wire oserdes_clk_delayed; wire oserdes_clkdiv; wire [1:0]oserdes_dq_ts; wire [1:0]oserdes_dqs; wire [1:0]oserdes_dqs_ts; wire out_fifo_n_0; wire out_fifo_n_1; wire out_fifo_n_2; wire phaser_out_n_0; wire phaser_out_n_1; wire [35:0]phy_dout; wire po_oserdes_rst; wire po_rd_enable; wire sync_pulse; wire \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ; wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED; ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized6 ddr_byte_group_io (.mem_dq_out(mem_dq_out), .oserdes_clk(oserdes_clk), .oserdes_clkdiv(oserdes_clkdiv), .oserdes_dq({of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1}), .po_oserdes_rst(po_oserdes_rst)); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .IS_C_INVERTED(1'b0), .IS_D1_INVERTED(1'b0), .IS_D2_INVERTED(1'b0), .SRTYPE("SYNC")) \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck (.C(oserdes_clk), .CE(1'b1), .D1(1'b0), .D2(1'b1), .Q(ddr_ck_out_q), .R(1'b0), .S(\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) (* XILINX_LEGACY_PRIM = "OBUFDS" *) OBUFDS #( .IOSTANDARD("DEFAULT")) \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf (.I(ddr_ck_out_q), .O(ddr_ck_out[0]), .OB(ddr_ck_out[1])); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized9 \of_pre_fifo_gen.u_ddr_of_pre_fifo (.CLK(CLK), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 }), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}), .SR(SR), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .mc_cas_n(mc_cas_n), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1]_0 (\my_empty_reg[1] ), .\my_empty_reg[7]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ), .\my_empty_reg[7]_1 (\my_empty_reg[7] ), .ofifo_rst_reg(D_of_full), .phy_dout(phy_dout)); (* BOX_TYPE = "PRIMITIVE" *) (* CLOCK_DOMAINS = "INDEPENDENT" *) OUT_FIFO #( .ALMOST_EMPTY_VALUE(1), .ALMOST_FULL_VALUE(1), .ARRAY_MODE("ARRAY_MODE_4_X_4"), .OUTPUT_DISABLE("FALSE"), .SYNCHRONOUS_MODE("FALSE")) out_fifo (.ALMOSTEMPTY(out_fifo_n_0), .ALMOSTFULL(out_fifo_n_1), .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 }), .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] }), .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] }), .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] }), .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,D4}), .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] }), .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] }), .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] }), .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ,\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] }), .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}), .EMPTY(out_fifo_n_2), .FULL(D_of_full), .Q0(of_q0), .Q1(of_q1), .Q2(of_q2), .Q3(of_q3), .Q4(of_q4), .Q5(of_q5), .Q6(of_q6), .Q7(of_q7), .Q8(of_q8), .Q9(of_q9), .RDCLK(oserdes_clkdiv), .RDEN(po_rd_enable), .RESET(SR), .WRCLK(CLK), .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 )); (* BOX_TYPE = "PRIMITIVE" *) PHASER_OUT_PHY #( .CLKOUT_DIV(4), .COARSE_BYPASS("FALSE"), .COARSE_DELAY(0), .DATA_CTL_N("FALSE"), .DATA_RD_CYCLES("FALSE"), .FINE_DELAY(60), .IS_RST_INVERTED(1'b0), .MEMREFCLK_PERIOD(1.112000), .OCLKDELAY_INV("TRUE"), .OCLK_DELAY(28), .OUTPUT_CLK_SRC("DELAYED_REF"), .PHASEREFCLK_PERIOD(1.000000), .PO(3'b111), .REFCLK_PERIOD(1.112000), .SYNC_IN_DIV_RST("TRUE")) phaser_out (.BURSTPENDINGPHY(OUTBURSTPENDING), .COARSEENABLE(D_po_coarse_enable110_out), .COARSEINC(D_po_coarse_enable110_out), .COARSEOVERFLOW(phaser_out_n_0), .COUNTERLOADEN(1'b0), .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .COUNTERREADEN(D_po_counter_read_en122_out), .COUNTERREADVAL(D_po_counter_read_val), .CTSBUS(oserdes_dqs_ts), .DQSBUS(oserdes_dqs), .DTSBUS(oserdes_dq_ts), .ENCALIBPHY(PCENABLECALIB), .FINEENABLE(D_po_fine_enable107_out), .FINEINC(D_po_fine_inc113_out), .FINEOVERFLOW(phaser_out_n_1), .FREQREFCLK(freq_refclk), .MEMREFCLK(mem_refclk), .OCLK(oserdes_clk), .OCLKDELAYED(oserdes_clk_delayed), .OCLKDIV(oserdes_clkdiv), .OSERDESRST(po_oserdes_rst), .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED), .RDENABLE(po_rd_enable), .RST(A_rst_primitives), .SELFINEOCLKDELAY(D_po_sel_fine_oclk_delay125_out), .SYNCIN(sync_pulse), .SYSCLK(CLK)); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[0]_i_1 (.I0(D_po_counter_read_val[0]), .I1(COUNTERREADVAL[0]), .I2(A_rst_primitives_reg[0]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[0]), .I5(\calib_sel_reg[1] [0]), .O(D[0])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[1]_i_1 (.I0(D_po_counter_read_val[1]), .I1(COUNTERREADVAL[1]), .I2(A_rst_primitives_reg[1]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[1]), .I5(\calib_sel_reg[1] [0]), .O(D[1])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[2]_i_1 (.I0(D_po_counter_read_val[2]), .I1(COUNTERREADVAL[2]), .I2(A_rst_primitives_reg[2]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[2]), .I5(\calib_sel_reg[1] [0]), .O(D[2])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[3]_i_1 (.I0(D_po_counter_read_val[3]), .I1(COUNTERREADVAL[3]), .I2(A_rst_primitives_reg[3]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[3]), .I5(\calib_sel_reg[1] [0]), .O(D[3])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[4]_i_1 (.I0(D_po_counter_read_val[4]), .I1(COUNTERREADVAL[4]), .I2(A_rst_primitives_reg[4]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[4]), .I5(\calib_sel_reg[1] [0]), .O(D[4])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[5]_i_1 (.I0(D_po_counter_read_val[5]), .I1(COUNTERREADVAL[5]), .I2(A_rst_primitives_reg[5]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[5]), .I5(\calib_sel_reg[1] [0]), .O(D[5])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[6]_i_1 (.I0(D_po_counter_read_val[6]), .I1(COUNTERREADVAL[6]), .I2(A_rst_primitives_reg[6]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[6]), .I5(\calib_sel_reg[1] [0]), .O(D[6])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[7]_i_1 (.I0(D_po_counter_read_val[7]), .I1(COUNTERREADVAL[7]), .I2(A_rst_primitives_reg[7]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[7]), .I5(\calib_sel_reg[1] [0]), .O(D[7])); LUT6 #( .INIT(64'hAACCAACCF0FFF000)) \po_counter_read_val[8]_i_1 (.I0(D_po_counter_read_val[8]), .I1(COUNTERREADVAL[8]), .I2(A_rst_primitives_reg[8]), .I3(\calib_sel_reg[1] [1]), .I4(A_rst_primitives_reg_0[8]), .I5(\calib_sel_reg[1] [0]), .O(D[8])); endmodule module ddr3_if_mig_7series_v4_0_ddr_calib_top (idelay_inc, phy_dout, phy_if_reset, \samps_r_reg[9] , \my_empty_reg[7] , \rd_ptr_timing_reg[0] , app_zq_r_reg, \my_empty_reg[7]_0 , init_calib_complete_r_reg, \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_en_stg2_f_timing_reg, out, dqs_po_en_stg2_f_reg, prbs_rdlvl_start_r_reg, A, fine_delay_sel_r_reg, \rd_ptr_timing_reg[0]_0 , \my_empty_reg[7]_1 , \my_empty_reg[7]_2 , \my_empty_reg[7]_3 , \my_empty_reg[7]_4 , LD0, \po_rdval_cnt_reg[8] , LD0_0, LD0_1, LD0_2, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_coarse_enable110_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , \po_counter_read_val_reg[8]_6 , \po_counter_read_val_reg[8]_7 , \po_counter_read_val_reg[8]_8 , \po_counter_read_val_reg[8]_9 , \po_counter_read_val_reg[8]_10 , \po_counter_read_val_reg[8]_11 , E, \po_counter_read_val_reg[8]_12 , \po_counter_read_val_reg[8]_13 , \po_counter_read_val_reg[8]_14 , \po_counter_read_val_reg[8]_15 , \pi_dqs_found_lanes_r1_reg[3] , \fine_delay_r_reg[5] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \po_counter_read_val_reg[8]_16 , \po_counter_read_val_reg[8]_17 , \po_counter_read_val_reg[8]_18 , ififo_rst_reg, \pi_dqs_found_lanes_r1_reg[3]_0 , \pi_dqs_found_lanes_r1_reg[3]_1 , \pi_dqs_found_lanes_r1_reg[3]_2 , \pi_dqs_found_lanes_r1_reg[2] , \fine_delay_r_reg[5]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \po_counter_read_val_reg[8]_19 , \po_counter_read_val_reg[8]_20 , \po_counter_read_val_reg[8]_21 , ififo_rst_reg_0, \pi_dqs_found_lanes_r1_reg[2]_0 , \pi_dqs_found_lanes_r1_reg[2]_1 , \pi_dqs_found_lanes_r1_reg[2]_2 , \pi_dqs_found_lanes_r1_reg[1] , \fine_delay_r_reg[5]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \po_counter_read_val_reg[8]_22 , \po_counter_read_val_reg[8]_23 , \po_counter_read_val_reg[8]_24 , ififo_rst_reg_1, \pi_dqs_found_lanes_r1_reg[1]_0 , \pi_dqs_found_lanes_r1_reg[1]_1 , \pi_dqs_found_lanes_r1_reg[1]_2 , D, COUNTERLOADVAL, \pi_dqs_found_lanes_r1_reg[0] , \fine_delay_r_reg[2] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , \po_counter_read_val_reg[8]_25 , \po_counter_read_val_reg[8]_26 , \po_counter_read_val_reg[8]_27 , ififo_rst_reg_2, \pi_dqs_found_lanes_r1_reg[0]_0 , \pi_dqs_found_lanes_r1_reg[0]_1 , \pi_dqs_found_lanes_r1_reg[0]_2 , \po_counter_read_val_reg[8]_28 , \po_counter_read_val_reg[8]_29 , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, A_1__s_port_, \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 , \A[1]__4 , D2, D0, D3, D5, D6, D1, \rd_ptr_timing_reg[0]_1 , D7, D8, \rd_ptr_timing_reg[0]_2 , \my_empty_reg[7]_5 , \my_empty_reg[7]_6 , \my_empty_reg[7]_7 , D4, \my_empty_reg[7]_8 , \my_empty_reg[7]_9 , \my_empty_reg[7]_10 , \my_empty_reg[7]_11 , \my_full_reg[3] , \rd_ptr_timing_reg[0]_3 , D9, \my_empty_reg[7]_12 , \my_empty_reg[7]_13 , \my_empty_reg[7]_14 , \my_empty_reg[7]_15 , \my_empty_reg[7]_16 , \my_empty_reg[7]_17 , \my_empty_reg[7]_18 , \my_empty_reg[7]_19 , \my_empty_reg[7]_20 , \my_empty_reg[7]_21 , \my_empty_reg[7]_22 , \my_empty_reg[7]_23 , \my_empty_reg[7]_24 , \my_empty_reg[7]_25 , \my_empty_reg[7]_26 , \my_empty_reg[7]_27 , \my_empty_reg[7]_28 , \my_empty_reg[7]_29 , \my_empty_reg[7]_30 , \my_empty_reg[7]_31 , \my_empty_reg[7]_32 , \my_empty_reg[7]_33 , \my_empty_reg[7]_34 , \my_empty_reg[7]_35 , \my_empty_reg[7]_36 , \my_empty_reg[7]_37 , \my_empty_reg[7]_38 , \my_empty_reg[7]_39 , \my_empty_reg[7]_40 , \my_empty_reg[7]_41 , \my_empty_reg[7]_42 , \my_empty_reg[7]_43 , \byte_r_reg[0] , \byte_r_reg[1] , \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , \zero2fuzz_r_reg[0] , maint_prescaler_r1, \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[5] , \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \rdlvl_dqs_tap_cnt_r_reg[0][3][0] , \idelay_tap_cnt_r_reg[0][3][0] , \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , \fine_delay_mod_reg[5] , \fine_delay_mod_reg[20] , \phy_ctl_wd_i1_reg[24] , phy_write_calib, phy_read_calib, \fine_delay_mod_reg[26] , \genblk9[1].fine_delay_incdec_pb_reg[1] , \genblk9[2].fine_delay_incdec_pb_reg[2] , \genblk9[3].fine_delay_incdec_pb_reg[3] , \genblk9[5].fine_delay_incdec_pb_reg[5] , \genblk9[6].fine_delay_incdec_pb_reg[6] , \genblk9[7].fine_delay_incdec_pb_reg[7] , mux_wrdata_en, mux_cmd_wren, mux_reset_n, \data_offset_1_i1_reg[5] , \rd_ptr_timing_reg[0]_4 , \my_full_reg[3]_0 , \byte_sel_data_map_reg[1] , \A[0]__4 , \A[0]__0 , \A[2]__2 , \A[1]__0 , \A[1]__4_0 , \A[1]__3 , \A[2]__1 , \pi_dqs_found_lanes_r1_reg[1]_3 , \pi_dqs_found_lanes_r1_reg[2]_3 , \pi_dqs_found_lanes_r1_reg[3]_3 , \fine_delay_r_reg[26] , \fine_delay_r_reg[26]_0 , \fine_delay_r_reg[26]_1 , \qcntr_r_reg[0] , CLK, rstdiv0_sync_r1_reg_rep__20, poc_sample_pd, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__9, phy_rddata_en, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 , \po_stg2_wrcal_cnt_reg[1] , \po_stg2_wrcal_cnt_reg[1]_0 , \po_stg2_wrcal_cnt_reg[1]_1 , \po_stg2_wrcal_cnt_reg[1]_2 , \mcGo_r_reg[15] , in0, rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__24, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, \rd_mux_sel_r_reg[1] , \rd_mux_sel_r_reg[1]_0 , \rd_mux_sel_r_reg[1]_1 , \rd_mux_sel_r_reg[1]_2 , \rd_mux_sel_r_reg[1]_3 , \rd_mux_sel_r_reg[1]_4 , \rd_mux_sel_r_reg[1]_5 , \rd_mux_sel_r_reg[1]_6 , \rd_mux_sel_r_reg[1]_7 , \rd_mux_sel_r_reg[1]_8 , \rd_mux_sel_r_reg[1]_9 , \rd_mux_sel_r_reg[1]_10 , \rd_mux_sel_r_reg[1]_11 , \rd_mux_sel_r_reg[1]_12 , \rd_mux_sel_r_reg[1]_13 , \rd_mux_sel_r_reg[1]_14 , \rd_mux_sel_r_reg[1]_15 , \rd_mux_sel_r_reg[1]_16 , \rd_mux_sel_r_reg[1]_17 , \rd_mux_sel_r_reg[1]_18 , \rd_mux_sel_r_reg[1]_19 , \rd_mux_sel_r_reg[1]_20 , \rd_mux_sel_r_reg[1]_21 , \rd_mux_sel_r_reg[1]_22 , \rd_mux_sel_r_reg[1]_23 , \rd_mux_sel_r_reg[1]_24 , \rd_mux_sel_r_reg[1]_25 , \rd_mux_sel_r_reg[1]_26 , \rd_mux_sel_r_reg[1]_27 , \rd_mux_sel_r_reg[1]_28 , \rd_mux_sel_r_reg[1]_29 , \rd_mux_sel_r_reg[1]_30 , \rd_mux_sel_r_reg[1]_31 , \rd_mux_sel_r_reg[1]_32 , \rd_mux_sel_r_reg[1]_33 , \rd_mux_sel_r_reg[1]_34 , \rd_mux_sel_r_reg[1]_35 , \rd_mux_sel_r_reg[1]_36 , \rd_mux_sel_r_reg[1]_37 , \rd_mux_sel_r_reg[1]_38 , \rd_mux_sel_r_reg[1]_39 , \rd_mux_sel_r_reg[1]_40 , \rd_mux_sel_r_reg[1]_41 , \rd_mux_sel_r_reg[1]_42 , \rd_mux_sel_r_reg[1]_43 , \rd_mux_sel_r_reg[1]_44 , \rd_mux_sel_r_reg[1]_45 , \rd_mux_sel_r_reg[1]_46 , \rd_mux_sel_r_reg[1]_47 , \rd_mux_sel_r_reg[1]_48 , \rd_mux_sel_r_reg[1]_49 , \rd_mux_sel_r_reg[1]_50 , \rd_mux_sel_r_reg[1]_51 , \rd_mux_sel_r_reg[1]_52 , \rd_mux_sel_r_reg[1]_53 , \rd_mux_sel_r_reg[1]_54 , \rd_mux_sel_r_reg[1]_55 , \rd_mux_sel_r_reg[1]_56 , \rd_mux_sel_r_reg[1]_57 , \rd_mux_sel_r_reg[1]_58 , \rd_mux_sel_r_reg[1]_59 , \rd_mux_sel_r_reg[1]_60 , \rd_mux_sel_r_reg[1]_61 , \rd_mux_sel_r_reg[1]_62 , rstdiv0_sync_r1_reg_rep__23, SR, A_rst_primitives_reg, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__18, rstdiv0_sync_r1_reg_rep__16, SS, tempmon_sample_en, rstdiv0_sync_r1_reg_rep__7, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 , \A[1]_0 , \A[1]_1 , \A[1]_2 , \A[1]_3 , \A[1]_4 , \A[1]_5 , \A[1]_6 , \A[1]_7 , \A[1]_8 , \A[1]_9 , \A[1]_10 , \A[1]_11 , \A[1]_12 , \A[1]_13 , \A[1]_14 , \A[1]_15 , \A[1]_16 , \A[1]_17 , \A[1]_18 , \A[1]_19 , \A[1]_20 , \A[1]_21 , \A[1]_22 , \A[1]_23 , \A[1]_24 , \A[1]_25 , \A[1]_26 , \A[1]_27 , \A[1]_28 , \A[1]_29 , \A[1]_30 , \A[1]_31 , \A[1]_32 , \A[1]_33 , \A[1]_34 , \A[1]_35 , \A[1]_36 , \A[1]_37 , \A[1]_38 , \A[1]_39 , \A[1]_40 , \A[1]_41 , \A[1]_42 , \A[1]_43 , \A[1]_44 , \A[1]_45 , \A[1]_46 , \A[1]_47 , \A[1]_48 , \A[1]_49 , \A[1]_50 , \A[1]_51 , \A[1]_52 , \A[1]_53 , \A[1]_54 , \A[1]_55 , \A[1]_56 , \A[1]_57 , \A[1]_58 , \A[1]_59 , \A[1]_60 , \A[1]_61 , \A[1]_62 , \A[1]_63 , rstdiv0_sync_r1_reg_rep__8, rstdiv0_sync_r1_reg_rep, p_0_out, \po_stg2_wrcal_cnt_reg[1]_3 , \po_stg2_wrcal_cnt_reg[1]_4 , \po_stg2_wrcal_cnt_reg[1]_5 , \po_stg2_wrcal_cnt_reg[1]_6 , \po_stg2_wrcal_cnt_reg[1]_7 , \po_stg2_wrcal_cnt_reg[1]_8 , \po_stg2_wrcal_cnt_reg[1]_9 , \po_stg2_wrcal_cnt_reg[1]_10 , \po_stg2_wrcal_cnt_reg[1]_11 , \po_stg2_wrcal_cnt_reg[1]_12 , \po_stg2_wrcal_cnt_reg[1]_13 , \po_stg2_wrcal_cnt_reg[1]_14 , \po_stg2_wrcal_cnt_reg[1]_15 , \po_stg2_wrcal_cnt_reg[1]_16 , \po_stg2_wrcal_cnt_reg[1]_17 , \po_stg2_wrcal_cnt_reg[1]_18 , \po_stg2_wrcal_cnt_reg[1]_19 , \po_stg2_wrcal_cnt_reg[1]_20 , \po_stg2_wrcal_cnt_reg[1]_21 , \po_stg2_wrcal_cnt_reg[1]_22 , \po_stg2_wrcal_cnt_reg[1]_23 , \po_stg2_wrcal_cnt_reg[1]_24 , \po_stg2_wrcal_cnt_reg[1]_25 , \po_stg2_wrcal_cnt_reg[1]_26 , \po_stg2_wrcal_cnt_reg[1]_27 , \po_stg2_wrcal_cnt_reg[1]_28 , \po_stg2_wrcal_cnt_reg[1]_29 , \po_stg2_wrcal_cnt_reg[1]_30 , \po_stg2_wrcal_cnt_reg[1]_31 , \po_stg2_wrcal_cnt_reg[1]_32 , \po_stg2_wrcal_cnt_reg[1]_33 , \po_stg2_wrcal_cnt_reg[1]_34 , \po_stg2_wrcal_cnt_reg[1]_35 , \po_stg2_wrcal_cnt_reg[1]_36 , \po_stg2_wrcal_cnt_reg[1]_37 , \po_stg2_wrcal_cnt_reg[1]_38 , \po_stg2_wrcal_cnt_reg[1]_39 , \po_stg2_wrcal_cnt_reg[1]_40 , \po_stg2_wrcal_cnt_reg[1]_41 , \po_stg2_wrcal_cnt_reg[1]_42 , \po_stg2_wrcal_cnt_reg[1]_43 , \po_stg2_wrcal_cnt_reg[1]_44 , \po_stg2_wrcal_cnt_reg[1]_45 , \po_stg2_wrcal_cnt_reg[1]_46 , \po_stg2_wrcal_cnt_reg[1]_47 , \po_stg2_wrcal_cnt_reg[1]_48 , \po_stg2_wrcal_cnt_reg[1]_49 , \po_stg2_wrcal_cnt_reg[1]_50 , \po_stg2_wrcal_cnt_reg[1]_51 , \po_stg2_wrcal_cnt_reg[1]_52 , \po_stg2_wrcal_cnt_reg[1]_53 , \po_stg2_wrcal_cnt_reg[1]_54 , \po_stg2_wrcal_cnt_reg[1]_55 , \po_stg2_wrcal_cnt_reg[1]_56 , \po_stg2_wrcal_cnt_reg[1]_57 , \po_stg2_wrcal_cnt_reg[1]_58 , \po_stg2_wrcal_cnt_reg[1]_59 , \po_stg2_wrcal_cnt_reg[1]_60 , \po_stg2_wrcal_cnt_reg[1]_61 , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__6, rstdiv0_sync_r1_reg_rep__5, Q, idelay_ld_rst, idelay_ld_rst_3, idelay_ld_rst_4, idelay_ld_rst_5, rstdiv0_sync_r1_reg_rep__26, rstdiv0_sync_r1_reg_rep__26_0, rstdiv0_sync_r1_reg_rep__25, \sm_r_reg[0]_0 , fine_delay_sel_r, fine_delay_mod, mc_cas_n, \rd_ptr_reg[3] , \my_empty_reg[1] , mem_out, \my_empty_reg[1]_0 , mc_ras_n, mc_odt, \rd_ptr_reg[3]_0 , \my_empty_reg[1]_1 , mc_cke, mc_we_n, \cmd_pipe_plus.mc_address_reg[44] , \rd_ptr_reg[3]_1 , \my_empty_reg[1]_2 , \cmd_pipe_plus.mc_bank_reg[8] , \rd_ptr_reg[3]_2 , \my_empty_reg[1]_3 , \rd_ptr_reg[3]_3 , \my_empty_reg[1]_4 , \rd_ptr_reg[3]_4 , \my_empty_reg[1]_5 , \rd_ptr_reg[3]_5 , \my_empty_reg[1]_6 , mc_cs_n, \pi_counter_read_val_reg[5] , \po_counter_read_val_reg[2] , rstdiv0_sync_r1_reg_rep__26_1, rstdiv0_sync_r1_reg_rep__26_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , sent_col, \po_counter_read_val_reg[8]_30 , \po_counter_read_val_reg[8]_31 , \po_counter_read_val_reg[5] , \A[2]__2_0 , psdone, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__19, \byte_r_reg[0]_0 , fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__24_0, p_81_in, rstdiv0_sync_r1_reg_rep__24_1, rstdiv0_sync_r1_reg_rep__17, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , my_empty, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 , my_empty_6, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 , my_empty_7, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , my_empty_8, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 , po_cnt_dec_reg, \device_temp_r_reg[11] , mc_wrdata_en, \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 , mc_cmd, \cmd_pipe_plus.mc_data_offset_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_reg[2]_0 , \cmd_pipe_plus.mc_data_offset_reg[3]_0 , \cmd_pipe_plus.mc_data_offset_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_reg[5]_0 , \stg3_r_reg[0] , pd_out); output idelay_inc; output [33:0]phy_dout; output phy_if_reset; output \samps_r_reg[9] ; output \my_empty_reg[7] ; output \rd_ptr_timing_reg[0] ; output app_zq_r_reg; output \my_empty_reg[7]_0 ; output init_calib_complete_r_reg; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_en_stg2_f_timing_reg; output out; output dqs_po_en_stg2_f_reg; output prbs_rdlvl_start_r_reg; output [1:0]A; output fine_delay_sel_r_reg; output [33:0]\rd_ptr_timing_reg[0]_0 ; output [71:0]\my_empty_reg[7]_1 ; output [71:0]\my_empty_reg[7]_2 ; output [71:0]\my_empty_reg[7]_3 ; output [71:0]\my_empty_reg[7]_4 ; output LD0; output [2:0]\po_rdval_cnt_reg[8] ; output LD0_0; output LD0_1; output LD0_2; output D_po_counter_read_en122_out; output D_po_fine_enable107_out; output D_po_coarse_enable110_out; output D_po_fine_inc113_out; output D_po_sel_fine_oclk_delay125_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output \po_counter_read_val_reg[8]_6 ; output \po_counter_read_val_reg[8]_7 ; output \po_counter_read_val_reg[8]_8 ; output \po_counter_read_val_reg[8]_9 ; output \po_counter_read_val_reg[8]_10 ; output \po_counter_read_val_reg[8]_11 ; output [0:0]E; output \po_counter_read_val_reg[8]_12 ; output \po_counter_read_val_reg[8]_13 ; output \po_counter_read_val_reg[8]_14 ; output \po_counter_read_val_reg[8]_15 ; output \pi_dqs_found_lanes_r1_reg[3] ; output [0:0]\fine_delay_r_reg[5] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \po_counter_read_val_reg[8]_16 ; output \po_counter_read_val_reg[8]_17 ; output \po_counter_read_val_reg[8]_18 ; output ififo_rst_reg; output \pi_dqs_found_lanes_r1_reg[3]_0 ; output \pi_dqs_found_lanes_r1_reg[3]_1 ; output \pi_dqs_found_lanes_r1_reg[3]_2 ; output \pi_dqs_found_lanes_r1_reg[2] ; output [0:0]\fine_delay_r_reg[5]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \po_counter_read_val_reg[8]_19 ; output \po_counter_read_val_reg[8]_20 ; output \po_counter_read_val_reg[8]_21 ; output ififo_rst_reg_0; output \pi_dqs_found_lanes_r1_reg[2]_0 ; output \pi_dqs_found_lanes_r1_reg[2]_1 ; output \pi_dqs_found_lanes_r1_reg[2]_2 ; output \pi_dqs_found_lanes_r1_reg[1] ; output [0:0]\fine_delay_r_reg[5]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \po_counter_read_val_reg[8]_22 ; output \po_counter_read_val_reg[8]_23 ; output \po_counter_read_val_reg[8]_24 ; output ififo_rst_reg_1; output \pi_dqs_found_lanes_r1_reg[1]_0 ; output \pi_dqs_found_lanes_r1_reg[1]_1 ; output \pi_dqs_found_lanes_r1_reg[1]_2 ; output [7:0]D; output [5:0]COUNTERLOADVAL; output \pi_dqs_found_lanes_r1_reg[0] ; output [0:0]\fine_delay_r_reg[2] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output \po_counter_read_val_reg[8]_25 ; output \po_counter_read_val_reg[8]_26 ; output \po_counter_read_val_reg[8]_27 ; output ififo_rst_reg_2; output \pi_dqs_found_lanes_r1_reg[0]_0 ; output \pi_dqs_found_lanes_r1_reg[0]_1 ; output \pi_dqs_found_lanes_r1_reg[0]_2 ; output \po_counter_read_val_reg[8]_28 ; output \po_counter_read_val_reg[8]_29 ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output A_1__s_port_; output [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; output \A[1]__4 ; output [2:0]D2; output [2:0]D0; output [2:0]D3; output [3:0]D5; output [3:0]D6; output [2:0]D1; output [7:0]\rd_ptr_timing_reg[0]_1 ; output [3:0]D7; output [3:0]D8; output [7:0]\rd_ptr_timing_reg[0]_2 ; output [3:0]\my_empty_reg[7]_5 ; output [3:0]\my_empty_reg[7]_6 ; output [3:0]\my_empty_reg[7]_7 ; output [3:0]D4; output [3:0]\my_empty_reg[7]_8 ; output [3:0]\my_empty_reg[7]_9 ; output [3:0]\my_empty_reg[7]_10 ; output [3:0]\my_empty_reg[7]_11 ; output [3:0]\my_full_reg[3] ; output [3:0]\rd_ptr_timing_reg[0]_3 ; output [3:0]D9; output [7:0]\my_empty_reg[7]_12 ; output [7:0]\my_empty_reg[7]_13 ; output [7:0]\my_empty_reg[7]_14 ; output [7:0]\my_empty_reg[7]_15 ; output [7:0]\my_empty_reg[7]_16 ; output [7:0]\my_empty_reg[7]_17 ; output [7:0]\my_empty_reg[7]_18 ; output [7:0]\my_empty_reg[7]_19 ; output [7:0]\my_empty_reg[7]_20 ; output [7:0]\my_empty_reg[7]_21 ; output [7:0]\my_empty_reg[7]_22 ; output [7:0]\my_empty_reg[7]_23 ; output [7:0]\my_empty_reg[7]_24 ; output [7:0]\my_empty_reg[7]_25 ; output [7:0]\my_empty_reg[7]_26 ; output [7:0]\my_empty_reg[7]_27 ; output [7:0]\my_empty_reg[7]_28 ; output [7:0]\my_empty_reg[7]_29 ; output [7:0]\my_empty_reg[7]_30 ; output [7:0]\my_empty_reg[7]_31 ; output [7:0]\my_empty_reg[7]_32 ; output [7:0]\my_empty_reg[7]_33 ; output [7:0]\my_empty_reg[7]_34 ; output [7:0]\my_empty_reg[7]_35 ; output [7:0]\my_empty_reg[7]_36 ; output [7:0]\my_empty_reg[7]_37 ; output [7:0]\my_empty_reg[7]_38 ; output [7:0]\my_empty_reg[7]_39 ; output [7:0]\my_empty_reg[7]_40 ; output [7:0]\my_empty_reg[7]_41 ; output [7:0]\my_empty_reg[7]_42 ; output [7:0]\my_empty_reg[7]_43 ; output \byte_r_reg[0] ; output \byte_r_reg[1] ; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]\zero2fuzz_r_reg[0] ; output maint_prescaler_r1; output \cmd_pipe_plus.mc_data_offset_reg[3] ; output [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; output \cmd_pipe_plus.mc_data_offset_reg[4] ; output \cmd_pipe_plus.mc_data_offset_reg[2] ; output \cmd_pipe_plus.mc_data_offset_reg[1] ; output \cmd_pipe_plus.mc_data_offset_1_reg[3] ; output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; output \cmd_pipe_plus.mc_data_offset_1_reg[4] ; output \cmd_pipe_plus.mc_data_offset_1_reg[2] ; output \cmd_pipe_plus.mc_data_offset_1_reg[1] ; output \cmd_pipe_plus.mc_data_offset_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ; output [1:0]\idelay_tap_cnt_r_reg[0][3][0] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output \fine_delay_mod_reg[5] ; output \fine_delay_mod_reg[20] ; output [10:0]\phy_ctl_wd_i1_reg[24] ; output phy_write_calib; output phy_read_calib; output \fine_delay_mod_reg[26] ; output \genblk9[1].fine_delay_incdec_pb_reg[1] ; output \genblk9[2].fine_delay_incdec_pb_reg[2] ; output \genblk9[3].fine_delay_incdec_pb_reg[3] ; output \genblk9[5].fine_delay_incdec_pb_reg[5] ; output \genblk9[6].fine_delay_incdec_pb_reg[6] ; output \genblk9[7].fine_delay_incdec_pb_reg[7] ; output mux_wrdata_en; output mux_cmd_wren; output mux_reset_n; output [5:0]\data_offset_1_i1_reg[5] ; output [1:0]\rd_ptr_timing_reg[0]_4 ; output [1:0]\my_full_reg[3]_0 ; output \byte_sel_data_map_reg[1] ; output \A[0]__4 ; output \A[0]__0 ; output \A[2]__2 ; output \A[1]__0 ; output \A[1]__4_0 ; output \A[1]__3 ; output \A[2]__1 ; output [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ; output [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ; output [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ; output [7:0]\fine_delay_r_reg[26] ; output [7:0]\fine_delay_r_reg[26]_0 ; output [7:0]\fine_delay_r_reg[26]_1 ; output [0:0]\qcntr_r_reg[0] ; input CLK; input rstdiv0_sync_r1_reg_rep__20; input poc_sample_pd; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__9; input phy_rddata_en; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ; input \po_stg2_wrcal_cnt_reg[1] ; input \po_stg2_wrcal_cnt_reg[1]_0 ; input \po_stg2_wrcal_cnt_reg[1]_1 ; input \po_stg2_wrcal_cnt_reg[1]_2 ; input \mcGo_r_reg[15] ; input [3:0]in0; input rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__24; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input \rd_mux_sel_r_reg[1] ; input \rd_mux_sel_r_reg[1]_0 ; input \rd_mux_sel_r_reg[1]_1 ; input \rd_mux_sel_r_reg[1]_2 ; input \rd_mux_sel_r_reg[1]_3 ; input \rd_mux_sel_r_reg[1]_4 ; input \rd_mux_sel_r_reg[1]_5 ; input \rd_mux_sel_r_reg[1]_6 ; input \rd_mux_sel_r_reg[1]_7 ; input \rd_mux_sel_r_reg[1]_8 ; input \rd_mux_sel_r_reg[1]_9 ; input \rd_mux_sel_r_reg[1]_10 ; input \rd_mux_sel_r_reg[1]_11 ; input \rd_mux_sel_r_reg[1]_12 ; input \rd_mux_sel_r_reg[1]_13 ; input \rd_mux_sel_r_reg[1]_14 ; input \rd_mux_sel_r_reg[1]_15 ; input \rd_mux_sel_r_reg[1]_16 ; input \rd_mux_sel_r_reg[1]_17 ; input \rd_mux_sel_r_reg[1]_18 ; input \rd_mux_sel_r_reg[1]_19 ; input \rd_mux_sel_r_reg[1]_20 ; input \rd_mux_sel_r_reg[1]_21 ; input \rd_mux_sel_r_reg[1]_22 ; input \rd_mux_sel_r_reg[1]_23 ; input \rd_mux_sel_r_reg[1]_24 ; input \rd_mux_sel_r_reg[1]_25 ; input \rd_mux_sel_r_reg[1]_26 ; input \rd_mux_sel_r_reg[1]_27 ; input \rd_mux_sel_r_reg[1]_28 ; input \rd_mux_sel_r_reg[1]_29 ; input \rd_mux_sel_r_reg[1]_30 ; input \rd_mux_sel_r_reg[1]_31 ; input \rd_mux_sel_r_reg[1]_32 ; input \rd_mux_sel_r_reg[1]_33 ; input \rd_mux_sel_r_reg[1]_34 ; input \rd_mux_sel_r_reg[1]_35 ; input \rd_mux_sel_r_reg[1]_36 ; input \rd_mux_sel_r_reg[1]_37 ; input \rd_mux_sel_r_reg[1]_38 ; input \rd_mux_sel_r_reg[1]_39 ; input \rd_mux_sel_r_reg[1]_40 ; input \rd_mux_sel_r_reg[1]_41 ; input \rd_mux_sel_r_reg[1]_42 ; input \rd_mux_sel_r_reg[1]_43 ; input \rd_mux_sel_r_reg[1]_44 ; input \rd_mux_sel_r_reg[1]_45 ; input \rd_mux_sel_r_reg[1]_46 ; input \rd_mux_sel_r_reg[1]_47 ; input \rd_mux_sel_r_reg[1]_48 ; input \rd_mux_sel_r_reg[1]_49 ; input \rd_mux_sel_r_reg[1]_50 ; input \rd_mux_sel_r_reg[1]_51 ; input \rd_mux_sel_r_reg[1]_52 ; input \rd_mux_sel_r_reg[1]_53 ; input \rd_mux_sel_r_reg[1]_54 ; input \rd_mux_sel_r_reg[1]_55 ; input \rd_mux_sel_r_reg[1]_56 ; input \rd_mux_sel_r_reg[1]_57 ; input \rd_mux_sel_r_reg[1]_58 ; input \rd_mux_sel_r_reg[1]_59 ; input \rd_mux_sel_r_reg[1]_60 ; input \rd_mux_sel_r_reg[1]_61 ; input \rd_mux_sel_r_reg[1]_62 ; input rstdiv0_sync_r1_reg_rep__23; input [0:0]SR; input A_rst_primitives_reg; input [0:0]rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [0:0]rstdiv0_sync_r1_reg_rep__18; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input tempmon_sample_en; input rstdiv0_sync_r1_reg_rep__7; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ; input \A[1]_0 ; input \A[1]_1 ; input \A[1]_2 ; input \A[1]_3 ; input \A[1]_4 ; input \A[1]_5 ; input \A[1]_6 ; input \A[1]_7 ; input \A[1]_8 ; input \A[1]_9 ; input \A[1]_10 ; input \A[1]_11 ; input \A[1]_12 ; input \A[1]_13 ; input \A[1]_14 ; input \A[1]_15 ; input \A[1]_16 ; input \A[1]_17 ; input \A[1]_18 ; input \A[1]_19 ; input \A[1]_20 ; input \A[1]_21 ; input \A[1]_22 ; input \A[1]_23 ; input \A[1]_24 ; input \A[1]_25 ; input \A[1]_26 ; input \A[1]_27 ; input \A[1]_28 ; input \A[1]_29 ; input \A[1]_30 ; input \A[1]_31 ; input \A[1]_32 ; input \A[1]_33 ; input \A[1]_34 ; input \A[1]_35 ; input \A[1]_36 ; input \A[1]_37 ; input \A[1]_38 ; input \A[1]_39 ; input \A[1]_40 ; input \A[1]_41 ; input \A[1]_42 ; input \A[1]_43 ; input \A[1]_44 ; input \A[1]_45 ; input \A[1]_46 ; input \A[1]_47 ; input \A[1]_48 ; input \A[1]_49 ; input \A[1]_50 ; input \A[1]_51 ; input \A[1]_52 ; input \A[1]_53 ; input \A[1]_54 ; input \A[1]_55 ; input \A[1]_56 ; input \A[1]_57 ; input \A[1]_58 ; input \A[1]_59 ; input \A[1]_60 ; input \A[1]_61 ; input \A[1]_62 ; input \A[1]_63 ; input rstdiv0_sync_r1_reg_rep__8; input rstdiv0_sync_r1_reg_rep; input p_0_out; input \po_stg2_wrcal_cnt_reg[1]_3 ; input \po_stg2_wrcal_cnt_reg[1]_4 ; input \po_stg2_wrcal_cnt_reg[1]_5 ; input \po_stg2_wrcal_cnt_reg[1]_6 ; input \po_stg2_wrcal_cnt_reg[1]_7 ; input \po_stg2_wrcal_cnt_reg[1]_8 ; input \po_stg2_wrcal_cnt_reg[1]_9 ; input \po_stg2_wrcal_cnt_reg[1]_10 ; input \po_stg2_wrcal_cnt_reg[1]_11 ; input \po_stg2_wrcal_cnt_reg[1]_12 ; input \po_stg2_wrcal_cnt_reg[1]_13 ; input \po_stg2_wrcal_cnt_reg[1]_14 ; input \po_stg2_wrcal_cnt_reg[1]_15 ; input \po_stg2_wrcal_cnt_reg[1]_16 ; input \po_stg2_wrcal_cnt_reg[1]_17 ; input \po_stg2_wrcal_cnt_reg[1]_18 ; input \po_stg2_wrcal_cnt_reg[1]_19 ; input \po_stg2_wrcal_cnt_reg[1]_20 ; input \po_stg2_wrcal_cnt_reg[1]_21 ; input \po_stg2_wrcal_cnt_reg[1]_22 ; input \po_stg2_wrcal_cnt_reg[1]_23 ; input \po_stg2_wrcal_cnt_reg[1]_24 ; input \po_stg2_wrcal_cnt_reg[1]_25 ; input \po_stg2_wrcal_cnt_reg[1]_26 ; input \po_stg2_wrcal_cnt_reg[1]_27 ; input \po_stg2_wrcal_cnt_reg[1]_28 ; input \po_stg2_wrcal_cnt_reg[1]_29 ; input \po_stg2_wrcal_cnt_reg[1]_30 ; input \po_stg2_wrcal_cnt_reg[1]_31 ; input \po_stg2_wrcal_cnt_reg[1]_32 ; input \po_stg2_wrcal_cnt_reg[1]_33 ; input \po_stg2_wrcal_cnt_reg[1]_34 ; input \po_stg2_wrcal_cnt_reg[1]_35 ; input \po_stg2_wrcal_cnt_reg[1]_36 ; input \po_stg2_wrcal_cnt_reg[1]_37 ; input \po_stg2_wrcal_cnt_reg[1]_38 ; input \po_stg2_wrcal_cnt_reg[1]_39 ; input \po_stg2_wrcal_cnt_reg[1]_40 ; input \po_stg2_wrcal_cnt_reg[1]_41 ; input \po_stg2_wrcal_cnt_reg[1]_42 ; input \po_stg2_wrcal_cnt_reg[1]_43 ; input \po_stg2_wrcal_cnt_reg[1]_44 ; input \po_stg2_wrcal_cnt_reg[1]_45 ; input \po_stg2_wrcal_cnt_reg[1]_46 ; input \po_stg2_wrcal_cnt_reg[1]_47 ; input \po_stg2_wrcal_cnt_reg[1]_48 ; input \po_stg2_wrcal_cnt_reg[1]_49 ; input \po_stg2_wrcal_cnt_reg[1]_50 ; input \po_stg2_wrcal_cnt_reg[1]_51 ; input \po_stg2_wrcal_cnt_reg[1]_52 ; input \po_stg2_wrcal_cnt_reg[1]_53 ; input \po_stg2_wrcal_cnt_reg[1]_54 ; input \po_stg2_wrcal_cnt_reg[1]_55 ; input \po_stg2_wrcal_cnt_reg[1]_56 ; input \po_stg2_wrcal_cnt_reg[1]_57 ; input \po_stg2_wrcal_cnt_reg[1]_58 ; input \po_stg2_wrcal_cnt_reg[1]_59 ; input \po_stg2_wrcal_cnt_reg[1]_60 ; input \po_stg2_wrcal_cnt_reg[1]_61 ; input rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__6; input [0:0]rstdiv0_sync_r1_reg_rep__5; input [287:0]Q; input idelay_ld_rst; input idelay_ld_rst_3; input idelay_ld_rst_4; input idelay_ld_rst_5; input rstdiv0_sync_r1_reg_rep__26; input rstdiv0_sync_r1_reg_rep__26_0; input rstdiv0_sync_r1_reg_rep__25; input [0:0]\sm_r_reg[0]_0 ; input fine_delay_sel_r; input [8:0]fine_delay_mod; input [2:0]mc_cas_n; input [37:0]\rd_ptr_reg[3] ; input \my_empty_reg[1] ; input [5:0]mem_out; input \my_empty_reg[1]_0 ; input [2:0]mc_ras_n; input [0:0]mc_odt; input [11:0]\rd_ptr_reg[3]_0 ; input \my_empty_reg[1]_1 ; input [0:0]mc_cke; input [2:0]mc_we_n; input [35:0]\cmd_pipe_plus.mc_address_reg[44] ; input [31:0]\rd_ptr_reg[3]_1 ; input \my_empty_reg[1]_2 ; input [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; input [63:0]\rd_ptr_reg[3]_2 ; input \my_empty_reg[1]_3 ; input [63:0]\rd_ptr_reg[3]_3 ; input \my_empty_reg[1]_4 ; input [63:0]\rd_ptr_reg[3]_4 ; input \my_empty_reg[1]_5 ; input [63:0]\rd_ptr_reg[3]_5 ; input \my_empty_reg[1]_6 ; input [0:0]mc_cs_n; input [5:0]\pi_counter_read_val_reg[5] ; input \po_counter_read_val_reg[2] ; input rstdiv0_sync_r1_reg_rep__26_1; input rstdiv0_sync_r1_reg_rep__26_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input sent_col; input [4:0]\po_counter_read_val_reg[8]_30 ; input [4:0]\po_counter_read_val_reg[8]_31 ; input [5:0]\po_counter_read_val_reg[5] ; input \A[2]__2_0 ; input psdone; input rstdiv0_sync_r1_reg_rep__0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [63:0]\byte_r_reg[0]_0 ; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__24_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__24_1; input [0:0]rstdiv0_sync_r1_reg_rep__17; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [0:0]my_empty; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; input [0:0]my_empty_6; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; input [0:0]my_empty_7; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [0:0]my_empty_8; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; input [0:0]po_cnt_dec_reg; input [11:0]\device_temp_r_reg[11] ; input mc_wrdata_en; input \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; input [1:0]mc_cmd; input \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[2]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[3]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; input \stg3_r_reg[0] ; input pd_out; wire [1:0]A; wire \A[0]__0 ; wire \A[0]__4 ; wire \A[1]_0 ; wire \A[1]_1 ; wire \A[1]_10 ; wire \A[1]_11 ; wire \A[1]_12 ; wire \A[1]_13 ; wire \A[1]_14 ; wire \A[1]_15 ; wire \A[1]_16 ; wire \A[1]_17 ; wire \A[1]_18 ; wire \A[1]_19 ; wire \A[1]_2 ; wire \A[1]_20 ; wire \A[1]_21 ; wire \A[1]_22 ; wire \A[1]_23 ; wire \A[1]_24 ; wire \A[1]_25 ; wire \A[1]_26 ; wire \A[1]_27 ; wire \A[1]_28 ; wire \A[1]_29 ; wire \A[1]_3 ; wire \A[1]_30 ; wire \A[1]_31 ; wire \A[1]_32 ; wire \A[1]_33 ; wire \A[1]_34 ; wire \A[1]_35 ; wire \A[1]_36 ; wire \A[1]_37 ; wire \A[1]_38 ; wire \A[1]_39 ; wire \A[1]_4 ; wire \A[1]_40 ; wire \A[1]_41 ; wire \A[1]_42 ; wire \A[1]_43 ; wire \A[1]_44 ; wire \A[1]_45 ; wire \A[1]_46 ; wire \A[1]_47 ; wire \A[1]_48 ; wire \A[1]_49 ; wire \A[1]_5 ; wire \A[1]_50 ; wire \A[1]_51 ; wire \A[1]_52 ; wire \A[1]_53 ; wire \A[1]_54 ; wire \A[1]_55 ; wire \A[1]_56 ; wire \A[1]_57 ; wire \A[1]_58 ; wire \A[1]_59 ; wire \A[1]_6 ; wire \A[1]_60 ; wire \A[1]_61 ; wire \A[1]_62 ; wire \A[1]_63 ; wire \A[1]_7 ; wire \A[1]_8 ; wire \A[1]_9 ; wire \A[1]__0 ; wire \A[1]__3 ; wire \A[1]__4 ; wire \A[1]__4_0 ; wire \A[2]__1 ; wire \A[2]__2 ; wire \A[2]__2_0 ; wire A_1__s_net_1; wire A_rst_primitives_reg; wire CLK; wire [5:0]COUNTERLOADVAL; wire [7:0]D; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]E; wire LD0; wire LD0_0; wire LD0_1; wire LD0_2; wire [287:0]Q; wire [0:0]SR; wire [0:0]SS; wire app_zq_r_reg; wire bit_cnt; wire burst_addr_r_i_1_n_0; wire \byte_r_reg[0] ; wire [63:0]\byte_r_reg[0]_0 ; wire \byte_r_reg[1] ; wire [2:2]byte_sel_cnt; wire \byte_sel_data_map_reg[1] ; wire cal1_cnt_cpt_r1; wire cal1_state_r1535_out; wire cal1_wait_r; wire cal2_done_r; wire cal2_done_r_i_1_n_0; wire cal2_if_reset_i_1_n_0; wire calib_complete; wire calib_in_common; wire [1:1]calib_zero_inputs; wire [0:0]calib_zero_inputs__0; wire ck_addr_cmd_delay_done; wire ck_po_stg2_f_en; wire ck_po_stg2_f_en_i_1_n_0; wire ck_po_stg2_f_indec; wire ck_po_stg2_f_indec_i_1_n_0; wire cmd_delay_start0; wire [35:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[2]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[3]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; wire cmd_po_en_stg2_f; wire cnt_cmd_done_r; wire cnt_dllk_zqinit_done_r; wire cnt_dllk_zqinit_done_r_i_1_n_0; wire [7:6]cnt_dllk_zqinit_r_reg__0; wire cnt_init_af_done_r; wire cnt_init_af_done_r_i_1_n_0; wire [1:0]cnt_init_af_r; wire cnt_init_mr_done_r; wire cnt_init_mr_done_r_i_1_n_0; wire [1:0]cnt_init_mr_r; wire cnt_init_mr_r1; wire cnt_pwron_cke_done_r; wire cnt_pwron_cke_done_r_i_1_n_0; wire [7:0]cnt_pwron_r_reg__0; wire cnt_pwron_reset_done_r; wire cnt_pwron_reset_done_r0; wire cnt_pwron_reset_done_r_i_1_n_0; wire cnt_shift_r0; wire cnt_txpr_done_r; wire cnt_txpr_done_r_i_1_n_0; wire [2:0]cnt_txpr_r_reg__0; wire cnt_wait_state; wire complex_act_start; wire complex_init_pi_dec_done; wire complex_init_pi_dec_done_r_i_1_n_0; wire complex_ocal_num_samples_done_r; wire [2:0]complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_reset_rd_addr; wire complex_oclk_calib_resume; wire complex_pi_incdec_done; wire complex_pi_incdec_done_i_1_n_0; wire \complex_row_cnt_ocal_reg[0] ; wire [2:0]ctl_lane_cnt; wire ctl_lane_sel; wire [5:0]\data_offset_1_i1_reg[5] ; wire ddr2_pre_flag_r_i_1_n_0; wire ddr2_refresh_flag_r; wire ddr2_refresh_flag_r_i_1_n_0; wire ddr3_lm_done_r; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ; (* MAX_FANOUT = "100" *) (* RTL_MAX_FANOUT = "found" *) wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ; (* MAX_FANOUT = "100" *) (* RTL_MAX_FANOUT = "found" *) wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ; wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ; wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ; wire ddr_phy_tempmon_0_n_2; wire ddr_phy_tempmon_0_n_3; wire ddr_phy_tempmon_0_n_4; wire ddr_phy_tempmon_0_n_5; wire ddr_phy_tempmon_0_n_6; wire [5:0]dec_cnt_reg; wire detect_edge_done_r; wire detect_pi_found_dqs; wire [11:0]\device_temp_r_reg[11] ; wire done_dqs_dec239_out; wire done_dqs_tap_inc; wire dq_cnt_inc_i_1_n_0; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; wire dqs_found_prech_req; wire dqs_found_prech_req_i_1_n_0; wire dqs_po_dec_done; wire dqs_po_dec_done_r2; wire dqs_po_en_stg2_f; wire dqs_po_en_stg2_f_reg; wire dqs_po_stg2_f_incdec; wire dqs_wl_po_stg2_c_incdec; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_103 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_104 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_109 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_110 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_111 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_73 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_78 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_79 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_80 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_95 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ; wire \dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ; wire early1_data_i_1_n_0; wire early2_data_i_1_n_0; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire [2:1]final_coarse_tap; wire final_dec_done_i_1_n_0; wire fine_adj_state_r144_out; wire fine_adj_state_r16_out; wire fine_adjust_done_r_i_1_n_0; wire fine_adjust_i_1_n_0; wire fine_adjust_reg; wire [8:0]fine_delay_mod; wire \fine_delay_mod_reg[20] ; wire \fine_delay_mod_reg[26] ; wire \fine_delay_mod_reg[5] ; wire [7:0]\fine_delay_r_reg[26] ; wire [7:0]\fine_delay_r_reg[26]_0 ; wire [7:0]\fine_delay_r_reg[26]_1 ; wire [0:0]\fine_delay_r_reg[2] ; wire [0:0]\fine_delay_r_reg[5] ; wire [0:0]\fine_delay_r_reg[5]_0 ; wire [0:0]\fine_delay_r_reg[5]_1 ; wire fine_delay_sel_i_1_n_0; wire fine_delay_sel_r; wire fine_delay_sel_r_reg; wire fine_dly_error_i_1_n_0; wire first_rdlvl_pat_r; wire first_wrcal_pat_r; wire flag_ck_negedge09_out; wire flag_ck_negedge_i_1_n_0; wire found_first_edge_r_i_1_n_0; wire found_second_edge_r_i_1_n_0; wire found_stable_eye_last_r; wire found_stable_eye_last_r_i_1_n_0; wire [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ; wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ; wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ; wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ; wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ; wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ; wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ; wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ; wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ; wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ; wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ; wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ; wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ; wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ; wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ; wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ; wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ; wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ; wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ; wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ; wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ; wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ; wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ; wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ; wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ; wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ; wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ; wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ; wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ; wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ; wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ; wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ; wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ; wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ; wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ; wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ; wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ; wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ; wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ; wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ; wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ; wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ; wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ; wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ; wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ; wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ; wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ; wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ; wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ; wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ; wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ; wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ; wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ; wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ; wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ; wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ; wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ; wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ; wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ; wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ; wire \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ; wire \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg ; wire \genblk8[0].left_edge_found_pb[0]_i_1_n_0 ; wire \genblk8[0].left_edge_updated[0]_i_1_n_0 ; wire \genblk8[0].right_edge_found_pb[0]_i_1_n_0 ; wire \genblk8[1].left_edge_found_pb[1]_i_1_n_0 ; wire \genblk8[1].left_edge_updated[1]_i_1_n_0 ; wire \genblk8[1].right_edge_found_pb[1]_i_1_n_0 ; wire \genblk8[2].left_edge_found_pb[2]_i_1_n_0 ; wire \genblk8[2].left_edge_updated[2]_i_1_n_0 ; wire \genblk8[2].right_edge_found_pb[2]_i_1_n_0 ; wire \genblk8[3].left_edge_found_pb[3]_i_1_n_0 ; wire \genblk8[3].left_edge_updated[3]_i_1_n_0 ; wire \genblk8[3].right_edge_found_pb[3]_i_1_n_0 ; wire \genblk8[4].left_edge_found_pb[4]_i_1_n_0 ; wire \genblk8[4].left_edge_updated[4]_i_1_n_0 ; wire \genblk8[4].right_edge_found_pb[4]_i_1_n_0 ; wire \genblk8[5].left_edge_found_pb[5]_i_1_n_0 ; wire \genblk8[5].left_edge_updated[5]_i_1_n_0 ; wire \genblk8[5].right_edge_found_pb[5]_i_1_n_0 ; wire \genblk8[6].left_edge_found_pb[6]_i_1_n_0 ; wire \genblk8[6].left_edge_updated[6]_i_1_n_0 ; wire \genblk8[6].right_edge_found_pb[6]_i_1_n_0 ; wire \genblk8[7].left_edge_found_pb[7]_i_1_n_0 ; wire \genblk8[7].left_edge_updated[7]_i_1_n_0 ; wire \genblk8[7].right_edge_found_pb[7]_i_1_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ; wire \genblk9[1].fine_delay_incdec_pb_reg[1] ; wire \genblk9[2].fine_delay_incdec_pb_reg[2] ; wire \genblk9[3].fine_delay_incdec_pb_reg[3] ; wire \genblk9[5].fine_delay_incdec_pb_reg[5] ; wire \genblk9[6].fine_delay_incdec_pb_reg[6] ; wire \genblk9[7].fine_delay_incdec_pb_reg[7] ; wire idel_adj_inc_i_1_n_0; wire idel_pat_detect_valid_r_i_1_n_0; wire idelay_ce; wire idelay_ce_int; wire idelay_ce_r1; wire idelay_inc; wire idelay_inc_int; wire idelay_inc_r1; wire idelay_ld; wire idelay_ld_done_i_1_n_0; wire idelay_ld_i_1_n_0; wire idelay_ld_rst; wire idelay_ld_rst_3; wire idelay_ld_rst_4; wire idelay_ld_rst_5; wire [1:0]\idelay_tap_cnt_r_reg[0][3][0] ; wire ififo_rst_reg; wire ififo_rst_reg_0; wire ififo_rst_reg_1; wire ififo_rst_reg_2; wire [3:0]in0; wire inhibit_edge_detect_r; wire inhibit_edge_detect_r_i_1_n_0; wire init_calib_complete_r_reg; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__0_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__10_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__11_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__12_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__13_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__1_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__2_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__3_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__4_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__8_n_0; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__9_n_0; wire init_complete_r_i_1_n_0; wire init_complete_r_timing_i_1_n_0; wire init_complete_r_timing_orig; wire init_dec_done_i_1_n_0; wire init_dqsfound_done_r2; wire init_dqsfound_done_r5; wire init_dqsfound_done_r_i_1_n_0; wire [6:6]init_state_r; wire [7:0]left_edge_updated; wire lim2init_prech_req; wire maint_prescaler_r1; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ; wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ; wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ; wire \mcGo_r_reg[15] ; wire [2:0]mc_cas_n; wire [0:0]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_we_n; wire mc_wrdata_en; wire mem_init_done_r; wire [5:0]mem_out; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mpr_dec_cpt_r_i_1_n_0; wire mpr_end_if_reset; wire mpr_last_byte_done; wire mpr_last_byte_done_i_1_n_0; wire mpr_rank_done_r_i_1_n_0; wire mpr_rdlvl_done_r_i_1_n_0; wire mpr_rdlvl_start_r; wire mpr_rnk_done; wire mux_cmd_wren; wire mux_reset_n; wire mux_wrdata_en; wire [0:0]my_empty; wire [0:0]my_empty_6; wire [0:0]my_empty_7; wire [0:0]my_empty_8; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire \my_empty_reg[7] ; wire \my_empty_reg[7]_0 ; wire [71:0]\my_empty_reg[7]_1 ; wire [3:0]\my_empty_reg[7]_10 ; wire [3:0]\my_empty_reg[7]_11 ; wire [7:0]\my_empty_reg[7]_12 ; wire [7:0]\my_empty_reg[7]_13 ; wire [7:0]\my_empty_reg[7]_14 ; wire [7:0]\my_empty_reg[7]_15 ; wire [7:0]\my_empty_reg[7]_16 ; wire [7:0]\my_empty_reg[7]_17 ; wire [7:0]\my_empty_reg[7]_18 ; wire [7:0]\my_empty_reg[7]_19 ; wire [71:0]\my_empty_reg[7]_2 ; wire [7:0]\my_empty_reg[7]_20 ; wire [7:0]\my_empty_reg[7]_21 ; wire [7:0]\my_empty_reg[7]_22 ; wire [7:0]\my_empty_reg[7]_23 ; wire [7:0]\my_empty_reg[7]_24 ; wire [7:0]\my_empty_reg[7]_25 ; wire [7:0]\my_empty_reg[7]_26 ; wire [7:0]\my_empty_reg[7]_27 ; wire [7:0]\my_empty_reg[7]_28 ; wire [7:0]\my_empty_reg[7]_29 ; wire [71:0]\my_empty_reg[7]_3 ; wire [7:0]\my_empty_reg[7]_30 ; wire [7:0]\my_empty_reg[7]_31 ; wire [7:0]\my_empty_reg[7]_32 ; wire [7:0]\my_empty_reg[7]_33 ; wire [7:0]\my_empty_reg[7]_34 ; wire [7:0]\my_empty_reg[7]_35 ; wire [7:0]\my_empty_reg[7]_36 ; wire [7:0]\my_empty_reg[7]_37 ; wire [7:0]\my_empty_reg[7]_38 ; wire [7:0]\my_empty_reg[7]_39 ; wire [71:0]\my_empty_reg[7]_4 ; wire [7:0]\my_empty_reg[7]_40 ; wire [7:0]\my_empty_reg[7]_41 ; wire [7:0]\my_empty_reg[7]_42 ; wire [7:0]\my_empty_reg[7]_43 ; wire [3:0]\my_empty_reg[7]_5 ; wire [3:0]\my_empty_reg[7]_6 ; wire [3:0]\my_empty_reg[7]_7 ; wire [3:0]\my_empty_reg[7]_8 ; wire [3:0]\my_empty_reg[7]_9 ; wire [3:0]\my_full_reg[3] ; wire [1:0]\my_full_reg[3]_0 ; wire new_cnt_dqs_r; wire new_cnt_dqs_r_i_1_n_0; wire no_err_win_detected_latch_i_1_n_0; wire num_samples_done_ind_i_1_n_0; wire num_samples_done_r; wire ocal_last_byte_done; wire ocd_prech_req; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ; wire \oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ; wire out; wire p_0_in; wire p_0_in102_in; wire p_0_in10_in; wire p_0_in13_in; wire p_0_in16_in; wire p_0_in1_in; wire p_0_in23_in; wire p_0_in4_in; wire p_0_in7_in; wire p_0_in84_in; wire p_0_in87_in; wire p_0_in90_in; wire p_0_in93_in; wire p_0_in96_in; wire p_0_in99_in; wire [3:2]p_0_in_0; wire p_0_in_2; wire p_0_out; wire p_103_out; wire p_106_out; wire p_119_out; wire p_122_out; wire p_127_out; wire p_130_out; wire p_143_out; wire p_146_out; wire p_154_out; wire p_1_in; wire p_1_in27_in; wire p_1_in50_in; wire p_2_in24_in; wire p_3_in25_in; wire p_81_in; wire p_95_out; wire p_98_out; wire [7:0]pb_detect_edge_done_r; wire pb_found_stable_eye_r52_out; wire pb_found_stable_eye_r56_out; wire pb_found_stable_eye_r60_out; wire pb_found_stable_eye_r64_out; wire pb_found_stable_eye_r68_out; wire pb_found_stable_eye_r72_out; wire pb_found_stable_eye_r76_out; wire pd_out; wire \phaser_in_gen.phaser_in_i_12__0_n_0 ; wire \phaser_in_gen.phaser_in_i_12__1_n_0 ; wire \phaser_in_gen.phaser_in_i_12__2_n_0 ; wire \phaser_in_gen.phaser_in_i_12_n_0 ; wire [10:0]\phy_ctl_wd_i1_reg[24] ; wire [33:0]phy_dout; wire phy_if_reset; wire phy_if_reset0__0; wire phy_if_reset_w; wire phy_rddata_en; wire phy_rddata_en_1; wire phy_read_calib; wire phy_write_calib; wire pi_calib_done; wire pi_cnt_dec_i_1_n_0; wire [0:0]pi_cnt_dec_reg; wire [5:0]\pi_counter_read_val_reg[5] ; wire [1:1]pi_dqs_found_all_bank; wire [1:0]pi_dqs_found_all_bank_r; wire [0:0]pi_dqs_found_any_bank; wire \pi_dqs_found_any_bank[0]_i_1_n_0 ; wire pi_dqs_found_done_r1; wire \pi_dqs_found_lanes_r1_reg[0] ; wire \pi_dqs_found_lanes_r1_reg[0]_0 ; wire \pi_dqs_found_lanes_r1_reg[0]_1 ; wire \pi_dqs_found_lanes_r1_reg[0]_2 ; wire \pi_dqs_found_lanes_r1_reg[1] ; wire \pi_dqs_found_lanes_r1_reg[1]_0 ; wire \pi_dqs_found_lanes_r1_reg[1]_1 ; wire \pi_dqs_found_lanes_r1_reg[1]_2 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ; wire \pi_dqs_found_lanes_r1_reg[2] ; wire \pi_dqs_found_lanes_r1_reg[2]_0 ; wire \pi_dqs_found_lanes_r1_reg[2]_1 ; wire \pi_dqs_found_lanes_r1_reg[2]_2 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ; wire \pi_dqs_found_lanes_r1_reg[3] ; wire \pi_dqs_found_lanes_r1_reg[3]_0 ; wire \pi_dqs_found_lanes_r1_reg[3]_1 ; wire \pi_dqs_found_lanes_r1_reg[3]_2 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ; wire pi_dqs_found_rank_done; wire pi_en_stg2_f_timing_reg; wire pi_fine_dly_dec_done; wire \pi_rst_stg1_cal_r_reg[0] ; wire pi_stg2_f_incdec_timing_i_1_n_0; wire pi_stg2_load_timing_i_1_n_0; wire [1:0]pi_stg2_rdlvl_cnt; wire po_cnt_dec_i_1__0_n_0; wire po_cnt_dec_i_1_n_0; wire [0:0]po_cnt_dec_reg; wire po_cnt_inc_i_1_n_0; wire \po_counter_read_val_reg[2] ; wire [5:0]\po_counter_read_val_reg[5] ; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_10 ; wire \po_counter_read_val_reg[8]_11 ; wire \po_counter_read_val_reg[8]_12 ; wire \po_counter_read_val_reg[8]_13 ; wire \po_counter_read_val_reg[8]_14 ; wire \po_counter_read_val_reg[8]_15 ; wire \po_counter_read_val_reg[8]_16 ; wire \po_counter_read_val_reg[8]_17 ; wire \po_counter_read_val_reg[8]_18 ; wire \po_counter_read_val_reg[8]_19 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_20 ; wire \po_counter_read_val_reg[8]_21 ; wire \po_counter_read_val_reg[8]_22 ; wire \po_counter_read_val_reg[8]_23 ; wire \po_counter_read_val_reg[8]_24 ; wire \po_counter_read_val_reg[8]_25 ; wire \po_counter_read_val_reg[8]_26 ; wire \po_counter_read_val_reg[8]_27 ; wire \po_counter_read_val_reg[8]_28 ; wire \po_counter_read_val_reg[8]_29 ; wire \po_counter_read_val_reg[8]_3 ; wire [4:0]\po_counter_read_val_reg[8]_30 ; wire [4:0]\po_counter_read_val_reg[8]_31 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire \po_counter_read_val_reg[8]_6 ; wire \po_counter_read_val_reg[8]_7 ; wire \po_counter_read_val_reg[8]_8 ; wire \po_counter_read_val_reg[8]_9 ; wire po_en_stg23; wire [0:0]po_enstg2_f; wire [2:0]\po_rdval_cnt_reg[8] ; wire po_stg23_incdec; wire [0:0]po_stg2_fincdec; wire [2:2]po_stg2_wrcal_cnt; wire \po_stg2_wrcal_cnt_reg[1] ; wire \po_stg2_wrcal_cnt_reg[1]_0 ; wire \po_stg2_wrcal_cnt_reg[1]_1 ; wire \po_stg2_wrcal_cnt_reg[1]_10 ; wire \po_stg2_wrcal_cnt_reg[1]_11 ; wire \po_stg2_wrcal_cnt_reg[1]_12 ; wire \po_stg2_wrcal_cnt_reg[1]_13 ; wire \po_stg2_wrcal_cnt_reg[1]_14 ; wire \po_stg2_wrcal_cnt_reg[1]_15 ; wire \po_stg2_wrcal_cnt_reg[1]_16 ; wire \po_stg2_wrcal_cnt_reg[1]_17 ; wire \po_stg2_wrcal_cnt_reg[1]_18 ; wire \po_stg2_wrcal_cnt_reg[1]_19 ; wire \po_stg2_wrcal_cnt_reg[1]_2 ; wire \po_stg2_wrcal_cnt_reg[1]_20 ; wire \po_stg2_wrcal_cnt_reg[1]_21 ; wire \po_stg2_wrcal_cnt_reg[1]_22 ; wire \po_stg2_wrcal_cnt_reg[1]_23 ; wire \po_stg2_wrcal_cnt_reg[1]_24 ; wire \po_stg2_wrcal_cnt_reg[1]_25 ; wire \po_stg2_wrcal_cnt_reg[1]_26 ; wire \po_stg2_wrcal_cnt_reg[1]_27 ; wire \po_stg2_wrcal_cnt_reg[1]_28 ; wire \po_stg2_wrcal_cnt_reg[1]_29 ; wire \po_stg2_wrcal_cnt_reg[1]_3 ; wire \po_stg2_wrcal_cnt_reg[1]_30 ; wire \po_stg2_wrcal_cnt_reg[1]_31 ; wire \po_stg2_wrcal_cnt_reg[1]_32 ; wire \po_stg2_wrcal_cnt_reg[1]_33 ; wire \po_stg2_wrcal_cnt_reg[1]_34 ; wire \po_stg2_wrcal_cnt_reg[1]_35 ; wire \po_stg2_wrcal_cnt_reg[1]_36 ; wire \po_stg2_wrcal_cnt_reg[1]_37 ; wire \po_stg2_wrcal_cnt_reg[1]_38 ; wire \po_stg2_wrcal_cnt_reg[1]_39 ; wire \po_stg2_wrcal_cnt_reg[1]_4 ; wire \po_stg2_wrcal_cnt_reg[1]_40 ; wire \po_stg2_wrcal_cnt_reg[1]_41 ; wire \po_stg2_wrcal_cnt_reg[1]_42 ; wire \po_stg2_wrcal_cnt_reg[1]_43 ; wire \po_stg2_wrcal_cnt_reg[1]_44 ; wire \po_stg2_wrcal_cnt_reg[1]_45 ; wire \po_stg2_wrcal_cnt_reg[1]_46 ; wire \po_stg2_wrcal_cnt_reg[1]_47 ; wire \po_stg2_wrcal_cnt_reg[1]_48 ; wire \po_stg2_wrcal_cnt_reg[1]_49 ; wire \po_stg2_wrcal_cnt_reg[1]_5 ; wire \po_stg2_wrcal_cnt_reg[1]_50 ; wire \po_stg2_wrcal_cnt_reg[1]_51 ; wire \po_stg2_wrcal_cnt_reg[1]_52 ; wire \po_stg2_wrcal_cnt_reg[1]_53 ; wire \po_stg2_wrcal_cnt_reg[1]_54 ; wire \po_stg2_wrcal_cnt_reg[1]_55 ; wire \po_stg2_wrcal_cnt_reg[1]_56 ; wire \po_stg2_wrcal_cnt_reg[1]_57 ; wire \po_stg2_wrcal_cnt_reg[1]_58 ; wire \po_stg2_wrcal_cnt_reg[1]_59 ; wire \po_stg2_wrcal_cnt_reg[1]_6 ; wire \po_stg2_wrcal_cnt_reg[1]_60 ; wire \po_stg2_wrcal_cnt_reg[1]_61 ; wire \po_stg2_wrcal_cnt_reg[1]_7 ; wire \po_stg2_wrcal_cnt_reg[1]_8 ; wire \po_stg2_wrcal_cnt_reg[1]_9 ; wire poc_sample_pd; wire \prbs_dqs_cnt_r[0]_i_1_n_0 ; wire \prbs_dqs_cnt_r[1]_i_1_n_0 ; wire \prbs_dqs_cnt_r[2]_i_1_n_0 ; wire prbs_dqs_tap_limit_r_i_1_n_0; wire prbs_found_1st_edge_r_i_1_n_0; wire prbs_last_byte_done; wire prbs_last_byte_done_i_1_n_0; wire prbs_last_byte_done_r; wire prbs_pi_stg2_f_en; wire prbs_pi_stg2_f_incdec; wire prbs_prech_req_r; wire prbs_prech_req_r_i_1_n_0; wire prbs_rdlvl_done_i_1_n_0; wire prbs_rdlvl_done_pulse0; wire prbs_rdlvl_done_r1; wire prbs_rdlvl_start_r; wire prbs_rdlvl_start_r_reg; wire [4:0]prbs_state_r; wire prbs_state_r178_out; wire prbs_tap_en_r; wire prbs_tap_en_r_i_1_n_0; wire prbs_tap_inc_r; wire prbs_tap_inc_r_i_1_n_0; wire prech_done; wire prech_pending_r; wire prech_pending_r_i_1_n_0; wire prech_req; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire rank_done_r_i_1_n_0; wire rd_active_r1; wire rd_active_r2; wire \rd_addr[7]_i_1_n_0 ; wire \rd_byte_data_offset_reg[0]_3 ; wire rd_data_offset_cal_done; wire [3:2]rd_data_offset_ranks_0; wire [3:2]rd_data_offset_ranks_1; wire \rd_mux_sel_r_reg[1] ; wire \rd_mux_sel_r_reg[1]_0 ; wire \rd_mux_sel_r_reg[1]_1 ; wire \rd_mux_sel_r_reg[1]_10 ; wire \rd_mux_sel_r_reg[1]_11 ; wire \rd_mux_sel_r_reg[1]_12 ; wire \rd_mux_sel_r_reg[1]_13 ; wire \rd_mux_sel_r_reg[1]_14 ; wire \rd_mux_sel_r_reg[1]_15 ; wire \rd_mux_sel_r_reg[1]_16 ; wire \rd_mux_sel_r_reg[1]_17 ; wire \rd_mux_sel_r_reg[1]_18 ; wire \rd_mux_sel_r_reg[1]_19 ; wire \rd_mux_sel_r_reg[1]_2 ; wire \rd_mux_sel_r_reg[1]_20 ; wire \rd_mux_sel_r_reg[1]_21 ; wire \rd_mux_sel_r_reg[1]_22 ; wire \rd_mux_sel_r_reg[1]_23 ; wire \rd_mux_sel_r_reg[1]_24 ; wire \rd_mux_sel_r_reg[1]_25 ; wire \rd_mux_sel_r_reg[1]_26 ; wire \rd_mux_sel_r_reg[1]_27 ; wire \rd_mux_sel_r_reg[1]_28 ; wire \rd_mux_sel_r_reg[1]_29 ; wire \rd_mux_sel_r_reg[1]_3 ; wire \rd_mux_sel_r_reg[1]_30 ; wire \rd_mux_sel_r_reg[1]_31 ; wire \rd_mux_sel_r_reg[1]_32 ; wire \rd_mux_sel_r_reg[1]_33 ; wire \rd_mux_sel_r_reg[1]_34 ; wire \rd_mux_sel_r_reg[1]_35 ; wire \rd_mux_sel_r_reg[1]_36 ; wire \rd_mux_sel_r_reg[1]_37 ; wire \rd_mux_sel_r_reg[1]_38 ; wire \rd_mux_sel_r_reg[1]_39 ; wire \rd_mux_sel_r_reg[1]_4 ; wire \rd_mux_sel_r_reg[1]_40 ; wire \rd_mux_sel_r_reg[1]_41 ; wire \rd_mux_sel_r_reg[1]_42 ; wire \rd_mux_sel_r_reg[1]_43 ; wire \rd_mux_sel_r_reg[1]_44 ; wire \rd_mux_sel_r_reg[1]_45 ; wire \rd_mux_sel_r_reg[1]_46 ; wire \rd_mux_sel_r_reg[1]_47 ; wire \rd_mux_sel_r_reg[1]_48 ; wire \rd_mux_sel_r_reg[1]_49 ; wire \rd_mux_sel_r_reg[1]_5 ; wire \rd_mux_sel_r_reg[1]_50 ; wire \rd_mux_sel_r_reg[1]_51 ; wire \rd_mux_sel_r_reg[1]_52 ; wire \rd_mux_sel_r_reg[1]_53 ; wire \rd_mux_sel_r_reg[1]_54 ; wire \rd_mux_sel_r_reg[1]_55 ; wire \rd_mux_sel_r_reg[1]_56 ; wire \rd_mux_sel_r_reg[1]_57 ; wire \rd_mux_sel_r_reg[1]_58 ; wire \rd_mux_sel_r_reg[1]_59 ; wire \rd_mux_sel_r_reg[1]_6 ; wire \rd_mux_sel_r_reg[1]_60 ; wire \rd_mux_sel_r_reg[1]_61 ; wire \rd_mux_sel_r_reg[1]_62 ; wire \rd_mux_sel_r_reg[1]_7 ; wire \rd_mux_sel_r_reg[1]_8 ; wire \rd_mux_sel_r_reg[1]_9 ; wire [37:0]\rd_ptr_reg[3] ; wire [11:0]\rd_ptr_reg[3]_0 ; wire [31:0]\rd_ptr_reg[3]_1 ; wire [63:0]\rd_ptr_reg[3]_2 ; wire [63:0]\rd_ptr_reg[3]_3 ; wire [63:0]\rd_ptr_reg[3]_4 ; wire [63:0]\rd_ptr_reg[3]_5 ; wire \rd_ptr_timing_reg[0] ; wire [33:0]\rd_ptr_timing_reg[0]_0 ; wire [7:0]\rd_ptr_timing_reg[0]_1 ; wire [7:0]\rd_ptr_timing_reg[0]_2 ; wire [3:0]\rd_ptr_timing_reg[0]_3 ; wire [1:0]\rd_ptr_timing_reg[0]_4 ; wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ; wire rdlvl_last_byte_done; wire rdlvl_last_byte_done_int_i_1_n_0; wire rdlvl_pi_incdec; wire rdlvl_pi_incdec_i_1_n_0; wire rdlvl_prech_req; wire rdlvl_rank_done_r_i_1_n_0; wire [14:14]rdlvl_start_dly0_r; wire rdlvl_start_pre; wire rdlvl_start_pre_i_1_n_0; wire rdlvl_stg1_done_int; wire rdlvl_stg1_done_int_i_1_n_0; wire rdlvl_stg1_rank_done; wire rdlvl_stg1_start_i_1_n_0; wire rdlvl_stg1_start_int; wire [2:2]regl_dqs_cnt; wire reset_if; wire reset_if_r8_reg_srl8_n_0; wire reset_if_r9; wire reset_rd_addr; wire reset_rd_addr0; wire reset_rd_addr_i_1_n_0; wire right_edge_found; wire right_edge_found_i_1_n_0; wire right_gain_pb; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire rst_dqs_find; wire rst_dqs_find_i_1_n_0; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [0:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__24_0; wire rstdiv0_sync_r1_reg_rep__24_1; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__26_1; wire rstdiv0_sync_r1_reg_rep__26_2; wire rstdiv0_sync_r1_reg_rep__4; wire [0:0]rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire samples_cnt_r; wire \samps_r_reg[9] ; wire sel; wire sent_col; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire sr_valid_r108_out; wire stable_cnt1; wire stable_cnt227_in; wire stg1_wr_done; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire store_sr_r_i_1_n_0; wire temp_lmr_done; wire tempmon_pi_f_en_r; wire tempmon_pi_f_inc; wire tempmon_pi_f_inc_r; wire tempmon_sample_en; wire tempmon_sel_pi_incdec; wire u_ddr_phy_init_n_101; wire u_ddr_phy_init_n_102; wire u_ddr_phy_init_n_104; wire u_ddr_phy_init_n_105; wire u_ddr_phy_init_n_106; wire u_ddr_phy_init_n_107; wire u_ddr_phy_init_n_108; wire u_ddr_phy_init_n_109; wire u_ddr_phy_init_n_110; wire u_ddr_phy_init_n_111; wire u_ddr_phy_init_n_114; wire u_ddr_phy_init_n_115; wire u_ddr_phy_init_n_116; wire u_ddr_phy_init_n_117; wire u_ddr_phy_init_n_120; wire u_ddr_phy_init_n_121; wire u_ddr_phy_init_n_122; wire u_ddr_phy_init_n_123; wire u_ddr_phy_init_n_124; wire u_ddr_phy_init_n_125; wire u_ddr_phy_init_n_126; wire u_ddr_phy_init_n_127; wire u_ddr_phy_init_n_18; wire u_ddr_phy_init_n_24; wire u_ddr_phy_init_n_29; wire u_ddr_phy_init_n_31; wire u_ddr_phy_init_n_33; wire u_ddr_phy_init_n_462; wire u_ddr_phy_init_n_464; wire u_ddr_phy_init_n_465; wire u_ddr_phy_init_n_468; wire u_ddr_phy_init_n_469; wire u_ddr_phy_init_n_470; wire u_ddr_phy_init_n_473; wire u_ddr_phy_init_n_474; wire u_ddr_phy_init_n_475; wire u_ddr_phy_init_n_476; wire u_ddr_phy_init_n_477; wire u_ddr_phy_init_n_478; wire u_ddr_phy_init_n_479; wire u_ddr_phy_init_n_480; wire u_ddr_phy_init_n_485; wire u_ddr_phy_init_n_490; wire u_ddr_phy_init_n_496; wire u_ddr_phy_init_n_497; wire u_ddr_phy_init_n_499; wire u_ddr_phy_init_n_500; wire u_ddr_phy_init_n_501; wire u_ddr_phy_init_n_502; wire u_ddr_phy_init_n_784; wire u_ddr_phy_init_n_785; wire u_ddr_phy_init_n_786; wire u_ddr_phy_init_n_790; wire u_ddr_phy_init_n_791; wire u_ddr_phy_init_n_9; wire u_ddr_phy_wrcal_n_100; wire u_ddr_phy_wrcal_n_101; wire u_ddr_phy_wrcal_n_102; wire u_ddr_phy_wrcal_n_103; wire u_ddr_phy_wrcal_n_104; wire u_ddr_phy_wrcal_n_105; wire u_ddr_phy_wrcal_n_106; wire u_ddr_phy_wrcal_n_107; wire u_ddr_phy_wrcal_n_108; wire u_ddr_phy_wrcal_n_109; wire u_ddr_phy_wrcal_n_110; wire u_ddr_phy_wrcal_n_111; wire u_ddr_phy_wrcal_n_112; wire u_ddr_phy_wrcal_n_113; wire u_ddr_phy_wrcal_n_114; wire u_ddr_phy_wrcal_n_115; wire u_ddr_phy_wrcal_n_116; wire u_ddr_phy_wrcal_n_117; wire u_ddr_phy_wrcal_n_118; wire u_ddr_phy_wrcal_n_119; wire u_ddr_phy_wrcal_n_120; wire u_ddr_phy_wrcal_n_4; wire u_ddr_phy_wrcal_n_5; wire u_ddr_phy_wrcal_n_66; wire u_ddr_phy_wrcal_n_67; wire u_ddr_phy_wrcal_n_69; wire u_ddr_phy_wrcal_n_71; wire u_ddr_phy_wrcal_n_73; wire u_ddr_phy_wrcal_n_74; wire u_ddr_phy_wrcal_n_81; wire u_ddr_phy_wrcal_n_82; wire u_ddr_phy_wrcal_n_83; wire u_ddr_phy_wrcal_n_84; wire u_ddr_phy_wrcal_n_85; wire u_ddr_phy_wrcal_n_89; wire u_ddr_phy_wrcal_n_90; wire u_ddr_phy_wrcal_n_91; wire u_ddr_phy_wrcal_n_92; wire u_ddr_phy_wrcal_n_93; wire u_ddr_phy_wrcal_n_94; wire u_ddr_phy_wrcal_n_95; wire u_ddr_phy_wrcal_n_96; wire u_ddr_phy_wrcal_n_97; wire u_ddr_phy_wrcal_n_98; wire u_ddr_prbs_gen_n_0; wire u_ddr_prbs_gen_n_1; wire u_ddr_prbs_gen_n_10; wire u_ddr_prbs_gen_n_100; wire u_ddr_prbs_gen_n_101; wire u_ddr_prbs_gen_n_102; wire u_ddr_prbs_gen_n_103; wire u_ddr_prbs_gen_n_104; wire u_ddr_prbs_gen_n_105; wire u_ddr_prbs_gen_n_106; wire u_ddr_prbs_gen_n_107; wire u_ddr_prbs_gen_n_108; wire u_ddr_prbs_gen_n_109; wire u_ddr_prbs_gen_n_11; wire u_ddr_prbs_gen_n_110; wire u_ddr_prbs_gen_n_111; wire u_ddr_prbs_gen_n_112; wire u_ddr_prbs_gen_n_113; wire u_ddr_prbs_gen_n_114; wire u_ddr_prbs_gen_n_115; wire u_ddr_prbs_gen_n_116; wire u_ddr_prbs_gen_n_117; wire u_ddr_prbs_gen_n_118; wire u_ddr_prbs_gen_n_119; wire u_ddr_prbs_gen_n_12; wire u_ddr_prbs_gen_n_120; wire u_ddr_prbs_gen_n_121; wire u_ddr_prbs_gen_n_13; wire u_ddr_prbs_gen_n_14; wire u_ddr_prbs_gen_n_15; wire u_ddr_prbs_gen_n_16; wire u_ddr_prbs_gen_n_17; wire u_ddr_prbs_gen_n_18; wire u_ddr_prbs_gen_n_19; wire u_ddr_prbs_gen_n_2; wire u_ddr_prbs_gen_n_20; wire u_ddr_prbs_gen_n_21; wire u_ddr_prbs_gen_n_22; wire u_ddr_prbs_gen_n_23; wire u_ddr_prbs_gen_n_24; wire u_ddr_prbs_gen_n_25; wire u_ddr_prbs_gen_n_26; wire u_ddr_prbs_gen_n_27; wire u_ddr_prbs_gen_n_28; wire u_ddr_prbs_gen_n_29; wire u_ddr_prbs_gen_n_3; wire u_ddr_prbs_gen_n_30; wire u_ddr_prbs_gen_n_31; wire u_ddr_prbs_gen_n_32; wire u_ddr_prbs_gen_n_33; wire u_ddr_prbs_gen_n_34; wire u_ddr_prbs_gen_n_35; wire u_ddr_prbs_gen_n_36; wire u_ddr_prbs_gen_n_37; wire u_ddr_prbs_gen_n_38; wire u_ddr_prbs_gen_n_39; wire u_ddr_prbs_gen_n_4; wire u_ddr_prbs_gen_n_40; wire u_ddr_prbs_gen_n_41; wire u_ddr_prbs_gen_n_42; wire u_ddr_prbs_gen_n_43; wire u_ddr_prbs_gen_n_44; wire u_ddr_prbs_gen_n_45; wire u_ddr_prbs_gen_n_46; wire u_ddr_prbs_gen_n_47; wire u_ddr_prbs_gen_n_48; wire u_ddr_prbs_gen_n_49; wire u_ddr_prbs_gen_n_5; wire u_ddr_prbs_gen_n_50; wire u_ddr_prbs_gen_n_51; wire u_ddr_prbs_gen_n_52; wire u_ddr_prbs_gen_n_53; wire u_ddr_prbs_gen_n_54; wire u_ddr_prbs_gen_n_55; wire u_ddr_prbs_gen_n_56; wire u_ddr_prbs_gen_n_57; wire u_ddr_prbs_gen_n_58; wire u_ddr_prbs_gen_n_59; wire u_ddr_prbs_gen_n_6; wire u_ddr_prbs_gen_n_60; wire u_ddr_prbs_gen_n_61; wire u_ddr_prbs_gen_n_62; wire u_ddr_prbs_gen_n_63; wire u_ddr_prbs_gen_n_64; wire u_ddr_prbs_gen_n_65; wire u_ddr_prbs_gen_n_66; wire u_ddr_prbs_gen_n_67; wire u_ddr_prbs_gen_n_68; wire u_ddr_prbs_gen_n_69; wire u_ddr_prbs_gen_n_7; wire u_ddr_prbs_gen_n_70; wire u_ddr_prbs_gen_n_71; wire u_ddr_prbs_gen_n_72; wire u_ddr_prbs_gen_n_73; wire u_ddr_prbs_gen_n_74; wire u_ddr_prbs_gen_n_75; wire u_ddr_prbs_gen_n_76; wire u_ddr_prbs_gen_n_77; wire u_ddr_prbs_gen_n_78; wire u_ddr_prbs_gen_n_79; wire u_ddr_prbs_gen_n_8; wire u_ddr_prbs_gen_n_80; wire u_ddr_prbs_gen_n_81; wire u_ddr_prbs_gen_n_82; wire u_ddr_prbs_gen_n_83; wire u_ddr_prbs_gen_n_84; wire u_ddr_prbs_gen_n_85; wire u_ddr_prbs_gen_n_86; wire u_ddr_prbs_gen_n_87; wire u_ddr_prbs_gen_n_88; wire u_ddr_prbs_gen_n_89; wire u_ddr_prbs_gen_n_9; wire u_ddr_prbs_gen_n_90; wire u_ddr_prbs_gen_n_91; wire u_ddr_prbs_gen_n_92; wire u_ddr_prbs_gen_n_93; wire u_ddr_prbs_gen_n_94; wire u_ddr_prbs_gen_n_95; wire u_ddr_prbs_gen_n_96; wire u_ddr_prbs_gen_n_97; wire u_ddr_prbs_gen_n_98; wire u_ddr_prbs_gen_n_99; wire [2:0]\u_ocd_lim/stg2_tap_cnt_reg ; wire [2:0]\u_ocd_lim/stg3_dec_val00_out ; wire [2:0]\u_ocd_lim/stg3_init_val ; wire [8:2]\u_ocd_po_cntlr/stg2_target_ns ; wire [1:0]wait_cnt_r_reg__0; wire [0:0]wait_cnt_r_reg__0_1; wire wl_edge_detect_valid_r_i_1_n_0; wire [0:0]wl_po_fine_cnt_sel_0; wire [2:1]wl_po_fine_cnt_sel_0__0; wire wl_sm_start; wire wr_level_done_i_1_n_0; wire wr_level_done_r_i_1_n_0; wire wrcal_pat_resume_r; wire wrcal_pat_resume_r_i_1_n_0; wire wrcal_prech_req; wire wrcal_rd_wait; wire wrcal_resume_r; wire wrcal_resume_w; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done_i_1_n_0; wire wrlvl_byte_done; wire wrlvl_byte_redo; wire wrlvl_byte_redo_i_1_n_0; wire wrlvl_byte_redo_r; wire wrlvl_done_r1; wire wrlvl_final_if_rst; wire wrlvl_final_mux; wire wrlvl_final_r; wire wrlvl_rank_done; wire wrlvl_rank_done_r_i_1_n_0; wire [0:0]\zero2fuzz_r_reg[0] ; assign A_1__s_port_ = A_1__s_net_1; (* SOFT_HLUTNM = "soft_lutpair730" *) LUT3 #( .INIT(8'h08)) \A[0]__0_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(byte_sel_cnt), .O(\A[0]__0 )); (* SOFT_HLUTNM = "soft_lutpair729" *) LUT3 #( .INIT(8'h20)) \A[0]__4_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(byte_sel_cnt), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .O(\A[0]__4 )); (* SOFT_HLUTNM = "soft_lutpair729" *) LUT3 #( .INIT(8'h02)) \A[1]__0_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(byte_sel_cnt), .O(\A[1]__0 )); (* SOFT_HLUTNM = "soft_lutpair733" *) LUT2 #( .INIT(4'h2)) \A[1]__3_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(byte_sel_cnt), .O(\A[1]__3 )); (* SOFT_HLUTNM = "soft_lutpair728" *) LUT3 #( .INIT(8'h02)) \A[1]__4_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(byte_sel_cnt), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .O(\A[1]__4_0 )); (* SOFT_HLUTNM = "soft_lutpair732" *) LUT2 #( .INIT(4'h1)) \A[1]_i_1 (.I0(byte_sel_cnt), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .O(\A[1]__4 )); (* SOFT_HLUTNM = "soft_lutpair732" *) LUT2 #( .INIT(4'h4)) \A[1]_i_2 (.I0(byte_sel_cnt), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .O(A_1__s_net_1)); (* SOFT_HLUTNM = "soft_lutpair733" *) LUT1 #( .INIT(2'h1)) \A[2]__1_i_1 (.I0(byte_sel_cnt), .O(\A[2]__1 )); (* SOFT_HLUTNM = "soft_lutpair730" *) LUT3 #( .INIT(8'h07)) \A[2]__2_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(byte_sel_cnt), .O(\A[2]__2 )); LUT5 #( .INIT(32'h000000AB)) burst_addr_r_i_1 (.I0(u_ddr_phy_init_n_476), .I1(u_ddr_phy_init_n_31), .I2(u_ddr_phy_init_n_109), .I3(u_ddr_phy_wrcal_n_82), .I4(rstdiv0_sync_r1_reg_rep__24), .O(burst_addr_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair728" *) LUT3 #( .INIT(8'h40)) \byte_sel_data_map[1]_i_1 (.I0(byte_sel_cnt), .I1(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .O(\byte_sel_data_map_reg[1] )); LUT4 #( .INIT(16'hBFB0)) cal2_done_r_i_1 (.I0(u_ddr_phy_wrcal_n_5), .I1(wrcal_sanity_chk), .I2(u_ddr_phy_wrcal_n_117), .I3(cal2_done_r), .O(cal2_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFBABF00008A80)) cal2_if_reset_i_1 (.I0(u_ddr_phy_wrcal_n_120), .I1(u_ddr_phy_wrcal_n_115), .I2(u_ddr_phy_wrcal_n_111), .I3(u_ddr_phy_wrcal_n_114), .I4(u_ddr_phy_wrcal_n_108), .I5(phy_if_reset_w), .O(cal2_if_reset_i_1_n_0)); (* syn_maxfan = "10" *) FDRE \calib_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_104 ), .Q(\po_rdval_cnt_reg[8] [0]), .R(1'b0)); (* syn_maxfan = "10" *) FDRE \calib_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_103 ), .Q(\po_rdval_cnt_reg[8] [1]), .R(1'b0)); (* syn_maxfan = "10" *) FDRE \calib_sel_reg[3] (.C(CLK), .CE(1'b1), .D(ddr_phy_tempmon_0_n_3), .Q(\po_rdval_cnt_reg[8] [2]), .R(1'b0)); (* syn_maxfan = "10" *) FDRE \calib_zero_inputs_reg[0] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ), .Q(calib_zero_inputs__0), .R(1'b0)); (* syn_maxfan = "10" *) FDRE \calib_zero_inputs_reg[1] (.C(CLK), .CE(1'b1), .D(ddr_phy_tempmon_0_n_4), .Q(calib_zero_inputs), .R(1'b0)); LUT5 #( .INIT(32'hDFBF0820)) ck_po_stg2_f_en_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I4(ck_po_stg2_f_en), .O(ck_po_stg2_f_en_i_1_n_0)); LUT5 #( .INIT(32'hD7BF0020)) ck_po_stg2_f_indec_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I4(ck_po_stg2_f_indec), .O(ck_po_stg2_f_indec_i_1_n_0)); LUT4 #( .INIT(16'hEAAA)) cnt_dllk_zqinit_done_r_i_1 (.I0(cnt_dllk_zqinit_done_r), .I1(cnt_dllk_zqinit_r_reg__0[6]), .I2(u_ddr_phy_init_n_496), .I3(cnt_dllk_zqinit_r_reg__0[7]), .O(cnt_dllk_zqinit_done_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000BA8A8A8A)) cnt_init_af_done_r_i_1 (.I0(cnt_init_af_done_r), .I1(mem_init_done_r), .I2(u_ddr_phy_init_n_110), .I3(cnt_init_af_r[1]), .I4(cnt_init_af_r[0]), .I5(u_ddr_phy_init_n_115), .O(cnt_init_af_done_r_i_1_n_0)); LUT6 #( .INIT(64'h000000000000E222)) cnt_init_mr_done_r_i_1 (.I0(cnt_init_mr_done_r), .I1(temp_lmr_done), .I2(cnt_init_mr_r[0]), .I3(cnt_init_mr_r[1]), .I4(cnt_init_mr_r1), .I5(u_ddr_phy_init_n_115), .O(cnt_init_mr_done_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000AAAABAAA)) cnt_pwron_cke_done_r_i_1 (.I0(cnt_pwron_cke_done_r), .I1(u_ddr_phy_init_n_490), .I2(cnt_pwron_r_reg__0[7]), .I3(cnt_pwron_r_reg__0[1]), .I4(cnt_pwron_r_reg__0[0]), .I5(cnt_pwron_reset_done_r0), .O(cnt_pwron_cke_done_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000FFFF0040)) cnt_pwron_reset_done_r_i_1 (.I0(cnt_pwron_r_reg__0[7]), .I1(cnt_pwron_r_reg__0[5]), .I2(cnt_pwron_r_reg__0[0]), .I3(u_ddr_phy_init_n_485), .I4(cnt_pwron_reset_done_r), .I5(cnt_pwron_reset_done_r0), .O(cnt_pwron_reset_done_r_i_1_n_0)); LUT5 #( .INIT(32'hBAAAAAAA)) cnt_txpr_done_r_i_1 (.I0(cnt_txpr_done_r), .I1(u_ddr_phy_init_n_500), .I2(cnt_txpr_r_reg__0[2]), .I3(cnt_txpr_r_reg__0[0]), .I4(cnt_txpr_r_reg__0[1]), .O(cnt_txpr_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFB00000020)) complex_init_pi_dec_done_r_i_1 (.I0(prbs_state_r[4]), .I1(prbs_state_r[3]), .I2(prbs_state_r[0]), .I3(prbs_state_r[2]), .I4(prbs_state_r[1]), .I5(complex_init_pi_dec_done), .O(complex_init_pi_dec_done_r_i_1_n_0)); LUT6 #( .INIT(64'h4474FFFF44740000)) complex_pi_incdec_done_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ), .I1(prbs_state_r[0]), .I2(cnt_wait_state), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ), .I5(complex_pi_incdec_done), .O(complex_pi_incdec_done_i_1_n_0)); LUT4 #( .INIT(16'h00CE)) ddr2_pre_flag_r_i_1 (.I0(u_ddr_phy_init_n_29), .I1(temp_lmr_done), .I2(u_ddr_phy_init_n_479), .I3(u_ddr_phy_init_n_115), .O(ddr2_pre_flag_r_i_1_n_0)); LUT6 #( .INIT(64'h00000000FFFF70F0)) ddr2_refresh_flag_r_i_1 (.I0(u_ddr_phy_init_n_480), .I1(cnt_cmd_done_r), .I2(ddr2_refresh_flag_r), .I3(cnt_init_mr_done_r), .I4(cnt_init_mr_r1), .I5(u_ddr_phy_init_n_115), .O(ddr2_refresh_flag_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair727" *) LUT3 #( .INIT(8'hAC)) \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/d_out (.I0(app_zq_r_reg), .I1(\rd_ptr_reg[3]_0 [3]), .I2(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [3])); ddr3_if_mig_7series_v4_0_ddr_phy_prbs_rdlvl \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl (.A(A), .\A[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .\A[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .\A[1]_1 (\A[1]_0 ), .\A[1]_10 (\A[1]_9 ), .\A[1]_11 (\A[1]_10 ), .\A[1]_12 (\A[1]_11 ), .\A[1]_13 (\A[1]_12 ), .\A[1]_14 (\A[1]_13 ), .\A[1]_15 (\A[1]_14 ), .\A[1]_16 (\A[1]_15 ), .\A[1]_17 (\A[1]_16 ), .\A[1]_18 (\A[1]_17 ), .\A[1]_19 (\A[1]_18 ), .\A[1]_2 (\A[1]_1 ), .\A[1]_20 (\A[1]_19 ), .\A[1]_21 (\A[1]_20 ), .\A[1]_22 (\A[1]_21 ), .\A[1]_23 (\A[1]_22 ), .\A[1]_24 (\A[1]_23 ), .\A[1]_25 (\A[1]_24 ), .\A[1]_26 (\A[1]_25 ), .\A[1]_27 (\A[1]_26 ), .\A[1]_28 (\A[1]_27 ), .\A[1]_29 (\A[1]_28 ), .\A[1]_3 (\A[1]_2 ), .\A[1]_30 (\A[1]_29 ), .\A[1]_31 (\A[1]_30 ), .\A[1]_32 (\A[1]_31 ), .\A[1]_33 (\A[1]_32 ), .\A[1]_34 (\A[1]_33 ), .\A[1]_35 (\A[1]_34 ), .\A[1]_36 (\A[1]_35 ), .\A[1]_37 (\A[1]_36 ), .\A[1]_38 (\A[1]_37 ), .\A[1]_39 (\A[1]_38 ), .\A[1]_4 (\A[1]_3 ), .\A[1]_40 (\A[1]_39 ), .\A[1]_41 (\A[1]_40 ), .\A[1]_42 (\A[1]_41 ), .\A[1]_43 (\A[1]_42 ), .\A[1]_44 (\A[1]_43 ), .\A[1]_45 (\A[1]_44 ), .\A[1]_46 (\A[1]_45 ), .\A[1]_47 (\A[1]_46 ), .\A[1]_48 (\A[1]_47 ), .\A[1]_49 (\A[1]_48 ), .\A[1]_5 (\A[1]_4 ), .\A[1]_50 (\A[1]_49 ), .\A[1]_51 (\A[1]_50 ), .\A[1]_52 (\A[1]_51 ), .\A[1]_53 (\A[1]_52 ), .\A[1]_54 (\A[1]_53 ), .\A[1]_55 (\A[1]_54 ), .\A[1]_56 (\A[1]_55 ), .\A[1]_57 (\A[1]_56 ), .\A[1]_58 (\A[1]_57 ), .\A[1]_59 (\A[1]_58 ), .\A[1]_6 (\A[1]_5 ), .\A[1]_60 (\A[1]_59 ), .\A[1]_61 (\A[1]_60 ), .\A[1]_62 (\A[1]_61 ), .\A[1]_63 (\A[1]_62 ), .\A[1]_64 (\A[1]_63 ), .\A[1]_7 (\A[1]_6 ), .\A[1]_8 (\A[1]_7 ), .\A[1]_9 (\A[1]_8 ), .\A[2]__2 (\A[2]__2_0 ), .CLK(CLK), .D(left_edge_updated), .E(samples_cnt_r), .Q(prbs_state_r), .bit_cnt(bit_cnt), .\calib_sel_reg[3] (\po_rdval_cnt_reg[8] [2]), .\calib_sel_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ), .\calib_sel_reg[3]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ), .\calib_sel_reg[3]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ), .cnt_wait_state(cnt_wait_state), .compare_err_latch_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ), .complex_act_start(complex_act_start), .complex_init_pi_dec_done(complex_init_pi_dec_done), .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr), .complex_oclkdelay_calib_done_r1_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .complex_pi_incdec_done(complex_pi_incdec_done), .complex_pi_incdec_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ), .complex_pi_incdec_done_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .\dec_cnt_reg[0]_0 (fine_dly_error_i_1_n_0), .\dout_o_reg[0] (u_ddr_prbs_gen_n_114), .\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_115), .\dout_o_reg[0]_1 (u_ddr_prbs_gen_n_116), .\dout_o_reg[0]_2 (u_ddr_prbs_gen_n_117), .\dout_o_reg[0]_3 (u_ddr_prbs_gen_n_118), .\dout_o_reg[0]_4 (u_ddr_prbs_gen_n_119), .\dout_o_reg[0]_5 (u_ddr_prbs_gen_n_120), .\dout_o_reg[0]_6 (u_ddr_prbs_gen_n_121), .\dout_o_reg[1] (u_ddr_prbs_gen_n_106), .\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_107), .\dout_o_reg[1]_1 (u_ddr_prbs_gen_n_108), .\dout_o_reg[1]_2 (u_ddr_prbs_gen_n_109), .\dout_o_reg[1]_3 (u_ddr_prbs_gen_n_110), .\dout_o_reg[1]_4 (u_ddr_prbs_gen_n_111), .\dout_o_reg[1]_5 (u_ddr_prbs_gen_n_112), .\dout_o_reg[1]_6 (u_ddr_prbs_gen_n_113), .\dout_o_reg[2] (u_ddr_prbs_gen_n_98), .\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_99), .\dout_o_reg[2]_1 (u_ddr_prbs_gen_n_100), .\dout_o_reg[2]_2 (u_ddr_prbs_gen_n_101), .\dout_o_reg[2]_3 (u_ddr_prbs_gen_n_102), .\dout_o_reg[2]_4 (u_ddr_prbs_gen_n_103), .\dout_o_reg[2]_5 (u_ddr_prbs_gen_n_104), .\dout_o_reg[2]_6 (u_ddr_prbs_gen_n_105), .\dout_o_reg[3] (u_ddr_prbs_gen_n_90), .\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_91), .\dout_o_reg[3]_1 (u_ddr_prbs_gen_n_92), .\dout_o_reg[3]_2 (u_ddr_prbs_gen_n_93), .\dout_o_reg[3]_3 (u_ddr_prbs_gen_n_94), .\dout_o_reg[3]_4 (u_ddr_prbs_gen_n_95), .\dout_o_reg[3]_5 (u_ddr_prbs_gen_n_96), .\dout_o_reg[3]_6 (u_ddr_prbs_gen_n_97), .\dout_o_reg[4] (u_ddr_prbs_gen_n_82), .\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_83), .\dout_o_reg[4]_1 (u_ddr_prbs_gen_n_84), .\dout_o_reg[4]_2 (u_ddr_prbs_gen_n_85), .\dout_o_reg[4]_3 (u_ddr_prbs_gen_n_86), .\dout_o_reg[4]_4 (u_ddr_prbs_gen_n_87), .\dout_o_reg[4]_5 (u_ddr_prbs_gen_n_88), .\dout_o_reg[4]_6 (u_ddr_prbs_gen_n_89), .\dout_o_reg[5] (u_ddr_prbs_gen_n_74), .\dout_o_reg[5]_0 (u_ddr_prbs_gen_n_75), .\dout_o_reg[5]_1 (u_ddr_prbs_gen_n_76), .\dout_o_reg[5]_2 (u_ddr_prbs_gen_n_77), .\dout_o_reg[5]_3 (u_ddr_prbs_gen_n_78), .\dout_o_reg[5]_4 (u_ddr_prbs_gen_n_79), .\dout_o_reg[5]_5 (u_ddr_prbs_gen_n_80), .\dout_o_reg[5]_6 (u_ddr_prbs_gen_n_81), .\dout_o_reg[6] (u_ddr_prbs_gen_n_66), .\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_67), .\dout_o_reg[6]_1 (u_ddr_prbs_gen_n_68), .\dout_o_reg[6]_2 (u_ddr_prbs_gen_n_69), .\dout_o_reg[6]_3 (u_ddr_prbs_gen_n_70), .\dout_o_reg[6]_4 (u_ddr_prbs_gen_n_71), .\dout_o_reg[6]_5 (u_ddr_prbs_gen_n_72), .\dout_o_reg[6]_6 (u_ddr_prbs_gen_n_73), .\dout_o_reg[7] (u_ddr_prbs_gen_n_58), .\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_59), .\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_60), .\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_61), .\dout_o_reg[7]_3 (u_ddr_prbs_gen_n_62), .\dout_o_reg[7]_4 (u_ddr_prbs_gen_n_63), .\dout_o_reg[7]_5 (u_ddr_prbs_gen_n_64), .\dout_o_reg[7]_6 (u_ddr_prbs_gen_n_65), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .\fine_delay_mod_reg[20] (\fine_delay_mod_reg[20] ), .\fine_delay_mod_reg[26] (\fine_delay_mod_reg[26] ), .\fine_delay_mod_reg[5] (\fine_delay_mod_reg[5] ), .fine_delay_sel_r_reg(fine_delay_sel_r_reg), .fine_delay_sel_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ), .fine_delay_sel_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ), .fine_dly_error_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ), .fine_dly_error_reg_1(prbs_rdlvl_done_i_1_n_0), .\genblk8[0].left_edge_found_pb_reg[0]_0 (\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ), .\genblk8[0].left_edge_updated_reg[0]_0 (\genblk8[0].left_edge_updated[0]_i_1_n_0 ), .\genblk8[0].left_loss_pb_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ), .\genblk8[0].left_loss_pb_reg[0]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .\genblk8[0].right_edge_found_pb_reg[0]_0 (\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ), .\genblk8[0].right_edge_pb_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ), .\genblk8[0].right_edge_pb_reg[0]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ), .\genblk8[1].left_edge_found_pb_reg[1]_0 (\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ), .\genblk8[1].left_edge_updated_reg[1]_0 (\genblk8[1].left_edge_updated[1]_i_1_n_0 ), .\genblk8[1].left_loss_pb_reg[6]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ), .\genblk8[1].right_edge_found_pb_reg[1]_0 (\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ), .\genblk8[1].right_edge_pb_reg[6]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ), .\genblk8[2].left_edge_found_pb_reg[2]_0 (\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ), .\genblk8[2].left_edge_updated_reg[2]_0 (\genblk8[2].left_edge_updated[2]_i_1_n_0 ), .\genblk8[2].left_loss_pb_reg[12]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ), .\genblk8[2].right_edge_found_pb_reg[2]_0 (\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ), .\genblk8[2].right_edge_pb_reg[12]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ), .\genblk8[2].right_edge_pb_reg[12]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ), .\genblk8[2].right_edge_pb_reg[12]_2 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .\genblk8[3].left_edge_found_pb_reg[3]_0 (\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ), .\genblk8[3].left_edge_updated_reg[3]_0 (\genblk8[3].left_edge_updated[3]_i_1_n_0 ), .\genblk8[3].left_loss_pb_reg[18]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ), .\genblk8[3].right_edge_found_pb_reg[3]_0 (\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ), .\genblk8[3].right_edge_pb_reg[18]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ), .\genblk8[4].left_edge_found_pb_reg[4]_0 (\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ), .\genblk8[4].left_edge_updated_reg[4]_0 (\genblk8[4].left_edge_updated[4]_i_1_n_0 ), .\genblk8[4].left_loss_pb_reg[24]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ), .\genblk8[4].right_edge_found_pb_reg[4]_0 (\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ), .\genblk8[4].right_edge_pb_reg[24]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ), .\genblk8[5].left_edge_found_pb_reg[5]_0 (\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ), .\genblk8[5].left_edge_updated_reg[5]_0 (\genblk8[5].left_edge_updated[5]_i_1_n_0 ), .\genblk8[5].left_loss_pb_reg[30]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ), .\genblk8[5].right_edge_found_pb_reg[5]_0 (\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ), .\genblk8[5].right_edge_pb_reg[30]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ), .\genblk8[5].right_edge_pb_reg[30]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ), .\genblk8[5].right_gain_pb_reg[30]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .\genblk8[6].left_edge_found_pb_reg[6]_0 (\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ), .\genblk8[6].left_edge_updated_reg[6]_0 (\genblk8[6].left_edge_updated[6]_i_1_n_0 ), .\genblk8[6].left_loss_pb_reg[36]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ), .\genblk8[6].right_edge_found_pb_reg[6]_0 (\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ), .\genblk8[6].right_edge_pb_reg[36]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ), .\genblk8[7].left_edge_found_pb_reg[7]_0 (\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ), .\genblk8[7].left_edge_updated_reg[7]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .\genblk8[7].left_edge_updated_reg[7]_1 (\genblk8[7].left_edge_updated[7]_i_1_n_0 ), .\genblk8[7].left_loss_pb_reg[42]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ), .\genblk8[7].right_edge_found_pb_reg[7]_0 (\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ), .\genblk8[7].right_edge_pb_reg[42]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ), .\genblk8[7].right_edge_pb_reg[42]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .\genblk9[0].fine_delay_incdec_pb_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ), .\genblk9[1].fine_delay_incdec_pb_reg[1]_0 (\genblk9[1].fine_delay_incdec_pb_reg[1] ), .\genblk9[2].fine_delay_incdec_pb_reg[2]_0 (\genblk9[2].fine_delay_incdec_pb_reg[2] ), .\genblk9[3].fine_delay_incdec_pb_reg[3]_0 (\genblk9[3].fine_delay_incdec_pb_reg[3] ), .\genblk9[5].fine_delay_incdec_pb_reg[5]_0 (\genblk9[5].fine_delay_incdec_pb_reg[5] ), .\genblk9[6].fine_delay_incdec_pb_reg[6]_0 (\genblk9[6].fine_delay_incdec_pb_reg[6] ), .\genblk9[7].fine_delay_incdec_pb_reg[7]_0 (\genblk9[7].fine_delay_incdec_pb_reg[7] ), .\init_state_r_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ), .\init_state_r_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ), .\init_state_r_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ), .\init_state_r_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ), .\largest_left_edge_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ), .\match_flag_or_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ), .new_cnt_dqs_r(new_cnt_dqs_r), .new_cnt_dqs_r_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ), .new_cnt_dqs_r_reg_1(prbs_dqs_tap_limit_r_i_1_n_0), .no_err_win_detected_latch_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ), .no_err_win_detected_latch_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ), .no_err_win_detected_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ), .no_err_win_detected_reg_1(right_edge_found_i_1_n_0), .\num_refresh_reg[1] (u_ddr_phy_init_n_117), .num_samples_done_ind_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ), .num_samples_done_r(num_samples_done_r), .ocal_last_byte_done(ocal_last_byte_done), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .\oclkdelay_ref_cnt_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ), .\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116), .p_103_out(p_103_out), .p_106_out(p_106_out), .p_119_out(p_119_out), .p_122_out(p_122_out), .p_127_out(p_127_out), .p_130_out(p_130_out), .p_143_out(p_143_out), .p_146_out(p_146_out), .p_154_out(p_154_out), .p_95_out(p_95_out), .p_98_out(p_98_out), .\pi_counter_read_val_reg[5] ({\pi_counter_read_val_reg[5] [5],\pi_counter_read_val_reg[5] [3],\pi_counter_read_val_reg[5] [1:0]}), .pi_en_stg2_f_timing_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ), .\prbs_dec_tap_cnt_reg[1]_0 ({dec_cnt_reg[5],dec_cnt_reg[0]}), .\prbs_dqs_cnt_r_reg[0]_0 (\prbs_dqs_cnt_r[1]_i_1_n_0 ), .\prbs_dqs_cnt_r_reg[0]_1 (\prbs_dqs_cnt_r[0]_i_1_n_0 ), .\prbs_dqs_cnt_r_reg[0]_2 (\prbs_dqs_cnt_r[2]_i_1_n_0 ), .\prbs_dqs_cnt_r_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .\prbs_dqs_cnt_r_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ), .prbs_found_1st_edge_r_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ), .prbs_found_1st_edge_r_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ), .prbs_last_byte_done(prbs_last_byte_done), .prbs_last_byte_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ), .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en), .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec), .prbs_prech_req_r(prbs_prech_req_r), .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0), .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1), .prbs_rdlvl_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ), .prbs_rdlvl_done_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ), .prbs_rdlvl_start_r(prbs_rdlvl_start_r), .prbs_rdlvl_start_reg(prbs_rdlvl_start_r_reg), .prbs_rdlvl_start_reg_0(u_ddr_phy_init_n_127), .prbs_state_r178_out(prbs_state_r178_out), .\prbs_state_r_reg[0]_0 (fine_delay_sel_i_1_n_0), .\prbs_state_r_reg[0]_1 (prbs_tap_inc_r_i_1_n_0), .\prbs_state_r_reg[0]_2 (prbs_tap_en_r_i_1_n_0), .\prbs_state_r_reg[0]_3 (prbs_last_byte_done_i_1_n_0), .\prbs_state_r_reg[0]_4 (complex_pi_incdec_done_i_1_n_0), .\prbs_state_r_reg[3]_0 (prbs_found_1st_edge_r_i_1_n_0), .\prbs_state_r_reg[3]_1 (no_err_win_detected_latch_i_1_n_0), .\prbs_state_r_reg[4]_0 (new_cnt_dqs_r_i_1_n_0), .\prbs_state_r_reg[4]_1 (num_samples_done_ind_i_1_n_0), .\prbs_state_r_reg[4]_2 (reset_rd_addr_i_1_n_0), .\prbs_state_r_reg[4]_3 (complex_init_pi_dec_done_r_i_1_n_0), .prbs_tap_en_r(prbs_tap_en_r), .prbs_tap_en_r_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ), .prbs_tap_inc_r(prbs_tap_inc_r), .prbs_tap_inc_r_reg_0(pi_stg2_f_incdec_timing_i_1_n_0), .prech_done(prech_done), .prech_done_reg(prbs_prech_req_r_i_1_n_0), .prech_req_r_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ), .\rd_victim_sel_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ), .\rd_victim_sel_reg[2]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ), .\rd_victim_sel_reg[2]_2 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ), .\rd_victim_sel_reg[2]_3 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ), .\rdlvl_cpt_tap_cnt_reg[5]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ), .\rdlvl_cpt_tap_cnt_reg[5]_1 ({\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }), .rdlvl_last_byte_done(rdlvl_last_byte_done), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_start_int(rdlvl_stg1_start_int), .reset_rd_addr(reset_rd_addr), .reset_rd_addr0(reset_rd_addr0), .right_edge_found(right_edge_found), .right_edge_found_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ), .right_edge_found_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ), .right_gain_pb(right_gain_pb), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\stage_cnt_reg[1]_0 (\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ), .\stg1_wr_rd_cnt_reg[3] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .wrlvl_final_mux(wrlvl_final_mux)); ddr3_if_mig_7series_v4_0_ddr_phy_rdlvl \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl (.CLK(CLK), .COUNTERLOADVAL(COUNTERLOADVAL), .D({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }), .E(u_ddr_phy_init_n_465), .\FSM_sequential_cal1_state_r_reg[1]_0 (rdlvl_pi_incdec_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[2]_0 (idel_adj_inc_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[3]_0 (mpr_dec_cpt_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_0 (idel_pat_detect_valid_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_1 (mpr_last_byte_done_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_2 (mpr_rank_done_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_3 (rdlvl_rank_done_r_i_1_n_0), .\FSM_sequential_cal1_state_r_reg[4]_4 (rdlvl_last_byte_done_int_i_1_n_0), .Q(calib_zero_inputs__0), .SR(SR), .cal1_cnt_cpt_r1(cal1_cnt_cpt_r1), .cal1_dq_idel_ce_reg_0(u_ddr_phy_wrcal_n_89), .cal1_state_r1535_out(cal1_state_r1535_out), .cal1_wait_r(cal1_wait_r), .calib_in_common(calib_in_common), .\calib_sel_reg[3] (\po_rdval_cnt_reg[8] ), .\calib_sel_reg[3]_0 ({\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }), .cmd_delay_start0(cmd_delay_start0), .\cnt_idel_dec_cpt_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ), .cnt_init_af_done_r(cnt_init_af_done_r), .complex_ocal_ref_req(complex_ocal_ref_req), .detect_edge_done_r(detect_edge_done_r), .\dout_o_reg[6] (u_ddr_prbs_gen_n_70), .\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_66), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .dqs_found_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ), .dqs_found_prech_req(dqs_found_prech_req), .dqs_po_dec_done(dqs_po_dec_done), .dqs_po_dec_done_r2(dqs_po_dec_done_r2), .first_wrcal_pat_r(first_wrcal_pat_r), .found_edge_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ), .found_edge_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ), .found_edge_r_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ), .found_edge_r_reg_3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ), .found_edge_r_reg_4(found_first_edge_r_i_1_n_0), .found_first_edge_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ), .found_stable_eye_last_r(found_stable_eye_last_r), .found_stable_eye_last_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ), .found_stable_eye_last_r_reg_1(found_second_edge_r_i_1_n_0), .found_stable_eye_r_reg_0(found_stable_eye_last_r_i_1_n_0), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ), .\gen_byte_sel_div1.calib_in_common_reg (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\phaser_in_gen.phaser_in_i_12_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\phaser_in_gen.phaser_in_i_12__0_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\phaser_in_gen.phaser_in_i_12__1_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\phaser_in_gen.phaser_in_i_12__2_n_0 ), .\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ), .\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 (\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ), .\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 (\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ), .\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ), .\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ), .\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 (\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ), .\gen_track_left_edge[0].pb_found_stable_eye_r_reg (\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ), .\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ), .\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ), .\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 (\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ), .\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ), .\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 (\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ), .\gen_track_left_edge[1].pb_found_stable_eye_r_reg (\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ), .\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 (\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ), .\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ), .\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 (\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ), .\gen_track_left_edge[2].pb_found_stable_eye_r_reg (\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ), .\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 (\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ), .\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ), .\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 (\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ), .\gen_track_left_edge[3].pb_found_stable_eye_r_reg (\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ), .\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 (\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ), .\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ), .\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ), .\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 (\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ), .\gen_track_left_edge[4].pb_found_stable_eye_r_reg (\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ), .\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 (\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ), .\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ), .\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 (\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ), .\gen_track_left_edge[5].pb_found_stable_eye_r_reg (\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ), .\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 (\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ), .\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ), .\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ), .\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 (\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ), .\gen_track_left_edge[6].pb_found_stable_eye_r_reg (\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ), .\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 (\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ), .\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ), .\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ), .\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 (\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ), .\gen_track_left_edge[7].pb_found_stable_eye_r_reg (\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ), .\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ), .\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .idel_adj_inc_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ), .idel_adj_inc_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ), .idel_adj_inc_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ), .\idel_dec_cnt_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ), .idelay_ce_int(idelay_ce_int), .idelay_inc_int(idelay_inc_int), .\init_state_r_reg[0] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ), .\init_state_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ), .\init_state_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ), .\init_state_r_reg[0]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ), .\init_state_r_reg[0]_3 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ), .\init_state_r_reg[0]_4 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ), .\init_state_r_reg[1] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ), .\init_state_r_reg[1]_0 ({u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}), .\init_state_r_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ), .\init_state_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ), .\init_state_r_reg[2]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ), .\init_state_r_reg[2]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ), .\init_state_r_reg[3] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ), .\init_state_r_reg[3]_0 (u_ddr_phy_init_n_111), .\init_state_r_reg[4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ), .\init_state_r_reg[5] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ), .\init_state_r_reg[5]_0 (u_ddr_phy_init_n_474), .mem_init_done_r(mem_init_done_r), .mpr_dec_cpt_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ), .mpr_dec_cpt_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ), .mpr_last_byte_done(mpr_last_byte_done), .mpr_last_byte_done_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ), .mpr_rank_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ), .mpr_rank_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ), .mpr_rd_rise0_prev_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ), .mpr_rd_rise0_prev_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ), .mpr_rdlvl_done_r1_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .mpr_rdlvl_done_r_reg_0(mpr_rdlvl_done_r_i_1_n_0), .mpr_rdlvl_done_r_reg_1(rdlvl_stg1_done_int_i_1_n_0), .mpr_rdlvl_start_r(mpr_rdlvl_start_r), .mpr_rdlvl_start_reg(u_ddr_phy_init_n_464), .mpr_rnk_done(mpr_rnk_done), .mpr_valid_r1_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ), .mpr_valid_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ), .\num_refresh_reg[1] (u_ddr_phy_init_n_117), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116), .out({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 }), .p_0_in(p_0_in), .p_0_in102_in(p_0_in102_in), .p_0_in10_in(p_0_in10_in), .p_0_in13_in(p_0_in13_in), .p_0_in16_in(p_0_in16_in), .p_0_in1_in(p_0_in1_in), .p_0_in4_in(p_0_in4_in), .p_0_in7_in(p_0_in7_in), .p_0_in84_in(p_0_in84_in), .p_0_in87_in(p_0_in87_in), .p_0_in90_in(p_0_in90_in), .p_0_in93_in(p_0_in93_in), .p_0_in96_in(p_0_in96_in), .p_0_in99_in(p_0_in99_in), .pb_detect_edge_done_r(pb_detect_edge_done_r), .pb_found_stable_eye_r52_out(pb_found_stable_eye_r52_out), .pb_found_stable_eye_r56_out(pb_found_stable_eye_r56_out), .pb_found_stable_eye_r60_out(pb_found_stable_eye_r60_out), .pb_found_stable_eye_r64_out(pb_found_stable_eye_r64_out), .pb_found_stable_eye_r68_out(pb_found_stable_eye_r68_out), .pb_found_stable_eye_r72_out(pb_found_stable_eye_r72_out), .pb_found_stable_eye_r76_out(pb_found_stable_eye_r76_out), .phy_rddata_en_1(phy_rddata_en_1), .pi_cnt_dec_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ), .pi_cnt_dec_reg_1(pi_cnt_dec_reg), .\pi_counter_read_val_reg[5] ({\pi_counter_read_val_reg[5] [5:4],\pi_counter_read_val_reg[5] [2:0]}), .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0]_0 ), .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_1 ), .\pi_dqs_found_lanes_r1_reg[0]_1 (\pi_dqs_found_lanes_r1_reg[0]_2 ), .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[1]_0 ), .\pi_dqs_found_lanes_r1_reg[1]_0 (\pi_dqs_found_lanes_r1_reg[1]_1 ), .\pi_dqs_found_lanes_r1_reg[1]_1 (\pi_dqs_found_lanes_r1_reg[1]_2 ), .\pi_dqs_found_lanes_r1_reg[1]_2 (\pi_dqs_found_lanes_r1_reg[1]_3 ), .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2]_0 ), .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_1 ), .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_2 ), .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_3 ), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3]_0 ), .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_1 ), .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_2 ), .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_3 ), .pi_en_stg2_f_timing_reg_0(pi_en_stg2_f_timing_reg), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .\pi_rdval_cnt_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ), .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt), .\pi_stg2_reg_l_timing_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ), .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_85), .\po_stg2_wrcal_cnt_reg[1] (\idelay_tap_cnt_r_reg[0][3][0] [1]), .\po_stg2_wrcal_cnt_reg[2] (u_ddr_phy_wrcal_n_107), .\prbs_dqs_cnt_r_reg[2] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ), .prbs_last_byte_done_r(prbs_last_byte_done_r), .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en), .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prbs_rdlvl_done_reg_rep_0(u_ddr_phy_init_n_497), .prbs_rdlvl_done_reg_rep_1(u_ddr_phy_wrcal_n_94), .prbs_rdlvl_prech_req_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ), .prech_done(prech_done), .prech_req(prech_req), .\rd_mux_sel_r_reg[1]_0 (\rd_mux_sel_r_reg[1] ), .\rd_mux_sel_r_reg[1]_1 (\rd_mux_sel_r_reg[1]_0 ), .\rd_mux_sel_r_reg[1]_10 (\rd_mux_sel_r_reg[1]_9 ), .\rd_mux_sel_r_reg[1]_11 (\rd_mux_sel_r_reg[1]_10 ), .\rd_mux_sel_r_reg[1]_12 (\rd_mux_sel_r_reg[1]_11 ), .\rd_mux_sel_r_reg[1]_13 (\rd_mux_sel_r_reg[1]_12 ), .\rd_mux_sel_r_reg[1]_14 (\rd_mux_sel_r_reg[1]_13 ), .\rd_mux_sel_r_reg[1]_15 (\rd_mux_sel_r_reg[1]_14 ), .\rd_mux_sel_r_reg[1]_16 (\rd_mux_sel_r_reg[1]_15 ), .\rd_mux_sel_r_reg[1]_17 (\rd_mux_sel_r_reg[1]_16 ), .\rd_mux_sel_r_reg[1]_18 (\rd_mux_sel_r_reg[1]_17 ), .\rd_mux_sel_r_reg[1]_19 (\rd_mux_sel_r_reg[1]_18 ), .\rd_mux_sel_r_reg[1]_2 (\rd_mux_sel_r_reg[1]_1 ), .\rd_mux_sel_r_reg[1]_20 (\rd_mux_sel_r_reg[1]_19 ), .\rd_mux_sel_r_reg[1]_21 (\rd_mux_sel_r_reg[1]_20 ), .\rd_mux_sel_r_reg[1]_22 (\rd_mux_sel_r_reg[1]_21 ), .\rd_mux_sel_r_reg[1]_23 (\rd_mux_sel_r_reg[1]_22 ), .\rd_mux_sel_r_reg[1]_24 (\rd_mux_sel_r_reg[1]_23 ), .\rd_mux_sel_r_reg[1]_25 (\rd_mux_sel_r_reg[1]_24 ), .\rd_mux_sel_r_reg[1]_26 (\rd_mux_sel_r_reg[1]_25 ), .\rd_mux_sel_r_reg[1]_27 (\rd_mux_sel_r_reg[1]_26 ), .\rd_mux_sel_r_reg[1]_28 (\rd_mux_sel_r_reg[1]_27 ), .\rd_mux_sel_r_reg[1]_29 (\rd_mux_sel_r_reg[1]_28 ), .\rd_mux_sel_r_reg[1]_3 (\rd_mux_sel_r_reg[1]_2 ), .\rd_mux_sel_r_reg[1]_30 (\rd_mux_sel_r_reg[1]_29 ), .\rd_mux_sel_r_reg[1]_31 (\rd_mux_sel_r_reg[1]_30 ), .\rd_mux_sel_r_reg[1]_32 (\rd_mux_sel_r_reg[1]_31 ), .\rd_mux_sel_r_reg[1]_33 (\rd_mux_sel_r_reg[1]_32 ), .\rd_mux_sel_r_reg[1]_34 (\rd_mux_sel_r_reg[1]_33 ), .\rd_mux_sel_r_reg[1]_35 (\rd_mux_sel_r_reg[1]_34 ), .\rd_mux_sel_r_reg[1]_36 (\rd_mux_sel_r_reg[1]_35 ), .\rd_mux_sel_r_reg[1]_37 (\rd_mux_sel_r_reg[1]_36 ), .\rd_mux_sel_r_reg[1]_38 (\rd_mux_sel_r_reg[1]_37 ), .\rd_mux_sel_r_reg[1]_39 (\rd_mux_sel_r_reg[1]_38 ), .\rd_mux_sel_r_reg[1]_4 (\rd_mux_sel_r_reg[1]_3 ), .\rd_mux_sel_r_reg[1]_40 (\rd_mux_sel_r_reg[1]_39 ), .\rd_mux_sel_r_reg[1]_41 (\rd_mux_sel_r_reg[1]_40 ), .\rd_mux_sel_r_reg[1]_42 (\rd_mux_sel_r_reg[1]_41 ), .\rd_mux_sel_r_reg[1]_43 (\rd_mux_sel_r_reg[1]_42 ), .\rd_mux_sel_r_reg[1]_44 (\rd_mux_sel_r_reg[1]_43 ), .\rd_mux_sel_r_reg[1]_45 (\rd_mux_sel_r_reg[1]_44 ), .\rd_mux_sel_r_reg[1]_46 (\rd_mux_sel_r_reg[1]_45 ), .\rd_mux_sel_r_reg[1]_47 (\rd_mux_sel_r_reg[1]_46 ), .\rd_mux_sel_r_reg[1]_48 (\rd_mux_sel_r_reg[1]_47 ), .\rd_mux_sel_r_reg[1]_49 (\rd_mux_sel_r_reg[1]_48 ), .\rd_mux_sel_r_reg[1]_5 (\rd_mux_sel_r_reg[1]_4 ), .\rd_mux_sel_r_reg[1]_50 (\rd_mux_sel_r_reg[1]_49 ), .\rd_mux_sel_r_reg[1]_51 (\rd_mux_sel_r_reg[1]_50 ), .\rd_mux_sel_r_reg[1]_52 (\rd_mux_sel_r_reg[1]_51 ), .\rd_mux_sel_r_reg[1]_53 (\rd_mux_sel_r_reg[1]_52 ), .\rd_mux_sel_r_reg[1]_54 (\rd_mux_sel_r_reg[1]_53 ), .\rd_mux_sel_r_reg[1]_55 (\rd_mux_sel_r_reg[1]_54 ), .\rd_mux_sel_r_reg[1]_56 (\rd_mux_sel_r_reg[1]_55 ), .\rd_mux_sel_r_reg[1]_57 (\rd_mux_sel_r_reg[1]_56 ), .\rd_mux_sel_r_reg[1]_58 (\rd_mux_sel_r_reg[1]_57 ), .\rd_mux_sel_r_reg[1]_59 (\rd_mux_sel_r_reg[1]_58 ), .\rd_mux_sel_r_reg[1]_6 (\rd_mux_sel_r_reg[1]_5 ), .\rd_mux_sel_r_reg[1]_60 (\rd_mux_sel_r_reg[1]_59 ), .\rd_mux_sel_r_reg[1]_61 (\rd_mux_sel_r_reg[1]_60 ), .\rd_mux_sel_r_reg[1]_62 (\rd_mux_sel_r_reg[1]_61 ), .\rd_mux_sel_r_reg[1]_63 (\rd_mux_sel_r_reg[1]_62 ), .\rd_mux_sel_r_reg[1]_7 (\rd_mux_sel_r_reg[1]_6 ), .\rd_mux_sel_r_reg[1]_8 (\rd_mux_sel_r_reg[1]_7 ), .\rd_mux_sel_r_reg[1]_9 (\rd_mux_sel_r_reg[1]_8 ), .\rdlvl_cpt_tap_cnt_reg[1] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ), .\rdlvl_cpt_tap_cnt_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ), .\rdlvl_cpt_tap_cnt_reg[4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ), .\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ), .rdlvl_last_byte_done(rdlvl_last_byte_done), .rdlvl_pi_incdec(rdlvl_pi_incdec), .rdlvl_pi_incdec_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ), .rdlvl_pi_incdec_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ), .rdlvl_prech_req(rdlvl_prech_req), .rdlvl_rank_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ), .rdlvl_stg1_done_int(rdlvl_stg1_done_int), .rdlvl_stg1_done_r1_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done), .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33), .rdlvl_stg1_start_reg_0(cnt_shift_r0), .\regl_dqs_cnt_r_reg[2]_0 (regl_dqs_cnt), .\regl_dqs_cnt_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ), .\regl_dqs_cnt_reg[2]_0 (pi_stg2_load_timing_i_1_n_0), .\right_edge_taps_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ), .\right_edge_taps_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ), .\right_edge_taps_r_reg[0]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .samp_cnt_done_r_reg_0(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ), .samp_cnt_done_r_reg_1(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ), .samp_cnt_done_r_reg_2(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ), .samp_cnt_done_r_reg_3(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ), .samp_cnt_done_r_reg_4(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ), .samp_cnt_done_r_reg_5(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ), .samp_cnt_done_r_reg_6(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg_0(samp_edge_cnt0_en_r_reg), .\second_edge_taps_r_reg[5]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ), .sr_valid_r108_out(sr_valid_r108_out), .sr_valid_r1_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ), .stg1_wr_done(stg1_wr_done), .\stg1_wr_rd_cnt_reg[3] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ), .store_sr_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ), .store_sr_req_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ), .store_sr_req_r_reg_1(store_sr_r_i_1_n_0), .tempmon_pi_f_en_r(tempmon_pi_f_en_r), .tempmon_pi_f_inc_r(tempmon_pi_f_inc_r), .\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0), .\wait_cnt_r_reg[0]_1 (pi_cnt_dec_i_1_n_0), .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .wrcal_prech_req(wrcal_prech_req), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_done_r1_reg(u_ddr_phy_wrcal_n_91), .wrlvl_done_r1_reg_0(u_ddr_phy_init_n_499), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_mux_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 )); ddr3_if_mig_7series_v4_0_ddr_phy_tempmon ddr_phy_tempmon_0 (.CLK(CLK), .D(ddr_phy_tempmon_0_n_3), .SS(SS), .calib_complete(calib_complete), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] (ddr_phy_tempmon_0_n_4), .\calib_zero_inputs_reg[1]_0 (ddr_phy_tempmon_0_n_5), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .cmd_delay_start0(cmd_delay_start0), .ctl_lane_sel(ctl_lane_sel), .delay_done_r4_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .fine_adjust_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (ddr_phy_tempmon_0_n_2), .\gen_byte_sel_div1.calib_in_common_reg (ddr_phy_tempmon_0_n_6), .oclkdelay_calib_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ), .rd_data_offset_cal_done(rd_data_offset_cal_done), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .tempmon_pi_f_inc(tempmon_pi_f_inc), .tempmon_sample_en(tempmon_sample_en), .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec)); LUT6 #( .INIT(64'hFEFFFFFF02000000)) dq_cnt_inc_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I4(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ), .I5(p_0_in_2), .O(dq_cnt_inc_i_1_n_0)); LUT6 #( .INIT(64'h00E2FFFF00E20000)) dqs_found_prech_req_i_1 (.I0(fine_adj_state_r16_out), .I1(fine_adj_state_r144_out), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_78 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_110 ), .I5(dqs_found_prech_req), .O(dqs_found_prech_req_i_1_n_0)); ddr3_if_mig_7series_v4_0_ddr_phy_dqs_found_cal \dqsfind_calib_right.u_ddr_phy_dqs_found_cal (.CLK(CLK), .D({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_103 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_104 }), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .\FSM_sequential_fine_adj_state_r_reg[0]_0 ({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 }), .\FSM_sequential_fine_adj_state_r_reg[0]_1 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_80 ), .\FSM_sequential_fine_adj_state_r_reg[0]_2 (fine_adjust_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[0]_3 (fine_adjust_done_r_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_0 (rst_dqs_find_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_1 (final_dec_done_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_2 (ck_po_stg2_f_indec_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[1]_3 (ck_po_stg2_f_en_i_1_n_0), .\FSM_sequential_fine_adj_state_r_reg[2]_0 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ), .\FSM_sequential_fine_adj_state_r_reg[2]_1 (dqs_found_prech_req_i_1_n_0), .Q(\po_rdval_cnt_reg[8] [1:0]), .byte_sel_cnt(byte_sel_cnt), .\calib_data_offset_0_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ), .\calib_data_offset_0_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ), .\calib_data_offset_0_reg[4] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ), .\calib_data_offset_0_reg[5] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ), .\calib_data_offset_1_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ), .\calib_data_offset_1_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ), .\calib_data_offset_1_reg[4] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_95 ), .\calib_data_offset_1_reg[5] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ), .\calib_zero_inputs_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ), .\calib_zero_inputs_reg[1]_0 ({calib_zero_inputs,calib_zero_inputs__0}), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .ck_po_stg2_f_en(ck_po_stg2_f_en), .ck_po_stg2_f_indec(ck_po_stg2_f_indec), .cmd_delay_start0(cmd_delay_start0), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1] ), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2] ), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4] ), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ), .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0] ), .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1] ), .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2] ), .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3] ), .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4] ), .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ), .cnt_cmd_done_r(cnt_cmd_done_r), .ctl_lane_cnt(ctl_lane_cnt), .ctl_lane_sel(ctl_lane_sel), .\dec_cnt_reg[0]_0 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ), .detect_pi_found_dqs(detect_pi_found_dqs), .dqs_found_prech_req(dqs_found_prech_req), .dqs_found_prech_req_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_78 ), .dqs_found_prech_req_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_110 ), .dqs_po_dec_done(dqs_po_dec_done), .dqs_po_en_stg2_f(dqs_po_en_stg2_f), .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec), .final_dec_done_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ), .final_dec_done_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_79 ), .fine_adj_state_r144_out(fine_adj_state_r144_out), .fine_adj_state_r16_out(fine_adj_state_r16_out), .fine_adjust_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ), .fine_adjust_reg_0(fine_adjust_reg), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .\gen_byte_sel_div1.calib_in_common_reg (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\phaser_in_gen.phaser_in_i_12_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\phaser_in_gen.phaser_in_i_12__0_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\phaser_in_gen.phaser_in_i_12__1_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\phaser_in_gen.phaser_in_i_12__2_n_0 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[0] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 (\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ), .\gen_byte_sel_div1.ctl_lane_sel_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 (\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ), .\gen_byte_sel_div1.ctl_lane_sel_reg[2] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ), .\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 (\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ), .ififo_rst_reg(ififo_rst_reg), .ififo_rst_reg_0(ififo_rst_reg_0), .ififo_rst_reg_1(ififo_rst_reg_1), .ififo_rst_reg_2(ififo_rst_reg_2), .in0(in0), .init_calib_complete_reg(ddr_phy_tempmon_0_n_5), .init_dec_done_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ), .init_dec_done_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ), .init_dec_done_reg_2(init_dec_done_i_1_n_0), .init_dqsfound_done_r2(init_dqsfound_done_r2), .init_dqsfound_done_r5(init_dqsfound_done_r5), .init_dqsfound_done_r_reg_0(init_dqsfound_done_r_i_1_n_0), .\init_state_r_reg[1] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ), .\init_state_r_reg[1]_0 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ), .\init_state_r_reg[1]_1 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ), .\init_state_r_reg[2] (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ), .\num_refresh_reg[1] (u_ddr_phy_init_n_117), .oclkdelay_calib_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ), .oclkdelay_calib_done_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .out({p_3_in25_in,p_2_in24_in,p_0_in23_in,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 }), .p_1_in27_in(p_1_in27_in), .p_1_in50_in(p_1_in50_in), .pi_calib_done(pi_calib_done), .\pi_dqs_found_all_bank_r_reg[1]_0 (pi_dqs_found_all_bank), .\pi_dqs_found_all_bank_r_reg[1]_1 (rank_done_r_i_1_n_0), .pi_dqs_found_any_bank(pi_dqs_found_any_bank), .pi_dqs_found_done_r1(pi_dqs_found_done_r1), .pi_dqs_found_done_r1_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .\pi_dqs_found_lanes_r3_reg[3]_0 (\pi_dqs_found_any_bank[0]_i_1_n_0 ), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .pi_dqs_found_start_reg(u_ddr_phy_init_n_502), .pi_dqs_found_start_reg_0(u_ddr_phy_init_n_501), .pi_f_inc_reg(ddr_phy_tempmon_0_n_6), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .\pi_rst_stg1_cal_r_reg[0]_0 (\pi_rst_stg1_cal_r_reg[0] ), .\pi_rst_stg1_cal_r_reg[0]_1 (\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_1 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_2 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_6 ), .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_23 ), .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_25 ), .\po_counter_read_val_reg[8]_12 (\po_counter_read_val_reg[8]_26 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_7 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_9 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_10 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_16 ), .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_17 ), .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_19 ), .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_20 ), .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_22 ), .po_en_stg23(po_en_stg23), .po_en_stg2_f(cmd_po_en_stg2_f), .po_enstg2_f(po_enstg2_f), .po_stg23_incdec(po_stg23_incdec), .po_stg2_fincdec(po_stg2_fincdec), .prbs_last_byte_done_r(prbs_last_byte_done_r), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prech_done(prech_done), .rank_done_r_reg_0(pi_dqs_found_all_bank_r), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_73 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 }), .\rank_final_loop[0].final_do_max_reg[0][3]_0 (rd_data_offset_ranks_0), .\rank_final_loop[0].final_do_max_reg[0][3]_1 (rd_data_offset_ranks_1), .\rd_byte_data_offset_reg[0][9]_0 (p_0_in_0), .\rd_byte_data_offset_reg[0]_3 (\rd_byte_data_offset_reg[0]_3 ), .rd_data_offset_cal_done(rd_data_offset_cal_done), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rst_dqs_find(rst_dqs_find), .rst_dqs_find_r1_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ), .rst_dqs_find_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_109 ), .rst_dqs_find_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_111 ), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .sent_col(sent_col), .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_final_mux(wrlvl_final_mux)); LUT4 #( .INIT(16'h2F20)) early1_data_i_1 (.I0(u_ddr_phy_wrcal_n_67), .I1(u_ddr_phy_wrcal_n_110), .I2(u_ddr_phy_wrcal_n_119), .I3(u_ddr_phy_wrcal_n_73), .O(early1_data_i_1_n_0)); LUT5 #( .INIT(32'h04FF0400)) early2_data_i_1 (.I0(u_ddr_phy_wrcal_n_67), .I1(u_ddr_phy_wrcal_n_66), .I2(u_ddr_phy_wrcal_n_110), .I3(u_ddr_phy_wrcal_n_119), .I4(u_ddr_phy_wrcal_n_74), .O(early2_data_i_1_n_0)); LUT5 #( .INIT(32'hFFFF0400)) final_dec_done_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_79 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ), .O(final_dec_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00100000)) fine_adjust_done_r_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I2(p_1_in27_in), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I5(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ), .O(fine_adjust_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00000100)) fine_adjust_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ), .I3(init_dqsfound_done_r5), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I5(\pi_rst_stg1_cal_r_reg[0] ), .O(fine_adjust_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair714" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[11]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[3]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [2])); (* SOFT_HLUTNM = "soft_lutpair702" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[11]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[3]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair714" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[11]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[3]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [2])); (* SOFT_HLUTNM = "soft_lutpair702" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[11]_i_1__2 (.I0(fine_delay_mod[3]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair713" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[14]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[4]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [3])); (* SOFT_HLUTNM = "soft_lutpair703" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[14]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[4]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair713" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[14]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[4]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [3])); (* SOFT_HLUTNM = "soft_lutpair703" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[14]_i_1__2 (.I0(fine_delay_mod[4]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair705" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[17]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[5]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [4])); (* SOFT_HLUTNM = "soft_lutpair711" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[17]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[5]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair711" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[17]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[5]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [4])); (* SOFT_HLUTNM = "soft_lutpair705" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[17]_i_1__2 (.I0(fine_delay_mod[5]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair704" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[20]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[6]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [5])); (* SOFT_HLUTNM = "soft_lutpair712" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[20]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[6]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair712" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[20]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[6]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [5])); (* SOFT_HLUTNM = "soft_lutpair704" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[20]_i_1__2 (.I0(fine_delay_mod[6]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair706" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[23]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[7]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [6])); (* SOFT_HLUTNM = "soft_lutpair715" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[23]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[7]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair715" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[23]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[7]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [6])); (* SOFT_HLUTNM = "soft_lutpair700" *) LUT5 #( .INIT(32'h0000AB00)) \fine_delay_r[23]_i_1__2 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair706" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[23]_i_2 (.I0(fine_delay_mod[7]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[7])); (* SOFT_HLUTNM = "soft_lutpair697" *) LUT5 #( .INIT(32'h0000EA00)) \fine_delay_r[26]_i_1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair700" *) LUT5 #( .INIT(32'h0000BA00)) \fine_delay_r[26]_i_1__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair697" *) LUT5 #( .INIT(32'h0000BA00)) \fine_delay_r[26]_i_1__1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(fine_delay_sel_r), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[5]_1 )); (* SOFT_HLUTNM = "soft_lutpair709" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[26]_i_2 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[8]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [7])); (* SOFT_HLUTNM = "soft_lutpair709" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[26]_i_2__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[8]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair717" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[26]_i_2__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[8]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [7])); (* SOFT_HLUTNM = "soft_lutpair708" *) LUT5 #( .INIT(32'h44440004)) \fine_delay_r[2]_i_1 (.I0(calib_zero_inputs__0), .I1(fine_delay_mod[0]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair707" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[5]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[1]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [0])); (* SOFT_HLUTNM = "soft_lutpair716" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[5]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[1]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair716" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[5]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[1]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [0])); (* SOFT_HLUTNM = "soft_lutpair707" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[5]_i_1__2 (.I0(fine_delay_mod[1]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair710" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[8]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[2]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26] [1])); (* SOFT_HLUTNM = "soft_lutpair710" *) LUT5 #( .INIT(32'h0000F200)) \fine_delay_r[8]_i_1__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(fine_delay_mod[2]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair701" *) LUT5 #( .INIT(32'h0000F800)) \fine_delay_r[8]_i_1__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(fine_delay_mod[2]), .I4(calib_zero_inputs__0), .O(\fine_delay_r_reg[26]_1 [1])); (* SOFT_HLUTNM = "soft_lutpair701" *) LUT5 #( .INIT(32'h22220002)) \fine_delay_r[8]_i_1__2 (.I0(fine_delay_mod[2]), .I1(calib_zero_inputs__0), .I2(\po_rdval_cnt_reg[8] [0]), .I3(\po_rdval_cnt_reg[8] [1]), .I4(calib_in_common), .O(D[2])); LUT6 #( .INIT(64'hFFFFDFDD00000008)) fine_delay_sel_i_1 (.I0(prbs_state_r[0]), .I1(prbs_state_r[4]), .I2(prbs_state_r[3]), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ), .I5(fine_delay_sel_r_reg), .O(fine_delay_sel_i_1_n_0)); LUT6 #( .INIT(64'h8FFFFFFF80000000)) fine_dly_error_i_1 (.I0(dec_cnt_reg[0]), .I1(dec_cnt_reg[5]), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ), .I3(prbs_state_r[1]), .I4(prbs_state_r[0]), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ), .O(fine_dly_error_i_1_n_0)); LUT6 #( .INIT(64'h00000000FFFFAAA8)) flag_ck_negedge_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ), .I2(stable_cnt1), .I3(stable_cnt227_in), .I4(flag_ck_negedge09_out), .I5(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ), .O(flag_ck_negedge_i_1_n_0)); LUT6 #( .INIT(64'h3F3FFBFF00000800)) found_first_edge_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ), .O(found_first_edge_r_i_1_n_0)); LUT5 #( .INIT(32'h08FF0800)) found_second_edge_r_i_1 (.I0(found_stable_eye_last_r), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ), .O(found_second_edge_r_i_1_n_0)); LUT3 #( .INIT(8'hB8)) found_stable_eye_last_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ), .I1(detect_edge_done_r), .I2(found_stable_eye_last_r), .O(found_stable_eye_last_r_i_1_n_0)); FDRE \gen_byte_sel_div1.byte_sel_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ), .Q(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .R(1'b0)); FDRE \gen_byte_sel_div1.byte_sel_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ), .Q(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .R(1'b0)); FDRE \gen_byte_sel_div1.byte_sel_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ), .Q(byte_sel_cnt), .R(1'b0)); (* syn_maxfan = "10" *) FDRE \gen_byte_sel_div1.calib_in_common_reg (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ), .Q(calib_in_common), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \gen_byte_sel_div1.ctl_lane_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ), .Q(\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \gen_byte_sel_div1.ctl_lane_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ), .Q(\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \gen_byte_sel_div1.ctl_lane_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ), .Q(\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__9)); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .O(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .O(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .O(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .O(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I3(pb_detect_edge_done_r[0]), .O(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[0].pb_found_edge_r[0]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ), .I5(pb_detect_edge_done_r[0]), .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ), .I1(pb_detect_edge_done_r[0]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ), .I4(pb_found_stable_eye_r76_out), .I5(\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in102_in), .I3(pb_detect_edge_done_r[1]), .O(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[1].pb_found_edge_r[1]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in16_in), .I5(pb_detect_edge_done_r[1]), .O(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ), .I1(pb_detect_edge_done_r[1]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ), .I4(pb_found_stable_eye_r72_out), .I5(\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in99_in), .I3(pb_detect_edge_done_r[2]), .O(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[2].pb_found_edge_r[2]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in13_in), .I5(pb_detect_edge_done_r[2]), .O(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ), .I1(pb_detect_edge_done_r[2]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ), .I4(pb_found_stable_eye_r68_out), .I5(\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in96_in), .I3(pb_detect_edge_done_r[3]), .O(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[3].pb_found_edge_r[3]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in10_in), .I5(pb_detect_edge_done_r[3]), .O(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ), .I1(pb_detect_edge_done_r[3]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ), .I4(pb_found_stable_eye_r64_out), .I5(\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in93_in), .I3(pb_detect_edge_done_r[4]), .O(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[4].pb_found_edge_r[4]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in7_in), .I5(pb_detect_edge_done_r[4]), .O(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ), .I1(pb_detect_edge_done_r[4]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ), .I4(pb_found_stable_eye_r60_out), .I5(\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in90_in), .I3(pb_detect_edge_done_r[5]), .O(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[5].pb_found_edge_r[5]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in4_in), .I5(pb_detect_edge_done_r[5]), .O(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ), .I1(pb_detect_edge_done_r[5]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ), .I4(pb_found_stable_eye_r56_out), .I5(\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in87_in), .I3(pb_detect_edge_done_r[6]), .O(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[6].pb_found_edge_r[6]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in1_in), .I5(pb_detect_edge_done_r[6]), .O(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ), .I1(pb_detect_edge_done_r[6]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ), .I4(pb_found_stable_eye_r52_out), .I5(\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 )); LUT4 #( .INIT(16'h5554)) \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I2(p_0_in84_in), .I3(pb_detect_edge_done_r[7]), .O(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 )); LUT6 #( .INIT(64'h5050505051515051)) \gen_track_left_edge[7].pb_found_edge_r[7]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ), .I4(p_0_in), .I5(pb_detect_edge_done_r[7]), .O(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFEFE01000000)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ), .I1(pb_detect_edge_done_r[7]), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ), .I5(\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[0].left_edge_found_pb[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ), .O(\genblk8[0].left_edge_found_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[0].left_edge_updated[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[0]), .O(\genblk8[0].left_edge_updated[0]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[0].right_edge_found_pb[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[0].right_edge_found_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[1].left_edge_found_pb[1]_i_1 (.I0(p_146_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ), .O(\genblk8[1].left_edge_found_pb[1]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[1].left_edge_updated[1]_i_1 (.I0(p_146_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[1]), .O(\genblk8[1].left_edge_updated[1]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[1].right_edge_found_pb[1]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ), .I2(p_143_out), .I3(p_146_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[1].right_edge_found_pb[1]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[2].left_edge_found_pb[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ), .O(\genblk8[2].left_edge_found_pb[2]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[2].left_edge_updated[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[2]), .O(\genblk8[2].left_edge_updated[2]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[2].right_edge_found_pb[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[2].right_edge_found_pb[2]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[3].left_edge_found_pb[3]_i_1 (.I0(p_130_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ), .O(\genblk8[3].left_edge_found_pb[3]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[3].left_edge_updated[3]_i_1 (.I0(p_130_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[3]), .O(\genblk8[3].left_edge_updated[3]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[3].right_edge_found_pb[3]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ), .I2(p_127_out), .I3(p_130_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[3].right_edge_found_pb[3]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[4].left_edge_found_pb[4]_i_1 (.I0(p_122_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ), .O(\genblk8[4].left_edge_found_pb[4]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[4].left_edge_updated[4]_i_1 (.I0(p_122_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[4]), .O(\genblk8[4].left_edge_updated[4]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[4].right_edge_found_pb[4]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ), .I2(p_119_out), .I3(p_122_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[4].right_edge_found_pb[4]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[5].left_edge_found_pb[5]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ), .O(\genblk8[5].left_edge_found_pb[5]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[5].left_edge_updated[5]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[5]), .O(\genblk8[5].left_edge_updated[5]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[5].right_edge_found_pb[5]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[5].right_edge_found_pb[5]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[6].left_edge_found_pb[6]_i_1 (.I0(p_106_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ), .O(\genblk8[6].left_edge_found_pb[6]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[6].left_edge_updated[6]_i_1 (.I0(p_106_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[6]), .O(\genblk8[6].left_edge_updated[6]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[6].right_edge_found_pb[6]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ), .I2(p_103_out), .I3(p_106_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[6].right_edge_found_pb[6]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[7].left_edge_found_pb[7]_i_1 (.I0(p_98_out), .I1(p_154_out), .I2(right_gain_pb), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ), .O(\genblk8[7].left_edge_found_pb[7]_i_1_n_0 )); LUT4 #( .INIT(16'hCF88)) \genblk8[7].left_edge_updated[7]_i_1 (.I0(p_98_out), .I1(p_154_out), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ), .I3(left_edge_updated[7]), .O(\genblk8[7].left_edge_updated[7]_i_1_n_0 )); LUT6 #( .INIT(64'hCCFE0000CCFECCCC)) \genblk8[7].right_edge_found_pb[7]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ), .I2(p_95_out), .I3(p_98_out), .I4(p_154_out), .I5(right_gain_pb), .O(\genblk8[7].right_edge_found_pb[7]_i_1_n_0 )); LUT2 #( .INIT(4'h4)) \genblk9[0].fine_delay_incdec_pb[0]_i_7 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ), .I1(bit_cnt), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 )); LUT6 #( .INIT(64'hFFDF77DF00000000)) idel_adj_inc_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ), .I4(cal1_wait_r), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ), .O(idel_adj_inc_i_1_n_0)); LUT6 #( .INIT(64'hF0F0B1F0F0B0F0F0)) idel_pat_detect_valid_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ), .O(idel_pat_detect_valid_r_i_1_n_0)); FDRE idelay_ce_r1_reg (.C(CLK), .CE(1'b1), .D(idelay_ce_int), .Q(idelay_ce_r1), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE idelay_ce_r2_reg (.C(CLK), .CE(1'b1), .D(idelay_ce_r1), .Q(idelay_ce), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE idelay_inc_r1_reg (.C(CLK), .CE(1'b1), .D(idelay_inc_int), .Q(idelay_inc_r1), .R(rstdiv0_sync_r1_reg_rep__9)); (* syn_maxfan = "30" *) FDRE idelay_inc_r2_reg (.C(CLK), .CE(1'b1), .D(idelay_inc_r1), .Q(idelay_inc), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hFFFFFCFF00000080)) idelay_ld_done_i_1 (.I0(u_ddr_phy_wrcal_n_113), .I1(u_ddr_phy_wrcal_n_111), .I2(u_ddr_phy_wrcal_n_109), .I3(u_ddr_phy_wrcal_n_110), .I4(u_ddr_phy_wrcal_n_108), .I5(u_ddr_phy_wrcal_n_69), .O(idelay_ld_done_i_1_n_0)); LUT4 #( .INIT(16'h2F20)) idelay_ld_i_1 (.I0(u_ddr_phy_wrcal_n_4), .I1(u_ddr_phy_wrcal_n_109), .I2(u_ddr_phy_wrcal_n_116), .I3(idelay_ld), .O(idelay_ld_i_1_n_0)); LUT3 #( .INIT(8'hB8)) inhibit_edge_detect_r_i_1 (.I0(inhibit_edge_detect_r), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ), .O(inhibit_edge_detect_r_i_1_n_0)); (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE init_calib_complete_reg (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(phy_dout[33]), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE init_calib_complete_reg_rep (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(\my_empty_reg[7] ), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__0 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__0_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__1 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__1_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__10 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__10_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__11 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__11_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__12 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__12_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__13 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__13_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE init_calib_complete_reg_rep__14 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_r_reg), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__2 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__2_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__3 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__3_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__4 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__4_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE init_calib_complete_reg_rep__5 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(\rd_ptr_timing_reg[0] ), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE init_calib_complete_reg_rep__6 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(app_zq_r_reg), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) FDRE init_calib_complete_reg_rep__7 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(\my_empty_reg[7]_0 ), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__8 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__8_n_0), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) (* ORIG_CELL_NAME = "init_calib_complete_reg" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE init_calib_complete_reg_rep__9 (.C(CLK), .CE(1'b1), .D(calib_complete), .Q(init_calib_complete_reg_rep__9_n_0), .R(1'b0)); LUT5 #( .INIT(32'hFFFF0004)) init_complete_r_i_1 (.I0(init_state_r), .I1(u_ddr_phy_init_n_105), .I2(u_ddr_phy_init_n_104), .I3(u_ddr_phy_init_n_470), .I4(u_ddr_phy_init_n_18), .O(init_complete_r_i_1_n_0)); LUT5 #( .INIT(32'hFFFF0004)) init_complete_r_timing_i_1 (.I0(init_state_r), .I1(u_ddr_phy_init_n_105), .I2(u_ddr_phy_init_n_104), .I3(u_ddr_phy_init_n_470), .I4(init_complete_r_timing_orig), .O(init_complete_r_timing_i_1_n_0)); LUT6 #( .INIT(64'hAAAAAAAAAABAAAAA)) init_dec_done_i_1 (.I0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_80 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ), .I5(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .O(init_dec_done_i_1_n_0)); LUT6 #( .INIT(64'h00000000000000E2)) init_dqsfound_done_r_i_1 (.I0(rd_data_offset_cal_done), .I1(p_1_in27_in), .I2(\rd_byte_data_offset_reg[0]_3 ), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ), .I5(p_1_in50_in), .O(init_dqsfound_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair699" *) LUT5 #( .INIT(32'h0000AB00)) \input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 )); (* SOFT_HLUTNM = "soft_lutpair698" *) LUT5 #( .INIT(32'h0000EA00)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair698" *) LUT5 #( .INIT(32'h0000BA00)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair699" *) LUT5 #( .INIT(32'h0000BA00)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(idelay_ce), .I4(calib_zero_inputs__0), .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 )); ddr3_if_mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay (.CLK(CLK), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .Q(\po_rdval_cnt_reg[8] [1:0]), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .cmd_delay_start0(cmd_delay_start0), .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r), .ctl_lane_cnt(ctl_lane_cnt), .delay_dec_done_reg_0(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ), .delay_dec_done_reg_1(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ), .dqs_po_dec_done(dqs_po_dec_done), .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec), .\init_state_r_reg[0] (\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ), .\mcGo_r_reg[15] (\mcGo_r_reg[15] ), .p_1_in(p_1_in), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .po_cnt_inc_reg_0(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_0 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_4 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_5 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_18 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_21 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_24 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_27 ), .po_en_stg2_f(cmd_po_en_stg2_f), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0_1), .\wait_cnt_r_reg[0]_1 (po_cnt_inc_i_1_n_0), .\wait_cnt_r_reg[0]_2 (po_cnt_dec_i_1_n_0)); ddr3_if_mig_7series_v4_0_ddr_phy_wrlvl \mb_wrlvl_inst.u_ddr_phy_wrlvl (.CLK(CLK), .D({\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}), .\FSM_sequential_wl_state_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ), .\FSM_sequential_wl_state_r_reg[0]_1 (wr_level_done_r_i_1_n_0), .\FSM_sequential_wl_state_r_reg[1]_0 (dq_cnt_inc_i_1_n_0), .\FSM_sequential_wl_state_r_reg[2]_0 (wl_edge_detect_valid_r_i_1_n_0), .\FSM_sequential_wl_state_r_reg[2]_1 (wrlvl_rank_done_r_i_1_n_0), .O({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }), .Q(\u_ocd_lim/stg3_init_val ), .S(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[1] (\byte_r_reg[1] ), .byte_sel_cnt(byte_sel_cnt), .\calib_sel_reg[3] (\po_rdval_cnt_reg[8] [2]), .delay_done_r4_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ), .done_dqs_dec239_out(done_dqs_dec239_out), .done_dqs_tap_inc(done_dqs_tap_inc), .dq_cnt_inc_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ), .dqs_po_dec_done(dqs_po_dec_done), .dqs_po_en_stg2_f(dqs_po_en_stg2_f), .dqs_po_en_stg2_f_reg_0(dqs_po_en_stg2_f_reg), .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec), .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec), .early1_data_reg(u_ddr_phy_wrcal_n_101), .early1_data_reg_0(u_ddr_phy_wrcal_n_73), .flag_ck_negedge09_out(flag_ck_negedge09_out), .flag_ck_negedge_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ), .flag_ck_negedge_reg_1(flag_ck_negedge_i_1_n_0), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ), .inhibit_edge_detect_r(inhibit_edge_detect_r), .inhibit_edge_detect_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ), .inhibit_edge_detect_r_reg_1(inhibit_edge_detect_r_i_1_n_0), .\lim_state_reg[12] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ), .\mcGo_r_reg[15] (\mcGo_r_reg[15] ), .my_empty(my_empty), .my_empty_6(my_empty_6), .my_empty_7(my_empty_7), .my_empty_8(my_empty_8), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_calib_done_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ), .oclkdelay_calib_done_r_reg_1(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ), .out({\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 }), .p_0_in(p_0_in_2), .p_1_in(p_1_in), .pi_f_inc_reg(ddr_phy_tempmon_0_n_2), .pi_fine_dly_dec_done(pi_fine_dly_dec_done), .po_cnt_dec_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ), .po_cnt_dec_reg_1(po_cnt_dec_reg), .\po_counter_read_val_reg[5] ({\po_counter_read_val_reg[5] [5:4],\po_counter_read_val_reg[5] [2:1]}), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_30 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_31 ), .\po_rdval_cnt_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ), .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_100), .\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_98), .\po_stg2_wrcal_cnt_reg[2] ({po_stg2_wrcal_cnt,\idelay_tap_cnt_r_reg[0][3][0] }), .\po_stg2_wrcal_cnt_reg[2]_0 (u_ddr_phy_wrcal_n_97), .\prbs_dqs_cnt_r_reg[2] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ), .\rank_cnt_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ), .\rank_cnt_r_reg[0]_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ), .\rd_data_edge_detect_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ), .\rd_data_edge_detect_r_reg[0]_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__15(rstdiv0_sync_r1_reg_rep__14[0]), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .\single_rank.done_dqs_dec_reg_0 (wr_level_done_i_1_n_0), .stable_cnt1(stable_cnt1), .stable_cnt227_in(stable_cnt227_in), .\stable_cnt_reg[3]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ), .\stg2_r_reg[0] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ), .\stg2_r_reg[4] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ), .\stg2_r_reg[5] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ), .\stg2_tap_cnt_reg[2] (\u_ocd_lim/stg2_tap_cnt_reg ), .\stg2_target_r_reg[4] (wl_po_fine_cnt_sel_0__0), .\stg3_dec_val_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ), .\stg3_dec_val_reg[2]_0 (\u_ocd_lim/stg3_dec_val00_out ), .\stg3_r_reg[5] ({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }), .\wait_cnt_reg[0]_0 (po_cnt_dec_i_1__0_n_0), .wl_sm_start(wl_sm_start), .wr_level_done_r1_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ), .wr_level_done_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ), .wr_lvl_start_reg(u_ddr_phy_init_n_790), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_r(wrlvl_byte_redo_r), .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_102), .wrlvl_done_r_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_r(wrlvl_final_r), .wrlvl_rank_done(wrlvl_rank_done), .wrlvl_rank_done_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ), .\wrlvl_redo_corse_inc_reg[2]_0 (final_coarse_tap)); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1 (.I0(init_calib_complete_reg_rep__13_n_0), .I1(mc_cas_n[1]), .O(phy_dout[32])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[260]), .O(\my_empty_reg[7]_1 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[261]), .O(\my_empty_reg[7]_2 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__3 (.I0(\my_empty_reg[7]_0 ), .I1(Q[262]), .O(\my_empty_reg[7]_3 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_1__4 (.I0(\my_empty_reg[7]_0 ), .I1(Q[263]), .O(\my_empty_reg[7]_4 [65])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[256]), .O(\my_empty_reg[7]_1 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[257]), .O(\my_empty_reg[7]_2 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__3 (.I0(\my_empty_reg[7]_0 ), .I1(Q[258]), .O(\my_empty_reg[7]_3 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__4 (.I0(\my_empty_reg[7]_0 ), .I1(Q[259]), .O(\my_empty_reg[7]_4 [64])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[268]), .O(\my_empty_reg[7]_1 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[269]), .O(\my_empty_reg[7]_2 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__3 (.I0(\my_empty_reg[7]_0 ), .I1(Q[270]), .O(\my_empty_reg[7]_3 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__4 (.I0(\my_empty_reg[7]_0 ), .I1(Q[271]), .O(\my_empty_reg[7]_4 [67])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__0 (.I0(\my_empty_reg[7]_0 ), .I1(Q[264]), .O(\my_empty_reg[7]_1 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[265]), .O(\my_empty_reg[7]_2 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[266]), .O(\my_empty_reg[7]_3 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_4__3 (.I0(\my_empty_reg[7]_0 ), .I1(Q[267]), .O(\my_empty_reg[7]_4 [66])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5 (.I0(\my_empty_reg[7]_0 ), .I1(Q[276]), .O(\my_empty_reg[7]_1 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5__0 (.I0(\my_empty_reg[7]_0 ), .I1(Q[277]), .O(\my_empty_reg[7]_2 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[278]), .O(\my_empty_reg[7]_3 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_5__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[279]), .O(\my_empty_reg[7]_4 [69])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6 (.I0(\my_empty_reg[7]_0 ), .I1(Q[272]), .O(\my_empty_reg[7]_1 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6__0 (.I0(\my_empty_reg[7]_0 ), .I1(Q[273]), .O(\my_empty_reg[7]_2 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[274]), .O(\my_empty_reg[7]_3 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_6__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[275]), .O(\my_empty_reg[7]_4 [68])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[284]), .O(\my_empty_reg[7]_1 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1__0 (.I0(\my_empty_reg[7]_0 ), .I1(Q[285]), .O(\my_empty_reg[7]_2 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[286]), .O(\my_empty_reg[7]_3 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_1__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[287]), .O(\my_empty_reg[7]_4 [71])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[280]), .O(\my_empty_reg[7]_1 [70])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2__0 (.I0(\my_empty_reg[7]_0 ), .I1(Q[281]), .O(\my_empty_reg[7]_2 [70])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2__1 (.I0(\my_empty_reg[7]_0 ), .I1(Q[282]), .O(\my_empty_reg[7]_3 [70])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_78_79_i_2__2 (.I0(\my_empty_reg[7]_0 ), .I1(Q[283]), .O(\my_empty_reg[7]_4 [70])); LUT6 #( .INIT(64'hAFFFFFFF04000000)) mpr_dec_cpt_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ), .I5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ), .O(mpr_dec_cpt_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair718" *) LUT4 #( .INIT(16'h2F20)) mpr_last_byte_done_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ), .I3(mpr_last_byte_done), .O(mpr_last_byte_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFC8C00000080)) mpr_rank_done_r_i_1 (.I0(cal1_cnt_cpt_r1), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ), .I5(mpr_rnk_done), .O(mpr_rank_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair731" *) LUT2 #( .INIT(4'hE)) mpr_rdlvl_done_r_i_1 (.I0(rdlvl_stg1_done_int), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .O(mpr_rdlvl_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFEFFFF00020000)) new_cnt_dqs_r_i_1 (.I0(new_cnt_dqs_r), .I1(prbs_state_r[4]), .I2(prbs_state_r[1]), .I3(prbs_state_r[2]), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ), .O(new_cnt_dqs_r_i_1_n_0)); LUT6 #( .INIT(64'h8F888FFF80888000)) no_err_win_detected_latch_i_1 (.I0(prbs_state_r[3]), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ), .I3(prbs_state_r[0]), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ), .O(no_err_win_detected_latch_i_1_n_0)); LUT6 #( .INIT(64'hF0F0F4F0B0B0F0F0)) num_samples_done_ind_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ), .I1(prbs_state_r[4]), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ), .I3(num_samples_done_r), .I4(prbs_state_r[1]), .I5(prbs_state_r[0]), .O(num_samples_done_ind_i_1_n_0)); ddr3_if_mig_7series_v4_0_ddr_phy_oclkdelay_cal \oclk_calib.u_ddr_phy_oclkdelay_cal (.CLK(CLK), .D(\u_ocd_lim/stg3_dec_val00_out ), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .O({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }), .Q(\po_rdval_cnt_reg[8] [1:0]), .S(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ), .\byte_r_reg[0]_1 (\byte_r_reg[0]_0 ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\cal2_state_r_reg[0] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .cnt_cmd_done_r(cnt_cmd_done_r), .\cnt_shift_r_reg[0] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ), .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r), .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel), .complex_ocal_ref_req(complex_ocal_ref_req), .complex_oclk_calib_resume(complex_oclk_calib_resume), .done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ), .\gen_byte_sel_div1.calib_in_common_reg (\phaser_in_gen.phaser_in_i_12__0_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\phaser_in_gen.phaser_in_i_12__2_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\phaser_in_gen.phaser_in_i_12__1_n_0 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\phaser_in_gen.phaser_in_i_12_n_0 ), .\init_state_r_reg[0] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ), .\init_state_r_reg[0]_0 (u_ddr_phy_init_n_114), .\init_state_r_reg[0]_1 (u_ddr_phy_init_n_478), .\init_state_r_reg[2] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ), .\init_state_r_reg[4] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ), .\init_state_r_reg[4]_0 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ), .\init_state_r_reg[4]_1 ({u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_108}), .\init_state_r_reg[5] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ), .\init_state_r_reg[5]_0 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ), .\init_state_r_reg[5]_1 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ), .\init_state_r_reg[6] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ), .lim2init_prech_req(lim2init_prech_req), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .ocal_last_byte_done(ocal_last_byte_done), .ocal_last_byte_done_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .ocal_last_byte_done_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ), .ocd_prech_req(ocd_prech_req), .oclkdelay_calib_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ), .oclkdelay_calib_start_int_reg(u_ddr_phy_init_n_462), .oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_24), .oclkdelay_center_calib_start_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ), .oclkdelay_int_ref_req_reg(u_ddr_phy_init_n_477), .pd_out(pd_out), .phy_rddata_en(phy_rddata_en), .phy_rddata_en_1(phy_rddata_en_1), .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt), .\po_counter_read_val_reg[2] (\po_counter_read_val_reg[2] ), .\po_counter_read_val_reg[5] (\po_counter_read_val_reg[5] ), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_3 ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_8 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_11 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_12 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_13 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_14 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_15 ), .po_en_stg23(po_en_stg23), .po_stg23_incdec(po_stg23_incdec), .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_105), .\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_106), .poc_sample_pd(poc_sample_pd), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prech_done(prech_done), .prech_req_posedge_r_reg(u_ddr_phy_init_n_9), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .rd_active_r1(rd_active_r1), .rd_active_r2(rd_active_r2), .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33), .\resume_wait_r_reg[5] (E), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0), .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1), .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\samps_r_reg[9] (\samps_r_reg[9] ), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .sr_valid_r108_out(sr_valid_r108_out), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .\stg2_tap_cnt_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ), .\stg2_tap_cnt_reg[3] (\u_ocd_lim/stg2_tap_cnt_reg ), .\stg2_target_r_reg[8] ({\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .\stg3_tap_cnt_reg[2] (\u_ocd_lim/stg3_init_val ), .\wl_po_fine_cnt_reg[14] (wl_po_fine_cnt_sel_0__0), .\wl_po_fine_cnt_reg[17] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ), .\wl_po_fine_cnt_reg[18] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ), .\wl_po_fine_cnt_reg[23] ({\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}), .\wl_po_fine_cnt_reg[3] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ), .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_mux_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .\zero2fuzz_r_reg[0] (\zero2fuzz_r_reg[0] )); LUT4 #( .INIT(16'h88F0)) out_fifo_i_10__6 (.I0(\cmd_pipe_plus.mc_address_reg[44] [35]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3]_0 [2]), .I3(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [2])); LUT4 #( .INIT(16'h88F0)) out_fifo_i_11__2 (.I0(\rd_ptr_timing_reg[0] ), .I1(mc_cas_n[1]), .I2(\rd_ptr_reg[3]_0 [1]), .I3(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [1])); LUT4 #( .INIT(16'h88F0)) out_fifo_i_12__6 (.I0(\cmd_pipe_plus.mc_address_reg[44] [13]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3]_0 [0]), .I3(\my_empty_reg[1]_1 ), .O(\my_full_reg[3] [0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_15__6 (.I0(mc_we_n[2]), .I1(\my_empty_reg[7] ), .I2(mem_out[5]), .I3(\my_empty_reg[1]_0 ), .O(D1[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_17__5 (.I0(mc_we_n[0]), .I1(\my_empty_reg[7] ), .I2(mem_out[3]), .I3(\my_empty_reg[1]_0 ), .O(D1[0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_17__6 (.I0(mc_cas_n[2]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [2]), .I3(\my_empty_reg[1] ), .O(D2[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_19__6 (.I0(mc_cas_n[0]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [0]), .I3(\my_empty_reg[1] ), .O(D2[0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_25__5 (.I0(mc_ras_n[2]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [5]), .I3(\my_empty_reg[1] ), .O(D3[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_27__5 (.I0(mc_ras_n[0]), .I1(\my_empty_reg[7] ), .I2(\rd_ptr_reg[3] [3]), .I3(\my_empty_reg[1] ), .O(D3[0])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_7__6 (.I0(mc_ras_n[2]), .I1(\my_empty_reg[7] ), .I2(mem_out[2]), .I3(\my_empty_reg[1]_0 ), .O(D0[2])); LUT4 #( .INIT(16'hBBF0)) out_fifo_i_9__6 (.I0(mc_cs_n), .I1(\my_empty_reg[7] ), .I2(mem_out[0]), .I3(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair727" *) LUT1 #( .INIT(2'h1)) \periodic_read_request.periodic_rd_r_lcl_i_1 (.I0(app_zq_r_reg), .O(maint_prescaler_r1)); (* SOFT_HLUTNM = "soft_lutpair724" *) LUT3 #( .INIT(8'hEA)) \phaser_in_gen.phaser_in_i_12 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .O(\phaser_in_gen.phaser_in_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair725" *) LUT3 #( .INIT(8'hBA)) \phaser_in_gen.phaser_in_i_12__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .O(\phaser_in_gen.phaser_in_i_12__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair725" *) LUT3 #( .INIT(8'hBA)) \phaser_in_gen.phaser_in_i_12__1 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .O(\phaser_in_gen.phaser_in_i_12__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair724" *) LUT3 #( .INIT(8'hAB)) \phaser_in_gen.phaser_in_i_12__2 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .O(\phaser_in_gen.phaser_in_i_12__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair708" *) LUT4 #( .INIT(16'h00F8)) \phaser_in_gen.phaser_in_i_2 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair717" *) LUT4 #( .INIT(16'h00F2)) \phaser_in_gen.phaser_in_i_2__0 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_rdval_cnt_reg[8] [0]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair721" *) LUT4 #( .INIT(16'h00F2)) \phaser_in_gen.phaser_in_i_2__1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair721" *) LUT4 #( .INIT(16'h00F1)) \phaser_in_gen.phaser_in_i_2__2 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_rdval_cnt_reg[8] [1]), .I2(calib_in_common), .I3(calib_zero_inputs__0), .O(\pi_dqs_found_lanes_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair720" *) LUT4 #( .INIT(16'h0040)) phaser_out_i_2 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(calib_zero_inputs), .O(D_po_counter_read_en122_out)); (* SOFT_HLUTNM = "soft_lutpair722" *) LUT4 #( .INIT(16'h0001)) phaser_out_i_2__0 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(calib_zero_inputs), .O(\po_counter_read_val_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair720" *) LUT4 #( .INIT(16'h0004)) phaser_out_i_2__5 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [1]), .I2(\po_rdval_cnt_reg[8] [0]), .I3(calib_zero_inputs), .O(\po_counter_read_val_reg[8]_28 )); (* SOFT_HLUTNM = "soft_lutpair722" *) LUT4 #( .INIT(16'h0004)) phaser_out_i_2__6 (.I0(calib_in_common), .I1(\po_rdval_cnt_reg[8] [0]), .I2(\po_rdval_cnt_reg[8] [1]), .I3(calib_zero_inputs), .O(\po_counter_read_val_reg[8]_29 )); LUT4 #( .INIT(16'hFFFE)) phy_if_reset0 (.I0(reset_if), .I1(phy_if_reset_w), .I2(mpr_end_if_reset), .I3(wrlvl_final_if_rst), .O(phy_if_reset0__0)); FDRE phy_if_reset_reg (.C(CLK), .CE(1'b1), .D(phy_if_reset0__0), .Q(phy_if_reset), .R(1'b0)); LUT6 #( .INIT(64'h0000000000400000)) pi_cnt_dec_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ), .I1(wait_cnt_r_reg__0[0]), .I2(dqs_po_dec_done_r2), .I3(wait_cnt_r_reg__0[1]), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ), .I5(rstdiv0_sync_r1_reg_rep__23), .O(pi_cnt_dec_i_1_n_0)); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \pi_dqs_found_any_bank[0]_i_1 (.I0(p_3_in25_in), .I1(p_2_in24_in), .I2(p_0_in23_in), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ), .I4(u_ddr_phy_init_n_502), .I5(pi_dqs_found_any_bank), .O(\pi_dqs_found_any_bank[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair726" *) LUT3 #( .INIT(8'h08)) pi_stg2_f_incdec_timing_i_1 (.I0(prbs_tap_inc_r), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ), .I2(rstdiv0_sync_r1_reg_rep__23), .O(pi_stg2_f_incdec_timing_i_1_n_0)); LUT3 #( .INIT(8'h04)) pi_stg2_load_timing_i_1 (.I0(regl_dqs_cnt), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ), .O(pi_stg2_load_timing_i_1_n_0)); LUT6 #( .INIT(64'h0000000000800000)) po_cnt_dec_i_1 (.I0(wait_cnt_r_reg__0_1), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ), .I4(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ), .I5(rstdiv0_sync_r1_reg_rep__25), .O(po_cnt_dec_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair723" *) LUT3 #( .INIT(8'h04)) po_cnt_dec_i_1__0 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ), .I2(rstdiv0_sync_r1_reg_rep__23), .O(po_cnt_dec_i_1__0_n_0)); LUT5 #( .INIT(32'h00000020)) po_cnt_inc_i_1 (.I0(wait_cnt_r_reg__0_1), .I1(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ), .I2(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ), .I3(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ), .I4(rstdiv0_sync_r1_reg_rep__24), .O(po_cnt_inc_i_1_n_0)); LUT4 #( .INIT(16'hFFFE)) po_en_stg2_f0 (.I0(ck_po_stg2_f_en), .I1(dqs_po_en_stg2_f), .I2(cmd_po_en_stg2_f), .I3(po_en_stg23), .O(po_enstg2_f)); LUT3 #( .INIT(8'hFE)) po_stg2_f_incdec0 (.I0(ck_po_stg2_f_indec), .I1(dqs_po_stg2_f_incdec), .I2(po_stg23_incdec), .O(po_stg2_fincdec)); LUT2 #( .INIT(4'h6)) \prbs_dqs_cnt_r[0]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .O(\prbs_dqs_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair719" *) LUT3 #( .INIT(8'h78)) \prbs_dqs_cnt_r[1]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .O(\prbs_dqs_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair719" *) LUT4 #( .INIT(16'h7F80)) \prbs_dqs_cnt_r[2]_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ), .O(\prbs_dqs_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair726" *) LUT3 #( .INIT(8'h02)) prbs_dqs_tap_limit_r_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ), .O(prbs_dqs_tap_limit_r_i_1_n_0)); LUT6 #( .INIT(64'hF2FFFFFF02000000)) prbs_found_1st_edge_r_i_1 (.I0(prbs_state_r178_out), .I1(prbs_state_r[3]), .I2(prbs_state_r[0]), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ), .O(prbs_found_1st_edge_r_i_1_n_0)); LUT6 #( .INIT(64'hDFDFF5F502000000)) prbs_last_byte_done_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I1(prbs_state_r[0]), .I2(prbs_state_r[1]), .I3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ), .I4(prbs_state_r[3]), .I5(prbs_last_byte_done), .O(prbs_last_byte_done_i_1_n_0)); LUT6 #( .INIT(64'hFFF337F300000400)) prbs_prech_req_r_i_1 (.I0(prech_done), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ), .I2(prbs_state_r[1]), .I3(prbs_state_r[3]), .I4(prbs_state_r[0]), .I5(prbs_prech_req_r), .O(prbs_prech_req_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFF7FFF00004000)) prbs_rdlvl_done_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ), .I2(prbs_state_r[3]), .I3(prbs_state_r[1]), .I4(prbs_state_r[2]), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .O(prbs_rdlvl_done_i_1_n_0)); LUT6 #( .INIT(64'hA8AAFFFFA8AA0000)) prbs_tap_en_r_i_1 (.I0(prbs_state_r[0]), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ), .I2(prbs_state_r[1]), .I3(prbs_state_r[3]), .I4(prbs_tap_en_r), .I5(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ), .O(prbs_tap_en_r_i_1_n_0)); LUT6 #( .INIT(64'h8A00FFFF8A000000)) prbs_tap_inc_r_i_1 (.I0(prbs_state_r[0]), .I1(prbs_state_r[1]), .I2(prbs_state_r[3]), .I3(prbs_state_r[2]), .I4(prbs_tap_en_r), .I5(prbs_tap_inc_r), .O(prbs_tap_inc_r_i_1_n_0)); LUT3 #( .INIT(8'hBA)) prech_pending_r_i_1 (.I0(u_ddr_phy_init_n_9), .I1(u_ddr_phy_init_n_468), .I2(prech_pending_r), .O(prech_pending_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000707070)) rank_done_r_i_1 (.I0(pi_dqs_found_all_bank_r[1]), .I1(pi_dqs_found_all_bank_r[0]), .I2(p_1_in27_in), .I3(rd_data_offset_cal_done), .I4(\rd_byte_data_offset_reg[0]_3 ), .I5(rstdiv0_sync_r1_reg_rep__24), .O(rank_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair723" *) LUT3 #( .INIT(8'hFE)) \rd_addr[7]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(complex_ocal_reset_rd_addr), .I2(reset_rd_addr), .O(\rd_addr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair718" *) LUT4 #( .INIT(16'h8F80)) rdlvl_last_byte_done_int_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ), .I3(rdlvl_last_byte_done), .O(rdlvl_last_byte_done_int_i_1_n_0)); LUT5 #( .INIT(32'h70FF7000)) rdlvl_pi_incdec_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ), .I4(rdlvl_pi_incdec), .O(rdlvl_pi_incdec_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFC8C00000080)) rdlvl_rank_done_r_i_1 (.I0(cal1_cnt_cpt_r1), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ), .I4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ), .I5(rdlvl_stg1_rank_done), .O(rdlvl_rank_done_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00010000)) rdlvl_start_pre_i_1 (.I0(u_ddr_phy_init_n_102), .I1(u_ddr_phy_init_n_469), .I2(u_ddr_phy_init_n_108), .I3(u_ddr_phy_init_n_107), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .I5(rdlvl_start_pre), .O(rdlvl_start_pre_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair731" *) LUT3 #( .INIT(8'hB8)) rdlvl_stg1_done_int_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .I1(rdlvl_stg1_done_int), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .O(rdlvl_stg1_done_int_i_1_n_0)); LUT6 #( .INIT(64'hFFFEFFFF00020000)) rdlvl_stg1_start_i_1 (.I0(rdlvl_start_dly0_r), .I1(u_ddr_phy_init_n_473), .I2(u_ddr_phy_init_n_108), .I3(u_ddr_phy_init_n_107), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .I5(u_ddr_phy_init_n_33), .O(rdlvl_stg1_start_i_1_n_0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 " *) SRL16E reset_if_r8_reg_srl8 (.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(reset_if), .Q(reset_if_r8_reg_srl8_n_0)); FDRE reset_if_r9_reg (.C(CLK), .CE(1'b1), .D(reset_if_r8_reg_srl8_n_0), .Q(reset_if_r9), .R(1'b0)); FDRE reset_if_reg (.C(CLK), .CE(1'b1), .D(u_ddr_phy_init_n_101), .Q(reset_if), .R(1'b0)); LUT6 #( .INIT(64'hFFEFFEFF00000010)) reset_rd_addr_i_1 (.I0(prbs_state_r[4]), .I1(prbs_state_r[2]), .I2(prbs_state_r[3]), .I3(prbs_state_r[0]), .I4(prbs_state_r[1]), .I5(reset_rd_addr), .O(reset_rd_addr_i_1_n_0)); LUT5 #( .INIT(32'h04FF0400)) right_edge_found_i_1 (.I0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ), .I1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ), .I2(prbs_state_r[4]), .I3(right_edge_found), .I4(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ), .O(right_edge_found_i_1_n_0)); LUT5 #( .INIT(32'hBABF8A80)) rst_dqs_find_i_1 (.I0(rst_dqs_find), .I1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_111 ), .I2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ), .I3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_109 ), .I4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ), .O(rst_dqs_find_i_1_n_0)); LUT4 #( .INIT(16'hABAA)) store_sr_r_i_1 (.I0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ), .I1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ), .I2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ), .I3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ), .O(store_sr_r_i_1_n_0)); FDRE tempmon_pi_f_en_r_reg (.C(CLK), .CE(1'b1), .D(tempmon_sel_pi_incdec), .Q(tempmon_pi_f_en_r), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE tempmon_pi_f_inc_r_reg (.C(CLK), .CE(1'b1), .D(tempmon_pi_f_inc), .Q(tempmon_pi_f_inc_r), .R(rstdiv0_sync_r1_reg_rep__9)); ddr3_if_mig_7series_v4_0_ddr_phy_init u_ddr_phy_init (.A_rst_primitives_reg(A_rst_primitives_reg), .CLK(CLK), .D({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }), .D0(D0[1]), .D1(D1[1]), .D2(D2[1]), .D3(D3[1]), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8), .D9(D9), .E(u_ddr_phy_init_n_465), .Q({init_state_r,u_ddr_phy_init_n_104,u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}), .\back_to_back_reads_4_1.num_reads_reg[0]_0 (u_ddr_phy_init_n_473), .\back_to_back_reads_4_1.num_reads_reg[1]_0 (u_ddr_phy_init_n_474), .burst_addr_r_reg_0(u_ddr_phy_init_n_31), .burst_addr_r_reg_1(u_ddr_phy_init_n_476), .burst_addr_r_reg_2(burst_addr_r_i_1_n_0), .cal1_state_r1535_out(cal1_state_r1535_out), .calib_complete(calib_complete), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .\cmd_pipe_plus.mc_address_reg[42] ({\cmd_pipe_plus.mc_address_reg[44] [34:14],\cmd_pipe_plus.mc_address_reg[44] [12:0]}), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5]_0 ), .cnt_cmd_done_r(cnt_cmd_done_r), .cnt_cmd_done_r_reg_0(ddr2_refresh_flag_r_i_1_n_0), .cnt_cmd_done_r_reg_1(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ), .cnt_dllk_zqinit_done_r(cnt_dllk_zqinit_done_r), .cnt_dllk_zqinit_done_r_reg_0(cnt_dllk_zqinit_done_r_i_1_n_0), .cnt_init_af_done_r(cnt_init_af_done_r), .cnt_init_af_done_r_reg_0(cnt_init_af_done_r_i_1_n_0), .cnt_init_af_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ), .cnt_init_af_r(cnt_init_af_r), .cnt_init_mr_done_r(cnt_init_mr_done_r), .cnt_init_mr_done_r_reg_0(cnt_init_mr_done_r_i_1_n_0), .cnt_init_mr_r(cnt_init_mr_r), .cnt_init_mr_r1(cnt_init_mr_r1), .\cnt_init_mr_r_reg[1]_0 (u_ddr_phy_init_n_110), .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r), .cnt_pwron_cke_done_r_reg_0(u_ddr_phy_init_n_490), .cnt_pwron_cke_done_r_reg_1(cnt_pwron_cke_done_r_i_1_n_0), .\cnt_pwron_r_reg[7]_0 ({cnt_pwron_r_reg__0[7],cnt_pwron_r_reg__0[5],cnt_pwron_r_reg__0[1:0]}), .\cnt_pwron_r_reg[7]_1 (cnt_pwron_reset_done_r_i_1_n_0), .cnt_pwron_reset_done_r(cnt_pwron_reset_done_r), .cnt_pwron_reset_done_r_reg_0(u_ddr_phy_init_n_485), .\cnt_shift_r_reg[0] (cnt_shift_r0), .\cnt_shift_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ), .cnt_txpr_done_r(cnt_txpr_done_r), .cnt_txpr_done_r_reg_0(u_ddr_phy_init_n_500), .cnt_txpr_done_r_reg_1(cnt_txpr_done_r_i_1_n_0), .\cnt_txpr_r_reg[2]_0 (cnt_txpr_r_reg__0), .complex_act_start(complex_act_start), .complex_init_pi_dec_done(complex_init_pi_dec_done), .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r), .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel), .complex_ocal_ref_req(complex_ocal_ref_req), .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr), .complex_oclk_calib_resume(complex_oclk_calib_resume), .complex_oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_114), .complex_pi_incdec_done(complex_pi_incdec_done), .\complex_row_cnt_ocal_reg[0]_0 (\complex_row_cnt_ocal_reg[0] ), .complex_victim_inc_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ), .\data_offset_1_i1_reg[5] (\data_offset_1_i1_reg[5] ), .ddr2_pre_flag_r_reg_0(u_ddr_phy_init_n_29), .ddr2_pre_flag_r_reg_1(u_ddr_phy_init_n_479), .ddr2_pre_flag_r_reg_2(ddr2_pre_flag_r_i_1_n_0), .ddr2_refresh_flag_r(ddr2_refresh_flag_r), .ddr2_refresh_flag_r_reg_0(u_ddr_phy_init_n_480), .ddr3_lm_done_r(ddr3_lm_done_r), .delay_done_r4_reg(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ), .detect_pi_found_dqs(detect_pi_found_dqs), .done_dqs_tap_inc(done_dqs_tap_inc), .done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ), .\dout_o_reg[0] (u_ddr_prbs_gen_n_120), .\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_116), .\dout_o_reg[10] (u_ddr_prbs_gen_n_6), .\dout_o_reg[10]_0 (u_ddr_prbs_gen_n_5), .\dout_o_reg[11] (u_ddr_prbs_gen_n_41), .\dout_o_reg[11]_0 (u_ddr_prbs_gen_n_42), .\dout_o_reg[11]_1 (u_ddr_prbs_gen_n_51), .\dout_o_reg[11]_2 (u_ddr_prbs_gen_n_52), .\dout_o_reg[11]_3 (u_ddr_prbs_gen_n_16), .\dout_o_reg[11]_4 (u_ddr_prbs_gen_n_15), .\dout_o_reg[12] (u_ddr_prbs_gen_n_2), .\dout_o_reg[12]_0 (u_ddr_prbs_gen_n_1), .\dout_o_reg[13] (u_ddr_prbs_gen_n_53), .\dout_o_reg[13]_0 (u_ddr_prbs_gen_n_54), .\dout_o_reg[13]_1 (u_ddr_prbs_gen_n_28), .\dout_o_reg[13]_2 (u_ddr_prbs_gen_n_27), .\dout_o_reg[13]_3 (u_ddr_prbs_gen_n_18), .\dout_o_reg[13]_4 (u_ddr_prbs_gen_n_17), .\dout_o_reg[13]_5 (u_ddr_prbs_gen_n_14), .\dout_o_reg[13]_6 (u_ddr_prbs_gen_n_13), .\dout_o_reg[14] (u_ddr_prbs_gen_n_46), .\dout_o_reg[14]_0 (u_ddr_prbs_gen_n_45), .\dout_o_reg[14]_1 (u_ddr_prbs_gen_n_44), .\dout_o_reg[14]_2 (u_ddr_prbs_gen_n_43), .\dout_o_reg[15] (u_ddr_prbs_gen_n_12), .\dout_o_reg[15]_0 (u_ddr_prbs_gen_n_11), .\dout_o_reg[15]_1 (u_ddr_prbs_gen_n_10), .\dout_o_reg[15]_2 (u_ddr_prbs_gen_n_9), .\dout_o_reg[1] (u_ddr_prbs_gen_n_19), .\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_20), .\dout_o_reg[2] (u_ddr_prbs_gen_n_105), .\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_101), .\dout_o_reg[3] (u_ddr_prbs_gen_n_21), .\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_22), .\dout_o_reg[4] (u_ddr_prbs_gen_n_88), .\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_84), .\dout_o_reg[6] (u_ddr_prbs_gen_n_56), .\dout_o_reg[7] (u_ddr_prbs_gen_n_24), .\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_23), .\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_25), .\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_26), .\dout_o_reg[8] (u_ddr_prbs_gen_n_48), .\dout_o_reg[8]_0 (u_ddr_prbs_gen_n_47), .\dout_o_reg[8]_1 (u_ddr_prbs_gen_n_8), .\dout_o_reg[8]_2 (u_ddr_prbs_gen_n_7), .\dout_o_reg[8]_3 (u_ddr_prbs_gen_n_4), .\dout_o_reg[8]_4 (u_ddr_prbs_gen_n_3), .\dout_o_reg[9] (u_ddr_prbs_gen_n_49), .\dout_o_reg[9]_0 (u_ddr_prbs_gen_n_50), .\dout_o_reg[9]_1 (u_ddr_prbs_gen_n_38), .\dout_o_reg[9]_2 (u_ddr_prbs_gen_n_37), .\dout_o_reg[9]_3 (u_ddr_prbs_gen_n_36), .\dout_o_reg[9]_4 (u_ddr_prbs_gen_n_35), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .dqs_found_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ), .dqs_found_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ), .dqs_found_done_r_reg_2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ), .dqs_found_prech_req(dqs_found_prech_req), .dqs_found_start_r_reg(u_ddr_phy_init_n_502), .\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .first_rdlvl_pat_r(first_rdlvl_pat_r), .first_rdlvl_pat_r_reg_0(u_ddr_prbs_gen_n_55), .first_wrcal_pat_r(first_wrcal_pat_r), .in0(init_complete_r_timing_orig), .init_calib_complete_reg_rep(\my_empty_reg[7] ), .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0_n_0), .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1_n_0), .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10_n_0), .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11_n_0), .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12_n_0), .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13_n_0), .init_calib_complete_reg_rep__14(init_calib_complete_r_reg), .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2_n_0), .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3_n_0), .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4_n_0), .init_calib_complete_reg_rep__5(\rd_ptr_timing_reg[0] ), .init_calib_complete_reg_rep__6(app_zq_r_reg), .init_calib_complete_reg_rep__7(\my_empty_reg[7]_0 ), .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8_n_0), .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_n_0), .init_complete_r1_reg_0(u_ddr_phy_init_n_18), .init_dqsfound_done_r2(init_dqsfound_done_r2), .\init_state_r_reg[0]_0 (u_ddr_phy_init_n_497), .\init_state_r_reg[0]_1 (rdlvl_start_pre_i_1_n_0), .\init_state_r_reg[1]_0 (u_ddr_phy_init_n_111), .\init_state_r_reg[1]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ), .\init_state_r_reg[2]_0 (u_ddr_phy_init_n_117), .\init_state_r_reg[2]_1 (u_ddr_phy_init_n_499), .\init_state_r_reg[2]_2 (\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ), .\init_state_r_reg[4]_0 (u_ddr_phy_init_n_475), .\init_state_r_reg[5]_0 (u_ddr_phy_init_n_478), .\init_state_r_reg[6]_0 (init_complete_r_i_1_n_0), .\init_state_r_reg[6]_1 (init_complete_r_timing_i_1_n_0), .lim2init_prech_req(lim2init_prech_req), .lim_start_r_reg(u_ddr_phy_init_n_462), .\mcGo_r_reg[15] (\mcGo_r_reg[15] ), .mc_cas_n(mc_cas_n[1]), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n[1]), .mc_we_n(mc_we_n[1]), .mc_wrdata_en(mc_wrdata_en), .mem_init_done_r(mem_init_done_r), .mem_init_done_r_reg_0(cnt_dllk_zqinit_r_reg__0), .mem_init_done_r_reg_1(u_ddr_phy_init_n_496), .mem_init_done_r_reg_2(u_ddr_phy_wrcal_n_92), .mem_out({mem_out[4],mem_out[1]}), .mpr_end_if_reset(mpr_end_if_reset), .mpr_last_byte_done(mpr_last_byte_done), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .mpr_rdlvl_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ), .mpr_rdlvl_done_r_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ), .mpr_rdlvl_done_r_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ), .mpr_rdlvl_start_r(mpr_rdlvl_start_r), .mpr_rdlvl_start_r_reg(u_ddr_phy_init_n_464), .mux_cmd_wren(mux_cmd_wren), .mux_reset_n(mux_reset_n), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ), .\my_empty_reg[1]_3 (\my_empty_reg[1]_3 ), .\my_empty_reg[1]_4 (\my_empty_reg[1]_4 ), .\my_empty_reg[1]_5 (\my_empty_reg[1]_5 ), .\my_empty_reg[1]_6 (\my_empty_reg[1]_6 ), .\my_empty_reg[7] (\my_empty_reg[7]_5 ), .\my_empty_reg[7]_0 (\my_empty_reg[7]_6 ), .\my_empty_reg[7]_1 (\my_empty_reg[7]_7 ), .\my_empty_reg[7]_10 (\my_empty_reg[7]_16 ), .\my_empty_reg[7]_11 (\my_empty_reg[7]_17 ), .\my_empty_reg[7]_12 (\my_empty_reg[7]_18 ), .\my_empty_reg[7]_13 (\my_empty_reg[7]_19 ), .\my_empty_reg[7]_14 (\my_empty_reg[7]_20 ), .\my_empty_reg[7]_15 (\my_empty_reg[7]_21 ), .\my_empty_reg[7]_16 (\my_empty_reg[7]_22 ), .\my_empty_reg[7]_17 (\my_empty_reg[7]_23 ), .\my_empty_reg[7]_18 (\my_empty_reg[7]_24 ), .\my_empty_reg[7]_19 (\my_empty_reg[7]_25 ), .\my_empty_reg[7]_2 (\my_empty_reg[7]_8 ), .\my_empty_reg[7]_20 (\my_empty_reg[7]_26 ), .\my_empty_reg[7]_21 (\my_empty_reg[7]_27 ), .\my_empty_reg[7]_22 (\my_empty_reg[7]_28 ), .\my_empty_reg[7]_23 (\my_empty_reg[7]_29 ), .\my_empty_reg[7]_24 (\my_empty_reg[7]_30 ), .\my_empty_reg[7]_25 (\my_empty_reg[7]_31 ), .\my_empty_reg[7]_26 (\my_empty_reg[7]_32 ), .\my_empty_reg[7]_27 (\my_empty_reg[7]_33 ), .\my_empty_reg[7]_28 (\my_empty_reg[7]_34 ), .\my_empty_reg[7]_29 (\my_empty_reg[7]_35 ), .\my_empty_reg[7]_3 (\my_empty_reg[7]_9 ), .\my_empty_reg[7]_30 (\my_empty_reg[7]_36 ), .\my_empty_reg[7]_31 (\my_empty_reg[7]_37 ), .\my_empty_reg[7]_32 (\my_empty_reg[7]_38 ), .\my_empty_reg[7]_33 (\my_empty_reg[7]_39 ), .\my_empty_reg[7]_34 (\my_empty_reg[7]_40 ), .\my_empty_reg[7]_35 (\my_empty_reg[7]_41 ), .\my_empty_reg[7]_36 (\my_empty_reg[7]_42 ), .\my_empty_reg[7]_37 (\my_empty_reg[7]_43 ), .\my_empty_reg[7]_38 (\my_empty_reg[7]_1 [63:0]), .\my_empty_reg[7]_39 (\my_empty_reg[7]_2 [63:0]), .\my_empty_reg[7]_4 (\my_empty_reg[7]_10 ), .\my_empty_reg[7]_40 (\my_empty_reg[7]_3 [63:0]), .\my_empty_reg[7]_41 (\my_empty_reg[7]_4 [63:0]), .\my_empty_reg[7]_5 (\my_empty_reg[7]_11 ), .\my_empty_reg[7]_6 (\my_empty_reg[7]_12 ), .\my_empty_reg[7]_7 (\my_empty_reg[7]_13 ), .\my_empty_reg[7]_8 (\my_empty_reg[7]_14 ), .\my_empty_reg[7]_9 (\my_empty_reg[7]_15 ), .\my_full_reg[3] (\my_full_reg[3]_0 ), .new_cnt_dqs_r_reg(u_ddr_phy_init_n_127), .num_samples_done_r(num_samples_done_r), .ocal_last_byte_done(ocal_last_byte_done), .ocd_prech_req(ocd_prech_req), .oclk_calib_resume_level_reg_0(u_ddr_phy_init_n_102), .oclk_calib_resume_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ), .oclk_calib_resume_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ), .oclkdelay_calib_done_r_reg(u_ddr_prbs_gen_n_40), .oclkdelay_calib_done_r_reg_0(u_ddr_prbs_gen_n_39), .oclkdelay_calib_done_r_reg_1(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ), .oclkdelay_calib_done_r_reg_2(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_calib_done_r_reg_3(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ), .oclkdelay_calib_done_r_reg_4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ), .oclkdelay_calib_done_r_reg_5(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ), .oclkdelay_center_calib_done_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .oclkdelay_center_calib_start_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ), .oclkdelay_center_calib_start_r_reg_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ), .oclkdelay_int_ref_req_reg_0(u_ddr_phy_init_n_477), .\oclkdelay_ref_cnt_reg[13]_0 (u_ddr_phy_init_n_24), .\odd_cwl.phy_cas_n_reg[1]_0 (u_ddr_phy_init_n_109), .\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_116), .out(out), .p_81_in(p_81_in), .\phy_ctl_wd_i1_reg[24] (\phy_ctl_wd_i1_reg[24] ), .phy_dout(phy_dout[31:0]), .phy_if_empty_r_reg(u_ddr_prbs_gen_n_0), .phy_rddata_en_1(phy_rddata_en_1), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .pi_calib_done(pi_calib_done), .\pi_dqs_found_all_bank_reg[1] (u_ddr_phy_init_n_501), .\pi_dqs_found_all_bank_reg[1]_0 (pi_dqs_found_all_bank), .pi_dqs_found_done_r1(pi_dqs_found_done_r1), .pi_dqs_found_done_r1_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ), .pi_dqs_found_done_r1_reg_1(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ), .pi_dqs_found_done_r1_reg_2(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ), .pi_dqs_found_done_r1_reg_3(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ), .pi_dqs_found_done_r1_reg_4(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ), .pi_dqs_found_done_r1_reg_5(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_95 ), .pi_dqs_found_done_r1_reg_6(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ), .pi_dqs_found_done_r1_reg_7(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .prbs_last_byte_done(prbs_last_byte_done), .prbs_last_byte_done_r(prbs_last_byte_done_r), .prbs_last_byte_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ), .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0), .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prbs_rdlvl_done_reg_rep_0(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ), .prbs_rdlvl_done_reg_rep_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ), .prbs_rdlvl_done_reg_rep_2(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ), .prbs_rdlvl_done_reg_rep_3(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ), .prbs_rdlvl_prech_req_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ), .prbs_rdlvl_start_r(prbs_rdlvl_start_r), .prbs_rdlvl_start_r_reg(prbs_rdlvl_start_r_reg), .prech_done(prech_done), .prech_pending_r(prech_pending_r), .prech_pending_r_reg_0(u_ddr_phy_init_n_9), .prech_pending_r_reg_1(u_ddr_phy_init_n_468), .prech_req(prech_req), .prech_req_posedge_r_reg_0(prech_pending_r_i_1_n_0), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] (rd_data_offset_ranks_0), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (rd_data_offset_ranks_1), .\rd_addr_reg[0] (u_ddr_phy_init_n_786), .\rd_addr_reg[3] (u_ddr_prbs_gen_n_57), .\rd_addr_reg_rep[7] (u_ddr_phy_init_n_785), .\rd_byte_data_offset_reg[0][3] ({\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_73 ,\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 }), .\rd_byte_data_offset_reg[0][9] (p_0_in_0), .\rd_ptr_reg[3] ({\rd_ptr_reg[3] [37:6],\rd_ptr_reg[3] [4],\rd_ptr_reg[3] [1]}), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 [11:4]), .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ), .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_2 ), .\rd_ptr_reg[3]_3 (\rd_ptr_reg[3]_3 ), .\rd_ptr_reg[3]_4 (\rd_ptr_reg[3]_4 ), .\rd_ptr_reg[3]_5 (\rd_ptr_reg[3]_5 ), .\rd_ptr_timing_reg[0] (\rd_ptr_timing_reg[0]_0 ), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0]_1 ), .\rd_ptr_timing_reg[0]_1 (\rd_ptr_timing_reg[0]_2 ), .\rd_ptr_timing_reg[0]_2 (\rd_ptr_timing_reg[0]_3 ), .\rd_ptr_timing_reg[0]_3 (\rd_ptr_timing_reg[0]_4 ), .\rd_victim_sel_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ), .\rd_victim_sel_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ), .\rd_victim_sel_reg[2] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ), .rdlvl_last_byte_done(rdlvl_last_byte_done), .rdlvl_pi_incdec(rdlvl_pi_incdec), .rdlvl_prech_req(rdlvl_prech_req), .rdlvl_start_dly0_r(rdlvl_start_dly0_r), .\rdlvl_start_dly0_r_reg[14]_0 (rdlvl_stg1_start_i_1_n_0), .rdlvl_start_pre(rdlvl_start_pre), .rdlvl_start_pre_reg_0(u_ddr_phy_init_n_469), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_done_int_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ), .rdlvl_stg1_done_int_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ), .rdlvl_stg1_done_int_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ), .rdlvl_stg1_done_int_reg_3(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ), .rdlvl_stg1_done_int_reg_4(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ), .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done), .rdlvl_stg1_start_int(rdlvl_stg1_start_int), .rdlvl_stg1_start_r_reg(u_ddr_phy_init_n_33), .read_calib_reg_0(u_ddr_phy_init_n_470), .\reg_ctrl_cnt_r_reg[3]_0 (u_ddr_phy_init_n_115), .reset_if(reset_if), .reset_if_r9(reset_if_r9), .reset_if_reg(u_ddr_phy_init_n_101), .reset_rd_addr(reset_rd_addr), .reset_rd_addr0(reset_rd_addr0), .\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0), .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .\samples_cnt_r_reg[11] (samples_cnt_r), .\samples_cnt_r_reg[11]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ), .stg1_wr_done(stg1_wr_done), .temp_lmr_done(temp_lmr_done), .\victim_sel_rotate.sel_reg[31] ({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}), .wl_sm_start(wl_sm_start), .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ), .wr_level_start_r_reg(u_ddr_phy_init_n_790), .wrcal_done_reg(u_ddr_phy_wrcal_n_103), .wrcal_done_reg_0(u_ddr_phy_wrcal_n_83), .wrcal_done_reg_1(u_ddr_phy_wrcal_n_84), .wrcal_done_reg_10(u_ddr_phy_wrcal_n_82), .wrcal_done_reg_11(u_ddr_phy_wrcal_n_81), .wrcal_done_reg_2(u_ddr_phy_wrcal_n_104), .wrcal_done_reg_3(u_ddr_prbs_gen_n_34), .wrcal_done_reg_4(u_ddr_prbs_gen_n_33), .wrcal_done_reg_5(u_ddr_prbs_gen_n_32), .wrcal_done_reg_6(u_ddr_prbs_gen_n_31), .wrcal_done_reg_7(u_ddr_prbs_gen_n_30), .wrcal_done_reg_8(u_ddr_prbs_gen_n_29), .wrcal_done_reg_9(u_ddr_phy_wrcal_n_93), .\wrcal_dqs_cnt_r_reg[0] (u_ddr_phy_init_n_784), .wrcal_prech_req(wrcal_prech_req), .wrcal_rd_wait(wrcal_rd_wait), .wrcal_resume_r(wrcal_resume_r), .wrcal_resume_w(wrcal_resume_w), .wrcal_sanity_chk(wrcal_sanity_chk), .wrcal_sanity_chk_done_reg(u_ddr_phy_wrcal_n_96), .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71), .wrcal_sanity_chk_r_reg(u_ddr_phy_wrcal_n_5), .wrcal_start_reg_0(u_ddr_phy_init_n_791), .\write_buffer.wr_buf_out_data_reg[255] (Q[255:0]), .write_request_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95), .wrlvl_byte_redo_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_final_if_rst(wrlvl_final_if_rst), .wrlvl_final_mux(wrlvl_final_mux), .wrlvl_final_mux_reg(u_ddr_phy_wrcal_n_90), .wrlvl_final_mux_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ), .wrlvl_rank_done(wrlvl_rank_done)); ddr3_if_mig_7series_v4_0_ddr_phy_wrcal u_ddr_phy_wrcal (.CLK(CLK), .\FSM_sequential_wl_state_r_reg[0] (u_ddr_phy_wrcal_n_102), .LD0(LD0), .LD0_0(LD0_0), .LD0_1(LD0_1), .LD0_2(LD0_2), .Q(calib_zero_inputs__0), .cal2_done_r(cal2_done_r), .cal2_done_r_reg_0(u_ddr_phy_wrcal_n_117), .cal2_if_reset_reg_0(u_ddr_phy_wrcal_n_114), .cal2_if_reset_reg_1(u_ddr_phy_wrcal_n_115), .cal2_if_reset_reg_2(u_ddr_phy_wrcal_n_120), .\cal2_state_r_reg[0]_0 (idelay_ld_done_i_1_n_0), .\cal2_state_r_reg[0]_1 (cal2_if_reset_i_1_n_0), .\cal2_state_r_reg[2]_0 (wrcal_pat_resume_r_i_1_n_0), .\cal2_state_r_reg[3]_0 (wrcal_sanity_chk_done_i_1_n_0), .calib_in_common(calib_in_common), .\calib_sel_reg[1] (\po_rdval_cnt_reg[8] [1:0]), .\corse_cnt_reg[0][2] (u_ddr_phy_wrcal_n_100), .\corse_cnt_reg[1][2] (u_ddr_phy_wrcal_n_97), .\corse_cnt_reg[2][2] (u_ddr_phy_wrcal_n_98), .ddr3_lm_done_r(ddr3_lm_done_r), .done_dqs_dec239_out(done_dqs_dec239_out), .dqs_found_done_r_reg(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ), .dqs_found_done_r_reg_0(\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ), .early1_data_reg_0(u_ddr_phy_wrcal_n_67), .early1_data_reg_1(u_ddr_phy_wrcal_n_73), .early1_data_reg_2(u_ddr_phy_wrcal_n_119), .early2_data_reg_0(u_ddr_phy_wrcal_n_66), .early2_data_reg_1(u_ddr_phy_wrcal_n_74), .\final_coarse_tap_reg[3][2] (final_coarse_tap), .first_wrcal_pat_r(first_wrcal_pat_r), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_phy_wrcal_n_105), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (u_ddr_phy_wrcal_n_106), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_phy_wrcal_n_107), .\gen_pat_match_div4.early1_data_match_r_reg_0 (early1_data_i_1_n_0), .\gen_pat_match_div4.early1_data_match_r_reg_1 (early2_data_i_1_n_0), .\gen_pat_match_div4.early2_data_match_r_reg_0 (wrlvl_byte_redo_i_1_n_0), .\gen_pat_match_div4.pat_data_match_valid_r_reg_0 (idelay_ld_i_1_n_0), .\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 (\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 (\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 (\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 (\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 (\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 (\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 (\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ), .\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 (\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 (\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 (\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 (\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 (\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 (\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 (\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 (\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 (\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ), .\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 (\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 (\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 (\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 (\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 (\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 (\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 (\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 (\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 (\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ), .\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 (\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 (\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 (\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 (\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 (\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ), .\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 (\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 (\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ), .\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 (\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 (\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 (\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 (\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 (\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 (\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 (\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 (\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ), .\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 (\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 (\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 (\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 (\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 (\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 (\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 (\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 (\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 (\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ), .\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 (\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 (\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 (\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 (\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 (\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 (\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 (\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 (\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 (\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ), .\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 (\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 (\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 (\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 (\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 (\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ), .\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 (\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 (\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ), .\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 (\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .idelay_ce_int(idelay_ce_int), .idelay_ld(idelay_ld), .idelay_ld_done_reg_0(u_ddr_phy_wrcal_n_113), .idelay_ld_reg_0(u_ddr_phy_wrcal_n_4), .idelay_ld_reg_1(u_ddr_phy_wrcal_n_116), .idelay_ld_rst(idelay_ld_rst), .idelay_ld_rst_3(idelay_ld_rst_3), .idelay_ld_rst_4(idelay_ld_rst_4), .idelay_ld_rst_5(idelay_ld_rst_5), .\idelay_tap_cnt_r_reg[0][1][0] (u_ddr_phy_wrcal_n_89), .\idelay_tap_cnt_r_reg[0][2][0] (u_ddr_phy_wrcal_n_85), .\idelay_tap_cnt_r_reg[0][2][0]_0 ({po_stg2_wrcal_cnt,\idelay_tap_cnt_r_reg[0][3][0] }), .\init_state_r_reg[0] (u_ddr_phy_wrcal_n_90), .\init_state_r_reg[0]_0 (u_ddr_phy_wrcal_n_93), .\init_state_r_reg[0]_1 (u_ddr_phy_wrcal_n_94), .\init_state_r_reg[0]_2 (u_ddr_phy_wrcal_n_96), .\init_state_r_reg[2] (u_ddr_phy_wrcal_n_91), .\init_state_r_reg[3] (u_ddr_phy_wrcal_n_81), .\init_state_r_reg[4] (u_ddr_phy_wrcal_n_92), .\init_state_r_reg[5] (u_ddr_phy_wrcal_n_95), .mem_init_done_r(mem_init_done_r), .mpr_last_byte_done(mpr_last_byte_done), .mpr_rdlvl_done_r_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ), .\not_empty_wait_cnt_reg[0]_0 ({u_ddr_phy_wrcal_n_108,u_ddr_phy_wrcal_n_109,u_ddr_phy_wrcal_n_110,u_ddr_phy_wrcal_n_111}), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .oclkdelay_calib_done_r_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ), .oclkdelay_center_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ), .p_0_out(p_0_out), .phy_if_reset_w(phy_if_reset_w), .phy_rddata_en_1(phy_rddata_en_1), .phy_rddata_en_r1_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ), .\po_stg2_wrcal_cnt_reg[1]_0 (\po_stg2_wrcal_cnt_reg[1] ), .\po_stg2_wrcal_cnt_reg[1]_1 (\po_stg2_wrcal_cnt_reg[1]_0 ), .\po_stg2_wrcal_cnt_reg[1]_10 (\po_stg2_wrcal_cnt_reg[1]_9 ), .\po_stg2_wrcal_cnt_reg[1]_11 (\po_stg2_wrcal_cnt_reg[1]_10 ), .\po_stg2_wrcal_cnt_reg[1]_12 (\po_stg2_wrcal_cnt_reg[1]_11 ), .\po_stg2_wrcal_cnt_reg[1]_13 (\po_stg2_wrcal_cnt_reg[1]_12 ), .\po_stg2_wrcal_cnt_reg[1]_14 (\po_stg2_wrcal_cnt_reg[1]_13 ), .\po_stg2_wrcal_cnt_reg[1]_15 (\po_stg2_wrcal_cnt_reg[1]_14 ), .\po_stg2_wrcal_cnt_reg[1]_16 (\po_stg2_wrcal_cnt_reg[1]_15 ), .\po_stg2_wrcal_cnt_reg[1]_17 (\po_stg2_wrcal_cnt_reg[1]_16 ), .\po_stg2_wrcal_cnt_reg[1]_18 (\po_stg2_wrcal_cnt_reg[1]_17 ), .\po_stg2_wrcal_cnt_reg[1]_19 (\po_stg2_wrcal_cnt_reg[1]_18 ), .\po_stg2_wrcal_cnt_reg[1]_2 (\po_stg2_wrcal_cnt_reg[1]_1 ), .\po_stg2_wrcal_cnt_reg[1]_20 (\po_stg2_wrcal_cnt_reg[1]_19 ), .\po_stg2_wrcal_cnt_reg[1]_21 (\po_stg2_wrcal_cnt_reg[1]_20 ), .\po_stg2_wrcal_cnt_reg[1]_22 (\po_stg2_wrcal_cnt_reg[1]_21 ), .\po_stg2_wrcal_cnt_reg[1]_23 (\po_stg2_wrcal_cnt_reg[1]_22 ), .\po_stg2_wrcal_cnt_reg[1]_24 (\po_stg2_wrcal_cnt_reg[1]_23 ), .\po_stg2_wrcal_cnt_reg[1]_25 (\po_stg2_wrcal_cnt_reg[1]_24 ), .\po_stg2_wrcal_cnt_reg[1]_26 (\po_stg2_wrcal_cnt_reg[1]_25 ), .\po_stg2_wrcal_cnt_reg[1]_27 (\po_stg2_wrcal_cnt_reg[1]_26 ), .\po_stg2_wrcal_cnt_reg[1]_28 (\po_stg2_wrcal_cnt_reg[1]_27 ), .\po_stg2_wrcal_cnt_reg[1]_29 (\po_stg2_wrcal_cnt_reg[1]_28 ), .\po_stg2_wrcal_cnt_reg[1]_3 (\po_stg2_wrcal_cnt_reg[1]_2 ), .\po_stg2_wrcal_cnt_reg[1]_30 (\po_stg2_wrcal_cnt_reg[1]_29 ), .\po_stg2_wrcal_cnt_reg[1]_31 (\po_stg2_wrcal_cnt_reg[1]_30 ), .\po_stg2_wrcal_cnt_reg[1]_32 (\po_stg2_wrcal_cnt_reg[1]_31 ), .\po_stg2_wrcal_cnt_reg[1]_33 (\po_stg2_wrcal_cnt_reg[1]_32 ), .\po_stg2_wrcal_cnt_reg[1]_34 (\po_stg2_wrcal_cnt_reg[1]_33 ), .\po_stg2_wrcal_cnt_reg[1]_35 (\po_stg2_wrcal_cnt_reg[1]_34 ), .\po_stg2_wrcal_cnt_reg[1]_36 (\po_stg2_wrcal_cnt_reg[1]_35 ), .\po_stg2_wrcal_cnt_reg[1]_37 (\po_stg2_wrcal_cnt_reg[1]_36 ), .\po_stg2_wrcal_cnt_reg[1]_38 (\po_stg2_wrcal_cnt_reg[1]_37 ), .\po_stg2_wrcal_cnt_reg[1]_39 (\po_stg2_wrcal_cnt_reg[1]_38 ), .\po_stg2_wrcal_cnt_reg[1]_4 (\po_stg2_wrcal_cnt_reg[1]_3 ), .\po_stg2_wrcal_cnt_reg[1]_40 (\po_stg2_wrcal_cnt_reg[1]_39 ), .\po_stg2_wrcal_cnt_reg[1]_41 (\po_stg2_wrcal_cnt_reg[1]_40 ), .\po_stg2_wrcal_cnt_reg[1]_42 (\po_stg2_wrcal_cnt_reg[1]_41 ), .\po_stg2_wrcal_cnt_reg[1]_43 (\po_stg2_wrcal_cnt_reg[1]_42 ), .\po_stg2_wrcal_cnt_reg[1]_44 (\po_stg2_wrcal_cnt_reg[1]_43 ), .\po_stg2_wrcal_cnt_reg[1]_45 (\po_stg2_wrcal_cnt_reg[1]_44 ), .\po_stg2_wrcal_cnt_reg[1]_46 (\po_stg2_wrcal_cnt_reg[1]_45 ), .\po_stg2_wrcal_cnt_reg[1]_47 (\po_stg2_wrcal_cnt_reg[1]_46 ), .\po_stg2_wrcal_cnt_reg[1]_48 (\po_stg2_wrcal_cnt_reg[1]_47 ), .\po_stg2_wrcal_cnt_reg[1]_49 (\po_stg2_wrcal_cnt_reg[1]_48 ), .\po_stg2_wrcal_cnt_reg[1]_5 (\po_stg2_wrcal_cnt_reg[1]_4 ), .\po_stg2_wrcal_cnt_reg[1]_50 (\po_stg2_wrcal_cnt_reg[1]_49 ), .\po_stg2_wrcal_cnt_reg[1]_51 (\po_stg2_wrcal_cnt_reg[1]_50 ), .\po_stg2_wrcal_cnt_reg[1]_52 (\po_stg2_wrcal_cnt_reg[1]_51 ), .\po_stg2_wrcal_cnt_reg[1]_53 (\po_stg2_wrcal_cnt_reg[1]_52 ), .\po_stg2_wrcal_cnt_reg[1]_54 (\po_stg2_wrcal_cnt_reg[1]_53 ), .\po_stg2_wrcal_cnt_reg[1]_55 (\po_stg2_wrcal_cnt_reg[1]_54 ), .\po_stg2_wrcal_cnt_reg[1]_56 (\po_stg2_wrcal_cnt_reg[1]_55 ), .\po_stg2_wrcal_cnt_reg[1]_57 (\po_stg2_wrcal_cnt_reg[1]_56 ), .\po_stg2_wrcal_cnt_reg[1]_58 (\po_stg2_wrcal_cnt_reg[1]_57 ), .\po_stg2_wrcal_cnt_reg[1]_59 (\po_stg2_wrcal_cnt_reg[1]_58 ), .\po_stg2_wrcal_cnt_reg[1]_6 (\po_stg2_wrcal_cnt_reg[1]_5 ), .\po_stg2_wrcal_cnt_reg[1]_60 (\po_stg2_wrcal_cnt_reg[1]_59 ), .\po_stg2_wrcal_cnt_reg[1]_61 (\po_stg2_wrcal_cnt_reg[1]_60 ), .\po_stg2_wrcal_cnt_reg[1]_62 (\po_stg2_wrcal_cnt_reg[1]_61 ), .\po_stg2_wrcal_cnt_reg[1]_7 (\po_stg2_wrcal_cnt_reg[1]_6 ), .\po_stg2_wrcal_cnt_reg[1]_8 (\po_stg2_wrcal_cnt_reg[1]_7 ), .\po_stg2_wrcal_cnt_reg[1]_9 (\po_stg2_wrcal_cnt_reg[1]_8 ), .\prbs_dqs_cnt_r_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ), .\prbs_dqs_cnt_r_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ), .prbs_rdlvl_done_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ), .prbs_rdlvl_done_reg_rep(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ), .prbs_rdlvl_done_reg_rep_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ), .prech_done(prech_done), .prech_req_posedge_r_reg(u_ddr_phy_init_n_9), .rd_active_r1(rd_active_r1), .rd_active_r2(rd_active_r2), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rdlvl_stg1_done_int_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ), .rdlvl_stg1_start_int_reg(u_ddr_phy_init_n_475), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .wl_sm_start(wl_sm_start), .wrcal_done_reg_0(u_ddr_phy_wrcal_n_5), .wrcal_done_reg_1(u_ddr_phy_wrcal_n_82), .wrcal_pat_resume_r(wrcal_pat_resume_r), .wrcal_pat_resume_r_reg_0(u_ddr_phy_wrcal_n_69), .wrcal_pat_resume_r_reg_1(u_ddr_phy_wrcal_n_112), .wrcal_prech_req(wrcal_prech_req), .wrcal_rd_wait(wrcal_rd_wait), .wrcal_resume_r(wrcal_resume_r), .wrcal_resume_w(wrcal_resume_w), .wrcal_sanity_chk(wrcal_sanity_chk), .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71), .wrcal_sanity_chk_r_reg_0(cal2_done_r_i_1_n_0), .wrcal_sanity_chk_reg(u_ddr_phy_init_n_784), .wrcal_start_reg(u_ddr_phy_init_n_791), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_phy_wrcal_n_84), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_phy_wrcal_n_104), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_phy_wrcal_n_103), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_phy_wrcal_n_83), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_byte_redo(wrlvl_byte_redo), .wrlvl_byte_redo_r(wrlvl_byte_redo_r), .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_118), .wrlvl_done_r1(wrlvl_done_r1), .wrlvl_final_mux(wrlvl_final_mux), .\wrlvl_redo_corse_inc_reg[2] (u_ddr_phy_wrcal_n_101)); ddr3_if_mig_7series_v4_0_ddr_prbs_gen u_ddr_prbs_gen (.CLK(CLK), .D({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}), .E(u_ddr_phy_init_n_786), .Q(u_ddr_prbs_gen_n_57), .SR(\rd_addr[7]_i_1_n_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ), .first_rdlvl_pat_r(first_rdlvl_pat_r), .\gen_mux_rd[0].compare_data_fall0_r1_reg[0] (u_ddr_prbs_gen_n_66), .\gen_mux_rd[0].compare_data_fall1_r1_reg[0] (u_ddr_prbs_gen_n_82), .\gen_mux_rd[0].compare_data_fall2_r1_reg[0] (u_ddr_prbs_gen_n_98), .\gen_mux_rd[0].compare_data_fall3_r1_reg[0] (u_ddr_prbs_gen_n_114), .\gen_mux_rd[0].compare_data_rise0_r1_reg[0] (u_ddr_prbs_gen_n_58), .\gen_mux_rd[0].compare_data_rise1_r1_reg[0] (u_ddr_prbs_gen_n_74), .\gen_mux_rd[0].compare_data_rise2_r1_reg[0] (u_ddr_prbs_gen_n_90), .\gen_mux_rd[0].compare_data_rise3_r1_reg[0] (u_ddr_prbs_gen_n_106), .\gen_mux_rd[1].compare_data_fall0_r1_reg[1] (u_ddr_prbs_gen_n_67), .\gen_mux_rd[1].compare_data_fall1_r1_reg[1] (u_ddr_prbs_gen_n_83), .\gen_mux_rd[1].compare_data_fall2_r1_reg[1] (u_ddr_prbs_gen_n_99), .\gen_mux_rd[1].compare_data_fall3_r1_reg[1] (u_ddr_prbs_gen_n_115), .\gen_mux_rd[1].compare_data_rise0_r1_reg[1] (u_ddr_prbs_gen_n_59), .\gen_mux_rd[1].compare_data_rise1_r1_reg[1] (u_ddr_prbs_gen_n_75), .\gen_mux_rd[1].compare_data_rise2_r1_reg[1] (u_ddr_prbs_gen_n_91), .\gen_mux_rd[1].compare_data_rise3_r1_reg[1] (u_ddr_prbs_gen_n_107), .\gen_mux_rd[2].compare_data_fall0_r1_reg[2] (u_ddr_prbs_gen_n_68), .\gen_mux_rd[2].compare_data_fall2_r1_reg[2] (u_ddr_prbs_gen_n_100), .\gen_mux_rd[2].compare_data_fall3_r1_reg[2] (u_ddr_prbs_gen_n_116), .\gen_mux_rd[2].compare_data_rise0_r1_reg[2] (u_ddr_prbs_gen_n_60), .\gen_mux_rd[2].compare_data_rise1_r1_reg[2] (u_ddr_prbs_gen_n_76), .\gen_mux_rd[2].compare_data_rise2_r1_reg[2] (u_ddr_prbs_gen_n_92), .\gen_mux_rd[2].compare_data_rise3_r1_reg[2] (u_ddr_prbs_gen_n_108), .\gen_mux_rd[3].compare_data_fall0_r1_reg[3] (u_ddr_prbs_gen_n_69), .\gen_mux_rd[3].compare_data_fall1_r1_reg[3] (u_ddr_prbs_gen_n_85), .\gen_mux_rd[3].compare_data_fall3_r1_reg[3] (u_ddr_prbs_gen_n_117), .\gen_mux_rd[3].compare_data_rise0_r1_reg[3] (u_ddr_prbs_gen_n_61), .\gen_mux_rd[3].compare_data_rise1_r1_reg[3] (u_ddr_prbs_gen_n_77), .\gen_mux_rd[3].compare_data_rise2_r1_reg[3] (u_ddr_prbs_gen_n_93), .\gen_mux_rd[3].compare_data_rise3_r1_reg[3] (u_ddr_prbs_gen_n_109), .\gen_mux_rd[4].compare_data_fall0_r1_reg[4] (u_ddr_prbs_gen_n_70), .\gen_mux_rd[4].compare_data_fall1_r1_reg[4] (u_ddr_prbs_gen_n_86), .\gen_mux_rd[4].compare_data_fall2_r1_reg[4] (u_ddr_prbs_gen_n_102), .\gen_mux_rd[4].compare_data_fall3_r1_reg[4] (u_ddr_prbs_gen_n_118), .\gen_mux_rd[4].compare_data_rise0_r1_reg[4] (u_ddr_prbs_gen_n_62), .\gen_mux_rd[4].compare_data_rise1_r1_reg[4] (u_ddr_prbs_gen_n_78), .\gen_mux_rd[4].compare_data_rise2_r1_reg[4] (u_ddr_prbs_gen_n_94), .\gen_mux_rd[4].compare_data_rise3_r1_reg[4] (u_ddr_prbs_gen_n_110), .\gen_mux_rd[5].compare_data_fall0_r1_reg[5] (u_ddr_prbs_gen_n_71), .\gen_mux_rd[5].compare_data_fall1_r1_reg[5] (u_ddr_prbs_gen_n_87), .\gen_mux_rd[5].compare_data_fall2_r1_reg[5] (u_ddr_prbs_gen_n_103), .\gen_mux_rd[5].compare_data_fall3_r1_reg[5] (u_ddr_prbs_gen_n_119), .\gen_mux_rd[5].compare_data_rise0_r1_reg[5] (u_ddr_prbs_gen_n_63), .\gen_mux_rd[5].compare_data_rise1_r1_reg[5] (u_ddr_prbs_gen_n_79), .\gen_mux_rd[5].compare_data_rise2_r1_reg[5] (u_ddr_prbs_gen_n_95), .\gen_mux_rd[5].compare_data_rise3_r1_reg[5] (u_ddr_prbs_gen_n_111), .\gen_mux_rd[6].compare_data_fall0_r1_reg[6] (u_ddr_prbs_gen_n_72), .\gen_mux_rd[6].compare_data_fall2_r1_reg[6] (u_ddr_prbs_gen_n_104), .\gen_mux_rd[6].compare_data_fall3_r1_reg[6] (u_ddr_prbs_gen_n_120), .\gen_mux_rd[6].compare_data_rise0_r1_reg[6] (u_ddr_prbs_gen_n_64), .\gen_mux_rd[6].compare_data_rise1_r1_reg[6] (u_ddr_prbs_gen_n_80), .\gen_mux_rd[6].compare_data_rise2_r1_reg[6] (u_ddr_prbs_gen_n_96), .\gen_mux_rd[6].compare_data_rise3_r1_reg[6] (u_ddr_prbs_gen_n_112), .\gen_mux_rd[7].compare_data_fall0_r1_reg[7] (u_ddr_prbs_gen_n_73), .\gen_mux_rd[7].compare_data_fall1_r1_reg[7] (u_ddr_prbs_gen_n_89), .\gen_mux_rd[7].compare_data_fall3_r1_reg[7] (u_ddr_prbs_gen_n_121), .\gen_mux_rd[7].compare_data_rise0_r1_reg[7] (u_ddr_prbs_gen_n_65), .\gen_mux_rd[7].compare_data_rise1_r1_reg[7] (u_ddr_prbs_gen_n_81), .\gen_mux_rd[7].compare_data_rise2_r1_reg[7] (u_ddr_prbs_gen_n_97), .\gen_mux_rd[7].compare_data_rise3_r1_reg[7] (u_ddr_prbs_gen_n_113), .oclkdelay_calib_done_r_reg(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .\rd_addr_reg[0]_0 (u_ddr_prbs_gen_n_0), .\rd_addr_reg[3]_0 (u_ddr_phy_init_n_785), .rdlvl_stg1_done_int_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .wrcal_done_reg(u_ddr_phy_wrcal_n_82), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] (u_ddr_prbs_gen_n_1), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] (u_ddr_prbs_gen_n_29), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] (u_ddr_prbs_gen_n_84), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] (u_ddr_prbs_gen_n_30), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] (u_ddr_prbs_gen_n_2), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] (u_ddr_prbs_gen_n_31), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] (u_ddr_prbs_gen_n_88), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] (u_ddr_prbs_gen_n_32), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] (u_ddr_prbs_gen_n_22), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] (u_ddr_prbs_gen_n_42), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] (u_ddr_prbs_gen_n_15), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] (u_ddr_prbs_gen_n_52), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] (u_ddr_prbs_gen_n_21), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] (u_ddr_prbs_gen_n_41), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] (u_ddr_prbs_gen_n_16), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] (u_ddr_prbs_gen_n_51), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] (u_ddr_prbs_gen_n_33), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] (u_ddr_prbs_gen_n_39), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_prbs_gen_n_5), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] (u_ddr_prbs_gen_n_101), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] (u_ddr_prbs_gen_n_34), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] (u_ddr_prbs_gen_n_40), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] (u_ddr_prbs_gen_n_6), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_prbs_gen_n_105), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] (u_ddr_prbs_gen_n_35), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] (u_ddr_prbs_gen_n_50), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] (u_ddr_prbs_gen_n_20), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] (u_ddr_prbs_gen_n_36), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] (u_ddr_prbs_gen_n_37), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_prbs_gen_n_49), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] (u_ddr_prbs_gen_n_19), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] (u_ddr_prbs_gen_n_38), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] (u_ddr_prbs_gen_n_47), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] (u_ddr_prbs_gen_n_3), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] (u_ddr_prbs_gen_n_9), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] (u_ddr_prbs_gen_n_7), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] (u_ddr_prbs_gen_n_48), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] (u_ddr_prbs_gen_n_4), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] (u_ddr_prbs_gen_n_8), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] (u_ddr_prbs_gen_n_23), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] (u_ddr_prbs_gen_n_26), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] (u_ddr_prbs_gen_n_10), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] (u_ddr_prbs_gen_n_11), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] (u_ddr_prbs_gen_n_24), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] (u_ddr_prbs_gen_n_25), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] (u_ddr_prbs_gen_n_12), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (u_ddr_prbs_gen_n_55), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] (u_ddr_prbs_gen_n_43), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] (u_ddr_prbs_gen_n_44), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] (u_ddr_prbs_gen_n_56), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] (u_ddr_prbs_gen_n_45), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] (u_ddr_prbs_gen_n_46), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] (u_ddr_prbs_gen_n_54), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] (u_ddr_prbs_gen_n_13), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] (u_ddr_prbs_gen_n_17), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_prbs_gen_n_27), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] (u_ddr_prbs_gen_n_53), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] (u_ddr_prbs_gen_n_14), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] (u_ddr_prbs_gen_n_18), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] (u_ddr_prbs_gen_n_28)); LUT6 #( .INIT(64'hEEBAFFFF00001000)) wl_edge_detect_valid_r_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ), .I4(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I5(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ), .O(wl_edge_detect_valid_r_i_1_n_0)); LUT5 #( .INIT(32'hA2A200A2)) wr_level_done_i_1 (.I0(done_dqs_tap_inc), .I1(wrlvl_final_mux), .I2(wrlvl_final_r), .I3(wrlvl_byte_redo), .I4(wrlvl_byte_redo_r), .O(wr_level_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFF0200000002)) wr_level_done_r_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I4(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ), .I5(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ), .O(wr_level_done_r_i_1_n_0)); LUT5 #( .INIT(32'hF8FFF800)) wrcal_pat_resume_r_i_1 (.I0(u_ddr_phy_wrcal_n_109), .I1(u_ddr_phy_wrcal_n_69), .I2(u_ddr_phy_wrcal_n_110), .I3(u_ddr_phy_wrcal_n_112), .I4(wrcal_pat_resume_r), .O(wrcal_pat_resume_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00004000)) wrcal_sanity_chk_done_i_1 (.I0(u_ddr_phy_wrcal_n_108), .I1(u_ddr_phy_wrcal_n_109), .I2(u_ddr_phy_wrcal_n_5), .I3(u_ddr_phy_wrcal_n_110), .I4(u_ddr_phy_wrcal_n_111), .I5(u_ddr_phy_wrcal_n_71), .O(wrcal_sanity_chk_done_i_1_n_0)); LUT6 #( .INIT(64'h0EFFFFFF0E000000)) wrlvl_byte_redo_i_1 (.I0(u_ddr_phy_wrcal_n_66), .I1(u_ddr_phy_wrcal_n_67), .I2(u_ddr_phy_wrcal_n_110), .I3(u_ddr_phy_wrcal_n_118), .I4(u_ddr_phy_wrcal_n_111), .I5(wrlvl_byte_redo), .O(wrlvl_byte_redo_i_1_n_0)); FDRE wrlvl_final_mux_reg (.C(CLK), .CE(1'b1), .D(\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ), .Q(wrlvl_final_mux), .R(1'b0)); LUT5 #( .INIT(32'h40FF4000)) wrlvl_rank_done_r_i_1 (.I0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ), .I1(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ), .I2(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ), .I3(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ), .I4(wrlvl_rank_done), .O(wrlvl_rank_done_r_i_1_n_0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_if_post_fifo (\not_strict_mode.app_rd_data_reg[228] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[0] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[231]_0 , mux_rd_valid_r_reg, \not_strict_mode.app_rd_data_reg[7]_0 , D_byte_rd_en, ififo_rst, CLK, if_empty_r_1, \read_fifo.fifo_out_data_r_reg[6] , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \my_empty_reg[4]_0 , if_empty_r, Q, C_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4]_1 ); output \not_strict_mode.app_rd_data_reg[228] ; output [63:0]\not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[0] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[231]_0 ; output mux_rd_valid_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output D_byte_rd_en; input ififo_rst; input CLK; input [0:0]if_empty_r_1; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [0:0]\my_empty_reg[4]_0 ; input [0:0]if_empty_r; input [65:0]Q; input C_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4]_1 ; wire A_byte_rd_en; wire CLK; wire C_byte_rd_en; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_byte_rd_en; wire [65:0]Q; wire [0:0]if_empty_r; wire [0:0]if_empty_r_0; wire [0:0]if_empty_r_1; wire ififo_rst; wire [71:9]mem_out; wire mem_reg_0_3_6_11_n_0; wire mem_reg_0_3_6_11_n_1; wire mux_rd_valid_r_reg; wire [3:0]my_empty; wire \my_empty[4]_i_1_n_0 ; wire \my_empty[4]_i_2__2_n_0 ; wire [0:0]\my_empty_reg[4]_0 ; wire [0:0]\my_empty_reg[4]_1 ; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1__2_n_0 ; wire \my_full[0]_i_2__2_n_0 ; wire \my_full[1]_i_1__2_n_0 ; wire \my_full[1]_i_2__2_n_0 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire [63:0]\not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[231]_0 ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1__2_n_0 ; wire \rd_ptr[1]_i_1__2_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__6_n_0 ; wire \rd_ptr_timing[1]_i_1__7_n_0 ; wire \read_fifo.fifo_out_data_r_reg[6] ; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__8_n_0 ; wire \wr_ptr[1]_i_1__8_n_0 ; wire \wr_ptr[1]_i_3__2_n_0 ; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair890" *) LUT4 #( .INIT(16'hF888)) i___114_i_3 (.I0(my_empty[0]), .I1(if_empty_r_1), .I2(\my_empty_reg[4]_0 ), .I3(if_empty_r), .O(mux_rd_valid_r_reg)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(mem_out[65:64]), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_66_71 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[67:66]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}), .DOB({mem_out[9],\not_strict_mode.app_rd_data_reg[7]_0 }), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_6_11_i_1__1 (.I0(if_empty_r_1), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3__2_n_0 ), .I3(my_empty[2]), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair923" *) LUT1 #( .INIT(2'h2)) mem_reg_0_3_6_11_i_2__1 (.I0(my_empty[0]), .O(my_empty[2])); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1 (.I0(my_full[1]), .I1(if_empty_r_1), .I2(\wr_ptr[1]_i_3__2_n_0 ), .I3(my_empty[1]), .O(\my_empty[4]_i_1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2__2 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty[1]), .O(\my_empty[4]_i_2__2_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1_n_0 ), .D(\my_empty[4]_i_2__2_n_0 ), .Q(my_empty[0]), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1_n_0 ), .D(\my_empty[4]_i_2__2_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1_n_0 ), .D(\my_empty[4]_i_2__2_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1__2 (.I0(my_full[0]), .I1(my_empty[1]), .I2(my_full[1]), .I3(if_empty_r_1), .I4(\wr_ptr[1]_i_3__2_n_0 ), .I5(\my_full[0]_i_2__2_n_0 ), .O(\my_full[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2__2 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2__2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1__2 (.I0(\my_full[1]_i_2__2_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair888" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2__2 (.I0(my_empty[1]), .I1(my_full[1]), .I2(if_empty_r_1), .I3(\wr_ptr[1]_i_3__2_n_0 ), .O(\my_full[1]_i_2__2_n_0 )); FDRE \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1__2_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1__2_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair891" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[0] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOC[0]), .O(\not_strict_mode.app_rd_data_reg[231] [0])); (* SOFT_HLUTNM = "soft_lutpair905" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[100]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[100] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [28])); (* SOFT_HLUTNM = "soft_lutpair905" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[101]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[101] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [29])); (* SOFT_HLUTNM = "soft_lutpair906" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[102]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[102] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [30])); (* SOFT_HLUTNM = "soft_lutpair906" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[103]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[103] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [31])); (* SOFT_HLUTNM = "soft_lutpair907" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[128]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[128] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [32])); (* SOFT_HLUTNM = "soft_lutpair907" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[129]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[129] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [33])); (* SOFT_HLUTNM = "soft_lutpair908" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[130]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[130] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [34])); (* SOFT_HLUTNM = "soft_lutpair909" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[131]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[131] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [35])); (* SOFT_HLUTNM = "soft_lutpair908" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[132]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[132] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [36])); (* SOFT_HLUTNM = "soft_lutpair909" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[133]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[133] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [37])); (* SOFT_HLUTNM = "soft_lutpair910" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[134]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[134] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [38])); (* SOFT_HLUTNM = "soft_lutpair910" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[135]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[135] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [39])); (* SOFT_HLUTNM = "soft_lutpair911" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[160]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[160] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [40])); (* SOFT_HLUTNM = "soft_lutpair911" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[161]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[161] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [41])); (* SOFT_HLUTNM = "soft_lutpair912" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[162]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[162] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [42])); (* SOFT_HLUTNM = "soft_lutpair912" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[163]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[163] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [43])); (* SOFT_HLUTNM = "soft_lutpair913" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[164]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[164] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [44])); (* SOFT_HLUTNM = "soft_lutpair913" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[165]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[165] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [45])); (* SOFT_HLUTNM = "soft_lutpair914" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[166]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[166] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [46])); (* SOFT_HLUTNM = "soft_lutpair914" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[167]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[167] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [47])); (* SOFT_HLUTNM = "soft_lutpair915" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[192]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[192] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [48])); (* SOFT_HLUTNM = "soft_lutpair915" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[193]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[193] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [49])); (* SOFT_HLUTNM = "soft_lutpair916" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[194]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[194] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [50])); (* SOFT_HLUTNM = "soft_lutpair916" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[195]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[195] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [51])); (* SOFT_HLUTNM = "soft_lutpair917" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[196]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[196] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [52])); (* SOFT_HLUTNM = "soft_lutpair917" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[197]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[197] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [53])); (* SOFT_HLUTNM = "soft_lutpair918" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[198]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[198] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [54])); (* SOFT_HLUTNM = "soft_lutpair918" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[199]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[199] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [55])); (* SOFT_HLUTNM = "soft_lutpair892" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[1] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOC[1]), .O(\not_strict_mode.app_rd_data_reg[231] [1])); (* SOFT_HLUTNM = "soft_lutpair919" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[224]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[224] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [56])); (* SOFT_HLUTNM = "soft_lutpair919" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[225]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[225] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [57])); (* SOFT_HLUTNM = "soft_lutpair920" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[226]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[226] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [58])); (* SOFT_HLUTNM = "soft_lutpair920" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[227]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[227] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [59])); (* SOFT_HLUTNM = "soft_lutpair921" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[228]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[228]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [60])); (* SOFT_HLUTNM = "soft_lutpair921" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[229]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[229] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [61])); (* SOFT_HLUTNM = "soft_lutpair922" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[230]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[230] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [62])); (* SOFT_HLUTNM = "soft_lutpair922" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[231]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[231]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [63])); (* SOFT_HLUTNM = "soft_lutpair893" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[2] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOB[0]), .O(\not_strict_mode.app_rd_data_reg[231] [2])); (* SOFT_HLUTNM = "soft_lutpair894" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[32]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[32] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [8])); (* SOFT_HLUTNM = "soft_lutpair895" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[33]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[33] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [9])); (* SOFT_HLUTNM = "soft_lutpair896" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[34]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[34] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [10])); (* SOFT_HLUTNM = "soft_lutpair896" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[35]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[35] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [11])); (* SOFT_HLUTNM = "soft_lutpair897" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[36]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[36] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [12])); (* SOFT_HLUTNM = "soft_lutpair897" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[37]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[37] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [13])); (* SOFT_HLUTNM = "soft_lutpair898" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[38]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[38] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [14])); (* SOFT_HLUTNM = "soft_lutpair898" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[39]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[39] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [15])); (* SOFT_HLUTNM = "soft_lutpair894" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[3] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOB[1]), .O(\not_strict_mode.app_rd_data_reg[231] [3])); (* SOFT_HLUTNM = "soft_lutpair895" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[4] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOA[0]), .O(\not_strict_mode.app_rd_data_reg[231] [4])); (* SOFT_HLUTNM = "soft_lutpair891" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[5] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(DOA[1]), .O(\not_strict_mode.app_rd_data_reg[231] [5])); (* SOFT_HLUTNM = "soft_lutpair899" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[64]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[64] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [16])); (* SOFT_HLUTNM = "soft_lutpair899" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[65]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[65] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [17])); (* SOFT_HLUTNM = "soft_lutpair900" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[66]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[66] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [18])); (* SOFT_HLUTNM = "soft_lutpair900" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[67]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[67] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [19])); (* SOFT_HLUTNM = "soft_lutpair901" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[68]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[68] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [20])); (* SOFT_HLUTNM = "soft_lutpair901" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[69]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[69] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [21])); (* SOFT_HLUTNM = "soft_lutpair892" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[6] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[231] [6])); (* SOFT_HLUTNM = "soft_lutpair902" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[70]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[70] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [22])); (* SOFT_HLUTNM = "soft_lutpair902" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[71]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[71] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [23])); (* SOFT_HLUTNM = "soft_lutpair893" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[7] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[231] [7])); (* SOFT_HLUTNM = "soft_lutpair903" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[96]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[96] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [24])); (* SOFT_HLUTNM = "soft_lutpair903" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[97]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[97] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [25])); (* SOFT_HLUTNM = "soft_lutpair904" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[98]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[98] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[231] [26])); (* SOFT_HLUTNM = "soft_lutpair904" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[99]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[99] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[231] [27])); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2 (.I0(Q[18]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[5] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3 (.I0(Q[26]), .I1(mem_out[32]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[4] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4 (.I0(Q[34]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[3] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5 (.I0(Q[42]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[2] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6 (.I0(Q[50]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[1] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7 (.I0(Q[58]), .I1(mem_out[64]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[0] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_8 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[228] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1 (.I0(Q[52]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[65] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2 (.I0(Q[60]), .I1(mem_out[66]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[64] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1 (.I0(Q[4]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[71] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2 (.I0(Q[12]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[70] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3 (.I0(Q[20]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[69] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4 (.I0(Q[28]), .I1(mem_out[34]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[68] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5 (.I0(Q[36]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[67] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6 (.I0(Q[44]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[66] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1 (.I0(Q[21]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[101] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2 (.I0(Q[29]), .I1(mem_out[35]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[100] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3 (.I0(Q[37]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[99] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4 (.I0(Q[45]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[98] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5 (.I0(Q[53]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[97] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6 (.I0(Q[61]), .I1(mem_out[67]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[96] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5 (.I0(Q[5]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[103] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6 (.I0(Q[13]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[102] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5 (.I0(Q[2]), .I1(\not_strict_mode.app_rd_data_reg[7]_0 ), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[7] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6 (.I0(Q[10]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[6] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1 (.I0(Q[38]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[131] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2 (.I0(Q[46]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[130] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3 (.I0(Q[54]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[129] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4 (.I0(Q[62]), .I1(mem_out[68]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[128] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3 (.I0(Q[6]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[135] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4 (.I0(Q[14]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[134] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5 (.I0(Q[22]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[133] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_6 (.I0(Q[30]), .I1(mem_out[36]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[132] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1 (.I0(Q[55]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[161] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2 (.I0(Q[63]), .I1(mem_out[69]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[160] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1 (.I0(Q[7]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[167] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2 (.I0(Q[15]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[166] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3 (.I0(Q[23]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[165] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4 (.I0(Q[31]), .I1(mem_out[37]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[164] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5 (.I0(Q[39]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[163] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_6 (.I0(Q[47]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[162] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1 (.I0(Q[24]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[197] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2 (.I0(Q[32]), .I1(mem_out[38]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[196] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3 (.I0(Q[40]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[195] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4 (.I0(Q[48]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[194] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5 (.I0(Q[56]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[193] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_6 (.I0(Q[64]), .I1(mem_out[70]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[192] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5 (.I0(Q[8]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[199] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_6 (.I0(Q[16]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[198] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1 (.I0(Q[41]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[227] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2 (.I0(Q[49]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[226] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3 (.I0(Q[57]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[225] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4 (.I0(Q[65]), .I1(mem_out[71]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[224] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3 (.I0(Q[9]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[231]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4 (.I0(Q[17]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[230] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5 (.I0(Q[25]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[229] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_6 (.I0(Q[33]), .I1(mem_out[39]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[228]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1 (.I0(Q[35]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[35] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2 (.I0(Q[43]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[34] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3 (.I0(Q[51]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[33] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4 (.I0(Q[59]), .I1(mem_out[65]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ), .O(\not_strict_mode.app_rd_data_reg[32] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3 (.I0(Q[3]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[39] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4 (.I0(Q[11]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[38] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5 (.I0(Q[19]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[37] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6 (.I0(Q[27]), .I1(mem_out[33]), .I2(\not_strict_mode.app_rd_data_reg[228] ), .O(\not_strict_mode.app_rd_data_reg[36] )); (* SOFT_HLUTNM = "soft_lutpair889" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1__2 (.I0(my_empty[1]), .I1(\wr_ptr[1]_i_3__2_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair889" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1__2 (.I0(rd_ptr[0]), .I1(my_empty[1]), .I2(\wr_ptr[1]_i_3__2_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1__2_n_0 )); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1__2_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1__2_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__6 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3__2_n_0 ), .I2(my_empty[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__6_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__7 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3__2_n_0 ), .I4(my_empty[1]), .O(\rd_ptr_timing[1]_i_1__7_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__6_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__7_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair888" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__8 (.I0(if_empty_r_1), .I1(my_empty[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3__2_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__8_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__8 (.I0(wr_ptr[0]), .I1(if_empty_r_1), .I2(my_empty[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3__2_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair923" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2__2 (.I0(my_empty[0]), .O(my_empty[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3__2 (.I0(my_empty[3]), .I1(if_empty_r_1), .I2(C_byte_rd_en), .I3(A_byte_rd_en), .I4(if_empty_r_0), .I5(\my_empty_reg[4]_1 ), .O(\wr_ptr[1]_i_3__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair890" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_4__1 (.I0(my_empty[0]), .O(my_empty[3])); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_5__1 (.I0(if_empty_r_1), .I1(my_empty[3]), .O(D_byte_rd_en)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__8_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__8_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_6 (phy_if_empty_r_reg, \not_strict_mode.app_rd_data_reg[236] , \rd_ptr_timing_reg[1]_0 , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[239]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , C_byte_rd_en, ififo_rst, CLK, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , Q, D_byte_rd_en, A_byte_rd_en, if_empty_r_0, \my_empty_reg[4]_0 ); output phy_if_empty_r_reg; output \not_strict_mode.app_rd_data_reg[236] ; output [0:0]\rd_ptr_timing_reg[1]_0 ; output [63:0]\not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[239]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output C_byte_rd_en; input ififo_rst; input CLK; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [65:0]Q; input D_byte_rd_en; input A_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]\my_empty_reg[4]_0 ; wire A_byte_rd_en; wire CLK; wire C_byte_rd_en; wire D_byte_rd_en; wire [65:0]Q; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire [0:0]if_empty_r_0; wire ififo_rst; wire [71:9]mem_out; wire mem_reg_0_3_6_11_n_0; wire mem_reg_0_3_6_11_n_1; wire [2:1]my_empty; wire \my_empty[4]_i_1__0_n_0 ; wire \my_empty[4]_i_2__1_n_0 ; wire [0:0]\my_empty_reg[4]_0 ; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1__1_n_0 ; wire \my_full[0]_i_2__1_n_0 ; wire \my_full[1]_i_1__1_n_0 ; wire \my_full[1]_i_2__1_n_0 ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire [63:0]\not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[239]_0 ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ; wire phy_if_empty_r_reg; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1__1_n_0 ; wire \rd_ptr[1]_i_1__1_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__4_n_0 ; wire \rd_ptr_timing[1]_i_1__6_n_0 ; wire [0:0]\rd_ptr_timing_reg[1]_0 ; wire \read_fifo.fifo_out_data_r_reg[6] ; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__6_n_0 ; wire \wr_ptr[1]_i_1__6_n_0 ; wire \wr_ptr[1]_i_3__1_n_0 ; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(mem_out[65:64]), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_66_71 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[67:66]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}), .DOB({mem_out[9],\not_strict_mode.app_rd_data_reg[15]_0 }), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_6_11_i_1__0 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3__1_n_0 ), .I3(my_empty[2]), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair871" *) LUT1 #( .INIT(2'h2)) mem_reg_0_3_6_11_i_2__0 (.I0(phy_if_empty_r_reg), .O(my_empty[2])); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1__0 (.I0(my_full[1]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\wr_ptr[1]_i_3__1_n_0 ), .I3(my_empty[1]), .O(\my_empty[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2__1 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty[1]), .O(\my_empty[4]_i_2__1_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1__0_n_0 ), .D(\my_empty[4]_i_2__1_n_0 ), .Q(phy_if_empty_r_reg), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1__0_n_0 ), .D(\my_empty[4]_i_2__1_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1__0_n_0 ), .D(\my_empty[4]_i_2__1_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1__1 (.I0(my_full[0]), .I1(my_empty[1]), .I2(my_full[1]), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\wr_ptr[1]_i_3__1_n_0 ), .I5(\my_full[0]_i_2__1_n_0 ), .O(\my_full[0]_i_1__1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2__1 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2__1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1__1 (.I0(\my_full[1]_i_2__1_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair837" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2__1 (.I0(my_empty[1]), .I1(my_full[1]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\wr_ptr[1]_i_3__1_n_0 ), .O(\my_full[1]_i_2__1_n_0 )); FDRE \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1__1_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1__1_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair851" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[104]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[104] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [24])); (* SOFT_HLUTNM = "soft_lutpair851" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[105]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[105] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [25])); (* SOFT_HLUTNM = "soft_lutpair852" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[106]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[106] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [26])); (* SOFT_HLUTNM = "soft_lutpair852" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[107]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[107] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [27])); (* SOFT_HLUTNM = "soft_lutpair853" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[108]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[108] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [28])); (* SOFT_HLUTNM = "soft_lutpair853" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[109]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[109] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [29])); (* SOFT_HLUTNM = "soft_lutpair841" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[10]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[10] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [2])); (* SOFT_HLUTNM = "soft_lutpair854" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[110]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[110] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [30])); (* SOFT_HLUTNM = "soft_lutpair854" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[111]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[111] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [31])); (* SOFT_HLUTNM = "soft_lutpair842" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[11]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[11] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [3])); (* SOFT_HLUTNM = "soft_lutpair843" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[12]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[12] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [4])); (* SOFT_HLUTNM = "soft_lutpair855" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[136]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[136] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [32])); (* SOFT_HLUTNM = "soft_lutpair855" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[137]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[137] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [33])); (* SOFT_HLUTNM = "soft_lutpair856" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[138]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[138] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [34])); (* SOFT_HLUTNM = "soft_lutpair856" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[139]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[139] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [35])); (* SOFT_HLUTNM = "soft_lutpair840" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[13]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[13] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [5])); (* SOFT_HLUTNM = "soft_lutpair857" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[140]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[140] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [36])); (* SOFT_HLUTNM = "soft_lutpair857" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[141]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[141] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [37])); (* SOFT_HLUTNM = "soft_lutpair858" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[142]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[142] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [38])); (* SOFT_HLUTNM = "soft_lutpair858" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[143]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[143] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [39])); (* SOFT_HLUTNM = "soft_lutpair841" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[14]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[14] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [6])); (* SOFT_HLUTNM = "soft_lutpair842" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[15]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[15] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [7])); (* SOFT_HLUTNM = "soft_lutpair859" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[168]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[168] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [40])); (* SOFT_HLUTNM = "soft_lutpair859" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[169]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[169] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [41])); (* SOFT_HLUTNM = "soft_lutpair860" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[170]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[170] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [42])); (* SOFT_HLUTNM = "soft_lutpair860" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[171]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[171] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [43])); (* SOFT_HLUTNM = "soft_lutpair861" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[172]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[172] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [44])); (* SOFT_HLUTNM = "soft_lutpair861" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[173]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[173] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [45])); (* SOFT_HLUTNM = "soft_lutpair862" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[174]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[174] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [46])); (* SOFT_HLUTNM = "soft_lutpair862" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[175]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[175] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [47])); (* SOFT_HLUTNM = "soft_lutpair863" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[200]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[200] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [48])); (* SOFT_HLUTNM = "soft_lutpair863" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[201]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[201] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [49])); (* SOFT_HLUTNM = "soft_lutpair864" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[202]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[202] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [50])); (* SOFT_HLUTNM = "soft_lutpair864" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[203]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[203] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [51])); (* SOFT_HLUTNM = "soft_lutpair865" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[204]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[204] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [52])); (* SOFT_HLUTNM = "soft_lutpair865" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[205]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[205] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [53])); (* SOFT_HLUTNM = "soft_lutpair866" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[206]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[206] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [54])); (* SOFT_HLUTNM = "soft_lutpair866" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[207]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[207] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [55])); (* SOFT_HLUTNM = "soft_lutpair867" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[232]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[232] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [56])); (* SOFT_HLUTNM = "soft_lutpair867" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[233]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[233] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [57])); (* SOFT_HLUTNM = "soft_lutpair868" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[234]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[234] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [58])); (* SOFT_HLUTNM = "soft_lutpair868" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[235]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[235] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [59])); (* SOFT_HLUTNM = "soft_lutpair869" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[236]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[236]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [60])); (* SOFT_HLUTNM = "soft_lutpair869" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[237]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[237] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [61])); (* SOFT_HLUTNM = "soft_lutpair870" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[238]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[238] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [62])); (* SOFT_HLUTNM = "soft_lutpair870" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[239]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[239]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [63])); (* SOFT_HLUTNM = "soft_lutpair839" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[40]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[40] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [8])); (* SOFT_HLUTNM = "soft_lutpair843" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[41]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[41] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [9])); (* SOFT_HLUTNM = "soft_lutpair844" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[42]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[42] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [10])); (* SOFT_HLUTNM = "soft_lutpair844" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[43]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[43] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [11])); (* SOFT_HLUTNM = "soft_lutpair845" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[44]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[44] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [12])); (* SOFT_HLUTNM = "soft_lutpair845" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[45]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[45] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [13])); (* SOFT_HLUTNM = "soft_lutpair846" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[46]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[46] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [14])); (* SOFT_HLUTNM = "soft_lutpair846" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[47]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[47] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [15])); (* SOFT_HLUTNM = "soft_lutpair847" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[72]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[72] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [16])); (* SOFT_HLUTNM = "soft_lutpair847" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[73]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[73] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [17])); (* SOFT_HLUTNM = "soft_lutpair848" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[74]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[74] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [18])); (* SOFT_HLUTNM = "soft_lutpair848" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[75]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[75] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [19])); (* SOFT_HLUTNM = "soft_lutpair849" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[76]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[76] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [20])); (* SOFT_HLUTNM = "soft_lutpair849" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[77]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[77] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [21])); (* SOFT_HLUTNM = "soft_lutpair850" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[78]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[78] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[239] [22])); (* SOFT_HLUTNM = "soft_lutpair850" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[79]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[79] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[239] [23])); (* SOFT_HLUTNM = "soft_lutpair839" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[8]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[8] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[239] [0])); (* SOFT_HLUTNM = "soft_lutpair840" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[9]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[9] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[239] [1])); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1 (.I0(Q[20]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[77] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2 (.I0(Q[28]), .I1(mem_out[34]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[76] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3 (.I0(Q[36]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[75] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4 (.I0(Q[44]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[74] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5 (.I0(Q[52]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[73] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6 (.I0(Q[60]), .I1(mem_out[66]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[72] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5 (.I0(Q[4]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[79] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6 (.I0(Q[12]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[78] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1 (.I0(Q[37]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[107] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2 (.I0(Q[45]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[106] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3 (.I0(Q[53]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[105] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4 (.I0(Q[61]), .I1(mem_out[67]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[104] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3 (.I0(Q[5]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[111] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4 (.I0(Q[13]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[110] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5 (.I0(Q[21]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[109] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6 (.I0(Q[29]), .I1(mem_out[35]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[108] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1 (.I0(Q[34]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[11] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2 (.I0(Q[42]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[10] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3 (.I0(Q[50]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[9] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4 (.I0(Q[58]), .I1(mem_out[64]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[8] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1 (.I0(Q[54]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[137] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2 (.I0(Q[62]), .I1(mem_out[68]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[136] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1 (.I0(Q[6]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[143] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2 (.I0(Q[14]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[142] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3 (.I0(Q[22]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[141] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4 (.I0(Q[30]), .I1(mem_out[36]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[140] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5 (.I0(Q[38]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[139] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_6 (.I0(Q[46]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[138] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1 (.I0(Q[23]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[173] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2 (.I0(Q[31]), .I1(mem_out[37]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[172] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3 (.I0(Q[39]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[171] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4 (.I0(Q[47]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[170] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5 (.I0(Q[55]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[169] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_6 (.I0(Q[63]), .I1(mem_out[69]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[168] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5 (.I0(Q[7]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[175] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_6 (.I0(Q[15]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[174] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3 (.I0(Q[2]), .I1(\not_strict_mode.app_rd_data_reg[15]_0 ), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[15] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4 (.I0(Q[10]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[14] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5 (.I0(Q[18]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[13] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6 (.I0(Q[26]), .I1(mem_out[32]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[12] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_8 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[236] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1 (.I0(Q[40]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[203] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2 (.I0(Q[48]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[202] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3 (.I0(Q[56]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[201] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4 (.I0(Q[64]), .I1(mem_out[70]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[200] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3 (.I0(Q[8]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[207] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4 (.I0(Q[16]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[206] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5 (.I0(Q[24]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[205] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_6 (.I0(Q[32]), .I1(mem_out[38]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[204] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1 (.I0(Q[57]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[233] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2 (.I0(Q[65]), .I1(mem_out[71]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[232] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1 (.I0(Q[9]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[239]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2 (.I0(Q[17]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[238] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3 (.I0(Q[25]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[237] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4 (.I0(Q[33]), .I1(mem_out[39]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[236]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5 (.I0(Q[41]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[235] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_6 (.I0(Q[49]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[234] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1 (.I0(Q[51]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[41] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2 (.I0(Q[59]), .I1(mem_out[65]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[40] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1 (.I0(Q[3]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[47] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2 (.I0(Q[11]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[46] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3 (.I0(Q[19]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[45] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4 (.I0(Q[27]), .I1(mem_out[33]), .I2(\not_strict_mode.app_rd_data_reg[236] ), .O(\not_strict_mode.app_rd_data_reg[44] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5 (.I0(Q[35]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[43] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6 (.I0(Q[43]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[42] )); (* SOFT_HLUTNM = "soft_lutpair838" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1__1 (.I0(my_empty[1]), .I1(\wr_ptr[1]_i_3__1_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair838" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1__1 (.I0(rd_ptr[0]), .I1(my_empty[1]), .I2(\wr_ptr[1]_i_3__1_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1__1_n_0 )); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1__1_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1__1_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__4 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3__1_n_0 ), .I2(my_empty[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__6 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3__1_n_0 ), .I4(my_empty[1]), .O(\rd_ptr_timing[1]_i_1__6_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__4_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__6_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair837" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__6 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3__1_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__6_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__6 (.I0(wr_ptr[0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(my_empty[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3__1_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__6_n_0 )); LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2__1 (.I0(phy_if_empty_r_reg), .O(my_empty[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3__1 (.I0(\rd_ptr_timing_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(D_byte_rd_en), .I3(A_byte_rd_en), .I4(if_empty_r_0), .I5(\my_empty_reg[4]_0 ), .O(\wr_ptr[1]_i_3__1_n_0 )); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_5__0 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\rd_ptr_timing_reg[1]_0 ), .O(C_byte_rd_en)); (* SOFT_HLUTNM = "soft_lutpair871" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_7 (.I0(phy_if_empty_r_reg), .O(\rd_ptr_timing_reg[1]_0 )); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__6_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__6_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_7 (\not_strict_mode.app_rd_data_reg[244] , \rd_ptr_timing_reg[1]_0 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , phy_rddata_en, mux_rd_valid_r_reg, \read_fifo.tail_r_reg[0] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[247]_0 , phy_if_empty_r_reg, \not_strict_mode.app_rd_data_reg[23]_0 , B_byte_rd_en, ififo_rst, CLK, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, if_empty_r_0, my_empty, \my_empty_reg[4]_0 , prbs_rdlvl_start_reg, out, tail_r, \read_fifo.fifo_out_data_r_reg[6]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , Q, D_byte_rd_en, A_byte_rd_en); output \not_strict_mode.app_rd_data_reg[244] ; output [0:0]\rd_ptr_timing_reg[1]_0 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output phy_rddata_en; output mux_rd_valid_r_reg; output \read_fifo.tail_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[247]_0 ; output phy_if_empty_r_reg; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output B_byte_rd_en; input ififo_rst; input CLK; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input [0:0]if_empty_r_0; input [1:0]my_empty; input \my_empty_reg[4]_0 ; input prbs_rdlvl_start_reg; input out; input [0:0]tail_r; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [65:0]Q; input D_byte_rd_en; input A_byte_rd_en; wire A_byte_rd_en; wire B_byte_rd_en; wire CLK; wire D_byte_rd_en; wire [65:0]Q; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire [0:0]if_empty_r_0; wire ififo_rst; wire [71:9]mem_out; wire mem_reg_0_3_6_11_n_0; wire mem_reg_0_3_6_11_n_1; wire mux_rd_valid_r_reg; wire [1:0]my_empty; wire \my_empty[4]_i_1__1_n_0 ; wire \my_empty[4]_i_2__0_n_0 ; wire [2:0]my_empty_0; wire \my_empty_reg[4]_0 ; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1__0_n_0 ; wire \my_full[0]_i_2__0_n_0 ; wire \my_full[1]_i_1__0_n_0 ; wire \my_full[1]_i_2__0_n_0 ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire [63:0]\not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[247]_0 ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire out; wire phy_if_empty_r_reg; wire phy_rddata_en; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rd_buf_we; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1__0_n_0 ; wire \rd_ptr[1]_i_1__0_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__2_n_0 ; wire \rd_ptr_timing[1]_i_1__5_n_0 ; wire [0:0]\rd_ptr_timing_reg[1]_0 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]tail_r; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__4_n_0 ; wire \wr_ptr[1]_i_1__4_n_0 ; wire \wr_ptr[1]_i_3__0_n_0 ; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; LUT6 #( .INIT(64'h0000077700000000)) i___114_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .I5(out), .O(\not_strict_mode.status_ram.rd_buf_we_r1_reg )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(mem_out[65:64]), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_66_71 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[67:66]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}), .DOB({mem_out[9],\not_strict_mode.app_rd_data_reg[23]_0 }), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_6_11_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3__0_n_0 ), .I3(my_empty_0[2]), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair820" *) LUT1 #( .INIT(2'h2)) mem_reg_0_3_6_11_i_2 (.I0(my_empty_0[0]), .O(my_empty_0[2])); LUT6 #( .INIT(64'h0000077700000000)) mux_rd_valid_r_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .I5(prbs_rdlvl_start_reg), .O(mux_rd_valid_r_reg)); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1__1 (.I0(my_full[1]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\wr_ptr[1]_i_3__0_n_0 ), .I3(my_empty_0[1]), .O(\my_empty[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2__0 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty_0[1]), .O(\my_empty[4]_i_2__0_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1__1_n_0 ), .D(\my_empty[4]_i_2__0_n_0 ), .Q(my_empty_0[0]), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1__1_n_0 ), .D(\my_empty[4]_i_2__0_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1__1_n_0 ), .D(\my_empty[4]_i_2__0_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1__0 (.I0(my_full[0]), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\wr_ptr[1]_i_3__0_n_0 ), .I5(\my_full[0]_i_2__0_n_0 ), .O(\my_full[0]_i_1__0_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2__0 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2__0_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1__0 (.I0(\my_full[1]_i_2__0_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair786" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2__0 (.I0(my_empty_0[1]), .I1(my_full[1]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\wr_ptr[1]_i_3__0_n_0 ), .O(\my_full[1]_i_2__0_n_0 )); FDRE \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1__0_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1__0_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair800" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[112]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[112] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [24])); (* SOFT_HLUTNM = "soft_lutpair800" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[113]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[113] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [25])); (* SOFT_HLUTNM = "soft_lutpair801" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[114]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[114] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [26])); (* SOFT_HLUTNM = "soft_lutpair801" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[115]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[115] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [27])); (* SOFT_HLUTNM = "soft_lutpair802" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[116]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[116] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [28])); (* SOFT_HLUTNM = "soft_lutpair802" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[117]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[117] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [29])); (* SOFT_HLUTNM = "soft_lutpair803" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[118]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[118] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [30])); (* SOFT_HLUTNM = "soft_lutpair803" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[119]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[119] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [31])); (* SOFT_HLUTNM = "soft_lutpair804" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[144]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[144] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [32])); (* SOFT_HLUTNM = "soft_lutpair804" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[145]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[145] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [33])); (* SOFT_HLUTNM = "soft_lutpair805" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[146]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[146] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [34])); (* SOFT_HLUTNM = "soft_lutpair805" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[147]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[147] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [35])); (* SOFT_HLUTNM = "soft_lutpair806" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[148]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[148] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [36])); (* SOFT_HLUTNM = "soft_lutpair807" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[149]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[149] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [37])); (* SOFT_HLUTNM = "soft_lutpair806" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[150]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[150] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [38])); (* SOFT_HLUTNM = "soft_lutpair807" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[151]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[151] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [39])); (* SOFT_HLUTNM = "soft_lutpair788" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[16]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[16] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[247] [0])); (* SOFT_HLUTNM = "soft_lutpair808" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[176]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[176] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [40])); (* SOFT_HLUTNM = "soft_lutpair808" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[177]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[177] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [41])); (* SOFT_HLUTNM = "soft_lutpair809" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[178]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[178] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [42])); (* SOFT_HLUTNM = "soft_lutpair809" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[179]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[179] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [43])); (* SOFT_HLUTNM = "soft_lutpair789" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[17]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[17] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[247] [1])); (* SOFT_HLUTNM = "soft_lutpair810" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[180]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[180] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [44])); (* SOFT_HLUTNM = "soft_lutpair810" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[181]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[181] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [45])); (* SOFT_HLUTNM = "soft_lutpair811" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[182]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[182] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [46])); (* SOFT_HLUTNM = "soft_lutpair811" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[183]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[183] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [47])); (* SOFT_HLUTNM = "soft_lutpair790" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[18]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[18] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [2])); (* SOFT_HLUTNM = "soft_lutpair791" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[19]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[19] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [3])); (* SOFT_HLUTNM = "soft_lutpair812" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[208]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[208] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [48])); (* SOFT_HLUTNM = "soft_lutpair812" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[209]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[209] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [49])); (* SOFT_HLUTNM = "soft_lutpair792" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[20]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[20] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [4])); (* SOFT_HLUTNM = "soft_lutpair813" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[210]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[210] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [50])); (* SOFT_HLUTNM = "soft_lutpair813" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[211]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[211] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [51])); (* SOFT_HLUTNM = "soft_lutpair814" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[212]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[212] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [52])); (* SOFT_HLUTNM = "soft_lutpair814" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[213]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[213] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [53])); (* SOFT_HLUTNM = "soft_lutpair815" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[214]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[214] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [54])); (* SOFT_HLUTNM = "soft_lutpair815" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[215]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[215] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [55])); (* SOFT_HLUTNM = "soft_lutpair793" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[21]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[21] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [5])); (* SOFT_HLUTNM = "soft_lutpair794" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[22]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[22] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [6])); (* SOFT_HLUTNM = "soft_lutpair795" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[23]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[23] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [7])); (* SOFT_HLUTNM = "soft_lutpair816" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[240]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[240] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [56])); (* SOFT_HLUTNM = "soft_lutpair816" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[241]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[241] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [57])); (* SOFT_HLUTNM = "soft_lutpair817" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[242]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[242] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [58])); (* SOFT_HLUTNM = "soft_lutpair817" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[243]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[243] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [59])); (* SOFT_HLUTNM = "soft_lutpair818" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[244]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[244]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [60])); (* SOFT_HLUTNM = "soft_lutpair818" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[245]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[245] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [61])); (* SOFT_HLUTNM = "soft_lutpair819" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[246]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[246] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [62])); (* SOFT_HLUTNM = "soft_lutpair819" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[247]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[247]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [63])); (* SOFT_HLUTNM = "soft_lutpair788" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[48]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[48] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [8])); (* SOFT_HLUTNM = "soft_lutpair789" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[49]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[49] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [9])); (* SOFT_HLUTNM = "soft_lutpair790" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[50]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[50] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [10])); (* SOFT_HLUTNM = "soft_lutpair791" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[51]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[51] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [11])); (* SOFT_HLUTNM = "soft_lutpair792" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[52]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[52] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [12])); (* SOFT_HLUTNM = "soft_lutpair793" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[53]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[53] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [13])); (* SOFT_HLUTNM = "soft_lutpair794" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[54]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[54] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [14])); (* SOFT_HLUTNM = "soft_lutpair795" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[55]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[55] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [15])); (* SOFT_HLUTNM = "soft_lutpair796" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[80]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[80] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [16])); (* SOFT_HLUTNM = "soft_lutpair796" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[81]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[81] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [17])); (* SOFT_HLUTNM = "soft_lutpair797" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[82]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[82] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [18])); (* SOFT_HLUTNM = "soft_lutpair797" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[83]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[83] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [19])); (* SOFT_HLUTNM = "soft_lutpair798" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[84]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[84] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [20])); (* SOFT_HLUTNM = "soft_lutpair798" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[85]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[85] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [21])); (* SOFT_HLUTNM = "soft_lutpair799" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[86]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[86] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[247] [22])); (* SOFT_HLUTNM = "soft_lutpair799" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[87]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[87] ), .I1(\read_fifo.fifo_out_data_r_reg[6]_0 ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[247] [23])); LUT3 #( .INIT(8'h2F)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1 (.I0(\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(ram_init_done_r), .O(rd_buf_we)); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1 (.I0(Q[36]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[83] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2 (.I0(Q[44]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[82] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3 (.I0(Q[52]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[81] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4 (.I0(Q[60]), .I1(mem_out[66]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[80] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3 (.I0(Q[4]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[87] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4 (.I0(Q[12]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[86] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5 (.I0(Q[20]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[85] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6 (.I0(Q[28]), .I1(mem_out[34]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[84] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1 (.I0(Q[53]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[113] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2 (.I0(Q[61]), .I1(mem_out[67]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[112] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1 (.I0(Q[5]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[119] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2 (.I0(Q[13]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[118] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3 (.I0(Q[21]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[117] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4 (.I0(Q[29]), .I1(mem_out[35]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[116] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5 (.I0(Q[37]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[115] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6 (.I0(Q[45]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[114] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1 (.I0(Q[22]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[149] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2 (.I0(Q[30]), .I1(mem_out[36]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[148] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3 (.I0(Q[38]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[147] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4 (.I0(Q[46]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[146] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5 (.I0(Q[54]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[145] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_6 (.I0(Q[62]), .I1(mem_out[68]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[144] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5 (.I0(Q[6]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[151] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_6 (.I0(Q[14]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[150] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1 (.I0(Q[39]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[179] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2 (.I0(Q[47]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[178] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3 (.I0(Q[55]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[177] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4 (.I0(Q[63]), .I1(mem_out[69]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[176] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1 (.I0(Q[50]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[17] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2 (.I0(Q[58]), .I1(mem_out[64]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[16] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3 (.I0(Q[7]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[183] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4 (.I0(Q[15]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[182] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5 (.I0(Q[23]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[181] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_6 (.I0(Q[31]), .I1(mem_out[37]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[180] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1 (.I0(Q[56]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[209] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2 (.I0(Q[64]), .I1(mem_out[70]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[208] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1 (.I0(Q[8]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[215] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2 (.I0(Q[16]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[214] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3 (.I0(Q[24]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[213] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4 (.I0(Q[32]), .I1(mem_out[38]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[212] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5 (.I0(Q[40]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[211] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_6 (.I0(Q[48]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[210] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1 (.I0(Q[2]), .I1(\not_strict_mode.app_rd_data_reg[23]_0 ), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[23] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2 (.I0(Q[10]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[22] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3 (.I0(Q[18]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[21] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4 (.I0(Q[26]), .I1(mem_out[32]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[20] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5 (.I0(Q[34]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[19] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6 (.I0(Q[42]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[18] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[244] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1 (.I0(Q[25]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[245] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2 (.I0(Q[33]), .I1(mem_out[39]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[244]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3 (.I0(Q[41]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[243] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4 (.I0(Q[49]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[242] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5 (.I0(Q[57]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[241] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_6 (.I0(Q[65]), .I1(mem_out[71]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[240] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5 (.I0(Q[9]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[247]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_6 (.I0(Q[17]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[246] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1 (.I0(Q[19]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[53] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2 (.I0(Q[27]), .I1(mem_out[33]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[52] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3 (.I0(Q[35]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[51] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4 (.I0(Q[43]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[50] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5 (.I0(Q[51]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[49] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6 (.I0(Q[59]), .I1(mem_out[65]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ), .O(\not_strict_mode.app_rd_data_reg[48] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5 (.I0(Q[3]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[55] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6 (.I0(Q[11]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[244] ), .O(\not_strict_mode.app_rd_data_reg[54] )); (* SOFT_HLUTNM = "soft_lutpair785" *) LUT5 #( .INIT(32'hFFFFF888)) phy_if_empty_r_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .O(phy_if_empty_r_reg)); (* SOFT_HLUTNM = "soft_lutpair785" *) LUT5 #( .INIT(32'h00000777)) phy_rddata_en_r1_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[0]), .I2(if_empty_r_0), .I3(my_empty[0]), .I4(\my_empty_reg[4]_0 ), .O(phy_rddata_en)); (* SOFT_HLUTNM = "soft_lutpair787" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1__0 (.I0(my_empty_0[1]), .I1(\wr_ptr[1]_i_3__0_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair787" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1__0 (.I0(rd_ptr[0]), .I1(my_empty_0[1]), .I2(\wr_ptr[1]_i_3__0_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1__0_n_0 )); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1__0_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1__0_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__2 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3__0_n_0 ), .I2(my_empty_0[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__5 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3__0_n_0 ), .I4(my_empty_0[1]), .O(\rd_ptr_timing[1]_i_1__5_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__2_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__5_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); LUT2 #( .INIT(4'h6)) \read_fifo.tail_r[0]_i_1 (.I0(\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .I1(tail_r), .O(\read_fifo.tail_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair786" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__4 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3__0_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__4_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__4 (.I0(wr_ptr[0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(my_empty_0[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3__0_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__4_n_0 )); LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2__0 (.I0(my_empty_0[0]), .O(my_empty_0[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3__0 (.I0(\rd_ptr_timing_reg[1]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(D_byte_rd_en), .I3(A_byte_rd_en), .I4(if_empty_r_0), .I5(my_empty[1]), .O(\wr_ptr[1]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair820" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_4__0 (.I0(my_empty_0[0]), .O(\rd_ptr_timing_reg[1]_0 )); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_6 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(\rd_ptr_timing_reg[1]_0 ), .O(B_byte_rd_en)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__4_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__4_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_if_post_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_8 (\wr_ptr_reg[1]_0 , \not_strict_mode.app_rd_data_reg[252] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[24] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , \not_strict_mode.app_rd_data_reg[31]_0 , A_byte_rd_en, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , ififo_rst, CLK, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] , \byte_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \byte_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , A, Q, D_byte_rd_en, B_byte_rd_en, if_empty_r_0, my_empty, \po_stg2_wrcal_cnt_reg[1] ); output \wr_ptr_reg[1]_0 ; output \not_strict_mode.app_rd_data_reg[252] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[24] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output A_byte_rd_en; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; input ififo_rst; input CLK; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; input \byte_r_reg[0] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input \byte_r_reg[1] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]A; input [65:0]Q; input D_byte_rd_en; input B_byte_rd_en; input [0:0]if_empty_r_0; input [0:0]my_empty; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]A; wire A_byte_rd_en; wire B_byte_rd_en; wire CLK; wire D_byte_rd_en; wire [65:0]Q; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire [63:0]\data_bytes_r_reg[63] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire [0:0]if_empty_r_0; wire ififo_rst; wire [63:1]mem_out; wire mem_reg_0_3_60_65_n_4; wire mem_reg_0_3_60_65_n_5; wire [0:0]my_empty; wire \my_empty[4]_i_1__2_n_0 ; wire \my_empty[4]_i_2_n_0 ; wire [3:1]my_empty_0; wire \my_empty_reg[4]_rep__0_n_0 ; wire \my_empty_reg[4]_rep_n_0 ; wire [1:0]my_full; wire \my_full[0]_i_1_n_0 ; wire \my_full[0]_i_2_n_0 ; wire \my_full[1]_i_1_n_0 ; wire \my_full[1]_i_2_n_0 ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [63:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ; wire p_0_out; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [1:0]rd_ptr; wire \rd_ptr[0]_i_1_n_0 ; wire \rd_ptr[1]_i_1_n_0 ; (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing; wire \rd_ptr_timing[0]_i_1__0_n_0 ; wire \rd_ptr_timing[1]_i_1__4_n_0 ; wire \read_fifo.fifo_out_data_r_reg[6] ; (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en; wire [1:0]wr_ptr; wire \wr_ptr[0]_i_1__2_n_0 ; wire \wr_ptr[1]_i_1__2_n_0 ; wire \wr_ptr[1]_i_3_n_0 ; wire \wr_ptr_reg[1]_0 ; wire [1:0]NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED; LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\data_bytes_r_reg[63] [0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[10]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\data_bytes_r_reg[63] [10])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[11]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\data_bytes_r_reg[63] [11])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[12]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\data_bytes_r_reg[63] [12])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[13]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\data_bytes_r_reg[63] [13])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[14]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\data_bytes_r_reg[63] [14])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[15]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\data_bytes_r_reg[63] [15])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[16]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(\data_bytes_r_reg[63] [16])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[17]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\data_bytes_r_reg[63] [17])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[18]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\data_bytes_r_reg[63] [18])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[19]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\data_bytes_r_reg[63] [19])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\data_bytes_r_reg[63] [1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[20]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\data_bytes_r_reg[63] [20])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[21]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\data_bytes_r_reg[63] [21])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[22]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\data_bytes_r_reg[63] [22])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[23]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\data_bytes_r_reg[63] [23])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[24]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\data_bytes_r_reg[63] [24])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[25]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\data_bytes_r_reg[63] [25])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[26]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\data_bytes_r_reg[63] [26])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[27]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\data_bytes_r_reg[63] [27])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[28]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\data_bytes_r_reg[63] [28])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[29]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\data_bytes_r_reg[63] [29])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\data_bytes_r_reg[63] [2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[30]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\data_bytes_r_reg[63] [30])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[31]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\data_bytes_r_reg[63] [31])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[32]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\data_bytes_r_reg[63] [32])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[33]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\data_bytes_r_reg[63] [33])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[34]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\data_bytes_r_reg[63] [34])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[35]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\data_bytes_r_reg[63] [35])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[36]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\data_bytes_r_reg[63] [36])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[37]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\data_bytes_r_reg[63] [37])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[38]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\data_bytes_r_reg[63] [38])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[39]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\data_bytes_r_reg[63] [39])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\data_bytes_r_reg[63] [3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[40]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\data_bytes_r_reg[63] [40])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[41]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\data_bytes_r_reg[63] [41])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[42]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\data_bytes_r_reg[63] [42])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[43]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\data_bytes_r_reg[63] [43])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[44]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\data_bytes_r_reg[63] [44])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[45]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\data_bytes_r_reg[63] [45])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[46]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\data_bytes_r_reg[63] [46])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[47]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\data_bytes_r_reg[63] [47])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[48]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\data_bytes_r_reg[63] [48])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[49]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\data_bytes_r_reg[63] [49])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\data_bytes_r_reg[63] [4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[50]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\data_bytes_r_reg[63] [50])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[51]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\data_bytes_r_reg[63] [51])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[52]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\data_bytes_r_reg[63] [52])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[53]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\data_bytes_r_reg[63] [53])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[54]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\data_bytes_r_reg[63] [54])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[55]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\data_bytes_r_reg[63] [55])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[56]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\data_bytes_r_reg[63] [56])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[57]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\data_bytes_r_reg[63] [57])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[58]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\data_bytes_r_reg[63] [58])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[59]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\data_bytes_r_reg[63] [59])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\data_bytes_r_reg[63] [5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[60]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\data_bytes_r_reg[63] [60])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[61]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\data_bytes_r_reg[63] [61])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[62]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\data_bytes_r_reg[63] [62])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[63]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\data_bytes_r_reg[63] [63])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\data_bytes_r_reg[63] [6])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\data_bytes_r_reg[63] [7])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[8]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\data_bytes_r_reg[63] [8])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \data_bytes_r[9]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I2(\byte_r_reg[0] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I4(\byte_r_reg[1] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\data_bytes_r_reg[63] [9])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\gen_mux_rd[0].mux_rd_fall0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\gen_mux_rd[0].mux_rd_fall1_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\gen_mux_rd[0].mux_rd_fall2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\gen_mux_rd[0].mux_rd_fall3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(\gen_mux_rd[0].mux_rd_rise1_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise2_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\gen_mux_rd[0].mux_rd_rise2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\gen_mux_rd[0].mux_rd_rise3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\gen_mux_rd[2].mux_rd_fall0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\gen_mux_rd[2].mux_rd_fall1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\gen_mux_rd[2].mux_rd_fall2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\gen_mux_rd[2].mux_rd_rise1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\gen_mux_rd[2].mux_rd_rise2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\gen_mux_rd[2].mux_rd_rise3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[3].mux_rd_rise3_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\gen_mux_rd[4].mux_rd_fall0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\gen_mux_rd[4].mux_rd_fall1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\gen_mux_rd[4].mux_rd_fall2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\gen_mux_rd[4].mux_rd_fall3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\gen_mux_rd[4].mux_rd_rise1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise2_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\gen_mux_rd[4].mux_rd_rise2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\gen_mux_rd[4].mux_rd_rise3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\gen_mux_rd[5].mux_rd_rise0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\gen_mux_rd[6].mux_rd_fall0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\gen_mux_rd[6].mux_rd_fall1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\gen_mux_rd[6].mux_rd_fall2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\gen_mux_rd[6].mux_rd_fall3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\gen_mux_rd[6].mux_rd_rise0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\gen_mux_rd[6].mux_rd_rise1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\gen_mux_rd[6].mux_rd_rise2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\gen_mux_rd[6].mux_rd_rise3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\gen_mux_rd[7].mux_rd_rise0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I2(A[1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I4(A[0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd[7].mux_rd_rise3_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I2(\rd_mux_sel_r_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I4(\rd_mux_sel_r_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ), .O(p_0_out)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] [1]), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .I4(\po_stg2_wrcal_cnt_reg[1] [0]), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] )); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_0_5 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[1:0]), .DIB(Q[3:2]), .DIC(Q[5:4]), .DID({1'b0,1'b0}), .DOA({mem_out[1],\not_strict_mode.app_rd_data_reg[31]_0 }), .DOB(mem_out[3:2]), .DOC(mem_out[5:4]), .DOD(NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0151)) mem_reg_0_3_0_5_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_full[0]), .I2(\wr_ptr[1]_i_3_n_0 ), .I3(my_empty_0[2]), .O(wr_en)); LUT1 #( .INIT(2'h2)) mem_reg_0_3_0_5_i_2 (.I0(\wr_ptr_reg[1]_0 ), .O(my_empty_0[2])); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_12_17 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[13:12]), .DIB(Q[15:14]), .DIC(Q[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(mem_out[17:16]), .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_18_23 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[19:18]), .DIB(Q[21:20]), .DIC(Q[23:22]), .DID({1'b0,1'b0}), .DOA(mem_out[19:18]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_24_29 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[25:24]), .DIB(Q[27:26]), .DIC(Q[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[25:24]), .DOB(mem_out[27:26]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_30_35 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[31:30]), .DIB(Q[33:32]), .DIC(Q[35:34]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(mem_out[33:32]), .DOC(mem_out[35:34]), .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_36_41 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[37:36]), .DIB(Q[39:38]), .DIC(Q[41:40]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(mem_out[41:40]), .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_42_47 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[43:42]), .DIB(Q[45:44]), .DIC(Q[47:46]), .DID({1'b0,1'b0}), .DOA(mem_out[43:42]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_48_53 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[49:48]), .DIB(Q[51:50]), .DIC(Q[53:52]), .DID({1'b0,1'b0}), .DOA(mem_out[49:48]), .DOB(mem_out[51:50]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_54_59 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[55:54]), .DIB(Q[57:56]), .DIC(Q[59:58]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(mem_out[57:56]), .DOC(mem_out[59:58]), .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_60_65 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[61:60]), .DIB(Q[63:62]), .DIC(Q[65:64]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}), .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_3_6_11 (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}), .ADDRD({1'b0,1'b0,1'b0,wr_ptr}), .DIA(Q[7:6]), .DIB(Q[9:8]), .DIC(Q[11:10]), .DID({1'b0,1'b0}), .DOA(mem_out[7:6]), .DOB(mem_out[9:8]), .DOC(mem_out[11:10]), .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h0140)) \my_empty[4]_i_1__2 (.I0(my_full[1]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\wr_ptr[1]_i_3_n_0 ), .I3(my_empty_0[1]), .O(\my_empty[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_empty[4]_i_2 (.I0(wr_ptr[1]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(wr_ptr[0]), .I4(my_empty_0[1]), .O(\my_empty[4]_i_2_n_0 )); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4] (.C(CLK), .CE(\my_empty[4]_i_1__2_n_0 ), .D(\my_empty[4]_i_2_n_0 ), .Q(\wr_ptr_reg[1]_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep (.C(CLK), .CE(\my_empty[4]_i_1__2_n_0 ), .D(\my_empty[4]_i_2_n_0 ), .Q(\my_empty_reg[4]_rep_n_0 ), .S(ififo_rst)); (* ORIG_CELL_NAME = "my_empty_reg[4]" *) FDSE \my_empty_reg[4]_rep__0 (.C(CLK), .CE(\my_empty[4]_i_1__2_n_0 ), .D(\my_empty[4]_i_2_n_0 ), .Q(\my_empty_reg[4]_rep__0_n_0 ), .S(ififo_rst)); LUT6 #( .INIT(64'hBAAAAAAB8AAAAAA8)) \my_full[0]_i_1 (.I0(my_full[0]), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I4(\wr_ptr[1]_i_3_n_0 ), .I5(\my_full[0]_i_2_n_0 ), .O(\my_full[0]_i_1_n_0 )); LUT5 #( .INIT(32'h00000960)) \my_full[0]_i_2 (.I0(rd_ptr[1]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(rd_ptr[0]), .I4(my_full[1]), .O(\my_full[0]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00411400)) \my_full[1]_i_1 (.I0(\my_full[1]_i_2_n_0 ), .I1(rd_ptr[1]), .I2(wr_ptr[1]), .I3(wr_ptr[0]), .I4(rd_ptr[0]), .I5(my_full[1]), .O(\my_full[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair734" *) LUT4 #( .INIT(16'hBFFE)) \my_full[1]_i_2 (.I0(my_empty_0[1]), .I1(my_full[1]), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(\wr_ptr[1]_i_3_n_0 ), .O(\my_full[1]_i_2_n_0 )); FDRE \my_full_reg[0] (.C(CLK), .CE(1'b1), .D(\my_full[0]_i_1_n_0 ), .Q(my_full[0]), .R(ififo_rst)); FDRE \my_full_reg[1] (.C(CLK), .CE(1'b1), .D(\my_full[1]_i_1_n_0 ), .Q(my_full[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair760" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[120]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[120] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [24])); (* SOFT_HLUTNM = "soft_lutpair761" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[121]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[121] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [25])); (* SOFT_HLUTNM = "soft_lutpair762" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[122]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[122] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [26])); (* SOFT_HLUTNM = "soft_lutpair763" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[123]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[123] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [27])); (* SOFT_HLUTNM = "soft_lutpair764" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[124]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[124] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [28])); (* SOFT_HLUTNM = "soft_lutpair765" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[125]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[125] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [29])); (* SOFT_HLUTNM = "soft_lutpair766" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[126]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[126] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [30])); (* SOFT_HLUTNM = "soft_lutpair767" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[127]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[127] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [31])); (* SOFT_HLUTNM = "soft_lutpair767" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[152]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[152] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [32])); (* SOFT_HLUTNM = "soft_lutpair766" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[153]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[153] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [33])); (* SOFT_HLUTNM = "soft_lutpair765" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[154]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[154] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [34])); (* SOFT_HLUTNM = "soft_lutpair764" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[155]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[155] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [35])); (* SOFT_HLUTNM = "soft_lutpair763" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[156]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[156] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [36])); (* SOFT_HLUTNM = "soft_lutpair762" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[157]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[157] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [37])); (* SOFT_HLUTNM = "soft_lutpair761" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[158]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[158] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [38])); (* SOFT_HLUTNM = "soft_lutpair760" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[159]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[159] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [39])); (* SOFT_HLUTNM = "soft_lutpair759" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[184]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[184] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [40])); (* SOFT_HLUTNM = "soft_lutpair758" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[185]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[185] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [41])); (* SOFT_HLUTNM = "soft_lutpair757" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[186]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[186] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [42])); (* SOFT_HLUTNM = "soft_lutpair756" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[187]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[187] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [43])); (* SOFT_HLUTNM = "soft_lutpair755" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[188]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[188] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [44])); (* SOFT_HLUTNM = "soft_lutpair754" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[189]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[189] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [45])); (* SOFT_HLUTNM = "soft_lutpair753" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[190]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[190] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [46])); (* SOFT_HLUTNM = "soft_lutpair752" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[191]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[191] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [47])); (* SOFT_HLUTNM = "soft_lutpair751" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[216]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[216] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [48])); (* SOFT_HLUTNM = "soft_lutpair750" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[217]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[217] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [49])); (* SOFT_HLUTNM = "soft_lutpair749" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[218]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[218] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [50])); (* SOFT_HLUTNM = "soft_lutpair748" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[219]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[219] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [51])); (* SOFT_HLUTNM = "soft_lutpair747" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[220]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[220] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [52])); (* SOFT_HLUTNM = "soft_lutpair746" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[221]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[221] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [53])); (* SOFT_HLUTNM = "soft_lutpair745" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[222]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[222] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [54])); (* SOFT_HLUTNM = "soft_lutpair744" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[223]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[223] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [55])); (* SOFT_HLUTNM = "soft_lutpair743" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[248]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[248] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [56])); (* SOFT_HLUTNM = "soft_lutpair742" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[249]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[249] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [57])); (* SOFT_HLUTNM = "soft_lutpair736" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[24]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[24] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair741" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[250]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[250] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [58])); (* SOFT_HLUTNM = "soft_lutpair740" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[251]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[251] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [59])); (* SOFT_HLUTNM = "soft_lutpair739" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[252]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[252]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [60])); (* SOFT_HLUTNM = "soft_lutpair738" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[253]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[253] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [61])); (* SOFT_HLUTNM = "soft_lutpair737" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[254]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[254] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [62])); (* SOFT_HLUTNM = "soft_lutpair736" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[255]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[255] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [63])); (* SOFT_HLUTNM = "soft_lutpair737" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[25]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[25] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair738" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[26]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[26] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair739" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[27]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[27] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [3])); (* SOFT_HLUTNM = "soft_lutpair740" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[28]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[28] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [4])); (* SOFT_HLUTNM = "soft_lutpair741" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[29]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[29] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [5])); (* SOFT_HLUTNM = "soft_lutpair742" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[30]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[30] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [6])); (* SOFT_HLUTNM = "soft_lutpair743" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[31]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[31] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [7])); (* SOFT_HLUTNM = "soft_lutpair744" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[56]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[56] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [8])); (* SOFT_HLUTNM = "soft_lutpair745" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[57]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[57] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [9])); (* SOFT_HLUTNM = "soft_lutpair746" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[58]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[58] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [10])); (* SOFT_HLUTNM = "soft_lutpair747" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[59]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[59] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [11])); (* SOFT_HLUTNM = "soft_lutpair748" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[60]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[60] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [12])); (* SOFT_HLUTNM = "soft_lutpair749" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[61]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[61] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [13])); (* SOFT_HLUTNM = "soft_lutpair750" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[62]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[62] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [14])); (* SOFT_HLUTNM = "soft_lutpair751" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[63]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[63] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [15])); (* SOFT_HLUTNM = "soft_lutpair752" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[88]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[88] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [16])); (* SOFT_HLUTNM = "soft_lutpair753" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[89]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[89] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [17])); (* SOFT_HLUTNM = "soft_lutpair754" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[90]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[90] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [18])); (* SOFT_HLUTNM = "soft_lutpair755" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[91]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[91] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [19])); (* SOFT_HLUTNM = "soft_lutpair756" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[92]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[92] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [20])); (* SOFT_HLUTNM = "soft_lutpair757" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[93]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[93] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [21])); (* SOFT_HLUTNM = "soft_lutpair758" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[94]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[94] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [22])); (* SOFT_HLUTNM = "soft_lutpair759" *) LUT3 #( .INIT(8'hB8)) \not_strict_mode.app_rd_data[95]_i_1 (.I0(\not_strict_mode.app_rd_data_reg[95] ), .I1(\read_fifo.fifo_out_data_r_reg[6] ), .I2(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]), .O(\not_strict_mode.app_rd_data_reg[255]_0 [23])); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3 (.I0(Q[1]), .I1(mem_out[1]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[63] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4 (.I0(Q[9]), .I1(mem_out[9]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[62] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5 (.I0(Q[17]), .I1(mem_out[17]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[61] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6 (.I0(Q[25]), .I1(mem_out[25]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[60] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1 (.I0(Q[50]), .I1(mem_out[50]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[89] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2 (.I0(Q[58]), .I1(mem_out[58]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[88] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1 (.I0(Q[2]), .I1(mem_out[2]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[95] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2 (.I0(Q[10]), .I1(mem_out[10]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[94] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3 (.I0(Q[18]), .I1(mem_out[18]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[93] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4 (.I0(Q[26]), .I1(mem_out[26]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[92] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5 (.I0(Q[34]), .I1(mem_out[34]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[91] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6 (.I0(Q[42]), .I1(mem_out[42]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[90] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1 (.I0(Q[19]), .I1(mem_out[19]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[125] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2 (.I0(Q[27]), .I1(mem_out[27]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[124] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3 (.I0(Q[35]), .I1(mem_out[35]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[123] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4 (.I0(Q[43]), .I1(mem_out[43]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[122] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5 (.I0(Q[51]), .I1(mem_out[51]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[121] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6 (.I0(Q[59]), .I1(mem_out[59]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[120] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5 (.I0(Q[3]), .I1(mem_out[3]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[127] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_6 (.I0(Q[11]), .I1(mem_out[11]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[126] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1 (.I0(Q[36]), .I1(mem_out[36]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[155] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2 (.I0(Q[44]), .I1(mem_out[44]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[154] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3 (.I0(Q[52]), .I1(mem_out[52]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[153] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4 (.I0(Q[60]), .I1(mem_out[60]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[152] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3 (.I0(Q[4]), .I1(mem_out[4]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[159] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4 (.I0(Q[12]), .I1(mem_out[12]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[158] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5 (.I0(Q[20]), .I1(mem_out[20]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[157] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_6 (.I0(Q[28]), .I1(mem_out[28]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[156] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1 (.I0(Q[53]), .I1(mem_out[53]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[185] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2 (.I0(Q[61]), .I1(mem_out[61]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[184] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1 (.I0(Q[5]), .I1(mem_out[5]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[191] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2 (.I0(Q[13]), .I1(mem_out[13]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[190] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3 (.I0(Q[21]), .I1(mem_out[21]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[189] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4 (.I0(Q[29]), .I1(mem_out[29]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[188] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5 (.I0(Q[37]), .I1(mem_out[37]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[187] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_6 (.I0(Q[45]), .I1(mem_out[45]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[186] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1 (.I0(Q[22]), .I1(mem_out[22]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[221] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2 (.I0(Q[30]), .I1(mem_out[30]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[220] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3 (.I0(Q[38]), .I1(mem_out[38]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[219] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4 (.I0(Q[46]), .I1(mem_out[46]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[218] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5 (.I0(Q[54]), .I1(mem_out[54]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[217] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_6 (.I0(Q[62]), .I1(mem_out[62]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[216] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5 (.I0(Q[6]), .I1(mem_out[6]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[223] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_6 (.I0(Q[14]), .I1(mem_out[14]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[222] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1 (.I0(Q[39]), .I1(mem_out[39]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[251] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2 (.I0(Q[47]), .I1(mem_out[47]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[250] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3 (.I0(Q[55]), .I1(mem_out[55]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[249] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4 (.I0(Q[63]), .I1(mem_out[63]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[248] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1 (.I0(Q[7]), .I1(mem_out[7]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[255] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2 (.I0(Q[15]), .I1(mem_out[15]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[254] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3 (.I0(Q[23]), .I1(mem_out[23]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[253] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4 (.I0(Q[31]), .I1(mem_out[31]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[252]_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1 (.I0(Q[16]), .I1(mem_out[16]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[29] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2 (.I0(Q[24]), .I1(mem_out[24]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[28] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3 (.I0(Q[32]), .I1(mem_out[32]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[27] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4 (.I0(Q[40]), .I1(mem_out[40]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[26] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5 (.I0(Q[48]), .I1(mem_out[48]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[25] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6 (.I0(Q[56]), .I1(mem_out[56]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[24] )); LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_7 (.I0(\my_empty_reg[4]_rep_n_0 ), .O(\not_strict_mode.app_rd_data_reg[252] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8 (.I0(\my_empty_reg[4]_rep__0_n_0 ), .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5 (.I0(Q[0]), .I1(\not_strict_mode.app_rd_data_reg[31]_0 ), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[31] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6 (.I0(Q[8]), .I1(mem_out[8]), .I2(\not_strict_mode.app_rd_data_reg[252] ), .O(\not_strict_mode.app_rd_data_reg[30] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1 (.I0(Q[33]), .I1(mem_out[33]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[59] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2 (.I0(Q[41]), .I1(mem_out[41]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[58] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3 (.I0(Q[49]), .I1(mem_out[49]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[57] )); LUT3 #( .INIT(8'hAC)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4 (.I0(Q[57]), .I1(mem_out[57]), .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ), .O(\not_strict_mode.app_rd_data_reg[56] )); (* SOFT_HLUTNM = "soft_lutpair735" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[0]_i_1 (.I0(my_empty_0[1]), .I1(\wr_ptr[1]_i_3_n_0 ), .I2(rd_ptr[0]), .O(\rd_ptr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair735" *) LUT4 #( .INIT(16'hDF20)) \rd_ptr[1]_i_1 (.I0(rd_ptr[0]), .I1(my_empty_0[1]), .I2(\wr_ptr[1]_i_3_n_0 ), .I3(rd_ptr[1]), .O(\rd_ptr[1]_i_1_n_0 )); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr[0]_i_1_n_0 ), .Q(rd_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr[1]_i_1_n_0 ), .Q(rd_ptr[1]), .R(ififo_rst)); LUT4 #( .INIT(16'hA2AE)) \rd_ptr_timing[0]_i_1__0 (.I0(rd_ptr_timing[0]), .I1(\wr_ptr[1]_i_3_n_0 ), .I2(my_empty_0[1]), .I3(rd_ptr[0]), .O(\rd_ptr_timing[0]_i_1__0_n_0 )); LUT5 #( .INIT(32'hF0F066F0)) \rd_ptr_timing[1]_i_1__4 (.I0(rd_ptr[0]), .I1(rd_ptr[1]), .I2(rd_ptr_timing[1]), .I3(\wr_ptr[1]_i_3_n_0 ), .I4(my_empty_0[1]), .O(\rd_ptr_timing[1]_i_1__4_n_0 )); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[0]_i_1__0_n_0 ), .Q(rd_ptr_timing[0]), .R(ififo_rst)); (* KEEP = "yes" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_ptr_timing[1]_i_1__4_n_0 ), .Q(rd_ptr_timing[1]), .R(ififo_rst)); (* SOFT_HLUTNM = "soft_lutpair734" *) LUT5 #( .INIT(32'hEEFA1105)) \wr_ptr[0]_i_1__2 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[1]), .I2(my_full[1]), .I3(\wr_ptr[1]_i_3_n_0 ), .I4(wr_ptr[0]), .O(\wr_ptr[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'hFDFDFFDD02020022)) \wr_ptr[1]_i_1__2 (.I0(wr_ptr[0]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(my_empty_0[1]), .I3(my_full[1]), .I4(\wr_ptr[1]_i_3_n_0 ), .I5(wr_ptr[1]), .O(\wr_ptr[1]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair768" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_2 (.I0(\wr_ptr_reg[1]_0 ), .O(my_empty_0[1])); LUT6 #( .INIT(64'h0000700070007000)) \wr_ptr[1]_i_3 (.I0(my_empty_0[3]), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(D_byte_rd_en), .I3(B_byte_rd_en), .I4(if_empty_r_0), .I5(my_empty), .O(\wr_ptr[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair768" *) LUT1 #( .INIT(2'h2)) \wr_ptr[1]_i_4 (.I0(\wr_ptr_reg[1]_0 ), .O(my_empty_0[3])); LUT2 #( .INIT(4'h7)) \wr_ptr[1]_i_5 (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I1(my_empty_0[3]), .O(A_byte_rd_en)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_ptr[0]_i_1__2_n_0 ), .Q(wr_ptr[0]), .R(ififo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_ptr[1]_i_1__2_n_0 ), .Q(wr_ptr[1]), .R(ififo_rst)); endmodule module ddr3_if_mig_7series_v4_0_ddr_mc_phy (\rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, idelay_ld_rst, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , idelay_ld_rst_0, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , idelay_ld_rst_1, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , idelay_ld_rst_2, \calib_seq_reg[0] , \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[228] , \my_empty_reg[1] , \my_empty_reg[1]_0 , phy_mc_ctl_full, \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \my_empty_reg[1]_3 , \my_empty_reg[1]_4 , \my_empty_reg[1]_5 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , \my_empty_reg[1]_6 , phy_rddata_en, mux_rd_valid_r_reg, rst_sync_r1_reg, \byte_r_reg[0] , \po_counter_read_val_r_reg[5] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \read_fifo.tail_r_reg[0] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , of_ctl_full_v, pi_phase_locked_all_r1_reg, \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , wr_en, wr_en_5, wr_en_6, \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7] , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7]_1 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7]_2 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \po_rdval_cnt_reg[8] , \pi_rdval_cnt_reg[5] , \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , \po_rdval_cnt_reg[8]_0 , phy_if_empty_r_reg, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , ddr_ck_out, \my_empty_reg[7]_3 , CLK, init_calib_complete_reg_rep__6, D5, D6, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, D0, D1, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, \calib_sel_reg[0]_2 , sync_pulse, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , \calib_sel_reg[1]_2 , \calib_sel_reg[1]_3 , \gen_byte_sel_div1.calib_in_common_reg_1 , \calib_sel_reg[1]_4 , \calib_sel_reg[1]_5 , \calib_sel_reg[1]_6 , phy_ctl_wr_i2, pll_locked, phy_read_calib, in0, phy_write_calib, Q, \data_offset_1_i2_reg[5] , \gen_byte_sel_div1.calib_in_common_reg_2 , \calib_sel_reg[0]_3 , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, mem_dqs_in, \gen_byte_sel_div1.calib_in_common_reg_3 , COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_4 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_5 , mem_dq_in, idelay_inc, LD0, CLKB0, phy_if_reset, \gen_byte_sel_div1.calib_in_common_reg_6 , \calib_sel_reg[0]_4 , pi_en_stg2_f_reg_0, pi_stg2_f_incdec_reg_0, \gen_byte_sel_div1.calib_in_common_reg_7 , \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_8 , ck_po_stg2_f_en_reg_0, ck_po_stg2_f_indec_reg_0, delay_done_r4_reg_0, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_9 , LD0_3, CLKB0_7, \gen_byte_sel_div1.calib_in_common_reg_10 , \calib_sel_reg[1]_7 , pi_en_stg2_f_reg_1, pi_stg2_f_incdec_reg_1, \gen_byte_sel_div1.calib_in_common_reg_11 , \calib_zero_inputs_reg[0]_0 , \gen_byte_sel_div1.calib_in_common_reg_12 , ck_po_stg2_f_en_reg_1, ck_po_stg2_f_indec_reg_1, delay_done_r4_reg_1, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_13 , LD0_4, CLKB0_8, \gen_byte_sel_div1.calib_in_common_reg_14 , \calib_sel_reg[0]_5 , pi_en_stg2_f_reg_2, pi_stg2_f_incdec_reg_2, \gen_byte_sel_div1.calib_in_common_reg_15 , \calib_zero_inputs_reg[0]_1 , \gen_byte_sel_div1.calib_in_common_reg_16 , ck_po_stg2_f_en_reg_2, ck_po_stg2_f_indec_reg_2, delay_done_r4_reg_2, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_17 , LD0_5, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, mux_cmd_wren, mem_out, \rd_ptr_reg[3] , mux_wrdata_en, \rd_ptr_reg[3]_0 , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, init_calib_complete_reg_rep__5, mc_cas_n, \cmd_pipe_plus.mc_address_reg[43] , init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , prbs_rdlvl_start_reg, out, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, \byte_r_reg[0]_0 , \byte_r_reg[1] , tail_r, \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , A, mux_wrdata, mux_wrdata_mask, E, \fine_delay_mod_reg[23] , \gen_byte_sel_div1.calib_in_common_reg_18 , \calib_sel_reg[0]_6 , \gen_byte_sel_div1.calib_in_common_reg_19 , \calib_sel_reg[1]_8 , \gen_byte_sel_div1.calib_in_common_reg_20 , \calib_sel_reg[0]_7 , \calib_sel_reg[3] , \po_stg2_wrcal_cnt_reg[1] , D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , phy_dout, init_calib_complete_reg_rep__6_0); output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output [3:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output [3:0]mem_dqs_out; output [3:0]mem_dqs_ts; output [59:0]mem_dq_out; output [35:0]mem_dq_ts; output idelay_ld_rst; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output idelay_ld_rst_0; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output idelay_ld_rst_1; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output idelay_ld_rst_2; output \calib_seq_reg[0] ; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[228] ; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output phy_mc_ctl_full; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \my_empty_reg[1]_3 ; output \my_empty_reg[1]_4 ; output \my_empty_reg[1]_5 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output \my_empty_reg[1]_6 ; output phy_rddata_en; output mux_rd_valid_r_reg; output rst_sync_r1_reg; output \byte_r_reg[0] ; output [5:0]\po_counter_read_val_r_reg[5] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \read_fifo.tail_r_reg[0] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output [0:0]of_ctl_full_v; output pi_phase_locked_all_r1_reg; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output wr_en; output wr_en_5; output wr_en_6; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7] ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7]_2 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [4:0]\po_rdval_cnt_reg[8] ; output [5:0]\pi_rdval_cnt_reg[5] ; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output [4:0]\po_rdval_cnt_reg[8]_0 ; output phy_if_empty_r_reg; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output [1:0]ddr_ck_out; output [31:0]\my_empty_reg[7]_3 ; input CLK; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [2:0]D0; input [2:0]D1; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[0]_2 ; input sync_pulse; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input \calib_sel_reg[1]_2 ; input \calib_sel_reg[1]_3 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \calib_sel_reg[1]_4 ; input \calib_sel_reg[1]_5 ; input \calib_sel_reg[1]_6 ; input phy_ctl_wr_i2; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input [10:0]Q; input [5:0]\data_offset_1_i2_reg[5] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \calib_sel_reg[0]_3 ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input [3:0]mem_dqs_in; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_4 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_5 ; input [31:0]mem_dq_in; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input \gen_byte_sel_div1.calib_in_common_reg_6 ; input \calib_sel_reg[0]_4 ; input pi_en_stg2_f_reg_0; input pi_stg2_f_incdec_reg_0; input \gen_byte_sel_div1.calib_in_common_reg_7 ; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_8 ; input ck_po_stg2_f_en_reg_0; input ck_po_stg2_f_indec_reg_0; input delay_done_r4_reg_0; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_9 ; input LD0_3; input CLKB0_7; input \gen_byte_sel_div1.calib_in_common_reg_10 ; input \calib_sel_reg[1]_7 ; input pi_en_stg2_f_reg_1; input pi_stg2_f_incdec_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_11 ; input [5:0]\calib_zero_inputs_reg[0]_0 ; input \gen_byte_sel_div1.calib_in_common_reg_12 ; input ck_po_stg2_f_en_reg_1; input ck_po_stg2_f_indec_reg_1; input delay_done_r4_reg_1; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_13 ; input LD0_4; input CLKB0_8; input \gen_byte_sel_div1.calib_in_common_reg_14 ; input \calib_sel_reg[0]_5 ; input pi_en_stg2_f_reg_2; input pi_stg2_f_incdec_reg_2; input \gen_byte_sel_div1.calib_in_common_reg_15 ; input [5:0]\calib_zero_inputs_reg[0]_1 ; input \gen_byte_sel_div1.calib_in_common_reg_16 ; input ck_po_stg2_f_en_reg_2; input ck_po_stg2_f_indec_reg_2; input delay_done_r4_reg_2; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_17 ; input LD0_5; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input mux_cmd_wren; input [11:0]mem_out; input [33:0]\rd_ptr_reg[3] ; input mux_wrdata_en; input [17:0]\rd_ptr_reg[3]_0 ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input init_calib_complete_reg_rep; input [31:0]\write_buffer.wr_buf_out_data_reg[287] ; input prbs_rdlvl_start_reg; input out; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input \byte_r_reg[0]_0 ; input \byte_r_reg[1] ; input [0:0]tail_r; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input [1:0]A; input [255:0]mux_wrdata; input [31:0]mux_wrdata_mask; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; input [7:0]\calib_sel_reg[0]_6 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; input [7:0]\calib_sel_reg[1]_8 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; input [7:0]\calib_sel_reg[0]_7 ; input [2:0]\calib_sel_reg[3] ; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input D_po_sel_fine_oclk_delay125_out; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input [35:0]phy_dout; input init_calib_complete_reg_rep__6_0; wire [1:0]A; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [5:0]COUNTERLOADVAL; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]E; wire LD0; wire LD0_3; wire LD0_4; wire LD0_5; wire [10:0]Q; wire RST0; wire [0:0]_phy_ctl_full_p__0; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[1] ; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire \calib_sel_reg[0]_3 ; wire \calib_sel_reg[0]_4 ; wire \calib_sel_reg[0]_5 ; wire [7:0]\calib_sel_reg[0]_6 ; wire [7:0]\calib_sel_reg[0]_7 ; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire \calib_sel_reg[1]_3 ; wire \calib_sel_reg[1]_4 ; wire \calib_sel_reg[1]_5 ; wire \calib_sel_reg[1]_6 ; wire \calib_sel_reg[1]_7 ; wire [7:0]\calib_sel_reg[1]_8 ; wire [2:0]\calib_sel_reg[3] ; wire \calib_seq_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0]_1 ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_en_reg_0; wire ck_po_stg2_f_en_reg_1; wire ck_po_stg2_f_en_reg_2; wire ck_po_stg2_f_indec_reg; wire ck_po_stg2_f_indec_reg_0; wire ck_po_stg2_f_indec_reg_1; wire ck_po_stg2_f_indec_reg_2; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire [63:0]\data_bytes_r_reg[63] ; wire [5:0]\data_offset_1_i2_reg[5] ; wire [1:0]ddr_ck_out; wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ; wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ; wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ; wire delay_done_r4_reg; wire delay_done_r4_reg_0; wire delay_done_r4_reg_1; wire delay_done_r4_reg_2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire [7:0]\fine_delay_mod_reg[23] ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_10 ; wire \gen_byte_sel_div1.calib_in_common_reg_11 ; wire \gen_byte_sel_div1.calib_in_common_reg_12 ; wire \gen_byte_sel_div1.calib_in_common_reg_13 ; wire \gen_byte_sel_div1.calib_in_common_reg_14 ; wire \gen_byte_sel_div1.calib_in_common_reg_15 ; wire \gen_byte_sel_div1.calib_in_common_reg_16 ; wire \gen_byte_sel_div1.calib_in_common_reg_17 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.calib_in_common_reg_4 ; wire \gen_byte_sel_div1.calib_in_common_reg_5 ; wire \gen_byte_sel_div1.calib_in_common_reg_6 ; wire \gen_byte_sel_div1.calib_in_common_reg_7 ; wire \gen_byte_sel_div1.calib_in_common_reg_8 ; wire \gen_byte_sel_div1.calib_in_common_reg_9 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_0; wire idelay_ld_rst_1; wire idelay_ld_rst_2; wire in0; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire [3:0]init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire \mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ; wire \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ; wire mcGo_r_reg_gate_n_0; wire mcGo_r_reg_r_0_n_0; wire mcGo_r_reg_r_10_n_0; wire mcGo_r_reg_r_11_n_0; wire mcGo_r_reg_r_12_n_0; wire mcGo_r_reg_r_13_n_0; wire mcGo_r_reg_r_1_n_0; wire mcGo_r_reg_r_2_n_0; wire mcGo_r_reg_r_3_n_0; wire mcGo_r_reg_r_4_n_0; wire mcGo_r_reg_r_5_n_0; wire mcGo_r_reg_r_6_n_0; wire mcGo_r_reg_r_7_n_0; wire mcGo_r_reg_r_8_n_0; wire mcGo_r_reg_r_9_n_0; wire mcGo_r_reg_r_n_0; wire [1:1]mcGo_w__0; wire [0:0]mc_cas_n; wire [31:0]mem_dq_in; wire [59:0]mem_dq_out; wire [35:0]mem_dq_ts; wire [3:0]mem_dqs_in; wire [3:0]mem_dqs_out; wire [3:0]mem_dqs_ts; wire [11:0]mem_out; wire mem_refclk; wire mmcm_locked; wire mux_cmd_wren; wire mux_rd_valid_r_reg; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire [63:0]\my_empty_reg[7] ; wire [63:0]\my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire [63:0]\my_empty_reg[7]_2 ; wire [31:0]\my_empty_reg[7]_3 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire out; wire p_0_out; wire phy_ctl_mstr_empty; wire phy_ctl_wr_i2; wire [35:0]phy_dout; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_mc_ctl_full; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [3:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_en_stg2_f_reg_0; wire pi_en_stg2_f_reg_1; wire pi_en_stg2_f_reg_2; wire pi_phase_locked_all_r1_reg; wire [5:0]\pi_rdval_cnt_reg[5] ; wire pi_stg2_f_incdec_reg; wire pi_stg2_f_incdec_reg_0; wire pi_stg2_f_incdec_reg_1; wire pi_stg2_f_incdec_reg_2; wire pll_locked; wire [5:0]\po_counter_read_val_r_reg[5] ; wire [5:1]\po_counter_read_val_w[0]_0 ; wire [4:0]\po_rdval_cnt_reg[8] ; wire [4:0]\po_rdval_cnt_reg[8]_0 ; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rclk_delay_11; wire \rclk_delay_reg[10]_srl11_i_1_n_0 ; wire rd_buf_we; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [33:0]\rd_ptr_reg[3] ; wire [17:0]\rd_ptr_reg[3]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [1:1]ref_dll_lock_w; wire rst_out_i_1_n_0; wire rst_primitives; wire rst_primitives_i_1_n_0; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; wire [31:0]\write_buffer.wr_buf_out_data_reg[287] ; ddr3_if_mig_7series_v4_0_ddr_phy_4lanes \ddr_phy_4lanes_0.u_ddr_phy_4lanes (.A(A), .CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .COUNTERLOADVAL(COUNTERLOADVAL), .DOA(DOA), .DOB(DOB), .DOC(DOC), .E(E), .LD0(LD0), .LD0_3(LD0_3), .LD0_4(LD0_4), .LD0_5(LD0_5), .Q(Q), .RST0(RST0), ._phy_ctl_full_p__0(_phy_ctl_full_p__0), .\byte_r_reg[0] (\byte_r_reg[0]_0 ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\calib_sel_reg[0] (\calib_sel_reg[0]_3 ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_4 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_5 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_6 ), .\calib_sel_reg[0]_3 (\calib_sel_reg[0]_7 ), .\calib_sel_reg[1] (\calib_sel_reg[1]_7 ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_8 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[3] [1:0]), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ), .\calib_zero_inputs_reg[0]_0 (\calib_zero_inputs_reg[0]_0 ), .\calib_zero_inputs_reg[0]_1 (\calib_zero_inputs_reg[0]_1 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg), .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0), .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1), .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg), .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0), .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1), .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .delay_done_r4_reg(delay_done_r4_reg), .delay_done_r4_reg_0(delay_done_r4_reg_0), .delay_done_r4_reg_1(delay_done_r4_reg_1), .delay_done_r4_reg_2(delay_done_r4_reg_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23] ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_4 ), .\gen_byte_sel_div1.calib_in_common_reg_10 (\gen_byte_sel_div1.calib_in_common_reg_13 ), .\gen_byte_sel_div1.calib_in_common_reg_11 (\gen_byte_sel_div1.calib_in_common_reg_14 ), .\gen_byte_sel_div1.calib_in_common_reg_12 (\gen_byte_sel_div1.calib_in_common_reg_15 ), .\gen_byte_sel_div1.calib_in_common_reg_13 (\gen_byte_sel_div1.calib_in_common_reg_16 ), .\gen_byte_sel_div1.calib_in_common_reg_14 (\gen_byte_sel_div1.calib_in_common_reg_17 ), .\gen_byte_sel_div1.calib_in_common_reg_15 (\gen_byte_sel_div1.calib_in_common_reg_18 ), .\gen_byte_sel_div1.calib_in_common_reg_16 (\gen_byte_sel_div1.calib_in_common_reg_19 ), .\gen_byte_sel_div1.calib_in_common_reg_17 (\gen_byte_sel_div1.calib_in_common_reg_20 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_5 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_6 ), .\gen_byte_sel_div1.calib_in_common_reg_4 (\gen_byte_sel_div1.calib_in_common_reg_7 ), .\gen_byte_sel_div1.calib_in_common_reg_5 (\gen_byte_sel_div1.calib_in_common_reg_8 ), .\gen_byte_sel_div1.calib_in_common_reg_6 (\gen_byte_sel_div1.calib_in_common_reg_9 ), .\gen_byte_sel_div1.calib_in_common_reg_7 (\gen_byte_sel_div1.calib_in_common_reg_10 ), .\gen_byte_sel_div1.calib_in_common_reg_8 (\gen_byte_sel_div1.calib_in_common_reg_11 ), .\gen_byte_sel_div1.calib_in_common_reg_9 (\gen_byte_sel_div1.calib_in_common_reg_12 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .idelay_ld_rst_0(idelay_ld_rst_0), .idelay_ld_rst_1(idelay_ld_rst_1), .idelay_ld_rst_2(idelay_ld_rst_2), .in0(in0), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ), .mcGo_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ), .mcGo_w__0(mcGo_w__0), .mem_dq_in(mem_dq_in), .mem_dq_out(mem_dq_out[35:0]), .mem_dq_ts(mem_dq_ts), .mem_dqs_in(mem_dqs_in), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .mem_refclk(mem_refclk), .mmcm_locked(mmcm_locked), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .mux_wrdata(mux_wrdata), .mux_wrdata_en(mux_wrdata_en), .mux_wrdata_mask(mux_wrdata_mask), .\my_empty_reg[1] (\my_empty_reg[1]_2 ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_3 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_4 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_5 ), .\my_empty_reg[7] (\my_empty_reg[7] ), .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ), .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ), .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] 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(\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), 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(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ), 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .ofs_rdy_r_reg(ofs_rdy_r_reg), .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0), .out(out), .p_0_out(p_0_out), .phy_ctl_mstr_empty(phy_ctl_mstr_empty), .phy_ctl_wr_i2(phy_ctl_wr_i2), .phy_ctl_wr_i2_reg(rst_primitives_i_1_n_0), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_if_reset(phy_if_reset), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ), .pi_en_stg2_f_reg(pi_en_stg2_f_reg), .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0), .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1), .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2), .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg), .\pi_rdval_cnt_reg[5] (\pi_rdval_cnt_reg[5] ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg), .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0), .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1), .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2), .pll_locked(pll_locked), .\po_rdval_cnt_reg[8] ({\po_rdval_cnt_reg[8] [4:2],\po_counter_read_val_w[0]_0 [5:4],\po_rdval_cnt_reg[8] [1],\po_counter_read_val_w[0]_0 [2:1],\po_rdval_cnt_reg[8] [0]}), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rclk_delay_11(rclk_delay_11), .\rclk_delay_reg[11]_0 (rst_out_i_1_n_0), .rd_buf_we(rd_buf_we), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .ref_dll_lock_w(ref_dll_lock_w), .rst_primitives(rst_primitives), .rst_primitives_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ), .rst_primitives_reg_1(\rclk_delay_reg[10]_srl11_i_1_n_0 ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .\write_buffer.wr_buf_out_data_reg[224] (\write_buffer.wr_buf_out_data_reg[224] ), .\write_buffer.wr_buf_out_data_reg[225] (\write_buffer.wr_buf_out_data_reg[225] ), .\write_buffer.wr_buf_out_data_reg[226] (\write_buffer.wr_buf_out_data_reg[226] ), .\write_buffer.wr_buf_out_data_reg[227] (\write_buffer.wr_buf_out_data_reg[227] ), .\write_buffer.wr_buf_out_data_reg[228] (\write_buffer.wr_buf_out_data_reg[228] ), .\write_buffer.wr_buf_out_data_reg[229] (\write_buffer.wr_buf_out_data_reg[229] ), .\write_buffer.wr_buf_out_data_reg[230] (\write_buffer.wr_buf_out_data_reg[230] ), .\write_buffer.wr_buf_out_data_reg[231] (\write_buffer.wr_buf_out_data_reg[231] ), .\write_buffer.wr_buf_out_data_reg[232] (\write_buffer.wr_buf_out_data_reg[232] ), .\write_buffer.wr_buf_out_data_reg[233] (\write_buffer.wr_buf_out_data_reg[233] ), .\write_buffer.wr_buf_out_data_reg[234] (\write_buffer.wr_buf_out_data_reg[234] ), .\write_buffer.wr_buf_out_data_reg[235] (\write_buffer.wr_buf_out_data_reg[235] ), .\write_buffer.wr_buf_out_data_reg[236] (\write_buffer.wr_buf_out_data_reg[236] ), .\write_buffer.wr_buf_out_data_reg[237] (\write_buffer.wr_buf_out_data_reg[237] ), .\write_buffer.wr_buf_out_data_reg[238] (\write_buffer.wr_buf_out_data_reg[238] ), .\write_buffer.wr_buf_out_data_reg[239] (\write_buffer.wr_buf_out_data_reg[239] ), .\write_buffer.wr_buf_out_data_reg[240] (\write_buffer.wr_buf_out_data_reg[240] ), .\write_buffer.wr_buf_out_data_reg[241] (\write_buffer.wr_buf_out_data_reg[241] ), .\write_buffer.wr_buf_out_data_reg[242] (\write_buffer.wr_buf_out_data_reg[242] ), .\write_buffer.wr_buf_out_data_reg[243] (\write_buffer.wr_buf_out_data_reg[243] ), .\write_buffer.wr_buf_out_data_reg[244] (\write_buffer.wr_buf_out_data_reg[244] ), .\write_buffer.wr_buf_out_data_reg[245] (\write_buffer.wr_buf_out_data_reg[245] ), .\write_buffer.wr_buf_out_data_reg[246] (\write_buffer.wr_buf_out_data_reg[246] ), .\write_buffer.wr_buf_out_data_reg[247] (\write_buffer.wr_buf_out_data_reg[247] ), .\write_buffer.wr_buf_out_data_reg[248] (\write_buffer.wr_buf_out_data_reg[248] ), .\write_buffer.wr_buf_out_data_reg[249] (\write_buffer.wr_buf_out_data_reg[249] ), .\write_buffer.wr_buf_out_data_reg[250] (\write_buffer.wr_buf_out_data_reg[250] ), .\write_buffer.wr_buf_out_data_reg[251] (\write_buffer.wr_buf_out_data_reg[251] ), .\write_buffer.wr_buf_out_data_reg[252] (\write_buffer.wr_buf_out_data_reg[252] ), .\write_buffer.wr_buf_out_data_reg[253] (\write_buffer.wr_buf_out_data_reg[253] ), .\write_buffer.wr_buf_out_data_reg[254] (\write_buffer.wr_buf_out_data_reg[254] ), .\write_buffer.wr_buf_out_data_reg[255] (\write_buffer.wr_buf_out_data_reg[255] ), .\write_buffer.wr_buf_out_data_reg[287] (\write_buffer.wr_buf_out_data_reg[287] )); ddr3_if_mig_7series_v4_0_ddr_phy_4lanes__parameterized0 \ddr_phy_4lanes_1.u_ddr_phy_4lanes (.CLK(CLK), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8), .D9(D9), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .D_po_counter_read_en122_out(D_po_counter_read_en122_out), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .PHYCTLWD({Q[10:9],\data_offset_1_i2_reg[5] ,Q[2:0]}), .Q(\wr_ptr_timing_reg[2] ), .RST0(RST0), ._phy_ctl_full_p__0(_phy_ctl_full_p__0), .\byte_r_reg[0] (\byte_r_reg[0] ), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_1 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_2 ), .\calib_sel_reg[1]_3 (\calib_sel_reg[1]_3 ), .\calib_sel_reg[1]_4 (\calib_sel_reg[1]_4 ), .\calib_sel_reg[1]_5 (\calib_sel_reg[1]_5 ), .\calib_sel_reg[1]_6 (\calib_sel_reg[1]_6 ), .\calib_sel_reg[3] (\calib_sel_reg[3] ), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .ddr_ck_out(ddr_ck_out), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .in0(in0), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0), .mcGo_w__0(mcGo_w__0), .mc_cas_n(mc_cas_n), .mem_dq_out(mem_dq_out[59:36]), .mem_out(mem_out), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_6 ), .\my_empty_reg[7] (\my_empty_reg[7]_3 ), .of_ctl_full_v(of_ctl_full_v), .phy_ctl_mstr_empty(phy_ctl_mstr_empty), .phy_ctl_wr_i2(phy_ctl_wr_i2), .phy_dout(phy_dout), .phy_mc_ctl_full(phy_mc_ctl_full), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .pll_locked(pll_locked), .\po_counter_read_val_r_reg[5] (\po_counter_read_val_r_reg[5] ), .\po_counter_read_val_reg[5]_0 ({\po_counter_read_val_w[0]_0 [5:4],\po_rdval_cnt_reg[8] [1],\po_counter_read_val_w[0]_0 [2:1],\po_rdval_cnt_reg[8] [0]}), .\po_rdval_cnt_reg[8] (\po_rdval_cnt_reg[8]_0 ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .ref_dll_lock_w(ref_dll_lock_w), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_1 )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 " *) SRL16E \mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 (.A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ), .Q(\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 )); FDRE \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 (.C(CLK), .CE(1'b1), .D(\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ), .Q(\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ), .R(1'b0)); FDRE \mcGo_r_reg[15] (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_gate_n_0), .Q(\calib_seq_reg[0] ), .R(in0)); LUT2 #( .INIT(4'h8)) mcGo_r_reg_gate (.I0(\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ), .I1(mcGo_r_reg_r_13_n_0), .O(mcGo_r_reg_gate_n_0)); FDRE mcGo_r_reg_r (.C(CLK), .CE(1'b1), .D(1'b1), .Q(mcGo_r_reg_r_n_0), .R(in0)); FDRE mcGo_r_reg_r_0 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_n_0), .Q(mcGo_r_reg_r_0_n_0), .R(in0)); FDRE mcGo_r_reg_r_1 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_0_n_0), .Q(mcGo_r_reg_r_1_n_0), .R(in0)); FDRE mcGo_r_reg_r_10 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_9_n_0), .Q(mcGo_r_reg_r_10_n_0), .R(in0)); FDRE mcGo_r_reg_r_11 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_10_n_0), .Q(mcGo_r_reg_r_11_n_0), .R(in0)); FDRE mcGo_r_reg_r_12 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_11_n_0), .Q(mcGo_r_reg_r_12_n_0), .R(in0)); FDRE mcGo_r_reg_r_13 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_12_n_0), .Q(mcGo_r_reg_r_13_n_0), .R(in0)); FDRE mcGo_r_reg_r_2 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_1_n_0), .Q(mcGo_r_reg_r_2_n_0), .R(in0)); FDRE mcGo_r_reg_r_3 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_2_n_0), .Q(mcGo_r_reg_r_3_n_0), .R(in0)); FDRE mcGo_r_reg_r_4 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_3_n_0), .Q(mcGo_r_reg_r_4_n_0), .R(in0)); FDRE mcGo_r_reg_r_5 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_4_n_0), .Q(mcGo_r_reg_r_5_n_0), .R(in0)); FDRE mcGo_r_reg_r_6 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_5_n_0), .Q(mcGo_r_reg_r_6_n_0), .R(in0)); FDRE mcGo_r_reg_r_7 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_6_n_0), .Q(mcGo_r_reg_r_7_n_0), .R(in0)); FDRE mcGo_r_reg_r_8 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_7_n_0), .Q(mcGo_r_reg_r_8_n_0), .R(in0)); FDRE mcGo_r_reg_r_9 (.C(CLK), .CE(1'b1), .D(mcGo_r_reg_r_8_n_0), .Q(mcGo_r_reg_r_9_n_0), .R(in0)); LUT1 #( .INIT(2'h1)) \rclk_delay_reg[10]_srl11_i_1 (.I0(rst_primitives), .O(\rclk_delay_reg[10]_srl11_i_1_n_0 )); LUT2 #( .INIT(4'hE)) rst_out_i_1 (.I0(rclk_delay_11), .I1(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ), .O(rst_out_i_1_n_0)); LUT1 #( .INIT(2'h1)) rst_primitives_i_1 (.I0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ), .O(rst_primitives_i_1_n_0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_mc_phy_wrapper (ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, fine_delay_sel_r, \fine_delay_mod_reg[26]_0 , \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \not_strict_mode.app_rd_data_reg[252] , idelay_ld_rst, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \not_strict_mode.app_rd_data_reg[244] , idelay_ld_rst_0, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \not_strict_mode.app_rd_data_reg[236] , idelay_ld_rst_1, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , \not_strict_mode.app_rd_data_reg[228] , idelay_ld_rst_2, \calib_seq_reg[0] , \my_empty_reg[1] , \my_empty_reg[1]_0 , phy_mc_ctl_full, \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \my_empty_reg[1]_3 , \my_empty_reg[1]_4 , \my_empty_reg[1]_5 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , \my_empty_reg[7] , \my_empty_reg[1]_6 , phy_rddata_en, mux_rd_valid_r_reg, rst_sync_r1_reg, \byte_r_reg[0] , \po_counter_read_val_r_reg[5] , \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \read_fifo.tail_r_reg[0] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , of_ctl_full_v, pd_out, pi_phase_locked_all_r1_reg, \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , wr_en, wr_en_5, wr_en_6, fine_delay_mod, \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7]_0 , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7]_1 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7]_2 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7]_3 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \po_rdval_cnt_reg[8] , \pi_rdval_cnt_reg[5] , \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , \po_rdval_cnt_reg[8]_0 , phy_if_empty_r_reg, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , ddr_ck_out, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, mux_reset_n, idle, mmcm_ps_clk, rst_sync_r1, CLK, mux_cmd_wren, \gen_byte_sel_div1.byte_sel_cnt_reg[2] , \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 , fine_delay_sel_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 , \gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 , \gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 , init_calib_complete_reg_rep__6, D5, D6, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, D0, D1, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, \calib_sel_reg[0]_2 , sync_pulse, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , \calib_sel_reg[1]_2 , \calib_sel_reg[1]_3 , \gen_byte_sel_div1.calib_in_common_reg_1 , \calib_sel_reg[1]_4 , \calib_sel_reg[1]_5 , \calib_sel_reg[1]_6 , pll_locked, phy_read_calib, in0, phy_write_calib, \gen_byte_sel_div1.calib_in_common_reg_2 , \calib_sel_reg[0]_3 , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, \gen_byte_sel_div1.calib_in_common_reg_3 , COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_4 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_5 , idelay_inc, LD0, CLKB0, phy_if_reset, \gen_byte_sel_div1.calib_in_common_reg_6 , \calib_sel_reg[0]_4 , pi_en_stg2_f_reg_0, pi_stg2_f_incdec_reg_0, \gen_byte_sel_div1.calib_in_common_reg_7 , \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_8 , ck_po_stg2_f_en_reg_0, ck_po_stg2_f_indec_reg_0, delay_done_r4_reg_0, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_9 , LD0_3, CLKB0_7, \gen_byte_sel_div1.calib_in_common_reg_10 , \calib_sel_reg[1]_7 , pi_en_stg2_f_reg_1, pi_stg2_f_incdec_reg_1, \gen_byte_sel_div1.calib_in_common_reg_11 , \calib_zero_inputs_reg[0]_0 , \gen_byte_sel_div1.calib_in_common_reg_12 , ck_po_stg2_f_en_reg_1, ck_po_stg2_f_indec_reg_1, delay_done_r4_reg_1, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_13 , LD0_4, CLKB0_8, \gen_byte_sel_div1.calib_in_common_reg_14 , \calib_sel_reg[0]_5 , pi_en_stg2_f_reg_2, pi_stg2_f_incdec_reg_2, \gen_byte_sel_div1.calib_in_common_reg_15 , \calib_zero_inputs_reg[0]_1 , \gen_byte_sel_div1.calib_in_common_reg_16 , ck_po_stg2_f_en_reg_2, ck_po_stg2_f_indec_reg_2, delay_done_r4_reg_2, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_17 , LD0_5, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, \gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 , mem_out, \rd_ptr_reg[3] , mux_wrdata_en, \rd_ptr_reg[3]_0 , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, \genblk9[6].fine_delay_incdec_pb_reg[6] , \genblk9[5].fine_delay_incdec_pb_reg[5] , \genblk9[7].fine_delay_incdec_pb_reg[7] , \genblk9[4].fine_delay_incdec_pb_reg[4] , \genblk9[3].fine_delay_incdec_pb_reg[3] , \genblk9[4].fine_delay_incdec_pb_reg[4]_0 , init_calib_complete_reg_rep__5, mc_cas_n, \cmd_pipe_plus.mc_address_reg[43] , init_calib_complete_reg_rep, Q, prbs_rdlvl_start_reg, out, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, \byte_r_reg[0]_0 , \byte_r_reg[1] , tail_r, \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , \genblk9[0].fine_delay_incdec_pb_reg[0] , \genblk9[1].fine_delay_incdec_pb_reg[1] , \genblk9[2].fine_delay_incdec_pb_reg[2] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , A, rstdiv0_sync_r1_reg_rep__2, SR, D, \cmd_pipe_plus.mc_data_offset_1_reg[5] , mux_wrdata, mux_wrdata_mask, E, \fine_delay_mod_reg[23]_0 , \gen_byte_sel_div1.calib_in_common_reg_18 , \calib_sel_reg[0]_6 , \gen_byte_sel_div1.calib_in_common_reg_19 , \calib_sel_reg[1]_8 , \gen_byte_sel_div1.calib_in_common_reg_20 , \calib_sel_reg[0]_7 , \calib_sel_reg[3] , \po_stg2_wrcal_cnt_reg[1] , D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , phy_dout, init_calib_complete_reg_rep__6_0); output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output fine_delay_sel_r; output \fine_delay_mod_reg[26]_0 ; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output [3:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output [0:0]\not_strict_mode.app_rd_data_reg[252] ; output idelay_ld_rst; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[244] ; output idelay_ld_rst_0; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[236] ; output idelay_ld_rst_1; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [0:0]\not_strict_mode.app_rd_data_reg[228] ; output idelay_ld_rst_2; output \calib_seq_reg[0] ; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output phy_mc_ctl_full; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \my_empty_reg[1]_3 ; output \my_empty_reg[1]_4 ; output \my_empty_reg[1]_5 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output [31:0]\my_empty_reg[7] ; output \my_empty_reg[1]_6 ; output phy_rddata_en; output mux_rd_valid_r_reg; output rst_sync_r1_reg; output \byte_r_reg[0] ; output [5:0]\po_counter_read_val_r_reg[5] ; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \read_fifo.tail_r_reg[0] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output [0:0]of_ctl_full_v; output pd_out; output pi_phase_locked_all_r1_reg; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output wr_en; output wr_en_5; output wr_en_6; output [8:0]fine_delay_mod; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7]_2 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7]_3 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [4:0]\po_rdval_cnt_reg[8] ; output [5:0]\pi_rdval_cnt_reg[5] ; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output [4:0]\po_rdval_cnt_reg[8]_0 ; output phy_if_empty_r_reg; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output [1:0]ddr_ck_out; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input mux_reset_n; input idle; input mmcm_ps_clk; input rst_sync_r1; input CLK; input mux_cmd_wren; input \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; input \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; input fine_delay_sel_reg; input \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [2:0]D0; input [2:0]D1; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[0]_2 ; input sync_pulse; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input \calib_sel_reg[1]_2 ; input \calib_sel_reg[1]_3 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \calib_sel_reg[1]_4 ; input \calib_sel_reg[1]_5 ; input \calib_sel_reg[1]_6 ; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \calib_sel_reg[0]_3 ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_4 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_5 ; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input \gen_byte_sel_div1.calib_in_common_reg_6 ; input \calib_sel_reg[0]_4 ; input pi_en_stg2_f_reg_0; input pi_stg2_f_incdec_reg_0; input \gen_byte_sel_div1.calib_in_common_reg_7 ; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_8 ; input ck_po_stg2_f_en_reg_0; input ck_po_stg2_f_indec_reg_0; input delay_done_r4_reg_0; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_9 ; input LD0_3; input CLKB0_7; input \gen_byte_sel_div1.calib_in_common_reg_10 ; input \calib_sel_reg[1]_7 ; input pi_en_stg2_f_reg_1; input pi_stg2_f_incdec_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_11 ; input [5:0]\calib_zero_inputs_reg[0]_0 ; input \gen_byte_sel_div1.calib_in_common_reg_12 ; input ck_po_stg2_f_en_reg_1; input ck_po_stg2_f_indec_reg_1; input delay_done_r4_reg_1; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_13 ; input LD0_4; input CLKB0_8; input \gen_byte_sel_div1.calib_in_common_reg_14 ; input \calib_sel_reg[0]_5 ; input pi_en_stg2_f_reg_2; input pi_stg2_f_incdec_reg_2; input \gen_byte_sel_div1.calib_in_common_reg_15 ; input [5:0]\calib_zero_inputs_reg[0]_1 ; input \gen_byte_sel_div1.calib_in_common_reg_16 ; input ck_po_stg2_f_en_reg_2; input ck_po_stg2_f_indec_reg_2; input delay_done_r4_reg_2; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_17 ; input LD0_5; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input \gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ; input [11:0]mem_out; input [33:0]\rd_ptr_reg[3] ; input mux_wrdata_en; input [17:0]\rd_ptr_reg[3]_0 ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input \genblk9[6].fine_delay_incdec_pb_reg[6] ; input \genblk9[5].fine_delay_incdec_pb_reg[5] ; input \genblk9[7].fine_delay_incdec_pb_reg[7] ; input \genblk9[4].fine_delay_incdec_pb_reg[4] ; input \genblk9[3].fine_delay_incdec_pb_reg[3] ; input \genblk9[4].fine_delay_incdec_pb_reg[4]_0 ; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input init_calib_complete_reg_rep; input [31:0]Q; input prbs_rdlvl_start_reg; input out; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input \byte_r_reg[0]_0 ; input \byte_r_reg[1] ; input [0:0]tail_r; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input \genblk9[0].fine_delay_incdec_pb_reg[0] ; input \genblk9[1].fine_delay_incdec_pb_reg[1] ; input \genblk9[2].fine_delay_incdec_pb_reg[2] ; input [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; input [1:0]A; input rstdiv0_sync_r1_reg_rep__2; input [0:0]SR; input [10:0]D; input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; input [255:0]mux_wrdata; input [31:0]mux_wrdata_mask; input [0:0]E; input [7:0]\fine_delay_mod_reg[23]_0 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; input [7:0]\calib_sel_reg[0]_6 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; input [7:0]\calib_sel_reg[1]_8 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; input [7:0]\calib_sel_reg[0]_7 ; input [2:0]\calib_sel_reg[3] ; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input D_po_sel_fine_oclk_delay125_out; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input [35:0]phy_dout; input init_calib_complete_reg_rep__6_0; wire [1:0]A; wire \A[0]__0_n_0 ; wire \A[0]__4_n_0 ; wire \A[1]__0_n_0 ; wire \A[1]__3_n_0 ; wire \A[1]__4_n_0 ; wire \A[2]__1_n_0 ; wire \A_n_0_[1] ; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [5:0]COUNTERLOADVAL; wire [10:0]D; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [0:0]E; wire LD0; wire LD0_3; wire LD0_4; wire LD0_5; wire [31:0]Q; wire RST0; wire [0:0]SR; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[1] ; wire [1:1]byte_sel_data_map; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire \calib_sel_reg[0]_3 ; wire \calib_sel_reg[0]_4 ; wire \calib_sel_reg[0]_5 ; wire [7:0]\calib_sel_reg[0]_6 ; wire [7:0]\calib_sel_reg[0]_7 ; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire \calib_sel_reg[1]_3 ; wire \calib_sel_reg[1]_4 ; wire \calib_sel_reg[1]_5 ; wire \calib_sel_reg[1]_6 ; wire \calib_sel_reg[1]_7 ; wire [7:0]\calib_sel_reg[1]_8 ; wire [2:0]\calib_sel_reg[3] ; wire \calib_seq_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0]_1 ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_en_reg_0; wire ck_po_stg2_f_en_reg_1; wire ck_po_stg2_f_en_reg_2; wire ck_po_stg2_f_indec_reg; wire ck_po_stg2_f_indec_reg_0; wire ck_po_stg2_f_indec_reg_1; wire ck_po_stg2_f_indec_reg_2; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire [63:0]\data_bytes_r_reg[63] ; wire [5:0]data_offset_1_i1; wire [5:0]data_offset_1_i2; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire delay_done_r4_reg; wire delay_done_r4_reg_0; wire delay_done_r4_reg_1; wire delay_done_r4_reg_2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire [8:0]fine_delay_mod; wire [11:2]fine_delay_mod0; wire \fine_delay_mod[11]_i_10_n_0 ; wire \fine_delay_mod[11]_i_11_n_0 ; wire \fine_delay_mod[11]_i_12_n_0 ; wire \fine_delay_mod[11]_i_1_n_0 ; wire \fine_delay_mod[11]_i_2_n_0 ; wire \fine_delay_mod[11]_i_3_n_0 ; wire \fine_delay_mod[11]_i_4_n_0 ; wire \fine_delay_mod[11]_i_5_n_0 ; wire \fine_delay_mod[11]_i_7_n_0 ; wire \fine_delay_mod[11]_i_9_n_0 ; wire \fine_delay_mod[14]_i_1_n_0 ; wire \fine_delay_mod[14]_i_2_n_0 ; wire \fine_delay_mod[14]_i_3_n_0 ; wire \fine_delay_mod[14]_i_4_n_0 ; wire \fine_delay_mod[14]_i_5_n_0 ; wire \fine_delay_mod[14]_i_6_n_0 ; wire \fine_delay_mod[14]_i_7_n_0 ; wire \fine_delay_mod[14]_i_8_n_0 ; wire \fine_delay_mod[17]_i_1_n_0 ; wire \fine_delay_mod[17]_i_2_n_0 ; wire \fine_delay_mod[17]_i_3_n_0 ; wire \fine_delay_mod[17]_i_4_n_0 ; wire \fine_delay_mod[17]_i_5_n_0 ; wire \fine_delay_mod[17]_i_6_n_0 ; wire \fine_delay_mod[17]_i_7_n_0 ; wire \fine_delay_mod[17]_i_8_n_0 ; wire \fine_delay_mod[17]_i_9_n_0 ; wire \fine_delay_mod[20]_i_1_n_0 ; wire \fine_delay_mod[20]_i_2_n_0 ; wire \fine_delay_mod[20]_i_3_n_0 ; wire \fine_delay_mod[20]_i_4_n_0 ; wire \fine_delay_mod[20]_i_5_n_0 ; wire \fine_delay_mod[20]_i_6_n_0 ; wire \fine_delay_mod[20]_i_7_n_0 ; wire \fine_delay_mod[20]_i_8_n_0 ; wire \fine_delay_mod[20]_i_9_n_0 ; wire \fine_delay_mod[23]_i_10_n_0 ; wire \fine_delay_mod[23]_i_1_n_0 ; wire \fine_delay_mod[23]_i_2_n_0 ; wire \fine_delay_mod[23]_i_3_n_0 ; wire \fine_delay_mod[23]_i_4_n_0 ; wire \fine_delay_mod[23]_i_5_n_0 ; wire \fine_delay_mod[23]_i_6_n_0 ; wire \fine_delay_mod[23]_i_7_n_0 ; wire \fine_delay_mod[23]_i_8_n_0 ; wire \fine_delay_mod[23]_i_9_n_0 ; wire \fine_delay_mod[26]_i_1_n_0 ; wire \fine_delay_mod[2]_i_10_n_0 ; wire \fine_delay_mod[2]_i_1_n_0 ; wire \fine_delay_mod[2]_i_2_n_0 ; wire \fine_delay_mod[2]_i_3_n_0 ; wire \fine_delay_mod[2]_i_4_n_0 ; wire \fine_delay_mod[2]_i_5_n_0 ; wire \fine_delay_mod[2]_i_7_n_0 ; wire \fine_delay_mod[2]_i_8_n_0 ; wire \fine_delay_mod[2]_i_9_n_0 ; wire \fine_delay_mod[5]_i_10_n_0 ; wire \fine_delay_mod[5]_i_11_n_0 ; wire \fine_delay_mod[5]_i_12_n_0 ; wire \fine_delay_mod[5]_i_1_n_0 ; wire \fine_delay_mod[5]_i_2_n_0 ; wire \fine_delay_mod[5]_i_3_n_0 ; wire \fine_delay_mod[5]_i_4_n_0 ; wire \fine_delay_mod[5]_i_5_n_0 ; wire \fine_delay_mod[5]_i_7_n_0 ; wire \fine_delay_mod[5]_i_8_n_0 ; wire \fine_delay_mod[5]_i_9_n_0 ; wire \fine_delay_mod[8]_i_10_n_0 ; wire \fine_delay_mod[8]_i_1_n_0 ; wire \fine_delay_mod[8]_i_2_n_0 ; wire \fine_delay_mod[8]_i_3_n_0 ; wire \fine_delay_mod[8]_i_4_n_0 ; wire \fine_delay_mod[8]_i_5_n_0 ; wire \fine_delay_mod[8]_i_7_n_0 ; wire \fine_delay_mod[8]_i_8_n_0 ; wire \fine_delay_mod[8]_i_9_n_0 ; wire [7:0]\fine_delay_mod_reg[23]_0 ; wire \fine_delay_mod_reg[26]_0 ; wire fine_delay_sel_r; wire fine_delay_sel_reg; wire freq_refclk; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ; wire [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_10 ; wire \gen_byte_sel_div1.calib_in_common_reg_11 ; wire \gen_byte_sel_div1.calib_in_common_reg_12 ; wire \gen_byte_sel_div1.calib_in_common_reg_13 ; wire \gen_byte_sel_div1.calib_in_common_reg_14 ; wire \gen_byte_sel_div1.calib_in_common_reg_15 ; wire \gen_byte_sel_div1.calib_in_common_reg_16 ; wire \gen_byte_sel_div1.calib_in_common_reg_17 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_18 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_19 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_20 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.calib_in_common_reg_4 ; wire \gen_byte_sel_div1.calib_in_common_reg_5 ; wire \gen_byte_sel_div1.calib_in_common_reg_6 ; wire \gen_byte_sel_div1.calib_in_common_reg_7 ; wire \gen_byte_sel_div1.calib_in_common_reg_8 ; wire \gen_byte_sel_div1.calib_in_common_reg_9 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire \genblk9[0].fine_delay_incdec_pb_reg[0] ; wire \genblk9[1].fine_delay_incdec_pb_reg[1] ; wire \genblk9[2].fine_delay_incdec_pb_reg[2] ; wire \genblk9[3].fine_delay_incdec_pb_reg[3] ; wire \genblk9[4].fine_delay_incdec_pb_reg[4] ; wire \genblk9[4].fine_delay_incdec_pb_reg[4]_0 ; wire \genblk9[5].fine_delay_incdec_pb_reg[5] ; wire \genblk9[6].fine_delay_incdec_pb_reg[6] ; wire \genblk9[7].fine_delay_incdec_pb_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_0; wire idelay_ld_rst_1; wire idelay_ld_rst_2; wire idle; wire in0; wire in_dqs_lpbk_to_iddr_0; wire in_dqs_lpbk_to_iddr_1; wire in_dqs_lpbk_to_iddr_2; wire in_dqs_lpbk_to_iddr_3; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire [3:0]init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire [0:0]mc_cas_n; wire [38:0]mem_dq_in; wire [93:0]mem_dq_out; wire [45:0]mem_dq_ts; wire [3:0]mem_dqs_in; wire [3:0]mem_dqs_out; wire [3:0]mem_dqs_ts; wire [11:0]mem_out; wire mem_refclk; wire mmcm_locked; wire mmcm_ps_clk; wire mux_cmd_wren; wire mux_rd_valid_r_reg; wire mux_reset_n; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire [31:0]\my_empty_reg[7] ; wire [63:0]\my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire [63:0]\my_empty_reg[7]_2 ; wire [63:0]\my_empty_reg[7]_3 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire [0:0]\not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire [0:0]\not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire [0:0]\not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire [0:0]\not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire out; wire p_0_out; wire pd_out; wire [2:0]pd_out_pre; wire [24:0]phy_ctl_wd_i1; wire [24:0]phy_ctl_wd_i2; wire phy_ctl_wr_i1; wire phy_ctl_wr_i2; wire [35:0]phy_dout; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_mc_ctl_full; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [3:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_en_stg2_f_reg_0; wire pi_en_stg2_f_reg_1; wire pi_en_stg2_f_reg_2; wire pi_phase_locked_all_r1_reg; wire [5:0]\pi_rdval_cnt_reg[5] ; wire pi_stg2_f_incdec_reg; wire pi_stg2_f_incdec_reg_0; wire pi_stg2_f_incdec_reg_1; wire pi_stg2_f_incdec_reg_2; wire pll_locked; wire [5:0]\po_counter_read_val_r_reg[5] ; wire [4:0]\po_rdval_cnt_reg[8] ; wire [4:0]\po_rdval_cnt_reg[8]_0 ; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rd_buf_we; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [33:0]\rd_ptr_reg[3] ; wire [17:0]\rd_ptr_reg[3]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; FDRE \A[0]__0 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ), .Q(\A[0]__0_n_0 ), .R(1'b0)); FDRE \A[0]__4 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ), .Q(\A[0]__4_n_0 ), .R(1'b0)); FDSE \A[1] (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ), .Q(\A_n_0_[1] ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDSE \A[1]__0 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ), .Q(\A[1]__0_n_0 ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDSE \A[1]__3 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ), .Q(\A[1]__3_n_0 ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDSE \A[1]__4 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ), .Q(\A[1]__4_n_0 ), .S(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDRE \A[2]__1 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ), .Q(\A[2]__1_n_0 ), .R(1'b0)); FDRE \A[2]__2 (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[0] ), .Q(\fine_delay_mod_reg[26]_0 ), .R(1'b0)); FDRE \byte_sel_data_map_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ), .Q(byte_sel_data_map), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf (.I(mem_dq_out[71]), .O(ddr3_cke)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf (.I(mem_dq_out[70]), .O(ddr3_odt)); FDRE \data_offset_1_i1_reg[0] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .Q(data_offset_1_i1[0]), .R(1'b0)); FDRE \data_offset_1_i1_reg[1] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .Q(data_offset_1_i1[1]), .R(1'b0)); FDRE \data_offset_1_i1_reg[2] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .Q(data_offset_1_i1[2]), .R(1'b0)); FDRE \data_offset_1_i1_reg[3] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .Q(data_offset_1_i1[3]), .R(1'b0)); FDRE \data_offset_1_i1_reg[4] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]), .Q(data_offset_1_i1[4]), .R(1'b0)); FDRE \data_offset_1_i1_reg[5] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]), .Q(data_offset_1_i1[5]), .R(1'b0)); FDRE \data_offset_1_i2_reg[0] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[0]), .Q(data_offset_1_i2[0]), .R(1'b0)); FDRE \data_offset_1_i2_reg[1] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[1]), .Q(data_offset_1_i2[1]), .R(1'b0)); FDRE \data_offset_1_i2_reg[2] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[2]), .Q(data_offset_1_i2[2]), .R(1'b0)); FDRE \data_offset_1_i2_reg[3] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[3]), .Q(data_offset_1_i2[3]), .R(1'b0)); FDRE \data_offset_1_i2_reg[4] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[4]), .Q(data_offset_1_i2[4]), .R(1'b0)); FDRE \data_offset_1_i2_reg[5] (.C(CLK), .CE(1'b1), .D(data_offset_1_i1[5]), .Q(data_offset_1_i2[5]), .R(1'b0)); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[11]_i_1 (.I0(\fine_delay_mod[11]_i_2_n_0 ), .I1(\fine_delay_mod[11]_i_3_n_0 ), .I2(\fine_delay_mod[11]_i_4_n_0 ), .I3(\fine_delay_mod[11]_i_5_n_0 ), .I4(fine_delay_mod0[11]), .I5(fine_delay_mod[3]), .O(\fine_delay_mod[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1027" *) LUT5 #( .INIT(32'h00575757)) \fine_delay_mod[11]_i_10 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(byte_sel_data_map), .I3(\fine_delay_mod_reg[26]_0 ), .I4(\A[1]__3_n_0 ), .O(\fine_delay_mod[11]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1026" *) LUT5 #( .INIT(32'h0000F888)) \fine_delay_mod[11]_i_11 (.I0(\A[1]__0_n_0 ), .I1(\A[0]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A_n_0_[1] ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[11]_i_11_n_0 )); LUT6 #( .INIT(64'h0088008800F80088)) \fine_delay_mod[11]_i_12 (.I0(\A[0]__4_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\fine_delay_mod_reg[26]_0 ), .I4(byte_sel_data_map), .I5(\A[0]__0_n_0 ), .O(\fine_delay_mod[11]_i_12_n_0 )); LUT6 #( .INIT(64'hF780808080808080)) \fine_delay_mod[11]_i_2 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\A[1]__3_n_0 ), .I4(\genblk9[5].fine_delay_incdec_pb_reg[5] ), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[11]_i_2_n_0 )); LUT6 #( .INIT(64'h0000770400000000)) \fine_delay_mod[11]_i_3 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\fine_delay_mod[11]_i_7_n_0 ), .I4(\A[2]__1_n_0 ), .I5(\fine_delay_mod[23]_i_6_n_0 ), .O(\fine_delay_mod[11]_i_3_n_0 )); LUT6 #( .INIT(64'h0700000000000000)) \fine_delay_mod[11]_i_4 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[11]_i_4_n_0 )); LUT6 #( .INIT(64'h8000800088008000)) \fine_delay_mod[11]_i_5 (.I0(\fine_delay_mod[11]_i_9_n_0 ), .I1(\fine_delay_mod[11]_i_10_n_0 ), .I2(\A[2]__1_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\fine_delay_mod[23]_i_8_n_0 ), .I5(\A[1]__0_n_0 ), .O(\fine_delay_mod[11]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFF888)) \fine_delay_mod[11]_i_6 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__3_n_0 ), .I4(\fine_delay_mod[11]_i_11_n_0 ), .I5(\fine_delay_mod[11]_i_12_n_0 ), .O(fine_delay_mod0[11])); (* SOFT_HLUTNM = "soft_lutpair1038" *) LUT3 #( .INIT(8'h1F)) \fine_delay_mod[11]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[11]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1032" *) LUT4 #( .INIT(16'h0008)) \fine_delay_mod[11]_i_9 (.I0(byte_sel_data_map), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .O(\fine_delay_mod[11]_i_9_n_0 )); LUT5 #( .INIT(32'hEEEFEEE0)) \fine_delay_mod[14]_i_1 (.I0(\fine_delay_mod[14]_i_2_n_0 ), .I1(\fine_delay_mod[14]_i_3_n_0 ), .I2(\fine_delay_mod[14]_i_4_n_0 ), .I3(\fine_delay_mod[14]_i_5_n_0 ), .I4(fine_delay_mod[4]), .O(\fine_delay_mod[14]_i_1_n_0 )); LUT6 #( .INIT(64'hC480FFFFC4800000)) \fine_delay_mod[14]_i_2 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[14]_i_6_n_0 ), .I3(\genblk9[3].fine_delay_incdec_pb_reg[3] ), .I4(\fine_delay_mod[14]_i_7_n_0 ), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .O(\fine_delay_mod[14]_i_2_n_0 )); LUT6 #( .INIT(64'h00B0003000300030)) \fine_delay_mod[14]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[17]_i_8_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .I5(\fine_delay_mod[14]_i_8_n_0 ), .O(\fine_delay_mod[14]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1035" *) LUT4 #( .INIT(16'h444C)) \fine_delay_mod[14]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[14]_i_4_n_0 )); LUT6 #( .INIT(64'h000000FF02020202)) \fine_delay_mod[14]_i_5 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[14]_i_5_n_0 )); LUT6 #( .INIT(64'h020202FF02020200)) \fine_delay_mod[14]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[14]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1040" *) LUT3 #( .INIT(8'hFD)) \fine_delay_mod[14]_i_7 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[14]_i_7_n_0 )); LUT2 #( .INIT(4'hE)) \fine_delay_mod[14]_i_8 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .O(\fine_delay_mod[14]_i_8_n_0 )); LUT5 #( .INIT(32'hEEEFEEE0)) \fine_delay_mod[17]_i_1 (.I0(\fine_delay_mod[17]_i_2_n_0 ), .I1(\fine_delay_mod[17]_i_3_n_0 ), .I2(\fine_delay_mod[17]_i_4_n_0 ), .I3(\fine_delay_mod[17]_i_5_n_0 ), .I4(fine_delay_mod[5]), .O(\fine_delay_mod[17]_i_1_n_0 )); LUT6 #( .INIT(64'hC840FFFFC8400000)) \fine_delay_mod[17]_i_2 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[17]_i_6_n_0 ), .I3(\genblk9[3].fine_delay_incdec_pb_reg[3] ), .I4(\fine_delay_mod[17]_i_7_n_0 ), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .O(\fine_delay_mod[17]_i_2_n_0 )); LUT6 #( .INIT(64'h7030000030300000)) \fine_delay_mod[17]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[17]_i_8_n_0 ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\fine_delay_mod[17]_i_9_n_0 ), .O(\fine_delay_mod[17]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1035" *) LUT4 #( .INIT(16'h88C8)) \fine_delay_mod[17]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[2]__1_n_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[17]_i_4_n_0 )); LUT6 #( .INIT(64'h0000FF0020202020)) \fine_delay_mod[17]_i_5 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[17]_i_5_n_0 )); LUT6 #( .INIT(64'h08FF080808000808)) \fine_delay_mod[17]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A_n_0_[1] ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[17]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1041" *) LUT3 #( .INIT(8'hDF)) \fine_delay_mod[17]_i_7 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[17]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1029" *) LUT4 #( .INIT(16'h0400)) \fine_delay_mod[17]_i_8 (.I0(byte_sel_data_map), .I1(\A[0]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .O(\fine_delay_mod[17]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1043" *) LUT2 #( .INIT(4'hB)) \fine_delay_mod[17]_i_9 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[17]_i_9_n_0 )); LUT6 #( .INIT(64'hFCFFFEFEFC00FEFE)) \fine_delay_mod[20]_i_1 (.I0(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .I1(\fine_delay_mod[20]_i_2_n_0 ), .I2(\fine_delay_mod[20]_i_3_n_0 ), .I3(\fine_delay_mod[20]_i_4_n_0 ), .I4(\fine_delay_mod[20]_i_5_n_0 ), .I5(fine_delay_mod[6]), .O(\fine_delay_mod[20]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1039" *) LUT3 #( .INIT(8'h80)) \fine_delay_mod[20]_i_2 (.I0(\fine_delay_mod[20]_i_6_n_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[20]_i_5_n_0 ), .O(\fine_delay_mod[20]_i_2_n_0 )); LUT5 #( .INIT(32'h004400C4)) \fine_delay_mod[20]_i_3 (.I0(\A[2]__1_n_0 ), .I1(\fine_delay_mod[23]_i_7_n_0 ), .I2(\fine_delay_mod[20]_i_7_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .O(\fine_delay_mod[20]_i_3_n_0 )); LUT5 #( .INIT(32'hFF808080)) \fine_delay_mod[20]_i_4 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\fine_delay_mod[20]_i_8_n_0 ), .I3(\A[2]__1_n_0 ), .I4(\fine_delay_mod[20]_i_9_n_0 ), .O(\fine_delay_mod[20]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1040" *) LUT3 #( .INIT(8'hF7)) \fine_delay_mod[20]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[20]_i_5_n_0 )); LUT6 #( .INIT(64'h08FF080808000808)) \fine_delay_mod[20]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[20]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1043" *) LUT2 #( .INIT(4'hB)) \fine_delay_mod[20]_i_7 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .O(\fine_delay_mod[20]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1042" *) LUT2 #( .INIT(4'h1)) \fine_delay_mod[20]_i_8 (.I0(\A[0]__0_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[20]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1033" *) LUT4 #( .INIT(16'h22F2)) \fine_delay_mod[20]_i_9 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__0_n_0 ), .I3(\A[0]__0_n_0 ), .O(\fine_delay_mod[20]_i_9_n_0 )); LUT6 #( .INIT(64'hFCFFFEFEFC00FEFE)) \fine_delay_mod[23]_i_1 (.I0(\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ), .I1(\fine_delay_mod[23]_i_2_n_0 ), .I2(\fine_delay_mod[23]_i_3_n_0 ), .I3(\fine_delay_mod[23]_i_4_n_0 ), .I4(\fine_delay_mod[23]_i_5_n_0 ), .I5(fine_delay_mod[7]), .O(\fine_delay_mod[23]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1030" *) LUT4 #( .INIT(16'hF888)) \fine_delay_mod[23]_i_10 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[23]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1039" *) LUT3 #( .INIT(8'h80)) \fine_delay_mod[23]_i_2 (.I0(\fine_delay_mod[23]_i_6_n_0 ), .I1(\A[2]__1_n_0 ), .I2(\fine_delay_mod[23]_i_5_n_0 ), .O(\fine_delay_mod[23]_i_2_n_0 )); LUT5 #( .INIT(32'h4400C400)) \fine_delay_mod[23]_i_3 (.I0(\A[2]__1_n_0 ), .I1(\fine_delay_mod[23]_i_7_n_0 ), .I2(\fine_delay_mod[23]_i_8_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[1]__0_n_0 ), .O(\fine_delay_mod[23]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1028" *) LUT5 #( .INIT(32'hFF808080)) \fine_delay_mod[23]_i_4 (.I0(\A[0]__0_n_0 ), .I1(byte_sel_data_map), .I2(\fine_delay_mod[23]_i_9_n_0 ), .I3(\A[2]__1_n_0 ), .I4(\fine_delay_mod[23]_i_10_n_0 ), .O(\fine_delay_mod[23]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1041" *) LUT3 #( .INIT(8'h7F)) \fine_delay_mod[23]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[23]_i_5_n_0 )); LUT6 #( .INIT(64'hFF80808000808080)) \fine_delay_mod[23]_i_6 (.I0(\genblk9[1].fine_delay_incdec_pb_reg[1] ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__0_n_0 ), .I4(\A[0]__0_n_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2] ), .O(\fine_delay_mod[23]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1032" *) LUT4 #( .INIT(16'h0800)) \fine_delay_mod[23]_i_7 (.I0(byte_sel_data_map), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .O(\fine_delay_mod[23]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1034" *) LUT2 #( .INIT(4'h7)) \fine_delay_mod[23]_i_8 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .O(\fine_delay_mod[23]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1042" *) LUT2 #( .INIT(4'h2)) \fine_delay_mod[23]_i_9 (.I0(\A[0]__0_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[23]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFEF00000020)) \fine_delay_mod[26]_i_1 (.I0(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I1(\A[0]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .I4(byte_sel_data_map), .I5(fine_delay_mod[8]), .O(\fine_delay_mod[26]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[2]_i_1 (.I0(\fine_delay_mod[2]_i_2_n_0 ), .I1(\fine_delay_mod[2]_i_3_n_0 ), .I2(\fine_delay_mod[2]_i_4_n_0 ), .I3(\fine_delay_mod[2]_i_5_n_0 ), .I4(fine_delay_mod0[2]), .I5(fine_delay_mod[0]), .O(\fine_delay_mod[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1030" *) LUT4 #( .INIT(16'h111F)) \fine_delay_mod[2]_i_10 (.I0(\A_n_0_[1] ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[2]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1036" *) LUT4 #( .INIT(16'h1000)) \fine_delay_mod[2]_i_2 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[2]_i_2_n_0 )); LUT5 #( .INIT(32'h00A80000)) \fine_delay_mod[2]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[1]__4_n_0 ), .I2(\fine_delay_mod[2]_i_7_n_0 ), .I3(\A[2]__1_n_0 ), .I4(\fine_delay_mod[14]_i_6_n_0 ), .O(\fine_delay_mod[2]_i_3_n_0 )); LUT6 #( .INIT(64'h5500752055005500)) \fine_delay_mod[2]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[0]__4_n_0 ), .I2(\A[1]__4_n_0 ), .I3(\genblk9[7].fine_delay_incdec_pb_reg[7] ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[2]_i_4_n_0 )); LUT6 #( .INIT(64'hAA80000000000000)) \fine_delay_mod[2]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(\fine_delay_mod[5]_i_8_n_0 ), .I5(\fine_delay_mod[2]_i_8_n_0 ), .O(\fine_delay_mod[2]_i_5_n_0 )); LUT6 #( .INIT(64'hFDDDFDDDFFFFFDDD)) \fine_delay_mod[2]_i_6 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\fine_delay_mod[2]_i_9_n_0 ), .I2(\fine_delay_mod[5]_i_11_n_0 ), .I3(\fine_delay_mod[20]_i_8_n_0 ), .I4(\fine_delay_mod[2]_i_10_n_0 ), .I5(\A[2]__1_n_0 ), .O(fine_delay_mod0[2])); (* SOFT_HLUTNM = "soft_lutpair1037" *) LUT3 #( .INIT(8'hF8)) \fine_delay_mod[2]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[2]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1025" *) LUT5 #( .INIT(32'h00FF00A8)) \fine_delay_mod[2]_i_8 (.I0(\A[1]__0_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A_n_0_[1] ), .I3(\A[0]__0_n_0 ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[2]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1031" *) LUT4 #( .INIT(16'h010F)) \fine_delay_mod[2]_i_9 (.I0(byte_sel_data_map), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__4_n_0 ), .I3(\A[1]__4_n_0 ), .O(\fine_delay_mod[2]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[5]_i_1 (.I0(\fine_delay_mod[5]_i_2_n_0 ), .I1(\fine_delay_mod[5]_i_3_n_0 ), .I2(\fine_delay_mod[5]_i_4_n_0 ), .I3(\fine_delay_mod[5]_i_5_n_0 ), .I4(fine_delay_mod0[5]), .I5(fine_delay_mod[1]), .O(\fine_delay_mod[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1031" *) LUT4 #( .INIT(16'h10F0)) \fine_delay_mod[5]_i_10 (.I0(byte_sel_data_map), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[0]__4_n_0 ), .I3(\A[1]__4_n_0 ), .O(\fine_delay_mod[5]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1028" *) LUT2 #( .INIT(4'h1)) \fine_delay_mod[5]_i_11 (.I0(byte_sel_data_map), .I1(\A[0]__0_n_0 ), .O(\fine_delay_mod[5]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1033" *) LUT4 #( .INIT(16'h22F2)) \fine_delay_mod[5]_i_12 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A_n_0_[1] ), .I2(\A[0]__0_n_0 ), .I3(\A[1]__0_n_0 ), .O(\fine_delay_mod[5]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1036" *) LUT4 #( .INIT(16'h0040)) \fine_delay_mod[5]_i_2 (.I0(\A[1]__4_n_0 ), .I1(\A[0]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1034" *) LUT4 #( .INIT(16'h0400)) \fine_delay_mod[5]_i_3 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\fine_delay_mod[5]_i_7_n_0 ), .I2(\A[2]__1_n_0 ), .I3(\fine_delay_mod[17]_i_6_n_0 ), .O(\fine_delay_mod[5]_i_3_n_0 )); LUT6 #( .INIT(64'hAA00EA40AA00AA00)) \fine_delay_mod[5]_i_4 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .I3(\genblk9[7].fine_delay_incdec_pb_reg[7] ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[5]_i_4_n_0 )); LUT6 #( .INIT(64'h4055000000000000)) \fine_delay_mod[5]_i_5 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(byte_sel_data_map), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(\fine_delay_mod[5]_i_8_n_0 ), .I5(\fine_delay_mod[5]_i_9_n_0 ), .O(\fine_delay_mod[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFEEEFEEEFFFFFEEE)) \fine_delay_mod[5]_i_6 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\fine_delay_mod[5]_i_10_n_0 ), .I2(\fine_delay_mod[5]_i_11_n_0 ), .I3(\fine_delay_mod[23]_i_9_n_0 ), .I4(\fine_delay_mod[5]_i_12_n_0 ), .I5(\A[2]__1_n_0 ), .O(fine_delay_mod0[5])); (* SOFT_HLUTNM = "soft_lutpair1038" *) LUT3 #( .INIT(8'h8F)) \fine_delay_mod[5]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1029" *) LUT4 #( .INIT(16'h0004)) \fine_delay_mod[5]_i_8 (.I0(\fine_delay_mod_reg[26]_0 ), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0] ), .I2(\A[0]__0_n_0 ), .I3(byte_sel_data_map), .O(\fine_delay_mod[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1025" *) LUT5 #( .INIT(32'hFF008A00)) \fine_delay_mod[5]_i_9 (.I0(\A[1]__0_n_0 ), .I1(\A_n_0_[1] ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[0]__0_n_0 ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[5]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \fine_delay_mod[8]_i_1 (.I0(\fine_delay_mod[8]_i_2_n_0 ), .I1(\fine_delay_mod[8]_i_3_n_0 ), .I2(\fine_delay_mod[8]_i_4_n_0 ), .I3(\fine_delay_mod[8]_i_5_n_0 ), .I4(fine_delay_mod0[8]), .I5(fine_delay_mod[2]), .O(\fine_delay_mod[8]_i_1_n_0 )); LUT6 #( .INIT(64'h00440044004F0044)) \fine_delay_mod[8]_i_10 (.I0(\A[0]__4_n_0 ), .I1(byte_sel_data_map), .I2(\A[0]__0_n_0 ), .I3(\fine_delay_mod_reg[26]_0 ), .I4(byte_sel_data_map), .I5(\A[0]__0_n_0 ), .O(\fine_delay_mod[8]_i_10_n_0 )); LUT6 #( .INIT(64'h40404040FB404040)) \fine_delay_mod[8]_i_2 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(\genblk9[6].fine_delay_incdec_pb_reg[6] ), .I3(\A[1]__3_n_0 ), .I4(\genblk9[5].fine_delay_incdec_pb_reg[5] ), .I5(\fine_delay_mod_reg[26]_0 ), .O(\fine_delay_mod[8]_i_2_n_0 )); LUT6 #( .INIT(64'h0000DD0C00000000)) \fine_delay_mod[8]_i_3 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\fine_delay_mod[8]_i_7_n_0 ), .I4(\A[2]__1_n_0 ), .I5(\fine_delay_mod[20]_i_6_n_0 ), .O(\fine_delay_mod[8]_i_3_n_0 )); LUT6 #( .INIT(64'h000D000000000000)) \fine_delay_mod[8]_i_4 (.I0(\A[1]__3_n_0 ), .I1(\fine_delay_mod_reg[26]_0 ), .I2(\A[1]__4_n_0 ), .I3(\A[0]__4_n_0 ), .I4(byte_sel_data_map), .I5(\genblk9[4].fine_delay_incdec_pb_reg[4] ), .O(\fine_delay_mod[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0080008000880080)) \fine_delay_mod[8]_i_5 (.I0(\fine_delay_mod[11]_i_9_n_0 ), .I1(\fine_delay_mod[8]_i_8_n_0 ), .I2(\A[2]__1_n_0 ), .I3(\A[0]__0_n_0 ), .I4(\fine_delay_mod[20]_i_7_n_0 ), .I5(\A[1]__0_n_0 ), .O(\fine_delay_mod[8]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF4F44)) \fine_delay_mod[8]_i_6 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A[1]__3_n_0 ), .I4(\fine_delay_mod[8]_i_9_n_0 ), .I5(\fine_delay_mod[8]_i_10_n_0 ), .O(fine_delay_mod0[8])); (* SOFT_HLUTNM = "soft_lutpair1037" *) LUT3 #( .INIT(8'hF1)) \fine_delay_mod[8]_i_7 (.I0(byte_sel_data_map), .I1(\A[1]__4_n_0 ), .I2(\A[0]__4_n_0 ), .O(\fine_delay_mod[8]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1027" *) LUT5 #( .INIT(32'hAB00ABAB)) \fine_delay_mod[8]_i_8 (.I0(\A[0]__4_n_0 ), .I1(\A[1]__4_n_0 ), .I2(byte_sel_data_map), .I3(\fine_delay_mod_reg[26]_0 ), .I4(\A[1]__3_n_0 ), .O(\fine_delay_mod[8]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1026" *) LUT5 #( .INIT(32'h00004F44)) \fine_delay_mod[8]_i_9 (.I0(\A[0]__0_n_0 ), .I1(\A[1]__0_n_0 ), .I2(\fine_delay_mod_reg[26]_0 ), .I3(\A_n_0_[1] ), .I4(\A[2]__1_n_0 ), .O(\fine_delay_mod[8]_i_9_n_0 )); FDRE \fine_delay_mod_reg[11] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[11]_i_1_n_0 ), .Q(fine_delay_mod[3]), .R(1'b0)); FDRE \fine_delay_mod_reg[14] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[14]_i_1_n_0 ), .Q(fine_delay_mod[4]), .R(1'b0)); FDRE \fine_delay_mod_reg[17] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[17]_i_1_n_0 ), .Q(fine_delay_mod[5]), .R(1'b0)); FDRE \fine_delay_mod_reg[20] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[20]_i_1_n_0 ), .Q(fine_delay_mod[6]), .R(1'b0)); FDRE \fine_delay_mod_reg[23] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[23]_i_1_n_0 ), .Q(fine_delay_mod[7]), .R(1'b0)); FDRE \fine_delay_mod_reg[26] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[26]_i_1_n_0 ), .Q(fine_delay_mod[8]), .R(1'b0)); FDRE \fine_delay_mod_reg[2] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[2]_i_1_n_0 ), .Q(fine_delay_mod[0]), .R(1'b0)); FDRE \fine_delay_mod_reg[5] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[5]_i_1_n_0 ), .Q(fine_delay_mod[1]), .R(1'b0)); FDRE \fine_delay_mod_reg[8] (.C(CLK), .CE(1'b1), .D(\fine_delay_mod[8]_i_1_n_0 ), .Q(fine_delay_mod[2]), .R(1'b0)); FDRE fine_delay_sel_r_reg (.C(CLK), .CE(1'b1), .D(fine_delay_sel_reg), .Q(fine_delay_sel_r), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[0].u_addr_obuf (.I(mem_dq_out[83]), .O(ddr3_addr[0])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[10].u_addr_obuf (.I(mem_dq_out[90]), .O(ddr3_addr[10])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[11].u_addr_obuf (.I(mem_dq_out[91]), .O(ddr3_addr[11])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[12].u_addr_obuf (.I(mem_dq_out[92]), .O(ddr3_addr[12])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[13].u_addr_obuf (.I(mem_dq_out[93]), .O(ddr3_addr[13])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[14].u_addr_obuf (.I(mem_dq_out[64]), .O(ddr3_addr[14])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[1].u_addr_obuf (.I(mem_dq_out[78]), .O(ddr3_addr[1])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[2].u_addr_obuf (.I(mem_dq_out[79]), .O(ddr3_addr[2])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[3].u_addr_obuf (.I(mem_dq_out[80]), .O(ddr3_addr[3])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[4].u_addr_obuf (.I(mem_dq_out[77]), .O(ddr3_addr[4])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[5].u_addr_obuf (.I(mem_dq_out[85]), .O(ddr3_addr[5])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[6].u_addr_obuf (.I(mem_dq_out[86]), .O(ddr3_addr[6])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[7].u_addr_obuf (.I(mem_dq_out[87]), .O(ddr3_addr[7])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[8].u_addr_obuf (.I(mem_dq_out[88]), .O(ddr3_addr[8])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_addr_obuf[9].u_addr_obuf (.I(mem_dq_out[89]), .O(ddr3_addr[9])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_bank_obuf[0].u_bank_obuf (.I(mem_dq_out[76]), .O(ddr3_ba[0])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_bank_obuf[1].u_bank_obuf (.I(mem_dq_out[81]), .O(ddr3_ba[1])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_bank_obuf[2].u_bank_obuf (.I(mem_dq_out[82]), .O(ddr3_ba[2])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf (.I(mem_dq_out[48]), .O(ddr3_cs_n)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[0].u_dm_obuf (.I(mem_dq_out[45]), .O(ddr3_dm[0]), .T(mem_dq_ts[45])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[1].u_dm_obuf (.I(mem_dq_out[33]), .O(ddr3_dm[1]), .T(mem_dq_ts[33])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[2].u_dm_obuf (.I(mem_dq_out[21]), .O(ddr3_dm[2]), .T(mem_dq_ts[21])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUFT #( .IOSTANDARD("DEFAULT")) \gen_dm_obuf.loop_dm[3].u_dm_obuf (.I(mem_dq_out[9]), .O(ddr3_dm[3]), .T(mem_dq_ts[9])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[0].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[44]), .IBUFDISABLE(idle), .IO(ddr3_dq[0]), .O(mem_dq_in[38]), .T(mem_dq_ts[44])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[10].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[30]), .IBUFDISABLE(idle), .IO(ddr3_dq[10]), .O(mem_dq_in[26]), .T(mem_dq_ts[30])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[11].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[29]), .IBUFDISABLE(idle), .IO(ddr3_dq[11]), .O(mem_dq_in[25]), .T(mem_dq_ts[29])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[12].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[28]), .IBUFDISABLE(idle), .IO(ddr3_dq[12]), .O(mem_dq_in[24]), .T(mem_dq_ts[28])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[13].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[27]), .IBUFDISABLE(idle), .IO(ddr3_dq[13]), .O(mem_dq_in[23]), .T(mem_dq_ts[27])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[14].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[26]), .IBUFDISABLE(idle), .IO(ddr3_dq[14]), .O(mem_dq_in[22]), .T(mem_dq_ts[26])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[15].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[25]), .IBUFDISABLE(idle), .IO(ddr3_dq[15]), .O(mem_dq_in[21]), .T(mem_dq_ts[25])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[16].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[20]), .IBUFDISABLE(idle), .IO(ddr3_dq[16]), .O(mem_dq_in[18]), .T(mem_dq_ts[20])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[17].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[19]), .IBUFDISABLE(idle), .IO(ddr3_dq[17]), .O(mem_dq_in[17]), .T(mem_dq_ts[19])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[18].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[18]), .IBUFDISABLE(idle), .IO(ddr3_dq[18]), .O(mem_dq_in[16]), .T(mem_dq_ts[18])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[19].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[17]), .IBUFDISABLE(idle), .IO(ddr3_dq[19]), .O(mem_dq_in[15]), .T(mem_dq_ts[17])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[1].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[43]), .IBUFDISABLE(idle), .IO(ddr3_dq[1]), .O(mem_dq_in[37]), .T(mem_dq_ts[43])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[20].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[16]), .IBUFDISABLE(idle), .IO(ddr3_dq[20]), .O(mem_dq_in[14]), .T(mem_dq_ts[16])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[21].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[15]), .IBUFDISABLE(idle), .IO(ddr3_dq[21]), .O(mem_dq_in[13]), .T(mem_dq_ts[15])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[22].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[14]), .IBUFDISABLE(idle), .IO(ddr3_dq[22]), .O(mem_dq_in[12]), .T(mem_dq_ts[14])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[23].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[13]), .IBUFDISABLE(idle), .IO(ddr3_dq[23]), .O(mem_dq_in[11]), .T(mem_dq_ts[13])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[24].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[7]), .IBUFDISABLE(idle), .IO(ddr3_dq[24]), .O(mem_dq_in[7]), .T(mem_dq_ts[7])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[25].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[6]), .IBUFDISABLE(idle), .IO(ddr3_dq[25]), .O(mem_dq_in[6]), .T(mem_dq_ts[6])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[26].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[5]), .IBUFDISABLE(idle), .IO(ddr3_dq[26]), .O(mem_dq_in[5]), .T(mem_dq_ts[5])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[27].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[4]), .IBUFDISABLE(idle), .IO(ddr3_dq[27]), .O(mem_dq_in[4]), .T(mem_dq_ts[4])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[28].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[3]), .IBUFDISABLE(idle), .IO(ddr3_dq[28]), .O(mem_dq_in[3]), .T(mem_dq_ts[3])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[29].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[2]), .IBUFDISABLE(idle), .IO(ddr3_dq[29]), .O(mem_dq_in[2]), .T(mem_dq_ts[2])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[2].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[42]), .IBUFDISABLE(idle), .IO(ddr3_dq[2]), .O(mem_dq_in[36]), .T(mem_dq_ts[42])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[30].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[1]), .IBUFDISABLE(idle), .IO(ddr3_dq[30]), .O(mem_dq_in[1]), .T(mem_dq_ts[1])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[31].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[0]), .IBUFDISABLE(idle), .IO(ddr3_dq[31]), .O(mem_dq_in[0]), .T(mem_dq_ts[0])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[3].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[41]), .IBUFDISABLE(idle), .IO(ddr3_dq[3]), .O(mem_dq_in[35]), .T(mem_dq_ts[41])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[4].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[40]), .IBUFDISABLE(idle), .IO(ddr3_dq[4]), .O(mem_dq_in[34]), .T(mem_dq_ts[40])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[5].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[39]), .IBUFDISABLE(idle), .IO(ddr3_dq[5]), .O(mem_dq_in[33]), .T(mem_dq_ts[39])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[6].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[38]), .IBUFDISABLE(idle), .IO(ddr3_dq[6]), .O(mem_dq_in[32]), .T(mem_dq_ts[38])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[7].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[37]), .IBUFDISABLE(idle), .IO(ddr3_dq[7]), .O(mem_dq_in[31]), .T(mem_dq_ts[37])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[8].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[32]), .IBUFDISABLE(idle), .IO(ddr3_dq[8]), .O(mem_dq_in[28]), .T(mem_dq_ts[32])); (* BOX_TYPE = "PRIMITIVE" *) IOBUF_DCIEN #( .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("TRUE")) \gen_dq_iobuf_HP.gen_dq_iobuf[9].u_iobuf_dq (.DCITERMDISABLE(idle), .I(mem_dq_out[31]), .IBUFDISABLE(idle), .IO(ddr3_dq[9]), .O(mem_dq_in[27]), .T(mem_dq_ts[31])); ddr3_if_mig_7series_v4_0_poc_pd \gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .in_dqs_lpbk_to_iddr_0(in_dqs_lpbk_to_iddr_0), .mmcm_ps_clk(mmcm_ps_clk), .pd_out_pre(pd_out_pre[0]), .rst_sync_r1(rst_sync_r1)); (* BOX_TYPE = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[3]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[0]), .IOB(ddr3_dqs_n[0]), .O(mem_dqs_in[3]), .OB(in_dqs_lpbk_to_iddr_0), .TM(mem_dqs_ts[3]), .TS(mem_dqs_ts[3])); ddr3_if_mig_7series_v4_0_poc_pd_3 \gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .in_dqs_lpbk_to_iddr_1(in_dqs_lpbk_to_iddr_1), .mmcm_ps_clk(mmcm_ps_clk), .pd_out_pre(pd_out_pre[1]), .rst_sync_r1(rst_sync_r1)); (* BOX_TYPE = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[2]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[1]), .IOB(ddr3_dqs_n[1]), .O(mem_dqs_in[2]), .OB(in_dqs_lpbk_to_iddr_1), .TM(mem_dqs_ts[2]), .TS(mem_dqs_ts[2])); ddr3_if_mig_7series_v4_0_poc_pd_4 \gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .in_dqs_lpbk_to_iddr_2(in_dqs_lpbk_to_iddr_2), .mmcm_ps_clk(mmcm_ps_clk), .pd_out_pre(pd_out_pre[2]), .rst_sync_r1(rst_sync_r1)); (* BOX_TYPE = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[1]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[2]), .IOB(ddr3_dqs_n[2]), .O(mem_dqs_in[1]), .OB(in_dqs_lpbk_to_iddr_2), .TM(mem_dqs_ts[1]), .TS(mem_dqs_ts[1])); ddr3_if_mig_7series_v4_0_poc_pd_5 \gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det (.CLK(CLK), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\gen_byte_sel_div1.byte_sel_cnt_reg[1] ), .in_dqs_lpbk_to_iddr_3(in_dqs_lpbk_to_iddr_3), .mmcm_ps_clk(mmcm_ps_clk), .pd_out(pd_out), .pd_out_r_reg_0(pd_out_pre), .rst_sync_r1(rst_sync_r1)); (* BOX_TYPE = "PRIMITIVE" *) IOBUFDS_DIFF_OUT_DCIEN #( .DQS_BIAS("TRUE"), .IOSTANDARD("DEFAULT"), .SIM_DEVICE("7SERIES"), .USE_IBUFDISABLE("FALSE")) \gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs (.DCITERMDISABLE(idle), .I(mem_dqs_out[0]), .IBUFDISABLE(1'b0), .IO(ddr3_dqs_p[3]), .IOB(ddr3_dqs_n[3]), .O(mem_dqs_in[0]), .OB(in_dqs_lpbk_to_iddr_3), .TM(mem_dqs_ts[0]), .TS(mem_dqs_ts[0])); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) \gen_reset_obuf.u_reset_obuf (.I(mux_reset_n), .O(ddr3_reset_n)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo \genblk24.phy_ctl_pre_fifo_0 (.CLK(CLK), .SR(SR), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized0 \genblk24.phy_ctl_pre_fifo_1 (.CLK(CLK), .SR(SR), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2)); ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized1 \genblk24.phy_ctl_pre_fifo_2 (.CLK(CLK), .SR(SR), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2)); FDRE \phy_ctl_wd_i1_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(phy_ctl_wd_i1[0]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[17] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(phy_ctl_wd_i1[17]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[18] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(phy_ctl_wd_i1[18]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[19] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(phy_ctl_wd_i1[19]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(phy_ctl_wd_i1[1]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[20] (.C(CLK), .CE(1'b1), .D(D[6]), .Q(phy_ctl_wd_i1[20]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[21] (.C(CLK), .CE(1'b1), .D(D[7]), .Q(phy_ctl_wd_i1[21]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[22] (.C(CLK), .CE(1'b1), .D(D[8]), .Q(phy_ctl_wd_i1[22]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[23] (.C(CLK), .CE(1'b1), .D(D[9]), .Q(phy_ctl_wd_i1[23]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[24] (.C(CLK), .CE(1'b1), .D(D[10]), .Q(phy_ctl_wd_i1[24]), .R(1'b0)); FDRE \phy_ctl_wd_i1_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(phy_ctl_wd_i1[2]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[0] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[0]), .Q(phy_ctl_wd_i2[0]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[17] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[17]), .Q(phy_ctl_wd_i2[17]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[18] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[18]), .Q(phy_ctl_wd_i2[18]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[19] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[19]), .Q(phy_ctl_wd_i2[19]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[1] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[1]), .Q(phy_ctl_wd_i2[1]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[20] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[20]), .Q(phy_ctl_wd_i2[20]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[21] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[21]), .Q(phy_ctl_wd_i2[21]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[22] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[22]), .Q(phy_ctl_wd_i2[22]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[23] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[23]), .Q(phy_ctl_wd_i2[23]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[24] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[24]), .Q(phy_ctl_wd_i2[24]), .R(1'b0)); FDRE \phy_ctl_wd_i2_reg[2] (.C(CLK), .CE(1'b1), .D(phy_ctl_wd_i1[2]), .Q(phy_ctl_wd_i2[2]), .R(1'b0)); FDRE phy_ctl_wr_i1_reg (.C(CLK), .CE(1'b1), .D(mux_cmd_wren), .Q(phy_ctl_wr_i1), .R(1'b0)); FDRE phy_ctl_wr_i2_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_wr_i1), .Q(phy_ctl_wr_i2), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) u_cas_n_obuf (.I(mem_dq_out[74]), .O(ddr3_cas_n)); ddr3_if_mig_7series_v4_0_ddr_mc_phy u_ddr_mc_phy (.A(A), .CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .COUNTERLOADVAL(COUNTERLOADVAL), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8), .D9(D9), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .D_po_counter_read_en122_out(D_po_counter_read_en122_out), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .E(E), .LD0(LD0), .LD0_3(LD0_3), .LD0_4(LD0_4), .LD0_5(LD0_5), .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}), .RST0(RST0), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[0]_0 (\byte_r_reg[0]_0 ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ), .\calib_sel_reg[0]_3 (\calib_sel_reg[0]_3 ), .\calib_sel_reg[0]_4 (\calib_sel_reg[0]_4 ), .\calib_sel_reg[0]_5 (\calib_sel_reg[0]_5 ), .\calib_sel_reg[0]_6 (\calib_sel_reg[0]_6 ), .\calib_sel_reg[0]_7 (\calib_sel_reg[0]_7 ), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_1 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_2 ), .\calib_sel_reg[1]_3 (\calib_sel_reg[1]_3 ), .\calib_sel_reg[1]_4 (\calib_sel_reg[1]_4 ), .\calib_sel_reg[1]_5 (\calib_sel_reg[1]_5 ), .\calib_sel_reg[1]_6 (\calib_sel_reg[1]_6 ), .\calib_sel_reg[1]_7 (\calib_sel_reg[1]_7 ), .\calib_sel_reg[1]_8 (\calib_sel_reg[1]_8 ), .\calib_sel_reg[3] (\calib_sel_reg[3] ), .\calib_seq_reg[0] (\calib_seq_reg[0] ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ), .\calib_zero_inputs_reg[0]_0 (\calib_zero_inputs_reg[0]_0 ), .\calib_zero_inputs_reg[0]_1 (\calib_zero_inputs_reg[0]_1 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg), .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0), .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1), .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg), .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0), .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1), .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .\data_offset_1_i2_reg[5] (data_offset_1_i2), .ddr_ck_out(ddr_ck_out), .delay_done_r4_reg(delay_done_r4_reg), .delay_done_r4_reg_0(delay_done_r4_reg_0), .delay_done_r4_reg_1(delay_done_r4_reg_1), .delay_done_r4_reg_2(delay_done_r4_reg_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23]_0 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_byte_sel_div1.calib_in_common_reg_10 (\gen_byte_sel_div1.calib_in_common_reg_10 ), .\gen_byte_sel_div1.calib_in_common_reg_11 (\gen_byte_sel_div1.calib_in_common_reg_11 ), .\gen_byte_sel_div1.calib_in_common_reg_12 (\gen_byte_sel_div1.calib_in_common_reg_12 ), .\gen_byte_sel_div1.calib_in_common_reg_13 (\gen_byte_sel_div1.calib_in_common_reg_13 ), .\gen_byte_sel_div1.calib_in_common_reg_14 (\gen_byte_sel_div1.calib_in_common_reg_14 ), .\gen_byte_sel_div1.calib_in_common_reg_15 (\gen_byte_sel_div1.calib_in_common_reg_15 ), .\gen_byte_sel_div1.calib_in_common_reg_16 (\gen_byte_sel_div1.calib_in_common_reg_16 ), .\gen_byte_sel_div1.calib_in_common_reg_17 (\gen_byte_sel_div1.calib_in_common_reg_17 ), .\gen_byte_sel_div1.calib_in_common_reg_18 (\gen_byte_sel_div1.calib_in_common_reg_18 ), .\gen_byte_sel_div1.calib_in_common_reg_19 (\gen_byte_sel_div1.calib_in_common_reg_19 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_byte_sel_div1.calib_in_common_reg_20 (\gen_byte_sel_div1.calib_in_common_reg_20 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_3 ), .\gen_byte_sel_div1.calib_in_common_reg_4 (\gen_byte_sel_div1.calib_in_common_reg_4 ), .\gen_byte_sel_div1.calib_in_common_reg_5 (\gen_byte_sel_div1.calib_in_common_reg_5 ), .\gen_byte_sel_div1.calib_in_common_reg_6 (\gen_byte_sel_div1.calib_in_common_reg_6 ), .\gen_byte_sel_div1.calib_in_common_reg_7 (\gen_byte_sel_div1.calib_in_common_reg_7 ), .\gen_byte_sel_div1.calib_in_common_reg_8 (\gen_byte_sel_div1.calib_in_common_reg_8 ), .\gen_byte_sel_div1.calib_in_common_reg_9 (\gen_byte_sel_div1.calib_in_common_reg_9 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .idelay_ld_rst_0(idelay_ld_rst_0), .idelay_ld_rst_1(idelay_ld_rst_1), .idelay_ld_rst_2(idelay_ld_rst_2), .in0(in0), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0), .mc_cas_n(mc_cas_n), .mem_dq_in({mem_dq_in[38:31],mem_dq_in[28:21],mem_dq_in[18:11],mem_dq_in[7:0]}), .mem_dq_out({mem_dq_out[93:85],mem_dq_out[83:74],mem_dq_out[71:70],mem_dq_out[64],mem_dq_out[49:48],mem_dq_out[45:37],mem_dq_out[33:25],mem_dq_out[21:13],mem_dq_out[9],mem_dq_out[7:0]}), .mem_dq_ts({mem_dq_ts[45:37],mem_dq_ts[33:25],mem_dq_ts[21:13],mem_dq_ts[9],mem_dq_ts[7:0]}), .mem_dqs_in(mem_dqs_in), .mem_dqs_out(mem_dqs_out), .mem_dqs_ts(mem_dqs_ts), .mem_out(mem_out), .mem_refclk(mem_refclk), .mmcm_locked(mmcm_locked), .mux_cmd_wren(mux_cmd_wren), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .mux_wrdata(mux_wrdata), .mux_wrdata_en(mux_wrdata_en), .mux_wrdata_mask(mux_wrdata_mask), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ), .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ), .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ), .\my_empty_reg[1]_3 (\my_empty_reg[1]_3 ), .\my_empty_reg[1]_4 (\my_empty_reg[1]_4 ), .\my_empty_reg[1]_5 (\my_empty_reg[1]_5 ), .\my_empty_reg[1]_6 (\my_empty_reg[1]_6 ), .\my_empty_reg[7] (\my_empty_reg[7]_0 ), .\my_empty_reg[7]_0 (\my_empty_reg[7]_1 ), .\my_empty_reg[7]_1 (\my_empty_reg[7]_2 ), .\my_empty_reg[7]_2 (\my_empty_reg[7]_3 ), .\my_empty_reg[7]_3 (\my_empty_reg[7] ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15]_0 ), .\not_strict_mode.app_rd_data_reg[15]_1 (\not_strict_mode.app_rd_data_reg[15]_1 ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[200] 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r_reg(ofs_rdy_r_reg), .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0), .out(out), .p_0_out(p_0_out), .phy_ctl_wr_i2(phy_ctl_wr_i2), .phy_dout(phy_dout), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_if_reset(phy_if_reset), .phy_mc_ctl_full(phy_mc_ctl_full), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ), .pi_en_stg2_f_reg(pi_en_stg2_f_reg), .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0), .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1), .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2), .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg), .\pi_rdval_cnt_reg[5] (\pi_rdval_cnt_reg[5] ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg), .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0), .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1), .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2), .pll_locked(pll_locked), .\po_counter_read_val_r_reg[5] (\po_counter_read_val_r_reg[5] ), .\po_rdval_cnt_reg[8] (\po_rdval_cnt_reg[8] ), .\po_rdval_cnt_reg[8]_0 (\po_rdval_cnt_reg[8]_0 ), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_1 ), .\write_buffer.wr_buf_out_data_reg[224] (\write_buffer.wr_buf_out_data_reg[224] ), .\write_buffer.wr_buf_out_data_reg[225] (\write_buffer.wr_buf_out_data_reg[225] ), .\write_buffer.wr_buf_out_data_reg[226] (\write_buffer.wr_buf_out_data_reg[226] ), .\write_buffer.wr_buf_out_data_reg[227] (\write_buffer.wr_buf_out_data_reg[227] ), .\write_buffer.wr_buf_out_data_reg[228] (\write_buffer.wr_buf_out_data_reg[228] ), .\write_buffer.wr_buf_out_data_reg[229] (\write_buffer.wr_buf_out_data_reg[229] ), .\write_buffer.wr_buf_out_data_reg[230] (\write_buffer.wr_buf_out_data_reg[230] ), .\write_buffer.wr_buf_out_data_reg[231] (\write_buffer.wr_buf_out_data_reg[231] ), .\write_buffer.wr_buf_out_data_reg[232] (\write_buffer.wr_buf_out_data_reg[232] ), .\write_buffer.wr_buf_out_data_reg[233] (\write_buffer.wr_buf_out_data_reg[233] ), .\write_buffer.wr_buf_out_data_reg[234] (\write_buffer.wr_buf_out_data_reg[234] ), .\write_buffer.wr_buf_out_data_reg[235] (\write_buffer.wr_buf_out_data_reg[235] ), .\write_buffer.wr_buf_out_data_reg[236] (\write_buffer.wr_buf_out_data_reg[236] ), .\write_buffer.wr_buf_out_data_reg[237] (\write_buffer.wr_buf_out_data_reg[237] ), .\write_buffer.wr_buf_out_data_reg[238] (\write_buffer.wr_buf_out_data_reg[238] ), .\write_buffer.wr_buf_out_data_reg[239] (\write_buffer.wr_buf_out_data_reg[239] ), .\write_buffer.wr_buf_out_data_reg[240] (\write_buffer.wr_buf_out_data_reg[240] ), .\write_buffer.wr_buf_out_data_reg[241] (\write_buffer.wr_buf_out_data_reg[241] ), .\write_buffer.wr_buf_out_data_reg[242] (\write_buffer.wr_buf_out_data_reg[242] ), .\write_buffer.wr_buf_out_data_reg[243] (\write_buffer.wr_buf_out_data_reg[243] ), .\write_buffer.wr_buf_out_data_reg[244] (\write_buffer.wr_buf_out_data_reg[244] ), .\write_buffer.wr_buf_out_data_reg[245] (\write_buffer.wr_buf_out_data_reg[245] ), .\write_buffer.wr_buf_out_data_reg[246] (\write_buffer.wr_buf_out_data_reg[246] ), .\write_buffer.wr_buf_out_data_reg[247] (\write_buffer.wr_buf_out_data_reg[247] ), .\write_buffer.wr_buf_out_data_reg[248] (\write_buffer.wr_buf_out_data_reg[248] ), .\write_buffer.wr_buf_out_data_reg[249] (\write_buffer.wr_buf_out_data_reg[249] ), .\write_buffer.wr_buf_out_data_reg[250] (\write_buffer.wr_buf_out_data_reg[250] ), .\write_buffer.wr_buf_out_data_reg[251] (\write_buffer.wr_buf_out_data_reg[251] ), .\write_buffer.wr_buf_out_data_reg[252] (\write_buffer.wr_buf_out_data_reg[252] ), .\write_buffer.wr_buf_out_data_reg[253] (\write_buffer.wr_buf_out_data_reg[253] ), .\write_buffer.wr_buf_out_data_reg[254] (\write_buffer.wr_buf_out_data_reg[254] ), .\write_buffer.wr_buf_out_data_reg[255] (\write_buffer.wr_buf_out_data_reg[255] ), .\write_buffer.wr_buf_out_data_reg[287] (Q)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) u_ras_n_obuf (.I(mem_dq_out[75]), .O(ddr3_ras_n)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) OBUF #( .IOSTANDARD("DEFAULT")) u_we_n_obuf (.I(mem_dq_out[49]), .O(ddr3_we_n)); endmodule module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo (rstdiv0_sync_r1_reg_rep__2, CLK, SR); input rstdiv0_sync_r1_reg_rep__2; input CLK; input [0:0]SR; wire CLK; wire [0:0]SR; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing; wire rstdiv0_sync_r1_reg_rep__2; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(wr_en)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(rd_ptr_timing[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[1]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[2]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[2]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized0 (SR, CLK, rstdiv0_sync_r1_reg_rep__2); input [0:0]SR; input CLK; input rstdiv0_sync_r1_reg_rep__2; wire CLK; wire [0:0]SR; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing; wire rstdiv0_sync_r1_reg_rep__2; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(wr_en)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(wr_ptr_timing[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[1]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[2]), .R(rstdiv0_sync_r1_reg_rep__2)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized1 (rstdiv0_sync_r1_reg_rep__2, CLK, SR); input rstdiv0_sync_r1_reg_rep__2; input CLK; input [0:0]SR; wire CLK; wire [0:0]SR; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing; wire rstdiv0_sync_r1_reg_rep__2; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(wr_en)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(rd_ptr_timing[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[1]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(rd_ptr_timing[2]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(1'b0), .D(1'b1), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(1'b0), .D(1'b0), .Q(wr_ptr_timing[2]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized2 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D8, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D8; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[287] ; input [71:0]phy_dout; wire CLK; wire [7:0]D8; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1_n_0 ; wire \entry_cnt[1]_i_1_n_0 ; wire \entry_cnt[2]_i_1_n_0 ; wire \entry_cnt[3]_i_1_n_0 ; wire \entry_cnt[4]_i_1_n_0 ; wire \entry_cnt[4]_i_2_n_0 ; wire \entry_cnt[4]_i_3_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_60_65_n_4; wire mem_reg_0_15_60_65_n_5; wire mem_reg_0_15_66_71_n_0; wire mem_reg_0_15_66_71_n_1; wire mem_reg_0_15_66_71_n_2; wire mem_reg_0_15_66_71_n_3; wire mem_reg_0_15_66_71_n_4; wire mem_reg_0_15_66_71_n_5; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__0_n_0 ; wire \my_empty[7]_i_1__0_n_0 ; wire \my_empty[7]_i_3__0_n_0 ; wire \my_empty[7]_i_4__0_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1_n_0 ; wire \my_full[4]_i_3__0_n_0 ; wire \my_full[4]_i_4__0_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__0_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[287] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair772" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair769" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair772" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1 (.I0(\entry_cnt[4]_i_3_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair769" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3_n_0 )); FDRE \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[0]_i_1_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[1]_i_1_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[2]_i_1_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[3]_i_1_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1_n_0 ), .D(\entry_cnt[4]_i_2_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[1:0]), .DIB(phy_dout[3:2]), .DIC(phy_dout[5:4]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [1:0]), .DOB(\my_empty_reg[7]_1 [3:2]), .DOC(\my_empty_reg[7]_1 [5:4]), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__0 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[13:12]), .DIB(phy_dout[15:14]), .DIC(phy_dout[17:16]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [13:12]), .DOB(\my_empty_reg[7]_1 [15:14]), .DOC(\my_empty_reg[7]_1 [17:16]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[19:18]), .DIB(phy_dout[21:20]), .DIC(phy_dout[23:22]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [19:18]), .DOB(\my_empty_reg[7]_1 [21:20]), .DOC(\my_empty_reg[7]_1 [23:22]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[25:24]), .DIB(phy_dout[27:26]), .DIC(phy_dout[29:28]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [25:24]), .DOB(\my_empty_reg[7]_1 [27:26]), .DOC(\my_empty_reg[7]_1 [29:28]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[31:30]), .DIB(phy_dout[33:32]), .DIC(phy_dout[35:34]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [31:30]), .DOB(\my_empty_reg[7]_1 [33:32]), .DOC(\my_empty_reg[7]_1 [35:34]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[37:36]), .DIB(phy_dout[39:38]), .DIC(phy_dout[41:40]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [37:36]), .DOB(\my_empty_reg[7]_1 [39:38]), .DOC(\my_empty_reg[7]_1 [41:40]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[43:42]), .DIB(phy_dout[45:44]), .DIC(phy_dout[47:46]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [43:42]), .DOB(\my_empty_reg[7]_1 [45:44]), .DOC(\my_empty_reg[7]_1 [47:46]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[49:48]), .DIB(phy_dout[51:50]), .DIC(phy_dout[53:52]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [49:48]), .DOB(\my_empty_reg[7]_1 [51:50]), .DOC(\my_empty_reg[7]_1 [53:52]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[55:54]), .DIB(phy_dout[57:56]), .DIC(phy_dout[59:58]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [55:54]), .DOB(\my_empty_reg[7]_1 [57:56]), .DOC(\my_empty_reg[7]_1 [59:58]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[61:60]), .DIB(phy_dout[63:62]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [61:60]), .DOB(\my_empty_reg[7]_1 [63:62]), .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}), .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}), .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[7:6]), .DIB(phy_dout[9:8]), .DIC(phy_dout[11:10]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [7:6]), .DOB(\my_empty_reg[7]_1 [9:8]), .DOC(\my_empty_reg[7]_1 [11:10]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__0 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__0 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__0 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__0_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__0_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair771" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__0 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair771" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__0 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDRE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__0_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__0_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__0 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__0_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__0_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair770" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__0 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair770" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__0 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__3 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair778" *) LUT2 #( .INIT(4'h2)) out_fifo_i_66__0 (.I0(mem_reg_0_15_66_71_n_4), .I1(\my_empty_reg[1]_0 ), .O(D8[7])); (* SOFT_HLUTNM = "soft_lutpair775" *) LUT2 #( .INIT(4'h2)) out_fifo_i_67__0 (.I0(mem_reg_0_15_66_71_n_5), .I1(\my_empty_reg[1]_0 ), .O(D8[6])); (* SOFT_HLUTNM = "soft_lutpair777" *) LUT2 #( .INIT(4'h2)) out_fifo_i_68__1 (.I0(mem_reg_0_15_66_71_n_2), .I1(\my_empty_reg[1]_0 ), .O(D8[5])); (* SOFT_HLUTNM = "soft_lutpair773" *) LUT2 #( .INIT(4'h2)) out_fifo_i_69__1 (.I0(mem_reg_0_15_66_71_n_3), .I1(\my_empty_reg[1]_0 ), .O(D8[4])); (* SOFT_HLUTNM = "soft_lutpair781" *) LUT2 #( .INIT(4'h2)) out_fifo_i_70 (.I0(mem_reg_0_15_66_71_n_0), .I1(\my_empty_reg[1]_0 ), .O(D8[3])); (* SOFT_HLUTNM = "soft_lutpair774" *) LUT2 #( .INIT(4'h2)) out_fifo_i_71 (.I0(mem_reg_0_15_66_71_n_1), .I1(\my_empty_reg[1]_0 ), .O(D8[2])); (* SOFT_HLUTNM = "soft_lutpair782" *) LUT2 #( .INIT(4'h2)) out_fifo_i_72 (.I0(mem_reg_0_15_60_65_n_4), .I1(\my_empty_reg[1]_0 ), .O(D8[1])); (* SOFT_HLUTNM = "soft_lutpair776" *) LUT2 #( .INIT(4'h2)) out_fifo_i_73 (.I0(mem_reg_0_15_60_65_n_5), .I1(\my_empty_reg[1]_0 ), .O(D8[0])); (* SOFT_HLUTNM = "soft_lutpair775" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair778" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair776" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair774" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair777" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__3 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair781" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair773" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair782" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[287] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair783" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__1 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair783" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__0 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair780" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__0 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__0 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair780" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__0 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair784" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__3 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair784" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__3 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair779" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__2 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair779" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized3 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D0, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[286] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D0; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[286] ; input [71:0]phy_dout; wire CLK; wire [7:0]D0; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1__0_n_0 ; wire \entry_cnt[1]_i_1__0_n_0 ; wire \entry_cnt[2]_i_1__0_n_0 ; wire \entry_cnt[3]_i_1__0_n_0 ; wire \entry_cnt[4]_i_1__0_n_0 ; wire \entry_cnt[4]_i_2__0_n_0 ; wire \entry_cnt[4]_i_3__0_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_0_5_n_0; wire mem_reg_0_15_0_5_n_1; wire mem_reg_0_15_0_5_n_2; wire mem_reg_0_15_0_5_n_3; wire mem_reg_0_15_0_5_n_4; wire mem_reg_0_15_0_5_n_5; wire mem_reg_0_15_6_11_n_0; wire mem_reg_0_15_6_11_n_1; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__1_n_0 ; wire \my_empty[7]_i_1__1_n_0 ; wire \my_empty[7]_i_3__1_n_0 ; wire \my_empty[7]_i_4__1_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1__0_n_0 ; wire \my_full[4]_i_3__1_n_0 ; wire \my_full[4]_i_4__1_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__1_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[286] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair823" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1__0 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair821" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1__0 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1__0 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair823" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1__0 (.I0(\entry_cnt[4]_i_3__0_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1__0_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1__0 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2__0 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3__0_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair821" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3__0 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3__0_n_0 )); FDRE \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[0]_i_1__0_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[1]_i_1__0_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[2]_i_1__0_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[3]_i_1__0_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1__0_n_0 ), .D(\entry_cnt[4]_i_2__0_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}), .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}), .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__1 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[5:4]), .DIB(phy_dout[7:6]), .DIC(phy_dout[9:8]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [5:4]), .DOB(\my_empty_reg[7]_1 [7:6]), .DOC(\my_empty_reg[7]_1 [9:8]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[11:10]), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [11:10]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[17:16]), .DIB(phy_dout[19:18]), .DIC(phy_dout[21:20]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [17:16]), .DOB(\my_empty_reg[7]_1 [19:18]), .DOC(\my_empty_reg[7]_1 [21:20]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[23:22]), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [23:22]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[29:28]), .DIB(phy_dout[31:30]), .DIC(phy_dout[33:32]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [29:28]), .DOB(\my_empty_reg[7]_1 [31:30]), .DOC(\my_empty_reg[7]_1 [33:32]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[35:34]), .DIB(phy_dout[37:36]), .DIC(phy_dout[39:38]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [35:34]), .DOB(\my_empty_reg[7]_1 [37:36]), .DOC(\my_empty_reg[7]_1 [39:38]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[41:40]), .DIB(phy_dout[43:42]), .DIC(phy_dout[45:44]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [41:40]), .DOB(\my_empty_reg[7]_1 [43:42]), .DOC(\my_empty_reg[7]_1 [45:44]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[47:46]), .DIB(phy_dout[49:48]), .DIC(phy_dout[51:50]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [47:46]), .DOB(\my_empty_reg[7]_1 [49:48]), .DOC(\my_empty_reg[7]_1 [51:50]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[53:52]), .DIB(phy_dout[55:54]), .DIC(phy_dout[57:56]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [53:52]), .DOB(\my_empty_reg[7]_1 [55:54]), .DOC(\my_empty_reg[7]_1 [57:56]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[59:58]), .DIB(phy_dout[61:60]), .DIC(phy_dout[63:62]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [59:58]), .DOB(\my_empty_reg[7]_1 [61:60]), .DOC(\my_empty_reg[7]_1 [63:62]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__1 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__1 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__1 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__1_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__1_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair824" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__1 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair824" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__1 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDRE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__1_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__1_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1__0 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__1 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__1_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__1_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair822" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__1 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair822" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__1 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1__0_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__4 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair830" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__3 (.I0(mem_reg_0_15_6_11_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[7])); (* SOFT_HLUTNM = "soft_lutpair826" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__3 (.I0(mem_reg_0_15_6_11_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[6])); (* SOFT_HLUTNM = "soft_lutpair831" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__3 (.I0(mem_reg_0_15_0_5_n_4), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair828" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__3 (.I0(mem_reg_0_15_0_5_n_5), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair829" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__3 (.I0(mem_reg_0_15_0_5_n_2), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair827" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair830" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair828" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair829" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair826" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__2 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair832" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair825" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__2 (.I0(mem_reg_0_15_0_5_n_3), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair825" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair831" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[286] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair832" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__2 (.I0(mem_reg_0_15_0_5_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair827" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__2 (.I0(mem_reg_0_15_0_5_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair836" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__3 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair836" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__1 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair834" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__1 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__1 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair834" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__1 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair835" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__5 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair835" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__5 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair833" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__3 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair833" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2__0 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized4 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D0, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[285] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D0; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[285] ; input [71:0]phy_dout; wire CLK; wire [7:0]D0; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1__1_n_0 ; wire \entry_cnt[1]_i_1__1_n_0 ; wire \entry_cnt[2]_i_1__1_n_0 ; wire \entry_cnt[3]_i_1__1_n_0 ; wire \entry_cnt[4]_i_1__1_n_0 ; wire \entry_cnt[4]_i_2__1_n_0 ; wire \entry_cnt[4]_i_3__1_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_0_5_n_0; wire mem_reg_0_15_0_5_n_1; wire mem_reg_0_15_0_5_n_2; wire mem_reg_0_15_0_5_n_3; wire mem_reg_0_15_0_5_n_4; wire mem_reg_0_15_0_5_n_5; wire mem_reg_0_15_6_11_n_0; wire mem_reg_0_15_6_11_n_1; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__2_n_0 ; wire \my_empty[7]_i_1__2_n_0 ; wire \my_empty[7]_i_3__2_n_0 ; wire \my_empty[7]_i_4__2_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1__1_n_0 ; wire \my_full[4]_i_3__2_n_0 ; wire \my_full[4]_i_4__2_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__2_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[285] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair874" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1__1 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair872" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1__1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1__1 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair874" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1__1 (.I0(\entry_cnt[4]_i_3__1_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1__1_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1__1 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2__1 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3__1_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair872" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3__1 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3__1_n_0 )); FDRE \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[0]_i_1__1_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[1]_i_1__1_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[2]_i_1__1_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[3]_i_1__1_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1__1_n_0 ), .D(\entry_cnt[4]_i_2__1_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}), .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}), .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[5:4]), .DIB(phy_dout[7:6]), .DIC(phy_dout[9:8]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [5:4]), .DOB(\my_empty_reg[7]_1 [7:6]), .DOC(\my_empty_reg[7]_1 [9:8]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[11:10]), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [11:10]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[17:16]), .DIB(phy_dout[19:18]), .DIC(phy_dout[21:20]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [17:16]), .DOB(\my_empty_reg[7]_1 [19:18]), .DOC(\my_empty_reg[7]_1 [21:20]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[23:22]), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [23:22]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[29:28]), .DIB(phy_dout[31:30]), .DIC(phy_dout[33:32]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [29:28]), .DOB(\my_empty_reg[7]_1 [31:30]), .DOC(\my_empty_reg[7]_1 [33:32]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[35:34]), .DIB(phy_dout[37:36]), .DIC(phy_dout[39:38]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [35:34]), .DOB(\my_empty_reg[7]_1 [37:36]), .DOC(\my_empty_reg[7]_1 [39:38]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[41:40]), .DIB(phy_dout[43:42]), .DIC(phy_dout[45:44]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [41:40]), .DOB(\my_empty_reg[7]_1 [43:42]), .DOC(\my_empty_reg[7]_1 [45:44]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[47:46]), .DIB(phy_dout[49:48]), .DIC(phy_dout[51:50]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [47:46]), .DOB(\my_empty_reg[7]_1 [49:48]), .DOC(\my_empty_reg[7]_1 [51:50]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[53:52]), .DIB(phy_dout[55:54]), .DIC(phy_dout[57:56]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [53:52]), .DOB(\my_empty_reg[7]_1 [55:54]), .DOC(\my_empty_reg[7]_1 [57:56]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[59:58]), .DIB(phy_dout[61:60]), .DIC(phy_dout[63:62]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [59:58]), .DOB(\my_empty_reg[7]_1 [61:60]), .DOC(\my_empty_reg[7]_1 [63:62]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__2 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__2_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__2 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__2_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__2_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair875" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__2 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair875" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__2 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__2_n_0 )); (* syn_maxfan = "3" *) FDRE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__2_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__2_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1__1 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__2 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__2_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__2_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair873" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__2 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair873" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__2 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__2_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1__1_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__5 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair881" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__4 (.I0(mem_reg_0_15_6_11_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[7])); (* SOFT_HLUTNM = "soft_lutpair877" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__4 (.I0(mem_reg_0_15_6_11_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[6])); (* SOFT_HLUTNM = "soft_lutpair882" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__4 (.I0(mem_reg_0_15_0_5_n_4), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair879" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__4 (.I0(mem_reg_0_15_0_5_n_5), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair880" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__4 (.I0(mem_reg_0_15_0_5_n_2), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair878" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair881" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair879" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair880" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair877" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__1 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair883" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair876" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__3 (.I0(mem_reg_0_15_0_5_n_3), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair876" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair882" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[285] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair883" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__3 (.I0(mem_reg_0_15_0_5_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair878" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__3 (.I0(mem_reg_0_15_0_5_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair887" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__5 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair887" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__2 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair885" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__2 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__2 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair885" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__2 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__2_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair886" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__7 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair886" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__7 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair884" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__4 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__4 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair884" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2__1 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized5 (\my_empty_reg[7]_0 , \my_empty_reg[1]_0 , D0, D9, \my_empty_reg[7]_1 , Q, ofifo_rst, CLK, ofifo_rst_reg, mux_wrdata_en, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[284] , phy_dout); output \my_empty_reg[7]_0 ; output \my_empty_reg[1]_0 ; output [7:0]D0; output [7:0]D9; output [63:0]\my_empty_reg[7]_1 ; output [2:0]Q; input ofifo_rst; input CLK; input ofifo_rst_reg; input mux_wrdata_en; input init_calib_complete_reg_rep; input [7:0]\write_buffer.wr_buf_out_data_reg[284] ; input [71:0]phy_dout; wire CLK; wire [7:0]D0; wire [7:0]D9; wire [2:0]Q; wire \entry_cnt[0]_i_1__2_n_0 ; wire \entry_cnt[1]_i_1__2_n_0 ; wire \entry_cnt[2]_i_1__2_n_0 ; wire \entry_cnt[3]_i_1__2_n_0 ; wire \entry_cnt[4]_i_1__2_n_0 ; wire \entry_cnt[4]_i_2__2_n_0 ; wire \entry_cnt[4]_i_3__2_n_0 ; wire \entry_cnt_reg_n_0_[0] ; wire \entry_cnt_reg_n_0_[1] ; wire init_calib_complete_reg_rep; wire mem_reg_0_15_0_5_n_0; wire mem_reg_0_15_0_5_n_1; wire mem_reg_0_15_0_5_n_2; wire mem_reg_0_15_0_5_n_3; wire mem_reg_0_15_0_5_n_4; wire mem_reg_0_15_0_5_n_5; wire mem_reg_0_15_6_11_n_0; wire mem_reg_0_15_6_11_n_1; wire mem_reg_0_15_72_77_n_0; wire mem_reg_0_15_72_77_n_1; wire mem_reg_0_15_72_77_n_2; wire mem_reg_0_15_72_77_n_3; wire mem_reg_0_15_72_77_n_4; wire mem_reg_0_15_72_77_n_5; wire mem_reg_0_15_78_79_n_0; wire mem_reg_0_15_78_79_n_1; wire mux_wrdata_en; wire my_empty0; wire \my_empty[1]_i_1__3_n_0 ; wire \my_empty[7]_i_1__3_n_0 ; wire \my_empty[7]_i_3__3_n_0 ; wire \my_empty[7]_i_4__3_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1__2_n_0 ; wire \my_full[4]_i_3__3_n_0 ; wire \my_full[4]_i_4__3_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst; wire ofifo_rst_reg; wire [71:0]phy_dout; wire \rd_ptr_reg_n_0_[0] ; wire \rd_ptr_reg_n_0_[1] ; wire \rd_ptr_reg_n_0_[2] ; wire \rd_ptr_reg_n_0_[3] ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1__3_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0; wire [3:0]wr_ptr_timing; wire [7:0]\write_buffer.wr_buf_out_data_reg[284] ; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair926" *) LUT1 #( .INIT(2'h1)) \entry_cnt[0]_i_1__2 (.I0(\entry_cnt_reg_n_0_[0] ), .O(\entry_cnt[0]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair924" *) LUT5 #( .INIT(32'hAA6A5595)) \entry_cnt[1]_i_1__2 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hFF7F0080AAEA5515)) \entry_cnt[2]_i_1__2 (.I0(\entry_cnt_reg_n_0_[0] ), .I1(ofifo_rst_reg), .I2(mux_wrdata_en), .I3(\my_full_reg_n_0_[4] ), .I4(Q[0]), .I5(\entry_cnt_reg_n_0_[1] ), .O(\entry_cnt[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair926" *) LUT5 #( .INIT(32'h7F80FE01)) \entry_cnt[3]_i_1__2 (.I0(\entry_cnt[4]_i_3__2_n_0 ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt_reg_n_0_[1] ), .I3(Q[1]), .I4(Q[0]), .O(\entry_cnt[3]_i_1__2_n_0 )); LUT4 #( .INIT(16'h5003)) \entry_cnt[4]_i_1__2 (.I0(\my_full_reg_n_0_[4] ), .I1(\my_empty_reg_n_0_[7] ), .I2(mux_wrdata_en), .I3(ofifo_rst_reg), .O(\entry_cnt[4]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFF8000FFFE0001)) \entry_cnt[4]_i_2__2 (.I0(\entry_cnt_reg_n_0_[1] ), .I1(\entry_cnt_reg_n_0_[0] ), .I2(\entry_cnt[4]_i_3__2_n_0 ), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\entry_cnt[4]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair924" *) LUT3 #( .INIT(8'h08)) \entry_cnt[4]_i_3__2 (.I0(ofifo_rst_reg), .I1(mux_wrdata_en), .I2(\my_full_reg_n_0_[4] ), .O(\entry_cnt[4]_i_3__2_n_0 )); FDRE \entry_cnt_reg[0] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[0]_i_1__2_n_0 ), .Q(\entry_cnt_reg_n_0_[0] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[1] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[1]_i_1__2_n_0 ), .Q(\entry_cnt_reg_n_0_[1] ), .R(ofifo_rst)); FDRE \entry_cnt_reg[2] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[2]_i_1__2_n_0 ), .Q(Q[0]), .R(ofifo_rst)); FDRE \entry_cnt_reg[3] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[3]_i_1__2_n_0 ), .Q(Q[1]), .R(ofifo_rst)); FDRE \entry_cnt_reg[4] (.C(CLK), .CE(\entry_cnt[4]_i_1__2_n_0 ), .D(\entry_cnt[4]_i_2__2_n_0 ), .Q(Q[2]), .R(ofifo_rst)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_0_5 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}), .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}), .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT4 #( .INIT(16'h082A)) mem_reg_0_15_0_5_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_12_17 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[5:4]), .DIB(phy_dout[7:6]), .DIC(phy_dout[9:8]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [5:4]), .DOB(\my_empty_reg[7]_1 [7:6]), .DOC(\my_empty_reg[7]_1 [9:8]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_18_23 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[11:10]), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [11:10]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_24_29 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[17:16]), .DIB(phy_dout[19:18]), .DIC(phy_dout[21:20]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [17:16]), .DOB(\my_empty_reg[7]_1 [19:18]), .DOC(\my_empty_reg[7]_1 [21:20]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_30_35 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[23:22]), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [23:22]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_36_41 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[29:28]), .DIB(phy_dout[31:30]), .DIC(phy_dout[33:32]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [29:28]), .DOB(\my_empty_reg[7]_1 [31:30]), .DOC(\my_empty_reg[7]_1 [33:32]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_42_47 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[35:34]), .DIB(phy_dout[37:36]), .DIC(phy_dout[39:38]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [35:34]), .DOB(\my_empty_reg[7]_1 [37:36]), .DOC(\my_empty_reg[7]_1 [39:38]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_48_53 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[41:40]), .DIB(phy_dout[43:42]), .DIC(phy_dout[45:44]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [41:40]), .DOB(\my_empty_reg[7]_1 [43:42]), .DOC(\my_empty_reg[7]_1 [45:44]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_54_59 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[47:46]), .DIB(phy_dout[49:48]), .DIC(phy_dout[51:50]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [47:46]), .DOB(\my_empty_reg[7]_1 [49:48]), .DOC(\my_empty_reg[7]_1 [51:50]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_60_65 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[53:52]), .DIB(phy_dout[55:54]), .DIC(phy_dout[57:56]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [53:52]), .DOB(\my_empty_reg[7]_1 [55:54]), .DOC(\my_empty_reg[7]_1 [57:56]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_66_71 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[59:58]), .DIB(phy_dout[61:60]), .DIC(phy_dout[63:62]), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [59:58]), .DOB(\my_empty_reg[7]_1 [61:60]), .DOC(\my_empty_reg[7]_1 [63:62]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_6_11 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_72_77 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[65:64]), .DIB(phy_dout[67:66]), .DIC(phy_dout[69:68]), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}), .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}), .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_78_79 (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[71:70]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}), .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]), .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]), .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[1]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1__3 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(ofifo_rst), .O(\my_empty[7]_i_1__3_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2__3 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3__3_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4__3_n_0 ), .I4(\rd_ptr_reg_n_0_[2] ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair927" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3__3 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair927" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4__3 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[1] ), .I4(\rd_ptr_reg_n_0_[3] ), .O(\my_empty[7]_i_4__3_n_0 )); (* syn_maxfan = "3" *) FDRE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__3_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1__3_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1__2 (.I0(my_full0), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(ofifo_rst), .O(\my_full[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2__3 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3__3_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4__3_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair925" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3__3 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair925" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4__3 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4__3_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1__2_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); LUT3 #( .INIT(8'h0D)) out_fifo_i_1__6 (.I0(\my_empty_reg[1]_0 ), .I1(mux_wrdata_en), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair933" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__5 (.I0(mem_reg_0_15_6_11_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[7])); (* SOFT_HLUTNM = "soft_lutpair929" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__5 (.I0(mem_reg_0_15_6_11_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[6])); (* SOFT_HLUTNM = "soft_lutpair934" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__5 (.I0(mem_reg_0_15_0_5_n_4), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair931" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__5 (.I0(mem_reg_0_15_0_5_n_5), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair932" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__5 (.I0(mem_reg_0_15_0_5_n_2), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair930" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_74__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [7]), .I2(mem_reg_0_15_78_79_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair933" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_75__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [6]), .I2(mem_reg_0_15_78_79_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[6])); (* SOFT_HLUTNM = "soft_lutpair931" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [5]), .I2(mem_reg_0_15_72_77_n_4), .I3(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair932" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [4]), .I2(mem_reg_0_15_72_77_n_5), .I3(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair929" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78__0 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [3]), .I2(mem_reg_0_15_72_77_n_2), .I3(\my_empty_reg[1]_0 ), .O(D9[3])); (* SOFT_HLUTNM = "soft_lutpair935" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_79 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [2]), .I2(mem_reg_0_15_72_77_n_3), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair928" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__4 (.I0(mem_reg_0_15_0_5_n_3), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair928" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_80 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [1]), .I2(mem_reg_0_15_72_77_n_0), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair934" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_81 (.I0(init_calib_complete_reg_rep), .I1(\write_buffer.wr_buf_out_data_reg[284] [0]), .I2(mem_reg_0_15_72_77_n_1), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair935" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__4 (.I0(mem_reg_0_15_0_5_n_0), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair930" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__4 (.I0(mem_reg_0_15_0_5_n_1), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_reg_n_0_[0] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_reg_n_0_[1] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_reg_n_0_[2] ), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_reg_n_0_[3] ), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair939" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1__7 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair939" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1__3 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair937" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1__3 (.I0(\rd_ptr_reg_n_0_[2] ), .I1(\rd_ptr_reg_n_0_[0] ), .I2(\rd_ptr_reg_n_0_[1] ), .I3(\rd_ptr_reg_n_0_[3] ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1__3 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair937" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2__3 (.I0(\rd_ptr_reg_n_0_[3] ), .I1(\rd_ptr_reg_n_0_[1] ), .I2(\rd_ptr_reg_n_0_[0] ), .I3(\rd_ptr_reg_n_0_[2] ), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1__3_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(ofifo_rst)); (* SOFT_HLUTNM = "soft_lutpair938" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__9 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair938" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__9 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair936" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__5 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); LUT4 #( .INIT(16'h082A)) \wr_ptr[3]_i_1__5 (.I0(mux_wrdata_en), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0)); (* SOFT_HLUTNM = "soft_lutpair936" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_2__2 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(ofifo_rst)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(ofifo_rst)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(ofifo_rst)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized6 (\rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , wr_en, \my_empty_reg[1]_0 , D0, D1, \rd_ptr_timing_reg[0]_0 , D2, Q, SR, CLK, mux_cmd_wren, ofifo_rst_reg, mem_out); output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output wr_en; output \my_empty_reg[1]_0 ; output [4:0]D0; output [4:0]D1; output \rd_ptr_timing_reg[0]_0 ; output [1:0]D2; output [3:0]Q; input [0:0]SR; input CLK; input mux_cmd_wren; input ofifo_rst_reg; input [11:0]mem_out; wire CLK; wire [4:0]D0; wire [4:0]D1; wire [1:0]D2; wire [3:0]Q; wire [0:0]SR; wire [11:0]mem_out; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1__6_n_0 ; wire \my_empty[6]_i_1__1_n_0 ; wire \my_empty[6]_i_3_n_0 ; wire \my_empty[6]_i_4_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg_n_0_[6] ; wire my_full0; wire \my_full[3]_i_1_n_0 ; wire \my_full[3]_i_3_n_0 ; wire \my_full[3]_i_4_n_0 ; wire \my_full_reg_n_0_[3] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst_reg; wire \rd_ptr[0]_i_1__1_n_0 ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire wr_en; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; (* SOFT_HLUTNM = "soft_lutpair940" *) LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[1]_i_1__6 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg[1]_0 ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[1]_i_1__6_n_0 )); LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[6]_i_1__1 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg_n_0_[6] ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[6]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[6]_i_2 (.I0(wr_ptr_timing[2]), .I1(\my_empty[6]_i_3_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[6]_i_4_n_0 ), .I4(\rd_ptr_timing_reg[2]_2 ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair941" *) LUT5 #( .INIT(32'h00000040)) \my_empty[6]_i_3 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_timing_reg[2]_0 ), .I2(\rd_ptr_timing_reg[2]_1 ), .I3(\rd_ptr_timing_reg[2]_3 ), .I4(wr_ptr_timing[0]), .O(\my_empty[6]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair941" *) LUT5 #( .INIT(32'h84210842)) \my_empty[6]_i_4 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_timing_reg[2]_0 ), .I3(\rd_ptr_timing_reg[2]_1 ), .I4(\rd_ptr_timing_reg[2]_3 ), .O(\my_empty[6]_i_4_n_0 )); (* syn_maxfan = "3" *) FDSE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__6_n_0 ), .Q(\my_empty_reg[1]_0 ), .S(SR)); (* syn_maxfan = "3" *) FDSE \my_empty_reg[6] (.C(CLK), .CE(1'b1), .D(\my_empty[6]_i_1__1_n_0 ), .Q(\my_empty_reg_n_0_[6] ), .S(SR)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[3]_i_1 (.I0(my_full0), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[3] ), .I4(\my_empty_reg_n_0_[6] ), .I5(SR), .O(\my_full[3]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[3]_i_2 (.I0(rd_ptr_timing[2]), .I1(\my_full[3]_i_3_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[3]_i_4_n_0 ), .I4(Q[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair942" *) LUT5 #( .INIT(32'h00000040)) \my_full[3]_i_3 (.I0(rd_ptr_timing[1]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(rd_ptr_timing[0]), .O(\my_full[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair942" *) LUT5 #( .INIT(32'h84210842)) \my_full[3]_i_4 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(\my_full[3]_i_4_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[3] (.C(CLK), .CE(1'b1), .D(\my_full[3]_i_1_n_0 ), .Q(\my_full_reg_n_0_[3] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair951" *) LUT2 #( .INIT(4'h2)) out_fifo_i_10__0 (.I0(mem_out[9]), .I1(\my_empty_reg[1]_0 ), .O(D1[4])); (* SOFT_HLUTNM = "soft_lutpair947" *) LUT2 #( .INIT(4'h2)) out_fifo_i_11__0 (.I0(mem_out[8]), .I1(\my_empty_reg[1]_0 ), .O(D1[3])); (* SOFT_HLUTNM = "soft_lutpair950" *) LUT2 #( .INIT(4'h2)) out_fifo_i_12__0 (.I0(mem_out[7]), .I1(\my_empty_reg[1]_0 ), .O(D1[2])); (* SOFT_HLUTNM = "soft_lutpair948" *) LUT2 #( .INIT(4'h2)) out_fifo_i_13__0 (.I0(mem_out[6]), .I1(\my_empty_reg[1]_0 ), .O(D1[1])); (* SOFT_HLUTNM = "soft_lutpair952" *) LUT2 #( .INIT(4'hE)) out_fifo_i_14 (.I0(mem_out[5]), .I1(\my_empty_reg[1]_0 ), .O(D1[0])); (* SOFT_HLUTNM = "soft_lutpair949" *) LUT2 #( .INIT(4'h2)) out_fifo_i_18__0 (.I0(mem_out[11]), .I1(\my_empty_reg[1]_0 ), .O(D2[1])); (* SOFT_HLUTNM = "soft_lutpair949" *) LUT2 #( .INIT(4'h2)) out_fifo_i_19__0 (.I0(mem_out[10]), .I1(\my_empty_reg[1]_0 ), .O(D2[0])); (* SOFT_HLUTNM = "soft_lutpair940" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1__0 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .O(\rd_ptr_timing_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair951" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__0 (.I0(mem_out[4]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair947" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__0 (.I0(mem_out[3]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair952" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__0 (.I0(mem_out[2]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair948" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__0 (.I0(mem_out[1]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair950" *) LUT2 #( .INIT(4'hE)) out_fifo_i_6__0 (.I0(mem_out[0]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); LUT2 #( .INIT(4'h1)) \rd_ptr[0]_i_1__1 (.I0(\my_empty_reg_n_0_[6] ), .I1(ofifo_rst_reg), .O(\rd_ptr[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair945" *) LUT2 #( .INIT(4'h9)) \rd_ptr[0]_i_2 (.I0(\rd_ptr_timing_reg[2]_3 ), .I1(\rd_ptr_timing_reg[2]_0 ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair945" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[1]_i_1 (.I0(\rd_ptr_timing_reg[2]_3 ), .I1(\rd_ptr_timing_reg[2]_0 ), .I2(\rd_ptr_timing_reg[2]_1 ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair944" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr[2]_i_1 (.I0(\rd_ptr_timing_reg[2]_2 ), .I1(\rd_ptr_timing_reg[2]_0 ), .I2(\rd_ptr_timing_reg[2]_1 ), .I3(\rd_ptr_timing_reg[2]_3 ), .O(nxt_rd_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair944" *) LUT4 #( .INIT(16'h4000)) \rd_ptr[3]_i_1 (.I0(\rd_ptr_timing_reg[2]_3 ), .I1(\rd_ptr_timing_reg[2]_1 ), .I2(\rd_ptr_timing_reg[2]_0 ), .I3(\rd_ptr_timing_reg[2]_2 ), .O(nxt_rd_ptr[3])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_timing_reg[2]_0 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_timing_reg[2]_1 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_timing_reg[2]_2 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_timing_reg[2]_3 ), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr[0]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg_n_0_[6] ), .O(wr_ptr0__0)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(Q[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(Q[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(Q[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(Q[3]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair946" *) LUT2 #( .INIT(4'h9)) \wr_ptr_timing[0]_i_1 (.I0(Q[3]), .I1(Q[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair946" *) LUT3 #( .INIT(8'hB4)) \wr_ptr_timing[1]_i_1 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair943" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr_timing[2]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair943" *) LUT4 #( .INIT(16'h4000)) \wr_ptr_timing[3]_i_1 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .O(nxt_wr_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized7 (\rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , wr_en_5, \my_empty_reg[1]_0 , \my_full_reg[3]_0 , D0, D3, D5, D6, D7, Q, SR, CLK, mux_cmd_wren, B_of_full, \rd_ptr_reg[3]_0 ); output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output wr_en_5; output \my_empty_reg[1]_0 ; output \my_full_reg[3]_0 ; output [5:0]D0; output [1:0]D3; output [1:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]Q; input [0:0]SR; input CLK; input mux_cmd_wren; input B_of_full; input [17:0]\rd_ptr_reg[3]_0 ; wire B_of_full; wire CLK; wire [5:0]D0; wire [1:0]D3; wire [1:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]Q; wire [0:0]SR; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1__4_n_0 ; wire \my_empty[6]_i_1_n_0 ; wire \my_empty[6]_i_3__0_n_0 ; wire \my_empty[6]_i_4__0_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg_n_0_[6] ; wire my_full0; wire \my_full[3]_i_1__0_n_0 ; wire \my_full[3]_i_3__0_n_0 ; wire \my_full[3]_i_4__0_n_0 ; wire \my_full_reg[3]_0 ; wire \my_full_reg_n_0_[3] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire \rd_ptr[3]_i_1__0_n_0 ; wire [17:0]\rd_ptr_reg[3]_0 ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire wr_en_5; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; (* SOFT_HLUTNM = "soft_lutpair955" *) LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[1]_i_1__4 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg[1]_0 ), .I3(B_of_full), .I4(mux_cmd_wren), .O(\my_empty[1]_i_1__4_n_0 )); LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[6]_i_1 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg_n_0_[6] ), .I3(B_of_full), .I4(mux_cmd_wren), .O(\my_empty[6]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[6]_i_2__0 (.I0(wr_ptr_timing[2]), .I1(\my_empty[6]_i_3__0_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[6]_i_4__0_n_0 ), .I4(\rd_ptr_timing_reg[2]_1 ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair954" *) LUT5 #( .INIT(32'h00000040)) \my_empty[6]_i_3__0 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .I4(wr_ptr_timing[0]), .O(\my_empty[6]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair954" *) LUT5 #( .INIT(32'h84210842)) \my_empty[6]_i_4__0 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_2 ), .I4(\rd_ptr_timing_reg[2]_0 ), .O(\my_empty[6]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDSE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__4_n_0 ), .Q(\my_empty_reg[1]_0 ), .S(SR)); (* syn_maxfan = "3" *) FDSE \my_empty_reg[6] (.C(CLK), .CE(1'b1), .D(\my_empty[6]_i_1_n_0 ), .Q(\my_empty_reg_n_0_[6] ), .S(SR)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[3]_i_1__0 (.I0(my_full0), .I1(mux_cmd_wren), .I2(B_of_full), .I3(\my_full_reg_n_0_[3] ), .I4(\my_empty_reg_n_0_[6] ), .I5(SR), .O(\my_full[3]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[3]_i_2__0 (.I0(rd_ptr_timing[2]), .I1(\my_full[3]_i_3__0_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[3]_i_4__0_n_0 ), .I4(Q[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair953" *) LUT5 #( .INIT(32'h00000040)) \my_full[3]_i_3__0 (.I0(rd_ptr_timing[1]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(rd_ptr_timing[0]), .O(\my_full[3]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair953" *) LUT5 #( .INIT(32'h84210842)) \my_full[3]_i_4__0 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(\my_full[3]_i_4__0_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[3] (.C(CLK), .CE(1'b1), .D(\my_full[3]_i_1__0_n_0 ), .Q(\my_full_reg_n_0_[3] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair961" *) LUT2 #( .INIT(4'h2)) out_fifo_i_17 (.I0(\rd_ptr_reg[3]_0 [9]), .I1(\my_empty_reg[1]_0 ), .O(D5[1])); (* SOFT_HLUTNM = "soft_lutpair967" *) LUT2 #( .INIT(4'h2)) out_fifo_i_18__1 (.I0(\rd_ptr_reg[3]_0 [8]), .I1(\my_empty_reg[1]_0 ), .O(D5[0])); (* SOFT_HLUTNM = "soft_lutpair955" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1__1 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(B_of_full), .O(\my_full_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair963" *) LUT2 #( .INIT(4'h2)) out_fifo_i_23 (.I0(\rd_ptr_reg[3]_0 [13]), .I1(\my_empty_reg[1]_0 ), .O(D6[3])); (* SOFT_HLUTNM = "soft_lutpair967" *) LUT2 #( .INIT(4'h2)) out_fifo_i_24__0 (.I0(\rd_ptr_reg[3]_0 [12]), .I1(\my_empty_reg[1]_0 ), .O(D6[2])); (* SOFT_HLUTNM = "soft_lutpair962" *) LUT2 #( .INIT(4'h2)) out_fifo_i_25 (.I0(\rd_ptr_reg[3]_0 [11]), .I1(\my_empty_reg[1]_0 ), .O(D6[1])); (* SOFT_HLUTNM = "soft_lutpair965" *) LUT2 #( .INIT(4'h2)) out_fifo_i_26__0 (.I0(\rd_ptr_reg[3]_0 [10]), .I1(\my_empty_reg[1]_0 ), .O(D6[0])); (* SOFT_HLUTNM = "soft_lutpair968" *) LUT2 #( .INIT(4'h2)) out_fifo_i_27__0 (.I0(\rd_ptr_reg[3]_0 [17]), .I1(\my_empty_reg[1]_0 ), .O(D7[3])); (* SOFT_HLUTNM = "soft_lutpair964" *) LUT2 #( .INIT(4'h2)) out_fifo_i_28__0 (.I0(\rd_ptr_reg[3]_0 [16]), .I1(\my_empty_reg[1]_0 ), .O(D7[2])); (* SOFT_HLUTNM = "soft_lutpair960" *) LUT2 #( .INIT(4'h2)) out_fifo_i_29__0 (.I0(\rd_ptr_reg[3]_0 [15]), .I1(\my_empty_reg[1]_0 ), .O(D7[1])); (* SOFT_HLUTNM = "soft_lutpair964" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__1 (.I0(\rd_ptr_reg[3]_0 [1]), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair968" *) LUT2 #( .INIT(4'h2)) out_fifo_i_30 (.I0(\rd_ptr_reg[3]_0 [14]), .I1(\my_empty_reg[1]_0 ), .O(D7[0])); (* SOFT_HLUTNM = "soft_lutpair961" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__1 (.I0(\rd_ptr_reg[3]_0 [0]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair965" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__1 (.I0(\rd_ptr_reg[3]_0 [5]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair962" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__1 (.I0(\rd_ptr_reg[3]_0 [4]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair963" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__1 (.I0(\rd_ptr_reg[3]_0 [3]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair960" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__0 (.I0(\rd_ptr_reg[3]_0 [2]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair966" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__0 (.I0(\rd_ptr_reg[3]_0 [7]), .I1(\my_empty_reg[1]_0 ), .O(D3[1])); (* SOFT_HLUTNM = "soft_lutpair966" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__0 (.I0(\rd_ptr_reg[3]_0 [6]), .I1(\my_empty_reg[1]_0 ), .O(D3[0])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(B_of_full), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en_5)); (* SOFT_HLUTNM = "soft_lutpair958" *) LUT2 #( .INIT(4'h9)) \rd_ptr[0]_i_1 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair958" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[1]_i_1__0 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair956" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr[2]_i_1__0 (.I0(\rd_ptr_timing_reg[2]_1 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr[3]_i_1__0 (.I0(\my_empty_reg_n_0_[6] ), .I1(B_of_full), .O(\rd_ptr[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair956" *) LUT4 #( .INIT(16'h4000)) \rd_ptr[3]_i_2 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_2 ), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_1 ), .O(nxt_rd_ptr[3])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_timing_reg[2]_3 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_timing_reg[2]_2 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_timing_reg[2]_1 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_timing_reg[2]_0 ), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__0_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(B_of_full), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg_n_0_[6] ), .O(wr_ptr0__0)); (* SOFT_HLUTNM = "soft_lutpair959" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__0 (.I0(Q[3]), .I1(Q[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair959" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__0 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair957" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair957" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_1__0 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(Q[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(Q[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(Q[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(Q[3]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized8 (\rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , wr_en_6, \my_empty_reg[1]_0 , D2, D3, \rd_ptr_timing_reg[0]_0 , D0, D1, D4, D7, D8, D9, Q, SR, CLK, mux_cmd_wren, ofifo_rst_reg, \rd_ptr_reg[3]_0 ); output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output wr_en_6; output \my_empty_reg[1]_0 ; output [4:0]D2; output [4:0]D3; output \rd_ptr_timing_reg[0]_0 ; output [5:0]D0; output [3:0]D1; output [3:0]D4; output [3:0]D7; output [3:0]D8; output [1:0]D9; output [3:0]Q; input [0:0]SR; input CLK; input mux_cmd_wren; input ofifo_rst_reg; input [33:0]\rd_ptr_reg[3]_0 ; wire CLK; wire [5:0]D0; wire [3:0]D1; wire [4:0]D2; wire [4:0]D3; wire [3:0]D4; wire [3:0]D7; wire [3:0]D8; wire [1:0]D9; wire [3:0]Q; wire [0:0]SR; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1__5_n_0 ; wire \my_empty[6]_i_1__0_n_0 ; wire \my_empty[6]_i_3__1_n_0 ; wire \my_empty[6]_i_4__1_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg_n_0_[6] ; wire my_full0; wire \my_full[3]_i_1__1_n_0 ; wire \my_full[3]_i_3__1_n_0 ; wire \my_full[3]_i_4__1_n_0 ; wire \my_full_reg_n_0_[3] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst_reg; wire \rd_ptr[3]_i_1__1_n_0 ; wire [33:0]\rd_ptr_reg[3]_0 ; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire wr_en_6; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; (* SOFT_HLUTNM = "soft_lutpair971" *) LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[1]_i_1__5 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg[1]_0 ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[1]_i_1__5_n_0 )); LUT5 #( .INIT(32'hC0F0F0F2)) \my_empty[6]_i_1__0 (.I0(my_empty0), .I1(\my_full_reg_n_0_[3] ), .I2(\my_empty_reg_n_0_[6] ), .I3(ofifo_rst_reg), .I4(mux_cmd_wren), .O(\my_empty[6]_i_1__0_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[6]_i_2__1 (.I0(wr_ptr_timing[2]), .I1(\my_empty[6]_i_3__1_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[6]_i_4__1_n_0 ), .I4(\rd_ptr_timing_reg[2]_1 ), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair969" *) LUT5 #( .INIT(32'h00000040)) \my_empty[6]_i_3__1 (.I0(wr_ptr_timing[1]), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .I4(wr_ptr_timing[0]), .O(\my_empty[6]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair969" *) LUT5 #( .INIT(32'h84210842)) \my_empty[6]_i_4__1 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_2 ), .I4(\rd_ptr_timing_reg[2]_0 ), .O(\my_empty[6]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDSE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1__5_n_0 ), .Q(\my_empty_reg[1]_0 ), .S(SR)); (* syn_maxfan = "3" *) FDSE \my_empty_reg[6] (.C(CLK), .CE(1'b1), .D(\my_empty[6]_i_1__0_n_0 ), .Q(\my_empty_reg_n_0_[6] ), .S(SR)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[3]_i_1__1 (.I0(my_full0), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[3] ), .I4(\my_empty_reg_n_0_[6] ), .I5(SR), .O(\my_full[3]_i_1__1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[3]_i_2__1 (.I0(rd_ptr_timing[2]), .I1(\my_full[3]_i_3__1_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[3]_i_4__1_n_0 ), .I4(Q[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair970" *) LUT5 #( .INIT(32'h00000040)) \my_full[3]_i_3__1 (.I0(rd_ptr_timing[1]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(rd_ptr_timing[0]), .O(\my_full[3]_i_3__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair970" *) LUT5 #( .INIT(32'h84210842)) \my_full[3]_i_4__1 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(\my_full[3]_i_4__1_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[3] (.C(CLK), .CE(1'b1), .D(\my_full[3]_i_1__1_n_0 ), .Q(\my_full_reg_n_0_[3] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair985" *) LUT2 #( .INIT(4'h2)) out_fifo_i_10__1 (.I0(\rd_ptr_reg[3]_0 [7]), .I1(\my_empty_reg[1]_0 ), .O(D1[1])); (* SOFT_HLUTNM = "soft_lutpair979" *) LUT2 #( .INIT(4'h2)) out_fifo_i_11__1 (.I0(\rd_ptr_reg[3]_0 [6]), .I1(\my_empty_reg[1]_0 ), .O(D1[0])); (* SOFT_HLUTNM = "soft_lutpair986" *) LUT2 #( .INIT(4'h2)) out_fifo_i_12__1 (.I0(\rd_ptr_reg[3]_0 [14]), .I1(\my_empty_reg[1]_0 ), .O(D2[4])); (* SOFT_HLUTNM = "soft_lutpair982" *) LUT2 #( .INIT(4'h2)) out_fifo_i_13__1 (.I0(\rd_ptr_reg[3]_0 [13]), .I1(\my_empty_reg[1]_0 ), .O(D2[3])); (* SOFT_HLUTNM = "soft_lutpair979" *) LUT2 #( .INIT(4'h2)) out_fifo_i_14__0 (.I0(\rd_ptr_reg[3]_0 [12]), .I1(\my_empty_reg[1]_0 ), .O(D2[2])); (* SOFT_HLUTNM = "soft_lutpair981" *) LUT2 #( .INIT(4'h2)) out_fifo_i_15 (.I0(\rd_ptr_reg[3]_0 [11]), .I1(\my_empty_reg[1]_0 ), .O(D2[1])); (* SOFT_HLUTNM = "soft_lutpair978" *) LUT2 #( .INIT(4'hE)) out_fifo_i_16 (.I0(\rd_ptr_reg[3]_0 [10]), .I1(\my_empty_reg[1]_0 ), .O(D2[0])); (* SOFT_HLUTNM = "soft_lutpair971" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1__2 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .O(\rd_ptr_timing_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair989" *) LUT2 #( .INIT(4'h2)) out_fifo_i_20__0 (.I0(\rd_ptr_reg[3]_0 [19]), .I1(\my_empty_reg[1]_0 ), .O(D3[4])); (* SOFT_HLUTNM = "soft_lutpair982" *) LUT2 #( .INIT(4'h2)) out_fifo_i_21__0 (.I0(\rd_ptr_reg[3]_0 [18]), .I1(\my_empty_reg[1]_0 ), .O(D3[3])); (* SOFT_HLUTNM = "soft_lutpair990" *) LUT2 #( .INIT(4'h2)) out_fifo_i_22 (.I0(\rd_ptr_reg[3]_0 [17]), .I1(\my_empty_reg[1]_0 ), .O(D3[2])); (* SOFT_HLUTNM = "soft_lutpair981" *) LUT2 #( .INIT(4'h2)) out_fifo_i_23__0 (.I0(\rd_ptr_reg[3]_0 [16]), .I1(\my_empty_reg[1]_0 ), .O(D3[1])); (* SOFT_HLUTNM = "soft_lutpair988" *) LUT2 #( .INIT(4'hE)) out_fifo_i_24 (.I0(\rd_ptr_reg[3]_0 [15]), .I1(\my_empty_reg[1]_0 ), .O(D3[0])); (* SOFT_HLUTNM = "soft_lutpair991" *) LUT2 #( .INIT(4'h2)) out_fifo_i_28__1 (.I0(\rd_ptr_reg[3]_0 [23]), .I1(\my_empty_reg[1]_0 ), .O(D4[3])); (* SOFT_HLUTNM = "soft_lutpair976" *) LUT2 #( .INIT(4'h2)) out_fifo_i_29__1 (.I0(\rd_ptr_reg[3]_0 [22]), .I1(\my_empty_reg[1]_0 ), .O(D4[2])); (* SOFT_HLUTNM = "soft_lutpair983" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2__2 (.I0(\rd_ptr_reg[3]_0 [1]), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair992" *) LUT2 #( .INIT(4'h2)) out_fifo_i_30__0 (.I0(\rd_ptr_reg[3]_0 [21]), .I1(\my_empty_reg[1]_0 ), .O(D4[1])); (* SOFT_HLUTNM = "soft_lutpair986" *) LUT2 #( .INIT(4'h2)) out_fifo_i_31 (.I0(\rd_ptr_reg[3]_0 [20]), .I1(\my_empty_reg[1]_0 ), .O(D4[0])); (* SOFT_HLUTNM = "soft_lutpair978" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3__2 (.I0(\rd_ptr_reg[3]_0 [0]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair985" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4__2 (.I0(\rd_ptr_reg[3]_0 [5]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair991" *) LUT2 #( .INIT(4'h2)) out_fifo_i_52__0 (.I0(\rd_ptr_reg[3]_0 [27]), .I1(\my_empty_reg[1]_0 ), .O(D7[3])); (* SOFT_HLUTNM = "soft_lutpair980" *) LUT2 #( .INIT(4'h2)) out_fifo_i_53__0 (.I0(\rd_ptr_reg[3]_0 [26]), .I1(\my_empty_reg[1]_0 ), .O(D7[2])); (* SOFT_HLUTNM = "soft_lutpair988" *) LUT2 #( .INIT(4'h2)) out_fifo_i_54 (.I0(\rd_ptr_reg[3]_0 [25]), .I1(\my_empty_reg[1]_0 ), .O(D7[1])); (* SOFT_HLUTNM = "soft_lutpair984" *) LUT2 #( .INIT(4'h2)) out_fifo_i_55 (.I0(\rd_ptr_reg[3]_0 [24]), .I1(\my_empty_reg[1]_0 ), .O(D7[0])); (* SOFT_HLUTNM = "soft_lutpair980" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5__2 (.I0(\rd_ptr_reg[3]_0 [4]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair989" *) LUT2 #( .INIT(4'h2)) out_fifo_i_60__0 (.I0(\rd_ptr_reg[3]_0 [31]), .I1(\my_empty_reg[1]_0 ), .O(D8[3])); (* SOFT_HLUTNM = "soft_lutpair987" *) LUT2 #( .INIT(4'h2)) out_fifo_i_61__0 (.I0(\rd_ptr_reg[3]_0 [30]), .I1(\my_empty_reg[1]_0 ), .O(D8[2])); (* SOFT_HLUTNM = "soft_lutpair992" *) LUT2 #( .INIT(4'h2)) out_fifo_i_62 (.I0(\rd_ptr_reg[3]_0 [29]), .I1(\my_empty_reg[1]_0 ), .O(D8[1])); (* SOFT_HLUTNM = "soft_lutpair977" *) LUT2 #( .INIT(4'h2)) out_fifo_i_63 (.I0(\rd_ptr_reg[3]_0 [28]), .I1(\my_empty_reg[1]_0 ), .O(D8[0])); (* SOFT_HLUTNM = "soft_lutpair990" *) LUT2 #( .INIT(4'h2)) out_fifo_i_68__0 (.I0(\rd_ptr_reg[3]_0 [33]), .I1(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair987" *) LUT2 #( .INIT(4'h2)) out_fifo_i_69__0 (.I0(\rd_ptr_reg[3]_0 [32]), .I1(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair983" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6__2 (.I0(\rd_ptr_reg[3]_0 [3]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair976" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7__1 (.I0(\rd_ptr_reg[3]_0 [2]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair984" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8__1 (.I0(\rd_ptr_reg[3]_0 [9]), .I1(\my_empty_reg[1]_0 ), .O(D1[3])); (* SOFT_HLUTNM = "soft_lutpair977" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9__1 (.I0(\rd_ptr_reg[3]_0 [8]), .I1(\my_empty_reg[1]_0 ), .O(D1[2])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en_6)); (* SOFT_HLUTNM = "soft_lutpair975" *) LUT2 #( .INIT(4'h9)) \rd_ptr[0]_i_1__0 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair975" *) LUT3 #( .INIT(8'hB4)) \rd_ptr[1]_i_1__1 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair972" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr[2]_i_1__1 (.I0(\rd_ptr_timing_reg[2]_1 ), .I1(\rd_ptr_timing_reg[2]_3 ), .I2(\rd_ptr_timing_reg[2]_2 ), .I3(\rd_ptr_timing_reg[2]_0 ), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr[3]_i_1__1 (.I0(\my_empty_reg_n_0_[6] ), .I1(ofifo_rst_reg), .O(\rd_ptr[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair972" *) LUT4 #( .INIT(16'h4000)) \rd_ptr[3]_i_2__0 (.I0(\rd_ptr_timing_reg[2]_0 ), .I1(\rd_ptr_timing_reg[2]_2 ), .I2(\rd_ptr_timing_reg[2]_3 ), .I3(\rd_ptr_timing_reg[2]_1 ), .O(nxt_rd_ptr[3])); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(\rd_ptr_timing_reg[2]_3 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(\rd_ptr_timing_reg[2]_2 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(\rd_ptr_timing_reg[2]_1 ), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(\rd_ptr_timing_reg[2]_0 ), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr[3]_i_1__1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[3] ), .I3(\my_empty_reg_n_0_[6] ), .O(wr_ptr0__0)); (* SOFT_HLUTNM = "soft_lutpair974" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1__1 (.I0(Q[3]), .I1(Q[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair974" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1__1 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair973" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair973" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_1__1 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(Q[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(Q[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(Q[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(Q[3]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_of_pre_fifo" *) module ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized9 (D9, \my_empty_reg[1]_0 , \my_empty_reg[7]_0 , D0, D1, D2, D3, D4, D5, D6, D7, D8, \my_empty_reg[7]_1 , SR, CLK, init_calib_complete_reg_rep__5, mc_cas_n, \cmd_pipe_plus.mc_address_reg[43] , init_calib_complete_reg_rep, mux_cmd_wren, ofifo_rst_reg, phy_dout, init_calib_complete_reg_rep__6); output [7:0]D9; output \my_empty_reg[1]_0 ; output \my_empty_reg[7]_0 ; output [5:0]D0; output [3:0]D1; output [3:0]D2; output [3:0]D3; output [3:0]D4; output [3:0]D5; output [3:0]D6; output [3:0]D7; output [3:0]D8; output [31:0]\my_empty_reg[7]_1 ; input [0:0]SR; input CLK; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input init_calib_complete_reg_rep; input mux_cmd_wren; input ofifo_rst_reg; input [35:0]phy_dout; input init_calib_complete_reg_rep__6; wire CLK; wire [5:0]D0; wire [3:0]D1; wire [3:0]D2; wire [3:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [7:0]D9; wire [0:0]SR; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire init_calib_complete_reg_rep__6; wire [0:0]mc_cas_n; wire [77:0]mem_out; wire mux_cmd_wren; wire my_empty0; wire \my_empty[1]_i_1_n_0 ; wire \my_empty[7]_i_1_n_0 ; wire \my_empty[7]_i_3_n_0 ; wire \my_empty[7]_i_4_n_0 ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[7]_0 ; wire [31:0]\my_empty_reg[7]_1 ; wire \my_empty_reg_n_0_[7] ; wire my_full0; wire \my_full[4]_i_1_n_0 ; wire \my_full[4]_i_3_n_0 ; wire \my_full[4]_i_4_n_0 ; wire \my_full_reg_n_0_[4] ; wire [3:0]nxt_rd_ptr; wire [3:0]nxt_wr_ptr; wire ofifo_rst_reg; wire [35:0]phy_dout; wire [3:0]rd_ptr; wire [3:0]rd_ptr_timing; wire \rd_ptr_timing[3]_i_1_n_0 ; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en; wire [3:0]wr_ptr; wire wr_ptr0__0; wire [3:0]wr_ptr_timing; wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED; wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair1003" *) LUT3 #( .INIT(8'hAC)) d_out (.I0(init_calib_complete_reg_rep__6), .I1(mem_out[75]), .I2(\my_empty_reg[1]_0 ), .O(D9[3])); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_0_5 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(mem_out[1:0]), .DOB(mem_out[3:2]), .DOC(mem_out[5:4]), .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_12_17 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(phy_dout[5:4]), .DID({1'b0,1'b0}), .DOA(mem_out[13:12]), .DOB(mem_out[15:14]), .DOC(\my_empty_reg[7]_1 [5:4]), .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_18_23 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[7:6]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [7:6]), .DOB(mem_out[21:20]), .DOC(mem_out[23:22]), .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_24_29 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[9:8]), .DIB(phy_dout[11:10]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [9:8]), .DOB(\my_empty_reg[7]_1 [11:10]), .DOC(mem_out[29:28]), .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_30_35 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[13:12]), .DIC(phy_dout[15:14]), .DID({1'b0,1'b0}), .DOA(mem_out[31:30]), .DOB(\my_empty_reg[7]_1 [13:12]), .DOC(\my_empty_reg[7]_1 [15:14]), .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_36_41 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(phy_dout[17:16]), .DID({1'b0,1'b0}), .DOA(mem_out[37:36]), .DOB(mem_out[39:38]), .DOC(\my_empty_reg[7]_1 [17:16]), .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_42_47 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[19:18]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [19:18]), .DOB(mem_out[45:44]), .DOC(mem_out[47:46]), .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_48_53 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[21:20]), .DIB(phy_dout[23:22]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [21:20]), .DOB(\my_empty_reg[7]_1 [23:22]), .DOC(mem_out[53:52]), .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_54_59 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[25:24]), .DIC(phy_dout[27:26]), .DID({1'b0,1'b0}), .DOA(mem_out[55:54]), .DOB(\my_empty_reg[7]_1 [25:24]), .DOC(\my_empty_reg[7]_1 [27:26]), .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_60_65 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB({1'b0,1'b0}), .DIC(phy_dout[29:28]), .DID({1'b0,1'b0}), .DOA(mem_out[61:60]), .DOB(mem_out[63:62]), .DOC(\my_empty_reg[7]_1 [29:28]), .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_66_71 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[31:30]), .DIB({1'b0,1'b0}), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(\my_empty_reg[7]_1 [31:30]), .DOB(mem_out[69:68]), .DOC(mem_out[71:70]), .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_6_11 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA({1'b0,1'b0}), .DIB(phy_dout[1:0]), .DIC(phy_dout[3:2]), .DID({1'b0,1'b0}), .DOA(mem_out[7:6]), .DOB(\my_empty_reg[7]_1 [1:0]), .DOC(\my_empty_reg[7]_1 [3:2]), .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M mem_reg_0_15_72_77 (.ADDRA({1'b0,rd_ptr}), .ADDRB({1'b0,rd_ptr}), .ADDRC({1'b0,rd_ptr}), .ADDRD({1'b0,wr_ptr}), .DIA(phy_dout[33:32]), .DIB(phy_dout[35:34]), .DIC({1'b0,1'b0}), .DID({1'b0,1'b0}), .DOA(mem_out[73:72]), .DOB(mem_out[75:74]), .DOC(mem_out[77:76]), .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]), .WCLK(CLK), .WE(wr_en)); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[1]_i_1 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_empty_reg[1]_0 ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(SR), .O(\my_empty[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF071F070)) \my_empty[7]_i_1 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_empty_reg_n_0_[7] ), .I3(\my_full_reg_n_0_[4] ), .I4(my_empty0), .I5(SR), .O(\my_empty[7]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_empty[7]_i_2 (.I0(wr_ptr_timing[2]), .I1(\my_empty[7]_i_3_n_0 ), .I2(wr_ptr_timing[3]), .I3(\my_empty[7]_i_4_n_0 ), .I4(rd_ptr[2]), .O(my_empty0)); (* SOFT_HLUTNM = "soft_lutpair993" *) LUT5 #( .INIT(32'h00000040)) \my_empty[7]_i_3 (.I0(wr_ptr_timing[1]), .I1(rd_ptr[0]), .I2(rd_ptr[1]), .I3(rd_ptr[3]), .I4(wr_ptr_timing[0]), .O(\my_empty[7]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair993" *) LUT5 #( .INIT(32'h84210842)) \my_empty[7]_i_4 (.I0(wr_ptr_timing[0]), .I1(wr_ptr_timing[1]), .I2(rd_ptr[0]), .I3(rd_ptr[1]), .I4(rd_ptr[3]), .O(\my_empty[7]_i_4_n_0 )); (* syn_maxfan = "3" *) FDRE \my_empty_reg[1] (.C(CLK), .CE(1'b1), .D(\my_empty[1]_i_1_n_0 ), .Q(\my_empty_reg[1]_0 ), .R(1'b0)); (* syn_maxfan = "3" *) FDRE \my_empty_reg[7] (.C(CLK), .CE(1'b1), .D(\my_empty[7]_i_1_n_0 ), .Q(\my_empty_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000FF00FC80)) \my_full[4]_i_1 (.I0(my_full0), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .I3(\my_full_reg_n_0_[4] ), .I4(\my_empty_reg_n_0_[7] ), .I5(SR), .O(\my_full[4]_i_1_n_0 )); LUT5 #( .INIT(32'h4A400D08)) \my_full[4]_i_2 (.I0(rd_ptr_timing[2]), .I1(\my_full[4]_i_3_n_0 ), .I2(rd_ptr_timing[3]), .I3(\my_full[4]_i_4_n_0 ), .I4(wr_ptr[2]), .O(my_full0)); (* SOFT_HLUTNM = "soft_lutpair994" *) LUT5 #( .INIT(32'h00000040)) \my_full[4]_i_3 (.I0(rd_ptr_timing[1]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .I4(rd_ptr_timing[0]), .O(\my_full[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair994" *) LUT5 #( .INIT(32'h84210842)) \my_full[4]_i_4 (.I0(rd_ptr_timing[0]), .I1(rd_ptr_timing[1]), .I2(wr_ptr[0]), .I3(wr_ptr[1]), .I4(wr_ptr[3]), .O(\my_full[4]_i_4_n_0 )); (* syn_maxfan = "3" *) FDRE \my_full_reg[4] (.C(CLK), .CE(1'b1), .D(\my_full[4]_i_1_n_0 ), .Q(\my_full_reg_n_0_[4] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1001" *) LUT3 #( .INIT(8'h0D)) out_fifo_i_1 (.I0(\my_empty_reg[1]_0 ), .I1(mux_cmd_wren), .I2(ofifo_rst_reg), .O(\my_empty_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair1009" *) LUT2 #( .INIT(4'h2)) out_fifo_i_10 (.I0(mem_out[15]), .I1(\my_empty_reg[1]_0 ), .O(D1[3])); (* SOFT_HLUTNM = "soft_lutpair998" *) LUT2 #( .INIT(4'h2)) out_fifo_i_11 (.I0(mem_out[14]), .I1(\my_empty_reg[1]_0 ), .O(D1[2])); (* SOFT_HLUTNM = "soft_lutpair1012" *) LUT2 #( .INIT(4'h2)) out_fifo_i_12 (.I0(mem_out[13]), .I1(\my_empty_reg[1]_0 ), .O(D1[1])); (* SOFT_HLUTNM = "soft_lutpair1003" *) LUT2 #( .INIT(4'h2)) out_fifo_i_13 (.I0(mem_out[12]), .I1(\my_empty_reg[1]_0 ), .O(D1[0])); (* SOFT_HLUTNM = "soft_lutpair1013" *) LUT2 #( .INIT(4'h2)) out_fifo_i_18 (.I0(mem_out[23]), .I1(\my_empty_reg[1]_0 ), .O(D2[3])); (* SOFT_HLUTNM = "soft_lutpair1006" *) LUT2 #( .INIT(4'h2)) out_fifo_i_19 (.I0(mem_out[22]), .I1(\my_empty_reg[1]_0 ), .O(D2[2])); (* SOFT_HLUTNM = "soft_lutpair1010" *) LUT2 #( .INIT(4'h2)) out_fifo_i_2 (.I0(mem_out[7]), .I1(\my_empty_reg[1]_0 ), .O(D0[5])); (* SOFT_HLUTNM = "soft_lutpair1013" *) LUT2 #( .INIT(4'h2)) out_fifo_i_20 (.I0(mem_out[21]), .I1(\my_empty_reg[1]_0 ), .O(D2[1])); (* SOFT_HLUTNM = "soft_lutpair1005" *) LUT2 #( .INIT(4'h2)) out_fifo_i_21 (.I0(mem_out[20]), .I1(\my_empty_reg[1]_0 ), .O(D2[0])); (* SOFT_HLUTNM = "soft_lutpair1018" *) LUT2 #( .INIT(4'h2)) out_fifo_i_26 (.I0(mem_out[31]), .I1(\my_empty_reg[1]_0 ), .O(D3[3])); (* SOFT_HLUTNM = "soft_lutpair1006" *) LUT2 #( .INIT(4'h2)) out_fifo_i_27 (.I0(mem_out[30]), .I1(\my_empty_reg[1]_0 ), .O(D3[2])); (* SOFT_HLUTNM = "soft_lutpair1019" *) LUT2 #( .INIT(4'h2)) out_fifo_i_28 (.I0(mem_out[29]), .I1(\my_empty_reg[1]_0 ), .O(D3[1])); (* SOFT_HLUTNM = "soft_lutpair1008" *) LUT2 #( .INIT(4'h2)) out_fifo_i_29 (.I0(mem_out[28]), .I1(\my_empty_reg[1]_0 ), .O(D3[0])); (* SOFT_HLUTNM = "soft_lutpair999" *) LUT2 #( .INIT(4'h2)) out_fifo_i_3 (.I0(mem_out[6]), .I1(\my_empty_reg[1]_0 ), .O(D0[4])); (* SOFT_HLUTNM = "soft_lutpair1021" *) LUT2 #( .INIT(4'h2)) out_fifo_i_34 (.I0(mem_out[39]), .I1(\my_empty_reg[1]_0 ), .O(D4[3])); (* SOFT_HLUTNM = "soft_lutpair1007" *) LUT2 #( .INIT(4'h2)) out_fifo_i_35 (.I0(mem_out[38]), .I1(\my_empty_reg[1]_0 ), .O(D4[2])); LUT2 #( .INIT(4'h2)) out_fifo_i_36 (.I0(mem_out[37]), .I1(\my_empty_reg[1]_0 ), .O(D4[1])); (* SOFT_HLUTNM = "soft_lutpair1011" *) LUT2 #( .INIT(4'h2)) out_fifo_i_37 (.I0(mem_out[36]), .I1(\my_empty_reg[1]_0 ), .O(D4[0])); (* SOFT_HLUTNM = "soft_lutpair1011" *) LUT2 #( .INIT(4'h2)) out_fifo_i_4 (.I0(mem_out[5]), .I1(\my_empty_reg[1]_0 ), .O(D0[3])); (* SOFT_HLUTNM = "soft_lutpair1020" *) LUT2 #( .INIT(4'h2)) out_fifo_i_42 (.I0(mem_out[47]), .I1(\my_empty_reg[1]_0 ), .O(D5[3])); (* SOFT_HLUTNM = "soft_lutpair1009" *) LUT2 #( .INIT(4'h2)) out_fifo_i_43 (.I0(mem_out[46]), .I1(\my_empty_reg[1]_0 ), .O(D5[2])); (* SOFT_HLUTNM = "soft_lutpair1017" *) LUT2 #( .INIT(4'h2)) out_fifo_i_44 (.I0(mem_out[45]), .I1(\my_empty_reg[1]_0 ), .O(D5[1])); (* SOFT_HLUTNM = "soft_lutpair1007" *) LUT2 #( .INIT(4'h2)) out_fifo_i_45 (.I0(mem_out[44]), .I1(\my_empty_reg[1]_0 ), .O(D5[0])); (* SOFT_HLUTNM = "soft_lutpair1004" *) LUT2 #( .INIT(4'h2)) out_fifo_i_5 (.I0(mem_out[4]), .I1(\my_empty_reg[1]_0 ), .O(D0[2])); (* SOFT_HLUTNM = "soft_lutpair1017" *) LUT2 #( .INIT(4'h2)) out_fifo_i_50 (.I0(mem_out[55]), .I1(\my_empty_reg[1]_0 ), .O(D6[3])); (* SOFT_HLUTNM = "soft_lutpair1014" *) LUT2 #( .INIT(4'h2)) out_fifo_i_51 (.I0(mem_out[54]), .I1(\my_empty_reg[1]_0 ), .O(D6[2])); (* SOFT_HLUTNM = "soft_lutpair1018" *) LUT2 #( .INIT(4'h2)) out_fifo_i_52 (.I0(mem_out[53]), .I1(\my_empty_reg[1]_0 ), .O(D6[1])); (* SOFT_HLUTNM = "soft_lutpair1014" *) LUT2 #( .INIT(4'h2)) out_fifo_i_53 (.I0(mem_out[52]), .I1(\my_empty_reg[1]_0 ), .O(D6[0])); (* SOFT_HLUTNM = "soft_lutpair1015" *) LUT2 #( .INIT(4'h2)) out_fifo_i_58 (.I0(mem_out[63]), .I1(\my_empty_reg[1]_0 ), .O(D7[3])); (* SOFT_HLUTNM = "soft_lutpair1005" *) LUT2 #( .INIT(4'h2)) out_fifo_i_59 (.I0(mem_out[62]), .I1(\my_empty_reg[1]_0 ), .O(D7[2])); (* SOFT_HLUTNM = "soft_lutpair1008" *) LUT2 #( .INIT(4'h2)) out_fifo_i_6 (.I0(mem_out[3]), .I1(\my_empty_reg[1]_0 ), .O(D0[1])); (* SOFT_HLUTNM = "soft_lutpair1019" *) LUT2 #( .INIT(4'h2)) out_fifo_i_60 (.I0(mem_out[61]), .I1(\my_empty_reg[1]_0 ), .O(D7[1])); (* SOFT_HLUTNM = "soft_lutpair1010" *) LUT2 #( .INIT(4'h2)) out_fifo_i_61 (.I0(mem_out[60]), .I1(\my_empty_reg[1]_0 ), .O(D7[0])); (* SOFT_HLUTNM = "soft_lutpair1020" *) LUT2 #( .INIT(4'h2)) out_fifo_i_66 (.I0(mem_out[71]), .I1(\my_empty_reg[1]_0 ), .O(D8[3])); (* SOFT_HLUTNM = "soft_lutpair1015" *) LUT2 #( .INIT(4'h2)) out_fifo_i_67 (.I0(mem_out[70]), .I1(\my_empty_reg[1]_0 ), .O(D8[2])); (* SOFT_HLUTNM = "soft_lutpair1016" *) LUT2 #( .INIT(4'h2)) out_fifo_i_68 (.I0(mem_out[69]), .I1(\my_empty_reg[1]_0 ), .O(D8[1])); (* SOFT_HLUTNM = "soft_lutpair1004" *) LUT2 #( .INIT(4'h2)) out_fifo_i_69 (.I0(mem_out[68]), .I1(\my_empty_reg[1]_0 ), .O(D8[0])); (* SOFT_HLUTNM = "soft_lutpair997" *) LUT2 #( .INIT(4'h2)) out_fifo_i_7 (.I0(mem_out[2]), .I1(\my_empty_reg[1]_0 ), .O(D0[0])); (* SOFT_HLUTNM = "soft_lutpair1021" *) LUT2 #( .INIT(4'h2)) out_fifo_i_74 (.I0(mem_out[77]), .I1(\my_empty_reg[1]_0 ), .O(D9[5])); (* SOFT_HLUTNM = "soft_lutpair1016" *) LUT2 #( .INIT(4'h2)) out_fifo_i_75 (.I0(mem_out[76]), .I1(\my_empty_reg[1]_0 ), .O(D9[4])); (* SOFT_HLUTNM = "soft_lutpair999" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_76 (.I0(\cmd_pipe_plus.mc_address_reg[43] [1]), .I1(init_calib_complete_reg_rep), .I2(mem_out[74]), .I3(\my_empty_reg[1]_0 ), .O(D9[2])); (* SOFT_HLUTNM = "soft_lutpair998" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_77 (.I0(init_calib_complete_reg_rep__5), .I1(mc_cas_n), .I2(mem_out[73]), .I3(\my_empty_reg[1]_0 ), .O(D9[1])); (* SOFT_HLUTNM = "soft_lutpair997" *) LUT4 #( .INIT(16'h88F0)) out_fifo_i_78 (.I0(\cmd_pipe_plus.mc_address_reg[43] [0]), .I1(init_calib_complete_reg_rep), .I2(mem_out[72]), .I3(\my_empty_reg[1]_0 ), .O(D9[0])); (* SOFT_HLUTNM = "soft_lutpair1012" *) LUT2 #( .INIT(4'h2)) out_fifo_i_8 (.I0(mem_out[1]), .I1(\my_empty_reg[1]_0 ), .O(D9[7])); (* SOFT_HLUTNM = "soft_lutpair1001" *) LUT2 #( .INIT(4'h2)) out_fifo_i_9 (.I0(mem_out[0]), .I1(\my_empty_reg[1]_0 ), .O(D9[6])); LUT4 #( .INIT(16'h082A)) p_17_out (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg[1]_0 ), .O(wr_en)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE \rd_ptr_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr[3]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair1002" *) LUT2 #( .INIT(4'h9)) \rd_ptr_timing[0]_i_1 (.I0(rd_ptr[3]), .I1(rd_ptr[0]), .O(nxt_rd_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair1002" *) LUT3 #( .INIT(8'hB4)) \rd_ptr_timing[1]_i_1 (.I0(rd_ptr[3]), .I1(rd_ptr[0]), .I2(rd_ptr[1]), .O(nxt_rd_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair996" *) LUT4 #( .INIT(16'hAA6A)) \rd_ptr_timing[2]_i_1 (.I0(rd_ptr[2]), .I1(rd_ptr[0]), .I2(rd_ptr[1]), .I3(rd_ptr[3]), .O(nxt_rd_ptr[2])); LUT2 #( .INIT(4'h1)) \rd_ptr_timing[3]_i_1 (.I0(\my_empty_reg_n_0_[7] ), .I1(ofifo_rst_reg), .O(\rd_ptr_timing[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair996" *) LUT4 #( .INIT(16'h4000)) \rd_ptr_timing[3]_i_2 (.I0(rd_ptr[3]), .I1(rd_ptr[1]), .I2(rd_ptr[0]), .I3(rd_ptr[2]), .O(nxt_rd_ptr[3])); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[0] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[0]), .Q(rd_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[1] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[1]), .Q(rd_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[2] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[2]), .Q(rd_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \rd_ptr_timing_reg[3] (.C(CLK), .CE(\rd_ptr_timing[3]_i_1_n_0 ), .D(nxt_rd_ptr[3]), .Q(rd_ptr_timing[3]), .R(SR)); LUT4 #( .INIT(16'h082A)) wr_ptr0 (.I0(mux_cmd_wren), .I1(ofifo_rst_reg), .I2(\my_full_reg_n_0_[4] ), .I3(\my_empty_reg_n_0_[7] ), .O(wr_ptr0__0)); (* SOFT_HLUTNM = "soft_lutpair1000" *) LUT2 #( .INIT(4'h9)) \wr_ptr[0]_i_1 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .O(nxt_wr_ptr[0])); (* SOFT_HLUTNM = "soft_lutpair1000" *) LUT3 #( .INIT(8'hB4)) \wr_ptr[1]_i_1 (.I0(wr_ptr[3]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .O(nxt_wr_ptr[1])); (* SOFT_HLUTNM = "soft_lutpair995" *) LUT4 #( .INIT(16'hAA6A)) \wr_ptr[2]_i_1 (.I0(wr_ptr[2]), .I1(wr_ptr[0]), .I2(wr_ptr[1]), .I3(wr_ptr[3]), .O(nxt_wr_ptr[2])); (* SOFT_HLUTNM = "soft_lutpair995" *) LUT4 #( .INIT(16'h4000)) \wr_ptr[3]_i_1 (.I0(wr_ptr[3]), .I1(wr_ptr[1]), .I2(wr_ptr[0]), .I3(wr_ptr[2]), .O(nxt_wr_ptr[3])); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr[0]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr[1]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr[2]), .R(SR)); (* syn_maxfan = "10" *) FDRE \wr_ptr_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr[3]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[0] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[0]), .Q(wr_ptr_timing[0]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[1] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[1]), .Q(wr_ptr_timing[1]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[2] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[2]), .Q(wr_ptr_timing[2]), .R(SR)); (* KEEP = "yes" *) (* MAX_FANOUT = "50" *) (* syn_maxfan = "10" *) FDRE \wr_ptr_timing_reg[3] (.C(CLK), .CE(wr_ptr0__0), .D(nxt_wr_ptr[3]), .Q(wr_ptr_timing[3]), .R(SR)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_4lanes (\pi_dqs_found_lanes_r1_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , mem_dqs_out, mem_dqs_ts, mem_dq_out, mem_dq_ts, idelay_ld_rst, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , idelay_ld_rst_0, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , idelay_ld_rst_1, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , idelay_ld_rst_2, _phy_ctl_full_p__0, rst_primitives_reg_0, rst_primitives, mcGo_reg_0, rclk_delay_11, \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[228] , \my_empty_reg[1] , \my_empty_reg[1]_0 , \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 , rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , phy_rddata_en, mux_rd_valid_r_reg, rst_sync_r1_reg, \data_bytes_r_reg[63] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252]_0 , \not_strict_mode.app_rd_data_reg[236]_0 , \not_strict_mode.app_rd_data_reg[244]_0 , \not_strict_mode.app_rd_data_reg[228]_0 , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \read_fifo.tail_r_reg[0] , \gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \not_strict_mode.app_rd_data_reg[255]_0 , pi_phase_locked_all_r1_reg, \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] , \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] , \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] , \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] , \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] , \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] , \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] , \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] , \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] , \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] , \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] , \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] , \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] , \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] , \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] , \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] , \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] , \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] , \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] , \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] , \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] , \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] , \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] , \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] , \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[31]_1 , \my_empty_reg[7] , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[23]_1 , \my_empty_reg[7]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[15]_1 , \my_empty_reg[7]_1 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[7]_1 , \my_empty_reg[7]_2 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \po_rdval_cnt_reg[8] , \pi_rdval_cnt_reg[5] , phy_if_empty_r_reg, p_0_out, \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] , \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] , \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] , \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] , \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] , \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] , \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] , \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] , \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] , \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] , \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] , \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] , \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0] , pi_en_stg2_f_reg, pi_stg2_f_incdec_reg, freq_refclk, mem_refclk, mem_dqs_in, \gen_byte_sel_div1.calib_in_common_reg_0 , sync_pulse, CLK, COUNTERLOADVAL, \gen_byte_sel_div1.calib_in_common_reg_1 , ck_po_stg2_f_en_reg, ck_po_stg2_f_indec_reg, delay_done_r4_reg, \write_buffer.wr_buf_out_data_reg[255] , \write_buffer.wr_buf_out_data_reg[254] , \write_buffer.wr_buf_out_data_reg[253] , \write_buffer.wr_buf_out_data_reg[252] , \write_buffer.wr_buf_out_data_reg[251] , \write_buffer.wr_buf_out_data_reg[250] , \write_buffer.wr_buf_out_data_reg[249] , \write_buffer.wr_buf_out_data_reg[248] , \gen_byte_sel_div1.calib_in_common_reg_2 , mem_dq_in, idelay_inc, LD0, CLKB0, phy_if_reset, \gen_byte_sel_div1.calib_in_common_reg_3 , \calib_sel_reg[0]_0 , pi_en_stg2_f_reg_0, pi_stg2_f_incdec_reg_0, \gen_byte_sel_div1.calib_in_common_reg_4 , \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.calib_in_common_reg_5 , ck_po_stg2_f_en_reg_0, ck_po_stg2_f_indec_reg_0, delay_done_r4_reg_0, \write_buffer.wr_buf_out_data_reg[247] , \write_buffer.wr_buf_out_data_reg[246] , \write_buffer.wr_buf_out_data_reg[245] , \write_buffer.wr_buf_out_data_reg[244] , \write_buffer.wr_buf_out_data_reg[243] , \write_buffer.wr_buf_out_data_reg[242] , \write_buffer.wr_buf_out_data_reg[241] , \write_buffer.wr_buf_out_data_reg[240] , \gen_byte_sel_div1.calib_in_common_reg_6 , LD0_3, CLKB0_7, \gen_byte_sel_div1.calib_in_common_reg_7 , \calib_sel_reg[1] , pi_en_stg2_f_reg_1, pi_stg2_f_incdec_reg_1, \gen_byte_sel_div1.calib_in_common_reg_8 , \calib_zero_inputs_reg[0]_0 , \gen_byte_sel_div1.calib_in_common_reg_9 , ck_po_stg2_f_en_reg_1, ck_po_stg2_f_indec_reg_1, delay_done_r4_reg_1, \write_buffer.wr_buf_out_data_reg[239] , \write_buffer.wr_buf_out_data_reg[238] , \write_buffer.wr_buf_out_data_reg[237] , \write_buffer.wr_buf_out_data_reg[236] , \write_buffer.wr_buf_out_data_reg[235] , \write_buffer.wr_buf_out_data_reg[234] , \write_buffer.wr_buf_out_data_reg[233] , \write_buffer.wr_buf_out_data_reg[232] , \gen_byte_sel_div1.calib_in_common_reg_10 , LD0_4, CLKB0_8, \gen_byte_sel_div1.calib_in_common_reg_11 , \calib_sel_reg[0]_1 , pi_en_stg2_f_reg_2, pi_stg2_f_incdec_reg_2, \gen_byte_sel_div1.calib_in_common_reg_12 , \calib_zero_inputs_reg[0]_1 , \gen_byte_sel_div1.calib_in_common_reg_13 , ck_po_stg2_f_en_reg_2, ck_po_stg2_f_indec_reg_2, delay_done_r4_reg_2, \write_buffer.wr_buf_out_data_reg[231] , \write_buffer.wr_buf_out_data_reg[230] , \write_buffer.wr_buf_out_data_reg[229] , \write_buffer.wr_buf_out_data_reg[228] , \write_buffer.wr_buf_out_data_reg[227] , \write_buffer.wr_buf_out_data_reg[226] , \write_buffer.wr_buf_out_data_reg[225] , \write_buffer.wr_buf_out_data_reg[224] , \gen_byte_sel_div1.calib_in_common_reg_14 , LD0_5, CLKB0_9, phy_ctl_mstr_empty, phy_ctl_wr_i2, pll_locked, phy_read_calib, in0, phy_write_calib, Q, RST0, phy_ctl_wr_i2_reg, \rclk_delay_reg[11]_0 , rstdiv0_sync_r1_reg_rep__9, rst_primitives_reg_1, mux_wrdata_en, mcGo_w__0, \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, init_calib_complete_reg_rep, \write_buffer.wr_buf_out_data_reg[287] , prbs_rdlvl_start_reg, out, ref_dll_lock_w, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, \byte_r_reg[0] , \byte_r_reg[1] , tail_r, \rd_mux_sel_r_reg[1] , \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , A, mux_wrdata, mux_wrdata_mask, E, \fine_delay_mod_reg[23] , \gen_byte_sel_div1.calib_in_common_reg_15 , \calib_sel_reg[0]_2 , \gen_byte_sel_div1.calib_in_common_reg_16 , \calib_sel_reg[1]_0 , \gen_byte_sel_div1.calib_in_common_reg_17 , \calib_sel_reg[0]_3 , \calib_sel_reg[1]_1 , \po_stg2_wrcal_cnt_reg[1] ); output [3:0]\pi_dqs_found_lanes_r1_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output [3:0]mem_dqs_out; output [3:0]mem_dqs_ts; output [35:0]mem_dq_out; output [35:0]mem_dq_ts; output idelay_ld_rst; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output idelay_ld_rst_0; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output idelay_ld_rst_1; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output idelay_ld_rst_2; output [0:0]_phy_ctl_full_p__0; output rst_primitives_reg_0; output rst_primitives; output mcGo_reg_0; output rclk_delay_11; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[228] ; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output phy_rddata_en; output mux_rd_valid_r_reg; output rst_sync_r1_reg; output [63:0]\data_bytes_r_reg[63] ; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252]_0 ; output \not_strict_mode.app_rd_data_reg[236]_0 ; output \not_strict_mode.app_rd_data_reg[244]_0 ; output \not_strict_mode.app_rd_data_reg[228]_0 ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \read_fifo.tail_r_reg[0] ; output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output pi_phase_locked_all_r1_reg; output \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; output \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; output \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; output \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; output \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; output \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; output \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; output \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; output \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; output \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; output \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; output \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; output \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; output \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; output \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; output \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; output [63:0]\my_empty_reg[7] ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; output [63:0]\my_empty_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; output [63:0]\my_empty_reg[7]_1 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; output [63:0]\my_empty_reg[7]_2 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [8:0]\po_rdval_cnt_reg[8] ; output [5:0]\pi_rdval_cnt_reg[5] ; output phy_if_empty_r_reg; output p_0_out; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; output \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; output \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; output \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; output \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0] ; input pi_en_stg2_f_reg; input pi_stg2_f_incdec_reg; input freq_refclk; input mem_refclk; input [3:0]mem_dqs_in; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input sync_pulse; input CLK; input [5:0]COUNTERLOADVAL; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input ck_po_stg2_f_en_reg; input ck_po_stg2_f_indec_reg; input delay_done_r4_reg; input [7:0]\write_buffer.wr_buf_out_data_reg[255] ; input [7:0]\write_buffer.wr_buf_out_data_reg[254] ; input [7:0]\write_buffer.wr_buf_out_data_reg[253] ; input [7:0]\write_buffer.wr_buf_out_data_reg[252] ; input [7:0]\write_buffer.wr_buf_out_data_reg[251] ; input [7:0]\write_buffer.wr_buf_out_data_reg[250] ; input [7:0]\write_buffer.wr_buf_out_data_reg[249] ; input [7:0]\write_buffer.wr_buf_out_data_reg[248] ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input [31:0]mem_dq_in; input idelay_inc; input LD0; input CLKB0; input phy_if_reset; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input \calib_sel_reg[0]_0 ; input pi_en_stg2_f_reg_0; input pi_stg2_f_incdec_reg_0; input \gen_byte_sel_div1.calib_in_common_reg_4 ; input [5:0]\calib_zero_inputs_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg_5 ; input ck_po_stg2_f_en_reg_0; input ck_po_stg2_f_indec_reg_0; input delay_done_r4_reg_0; input [7:0]\write_buffer.wr_buf_out_data_reg[247] ; input [7:0]\write_buffer.wr_buf_out_data_reg[246] ; input [7:0]\write_buffer.wr_buf_out_data_reg[245] ; input [7:0]\write_buffer.wr_buf_out_data_reg[244] ; input [7:0]\write_buffer.wr_buf_out_data_reg[243] ; input [7:0]\write_buffer.wr_buf_out_data_reg[242] ; input [7:0]\write_buffer.wr_buf_out_data_reg[241] ; input [7:0]\write_buffer.wr_buf_out_data_reg[240] ; input \gen_byte_sel_div1.calib_in_common_reg_6 ; input LD0_3; input CLKB0_7; input \gen_byte_sel_div1.calib_in_common_reg_7 ; input \calib_sel_reg[1] ; input pi_en_stg2_f_reg_1; input pi_stg2_f_incdec_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_8 ; input [5:0]\calib_zero_inputs_reg[0]_0 ; input \gen_byte_sel_div1.calib_in_common_reg_9 ; input ck_po_stg2_f_en_reg_1; input ck_po_stg2_f_indec_reg_1; input delay_done_r4_reg_1; input [7:0]\write_buffer.wr_buf_out_data_reg[239] ; input [7:0]\write_buffer.wr_buf_out_data_reg[238] ; input [7:0]\write_buffer.wr_buf_out_data_reg[237] ; input [7:0]\write_buffer.wr_buf_out_data_reg[236] ; input [7:0]\write_buffer.wr_buf_out_data_reg[235] ; input [7:0]\write_buffer.wr_buf_out_data_reg[234] ; input [7:0]\write_buffer.wr_buf_out_data_reg[233] ; input [7:0]\write_buffer.wr_buf_out_data_reg[232] ; input \gen_byte_sel_div1.calib_in_common_reg_10 ; input LD0_4; input CLKB0_8; input \gen_byte_sel_div1.calib_in_common_reg_11 ; input \calib_sel_reg[0]_1 ; input pi_en_stg2_f_reg_2; input pi_stg2_f_incdec_reg_2; input \gen_byte_sel_div1.calib_in_common_reg_12 ; input [5:0]\calib_zero_inputs_reg[0]_1 ; input \gen_byte_sel_div1.calib_in_common_reg_13 ; input ck_po_stg2_f_en_reg_2; input ck_po_stg2_f_indec_reg_2; input delay_done_r4_reg_2; input [7:0]\write_buffer.wr_buf_out_data_reg[231] ; input [7:0]\write_buffer.wr_buf_out_data_reg[230] ; input [7:0]\write_buffer.wr_buf_out_data_reg[229] ; input [7:0]\write_buffer.wr_buf_out_data_reg[228] ; input [7:0]\write_buffer.wr_buf_out_data_reg[227] ; input [7:0]\write_buffer.wr_buf_out_data_reg[226] ; input [7:0]\write_buffer.wr_buf_out_data_reg[225] ; input [7:0]\write_buffer.wr_buf_out_data_reg[224] ; input \gen_byte_sel_div1.calib_in_common_reg_14 ; input LD0_5; input CLKB0_9; input phy_ctl_mstr_empty; input phy_ctl_wr_i2; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input [10:0]Q; input RST0; input phy_ctl_wr_i2_reg; input \rclk_delay_reg[11]_0 ; input rstdiv0_sync_r1_reg_rep__9; input rst_primitives_reg_1; input mux_wrdata_en; input [0:0]mcGo_w__0; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input init_calib_complete_reg_rep; input [31:0]\write_buffer.wr_buf_out_data_reg[287] ; input prbs_rdlvl_start_reg; input out; input [0:0]ref_dll_lock_w; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input \byte_r_reg[0] ; input \byte_r_reg[1] ; input [0:0]tail_r; input [1:0]\rd_mux_sel_r_reg[1] ; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input [1:0]A; input [255:0]mux_wrdata; input [31:0]mux_wrdata_mask; input [0:0]E; input [7:0]\fine_delay_mod_reg[23] ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_15 ; input [7:0]\calib_sel_reg[0]_2 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_16 ; input [7:0]\calib_sel_reg[1]_0 ; input [0:0]\gen_byte_sel_div1.calib_in_common_reg_17 ; input [7:0]\calib_sel_reg[0]_3 ; input [1:0]\calib_sel_reg[1]_1 ; input [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire [1:0]A; wire A_byte_rd_en; wire [5:0]A_pi_counter_read_val; (* async_reg = "true" *) wire A_pi_rst_div2; wire [8:0]A_po_counter_read_val; wire A_rst_primitives; wire B_byte_rd_en; wire [5:0]B_pi_counter_read_val; (* async_reg = "true" *) wire B_pi_rst_div2; wire [8:0]B_po_counter_read_val; wire B_rclk; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [5:0]COUNTERLOADVAL; wire C_byte_rd_en; wire [5:0]C_pi_counter_read_val; (* async_reg = "true" *) wire C_pi_rst_div2; wire [8:0]C_po_counter_read_val; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire D_byte_rd_en; (* async_reg = "true" *) wire D_pi_rst_div2; wire [0:0]E; wire LD0; wire LD0_3; wire LD0_4; wire LD0_5; wire [10:0]Q; wire RST0; wire [0:0]_phy_ctl_full_p__0; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire [7:0]\calib_sel_reg[0]_2 ; wire [7:0]\calib_sel_reg[0]_3 ; wire \calib_sel_reg[1] ; wire [7:0]\calib_sel_reg[1]_0 ; wire [1:0]\calib_sel_reg[1]_1 ; wire [5:0]\calib_zero_inputs_reg[0] ; wire [5:0]\calib_zero_inputs_reg[0]_0 ; wire [5:0]\calib_zero_inputs_reg[0]_1 ; wire ck_po_stg2_f_en_reg; wire ck_po_stg2_f_en_reg_0; wire ck_po_stg2_f_en_reg_1; wire ck_po_stg2_f_en_reg_2; wire ck_po_stg2_f_indec_reg; wire ck_po_stg2_f_indec_reg_0; wire ck_po_stg2_f_indec_reg_1; wire ck_po_stg2_f_indec_reg_2; wire [63:0]\data_bytes_r_reg[63] ; wire \ddr_byte_lane_A.ddr_byte_lane_A_n_2 ; wire \ddr_byte_lane_C.ddr_byte_lane_C_n_2 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_154 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_2 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_222 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_223 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_224 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_225 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_226 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_227 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_228 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_229 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_230 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_231 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_232 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_233 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_234 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_235 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_236 ; wire delay_done_r4_reg; wire delay_done_r4_reg_0; wire delay_done_r4_reg_1; wire delay_done_r4_reg_2; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ; wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 ; wire [7:0]\fine_delay_mod_reg[23] ; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_10 ; wire \gen_byte_sel_div1.calib_in_common_reg_11 ; wire \gen_byte_sel_div1.calib_in_common_reg_12 ; wire \gen_byte_sel_div1.calib_in_common_reg_13 ; wire \gen_byte_sel_div1.calib_in_common_reg_14 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_15 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_16 ; wire [0:0]\gen_byte_sel_div1.calib_in_common_reg_17 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.calib_in_common_reg_4 ; wire \gen_byte_sel_div1.calib_in_common_reg_5 ; wire \gen_byte_sel_div1.calib_in_common_reg_6 ; wire \gen_byte_sel_div1.calib_in_common_reg_7 ; wire \gen_byte_sel_div1.calib_in_common_reg_8 ; wire \gen_byte_sel_div1.calib_in_common_reg_9 ; wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ; wire idelay_inc; wire idelay_ld_rst; wire idelay_ld_rst_0; wire idelay_ld_rst_1; wire idelay_ld_rst_2; wire [3:3]if_empty_r; wire [3:3]if_empty_r_2; wire [3:3]if_empty_r_5; wire in0; wire init_calib_complete_reg_rep; wire \mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ; wire mcGo_reg_0; wire [0:0]mcGo_w; wire [0:0]mcGo_w__0; wire [31:0]mem_dq_in; wire [35:0]mem_dq_out; wire [35:0]mem_dq_ts; wire [3:0]mem_dqs_in; wire [3:0]mem_dqs_out; wire [3:0]mem_dqs_ts; wire mem_refclk; wire mmcm_locked; wire mux_rd_valid_r_reg; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire [63:0]\my_empty_reg[7] ; wire [63:0]\my_empty_reg[7]_0 ; wire [63:0]\my_empty_reg[7]_1 ; wire [63:0]\my_empty_reg[7]_2 ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[15]_1 ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[228]_0 ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[236]_0 ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[23]_1 ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[244]_0 ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[252]_0 ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[31]_1 ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [0:0]\not_strict_mode.app_rd_data_reg[7]_1 ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ; wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire out; wire p_0_out; wire [15:0]phaser_ctl_bus; wire phy_control_i_n_0; wire phy_control_i_n_1; wire phy_control_i_n_14; wire phy_control_i_n_15; wire phy_control_i_n_16; wire phy_control_i_n_17; wire phy_ctl_mstr_empty; wire phy_ctl_wr_i2; wire phy_ctl_wr_i2_reg; wire [1:0]phy_encalib; wire phy_if_empty_r_reg; wire phy_if_reset; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [3:0]\pi_dqs_found_lanes_r1_reg[3] ; wire pi_en_stg2_f_reg; wire pi_en_stg2_f_reg_0; wire pi_en_stg2_f_reg_1; wire pi_en_stg2_f_reg_2; wire pi_phase_locked_all_r1_reg; wire [5:0]\pi_rdval_cnt_reg[5] ; wire pi_stg2_f_incdec_reg; wire pi_stg2_f_incdec_reg_0; wire pi_stg2_f_incdec_reg_1; wire pi_stg2_f_incdec_reg_2; wire pll_locked; wire [8:0]\po_rdval_cnt_reg[8] ; wire [1:0]\po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_start_reg; wire ram_init_done_r; wire rclk_delay_11; wire \rclk_delay_reg[10]_srl11_n_0 ; wire \rclk_delay_reg[11]_0 ; wire rd_buf_we; wire [1:0]\rd_mux_sel_r_reg[1] ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire [0:0]ref_dll_lock_w; wire [0:0]ref_dll_lock_w__0; wire rst_primitives; wire rst_primitives_reg_0; wire rst_primitives_reg_1; wire rst_r4; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire [7:0]\write_buffer.wr_buf_out_data_reg[224] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[225] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[226] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[227] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[228] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[229] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[230] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[231] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[232] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[233] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[234] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[235] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[236] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[237] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[238] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[239] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[240] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[241] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[242] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[243] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[244] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[245] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[246] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[247] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[248] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[249] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[250] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[251] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[252] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[253] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[254] ; wire [7:0]\write_buffer.wr_buf_out_data_reg[255] ; wire [31:0]\write_buffer.wr_buf_out_data_reg[287] ; FDRE #( .INIT(1'b0)) A_rst_primitives_reg (.C(CLK), .CE(1'b1), .D(rst_primitives), .Q(A_rst_primitives), .R(1'b0)); ddr3_if_mig_7series_v4_0_ddr_byte_lane \ddr_byte_lane_A.ddr_byte_lane_A (.A(A), .A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .B_byte_rd_en(B_byte_rd_en), .CLK(CLK), .CLKB0(CLKB0), .COUNTERLOADVAL(COUNTERLOADVAL), .COUNTERREADVAL(A_pi_counter_read_val), .D_byte_rd_en(D_byte_rd_en), .E(E), .LD0(LD0), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ), .\byte_r_reg[0] (\byte_r_reg[0] ), .\byte_r_reg[1] (\byte_r_reg[1] ), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg), .\data_bytes_r_reg[63] (\data_bytes_r_reg[63] ), .delay_done_r4_reg(delay_done_r4_reg), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\not_strict_mode.app_rd_data_reg[79] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\not_strict_mode.app_rd_data_reg[87] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 (\not_strict_mode.app_rd_data_reg[71] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\not_strict_mode.app_rd_data_reg[111] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\not_strict_mode.app_rd_data_reg[119] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 (\not_strict_mode.app_rd_data_reg[103] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\not_strict_mode.app_rd_data_reg[143] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\not_strict_mode.app_rd_data_reg[151] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 (\not_strict_mode.app_rd_data_reg[135] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\not_strict_mode.app_rd_data_reg[175] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\not_strict_mode.app_rd_data_reg[183] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 (\not_strict_mode.app_rd_data_reg[167] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\not_strict_mode.app_rd_data_reg[207] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\not_strict_mode.app_rd_data_reg[215] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 (\not_strict_mode.app_rd_data_reg[199] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\not_strict_mode.app_rd_data_reg[239] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\not_strict_mode.app_rd_data_reg[247] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 (\not_strict_mode.app_rd_data_reg[231] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\not_strict_mode.app_rd_data_reg[14] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\not_strict_mode.app_rd_data_reg[22] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\not_strict_mode.app_rd_data_reg[6] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\not_strict_mode.app_rd_data_reg[46] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\not_strict_mode.app_rd_data_reg[54] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\not_strict_mode.app_rd_data_reg[38] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\not_strict_mode.app_rd_data_reg[78] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\not_strict_mode.app_rd_data_reg[86] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\not_strict_mode.app_rd_data_reg[70] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\not_strict_mode.app_rd_data_reg[110] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\not_strict_mode.app_rd_data_reg[118] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\not_strict_mode.app_rd_data_reg[102] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\not_strict_mode.app_rd_data_reg[142] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\not_strict_mode.app_rd_data_reg[150] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\not_strict_mode.app_rd_data_reg[134] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\not_strict_mode.app_rd_data_reg[174] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\not_strict_mode.app_rd_data_reg[182] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\not_strict_mode.app_rd_data_reg[166] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\not_strict_mode.app_rd_data_reg[206] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\not_strict_mode.app_rd_data_reg[214] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\not_strict_mode.app_rd_data_reg[198] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\not_strict_mode.app_rd_data_reg[238] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\not_strict_mode.app_rd_data_reg[246] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\not_strict_mode.app_rd_data_reg[230] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\not_strict_mode.app_rd_data_reg[13] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\not_strict_mode.app_rd_data_reg[21] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\not_strict_mode.app_rd_data_reg[5] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\not_strict_mode.app_rd_data_reg[45] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\not_strict_mode.app_rd_data_reg[53] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\not_strict_mode.app_rd_data_reg[37] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\not_strict_mode.app_rd_data_reg[77] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\not_strict_mode.app_rd_data_reg[85] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\not_strict_mode.app_rd_data_reg[69] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\not_strict_mode.app_rd_data_reg[109] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\not_strict_mode.app_rd_data_reg[117] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\not_strict_mode.app_rd_data_reg[101] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\not_strict_mode.app_rd_data_reg[141] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\not_strict_mode.app_rd_data_reg[149] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\not_strict_mode.app_rd_data_reg[133] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\not_strict_mode.app_rd_data_reg[173] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\not_strict_mode.app_rd_data_reg[181] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\not_strict_mode.app_rd_data_reg[165] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\not_strict_mode.app_rd_data_reg[205] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\not_strict_mode.app_rd_data_reg[213] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\not_strict_mode.app_rd_data_reg[197] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\not_strict_mode.app_rd_data_reg[237] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\not_strict_mode.app_rd_data_reg[245] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\not_strict_mode.app_rd_data_reg[229] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\not_strict_mode.app_rd_data_reg[12] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\not_strict_mode.app_rd_data_reg[20] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\not_strict_mode.app_rd_data_reg[4] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\not_strict_mode.app_rd_data_reg[44] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\not_strict_mode.app_rd_data_reg[52] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\not_strict_mode.app_rd_data_reg[36] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\not_strict_mode.app_rd_data_reg[76] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\not_strict_mode.app_rd_data_reg[84] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\not_strict_mode.app_rd_data_reg[68] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\not_strict_mode.app_rd_data_reg[108] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\not_strict_mode.app_rd_data_reg[116] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\not_strict_mode.app_rd_data_reg[100] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\not_strict_mode.app_rd_data_reg[140] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\not_strict_mode.app_rd_data_reg[148] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\not_strict_mode.app_rd_data_reg[132] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\not_strict_mode.app_rd_data_reg[172] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\not_strict_mode.app_rd_data_reg[180] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\not_strict_mode.app_rd_data_reg[164] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\not_strict_mode.app_rd_data_reg[204] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\not_strict_mode.app_rd_data_reg[212] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\not_strict_mode.app_rd_data_reg[196] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\not_strict_mode.app_rd_data_reg[236]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\not_strict_mode.app_rd_data_reg[244]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\not_strict_mode.app_rd_data_reg[228]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\not_strict_mode.app_rd_data_reg[11] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\not_strict_mode.app_rd_data_reg[19] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\not_strict_mode.app_rd_data_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\not_strict_mode.app_rd_data_reg[43] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\not_strict_mode.app_rd_data_reg[51] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\not_strict_mode.app_rd_data_reg[35] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\not_strict_mode.app_rd_data_reg[75] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\not_strict_mode.app_rd_data_reg[83] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\not_strict_mode.app_rd_data_reg[67] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\not_strict_mode.app_rd_data_reg[107] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\not_strict_mode.app_rd_data_reg[115] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\not_strict_mode.app_rd_data_reg[99] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\not_strict_mode.app_rd_data_reg[139] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\not_strict_mode.app_rd_data_reg[147] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\not_strict_mode.app_rd_data_reg[131] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\not_strict_mode.app_rd_data_reg[171] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\not_strict_mode.app_rd_data_reg[179] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\not_strict_mode.app_rd_data_reg[163] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\not_strict_mode.app_rd_data_reg[203] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\not_strict_mode.app_rd_data_reg[211] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\not_strict_mode.app_rd_data_reg[195] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\not_strict_mode.app_rd_data_reg[235] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\not_strict_mode.app_rd_data_reg[243] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\not_strict_mode.app_rd_data_reg[227] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\not_strict_mode.app_rd_data_reg[10] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\not_strict_mode.app_rd_data_reg[18] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\not_strict_mode.app_rd_data_reg[2] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\not_strict_mode.app_rd_data_reg[42] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\not_strict_mode.app_rd_data_reg[50] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\not_strict_mode.app_rd_data_reg[34] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\not_strict_mode.app_rd_data_reg[74] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\not_strict_mode.app_rd_data_reg[82] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\not_strict_mode.app_rd_data_reg[66] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\not_strict_mode.app_rd_data_reg[106] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\not_strict_mode.app_rd_data_reg[114] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\not_strict_mode.app_rd_data_reg[98] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\not_strict_mode.app_rd_data_reg[138] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\not_strict_mode.app_rd_data_reg[146] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\not_strict_mode.app_rd_data_reg[130] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\not_strict_mode.app_rd_data_reg[170] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\not_strict_mode.app_rd_data_reg[178] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\not_strict_mode.app_rd_data_reg[162] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\not_strict_mode.app_rd_data_reg[202] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\not_strict_mode.app_rd_data_reg[210] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\not_strict_mode.app_rd_data_reg[194] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\not_strict_mode.app_rd_data_reg[234] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\not_strict_mode.app_rd_data_reg[242] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\not_strict_mode.app_rd_data_reg[226] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\not_strict_mode.app_rd_data_reg[9] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\not_strict_mode.app_rd_data_reg[17] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\not_strict_mode.app_rd_data_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\not_strict_mode.app_rd_data_reg[41] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\not_strict_mode.app_rd_data_reg[49] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\not_strict_mode.app_rd_data_reg[33] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\not_strict_mode.app_rd_data_reg[73] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\not_strict_mode.app_rd_data_reg[81] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\not_strict_mode.app_rd_data_reg[65] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\not_strict_mode.app_rd_data_reg[105] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\not_strict_mode.app_rd_data_reg[113] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\not_strict_mode.app_rd_data_reg[97] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\not_strict_mode.app_rd_data_reg[137] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\not_strict_mode.app_rd_data_reg[145] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\not_strict_mode.app_rd_data_reg[129] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\not_strict_mode.app_rd_data_reg[169] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\not_strict_mode.app_rd_data_reg[177] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\not_strict_mode.app_rd_data_reg[161] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\not_strict_mode.app_rd_data_reg[201] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\not_strict_mode.app_rd_data_reg[209] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\not_strict_mode.app_rd_data_reg[193] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\not_strict_mode.app_rd_data_reg[233] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\not_strict_mode.app_rd_data_reg[241] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\not_strict_mode.app_rd_data_reg[225] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\not_strict_mode.app_rd_data_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\not_strict_mode.app_rd_data_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\not_strict_mode.app_rd_data_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\not_strict_mode.app_rd_data_reg[40] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\not_strict_mode.app_rd_data_reg[48] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\not_strict_mode.app_rd_data_reg[32] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\not_strict_mode.app_rd_data_reg[72] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\not_strict_mode.app_rd_data_reg[80] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\not_strict_mode.app_rd_data_reg[64] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\not_strict_mode.app_rd_data_reg[104] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\not_strict_mode.app_rd_data_reg[112] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\not_strict_mode.app_rd_data_reg[96] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\not_strict_mode.app_rd_data_reg[136] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\not_strict_mode.app_rd_data_reg[144] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\not_strict_mode.app_rd_data_reg[128] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\not_strict_mode.app_rd_data_reg[168] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\not_strict_mode.app_rd_data_reg[176] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\not_strict_mode.app_rd_data_reg[160] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\not_strict_mode.app_rd_data_reg[200] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\not_strict_mode.app_rd_data_reg[208] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\not_strict_mode.app_rd_data_reg[192] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\not_strict_mode.app_rd_data_reg[232] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\not_strict_mode.app_rd_data_reg[240] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\not_strict_mode.app_rd_data_reg[224] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\not_strict_mode.app_rd_data_reg[15] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\not_strict_mode.app_rd_data_reg[23] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\not_strict_mode.app_rd_data_reg[7] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\not_strict_mode.app_rd_data_reg[47] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\not_strict_mode.app_rd_data_reg[55] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 (\not_strict_mode.app_rd_data_reg[39] ), .\fine_delay_mod_reg[23] (\fine_delay_mod_reg[23] ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_2 ), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ), .idelay_inc(idelay_inc), .idelay_ld_rst(idelay_ld_rst), .if_empty_r(if_empty_r), .if_empty_r_0(if_empty_r_5), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[7:0]), .mem_dq_out(mem_dq_out[8:0]), .mem_dq_ts(mem_dq_ts[8:0]), .mem_dqs_in(mem_dqs_in[0]), .mem_dqs_out(mem_dqs_out[0]), .mem_dqs_ts(mem_dqs_ts[0]), .mem_refclk(mem_refclk), .mux_wrdata_en(mux_wrdata_en), .my_empty(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3]), .\my_empty_reg[1] (\my_empty_reg[1] ), .\my_empty_reg[7] (\my_empty_reg[7] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[252]_0 (\not_strict_mode.app_rd_data_reg[252]_0 ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 ({\not_strict_mode.app_rd_data_reg[255]_0 [255:248],\not_strict_mode.app_rd_data_reg[255]_0 [223:216],\not_strict_mode.app_rd_data_reg[255]_0 [191:184],\not_strict_mode.app_rd_data_reg[255]_0 [159:152],\not_strict_mode.app_rd_data_reg[255]_0 [127:120],\not_strict_mode.app_rd_data_reg[255]_0 [95:88],\not_strict_mode.app_rd_data_reg[255]_0 [63:56],\not_strict_mode.app_rd_data_reg[255]_0 [31:24]}), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31]_0 ), .\not_strict_mode.app_rd_data_reg[31]_1 (\not_strict_mode.app_rd_data_reg[31]_1 ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ), .p_0_out(p_0_out), .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}), .phy_dout({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}), .phy_if_reset(phy_if_reset), .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[3] [0]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg), .pi_phase_locked_all_r1_reg(\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg), .\po_counter_read_val_reg[8] (A_po_counter_read_val), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6]_0 ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .\wr_ptr_reg[1] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\write_buffer.wr_buf_out_data_reg[248] (\write_buffer.wr_buf_out_data_reg[248] ), .\write_buffer.wr_buf_out_data_reg[249] (\write_buffer.wr_buf_out_data_reg[249] ), .\write_buffer.wr_buf_out_data_reg[250] (\write_buffer.wr_buf_out_data_reg[250] ), .\write_buffer.wr_buf_out_data_reg[251] (\write_buffer.wr_buf_out_data_reg[251] ), .\write_buffer.wr_buf_out_data_reg[252] (\write_buffer.wr_buf_out_data_reg[252] ), .\write_buffer.wr_buf_out_data_reg[253] (\write_buffer.wr_buf_out_data_reg[253] ), .\write_buffer.wr_buf_out_data_reg[254] (\write_buffer.wr_buf_out_data_reg[254] ), .\write_buffer.wr_buf_out_data_reg[255] (\write_buffer.wr_buf_out_data_reg[255] ), .\write_buffer.wr_buf_out_data_reg[287] ({\write_buffer.wr_buf_out_data_reg[287] [31],\write_buffer.wr_buf_out_data_reg[287] [27],\write_buffer.wr_buf_out_data_reg[287] [23],\write_buffer.wr_buf_out_data_reg[287] [19],\write_buffer.wr_buf_out_data_reg[287] [15],\write_buffer.wr_buf_out_data_reg[287] [11],\write_buffer.wr_buf_out_data_reg[287] [7],\write_buffer.wr_buf_out_data_reg[287] [3]})); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized0 \ddr_byte_lane_B.ddr_byte_lane_B (.A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ), .A_rst_primitives_reg_0(\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ), .A_rst_primitives_reg_1(\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ), .B_byte_rd_en(B_byte_rd_en), .B_rclk(B_rclk), .CLK(CLK), .CLKB0_7(CLKB0_7), .COUNTERREADVAL(B_pi_counter_read_val), .D_byte_rd_en(D_byte_rd_en), .LD0_3(LD0_3), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ), .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_2 ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_0), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_0), .delay_done_r4_reg(delay_done_r4_reg_0), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_3 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_4 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_5 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_6 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_15 ), .idelay_inc(idelay_inc), .idelay_ld_rst_0(idelay_ld_rst_0), .if_empty_r(if_empty_r_2), .if_empty_r_0(if_empty_r_5), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[15:8]), .mem_dq_out(mem_dq_out[17:9]), .mem_dq_ts(mem_dq_ts[17:9]), .mem_dqs_in(mem_dqs_in[1]), .mem_dqs_out(mem_dqs_out[1]), .mem_dqs_ts(mem_dqs_ts[1]), .mem_refclk(mem_refclk), .mux_rd_valid_r_reg(mux_rd_valid_r_reg), .mux_wrdata_en(mux_wrdata_en), .my_empty({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}), .\my_empty_reg[1] (\my_empty_reg[1]_0 ), .\my_empty_reg[4] (\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ), .\my_empty_reg[7] (\my_empty_reg[7]_0 ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[22] (\not_strict_mode.app_rd_data_reg[22] ), .\not_strict_mode.app_rd_data_reg[23] (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23]_0 ), .\not_strict_mode.app_rd_data_reg[23]_1 (\not_strict_mode.app_rd_data_reg[23]_1 ), .\not_strict_mode.app_rd_data_reg[240] (\not_strict_mode.app_rd_data_reg[240] ), .\not_strict_mode.app_rd_data_reg[241] (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[244]_0 (\not_strict_mode.app_rd_data_reg[244]_0 ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] ({\not_strict_mode.app_rd_data_reg[255]_0 [247:240],\not_strict_mode.app_rd_data_reg[255]_0 [215:208],\not_strict_mode.app_rd_data_reg[255]_0 [183:176],\not_strict_mode.app_rd_data_reg[255]_0 [151:144],\not_strict_mode.app_rd_data_reg[255]_0 [119:112],\not_strict_mode.app_rd_data_reg[255]_0 [87:80],\not_strict_mode.app_rd_data_reg[255]_0 [55:48],\not_strict_mode.app_rd_data_reg[255]_0 [23:16]}), .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .out(out), .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}), .phy_dout({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}), .phy_if_empty_r_reg(phy_if_empty_r_reg), .phy_if_reset(phy_if_reset), .phy_rddata_en(phy_rddata_en), .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[3] [1]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg_0), .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_0), .\po_counter_read_val_reg[8] (B_po_counter_read_val), .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_ptr_timing_reg[1] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .tail_r(tail_r), .\write_buffer.wr_buf_out_data_reg[240] (\write_buffer.wr_buf_out_data_reg[240] ), .\write_buffer.wr_buf_out_data_reg[241] (\write_buffer.wr_buf_out_data_reg[241] ), .\write_buffer.wr_buf_out_data_reg[242] (\write_buffer.wr_buf_out_data_reg[242] ), .\write_buffer.wr_buf_out_data_reg[243] (\write_buffer.wr_buf_out_data_reg[243] ), .\write_buffer.wr_buf_out_data_reg[244] (\write_buffer.wr_buf_out_data_reg[244] ), .\write_buffer.wr_buf_out_data_reg[245] (\write_buffer.wr_buf_out_data_reg[245] ), .\write_buffer.wr_buf_out_data_reg[246] (\write_buffer.wr_buf_out_data_reg[246] ), .\write_buffer.wr_buf_out_data_reg[247] (\write_buffer.wr_buf_out_data_reg[247] ), .\write_buffer.wr_buf_out_data_reg[286] ({\write_buffer.wr_buf_out_data_reg[287] [30],\write_buffer.wr_buf_out_data_reg[287] [26],\write_buffer.wr_buf_out_data_reg[287] [22],\write_buffer.wr_buf_out_data_reg[287] [18],\write_buffer.wr_buf_out_data_reg[287] [14],\write_buffer.wr_buf_out_data_reg[287] [10],\write_buffer.wr_buf_out_data_reg[287] [6],\write_buffer.wr_buf_out_data_reg[287] [2]})); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized1 \ddr_byte_lane_C.ddr_byte_lane_C (.A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .CLK(CLK), .CLKB0_8(CLKB0_8), .COUNTERREADVAL(C_pi_counter_read_val), .C_byte_rd_en(C_byte_rd_en), .D_byte_rd_en(D_byte_rd_en), .LD0_4(LD0_4), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0]_0 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_1), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_1), .delay_done_r4_reg(delay_done_r4_reg_1), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_7 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_8 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_9 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_10 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_16 ), .idelay_inc(idelay_inc), .idelay_ld_rst_1(idelay_ld_rst_1), .if_empty_r(if_empty_r_5), .if_empty_r_0(if_empty_r_2), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[23:16]), .mem_dq_out(mem_dq_out[26:18]), .mem_dq_ts(mem_dq_ts[26:18]), .mem_dqs_in(mem_dqs_in[2]), .mem_dqs_out(mem_dqs_out[2]), .mem_dqs_ts(mem_dqs_ts[2]), .mem_refclk(mem_refclk), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1] (\my_empty_reg[1]_1 ), .\my_empty_reg[4] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ), .\my_empty_reg[7] (\my_empty_reg[7]_1 ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15]_0 ), .\not_strict_mode.app_rd_data_reg[15]_1 (\not_strict_mode.app_rd_data_reg[15]_1 ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ), .\not_strict_mode.app_rd_data_reg[233] (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[234] (\not_strict_mode.app_rd_data_reg[234] ), .\not_strict_mode.app_rd_data_reg[235] (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[236] (\not_strict_mode.app_rd_data_reg[236] ), .\not_strict_mode.app_rd_data_reg[236]_0 (\not_strict_mode.app_rd_data_reg[236]_0 ), .\not_strict_mode.app_rd_data_reg[237] (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[238] (\not_strict_mode.app_rd_data_reg[238] ), .\not_strict_mode.app_rd_data_reg[239] ({\not_strict_mode.app_rd_data_reg[255]_0 [239:232],\not_strict_mode.app_rd_data_reg[255]_0 [207:200],\not_strict_mode.app_rd_data_reg[255]_0 [175:168],\not_strict_mode.app_rd_data_reg[255]_0 [143:136],\not_strict_mode.app_rd_data_reg[255]_0 [111:104],\not_strict_mode.app_rd_data_reg[255]_0 [79:72],\not_strict_mode.app_rd_data_reg[255]_0 [47:40],\not_strict_mode.app_rd_data_reg[255]_0 [15:8]}), .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[72] (\not_strict_mode.app_rd_data_reg[72] ), .\not_strict_mode.app_rd_data_reg[73] (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[74] (\not_strict_mode.app_rd_data_reg[74] ), .\not_strict_mode.app_rd_data_reg[75] (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[76] (\not_strict_mode.app_rd_data_reg[76] ), .\not_strict_mode.app_rd_data_reg[77] (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[78] (\not_strict_mode.app_rd_data_reg[78] ), .\not_strict_mode.app_rd_data_reg[79] (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ), .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}), .phy_dout({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}), .phy_if_reset(phy_if_reset), .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[3] [2]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg_1), .pi_phase_locked_all_r1_reg(\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_1), .\po_counter_read_val_reg[8] (C_po_counter_read_val), .\rd_ptr_timing_reg[1] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6]_0 ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .\write_buffer.wr_buf_out_data_reg[232] (\write_buffer.wr_buf_out_data_reg[232] ), .\write_buffer.wr_buf_out_data_reg[233] (\write_buffer.wr_buf_out_data_reg[233] ), .\write_buffer.wr_buf_out_data_reg[234] (\write_buffer.wr_buf_out_data_reg[234] ), .\write_buffer.wr_buf_out_data_reg[235] (\write_buffer.wr_buf_out_data_reg[235] ), .\write_buffer.wr_buf_out_data_reg[236] (\write_buffer.wr_buf_out_data_reg[236] ), .\write_buffer.wr_buf_out_data_reg[237] (\write_buffer.wr_buf_out_data_reg[237] ), .\write_buffer.wr_buf_out_data_reg[238] (\write_buffer.wr_buf_out_data_reg[238] ), .\write_buffer.wr_buf_out_data_reg[239] (\write_buffer.wr_buf_out_data_reg[239] ), .\write_buffer.wr_buf_out_data_reg[285] ({\write_buffer.wr_buf_out_data_reg[287] [29],\write_buffer.wr_buf_out_data_reg[287] [25],\write_buffer.wr_buf_out_data_reg[287] [21],\write_buffer.wr_buf_out_data_reg[287] [17],\write_buffer.wr_buf_out_data_reg[287] [13],\write_buffer.wr_buf_out_data_reg[287] [9],\write_buffer.wr_buf_out_data_reg[287] [5],\write_buffer.wr_buf_out_data_reg[287] [1]})); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized2 \ddr_byte_lane_D.ddr_byte_lane_D (.A_byte_rd_en(A_byte_rd_en), .A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(C_pi_counter_read_val), .A_rst_primitives_reg_0(A_pi_counter_read_val), .A_rst_primitives_reg_1(B_po_counter_read_val), .A_rst_primitives_reg_2(C_po_counter_read_val), .A_rst_primitives_reg_3(A_po_counter_read_val), .CLK(CLK), .CLKB0_9(CLKB0_9), .COUNTERREADVAL(B_pi_counter_read_val), .C_byte_rd_en(C_byte_rd_en), .D({\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_227 }), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_byte_rd_en(D_byte_rd_en), .LD0_5(LD0_5), .PCENABLECALIB(phy_encalib), .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ), .\calib_sel_reg[0] (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_3 ), .\calib_sel_reg[1] (\calib_sel_reg[1]_1 ), .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0]_1 ), .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_2), .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_2), .delay_done_r4_reg(delay_done_r4_reg_2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_11 ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_12 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_13 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_14 ), .\gen_byte_sel_div1.calib_in_common_reg_3 (\gen_byte_sel_div1.calib_in_common_reg_17 ), .idelay_inc(idelay_inc), .idelay_ld_rst_2(idelay_ld_rst_2), .if_empty_r(if_empty_r), .if_empty_r_0(if_empty_r_2), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .mem_dq_in(mem_dq_in[31:24]), .mem_dq_out(mem_dq_out[35:27]), .mem_dq_ts(mem_dq_ts[35:27]), .mem_dqs_in(mem_dqs_in[3]), .mem_dqs_out(mem_dqs_out[3]), .mem_dqs_ts(mem_dqs_ts[3]), .mem_refclk(mem_refclk), .mux_rd_valid_r_reg(\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ), .mux_wrdata_en(mux_wrdata_en), .\my_empty_reg[1] (\my_empty_reg[1]_2 ), .\my_empty_reg[4] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\my_empty_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ), .\my_empty_reg[7] (\my_empty_reg[7]_2 ), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), .\not_strict_mode.app_rd_data_reg[227] (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[228] (\not_strict_mode.app_rd_data_reg[228] ), .\not_strict_mode.app_rd_data_reg[228]_0 (\not_strict_mode.app_rd_data_reg[228]_0 ), .\not_strict_mode.app_rd_data_reg[229] (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[230] (\not_strict_mode.app_rd_data_reg[230] ), .\not_strict_mode.app_rd_data_reg[231] ({\not_strict_mode.app_rd_data_reg[255]_0 [231:224],\not_strict_mode.app_rd_data_reg[255]_0 [199:192],\not_strict_mode.app_rd_data_reg[255]_0 [167:160],\not_strict_mode.app_rd_data_reg[255]_0 [135:128],\not_strict_mode.app_rd_data_reg[255]_0 [103:96],\not_strict_mode.app_rd_data_reg[255]_0 [71:64],\not_strict_mode.app_rd_data_reg[255]_0 [39:32],\not_strict_mode.app_rd_data_reg[255]_0 [7:0]}), .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), .\not_strict_mode.app_rd_data_reg[70] (\not_strict_mode.app_rd_data_reg[70] ), .\not_strict_mode.app_rd_data_reg[71] (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[7] (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7]_0 ), .\not_strict_mode.app_rd_data_reg[7]_1 (\not_strict_mode.app_rd_data_reg[7]_1 ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ), .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}), .phy_dout({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}), .phy_if_reset(phy_if_reset), .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] [3]), .pi_en_stg2_f_reg(pi_en_stg2_f_reg_2), .pi_phase_locked_all_r1_reg(\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ), .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_2), .\po_counter_read_val_reg[8] ({\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_236 }), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6]_0 ), .rst_r4(rst_r4), .sync_pulse(sync_pulse), .\write_buffer.wr_buf_out_data_reg[224] (\write_buffer.wr_buf_out_data_reg[224] ), .\write_buffer.wr_buf_out_data_reg[225] (\write_buffer.wr_buf_out_data_reg[225] ), .\write_buffer.wr_buf_out_data_reg[226] (\write_buffer.wr_buf_out_data_reg[226] ), .\write_buffer.wr_buf_out_data_reg[227] (\write_buffer.wr_buf_out_data_reg[227] ), .\write_buffer.wr_buf_out_data_reg[228] (\write_buffer.wr_buf_out_data_reg[228] ), .\write_buffer.wr_buf_out_data_reg[229] (\write_buffer.wr_buf_out_data_reg[229] ), .\write_buffer.wr_buf_out_data_reg[230] (\write_buffer.wr_buf_out_data_reg[230] ), .\write_buffer.wr_buf_out_data_reg[231] (\write_buffer.wr_buf_out_data_reg[231] ), .\write_buffer.wr_buf_out_data_reg[284] ({\write_buffer.wr_buf_out_data_reg[287] [28],\write_buffer.wr_buf_out_data_reg[287] [24],\write_buffer.wr_buf_out_data_reg[287] [20],\write_buffer.wr_buf_out_data_reg[287] [16],\write_buffer.wr_buf_out_data_reg[287] [12],\write_buffer.wr_buf_out_data_reg[287] [8],\write_buffer.wr_buf_out_data_reg[287] [4],\write_buffer.wr_buf_out_data_reg[287] [0]})); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(A_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(B_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(C_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(D_pi_rst_div2)); LUT2 #( .INIT(4'h8)) \mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_i_1 (.I0(mcGo_w), .I1(mcGo_w__0), .O(\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 )); FDRE #( .INIT(1'b0)) mcGo_reg (.C(CLK), .CE(1'b1), .D(mcGo_reg_0), .Q(mcGo_w), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) ofs_rdy_r_i_3 (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [2]), .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [4]), .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [3]), .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [2]), .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [4]), .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [3]), .O(ofs_rdy_r_reg_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) ofs_rdy_r_i_4 (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [2]), .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [4]), .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [3]), .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [2]), .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [4]), .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [3]), .O(ofs_rdy_r_reg)); (* BOX_TYPE = "PRIMITIVE" *) PHASER_REF #( .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0)) phaser_ref_i (.CLKIN(freq_refclk), .LOCKED(ref_dll_lock_w__0), .PWRDWN(1'b0), .RST(RST0)); (* BOX_TYPE = "PRIMITIVE" *) PHY_CONTROL #( .AO_TOGGLE(1), .BURST_MODE("TRUE"), .CLK_RATIO(4), .CMD_OFFSET(8), .CO_DURATION(1), .DATA_CTL_A_N("TRUE"), .DATA_CTL_B_N("TRUE"), .DATA_CTL_C_N("TRUE"), .DATA_CTL_D_N("TRUE"), .DISABLE_SEQ_MATCH("TRUE"), .DI_DURATION(1), .DO_DURATION(1), .EVENTS_DELAY(18), .FOUR_WINDOW_CLOCKS(63), .MULTI_REGION("TRUE"), .PHY_COUNT_ENABLE("FALSE"), .RD_CMD_OFFSET_0(10), .RD_CMD_OFFSET_1(10), .RD_CMD_OFFSET_2(10), .RD_CMD_OFFSET_3(10), .RD_DURATION_0(6), .RD_DURATION_1(6), .RD_DURATION_2(6), .RD_DURATION_3(6), .SYNC_MODE("FALSE"), .WR_CMD_OFFSET_0(8), .WR_CMD_OFFSET_1(8), .WR_CMD_OFFSET_2(8), .WR_CMD_OFFSET_3(8), .WR_DURATION_0(7), .WR_DURATION_1(7), .WR_DURATION_2(7), .WR_DURATION_3(7)) phy_control_i (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}), .INBURSTPENDING(phaser_ctl_bus[7:4]), .INRANKA(phaser_ctl_bus[9:8]), .INRANKB(phaser_ctl_bus[11:10]), .INRANKC(phaser_ctl_bus[13:12]), .INRANKD(phaser_ctl_bus[15:14]), .MEMREFCLK(mem_refclk), .OUTBURSTPENDING(phaser_ctl_bus[3:0]), .PCENABLECALIB(phy_encalib), .PHYCLK(CLK), .PHYCTLALMOSTFULL(phy_control_i_n_0), .PHYCTLEMPTY(phy_control_i_n_1), .PHYCTLFULL(_phy_ctl_full_p__0), .PHYCTLMSTREMPTY(phy_ctl_mstr_empty), .PHYCTLREADY(rst_primitives_reg_0), .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}), .PHYCTLWRENABLE(phy_ctl_wr_i2), .PLLLOCK(pll_locked), .READCALIBENABLE(phy_read_calib), .REFDLLLOCK(ref_dll_lock_w__0), .RESET(in0), .SYNCIN(sync_pulse), .WRITECALIBENABLE(phy_write_calib)); FDRE \pi_counter_read_val_reg[0] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_227 ), .Q(\pi_rdval_cnt_reg[5] [0]), .R(1'b0)); FDRE \pi_counter_read_val_reg[1] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ), .Q(\pi_rdval_cnt_reg[5] [1]), .R(1'b0)); FDRE \pi_counter_read_val_reg[2] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ), .Q(\pi_rdval_cnt_reg[5] [2]), .R(1'b0)); FDRE \pi_counter_read_val_reg[3] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ), .Q(\pi_rdval_cnt_reg[5] [3]), .R(1'b0)); FDRE \pi_counter_read_val_reg[4] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ), .Q(\pi_rdval_cnt_reg[5] [4]), .R(1'b0)); FDRE \pi_counter_read_val_reg[5] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ), .Q(\pi_rdval_cnt_reg[5] [5]), .R(1'b0)); FDRE \po_counter_read_val_reg[0] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ), .Q(\po_rdval_cnt_reg[8] [0]), .R(1'b0)); FDRE \po_counter_read_val_reg[1] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ), .Q(\po_rdval_cnt_reg[8] [1]), .R(1'b0)); FDRE \po_counter_read_val_reg[2] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ), .Q(\po_rdval_cnt_reg[8] [2]), .R(1'b0)); FDRE \po_counter_read_val_reg[3] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ), .Q(\po_rdval_cnt_reg[8] [3]), .R(1'b0)); FDRE \po_counter_read_val_reg[4] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ), .Q(\po_rdval_cnt_reg[8] [4]), .R(1'b0)); FDRE \po_counter_read_val_reg[5] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ), .Q(\po_rdval_cnt_reg[8] [5]), .R(1'b0)); FDRE \po_counter_read_val_reg[6] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ), .Q(\po_rdval_cnt_reg[8] [6]), .R(1'b0)); FDRE \po_counter_read_val_reg[7] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ), .Q(\po_rdval_cnt_reg[8] [7]), .R(1'b0)); FDRE \po_counter_read_val_reg[8] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ), .Q(\po_rdval_cnt_reg[8] [8]), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) SRL16E \rclk_delay_reg[10]_srl11 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(rst_primitives_reg_1), .Q(\rclk_delay_reg[10]_srl11_n_0 )); FDRE \rclk_delay_reg[11] (.C(CLK), .CE(1'b1), .D(\rclk_delay_reg[10]_srl11_n_0 ), .Q(rclk_delay_11), .R(1'b0)); FDCE #( .INIT(1'b0)) rst_out_reg (.C(CLK), .CE(1'b1), .CLR(rstdiv0_sync_r1_reg_rep__9), .D(\rclk_delay_reg[11]_0 ), .Q(mcGo_reg_0)); FDRE #( .INIT(1'b0)) rst_primitives_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_wr_i2_reg), .Q(rst_primitives), .R(1'b0)); LUT5 #( .INIT(32'h7FFFFFFF)) \rstdiv2_sync_r[11]_i_1 (.I0(ref_dll_lock_w__0), .I1(ref_dll_lock_w), .I2(sys_rst), .I3(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .I4(mmcm_locked), .O(rst_sync_r1_reg)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_ddr_phy_4lanes" *) module ddr3_if_mig_7series_v4_0_ddr_phy_4lanes__parameterized0 (\rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , phy_ctl_mstr_empty, ref_dll_lock_w, mcGo_w__0, \my_empty_reg[1] , \my_empty_reg[1]_0 , phy_mc_ctl_full, \my_empty_reg[1]_1 , \my_empty_reg[1]_2 , \byte_r_reg[0] , \po_counter_read_val_r_reg[5] , of_ctl_full_v, wr_en, wr_en_5, wr_en_6, Q, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , mem_dq_out, \po_rdval_cnt_reg[8] , ddr_ck_out, \my_empty_reg[7] , CLK, init_calib_complete_reg_rep__6, D5, D6, D2, D3, \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] , \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] , D7, D8, D9, D0, D1, \calib_sel_reg[0] , \gen_byte_sel_div1.calib_in_common_reg , \calib_sel_reg[0]_0 , \calib_sel_reg[0]_1 , freq_refclk, mem_refclk, \calib_sel_reg[0]_2 , sync_pulse, \calib_sel_reg[1] , \gen_byte_sel_div1.calib_in_common_reg_0 , \calib_sel_reg[1]_0 , \calib_sel_reg[1]_1 , \calib_sel_reg[1]_2 , \calib_sel_reg[1]_3 , \gen_byte_sel_div1.calib_in_common_reg_1 , \calib_sel_reg[1]_4 , \calib_sel_reg[1]_5 , \calib_sel_reg[1]_6 , phy_ctl_wr_i2, pll_locked, phy_read_calib, in0, phy_write_calib, PHYCTLWD, RST0, rstdiv0_sync_r1_reg_rep__9, mux_cmd_wren, mem_out, \rd_ptr_reg[3] , _phy_ctl_full_p__0, \rd_ptr_reg[3]_0 , init_calib_complete_reg_rep__5, mc_cas_n, \cmd_pipe_plus.mc_address_reg[43] , init_calib_complete_reg_rep, \calib_sel_reg[3] , \po_counter_read_val_reg[5]_0 , D_po_coarse_enable110_out, D_po_counter_read_en122_out, D_po_fine_enable107_out, D_po_fine_inc113_out, D_po_sel_fine_oclk_delay125_out, \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] , D4, \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] , phy_dout, init_calib_complete_reg_rep__6_0); output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output phy_ctl_mstr_empty; output [0:0]ref_dll_lock_w; output [0:0]mcGo_w__0; output \my_empty_reg[1] ; output \my_empty_reg[1]_0 ; output phy_mc_ctl_full; output \my_empty_reg[1]_1 ; output \my_empty_reg[1]_2 ; output \byte_r_reg[0] ; output [5:0]\po_counter_read_val_r_reg[5] ; output [0:0]of_ctl_full_v; output wr_en; output wr_en_5; output wr_en_6; output [3:0]Q; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [23:0]mem_dq_out; output [4:0]\po_rdval_cnt_reg[8] ; output [1:0]ddr_ck_out; output [31:0]\my_empty_reg[7] ; input CLK; input [3:0]init_calib_complete_reg_rep__6; input [3:0]D5; input [3:0]D6; input [2:0]D2; input [2:0]D3; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; input [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; input [3:0]D7; input [3:0]D8; input [3:0]D9; input [2:0]D0; input [2:0]D1; input \calib_sel_reg[0] ; input \gen_byte_sel_div1.calib_in_common_reg ; input \calib_sel_reg[0]_0 ; input \calib_sel_reg[0]_1 ; input freq_refclk; input mem_refclk; input \calib_sel_reg[0]_2 ; input sync_pulse; input \calib_sel_reg[1] ; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \calib_sel_reg[1]_0 ; input \calib_sel_reg[1]_1 ; input \calib_sel_reg[1]_2 ; input \calib_sel_reg[1]_3 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \calib_sel_reg[1]_4 ; input \calib_sel_reg[1]_5 ; input \calib_sel_reg[1]_6 ; input phy_ctl_wr_i2; input pll_locked; input phy_read_calib; input in0; input phy_write_calib; input [10:0]PHYCTLWD; input RST0; input rstdiv0_sync_r1_reg_rep__9; input mux_cmd_wren; input [11:0]mem_out; input [33:0]\rd_ptr_reg[3] ; input [0:0]_phy_ctl_full_p__0; input [17:0]\rd_ptr_reg[3]_0 ; input init_calib_complete_reg_rep__5; input [0:0]mc_cas_n; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input init_calib_complete_reg_rep; input [2:0]\calib_sel_reg[3] ; input [5:0]\po_counter_read_val_reg[5]_0 ; input D_po_coarse_enable110_out; input D_po_counter_read_en122_out; input D_po_fine_enable107_out; input D_po_fine_inc113_out; input D_po_sel_fine_oclk_delay125_out; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; input [3:0]D4; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; input [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; input [35:0]phy_dout; input init_calib_complete_reg_rep__6_0; wire A_of_full; (* async_reg = "true" *) wire A_pi_rst_div2; wire [8:0]A_po_counter_read_val; wire A_rst_primitives; (* async_reg = "true" *) wire B_pi_rst_div2; wire [8:0]B_po_counter_read_val; wire CLK; wire C_of_full; (* async_reg = "true" *) wire C_pi_rst_div2; wire [8:0]C_po_counter_read_val; wire [2:0]D0; wire [2:0]D1; wire [2:0]D2; wire [2:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire D_of_full; (* async_reg = "true" *) wire D_pi_rst_div2; wire D_po_coarse_enable110_out; wire D_po_counter_read_en122_out; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire D_po_sel_fine_oclk_delay125_out; wire [10:0]PHYCTLWD; wire [3:0]Q; wire RST0; wire [1:1]_phy_ctl_full_p; wire [0:0]_phy_ctl_full_p__0; wire \byte_r_reg[0] ; wire \calib_sel_reg[0] ; wire \calib_sel_reg[0]_0 ; wire \calib_sel_reg[0]_1 ; wire \calib_sel_reg[0]_2 ; wire \calib_sel_reg[1] ; wire \calib_sel_reg[1]_0 ; wire \calib_sel_reg[1]_1 ; wire \calib_sel_reg[1]_2 ; wire \calib_sel_reg[1]_3 ; wire \calib_sel_reg[1]_4 ; wire \calib_sel_reg[1]_5 ; wire \calib_sel_reg[1]_6 ; wire [2:0]\calib_sel_reg[3] ; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_1 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_2 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_3 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_4 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_5 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_6 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_7 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_8 ; wire \ddr_byte_lane_D.ddr_byte_lane_D_n_9 ; wire [1:0]ddr_ck_out; wire freq_refclk; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ; wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ; wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ; wire in0; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__5; wire [3:0]init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire [0:0]mcGo_w__0; wire [0:0]mc_cas_n; wire [23:0]mem_dq_out; wire [11:0]mem_out; wire mem_refclk; wire mux_cmd_wren; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire [31:0]\my_empty_reg[7] ; wire [0:0]of_ctl_full_v; wire ofifo_rst; wire [3:3]phaser_ctl_bus; wire phy_control_i_n_0; wire phy_control_i_n_10; wire phy_control_i_n_11; wire phy_control_i_n_14; wire phy_control_i_n_15; wire phy_control_i_n_16; wire phy_control_i_n_17; wire phy_control_i_n_18; wire phy_control_i_n_19; wire phy_control_i_n_20; wire phy_control_i_n_21; wire phy_control_i_n_23; wire phy_control_i_n_24; wire phy_control_i_n_25; wire phy_control_i_n_3; wire phy_control_i_n_4; wire phy_control_i_n_5; wire phy_control_i_n_6; wire phy_control_i_n_7; wire phy_control_i_n_8; wire phy_control_i_n_9; wire phy_ctl_mstr_empty; wire phy_ctl_wr_i2; wire [35:0]phy_dout; wire [1:0]phy_encalib; wire phy_mc_ctl_full; wire phy_read_calib; wire phy_write_calib; wire pll_locked; wire [5:0]\po_counter_read_val_r_reg[5] ; wire [5:0]\po_counter_read_val_reg[5]_0 ; wire [5:1]\po_counter_read_val_w[1]_2 ; wire [4:0]\po_rdval_cnt_reg[8] ; wire rclk_delay_11; wire \rclk_delay_reg[10]_srl11_i_1__0_n_0 ; wire \rclk_delay_reg[10]_srl11_n_0 ; wire [33:0]\rd_ptr_reg[3] ; wire [17:0]\rd_ptr_reg[3]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]ref_dll_lock_w; wire rst_out_i_1__0_n_0; wire rst_out_reg_n_0; wire rst_primitives; wire rst_primitives_i_1__0_n_0; wire rstdiv0_sync_r1_reg_rep__9; wire sync_pulse; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; FDRE #( .INIT(1'b0)) A_rst_primitives_reg (.C(CLK), .CE(1'b1), .D(rst_primitives), .Q(A_rst_primitives), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \byte_r[0]_i_3 (.I0(\po_counter_read_val_r_reg[5] [2]), .I1(\po_counter_read_val_r_reg[5] [5]), .I2(\po_counter_read_val_r_reg[5] [0]), .I3(\po_counter_read_val_r_reg[5] [3]), .I4(\po_counter_read_val_r_reg[5] [1]), .I5(\po_counter_read_val_r_reg[5] [4]), .O(\byte_r_reg[0] )); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized3 \ddr_byte_lane_A.ddr_byte_lane_A (.A_of_full(A_of_full), .A_rst_primitives(A_rst_primitives), .CLK(CLK), .COUNTERREADVAL(A_po_counter_read_val), .D0(D0), .D1(D1), .OUTBURSTPENDING(phy_control_i_n_25), .PCENABLECALIB(phy_encalib), .Q(\wr_ptr_timing_reg[2]_0 ), .SR(ofifo_rst), .\calib_sel_reg[1] (\calib_sel_reg[1] ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_1 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_2 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_0 ), .mem_dq_out(mem_dq_out[1:0]), .mem_out(mem_out), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1] ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_9 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_10 ), .sync_pulse(sync_pulse), .wr_en(wr_en)); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized4 \ddr_byte_lane_B.ddr_byte_lane_B (.A_of_full(A_of_full), .A_rst_primitives(A_rst_primitives), .CLK(CLK), .COUNTERREADVAL(B_po_counter_read_val), .C_of_full(C_of_full), .D5(D5), .D6(D6), .D_of_full(D_of_full), .OUTBURSTPENDING(phy_control_i_n_24), .PCENABLECALIB(phy_encalib), .Q(Q), .SR(ofifo_rst), .\calib_sel_reg[1] (\calib_sel_reg[1]_3 ), .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_4 ), .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_5 ), .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_6 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg_1 ), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .mem_dq_out(mem_dq_out[4:2]), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1]_1 ), .of_ctl_full_v(of_ctl_full_v), .\rd_ptr_reg[3] (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .sync_pulse(sync_pulse), .wr_en_5(wr_en_5)); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized5 \ddr_byte_lane_C.ddr_byte_lane_C (.A_rst_primitives(A_rst_primitives), .CLK(CLK), .COUNTERREADVAL(C_po_counter_read_val), .C_of_full(C_of_full), .D2(D2), .D3(D3), .D7(D7), .D8(D8), .D9(D9), .OUTBURSTPENDING(phy_control_i_n_23), .PCENABLECALIB(phy_encalib), .Q(\wr_ptr_timing_reg[2] ), .SR(ofifo_rst), .\calib_sel_reg[0] (\calib_sel_reg[0] ), .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ), .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ), .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ), .mem_dq_out(mem_dq_out[14:5]), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1]_0 ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_6 ), .sync_pulse(sync_pulse), .wr_en_6(wr_en_6)); ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized6 \ddr_byte_lane_D.ddr_byte_lane_D (.A_rst_primitives(A_rst_primitives), .A_rst_primitives_reg(C_po_counter_read_val), .A_rst_primitives_reg_0(A_po_counter_read_val), .CLK(CLK), .COUNTERREADVAL(B_po_counter_read_val), .D({\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_9 }), .D4(D4), .D_of_full(D_of_full), .D_po_coarse_enable110_out(D_po_coarse_enable110_out), .D_po_counter_read_en122_out(D_po_counter_read_en122_out), .D_po_fine_enable107_out(D_po_fine_enable107_out), .D_po_fine_inc113_out(D_po_fine_inc113_out), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .OUTBURSTPENDING(phaser_ctl_bus), .PCENABLECALIB(phy_encalib), .SR(ofifo_rst), .\calib_sel_reg[1] (\calib_sel_reg[3] [1:0]), .\cmd_pipe_plus.mc_address_reg[43] (\cmd_pipe_plus.mc_address_reg[43] ), .ddr_ck_out(ddr_ck_out), .freq_refclk(freq_refclk), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ), .init_calib_complete_reg_rep(init_calib_complete_reg_rep), .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0), .mc_cas_n(mc_cas_n), .mem_dq_out(mem_dq_out[23:15]), .mem_refclk(mem_refclk), .mux_cmd_wren(mux_cmd_wren), .\my_empty_reg[1] (\my_empty_reg[1]_2 ), .\my_empty_reg[7] (\my_empty_reg[7] ), .phy_dout(phy_dout), .sync_pulse(sync_pulse)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(A_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(B_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(C_pi_rst_div2)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(D_pi_rst_div2)); FDRE #( .INIT(1'b0)) mcGo_reg (.C(CLK), .CE(1'b1), .D(rst_out_reg_n_0), .Q(mcGo_w__0), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) PHASER_REF #( .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0)) phaser_ref_i (.CLKIN(freq_refclk), .LOCKED(ref_dll_lock_w), .PWRDWN(1'b0), .RST(RST0)); (* BOX_TYPE = "PRIMITIVE" *) PHY_CONTROL #( .AO_TOGGLE(1), .BURST_MODE("TRUE"), .CLK_RATIO(4), .CMD_OFFSET(8), .CO_DURATION(1), .DATA_CTL_A_N("FALSE"), .DATA_CTL_B_N("FALSE"), .DATA_CTL_C_N("FALSE"), .DATA_CTL_D_N("FALSE"), .DISABLE_SEQ_MATCH("TRUE"), .DI_DURATION(1), .DO_DURATION(1), .EVENTS_DELAY(18), .FOUR_WINDOW_CLOCKS(63), .MULTI_REGION("TRUE"), .PHY_COUNT_ENABLE("FALSE"), .RD_CMD_OFFSET_0(10), .RD_CMD_OFFSET_1(10), .RD_CMD_OFFSET_2(10), .RD_CMD_OFFSET_3(10), .RD_DURATION_0(6), .RD_DURATION_1(6), .RD_DURATION_2(6), .RD_DURATION_3(6), .SYNC_MODE("FALSE"), .WR_CMD_OFFSET_0(8), .WR_CMD_OFFSET_1(8), .WR_CMD_OFFSET_2(8), .WR_CMD_OFFSET_3(8), .WR_DURATION_0(7), .WR_DURATION_1(7), .WR_DURATION_2(7), .WR_DURATION_3(7)) phy_control_i (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}), .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}), .INRANKA({phy_control_i_n_4,phy_control_i_n_5}), .INRANKB({phy_control_i_n_6,phy_control_i_n_7}), .INRANKC({phy_control_i_n_8,phy_control_i_n_9}), .INRANKD({phy_control_i_n_10,phy_control_i_n_11}), .MEMREFCLK(mem_refclk), .OUTBURSTPENDING({phaser_ctl_bus,phy_control_i_n_23,phy_control_i_n_24,phy_control_i_n_25}), .PCENABLECALIB(phy_encalib), .PHYCLK(CLK), .PHYCTLALMOSTFULL(phy_control_i_n_0), .PHYCTLEMPTY(phy_ctl_mstr_empty), .PHYCTLFULL(_phy_ctl_full_p), .PHYCTLMSTREMPTY(phy_ctl_mstr_empty), .PHYCTLREADY(phy_control_i_n_3), .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}), .PHYCTLWRENABLE(phy_ctl_wr_i2), .PLLLOCK(pll_locked), .READCALIBENABLE(phy_read_calib), .REFDLLLOCK(ref_dll_lock_w), .RESET(in0), .SYNCIN(sync_pulse), .WRITECALIBENABLE(phy_write_calib)); LUT2 #( .INIT(4'hE)) phy_mc_ctl_full_r_i_1 (.I0(_phy_ctl_full_p), .I1(_phy_ctl_full_p__0), .O(phy_mc_ctl_full)); (* SOFT_HLUTNM = "soft_lutpair1022" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[0]_i_1 (.I0(\po_rdval_cnt_reg[8] [0]), .I1(\po_counter_read_val_reg[5]_0 [0]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [0])); (* SOFT_HLUTNM = "soft_lutpair1022" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[1]_i_1 (.I0(\po_counter_read_val_w[1]_2 [1]), .I1(\po_counter_read_val_reg[5]_0 [1]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [1])); (* SOFT_HLUTNM = "soft_lutpair1023" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[2]_i_1 (.I0(\po_counter_read_val_w[1]_2 [2]), .I1(\po_counter_read_val_reg[5]_0 [2]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [2])); (* SOFT_HLUTNM = "soft_lutpair1023" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[3]_i_1 (.I0(\po_rdval_cnt_reg[8] [1]), .I1(\po_counter_read_val_reg[5]_0 [3]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [3])); (* SOFT_HLUTNM = "soft_lutpair1024" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[4]_i_1 (.I0(\po_counter_read_val_w[1]_2 [4]), .I1(\po_counter_read_val_reg[5]_0 [4]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [4])); (* SOFT_HLUTNM = "soft_lutpair1024" *) LUT3 #( .INIT(8'hAC)) \po_counter_read_val_r[5]_i_1 (.I0(\po_counter_read_val_w[1]_2 [5]), .I1(\po_counter_read_val_reg[5]_0 [5]), .I2(\calib_sel_reg[3] [2]), .O(\po_counter_read_val_r_reg[5] [5])); FDRE \po_counter_read_val_reg[0] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_9 ), .Q(\po_rdval_cnt_reg[8] [0]), .R(1'b0)); FDRE \po_counter_read_val_reg[1] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ), .Q(\po_counter_read_val_w[1]_2 [1]), .R(1'b0)); FDRE \po_counter_read_val_reg[2] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ), .Q(\po_counter_read_val_w[1]_2 [2]), .R(1'b0)); FDRE \po_counter_read_val_reg[3] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ), .Q(\po_rdval_cnt_reg[8] [1]), .R(1'b0)); FDRE \po_counter_read_val_reg[4] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ), .Q(\po_counter_read_val_w[1]_2 [4]), .R(1'b0)); FDRE \po_counter_read_val_reg[5] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ), .Q(\po_counter_read_val_w[1]_2 [5]), .R(1'b0)); FDRE \po_counter_read_val_reg[6] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ), .Q(\po_rdval_cnt_reg[8] [2]), .R(1'b0)); FDRE \po_counter_read_val_reg[7] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ), .Q(\po_rdval_cnt_reg[8] [3]), .R(1'b0)); FDRE \po_counter_read_val_reg[8] (.C(CLK), .CE(1'b1), .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ), .Q(\po_rdval_cnt_reg[8] [4]), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) SRL16E \rclk_delay_reg[10]_srl11 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(\rclk_delay_reg[10]_srl11_i_1__0_n_0 ), .Q(\rclk_delay_reg[10]_srl11_n_0 )); LUT1 #( .INIT(2'h1)) \rclk_delay_reg[10]_srl11_i_1__0 (.I0(rst_primitives), .O(\rclk_delay_reg[10]_srl11_i_1__0_n_0 )); FDRE \rclk_delay_reg[11] (.C(CLK), .CE(1'b1), .D(\rclk_delay_reg[10]_srl11_n_0 ), .Q(rclk_delay_11), .R(1'b0)); LUT2 #( .INIT(4'hE)) rst_out_i_1__0 (.I0(rclk_delay_11), .I1(rst_out_reg_n_0), .O(rst_out_i_1__0_n_0)); FDCE #( .INIT(1'b0)) rst_out_reg (.C(CLK), .CE(1'b1), .CLR(rstdiv0_sync_r1_reg_rep__9), .D(rst_out_i_1__0_n_0), .Q(rst_out_reg_n_0)); LUT1 #( .INIT(2'h1)) rst_primitives_i_1__0 (.I0(phy_control_i_n_3), .O(rst_primitives_i_1__0_n_0)); FDRE #( .INIT(1'b0)) rst_primitives_reg (.C(CLK), .CE(1'b1), .D(rst_primitives_i_1__0_n_0), .Q(rst_primitives), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay (ck_addr_cmd_delay_done, po_en_stg2_f, D_po_coarse_enable110_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , \wait_cnt_r_reg[0]_0 , \init_state_r_reg[0] , delay_dec_done_reg_0, delay_dec_done_reg_1, ctl_lane_cnt, po_cnt_inc_reg_0, CLK, rstdiv0_sync_r1_reg_rep__9, \wait_cnt_r_reg[0]_1 , \wait_cnt_r_reg[0]_2 , Q, calib_in_common, dqs_wl_po_stg2_c_incdec, \calib_zero_inputs_reg[1] , cnt_pwron_cke_done_r, \mcGo_r_reg[15] , pi_fine_dly_dec_done, dqs_po_dec_done, rstdiv0_sync_r1_reg_rep__25, rstdiv0_sync_r1_reg_rep__24, cmd_delay_start0, p_1_in); output ck_addr_cmd_delay_done; output po_en_stg2_f; output D_po_coarse_enable110_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output [0:0]\wait_cnt_r_reg[0]_0 ; output \init_state_r_reg[0] ; output delay_dec_done_reg_0; output delay_dec_done_reg_1; output [2:0]ctl_lane_cnt; output po_cnt_inc_reg_0; input CLK; input rstdiv0_sync_r1_reg_rep__9; input \wait_cnt_r_reg[0]_1 ; input \wait_cnt_r_reg[0]_2 ; input [1:0]Q; input calib_in_common; input dqs_wl_po_stg2_c_incdec; input [1:0]\calib_zero_inputs_reg[1] ; input cnt_pwron_cke_done_r; input \mcGo_r_reg[15] ; input pi_fine_dly_dec_done; input dqs_po_dec_done; input rstdiv0_sync_r1_reg_rep__25; input rstdiv0_sync_r1_reg_rep__24; input cmd_delay_start0; input p_1_in; wire CLK; wire D_po_coarse_enable110_out; wire [1:0]Q; wire calib_in_common; wire [1:0]\calib_zero_inputs_reg[1] ; wire ck_addr_cmd_delay_done; wire cmd_delay_start0; wire cnt_pwron_cke_done_r; wire [2:0]ctl_lane_cnt; wire ctl_lane_cnt1; wire \ctl_lane_cnt[0]_i_1_n_0 ; wire \ctl_lane_cnt[1]_i_1_n_0 ; wire \ctl_lane_cnt[2]_i_1_n_0 ; wire \ctl_lane_cnt[2]_i_4_n_0 ; wire \ctl_lane_cnt[3]_i_1_n_0 ; wire \ctl_lane_cnt[3]_i_3_n_0 ; wire \ctl_lane_cnt_reg_n_0_[3] ; wire delay_cnt_r0; wire \delay_cnt_r[0]_i_1_n_0 ; wire \delay_cnt_r[0]_i_2_n_0 ; wire \delay_cnt_r[1]_i_1_n_0 ; wire \delay_cnt_r[2]_i_1_n_0 ; wire \delay_cnt_r[3]_i_1_n_0 ; wire \delay_cnt_r[4]_i_1_n_0 ; wire \delay_cnt_r[5]_i_1_n_0 ; wire \delay_cnt_r[5]_i_3_n_0 ; wire \delay_cnt_r[5]_i_5_n_0 ; wire \delay_cnt_r_reg_n_0_[0] ; wire \delay_cnt_r_reg_n_0_[1] ; wire \delay_cnt_r_reg_n_0_[2] ; wire \delay_cnt_r_reg_n_0_[3] ; wire \delay_cnt_r_reg_n_0_[4] ; wire \delay_cnt_r_reg_n_0_[5] ; wire delay_dec_done; wire delay_dec_done_i_1_n_0; wire delay_dec_done_reg_0; wire delay_dec_done_reg_1; wire delay_done_r3_reg_srl3_n_0; wire delaydec_cnt_r0; wire delaydec_cnt_r10_in; wire \delaydec_cnt_r[0]_i_1_n_0 ; wire \delaydec_cnt_r[1]_i_1_n_0 ; wire \delaydec_cnt_r[2]_i_1_n_0 ; wire \delaydec_cnt_r[3]_i_1_n_0 ; wire \delaydec_cnt_r[4]_i_1_n_0 ; wire \delaydec_cnt_r[5]_i_1_n_0 ; wire \delaydec_cnt_r[5]_i_3_n_0 ; wire [5:0]delaydec_cnt_r_reg__0; wire dqs_po_dec_done; wire dqs_wl_po_stg2_c_incdec; wire \init_state_r_reg[0] ; wire \mcGo_r_reg[15] ; wire p_1_in; wire p_3_in; wire pi_fine_dly_dec_done; wire po_cnt_dec; wire po_cnt_inc; wire po_cnt_inc_reg_0; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire po_en_stg2_f; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__9; wire wait_cnt_r0; wire [0:0]wait_cnt_r0__0; wire \wait_cnt_r[1]_i_1__0_n_0 ; wire \wait_cnt_r[2]_i_1__1_n_0 ; wire \wait_cnt_r[3]_i_1__0_n_0 ; wire \wait_cnt_r[3]_i_3__0_n_0 ; wire [0:0]\wait_cnt_r_reg[0]_0 ; wire \wait_cnt_r_reg[0]_1 ; wire \wait_cnt_r_reg[0]_2 ; wire [3:1]wait_cnt_r_reg__0__0; LUT6 #( .INIT(64'h00000000DE000000)) \ctl_lane_cnt[0]_i_1 (.I0(ctl_lane_cnt[0]), .I1(ctl_lane_cnt1), .I2(delaydec_cnt_r10_in), .I3(pi_fine_dly_dec_done), .I4(dqs_po_dec_done), .I5(rstdiv0_sync_r1_reg_rep__25), .O(\ctl_lane_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000DEEE0000)) \ctl_lane_cnt[1]_i_1 (.I0(ctl_lane_cnt[1]), .I1(ctl_lane_cnt1), .I2(delaydec_cnt_r10_in), .I3(ctl_lane_cnt[0]), .I4(cmd_delay_start0), .I5(rstdiv0_sync_r1_reg_rep__25), .O(\ctl_lane_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000006AAA)) \ctl_lane_cnt[2]_i_1 (.I0(ctl_lane_cnt[2]), .I1(delaydec_cnt_r10_in), .I2(ctl_lane_cnt[0]), .I3(ctl_lane_cnt[1]), .I4(p_1_in), .I5(ctl_lane_cnt1), .O(\ctl_lane_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair308" *) LUT4 #( .INIT(16'h0004)) \ctl_lane_cnt[2]_i_3 (.I0(\delay_cnt_r[0]_i_2_n_0 ), .I1(delaydec_cnt_r_reg__0[0]), .I2(delay_dec_done), .I3(\ctl_lane_cnt[2]_i_4_n_0 ), .O(ctl_lane_cnt1)); LUT5 #( .INIT(32'hFFFFFFFE)) \ctl_lane_cnt[2]_i_4 (.I0(delaydec_cnt_r_reg__0[4]), .I1(delaydec_cnt_r_reg__0[2]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[3]), .I4(delaydec_cnt_r_reg__0[5]), .O(\ctl_lane_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'h000000006AAAAAAA)) \ctl_lane_cnt[3]_i_1 (.I0(\ctl_lane_cnt_reg_n_0_[3] ), .I1(delaydec_cnt_r10_in), .I2(ctl_lane_cnt[2]), .I3(ctl_lane_cnt[1]), .I4(ctl_lane_cnt[0]), .I5(\ctl_lane_cnt[3]_i_3_n_0 ), .O(\ctl_lane_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000054555555)) \ctl_lane_cnt[3]_i_2 (.I0(delay_dec_done_reg_1), .I1(\ctl_lane_cnt_reg_n_0_[3] ), .I2(ctl_lane_cnt[2]), .I3(ctl_lane_cnt[1]), .I4(ctl_lane_cnt[0]), .I5(delay_dec_done_reg_0), .O(delaydec_cnt_r10_in)); LUT4 #( .INIT(16'hFFBF)) \ctl_lane_cnt[3]_i_3 (.I0(ctl_lane_cnt1), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(rstdiv0_sync_r1_reg_rep__25), .O(\ctl_lane_cnt[3]_i_3_n_0 )); FDRE \ctl_lane_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[0]_i_1_n_0 ), .Q(ctl_lane_cnt[0]), .R(1'b0)); FDRE \ctl_lane_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[1]_i_1_n_0 ), .Q(ctl_lane_cnt[1]), .R(1'b0)); FDRE \ctl_lane_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[2]_i_1_n_0 ), .Q(ctl_lane_cnt[2]), .R(1'b0)); FDRE \ctl_lane_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\ctl_lane_cnt[3]_i_1_n_0 ), .Q(\ctl_lane_cnt_reg_n_0_[3] ), .R(1'b0)); LUT5 #( .INIT(32'hDDFFEEFC)) \delay_cnt_r[0]_i_1 (.I0(po_cnt_inc), .I1(delay_dec_done_reg_0), .I2(\delay_cnt_r[0]_i_2_n_0 ), .I3(delay_dec_done_reg_1), .I4(\delay_cnt_r_reg_n_0_[0] ), .O(\delay_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair305" *) LUT4 #( .INIT(16'hEFFF)) \delay_cnt_r[0]_i_2 (.I0(\ctl_lane_cnt_reg_n_0_[3] ), .I1(ctl_lane_cnt[2]), .I2(ctl_lane_cnt[1]), .I3(ctl_lane_cnt[0]), .O(\delay_cnt_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair310" *) LUT2 #( .INIT(4'h9)) \delay_cnt_r[1]_i_1 (.I0(\delay_cnt_r_reg_n_0_[0] ), .I1(\delay_cnt_r_reg_n_0_[1] ), .O(\delay_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair310" *) LUT3 #( .INIT(8'hE1)) \delay_cnt_r[2]_i_1 (.I0(\delay_cnt_r_reg_n_0_[1] ), .I1(\delay_cnt_r_reg_n_0_[0] ), .I2(\delay_cnt_r_reg_n_0_[2] ), .O(\delay_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair306" *) LUT4 #( .INIT(16'hFE01)) \delay_cnt_r[3]_i_1 (.I0(\delay_cnt_r_reg_n_0_[2] ), .I1(\delay_cnt_r_reg_n_0_[0] ), .I2(\delay_cnt_r_reg_n_0_[1] ), .I3(\delay_cnt_r_reg_n_0_[3] ), .O(\delay_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair306" *) LUT5 #( .INIT(32'hFFFE0001)) \delay_cnt_r[4]_i_1 (.I0(\delay_cnt_r_reg_n_0_[3] ), .I1(\delay_cnt_r_reg_n_0_[1] ), .I2(\delay_cnt_r_reg_n_0_[0] ), .I3(\delay_cnt_r_reg_n_0_[2] ), .I4(\delay_cnt_r_reg_n_0_[4] ), .O(\delay_cnt_r[4]_i_1_n_0 )); LUT3 #( .INIT(8'hFE)) \delay_cnt_r[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(delay_dec_done_reg_0), .I2(\delay_cnt_r[5]_i_5_n_0 ), .O(\delay_cnt_r[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \delay_cnt_r[5]_i_2 (.I0(delay_dec_done_reg_1), .I1(po_cnt_inc), .O(delay_cnt_r0)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \delay_cnt_r[5]_i_3 (.I0(\delay_cnt_r_reg_n_0_[4] ), .I1(\delay_cnt_r_reg_n_0_[2] ), .I2(\delay_cnt_r_reg_n_0_[0] ), .I3(\delay_cnt_r_reg_n_0_[1] ), .I4(\delay_cnt_r_reg_n_0_[3] ), .I5(\delay_cnt_r_reg_n_0_[5] ), .O(\delay_cnt_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \delay_cnt_r[5]_i_4 (.I0(delaydec_cnt_r_reg__0[5]), .I1(delaydec_cnt_r_reg__0[3]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[2]), .I4(delaydec_cnt_r_reg__0[4]), .I5(delaydec_cnt_r_reg__0[0]), .O(delay_dec_done_reg_0)); (* SOFT_HLUTNM = "soft_lutpair305" *) LUT5 #( .INIT(32'h0000FFF7)) \delay_cnt_r[5]_i_5 (.I0(ctl_lane_cnt[0]), .I1(ctl_lane_cnt[1]), .I2(ctl_lane_cnt[2]), .I3(\ctl_lane_cnt_reg_n_0_[3] ), .I4(delay_dec_done_reg_1), .O(\delay_cnt_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \delay_cnt_r[5]_i_6 (.I0(\delay_cnt_r_reg_n_0_[4] ), .I1(\delay_cnt_r_reg_n_0_[2] ), .I2(\delay_cnt_r_reg_n_0_[0] ), .I3(\delay_cnt_r_reg_n_0_[1] ), .I4(\delay_cnt_r_reg_n_0_[3] ), .I5(\delay_cnt_r_reg_n_0_[5] ), .O(delay_dec_done_reg_1)); FDRE \delay_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\delay_cnt_r[0]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \delay_cnt_r_reg[1] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[1]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[1] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE \delay_cnt_r_reg[2] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[2]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[2] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE \delay_cnt_r_reg[3] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[3]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[3] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE \delay_cnt_r_reg[4] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[4]_i_1_n_0 ), .Q(\delay_cnt_r_reg_n_0_[4] ), .R(\delay_cnt_r[5]_i_1_n_0 )); FDRE \delay_cnt_r_reg[5] (.C(CLK), .CE(delay_cnt_r0), .D(\delay_cnt_r[5]_i_3_n_0 ), .Q(\delay_cnt_r_reg_n_0_[5] ), .R(\delay_cnt_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000AAAB0000)) delay_dec_done_i_1 (.I0(delay_dec_done), .I1(\delay_cnt_r[0]_i_2_n_0 ), .I2(delay_dec_done_reg_0), .I3(delay_dec_done_reg_1), .I4(cmd_delay_start0), .I5(rstdiv0_sync_r1_reg_rep__25), .O(delay_dec_done_i_1_n_0)); FDRE delay_dec_done_reg (.C(CLK), .CE(1'b1), .D(delay_dec_done_i_1_n_0), .Q(delay_dec_done), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 " *) SRL16E delay_done_r3_reg_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(delay_dec_done), .Q(delay_done_r3_reg_srl3_n_0)); (* syn_maxfan = "10" *) FDRE delay_done_r4_reg (.C(CLK), .CE(1'b1), .D(delay_done_r3_reg_srl3_n_0), .Q(ck_addr_cmd_delay_done), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair312" *) LUT1 #( .INIT(2'h1)) \delaydec_cnt_r[0]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .O(\delaydec_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair308" *) LUT2 #( .INIT(4'h9)) \delaydec_cnt_r[1]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[1]), .O(\delaydec_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair312" *) LUT3 #( .INIT(8'hE1)) \delaydec_cnt_r[2]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[1]), .I2(delaydec_cnt_r_reg__0[2]), .O(\delaydec_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair307" *) LUT4 #( .INIT(16'hFE01)) \delaydec_cnt_r[3]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[1]), .I2(delaydec_cnt_r_reg__0[2]), .I3(delaydec_cnt_r_reg__0[3]), .O(\delaydec_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair307" *) LUT5 #( .INIT(32'hFFFE0001)) \delaydec_cnt_r[4]_i_1 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[2]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[3]), .I4(delaydec_cnt_r_reg__0[4]), .O(\delaydec_cnt_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'hFFBF)) \delaydec_cnt_r[5]_i_1 (.I0(delaydec_cnt_r10_in), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(rstdiv0_sync_r1_reg_rep__25), .O(\delaydec_cnt_r[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \delaydec_cnt_r[5]_i_2 (.I0(delay_dec_done_reg_0), .I1(po_cnt_dec), .O(delaydec_cnt_r0)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \delaydec_cnt_r[5]_i_3 (.I0(delaydec_cnt_r_reg__0[0]), .I1(delaydec_cnt_r_reg__0[3]), .I2(delaydec_cnt_r_reg__0[1]), .I3(delaydec_cnt_r_reg__0[2]), .I4(delaydec_cnt_r_reg__0[4]), .I5(delaydec_cnt_r_reg__0[5]), .O(\delaydec_cnt_r[5]_i_3_n_0 )); FDSE \delaydec_cnt_r_reg[0] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[0]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[0]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDRE \delaydec_cnt_r_reg[1] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[1]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[1]), .R(\delaydec_cnt_r[5]_i_1_n_0 )); FDSE \delaydec_cnt_r_reg[2] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[2]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[2]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDSE \delaydec_cnt_r_reg[3] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[3]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[3]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDSE \delaydec_cnt_r_reg[4] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[4]_i_1_n_0 ), .Q(delaydec_cnt_r_reg__0[4]), .S(\delaydec_cnt_r[5]_i_1_n_0 )); FDRE \delaydec_cnt_r_reg[5] (.C(CLK), .CE(delaydec_cnt_r0), .D(\delaydec_cnt_r[5]_i_3_n_0 ), .Q(delaydec_cnt_r_reg__0[5]), .R(\delaydec_cnt_r[5]_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \init_state_r[0]_i_39 (.I0(ck_addr_cmd_delay_done), .I1(cnt_pwron_cke_done_r), .I2(\mcGo_r_reg[15] ), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h0000000008080800)) phaser_out_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(D_po_coarse_enable110_out)); LUT6 #( .INIT(64'h0000000001010100)) phaser_out_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8] )); LUT6 #( .INIT(64'h0000000004040400)) phaser_out_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_0 )); LUT6 #( .INIT(64'h0000000004040400)) phaser_out_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_1 )); LUT6 #( .INIT(64'h00000000EAEAEA00)) phaser_out_i_1__3 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_2 )); LUT6 #( .INIT(64'h00000000BABABA00)) phaser_out_i_1__4 (.I0(calib_in_common), .I1(Q[0]), .I2(Q[1]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_3 )); LUT6 #( .INIT(64'h00000000BABABA00)) phaser_out_i_1__5 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_4 )); LUT6 #( .INIT(64'h00000000ABABAB00)) phaser_out_i_1__6 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(p_3_in), .I4(dqs_wl_po_stg2_c_incdec), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_5 )); FDRE po_cnt_dec_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_r_reg[0]_2 ), .Q(po_cnt_dec), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair309" *) LUT3 #( .INIT(8'hFE)) po_cnt_inc_i_2 (.I0(wait_cnt_r_reg__0__0[2]), .I1(wait_cnt_r_reg__0__0[1]), .I2(wait_cnt_r_reg__0__0[3]), .O(po_cnt_inc_reg_0)); FDRE po_cnt_inc_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_r_reg[0]_1 ), .Q(po_cnt_inc), .R(1'b0)); FDRE po_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(po_cnt_dec), .Q(po_en_stg2_f), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE po_stg2_c_incdec_reg (.C(CLK), .CE(1'b1), .D(po_cnt_inc), .Q(p_3_in), .R(rstdiv0_sync_r1_reg_rep__9)); LUT1 #( .INIT(2'h1)) \wait_cnt_r[0]_i_1__0 (.I0(\wait_cnt_r_reg[0]_0 ), .O(wait_cnt_r0__0)); (* SOFT_HLUTNM = "soft_lutpair311" *) LUT2 #( .INIT(4'h9)) \wait_cnt_r[1]_i_1__0 (.I0(\wait_cnt_r_reg[0]_0 ), .I1(wait_cnt_r_reg__0__0[1]), .O(\wait_cnt_r[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair311" *) LUT3 #( .INIT(8'hE1)) \wait_cnt_r[2]_i_1__1 (.I0(wait_cnt_r_reg__0__0[1]), .I1(\wait_cnt_r_reg[0]_0 ), .I2(wait_cnt_r_reg__0__0[2]), .O(\wait_cnt_r[2]_i_1__1_n_0 )); LUT3 #( .INIT(8'hFE)) \wait_cnt_r[3]_i_1__0 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(po_cnt_dec), .I2(po_cnt_inc), .O(\wait_cnt_r[3]_i_1__0_n_0 )); LUT6 #( .INIT(64'hC0C0C0C0C0C0C080)) \wait_cnt_r[3]_i_2__0 (.I0(\wait_cnt_r_reg[0]_0 ), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(wait_cnt_r_reg__0__0[2]), .I4(wait_cnt_r_reg__0__0[1]), .I5(wait_cnt_r_reg__0__0[3]), .O(wait_cnt_r0)); (* SOFT_HLUTNM = "soft_lutpair309" *) LUT4 #( .INIT(16'hFE01)) \wait_cnt_r[3]_i_3__0 (.I0(\wait_cnt_r_reg[0]_0 ), .I1(wait_cnt_r_reg__0__0[1]), .I2(wait_cnt_r_reg__0__0[2]), .I3(wait_cnt_r_reg__0__0[3]), .O(\wait_cnt_r[3]_i_3__0_n_0 )); FDRE \wait_cnt_r_reg[0] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0), .Q(\wait_cnt_r_reg[0]_0 ), .R(\wait_cnt_r[3]_i_1__0_n_0 )); FDRE \wait_cnt_r_reg[1] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[1]_i_1__0_n_0 ), .Q(wait_cnt_r_reg__0__0[1]), .R(\wait_cnt_r[3]_i_1__0_n_0 )); FDRE \wait_cnt_r_reg[2] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[2]_i_1__1_n_0 ), .Q(wait_cnt_r_reg__0__0[2]), .R(\wait_cnt_r[3]_i_1__0_n_0 )); FDSE \wait_cnt_r_reg[3] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[3]_i_3__0_n_0 ), .Q(wait_cnt_r_reg__0__0[3]), .S(\wait_cnt_r[3]_i_1__0_n_0 )); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_dqs_found_cal (init_dqsfound_done_r2, init_dqsfound_done_r5, out, pi_dqs_found_any_bank, pi_dqs_found_rank_done, rd_data_offset_cal_done, rst_dqs_find_r1_reg_0, pi_dqs_found_done_r1_reg, \pi_rst_stg1_cal_r_reg[0]_0 , fine_adjust_done_r_reg_0, init_dec_done_reg_0, final_dec_done_reg_0, dqs_found_prech_req, ck_po_stg2_f_indec, ck_po_stg2_f_en, \pi_dqs_found_all_bank_r_reg[1]_0 , D_po_fine_enable107_out, D_po_fine_inc113_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \gen_byte_sel_div1.calib_in_common_reg , \po_counter_read_val_reg[8]_5 , \po_counter_read_val_reg[8]_6 , ififo_rst_reg, \po_counter_read_val_reg[8]_7 , \po_counter_read_val_reg[8]_8 , ififo_rst_reg_0, \po_counter_read_val_reg[8]_9 , \po_counter_read_val_reg[8]_10 , ififo_rst_reg_1, \po_counter_read_val_reg[8]_11 , \po_counter_read_val_reg[8]_12 , ififo_rst_reg_2, fine_adj_state_r144_out, \FSM_sequential_fine_adj_state_r_reg[2]_0 , \dec_cnt_reg[0]_0 , \FSM_sequential_fine_adj_state_r_reg[0]_0 , \rd_byte_data_offset_reg[0][9]_0 , \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[5] , \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \rd_byte_data_offset_reg[0]_3 , p_1_in27_in, \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 , p_1_in50_in, \pi_rst_stg1_cal_r_reg[0]_1 , fine_adj_state_r16_out, dqs_found_prech_req_reg_0, final_dec_done_reg_1, \FSM_sequential_fine_adj_state_r_reg[0]_1 , \rank_final_loop[0].final_do_max_reg[0][3]_0 , \rank_final_loop[0].final_do_max_reg[0][3]_1 , \init_state_r_reg[1] , \init_state_r_reg[2] , \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] , \init_state_r_reg[1]_0 , \init_state_r_reg[1]_1 , \calib_data_offset_0_reg[5] , \calib_data_offset_0_reg[4] , \calib_data_offset_0_reg[1] , \calib_data_offset_0_reg[0] , \calib_data_offset_1_reg[5] , \calib_data_offset_1_reg[4] , \calib_data_offset_1_reg[1] , \calib_data_offset_1_reg[0] , \gen_byte_sel_div1.ctl_lane_sel_reg[0] , ctl_lane_sel, \gen_byte_sel_div1.ctl_lane_sel_reg[1] , \gen_byte_sel_div1.ctl_lane_sel_reg[2] , \calib_zero_inputs_reg[1] , D, \calib_zero_inputs_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[0] , rank_done_r_reg_0, rst_dqs_find_reg_0, dqs_found_prech_req_reg_1, rst_dqs_find_reg_1, init_dec_done_reg_1, rst_dqs_find, CLK, in0, pi_dqs_found_start_reg, rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__2, \pi_dqs_found_lanes_r3_reg[3]_0 , \pi_dqs_found_all_bank_r_reg[1]_1 , init_dqsfound_done_r_reg_0, rstdiv0_sync_r1_reg_rep__13, \FSM_sequential_fine_adj_state_r_reg[0]_2 , \FSM_sequential_fine_adj_state_r_reg[1]_0 , \FSM_sequential_fine_adj_state_r_reg[0]_3 , init_dec_done_reg_2, \FSM_sequential_fine_adj_state_r_reg[1]_1 , \FSM_sequential_fine_adj_state_r_reg[2]_1 , \FSM_sequential_fine_adj_state_r_reg[1]_2 , \FSM_sequential_fine_adj_state_r_reg[1]_3 , pi_dqs_found_start_reg_0, Q, calib_in_common, po_enstg2_f, \calib_zero_inputs_reg[1]_0 , po_stg2_fincdec, pi_calib_done, oclkdelay_calib_done_r_reg, pi_f_inc_reg, \gen_byte_sel_div1.calib_in_common_reg_0 , dqs_po_stg2_f_incdec, po_stg23_incdec, dqs_po_en_stg2_f, po_en_stg2_f, po_en_stg23, \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , \gen_byte_sel_div1.calib_in_common_reg_3 , wrcal_done_reg, rdlvl_stg1_done_int_reg, prbs_rdlvl_done_reg_rep, sent_col, rstdiv0_sync_r1_reg_rep__24, detect_pi_found_dqs, \num_refresh_reg[1] , oclkdelay_calib_done_r_reg_0, mpr_rdlvl_done_r_reg, cnt_cmd_done_r, prbs_last_byte_done_r, wrlvl_byte_redo, wrlvl_done_r1, oclkdelay_center_calib_done_r_reg, wrlvl_final_mux, pi_dqs_found_done_r1, ck_addr_cmd_delay_done, ctl_lane_cnt, \gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 , \gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 , \gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 , pi_fine_dly_dec_done, dqs_po_dec_done, tempmon_sel_pi_incdec, byte_sel_cnt, \gen_byte_sel_div1.byte_sel_cnt_reg[1] , init_calib_complete_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 , cmd_delay_start0, rstdiv0_sync_r1_reg_rep__25, fine_adjust_reg_0, rstdiv0_sync_r1_reg_rep__19, prech_done); output init_dqsfound_done_r2; output init_dqsfound_done_r5; output [3:0]out; output [0:0]pi_dqs_found_any_bank; output pi_dqs_found_rank_done; output rd_data_offset_cal_done; output rst_dqs_find_r1_reg_0; output pi_dqs_found_done_r1_reg; output \pi_rst_stg1_cal_r_reg[0]_0 ; output fine_adjust_done_r_reg_0; output init_dec_done_reg_0; output final_dec_done_reg_0; output dqs_found_prech_req; output ck_po_stg2_f_indec; output ck_po_stg2_f_en; output [0:0]\pi_dqs_found_all_bank_r_reg[1]_0 ; output D_po_fine_enable107_out; output D_po_fine_inc113_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \gen_byte_sel_div1.calib_in_common_reg ; output \po_counter_read_val_reg[8]_5 ; output \po_counter_read_val_reg[8]_6 ; output ififo_rst_reg; output \po_counter_read_val_reg[8]_7 ; output \po_counter_read_val_reg[8]_8 ; output ififo_rst_reg_0; output \po_counter_read_val_reg[8]_9 ; output \po_counter_read_val_reg[8]_10 ; output ififo_rst_reg_1; output \po_counter_read_val_reg[8]_11 ; output \po_counter_read_val_reg[8]_12 ; output ififo_rst_reg_2; output fine_adj_state_r144_out; output \FSM_sequential_fine_adj_state_r_reg[2]_0 ; output \dec_cnt_reg[0]_0 ; output [3:0]\FSM_sequential_fine_adj_state_r_reg[0]_0 ; output [1:0]\rd_byte_data_offset_reg[0][9]_0 ; output \cmd_pipe_plus.mc_data_offset_reg[3] ; output [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; output \cmd_pipe_plus.mc_data_offset_reg[4] ; output \cmd_pipe_plus.mc_data_offset_reg[2] ; output \cmd_pipe_plus.mc_data_offset_reg[1] ; output \cmd_pipe_plus.mc_data_offset_1_reg[3] ; output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; output \cmd_pipe_plus.mc_data_offset_1_reg[4] ; output \cmd_pipe_plus.mc_data_offset_1_reg[2] ; output \cmd_pipe_plus.mc_data_offset_1_reg[1] ; output \cmd_pipe_plus.mc_data_offset_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \rd_byte_data_offset_reg[0]_3 ; output p_1_in27_in; output [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ; output p_1_in50_in; output \pi_rst_stg1_cal_r_reg[0]_1 ; output fine_adj_state_r16_out; output dqs_found_prech_req_reg_0; output final_dec_done_reg_1; output \FSM_sequential_fine_adj_state_r_reg[0]_1 ; output [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_0 ; output [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_1 ; output \init_state_r_reg[1] ; output \init_state_r_reg[2] ; output \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; output \init_state_r_reg[1]_0 ; output \init_state_r_reg[1]_1 ; output \calib_data_offset_0_reg[5] ; output \calib_data_offset_0_reg[4] ; output \calib_data_offset_0_reg[1] ; output \calib_data_offset_0_reg[0] ; output \calib_data_offset_1_reg[5] ; output \calib_data_offset_1_reg[4] ; output \calib_data_offset_1_reg[1] ; output \calib_data_offset_1_reg[0] ; output \gen_byte_sel_div1.ctl_lane_sel_reg[0] ; output ctl_lane_sel; output \gen_byte_sel_div1.ctl_lane_sel_reg[1] ; output \gen_byte_sel_div1.ctl_lane_sel_reg[2] ; output \calib_zero_inputs_reg[1] ; output [1:0]D; output [0:0]\calib_zero_inputs_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output [1:0]rank_done_r_reg_0; output rst_dqs_find_reg_0; output dqs_found_prech_req_reg_1; output rst_dqs_find_reg_1; output init_dec_done_reg_1; output rst_dqs_find; input CLK; input [3:0]in0; input pi_dqs_found_start_reg; input rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__2; input \pi_dqs_found_lanes_r3_reg[3]_0 ; input \pi_dqs_found_all_bank_r_reg[1]_1 ; input init_dqsfound_done_r_reg_0; input rstdiv0_sync_r1_reg_rep__13; input \FSM_sequential_fine_adj_state_r_reg[0]_2 ; input \FSM_sequential_fine_adj_state_r_reg[1]_0 ; input \FSM_sequential_fine_adj_state_r_reg[0]_3 ; input init_dec_done_reg_2; input \FSM_sequential_fine_adj_state_r_reg[1]_1 ; input \FSM_sequential_fine_adj_state_r_reg[2]_1 ; input \FSM_sequential_fine_adj_state_r_reg[1]_2 ; input \FSM_sequential_fine_adj_state_r_reg[1]_3 ; input pi_dqs_found_start_reg_0; input [1:0]Q; input calib_in_common; input [0:0]po_enstg2_f; input [1:0]\calib_zero_inputs_reg[1]_0 ; input [0:0]po_stg2_fincdec; input pi_calib_done; input oclkdelay_calib_done_r_reg; input pi_f_inc_reg; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input dqs_po_stg2_f_incdec; input po_stg23_incdec; input dqs_po_en_stg2_f; input po_en_stg2_f; input po_en_stg23; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input wrcal_done_reg; input rdlvl_stg1_done_int_reg; input prbs_rdlvl_done_reg_rep; input sent_col; input rstdiv0_sync_r1_reg_rep__24; input detect_pi_found_dqs; input \num_refresh_reg[1] ; input oclkdelay_calib_done_r_reg_0; input mpr_rdlvl_done_r_reg; input cnt_cmd_done_r; input prbs_last_byte_done_r; input wrlvl_byte_redo; input wrlvl_done_r1; input oclkdelay_center_calib_done_r_reg; input wrlvl_final_mux; input pi_dqs_found_done_r1; input ck_addr_cmd_delay_done; input [2:0]ctl_lane_cnt; input \gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ; input \gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ; input \gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ; input pi_fine_dly_dec_done; input dqs_po_dec_done; input tempmon_sel_pi_incdec; input [0:0]byte_sel_cnt; input \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; input init_calib_complete_reg; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; input cmd_delay_start0; input rstdiv0_sync_r1_reg_rep__25; input fine_adjust_reg_0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input prech_done; wire CLK; wire [1:0]D; wire D_po_fine_enable107_out; wire D_po_fine_inc113_out; wire \FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ; wire \FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ; wire \FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ; wire \FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ; wire \FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ; (* RTL_KEEP = "yes" *) wire [3:0]\FSM_sequential_fine_adj_state_r_reg[0]_0 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_1 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_2 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_3 ; wire \FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_0 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_1 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_2 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_3 ; wire \FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ; wire \FSM_sequential_fine_adj_state_r_reg[2]_0 ; wire \FSM_sequential_fine_adj_state_r_reg[2]_1 ; wire [1:0]Q; wire [0:0]byte_sel_cnt; wire \calib_data_offset_0_reg[0] ; wire \calib_data_offset_0_reg[1] ; wire \calib_data_offset_0_reg[4] ; wire \calib_data_offset_0_reg[5] ; wire \calib_data_offset_1_reg[0] ; wire \calib_data_offset_1_reg[1] ; wire \calib_data_offset_1_reg[4] ; wire \calib_data_offset_1_reg[5] ; wire calib_in_common; wire [0:0]\calib_zero_inputs_reg[0] ; wire \calib_zero_inputs_reg[1] ; wire [1:0]\calib_zero_inputs_reg[1]_0 ; wire ck_addr_cmd_delay_done; wire ck_po_stg2_f_en; wire ck_po_stg2_f_indec; wire cmd_delay_start0; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; wire cnt_cmd_done_r; wire [2:0]ctl_lane_cnt; wire ctl_lane_cnt_0; wire [3:0]ctl_lane_cnt__0; wire \ctl_lane_cnt_reg_n_0_[3] ; wire ctl_lane_sel; wire [5:0]dec_cnt; wire \dec_cnt[0]_i_2_n_0 ; wire \dec_cnt[0]_i_4_n_0 ; wire \dec_cnt[0]_i_5_n_0 ; wire \dec_cnt[0]_i_6_n_0 ; wire \dec_cnt[0]_i_7_n_0 ; wire \dec_cnt[1]_i_2_n_0 ; wire \dec_cnt[1]_i_3_n_0 ; wire \dec_cnt[1]_i_4_n_0 ; wire \dec_cnt[2]_i_2_n_0 ; wire \dec_cnt[2]_i_3_n_0 ; wire \dec_cnt[2]_i_4_n_0 ; wire \dec_cnt[3]_i_2_n_0 ; wire \dec_cnt[3]_i_3_n_0 ; wire \dec_cnt[3]_i_4_n_0 ; wire \dec_cnt[4]_i_2_n_0 ; wire \dec_cnt[4]_i_3_n_0 ; wire \dec_cnt[4]_i_5_n_0 ; wire \dec_cnt[4]_i_6_n_0 ; wire \dec_cnt[4]_i_7_n_0 ; wire \dec_cnt[5]_i_10_n_0 ; wire \dec_cnt[5]_i_1_n_0 ; wire \dec_cnt[5]_i_3_n_0 ; wire \dec_cnt[5]_i_4_n_0 ; wire \dec_cnt[5]_i_6_n_0 ; wire \dec_cnt[5]_i_7_n_0 ; wire \dec_cnt[5]_i_8_n_0 ; wire \dec_cnt[5]_i_9_n_0 ; wire \dec_cnt_reg[0]_0 ; wire \dec_cnt_reg[0]_i_3_n_0 ; wire \dec_cnt_reg[0]_i_3_n_1 ; wire \dec_cnt_reg[0]_i_3_n_2 ; wire \dec_cnt_reg[0]_i_3_n_3 ; wire \dec_cnt_reg[0]_i_3_n_4 ; wire \dec_cnt_reg[0]_i_3_n_5 ; wire \dec_cnt_reg[0]_i_3_n_6 ; wire \dec_cnt_reg[4]_i_4_n_3 ; wire \dec_cnt_reg[4]_i_4_n_6 ; wire \dec_cnt_reg[4]_i_4_n_7 ; wire \dec_cnt_reg_n_0_[0] ; wire \dec_cnt_reg_n_0_[1] ; wire \dec_cnt_reg_n_0_[2] ; wire \dec_cnt_reg_n_0_[3] ; wire \dec_cnt_reg_n_0_[4] ; wire \dec_cnt_reg_n_0_[5] ; wire detect_pi_found_dqs; wire detect_rd_cnt0; wire [3:0]detect_rd_cnt0__0; wire \detect_rd_cnt[1]_i_1_n_0 ; wire \detect_rd_cnt[3]_i_1_n_0 ; wire [3:0]detect_rd_cnt_reg__0; wire dqs_found_done_r0; wire dqs_found_done_r_i_3_n_0; wire dqs_found_prech_req; wire dqs_found_prech_req_i_5_n_0; wire dqs_found_prech_req_reg_0; wire dqs_found_prech_req_reg_1; wire dqs_found_start_r; wire dqs_po_dec_done; wire dqs_po_en_stg2_f; wire dqs_po_stg2_f_incdec; wire final_data_offset; wire final_data_offset_mc; wire final_dec_done_reg_0; wire final_dec_done_reg_1; wire fine_adj_state_r110_out; wire fine_adj_state_r134_out; wire fine_adj_state_r141_out; wire fine_adj_state_r144_out; wire fine_adj_state_r167_out; wire fine_adj_state_r16_out; wire fine_adj_state_r17_out; wire fine_adjust_done_r_reg_0; wire [2:0]fine_adjust_lane_cnt; wire fine_adjust_reg_0; wire first_fail_detect; wire first_fail_detect_i_1_n_0; wire first_fail_detect_i_2_n_0; wire first_fail_detect_reg_n_0; wire \first_fail_taps[0]_i_1_n_0 ; wire \first_fail_taps[1]_i_1_n_0 ; wire \first_fail_taps[2]_i_1_n_0 ; wire \first_fail_taps[3]_i_1_n_0 ; wire \first_fail_taps[4]_i_1_n_0 ; wire \first_fail_taps[5]_i_2_n_0 ; wire \first_fail_taps[5]_i_4_n_0 ; wire \first_fail_taps[5]_i_5_n_0 ; wire \first_fail_taps[5]_i_6_n_0 ; wire \first_fail_taps[5]_i_7_n_0 ; wire \first_fail_taps_reg_n_0_[0] ; wire \first_fail_taps_reg_n_0_[1] ; wire \first_fail_taps_reg_n_0_[2] ; wire \first_fail_taps_reg_n_0_[3] ; wire \first_fail_taps_reg_n_0_[4] ; wire \first_fail_taps_reg_n_0_[5] ; wire \gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.calib_in_common_i_2_n_0 ; wire \gen_byte_sel_div1.calib_in_common_i_5_n_0 ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[0] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[1] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[2] ; wire \gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ; wire ififo_rst_reg; wire ififo_rst_reg_0; wire ififo_rst_reg_1; wire ififo_rst_reg_2; wire [3:0]in0; wire inc_cnt; wire \inc_cnt[4]_i_1_n_0 ; wire \inc_cnt_reg_n_0_[0] ; wire \inc_cnt_reg_n_0_[1] ; wire \inc_cnt_reg_n_0_[2] ; wire \inc_cnt_reg_n_0_[3] ; wire \inc_cnt_reg_n_0_[4] ; wire \inc_cnt_reg_n_0_[5] ; wire init_calib_complete_reg; wire init_dec_cnt; wire [5:0]init_dec_cnt0; wire \init_dec_cnt[1]_i_1_n_0 ; wire [5:0]init_dec_cnt_reg__0; wire init_dec_done_reg_0; wire init_dec_done_reg_1; wire init_dec_done_reg_2; wire init_dqsfound_done_r1_reg_n_0; wire init_dqsfound_done_r2; wire init_dqsfound_done_r4_reg_srl2_n_0; wire init_dqsfound_done_r5; wire init_dqsfound_done_r_reg_0; wire \init_state_r[1]_i_29_n_0 ; wire \init_state_r[1]_i_30_n_0 ; wire \init_state_r_reg[1] ; wire \init_state_r_reg[1]_0 ; wire \init_state_r_reg[1]_1 ; wire \init_state_r_reg[2] ; wire mpr_rdlvl_done_r_reg; wire n_0_0; wire n_0_1; wire n_0_2; wire n_0_3; wire \num_refresh_reg[1] ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_center_calib_done_r_reg; wire [5:0]p_0_in; wire p_0_in19_in; wire [5:0]p_0_in__0; wire [4:0]p_0_in__1; wire [5:0]p_1_in; wire p_1_in27_in; wire p_1_in50_in; wire p_22_out; wire pi_calib_done; wire [0:0]pi_dqs_found_all_bank; wire \pi_dqs_found_all_bank[0]_i_1_n_0 ; wire [0:0]\pi_dqs_found_all_bank_r_reg[1]_0 ; wire \pi_dqs_found_all_bank_r_reg[1]_1 ; wire [0:0]pi_dqs_found_any_bank; wire \pi_dqs_found_any_bank_r_reg_n_0_[0] ; wire pi_dqs_found_done_r1; wire pi_dqs_found_done_r1_reg; (* async_reg = "true" *) wire [7:0]pi_dqs_found_lanes_r1; (* async_reg = "true" *) wire [7:0]pi_dqs_found_lanes_r2; (* async_reg = "true" *) wire [7:0]pi_dqs_found_lanes_r3; wire \pi_dqs_found_lanes_r3_reg[3]_0 ; wire pi_dqs_found_rank_done; wire pi_dqs_found_start_reg; wire pi_dqs_found_start_reg_0; wire pi_f_inc_reg; wire pi_fine_dly_dec_done; wire \pi_rst_stg1_cal[0]_i_1_n_0 ; wire \pi_rst_stg1_cal[1]_i_1_n_0 ; wire pi_rst_stg1_cal_r1_reg0; wire pi_rst_stg1_cal_r1_reg017_out; wire \pi_rst_stg1_cal_r1_reg_n_0_[0] ; wire \pi_rst_stg1_cal_r[0]_i_1_n_0 ; wire \pi_rst_stg1_cal_r[0]_i_2_n_0 ; wire \pi_rst_stg1_cal_r[0]_i_3_n_0 ; wire \pi_rst_stg1_cal_r[1]_i_1_n_0 ; wire \pi_rst_stg1_cal_r[1]_i_2_n_0 ; wire \pi_rst_stg1_cal_r_reg[0]_0 ; wire \pi_rst_stg1_cal_r_reg[0]_1 ; wire \pi_rst_stg1_cal_reg_n_0_[1] ; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_10 ; wire \po_counter_read_val_reg[8]_11 ; wire \po_counter_read_val_reg[8]_12 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire \po_counter_read_val_reg[8]_6 ; wire \po_counter_read_val_reg[8]_7 ; wire \po_counter_read_val_reg[8]_8 ; wire \po_counter_read_val_reg[8]_9 ; wire po_en_stg23; wire po_en_stg2_f; wire [0:0]po_enstg2_f; wire po_stg23_incdec; wire [0:0]po_stg2_fincdec; wire prbs_last_byte_done_r; wire prbs_rdlvl_done_reg_rep; wire prech_done; wire rank_done_r1; wire [1:0]rank_done_r_reg_0; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ; wire [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ; wire \rank_final_loop[0].final_do_index_reg_n_0_[0][0] ; wire \rank_final_loop[0].final_do_index_reg_n_0_[0][1] ; wire \rank_final_loop[0].final_do_index_reg_n_0_[0][2] ; wire \rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ; wire \rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ; wire \rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ; wire \rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ; wire [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_0 ; wire [1:0]\rank_final_loop[0].final_do_max_reg[0][3]_1 ; wire [5:0]\rank_final_loop[0].final_do_max_reg[0]__0 ; wire rd_byte_data_offset; wire \rd_byte_data_offset[0][11]_i_1_n_0 ; wire \rd_byte_data_offset[0][11]_i_2_n_0 ; wire \rd_byte_data_offset[0][11]_i_4_n_0 ; wire \rd_byte_data_offset[0][5]_i_1_n_0 ; wire \rd_byte_data_offset[0][5]_i_3_n_0 ; wire \rd_byte_data_offset[0][5]_i_4_n_0 ; wire \rd_byte_data_offset[0][7]_i_1_n_0 ; wire [1:0]\rd_byte_data_offset_reg[0][9]_0 ; wire \rd_byte_data_offset_reg[0]_3 ; wire \rd_byte_data_offset_reg_n_0_[0][0] ; wire \rd_byte_data_offset_reg_n_0_[0][1] ; wire \rd_byte_data_offset_reg_n_0_[0][4] ; wire \rd_byte_data_offset_reg_n_0_[0][5] ; wire rd_data_offset_cal_done; wire [5:0]rd_data_offset_ranks_0; wire [5:0]rd_data_offset_ranks_1; wire rdlvl_stg1_done_int_reg; wire \rnk_cnt_r[0]_i_1_n_0 ; wire \rnk_cnt_r[1]_i_1_n_0 ; wire \rnk_cnt_r_reg_n_0_[0] ; wire \rnk_cnt_r_reg_n_0_[1] ; wire rst_dqs_find; wire rst_dqs_find_i_5_n_0; wire rst_dqs_find_i_6_n_0; wire rst_dqs_find_r1; wire rst_dqs_find_r1_reg_0; wire rst_dqs_find_r2; wire rst_dqs_find_reg_0; wire rst_dqs_find_reg_1; wire [0:0]rst_stg1_cal; wire rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__25; wire sent_col; wire stable_pass_cnt; wire \stable_pass_cnt[3]_i_1_n_0 ; wire \stable_pass_cnt[5]_i_2_n_0 ; wire \stable_pass_cnt[5]_i_3_n_0 ; wire [5:1]stable_pass_cnt_reg__0; wire \stable_pass_cnt_reg_n_0_[0] ; wire tempmon_sel_pi_incdec; wire wrcal_done_reg; wire wrlvl_byte_redo; wire wrlvl_done_r1; wire wrlvl_final_mux; wire [0:0]\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED ; wire [3:1]\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED ; wire [3:2]\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED ; assign out[3:0] = pi_dqs_found_lanes_r3[3:0]; LUT6 #( .INIT(64'hF3B0FFFFF3B00000)) \FSM_sequential_fine_adj_state_r[0]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ), .O(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair271" *) LUT4 #( .INIT(16'h0008)) \FSM_sequential_fine_adj_state_r[0]_i_2 (.I0(fine_adjust_lane_cnt[1]), .I1(fine_adjust_lane_cnt[0]), .I2(\ctl_lane_cnt_reg_n_0_[3] ), .I3(fine_adjust_lane_cnt[2]), .O(\FSM_sequential_fine_adj_state_r_reg[0]_1 )); LUT5 #( .INIT(32'hA8AAFFFF)) \FSM_sequential_fine_adj_state_r[0]_i_4 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I1(\dec_cnt_reg[0]_0 ), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 )); LUT5 #( .INIT(32'hCCCC7477)) \FSM_sequential_fine_adj_state_r[0]_i_5 (.I0(fine_adj_state_r167_out), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(final_dec_done_reg_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFAFF0AFF030F030)) \FSM_sequential_fine_adj_state_r[1]_i_2 (.I0(fine_adj_state_r167_out), .I1(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FFEA00EA)) \FSM_sequential_fine_adj_state_r[1]_i_3 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I1(pi_dqs_found_all_bank), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair269" *) LUT5 #( .INIT(32'h00000040)) \FSM_sequential_fine_adj_state_r[1]_i_4 (.I0(detect_rd_cnt_reg__0[1]), .I1(detect_rd_cnt_reg__0[0]), .I2(detect_pi_found_dqs), .I3(detect_rd_cnt_reg__0[2]), .I4(detect_rd_cnt_reg__0[3]), .O(fine_adj_state_r167_out)); LUT6 #( .INIT(64'h0000000000001000)) \FSM_sequential_fine_adj_state_r[1]_i_5 (.I0(fine_adjust_lane_cnt[2]), .I1(\ctl_lane_cnt_reg_n_0_[3] ), .I2(fine_adjust_lane_cnt[0]), .I3(fine_adjust_lane_cnt[1]), .I4(\dec_cnt_reg[0]_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .O(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h0033CCBB33FFFC00)) \FSM_sequential_fine_adj_state_r[2]_i_1 (.I0(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hC8FF40FF88FF0000)) \FSM_sequential_fine_adj_state_r[2]_i_2 (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I1(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ), .I2(fine_adj_state_r134_out), .I3(fine_adj_state_r144_out), .I4(fine_adj_state_r110_out), .I5(fine_adj_state_r17_out), .O(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 )); LUT3 #( .INIT(8'h8F)) \FSM_sequential_fine_adj_state_r[2]_i_3 (.I0(\first_fail_taps[5]_i_5_n_0 ), .I1(\first_fail_taps[5]_i_7_n_0 ), .I2(first_fail_detect_reg_n_0), .O(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 )); LUT3 #( .INIT(8'h54)) \FSM_sequential_fine_adj_state_r[2]_i_4 (.I0(fine_adj_state_r141_out), .I1(first_fail_detect_i_2_n_0), .I2(first_fail_detect_reg_n_0), .O(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 )); LUT5 #( .INIT(32'h0000BF00)) \FSM_sequential_fine_adj_state_r[2]_i_5 (.I0(\first_fail_taps[5]_i_6_n_0 ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[4] ), .I3(\first_fail_taps[5]_i_5_n_0 ), .I4(\first_fail_taps[5]_i_7_n_0 ), .O(fine_adj_state_r134_out)); LUT6 #( .INIT(64'h0000000000101000)) \FSM_sequential_fine_adj_state_r[2]_i_6 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[3] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[5] ), .O(fine_adj_state_r110_out)); LUT6 #( .INIT(64'h0000008000000028)) \FSM_sequential_fine_adj_state_r[2]_i_7 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[4] ), .I2(\inc_cnt_reg_n_0_[2] ), .I3(\inc_cnt_reg_n_0_[0] ), .I4(\inc_cnt_reg_n_0_[1] ), .I5(\inc_cnt_reg_n_0_[3] ), .O(fine_adj_state_r17_out)); LUT5 #( .INIT(32'hB8FFB800)) \FSM_sequential_fine_adj_state_r[3]_i_1 (.I0(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I4(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ), .O(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h33BBFF88CC003000)) \FSM_sequential_fine_adj_state_r[3]_i_2 (.I0(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I2(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hBFBFBFBFFFFCFCFC)) \FSM_sequential_fine_adj_state_r[3]_i_3 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(pi_dqs_found_all_bank), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'hBFBFBFBFCFCCCCCC)) \FSM_sequential_fine_adj_state_r[3]_i_4 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(pi_dqs_found_all_bank), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFF4FFFFFFF40)) \FSM_sequential_fine_adj_state_r[3]_i_5 (.I0(pi_dqs_found_any_bank), .I1(rst_dqs_find_r2), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(init_dqsfound_done_r5), .O(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 )); LUT5 #( .INIT(32'h0000FD0D)) \FSM_sequential_fine_adj_state_r[3]_i_6 (.I0(first_fail_detect_i_2_n_0), .I1(fine_adj_state_r16_out), .I2(fine_adj_state_r144_out), .I3(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_fine_adj_state_r[3]_i_7 (.I0(init_dec_cnt_reg__0[5]), .I1(init_dec_cnt_reg__0[3]), .I2(init_dec_cnt_reg__0[0]), .I3(init_dec_cnt_reg__0[1]), .I4(init_dec_cnt_reg__0[2]), .I5(init_dec_cnt_reg__0[4]), .O(\FSM_sequential_fine_adj_state_r_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFB8FFFFFFBB)) \FSM_sequential_fine_adj_state_r[3]_i_8 (.I0(fine_adj_state_r110_out), .I1(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I2(fine_adj_state_r17_out), .I3(fine_adj_state_r141_out), .I4(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ), .I5(fine_adj_state_r134_out), .O(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 )); LUT2 #( .INIT(4'h1)) \FSM_sequential_fine_adj_state_r[3]_i_9 (.I0(first_fail_detect_reg_n_0), .I1(first_fail_detect_i_2_n_0), .O(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 )); (* KEEP = "yes" *) FDRE \FSM_sequential_fine_adj_state_r_reg[0] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_fine_adj_state_r_reg[0]_i_3 (.I0(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ), .I1(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ), .O(\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ), .S(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0])); (* KEEP = "yes" *) FDRE \FSM_sequential_fine_adj_state_r_reg[1] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_fine_adj_state_r_reg[1]_i_1 (.I0(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ), .I1(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ), .O(\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ), .S(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1])); (* KEEP = "yes" *) FDRE \FSM_sequential_fine_adj_state_r_reg[2] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__19)); (* KEEP = "yes" *) FDRE \FSM_sequential_fine_adj_state_r_reg[3] (.C(CLK), .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ), .D(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ), .Q(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .R(rstdiv0_sync_r1_reg_rep__19)); (* SOFT_HLUTNM = "soft_lutpair296" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[0]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[0]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\calib_data_offset_0_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair295" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[1]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[1]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][1] ), .O(\calib_data_offset_0_reg[1] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[4]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[4]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][4] ), .O(\calib_data_offset_0_reg[4] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_0[5]_i_2 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_0[5]), .I2(init_dqsfound_done_r2), .I3(\rd_byte_data_offset_reg_n_0_[0][5] ), .O(\calib_data_offset_0_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair298" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[0]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[0]), .I2(init_dqsfound_done_r2), .I3(p_0_in[0]), .O(\calib_data_offset_1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair294" *) LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[1]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[1]), .I2(init_dqsfound_done_r2), .I3(p_0_in[1]), .O(\calib_data_offset_1_reg[1] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[4]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[4]), .I2(init_dqsfound_done_r2), .I3(p_0_in[4]), .O(\calib_data_offset_1_reg[4] )); LUT4 #( .INIT(16'hCDC8)) \calib_data_offset_1[5]_i_1 (.I0(pi_dqs_found_done_r1), .I1(rd_data_offset_ranks_1[5]), .I2(init_dqsfound_done_r2), .I3(p_0_in[5]), .O(\calib_data_offset_1_reg[5] )); LUT6 #( .INIT(64'h4040404F00000000)) \calib_sel[0]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ), .I1(\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ), .I2(ctl_lane_sel), .I3(byte_sel_cnt), .I4(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ), .I5(init_calib_complete_reg), .O(D[0])); LUT6 #( .INIT(64'h4040404F00000000)) \calib_sel[1]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ), .I1(\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ), .I2(ctl_lane_sel), .I3(byte_sel_cnt), .I4(\gen_byte_sel_div1.byte_sel_cnt_reg[1] ), .I5(init_calib_complete_reg), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair283" *) LUT5 #( .INIT(32'h08008888)) \calib_sel[3]_i_2 (.I0(dqs_po_dec_done), .I1(pi_fine_dly_dec_done), .I2(fine_adjust_done_r_reg_0), .I3(rd_data_offset_cal_done), .I4(ck_addr_cmd_delay_done), .O(ctl_lane_sel)); (* SOFT_HLUTNM = "soft_lutpair290" *) LUT4 #( .INIT(16'h10FF)) \calib_zero_inputs[0]_i_1 (.I0(rst_stg1_cal), .I1(\pi_rst_stg1_cal_reg_n_0_[1] ), .I2(ctl_lane_sel), .I3(init_calib_complete_reg), .O(\calib_zero_inputs_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair283" *) LUT3 #( .INIT(8'hA2)) \calib_zero_inputs[1]_i_2 (.I0(ck_addr_cmd_delay_done), .I1(rd_data_offset_cal_done), .I2(fine_adjust_done_r_reg_0), .O(\calib_zero_inputs_reg[1] )); FDRE ck_po_stg2_f_en_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_3 ), .Q(ck_po_stg2_f_en), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE ck_po_stg2_f_indec_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_2 ), .Q(ck_po_stg2_f_indec), .R(rstdiv0_sync_r1_reg_rep__12)); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_data_offset[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .O(\cmd_pipe_plus.mc_data_offset_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair284" *) LUT2 #( .INIT(4'h6)) \cmd_pipe_plus.mc_data_offset[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .I1(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .O(\cmd_pipe_plus.mc_data_offset_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair287" *) LUT4 #( .INIT(16'h2A80)) \cmd_pipe_plus.mc_data_offset[2]_i_1 (.I0(sent_col), .I1(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .I2(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .I3(\cmd_pipe_plus.mc_data_offset_reg[5] [2]), .O(\cmd_pipe_plus.mc_data_offset_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair287" *) LUT5 #( .INIT(32'h2AAA8000)) \cmd_pipe_plus.mc_data_offset[3]_i_1 (.I0(sent_col), .I1(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .I2(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .I3(\cmd_pipe_plus.mc_data_offset_reg[5] [2]), .I4(\cmd_pipe_plus.mc_data_offset_reg[5] [3]), .O(\cmd_pipe_plus.mc_data_offset_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair284" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cmd_pipe_plus.mc_data_offset[4]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] [4]), .I1(\cmd_pipe_plus.mc_data_offset_reg[5] [3]), .I2(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .I3(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .I4(\cmd_pipe_plus.mc_data_offset_reg[5] [2]), .O(\cmd_pipe_plus.mc_data_offset_reg[4] )); LUT1 #( .INIT(2'h1)) \cmd_pipe_plus.mc_data_offset_1[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair280" *) LUT2 #( .INIT(4'h6)) \cmd_pipe_plus.mc_data_offset_1[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair282" *) LUT4 #( .INIT(16'h2A80)) \cmd_pipe_plus.mc_data_offset_1[2]_i_1 (.I0(sent_col), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .I2(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .I3(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair282" *) LUT5 #( .INIT(32'h2AAA8000)) \cmd_pipe_plus.mc_data_offset_1[3]_i_1 (.I0(sent_col), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .I2(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .I3(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .I4(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair280" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cmd_pipe_plus.mc_data_offset_1[4]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .I2(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .I3(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .I4(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .O(\cmd_pipe_plus.mc_data_offset_1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair303" *) LUT1 #( .INIT(2'h1)) \ctl_lane_cnt[0]_i_1__0 (.I0(fine_adjust_lane_cnt[0]), .O(ctl_lane_cnt__0[0])); (* SOFT_HLUTNM = "soft_lutpair303" *) LUT2 #( .INIT(4'h6)) \ctl_lane_cnt[1]_i_1__0 (.I0(fine_adjust_lane_cnt[0]), .I1(fine_adjust_lane_cnt[1]), .O(ctl_lane_cnt__0[1])); (* SOFT_HLUTNM = "soft_lutpair293" *) LUT4 #( .INIT(16'h4AAA)) \ctl_lane_cnt[2]_i_1__0 (.I0(fine_adjust_lane_cnt[2]), .I1(\ctl_lane_cnt_reg_n_0_[3] ), .I2(fine_adjust_lane_cnt[0]), .I3(fine_adjust_lane_cnt[1]), .O(ctl_lane_cnt__0[2])); LUT4 #( .INIT(16'h2040)) \ctl_lane_cnt[3]_i_1__0 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(ctl_lane_cnt_0)); (* SOFT_HLUTNM = "soft_lutpair293" *) LUT4 #( .INIT(16'h6AAA)) \ctl_lane_cnt[3]_i_2__0 (.I0(\ctl_lane_cnt_reg_n_0_[3] ), .I1(fine_adjust_lane_cnt[0]), .I2(fine_adjust_lane_cnt[1]), .I3(fine_adjust_lane_cnt[2]), .O(ctl_lane_cnt__0[3])); FDRE \ctl_lane_cnt_reg[0] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[0]), .Q(fine_adjust_lane_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \ctl_lane_cnt_reg[1] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[1]), .Q(fine_adjust_lane_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \ctl_lane_cnt_reg[2] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[2]), .Q(fine_adjust_lane_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \ctl_lane_cnt_reg[3] (.C(CLK), .CE(ctl_lane_cnt_0), .D(ctl_lane_cnt__0[3]), .Q(\ctl_lane_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__2)); LUT6 #( .INIT(64'h7444744474777444)) \dec_cnt[0]_i_1 (.I0(\dec_cnt_reg_n_0_[0] ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\dec_cnt[0]_i_2_n_0 ), .I3(fine_adj_state_r144_out), .I4(\dec_cnt_reg[0]_i_3_n_6 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(dec_cnt[0])); LUT6 #( .INIT(64'h0000888BFFFF888B)) \dec_cnt[0]_i_2 (.I0(\dec_cnt_reg[0]_i_3_n_6 ), .I1(first_fail_detect_i_2_n_0), .I2(\first_fail_taps_reg_n_0_[1] ), .I3(\first_fail_taps[5]_i_5_n_0 ), .I4(fine_adj_state_r141_out), .I5(\inc_cnt_reg_n_0_[1] ), .O(\dec_cnt[0]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_4 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\first_fail_taps_reg_n_0_[3] ), .O(\dec_cnt[0]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_5 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\first_fail_taps_reg_n_0_[2] ), .O(\dec_cnt[0]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_6 (.I0(\inc_cnt_reg_n_0_[1] ), .I1(\first_fail_taps_reg_n_0_[1] ), .O(\dec_cnt[0]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[0]_i_7 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\first_fail_taps_reg_n_0_[0] ), .O(\dec_cnt[0]_i_7_n_0 )); LUT4 #( .INIT(16'h9F90)) \dec_cnt[1]_i_1 (.I0(\dec_cnt_reg_n_0_[0] ), .I1(\dec_cnt_reg_n_0_[1] ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\dec_cnt[1]_i_2_n_0 ), .O(dec_cnt[1])); LUT6 #( .INIT(64'h08880888FBBB0888)) \dec_cnt[1]_i_2 (.I0(\dec_cnt[1]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(pi_dqs_found_all_bank), .I4(\dec_cnt_reg[0]_i_3_n_5 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(\dec_cnt[1]_i_2_n_0 )); LUT6 #( .INIT(64'h6F606F6F6F606060)) \dec_cnt[1]_i_3 (.I0(\inc_cnt_reg_n_0_[1] ), .I1(\inc_cnt_reg_n_0_[2] ), .I2(fine_adj_state_r141_out), .I3(\dec_cnt_reg[0]_i_3_n_5 ), .I4(first_fail_detect_i_2_n_0), .I5(\dec_cnt[1]_i_4_n_0 ), .O(\dec_cnt[1]_i_3_n_0 )); LUT6 #( .INIT(64'h5555555540000000)) \dec_cnt[1]_i_4 (.I0(\first_fail_taps_reg_n_0_[2] ), .I1(stable_pass_cnt_reg__0[4]), .I2(stable_pass_cnt_reg__0[3]), .I3(stable_pass_cnt_reg__0[2]), .I4(stable_pass_cnt_reg__0[1]), .I5(stable_pass_cnt_reg__0[5]), .O(\dec_cnt[1]_i_4_n_0 )); LUT5 #( .INIT(32'hE1FFE100)) \dec_cnt[2]_i_1 (.I0(\dec_cnt_reg_n_0_[0] ), .I1(\dec_cnt_reg_n_0_[1] ), .I2(\dec_cnt_reg_n_0_[2] ), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\dec_cnt[2]_i_2_n_0 ), .O(dec_cnt[2])); LUT6 #( .INIT(64'h08880888FBBB0888)) \dec_cnt[2]_i_2 (.I0(\dec_cnt[2]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(pi_dqs_found_all_bank), .I4(\dec_cnt_reg[0]_i_3_n_4 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(\dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B888B888B8BB)) \dec_cnt[2]_i_3 (.I0(\dec_cnt[2]_i_4_n_0 ), .I1(fine_adj_state_r141_out), .I2(\dec_cnt_reg[0]_i_3_n_4 ), .I3(first_fail_detect_i_2_n_0), .I4(\first_fail_taps_reg_n_0_[3] ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\dec_cnt[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair300" *) LUT3 #( .INIT(8'h6A)) \dec_cnt[2]_i_4 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[2] ), .O(\dec_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFE01FFFFFE010000)) \dec_cnt[3]_i_1 (.I0(\dec_cnt_reg_n_0_[2] ), .I1(\dec_cnt_reg_n_0_[1] ), .I2(\dec_cnt_reg_n_0_[0] ), .I3(\dec_cnt_reg_n_0_[3] ), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I5(\dec_cnt[3]_i_2_n_0 ), .O(dec_cnt[3])); LUT6 #( .INIT(64'h08880888FBBB0888)) \dec_cnt[3]_i_2 (.I0(\dec_cnt[3]_i_3_n_0 ), .I1(detect_pi_found_dqs), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(pi_dqs_found_all_bank), .I4(\dec_cnt_reg[4]_i_4_n_7 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(\dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B888B888B8BB)) \dec_cnt[3]_i_3 (.I0(\dec_cnt[3]_i_4_n_0 ), .I1(fine_adj_state_r141_out), .I2(\dec_cnt_reg[4]_i_4_n_7 ), .I3(first_fail_detect_i_2_n_0), .I4(\first_fail_taps_reg_n_0_[4] ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\dec_cnt[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair278" *) LUT4 #( .INIT(16'h6AAA)) \dec_cnt[3]_i_4 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[3] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .O(\dec_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'hB888B888B8BBB888)) \dec_cnt[4]_i_1 (.I0(\dec_cnt[4]_i_2_n_0 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(\dec_cnt[4]_i_3_n_0 ), .I3(fine_adj_state_r144_out), .I4(\dec_cnt_reg[4]_i_4_n_6 ), .I5(\dec_cnt[5]_i_9_n_0 ), .O(dec_cnt[4])); (* SOFT_HLUTNM = "soft_lutpair275" *) LUT5 #( .INIT(32'hFFFE0001)) \dec_cnt[4]_i_2 (.I0(\dec_cnt_reg_n_0_[3] ), .I1(\dec_cnt_reg_n_0_[0] ), .I2(\dec_cnt_reg_n_0_[1] ), .I3(\dec_cnt_reg_n_0_[2] ), .I4(\dec_cnt_reg_n_0_[4] ), .O(\dec_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B888B888B8BB)) \dec_cnt[4]_i_3 (.I0(\dec_cnt[4]_i_5_n_0 ), .I1(fine_adj_state_r141_out), .I2(\dec_cnt_reg[4]_i_4_n_6 ), .I3(first_fail_detect_i_2_n_0), .I4(\first_fail_taps_reg_n_0_[5] ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\dec_cnt[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair278" *) LUT5 #( .INIT(32'h6AAAAAAA)) \dec_cnt[4]_i_5 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[4] ), .I2(\inc_cnt_reg_n_0_[2] ), .I3(\inc_cnt_reg_n_0_[1] ), .I4(\inc_cnt_reg_n_0_[3] ), .O(\dec_cnt[4]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[4]_i_6 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\first_fail_taps_reg_n_0_[5] ), .O(\dec_cnt[4]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \dec_cnt[4]_i_7 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\first_fail_taps_reg_n_0_[4] ), .O(\dec_cnt[4]_i_7_n_0 )); LUT6 #( .INIT(64'h0808C80800000000)) \dec_cnt[5]_i_1 (.I0(\dec_cnt[5]_i_3_n_0 ), .I1(\dec_cnt[5]_i_4_n_0 ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\dec_cnt_reg[0]_0 ), .I4(\dec_cnt[5]_i_6_n_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(\dec_cnt[5]_i_1_n_0 )); LUT4 #( .INIT(16'h2220)) \dec_cnt[5]_i_10 (.I0(\first_fail_taps[5]_i_4_n_0 ), .I1(fine_adj_state_r141_out), .I2(first_fail_detect_reg_n_0), .I3(first_fail_detect_i_2_n_0), .O(\dec_cnt[5]_i_10_n_0 )); LUT6 #( .INIT(64'h9F909F9F9F909090)) \dec_cnt[5]_i_2 (.I0(\dec_cnt[5]_i_7_n_0 ), .I1(\dec_cnt_reg_n_0_[5] ), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\dec_cnt[5]_i_8_n_0 ), .I4(fine_adj_state_r144_out), .I5(\dec_cnt[5]_i_9_n_0 ), .O(dec_cnt[5])); LUT6 #( .INIT(64'h0555000035550000)) \dec_cnt[5]_i_3 (.I0(\dec_cnt[5]_i_10_n_0 ), .I1(fine_adj_state_r16_out), .I2(pi_dqs_found_all_bank), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(detect_pi_found_dqs), .I5(first_fail_detect_i_2_n_0), .O(\dec_cnt[5]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \dec_cnt[5]_i_4 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(\dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \dec_cnt[5]_i_5 (.I0(\dec_cnt_reg_n_0_[5] ), .I1(\dec_cnt_reg_n_0_[3] ), .I2(\dec_cnt_reg_n_0_[0] ), .I3(\dec_cnt_reg_n_0_[1] ), .I4(\dec_cnt_reg_n_0_[2] ), .I5(\dec_cnt_reg_n_0_[4] ), .O(\dec_cnt_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair271" *) LUT5 #( .INIT(32'hFEFFFFFF)) \dec_cnt[5]_i_6 (.I0(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I1(fine_adjust_lane_cnt[2]), .I2(\ctl_lane_cnt_reg_n_0_[3] ), .I3(fine_adjust_lane_cnt[0]), .I4(fine_adjust_lane_cnt[1]), .O(\dec_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair275" *) LUT5 #( .INIT(32'hFFFFFFFE)) \dec_cnt[5]_i_7 (.I0(\dec_cnt_reg_n_0_[4] ), .I1(\dec_cnt_reg_n_0_[2] ), .I2(\dec_cnt_reg_n_0_[1] ), .I3(\dec_cnt_reg_n_0_[0] ), .I4(\dec_cnt_reg_n_0_[3] ), .O(\dec_cnt[5]_i_7_n_0 )); LUT6 #( .INIT(64'h0080000000D00000)) \dec_cnt[5]_i_8 (.I0(\first_fail_taps[5]_i_5_n_0 ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[4] ), .I3(\first_fail_taps[5]_i_6_n_0 ), .I4(\inc_cnt_reg_n_0_[5] ), .I5(first_fail_detect_reg_n_0), .O(\dec_cnt[5]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFE0000FFFFFFFF)) \dec_cnt[5]_i_9 (.I0(\first_fail_taps_reg_n_0_[2] ), .I1(\first_fail_taps_reg_n_0_[1] ), .I2(\first_fail_taps_reg_n_0_[4] ), .I3(\first_fail_taps_reg_n_0_[3] ), .I4(\first_fail_taps_reg_n_0_[5] ), .I5(first_fail_detect_reg_n_0), .O(\dec_cnt[5]_i_9_n_0 )); FDRE \dec_cnt_reg[0] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[0]), .Q(\dec_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__13)); CARRY4 \dec_cnt_reg[0]_i_3 (.CI(1'b0), .CO({\dec_cnt_reg[0]_i_3_n_0 ,\dec_cnt_reg[0]_i_3_n_1 ,\dec_cnt_reg[0]_i_3_n_2 ,\dec_cnt_reg[0]_i_3_n_3 }), .CYINIT(1'b1), .DI({\inc_cnt_reg_n_0_[3] ,\inc_cnt_reg_n_0_[2] ,\inc_cnt_reg_n_0_[1] ,\inc_cnt_reg_n_0_[0] }), .O({\dec_cnt_reg[0]_i_3_n_4 ,\dec_cnt_reg[0]_i_3_n_5 ,\dec_cnt_reg[0]_i_3_n_6 ,\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED [0]}), .S({\dec_cnt[0]_i_4_n_0 ,\dec_cnt[0]_i_5_n_0 ,\dec_cnt[0]_i_6_n_0 ,\dec_cnt[0]_i_7_n_0 })); FDRE \dec_cnt_reg[1] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[1]), .Q(\dec_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \dec_cnt_reg[2] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[2]), .Q(\dec_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \dec_cnt_reg[3] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[3]), .Q(\dec_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \dec_cnt_reg[4] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[4]), .Q(\dec_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__13)); CARRY4 \dec_cnt_reg[4]_i_4 (.CI(\dec_cnt_reg[0]_i_3_n_0 ), .CO({\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED [3:1],\dec_cnt_reg[4]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\inc_cnt_reg_n_0_[4] }), .O({\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED [3:2],\dec_cnt_reg[4]_i_4_n_6 ,\dec_cnt_reg[4]_i_4_n_7 }), .S({1'b0,1'b0,\dec_cnt[4]_i_6_n_0 ,\dec_cnt[4]_i_7_n_0 })); FDRE \dec_cnt_reg[5] (.C(CLK), .CE(\dec_cnt[5]_i_1_n_0 ), .D(dec_cnt[5]), .Q(\dec_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT1 #( .INIT(2'h1)) \detect_rd_cnt[0]_i_1 (.I0(detect_rd_cnt_reg__0[0]), .O(detect_rd_cnt0__0[0])); (* SOFT_HLUTNM = "soft_lutpair299" *) LUT2 #( .INIT(4'h9)) \detect_rd_cnt[1]_i_1 (.I0(detect_rd_cnt_reg__0[0]), .I1(detect_rd_cnt_reg__0[1]), .O(\detect_rd_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair299" *) LUT3 #( .INIT(8'hA9)) \detect_rd_cnt[2]_i_1 (.I0(detect_rd_cnt_reg__0[2]), .I1(detect_rd_cnt_reg__0[1]), .I2(detect_rd_cnt_reg__0[0]), .O(detect_rd_cnt0__0[2])); LUT5 #( .INIT(32'hAAAAAAAB)) \detect_rd_cnt[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_rd_cnt_reg__0[3]), .I3(detect_rd_cnt_reg__0[0]), .I4(detect_rd_cnt_reg__0[1]), .O(\detect_rd_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'hAAAAAAA8)) \detect_rd_cnt[3]_i_2 (.I0(detect_pi_found_dqs), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_rd_cnt_reg__0[3]), .I3(detect_rd_cnt_reg__0[0]), .I4(detect_rd_cnt_reg__0[1]), .O(detect_rd_cnt0)); (* SOFT_HLUTNM = "soft_lutpair269" *) LUT4 #( .INIT(16'hAAA9)) \detect_rd_cnt[3]_i_3 (.I0(detect_rd_cnt_reg__0[3]), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_rd_cnt_reg__0[0]), .I3(detect_rd_cnt_reg__0[1]), .O(detect_rd_cnt0__0[3])); FDSE \detect_rd_cnt_reg[0] (.C(CLK), .CE(detect_rd_cnt0), .D(detect_rd_cnt0__0[0]), .Q(detect_rd_cnt_reg__0[0]), .S(\detect_rd_cnt[3]_i_1_n_0 )); FDSE \detect_rd_cnt_reg[1] (.C(CLK), .CE(detect_rd_cnt0), .D(\detect_rd_cnt[1]_i_1_n_0 ), .Q(detect_rd_cnt_reg__0[1]), .S(\detect_rd_cnt[3]_i_1_n_0 )); FDSE \detect_rd_cnt_reg[2] (.C(CLK), .CE(detect_rd_cnt0), .D(detect_rd_cnt0__0[2]), .Q(detect_rd_cnt_reg__0[2]), .S(\detect_rd_cnt[3]_i_1_n_0 )); FDRE \detect_rd_cnt_reg[3] (.C(CLK), .CE(detect_rd_cnt0), .D(detect_rd_cnt0__0[3]), .Q(detect_rd_cnt_reg__0[3]), .R(\detect_rd_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000800000000000)) dqs_found_done_r_i_1 (.I0(\rd_byte_data_offset_reg[0]_3 ), .I1(init_dqsfound_done_r1_reg_n_0), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I3(dqs_found_done_r_i_3_n_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I5(p_1_in27_in), .O(dqs_found_done_r0)); LUT2 #( .INIT(4'h1)) dqs_found_done_r_i_2 (.I0(\rnk_cnt_r_reg_n_0_[1] ), .I1(\rnk_cnt_r_reg_n_0_[0] ), .O(\rd_byte_data_offset_reg[0]_3 )); LUT2 #( .INIT(4'h1)) dqs_found_done_r_i_3 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .O(dqs_found_done_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair292" *) LUT2 #( .INIT(4'h8)) dqs_found_done_r_i_4 (.I0(pi_dqs_found_all_bank), .I1(\pi_dqs_found_all_bank_r_reg[1]_0 ), .O(p_1_in27_in)); FDRE dqs_found_done_r_reg (.C(CLK), .CE(1'b1), .D(dqs_found_done_r0), .Q(pi_dqs_found_done_r1_reg), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'h0201010000020200)) dqs_found_prech_req_i_2 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[0] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[5] ), .O(fine_adj_state_r16_out)); LUT3 #( .INIT(8'hB8)) dqs_found_prech_req_i_3 (.I0(fine_adj_state_r110_out), .I1(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I2(fine_adj_state_r17_out), .O(dqs_found_prech_req_reg_0)); LUT6 #( .INIT(64'hC008000800000000)) dqs_found_prech_req_i_4 (.I0(dqs_found_prech_req_i_5_n_0), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(prech_done), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(dqs_found_prech_req_reg_1)); LUT6 #( .INIT(64'hF0C0F040F0800000)) dqs_found_prech_req_i_5 (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ), .I1(\dec_cnt[5]_i_10_n_0 ), .I2(detect_pi_found_dqs), .I3(p_1_in27_in), .I4(fine_adj_state_r110_out), .I5(fine_adj_state_r17_out), .O(dqs_found_prech_req_i_5_n_0)); FDRE dqs_found_prech_req_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[2]_1 ), .Q(dqs_found_prech_req), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE dqs_found_start_r_reg (.C(CLK), .CE(1'b1), .D(pi_dqs_found_start_reg), .Q(dqs_found_start_r), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) final_dec_done_i_2 (.I0(\dec_cnt_reg[0]_0 ), .I1(fine_adjust_lane_cnt[1]), .I2(fine_adjust_lane_cnt[0]), .I3(\ctl_lane_cnt_reg_n_0_[3] ), .I4(fine_adjust_lane_cnt[2]), .I5(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .O(final_dec_done_reg_1)); FDRE final_dec_done_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_1 ), .Q(final_dec_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE fine_adjust_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[0]_3 ), .Q(fine_adjust_done_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE fine_adjust_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[0]_2 ), .Q(\pi_rst_stg1_cal_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT5 #( .INIT(32'hFFFFAEAF)) first_fail_detect_i_1 (.I0(\first_fail_taps[5]_i_4_n_0 ), .I1(\first_fail_taps[5]_i_5_n_0 ), .I2(first_fail_detect_i_2_n_0), .I3(first_fail_detect_reg_n_0), .I4(fine_adj_state_r141_out), .O(first_fail_detect_i_1_n_0)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) first_fail_detect_i_2 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[3] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[0] ), .O(first_fail_detect_i_2_n_0)); LUT6 #( .INIT(64'h000000000000FF08)) first_fail_detect_i_3 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\first_fail_taps[5]_i_6_n_0 ), .I3(\inc_cnt_reg_n_0_[5] ), .I4(\first_fail_taps[5]_i_5_n_0 ), .I5(first_fail_detect_reg_n_0), .O(fine_adj_state_r141_out)); FDRE first_fail_detect_reg (.C(CLK), .CE(first_fail_detect), .D(first_fail_detect_i_1_n_0), .Q(first_fail_detect_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__2)); LUT3 #( .INIT(8'hB8)) \first_fail_taps[0]_i_1 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[0]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[1]_i_1 (.I0(\inc_cnt_reg_n_0_[1] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[1]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[2]_i_1 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[2]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[3]_i_1 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[3]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \first_fail_taps[4]_i_1 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[4]_i_1_n_0 )); LUT6 #( .INIT(64'h0020000000000000)) \first_fail_taps[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(fine_adj_state_r144_out), .I5(first_fail_detect_i_1_n_0), .O(first_fail_detect)); LUT3 #( .INIT(8'hB8)) \first_fail_taps[5]_i_2 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[5]_i_2_n_0 )); LUT3 #( .INIT(8'h2A)) \first_fail_taps[5]_i_3 (.I0(detect_pi_found_dqs), .I1(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I2(pi_dqs_found_all_bank), .O(fine_adj_state_r144_out)); LUT6 #( .INIT(64'hFFFFF7FF00FF00FF)) \first_fail_taps[5]_i_4 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\first_fail_taps[5]_i_6_n_0 ), .I3(first_fail_detect_reg_n_0), .I4(\first_fail_taps[5]_i_7_n_0 ), .I5(\first_fail_taps[5]_i_5_n_0 ), .O(\first_fail_taps[5]_i_4_n_0 )); LUT5 #( .INIT(32'h15555555)) \first_fail_taps[5]_i_5 (.I0(stable_pass_cnt_reg__0[5]), .I1(stable_pass_cnt_reg__0[1]), .I2(stable_pass_cnt_reg__0[2]), .I3(stable_pass_cnt_reg__0[3]), .I4(stable_pass_cnt_reg__0[4]), .O(\first_fail_taps[5]_i_5_n_0 )); LUT3 #( .INIT(8'h7F)) \first_fail_taps[5]_i_6 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[3] ), .O(\first_fail_taps[5]_i_6_n_0 )); LUT6 #( .INIT(64'h00000001FFFFFFFF)) \first_fail_taps[5]_i_7 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[0] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[4] ), .I5(\inc_cnt_reg_n_0_[5] ), .O(\first_fail_taps[5]_i_7_n_0 )); FDRE \first_fail_taps_reg[0] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[0]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \first_fail_taps_reg[1] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[1]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \first_fail_taps_reg[2] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[2]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \first_fail_taps_reg[3] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[3]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \first_fail_taps_reg[4] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[4]_i_1_n_0 ), .Q(\first_fail_taps_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \first_fail_taps_reg[5] (.C(CLK), .CE(first_fail_detect), .D(\first_fail_taps[5]_i_2_n_0 ), .Q(\first_fail_taps_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'hFFFFFFFF88A8FFFF)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_4 (.I0(ck_addr_cmd_delay_done), .I1(\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ), .I2(rd_data_offset_cal_done), .I3(fine_adjust_done_r_reg_0), .I4(cmd_delay_start0), .I5(rstdiv0_sync_r1_reg_rep__25), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair291" *) LUT2 #( .INIT(4'h7)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_9 (.I0(pi_dqs_found_done_r1_reg), .I1(pi_calib_done), .O(\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 )); LUT6 #( .INIT(64'hAAAAAAEAAAAAAA2A)) \gen_byte_sel_div1.calib_in_common_i_1 (.I0(\gen_byte_sel_div1.calib_in_common_i_2_n_0 ), .I1(pi_dqs_found_done_r1_reg), .I2(pi_calib_done), .I3(oclkdelay_calib_done_r_reg), .I4(pi_f_inc_reg), .I5(calib_in_common), .O(\gen_byte_sel_div1.calib_in_common_reg )); LUT6 #( .INIT(64'hBFBFFFBFFFBFFFBF)) \gen_byte_sel_div1.calib_in_common_i_2 (.I0(\gen_byte_sel_div1.calib_in_common_i_5_n_0 ), .I1(pi_fine_dly_dec_done), .I2(dqs_po_dec_done), .I3(\calib_zero_inputs_reg[1] ), .I4(pi_calib_done), .I5(pi_dqs_found_done_r1_reg), .O(\gen_byte_sel_div1.calib_in_common_i_2_n_0 )); LUT6 #( .INIT(64'h3533000005000000)) \gen_byte_sel_div1.calib_in_common_i_5 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(oclkdelay_calib_done_r_reg), .I2(fine_adjust_done_r_reg_0), .I3(rd_data_offset_cal_done), .I4(ck_addr_cmd_delay_done), .I5(tempmon_sel_pi_incdec), .O(\gen_byte_sel_div1.calib_in_common_i_5_n_0 )); LUT6 #( .INIT(64'h8F80FFFF8F800000)) \gen_byte_sel_div1.ctl_lane_sel[0]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(fine_adjust_lane_cnt[0]), .I2(ck_addr_cmd_delay_done), .I3(ctl_lane_cnt[0]), .I4(ctl_lane_sel), .I5(\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ), .O(\gen_byte_sel_div1.ctl_lane_sel_reg[0] )); LUT6 #( .INIT(64'h8F80FFFF8F800000)) \gen_byte_sel_div1.ctl_lane_sel[1]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(fine_adjust_lane_cnt[1]), .I2(ck_addr_cmd_delay_done), .I3(ctl_lane_cnt[1]), .I4(ctl_lane_sel), .I5(\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ), .O(\gen_byte_sel_div1.ctl_lane_sel_reg[1] )); LUT6 #( .INIT(64'h8F80FFFF8F800000)) \gen_byte_sel_div1.ctl_lane_sel[2]_i_1 (.I0(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ), .I1(fine_adjust_lane_cnt[2]), .I2(ck_addr_cmd_delay_done), .I3(ctl_lane_cnt[2]), .I4(ctl_lane_sel), .I5(\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ), .O(\gen_byte_sel_div1.ctl_lane_sel_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair290" *) LUT2 #( .INIT(4'h1)) \gen_byte_sel_div1.ctl_lane_sel[2]_i_2 (.I0(rst_stg1_cal), .I1(\pi_rst_stg1_cal_reg_n_0_[1] ), .O(\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair289" *) LUT3 #( .INIT(8'h80)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3 (.I0(pi_dqs_found_done_r1_reg), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg_rep), .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] )); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b1), .O(n_0_0)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b1), .O(n_0_1)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b1), .O(n_0_2)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b1), .O(n_0_3)); (* SOFT_HLUTNM = "soft_lutpair302" *) LUT1 #( .INIT(2'h1)) \inc_cnt[0]_i_1 (.I0(\inc_cnt_reg_n_0_[0] ), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair302" *) LUT2 #( .INIT(4'h6)) \inc_cnt[1]_i_1 (.I0(\inc_cnt_reg_n_0_[0] ), .I1(\inc_cnt_reg_n_0_[1] ), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair300" *) LUT3 #( .INIT(8'h6A)) \inc_cnt[2]_i_1 (.I0(\inc_cnt_reg_n_0_[2] ), .I1(\inc_cnt_reg_n_0_[1] ), .I2(\inc_cnt_reg_n_0_[0] ), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair286" *) LUT4 #( .INIT(16'h6AAA)) \inc_cnt[3]_i_1 (.I0(\inc_cnt_reg_n_0_[3] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair286" *) LUT5 #( .INIT(32'h6AAAAAAA)) \inc_cnt[4]_i_1 (.I0(\inc_cnt_reg_n_0_[4] ), .I1(\inc_cnt_reg_n_0_[0] ), .I2(\inc_cnt_reg_n_0_[2] ), .I3(\inc_cnt_reg_n_0_[1] ), .I4(\inc_cnt_reg_n_0_[3] ), .O(\inc_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'h00200000)) \inc_cnt[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(inc_cnt)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \inc_cnt[5]_i_2 (.I0(\inc_cnt_reg_n_0_[5] ), .I1(\inc_cnt_reg_n_0_[3] ), .I2(\inc_cnt_reg_n_0_[1] ), .I3(\inc_cnt_reg_n_0_[2] ), .I4(\inc_cnt_reg_n_0_[0] ), .I5(\inc_cnt_reg_n_0_[4] ), .O(p_0_in__0[5])); FDRE \inc_cnt_reg[0] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[0]), .Q(\inc_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \inc_cnt_reg[1] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[1]), .Q(\inc_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \inc_cnt_reg[2] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[2]), .Q(\inc_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \inc_cnt_reg[3] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[3]), .Q(\inc_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \inc_cnt_reg[4] (.C(CLK), .CE(inc_cnt), .D(\inc_cnt[4]_i_1_n_0 ), .Q(\inc_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \inc_cnt_reg[5] (.C(CLK), .CE(inc_cnt), .D(p_0_in__0[5]), .Q(\inc_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__2)); LUT1 #( .INIT(2'h1)) \init_dec_cnt[0]_i_1 (.I0(init_dec_cnt_reg__0[0]), .O(init_dec_cnt0[0])); (* SOFT_HLUTNM = "soft_lutpair301" *) LUT2 #( .INIT(4'h9)) \init_dec_cnt[1]_i_1 (.I0(init_dec_cnt_reg__0[0]), .I1(init_dec_cnt_reg__0[1]), .O(\init_dec_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair301" *) LUT3 #( .INIT(8'hE1)) \init_dec_cnt[2]_i_1 (.I0(init_dec_cnt_reg__0[0]), .I1(init_dec_cnt_reg__0[1]), .I2(init_dec_cnt_reg__0[2]), .O(init_dec_cnt0[2])); (* SOFT_HLUTNM = "soft_lutpair281" *) LUT4 #( .INIT(16'hFE01)) \init_dec_cnt[3]_i_1 (.I0(init_dec_cnt_reg__0[2]), .I1(init_dec_cnt_reg__0[1]), .I2(init_dec_cnt_reg__0[0]), .I3(init_dec_cnt_reg__0[3]), .O(init_dec_cnt0[3])); (* SOFT_HLUTNM = "soft_lutpair281" *) LUT5 #( .INIT(32'hFFFE0001)) \init_dec_cnt[4]_i_1 (.I0(init_dec_cnt_reg__0[3]), .I1(init_dec_cnt_reg__0[0]), .I2(init_dec_cnt_reg__0[1]), .I3(init_dec_cnt_reg__0[2]), .I4(init_dec_cnt_reg__0[4]), .O(init_dec_cnt0[4])); LUT6 #( .INIT(64'h2000000000000000)) \init_dec_cnt[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_1 ), .I4(\FSM_sequential_fine_adj_state_r_reg[2]_0 ), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .O(init_dec_cnt)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \init_dec_cnt[5]_i_2 (.I0(init_dec_cnt_reg__0[4]), .I1(init_dec_cnt_reg__0[2]), .I2(init_dec_cnt_reg__0[1]), .I3(init_dec_cnt_reg__0[0]), .I4(init_dec_cnt_reg__0[3]), .I5(init_dec_cnt_reg__0[5]), .O(init_dec_cnt0[5])); FDSE \init_dec_cnt_reg[0] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[0]), .Q(init_dec_cnt_reg__0[0]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE \init_dec_cnt_reg[1] (.C(CLK), .CE(init_dec_cnt), .D(\init_dec_cnt[1]_i_1_n_0 ), .Q(init_dec_cnt_reg__0[1]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE \init_dec_cnt_reg[2] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[2]), .Q(init_dec_cnt_reg__0[2]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE \init_dec_cnt_reg[3] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[3]), .Q(init_dec_cnt_reg__0[3]), .S(rstdiv0_sync_r1_reg_rep__2)); FDSE \init_dec_cnt_reg[4] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[4]), .Q(init_dec_cnt_reg__0[4]), .S(rstdiv0_sync_r1_reg_rep__2)); FDRE \init_dec_cnt_reg[5] (.C(CLK), .CE(init_dec_cnt), .D(init_dec_cnt0[5]), .Q(init_dec_cnt_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__2)); LUT3 #( .INIT(8'h08)) init_dec_done_i_2 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(init_dec_done_reg_1)); FDRE init_dec_done_reg (.C(CLK), .CE(1'b1), .D(init_dec_done_reg_2), .Q(init_dec_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE init_dqsfound_done_r1_reg (.C(CLK), .CE(1'b1), .D(rd_data_offset_cal_done), .Q(init_dqsfound_done_r1_reg_n_0), .R(1'b0)); FDRE init_dqsfound_done_r2_reg (.C(CLK), .CE(1'b1), .D(init_dqsfound_done_r1_reg_n_0), .Q(init_dqsfound_done_r2), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r4_reg_srl2 " *) SRL16E init_dqsfound_done_r4_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(init_dqsfound_done_r2), .Q(init_dqsfound_done_r4_reg_srl2_n_0)); FDRE init_dqsfound_done_r5_reg (.C(CLK), .CE(1'b1), .D(init_dqsfound_done_r4_reg_srl2_n_0), .Q(init_dqsfound_done_r5), .R(1'b0)); FDRE init_dqsfound_done_r_reg (.C(CLK), .CE(1'b1), .D(init_dqsfound_done_r_reg_0), .Q(rd_data_offset_cal_done), .R(1'b0)); LUT6 #( .INIT(64'h0003FFFF33A3FFFF)) \init_state_r[1]_i_14 (.I0(\init_state_r[1]_i_29_n_0 ), .I1(\num_refresh_reg[1] ), .I2(oclkdelay_calib_done_r_reg_0), .I3(mpr_rdlvl_done_r_reg), .I4(cnt_cmd_done_r), .I5(\init_state_r[1]_i_30_n_0 ), .O(\init_state_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair291" *) LUT4 #( .INIT(16'h00DF)) \init_state_r[1]_i_29 (.I0(pi_dqs_found_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_last_byte_done_r), .I3(wrcal_done_reg), .O(\init_state_r[1]_i_29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair289" *) LUT4 #( .INIT(16'h5DFD)) \init_state_r[1]_i_30 (.I0(pi_dqs_found_done_r1_reg), .I1(wrcal_done_reg), .I2(rdlvl_stg1_done_int_reg), .I3(prbs_rdlvl_done_reg_rep), .O(\init_state_r[1]_i_30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair288" *) LUT2 #( .INIT(4'h7)) \init_state_r[1]_i_31 (.I0(pi_dqs_found_done_r1_reg), .I1(wrcal_done_reg), .O(\init_state_r_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair288" *) LUT4 #( .INIT(16'hFFFB)) \init_state_r[1]_i_44 (.I0(wrlvl_final_mux), .I1(pi_dqs_found_done_r1_reg), .I2(wrlvl_byte_redo), .I3(wrlvl_done_r1), .O(\init_state_r_reg[1]_0 )); LUT6 #( .INIT(64'hF0FDFDFDFDFDFDFD)) \init_state_r[2]_i_31 (.I0(pi_dqs_found_done_r1_reg), .I1(wrlvl_byte_redo), .I2(wrlvl_done_r1), .I3(oclkdelay_center_calib_done_r_reg), .I4(prbs_rdlvl_done_reg_rep), .I5(rdlvl_stg1_done_int_reg), .O(\init_state_r_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair266" *) LUT5 #( .INIT(32'h0000EA00)) \phaser_in_gen.phaser_in_i_5 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg)); (* SOFT_HLUTNM = "soft_lutpair266" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_5__0 (.I0(calib_in_common), .I1(Q[0]), .I2(Q[1]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg_0)); (* SOFT_HLUTNM = "soft_lutpair267" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_5__1 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg_1)); (* SOFT_HLUTNM = "soft_lutpair267" *) LUT5 #( .INIT(32'h0000AB00)) \phaser_in_gen.phaser_in_i_5__2 (.I0(calib_in_common), .I1(Q[1]), .I2(Q[0]), .I3(rst_stg1_cal), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(ififo_rst_reg_2)); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__1 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_6 )); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__2 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_8 )); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__3 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_10 )); LUT6 #( .INIT(64'h00000000AAAAAAA8)) phaser_out_i_2__4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(ck_po_stg2_f_en), .I2(dqs_po_en_stg2_f), .I3(po_en_stg2_f), .I4(po_en_stg23), .I5(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_12 )); (* SOFT_HLUTNM = "soft_lutpair270" *) LUT5 #( .INIT(32'h00000800)) phaser_out_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(D_po_fine_enable107_out)); (* SOFT_HLUTNM = "soft_lutpair270" *) LUT5 #( .INIT(32'h00000100)) phaser_out_i_3__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair272" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_3__1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_1 )); (* SOFT_HLUTNM = "soft_lutpair272" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_3__2 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(po_enstg2_f), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_3 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__3 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_5 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_7 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__5 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_9 )); LUT5 #( .INIT(32'h0000AAA8)) phaser_out_i_3__6 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(ck_po_stg2_f_indec), .I2(dqs_po_stg2_f_incdec), .I3(po_stg23_incdec), .I4(\calib_zero_inputs_reg[1]_0 [0]), .O(\po_counter_read_val_reg[8]_11 )); (* SOFT_HLUTNM = "soft_lutpair265" *) LUT5 #( .INIT(32'h00000800)) phaser_out_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(D_po_fine_inc113_out)); (* SOFT_HLUTNM = "soft_lutpair268" *) LUT5 #( .INIT(32'h00000100)) phaser_out_i_4__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_0 )); (* SOFT_HLUTNM = "soft_lutpair268" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_4__1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_2 )); (* SOFT_HLUTNM = "soft_lutpair265" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_4__2 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(po_stg2_fincdec), .I4(\calib_zero_inputs_reg[1]_0 [1]), .O(\po_counter_read_val_reg[8]_4 )); LUT6 #( .INIT(64'h8000FFFF80000000)) \pi_dqs_found_all_bank[0]_i_1 (.I0(pi_dqs_found_lanes_r3[2]), .I1(pi_dqs_found_lanes_r3[3]), .I2(pi_dqs_found_lanes_r3[1]), .I3(pi_dqs_found_lanes_r3[0]), .I4(pi_dqs_found_start_reg), .I5(pi_dqs_found_all_bank), .O(\pi_dqs_found_all_bank[0]_i_1_n_0 )); FDRE \pi_dqs_found_all_bank_r_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_all_bank), .Q(rank_done_r_reg_0[0]), .R(1'b0)); FDRE \pi_dqs_found_all_bank_r_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_all_bank_r_reg[1]_0 ), .Q(rank_done_r_reg_0[1]), .R(1'b0)); FDRE \pi_dqs_found_all_bank_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_all_bank[0]_i_1_n_0 ), .Q(pi_dqs_found_all_bank), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \pi_dqs_found_all_bank_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_start_reg_0), .Q(\pi_dqs_found_all_bank_r_reg[1]_0 ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \pi_dqs_found_any_bank_r_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_any_bank), .Q(\pi_dqs_found_any_bank_r_reg_n_0_[0] ), .R(1'b0)); FDRE \pi_dqs_found_any_bank_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_lanes_r3_reg[3]_0 ), .Q(pi_dqs_found_any_bank), .R(rstdiv0_sync_r1_reg_rep__12)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[0] (.C(CLK), .CE(1'b1), .D(in0[0]), .Q(pi_dqs_found_lanes_r1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[1] (.C(CLK), .CE(1'b1), .D(in0[1]), .Q(pi_dqs_found_lanes_r1[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[2] (.C(CLK), .CE(1'b1), .D(in0[2]), .Q(pi_dqs_found_lanes_r1[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[3] (.C(CLK), .CE(1'b1), .D(in0[3]), .Q(pi_dqs_found_lanes_r1[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[4] (.C(CLK), .CE(1'b1), .D(n_0_3), .Q(pi_dqs_found_lanes_r1[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[5] (.C(CLK), .CE(1'b1), .D(n_0_2), .Q(pi_dqs_found_lanes_r1[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[6] (.C(CLK), .CE(1'b1), .D(n_0_1), .Q(pi_dqs_found_lanes_r1[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r1_reg[7] (.C(CLK), .CE(1'b1), .D(n_0_0), .Q(pi_dqs_found_lanes_r1[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[0]), .Q(pi_dqs_found_lanes_r2[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[1]), .Q(pi_dqs_found_lanes_r2[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[2] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[2]), .Q(pi_dqs_found_lanes_r2[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[3] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[3]), .Q(pi_dqs_found_lanes_r2[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[4]), .Q(pi_dqs_found_lanes_r2[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[5]), .Q(pi_dqs_found_lanes_r2[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[6] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[6]), .Q(pi_dqs_found_lanes_r2[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r2_reg[7] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r1[7]), .Q(pi_dqs_found_lanes_r2[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[0]), .Q(pi_dqs_found_lanes_r3[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[1]), .Q(pi_dqs_found_lanes_r3[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[2] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[2]), .Q(pi_dqs_found_lanes_r3[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[3] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[3]), .Q(pi_dqs_found_lanes_r3[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[4]), .Q(pi_dqs_found_lanes_r3[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[5]), .Q(pi_dqs_found_lanes_r3[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[6] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[6]), .Q(pi_dqs_found_lanes_r3[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \pi_dqs_found_lanes_r3_reg[7] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_lanes_r2[7]), .Q(pi_dqs_found_lanes_r3[7]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair304" *) LUT2 #( .INIT(4'hE)) \pi_rst_stg1_cal[0]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_1 ), .I1(rst_dqs_find_r1_reg_0), .O(\pi_rst_stg1_cal[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair304" *) LUT2 #( .INIT(4'hE)) \pi_rst_stg1_cal[1]_i_1 (.I0(p_1_in50_in), .I1(rst_dqs_find_r1_reg_0), .O(\pi_rst_stg1_cal[1]_i_1_n_0 )); LUT6 #( .INIT(64'h1111111010101010)) \pi_rst_stg1_cal_r1[0]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(\pi_rst_stg1_cal_r_reg[0]_1 ), .I3(\pi_dqs_found_any_bank_r_reg_n_0_[0] ), .I4(pi_dqs_found_all_bank), .I5(\pi_rst_stg1_cal_r1_reg_n_0_[0] ), .O(pi_rst_stg1_cal_r1_reg017_out)); LUT5 #( .INIT(32'h11101010)) \pi_rst_stg1_cal_r1[1]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(p_1_in50_in), .I3(p_0_in19_in), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .O(pi_rst_stg1_cal_r1_reg0)); FDRE \pi_rst_stg1_cal_r1_reg[0] (.C(CLK), .CE(1'b1), .D(pi_rst_stg1_cal_r1_reg017_out), .Q(\pi_rst_stg1_cal_r1_reg_n_0_[0] ), .R(1'b0)); FDRE \pi_rst_stg1_cal_r1_reg[1] (.C(CLK), .CE(1'b1), .D(pi_rst_stg1_cal_r1_reg0), .Q(p_0_in19_in), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000FE)) \pi_rst_stg1_cal_r[0]_i_1 (.I0(\pi_rst_stg1_cal_r_reg[0]_1 ), .I1(\pi_rst_stg1_cal_r[0]_i_2_n_0 ), .I2(\pi_rst_stg1_cal_r[0]_i_3_n_0 ), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(\pi_rst_stg1_cal_r_reg[0]_0 ), .I5(\pi_rst_stg1_cal_r1_reg_n_0_[0] ), .O(\pi_rst_stg1_cal_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h0007)) \pi_rst_stg1_cal_r[0]_i_2 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I2(\rd_byte_data_offset_reg_n_0_[0][5] ), .I3(\rd_byte_data_offset_reg_n_0_[0][4] ), .O(\pi_rst_stg1_cal_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair292" *) LUT4 #( .INIT(16'h4F44)) \pi_rst_stg1_cal_r[0]_i_3 (.I0(dqs_found_start_r), .I1(pi_dqs_found_start_reg), .I2(pi_dqs_found_all_bank), .I3(\pi_dqs_found_any_bank_r_reg_n_0_[0] ), .O(\pi_rst_stg1_cal_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000EFEE0000)) \pi_rst_stg1_cal_r[1]_i_1 (.I0(p_1_in50_in), .I1(\pi_rst_stg1_cal_r[1]_i_2_n_0 ), .I2(dqs_found_start_r), .I3(pi_dqs_found_start_reg), .I4(fine_adjust_reg_0), .I5(p_0_in19_in), .O(\pi_rst_stg1_cal_r[1]_i_1_n_0 )); LUT4 #( .INIT(16'h0007)) \pi_rst_stg1_cal_r[1]_i_2 (.I0(\rd_byte_data_offset_reg[0][9]_0 [1]), .I1(\rd_byte_data_offset_reg[0][9]_0 [0]), .I2(p_0_in[5]), .I3(p_0_in[4]), .O(\pi_rst_stg1_cal_r[1]_i_2_n_0 )); FDRE \pi_rst_stg1_cal_r_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal_r[0]_i_1_n_0 ), .Q(\pi_rst_stg1_cal_r_reg[0]_1 ), .R(1'b0)); FDRE \pi_rst_stg1_cal_r_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal_r[1]_i_1_n_0 ), .Q(p_1_in50_in), .R(1'b0)); FDRE \pi_rst_stg1_cal_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal[0]_i_1_n_0 ), .Q(rst_stg1_cal), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \pi_rst_stg1_cal_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_rst_stg1_cal[1]_i_1_n_0 ), .Q(\pi_rst_stg1_cal_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE rank_done_r1_reg (.C(CLK), .CE(1'b1), .D(pi_dqs_found_rank_done), .Q(rank_done_r1), .R(1'b0)); FDRE rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\pi_dqs_found_all_bank_r_reg[1]_1 ), .Q(pi_dqs_found_rank_done), .R(1'b0)); LUT2 #( .INIT(4'h2)) \rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 (.I0(rd_data_offset_cal_done), .I1(init_dqsfound_done_r1_reg_n_0), .O(p_22_out)); (* SOFT_HLUTNM = "soft_lutpair296" *) LUT1 #( .INIT(2'h1)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 (.I0(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair295" *) LUT2 #( .INIT(4'h9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 (.I0(\rd_byte_data_offset_reg_n_0_[0][1] ), .I1(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I1(\rd_byte_data_offset_reg_n_0_[0][0] ), .I2(\rd_byte_data_offset_reg_n_0_[0][1] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair276" *) LUT4 #( .INIT(16'hAAA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I2(\rd_byte_data_offset_reg_n_0_[0][1] ), .I3(\rd_byte_data_offset_reg_n_0_[0][0] ), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair276" *) LUT5 #( .INIT(32'hAAAAAAA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I2(\rd_byte_data_offset_reg_n_0_[0][0] ), .I3(\rd_byte_data_offset_reg_n_0_[0][1] ), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 )); LUT3 #( .INIT(8'h04)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 (.I0(init_dqsfound_done_r1_reg_n_0), .I1(rd_data_offset_cal_done), .I2(rstdiv0_sync_r1_reg_rep__24), .O(final_data_offset_mc)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ), .I1(\rd_byte_data_offset_reg_n_0_[0][4] ), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I3(\rd_byte_data_offset_reg_n_0_[0][1] ), .I4(\rd_byte_data_offset_reg_n_0_[0][0] ), .I5(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 )); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [0]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [1]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [2]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [3]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [4]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (.C(CLK), .CE(final_data_offset_mc), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ), .Q(\cmd_pipe_plus.mc_data_offset_reg[5] [5]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][0] ), .Q(rd_data_offset_ranks_0[0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][1] ), .Q(rd_data_offset_ranks_0[1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] (.C(CLK), .CE(p_22_out), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] (.C(CLK), .CE(p_22_out), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][4] ), .Q(rd_data_offset_ranks_0[4]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] (.C(CLK), .CE(p_22_out), .D(\rd_byte_data_offset_reg_n_0_[0][5] ), .Q(rd_data_offset_ranks_0[5]), .R(rstdiv0_sync_r1_reg_rep__12)); LUT3 #( .INIT(8'h8A)) \rank_final_loop[0].bank_final_loop[1].final_data_offset[0][11]_i_1 (.I0(init_dqsfound_done_r5), .I1(init_dqsfound_done_r1_reg_n_0), .I2(rd_data_offset_cal_done), .O(final_data_offset)); LUT4 #( .INIT(16'h00D0)) \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1 (.I0(rd_data_offset_cal_done), .I1(init_dqsfound_done_r1_reg_n_0), .I2(init_dqsfound_done_r5), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 )); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9] (.C(CLK), .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]), .R(1'b0)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .Q(rd_data_offset_ranks_1[4]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .Q(rd_data_offset_ranks_1[5]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .Q(rd_data_offset_ranks_1[0]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .Q(rd_data_offset_ranks_1[1]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (.C(CLK), .CE(final_data_offset), .D(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .Q(\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]), .R(rstdiv0_sync_r1_reg_rep__13)); LUT1 #( .INIT(2'h1)) \rank_final_loop[0].final_do_index[0][0]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .O(\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair285" *) LUT2 #( .INIT(4'h6)) \rank_final_loop[0].final_do_index[0][1]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .O(\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair264" *) LUT3 #( .INIT(8'h6A)) \rank_final_loop[0].final_do_index[0][2]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .O(\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 )); FDRE \rank_final_loop[0].final_do_index_reg[0][0] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].final_do_index_reg[0][1] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rank_final_loop[0].final_do_index_reg[0][2] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__13)); (* SOFT_HLUTNM = "soft_lutpair274" *) LUT5 #( .INIT(32'hEFEEEFFF)) \rank_final_loop[0].final_do_max[0][0]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(rd_data_offset_ranks_1[0]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(rd_data_offset_ranks_0[0]), .O(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'hFAF5FCFCFAF5F3F3)) \rank_final_loop[0].final_do_max[0][1]_i_1 (.I0(rd_data_offset_ranks_1[1]), .I1(rd_data_offset_ranks_0[1]), .I2(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ), .I3(rd_data_offset_ranks_1[0]), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I5(rd_data_offset_ranks_0[0]), .O(\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h555555555555A959)) \rank_final_loop[0].final_do_max[0][2]_i_1 (.I0(\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ), .I1(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I5(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FAFFFACC)) \rank_final_loop[0].final_do_max[0][2]_i_2 (.I0(rd_data_offset_ranks_1[0]), .I1(rd_data_offset_ranks_0[0]), .I2(rd_data_offset_ranks_1[1]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(rd_data_offset_ranks_0[1]), .I5(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ), .O(\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h555555555555A959)) \rank_final_loop[0].final_do_max[0][3]_i_1 (.I0(\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ), .I1(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I5(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF10111000)) \rank_final_loop[0].final_do_max[0][3]_i_2 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I5(\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ), .O(\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 )); LUT6 #( .INIT(64'hEFEEEFFF10111000)) \rank_final_loop[0].final_do_max[0][4]_i_1 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(rd_data_offset_ranks_1[4]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(rd_data_offset_ranks_0[4]), .I5(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ), .O(\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FFFF4F44)) \rank_final_loop[0].final_do_max[0][5]_i_1 (.I0(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .I1(rd_data_offset_ranks_0[5]), .I2(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .I3(rd_data_offset_ranks_0[4]), .I4(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ), .I5(\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 )); LUT6 #( .INIT(64'h4540BABF45404540)) \rank_final_loop[0].final_do_max[0][5]_i_2 (.I0(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ), .I1(rd_data_offset_ranks_1[5]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(rd_data_offset_ranks_0[5]), .I4(\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ), .I5(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FFFF4F44)) \rank_final_loop[0].final_do_max[0][5]_i_3 (.I0(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .I1(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I2(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .I3(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I4(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ), .I5(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair264" *) LUT5 #( .INIT(32'hFFFFFFF4)) \rank_final_loop[0].final_do_max[0][5]_i_4 (.I0(rd_data_offset_ranks_0[5]), .I1(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair274" *) LUT2 #( .INIT(4'hE)) \rank_final_loop[0].final_do_max[0][5]_i_5 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .O(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair285" *) LUT5 #( .INIT(32'h000000E2)) \rank_final_loop[0].final_do_max[0][5]_i_6 (.I0(rd_data_offset_ranks_0[4]), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I2(rd_data_offset_ranks_1[4]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .O(\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000EFEEEFFF)) \rank_final_loop[0].final_do_max[0][5]_i_7 (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ), .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ), .I2(\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]), .I3(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ), .I4(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I5(\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ), .O(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 )); LUT6 #( .INIT(64'h40F4000040F440F4)) \rank_final_loop[0].final_do_max[0][5]_i_8 (.I0(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .I1(rd_data_offset_ranks_0[0]), .I2(rd_data_offset_ranks_0[1]), .I3(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .I4(\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]), .I5(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .O(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 )); LUT4 #( .INIT(16'h4F44)) \rank_final_loop[0].final_do_max[0][5]_i_9 (.I0(\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]), .I1(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .I2(rd_data_offset_ranks_0[4]), .I3(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .O(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 )); FDRE \rank_final_loop[0].final_do_max_reg[0][0] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].final_do_max_reg[0][1] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].final_do_max_reg[0][2] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].final_do_max_reg[0][3] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [3]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].final_do_max_reg[0][4] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [4]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \rank_final_loop[0].final_do_max_reg[0][5] (.C(CLK), .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ), .D(\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ), .Q(\rank_final_loop[0].final_do_max_reg[0]__0 [5]), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair279" *) LUT5 #( .INIT(32'hAAAAAAA9)) \rd_byte_data_offset[0][10]_i_1 (.I0(p_0_in[4]), .I1(\rd_byte_data_offset_reg[0][9]_0 [1]), .I2(p_0_in[1]), .I3(p_0_in[0]), .I4(\rd_byte_data_offset_reg[0][9]_0 [0]), .O(p_1_in[4])); LUT4 #( .INIT(16'hAAAB)) \rd_byte_data_offset[0][11]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(\rd_byte_data_offset[0][11]_i_4_n_0 ), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .O(\rd_byte_data_offset[0][11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000080000000000)) \rd_byte_data_offset[0][11]_i_2 (.I0(\rd_byte_data_offset[0][5]_i_4_n_0 ), .I1(\rd_byte_data_offset_reg[0]_3 ), .I2(\pi_rst_stg1_cal_r_reg[0]_0 ), .I3(dqs_found_start_r), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I5(\rd_byte_data_offset[0][11]_i_4_n_0 ), .O(\rd_byte_data_offset[0][11]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \rd_byte_data_offset[0][11]_i_3 (.I0(p_0_in[5]), .I1(p_0_in[4]), .I2(\rd_byte_data_offset_reg[0][9]_0 [0]), .I3(p_0_in[0]), .I4(p_0_in[1]), .I5(\rd_byte_data_offset_reg[0][9]_0 [1]), .O(p_1_in[5])); LUT6 #( .INIT(64'hBBBBBBB0BBB0BBB0)) \rd_byte_data_offset[0][11]_i_4 (.I0(rd_data_offset_cal_done), .I1(rank_done_r1), .I2(p_0_in[4]), .I3(p_0_in[5]), .I4(\rd_byte_data_offset_reg[0][9]_0 [0]), .I5(\rd_byte_data_offset_reg[0][9]_0 [1]), .O(\rd_byte_data_offset[0][11]_i_4_n_0 )); LUT4 #( .INIT(16'hAAAB)) \rd_byte_data_offset[0][5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(\rd_byte_data_offset[0][5]_i_3_n_0 ), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .O(\rd_byte_data_offset[0][5]_i_1_n_0 )); LUT6 #( .INIT(64'h0000080000000000)) \rd_byte_data_offset[0][5]_i_2 (.I0(\rd_byte_data_offset[0][5]_i_4_n_0 ), .I1(\rd_byte_data_offset_reg[0]_3 ), .I2(\pi_rst_stg1_cal_r_reg[0]_0 ), .I3(dqs_found_start_r), .I4(pi_dqs_found_all_bank), .I5(\rd_byte_data_offset[0][5]_i_3_n_0 ), .O(rd_byte_data_offset)); LUT6 #( .INIT(64'hFEEE0000FEEEFEEE)) \rd_byte_data_offset[0][5]_i_3 (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ), .I1(\rd_byte_data_offset_reg_n_0_[0][5] ), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .I4(rd_data_offset_cal_done), .I5(rank_done_r1), .O(\rd_byte_data_offset[0][5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000001000)) \rd_byte_data_offset[0][5]_i_4 (.I0(detect_rd_cnt_reg__0[3]), .I1(detect_rd_cnt_reg__0[2]), .I2(detect_pi_found_dqs), .I3(detect_rd_cnt_reg__0[0]), .I4(detect_rd_cnt_reg__0[1]), .I5(rd_data_offset_cal_done), .O(\rd_byte_data_offset[0][5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair298" *) LUT1 #( .INIT(2'h1)) \rd_byte_data_offset[0][6]_i_1 (.I0(p_0_in[0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair294" *) LUT2 #( .INIT(4'h9)) \rd_byte_data_offset[0][7]_i_1 (.I0(p_0_in[0]), .I1(p_0_in[1]), .O(\rd_byte_data_offset[0][7]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \rd_byte_data_offset[0][8]_i_1 (.I0(\rd_byte_data_offset_reg[0][9]_0 [0]), .I1(p_0_in[1]), .I2(p_0_in[0]), .O(p_1_in[2])); (* SOFT_HLUTNM = "soft_lutpair279" *) LUT4 #( .INIT(16'hAAA9)) \rd_byte_data_offset[0][9]_i_1 (.I0(\rd_byte_data_offset_reg[0][9]_0 [1]), .I1(\rd_byte_data_offset_reg[0][9]_0 [0]), .I2(p_0_in[0]), .I3(p_0_in[1]), .O(p_1_in[3])); FDRE \rd_byte_data_offset_reg[0][0] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][0] ), .R(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDSE \rd_byte_data_offset_reg[0][10] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[4]), .Q(p_0_in[4]), .S(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDRE \rd_byte_data_offset_reg[0][11] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[5]), .Q(p_0_in[5]), .R(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDSE \rd_byte_data_offset_reg[0][1] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][1] ), .S(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDRE \rd_byte_data_offset_reg[0][2] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ), .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]), .R(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDSE \rd_byte_data_offset_reg[0][3] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ), .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]), .S(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDSE \rd_byte_data_offset_reg[0][4] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][4] ), .S(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDRE \rd_byte_data_offset_reg[0][5] (.C(CLK), .CE(rd_byte_data_offset), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ), .Q(\rd_byte_data_offset_reg_n_0_[0][5] ), .R(\rd_byte_data_offset[0][5]_i_1_n_0 )); FDRE \rd_byte_data_offset_reg[0][6] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[0]), .Q(p_0_in[0]), .R(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDSE \rd_byte_data_offset_reg[0][7] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(\rd_byte_data_offset[0][7]_i_1_n_0 ), .Q(p_0_in[1]), .S(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDRE \rd_byte_data_offset_reg[0][8] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[2]), .Q(\rd_byte_data_offset_reg[0][9]_0 [0]), .R(\rd_byte_data_offset[0][11]_i_1_n_0 )); FDSE \rd_byte_data_offset_reg[0][9] (.C(CLK), .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ), .D(p_1_in[3]), .Q(\rd_byte_data_offset_reg[0][9]_0 [1]), .S(\rd_byte_data_offset[0][11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair297" *) LUT3 #( .INIT(8'hD2)) \rnk_cnt_r[0]_i_1 (.I0(pi_dqs_found_rank_done), .I1(rd_data_offset_cal_done), .I2(\rnk_cnt_r_reg_n_0_[0] ), .O(\rnk_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair297" *) LUT4 #( .INIT(16'hF708)) \rnk_cnt_r[1]_i_1 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(pi_dqs_found_rank_done), .I2(rd_data_offset_cal_done), .I3(\rnk_cnt_r_reg_n_0_[1] ), .O(\rnk_cnt_r[1]_i_1_n_0 )); FDRE \rnk_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[0]_i_1_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rnk_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[1]_i_1_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__13)); LUT5 #( .INIT(32'h8800FF30)) rst_dqs_find_i_2 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I2(init_dqsfound_done_r5), .I3(rst_dqs_find_i_5_n_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .O(rst_dqs_find)); LUT6 #( .INIT(64'hBB00BB0030333000)) rst_dqs_find_i_3 (.I0(prech_done), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I2(rst_dqs_find_i_6_n_0), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(p_1_in27_in), .I5(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(rst_dqs_find_reg_1)); LUT6 #( .INIT(64'h0000004F00000040)) rst_dqs_find_i_4 (.I0(pi_dqs_found_any_bank), .I1(rst_dqs_find_r2), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I5(init_dqsfound_done_r5), .O(rst_dqs_find_reg_0)); LUT5 #( .INIT(32'hFFFF8A80)) rst_dqs_find_i_5 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I1(\first_fail_taps[5]_i_4_n_0 ), .I2(fine_adj_state_r144_out), .I3(first_fail_detect_i_2_n_0), .I4(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .O(rst_dqs_find_i_5_n_0)); LUT6 #( .INIT(64'h40F0F0F040000000)) rst_dqs_find_i_6 (.I0(fine_adj_state_r16_out), .I1(first_fail_detect_i_2_n_0), .I2(detect_pi_found_dqs), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(pi_dqs_found_all_bank), .I5(\dec_cnt[5]_i_10_n_0 ), .O(rst_dqs_find_i_6_n_0)); FDRE rst_dqs_find_r1_reg (.C(CLK), .CE(1'b1), .D(rst_dqs_find_r1_reg_0), .Q(rst_dqs_find_r1), .R(1'b0)); FDRE rst_dqs_find_r2_reg (.C(CLK), .CE(1'b1), .D(rst_dqs_find_r1), .Q(rst_dqs_find_r2), .R(1'b0)); FDRE rst_dqs_find_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_fine_adj_state_r_reg[1]_0 ), .Q(rst_dqs_find_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair277" *) LUT4 #( .INIT(16'h4055)) \stable_pass_cnt[0]_i_1 (.I0(\stable_pass_cnt_reg_n_0_[0] ), .I1(pi_dqs_found_all_bank), .I2(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I3(detect_pi_found_dqs), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair277" *) LUT5 #( .INIT(32'h60006666)) \stable_pass_cnt[1]_i_1 (.I0(stable_pass_cnt_reg__0[1]), .I1(\stable_pass_cnt_reg_n_0_[0] ), .I2(pi_dqs_found_all_bank), .I3(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I4(detect_pi_found_dqs), .O(p_0_in__1[1])); LUT6 #( .INIT(64'h7800000078787878)) \stable_pass_cnt[2]_i_1 (.I0(\stable_pass_cnt_reg_n_0_[0] ), .I1(stable_pass_cnt_reg__0[1]), .I2(stable_pass_cnt_reg__0[2]), .I3(pi_dqs_found_all_bank), .I4(\pi_dqs_found_all_bank_r_reg[1]_0 ), .I5(detect_pi_found_dqs), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair273" *) LUT5 #( .INIT(32'h15554000)) \stable_pass_cnt[3]_i_1 (.I0(fine_adj_state_r144_out), .I1(stable_pass_cnt_reg__0[2]), .I2(stable_pass_cnt_reg__0[1]), .I3(\stable_pass_cnt_reg_n_0_[0] ), .I4(stable_pass_cnt_reg__0[3]), .O(\stable_pass_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h000000007FFF8000)) \stable_pass_cnt[4]_i_1 (.I0(\stable_pass_cnt_reg_n_0_[0] ), .I1(stable_pass_cnt_reg__0[1]), .I2(stable_pass_cnt_reg__0[2]), .I3(stable_pass_cnt_reg__0[3]), .I4(stable_pass_cnt_reg__0[4]), .I5(fine_adj_state_r144_out), .O(p_0_in__1[4])); LUT5 #( .INIT(32'h00200000)) \stable_pass_cnt[5]_i_1 (.I0(\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]), .I1(\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]), .I2(\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]), .I3(\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]), .I4(detect_pi_found_dqs), .O(stable_pass_cnt)); LUT5 #( .INIT(32'h15554000)) \stable_pass_cnt[5]_i_2 (.I0(fine_adj_state_r144_out), .I1(stable_pass_cnt_reg__0[4]), .I2(stable_pass_cnt_reg__0[3]), .I3(\stable_pass_cnt[5]_i_3_n_0 ), .I4(stable_pass_cnt_reg__0[5]), .O(\stable_pass_cnt[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair273" *) LUT3 #( .INIT(8'h80)) \stable_pass_cnt[5]_i_3 (.I0(stable_pass_cnt_reg__0[2]), .I1(stable_pass_cnt_reg__0[1]), .I2(\stable_pass_cnt_reg_n_0_[0] ), .O(\stable_pass_cnt[5]_i_3_n_0 )); FDRE \stable_pass_cnt_reg[0] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[0]), .Q(\stable_pass_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \stable_pass_cnt_reg[1] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[1]), .Q(stable_pass_cnt_reg__0[1]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \stable_pass_cnt_reg[2] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[2]), .Q(stable_pass_cnt_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \stable_pass_cnt_reg[3] (.C(CLK), .CE(stable_pass_cnt), .D(\stable_pass_cnt[3]_i_1_n_0 ), .Q(stable_pass_cnt_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \stable_pass_cnt_reg[4] (.C(CLK), .CE(stable_pass_cnt), .D(p_0_in__1[4]), .Q(stable_pass_cnt_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE \stable_pass_cnt_reg[5] (.C(CLK), .CE(stable_pass_cnt), .D(\stable_pass_cnt[5]_i_2_n_0 ), .Q(stable_pass_cnt_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__2)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_init (prbs_rdlvl_done_r1, prech_done, rdlvl_start_pre, rdlvl_start_dly0_r, in0, out, cnt_cmd_done_r, wrlvl_done_r1, prbs_last_byte_done_r, prech_pending_r_reg_0, pi_calib_done, wrcal_resume_r, complex_ocal_reset_rd_addr, wl_sm_start, wrcal_rd_wait, wrcal_sanity_chk, detect_pi_found_dqs, mpr_end_if_reset, init_complete_r1_reg_0, calib_complete, cnt_pwron_reset_done_r, cnt_pwron_cke_done_r, pi_dqs_found_done_r1, complex_act_start, \oclkdelay_ref_cnt_reg[13]_0 , cnt_txpr_done_r, cnt_dllk_zqinit_done_r, cnt_init_mr_done_r, ddr2_refresh_flag_r, ddr2_pre_flag_r_reg_0, cnt_init_af_done_r, burst_addr_r_reg_0, prech_pending_r, rdlvl_stg1_start_r_reg, ocal_last_byte_done, \rd_ptr_timing_reg[0] , phy_dout, reset_if_reg, oclk_calib_resume_level_reg_0, Q, \odd_cwl.phy_cas_n_reg[1]_0 , \cnt_init_mr_r_reg[1]_0 , \init_state_r_reg[1]_0 , cnt_init_mr_r, complex_oclkdelay_calib_start_int_reg_0, \reg_ctrl_cnt_r_reg[3]_0 , \one_rank.stg1_wr_done_reg_0 , \init_state_r_reg[2]_0 , mem_init_done_r, \victim_sel_rotate.sel_reg[31] , new_cnt_dqs_r_reg, prbs_rdlvl_start_r_reg, first_wrcal_pat_r, D2, D0, D3, D5, D6, D1, \rd_ptr_timing_reg[0]_0 , D7, D8, \rd_ptr_timing_reg[0]_1 , \my_empty_reg[7] , \my_empty_reg[7]_0 , \my_empty_reg[7]_1 , D4, \my_empty_reg[7]_2 , \my_empty_reg[7]_3 , \my_empty_reg[7]_4 , \my_empty_reg[7]_5 , \rd_ptr_timing_reg[0]_2 , D9, \my_empty_reg[7]_6 , \my_empty_reg[7]_7 , \my_empty_reg[7]_8 , \my_empty_reg[7]_9 , \my_empty_reg[7]_10 , \my_empty_reg[7]_11 , \my_empty_reg[7]_12 , \my_empty_reg[7]_13 , \my_empty_reg[7]_14 , \my_empty_reg[7]_15 , \my_empty_reg[7]_16 , \my_empty_reg[7]_17 , \my_empty_reg[7]_18 , \my_empty_reg[7]_19 , \my_empty_reg[7]_20 , \my_empty_reg[7]_21 , \my_empty_reg[7]_22 , \my_empty_reg[7]_23 , \my_empty_reg[7]_24 , \my_empty_reg[7]_25 , \my_empty_reg[7]_26 , \my_empty_reg[7]_27 , \my_empty_reg[7]_28 , \my_empty_reg[7]_29 , \my_empty_reg[7]_30 , \my_empty_reg[7]_31 , \my_empty_reg[7]_32 , \my_empty_reg[7]_33 , \my_empty_reg[7]_34 , \my_empty_reg[7]_35 , \my_empty_reg[7]_36 , \my_empty_reg[7]_37 , lim_start_r_reg, cal1_state_r1535_out, mpr_rdlvl_start_r_reg, E, \cnt_shift_r_reg[0] , cnt_init_mr_r1, prech_pending_r_reg_1, rdlvl_start_pre_reg_0, read_calib_reg_0, temp_lmr_done, stg1_wr_done, \back_to_back_reads_4_1.num_reads_reg[0]_0 , \back_to_back_reads_4_1.num_reads_reg[1]_0 , \init_state_r_reg[4]_0 , burst_addr_r_reg_1, oclkdelay_int_ref_req_reg_0, \init_state_r_reg[5]_0 , ddr2_pre_flag_r_reg_1, ddr2_refresh_flag_r_reg_0, \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 , \complex_row_cnt_ocal_reg[0]_0 , ddr3_lm_done_r, \row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 , cnt_pwron_reset_done_r_reg_0, \cnt_pwron_r_reg[7]_0 , cnt_pwron_cke_done_r_reg_0, \cnt_txpr_r_reg[2]_0 , mem_init_done_r_reg_0, mem_init_done_r_reg_1, \init_state_r_reg[0]_0 , rdlvl_stg1_start_int, \init_state_r_reg[2]_1 , cnt_txpr_done_r_reg_0, \pi_dqs_found_all_bank_reg[1] , dqs_found_start_r_reg, mux_wrdata_en, mux_cmd_wren, mux_reset_n, \data_offset_1_i1_reg[5] , \rd_ptr_timing_reg[0]_3 , \my_full_reg[3] , \phy_ctl_wd_i1_reg[24] , \my_empty_reg[7]_38 , \my_empty_reg[7]_39 , \my_empty_reg[7]_40 , \my_empty_reg[7]_41 , \samples_cnt_r_reg[11] , \wrcal_dqs_cnt_r_reg[0] , \rd_addr_reg_rep[7] , \rd_addr_reg[0] , cnt_init_af_r, wrlvl_final_if_rst, wr_level_start_r_reg, wrcal_start_reg_0, phy_write_calib, phy_read_calib, first_rdlvl_pat_r, prbs_rdlvl_done_reg_rep, CLK, rdlvl_stg1_done_int_reg, A_rst_primitives_reg, rstdiv0_sync_r1_reg_rep__12, wr_level_done_reg, prbs_last_byte_done, wrlvl_rank_done, prbs_rdlvl_done_pulse0, reset_rd_addr0, prech_req, wrcal_resume_w, rstdiv0_sync_r1_reg_rep__11, rdlvl_last_byte_done, dqs_found_done_r_reg, rstdiv0_sync_r1_reg_rep__10, cnt_pwron_cke_done_r_reg_1, cnt_txpr_done_r_reg_1, cnt_dllk_zqinit_done_r_reg_0, cnt_init_mr_done_r_reg_0, cnt_cmd_done_r_reg_0, ddr2_pre_flag_r_reg_2, cnt_init_af_done_r_reg_0, burst_addr_r_reg_2, prech_req_posedge_r_reg_0, \init_state_r_reg[0]_1 , \rdlvl_start_dly0_r_reg[14]_0 , \init_state_r_reg[6]_0 , \cnt_pwron_r_reg[7]_1 , \init_state_r_reg[6]_1 , oclkdelay_center_calib_done_r_reg, rdlvl_stg1_done_int_reg_0, oclkdelay_calib_done_r_reg, oclkdelay_calib_done_r_reg_0, \dout_o_reg[11] , \dout_o_reg[11]_0 , D, wrcal_done_reg, \dout_o_reg[9] , \dout_o_reg[9]_0 , \dout_o_reg[11]_1 , \dout_o_reg[11]_2 , \dout_o_reg[13] , \dout_o_reg[13]_0 , wrcal_done_reg_0, \dout_o_reg[9]_1 , \dout_o_reg[9]_2 , \dout_o_reg[9]_3 , \dout_o_reg[9]_4 , \dout_o_reg[13]_1 , \dout_o_reg[13]_2 , \dout_o_reg[1] , \dout_o_reg[1]_0 , \dout_o_reg[13]_3 , \dout_o_reg[13]_4 , oclkdelay_calib_done_r_reg_1, \dout_o_reg[11]_3 , \dout_o_reg[11]_4 , \dout_o_reg[13]_5 , \dout_o_reg[13]_6 , \dout_o_reg[15] , \dout_o_reg[7] , \dout_o_reg[15]_0 , \dout_o_reg[15]_1 , \dout_o_reg[7]_0 , \dout_o_reg[15]_2 , wrcal_done_reg_1, \dout_o_reg[3] , \dout_o_reg[3]_0 , \dout_o_reg[7]_1 , \dout_o_reg[7]_2 , \dout_o_reg[8] , \dout_o_reg[8]_0 , \dout_o_reg[14] , \dout_o_reg[14]_0 , \dout_o_reg[6] , \dout_o_reg[14]_1 , \dout_o_reg[14]_2 , first_rdlvl_pat_r_reg_0, wrcal_done_reg_2, \dout_o_reg[2] , \dout_o_reg[2]_0 , \dout_o_reg[4] , \dout_o_reg[4]_0 , \dout_o_reg[8]_1 , \dout_o_reg[8]_2 , \dout_o_reg[10] , \dout_o_reg[10]_0 , \dout_o_reg[8]_3 , \dout_o_reg[8]_4 , \dout_o_reg[12] , \dout_o_reg[12]_0 , wrcal_done_reg_3, wrcal_done_reg_4, wrcal_done_reg_5, wrcal_done_reg_6, wrcal_done_reg_7, wrcal_done_reg_8, init_calib_complete_reg_rep__13, init_calib_complete_reg_rep__12, rstdiv0_sync_r1_reg_rep__25, reset_if_r9, prbs_rdlvl_done_reg, reset_if, delay_done_r4_reg, dqs_found_done_r_reg_0, wrcal_done_reg_9, oclkdelay_center_calib_start_r_reg, oclk_calib_resume_r_reg, prbs_rdlvl_done_reg_rep_0, complex_oclk_calib_resume, pi_dqs_found_rank_done, wrcal_sanity_chk_done_reg, wrcal_done_reg_10, wrlvl_byte_redo, wrcal_prech_req, \init_state_r_reg[1]_1 , prbs_rdlvl_start_r, oclkdelay_calib_done_r_reg_2, mc_cas_n, init_calib_complete_reg_rep__6, \rd_ptr_reg[3] , \my_empty_reg[1] , mem_out, \my_empty_reg[1]_0 , mc_ras_n, mc_odt, \rd_ptr_reg[3]_0 , \my_empty_reg[1]_1 , mc_cke, mc_we_n, \cmd_pipe_plus.mc_address_reg[42] , \rd_ptr_reg[3]_1 , \my_empty_reg[1]_2 , init_calib_complete_reg_rep__5, \cmd_pipe_plus.mc_bank_reg[8] , \write_buffer.wr_buf_out_data_reg[255] , \rd_ptr_reg[3]_2 , \my_empty_reg[1]_3 , \rd_ptr_reg[3]_3 , \my_empty_reg[1]_4 , init_calib_complete_reg_rep__4, \rd_ptr_reg[3]_4 , \my_empty_reg[1]_5 , \rd_ptr_reg[3]_5 , \my_empty_reg[1]_6 , init_calib_complete_reg_rep__3, init_calib_complete_reg_rep__2, init_calib_complete_reg_rep__1, init_calib_complete_reg_rep__0, init_calib_complete_reg_rep, \rd_byte_data_offset_reg[0][3] , init_dqsfound_done_r2, \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] , \rd_byte_data_offset_reg[0][9] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] , mpr_rdlvl_start_r, phy_rddata_en_1, mpr_rdlvl_done_r_reg, \cnt_shift_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__23, \mcGo_r_reg[15] , ck_addr_cmd_delay_done, prbs_rdlvl_done_reg_0, wrlvl_final_mux, mpr_rdlvl_done_r_reg_0, \init_state_r_reg[2]_2 , rstdiv0_sync_r1_reg_rep__24, rdlvl_pi_incdec, dqs_found_prech_req, prbs_rdlvl_prech_req_reg, complex_ocal_ref_req, rdlvl_prech_req, complex_pi_incdec_done, wrcal_done_reg_11, rdlvl_stg1_done_int_reg_1, phy_if_empty_r_reg, wrcal_sanity_chk_done_reg_0, rdlvl_stg1_done_int_reg_2, oclkdelay_calib_done_r_reg_3, lim2init_prech_req, ocd_prech_req, oclkdelay_calib_done_r_reg_4, cnt_cmd_done_r_reg_1, oclkdelay_center_calib_start_r_reg_0, oclk_calib_resume_r_reg_0, mpr_rdlvl_done_r_reg_1, dqs_found_done_r_reg_1, wrlvl_byte_redo_reg, mpr_rdlvl_done_r_reg_2, oclkdelay_center_calib_done_r_reg_0, complex_victim_inc_reg, complex_ocal_num_samples_done_r, reset_rd_addr, dqs_found_done_r_reg_2, prbs_last_byte_done_reg, \rd_victim_sel_reg[1] , \rd_victim_sel_reg[0] , \rd_victim_sel_reg[2] , cnt_init_af_done_r_reg_1, num_samples_done_r, complex_init_pi_dec_done, done_r_reg, rdlvl_stg1_rank_done, write_request_r_reg, complex_ocal_rd_victim_sel, prbs_rdlvl_done_reg_rep_1, prbs_rdlvl_done_reg_rep_2, wrlvl_final_mux_reg, oclkdelay_calib_done_r_reg_5, wrlvl_byte_redo_reg_0, mem_init_done_r_reg_2, rdlvl_stg1_done_int_reg_3, wrlvl_final_mux_reg_0, prbs_rdlvl_done_reg_rep_3, mpr_last_byte_done, rdlvl_stg1_done_int_reg_4, \dout_o_reg[0] , \dout_o_reg[0]_0 , \pi_dqs_found_all_bank_reg[1]_0 , mc_wrdata_en, init_calib_complete_reg_rep__14, \cmd_pipe_plus.mc_data_offset_1_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , mc_cmd, \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[5] , init_calib_complete_reg_rep__11, init_calib_complete_reg_rep__10, init_calib_complete_reg_rep__9, init_calib_complete_reg_rep__8, init_calib_complete_reg_rep__7, \samples_cnt_r_reg[11]_0 , wrcal_sanity_chk_r_reg, \rd_addr_reg[3] , rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__24_0, done_dqs_tap_inc, p_81_in, rstdiv0_sync_r1_reg_rep__24_1, pi_dqs_found_done_r1_reg_0, pi_dqs_found_done_r1_reg_1, pi_dqs_found_done_r1_reg_2, pi_dqs_found_done_r1_reg_3, pi_dqs_found_done_r1_reg_4, pi_dqs_found_done_r1_reg_5, pi_dqs_found_done_r1_reg_6, pi_dqs_found_done_r1_reg_7, rstdiv0_sync_r1_reg_rep__19, rstdiv0_sync_r1_reg_rep__18); output prbs_rdlvl_done_r1; output prech_done; output rdlvl_start_pre; output [0:0]rdlvl_start_dly0_r; output in0; output out; output cnt_cmd_done_r; output wrlvl_done_r1; output prbs_last_byte_done_r; output prech_pending_r_reg_0; output pi_calib_done; output wrcal_resume_r; output complex_ocal_reset_rd_addr; output wl_sm_start; output wrcal_rd_wait; output wrcal_sanity_chk; output detect_pi_found_dqs; output mpr_end_if_reset; output init_complete_r1_reg_0; output calib_complete; output cnt_pwron_reset_done_r; output cnt_pwron_cke_done_r; output pi_dqs_found_done_r1; output complex_act_start; output \oclkdelay_ref_cnt_reg[13]_0 ; output cnt_txpr_done_r; output cnt_dllk_zqinit_done_r; output cnt_init_mr_done_r; output ddr2_refresh_flag_r; output ddr2_pre_flag_r_reg_0; output cnt_init_af_done_r; output burst_addr_r_reg_0; output prech_pending_r; output rdlvl_stg1_start_r_reg; output ocal_last_byte_done; output [33:0]\rd_ptr_timing_reg[0] ; output [31:0]phy_dout; output reset_if_reg; output oclk_calib_resume_level_reg_0; output [5:0]Q; output \odd_cwl.phy_cas_n_reg[1]_0 ; output \cnt_init_mr_r_reg[1]_0 ; output \init_state_r_reg[1]_0 ; output [1:0]cnt_init_mr_r; output complex_oclkdelay_calib_start_int_reg_0; output \reg_ctrl_cnt_r_reg[3]_0 ; output \one_rank.stg1_wr_done_reg_0 ; output \init_state_r_reg[2]_0 ; output mem_init_done_r; output [7:0]\victim_sel_rotate.sel_reg[31] ; output new_cnt_dqs_r_reg; output prbs_rdlvl_start_r_reg; output first_wrcal_pat_r; output [0:0]D2; output [0:0]D0; output [0:0]D3; output [3:0]D5; output [3:0]D6; output [0:0]D1; output [7:0]\rd_ptr_timing_reg[0]_0 ; output [3:0]D7; output [3:0]D8; output [7:0]\rd_ptr_timing_reg[0]_1 ; output [3:0]\my_empty_reg[7] ; output [3:0]\my_empty_reg[7]_0 ; output [3:0]\my_empty_reg[7]_1 ; output [3:0]D4; output [3:0]\my_empty_reg[7]_2 ; output [3:0]\my_empty_reg[7]_3 ; output [3:0]\my_empty_reg[7]_4 ; output [3:0]\my_empty_reg[7]_5 ; output [3:0]\rd_ptr_timing_reg[0]_2 ; output [3:0]D9; output [7:0]\my_empty_reg[7]_6 ; output [7:0]\my_empty_reg[7]_7 ; output [7:0]\my_empty_reg[7]_8 ; output [7:0]\my_empty_reg[7]_9 ; output [7:0]\my_empty_reg[7]_10 ; output [7:0]\my_empty_reg[7]_11 ; output [7:0]\my_empty_reg[7]_12 ; output [7:0]\my_empty_reg[7]_13 ; output [7:0]\my_empty_reg[7]_14 ; output [7:0]\my_empty_reg[7]_15 ; output [7:0]\my_empty_reg[7]_16 ; output [7:0]\my_empty_reg[7]_17 ; output [7:0]\my_empty_reg[7]_18 ; output [7:0]\my_empty_reg[7]_19 ; output [7:0]\my_empty_reg[7]_20 ; output [7:0]\my_empty_reg[7]_21 ; output [7:0]\my_empty_reg[7]_22 ; output [7:0]\my_empty_reg[7]_23 ; output [7:0]\my_empty_reg[7]_24 ; output [7:0]\my_empty_reg[7]_25 ; output [7:0]\my_empty_reg[7]_26 ; output [7:0]\my_empty_reg[7]_27 ; output [7:0]\my_empty_reg[7]_28 ; output [7:0]\my_empty_reg[7]_29 ; output [7:0]\my_empty_reg[7]_30 ; output [7:0]\my_empty_reg[7]_31 ; output [7:0]\my_empty_reg[7]_32 ; output [7:0]\my_empty_reg[7]_33 ; output [7:0]\my_empty_reg[7]_34 ; output [7:0]\my_empty_reg[7]_35 ; output [7:0]\my_empty_reg[7]_36 ; output [7:0]\my_empty_reg[7]_37 ; output lim_start_r_reg; output cal1_state_r1535_out; output mpr_rdlvl_start_r_reg; output [0:0]E; output [0:0]\cnt_shift_r_reg[0] ; output cnt_init_mr_r1; output prech_pending_r_reg_1; output rdlvl_start_pre_reg_0; output read_calib_reg_0; output temp_lmr_done; output stg1_wr_done; output \back_to_back_reads_4_1.num_reads_reg[0]_0 ; output \back_to_back_reads_4_1.num_reads_reg[1]_0 ; output \init_state_r_reg[4]_0 ; output burst_addr_r_reg_1; output oclkdelay_int_ref_req_reg_0; output \init_state_r_reg[5]_0 ; output ddr2_pre_flag_r_reg_1; output ddr2_refresh_flag_r_reg_0; output \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ; output \complex_row_cnt_ocal_reg[0]_0 ; output ddr3_lm_done_r; output \row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ; output cnt_pwron_reset_done_r_reg_0; output [3:0]\cnt_pwron_r_reg[7]_0 ; output cnt_pwron_cke_done_r_reg_0; output [2:0]\cnt_txpr_r_reg[2]_0 ; output [1:0]mem_init_done_r_reg_0; output mem_init_done_r_reg_1; output \init_state_r_reg[0]_0 ; output rdlvl_stg1_start_int; output \init_state_r_reg[2]_1 ; output cnt_txpr_done_r_reg_0; output \pi_dqs_found_all_bank_reg[1] ; output dqs_found_start_r_reg; output mux_wrdata_en; output mux_cmd_wren; output mux_reset_n; output [5:0]\data_offset_1_i1_reg[5] ; output [1:0]\rd_ptr_timing_reg[0]_3 ; output [1:0]\my_full_reg[3] ; output [10:0]\phy_ctl_wd_i1_reg[24] ; output [63:0]\my_empty_reg[7]_38 ; output [63:0]\my_empty_reg[7]_39 ; output [63:0]\my_empty_reg[7]_40 ; output [63:0]\my_empty_reg[7]_41 ; output [0:0]\samples_cnt_r_reg[11] ; output \wrcal_dqs_cnt_r_reg[0] ; output \rd_addr_reg_rep[7] ; output [0:0]\rd_addr_reg[0] ; output [1:0]cnt_init_af_r; output wrlvl_final_if_rst; output wr_level_start_r_reg; output wrcal_start_reg_0; output phy_write_calib; output phy_read_calib; output first_rdlvl_pat_r; input prbs_rdlvl_done_reg_rep; input CLK; input rdlvl_stg1_done_int_reg; input A_rst_primitives_reg; input rstdiv0_sync_r1_reg_rep__12; input wr_level_done_reg; input prbs_last_byte_done; input wrlvl_rank_done; input prbs_rdlvl_done_pulse0; input reset_rd_addr0; input prech_req; input wrcal_resume_w; input [0:0]rstdiv0_sync_r1_reg_rep__11; input rdlvl_last_byte_done; input dqs_found_done_r_reg; input rstdiv0_sync_r1_reg_rep__10; input cnt_pwron_cke_done_r_reg_1; input cnt_txpr_done_r_reg_1; input cnt_dllk_zqinit_done_r_reg_0; input cnt_init_mr_done_r_reg_0; input cnt_cmd_done_r_reg_0; input ddr2_pre_flag_r_reg_2; input cnt_init_af_done_r_reg_0; input burst_addr_r_reg_2; input prech_req_posedge_r_reg_0; input \init_state_r_reg[0]_1 ; input \rdlvl_start_dly0_r_reg[14]_0 ; input \init_state_r_reg[6]_0 ; input \cnt_pwron_r_reg[7]_1 ; input \init_state_r_reg[6]_1 ; input oclkdelay_center_calib_done_r_reg; input rdlvl_stg1_done_int_reg_0; input oclkdelay_calib_done_r_reg; input oclkdelay_calib_done_r_reg_0; input \dout_o_reg[11] ; input \dout_o_reg[11]_0 ; input [1:0]D; input wrcal_done_reg; input \dout_o_reg[9] ; input \dout_o_reg[9]_0 ; input \dout_o_reg[11]_1 ; input \dout_o_reg[11]_2 ; input \dout_o_reg[13] ; input \dout_o_reg[13]_0 ; input wrcal_done_reg_0; input \dout_o_reg[9]_1 ; input \dout_o_reg[9]_2 ; input \dout_o_reg[9]_3 ; input \dout_o_reg[9]_4 ; input \dout_o_reg[13]_1 ; input \dout_o_reg[13]_2 ; input \dout_o_reg[1] ; input \dout_o_reg[1]_0 ; input \dout_o_reg[13]_3 ; input \dout_o_reg[13]_4 ; input oclkdelay_calib_done_r_reg_1; input \dout_o_reg[11]_3 ; input \dout_o_reg[11]_4 ; input \dout_o_reg[13]_5 ; input \dout_o_reg[13]_6 ; input \dout_o_reg[15] ; input \dout_o_reg[7] ; input \dout_o_reg[15]_0 ; input \dout_o_reg[15]_1 ; input \dout_o_reg[7]_0 ; input \dout_o_reg[15]_2 ; input wrcal_done_reg_1; input \dout_o_reg[3] ; input \dout_o_reg[3]_0 ; input \dout_o_reg[7]_1 ; input \dout_o_reg[7]_2 ; input \dout_o_reg[8] ; input \dout_o_reg[8]_0 ; input \dout_o_reg[14] ; input \dout_o_reg[14]_0 ; input \dout_o_reg[6] ; input \dout_o_reg[14]_1 ; input \dout_o_reg[14]_2 ; input first_rdlvl_pat_r_reg_0; input wrcal_done_reg_2; input \dout_o_reg[2] ; input \dout_o_reg[2]_0 ; input \dout_o_reg[4] ; input \dout_o_reg[4]_0 ; input \dout_o_reg[8]_1 ; input \dout_o_reg[8]_2 ; input \dout_o_reg[10] ; input \dout_o_reg[10]_0 ; input \dout_o_reg[8]_3 ; input \dout_o_reg[8]_4 ; input \dout_o_reg[12] ; input \dout_o_reg[12]_0 ; input wrcal_done_reg_3; input wrcal_done_reg_4; input wrcal_done_reg_5; input wrcal_done_reg_6; input wrcal_done_reg_7; input wrcal_done_reg_8; input init_calib_complete_reg_rep__13; input init_calib_complete_reg_rep__12; input rstdiv0_sync_r1_reg_rep__25; input reset_if_r9; input prbs_rdlvl_done_reg; input reset_if; input delay_done_r4_reg; input dqs_found_done_r_reg_0; input wrcal_done_reg_9; input oclkdelay_center_calib_start_r_reg; input oclk_calib_resume_r_reg; input prbs_rdlvl_done_reg_rep_0; input complex_oclk_calib_resume; input pi_dqs_found_rank_done; input wrcal_sanity_chk_done_reg; input wrcal_done_reg_10; input wrlvl_byte_redo; input wrcal_prech_req; input \init_state_r_reg[1]_1 ; input prbs_rdlvl_start_r; input oclkdelay_calib_done_r_reg_2; input [0:0]mc_cas_n; input init_calib_complete_reg_rep__6; input [33:0]\rd_ptr_reg[3] ; input \my_empty_reg[1] ; input [1:0]mem_out; input \my_empty_reg[1]_0 ; input [0:0]mc_ras_n; input [0:0]mc_odt; input [7:0]\rd_ptr_reg[3]_0 ; input \my_empty_reg[1]_1 ; input [0:0]mc_cke; input [0:0]mc_we_n; input [33:0]\cmd_pipe_plus.mc_address_reg[42] ; input [31:0]\rd_ptr_reg[3]_1 ; input \my_empty_reg[1]_2 ; input init_calib_complete_reg_rep__5; input [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; input [255:0]\write_buffer.wr_buf_out_data_reg[255] ; input [63:0]\rd_ptr_reg[3]_2 ; input \my_empty_reg[1]_3 ; input [63:0]\rd_ptr_reg[3]_3 ; input \my_empty_reg[1]_4 ; input init_calib_complete_reg_rep__4; input [63:0]\rd_ptr_reg[3]_4 ; input \my_empty_reg[1]_5 ; input [63:0]\rd_ptr_reg[3]_5 ; input \my_empty_reg[1]_6 ; input init_calib_complete_reg_rep__3; input init_calib_complete_reg_rep__2; input init_calib_complete_reg_rep__1; input init_calib_complete_reg_rep__0; input init_calib_complete_reg_rep; input [1:0]\rd_byte_data_offset_reg[0][3] ; input init_dqsfound_done_r2; input [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ; input [1:0]\rd_byte_data_offset_reg[0][9] ; input [1:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ; input mpr_rdlvl_start_r; input phy_rddata_en_1; input mpr_rdlvl_done_r_reg; input \cnt_shift_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__23; input \mcGo_r_reg[15] ; input ck_addr_cmd_delay_done; input prbs_rdlvl_done_reg_0; input wrlvl_final_mux; input mpr_rdlvl_done_r_reg_0; input \init_state_r_reg[2]_2 ; input rstdiv0_sync_r1_reg_rep__24; input rdlvl_pi_incdec; input dqs_found_prech_req; input prbs_rdlvl_prech_req_reg; input complex_ocal_ref_req; input rdlvl_prech_req; input complex_pi_incdec_done; input wrcal_done_reg_11; input rdlvl_stg1_done_int_reg_1; input phy_if_empty_r_reg; input wrcal_sanity_chk_done_reg_0; input rdlvl_stg1_done_int_reg_2; input oclkdelay_calib_done_r_reg_3; input lim2init_prech_req; input ocd_prech_req; input oclkdelay_calib_done_r_reg_4; input cnt_cmd_done_r_reg_1; input oclkdelay_center_calib_start_r_reg_0; input oclk_calib_resume_r_reg_0; input mpr_rdlvl_done_r_reg_1; input dqs_found_done_r_reg_1; input wrlvl_byte_redo_reg; input mpr_rdlvl_done_r_reg_2; input oclkdelay_center_calib_done_r_reg_0; input complex_victim_inc_reg; input complex_ocal_num_samples_done_r; input reset_rd_addr; input dqs_found_done_r_reg_2; input prbs_last_byte_done_reg; input \rd_victim_sel_reg[1] ; input \rd_victim_sel_reg[0] ; input \rd_victim_sel_reg[2] ; input cnt_init_af_done_r_reg_1; input num_samples_done_r; input complex_init_pi_dec_done; input done_r_reg; input rdlvl_stg1_rank_done; input write_request_r_reg; input [2:0]complex_ocal_rd_victim_sel; input prbs_rdlvl_done_reg_rep_1; input prbs_rdlvl_done_reg_rep_2; input wrlvl_final_mux_reg; input oclkdelay_calib_done_r_reg_5; input wrlvl_byte_redo_reg_0; input mem_init_done_r_reg_2; input rdlvl_stg1_done_int_reg_3; input wrlvl_final_mux_reg_0; input prbs_rdlvl_done_reg_rep_3; input mpr_last_byte_done; input rdlvl_stg1_done_int_reg_4; input \dout_o_reg[0] ; input \dout_o_reg[0]_0 ; input [0:0]\pi_dqs_found_all_bank_reg[1]_0 ; input mc_wrdata_en; input init_calib_complete_reg_rep__14; input \cmd_pipe_plus.mc_data_offset_1_reg[0] ; input \cmd_pipe_plus.mc_data_offset_1_reg[1] ; input \cmd_pipe_plus.mc_data_offset_1_reg[2] ; input \cmd_pipe_plus.mc_data_offset_1_reg[3] ; input \cmd_pipe_plus.mc_data_offset_1_reg[4] ; input \cmd_pipe_plus.mc_data_offset_1_reg[5] ; input [1:0]mc_cmd; input \cmd_pipe_plus.mc_data_offset_reg[0] ; input \cmd_pipe_plus.mc_data_offset_reg[1] ; input \cmd_pipe_plus.mc_data_offset_reg[2] ; input \cmd_pipe_plus.mc_data_offset_reg[3] ; input \cmd_pipe_plus.mc_data_offset_reg[4] ; input \cmd_pipe_plus.mc_data_offset_reg[5] ; input init_calib_complete_reg_rep__11; input init_calib_complete_reg_rep__10; input init_calib_complete_reg_rep__9; input init_calib_complete_reg_rep__8; input init_calib_complete_reg_rep__7; input \samples_cnt_r_reg[11]_0 ; input wrcal_sanity_chk_r_reg; input [0:0]\rd_addr_reg[3] ; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__24_0; input done_dqs_tap_inc; input p_81_in; input rstdiv0_sync_r1_reg_rep__24_1; input pi_dqs_found_done_r1_reg_0; input pi_dqs_found_done_r1_reg_1; input pi_dqs_found_done_r1_reg_2; input pi_dqs_found_done_r1_reg_3; input pi_dqs_found_done_r1_reg_4; input pi_dqs_found_done_r1_reg_5; input pi_dqs_found_done_r1_reg_6; input pi_dqs_found_done_r1_reg_7; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [0:0]rstdiv0_sync_r1_reg_rep__18; wire A_rst_primitives_reg; wire CLK; wire [1:0]D; wire [0:0]D0; wire [0:0]D1; wire [0:0]D2; wire [0:0]D3; wire [3:0]D4; wire [3:0]D5; wire [3:0]D6; wire [3:0]D7; wire [3:0]D8; wire [3:0]D9; wire \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ; wire \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ; wire [0:0]E; wire [5:0]Q; wire \back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ; wire \back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ; wire \back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ; wire \back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ; wire \back_to_back_reads_4_1.num_reads_reg[0]_0 ; wire \back_to_back_reads_4_1.num_reads_reg[1]_0 ; wire [1:0]bank_w; wire burst_addr_r_reg_0; wire burst_addr_r_reg_1; wire burst_addr_r_reg_2; wire cal1_state_r1535_out; wire [3:3]calib_cke; wire [2:0]calib_cmd; wire \calib_cmd[0]_i_1_n_0 ; wire \calib_cmd[1]_i_1_n_0 ; wire \calib_cmd[2]_i_1_n_0 ; wire \calib_cmd[2]_i_2_n_0 ; wire \calib_cmd[2]_i_3_n_0 ; wire \calib_cmd[2]_i_4_n_0 ; wire \calib_cmd[2]_i_5_n_0 ; wire \calib_cmd[2]_i_6_n_0 ; wire \calib_cmd[2]_i_7_n_0 ; wire \calib_cmd[2]_i_8_n_0 ; wire calib_complete; wire calib_ctl_wren; wire calib_ctl_wren0; wire [5:0]calib_data_offset_0; wire \calib_data_offset_0[2]_i_1_n_0 ; wire \calib_data_offset_0[3]_i_1_n_0 ; wire \calib_data_offset_0[3]_i_2_n_0 ; wire \calib_data_offset_0[5]_i_1_n_0 ; wire [5:0]calib_data_offset_1; wire \calib_data_offset_1[2]_i_1_n_0 ; wire \calib_data_offset_1[3]_i_1_n_0 ; wire [0:0]calib_odt; wire \calib_odt[0]_i_1_n_0 ; wire \calib_odt[0]_i_2_n_0 ; wire \calib_odt[0]_i_3_n_0 ; wire \calib_odt[0]_i_4_n_0 ; wire \calib_seq[0]_i_1_n_0 ; wire \calib_seq[1]_i_1_n_0 ; wire calib_wrdata_en; wire ck_addr_cmd_delay_done; wire clear; wire [33:0]\cmd_pipe_plus.mc_address_reg[42] ; wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_reg[5] ; wire cnt_cmd_done_m7_r; wire cnt_cmd_done_m7_r_i_1_n_0; wire cnt_cmd_done_m7_r_i_2_n_0; wire cnt_cmd_done_r; wire cnt_cmd_done_r_i_1_n_0; wire cnt_cmd_done_r_reg_0; wire cnt_cmd_done_r_reg_1; wire \cnt_cmd_r[0]_i_1_n_0 ; wire \cnt_cmd_r[1]_i_1_n_0 ; wire \cnt_cmd_r[2]_i_1_n_0 ; wire \cnt_cmd_r[3]_i_1_n_0 ; wire \cnt_cmd_r[4]_i_1_n_0 ; wire \cnt_cmd_r[5]_i_1_n_0 ; wire \cnt_cmd_r[6]_i_1_n_0 ; wire \cnt_cmd_r[6]_i_2_n_0 ; wire \cnt_cmd_r[6]_i_3_n_0 ; wire \cnt_cmd_r[6]_i_4_n_0 ; wire \cnt_cmd_r[6]_i_5_n_0 ; wire \cnt_cmd_r_reg_n_0_[0] ; wire \cnt_cmd_r_reg_n_0_[1] ; wire \cnt_cmd_r_reg_n_0_[2] ; wire \cnt_cmd_r_reg_n_0_[3] ; wire \cnt_cmd_r_reg_n_0_[4] ; wire \cnt_cmd_r_reg_n_0_[5] ; wire \cnt_cmd_r_reg_n_0_[6] ; wire cnt_dllk_zqinit_done_r; wire cnt_dllk_zqinit_done_r_reg_0; wire cnt_dllk_zqinit_r; wire [5:0]cnt_dllk_zqinit_r_reg__0; wire cnt_init_af_done_r; wire cnt_init_af_done_r_reg_0; wire cnt_init_af_done_r_reg_1; wire [1:0]cnt_init_af_r; wire \cnt_init_af_r[0]_i_1_n_0 ; wire \cnt_init_af_r[1]_i_1_n_0 ; wire cnt_init_mr_done_r; wire cnt_init_mr_done_r_reg_0; wire [1:0]cnt_init_mr_r; wire cnt_init_mr_r1; wire \cnt_init_mr_r[0]_i_1_n_0 ; wire \cnt_init_mr_r[1]_i_1_n_0 ; wire \cnt_init_mr_r_reg[1]_0 ; wire [9:0]cnt_pwron_ce_r_reg__0; wire cnt_pwron_cke_done_r; wire cnt_pwron_cke_done_r_reg_0; wire cnt_pwron_cke_done_r_reg_1; wire \cnt_pwron_r[6]_i_2_n_0 ; wire \cnt_pwron_r[8]_i_2_n_0 ; wire [3:0]\cnt_pwron_r_reg[7]_0 ; wire \cnt_pwron_r_reg[7]_1 ; wire [8:2]cnt_pwron_r_reg__0; wire cnt_pwron_reset_done_r; wire cnt_pwron_reset_done_r_reg_0; wire [0:0]\cnt_shift_r_reg[0] ; wire \cnt_shift_r_reg[0]_0 ; wire cnt_txpr_done_r; wire cnt_txpr_done_r_reg_0; wire cnt_txpr_done_r_reg_1; wire \cnt_txpr_r[7]_i_3_n_0 ; wire [2:0]\cnt_txpr_r_reg[2]_0 ; wire [7:3]cnt_txpr_r_reg__0; wire complex_act_start; wire complex_act_start0; wire complex_address0; wire \complex_address[9]_i_2_n_0 ; wire \complex_address[9]_i_3_n_0 ; wire \complex_address[9]_i_4_n_0 ; wire \complex_address_reg_n_0_[0] ; wire \complex_address_reg_n_0_[1] ; wire \complex_address_reg_n_0_[2] ; wire \complex_address_reg_n_0_[3] ; wire \complex_address_reg_n_0_[4] ; wire \complex_address_reg_n_0_[5] ; wire \complex_address_reg_n_0_[6] ; wire \complex_address_reg_n_0_[7] ; wire \complex_address_reg_n_0_[8] ; wire \complex_address_reg_n_0_[9] ; wire complex_byte_rd_done; wire complex_byte_rd_done_i_1_n_0; wire complex_byte_rd_done_i_2_n_0; wire complex_init_pi_dec_done; wire complex_mask_lim_done; wire complex_mask_lim_done_i_1_n_0; wire \complex_num_reads[0]_i_1_n_0 ; wire \complex_num_reads[1]_i_1_n_0 ; wire \complex_num_reads[1]_i_2_n_0 ; wire \complex_num_reads[2]_i_1_n_0 ; wire \complex_num_reads[2]_i_2_n_0 ; wire \complex_num_reads[2]_i_3_n_0 ; wire \complex_num_reads[2]_i_4_n_0 ; wire \complex_num_reads[2]_i_5_n_0 ; wire \complex_num_reads[2]_i_6_n_0 ; wire \complex_num_reads[3]_i_1_n_0 ; wire \complex_num_reads[3]_i_2_n_0 ; wire \complex_num_reads[3]_i_3_n_0 ; wire \complex_num_reads[3]_i_4_n_0 ; wire \complex_num_reads[3]_i_5_n_0 ; wire \complex_num_reads[3]_i_6_n_0 ; wire \complex_num_reads[3]_i_7_n_0 ; wire \complex_num_reads[3]_i_8_n_0 ; wire \complex_num_reads_dec[3]_i_2_n_0 ; wire \complex_num_reads_dec[3]_i_4_n_0 ; wire \complex_num_reads_dec[3]_i_5_n_0 ; wire [3:0]complex_num_reads_dec_reg__0; wire \complex_num_reads_reg_n_0_[0] ; wire \complex_num_reads_reg_n_0_[1] ; wire \complex_num_reads_reg_n_0_[2] ; wire \complex_num_reads_reg_n_0_[3] ; wire \complex_num_writes[0]_i_1_n_0 ; wire \complex_num_writes[0]_i_2_n_0 ; wire \complex_num_writes[1]_i_1_n_0 ; wire \complex_num_writes[1]_i_2_n_0 ; wire \complex_num_writes[2]_i_1_n_0 ; wire \complex_num_writes[2]_i_2_n_0 ; wire \complex_num_writes[2]_i_3_n_0 ; wire \complex_num_writes[2]_i_4_n_0 ; wire \complex_num_writes[2]_i_5_n_0 ; wire \complex_num_writes[2]_i_6_n_0 ; wire \complex_num_writes[2]_i_7_n_0 ; wire \complex_num_writes[2]_i_8_n_0 ; wire \complex_num_writes[3]_i_1_n_0 ; wire \complex_num_writes[3]_i_2_n_0 ; wire \complex_num_writes[3]_i_3_n_0 ; wire \complex_num_writes[3]_i_4_n_0 ; wire \complex_num_writes[4]_i_10_n_0 ; wire \complex_num_writes[4]_i_11_n_0 ; wire \complex_num_writes[4]_i_12_n_0 ; wire \complex_num_writes[4]_i_13_n_0 ; wire \complex_num_writes[4]_i_14_n_0 ; wire \complex_num_writes[4]_i_15_n_0 ; wire \complex_num_writes[4]_i_1_n_0 ; wire \complex_num_writes[4]_i_2_n_0 ; wire \complex_num_writes[4]_i_3_n_0 ; wire \complex_num_writes[4]_i_4_n_0 ; wire \complex_num_writes[4]_i_5_n_0 ; wire \complex_num_writes[4]_i_6_n_0 ; wire \complex_num_writes[4]_i_7_n_0 ; wire \complex_num_writes[4]_i_8_n_0 ; wire \complex_num_writes[4]_i_9_n_0 ; wire \complex_num_writes_dec[4]_i_2_n_0 ; wire \complex_num_writes_dec[4]_i_4_n_0 ; wire \complex_num_writes_dec[4]_i_5_n_0 ; wire \complex_num_writes_dec[4]_i_6_n_0 ; wire [4:0]complex_num_writes_dec_reg__0; wire \complex_num_writes_reg_n_0_[0] ; wire \complex_num_writes_reg_n_0_[1] ; wire \complex_num_writes_reg_n_0_[2] ; wire \complex_num_writes_reg_n_0_[3] ; wire \complex_num_writes_reg_n_0_[4] ; wire complex_ocal_num_samples_done_r; wire complex_ocal_odt_ext; wire complex_ocal_odt_ext_i_1_n_0; wire complex_ocal_odt_ext_i_2_n_0; wire complex_ocal_odt_ext_i_3_n_0; wire complex_ocal_odt_ext_i_4_n_0; wire [2:0]complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_reset_rd_addr; wire complex_ocal_reset_rd_addr0; wire complex_ocal_reset_rd_addr_i_2_n_0; wire complex_ocal_reset_rd_addr_i_3_n_0; wire complex_ocal_wr_start; wire complex_ocal_wr_start_i_1_n_0; wire complex_oclk_calib_resume; wire complex_oclkdelay_calib_done_r1; wire complex_oclkdelay_calib_start_int; wire complex_oclkdelay_calib_start_int_i_1_n_0; wire complex_oclkdelay_calib_start_int_i_2_n_0; wire complex_oclkdelay_calib_start_int_reg_0; wire complex_oclkdelay_calib_start_r1; wire complex_oclkdelay_calib_start_r2; wire complex_odt_ext; wire complex_odt_ext_i_1_n_0; wire complex_pi_incdec_done; wire complex_row0_rd_done; wire complex_row0_rd_done1; wire complex_row0_rd_done_i_1_n_0; wire complex_row0_rd_done_i_2_n_0; wire complex_row0_wr_done; wire complex_row0_wr_done0; wire [2:0]complex_row1_rd_cnt; wire \complex_row1_rd_cnt[0]_i_1_n_0 ; wire \complex_row1_rd_cnt[1]_i_1_n_0 ; wire \complex_row1_rd_cnt[2]_i_1_n_0 ; wire complex_row1_rd_done; wire complex_row1_rd_done_i_1_n_0; wire complex_row1_rd_done_i_2_n_0; wire complex_row1_rd_done_r1; wire complex_row1_wr_done; wire complex_row_cnt; wire complex_row_cnt_ocal; wire complex_row_cnt_ocal0; wire \complex_row_cnt_ocal[7]_i_5_n_0 ; wire \complex_row_cnt_ocal[7]_i_6_n_0 ; wire \complex_row_cnt_ocal[7]_i_7_n_0 ; wire \complex_row_cnt_ocal[7]_i_8_n_0 ; wire \complex_row_cnt_ocal[7]_i_9_n_0 ; wire \complex_row_cnt_ocal_reg[0]_0 ; wire [7:0]complex_row_cnt_ocal_reg__0; wire complex_sample_cnt_inc; wire complex_sample_cnt_inc0; wire complex_sample_cnt_inc_i_2_n_0; wire complex_sample_cnt_inc_r1; wire complex_sample_cnt_inc_r2; wire complex_victim_inc_reg; wire \complex_wait_cnt[3]_i_1_n_0 ; wire \complex_wait_cnt[3]_i_3_n_0 ; wire [3:0]complex_wait_cnt_reg__0; wire complex_wr_done; wire [5:0]\data_offset_1_i1_reg[5] ; wire ddr2_pre_flag_r_reg_0; wire ddr2_pre_flag_r_reg_1; wire ddr2_pre_flag_r_reg_2; wire ddr2_refresh_flag_r; wire ddr2_refresh_flag_r_reg_0; wire ddr3_lm_done_r; wire ddr3_lm_done_r_i_1_n_0; wire ddr3_lm_done_r_i_2_n_0; wire delay_done_r4_reg; wire detect_pi_found_dqs; wire detect_pi_found_dqs0; wire done_dqs_tap_inc; wire done_r_reg; wire \dout_o_reg[0] ; wire \dout_o_reg[0]_0 ; wire \dout_o_reg[10] ; wire \dout_o_reg[10]_0 ; wire \dout_o_reg[11] ; wire \dout_o_reg[11]_0 ; wire \dout_o_reg[11]_1 ; wire \dout_o_reg[11]_2 ; wire \dout_o_reg[11]_3 ; wire \dout_o_reg[11]_4 ; wire \dout_o_reg[12] ; wire \dout_o_reg[12]_0 ; wire \dout_o_reg[13] ; wire \dout_o_reg[13]_0 ; wire \dout_o_reg[13]_1 ; wire \dout_o_reg[13]_2 ; wire \dout_o_reg[13]_3 ; wire \dout_o_reg[13]_4 ; wire \dout_o_reg[13]_5 ; wire \dout_o_reg[13]_6 ; wire \dout_o_reg[14] ; wire \dout_o_reg[14]_0 ; wire \dout_o_reg[14]_1 ; wire \dout_o_reg[14]_2 ; wire \dout_o_reg[15] ; wire \dout_o_reg[15]_0 ; wire \dout_o_reg[15]_1 ; wire \dout_o_reg[15]_2 ; wire \dout_o_reg[1] ; wire \dout_o_reg[1]_0 ; wire \dout_o_reg[2] ; wire \dout_o_reg[2]_0 ; wire \dout_o_reg[3] ; wire \dout_o_reg[3]_0 ; wire \dout_o_reg[4] ; wire \dout_o_reg[4]_0 ; wire \dout_o_reg[6] ; wire \dout_o_reg[7] ; wire \dout_o_reg[7]_0 ; wire \dout_o_reg[7]_1 ; wire \dout_o_reg[7]_2 ; wire \dout_o_reg[8] ; wire \dout_o_reg[8]_0 ; wire \dout_o_reg[8]_1 ; wire \dout_o_reg[8]_2 ; wire \dout_o_reg[8]_3 ; wire \dout_o_reg[8]_4 ; wire \dout_o_reg[9] ; wire \dout_o_reg[9]_0 ; wire \dout_o_reg[9]_1 ; wire \dout_o_reg[9]_2 ; wire \dout_o_reg[9]_3 ; wire \dout_o_reg[9]_4 ; wire [1:0]dqs_asrt_cnt; wire \dqs_asrt_cnt[0]_i_1_n_0 ; wire \dqs_asrt_cnt[1]_i_1_n_0 ; wire dqs_found_done_r_reg; wire dqs_found_done_r_reg_0; wire dqs_found_done_r_reg_1; wire dqs_found_done_r_reg_2; wire dqs_found_prech_req; wire dqs_found_start_r_reg; wire \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ; wire \en_cnt_div4.wrlvl_odt_i_1_n_0 ; wire \en_cnt_div4.wrlvl_odt_i_2_n_0 ; wire [4:0]enable_wrlvl_cnt; wire enable_wrlvl_cnt0; wire first_rdlvl_pat_r; wire first_rdlvl_pat_r_i_1_n_0; wire first_rdlvl_pat_r_reg_0; wire first_wrcal_pat_r; wire first_wrcal_pat_r_i_1_n_0; wire first_wrcal_pat_r_i_2_n_0; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ; wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ; wire \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ; wire [1:1]\gen_rnk[0].mr1_r_reg[0]_196 ; wire init_calib_complete_reg_rep; wire init_calib_complete_reg_rep__0; wire init_calib_complete_reg_rep__1; wire init_calib_complete_reg_rep__10; wire init_calib_complete_reg_rep__11; wire init_calib_complete_reg_rep__12; wire init_calib_complete_reg_rep__13; wire init_calib_complete_reg_rep__14; wire init_calib_complete_reg_rep__2; wire init_calib_complete_reg_rep__3; wire init_calib_complete_reg_rep__4; wire init_calib_complete_reg_rep__5; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__7; wire init_calib_complete_reg_rep__8; wire init_calib_complete_reg_rep__9; wire init_complete_r1; wire init_complete_r1_reg_0; (* RTL_KEEP = "true" *) wire init_complete_r1_timing; wire init_complete_r2; (* RTL_KEEP = "true" *) wire init_complete_r_timing; wire init_dqsfound_done_r2; wire init_next_state1100_out; wire [6:0]init_state_r1; wire \init_state_r[0]_i_10_n_0 ; wire \init_state_r[0]_i_11_n_0 ; wire \init_state_r[0]_i_13_n_0 ; wire \init_state_r[0]_i_14_n_0 ; wire \init_state_r[0]_i_15_n_0 ; wire \init_state_r[0]_i_16_n_0 ; wire \init_state_r[0]_i_17_n_0 ; wire \init_state_r[0]_i_18_n_0 ; wire \init_state_r[0]_i_19_n_0 ; wire \init_state_r[0]_i_1_n_0 ; wire \init_state_r[0]_i_20_n_0 ; wire \init_state_r[0]_i_21_n_0 ; wire \init_state_r[0]_i_22_n_0 ; wire \init_state_r[0]_i_23_n_0 ; wire \init_state_r[0]_i_24_n_0 ; wire \init_state_r[0]_i_25_n_0 ; wire \init_state_r[0]_i_26_n_0 ; wire \init_state_r[0]_i_27_n_0 ; wire \init_state_r[0]_i_28_n_0 ; wire \init_state_r[0]_i_29_n_0 ; wire \init_state_r[0]_i_2_n_0 ; wire \init_state_r[0]_i_30_n_0 ; wire \init_state_r[0]_i_31_n_0 ; wire \init_state_r[0]_i_33_n_0 ; wire \init_state_r[0]_i_34_n_0 ; wire \init_state_r[0]_i_3_n_0 ; wire \init_state_r[0]_i_40_n_0 ; wire \init_state_r[0]_i_41_n_0 ; wire \init_state_r[0]_i_42_n_0 ; wire \init_state_r[0]_i_43_n_0 ; wire \init_state_r[0]_i_45_n_0 ; wire \init_state_r[0]_i_46_n_0 ; wire \init_state_r[0]_i_51_n_0 ; wire \init_state_r[0]_i_5_n_0 ; wire \init_state_r[0]_i_6_n_0 ; wire \init_state_r[0]_i_7_n_0 ; wire \init_state_r[0]_i_8_n_0 ; wire \init_state_r[0]_i_9_n_0 ; wire \init_state_r[1]_i_10_n_0 ; wire \init_state_r[1]_i_11_n_0 ; wire \init_state_r[1]_i_12_n_0 ; wire \init_state_r[1]_i_13_n_0 ; wire \init_state_r[1]_i_15_n_0 ; wire \init_state_r[1]_i_16_n_0 ; wire \init_state_r[1]_i_17_n_0 ; wire \init_state_r[1]_i_18_n_0 ; wire \init_state_r[1]_i_19_n_0 ; wire \init_state_r[1]_i_1_n_0 ; wire \init_state_r[1]_i_20_n_0 ; wire \init_state_r[1]_i_21_n_0 ; wire \init_state_r[1]_i_22_n_0 ; wire \init_state_r[1]_i_23_n_0 ; wire \init_state_r[1]_i_24_n_0 ; wire \init_state_r[1]_i_25_n_0 ; wire \init_state_r[1]_i_26_n_0 ; wire \init_state_r[1]_i_27_n_0 ; wire \init_state_r[1]_i_28_n_0 ; wire \init_state_r[1]_i_2_n_0 ; wire \init_state_r[1]_i_33_n_0 ; wire \init_state_r[1]_i_34_n_0 ; wire \init_state_r[1]_i_35_n_0 ; wire \init_state_r[1]_i_36_n_0 ; wire \init_state_r[1]_i_37_n_0 ; wire \init_state_r[1]_i_39_n_0 ; wire \init_state_r[1]_i_3_n_0 ; wire \init_state_r[1]_i_40_n_0 ; wire \init_state_r[1]_i_41_n_0 ; wire \init_state_r[1]_i_42_n_0 ; wire \init_state_r[1]_i_43_n_0 ; wire \init_state_r[1]_i_46_n_0 ; wire \init_state_r[1]_i_47_n_0 ; wire \init_state_r[1]_i_48_n_0 ; wire \init_state_r[1]_i_5_n_0 ; wire \init_state_r[1]_i_6_n_0 ; wire \init_state_r[1]_i_7_n_0 ; wire \init_state_r[1]_i_8_n_0 ; wire \init_state_r[1]_i_9_n_0 ; wire \init_state_r[2]_i_10_n_0 ; wire \init_state_r[2]_i_11_n_0 ; wire \init_state_r[2]_i_12_n_0 ; wire \init_state_r[2]_i_14_n_0 ; wire \init_state_r[2]_i_16_n_0 ; wire \init_state_r[2]_i_17_n_0 ; wire \init_state_r[2]_i_18_n_0 ; wire \init_state_r[2]_i_1_n_0 ; wire \init_state_r[2]_i_20_n_0 ; wire \init_state_r[2]_i_21_n_0 ; wire \init_state_r[2]_i_22_n_0 ; wire \init_state_r[2]_i_24_n_0 ; wire \init_state_r[2]_i_25_n_0 ; wire \init_state_r[2]_i_26_n_0 ; wire \init_state_r[2]_i_27_n_0 ; wire \init_state_r[2]_i_2_n_0 ; wire \init_state_r[2]_i_32_n_0 ; wire \init_state_r[2]_i_33_n_0 ; wire \init_state_r[2]_i_34_n_0 ; wire \init_state_r[2]_i_35_n_0 ; wire \init_state_r[2]_i_36_n_0 ; wire \init_state_r[2]_i_37_n_0 ; wire \init_state_r[2]_i_3_n_0 ; wire \init_state_r[2]_i_4_n_0 ; wire \init_state_r[2]_i_5_n_0 ; wire \init_state_r[2]_i_6_n_0 ; wire \init_state_r[2]_i_7_n_0 ; wire \init_state_r[2]_i_8_n_0 ; wire \init_state_r[2]_i_9_n_0 ; wire \init_state_r[3]_i_10_n_0 ; wire \init_state_r[3]_i_11_n_0 ; wire \init_state_r[3]_i_13_n_0 ; wire \init_state_r[3]_i_14_n_0 ; wire \init_state_r[3]_i_15_n_0 ; wire \init_state_r[3]_i_16_n_0 ; wire \init_state_r[3]_i_17_n_0 ; wire \init_state_r[3]_i_18_n_0 ; wire \init_state_r[3]_i_19_n_0 ; wire \init_state_r[3]_i_1_n_0 ; wire \init_state_r[3]_i_20_n_0 ; wire \init_state_r[3]_i_21_n_0 ; wire \init_state_r[3]_i_22_n_0 ; wire \init_state_r[3]_i_23_n_0 ; wire \init_state_r[3]_i_24_n_0 ; wire \init_state_r[3]_i_25_n_0 ; wire \init_state_r[3]_i_2_n_0 ; wire \init_state_r[3]_i_3_n_0 ; wire \init_state_r[3]_i_4_n_0 ; wire \init_state_r[3]_i_5_n_0 ; wire \init_state_r[3]_i_6_n_0 ; wire \init_state_r[3]_i_7_n_0 ; wire \init_state_r[4]_i_10_n_0 ; wire \init_state_r[4]_i_11_n_0 ; wire \init_state_r[4]_i_12_n_0 ; wire \init_state_r[4]_i_13_n_0 ; wire \init_state_r[4]_i_15_n_0 ; wire \init_state_r[4]_i_16_n_0 ; wire \init_state_r[4]_i_17_n_0 ; wire \init_state_r[4]_i_18_n_0 ; wire \init_state_r[4]_i_19_n_0 ; wire \init_state_r[4]_i_1_n_0 ; wire \init_state_r[4]_i_20_n_0 ; wire \init_state_r[4]_i_21_n_0 ; wire \init_state_r[4]_i_22_n_0 ; wire \init_state_r[4]_i_26_n_0 ; wire \init_state_r[4]_i_27_n_0 ; wire \init_state_r[4]_i_28_n_0 ; wire \init_state_r[4]_i_29_n_0 ; wire \init_state_r[4]_i_2_n_0 ; wire \init_state_r[4]_i_30_n_0 ; wire \init_state_r[4]_i_31_n_0 ; wire \init_state_r[4]_i_32_n_0 ; wire \init_state_r[4]_i_33_n_0 ; wire \init_state_r[4]_i_37_n_0 ; wire \init_state_r[4]_i_38_n_0 ; wire \init_state_r[4]_i_39_n_0 ; wire \init_state_r[4]_i_3_n_0 ; wire \init_state_r[4]_i_40_n_0 ; wire \init_state_r[4]_i_4_n_0 ; wire \init_state_r[4]_i_5_n_0 ; wire \init_state_r[4]_i_6_n_0 ; wire \init_state_r[4]_i_7_n_0 ; wire \init_state_r[4]_i_8_n_0 ; wire \init_state_r[4]_i_9_n_0 ; wire \init_state_r[5]_i_10_n_0 ; wire \init_state_r[5]_i_11_n_0 ; wire \init_state_r[5]_i_12_n_0 ; wire \init_state_r[5]_i_13_n_0 ; wire \init_state_r[5]_i_14_n_0 ; wire \init_state_r[5]_i_15_n_0 ; wire \init_state_r[5]_i_16_n_0 ; wire \init_state_r[5]_i_17_n_0 ; wire \init_state_r[5]_i_18_n_0 ; wire \init_state_r[5]_i_19_n_0 ; wire \init_state_r[5]_i_1_n_0 ; wire \init_state_r[5]_i_20_n_0 ; wire \init_state_r[5]_i_21_n_0 ; wire \init_state_r[5]_i_22_n_0 ; wire \init_state_r[5]_i_23_n_0 ; wire \init_state_r[5]_i_24_n_0 ; wire \init_state_r[5]_i_25_n_0 ; wire \init_state_r[5]_i_26_n_0 ; wire \init_state_r[5]_i_27_n_0 ; wire \init_state_r[5]_i_29_n_0 ; wire \init_state_r[5]_i_2_n_0 ; wire \init_state_r[5]_i_31_n_0 ; wire \init_state_r[5]_i_32_n_0 ; wire \init_state_r[5]_i_33_n_0 ; wire \init_state_r[5]_i_34_n_0 ; wire \init_state_r[5]_i_35_n_0 ; wire \init_state_r[5]_i_36_n_0 ; wire \init_state_r[5]_i_38_n_0 ; wire \init_state_r[5]_i_39_n_0 ; wire \init_state_r[5]_i_3_n_0 ; wire \init_state_r[5]_i_40_n_0 ; wire \init_state_r[5]_i_41_n_0 ; wire \init_state_r[5]_i_42_n_0 ; wire \init_state_r[5]_i_43_n_0 ; wire \init_state_r[5]_i_44_n_0 ; wire \init_state_r[5]_i_45_n_0 ; wire \init_state_r[5]_i_48_n_0 ; wire \init_state_r[5]_i_49_n_0 ; wire \init_state_r[5]_i_4_n_0 ; wire \init_state_r[5]_i_50_n_0 ; wire \init_state_r[5]_i_51_n_0 ; wire \init_state_r[5]_i_52_n_0 ; wire \init_state_r[5]_i_53_n_0 ; wire \init_state_r[5]_i_54_n_0 ; wire \init_state_r[5]_i_56_n_0 ; wire \init_state_r[5]_i_57_n_0 ; wire \init_state_r[5]_i_58_n_0 ; wire \init_state_r[5]_i_5_n_0 ; wire \init_state_r[5]_i_60_n_0 ; wire \init_state_r[5]_i_61_n_0 ; wire \init_state_r[5]_i_62_n_0 ; wire \init_state_r[5]_i_6_n_0 ; wire \init_state_r[5]_i_7_n_0 ; wire \init_state_r[5]_i_8_n_0 ; wire \init_state_r[5]_i_9_n_0 ; wire \init_state_r[6]_i_10_n_0 ; wire \init_state_r[6]_i_11_n_0 ; wire \init_state_r[6]_i_12_n_0 ; wire \init_state_r[6]_i_13_n_0 ; wire \init_state_r[6]_i_14_n_0 ; wire \init_state_r[6]_i_15_n_0 ; wire \init_state_r[6]_i_16_n_0 ; wire \init_state_r[6]_i_17_n_0 ; wire \init_state_r[6]_i_18_n_0 ; wire \init_state_r[6]_i_19_n_0 ; wire \init_state_r[6]_i_1_n_0 ; wire \init_state_r[6]_i_20_n_0 ; wire \init_state_r[6]_i_21_n_0 ; wire \init_state_r[6]_i_22_n_0 ; wire \init_state_r[6]_i_2_n_0 ; wire \init_state_r[6]_i_3_n_0 ; wire \init_state_r[6]_i_4_n_0 ; wire \init_state_r[6]_i_5_n_0 ; wire \init_state_r[6]_i_7_n_0 ; wire \init_state_r[6]_i_8_n_0 ; wire \init_state_r[6]_i_9_n_0 ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[1]_0 ; wire \init_state_r_reg[1]_1 ; wire \init_state_r_reg[2]_0 ; wire \init_state_r_reg[2]_1 ; wire \init_state_r_reg[2]_2 ; wire \init_state_r_reg[4]_0 ; wire \init_state_r_reg[5]_0 ; wire \init_state_r_reg[6]_0 ; wire \init_state_r_reg[6]_1 ; wire \init_state_r_reg_n_0_[3] ; wire lim2init_prech_req; wire lim_start_r_reg; wire mask_lim_done; wire mask_lim_done_i_1_n_0; wire \mcGo_r_reg[15] ; wire [0:0]mc_cas_n; wire [0:0]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_odt; wire [0:0]mc_ras_n; wire [0:0]mc_we_n; wire mc_wrdata_en; wire mem_init_done_r; wire mem_init_done_r_i_1_n_0; wire [1:0]mem_init_done_r_reg_0; wire mem_init_done_r_reg_1; wire mem_init_done_r_reg_2; wire [1:0]mem_out; wire mpr_end_if_reset; wire mpr_end_if_reset0; wire mpr_last_byte_done; wire mpr_rdlvl_done_r_reg; wire mpr_rdlvl_done_r_reg_0; wire mpr_rdlvl_done_r_reg_1; wire mpr_rdlvl_done_r_reg_2; wire mpr_rdlvl_start_i_1_n_0; wire mpr_rdlvl_start_i_2_n_0; wire mpr_rdlvl_start_r; wire mpr_rdlvl_start_r_reg; wire mux_cmd_wren; wire mux_reset_n; wire mux_wrdata_en; wire \my_empty_reg[1] ; wire \my_empty_reg[1]_0 ; wire \my_empty_reg[1]_1 ; wire \my_empty_reg[1]_2 ; wire \my_empty_reg[1]_3 ; wire \my_empty_reg[1]_4 ; wire \my_empty_reg[1]_5 ; wire \my_empty_reg[1]_6 ; wire [3:0]\my_empty_reg[7] ; wire [3:0]\my_empty_reg[7]_0 ; wire [3:0]\my_empty_reg[7]_1 ; wire [7:0]\my_empty_reg[7]_10 ; wire [7:0]\my_empty_reg[7]_11 ; wire [7:0]\my_empty_reg[7]_12 ; wire [7:0]\my_empty_reg[7]_13 ; wire [7:0]\my_empty_reg[7]_14 ; wire [7:0]\my_empty_reg[7]_15 ; wire [7:0]\my_empty_reg[7]_16 ; wire [7:0]\my_empty_reg[7]_17 ; wire [7:0]\my_empty_reg[7]_18 ; wire [7:0]\my_empty_reg[7]_19 ; wire [3:0]\my_empty_reg[7]_2 ; wire [7:0]\my_empty_reg[7]_20 ; wire [7:0]\my_empty_reg[7]_21 ; wire [7:0]\my_empty_reg[7]_22 ; wire [7:0]\my_empty_reg[7]_23 ; wire [7:0]\my_empty_reg[7]_24 ; wire [7:0]\my_empty_reg[7]_25 ; wire [7:0]\my_empty_reg[7]_26 ; wire [7:0]\my_empty_reg[7]_27 ; wire [7:0]\my_empty_reg[7]_28 ; wire [7:0]\my_empty_reg[7]_29 ; wire [3:0]\my_empty_reg[7]_3 ; wire [7:0]\my_empty_reg[7]_30 ; wire [7:0]\my_empty_reg[7]_31 ; wire [7:0]\my_empty_reg[7]_32 ; wire [7:0]\my_empty_reg[7]_33 ; wire [7:0]\my_empty_reg[7]_34 ; wire [7:0]\my_empty_reg[7]_35 ; wire [7:0]\my_empty_reg[7]_36 ; wire [7:0]\my_empty_reg[7]_37 ; wire [63:0]\my_empty_reg[7]_38 ; wire [63:0]\my_empty_reg[7]_39 ; wire [3:0]\my_empty_reg[7]_4 ; wire [63:0]\my_empty_reg[7]_40 ; wire [63:0]\my_empty_reg[7]_41 ; wire [3:0]\my_empty_reg[7]_5 ; wire [7:0]\my_empty_reg[7]_6 ; wire [7:0]\my_empty_reg[7]_7 ; wire [7:0]\my_empty_reg[7]_8 ; wire [7:0]\my_empty_reg[7]_9 ; wire [1:0]\my_full_reg[3] ; wire new_cnt_dqs_r_reg; wire [2:0]num_reads; wire num_reads0; wire num_refresh0; wire \num_refresh[3]_i_1_n_0 ; wire \num_refresh[3]_i_4_n_0 ; wire \num_refresh[3]_i_5_n_0 ; wire \num_refresh[3]_i_6_n_0 ; wire [3:0]num_refresh_reg__0; wire num_samples_done_r; wire \ocal_act_wait_cnt[3]_i_1_n_0 ; wire \ocal_act_wait_cnt[3]_i_3_n_0 ; wire [3:0]ocal_act_wait_cnt_reg__0; wire ocal_last_byte_done; wire ocd_prech_req; wire oclk_calib_resume_level; wire oclk_calib_resume_level_i_1_n_0; wire oclk_calib_resume_level_reg_0; wire oclk_calib_resume_r_reg; wire oclk_calib_resume_r_reg_0; wire [3:2]oclk_wr_cnt0; wire \oclk_wr_cnt[0]_i_1_n_0 ; wire \oclk_wr_cnt[1]_i_1_n_0 ; wire \oclk_wr_cnt[3]_i_1_n_0 ; wire \oclk_wr_cnt[3]_i_4_n_0 ; wire [3:0]oclk_wr_cnt_reg__0; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_calib_done_r_reg_1; wire oclkdelay_calib_done_r_reg_2; wire oclkdelay_calib_done_r_reg_3; wire oclkdelay_calib_done_r_reg_4; wire oclkdelay_calib_done_r_reg_5; wire oclkdelay_calib_start_int_i_1_n_0; wire oclkdelay_calib_start_pre; wire oclkdelay_center_calib_done_r_reg; wire oclkdelay_center_calib_done_r_reg_0; wire oclkdelay_center_calib_start_r_reg; wire oclkdelay_center_calib_start_r_reg_0; wire oclkdelay_int_ref_req0; wire oclkdelay_int_ref_req_i_1_n_0; wire oclkdelay_int_ref_req_i_2_n_0; wire oclkdelay_int_ref_req_i_3_n_0; wire oclkdelay_int_ref_req_i_5_n_0; wire oclkdelay_int_ref_req_reg_0; wire \oclkdelay_ref_cnt[0]_i_1_n_0 ; wire \oclkdelay_ref_cnt[0]_i_4_n_0 ; wire \oclkdelay_ref_cnt[0]_i_5_n_0 ; wire \oclkdelay_ref_cnt[0]_i_6_n_0 ; wire \oclkdelay_ref_cnt[0]_i_7_n_0 ; wire \oclkdelay_ref_cnt[12]_i_2_n_0 ; wire \oclkdelay_ref_cnt[12]_i_3_n_0 ; wire \oclkdelay_ref_cnt[4]_i_2_n_0 ; wire \oclkdelay_ref_cnt[4]_i_3_n_0 ; wire \oclkdelay_ref_cnt[4]_i_4_n_0 ; wire \oclkdelay_ref_cnt[4]_i_5_n_0 ; wire \oclkdelay_ref_cnt[8]_i_2_n_0 ; wire \oclkdelay_ref_cnt[8]_i_3_n_0 ; wire \oclkdelay_ref_cnt[8]_i_4_n_0 ; wire \oclkdelay_ref_cnt[8]_i_5_n_0 ; wire [13:0]oclkdelay_ref_cnt_reg; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_0 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_1 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_2 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_3 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_4 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_5 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_6 ; wire \oclkdelay_ref_cnt_reg[0]_i_2_n_7 ; wire \oclkdelay_ref_cnt_reg[12]_i_1_n_3 ; wire \oclkdelay_ref_cnt_reg[12]_i_1_n_6 ; wire \oclkdelay_ref_cnt_reg[12]_i_1_n_7 ; wire \oclkdelay_ref_cnt_reg[13]_0 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_0 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_1 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_2 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_3 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_4 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_5 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_6 ; wire \oclkdelay_ref_cnt_reg[4]_i_1_n_7 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_0 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_1 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_2 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_3 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_4 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_5 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_6 ; wire \oclkdelay_ref_cnt_reg[8]_i_1_n_7 ; wire [5:5]oclkdelay_start_dly_r; wire \oclkdelay_start_dly_r_reg[4]_srl5_n_0 ; wire \odd_cwl.phy_cas_n[1]_i_1_n_0 ; wire \odd_cwl.phy_cas_n_reg[1]_0 ; wire \odd_cwl.phy_ras_n[1]_i_1_n_0 ; wire \odd_cwl.phy_ras_n[1]_i_2_n_0 ; wire \odd_cwl.phy_we_n[1]_i_1_n_0 ; wire \one_rank.stg1_wr_done_i_1_n_0 ; wire \one_rank.stg1_wr_done_reg_0 ; wire \one_rank_complex.complex_wr_done_i_1_n_0 ; wire \one_rank_complex.complex_wr_done_i_2_n_0 ; wire \one_rank_complex.complex_wr_done_i_3_n_0 ; wire \one_rank_complex.complex_wr_done_i_4_n_0 ; wire \one_rank_complex.complex_wr_done_i_5_n_0 ; wire p_0_in0_in; wire [9:0]p_0_in__0; wire [8:0]p_0_in__0__0; wire [7:0]p_0_in__1; wire [3:1]p_0_in__2; wire [7:0]p_0_in__3; wire [3:0]p_0_in__4; wire [7:0]p_0_in__5; wire [3:0]p_0_in__6; wire [4:0]p_0_in__7; wire [3:0]p_0_in__8; wire [3:0]p_0_in__9; wire p_81_in; wire [11:9]phy_bank; wire [1:1]phy_cas_n; wire [1:1]phy_cs_n; wire [10:0]\phy_ctl_wd_i1_reg[24] ; wire [31:0]phy_dout; wire phy_if_empty_r_reg; wire [1:1]phy_ras_n; wire phy_rddata_en_1; wire phy_read_calib; wire phy_reset_n; wire [1:1]phy_we_n; wire [255:24]phy_wrdata; wire phy_wrdata_en; wire phy_write_calib; wire pi_calib_done; wire pi_calib_done_r; wire pi_calib_done_r_i_1_n_0; wire pi_calib_rank_done_r; wire \pi_dqs_found_all_bank_reg[1] ; wire [0:0]\pi_dqs_found_all_bank_reg[1]_0 ; wire pi_dqs_found_done_r1; wire pi_dqs_found_done_r1_reg_0; wire pi_dqs_found_done_r1_reg_1; wire pi_dqs_found_done_r1_reg_2; wire pi_dqs_found_done_r1_reg_3; wire pi_dqs_found_done_r1_reg_4; wire pi_dqs_found_done_r1_reg_5; wire pi_dqs_found_done_r1_reg_6; wire pi_dqs_found_done_r1_reg_7; wire pi_dqs_found_rank_done; wire pi_dqs_found_start_i_1_n_0; (* async_reg = "true" *) wire pi_phase_locked_all_r1; (* async_reg = "true" *) wire pi_phase_locked_all_r2; (* async_reg = "true" *) wire pi_phase_locked_all_r3; (* async_reg = "true" *) wire pi_phase_locked_all_r4; wire prbs_gen_clk_en; wire prbs_gen_clk_en040_out; wire prbs_gen_clk_en_i_1_n_0; wire prbs_gen_clk_en_i_2_n_0; wire prbs_gen_clk_en_i_3_n_0; wire prbs_gen_clk_en_i_5_n_0; wire prbs_gen_oclk_clk_en; wire prbs_gen_oclk_clk_en_i_1_n_0; wire prbs_gen_oclk_clk_en_i_2_n_0; wire prbs_gen_oclk_clk_en_i_3_n_0; wire prbs_gen_oclk_clk_en_i_4_n_0; wire prbs_gen_oclk_clk_en_i_5_n_0; wire prbs_gen_oclk_clk_en_i_6_n_0; wire prbs_gen_oclk_clk_en_i_7_n_0; wire prbs_gen_oclk_clk_en_i_8_n_0; wire prbs_gen_oclk_clk_en_i_9_n_0; wire prbs_last_byte_done; wire prbs_last_byte_done_r; wire prbs_last_byte_done_reg; wire prbs_rdlvl_done_pulse; wire prbs_rdlvl_done_pulse0; wire prbs_rdlvl_done_r1; wire prbs_rdlvl_done_r2; wire prbs_rdlvl_done_r3; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_0; wire prbs_rdlvl_done_reg_rep; wire prbs_rdlvl_done_reg_rep_0; wire prbs_rdlvl_done_reg_rep_1; wire prbs_rdlvl_done_reg_rep_2; wire prbs_rdlvl_done_reg_rep_3; wire prbs_rdlvl_prech_req_reg; wire prbs_rdlvl_start_i_1_n_0; wire prbs_rdlvl_start_i_2_n_0; wire prbs_rdlvl_start_i_3_n_0; wire prbs_rdlvl_start_r; wire prbs_rdlvl_start_r_reg; wire prech_done; wire \prech_done_dly_r_reg[15]_srl16_n_0 ; wire prech_done_pre; wire prech_done_r2; wire prech_done_r3; wire prech_pending_r; wire prech_pending_r_i_3_n_0; wire prech_pending_r_i_4_n_0; wire prech_pending_r_i_5_n_0; wire prech_pending_r_i_6_n_0; wire prech_pending_r_i_7_n_0; wire prech_pending_r_i_8_n_0; wire prech_pending_r_i_9_n_0; wire prech_pending_r_reg_0; wire prech_pending_r_reg_1; wire prech_req; wire prech_req_posedge_r0; wire prech_req_posedge_r_i_2_n_0; wire prech_req_posedge_r_reg_0; wire prech_req_r; wire pwron_ce_r; wire pwron_ce_r_i_2_n_0; wire pwron_ce_r_i_3_n_0; wire [1:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ; wire [1:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ; wire [0:0]\rd_addr_reg[0] ; wire [0:0]\rd_addr_reg[3] ; wire \rd_addr_reg_rep[7] ; wire [1:0]\rd_byte_data_offset_reg[0][3] ; wire [1:0]\rd_byte_data_offset_reg[0][9] ; wire [33:0]\rd_ptr_reg[3] ; wire [7:0]\rd_ptr_reg[3]_0 ; wire [31:0]\rd_ptr_reg[3]_1 ; wire [63:0]\rd_ptr_reg[3]_2 ; wire [63:0]\rd_ptr_reg[3]_3 ; wire [63:0]\rd_ptr_reg[3]_4 ; wire [63:0]\rd_ptr_reg[3]_5 ; wire [33:0]\rd_ptr_timing_reg[0] ; wire [7:0]\rd_ptr_timing_reg[0]_0 ; wire [7:0]\rd_ptr_timing_reg[0]_1 ; wire [3:0]\rd_ptr_timing_reg[0]_2 ; wire [1:0]\rd_ptr_timing_reg[0]_3 ; wire \rd_victim_sel_reg[0] ; wire \rd_victim_sel_reg[1] ; wire \rd_victim_sel_reg[2] ; wire rdlvl_last_byte_done; wire rdlvl_last_byte_done_r; wire rdlvl_pi_incdec; wire rdlvl_prech_req; wire [0:0]rdlvl_start_dly0_r; wire \rdlvl_start_dly0_r_reg[13]_srl14_n_0 ; wire \rdlvl_start_dly0_r_reg[14]_0 ; wire rdlvl_start_pre; wire rdlvl_start_pre_reg_0; wire rdlvl_stg1_done_int_reg; wire rdlvl_stg1_done_int_reg_0; wire rdlvl_stg1_done_int_reg_1; wire rdlvl_stg1_done_int_reg_2; wire rdlvl_stg1_done_int_reg_3; wire rdlvl_stg1_done_int_reg_4; wire rdlvl_stg1_done_r1; wire rdlvl_stg1_rank_done; wire rdlvl_stg1_start_int; wire rdlvl_stg1_start_int_i_1_n_0; wire rdlvl_stg1_start_int_i_2_n_0; wire rdlvl_stg1_start_r_reg; wire read_calib_i_1_n_0; wire read_calib_i_2_n_0; wire read_calib_reg_0; wire reg_ctrl_cnt_r; wire \reg_ctrl_cnt_r[0]_i_1_n_0 ; wire \reg_ctrl_cnt_r_reg[3]_0 ; wire [3:0]reg_ctrl_cnt_r_reg__0; wire reset_if; wire reset_if_i_2_n_0; wire reset_if_r9; wire reset_if_reg; wire reset_rd_addr; wire reset_rd_addr0; wire reset_rd_addr_r1; wire \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire rstdiv0_sync_r1_reg_rep__12; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__24_0; wire rstdiv0_sync_r1_reg_rep__24_1; wire rstdiv0_sync_r1_reg_rep__25; wire [0:0]\samples_cnt_r_reg[11] ; wire \samples_cnt_r_reg[11]_0 ; wire stg1_wr_done; wire \stg1_wr_rd_cnt[0]_i_1_n_0 ; wire \stg1_wr_rd_cnt[1]_i_1_n_0 ; wire \stg1_wr_rd_cnt[2]_i_1_n_0 ; wire \stg1_wr_rd_cnt[3]_i_1_n_0 ; wire \stg1_wr_rd_cnt[3]_i_2_n_0 ; wire \stg1_wr_rd_cnt[4]_i_1_n_0 ; wire \stg1_wr_rd_cnt[4]_i_3_n_0 ; wire \stg1_wr_rd_cnt[4]_i_4_n_0 ; wire \stg1_wr_rd_cnt[4]_i_5_n_0 ; wire \stg1_wr_rd_cnt[4]_i_6_n_0 ; wire \stg1_wr_rd_cnt[5]_i_1_n_0 ; wire \stg1_wr_rd_cnt[5]_i_2_n_0 ; wire \stg1_wr_rd_cnt[6]_i_1_n_0 ; wire \stg1_wr_rd_cnt[6]_i_2_n_0 ; wire \stg1_wr_rd_cnt[7]_i_1_n_0 ; wire \stg1_wr_rd_cnt[8]_i_1_n_0 ; wire \stg1_wr_rd_cnt[8]_i_2_n_0 ; wire \stg1_wr_rd_cnt[8]_i_3_n_0 ; wire \stg1_wr_rd_cnt[8]_i_4_n_0 ; wire \stg1_wr_rd_cnt[8]_i_5_n_0 ; wire \stg1_wr_rd_cnt[8]_i_6_n_0 ; wire \stg1_wr_rd_cnt_reg_n_0_[0] ; wire \stg1_wr_rd_cnt_reg_n_0_[1] ; wire \stg1_wr_rd_cnt_reg_n_0_[2] ; wire \stg1_wr_rd_cnt_reg_n_0_[3] ; wire \stg1_wr_rd_cnt_reg_n_0_[4] ; wire \stg1_wr_rd_cnt_reg_n_0_[5] ; wire \stg1_wr_rd_cnt_reg_n_0_[6] ; wire \stg1_wr_rd_cnt_reg_n_0_[7] ; wire \stg1_wr_rd_cnt_reg_n_0_[8] ; wire temp_lmr_done; wire \victim_sel[0]_i_1_n_0 ; wire \victim_sel[0]_i_2_n_0 ; wire \victim_sel[1]_i_1_n_0 ; wire \victim_sel[1]_i_2_n_0 ; wire \victim_sel[2]_i_1_n_0 ; wire \victim_sel[2]_i_2_n_0 ; wire \victim_sel[2]_i_3_n_0 ; wire \victim_sel[2]_i_4_n_0 ; wire \victim_sel[2]_i_5_n_0 ; wire \victim_sel_reg_n_0_[0] ; wire \victim_sel_reg_n_0_[1] ; wire \victim_sel_reg_n_0_[2] ; wire [7:0]\victim_sel_rotate.sel_reg[31] ; wire wl_sm_start; wire \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ; wire \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ; wire wr_level_done_reg; wire wr_level_dqs_asrt; wire wr_level_dqs_asrt_i_1_n_0; wire wr_level_dqs_asrt_r1; wire wr_level_start_r_reg; wire wr_lvl_start_i_1_n_0; wire wr_victim_inc; wire wr_victim_inc0; wire wr_victim_inc_i_2_n_0; wire wr_victim_inc_i_3_n_0; wire [2:0]wr_victim_sel; wire \wr_victim_sel[0]_i_1_n_0 ; wire \wr_victim_sel[1]_i_1_n_0 ; wire \wr_victim_sel[2]_i_1_n_0 ; wire [2:0]wr_victim_sel_ocal; wire \wr_victim_sel_ocal[0]_i_1_n_0 ; wire \wr_victim_sel_ocal[1]_i_1_n_0 ; wire \wr_victim_sel_ocal[2]_i_1_n_0 ; wire wrcal_done_reg; wire wrcal_done_reg_0; wire wrcal_done_reg_1; wire wrcal_done_reg_10; wire wrcal_done_reg_11; wire wrcal_done_reg_2; wire wrcal_done_reg_3; wire wrcal_done_reg_4; wire wrcal_done_reg_5; wire wrcal_done_reg_6; wire wrcal_done_reg_7; wire wrcal_done_reg_8; wire wrcal_done_reg_9; wire \wrcal_dqs_cnt_r_reg[0] ; wire wrcal_final_chk; wire wrcal_final_chk_i_1_n_0; wire wrcal_final_chk_i_2_n_0; wire wrcal_prech_req; wire wrcal_rd_wait; wire wrcal_rd_wait_i_1_n_0; wire wrcal_reads; wire wrcal_reads05_out; wire \wrcal_reads[0]_i_1_n_0 ; wire \wrcal_reads[1]_i_1_n_0 ; wire \wrcal_reads[2]_i_1_n_0 ; wire \wrcal_reads[3]_i_1_n_0 ; wire \wrcal_reads[4]_i_1_n_0 ; wire \wrcal_reads[5]_i_1_n_0 ; wire \wrcal_reads[5]_i_2_n_0 ; wire \wrcal_reads[6]_i_1_n_0 ; wire \wrcal_reads[7]_i_2_n_0 ; wire \wrcal_reads[7]_i_3_n_0 ; wire \wrcal_reads[7]_i_5_n_0 ; wire \wrcal_reads[7]_i_6_n_0 ; wire \wrcal_reads[7]_i_7_n_0 ; wire \wrcal_reads_reg_n_0_[0] ; wire \wrcal_reads_reg_n_0_[1] ; wire \wrcal_reads_reg_n_0_[2] ; wire \wrcal_reads_reg_n_0_[3] ; wire \wrcal_reads_reg_n_0_[4] ; wire \wrcal_reads_reg_n_0_[5] ; wire \wrcal_reads_reg_n_0_[6] ; wire \wrcal_reads_reg_n_0_[7] ; wire wrcal_resume_r; wire wrcal_resume_w; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done_reg; wire wrcal_sanity_chk_done_reg_0; wire wrcal_sanity_chk_r_reg; wire [5:5]wrcal_start_dly_r; wire \wrcal_start_dly_r_reg[4]_srl5_n_0 ; wire wrcal_start_i_1_n_0; wire wrcal_start_pre; wire wrcal_start_reg_0; wire [3:2]wrcal_wr_cnt0; wire \wrcal_wr_cnt[0]_i_1_n_0 ; wire \wrcal_wr_cnt[1]_i_1_n_0 ; wire \wrcal_wr_cnt[3]_i_1_n_0 ; wire \wrcal_wr_cnt[3]_i_2_n_0 ; wire \wrcal_wr_cnt[3]_i_4_n_0 ; wire [3:0]wrcal_wr_cnt_reg__0; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ; wire [255:0]\write_buffer.wr_buf_out_data_reg[255] ; wire write_calib_i_1_n_0; wire write_calib_i_2_n_0; wire write_request_r_reg; wire wrlvl_active; wire wrlvl_active_i_1_n_0; wire wrlvl_active_r1; wire wrlvl_byte_redo; wire wrlvl_byte_redo_reg; wire wrlvl_byte_redo_reg_0; wire wrlvl_done_r; wire wrlvl_done_r1; wire wrlvl_final_if_rst; wire wrlvl_final_if_rst_i_1_n_0; wire wrlvl_final_if_rst_i_2_n_0; wire wrlvl_final_mux; wire wrlvl_final_mux_reg; wire wrlvl_final_mux_reg_0; wire wrlvl_odt; wire wrlvl_odt_ctl; wire wrlvl_odt_ctl_i_1_n_0; wire wrlvl_odt_ctl_i_2_n_0; wire wrlvl_odt_ctl_i_3_n_0; wire wrlvl_rank_done; wire wrlvl_rank_done_r1; wire wrlvl_rank_done_r6_reg_srl5_n_0; wire wrlvl_rank_done_r7; wire [3:1]\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED ; assign in0 = init_complete_r_timing; assign out = init_complete_r1_timing; LUT6 #( .INIT(64'h000000000000E0EE)) \DDR3_1rank.phy_int_cs_n[1]_i_1 (.I0(\odd_cwl.phy_cas_n_reg[1]_0 ), .I1(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ), .I2(rdlvl_stg1_start_int_i_2_n_0), .I3(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ), .I4(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ), .I5(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ), .O(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \DDR3_1rank.phy_int_cs_n[1]_i_2 (.I0(\calib_cmd[2]_i_2_n_0 ), .I1(\calib_cmd[2]_i_3_n_0 ), .O(\odd_cwl.phy_cas_n_reg[1]_0 )); LUT6 #( .INIT(64'h0000000000000010)) \DDR3_1rank.phy_int_cs_n[1]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[5]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[3]), .I5(Q[4]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair597" *) LUT3 #( .INIT(8'h04)) \DDR3_1rank.phy_int_cs_n[1]_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[0]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAABBA)) \DDR3_1rank.phy_int_cs_n[1]_i_5 (.I0(write_calib_i_2_n_0), .I1(read_calib_i_2_n_0), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(prbs_rdlvl_start_i_2_n_0), .I5(temp_lmr_done), .O(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \DDR3_1rank.phy_int_cs_n[1]_i_6 (.I0(\num_refresh[3]_i_4_n_0 ), .I1(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ), .I2(\victim_sel[2]_i_5_n_0 ), .I3(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ), .I4(complex_row1_rd_done_i_2_n_0), .I5(\cnt_init_mr_r_reg[1]_0 ), .O(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000040000)) \DDR3_1rank.phy_int_cs_n[1]_i_7 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[5]), .I4(Q[3]), .I5(Q[4]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \DDR3_1rank.phy_int_cs_n[1]_i_8 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[4]), .I3(prbs_rdlvl_start_i_2_n_0), .I4(Q[5]), .I5(Q[3]), .O(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 )); FDSE \DDR3_1rank.phy_int_cs_n_reg[1] (.C(CLK), .CE(1'b1), .D(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ), .Q(phy_cs_n), .S(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'h2)) \FSM_sequential_cal1_state_r[5]_i_10 (.I0(mpr_rdlvl_start_r_reg), .I1(mpr_rdlvl_start_r), .O(cal1_state_r1535_out)); LUT6 #( .INIT(64'h0000000066666706)) \back_to_back_reads_4_1.num_reads[0]_i_1 (.I0(num_reads[0]), .I1(num_reads0), .I2(Q[1]), .I3(Q[0]), .I4(\back_to_back_reads_4_1.num_reads_reg[0]_0 ), .I5(rstdiv0_sync_r1_reg_rep__25), .O(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair504" *) LUT3 #( .INIT(8'hFE)) \back_to_back_reads_4_1.num_reads[0]_i_2 (.I0(num_reads[0]), .I1(num_reads[2]), .I2(num_reads[1]), .O(num_reads0)); (* SOFT_HLUTNM = "soft_lutpair521" *) LUT5 #( .INIT(32'hFFFFFEFF)) \back_to_back_reads_4_1.num_reads[0]_i_3 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[5]), .I3(Q[3]), .I4(Q[4]), .O(\back_to_back_reads_4_1.num_reads_reg[0]_0 )); LUT6 #( .INIT(64'h00000000CC320000)) \back_to_back_reads_4_1.num_reads[1]_i_1 (.I0(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ), .I1(num_reads[1]), .I2(num_reads[2]), .I3(num_reads[0]), .I4(\back_to_back_reads_4_1.num_reads_reg[1]_0 ), .I5(rstdiv0_sync_r1_reg_rep__25), .O(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \back_to_back_reads_4_1.num_reads[1]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(Q[4]), .I2(Q[3]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 )); LUT5 #( .INIT(32'h00C80000)) \back_to_back_reads_4_1.num_reads[2]_i_1 (.I0(num_reads[1]), .I1(num_reads[2]), .I2(num_reads[0]), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(\back_to_back_reads_4_1.num_reads_reg[1]_0 ), .O(\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 )); FDRE \back_to_back_reads_4_1.num_reads_reg[0] (.C(CLK), .CE(1'b1), .D(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ), .Q(num_reads[0]), .R(1'b0)); FDRE \back_to_back_reads_4_1.num_reads_reg[1] (.C(CLK), .CE(1'b1), .D(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ), .Q(num_reads[1]), .R(1'b0)); FDRE \back_to_back_reads_4_1.num_reads_reg[2] (.C(CLK), .CE(1'b1), .D(\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ), .Q(num_reads[2]), .R(1'b0)); LUT6 #( .INIT(64'h0000010000009595)) burst_addr_r_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(\init_state_r[5]_i_26_n_0 ), .I5(Q[3]), .O(burst_addr_r_reg_1)); FDRE burst_addr_r_reg (.C(CLK), .CE(1'b1), .D(burst_addr_r_reg_2), .Q(burst_addr_r_reg_0), .R(1'b0)); FDRE \calib_cke_reg[0] (.C(CLK), .CE(1'b1), .D(cnt_pwron_cke_done_r), .Q(calib_cke), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair575" *) LUT3 #( .INIT(8'hFB)) \calib_cmd[0]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_cmd[2]_i_3_n_0 ), .O(\calib_cmd[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair575" *) LUT3 #( .INIT(8'h40)) \calib_cmd[1]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_cmd[2]_i_3_n_0 ), .O(\calib_cmd[1]_i_1_n_0 )); LUT3 #( .INIT(8'h04)) \calib_cmd[2]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_cmd[2]_i_3_n_0 ), .O(\calib_cmd[2]_i_1_n_0 )); LUT3 #( .INIT(8'h01)) \calib_cmd[2]_i_2 (.I0(\wrcal_wr_cnt[3]_i_2_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I2(\calib_cmd[2]_i_4_n_0 ), .O(\calib_cmd[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFEFEFEFEFFFFFEFF)) \calib_cmd[2]_i_3 (.I0(\calib_cmd[2]_i_5_n_0 ), .I1(\calib_cmd[2]_i_6_n_0 ), .I2(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ), .I3(\calib_cmd[2]_i_7_n_0 ), .I4(\calib_cmd[2]_i_8_n_0 ), .I5(rdlvl_pi_incdec), .O(\calib_cmd[2]_i_3_n_0 )); LUT6 #( .INIT(64'h08080000000000FF)) \calib_cmd[2]_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(read_calib_i_2_n_0), .I3(prbs_rdlvl_start_i_3_n_0), .I4(Q[0]), .I5(Q[1]), .O(\calib_cmd[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000040048)) \calib_cmd[2]_i_5 (.I0(Q[1]), .I1(Q[0]), .I2(Q[3]), .I3(\init_state_r[5]_i_26_n_0 ), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\calib_cmd[2]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000040200)) \calib_cmd[2]_i_6 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[0]), .I3(Q[2]), .I4(Q[3]), .I5(\init_state_r[5]_i_26_n_0 ), .O(\calib_cmd[2]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair507" *) LUT5 #( .INIT(32'hFFFFFDFF)) \calib_cmd[2]_i_7 (.I0(Q[0]), .I1(read_calib_i_2_n_0), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[1]), .O(\calib_cmd[2]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000000100)) \calib_cmd[2]_i_8 (.I0(Q[1]), .I1(Q[0]), .I2(Q[4]), .I3(Q[3]), .I4(Q[5]), .I5(oclk_calib_resume_level_reg_0), .O(\calib_cmd[2]_i_8_n_0 )); FDRE \calib_cmd_reg[0] (.C(CLK), .CE(1'b1), .D(\calib_cmd[0]_i_1_n_0 ), .Q(calib_cmd[0]), .R(1'b0)); FDRE \calib_cmd_reg[1] (.C(CLK), .CE(1'b1), .D(\calib_cmd[1]_i_1_n_0 ), .Q(calib_cmd[1]), .R(1'b0)); FDRE \calib_cmd_reg[2] (.C(CLK), .CE(1'b1), .D(\calib_cmd[2]_i_1_n_0 ), .Q(calib_cmd[2]), .R(1'b0)); LUT2 #( .INIT(4'h8)) calib_ctl_wren_i_1 (.I0(cnt_pwron_cke_done_r), .I1(\mcGo_r_reg[15] ), .O(calib_ctl_wren0)); FDRE calib_ctl_wren_reg (.C(CLK), .CE(1'b1), .D(calib_ctl_wren0), .Q(calib_ctl_wren), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_0[2]_i_1 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][3] [0]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [0]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_0[2]_i_1_n_0 )); LUT2 #( .INIT(4'hB)) \calib_data_offset_0[3]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .O(\calib_data_offset_0[3]_i_1_n_0 )); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_0[3]_i_2 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][3] [1]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [1]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_0[3]_i_2_n_0 )); LUT4 #( .INIT(16'hBFFF)) \calib_data_offset_0[5]_i_1 (.I0(wr_level_dqs_asrt), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(pi_calib_done), .I3(\calib_cmd[2]_i_3_n_0 ), .O(\calib_data_offset_0[5]_i_1_n_0 )); FDRE \calib_data_offset_0_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_3), .Q(calib_data_offset_0[0]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE \calib_data_offset_0_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_2), .Q(calib_data_offset_0[1]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDSE \calib_data_offset_0_reg[2] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_0[2]_i_1_n_0 ), .Q(calib_data_offset_0[2]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDSE \calib_data_offset_0_reg[3] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_0[3]_i_2_n_0 ), .Q(calib_data_offset_0[3]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDRE \calib_data_offset_0_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_1), .Q(calib_data_offset_0[4]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE \calib_data_offset_0_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_0), .Q(calib_data_offset_0[5]), .R(\calib_data_offset_0[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_1[2]_i_1 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][9] [0]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [0]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_1[2]_i_1_n_0 )); LUT6 #( .INIT(64'h8888000088800080)) \calib_data_offset_1[3]_i_1 (.I0(pi_calib_done), .I1(\calib_cmd[2]_i_3_n_0 ), .I2(\rd_byte_data_offset_reg[0][9] [1]), .I3(init_dqsfound_done_r2), .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [1]), .I5(pi_dqs_found_done_r1), .O(\calib_data_offset_1[3]_i_1_n_0 )); FDRE \calib_data_offset_1_reg[0] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_7), .Q(calib_data_offset_1[0]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE \calib_data_offset_1_reg[1] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_6), .Q(calib_data_offset_1[1]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDSE \calib_data_offset_1_reg[2] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_1[2]_i_1_n_0 ), .Q(calib_data_offset_1[2]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDSE \calib_data_offset_1_reg[3] (.C(CLK), .CE(1'b1), .D(\calib_data_offset_1[3]_i_1_n_0 ), .Q(calib_data_offset_1[3]), .S(\calib_data_offset_0[3]_i_1_n_0 )); FDRE \calib_data_offset_1_reg[4] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_5), .Q(calib_data_offset_1[4]), .R(\calib_data_offset_0[5]_i_1_n_0 )); FDRE \calib_data_offset_1_reg[5] (.C(CLK), .CE(1'b1), .D(pi_dqs_found_done_r1_reg_4), .Q(calib_data_offset_1[5]), .R(\calib_data_offset_0[5]_i_1_n_0 )); LUT5 #( .INIT(32'h0000AAA2)) \calib_odt[0]_i_1 (.I0(\gen_rnk[0].mr1_r_reg[0]_196 ), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\calib_odt[0]_i_2_n_0 ), .I3(\calib_odt[0]_i_3_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__24), .O(\calib_odt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hCFDCCFDFCCDCCCDF)) \calib_odt[0]_i_2 (.I0(first_wrcal_pat_r_i_2_n_0), .I1(stg1_wr_done), .I2(Q[1]), .I3(Q[0]), .I4(complex_ocal_odt_ext_i_4_n_0), .I5(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .O(\calib_odt[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF2000)) \calib_odt[0]_i_3 (.I0(wrlvl_odt), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(\calib_odt[0]_i_4_n_0 ), .I4(complex_odt_ext), .I5(complex_ocal_odt_ext), .O(\calib_odt[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair525" *) LUT5 #( .INIT(32'h00100000)) \calib_odt[0]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[0]), .I3(Q[3]), .I4(Q[1]), .O(\calib_odt[0]_i_4_n_0 )); FDRE \calib_odt_reg[0] (.C(CLK), .CE(1'b1), .D(\calib_odt[0]_i_1_n_0 ), .Q(calib_odt), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair559" *) LUT3 #( .INIT(8'h78)) \calib_seq[0]_i_1 (.I0(cnt_pwron_cke_done_r), .I1(\mcGo_r_reg[15] ), .I2(\phy_ctl_wd_i1_reg[24] [9]), .O(\calib_seq[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair559" *) LUT4 #( .INIT(16'h7F80)) \calib_seq[1]_i_1 (.I0(\phy_ctl_wd_i1_reg[24] [9]), .I1(cnt_pwron_cke_done_r), .I2(\mcGo_r_reg[15] ), .I3(\phy_ctl_wd_i1_reg[24] [10]), .O(\calib_seq[1]_i_1_n_0 )); FDRE \calib_seq_reg[0] (.C(CLK), .CE(1'b1), .D(\calib_seq[0]_i_1_n_0 ), .Q(\phy_ctl_wd_i1_reg[24] [9]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \calib_seq_reg[1] (.C(CLK), .CE(1'b1), .D(\calib_seq[1]_i_1_n_0 ), .Q(\phy_ctl_wd_i1_reg[24] [10]), .R(rstdiv0_sync_r1_reg_rep__12)); LUT1 #( .INIT(2'h1)) calib_wrdata_en_i_1 (.I0(\calib_cmd[2]_i_2_n_0 ), .O(phy_wrdata_en)); FDRE calib_wrdata_en_reg (.C(CLK), .CE(1'b1), .D(phy_wrdata_en), .Q(calib_wrdata_en), .R(1'b0)); LUT6 #( .INIT(64'h0000000000008000)) cnt_cmd_done_m7_r_i_1 (.I0(\cnt_cmd_r_reg_n_0_[6] ), .I1(\cnt_cmd_r_reg_n_0_[5] ), .I2(\cnt_cmd_r_reg_n_0_[4] ), .I3(\cnt_cmd_r_reg_n_0_[3] ), .I4(cnt_cmd_done_m7_r_i_2_n_0), .I5(\cnt_cmd_r_reg_n_0_[2] ), .O(cnt_cmd_done_m7_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair604" *) LUT2 #( .INIT(4'hE)) cnt_cmd_done_m7_r_i_2 (.I0(\cnt_cmd_r_reg_n_0_[0] ), .I1(\cnt_cmd_r_reg_n_0_[1] ), .O(cnt_cmd_done_m7_r_i_2_n_0)); FDRE cnt_cmd_done_m7_r_reg (.C(CLK), .CE(1'b1), .D(cnt_cmd_done_m7_r_i_1_n_0), .Q(cnt_cmd_done_m7_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair580" *) LUT3 #( .INIT(8'h80)) cnt_cmd_done_r_i_1 (.I0(\cnt_cmd_r[6]_i_5_n_0 ), .I1(\cnt_cmd_r_reg_n_0_[5] ), .I2(\cnt_cmd_r_reg_n_0_[6] ), .O(cnt_cmd_done_r_i_1_n_0)); FDRE cnt_cmd_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_cmd_done_r_i_1_n_0), .Q(cnt_cmd_done_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cnt_cmd_r[0]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[0] ), .O(\cnt_cmd_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair604" *) LUT2 #( .INIT(4'h6)) \cnt_cmd_r[1]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[1] ), .I1(\cnt_cmd_r_reg_n_0_[0] ), .O(\cnt_cmd_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair555" *) LUT3 #( .INIT(8'h6A)) \cnt_cmd_r[2]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[2] ), .I1(\cnt_cmd_r_reg_n_0_[1] ), .I2(\cnt_cmd_r_reg_n_0_[0] ), .O(\cnt_cmd_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair555" *) LUT4 #( .INIT(16'h6AAA)) \cnt_cmd_r[3]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[3] ), .I1(\cnt_cmd_r_reg_n_0_[2] ), .I2(\cnt_cmd_r_reg_n_0_[0] ), .I3(\cnt_cmd_r_reg_n_0_[1] ), .O(\cnt_cmd_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair487" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_cmd_r[4]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[4] ), .I1(\cnt_cmd_r_reg_n_0_[3] ), .I2(\cnt_cmd_r_reg_n_0_[1] ), .I3(\cnt_cmd_r_reg_n_0_[0] ), .I4(\cnt_cmd_r_reg_n_0_[2] ), .O(\cnt_cmd_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_cmd_r[5]_i_1 (.I0(\cnt_cmd_r_reg_n_0_[5] ), .I1(\cnt_cmd_r_reg_n_0_[4] ), .I2(\cnt_cmd_r_reg_n_0_[3] ), .I3(\cnt_cmd_r_reg_n_0_[1] ), .I4(\cnt_cmd_r_reg_n_0_[0] ), .I5(\cnt_cmd_r_reg_n_0_[2] ), .O(\cnt_cmd_r[5]_i_1_n_0 )); LUT3 #( .INIT(8'hFE)) \cnt_cmd_r[6]_i_1 (.I0(\cnt_cmd_r[6]_i_3_n_0 ), .I1(\cnt_cmd_r[6]_i_4_n_0 ), .I2(Q[5]), .O(\cnt_cmd_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair580" *) LUT3 #( .INIT(8'h6A)) \cnt_cmd_r[6]_i_2 (.I0(\cnt_cmd_r_reg_n_0_[6] ), .I1(\cnt_cmd_r_reg_n_0_[5] ), .I2(\cnt_cmd_r[6]_i_5_n_0 ), .O(\cnt_cmd_r[6]_i_2_n_0 )); LUT6 #( .INIT(64'h5544151145411111)) \cnt_cmd_r[6]_i_3 (.I0(Q[0]), .I1(Q[4]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[2]), .I4(Q[3]), .I5(Q[1]), .O(\cnt_cmd_r[6]_i_3_n_0 )); LUT6 #( .INIT(64'hA8AAA8A2A820A8AA)) \cnt_cmd_r[6]_i_4 (.I0(Q[0]), .I1(Q[3]), .I2(Q[4]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[1]), .I5(Q[2]), .O(\cnt_cmd_r[6]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair487" *) LUT5 #( .INIT(32'h80000000)) \cnt_cmd_r[6]_i_5 (.I0(\cnt_cmd_r_reg_n_0_[2] ), .I1(\cnt_cmd_r_reg_n_0_[0] ), .I2(\cnt_cmd_r_reg_n_0_[1] ), .I3(\cnt_cmd_r_reg_n_0_[3] ), .I4(\cnt_cmd_r_reg_n_0_[4] ), .O(\cnt_cmd_r[6]_i_5_n_0 )); FDRE \cnt_cmd_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[0]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[0] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE \cnt_cmd_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[1]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[1] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE \cnt_cmd_r_reg[2] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[2]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[2] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE \cnt_cmd_r_reg[3] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[3]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[3] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE \cnt_cmd_r_reg[4] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[4]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[4] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE \cnt_cmd_r_reg[5] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[5]_i_1_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[5] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE \cnt_cmd_r_reg[6] (.C(CLK), .CE(1'b1), .D(\cnt_cmd_r[6]_i_2_n_0 ), .Q(\cnt_cmd_r_reg_n_0_[6] ), .R(\cnt_cmd_r[6]_i_1_n_0 )); FDRE cnt_dllk_zqinit_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_dllk_zqinit_done_r_reg_0), .Q(cnt_dllk_zqinit_done_r), .R(cnt_dllk_zqinit_r)); LUT1 #( .INIT(2'h1)) \cnt_dllk_zqinit_r[0]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[0]), .O(p_0_in__3[0])); (* SOFT_HLUTNM = "soft_lutpair598" *) LUT2 #( .INIT(4'h6)) \cnt_dllk_zqinit_r[1]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[1]), .I1(cnt_dllk_zqinit_r_reg__0[0]), .O(p_0_in__3[1])); (* SOFT_HLUTNM = "soft_lutpair598" *) LUT3 #( .INIT(8'h6A)) \cnt_dllk_zqinit_r[2]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[2]), .I1(cnt_dllk_zqinit_r_reg__0[0]), .I2(cnt_dllk_zqinit_r_reg__0[1]), .O(p_0_in__3[2])); (* SOFT_HLUTNM = "soft_lutpair520" *) LUT4 #( .INIT(16'h6AAA)) \cnt_dllk_zqinit_r[3]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[3]), .I1(cnt_dllk_zqinit_r_reg__0[1]), .I2(cnt_dllk_zqinit_r_reg__0[0]), .I3(cnt_dllk_zqinit_r_reg__0[2]), .O(p_0_in__3[3])); (* SOFT_HLUTNM = "soft_lutpair520" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_dllk_zqinit_r[4]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[4]), .I1(cnt_dllk_zqinit_r_reg__0[2]), .I2(cnt_dllk_zqinit_r_reg__0[0]), .I3(cnt_dllk_zqinit_r_reg__0[1]), .I4(cnt_dllk_zqinit_r_reg__0[3]), .O(p_0_in__3[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_dllk_zqinit_r[5]_i_1 (.I0(cnt_dllk_zqinit_r_reg__0[5]), .I1(cnt_dllk_zqinit_r_reg__0[3]), .I2(cnt_dllk_zqinit_r_reg__0[1]), .I3(cnt_dllk_zqinit_r_reg__0[0]), .I4(cnt_dllk_zqinit_r_reg__0[2]), .I5(cnt_dllk_zqinit_r_reg__0[4]), .O(p_0_in__3[5])); (* SOFT_HLUTNM = "soft_lutpair595" *) LUT2 #( .INIT(4'h6)) \cnt_dllk_zqinit_r[6]_i_1 (.I0(mem_init_done_r_reg_0[0]), .I1(mem_init_done_r_reg_1), .O(p_0_in__3[6])); LUT6 #( .INIT(64'h0000000000000010)) \cnt_dllk_zqinit_r[7]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(cnt_dllk_zqinit_r)); (* SOFT_HLUTNM = "soft_lutpair595" *) LUT3 #( .INIT(8'h6A)) \cnt_dllk_zqinit_r[7]_i_2 (.I0(mem_init_done_r_reg_0[1]), .I1(mem_init_done_r_reg_1), .I2(mem_init_done_r_reg_0[0]), .O(p_0_in__3[7])); FDRE \cnt_dllk_zqinit_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__3[0]), .Q(cnt_dllk_zqinit_r_reg__0[0]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__3[1]), .Q(cnt_dllk_zqinit_r_reg__0[1]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__3[2]), .Q(cnt_dllk_zqinit_r_reg__0[2]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__3[3]), .Q(cnt_dllk_zqinit_r_reg__0[3]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__3[4]), .Q(cnt_dllk_zqinit_r_reg__0[4]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[5] (.C(CLK), .CE(1'b1), .D(p_0_in__3[5]), .Q(cnt_dllk_zqinit_r_reg__0[5]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[6] (.C(CLK), .CE(1'b1), .D(p_0_in__3[6]), .Q(mem_init_done_r_reg_0[0]), .R(cnt_dllk_zqinit_r)); FDRE \cnt_dllk_zqinit_r_reg[7] (.C(CLK), .CE(1'b1), .D(p_0_in__3[7]), .Q(mem_init_done_r_reg_0[1]), .R(cnt_dllk_zqinit_r)); FDRE cnt_init_af_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_init_af_done_r_reg_0), .Q(cnt_init_af_done_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair500" *) LUT4 #( .INIT(16'h009A)) \cnt_init_af_r[0]_i_1 (.I0(cnt_init_af_r[0]), .I1(mem_init_done_r), .I2(\cnt_init_mr_r_reg[1]_0 ), .I3(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_af_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair500" *) LUT5 #( .INIT(32'h00009AAA)) \cnt_init_af_r[1]_i_1 (.I0(cnt_init_af_r[1]), .I1(mem_init_done_r), .I2(\cnt_init_mr_r_reg[1]_0 ), .I3(cnt_init_af_r[0]), .I4(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_af_r[1]_i_1_n_0 )); FDRE \cnt_init_af_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cnt_init_af_r[0]_i_1_n_0 ), .Q(cnt_init_af_r[0]), .R(1'b0)); FDRE \cnt_init_af_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cnt_init_af_r[1]_i_1_n_0 ), .Q(cnt_init_af_r[1]), .R(1'b0)); LUT6 #( .INIT(64'h0000000004000000)) cnt_init_mr_done_r_i_2 (.I0(Q[5]), .I1(Q[3]), .I2(Q[4]), .I3(\init_state_r_reg[1]_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I5(mem_init_done_r), .O(cnt_init_mr_r1)); FDRE cnt_init_mr_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_init_mr_done_r_reg_0), .Q(cnt_init_mr_done_r), .R(1'b0)); LUT5 #( .INIT(32'h00006606)) \cnt_init_mr_r[0]_i_1 (.I0(cnt_init_mr_r[0]), .I1(temp_lmr_done), .I2(\cnt_init_mr_r_reg[1]_0 ), .I3(mem_init_done_r), .I4(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_mr_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000006A6A006A)) \cnt_init_mr_r[1]_i_1 (.I0(cnt_init_mr_r[1]), .I1(temp_lmr_done), .I2(cnt_init_mr_r[0]), .I3(\cnt_init_mr_r_reg[1]_0 ), .I4(mem_init_done_r), .I5(\reg_ctrl_cnt_r_reg[3]_0 ), .O(\cnt_init_mr_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \cnt_init_mr_r[1]_i_2 (.I0(Q[1]), .I1(Q[4]), .I2(Q[5]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[3]), .I5(Q[0]), .O(temp_lmr_done)); LUT6 #( .INIT(64'h0000000000080000)) \cnt_init_mr_r[1]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(Q[4]), .I4(Q[3]), .I5(Q[5]), .O(\cnt_init_mr_r_reg[1]_0 )); FDRE \cnt_init_mr_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cnt_init_mr_r[0]_i_1_n_0 ), .Q(cnt_init_mr_r[0]), .R(1'b0)); FDRE \cnt_init_mr_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cnt_init_mr_r[1]_i_1_n_0 ), .Q(cnt_init_mr_r[1]), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cnt_pwron_ce_r[0]_i_1 (.I0(cnt_pwron_ce_r_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair602" *) LUT2 #( .INIT(4'h6)) \cnt_pwron_ce_r[1]_i_1 (.I0(cnt_pwron_ce_r_reg__0[1]), .I1(cnt_pwron_ce_r_reg__0[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair602" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_ce_r[2]_i_1 (.I0(cnt_pwron_ce_r_reg__0[2]), .I1(cnt_pwron_ce_r_reg__0[0]), .I2(cnt_pwron_ce_r_reg__0[1]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair495" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_ce_r[3]_i_1 (.I0(cnt_pwron_ce_r_reg__0[3]), .I1(cnt_pwron_ce_r_reg__0[1]), .I2(cnt_pwron_ce_r_reg__0[0]), .I3(cnt_pwron_ce_r_reg__0[2]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair495" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_pwron_ce_r[4]_i_1 (.I0(cnt_pwron_ce_r_reg__0[4]), .I1(cnt_pwron_ce_r_reg__0[2]), .I2(cnt_pwron_ce_r_reg__0[0]), .I3(cnt_pwron_ce_r_reg__0[1]), .I4(cnt_pwron_ce_r_reg__0[3]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_pwron_ce_r[5]_i_1 (.I0(cnt_pwron_ce_r_reg__0[5]), .I1(cnt_pwron_ce_r_reg__0[3]), .I2(cnt_pwron_ce_r_reg__0[1]), .I3(cnt_pwron_ce_r_reg__0[0]), .I4(cnt_pwron_ce_r_reg__0[2]), .I5(cnt_pwron_ce_r_reg__0[4]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair601" *) LUT2 #( .INIT(4'h6)) \cnt_pwron_ce_r[6]_i_1 (.I0(cnt_pwron_ce_r_reg__0[6]), .I1(pwron_ce_r_i_3_n_0), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair601" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_ce_r[7]_i_1 (.I0(cnt_pwron_ce_r_reg__0[7]), .I1(pwron_ce_r_i_3_n_0), .I2(cnt_pwron_ce_r_reg__0[6]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair511" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_ce_r[8]_i_1 (.I0(cnt_pwron_ce_r_reg__0[8]), .I1(cnt_pwron_ce_r_reg__0[6]), .I2(pwron_ce_r_i_3_n_0), .I3(cnt_pwron_ce_r_reg__0[7]), .O(p_0_in__0[8])); (* SOFT_HLUTNM = "soft_lutpair511" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_pwron_ce_r[9]_i_1 (.I0(cnt_pwron_ce_r_reg__0[9]), .I1(cnt_pwron_ce_r_reg__0[7]), .I2(pwron_ce_r_i_3_n_0), .I3(cnt_pwron_ce_r_reg__0[6]), .I4(cnt_pwron_ce_r_reg__0[8]), .O(p_0_in__0[9])); FDRE \cnt_pwron_ce_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0[0]), .Q(cnt_pwron_ce_r_reg__0[0]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0[1]), .Q(cnt_pwron_ce_r_reg__0[1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0[2]), .Q(cnt_pwron_ce_r_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0[3]), .Q(cnt_pwron_ce_r_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__0[4]), .Q(cnt_pwron_ce_r_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[5] (.C(CLK), .CE(1'b1), .D(p_0_in__0[5]), .Q(cnt_pwron_ce_r_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[6] (.C(CLK), .CE(1'b1), .D(p_0_in__0[6]), .Q(cnt_pwron_ce_r_reg__0[6]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[7] (.C(CLK), .CE(1'b1), .D(p_0_in__0[7]), .Q(cnt_pwron_ce_r_reg__0[7]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[8] (.C(CLK), .CE(1'b1), .D(p_0_in__0[8]), .Q(cnt_pwron_ce_r_reg__0[8]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_ce_r_reg[9] (.C(CLK), .CE(1'b1), .D(p_0_in__0[9]), .Q(cnt_pwron_ce_r_reg__0[9]), .R(rstdiv0_sync_r1_reg_rep__19)); LUT6 #( .INIT(64'hFEFFFFFFFFFFFFFF)) cnt_pwron_cke_done_r_i_2 (.I0(cnt_pwron_r_reg__0[8]), .I1(cnt_pwron_r_reg__0[6]), .I2(\cnt_pwron_r_reg[7]_0 [2]), .I3(cnt_pwron_r_reg__0[4]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[2]), .O(cnt_pwron_cke_done_r_reg_0)); FDRE cnt_pwron_cke_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_pwron_cke_done_r_reg_1), .Q(cnt_pwron_cke_done_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cnt_pwron_r[0]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [0]), .O(p_0_in__0__0[0])); (* SOFT_HLUTNM = "soft_lutpair600" *) LUT2 #( .INIT(4'h6)) \cnt_pwron_r[1]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [1]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair600" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_r[2]_i_1 (.I0(cnt_pwron_r_reg__0[2]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .O(p_0_in__0__0[2])); (* SOFT_HLUTNM = "soft_lutpair515" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_r[3]_i_1 (.I0(cnt_pwron_r_reg__0[3]), .I1(\cnt_pwron_r_reg[7]_0 [1]), .I2(\cnt_pwron_r_reg[7]_0 [0]), .I3(cnt_pwron_r_reg__0[2]), .O(p_0_in__0__0[3])); (* SOFT_HLUTNM = "soft_lutpair515" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_pwron_r[4]_i_1 (.I0(cnt_pwron_r_reg__0[4]), .I1(cnt_pwron_r_reg__0[3]), .I2(cnt_pwron_r_reg__0[2]), .I3(\cnt_pwron_r_reg[7]_0 [1]), .I4(\cnt_pwron_r_reg[7]_0 [0]), .O(p_0_in__0__0[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_pwron_r[5]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [2]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .I3(cnt_pwron_r_reg__0[2]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[4]), .O(p_0_in__0__0[5])); LUT6 #( .INIT(64'hA6AAAAAAAAAAAAAA)) \cnt_pwron_r[6]_i_1 (.I0(cnt_pwron_r_reg__0[6]), .I1(cnt_pwron_r_reg__0[4]), .I2(\cnt_pwron_r[6]_i_2_n_0 ), .I3(\cnt_pwron_r_reg[7]_0 [1]), .I4(\cnt_pwron_r_reg[7]_0 [0]), .I5(\cnt_pwron_r_reg[7]_0 [2]), .O(p_0_in__0__0[6])); LUT2 #( .INIT(4'h7)) \cnt_pwron_r[6]_i_2 (.I0(cnt_pwron_r_reg__0[3]), .I1(cnt_pwron_r_reg__0[2]), .O(\cnt_pwron_r[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair535" *) LUT3 #( .INIT(8'h6A)) \cnt_pwron_r[7]_i_1 (.I0(\cnt_pwron_r_reg[7]_0 [3]), .I1(\cnt_pwron_r[8]_i_2_n_0 ), .I2(cnt_pwron_r_reg__0[6]), .O(p_0_in__0__0[7])); (* SOFT_HLUTNM = "soft_lutpair535" *) LUT4 #( .INIT(16'h6AAA)) \cnt_pwron_r[8]_i_1 (.I0(cnt_pwron_r_reg__0[8]), .I1(cnt_pwron_r_reg__0[6]), .I2(\cnt_pwron_r[8]_i_2_n_0 ), .I3(\cnt_pwron_r_reg[7]_0 [3]), .O(p_0_in__0__0[8])); LUT6 #( .INIT(64'h8000000000000000)) \cnt_pwron_r[8]_i_2 (.I0(\cnt_pwron_r_reg[7]_0 [2]), .I1(\cnt_pwron_r_reg[7]_0 [0]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .I3(cnt_pwron_r_reg__0[2]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[4]), .O(\cnt_pwron_r[8]_i_2_n_0 )); FDRE \cnt_pwron_r_reg[0] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[0]), .Q(\cnt_pwron_r_reg[7]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[1] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[1]), .Q(\cnt_pwron_r_reg[7]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[2] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[2]), .Q(cnt_pwron_r_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[3] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[3]), .Q(cnt_pwron_r_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[4] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[4]), .Q(cnt_pwron_r_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[5] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[5]), .Q(\cnt_pwron_r_reg[7]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[6] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[6]), .Q(cnt_pwron_r_reg__0[6]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[7] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[7]), .Q(\cnt_pwron_r_reg[7]_0 [3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \cnt_pwron_r_reg[8] (.C(CLK), .CE(pwron_ce_r), .D(p_0_in__0__0[8]), .Q(cnt_pwron_r_reg__0[8]), .R(rstdiv0_sync_r1_reg_rep__19)); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) cnt_pwron_reset_done_r_i_2 (.I0(cnt_pwron_r_reg__0[8]), .I1(cnt_pwron_r_reg__0[6]), .I2(\cnt_pwron_r_reg[7]_0 [1]), .I3(cnt_pwron_r_reg__0[4]), .I4(cnt_pwron_r_reg__0[3]), .I5(cnt_pwron_r_reg__0[2]), .O(cnt_pwron_reset_done_r_reg_0)); FDRE cnt_pwron_reset_done_r_reg (.C(CLK), .CE(1'b1), .D(\cnt_pwron_r_reg[7]_1 ), .Q(cnt_pwron_reset_done_r), .R(1'b0)); LUT3 #( .INIT(8'hBA)) \cnt_shift_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(rdlvl_stg1_start_r_reg), .I2(mpr_rdlvl_done_r_reg), .O(\cnt_shift_r_reg[0] )); LUT5 #( .INIT(32'h88C88888)) \cnt_shift_r[3]_i_2 (.I0(rdlvl_stg1_start_r_reg), .I1(phy_rddata_en_1), .I2(mpr_rdlvl_start_r_reg), .I3(mpr_rdlvl_done_r_reg), .I4(\cnt_shift_r_reg[0]_0 ), .O(E)); LUT5 #( .INIT(32'hFFFFFFEF)) cnt_txpr_done_r_i_2 (.I0(cnt_txpr_r_reg__0[7]), .I1(cnt_txpr_r_reg__0[4]), .I2(cnt_txpr_r_reg__0[6]), .I3(cnt_txpr_r_reg__0[3]), .I4(cnt_txpr_r_reg__0[5]), .O(cnt_txpr_done_r_reg_0)); FDRE cnt_txpr_done_r_reg (.C(CLK), .CE(1'b1), .D(cnt_txpr_done_r_reg_1), .Q(cnt_txpr_done_r), .R(clear)); (* SOFT_HLUTNM = "soft_lutpair609" *) LUT1 #( .INIT(2'h1)) \cnt_txpr_r[0]_i_1 (.I0(\cnt_txpr_r_reg[2]_0 [0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair609" *) LUT2 #( .INIT(4'h6)) \cnt_txpr_r[1]_i_1 (.I0(\cnt_txpr_r_reg[2]_0 [1]), .I1(\cnt_txpr_r_reg[2]_0 [0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair599" *) LUT3 #( .INIT(8'h6A)) \cnt_txpr_r[2]_i_1 (.I0(\cnt_txpr_r_reg[2]_0 [2]), .I1(\cnt_txpr_r_reg[2]_0 [0]), .I2(\cnt_txpr_r_reg[2]_0 [1]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair490" *) LUT4 #( .INIT(16'h6AAA)) \cnt_txpr_r[3]_i_1 (.I0(cnt_txpr_r_reg__0[3]), .I1(\cnt_txpr_r_reg[2]_0 [1]), .I2(\cnt_txpr_r_reg[2]_0 [0]), .I3(\cnt_txpr_r_reg[2]_0 [2]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair490" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_txpr_r[4]_i_1 (.I0(cnt_txpr_r_reg__0[4]), .I1(\cnt_txpr_r_reg[2]_0 [2]), .I2(\cnt_txpr_r_reg[2]_0 [0]), .I3(\cnt_txpr_r_reg[2]_0 [1]), .I4(cnt_txpr_r_reg__0[3]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_txpr_r[5]_i_1 (.I0(cnt_txpr_r_reg__0[5]), .I1(cnt_txpr_r_reg__0[3]), .I2(\cnt_txpr_r_reg[2]_0 [1]), .I3(\cnt_txpr_r_reg[2]_0 [0]), .I4(\cnt_txpr_r_reg[2]_0 [2]), .I5(cnt_txpr_r_reg__0[4]), .O(p_0_in__1[5])); LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_txpr_r[6]_i_1 (.I0(cnt_txpr_r_reg__0[6]), .I1(cnt_txpr_r_reg__0[4]), .I2(\cnt_txpr_r[7]_i_3_n_0 ), .I3(cnt_txpr_r_reg__0[3]), .I4(cnt_txpr_r_reg__0[5]), .O(p_0_in__1[6])); LUT1 #( .INIT(2'h1)) \cnt_txpr_r[7]_i_1 (.I0(cnt_pwron_cke_done_r), .O(clear)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \cnt_txpr_r[7]_i_2 (.I0(cnt_txpr_r_reg__0[7]), .I1(cnt_txpr_r_reg__0[6]), .I2(cnt_txpr_r_reg__0[5]), .I3(cnt_txpr_r_reg__0[3]), .I4(\cnt_txpr_r[7]_i_3_n_0 ), .I5(cnt_txpr_r_reg__0[4]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair599" *) LUT3 #( .INIT(8'h80)) \cnt_txpr_r[7]_i_3 (.I0(\cnt_txpr_r_reg[2]_0 [2]), .I1(\cnt_txpr_r_reg[2]_0 [0]), .I2(\cnt_txpr_r_reg[2]_0 [1]), .O(\cnt_txpr_r[7]_i_3_n_0 )); FDRE \cnt_txpr_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__1[0]), .Q(\cnt_txpr_r_reg[2]_0 [0]), .R(clear)); FDRE \cnt_txpr_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__1[1]), .Q(\cnt_txpr_r_reg[2]_0 [1]), .R(clear)); FDRE \cnt_txpr_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__1[2]), .Q(\cnt_txpr_r_reg[2]_0 [2]), .R(clear)); FDRE \cnt_txpr_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__1[3]), .Q(cnt_txpr_r_reg__0[3]), .R(clear)); FDRE \cnt_txpr_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__1[4]), .Q(cnt_txpr_r_reg__0[4]), .R(clear)); FDRE \cnt_txpr_r_reg[5] (.C(CLK), .CE(1'b1), .D(p_0_in__1[5]), .Q(cnt_txpr_r_reg__0[5]), .R(clear)); FDRE \cnt_txpr_r_reg[6] (.C(CLK), .CE(1'b1), .D(p_0_in__1[6]), .Q(cnt_txpr_r_reg__0[6]), .R(clear)); FDRE \cnt_txpr_r_reg[7] (.C(CLK), .CE(1'b1), .D(p_0_in__1[7]), .Q(cnt_txpr_r_reg__0[7]), .R(clear)); LUT6 #( .INIT(64'h0000404000034040)) complex_act_start_i_1 (.I0(read_calib_reg_0), .I1(Q[4]), .I2(Q[3]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[5]), .I5(prbs_rdlvl_start_i_2_n_0), .O(complex_act_start0)); FDRE complex_act_start_reg (.C(CLK), .CE(1'b1), .D(complex_act_start0), .Q(complex_act_start), .R(1'b0)); LUT5 #( .INIT(32'hFFFEFD00)) \complex_address[9]_i_1 (.I0(init_state_r1[2]), .I1(init_state_r1[6]), .I2(\complex_address[9]_i_2_n_0 ), .I3(\complex_address[9]_i_3_n_0 ), .I4(\complex_address[9]_i_4_n_0 ), .O(complex_address0)); (* SOFT_HLUTNM = "soft_lutpair513" *) LUT5 #( .INIT(32'hFFFF7FFF)) \complex_address[9]_i_2 (.I0(init_state_r1[3]), .I1(init_state_r1[4]), .I2(init_state_r1[5]), .I3(init_state_r1[0]), .I4(init_state_r1[1]), .O(\complex_address[9]_i_2_n_0 )); LUT6 #( .INIT(64'h2000000000000000)) \complex_address[9]_i_3 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(Q[2]), .I4(\init_state_r_reg_n_0_[3] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\complex_address[9]_i_3_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \complex_address[9]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\complex_address[9]_i_4_n_0 )); FDRE \complex_address_reg[0] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .Q(\complex_address_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[1] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .Q(\complex_address_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[2] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .Q(\complex_address_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[3] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .Q(\complex_address_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[4] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .Q(\complex_address_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[5] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .Q(\complex_address_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[6] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .Q(\complex_address_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[7] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .Q(\complex_address_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[8] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .Q(\complex_address_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \complex_address_reg[9] (.C(CLK), .CE(complex_address0), .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .Q(\complex_address_reg_n_0_[9] ), .R(rstdiv0_sync_r1_reg_rep__11)); LUT5 #( .INIT(32'h0000000E)) complex_byte_rd_done_i_1 (.I0(complex_byte_rd_done), .I1(complex_byte_rd_done_i_2_n_0), .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I3(prbs_rdlvl_done_pulse), .I4(rstdiv0_sync_r1_reg_rep__25), .O(complex_byte_rd_done_i_1_n_0)); LUT6 #( .INIT(64'h0000800000000000)) complex_byte_rd_done_i_2 (.I0(complex_row1_rd_cnt[0]), .I1(complex_row1_rd_cnt[1]), .I2(complex_row1_rd_cnt[2]), .I3(complex_row1_rd_done), .I4(complex_row1_rd_done_r1), .I5(prbs_rdlvl_done_reg_rep), .O(complex_byte_rd_done_i_2_n_0)); FDRE complex_byte_rd_done_reg (.C(CLK), .CE(1'b1), .D(complex_byte_rd_done_i_1_n_0), .Q(complex_byte_rd_done), .R(1'b0)); LUT5 #( .INIT(32'h000000AE)) complex_mask_lim_done_i_1 (.I0(complex_mask_lim_done), .I1(complex_oclkdelay_calib_start_int), .I2(prbs_rdlvl_done_reg), .I3(prbs_rdlvl_done_r3), .I4(rstdiv0_sync_r1_reg_rep__25), .O(complex_mask_lim_done_i_1_n_0)); FDRE complex_mask_lim_done_reg (.C(CLK), .CE(1'b1), .D(complex_mask_lim_done_i_1_n_0), .Q(complex_mask_lim_done), .R(1'b0)); LUT5 #( .INIT(32'hFFFF26EE)) \complex_num_reads[0]_i_1 (.I0(\complex_num_reads_reg_n_0_[0] ), .I1(\complex_num_reads[3]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_5_n_0 ), .I3(\complex_num_reads[2]_i_4_n_0 ), .I4(\complex_num_reads[3]_i_4_n_0 ), .O(\complex_num_reads[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000222FE22)) \complex_num_reads[1]_i_1 (.I0(\complex_num_reads_reg_n_0_[1] ), .I1(\complex_num_reads[2]_i_2_n_0 ), .I2(\complex_num_writes[2]_i_4_n_0 ), .I3(\complex_num_reads[2]_i_4_n_0 ), .I4(\complex_num_reads[1]_i_2_n_0 ), .I5(\complex_num_reads[2]_i_5_n_0 ), .O(\complex_num_reads[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair553" *) LUT4 #( .INIT(16'hA88A)) \complex_num_reads[1]_i_2 (.I0(\complex_num_reads[3]_i_8_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_reads_reg_n_0_[1] ), .I3(\complex_num_reads_reg_n_0_[0] ), .O(\complex_num_reads[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000002E2222)) \complex_num_reads[2]_i_1 (.I0(\complex_num_reads_reg_n_0_[2] ), .I1(\complex_num_reads[2]_i_2_n_0 ), .I2(\complex_num_reads[2]_i_3_n_0 ), .I3(\complex_num_writes[2]_i_4_n_0 ), .I4(\complex_num_reads[2]_i_4_n_0 ), .I5(\complex_num_reads[2]_i_5_n_0 ), .O(\complex_num_reads[2]_i_1_n_0 )); LUT3 #( .INIT(8'hEA)) \complex_num_reads[2]_i_2 (.I0(\complex_num_reads[3]_i_2_n_0 ), .I1(\complex_num_reads[2]_i_4_n_0 ), .I2(\complex_num_reads[2]_i_6_n_0 ), .O(\complex_num_reads[2]_i_2_n_0 )); LUT4 #( .INIT(16'h802A)) \complex_num_reads[2]_i_3 (.I0(\complex_num_writes[2]_i_6_n_0 ), .I1(\complex_num_reads_reg_n_0_[1] ), .I2(\complex_num_reads_reg_n_0_[0] ), .I3(\complex_num_reads_reg_n_0_[2] ), .O(\complex_num_reads[2]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000008000)) \complex_num_reads[2]_i_4 (.I0(\complex_address[9]_i_4_n_0 ), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[3]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .I5(complex_row0_rd_done), .O(\complex_num_reads[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFFEAAAAAAAAAAAAA)) \complex_num_reads[2]_i_5 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(\complex_num_reads_reg_n_0_[2] ), .I2(\complex_num_reads_reg_n_0_[1] ), .I3(\complex_num_reads_reg_n_0_[3] ), .I4(\complex_num_writes[4]_i_7_n_0 ), .I5(\complex_num_reads[2]_i_4_n_0 ), .O(\complex_num_reads[2]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \complex_num_reads[2]_i_6 (.I0(\complex_num_writes[2]_i_7_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\complex_num_reads[2]_i_6_n_0 )); LUT4 #( .INIT(16'h00E2)) \complex_num_reads[3]_i_1 (.I0(\complex_num_reads_reg_n_0_[3] ), .I1(\complex_num_reads[3]_i_2_n_0 ), .I2(\complex_num_reads[3]_i_3_n_0 ), .I3(\complex_num_reads[3]_i_4_n_0 ), .O(\complex_num_reads[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFEFEFE0EFEFEFEFE)) \complex_num_reads[3]_i_2 (.I0(\complex_num_writes[3]_i_4_n_0 ), .I1(stg1_wr_done), .I2(\complex_num_reads[2]_i_4_n_0 ), .I3(\complex_num_writes[4]_i_7_n_0 ), .I4(\complex_num_reads[3]_i_5_n_0 ), .I5(\complex_num_reads[3]_i_6_n_0 ), .O(\complex_num_reads[3]_i_2_n_0 )); LUT6 #( .INIT(64'h8AA8A8A8A8A8A8A8)) \complex_num_reads[3]_i_3 (.I0(\complex_num_reads[2]_i_4_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_reads_reg_n_0_[3] ), .I3(\complex_num_reads_reg_n_0_[1] ), .I4(\complex_num_reads_reg_n_0_[0] ), .I5(\complex_num_reads_reg_n_0_[2] ), .O(\complex_num_reads[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFEF0F0F0FEFFF0F0)) \complex_num_reads[3]_i_4 (.I0(\complex_num_reads_reg_n_0_[3] ), .I1(\complex_num_reads[3]_i_7_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__24), .I3(\complex_num_writes[4]_i_7_n_0 ), .I4(\complex_num_reads[2]_i_4_n_0 ), .I5(\complex_num_reads[3]_i_8_n_0 ), .O(\complex_num_reads[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair496" *) LUT5 #( .INIT(32'hAAAABBBF)) \complex_num_reads[3]_i_5 (.I0(\complex_num_writes[4]_i_5_n_0 ), .I1(\complex_num_reads_reg_n_0_[2] ), .I2(\complex_num_reads_reg_n_0_[0] ), .I3(\complex_num_reads_reg_n_0_[1] ), .I4(\complex_num_reads_reg_n_0_[3] ), .O(\complex_num_reads[3]_i_5_n_0 )); LUT5 #( .INIT(32'hFEAAEAAA)) \complex_num_reads[3]_i_6 (.I0(\complex_num_writes[4]_i_14_n_0 ), .I1(\complex_num_reads_reg_n_0_[1] ), .I2(\complex_num_reads_reg_n_0_[2] ), .I3(\complex_num_reads_reg_n_0_[3] ), .I4(\complex_num_writes[4]_i_15_n_0 ), .O(\complex_num_reads[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair496" *) LUT2 #( .INIT(4'h8)) \complex_num_reads[3]_i_7 (.I0(\complex_num_reads_reg_n_0_[2] ), .I1(\complex_num_reads_reg_n_0_[1] ), .O(\complex_num_reads[3]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFDEFFFFFFFFF)) \complex_num_reads[3]_i_8 (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I5(\complex_num_writes[2]_i_7_n_0 ), .O(\complex_num_reads[3]_i_8_n_0 )); LUT3 #( .INIT(8'h74)) \complex_num_reads_dec[0]_i_1 (.I0(complex_num_reads_dec_reg__0[0]), .I1(\complex_num_reads_dec[3]_i_4_n_0 ), .I2(\complex_num_reads_reg_n_0_[0] ), .O(p_0_in__8[0])); LUT4 #( .INIT(16'h9F90)) \complex_num_reads_dec[1]_i_1 (.I0(complex_num_reads_dec_reg__0[1]), .I1(complex_num_reads_dec_reg__0[0]), .I2(\complex_num_reads_dec[3]_i_4_n_0 ), .I3(\complex_num_reads_reg_n_0_[1] ), .O(p_0_in__8[1])); LUT5 #( .INIT(32'hA9FFA900)) \complex_num_reads_dec[2]_i_1 (.I0(complex_num_reads_dec_reg__0[2]), .I1(complex_num_reads_dec_reg__0[0]), .I2(complex_num_reads_dec_reg__0[1]), .I3(\complex_num_reads_dec[3]_i_4_n_0 ), .I4(\complex_num_reads_reg_n_0_[2] ), .O(p_0_in__8[2])); LUT6 #( .INIT(64'hDDDDDDDDDDDDDDD5)) \complex_num_reads_dec[3]_i_2 (.I0(\complex_num_reads_dec[3]_i_4_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I2(complex_num_reads_dec_reg__0[0]), .I3(complex_num_reads_dec_reg__0[1]), .I4(complex_num_reads_dec_reg__0[2]), .I5(complex_num_reads_dec_reg__0[3]), .O(\complex_num_reads_dec[3]_i_2_n_0 )); LUT6 #( .INIT(64'hAAA9FFFFAAA90000)) \complex_num_reads_dec[3]_i_3 (.I0(complex_num_reads_dec_reg__0[3]), .I1(complex_num_reads_dec_reg__0[2]), .I2(complex_num_reads_dec_reg__0[1]), .I3(complex_num_reads_dec_reg__0[0]), .I4(\complex_num_reads_dec[3]_i_4_n_0 ), .I5(\complex_num_reads_reg_n_0_[3] ), .O(p_0_in__8[3])); LUT6 #( .INIT(64'h5545555555555555)) \complex_num_reads_dec[3]_i_4 (.I0(\complex_num_reads_dec[3]_i_5_n_0 ), .I1(complex_row0_rd_done), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(complex_oclkdelay_calib_start_int_i_2_n_0), .I4(\init_state_r_reg[1]_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\complex_num_reads_dec[3]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00400000)) \complex_num_reads_dec[3]_i_5 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .I5(stg1_wr_done), .O(\complex_num_reads_dec[3]_i_5_n_0 )); FDSE \complex_num_reads_dec_reg[0] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_2_n_0 ), .D(p_0_in__8[0]), .Q(complex_num_reads_dec_reg__0[0]), .S(rstdiv0_sync_r1_reg_rep__18)); FDRE \complex_num_reads_dec_reg[1] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_2_n_0 ), .D(p_0_in__8[1]), .Q(complex_num_reads_dec_reg__0[1]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \complex_num_reads_dec_reg[2] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_2_n_0 ), .D(p_0_in__8[2]), .Q(complex_num_reads_dec_reg__0[2]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \complex_num_reads_dec_reg[3] (.C(CLK), .CE(\complex_num_reads_dec[3]_i_2_n_0 ), .D(p_0_in__8[3]), .Q(complex_num_reads_dec_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \complex_num_reads_reg[0] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[0]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[0] ), .R(1'b0)); FDRE \complex_num_reads_reg[1] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[1]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[1] ), .R(1'b0)); FDRE \complex_num_reads_reg[2] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[2]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[2] ), .R(1'b0)); FDRE \complex_num_reads_reg[3] (.C(CLK), .CE(1'b1), .D(\complex_num_reads[3]_i_1_n_0 ), .Q(\complex_num_reads_reg_n_0_[3] ), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF22622E6E)) \complex_num_writes[0]_i_1 (.I0(\complex_num_writes_reg_n_0_[0] ), .I1(\complex_num_writes[3]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .I3(\complex_num_writes[4]_i_5_n_0 ), .I4(\complex_num_writes[0]_i_2_n_0 ), .I5(\complex_num_writes[4]_i_6_n_0 ), .O(\complex_num_writes[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \complex_num_writes[0]_i_2 (.I0(complex_row0_wr_done), .I1(prbs_rdlvl_start_i_2_n_0), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[4]), .O(\complex_num_writes[0]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FEEE0222)) \complex_num_writes[1]_i_1 (.I0(\complex_num_writes_reg_n_0_[1] ), .I1(\complex_num_writes[2]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .I3(\complex_num_writes[2]_i_4_n_0 ), .I4(\complex_num_writes[1]_i_2_n_0 ), .I5(\complex_num_writes[2]_i_5_n_0 ), .O(\complex_num_writes[1]_i_1_n_0 )); LUT6 #( .INIT(64'hBAAABABABABABAAA)) \complex_num_writes[1]_i_2 (.I0(\complex_num_writes[0]_i_2_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .I3(\complex_num_writes[4]_i_11_n_0 ), .I4(\complex_num_writes_reg_n_0_[0] ), .I5(\complex_num_writes_reg_n_0_[1] ), .O(\complex_num_writes[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000E2E2E2)) \complex_num_writes[2]_i_1 (.I0(\complex_num_writes_reg_n_0_[2] ), .I1(\complex_num_writes[2]_i_2_n_0 ), .I2(\complex_num_writes[2]_i_3_n_0 ), .I3(\complex_num_writes[4]_i_4_n_0 ), .I4(\complex_num_writes[2]_i_4_n_0 ), .I5(\complex_num_writes[2]_i_5_n_0 ), .O(\complex_num_writes[2]_i_1_n_0 )); LUT3 #( .INIT(8'hBA)) \complex_num_writes[2]_i_2 (.I0(\complex_num_writes[4]_i_2_n_0 ), .I1(\complex_num_writes[2]_i_6_n_0 ), .I2(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFF7FD5FFFF0000)) \complex_num_writes[2]_i_3 (.I0(\complex_num_writes[2]_i_6_n_0 ), .I1(\complex_num_writes_reg_n_0_[1] ), .I2(\complex_num_writes_reg_n_0_[0] ), .I3(\complex_num_writes_reg_n_0_[2] ), .I4(\complex_num_writes[0]_i_2_n_0 ), .I5(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[2]_i_3_n_0 )); LUT6 #( .INIT(64'h0000002000000000)) \complex_num_writes[2]_i_4 (.I0(\complex_num_writes[2]_i_7_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ), .O(\complex_num_writes[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFEEEAAAAAAAAAAAA)) \complex_num_writes[2]_i_5 (.I0(complex_row0_rd_done1), .I1(\complex_num_writes[2]_i_8_n_0 ), .I2(\complex_num_writes_reg_n_0_[2] ), .I3(\complex_num_writes_reg_n_0_[1] ), .I4(\complex_num_writes[4]_i_7_n_0 ), .I5(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair553" *) LUT2 #( .INIT(4'h1)) \complex_num_writes[2]_i_6 (.I0(\complex_num_reads[2]_i_6_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .O(\complex_num_writes[2]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair561" *) LUT4 #( .INIT(16'h1000)) \complex_num_writes[2]_i_7 (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ), .O(\complex_num_writes[2]_i_7_n_0 )); LUT2 #( .INIT(4'hE)) \complex_num_writes[2]_i_8 (.I0(\complex_num_writes_reg_n_0_[4] ), .I1(\complex_num_writes_reg_n_0_[3] ), .O(\complex_num_writes[2]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000EEE2E2E2)) \complex_num_writes[3]_i_1 (.I0(\complex_num_writes_reg_n_0_[3] ), .I1(\complex_num_writes[3]_i_2_n_0 ), .I2(\complex_num_writes[3]_i_3_n_0 ), .I3(complex_row0_wr_done), .I4(\complex_num_writes[3]_i_4_n_0 ), .I5(\complex_num_writes[4]_i_6_n_0 ), .O(\complex_num_writes[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair573" *) LUT3 #( .INIT(8'hF8)) \complex_num_writes[3]_i_2 (.I0(\complex_num_writes[4]_i_5_n_0 ), .I1(\complex_num_writes[4]_i_4_n_0 ), .I2(\complex_num_writes[4]_i_2_n_0 ), .O(\complex_num_writes[3]_i_2_n_0 )); LUT6 #( .INIT(64'h8AA8A8A8A8A8A8A8)) \complex_num_writes[3]_i_3 (.I0(\complex_num_writes[4]_i_4_n_0 ), .I1(\complex_num_writes[4]_i_5_n_0 ), .I2(\complex_num_writes_reg_n_0_[3] ), .I3(\complex_num_writes_reg_n_0_[1] ), .I4(\complex_num_writes_reg_n_0_[0] ), .I5(\complex_num_writes_reg_n_0_[2] ), .O(\complex_num_writes[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000002000)) \complex_num_writes[3]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(Q[2]), .I4(\init_state_r_reg_n_0_[3] ), .I5(prbs_rdlvl_start_i_2_n_0), .O(\complex_num_writes[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000E2E2E2)) \complex_num_writes[4]_i_1 (.I0(\complex_num_writes_reg_n_0_[4] ), .I1(\complex_num_writes[4]_i_2_n_0 ), .I2(\complex_num_writes[4]_i_3_n_0 ), .I3(\complex_num_writes[4]_i_4_n_0 ), .I4(\complex_num_writes[4]_i_5_n_0 ), .I5(\complex_num_writes[4]_i_6_n_0 ), .O(\complex_num_writes[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair578" *) LUT3 #( .INIT(8'h80)) \complex_num_writes[4]_i_10 (.I0(\complex_num_writes_reg_n_0_[2] ), .I1(\complex_num_writes_reg_n_0_[0] ), .I2(\complex_num_writes_reg_n_0_[1] ), .O(\complex_num_writes[4]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair573" *) LUT3 #( .INIT(8'h04)) \complex_num_writes[4]_i_11 (.I0(\complex_num_reads[3]_i_8_n_0 ), .I1(\complex_num_writes[4]_i_4_n_0 ), .I2(\complex_num_writes[4]_i_7_n_0 ), .O(\complex_num_writes[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair606" *) LUT2 #( .INIT(4'h7)) \complex_num_writes[4]_i_12 (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\complex_num_writes[4]_i_12_n_0 )); LUT2 #( .INIT(4'hE)) \complex_num_writes[4]_i_13 (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .O(\complex_num_writes[4]_i_13_n_0 )); LUT6 #( .INIT(64'hEEEEEEECEEECEEEC)) \complex_num_writes[4]_i_14 (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I1(\complex_num_writes[4]_i_13_n_0 ), .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I5(\stg1_wr_rd_cnt[4]_i_3_n_0 ), .O(\complex_num_writes[4]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFEFFFEFFFEFEFE)) \complex_num_writes[4]_i_15 (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ), .O(\complex_num_writes[4]_i_15_n_0 )); LUT5 #( .INIT(32'hEEE2EEEE)) \complex_num_writes[4]_i_2 (.I0(\complex_num_writes[3]_i_4_n_0 ), .I1(\complex_num_writes[4]_i_4_n_0 ), .I2(\complex_num_writes[4]_i_7_n_0 ), .I3(\complex_num_writes[4]_i_8_n_0 ), .I4(\complex_num_writes[4]_i_9_n_0 ), .O(\complex_num_writes[4]_i_2_n_0 )); LUT6 #( .INIT(64'hFF6A6A6AFF000000)) \complex_num_writes[4]_i_3 (.I0(\complex_num_writes_reg_n_0_[4] ), .I1(\complex_num_writes_reg_n_0_[3] ), .I2(\complex_num_writes[4]_i_10_n_0 ), .I3(complex_row0_wr_done), .I4(\complex_num_writes[3]_i_4_n_0 ), .I5(\complex_num_writes[4]_i_4_n_0 ), .O(\complex_num_writes[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000008000)) \complex_num_writes[4]_i_4 (.I0(\complex_address[9]_i_3_n_0 ), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[3]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .I5(complex_row0_wr_done), .O(\complex_num_writes[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair489" *) LUT5 #( .INIT(32'h40000000)) \complex_num_writes[4]_i_5 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\complex_num_writes[4]_i_5_n_0 )); LUT2 #( .INIT(4'hE)) \complex_num_writes[4]_i_6 (.I0(\complex_num_writes[2]_i_5_n_0 ), .I1(\complex_num_writes[4]_i_11_n_0 ), .O(\complex_num_writes[4]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF008A00)) \complex_num_writes[4]_i_7 (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I2(\complex_num_writes[4]_i_12_n_0 ), .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I5(\complex_num_writes[4]_i_13_n_0 ), .O(\complex_num_writes[4]_i_7_n_0 )); LUT6 #( .INIT(64'h000000000000222A)) \complex_num_writes[4]_i_8 (.I0(\complex_num_writes[4]_i_14_n_0 ), .I1(\complex_num_writes_reg_n_0_[2] ), .I2(\complex_num_writes_reg_n_0_[0] ), .I3(\complex_num_writes_reg_n_0_[1] ), .I4(\complex_num_writes_reg_n_0_[4] ), .I5(\complex_num_writes_reg_n_0_[3] ), .O(\complex_num_writes[4]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFE080)) \complex_num_writes[4]_i_9 (.I0(\complex_num_writes_reg_n_0_[1] ), .I1(\complex_num_writes_reg_n_0_[2] ), .I2(\complex_num_writes_reg_n_0_[3] ), .I3(\complex_num_writes[4]_i_15_n_0 ), .I4(\complex_num_writes[4]_i_14_n_0 ), .I5(\complex_num_writes_reg_n_0_[4] ), .O(\complex_num_writes[4]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair578" *) LUT3 #( .INIT(8'h74)) \complex_num_writes_dec[0]_i_1 (.I0(complex_num_writes_dec_reg__0[0]), .I1(\complex_num_writes_dec[4]_i_4_n_0 ), .I2(\complex_num_writes_reg_n_0_[0] ), .O(p_0_in__7[0])); LUT4 #( .INIT(16'h9F90)) \complex_num_writes_dec[1]_i_1 (.I0(complex_num_writes_dec_reg__0[0]), .I1(complex_num_writes_dec_reg__0[1]), .I2(\complex_num_writes_dec[4]_i_4_n_0 ), .I3(\complex_num_writes_reg_n_0_[1] ), .O(p_0_in__7[1])); (* SOFT_HLUTNM = "soft_lutpair491" *) LUT5 #( .INIT(32'hA9FFA900)) \complex_num_writes_dec[2]_i_1 (.I0(complex_num_writes_dec_reg__0[2]), .I1(complex_num_writes_dec_reg__0[1]), .I2(complex_num_writes_dec_reg__0[0]), .I3(\complex_num_writes_dec[4]_i_4_n_0 ), .I4(\complex_num_writes_reg_n_0_[2] ), .O(p_0_in__7[2])); LUT6 #( .INIT(64'hAAA9FFFFAAA90000)) \complex_num_writes_dec[3]_i_1 (.I0(complex_num_writes_dec_reg__0[3]), .I1(complex_num_writes_dec_reg__0[2]), .I2(complex_num_writes_dec_reg__0[0]), .I3(complex_num_writes_dec_reg__0[1]), .I4(\complex_num_writes_dec[4]_i_4_n_0 ), .I5(\complex_num_writes_reg_n_0_[3] ), .O(p_0_in__7[3])); LUT2 #( .INIT(4'hE)) \complex_num_writes_dec[4]_i_1 (.I0(prbs_rdlvl_done_pulse), .I1(rstdiv0_sync_r1_reg_rep__24), .O(complex_row0_rd_done1)); LUT5 #( .INIT(32'hDDDDDDD5)) \complex_num_writes_dec[4]_i_2 (.I0(\complex_num_writes_dec[4]_i_4_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I2(complex_num_writes_dec_reg__0[1]), .I3(complex_num_writes_dec_reg__0[0]), .I4(\complex_num_writes_dec[4]_i_5_n_0 ), .O(\complex_num_writes_dec[4]_i_2_n_0 )); LUT6 #( .INIT(64'hAA9AFFFFAA9A0000)) \complex_num_writes_dec[4]_i_3 (.I0(complex_num_writes_dec_reg__0[4]), .I1(complex_num_writes_dec_reg__0[3]), .I2(\complex_num_writes_dec[4]_i_6_n_0 ), .I3(complex_num_writes_dec_reg__0[2]), .I4(\complex_num_writes_dec[4]_i_4_n_0 ), .I5(\complex_num_writes_reg_n_0_[4] ), .O(p_0_in__7[4])); LUT5 #( .INIT(32'h10111111)) \complex_num_writes_dec[4]_i_4 (.I0(stg1_wr_done), .I1(\complex_num_writes[3]_i_4_n_0 ), .I2(complex_row0_rd_done), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(\complex_address[9]_i_3_n_0 ), .O(\complex_num_writes_dec[4]_i_4_n_0 )); LUT3 #( .INIT(8'hFE)) \complex_num_writes_dec[4]_i_5 (.I0(complex_num_writes_dec_reg__0[3]), .I1(complex_num_writes_dec_reg__0[2]), .I2(complex_num_writes_dec_reg__0[4]), .O(\complex_num_writes_dec[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair491" *) LUT2 #( .INIT(4'h1)) \complex_num_writes_dec[4]_i_6 (.I0(complex_num_writes_dec_reg__0[0]), .I1(complex_num_writes_dec_reg__0[1]), .O(\complex_num_writes_dec[4]_i_6_n_0 )); FDSE \complex_num_writes_dec_reg[0] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[0]), .Q(complex_num_writes_dec_reg__0[0]), .S(complex_row0_rd_done1)); FDRE \complex_num_writes_dec_reg[1] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[1]), .Q(complex_num_writes_dec_reg__0[1]), .R(complex_row0_rd_done1)); FDRE \complex_num_writes_dec_reg[2] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[2]), .Q(complex_num_writes_dec_reg__0[2]), .R(complex_row0_rd_done1)); FDRE \complex_num_writes_dec_reg[3] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[3]), .Q(complex_num_writes_dec_reg__0[3]), .R(complex_row0_rd_done1)); FDRE \complex_num_writes_dec_reg[4] (.C(CLK), .CE(\complex_num_writes_dec[4]_i_2_n_0 ), .D(p_0_in__7[4]), .Q(complex_num_writes_dec_reg__0[4]), .R(complex_row0_rd_done1)); FDRE \complex_num_writes_reg[0] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[0]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[0] ), .R(1'b0)); FDRE \complex_num_writes_reg[1] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[1]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[1] ), .R(1'b0)); FDRE \complex_num_writes_reg[2] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[2]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[2] ), .R(1'b0)); FDRE \complex_num_writes_reg[3] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[3]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[3] ), .R(1'b0)); FDRE \complex_num_writes_reg[4] (.C(CLK), .CE(1'b1), .D(\complex_num_writes[4]_i_1_n_0 ), .Q(\complex_num_writes_reg_n_0_[4] ), .R(1'b0)); LUT5 #( .INIT(32'h0000AABA)) complex_ocal_odt_ext_i_1 (.I0(complex_ocal_odt_ext), .I1(complex_ocal_odt_ext_i_2_n_0), .I2(Q[5]), .I3(Q[1]), .I4(complex_ocal_odt_ext_i_3_n_0), .O(complex_ocal_odt_ext_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair541" *) LUT4 #( .INIT(16'hFFFE)) complex_ocal_odt_ext_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .O(complex_ocal_odt_ext_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFF400040F0)) complex_ocal_odt_ext_i_3 (.I0(\back_to_back_reads_4_1.num_reads_reg[0]_0 ), .I1(cnt_cmd_done_m7_r), .I2(Q[1]), .I3(Q[0]), .I4(complex_ocal_odt_ext_i_4_n_0), .I5(rstdiv0_sync_r1_reg_rep__24), .O(complex_ocal_odt_ext_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair521" *) LUT5 #( .INIT(32'hFFEFFFFF)) complex_ocal_odt_ext_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .O(complex_ocal_odt_ext_i_4_n_0)); FDRE complex_ocal_odt_ext_reg (.C(CLK), .CE(1'b1), .D(complex_ocal_odt_ext_i_1_n_0), .Q(complex_ocal_odt_ext), .R(1'b0)); LUT6 #( .INIT(64'h44444F4444444444)) complex_ocal_reset_rd_addr_i_1 (.I0(prbs_last_byte_done_r), .I1(prbs_last_byte_done), .I2(complex_ocal_reset_rd_addr_i_2_n_0), .I3(complex_wait_cnt_reg__0[3]), .I4(complex_wait_cnt_reg__0[2]), .I5(complex_ocal_reset_rd_addr_i_3_n_0), .O(complex_ocal_reset_rd_addr0)); (* SOFT_HLUTNM = "soft_lutpair605" *) LUT2 #( .INIT(4'hB)) complex_ocal_reset_rd_addr_i_2 (.I0(complex_wait_cnt_reg__0[1]), .I1(complex_wait_cnt_reg__0[0]), .O(complex_ocal_reset_rd_addr_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) complex_ocal_reset_rd_addr_i_3 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r[4]_i_5_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(complex_ocal_reset_rd_addr_i_3_n_0)); FDRE complex_ocal_reset_rd_addr_reg (.C(CLK), .CE(1'b1), .D(complex_ocal_reset_rd_addr0), .Q(complex_ocal_reset_rd_addr), .R(1'b0)); LUT2 #( .INIT(4'hE)) complex_ocal_wr_start_i_1 (.I0(complex_ocal_reset_rd_addr), .I1(complex_ocal_wr_start), .O(complex_ocal_wr_start_i_1_n_0)); FDRE complex_ocal_wr_start_reg (.C(CLK), .CE(1'b1), .D(complex_ocal_wr_start_i_1_n_0), .Q(complex_ocal_wr_start), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE complex_oclkdelay_calib_done_r1_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_reg_rep), .Q(complex_oclkdelay_calib_done_r1), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'hFFFFFFFF00040000)) complex_oclkdelay_calib_start_int_i_1 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(complex_oclkdelay_calib_start_int_reg_0), .I4(prbs_last_byte_done_r), .I5(complex_oclkdelay_calib_start_int), .O(complex_oclkdelay_calib_start_int_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair572" *) LUT3 #( .INIT(8'hDF)) complex_oclkdelay_calib_start_int_i_2 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .O(complex_oclkdelay_calib_start_int_i_2_n_0)); LUT2 #( .INIT(4'hB)) complex_oclkdelay_calib_start_int_i_3 (.I0(Q[0]), .I1(Q[1]), .O(complex_oclkdelay_calib_start_int_reg_0)); FDRE complex_oclkdelay_calib_start_int_reg (.C(CLK), .CE(1'b1), .D(complex_oclkdelay_calib_start_int_i_1_n_0), .Q(complex_oclkdelay_calib_start_int), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE complex_oclkdelay_calib_start_r1_reg (.C(CLK), .CE(1'b1), .D(complex_oclkdelay_calib_start_int), .Q(complex_oclkdelay_calib_start_r1), .R(1'b0)); FDRE complex_oclkdelay_calib_start_r2_reg (.C(CLK), .CE(1'b1), .D(complex_oclkdelay_calib_start_r1), .Q(complex_oclkdelay_calib_start_r2), .R(1'b0)); LUT6 #( .INIT(64'h000000000000AAEA)) complex_odt_ext_i_1 (.I0(complex_odt_ext), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I2(rdlvl_stg1_done_r1), .I3(complex_sample_cnt_inc_i_2_n_0), .I4(complex_row1_rd_done_i_2_n_0), .I5(rstdiv0_sync_r1_reg_rep__24), .O(complex_odt_ext_i_1_n_0)); FDRE complex_odt_ext_reg (.C(CLK), .CE(1'b1), .D(complex_odt_ext_i_1_n_0), .Q(complex_odt_ext), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair560" *) LUT4 #( .INIT(16'h0002)) complex_row0_rd_done_i_1 (.I0(complex_row0_rd_done_i_2_n_0), .I1(prbs_rdlvl_done_pulse), .I2(rstdiv0_sync_r1_reg_rep__25), .I3(complex_sample_cnt_inc), .O(complex_row0_rd_done_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF0000E000)) complex_row0_rd_done_i_2 (.I0(prbs_rdlvl_start_r_reg), .I1(complex_oclkdelay_calib_start_int), .I2(complex_row1_wr_done), .I3(complex_row0_wr_done), .I4(wr_victim_inc_i_2_n_0), .I5(complex_row0_rd_done), .O(complex_row0_rd_done_i_2_n_0)); FDRE complex_row0_rd_done_reg (.C(CLK), .CE(1'b1), .D(complex_row0_rd_done_i_1_n_0), .Q(complex_row0_rd_done), .R(1'b0)); LUT5 #( .INIT(32'h0000009A)) \complex_row1_rd_cnt[0]_i_1 (.I0(complex_row1_rd_cnt[0]), .I1(complex_row1_rd_done_r1), .I2(complex_row1_rd_done), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(prbs_rdlvl_done_pulse), .O(\complex_row1_rd_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000009AAA)) \complex_row1_rd_cnt[1]_i_1 (.I0(complex_row1_rd_cnt[1]), .I1(complex_row1_rd_done_r1), .I2(complex_row1_rd_done), .I3(complex_row1_rd_cnt[0]), .I4(rstdiv0_sync_r1_reg_rep__25), .I5(prbs_rdlvl_done_pulse), .O(\complex_row1_rd_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000009AAAAAAA)) \complex_row1_rd_cnt[2]_i_1 (.I0(complex_row1_rd_cnt[2]), .I1(complex_row1_rd_done_r1), .I2(complex_row1_rd_done), .I3(complex_row1_rd_cnt[0]), .I4(complex_row1_rd_cnt[1]), .I5(complex_row0_rd_done1), .O(\complex_row1_rd_cnt[2]_i_1_n_0 )); FDRE \complex_row1_rd_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\complex_row1_rd_cnt[0]_i_1_n_0 ), .Q(complex_row1_rd_cnt[0]), .R(1'b0)); FDRE \complex_row1_rd_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\complex_row1_rd_cnt[1]_i_1_n_0 ), .Q(complex_row1_rd_cnt[1]), .R(1'b0)); FDRE \complex_row1_rd_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\complex_row1_rd_cnt[2]_i_1_n_0 ), .Q(complex_row1_rd_cnt[2]), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000AE)) complex_row1_rd_done_i_1 (.I0(complex_row1_rd_done), .I1(complex_row0_rd_done), .I2(wr_victim_inc_i_2_n_0), .I3(complex_row1_rd_done_i_2_n_0), .I4(prbs_rdlvl_done_pulse), .I5(rstdiv0_sync_r1_reg_rep__25), .O(complex_row1_rd_done_i_1_n_0)); LUT6 #( .INIT(64'h0000000000100000)) complex_row1_rd_done_i_2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[3]), .I5(Q[5]), .O(complex_row1_rd_done_i_2_n_0)); FDRE complex_row1_rd_done_r1_reg (.C(CLK), .CE(1'b1), .D(complex_row1_rd_done), .Q(complex_row1_rd_done_r1), .R(1'b0)); FDRE complex_row1_rd_done_reg (.C(CLK), .CE(1'b1), .D(complex_row1_rd_done_i_1_n_0), .Q(complex_row1_rd_done), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair612" *) LUT1 #( .INIT(2'h1)) \complex_row_cnt_ocal[0]_i_1 (.I0(complex_row_cnt_ocal_reg__0[0]), .O(p_0_in__5[0])); (* SOFT_HLUTNM = "soft_lutpair612" *) LUT2 #( .INIT(4'h6)) \complex_row_cnt_ocal[1]_i_1 (.I0(complex_row_cnt_ocal_reg__0[1]), .I1(complex_row_cnt_ocal_reg__0[0]), .O(p_0_in__5[1])); (* SOFT_HLUTNM = "soft_lutpair563" *) LUT3 #( .INIT(8'h6A)) \complex_row_cnt_ocal[2]_i_1 (.I0(complex_row_cnt_ocal_reg__0[2]), .I1(complex_row_cnt_ocal_reg__0[0]), .I2(complex_row_cnt_ocal_reg__0[1]), .O(p_0_in__5[2])); (* SOFT_HLUTNM = "soft_lutpair563" *) LUT4 #( .INIT(16'h6AAA)) \complex_row_cnt_ocal[3]_i_1 (.I0(complex_row_cnt_ocal_reg__0[3]), .I1(complex_row_cnt_ocal_reg__0[1]), .I2(complex_row_cnt_ocal_reg__0[0]), .I3(complex_row_cnt_ocal_reg__0[2]), .O(p_0_in__5[3])); (* SOFT_HLUTNM = "soft_lutpair483" *) LUT5 #( .INIT(32'h6AAAAAAA)) \complex_row_cnt_ocal[4]_i_1 (.I0(complex_row_cnt_ocal_reg__0[4]), .I1(complex_row_cnt_ocal_reg__0[3]), .I2(complex_row_cnt_ocal_reg__0[2]), .I3(complex_row_cnt_ocal_reg__0[0]), .I4(complex_row_cnt_ocal_reg__0[1]), .O(p_0_in__5[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \complex_row_cnt_ocal[5]_i_1 (.I0(complex_row_cnt_ocal_reg__0[5]), .I1(complex_row_cnt_ocal_reg__0[1]), .I2(complex_row_cnt_ocal_reg__0[0]), .I3(complex_row_cnt_ocal_reg__0[2]), .I4(complex_row_cnt_ocal_reg__0[3]), .I5(complex_row_cnt_ocal_reg__0[4]), .O(p_0_in__5[5])); (* SOFT_HLUTNM = "soft_lutpair512" *) LUT4 #( .INIT(16'h6AAA)) \complex_row_cnt_ocal[6]_i_1 (.I0(complex_row_cnt_ocal_reg__0[6]), .I1(complex_row_cnt_ocal_reg__0[4]), .I2(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I3(complex_row_cnt_ocal_reg__0[5]), .O(p_0_in__5[6])); LUT5 #( .INIT(32'hFFFFFFFB)) \complex_row_cnt_ocal[7]_i_1 (.I0(\complex_row_cnt_ocal_reg[0]_0 ), .I1(rdlvl_stg1_done_r1), .I2(complex_byte_rd_done), .I3(rstdiv0_sync_r1_reg_rep__24), .I4(prbs_rdlvl_done_pulse), .O(complex_row_cnt_ocal0)); LUT6 #( .INIT(64'hAAAAAAAAAAAA0800)) \complex_row_cnt_ocal[7]_i_2 (.I0(\complex_row_cnt_ocal[7]_i_5_n_0 ), .I1(\complex_row_cnt_ocal[7]_i_6_n_0 ), .I2(\complex_row_cnt_ocal[7]_i_7_n_0 ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(wr_victim_inc), .I5(complex_sample_cnt_inc_r2), .O(complex_row_cnt_ocal)); (* SOFT_HLUTNM = "soft_lutpair512" *) LUT5 #( .INIT(32'h6AAAAAAA)) \complex_row_cnt_ocal[7]_i_3 (.I0(complex_row_cnt_ocal_reg__0[7]), .I1(complex_row_cnt_ocal_reg__0[5]), .I2(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I3(complex_row_cnt_ocal_reg__0[4]), .I4(complex_row_cnt_ocal_reg__0[6]), .O(p_0_in__5[7])); LUT6 #( .INIT(64'h0000000000000008)) \complex_row_cnt_ocal[7]_i_4 (.I0(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I1(wr_victim_inc), .I2(complex_row_cnt_ocal_reg__0[4]), .I3(complex_row_cnt_ocal_reg__0[7]), .I4(complex_row_cnt_ocal_reg__0[5]), .I5(complex_row_cnt_ocal_reg__0[6]), .O(\complex_row_cnt_ocal_reg[0]_0 )); LUT6 #( .INIT(64'h0000000000000004)) \complex_row_cnt_ocal[7]_i_5 (.I0(\complex_row_cnt_ocal[7]_i_8_n_0 ), .I1(prbs_rdlvl_done_reg_rep), .I2(complex_row_cnt_ocal_reg__0[4]), .I3(complex_row_cnt_ocal_reg__0[7]), .I4(complex_row_cnt_ocal_reg__0[5]), .I5(complex_row_cnt_ocal_reg__0[6]), .O(\complex_row_cnt_ocal[7]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000002000)) \complex_row_cnt_ocal[7]_i_6 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\wrcal_reads[7]_i_5_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(\complex_row_cnt_ocal[7]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFFFFFFFF)) \complex_row_cnt_ocal[7]_i_7 (.I0(\complex_row_cnt_ocal[7]_i_9_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[1] ), .O(\complex_row_cnt_ocal[7]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair483" *) LUT4 #( .INIT(16'h8000)) \complex_row_cnt_ocal[7]_i_8 (.I0(complex_row_cnt_ocal_reg__0[1]), .I1(complex_row_cnt_ocal_reg__0[0]), .I2(complex_row_cnt_ocal_reg__0[2]), .I3(complex_row_cnt_ocal_reg__0[3]), .O(\complex_row_cnt_ocal[7]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair517" *) LUT3 #( .INIT(8'hFE)) \complex_row_cnt_ocal[7]_i_9 (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ), .O(\complex_row_cnt_ocal[7]_i_9_n_0 )); FDRE \complex_row_cnt_ocal_reg[0] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[0]), .Q(complex_row_cnt_ocal_reg__0[0]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[1] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[1]), .Q(complex_row_cnt_ocal_reg__0[1]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[2] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[2]), .Q(complex_row_cnt_ocal_reg__0[2]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[3] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[3]), .Q(complex_row_cnt_ocal_reg__0[3]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[4] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[4]), .Q(complex_row_cnt_ocal_reg__0[4]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[5] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[5]), .Q(complex_row_cnt_ocal_reg__0[5]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[6] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[6]), .Q(complex_row_cnt_ocal_reg__0[6]), .R(complex_row_cnt_ocal0)); FDRE \complex_row_cnt_ocal_reg[7] (.C(CLK), .CE(complex_row_cnt_ocal), .D(p_0_in__5[7]), .Q(complex_row_cnt_ocal_reg__0[7]), .R(complex_row_cnt_ocal0)); LUT2 #( .INIT(4'h2)) complex_sample_cnt_inc_i_1 (.I0(complex_row1_rd_done), .I1(complex_sample_cnt_inc_i_2_n_0), .O(complex_sample_cnt_inc0)); (* SOFT_HLUTNM = "soft_lutpair489" *) LUT5 #( .INIT(32'hFFFFFFEF)) complex_sample_cnt_inc_i_2 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(complex_sample_cnt_inc_i_2_n_0)); FDRE complex_sample_cnt_inc_r1_reg (.C(CLK), .CE(1'b1), .D(complex_sample_cnt_inc), .Q(complex_sample_cnt_inc_r1), .R(1'b0)); FDRE complex_sample_cnt_inc_r2_reg (.C(CLK), .CE(1'b1), .D(complex_sample_cnt_inc_r1), .Q(complex_sample_cnt_inc_r2), .R(1'b0)); FDRE complex_sample_cnt_inc_reg (.C(CLK), .CE(1'b1), .D(complex_sample_cnt_inc0), .Q(complex_sample_cnt_inc), .R(rstdiv0_sync_r1_reg_rep__12)); LUT1 #( .INIT(2'h1)) \complex_wait_cnt[0]_i_1 (.I0(complex_wait_cnt_reg__0[0]), .O(p_0_in__6[0])); (* SOFT_HLUTNM = "soft_lutpair605" *) LUT2 #( .INIT(4'h6)) \complex_wait_cnt[1]_i_1 (.I0(complex_wait_cnt_reg__0[1]), .I1(complex_wait_cnt_reg__0[0]), .O(p_0_in__6[1])); (* SOFT_HLUTNM = "soft_lutpair557" *) LUT3 #( .INIT(8'h78)) \complex_wait_cnt[2]_i_1 (.I0(complex_wait_cnt_reg__0[1]), .I1(complex_wait_cnt_reg__0[0]), .I2(complex_wait_cnt_reg__0[2]), .O(p_0_in__6[2])); LUT6 #( .INIT(64'hFFFFFFFFFBABEFBF)) \complex_wait_cnt[3]_i_1 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(Q[0]), .I5(\complex_wait_cnt[3]_i_3_n_0 ), .O(\complex_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair557" *) LUT4 #( .INIT(16'h6AAA)) \complex_wait_cnt[3]_i_2 (.I0(complex_wait_cnt_reg__0[3]), .I1(complex_wait_cnt_reg__0[1]), .I2(complex_wait_cnt_reg__0[0]), .I3(complex_wait_cnt_reg__0[2]), .O(p_0_in__6[3])); (* SOFT_HLUTNM = "soft_lutpair505" *) LUT5 #( .INIT(32'hEAAAAAAA)) \complex_wait_cnt[3]_i_3 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(complex_wait_cnt_reg__0[3]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .O(\complex_wait_cnt[3]_i_3_n_0 )); FDRE \complex_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__6[0]), .Q(complex_wait_cnt_reg__0[0]), .R(\complex_wait_cnt[3]_i_1_n_0 )); FDRE \complex_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__6[1]), .Q(complex_wait_cnt_reg__0[1]), .R(\complex_wait_cnt[3]_i_1_n_0 )); FDRE \complex_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__6[2]), .Q(complex_wait_cnt_reg__0[2]), .R(\complex_wait_cnt[3]_i_1_n_0 )); FDRE \complex_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__6[3]), .Q(complex_wait_cnt_reg__0[3]), .R(\complex_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair588" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[0]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[0]), .O(\data_offset_1_i1_reg[5] [0])); (* SOFT_HLUTNM = "soft_lutpair589" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[1] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[1]), .O(\data_offset_1_i1_reg[5] [1])); (* SOFT_HLUTNM = "soft_lutpair590" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[2]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[2] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[2]), .O(\data_offset_1_i1_reg[5] [2])); (* SOFT_HLUTNM = "soft_lutpair591" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[3]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[3] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[3]), .O(\data_offset_1_i1_reg[5] [3])); (* SOFT_HLUTNM = "soft_lutpair590" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[4]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[4] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[4]), .O(\data_offset_1_i1_reg[5] [4])); (* SOFT_HLUTNM = "soft_lutpair589" *) LUT3 #( .INIT(8'hB8)) \data_offset_1_i1[5]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] ), .I1(init_calib_complete_reg_rep__14), .I2(calib_data_offset_1[5]), .O(\data_offset_1_i1_reg[5] [5])); (* SOFT_HLUTNM = "soft_lutpair539" *) LUT4 #( .INIT(16'h8000)) ddr2_pre_flag_r_i_2 (.I0(ddr2_refresh_flag_r_reg_0), .I1(cnt_cmd_done_r), .I2(ddr2_refresh_flag_r), .I3(cnt_init_mr_done_r), .O(ddr2_pre_flag_r_reg_1)); FDRE ddr2_pre_flag_r_reg (.C(CLK), .CE(1'b1), .D(ddr2_pre_flag_r_reg_2), .Q(ddr2_pre_flag_r_reg_0), .R(1'b0)); LUT6 #( .INIT(64'h0000010000000000)) ddr2_refresh_flag_r_i_2 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[5]), .I2(Q[4]), .I3(Q[0]), .I4(Q[3]), .I5(Q[1]), .O(ddr2_refresh_flag_r_reg_0)); FDRE ddr2_refresh_flag_r_reg (.C(CLK), .CE(1'b1), .D(cnt_cmd_done_r_reg_0), .Q(ddr2_refresh_flag_r), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000200)) ddr3_lm_done_r_i_1 (.I0(wrcal_done_reg_10), .I1(oclk_calib_resume_level_reg_0), .I2(\init_state_r[5]_i_2_n_0 ), .I3(Q[0]), .I4(ddr3_lm_done_r_i_2_n_0), .I5(ddr3_lm_done_r), .O(ddr3_lm_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair498" *) LUT2 #( .INIT(4'hB)) ddr3_lm_done_r_i_2 (.I0(Q[3]), .I1(Q[1]), .O(ddr3_lm_done_r_i_2_n_0)); FDRE ddr3_lm_done_r_reg (.C(CLK), .CE(1'b1), .D(ddr3_lm_done_r_i_1_n_0), .Q(ddr3_lm_done_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'h0000000000000080)) detect_pi_found_dqs_i_1 (.I0(\cnt_cmd_r_reg_n_0_[5] ), .I1(\cnt_cmd_r[6]_i_5_n_0 ), .I2(Q[1]), .I3(Q[0]), .I4(\back_to_back_reads_4_1.num_reads_reg[0]_0 ), .I5(\cnt_cmd_r_reg_n_0_[6] ), .O(detect_pi_found_dqs0)); FDRE detect_pi_found_dqs_reg (.C(CLK), .CE(1'b1), .D(detect_pi_found_dqs0), .Q(detect_pi_found_dqs), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h00000000DADA00DA)) \dqs_asrt_cnt[0]_i_1 (.I0(dqs_asrt_cnt[0]), .I1(dqs_asrt_cnt[1]), .I2(wr_level_dqs_asrt), .I3(wrlvl_done_r), .I4(wrlvl_done_r1), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\dqs_asrt_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000ECEC00EC)) \dqs_asrt_cnt[1]_i_1 (.I0(dqs_asrt_cnt[0]), .I1(dqs_asrt_cnt[1]), .I2(wr_level_dqs_asrt), .I3(wrlvl_done_r), .I4(wrlvl_done_r1), .I5(rstdiv0_sync_r1_reg_rep__25), .O(\dqs_asrt_cnt[1]_i_1_n_0 )); FDRE \dqs_asrt_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\dqs_asrt_cnt[0]_i_1_n_0 ), .Q(dqs_asrt_cnt[0]), .R(1'b0)); FDRE \dqs_asrt_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\dqs_asrt_cnt[1]_i_1_n_0 ), .Q(dqs_asrt_cnt[1]), .R(1'b0)); LUT6 #( .INIT(64'h000000000F0F0F0E)) \en_cnt_div4.enable_wrlvl_cnt[0]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(rstdiv0_sync_r1_reg_rep__24_0), .O(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000F00FF00E)) \en_cnt_div4.enable_wrlvl_cnt[1]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(rstdiv0_sync_r1_reg_rep__24_0), .O(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFF0000E)) \en_cnt_div4.enable_wrlvl_cnt[2]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ), .O(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAA4)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_2 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ), .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h444444444444444F)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_3 (.I0(enable_wrlvl_cnt0), .I1(wrlvl_odt), .I2(read_calib_reg_0), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair519" *) LUT5 #( .INIT(32'hFFFFFFFE)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_4 (.I0(enable_wrlvl_cnt[2]), .I1(enable_wrlvl_cnt[1]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[4]), .I4(enable_wrlvl_cnt[3]), .O(enable_wrlvl_cnt0)); LUT6 #( .INIT(64'h00000000CCCCCCC8)) \en_cnt_div4.enable_wrlvl_cnt[4]_i_1 (.I0(enable_wrlvl_cnt[3]), .I1(enable_wrlvl_cnt[4]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[1]), .I4(enable_wrlvl_cnt[2]), .I5(rstdiv0_sync_r1_reg_rep__24_0), .O(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 )); FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ), .Q(enable_wrlvl_cnt[0]), .R(1'b0)); FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ), .Q(enable_wrlvl_cnt[1]), .R(1'b0)); FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ), .Q(enable_wrlvl_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ), .Q(enable_wrlvl_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ), .Q(enable_wrlvl_cnt[4]), .R(1'b0)); LUT4 #( .INIT(16'h000E)) \en_cnt_div4.wrlvl_odt_i_1 (.I0(wrlvl_odt), .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ), .I2(wrlvl_odt_ctl), .I3(rstdiv0_sync_r1_reg_rep__25), .O(\en_cnt_div4.wrlvl_odt_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair519" *) LUT5 #( .INIT(32'h00000010)) \en_cnt_div4.wrlvl_odt_i_2 (.I0(enable_wrlvl_cnt[4]), .I1(enable_wrlvl_cnt[3]), .I2(enable_wrlvl_cnt[0]), .I3(enable_wrlvl_cnt[2]), .I4(enable_wrlvl_cnt[1]), .O(\en_cnt_div4.wrlvl_odt_i_2_n_0 )); FDRE \en_cnt_div4.wrlvl_odt_reg (.C(CLK), .CE(1'b1), .D(\en_cnt_div4.wrlvl_odt_i_1_n_0 ), .Q(wrlvl_odt), .R(1'b0)); LUT4 #( .INIT(16'hFFF4)) first_rdlvl_pat_r_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(first_rdlvl_pat_r), .I2(rdlvl_stg1_rank_done), .I3(rstdiv0_sync_r1_reg_rep__24), .O(first_rdlvl_pat_r_i_1_n_0)); FDRE first_rdlvl_pat_r_reg (.C(CLK), .CE(1'b1), .D(first_rdlvl_pat_r_i_1_n_0), .Q(first_rdlvl_pat_r), .R(1'b0)); LUT6 #( .INIT(64'hFEFEFEFEFEFCFEFF)) first_wrcal_pat_r_i_1 (.I0(first_wrcal_pat_r), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(wrcal_resume_w), .I3(Q[1]), .I4(Q[0]), .I5(first_wrcal_pat_r_i_2_n_0), .O(first_wrcal_pat_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair494" *) LUT5 #( .INIT(32'hFFFFFEFF)) first_wrcal_pat_r_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[5]), .I3(Q[4]), .I4(Q[3]), .O(first_wrcal_pat_r_i_2_n_0)); FDRE first_wrcal_pat_r_reg (.C(CLK), .CE(1'b1), .D(first_wrcal_pat_r_i_1_n_0), .Q(first_wrcal_pat_r), .R(1'b0)); LUT6 #( .INIT(64'h0404550404040404)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ), .I3(reg_ctrl_cnt_r), .I4(reg_ctrl_cnt_r_reg__0[3]), .I5(reg_ctrl_cnt_r_reg__0[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F44FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\complex_address_reg_n_0_[0] ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 )); LUT6 #( .INIT(64'h5515FFFF55155515)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 (.I0(Q[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 )); LUT6 #( .INIT(64'h000000000000005D)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(complex_row_cnt_ocal_reg__0[0]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFF888)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I2(\complex_address_reg_n_0_[0] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I4(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0D0FF)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 )); LUT2 #( .INIT(4'h1)) \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair583" *) LUT2 #( .INIT(4'hE)) \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 )); LUT6 #( .INIT(64'h0010009000000010)) \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 (.I0(Q[0]), .I1(Q[1]), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 )); LUT6 #( .INIT(64'h0000554000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I1(cnt_init_mr_r[0]), .I2(cnt_init_mr_r[1]), .I3(dqs_found_done_r_reg_0), .I4(Q[5]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFDFFFD7DFFEFF)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2 (.I0(Q[0]), .I1(Q[3]), .I2(Q[4]), .I3(Q[1]), .I4(\init_state_r_reg_n_0_[3] ), .I5(Q[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair522" *) LUT5 #( .INIT(32'h00000010)) \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4 (.I0(Q[2]), .I1(Q[4]), .I2(Q[1]), .I3(Q[3]), .I4(Q[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 )); LUT6 #( .INIT(64'h0004010000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[5]), .I3(Q[3]), .I4(Q[4]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 (.I0(Q[0]), .I1(Q[1]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFF80)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFEAEAEAFFFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 (.I0(prbs_rdlvl_done_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I2(\complex_address_reg_n_0_[1] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F44FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\complex_address_reg_n_0_[1] ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair543" *) LUT3 #( .INIT(8'h08)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 (.I0(reg_ctrl_cnt_r), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r_reg__0[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0D0FF)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 )); LUT6 #( .INIT(64'h000000000000005D)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(complex_row_cnt_ocal_reg__0[1]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ), .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 )); LUT2 #( .INIT(4'h1)) \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 )); LUT6 #( .INIT(64'h010101FF01010101)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 )); LUT2 #( .INIT(4'h1)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 )); LUT6 #( .INIT(64'h5FF55FF50F3F0F30)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 (.I0(\gen_rnk[0].mr1_r_reg[0]_196 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000022202220222)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ), .I1(prbs_rdlvl_done_reg), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I3(\complex_address_reg_n_0_[2] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F44FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\complex_address_reg_n_0_[2] ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFF8080808080)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 (.I0(dqs_found_done_r_reg), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg_rep), .I3(cnt_init_mr_r[0]), .I4(\gen_rnk[0].mr1_r_reg[0]_196 ), .I5(cnt_init_mr_r[1]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair586" *) LUT3 #( .INIT(8'hEF)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 (.I0(reg_ctrl_cnt_r_reg__0[3]), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r_reg__0[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0D0FF)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 )); LUT6 #( .INIT(64'h000000000000005D)) \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(complex_row_cnt_ocal_reg__0[2]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 )); LUT6 #( .INIT(64'h000000000000AAAB)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 )); LUT5 #( .INIT(32'h0047FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I2(\complex_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I4(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000D000D0D0)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4 (.I0(complex_row_cnt_ocal_reg__0[3]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000AAA222A2)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\complex_address_reg_n_0_[3] ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000FFEFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[5]), .I2(Q[4]), .I3(Q[3]), .I4(Q[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 )); LUT2 #( .INIT(4'hE)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ), .I1(burst_addr_r_reg_0), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF4044)) \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 )); LUT6 #( .INIT(64'hABABABABABAAABAB)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FEEEFEFE)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FBFB00F3)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0014551455140014)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I1(\complex_address_reg_n_0_[4] ), .I2(\complex_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 )); LUT3 #( .INIT(8'h82)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 )); LUT6 #( .INIT(64'hBEFFBEAAAAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6 (.I0(prbs_rdlvl_done_reg), .I1(\complex_address_reg_n_0_[3] ), .I2(\complex_address_reg_n_0_[4] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 )); LUT3 #( .INIT(8'h02)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7 (.I0(complex_row_cnt_ocal_reg__0[4]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair554" *) LUT2 #( .INIT(4'h6)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 )); LUT5 #( .INIT(32'h00000100)) \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9 (.I0(init_state_r1[5]), .I1(init_state_r1[4]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ), .I3(init_state_r1[3]), .I4(init_state_r1[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 )); LUT6 #( .INIT(64'h0004000400045555)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFEEEF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I2(read_calib_reg_0), .I3(read_calib_i_2_n_0), .I4(\calib_cmd[2]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair502" *) LUT4 #( .INIT(16'h802A)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 )); LUT2 #( .INIT(4'hE)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 )); LUT6 #( .INIT(64'hBEFFBEAAAAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13 (.I0(prbs_rdlvl_done_reg), .I1(\complex_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4500FFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FEEEFEFE)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair546" *) LUT4 #( .INIT(16'h00BF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I3(Q[5]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 )); LUT2 #( .INIT(4'hB)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 (.I0(Q[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000FFFFEAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 (.I0(cnt_init_mr_r[1]), .I1(prbs_rdlvl_done_reg), .I2(rdlvl_stg1_done_int_reg), .I3(dqs_found_done_r_reg), .I4(cnt_init_mr_r[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 )); LUT3 #( .INIT(8'h6A)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 )); LUT6 #( .INIT(64'hFF020202FFFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8 (.I0(complex_row_cnt_ocal_reg__0[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 )); LUT6 #( .INIT(64'h5555154000001540)) \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I1(\complex_address_reg_n_0_[4] ), .I2(\complex_address_reg_n_0_[3] ), .I3(\complex_address_reg_n_0_[5] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 )); LUT5 #( .INIT(32'h888F8888)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 (.I0(\gen_rnk[0].mr1_r_reg[0]_196 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair502" *) LUT5 #( .INIT(32'h80002AAA)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFF10FF10FF10FF)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(complex_row_cnt_ocal_reg__0[6]), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 )); LUT6 #( .INIT(64'h7447474747474747)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I2(\complex_address_reg_n_0_[6] ), .I3(\complex_address_reg_n_0_[5] ), .I4(\complex_address_reg_n_0_[4] ), .I5(\complex_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair583" *) LUT3 #( .INIT(8'h01)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000AA2A222A)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair585" *) LUT3 #( .INIT(8'h4F)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 (.I0(Q[5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 )); LUT6 #( .INIT(64'h10FF10FF10FFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ), .I3(prbs_rdlvl_done_reg), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 )); LUT6 #( .INIT(64'h5555FFFFFFEF5555)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I1(dqs_found_done_r_reg_0), .I2(cnt_init_mr_r[1]), .I3(cnt_init_mr_r[0]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0FFD0)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair523" *) LUT4 #( .INIT(16'h6AAA)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair528" *) LUT4 #( .INIT(16'h9555)) \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9 (.I0(\complex_address_reg_n_0_[6] ), .I1(\complex_address_reg_n_0_[5] ), .I2(\complex_address_reg_n_0_[4] ), .I3(\complex_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 )); LUT6 #( .INIT(64'hAA20AAAAAA20AA20)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair528" *) LUT5 #( .INIT(32'h95555555)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 (.I0(\complex_address_reg_n_0_[7] ), .I1(\complex_address_reg_n_0_[6] ), .I2(\complex_address_reg_n_0_[3] ), .I3(\complex_address_reg_n_0_[4] ), .I4(\complex_address_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD0D0FFD0)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00100000)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[5]), .I2(Q[4]), .I3(Q[3]), .I4(Q[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 )); LUT4 #( .INIT(16'hFBAA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(complex_row_cnt_ocal_reg__0[7]), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 )); LUT4 #( .INIT(16'h5101)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 )); LUT6 #( .INIT(64'h5554555555555555)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I3(rdlvl_stg1_done_int_reg), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair513" *) LUT4 #( .INIT(16'h4000)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17 (.I0(init_state_r1[0]), .I1(init_state_r1[3]), .I2(init_state_r1[4]), .I3(init_state_r1[5]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18 (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair546" *) LUT4 #( .INIT(16'h5540)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ), .I3(Q[5]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 )); LUT6 #( .INIT(64'h0020000000000070)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[1]), .I3(Q[3]), .I4(Q[0]), .I5(Q[4]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 )); LUT6 #( .INIT(64'h0040444055555555)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 (.I0(prbs_rdlvl_done_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000BBBAFFBA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6EEF)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 (.I0(Q[0]), .I1(Q[3]), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[4]), .I5(Q[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 )); LUT6 #( .INIT(64'hFF54000000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 (.I0(complex_row0_rd_done), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair523" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair501" *) LUT5 #( .INIT(32'hAAA8AAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I1(init_state_r1[1]), .I2(init_state_r1[2]), .I3(init_state_r1[6]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF111F0000)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 )); LUT6 #( .INIT(64'h800000007FFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 )); LUT6 #( .INIT(64'h9555555555555555)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 (.I0(\complex_address_reg_n_0_[8] ), .I1(\complex_address_reg_n_0_[7] ), .I2(\complex_address_reg_n_0_[5] ), .I3(\complex_address_reg_n_0_[4] ), .I4(\complex_address_reg_n_0_[3] ), .I5(\complex_address_reg_n_0_[6] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAABAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ), .I2(cnt_init_mr_r[0]), .I3(cnt_init_mr_r[1]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ), .I5(dqs_found_done_r_reg_0), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0404040455045555)) \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5 (.I0(prbs_rdlvl_done_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF1F110000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ), .I4(prbs_rdlvl_done_reg), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair501" *) LUT3 #( .INIT(8'hDF)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 (.I0(init_state_r1[2]), .I1(init_state_r1[6]), .I2(init_state_r1[1]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 )); LUT2 #( .INIT(4'hB)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 (.I0(\complex_address_reg_n_0_[4] ), .I1(\complex_address_reg_n_0_[3] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 )); LUT2 #( .INIT(4'h2)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 )); LUT6 #( .INIT(64'hBBBBBBBBBBBBBBFB)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 (.I0(first_wrcal_pat_r_i_2_n_0), .I1(Q[0]), .I2(wrcal_wr_cnt_reg__0[2]), .I3(wrcal_wr_cnt_reg__0[1]), .I4(wrcal_wr_cnt_reg__0[0]), .I5(wrcal_wr_cnt_reg__0[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF04000000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[3]), .I2(Q[5]), .I3(Q[4]), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I5(\calib_cmd[2]_i_4_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAEEEFAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ), .I1(complex_row0_rd_done), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ), .I3(\one_rank.stg1_wr_done_reg_0 ), .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I5(\complex_row_cnt_ocal[7]_i_7_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 )); LUT6 #( .INIT(64'h2000000000000000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ), .I1(\complex_num_writes[4]_i_12_n_0 ), .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair561" *) LUT3 #( .INIT(8'h02)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19 (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 )); LUT2 #( .INIT(4'h8)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair558" *) LUT2 #( .INIT(4'h6)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ), .I1(init_state_r1[5]), .I2(init_state_r1[4]), .I3(init_state_r1[0]), .I4(init_state_r1[3]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 (.I0(\complex_address_reg_n_0_[9] ), .I1(\complex_address_reg_n_0_[8] ), .I2(\complex_address_reg_n_0_[6] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ), .I4(\complex_address_reg_n_0_[5] ), .I5(\complex_address_reg_n_0_[7] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAFFABABAB)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ), .I5(prbs_rdlvl_done_reg), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 )); LUT4 #( .INIT(16'h00FD)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 (.I0(init_state_r1[3]), .I1(wrlvl_odt_ctl_i_3_n_0), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 )); LUT6 #( .INIT(64'h00000300AAAAAAAA)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ), .I1(oclk_wr_cnt_reg__0[3]), .I2(oclk_wr_cnt_reg__0[1]), .I3(oclk_wr_cnt_reg__0[2]), .I4(oclk_wr_cnt_reg__0[0]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 )); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ), .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .R(1'b0)); LUT6 #( .INIT(64'h888888888888888A)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ), .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ), .I3(Q[4]), .I4(Q[3]), .I5(Q[0]), .O(bank_w[0])); LUT6 #( .INIT(64'h0D0F0F0F0F0F040F)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .I3(\wrcal_reads[7]_i_5_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 )); LUT6 #( .INIT(64'h2000000028000000)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(Q[0]), .I5(Q[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFF00FFFF00F9FF)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4 (.I0(cnt_init_mr_r[0]), .I1(cnt_init_mr_r[1]), .I2(dqs_found_done_r_reg_0), .I3(Q[1]), .I4(\init_state_r_reg_n_0_[3] ), .I5(Q[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 )); LUT6 #( .INIT(64'h3030303034303030)) \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5 (.I0(reg_ctrl_cnt_r_reg__0[0]), .I1(Q[3]), .I2(Q[4]), .I3(reg_ctrl_cnt_r_reg__0[2]), .I4(reg_ctrl_cnt_r_reg__0[1]), .I5(reg_ctrl_cnt_r_reg__0[3]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair498" *) LUT5 #( .INIT(32'h00010000)) \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(Q[5]), .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ), .I3(Q[3]), .I4(Q[1]), .O(bank_w[1])); LUT6 #( .INIT(64'hAA55FFFFFFFFFF54)) \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 (.I0(\init_state_r_reg_n_0_[3] ), .I1(dqs_found_done_r_reg_0), .I2(cnt_init_mr_r[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[0]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair543" *) LUT4 #( .INIT(16'h4000)) \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[3]), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r), .I3(reg_ctrl_cnt_r_reg__0[2]), .O(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 )); FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (.C(CLK), .CE(1'b1), .D(bank_w[0]), .Q(phy_bank[9]), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] (.C(CLK), .CE(1'b1), .D(bank_w[1]), .Q(phy_bank[10]), .R(1'b0)); FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ), .Q(phy_bank[11]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair596" *) LUT2 #( .INIT(4'hE)) \gen_reset_obuf.u_reset_obuf_i_1 (.I0(init_calib_complete_reg_rep__14), .I1(phy_reset_n), .O(mux_reset_n)); FDRE \gen_rnk[0].mr1_r_reg[0][1] (.C(CLK), .CE(1'b1), .D(1'b1), .Q(\gen_rnk[0].mr1_r_reg[0]_196 ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE init_calib_complete_reg (.C(CLK), .CE(1'b1), .D(init_complete_r2), .Q(calib_complete), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE init_complete_r1_reg (.C(CLK), .CE(1'b1), .D(init_complete_r1_reg_0), .Q(init_complete_r1), .R(rstdiv0_sync_r1_reg_rep__11)); (* KEEP = "yes" *) FDRE init_complete_r1_timing_reg (.C(CLK), .CE(1'b1), .D(init_complete_r_timing), .Q(init_complete_r1_timing), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE init_complete_r2_reg (.C(CLK), .CE(1'b1), .D(init_complete_r1), .Q(init_complete_r2), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE init_complete_r_reg (.C(CLK), .CE(1'b1), .D(\init_state_r_reg[6]_0 ), .Q(init_complete_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); (* KEEP = "yes" *) FDRE init_complete_r_timing_reg (.C(CLK), .CE(1'b1), .D(\init_state_r_reg[6]_1 ), .Q(init_complete_r_timing), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r1_reg[0] (.C(CLK), .CE(1'b1), .D(Q[0]), .Q(init_state_r1[0]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \init_state_r1_reg[1] (.C(CLK), .CE(1'b1), .D(Q[1]), .Q(init_state_r1[1]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \init_state_r1_reg[2] (.C(CLK), .CE(1'b1), .D(Q[2]), .Q(init_state_r1[2]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \init_state_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\init_state_r_reg_n_0_[3] ), .Q(init_state_r1[3]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \init_state_r1_reg[4] (.C(CLK), .CE(1'b1), .D(Q[3]), .Q(init_state_r1[4]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \init_state_r1_reg[5] (.C(CLK), .CE(1'b1), .D(Q[4]), .Q(init_state_r1[5]), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \init_state_r1_reg[6] (.C(CLK), .CE(1'b1), .D(Q[5]), .Q(init_state_r1[6]), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'hAAAAAAAAEEEFFFFF)) \init_state_r[0]_i_1 (.I0(\init_state_r[0]_i_2_n_0 ), .I1(\init_state_r[0]_i_3_n_0 ), .I2(oclk_calib_resume_level_reg_0), .I3(\init_state_r[0]_i_5_n_0 ), .I4(\init_state_r[0]_i_6_n_0 ), .I5(\init_state_r[0]_i_7_n_0 ), .O(\init_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFF000000FFFF1103)) \init_state_r[0]_i_10 (.I0(\init_state_r[0]_i_26_n_0 ), .I1(prech_pending_r_reg_0), .I2(\init_state_r[0]_i_27_n_0 ), .I3(Q[0]), .I4(Q[1]), .I5(prbs_rdlvl_done_pulse0), .O(\init_state_r[0]_i_10_n_0 )); LUT6 #( .INIT(64'hEFEFEFEFFFEFEFEF)) \init_state_r[0]_i_11 (.I0(\init_state_r[0]_i_28_n_0 ), .I1(\init_state_r[0]_i_29_n_0 ), .I2(Q[3]), .I3(\init_state_r[0]_i_30_n_0 ), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(\init_state_r[0]_i_31_n_0 ), .O(\init_state_r[0]_i_11_n_0 )); LUT6 #( .INIT(64'hDDDFDDDDDDDDDDDD)) \init_state_r[0]_i_13 (.I0(Q[3]), .I1(\init_state_r_reg[5]_0 ), .I2(\init_state_r[4]_i_5_n_0 ), .I3(Q[0]), .I4(cnt_cmd_done_r), .I5(\init_state_r[0]_i_33_n_0 ), .O(\init_state_r[0]_i_13_n_0 )); LUT5 #( .INIT(32'hAAAABBAB)) \init_state_r[0]_i_14 (.I0(Q[1]), .I1(\init_state_r[0]_i_34_n_0 ), .I2(rdlvl_stg1_done_int_reg), .I3(rdlvl_stg1_done_r1), .I4(rdlvl_stg1_rank_done), .O(\init_state_r[0]_i_14_n_0 )); LUT6 #( .INIT(64'h0000FF00FF00FE00)) \init_state_r[0]_i_15 (.I0(prech_pending_r_reg_0), .I1(pi_dqs_found_rank_done), .I2(dqs_found_done_r_reg), .I3(Q[1]), .I4(cnt_cmd_done_r), .I5(Q[0]), .O(\init_state_r[0]_i_15_n_0 )); LUT6 #( .INIT(64'h0000000000F0FEFE)) \init_state_r[0]_i_16 (.I0(prbs_rdlvl_done_reg_rep_2), .I1(wrlvl_final_mux_reg), .I2(cnt_init_af_done_r), .I3(mem_init_done_r), .I4(oclkdelay_calib_done_r_reg_5), .I5(wrlvl_byte_redo_reg_0), .O(\init_state_r[0]_i_16_n_0 )); LUT6 #( .INIT(64'h1505155515001550)) \init_state_r[0]_i_17 (.I0(oclk_calib_resume_level_reg_0), .I1(cnt_cmd_done_r), .I2(Q[0]), .I3(Q[1]), .I4(cnt_txpr_done_r), .I5(delay_done_r4_reg), .O(\init_state_r[0]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDF005F00)) \init_state_r[0]_i_18 (.I0(Q[0]), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(\init_state_r_reg[1]_0 ), .I4(wrlvl_done_r1), .I5(\init_state_r[0]_i_40_n_0 ), .O(\init_state_r[0]_i_18_n_0 )); LUT6 #( .INIT(64'hAEBBBFBBAABBBFBB)) \init_state_r[0]_i_19 (.I0(\init_state_r[0]_i_41_n_0 ), .I1(Q[1]), .I2(reset_rd_addr_r1), .I3(Q[0]), .I4(cnt_cmd_done_r), .I5(rdlvl_stg1_done_r1), .O(\init_state_r[0]_i_19_n_0 )); LUT6 #( .INIT(64'hABABABABAAABAAAA)) \init_state_r[0]_i_2 (.I0(\init_state_r[0]_i_8_n_0 ), .I1(\init_state_r[5]_i_26_n_0 ), .I2(\init_state_r[0]_i_9_n_0 ), .I3(\init_state_r[0]_i_10_n_0 ), .I4(\init_state_r_reg[1]_0 ), .I5(\init_state_r[0]_i_11_n_0 ), .O(\init_state_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair486" *) LUT5 #( .INIT(32'hFFFDDDDD)) \init_state_r[0]_i_20 (.I0(Q[1]), .I1(Q[0]), .I2(rdlvl_stg1_done_r1), .I3(complex_sample_cnt_inc_i_2_n_0), .I4(\init_state_r[5]_i_32_n_0 ), .O(\init_state_r[0]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFF133)) \init_state_r[0]_i_21 (.I0(\init_state_r[6]_i_21_n_0 ), .I1(write_request_r_reg), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\init_state_r[0]_i_21_n_0 )); LUT6 #( .INIT(64'hFFBFAFBFAAAAAAAA)) \init_state_r[0]_i_22 (.I0(oclk_calib_resume_level_reg_0), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(burst_addr_r_reg_0), .I5(\init_state_r[0]_i_42_n_0 ), .O(\init_state_r[0]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEAEAEEEA)) \init_state_r[0]_i_23 (.I0(\init_state_r[0]_i_43_n_0 ), .I1(\init_state_r_reg[1]_0 ), .I2(\init_state_r_reg[1]_1 ), .I3(cnt_cmd_done_r), .I4(Q[0]), .I5(\init_state_r[4]_i_28_n_0 ), .O(\init_state_r[0]_i_23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair577" *) LUT3 #( .INIT(8'h10)) \init_state_r[0]_i_24 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .O(\init_state_r[0]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair540" *) LUT4 #( .INIT(16'h0010)) \init_state_r[0]_i_25 (.I0(\wrcal_reads_reg_n_0_[4] ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(\wrcal_reads_reg_n_0_[0] ), .I3(\init_state_r[0]_i_45_n_0 ), .O(\init_state_r[0]_i_25_n_0 )); LUT6 #( .INIT(64'h0888888888888888)) \init_state_r[0]_i_26 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(Q[0]), .I2(complex_wait_cnt_reg__0[0]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[2]), .I5(complex_wait_cnt_reg__0[3]), .O(\init_state_r[0]_i_26_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \init_state_r[0]_i_27 (.I0(complex_num_reads_dec_reg__0[1]), .I1(complex_num_reads_dec_reg__0[0]), .I2(prbs_rdlvl_done_reg_rep), .I3(complex_row0_rd_done), .I4(complex_num_reads_dec_reg__0[3]), .I5(complex_num_reads_dec_reg__0[2]), .O(\init_state_r[0]_i_27_n_0 )); LUT6 #( .INIT(64'h0101010101014501)) \init_state_r[0]_i_28 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(Q[1]), .I2(\init_state_r[0]_i_46_n_0 ), .I3(prbs_rdlvl_done_reg_rep_0), .I4(Q[0]), .I5(complex_oclk_calib_resume), .O(\init_state_r[0]_i_28_n_0 )); LUT6 #( .INIT(64'h0000000000F0EFE0)) \init_state_r[0]_i_29 (.I0(\init_state_r[6]_i_16_n_0 ), .I1(oclkdelay_center_calib_start_r_reg_0), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(Q[0]), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[0]_i_29_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF000E0000)) \init_state_r[0]_i_3 (.I0(\init_state_r[2]_i_12_n_0 ), .I1(wrcal_sanity_chk_done_reg), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\init_state_r[0]_i_13_n_0 ), .O(\init_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDFDFDFDD)) \init_state_r[0]_i_30 (.I0(prbs_gen_oclk_clk_en_i_8_n_0), .I1(\init_state_r[3]_i_23_n_0 ), .I2(complex_oclkdelay_calib_start_r2), .I3(prbs_rdlvl_done_reg), .I4(prbs_last_byte_done_r), .I5(\init_state_r[4]_i_39_n_0 ), .O(\init_state_r[0]_i_30_n_0 )); LUT6 #( .INIT(64'h0004000400000004)) \init_state_r[0]_i_31 (.I0(oclkdelay_center_calib_start_r_reg), .I1(prbs_gen_oclk_clk_en_i_8_n_0), .I2(prech_pending_r_reg_0), .I3(prbs_rdlvl_start_i_2_n_0), .I4(complex_row1_wr_done), .I5(\one_rank.stg1_wr_done_reg_0 ), .O(\init_state_r[0]_i_31_n_0 )); (* SOFT_HLUTNM = "soft_lutpair562" *) LUT4 #( .INIT(16'hFFEF)) \init_state_r[0]_i_33 (.I0(reg_ctrl_cnt_r_reg__0[1]), .I1(reg_ctrl_cnt_r_reg__0[0]), .I2(reg_ctrl_cnt_r_reg__0[3]), .I3(reg_ctrl_cnt_r_reg__0[2]), .O(\init_state_r[0]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair544" *) LUT4 #( .INIT(16'hFFAE)) \init_state_r[0]_i_34 (.I0(Q[0]), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_rdlvl_done_r1), .I3(prech_pending_r_reg_0), .O(\init_state_r[0]_i_34_n_0 )); LUT2 #( .INIT(4'hE)) \init_state_r[0]_i_4 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .O(oclk_calib_resume_level_reg_0)); LUT6 #( .INIT(64'hBAFFAAAABFFFAAAA)) \init_state_r[0]_i_40 (.I0(Q[3]), .I1(wrlvl_rank_done_r7), .I2(Q[1]), .I3(Q[0]), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(cnt_dllk_zqinit_done_r), .O(\init_state_r[0]_i_40_n_0 )); LUT6 #( .INIT(64'h0000400044444444)) \init_state_r[0]_i_41 (.I0(Q[1]), .I1(pi_calib_done), .I2(\init_state_r[0]_i_51_n_0 ), .I3(wrcal_done_reg_10), .I4(rdlvl_stg1_done_int_reg_4), .I5(dqs_found_done_r_reg), .O(\init_state_r[0]_i_41_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAABABB)) \init_state_r[0]_i_42 (.I0(\init_state_r[1]_i_20_n_0 ), .I1(Q[0]), .I2(wrcal_prech_req), .I3(cnt_cmd_done_r), .I4(wrcal_done_reg_10), .I5(prech_pending_r_reg_0), .O(\init_state_r[0]_i_42_n_0 )); LUT6 #( .INIT(64'h000000000000F0EF)) \init_state_r[0]_i_43 (.I0(\init_state_r[2]_i_36_n_0 ), .I1(cnt_cmd_done_r_reg_1), .I2(Q[1]), .I3(Q[0]), .I4(\init_state_r[4]_i_5_n_0 ), .I5(\init_state_r[5]_i_57_n_0 ), .O(\init_state_r[0]_i_43_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \init_state_r[0]_i_45 (.I0(\wrcal_reads_reg_n_0_[3] ), .I1(\wrcal_reads_reg_n_0_[1] ), .I2(\wrcal_reads_reg_n_0_[7] ), .I3(Q[0]), .I4(\wrcal_reads_reg_n_0_[2] ), .I5(\wrcal_reads_reg_n_0_[5] ), .O(\init_state_r[0]_i_45_n_0 )); LUT6 #( .INIT(64'h4500FFFF4545FFFF)) \init_state_r[0]_i_46 (.I0(prech_pending_r_reg_0), .I1(complex_oclkdelay_calib_done_r1), .I2(prbs_rdlvl_done_reg), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(Q[0]), .I5(complex_sample_cnt_inc_i_2_n_0), .O(\init_state_r[0]_i_46_n_0 )); LUT6 #( .INIT(64'h00000000FFFF1000)) \init_state_r[0]_i_5 (.I0(num_reads[1]), .I1(num_reads[2]), .I2(num_reads[0]), .I3(Q[0]), .I4(\init_state_r[0]_i_14_n_0 ), .I5(\init_state_r[0]_i_15_n_0 ), .O(\init_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'h0155455501550055)) \init_state_r[0]_i_50 (.I0(\init_state_r_reg[2]_0 ), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_last_byte_done_r), .I3(dqs_found_done_r_reg), .I4(rdlvl_stg1_done_int_reg), .I5(wrcal_done_reg_10), .O(\init_state_r_reg[0]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFC44)) \init_state_r[0]_i_51 (.I0(rdlvl_stg1_start_int), .I1(prbs_rdlvl_done_reg_rep), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(rdlvl_stg1_done_int_reg), .I4(rdlvl_last_byte_done), .I5(prbs_last_byte_done), .O(\init_state_r[0]_i_51_n_0 )); LUT6 #( .INIT(64'hEFAFFFBFFFFFFFFF)) \init_state_r[0]_i_6 (.I0(Q[0]), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(\init_state_r[0]_i_16_n_0 ), .I4(ddr2_pre_flag_r_reg_0), .I5(\init_state_r_reg[1]_0 ), .O(\init_state_r[0]_i_6_n_0 )); LUT6 #( .INIT(64'hABAAABABABAAABAA)) \init_state_r[0]_i_7 (.I0(\init_state_r[5]_i_2_n_0 ), .I1(\init_state_r[0]_i_17_n_0 ), .I2(\init_state_r[0]_i_18_n_0 ), .I3(\init_state_r[4]_i_5_n_0 ), .I4(\init_state_r[0]_i_19_n_0 ), .I5(\init_state_r[0]_i_20_n_0 ), .O(\init_state_r[0]_i_7_n_0 )); LUT6 #( .INIT(64'h88008A008A008A00)) \init_state_r[0]_i_8 (.I0(\init_state_r[0]_i_21_n_0 ), .I1(Q[0]), .I2(Q[2]), .I3(Q[5]), .I4(\init_state_r[5]_i_36_n_0 ), .I5(Q[1]), .O(\init_state_r[0]_i_8_n_0 )); LUT6 #( .INIT(64'h2222222200202222)) \init_state_r[0]_i_9 (.I0(\init_state_r[0]_i_22_n_0 ), .I1(\init_state_r[0]_i_23_n_0 ), .I2(wrcal_done_reg_9), .I3(Q[0]), .I4(\init_state_r[0]_i_24_n_0 ), .I5(\init_state_r[0]_i_25_n_0 ), .O(\init_state_r[0]_i_9_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAEEFE)) \init_state_r[1]_i_1 (.I0(\init_state_r[1]_i_2_n_0 ), .I1(\init_state_r[1]_i_3_n_0 ), .I2(\init_state_r_reg[1]_0 ), .I3(\init_state_r[1]_i_5_n_0 ), .I4(\init_state_r[5]_i_2_n_0 ), .I5(\init_state_r[1]_i_6_n_0 ), .O(\init_state_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair504" *) LUT5 #( .INIT(32'hFFFBAAAA)) \init_state_r[1]_i_10 (.I0(\init_state_r[0]_i_14_n_0 ), .I1(num_reads[0]), .I2(num_reads[2]), .I3(num_reads[1]), .I4(Q[0]), .O(\init_state_r[1]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair526" *) LUT5 #( .INIT(32'h22222220)) \init_state_r[1]_i_11 (.I0(Q[1]), .I1(Q[0]), .I2(dqs_found_done_r_reg), .I3(pi_dqs_found_rank_done), .I4(prech_pending_r_reg_0), .O(\init_state_r[1]_i_11_n_0 )); LUT6 #( .INIT(64'hBBBBBBFFBBFFBBFB)) \init_state_r[1]_i_12 (.I0(\init_state_r[1]_i_25_n_0 ), .I1(Q[3]), .I2(cnt_cmd_done_r), .I3(\init_state_r[4]_i_5_n_0 ), .I4(Q[0]), .I5(Q[1]), .O(\init_state_r[1]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0B0B080B)) \init_state_r[1]_i_13 (.I0(wrlvl_byte_redo_reg), .I1(mpr_rdlvl_done_r_reg_2), .I2(\init_state_r[1]_i_26_n_0 ), .I3(oclkdelay_calib_done_r_reg_2), .I4(\init_state_r[1]_i_27_n_0 ), .I5(\init_state_r[1]_i_28_n_0 ), .O(\init_state_r[1]_i_13_n_0 )); LUT6 #( .INIT(64'hFFE0FFE0FFE0FFFF)) \init_state_r[1]_i_15 (.I0(dqs_found_done_r_reg_2), .I1(prbs_last_byte_done_reg), .I2(\init_state_r[1]_i_33_n_0 ), .I3(\init_state_r[1]_i_34_n_0 ), .I4(Q[0]), .I5(\init_state_r[5]_i_32_n_0 ), .O(\init_state_r[1]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair566" *) LUT4 #( .INIT(16'h0020)) \init_state_r[1]_i_16 (.I0(Q[0]), .I1(Q[1]), .I2(cnt_dllk_zqinit_done_r), .I3(mem_init_done_r), .O(\init_state_r[1]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF7070FF70)) \init_state_r[1]_i_17 (.I0(Q[0]), .I1(wrlvl_rank_done_r7), .I2(\init_state_r[1]_i_35_n_0 ), .I3(\init_state_r_reg[1]_0 ), .I4(\init_state_r[1]_i_36_n_0 ), .I5(Q[3]), .O(\init_state_r[1]_i_17_n_0 )); LUT6 #( .INIT(64'hE0000F0FE000FFFF)) \init_state_r[1]_i_18 (.I0(cnt_init_mr_done_r), .I1(dqs_found_done_r_reg_0), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(cnt_txpr_done_r), .O(\init_state_r[1]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair533" *) LUT5 #( .INIT(32'hF2F2F2FF)) \init_state_r[1]_i_19 (.I0(cnt_cmd_done_r), .I1(wrcal_prech_req), .I2(Q[0]), .I3(prech_pending_r_reg_0), .I4(wrcal_done_reg_10), .O(\init_state_r[1]_i_19_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF0200)) \init_state_r[1]_i_2 (.I0(Q[4]), .I1(Q[5]), .I2(\init_state_r[1]_i_7_n_0 ), .I3(\init_state_r[1]_i_8_n_0 ), .I4(\init_state_r[1]_i_9_n_0 ), .I5(\init_state_r[5]_i_19_n_0 ), .O(\init_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAABAAAAAAAAAA)) \init_state_r[1]_i_20 (.I0(Q[1]), .I1(wrcal_wr_cnt_reg__0[3]), .I2(wrcal_wr_cnt_reg__0[2]), .I3(wrcal_wr_cnt_reg__0[0]), .I4(wrcal_wr_cnt_reg__0[1]), .I5(Q[0]), .O(\init_state_r[1]_i_20_n_0 )); LUT6 #( .INIT(64'hFEFEFEFEFFFEFEFE)) \init_state_r[1]_i_21 (.I0(\init_state_r[1]_i_37_n_0 ), .I1(Q[3]), .I2(mpr_rdlvl_done_r_reg_0), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\init_state_r[5]_i_57_n_0 ), .O(\init_state_r[1]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair529" *) LUT5 #( .INIT(32'hEFEEAAAA)) \init_state_r[1]_i_22 (.I0(Q[1]), .I1(prech_pending_r_reg_0), .I2(complex_oclkdelay_calib_done_r1), .I3(prbs_rdlvl_done_reg_rep), .I4(Q[0]), .O(\init_state_r[1]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFAABA)) \init_state_r[1]_i_23 (.I0(\init_state_r[1]_i_39_n_0 ), .I1(Q[0]), .I2(\init_state_r_reg[1]_0 ), .I3(\init_state_r[1]_i_40_n_0 ), .I4(\init_state_r[1]_i_41_n_0 ), .I5(\init_state_r[1]_i_42_n_0 ), .O(\init_state_r[1]_i_23_n_0 )); LUT6 #( .INIT(64'hCCCCCC88CCCCCC08)) \init_state_r[1]_i_24 (.I0(\init_state_r[5]_i_13_n_0 ), .I1(\init_state_r[1]_i_43_n_0 ), .I2(\init_state_r[0]_i_27_n_0 ), .I3(prech_pending_r_reg_0), .I4(prbs_rdlvl_done_pulse0), .I5(Q[0]), .O(\init_state_r[1]_i_24_n_0 )); LUT6 #( .INIT(64'h2820202028202820)) \init_state_r[1]_i_25 (.I0(\wrcal_reads[7]_i_5_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(wrcal_sanity_chk_done_reg_0), .I5(rdlvl_stg1_done_int_reg_2), .O(\init_state_r[1]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair493" *) LUT5 #( .INIT(32'h0020FFFF)) \init_state_r[1]_i_26 (.I0(prbs_last_byte_done_r), .I1(prbs_rdlvl_done_reg_rep), .I2(dqs_found_done_r_reg), .I3(\init_state_r_reg[2]_0 ), .I4(mem_init_done_r), .O(\init_state_r[1]_i_26_n_0 )); LUT6 #( .INIT(64'h8A8A8A88AAAAAAAA)) \init_state_r[1]_i_27 (.I0(wrlvl_final_mux_reg_0), .I1(wrlvl_done_r1), .I2(prbs_rdlvl_done_reg_rep), .I3(rdlvl_stg1_done_int_reg), .I4(prbs_last_byte_done_r), .I5(prbs_rdlvl_done_reg_rep_3), .O(\init_state_r[1]_i_27_n_0 )); LUT6 #( .INIT(64'h000000F200000000)) \init_state_r[1]_i_28 (.I0(wrcal_done_reg_10), .I1(\init_state_r[1]_i_46_n_0 ), .I2(prbs_rdlvl_done_reg_rep_1), .I3(mem_init_done_r), .I4(cnt_init_af_done_r), .I5(mpr_rdlvl_done_r_reg_1), .O(\init_state_r[1]_i_28_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000FF5D)) \init_state_r[1]_i_3 (.I0(\init_state_r[1]_i_10_n_0 ), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(\init_state_r[1]_i_11_n_0 ), .I4(oclk_calib_resume_level_reg_0), .I5(\init_state_r[1]_i_12_n_0 ), .O(\init_state_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair581" *) LUT2 #( .INIT(4'h2)) \init_state_r[1]_i_33 (.I0(pi_calib_done), .I1(Q[1]), .O(\init_state_r[1]_i_33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF10000FFF)) \init_state_r[1]_i_34 (.I0(rdlvl_stg1_done_r1), .I1(reset_rd_addr_r1), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(\init_state_r[4]_i_5_n_0 ), .O(\init_state_r[1]_i_34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair570" *) LUT3 #( .INIT(8'h08)) \init_state_r[1]_i_35 (.I0(Q[1]), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[1]_i_35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair566" *) LUT3 #( .INIT(8'h07)) \init_state_r[1]_i_36 (.I0(Q[0]), .I1(cnt_cmd_done_r), .I2(Q[1]), .O(\init_state_r[1]_i_36_n_0 )); LUT6 #( .INIT(64'h4444444044404440)) \init_state_r[1]_i_37 (.I0(Q[0]), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(\init_state_r[5]_i_49_n_0 ), .I3(Q[1]), .I4(wrcal_final_chk), .I5(wrcal_resume_r), .O(\init_state_r[1]_i_37_n_0 )); LUT6 #( .INIT(64'h1FFF0000FFFFFFFF)) \init_state_r[1]_i_39 (.I0(\one_rank.stg1_wr_done_reg_0 ), .I1(oclkdelay_center_calib_start_r_reg), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(\init_state_r[2]_i_33_n_0 ), .I4(\init_state_r[1]_i_35_n_0 ), .I5(Q[3]), .O(\init_state_r[1]_i_39_n_0 )); (* SOFT_HLUTNM = "soft_lutpair541" *) LUT2 #( .INIT(4'h2)) \init_state_r[1]_i_4 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .O(\init_state_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair551" *) LUT4 #( .INIT(16'hB0BB)) \init_state_r[1]_i_40 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg_rep), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[1]), .O(\init_state_r[1]_i_40_n_0 )); LUT6 #( .INIT(64'h1515100015155444)) \init_state_r[1]_i_41 (.I0(oclk_calib_resume_level_reg_0), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(oclkdelay_int_ref_req_reg_0), .I4(Q[0]), .I5(\init_state_r[1]_i_47_n_0 ), .O(\init_state_r[1]_i_41_n_0 )); LUT6 #( .INIT(64'h0000000088880080)) \init_state_r[1]_i_42 (.I0(Q[0]), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(\init_state_r[1]_i_48_n_0 ), .I4(prbs_rdlvl_done_pulse0), .I5(Q[1]), .O(\init_state_r[1]_i_42_n_0 )); (* SOFT_HLUTNM = "soft_lutpair570" *) LUT3 #( .INIT(8'h04)) \init_state_r[1]_i_43 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .O(\init_state_r[1]_i_43_n_0 )); LUT2 #( .INIT(4'h2)) \init_state_r[1]_i_46 (.I0(wrlvl_final_mux), .I1(wrlvl_done_r1), .O(\init_state_r[1]_i_46_n_0 )); LUT6 #( .INIT(64'h0000000000010000)) \init_state_r[1]_i_47 (.I0(wrlvl_final_mux), .I1(oclkdelay_int_ref_req_reg_0), .I2(prech_pending_r_reg_0), .I3(oclkdelay_calib_done_r_reg_2), .I4(oclkdelay_center_calib_start_r_reg), .I5(\init_state_r[6]_i_16_n_0 ), .O(\init_state_r[1]_i_47_n_0 )); (* SOFT_HLUTNM = "soft_lutpair510" *) LUT5 #( .INIT(32'h0000CC40)) \init_state_r[1]_i_48 (.I0(complex_oclkdelay_calib_start_int), .I1(done_r_reg), .I2(prbs_last_byte_done_r), .I3(prbs_rdlvl_done_reg_rep), .I4(complex_oclkdelay_calib_start_r2), .O(\init_state_r[1]_i_48_n_0 )); LUT6 #( .INIT(64'hFFFF00002222F0FF)) \init_state_r[1]_i_5 (.I0(\init_state_r[1]_i_13_n_0 ), .I1(oclkdelay_calib_done_r_reg_4), .I2(ddr2_pre_flag_r_reg_0), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(Q[0]), .O(\init_state_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h0000A2AA0000A0A8)) \init_state_r[1]_i_6 (.I0(\init_state_r[1]_i_15_n_0 ), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(\init_state_r[1]_i_16_n_0 ), .I4(\init_state_r[1]_i_17_n_0 ), .I5(\init_state_r[1]_i_18_n_0 ), .O(\init_state_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000BABAFFBA)) \init_state_r[1]_i_7 (.I0(oclk_calib_resume_level_reg_0), .I1(prbs_rdlvl_start_i_2_n_0), .I2(burst_addr_r_reg_0), .I3(\init_state_r[1]_i_19_n_0 ), .I4(\init_state_r[1]_i_20_n_0 ), .I5(\init_state_r[1]_i_21_n_0 ), .O(\init_state_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF00FD)) \init_state_r[1]_i_8 (.I0(\init_state_r[5]_i_42_n_0 ), .I1(\init_state_r[1]_i_22_n_0 ), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(\init_state_r[4]_i_5_n_0 ), .I4(\init_state_r[1]_i_23_n_0 ), .I5(\init_state_r[1]_i_24_n_0 ), .O(\init_state_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'hFF80FFFF80808080)) \init_state_r[1]_i_9 (.I0(Q[5]), .I1(Q[2]), .I2(Q[1]), .I3(prech_pending_r_reg_0), .I4(oclkdelay_calib_done_r_reg_2), .I5(\init_state_r[6]_i_11_n_0 ), .O(\init_state_r[1]_i_9_n_0 )); LUT6 #( .INIT(64'hAEAEAEAAAEAEAEAE)) \init_state_r[2]_i_1 (.I0(\init_state_r[2]_i_2_n_0 ), .I1(\init_state_r[2]_i_3_n_0 ), .I2(\init_state_r[5]_i_2_n_0 ), .I3(\init_state_r[2]_i_4_n_0 ), .I4(\init_state_r[2]_i_5_n_0 ), .I5(\init_state_r[2]_i_6_n_0 ), .O(\init_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAA0002)) \init_state_r[2]_i_10 (.I0(\init_state_r[2]_i_25_n_0 ), .I1(dqs_found_done_r_reg_0), .I2(cnt_init_mr_done_r), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\init_state_r[2]_i_26_n_0 ), .O(\init_state_r[2]_i_10_n_0 )); LUT6 #( .INIT(64'hF2FF000000000000)) \init_state_r[2]_i_11 (.I0(pi_calib_done), .I1(wrcal_done_reg_11), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(\init_state_r[2]_i_27_n_0 ), .I5(\init_state_r[0]_i_20_n_0 ), .O(\init_state_r[2]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair533" *) LUT2 #( .INIT(4'h7)) \init_state_r[2]_i_12 (.I0(Q[0]), .I1(cnt_cmd_done_r), .O(\init_state_r[2]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair497" *) LUT5 #( .INIT(32'h45454500)) \init_state_r[2]_i_14 (.I0(\init_state_r_reg[2]_0 ), .I1(mem_init_done_r), .I2(cnt_init_af_done_r), .I3(prbs_rdlvl_done_reg_rep_1), .I4(\init_state_r[4]_i_26_n_0 ), .O(\init_state_r[2]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair506" *) LUT2 #( .INIT(4'h7)) \init_state_r[2]_i_16 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .O(\init_state_r[2]_i_16_n_0 )); LUT6 #( .INIT(64'hAAAABFFFAAAABBBB)) \init_state_r[2]_i_17 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[2]), .I5(\init_state_r[5]_i_56_n_0 ), .O(\init_state_r[2]_i_17_n_0 )); LUT6 #( .INIT(64'h80AA808080AA80AA)) \init_state_r[2]_i_18 (.I0(Q[2]), .I1(prbs_rdlvl_done_pulse0), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(\init_state_r[6]_i_22_n_0 ), .I4(\init_state_r[2]_i_32_n_0 ), .I5(\init_state_r[2]_i_33_n_0 ), .O(\init_state_r[2]_i_18_n_0 )); LUT6 #( .INIT(64'hF200FFFFF200F200)) \init_state_r[2]_i_2 (.I0(complex_pi_incdec_done), .I1(prbs_rdlvl_start_i_2_n_0), .I2(\init_state_r[2]_i_7_n_0 ), .I3(Q[5]), .I4(\init_state_r[2]_i_8_n_0 ), .I5(\init_state_r[2]_i_9_n_0 ), .O(\init_state_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'h10111010FFFFFFFF)) \init_state_r[2]_i_20 (.I0(\init_state_r[2]_i_16_n_0 ), .I1(Q[2]), .I2(complex_oclkdelay_calib_start_int_reg_0), .I3(prbs_rdlvl_done_pulse0), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(Q[3]), .O(\init_state_r[2]_i_20_n_0 )); LUT6 #( .INIT(64'hF000F2F200000000)) \init_state_r[2]_i_21 (.I0(pi_phase_locked_all_r3), .I1(pi_phase_locked_all_r4), .I2(Q[0]), .I3(\init_state_r[2]_i_34_n_0 ), .I4(\init_state_r_reg_n_0_[3] ), .I5(\init_state_r[2]_i_35_n_0 ), .O(\init_state_r[2]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFF010FFFFFFFFF)) \init_state_r[2]_i_22 (.I0(\init_state_r_reg_n_0_[3] ), .I1(burst_addr_r_reg_0), .I2(Q[2]), .I3(Q[1]), .I4(Q[5]), .I5(Q[4]), .O(\init_state_r[2]_i_22_n_0 )); LUT6 #( .INIT(64'hFFBFBBBBAAAAAAAA)) \init_state_r[2]_i_24 (.I0(Q[0]), .I1(\init_state_r_reg_n_0_[3] ), .I2(\init_state_r[2]_i_36_n_0 ), .I3(cnt_cmd_done_r_reg_1), .I4(Q[1]), .I5(Q[2]), .O(\init_state_r[2]_i_24_n_0 )); LUT6 #( .INIT(64'hFF0F4F4F0F0F0F0F)) \init_state_r[2]_i_25 (.I0(mem_init_done_r), .I1(cnt_dllk_zqinit_done_r), .I2(Q[2]), .I3(wrlvl_rank_done_r7), .I4(Q[1]), .I5(Q[0]), .O(\init_state_r[2]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair548" *) LUT3 #( .INIT(8'h7F)) \init_state_r[2]_i_26 (.I0(cnt_cmd_done_r), .I1(Q[0]), .I2(Q[1]), .O(\init_state_r[2]_i_26_n_0 )); LUT6 #( .INIT(64'hEC00FFF0ECF0FFF0)) \init_state_r[2]_i_27 (.I0(reset_rd_addr_r1), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(complex_sample_cnt_inc_i_2_n_0), .O(\init_state_r[2]_i_27_n_0 )); LUT6 #( .INIT(64'hF0FFF1F1F3F3F3F3)) \init_state_r[2]_i_3 (.I0(wrlvl_done_r1), .I1(\init_state_r[2]_i_10_n_0 ), .I2(Q[3]), .I3(\init_state_r[2]_i_11_n_0 ), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hAB00AB00AB00ABFF)) \init_state_r[2]_i_30 (.I0(\init_state_r[2]_i_37_n_0 ), .I1(wrlvl_done_r1), .I2(wrlvl_byte_redo), .I3(mem_init_done_r), .I4(wrcal_done_reg_10), .I5(cnt_init_af_done_r), .O(\init_state_r_reg[2]_1 )); LUT6 #( .INIT(64'h8000800080000000)) \init_state_r[2]_i_32 (.I0(complex_wait_cnt_reg__0[3]), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[1]), .I3(complex_wait_cnt_reg__0[0]), .I4(oclkdelay_center_calib_start_r_reg), .I5(\one_rank.stg1_wr_done_reg_0 ), .O(\init_state_r[2]_i_32_n_0 )); (* SOFT_HLUTNM = "soft_lutpair526" *) LUT2 #( .INIT(4'h2)) \init_state_r[2]_i_33 (.I0(Q[0]), .I1(prech_pending_r_reg_0), .O(\init_state_r[2]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair547" *) LUT4 #( .INIT(16'h0010)) \init_state_r[2]_i_34 (.I0(oclk_wr_cnt_reg__0[3]), .I1(oclk_wr_cnt_reg__0[1]), .I2(oclk_wr_cnt_reg__0[0]), .I3(oclk_wr_cnt_reg__0[2]), .O(\init_state_r[2]_i_34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair551" *) LUT2 #( .INIT(4'h8)) \init_state_r[2]_i_35 (.I0(Q[2]), .I1(Q[1]), .O(\init_state_r[2]_i_35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair534" *) LUT2 #( .INIT(4'hE)) \init_state_r[2]_i_36 (.I0(prech_pending_r_reg_0), .I1(oclkdelay_calib_done_r_reg_2), .O(\init_state_r[2]_i_36_n_0 )); (* SOFT_HLUTNM = "soft_lutpair574" *) LUT3 #( .INIT(8'hDF)) \init_state_r[2]_i_37 (.I0(prbs_last_byte_done_r), .I1(prbs_rdlvl_done_reg_rep), .I2(dqs_found_done_r_reg), .O(\init_state_r[2]_i_37_n_0 )); LUT6 #( .INIT(64'hEEFE000000000000)) \init_state_r[2]_i_4 (.I0(wrcal_sanity_chk_done_reg_0), .I1(\init_state_r[2]_i_12_n_0 ), .I2(ddr3_lm_done_r), .I3(rdlvl_stg1_done_int_reg_2), .I4(prbs_rdlvl_start_i_2_n_0), .I5(\wrcal_reads[7]_i_5_n_0 ), .O(\init_state_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'h5FF755555555D555)) \init_state_r[2]_i_5 (.I0(Q[3]), .I1(cnt_cmd_done_r), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF040F)) \init_state_r[2]_i_6 (.I0(\init_state_r[2]_i_14_n_0 ), .I1(cnt_init_af_done_r_reg_1), .I2(Q[0]), .I3(cnt_cmd_done_r), .I4(Q[2]), .I5(\init_state_r[2]_i_16_n_0 ), .O(\init_state_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'hAAAEAAAAAAAAAAAA)) \init_state_r[2]_i_7 (.I0(Q[2]), .I1(oclkdelay_calib_done_r_reg_2), .I2(prech_pending_r_reg_0), .I3(Q[1]), .I4(Q[0]), .I5(\init_state_r[6]_i_21_n_0 ), .O(\init_state_r[2]_i_7_n_0 )); LUT6 #( .INIT(64'h000E000E0000000E)) \init_state_r[2]_i_8 (.I0(\init_state_r[2]_i_17_n_0 ), .I1(\init_state_r[2]_i_18_n_0 ), .I2(\init_state_r_reg[2]_2 ), .I3(\init_state_r[2]_i_20_n_0 ), .I4(\init_state_r[5]_i_42_n_0 ), .I5(\init_state_r[5]_i_41_n_0 ), .O(\init_state_r[2]_i_8_n_0 )); LUT6 #( .INIT(64'h11010000FFFFFFFF)) \init_state_r[2]_i_9 (.I0(\init_state_r[2]_i_21_n_0 ), .I1(\init_state_r[2]_i_22_n_0 ), .I2(\wrcal_reads[7]_i_6_n_0 ), .I3(wrcal_done_reg_9), .I4(\init_state_r[2]_i_24_n_0 ), .I5(complex_oclkdelay_calib_start_int_i_2_n_0), .O(\init_state_r[2]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair484" *) LUT1 #( .INIT(2'h1)) \init_state_r[3]_i_1 (.I0(\init_state_r[3]_i_2_n_0 ), .O(\init_state_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair565" *) LUT4 #( .INIT(16'h0111)) \init_state_r[3]_i_10 (.I0(Q[1]), .I1(Q[0]), .I2(ddr2_pre_flag_r_reg_0), .I3(cnt_cmd_done_r), .O(\init_state_r[3]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair579" *) LUT2 #( .INIT(4'h2)) \init_state_r[3]_i_11 (.I0(\init_state_r_reg_n_0_[3] ), .I1(cnt_cmd_done_r), .O(\init_state_r[3]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair532" *) LUT5 #( .INIT(32'hF3FF23FF)) \init_state_r[3]_i_13 (.I0(\init_state_r_reg_n_0_[3] ), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(reset_rd_addr_r1), .O(\init_state_r[3]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair494" *) LUT5 #( .INIT(32'hFEFFFFFF)) \init_state_r[3]_i_14 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .O(\init_state_r[3]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF4440)) \init_state_r[3]_i_15 (.I0(\wrcal_reads[7]_i_5_n_0 ), .I1(Q[5]), .I2(\init_state_r[3]_i_19_n_0 ), .I3(\init_state_r[3]_i_20_n_0 ), .I4(\init_state_r[3]_i_21_n_0 ), .I5(\init_state_r[3]_i_22_n_0 ), .O(\init_state_r[3]_i_15_n_0 )); LUT6 #( .INIT(64'h0202222202022202)) \init_state_r[3]_i_16 (.I0(\init_state_r[5]_i_41_n_0 ), .I1(\init_state_r_reg[2]_2 ), .I2(\init_state_r[5]_i_53_n_0 ), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(complex_oclkdelay_calib_start_int_reg_0), .I5(prbs_rdlvl_done_pulse0), .O(\init_state_r[3]_i_16_n_0 )); LUT6 #( .INIT(64'hFFDDFFFFF0DDFFFF)) \init_state_r[3]_i_17 (.I0(\init_state_r[3]_i_23_n_0 ), .I1(prbs_rdlvl_done_pulse0), .I2(prech_pending_r_reg_0), .I3(Q[1]), .I4(Q[0]), .I5(oclkdelay_center_calib_start_r_reg), .O(\init_state_r[3]_i_17_n_0 )); LUT6 #( .INIT(64'hCFFFAFCF00FF00CF)) \init_state_r[3]_i_18 (.I0(oclkdelay_center_calib_start_r_reg_0), .I1(cnt_cmd_done_r), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(Q[0]), .I5(\init_state_r[5]_i_56_n_0 ), .O(\init_state_r[3]_i_18_n_0 )); LUT6 #( .INIT(64'h0044000000440400)) \init_state_r[3]_i_19 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(write_request_r_reg), .I5(\init_state_r[6]_i_21_n_0 ), .O(\init_state_r[3]_i_19_n_0 )); LUT6 #( .INIT(64'h00FE00FE00FE0000)) \init_state_r[3]_i_2 (.I0(\init_state_r[3]_i_3_n_0 ), .I1(\init_state_r[3]_i_4_n_0 ), .I2(\init_state_r[3]_i_5_n_0 ), .I3(\init_state_r[3]_i_6_n_0 ), .I4(complex_oclkdelay_calib_start_int_i_2_n_0), .I5(\init_state_r[3]_i_7_n_0 ), .O(\init_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF08880800)) \init_state_r[3]_i_20 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(complex_pi_incdec_done), .I3(Q[0]), .I4(\init_state_r[5]_i_36_n_0 ), .I5(\init_state_r[2]_i_7_n_0 ), .O(\init_state_r[3]_i_20_n_0 )); LUT6 #( .INIT(64'h0000000011014444)) \init_state_r[3]_i_21 (.I0(rdlvl_stg1_start_int_i_2_n_0), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[1]), .I3(wrlvl_rank_done_r7), .I4(Q[2]), .I5(\init_state_r[3]_i_24_n_0 ), .O(\init_state_r[3]_i_21_n_0 )); LUT6 #( .INIT(64'h0000AFAF0000C000)) \init_state_r[3]_i_22 (.I0(\init_state_r[4]_i_27_n_0 ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(read_calib_i_2_n_0), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[3]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair510" *) LUT4 #( .INIT(16'h3B30)) \init_state_r[3]_i_23 (.I0(complex_oclkdelay_calib_start_int), .I1(done_r_reg), .I2(prbs_rdlvl_done_reg_rep), .I3(prbs_last_byte_done_r), .O(\init_state_r[3]_i_23_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF40434343)) \init_state_r[3]_i_24 (.I0(\init_state_r[2]_i_12_n_0 ), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(cnt_dllk_zqinit_done_r), .I4(mem_init_done_r), .I5(\init_state_r[3]_i_25_n_0 ), .O(\init_state_r[3]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair524" *) LUT2 #( .INIT(4'h2)) \init_state_r[3]_i_25 (.I0(Q[2]), .I1(Q[0]), .O(\init_state_r[3]_i_25_n_0 )); LUT6 #( .INIT(64'h08AAAAAA08AA08AA)) \init_state_r[3]_i_3 (.I0(\init_state_r[4]_i_11_n_0 ), .I1(cnt_init_af_done_r), .I2(mem_init_done_r), .I3(mpr_rdlvl_done_r_reg_1), .I4(\init_state_r[4]_i_26_n_0 ), .I5(dqs_found_done_r_reg_1), .O(\init_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDDDD00F0)) \init_state_r[3]_i_4 (.I0(\init_state_r[2]_i_16_n_0 ), .I1(\init_state_r[4]_i_21_n_0 ), .I2(\init_state_r[3]_i_10_n_0 ), .I3(\init_state_r[3]_i_11_n_0 ), .I4(Q[2]), .I5(rdlvl_start_pre_reg_0), .O(\init_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0155555505555555)) \init_state_r[3]_i_5 (.I0(\init_state_r_reg_n_0_[3] ), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(wrcal_sanity_chk_done_reg), .O(\init_state_r[3]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000FF08)) \init_state_r[3]_i_6 (.I0(wrcal_done_reg_11), .I1(pi_calib_done), .I2(Q[1]), .I3(\init_state_r[3]_i_13_n_0 ), .I4(\init_state_r[3]_i_14_n_0 ), .I5(\init_state_r[3]_i_15_n_0 ), .O(\init_state_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hAAAAAA2AAAA0AA20)) \init_state_r[3]_i_7 (.I0(\init_state_r[3]_i_16_n_0 ), .I1(prbs_gen_oclk_clk_en_i_8_n_0), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(\init_state_r[3]_i_17_n_0 ), .I5(\init_state_r[3]_i_18_n_0 ), .O(\init_state_r[3]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF55550051)) \init_state_r[4]_i_1 (.I0(\init_state_r[4]_i_2_n_0 ), .I1(\init_state_r[4]_i_3_n_0 ), .I2(\init_state_r[4]_i_4_n_0 ), .I3(\init_state_r[4]_i_5_n_0 ), .I4(\init_state_r[4]_i_6_n_0 ), .I5(\init_state_r[4]_i_7_n_0 ), .O(\init_state_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAA88A888888888)) \init_state_r[4]_i_10 (.I0(\init_state_r[4]_i_22_n_0 ), .I1(mem_init_done_r_reg_2), .I2(\init_state_r_reg[2]_0 ), .I3(rdlvl_stg1_done_int_reg_3), .I4(\init_state_r[4]_i_26_n_0 ), .I5(wrlvl_byte_redo_reg), .O(\init_state_r[4]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair565" *) LUT3 #( .INIT(8'h08)) \init_state_r[4]_i_11 (.I0(cnt_cmd_done_r), .I1(Q[1]), .I2(Q[0]), .O(\init_state_r[4]_i_11_n_0 )); LUT6 #( .INIT(64'h0001000DFFFFFFFF)) \init_state_r[4]_i_12 (.I0(Q[3]), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(Q[0]), .I4(ddr2_pre_flag_r_reg_0), .I5(\init_state_r_reg[1]_0 ), .O(\init_state_r[4]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair581" *) LUT3 #( .INIT(8'h8A)) \init_state_r[4]_i_13 (.I0(pi_calib_done), .I1(wrcal_done_reg_10), .I2(dqs_found_done_r_reg), .O(\init_state_r[4]_i_13_n_0 )); LUT6 #( .INIT(64'hFF540000FF5C000C)) \init_state_r[4]_i_14 (.I0(rdlvl_stg1_start_int), .I1(\one_rank.stg1_wr_done_reg_0 ), .I2(rdlvl_last_byte_done), .I3(rdlvl_stg1_done_int_reg), .I4(prbs_rdlvl_done_reg_rep), .I5(prbs_last_byte_done), .O(\init_state_r_reg[4]_0 )); LUT6 #( .INIT(64'h0080000000000000)) \init_state_r[4]_i_15 (.I0(Q[0]), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[2]), .I4(wrlvl_done_r1), .I5(cnt_cmd_done_r), .O(\init_state_r[4]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFF01FF01FF01)) \init_state_r[4]_i_16 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(\init_state_r[4]_i_5_n_0 ), .I2(\init_state_r[4]_i_27_n_0 ), .I3(\init_state_r[4]_i_28_n_0 ), .I4(\init_state_r[4]_i_29_n_0 ), .I5(\init_state_r[5]_i_49_n_0 ), .O(\init_state_r[4]_i_16_n_0 )); LUT6 #( .INIT(64'h00000000FF77F7F7)) \init_state_r[4]_i_17 (.I0(Q[3]), .I1(Q[1]), .I2(cnt_cmd_done_r), .I3(burst_addr_r_reg_0), .I4(Q[0]), .I5(\init_state_r[5]_i_51_n_0 ), .O(\init_state_r[4]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEAA)) \init_state_r[4]_i_18 (.I0(\init_state_r[4]_i_30_n_0 ), .I1(prech_pending_r_reg_0), .I2(\init_state_r[5]_i_13_n_0 ), .I3(\init_state_r_reg[1]_0 ), .I4(\init_state_r[4]_i_31_n_0 ), .I5(\init_state_r[4]_i_32_n_0 ), .O(\init_state_r[4]_i_18_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEA00)) \init_state_r[4]_i_19 (.I0(Q[3]), .I1(complex_pi_incdec_done), .I2(Q[0]), .I3(\init_state_r[5]_i_19_n_0 ), .I4(\init_state_r[4]_i_33_n_0 ), .I5(\init_state_r[6]_i_11_n_0 ), .O(\init_state_r[4]_i_19_n_0 )); LUT6 #( .INIT(64'hABABABABAAABAAAA)) \init_state_r[4]_i_2 (.I0(\init_state_r[5]_i_2_n_0 ), .I1(\init_state_r[4]_i_8_n_0 ), .I2(\init_state_r[4]_i_9_n_0 ), .I3(\init_state_r[4]_i_10_n_0 ), .I4(\init_state_r[4]_i_11_n_0 ), .I5(\init_state_r[4]_i_12_n_0 ), .O(\init_state_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h4000000000000000)) \init_state_r[4]_i_20 (.I0(ddr3_lm_done_r), .I1(wrcal_done_reg_10), .I2(dqs_found_done_r_reg), .I3(wrlvl_done_r1), .I4(prbs_rdlvl_done_reg_rep), .I5(rdlvl_stg1_done_int_reg), .O(\init_state_r[4]_i_20_n_0 )); LUT6 #( .INIT(64'h0000000000000400)) \init_state_r[4]_i_21 (.I0(Q[0]), .I1(cnt_cmd_done_r), .I2(reg_ctrl_cnt_r_reg__0[2]), .I3(reg_ctrl_cnt_r_reg__0[3]), .I4(reg_ctrl_cnt_r_reg__0[0]), .I5(reg_ctrl_cnt_r_reg__0[1]), .O(\init_state_r[4]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair497" *) LUT2 #( .INIT(4'hB)) \init_state_r[4]_i_22 (.I0(mem_init_done_r), .I1(cnt_init_af_done_r), .O(\init_state_r[4]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair485" *) LUT4 #( .INIT(16'hFEFF)) \init_state_r[4]_i_24 (.I0(num_refresh_reg__0[1]), .I1(num_refresh_reg__0[0]), .I2(num_refresh_reg__0[2]), .I3(num_refresh_reg__0[3]), .O(\init_state_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair493" *) LUT4 #( .INIT(16'h0800)) \init_state_r[4]_i_26 (.I0(mem_init_done_r), .I1(dqs_found_done_r_reg), .I2(prbs_rdlvl_done_reg_rep), .I3(prbs_last_byte_done_r), .O(\init_state_r[4]_i_26_n_0 )); LUT6 #( .INIT(64'h00FF00AB00FF0000)) \init_state_r[4]_i_27 (.I0(cnt_cmd_done_r_reg_1), .I1(prech_pending_r_reg_0), .I2(oclkdelay_calib_done_r_reg_2), .I3(\init_state_r[5]_i_57_n_0 ), .I4(Q[0]), .I5(Q[1]), .O(\init_state_r[4]_i_27_n_0 )); LUT4 #( .INIT(16'hABAA)) \init_state_r[4]_i_28 (.I0(Q[3]), .I1(read_calib_reg_0), .I2(pi_phase_locked_all_r4), .I3(pi_phase_locked_all_r3), .O(\init_state_r[4]_i_28_n_0 )); (* SOFT_HLUTNM = "soft_lutpair536" *) LUT4 #( .INIT(16'h0004)) \init_state_r[4]_i_29 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .O(\init_state_r[4]_i_29_n_0 )); LUT6 #( .INIT(64'h75FF75FF00FFFFFF)) \init_state_r[4]_i_3 (.I0(\init_state_r[4]_i_13_n_0 ), .I1(\init_state_r_reg[4]_0 ), .I2(dqs_found_done_r_reg), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I4(Q[3]), .I5(cnt_cmd_done_r), .O(\init_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'h4444454445454545)) \init_state_r[4]_i_30 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(oclk_calib_resume_r_reg), .I2(Q[1]), .I3(Q[3]), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(\init_state_r[4]_i_37_n_0 ), .O(\init_state_r[4]_i_30_n_0 )); LUT6 #( .INIT(64'h45004545FFFFFFFF)) \init_state_r[4]_i_31 (.I0(oclk_calib_resume_level_reg_0), .I1(\init_state_r[5]_i_56_n_0 ), .I2(Q[1]), .I3(\init_state_r[6]_i_17_n_0 ), .I4(oclkdelay_center_calib_start_r_reg), .I5(Q[3]), .O(\init_state_r[4]_i_31_n_0 )); LUT6 #( .INIT(64'h2828282828282800)) \init_state_r[4]_i_32 (.I0(\init_state_r[4]_i_38_n_0 ), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(\init_state_r[4]_i_39_n_0 ), .I5(Q[3]), .O(\init_state_r[4]_i_32_n_0 )); LUT6 #( .INIT(64'hFF00060000000000)) \init_state_r[4]_i_33 (.I0(Q[0]), .I1(write_request_r_reg), .I2(Q[1]), .I3(Q[3]), .I4(Q[2]), .I5(Q[5]), .O(\init_state_r[4]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair488" *) LUT5 #( .INIT(32'h2022FFFF)) \init_state_r[4]_i_37 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(prech_pending_r_reg_0), .I2(complex_oclkdelay_calib_done_r1), .I3(prbs_rdlvl_done_reg), .I4(Q[0]), .O(\init_state_r[4]_i_37_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFD00)) \init_state_r[4]_i_38 (.I0(\init_state_r[5]_i_54_n_0 ), .I1(\init_state_r[4]_i_40_n_0 ), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(\init_state_r[6]_i_22_n_0 ), .I5(\init_state_r_reg[1]_0 ), .O(\init_state_r[4]_i_38_n_0 )); (* SOFT_HLUTNM = "soft_lutpair548" *) LUT4 #( .INIT(16'hF4FF)) \init_state_r[4]_i_39 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg), .I2(Q[1]), .I3(Q[0]), .O(\init_state_r[4]_i_39_n_0 )); LUT6 #( .INIT(64'hAAAAFFFFAAAABBFA)) \init_state_r[4]_i_4 (.I0(\init_state_r[5]_i_12_n_0 ), .I1(rdlvl_stg1_done_r1), .I2(Q[3]), .I3(cnt_cmd_done_r), .I4(prbs_rdlvl_start_i_2_n_0), .I5(reset_rd_addr_r1), .O(\init_state_r[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair508" *) LUT5 #( .INIT(32'h2AAAAAAA)) \init_state_r[4]_i_40 (.I0(Q[3]), .I1(complex_wait_cnt_reg__0[3]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[1]), .I4(complex_wait_cnt_reg__0[0]), .O(\init_state_r[4]_i_40_n_0 )); LUT2 #( .INIT(4'h7)) \init_state_r[4]_i_5 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF0400)) \init_state_r[4]_i_6 (.I0(oclk_calib_resume_level_reg_0), .I1(cnt_cmd_done_r), .I2(prbs_rdlvl_start_i_2_n_0), .I3(dqs_found_done_r_reg_0), .I4(\init_state_r[4]_i_15_n_0 ), .I5(Q[3]), .O(\init_state_r[4]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF44450000)) \init_state_r[4]_i_7 (.I0(\init_state_r[5]_i_26_n_0 ), .I1(\init_state_r[4]_i_16_n_0 ), .I2(oclk_calib_resume_level_reg_0), .I3(\init_state_r[4]_i_17_n_0 ), .I4(\init_state_r[4]_i_18_n_0 ), .I5(\init_state_r[4]_i_19_n_0 ), .O(\init_state_r[4]_i_7_n_0 )); LUT6 #( .INIT(64'hA2AAA200AAAAAAAA)) \init_state_r[4]_i_8 (.I0(\wrcal_reads[7]_i_5_n_0 ), .I1(\init_state_r[4]_i_20_n_0 ), .I2(wrcal_sanity_chk_done_reg_0), .I3(cnt_cmd_done_r), .I4(Q[3]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\init_state_r[4]_i_8_n_0 )); LUT6 #( .INIT(64'h57DF55555555FFFF)) \init_state_r[4]_i_9 (.I0(Q[3]), .I1(Q[1]), .I2(\init_state_r[4]_i_21_n_0 ), .I3(Q[0]), .I4(\init_state_r_reg_n_0_[3] ), .I5(Q[2]), .O(\init_state_r[4]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF1110)) \init_state_r[5]_i_1 (.I0(\init_state_r[5]_i_2_n_0 ), .I1(\init_state_r[5]_i_3_n_0 ), .I2(\init_state_r[5]_i_4_n_0 ), .I3(\init_state_r[5]_i_5_n_0 ), .I4(\init_state_r[5]_i_6_n_0 ), .I5(\init_state_r[5]_i_7_n_0 ), .O(\init_state_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000AA10)) \init_state_r[5]_i_10 (.I0(Q[1]), .I1(cnt_cmd_done_r), .I2(Q[4]), .I3(Q[0]), .I4(\init_state_r[4]_i_5_n_0 ), .I5(\init_state_r[5]_i_31_n_0 ), .O(\init_state_r[5]_i_10_n_0 )); LUT6 #( .INIT(64'h00000000002A0000)) \init_state_r[5]_i_11 (.I0(\init_state_r[1]_i_10_n_0 ), .I1(cnt_cmd_done_r), .I2(Q[1]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[4]), .I5(\init_state_r[1]_i_11_n_0 ), .O(\init_state_r[5]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair486" *) LUT5 #( .INIT(32'h02220202)) \init_state_r[5]_i_12 (.I0(Q[1]), .I1(Q[0]), .I2(\init_state_r[5]_i_32_n_0 ), .I3(complex_sample_cnt_inc_i_2_n_0), .I4(rdlvl_stg1_done_r1), .O(\init_state_r[5]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair503" *) LUT5 #( .INIT(32'h00000010)) \init_state_r[5]_i_13 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\init_state_r[5]_i_13_n_0 )); LUT6 #( .INIT(64'h7500FFFF75007500)) \init_state_r[5]_i_14 (.I0(pi_calib_done), .I1(wrcal_done_reg_10), .I2(dqs_found_done_r_reg), .I3(\init_state_r[5]_i_33_n_0 ), .I4(prbs_rdlvl_start_i_2_n_0), .I5(reset_rd_addr_r1), .O(\init_state_r[5]_i_14_n_0 )); LUT6 #( .INIT(64'h00000000000FCDCD)) \init_state_r[5]_i_15 (.I0(cnt_txpr_done_r), .I1(\init_state_r[5]_i_34_n_0 ), .I2(\init_state_r[5]_i_16_n_0 ), .I3(cnt_cmd_done_r), .I4(Q[1]), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[5]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair527" *) LUT2 #( .INIT(4'h7)) \init_state_r[5]_i_16 (.I0(Q[4]), .I1(Q[0]), .O(\init_state_r[5]_i_16_n_0 )); LUT6 #( .INIT(64'h0000000040700000)) \init_state_r[5]_i_17 (.I0(wrlvl_rank_done_r7), .I1(Q[1]), .I2(Q[0]), .I3(cnt_dllk_zqinit_done_r), .I4(\init_state_r[5]_i_35_n_0 ), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[5]_i_17_n_0 )); LUT2 #( .INIT(4'h8)) \init_state_r[5]_i_18 (.I0(Q[0]), .I1(complex_pi_incdec_done), .O(\init_state_r[5]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair524" *) LUT5 #( .INIT(32'h00E00000)) \init_state_r[5]_i_19 (.I0(\init_state_r[5]_i_36_n_0 ), .I1(Q[0]), .I2(Q[5]), .I3(Q[2]), .I4(Q[1]), .O(\init_state_r[5]_i_19_n_0 )); LUT2 #( .INIT(4'hE)) \init_state_r[5]_i_2 (.I0(Q[5]), .I1(Q[4]), .O(\init_state_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'hBFBF15B7FFFFFFFF)) \init_state_r[5]_i_20 (.I0(Q[0]), .I1(Q[4]), .I2(write_request_r_reg), .I3(\init_state_r[6]_i_21_n_0 ), .I4(prech_pending_r_reg_0), .I5(\init_state_r[5]_i_38_n_0 ), .O(\init_state_r[5]_i_20_n_0 )); LUT6 #( .INIT(64'h444F44444F4F4F4F)) \init_state_r[5]_i_21 (.I0(\init_state_r[5]_i_39_n_0 ), .I1(\init_state_r[5]_i_40_n_0 ), .I2(\init_state_r[5]_i_41_n_0 ), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .I4(Q[4]), .I5(\init_state_r[5]_i_42_n_0 ), .O(\init_state_r[5]_i_21_n_0 )); LUT6 #( .INIT(64'h0808080888888808)) \init_state_r[5]_i_22 (.I0(\init_state_r[5]_i_43_n_0 ), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(Q[4]), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(prbs_rdlvl_done_pulse0), .O(\init_state_r[5]_i_22_n_0 )); LUT6 #( .INIT(64'h4F4F4F4FFF4F4F4F)) \init_state_r[5]_i_23 (.I0(\init_state_r[5]_i_44_n_0 ), .I1(\init_state_r[5]_i_45_n_0 ), .I2(Q[3]), .I3(\init_state_r_reg[5]_0 ), .I4(Q[4]), .I5(oclk_calib_resume_r_reg_0), .O(\init_state_r[5]_i_23_n_0 )); LUT6 #( .INIT(64'h44455555FFFFFFFF)) \init_state_r[5]_i_24 (.I0(\init_state_r[5]_i_48_n_0 ), .I1(\init_state_r[5]_i_49_n_0 ), .I2(Q[4]), .I3(wrcal_resume_r), .I4(\wrcal_reads[7]_i_6_n_0 ), .I5(\wrcal_reads[7]_i_5_n_0 ), .O(\init_state_r[5]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEEFEE)) \init_state_r[5]_i_25 (.I0(\init_state_r[5]_i_50_n_0 ), .I1(Q[3]), .I2(\init_state_r[5]_i_51_n_0 ), .I3(Q[4]), .I4(oclk_calib_resume_level_reg_0), .I5(\init_state_r[5]_i_52_n_0 ), .O(\init_state_r[5]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair550" *) LUT2 #( .INIT(4'hB)) \init_state_r[5]_i_26 (.I0(Q[5]), .I1(Q[4]), .O(\init_state_r[5]_i_26_n_0 )); LUT6 #( .INIT(64'h00000000000000D0)) \init_state_r[5]_i_27 (.I0(cnt_init_af_done_r), .I1(mem_init_done_r), .I2(num_refresh_reg__0[3]), .I3(num_refresh_reg__0[2]), .I4(num_refresh_reg__0[0]), .I5(num_refresh_reg__0[1]), .O(\init_state_r[5]_i_27_n_0 )); LUT6 #( .INIT(64'h44FEFFFF44EEFFFF)) \init_state_r[5]_i_29 (.I0(rdlvl_stg1_done_int_reg), .I1(wrcal_done_reg_10), .I2(prbs_last_byte_done_r), .I3(prbs_rdlvl_done_reg_rep), .I4(dqs_found_done_r_reg), .I5(mem_init_done_r), .O(\init_state_r[5]_i_29_n_0 )); LUT6 #( .INIT(64'h000000000000D5DD)) \init_state_r[5]_i_3 (.I0(\init_state_r_reg[1]_0 ), .I1(\init_state_r[5]_i_8_n_0 ), .I2(cnt_cmd_done_r), .I3(\init_state_r[5]_i_9_n_0 ), .I4(\init_state_r[5]_i_10_n_0 ), .I5(\init_state_r[5]_i_11_n_0 ), .O(\init_state_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h00010000FFFFFFFF)) \init_state_r[5]_i_31 (.I0(cnt_cmd_done_r), .I1(\init_state_r[5]_i_16_n_0 ), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(Q[3]), .O(\init_state_r[5]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFFFFFFFF)) \init_state_r[5]_i_32 (.I0(\complex_num_writes_dec[4]_i_5_n_0 ), .I1(rdlvl_stg1_done_r1), .I2(complex_row0_wr_done), .I3(prbs_rdlvl_done_reg_rep), .I4(complex_num_writes_dec_reg__0[1]), .I5(complex_num_writes_dec_reg__0[0]), .O(\init_state_r[5]_i_32_n_0 )); (* SOFT_HLUTNM = "soft_lutpair532" *) LUT3 #( .INIT(8'h20)) \init_state_r[5]_i_33 (.I0(cnt_cmd_done_r), .I1(Q[1]), .I2(Q[0]), .O(\init_state_r[5]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair527" *) LUT5 #( .INIT(32'h04444444)) \init_state_r[5]_i_34 (.I0(Q[0]), .I1(Q[4]), .I2(\mcGo_r_reg[15] ), .I3(cnt_pwron_cke_done_r), .I4(ck_addr_cmd_delay_done), .O(\init_state_r[5]_i_34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair522" *) LUT2 #( .INIT(4'h8)) \init_state_r[5]_i_35 (.I0(Q[4]), .I1(Q[2]), .O(\init_state_r[5]_i_35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair538" *) LUT4 #( .INIT(16'h7FFF)) \init_state_r[5]_i_36 (.I0(ocal_act_wait_cnt_reg__0[2]), .I1(ocal_act_wait_cnt_reg__0[1]), .I2(ocal_act_wait_cnt_reg__0[0]), .I3(ocal_act_wait_cnt_reg__0[3]), .O(\init_state_r[5]_i_36_n_0 )); (* SOFT_HLUTNM = "soft_lutpair577" *) LUT2 #( .INIT(4'h1)) \init_state_r[5]_i_38 (.I0(Q[2]), .I1(Q[1]), .O(\init_state_r[5]_i_38_n_0 )); LUT6 #( .INIT(64'h0000444FFFFFFFFF)) \init_state_r[5]_i_39 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[4]), .I4(complex_oclkdelay_calib_start_int_reg_0), .I5(\init_state_r[5]_i_53_n_0 ), .O(\init_state_r[5]_i_39_n_0 )); LUT6 #( .INIT(64'h5555555544444544)) \init_state_r[5]_i_4 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(\init_state_r[5]_i_12_n_0 ), .I2(complex_oclkdelay_calib_start_int_reg_0), .I3(Q[4]), .I4(\init_state_r[5]_i_13_n_0 ), .I5(\init_state_r[5]_i_14_n_0 ), .O(\init_state_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFE2)) \init_state_r[5]_i_40 (.I0(\init_state_r[0]_i_27_n_0 ), .I1(Q[0]), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[4]), .I4(Q[1]), .I5(\init_state_r[5]_i_13_n_0 ), .O(\init_state_r[5]_i_40_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEAAEA)) \init_state_r[5]_i_41 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(Q[0]), .I2(prbs_rdlvl_done_reg), .I3(complex_oclkdelay_calib_done_r1), .I4(prech_pending_r_reg_0), .I5(Q[1]), .O(\init_state_r[5]_i_41_n_0 )); (* SOFT_HLUTNM = "soft_lutpair488" *) LUT2 #( .INIT(4'hB)) \init_state_r[5]_i_42 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(Q[0]), .O(\init_state_r[5]_i_42_n_0 )); LUT6 #( .INIT(64'hAAAAAAAABFBBAAAA)) \init_state_r[5]_i_43 (.I0(\init_state_r[6]_i_22_n_0 ), .I1(\init_state_r[5]_i_54_n_0 ), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(Q[4]), .I4(Q[0]), .I5(prech_pending_r_reg_0), .O(\init_state_r[5]_i_43_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF03000101)) \init_state_r[5]_i_44 (.I0(Q[4]), .I1(Q[1]), .I2(Q[0]), .I3(oclkdelay_int_ref_req_reg_0), .I4(cnt_cmd_done_r), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[5]_i_44_n_0 )); LUT6 #( .INIT(64'h3373F373FFFFFFFF)) \init_state_r[5]_i_45 (.I0(oclkdelay_center_calib_start_r_reg_0), .I1(\init_state_r[5]_i_56_n_0 ), .I2(Q[4]), .I3(Q[0]), .I4(cnt_cmd_done_r), .I5(Q[1]), .O(\init_state_r[5]_i_45_n_0 )); (* SOFT_HLUTNM = "soft_lutpair536" *) LUT4 #( .INIT(16'h4000)) \init_state_r[5]_i_46 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .I3(\init_state_r_reg_n_0_[3] ), .O(\init_state_r_reg[5]_0 )); LUT6 #( .INIT(64'hFFFFFFFFE8E8C8E8)) \init_state_r[5]_i_48 (.I0(Q[1]), .I1(Q[0]), .I2(Q[4]), .I3(pi_phase_locked_all_r3), .I4(pi_phase_locked_all_r4), .I5(\init_state_r[0]_i_25_n_0 ), .O(\init_state_r[5]_i_48_n_0 )); (* SOFT_HLUTNM = "soft_lutpair534" *) LUT4 #( .INIT(16'h5554)) \init_state_r[5]_i_49 (.I0(wrcal_resume_r), .I1(wrcal_done_reg_10), .I2(prech_pending_r_reg_0), .I3(wrlvl_byte_redo), .O(\init_state_r[5]_i_49_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEEFEE)) \init_state_r[5]_i_5 (.I0(\init_state_r[5]_i_15_n_0 ), .I1(Q[3]), .I2(\init_state_r[5]_i_16_n_0 ), .I3(\init_state_r_reg_n_0_[3] ), .I4(cnt_cmd_done_r), .I5(\init_state_r[5]_i_17_n_0 ), .O(\init_state_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000EEEEFEEE)) \init_state_r[5]_i_50 (.I0(\init_state_r[5]_i_57_n_0 ), .I1(\init_state_r[5]_i_58_n_0 ), .I2(Q[1]), .I3(Q[4]), .I4(oclkdelay_calib_done_r_reg_3), .I5(\init_state_r[5]_i_60_n_0 ), .O(\init_state_r[5]_i_50_n_0 )); LUT6 #( .INIT(64'h0054000000540054)) \init_state_r[5]_i_51 (.I0(Q[1]), .I1(wrcal_done_reg_10), .I2(prech_pending_r_reg_0), .I3(Q[0]), .I4(wrcal_prech_req), .I5(cnt_cmd_done_r), .O(\init_state_r[5]_i_51_n_0 )); LUT6 #( .INIT(64'h00000000F2F200F2)) \init_state_r[5]_i_52 (.I0(\init_state_r[5]_i_61_n_0 ), .I1(wrcal_prech_req), .I2(\init_state_r[1]_i_20_n_0 ), .I3(Q[1]), .I4(\init_state_r[5]_i_62_n_0 ), .I5(oclk_calib_resume_level_reg_0), .O(\init_state_r[5]_i_52_n_0 )); LUT6 #( .INIT(64'h4044404040444044)) \init_state_r[5]_i_53 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[1]), .I3(prech_pending_r_reg_0), .I4(prbs_rdlvl_done_r1), .I5(prbs_rdlvl_done_reg), .O(\init_state_r[5]_i_53_n_0 )); LUT6 #( .INIT(64'hFFFF00BFFFFFFFFF)) \init_state_r[5]_i_54 (.I0(complex_row1_wr_done), .I1(complex_ocal_num_samples_done_r), .I2(complex_oclkdelay_calib_start_int), .I3(\one_rank.stg1_wr_done_reg_0 ), .I4(oclkdelay_center_calib_start_r_reg), .I5(prbs_gen_oclk_clk_en_i_8_n_0), .O(\init_state_r[5]_i_54_n_0 )); (* SOFT_HLUTNM = "soft_lutpair537" *) LUT4 #( .INIT(16'hEEEF)) \init_state_r[5]_i_56 (.I0(oclkdelay_int_ref_req_reg_0), .I1(Q[0]), .I2(complex_oclk_calib_resume), .I3(oclk_calib_resume_level), .O(\init_state_r[5]_i_56_n_0 )); LUT6 #( .INIT(64'h0004000000000000)) \init_state_r[5]_i_57 (.I0(oclk_wr_cnt_reg__0[2]), .I1(oclk_wr_cnt_reg__0[0]), .I2(oclk_wr_cnt_reg__0[1]), .I3(oclk_wr_cnt_reg__0[3]), .I4(Q[1]), .I5(Q[0]), .O(\init_state_r[5]_i_57_n_0 )); LUT6 #( .INIT(64'h5D5D5D5D5D5D7D5D)) \init_state_r[5]_i_58 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(cnt_cmd_done_r), .I4(lim2init_prech_req), .I5(ocd_prech_req), .O(\init_state_r[5]_i_58_n_0 )); LUT6 #( .INIT(64'hFFCF8F8FCCCC8888)) \init_state_r[5]_i_6 (.I0(\init_state_r[5]_i_18_n_0 ), .I1(\init_state_r[5]_i_19_n_0 ), .I2(\init_state_r[5]_i_20_n_0 ), .I3(Q[2]), .I4(Q[4]), .I5(Q[5]), .O(\init_state_r[5]_i_6_n_0 )); LUT6 #( .INIT(64'h000000F1FFFFFFFF)) \init_state_r[5]_i_60 (.I0(cnt_cmd_done_r), .I1(Q[0]), .I2(\init_state_r_reg[1]_1 ), .I3(Q[4]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\init_state_r[5]_i_60_n_0 )); (* SOFT_HLUTNM = "soft_lutpair539" *) LUT2 #( .INIT(4'h2)) \init_state_r[5]_i_61 (.I0(cnt_cmd_done_r), .I1(Q[0]), .O(\init_state_r[5]_i_61_n_0 )); (* SOFT_HLUTNM = "soft_lutpair579" *) LUT3 #( .INIT(8'hCA)) \init_state_r[5]_i_62 (.I0(cnt_cmd_done_r), .I1(burst_addr_r_reg_0), .I2(Q[0]), .O(\init_state_r[5]_i_62_n_0 )); LUT6 #( .INIT(64'h00000000FEFE00FE)) \init_state_r[5]_i_7 (.I0(\init_state_r[5]_i_21_n_0 ), .I1(\init_state_r[5]_i_22_n_0 ), .I2(\init_state_r[5]_i_23_n_0 ), .I3(\init_state_r[5]_i_24_n_0 ), .I4(\init_state_r[5]_i_25_n_0 ), .I5(\init_state_r[5]_i_26_n_0 ), .O(\init_state_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFF5FFFDFDFDFDF)) \init_state_r[5]_i_8 (.I0(\init_state_r[4]_i_11_n_0 ), .I1(oclkdelay_calib_done_r_reg_2), .I2(\init_state_r[5]_i_27_n_0 ), .I3(wrlvl_byte_redo_reg), .I4(\init_state_r[5]_i_29_n_0 ), .I5(mpr_rdlvl_done_r_reg_2), .O(\init_state_r[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair597" *) LUT2 #( .INIT(4'h2)) \init_state_r[5]_i_9 (.I0(Q[4]), .I1(Q[0]), .O(\init_state_r[5]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00D00000)) \init_state_r[6]_i_1 (.I0(\init_state_r[6]_i_2_n_0 ), .I1(\init_state_r[6]_i_3_n_0 ), .I2(Q[4]), .I3(Q[5]), .I4(Q[3]), .I5(\init_state_r[6]_i_4_n_0 ), .O(\init_state_r[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0100000000000000)) \init_state_r[6]_i_10 (.I0(\init_state_r[4]_i_5_n_0 ), .I1(Q[4]), .I2(ddr3_lm_done_r_i_2_n_0), .I3(\init_state_r[6]_i_20_n_0 ), .I4(cnt_cmd_done_r), .I5(rdlvl_stg1_done_r1), .O(\init_state_r[6]_i_10_n_0 )); LUT6 #( .INIT(64'h0020002000200000)) \init_state_r[6]_i_11 (.I0(Q[0]), .I1(Q[1]), .I2(Q[5]), .I3(Q[2]), .I4(\init_state_r[6]_i_21_n_0 ), .I5(prech_pending_r_reg_0), .O(\init_state_r[6]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair529" *) LUT4 #( .INIT(16'hAA08)) \init_state_r[6]_i_12 (.I0(Q[0]), .I1(prbs_rdlvl_done_reg_rep), .I2(complex_oclkdelay_calib_done_r1), .I3(prech_pending_r_reg_0), .O(\init_state_r[6]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair550" *) LUT4 #( .INIT(16'hFF4F)) \init_state_r[6]_i_13 (.I0(prbs_rdlvl_done_r1), .I1(prbs_rdlvl_done_reg), .I2(Q[5]), .I3(prbs_gen_oclk_clk_en_i_8_n_0), .O(\init_state_r[6]_i_13_n_0 )); LUT4 #( .INIT(16'hFFAE)) \init_state_r[6]_i_14 (.I0(\init_state_r[5]_i_13_n_0 ), .I1(prbs_rdlvl_done_reg), .I2(prbs_rdlvl_done_r1), .I3(prech_pending_r_reg_0), .O(\init_state_r[6]_i_14_n_0 )); LUT6 #( .INIT(64'h8000FFFF80000000)) \init_state_r[6]_i_15 (.I0(complex_wait_cnt_reg__0[0]), .I1(complex_wait_cnt_reg__0[1]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[3]), .I4(Q[0]), .I5(\init_state_r[0]_i_27_n_0 ), .O(\init_state_r[6]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair537" *) LUT2 #( .INIT(4'hE)) \init_state_r[6]_i_16 (.I0(oclk_calib_resume_level), .I1(complex_oclk_calib_resume), .O(\init_state_r[6]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \init_state_r[6]_i_17 (.I0(Q[1]), .I1(Q[0]), .I2(wrlvl_final_mux), .I3(oclkdelay_int_ref_req_reg_0), .I4(prech_pending_r_reg_0), .I5(oclkdelay_calib_done_r_reg_2), .O(\init_state_r[6]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair509" *) LUT2 #( .INIT(4'h6)) \init_state_r[6]_i_18 (.I0(Q[0]), .I1(Q[1]), .O(\init_state_r[6]_i_18_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFABFB0000)) \init_state_r[6]_i_19 (.I0(prech_pending_r_reg_0), .I1(Q[5]), .I2(prbs_gen_oclk_clk_en_i_8_n_0), .I3(oclkdelay_center_calib_start_r_reg), .I4(Q[0]), .I5(\init_state_r[6]_i_22_n_0 ), .O(\init_state_r[6]_i_19_n_0 )); LUT6 #( .INIT(64'hFBFBFBFAFBFBFBFB)) \init_state_r[6]_i_2 (.I0(\init_state_r[6]_i_5_n_0 ), .I1(complex_oclkdelay_calib_start_int_reg_0), .I2(\init_state_r[4]_i_5_n_0 ), .I3(prbs_rdlvl_done_reg_rep_0), .I4(complex_oclk_calib_resume), .I5(Q[5]), .O(\init_state_r[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair544" *) LUT2 #( .INIT(4'h2)) \init_state_r[6]_i_20 (.I0(Q[0]), .I1(reset_rd_addr_r1), .O(\init_state_r[6]_i_20_n_0 )); LUT4 #( .INIT(16'h0004)) \init_state_r[6]_i_21 (.I0(mask_lim_done), .I1(done_r_reg), .I2(complex_mask_lim_done), .I3(oclkdelay_center_calib_start_r_reg), .O(\init_state_r[6]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair509" *) LUT5 #( .INIT(32'h37773737)) \init_state_r[6]_i_22 (.I0(Q[0]), .I1(Q[1]), .I2(prbs_rdlvl_start_r_reg), .I3(num_samples_done_r), .I4(complex_init_pi_dec_done), .O(\init_state_r[6]_i_22_n_0 )); LUT6 #( .INIT(64'h0503FFFF05F3FFFF)) \init_state_r[6]_i_3 (.I0(\init_state_r[6]_i_7_n_0 ), .I1(\init_state_r[6]_i_8_n_0 ), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[3]), .I5(\init_state_r[6]_i_9_n_0 ), .O(\init_state_r[6]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000FAFACAFA)) \init_state_r[6]_i_4 (.I0(\init_state_r[6]_i_10_n_0 ), .I1(Q[2]), .I2(Q[5]), .I3(complex_pi_incdec_done), .I4(prbs_rdlvl_start_i_2_n_0), .I5(\init_state_r[6]_i_11_n_0 ), .O(\init_state_r[6]_i_4_n_0 )); LUT6 #( .INIT(64'h5555555545455545)) \init_state_r[6]_i_5 (.I0(Q[1]), .I1(prbs_gen_oclk_clk_en_i_8_n_0), .I2(Q[5]), .I3(Q[0]), .I4(complex_sample_cnt_inc_i_2_n_0), .I5(\init_state_r[6]_i_12_n_0 ), .O(\init_state_r[6]_i_5_n_0 )); LUT6 #( .INIT(64'hEEEEFFFFEEEEF0FF)) \init_state_r[6]_i_7 (.I0(\init_state_r[6]_i_13_n_0 ), .I1(Q[0]), .I2(\init_state_r[6]_i_14_n_0 ), .I3(Q[5]), .I4(Q[1]), .I5(\init_state_r[6]_i_15_n_0 ), .O(\init_state_r[6]_i_7_n_0 )); LUT6 #( .INIT(64'hFAFAFBFBFA00FBFB)) \init_state_r[6]_i_8 (.I0(\init_state_r[6]_i_16_n_0 ), .I1(oclkdelay_center_calib_start_r_reg), .I2(\init_state_r[6]_i_17_n_0 ), .I3(\init_state_r[6]_i_18_n_0 ), .I4(Q[5]), .I5(cnt_cmd_done_r), .O(\init_state_r[6]_i_8_n_0 )); LUT6 #( .INIT(64'hAAAA20AAAAAAAAAA)) \init_state_r[6]_i_9 (.I0(\init_state_r[6]_i_19_n_0 ), .I1(prbs_rdlvl_done_r1), .I2(prbs_rdlvl_done_reg), .I3(Q[5]), .I4(prbs_gen_oclk_clk_en_i_8_n_0), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\init_state_r[6]_i_9_n_0 )); FDRE \init_state_r_reg[0] (.C(CLK), .CE(1'b1), .D(\init_state_r[0]_i_1_n_0 ), .Q(Q[0]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r_reg[1] (.C(CLK), .CE(1'b1), .D(\init_state_r[1]_i_1_n_0 ), .Q(Q[1]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r_reg[2] (.C(CLK), .CE(1'b1), .D(\init_state_r[2]_i_1_n_0 ), .Q(Q[2]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r_reg[3] (.C(CLK), .CE(1'b1), .D(\init_state_r[3]_i_1_n_0 ), .Q(\init_state_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r_reg[4] (.C(CLK), .CE(1'b1), .D(\init_state_r[4]_i_1_n_0 ), .Q(Q[3]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r_reg[5] (.C(CLK), .CE(1'b1), .D(\init_state_r[5]_i_1_n_0 ), .Q(Q[4]), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \init_state_r_reg[6] (.C(CLK), .CE(1'b1), .D(\init_state_r[6]_i_1_n_0 ), .Q(Q[5]), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair608" *) LUT2 #( .INIT(4'h2)) lim_start_r_i_3 (.I0(\oclkdelay_ref_cnt_reg[13]_0 ), .I1(oclkdelay_calib_done_r_reg_2), .O(lim_start_r_reg)); LUT4 #( .INIT(16'h000E)) mask_lim_done_i_1 (.I0(mask_lim_done), .I1(prech_pending_r), .I2(prech_done_r3), .I3(rstdiv0_sync_r1_reg_rep__25), .O(mask_lim_done_i_1_n_0)); FDRE mask_lim_done_reg (.C(CLK), .CE(1'b1), .D(mask_lim_done_i_1_n_0), .Q(mask_lim_done), .R(1'b0)); LUT5 #( .INIT(32'hFFFF4000)) mem_init_done_r_i_1 (.I0(cnt_dllk_zqinit_done_r), .I1(mem_init_done_r_reg_0[1]), .I2(mem_init_done_r_reg_1), .I3(mem_init_done_r_reg_0[0]), .I4(mem_init_done_r), .O(mem_init_done_r_i_1_n_0)); LUT6 #( .INIT(64'h8000000000000000)) mem_init_done_r_i_2 (.I0(cnt_dllk_zqinit_r_reg__0[5]), .I1(cnt_dllk_zqinit_r_reg__0[3]), .I2(cnt_dllk_zqinit_r_reg__0[1]), .I3(cnt_dllk_zqinit_r_reg__0[0]), .I4(cnt_dllk_zqinit_r_reg__0[2]), .I5(cnt_dllk_zqinit_r_reg__0[4]), .O(mem_init_done_r_reg_1)); FDRE mem_init_done_r_reg (.C(CLK), .CE(1'b1), .D(mem_init_done_r_i_1_n_0), .Q(mem_init_done_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_0_5_i_1 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_cs_n), .O(\rd_ptr_timing_reg[0]_3 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [63]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [31]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [127]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [95]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [191]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_0_5_i_7 (.I0(\write_buffer.wr_buf_out_data_reg[255] [159]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [4])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_12_17_i_1 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_cas_n), .O(\rd_ptr_timing_reg[0] [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [16]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [167]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [175]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [183]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [190]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [6]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [135]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [143]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [151]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [158]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [231]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [239]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [247]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [254]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [199]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [207]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [215]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [222]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [38]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [46]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [54]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [61]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [6]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [14]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [22]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_12_17_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [29]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [102]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [110]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [118]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [125]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [19])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_18_23_i_1__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [27]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [70]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [78]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [86]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [93]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [166]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [174]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [182]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [189]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [134]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [142]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [150]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [157]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [230]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [238]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [246]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [253]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [198]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [206]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [214]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_18_23_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [221]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [22])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_24_29_i_1 (.I0(mc_ras_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_ras_n), .O(\rd_ptr_timing_reg[0] [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [17]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [37]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [45]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [53]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [60]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [7]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [5]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [13]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [21]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [28]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [101]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [109]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [117]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [124]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [27])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_24_29_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[42] [28]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [69]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [77]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [85]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [92]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [165]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [173]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [181]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [188]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [133]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [141]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [149]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_24_29_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [156]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [18]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [3]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [229]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [237]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [245]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [252]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [8]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [0]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [197]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [205]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [213]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [220]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [36]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [44]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [52]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [59]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [33])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_30_35_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[15])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_30_35_i_3__4 (.I0(phy_bank[9]), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [5])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[42] [29]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [6]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [4])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [4]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [12]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [20]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_4__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [27]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [100]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [108]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [116]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [123]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [68]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [76]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [84]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_30_35_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [91]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [14]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [19]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[17])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [164]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [172]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [180]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [187]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [4]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [9]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [132]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [140]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [148]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [155]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [228]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [236]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [244]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [251]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [196]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [204]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [212]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [219]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [35]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [43]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [51]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [58]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [3]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [11]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [19]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [32])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_36_41_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [26]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [40])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_42_47_i_1 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__14), .I2(calib_odt), .O(\my_full_reg[3] [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [99]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [107]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [115]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [35])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [122]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [43])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_42_47_i_1__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [9])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_42_47_i_1__5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [25]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [30]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [67]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [75]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [83]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [34])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [90]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [5]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [163]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [171]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [179]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [37])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_3__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [186]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [2]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [131]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [139]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [147]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [36])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [154]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [227]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [235]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [243]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [39])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [250]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [47])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_42_47_i_5__3 (.I0(phy_bank[11]), .I1(init_calib_complete_reg_rep__12), .O(\rd_ptr_timing_reg[0] [13])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [8]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [12])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [195]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [203]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [211]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [38])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_42_47_i_6__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [218]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [46])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_48_53_i_1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__14), .I2(calib_cke), .O(\my_full_reg[3] [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__0 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [15])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [20]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [34]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [42]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [50]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [41])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_1__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [57]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [1]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [14])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [10]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [2]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [40])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [10]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [40])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [18]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [40])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [25]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [98]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [43])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [106]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [43])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [114]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [43])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [121]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [51])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_48_53_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [17])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_48_53_i_3__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[42] [22]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [16])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [31]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [66]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [74]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [82]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [42])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_4__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [89]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [19])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [162]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [170]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [178]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [45])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_5__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [185]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6 (.I0(\cmd_pipe_plus.mc_address_reg[42] [0]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [18])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [130]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [138]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [146]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [44])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_48_53_i_6__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [153]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [226]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [47])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [234]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [47])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [242]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [47])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [249]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [55])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_54_59_i_1__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [21])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [11]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [21]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [20])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [194]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [46])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [202]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [46])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [210]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [46])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [217]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [23])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [33]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [41]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [49]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [49])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_3__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [56]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [57])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_54_59_i_3__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[42] [2]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [22])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [32]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [1]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [9]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [17]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [48])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_4__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [24]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [97]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [51])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [105]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [51])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [113]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [51])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_5__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [120]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [59])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_54_59_i_5__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [25])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6 (.I0(\cmd_pipe_plus.mc_address_reg[42] [23]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [24])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [65]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [73]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [81]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [50])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_54_59_i_6__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [88]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [13]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [27])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__0 (.I0(mc_ras_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[29])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [161]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [169]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [177]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [53])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [184]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [3]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__14), .O(\rd_ptr_timing_reg[0] [26])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [12]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [129]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [137]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [145]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [52])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_2__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [152]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_41 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [225]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [55])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [233]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [55])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [241]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [55])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [248]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [193]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [201]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [209]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [54])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [216]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [62])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [32]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [57])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [40]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [57])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [48]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [57])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [0]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [8]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_60_65_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [16]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [56])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [96]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [59])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_1__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [104]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [59])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [112]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [59])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_66_71_i_1__2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [29])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_66_71_i_1__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [24]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [28])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [33]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[30])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [64]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [72]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [80]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [58])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [160]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [168]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_39 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [176]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_40 [61])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [128]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [136]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [144]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [60])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [224]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_38 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_5__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [232]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_5__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [240]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [63])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [192]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__9), .O(\my_empty_reg[7]_38 [62])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_6__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [200]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_39 [62])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_66_71_i_6__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [208]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_40 [62])); LUT3 #( .INIT(8'hB8)) mem_reg_0_15_6_11_i_1 (.I0(mc_we_n), .I1(init_calib_complete_reg_rep__14), .I2(phy_we_n), .O(\rd_ptr_timing_reg[0]_3 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [15]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [39]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [47]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [55]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [1])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_1__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [255]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7]_41 [7])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__14), .O(phy_dout[0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [7]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_38 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [15]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_39 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [23]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_40 [0])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_2__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [223]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__8), .O(\my_empty_reg[7]_41 [6])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [62]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [9])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [103]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_38 [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [111]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_39 [3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_3__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [119]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_40 [3])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_6_11_i_3__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I1(init_calib_complete_reg_rep__13), .O(phy_dout[3])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4 (.I0(\cmd_pipe_plus.mc_address_reg[42] [26]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__13), .O(phy_dout[2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [30]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__12), .O(\my_empty_reg[7]_41 [8])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [71]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_38 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [79]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_39 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_4__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [87]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_40 [2])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [126]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__10), .O(\my_empty_reg[7]_41 [11])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_6_11_i_6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [94]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__11), .O(\my_empty_reg[7]_41 [10])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_72_77_i_1__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [4]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [31])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_72_77_i_2 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [1]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [30])); LUT2 #( .INIT(4'hE)) mem_reg_0_15_72_77_i_3 (.I0(phy_bank[10]), .I1(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [33])); LUT3 #( .INIT(8'hAC)) mem_reg_0_15_72_77_i_4 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [7]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__13), .O(\rd_ptr_timing_reg[0] [32])); (* SOFT_HLUTNM = "soft_lutpair485" *) LUT5 #( .INIT(32'hAAAAAAA8)) mpr_end_if_reset_i_1 (.I0(mpr_last_byte_done), .I1(num_refresh_reg__0[2]), .I2(num_refresh_reg__0[0]), .I3(num_refresh_reg__0[1]), .I4(num_refresh_reg__0[3]), .O(mpr_end_if_reset0)); FDRE mpr_end_if_reset_reg (.C(CLK), .CE(1'b1), .D(mpr_end_if_reset0), .Q(mpr_end_if_reset), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'hFFFFFFFF00100000)) mpr_rdlvl_start_i_1 (.I0(mpr_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[1]), .I4(dqs_found_done_r_reg), .I5(mpr_rdlvl_start_r_reg), .O(mpr_rdlvl_start_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair525" *) LUT4 #( .INIT(16'hFBFF)) mpr_rdlvl_start_i_2 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(Q[0]), .O(mpr_rdlvl_start_i_2_n_0)); FDRE mpr_rdlvl_start_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_start_i_1_n_0), .Q(mpr_rdlvl_start_r_reg), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair611" *) LUT1 #( .INIT(2'h1)) \num_refresh[0]_i_1 (.I0(num_refresh_reg__0[0]), .O(p_0_in__4[0])); (* SOFT_HLUTNM = "soft_lutpair611" *) LUT2 #( .INIT(4'h6)) \num_refresh[1]_i_1 (.I0(num_refresh_reg__0[1]), .I1(num_refresh_reg__0[0]), .O(p_0_in__4[1])); (* SOFT_HLUTNM = "soft_lutpair556" *) LUT3 #( .INIT(8'h6A)) \num_refresh[2]_i_1 (.I0(num_refresh_reg__0[2]), .I1(num_refresh_reg__0[0]), .I2(num_refresh_reg__0[1]), .O(p_0_in__4[2])); LUT6 #( .INIT(64'hFEFEFEFEFEFFFEFE)) \num_refresh[3]_i_1 (.I0(\num_refresh[3]_i_4_n_0 ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(\num_refresh[3]_i_5_n_0 ), .I3(prbs_rdlvl_start_i_2_n_0), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(read_calib_i_2_n_0), .O(\num_refresh[3]_i_1_n_0 )); LUT6 #( .INIT(64'h22A2AAA2AAAAAAAA)) \num_refresh[3]_i_2 (.I0(\cnt_init_mr_r_reg[1]_0 ), .I1(dqs_found_done_r_reg), .I2(wrcal_done_reg_10), .I3(rdlvl_stg1_done_int_reg), .I4(prbs_rdlvl_done_reg), .I5(oclkdelay_calib_done_r_reg_2), .O(num_refresh0)); (* SOFT_HLUTNM = "soft_lutpair556" *) LUT4 #( .INIT(16'h6AAA)) \num_refresh[3]_i_3 (.I0(num_refresh_reg__0[3]), .I1(num_refresh_reg__0[1]), .I2(num_refresh_reg__0[0]), .I3(num_refresh_reg__0[2]), .O(p_0_in__4[3])); (* SOFT_HLUTNM = "soft_lutpair506" *) LUT5 #( .INIT(32'h404000FF)) \num_refresh[3]_i_4 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[0]), .I3(\num_refresh[3]_i_6_n_0 ), .I4(Q[1]), .O(\num_refresh[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000002000)) \num_refresh[3]_i_5 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(complex_oclkdelay_calib_start_int_reg_0), .O(\num_refresh[3]_i_5_n_0 )); LUT6 #( .INIT(64'hFBFFFFFFFEFFFFFF)) \num_refresh[3]_i_6 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(Q[0]), .O(\num_refresh[3]_i_6_n_0 )); FDRE \num_refresh_reg[0] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[0]), .Q(num_refresh_reg__0[0]), .R(\num_refresh[3]_i_1_n_0 )); FDRE \num_refresh_reg[1] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[1]), .Q(num_refresh_reg__0[1]), .R(\num_refresh[3]_i_1_n_0 )); FDRE \num_refresh_reg[2] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[2]), .Q(num_refresh_reg__0[2]), .R(\num_refresh[3]_i_1_n_0 )); FDRE \num_refresh_reg[3] (.C(CLK), .CE(num_refresh0), .D(p_0_in__4[3]), .Q(num_refresh_reg__0[3]), .R(\num_refresh[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \ocal_act_wait_cnt[0]_i_1 (.I0(ocal_act_wait_cnt_reg__0[0]), .O(p_0_in__9[0])); (* SOFT_HLUTNM = "soft_lutpair603" *) LUT2 #( .INIT(4'h6)) \ocal_act_wait_cnt[1]_i_1 (.I0(ocal_act_wait_cnt_reg__0[1]), .I1(ocal_act_wait_cnt_reg__0[0]), .O(p_0_in__9[1])); (* SOFT_HLUTNM = "soft_lutpair603" *) LUT3 #( .INIT(8'h6A)) \ocal_act_wait_cnt[2]_i_1 (.I0(ocal_act_wait_cnt_reg__0[2]), .I1(ocal_act_wait_cnt_reg__0[1]), .I2(ocal_act_wait_cnt_reg__0[0]), .O(p_0_in__9[2])); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) \ocal_act_wait_cnt[3]_i_1 (.I0(\ocal_act_wait_cnt[3]_i_3_n_0 ), .I1(Q[4]), .I2(Q[3]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[5]), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\ocal_act_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair538" *) LUT4 #( .INIT(16'h6AAA)) \ocal_act_wait_cnt[3]_i_2 (.I0(ocal_act_wait_cnt_reg__0[3]), .I1(ocal_act_wait_cnt_reg__0[0]), .I2(ocal_act_wait_cnt_reg__0[1]), .I3(ocal_act_wait_cnt_reg__0[2]), .O(p_0_in__9[3])); LUT6 #( .INIT(64'h000000007FFF0000)) \ocal_act_wait_cnt[3]_i_3 (.I0(ocal_act_wait_cnt_reg__0[3]), .I1(ocal_act_wait_cnt_reg__0[0]), .I2(ocal_act_wait_cnt_reg__0[1]), .I3(ocal_act_wait_cnt_reg__0[2]), .I4(Q[1]), .I5(Q[0]), .O(\ocal_act_wait_cnt[3]_i_3_n_0 )); FDRE \ocal_act_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__9[0]), .Q(ocal_act_wait_cnt_reg__0[0]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE \ocal_act_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__9[1]), .Q(ocal_act_wait_cnt_reg__0[1]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE \ocal_act_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__9[2]), .Q(ocal_act_wait_cnt_reg__0[2]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE \ocal_act_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__9[3]), .Q(ocal_act_wait_cnt_reg__0[3]), .R(\ocal_act_wait_cnt[3]_i_1_n_0 )); FDRE ocal_last_byte_done_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_center_calib_done_r_reg), .Q(ocal_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h00000000EEEEEE0E)) oclk_calib_resume_level_i_1 (.I0(oclk_calib_resume_level), .I1(complex_oclk_calib_resume), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(complex_oclkdelay_calib_start_int_i_2_n_0), .I4(oclk_calib_resume_level_reg_0), .I5(rstdiv0_sync_r1_reg_rep__25), .O(oclk_calib_resume_level_i_1_n_0)); FDRE oclk_calib_resume_level_reg (.C(CLK), .CE(1'b1), .D(oclk_calib_resume_level_i_1_n_0), .Q(oclk_calib_resume_level), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair607" *) LUT1 #( .INIT(2'h1)) \oclk_wr_cnt[0]_i_1 (.I0(oclk_wr_cnt_reg__0[0]), .O(\oclk_wr_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair607" *) LUT2 #( .INIT(4'h9)) \oclk_wr_cnt[1]_i_1 (.I0(oclk_wr_cnt_reg__0[0]), .I1(oclk_wr_cnt_reg__0[1]), .O(\oclk_wr_cnt[1]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \oclk_wr_cnt[2]_i_1 (.I0(oclk_wr_cnt_reg__0[2]), .I1(oclk_wr_cnt_reg__0[1]), .I2(oclk_wr_cnt_reg__0[0]), .O(oclk_wr_cnt0[2])); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAAB)) \oclk_wr_cnt[3]_i_1 (.I0(\oclk_wr_cnt[3]_i_4_n_0 ), .I1(oclk_wr_cnt_reg__0[2]), .I2(oclk_wr_cnt_reg__0[0]), .I3(oclk_wr_cnt_reg__0[1]), .I4(oclk_wr_cnt_reg__0[3]), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\oclk_wr_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'h00800000)) \oclk_wr_cnt[3]_i_2 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(read_calib_i_2_n_0), .I4(\init_state_r_reg_n_0_[3] ), .O(p_0_in0_in)); (* SOFT_HLUTNM = "soft_lutpair547" *) LUT4 #( .INIT(16'hAAA9)) \oclk_wr_cnt[3]_i_3 (.I0(oclk_wr_cnt_reg__0[3]), .I1(oclk_wr_cnt_reg__0[2]), .I2(oclk_wr_cnt_reg__0[0]), .I3(oclk_wr_cnt_reg__0[1]), .O(oclk_wr_cnt0[3])); LUT6 #( .INIT(64'h0000000000100000)) \oclk_wr_cnt[3]_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(Q[4]), .I3(Q[5]), .I4(Q[3]), .I5(oclk_calib_resume_level_reg_0), .O(\oclk_wr_cnt[3]_i_4_n_0 )); FDRE \oclk_wr_cnt_reg[0] (.C(CLK), .CE(p_0_in0_in), .D(\oclk_wr_cnt[0]_i_1_n_0 ), .Q(oclk_wr_cnt_reg__0[0]), .R(\oclk_wr_cnt[3]_i_1_n_0 )); FDRE \oclk_wr_cnt_reg[1] (.C(CLK), .CE(p_0_in0_in), .D(\oclk_wr_cnt[1]_i_1_n_0 ), .Q(oclk_wr_cnt_reg__0[1]), .R(\oclk_wr_cnt[3]_i_1_n_0 )); FDSE \oclk_wr_cnt_reg[2] (.C(CLK), .CE(p_0_in0_in), .D(oclk_wr_cnt0[2]), .Q(oclk_wr_cnt_reg__0[2]), .S(\oclk_wr_cnt[3]_i_1_n_0 )); FDRE \oclk_wr_cnt_reg[3] (.C(CLK), .CE(p_0_in0_in), .D(oclk_wr_cnt0[3]), .Q(oclk_wr_cnt_reg__0[3]), .R(\oclk_wr_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair608" *) LUT2 #( .INIT(4'hE)) oclkdelay_calib_start_int_i_1 (.I0(oclkdelay_start_dly_r), .I1(\oclkdelay_ref_cnt_reg[13]_0 ), .O(oclkdelay_calib_start_int_i_1_n_0)); FDRE oclkdelay_calib_start_int_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_start_int_i_1_n_0), .Q(\oclkdelay_ref_cnt_reg[13]_0 ), .R(rstdiv0_sync_r1_reg_rep__12)); LUT5 #( .INIT(32'h0000AAEA)) oclkdelay_int_ref_req_i_1 (.I0(oclkdelay_int_ref_req_reg_0), .I1(oclkdelay_int_ref_req_i_2_n_0), .I2(oclkdelay_ref_cnt_reg[0]), .I3(oclkdelay_int_ref_req_i_3_n_0), .I4(oclkdelay_int_ref_req0), .O(oclkdelay_int_ref_req_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000001)) oclkdelay_int_ref_req_i_2 (.I0(oclkdelay_ref_cnt_reg[12]), .I1(oclkdelay_ref_cnt_reg[8]), .I2(oclkdelay_ref_cnt_reg[11]), .I3(oclkdelay_ref_cnt_reg[13]), .I4(oclkdelay_ref_cnt_reg[10]), .I5(oclkdelay_ref_cnt_reg[9]), .O(oclkdelay_int_ref_req_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) oclkdelay_int_ref_req_i_3 (.I0(oclkdelay_ref_cnt_reg[5]), .I1(oclkdelay_ref_cnt_reg[4]), .I2(oclkdelay_ref_cnt_reg[6]), .I3(oclkdelay_int_ref_req_i_5_n_0), .O(oclkdelay_int_ref_req_i_3_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF4)) oclkdelay_int_ref_req_i_4 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .I2(ocal_last_byte_done), .I3(oclkdelay_center_calib_done_r_reg_0), .I4(rstdiv0_sync_r1_reg_rep__24), .I5(oclkdelay_calib_done_r_reg_2), .O(oclkdelay_int_ref_req0)); LUT4 #( .INIT(16'hFFFE)) oclkdelay_int_ref_req_i_5 (.I0(oclkdelay_ref_cnt_reg[1]), .I1(oclkdelay_ref_cnt_reg[3]), .I2(oclkdelay_ref_cnt_reg[7]), .I3(oclkdelay_ref_cnt_reg[2]), .O(oclkdelay_int_ref_req_i_5_n_0)); FDRE oclkdelay_int_ref_req_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_int_ref_req_i_1_n_0), .Q(oclkdelay_int_ref_req_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hEEEEEFEEEEEEEEEE)) \oclkdelay_ref_cnt[0]_i_1 (.I0(prbs_rdlvl_done_reg_0), .I1(\cnt_init_mr_r_reg[1]_0 ), .I2(oclkdelay_int_ref_req_i_3_n_0), .I3(\oclkdelay_ref_cnt_reg[13]_0 ), .I4(oclkdelay_ref_cnt_reg[0]), .I5(oclkdelay_int_ref_req_i_2_n_0), .O(\oclkdelay_ref_cnt[0]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_4 (.I0(oclkdelay_ref_cnt_reg[3]), .O(\oclkdelay_ref_cnt[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_5 (.I0(oclkdelay_ref_cnt_reg[2]), .O(\oclkdelay_ref_cnt[0]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_6 (.I0(oclkdelay_ref_cnt_reg[1]), .O(\oclkdelay_ref_cnt[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[0]_i_7 (.I0(oclkdelay_ref_cnt_reg[0]), .O(\oclkdelay_ref_cnt[0]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[12]_i_2 (.I0(oclkdelay_ref_cnt_reg[13]), .O(\oclkdelay_ref_cnt[12]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[12]_i_3 (.I0(oclkdelay_ref_cnt_reg[12]), .O(\oclkdelay_ref_cnt[12]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_2 (.I0(oclkdelay_ref_cnt_reg[7]), .O(\oclkdelay_ref_cnt[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_3 (.I0(oclkdelay_ref_cnt_reg[6]), .O(\oclkdelay_ref_cnt[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_4 (.I0(oclkdelay_ref_cnt_reg[5]), .O(\oclkdelay_ref_cnt[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[4]_i_5 (.I0(oclkdelay_ref_cnt_reg[4]), .O(\oclkdelay_ref_cnt[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_2 (.I0(oclkdelay_ref_cnt_reg[11]), .O(\oclkdelay_ref_cnt[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_3 (.I0(oclkdelay_ref_cnt_reg[10]), .O(\oclkdelay_ref_cnt[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_4 (.I0(oclkdelay_ref_cnt_reg[9]), .O(\oclkdelay_ref_cnt[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \oclkdelay_ref_cnt[8]_i_5 (.I0(oclkdelay_ref_cnt_reg[8]), .O(\oclkdelay_ref_cnt[8]_i_5_n_0 )); FDRE \oclkdelay_ref_cnt_reg[0] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_7 ), .Q(oclkdelay_ref_cnt_reg[0]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[0]_i_2 (.CI(1'b0), .CO({\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_1 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_2 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ,\oclkdelay_ref_cnt_reg[0]_i_2_n_7 }), .S({\oclkdelay_ref_cnt[0]_i_4_n_0 ,\oclkdelay_ref_cnt[0]_i_5_n_0 ,\oclkdelay_ref_cnt[0]_i_6_n_0 ,\oclkdelay_ref_cnt[0]_i_7_n_0 })); FDSE \oclkdelay_ref_cnt_reg[10] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ), .Q(oclkdelay_ref_cnt_reg[10]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDRE \oclkdelay_ref_cnt_reg[11] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ), .Q(oclkdelay_ref_cnt_reg[11]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[12] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[12]_i_1_n_7 ), .Q(oclkdelay_ref_cnt_reg[12]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[12]_i_1 (.CI(\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ), .CO({\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED [3:1],\oclkdelay_ref_cnt_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED [3:2],\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ,\oclkdelay_ref_cnt_reg[12]_i_1_n_7 }), .S({1'b0,1'b0,\oclkdelay_ref_cnt[12]_i_2_n_0 ,\oclkdelay_ref_cnt[12]_i_3_n_0 })); FDSE \oclkdelay_ref_cnt_reg[13] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ), .Q(oclkdelay_ref_cnt_reg[13]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[1] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ), .Q(oclkdelay_ref_cnt_reg[1]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[2] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ), .Q(oclkdelay_ref_cnt_reg[2]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[3] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ), .Q(oclkdelay_ref_cnt_reg[3]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[4] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_7 ), .Q(oclkdelay_ref_cnt_reg[4]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[4]_i_1 (.CI(\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ), .CO({\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_1 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_2 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ,\oclkdelay_ref_cnt_reg[4]_i_1_n_7 }), .S({\oclkdelay_ref_cnt[4]_i_2_n_0 ,\oclkdelay_ref_cnt[4]_i_3_n_0 ,\oclkdelay_ref_cnt[4]_i_4_n_0 ,\oclkdelay_ref_cnt[4]_i_5_n_0 })); FDSE \oclkdelay_ref_cnt_reg[5] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ), .Q(oclkdelay_ref_cnt_reg[5]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDRE \oclkdelay_ref_cnt_reg[6] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ), .Q(oclkdelay_ref_cnt_reg[6]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[7] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ), .Q(oclkdelay_ref_cnt_reg[7]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); FDSE \oclkdelay_ref_cnt_reg[8] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_7 ), .Q(oclkdelay_ref_cnt_reg[8]), .S(\oclkdelay_ref_cnt[0]_i_1_n_0 )); CARRY4 \oclkdelay_ref_cnt_reg[8]_i_1 (.CI(\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ), .CO({\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_1 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_2 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ,\oclkdelay_ref_cnt_reg[8]_i_1_n_7 }), .S({\oclkdelay_ref_cnt[8]_i_2_n_0 ,\oclkdelay_ref_cnt[8]_i_3_n_0 ,\oclkdelay_ref_cnt[8]_i_4_n_0 ,\oclkdelay_ref_cnt[8]_i_5_n_0 })); FDRE \oclkdelay_ref_cnt_reg[9] (.C(CLK), .CE(\oclkdelay_ref_cnt_reg[13]_0 ), .D(\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ), .Q(oclkdelay_ref_cnt_reg[9]), .R(\oclkdelay_ref_cnt[0]_i_1_n_0 )); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[4]_srl5 " *) SRL16E \oclkdelay_start_dly_r_reg[4]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(oclkdelay_calib_start_pre), .Q(\oclkdelay_start_dly_r_reg[4]_srl5_n_0 )); LUT6 #( .INIT(64'h0000000020000000)) \oclkdelay_start_dly_r_reg[4]_srl5_i_1 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(Q[2]), .I4(\init_state_r_reg_n_0_[3] ), .I5(prbs_rdlvl_start_i_2_n_0), .O(oclkdelay_calib_start_pre)); FDRE \oclkdelay_start_dly_r_reg[5] (.C(CLK), .CE(1'b1), .D(\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ), .Q(oclkdelay_start_dly_r), .R(1'b0)); LUT3 #( .INIT(8'h02)) \odd_cwl.phy_cas_n[1]_i_1 (.I0(\odd_cwl.phy_cas_n_reg[1]_0 ), .I1(\odd_cwl.phy_ras_n[1]_i_2_n_0 ), .I2(\cnt_init_mr_r_reg[1]_0 ), .O(\odd_cwl.phy_cas_n[1]_i_1_n_0 )); FDRE \odd_cwl.phy_cas_n_reg[1] (.C(CLK), .CE(1'b1), .D(\odd_cwl.phy_cas_n[1]_i_1_n_0 ), .Q(phy_cas_n), .R(1'b0)); LUT2 #( .INIT(4'h1)) \odd_cwl.phy_ras_n[1]_i_1 (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ), .I1(\odd_cwl.phy_ras_n[1]_i_2_n_0 ), .O(\odd_cwl.phy_ras_n[1]_i_1_n_0 )); LUT6 #( .INIT(64'hEEEEEEEEEEEEEEEF)) \odd_cwl.phy_ras_n[1]_i_2 (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ), .I1(reg_ctrl_cnt_r), .I2(Q[5]), .I3(Q[4]), .I4(Q[3]), .I5(read_calib_reg_0), .O(\odd_cwl.phy_ras_n[1]_i_2_n_0 )); FDRE \odd_cwl.phy_ras_n_reg[1] (.C(CLK), .CE(1'b1), .D(\odd_cwl.phy_ras_n[1]_i_1_n_0 ), .Q(phy_ras_n), .R(1'b0)); LUT3 #( .INIT(8'h04)) \odd_cwl.phy_we_n[1]_i_1 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ), .I1(\calib_cmd[2]_i_2_n_0 ), .I2(\odd_cwl.phy_ras_n[1]_i_2_n_0 ), .O(\odd_cwl.phy_we_n[1]_i_1_n_0 )); FDRE \odd_cwl.phy_we_n_reg[1] (.C(CLK), .CE(1'b1), .D(\odd_cwl.phy_we_n[1]_i_1_n_0 ), .Q(phy_we_n), .R(1'b0)); LUT6 #( .INIT(64'h000000000000000E)) \one_rank.stg1_wr_done_i_1 (.I0(\one_rank.stg1_wr_done_reg_0 ), .I1(stg1_wr_done), .I2(\reg_ctrl_cnt_r_reg[3]_0 ), .I3(rdlvl_last_byte_done), .I4(prbs_rdlvl_done_pulse), .I5(complex_byte_rd_done), .O(\one_rank.stg1_wr_done_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \one_rank.stg1_wr_done_i_2 (.I0(Q[1]), .I1(Q[3]), .I2(Q[0]), .I3(Q[5]), .I4(Q[4]), .I5(\init_state_r[4]_i_5_n_0 ), .O(stg1_wr_done)); FDRE \one_rank.stg1_wr_done_reg (.C(CLK), .CE(1'b1), .D(\one_rank.stg1_wr_done_i_1_n_0 ), .Q(\one_rank.stg1_wr_done_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000000E0E0E)) \one_rank_complex.complex_wr_done_i_1 (.I0(complex_wr_done), .I1(\one_rank_complex.complex_wr_done_i_2_n_0 ), .I2(\one_rank_complex.complex_wr_done_i_3_n_0 ), .I3(prbs_rdlvl_done_reg), .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I5(\one_rank_complex.complex_wr_done_i_4_n_0 ), .O(\one_rank_complex.complex_wr_done_i_1_n_0 )); LUT6 #( .INIT(64'h0000800000000000)) \one_rank_complex.complex_wr_done_i_2 (.I0(\one_rank_complex.complex_wr_done_i_5_n_0 ), .I1(complex_wait_cnt_reg__0[2]), .I2(complex_wait_cnt_reg__0[3]), .I3(complex_row1_wr_done), .I4(complex_wait_cnt_reg__0[1]), .I5(complex_wait_cnt_reg__0[0]), .O(\one_rank_complex.complex_wr_done_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000080000)) \one_rank_complex.complex_wr_done_i_3 (.I0(complex_byte_rd_done), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[0]), .I4(Q[2]), .I5(complex_oclkdelay_calib_start_int_i_2_n_0), .O(\one_rank_complex.complex_wr_done_i_3_n_0 )); LUT3 #( .INIT(8'hFE)) \one_rank_complex.complex_wr_done_i_4 (.I0(\reg_ctrl_cnt_r_reg[3]_0 ), .I1(rdlvl_last_byte_done), .I2(prbs_rdlvl_done_pulse), .O(\one_rank_complex.complex_wr_done_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair516" *) LUT5 #( .INIT(32'h00001800)) \one_rank_complex.complex_wr_done_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[2]), .I4(complex_oclkdelay_calib_start_int_i_2_n_0), .O(\one_rank_complex.complex_wr_done_i_5_n_0 )); FDRE \one_rank_complex.complex_wr_done_reg (.C(CLK), .CE(1'b1), .D(\one_rank_complex.complex_wr_done_i_1_n_0 ), .Q(complex_wr_done), .R(1'b0)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [231]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [7]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [239]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [7]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [247]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [7]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_10__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [254]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [15]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [199]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [6]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [207]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [6]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [215]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [6]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_11__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [222]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [14]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [167]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [5]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [175]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [5]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [183]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [5]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_12__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [190]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [13]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [5])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_13__2 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [3]), .I4(\my_empty_reg[1]_1 ), .O(D5[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [135]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [4]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [143]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [4]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [151]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [4]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_13__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [158]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [12]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [4])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_14__1 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [2]), .I4(\my_empty_reg[1]_1 ), .O(D5[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [103]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [3]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [111]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [3]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [119]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [3]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_14__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [126]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [11]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_14__6 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [3]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [3])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_15__0 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [1]), .I4(\my_empty_reg[1]_1 ), .O(D5[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [26]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [2]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [71]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [2]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [79]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [2]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [87]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [2]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_15__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [94]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [10]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [2])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_16__0 (.I0(mc_odt), .I1(init_calib_complete_reg_rep__6), .I2(calib_odt), .I3(\rd_ptr_reg[3]_0 [0]), .I4(\my_empty_reg[1]_1 ), .O(D5[0])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_16__1 (.I0(mc_we_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_we_n), .I3(mem_out[1]), .I4(\my_empty_reg[1]_0 ), .O(D1)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__2 (.I0(\cmd_pipe_plus.mc_address_reg[42] [15]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [1]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [39]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [1]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [47]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [1]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [55]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [1]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_16__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [62]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [9]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [5]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [0]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7] [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [7]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [0]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_13 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [15]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [0]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_21 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [23]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [0]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_29 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_17__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [30]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [8]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_36 [0])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_18__2 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_cas_n), .I3(\rd_ptr_reg[3] [0]), .I4(\my_empty_reg[1] ), .O(D2)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [230]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [15]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [238]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [15]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [246]), .I1(phy_wrdata[254]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [15]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_18__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [253]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [23]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [7])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_19__1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [7]), .I4(\my_empty_reg[1]_1 ), .O(D6[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [198]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [14]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [206]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [14]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [214]), .I1(phy_wrdata[222]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [14]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_19__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [221]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [22]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [6])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_20__1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [6]), .I4(\my_empty_reg[1]_1 ), .O(D6[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [166]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [13]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [174]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [13]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [182]), .I1(phy_wrdata[190]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [13]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_20__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [189]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [21]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [5])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_21__1 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [5]), .I4(\my_empty_reg[1]_1 ), .O(D6[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [134]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [12]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [142]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [12]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [150]), .I1(phy_wrdata[158]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [12]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_21__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [157]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [20]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [4])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_22__0 (.I0(mc_cke), .I1(init_calib_complete_reg_rep__6), .I2(calib_cke), .I3(\rd_ptr_reg[3]_0 [4]), .I4(\my_empty_reg[1]_1 ), .O(D6[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [102]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [11]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [110]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [11]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [118]), .I1(phy_wrdata[126]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [11]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_22__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [125]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [19]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_22__5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [7]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [27]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [6]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [70]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [10]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [78]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [10]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [86]), .I1(phy_wrdata[94]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [10]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_23__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [93]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [18]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [16]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [5]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [38]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [9]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [46]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [9]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [54]), .I1(phy_wrdata[62]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [9]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_24__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [61]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [17]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [6]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [4]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_0 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [6]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [8]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_12 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [14]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [8]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_20 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [22]), .I1(phy_wrdata[30]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [8]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_28 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_25__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [29]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [16]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_35 [0])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_26__1 (.I0(mc_ras_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_ras_n), .I3(\rd_ptr_reg[3] [1]), .I4(\my_empty_reg[1] ), .O(D3)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [229]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [23]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [237]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [23]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [245]), .I1(phy_wrdata[253]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [23]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_26__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [252]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [31]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [197]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [22]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [205]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [22]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [213]), .I1(phy_wrdata[221]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [22]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_27__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [220]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [30]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [165]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [21]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [173]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [21]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [181]), .I1(phy_wrdata[189]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [21]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_28__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [188]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [29]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [133]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [20]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [141]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [20]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [149]), .I1(phy_wrdata[157]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [20]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_29__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [156]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [28]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_2__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [255]), .I1(phy_wrdata[255]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [7]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [101]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [19]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [109]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [19]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [117]), .I1(phy_wrdata[125]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [19]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_30__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [124]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [27]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_30__5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [11]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [28]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [10]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [69]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [18]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [77]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [18]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [85]), .I1(phy_wrdata[93]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [18]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_31__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [92]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [26]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32 (.I0(\cmd_pipe_plus.mc_address_reg[42] [17]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [9]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [37]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [17]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [45]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [17]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [53]), .I1(phy_wrdata[61]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [17]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_32__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [60]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [25]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_32__4 (.I0(phy_bank[9]), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3] [5]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33 (.I0(\cmd_pipe_plus.mc_address_reg[42] [7]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [8]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_1 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [6]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [4]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [5]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [16]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_11 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [13]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [16]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_19 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [21]), .I1(phy_wrdata[29]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [16]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_27 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_33__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [28]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [24]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_34 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [3]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [3]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [228]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [31]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [236]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [31]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [244]), .I1(phy_wrdata[252]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [31]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_34__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [251]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [39]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [0]), .I1(phy_bank[9]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [2]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_2 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [196]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [30]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [204]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [30]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [212]), .I1(phy_wrdata[220]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [30]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_35__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [219]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [38]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [164]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [29]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [172]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [29]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [180]), .I1(phy_wrdata[188]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [29]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_36__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [187]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [37]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [5])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_36__4 (.I0(phy_bank[11]), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3] [13]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [8]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [12]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [132]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [28]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [140]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [28]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [148]), .I1(phy_wrdata[156]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [28]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_37__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [155]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [36]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [5]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [11]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [100]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [27]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [108]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [27]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [116]), .I1(phy_wrdata[124]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [27]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_38__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [123]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [35]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_38__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [15]), .I3(\my_empty_reg[1]_2 ), .O(D4[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39 (.I0(\cmd_pipe_plus.mc_address_reg[42] [29]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [14]), .I4(\my_empty_reg[1]_2 ), .O(D4[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__0 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [2]), .I1(phy_bank[11]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [10]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [68]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [26]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [76]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [26]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [84]), .I1(phy_wrdata[92]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [26]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_39__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [91]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [34]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_3__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [223]), .I1(phy_wrdata[223]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [6]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40 (.I0(\cmd_pipe_plus.mc_address_reg[42] [18]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [13]), .I4(\my_empty_reg[1]_2 ), .O(D4[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [36]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [25]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [44]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [25]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [52]), .I1(phy_wrdata[60]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [25]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_40__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [59]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [33]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [1])); (* SOFT_HLUTNM = "soft_lutpair554" *) LUT4 #( .INIT(16'hEEF0)) out_fifo_i_40__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [9]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41 (.I0(\cmd_pipe_plus.mc_address_reg[42] [8]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [12]), .I4(\my_empty_reg[1]_2 ), .O(D4[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [25]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [8]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [4]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [24]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_10 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [12]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [24]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_18 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [20]), .I1(phy_wrdata[28]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [24]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_26 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_41__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [27]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [32]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_33 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [14]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [7]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [227]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [39]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [235]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [39]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [243]), .I1(phy_wrdata[251]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [39]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_42__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [250]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [47]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [4]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [6]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_1 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [195]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [38]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [203]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [38]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [211]), .I1(phy_wrdata[219]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [38]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_43__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [218]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [46]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [163]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [37]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [171]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [37]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [179]), .I1(phy_wrdata[187]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [37]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_44__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [186]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [45]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [5])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_44__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [21]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [21]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [20]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [131]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [36]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [139]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [36]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [147]), .I1(phy_wrdata[155]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [36]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_45__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [154]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [44]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [19]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [99]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [35]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [107]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [35]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [115]), .I1(phy_wrdata[123]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [35]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_46__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [122]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [43]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [3])); (* SOFT_HLUTNM = "soft_lutpair558" *) LUT4 #( .INIT(16'hEEF0)) out_fifo_i_46__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3]_1 [19]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47 (.I0(\cmd_pipe_plus.mc_address_reg[42] [0]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [18]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [30]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [18]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [67]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [34]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [75]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [34]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [83]), .I1(phy_wrdata[91]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [34]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_47__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [90]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [42]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48 (.I0(\cmd_pipe_plus.mc_address_reg[42] [19]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [17]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [35]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [33]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [43]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [33]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [51]), .I1(phy_wrdata[59]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [33]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_48__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [58]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [41]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_48__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [17]), .I3(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49 (.I0(\cmd_pipe_plus.mc_address_reg[42] [9]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [16]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_2 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [22]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [16]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [3]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [32]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_9 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [11]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [32]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_17 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [19]), .I1(phy_wrdata[27]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [32]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_25 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_49__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [26]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [40]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_32 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_4__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [191]), .I1(phy_wrdata[191]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [5]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__0 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [15]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [226]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [47]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [234]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [47]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [242]), .I1(phy_wrdata[250]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [47]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_50__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [249]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [55]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [1]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [14]), .I4(\my_empty_reg[1] ), .O(\rd_ptr_timing_reg[0]_0 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [194]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [46]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [202]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [46]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [210]), .I1(phy_wrdata[218]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [46]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_51__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [217]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [54]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [162]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [45]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [170]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [45]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [178]), .I1(phy_wrdata[186]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [45]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_52__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [185]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [53]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [130]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [44]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [138]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [44]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [146]), .I1(phy_wrdata[154]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [44]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_53__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [153]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [52]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [98]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [43]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [106]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [43]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [114]), .I1(phy_wrdata[122]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [43]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_54__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [121]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [51]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_54__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3]_1 [23]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [31]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [22]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [66]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [42]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [74]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [42]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [82]), .I1(phy_wrdata[90]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [42]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_55__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [89]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [50]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56 (.I0(\cmd_pipe_plus.mc_address_reg[42] [20]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [21]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [34]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [41]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [42]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [41]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [50]), .I1(phy_wrdata[58]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [41]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_56__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [57]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [49]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_56__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [25]), .I3(\my_empty_reg[1] ), .O(D7[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57 (.I0(\cmd_pipe_plus.mc_address_reg[42] [10]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [20]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_3 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [23]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [24]), .I4(\my_empty_reg[1] ), .O(D7[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [2]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [40]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_8 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [10]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [40]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_16 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [18]), .I1(phy_wrdata[26]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [40]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_24 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_57__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [25]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [48]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_31 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__0 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [23]), .I4(\my_empty_reg[1] ), .O(D7[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [225]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [55]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [233]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [55]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [241]), .I1(phy_wrdata[249]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [55]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_58__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [248]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [63]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [2]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [22]), .I4(\my_empty_reg[1] ), .O(D7[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [193]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [54]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [201]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [54]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [209]), .I1(phy_wrdata[217]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [54]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_59__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [216]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_5 [62]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_5__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [159]), .I1(phy_wrdata[159]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [4]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [161]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [53]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [169]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [53]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [177]), .I1(phy_wrdata[185]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [53]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_60__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [184]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_5 [61]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [129]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [52]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [137]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [52]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [145]), .I1(phy_wrdata[153]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [52]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_61__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [152]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [60]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [97]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [51]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [105]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [51]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [113]), .I1(phy_wrdata[121]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [51]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_62__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [120]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [59]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_62__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3]_1 [27]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [32]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [26]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [65]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [50]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [73]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [50]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [81]), .I1(phy_wrdata[89]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [50]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_63__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [88]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [58]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64 (.I0(mc_cas_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [25]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [33]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [49]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [41]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [49]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [49]), .I1(phy_wrdata[57]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [49]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_64__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [56]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [57]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [1])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_64__4 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I1(init_calib_complete_reg_rep__0), .I2(\rd_ptr_reg[3] [29]), .I3(\my_empty_reg[1] ), .O(D8[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65 (.I0(\cmd_pipe_plus.mc_address_reg[42] [11]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [24]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_4 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [24]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [28]), .I4(\my_empty_reg[1] ), .O(D8[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [1]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [48]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_7 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [9]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [48]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_15 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [17]), .I1(phy_wrdata[25]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [48]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_23 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_65__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [24]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [56]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_30 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [13]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [27]), .I4(\my_empty_reg[1] ), .O(D8[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [224]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_2 [63]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [232]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_3 [63]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_66__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [240]), .I1(phy_wrdata[248]), .I2(init_calib_complete_reg_rep__0), .I3(\rd_ptr_reg[3]_4 [63]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [7])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__1 (.I0(\cmd_pipe_plus.mc_address_reg[42] [3]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3] [26]), .I4(\my_empty_reg[1] ), .O(D8[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [192]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_2 [62]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [200]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [62]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_67__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [208]), .I1(phy_wrdata[216]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [62]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [6])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_68__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [160]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [61]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_68__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [168]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_3 [61]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_68__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [176]), .I1(phy_wrdata[184]), .I2(init_calib_complete_reg_rep__1), .I3(\rd_ptr_reg[3]_4 [61]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [5])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_69__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [128]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_2 [60]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_69__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [136]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_3 [60]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_69__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [144]), .I1(phy_wrdata[152]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_4 [60]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [4])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_6__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [127]), .I1(phy_wrdata[127]), .I2(init_calib_complete_reg_rep__2), .I3(\rd_ptr_reg[3]_5 [3]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_70__0 (.I0(\write_buffer.wr_buf_out_data_reg[255] [96]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_2 [59]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_70__1 (.I0(\write_buffer.wr_buf_out_data_reg[255] [104]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [59]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_70__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [112]), .I1(phy_wrdata[120]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [59]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_70__3 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3]_1 [31]), .I3(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [3])); LUT4 #( .INIT(16'hEEF0)) out_fifo_i_70__4 (.I0(phy_bank[10]), .I1(init_calib_complete_reg_rep), .I2(\rd_ptr_reg[3] [33]), .I3(\my_empty_reg[1] ), .O(D9[3])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [33]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [30]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__1 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [7]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [32]), .I4(\my_empty_reg[1] ), .O(D9[2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [64]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [58]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [72]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_3 [58]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_71__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [80]), .I1(phy_wrdata[88]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_4 [58]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [2])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__0 (.I0(mc_ras_n), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_1 [29]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__1 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [4]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [31]), .I4(\my_empty_reg[1] ), .O(D9[1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [32]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_2 [57]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [40]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_3 [57]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_72__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [48]), .I1(phy_wrdata[56]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [57]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__0 (.I0(\cmd_pipe_plus.mc_address_reg[42] [12]), .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ), .I2(init_calib_complete_reg_rep__6), .I3(\rd_ptr_reg[3]_1 [28]), .I4(\my_empty_reg[1]_2 ), .O(\my_empty_reg[7]_5 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__1 (.I0(\cmd_pipe_plus.mc_bank_reg[8] [1]), .I1(phy_bank[10]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3] [30]), .I4(\my_empty_reg[1] ), .O(D9[0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__2 (.I0(\write_buffer.wr_buf_out_data_reg[255] [0]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_2 [56]), .I4(\my_empty_reg[1]_3 ), .O(\my_empty_reg[7]_6 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__3 (.I0(\write_buffer.wr_buf_out_data_reg[255] [8]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__5), .I3(\rd_ptr_reg[3]_3 [56]), .I4(\my_empty_reg[1]_4 ), .O(\my_empty_reg[7]_14 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_73__4 (.I0(\write_buffer.wr_buf_out_data_reg[255] [16]), .I1(phy_wrdata[24]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_4 [56]), .I4(\my_empty_reg[1]_5 ), .O(\my_empty_reg[7]_22 [0])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_7__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [95]), .I1(phy_wrdata[95]), .I2(init_calib_complete_reg_rep__3), .I3(\rd_ptr_reg[3]_5 [2]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [2])); LUT5 #( .INIT(32'hB8B8FF00)) out_fifo_i_8__5 (.I0(mc_cas_n), .I1(init_calib_complete_reg_rep__6), .I2(phy_cs_n), .I3(mem_out[0]), .I4(\my_empty_reg[1]_0 ), .O(D0)); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_8__6 (.I0(\write_buffer.wr_buf_out_data_reg[255] [63]), .I1(phy_wrdata[63]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [1]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [1])); LUT5 #( .INIT(32'hACACFF00)) out_fifo_i_9__5 (.I0(\write_buffer.wr_buf_out_data_reg[255] [31]), .I1(phy_wrdata[31]), .I2(init_calib_complete_reg_rep__4), .I3(\rd_ptr_reg[3]_5 [0]), .I4(\my_empty_reg[1]_6 ), .O(\my_empty_reg[7]_37 [0])); (* SOFT_HLUTNM = "soft_lutpair591" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[0]_i_1 (.I0(mc_cmd[0]), .I1(calib_cmd[0]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [0])); (* SOFT_HLUTNM = "soft_lutpair592" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[17]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[0] ), .I1(calib_data_offset_0[0]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [3])); (* SOFT_HLUTNM = "soft_lutpair593" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[18]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[1] ), .I1(calib_data_offset_0[1]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [4])); (* SOFT_HLUTNM = "soft_lutpair594" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[19]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[2] ), .I1(calib_data_offset_0[2]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [5])); (* SOFT_HLUTNM = "soft_lutpair588" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[1]_i_1 (.I0(mc_cmd[1]), .I1(calib_cmd[1]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [1])); (* SOFT_HLUTNM = "soft_lutpair593" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[20]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ), .I1(calib_data_offset_0[3]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [6])); (* SOFT_HLUTNM = "soft_lutpair596" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[21]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[4] ), .I1(calib_data_offset_0[4]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [7])); (* SOFT_HLUTNM = "soft_lutpair594" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[22]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] ), .I1(calib_data_offset_0[5]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [8])); (* SOFT_HLUTNM = "soft_lutpair592" *) LUT3 #( .INIT(8'hAC)) \phy_ctl_wd_i1[2]_i_1 (.I0(mc_cas_n), .I1(calib_cmd[2]), .I2(init_calib_complete_reg_rep__14), .O(\phy_ctl_wd_i1_reg[24] [2])); FDCE phy_reset_n_reg (.C(CLK), .CE(1'b1), .CLR(rstdiv0_sync_r1_reg_rep__11), .D(cnt_pwron_reset_done_r), .Q(phy_reset_n)); FDRE pi_calib_done_r1_reg (.C(CLK), .CE(1'b1), .D(pi_calib_done_r), .Q(pi_calib_done), .R(1'b0)); LUT2 #( .INIT(4'hE)) pi_calib_done_r_i_1 (.I0(pi_calib_rank_done_r), .I1(pi_calib_done_r), .O(pi_calib_done_r_i_1_n_0)); FDRE pi_calib_done_r_reg (.C(CLK), .CE(1'b1), .D(pi_calib_done_r_i_1_n_0), .Q(pi_calib_done_r), .R(rstdiv0_sync_r1_reg_rep__11)); LUT2 #( .INIT(4'h2)) pi_calib_rank_done_r_i_1 (.I0(pi_phase_locked_all_r3), .I1(pi_phase_locked_all_r4), .O(init_next_state1100_out)); FDRE pi_calib_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(init_next_state1100_out), .Q(pi_calib_rank_done_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'hE)) \pi_dqs_found_all_bank[1]_i_2 (.I0(dqs_found_start_r_reg), .I1(\pi_dqs_found_all_bank_reg[1]_0 ), .O(\pi_dqs_found_all_bank_reg[1] )); FDRE pi_dqs_found_done_r1_reg (.C(CLK), .CE(1'b1), .D(dqs_found_done_r_reg), .Q(pi_dqs_found_done_r1), .R(rstdiv0_sync_r1_reg_rep__11)); LUT5 #( .INIT(32'h000000AE)) pi_dqs_found_start_i_1 (.I0(dqs_found_start_r_reg), .I1(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ), .I2(dqs_found_done_r_reg), .I3(wrlvl_byte_redo), .I4(rstdiv0_sync_r1_reg_rep__24), .O(pi_dqs_found_start_i_1_n_0)); FDRE pi_dqs_found_start_reg (.C(CLK), .CE(1'b1), .D(pi_dqs_found_start_i_1_n_0), .Q(dqs_found_start_r_reg), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE pi_phase_locked_all_r1_reg (.C(CLK), .CE(1'b1), .D(A_rst_primitives_reg), .Q(pi_phase_locked_all_r1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE pi_phase_locked_all_r2_reg (.C(CLK), .CE(1'b1), .D(pi_phase_locked_all_r1), .Q(pi_phase_locked_all_r2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE pi_phase_locked_all_r3_reg (.C(CLK), .CE(1'b1), .D(pi_phase_locked_all_r2), .Q(pi_phase_locked_all_r3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE pi_phase_locked_all_r4_reg (.C(CLK), .CE(1'b1), .D(pi_phase_locked_all_r3), .Q(pi_phase_locked_all_r4), .R(1'b0)); LUT6 #( .INIT(64'h00000000FFFFEEFE)) prbs_gen_clk_en_i_1 (.I0(prbs_gen_clk_en), .I1(prbs_gen_clk_en_i_2_n_0), .I2(prbs_rdlvl_start_r_reg), .I3(prbs_gen_clk_en_i_3_n_0), .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I5(prbs_gen_clk_en040_out), .O(prbs_gen_clk_en_i_1_n_0)); LUT6 #( .INIT(64'h20AAAAAA20AA20AA)) prbs_gen_clk_en_i_2 (.I0(rdlvl_stg1_done_r1), .I1(prbs_gen_clk_en_i_5_n_0), .I2(\complex_num_writes[3]_i_4_n_0 ), .I3(phy_if_empty_r_reg), .I4(\stg1_wr_rd_cnt[4]_i_6_n_0 ), .I5(cnt_cmd_done_r_i_1_n_0), .O(prbs_gen_clk_en_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFEF)) prbs_gen_clk_en_i_3 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[4]), .I2(Q[3]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(prbs_gen_clk_en_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair552" *) LUT4 #( .INIT(16'hEEEF)) prbs_gen_clk_en_i_4 (.I0(prbs_rdlvl_done_reg), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(wr_victim_inc_i_2_n_0), .I3(\one_rank.stg1_wr_done_reg_0 ), .O(prbs_gen_clk_en040_out)); (* SOFT_HLUTNM = "soft_lutpair508" *) LUT4 #( .INIT(16'hFF7F)) prbs_gen_clk_en_i_5 (.I0(complex_wait_cnt_reg__0[2]), .I1(complex_wait_cnt_reg__0[3]), .I2(complex_wait_cnt_reg__0[1]), .I3(complex_wait_cnt_reg__0[0]), .O(prbs_gen_clk_en_i_5_n_0)); FDRE prbs_gen_clk_en_reg (.C(CLK), .CE(1'b1), .D(prbs_gen_clk_en_i_1_n_0), .Q(prbs_gen_clk_en), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000002)) prbs_gen_oclk_clk_en_i_1 (.I0(prbs_gen_oclk_clk_en_i_2_n_0), .I1(prbs_gen_oclk_clk_en_i_3_n_0), .I2(\one_rank_complex.complex_wr_done_i_3_n_0 ), .I3(prbs_gen_oclk_clk_en_i_4_n_0), .I4(prbs_gen_oclk_clk_en_i_5_n_0), .I5(prbs_gen_clk_en040_out), .O(prbs_gen_oclk_clk_en_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFAE)) prbs_gen_oclk_clk_en_i_2 (.I0(prbs_gen_oclk_clk_en_i_6_n_0), .I1(prbs_rdlvl_done_r1), .I2(phy_if_empty_r_reg), .I3(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I4(prbs_gen_oclk_clk_en_i_7_n_0), .I5(prbs_gen_oclk_clk_en), .O(prbs_gen_oclk_clk_en_i_2_n_0)); LUT6 #( .INIT(64'h0000000000002000)) prbs_gen_oclk_clk_en_i_3 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(prbs_rdlvl_start_i_2_n_0), .O(prbs_gen_oclk_clk_en_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000008)) prbs_gen_oclk_clk_en_i_4 (.I0(prbs_gen_oclk_clk_en_i_8_n_0), .I1(\complex_num_writes_reg_n_0_[0] ), .I2(\complex_num_writes_reg_n_0_[1] ), .I3(\complex_num_writes_reg_n_0_[2] ), .I4(\complex_num_writes_reg_n_0_[4] ), .I5(\complex_num_writes_reg_n_0_[3] ), .O(prbs_gen_oclk_clk_en_i_4_n_0)); LUT6 #( .INIT(64'hAABAAAAAFFFFFFFF)) prbs_gen_oclk_clk_en_i_5 (.I0(prbs_gen_oclk_clk_en_i_9_n_0), .I1(complex_num_writes_dec_reg__0[0]), .I2(complex_num_writes_dec_reg__0[1]), .I3(\complex_num_writes_dec[4]_i_5_n_0 ), .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .I5(complex_ocal_wr_start), .O(prbs_gen_oclk_clk_en_i_5_n_0)); LUT6 #( .INIT(64'h0001101100010001)) prbs_gen_oclk_clk_en_i_6 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(\init_state_r[4]_i_5_n_0 ), .I2(Q[1]), .I3(prbs_gen_clk_en_i_5_n_0), .I4(Q[0]), .I5(complex_oclk_calib_resume), .O(prbs_gen_oclk_clk_en_i_6_n_0)); LUT5 #( .INIT(32'h00000004)) prbs_gen_oclk_clk_en_i_7 (.I0(prbs_gen_clk_en_i_5_n_0), .I1(\complex_num_writes[3]_i_4_n_0 ), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(complex_row1_wr_done), .I4(complex_ocal_num_samples_done_r), .O(prbs_gen_oclk_clk_en_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair505" *) LUT4 #( .INIT(16'h8000)) prbs_gen_oclk_clk_en_i_8 (.I0(complex_wait_cnt_reg__0[0]), .I1(complex_wait_cnt_reg__0[1]), .I2(complex_wait_cnt_reg__0[2]), .I3(complex_wait_cnt_reg__0[3]), .O(prbs_gen_oclk_clk_en_i_8_n_0)); LUT6 #( .INIT(64'h0000D00000000000)) prbs_gen_oclk_clk_en_i_9 (.I0(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .I1(complex_oclkdelay_calib_start_int_reg_0), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ), .I3(init_state_r1[2]), .I4(init_state_r1[6]), .I5(init_state_r1[1]), .O(prbs_gen_oclk_clk_en_i_9_n_0)); FDRE prbs_gen_oclk_clk_en_reg (.C(CLK), .CE(1'b1), .D(prbs_gen_oclk_clk_en_i_1_n_0), .Q(prbs_gen_oclk_clk_en), .R(1'b0)); FDRE prbs_last_byte_done_r_reg (.C(CLK), .CE(1'b1), .D(prbs_last_byte_done), .Q(prbs_last_byte_done_r), .R(1'b0)); FDRE prbs_rdlvl_done_pulse_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_pulse0), .Q(prbs_rdlvl_done_pulse), .R(1'b0)); FDRE prbs_rdlvl_done_r1_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_reg_rep), .Q(prbs_rdlvl_done_r1), .R(1'b0)); FDRE prbs_rdlvl_done_r2_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_r1), .Q(prbs_rdlvl_done_r2), .R(1'b0)); FDRE prbs_rdlvl_done_r3_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_done_r2), .Q(prbs_rdlvl_done_r3), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000020)) prbs_rdlvl_start_i_1 (.I0(rdlvl_stg1_done_int_reg), .I1(prbs_rdlvl_done_reg), .I2(dqs_found_done_r_reg), .I3(prbs_rdlvl_start_i_2_n_0), .I4(prbs_rdlvl_start_i_3_n_0), .I5(prbs_rdlvl_start_r_reg), .O(prbs_rdlvl_start_i_1_n_0)); LUT2 #( .INIT(4'h7)) prbs_rdlvl_start_i_2 (.I0(Q[0]), .I1(Q[1]), .O(prbs_rdlvl_start_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair482" *) LUT5 #( .INIT(32'hFFFEFFFF)) prbs_rdlvl_start_i_3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[5]), .O(prbs_rdlvl_start_i_3_n_0)); FDRE prbs_rdlvl_start_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_start_i_1_n_0), .Q(prbs_rdlvl_start_r_reg), .R(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'h2)) \prbs_state_r[4]_i_10 (.I0(prbs_rdlvl_start_r_reg), .I1(prbs_rdlvl_start_r), .O(new_cnt_dqs_r_reg)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 " *) SRL16E \prech_done_dly_r_reg[15]_srl16 (.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(prech_done_pre), .Q(\prech_done_dly_r_reg[15]_srl16_n_0 )); LUT2 #( .INIT(4'h2)) \prech_done_dly_r_reg[15]_srl16_i_1 (.I0(prech_pending_r_reg_1), .I1(prech_pending_r_reg_0), .O(prech_done_pre)); FDRE prech_done_r2_reg (.C(CLK), .CE(1'b1), .D(prech_done), .Q(prech_done_r2), .R(1'b0)); FDRE prech_done_r3_reg (.C(CLK), .CE(1'b1), .D(prech_done_r2), .Q(prech_done_r3), .R(1'b0)); FDRE prech_done_reg (.C(CLK), .CE(1'b1), .D(\prech_done_dly_r_reg[15]_srl16_n_0 ), .Q(prech_done), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAA8A8A8A8A8A)) prech_pending_r_i_2 (.I0(prech_pending_r), .I1(prech_pending_r_i_3_n_0), .I2(prech_pending_r_i_4_n_0), .I3(\complex_row_cnt_ocal[7]_i_6_n_0 ), .I4(prech_pending_r_i_5_n_0), .I5(prbs_last_byte_done_r), .O(prech_pending_r_reg_1)); LUT6 #( .INIT(64'hFFFFFFFFFF5D0000)) prech_pending_r_i_3 (.I0(prech_pending_r_i_6_n_0), .I1(\wrcal_reads[7]_i_6_n_0 ), .I2(first_wrcal_pat_r_i_2_n_0), .I3(prech_pending_r_i_7_n_0), .I4(cnt_cmd_done_r), .I5(prech_pending_r_i_8_n_0), .O(prech_pending_r_i_3_n_0)); LUT6 #( .INIT(64'h0000FDFFFDFFFDFF)) prech_pending_r_i_4 (.I0(dqs_found_prech_req), .I1(\init_state_r[4]_i_5_n_0 ), .I2(rdlvl_stg1_start_int_i_2_n_0), .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I4(\num_refresh[3]_i_5_n_0 ), .I5(complex_oclkdelay_calib_start_r1), .O(prech_pending_r_i_4_n_0)); LUT6 #( .INIT(64'h0000000000000008)) prech_pending_r_i_5 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(cnt_cmd_done_r), .I2(\init_state_r[4]_i_5_n_0 ), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(prech_pending_r_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) prech_pending_r_i_6 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(rdlvl_start_pre_reg_0), .I3(oclkdelay_calib_done_r_reg_2), .I4(wrlvl_final_mux), .I5(complex_oclkdelay_calib_start_int_reg_0), .O(prech_pending_r_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair492" *) LUT5 #( .INIT(32'h00000080)) prech_pending_r_i_7 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(read_calib_i_2_n_0), .O(prech_pending_r_i_7_n_0)); LUT6 #( .INIT(64'hFFFFFFFEFFFEFFFE)) prech_pending_r_i_8 (.I0(oclkdelay_calib_start_pre), .I1(prech_pending_r_i_9_n_0), .I2(stg1_wr_done), .I3(\calib_cmd[2]_i_8_n_0 ), .I4(prech_pending_r_i_5_n_0), .I5(rdlvl_last_byte_done_r), .O(prech_pending_r_i_8_n_0)); LUT6 #( .INIT(64'h0000000000040000)) prech_pending_r_i_9 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(\init_state_r_reg_n_0_[3] ), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(prech_pending_r_i_9_n_0)); FDRE prech_pending_r_reg (.C(CLK), .CE(1'b1), .D(prech_req_posedge_r_reg_0), .Q(prech_pending_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT2 #( .INIT(4'h1)) prech_req_posedge_r_i_1 (.I0(prech_req_r), .I1(prech_req_posedge_r_i_2_n_0), .O(prech_req_posedge_r0)); LUT6 #( .INIT(64'h000000000000000B)) prech_req_posedge_r_i_2 (.I0(\back_to_back_reads_4_1.num_reads_reg[1]_0 ), .I1(dqs_found_prech_req), .I2(prbs_rdlvl_prech_req_reg), .I3(complex_ocal_ref_req), .I4(wrcal_prech_req), .I5(rdlvl_prech_req), .O(prech_req_posedge_r_i_2_n_0)); FDRE prech_req_posedge_r_reg (.C(CLK), .CE(1'b1), .D(prech_req_posedge_r0), .Q(prech_pending_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFEF)) prech_req_r_i_3 (.I0(complex_oclkdelay_calib_start_int_reg_0), .I1(Q[4]), .I2(Q[3]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\back_to_back_reads_4_1.num_reads_reg[1]_0 )); FDRE prech_req_r_reg (.C(CLK), .CE(1'b1), .D(prech_req), .Q(prech_req_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT5 #( .INIT(32'h80000000)) pwron_ce_r_i_2 (.I0(cnt_pwron_ce_r_reg__0[9]), .I1(cnt_pwron_ce_r_reg__0[7]), .I2(pwron_ce_r_i_3_n_0), .I3(cnt_pwron_ce_r_reg__0[6]), .I4(cnt_pwron_ce_r_reg__0[8]), .O(pwron_ce_r_i_2_n_0)); LUT6 #( .INIT(64'h8000000000000000)) pwron_ce_r_i_3 (.I0(cnt_pwron_ce_r_reg__0[5]), .I1(cnt_pwron_ce_r_reg__0[3]), .I2(cnt_pwron_ce_r_reg__0[1]), .I3(cnt_pwron_ce_r_reg__0[0]), .I4(cnt_pwron_ce_r_reg__0[2]), .I5(cnt_pwron_ce_r_reg__0[4]), .O(pwron_ce_r_i_3_n_0)); FDRE pwron_ce_r_reg (.C(CLK), .CE(1'b1), .D(pwron_ce_r_i_2_n_0), .Q(pwron_ce_r), .R(rstdiv0_sync_r1_reg_rep__12)); LUT6 #( .INIT(64'h0000BBB0FFF0FFF0)) \rd_addr[7]_i_2 (.I0(prbs_rdlvl_done_reg_rep), .I1(prbs_rdlvl_start_r_reg), .I2(prbs_gen_clk_en), .I3(prbs_gen_oclk_clk_en), .I4(complex_wr_done), .I5(phy_if_empty_r_reg), .O(\rd_addr_reg[0] )); LUT6 #( .INIT(64'h959595AAAAAAAAAA)) \rd_addr[7]_i_7 (.I0(\rd_addr_reg[3] ), .I1(phy_if_empty_r_reg), .I2(complex_wr_done), .I3(prbs_gen_oclk_clk_en), .I4(prbs_gen_clk_en), .I5(prbs_rdlvl_done_reg_rep), .O(\rd_addr_reg_rep[7] )); FDRE rdlvl_last_byte_done_r_reg (.C(CLK), .CE(1'b1), .D(rdlvl_last_byte_done), .Q(rdlvl_last_byte_done_r), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 " *) SRL16E \rdlvl_start_dly0_r_reg[13]_srl14 (.A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b1), .CE(1'b1), .CLK(CLK), .D(rdlvl_start_pre), .Q(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 )); FDRE \rdlvl_start_dly0_r_reg[14] (.C(CLK), .CE(1'b1), .D(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ), .Q(rdlvl_start_dly0_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair585" *) LUT3 #( .INIT(8'hFB)) rdlvl_start_pre_i_2 (.I0(Q[4]), .I1(Q[3]), .I2(Q[5]), .O(rdlvl_start_pre_reg_0)); FDRE rdlvl_start_pre_reg (.C(CLK), .CE(1'b1), .D(\init_state_r_reg[0]_1 ), .Q(rdlvl_start_pre), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE rdlvl_stg1_done_r1_reg (.C(CLK), .CE(1'b1), .D(rdlvl_stg1_done_int_reg), .Q(rdlvl_stg1_done_r1), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000080)) rdlvl_stg1_start_int_i_1 (.I0(dqs_found_done_r_reg), .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I2(cnt_cmd_done_r), .I3(\init_state_r[4]_i_5_n_0 ), .I4(rdlvl_stg1_start_int_i_2_n_0), .I5(rdlvl_stg1_start_int), .O(rdlvl_stg1_start_int_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair572" *) LUT3 #( .INIT(8'hFE)) rdlvl_stg1_start_int_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .O(rdlvl_stg1_start_int_i_2_n_0)); FDRE rdlvl_stg1_start_int_reg (.C(CLK), .CE(1'b1), .D(rdlvl_stg1_start_int_i_1_n_0), .Q(rdlvl_stg1_start_int), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE rdlvl_stg1_start_reg (.C(CLK), .CE(1'b1), .D(\rdlvl_start_dly0_r_reg[14]_0 ), .Q(rdlvl_stg1_start_r_reg), .R(rstdiv0_sync_r1_reg_rep__12)); LUT5 #( .INIT(32'h000000AB)) read_calib_i_1 (.I0(phy_read_calib), .I1(read_calib_i_2_n_0), .I2(read_calib_reg_0), .I3(pi_calib_done), .I4(rstdiv0_sync_r1_reg_rep__24), .O(read_calib_i_1_n_0)); LUT3 #( .INIT(8'hFB)) read_calib_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .O(read_calib_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair507" *) LUT4 #( .INIT(16'hFDFF)) read_calib_i_3 (.I0(Q[1]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[0]), .I3(Q[2]), .O(read_calib_reg_0)); FDRE read_calib_reg (.C(CLK), .CE(1'b1), .D(read_calib_i_1_n_0), .Q(phy_read_calib), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair610" *) LUT1 #( .INIT(2'h1)) \reg_ctrl_cnt_r[0]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[0]), .O(\reg_ctrl_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair610" *) LUT2 #( .INIT(4'h6)) \reg_ctrl_cnt_r[1]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[0]), .I1(reg_ctrl_cnt_r_reg__0[1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair586" *) LUT3 #( .INIT(8'h6A)) \reg_ctrl_cnt_r[2]_i_1 (.I0(reg_ctrl_cnt_r_reg__0[2]), .I1(reg_ctrl_cnt_r_reg__0[1]), .I2(reg_ctrl_cnt_r_reg__0[0]), .O(p_0_in__2[2])); LUT6 #( .INIT(64'h0000000000000001)) \reg_ctrl_cnt_r[3]_i_1 (.I0(Q[1]), .I1(Q[4]), .I2(Q[5]), .I3(oclk_calib_resume_level_reg_0), .I4(Q[3]), .I5(Q[0]), .O(\reg_ctrl_cnt_r_reg[3]_0 )); LUT6 #( .INIT(64'h0000000001000000)) \reg_ctrl_cnt_r[3]_i_2 (.I0(prbs_rdlvl_start_i_2_n_0), .I1(Q[2]), .I2(Q[4]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[3]), .I5(Q[5]), .O(reg_ctrl_cnt_r)); (* SOFT_HLUTNM = "soft_lutpair562" *) LUT4 #( .INIT(16'h6AAA)) \reg_ctrl_cnt_r[3]_i_3 (.I0(reg_ctrl_cnt_r_reg__0[3]), .I1(reg_ctrl_cnt_r_reg__0[2]), .I2(reg_ctrl_cnt_r_reg__0[0]), .I3(reg_ctrl_cnt_r_reg__0[1]), .O(p_0_in__2[3])); FDRE \reg_ctrl_cnt_r_reg[0] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(\reg_ctrl_cnt_r[0]_i_1_n_0 ), .Q(reg_ctrl_cnt_r_reg__0[0]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); FDRE \reg_ctrl_cnt_r_reg[1] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(p_0_in__2[1]), .Q(reg_ctrl_cnt_r_reg__0[1]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); FDRE \reg_ctrl_cnt_r_reg[2] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(p_0_in__2[2]), .Q(reg_ctrl_cnt_r_reg__0[2]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); FDRE \reg_ctrl_cnt_r_reg[3] (.C(CLK), .CE(reg_ctrl_cnt_r), .D(p_0_in__2[3]), .Q(reg_ctrl_cnt_r_reg__0[3]), .R(\reg_ctrl_cnt_r_reg[3]_0 )); LUT3 #( .INIT(8'h02)) reset_if_i_1 (.I0(reset_if_i_2_n_0), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(reset_if_r9), .O(reset_if_reg)); LUT5 #( .INIT(32'hFFFF22F2)) reset_if_i_2 (.I0(rdlvl_stg1_done_int_reg), .I1(rdlvl_stg1_done_r1), .I2(prbs_rdlvl_done_reg), .I3(prbs_rdlvl_done_r1), .I4(reset_if), .O(reset_if_i_2_n_0)); FDRE reset_rd_addr_r1_reg (.C(CLK), .CE(1'b1), .D(reset_rd_addr0), .Q(reset_rd_addr_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair518" *) LUT2 #( .INIT(4'h1)) \row_cnt_victim_rotate.complex_row_cnt[0]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 )); LUT4 #( .INIT(16'h8BB8)) \row_cnt_victim_rotate.complex_row_cnt[1]_i_1 (.I0(\rd_victim_sel_reg[0] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .O(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair518" *) LUT5 #( .INIT(32'h8BB8B8B8)) \row_cnt_victim_rotate.complex_row_cnt[2]_i_1 (.I0(\rd_victim_sel_reg[1] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .O(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h8BB8B8B8B8B8B8B8)) \row_cnt_victim_rotate.complex_row_cnt[3]_i_1 (.I0(\rd_victim_sel_reg[2] ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .O(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'hEEEEFFEFAAAAAAAA)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ), .I1(reset_rd_addr_r1), .I2(complex_sample_cnt_inc_r2), .I3(complex_victim_inc_reg), .I4(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_10 (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I1(\complex_row_cnt_ocal[7]_i_7_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 )); LUT3 #( .INIT(8'h0E)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_2 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I1(\one_rank.stg1_wr_done_reg_0 ), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ), .O(complex_row_cnt)); LUT6 #( .INIT(64'h000000007FFF8000)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_3 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 )); LUT4 #( .INIT(16'hFFFB)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_4 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ), .I1(rdlvl_stg1_done_r1), .I2(rstdiv0_sync_r1_reg_rep__24), .I3(prbs_rdlvl_done_reg), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 )); LUT5 #( .INIT(32'h00000001)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_5 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I4(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair549" *) LUT2 #( .INIT(4'h2)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_6 (.I0(\one_rank.stg1_wr_done_reg_0 ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 )); LUT6 #( .INIT(64'h000000000000000B)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_7 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ), .I1(\complex_row_cnt_ocal[7]_i_6_n_0 ), .I2(reset_rd_addr_r1), .I3(complex_victim_inc_reg), .I4(wr_victim_inc), .I5(complex_sample_cnt_inc_r2), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair549" *) LUT4 #( .INIT(16'h4044)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_8 (.I0(complex_victim_inc_reg), .I1(complex_sample_cnt_inc_r2), .I2(\one_rank.stg1_wr_done_reg_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 )); LUT6 #( .INIT(64'h0000000200000000)) \row_cnt_victim_rotate.complex_row_cnt[4]_i_9 (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(wr_victim_inc), .O(\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 )); LUT6 #( .INIT(64'h00000000262A2A2A)) \row_cnt_victim_rotate.complex_row_cnt[5]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I1(complex_row_cnt), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \row_cnt_victim_rotate.complex_row_cnt[5]_i_2 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 )); LUT5 #( .INIT(32'h0000262A)) \row_cnt_victim_rotate.complex_row_cnt[6]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I1(complex_row_cnt), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000262A2A2A)) \row_cnt_victim_rotate.complex_row_cnt[7]_i_1 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .I1(complex_row_cnt), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ), .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \row_cnt_victim_rotate.complex_row_cnt[7]_i_2 (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFBBFBAAAAAAAA)) \row_cnt_victim_rotate.complex_row_cnt[7]_i_3 (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ), .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I2(complex_sample_cnt_inc_r2), .I3(complex_victim_inc_reg), .I4(reset_rd_addr_r1), .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ), .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 )); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[0] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[1] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[2] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[3] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[4] (.C(CLK), .CE(complex_row_cnt), .D(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ), .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 )); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[5] (.C(CLK), .CE(1'b1), .D(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ), .R(1'b0)); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[6] (.C(CLK), .CE(1'b1), .D(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ), .R(1'b0)); FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[7] (.C(CLK), .CE(1'b1), .D(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair560" *) LUT2 #( .INIT(4'hB)) \samples_cnt_r[11]_i_1 (.I0(complex_sample_cnt_inc), .I1(\samples_cnt_r_reg[11]_0 ), .O(\samples_cnt_r_reg[11] )); LUT3 #( .INIT(8'hBA)) \stg1_wr_rd_cnt[0]_i_1 (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .O(\stg1_wr_rd_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0D00000D0D0D0D0D)) \stg1_wr_rd_cnt[1]_i_1 (.I0(stg1_wr_done), .I1(rdlvl_stg1_done_int_reg), .I2(rstdiv0_sync_r1_reg_rep__24), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I5(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .O(\stg1_wr_rd_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair567" *) LUT4 #( .INIT(16'hFD57)) \stg1_wr_rd_cnt[2]_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\stg1_wr_rd_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00A8AAA8AAA800A8)) \stg1_wr_rd_cnt[3]_i_1 (.I0(rdlvl_stg1_done_int_reg_1), .I1(\stg1_wr_rd_cnt[3]_i_2_n_0 ), .I2(prbs_rdlvl_done_reg), .I3(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ), .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ), .O(\stg1_wr_rd_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFD0FF)) \stg1_wr_rd_cnt[3]_i_2 (.I0(complex_row0_rd_done), .I1(complex_row1_rd_done), .I2(complex_row1_wr_done), .I3(complex_row0_wr_done), .I4(wr_victim_inc), .O(\stg1_wr_rd_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h88888882AAAAAAAA)) \stg1_wr_rd_cnt[4]_i_1 (.I0(rdlvl_stg1_done_int_reg_1), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ), .I5(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .O(\stg1_wr_rd_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair606" *) LUT2 #( .INIT(4'hE)) \stg1_wr_rd_cnt[4]_i_3 (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(\stg1_wr_rd_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0222022200000222)) \stg1_wr_rd_cnt[4]_i_4 (.I0(complex_sample_cnt_inc_i_2_n_0), .I1(rdlvl_last_byte_done), .I2(\wrcal_reads[7]_i_6_n_0 ), .I3(\stg1_wr_rd_cnt[4]_i_5_n_0 ), .I4(prbs_rdlvl_prech_req_reg), .I5(\stg1_wr_rd_cnt[4]_i_6_n_0 ), .O(\stg1_wr_rd_cnt[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair482" *) LUT5 #( .INIT(32'h00800000)) \stg1_wr_rd_cnt[4]_i_5 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .O(\stg1_wr_rd_cnt[4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFF7FFFFFFFF)) \stg1_wr_rd_cnt[4]_i_6 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[3]), .I3(Q[4]), .I4(Q[5]), .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .O(\stg1_wr_rd_cnt[4]_i_6_n_0 )); LUT6 #( .INIT(64'hEEEBEEEEAAAAAAAA)) \stg1_wr_rd_cnt[5]_i_1 (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ), .I5(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .O(\stg1_wr_rd_cnt[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair567" *) LUT3 #( .INIT(8'h01)) \stg1_wr_rd_cnt[5]_i_2 (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ), .O(\stg1_wr_rd_cnt[5]_i_2_n_0 )); LUT4 #( .INIT(16'hFF60)) \stg1_wr_rd_cnt[6]_i_1 (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ), .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I3(\stg1_wr_rd_cnt[6]_i_2_n_0 ), .O(\stg1_wr_rd_cnt[6]_i_1_n_0 )); LUT5 #( .INIT(32'h00002022)) \stg1_wr_rd_cnt[6]_i_2 (.I0(\stg1_wr_rd_cnt[3]_i_2_n_0 ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(rdlvl_stg1_done_int_reg), .I3(stg1_wr_done), .I4(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .O(\stg1_wr_rd_cnt[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair514" *) LUT4 #( .INIT(16'hA208)) \stg1_wr_rd_cnt[7]_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ), .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ), .O(\stg1_wr_rd_cnt[7]_i_1_n_0 )); LUT4 #( .INIT(16'hFFD5)) \stg1_wr_rd_cnt[8]_i_1 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ), .I2(rdlvl_stg1_done_int_reg), .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ), .O(\stg1_wr_rd_cnt[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair514" *) LUT5 #( .INIT(32'hA8AA0200)) \stg1_wr_rd_cnt[8]_i_2 (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ), .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ), .I3(\stg1_wr_rd_cnt[8]_i_6_n_0 ), .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ), .O(\stg1_wr_rd_cnt[8]_i_2_n_0 )); LUT4 #( .INIT(16'h00A2)) \stg1_wr_rd_cnt[8]_i_3 (.I0(\stg1_wr_rd_cnt[4]_i_4_n_0 ), .I1(stg1_wr_done), .I2(rdlvl_stg1_done_int_reg), .I3(rstdiv0_sync_r1_reg_rep__24), .O(\stg1_wr_rd_cnt[8]_i_3_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \stg1_wr_rd_cnt[8]_i_4 (.I0(Q[4]), .I1(Q[5]), .I2(Q[3]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[2]), .I5(\wrcal_reads[7]_i_6_n_0 ), .O(\stg1_wr_rd_cnt[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000000080)) \stg1_wr_rd_cnt[8]_i_5 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(\init_state_r[5]_i_2_n_0 ), .I5(Q[3]), .O(\stg1_wr_rd_cnt[8]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \stg1_wr_rd_cnt[8]_i_6 (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ), .O(\stg1_wr_rd_cnt[8]_i_6_n_0 )); FDRE \stg1_wr_rd_cnt_reg[0] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[0]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[0] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[1] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[1]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[1] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[2] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[2]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[2] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[3] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[3]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[3] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[4] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[4]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[4] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[5] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[5]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[5] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[6] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[6]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[6] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[7] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[7]_i_1_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[7] ), .R(1'b0)); FDRE \stg1_wr_rd_cnt_reg[8] (.C(CLK), .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ), .D(\stg1_wr_rd_cnt[8]_i_2_n_0 ), .Q(\stg1_wr_rd_cnt_reg_n_0_[8] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair582" *) LUT3 #( .INIT(8'hB8)) \victim_sel[0]_i_1 (.I0(\victim_sel[0]_i_2_n_0 ), .I1(\victim_sel[2]_i_3_n_0 ), .I2(\victim_sel_reg_n_0_[0] ), .O(\victim_sel[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \victim_sel[0]_i_2 (.I0(complex_ocal_rd_victim_sel[0]), .I1(\rd_victim_sel_reg[0] ), .I2(\victim_sel[2]_i_4_n_0 ), .I3(wr_victim_sel_ocal[0]), .I4(prbs_rdlvl_done_reg_rep), .I5(wr_victim_sel[0]), .O(\victim_sel[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair584" *) LUT3 #( .INIT(8'hB8)) \victim_sel[1]_i_1 (.I0(\victim_sel[1]_i_2_n_0 ), .I1(\victim_sel[2]_i_3_n_0 ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel[1]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \victim_sel[1]_i_2 (.I0(complex_ocal_rd_victim_sel[1]), .I1(\rd_victim_sel_reg[1] ), .I2(\victim_sel[2]_i_4_n_0 ), .I3(wr_victim_sel_ocal[1]), .I4(prbs_rdlvl_done_reg_rep), .I5(wr_victim_sel[1]), .O(\victim_sel[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair582" *) LUT3 #( .INIT(8'hB8)) \victim_sel[2]_i_1 (.I0(\victim_sel[2]_i_2_n_0 ), .I1(\victim_sel[2]_i_3_n_0 ), .I2(\victim_sel_reg_n_0_[2] ), .O(\victim_sel[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \victim_sel[2]_i_2 (.I0(complex_ocal_rd_victim_sel[2]), .I1(\rd_victim_sel_reg[2] ), .I2(\victim_sel[2]_i_4_n_0 ), .I3(wr_victim_sel_ocal[2]), .I4(prbs_rdlvl_done_reg_rep), .I5(wr_victim_sel[2]), .O(\victim_sel[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBABF)) \victim_sel[2]_i_3 (.I0(\victim_sel[2]_i_5_n_0 ), .I1(complex_wr_done), .I2(prbs_rdlvl_done_reg), .I3(\one_rank.stg1_wr_done_reg_0 ), .I4(reset_rd_addr), .I5(complex_ocal_reset_rd_addr), .O(\victim_sel[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair574" *) LUT3 #( .INIT(8'hB8)) \victim_sel[2]_i_4 (.I0(complex_wr_done), .I1(prbs_rdlvl_done_reg_rep), .I2(\one_rank.stg1_wr_done_reg_0 ), .O(\victim_sel[2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair516" *) LUT5 #( .INIT(32'h00040000)) \victim_sel[2]_i_5 (.I0(complex_oclkdelay_calib_start_int_i_2_n_0), .I1(Q[2]), .I2(Q[0]), .I3(\init_state_r_reg_n_0_[3] ), .I4(Q[1]), .O(\victim_sel[2]_i_5_n_0 )); FDRE \victim_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\victim_sel[0]_i_1_n_0 ), .Q(\victim_sel_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \victim_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\victim_sel[1]_i_1_n_0 ), .Q(\victim_sel_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__12)); FDRE \victim_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\victim_sel[2]_i_1_n_0 ), .Q(\victim_sel_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair568" *) LUT3 #( .INIT(8'h01)) \victim_sel_rotate.sel[24]_i_1 (.I0(\victim_sel_reg_n_0_[2] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [0])); (* SOFT_HLUTNM = "soft_lutpair584" *) LUT3 #( .INIT(8'h02)) \victim_sel_rotate.sel[25]_i_1 (.I0(\victim_sel_reg_n_0_[0] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [1])); (* SOFT_HLUTNM = "soft_lutpair587" *) LUT3 #( .INIT(8'h02)) \victim_sel_rotate.sel[26]_i_1 (.I0(\victim_sel_reg_n_0_[1] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[0] ), .O(\victim_sel_rotate.sel_reg[31] [2])); LUT3 #( .INIT(8'h40)) \victim_sel_rotate.sel[27]_i_1 (.I0(\victim_sel_reg_n_0_[2] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [3])); (* SOFT_HLUTNM = "soft_lutpair568" *) LUT3 #( .INIT(8'h02)) \victim_sel_rotate.sel[28]_i_1 (.I0(\victim_sel_reg_n_0_[2] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [4])); (* SOFT_HLUTNM = "soft_lutpair571" *) LUT3 #( .INIT(8'h08)) \victim_sel_rotate.sel[29]_i_1 (.I0(\victim_sel_reg_n_0_[0] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [5])); (* SOFT_HLUTNM = "soft_lutpair587" *) LUT3 #( .INIT(8'h40)) \victim_sel_rotate.sel[30]_i_1 (.I0(\victim_sel_reg_n_0_[0] ), .I1(\victim_sel_reg_n_0_[2] ), .I2(\victim_sel_reg_n_0_[1] ), .O(\victim_sel_rotate.sel_reg[31] [6])); (* SOFT_HLUTNM = "soft_lutpair571" *) LUT3 #( .INIT(8'h80)) \victim_sel_rotate.sel[31]_i_1 (.I0(\victim_sel_reg_n_0_[1] ), .I1(\victim_sel_reg_n_0_[0] ), .I2(\victim_sel_reg_n_0_[2] ), .O(\victim_sel_rotate.sel_reg[31] [7])); FDRE wl_sm_start_reg (.C(CLK), .CE(1'b1), .D(wr_level_dqs_asrt_r1), .Q(wl_sm_start), .R(rstdiv0_sync_r1_reg_rep__11)); (* SOFT_HLUTNM = "soft_lutpair545" *) LUT4 #( .INIT(16'h00AE)) \wr_done_victim_rotate.complex_row0_wr_done_i_1 (.I0(complex_row0_wr_done), .I1(rdlvl_stg1_done_r1), .I2(wr_victim_inc_i_2_n_0), .I3(complex_row0_wr_done0), .O(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFEEFEEEEEEEEE)) \wr_done_victim_rotate.complex_row0_wr_done_i_2 (.I0(complex_row0_rd_done1), .I1(complex_byte_rd_done), .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ), .I3(prbs_rdlvl_done_reg), .I4(\complex_row_cnt_ocal[7]_i_5_n_0 ), .I5(wr_victim_inc), .O(complex_row0_wr_done0)); FDRE \wr_done_victim_rotate.complex_row0_wr_done_reg (.C(CLK), .CE(1'b1), .D(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ), .Q(complex_row0_wr_done), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair545" *) LUT4 #( .INIT(16'h00AE)) \wr_done_victim_rotate.complex_row1_wr_done_i_1 (.I0(complex_row1_wr_done), .I1(complex_row0_wr_done), .I2(wr_victim_inc_i_2_n_0), .I3(complex_row0_wr_done0), .O(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 )); FDRE \wr_done_victim_rotate.complex_row1_wr_done_reg (.C(CLK), .CE(1'b1), .D(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ), .Q(complex_row1_wr_done), .R(1'b0)); LUT4 #( .INIT(16'h00E0)) wr_level_dqs_asrt_i_1 (.I0(wr_level_dqs_asrt), .I1(wrlvl_active_r1), .I2(\en_cnt_div4.wrlvl_odt_i_2_n_0 ), .I3(rstdiv0_sync_r1_reg_rep__25), .O(wr_level_dqs_asrt_i_1_n_0)); FDRE wr_level_dqs_asrt_r1_reg (.C(CLK), .CE(1'b1), .D(wr_level_dqs_asrt), .Q(wr_level_dqs_asrt_r1), .R(1'b0)); FDRE wr_level_dqs_asrt_reg (.C(CLK), .CE(1'b1), .D(wr_level_dqs_asrt_i_1_n_0), .Q(wr_level_dqs_asrt), .R(1'b0)); LUT5 #( .INIT(32'h0000EA00)) wr_lvl_start_i_1 (.I0(wr_level_start_r_reg), .I1(dqs_asrt_cnt[0]), .I2(dqs_asrt_cnt[1]), .I3(wrlvl_active), .I4(rstdiv0_sync_r1_reg_rep__24), .O(wr_lvl_start_i_1_n_0)); FDRE wr_lvl_start_reg (.C(CLK), .CE(1'b1), .D(wr_lvl_start_i_1_n_0), .Q(wr_level_start_r_reg), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair569" *) LUT2 #( .INIT(4'hE)) wr_ptr0_i_1 (.I0(init_calib_complete_reg_rep__14), .I1(calib_ctl_wren), .O(mux_cmd_wren)); (* SOFT_HLUTNM = "soft_lutpair569" *) LUT3 #( .INIT(8'hB8)) \wr_ptr[3]_i_3 (.I0(mc_wrdata_en), .I1(init_calib_complete_reg_rep__14), .I2(calib_wrdata_en), .O(mux_wrdata_en)); (* SOFT_HLUTNM = "soft_lutpair552" *) LUT3 #( .INIT(8'h04)) wr_victim_inc_i_1 (.I0(wr_victim_inc_i_2_n_0), .I1(complex_row0_wr_done), .I2(\one_rank.stg1_wr_done_reg_0 ), .O(wr_victim_inc0)); (* SOFT_HLUTNM = "soft_lutpair503" *) LUT5 #( .INIT(32'hFFFFFEFF)) wr_victim_inc_i_2 (.I0(wr_victim_inc_i_3_n_0), .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ), .O(wr_victim_inc_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair517" *) LUT5 #( .INIT(32'hFFFFFFFE)) wr_victim_inc_i_3 (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ), .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ), .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ), .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ), .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ), .O(wr_victim_inc_i_3_n_0)); FDRE wr_victim_inc_reg (.C(CLK), .CE(1'b1), .D(wr_victim_inc0), .Q(wr_victim_inc), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair530" *) LUT4 #( .INIT(16'h006A)) \wr_victim_sel[0]_i_1 (.I0(wr_victim_sel[0]), .I1(wr_victim_inc), .I2(rdlvl_stg1_done_r1), .I3(p_81_in), .O(\wr_victim_sel[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair530" *) LUT5 #( .INIT(32'h00006AAA)) \wr_victim_sel[1]_i_1 (.I0(wr_victim_sel[1]), .I1(wr_victim_inc), .I2(rdlvl_stg1_done_r1), .I3(wr_victim_sel[0]), .I4(p_81_in), .O(\wr_victim_sel[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000006AAAAAAA)) \wr_victim_sel[2]_i_1 (.I0(wr_victim_sel[2]), .I1(wr_victim_inc), .I2(rdlvl_stg1_done_r1), .I3(wr_victim_sel[1]), .I4(wr_victim_sel[0]), .I5(p_81_in), .O(\wr_victim_sel[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair531" *) LUT4 #( .INIT(16'h006A)) \wr_victim_sel_ocal[0]_i_1 (.I0(wr_victim_sel_ocal[0]), .I1(prbs_rdlvl_done_reg), .I2(wr_victim_inc), .I3(rstdiv0_sync_r1_reg_rep__24_1), .O(\wr_victim_sel_ocal[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair531" *) LUT5 #( .INIT(32'h00006AAA)) \wr_victim_sel_ocal[1]_i_1 (.I0(wr_victim_sel_ocal[1]), .I1(prbs_rdlvl_done_reg), .I2(wr_victim_inc), .I3(wr_victim_sel_ocal[0]), .I4(rstdiv0_sync_r1_reg_rep__24_1), .O(\wr_victim_sel_ocal[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000006AAAAAAA)) \wr_victim_sel_ocal[2]_i_1 (.I0(wr_victim_sel_ocal[2]), .I1(prbs_rdlvl_done_reg), .I2(wr_victim_inc), .I3(wr_victim_sel_ocal[1]), .I4(wr_victim_sel_ocal[0]), .I5(rstdiv0_sync_r1_reg_rep__24_1), .O(\wr_victim_sel_ocal[2]_i_1_n_0 )); FDRE \wr_victim_sel_ocal_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel_ocal[0]_i_1_n_0 ), .Q(wr_victim_sel_ocal[0]), .R(1'b0)); FDRE \wr_victim_sel_ocal_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel_ocal[1]_i_1_n_0 ), .Q(wr_victim_sel_ocal[1]), .R(1'b0)); FDRE \wr_victim_sel_ocal_reg[2] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel_ocal[2]_i_1_n_0 ), .Q(wr_victim_sel_ocal[2]), .R(1'b0)); FDRE \wr_victim_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel[0]_i_1_n_0 ), .Q(wr_victim_sel[0]), .R(1'b0)); FDRE \wr_victim_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel[1]_i_1_n_0 ), .Q(wr_victim_sel[1]), .R(1'b0)); FDRE \wr_victim_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\wr_victim_sel[2]_i_1_n_0 ), .Q(wr_victim_sel[2]), .R(1'b0)); LUT2 #( .INIT(4'h2)) \wrcal_dqs_cnt_r[2]_i_5 (.I0(wrcal_sanity_chk), .I1(wrcal_sanity_chk_r_reg), .O(\wrcal_dqs_cnt_r_reg[0] )); LUT5 #( .INIT(32'hFFFF0080)) wrcal_final_chk_i_1 (.I0(\init_state_r[1]_i_1_n_0 ), .I1(\init_state_r[0]_i_1_n_0 ), .I2(\init_state_r[4]_i_1_n_0 ), .I3(wrcal_final_chk_i_2_n_0), .I4(wrcal_final_chk), .O(wrcal_final_chk_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair484" *) LUT5 #( .INIT(32'hFFFFFFDF)) wrcal_final_chk_i_2 (.I0(\init_state_r[2]_i_1_n_0 ), .I1(\init_state_r[5]_i_1_n_0 ), .I2(wrcal_done_reg_10), .I3(\init_state_r[3]_i_2_n_0 ), .I4(\init_state_r[6]_i_1_n_0 ), .O(wrcal_final_chk_i_2_n_0)); FDRE wrcal_final_chk_reg (.C(CLK), .CE(1'b1), .D(wrcal_final_chk_i_1_n_0), .Q(wrcal_final_chk), .R(rstdiv0_sync_r1_reg_rep__11)); LUT6 #( .INIT(64'h0000000000100000)) wrcal_rd_wait_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(\wrcal_reads[7]_i_5_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(wrcal_rd_wait_i_1_n_0)); FDRE wrcal_rd_wait_reg (.C(CLK), .CE(1'b1), .D(wrcal_rd_wait_i_1_n_0), .Q(wrcal_rd_wait), .R(rstdiv0_sync_r1_reg_rep__12)); (* SOFT_HLUTNM = "soft_lutpair540" *) LUT2 #( .INIT(4'hB)) \wrcal_reads[0]_i_1 (.I0(wrcal_reads), .I1(\wrcal_reads_reg_n_0_[0] ), .O(\wrcal_reads[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair576" *) LUT3 #( .INIT(8'hF9)) \wrcal_reads[1]_i_1 (.I0(\wrcal_reads_reg_n_0_[0] ), .I1(\wrcal_reads_reg_n_0_[1] ), .I2(wrcal_reads), .O(\wrcal_reads[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair499" *) LUT4 #( .INIT(16'hFFE1)) \wrcal_reads[2]_i_1 (.I0(\wrcal_reads_reg_n_0_[1] ), .I1(\wrcal_reads_reg_n_0_[0] ), .I2(\wrcal_reads_reg_n_0_[2] ), .I3(wrcal_reads), .O(\wrcal_reads[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair499" *) LUT5 #( .INIT(32'hFFFFFE01)) \wrcal_reads[3]_i_1 (.I0(\wrcal_reads_reg_n_0_[0] ), .I1(\wrcal_reads_reg_n_0_[1] ), .I2(\wrcal_reads_reg_n_0_[2] ), .I3(\wrcal_reads_reg_n_0_[3] ), .I4(wrcal_reads), .O(\wrcal_reads[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFE0001)) \wrcal_reads[4]_i_1 (.I0(\wrcal_reads_reg_n_0_[3] ), .I1(\wrcal_reads_reg_n_0_[2] ), .I2(\wrcal_reads_reg_n_0_[1] ), .I3(\wrcal_reads_reg_n_0_[0] ), .I4(\wrcal_reads_reg_n_0_[4] ), .I5(wrcal_reads), .O(\wrcal_reads[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair576" *) LUT3 #( .INIT(8'hF6)) \wrcal_reads[5]_i_1 (.I0(\wrcal_reads[5]_i_2_n_0 ), .I1(\wrcal_reads_reg_n_0_[5] ), .I2(wrcal_reads), .O(\wrcal_reads[5]_i_1_n_0 )); LUT5 #( .INIT(32'h00000001)) \wrcal_reads[5]_i_2 (.I0(\wrcal_reads_reg_n_0_[4] ), .I1(\wrcal_reads_reg_n_0_[0] ), .I2(\wrcal_reads_reg_n_0_[1] ), .I3(\wrcal_reads_reg_n_0_[2] ), .I4(\wrcal_reads_reg_n_0_[3] ), .O(\wrcal_reads[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair542" *) LUT3 #( .INIT(8'hF6)) \wrcal_reads[6]_i_1 (.I0(\wrcal_reads[7]_i_7_n_0 ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(wrcal_reads), .O(\wrcal_reads[6]_i_1_n_0 )); LUT6 #( .INIT(64'hAABAAAAAAAAAAAAA)) \wrcal_reads[7]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(\wrcal_reads[7]_i_5_n_0 ), .I5(\wrcal_reads[7]_i_6_n_0 ), .O(wrcal_reads05_out)); LUT4 #( .INIT(16'hFFFD)) \wrcal_reads[7]_i_2 (.I0(\wrcal_reads[7]_i_7_n_0 ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(\wrcal_reads_reg_n_0_[7] ), .I3(wrcal_reads), .O(\wrcal_reads[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair542" *) LUT4 #( .INIT(16'hFFD2)) \wrcal_reads[7]_i_3 (.I0(\wrcal_reads[7]_i_7_n_0 ), .I1(\wrcal_reads_reg_n_0_[6] ), .I2(\wrcal_reads_reg_n_0_[7] ), .I3(wrcal_reads), .O(\wrcal_reads[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \wrcal_reads[7]_i_5 (.I0(Q[2]), .I1(\init_state_r_reg_n_0_[3] ), .O(\wrcal_reads[7]_i_5_n_0 )); LUT2 #( .INIT(4'h1)) \wrcal_reads[7]_i_6 (.I0(Q[0]), .I1(Q[1]), .O(\wrcal_reads[7]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \wrcal_reads[7]_i_7 (.I0(\wrcal_reads_reg_n_0_[3] ), .I1(\wrcal_reads_reg_n_0_[2] ), .I2(\wrcal_reads_reg_n_0_[1] ), .I3(\wrcal_reads_reg_n_0_[0] ), .I4(\wrcal_reads_reg_n_0_[4] ), .I5(\wrcal_reads_reg_n_0_[5] ), .O(\wrcal_reads[7]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000004000)) \wrcal_reads[7]_i_8 (.I0(read_calib_i_2_n_0), .I1(\wrcal_reads[7]_i_5_n_0 ), .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I3(\wrcal_reads[7]_i_7_n_0 ), .I4(\wrcal_reads_reg_n_0_[6] ), .I5(\wrcal_reads_reg_n_0_[7] ), .O(wrcal_reads)); FDRE \wrcal_reads_reg[0] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[0]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[0] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[1] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[1]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[1] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[2] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[2]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[2] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[3] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[3]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[3] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[4] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[4]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[4] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[5] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[5]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[5] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[6] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[6]_i_1_n_0 ), .Q(\wrcal_reads_reg_n_0_[6] ), .R(wrcal_reads05_out)); FDRE \wrcal_reads_reg[7] (.C(CLK), .CE(\wrcal_reads[7]_i_2_n_0 ), .D(\wrcal_reads[7]_i_3_n_0 ), .Q(\wrcal_reads_reg_n_0_[7] ), .R(wrcal_reads05_out)); FDRE wrcal_resume_r_reg (.C(CLK), .CE(1'b1), .D(wrcal_resume_w), .Q(wrcal_resume_r), .R(1'b0)); FDRE wrcal_sanity_chk_reg (.C(CLK), .CE(1'b1), .D(wrcal_final_chk), .Q(wrcal_sanity_chk), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 " *) SRL16E \wrcal_start_dly_r_reg[4]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(wrcal_start_pre), .Q(\wrcal_start_dly_r_reg[4]_srl5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair492" *) LUT5 #( .INIT(32'h01000400)) \wrcal_start_dly_r_reg[4]_srl5_i_1 (.I0(\init_state_r_reg_n_0_[3] ), .I1(Q[2]), .I2(read_calib_i_2_n_0), .I3(Q[0]), .I4(Q[1]), .O(wrcal_start_pre)); FDRE \wrcal_start_dly_r_reg[5] (.C(CLK), .CE(1'b1), .D(\wrcal_start_dly_r_reg[4]_srl5_n_0 ), .Q(wrcal_start_dly_r), .R(1'b0)); LUT4 #( .INIT(16'h000E)) wrcal_start_i_1 (.I0(wrcal_start_reg_0), .I1(wrcal_start_dly_r), .I2(wrlvl_byte_redo), .I3(rstdiv0_sync_r1_reg_rep__24), .O(wrcal_start_i_1_n_0)); FDRE wrcal_start_reg (.C(CLK), .CE(1'b1), .D(wrcal_start_i_1_n_0), .Q(wrcal_start_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair613" *) LUT1 #( .INIT(2'h1)) \wrcal_wr_cnt[0]_i_1 (.I0(wrcal_wr_cnt_reg__0[0]), .O(\wrcal_wr_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair613" *) LUT2 #( .INIT(4'h9)) \wrcal_wr_cnt[1]_i_1 (.I0(wrcal_wr_cnt_reg__0[0]), .I1(wrcal_wr_cnt_reg__0[1]), .O(\wrcal_wr_cnt[1]_i_1_n_0 )); LUT3 #( .INIT(8'hA9)) \wrcal_wr_cnt[2]_i_1 (.I0(wrcal_wr_cnt_reg__0[2]), .I1(wrcal_wr_cnt_reg__0[1]), .I2(wrcal_wr_cnt_reg__0[0]), .O(wrcal_wr_cnt0[2])); LUT6 #( .INIT(64'hFFFFFFFF111111F1)) \wrcal_wr_cnt[3]_i_1 (.I0(first_wrcal_pat_r_i_2_n_0), .I1(complex_oclkdelay_calib_start_int_reg_0), .I2(\wrcal_wr_cnt[3]_i_4_n_0 ), .I3(wrcal_wr_cnt_reg__0[3]), .I4(wrcal_wr_cnt_reg__0[2]), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\wrcal_wr_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \wrcal_wr_cnt[3]_i_2 (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(Q[2]), .I5(\init_state_r_reg_n_0_[3] ), .O(\wrcal_wr_cnt[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair564" *) LUT4 #( .INIT(16'hCCC9)) \wrcal_wr_cnt[3]_i_3 (.I0(wrcal_wr_cnt_reg__0[2]), .I1(wrcal_wr_cnt_reg__0[3]), .I2(wrcal_wr_cnt_reg__0[0]), .I3(wrcal_wr_cnt_reg__0[1]), .O(wrcal_wr_cnt0[3])); (* SOFT_HLUTNM = "soft_lutpair564" *) LUT2 #( .INIT(4'h1)) \wrcal_wr_cnt[3]_i_4 (.I0(wrcal_wr_cnt_reg__0[0]), .I1(wrcal_wr_cnt_reg__0[1]), .O(\wrcal_wr_cnt[3]_i_4_n_0 )); FDRE \wrcal_wr_cnt_reg[0] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(\wrcal_wr_cnt[0]_i_1_n_0 ), .Q(wrcal_wr_cnt_reg__0[0]), .R(\wrcal_wr_cnt[3]_i_1_n_0 )); FDRE \wrcal_wr_cnt_reg[1] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(\wrcal_wr_cnt[1]_i_1_n_0 ), .Q(wrcal_wr_cnt_reg__0[1]), .R(\wrcal_wr_cnt[3]_i_1_n_0 )); FDSE \wrcal_wr_cnt_reg[2] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(wrcal_wr_cnt0[2]), .Q(wrcal_wr_cnt_reg__0[2]), .S(\wrcal_wr_cnt[3]_i_1_n_0 )); FDRE \wrcal_wr_cnt_reg[3] (.C(CLK), .CE(\wrcal_wr_cnt[3]_i_2_n_0 ), .D(wrcal_wr_cnt0[3]), .Q(wrcal_wr_cnt_reg__0[3]), .R(\wrcal_wr_cnt[3]_i_1_n_0 )); LUT3 #( .INIT(8'h2F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1 (.I0(first_wrcal_pat_r), .I1(wrcal_done_reg_10), .I2(oclkdelay_calib_done_r_reg_2), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); LUT5 #( .INIT(32'hFAFF3AFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1 (.I0(first_wrcal_pat_r), .I1(rdlvl_stg1_done_int_reg), .I2(wrcal_done_reg_10), .I3(oclkdelay_calib_done_r_reg_2), .I4(\dout_o_reg[0]_0 ), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 )); LUT5 #( .INIT(32'hFAFF3AFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2 (.I0(first_wrcal_pat_r), .I1(rdlvl_stg1_done_int_reg), .I2(wrcal_done_reg_10), .I3(oclkdelay_calib_done_r_reg_2), .I4(\dout_o_reg[0] ), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 )); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[12]_0 ), .Q(phy_wrdata[120]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_8), .Q(phy_wrdata[121]), .S(wrcal_done_reg_0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[4]_0 ), .Q(phy_wrdata[122]), .S(wrcal_done_reg_2)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_7), .Q(phy_wrdata[123]), .S(wrcal_done_reg_0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[12] ), .Q(phy_wrdata[124]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_6), .Q(phy_wrdata[125]), .S(wrcal_done_reg_0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[4] ), .Q(phy_wrdata[126]), .S(wrcal_done_reg_2)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_5), .Q(phy_wrdata[127]), .S(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[3]_0 ), .Q(phy_wrdata[152]), .R(wrcal_done_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_0 ), .Q(phy_wrdata[153]), .R(1'b0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_4 ), .Q(phy_wrdata[154]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_2 ), .Q(phy_wrdata[155]), .R(wrcal_done_reg)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[3] ), .Q(phy_wrdata[156]), .R(wrcal_done_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11] ), .Q(phy_wrdata[157]), .R(1'b0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_3 ), .Q(phy_wrdata[158]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[11]_1 ), .Q(phy_wrdata[159]), .R(wrcal_done_reg)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_4), .Q(phy_wrdata[184]), .S(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(oclkdelay_calib_done_r_reg_0), .Q(phy_wrdata[185]), .R(1'b0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[10]_0 ), .Q(phy_wrdata[186]), .S(wrcal_done_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[2]_0 ), .Q(phy_wrdata[187]), .S(wrcal_done_reg_2)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(wrcal_done_reg_3), .Q(phy_wrdata[188]), .S(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(oclkdelay_calib_done_r_reg), .Q(phy_wrdata[189]), .R(1'b0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[10] ), .Q(phy_wrdata[190]), .S(wrcal_done_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[2] ), .Q(phy_wrdata[191]), .S(wrcal_done_reg_2)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_4 ), .Q(phy_wrdata[216]), .R(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_0 ), .Q(phy_wrdata[217]), .R(wrcal_done_reg)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[1]_0 ), .Q(phy_wrdata[218]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_3 ), .Q(phy_wrdata[219]), .R(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_2 ), .Q(phy_wrdata[220]), .R(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9] ), .Q(phy_wrdata[221]), .R(wrcal_done_reg)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[1] ), .Q(phy_wrdata[222]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[9]_1 ), .Q(phy_wrdata[223]), .R(wrcal_done_reg_0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_0 ), .Q(phy_wrdata[248]), .S(oclkdelay_calib_done_r_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_4 ), .Q(phy_wrdata[249]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15]_2 ), .Q(phy_wrdata[24]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[250] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ), .Q(phy_wrdata[250]), .R(1'b0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_2 ), .Q(phy_wrdata[251]), .S(wrcal_done_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8] ), .Q(phy_wrdata[252]), .S(oclkdelay_calib_done_r_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_3 ), .Q(phy_wrdata[253]), .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ), .Q(phy_wrdata[254]), .R(1'b0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[8]_1 ), .Q(phy_wrdata[255]), .S(wrcal_done_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7]_0 ), .Q(phy_wrdata[25]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7]_2 ), .Q(phy_wrdata[26]), .R(wrcal_done_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15]_1 ), .Q(phy_wrdata[27]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15]_0 ), .Q(phy_wrdata[28]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7] ), .Q(phy_wrdata[29]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[7]_1 ), .Q(phy_wrdata[30]), .R(wrcal_done_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[15] ), .Q(phy_wrdata[31]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(D[0]), .Q(phy_wrdata[56]), .R(1'b0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(first_rdlvl_pat_r_reg_0), .Q(phy_wrdata[57]), .S(oclkdelay_calib_done_r_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14]_2 ), .Q(phy_wrdata[58]), .S(oclkdelay_calib_done_r_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14]_1 ), .Q(phy_wrdata[59]), .S(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[60] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(D[1]), .Q(phy_wrdata[60]), .R(1'b0)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[6] ), .Q(phy_wrdata[61]), .S(oclkdelay_calib_done_r_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14]_0 ), .Q(phy_wrdata[62]), .S(oclkdelay_calib_done_r_reg_1)); FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[14] ), .Q(phy_wrdata[63]), .S(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_0 ), .Q(phy_wrdata[88]), .R(wrcal_done_reg)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_6 ), .Q(phy_wrdata[89]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_4 ), .Q(phy_wrdata[90]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_2 ), .Q(phy_wrdata[91]), .R(wrcal_done_reg_0)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13] ), .Q(phy_wrdata[92]), .R(wrcal_done_reg)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_5 ), .Q(phy_wrdata[93]), .R(oclkdelay_calib_done_r_reg_1)); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_3 ), .Q(phy_wrdata[94]), .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 )); FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] (.C(CLK), .CE(rdlvl_stg1_done_int_reg_0), .D(\dout_o_reg[13]_1 ), .Q(phy_wrdata[95]), .R(wrcal_done_reg_0)); LUT6 #( .INIT(64'h000000000EEEEEEE)) write_calib_i_1 (.I0(phy_write_calib), .I1(wrlvl_active_r1), .I2(done_dqs_tap_inc), .I3(write_calib_i_2_n_0), .I4(Q[1]), .I5(rstdiv0_sync_r1_reg_rep__24), .O(write_calib_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000004)) write_calib_i_2 (.I0(Q[0]), .I1(\init_state_r_reg_n_0_[3] ), .I2(Q[2]), .I3(Q[5]), .I4(Q[4]), .I5(Q[3]), .O(write_calib_i_2_n_0)); FDRE write_calib_reg (.C(CLK), .CE(1'b1), .D(write_calib_i_1_n_0), .Q(phy_write_calib), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000EA)) wrlvl_active_i_1 (.I0(wrlvl_active), .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ), .I2(wrlvl_odt), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(done_dqs_tap_inc), .I5(wrlvl_rank_done), .O(wrlvl_active_i_1_n_0)); FDRE wrlvl_active_r1_reg (.C(CLK), .CE(1'b1), .D(wrlvl_active), .Q(wrlvl_active_r1), .R(1'b0)); FDRE wrlvl_active_reg (.C(CLK), .CE(1'b1), .D(wrlvl_active_i_1_n_0), .Q(wrlvl_active), .R(1'b0)); FDRE wrlvl_done_r1_reg (.C(CLK), .CE(1'b1), .D(wrlvl_done_r), .Q(wrlvl_done_r1), .R(1'b0)); FDRE wrlvl_done_r_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_reg), .Q(wrlvl_done_r), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000AE)) wrlvl_final_if_rst_i_1 (.I0(wrlvl_final_if_rst), .I1(wrlvl_done_r), .I2(wrlvl_final_if_rst_i_2_n_0), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(\cnt_init_mr_r_reg[1]_0 ), .I5(\wrcal_wr_cnt[3]_i_2_n_0 ), .O(wrlvl_final_if_rst_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) wrlvl_final_if_rst_i_2 (.I0(Q[1]), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(\init_state_r_reg[1]_0 ), .I5(Q[0]), .O(wrlvl_final_if_rst_i_2_n_0)); FDRE wrlvl_final_if_rst_reg (.C(CLK), .CE(1'b1), .D(wrlvl_final_if_rst_i_1_n_0), .Q(wrlvl_final_if_rst), .R(1'b0)); LUT5 #( .INIT(32'h000000AE)) wrlvl_odt_ctl_i_1 (.I0(wrlvl_odt_ctl), .I1(wrlvl_rank_done), .I2(wrlvl_rank_done_r1), .I3(wrlvl_odt_ctl_i_2_n_0), .I4(rstdiv0_sync_r1_reg_rep__25), .O(wrlvl_odt_ctl_i_1_n_0)); LUT6 #( .INIT(64'h0001000100010000)) wrlvl_odt_ctl_i_2 (.I0(read_calib_reg_0), .I1(Q[3]), .I2(Q[4]), .I3(Q[5]), .I4(wrlvl_odt_ctl_i_3_n_0), .I5(init_state_r1[3]), .O(wrlvl_odt_ctl_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) wrlvl_odt_ctl_i_3 (.I0(init_state_r1[1]), .I1(init_state_r1[6]), .I2(init_state_r1[2]), .I3(init_state_r1[5]), .I4(init_state_r1[4]), .I5(init_state_r1[0]), .O(wrlvl_odt_ctl_i_3_n_0)); FDRE wrlvl_odt_ctl_reg (.C(CLK), .CE(1'b1), .D(wrlvl_odt_ctl_i_1_n_0), .Q(wrlvl_odt_ctl), .R(1'b0)); FDRE wrlvl_rank_done_r1_reg (.C(CLK), .CE(1'b1), .D(wrlvl_rank_done), .Q(wrlvl_rank_done_r1), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 " *) SRL16E wrlvl_rank_done_r6_reg_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(wrlvl_rank_done_r1), .Q(wrlvl_rank_done_r6_reg_srl5_n_0)); FDRE wrlvl_rank_done_r7_reg (.C(CLK), .CE(1'b1), .D(wrlvl_rank_done_r6_reg_srl5_n_0), .Q(wrlvl_rank_done_r7), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_cntlr (prech_req_r_reg, rd_active_r1_reg, lim_start, wrlvl_final_mux_reg, reset_scan, complex_ocal_ref_req, \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] , \byte_r_reg[1]_0 , \byte_r_reg[0]_0 , D, \simp_stg3_final_r_reg[23] , \simp_stg3_final_r_reg[11] , \simp_stg3_final_r_reg[5] , \simp_stg3_final_r_reg[17] , done_r_reg, \rd_victim_sel_r_reg[0] , \stg3_init_val_reg[3] , sr_valid_r108_out, \init_state_r_reg[2] , \init_state_r_reg[5] , ocal_last_byte_done_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \cal2_state_r_reg[0] , ocd_cntlr2stg2_dec_r, rstdiv0_sync_r1_reg_rep__9, CLK, phy_rddata_en, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__26, done_r_reg_0, oclkdelay_calib_start_int_reg, prech_req_r_reg_0, rstdiv0_sync_r1_reg_rep__26_0, po_rdy, \po_counter_read_val_reg[2] , \simp_stg3_final_r_reg[17]_0 , \simp_stg3_final_r_reg[16] , \simp_stg3_final_r_reg[10] , \simp_stg3_final_r_reg[2] , \simp_stg3_final_r_reg[8] , \simp_stg3_final_r_reg[19] , \simp_stg3_final_r_reg[12] , lim_start_r, rstdiv0_sync_r1_reg_rep__25, \data_cnt_r_reg[7] , rstdiv0_sync_r1_reg_rep__20, rdlvl_stg1_start_reg, \cnt_shift_r_reg[0] , \init_state_r_reg[0] , \init_state_r_reg[2]_0 , prbs_rdlvl_done_reg, oclk_calib_resume_r_reg, prech_req_posedge_r_reg, cnt_cmd_done_r, oclkdelay_center_calib_done_r_reg, ocal_last_byte_done, \po_stg2_wrcal_cnt_reg[0] , wr_level_done_reg, oclkdelay_calib_done_r_reg_0, pi_stg2_rdlvl_cnt, \po_stg2_wrcal_cnt_reg[1] , rd_active_r1, wrlvl_byte_done, rstdiv0_sync_r1_reg_rep__2, prech_done, oclkdelay_calib_start_int_reg_0); output prech_req_r_reg; output rd_active_r1_reg; output lim_start; output wrlvl_final_mux_reg; output reset_scan; output complex_ocal_ref_req; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; output \byte_r_reg[1]_0 ; output \byte_r_reg[0]_0 ; output [4:0]D; output \simp_stg3_final_r_reg[23] ; output \simp_stg3_final_r_reg[11] ; output \simp_stg3_final_r_reg[5] ; output \simp_stg3_final_r_reg[17] ; output done_r_reg; output \rd_victim_sel_r_reg[0] ; output \stg3_init_val_reg[3] ; output sr_valid_r108_out; output \init_state_r_reg[2] ; output \init_state_r_reg[5] ; output ocal_last_byte_done_reg; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \cal2_state_r_reg[0] ; output ocd_cntlr2stg2_dec_r; input rstdiv0_sync_r1_reg_rep__9; input CLK; input phy_rddata_en; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__26; input done_r_reg_0; input oclkdelay_calib_start_int_reg; input prech_req_r_reg_0; input rstdiv0_sync_r1_reg_rep__26_0; input po_rdy; input \po_counter_read_val_reg[2] ; input \simp_stg3_final_r_reg[17]_0 ; input \simp_stg3_final_r_reg[16] ; input \simp_stg3_final_r_reg[10] ; input \simp_stg3_final_r_reg[2] ; input \simp_stg3_final_r_reg[8] ; input \simp_stg3_final_r_reg[19] ; input \simp_stg3_final_r_reg[12] ; input lim_start_r; input rstdiv0_sync_r1_reg_rep__25; input \data_cnt_r_reg[7] ; input rstdiv0_sync_r1_reg_rep__20; input rdlvl_stg1_start_reg; input \cnt_shift_r_reg[0] ; input \init_state_r_reg[0] ; input [1:0]\init_state_r_reg[2]_0 ; input prbs_rdlvl_done_reg; input oclk_calib_resume_r_reg; input prech_req_posedge_r_reg; input cnt_cmd_done_r; input oclkdelay_center_calib_done_r_reg; input ocal_last_byte_done; input \po_stg2_wrcal_cnt_reg[0] ; input wr_level_done_reg; input oclkdelay_calib_done_r_reg_0; input [1:0]pi_stg2_rdlvl_cnt; input \po_stg2_wrcal_cnt_reg[1] ; input rd_active_r1; input wrlvl_byte_done; input rstdiv0_sync_r1_reg_rep__2; input prech_done; input oclkdelay_calib_start_int_reg_0; wire CLK; wire [4:0]D; wire \FSM_sequential_sm_r[0]_i_1_n_0 ; wire \FSM_sequential_sm_r[1]_i_1_n_0 ; wire \FSM_sequential_sm_r[2]_i_1_n_0 ; wire \FSM_sequential_sm_r[2]_i_2_n_0 ; wire \FSM_sequential_sm_r[2]_i_4_n_0 ; wire \FSM_sequential_sm_r[2]_i_5_n_0 ; wire \FSM_sequential_sm_r_reg[2]_i_3_n_0 ; wire \byte_r[0]_i_1_n_0 ; wire \byte_r[0]_i_2_n_0 ; wire \byte_r[1]_i_1_n_0 ; wire \byte_r[1]_i_2_n_0 ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[1]_0 ; wire \cal2_state_r_reg[0] ; wire cnt_cmd_done_r; wire \cnt_shift_r_reg[0] ; wire complex_ocal_ref_req; wire \data_cnt_r_reg[7] ; wire done_r_reg; wire done_r_reg_0; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[2] ; wire [1:0]\init_state_r_reg[2]_0 ; wire \init_state_r_reg[5] ; wire lim_start; wire lim_start_r; wire lim_start_r_i_1_n_0; wire lim_start_r_i_2_n_0; wire ocal_last_byte_done; wire ocal_last_byte_done_reg; wire ocd_cntlr2stg2_dec_r; wire ocd_prech_req_ns; wire oclk_calib_resume_r_reg; wire oclkdelay_calib_done_r_i_1_n_0; wire oclkdelay_calib_done_r_i_3_n_0; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_calib_start_int_reg; wire oclkdelay_calib_start_int_reg_0; wire oclkdelay_center_calib_done_r_reg; wire phy_rddata_en; wire [1:0]pi_stg2_rdlvl_cnt; wire \po_counter_read_val_reg[2] ; wire [3:0]po_rd_wait_ns; wire \po_rd_wait_r[0]_i_2_n_0 ; wire \po_rd_wait_r[1]_i_2_n_0 ; wire \po_rd_wait_r[2]_i_2_n_0 ; wire \po_rd_wait_r[2]_i_3_n_0 ; wire \po_rd_wait_r[3]_i_1_n_0 ; wire \po_rd_wait_r[3]_i_3_n_0 ; wire \po_rd_wait_r[3]_i_4_n_0 ; wire \po_rd_wait_r[3]_i_5_n_0 ; wire \po_rd_wait_r[3]_i_6_n_0 ; wire [3:0]po_rd_wait_r_reg__0; wire po_rdy; wire \po_stg2_wrcal_cnt_reg[0] ; wire \po_stg2_wrcal_cnt_reg[1] ; wire prbs_rdlvl_done_reg; wire prech_done; wire prech_req_posedge_r_reg; wire prech_req_r_reg; wire prech_req_r_reg_0; wire rd_active_r1; wire rd_active_r1_reg; wire \rd_victim_sel_r_reg[0] ; wire rdlvl_stg1_start_reg; wire reset_scan; wire reset_scan_r_i_1_n_0; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__9; wire \simp_stg3_final_r_reg[10] ; wire \simp_stg3_final_r_reg[11] ; wire \simp_stg3_final_r_reg[12] ; wire \simp_stg3_final_r_reg[16] ; wire \simp_stg3_final_r_reg[17] ; wire \simp_stg3_final_r_reg[17]_0 ; wire \simp_stg3_final_r_reg[19] ; wire \simp_stg3_final_r_reg[23] ; wire \simp_stg3_final_r_reg[2] ; wire \simp_stg3_final_r_reg[5] ; wire \simp_stg3_final_r_reg[8] ; (* RTL_KEEP = "yes" *) wire [2:0]sm_r; wire sr_valid_r108_out; wire \stg3_init_val_reg[3] ; wire wr_level_done_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; wire wrlvl_byte_done; wire wrlvl_final_mux_reg; wire wrlvl_final_r0; LUT3 #( .INIT(8'h74)) \FSM_sequential_sm_r[0]_i_1 (.I0(sm_r[0]), .I1(\FSM_sequential_sm_r_reg[2]_i_3_n_0 ), .I2(sm_r[0]), .O(\FSM_sequential_sm_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h8FB0FFFF8FB00000)) \FSM_sequential_sm_r[1]_i_1 (.I0(\FSM_sequential_sm_r[2]_i_2_n_0 ), .I1(sm_r[2]), .I2(sm_r[1]), .I3(sm_r[0]), .I4(\FSM_sequential_sm_r_reg[2]_i_3_n_0 ), .I5(sm_r[1]), .O(\FSM_sequential_sm_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hAFC0FFFFAFC00000)) \FSM_sequential_sm_r[2]_i_1 (.I0(\FSM_sequential_sm_r[2]_i_2_n_0 ), .I1(sm_r[0]), .I2(sm_r[1]), .I3(sm_r[2]), .I4(\FSM_sequential_sm_r_reg[2]_i_3_n_0 ), .I5(sm_r[2]), .O(\FSM_sequential_sm_r[2]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \FSM_sequential_sm_r[2]_i_2 (.I0(\byte_r_reg[0]_0 ), .I1(\byte_r_reg[1]_0 ), .I2(sm_r[0]), .O(\FSM_sequential_sm_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'hBBBBCFCC)) \FSM_sequential_sm_r[2]_i_4 (.I0(prech_done), .I1(sm_r[2]), .I2(wrlvl_final_mux_reg), .I3(oclkdelay_calib_start_int_reg_0), .I4(sm_r[0]), .O(\FSM_sequential_sm_r[2]_i_4_n_0 )); LUT5 #( .INIT(32'hB8FFB8CC)) \FSM_sequential_sm_r[2]_i_5 (.I0(oclkdelay_calib_done_r_i_3_n_0), .I1(sm_r[2]), .I2(rstdiv0_sync_r1_reg_rep__26), .I3(sm_r[0]), .I4(done_r_reg_0), .O(\FSM_sequential_sm_r[2]_i_5_n_0 )); (* KEEP = "yes" *) FDRE \FSM_sequential_sm_r_reg[0] (.C(CLK), .CE(1'b1), .D(\FSM_sequential_sm_r[0]_i_1_n_0 ), .Q(sm_r[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE \FSM_sequential_sm_r_reg[1] (.C(CLK), .CE(1'b1), .D(\FSM_sequential_sm_r[1]_i_1_n_0 ), .Q(sm_r[1]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE \FSM_sequential_sm_r_reg[2] (.C(CLK), .CE(1'b1), .D(\FSM_sequential_sm_r[2]_i_1_n_0 ), .Q(sm_r[2]), .R(rstdiv0_sync_r1_reg_rep__2)); MUXF7 \FSM_sequential_sm_r_reg[2]_i_3 (.I0(\FSM_sequential_sm_r[2]_i_4_n_0 ), .I1(\FSM_sequential_sm_r[2]_i_5_n_0 ), .O(\FSM_sequential_sm_r_reg[2]_i_3_n_0 ), .S(sm_r[1])); LUT6 #( .INIT(64'hFFFF5EDE0000A020)) \byte_r[0]_i_1 (.I0(sm_r[2]), .I1(sm_r[0]), .I2(sm_r[1]), .I3(\byte_r[0]_i_2_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__26_0), .I5(\byte_r_reg[0]_0 ), .O(\byte_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair353" *) LUT5 #( .INIT(32'h00000444)) \byte_r[0]_i_2 (.I0(\po_rd_wait_r[3]_i_6_n_0 ), .I1(po_rdy), .I2(\byte_r_reg[1]_0 ), .I3(\byte_r_reg[0]_0 ), .I4(\po_counter_read_val_reg[2] ), .O(\byte_r[0]_i_2_n_0 )); LUT4 #( .INIT(16'h4F80)) \byte_r[1]_i_1 (.I0(\byte_r_reg[0]_0 ), .I1(sm_r[1]), .I2(\byte_r[1]_i_2_n_0 ), .I3(\byte_r_reg[1]_0 ), .O(\byte_r[1]_i_1_n_0 )); LUT5 #( .INIT(32'h0000A121)) \byte_r[1]_i_2 (.I0(sm_r[2]), .I1(sm_r[0]), .I2(sm_r[1]), .I3(\byte_r[0]_i_2_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__26_0), .O(\byte_r[1]_i_2_n_0 )); FDRE \byte_r_reg[0] (.C(CLK), .CE(1'b1), .D(\byte_r[0]_i_1_n_0 ), .Q(\byte_r_reg[0]_0 ), .R(1'b0)); FDRE \byte_r_reg[1] (.C(CLK), .CE(1'b1), .D(\byte_r[1]_i_1_n_0 ), .Q(\byte_r_reg[1]_0 ), .R(1'b0)); LUT3 #( .INIT(8'h40)) \cal2_state_r[3]_i_10 (.I0(rd_active_r1_reg), .I1(rd_active_r1), .I2(wrlvl_byte_done), .O(\cal2_state_r_reg[0] )); LUT2 #( .INIT(4'h2)) done_r_i_2 (.I0(lim_start), .I1(lim_start_r), .O(done_r_reg)); LUT6 #( .INIT(64'hFF00F4000000F400)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_2 (.I0(wrlvl_final_mux_reg), .I1(\byte_r_reg[0]_0 ), .I2(\po_stg2_wrcal_cnt_reg[0] ), .I3(wr_level_done_reg), .I4(oclkdelay_calib_done_r_reg_0), .I5(pi_stg2_rdlvl_cnt[0]), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'hFF00F4000000F400)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_2 (.I0(wrlvl_final_mux_reg), .I1(\byte_r_reg[1]_0 ), .I2(\po_stg2_wrcal_cnt_reg[1] ), .I3(wr_level_done_reg), .I4(oclkdelay_calib_done_r_reg_0), .I5(pi_stg2_rdlvl_cnt[1]), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[1] )); LUT6 #( .INIT(64'hAAAAAAAA00000008)) \init_state_r[2]_i_19 (.I0(\init_state_r_reg[0] ), .I1(\init_state_r_reg[2]_0 [1]), .I2(prech_req_r_reg), .I3(prech_req_r_reg_0), .I4(prbs_rdlvl_done_reg), .I5(oclk_calib_resume_r_reg), .O(\init_state_r_reg[2] )); LUT6 #( .INIT(64'h00000000EEEEEE0E)) \init_state_r[5]_i_59 (.I0(wrlvl_final_mux_reg), .I1(prech_req_posedge_r_reg), .I2(cnt_cmd_done_r), .I3(prech_req_r_reg_0), .I4(prech_req_r_reg), .I5(\init_state_r_reg[2]_0 [0]), .O(\init_state_r_reg[5] )); LUT6 #( .INIT(64'hFFFF777788880300)) lim_start_r_i_1 (.I0(lim_start_r_i_2_n_0), .I1(sm_r[1]), .I2(sm_r[0]), .I3(oclkdelay_calib_start_int_reg), .I4(sm_r[2]), .I5(lim_start), .O(lim_start_r_i_1_n_0)); LUT5 #( .INIT(32'h00007F70)) lim_start_r_i_2 (.I0(\byte_r_reg[0]_0 ), .I1(\byte_r_reg[1]_0 ), .I2(sm_r[2]), .I3(done_r_reg_0), .I4(sm_r[0]), .O(lim_start_r_i_2_n_0)); FDRE lim_start_r_reg (.C(CLK), .CE(1'b1), .D(lim_start_r_i_1_n_0), .Q(lim_start), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair355" *) LUT4 #( .INIT(16'hFF80)) ocal_last_byte_done_i_2 (.I0(oclkdelay_center_calib_done_r_reg), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .I3(ocal_last_byte_done), .O(ocal_last_byte_done_reg)); LUT3 #( .INIT(8'h04)) ocd_prech_req_r_i_1 (.I0(sm_r[0]), .I1(sm_r[2]), .I2(sm_r[1]), .O(ocd_prech_req_ns)); FDRE ocd_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(ocd_prech_req_ns), .Q(prech_req_r_reg), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'hBFFFFFFF80000000)) oclkdelay_calib_done_r_i_1 (.I0(wrlvl_final_r0), .I1(sm_r[2]), .I2(oclkdelay_calib_done_r_i_3_n_0), .I3(sm_r[0]), .I4(sm_r[1]), .I5(wrlvl_final_mux_reg), .O(oclkdelay_calib_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair354" *) LUT5 #( .INIT(32'h00000002)) oclkdelay_calib_done_r_i_2 (.I0(po_rdy), .I1(po_rd_wait_r_reg__0[0]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[2]), .I4(po_rd_wait_r_reg__0[3]), .O(wrlvl_final_r0)); (* SOFT_HLUTNM = "soft_lutpair353" *) LUT5 #( .INIT(32'h04000000)) oclkdelay_calib_done_r_i_3 (.I0(\po_rd_wait_r[3]_i_6_n_0 ), .I1(po_rdy), .I2(\po_counter_read_val_reg[2] ), .I3(\byte_r_reg[1]_0 ), .I4(\byte_r_reg[0]_0 ), .O(oclkdelay_calib_done_r_i_3_n_0)); FDRE oclkdelay_calib_done_r_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_i_1_n_0), .Q(wrlvl_final_mux_reg), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE phy_rddata_en_r1_reg (.C(CLK), .CE(1'b1), .D(phy_rddata_en), .Q(rd_active_r1_reg), .R(1'b0)); LUT4 #( .INIT(16'h40EF)) \po_rd_wait_r[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(\po_rd_wait_r[0]_i_2_n_0 ), .I2(sm_r[1]), .I3(po_rd_wait_r_reg__0[0]), .O(po_rd_wait_ns[0])); LUT6 #( .INIT(64'h000000004777FFFF)) \po_rd_wait_r[0]_i_2 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1]_0 ), .I4(sm_r[2]), .I5(po_rd_wait_r_reg__0[0]), .O(\po_rd_wait_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'hEFFF40004000EFFF)) \po_rd_wait_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(\po_rd_wait_r[1]_i_2_n_0 ), .I2(sm_r[2]), .I3(sm_r[1]), .I4(po_rd_wait_r_reg__0[0]), .I5(po_rd_wait_r_reg__0[1]), .O(po_rd_wait_ns[1])); LUT6 #( .INIT(64'h4777000000004777)) \po_rd_wait_r[1]_i_2 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1]_0 ), .I4(po_rd_wait_r_reg__0[0]), .I5(po_rd_wait_r_reg__0[1]), .O(\po_rd_wait_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hEF40EF40EF4040EF)) \po_rd_wait_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(\po_rd_wait_r[2]_i_2_n_0 ), .I2(sm_r[1]), .I3(po_rd_wait_r_reg__0[2]), .I4(po_rd_wait_r_reg__0[0]), .I5(po_rd_wait_r_reg__0[1]), .O(po_rd_wait_ns[2])); LUT6 #( .INIT(64'h4777FFFF00000000)) \po_rd_wait_r[2]_i_2 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1]_0 ), .I4(sm_r[2]), .I5(\po_rd_wait_r[2]_i_3_n_0 ), .O(\po_rd_wait_r[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair356" *) LUT3 #( .INIT(8'hA9)) \po_rd_wait_r[2]_i_3 (.I0(po_rd_wait_r_reg__0[2]), .I1(po_rd_wait_r_reg__0[0]), .I2(po_rd_wait_r_reg__0[1]), .O(\po_rd_wait_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \po_rd_wait_r[3]_i_1 (.I0(po_rd_wait_r_reg__0[3]), .I1(po_rd_wait_r_reg__0[2]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[0]), .I4(rstdiv0_sync_r1_reg_rep__26_0), .I5(\po_rd_wait_r[3]_i_3_n_0 ), .O(\po_rd_wait_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF01000000)) \po_rd_wait_r[3]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(sm_r[0]), .I2(\po_rd_wait_r[3]_i_4_n_0 ), .I3(sm_r[2]), .I4(sm_r[1]), .I5(\po_rd_wait_r[3]_i_5_n_0 ), .O(po_rd_wait_ns[3])); LUT6 #( .INIT(64'hFFFFFFFF8B000000)) \po_rd_wait_r[3]_i_3 (.I0(\byte_r[0]_i_2_n_0 ), .I1(sm_r[0]), .I2(\po_rd_wait_r[3]_i_4_n_0 ), .I3(sm_r[2]), .I4(sm_r[1]), .I5(\po_rd_wait_r[3]_i_6_n_0 ), .O(\po_rd_wait_r[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair361" *) LUT2 #( .INIT(4'h7)) \po_rd_wait_r[3]_i_4 (.I0(\byte_r_reg[1]_0 ), .I1(\byte_r_reg[0]_0 ), .O(\po_rd_wait_r[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair356" *) LUT4 #( .INIT(16'hAAA9)) \po_rd_wait_r[3]_i_5 (.I0(po_rd_wait_r_reg__0[3]), .I1(po_rd_wait_r_reg__0[2]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[0]), .O(\po_rd_wait_r[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair354" *) LUT4 #( .INIT(16'hFFFE)) \po_rd_wait_r[3]_i_6 (.I0(po_rd_wait_r_reg__0[3]), .I1(po_rd_wait_r_reg__0[2]), .I2(po_rd_wait_r_reg__0[1]), .I3(po_rd_wait_r_reg__0[0]), .O(\po_rd_wait_r[3]_i_6_n_0 )); FDRE \po_rd_wait_r_reg[0] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[0]), .Q(po_rd_wait_r_reg__0[0]), .R(1'b0)); FDRE \po_rd_wait_r_reg[1] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[1]), .Q(po_rd_wait_r_reg__0[1]), .R(1'b0)); FDRE \po_rd_wait_r_reg[2] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[2]), .Q(po_rd_wait_r_reg__0[2]), .R(1'b0)); FDRE \po_rd_wait_r_reg[3] (.C(CLK), .CE(\po_rd_wait_r[3]_i_1_n_0 ), .D(po_rd_wait_ns[3]), .Q(po_rd_wait_r_reg__0[3]), .R(1'b0)); LUT6 #( .INIT(64'h0080000000000000)) po_rdy_r_i_8 (.I0(sm_r[2]), .I1(\po_counter_read_val_reg[2] ), .I2(po_rdy), .I3(\po_rd_wait_r[3]_i_6_n_0 ), .I4(sm_r[0]), .I5(sm_r[1]), .O(ocd_cntlr2stg2_dec_r)); LUT2 #( .INIT(4'hE)) prech_req_r_i_2__0 (.I0(prech_req_r_reg), .I1(prech_req_r_reg_0), .O(complex_ocal_ref_req)); (* SOFT_HLUTNM = "soft_lutpair358" *) LUT3 #( .INIT(8'h04)) \rd_victim_sel_r[2]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(rd_active_r1_reg), .I2(\data_cnt_r_reg[7] ), .O(\rd_victim_sel_r_reg[0] )); LUT6 #( .INIT(64'hFAFFFFFF40400000)) reset_scan_r_i_1 (.I0(sm_r[2]), .I1(rstdiv0_sync_r1_reg_rep__26), .I2(sm_r[0]), .I3(done_r_reg_0), .I4(sm_r[1]), .I5(reset_scan), .O(reset_scan_r_i_1_n_0)); FDSE reset_scan_r_reg (.C(CLK), .CE(1'b1), .D(reset_scan_r_i_1_n_0), .Q(reset_scan), .S(rstdiv0_sync_r1_reg_rep__9)); (* SOFT_HLUTNM = "soft_lutpair360" *) LUT3 #( .INIT(8'h08)) \simp_stg3_final_r[11]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .O(\simp_stg3_final_r_reg[11] )); (* SOFT_HLUTNM = "soft_lutpair360" *) LUT3 #( .INIT(8'h08)) \simp_stg3_final_r[17]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(\byte_r_reg[1]_0 ), .I2(\byte_r_reg[0]_0 ), .O(\simp_stg3_final_r_reg[17] )); (* SOFT_HLUTNM = "soft_lutpair355" *) LUT3 #( .INIT(8'h80)) \simp_stg3_final_r[23]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .O(\simp_stg3_final_r_reg[23] )); (* SOFT_HLUTNM = "soft_lutpair361" *) LUT3 #( .INIT(8'h02)) \simp_stg3_final_r[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1]_0 ), .O(\simp_stg3_final_r_reg[5] )); LUT4 #( .INIT(16'h0020)) sr_valid_r_i_1 (.I0(rd_active_r1_reg), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(rdlvl_stg1_start_reg), .I3(\cnt_shift_r_reg[0] ), .O(sr_valid_r108_out)); (* SOFT_HLUTNM = "soft_lutpair359" *) LUT3 #( .INIT(8'h04)) \stg3_init_val[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(wrlvl_final_mux_reg), .I2(\simp_stg3_final_r_reg[12] ), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair357" *) LUT3 #( .INIT(8'h04)) \stg3_init_val[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(wrlvl_final_mux_reg), .I2(\simp_stg3_final_r_reg[19] ), .O(D[1])); LUT6 #( .INIT(64'hFFFFFFFFDDDDDDFD)) \stg3_init_val[2]_i_1 (.I0(wrlvl_final_mux_reg), .I1(rstdiv0_sync_r1_reg_rep__26_0), .I2(\simp_stg3_final_r_reg[2] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1]_0 ), .I5(\simp_stg3_final_r_reg[8] ), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair358" *) LUT2 #( .INIT(4'h2)) \stg3_init_val[3]_i_3 (.I0(wrlvl_final_mux_reg), .I1(rstdiv0_sync_r1_reg_rep__25), .O(\stg3_init_val_reg[3] )); LUT6 #( .INIT(64'hFFFFFFFFDDDDFDDD)) \stg3_init_val[4]_i_1 (.I0(wrlvl_final_mux_reg), .I1(rstdiv0_sync_r1_reg_rep__26_0), .I2(\simp_stg3_final_r_reg[16] ), .I3(\byte_r_reg[1]_0 ), .I4(\byte_r_reg[0]_0 ), .I5(\simp_stg3_final_r_reg[10] ), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair357" *) LUT3 #( .INIT(8'h04)) \stg3_init_val[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_0), .I1(wrlvl_final_mux_reg), .I2(\simp_stg3_final_r_reg[17]_0 ), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair359" *) LUT1 #( .INIT(2'h1)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_1 (.I0(wrlvl_final_mux_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] )); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_data (E, \zero_r_reg[9] , \zero_r_reg[9]_0 , \rd_victim_sel_r_reg[0] , agg_samp_r, \byte_r_reg[0] , CLK); output [0:0]E; output \zero_r_reg[9] ; output \zero_r_reg[9]_0 ; input \rd_victim_sel_r_reg[0] ; input [1:0]agg_samp_r; input [63:0]\byte_r_reg[0] ; input CLK; wire CLK; wire [0:0]E; wire [1:0]agg_samp_r; wire [63:0]\byte_r_reg[0] ; wire [63:0]data_bytes_r; wire \rd_victim_sel_r_reg[0] ; wire \zero_r[9]_i_10_n_0 ; wire \zero_r[9]_i_11_n_0 ; wire \zero_r[9]_i_12_n_0 ; wire \zero_r[9]_i_13_n_0 ; wire \zero_r[9]_i_14_n_0 ; wire \zero_r[9]_i_15_n_0 ; wire \zero_r[9]_i_16_n_0 ; wire \zero_r[9]_i_17_n_0 ; wire \zero_r[9]_i_18_n_0 ; wire \zero_r[9]_i_19_n_0 ; wire \zero_r[9]_i_20_n_0 ; wire \zero_r[9]_i_21_n_0 ; wire \zero_r[9]_i_22_n_0 ; wire \zero_r[9]_i_23_n_0 ; wire \zero_r[9]_i_24_n_0 ; wire \zero_r[9]_i_25_n_0 ; wire \zero_r[9]_i_26_n_0 ; wire \zero_r[9]_i_27_n_0 ; wire \zero_r[9]_i_28_n_0 ; wire \zero_r[9]_i_29_n_0 ; wire \zero_r[9]_i_30_n_0 ; wire \zero_r[9]_i_31_n_0 ; wire \zero_r[9]_i_32_n_0 ; wire \zero_r[9]_i_33_n_0 ; wire \zero_r[9]_i_34_n_0 ; wire \zero_r[9]_i_35_n_0 ; wire \zero_r[9]_i_36_n_0 ; wire \zero_r[9]_i_37_n_0 ; wire \zero_r[9]_i_38_n_0 ; wire \zero_r[9]_i_39_n_0 ; wire \zero_r[9]_i_40_n_0 ; wire \zero_r[9]_i_9_n_0 ; wire \zero_r_reg[9] ; wire \zero_r_reg[9]_0 ; FDRE \data_bytes_r_reg[0] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [0]), .Q(data_bytes_r[0]), .R(1'b0)); FDRE \data_bytes_r_reg[10] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [10]), .Q(data_bytes_r[10]), .R(1'b0)); FDRE \data_bytes_r_reg[11] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [11]), .Q(data_bytes_r[11]), .R(1'b0)); FDRE \data_bytes_r_reg[12] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [12]), .Q(data_bytes_r[12]), .R(1'b0)); FDRE \data_bytes_r_reg[13] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [13]), .Q(data_bytes_r[13]), .R(1'b0)); FDRE \data_bytes_r_reg[14] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [14]), .Q(data_bytes_r[14]), .R(1'b0)); FDRE \data_bytes_r_reg[15] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [15]), .Q(data_bytes_r[15]), .R(1'b0)); FDRE \data_bytes_r_reg[16] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [16]), .Q(data_bytes_r[16]), .R(1'b0)); FDRE \data_bytes_r_reg[17] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [17]), .Q(data_bytes_r[17]), .R(1'b0)); FDRE \data_bytes_r_reg[18] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [18]), .Q(data_bytes_r[18]), .R(1'b0)); FDRE \data_bytes_r_reg[19] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [19]), .Q(data_bytes_r[19]), .R(1'b0)); FDRE \data_bytes_r_reg[1] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [1]), .Q(data_bytes_r[1]), .R(1'b0)); FDRE \data_bytes_r_reg[20] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [20]), .Q(data_bytes_r[20]), .R(1'b0)); FDRE \data_bytes_r_reg[21] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [21]), .Q(data_bytes_r[21]), .R(1'b0)); FDRE \data_bytes_r_reg[22] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [22]), .Q(data_bytes_r[22]), .R(1'b0)); FDRE \data_bytes_r_reg[23] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [23]), .Q(data_bytes_r[23]), .R(1'b0)); FDRE \data_bytes_r_reg[24] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [24]), .Q(data_bytes_r[24]), .R(1'b0)); FDRE \data_bytes_r_reg[25] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [25]), .Q(data_bytes_r[25]), .R(1'b0)); FDRE \data_bytes_r_reg[26] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [26]), .Q(data_bytes_r[26]), .R(1'b0)); FDRE \data_bytes_r_reg[27] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [27]), .Q(data_bytes_r[27]), .R(1'b0)); FDRE \data_bytes_r_reg[28] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [28]), .Q(data_bytes_r[28]), .R(1'b0)); FDRE \data_bytes_r_reg[29] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [29]), .Q(data_bytes_r[29]), .R(1'b0)); FDRE \data_bytes_r_reg[2] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [2]), .Q(data_bytes_r[2]), .R(1'b0)); FDRE \data_bytes_r_reg[30] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [30]), .Q(data_bytes_r[30]), .R(1'b0)); FDRE \data_bytes_r_reg[31] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [31]), .Q(data_bytes_r[31]), .R(1'b0)); FDRE \data_bytes_r_reg[32] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [32]), .Q(data_bytes_r[32]), .R(1'b0)); FDRE \data_bytes_r_reg[33] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [33]), .Q(data_bytes_r[33]), .R(1'b0)); FDRE \data_bytes_r_reg[34] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [34]), .Q(data_bytes_r[34]), .R(1'b0)); FDRE \data_bytes_r_reg[35] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [35]), .Q(data_bytes_r[35]), .R(1'b0)); FDRE \data_bytes_r_reg[36] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [36]), .Q(data_bytes_r[36]), .R(1'b0)); FDRE \data_bytes_r_reg[37] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [37]), .Q(data_bytes_r[37]), .R(1'b0)); FDRE \data_bytes_r_reg[38] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [38]), .Q(data_bytes_r[38]), .R(1'b0)); FDRE \data_bytes_r_reg[39] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [39]), .Q(data_bytes_r[39]), .R(1'b0)); FDRE \data_bytes_r_reg[3] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [3]), .Q(data_bytes_r[3]), .R(1'b0)); FDRE \data_bytes_r_reg[40] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [40]), .Q(data_bytes_r[40]), .R(1'b0)); FDRE \data_bytes_r_reg[41] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [41]), .Q(data_bytes_r[41]), .R(1'b0)); FDRE \data_bytes_r_reg[42] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [42]), .Q(data_bytes_r[42]), .R(1'b0)); FDRE \data_bytes_r_reg[43] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [43]), .Q(data_bytes_r[43]), .R(1'b0)); FDRE \data_bytes_r_reg[44] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [44]), .Q(data_bytes_r[44]), .R(1'b0)); FDRE \data_bytes_r_reg[45] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [45]), .Q(data_bytes_r[45]), .R(1'b0)); FDRE \data_bytes_r_reg[46] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [46]), .Q(data_bytes_r[46]), .R(1'b0)); FDRE \data_bytes_r_reg[47] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [47]), .Q(data_bytes_r[47]), .R(1'b0)); FDRE \data_bytes_r_reg[48] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [48]), .Q(data_bytes_r[48]), .R(1'b0)); FDRE \data_bytes_r_reg[49] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [49]), .Q(data_bytes_r[49]), .R(1'b0)); FDRE \data_bytes_r_reg[4] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [4]), .Q(data_bytes_r[4]), .R(1'b0)); FDRE \data_bytes_r_reg[50] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [50]), .Q(data_bytes_r[50]), .R(1'b0)); FDRE \data_bytes_r_reg[51] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [51]), .Q(data_bytes_r[51]), .R(1'b0)); FDRE \data_bytes_r_reg[52] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [52]), .Q(data_bytes_r[52]), .R(1'b0)); FDRE \data_bytes_r_reg[53] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [53]), .Q(data_bytes_r[53]), .R(1'b0)); FDRE \data_bytes_r_reg[54] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [54]), .Q(data_bytes_r[54]), .R(1'b0)); FDRE \data_bytes_r_reg[55] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [55]), .Q(data_bytes_r[55]), .R(1'b0)); FDRE \data_bytes_r_reg[56] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [56]), .Q(data_bytes_r[56]), .R(1'b0)); FDRE \data_bytes_r_reg[57] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [57]), .Q(data_bytes_r[57]), .R(1'b0)); FDRE \data_bytes_r_reg[58] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [58]), .Q(data_bytes_r[58]), .R(1'b0)); FDRE \data_bytes_r_reg[59] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [59]), .Q(data_bytes_r[59]), .R(1'b0)); FDRE \data_bytes_r_reg[5] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [5]), .Q(data_bytes_r[5]), .R(1'b0)); FDRE \data_bytes_r_reg[60] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [60]), .Q(data_bytes_r[60]), .R(1'b0)); FDRE \data_bytes_r_reg[61] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [61]), .Q(data_bytes_r[61]), .R(1'b0)); FDRE \data_bytes_r_reg[62] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [62]), .Q(data_bytes_r[62]), .R(1'b0)); FDRE \data_bytes_r_reg[63] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [63]), .Q(data_bytes_r[63]), .R(1'b0)); FDRE \data_bytes_r_reg[6] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [6]), .Q(data_bytes_r[6]), .R(1'b0)); FDRE \data_bytes_r_reg[7] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [7]), .Q(data_bytes_r[7]), .R(1'b0)); FDRE \data_bytes_r_reg[8] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [8]), .Q(data_bytes_r[8]), .R(1'b0)); FDRE \data_bytes_r_reg[9] (.C(CLK), .CE(1'b1), .D(\byte_r_reg[0] [9]), .Q(data_bytes_r[9]), .R(1'b0)); LUT6 #( .INIT(64'h0000010000000000)) \zero_r[9]_i_10 (.I0(data_bytes_r[53]), .I1(data_bytes_r[52]), .I2(data_bytes_r[48]), .I3(data_bytes_r[58]), .I4(data_bytes_r[1]), .I5(data_bytes_r[59]), .O(\zero_r[9]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \zero_r[9]_i_11 (.I0(\zero_r[9]_i_21_n_0 ), .I1(data_bytes_r[56]), .I2(data_bytes_r[38]), .I3(data_bytes_r[42]), .I4(data_bytes_r[35]), .I5(\zero_r[9]_i_22_n_0 ), .O(\zero_r[9]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \zero_r[9]_i_12 (.I0(\zero_r[9]_i_23_n_0 ), .I1(data_bytes_r[2]), .I2(data_bytes_r[3]), .I3(data_bytes_r[30]), .I4(data_bytes_r[39]), .I5(\zero_r[9]_i_24_n_0 ), .O(\zero_r[9]_i_12_n_0 )); LUT5 #( .INIT(32'hFFFFFF7F)) \zero_r[9]_i_13 (.I0(data_bytes_r[25]), .I1(data_bytes_r[9]), .I2(data_bytes_r[12]), .I3(\zero_r[9]_i_25_n_0 ), .I4(\zero_r[9]_i_26_n_0 ), .O(\zero_r[9]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFBFFFFFF)) \zero_r[9]_i_14 (.I0(\zero_r[9]_i_27_n_0 ), .I1(data_bytes_r[32]), .I2(data_bytes_r[29]), .I3(data_bytes_r[21]), .I4(data_bytes_r[19]), .I5(\zero_r[9]_i_28_n_0 ), .O(\zero_r[9]_i_14_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \zero_r[9]_i_15 (.I0(data_bytes_r[14]), .I1(data_bytes_r[30]), .I2(data_bytes_r[31]), .I3(data_bytes_r[46]), .I4(data_bytes_r[48]), .I5(data_bytes_r[54]), .O(\zero_r[9]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \zero_r[9]_i_16 (.I0(\zero_r[9]_i_29_n_0 ), .I1(data_bytes_r[49]), .I2(data_bytes_r[63]), .I3(data_bytes_r[22]), .I4(data_bytes_r[43]), .I5(\zero_r[9]_i_30_n_0 ), .O(\zero_r[9]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFBFFFFFF)) \zero_r[9]_i_17 (.I0(\zero_r[9]_i_31_n_0 ), .I1(data_bytes_r[53]), .I2(data_bytes_r[11]), .I3(data_bytes_r[7]), .I4(data_bytes_r[18]), .I5(\zero_r[9]_i_32_n_0 ), .O(\zero_r[9]_i_17_n_0 )); LUT5 #( .INIT(32'hFFFFFFDF)) \zero_r[9]_i_18 (.I0(data_bytes_r[36]), .I1(data_bytes_r[24]), .I2(data_bytes_r[4]), .I3(\zero_r[9]_i_33_n_0 ), .I4(\zero_r[9]_i_34_n_0 ), .O(\zero_r[9]_i_18_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_19 (.I0(data_bytes_r[43]), .I1(data_bytes_r[6]), .I2(data_bytes_r[54]), .I3(data_bytes_r[37]), .O(\zero_r[9]_i_19_n_0 )); LUT3 #( .INIT(8'h08)) \zero_r[9]_i_2 (.I0(\zero_r_reg[9] ), .I1(\rd_victim_sel_r_reg[0] ), .I2(\zero_r_reg[9]_0 ), .O(E)); LUT5 #( .INIT(32'hFFFF7FFF)) \zero_r[9]_i_20 (.I0(data_bytes_r[40]), .I1(data_bytes_r[29]), .I2(data_bytes_r[27]), .I3(data_bytes_r[60]), .I4(\zero_r[9]_i_35_n_0 ), .O(\zero_r[9]_i_20_n_0 )); LUT4 #( .INIT(16'hFFDF)) \zero_r[9]_i_21 (.I0(data_bytes_r[44]), .I1(data_bytes_r[20]), .I2(agg_samp_r[0]), .I3(data_bytes_r[55]), .O(\zero_r[9]_i_21_n_0 )); LUT5 #( .INIT(32'hFFFFFFFB)) \zero_r[9]_i_22 (.I0(data_bytes_r[19]), .I1(data_bytes_r[63]), .I2(data_bytes_r[5]), .I3(data_bytes_r[4]), .I4(\zero_r[9]_i_36_n_0 ), .O(\zero_r[9]_i_22_n_0 )); LUT4 #( .INIT(16'hFFF7)) \zero_r[9]_i_23 (.I0(data_bytes_r[61]), .I1(data_bytes_r[31]), .I2(data_bytes_r[32]), .I3(data_bytes_r[23]), .O(\zero_r[9]_i_23_n_0 )); LUT5 #( .INIT(32'hFFFFBFFF)) \zero_r[9]_i_24 (.I0(data_bytes_r[34]), .I1(data_bytes_r[41]), .I2(data_bytes_r[45]), .I3(data_bytes_r[14]), .I4(\zero_r[9]_i_37_n_0 ), .O(\zero_r[9]_i_24_n_0 )); LUT4 #( .INIT(16'hFFDF)) \zero_r[9]_i_25 (.I0(data_bytes_r[57]), .I1(data_bytes_r[16]), .I2(data_bytes_r[26]), .I3(data_bytes_r[17]), .O(\zero_r[9]_i_25_n_0 )); LUT4 #( .INIT(16'hEFFF)) \zero_r[9]_i_26 (.I0(data_bytes_r[22]), .I1(data_bytes_r[51]), .I2(data_bytes_r[13]), .I3(data_bytes_r[28]), .O(\zero_r[9]_i_26_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_27 (.I0(data_bytes_r[6]), .I1(data_bytes_r[9]), .I2(data_bytes_r[12]), .I3(data_bytes_r[60]), .O(\zero_r[9]_i_27_n_0 )); LUT5 #( .INIT(32'hFFFFBFFF)) \zero_r[9]_i_28 (.I0(data_bytes_r[47]), .I1(data_bytes_r[51]), .I2(data_bytes_r[55]), .I3(data_bytes_r[34]), .I4(\zero_r[9]_i_38_n_0 ), .O(\zero_r[9]_i_28_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_29 (.I0(data_bytes_r[39]), .I1(data_bytes_r[13]), .I2(data_bytes_r[26]), .I3(data_bytes_r[57]), .O(\zero_r[9]_i_29_n_0 )); LUT5 #( .INIT(32'hFFFFF7FF)) \zero_r[9]_i_30 (.I0(data_bytes_r[0]), .I1(data_bytes_r[5]), .I2(data_bytes_r[59]), .I3(agg_samp_r[1]), .I4(\zero_r[9]_i_39_n_0 ), .O(\zero_r[9]_i_30_n_0 )); LUT4 #( .INIT(16'hEFFF)) \zero_r[9]_i_31 (.I0(data_bytes_r[25]), .I1(data_bytes_r[10]), .I2(data_bytes_r[20]), .I3(data_bytes_r[33]), .O(\zero_r[9]_i_31_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \zero_r[9]_i_32 (.I0(data_bytes_r[27]), .I1(data_bytes_r[56]), .I2(data_bytes_r[8]), .I3(data_bytes_r[17]), .I4(\zero_r[9]_i_40_n_0 ), .O(\zero_r[9]_i_32_n_0 )); LUT4 #( .INIT(16'hFFF7)) \zero_r[9]_i_33 (.I0(data_bytes_r[23]), .I1(data_bytes_r[50]), .I2(data_bytes_r[41]), .I3(data_bytes_r[44]), .O(\zero_r[9]_i_33_n_0 )); LUT4 #( .INIT(16'hFF7F)) \zero_r[9]_i_34 (.I0(data_bytes_r[16]), .I1(data_bytes_r[35]), .I2(data_bytes_r[38]), .I3(data_bytes_r[62]), .O(\zero_r[9]_i_34_n_0 )); LUT4 #( .INIT(16'hFFFE)) \zero_r[9]_i_35 (.I0(data_bytes_r[49]), .I1(data_bytes_r[33]), .I2(data_bytes_r[18]), .I3(data_bytes_r[36]), .O(\zero_r[9]_i_35_n_0 )); LUT4 #( .INIT(16'hFFDF)) \zero_r[9]_i_36 (.I0(data_bytes_r[10]), .I1(data_bytes_r[7]), .I2(data_bytes_r[8]), .I3(data_bytes_r[21]), .O(\zero_r[9]_i_36_n_0 )); LUT4 #( .INIT(16'h7FFF)) \zero_r[9]_i_37 (.I0(data_bytes_r[15]), .I1(data_bytes_r[47]), .I2(data_bytes_r[46]), .I3(data_bytes_r[11]), .O(\zero_r[9]_i_37_n_0 )); LUT4 #( .INIT(16'hFFFD)) \zero_r[9]_i_38 (.I0(data_bytes_r[52]), .I1(data_bytes_r[61]), .I2(data_bytes_r[15]), .I3(data_bytes_r[45]), .O(\zero_r[9]_i_38_n_0 )); LUT4 #( .INIT(16'hFFFE)) \zero_r[9]_i_39 (.I0(data_bytes_r[42]), .I1(data_bytes_r[28]), .I2(data_bytes_r[40]), .I3(data_bytes_r[58]), .O(\zero_r[9]_i_39_n_0 )); LUT4 #( .INIT(16'h7FFF)) \zero_r[9]_i_40 (.I0(data_bytes_r[2]), .I1(data_bytes_r[3]), .I2(data_bytes_r[1]), .I3(data_bytes_r[37]), .O(\zero_r[9]_i_40_n_0 )); LUT5 #( .INIT(32'h00000004)) \zero_r[9]_i_5 (.I0(\zero_r[9]_i_9_n_0 ), .I1(\zero_r[9]_i_10_n_0 ), .I2(\zero_r[9]_i_11_n_0 ), .I3(\zero_r[9]_i_12_n_0 ), .I4(\zero_r[9]_i_13_n_0 ), .O(\zero_r_reg[9] )); LUT5 #( .INIT(32'h00000004)) \zero_r[9]_i_7 (.I0(\zero_r[9]_i_14_n_0 ), .I1(\zero_r[9]_i_15_n_0 ), .I2(\zero_r[9]_i_16_n_0 ), .I3(\zero_r[9]_i_17_n_0 ), .I4(\zero_r[9]_i_18_n_0 ), .O(\zero_r_reg[9]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \zero_r[9]_i_9 (.I0(\zero_r[9]_i_19_n_0 ), .I1(data_bytes_r[24]), .I2(data_bytes_r[50]), .I3(data_bytes_r[62]), .I4(data_bytes_r[0]), .I5(\zero_r[9]_i_20_n_0 ), .O(\zero_r[9]_i_9_n_0 )); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_edge (prev_samp_valid_r, o2f_r_reg_0, \ninety_offsets_final_r_reg[0] , f2o_r_reg_0, scan_right, prev_samp_r, \ninety_offsets_final_r_reg[1] , dec_po_ns, inc_po_ns, \ninety_offsets_final_r_reg[0]_0 , reset_scan, samp_done_r_reg, CLK, scanning_right_r_reg, scanning_right_r_reg_0, \samp_result_r_reg[1] , \samp_result_r_reg[0] , rd_active_r1_reg, rd_active_r1_reg_0, scanning_right, ocd_ktap_left_r_reg, Q, \stg3_left_lim_reg[5] , rd_active_r1, samp_done, \stg3_right_lim_reg[5] , E, D, reset_scan_r_reg); output prev_samp_valid_r; output o2f_r_reg_0; output \ninety_offsets_final_r_reg[0] ; output f2o_r_reg_0; output scan_right; output [1:0]prev_samp_r; output \ninety_offsets_final_r_reg[1] ; output dec_po_ns; output inc_po_ns; output \ninety_offsets_final_r_reg[0]_0 ; input reset_scan; input samp_done_r_reg; input CLK; input scanning_right_r_reg; input scanning_right_r_reg_0; input \samp_result_r_reg[1] ; input \samp_result_r_reg[0] ; input rd_active_r1_reg; input rd_active_r1_reg_0; input scanning_right; input ocd_ktap_left_r_reg; input [5:0]Q; input [5:0]\stg3_left_lim_reg[5] ; input rd_active_r1; input samp_done; input [5:0]\stg3_right_lim_reg[5] ; input [0:0]E; input [5:0]D; input [0:0]reset_scan_r_reg; wire CLK; wire [5:0]D; wire [0:0]E; wire [5:0]Q; wire dec_po_ns; wire dec_po_r_i_10_n_0; wire dec_po_r_i_11_n_0; wire dec_po_r_i_12_n_0; wire dec_po_r_i_13_n_0; wire dec_po_r_i_14_n_0; wire dec_po_r_i_15_n_0; wire dec_po_r_i_16_n_0; wire dec_po_r_i_17_n_0; wire dec_po_r_i_18_n_0; wire dec_po_r_i_20_n_0; wire dec_po_r_i_21_n_0; wire dec_po_r_i_22_n_0; wire dec_po_r_i_23_n_0; wire dec_po_r_i_24_n_0; wire dec_po_r_i_26_n_0; wire dec_po_r_i_27_n_0; wire dec_po_r_i_28_n_0; wire dec_po_r_i_29_n_0; wire dec_po_r_i_2_n_0; wire dec_po_r_i_30_n_0; wire dec_po_r_i_31_n_0; wire dec_po_r_i_32_n_0; wire dec_po_r_i_3_n_0; wire dec_po_r_i_4_n_0; wire dec_po_r_i_5_n_0; wire dec_po_r_i_6_n_0; wire dec_po_r_i_7_n_0; wire dec_po_r_i_9_n_0; wire dec_po_r_reg_i_19_n_0; wire dec_po_r_reg_i_8_n_0; wire f2o_r_i_1_n_0; wire f2o_r_reg_0; wire \fuzz2oneeighty_r[5]_i_1_n_0 ; wire \fuzz2oneeighty_r[5]_i_2_n_0 ; wire \fuzz2oneeighty_r_reg_n_0_[0] ; wire \fuzz2oneeighty_r_reg_n_0_[1] ; wire \fuzz2oneeighty_r_reg_n_0_[2] ; wire \fuzz2oneeighty_r_reg_n_0_[3] ; wire \fuzz2oneeighty_r_reg_n_0_[4] ; wire \fuzz2oneeighty_r_reg_n_0_[5] ; wire \fuzz2zero_r_reg_n_0_[0] ; wire \fuzz2zero_r_reg_n_0_[1] ; wire \fuzz2zero_r_reg_n_0_[2] ; wire \fuzz2zero_r_reg_n_0_[3] ; wire \fuzz2zero_r_reg_n_0_[4] ; wire \fuzz2zero_r_reg_n_0_[5] ; wire inc_po_ns; wire inc_po_r_i_2_n_0; wire inc_po_r_i_3_n_0; wire inc_po_r_i_4_n_0; wire \ninety_offsets_final_r_reg[0] ; wire \ninety_offsets_final_r_reg[0]_0 ; wire \ninety_offsets_final_r_reg[1] ; wire o2f_r_reg_0; wire ocd_ktap_left_r_reg; wire \oneeighty2fuzz_r_reg_n_0_[0] ; wire \oneeighty2fuzz_r_reg_n_0_[1] ; wire \oneeighty2fuzz_r_reg_n_0_[2] ; wire \oneeighty2fuzz_r_reg_n_0_[3] ; wire \oneeighty2fuzz_r_reg_n_0_[4] ; wire \oneeighty2fuzz_r_reg_n_0_[5] ; wire [1:0]prev_samp_r; wire prev_samp_valid_r; wire rd_active_r1; wire rd_active_r1_reg; wire rd_active_r1_reg_0; wire reset_scan; wire [0:0]reset_scan_r_reg; wire samp_done; wire samp_done_r_reg; wire \samp_result_r_reg[0] ; wire \samp_result_r_reg[1] ; wire scan_right; wire scan_right_r_i_1_n_0; wire scanning_right; wire scanning_right_r_reg; wire scanning_right_r_reg_0; wire [5:0]\stg3_left_lim_reg[5] ; wire [5:0]\stg3_right_lim_reg[5] ; wire \u_ocd_po_cntlr/noise ; wire z2f_r_i_1_n_0; wire z2f_r_reg_n_0; wire zero2fuzz_ns; wire \zero2fuzz_r_reg_n_0_[0] ; wire \zero2fuzz_r_reg_n_0_[1] ; wire \zero2fuzz_r_reg_n_0_[2] ; wire \zero2fuzz_r_reg_n_0_[3] ; wire \zero2fuzz_r_reg_n_0_[4] ; wire \zero2fuzz_r_reg_n_0_[5] ; LUT6 #( .INIT(64'hFEE00000FFFFFEE0)) dec_po_r_i_1 (.I0(dec_po_r_i_2_n_0), .I1(dec_po_r_i_3_n_0), .I2(dec_po_r_i_4_n_0), .I3(Q[4]), .I4(Q[5]), .I5(dec_po_r_i_5_n_0), .O(dec_po_ns)); (* SOFT_HLUTNM = "soft_lutpair364" *) LUT3 #( .INIT(8'h8A)) dec_po_r_i_10 (.I0(\ninety_offsets_final_r_reg[0] ), .I1(z2f_r_reg_n_0), .I2(f2o_r_reg_0), .O(dec_po_r_i_10_n_0)); LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_11 (.I0(\zero2fuzz_r_reg_n_0_[3] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [3]), .I4(\fuzz2oneeighty_r_reg_n_0_[3] ), .O(dec_po_r_i_11_n_0)); LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_12 (.I0(\zero2fuzz_r_reg_n_0_[4] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [4]), .I4(\fuzz2oneeighty_r_reg_n_0_[4] ), .O(dec_po_r_i_12_n_0)); LUT6 #( .INIT(64'h1010001015155515)) dec_po_r_i_13 (.I0(ocd_ktap_left_r_reg), .I1(\zero2fuzz_r_reg_n_0_[4] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(\ninety_offsets_final_r_reg[0] ), .I5(dec_po_r_i_23_n_0), .O(dec_po_r_i_13_n_0)); LUT6 #( .INIT(64'h0000FF00AE00AE00)) dec_po_r_i_14 (.I0(dec_po_r_i_24_n_0), .I1(\u_ocd_po_cntlr/noise ), .I2(\zero2fuzz_r_reg_n_0_[5] ), .I3(ocd_ktap_left_r_reg), .I4(\fuzz2zero_r_reg_n_0_[5] ), .I5(dec_po_r_i_10_n_0), .O(dec_po_r_i_14_n_0)); (* SOFT_HLUTNM = "soft_lutpair365" *) LUT3 #( .INIT(8'h4F)) dec_po_r_i_15 (.I0(\ninety_offsets_final_r_reg[0] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .O(dec_po_r_i_15_n_0)); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_16 (.I0(\fuzz2oneeighty_r_reg_n_0_[5] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [5]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[5] ), .O(dec_po_r_i_16_n_0)); LUT6 #( .INIT(64'h0000000035355535)) dec_po_r_i_17 (.I0(dec_po_r_i_26_n_0), .I1(\zero2fuzz_r_reg_n_0_[1] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(\ninety_offsets_final_r_reg[0] ), .I5(ocd_ktap_left_r_reg), .O(dec_po_r_i_17_n_0)); LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_18 (.I0(\zero2fuzz_r_reg_n_0_[1] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [1]), .I4(\fuzz2oneeighty_r_reg_n_0_[1] ), .O(dec_po_r_i_18_n_0)); LUT6 #( .INIT(64'h008E00FF0000008E)) dec_po_r_i_2 (.I0(Q[1]), .I1(dec_po_r_i_6_n_0), .I2(dec_po_r_i_7_n_0), .I3(inc_po_r_i_3_n_0), .I4(dec_po_r_reg_i_8_n_0), .I5(Q[2]), .O(dec_po_r_i_2_n_0)); LUT5 #( .INIT(32'hEFAA20AA)) dec_po_r_i_20 (.I0(dec_po_r_i_29_n_0), .I1(\ninety_offsets_final_r_reg[0] ), .I2(f2o_r_reg_0), .I3(z2f_r_reg_n_0), .I4(\zero2fuzz_r_reg_n_0_[2] ), .O(dec_po_r_i_20_n_0)); LUT5 #( .INIT(32'hBFBB8088)) dec_po_r_i_21 (.I0(\fuzz2zero_r_reg_n_0_[2] ), .I1(\ninety_offsets_final_r_reg[0] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(dec_po_r_i_30_n_0), .O(dec_po_r_i_21_n_0)); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_22 (.I0(\fuzz2oneeighty_r_reg_n_0_[3] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [3]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[3] ), .O(dec_po_r_i_22_n_0)); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_23 (.I0(\fuzz2oneeighty_r_reg_n_0_[4] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [4]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[4] ), .O(dec_po_r_i_23_n_0)); (* SOFT_HLUTNM = "soft_lutpair364" *) LUT4 #( .INIT(16'h0437)) dec_po_r_i_24 (.I0(\fuzz2oneeighty_r_reg_n_0_[5] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [5]), .O(dec_po_r_i_24_n_0)); (* SOFT_HLUTNM = "soft_lutpair362" *) LUT2 #( .INIT(4'h8)) dec_po_r_i_25 (.I0(f2o_r_reg_0), .I1(z2f_r_reg_n_0), .O(\u_ocd_po_cntlr/noise )); LUT6 #( .INIT(64'hBF8CBF80B380BF80)) dec_po_r_i_26 (.I0(\fuzz2oneeighty_r_reg_n_0_[1] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_right_lim_reg[5] [1]), .I4(o2f_r_reg_0), .I5(\oneeighty2fuzz_r_reg_n_0_[1] ), .O(dec_po_r_i_26_n_0)); LUT5 #( .INIT(32'h8A00BAFF)) dec_po_r_i_27 (.I0(\zero2fuzz_r_reg_n_0_[0] ), .I1(\ninety_offsets_final_r_reg[0] ), .I2(f2o_r_reg_0), .I3(z2f_r_reg_n_0), .I4(dec_po_r_i_31_n_0), .O(dec_po_r_i_27_n_0)); LUT5 #( .INIT(32'hBFBB8088)) dec_po_r_i_28 (.I0(\fuzz2zero_r_reg_n_0_[0] ), .I1(\ninety_offsets_final_r_reg[0] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(dec_po_r_i_32_n_0), .O(dec_po_r_i_28_n_0)); LUT6 #( .INIT(64'hFFAAE2AA00AAE2AA)) dec_po_r_i_29 (.I0(\stg3_right_lim_reg[5] [2]), .I1(o2f_r_reg_0), .I2(\oneeighty2fuzz_r_reg_n_0_[2] ), .I3(f2o_r_reg_0), .I4(z2f_r_reg_n_0), .I5(\fuzz2oneeighty_r_reg_n_0_[2] ), .O(dec_po_r_i_29_n_0)); LUT6 #( .INIT(64'hAEAABFAA00000000)) dec_po_r_i_3 (.I0(dec_po_r_i_9_n_0), .I1(dec_po_r_i_10_n_0), .I2(\fuzz2zero_r_reg_n_0_[3] ), .I3(ocd_ktap_left_r_reg), .I4(dec_po_r_i_11_n_0), .I5(Q[3]), .O(dec_po_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair362" *) LUT5 #( .INIT(32'hBF8CB380)) dec_po_r_i_30 (.I0(\zero2fuzz_r_reg_n_0_[2] ), .I1(f2o_r_reg_0), .I2(z2f_r_reg_n_0), .I3(\stg3_left_lim_reg[5] [2]), .I4(\fuzz2oneeighty_r_reg_n_0_[2] ), .O(dec_po_r_i_30_n_0)); LUT6 #( .INIT(64'h00FF55551D1D5555)) dec_po_r_i_31 (.I0(\stg3_right_lim_reg[5] [0]), .I1(o2f_r_reg_0), .I2(\oneeighty2fuzz_r_reg_n_0_[0] ), .I3(\fuzz2oneeighty_r_reg_n_0_[0] ), .I4(f2o_r_reg_0), .I5(z2f_r_reg_n_0), .O(dec_po_r_i_31_n_0)); (* SOFT_HLUTNM = "soft_lutpair363" *) LUT5 #( .INIT(32'hFACA0ACA)) dec_po_r_i_32 (.I0(\stg3_left_lim_reg[5] [0]), .I1(\fuzz2oneeighty_r_reg_n_0_[0] ), .I2(f2o_r_reg_0), .I3(z2f_r_reg_n_0), .I4(\zero2fuzz_r_reg_n_0_[0] ), .O(dec_po_r_i_32_n_0)); LUT5 #( .INIT(32'hFFFF2070)) dec_po_r_i_4 (.I0(dec_po_r_i_10_n_0), .I1(\fuzz2zero_r_reg_n_0_[4] ), .I2(ocd_ktap_left_r_reg), .I3(dec_po_r_i_12_n_0), .I4(dec_po_r_i_13_n_0), .O(dec_po_r_i_4_n_0)); LUT5 #( .INIT(32'h55544544)) dec_po_r_i_5 (.I0(dec_po_r_i_14_n_0), .I1(ocd_ktap_left_r_reg), .I2(dec_po_r_i_15_n_0), .I3(\zero2fuzz_r_reg_n_0_[5] ), .I4(dec_po_r_i_16_n_0), .O(dec_po_r_i_5_n_0)); LUT5 #( .INIT(32'hABEFAAAA)) dec_po_r_i_6 (.I0(dec_po_r_i_17_n_0), .I1(dec_po_r_i_10_n_0), .I2(dec_po_r_i_18_n_0), .I3(\fuzz2zero_r_reg_n_0_[1] ), .I4(ocd_ktap_left_r_reg), .O(dec_po_r_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair366" *) LUT2 #( .INIT(4'hB)) dec_po_r_i_7 (.I0(dec_po_r_reg_i_19_n_0), .I1(Q[0]), .O(dec_po_r_i_7_n_0)); LUT6 #( .INIT(64'h1010001015155515)) dec_po_r_i_9 (.I0(ocd_ktap_left_r_reg), .I1(\zero2fuzz_r_reg_n_0_[3] ), .I2(z2f_r_reg_n_0), .I3(f2o_r_reg_0), .I4(\ninety_offsets_final_r_reg[0] ), .I5(dec_po_r_i_22_n_0), .O(dec_po_r_i_9_n_0)); MUXF7 dec_po_r_reg_i_19 (.I0(dec_po_r_i_27_n_0), .I1(dec_po_r_i_28_n_0), .O(dec_po_r_reg_i_19_n_0), .S(ocd_ktap_left_r_reg)); MUXF7 dec_po_r_reg_i_8 (.I0(dec_po_r_i_20_n_0), .I1(dec_po_r_i_21_n_0), .O(dec_po_r_reg_i_8_n_0), .S(ocd_ktap_left_r_reg)); LUT6 #( .INIT(64'hFFFFFFFF00000020)) f2o_r_i_1 (.I0(rd_active_r1_reg), .I1(rd_active_r1_reg_0), .I2(scanning_right), .I3(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I4(prev_samp_r[1]), .I5(f2o_r_reg_0), .O(f2o_r_i_1_n_0)); FDRE f2o_r_reg (.C(CLK), .CE(1'b1), .D(f2o_r_i_1_n_0), .Q(f2o_r_reg_0), .R(reset_scan)); FDRE f2z_r_reg (.C(CLK), .CE(1'b1), .D(scanning_right_r_reg_0), .Q(\ninety_offsets_final_r_reg[0] ), .R(reset_scan)); LUT6 #( .INIT(64'h0000000000100000)) \fuzz2oneeighty_r[5]_i_1 (.I0(prev_samp_r[1]), .I1(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I2(scanning_right), .I3(rd_active_r1_reg_0), .I4(rd_active_r1_reg), .I5(reset_scan), .O(\fuzz2oneeighty_r[5]_i_1_n_0 )); LUT3 #( .INIT(8'h7F)) \fuzz2oneeighty_r[5]_i_2 (.I0(prev_samp_valid_r), .I1(rd_active_r1), .I2(samp_done), .O(\fuzz2oneeighty_r[5]_i_2_n_0 )); FDRE \fuzz2oneeighty_r_reg[0] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[0]), .Q(\fuzz2oneeighty_r_reg_n_0_[0] ), .R(1'b0)); FDRE \fuzz2oneeighty_r_reg[1] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[1]), .Q(\fuzz2oneeighty_r_reg_n_0_[1] ), .R(1'b0)); FDRE \fuzz2oneeighty_r_reg[2] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[2]), .Q(\fuzz2oneeighty_r_reg_n_0_[2] ), .R(1'b0)); FDRE \fuzz2oneeighty_r_reg[3] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[3]), .Q(\fuzz2oneeighty_r_reg_n_0_[3] ), .R(1'b0)); FDRE \fuzz2oneeighty_r_reg[4] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[4]), .Q(\fuzz2oneeighty_r_reg_n_0_[4] ), .R(1'b0)); FDRE \fuzz2oneeighty_r_reg[5] (.C(CLK), .CE(\fuzz2oneeighty_r[5]_i_1_n_0 ), .D(Q[5]), .Q(\fuzz2oneeighty_r_reg_n_0_[5] ), .R(1'b0)); FDRE \fuzz2zero_r_reg[0] (.C(CLK), .CE(E), .D(Q[0]), .Q(\fuzz2zero_r_reg_n_0_[0] ), .R(1'b0)); FDRE \fuzz2zero_r_reg[1] (.C(CLK), .CE(E), .D(Q[1]), .Q(\fuzz2zero_r_reg_n_0_[1] ), .R(1'b0)); FDRE \fuzz2zero_r_reg[2] (.C(CLK), .CE(E), .D(Q[2]), .Q(\fuzz2zero_r_reg_n_0_[2] ), .R(1'b0)); FDRE \fuzz2zero_r_reg[3] (.C(CLK), .CE(E), .D(Q[3]), .Q(\fuzz2zero_r_reg_n_0_[3] ), .R(1'b0)); FDRE \fuzz2zero_r_reg[4] (.C(CLK), .CE(E), .D(Q[4]), .Q(\fuzz2zero_r_reg_n_0_[4] ), .R(1'b0)); FDRE \fuzz2zero_r_reg[5] (.C(CLK), .CE(E), .D(Q[5]), .Q(\fuzz2zero_r_reg_n_0_[5] ), .R(1'b0)); LUT6 #( .INIT(64'h70F770F770F710F1)) inc_po_r_i_1 (.I0(dec_po_r_i_4_n_0), .I1(Q[4]), .I2(dec_po_r_i_5_n_0), .I3(Q[5]), .I4(inc_po_r_i_2_n_0), .I5(inc_po_r_i_3_n_0), .O(inc_po_ns)); LUT6 #( .INIT(64'h0000000071FF0071)) inc_po_r_i_2 (.I0(dec_po_r_i_6_n_0), .I1(Q[1]), .I2(inc_po_r_i_4_n_0), .I3(Q[2]), .I4(dec_po_r_reg_i_8_n_0), .I5(dec_po_r_i_3_n_0), .O(inc_po_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000051554055)) inc_po_r_i_3 (.I0(dec_po_r_i_9_n_0), .I1(dec_po_r_i_10_n_0), .I2(\fuzz2zero_r_reg_n_0_[3] ), .I3(ocd_ktap_left_r_reg), .I4(dec_po_r_i_11_n_0), .I5(Q[3]), .O(inc_po_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair366" *) LUT2 #( .INIT(4'h2)) inc_po_r_i_4 (.I0(dec_po_r_reg_i_19_n_0), .I1(Q[0]), .O(inc_po_r_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair365" *) LUT3 #( .INIT(8'h20)) \ninety_offsets_final_r[0]_i_1 (.I0(f2o_r_reg_0), .I1(\ninety_offsets_final_r_reg[0] ), .I2(z2f_r_reg_n_0), .O(\ninety_offsets_final_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair363" *) LUT2 #( .INIT(4'h2)) \ninety_offsets_final_r[1]_i_1 (.I0(f2o_r_reg_0), .I1(z2f_r_reg_n_0), .O(\ninety_offsets_final_r_reg[1] )); FDRE o2f_r_reg (.C(CLK), .CE(1'b1), .D(scanning_right_r_reg), .Q(o2f_r_reg_0), .R(reset_scan)); FDRE \oneeighty2fuzz_r_reg[0] (.C(CLK), .CE(reset_scan_r_reg), .D(D[0]), .Q(\oneeighty2fuzz_r_reg_n_0_[0] ), .R(1'b0)); FDRE \oneeighty2fuzz_r_reg[1] (.C(CLK), .CE(reset_scan_r_reg), .D(D[1]), .Q(\oneeighty2fuzz_r_reg_n_0_[1] ), .R(1'b0)); FDRE \oneeighty2fuzz_r_reg[2] (.C(CLK), .CE(reset_scan_r_reg), .D(D[2]), .Q(\oneeighty2fuzz_r_reg_n_0_[2] ), .R(1'b0)); FDRE \oneeighty2fuzz_r_reg[3] (.C(CLK), .CE(reset_scan_r_reg), .D(D[3]), .Q(\oneeighty2fuzz_r_reg_n_0_[3] ), .R(1'b0)); FDRE \oneeighty2fuzz_r_reg[4] (.C(CLK), .CE(reset_scan_r_reg), .D(D[4]), .Q(\oneeighty2fuzz_r_reg_n_0_[4] ), .R(1'b0)); FDRE \oneeighty2fuzz_r_reg[5] (.C(CLK), .CE(reset_scan_r_reg), .D(D[5]), .Q(\oneeighty2fuzz_r_reg_n_0_[5] ), .R(1'b0)); FDRE \prev_samp_r_reg[0] (.C(CLK), .CE(1'b1), .D(\samp_result_r_reg[0] ), .Q(prev_samp_r[0]), .R(1'b0)); FDRE \prev_samp_r_reg[1] (.C(CLK), .CE(1'b1), .D(\samp_result_r_reg[1] ), .Q(prev_samp_r[1]), .R(1'b0)); FDRE prev_samp_valid_r_reg (.C(CLK), .CE(1'b1), .D(samp_done_r_reg), .Q(prev_samp_valid_r), .R(reset_scan)); LUT6 #( .INIT(64'h0000000000000010)) scan_right_r_i_1 (.I0(rd_active_r1_reg_0), .I1(scanning_right), .I2(prev_samp_r[0]), .I3(prev_samp_r[1]), .I4(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I5(reset_scan), .O(scan_right_r_i_1_n_0)); FDRE scan_right_r_reg (.C(CLK), .CE(1'b1), .D(scan_right_r_i_1_n_0), .Q(scan_right), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00000400)) z2f_r_i_1 (.I0(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I1(scanning_right), .I2(rd_active_r1_reg_0), .I3(prev_samp_r[0]), .I4(prev_samp_r[1]), .I5(z2f_r_reg_n_0), .O(z2f_r_i_1_n_0)); FDRE z2f_r_reg (.C(CLK), .CE(1'b1), .D(z2f_r_i_1_n_0), .Q(z2f_r_reg_n_0), .R(reset_scan)); LUT6 #( .INIT(64'h0000000000000400)) \zero2fuzz_r[5]_i_1 (.I0(prev_samp_r[1]), .I1(prev_samp_r[0]), .I2(rd_active_r1_reg_0), .I3(scanning_right), .I4(\fuzz2oneeighty_r[5]_i_2_n_0 ), .I5(reset_scan), .O(zero2fuzz_ns)); FDRE \zero2fuzz_r_reg[0] (.C(CLK), .CE(zero2fuzz_ns), .D(D[0]), .Q(\zero2fuzz_r_reg_n_0_[0] ), .R(1'b0)); FDRE \zero2fuzz_r_reg[1] (.C(CLK), .CE(zero2fuzz_ns), .D(D[1]), .Q(\zero2fuzz_r_reg_n_0_[1] ), .R(1'b0)); FDRE \zero2fuzz_r_reg[2] (.C(CLK), .CE(zero2fuzz_ns), .D(D[2]), .Q(\zero2fuzz_r_reg_n_0_[2] ), .R(1'b0)); FDRE \zero2fuzz_r_reg[3] (.C(CLK), .CE(zero2fuzz_ns), .D(D[3]), .Q(\zero2fuzz_r_reg_n_0_[3] ), .R(1'b0)); FDRE \zero2fuzz_r_reg[4] (.C(CLK), .CE(zero2fuzz_ns), .D(D[4]), .Q(\zero2fuzz_r_reg_n_0_[4] ), .R(1'b0)); FDRE \zero2fuzz_r_reg[5] (.C(CLK), .CE(zero2fuzz_ns), .D(D[5]), .Q(\zero2fuzz_r_reg_n_0_[5] ), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_lim (lim_start_r, lim2poc_ktap_right, prech_req_r_reg_0, lim2stg2_inc, lim2stg3_dec, lim2stg3_inc, lim2stg2_dec, lim2poc_rdy, done_r_reg_0, po_stg23_sel_r_reg, stg3_dec2init_val_r_reg_0, stg3_inc2init_val_r_reg_0, \stg2_tap_cnt_reg[0]_0 , \stg2_tap_cnt_reg[3]_0 , \stg3_tap_cnt_reg[2]_0 , scanning_right_r_reg, scanning_right_r_reg_0, oclkdelay_center_calib_start_r_reg, oclkdelay_center_calib_start_r_reg_0, \init_state_r_reg[6] , \init_state_r_reg[5] , \init_state_r_reg[4] , rstdiv0_sync_r1_reg_rep__10, CLK, lim_start, done_r_reg_1, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__26, \po_wait_r_reg[0] , \sm_r_reg[2] , lim_start_r_reg_0, prech_done, \wl_po_fine_cnt_reg[17] , rstdiv0_sync_r1_reg_rep__20, \byte_r_reg[0] , Q, \stg2_tap_cnt_reg[2]_0 , \wl_po_fine_cnt_reg[3] , \wl_po_fine_cnt_reg[14] , \wl_po_fine_cnt_reg[18] , \rise_lead_r_reg[5] , rstdiv0_sync_r1_reg_rep__26_0, po_rdy, scan_right, scanning_right, \stg3_r_reg[5] , o2f_r_reg, \mmcm_init_trail_reg[0]_0 , \mmcm_current_reg[0]_0 , prbs_rdlvl_done_reg_rep, ocd_prech_req_r_reg, oclk_center_write_resume, cnt_cmd_done_r, rstdiv0_sync_r1_reg_rep__19, rstdiv0_sync_r1_reg_rep__11, D, oclkdelay_calib_done_r_reg); output lim_start_r; output lim2poc_ktap_right; output prech_req_r_reg_0; output lim2stg2_inc; output lim2stg3_dec; output lim2stg3_inc; output lim2stg2_dec; output lim2poc_rdy; output done_r_reg_0; output po_stg23_sel_r_reg; output stg3_dec2init_val_r_reg_0; output stg3_inc2init_val_r_reg_0; output \stg2_tap_cnt_reg[0]_0 ; output [2:0]\stg2_tap_cnt_reg[3]_0 ; output [2:0]\stg3_tap_cnt_reg[2]_0 ; output scanning_right_r_reg; output [5:0]scanning_right_r_reg_0; output oclkdelay_center_calib_start_r_reg; output [5:0]oclkdelay_center_calib_start_r_reg_0; output \init_state_r_reg[6] ; output \init_state_r_reg[5] ; output \init_state_r_reg[4] ; input rstdiv0_sync_r1_reg_rep__10; input CLK; input lim_start; input done_r_reg_1; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__26; input \po_wait_r_reg[0] ; input \sm_r_reg[2] ; input lim_start_r_reg_0; input prech_done; input \wl_po_fine_cnt_reg[17] ; input rstdiv0_sync_r1_reg_rep__20; input \byte_r_reg[0] ; input [5:0]Q; input \stg2_tap_cnt_reg[2]_0 ; input \wl_po_fine_cnt_reg[3] ; input [1:0]\wl_po_fine_cnt_reg[14] ; input \wl_po_fine_cnt_reg[18] ; input [5:0]\rise_lead_r_reg[5] ; input rstdiv0_sync_r1_reg_rep__26_0; input po_rdy; input scan_right; input scanning_right; input [5:0]\stg3_r_reg[5] ; input o2f_r_reg; input \mmcm_init_trail_reg[0]_0 ; input \mmcm_current_reg[0]_0 ; input prbs_rdlvl_done_reg_rep; input ocd_prech_req_r_reg; input oclk_center_write_resume; input cnt_cmd_done_r; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [0:0]rstdiv0_sync_r1_reg_rep__11; input [2:0]D; input [5:0]oclkdelay_calib_done_r_reg; wire CLK; wire [2:0]D; wire [5:0]Q; wire \byte_r_reg[0] ; wire cnt_cmd_done_r; wire detect_done_r; wire done_r_i_1__0_n_0; wire done_r_reg_0; wire done_r_reg_1; wire \init_state_r_reg[4] ; wire \init_state_r_reg[5] ; wire \init_state_r_reg[6] ; wire ktap_right_r_i_1_n_0; wire ktap_right_r_i_2_n_0; wire lim2init_write_request; wire lim2poc_ktap_right; wire lim2poc_rdy; wire lim2stg2_dec; wire lim2stg2_inc; wire lim2stg3_dec; wire lim2stg3_inc; wire lim_nxt_state; wire lim_start; wire lim_start_r; wire lim_start_r_reg_0; wire [13:0]lim_state; wire \lim_state[0]_i_1_n_0 ; wire \lim_state[0]_i_2_n_0 ; wire \lim_state[0]_i_3_n_0 ; wire \lim_state[0]_i_4_n_0 ; wire \lim_state[0]_i_5_n_0 ; wire \lim_state[10]_i_1_n_0 ; wire \lim_state[10]_i_2_n_0 ; wire \lim_state[10]_i_3_n_0 ; wire \lim_state[11]_i_1_n_0 ; wire \lim_state[11]_i_2_n_0 ; wire \lim_state[11]_i_3_n_0 ; wire \lim_state[11]_i_4_n_0 ; wire \lim_state[11]_i_5_n_0 ; wire \lim_state[11]_i_6_n_0 ; wire \lim_state[11]_i_7_n_0 ; wire \lim_state[12]_i_1_n_0 ; wire \lim_state[12]_i_2_n_0 ; wire \lim_state[12]_i_3_n_0 ; wire \lim_state[12]_i_4_n_0 ; wire \lim_state[12]_i_5_n_0 ; wire \lim_state[12]_i_7_n_0 ; wire \lim_state[13]_i_10_n_0 ; wire \lim_state[13]_i_11_n_0 ; wire \lim_state[13]_i_12_n_0 ; wire \lim_state[13]_i_13_n_0 ; wire \lim_state[13]_i_14_n_0 ; wire \lim_state[13]_i_2_n_0 ; wire \lim_state[13]_i_3_n_0 ; wire \lim_state[13]_i_4_n_0 ; wire \lim_state[13]_i_5_n_0 ; wire \lim_state[13]_i_6_n_0 ; wire \lim_state[13]_i_7_n_0 ; wire \lim_state[13]_i_8_n_0 ; wire \lim_state[13]_i_9_n_0 ; wire \lim_state[1]_i_1_n_0 ; wire \lim_state[1]_i_2_n_0 ; wire \lim_state[2]_i_1_n_0 ; wire \lim_state[2]_i_2_n_0 ; wire \lim_state[2]_i_3_n_0 ; wire \lim_state[2]_i_4_n_0 ; wire \lim_state[3]_i_1_n_0 ; wire \lim_state[4]_i_1_n_0 ; wire \lim_state[4]_i_2_n_0 ; wire \lim_state[4]_i_3_n_0 ; wire \lim_state[5]_i_1_n_0 ; wire \lim_state[5]_i_2_n_0 ; wire \lim_state[6]_i_10_n_0 ; wire \lim_state[6]_i_11_n_0 ; wire \lim_state[6]_i_12_n_0 ; wire \lim_state[6]_i_13_n_0 ; wire \lim_state[6]_i_14_n_0 ; wire \lim_state[6]_i_15_n_0 ; wire \lim_state[6]_i_16_n_0 ; wire \lim_state[6]_i_17_n_0 ; wire \lim_state[6]_i_18_n_0 ; wire \lim_state[6]_i_19_n_0 ; wire \lim_state[6]_i_1_n_0 ; wire \lim_state[6]_i_20_n_0 ; wire \lim_state[6]_i_21_n_0 ; wire \lim_state[6]_i_22_n_0 ; wire \lim_state[6]_i_2_n_0 ; wire \lim_state[6]_i_3_n_0 ; wire \lim_state[6]_i_4_n_0 ; wire \lim_state[6]_i_5_n_0 ; wire \lim_state[6]_i_6_n_0 ; wire \lim_state[6]_i_7_n_0 ; wire \lim_state[6]_i_8_n_0 ; wire \lim_state[6]_i_9_n_0 ; wire \lim_state[7]_i_1_n_0 ; wire \lim_state[7]_i_2_n_0 ; wire \lim_state[7]_i_3_n_0 ; wire \lim_state[8]_i_1_n_0 ; wire \lim_state[9]_i_1_n_0 ; wire \lim_state[9]_i_2_n_0 ; wire \lim_state[9]_i_3_n_0 ; wire \mmcm_current[0]_i_1_n_0 ; wire \mmcm_current[0]_i_2_n_0 ; wire \mmcm_current[1]_i_1_n_0 ; wire \mmcm_current[1]_i_2_n_0 ; wire \mmcm_current[2]_i_1_n_0 ; wire \mmcm_current[2]_i_2_n_0 ; wire \mmcm_current[3]_i_1_n_0 ; wire \mmcm_current[3]_i_2_n_0 ; wire \mmcm_current[4]_i_1_n_0 ; wire \mmcm_current[4]_i_2_n_0 ; wire \mmcm_current[5]_i_1_n_0 ; wire \mmcm_current[5]_i_2_n_0 ; wire \mmcm_current_reg[0]_0 ; wire \mmcm_current_reg_n_0_[0] ; wire \mmcm_current_reg_n_0_[1] ; wire \mmcm_current_reg_n_0_[2] ; wire \mmcm_current_reg_n_0_[3] ; wire \mmcm_current_reg_n_0_[4] ; wire \mmcm_current_reg_n_0_[5] ; wire mmcm_init_lead; wire \mmcm_init_lead[5]_i_2_n_0 ; wire \mmcm_init_lead[5]_i_3_n_0 ; wire \mmcm_init_lead[5]_i_4_n_0 ; wire \mmcm_init_lead[5]_i_5_n_0 ; wire \mmcm_init_lead[5]_i_6_n_0 ; wire \mmcm_init_lead[5]_i_7_n_0 ; wire \mmcm_init_lead[5]_i_8_n_0 ; wire \mmcm_init_lead_reg_n_0_[0] ; wire \mmcm_init_lead_reg_n_0_[1] ; wire \mmcm_init_lead_reg_n_0_[2] ; wire \mmcm_init_lead_reg_n_0_[3] ; wire \mmcm_init_lead_reg_n_0_[4] ; wire \mmcm_init_lead_reg_n_0_[5] ; wire mmcm_init_trail; wire \mmcm_init_trail[5]_i_2_n_0 ; wire \mmcm_init_trail[5]_i_3_n_0 ; wire \mmcm_init_trail[5]_i_4_n_0 ; wire \mmcm_init_trail_reg[0]_0 ; wire \mmcm_init_trail_reg_n_0_[0] ; wire \mmcm_init_trail_reg_n_0_[1] ; wire \mmcm_init_trail_reg_n_0_[2] ; wire \mmcm_init_trail_reg_n_0_[3] ; wire \mmcm_init_trail_reg_n_0_[4] ; wire \mmcm_init_trail_reg_n_0_[5] ; wire mod_sub0_return0__14_carry__0_i_1_n_0; wire mod_sub0_return0__14_carry__0_i_2_n_0; wire mod_sub0_return0__14_carry__0_n_1; wire mod_sub0_return0__14_carry__0_n_3; wire mod_sub0_return0__14_carry__0_n_6; wire mod_sub0_return0__14_carry__0_n_7; wire mod_sub0_return0__14_carry_i_1_n_0; wire mod_sub0_return0__14_carry_i_2_n_0; wire mod_sub0_return0__14_carry_i_3_n_0; wire mod_sub0_return0__14_carry_i_4_n_0; wire mod_sub0_return0__14_carry_n_0; wire mod_sub0_return0__14_carry_n_1; wire mod_sub0_return0__14_carry_n_2; wire mod_sub0_return0__14_carry_n_3; wire mod_sub0_return0__14_carry_n_4; wire mod_sub0_return0__14_carry_n_5; wire mod_sub0_return0__14_carry_n_6; wire mod_sub0_return0_carry__0_i_1_n_0; wire mod_sub0_return0_carry__0_i_2_n_0; wire mod_sub0_return0_carry__0_i_3_n_0; wire mod_sub0_return0_carry__0_i_4_n_0; wire mod_sub0_return0_carry__0_i_5_n_0; wire mod_sub0_return0_carry__0_n_2; wire mod_sub0_return0_carry__0_n_3; wire mod_sub0_return0_carry__0_n_5; wire mod_sub0_return0_carry__0_n_6; wire mod_sub0_return0_carry__0_n_7; wire mod_sub0_return0_carry_i_1_n_0; wire mod_sub0_return0_carry_i_2_n_0; wire mod_sub0_return0_carry_i_3_n_0; wire mod_sub0_return0_carry_i_4_n_0; wire mod_sub0_return0_carry_n_0; wire mod_sub0_return0_carry_n_1; wire mod_sub0_return0_carry_n_2; wire mod_sub0_return0_carry_n_3; wire mod_sub0_return0_carry_n_4; wire mod_sub0_return0_carry_n_5; wire mod_sub0_return0_carry_n_6; wire mod_sub0_return0_carry_n_7; wire mod_sub_return0__14_carry__0_i_1_n_0; wire mod_sub_return0__14_carry__0_i_2_n_0; wire mod_sub_return0__14_carry__0_n_1; wire mod_sub_return0__14_carry__0_n_3; wire mod_sub_return0__14_carry__0_n_6; wire mod_sub_return0__14_carry__0_n_7; wire mod_sub_return0__14_carry_i_1_n_0; wire mod_sub_return0__14_carry_i_2_n_0; wire mod_sub_return0__14_carry_i_3_n_0; wire mod_sub_return0__14_carry_i_4_n_0; wire mod_sub_return0__14_carry_n_0; wire mod_sub_return0__14_carry_n_1; wire mod_sub_return0__14_carry_n_2; wire mod_sub_return0__14_carry_n_3; wire mod_sub_return0__14_carry_n_4; wire mod_sub_return0__14_carry_n_5; wire mod_sub_return0__14_carry_n_6; wire mod_sub_return0_carry__0_i_1__0_n_0; wire mod_sub_return0_carry__0_i_2_n_0; wire mod_sub_return0_carry__0_i_3_n_0; wire mod_sub_return0_carry__0_i_4_n_0; wire mod_sub_return0_carry__0_i_5_n_0; wire mod_sub_return0_carry__0_n_2; wire mod_sub_return0_carry__0_n_3; wire mod_sub_return0_carry__0_n_5; wire mod_sub_return0_carry__0_n_6; wire mod_sub_return0_carry__0_n_7; wire mod_sub_return0_carry_i_1__0_n_0; wire mod_sub_return0_carry_i_2_n_0; wire mod_sub_return0_carry_i_3_n_0; wire mod_sub_return0_carry_i_4_n_0; wire mod_sub_return0_carry_n_0; wire mod_sub_return0_carry_n_1; wire mod_sub_return0_carry_n_2; wire mod_sub_return0_carry_n_3; wire mod_sub_return0_carry_n_4; wire mod_sub_return0_carry_n_5; wire mod_sub_return0_carry_n_6; wire mod_sub_return0_carry_n_7; wire o2f_r_reg; wire ocd_prech_req_r_reg; wire oclk_center_write_resume; wire [5:0]oclkdelay_calib_done_r_reg; wire oclkdelay_center_calib_start_r_i_3_n_0; wire oclkdelay_center_calib_start_r_i_4_n_0; wire oclkdelay_center_calib_start_r_reg; wire [5:0]oclkdelay_center_calib_start_r_reg_0; wire [3:0]p_0_in; wire [5:0]p_0_in__0; wire po_rdy; wire po_stg23_sel_r_reg; wire \po_wait_r_reg[0] ; wire poc_ready_r_i_1_n_0; wire prbs_rdlvl_done_reg_rep; wire prech_done; wire prech_req_r_i_1__0_n_0; wire prech_req_r_i_2_n_0; wire prech_req_r_reg_0; wire [5:0]\rise_lead_r_reg[5] ; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__9; wire scan_right; wire scanning_right; wire scanning_right_r_i_4_n_0; wire scanning_right_r_i_5_n_0; wire scanning_right_r_reg; wire [5:0]scanning_right_r_reg_0; wire \sm_r_reg[2] ; wire stg2_dec_req_r_i_1_n_0; wire stg2_inc_r; wire stg2_inc_r_i_1_n_0; wire stg2_inc_r_i_2_n_0; wire stg2_inc_r_i_3_n_0; wire stg2_inc_r_i_4_n_0; wire stg2_inc_req_r_i_1_n_0; wire stg2_inc_req_r_i_2_n_0; wire stg2_tap_cnt0; wire \stg2_tap_cnt[1]_i_3_n_0 ; wire \stg2_tap_cnt[1]_i_4_n_0 ; wire \stg2_tap_cnt[2]_i_3_n_0 ; wire \stg2_tap_cnt[2]_i_4_n_0 ; wire \stg2_tap_cnt[2]_i_5_n_0 ; wire \stg2_tap_cnt[2]_i_6_n_0 ; wire \stg2_tap_cnt[3]_i_3_n_0 ; wire \stg2_tap_cnt[4]_i_3_n_0 ; wire \stg2_tap_cnt[5]_i_6_n_0 ; wire \stg2_tap_cnt_reg[0]_0 ; wire \stg2_tap_cnt_reg[2]_0 ; wire [2:0]\stg2_tap_cnt_reg[3]_0 ; wire [5:3]stg2_tap_cnt_reg__0; wire stg3_dec2init_val_r; wire stg3_dec2init_val_r1; wire stg3_dec2init_val_r_i_10_n_0; wire stg3_dec2init_val_r_i_12_n_0; wire stg3_dec2init_val_r_i_13_n_0; wire stg3_dec2init_val_r_i_1_n_0; wire stg3_dec2init_val_r_i_2_n_0; wire stg3_dec2init_val_r_i_3_n_0; wire stg3_dec2init_val_r_i_4_n_0; wire stg3_dec2init_val_r_i_5_n_0; wire stg3_dec2init_val_r_i_6_n_0; wire stg3_dec2init_val_r_i_7_n_0; wire stg3_dec2init_val_r_i_8_n_0; wire stg3_dec2init_val_r_i_9_n_0; wire stg3_dec2init_val_r_reg_0; wire stg3_dec_r; wire stg3_dec_r_i_1_n_0; wire stg3_dec_r_i_2_n_0; wire stg3_dec_r_i_3_n_0; wire stg3_dec_r_i_4_n_0; wire stg3_dec_r_i_5_n_0; wire stg3_dec_req_r_i_1_n_0; wire stg3_dec_req_r_i_2_n_0; wire stg3_dec_req_r_i_3_n_0; wire [5:0]stg3_dec_val; wire [4:3]stg3_dec_val00_out; wire \stg3_dec_val[5]_i_1_n_0 ; wire \stg3_dec_val[5]_i_2_n_0 ; wire \stg3_dec_val[5]_i_3_n_0 ; wire stg3_inc2init_val_r; wire stg3_inc2init_val_r1; wire stg3_inc2init_val_r_i_1_n_0; wire stg3_inc2init_val_r_i_2_n_0; wire stg3_inc2init_val_r_i_3_n_0; wire stg3_inc2init_val_r_reg_0; wire stg3_inc_req_r_i_1_n_0; wire [5:0]stg3_inc_val; wire \stg3_inc_val[0]_i_1_n_0 ; wire \stg3_inc_val[1]_i_1_n_0 ; wire \stg3_inc_val[2]_i_1_n_0 ; wire \stg3_inc_val[2]_i_2_n_0 ; wire \stg3_inc_val[3]_i_1_n_0 ; wire \stg3_inc_val[3]_i_2_n_0 ; wire \stg3_inc_val[4]_i_1_n_0 ; wire \stg3_inc_val[5]_i_1_n_0 ; wire \stg3_inc_val[5]_i_2_n_0 ; wire \stg3_inc_val[5]_i_3_n_0 ; wire stg3_init_dec_r; wire stg3_init_dec_r_i_1_n_0; wire stg3_init_dec_r_i_2_n_0; wire stg3_init_dec_r_i_3_n_0; wire stg3_init_dec_r_i_4_n_0; wire [5:3]stg3_init_val; wire stg3_left_lim0; wire \stg3_left_lim[5]_i_1_n_0 ; wire [5:0]\stg3_r_reg[5] ; wire stg3_right_lim0; wire \stg3_right_lim[5]_i_1_n_0 ; wire stg3_tap_cnt0; wire \stg3_tap_cnt[0]_i_1_n_0 ; wire \stg3_tap_cnt[1]_i_1_n_0 ; wire \stg3_tap_cnt[1]_i_2_n_0 ; wire \stg3_tap_cnt[2]_i_1_n_0 ; wire \stg3_tap_cnt[2]_i_2_n_0 ; wire \stg3_tap_cnt[3]_i_1_n_0 ; wire \stg3_tap_cnt[3]_i_2_n_0 ; wire \stg3_tap_cnt[3]_i_3_n_0 ; wire \stg3_tap_cnt[3]_i_4_n_0 ; wire \stg3_tap_cnt[4]_i_1_n_0 ; wire \stg3_tap_cnt[5]_i_2_n_0 ; wire \stg3_tap_cnt[5]_i_4_n_0 ; wire \stg3_tap_cnt[5]_i_5_n_0 ; wire \stg3_tap_cnt[5]_i_6_n_0 ; wire [2:0]\stg3_tap_cnt_reg[2]_0 ; wire \stg3_tap_cnt_reg_n_0_[0] ; wire \stg3_tap_cnt_reg_n_0_[1] ; wire \stg3_tap_cnt_reg_n_0_[2] ; wire \stg3_tap_cnt_reg_n_0_[3] ; wire \stg3_tap_cnt_reg_n_0_[4] ; wire \stg3_tap_cnt_reg_n_0_[5] ; wire wait_cnt_done; wire wait_cnt_done_i_1_n_0; wire wait_cnt_en_r; wire wait_cnt_en_r0; wire wait_cnt_en_r_i_2_n_0; wire wait_cnt_en_r_i_3_n_0; wire \wait_cnt_r[3]_i_1_n_0 ; wire [3:0]wait_cnt_r_reg__0; wire [1:0]\wl_po_fine_cnt_reg[14] ; wire \wl_po_fine_cnt_reg[17] ; wire \wl_po_fine_cnt_reg[18] ; wire \wl_po_fine_cnt_reg[3] ; wire write_request_r_i_1_n_0; wire write_request_r_i_2_n_0; wire [0:0]NLW_mod_sub0_return0__14_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED; wire [3:2]NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_mod_sub0_return0_carry__0_O_UNCONNECTED; wire [0:0]NLW_mod_sub_return0__14_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED; wire [3:2]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_mod_sub_return0_carry__0_O_UNCONNECTED; FDRE detect_done_r_reg (.C(CLK), .CE(1'b1), .D(done_r_reg_1), .Q(detect_done_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFF7FFF00880000)) done_r_i_1__0 (.I0(\lim_state[0]_i_2_n_0 ), .I1(\lim_state[4]_i_3_n_0 ), .I2(lim_start_r_reg_0), .I3(lim_state[0]), .I4(lim_state[13]), .I5(done_r_reg_0), .O(done_r_i_1__0_n_0)); FDRE done_r_reg (.C(CLK), .CE(1'b1), .D(done_r_i_1__0_n_0), .Q(done_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__9)); (* SOFT_HLUTNM = "soft_lutpair391" *) LUT3 #( .INIT(8'h02)) \init_state_r[4]_i_35 (.I0(cnt_cmd_done_r), .I1(prech_req_r_reg_0), .I2(ocd_prech_req_r_reg), .O(\init_state_r_reg[4] )); LUT2 #( .INIT(4'hE)) \init_state_r[5]_i_37 (.I0(lim2init_write_request), .I1(oclk_center_write_resume), .O(\init_state_r_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair391" *) LUT3 #( .INIT(8'hFE)) \init_state_r[6]_i_6 (.I0(prbs_rdlvl_done_reg_rep), .I1(prech_req_r_reg_0), .I2(ocd_prech_req_r_reg), .O(\init_state_r_reg[6] )); LUT6 #( .INIT(64'hFFEFFFFF01000000)) ktap_right_r_i_1 (.I0(\lim_state[13]_i_7_n_0 ), .I1(lim_state[0]), .I2(lim_state[13]), .I3(lim_state[1]), .I4(ktap_right_r_i_2_n_0), .I5(lim2poc_ktap_right), .O(ktap_right_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair383" *) LUT4 #( .INIT(16'h0001)) ktap_right_r_i_2 (.I0(lim_state[9]), .I1(lim_state[12]), .I2(lim_state[10]), .I3(lim_state[11]), .O(ktap_right_r_i_2_n_0)); FDRE ktap_right_r_reg (.C(CLK), .CE(1'b1), .D(ktap_right_r_i_1_n_0), .Q(lim2poc_ktap_right), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE lim_start_r_reg (.C(CLK), .CE(1'b1), .D(lim_start), .Q(lim_start_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT4 #( .INIT(16'hFFD0)) \lim_state[0]_i_1 (.I0(\lim_state[0]_i_2_n_0 ), .I1(\lim_state[0]_i_3_n_0 ), .I2(wait_cnt_en_r_i_2_n_0), .I3(\lim_state[0]_i_4_n_0 ), .O(\lim_state[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair378" *) LUT4 #( .INIT(16'h0001)) \lim_state[0]_i_2 (.I0(lim_state[1]), .I1(lim_state[4]), .I2(lim_state[2]), .I3(lim_state[3]), .O(\lim_state[0]_i_2_n_0 )); LUT6 #( .INIT(64'hAAA8A880AAAAAAAA)) \lim_state[0]_i_3 (.I0(\lim_state[0]_i_5_n_0 ), .I1(lim_state[8]), .I2(lim_state[7]), .I3(lim_state[6]), .I4(lim_state[5]), .I5(\lim_state[1]_i_2_n_0 ), .O(\lim_state[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFDFFFCFCC2)) \lim_state[0]_i_4 (.I0(\lim_state[4]_i_3_n_0 ), .I1(lim_state[3]), .I2(lim_state[2]), .I3(lim_state[4]), .I4(lim_state[1]), .I5(lim_state[0]), .O(\lim_state[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFEFEEC)) \lim_state[0]_i_5 (.I0(lim_state[9]), .I1(lim_state[13]), .I2(lim_state[12]), .I3(lim_state[10]), .I4(lim_state[11]), .I5(wait_cnt_en_r_i_3_n_0), .O(\lim_state[0]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000020200)) \lim_state[10]_i_1 (.I0(\lim_state[10]_i_2_n_0 ), .I1(lim_state[0]), .I2(lim_state[9]), .I3(lim_state[7]), .I4(lim_state[8]), .I5(\lim_state[10]_i_3_n_0 ), .O(\lim_state[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair369" *) LUT5 #( .INIT(32'h00010000)) \lim_state[10]_i_2 (.I0(lim_state[12]), .I1(lim_state[13]), .I2(lim_state[11]), .I3(lim_state[10]), .I4(\lim_state[0]_i_2_n_0 ), .O(\lim_state[10]_i_2_n_0 )); LUT2 #( .INIT(4'hE)) \lim_state[10]_i_3 (.I0(lim_state[6]), .I1(lim_state[5]), .O(\lim_state[10]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000E2000000)) \lim_state[11]_i_1 (.I0(\lim_state[11]_i_2_n_0 ), .I1(lim_state[1]), .I2(\lim_state[11]_i_3_n_0 ), .I3(\lim_state[11]_i_4_n_0 ), .I4(\lim_state[11]_i_5_n_0 ), .I5(lim_state[13]), .O(\lim_state[11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000FFFFA8A00000)) \lim_state[11]_i_2 (.I0(\lim_state[6]_i_4_n_0 ), .I1(stg3_inc2init_val_r), .I2(stg3_dec2init_val_r), .I3(\lim_state[11]_i_6_n_0 ), .I4(lim_state[9]), .I5(lim_state[10]), .O(\lim_state[11]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair383" *) LUT2 #( .INIT(4'h1)) \lim_state[11]_i_3 (.I0(lim_state[10]), .I1(lim_state[9]), .O(\lim_state[11]_i_3_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[11]_i_4 (.I0(lim_state[0]), .I1(lim_state[3]), .I2(lim_state[2]), .I3(lim_state[4]), .I4(wait_cnt_en_r_i_3_n_0), .O(\lim_state[11]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair380" *) LUT2 #( .INIT(4'h1)) \lim_state[11]_i_5 (.I0(lim_state[11]), .I1(lim_state[12]), .O(\lim_state[11]_i_5_n_0 )); LUT6 #( .INIT(64'h444F444F444F4444)) \lim_state[11]_i_6 (.I0(stg3_inc_val[5]), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(\mmcm_init_lead[5]_i_3_n_0 ), .I3(\lim_state[11]_i_7_n_0 ), .I4(\mmcm_init_lead[5]_i_6_n_0 ), .I5(\mmcm_init_lead[5]_i_4_n_0 ), .O(\lim_state[11]_i_6_n_0 )); LUT6 #( .INIT(64'h00B0BBBB000000B0)) \lim_state[11]_i_7 (.I0(stg3_inc_val[4]), .I1(\stg3_tap_cnt_reg_n_0_[4] ), .I2(stg3_inc_val[2]), .I3(\stg3_tap_cnt_reg_n_0_[2] ), .I4(\stg3_tap_cnt_reg_n_0_[3] ), .I5(stg3_inc_val[3]), .O(\lim_state[11]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair368" *) LUT5 #( .INIT(32'h00005D55)) \lim_state[12]_i_1 (.I0(\lim_state[12]_i_2_n_0 ), .I1(\lim_state[12]_i_3_n_0 ), .I2(stg3_dec2init_val_r), .I3(stg3_inc2init_val_r), .I4(\lim_state[12]_i_4_n_0 ), .O(\lim_state[12]_i_1_n_0 )); LUT6 #( .INIT(64'h555F5DDF5DDF5DDF)) \lim_state[12]_i_2 (.I0(stg3_dec2init_val_r), .I1(\lim_state[12]_i_5_n_0 ), .I2(stg2_tap_cnt_reg__0[5]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg2_tap_cnt_reg__0[4]), .I5(\byte_r_reg[0] ), .O(\lim_state[12]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \lim_state[12]_i_3 (.I0(\stg2_tap_cnt_reg[3]_0 [1]), .I1(\stg2_tap_cnt_reg[3]_0 [0]), .I2(\stg2_tap_cnt_reg[3]_0 [2]), .I3(stg2_tap_cnt_reg__0[3]), .I4(stg2_tap_cnt_reg__0[5]), .I5(stg2_tap_cnt_reg__0[4]), .O(\lim_state[12]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFDFFFF)) \lim_state[12]_i_4 (.I0(lim_state[11]), .I1(wait_cnt_en_r_i_3_n_0), .I2(lim_state[0]), .I3(lim_state[3]), .I4(\lim_state[13]_i_11_n_0 ), .I5(stg2_inc_r_i_2_n_0), .O(\lim_state[12]_i_4_n_0 )); LUT6 #( .INIT(64'h111111FF11F1F1FF)) \lim_state[12]_i_5 (.I0(stg2_tap_cnt_reg__0[4]), .I1(\byte_r_reg[0] ), .I2(\stg2_tap_cnt_reg[2]_0 ), .I3(\wl_po_fine_cnt_reg[3] ), .I4(stg2_tap_cnt_reg__0[3]), .I5(\lim_state[12]_i_7_n_0 ), .O(\lim_state[12]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair373" *) LUT2 #( .INIT(4'h2)) \lim_state[12]_i_7 (.I0(\stg2_tap_cnt_reg[3]_0 [2]), .I1(\wl_po_fine_cnt_reg[14] [1]), .O(\lim_state[12]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEEEEEA)) \lim_state[13]_i_1 (.I0(lim_state[13]), .I1(\lim_state[13]_i_3_n_0 ), .I2(lim_state[4]), .I3(\lim_state[13]_i_4_n_0 ), .I4(\lim_state[13]_i_5_n_0 ), .I5(\lim_state[13]_i_6_n_0 ), .O(lim_nxt_state)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF4)) \lim_state[13]_i_10 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[3]), .I3(lim_state[2]), .I4(lim_state[4]), .I5(lim_state[1]), .O(\lim_state[13]_i_10_n_0 )); LUT3 #( .INIT(8'h01)) \lim_state[13]_i_11 (.I0(lim_state[2]), .I1(lim_state[4]), .I2(lim_state[1]), .O(\lim_state[13]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair379" *) LUT3 #( .INIT(8'h01)) \lim_state[13]_i_12 (.I0(lim_state[9]), .I1(lim_state[10]), .I2(lim_state[12]), .O(\lim_state[13]_i_12_n_0 )); LUT6 #( .INIT(64'h00000000EEEEEEFE)) \lim_state[13]_i_13 (.I0(lim_state[10]), .I1(lim_state[8]), .I2(po_rdy), .I3(lim2stg3_dec), .I4(lim2stg3_inc), .I5(\lim_state[13]_i_14_n_0 ), .O(\lim_state[13]_i_13_n_0 )); LUT5 #( .INIT(32'h000000FB)) \lim_state[13]_i_14 (.I0(lim2stg2_dec), .I1(po_rdy), .I2(lim2stg2_inc), .I3(lim_state[8]), .I4(lim_state[9]), .O(\lim_state[13]_i_14_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \lim_state[13]_i_2 (.I0(\lim_state[13]_i_7_n_0 ), .I1(\lim_state[13]_i_8_n_0 ), .I2(lim_state[1]), .I3(lim_state[13]), .I4(lim_state[12]), .I5(stg3_dec2init_val_r), .O(\lim_state[13]_i_2_n_0 )); LUT6 #( .INIT(64'hAAA8A888AAAAAAAA)) \lim_state[13]_i_3 (.I0(\lim_state[13]_i_9_n_0 ), .I1(wait_cnt_done), .I2(lim_state[4]), .I3(lim_state[1]), .I4(lim_state[2]), .I5(\lim_state[4]_i_3_n_0 ), .O(\lim_state[13]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair382" *) LUT4 #( .INIT(16'hFFFE)) \lim_state[13]_i_4 (.I0(lim_state[10]), .I1(lim_state[11]), .I2(lim_state[8]), .I3(lim_state[9]), .O(\lim_state[13]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEEE)) \lim_state[13]_i_5 (.I0(\lim_state[10]_i_3_n_0 ), .I1(lim_state[7]), .I2(lim_state[12]), .I3(prech_done), .I4(lim_state[2]), .I5(lim_state[1]), .O(\lim_state[13]_i_5_n_0 )); LUT6 #( .INIT(64'hC8CFCCC0FFF0FFF0)) \lim_state[13]_i_6 (.I0(done_r_reg_1), .I1(\lim_state[13]_i_10_n_0 ), .I2(lim_state[0]), .I3(lim_state[3]), .I4(\lim_state[13]_i_11_n_0 ), .I5(\lim_state[13]_i_12_n_0 ), .O(\lim_state[13]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \lim_state[13]_i_7 (.I0(lim_state[8]), .I1(lim_state[7]), .I2(\lim_state[10]_i_3_n_0 ), .I3(lim_state[4]), .I4(lim_state[2]), .I5(lim_state[3]), .O(\lim_state[13]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair382" *) LUT4 #( .INIT(16'hFFFE)) \lim_state[13]_i_8 (.I0(lim_state[10]), .I1(lim_state[11]), .I2(lim_state[0]), .I3(lim_state[9]), .O(\lim_state[13]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \lim_state[13]_i_9 (.I0(\lim_state[13]_i_13_n_0 ), .I1(lim_state[12]), .I2(lim_state[11]), .I3(\lim_state[13]_i_11_n_0 ), .I4(lim_state[7]), .I5(\lim_state[10]_i_3_n_0 ), .O(\lim_state[13]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair384" *) LUT4 #( .INIT(16'h0040)) \lim_state[1]_i_1 (.I0(\lim_state[13]_i_7_n_0 ), .I1(\lim_state[1]_i_2_n_0 ), .I2(lim_state[0]), .I3(lim_state[1]), .O(\lim_state[1]_i_1_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[1]_i_2 (.I0(lim_state[11]), .I1(lim_state[10]), .I2(lim_state[12]), .I3(lim_state[9]), .I4(lim_state[13]), .O(\lim_state[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \lim_state[2]_i_1 (.I0(\lim_state[2]_i_2_n_0 ), .I1(\lim_state[2]_i_3_n_0 ), .I2(lim_state[6]), .I3(lim_state[5]), .I4(lim_state[7]), .I5(\lim_state[2]_i_4_n_0 ), .O(\lim_state[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00F000F000F1FFFF)) \lim_state[2]_i_2 (.I0(stg3_inc2init_val_r), .I1(stg3_init_dec_r), .I2(\lim_state[6]_i_3_n_0 ), .I3(lim_state[12]), .I4(lim_state[9]), .I5(stg3_dec2init_val_r), .O(\lim_state[2]_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \lim_state[2]_i_3 (.I0(lim_state[0]), .I1(lim_state[3]), .I2(lim_state[1]), .I3(lim_state[2]), .O(\lim_state[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFEFFFEFFFEFFFFFF)) \lim_state[2]_i_4 (.I0(lim_state[10]), .I1(lim_state[8]), .I2(lim_state[11]), .I3(\lim_state[4]_i_2_n_0 ), .I4(lim_state[12]), .I5(lim_state[9]), .O(\lim_state[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000010000000)) \lim_state[3]_i_1 (.I0(lim_state[0]), .I1(lim_state[1]), .I2(\lim_state[4]_i_2_n_0 ), .I3(\lim_state[4]_i_3_n_0 ), .I4(lim_state[2]), .I5(lim_state[3]), .O(\lim_state[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000010000000)) \lim_state[4]_i_1 (.I0(lim_state[0]), .I1(lim_state[1]), .I2(\lim_state[4]_i_2_n_0 ), .I3(\lim_state[4]_i_3_n_0 ), .I4(lim_state[3]), .I5(lim_state[2]), .O(\lim_state[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair372" *) LUT2 #( .INIT(4'h1)) \lim_state[4]_i_2 (.I0(lim_state[4]), .I1(lim_state[13]), .O(\lim_state[4]_i_2_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[4]_i_3 (.I0(lim_state[11]), .I1(lim_state[10]), .I2(lim_state[12]), .I3(lim_state[9]), .I4(wait_cnt_en_r_i_3_n_0), .O(\lim_state[4]_i_3_n_0 )); LUT4 #( .INIT(16'h888A)) \lim_state[5]_i_1 (.I0(\lim_state[6]_i_2_n_0 ), .I1(\lim_state[5]_i_2_n_0 ), .I2(lim_state[9]), .I3(\lim_state[6]_i_5_n_0 ), .O(\lim_state[5]_i_1_n_0 )); LUT5 #( .INIT(32'h00000010)) \lim_state[5]_i_2 (.I0(lim_state[4]), .I1(stg3_init_dec_r), .I2(stg3_inc2init_val_r), .I3(stg3_dec2init_val_r), .I4(\lim_state[11]_i_6_n_0 ), .O(\lim_state[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0002AAAA00020002)) \lim_state[6]_i_1 (.I0(\lim_state[6]_i_2_n_0 ), .I1(\lim_state[6]_i_3_n_0 ), .I2(lim_state[4]), .I3(\lim_state[6]_i_4_n_0 ), .I4(lim_state[9]), .I5(\lim_state[6]_i_5_n_0 ), .O(\lim_state[6]_i_1_n_0 )); LUT6 #( .INIT(64'h1D1D1D1D1D1D1DFF)) \lim_state[6]_i_10 (.I0(\lim_state[6]_i_14_n_0 ), .I1(\lim_state[6]_i_15_n_0 ), .I2(\lim_state[6]_i_16_n_0 ), .I3(\stg3_tap_cnt_reg_n_0_[4] ), .I4(\stg3_tap_cnt_reg_n_0_[5] ), .I5(\lim_state[6]_i_17_n_0 ), .O(\lim_state[6]_i_10_n_0 )); LUT6 #( .INIT(64'hD0FD0000FFFFD0FD)) \lim_state[6]_i_11 (.I0(\stg3_tap_cnt_reg_n_0_[0] ), .I1(stg3_dec_val[0]), .I2(stg3_dec_val[1]), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(stg3_dec_val[2]), .I5(\stg3_tap_cnt_reg_n_0_[2] ), .O(\lim_state[6]_i_11_n_0 )); LUT6 #( .INIT(64'h0D000D00DD0D0D00)) \lim_state[6]_i_12 (.I0(\stg3_tap_cnt_reg[2]_0 [2]), .I1(\stg3_tap_cnt_reg_n_0_[2] ), .I2(\stg3_tap_cnt_reg[2]_0 [1]), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt_reg_n_0_[0] ), .I5(\stg3_tap_cnt_reg[2]_0 [0]), .O(\lim_state[6]_i_12_n_0 )); LUT4 #( .INIT(16'h4F44)) \lim_state[6]_i_13 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_init_val[4]), .I2(\stg3_tap_cnt_reg_n_0_[3] ), .I3(stg3_init_val[3]), .O(\lim_state[6]_i_13_n_0 )); LUT4 #( .INIT(16'h0002)) \lim_state[6]_i_14 (.I0(\lim_state[6]_i_18_n_0 ), .I1(mod_sub_return0_carry__0_n_6), .I2(mod_sub_return0_carry__0_n_5), .I3(mod_sub_return0_carry__0_n_7), .O(\lim_state[6]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair376" *) LUT5 #( .INIT(32'h4D44DDDD)) \lim_state[6]_i_15 (.I0(\mmcm_current_reg_n_0_[5] ), .I1(\mmcm_init_trail_reg_n_0_[5] ), .I2(\mmcm_current_reg_n_0_[4] ), .I3(\mmcm_init_trail_reg_n_0_[4] ), .I4(\lim_state[6]_i_19_n_0 ), .O(\lim_state[6]_i_15_n_0 )); LUT4 #( .INIT(16'h0020)) \lim_state[6]_i_16 (.I0(\lim_state[6]_i_20_n_0 ), .I1(mod_sub_return0__14_carry__0_n_7), .I2(mod_sub_return0__14_carry__0_n_1), .I3(mod_sub_return0__14_carry__0_n_6), .O(\lim_state[6]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair377" *) LUT4 #( .INIT(16'hFFFE)) \lim_state[6]_i_17 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .O(\lim_state[6]_i_17_n_0 )); LUT4 #( .INIT(16'h5557)) \lim_state[6]_i_18 (.I0(mod_sub_return0_carry_n_4), .I1(mod_sub_return0_carry_n_6), .I2(mod_sub_return0_carry_n_5), .I3(mod_sub_return0_carry_n_7), .O(\lim_state[6]_i_18_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFB000FFB0)) \lim_state[6]_i_19 (.I0(\mmcm_current_reg_n_0_[2] ), .I1(\mmcm_init_trail_reg_n_0_[2] ), .I2(\lim_state[6]_i_21_n_0 ), .I3(\mmcm_current_reg_n_0_[3] ), .I4(\mmcm_init_trail_reg_n_0_[3] ), .I5(\lim_state[6]_i_22_n_0 ), .O(\lim_state[6]_i_19_n_0 )); LUT5 #( .INIT(32'h11100000)) \lim_state[6]_i_2 (.I0(wait_cnt_en_r_i_3_n_0), .I1(\lim_state[2]_i_3_n_0 ), .I2(lim_state[4]), .I3(lim_state[9]), .I4(\lim_state[6]_i_6_n_0 ), .O(\lim_state[6]_i_2_n_0 )); LUT4 #( .INIT(16'h5557)) \lim_state[6]_i_20 (.I0(mod_sub_return0__14_carry_n_4), .I1(mod_sub_return0__14_carry_n_6), .I2(mod_sub_return0__14_carry_n_5), .I3(\mmcm_init_trail_reg[0]_0 ), .O(\lim_state[6]_i_20_n_0 )); LUT6 #( .INIT(64'h40F440F4FFFF40F4)) \lim_state[6]_i_21 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .I2(\mmcm_current_reg_n_0_[1] ), .I3(\mmcm_init_trail_reg_n_0_[1] ), .I4(\mmcm_current_reg_n_0_[2] ), .I5(\mmcm_init_trail_reg_n_0_[2] ), .O(\lim_state[6]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair376" *) LUT2 #( .INIT(4'h2)) \lim_state[6]_i_22 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_trail_reg_n_0_[4] ), .O(\lim_state[6]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair393" *) LUT2 #( .INIT(4'h9)) \lim_state[6]_i_24 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .O(stg3_inc2init_val_r_reg_0)); LUT4 #( .INIT(16'h8A08)) \lim_state[6]_i_3 (.I0(stg3_init_dec_r), .I1(stg3_dec_val[5]), .I2(\stg3_tap_cnt_reg_n_0_[5] ), .I3(\lim_state[6]_i_7_n_0 ), .O(\lim_state[6]_i_3_n_0 )); LUT6 #( .INIT(64'h1055105510555555)) \lim_state[6]_i_4 (.I0(stg3_init_dec_r), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(stg3_init_val[5]), .I3(stg3_dec2init_val_r), .I4(\lim_state[6]_i_8_n_0 ), .I5(\lim_state[6]_i_9_n_0 ), .O(\lim_state[6]_i_4_n_0 )); LUT3 #( .INIT(8'hAE)) \lim_state[6]_i_5 (.I0(stg3_dec2init_val_r_i_2_n_0), .I1(stg3_dec_r), .I2(\lim_state[6]_i_10_n_0 ), .O(\lim_state[6]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair369" *) LUT4 #( .INIT(16'h0001)) \lim_state[6]_i_6 (.I0(lim_state[10]), .I1(lim_state[11]), .I2(lim_state[13]), .I3(lim_state[12]), .O(\lim_state[6]_i_6_n_0 )); LUT5 #( .INIT(32'hD4DD44D4)) \lim_state[6]_i_7 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_dec_val[4]), .I2(\lim_state[6]_i_11_n_0 ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .I4(stg3_dec_val[3]), .O(\lim_state[6]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFFF4F44)) \lim_state[6]_i_8 (.I0(stg3_init_val[3]), .I1(\stg3_tap_cnt_reg_n_0_[3] ), .I2(\stg3_tap_cnt_reg[2]_0 [2]), .I3(\stg3_tap_cnt_reg_n_0_[2] ), .I4(\lim_state[6]_i_12_n_0 ), .I5(\lim_state[6]_i_13_n_0 ), .O(\lim_state[6]_i_8_n_0 )); LUT4 #( .INIT(16'h4F44)) \lim_state[6]_i_9 (.I0(stg3_init_val[4]), .I1(\stg3_tap_cnt_reg_n_0_[4] ), .I2(stg3_init_val[5]), .I3(\stg3_tap_cnt_reg_n_0_[5] ), .O(\lim_state[6]_i_9_n_0 )); LUT5 #( .INIT(32'h0000888A)) \lim_state[7]_i_1 (.I0(\lim_state[12]_i_2_n_0 ), .I1(stg3_dec2init_val_r), .I2(\lim_state[7]_i_2_n_0 ), .I3(stg3_inc2init_val_r), .I4(\lim_state[12]_i_4_n_0 ), .O(\lim_state[7]_i_1_n_0 )); LUT6 #( .INIT(64'h55555555D5555555)) \lim_state[7]_i_2 (.I0(stg2_inc_r), .I1(stg2_tap_cnt_reg__0[5]), .I2(stg2_tap_cnt_reg__0[4]), .I3(\stg2_tap_cnt_reg[3]_0 [1]), .I4(\stg2_tap_cnt_reg[3]_0 [0]), .I5(\lim_state[7]_i_3_n_0 ), .O(\lim_state[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair367" *) LUT2 #( .INIT(4'h7)) \lim_state[7]_i_3 (.I0(\stg2_tap_cnt_reg[3]_0 [2]), .I1(stg2_tap_cnt_reg__0[3]), .O(\lim_state[7]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair368" *) LUT4 #( .INIT(16'h0004)) \lim_state[8]_i_1 (.I0(\lim_state[12]_i_4_n_0 ), .I1(stg3_inc2init_val_r), .I2(stg3_dec2init_val_r), .I3(\lim_state[12]_i_3_n_0 ), .O(\lim_state[8]_i_1_n_0 )); LUT5 #( .INIT(32'h17001400)) \lim_state[9]_i_1 (.I0(lim_state[11]), .I1(lim_state[5]), .I2(lim_state[6]), .I3(\lim_state[9]_i_2_n_0 ), .I4(\lim_state[9]_i_3_n_0 ), .O(\lim_state[9]_i_1_n_0 )); LUT5 #( .INIT(32'h00000001)) \lim_state[9]_i_2 (.I0(stg2_inc_r_i_2_n_0), .I1(lim_state[4]), .I2(lim_state[8]), .I3(lim_state[7]), .I4(\lim_state[2]_i_3_n_0 ), .O(\lim_state[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair386" *) LUT4 #( .INIT(16'h0200)) \lim_state[9]_i_3 (.I0(\lim_state[7]_i_2_n_0 ), .I1(stg3_dec2init_val_r), .I2(stg3_inc2init_val_r), .I3(lim_state[11]), .O(\lim_state[9]_i_3_n_0 )); FDSE \lim_state_reg[0] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[0]_i_1_n_0 ), .Q(lim_state[0]), .S(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[10] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[10]_i_1_n_0 ), .Q(lim_state[10]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[11] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[11]_i_1_n_0 ), .Q(lim_state[11]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[12] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[12]_i_1_n_0 ), .Q(lim_state[12]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[13] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[13]_i_2_n_0 ), .Q(lim_state[13]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[1] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[1]_i_1_n_0 ), .Q(lim_state[1]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[2] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[2]_i_1_n_0 ), .Q(lim_state[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[3] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[3]_i_1_n_0 ), .Q(lim_state[3]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[4] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[4]_i_1_n_0 ), .Q(lim_state[4]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[5] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[5]_i_1_n_0 ), .Q(lim_state[5]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[6] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[6]_i_1_n_0 ), .Q(lim_state[6]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[7] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[7]_i_1_n_0 ), .Q(lim_state[7]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[8] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[8]_i_1_n_0 ), .Q(lim_state[8]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \lim_state_reg[9] (.C(CLK), .CE(lim_nxt_state), .D(\lim_state[9]_i_1_n_0 ), .Q(lim_state[9]), .R(rstdiv0_sync_r1_reg_rep__10)); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[0]_i_1 (.I0(\mmcm_current[0]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[0] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[0]), .O(\mmcm_current[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair387" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[0]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [0]), .O(\mmcm_current[0]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[1]_i_1 (.I0(\mmcm_current[1]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[1] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[1]), .O(\mmcm_current[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair388" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[1]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[1] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [1]), .O(\mmcm_current[1]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[2]_i_1 (.I0(\mmcm_current[2]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[2] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[2]), .O(\mmcm_current[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair389" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[2]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[2] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [2]), .O(\mmcm_current[2]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[3]_i_1 (.I0(\mmcm_current[3]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[3] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[3]), .O(\mmcm_current[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair387" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[3]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[3] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [3]), .O(\mmcm_current[3]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[4]_i_1 (.I0(\mmcm_current[4]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[4] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[4]), .O(\mmcm_current[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair388" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[4]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [4]), .O(\mmcm_current[4]_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \mmcm_current[5]_i_1 (.I0(\mmcm_current[5]_i_2_n_0 ), .I1(stg3_dec_r), .I2(\mmcm_init_lead_reg_n_0_[5] ), .I3(\mmcm_init_lead[5]_i_2_n_0 ), .I4(Q[5]), .O(\mmcm_current[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair389" *) LUT3 #( .INIT(8'hB8)) \mmcm_current[5]_i_2 (.I0(\mmcm_init_trail_reg_n_0_[5] ), .I1(\mmcm_init_trail[5]_i_2_n_0 ), .I2(\rise_lead_r_reg[5] [5]), .O(\mmcm_current[5]_i_2_n_0 )); FDRE \mmcm_current_reg[0] (.C(CLK), .CE(1'b1), .D(\mmcm_current[0]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_current_reg[1] (.C(CLK), .CE(1'b1), .D(\mmcm_current[1]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_current_reg[2] (.C(CLK), .CE(1'b1), .D(\mmcm_current[2]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_current_reg[3] (.C(CLK), .CE(1'b1), .D(\mmcm_current[3]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_current_reg[4] (.C(CLK), .CE(1'b1), .D(\mmcm_current[4]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_current_reg[5] (.C(CLK), .CE(1'b1), .D(\mmcm_current[5]_i_1_n_0 ), .Q(\mmcm_current_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); LUT3 #( .INIT(8'h20)) \mmcm_init_lead[5]_i_1 (.I0(\mmcm_init_lead[5]_i_2_n_0 ), .I1(detect_done_r), .I2(done_r_reg_1), .O(mmcm_init_lead)); LUT4 #( .INIT(16'h0004)) \mmcm_init_lead[5]_i_2 (.I0(\mmcm_init_lead[5]_i_3_n_0 ), .I1(\mmcm_init_lead[5]_i_4_n_0 ), .I2(\mmcm_init_lead[5]_i_5_n_0 ), .I3(\mmcm_init_lead[5]_i_6_n_0 ), .O(\mmcm_init_lead[5]_i_2_n_0 )); LUT4 #( .INIT(16'h4F44)) \mmcm_init_lead[5]_i_3 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_inc_val[4]), .I2(\stg3_tap_cnt_reg_n_0_[5] ), .I3(stg3_inc_val[5]), .O(\mmcm_init_lead[5]_i_3_n_0 )); LUT4 #( .INIT(16'hD0DD)) \mmcm_init_lead[5]_i_4 (.I0(stg3_inc_val[1]), .I1(\stg3_tap_cnt_reg_n_0_[1] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(stg3_inc_val[0]), .O(\mmcm_init_lead[5]_i_4_n_0 )); LUT5 #( .INIT(32'h5D5DFF5D)) \mmcm_init_lead[5]_i_5 (.I0(\mmcm_init_lead[5]_i_7_n_0 ), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(stg3_inc_val[5]), .I3(\stg3_tap_cnt_reg_n_0_[0] ), .I4(stg3_inc_val[0]), .O(\mmcm_init_lead[5]_i_5_n_0 )); LUT5 #( .INIT(32'h22F2FFFF)) \mmcm_init_lead[5]_i_6 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(stg3_inc_val[1]), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(stg3_inc_val[2]), .I4(\mmcm_init_lead[5]_i_8_n_0 ), .O(\mmcm_init_lead[5]_i_6_n_0 )); LUT4 #( .INIT(16'hD0DD)) \mmcm_init_lead[5]_i_7 (.I0(stg3_inc_val[3]), .I1(\stg3_tap_cnt_reg_n_0_[3] ), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(stg3_inc_val[2]), .O(\mmcm_init_lead[5]_i_7_n_0 )); LUT4 #( .INIT(16'hD0DD)) \mmcm_init_lead[5]_i_8 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_inc_val[4]), .I2(stg3_inc_val[3]), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .O(\mmcm_init_lead[5]_i_8_n_0 )); FDRE \mmcm_init_lead_reg[0] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [0]), .Q(\mmcm_init_lead_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_lead_reg[1] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [1]), .Q(\mmcm_init_lead_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_lead_reg[2] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [2]), .Q(\mmcm_init_lead_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_lead_reg[3] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [3]), .Q(\mmcm_init_lead_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_lead_reg[4] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [4]), .Q(\mmcm_init_lead_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_lead_reg[5] (.C(CLK), .CE(mmcm_init_lead), .D(\rise_lead_r_reg[5] [5]), .Q(\mmcm_init_lead_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); LUT3 #( .INIT(8'h40)) \mmcm_init_trail[5]_i_1 (.I0(detect_done_r), .I1(done_r_reg_1), .I2(\mmcm_init_trail[5]_i_2_n_0 ), .O(mmcm_init_trail)); LUT6 #( .INIT(64'h0000000009000009)) \mmcm_init_trail[5]_i_2 (.I0(stg3_dec_val[5]), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(\mmcm_init_trail[5]_i_3_n_0 ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .I4(stg3_dec_val[3]), .I5(\mmcm_init_trail[5]_i_4_n_0 ), .O(\mmcm_init_trail[5]_i_2_n_0 )); LUT2 #( .INIT(4'h6)) \mmcm_init_trail[5]_i_3 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(stg3_dec_val[4]), .O(\mmcm_init_trail[5]_i_3_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \mmcm_init_trail[5]_i_4 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(stg3_dec_val[1]), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(stg3_dec_val[2]), .I4(stg3_dec_val[0]), .I5(\stg3_tap_cnt_reg_n_0_[0] ), .O(\mmcm_init_trail[5]_i_4_n_0 )); FDRE \mmcm_init_trail_reg[0] (.C(CLK), .CE(mmcm_init_trail), .D(Q[0]), .Q(\mmcm_init_trail_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_trail_reg[1] (.C(CLK), .CE(mmcm_init_trail), .D(Q[1]), .Q(\mmcm_init_trail_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_trail_reg[2] (.C(CLK), .CE(mmcm_init_trail), .D(Q[2]), .Q(\mmcm_init_trail_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_trail_reg[3] (.C(CLK), .CE(mmcm_init_trail), .D(Q[3]), .Q(\mmcm_init_trail_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_trail_reg[4] (.C(CLK), .CE(mmcm_init_trail), .D(Q[4]), .Q(\mmcm_init_trail_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__11)); FDRE \mmcm_init_trail_reg[5] (.C(CLK), .CE(mmcm_init_trail), .D(Q[5]), .Q(\mmcm_init_trail_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__11)); CARRY4 mod_sub0_return0__14_carry (.CI(1'b0), .CO({mod_sub0_return0__14_carry_n_0,mod_sub0_return0__14_carry_n_1,mod_sub0_return0__14_carry_n_2,mod_sub0_return0__14_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_current_reg_n_0_[3] ,\mmcm_current_reg_n_0_[2] ,\mmcm_current_reg_n_0_[1] ,\mmcm_current_reg_n_0_[0] }), .O({mod_sub0_return0__14_carry_n_4,mod_sub0_return0__14_carry_n_5,mod_sub0_return0__14_carry_n_6,NLW_mod_sub0_return0__14_carry_O_UNCONNECTED[0]}), .S({mod_sub0_return0__14_carry_i_1_n_0,mod_sub0_return0__14_carry_i_2_n_0,mod_sub0_return0__14_carry_i_3_n_0,mod_sub0_return0__14_carry_i_4_n_0})); CARRY4 mod_sub0_return0__14_carry__0 (.CI(mod_sub0_return0__14_carry_n_0), .CO({NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub0_return0__14_carry__0_n_1,NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub0_return0__14_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\mmcm_current_reg_n_0_[5] ,\mmcm_current_reg_n_0_[4] }), .O({NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub0_return0__14_carry__0_n_6,mod_sub0_return0__14_carry__0_n_7}), .S({1'b0,1'b1,mod_sub0_return0__14_carry__0_i_1_n_0,mod_sub0_return0__14_carry__0_i_2_n_0})); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry__0_i_1 (.I0(\mmcm_current_reg_n_0_[5] ), .I1(\mmcm_init_lead_reg_n_0_[5] ), .O(mod_sub0_return0__14_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry__0_i_2 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_lead_reg_n_0_[4] ), .O(mod_sub0_return0__14_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_1 (.I0(\mmcm_current_reg_n_0_[3] ), .I1(\mmcm_init_lead_reg_n_0_[3] ), .O(mod_sub0_return0__14_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_2 (.I0(\mmcm_current_reg_n_0_[2] ), .I1(\mmcm_init_lead_reg_n_0_[2] ), .O(mod_sub0_return0__14_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_3 (.I0(\mmcm_current_reg_n_0_[1] ), .I1(\mmcm_init_lead_reg_n_0_[1] ), .O(mod_sub0_return0__14_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0__14_carry_i_4 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .O(mod_sub0_return0__14_carry_i_4_n_0)); CARRY4 mod_sub0_return0_carry (.CI(1'b0), .CO({mod_sub0_return0_carry_n_0,mod_sub0_return0_carry_n_1,mod_sub0_return0_carry_n_2,mod_sub0_return0_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_init_lead_reg_n_0_[3] ,\mmcm_current_reg_n_0_[2] ,\mmcm_current_reg_n_0_[1] ,\mmcm_current_reg_n_0_[0] }), .O({mod_sub0_return0_carry_n_4,mod_sub0_return0_carry_n_5,mod_sub0_return0_carry_n_6,mod_sub0_return0_carry_n_7}), .S({mod_sub0_return0_carry_i_1_n_0,mod_sub0_return0_carry_i_2_n_0,mod_sub0_return0_carry_i_3_n_0,mod_sub0_return0_carry_i_4_n_0})); CARRY4 mod_sub0_return0_carry__0 (.CI(mod_sub0_return0_carry_n_0), .CO({NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub0_return0_carry__0_n_2,mod_sub0_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,mod_sub0_return0_carry__0_i_1_n_0,mod_sub0_return0_carry__0_i_2_n_0}), .O({NLW_mod_sub0_return0_carry__0_O_UNCONNECTED[3],mod_sub0_return0_carry__0_n_5,mod_sub0_return0_carry__0_n_6,mod_sub0_return0_carry__0_n_7}), .S({1'b0,mod_sub0_return0_carry__0_i_3_n_0,mod_sub0_return0_carry__0_i_4_n_0,mod_sub0_return0_carry__0_i_5_n_0})); LUT2 #( .INIT(4'hB)) mod_sub0_return0_carry__0_i_1 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_lead_reg_n_0_[4] ), .O(mod_sub0_return0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h6)) mod_sub0_return0_carry__0_i_2 (.I0(\mmcm_init_lead_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(mod_sub0_return0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h2)) mod_sub0_return0_carry__0_i_3 (.I0(\mmcm_init_lead_reg_n_0_[5] ), .I1(\mmcm_current_reg_n_0_[5] ), .O(mod_sub0_return0_carry__0_i_3_n_0)); LUT4 #( .INIT(16'hB44B)) mod_sub0_return0_carry__0_i_4 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_lead_reg_n_0_[4] ), .I2(\mmcm_init_lead_reg_n_0_[5] ), .I3(\mmcm_current_reg_n_0_[5] ), .O(mod_sub0_return0_carry__0_i_4_n_0)); LUT3 #( .INIT(8'h69)) mod_sub0_return0_carry__0_i_5 (.I0(\mmcm_init_lead_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .I2(\mmcm_init_lead_reg_n_0_[3] ), .O(mod_sub0_return0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h6)) mod_sub0_return0_carry_i_1 (.I0(\mmcm_init_lead_reg_n_0_[3] ), .I1(\mmcm_current_reg_n_0_[3] ), .O(mod_sub0_return0_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0_carry_i_2 (.I0(\mmcm_current_reg_n_0_[2] ), .I1(\mmcm_init_lead_reg_n_0_[2] ), .O(mod_sub0_return0_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0_carry_i_3 (.I0(\mmcm_current_reg_n_0_[1] ), .I1(\mmcm_init_lead_reg_n_0_[1] ), .O(mod_sub0_return0_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub0_return0_carry_i_4 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .O(mod_sub0_return0_carry_i_4_n_0)); CARRY4 mod_sub_return0__14_carry (.CI(1'b0), .CO({mod_sub_return0__14_carry_n_0,mod_sub_return0__14_carry_n_1,mod_sub_return0__14_carry_n_2,mod_sub_return0__14_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_init_trail_reg_n_0_[3] ,\mmcm_init_trail_reg_n_0_[2] ,\mmcm_init_trail_reg_n_0_[1] ,\mmcm_init_trail_reg_n_0_[0] }), .O({mod_sub_return0__14_carry_n_4,mod_sub_return0__14_carry_n_5,mod_sub_return0__14_carry_n_6,NLW_mod_sub_return0__14_carry_O_UNCONNECTED[0]}), .S({mod_sub_return0__14_carry_i_1_n_0,mod_sub_return0__14_carry_i_2_n_0,mod_sub_return0__14_carry_i_3_n_0,mod_sub_return0__14_carry_i_4_n_0})); CARRY4 mod_sub_return0__14_carry__0 (.CI(mod_sub_return0__14_carry_n_0), .CO({NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub_return0__14_carry__0_n_1,NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub_return0__14_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\mmcm_init_trail_reg_n_0_[5] ,\mmcm_init_trail_reg_n_0_[4] }), .O({NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__14_carry__0_n_6,mod_sub_return0__14_carry__0_n_7}), .S({1'b0,1'b1,mod_sub_return0__14_carry__0_i_1_n_0,mod_sub_return0__14_carry__0_i_2_n_0})); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry__0_i_1 (.I0(\mmcm_init_trail_reg_n_0_[5] ), .I1(\mmcm_current_reg_n_0_[5] ), .O(mod_sub_return0__14_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry__0_i_2 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(mod_sub_return0__14_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_1 (.I0(\mmcm_init_trail_reg_n_0_[3] ), .I1(\mmcm_current_reg_n_0_[3] ), .O(mod_sub_return0__14_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_2 (.I0(\mmcm_init_trail_reg_n_0_[2] ), .I1(\mmcm_current_reg_n_0_[2] ), .O(mod_sub_return0__14_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_3 (.I0(\mmcm_init_trail_reg_n_0_[1] ), .I1(\mmcm_current_reg_n_0_[1] ), .O(mod_sub_return0__14_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0__14_carry_i_4 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .O(mod_sub_return0__14_carry_i_4_n_0)); CARRY4 mod_sub_return0_carry (.CI(1'b0), .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}), .CYINIT(1'b1), .DI({\mmcm_current_reg_n_0_[3] ,\mmcm_init_trail_reg_n_0_[2] ,\mmcm_init_trail_reg_n_0_[1] ,\mmcm_init_trail_reg_n_0_[0] }), .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}), .S({mod_sub_return0_carry_i_1__0_n_0,mod_sub_return0_carry_i_2_n_0,mod_sub_return0_carry_i_3_n_0,mod_sub_return0_carry_i_4_n_0})); CARRY4 mod_sub_return0_carry__0 (.CI(mod_sub_return0_carry_n_0), .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_2,mod_sub_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,mod_sub_return0_carry__0_i_1__0_n_0,mod_sub_return0_carry__0_i_2_n_0}), .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3],mod_sub_return0_carry__0_n_5,mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}), .S({1'b0,mod_sub_return0_carry__0_i_3_n_0,mod_sub_return0_carry__0_i_4_n_0,mod_sub_return0_carry__0_i_5_n_0})); LUT2 #( .INIT(4'hB)) mod_sub_return0_carry__0_i_1__0 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(mod_sub_return0_carry__0_i_1__0_n_0)); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry__0_i_2 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_trail_reg_n_0_[4] ), .O(mod_sub_return0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h2)) mod_sub_return0_carry__0_i_3 (.I0(\mmcm_current_reg_n_0_[5] ), .I1(\mmcm_init_trail_reg_n_0_[5] ), .O(mod_sub_return0_carry__0_i_3_n_0)); LUT4 #( .INIT(16'hB44B)) mod_sub_return0_carry__0_i_4 (.I0(\mmcm_init_trail_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .I2(\mmcm_current_reg_n_0_[5] ), .I3(\mmcm_init_trail_reg_n_0_[5] ), .O(mod_sub_return0_carry__0_i_4_n_0)); LUT3 #( .INIT(8'h69)) mod_sub_return0_carry__0_i_5 (.I0(\mmcm_current_reg_n_0_[4] ), .I1(\mmcm_init_trail_reg_n_0_[4] ), .I2(\mmcm_current_reg_n_0_[3] ), .O(mod_sub_return0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry_i_1__0 (.I0(\mmcm_current_reg_n_0_[3] ), .I1(\mmcm_init_trail_reg_n_0_[3] ), .O(mod_sub_return0_carry_i_1__0_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0_carry_i_2 (.I0(\mmcm_init_trail_reg_n_0_[2] ), .I1(\mmcm_current_reg_n_0_[2] ), .O(mod_sub_return0_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0_carry_i_3 (.I0(\mmcm_init_trail_reg_n_0_[1] ), .I1(\mmcm_current_reg_n_0_[1] ), .O(mod_sub_return0_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) mod_sub_return0_carry_i_4 (.I0(\mmcm_init_trail_reg_n_0_[0] ), .I1(\mmcm_current_reg_n_0_[0] ), .O(mod_sub_return0_carry_i_4_n_0)); LUT4 #( .INIT(16'h8A88)) oclkdelay_center_calib_start_r_i_2 (.I0(scanning_right), .I1(o2f_r_reg), .I2(oclkdelay_center_calib_start_r_i_3_n_0), .I3(oclkdelay_center_calib_start_r_i_4_n_0), .O(oclkdelay_center_calib_start_r_reg)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) oclkdelay_center_calib_start_r_i_3 (.I0(oclkdelay_center_calib_start_r_reg_0[2]), .I1(\stg3_r_reg[5] [2]), .I2(oclkdelay_center_calib_start_r_reg_0[1]), .I3(\stg3_r_reg[5] [1]), .I4(\stg3_r_reg[5] [0]), .I5(oclkdelay_center_calib_start_r_reg_0[0]), .O(oclkdelay_center_calib_start_r_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) oclkdelay_center_calib_start_r_i_4 (.I0(oclkdelay_center_calib_start_r_reg_0[5]), .I1(\stg3_r_reg[5] [5]), .I2(oclkdelay_center_calib_start_r_reg_0[4]), .I3(\stg3_r_reg[5] [4]), .I4(oclkdelay_center_calib_start_r_reg_0[3]), .I5(\stg3_r_reg[5] [3]), .O(oclkdelay_center_calib_start_r_i_4_n_0)); LUT5 #( .INIT(32'h55555554)) po_stg23_sel_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(\po_wait_r_reg[0] ), .I2(\sm_r_reg[2] ), .I3(lim2stg3_dec), .I4(lim2stg3_inc), .O(po_stg23_sel_r_reg)); LUT6 #( .INIT(64'hBFFFBFFF20200000)) poc_ready_r_i_1 (.I0(lim_state[2]), .I1(lim_state[3]), .I2(write_request_r_i_2_n_0), .I3(done_r_reg_1), .I4(wait_cnt_done), .I5(lim2poc_rdy), .O(poc_ready_r_i_1_n_0)); FDRE poc_ready_r_reg (.C(CLK), .CE(1'b1), .D(poc_ready_r_i_1_n_0), .Q(lim2poc_rdy), .R(rstdiv0_sync_r1_reg_rep__10)); LUT5 #( .INIT(32'hFFF70004)) prech_req_r_i_1__0 (.I0(prech_done), .I1(prech_req_r_i_2_n_0), .I2(\lim_state[13]_i_4_n_0 ), .I3(\lim_state[2]_i_3_n_0 ), .I4(prech_req_r_reg_0), .O(prech_req_r_i_1__0_n_0)); LUT6 #( .INIT(64'h0000000000010000)) prech_req_r_i_2 (.I0(lim_state[6]), .I1(lim_state[5]), .I2(lim_state[7]), .I3(lim_state[4]), .I4(lim_state[12]), .I5(lim_state[13]), .O(prech_req_r_i_2_n_0)); FDRE prech_req_r_reg (.C(CLK), .CE(1'b1), .D(prech_req_r_i_1__0_n_0), .Q(prech_req_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__10)); LUT4 #( .INIT(16'h000E)) scanning_right_r_i_2 (.I0(scanning_right_r_i_4_n_0), .I1(scanning_right_r_i_5_n_0), .I2(scan_right), .I3(scanning_right), .O(scanning_right_r_reg)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) scanning_right_r_i_4 (.I0(scanning_right_r_reg_0[0]), .I1(\stg3_r_reg[5] [0]), .I2(\stg3_r_reg[5] [1]), .I3(scanning_right_r_reg_0[1]), .I4(\stg3_r_reg[5] [2]), .I5(scanning_right_r_reg_0[2]), .O(scanning_right_r_i_4_n_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) scanning_right_r_i_5 (.I0(scanning_right_r_reg_0[3]), .I1(\stg3_r_reg[5] [3]), .I2(\stg3_r_reg[5] [4]), .I3(scanning_right_r_reg_0[4]), .I4(\stg3_r_reg[5] [5]), .I5(scanning_right_r_reg_0[5]), .O(scanning_right_r_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFFDF00000008)) stg2_dec_req_r_i_1 (.I0(stg2_inc_req_r_i_2_n_0), .I1(lim_state[8]), .I2(lim_state[10]), .I3(lim_state[0]), .I4(lim_state[7]), .I5(lim2stg2_dec), .O(stg2_dec_req_r_i_1_n_0)); FDRE stg2_dec_req_r_reg (.C(CLK), .CE(1'b1), .D(stg2_dec_req_r_i_1_n_0), .Q(lim2stg2_dec), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFFFD00003020)) stg2_inc_r_i_1 (.I0(\lim_state[9]_i_3_n_0 ), .I1(stg2_inc_r_i_2_n_0), .I2(stg2_inc_r_i_3_n_0), .I3(lim_state[0]), .I4(stg2_inc_r_i_4_n_0), .I5(stg2_inc_r), .O(stg2_inc_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair379" *) LUT4 #( .INIT(16'hFFFE)) stg2_inc_r_i_2 (.I0(lim_state[13]), .I1(lim_state[12]), .I2(lim_state[9]), .I3(lim_state[10]), .O(stg2_inc_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair392" *) LUT3 #( .INIT(8'h04)) stg2_inc_r_i_3 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[11]), .O(stg2_inc_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair378" *) LUT5 #( .INIT(32'hFFFFFFFE)) stg2_inc_r_i_4 (.I0(lim_state[1]), .I1(lim_state[3]), .I2(lim_state[2]), .I3(lim_state[4]), .I4(wait_cnt_en_r_i_3_n_0), .O(stg2_inc_r_i_4_n_0)); FDRE stg2_inc_r_reg (.C(CLK), .CE(1'b1), .D(stg2_inc_r_i_1_n_0), .Q(stg2_inc_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFFF700000020)) stg2_inc_req_r_i_1 (.I0(stg2_inc_req_r_i_2_n_0), .I1(lim_state[10]), .I2(lim_state[7]), .I3(lim_state[8]), .I4(lim_state[0]), .I5(lim2stg2_inc), .O(stg2_inc_req_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000002)) stg2_inc_req_r_i_2 (.I0(\lim_state[0]_i_2_n_0 ), .I1(lim_state[12]), .I2(lim_state[11]), .I3(lim_state[13]), .I4(lim_state[9]), .I5(\lim_state[10]_i_3_n_0 ), .O(stg2_inc_req_r_i_2_n_0)); FDRE stg2_inc_req_r_reg (.C(CLK), .CE(1'b1), .D(stg2_inc_req_r_i_1_n_0), .Q(lim2stg2_inc), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair390" *) LUT3 #( .INIT(8'h47)) \stg2_tap_cnt[0]_i_1 (.I0(\wl_po_fine_cnt_reg[18] ), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt_reg[3]_0 [0]), .O(p_0_in__0[0])); LUT5 #( .INIT(32'h8BB8B88B)) \stg2_tap_cnt[1]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt[1]_i_3_n_0 ), .I3(\stg2_tap_cnt_reg[3]_0 [1]), .I4(\stg2_tap_cnt_reg[3]_0 [0]), .O(p_0_in__0[1])); LUT6 #( .INIT(64'h0000000000000100)) \stg2_tap_cnt[1]_i_3 (.I0(\stg2_tap_cnt[1]_i_4_n_0 ), .I1(lim_state[12]), .I2(\lim_state[2]_i_3_n_0 ), .I3(lim_state[7]), .I4(lim_state[6]), .I5(lim_state[5]), .O(\stg2_tap_cnt[1]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \stg2_tap_cnt[1]_i_4 (.I0(lim_state[9]), .I1(lim_state[8]), .I2(lim_state[11]), .I3(lim_state[10]), .I4(lim_state[13]), .I5(lim_state[4]), .O(\stg2_tap_cnt[1]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair373" *) LUT5 #( .INIT(32'h8B8B8BB8)) \stg2_tap_cnt[2]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [1]), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt_reg[3]_0 [2]), .I3(\stg2_tap_cnt[2]_i_3_n_0 ), .I4(\stg2_tap_cnt[2]_i_4_n_0 ), .O(p_0_in__0[2])); LUT6 #( .INIT(64'h0001000000000000)) \stg2_tap_cnt[2]_i_3 (.I0(\stg2_tap_cnt[2]_i_5_n_0 ), .I1(\lim_state[13]_i_4_n_0 ), .I2(lim_state[12]), .I3(\lim_state[2]_i_3_n_0 ), .I4(\stg2_tap_cnt_reg[3]_0 [1]), .I5(\stg2_tap_cnt_reg[3]_0 [0]), .O(\stg2_tap_cnt[2]_i_3_n_0 )); LUT6 #( .INIT(64'h1111111111101111)) \stg2_tap_cnt[2]_i_4 (.I0(\stg2_tap_cnt_reg[3]_0 [1]), .I1(\stg2_tap_cnt_reg[3]_0 [0]), .I2(lim_state[5]), .I3(lim_state[6]), .I4(lim_state[7]), .I5(\stg2_tap_cnt[2]_i_6_n_0 ), .O(\stg2_tap_cnt[2]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \stg2_tap_cnt[2]_i_5 (.I0(lim_state[6]), .I1(lim_state[5]), .I2(lim_state[4]), .I3(lim_state[7]), .I4(lim_state[13]), .O(\stg2_tap_cnt[2]_i_5_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \stg2_tap_cnt[2]_i_6 (.I0(\lim_state[2]_i_3_n_0 ), .I1(lim_state[12]), .I2(lim_state[4]), .I3(lim_state[13]), .I4(\lim_state[13]_i_4_n_0 ), .O(\stg2_tap_cnt[2]_i_6_n_0 )); LUT5 #( .INIT(32'h74474774)) \stg2_tap_cnt[3]_i_1 (.I0(\wl_po_fine_cnt_reg[3] ), .I1(\stg2_tap_cnt[3]_i_3_n_0 ), .I2(\stg2_tap_cnt[4]_i_3_n_0 ), .I3(stg2_tap_cnt_reg__0[3]), .I4(\stg2_tap_cnt_reg[3]_0 [2]), .O(p_0_in__0[3])); LUT6 #( .INIT(64'h0000000000000110)) \stg2_tap_cnt[3]_i_3 (.I0(wait_cnt_en_r_i_2_n_0), .I1(lim_state[3]), .I2(lim_state[1]), .I3(lim_state[0]), .I4(lim_state[4]), .I5(lim_state[2]), .O(\stg2_tap_cnt[3]_i_3_n_0 )); LUT6 #( .INIT(64'h7447747474744774)) \stg2_tap_cnt[4]_i_1 (.I0(\byte_r_reg[0] ), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(stg2_tap_cnt_reg__0[4]), .I3(\stg2_tap_cnt[4]_i_3_n_0 ), .I4(stg2_tap_cnt_reg__0[3]), .I5(\stg2_tap_cnt_reg[3]_0 [2]), .O(p_0_in__0[4])); LUT5 #( .INIT(32'h01FF0101)) \stg2_tap_cnt[4]_i_3 (.I0(\stg2_tap_cnt[1]_i_3_n_0 ), .I1(\stg2_tap_cnt_reg[3]_0 [0]), .I2(\stg2_tap_cnt_reg[3]_0 [1]), .I3(\stg2_tap_cnt[2]_i_3_n_0 ), .I4(\stg2_tap_cnt_reg[3]_0 [2]), .O(\stg2_tap_cnt[4]_i_3_n_0 )); LUT2 #( .INIT(4'hE)) \stg2_tap_cnt[5]_i_2 (.I0(\stg2_tap_cnt_reg[0]_0 ), .I1(\lim_state[10]_i_1_n_0 ), .O(stg2_tap_cnt0)); (* SOFT_HLUTNM = "soft_lutpair390" *) LUT3 #( .INIT(8'h74)) \stg2_tap_cnt[5]_i_3 (.I0(\wl_po_fine_cnt_reg[17] ), .I1(\stg2_tap_cnt_reg[0]_0 ), .I2(\stg2_tap_cnt[5]_i_6_n_0 ), .O(p_0_in__0[5])); LUT4 #( .INIT(16'h0440)) \stg2_tap_cnt[5]_i_4 (.I0(\lim_state[13]_i_7_n_0 ), .I1(\lim_state[1]_i_2_n_0 ), .I2(lim_state[0]), .I3(lim_state[1]), .O(\stg2_tap_cnt_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair367" *) LUT5 #( .INIT(32'hAAA96AAA)) \stg2_tap_cnt[5]_i_6 (.I0(stg2_tap_cnt_reg__0[5]), .I1(stg2_tap_cnt_reg__0[4]), .I2(\stg2_tap_cnt_reg[3]_0 [2]), .I3(stg2_tap_cnt_reg__0[3]), .I4(\stg2_tap_cnt[4]_i_3_n_0 ), .O(\stg2_tap_cnt[5]_i_6_n_0 )); FDRE \stg2_tap_cnt_reg[0] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[0]), .Q(\stg2_tap_cnt_reg[3]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \stg2_tap_cnt_reg[1] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[1]), .Q(\stg2_tap_cnt_reg[3]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \stg2_tap_cnt_reg[2] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[2]), .Q(\stg2_tap_cnt_reg[3]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \stg2_tap_cnt_reg[3] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[3]), .Q(stg2_tap_cnt_reg__0[3]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \stg2_tap_cnt_reg[4] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[4]), .Q(stg2_tap_cnt_reg__0[4]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \stg2_tap_cnt_reg[5] (.C(CLK), .CE(stg2_tap_cnt0), .D(p_0_in__0[5]), .Q(stg2_tap_cnt_reg__0[5]), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE stg3_dec2init_val_r1_reg (.C(CLK), .CE(1'b1), .D(stg3_dec2init_val_r), .Q(stg3_dec2init_val_r1), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFAFAA00000D00)) stg3_dec2init_val_r_i_1 (.I0(lim_state[4]), .I1(stg3_dec2init_val_r_i_2_n_0), .I2(lim_state[13]), .I3(wait_cnt_done), .I4(stg3_dec2init_val_r_i_3_n_0), .I5(stg3_dec2init_val_r), .O(stg3_dec2init_val_r_i_1_n_0)); LUT4 #( .INIT(16'h5557)) stg3_dec2init_val_r_i_10 (.I0(mod_sub0_return0_carry_n_4), .I1(mod_sub0_return0_carry_n_6), .I2(mod_sub0_return0_carry_n_5), .I3(mod_sub0_return0_carry_n_7), .O(stg3_dec2init_val_r_i_10_n_0)); LUT6 #( .INIT(64'h40F440F4FFFF40F4)) stg3_dec2init_val_r_i_12 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .I2(\mmcm_init_lead_reg_n_0_[1] ), .I3(\mmcm_current_reg_n_0_[1] ), .I4(\mmcm_init_lead_reg_n_0_[2] ), .I5(\mmcm_current_reg_n_0_[2] ), .O(stg3_dec2init_val_r_i_12_n_0)); (* SOFT_HLUTNM = "soft_lutpair375" *) LUT2 #( .INIT(4'h2)) stg3_dec2init_val_r_i_13 (.I0(\mmcm_init_lead_reg_n_0_[4] ), .I1(\mmcm_current_reg_n_0_[4] ), .O(stg3_dec2init_val_r_i_13_n_0)); (* SOFT_HLUTNM = "soft_lutpair393" *) LUT2 #( .INIT(4'h9)) stg3_dec2init_val_r_i_14 (.I0(\mmcm_current_reg_n_0_[0] ), .I1(\mmcm_init_lead_reg_n_0_[0] ), .O(stg3_dec2init_val_r_reg_0)); LUT6 #( .INIT(64'h4445554544555555)) stg3_dec2init_val_r_i_2 (.I0(stg3_dec_r), .I1(stg3_dec2init_val_r_i_4_n_0), .I2(stg3_dec2init_val_r_i_5_n_0), .I3(stg3_dec2init_val_r_i_6_n_0), .I4(stg3_dec2init_val_r_i_7_n_0), .I5(stg3_dec2init_val_r_i_8_n_0), .O(stg3_dec2init_val_r_i_2_n_0)); LUT4 #( .INIT(16'hDDDF)) stg3_dec2init_val_r_i_3 (.I0(\lim_state[4]_i_3_n_0 ), .I1(\lim_state[2]_i_3_n_0 ), .I2(lim_state[4]), .I3(lim_state[13]), .O(stg3_dec2init_val_r_i_3_n_0)); LUT6 #( .INIT(64'h8000000000000000)) stg3_dec2init_val_r_i_4 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(\stg3_tap_cnt_reg_n_0_[5] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt_reg_n_0_[3] ), .I5(\stg3_tap_cnt_reg_n_0_[2] ), .O(stg3_dec2init_val_r_i_4_n_0)); LUT3 #( .INIT(8'h04)) stg3_dec2init_val_r_i_5 (.I0(mod_sub0_return0__14_carry__0_n_6), .I1(mod_sub0_return0__14_carry__0_n_1), .I2(mod_sub0_return0__14_carry__0_n_7), .O(stg3_dec2init_val_r_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair375" *) LUT5 #( .INIT(32'hB2BB2222)) stg3_dec2init_val_r_i_6 (.I0(\mmcm_init_lead_reg_n_0_[5] ), .I1(\mmcm_current_reg_n_0_[5] ), .I2(\mmcm_init_lead_reg_n_0_[4] ), .I3(\mmcm_current_reg_n_0_[4] ), .I4(stg3_dec2init_val_r_i_9_n_0), .O(stg3_dec2init_val_r_i_6_n_0)); LUT4 #( .INIT(16'h0002)) stg3_dec2init_val_r_i_7 (.I0(stg3_dec2init_val_r_i_10_n_0), .I1(mod_sub0_return0_carry__0_n_7), .I2(mod_sub0_return0_carry__0_n_5), .I3(mod_sub0_return0_carry__0_n_6), .O(stg3_dec2init_val_r_i_7_n_0)); LUT4 #( .INIT(16'h5557)) stg3_dec2init_val_r_i_8 (.I0(mod_sub0_return0__14_carry_n_4), .I1(mod_sub0_return0__14_carry_n_6), .I2(mod_sub0_return0__14_carry_n_5), .I3(\mmcm_current_reg[0]_0 ), .O(stg3_dec2init_val_r_i_8_n_0)); LUT6 #( .INIT(64'hFFFFFFFFB000FFB0)) stg3_dec2init_val_r_i_9 (.I0(\mmcm_init_lead_reg_n_0_[2] ), .I1(\mmcm_current_reg_n_0_[2] ), .I2(stg3_dec2init_val_r_i_12_n_0), .I3(\mmcm_init_lead_reg_n_0_[3] ), .I4(\mmcm_current_reg_n_0_[3] ), .I5(stg3_dec2init_val_r_i_13_n_0), .O(stg3_dec2init_val_r_i_9_n_0)); FDRE stg3_dec2init_val_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec2init_val_r_i_1_n_0), .Q(stg3_dec2init_val_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFDFFFF30200000)) stg3_dec_r_i_1 (.I0(stg3_dec_r_i_2_n_0), .I1(stg3_dec_r_i_3_n_0), .I2(stg3_dec_r_i_4_n_0), .I3(lim_state[0]), .I4(stg3_dec_r_i_5_n_0), .I5(stg3_dec_r), .O(stg3_dec_r_i_1_n_0)); LUT4 #( .INIT(16'h8000)) stg3_dec_r_i_2 (.I0(\lim_state[6]_i_10_n_0 ), .I1(lim_state[4]), .I2(wait_cnt_done), .I3(stg3_dec_r), .O(stg3_dec_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair384" *) LUT2 #( .INIT(4'hE)) stg3_dec_r_i_3 (.I0(lim_state[2]), .I1(lim_state[1]), .O(stg3_dec_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair392" *) LUT3 #( .INIT(8'h04)) stg3_dec_r_i_4 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[4]), .O(stg3_dec_r_i_4_n_0)); LUT6 #( .INIT(64'h0000000000000004)) stg3_dec_r_i_5 (.I0(lim_state[3]), .I1(\lim_state[1]_i_2_n_0 ), .I2(lim_state[5]), .I3(lim_state[6]), .I4(lim_state[7]), .I5(lim_state[8]), .O(stg3_dec_r_i_5_n_0)); FDRE stg3_dec_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec_r_i_1_n_0), .Q(stg3_dec_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFDFF00000020)) stg3_dec_req_r_i_1 (.I0(stg3_dec_req_r_i_2_n_0), .I1(lim_state[7]), .I2(lim_state[6]), .I3(lim_state[9]), .I4(lim_state[5]), .I5(lim2stg3_dec), .O(stg3_dec_req_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000002)) stg3_dec_req_r_i_2 (.I0(\lim_state[0]_i_2_n_0 ), .I1(stg3_dec_req_r_i_3_n_0), .I2(lim_state[13]), .I3(lim_state[12]), .I4(lim_state[0]), .I5(lim_state[8]), .O(stg3_dec_req_r_i_2_n_0)); LUT2 #( .INIT(4'hE)) stg3_dec_req_r_i_3 (.I0(lim_state[11]), .I1(lim_state[10]), .O(stg3_dec_req_r_i_3_n_0)); FDRE stg3_dec_req_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec_req_r_i_1_n_0), .Q(lim2stg3_dec), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair371" *) LUT3 #( .INIT(8'h69)) \stg3_dec_val[3]_i_1 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .O(stg3_dec_val00_out[3])); (* SOFT_HLUTNM = "soft_lutpair371" *) LUT5 #( .INIT(32'h4DB2B24D)) \stg3_dec_val[4]_i_1 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg3_init_val[4]), .O(stg3_dec_val00_out[4])); LUT5 #( .INIT(32'hFF00FF71)) \stg3_dec_val[5]_i_1 (.I0(\stg3_inc_val[5]_i_2_n_0 ), .I1(stg3_init_val[4]), .I2(\wl_po_fine_cnt_reg[17] ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(stg3_init_val[5]), .O(\stg3_dec_val[5]_i_1_n_0 )); LUT6 #( .INIT(64'hB2FF00B24D00FF4D)) \stg3_dec_val[5]_i_2 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg3_init_val[4]), .I5(stg3_init_val[5]), .O(\stg3_dec_val[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFEE0FFFF0000FEE0)) \stg3_dec_val[5]_i_3 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\wl_po_fine_cnt_reg[14] [0]), .I2(\stg3_tap_cnt_reg[2]_0 [1]), .I3(\wl_po_fine_cnt_reg[14] [1]), .I4(\wl_po_fine_cnt_reg[3] ), .I5(\stg3_tap_cnt_reg[2]_0 [2]), .O(\stg3_dec_val[5]_i_3_n_0 )); FDRE \stg3_dec_val_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(stg3_dec_val[0]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE \stg3_dec_val_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(stg3_dec_val[1]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE \stg3_dec_val_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(stg3_dec_val[2]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE \stg3_dec_val_reg[3] (.C(CLK), .CE(1'b1), .D(stg3_dec_val00_out[3]), .Q(stg3_dec_val[3]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE \stg3_dec_val_reg[4] (.C(CLK), .CE(1'b1), .D(stg3_dec_val00_out[4]), .Q(stg3_dec_val[4]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE \stg3_dec_val_reg[5] (.C(CLK), .CE(1'b1), .D(\stg3_dec_val[5]_i_2_n_0 ), .Q(stg3_dec_val[5]), .R(\stg3_dec_val[5]_i_1_n_0 )); FDRE stg3_inc2init_val_r1_reg (.C(CLK), .CE(1'b1), .D(stg3_inc2init_val_r), .Q(stg3_inc2init_val_r1), .R(rstdiv0_sync_r1_reg_rep__9)); LUT5 #( .INIT(32'hFF0B0008)) stg3_inc2init_val_r_i_1 (.I0(stg3_dec_r), .I1(stg3_dec_r_i_2_n_0), .I2(lim_state[11]), .I3(stg3_inc2init_val_r_i_2_n_0), .I4(stg3_inc2init_val_r), .O(stg3_inc2init_val_r_i_1_n_0)); LUT6 #( .INIT(64'hEEEEEEEEFFFFFFEF)) stg3_inc2init_val_r_i_2 (.I0(wait_cnt_en_r_i_3_n_0), .I1(\lim_state[2]_i_3_n_0 ), .I2(stg3_inc2init_val_r_i_3_n_0), .I3(stg2_inc_r_i_2_n_0), .I4(lim_state[4]), .I5(\lim_state[1]_i_2_n_0 ), .O(stg3_inc2init_val_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair386" *) LUT3 #( .INIT(8'h20)) stg3_inc2init_val_r_i_3 (.I0(\lim_state[12]_i_3_n_0 ), .I1(stg3_dec2init_val_r), .I2(stg3_inc2init_val_r), .O(stg3_inc2init_val_r_i_3_n_0)); FDRE stg3_inc2init_val_r_reg (.C(CLK), .CE(1'b1), .D(stg3_inc2init_val_r_i_1_n_0), .Q(stg3_inc2init_val_r), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFFF700000020)) stg3_inc_req_r_i_1 (.I0(stg3_dec_req_r_i_2_n_0), .I1(lim_state[9]), .I2(lim_state[5]), .I3(lim_state[7]), .I4(lim_state[6]), .I5(lim2stg3_inc), .O(stg3_inc_req_r_i_1_n_0)); FDRE stg3_inc_req_r_reg (.C(CLK), .CE(1'b1), .D(stg3_inc_req_r_i_1_n_0), .Q(lim2stg3_inc), .R(rstdiv0_sync_r1_reg_rep__10)); LUT3 #( .INIT(8'hF6)) \stg3_inc_val[0]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(\stg3_tap_cnt_reg[2]_0 [0]), .I2(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair370" *) LUT5 #( .INIT(32'hFFFF9666)) \stg3_inc_val[1]_i_1 (.I0(\stg3_tap_cnt_reg[2]_0 [1]), .I1(\wl_po_fine_cnt_reg[14] [1]), .I2(\stg3_tap_cnt_reg[2]_0 [0]), .I3(\wl_po_fine_cnt_reg[14] [0]), .I4(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[1]_i_1_n_0 )); LUT4 #( .INIT(16'hFF96)) \stg3_inc_val[2]_i_1 (.I0(\stg3_tap_cnt_reg[2]_0 [2]), .I1(\wl_po_fine_cnt_reg[3] ), .I2(\stg3_inc_val[2]_i_2_n_0 ), .I3(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair370" *) LUT4 #( .INIT(16'h077F)) \stg3_inc_val[2]_i_2 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\wl_po_fine_cnt_reg[14] [0]), .I2(\wl_po_fine_cnt_reg[14] [1]), .I3(\stg3_tap_cnt_reg[2]_0 [1]), .O(\stg3_inc_val[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair381" *) LUT4 #( .INIT(16'hFF96)) \stg3_inc_val[3]_i_1 (.I0(stg3_init_val[3]), .I1(\byte_r_reg[0] ), .I2(\stg3_inc_val[3]_i_2_n_0 ), .I3(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[3]_i_1_n_0 )); LUT6 #( .INIT(64'h077FFFFF0000077F)) \stg3_inc_val[3]_i_2 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\wl_po_fine_cnt_reg[14] [0]), .I2(\wl_po_fine_cnt_reg[14] [1]), .I3(\stg3_tap_cnt_reg[2]_0 [1]), .I4(\stg3_tap_cnt_reg[2]_0 [2]), .I5(\wl_po_fine_cnt_reg[3] ), .O(\stg3_inc_val[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair374" *) LUT4 #( .INIT(16'hFF69)) \stg3_inc_val[4]_i_1 (.I0(stg3_init_val[4]), .I1(\wl_po_fine_cnt_reg[17] ), .I2(\stg3_inc_val[5]_i_2_n_0 ), .I3(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair374" *) LUT5 #( .INIT(32'hFFFF718E)) \stg3_inc_val[5]_i_1 (.I0(\stg3_inc_val[5]_i_2_n_0 ), .I1(stg3_init_val[4]), .I2(\wl_po_fine_cnt_reg[17] ), .I3(stg3_init_val[5]), .I4(\stg3_inc_val[5]_i_3_n_0 ), .O(\stg3_inc_val[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair381" *) LUT3 #( .INIT(8'h4D)) \stg3_inc_val[5]_i_2 (.I0(\stg3_inc_val[3]_i_2_n_0 ), .I1(stg3_init_val[3]), .I2(\byte_r_reg[0] ), .O(\stg3_inc_val[5]_i_2_n_0 )); LUT6 #( .INIT(64'hB2FF00B200000000)) \stg3_inc_val[5]_i_3 (.I0(\stg3_dec_val[5]_i_3_n_0 ), .I1(\byte_r_reg[0] ), .I2(stg3_init_val[3]), .I3(\wl_po_fine_cnt_reg[17] ), .I4(stg3_init_val[4]), .I5(stg3_init_val[5]), .O(\stg3_inc_val[5]_i_3_n_0 )); FDRE \stg3_inc_val_reg[0] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[0]_i_1_n_0 ), .Q(stg3_inc_val[0]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \stg3_inc_val_reg[1] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[1]_i_1_n_0 ), .Q(stg3_inc_val[1]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \stg3_inc_val_reg[2] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[2]_i_1_n_0 ), .Q(stg3_inc_val[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \stg3_inc_val_reg[3] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[3]_i_1_n_0 ), .Q(stg3_inc_val[3]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \stg3_inc_val_reg[4] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[4]_i_1_n_0 ), .Q(stg3_inc_val[4]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \stg3_inc_val_reg[5] (.C(CLK), .CE(1'b1), .D(\stg3_inc_val[5]_i_1_n_0 ), .Q(stg3_inc_val[5]), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hFFFFFFF70000FF00)) stg3_init_dec_r_i_1 (.I0(\lim_state[6]_i_3_n_0 ), .I1(stg3_init_dec_r_i_2_n_0), .I2(lim_state[0]), .I3(stg3_init_dec_r_i_3_n_0), .I4(stg3_init_dec_r_i_4_n_0), .I5(stg3_init_dec_r), .O(stg3_init_dec_r_i_1_n_0)); LUT3 #( .INIT(8'h02)) stg3_init_dec_r_i_2 (.I0(po_rdy), .I1(lim2stg3_dec), .I2(lim2stg3_inc), .O(stg3_init_dec_r_i_2_n_0)); LUT3 #( .INIT(8'h04)) stg3_init_dec_r_i_3 (.I0(lim_start_r), .I1(lim_start), .I2(lim_state[9]), .O(stg3_init_dec_r_i_3_n_0)); LUT5 #( .INIT(32'hEFEFEFFF)) stg3_init_dec_r_i_4 (.I0(\lim_state[13]_i_7_n_0 ), .I1(lim_state[1]), .I2(\lim_state[6]_i_6_n_0 ), .I3(lim_state[9]), .I4(lim_state[0]), .O(stg3_init_dec_r_i_4_n_0)); FDRE stg3_init_dec_r_reg (.C(CLK), .CE(1'b1), .D(stg3_init_dec_r_i_1_n_0), .Q(stg3_init_dec_r), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \stg3_init_val_reg[0] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[0]), .Q(\stg3_tap_cnt_reg[2]_0 [0]), .R(1'b0)); FDRE \stg3_init_val_reg[1] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[1]), .Q(\stg3_tap_cnt_reg[2]_0 [1]), .R(1'b0)); FDRE \stg3_init_val_reg[2] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[2]), .Q(\stg3_tap_cnt_reg[2]_0 [2]), .R(1'b0)); FDRE \stg3_init_val_reg[3] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[3]), .Q(stg3_init_val[3]), .R(1'b0)); FDRE \stg3_init_val_reg[4] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[4]), .Q(stg3_init_val[4]), .R(1'b0)); FDRE \stg3_init_val_reg[5] (.C(CLK), .CE(1'b1), .D(oclkdelay_calib_done_r_reg[5]), .Q(stg3_init_val[5]), .R(1'b0)); LUT5 #( .INIT(32'hAAAAFBAA)) \stg3_left_lim[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(stg3_inc2init_val_r), .I2(stg3_inc2init_val_r1), .I3(lim_start), .I4(lim_start_r), .O(\stg3_left_lim[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \stg3_left_lim[5]_i_2 (.I0(stg3_inc2init_val_r), .I1(stg3_inc2init_val_r1), .O(stg3_left_lim0)); FDRE \stg3_left_lim_reg[0] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[0] ), .Q(scanning_right_r_reg_0[0]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE \stg3_left_lim_reg[1] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[1] ), .Q(scanning_right_r_reg_0[1]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE \stg3_left_lim_reg[2] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[2] ), .Q(scanning_right_r_reg_0[2]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE \stg3_left_lim_reg[3] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[3] ), .Q(scanning_right_r_reg_0[3]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE \stg3_left_lim_reg[4] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[4] ), .Q(scanning_right_r_reg_0[4]), .R(\stg3_left_lim[5]_i_1_n_0 )); FDRE \stg3_left_lim_reg[5] (.C(CLK), .CE(stg3_left_lim0), .D(\stg3_tap_cnt_reg_n_0_[5] ), .Q(scanning_right_r_reg_0[5]), .R(\stg3_left_lim[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAAAAFBAA)) \stg3_right_lim[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(stg3_dec2init_val_r), .I2(stg3_dec2init_val_r1), .I3(lim_start), .I4(lim_start_r), .O(\stg3_right_lim[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \stg3_right_lim[5]_i_2 (.I0(stg3_dec2init_val_r), .I1(stg3_dec2init_val_r1), .O(stg3_right_lim0)); FDRE \stg3_right_lim_reg[0] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[0] ), .Q(oclkdelay_center_calib_start_r_reg_0[0]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE \stg3_right_lim_reg[1] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[1] ), .Q(oclkdelay_center_calib_start_r_reg_0[1]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE \stg3_right_lim_reg[2] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[2] ), .Q(oclkdelay_center_calib_start_r_reg_0[2]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE \stg3_right_lim_reg[3] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[3] ), .Q(oclkdelay_center_calib_start_r_reg_0[3]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE \stg3_right_lim_reg[4] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[4] ), .Q(oclkdelay_center_calib_start_r_reg_0[4]), .R(\stg3_right_lim[5]_i_1_n_0 )); FDRE \stg3_right_lim_reg[5] (.C(CLK), .CE(stg3_right_lim0), .D(\stg3_tap_cnt_reg_n_0_[5] ), .Q(oclkdelay_center_calib_start_r_reg_0[5]), .R(\stg3_right_lim[5]_i_1_n_0 )); LUT3 #( .INIT(8'h3A)) \stg3_tap_cnt[0]_i_1 (.I0(\stg3_tap_cnt_reg[2]_0 [0]), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(rstdiv0_sync_r1_reg_rep__26_0), .O(\stg3_tap_cnt[0]_i_1_n_0 )); LUT5 #( .INIT(32'h96FF9600)) \stg3_tap_cnt[1]_i_1 (.I0(\stg3_tap_cnt[1]_i_2_n_0 ), .I1(\stg3_tap_cnt_reg_n_0_[1] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(rstdiv0_sync_r1_reg_rep__26_0), .I4(\stg3_tap_cnt_reg[2]_0 [1]), .O(\stg3_tap_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \stg3_tap_cnt[1]_i_2 (.I0(\stg2_tap_cnt[1]_i_4_n_0 ), .I1(lim_state[12]), .I2(\lim_state[2]_i_3_n_0 ), .I3(lim_state[7]), .I4(lim_state[6]), .I5(lim_state[5]), .O(\stg3_tap_cnt[1]_i_2_n_0 )); LUT4 #( .INIT(16'h6F60)) \stg3_tap_cnt[2]_i_1 (.I0(\stg3_tap_cnt_reg_n_0_[2] ), .I1(\stg3_tap_cnt[2]_i_2_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__26_0), .I3(\stg3_tap_cnt_reg[2]_0 [2]), .O(\stg3_tap_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h001000000000FFEF)) \stg3_tap_cnt[2]_i_2 (.I0(\lim_state[2]_i_3_n_0 ), .I1(lim_state[12]), .I2(lim_state[5]), .I3(\stg3_tap_cnt[3]_i_4_n_0 ), .I4(\stg3_tap_cnt_reg_n_0_[0] ), .I5(\stg3_tap_cnt_reg_n_0_[1] ), .O(\stg3_tap_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hD32CFFFFD32C0000)) \stg3_tap_cnt[3]_i_1 (.I0(\stg3_tap_cnt[3]_i_2_n_0 ), .I1(\stg3_tap_cnt[3]_i_3_n_0 ), .I2(\stg3_tap_cnt_reg_n_0_[2] ), .I3(\stg3_tap_cnt_reg_n_0_[3] ), .I4(rstdiv0_sync_r1_reg_rep__26_0), .I5(stg3_init_val[3]), .O(\stg3_tap_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000800)) \stg3_tap_cnt[3]_i_2 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(\stg3_tap_cnt[3]_i_4_n_0 ), .I3(lim_state[5]), .I4(lim_state[12]), .I5(\lim_state[2]_i_3_n_0 ), .O(\stg3_tap_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h1111111111101111)) \stg3_tap_cnt[3]_i_3 (.I0(\stg3_tap_cnt_reg_n_0_[1] ), .I1(\stg3_tap_cnt_reg_n_0_[0] ), .I2(\lim_state[2]_i_3_n_0 ), .I3(lim_state[12]), .I4(lim_state[5]), .I5(\stg3_tap_cnt[3]_i_4_n_0 ), .O(\stg3_tap_cnt[3]_i_3_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \stg3_tap_cnt[3]_i_4 (.I0(\lim_state[13]_i_4_n_0 ), .I1(lim_state[7]), .I2(lim_state[6]), .I3(lim_state[4]), .I4(lim_state[13]), .O(\stg3_tap_cnt[3]_i_4_n_0 )); LUT5 #( .INIT(32'h56FF5600)) \stg3_tap_cnt[4]_i_1 (.I0(\stg3_tap_cnt_reg_n_0_[4] ), .I1(\stg3_tap_cnt[5]_i_4_n_0 ), .I2(\stg3_tap_cnt[5]_i_5_n_0 ), .I3(rstdiv0_sync_r1_reg_rep__26_0), .I4(stg3_init_val[4]), .O(\stg3_tap_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'h1400FFFF)) \stg3_tap_cnt[5]_i_1 (.I0(lim_state[11]), .I1(lim_state[5]), .I2(lim_state[6]), .I3(\lim_state[9]_i_2_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__26_0), .O(stg3_tap_cnt0)); LUT6 #( .INIT(64'hD32CFFFFD32C0000)) \stg3_tap_cnt[5]_i_2 (.I0(\stg3_tap_cnt[5]_i_4_n_0 ), .I1(\stg3_tap_cnt[5]_i_5_n_0 ), .I2(\stg3_tap_cnt_reg_n_0_[4] ), .I3(\stg3_tap_cnt_reg_n_0_[5] ), .I4(rstdiv0_sync_r1_reg_rep__26_0), .I5(stg3_init_val[5]), .O(\stg3_tap_cnt[5]_i_2_n_0 )); LUT5 #( .INIT(32'h00008000)) \stg3_tap_cnt[5]_i_4 (.I0(\stg3_tap_cnt_reg_n_0_[2] ), .I1(\stg3_tap_cnt_reg_n_0_[3] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt[1]_i_2_n_0 ), .O(\stg3_tap_cnt[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair377" *) LUT5 #( .INIT(32'h00000001)) \stg3_tap_cnt[5]_i_5 (.I0(\stg3_tap_cnt_reg_n_0_[3] ), .I1(\stg3_tap_cnt_reg_n_0_[2] ), .I2(\stg3_tap_cnt_reg_n_0_[0] ), .I3(\stg3_tap_cnt_reg_n_0_[1] ), .I4(\stg3_tap_cnt[5]_i_6_n_0 ), .O(\stg3_tap_cnt[5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair380" *) LUT4 #( .INIT(16'h0004)) \stg3_tap_cnt[5]_i_6 (.I0(\stg3_tap_cnt[3]_i_4_n_0 ), .I1(lim_state[5]), .I2(lim_state[12]), .I3(\lim_state[2]_i_3_n_0 ), .O(\stg3_tap_cnt[5]_i_6_n_0 )); FDRE \stg3_tap_cnt_reg[0] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[0]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[0] ), .R(1'b0)); FDRE \stg3_tap_cnt_reg[1] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[1]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[1] ), .R(1'b0)); FDRE \stg3_tap_cnt_reg[2] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[2]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[2] ), .R(1'b0)); FDRE \stg3_tap_cnt_reg[3] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[3]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[3] ), .R(1'b0)); FDRE \stg3_tap_cnt_reg[4] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[4]_i_1_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[4] ), .R(1'b0)); FDRE \stg3_tap_cnt_reg[5] (.C(CLK), .CE(stg3_tap_cnt0), .D(\stg3_tap_cnt[5]_i_2_n_0 ), .Q(\stg3_tap_cnt_reg_n_0_[5] ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) wait_cnt_done_i_1 (.I0(wait_cnt_en_r), .I1(wait_cnt_r_reg__0[2]), .I2(wait_cnt_r_reg__0[3]), .I3(wait_cnt_r_reg__0[1]), .I4(wait_cnt_r_reg__0[0]), .O(wait_cnt_done_i_1_n_0)); FDRE wait_cnt_done_reg (.C(CLK), .CE(1'b1), .D(wait_cnt_done_i_1_n_0), .Q(wait_cnt_done), .R(1'b0)); LUT6 #( .INIT(64'h0000000000010110)) wait_cnt_en_r_i_1 (.I0(wait_cnt_en_r_i_2_n_0), .I1(lim_state[0]), .I2(lim_state[1]), .I3(lim_state[4]), .I4(lim_state[2]), .I5(lim_state[3]), .O(wait_cnt_en_r0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) wait_cnt_en_r_i_2 (.I0(wait_cnt_en_r_i_3_n_0), .I1(lim_state[13]), .I2(lim_state[9]), .I3(lim_state[12]), .I4(lim_state[10]), .I5(lim_state[11]), .O(wait_cnt_en_r_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) wait_cnt_en_r_i_3 (.I0(lim_state[5]), .I1(lim_state[6]), .I2(lim_state[7]), .I3(lim_state[8]), .O(wait_cnt_en_r_i_3_n_0)); FDRE wait_cnt_en_r_reg (.C(CLK), .CE(1'b1), .D(wait_cnt_en_r0), .Q(wait_cnt_en_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair394" *) LUT1 #( .INIT(2'h1)) \wait_cnt_r[0]_i_1 (.I0(wait_cnt_r_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair394" *) LUT2 #( .INIT(4'h6)) \wait_cnt_r[1]_i_1 (.I0(wait_cnt_r_reg__0[0]), .I1(wait_cnt_r_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair385" *) LUT3 #( .INIT(8'h6A)) \wait_cnt_r[2]_i_1 (.I0(wait_cnt_r_reg__0[2]), .I1(wait_cnt_r_reg__0[1]), .I2(wait_cnt_r_reg__0[0]), .O(p_0_in[2])); LUT5 #( .INIT(32'h0080FFFF)) \wait_cnt_r[3]_i_1 (.I0(wait_cnt_r_reg__0[2]), .I1(wait_cnt_r_reg__0[3]), .I2(wait_cnt_r_reg__0[1]), .I3(wait_cnt_r_reg__0[0]), .I4(wait_cnt_en_r), .O(\wait_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair385" *) LUT4 #( .INIT(16'h6AAA)) \wait_cnt_r[3]_i_2 (.I0(wait_cnt_r_reg__0[3]), .I1(wait_cnt_r_reg__0[0]), .I2(wait_cnt_r_reg__0[1]), .I3(wait_cnt_r_reg__0[2]), .O(p_0_in[3])); FDRE \wait_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in[0]), .Q(wait_cnt_r_reg__0[0]), .R(\wait_cnt_r[3]_i_1_n_0 )); FDRE \wait_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in[1]), .Q(wait_cnt_r_reg__0[1]), .R(\wait_cnt_r[3]_i_1_n_0 )); FDRE \wait_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in[2]), .Q(wait_cnt_r_reg__0[2]), .R(\wait_cnt_r[3]_i_1_n_0 )); FDRE \wait_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in[3]), .Q(wait_cnt_r_reg__0[3]), .R(\wait_cnt_r[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFF7F0C00)) write_request_r_i_1 (.I0(done_r_reg_1), .I1(write_request_r_i_2_n_0), .I2(lim_state[3]), .I3(lim_state[2]), .I4(lim2init_write_request), .O(write_request_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair372" *) LUT5 #( .INIT(32'h00000002)) write_request_r_i_2 (.I0(\lim_state[4]_i_3_n_0 ), .I1(lim_state[4]), .I2(lim_state[13]), .I3(lim_state[1]), .I4(lim_state[0]), .O(write_request_r_i_2_n_0)); FDRE write_request_r_reg (.C(CLK), .CE(1'b1), .D(write_request_r_i_1_n_0), .Q(lim2init_write_request), .R(rstdiv0_sync_r1_reg_rep__10)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_mux (po_rdy, po_stg23_incdec, \po_wait_r_reg[3]_0 , D_po_sel_fine_oclk_delay125_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , po_stg23_sel_r_reg_0, CLK, stg3_inc_req_r_reg, stg3_dec_req_r_reg, Q, calib_in_common, \calib_zero_inputs_reg[1] , rstdiv0_sync_r1_reg_rep__25, \gen_byte_sel_div1.calib_in_common_reg , ck_addr_cmd_delay_done, oclkdelay_calib_done_r_reg, mpr_rdlvl_done_r_reg, \gen_byte_sel_div1.calib_in_common_reg_0 , \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , stg2_dec_req_r_reg, setup_po, rstdiv0_sync_r1_reg_rep__10); output po_rdy; output po_stg23_incdec; output \po_wait_r_reg[3]_0 ; output D_po_sel_fine_oclk_delay125_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output po_stg23_sel_r_reg_0; input CLK; input stg3_inc_req_r_reg; input stg3_dec_req_r_reg; input [1:0]Q; input calib_in_common; input [1:0]\calib_zero_inputs_reg[1] ; input rstdiv0_sync_r1_reg_rep__25; input \gen_byte_sel_div1.calib_in_common_reg ; input ck_addr_cmd_delay_done; input oclkdelay_calib_done_r_reg; input mpr_rdlvl_done_r_reg; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input stg2_dec_req_r_reg; input setup_po; input rstdiv0_sync_r1_reg_rep__10; wire CLK; wire D_po_sel_fine_oclk_delay125_out; wire [1:0]Q; wire calib_in_common; wire [1:0]\calib_zero_inputs_reg[1] ; wire ck_addr_cmd_delay_done; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire mpr_rdlvl_done_r_reg; wire oclkdelay_calib_done_r_reg; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire po_en_stg23_r_i_1_n_0; wire po_rdy; wire po_rdy_ns; wire [0:0]po_sel_stg2stg3; wire [1:0]po_setup_r; wire po_setup_r0; wire \po_setup_r[0]_i_1_n_0 ; wire \po_setup_r[1]_i_1_n_0 ; wire po_stg23_incdec; wire po_stg23_sel; wire po_stg23_sel_r_reg_0; wire [3:0]po_wait_r; wire \po_wait_r[0]_i_1_n_0 ; wire \po_wait_r[1]_i_1_n_0 ; wire \po_wait_r[2]_i_1_n_0 ; wire \po_wait_r[3]_i_1_n_0 ; wire \po_wait_r_reg[3]_0 ; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__25; wire setup_po; wire stg2_dec_req_r_reg; wire stg3_dec_req_r_reg; wire stg3_inc_req_r_reg; LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__3 (.I0(\gen_byte_sel_div1.calib_in_common_reg ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_2 )); LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_3 )); LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__5 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_4 )); LUT6 #( .INIT(64'h0000000000800000)) phaser_out_i_4__6 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(ck_addr_cmd_delay_done), .I2(po_stg23_sel), .I3(oclkdelay_calib_done_r_reg), .I4(mpr_rdlvl_done_r_reg), .I5(\calib_zero_inputs_reg[1] [0]), .O(\po_counter_read_val_reg[8]_5 )); (* SOFT_HLUTNM = "soft_lutpair395" *) LUT5 #( .INIT(32'h00000800)) phaser_out_i_5 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(D_po_sel_fine_oclk_delay125_out)); (* SOFT_HLUTNM = "soft_lutpair395" *) LUT5 #( .INIT(32'h00000100)) phaser_out_i_5__0 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair396" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_5__1 (.I0(Q[1]), .I1(Q[0]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_0 )); (* SOFT_HLUTNM = "soft_lutpair396" *) LUT5 #( .INIT(32'h00000400)) phaser_out_i_5__2 (.I0(Q[0]), .I1(Q[1]), .I2(calib_in_common), .I3(po_sel_stg2stg3), .I4(\calib_zero_inputs_reg[1] [1]), .O(\po_counter_read_val_reg[8]_1 )); LUT4 #( .INIT(16'h0800)) phaser_out_i_6 (.I0(ck_addr_cmd_delay_done), .I1(po_stg23_sel), .I2(oclkdelay_calib_done_r_reg), .I3(mpr_rdlvl_done_r_reg), .O(po_sel_stg2stg3)); (* SOFT_HLUTNM = "soft_lutpair397" *) LUT3 #( .INIT(8'h04)) po_en_stg23_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(po_setup_r[0]), .I2(po_setup_r[1]), .O(po_en_stg23_r_i_1_n_0)); FDRE po_en_stg23_r_reg (.C(CLK), .CE(1'b1), .D(po_en_stg23_r_i_1_n_0), .Q(\po_wait_r_reg[3]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000001)) po_rdy_r_i_1 (.I0(setup_po), .I1(\po_wait_r[3]_i_1_n_0 ), .I2(po_setup_r0), .I3(\po_wait_r[0]_i_1_n_0 ), .I4(\po_wait_r[1]_i_1_n_0 ), .I5(\po_wait_r[2]_i_1_n_0 ), .O(po_rdy_ns)); (* SOFT_HLUTNM = "soft_lutpair397" *) LUT2 #( .INIT(4'hE)) po_rdy_r_i_3 (.I0(po_setup_r[0]), .I1(po_setup_r[1]), .O(po_setup_r0)); FDRE po_rdy_r_reg (.C(CLK), .CE(1'b1), .D(po_rdy_ns), .Q(po_rdy), .R(1'b0)); LUT3 #( .INIT(8'hF2)) \po_setup_r[0]_i_1 (.I0(po_setup_r[1]), .I1(po_setup_r[0]), .I2(setup_po), .O(\po_setup_r[0]_i_1_n_0 )); LUT3 #( .INIT(8'hF8)) \po_setup_r[1]_i_1 (.I0(po_setup_r[1]), .I1(po_setup_r[0]), .I2(setup_po), .O(\po_setup_r[1]_i_1_n_0 )); FDRE \po_setup_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_setup_r[0]_i_1_n_0 ), .Q(po_setup_r[0]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \po_setup_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_setup_r[1]_i_1_n_0 ), .Q(po_setup_r[1]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE po_stg23_incdec_r_reg (.C(CLK), .CE(1'b1), .D(stg3_inc_req_r_reg), .Q(po_stg23_incdec), .R(1'b0)); LUT6 #( .INIT(64'h5555555100000000)) po_stg23_sel_r_i_2 (.I0(stg2_dec_req_r_reg), .I1(po_wait_r[0]), .I2(po_wait_r[1]), .I3(po_wait_r[3]), .I4(po_wait_r[2]), .I5(po_stg23_sel), .O(po_stg23_sel_r_reg_0)); FDRE po_stg23_sel_r_reg (.C(CLK), .CE(1'b1), .D(stg3_dec_req_r_reg), .Q(po_stg23_sel), .R(1'b0)); LUT6 #( .INIT(64'h00000000000000FE)) \po_wait_r[0]_i_1 (.I0(po_wait_r[1]), .I1(po_wait_r[2]), .I2(po_wait_r[3]), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(po_wait_r[0]), .I5(\po_wait_r_reg[3]_0 ), .O(\po_wait_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h5445544554455444)) \po_wait_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\po_wait_r_reg[3]_0 ), .I2(po_wait_r[0]), .I3(po_wait_r[1]), .I4(po_wait_r[2]), .I5(po_wait_r[3]), .O(\po_wait_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h5554444555544444)) \po_wait_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\po_wait_r_reg[3]_0 ), .I2(po_wait_r[0]), .I3(po_wait_r[1]), .I4(po_wait_r[2]), .I5(po_wait_r[3]), .O(\po_wait_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h5555555444444444)) \po_wait_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(\po_wait_r_reg[3]_0 ), .I2(po_wait_r[2]), .I3(po_wait_r[0]), .I4(po_wait_r[1]), .I5(po_wait_r[3]), .O(\po_wait_r[3]_i_1_n_0 )); FDRE \po_wait_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_wait_r[0]_i_1_n_0 ), .Q(po_wait_r[0]), .R(1'b0)); FDRE \po_wait_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_wait_r[1]_i_1_n_0 ), .Q(po_wait_r[1]), .R(1'b0)); FDRE \po_wait_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_wait_r[2]_i_1_n_0 ), .Q(po_wait_r[2]), .R(1'b0)); FDRE \po_wait_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_wait_r[3]_i_1_n_0 ), .Q(po_wait_r[3]), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_po_cntlr (O, ocal_last_byte_done_reg, oclk_center_write_resume, complex_ocal_num_samples_done_r, \sm_r_reg[3]_0 , oclkdelay_center_calib_start_r_reg_0, scanning_right, S, Q, po_stg23_incdec_r_reg, setup_po, \stg2_r_reg[0]_0 , \two_r_reg[1]_0 , E, o2f_r_reg, f2z_r_reg, \stg2_target_r_reg[8]_0 , po_stg23_incdec_r_reg_0, \stg3_init_val_reg[5] , \stg3_init_val_reg[3] , \stg3_init_val_reg[4] , \stg3_init_val_reg[2] , \stg3_init_val_reg[1] , \stg3_init_val_reg[0] , \rise_trail_r_reg[5] , \run_ends_r_reg[1] , \sm_r_reg[0]_0 , D, samp_done_ns8_out, ninety_offsets, use_noise_window, \init_state_r_reg[0] , poc_backup_r_reg_0, edge_aligned_r_reg, \stg3_init_val_reg[4]_0 , \stg3_init_val_reg[2]_0 , rstdiv0_sync_r1_reg_rep__10, CLK, dec_po_ns, inc_po_ns, rstdiv0_sync_r1_reg_rep__9, \wl_po_fine_cnt_reg[14] , \stg3_r_reg[0]_0 , f2o_r_reg, f2o_r_reg_0, rstdiv0_sync_r1_reg_rep__26, lim2stg3_inc, po_stg23_incdec, ocd_cntlr2stg2_dec_r, scanning_right_r_reg_0, scan_right_r_reg, samp_done, rd_active_r2, poc_backup_r_reg_1, done_r_reg, o2f_ns1_out, o2f_r_reg_0, f2z_ns5_out, f2z_r_reg_0, rstdiv0_sync_r1_reg_rep__20, lim2stg3_dec, lim2stg2_dec, \byte_r_reg[0] , \wl_po_fine_cnt_reg[3] , \wl_po_fine_cnt_reg[17] , \wl_po_fine_cnt_reg[18] , \byte_r_reg[0]_0 , \byte_r_reg[1] , oclkdelay_calib_done_r_reg, lim2poc_ktap_right, lim2poc_rdy, po_rdy, lim2stg2_inc, edge_aligned_r_reg_0, \sm_r_reg[0]_1 , reset_scan, rstdiv0_sync_r1_reg_rep__26_0, samp_done_r_reg, rstdiv0_sync_r1_reg_rep__25, wrlvl_final_mux, oclkdelay_int_ref_req_reg, prech_req_posedge_r_reg, oclkdelay_calib_done_r_reg_0, \run_ends_r_reg[1]_0 , \run_ends_r_reg[0] , \po_counter_read_val_reg[5] , \byte_r_reg[0]_1 , \byte_r_reg[1]_0 , \byte_r_reg[0]_2 , \byte_r_reg[0]_3 , \wl_po_fine_cnt_reg[23] ); output [3:0]O; output ocal_last_byte_done_reg; output oclk_center_write_resume; output complex_ocal_num_samples_done_r; output \sm_r_reg[3]_0 ; output oclkdelay_center_calib_start_r_reg_0; output scanning_right; output [0:0]S; output [5:0]Q; output po_stg23_incdec_r_reg; output setup_po; output [0:0]\stg2_r_reg[0]_0 ; output \two_r_reg[1]_0 ; output [0:0]E; output o2f_r_reg; output f2z_r_reg; output [2:0]\stg2_target_r_reg[8]_0 ; output po_stg23_incdec_r_reg_0; output \stg3_init_val_reg[5] ; output [0:0]\stg3_init_val_reg[3] ; output \stg3_init_val_reg[4] ; output \stg3_init_val_reg[2] ; output \stg3_init_val_reg[1] ; output \stg3_init_val_reg[0] ; output \rise_trail_r_reg[5] ; output \run_ends_r_reg[1] ; output \sm_r_reg[0]_0 ; output [5:0]D; output samp_done_ns8_out; output [1:0]ninety_offsets; output use_noise_window; output \init_state_r_reg[0] ; output poc_backup_r_reg_0; output edge_aligned_r_reg; output \stg3_init_val_reg[4]_0 ; output \stg3_init_val_reg[2]_0 ; input rstdiv0_sync_r1_reg_rep__10; input CLK; input dec_po_ns; input inc_po_ns; input rstdiv0_sync_r1_reg_rep__9; input [1:0]\wl_po_fine_cnt_reg[14] ; input \stg3_r_reg[0]_0 ; input f2o_r_reg; input f2o_r_reg_0; input rstdiv0_sync_r1_reg_rep__26; input lim2stg3_inc; input po_stg23_incdec; input ocd_cntlr2stg2_dec_r; input scanning_right_r_reg_0; input scan_right_r_reg; input samp_done; input rd_active_r2; input poc_backup_r_reg_1; input done_r_reg; input o2f_ns1_out; input o2f_r_reg_0; input f2z_ns5_out; input f2z_r_reg_0; input rstdiv0_sync_r1_reg_rep__20; input lim2stg3_dec; input lim2stg2_dec; input \byte_r_reg[0] ; input \wl_po_fine_cnt_reg[3] ; input \wl_po_fine_cnt_reg[17] ; input \wl_po_fine_cnt_reg[18] ; input \byte_r_reg[0]_0 ; input \byte_r_reg[1] ; input oclkdelay_calib_done_r_reg; input lim2poc_ktap_right; input lim2poc_rdy; input po_rdy; input lim2stg2_inc; input edge_aligned_r_reg_0; input \sm_r_reg[0]_1 ; input reset_scan; input rstdiv0_sync_r1_reg_rep__26_0; input samp_done_r_reg; input rstdiv0_sync_r1_reg_rep__25; input wrlvl_final_mux; input oclkdelay_int_ref_req_reg; input prech_req_posedge_r_reg; input oclkdelay_calib_done_r_reg_0; input \run_ends_r_reg[1]_0 ; input \run_ends_r_reg[0] ; input [5:0]\po_counter_read_val_reg[5] ; input \byte_r_reg[0]_1 ; input \byte_r_reg[1]_0 ; input \byte_r_reg[0]_2 ; input \byte_r_reg[0]_3 ; input [7:0]\wl_po_fine_cnt_reg[23] ; wire [8:0]A; wire CLK; wire [5:0]D; wire [0:0]E; wire [3:0]O; wire [5:0]Q; wire [0:0]S; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire \byte_r_reg[0]_1 ; wire \byte_r_reg[0]_2 ; wire \byte_r_reg[0]_3 ; wire \byte_r_reg[1] ; wire \byte_r_reg[1]_0 ; wire cmplx_samples_done_r_i_2_n_0; wire cmplx_samples_done_r_i_3_n_0; wire complex_ocal_num_samples_done_r; wire dec_po_ns; wire dec_po_r; wire done_r_reg; wire edge_aligned_r_reg; wire edge_aligned_r_reg_0; wire f2o_r_reg; wire f2o_r_reg_0; wire f2z_ns5_out; wire f2z_r_reg; wire f2z_r_reg_0; wire inc_po_ns; wire inc_po_r; wire \init_state_r_reg[0] ; wire lim2poc_ktap_right; wire lim2poc_rdy; wire lim2stg2_dec; wire lim2stg2_inc; wire lim2stg3_dec; wire lim2stg3_inc; wire [1:0]ninety_offsets; wire [1:0]ninety_offsets_final_r; wire ninety_offsets_ns; wire \ninety_offsets_r[0]_i_1_n_0 ; wire \ninety_offsets_r[1]_i_1_n_0 ; wire \ninety_offsets_r[1]_i_3_n_0 ; wire \ninety_offsets_r[1]_i_4_n_0 ; wire o2f_ns1_out; wire o2f_r_reg; wire o2f_r_reg_0; wire ocal_last_byte_done_reg; wire ocd2stg3_dec; wire ocd_cntlr2stg2_dec_r; wire ocd_edge_detect_rdy; wire ocd_edge_detect_rdy_r_i_1_n_0; wire ocd_ktap_left_r_i_2_n_0; wire ocd_ktap_left_r_i_3_n_0; wire ocd_ktap_left_r_i_4_n_0; wire ocd_ktap_right; wire ocd_ktap_right_r_i_1_n_0; wire oclk_calib_resume_r_i_5_n_0; wire oclk_center_write_resume; wire oclk_center_write_resume_r_i_2_n_0; wire oclk_center_write_resume_r_i_3_n_0; wire oclk_center_write_resume_r_i_4_n_0; wire oclk_center_write_resume_r_i_5_n_0; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_center_calib_done_r_i_1_n_0; wire oclkdelay_center_calib_done_r_i_2_n_0; wire oclkdelay_center_calib_done_r_i_3_n_0; wire oclkdelay_center_calib_done_r_i_4_n_0; wire oclkdelay_center_calib_start_r_i_1_n_0; wire oclkdelay_center_calib_start_r_reg_0; wire oclkdelay_int_ref_req_reg; wire [8:1]out; wire [5:0]p_0_in; wire p_0_in0_carry__0_i_1_n_0; wire p_0_in0_carry__0_i_2_n_0; wire p_0_in0_carry__0_i_3_n_0; wire p_0_in0_carry__0_i_4_n_0; wire p_0_in0_carry__0_n_2; wire p_0_in0_carry__0_n_3; wire p_0_in0_carry__0_n_5; wire p_0_in0_carry__0_n_6; wire p_0_in0_carry__0_n_7; wire p_0_in0_carry_i_10_n_0; wire p_0_in0_carry_i_10_n_1; wire p_0_in0_carry_i_10_n_2; wire p_0_in0_carry_i_10_n_3; wire p_0_in0_carry_i_10_n_4; wire p_0_in0_carry_i_10_n_5; wire p_0_in0_carry_i_10_n_6; wire p_0_in0_carry_i_11_n_3; wire p_0_in0_carry_i_11_n_6; wire p_0_in0_carry_i_11_n_7; wire p_0_in0_carry_i_12_n_3; wire p_0_in0_carry_i_13_n_0; wire p_0_in0_carry_i_14_n_0; wire p_0_in0_carry_i_15_n_0; wire p_0_in0_carry_i_16_n_0; wire p_0_in0_carry_i_17_n_0; wire p_0_in0_carry_i_18_n_0; wire p_0_in0_carry_i_19_n_0; wire p_0_in0_carry_i_1_n_0; wire p_0_in0_carry_i_20_n_0; wire p_0_in0_carry_i_21_n_0; wire p_0_in0_carry_i_22_n_0; wire p_0_in0_carry_i_23_n_0; wire p_0_in0_carry_i_24_n_0; wire p_0_in0_carry_i_2_n_0; wire p_0_in0_carry_i_3_n_0; wire p_0_in0_carry_i_4_n_0; wire p_0_in0_carry_i_5_n_0; wire p_0_in0_carry_i_6_n_0; wire p_0_in0_carry_i_7_n_0; wire p_0_in0_carry_i_8_n_0; wire p_0_in0_carry_i_8_n_1; wire p_0_in0_carry_i_8_n_2; wire p_0_in0_carry_i_8_n_3; wire p_0_in0_carry_i_9_n_0; wire p_0_in0_carry_n_0; wire p_0_in0_carry_n_1; wire p_0_in0_carry_n_2; wire p_0_in0_carry_n_3; wire p_1_in; wire p_55_in; wire p_58_in; wire p_63_in; wire [5:0]po_counter_read_val_r; wire [5:0]\po_counter_read_val_reg[5] ; wire po_done_ns; wire po_done_r; wire po_done_r_i_1_n_0; wire po_rdy; wire po_rdy_r_i_5_n_0; wire po_rdy_r_i_6_n_0; wire po_rdy_r_i_7_n_0; wire po_stg23_incdec; wire po_stg23_incdec_r_i_10_n_0; wire po_stg23_incdec_r_i_2_n_0; wire po_stg23_incdec_r_i_3_n_0; wire po_stg23_incdec_r_i_4_n_0; wire po_stg23_incdec_r_i_5_n_0; wire po_stg23_incdec_r_i_6_n_0; wire po_stg23_incdec_r_i_7_n_0; wire po_stg23_incdec_r_i_8_n_0; wire po_stg23_incdec_r_i_9_n_0; wire po_stg23_incdec_r_reg; wire po_stg23_incdec_r_reg_0; wire poc_backup_r; wire poc_backup_r_i_1__0_n_0; wire poc_backup_r_i_2__0_n_0; wire poc_backup_r_i_3_n_0; wire poc_backup_r_i_4_n_0; wire poc_backup_r_i_5_n_0; wire poc_backup_r_reg_0; wire poc_backup_r_reg_1; wire prech_req_posedge_r_reg; wire rd_active_r2; wire reset_scan; wire [9:5]resume_wait_ns0; wire [10:0]resume_wait_r; wire \resume_wait_r[0]_i_1_n_0 ; wire \resume_wait_r[10]_i_1_n_0 ; wire \resume_wait_r[10]_i_2_n_0 ; wire \resume_wait_r[10]_i_3_n_0 ; wire \resume_wait_r[10]_i_4_n_0 ; wire \resume_wait_r[1]_i_1_n_0 ; wire \resume_wait_r[2]_i_1_n_0 ; wire \resume_wait_r[2]_i_2_n_0 ; wire \resume_wait_r[3]_i_1_n_0 ; wire \resume_wait_r[4]_i_1_n_0 ; wire \resume_wait_r[4]_i_2_n_0 ; wire \resume_wait_r[7]_i_2_n_0 ; wire \resume_wait_r[9]_i_1_n_0 ; wire \resume_wait_r[9]_i_4_n_0 ; wire \resume_wait_r[9]_i_5_n_0 ; wire \resume_wait_r[9]_i_6_n_0 ; wire \resume_wait_r[9]_i_7_n_0 ; wire \resume_wait_r[9]_i_8_n_0 ; wire \rise_trail_r_reg[5] ; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__9; wire \run_ends_r_reg[0] ; wire \run_ends_r_reg[1] ; wire \run_ends_r_reg[1]_0 ; wire samp_done; wire samp_done_ns8_out; wire samp_done_r_reg; wire scan_right_r_reg; wire scanning_right; wire scanning_right_r_i_1_n_0; wire scanning_right_r_i_3_n_0; wire scanning_right_r_reg_0; wire setup_po; wire \simp_stg3_final_r_reg_n_0_[0] ; wire \simp_stg3_final_r_reg_n_0_[10] ; wire \simp_stg3_final_r_reg_n_0_[11] ; wire \simp_stg3_final_r_reg_n_0_[12] ; wire \simp_stg3_final_r_reg_n_0_[13] ; wire \simp_stg3_final_r_reg_n_0_[14] ; wire \simp_stg3_final_r_reg_n_0_[15] ; wire \simp_stg3_final_r_reg_n_0_[17] ; wire \simp_stg3_final_r_reg_n_0_[18] ; wire \simp_stg3_final_r_reg_n_0_[19] ; wire \simp_stg3_final_r_reg_n_0_[1] ; wire \simp_stg3_final_r_reg_n_0_[20] ; wire \simp_stg3_final_r_reg_n_0_[21] ; wire \simp_stg3_final_r_reg_n_0_[22] ; wire \simp_stg3_final_r_reg_n_0_[23] ; wire \simp_stg3_final_r_reg_n_0_[3] ; wire \simp_stg3_final_r_reg_n_0_[4] ; wire \simp_stg3_final_r_reg_n_0_[5] ; wire \simp_stg3_final_r_reg_n_0_[6] ; wire \simp_stg3_final_r_reg_n_0_[7] ; wire \simp_stg3_final_r_reg_n_0_[8] ; wire \simp_stg3_final_r_reg_n_0_[9] ; wire sm_ns; wire [3:0]sm_r; wire \sm_r[0]_i_1_n_0 ; wire \sm_r[0]_i_2__0_n_0 ; wire \sm_r[0]_i_3_n_0 ; wire \sm_r[1]_i_1_n_0 ; wire \sm_r[1]_i_2_n_0 ; wire \sm_r[2]_i_1_n_0 ; wire \sm_r[2]_i_2_n_0 ; wire \sm_r[3]_i_10_n_0 ; wire \sm_r[3]_i_2_n_0 ; wire \sm_r[3]_i_3_n_0 ; wire \sm_r[3]_i_4_n_0 ; wire \sm_r[3]_i_6_n_0 ; wire \sm_r[3]_i_7_n_0 ; wire \sm_r[3]_i_8_n_0 ; wire \sm_r[3]_i_9_n_0 ; wire \sm_r_reg[0]_0 ; wire \sm_r_reg[0]_1 ; wire \sm_r_reg[3]_0 ; wire [5:0]stg2_final_r; wire \stg2_final_r[0]_i_1_n_0 ; wire \stg2_final_r[1]_i_1_n_0 ; wire \stg2_final_r[2]_i_1_n_0 ; wire \stg2_final_r[3]_i_1_n_0 ; wire \stg2_final_r[4]_i_1_n_0 ; wire \stg2_final_r[5]_i_1_n_0 ; wire [8:0]stg2_ns; wire stg2_ns0_carry__0_i_1_n_0; wire stg2_ns0_carry__0_i_2_n_0; wire stg2_ns0_carry__0_i_3_n_0; wire stg2_ns0_carry__0_i_4_n_0; wire stg2_ns0_carry__0_n_1; wire stg2_ns0_carry__0_n_2; wire stg2_ns0_carry__0_n_3; wire stg2_ns0_carry_i_1_n_0; wire stg2_ns0_carry_i_2_n_0; wire stg2_ns0_carry_i_3_n_0; wire stg2_ns0_carry_i_4_n_0; wire stg2_ns0_carry_n_0; wire stg2_ns0_carry_n_1; wire stg2_ns0_carry_n_2; wire stg2_ns0_carry_n_3; wire \stg2_r[8]_i_1_n_0 ; wire \stg2_r[8]_i_3_n_0 ; wire [0:0]\stg2_r_reg[0]_0 ; wire [1:1]stg2_target_ns; wire [2:0]\stg2_target_r_reg[8]_0 ; wire \stg2_target_r_reg_n_0_[0] ; wire \stg2_target_r_reg_n_0_[1] ; wire \stg2_target_r_reg_n_0_[2] ; wire \stg2_target_r_reg_n_0_[3] ; wire \stg2_target_r_reg_n_0_[4] ; wire \stg2_target_r_reg_n_0_[5] ; wire \stg2_target_r_reg_n_0_[6] ; wire \stg2_target_r_reg_n_0_[7] ; wire \stg3_init_val[3]_i_2_n_0 ; wire \stg3_init_val_reg[0] ; wire \stg3_init_val_reg[1] ; wire \stg3_init_val_reg[2] ; wire \stg3_init_val_reg[2]_0 ; wire [0:0]\stg3_init_val_reg[3] ; wire \stg3_init_val_reg[4] ; wire \stg3_init_val_reg[4]_0 ; wire \stg3_init_val_reg[5] ; wire [5:0]stg3_ns; wire \stg3_r[5]_i_10_n_0 ; wire \stg3_r[5]_i_11_n_0 ; wire \stg3_r[5]_i_12_n_0 ; wire \stg3_r[5]_i_1_n_0 ; wire \stg3_r[5]_i_4_n_0 ; wire \stg3_r[5]_i_5_n_0 ; wire \stg3_r[5]_i_6_n_0 ; wire \stg3_r[5]_i_7_n_0 ; wire \stg3_r[5]_i_9_n_0 ; wire \stg3_r_reg[0]_0 ; wire [1:0]two_r; wire \two_r[0]_i_1_n_0 ; wire \two_r[1]_i_1_n_0 ; wire \two_r[1]_i_2_n_0 ; wire \two_r_reg[1]_0 ; wire up_r; wire up_r_i_1_n_0; wire use_noise_window; wire [1:0]\wl_po_fine_cnt_reg[14] ; wire \wl_po_fine_cnt_reg[17] ; wire \wl_po_fine_cnt_reg[18] ; wire [7:0]\wl_po_fine_cnt_reg[23] ; wire \wl_po_fine_cnt_reg[3] ; wire wrlvl_final_mux; wire [3:2]NLW_p_0_in0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_p_0_in0_carry__0_O_UNCONNECTED; wire [3:1]NLW_p_0_in0_carry_i_11_CO_UNCONNECTED; wire [3:2]NLW_p_0_in0_carry_i_11_O_UNCONNECTED; wire [3:1]NLW_p_0_in0_carry_i_12_CO_UNCONNECTED; wire [3:2]NLW_p_0_in0_carry_i_12_O_UNCONNECTED; wire [0:0]NLW_p_0_in0_carry_i_8_O_UNCONNECTED; wire [3:3]NLW_stg2_ns0_carry__0_CO_UNCONNECTED; LUT3 #( .INIT(8'h04)) cmplx_samples_done_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(complex_ocal_num_samples_done_r), .I2(cmplx_samples_done_r_i_2_n_0), .O(p_58_in)); LUT5 #( .INIT(32'h0008AAAA)) cmplx_samples_done_r_i_2 (.I0(oclk_calib_resume_r_i_5_n_0), .I1(cmplx_samples_done_r_i_3_n_0), .I2(inc_po_r), .I3(dec_po_r), .I4(sm_r[0]), .O(cmplx_samples_done_r_i_2_n_0)); LUT3 #( .INIT(8'h08)) cmplx_samples_done_r_i_3 (.I0(po_done_r), .I1(\stg2_r_reg[0]_0 ), .I2(E), .O(cmplx_samples_done_r_i_3_n_0)); FDRE cmplx_samples_done_r_reg (.C(CLK), .CE(1'b1), .D(p_58_in), .Q(complex_ocal_num_samples_done_r), .R(1'b0)); FDRE dec_po_r_reg (.C(CLK), .CE(1'b1), .D(dec_po_ns), .Q(dec_po_r), .R(1'b0)); LUT2 #( .INIT(4'hE)) done_r_i_2__0 (.I0(ocd_edge_detect_rdy), .I1(lim2poc_rdy), .O(\run_ends_r_reg[1] )); LUT2 #( .INIT(4'hE)) edge_aligned_r_i_4 (.I0(\sm_r_reg[3]_0 ), .I1(\rise_trail_r_reg[5] ), .O(edge_aligned_r_reg)); (* SOFT_HLUTNM = "soft_lutpair421" *) LUT3 #( .INIT(8'hB8)) f2z_r_i_1 (.I0(scanning_right), .I1(f2z_ns5_out), .I2(f2z_r_reg_0), .O(f2z_r_reg)); LUT2 #( .INIT(4'h2)) i___15_i_1__0 (.I0(ninety_offsets[0]), .I1(ninety_offsets[1]), .O(use_noise_window)); (* SOFT_HLUTNM = "soft_lutpair416" *) LUT2 #( .INIT(4'hE)) i___7_i_2 (.I0(ocd_ktap_right), .I1(lim2poc_ktap_right), .O(\rise_trail_r_reg[5] )); FDRE inc_po_r_reg (.C(CLK), .CE(1'b1), .D(inc_po_ns), .Q(inc_po_r), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFFFE)) \init_state_r[5]_i_55 (.I0(oclkdelay_center_calib_start_r_reg_0), .I1(wrlvl_final_mux), .I2(oclkdelay_int_ref_req_reg), .I3(prech_req_posedge_r_reg), .I4(oclkdelay_calib_done_r_reg_0), .O(\init_state_r_reg[0] )); FDRE \ninety_offsets_final_r_reg[0] (.C(CLK), .CE(1'b1), .D(f2o_r_reg_0), .Q(ninety_offsets_final_r[0]), .R(1'b0)); FDRE \ninety_offsets_final_r_reg[1] (.C(CLK), .CE(1'b1), .D(f2o_r_reg), .Q(ninety_offsets_final_r[1]), .R(1'b0)); LUT5 #( .INIT(32'hE0FFEF00)) \ninety_offsets_r[0]_i_1 (.I0(ninety_offsets_final_r[1]), .I1(ninety_offsets_final_r[0]), .I2(sm_r[0]), .I3(ninety_offsets_ns), .I4(ninety_offsets[0]), .O(\ninety_offsets_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair409" *) LUT4 #( .INIT(16'h4F80)) \ninety_offsets_r[1]_i_1 (.I0(ninety_offsets[0]), .I1(sm_r[2]), .I2(ninety_offsets_ns), .I3(ninety_offsets[1]), .O(\ninety_offsets_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00000040)) \ninety_offsets_r[1]_i_2 (.I0(sm_r[2]), .I1(sm_r[0]), .I2(\stg2_r_reg[0]_0 ), .I3(sm_r[3]), .I4(rstdiv0_sync_r1_reg_rep__26), .I5(\ninety_offsets_r[1]_i_3_n_0 ), .O(ninety_offsets_ns)); LUT6 #( .INIT(64'h0000000001000000)) \ninety_offsets_r[1]_i_3 (.I0(sm_r[3]), .I1(rstdiv0_sync_r1_reg_rep__26), .I2(\ninety_offsets_r[1]_i_4_n_0 ), .I3(oclk_center_write_resume_r_i_5_n_0), .I4(done_r_reg), .I5(E), .O(\ninety_offsets_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair404" *) LUT5 #( .INIT(32'hFFFFFFFB)) \ninety_offsets_r[1]_i_4 (.I0(\stg2_r_reg[0]_0 ), .I1(sm_r[2]), .I2(sm_r[0]), .I3(\sm_r_reg[3]_0 ), .I4(ocd_ktap_right), .O(\ninety_offsets_r[1]_i_4_n_0 )); FDRE \ninety_offsets_r_reg[0] (.C(CLK), .CE(1'b1), .D(\ninety_offsets_r[0]_i_1_n_0 ), .Q(ninety_offsets[0]), .R(1'b0)); FDRE \ninety_offsets_r_reg[1] (.C(CLK), .CE(1'b1), .D(\ninety_offsets_r[1]_i_1_n_0 ), .Q(ninety_offsets[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair421" *) LUT3 #( .INIT(8'hB8)) o2f_r_i_1 (.I0(scanning_right), .I1(o2f_ns1_out), .I2(o2f_r_reg_0), .O(o2f_r_reg)); (* SOFT_HLUTNM = "soft_lutpair406" *) LUT5 #( .INIT(32'hFDFF0100)) ocd_edge_detect_rdy_r_i_1 (.I0(done_r_reg), .I1(E), .I2(sm_r[3]), .I3(\sm_r[3]_i_6_n_0 ), .I4(ocd_edge_detect_rdy), .O(ocd_edge_detect_rdy_r_i_1_n_0)); FDRE ocd_edge_detect_rdy_r_reg (.C(CLK), .CE(1'b1), .D(ocd_edge_detect_rdy_r_i_1_n_0), .Q(ocd_edge_detect_rdy), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'h00000000EEEEEEE0)) ocd_ktap_left_r_i_1 (.I0(ocd_ktap_left_r_i_2_n_0), .I1(\sm_r_reg[3]_0 ), .I2(sm_r[0]), .I3(\stg2_r_reg[0]_0 ), .I4(ocd_ktap_left_r_i_3_n_0), .I5(rstdiv0_sync_r1_reg_rep__20), .O(p_55_in)); LUT6 #( .INIT(64'h2000000000000000)) ocd_ktap_left_r_i_2 (.I0(scanning_right_r_reg_0), .I1(\stg2_r_reg[0]_0 ), .I2(rd_active_r2), .I3(samp_done), .I4(sm_r[0]), .I5(ocd_ktap_left_r_i_4_n_0), .O(ocd_ktap_left_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair411" *) LUT4 #( .INIT(16'hFFDF)) ocd_ktap_left_r_i_3 (.I0(sm_r[2]), .I1(sm_r[3]), .I2(done_r_reg), .I3(E), .O(ocd_ktap_left_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair409" *) LUT2 #( .INIT(4'h1)) ocd_ktap_left_r_i_4 (.I0(sm_r[3]), .I1(sm_r[2]), .O(ocd_ktap_left_r_i_4_n_0)); FDRE ocd_ktap_left_r_reg (.C(CLK), .CE(1'b1), .D(p_55_in), .Q(\sm_r_reg[3]_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFFF0200FDFF0000)) ocd_ktap_right_r_i_1 (.I0(\sm_r[3]_i_6_n_0 ), .I1(sm_r[3]), .I2(E), .I3(done_r_reg), .I4(ocd_ktap_right), .I5(\sm_r_reg[3]_0 ), .O(ocd_ktap_right_r_i_1_n_0)); FDRE ocd_ktap_right_r_reg (.C(CLK), .CE(1'b1), .D(ocd_ktap_right_r_i_1_n_0), .Q(ocd_ktap_right), .R(rstdiv0_sync_r1_reg_rep__9)); LUT4 #( .INIT(16'h0002)) oclk_calib_resume_r_i_2 (.I0(oclk_calib_resume_r_i_5_n_0), .I1(rstdiv0_sync_r1_reg_rep__26), .I2(\sm_r_reg[0]_1 ), .I3(sm_r[0]), .O(samp_done_ns8_out)); LUT6 #( .INIT(64'h00000000000000A3)) oclk_calib_resume_r_i_5 (.I0(po_done_r), .I1(reset_scan), .I2(\stg2_r_reg[0]_0 ), .I3(sm_r[3]), .I4(sm_r[2]), .I5(E), .O(oclk_calib_resume_r_i_5_n_0)); LUT6 #( .INIT(64'hFFFF008000000000)) oclk_center_write_resume_r_i_1 (.I0(oclk_center_write_resume_r_i_2_n_0), .I1(\stg2_r_reg[0]_0 ), .I2(po_done_r), .I3(sm_r[3]), .I4(oclk_center_write_resume), .I5(oclk_center_write_resume_r_i_3_n_0), .O(p_63_in)); LUT4 #( .INIT(16'hAAAB)) oclk_center_write_resume_r_i_2 (.I0(sm_r[2]), .I1(dec_po_r), .I2(inc_po_r), .I3(E), .O(oclk_center_write_resume_r_i_2_n_0)); LUT5 #( .INIT(32'h55554044)) oclk_center_write_resume_r_i_3 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(oclk_center_write_resume), .I2(ocd_ktap_left_r_i_3_n_0), .I3(oclk_center_write_resume_r_i_4_n_0), .I4(sm_r[0]), .O(oclk_center_write_resume_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair407" *) LUT4 #( .INIT(16'h00F1)) oclk_center_write_resume_r_i_4 (.I0(ocd_ktap_right), .I1(oclk_center_write_resume_r_i_5_n_0), .I2(\sm_r_reg[3]_0 ), .I3(\stg2_r_reg[0]_0 ), .O(oclk_center_write_resume_r_i_4_n_0)); LUT6 #( .INIT(64'h0880888888880880)) oclk_center_write_resume_r_i_5 (.I0(edge_aligned_r_reg_0), .I1(ocd_edge_detect_rdy), .I2(ninety_offsets[0]), .I3(ninety_offsets_final_r[0]), .I4(ninety_offsets[1]), .I5(ninety_offsets_final_r[1]), .O(oclk_center_write_resume_r_i_5_n_0)); FDRE oclk_center_write_resume_r_reg (.C(CLK), .CE(1'b1), .D(p_63_in), .Q(oclk_center_write_resume), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000002)) oclkdelay_center_calib_done_r_i_1 (.I0(oclkdelay_center_calib_done_r_i_2_n_0), .I1(resume_wait_r[3]), .I2(resume_wait_r[4]), .I3(resume_wait_r[5]), .I4(oclkdelay_center_calib_done_r_i_3_n_0), .I5(oclkdelay_center_calib_done_r_i_4_n_0), .O(oclkdelay_center_calib_done_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair405" *) LUT5 #( .INIT(32'h00000004)) oclkdelay_center_calib_done_r_i_2 (.I0(resume_wait_r[1]), .I1(resume_wait_r[0]), .I2(resume_wait_r[2]), .I3(poc_backup_r), .I4(resume_wait_r[10]), .O(oclkdelay_center_calib_done_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair408" *) LUT4 #( .INIT(16'hFFEF)) oclkdelay_center_calib_done_r_i_3 (.I0(sm_r[2]), .I1(\stg2_r_reg[0]_0 ), .I2(sm_r[3]), .I3(sm_r[0]), .O(oclkdelay_center_calib_done_r_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair401" *) LUT4 #( .INIT(16'hFFFE)) oclkdelay_center_calib_done_r_i_4 (.I0(resume_wait_r[8]), .I1(resume_wait_r[7]), .I2(resume_wait_r[9]), .I3(resume_wait_r[6]), .O(oclkdelay_center_calib_done_r_i_4_n_0)); FDRE oclkdelay_center_calib_done_r_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_center_calib_done_r_i_1_n_0), .Q(ocal_last_byte_done_reg), .R(rstdiv0_sync_r1_reg_rep__10)); LUT6 #( .INIT(64'hEE44EFFFEE44E000)) oclkdelay_center_calib_start_r_i_1 (.I0(sm_r[0]), .I1(poc_backup_r), .I2(\sm_r[3]_i_3_n_0 ), .I3(scanning_right_r_reg_0), .I4(oclkdelay_center_calib_done_r_i_1_n_0), .I5(oclkdelay_center_calib_start_r_reg_0), .O(oclkdelay_center_calib_start_r_i_1_n_0)); FDRE oclkdelay_center_calib_start_r_reg (.C(CLK), .CE(1'b1), .D(oclkdelay_center_calib_start_r_i_1_n_0), .Q(oclkdelay_center_calib_start_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__9)); CARRY4 p_0_in0_carry (.CI(1'b0), .CO({p_0_in0_carry_n_0,p_0_in0_carry_n_1,p_0_in0_carry_n_2,p_0_in0_carry_n_3}), .CYINIT(1'b0), .DI({p_0_in0_carry_i_1_n_0,p_0_in0_carry_i_2_n_0,p_0_in0_carry_i_3_n_0,1'b0}), .O(O), .S({p_0_in0_carry_i_4_n_0,p_0_in0_carry_i_5_n_0,p_0_in0_carry_i_6_n_0,p_0_in0_carry_i_7_n_0})); CARRY4 p_0_in0_carry__0 (.CI(p_0_in0_carry_n_0), .CO({NLW_p_0_in0_carry__0_CO_UNCONNECTED[3:2],p_0_in0_carry__0_n_2,p_0_in0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,p_0_in0_carry__0_i_1_n_0,p_0_in0_carry__0_i_2_n_0}), .O({NLW_p_0_in0_carry__0_O_UNCONNECTED[3],p_0_in0_carry__0_n_5,p_0_in0_carry__0_n_6,p_0_in0_carry__0_n_7}), .S({1'b0,1'b1,p_0_in0_carry__0_i_3_n_0,p_0_in0_carry__0_i_4_n_0})); LUT2 #( .INIT(4'hB)) p_0_in0_carry__0_i_1 (.I0(p_0_in0_carry_i_9_n_0), .I1(p_0_in[5]), .O(p_0_in0_carry__0_i_1_n_0)); LUT4 #( .INIT(16'hF404)) p_0_in0_carry__0_i_2 (.I0(p_0_in[3]), .I1(p_0_in[4]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_11_n_7), .O(p_0_in0_carry__0_i_2_n_0)); LUT4 #( .INIT(16'h553F)) p_0_in0_carry__0_i_3 (.I0(p_0_in0_carry_i_11_n_6), .I1(p_0_in[4]), .I2(p_0_in[5]), .I3(p_0_in0_carry_i_9_n_0), .O(p_0_in0_carry__0_i_3_n_0)); LUT6 #( .INIT(64'hAAC355C3AA0F550F)) p_0_in0_carry__0_i_4 (.I0(p_0_in0_carry_i_11_n_7), .I1(p_0_in[3]), .I2(p_0_in[5]), .I3(p_0_in0_carry_i_9_n_0), .I4(p_0_in0_carry_i_11_n_6), .I5(p_0_in[4]), .O(p_0_in0_carry__0_i_4_n_0)); LUT4 #( .INIT(16'hF404)) p_0_in0_carry_i_1 (.I0(p_0_in[2]), .I1(p_0_in[3]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_10_n_4), .O(p_0_in0_carry_i_1_n_0)); CARRY4 p_0_in0_carry_i_10 (.CI(1'b0), .CO({p_0_in0_carry_i_10_n_0,p_0_in0_carry_i_10_n_1,p_0_in0_carry_i_10_n_2,p_0_in0_carry_i_10_n_3}), .CYINIT(1'b1), .DI({1'b1,1'b1,1'b0,1'b0}), .O({p_0_in0_carry_i_10_n_4,p_0_in0_carry_i_10_n_5,p_0_in0_carry_i_10_n_6,p_0_in[0]}), .S({p_0_in0_carry_i_17_n_0,p_0_in0_carry_i_18_n_0,p_0_in0_carry_i_19_n_0,p_0_in0_carry_i_20_n_0})); CARRY4 p_0_in0_carry_i_11 (.CI(p_0_in0_carry_i_10_n_0), .CO({NLW_p_0_in0_carry_i_11_CO_UNCONNECTED[3:1],p_0_in0_carry_i_11_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({NLW_p_0_in0_carry_i_11_O_UNCONNECTED[3:2],p_0_in0_carry_i_11_n_6,p_0_in0_carry_i_11_n_7}), .S({1'b0,1'b0,p_0_in0_carry_i_21_n_0,p_0_in0_carry_i_22_n_0})); CARRY4 p_0_in0_carry_i_12 (.CI(p_0_in0_carry_i_8_n_0), .CO({NLW_p_0_in0_carry_i_12_CO_UNCONNECTED[3:1],p_0_in0_carry_i_12_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,Q[4]}), .O({NLW_p_0_in0_carry_i_12_O_UNCONNECTED[3:2],p_0_in[5:4]}), .S({1'b0,1'b0,p_0_in0_carry_i_23_n_0,p_0_in0_carry_i_24_n_0})); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_13 (.I0(Q[3]), .O(p_0_in0_carry_i_13_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_14 (.I0(Q[2]), .O(p_0_in0_carry_i_14_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_15 (.I0(Q[1]), .O(p_0_in0_carry_i_15_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_16 (.I0(Q[0]), .O(p_0_in0_carry_i_16_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_17 (.I0(Q[3]), .O(p_0_in0_carry_i_17_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_18 (.I0(Q[2]), .O(p_0_in0_carry_i_18_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_19 (.I0(Q[1]), .O(p_0_in0_carry_i_19_n_0)); LUT4 #( .INIT(16'hF404)) p_0_in0_carry_i_2 (.I0(p_0_in[1]), .I1(p_0_in[2]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_10_n_5), .O(p_0_in0_carry_i_2_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_20 (.I0(Q[0]), .O(p_0_in0_carry_i_20_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_21 (.I0(Q[5]), .O(p_0_in0_carry_i_21_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_22 (.I0(Q[4]), .O(p_0_in0_carry_i_22_n_0)); LUT1 #( .INIT(2'h1)) p_0_in0_carry_i_23 (.I0(Q[5]), .O(p_0_in0_carry_i_23_n_0)); LUT1 #( .INIT(2'h2)) p_0_in0_carry_i_24 (.I0(Q[4]), .O(p_0_in0_carry_i_24_n_0)); LUT3 #( .INIT(8'hEF)) p_0_in0_carry_i_3 (.I0(p_0_in[1]), .I1(p_0_in0_carry_i_9_n_0), .I2(p_0_in[0]), .O(p_0_in0_carry_i_3_n_0)); LUT6 #( .INIT(64'hA5CCA533A500A5FF)) p_0_in0_carry_i_4 (.I0(p_0_in0_carry_i_10_n_4), .I1(p_0_in[2]), .I2(p_0_in0_carry_i_11_n_7), .I3(p_0_in0_carry_i_9_n_0), .I4(p_0_in[4]), .I5(p_0_in[3]), .O(p_0_in0_carry_i_4_n_0)); LUT6 #( .INIT(64'hAA55C3C3AA550F0F)) p_0_in0_carry_i_5 (.I0(p_0_in0_carry_i_10_n_5), .I1(p_0_in[1]), .I2(p_0_in[3]), .I3(p_0_in0_carry_i_10_n_4), .I4(p_0_in0_carry_i_9_n_0), .I5(p_0_in[2]), .O(p_0_in0_carry_i_5_n_0)); LUT5 #( .INIT(32'hF033F066)) p_0_in0_carry_i_6 (.I0(p_0_in[0]), .I1(p_0_in[2]), .I2(p_0_in0_carry_i_10_n_5), .I3(p_0_in0_carry_i_9_n_0), .I4(p_0_in[1]), .O(p_0_in0_carry_i_6_n_0)); LUT4 #( .INIT(16'hF606)) p_0_in0_carry_i_7 (.I0(p_0_in[0]), .I1(p_0_in[1]), .I2(p_0_in0_carry_i_9_n_0), .I3(p_0_in0_carry_i_10_n_6), .O(p_0_in0_carry_i_7_n_0)); CARRY4 p_0_in0_carry_i_8 (.CI(1'b0), .CO({p_0_in0_carry_i_8_n_0,p_0_in0_carry_i_8_n_1,p_0_in0_carry_i_8_n_2,p_0_in0_carry_i_8_n_3}), .CYINIT(1'b1), .DI(Q[3:0]), .O({p_0_in[3:1],NLW_p_0_in0_carry_i_8_O_UNCONNECTED[0]}), .S({p_0_in0_carry_i_13_n_0,p_0_in0_carry_i_14_n_0,p_0_in0_carry_i_15_n_0,p_0_in0_carry_i_16_n_0})); LUT6 #( .INIT(64'h0155555555555555)) p_0_in0_carry_i_9 (.I0(Q[5]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[3]), .O(p_0_in0_carry_i_9_n_0)); FDRE \po_counter_read_val_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [0]), .Q(po_counter_read_val_r[0]), .R(1'b0)); FDRE \po_counter_read_val_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [1]), .Q(po_counter_read_val_r[1]), .R(1'b0)); FDRE \po_counter_read_val_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [2]), .Q(po_counter_read_val_r[2]), .R(1'b0)); FDRE \po_counter_read_val_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [3]), .Q(po_counter_read_val_r[3]), .R(1'b0)); FDRE \po_counter_read_val_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [4]), .Q(po_counter_read_val_r[4]), .R(1'b0)); FDRE \po_counter_read_val_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_counter_read_val_reg[5] [5]), .Q(po_counter_read_val_r[5]), .R(1'b0)); LUT3 #( .INIT(8'hDC)) po_done_r_i_1 (.I0(\two_r_reg[1]_0 ), .I1(po_done_ns), .I2(po_done_r), .O(po_done_r_i_1_n_0)); LUT6 #( .INIT(64'hAAAAAAAABAFFAAAA)) po_done_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(two_r[0]), .I2(two_r[1]), .I3(\two_r[1]_i_2_n_0 ), .I4(po_rdy), .I5(po_done_r), .O(po_done_ns)); FDRE po_done_r_reg (.C(CLK), .CE(1'b1), .D(po_done_r_i_1_n_0), .Q(po_done_r), .R(1'b0)); LUT4 #( .INIT(16'hFFFE)) po_rdy_r_i_2 (.I0(po_stg23_incdec_r_reg_0), .I1(lim2stg3_inc), .I2(lim2stg3_dec), .I3(\two_r_reg[1]_0 ), .O(setup_po)); LUT6 #( .INIT(64'hFFFFFFFFEEEFEEEE)) po_rdy_r_i_4 (.I0(po_stg23_incdec_r_i_2_n_0), .I1(lim2stg2_dec), .I2(up_r), .I3(po_rdy_r_i_5_n_0), .I4(po_rdy_r_i_6_n_0), .I5(po_rdy_r_i_7_n_0), .O(po_stg23_incdec_r_reg_0)); LUT6 #( .INIT(64'h0000000000000001)) po_rdy_r_i_5 (.I0(A[2]), .I1(A[5]), .I2(A[4]), .I3(A[0]), .I4(A[3]), .I5(A[1]), .O(po_rdy_r_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair412" *) LUT4 #( .INIT(16'h0002)) po_rdy_r_i_6 (.I0(\stg2_r[8]_i_3_n_0 ), .I1(A[7]), .I2(A[8]), .I3(A[6]), .O(po_rdy_r_i_6_n_0)); LUT6 #( .INIT(64'h4545444544444444)) po_rdy_r_i_7 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(ocd_cntlr2stg2_dec_r), .I2(\sm_r[3]_i_9_n_0 ), .I3(stg2_final_r[5]), .I4(po_counter_read_val_r[5]), .I5(po_stg23_incdec_r_i_4_n_0), .O(po_rdy_r_i_7_n_0)); LUT6 #( .INIT(64'h5455555554555455)) po_stg23_incdec_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(po_stg23_incdec_r_i_2_n_0), .I2(lim2stg3_inc), .I3(\stg3_r[5]_i_6_n_0 ), .I4(setup_po), .I5(po_stg23_incdec), .O(po_stg23_incdec_r_reg)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) po_stg23_incdec_r_i_10 (.I0(A[4]), .I1(A[2]), .I2(A[5]), .I3(A[1]), .I4(A[0]), .I5(A[3]), .O(po_stg23_incdec_r_i_10_n_0)); LUT5 #( .INIT(32'hFFFFFF10)) po_stg23_incdec_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(po_stg23_incdec_r_i_3_n_0), .I2(po_stg23_incdec_r_i_4_n_0), .I3(po_stg23_incdec_r_i_5_n_0), .I4(lim2stg2_inc), .O(po_stg23_incdec_r_i_2_n_0)); LUT6 #( .INIT(64'hD5DD0000D5DDD5DD)) po_stg23_incdec_r_i_3 (.I0(po_stg23_incdec_r_i_6_n_0), .I1(po_stg23_incdec_r_i_7_n_0), .I2(po_stg23_incdec_r_i_8_n_0), .I3(po_stg23_incdec_r_i_9_n_0), .I4(po_counter_read_val_r[5]), .I5(stg2_final_r[5]), .O(po_stg23_incdec_r_i_3_n_0)); LUT4 #( .INIT(16'h0002)) po_stg23_incdec_r_i_4 (.I0(po_rdy), .I1(E), .I2(oclkdelay_center_calib_done_r_i_3_n_0), .I3(poc_backup_r), .O(po_stg23_incdec_r_i_4_n_0)); LUT6 #( .INIT(64'h0100000000000000)) po_stg23_incdec_r_i_5 (.I0(A[6]), .I1(A[8]), .I2(A[7]), .I3(\stg2_r[8]_i_3_n_0 ), .I4(po_stg23_incdec_r_i_10_n_0), .I5(up_r), .O(po_stg23_incdec_r_i_5_n_0)); LUT4 #( .INIT(16'hD0DD)) po_stg23_incdec_r_i_6 (.I0(po_counter_read_val_r[5]), .I1(stg2_final_r[5]), .I2(stg2_final_r[4]), .I3(po_counter_read_val_r[4]), .O(po_stg23_incdec_r_i_6_n_0)); LUT4 #( .INIT(16'hD0DD)) po_stg23_incdec_r_i_7 (.I0(stg2_final_r[3]), .I1(po_counter_read_val_r[3]), .I2(po_counter_read_val_r[4]), .I3(stg2_final_r[4]), .O(po_stg23_incdec_r_i_7_n_0)); LUT6 #( .INIT(64'hB0BBBBBB0000B0BB)) po_stg23_incdec_r_i_8 (.I0(po_counter_read_val_r[2]), .I1(stg2_final_r[2]), .I2(po_counter_read_val_r[0]), .I3(stg2_final_r[0]), .I4(stg2_final_r[1]), .I5(po_counter_read_val_r[1]), .O(po_stg23_incdec_r_i_8_n_0)); LUT4 #( .INIT(16'hD0DD)) po_stg23_incdec_r_i_9 (.I0(po_counter_read_val_r[2]), .I1(stg2_final_r[2]), .I2(stg2_final_r[3]), .I3(po_counter_read_val_r[3]), .O(po_stg23_incdec_r_i_9_n_0)); LUT6 #( .INIT(64'hFFFFEAFF0000EA00)) poc_backup_r_i_1__0 (.I0(poc_backup_r_i_2__0_n_0), .I1(poc_backup_r_reg_1), .I2(sm_r[2]), .I3(poc_backup_r_i_3_n_0), .I4(poc_backup_r_i_4_n_0), .I5(poc_backup_r), .O(poc_backup_r_i_1__0_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFF7F)) poc_backup_r_i_2 (.I0(\run_ends_r_reg[1]_0 ), .I1(\run_ends_r_reg[0] ), .I2(\run_ends_r_reg[1] ), .I3(\sm_r_reg[3]_0 ), .I4(\rise_trail_r_reg[5] ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(poc_backup_r_reg_0)); (* SOFT_HLUTNM = "soft_lutpair406" *) LUT2 #( .INIT(4'h8)) poc_backup_r_i_2__0 (.I0(sm_r[3]), .I1(E), .O(poc_backup_r_i_2__0_n_0)); LUT3 #( .INIT(8'h01)) poc_backup_r_i_3 (.I0(sm_r[0]), .I1(\stg2_r_reg[0]_0 ), .I2(rstdiv0_sync_r1_reg_rep__25), .O(poc_backup_r_i_3_n_0)); LUT6 #( .INIT(64'hFFFFFFF0F700F700)) poc_backup_r_i_4 (.I0(poc_backup_r), .I1(po_rdy), .I2(E), .I3(sm_r[3]), .I4(poc_backup_r_i_5_n_0), .I5(sm_r[2]), .O(poc_backup_r_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair416" *) LUT4 #( .INIT(16'hFFF7)) poc_backup_r_i_5 (.I0(\sm_r[3]_i_7_n_0 ), .I1(done_r_reg), .I2(ocd_ktap_right), .I3(\sm_r_reg[3]_0 ), .O(poc_backup_r_i_5_n_0)); FDRE poc_backup_r_reg (.C(CLK), .CE(1'b1), .D(poc_backup_r_i_1__0_n_0), .Q(poc_backup_r), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF0000FF46)) \resume_wait_r[0]_i_1 (.I0(resume_wait_r[0]), .I1(E), .I2(rstdiv0_sync_r1_reg_rep__26), .I3(\resume_wait_r[9]_i_5_n_0 ), .I4(\resume_wait_r[10]_i_3_n_0 ), .I5(\resume_wait_r[10]_i_4_n_0 ), .O(\resume_wait_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair403" *) LUT5 #( .INIT(32'h0000FF02)) \resume_wait_r[10]_i_1 (.I0(resume_wait_r[10]), .I1(\resume_wait_r[10]_i_2_n_0 ), .I2(\resume_wait_r[9]_i_5_n_0 ), .I3(\resume_wait_r[10]_i_3_n_0 ), .I4(\resume_wait_r[10]_i_4_n_0 ), .O(\resume_wait_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair401" *) LUT5 #( .INIT(32'h00000001)) \resume_wait_r[10]_i_2 (.I0(\resume_wait_r[9]_i_6_n_0 ), .I1(resume_wait_r[6]), .I2(resume_wait_r[9]), .I3(resume_wait_r[7]), .I4(resume_wait_r[8]), .O(\resume_wait_r[10]_i_2_n_0 )); LUT6 #( .INIT(64'h0000008000000000)) \resume_wait_r[10]_i_3 (.I0(oclk_center_write_resume_r_i_2_n_0), .I1(\stg2_r_reg[0]_0 ), .I2(po_done_r), .I3(sm_r[3]), .I4(oclk_center_write_resume), .I5(oclk_center_write_resume_r_i_3_n_0), .O(\resume_wait_r[10]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000022222220)) \resume_wait_r[10]_i_4 (.I0(ocd_ktap_left_r_i_2_n_0), .I1(\sm_r_reg[3]_0 ), .I2(sm_r[0]), .I3(\stg2_r_reg[0]_0 ), .I4(ocd_ktap_left_r_i_3_n_0), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\resume_wait_r[10]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000EECEDDCE)) \resume_wait_r[1]_i_1 (.I0(resume_wait_r[1]), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__26), .I3(E), .I4(resume_wait_r[0]), .I5(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000EECEDDCE)) \resume_wait_r[2]_i_1 (.I0(resume_wait_r[2]), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__26), .I3(E), .I4(\resume_wait_r[2]_i_2_n_0 ), .I5(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[2]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \resume_wait_r[2]_i_2 (.I0(resume_wait_r[0]), .I1(resume_wait_r[1]), .O(\resume_wait_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000DDCEEECE)) \resume_wait_r[3]_i_1 (.I0(resume_wait_r[3]), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__26), .I3(E), .I4(\resume_wait_r[7]_i_2_n_0 ), .I5(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[3]_i_1_n_0 )); LUT4 #( .INIT(16'h00D0)) \resume_wait_r[4]_i_1 (.I0(oclk_center_write_resume), .I1(oclk_center_write_resume_r_i_3_n_0), .I2(\resume_wait_r[4]_i_2_n_0 ), .I3(\resume_wait_r[9]_i_4_n_0 ), .O(\resume_wait_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFD0DFFFFF2020)) \resume_wait_r[4]_i_2 (.I0(\resume_wait_r[7]_i_2_n_0 ), .I1(resume_wait_r[3]), .I2(E), .I3(rstdiv0_sync_r1_reg_rep__26), .I4(\resume_wait_r[9]_i_8_n_0 ), .I5(resume_wait_r[4]), .O(\resume_wait_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \resume_wait_r[5]_i_1 (.I0(resume_wait_r[5]), .I1(resume_wait_r[3]), .I2(resume_wait_r[4]), .I3(resume_wait_r[2]), .I4(resume_wait_r[1]), .I5(resume_wait_r[0]), .O(resume_wait_ns0[5])); (* SOFT_HLUTNM = "soft_lutpair400" *) LUT5 #( .INIT(32'hFEFF0100)) \resume_wait_r[6]_i_1 (.I0(resume_wait_r[3]), .I1(resume_wait_r[4]), .I2(resume_wait_r[5]), .I3(\resume_wait_r[7]_i_2_n_0 ), .I4(resume_wait_r[6]), .O(resume_wait_ns0[6])); LUT6 #( .INIT(64'hFFFFFFFB00000004)) \resume_wait_r[7]_i_1 (.I0(resume_wait_r[6]), .I1(\resume_wait_r[7]_i_2_n_0 ), .I2(resume_wait_r[5]), .I3(resume_wait_r[4]), .I4(resume_wait_r[3]), .I5(resume_wait_r[7]), .O(resume_wait_ns0[7])); (* SOFT_HLUTNM = "soft_lutpair405" *) LUT3 #( .INIT(8'h01)) \resume_wait_r[7]_i_2 (.I0(resume_wait_r[2]), .I1(resume_wait_r[1]), .I2(resume_wait_r[0]), .O(\resume_wait_r[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair415" *) LUT3 #( .INIT(8'hE1)) \resume_wait_r[8]_i_1 (.I0(resume_wait_r[7]), .I1(\resume_wait_r[9]_i_7_n_0 ), .I2(resume_wait_r[8]), .O(resume_wait_ns0[8])); LUT4 #( .INIT(16'hEEFE)) \resume_wait_r[9]_i_1 (.I0(\resume_wait_r[9]_i_4_n_0 ), .I1(\resume_wait_r[9]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__26), .I3(E), .O(\resume_wait_r[9]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \resume_wait_r[9]_i_2 (.I0(resume_wait_r[10]), .I1(resume_wait_r[8]), .I2(resume_wait_r[7]), .I3(resume_wait_r[9]), .I4(resume_wait_r[6]), .I5(\resume_wait_r[9]_i_6_n_0 ), .O(E)); (* SOFT_HLUTNM = "soft_lutpair415" *) LUT4 #( .INIT(16'hAAA9)) \resume_wait_r[9]_i_3 (.I0(resume_wait_r[9]), .I1(\resume_wait_r[9]_i_7_n_0 ), .I2(resume_wait_r[7]), .I3(resume_wait_r[8]), .O(resume_wait_ns0[9])); (* SOFT_HLUTNM = "soft_lutpair403" *) LUT2 #( .INIT(4'hE)) \resume_wait_r[9]_i_4 (.I0(\resume_wait_r[10]_i_4_n_0 ), .I1(\resume_wait_r[10]_i_3_n_0 ), .O(\resume_wait_r[9]_i_4_n_0 )); LUT3 #( .INIT(8'hF2)) \resume_wait_r[9]_i_5 (.I0(oclk_center_write_resume), .I1(oclk_center_write_resume_r_i_3_n_0), .I2(\resume_wait_r[9]_i_8_n_0 ), .O(\resume_wait_r[9]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \resume_wait_r[9]_i_6 (.I0(resume_wait_r[3]), .I1(resume_wait_r[4]), .I2(resume_wait_r[5]), .I3(resume_wait_r[0]), .I4(resume_wait_r[1]), .I5(resume_wait_r[2]), .O(\resume_wait_r[9]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair400" *) LUT5 #( .INIT(32'hFFFFFFFB)) \resume_wait_r[9]_i_7 (.I0(resume_wait_r[6]), .I1(\resume_wait_r[7]_i_2_n_0 ), .I2(resume_wait_r[5]), .I3(resume_wait_r[4]), .I4(resume_wait_r[3]), .O(\resume_wait_r[9]_i_7_n_0 )); LUT2 #( .INIT(4'h2)) \resume_wait_r[9]_i_8 (.I0(poc_backup_r), .I1(\stg3_r[5]_i_6_n_0 ), .O(\resume_wait_r[9]_i_8_n_0 )); FDRE \resume_wait_r_reg[0] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[0]_i_1_n_0 ), .Q(resume_wait_r[0]), .R(1'b0)); FDRE \resume_wait_r_reg[10] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[10]_i_1_n_0 ), .Q(resume_wait_r[10]), .R(1'b0)); FDRE \resume_wait_r_reg[1] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[1]_i_1_n_0 ), .Q(resume_wait_r[1]), .R(1'b0)); FDRE \resume_wait_r_reg[2] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[2]_i_1_n_0 ), .Q(resume_wait_r[2]), .R(1'b0)); FDRE \resume_wait_r_reg[3] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[3]_i_1_n_0 ), .Q(resume_wait_r[3]), .R(1'b0)); FDRE \resume_wait_r_reg[4] (.C(CLK), .CE(1'b1), .D(\resume_wait_r[4]_i_1_n_0 ), .Q(resume_wait_r[4]), .R(1'b0)); FDRE \resume_wait_r_reg[5] (.C(CLK), .CE(E), .D(resume_wait_ns0[5]), .Q(resume_wait_r[5]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE \resume_wait_r_reg[6] (.C(CLK), .CE(E), .D(resume_wait_ns0[6]), .Q(resume_wait_r[6]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE \resume_wait_r_reg[7] (.C(CLK), .CE(E), .D(resume_wait_ns0[7]), .Q(resume_wait_r[7]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE \resume_wait_r_reg[8] (.C(CLK), .CE(E), .D(resume_wait_ns0[8]), .Q(resume_wait_r[8]), .R(\resume_wait_r[9]_i_1_n_0 )); FDRE \resume_wait_r_reg[9] (.C(CLK), .CE(E), .D(resume_wait_ns0[9]), .Q(resume_wait_r[9]), .R(\resume_wait_r[9]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF7F0000004000)) scanning_right_r_i_1 (.I0(scan_right_r_reg), .I1(samp_done), .I2(rd_active_r2), .I3(sm_r[0]), .I4(scanning_right_r_i_3_n_0), .I5(scanning_right), .O(scanning_right_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair398" *) LUT4 #( .INIT(16'hFFFE)) scanning_right_r_i_3 (.I0(sm_r[2]), .I1(\stg2_r_reg[0]_0 ), .I2(sm_r[3]), .I3(rstdiv0_sync_r1_reg_rep__26), .O(scanning_right_r_i_3_n_0)); FDRE scanning_right_r_reg (.C(CLK), .CE(1'b1), .D(scanning_right_r_i_1_n_0), .Q(scanning_right), .R(1'b0)); FDRE \simp_stg3_final_r_reg[0] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[0] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[10] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[4]), .Q(\simp_stg3_final_r_reg_n_0_[10] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[11] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[11] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[12] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[12] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[13] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[13] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[14] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[2]), .Q(\simp_stg3_final_r_reg_n_0_[14] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[15] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[15] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[16] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[4]), .Q(\stg3_init_val_reg[4]_0 ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[17] (.C(CLK), .CE(\byte_r_reg[1]_0 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[17] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[18] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[18] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[19] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[19] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[1] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[1] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[20] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[2]), .Q(\simp_stg3_final_r_reg_n_0_[20] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[21] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[21] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[22] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[4]), .Q(\simp_stg3_final_r_reg_n_0_[22] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[23] (.C(CLK), .CE(\byte_r_reg[0]_1 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[23] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[2] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[2]), .Q(\stg3_init_val_reg[2]_0 ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[3] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[3] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[4] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[4]), .Q(\simp_stg3_final_r_reg_n_0_[4] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[5] (.C(CLK), .CE(\byte_r_reg[0]_3 ), .D(Q[5]), .Q(\simp_stg3_final_r_reg_n_0_[5] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[6] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[0]), .Q(\simp_stg3_final_r_reg_n_0_[6] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[7] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[1]), .Q(\simp_stg3_final_r_reg_n_0_[7] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[8] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[2]), .Q(\simp_stg3_final_r_reg_n_0_[8] ), .R(1'b0)); FDRE \simp_stg3_final_r_reg[9] (.C(CLK), .CE(\byte_r_reg[0]_2 ), .D(Q[3]), .Q(\simp_stg3_final_r_reg_n_0_[9] ), .R(1'b0)); LUT3 #( .INIT(8'hB8)) \sm_r[0]_i_1 (.I0(E), .I1(sm_r[3]), .I2(\sm_r[0]_i_2__0_n_0 ), .O(\sm_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000AAFFF3FFFF)) \sm_r[0]_i_2__0 (.I0(scanning_right_r_reg_0), .I1(\sm_r[0]_i_3_n_0 ), .I2(\sm_r_reg[3]_0 ), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[2]), .I5(sm_r[0]), .O(\sm_r[0]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair407" *) LUT2 #( .INIT(4'h1)) \sm_r[0]_i_3 (.I0(ocd_ktap_right), .I1(oclk_center_write_resume_r_i_5_n_0), .O(\sm_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair411" *) LUT3 #( .INIT(8'hB8)) \sm_r[1]_i_1 (.I0(E), .I1(sm_r[3]), .I2(\sm_r[1]_i_2_n_0 ), .O(\sm_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000EEEF55550000)) \sm_r[1]_i_2 (.I0(\stg2_r_reg[0]_0 ), .I1(\sm_r_reg[3]_0 ), .I2(ocd_ktap_right), .I3(edge_aligned_r_reg_0), .I4(sm_r[0]), .I5(sm_r[2]), .O(\sm_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hBBBBB88888888888)) \sm_r[2]_i_1 (.I0(E), .I1(sm_r[3]), .I2(\stg2_r_reg[0]_0 ), .I3(sm_r[0]), .I4(sm_r[2]), .I5(\sm_r[2]_i_2_n_0 ), .O(\sm_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF0DFFFF)) \sm_r[2]_i_2 (.I0(\sm_r[3]_i_7_n_0 ), .I1(ocd_ktap_right), .I2(\sm_r_reg[3]_0 ), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[2]), .I5(sm_r[0]), .O(\sm_r[2]_i_2_n_0 )); LUT4 #( .INIT(16'hFEFF)) \sm_r[3]_i_1 (.I0(\sm_r[3]_i_3_n_0 ), .I1(\sm_r[3]_i_4_n_0 ), .I2(cmplx_samples_done_r_i_2_n_0), .I3(\sm_r_reg[0]_0 ), .O(sm_ns)); LUT6 #( .INIT(64'h00B0BBBB000000B0)) \sm_r[3]_i_10 (.I0(po_counter_read_val_r[2]), .I1(stg2_final_r[2]), .I2(po_counter_read_val_r[0]), .I3(stg2_final_r[0]), .I4(stg2_final_r[1]), .I5(po_counter_read_val_r[1]), .O(\sm_r[3]_i_10_n_0 )); LUT6 #( .INIT(64'h888B888888888888)) \sm_r[3]_i_2 (.I0(E), .I1(sm_r[3]), .I2(ocd_ktap_right), .I3(\sm_r_reg[3]_0 ), .I4(\sm_r[3]_i_6_n_0 ), .I5(\sm_r[3]_i_7_n_0 ), .O(\sm_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000010000000)) \sm_r[3]_i_3 (.I0(sm_r[3]), .I1(sm_r[2]), .I2(sm_r[0]), .I3(samp_done), .I4(rd_active_r2), .I5(\stg2_r_reg[0]_0 ), .O(\sm_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000F3F203F2)) \sm_r[3]_i_4 (.I0(done_r_reg), .I1(E), .I2(sm_r[0]), .I3(\stg2_r_reg[0]_0 ), .I4(po_done_r), .I5(\sm_r[3]_i_8_n_0 ), .O(\sm_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFF7FFFFFFFF)) \sm_r[3]_i_5 (.I0(\sm_r[3]_i_9_n_0 ), .I1(po_stg23_incdec_r_i_3_n_0), .I2(poc_backup_r), .I3(oclkdelay_center_calib_done_r_i_3_n_0), .I4(E), .I5(po_rdy), .O(\sm_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair404" *) LUT3 #( .INIT(8'h04)) \sm_r[3]_i_6 (.I0(sm_r[0]), .I1(sm_r[2]), .I2(\stg2_r_reg[0]_0 ), .O(\sm_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hA22A22222222A22A)) \sm_r[3]_i_7 (.I0(edge_aligned_r_reg_0), .I1(ocd_edge_detect_rdy), .I2(ninety_offsets[0]), .I3(ninety_offsets_final_r[0]), .I4(ninety_offsets[1]), .I5(ninety_offsets_final_r[1]), .O(\sm_r[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair408" *) LUT2 #( .INIT(4'hB)) \sm_r[3]_i_8 (.I0(sm_r[3]), .I1(sm_r[2]), .O(\sm_r[3]_i_8_n_0 )); LUT4 #( .INIT(16'h08AA)) \sm_r[3]_i_9 (.I0(po_stg23_incdec_r_i_6_n_0), .I1(po_stg23_incdec_r_i_9_n_0), .I2(\sm_r[3]_i_10_n_0 ), .I3(po_stg23_incdec_r_i_7_n_0), .O(\sm_r[3]_i_9_n_0 )); FDRE \sm_r_reg[0] (.C(CLK), .CE(sm_ns), .D(\sm_r[0]_i_1_n_0 ), .Q(sm_r[0]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \sm_r_reg[1] (.C(CLK), .CE(sm_ns), .D(\sm_r[1]_i_1_n_0 ), .Q(\stg2_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \sm_r_reg[2] (.C(CLK), .CE(sm_ns), .D(\sm_r[2]_i_1_n_0 ), .Q(sm_r[2]), .R(rstdiv0_sync_r1_reg_rep__10)); FDRE \sm_r_reg[3] (.C(CLK), .CE(sm_ns), .D(\sm_r[3]_i_2_n_0 ), .Q(sm_r[3]), .R(rstdiv0_sync_r1_reg_rep__10)); (* SOFT_HLUTNM = "soft_lutpair410" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[0]_i_1 (.I0(\stg2_target_r_reg_n_0_[0] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair413" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[1]_i_1 (.I0(\stg2_target_r_reg_n_0_[1] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair414" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[2]_i_1 (.I0(\stg2_target_r_reg_n_0_[2] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair413" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[3]_i_1 (.I0(\stg2_target_r_reg_n_0_[3] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair414" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[4]_i_1 (.I0(\stg2_target_r_reg_n_0_[4] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair410" *) LUT4 #( .INIT(16'hFFFE)) \stg2_final_r[5]_i_1 (.I0(\stg2_target_r_reg_n_0_[5] ), .I1(\stg2_target_r_reg_n_0_[6] ), .I2(p_1_in), .I3(\stg2_target_r_reg_n_0_[7] ), .O(\stg2_final_r[5]_i_1_n_0 )); FDRE \stg2_final_r_reg[0] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[0]_i_1_n_0 ), .Q(stg2_final_r[0]), .R(p_1_in)); FDRE \stg2_final_r_reg[1] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[1]_i_1_n_0 ), .Q(stg2_final_r[1]), .R(p_1_in)); FDRE \stg2_final_r_reg[2] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[2]_i_1_n_0 ), .Q(stg2_final_r[2]), .R(p_1_in)); FDRE \stg2_final_r_reg[3] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[3]_i_1_n_0 ), .Q(stg2_final_r[3]), .R(p_1_in)); FDRE \stg2_final_r_reg[4] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[4]_i_1_n_0 ), .Q(stg2_final_r[4]), .R(p_1_in)); FDRE \stg2_final_r_reg[5] (.C(CLK), .CE(1'b1), .D(\stg2_final_r[5]_i_1_n_0 ), .Q(stg2_final_r[5]), .R(p_1_in)); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 stg2_ns0_carry (.CI(1'b0), .CO({stg2_ns0_carry_n_0,stg2_ns0_carry_n_1,stg2_ns0_carry_n_2,stg2_ns0_carry_n_3}), .CYINIT(A[0]), .DI({A[3:1],up_r}), .O(out[4:1]), .S({stg2_ns0_carry_i_1_n_0,stg2_ns0_carry_i_2_n_0,stg2_ns0_carry_i_3_n_0,stg2_ns0_carry_i_4_n_0})); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 stg2_ns0_carry__0 (.CI(stg2_ns0_carry_n_0), .CO({NLW_stg2_ns0_carry__0_CO_UNCONNECTED[3],stg2_ns0_carry__0_n_1,stg2_ns0_carry__0_n_2,stg2_ns0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,A[6:4]}), .O(out[8:5]), .S({stg2_ns0_carry__0_i_1_n_0,stg2_ns0_carry__0_i_2_n_0,stg2_ns0_carry__0_i_3_n_0,stg2_ns0_carry__0_i_4_n_0})); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_1 (.I0(A[7]), .I1(A[8]), .O(stg2_ns0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_2 (.I0(A[6]), .I1(A[7]), .O(stg2_ns0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_3 (.I0(A[5]), .I1(A[6]), .O(stg2_ns0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry__0_i_4 (.I0(A[4]), .I1(A[5]), .O(stg2_ns0_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_1 (.I0(A[3]), .I1(A[4]), .O(stg2_ns0_carry_i_1_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_2 (.I0(A[2]), .I1(A[3]), .O(stg2_ns0_carry_i_2_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_3 (.I0(A[1]), .I1(A[2]), .O(stg2_ns0_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) stg2_ns0_carry_i_4 (.I0(A[1]), .I1(up_r), .O(stg2_ns0_carry_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair419" *) LUT3 #( .INIT(8'h35)) \stg2_r[0]_i_1 (.I0(\wl_po_fine_cnt_reg[18] ), .I1(A[0]), .I2(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[0])); (* SOFT_HLUTNM = "soft_lutpair420" *) LUT3 #( .INIT(8'hB8)) \stg2_r[1]_i_1 (.I0(out[1]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[14] [0]), .O(stg2_ns[1])); (* SOFT_HLUTNM = "soft_lutpair417" *) LUT3 #( .INIT(8'hB8)) \stg2_r[2]_i_1 (.I0(out[2]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[14] [1]), .O(stg2_ns[2])); (* SOFT_HLUTNM = "soft_lutpair419" *) LUT3 #( .INIT(8'h8B)) \stg2_r[3]_i_1 (.I0(out[3]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[3] ), .O(stg2_ns[3])); (* SOFT_HLUTNM = "soft_lutpair417" *) LUT3 #( .INIT(8'h8B)) \stg2_r[4]_i_1 (.I0(out[4]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\byte_r_reg[0] ), .O(stg2_ns[4])); (* SOFT_HLUTNM = "soft_lutpair420" *) LUT3 #( .INIT(8'h8B)) \stg2_r[5]_i_1 (.I0(out[5]), .I1(\stg2_r[8]_i_3_n_0 ), .I2(\wl_po_fine_cnt_reg[17] ), .O(stg2_ns[5])); (* SOFT_HLUTNM = "soft_lutpair412" *) LUT2 #( .INIT(4'h8)) \stg2_r[6]_i_1 (.I0(out[6]), .I1(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[6])); (* SOFT_HLUTNM = "soft_lutpair422" *) LUT2 #( .INIT(4'h8)) \stg2_r[7]_i_1 (.I0(out[7]), .I1(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[7])); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) \stg2_r[8]_i_1 (.I0(\stg2_r[8]_i_3_n_0 ), .I1(sm_r[0]), .I2(\stg2_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__26), .I4(sm_r[3]), .I5(sm_r[2]), .O(\stg2_r[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair422" *) LUT2 #( .INIT(4'h8)) \stg2_r[8]_i_2 (.I0(out[8]), .I1(\stg2_r[8]_i_3_n_0 ), .O(stg2_ns[8])); LUT5 #( .INIT(32'h40400040)) \stg2_r[8]_i_3 (.I0(po_done_r), .I1(po_rdy), .I2(\two_r[1]_i_2_n_0 ), .I3(two_r[1]), .I4(two_r[0]), .O(\stg2_r[8]_i_3_n_0 )); FDRE \stg2_r_reg[0] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[0]), .Q(A[0]), .R(1'b0)); FDRE \stg2_r_reg[1] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[1]), .Q(A[1]), .R(1'b0)); FDRE \stg2_r_reg[2] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[2]), .Q(A[2]), .R(1'b0)); FDRE \stg2_r_reg[3] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[3]), .Q(A[3]), .R(1'b0)); FDRE \stg2_r_reg[4] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[4]), .Q(A[4]), .R(1'b0)); FDRE \stg2_r_reg[5] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[5]), .Q(A[5]), .R(1'b0)); FDRE \stg2_r_reg[6] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[6]), .Q(A[6]), .R(1'b0)); FDRE \stg2_r_reg[7] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[7]), .Q(A[7]), .R(1'b0)); FDRE \stg2_r_reg[8] (.C(CLK), .CE(\stg2_r[8]_i_1_n_0 ), .D(stg2_ns[8]), .Q(A[8]), .R(1'b0)); LUT4 #( .INIT(16'h56A6)) \stg2_target_r[1]_i_1 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(p_0_in[0]), .I2(p_0_in0_carry_i_9_n_0), .I3(\stg3_r_reg[0]_0 ), .O(stg2_target_ns)); LUT4 #( .INIT(16'h56A6)) \stg2_target_r[4]_i_7 (.I0(\wl_po_fine_cnt_reg[14] [0]), .I1(p_0_in[0]), .I2(p_0_in0_carry_i_9_n_0), .I3(\stg3_r_reg[0]_0 ), .O(S)); LUT1 #( .INIT(2'h2)) \stg2_target_r[8]_i_3 (.I0(p_0_in0_carry__0_n_5), .O(\stg2_target_r_reg[8]_0 [2])); LUT1 #( .INIT(2'h2)) \stg2_target_r[8]_i_4 (.I0(p_0_in0_carry__0_n_6), .O(\stg2_target_r_reg[8]_0 [1])); LUT1 #( .INIT(2'h2)) \stg2_target_r[8]_i_5 (.I0(p_0_in0_carry__0_n_7), .O(\stg2_target_r_reg[8]_0 [0])); FDRE \stg2_target_r_reg[0] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [0]), .Q(\stg2_target_r_reg_n_0_[0] ), .R(1'b0)); FDRE \stg2_target_r_reg[1] (.C(CLK), .CE(1'b1), .D(stg2_target_ns), .Q(\stg2_target_r_reg_n_0_[1] ), .R(1'b0)); FDRE \stg2_target_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [1]), .Q(\stg2_target_r_reg_n_0_[2] ), .R(1'b0)); FDRE \stg2_target_r_reg[3] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [2]), .Q(\stg2_target_r_reg_n_0_[3] ), .R(1'b0)); FDRE \stg2_target_r_reg[4] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [3]), .Q(\stg2_target_r_reg_n_0_[4] ), .R(1'b0)); FDRE \stg2_target_r_reg[5] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [4]), .Q(\stg2_target_r_reg_n_0_[5] ), .R(1'b0)); FDRE \stg2_target_r_reg[6] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [5]), .Q(\stg2_target_r_reg_n_0_[6] ), .R(1'b0)); FDRE \stg2_target_r_reg[7] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [6]), .Q(\stg2_target_r_reg_n_0_[7] ), .R(1'b0)); FDRE \stg2_target_r_reg[8] (.C(CLK), .CE(1'b1), .D(\wl_po_fine_cnt_reg[23] [7]), .Q(p_1_in), .R(1'b0)); LUT6 #( .INIT(64'h00550F33FF550F33)) \stg3_init_val[0]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[12] ), .I1(\simp_stg3_final_r_reg_n_0_[0] ), .I2(\simp_stg3_final_r_reg_n_0_[6] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1] ), .I5(\simp_stg3_final_r_reg_n_0_[18] ), .O(\stg3_init_val_reg[0] )); LUT6 #( .INIT(64'h5500330F55FF330F)) \stg3_init_val[1]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[19] ), .I1(\simp_stg3_final_r_reg_n_0_[7] ), .I2(\simp_stg3_final_r_reg_n_0_[1] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1] ), .I5(\simp_stg3_final_r_reg_n_0_[13] ), .O(\stg3_init_val_reg[1] )); LUT5 #( .INIT(32'hFAC00AC0)) \stg3_init_val[2]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[8] ), .I1(\simp_stg3_final_r_reg_n_0_[14] ), .I2(\byte_r_reg[1] ), .I3(\byte_r_reg[0]_0 ), .I4(\simp_stg3_final_r_reg_n_0_[20] ), .O(\stg3_init_val_reg[2] )); LUT6 #( .INIT(64'h7747FFFF7444FFFF)) \stg3_init_val[3]_i_1 (.I0(\stg3_init_val[3]_i_2_n_0 ), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1] ), .I3(\simp_stg3_final_r_reg_n_0_[15] ), .I4(oclkdelay_calib_done_r_reg), .I5(\simp_stg3_final_r_reg_n_0_[3] ), .O(\stg3_init_val_reg[3] )); LUT5 #( .INIT(32'h0407C4C7)) \stg3_init_val[3]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[9] ), .I1(\byte_r_reg[0]_0 ), .I2(\byte_r_reg[1] ), .I3(\simp_stg3_final_r_reg_n_0_[5] ), .I4(\simp_stg3_final_r_reg_n_0_[21] ), .O(\stg3_init_val[3]_i_2_n_0 )); LUT5 #( .INIT(32'hF0AC00AC)) \stg3_init_val[4]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[10] ), .I1(\simp_stg3_final_r_reg_n_0_[4] ), .I2(\byte_r_reg[0]_0 ), .I3(\byte_r_reg[1] ), .I4(\simp_stg3_final_r_reg_n_0_[22] ), .O(\stg3_init_val_reg[4] )); LUT6 #( .INIT(64'h0FDD00CC0FDDFFCC)) \stg3_init_val[5]_i_2 (.I0(\simp_stg3_final_r_reg_n_0_[17] ), .I1(\stg3_init_val[3]_i_2_n_0 ), .I2(\simp_stg3_final_r_reg_n_0_[23] ), .I3(\byte_r_reg[0]_0 ), .I4(\byte_r_reg[1] ), .I5(\simp_stg3_final_r_reg_n_0_[11] ), .O(\stg3_init_val_reg[5] )); LUT2 #( .INIT(4'h2)) \stg3_r[0]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(Q[0]), .O(stg3_ns[0])); (* SOFT_HLUTNM = "soft_lutpair402" *) LUT4 #( .INIT(16'hD714)) \stg3_r[1]_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(Q[1]), .I2(Q[0]), .I3(ocd2stg3_dec), .O(stg3_ns[1])); (* SOFT_HLUTNM = "soft_lutpair402" *) LUT5 #( .INIT(32'h8CC2BEEE)) \stg3_r[2]_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(ocd2stg3_dec), .O(stg3_ns[2])); LUT6 #( .INIT(64'h8CCCCCC2BEEEEEEE)) \stg3_r[3]_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(ocd2stg3_dec), .O(stg3_ns[3])); LUT6 #( .INIT(64'hFF6A0000FF6AFF6A)) \stg3_r[4]_i_1 (.I0(Q[4]), .I1(Q[3]), .I2(\stg3_r[5]_i_5_n_0 ), .I3(\stg3_r[5]_i_6_n_0 ), .I4(D[4]), .I5(ocd2stg3_dec), .O(stg3_ns[4])); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) \stg3_r[5]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(sm_r[0]), .I2(\stg2_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__26), .I4(sm_r[3]), .I5(sm_r[2]), .O(\stg3_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'hEEEE0EEEEEEEEEEE)) \stg3_r[5]_i_10 (.I0(scan_right_r_reg), .I1(samp_done_r_reg), .I2(po_done_r), .I3(\stg2_r_reg[0]_0 ), .I4(E), .I5(inc_po_r), .O(\stg3_r[5]_i_10_n_0 )); LUT5 #( .INIT(32'hFFFFFFEF)) \stg3_r[5]_i_11 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(sm_r[0]), .I2(sm_r[3]), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[2]), .O(\stg3_r[5]_i_11_n_0 )); LUT6 #( .INIT(64'h0080AAAA00800080)) \stg3_r[5]_i_12 (.I0(\stg3_r[5]_i_9_n_0 ), .I1(cmplx_samples_done_r_i_3_n_0), .I2(dec_po_r), .I3(inc_po_r), .I4(samp_done_r_reg), .I5(scan_right_r_reg), .O(\stg3_r[5]_i_12_n_0 )); LUT6 #( .INIT(64'h006AFFFF006A006A)) \stg3_r[5]_i_2 (.I0(Q[5]), .I1(\stg3_r[5]_i_4_n_0 ), .I2(\stg3_r[5]_i_5_n_0 ), .I3(\stg3_r[5]_i_6_n_0 ), .I4(\stg3_r[5]_i_7_n_0 ), .I5(ocd2stg3_dec), .O(stg3_ns[5])); LUT2 #( .INIT(4'hB)) \stg3_r[5]_i_3 (.I0(ocd2stg3_dec), .I1(\stg3_r[5]_i_6_n_0 ), .O(\two_r_reg[1]_0 )); LUT2 #( .INIT(4'h8)) \stg3_r[5]_i_4 (.I0(Q[4]), .I1(Q[3]), .O(\stg3_r[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair418" *) LUT3 #( .INIT(8'h80)) \stg3_r[5]_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\stg3_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'hDDDDDDDDD0DDDDDD)) \stg3_r[5]_i_6 (.I0(\stg3_r[5]_i_9_n_0 ), .I1(\stg3_r[5]_i_10_n_0 ), .I2(\stg3_r[5]_i_11_n_0 ), .I3(poc_backup_r), .I4(po_rdy), .I5(E), .O(\stg3_r[5]_i_6_n_0 )); LUT6 #( .INIT(64'h5555555555555556)) \stg3_r[5]_i_7 (.I0(Q[5]), .I1(Q[4]), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(Q[3]), .O(\stg3_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAEAA)) \stg3_r[5]_i_8 (.I0(\stg3_r[5]_i_12_n_0 ), .I1(sm_r[2]), .I2(sm_r[3]), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[0]), .I5(rstdiv0_sync_r1_reg_rep__26_0), .O(ocd2stg3_dec)); LUT4 #( .INIT(16'h0100)) \stg3_r[5]_i_9 (.I0(rstdiv0_sync_r1_reg_rep__26), .I1(sm_r[3]), .I2(sm_r[2]), .I3(sm_r[0]), .O(\stg3_r[5]_i_9_n_0 )); FDRE \stg3_r_reg[0] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[0]), .Q(Q[0]), .R(1'b0)); FDRE \stg3_r_reg[1] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[1]), .Q(Q[1]), .R(1'b0)); FDRE \stg3_r_reg[2] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[2]), .Q(Q[2]), .R(1'b0)); FDRE \stg3_r_reg[3] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[3]), .Q(Q[3]), .R(1'b0)); FDRE \stg3_r_reg[4] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[4]), .Q(Q[4]), .R(1'b0)); FDRE \stg3_r_reg[5] (.C(CLK), .CE(\stg3_r[5]_i_1_n_0 ), .D(stg3_ns[5]), .Q(Q[5]), .R(1'b0)); LUT3 #( .INIT(8'h1C)) \two_r[0]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(\stg2_r[8]_i_3_n_0 ), .I2(two_r[0]), .O(\two_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h505050501C505050)) \two_r[1]_i_1 (.I0(\two_r_reg[1]_0 ), .I1(two_r[0]), .I2(two_r[1]), .I3(\two_r[1]_i_2_n_0 ), .I4(po_rdy), .I5(po_done_r), .O(\two_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair398" *) LUT5 #( .INIT(32'hFCFFFFEF)) \two_r[1]_i_2 (.I0(sm_r[2]), .I1(rstdiv0_sync_r1_reg_rep__26), .I2(sm_r[3]), .I3(\stg2_r_reg[0]_0 ), .I4(sm_r[0]), .O(\two_r[1]_i_2_n_0 )); FDRE \two_r_reg[0] (.C(CLK), .CE(1'b1), .D(\two_r[0]_i_1_n_0 ), .Q(two_r[0]), .R(1'b0)); FDRE \two_r_reg[1] (.C(CLK), .CE(1'b1), .D(\two_r[1]_i_1_n_0 ), .Q(two_r[1]), .R(1'b0)); LUT3 #( .INIT(8'hF8)) up_r_i_1 (.I0(\stg3_r[5]_i_6_n_0 ), .I1(up_r), .I2(ocd2stg3_dec), .O(up_r_i_1_n_0)); FDRE up_r_reg (.C(CLK), .CE(1'b1), .D(up_r_i_1_n_0), .Q(up_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair423" *) LUT1 #( .INIT(2'h1)) \zero2fuzz_r[0]_i_1 (.I0(Q[0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair423" *) LUT2 #( .INIT(4'h9)) \zero2fuzz_r[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair418" *) LUT3 #( .INIT(8'hA9)) \zero2fuzz_r[2]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair399" *) LUT4 #( .INIT(16'hAAA9)) \zero2fuzz_r[3]_i_1 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair399" *) LUT5 #( .INIT(32'hAAAAAAA9)) \zero2fuzz_r[4]_i_1 (.I0(Q[4]), .I1(Q[3]), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .O(D[4])); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \zero2fuzz_r[5]_i_2 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[5]), .O(D[5])); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_ocd_samp (oclk_calib_resume_level_reg, \samps_r_reg[9]_0 , samp_done, oclk_calib_resume_r_reg_0, prev_samp_valid_r_reg, D, \samps_r_reg[0]_0 , agg_samp_r, \stg3_r_reg[1] , \rd_victim_sel_r_reg[2]_0 , \rd_victim_sel_r_reg[1]_0 , \rd_victim_sel_r_reg[1]_1 , \oneeighty2fuzz_r_reg[5] , o2f_ns1_out, E, f2z_ns5_out, \init_state_r_reg[4] , \init_state_r_reg[5] , \prev_samp_r_reg[0] , \prev_samp_r_reg[1] , rstdiv0_sync_r1_reg_rep__10, CLK, rstdiv0_sync_r1_reg_rep__9, samp_done_ns8_out, phy_rddata_en_r1_reg, rstdiv0_sync_r1_reg_rep__26, rstdiv0_sync_r1_reg_rep__25, \sm_r_reg[0]_0 , rd_active_r1, prev_samp_valid_r, rstdiv0_sync_r1_reg_rep__20, \data_bytes_r_reg[32] , \data_bytes_r_reg[24] , rd_active_r2, \sm_r_reg[1] , scanning_right_r_reg, phy_rddata_en_r1_reg_0, reset_scan, prev_samp_r, f2o_r_reg, scanning_right, \init_state_r_reg[0] , prbs_rdlvl_done_reg, prech_req_r_reg, ocd_prech_req_r_reg, \init_state_r_reg[4]_0 , prbs_rdlvl_done_reg_rep, \rd_victim_sel_r_reg[0]_0 ); output oclk_calib_resume_level_reg; output \samps_r_reg[9]_0 ; output samp_done; output oclk_calib_resume_r_reg_0; output prev_samp_valid_r_reg; output [1:0]D; output \samps_r_reg[0]_0 ; output [1:0]agg_samp_r; output \stg3_r_reg[1] ; output \rd_victim_sel_r_reg[2]_0 ; output \rd_victim_sel_r_reg[1]_0 ; output \rd_victim_sel_r_reg[1]_1 ; output [0:0]\oneeighty2fuzz_r_reg[5] ; output o2f_ns1_out; output [0:0]E; output f2z_ns5_out; output \init_state_r_reg[4] ; output \init_state_r_reg[5] ; output \prev_samp_r_reg[0] ; output \prev_samp_r_reg[1] ; input rstdiv0_sync_r1_reg_rep__10; input CLK; input rstdiv0_sync_r1_reg_rep__9; input samp_done_ns8_out; input phy_rddata_en_r1_reg; input rstdiv0_sync_r1_reg_rep__26; input rstdiv0_sync_r1_reg_rep__25; input [0:0]\sm_r_reg[0]_0 ; input rd_active_r1; input prev_samp_valid_r; input rstdiv0_sync_r1_reg_rep__20; input \data_bytes_r_reg[32] ; input \data_bytes_r_reg[24] ; input rd_active_r2; input [0:0]\sm_r_reg[1] ; input scanning_right_r_reg; input phy_rddata_en_r1_reg_0; input reset_scan; input [1:0]prev_samp_r; input f2o_r_reg; input scanning_right; input \init_state_r_reg[0] ; input prbs_rdlvl_done_reg; input prech_req_r_reg; input ocd_prech_req_r_reg; input [0:0]\init_state_r_reg[4]_0 ; input prbs_rdlvl_done_reg_rep; input [0:0]\rd_victim_sel_r_reg[0]_0 ; wire CLK; wire [1:0]D; wire [0:0]E; wire agg_samp_ns; wire [1:0]agg_samp_r; wire \agg_samp_r[0]_i_1_n_0 ; wire \agg_samp_r[1]_i_1_n_0 ; wire \data_bytes_r_reg[24] ; wire \data_bytes_r_reg[32] ; wire data_cnt_ns; wire [7:0]data_cnt_r; wire \data_cnt_r[2]_i_1_n_0 ; wire \data_cnt_r[3]_i_1_n_0 ; wire \data_cnt_r[4]_i_1_n_0 ; wire \data_cnt_r[6]_i_3_n_0 ; wire \data_cnt_r[7]_i_1_n_0 ; wire \data_cnt_r[7]_i_2_n_0 ; wire f2o_r_reg; wire f2z_ns5_out; wire \fuzz2zero_r[5]_i_3_n_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[4] ; wire [0:0]\init_state_r_reg[4]_0 ; wire \init_state_r_reg[5] ; wire o2f_ns1_out; wire ocd_prech_req_r_reg; wire oclk_calib_resume_level_reg; wire oclk_calib_resume_r_i_1_n_0; wire oclk_calib_resume_r_i_6_n_0; wire oclk_calib_resume_r_reg_0; wire [0:0]\oneeighty2fuzz_r_reg[5] ; wire oneeighty_ge_thresh; wire oneeighty_ge_thresh_carry__0_i_1_n_0; wire oneeighty_ge_thresh_carry_i_1_n_0; wire oneeighty_ge_thresh_carry_i_2_n_0; wire oneeighty_ge_thresh_carry_i_3_n_0; wire oneeighty_ge_thresh_carry_i_4_n_0; wire oneeighty_ge_thresh_carry_i_5_n_0; wire oneeighty_ge_thresh_carry_i_6_n_0; wire oneeighty_ge_thresh_carry_n_0; wire oneeighty_ge_thresh_carry_n_1; wire oneeighty_ge_thresh_carry_n_2; wire oneeighty_ge_thresh_carry_n_3; wire oneeighty_le_half_thresh; wire oneeighty_le_half_thresh_carry__0_i_1_n_0; wire oneeighty_le_half_thresh_carry_i_1_n_0; wire oneeighty_le_half_thresh_carry_i_2_n_0; wire oneeighty_le_half_thresh_carry_i_3_n_0; wire oneeighty_le_half_thresh_carry_i_4_n_0; wire oneeighty_le_half_thresh_carry_i_5_n_0; wire oneeighty_le_half_thresh_carry_i_6_n_0; wire oneeighty_le_half_thresh_carry_i_7_n_0; wire oneeighty_le_half_thresh_carry_n_0; wire oneeighty_le_half_thresh_carry_n_1; wire oneeighty_le_half_thresh_carry_n_2; wire oneeighty_le_half_thresh_carry_n_3; wire oneeighty_ns; wire \oneeighty_r[0]_i_1_n_0 ; wire \oneeighty_r[6]_i_2_n_0 ; wire \oneeighty_r[9]_i_3_n_0 ; wire [9:0]oneeighty_r_reg__0; wire [6:0]p_0_in; wire p_0_in11_in; wire [9:1]p_0_in__1; wire [9:1]p_0_in__2; wire phy_rddata_en_r1_reg; wire phy_rddata_en_r1_reg_0; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prech_req_r_reg; wire [1:0]prev_samp_r; wire \prev_samp_r_reg[0] ; wire \prev_samp_r_reg[1] ; wire prev_samp_valid_r; wire prev_samp_valid_r_reg; wire rd_active_r1; wire rd_active_r2; wire \rd_victim_sel_r[0]_i_1_n_0 ; wire \rd_victim_sel_r[1]_i_1_n_0 ; wire \rd_victim_sel_r[2]_i_1_n_0 ; wire [0:0]\rd_victim_sel_r_reg[0]_0 ; wire \rd_victim_sel_r_reg[1]_0 ; wire \rd_victim_sel_r_reg[1]_1 ; wire \rd_victim_sel_r_reg[2]_0 ; wire reset_scan; wire rstdiv0_sync_r1_reg_rep__10; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__9; wire samp_done; wire samp_done_ns8_out; wire samp_done_ns9_in; wire samp_done_r_i_1_n_0; wire \samp_result_r_reg_n_0_[0] ; wire samps_ns; wire [9:0]samps_r; wire [8:0]samps_r0; wire \samps_r[1]_i_1_n_0 ; wire \samps_r[4]_i_1_n_0 ; wire \samps_r[5]_i_1_n_0 ; wire \samps_r[7]_i_1_n_0 ; wire \samps_r[8]_i_3_n_0 ; wire \samps_r[8]_i_4_n_0 ; wire \samps_r[8]_i_5_n_0 ; wire \samps_r[9]_i_1_n_0 ; wire \samps_r[9]_i_2_n_0 ; wire \samps_r[9]_i_3_n_0 ; wire \samps_r_reg[0]_0 ; wire \samps_r_reg[9]_0 ; wire scanning_right; wire scanning_right_r_reg; wire \sm_r[0]_i_1__0_n_0 ; wire [0:0]\sm_r_reg[0]_0 ; wire [0:0]\sm_r_reg[1] ; wire \stg3_r_reg[1] ; wire \u_ocd_edge/samp_valid ; wire zero_ge_thresh; wire zero_ge_thresh_carry__0_i_1_n_0; wire zero_ge_thresh_carry_i_1_n_0; wire zero_ge_thresh_carry_i_2_n_0; wire zero_ge_thresh_carry_i_3_n_0; wire zero_ge_thresh_carry_i_4_n_0; wire zero_ge_thresh_carry_i_5_n_0; wire zero_ge_thresh_carry_i_6_n_0; wire zero_ge_thresh_carry_n_0; wire zero_ge_thresh_carry_n_1; wire zero_ge_thresh_carry_n_2; wire zero_ge_thresh_carry_n_3; wire zero_le_half_thresh; wire zero_le_half_thresh_carry__0_i_1_n_0; wire zero_le_half_thresh_carry_i_1_n_0; wire zero_le_half_thresh_carry_i_2_n_0; wire zero_le_half_thresh_carry_i_3_n_0; wire zero_le_half_thresh_carry_i_4_n_0; wire zero_le_half_thresh_carry_i_5_n_0; wire zero_le_half_thresh_carry_i_6_n_0; wire zero_le_half_thresh_carry_i_7_n_0; wire zero_le_half_thresh_carry_n_0; wire zero_le_half_thresh_carry_n_1; wire zero_le_half_thresh_carry_n_2; wire zero_le_half_thresh_carry_n_3; wire \zero_r[0]_i_1_n_0 ; wire \zero_r[6]_i_2_n_0 ; wire \zero_r[9]_i_8_n_0 ; wire [9:0]zero_r_reg__0; wire [3:0]NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED; wire [3:0]NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED; wire [3:0]NLW_zero_ge_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_zero_ge_thresh_carry__0_O_UNCONNECTED; wire [3:0]NLW_zero_le_half_thresh_carry_O_UNCONNECTED; wire [3:1]NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED; wire [3:0]NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED; LUT6 #( .INIT(64'hFFFFFFF1F1F1FFF1)) \agg_samp_r[0]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(\samps_r_reg[0]_0 ), .I3(agg_samp_r[0]), .I4(agg_samp_ns), .I5(\data_bytes_r_reg[24] ), .O(\agg_samp_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFF1F1F1FFF1)) \agg_samp_r[1]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(\samps_r_reg[0]_0 ), .I3(agg_samp_r[1]), .I4(agg_samp_ns), .I5(\data_bytes_r_reg[32] ), .O(\agg_samp_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h4444444444444440)) \agg_samp_r[1]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(phy_rddata_en_r1_reg), .I2(\rd_victim_sel_r_reg[2]_0 ), .I3(\rd_victim_sel_r_reg[1]_0 ), .I4(\rd_victim_sel_r_reg[1]_1 ), .I5(oclk_calib_resume_r_reg_0), .O(agg_samp_ns)); FDRE \agg_samp_r_reg[0] (.C(CLK), .CE(1'b1), .D(\agg_samp_r[0]_i_1_n_0 ), .Q(agg_samp_r[0]), .R(1'b0)); FDRE \agg_samp_r_reg[1] (.C(CLK), .CE(1'b1), .D(\agg_samp_r[1]_i_1_n_0 ), .Q(agg_samp_r[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair435" *) LUT3 #( .INIT(8'h7F)) \data_cnt_r[0]_i_1 (.I0(data_cnt_r[0]), .I1(\samps_r_reg[9]_0 ), .I2(oclk_calib_resume_r_reg_0), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair435" *) LUT3 #( .INIT(8'h82)) \data_cnt_r[1]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(data_cnt_r[1]), .I2(data_cnt_r[0]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair431" *) LUT3 #( .INIT(8'hA9)) \data_cnt_r[2]_i_1 (.I0(data_cnt_r[2]), .I1(data_cnt_r[1]), .I2(data_cnt_r[0]), .O(\data_cnt_r[2]_i_1_n_0 )); LUT4 #( .INIT(16'hAAA9)) \data_cnt_r[3]_i_1 (.I0(data_cnt_r[3]), .I1(data_cnt_r[2]), .I2(data_cnt_r[1]), .I3(data_cnt_r[0]), .O(\data_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair428" *) LUT5 #( .INIT(32'hAAAAAAA9)) \data_cnt_r[4]_i_1 (.I0(data_cnt_r[4]), .I1(data_cnt_r[3]), .I2(data_cnt_r[0]), .I3(data_cnt_r[1]), .I4(data_cnt_r[2]), .O(\data_cnt_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair432" *) LUT3 #( .INIT(8'h28)) \data_cnt_r[5]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(\data_cnt_r[6]_i_3_n_0 ), .I2(data_cnt_r[5]), .O(p_0_in[5])); LUT3 #( .INIT(8'h31)) \data_cnt_r[6]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(phy_rddata_en_r1_reg), .O(data_cnt_ns)); (* SOFT_HLUTNM = "soft_lutpair432" *) LUT4 #( .INIT(16'h8A20)) \data_cnt_r[6]_i_2 (.I0(\samps_r_reg[9]_0 ), .I1(data_cnt_r[5]), .I2(\data_cnt_r[6]_i_3_n_0 ), .I3(data_cnt_r[6]), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair428" *) LUT5 #( .INIT(32'h00000001)) \data_cnt_r[6]_i_3 (.I0(data_cnt_r[3]), .I1(data_cnt_r[0]), .I2(data_cnt_r[1]), .I3(data_cnt_r[2]), .I4(data_cnt_r[4]), .O(\data_cnt_r[6]_i_3_n_0 )); LUT4 #( .INIT(16'h0323)) \data_cnt_r[7]_i_1 (.I0(phy_rddata_en_r1_reg), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(\samps_r_reg[9]_0 ), .I3(oclk_calib_resume_r_reg_0), .O(\data_cnt_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'hAAA6)) \data_cnt_r[7]_i_2 (.I0(data_cnt_r[7]), .I1(\data_cnt_r[6]_i_3_n_0 ), .I2(data_cnt_r[5]), .I3(data_cnt_r[6]), .O(\data_cnt_r[7]_i_2_n_0 )); FDRE \data_cnt_r_reg[0] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[0]), .Q(data_cnt_r[0]), .R(1'b0)); FDRE \data_cnt_r_reg[1] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[1]), .Q(data_cnt_r[1]), .R(1'b0)); FDRE \data_cnt_r_reg[2] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[2]_i_1_n_0 ), .Q(data_cnt_r[2]), .R(\data_cnt_r[7]_i_1_n_0 )); FDRE \data_cnt_r_reg[3] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[3]_i_1_n_0 ), .Q(data_cnt_r[3]), .R(\data_cnt_r[7]_i_1_n_0 )); FDRE \data_cnt_r_reg[4] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[4]_i_1_n_0 ), .Q(data_cnt_r[4]), .R(\data_cnt_r[7]_i_1_n_0 )); FDRE \data_cnt_r_reg[5] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[5]), .Q(data_cnt_r[5]), .R(1'b0)); FDRE \data_cnt_r_reg[6] (.C(CLK), .CE(data_cnt_ns), .D(p_0_in[6]), .Q(data_cnt_r[6]), .R(1'b0)); FDRE \data_cnt_r_reg[7] (.C(CLK), .CE(data_cnt_ns), .D(\data_cnt_r[7]_i_2_n_0 ), .Q(data_cnt_r[7]), .R(\data_cnt_r[7]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \fuzz2zero_r[5]_i_1 (.I0(f2z_ns5_out), .I1(reset_scan), .O(E)); LUT6 #( .INIT(64'h0080808000000000)) \fuzz2zero_r[5]_i_2 (.I0(\fuzz2zero_r[5]_i_3_n_0 ), .I1(\u_ocd_edge/samp_valid ), .I2(prev_samp_valid_r), .I3(f2o_r_reg), .I4(prev_samp_r[1]), .I5(D[0]), .O(f2z_ns5_out)); LUT3 #( .INIT(8'h04)) \fuzz2zero_r[5]_i_3 (.I0(D[1]), .I1(scanning_right), .I2(prev_samp_r[0]), .O(\fuzz2zero_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h1111111111111110)) \init_state_r[4]_i_36 (.I0(\init_state_r_reg[0] ), .I1(oclk_calib_resume_level_reg), .I2(prbs_rdlvl_done_reg), .I3(prech_req_r_reg), .I4(ocd_prech_req_r_reg), .I5(\init_state_r_reg[4]_0 ), .O(\init_state_r_reg[4] )); LUT4 #( .INIT(16'hFFFE)) \init_state_r[5]_i_47 (.I0(oclk_calib_resume_level_reg), .I1(ocd_prech_req_r_reg), .I2(prech_req_r_reg), .I3(prbs_rdlvl_done_reg_rep), .O(\init_state_r_reg[5] )); LUT5 #( .INIT(32'hAAAABAAA)) oclk_calib_resume_r_i_1 (.I0(samp_done_ns8_out), .I1(oclk_calib_resume_r_reg_0), .I2(phy_rddata_en_r1_reg), .I3(\samps_r_reg[9]_0 ), .I4(samp_done_ns9_in), .O(oclk_calib_resume_r_i_1_n_0)); LUT5 #( .INIT(32'hFFFFFEFF)) oclk_calib_resume_r_i_3 (.I0(data_cnt_r[7]), .I1(data_cnt_r[4]), .I2(data_cnt_r[3]), .I3(data_cnt_r[0]), .I4(oclk_calib_resume_r_i_6_n_0), .O(oclk_calib_resume_r_reg_0)); LUT6 #( .INIT(64'hAAAAAAABAAAAAAAA)) oclk_calib_resume_r_i_4 (.I0(samp_done), .I1(oclk_calib_resume_r_reg_0), .I2(\rd_victim_sel_r_reg[1]_1 ), .I3(\rd_victim_sel_r_reg[1]_0 ), .I4(\rd_victim_sel_r_reg[2]_0 ), .I5(\samps_r[8]_i_3_n_0 ), .O(samp_done_ns9_in)); (* SOFT_HLUTNM = "soft_lutpair431" *) LUT4 #( .INIT(16'hFFFE)) oclk_calib_resume_r_i_6 (.I0(data_cnt_r[6]), .I1(data_cnt_r[5]), .I2(data_cnt_r[1]), .I3(data_cnt_r[2]), .O(oclk_calib_resume_r_i_6_n_0)); FDRE oclk_calib_resume_r_reg (.C(CLK), .CE(1'b1), .D(oclk_calib_resume_r_i_1_n_0), .Q(oclk_calib_resume_level_reg), .R(rstdiv0_sync_r1_reg_rep__10)); LUT2 #( .INIT(4'h2)) \oneeighty2fuzz_r[5]_i_1 (.I0(o2f_ns1_out), .I1(reset_scan), .O(\oneeighty2fuzz_r_reg[5] )); LUT6 #( .INIT(64'h8000800000008000)) \oneeighty2fuzz_r[5]_i_2 (.I0(\fuzz2zero_r[5]_i_3_n_0 ), .I1(\u_ocd_edge/samp_valid ), .I2(prev_samp_valid_r), .I3(prev_samp_r[1]), .I4(D[0]), .I5(f2o_r_reg), .O(o2f_ns1_out)); CARRY4 oneeighty_ge_thresh_carry (.CI(1'b0), .CO({oneeighty_ge_thresh_carry_n_0,oneeighty_ge_thresh_carry_n_1,oneeighty_ge_thresh_carry_n_2,oneeighty_ge_thresh_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,oneeighty_ge_thresh_carry_i_1_n_0,oneeighty_r_reg__0[3],oneeighty_ge_thresh_carry_i_2_n_0}), .O(NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED[3:0]), .S({oneeighty_ge_thresh_carry_i_3_n_0,oneeighty_ge_thresh_carry_i_4_n_0,oneeighty_ge_thresh_carry_i_5_n_0,oneeighty_ge_thresh_carry_i_6_n_0})); CARRY4 oneeighty_ge_thresh_carry__0 (.CI(oneeighty_ge_thresh_carry_n_0), .CO({NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_ge_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,oneeighty_r_reg__0[9]}), .O(NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,oneeighty_ge_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry__0_i_1 (.I0(oneeighty_r_reg__0[8]), .I1(oneeighty_r_reg__0[9]), .O(oneeighty_ge_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_ge_thresh_carry_i_1 (.I0(oneeighty_r_reg__0[4]), .I1(oneeighty_r_reg__0[5]), .O(oneeighty_ge_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_ge_thresh_carry_i_2 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(oneeighty_ge_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_ge_thresh_carry_i_3 (.I0(oneeighty_r_reg__0[7]), .I1(oneeighty_r_reg__0[6]), .O(oneeighty_ge_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry_i_4 (.I0(oneeighty_r_reg__0[5]), .I1(oneeighty_r_reg__0[4]), .O(oneeighty_ge_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry_i_5 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[3]), .O(oneeighty_ge_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) oneeighty_ge_thresh_carry_i_6 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(oneeighty_ge_thresh_carry_i_6_n_0)); CARRY4 oneeighty_le_half_thresh_carry (.CI(1'b0), .CO({oneeighty_le_half_thresh_carry_n_0,oneeighty_le_half_thresh_carry_n_1,oneeighty_le_half_thresh_carry_n_2,oneeighty_le_half_thresh_carry_n_3}), .CYINIT(1'b1), .DI({oneeighty_le_half_thresh_carry_i_1_n_0,oneeighty_le_half_thresh_carry_i_2_n_0,1'b0,oneeighty_le_half_thresh_carry_i_3_n_0}), .O(NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED[3:0]), .S({oneeighty_le_half_thresh_carry_i_4_n_0,oneeighty_le_half_thresh_carry_i_5_n_0,oneeighty_le_half_thresh_carry_i_6_n_0,oneeighty_le_half_thresh_carry_i_7_n_0})); CARRY4 oneeighty_le_half_thresh_carry__0 (.CI(oneeighty_le_half_thresh_carry_n_0), .CO({NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_le_half_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,oneeighty_le_half_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h1)) oneeighty_le_half_thresh_carry__0_i_1 (.I0(oneeighty_r_reg__0[8]), .I1(oneeighty_r_reg__0[9]), .O(oneeighty_le_half_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h7)) oneeighty_le_half_thresh_carry_i_1 (.I0(oneeighty_r_reg__0[6]), .I1(oneeighty_r_reg__0[7]), .O(oneeighty_le_half_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h7)) oneeighty_le_half_thresh_carry_i_2 (.I0(oneeighty_r_reg__0[5]), .I1(oneeighty_r_reg__0[4]), .O(oneeighty_le_half_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h7)) oneeighty_le_half_thresh_carry_i_3 (.I0(oneeighty_r_reg__0[0]), .I1(oneeighty_r_reg__0[1]), .O(oneeighty_le_half_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_le_half_thresh_carry_i_4 (.I0(oneeighty_r_reg__0[7]), .I1(oneeighty_r_reg__0[6]), .O(oneeighty_le_half_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_le_half_thresh_carry_i_5 (.I0(oneeighty_r_reg__0[4]), .I1(oneeighty_r_reg__0[5]), .O(oneeighty_le_half_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h1)) oneeighty_le_half_thresh_carry_i_6 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[3]), .O(oneeighty_le_half_thresh_carry_i_6_n_0)); LUT2 #( .INIT(4'h8)) oneeighty_le_half_thresh_carry_i_7 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(oneeighty_le_half_thresh_carry_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair440" *) LUT1 #( .INIT(2'h1)) \oneeighty_r[0]_i_1 (.I0(oneeighty_r_reg__0[0]), .O(\oneeighty_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair440" *) LUT2 #( .INIT(4'h6)) \oneeighty_r[1]_i_1 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair437" *) LUT3 #( .INIT(8'h6A)) \oneeighty_r[2]_i_1 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[0]), .I2(oneeighty_r_reg__0[1]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair425" *) LUT4 #( .INIT(16'h6AAA)) \oneeighty_r[3]_i_1 (.I0(oneeighty_r_reg__0[3]), .I1(oneeighty_r_reg__0[1]), .I2(oneeighty_r_reg__0[0]), .I3(oneeighty_r_reg__0[2]), .O(p_0_in__2[3])); (* SOFT_HLUTNM = "soft_lutpair425" *) LUT5 #( .INIT(32'h6AAAAAAA)) \oneeighty_r[4]_i_1 (.I0(oneeighty_r_reg__0[4]), .I1(oneeighty_r_reg__0[2]), .I2(oneeighty_r_reg__0[0]), .I3(oneeighty_r_reg__0[1]), .I4(oneeighty_r_reg__0[3]), .O(p_0_in__2[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \oneeighty_r[5]_i_1 (.I0(oneeighty_r_reg__0[5]), .I1(oneeighty_r_reg__0[3]), .I2(oneeighty_r_reg__0[1]), .I3(oneeighty_r_reg__0[0]), .I4(oneeighty_r_reg__0[2]), .I5(oneeighty_r_reg__0[4]), .O(p_0_in__2[5])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \oneeighty_r[6]_i_1 (.I0(oneeighty_r_reg__0[6]), .I1(oneeighty_r_reg__0[4]), .I2(oneeighty_r_reg__0[5]), .I3(oneeighty_r_reg__0[3]), .I4(\oneeighty_r[6]_i_2_n_0 ), .I5(oneeighty_r_reg__0[2]), .O(p_0_in__2[6])); (* SOFT_HLUTNM = "soft_lutpair437" *) LUT2 #( .INIT(4'h8)) \oneeighty_r[6]_i_2 (.I0(oneeighty_r_reg__0[1]), .I1(oneeighty_r_reg__0[0]), .O(\oneeighty_r[6]_i_2_n_0 )); LUT3 #( .INIT(8'h6A)) \oneeighty_r[7]_i_1 (.I0(oneeighty_r_reg__0[7]), .I1(\oneeighty_r[9]_i_3_n_0 ), .I2(oneeighty_r_reg__0[6]), .O(p_0_in__2[7])); (* SOFT_HLUTNM = "soft_lutpair430" *) LUT4 #( .INIT(16'h6AAA)) \oneeighty_r[8]_i_1 (.I0(oneeighty_r_reg__0[8]), .I1(oneeighty_r_reg__0[7]), .I2(oneeighty_r_reg__0[6]), .I3(\oneeighty_r[9]_i_3_n_0 ), .O(p_0_in__2[8])); LUT2 #( .INIT(4'h8)) \oneeighty_r[9]_i_1 (.I0(\samps_r_reg[0]_0 ), .I1(\data_bytes_r_reg[32] ), .O(oneeighty_ns)); (* SOFT_HLUTNM = "soft_lutpair430" *) LUT5 #( .INIT(32'h6AAAAAAA)) \oneeighty_r[9]_i_2 (.I0(oneeighty_r_reg__0[9]), .I1(\oneeighty_r[9]_i_3_n_0 ), .I2(oneeighty_r_reg__0[6]), .I3(oneeighty_r_reg__0[7]), .I4(oneeighty_r_reg__0[8]), .O(p_0_in__2[9])); LUT6 #( .INIT(64'h8000000000000000)) \oneeighty_r[9]_i_3 (.I0(oneeighty_r_reg__0[2]), .I1(oneeighty_r_reg__0[0]), .I2(oneeighty_r_reg__0[1]), .I3(oneeighty_r_reg__0[3]), .I4(oneeighty_r_reg__0[5]), .I5(oneeighty_r_reg__0[4]), .O(\oneeighty_r[9]_i_3_n_0 )); FDRE \oneeighty_r_reg[0] (.C(CLK), .CE(oneeighty_ns), .D(\oneeighty_r[0]_i_1_n_0 ), .Q(oneeighty_r_reg__0[0]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[1] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[1]), .Q(oneeighty_r_reg__0[1]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[2] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[2]), .Q(oneeighty_r_reg__0[2]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[3] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[3]), .Q(oneeighty_r_reg__0[3]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[4] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[4]), .Q(oneeighty_r_reg__0[4]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[5] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[5]), .Q(oneeighty_r_reg__0[5]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[6] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[6]), .Q(oneeighty_r_reg__0[6]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[7] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[7]), .Q(oneeighty_r_reg__0[7]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[8] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[8]), .Q(oneeighty_r_reg__0[8]), .R(\sm_r_reg[0]_0 )); FDRE \oneeighty_r_reg[9] (.C(CLK), .CE(oneeighty_ns), .D(p_0_in__2[9]), .Q(oneeighty_r_reg__0[9]), .R(\sm_r_reg[0]_0 )); LUT6 #( .INIT(64'h003AFFFF003A0000)) \prev_samp_r[0]_i_1 (.I0(zero_ge_thresh), .I1(zero_le_half_thresh), .I2(\samp_result_r_reg_n_0_[0] ), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(\u_ocd_edge/samp_valid ), .I5(prev_samp_r[0]), .O(\prev_samp_r_reg[0] )); LUT6 #( .INIT(64'h0454FFFF04540000)) \prev_samp_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(oneeighty_ge_thresh), .I2(p_0_in11_in), .I3(oneeighty_le_half_thresh), .I4(\u_ocd_edge/samp_valid ), .I5(prev_samp_r[1]), .O(\prev_samp_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair434" *) LUT2 #( .INIT(4'h8)) \prev_samp_r[1]_i_2 (.I0(samp_done), .I1(rd_active_r1), .O(\u_ocd_edge/samp_valid )); (* SOFT_HLUTNM = "soft_lutpair434" *) LUT3 #( .INIT(8'hF8)) prev_samp_valid_r_i_1 (.I0(samp_done), .I1(rd_active_r1), .I2(prev_samp_valid_r), .O(prev_samp_valid_r_reg)); LUT6 #( .INIT(64'h6664666466640000)) \rd_victim_sel_r[0]_i_1 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(\rd_victim_sel_r_reg[2]_0 ), .I4(rstdiv0_sync_r1_reg_rep__25), .I5(\samps_r_reg[9]_0 ), .O(\rd_victim_sel_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'h78787800)) \rd_victim_sel_r[1]_i_1 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(\samps_r_reg[9]_0 ), .O(\rd_victim_sel_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h7F807F807F800000)) \rd_victim_sel_r[2]_i_1 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(\rd_victim_sel_r_reg[2]_0 ), .I4(rstdiv0_sync_r1_reg_rep__25), .I5(\samps_r_reg[9]_0 ), .O(\rd_victim_sel_r[2]_i_1_n_0 )); FDRE \rd_victim_sel_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel_r[0]_i_1_n_0 ), .Q(\rd_victim_sel_r_reg[1]_1 ), .R(1'b0)); FDRE \rd_victim_sel_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel_r[1]_i_1_n_0 ), .Q(\rd_victim_sel_r_reg[1]_0 ), .R(1'b0)); FDRE \rd_victim_sel_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel_r[2]_i_1_n_0 ), .Q(\rd_victim_sel_r_reg[2]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAEAAA2A)) samp_done_r_i_1 (.I0(samp_done), .I1(\samps_r_reg[9]_0 ), .I2(phy_rddata_en_r1_reg), .I3(rstdiv0_sync_r1_reg_rep__26), .I4(samp_done_ns9_in), .I5(samp_done_ns8_out), .O(samp_done_r_i_1_n_0)); FDRE samp_done_r_reg (.C(CLK), .CE(1'b1), .D(samp_done_r_i_1_n_0), .Q(samp_done), .R(1'b0)); LUT6 #( .INIT(64'h000000003FFF8080)) \samp_result_r[0]_i_1 (.I0(zero_ge_thresh), .I1(rd_active_r1), .I2(samp_done), .I3(zero_le_half_thresh), .I4(\samp_result_r_reg_n_0_[0] ), .I5(rstdiv0_sync_r1_reg_rep__25), .O(D[0])); LUT6 #( .INIT(64'h1515400055554000)) \samp_result_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(rd_active_r1), .I2(samp_done), .I3(oneeighty_ge_thresh), .I4(p_0_in11_in), .I5(oneeighty_le_half_thresh), .O(D[1])); FDRE \samp_result_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\samp_result_r_reg_n_0_[0] ), .R(1'b0)); FDRE \samp_result_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(p_0_in11_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair438" *) LUT1 #( .INIT(2'h1)) \samps_r[0]_i_1 (.I0(samps_r[0]), .O(samps_r0[0])); LUT4 #( .INIT(16'h9990)) \samps_r[1]_i_1 (.I0(samps_r[1]), .I1(samps_r[0]), .I2(\samps_r_reg[9]_0 ), .I3(rstdiv0_sync_r1_reg_rep__25), .O(\samps_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair438" *) LUT3 #( .INIT(8'hA9)) \samps_r[2]_i_1 (.I0(samps_r[2]), .I1(samps_r[1]), .I2(samps_r[0]), .O(samps_r0[2])); (* SOFT_HLUTNM = "soft_lutpair427" *) LUT4 #( .INIT(16'hAAA9)) \samps_r[3]_i_1 (.I0(samps_r[3]), .I1(samps_r[2]), .I2(samps_r[0]), .I3(samps_r[1]), .O(samps_r0[3])); LUT6 #( .INIT(64'h00000000FFFE0001)) \samps_r[4]_i_1 (.I0(samps_r[2]), .I1(samps_r[0]), .I2(samps_r[1]), .I3(samps_r[3]), .I4(samps_r[4]), .I5(\sm_r_reg[0]_0 ), .O(\samps_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h9990)) \samps_r[5]_i_1 (.I0(\samps_r[8]_i_4_n_0 ), .I1(samps_r[5]), .I2(\samps_r_reg[9]_0 ), .I3(rstdiv0_sync_r1_reg_rep__25), .O(\samps_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair433" *) LUT3 #( .INIT(8'hA9)) \samps_r[6]_i_1 (.I0(samps_r[6]), .I1(\samps_r[8]_i_4_n_0 ), .I2(samps_r[5]), .O(samps_r0[6])); (* SOFT_HLUTNM = "soft_lutpair433" *) LUT4 #( .INIT(16'hAAA9)) \samps_r[7]_i_1 (.I0(samps_r[7]), .I1(samps_r[6]), .I2(samps_r[5]), .I3(\samps_r[8]_i_4_n_0 ), .O(\samps_r[7]_i_1_n_0 )); LUT4 #( .INIT(16'h1F11)) \samps_r[8]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(\samps_r[8]_i_3_n_0 ), .I3(\samps_r_reg[0]_0 ), .O(samps_ns)); (* SOFT_HLUTNM = "soft_lutpair429" *) LUT5 #( .INIT(32'hAAAAAAA9)) \samps_r[8]_i_2 (.I0(samps_r[8]), .I1(\samps_r[8]_i_4_n_0 ), .I2(samps_r[5]), .I3(samps_r[6]), .I4(samps_r[7]), .O(samps_r0[8])); LUT5 #( .INIT(32'h00000001)) \samps_r[8]_i_3 (.I0(samps_r[2]), .I1(samps_r[9]), .I2(samps_r[6]), .I3(samps_r[5]), .I4(\samps_r[8]_i_5_n_0 ), .O(\samps_r[8]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair427" *) LUT5 #( .INIT(32'hFFFFFFFE)) \samps_r[8]_i_4 (.I0(samps_r[4]), .I1(samps_r[3]), .I2(samps_r[2]), .I3(samps_r[0]), .I4(samps_r[1]), .O(\samps_r[8]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \samps_r[8]_i_5 (.I0(samps_r[4]), .I1(samps_r[3]), .I2(samps_r[8]), .I3(samps_r[0]), .I4(samps_r[1]), .I5(samps_r[7]), .O(\samps_r[8]_i_5_n_0 )); LUT4 #( .INIT(16'h1F11)) \samps_r[9]_i_1 (.I0(\samps_r_reg[9]_0 ), .I1(rstdiv0_sync_r1_reg_rep__20), .I2(\samps_r[8]_i_3_n_0 ), .I3(\samps_r_reg[0]_0 ), .O(\samps_r[9]_i_1_n_0 )); LUT5 #( .INIT(32'hD2D2D2FF)) \samps_r[9]_i_2 (.I0(\samps_r[9]_i_3_n_0 ), .I1(samps_r[8]), .I2(samps_r[9]), .I3(\samps_r_reg[9]_0 ), .I4(rstdiv0_sync_r1_reg_rep__25), .O(\samps_r[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair429" *) LUT4 #( .INIT(16'h0001)) \samps_r[9]_i_3 (.I0(samps_r[7]), .I1(samps_r[6]), .I2(samps_r[5]), .I3(\samps_r[8]_i_4_n_0 ), .O(\samps_r[9]_i_3_n_0 )); FDRE \samps_r_reg[0] (.C(CLK), .CE(samps_ns), .D(samps_r0[0]), .Q(samps_r[0]), .R(\sm_r_reg[0]_0 )); FDRE \samps_r_reg[1] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[1]_i_1_n_0 ), .Q(samps_r[1]), .R(1'b0)); FDRE \samps_r_reg[2] (.C(CLK), .CE(samps_ns), .D(samps_r0[2]), .Q(samps_r[2]), .R(\sm_r_reg[0]_0 )); FDRE \samps_r_reg[3] (.C(CLK), .CE(samps_ns), .D(samps_r0[3]), .Q(samps_r[3]), .R(\sm_r_reg[0]_0 )); FDRE \samps_r_reg[4] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[4]_i_1_n_0 ), .Q(samps_r[4]), .R(1'b0)); FDRE \samps_r_reg[5] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[5]_i_1_n_0 ), .Q(samps_r[5]), .R(1'b0)); FDRE \samps_r_reg[6] (.C(CLK), .CE(samps_ns), .D(samps_r0[6]), .Q(samps_r[6]), .R(\sm_r_reg[0]_0 )); FDRE \samps_r_reg[7] (.C(CLK), .CE(samps_ns), .D(\samps_r[7]_i_1_n_0 ), .Q(samps_r[7]), .R(\sm_r_reg[0]_0 )); FDRE \samps_r_reg[8] (.C(CLK), .CE(samps_ns), .D(samps_r0[8]), .Q(samps_r[8]), .R(\sm_r_reg[0]_0 )); FDRE \samps_r_reg[9] (.C(CLK), .CE(\samps_r[9]_i_1_n_0 ), .D(\samps_r[9]_i_2_n_0 ), .Q(samps_r[9]), .R(1'b0)); LUT4 #( .INIT(16'hAEEE)) \sm_r[0]_i_1__0 (.I0(samp_done_ns8_out), .I1(\samps_r_reg[9]_0 ), .I2(phy_rddata_en_r1_reg), .I3(samp_done_ns9_in), .O(\sm_r[0]_i_1__0_n_0 )); FDRE \sm_r_reg[0] (.C(CLK), .CE(1'b1), .D(\sm_r[0]_i_1__0_n_0 ), .Q(\samps_r_reg[9]_0 ), .R(rstdiv0_sync_r1_reg_rep__9)); LUT4 #( .INIT(16'hFFF7)) \stg3_r[5]_i_14 (.I0(samp_done), .I1(rd_active_r2), .I2(\sm_r_reg[1] ), .I3(scanning_right_r_reg), .O(\stg3_r_reg[1] )); CARRY4 zero_ge_thresh_carry (.CI(1'b0), .CO({zero_ge_thresh_carry_n_0,zero_ge_thresh_carry_n_1,zero_ge_thresh_carry_n_2,zero_ge_thresh_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,zero_ge_thresh_carry_i_1_n_0,zero_r_reg__0[3],zero_ge_thresh_carry_i_2_n_0}), .O(NLW_zero_ge_thresh_carry_O_UNCONNECTED[3:0]), .S({zero_ge_thresh_carry_i_3_n_0,zero_ge_thresh_carry_i_4_n_0,zero_ge_thresh_carry_i_5_n_0,zero_ge_thresh_carry_i_6_n_0})); CARRY4 zero_ge_thresh_carry__0 (.CI(zero_ge_thresh_carry_n_0), .CO({NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED[3:1],zero_ge_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,zero_r_reg__0[9]}), .O(NLW_zero_ge_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,zero_ge_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry__0_i_1 (.I0(zero_r_reg__0[8]), .I1(zero_r_reg__0[9]), .O(zero_ge_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h8)) zero_ge_thresh_carry_i_1 (.I0(zero_r_reg__0[4]), .I1(zero_r_reg__0[5]), .O(zero_ge_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) zero_ge_thresh_carry_i_2 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(zero_ge_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h8)) zero_ge_thresh_carry_i_3 (.I0(zero_r_reg__0[6]), .I1(zero_r_reg__0[7]), .O(zero_ge_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry_i_4 (.I0(zero_r_reg__0[5]), .I1(zero_r_reg__0[4]), .O(zero_ge_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry_i_5 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[3]), .O(zero_ge_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) zero_ge_thresh_carry_i_6 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(zero_ge_thresh_carry_i_6_n_0)); CARRY4 zero_le_half_thresh_carry (.CI(1'b0), .CO({zero_le_half_thresh_carry_n_0,zero_le_half_thresh_carry_n_1,zero_le_half_thresh_carry_n_2,zero_le_half_thresh_carry_n_3}), .CYINIT(1'b1), .DI({zero_le_half_thresh_carry_i_1_n_0,zero_le_half_thresh_carry_i_2_n_0,1'b0,zero_le_half_thresh_carry_i_3_n_0}), .O(NLW_zero_le_half_thresh_carry_O_UNCONNECTED[3:0]), .S({zero_le_half_thresh_carry_i_4_n_0,zero_le_half_thresh_carry_i_5_n_0,zero_le_half_thresh_carry_i_6_n_0,zero_le_half_thresh_carry_i_7_n_0})); CARRY4 zero_le_half_thresh_carry__0 (.CI(zero_le_half_thresh_carry_n_0), .CO({NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],zero_le_half_thresh}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,zero_le_half_thresh_carry__0_i_1_n_0})); LUT2 #( .INIT(4'h1)) zero_le_half_thresh_carry__0_i_1 (.I0(zero_r_reg__0[8]), .I1(zero_r_reg__0[9]), .O(zero_le_half_thresh_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h7)) zero_le_half_thresh_carry_i_1 (.I0(zero_r_reg__0[7]), .I1(zero_r_reg__0[6]), .O(zero_le_half_thresh_carry_i_1_n_0)); LUT2 #( .INIT(4'h7)) zero_le_half_thresh_carry_i_2 (.I0(zero_r_reg__0[5]), .I1(zero_r_reg__0[4]), .O(zero_le_half_thresh_carry_i_2_n_0)); LUT2 #( .INIT(4'h7)) zero_le_half_thresh_carry_i_3 (.I0(zero_r_reg__0[0]), .I1(zero_r_reg__0[1]), .O(zero_le_half_thresh_carry_i_3_n_0)); LUT2 #( .INIT(4'h8)) zero_le_half_thresh_carry_i_4 (.I0(zero_r_reg__0[6]), .I1(zero_r_reg__0[7]), .O(zero_le_half_thresh_carry_i_4_n_0)); LUT2 #( .INIT(4'h8)) zero_le_half_thresh_carry_i_5 (.I0(zero_r_reg__0[4]), .I1(zero_r_reg__0[5]), .O(zero_le_half_thresh_carry_i_5_n_0)); LUT2 #( .INIT(4'h1)) zero_le_half_thresh_carry_i_6 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[3]), .O(zero_le_half_thresh_carry_i_6_n_0)); LUT2 #( .INIT(4'h8)) zero_le_half_thresh_carry_i_7 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(zero_le_half_thresh_carry_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair439" *) LUT1 #( .INIT(2'h1)) \zero_r[0]_i_1 (.I0(zero_r_reg__0[0]), .O(\zero_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair439" *) LUT2 #( .INIT(4'h6)) \zero_r[1]_i_1 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair436" *) LUT3 #( .INIT(8'h6A)) \zero_r[2]_i_1 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[0]), .I2(zero_r_reg__0[1]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair424" *) LUT4 #( .INIT(16'h6AAA)) \zero_r[3]_i_1 (.I0(zero_r_reg__0[3]), .I1(zero_r_reg__0[1]), .I2(zero_r_reg__0[0]), .I3(zero_r_reg__0[2]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair424" *) LUT5 #( .INIT(32'h6AAAAAAA)) \zero_r[4]_i_1 (.I0(zero_r_reg__0[4]), .I1(zero_r_reg__0[2]), .I2(zero_r_reg__0[0]), .I3(zero_r_reg__0[1]), .I4(zero_r_reg__0[3]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \zero_r[5]_i_1 (.I0(zero_r_reg__0[5]), .I1(zero_r_reg__0[3]), .I2(zero_r_reg__0[1]), .I3(zero_r_reg__0[0]), .I4(zero_r_reg__0[2]), .I5(zero_r_reg__0[4]), .O(p_0_in__1[5])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \zero_r[6]_i_1 (.I0(zero_r_reg__0[6]), .I1(zero_r_reg__0[4]), .I2(zero_r_reg__0[5]), .I3(zero_r_reg__0[3]), .I4(\zero_r[6]_i_2_n_0 ), .I5(zero_r_reg__0[2]), .O(p_0_in__1[6])); (* SOFT_HLUTNM = "soft_lutpair436" *) LUT2 #( .INIT(4'h8)) \zero_r[6]_i_2 (.I0(zero_r_reg__0[1]), .I1(zero_r_reg__0[0]), .O(\zero_r[6]_i_2_n_0 )); LUT3 #( .INIT(8'h6A)) \zero_r[7]_i_1 (.I0(zero_r_reg__0[7]), .I1(\zero_r[9]_i_8_n_0 ), .I2(zero_r_reg__0[6]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair426" *) LUT4 #( .INIT(16'h6AAA)) \zero_r[8]_i_1 (.I0(zero_r_reg__0[8]), .I1(zero_r_reg__0[6]), .I2(zero_r_reg__0[7]), .I3(\zero_r[9]_i_8_n_0 ), .O(p_0_in__1[8])); (* SOFT_HLUTNM = "soft_lutpair426" *) LUT5 #( .INIT(32'h6AAAAAAA)) \zero_r[9]_i_3 (.I0(zero_r_reg__0[9]), .I1(zero_r_reg__0[7]), .I2(\zero_r[9]_i_8_n_0 ), .I3(zero_r_reg__0[6]), .I4(zero_r_reg__0[8]), .O(p_0_in__1[9])); LUT4 #( .INIT(16'h0002)) \zero_r[9]_i_6 (.I0(phy_rddata_en_r1_reg_0), .I1(\rd_victim_sel_r_reg[1]_1 ), .I2(\rd_victim_sel_r_reg[1]_0 ), .I3(\rd_victim_sel_r_reg[2]_0 ), .O(\samps_r_reg[0]_0 )); LUT6 #( .INIT(64'h8000000000000000)) \zero_r[9]_i_8 (.I0(zero_r_reg__0[2]), .I1(zero_r_reg__0[0]), .I2(zero_r_reg__0[1]), .I3(zero_r_reg__0[3]), .I4(zero_r_reg__0[5]), .I5(zero_r_reg__0[4]), .O(\zero_r[9]_i_8_n_0 )); FDRE \zero_r_reg[0] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(\zero_r[0]_i_1_n_0 ), .Q(zero_r_reg__0[0]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[1] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[1]), .Q(zero_r_reg__0[1]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[2] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[2]), .Q(zero_r_reg__0[2]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[3] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[3]), .Q(zero_r_reg__0[3]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[4] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[4]), .Q(zero_r_reg__0[4]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[5] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[5]), .Q(zero_r_reg__0[5]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[6] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[6]), .Q(zero_r_reg__0[6]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[7] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[7]), .Q(zero_r_reg__0[7]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[8] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[8]), .Q(zero_r_reg__0[8]), .R(\sm_r_reg[0]_0 )); FDRE \zero_r_reg[9] (.C(CLK), .CE(\rd_victim_sel_r_reg[0]_0 ), .D(p_0_in__1[9]), .Q(zero_r_reg__0[9]), .R(\sm_r_reg[0]_0 )); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_oclkdelay_cal (O, ocal_last_byte_done_reg, complex_oclk_calib_resume, ocd_prech_req, complex_ocal_num_samples_done_r, po_stg23_incdec, po_en_stg23, phy_rddata_en_1, wrlvl_final_mux_reg, lim2init_prech_req, done_r_reg, \samps_r_reg[9] , oclkdelay_center_calib_start_r_reg, D_po_sel_fine_oclk_delay125_out, \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \po_counter_read_val_reg[8]_1 , \resume_wait_r_reg[5] , \po_counter_read_val_reg[8]_2 , \po_counter_read_val_reg[8]_3 , \po_counter_read_val_reg[8]_4 , \po_counter_read_val_reg[8]_5 , complex_ocal_ref_req, stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] , \stg2_target_r_reg[8] , \stg3_tap_cnt_reg[2] , \byte_r_reg[1] , \byte_r_reg[0] , \stg2_tap_cnt_reg[3] , \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , complex_ocal_rd_victim_sel, \zero2fuzz_r_reg[0] , sr_valid_r108_out, \init_state_r_reg[4] , \init_state_r_reg[2] , \init_state_r_reg[0] , \init_state_r_reg[5] , \init_state_r_reg[5]_0 , \init_state_r_reg[6] , \init_state_r_reg[5]_1 , \init_state_r_reg[4]_0 , ocal_last_byte_done_reg_0, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \cal2_state_r_reg[0] , S, \qcntr_r_reg[0] , CLK, rstdiv0_sync_r1_reg_rep__20, poc_sample_pd, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__9, phy_rddata_en, Q, calib_in_common, \calib_zero_inputs_reg[1] , rstdiv0_sync_r1_reg_rep__26, rstdiv0_sync_r1_reg_rep__26_0, oclkdelay_calib_start_int_reg, prech_done, rd_active_r2, rstdiv0_sync_r1_reg_rep__25, \sm_r_reg[0]_0 , rd_active_r1, \gen_byte_sel_div1.calib_in_common_reg , ck_addr_cmd_delay_done, mpr_rdlvl_done_r_reg, \gen_byte_sel_div1.calib_in_common_reg_0 , \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , \wl_po_fine_cnt_reg[17] , \byte_r_reg[0]_0 , D, \po_counter_read_val_reg[2] , \stg2_tap_cnt_reg[2] , \wl_po_fine_cnt_reg[3] , \wl_po_fine_cnt_reg[14] , \wl_po_fine_cnt_reg[18] , rstdiv0_sync_r1_reg_rep__26_1, rstdiv0_sync_r1_reg_rep__26_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , rdlvl_stg1_start_reg, \cnt_shift_r_reg[0] , \init_state_r_reg[0]_0 , prbs_rdlvl_done_reg, \init_state_r_reg[4]_1 , \init_state_r_reg[0]_1 , wrlvl_final_mux, oclkdelay_int_ref_req_reg, prech_req_posedge_r_reg, cnt_cmd_done_r, prbs_rdlvl_done_reg_rep, ocal_last_byte_done, \po_stg2_wrcal_cnt_reg[0] , wr_level_done_reg, oclkdelay_calib_done_r_reg, pi_stg2_rdlvl_cnt, \po_stg2_wrcal_cnt_reg[1] , wrlvl_byte_done, \wl_po_fine_cnt_reg[23] , \stg3_r_reg[0] , psdone, rstdiv0_sync_r1_reg_rep, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__19, rstdiv0_sync_r1_reg_rep__11, \po_counter_read_val_reg[5] , \byte_r_reg[0]_1 , rstdiv0_sync_r1_reg_rep__2, oclkdelay_calib_start_int_reg_0, pd_out); output [3:0]O; output ocal_last_byte_done_reg; output complex_oclk_calib_resume; output ocd_prech_req; output complex_ocal_num_samples_done_r; output po_stg23_incdec; output po_en_stg23; output phy_rddata_en_1; output wrlvl_final_mux_reg; output lim2init_prech_req; output done_r_reg; output \samps_r_reg[9] ; output oclkdelay_center_calib_start_r_reg; output D_po_sel_fine_oclk_delay125_out; output \po_counter_read_val_reg[8] ; output \po_counter_read_val_reg[8]_0 ; output \po_counter_read_val_reg[8]_1 ; output \resume_wait_r_reg[5] ; output \po_counter_read_val_reg[8]_2 ; output \po_counter_read_val_reg[8]_3 ; output \po_counter_read_val_reg[8]_4 ; output \po_counter_read_val_reg[8]_5 ; output complex_ocal_ref_req; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; output [2:0]\stg2_target_r_reg[8] ; output [2:0]\stg3_tap_cnt_reg[2] ; output \byte_r_reg[1] ; output \byte_r_reg[0] ; output [2:0]\stg2_tap_cnt_reg[3] ; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [2:0]complex_ocal_rd_victim_sel; output [0:0]\zero2fuzz_r_reg[0] ; output sr_valid_r108_out; output \init_state_r_reg[4] ; output \init_state_r_reg[2] ; output \init_state_r_reg[0] ; output \init_state_r_reg[5] ; output \init_state_r_reg[5]_0 ; output \init_state_r_reg[6] ; output \init_state_r_reg[5]_1 ; output \init_state_r_reg[4]_0 ; output ocal_last_byte_done_reg_0; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \cal2_state_r_reg[0] ; output [0:0]S; output [0:0]\qcntr_r_reg[0] ; input CLK; input rstdiv0_sync_r1_reg_rep__20; input poc_sample_pd; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__9; input phy_rddata_en; input [1:0]Q; input calib_in_common; input [1:0]\calib_zero_inputs_reg[1] ; input rstdiv0_sync_r1_reg_rep__26; input rstdiv0_sync_r1_reg_rep__26_0; input oclkdelay_calib_start_int_reg; input prech_done; input rd_active_r2; input rstdiv0_sync_r1_reg_rep__25; input [0:0]\sm_r_reg[0]_0 ; input rd_active_r1; input \gen_byte_sel_div1.calib_in_common_reg ; input ck_addr_cmd_delay_done; input mpr_rdlvl_done_r_reg; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \wl_po_fine_cnt_reg[17] ; input \byte_r_reg[0]_0 ; input [2:0]D; input \po_counter_read_val_reg[2] ; input \stg2_tap_cnt_reg[2] ; input \wl_po_fine_cnt_reg[3] ; input [1:0]\wl_po_fine_cnt_reg[14] ; input \wl_po_fine_cnt_reg[18] ; input rstdiv0_sync_r1_reg_rep__26_1; input rstdiv0_sync_r1_reg_rep__26_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input rdlvl_stg1_start_reg; input \cnt_shift_r_reg[0] ; input \init_state_r_reg[0]_0 ; input prbs_rdlvl_done_reg; input [2:0]\init_state_r_reg[4]_1 ; input \init_state_r_reg[0]_1 ; input wrlvl_final_mux; input oclkdelay_int_ref_req_reg; input prech_req_posedge_r_reg; input cnt_cmd_done_r; input prbs_rdlvl_done_reg_rep; input ocal_last_byte_done; input \po_stg2_wrcal_cnt_reg[0] ; input wr_level_done_reg; input oclkdelay_calib_done_r_reg; input [1:0]pi_stg2_rdlvl_cnt; input \po_stg2_wrcal_cnt_reg[1] ; input wrlvl_byte_done; input [7:0]\wl_po_fine_cnt_reg[23] ; input \stg3_r_reg[0] ; input psdone; input rstdiv0_sync_r1_reg_rep; input rstdiv0_sync_r1_reg_rep__0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [0:0]rstdiv0_sync_r1_reg_rep__11; input [5:0]\po_counter_read_val_reg[5] ; input [63:0]\byte_r_reg[0]_1 ; input rstdiv0_sync_r1_reg_rep__2; input oclkdelay_calib_start_int_reg_0; input pd_out; wire CLK; wire [2:0]D; wire D_po_sel_fine_oclk_delay125_out; wire [3:0]O; wire [1:0]Q; wire [0:0]S; wire [1:0]agg_samp_r; wire \byte_r_reg[0] ; wire \byte_r_reg[0]_0 ; wire [63:0]\byte_r_reg[0]_1 ; wire \byte_r_reg[1] ; wire \cal2_state_r_reg[0] ; wire calib_in_common; wire [1:0]\calib_zero_inputs_reg[1] ; wire ck_addr_cmd_delay_done; wire cnt_cmd_done_r; wire \cnt_shift_r_reg[0] ; wire complex_ocal_num_samples_done_r; wire [2:0]complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_oclk_calib_resume; wire dec_po_ns; wire done_r_reg; wire f2z_ns5_out; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire inc_po_ns; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[2] ; wire \init_state_r_reg[4] ; wire \init_state_r_reg[4]_0 ; wire [2:0]\init_state_r_reg[4]_1 ; wire \init_state_r_reg[5] ; wire \init_state_r_reg[5]_0 ; wire \init_state_r_reg[5]_1 ; wire \init_state_r_reg[6] ; wire lim2init_prech_req; wire lim2poc_ktap_right; wire lim2poc_rdy; wire lim2stg2_dec; wire lim2stg2_inc; wire lim2stg3_dec; wire lim2stg3_inc; wire lim_start; wire lim_start_r; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mpr_rdlvl_done_r_reg; wire [1:0]ninety_offsets; wire o2f_ns1_out; wire ocal_last_byte_done; wire ocal_last_byte_done_reg; wire ocal_last_byte_done_reg_0; wire ocd_cntlr2stg2_dec_r; wire ocd_prech_req; wire oclk_center_write_resume; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_start_int_reg; wire oclkdelay_calib_start_int_reg_0; wire oclkdelay_center_calib_start_r_reg; wire oclkdelay_int_ref_req_reg; wire pd_out; wire phy_rddata_en; wire phy_rddata_en_1; wire [1:0]pi_stg2_rdlvl_cnt; wire \po_counter_read_val_reg[2] ; wire [5:0]\po_counter_read_val_reg[5] ; wire \po_counter_read_val_reg[8] ; wire \po_counter_read_val_reg[8]_0 ; wire \po_counter_read_val_reg[8]_1 ; wire \po_counter_read_val_reg[8]_2 ; wire \po_counter_read_val_reg[8]_3 ; wire \po_counter_read_val_reg[8]_4 ; wire \po_counter_read_val_reg[8]_5 ; wire po_en_stg23; wire po_rdy; wire po_stg23_incdec; wire \po_stg2_wrcal_cnt_reg[0] ; wire \po_stg2_wrcal_cnt_reg[1] ; wire poc_sample_pd; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prech_done; wire prech_req_posedge_r_reg; wire [1:0]prev_samp_r; wire prev_samp_valid_r; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire rd_active_r1; wire rd_active_r2; wire rdlvl_stg1_start_reg; wire reset_scan; wire \resume_wait_r_reg[5] ; wire [5:0]rise_lead_right; wire [5:0]rise_trail_right; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__26_1; wire rstdiv0_sync_r1_reg_rep__26_2; wire rstdiv0_sync_r1_reg_rep__9; wire samp_done; wire samp_done_ns8_out; wire \samps_r_reg[9] ; wire scan_right; wire scanning_right; wire setup_po; wire [1:1]sm_r; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire sr_valid_r108_out; wire \stg2_tap_cnt_reg[0] ; wire \stg2_tap_cnt_reg[2] ; wire [2:0]\stg2_tap_cnt_reg[3] ; wire [2:0]\stg2_target_r_reg[8] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire [2:0]\stg3_tap_cnt_reg[2] ; wire u_ocd_cntlr_n_10; wire u_ocd_cntlr_n_11; wire u_ocd_cntlr_n_12; wire u_ocd_cntlr_n_13; wire u_ocd_cntlr_n_14; wire u_ocd_cntlr_n_15; wire u_ocd_cntlr_n_16; wire u_ocd_cntlr_n_17; wire u_ocd_cntlr_n_18; wire u_ocd_cntlr_n_19; wire u_ocd_cntlr_n_20; wire u_ocd_cntlr_n_9; wire u_ocd_data_n_0; wire u_ocd_data_n_1; wire u_ocd_data_n_2; wire u_ocd_edge_n_1; wire u_ocd_edge_n_10; wire u_ocd_edge_n_2; wire u_ocd_edge_n_3; wire u_ocd_edge_n_7; wire u_ocd_lim_n_19; wire u_ocd_lim_n_20; wire u_ocd_lim_n_21; wire u_ocd_lim_n_22; wire u_ocd_lim_n_23; wire u_ocd_lim_n_24; wire u_ocd_lim_n_25; wire u_ocd_lim_n_26; wire u_ocd_lim_n_27; wire u_ocd_lim_n_28; wire u_ocd_lim_n_29; wire u_ocd_lim_n_30; wire u_ocd_lim_n_31; wire u_ocd_lim_n_32; wire u_ocd_lim_n_9; wire u_ocd_mux_n_11; wire u_ocd_po_cntlr_n_11; wire u_ocd_po_cntlr_n_12; wire u_ocd_po_cntlr_n_13; wire u_ocd_po_cntlr_n_14; wire u_ocd_po_cntlr_n_15; wire u_ocd_po_cntlr_n_16; wire u_ocd_po_cntlr_n_17; wire u_ocd_po_cntlr_n_20; wire u_ocd_po_cntlr_n_22; wire u_ocd_po_cntlr_n_23; wire u_ocd_po_cntlr_n_27; wire u_ocd_po_cntlr_n_28; wire u_ocd_po_cntlr_n_29; wire u_ocd_po_cntlr_n_30; wire u_ocd_po_cntlr_n_31; wire u_ocd_po_cntlr_n_32; wire u_ocd_po_cntlr_n_33; wire u_ocd_po_cntlr_n_34; wire u_ocd_po_cntlr_n_35; wire u_ocd_po_cntlr_n_48; wire u_ocd_po_cntlr_n_49; wire u_ocd_po_cntlr_n_50; wire u_ocd_po_cntlr_n_51; wire u_ocd_po_cntlr_n_7; wire u_ocd_samp_n_10; wire u_ocd_samp_n_14; wire u_ocd_samp_n_16; wire u_ocd_samp_n_20; wire u_ocd_samp_n_21; wire u_ocd_samp_n_3; wire u_ocd_samp_n_4; wire u_ocd_samp_n_5; wire u_ocd_samp_n_6; wire u_ocd_samp_n_7; wire u_poc_n_0; wire u_poc_n_1; wire u_poc_n_16; wire u_poc_n_17; wire u_poc_n_2; wire use_noise_window; wire [1:0]\wl_po_fine_cnt_reg[14] ; wire \wl_po_fine_cnt_reg[17] ; wire \wl_po_fine_cnt_reg[18] ; wire [7:0]\wl_po_fine_cnt_reg[23] ; wire \wl_po_fine_cnt_reg[3] ; wire wr_level_done_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; wire wrlvl_byte_done; wire wrlvl_final_mux; wire wrlvl_final_mux_reg; wire [5:1]zero2fuzz_r0; wire [0:0]\zero2fuzz_r_reg[0] ; ddr3_if_mig_7series_v4_0_ddr_phy_ocd_cntlr u_ocd_cntlr (.CLK(CLK), .D({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}), .\byte_r_reg[0]_0 (\byte_r_reg[0] ), .\byte_r_reg[1]_0 (\byte_r_reg[1] ), .\cal2_state_r_reg[0] (\cal2_state_r_reg[0] ), .cnt_cmd_done_r(cnt_cmd_done_r), .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ), .complex_ocal_ref_req(complex_ocal_ref_req), .\data_cnt_r_reg[7] (u_ocd_samp_n_3), .done_r_reg(u_ocd_cntlr_n_18), .done_r_reg_0(done_r_reg), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\gen_byte_sel_div1.byte_sel_cnt_reg[0] ), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\gen_byte_sel_div1.byte_sel_cnt_reg[1] ), .\init_state_r_reg[0] (\init_state_r_reg[0]_1 ), .\init_state_r_reg[2] (\init_state_r_reg[2] ), .\init_state_r_reg[2]_0 (\init_state_r_reg[4]_1 [1:0]), .\init_state_r_reg[5] (\init_state_r_reg[5] ), .lim_start(lim_start), .lim_start_r(lim_start_r), .ocal_last_byte_done(ocal_last_byte_done), .ocal_last_byte_done_reg(ocal_last_byte_done_reg_0), .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r), .oclk_calib_resume_r_reg(complex_oclk_calib_resume), .oclkdelay_calib_done_r_reg_0(oclkdelay_calib_done_r_reg), .oclkdelay_calib_start_int_reg(oclkdelay_calib_start_int_reg), .oclkdelay_calib_start_int_reg_0(oclkdelay_calib_start_int_reg_0), .oclkdelay_center_calib_done_r_reg(ocal_last_byte_done_reg), .phy_rddata_en(phy_rddata_en), .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt), .\po_counter_read_val_reg[2] (\po_counter_read_val_reg[2] ), .po_rdy(po_rdy), .\po_stg2_wrcal_cnt_reg[0] (\po_stg2_wrcal_cnt_reg[0] ), .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ), .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg), .prech_done(prech_done), .prech_req_posedge_r_reg(prech_req_posedge_r_reg), .prech_req_r_reg(ocd_prech_req), .prech_req_r_reg_0(lim2init_prech_req), .rd_active_r1(rd_active_r1), .rd_active_r1_reg(phy_rddata_en_1), .\rd_victim_sel_r_reg[0] (u_ocd_cntlr_n_19), .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg), .reset_scan(reset_scan), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26_0), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\simp_stg3_final_r_reg[10] (u_ocd_po_cntlr_n_30), .\simp_stg3_final_r_reg[11] (u_ocd_cntlr_n_15), .\simp_stg3_final_r_reg[12] (u_ocd_po_cntlr_n_33), .\simp_stg3_final_r_reg[16] (u_ocd_po_cntlr_n_50), .\simp_stg3_final_r_reg[17] (u_ocd_cntlr_n_17), .\simp_stg3_final_r_reg[17]_0 (u_ocd_po_cntlr_n_28), .\simp_stg3_final_r_reg[19] (u_ocd_po_cntlr_n_32), .\simp_stg3_final_r_reg[23] (u_ocd_cntlr_n_14), .\simp_stg3_final_r_reg[2] (u_ocd_po_cntlr_n_51), .\simp_stg3_final_r_reg[5] (u_ocd_cntlr_n_16), .\simp_stg3_final_r_reg[8] (u_ocd_po_cntlr_n_31), .sr_valid_r108_out(sr_valid_r108_out), .\stg3_init_val_reg[3] (u_ocd_cntlr_n_20), .wr_level_done_reg(wr_level_done_reg), .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ), .wrlvl_byte_done(wrlvl_byte_done), .wrlvl_final_mux_reg(wrlvl_final_mux_reg)); ddr3_if_mig_7series_v4_0_ddr_phy_ocd_data u_ocd_data (.CLK(CLK), .E(u_ocd_data_n_0), .agg_samp_r(agg_samp_r), .\byte_r_reg[0] (\byte_r_reg[0]_1 ), .\rd_victim_sel_r_reg[0] (u_ocd_samp_n_7), .\zero_r_reg[9] (u_ocd_data_n_1), .\zero_r_reg[9]_0 (u_ocd_data_n_2)); ddr3_if_mig_7series_v4_0_ddr_phy_ocd_edge u_ocd_edge (.CLK(CLK), .D({zero2fuzz_r0,\zero2fuzz_r_reg[0] }), .E(u_ocd_samp_n_16), .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}), .dec_po_ns(dec_po_ns), .f2o_r_reg_0(u_ocd_edge_n_3), .inc_po_ns(inc_po_ns), .\ninety_offsets_final_r_reg[0] (u_ocd_edge_n_2), .\ninety_offsets_final_r_reg[0]_0 (u_ocd_edge_n_10), .\ninety_offsets_final_r_reg[1] (u_ocd_edge_n_7), .o2f_r_reg_0(u_ocd_edge_n_1), .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7), .prev_samp_r(prev_samp_r), .prev_samp_valid_r(prev_samp_valid_r), .rd_active_r1(rd_active_r1), .rd_active_r1_reg(u_ocd_samp_n_5), .rd_active_r1_reg_0(u_ocd_samp_n_6), .reset_scan(reset_scan), .reset_scan_r_reg(u_ocd_samp_n_14), .samp_done(samp_done), .samp_done_r_reg(u_ocd_samp_n_4), .\samp_result_r_reg[0] (u_ocd_samp_n_20), .\samp_result_r_reg[1] (u_ocd_samp_n_21), .scan_right(scan_right), .scanning_right(scanning_right), .scanning_right_r_reg(u_ocd_po_cntlr_n_22), .scanning_right_r_reg_0(u_ocd_po_cntlr_n_23), .\stg3_left_lim_reg[5] ({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}), .\stg3_right_lim_reg[5] ({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32})); ddr3_if_mig_7series_v4_0_ddr_phy_ocd_lim u_ocd_lim (.CLK(CLK), .D(D), .Q(rise_trail_right), .\byte_r_reg[0] (\byte_r_reg[0]_0 ), .cnt_cmd_done_r(cnt_cmd_done_r), .done_r_reg_0(done_r_reg), .done_r_reg_1(u_poc_n_0), .\init_state_r_reg[4] (\init_state_r_reg[4]_0 ), .\init_state_r_reg[5] (\init_state_r_reg[5]_1 ), .\init_state_r_reg[6] (\init_state_r_reg[6] ), .lim2poc_ktap_right(lim2poc_ktap_right), .lim2poc_rdy(lim2poc_rdy), .lim2stg2_dec(lim2stg2_dec), .lim2stg2_inc(lim2stg2_inc), .lim2stg3_dec(lim2stg3_dec), .lim2stg3_inc(lim2stg3_inc), .lim_start(lim_start), .lim_start_r(lim_start_r), .lim_start_r_reg_0(u_ocd_cntlr_n_18), .\mmcm_current_reg[0]_0 (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0]_0 (\mmcm_init_trail_reg[0] ), .o2f_r_reg(u_ocd_edge_n_1), .ocd_prech_req_r_reg(ocd_prech_req), .oclk_center_write_resume(oclk_center_write_resume), .oclkdelay_calib_done_r_reg({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_po_cntlr_n_29,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}), .oclkdelay_center_calib_start_r_reg(u_ocd_lim_n_26), .oclkdelay_center_calib_start_r_reg_0({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32}), .po_rdy(po_rdy), .po_stg23_sel_r_reg(u_ocd_lim_n_9), .\po_wait_r_reg[0] (u_ocd_mux_n_11), .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep), .prech_done(prech_done), .prech_req_r_reg_0(lim2init_prech_req), .\rise_lead_r_reg[5] (rise_lead_right), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_1), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .scan_right(scan_right), .scanning_right(scanning_right), .scanning_right_r_reg(u_ocd_lim_n_19), .scanning_right_r_reg_0({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}), .\sm_r_reg[2] (u_ocd_po_cntlr_n_20), .\stg2_tap_cnt_reg[0]_0 (\stg2_tap_cnt_reg[0] ), .\stg2_tap_cnt_reg[2]_0 (\stg2_tap_cnt_reg[2] ), .\stg2_tap_cnt_reg[3]_0 (\stg2_tap_cnt_reg[3] ), .stg3_dec2init_val_r_reg_0(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg_0(stg3_inc2init_val_r_reg), .\stg3_r_reg[5] ({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}), .\stg3_tap_cnt_reg[2]_0 (\stg3_tap_cnt_reg[2] ), .\wl_po_fine_cnt_reg[14] (\wl_po_fine_cnt_reg[14] ), .\wl_po_fine_cnt_reg[17] (\wl_po_fine_cnt_reg[17] ), .\wl_po_fine_cnt_reg[18] (\wl_po_fine_cnt_reg[18] ), .\wl_po_fine_cnt_reg[3] (\wl_po_fine_cnt_reg[3] )); ddr3_if_mig_7series_v4_0_ddr_phy_ocd_mux u_ocd_mux (.CLK(CLK), .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out), .Q(Q), .calib_in_common(calib_in_common), .\calib_zero_inputs_reg[1] (\calib_zero_inputs_reg[1] ), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .\gen_byte_sel_div1.calib_in_common_reg (\gen_byte_sel_div1.calib_in_common_reg ), .\gen_byte_sel_div1.calib_in_common_reg_0 (\gen_byte_sel_div1.calib_in_common_reg_0 ), .\gen_byte_sel_div1.calib_in_common_reg_1 (\gen_byte_sel_div1.calib_in_common_reg_1 ), .\gen_byte_sel_div1.calib_in_common_reg_2 (\gen_byte_sel_div1.calib_in_common_reg_2 ), .mpr_rdlvl_done_r_reg(mpr_rdlvl_done_r_reg), .oclkdelay_calib_done_r_reg(wrlvl_final_mux_reg), .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8] ), .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_0 ), .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_1 ), .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_2 ), .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_3 ), .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_4 ), .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_5 ), .po_rdy(po_rdy), .po_stg23_incdec(po_stg23_incdec), .po_stg23_sel_r_reg_0(u_ocd_mux_n_11), .\po_wait_r_reg[3]_0 (po_en_stg23), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .setup_po(setup_po), .stg2_dec_req_r_reg(u_ocd_po_cntlr_n_27), .stg3_dec_req_r_reg(u_ocd_lim_n_9), .stg3_inc_req_r_reg(u_ocd_po_cntlr_n_17)); ddr3_if_mig_7series_v4_0_ddr_phy_ocd_po_cntlr u_ocd_po_cntlr (.CLK(CLK), .D({zero2fuzz_r0,\zero2fuzz_r_reg[0] }), .E(\resume_wait_r_reg[5] ), .O(O), .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}), .S(S), .\byte_r_reg[0] (\byte_r_reg[0]_0 ), .\byte_r_reg[0]_0 (\byte_r_reg[0] ), .\byte_r_reg[0]_1 (u_ocd_cntlr_n_14), .\byte_r_reg[0]_2 (u_ocd_cntlr_n_15), .\byte_r_reg[0]_3 (u_ocd_cntlr_n_16), .\byte_r_reg[1] (\byte_r_reg[1] ), .\byte_r_reg[1]_0 (u_ocd_cntlr_n_17), .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r), .dec_po_ns(dec_po_ns), .done_r_reg(u_poc_n_0), .edge_aligned_r_reg(u_ocd_po_cntlr_n_49), .edge_aligned_r_reg_0(u_poc_n_1), .f2o_r_reg(u_ocd_edge_n_7), .f2o_r_reg_0(u_ocd_edge_n_10), .f2z_ns5_out(f2z_ns5_out), .f2z_r_reg(u_ocd_po_cntlr_n_23), .f2z_r_reg_0(u_ocd_edge_n_2), .inc_po_ns(inc_po_ns), .\init_state_r_reg[0] (\init_state_r_reg[0] ), .lim2poc_ktap_right(lim2poc_ktap_right), .lim2poc_rdy(lim2poc_rdy), .lim2stg2_dec(lim2stg2_dec), .lim2stg2_inc(lim2stg2_inc), .lim2stg3_dec(lim2stg3_dec), .lim2stg3_inc(lim2stg3_inc), .ninety_offsets(ninety_offsets), .o2f_ns1_out(o2f_ns1_out), .o2f_r_reg(u_ocd_po_cntlr_n_22), .o2f_r_reg_0(u_ocd_edge_n_1), .ocal_last_byte_done_reg(ocal_last_byte_done_reg), .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r), .oclk_center_write_resume(oclk_center_write_resume), .oclkdelay_calib_done_r_reg(u_ocd_cntlr_n_20), .oclkdelay_calib_done_r_reg_0(wrlvl_final_mux_reg), .oclkdelay_center_calib_start_r_reg_0(oclkdelay_center_calib_start_r_reg), .oclkdelay_int_ref_req_reg(oclkdelay_int_ref_req_reg), .\po_counter_read_val_reg[5] (\po_counter_read_val_reg[5] ), .po_rdy(po_rdy), .po_stg23_incdec(po_stg23_incdec), .po_stg23_incdec_r_reg(u_ocd_po_cntlr_n_17), .po_stg23_incdec_r_reg_0(u_ocd_po_cntlr_n_27), .poc_backup_r_reg_0(u_ocd_po_cntlr_n_48), .poc_backup_r_reg_1(u_poc_n_2), .prech_req_posedge_r_reg(prech_req_posedge_r_reg), .rd_active_r2(rd_active_r2), .reset_scan(reset_scan), .\rise_trail_r_reg[5] (u_ocd_po_cntlr_n_34), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_2), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .\run_ends_r_reg[0] (u_poc_n_16), .\run_ends_r_reg[1] (u_ocd_po_cntlr_n_35), .\run_ends_r_reg[1]_0 (u_poc_n_17), .samp_done(samp_done), .samp_done_ns8_out(samp_done_ns8_out), .samp_done_r_reg(u_ocd_samp_n_10), .scan_right_r_reg(u_ocd_lim_n_19), .scanning_right(scanning_right), .scanning_right_r_reg_0(u_ocd_lim_n_26), .setup_po(setup_po), .\sm_r_reg[0]_0 (\sm_r_reg[0] ), .\sm_r_reg[0]_1 (\samps_r_reg[9] ), .\sm_r_reg[3]_0 (u_ocd_po_cntlr_n_7), .\stg2_r_reg[0]_0 (sm_r), .\stg2_target_r_reg[8]_0 (\stg2_target_r_reg[8] ), .\stg3_init_val_reg[0] (u_ocd_po_cntlr_n_33), .\stg3_init_val_reg[1] (u_ocd_po_cntlr_n_32), .\stg3_init_val_reg[2] (u_ocd_po_cntlr_n_31), .\stg3_init_val_reg[2]_0 (u_ocd_po_cntlr_n_51), .\stg3_init_val_reg[3] (u_ocd_po_cntlr_n_29), .\stg3_init_val_reg[4] (u_ocd_po_cntlr_n_30), .\stg3_init_val_reg[4]_0 (u_ocd_po_cntlr_n_50), .\stg3_init_val_reg[5] (u_ocd_po_cntlr_n_28), .\stg3_r_reg[0]_0 (\stg3_r_reg[0] ), .\two_r_reg[1]_0 (u_ocd_po_cntlr_n_20), .use_noise_window(use_noise_window), .\wl_po_fine_cnt_reg[14] (\wl_po_fine_cnt_reg[14] ), .\wl_po_fine_cnt_reg[17] (\wl_po_fine_cnt_reg[17] ), .\wl_po_fine_cnt_reg[18] (\wl_po_fine_cnt_reg[18] ), .\wl_po_fine_cnt_reg[23] (\wl_po_fine_cnt_reg[23] ), .\wl_po_fine_cnt_reg[3] (\wl_po_fine_cnt_reg[3] ), .wrlvl_final_mux(wrlvl_final_mux)); ddr3_if_mig_7series_v4_0_ddr_phy_ocd_samp u_ocd_samp (.CLK(CLK), .D({u_ocd_samp_n_5,u_ocd_samp_n_6}), .E(u_ocd_samp_n_16), .agg_samp_r(agg_samp_r), .\data_bytes_r_reg[24] (u_ocd_data_n_1), .\data_bytes_r_reg[32] (u_ocd_data_n_2), .f2o_r_reg(u_ocd_edge_n_3), .f2z_ns5_out(f2z_ns5_out), .\init_state_r_reg[0] (\init_state_r_reg[0]_0 ), .\init_state_r_reg[4] (\init_state_r_reg[4] ), .\init_state_r_reg[4]_0 (\init_state_r_reg[4]_1 [2]), .\init_state_r_reg[5] (\init_state_r_reg[5]_0 ), .o2f_ns1_out(o2f_ns1_out), .ocd_prech_req_r_reg(ocd_prech_req), .oclk_calib_resume_level_reg(complex_oclk_calib_resume), .oclk_calib_resume_r_reg_0(u_ocd_samp_n_3), .\oneeighty2fuzz_r_reg[5] (u_ocd_samp_n_14), .phy_rddata_en_r1_reg(phy_rddata_en_1), .phy_rddata_en_r1_reg_0(u_ocd_cntlr_n_19), .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg), .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep), .prech_req_r_reg(lim2init_prech_req), .prev_samp_r(prev_samp_r), .\prev_samp_r_reg[0] (u_ocd_samp_n_20), .\prev_samp_r_reg[1] (u_ocd_samp_n_21), .prev_samp_valid_r(prev_samp_valid_r), .prev_samp_valid_r_reg(u_ocd_samp_n_4), .rd_active_r1(rd_active_r1), .rd_active_r2(rd_active_r2), .\rd_victim_sel_r_reg[0]_0 (u_ocd_data_n_0), .\rd_victim_sel_r_reg[1]_0 (complex_ocal_rd_victim_sel[1]), .\rd_victim_sel_r_reg[1]_1 (complex_ocal_rd_victim_sel[0]), .\rd_victim_sel_r_reg[2]_0 (complex_ocal_rd_victim_sel[2]), .reset_scan(reset_scan), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .samp_done(samp_done), .samp_done_ns8_out(samp_done_ns8_out), .\samps_r_reg[0]_0 (u_ocd_samp_n_7), .\samps_r_reg[9]_0 (\samps_r_reg[9] ), .scanning_right(scanning_right), .scanning_right_r_reg(u_ocd_lim_n_26), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\sm_r_reg[1] (sm_r), .\stg3_r_reg[1] (u_ocd_samp_n_10)); ddr3_if_mig_7series_v4_0_poc_top u_poc (.CLK(CLK), .Q(rise_trail_right), .detect_done_r_reg(u_poc_n_0), .\mmcm_init_lead_reg[5] (rise_lead_right), .ninety_offsets(ninety_offsets), .ocd_edge_detect_rdy_r_reg(u_ocd_po_cntlr_n_35), .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7), .ocd_ktap_left_r_reg_0(u_ocd_po_cntlr_n_49), .ocd_ktap_right_r_reg(u_ocd_po_cntlr_n_34), .pd_out(pd_out), .poc_backup_r_reg(u_poc_n_2), .poc_sample_pd(poc_sample_pd), .\prev_r_reg[0] (u_poc_n_16), .\prev_r_reg[0]_0 (u_poc_n_17), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\run_ends_r_reg[1] (u_ocd_po_cntlr_n_48), .\sm_r_reg[1] (u_poc_n_1), .use_noise_window(use_noise_window)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_prbs_rdlvl (prbs_rdlvl_start_r, \row_cnt_victim_rotate.complex_row_cnt_reg[4] , prech_req_r_reg, prbs_prech_req_r, pi_en_stg2_f_timing_reg_0, prbs_pi_stg2_f_en, prbs_pi_stg2_f_incdec, A, \A[0]_0 , \A[1]_0 , no_err_win_detected_latch_reg_0, cnt_wait_state, \rdlvl_cpt_tap_cnt_reg[5]_0 , prbs_found_1st_edge_r_reg_0, \genblk8[0].left_loss_pb_reg[0]_0 , \genblk8[1].left_loss_pb_reg[6]_0 , \genblk8[2].left_loss_pb_reg[12]_0 , \genblk8[3].left_loss_pb_reg[18]_0 , \genblk8[4].left_loss_pb_reg[24]_0 , \genblk8[5].left_loss_pb_reg[30]_0 , \genblk8[6].left_loss_pb_reg[36]_0 , \genblk8[7].left_loss_pb_reg[42]_0 , \genblk8[0].right_edge_pb_reg[0]_0 , \genblk8[1].right_edge_pb_reg[6]_0 , \genblk8[2].right_edge_pb_reg[12]_0 , \genblk8[3].right_edge_pb_reg[18]_0 , \genblk8[4].right_edge_pb_reg[24]_0 , \genblk8[5].right_edge_pb_reg[30]_0 , \genblk8[6].right_edge_pb_reg[36]_0 , \genblk8[7].right_edge_pb_reg[42]_0 , fine_delay_sel_r_reg, right_edge_found_reg_0, prbs_tap_inc_r, \match_flag_or_reg[0]_0 , \largest_left_edge_reg[0]_0 , D, prbs_rdlvl_done_reg_0, \stg1_wr_rd_cnt_reg[3] , prbs_last_byte_done, reset_rd_addr, complex_init_pi_dec_done, complex_pi_incdec_done, \prbs_dqs_cnt_r_reg[2]_0 , complex_oclkdelay_calib_done_r1_reg, p_154_out, p_95_out, \genblk8[7].right_edge_pb_reg[42]_1 , p_98_out, p_103_out, p_106_out, \genblk8[5].right_edge_pb_reg[30]_1 , \genblk8[5].right_gain_pb_reg[30]_0 , p_119_out, p_122_out, p_127_out, p_130_out, \genblk8[2].right_edge_pb_reg[12]_1 , \genblk8[2].right_edge_pb_reg[12]_2 , p_143_out, p_146_out, \genblk8[0].right_edge_pb_reg[0]_1 , \genblk8[0].left_loss_pb_reg[0]_1 , Q, num_samples_done_r, prbs_state_r178_out, bit_cnt, \genblk9[0].fine_delay_incdec_pb_reg[0]_0 , right_edge_found_reg_1, \prbs_dec_tap_cnt_reg[1]_0 , reset_rd_addr0, \genblk8[7].left_edge_updated_reg[7]_0 , \rd_victim_sel_reg[2]_0 , \oclkdelay_ref_cnt_reg[0] , prbs_rdlvl_done_pulse0, \init_state_r_reg[0] , \init_state_r_reg[1] , \init_state_r_reg[0]_0 , \init_state_r_reg[1]_0 , \fine_delay_mod_reg[5] , \fine_delay_mod_reg[20] , \rdlvl_cpt_tap_cnt_reg[5]_1 , right_gain_pb, right_edge_found, no_err_win_detected_reg_0, prbs_found_1st_edge_r_reg_1, prbs_tap_en_r_reg_0, prbs_tap_en_r, fine_delay_sel_reg_0, no_err_win_detected_latch_reg_1, fine_delay_sel_reg_1, complex_pi_incdec_done_reg_0, num_samples_done_ind_reg_0, complex_pi_incdec_done_reg_1, fine_dly_error_reg_0, compare_err_latch_reg_0, \prbs_dqs_cnt_r_reg[1]_0 , prbs_rdlvl_done_reg_1, prbs_last_byte_done_reg_0, new_cnt_dqs_r_reg_0, new_cnt_dqs_r, \rd_victim_sel_reg[2]_1 , \rd_victim_sel_reg[2]_2 , \rd_victim_sel_reg[2]_3 , \fine_delay_mod_reg[26] , \genblk9[1].fine_delay_incdec_pb_reg[1]_0 , \genblk9[2].fine_delay_incdec_pb_reg[2]_0 , \genblk9[3].fine_delay_incdec_pb_reg[3]_0 , \genblk9[5].fine_delay_incdec_pb_reg[5]_0 , \genblk9[6].fine_delay_incdec_pb_reg[6]_0 , \genblk9[7].fine_delay_incdec_pb_reg[7]_0 , CLK, prbs_rdlvl_start_reg, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , rstdiv0_sync_r1_reg_rep__7, \dout_o_reg[7] , \dout_o_reg[7]_0 , \dout_o_reg[7]_1 , \dout_o_reg[7]_2 , \dout_o_reg[7]_3 , \dout_o_reg[7]_4 , \dout_o_reg[7]_5 , \dout_o_reg[7]_6 , \A[1]_1 , \A[1]_2 , \A[1]_3 , \A[1]_4 , \A[1]_5 , \A[1]_6 , \A[1]_7 , \A[1]_8 , \dout_o_reg[6] , \dout_o_reg[6]_0 , \dout_o_reg[6]_1 , \dout_o_reg[6]_2 , \dout_o_reg[6]_3 , \dout_o_reg[6]_4 , \dout_o_reg[6]_5 , \dout_o_reg[6]_6 , \A[1]_9 , \A[1]_10 , \A[1]_11 , \A[1]_12 , \A[1]_13 , \A[1]_14 , \A[1]_15 , \A[1]_16 , \dout_o_reg[5] , \dout_o_reg[5]_0 , \dout_o_reg[5]_1 , \dout_o_reg[5]_2 , \dout_o_reg[5]_3 , \dout_o_reg[5]_4 , \dout_o_reg[5]_5 , \dout_o_reg[5]_6 , \A[1]_17 , \A[1]_18 , \A[1]_19 , \A[1]_20 , \A[1]_21 , \A[1]_22 , \A[1]_23 , \A[1]_24 , \dout_o_reg[4] , \dout_o_reg[4]_0 , \dout_o_reg[4]_1 , \dout_o_reg[4]_2 , \dout_o_reg[4]_3 , \dout_o_reg[4]_4 , \dout_o_reg[4]_5 , \dout_o_reg[4]_6 , \A[1]_25 , \A[1]_26 , \A[1]_27 , \A[1]_28 , \A[1]_29 , \A[1]_30 , \A[1]_31 , \A[1]_32 , \dout_o_reg[3] , \dout_o_reg[3]_0 , \dout_o_reg[3]_1 , \dout_o_reg[3]_2 , \dout_o_reg[3]_3 , \dout_o_reg[3]_4 , \dout_o_reg[3]_5 , \dout_o_reg[3]_6 , \A[1]_33 , \A[1]_34 , \A[1]_35 , \A[1]_36 , \A[1]_37 , \A[1]_38 , \A[1]_39 , \A[1]_40 , \dout_o_reg[2] , \dout_o_reg[2]_0 , \dout_o_reg[2]_1 , \dout_o_reg[2]_2 , \dout_o_reg[2]_3 , \dout_o_reg[2]_4 , \dout_o_reg[2]_5 , \dout_o_reg[2]_6 , \A[1]_41 , \A[1]_42 , \A[1]_43 , \A[1]_44 , \A[1]_45 , \A[1]_46 , \A[1]_47 , \A[1]_48 , \dout_o_reg[1] , \dout_o_reg[1]_0 , \dout_o_reg[1]_1 , \dout_o_reg[1]_2 , \dout_o_reg[1]_3 , \dout_o_reg[1]_4 , \dout_o_reg[1]_5 , \dout_o_reg[1]_6 , \A[1]_49 , \A[1]_50 , \A[1]_51 , \A[1]_52 , \A[1]_53 , \A[1]_54 , \A[1]_55 , \A[1]_56 , \dout_o_reg[0] , \dout_o_reg[0]_0 , \dout_o_reg[0]_1 , \dout_o_reg[0]_2 , \dout_o_reg[0]_3 , \dout_o_reg[0]_4 , \dout_o_reg[0]_5 , \dout_o_reg[0]_6 , \A[1]_57 , \A[1]_58 , \A[1]_59 , \A[1]_60 , \A[1]_61 , \A[1]_62 , \A[1]_63 , \A[1]_64 , rstdiv0_sync_r1_reg_rep__8, rstdiv0_sync_r1_reg_rep__2, \prbs_state_r_reg[4]_0 , \prbs_state_r_reg[3]_0 , \genblk8[0].left_edge_found_pb_reg[0]_0 , \genblk8[1].left_edge_found_pb_reg[1]_0 , \genblk8[2].left_edge_found_pb_reg[2]_0 , \genblk8[3].left_edge_found_pb_reg[3]_0 , \genblk8[4].left_edge_found_pb_reg[4]_0 , \genblk8[5].left_edge_found_pb_reg[5]_0 , \genblk8[6].left_edge_found_pb_reg[6]_0 , \genblk8[7].left_edge_found_pb_reg[7]_0 , \genblk8[0].right_edge_found_pb_reg[0]_0 , \genblk8[1].right_edge_found_pb_reg[1]_0 , \genblk8[2].right_edge_found_pb_reg[2]_0 , \genblk8[3].right_edge_found_pb_reg[3]_0 , \genblk8[4].right_edge_found_pb_reg[4]_0 , \genblk8[5].right_edge_found_pb_reg[5]_0 , \genblk8[6].right_edge_found_pb_reg[6]_0 , \genblk8[7].right_edge_found_pb_reg[7]_0 , \prbs_state_r_reg[0]_0 , no_err_win_detected_reg_1, new_cnt_dqs_r_reg_1, \prbs_state_r_reg[0]_1 , \prbs_state_r_reg[0]_2 , \prbs_state_r_reg[4]_1 , \prbs_state_r_reg[3]_1 , \genblk8[0].left_edge_updated_reg[0]_0 , \genblk8[1].left_edge_updated_reg[1]_0 , \genblk8[2].left_edge_updated_reg[2]_0 , \genblk8[3].left_edge_updated_reg[3]_0 , \genblk8[4].left_edge_updated_reg[4]_0 , \genblk8[5].left_edge_updated_reg[5]_0 , \genblk8[6].left_edge_updated_reg[6]_0 , \genblk8[7].left_edge_updated_reg[7]_1 , \dec_cnt_reg[0]_0 , fine_dly_error_reg_1, \prbs_state_r_reg[0]_3 , prech_done_reg, prbs_tap_inc_r_reg_0, rstdiv0_sync_r1_reg_rep__9, \prbs_state_r_reg[4]_2 , \prbs_state_r_reg[4]_3 , \prbs_state_r_reg[0]_4 , \prbs_dqs_cnt_r_reg[0]_0 , \prbs_dqs_cnt_r_reg[0]_1 , \prbs_dqs_cnt_r_reg[0]_2 , rstdiv0_sync_r1_reg_rep, complex_ocal_reset_rd_addr, \calib_sel_reg[3] , \pi_counter_read_val_reg[5] , rstdiv0_sync_r1_reg_rep__24, oclkdelay_center_calib_done_r_reg, ocal_last_byte_done, prbs_rdlvl_done_r1, rdlvl_stg1_done_int_reg, wrcal_done_reg, dqs_found_done_r_reg, \num_refresh_reg[1] , wrlvl_final_mux, rdlvl_stg1_start_int, rdlvl_last_byte_done, \one_rank.stg1_wr_done_reg , \A[2]__2 , \calib_sel_reg[3]_0 , \calib_sel_reg[3]_1 , \calib_sel_reg[3]_2 , rstdiv0_sync_r1_reg_rep__23, complex_act_start, prech_done, prbs_rdlvl_start_reg_0, E, \stage_cnt_reg[1]_0 ); output prbs_rdlvl_start_r; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output prech_req_r_reg; output prbs_prech_req_r; output pi_en_stg2_f_timing_reg_0; output prbs_pi_stg2_f_en; output prbs_pi_stg2_f_incdec; output [1:0]A; output \A[0]_0 ; output \A[1]_0 ; output no_err_win_detected_latch_reg_0; output cnt_wait_state; output \rdlvl_cpt_tap_cnt_reg[5]_0 ; output prbs_found_1st_edge_r_reg_0; output \genblk8[0].left_loss_pb_reg[0]_0 ; output \genblk8[1].left_loss_pb_reg[6]_0 ; output \genblk8[2].left_loss_pb_reg[12]_0 ; output \genblk8[3].left_loss_pb_reg[18]_0 ; output \genblk8[4].left_loss_pb_reg[24]_0 ; output \genblk8[5].left_loss_pb_reg[30]_0 ; output \genblk8[6].left_loss_pb_reg[36]_0 ; output \genblk8[7].left_loss_pb_reg[42]_0 ; output \genblk8[0].right_edge_pb_reg[0]_0 ; output \genblk8[1].right_edge_pb_reg[6]_0 ; output \genblk8[2].right_edge_pb_reg[12]_0 ; output \genblk8[3].right_edge_pb_reg[18]_0 ; output \genblk8[4].right_edge_pb_reg[24]_0 ; output \genblk8[5].right_edge_pb_reg[30]_0 ; output \genblk8[6].right_edge_pb_reg[36]_0 ; output \genblk8[7].right_edge_pb_reg[42]_0 ; output fine_delay_sel_r_reg; output right_edge_found_reg_0; output prbs_tap_inc_r; output \match_flag_or_reg[0]_0 ; output \largest_left_edge_reg[0]_0 ; output [7:0]D; output prbs_rdlvl_done_reg_0; output \stg1_wr_rd_cnt_reg[3] ; output prbs_last_byte_done; output reset_rd_addr; output complex_init_pi_dec_done; output complex_pi_incdec_done; output \prbs_dqs_cnt_r_reg[2]_0 ; output complex_oclkdelay_calib_done_r1_reg; output p_154_out; output p_95_out; output \genblk8[7].right_edge_pb_reg[42]_1 ; output p_98_out; output p_103_out; output p_106_out; output \genblk8[5].right_edge_pb_reg[30]_1 ; output \genblk8[5].right_gain_pb_reg[30]_0 ; output p_119_out; output p_122_out; output p_127_out; output p_130_out; output \genblk8[2].right_edge_pb_reg[12]_1 ; output \genblk8[2].right_edge_pb_reg[12]_2 ; output p_143_out; output p_146_out; output \genblk8[0].right_edge_pb_reg[0]_1 ; output \genblk8[0].left_loss_pb_reg[0]_1 ; output [4:0]Q; output num_samples_done_r; output prbs_state_r178_out; output bit_cnt; output \genblk9[0].fine_delay_incdec_pb_reg[0]_0 ; output right_edge_found_reg_1; output [1:0]\prbs_dec_tap_cnt_reg[1]_0 ; output reset_rd_addr0; output \genblk8[7].left_edge_updated_reg[7]_0 ; output \rd_victim_sel_reg[2]_0 ; output \oclkdelay_ref_cnt_reg[0] ; output prbs_rdlvl_done_pulse0; output \init_state_r_reg[0] ; output \init_state_r_reg[1] ; output \init_state_r_reg[0]_0 ; output \init_state_r_reg[1]_0 ; output \fine_delay_mod_reg[5] ; output \fine_delay_mod_reg[20] ; output [2:0]\rdlvl_cpt_tap_cnt_reg[5]_1 ; output right_gain_pb; output right_edge_found; output no_err_win_detected_reg_0; output prbs_found_1st_edge_r_reg_1; output prbs_tap_en_r_reg_0; output prbs_tap_en_r; output fine_delay_sel_reg_0; output no_err_win_detected_latch_reg_1; output fine_delay_sel_reg_1; output complex_pi_incdec_done_reg_0; output num_samples_done_ind_reg_0; output complex_pi_incdec_done_reg_1; output fine_dly_error_reg_0; output compare_err_latch_reg_0; output \prbs_dqs_cnt_r_reg[1]_0 ; output prbs_rdlvl_done_reg_1; output prbs_last_byte_done_reg_0; output new_cnt_dqs_r_reg_0; output new_cnt_dqs_r; output \rd_victim_sel_reg[2]_1 ; output \rd_victim_sel_reg[2]_2 ; output \rd_victim_sel_reg[2]_3 ; output \fine_delay_mod_reg[26] ; output \genblk9[1].fine_delay_incdec_pb_reg[1]_0 ; output \genblk9[2].fine_delay_incdec_pb_reg[2]_0 ; output \genblk9[3].fine_delay_incdec_pb_reg[3]_0 ; output \genblk9[5].fine_delay_incdec_pb_reg[5]_0 ; output \genblk9[6].fine_delay_incdec_pb_reg[6]_0 ; output \genblk9[7].fine_delay_incdec_pb_reg[7]_0 ; input CLK; input prbs_rdlvl_start_reg; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input rstdiv0_sync_r1_reg_rep__7; input \dout_o_reg[7] ; input \dout_o_reg[7]_0 ; input \dout_o_reg[7]_1 ; input \dout_o_reg[7]_2 ; input \dout_o_reg[7]_3 ; input \dout_o_reg[7]_4 ; input \dout_o_reg[7]_5 ; input \dout_o_reg[7]_6 ; input \A[1]_1 ; input \A[1]_2 ; input \A[1]_3 ; input \A[1]_4 ; input \A[1]_5 ; input \A[1]_6 ; input \A[1]_7 ; input \A[1]_8 ; input \dout_o_reg[6] ; input \dout_o_reg[6]_0 ; input \dout_o_reg[6]_1 ; input \dout_o_reg[6]_2 ; input \dout_o_reg[6]_3 ; input \dout_o_reg[6]_4 ; input \dout_o_reg[6]_5 ; input \dout_o_reg[6]_6 ; input \A[1]_9 ; input \A[1]_10 ; input \A[1]_11 ; input \A[1]_12 ; input \A[1]_13 ; input \A[1]_14 ; input \A[1]_15 ; input \A[1]_16 ; input \dout_o_reg[5] ; input \dout_o_reg[5]_0 ; input \dout_o_reg[5]_1 ; input \dout_o_reg[5]_2 ; input \dout_o_reg[5]_3 ; input \dout_o_reg[5]_4 ; input \dout_o_reg[5]_5 ; input \dout_o_reg[5]_6 ; input \A[1]_17 ; input \A[1]_18 ; input \A[1]_19 ; input \A[1]_20 ; input \A[1]_21 ; input \A[1]_22 ; input \A[1]_23 ; input \A[1]_24 ; input \dout_o_reg[4] ; input \dout_o_reg[4]_0 ; input \dout_o_reg[4]_1 ; input \dout_o_reg[4]_2 ; input \dout_o_reg[4]_3 ; input \dout_o_reg[4]_4 ; input \dout_o_reg[4]_5 ; input \dout_o_reg[4]_6 ; input \A[1]_25 ; input \A[1]_26 ; input \A[1]_27 ; input \A[1]_28 ; input \A[1]_29 ; input \A[1]_30 ; input \A[1]_31 ; input \A[1]_32 ; input \dout_o_reg[3] ; input \dout_o_reg[3]_0 ; input \dout_o_reg[3]_1 ; input \dout_o_reg[3]_2 ; input \dout_o_reg[3]_3 ; input \dout_o_reg[3]_4 ; input \dout_o_reg[3]_5 ; input \dout_o_reg[3]_6 ; input \A[1]_33 ; input \A[1]_34 ; input \A[1]_35 ; input \A[1]_36 ; input \A[1]_37 ; input \A[1]_38 ; input \A[1]_39 ; input \A[1]_40 ; input \dout_o_reg[2] ; input \dout_o_reg[2]_0 ; input \dout_o_reg[2]_1 ; input \dout_o_reg[2]_2 ; input \dout_o_reg[2]_3 ; input \dout_o_reg[2]_4 ; input \dout_o_reg[2]_5 ; input \dout_o_reg[2]_6 ; input \A[1]_41 ; input \A[1]_42 ; input \A[1]_43 ; input \A[1]_44 ; input \A[1]_45 ; input \A[1]_46 ; input \A[1]_47 ; input \A[1]_48 ; input \dout_o_reg[1] ; input \dout_o_reg[1]_0 ; input \dout_o_reg[1]_1 ; input \dout_o_reg[1]_2 ; input \dout_o_reg[1]_3 ; input \dout_o_reg[1]_4 ; input \dout_o_reg[1]_5 ; input \dout_o_reg[1]_6 ; input \A[1]_49 ; input \A[1]_50 ; input \A[1]_51 ; input \A[1]_52 ; input \A[1]_53 ; input \A[1]_54 ; input \A[1]_55 ; input \A[1]_56 ; input \dout_o_reg[0] ; input \dout_o_reg[0]_0 ; input \dout_o_reg[0]_1 ; input \dout_o_reg[0]_2 ; input \dout_o_reg[0]_3 ; input \dout_o_reg[0]_4 ; input \dout_o_reg[0]_5 ; input \dout_o_reg[0]_6 ; input \A[1]_57 ; input \A[1]_58 ; input \A[1]_59 ; input \A[1]_60 ; input \A[1]_61 ; input \A[1]_62 ; input \A[1]_63 ; input \A[1]_64 ; input rstdiv0_sync_r1_reg_rep__8; input rstdiv0_sync_r1_reg_rep__2; input \prbs_state_r_reg[4]_0 ; input \prbs_state_r_reg[3]_0 ; input \genblk8[0].left_edge_found_pb_reg[0]_0 ; input \genblk8[1].left_edge_found_pb_reg[1]_0 ; input \genblk8[2].left_edge_found_pb_reg[2]_0 ; input \genblk8[3].left_edge_found_pb_reg[3]_0 ; input \genblk8[4].left_edge_found_pb_reg[4]_0 ; input \genblk8[5].left_edge_found_pb_reg[5]_0 ; input \genblk8[6].left_edge_found_pb_reg[6]_0 ; input \genblk8[7].left_edge_found_pb_reg[7]_0 ; input \genblk8[0].right_edge_found_pb_reg[0]_0 ; input \genblk8[1].right_edge_found_pb_reg[1]_0 ; input \genblk8[2].right_edge_found_pb_reg[2]_0 ; input \genblk8[3].right_edge_found_pb_reg[3]_0 ; input \genblk8[4].right_edge_found_pb_reg[4]_0 ; input \genblk8[5].right_edge_found_pb_reg[5]_0 ; input \genblk8[6].right_edge_found_pb_reg[6]_0 ; input \genblk8[7].right_edge_found_pb_reg[7]_0 ; input \prbs_state_r_reg[0]_0 ; input no_err_win_detected_reg_1; input new_cnt_dqs_r_reg_1; input \prbs_state_r_reg[0]_1 ; input \prbs_state_r_reg[0]_2 ; input \prbs_state_r_reg[4]_1 ; input \prbs_state_r_reg[3]_1 ; input \genblk8[0].left_edge_updated_reg[0]_0 ; input \genblk8[1].left_edge_updated_reg[1]_0 ; input \genblk8[2].left_edge_updated_reg[2]_0 ; input \genblk8[3].left_edge_updated_reg[3]_0 ; input \genblk8[4].left_edge_updated_reg[4]_0 ; input \genblk8[5].left_edge_updated_reg[5]_0 ; input \genblk8[6].left_edge_updated_reg[6]_0 ; input \genblk8[7].left_edge_updated_reg[7]_1 ; input \dec_cnt_reg[0]_0 ; input fine_dly_error_reg_1; input \prbs_state_r_reg[0]_3 ; input prech_done_reg; input prbs_tap_inc_r_reg_0; input rstdiv0_sync_r1_reg_rep__9; input \prbs_state_r_reg[4]_2 ; input \prbs_state_r_reg[4]_3 ; input \prbs_state_r_reg[0]_4 ; input \prbs_dqs_cnt_r_reg[0]_0 ; input \prbs_dqs_cnt_r_reg[0]_1 ; input \prbs_dqs_cnt_r_reg[0]_2 ; input rstdiv0_sync_r1_reg_rep; input complex_ocal_reset_rd_addr; input [0:0]\calib_sel_reg[3] ; input [3:0]\pi_counter_read_val_reg[5] ; input rstdiv0_sync_r1_reg_rep__24; input oclkdelay_center_calib_done_r_reg; input ocal_last_byte_done; input prbs_rdlvl_done_r1; input rdlvl_stg1_done_int_reg; input wrcal_done_reg; input dqs_found_done_r_reg; input \num_refresh_reg[1] ; input wrlvl_final_mux; input rdlvl_stg1_start_int; input rdlvl_last_byte_done; input \one_rank.stg1_wr_done_reg ; input \A[2]__2 ; input \calib_sel_reg[3]_0 ; input \calib_sel_reg[3]_1 ; input \calib_sel_reg[3]_2 ; input rstdiv0_sync_r1_reg_rep__23; input complex_act_start; input prech_done; input prbs_rdlvl_start_reg_0; input [0:0]E; input \stage_cnt_reg[1]_0 ; wire [1:0]A; wire \A[0]_0 ; wire \A[1]_0 ; wire \A[1]_1 ; wire \A[1]_10 ; wire \A[1]_11 ; wire \A[1]_12 ; wire \A[1]_13 ; wire \A[1]_14 ; wire \A[1]_15 ; wire \A[1]_16 ; wire \A[1]_17 ; wire \A[1]_18 ; wire \A[1]_19 ; wire \A[1]_2 ; wire \A[1]_20 ; wire \A[1]_21 ; wire \A[1]_22 ; wire \A[1]_23 ; wire \A[1]_24 ; wire \A[1]_25 ; wire \A[1]_26 ; wire \A[1]_27 ; wire \A[1]_28 ; wire \A[1]_29 ; wire \A[1]_3 ; wire \A[1]_30 ; wire \A[1]_31 ; wire \A[1]_32 ; wire \A[1]_33 ; wire \A[1]_34 ; wire \A[1]_35 ; wire \A[1]_36 ; wire \A[1]_37 ; wire \A[1]_38 ; wire \A[1]_39 ; wire \A[1]_4 ; wire \A[1]_40 ; wire \A[1]_41 ; wire \A[1]_42 ; wire \A[1]_43 ; wire \A[1]_44 ; wire \A[1]_45 ; wire \A[1]_46 ; wire \A[1]_47 ; wire \A[1]_48 ; wire \A[1]_49 ; wire \A[1]_5 ; wire \A[1]_50 ; wire \A[1]_51 ; wire \A[1]_52 ; wire \A[1]_53 ; wire \A[1]_54 ; wire \A[1]_55 ; wire \A[1]_56 ; wire \A[1]_57 ; wire \A[1]_58 ; wire \A[1]_59 ; wire \A[1]_6 ; wire \A[1]_60 ; wire \A[1]_61 ; wire \A[1]_62 ; wire \A[1]_63 ; wire \A[1]_64 ; wire \A[1]_7 ; wire \A[1]_8 ; wire \A[1]_9 ; wire \A[2]__2 ; wire CLK; wire [7:0]D; wire [0:0]E; wire [4:0]Q; wire bit_cnt; wire bit_cnt0; wire \bit_cnt[7]_i_3_n_0 ; wire \bit_cnt[7]_i_4_n_0 ; wire [7:0]bit_cnt_reg__0; wire [0:0]\calib_sel_reg[3] ; wire \calib_sel_reg[3]_0 ; wire \calib_sel_reg[3]_1 ; wire \calib_sel_reg[3]_2 ; wire \cmp_err_4to1.compare_err_f0_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f0_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f0_reg_n_0 ; wire \cmp_err_4to1.compare_err_f1_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f1_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f1_reg_n_0 ; wire \cmp_err_4to1.compare_err_f2_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f2_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f2_reg_n_0 ; wire \cmp_err_4to1.compare_err_f3_i_2_n_0 ; wire \cmp_err_4to1.compare_err_f3_i_3_n_0 ; wire \cmp_err_4to1.compare_err_f3_reg_n_0 ; wire \cmp_err_4to1.compare_err_i_4_n_0 ; wire \cmp_err_4to1.compare_err_r0_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r0_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r0_reg_n_0 ; wire \cmp_err_4to1.compare_err_r1_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r1_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r1_reg_n_0 ; wire \cmp_err_4to1.compare_err_r2_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r2_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r2_reg_n_0 ; wire \cmp_err_4to1.compare_err_r3_i_2_n_0 ; wire \cmp_err_4to1.compare_err_r3_i_3_n_0 ; wire \cmp_err_4to1.compare_err_r3_reg_n_0 ; wire \cmp_err_4to1.compare_err_reg_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ; wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ; wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ; wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ; wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ; wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ; wire cnt_wait_state; wire cnt_wait_state_i_1_n_0; wire compare_err0; wire compare_err086_out__0; wire compare_err2; wire compare_err_f00; wire compare_err_f10; wire compare_err_f20; wire compare_err_f30; wire compare_err_latch_i_1_n_0; wire compare_err_latch_i_2_n_0; wire compare_err_latch_reg_0; wire compare_err_latch_reg_n_0; wire [7:0]compare_err_pb; wire compare_err_pb_and2; wire compare_err_pb_and_i_1_n_0; wire compare_err_pb_and_i_2_n_0; wire compare_err_pb_and_i_3_n_0; wire compare_err_pb_and_reg_n_0; wire compare_err_pb_or_i_1_n_0; wire compare_err_pb_or_i_2_n_0; wire compare_err_pb_or_i_3_n_0; wire compare_err_r00; wire compare_err_r10; wire compare_err_r20; wire compare_err_r30; wire complex_act_start; wire complex_init_pi_dec_done; wire complex_ocal_reset_rd_addr; wire complex_oclkdelay_calib_done_r1_reg; wire complex_pi_incdec_done; wire complex_pi_incdec_done_i_3_n_0; wire complex_pi_incdec_done_i_4_n_0; wire complex_pi_incdec_done_i_5_n_0; wire complex_pi_incdec_done_i_6_n_0; wire complex_pi_incdec_done_reg_0; wire complex_pi_incdec_done_reg_1; wire complex_victim_inc__0; wire [11:1]data0; wire \dec_cnt[0]_i_11_n_0 ; wire \dec_cnt[0]_i_13_n_0 ; wire \dec_cnt[0]_i_14_n_0 ; wire \dec_cnt[0]_i_15_n_0 ; wire \dec_cnt[0]_i_16_n_0 ; wire \dec_cnt[0]_i_17_n_0 ; wire \dec_cnt[0]_i_1_n_0 ; wire \dec_cnt[0]_i_20_n_0 ; wire \dec_cnt[0]_i_21_n_0 ; wire \dec_cnt[0]_i_22_n_0 ; wire \dec_cnt[0]_i_23_n_0 ; wire \dec_cnt[0]_i_24_n_0 ; wire \dec_cnt[0]_i_25_n_0 ; wire \dec_cnt[0]_i_26_n_0 ; wire \dec_cnt[0]_i_29_n_0 ; wire \dec_cnt[0]_i_32_n_0 ; wire \dec_cnt[0]_i_33_n_0 ; wire \dec_cnt[0]_i_34_n_0 ; wire \dec_cnt[0]_i_35_n_0 ; wire \dec_cnt[0]_i_36_n_0 ; wire \dec_cnt[0]_i_37_n_0 ; wire \dec_cnt[0]_i_38_n_0 ; wire \dec_cnt[0]_i_39_n_0 ; wire \dec_cnt[0]_i_3_n_0 ; wire \dec_cnt[0]_i_40_n_0 ; wire \dec_cnt[0]_i_41_n_0 ; wire \dec_cnt[0]_i_42_n_0 ; wire \dec_cnt[0]_i_43_n_0 ; wire \dec_cnt[0]_i_44_n_0 ; wire \dec_cnt[0]_i_45_n_0 ; wire \dec_cnt[0]_i_46_n_0 ; wire \dec_cnt[0]_i_47_n_0 ; wire \dec_cnt[0]_i_4_n_0 ; wire \dec_cnt[0]_i_5_n_0 ; wire \dec_cnt[0]_i_6_n_0 ; wire \dec_cnt[0]_i_8_n_0 ; wire \dec_cnt[0]_i_9_n_0 ; wire \dec_cnt[1]_i_13_n_0 ; wire \dec_cnt[1]_i_15_n_0 ; wire \dec_cnt[1]_i_16_n_0 ; wire \dec_cnt[1]_i_19_n_0 ; wire \dec_cnt[1]_i_1_n_0 ; wire \dec_cnt[1]_i_20_n_0 ; wire \dec_cnt[1]_i_21_n_0 ; wire \dec_cnt[1]_i_22_n_0 ; wire \dec_cnt[1]_i_25_n_0 ; wire \dec_cnt[1]_i_26_n_0 ; wire \dec_cnt[1]_i_27_n_0 ; wire \dec_cnt[1]_i_28_n_0 ; wire \dec_cnt[1]_i_29_n_0 ; wire \dec_cnt[1]_i_2_n_0 ; wire \dec_cnt[1]_i_30_n_0 ; wire \dec_cnt[1]_i_31_n_0 ; wire \dec_cnt[1]_i_32_n_0 ; wire \dec_cnt[1]_i_33_n_0 ; wire \dec_cnt[1]_i_34_n_0 ; wire \dec_cnt[1]_i_35_n_0 ; wire \dec_cnt[1]_i_36_n_0 ; wire \dec_cnt[1]_i_37_n_0 ; wire \dec_cnt[1]_i_38_n_0 ; wire \dec_cnt[1]_i_3_n_0 ; wire \dec_cnt[1]_i_4_n_0 ; wire \dec_cnt[1]_i_5_n_0 ; wire \dec_cnt[1]_i_6_n_0 ; wire \dec_cnt[1]_i_8_n_0 ; wire \dec_cnt[1]_i_9_n_0 ; wire \dec_cnt[2]_i_10_n_0 ; wire \dec_cnt[2]_i_11_n_0 ; wire \dec_cnt[2]_i_12_n_0 ; wire \dec_cnt[2]_i_13_n_0 ; wire \dec_cnt[2]_i_14_n_0 ; wire \dec_cnt[2]_i_15_n_0 ; wire \dec_cnt[2]_i_17_n_0 ; wire \dec_cnt[2]_i_18_n_0 ; wire \dec_cnt[2]_i_19_n_0 ; wire \dec_cnt[2]_i_20_n_0 ; wire \dec_cnt[2]_i_21_n_0 ; wire \dec_cnt[2]_i_22_n_0 ; wire \dec_cnt[2]_i_23_n_0 ; wire \dec_cnt[2]_i_24_n_0 ; wire \dec_cnt[2]_i_25_n_0 ; wire \dec_cnt[2]_i_26_n_0 ; wire \dec_cnt[2]_i_27_n_0 ; wire \dec_cnt[2]_i_28_n_0 ; wire \dec_cnt[2]_i_29_n_0 ; wire \dec_cnt[2]_i_2_n_0 ; wire \dec_cnt[2]_i_30_n_0 ; wire \dec_cnt[2]_i_31_n_0 ; wire \dec_cnt[2]_i_32_n_0 ; wire \dec_cnt[2]_i_33_n_0 ; wire \dec_cnt[2]_i_34_n_0 ; wire \dec_cnt[2]_i_3_n_0 ; wire \dec_cnt[2]_i_5_n_0 ; wire \dec_cnt[2]_i_6_n_0 ; wire \dec_cnt[2]_i_7_n_0 ; wire \dec_cnt[3]_i_10_n_0 ; wire \dec_cnt[3]_i_11_n_0 ; wire \dec_cnt[3]_i_12_n_0 ; wire \dec_cnt[3]_i_13_n_0 ; wire \dec_cnt[3]_i_14_n_0 ; wire \dec_cnt[3]_i_15_n_0 ; wire \dec_cnt[3]_i_16_n_0 ; wire \dec_cnt[3]_i_17_n_0 ; wire \dec_cnt[3]_i_18_n_0 ; wire \dec_cnt[3]_i_19_n_0 ; wire \dec_cnt[3]_i_1_n_0 ; wire \dec_cnt[3]_i_20_n_0 ; wire \dec_cnt[3]_i_21_n_0 ; wire \dec_cnt[3]_i_22_n_0 ; wire \dec_cnt[3]_i_23_n_0 ; wire \dec_cnt[3]_i_24_n_0 ; wire \dec_cnt[3]_i_25_n_0 ; wire \dec_cnt[3]_i_26_n_0 ; wire \dec_cnt[3]_i_27_n_0 ; wire \dec_cnt[3]_i_2_n_0 ; wire \dec_cnt[3]_i_3_n_0 ; wire \dec_cnt[3]_i_4_n_0 ; wire \dec_cnt[3]_i_5_n_0 ; wire \dec_cnt[3]_i_6_n_0 ; wire \dec_cnt[3]_i_7_n_0 ; wire \dec_cnt[3]_i_8_n_0 ; wire \dec_cnt[3]_i_9_n_0 ; wire \dec_cnt[4]_i_10_n_0 ; wire \dec_cnt[4]_i_11_n_0 ; wire \dec_cnt[4]_i_12_n_0 ; wire \dec_cnt[4]_i_13_n_0 ; wire \dec_cnt[4]_i_14_n_0 ; wire \dec_cnt[4]_i_15_n_0 ; wire \dec_cnt[4]_i_16_n_0 ; wire \dec_cnt[4]_i_17_n_0 ; wire \dec_cnt[4]_i_1_n_0 ; wire \dec_cnt[4]_i_3_n_0 ; wire \dec_cnt[4]_i_4_n_0 ; wire \dec_cnt[4]_i_5_n_0 ; wire \dec_cnt[4]_i_6_n_0 ; wire \dec_cnt[4]_i_7_n_0 ; wire \dec_cnt[4]_i_8_n_0 ; wire \dec_cnt[4]_i_9_n_0 ; wire \dec_cnt[5]_i_1_n_0 ; wire \dec_cnt[5]_i_2_n_0 ; wire \dec_cnt[5]_i_3_n_0 ; wire \dec_cnt[5]_i_4_n_0 ; wire \dec_cnt[5]_i_5_n_0 ; wire \dec_cnt[5]_i_6_n_0 ; wire \dec_cnt[5]_i_7_n_0 ; wire [4:1]dec_cnt_reg; wire \dec_cnt_reg[0]_0 ; wire \dec_cnt_reg[0]_i_10_n_0 ; wire \dec_cnt_reg[0]_i_12_n_0 ; wire \dec_cnt_reg[0]_i_18_n_0 ; wire \dec_cnt_reg[0]_i_19_n_0 ; wire \dec_cnt_reg[0]_i_27_n_0 ; wire \dec_cnt_reg[0]_i_28_n_0 ; wire \dec_cnt_reg[0]_i_2_n_0 ; wire \dec_cnt_reg[0]_i_30_n_0 ; wire \dec_cnt_reg[0]_i_31_n_0 ; wire \dec_cnt_reg[0]_i_7_n_0 ; wire \dec_cnt_reg[1]_i_10_n_0 ; wire \dec_cnt_reg[1]_i_11_n_0 ; wire \dec_cnt_reg[1]_i_12_n_0 ; wire \dec_cnt_reg[1]_i_14_n_0 ; wire \dec_cnt_reg[1]_i_17_n_0 ; wire \dec_cnt_reg[1]_i_18_n_0 ; wire \dec_cnt_reg[1]_i_23_n_0 ; wire \dec_cnt_reg[1]_i_24_n_0 ; wire \dec_cnt_reg[1]_i_7_n_0 ; wire \dec_cnt_reg[2]_i_16_n_0 ; wire \dec_cnt_reg[2]_i_1_n_0 ; wire \dec_cnt_reg[2]_i_4_n_0 ; wire \dec_cnt_reg[2]_i_8_n_0 ; wire \dec_cnt_reg[2]_i_9_n_0 ; wire \dec_cnt_reg[4]_i_2_n_0 ; wire \dout_o_reg[0] ; wire \dout_o_reg[0]_0 ; wire \dout_o_reg[0]_1 ; wire \dout_o_reg[0]_2 ; wire \dout_o_reg[0]_3 ; wire \dout_o_reg[0]_4 ; wire \dout_o_reg[0]_5 ; wire \dout_o_reg[0]_6 ; wire \dout_o_reg[1] ; wire \dout_o_reg[1]_0 ; wire \dout_o_reg[1]_1 ; wire \dout_o_reg[1]_2 ; wire \dout_o_reg[1]_3 ; wire \dout_o_reg[1]_4 ; wire \dout_o_reg[1]_5 ; wire \dout_o_reg[1]_6 ; wire \dout_o_reg[2] ; wire \dout_o_reg[2]_0 ; wire \dout_o_reg[2]_1 ; wire \dout_o_reg[2]_2 ; wire \dout_o_reg[2]_3 ; wire \dout_o_reg[2]_4 ; wire \dout_o_reg[2]_5 ; wire \dout_o_reg[2]_6 ; wire \dout_o_reg[3] ; wire \dout_o_reg[3]_0 ; wire \dout_o_reg[3]_1 ; wire \dout_o_reg[3]_2 ; wire \dout_o_reg[3]_3 ; wire \dout_o_reg[3]_4 ; wire \dout_o_reg[3]_5 ; wire \dout_o_reg[3]_6 ; wire \dout_o_reg[4] ; wire \dout_o_reg[4]_0 ; wire \dout_o_reg[4]_1 ; wire \dout_o_reg[4]_2 ; wire \dout_o_reg[4]_3 ; wire \dout_o_reg[4]_4 ; wire \dout_o_reg[4]_5 ; wire \dout_o_reg[4]_6 ; wire \dout_o_reg[5] ; wire \dout_o_reg[5]_0 ; wire \dout_o_reg[5]_1 ; wire \dout_o_reg[5]_2 ; wire \dout_o_reg[5]_3 ; wire \dout_o_reg[5]_4 ; wire \dout_o_reg[5]_5 ; wire \dout_o_reg[5]_6 ; wire \dout_o_reg[6] ; wire \dout_o_reg[6]_0 ; wire \dout_o_reg[6]_1 ; wire \dout_o_reg[6]_2 ; wire \dout_o_reg[6]_3 ; wire \dout_o_reg[6]_4 ; wire \dout_o_reg[6]_5 ; wire \dout_o_reg[6]_6 ; wire \dout_o_reg[7] ; wire \dout_o_reg[7]_0 ; wire \dout_o_reg[7]_1 ; wire \dout_o_reg[7]_2 ; wire \dout_o_reg[7]_3 ; wire \dout_o_reg[7]_4 ; wire \dout_o_reg[7]_5 ; wire \dout_o_reg[7]_6 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire dqs_found_done_r_reg; wire err_chk_invalid; wire err_chk_invalid_i_1_n_0; wire \fine_delay_mod_reg[20] ; wire \fine_delay_mod_reg[26] ; wire \fine_delay_mod_reg[5] ; wire fine_delay_sel_i_4_n_0; wire fine_delay_sel_r_reg; wire fine_delay_sel_reg_0; wire fine_delay_sel_reg_1; wire fine_dly_error_reg_0; wire fine_dly_error_reg_1; wire fine_inc_stage_i_1_n_0; wire fine_inc_stage_reg_n_0; wire fine_pi_dec_cnt; wire \fine_pi_dec_cnt[0]_i_1_n_0 ; wire \fine_pi_dec_cnt[0]_i_2_n_0 ; wire \fine_pi_dec_cnt[1]_i_1_n_0 ; wire \fine_pi_dec_cnt[1]_i_2_n_0 ; wire \fine_pi_dec_cnt[2]_i_1_n_0 ; wire \fine_pi_dec_cnt[2]_i_2_n_0 ; wire \fine_pi_dec_cnt[3]_i_10_n_0 ; wire \fine_pi_dec_cnt[3]_i_1_n_0 ; wire \fine_pi_dec_cnt[3]_i_2_n_0 ; wire \fine_pi_dec_cnt[3]_i_4_n_0 ; wire \fine_pi_dec_cnt[3]_i_5_n_0 ; wire \fine_pi_dec_cnt[3]_i_6_n_0 ; wire \fine_pi_dec_cnt[3]_i_7_n_0 ; wire \fine_pi_dec_cnt[3]_i_8_n_0 ; wire \fine_pi_dec_cnt[3]_i_9_n_0 ; wire \fine_pi_dec_cnt[4]_i_2_n_0 ; wire \fine_pi_dec_cnt[4]_i_3_n_0 ; wire \fine_pi_dec_cnt[5]_i_10_n_0 ; wire \fine_pi_dec_cnt[5]_i_11_n_0 ; wire \fine_pi_dec_cnt[5]_i_3_n_0 ; wire \fine_pi_dec_cnt[5]_i_4_n_0 ; wire \fine_pi_dec_cnt[5]_i_5_n_0 ; wire \fine_pi_dec_cnt[5]_i_6_n_0 ; wire \fine_pi_dec_cnt[5]_i_7_n_0 ; wire \fine_pi_dec_cnt[5]_i_9_n_0 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_0 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_1 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_2 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_3 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_4 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_5 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_6 ; wire \fine_pi_dec_cnt_reg[3]_i_3_n_7 ; wire \fine_pi_dec_cnt_reg[4]_i_1_n_0 ; wire \fine_pi_dec_cnt_reg[5]_i_2_n_0 ; wire \fine_pi_dec_cnt_reg[5]_i_8_n_3 ; wire \fine_pi_dec_cnt_reg[5]_i_8_n_6 ; wire \fine_pi_dec_cnt_reg[5]_i_8_n_7 ; wire \fine_pi_dec_cnt_reg_n_0_[0] ; wire \fine_pi_dec_cnt_reg_n_0_[1] ; wire \fine_pi_dec_cnt_reg_n_0_[2] ; wire \fine_pi_dec_cnt_reg_n_0_[3] ; wire \fine_pi_dec_cnt_reg_n_0_[4] ; wire \fine_pi_dec_cnt_reg_n_0_[5] ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ; wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ; wire \gen_mux_rd[0].compare_data_fall0_r1_reg ; wire \gen_mux_rd[0].compare_data_fall1_r1_reg ; wire \gen_mux_rd[0].compare_data_fall2_r1_reg ; wire \gen_mux_rd[0].compare_data_fall3_r1_reg ; wire \gen_mux_rd[0].compare_data_rise0_r1_reg ; wire \gen_mux_rd[0].compare_data_rise1_r1_reg ; wire \gen_mux_rd[0].compare_data_rise2_r1_reg ; wire \gen_mux_rd[0].compare_data_rise3_r1_reg ; wire \gen_mux_rd[1].compare_data_fall0_r1_reg ; wire \gen_mux_rd[1].compare_data_fall1_r1_reg ; wire \gen_mux_rd[1].compare_data_fall2_r1_reg ; wire \gen_mux_rd[1].compare_data_fall3_r1_reg ; wire \gen_mux_rd[1].compare_data_rise0_r1_reg ; wire \gen_mux_rd[1].compare_data_rise1_r1_reg ; wire \gen_mux_rd[1].compare_data_rise2_r1_reg ; wire \gen_mux_rd[1].compare_data_rise3_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[1].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[1].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[2].compare_data_fall0_r1_reg ; wire \gen_mux_rd[2].compare_data_fall1_r1_reg ; wire \gen_mux_rd[2].compare_data_fall2_r1_reg ; wire \gen_mux_rd[2].compare_data_fall3_r1_reg ; wire \gen_mux_rd[2].compare_data_rise0_r1_reg ; wire \gen_mux_rd[2].compare_data_rise1_r1_reg ; wire \gen_mux_rd[2].compare_data_rise2_r1_reg ; wire \gen_mux_rd[2].compare_data_rise3_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[2].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[2].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[3].compare_data_fall0_r1_reg ; wire \gen_mux_rd[3].compare_data_fall1_r1_reg ; wire \gen_mux_rd[3].compare_data_fall2_r1_reg ; wire \gen_mux_rd[3].compare_data_fall3_r1_reg ; wire \gen_mux_rd[3].compare_data_rise0_r1_reg ; wire \gen_mux_rd[3].compare_data_rise1_r1_reg ; wire \gen_mux_rd[3].compare_data_rise2_r1_reg ; wire \gen_mux_rd[3].compare_data_rise3_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[3].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[3].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[4].compare_data_fall0_r1_reg ; wire \gen_mux_rd[4].compare_data_fall1_r1_reg ; wire \gen_mux_rd[4].compare_data_fall2_r1_reg ; wire \gen_mux_rd[4].compare_data_fall3_r1_reg ; wire \gen_mux_rd[4].compare_data_rise0_r1_reg ; wire \gen_mux_rd[4].compare_data_rise1_r1_reg ; wire \gen_mux_rd[4].compare_data_rise2_r1_reg ; wire \gen_mux_rd[4].compare_data_rise3_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[4].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[4].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[5].compare_data_fall0_r1_reg ; wire \gen_mux_rd[5].compare_data_fall1_r1_reg ; wire \gen_mux_rd[5].compare_data_fall2_r1_reg ; wire \gen_mux_rd[5].compare_data_fall3_r1_reg ; wire \gen_mux_rd[5].compare_data_rise0_r1_reg ; wire \gen_mux_rd[5].compare_data_rise1_r1_reg ; wire \gen_mux_rd[5].compare_data_rise2_r1_reg ; wire \gen_mux_rd[5].compare_data_rise3_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[5].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[5].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[6].compare_data_fall0_r1_reg ; wire \gen_mux_rd[6].compare_data_fall1_r1_reg ; wire \gen_mux_rd[6].compare_data_fall2_r1_reg ; wire \gen_mux_rd[6].compare_data_fall3_r1_reg ; wire \gen_mux_rd[6].compare_data_rise0_r1_reg ; wire \gen_mux_rd[6].compare_data_rise1_r1_reg ; wire \gen_mux_rd[6].compare_data_rise2_r1_reg ; wire \gen_mux_rd[6].compare_data_rise3_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[6].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[6].mux_rd_rise3_r1_reg ; wire \gen_mux_rd[7].compare_data_fall0_r1_reg ; wire \gen_mux_rd[7].compare_data_fall1_r1_reg ; wire \gen_mux_rd[7].compare_data_fall2_r1_reg ; wire \gen_mux_rd[7].compare_data_fall3_r1_reg ; wire \gen_mux_rd[7].compare_data_rise0_r1_reg ; wire \gen_mux_rd[7].compare_data_rise1_r1_reg ; wire \gen_mux_rd[7].compare_data_rise2_r1_reg ; wire \gen_mux_rd[7].compare_data_rise3_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall0_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall1_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall2_r1_reg ; wire \gen_mux_rd[7].mux_rd_fall3_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise0_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise1_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise2_r1_reg ; wire \gen_mux_rd[7].mux_rd_rise3_r1_reg ; wire \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ; wire \genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ; wire \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ; wire \genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ; wire \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ; wire \genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ; wire \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ; wire \genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ; wire \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ; wire \genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ; wire \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ; wire \genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ; wire \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ; wire \genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ; wire \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ; wire \genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ; wire \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ; wire \genblk8[0].left_edge_found_pb_reg[0]_0 ; wire \genblk8[0].left_edge_pb[0]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[1]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[2]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[3]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[4]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[5]_i_1_n_0 ; wire \genblk8[0].left_edge_pb[5]_i_3_n_0 ; wire \genblk8[0].left_edge_pb[5]_i_5_n_0 ; wire \genblk8[0].left_edge_pb_reg_n_0_[0] ; wire \genblk8[0].left_edge_pb_reg_n_0_[1] ; wire \genblk8[0].left_edge_pb_reg_n_0_[2] ; wire \genblk8[0].left_edge_pb_reg_n_0_[3] ; wire \genblk8[0].left_edge_pb_reg_n_0_[4] ; wire \genblk8[0].left_edge_pb_reg_n_0_[5] ; wire \genblk8[0].left_edge_updated_reg[0]_0 ; wire \genblk8[0].left_loss_pb[0]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[1]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[2]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_3_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_4_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_5_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_6_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_7_n_0 ; wire \genblk8[0].left_loss_pb[3]_i_8_n_0 ; wire \genblk8[0].left_loss_pb[4]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_10_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_11_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_12_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_13_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_15_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_16_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_17_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_18_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_1_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_20_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_21_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_22_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_23_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_24_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_25_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_26_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_27_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_28_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_29_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_2_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_30_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_31_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_7_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_8_n_0 ; wire \genblk8[0].left_loss_pb[5]_i_9_n_0 ; wire \genblk8[0].left_loss_pb_reg[0]_0 ; wire \genblk8[0].left_loss_pb_reg[0]_1 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_3 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ; wire \genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_14_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_19_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_4_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_5_n_3 ; wire \genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ; wire \genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ; wire \genblk8[0].left_loss_pb_reg[5]_i_6_n_3 ; wire [5:2]\genblk8[0].left_loss_pb_reg__0 ; wire \genblk8[0].left_loss_pb_reg_n_0_[0] ; wire \genblk8[0].left_loss_pb_reg_n_0_[1] ; wire \genblk8[0].match_flag_pb[7]_i_1_n_0 ; wire \genblk8[0].right_edge_found_pb_reg[0]_0 ; wire \genblk8[0].right_edge_pb[1]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[2]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[3]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[4]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[5]_i_1_n_0 ; wire \genblk8[0].right_edge_pb[5]_i_2_n_0 ; wire \genblk8[0].right_edge_pb[5]_i_3_n_0 ; wire \genblk8[0].right_edge_pb_reg[0]_0 ; wire \genblk8[0].right_edge_pb_reg[0]_1 ; wire \genblk8[0].right_edge_pb_reg_n_0_[0] ; wire \genblk8[0].right_edge_pb_reg_n_0_[1] ; wire \genblk8[0].right_edge_pb_reg_n_0_[2] ; wire \genblk8[0].right_edge_pb_reg_n_0_[3] ; wire \genblk8[0].right_edge_pb_reg_n_0_[4] ; wire \genblk8[0].right_edge_pb_reg_n_0_[5] ; wire \genblk8[0].right_gain_pb[0]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[1]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[2]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_10_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_11_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_4_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_5_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_6_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_7_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_8_n_0 ; wire \genblk8[0].right_gain_pb[3]_i_9_n_0 ; wire \genblk8[0].right_gain_pb[4]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_11_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_12_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_13_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_14_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_15_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_16_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_17_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_18_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_19_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_1_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_20_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_23_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_24_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_25_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_26_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_27_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_28_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_2_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_30_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_31_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_32_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_33_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_35_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_36_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_37_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_38_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_3_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_40_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_41_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_42_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_43_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_44_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_45_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_46_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_47_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_48_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_49_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_50_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_52_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_53_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_54_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_55_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_56_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_57_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_58_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_59_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_60_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_61_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_62_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_8_n_0 ; wire \genblk8[0].right_gain_pb[5]_i_9_n_0 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_3 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ; wire \genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_3 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ; wire \genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_10_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_21_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_22_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_29_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_34_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_39_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_51_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ; wire \genblk8[0].right_gain_pb_reg[5]_i_5_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_6_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ; wire \genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ; wire \genblk8[0].right_gain_pb_reg[5]_i_7_n_3 ; wire \genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ; wire \genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ; wire [5:2]\genblk8[0].right_gain_pb_reg__0 ; wire \genblk8[0].right_gain_pb_reg_n_0_[0] ; wire \genblk8[0].right_gain_pb_reg_n_0_[1] ; wire \genblk8[1].left_edge_found_pb_reg[1]_0 ; wire \genblk8[1].left_edge_pb[11]_i_1_n_0 ; wire \genblk8[1].left_edge_pb[11]_i_3_n_0 ; wire \genblk8[1].left_edge_pb_reg_n_0_[10] ; wire \genblk8[1].left_edge_pb_reg_n_0_[11] ; wire \genblk8[1].left_edge_pb_reg_n_0_[6] ; wire \genblk8[1].left_edge_pb_reg_n_0_[7] ; wire \genblk8[1].left_edge_pb_reg_n_0_[8] ; wire \genblk8[1].left_edge_pb_reg_n_0_[9] ; wire \genblk8[1].left_edge_updated_reg[1]_0 ; wire \genblk8[1].left_loss_pb[11]_i_1_n_0 ; wire \genblk8[1].left_loss_pb_reg[6]_0 ; wire [5:2]\genblk8[1].left_loss_pb_reg__0 ; wire \genblk8[1].left_loss_pb_reg_n_0_[6] ; wire \genblk8[1].left_loss_pb_reg_n_0_[7] ; wire \genblk8[1].right_edge_found_pb_reg[1]_0 ; wire \genblk8[1].right_edge_pb[11]_i_1_n_0 ; wire \genblk8[1].right_edge_pb[11]_i_2_n_0 ; wire \genblk8[1].right_edge_pb_reg[6]_0 ; wire \genblk8[1].right_edge_pb_reg_n_0_[10] ; wire \genblk8[1].right_edge_pb_reg_n_0_[11] ; wire \genblk8[1].right_edge_pb_reg_n_0_[6] ; wire \genblk8[1].right_edge_pb_reg_n_0_[7] ; wire \genblk8[1].right_edge_pb_reg_n_0_[8] ; wire \genblk8[1].right_edge_pb_reg_n_0_[9] ; wire \genblk8[1].right_gain_pb[10]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_10_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_11_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_12_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_13_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_14_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_16_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_17_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_19_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_20_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_21_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_22_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_24_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_25_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_26_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_27_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_29_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_2_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_30_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_31_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_32_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_33_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_34_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_35_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_36_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_37_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_38_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_39_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_3_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_7_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_8_n_0 ; wire \genblk8[1].right_gain_pb[11]_i_9_n_0 ; wire \genblk8[1].right_gain_pb[6]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[7]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[8]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_10_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_11_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_1_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_4_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_5_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_6_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_7_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_8_n_0 ; wire \genblk8[1].right_gain_pb[9]_i_9_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_15_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_18_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_23_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ; wire \genblk8[1].right_gain_pb_reg[11]_i_28_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ; wire \genblk8[1].right_gain_pb_reg[11]_i_5_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ; wire \genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ; wire \genblk8[1].right_gain_pb_reg[11]_i_6_n_3 ; wire \genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ; wire \genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_3 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ; wire \genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_3 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ; wire \genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ; wire [5:2]\genblk8[1].right_gain_pb_reg__0 ; wire \genblk8[1].right_gain_pb_reg_n_0_[6] ; wire \genblk8[1].right_gain_pb_reg_n_0_[7] ; wire \genblk8[2].left_edge_found_pb_reg[2]_0 ; wire \genblk8[2].left_edge_pb[17]_i_1_n_0 ; wire \genblk8[2].left_edge_pb[17]_i_3_n_0 ; wire \genblk8[2].left_edge_pb_reg_n_0_[12] ; wire \genblk8[2].left_edge_pb_reg_n_0_[13] ; wire \genblk8[2].left_edge_pb_reg_n_0_[14] ; wire \genblk8[2].left_edge_pb_reg_n_0_[15] ; wire \genblk8[2].left_edge_pb_reg_n_0_[16] ; wire \genblk8[2].left_edge_pb_reg_n_0_[17] ; wire \genblk8[2].left_edge_updated_reg[2]_0 ; wire \genblk8[2].left_loss_pb[17]_i_1_n_0 ; wire \genblk8[2].left_loss_pb_reg[12]_0 ; wire [5:2]\genblk8[2].left_loss_pb_reg__0 ; wire \genblk8[2].left_loss_pb_reg_n_0_[12] ; wire \genblk8[2].left_loss_pb_reg_n_0_[13] ; wire \genblk8[2].right_edge_found_pb_reg[2]_0 ; wire \genblk8[2].right_edge_pb[17]_i_1_n_0 ; wire \genblk8[2].right_edge_pb[17]_i_2_n_0 ; wire \genblk8[2].right_edge_pb_reg[12]_0 ; wire \genblk8[2].right_edge_pb_reg[12]_1 ; wire \genblk8[2].right_edge_pb_reg[12]_2 ; wire \genblk8[2].right_edge_pb_reg_n_0_[12] ; wire \genblk8[2].right_edge_pb_reg_n_0_[13] ; wire \genblk8[2].right_edge_pb_reg_n_0_[14] ; wire \genblk8[2].right_edge_pb_reg_n_0_[15] ; wire \genblk8[2].right_edge_pb_reg_n_0_[16] ; wire \genblk8[2].right_edge_pb_reg_n_0_[17] ; wire \genblk8[2].right_gain_pb[12]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[13]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[14]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_10_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_11_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_4_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_5_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_6_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_7_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_8_n_0 ; wire \genblk8[2].right_gain_pb[15]_i_9_n_0 ; wire \genblk8[2].right_gain_pb[16]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_10_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_11_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_12_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_13_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_14_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_16_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_17_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_19_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_1_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_20_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_21_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_22_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_24_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_25_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_26_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_27_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_29_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_2_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_30_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_31_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_32_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_33_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_34_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_35_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_36_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_37_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_38_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_39_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_3_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_7_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_8_n_0 ; wire \genblk8[2].right_gain_pb[17]_i_9_n_0 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_3 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ; wire \genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_3 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ; wire \genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_15_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_18_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_23_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ; wire \genblk8[2].right_gain_pb_reg[17]_i_28_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ; wire \genblk8[2].right_gain_pb_reg[17]_i_5_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ; wire \genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ; wire \genblk8[2].right_gain_pb_reg[17]_i_6_n_3 ; wire \genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ; wire \genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ; wire [5:2]\genblk8[2].right_gain_pb_reg__0 ; wire \genblk8[2].right_gain_pb_reg_n_0_[12] ; wire \genblk8[2].right_gain_pb_reg_n_0_[13] ; wire \genblk8[3].left_edge_found_pb_reg[3]_0 ; wire \genblk8[3].left_edge_pb[23]_i_1_n_0 ; wire \genblk8[3].left_edge_pb[23]_i_3_n_0 ; wire \genblk8[3].left_edge_pb_reg_n_0_[18] ; wire \genblk8[3].left_edge_pb_reg_n_0_[19] ; wire \genblk8[3].left_edge_pb_reg_n_0_[20] ; wire \genblk8[3].left_edge_pb_reg_n_0_[21] ; wire \genblk8[3].left_edge_pb_reg_n_0_[22] ; wire \genblk8[3].left_edge_pb_reg_n_0_[23] ; wire \genblk8[3].left_edge_updated_reg[3]_0 ; wire \genblk8[3].left_loss_pb[23]_i_1_n_0 ; wire \genblk8[3].left_loss_pb_reg[18]_0 ; wire [5:2]\genblk8[3].left_loss_pb_reg__0 ; wire \genblk8[3].left_loss_pb_reg_n_0_[18] ; wire \genblk8[3].left_loss_pb_reg_n_0_[19] ; wire \genblk8[3].right_edge_found_pb_reg[3]_0 ; wire \genblk8[3].right_edge_pb[23]_i_1_n_0 ; wire \genblk8[3].right_edge_pb[23]_i_2_n_0 ; wire \genblk8[3].right_edge_pb_reg[18]_0 ; wire \genblk8[3].right_edge_pb_reg_n_0_[18] ; wire \genblk8[3].right_edge_pb_reg_n_0_[19] ; wire \genblk8[3].right_edge_pb_reg_n_0_[20] ; wire \genblk8[3].right_edge_pb_reg_n_0_[21] ; wire \genblk8[3].right_edge_pb_reg_n_0_[22] ; wire \genblk8[3].right_edge_pb_reg_n_0_[23] ; wire \genblk8[3].right_gain_pb[18]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[19]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[20]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_10_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_11_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_4_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_5_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_6_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_7_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_8_n_0 ; wire \genblk8[3].right_gain_pb[21]_i_9_n_0 ; wire \genblk8[3].right_gain_pb[22]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_10_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_11_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_12_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_13_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_14_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_16_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_17_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_19_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_1_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_20_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_21_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_22_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_24_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_25_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_26_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_27_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_29_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_2_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_30_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_31_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_32_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_33_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_34_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_35_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_36_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_37_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_38_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_39_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_3_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_7_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_8_n_0 ; wire \genblk8[3].right_gain_pb[23]_i_9_n_0 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_3 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ; wire \genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_3 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ; wire \genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_15_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_18_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_23_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ; wire \genblk8[3].right_gain_pb_reg[23]_i_28_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ; wire \genblk8[3].right_gain_pb_reg[23]_i_5_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ; wire \genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ; wire \genblk8[3].right_gain_pb_reg[23]_i_6_n_3 ; wire \genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ; wire \genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ; wire [5:2]\genblk8[3].right_gain_pb_reg__0 ; wire \genblk8[3].right_gain_pb_reg_n_0_[18] ; wire \genblk8[3].right_gain_pb_reg_n_0_[19] ; wire \genblk8[4].left_edge_found_pb_reg[4]_0 ; wire \genblk8[4].left_edge_pb[29]_i_1_n_0 ; wire \genblk8[4].left_edge_pb[29]_i_3_n_0 ; wire \genblk8[4].left_edge_pb_reg_n_0_[24] ; wire \genblk8[4].left_edge_pb_reg_n_0_[25] ; wire \genblk8[4].left_edge_pb_reg_n_0_[26] ; wire \genblk8[4].left_edge_pb_reg_n_0_[27] ; wire \genblk8[4].left_edge_pb_reg_n_0_[28] ; wire \genblk8[4].left_edge_pb_reg_n_0_[29] ; wire \genblk8[4].left_edge_updated_reg[4]_0 ; wire \genblk8[4].left_loss_pb[29]_i_1_n_0 ; wire \genblk8[4].left_loss_pb_reg[24]_0 ; wire [5:2]\genblk8[4].left_loss_pb_reg__0 ; wire \genblk8[4].left_loss_pb_reg_n_0_[24] ; wire \genblk8[4].left_loss_pb_reg_n_0_[25] ; wire \genblk8[4].right_edge_found_pb_reg[4]_0 ; wire \genblk8[4].right_edge_pb[29]_i_1_n_0 ; wire \genblk8[4].right_edge_pb[29]_i_2_n_0 ; wire \genblk8[4].right_edge_pb_reg[24]_0 ; wire \genblk8[4].right_edge_pb_reg_n_0_[24] ; wire \genblk8[4].right_edge_pb_reg_n_0_[25] ; wire \genblk8[4].right_edge_pb_reg_n_0_[26] ; wire \genblk8[4].right_edge_pb_reg_n_0_[27] ; wire \genblk8[4].right_edge_pb_reg_n_0_[28] ; wire \genblk8[4].right_edge_pb_reg_n_0_[29] ; wire \genblk8[4].right_gain_pb[24]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[25]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[26]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_10_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_11_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_4_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_5_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_6_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_7_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_8_n_0 ; wire \genblk8[4].right_gain_pb[27]_i_9_n_0 ; wire \genblk8[4].right_gain_pb[28]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_10_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_11_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_12_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_13_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_14_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_16_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_17_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_19_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_1_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_20_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_21_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_22_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_24_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_25_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_26_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_27_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_29_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_2_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_30_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_31_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_32_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_33_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_34_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_35_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_36_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_37_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_38_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_39_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_3_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_7_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_8_n_0 ; wire \genblk8[4].right_gain_pb[29]_i_9_n_0 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_3 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ; wire \genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_3 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ; wire \genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_15_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_18_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_23_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ; wire \genblk8[4].right_gain_pb_reg[29]_i_28_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ; wire \genblk8[4].right_gain_pb_reg[29]_i_5_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ; wire \genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ; wire \genblk8[4].right_gain_pb_reg[29]_i_6_n_3 ; wire \genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ; wire \genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ; wire [5:2]\genblk8[4].right_gain_pb_reg__0 ; wire \genblk8[4].right_gain_pb_reg_n_0_[24] ; wire \genblk8[4].right_gain_pb_reg_n_0_[25] ; wire \genblk8[5].left_edge_found_pb_reg[5]_0 ; wire \genblk8[5].left_edge_pb[35]_i_1_n_0 ; wire \genblk8[5].left_edge_pb[35]_i_3_n_0 ; wire \genblk8[5].left_edge_pb_reg_n_0_[30] ; wire \genblk8[5].left_edge_pb_reg_n_0_[31] ; wire \genblk8[5].left_edge_pb_reg_n_0_[32] ; wire \genblk8[5].left_edge_pb_reg_n_0_[33] ; wire \genblk8[5].left_edge_pb_reg_n_0_[34] ; wire \genblk8[5].left_edge_pb_reg_n_0_[35] ; wire \genblk8[5].left_edge_updated_reg[5]_0 ; wire \genblk8[5].left_loss_pb[35]_i_1_n_0 ; wire \genblk8[5].left_loss_pb_reg[30]_0 ; wire [5:2]\genblk8[5].left_loss_pb_reg__0 ; wire \genblk8[5].left_loss_pb_reg_n_0_[30] ; wire \genblk8[5].left_loss_pb_reg_n_0_[31] ; wire \genblk8[5].right_edge_found_pb_reg[5]_0 ; wire \genblk8[5].right_edge_pb[35]_i_1_n_0 ; wire \genblk8[5].right_edge_pb[35]_i_2_n_0 ; wire \genblk8[5].right_edge_pb_reg[30]_0 ; wire \genblk8[5].right_edge_pb_reg[30]_1 ; wire \genblk8[5].right_edge_pb_reg_n_0_[30] ; wire \genblk8[5].right_edge_pb_reg_n_0_[31] ; wire \genblk8[5].right_edge_pb_reg_n_0_[32] ; wire \genblk8[5].right_edge_pb_reg_n_0_[33] ; wire \genblk8[5].right_edge_pb_reg_n_0_[34] ; wire \genblk8[5].right_edge_pb_reg_n_0_[35] ; wire \genblk8[5].right_gain_pb[30]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[31]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[32]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_10_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_11_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_4_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_5_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_6_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_7_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_8_n_0 ; wire \genblk8[5].right_gain_pb[33]_i_9_n_0 ; wire \genblk8[5].right_gain_pb[34]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_10_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_11_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_12_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_13_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_14_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_16_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_17_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_19_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_1_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_20_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_21_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_22_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_24_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_25_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_26_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_27_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_29_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_2_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_30_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_31_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_32_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_33_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_34_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_35_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_36_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_37_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_38_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_39_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_3_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_7_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_8_n_0 ; wire \genblk8[5].right_gain_pb[35]_i_9_n_0 ; wire \genblk8[5].right_gain_pb_reg[30]_0 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_3 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ; wire \genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_3 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ; wire \genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_15_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_18_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_23_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ; wire \genblk8[5].right_gain_pb_reg[35]_i_28_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ; wire \genblk8[5].right_gain_pb_reg[35]_i_5_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ; wire \genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ; wire \genblk8[5].right_gain_pb_reg[35]_i_6_n_3 ; wire \genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ; wire \genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ; wire [5:2]\genblk8[5].right_gain_pb_reg__0 ; wire \genblk8[5].right_gain_pb_reg_n_0_[30] ; wire \genblk8[5].right_gain_pb_reg_n_0_[31] ; wire \genblk8[6].left_edge_found_pb_reg[6]_0 ; wire \genblk8[6].left_edge_pb[41]_i_1_n_0 ; wire \genblk8[6].left_edge_pb[41]_i_3_n_0 ; wire \genblk8[6].left_edge_pb_reg_n_0_[36] ; wire \genblk8[6].left_edge_pb_reg_n_0_[37] ; wire \genblk8[6].left_edge_pb_reg_n_0_[38] ; wire \genblk8[6].left_edge_pb_reg_n_0_[39] ; wire \genblk8[6].left_edge_pb_reg_n_0_[40] ; wire \genblk8[6].left_edge_pb_reg_n_0_[41] ; wire \genblk8[6].left_edge_updated_reg[6]_0 ; wire \genblk8[6].left_loss_pb[41]_i_1_n_0 ; wire \genblk8[6].left_loss_pb_reg[36]_0 ; wire [5:2]\genblk8[6].left_loss_pb_reg__0 ; wire \genblk8[6].left_loss_pb_reg_n_0_[36] ; wire \genblk8[6].left_loss_pb_reg_n_0_[37] ; wire \genblk8[6].right_edge_found_pb_reg[6]_0 ; wire \genblk8[6].right_edge_pb[41]_i_1_n_0 ; wire \genblk8[6].right_edge_pb[41]_i_2_n_0 ; wire \genblk8[6].right_edge_pb_reg[36]_0 ; wire \genblk8[6].right_edge_pb_reg_n_0_[36] ; wire \genblk8[6].right_edge_pb_reg_n_0_[37] ; wire \genblk8[6].right_edge_pb_reg_n_0_[38] ; wire \genblk8[6].right_edge_pb_reg_n_0_[39] ; wire \genblk8[6].right_edge_pb_reg_n_0_[40] ; wire \genblk8[6].right_edge_pb_reg_n_0_[41] ; wire \genblk8[6].right_gain_pb[36]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[37]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[38]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_10_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_11_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_4_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_5_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_6_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_7_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_8_n_0 ; wire \genblk8[6].right_gain_pb[39]_i_9_n_0 ; wire \genblk8[6].right_gain_pb[40]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_10_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_11_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_12_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_13_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_14_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_16_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_17_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_19_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_1_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_20_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_21_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_22_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_24_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_25_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_26_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_27_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_29_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_2_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_30_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_31_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_32_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_33_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_34_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_35_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_36_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_37_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_38_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_39_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_3_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_7_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_8_n_0 ; wire \genblk8[6].right_gain_pb[41]_i_9_n_0 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_3 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ; wire \genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_3 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ; wire \genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_15_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_18_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_23_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ; wire \genblk8[6].right_gain_pb_reg[41]_i_28_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ; wire \genblk8[6].right_gain_pb_reg[41]_i_5_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ; wire \genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ; wire \genblk8[6].right_gain_pb_reg[41]_i_6_n_3 ; wire \genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ; wire \genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ; wire [5:2]\genblk8[6].right_gain_pb_reg__0 ; wire \genblk8[6].right_gain_pb_reg_n_0_[36] ; wire \genblk8[6].right_gain_pb_reg_n_0_[37] ; wire \genblk8[7].left_edge_found_pb_reg[7]_0 ; wire \genblk8[7].left_edge_pb[47]_i_1_n_0 ; wire \genblk8[7].left_edge_pb[47]_i_3_n_0 ; wire \genblk8[7].left_edge_pb_reg_n_0_[42] ; wire \genblk8[7].left_edge_pb_reg_n_0_[43] ; wire \genblk8[7].left_edge_pb_reg_n_0_[44] ; wire \genblk8[7].left_edge_pb_reg_n_0_[45] ; wire \genblk8[7].left_edge_pb_reg_n_0_[46] ; wire \genblk8[7].left_edge_pb_reg_n_0_[47] ; wire \genblk8[7].left_edge_updated_reg[7]_0 ; wire \genblk8[7].left_edge_updated_reg[7]_1 ; wire \genblk8[7].left_loss_pb[47]_i_1_n_0 ; wire \genblk8[7].left_loss_pb_reg[42]_0 ; wire [5:2]\genblk8[7].left_loss_pb_reg__0 ; wire \genblk8[7].left_loss_pb_reg_n_0_[42] ; wire \genblk8[7].left_loss_pb_reg_n_0_[43] ; wire \genblk8[7].right_edge_found_pb_reg[7]_0 ; wire \genblk8[7].right_edge_pb[47]_i_1_n_0 ; wire \genblk8[7].right_edge_pb[47]_i_2_n_0 ; wire \genblk8[7].right_edge_pb_reg[42]_0 ; wire \genblk8[7].right_edge_pb_reg[42]_1 ; wire \genblk8[7].right_edge_pb_reg_n_0_[42] ; wire \genblk8[7].right_edge_pb_reg_n_0_[43] ; wire \genblk8[7].right_edge_pb_reg_n_0_[44] ; wire \genblk8[7].right_edge_pb_reg_n_0_[45] ; wire \genblk8[7].right_edge_pb_reg_n_0_[46] ; wire \genblk8[7].right_edge_pb_reg_n_0_[47] ; wire \genblk8[7].right_gain_pb[42]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[43]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[44]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_10_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_11_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_4_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_5_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_6_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_7_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_8_n_0 ; wire \genblk8[7].right_gain_pb[45]_i_9_n_0 ; wire \genblk8[7].right_gain_pb[46]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_10_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_11_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_12_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_13_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_14_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_16_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_17_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_19_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_1_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_20_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_21_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_22_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_24_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_25_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_26_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_27_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_29_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_2_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_30_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_31_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_32_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_33_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_34_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_35_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_36_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_37_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_38_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_39_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_3_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_7_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_8_n_0 ; wire \genblk8[7].right_gain_pb[47]_i_9_n_0 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_3 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ; wire \genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_3 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ; wire \genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_15_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_18_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_23_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ; wire \genblk8[7].right_gain_pb_reg[47]_i_28_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ; wire \genblk8[7].right_gain_pb_reg[47]_i_5_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ; wire \genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ; wire \genblk8[7].right_gain_pb_reg[47]_i_6_n_3 ; wire \genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ; wire \genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ; wire [5:2]\genblk8[7].right_gain_pb_reg__0 ; wire \genblk8[7].right_gain_pb_reg_n_0_[42] ; wire \genblk8[7].right_gain_pb_reg_n_0_[43] ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ; wire \genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ; wire \genblk9[0].fine_delay_incdec_pb_reg[0]_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ; wire \genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ; wire \genblk9[1].fine_delay_incdec_pb_reg[1]_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ; wire \genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ; wire \genblk9[2].fine_delay_incdec_pb_reg[2]_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ; wire \genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ; wire \genblk9[3].fine_delay_incdec_pb_reg[3]_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ; wire \genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ; wire \genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ; wire \genblk9[5].fine_delay_incdec_pb_reg[5]_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ; wire \genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ; wire \genblk9[6].fine_delay_incdec_pb_reg[6]_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ; wire \genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ; wire \genblk9[7].fine_delay_incdec_pb_reg[7]_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[1] ; wire \init_state_r_reg[1]_0 ; wire \largest_left_edge[0]_i_1_n_0 ; wire \largest_left_edge[1]_i_1_n_0 ; wire \largest_left_edge[2]_i_1_n_0 ; wire \largest_left_edge[3]_i_1_n_0 ; wire \largest_left_edge[4]_i_1_n_0 ; wire \largest_left_edge[5]_i_1_n_0 ; wire \largest_left_edge[5]_i_2_n_0 ; wire \largest_left_edge[5]_i_4_n_0 ; wire \largest_left_edge[5]_i_5_n_0 ; wire \largest_left_edge[5]_i_6_n_0 ; wire \largest_left_edge_reg[0]_0 ; wire \largest_left_edge_reg_n_0_[0] ; wire \largest_left_edge_reg_n_0_[1] ; wire \largest_left_edge_reg_n_0_[2] ; wire \largest_left_edge_reg_n_0_[3] ; wire \largest_left_edge_reg_n_0_[4] ; wire \largest_left_edge_reg_n_0_[5] ; wire left_edge_pb; wire [5:0]left_edge_ref; wire \left_edge_ref[0]_i_1_n_0 ; wire \left_edge_ref[0]_i_2_n_0 ; wire \left_edge_ref[0]_i_3_n_0 ; wire \left_edge_ref[1]_i_1_n_0 ; wire \left_edge_ref[1]_i_2_n_0 ; wire \left_edge_ref[1]_i_3_n_0 ; wire \left_edge_ref[2]_i_1_n_0 ; wire \left_edge_ref[2]_i_2_n_0 ; wire \left_edge_ref[2]_i_3_n_0 ; wire \left_edge_ref[3]_i_1_n_0 ; wire \left_edge_ref[3]_i_2_n_0 ; wire \left_edge_ref[3]_i_3_n_0 ; wire \left_edge_ref[4]_i_11_n_0 ; wire \left_edge_ref[4]_i_12_n_0 ; wire \left_edge_ref[4]_i_1_n_0 ; wire \left_edge_ref[4]_i_2_n_0 ; wire \left_edge_ref[4]_i_4_n_0 ; wire \left_edge_ref[4]_i_5_n_0 ; wire \left_edge_ref[4]_i_6_n_0 ; wire \left_edge_ref[4]_i_7_n_0 ; wire \left_edge_ref[4]_i_8_n_0 ; wire \left_edge_ref[4]_i_9_n_0 ; wire \left_edge_ref[5]_i_10_n_0 ; wire \left_edge_ref[5]_i_11_n_0 ; wire \left_edge_ref[5]_i_12_n_0 ; wire \left_edge_ref[5]_i_13_n_0 ; wire \left_edge_ref[5]_i_14_n_0 ; wire \left_edge_ref[5]_i_15_n_0 ; wire \left_edge_ref[5]_i_17_n_0 ; wire \left_edge_ref[5]_i_18_n_0 ; wire \left_edge_ref[5]_i_19_n_0 ; wire \left_edge_ref[5]_i_1_n_0 ; wire \left_edge_ref[5]_i_2_n_0 ; wire \left_edge_ref[5]_i_5_n_0 ; wire \left_edge_ref[5]_i_7_n_0 ; wire \left_edge_ref[5]_i_8_n_0 ; wire \left_edge_ref[5]_i_9_n_0 ; wire \left_edge_ref_reg[4]_i_10_n_0 ; wire \left_edge_ref_reg[4]_i_3_n_0 ; wire \left_edge_ref_reg[5]_i_16_n_0 ; wire \left_edge_ref_reg[5]_i_3_n_0 ; wire \left_edge_ref_reg[5]_i_3_n_1 ; wire \left_edge_ref_reg[5]_i_3_n_2 ; wire \left_edge_ref_reg[5]_i_3_n_3 ; wire \left_edge_ref_reg[5]_i_3_n_4 ; wire \left_edge_ref_reg[5]_i_3_n_5 ; wire \left_edge_ref_reg[5]_i_3_n_6 ; wire \left_edge_ref_reg[5]_i_3_n_7 ; wire \left_edge_ref_reg[5]_i_4_n_0 ; wire \left_edge_ref_reg[5]_i_6_n_7 ; wire match_flag_and; wire \match_flag_and[0]_i_1_n_0 ; wire \match_flag_and[1]_i_1_n_0 ; wire \match_flag_and[2]_i_1_n_0 ; wire \match_flag_and[3]_i_1_n_0 ; wire \match_flag_and[4]_i_1_n_0 ; wire \match_flag_and[5]_i_1_n_0 ; wire \match_flag_and[6]_i_1_n_0 ; wire \match_flag_and[7]_i_2_n_0 ; wire \match_flag_and[7]_i_3_n_0 ; wire \match_flag_and_reg_n_0_[0] ; wire \match_flag_and_reg_n_0_[1] ; wire \match_flag_and_reg_n_0_[2] ; wire \match_flag_and_reg_n_0_[3] ; wire \match_flag_and_reg_n_0_[4] ; wire \match_flag_and_reg_n_0_[5] ; wire \match_flag_and_reg_n_0_[6] ; wire \match_flag_and_reg_n_0_[7] ; wire \match_flag_or[0]_i_1_n_0 ; wire \match_flag_or[1]_i_1_n_0 ; wire \match_flag_or[2]_i_1_n_0 ; wire \match_flag_or[3]_i_1_n_0 ; wire \match_flag_or[4]_i_1_n_0 ; wire \match_flag_or[5]_i_1_n_0 ; wire \match_flag_or[6]_i_1_n_0 ; wire \match_flag_or_reg[0]_0 ; wire [63:0]match_flag_pb; wire mux_rd_fall0_r1; wire mux_rd_fall0_r2; wire mux_rd_fall1_r1; wire mux_rd_fall1_r2; wire mux_rd_fall2_r1; wire mux_rd_fall2_r2; wire mux_rd_fall3_r1; wire mux_rd_fall3_r2; wire mux_rd_rise0_r1; wire mux_rd_rise0_r2; wire mux_rd_rise1_r1; wire mux_rd_rise1_r2; wire mux_rd_rise2_r1; wire mux_rd_rise2_r2; wire mux_rd_rise3_r1; wire mux_rd_rise3_r2; wire mux_rd_valid_r; wire new_cnt_dqs_r; wire new_cnt_dqs_r_reg_0; wire new_cnt_dqs_r_reg_1; wire no_err_win_detected_i_1_n_0; wire no_err_win_detected_i_2_n_0; wire no_err_win_detected_i_3_n_0; wire no_err_win_detected_latch_reg_0; wire no_err_win_detected_latch_reg_1; wire no_err_win_detected_reg_0; wire no_err_win_detected_reg_1; wire \num_refresh_reg[1] ; wire num_samples_done_ind_reg_0; wire num_samples_done_r; wire ocal_last_byte_done; wire oclkdelay_center_calib_done_r_reg; wire \oclkdelay_ref_cnt_reg[0] ; wire \one_rank.stg1_wr_done_reg ; wire [3:0]p_0_in; wire [7:0]p_0_in__0; wire p_103_out; wire p_106_out; wire p_10_out; wire p_119_out; wire p_122_out; wire p_127_out; wire p_130_out; wire p_143_out; wire p_146_out; wire p_154_out; wire p_19_out; wire p_1_in159_in; wire p_28_out; wire p_37_out; wire [0:0]p_3_in; wire p_46_out; wire p_55_out; wire p_64_out; wire p_66_out; wire p_75_out; wire p_95_out; wire p_98_out; wire [3:0]\pi_counter_read_val_reg[5] ; wire pi_en_stg2_f_timing; wire pi_en_stg2_f_timing_reg_0; wire pi_stg2_f_incdec_timing; wire [5:0]prbs_dec_tap_cnt; wire \prbs_dec_tap_cnt[0]_i_1_n_0 ; wire \prbs_dec_tap_cnt[1]_i_1_n_0 ; wire \prbs_dec_tap_cnt[2]_i_1_n_0 ; wire \prbs_dec_tap_cnt[2]_i_2_n_0 ; wire \prbs_dec_tap_cnt[2]_i_3_n_0 ; wire \prbs_dec_tap_cnt[2]_i_4_n_0 ; wire \prbs_dec_tap_cnt[3]_i_1_n_0 ; wire \prbs_dec_tap_cnt[3]_i_2_n_0 ; wire \prbs_dec_tap_cnt[4]_i_2_n_0 ; wire \prbs_dec_tap_cnt[4]_i_3_n_0 ; wire \prbs_dec_tap_cnt[5]_i_1_n_0 ; wire \prbs_dec_tap_cnt[5]_i_4_n_0 ; wire \prbs_dec_tap_cnt[5]_i_5_n_0 ; wire [1:0]\prbs_dec_tap_cnt_reg[1]_0 ; wire \prbs_dec_tap_cnt_reg[4]_i_1_n_0 ; wire \prbs_dec_tap_cnt_reg[5]_i_2_n_0 ; wire \prbs_dqs_cnt_r_reg[0]_0 ; wire \prbs_dqs_cnt_r_reg[0]_1 ; wire \prbs_dqs_cnt_r_reg[0]_2 ; wire \prbs_dqs_cnt_r_reg[1]_0 ; wire \prbs_dqs_cnt_r_reg[2]_0 ; wire \prbs_dqs_tap_cnt_r[0]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[1]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[2]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_i_2_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_i_3_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[4]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[4]_i_2_n_0 ; wire \prbs_dqs_tap_cnt_r[4]_i_3_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_1_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_2_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_3_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_4_n_0 ; wire \prbs_dqs_tap_cnt_r[5]_i_5_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ; wire \prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[0] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[1] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[2] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[3] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[4] ; wire \prbs_dqs_tap_cnt_r_reg_n_0_[5] ; wire prbs_dqs_tap_limit_r; wire prbs_found_1st_edge_r_i_5_n_0; wire prbs_found_1st_edge_r_reg_0; wire prbs_found_1st_edge_r_reg_1; wire \prbs_inc_tap_cnt[0]_i_1_n_0 ; wire \prbs_inc_tap_cnt[1]_i_1_n_0 ; wire \prbs_inc_tap_cnt[1]_i_2_n_0 ; wire \prbs_inc_tap_cnt[2]_i_1_n_0 ; wire \prbs_inc_tap_cnt[2]_i_2_n_0 ; wire \prbs_inc_tap_cnt[2]_i_3_n_0 ; wire \prbs_inc_tap_cnt[3]_i_1_n_0 ; wire \prbs_inc_tap_cnt[3]_i_2_n_0 ; wire \prbs_inc_tap_cnt[3]_i_3_n_0 ; wire \prbs_inc_tap_cnt[3]_i_4_n_0 ; wire \prbs_inc_tap_cnt[4]_i_1_n_0 ; wire \prbs_inc_tap_cnt[4]_i_2_n_0 ; wire \prbs_inc_tap_cnt[5]_i_1_n_0 ; wire \prbs_inc_tap_cnt[5]_i_2_n_0 ; wire \prbs_inc_tap_cnt[5]_i_3_n_0 ; wire \prbs_inc_tap_cnt[5]_i_4_n_0 ; wire \prbs_inc_tap_cnt[5]_i_5_n_0 ; wire \prbs_inc_tap_cnt[5]_i_6_n_0 ; wire \prbs_inc_tap_cnt[5]_i_7_n_0 ; wire \prbs_inc_tap_cnt[5]_i_8_n_0 ; wire \prbs_inc_tap_cnt[5]_i_9_n_0 ; wire \prbs_inc_tap_cnt_reg_n_0_[0] ; wire \prbs_inc_tap_cnt_reg_n_0_[1] ; wire \prbs_inc_tap_cnt_reg_n_0_[2] ; wire \prbs_inc_tap_cnt_reg_n_0_[3] ; wire \prbs_inc_tap_cnt_reg_n_0_[4] ; wire \prbs_inc_tap_cnt_reg_n_0_[5] ; wire prbs_last_byte_done; wire prbs_last_byte_done_reg_0; wire prbs_pi_stg2_f_en; wire prbs_pi_stg2_f_incdec; wire prbs_prech_req_r; wire prbs_rdlvl_done_pulse0; wire prbs_rdlvl_done_r1; wire prbs_rdlvl_done_reg_0; wire prbs_rdlvl_done_reg_1; wire prbs_rdlvl_start_r; wire prbs_rdlvl_start_reg; wire prbs_rdlvl_start_reg_0; wire prbs_state_r1; wire prbs_state_r178_out; wire \prbs_state_r[0]_i_1_n_0 ; wire \prbs_state_r[0]_i_2_n_0 ; wire \prbs_state_r[0]_i_3_n_0 ; wire \prbs_state_r[0]_i_4_n_0 ; wire \prbs_state_r[0]_i_5_n_0 ; wire \prbs_state_r[1]_i_1_n_0 ; wire \prbs_state_r[1]_i_2_n_0 ; wire \prbs_state_r[1]_i_3_n_0 ; wire \prbs_state_r[1]_i_4_n_0 ; wire \prbs_state_r[1]_i_5_n_0 ; wire \prbs_state_r[1]_i_6_n_0 ; wire \prbs_state_r[2]_i_10_n_0 ; wire \prbs_state_r[2]_i_11_n_0 ; wire \prbs_state_r[2]_i_2_n_0 ; wire \prbs_state_r[2]_i_3_n_0 ; wire \prbs_state_r[2]_i_4_n_0 ; wire \prbs_state_r[2]_i_6_n_0 ; wire \prbs_state_r[2]_i_7_n_0 ; wire \prbs_state_r[2]_i_8_n_0 ; wire \prbs_state_r[2]_i_9_n_0 ; wire \prbs_state_r[3]_i_1_n_0 ; wire \prbs_state_r[3]_i_2_n_0 ; wire \prbs_state_r[3]_i_3_n_0 ; wire \prbs_state_r[3]_i_4_n_0 ; wire \prbs_state_r[4]_i_11_n_0 ; wire \prbs_state_r[4]_i_2_n_0 ; wire \prbs_state_r[4]_i_3_n_0 ; wire \prbs_state_r[4]_i_4_n_0 ; wire \prbs_state_r[4]_i_5_n_0 ; wire \prbs_state_r[4]_i_6_n_0 ; wire \prbs_state_r[4]_i_7_n_0 ; wire \prbs_state_r[4]_i_8_n_0 ; wire \prbs_state_r[4]_i_9_n_0 ; wire \prbs_state_r_reg[0]_0 ; wire \prbs_state_r_reg[0]_1 ; wire \prbs_state_r_reg[0]_2 ; wire \prbs_state_r_reg[0]_3 ; wire \prbs_state_r_reg[0]_4 ; wire \prbs_state_r_reg[2]_i_1_n_0 ; wire \prbs_state_r_reg[3]_0 ; wire \prbs_state_r_reg[3]_1 ; wire \prbs_state_r_reg[4]_0 ; wire \prbs_state_r_reg[4]_1 ; wire \prbs_state_r_reg[4]_2 ; wire \prbs_state_r_reg[4]_3 ; wire prbs_tap_en_r; wire prbs_tap_en_r_reg_0; wire prbs_tap_inc_r; wire prbs_tap_inc_r_i_3_n_0; wire prbs_tap_inc_r_reg_0; wire prech_done; wire prech_done_reg; wire prech_req_r_reg; wire rd_valid_r1; wire rd_valid_r2_reg_n_0; wire \rd_victim_sel[0]_i_1_n_0 ; wire \rd_victim_sel[1]_i_1_n_0 ; wire \rd_victim_sel[2]_i_1_n_0 ; wire \rd_victim_sel_reg[2]_0 ; wire \rd_victim_sel_reg[2]_1 ; wire \rd_victim_sel_reg[2]_2 ; wire \rd_victim_sel_reg[2]_3 ; wire [5:0]rdlvl_cpt_tap_cnt; wire \rdlvl_cpt_tap_cnt_reg[5]_0 ; wire [2:0]\rdlvl_cpt_tap_cnt_reg[5]_1 ; wire rdlvl_last_byte_done; wire rdlvl_stg1_done_int_reg; wire rdlvl_stg1_start_int; wire [7:3]ref_bit; wire \ref_bit[7]_i_3_n_0 ; wire \ref_bit[7]_i_4_n_0 ; wire \ref_bit[7]_i_5_n_0 ; wire \ref_bit[7]_i_6_n_0 ; wire ref_bit_per_bit; wire ref_bit_per_bit0; wire \ref_bit_per_bit[7]_i_2_n_0 ; wire \ref_bit_per_bit[7]_i_3_n_0 ; wire \ref_bit_per_bit_reg_n_0_[0] ; wire \ref_bit_per_bit_reg_n_0_[1] ; wire \ref_bit_per_bit_reg_n_0_[2] ; wire \ref_bit_per_bit_reg_n_0_[3] ; wire \ref_bit_per_bit_reg_n_0_[4] ; wire \ref_bit_per_bit_reg_n_0_[5] ; wire \ref_bit_per_bit_reg_n_0_[6] ; wire \ref_bit_per_bit_reg_n_0_[7] ; wire \ref_bit_reg_n_0_[0] ; wire \ref_bit_reg_n_0_[1] ; wire \ref_bit_reg_n_0_[2] ; wire ref_right_edge; wire ref_right_edge125_in; wire \ref_right_edge[0]_i_1_n_0 ; wire \ref_right_edge[0]_i_3_n_0 ; wire \ref_right_edge[0]_i_4_n_0 ; wire \ref_right_edge[1]_i_1_n_0 ; wire \ref_right_edge[1]_i_3_n_0 ; wire \ref_right_edge[1]_i_4_n_0 ; wire \ref_right_edge[1]_i_5_n_0 ; wire \ref_right_edge[1]_i_6_n_0 ; wire \ref_right_edge[2]_i_1_n_0 ; wire \ref_right_edge[2]_i_2_n_0 ; wire \ref_right_edge[2]_i_3_n_0 ; wire \ref_right_edge[3]_i_1_n_0 ; wire \ref_right_edge[3]_i_2_n_0 ; wire \ref_right_edge[3]_i_3_n_0 ; wire \ref_right_edge[4]_i_10_n_0 ; wire \ref_right_edge[4]_i_11_n_0 ; wire \ref_right_edge[4]_i_1_n_0 ; wire \ref_right_edge[4]_i_2_n_0 ; wire \ref_right_edge[4]_i_4_n_0 ; wire \ref_right_edge[4]_i_5_n_0 ; wire \ref_right_edge[4]_i_6_n_0 ; wire \ref_right_edge[4]_i_7_n_0 ; wire \ref_right_edge[4]_i_8_n_0 ; wire \ref_right_edge[4]_i_9_n_0 ; wire \ref_right_edge[5]_i_10_n_0 ; wire \ref_right_edge[5]_i_11_n_0 ; wire \ref_right_edge[5]_i_12_n_0 ; wire \ref_right_edge[5]_i_13_n_0 ; wire \ref_right_edge[5]_i_14_n_0 ; wire \ref_right_edge[5]_i_15_n_0 ; wire \ref_right_edge[5]_i_16_n_0 ; wire \ref_right_edge[5]_i_1_n_0 ; wire \ref_right_edge[5]_i_2_n_0 ; wire \ref_right_edge[5]_i_5_n_0 ; wire \ref_right_edge[5]_i_7_n_0 ; wire \ref_right_edge[5]_i_8_n_0 ; wire \ref_right_edge[5]_i_9_n_0 ; wire \ref_right_edge_reg[0]_i_2_n_0 ; wire \ref_right_edge_reg[1]_i_2_n_0 ; wire \ref_right_edge_reg[4]_i_3_n_0 ; wire \ref_right_edge_reg[5]_i_3_n_0 ; wire \ref_right_edge_reg[5]_i_3_n_1 ; wire \ref_right_edge_reg[5]_i_3_n_2 ; wire \ref_right_edge_reg[5]_i_3_n_3 ; wire \ref_right_edge_reg[5]_i_3_n_4 ; wire \ref_right_edge_reg[5]_i_3_n_5 ; wire \ref_right_edge_reg[5]_i_3_n_6 ; wire \ref_right_edge_reg[5]_i_3_n_7 ; wire \ref_right_edge_reg[5]_i_4_n_0 ; wire \ref_right_edge_reg[5]_i_6_n_7 ; wire \ref_right_edge_reg_n_0_[0] ; wire \ref_right_edge_reg_n_0_[1] ; wire \ref_right_edge_reg_n_0_[2] ; wire \ref_right_edge_reg_n_0_[3] ; wire \ref_right_edge_reg_n_0_[4] ; wire \ref_right_edge_reg_n_0_[5] ; wire reset_rd_addr; wire reset_rd_addr0; wire right_edge_found; wire right_edge_found_i_4_n_0; wire right_edge_found_i_5_n_0; wire right_edge_found_reg_0; wire right_edge_found_reg_1; wire [5:0]right_edge_ref; wire \right_edge_ref[0]_i_1_n_0 ; wire \right_edge_ref[0]_i_2_n_0 ; wire \right_edge_ref[0]_i_3_n_0 ; wire \right_edge_ref[1]_i_1_n_0 ; wire \right_edge_ref[1]_i_2_n_0 ; wire \right_edge_ref[1]_i_3_n_0 ; wire \right_edge_ref[2]_i_1_n_0 ; wire \right_edge_ref[2]_i_2_n_0 ; wire \right_edge_ref[2]_i_3_n_0 ; wire \right_edge_ref[3]_i_1_n_0 ; wire \right_edge_ref[3]_i_2_n_0 ; wire \right_edge_ref[3]_i_3_n_0 ; wire \right_edge_ref[4]_i_11_n_0 ; wire \right_edge_ref[4]_i_12_n_0 ; wire \right_edge_ref[4]_i_1_n_0 ; wire \right_edge_ref[4]_i_2_n_0 ; wire \right_edge_ref[4]_i_4_n_0 ; wire \right_edge_ref[4]_i_5_n_0 ; wire \right_edge_ref[4]_i_6_n_0 ; wire \right_edge_ref[4]_i_7_n_0 ; wire \right_edge_ref[4]_i_8_n_0 ; wire \right_edge_ref[4]_i_9_n_0 ; wire \right_edge_ref[5]_i_11_n_0 ; wire \right_edge_ref[5]_i_12_n_0 ; wire \right_edge_ref[5]_i_1_n_0 ; wire \right_edge_ref[5]_i_2_n_0 ; wire \right_edge_ref[5]_i_4_n_0 ; wire \right_edge_ref[5]_i_5_n_0 ; wire \right_edge_ref[5]_i_6_n_0 ; wire \right_edge_ref[5]_i_7_n_0 ; wire \right_edge_ref[5]_i_8_n_0 ; wire \right_edge_ref[5]_i_9_n_0 ; wire \right_edge_ref_reg[4]_i_10_n_0 ; wire \right_edge_ref_reg[4]_i_3_n_0 ; wire \right_edge_ref_reg[5]_i_10_n_0 ; wire \right_edge_ref_reg[5]_i_3_n_0 ; wire right_gain_pb; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire \samples_cnt_r[0]_i_1_n_0 ; wire \samples_cnt_r[0]_i_2_n_0 ; wire \samples_cnt_r[0]_i_3_n_0 ; wire \samples_cnt_r[10]_i_1_n_0 ; wire \samples_cnt_r[11]_i_2_n_0 ; wire \samples_cnt_r[11]_i_5_n_0 ; wire \samples_cnt_r[11]_i_6_n_0 ; wire \samples_cnt_r[11]_i_7_n_0 ; wire \samples_cnt_r[1]_i_1_n_0 ; wire \samples_cnt_r[2]_i_1_n_0 ; wire \samples_cnt_r[3]_i_1_n_0 ; wire \samples_cnt_r[4]_i_1_n_0 ; wire \samples_cnt_r[4]_i_3_n_0 ; wire \samples_cnt_r[4]_i_4_n_0 ; wire \samples_cnt_r[4]_i_5_n_0 ; wire \samples_cnt_r[4]_i_6_n_0 ; wire \samples_cnt_r[5]_i_1_n_0 ; wire \samples_cnt_r[6]_i_1_n_0 ; wire \samples_cnt_r[7]_i_1_n_0 ; wire \samples_cnt_r[8]_i_1_n_0 ; wire \samples_cnt_r[8]_i_3_n_0 ; wire \samples_cnt_r[8]_i_4_n_0 ; wire \samples_cnt_r[8]_i_5_n_0 ; wire \samples_cnt_r[8]_i_6_n_0 ; wire \samples_cnt_r[9]_i_1_n_0 ; wire \samples_cnt_r_reg[11]_i_4_n_2 ; wire \samples_cnt_r_reg[11]_i_4_n_3 ; wire \samples_cnt_r_reg[4]_i_2_n_0 ; wire \samples_cnt_r_reg[4]_i_2_n_1 ; wire \samples_cnt_r_reg[4]_i_2_n_2 ; wire \samples_cnt_r_reg[4]_i_2_n_3 ; wire \samples_cnt_r_reg[8]_i_2_n_0 ; wire \samples_cnt_r_reg[8]_i_2_n_1 ; wire \samples_cnt_r_reg[8]_i_2_n_2 ; wire \samples_cnt_r_reg[8]_i_2_n_3 ; wire \samples_cnt_r_reg_n_0_[0] ; wire \samples_cnt_r_reg_n_0_[10] ; wire \samples_cnt_r_reg_n_0_[11] ; wire \samples_cnt_r_reg_n_0_[1] ; wire \samples_cnt_r_reg_n_0_[2] ; wire \samples_cnt_r_reg_n_0_[3] ; wire \samples_cnt_r_reg_n_0_[4] ; wire \samples_cnt_r_reg_n_0_[5] ; wire \samples_cnt_r_reg_n_0_[6] ; wire \samples_cnt_r_reg_n_0_[7] ; wire \samples_cnt_r_reg_n_0_[8] ; wire \samples_cnt_r_reg_n_0_[9] ; wire [7:0]sel0; wire smallest_right_edge; wire \smallest_right_edge[0]_i_1_n_0 ; wire \smallest_right_edge[1]_i_1_n_0 ; wire \smallest_right_edge[2]_i_1_n_0 ; wire \smallest_right_edge[3]_i_1_n_0 ; wire \smallest_right_edge[4]_i_1_n_0 ; wire \smallest_right_edge[5]_i_2_n_0 ; wire \smallest_right_edge[5]_i_3_n_0 ; wire \smallest_right_edge[5]_i_4_n_0 ; wire \smallest_right_edge_reg_n_0_[0] ; wire \smallest_right_edge_reg_n_0_[1] ; wire \smallest_right_edge_reg_n_0_[2] ; wire \smallest_right_edge_reg_n_0_[3] ; wire \smallest_right_edge_reg_n_0_[4] ; wire \smallest_right_edge_reg_n_0_[5] ; wire \stage_cnt[0]_i_1_n_0 ; wire \stage_cnt[1]_i_1_n_0 ; wire \stage_cnt[1]_i_2_n_0 ; wire \stage_cnt_reg[1]_0 ; wire \stage_cnt_reg_n_0_[0] ; wire \stg1_wr_rd_cnt_reg[3] ; wire \victim_not_fixed.num_samples_done_r_i_1_n_0 ; wire \victim_not_fixed.num_samples_done_r_i_2_n_0 ; wire wait_state_cnt_en_r; wire wait_state_cnt_en_r0; wire \wait_state_cnt_r[2]_i_1_n_0 ; wire \wait_state_cnt_r[3]_i_1_n_0 ; wire [3:0]wait_state_cnt_r_reg__0; wire wrcal_done_reg; wire wrlvl_final_mux; wire [3:1]\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED ; wire [3:2]\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED ; wire [3:0]\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED ; wire [3:1]\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED ; wire [3:1]\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED ; wire [3:0]\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED ; wire [3:1]\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED ; wire [3:2]\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED ; wire [3:3]\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED ; FDRE \A[0] (.C(CLK), .CE(1'b1), .D(\A[0]_0 ), .Q(A[0]), .R(1'b0)); FDRE \A[1] (.C(CLK), .CE(1'b1), .D(\A[1]_0 ), .Q(A[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT1 #( .INIT(2'h1)) \bit_cnt[0]_i_1 (.I0(bit_cnt_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT2 #( .INIT(4'h6)) \bit_cnt[1]_i_1 (.I0(bit_cnt_reg__0[0]), .I1(bit_cnt_reg__0[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'h78)) \bit_cnt[2]_i_1 (.I0(bit_cnt_reg__0[0]), .I1(bit_cnt_reg__0[1]), .I2(bit_cnt_reg__0[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT4 #( .INIT(16'h7F80)) \bit_cnt[3]_i_1 (.I0(bit_cnt_reg__0[1]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[2]), .I3(bit_cnt_reg__0[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT5 #( .INIT(32'h7FFF8000)) \bit_cnt[4]_i_1 (.I0(bit_cnt_reg__0[2]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[1]), .I3(bit_cnt_reg__0[3]), .I4(bit_cnt_reg__0[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \bit_cnt[5]_i_1 (.I0(bit_cnt_reg__0[3]), .I1(bit_cnt_reg__0[1]), .I2(bit_cnt_reg__0[0]), .I3(bit_cnt_reg__0[2]), .I4(bit_cnt_reg__0[4]), .I5(bit_cnt_reg__0[5]), .O(p_0_in__0[5])); LUT2 #( .INIT(4'h6)) \bit_cnt[6]_i_1 (.I0(\bit_cnt[7]_i_4_n_0 ), .I1(bit_cnt_reg__0[6]), .O(p_0_in__0[6])); LUT6 #( .INIT(64'h0000000000000100)) \bit_cnt[7]_i_1 (.I0(bit_cnt_reg__0[6]), .I1(bit_cnt_reg__0[7]), .I2(\ref_bit_per_bit[7]_i_2_n_0 ), .I3(\bit_cnt[7]_i_3_n_0 ), .I4(bit_cnt_reg__0[5]), .I5(bit_cnt_reg__0[4]), .O(bit_cnt0)); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'h78)) \bit_cnt[7]_i_2 (.I0(\bit_cnt[7]_i_4_n_0 ), .I1(bit_cnt_reg__0[6]), .I2(bit_cnt_reg__0[7]), .O(p_0_in__0[7])); LUT6 #( .INIT(64'h0000000000000800)) \bit_cnt[7]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[4]), .I4(Q[3]), .I5(bit_cnt_reg__0[3]), .O(\bit_cnt[7]_i_3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \bit_cnt[7]_i_4 (.I0(bit_cnt_reg__0[5]), .I1(bit_cnt_reg__0[3]), .I2(bit_cnt_reg__0[1]), .I3(bit_cnt_reg__0[0]), .I4(bit_cnt_reg__0[2]), .I5(bit_cnt_reg__0[4]), .O(\bit_cnt[7]_i_4_n_0 )); FDRE \bit_cnt_reg[0] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[0]), .Q(bit_cnt_reg__0[0]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[1] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[1]), .Q(bit_cnt_reg__0[1]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[2] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[2]), .Q(bit_cnt_reg__0[2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[3] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[3]), .Q(bit_cnt_reg__0[3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[4] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[4]), .Q(bit_cnt_reg__0[4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[5] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[5]), .Q(bit_cnt_reg__0[5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[6] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[6]), .Q(bit_cnt_reg__0[6]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \bit_cnt_reg[7] (.C(CLK), .CE(bit_cnt0), .D(p_0_in__0[7]), .Q(bit_cnt_reg__0[7]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f0_i_1 (.I0(\gen_mux_rd[7].compare_data_fall0_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ), .I4(\cmp_err_4to1.compare_err_f0_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f0_i_3_n_0 ), .O(compare_err_f00)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f0_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall0_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ), .O(\cmp_err_4to1.compare_err_f0_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f0_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall0_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ), .O(\cmp_err_4to1.compare_err_f0_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_f0_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f00), .Q(\cmp_err_4to1.compare_err_f0_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f1_i_1 (.I0(\gen_mux_rd[7].compare_data_fall1_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ), .I4(\cmp_err_4to1.compare_err_f1_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f1_i_3_n_0 ), .O(compare_err_f10)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f1_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall1_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ), .O(\cmp_err_4to1.compare_err_f1_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f1_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall1_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ), .O(\cmp_err_4to1.compare_err_f1_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_f1_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f10), .Q(\cmp_err_4to1.compare_err_f1_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f2_i_1 (.I0(\gen_mux_rd[7].compare_data_fall2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ), .I4(\cmp_err_4to1.compare_err_f2_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f2_i_3_n_0 ), .O(compare_err_f20)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f2_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall2_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ), .O(\cmp_err_4to1.compare_err_f2_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f2_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall2_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ), .O(\cmp_err_4to1.compare_err_f2_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_f2_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f20), .Q(\cmp_err_4to1.compare_err_f2_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f3_i_1 (.I0(\gen_mux_rd[7].compare_data_fall3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ), .I4(\cmp_err_4to1.compare_err_f3_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_f3_i_3_n_0 ), .O(compare_err_f30)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f3_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall3_r1_reg ), .I2(\gen_mux_rd[5].compare_data_fall3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ), .O(\cmp_err_4to1.compare_err_f3_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_f3_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall3_r1_reg ), .I2(\gen_mux_rd[2].compare_data_fall3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ), .O(\cmp_err_4to1.compare_err_f3_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_f3_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_f30), .Q(\cmp_err_4to1.compare_err_f3_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hAAAAAAAEAAAAAEAA)) \cmp_err_4to1.compare_err_i_1 (.I0(compare_err2), .I1(Q[0]), .I2(Q[4]), .I3(Q[1]), .I4(Q[3]), .I5(Q[2]), .O(compare_err0)); LUT5 #( .INIT(32'hFFFFFFFE)) \cmp_err_4to1.compare_err_i_2 (.I0(\cmp_err_4to1.compare_err_r0_reg_n_0 ), .I1(\cmp_err_4to1.compare_err_f2_reg_n_0 ), .I2(\cmp_err_4to1.compare_err_r2_reg_n_0 ), .I3(\cmp_err_4to1.compare_err_r3_reg_n_0 ), .I4(\cmp_err_4to1.compare_err_i_4_n_0 ), .O(compare_err086_out__0)); LUT2 #( .INIT(4'hE)) \cmp_err_4to1.compare_err_i_3 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I1(rstdiv0_sync_r1_reg_rep__23), .O(compare_err2)); LUT4 #( .INIT(16'hFFFE)) \cmp_err_4to1.compare_err_i_4 (.I0(\cmp_err_4to1.compare_err_r1_reg_n_0 ), .I1(\cmp_err_4to1.compare_err_f1_reg_n_0 ), .I2(\cmp_err_4to1.compare_err_f3_reg_n_0 ), .I3(\cmp_err_4to1.compare_err_f0_reg_n_0 ), .O(\cmp_err_4to1.compare_err_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r0_i_1 (.I0(\gen_mux_rd[7].compare_data_rise0_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ), .I4(\cmp_err_4to1.compare_err_r0_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r0_i_3_n_0 ), .O(compare_err_r00)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r0_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise0_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ), .O(\cmp_err_4to1.compare_err_r0_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r0_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise0_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise0_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise0_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ), .O(\cmp_err_4to1.compare_err_r0_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_r0_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r00), .Q(\cmp_err_4to1.compare_err_r0_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r1_i_1 (.I0(\gen_mux_rd[7].compare_data_rise1_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ), .I4(\cmp_err_4to1.compare_err_r1_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r1_i_3_n_0 ), .O(compare_err_r10)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r1_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise1_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ), .O(\cmp_err_4to1.compare_err_r1_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r1_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise1_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise1_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ), .O(\cmp_err_4to1.compare_err_r1_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_r1_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r10), .Q(\cmp_err_4to1.compare_err_r1_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r2_i_1 (.I0(\gen_mux_rd[7].compare_data_rise2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ), .I4(\cmp_err_4to1.compare_err_r2_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r2_i_3_n_0 ), .O(compare_err_r20)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r2_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise2_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ), .O(\cmp_err_4to1.compare_err_r2_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r2_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise2_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise2_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ), .O(\cmp_err_4to1.compare_err_r2_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_r2_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r20), .Q(\cmp_err_4to1.compare_err_r2_reg_n_0 ), .R(compare_err0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r3_i_1 (.I0(\gen_mux_rd[7].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ), .I4(\cmp_err_4to1.compare_err_r3_i_2_n_0 ), .I5(\cmp_err_4to1.compare_err_r3_i_3_n_0 ), .O(compare_err_r30)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r3_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[3].compare_data_rise3_r1_reg ), .I2(\gen_mux_rd[5].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ), .I4(\gen_mux_rd[4].compare_data_rise3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ), .O(\cmp_err_4to1.compare_err_r3_i_2_n_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \cmp_err_4to1.compare_err_r3_i_3 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[0].compare_data_rise3_r1_reg ), .I2(\gen_mux_rd[2].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ), .I4(\gen_mux_rd[1].compare_data_rise3_r1_reg ), .I5(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ), .O(\cmp_err_4to1.compare_err_r3_i_3_n_0 )); FDRE \cmp_err_4to1.compare_err_r3_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err_r30), .Q(\cmp_err_4to1.compare_err_r3_reg_n_0 ), .R(compare_err0)); FDRE \cmp_err_4to1.compare_err_reg (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(compare_err086_out__0), .Q(\cmp_err_4to1.compare_err_reg_n_0 ), .R(compare_err0)); LUT5 #( .INIT(32'hFFFFFFEA)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_1 (.I0(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ), .I1(compare_err_pb_and2), .I2(err_chk_invalid), .I3(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I4(rstdiv0_sync_r1_reg_rep__23), .O(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_2 (.I0(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ), .I1(\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[0].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ), .I4(\gen_mux_rd[0].compare_data_rise3_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ), .O(p_75_out)); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'h4000)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(Q[0]), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( .INIT(32'h04000010)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[3]), .I4(Q[2]), .O(compare_err_pb_and2)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall0_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ), .I3(\gen_mux_rd[0].compare_data_rise1_r1_reg ), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6 (.I0(\gen_mux_rd[0].compare_data_rise2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ), .I2(\gen_mux_rd[0].compare_data_fall1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7 (.I0(\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[0].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[0].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 )); FDRE \cmp_err_pb_4to1.(null)[0].compare_err_pb_reg[0] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_75_out), .Q(compare_err_pb[0]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_1 (.I0(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[1].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[1].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ), .O(p_64_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2 (.I0(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[1].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[1].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3 (.I0(\gen_mux_rd[1].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[1].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4 (.I0(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[1].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[1].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[1].compare_err_pb_reg[1] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_64_out), .Q(compare_err_pb[1]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_1 (.I0(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[2].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[2].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ), .O(p_55_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2 (.I0(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[2].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[2].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3 (.I0(\gen_mux_rd[2].compare_data_fall3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ), .I2(\gen_mux_rd[2].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4 (.I0(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[2].compare_data_rise0_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ), .I3(\gen_mux_rd[2].compare_data_rise3_r1_reg ), .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[2].compare_err_pb_reg[2] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_55_out), .Q(compare_err_pb[2]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_1 (.I0(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[3].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[3].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ), .O(p_46_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[3].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3 (.I0(\gen_mux_rd[3].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[3].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4 (.I0(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[3].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[3].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[3].compare_err_pb_reg[3] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_46_out), .Q(compare_err_pb[3]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_1 (.I0(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[4].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[4].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ), .O(p_37_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2 (.I0(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[4].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[4].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3 (.I0(\gen_mux_rd[4].compare_data_rise3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ), .I2(\gen_mux_rd[4].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4 (.I0(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[4].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[4].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[4].compare_err_pb_reg[4] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_37_out), .Q(compare_err_pb[4]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_1 (.I0(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[5].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ), .I4(\gen_mux_rd[5].compare_data_fall0_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ), .O(p_28_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2 (.I0(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ), .I1(\gen_mux_rd[5].compare_data_fall1_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ), .I3(\gen_mux_rd[5].compare_data_rise2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3 (.I0(\gen_mux_rd[5].compare_data_fall3_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ), .I2(\gen_mux_rd[5].compare_data_rise3_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4 (.I0(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ), .I1(\gen_mux_rd[5].compare_data_rise0_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ), .I3(\gen_mux_rd[5].compare_data_fall2_r1_reg ), .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[5].compare_err_pb_reg[5] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_28_out), .Q(compare_err_pb[5]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_1 (.I0(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[6].compare_data_fall2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[6].compare_data_fall1_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ), .O(p_19_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2 (.I0(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[6].compare_data_rise3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ), .I3(\gen_mux_rd[6].compare_data_fall3_r1_reg ), .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3 (.I0(\gen_mux_rd[6].compare_data_fall0_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ), .I2(\gen_mux_rd[6].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4 (.I0(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ), .I1(\gen_mux_rd[6].compare_data_rise2_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[6].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[6].compare_err_pb_reg[6] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_19_out), .Q(compare_err_pb[6]), .R(p_66_out)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_1 (.I0(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ), .I2(\gen_mux_rd[7].compare_data_rise1_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ), .I4(\gen_mux_rd[7].compare_data_fall1_r1_reg ), .I5(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ), .O(p_10_out)); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2 (.I0(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ), .I1(\gen_mux_rd[7].compare_data_rise3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ), .I3(\gen_mux_rd[7].compare_data_fall0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3 (.I0(\gen_mux_rd[7].compare_data_fall2_r1_reg ), .I1(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ), .I2(\gen_mux_rd[7].compare_data_rise2_r1_reg ), .I3(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ), .I4(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ), .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 )); LUT4 #( .INIT(16'h6FF6)) \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4 (.I0(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ), .I1(\gen_mux_rd[7].compare_data_fall3_r1_reg ), .I2(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ), .I3(\gen_mux_rd[7].compare_data_rise0_r1_reg ), .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 )); FDRE \cmp_err_pb_4to1.(null)[7].compare_err_pb_reg[7] (.C(CLK), .CE(rd_valid_r2_reg_n_0), .D(p_10_out), .Q(compare_err_pb[7]), .R(p_66_out)); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT5 #( .INIT(32'h80000000)) cnt_wait_state_i_1 (.I0(wait_state_cnt_en_r), .I1(wait_state_cnt_r_reg__0[3]), .I2(wait_state_cnt_r_reg__0[2]), .I3(wait_state_cnt_r_reg__0[0]), .I4(wait_state_cnt_r_reg__0[1]), .O(cnt_wait_state_i_1_n_0)); FDRE cnt_wait_state_reg (.C(CLK), .CE(1'b1), .D(cnt_wait_state_i_1_n_0), .Q(cnt_wait_state), .R(1'b0)); LUT6 #( .INIT(64'hAAAAABAAAAAAAAAA)) compare_err_latch_i_1 (.I0(compare_err_latch_i_2_n_0), .I1(compare_err_latch_reg_0), .I2(Q[2]), .I3(\cmp_err_4to1.compare_err_reg_n_0 ), .I4(Q[0]), .I5(Q[1]), .O(compare_err_latch_i_1_n_0)); LUT6 #( .INIT(64'h0000000200000000)) compare_err_latch_i_2 (.I0(compare_err_latch_reg_n_0), .I1(Q[2]), .I2(Q[3]), .I3(Q[0]), .I4(Q[4]), .I5(Q[1]), .O(compare_err_latch_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'hE)) compare_err_latch_i_3 (.I0(Q[3]), .I1(Q[4]), .O(compare_err_latch_reg_0)); FDRE compare_err_latch_reg (.C(CLK), .CE(1'b1), .D(compare_err_latch_i_1_n_0), .Q(compare_err_latch_reg_n_0), .R(1'b0)); LUT5 #( .INIT(32'h00002022)) compare_err_pb_and_i_1 (.I0(compare_err_pb_and_i_2_n_0), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(cnt_wait_state), .I3(compare_err_pb_and2), .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ), .O(compare_err_pb_and_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40000000)) compare_err_pb_and_i_2 (.I0(compare_err_pb_and_i_3_n_0), .I1(compare_err_pb[5]), .I2(compare_err_pb[4]), .I3(compare_err_pb[6]), .I4(compare_err_pb[7]), .I5(compare_err_pb_and_reg_n_0), .O(compare_err_pb_and_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'h7FFF)) compare_err_pb_and_i_3 (.I0(compare_err_pb[1]), .I1(compare_err_pb[0]), .I2(compare_err_pb[3]), .I3(compare_err_pb[2]), .O(compare_err_pb_and_i_3_n_0)); FDRE compare_err_pb_and_reg (.C(CLK), .CE(1'b1), .D(compare_err_pb_and_i_1_n_0), .Q(compare_err_pb_and_reg_n_0), .R(1'b0)); LUT5 #( .INIT(32'h00002022)) compare_err_pb_or_i_1 (.I0(compare_err_pb_or_i_2_n_0), .I1(rstdiv0_sync_r1_reg_rep__23), .I2(cnt_wait_state), .I3(compare_err_pb_and2), .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ), .O(compare_err_pb_or_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) compare_err_pb_or_i_2 (.I0(compare_err_pb_or_i_3_n_0), .I1(compare_err_pb[3]), .I2(compare_err_pb[2]), .I3(compare_err_pb[1]), .I4(compare_err_pb[0]), .I5(sel0[0]), .O(compare_err_pb_or_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT4 #( .INIT(16'h0001)) compare_err_pb_or_i_3 (.I0(compare_err_pb[6]), .I1(compare_err_pb[7]), .I2(compare_err_pb[5]), .I3(compare_err_pb[4]), .O(compare_err_pb_or_i_3_n_0)); FDRE compare_err_pb_or_reg (.C(CLK), .CE(1'b1), .D(compare_err_pb_or_i_1_n_0), .Q(sel0[0]), .R(1'b0)); FDRE complex_init_pi_dec_done_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_3 ), .Q(complex_init_pi_dec_done), .R(rstdiv0_sync_r1_reg_rep__2)); LUT6 #( .INIT(64'h88B88888B8B8B8B8)) complex_pi_incdec_done_i_2 (.I0(complex_pi_incdec_done_i_3_n_0), .I1(complex_pi_incdec_done_i_4_n_0), .I2(complex_pi_incdec_done_i_5_n_0), .I3(\prbs_state_r[1]_i_5_n_0 ), .I4(cnt_wait_state), .I5(complex_pi_incdec_done_i_6_n_0), .O(complex_pi_incdec_done_reg_0)); LUT6 #( .INIT(64'hC0F07373C0F04040)) complex_pi_incdec_done_i_3 (.I0(prbs_tap_en_r_reg_0), .I1(complex_pi_incdec_done_i_5_n_0), .I2(cnt_wait_state), .I3(p_3_in), .I4(complex_pi_incdec_done_i_6_n_0), .I5(\prbs_state_r[3]_i_4_n_0 ), .O(complex_pi_incdec_done_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT5 #( .INIT(32'h04000118)) complex_pi_incdec_done_i_4 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[2]), .I4(Q[3]), .O(complex_pi_incdec_done_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT5 #( .INIT(32'h04040834)) complex_pi_incdec_done_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[3]), .I4(Q[2]), .O(complex_pi_incdec_done_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT5 #( .INIT(32'hEFDCFFF7)) complex_pi_incdec_done_i_6 (.I0(Q[0]), .I1(Q[4]), .I2(Q[3]), .I3(Q[2]), .I4(Q[1]), .O(complex_pi_incdec_done_i_6_n_0)); FDRE complex_pi_incdec_done_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_4 ), .Q(complex_pi_incdec_done), .R(rstdiv0_sync_r1_reg_rep__2)); LUT1 #( .INIT(2'h1)) complex_victim_inc_i_2 (.I0(\rd_victim_sel_reg[2]_0 ), .O(complex_victim_inc__0)); FDRE complex_victim_inc_reg (.C(CLK), .CE(1'b1), .D(complex_victim_inc__0), .Q(\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT5 #( .INIT(32'hB8FFB8CC)) \dec_cnt[0]_i_1 (.I0(\dec_cnt_reg[0]_i_2_n_0 ), .I1(\largest_left_edge_reg_n_0_[5] ), .I2(\dec_cnt[0]_i_3_n_0 ), .I3(\smallest_right_edge_reg_n_0_[5] ), .I4(\dec_cnt[0]_i_4_n_0 ), .O(\dec_cnt[0]_i_1_n_0 )); LUT5 #( .INIT(32'hAFAFCFC0)) \dec_cnt[0]_i_11 (.I0(\dec_cnt[5]_i_6_n_0 ), .I1(\dec_cnt[0]_i_29_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_14_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[0]_i_11_n_0 )); LUT5 #( .INIT(32'hFFFFDE8E)) \dec_cnt[0]_i_13 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\dec_cnt[0]_i_14_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_32_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[0]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDFFDFFFF)) \dec_cnt[0]_i_14 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[0]_i_14_n_0 )); LUT6 #( .INIT(64'h7E733BEEE73EBEC3)) \dec_cnt[0]_i_15 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_15_n_0 )); LUT6 #( .INIT(64'h3E432BAEE6323AC3)) \dec_cnt[0]_i_16 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_16_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_17 (.I0(\dec_cnt[0]_i_33_n_0 ), .I1(\dec_cnt[0]_i_34_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_26_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[0]_i_35_n_0 ), .O(\dec_cnt[0]_i_17_n_0 )); LUT6 #( .INIT(64'h9996966669699999)) \dec_cnt[0]_i_20 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_20_n_0 )); LUT6 #( .INIT(64'hC29C39C323CE9C22)) \dec_cnt[0]_i_21 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_21_n_0 )); LUT6 #( .INIT(64'h25B649A565A55A64)) \dec_cnt[0]_i_22 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_22_n_0 )); LUT6 #( .INIT(64'h7DFEF57E08818110)) \dec_cnt[0]_i_23 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_23_n_0 )); LUT6 #( .INIT(64'h9796766669899991)) \dec_cnt[0]_i_24 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_24_n_0 )); LUT6 #( .INIT(64'h629C394323C69C32)) \dec_cnt[0]_i_25 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_25_n_0 )); LUT6 #( .INIT(64'h6B7F6AF74AB756A6)) \dec_cnt[0]_i_26 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_26_n_0 )); LUT6 #( .INIT(64'h3E732BEEE736BEC3)) \dec_cnt[0]_i_29 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_29_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_3 (.I0(\dec_cnt_reg[0]_i_7_n_0 ), .I1(\dec_cnt[0]_i_8_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[0]_i_9_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt_reg[0]_i_10_n_0 ), .O(\dec_cnt[0]_i_3_n_0 )); LUT6 #( .INIT(64'h3E532BEEE7323AC3)) \dec_cnt[0]_i_32 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_32_n_0 )); LUT6 #( .INIT(64'h9B96966669699999)) \dec_cnt[0]_i_33 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_33_n_0 )); LUT6 #( .INIT(64'hC29C39C323CE9C32)) \dec_cnt[0]_i_34 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_34_n_0 )); LUT6 #( .INIT(64'h7DBEF57E08C18110)) \dec_cnt[0]_i_35 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_35_n_0 )); LUT6 #( .INIT(64'hF00FE51A1ECFF00F)) \dec_cnt[0]_i_36 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_36_n_0 )); LUT6 #( .INIT(64'h3A755DAAA6558A15)) \dec_cnt[0]_i_37 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_37_n_0 )); LUT6 #( .INIT(64'h1CC32B8CC63238C1)) \dec_cnt[0]_i_38 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_38_n_0 )); LUT6 #( .INIT(64'hFF0F00E000F0FF3F)) \dec_cnt[0]_i_39 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_39_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \dec_cnt[0]_i_4 (.I0(\dec_cnt[0]_i_11_n_0 ), .I1(\largest_left_edge_reg_n_0_[4] ), .I2(\dec_cnt_reg[0]_i_12_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[0]_i_13_n_0 ), .O(\dec_cnt[0]_i_4_n_0 )); LUT6 #( .INIT(64'hF00F87E0708FF00F)) \dec_cnt[0]_i_40 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_40_n_0 )); LUT6 #( .INIT(64'h271D55AA8A55A285)) \dec_cnt[0]_i_41 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_41_n_0 )); LUT6 #( .INIT(64'h1C532BCCC736BCC1)) \dec_cnt[0]_i_42 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_42_n_0 )); LUT6 #( .INIT(64'hF00F0FF0F00BF00F)) \dec_cnt[0]_i_43 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_43_n_0 )); LUT6 #( .INIT(64'h1DBED57E48C10110)) \dec_cnt[0]_i_44 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_44_n_0 )); LUT6 #( .INIT(64'h6A7F6AB75AB756AE)) \dec_cnt[0]_i_45 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[0]_i_45_n_0 )); LUT6 #( .INIT(64'h633C33CCDC63C63A)) \dec_cnt[0]_i_46 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_46_n_0 )); LUT6 #( .INIT(64'h9796666669999995)) \dec_cnt[0]_i_47 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[0]_i_47_n_0 )); LUT5 #( .INIT(32'hFFFFDE8E)) \dec_cnt[0]_i_5 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\dec_cnt[0]_i_14_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_15_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[0]_i_5_n_0 )); LUT6 #( .INIT(64'hF3B8FFFFF3B80000)) \dec_cnt[0]_i_6 (.I0(\dec_cnt[0]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[0]_i_14_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt[0]_i_17_n_0 ), .O(\dec_cnt[0]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_8 (.I0(\dec_cnt[0]_i_20_n_0 ), .I1(\dec_cnt[0]_i_21_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_22_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[0]_i_23_n_0 ), .O(\dec_cnt[0]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[0]_i_9 (.I0(\dec_cnt[0]_i_24_n_0 ), .I1(\dec_cnt[0]_i_25_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[0]_i_26_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[0]_i_23_n_0 ), .O(\dec_cnt[0]_i_9_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[1]_i_1 (.I0(\dec_cnt[1]_i_2_n_0 ), .I1(\largest_left_edge_reg_n_0_[5] ), .I2(\dec_cnt[1]_i_3_n_0 ), .I3(\smallest_right_edge_reg_n_0_[5] ), .I4(\dec_cnt[1]_i_4_n_0 ), .O(\dec_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hA61AAFB6BE5BA69A)) \dec_cnt[1]_i_13 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_13_n_0 )); LUT6 #( .INIT(64'hE73BE633C673CE62)) \dec_cnt[1]_i_15 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_15_n_0 )); LUT6 #( .INIT(64'h0A7F8AFE3F017F11)) \dec_cnt[1]_i_16 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_16_n_0 )); LUT6 #( .INIT(64'hE731E633C673CE62)) \dec_cnt[1]_i_19 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_19_n_0 )); LUT5 #( .INIT(32'hDE8EFFFF)) \dec_cnt[1]_i_2 (.I0(\largest_left_edge_reg_n_0_[4] ), .I1(\dec_cnt[1]_i_5_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[1]_i_6_n_0 ), .I4(\smallest_right_edge_reg_n_0_[5] ), .O(\dec_cnt[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0A7F8AFE7F017F11)) \dec_cnt[1]_i_20 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_20_n_0 )); LUT6 #( .INIT(64'h8F8E0E1EE787878F)) \dec_cnt[1]_i_21 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_21_n_0 )); LUT6 #( .INIT(64'hE759A651AE758A64)) \dec_cnt[1]_i_22 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_22_n_0 )); LUT6 #( .INIT(64'hE579A561A6E596A4)) \dec_cnt[1]_i_25 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_25_n_0 )); LUT6 #( .INIT(64'h8F8E1E1EE787878F)) \dec_cnt[1]_i_26 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_26_n_0 )); LUT6 #( .INIT(64'h6A7FAA7E3F017F11)) \dec_cnt[1]_i_27 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_27_n_0 )); LUT6 #( .INIT(64'hDAD2DAF22F4F4F4A)) \dec_cnt[1]_i_28 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_28_n_0 )); LUT6 #( .INIT(64'h6759A659A6758A64)) \dec_cnt[1]_i_29 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_29_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[1]_i_3 (.I0(\dec_cnt_reg[1]_i_7_n_0 ), .I1(\dec_cnt[1]_i_8_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[1]_i_9_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt_reg[1]_i_10_n_0 ), .O(\dec_cnt[1]_i_3_n_0 )); LUT6 #( .INIT(64'h878E8E1EE7E78787)) \dec_cnt[1]_i_30 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_30_n_0 )); LUT6 #( .INIT(64'h6663866696869696)) \dec_cnt[1]_i_31 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_31_n_0 )); LUT6 #( .INIT(64'h89C991C9EC6CCC6C)) \dec_cnt[1]_i_32 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_32_n_0 )); LUT6 #( .INIT(64'h869AA5969E5BA69A)) \dec_cnt[1]_i_33 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_33_n_0 )); LUT6 #( .INIT(64'h6966696966866666)) \dec_cnt[1]_i_34 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_34_n_0 )); LUT6 #( .INIT(64'h6616666696991696)) \dec_cnt[1]_i_35 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_35_n_0 )); LUT6 #( .INIT(64'hCF00F38C8C33F700)) \dec_cnt[1]_i_36 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_36_n_0 )); LUT6 #( .INIT(64'h861AA5969E5BA69A)) \dec_cnt[1]_i_37 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[1]_i_37_n_0 )); LUT6 #( .INIT(64'h6669666696669296)) \dec_cnt[1]_i_38 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[1]_i_38_n_0 )); LUT6 #( .INIT(64'hFFFF00FFB8FFB800)) \dec_cnt[1]_i_4 (.I0(\dec_cnt_reg[1]_i_11_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt_reg[1]_i_12_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[1]_i_5_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[1]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'hF3B8)) \dec_cnt[1]_i_5 (.I0(\dec_cnt[1]_i_13_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[1]_i_5_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[1]_i_6 (.I0(\dec_cnt_reg[1]_i_14_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[1]_i_15_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[1]_i_16_n_0 ), .O(\dec_cnt[1]_i_6_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[1]_i_8 (.I0(\dec_cnt_reg[1]_i_14_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[1]_i_19_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[1]_i_20_n_0 ), .O(\dec_cnt[1]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[1]_i_9 (.I0(\dec_cnt[1]_i_21_n_0 ), .I1(\dec_cnt[1]_i_22_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[1]_i_15_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[1]_i_20_n_0 ), .O(\dec_cnt[1]_i_9_n_0 )); LUT6 #( .INIT(64'h42C444C433232323)) \dec_cnt[2]_i_10 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_10_n_0 )); LUT6 #( .INIT(64'hDC9CC4DC9DBDDC9D)) \dec_cnt[2]_i_11 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEFEEEEF7)) \dec_cnt[2]_i_12 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_12_n_0 )); LUT6 #( .INIT(64'h26A22524AAAAA4A4)) \dec_cnt[2]_i_13 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'hDF)) \dec_cnt[2]_i_14 (.I0(\smallest_right_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT4 #( .INIT(16'h00AE)) \dec_cnt[2]_i_15 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFBDABEB)) \dec_cnt[2]_i_17 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_17_n_0 )); LUT6 #( .INIT(64'h26A225A4AAAAA4A4)) \dec_cnt[2]_i_18 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_18_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_19 (.I0(\dec_cnt[2]_i_25_n_0 ), .I1(\dec_cnt[2]_i_26_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_27_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_28_n_0 ), .O(\dec_cnt[2]_i_19_n_0 )); LUT6 #( .INIT(64'hBBBB88BBB8BBB888)) \dec_cnt[2]_i_2 (.I0(\dec_cnt_reg[2]_i_4_n_0 ), .I1(\smallest_right_edge_reg_n_0_[5] ), .I2(\dec_cnt[2]_i_5_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[2]_i_6_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_20 (.I0(\dec_cnt[2]_i_10_n_0 ), .I1(\dec_cnt[2]_i_29_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_17_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_30_n_0 ), .O(\dec_cnt[2]_i_20_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[2]_i_21 (.I0(\dec_cnt_reg[2]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[2]_i_31_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[2]_i_30_n_0 ), .O(\dec_cnt[2]_i_21_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_22 (.I0(\dec_cnt[2]_i_32_n_0 ), .I1(\dec_cnt[2]_i_33_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_27_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_34_n_0 ), .O(\dec_cnt[2]_i_22_n_0 )); LUT6 #( .INIT(64'hDCC49DC49DCCB9DD)) \dec_cnt[2]_i_23 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_23_n_0 )); LUT6 #( .INIT(64'h424442C433232323)) \dec_cnt[2]_i_24 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_24_n_0 )); LUT6 #( .INIT(64'h242422242226B222)) \dec_cnt[2]_i_25 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_25_n_0 )); LUT6 #( .INIT(64'hB39BB39BD9CDD9D9)) \dec_cnt[2]_i_26 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_26_n_0 )); LUT6 #( .INIT(64'hCF8FFFCFF7FFF3FF)) \dec_cnt[2]_i_27 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_27_n_0 )); LUT6 #( .INIT(64'h115100108808AA8A)) \dec_cnt[2]_i_28 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_28_n_0 )); LUT6 #( .INIT(64'hDCC49DCC9DCCB9DD)) \dec_cnt[2]_i_29 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_29_n_0 )); LUT5 #( .INIT(32'hDE8EFFFF)) \dec_cnt[2]_i_3 (.I0(\largest_left_edge_reg_n_0_[4] ), .I1(\dec_cnt[2]_i_6_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[2]_i_7_n_0 ), .I4(\smallest_right_edge_reg_n_0_[5] ), .O(\dec_cnt[2]_i_3_n_0 )); LUT6 #( .INIT(64'h22A225A4AAAAA4A4)) \dec_cnt[2]_i_30 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF77011501)) \dec_cnt[2]_i_31 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_31_n_0 )); LUT6 #( .INIT(64'h00204404AAAA22A2)) \dec_cnt[2]_i_32 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[2]_i_32_n_0 )); LUT6 #( .INIT(64'hBB9BB39BD9CDD9D9)) \dec_cnt[2]_i_33 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_33_n_0 )); LUT6 #( .INIT(64'h2444242422223222)) \dec_cnt[2]_i_34 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[2]_i_34_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[2]_i_5 (.I0(\dec_cnt[2]_i_10_n_0 ), .I1(\dec_cnt[2]_i_11_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[2]_i_12_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[2]_i_13_n_0 ), .O(\dec_cnt[2]_i_5_n_0 )); LUT6 #( .INIT(64'hEFEAFFFFFFFFFFFF)) \dec_cnt[2]_i_6 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\dec_cnt[2]_i_14_n_0 ), .I2(\largest_left_edge_reg_n_0_[2] ), .I3(\dec_cnt[2]_i_15_n_0 ), .I4(\smallest_right_edge_reg_n_0_[2] ), .I5(\smallest_right_edge_reg_n_0_[3] ), .O(\dec_cnt[2]_i_6_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[2]_i_7 (.I0(\dec_cnt_reg[2]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[2]_i_17_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[2]_i_18_n_0 ), .O(\dec_cnt[2]_i_7_n_0 )); LUT5 #( .INIT(32'hB8FFB8CC)) \dec_cnt[3]_i_1 (.I0(\dec_cnt[3]_i_2_n_0 ), .I1(\largest_left_edge_reg_n_0_[5] ), .I2(\dec_cnt[3]_i_3_n_0 ), .I3(\smallest_right_edge_reg_n_0_[5] ), .I4(\dec_cnt[3]_i_4_n_0 ), .O(\dec_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[3]_i_10 (.I0(\dec_cnt[3]_i_12_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_5_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[3]_i_16_n_0 ), .O(\dec_cnt[3]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[3]_i_11 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\dec_cnt[3]_i_21_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[3]_i_19_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[3]_i_22_n_0 ), .O(\dec_cnt[3]_i_11_n_0 )); LUT6 #( .INIT(64'hBBBBBBBBBB8BBBBB)) \dec_cnt[3]_i_12 (.I0(\dec_cnt[3]_i_23_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\dec_cnt[4]_i_11_n_0 ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_12_n_0 )); LUT6 #( .INIT(64'hBBB888B8BBBBBBBB)) \dec_cnt[3]_i_13 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_24_n_0 ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\dec_cnt[3]_i_25_n_0 ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'hFFFFBFAA)) \dec_cnt[3]_i_14 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF775FFFF)) \dec_cnt[3]_i_15 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_15_n_0 )); LUT6 #( .INIT(64'hF1115111FFFFFFFF)) \dec_cnt[3]_i_16 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[2] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_16_n_0 )); LUT6 #( .INIT(64'h6C6C66642626B226)) \dec_cnt[3]_i_17 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_17_n_0 )); LUT6 #( .INIT(64'hB8883333B8880000)) \dec_cnt[3]_i_18 (.I0(\dec_cnt[3]_i_26_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[4]_i_15_n_0 ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\largest_left_edge_reg_n_0_[2] ), .I5(\dec_cnt[3]_i_27_n_0 ), .O(\dec_cnt[3]_i_18_n_0 )); LUT6 #( .INIT(64'hCF8FFFCFFFFFFFFF)) \dec_cnt[3]_i_19 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_19_n_0 )); LUT6 #( .INIT(64'hFFFF00FFB8FFB800)) \dec_cnt[3]_i_2 (.I0(\dec_cnt[3]_i_5_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_6_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[3]_i_7_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000AB2A2222)) \dec_cnt[3]_i_20 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_20_n_0 )); LUT6 #( .INIT(64'h4444DD4500000000)) \dec_cnt[3]_i_21 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_21_n_0 )); LUT6 #( .INIT(64'h5515110100000000)) \dec_cnt[3]_i_22 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFCDDD4CCC)) \dec_cnt[3]_i_23 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[0] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_23_n_0 )); LUT2 #( .INIT(4'h1)) \dec_cnt[3]_i_24 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h8CCF)) \dec_cnt[3]_i_25 (.I0(\smallest_right_edge_reg_n_0_[0] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT5 #( .INIT(32'h445455D5)) \dec_cnt[3]_i_26 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[3]_i_26_n_0 )); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'hAAFB0000)) \dec_cnt[3]_i_27 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .I4(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[3]_i_27_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \dec_cnt[3]_i_3 (.I0(\dec_cnt[3]_i_8_n_0 ), .I1(\dec_cnt[3]_i_9_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[3]_i_10_n_0 ), .I4(\largest_left_edge_reg_n_0_[4] ), .I5(\dec_cnt[3]_i_11_n_0 ), .O(\dec_cnt[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFF00FFB8FFB800)) \dec_cnt[3]_i_4 (.I0(\dec_cnt[3]_i_12_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_13_n_0 ), .I3(\smallest_right_edge_reg_n_0_[4] ), .I4(\dec_cnt[3]_i_7_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'hEFE0FFFFEFE00000)) \dec_cnt[3]_i_5 (.I0(\dec_cnt[4]_i_16_n_0 ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\largest_left_edge_reg_n_0_[2] ), .I3(\dec_cnt[3]_i_14_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[3]_i_15_n_0 ), .O(\dec_cnt[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'hB8)) \dec_cnt[3]_i_6 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_16_n_0 ), .O(\dec_cnt[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'hF3B8)) \dec_cnt[3]_i_7 (.I0(\dec_cnt[3]_i_17_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[3]_i_7_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \dec_cnt[3]_i_8 (.I0(\dec_cnt[3]_i_18_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_19_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\dec_cnt[3]_i_20_n_0 ), .O(\dec_cnt[3]_i_8_n_0 )); LUT4 #( .INIT(16'h88B8)) \dec_cnt[3]_i_9 (.I0(\dec_cnt[3]_i_5_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[3]_i_16_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[3]_i_9_n_0 )); LUT6 #( .INIT(64'hEFEAFFFF4540AAAA)) \dec_cnt[4]_i_1 (.I0(\largest_left_edge_reg_n_0_[5] ), .I1(\dec_cnt_reg[4]_i_2_n_0 ), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\dec_cnt[4]_i_3_n_0 ), .I4(\smallest_right_edge_reg_n_0_[5] ), .I5(\dec_cnt[4]_i_4_n_0 ), .O(\dec_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'hF3B8)) \dec_cnt[4]_i_10 (.I0(\dec_cnt[5]_i_5_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[4]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'h8E)) \dec_cnt[4]_i_11 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .O(\dec_cnt[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT5 #( .INIT(32'hBABBA2AA)) \dec_cnt[4]_i_12 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_12_n_0 )); LUT6 #( .INIT(64'h3000703000000000)) \dec_cnt[4]_i_13 (.I0(\largest_left_edge_reg_n_0_[0] ), .I1(\largest_left_edge_reg_n_0_[2] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF5D45DDDD)) \dec_cnt[4]_i_14 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h0400)) \dec_cnt[4]_i_15 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'hD0)) \dec_cnt[4]_i_16 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT4 #( .INIT(16'h20BA)) \dec_cnt[4]_i_17 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(\largest_left_edge_reg_n_0_[0] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[1] ), .O(\dec_cnt[4]_i_17_n_0 )); LUT6 #( .INIT(64'hB8BBBBBBB8BB8888)) \dec_cnt[4]_i_3 (.I0(\dec_cnt[4]_i_7_n_0 ), .I1(\largest_left_edge_reg_n_0_[4] ), .I2(\dec_cnt[4]_i_8_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .I4(\smallest_right_edge_reg_n_0_[3] ), .I5(\dec_cnt[4]_i_9_n_0 ), .O(\dec_cnt[4]_i_3_n_0 )); LUT4 #( .INIT(16'hF3B8)) \dec_cnt[4]_i_4 (.I0(\dec_cnt[4]_i_7_n_0 ), .I1(\smallest_right_edge_reg_n_0_[4] ), .I2(\dec_cnt[4]_i_10_n_0 ), .I3(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[4]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFFFFFFFF)) \dec_cnt[4]_i_5 (.I0(\largest_left_edge_reg_n_0_[3] ), .I1(\smallest_right_edge_reg_n_0_[2] ), .I2(\dec_cnt[4]_i_11_n_0 ), .I3(\smallest_right_edge_reg_n_0_[1] ), .I4(\largest_left_edge_reg_n_0_[2] ), .I5(\smallest_right_edge_reg_n_0_[3] ), .O(\dec_cnt[4]_i_5_n_0 )); LUT6 #( .INIT(64'hDFD0FFFFDFD0F0F0)) \dec_cnt[4]_i_6 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\dec_cnt[4]_i_12_n_0 ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[4]_i_13_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\dec_cnt[4]_i_14_n_0 ), .O(\dec_cnt[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'hB888)) \dec_cnt[4]_i_7 (.I0(\dec_cnt[5]_i_4_n_0 ), .I1(\smallest_right_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_5_n_0 ), .I3(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[4]_i_7_n_0 )); LUT6 #( .INIT(64'hFFDFFFFF5545DD5D)) \dec_cnt[4]_i_8 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_8_n_0 )); LUT6 #( .INIT(64'hAF0FAF00CF0FCF0F)) \dec_cnt[4]_i_9 (.I0(\dec_cnt[4]_i_15_n_0 ), .I1(\dec_cnt[4]_i_16_n_0 ), .I2(\largest_left_edge_reg_n_0_[3] ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\dec_cnt[4]_i_17_n_0 ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[4]_i_9_n_0 )); LUT4 #( .INIT(16'hEF4A)) \dec_cnt[5]_i_1 (.I0(\largest_left_edge_reg_n_0_[5] ), .I1(\dec_cnt[5]_i_2_n_0 ), .I2(\smallest_right_edge_reg_n_0_[5] ), .I3(\dec_cnt[5]_i_3_n_0 ), .O(\dec_cnt[5]_i_1_n_0 )); LUT6 #( .INIT(64'h0300000080808080)) \dec_cnt[5]_i_2 (.I0(\dec_cnt[5]_i_4_n_0 ), .I1(\smallest_right_edge_reg_n_0_[4] ), .I2(\smallest_right_edge_reg_n_0_[3] ), .I3(\dec_cnt[5]_i_5_n_0 ), .I4(\largest_left_edge_reg_n_0_[3] ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[5]_i_2_n_0 )); LUT6 #( .INIT(64'hF7FDD5FD51DC4054)) \dec_cnt[5]_i_3 (.I0(\smallest_right_edge_reg_n_0_[4] ), .I1(\largest_left_edge_reg_n_0_[3] ), .I2(\dec_cnt[5]_i_6_n_0 ), .I3(\smallest_right_edge_reg_n_0_[3] ), .I4(\dec_cnt[5]_i_5_n_0 ), .I5(\largest_left_edge_reg_n_0_[4] ), .O(\dec_cnt[5]_i_3_n_0 )); LUT5 #( .INIT(32'h00004000)) \dec_cnt[5]_i_4 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\dec_cnt[5]_i_7_n_0 ), .I3(\smallest_right_edge_reg_n_0_[2] ), .I4(\largest_left_edge_reg_n_0_[3] ), .O(\dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'h02000000ABAA2A22)) \dec_cnt[5]_i_5 (.I0(\largest_left_edge_reg_n_0_[2] ), .I1(\smallest_right_edge_reg_n_0_[1] ), .I2(\smallest_right_edge_reg_n_0_[0] ), .I3(\largest_left_edge_reg_n_0_[0] ), .I4(\largest_left_edge_reg_n_0_[1] ), .I5(\smallest_right_edge_reg_n_0_[2] ), .O(\dec_cnt[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDDFDFFFF)) \dec_cnt[5]_i_6 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(\largest_left_edge_reg_n_0_[1] ), .I2(\largest_left_edge_reg_n_0_[0] ), .I3(\smallest_right_edge_reg_n_0_[0] ), .I4(\smallest_right_edge_reg_n_0_[1] ), .I5(\largest_left_edge_reg_n_0_[2] ), .O(\dec_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'h4D)) \dec_cnt[5]_i_7 (.I0(\largest_left_edge_reg_n_0_[1] ), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\largest_left_edge_reg_n_0_[0] ), .O(\dec_cnt[5]_i_7_n_0 )); FDRE \dec_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\dec_cnt[0]_i_1_n_0 ), .Q(\prbs_dec_tap_cnt_reg[1]_0 [0]), .R(1'b0)); MUXF8 \dec_cnt_reg[0]_i_10 (.I0(\dec_cnt_reg[0]_i_27_n_0 ), .I1(\dec_cnt_reg[0]_i_28_n_0 ), .O(\dec_cnt_reg[0]_i_10_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[0]_i_12 (.I0(\dec_cnt_reg[0]_i_30_n_0 ), .I1(\dec_cnt_reg[0]_i_31_n_0 ), .O(\dec_cnt_reg[0]_i_12_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_18 (.I0(\dec_cnt[0]_i_36_n_0 ), .I1(\dec_cnt[0]_i_37_n_0 ), .O(\dec_cnt_reg[0]_i_18_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_19 (.I0(\dec_cnt[0]_i_38_n_0 ), .I1(\dec_cnt[0]_i_39_n_0 ), .O(\dec_cnt_reg[0]_i_19_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_2 (.I0(\dec_cnt[0]_i_5_n_0 ), .I1(\dec_cnt[0]_i_6_n_0 ), .O(\dec_cnt_reg[0]_i_2_n_0 ), .S(\smallest_right_edge_reg_n_0_[4] )); MUXF7 \dec_cnt_reg[0]_i_27 (.I0(\dec_cnt[0]_i_40_n_0 ), .I1(\dec_cnt[0]_i_41_n_0 ), .O(\dec_cnt_reg[0]_i_27_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_28 (.I0(\dec_cnt[0]_i_42_n_0 ), .I1(\dec_cnt[0]_i_43_n_0 ), .O(\dec_cnt_reg[0]_i_28_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_30 (.I0(\dec_cnt[0]_i_44_n_0 ), .I1(\dec_cnt[0]_i_45_n_0 ), .O(\dec_cnt_reg[0]_i_30_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[0]_i_31 (.I0(\dec_cnt[0]_i_46_n_0 ), .I1(\dec_cnt[0]_i_47_n_0 ), .O(\dec_cnt_reg[0]_i_31_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[0]_i_7 (.I0(\dec_cnt_reg[0]_i_18_n_0 ), .I1(\dec_cnt_reg[0]_i_19_n_0 ), .O(\dec_cnt_reg[0]_i_7_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); FDRE \dec_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\dec_cnt[1]_i_1_n_0 ), .Q(dec_cnt_reg[1]), .R(1'b0)); MUXF8 \dec_cnt_reg[1]_i_10 (.I0(\dec_cnt_reg[1]_i_23_n_0 ), .I1(\dec_cnt_reg[1]_i_24_n_0 ), .O(\dec_cnt_reg[1]_i_10_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_11 (.I0(\dec_cnt[1]_i_25_n_0 ), .I1(\dec_cnt[1]_i_26_n_0 ), .O(\dec_cnt_reg[1]_i_11_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_12 (.I0(\dec_cnt[1]_i_27_n_0 ), .I1(\dec_cnt[1]_i_28_n_0 ), .O(\dec_cnt_reg[1]_i_12_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_14 (.I0(\dec_cnt[1]_i_29_n_0 ), .I1(\dec_cnt[1]_i_30_n_0 ), .O(\dec_cnt_reg[1]_i_14_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_17 (.I0(\dec_cnt[1]_i_31_n_0 ), .I1(\dec_cnt[1]_i_32_n_0 ), .O(\dec_cnt_reg[1]_i_17_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_18 (.I0(\dec_cnt[1]_i_33_n_0 ), .I1(\dec_cnt[1]_i_34_n_0 ), .O(\dec_cnt_reg[1]_i_18_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_23 (.I0(\dec_cnt[1]_i_35_n_0 ), .I1(\dec_cnt[1]_i_36_n_0 ), .O(\dec_cnt_reg[1]_i_23_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF7 \dec_cnt_reg[1]_i_24 (.I0(\dec_cnt[1]_i_37_n_0 ), .I1(\dec_cnt[1]_i_38_n_0 ), .O(\dec_cnt_reg[1]_i_24_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[1]_i_7 (.I0(\dec_cnt_reg[1]_i_17_n_0 ), .I1(\dec_cnt_reg[1]_i_18_n_0 ), .O(\dec_cnt_reg[1]_i_7_n_0 ), .S(\smallest_right_edge_reg_n_0_[3] )); FDRE \dec_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\dec_cnt_reg[2]_i_1_n_0 ), .Q(dec_cnt_reg[2]), .R(1'b0)); MUXF7 \dec_cnt_reg[2]_i_1 (.I0(\dec_cnt[2]_i_2_n_0 ), .I1(\dec_cnt[2]_i_3_n_0 ), .O(\dec_cnt_reg[2]_i_1_n_0 ), .S(\largest_left_edge_reg_n_0_[5] )); MUXF7 \dec_cnt_reg[2]_i_16 (.I0(\dec_cnt[2]_i_23_n_0 ), .I1(\dec_cnt[2]_i_24_n_0 ), .O(\dec_cnt_reg[2]_i_16_n_0 ), .S(\largest_left_edge_reg_n_0_[3] )); MUXF8 \dec_cnt_reg[2]_i_4 (.I0(\dec_cnt_reg[2]_i_8_n_0 ), .I1(\dec_cnt_reg[2]_i_9_n_0 ), .O(\dec_cnt_reg[2]_i_4_n_0 ), .S(\smallest_right_edge_reg_n_0_[4] )); MUXF7 \dec_cnt_reg[2]_i_8 (.I0(\dec_cnt[2]_i_19_n_0 ), .I1(\dec_cnt[2]_i_20_n_0 ), .O(\dec_cnt_reg[2]_i_8_n_0 ), .S(\largest_left_edge_reg_n_0_[4] )); MUXF7 \dec_cnt_reg[2]_i_9 (.I0(\dec_cnt[2]_i_21_n_0 ), .I1(\dec_cnt[2]_i_22_n_0 ), .O(\dec_cnt_reg[2]_i_9_n_0 ), .S(\largest_left_edge_reg_n_0_[4] )); FDRE \dec_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\dec_cnt[3]_i_1_n_0 ), .Q(dec_cnt_reg[3]), .R(1'b0)); FDRE \dec_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(\dec_cnt[4]_i_1_n_0 ), .Q(dec_cnt_reg[4]), .R(1'b0)); MUXF7 \dec_cnt_reg[4]_i_2 (.I0(\dec_cnt[4]_i_5_n_0 ), .I1(\dec_cnt[4]_i_6_n_0 ), .O(\dec_cnt_reg[4]_i_2_n_0 ), .S(\largest_left_edge_reg_n_0_[4] )); FDRE \dec_cnt_reg[5] (.C(CLK), .CE(1'b1), .D(\dec_cnt[5]_i_1_n_0 ), .Q(\prbs_dec_tap_cnt_reg[1]_0 [1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT3 #( .INIT(8'h7F)) err_chk_invalid_i_1 (.I0(wait_state_cnt_r_reg__0[3]), .I1(wait_state_cnt_r_reg__0[1]), .I2(wait_state_cnt_r_reg__0[2]), .O(err_chk_invalid_i_1_n_0)); FDRE err_chk_invalid_reg (.C(CLK), .CE(1'b1), .D(err_chk_invalid_i_1_n_0), .Q(err_chk_invalid), .R(1'b0)); LUT2 #( .INIT(4'h2)) \fine_delay_mod[11]_i_8 (.I0(\fine_delay_mod_reg[20] ), .I1(\A[2]__2 ), .O(\fine_delay_mod_reg[5] )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) fine_delay_sel_i_2 (.I0(Q[4]), .I1(fine_delay_sel_i_4_n_0), .I2(bit_cnt_reg__0[7]), .I3(bit_cnt_reg__0[6]), .I4(bit_cnt_reg__0[4]), .I5(bit_cnt_reg__0[5]), .O(fine_delay_sel_reg_0)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( .INIT(8'hBD)) fine_delay_sel_i_3 (.I0(Q[1]), .I1(Q[2]), .I2(Q[3]), .O(fine_delay_sel_reg_1)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'hFFEF)) fine_delay_sel_i_4 (.I0(bit_cnt_reg__0[2]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[3]), .I3(bit_cnt_reg__0[1]), .O(fine_delay_sel_i_4_n_0)); FDRE fine_delay_sel_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_0 ), .Q(fine_delay_sel_r_reg), .R(rstdiv0_sync_r1_reg_rep__7)); LUT6 #( .INIT(64'h0100000022002200)) fine_dly_error_i_2 (.I0(Q[2]), .I1(Q[3]), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I5(Q[4]), .O(fine_dly_error_reg_0)); FDRE fine_dly_error_reg (.C(CLK), .CE(1'b1), .D(\dec_cnt_reg[0]_0 ), .Q(prbs_rdlvl_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__2)); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'h7)) fine_inc_stage_i_1 (.I0(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I1(\stage_cnt_reg_n_0_[0] ), .O(fine_inc_stage_i_1_n_0)); FDSE fine_inc_stage_reg (.C(CLK), .CE(1'b1), .D(fine_inc_stage_i_1_n_0), .Q(fine_inc_stage_reg_n_0), .S(rstdiv0_sync_r1_reg_rep__8)); LUT5 #( .INIT(32'h74777444)) \fine_pi_dec_cnt[0]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[0] ), .I1(Q[2]), .I2(\fine_pi_dec_cnt[0]_i_2_n_0 ), .I3(Q[1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_1 [0]), .O(\fine_pi_dec_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h8A8ABA8ABA8ABA8A)) \fine_pi_dec_cnt[0]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\stage_cnt_reg_n_0_[0] ), .I2(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I3(\fine_pi_dec_cnt_reg[3]_i_3_n_7 ), .I4(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I5(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\fine_pi_dec_cnt[0]_i_2_n_0 )); LUT6 #( .INIT(64'h9F909F9F9F909090)) \fine_pi_dec_cnt[1]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[0] ), .I1(\fine_pi_dec_cnt_reg_n_0_[1] ), .I2(Q[2]), .I3(\fine_pi_dec_cnt[1]_i_2_n_0 ), .I4(Q[1]), .I5(\calib_sel_reg[3]_0 ), .O(\fine_pi_dec_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h8A8ABA8ABA8ABA8A)) \fine_pi_dec_cnt[1]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I1(\stage_cnt_reg_n_0_[0] ), .I2(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I3(\fine_pi_dec_cnt_reg[3]_i_3_n_6 ), .I4(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I5(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\fine_pi_dec_cnt[1]_i_2_n_0 )); LUT5 #( .INIT(32'hE1FFE100)) \fine_pi_dec_cnt[2]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[1] ), .I1(\fine_pi_dec_cnt_reg_n_0_[0] ), .I2(\fine_pi_dec_cnt_reg_n_0_[2] ), .I3(Q[2]), .I4(\fine_pi_dec_cnt[2]_i_2_n_0 ), .O(\fine_pi_dec_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h88B8FFFF88B80000)) \fine_pi_dec_cnt[2]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\fine_pi_dec_cnt_reg[3]_i_3_n_5 ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(Q[1]), .I5(\calib_sel_reg[3]_1 ), .O(\fine_pi_dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFE01FFFFFE010000)) \fine_pi_dec_cnt[3]_i_1 (.I0(\fine_pi_dec_cnt_reg_n_0_[0] ), .I1(\fine_pi_dec_cnt_reg_n_0_[1] ), .I2(\fine_pi_dec_cnt_reg_n_0_[2] ), .I3(\fine_pi_dec_cnt_reg_n_0_[3] ), .I4(Q[2]), .I5(\fine_pi_dec_cnt[3]_i_2_n_0 ), .O(\fine_pi_dec_cnt[3]_i_1_n_0 )); (* HLUTNM = "lutpair3" *) LUT3 #( .INIT(8'h96)) \fine_pi_dec_cnt[3]_i_10 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(\smallest_right_edge_reg_n_0_[0] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\fine_pi_dec_cnt[3]_i_10_n_0 )); LUT6 #( .INIT(64'h88B8FFFF88B80000)) \fine_pi_dec_cnt[3]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\fine_pi_dec_cnt_reg[3]_i_3_n_4 ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(Q[1]), .I5(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .O(\fine_pi_dec_cnt[3]_i_2_n_0 )); (* HLUTNM = "lutpair1" *) LUT3 #( .INIT(8'hD4)) \fine_pi_dec_cnt[3]_i_4 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(dec_cnt_reg[2]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\fine_pi_dec_cnt[3]_i_4_n_0 )); (* HLUTNM = "lutpair0" *) LUT3 #( .INIT(8'hD4)) \fine_pi_dec_cnt[3]_i_5 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(dec_cnt_reg[1]), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\fine_pi_dec_cnt[3]_i_5_n_0 )); (* HLUTNM = "lutpair3" *) LUT2 #( .INIT(4'hB)) \fine_pi_dec_cnt[3]_i_6 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(\smallest_right_edge_reg_n_0_[0] ), .O(\fine_pi_dec_cnt[3]_i_6_n_0 )); (* HLUTNM = "lutpair2" *) LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[3]_i_7 (.I0(\smallest_right_edge_reg_n_0_[3] ), .I1(dec_cnt_reg[3]), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I3(\fine_pi_dec_cnt[3]_i_4_n_0 ), .O(\fine_pi_dec_cnt[3]_i_7_n_0 )); (* HLUTNM = "lutpair1" *) LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[3]_i_8 (.I0(\smallest_right_edge_reg_n_0_[2] ), .I1(dec_cnt_reg[2]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\fine_pi_dec_cnt[3]_i_5_n_0 ), .O(\fine_pi_dec_cnt[3]_i_8_n_0 )); (* HLUTNM = "lutpair0" *) LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[3]_i_9 (.I0(\smallest_right_edge_reg_n_0_[1] ), .I1(dec_cnt_reg[1]), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\fine_pi_dec_cnt[3]_i_6_n_0 ), .O(\fine_pi_dec_cnt[3]_i_9_n_0 )); LUT6 #( .INIT(64'h88B8FFFF88B80000)) \fine_pi_dec_cnt[4]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\fine_pi_dec_cnt_reg[5]_i_8_n_7 ), .I3(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I4(Q[1]), .I5(\calib_sel_reg[3]_2 ), .O(\fine_pi_dec_cnt[4]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFE0001)) \fine_pi_dec_cnt[4]_i_3 (.I0(\fine_pi_dec_cnt_reg_n_0_[3] ), .I1(\fine_pi_dec_cnt_reg_n_0_[2] ), .I2(\fine_pi_dec_cnt_reg_n_0_[1] ), .I3(\fine_pi_dec_cnt_reg_n_0_[0] ), .I4(\fine_pi_dec_cnt_reg_n_0_[4] ), .O(\fine_pi_dec_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'h8E71718E718E8E71)) \fine_pi_dec_cnt[5]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(dec_cnt_reg[4]), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I4(\smallest_right_edge_reg_n_0_[5] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\fine_pi_dec_cnt[5]_i_10_n_0 )); LUT4 #( .INIT(16'h9669)) \fine_pi_dec_cnt[5]_i_11 (.I0(\fine_pi_dec_cnt[5]_i_9_n_0 ), .I1(dec_cnt_reg[4]), .I2(\smallest_right_edge_reg_n_0_[4] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\fine_pi_dec_cnt[5]_i_11_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \fine_pi_dec_cnt[5]_i_3 (.I0(prbs_rdlvl_start_r), .I1(prbs_rdlvl_start_reg), .I2(Q[3]), .I3(Q[2]), .I4(Q[4]), .I5(Q[1]), .O(\fine_pi_dec_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'h1010180800001808)) \fine_pi_dec_cnt[5]_i_4 (.I0(Q[1]), .I1(Q[4]), .I2(Q[3]), .I3(cnt_wait_state), .I4(Q[2]), .I5(prbs_tap_en_r_reg_0), .O(\fine_pi_dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hBBB8FFFFBBB80000)) \fine_pi_dec_cnt[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\fine_pi_dec_cnt[5]_i_7_n_0 ), .I2(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I3(\fine_pi_dec_cnt_reg[5]_i_8_n_6 ), .I4(Q[1]), .I5(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]), .O(\fine_pi_dec_cnt[5]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \fine_pi_dec_cnt[5]_i_6 (.I0(\fine_pi_dec_cnt_reg_n_0_[4] ), .I1(\fine_pi_dec_cnt_reg_n_0_[0] ), .I2(\fine_pi_dec_cnt_reg_n_0_[1] ), .I3(\fine_pi_dec_cnt_reg_n_0_[2] ), .I4(\fine_pi_dec_cnt_reg_n_0_[3] ), .I5(\fine_pi_dec_cnt_reg_n_0_[5] ), .O(\fine_pi_dec_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'hB)) \fine_pi_dec_cnt[5]_i_7 (.I0(\stage_cnt_reg_n_0_[0] ), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .O(\fine_pi_dec_cnt[5]_i_7_n_0 )); (* HLUTNM = "lutpair2" *) LUT3 #( .INIT(8'hD4)) \fine_pi_dec_cnt[5]_i_9 (.I0(\smallest_right_edge_reg_n_0_[3] ), .I1(dec_cnt_reg[3]), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\fine_pi_dec_cnt[5]_i_9_n_0 )); FDRE \fine_pi_dec_cnt_reg[0] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[0]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \fine_pi_dec_cnt_reg[1] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[1]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \fine_pi_dec_cnt_reg[2] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[2]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \fine_pi_dec_cnt_reg[3] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt[3]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \fine_pi_dec_cnt_reg[3]_i_3 (.CI(1'b0), .CO({\fine_pi_dec_cnt_reg[3]_i_3_n_0 ,\fine_pi_dec_cnt_reg[3]_i_3_n_1 ,\fine_pi_dec_cnt_reg[3]_i_3_n_2 ,\fine_pi_dec_cnt_reg[3]_i_3_n_3 }), .CYINIT(1'b0), .DI({\fine_pi_dec_cnt[3]_i_4_n_0 ,\fine_pi_dec_cnt[3]_i_5_n_0 ,\fine_pi_dec_cnt[3]_i_6_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\fine_pi_dec_cnt_reg[3]_i_3_n_4 ,\fine_pi_dec_cnt_reg[3]_i_3_n_5 ,\fine_pi_dec_cnt_reg[3]_i_3_n_6 ,\fine_pi_dec_cnt_reg[3]_i_3_n_7 }), .S({\fine_pi_dec_cnt[3]_i_7_n_0 ,\fine_pi_dec_cnt[3]_i_8_n_0 ,\fine_pi_dec_cnt[3]_i_9_n_0 ,\fine_pi_dec_cnt[3]_i_10_n_0 })); FDRE \fine_pi_dec_cnt_reg[4] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt_reg[4]_i_1_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); MUXF7 \fine_pi_dec_cnt_reg[4]_i_1 (.I0(\fine_pi_dec_cnt[4]_i_2_n_0 ), .I1(\fine_pi_dec_cnt[4]_i_3_n_0 ), .O(\fine_pi_dec_cnt_reg[4]_i_1_n_0 ), .S(Q[2])); FDRE \fine_pi_dec_cnt_reg[5] (.C(CLK), .CE(fine_pi_dec_cnt), .D(\fine_pi_dec_cnt_reg[5]_i_2_n_0 ), .Q(\fine_pi_dec_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); MUXF7 \fine_pi_dec_cnt_reg[5]_i_1 (.I0(\fine_pi_dec_cnt[5]_i_3_n_0 ), .I1(\fine_pi_dec_cnt[5]_i_4_n_0 ), .O(fine_pi_dec_cnt), .S(Q[0])); MUXF7 \fine_pi_dec_cnt_reg[5]_i_2 (.I0(\fine_pi_dec_cnt[5]_i_5_n_0 ), .I1(\fine_pi_dec_cnt[5]_i_6_n_0 ), .O(\fine_pi_dec_cnt_reg[5]_i_2_n_0 ), .S(Q[2])); CARRY4 \fine_pi_dec_cnt_reg[5]_i_8 (.CI(\fine_pi_dec_cnt_reg[3]_i_3_n_0 ), .CO({\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED [3:1],\fine_pi_dec_cnt_reg[5]_i_8_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\fine_pi_dec_cnt[5]_i_9_n_0 }), .O({\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED [3:2],\fine_pi_dec_cnt_reg[5]_i_8_n_6 ,\fine_pi_dec_cnt_reg[5]_i_8_n_7 }), .S({1'b0,1'b0,\fine_pi_dec_cnt[5]_i_10_n_0 ,\fine_pi_dec_cnt[5]_i_11_n_0 })); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall0_r1), .Q(mux_rd_fall0_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall0_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall1_r1), .Q(mux_rd_fall1_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall1_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall2_r1), .Q(mux_rd_fall2_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall2_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_fall3_r1), .Q(mux_rd_fall3_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_fall3_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise0_r1), .Q(mux_rd_rise0_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise0_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise1_r1), .Q(mux_rd_rise1_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise1_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise2_r1), .Q(mux_rd_rise2_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise2_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r2_reg[0] (.C(CLK), .CE(mux_rd_valid_r), .D(mux_rd_rise3_r1), .Q(mux_rd_rise3_r2), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg[0] (.C(CLK), .CE(1'b1), .D(mux_rd_rise3_r2), .Q(\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg[1] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[1].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg[2] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[2].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg[3] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[3].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg[4] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[4].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg[5] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[5].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg[6] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[6].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_fall3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise0_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise1_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise2_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg[7] (.C(CLK), .CE(mux_rd_valid_r), .D(\gen_mux_rd[7].mux_rd_rise3_r1_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ), .R(1'b0)); FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ), .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_fall0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6] ), .Q(\gen_mux_rd[0].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_fall1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4] ), .Q(\gen_mux_rd[0].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_fall2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2] ), .Q(\gen_mux_rd[0].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_fall3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0] ), .Q(\gen_mux_rd[0].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_rise0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7] ), .Q(\gen_mux_rd[0].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_rise1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5] ), .Q(\gen_mux_rd[0].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_rise2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3] ), .Q(\gen_mux_rd[0].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].compare_data_rise3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1] ), .Q(\gen_mux_rd[0].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_9 ), .Q(mux_rd_fall0_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_25 ), .Q(mux_rd_fall1_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_41 ), .Q(mux_rd_fall2_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_57 ), .Q(mux_rd_fall3_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_1 ), .Q(mux_rd_rise0_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_17 ), .Q(mux_rd_rise1_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_33 ), .Q(mux_rd_rise2_r1), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\A[1]_49 ), .Q(mux_rd_rise3_r1), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_fall0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_0 ), .Q(\gen_mux_rd[1].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_fall1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_0 ), .Q(\gen_mux_rd[1].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_fall2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_0 ), .Q(\gen_mux_rd[1].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_fall3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_0 ), .Q(\gen_mux_rd[1].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_rise0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_0 ), .Q(\gen_mux_rd[1].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_rise1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_0 ), .Q(\gen_mux_rd[1].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_rise2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_0 ), .Q(\gen_mux_rd[1].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].compare_data_rise3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_0 ), .Q(\gen_mux_rd[1].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_10 ), .Q(\gen_mux_rd[1].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_26 ), .Q(\gen_mux_rd[1].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_42 ), .Q(\gen_mux_rd[1].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_58 ), .Q(\gen_mux_rd[1].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_2 ), .Q(\gen_mux_rd[1].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_18 ), .Q(\gen_mux_rd[1].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_34 ), .Q(\gen_mux_rd[1].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\A[1]_50 ), .Q(\gen_mux_rd[1].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_fall0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_1 ), .Q(\gen_mux_rd[2].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_fall1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_1 ), .Q(\gen_mux_rd[2].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_fall2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_1 ), .Q(\gen_mux_rd[2].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_fall3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_1 ), .Q(\gen_mux_rd[2].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_rise0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_1 ), .Q(\gen_mux_rd[2].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_rise1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_1 ), .Q(\gen_mux_rd[2].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_rise2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_1 ), .Q(\gen_mux_rd[2].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].compare_data_rise3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_1 ), .Q(\gen_mux_rd[2].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_11 ), .Q(\gen_mux_rd[2].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_27 ), .Q(\gen_mux_rd[2].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_43 ), .Q(\gen_mux_rd[2].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_59 ), .Q(\gen_mux_rd[2].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_3 ), .Q(\gen_mux_rd[2].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_19 ), .Q(\gen_mux_rd[2].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_35 ), .Q(\gen_mux_rd[2].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\A[1]_51 ), .Q(\gen_mux_rd[2].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_fall0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_2 ), .Q(\gen_mux_rd[3].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_fall1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_2 ), .Q(\gen_mux_rd[3].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_fall2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_2 ), .Q(\gen_mux_rd[3].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_fall3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_2 ), .Q(\gen_mux_rd[3].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_rise0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_2 ), .Q(\gen_mux_rd[3].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_rise1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_2 ), .Q(\gen_mux_rd[3].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_rise2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_2 ), .Q(\gen_mux_rd[3].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].compare_data_rise3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_2 ), .Q(\gen_mux_rd[3].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_12 ), .Q(\gen_mux_rd[3].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_28 ), .Q(\gen_mux_rd[3].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_44 ), .Q(\gen_mux_rd[3].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_60 ), .Q(\gen_mux_rd[3].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_4 ), .Q(\gen_mux_rd[3].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_20 ), .Q(\gen_mux_rd[3].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_36 ), .Q(\gen_mux_rd[3].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\A[1]_52 ), .Q(\gen_mux_rd[3].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_fall0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_3 ), .Q(\gen_mux_rd[4].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_fall1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_3 ), .Q(\gen_mux_rd[4].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_fall2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_3 ), .Q(\gen_mux_rd[4].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_fall3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_3 ), .Q(\gen_mux_rd[4].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_rise0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_3 ), .Q(\gen_mux_rd[4].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_rise1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_3 ), .Q(\gen_mux_rd[4].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_rise2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_3 ), .Q(\gen_mux_rd[4].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].compare_data_rise3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_3 ), .Q(\gen_mux_rd[4].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_13 ), .Q(\gen_mux_rd[4].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_29 ), .Q(\gen_mux_rd[4].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_45 ), .Q(\gen_mux_rd[4].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_61 ), .Q(\gen_mux_rd[4].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_5 ), .Q(\gen_mux_rd[4].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_21 ), .Q(\gen_mux_rd[4].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_37 ), .Q(\gen_mux_rd[4].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\A[1]_53 ), .Q(\gen_mux_rd[4].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_fall0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_4 ), .Q(\gen_mux_rd[5].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_fall1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_4 ), .Q(\gen_mux_rd[5].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_fall2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_4 ), .Q(\gen_mux_rd[5].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_fall3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_4 ), .Q(\gen_mux_rd[5].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_rise0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_4 ), .Q(\gen_mux_rd[5].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_rise1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_4 ), .Q(\gen_mux_rd[5].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_rise2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_4 ), .Q(\gen_mux_rd[5].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].compare_data_rise3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_4 ), .Q(\gen_mux_rd[5].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_14 ), .Q(\gen_mux_rd[5].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_30 ), .Q(\gen_mux_rd[5].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_46 ), .Q(\gen_mux_rd[5].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_62 ), .Q(\gen_mux_rd[5].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_6 ), .Q(\gen_mux_rd[5].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_22 ), .Q(\gen_mux_rd[5].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_38 ), .Q(\gen_mux_rd[5].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\A[1]_54 ), .Q(\gen_mux_rd[5].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_fall0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_5 ), .Q(\gen_mux_rd[6].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_fall1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_5 ), .Q(\gen_mux_rd[6].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_fall2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_5 ), .Q(\gen_mux_rd[6].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_fall3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_5 ), .Q(\gen_mux_rd[6].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_rise0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_5 ), .Q(\gen_mux_rd[6].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_rise1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_5 ), .Q(\gen_mux_rd[6].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_rise2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_5 ), .Q(\gen_mux_rd[6].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].compare_data_rise3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_5 ), .Q(\gen_mux_rd[6].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_15 ), .Q(\gen_mux_rd[6].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_31 ), .Q(\gen_mux_rd[6].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_47 ), .Q(\gen_mux_rd[6].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_63 ), .Q(\gen_mux_rd[6].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_7 ), .Q(\gen_mux_rd[6].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_23 ), .Q(\gen_mux_rd[6].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_39 ), .Q(\gen_mux_rd[6].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (.C(CLK), .CE(1'b1), .D(\A[1]_55 ), .Q(\gen_mux_rd[6].mux_rd_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_fall0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[6]_6 ), .Q(\gen_mux_rd[7].compare_data_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_fall1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[4]_6 ), .Q(\gen_mux_rd[7].compare_data_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_fall2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[2]_6 ), .Q(\gen_mux_rd[7].compare_data_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_fall3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[0]_6 ), .Q(\gen_mux_rd[7].compare_data_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_rise0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[7]_6 ), .Q(\gen_mux_rd[7].compare_data_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_rise1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[5]_6 ), .Q(\gen_mux_rd[7].compare_data_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_rise2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[3]_6 ), .Q(\gen_mux_rd[7].compare_data_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].compare_data_rise3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o_reg[1]_6 ), .Q(\gen_mux_rd[7].compare_data_rise3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_16 ), .Q(\gen_mux_rd[7].mux_rd_fall0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_32 ), .Q(\gen_mux_rd[7].mux_rd_fall1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_48 ), .Q(\gen_mux_rd[7].mux_rd_fall2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_64 ), .Q(\gen_mux_rd[7].mux_rd_fall3_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_8 ), .Q(\gen_mux_rd[7].mux_rd_rise0_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_24 ), .Q(\gen_mux_rd[7].mux_rd_rise1_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_40 ), .Q(\gen_mux_rd[7].mux_rd_rise2_r1_reg ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (.C(CLK), .CE(1'b1), .D(\A[1]_56 ), .Q(\gen_mux_rd[7].mux_rd_rise3_r1_reg ), .R(1'b0)); LUT6 #( .INIT(64'h00000001D000C000)) \genblk7[0].compare_err_pb_latch_r[0]_i_1 (.I0(cnt_wait_state), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .I4(Q[1]), .I5(Q[4]), .O(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[0].compare_err_pb_latch_r[0]_i_2 (.I0(compare_err_pb[0]), .I1(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .O(\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 )); FDRE \genblk7[0].compare_err_pb_latch_r_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ), .Q(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT2 #( .INIT(4'hE)) \genblk7[1].compare_err_pb_latch_r[1]_i_1 (.I0(compare_err_pb[1]), .I1(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .O(\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 )); FDRE \genblk7[1].compare_err_pb_latch_r_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ), .Q(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[2].compare_err_pb_latch_r[2]_i_1 (.I0(compare_err_pb[2]), .I1(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .O(\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 )); FDRE \genblk7[2].compare_err_pb_latch_r_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ), .Q(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[3].compare_err_pb_latch_r[3]_i_1 (.I0(compare_err_pb[3]), .I1(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .O(\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 )); FDRE \genblk7[3].compare_err_pb_latch_r_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ), .Q(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[4].compare_err_pb_latch_r[4]_i_1 (.I0(compare_err_pb[4]), .I1(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .O(\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 )); FDRE \genblk7[4].compare_err_pb_latch_r_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ), .Q(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[5].compare_err_pb_latch_r[5]_i_1 (.I0(compare_err_pb[5]), .I1(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .O(\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 )); FDRE \genblk7[5].compare_err_pb_latch_r_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ), .Q(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'hE)) \genblk7[6].compare_err_pb_latch_r[6]_i_1 (.I0(compare_err_pb[6]), .I1(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .O(\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 )); FDRE \genblk7[6].compare_err_pb_latch_r_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ), .Q(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \genblk7[7].compare_err_pb_latch_r[7]_i_1 (.I0(compare_err_pb[7]), .I1(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .O(\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 )); FDRE \genblk7[7].compare_err_pb_latch_r_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ), .Q(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 )); FDRE \genblk8[0].left_edge_found_pb_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk8[0].left_edge_found_pb_reg[0]_0 ), .Q(\genblk8[0].left_loss_pb_reg[0]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT1 #( .INIT(2'h1)) \genblk8[0].left_edge_pb[0]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\genblk8[0].left_edge_pb[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \genblk8[0].left_edge_pb[1]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_edge_pb[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'h78)) \genblk8[0].left_edge_pb[2]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].left_edge_pb[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT4 #( .INIT(16'h9555)) \genblk8[0].left_edge_pb[3]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_edge_pb[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT5 #( .INIT(32'hAAAA9555)) \genblk8[0].left_edge_pb[4]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .O(\genblk8[0].left_edge_pb[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00000004)) \genblk8[0].left_edge_pb[5]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[4]), .I3(Q[1]), .I4(Q[3]), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[0].left_edge_pb[5]_i_2 (.I0(p_154_out), .I1(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(left_edge_pb)); LUT6 #( .INIT(64'hAAAAAAAAA9999999)) \genblk8[0].left_edge_pb[5]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\genblk8[0].left_edge_pb[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[0].left_edge_pb[5]_i_4 (.I0(match_flag_pb[7]), .I1(\genblk8[0].left_edge_pb[5]_i_5_n_0 ), .I2(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .I3(match_flag_pb[6]), .I4(match_flag_pb[4]), .I5(match_flag_pb[5]), .O(\genblk8[0].left_loss_pb_reg[0]_1 )); LUT4 #( .INIT(16'hFFFE)) \genblk8[0].left_edge_pb[5]_i_5 (.I0(match_flag_pb[2]), .I1(match_flag_pb[3]), .I2(match_flag_pb[0]), .I3(match_flag_pb[1]), .O(\genblk8[0].left_edge_pb[5]_i_5_n_0 )); FDRE \genblk8[0].left_edge_pb_reg[0] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_edge_pb_reg[1] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_edge_pb_reg[2] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[2] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_edge_pb_reg[3] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[3] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_edge_pb_reg[4] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[4] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_edge_pb_reg[5] (.C(CLK), .CE(left_edge_pb), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[0].left_edge_pb_reg_n_0_[5] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'h0080)) \genblk8[0].left_edge_updated[0]_i_2 (.I0(Q[0]), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .O(\genblk8[7].left_edge_updated_reg[7]_0 )); FDRE \genblk8[0].left_edge_updated_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk8[0].left_edge_updated_reg[0]_0 ), .Q(D[0]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[0]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ), .O(\genblk8[0].left_loss_pb[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[1]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ), .O(\genblk8[0].left_loss_pb[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[2]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ), .O(\genblk8[0].left_loss_pb[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[3]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ), .O(\genblk8[0].left_loss_pb[3]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \genblk8[0].left_loss_pb[3]_i_3 (.I0(left_edge_ref[3]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .O(\genblk8[0].left_loss_pb[3]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \genblk8[0].left_loss_pb[3]_i_4 (.I0(left_edge_ref[1]), .O(\genblk8[0].left_loss_pb[3]_i_4_n_0 )); LUT4 #( .INIT(16'h6966)) \genblk8[0].left_loss_pb[3]_i_5 (.I0(left_edge_ref[3]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I2(left_edge_ref[2]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].left_loss_pb[3]_i_5_n_0 )); LUT3 #( .INIT(8'h96)) \genblk8[0].left_loss_pb[3]_i_6 (.I0(left_edge_ref[1]), .I1(left_edge_ref[2]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].left_loss_pb[3]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \genblk8[0].left_loss_pb[3]_i_7 (.I0(left_edge_ref[1]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_loss_pb[3]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].left_loss_pb[3]_i_8 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I1(left_edge_ref[0]), .O(\genblk8[0].left_loss_pb[3]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[4]_i_1 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ), .O(\genblk8[0].left_loss_pb[4]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[0].left_loss_pb[5]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[0].left_loss_pb_reg[0]_0 ), .I4(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(\genblk8[0].left_loss_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_10_n_0 )); LUT2 #( .INIT(4'hB)) \genblk8[0].left_loss_pb[5]_i_11 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I1(left_edge_ref[3]), .O(\genblk8[0].left_loss_pb[5]_i_11_n_0 )); LUT4 #( .INIT(16'hD22D)) \genblk8[0].left_loss_pb[5]_i_12 (.I0(left_edge_ref[4]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(left_edge_ref[5]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_12_n_0 )); LUT4 #( .INIT(16'hD22D)) \genblk8[0].left_loss_pb[5]_i_13 (.I0(left_edge_ref[3]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I2(left_edge_ref[4]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\genblk8[0].left_loss_pb[5]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_15 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_16 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_17 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_18 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'h40)) \genblk8[0].left_loss_pb[5]_i_2 (.I0(\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ), .I1(p_154_out), .I2(\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ), .O(\genblk8[0].left_loss_pb[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_23 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_23_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[0].left_loss_pb[5]_i_24 (.I0(left_edge_ref[4]), .I1(left_edge_ref[5]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I3(\genblk8[0].left_loss_pb[5]_i_31_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_24_n_0 )); LUT6 #( .INIT(64'h8CCCCEEEE0000888)) \genblk8[0].left_loss_pb[5]_i_25 (.I0(left_edge_ref[2]), .I1(left_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].left_loss_pb[5]_i_25_n_0 )); LUT4 #( .INIT(16'hCB80)) \genblk8[0].left_loss_pb[5]_i_26 (.I0(left_edge_ref[0]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I3(left_edge_ref[1]), .O(\genblk8[0].left_loss_pb[5]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_27_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[0].left_loss_pb[5]_i_28 (.I0(left_edge_ref[4]), .I1(left_edge_ref[5]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I3(\genblk8[0].left_loss_pb[5]_i_31_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_28_n_0 )); LUT6 #( .INIT(64'h4222211118888444)) \genblk8[0].left_loss_pb[5]_i_29 (.I0(left_edge_ref[2]), .I1(left_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].left_loss_pb[5]_i_29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT5 #( .INIT(32'h00400000)) \genblk8[0].left_loss_pb[5]_i_3 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(right_gain_pb)); LUT4 #( .INIT(16'h1842)) \genblk8[0].left_loss_pb[5]_i_30 (.I0(left_edge_ref[0]), .I1(left_edge_ref[1]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_loss_pb[5]_i_30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'h80)) \genblk8[0].left_loss_pb[5]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .O(\genblk8[0].left_loss_pb[5]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_8 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \genblk8[0].left_loss_pb[5]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].left_loss_pb[5]_i_9_n_0 )); FDRE \genblk8[0].left_loss_pb_reg[0] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_loss_pb_reg[1] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_loss_pb_reg[2] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_loss_pb_reg[3] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].left_loss_pb_reg[3]_i_2 (.CI(1'b0), .CO({\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_3 }), .CYINIT(1'b0), .DI({\genblk8[0].left_loss_pb[3]_i_3_n_0 ,\genblk8[0].left_loss_pb[3]_i_4_n_0 ,left_edge_ref[1],\prbs_dqs_tap_cnt_r_reg_n_0_[0] }), .O({\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ,\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 }), .S({\genblk8[0].left_loss_pb[3]_i_5_n_0 ,\genblk8[0].left_loss_pb[3]_i_6_n_0 ,\genblk8[0].left_loss_pb[3]_i_7_n_0 ,\genblk8[0].left_loss_pb[3]_i_8_n_0 })); FDRE \genblk8[0].left_loss_pb_reg[4] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[0].left_loss_pb_reg[5] (.C(CLK), .CE(\genblk8[0].left_loss_pb[5]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[0].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_14 (.CI(\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ), .CO({\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_14_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_20_n_0 ,\genblk8[0].left_loss_pb[5]_i_21_n_0 ,\genblk8[0].left_loss_pb[5]_i_22_n_0 ,\genblk8[0].left_loss_pb[5]_i_23_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_19 (.CI(1'b0), .CO({\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_19_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[0].left_loss_pb[5]_i_24_n_0 ,\genblk8[0].left_loss_pb[5]_i_25_n_0 ,\genblk8[0].left_loss_pb[5]_i_26_n_0 }), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_27_n_0 ,\genblk8[0].left_loss_pb[5]_i_28_n_0 ,\genblk8[0].left_loss_pb[5]_i_29_n_0 ,\genblk8[0].left_loss_pb[5]_i_30_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_4 (.CI(\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ), .CO({\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_7_n_0 ,\genblk8[0].left_loss_pb[5]_i_8_n_0 ,\genblk8[0].left_loss_pb[5]_i_9_n_0 ,\genblk8[0].left_loss_pb[5]_i_10_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_5 (.CI(\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ), .CO({\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED [3:1],\genblk8[0].left_loss_pb_reg[5]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\genblk8[0].left_loss_pb[5]_i_11_n_0 }), .O({\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED [3:2],\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ,\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[0].left_loss_pb[5]_i_12_n_0 ,\genblk8[0].left_loss_pb[5]_i_13_n_0 })); CARRY4 \genblk8[0].left_loss_pb_reg[5]_i_6 (.CI(\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ), .CO({\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ,\genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ,\genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ,\genblk8[0].left_loss_pb_reg[5]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED [3:0]), .S({\genblk8[0].left_loss_pb[5]_i_15_n_0 ,\genblk8[0].left_loss_pb[5]_i_16_n_0 ,\genblk8[0].left_loss_pb[5]_i_17_n_0 ,\genblk8[0].left_loss_pb[5]_i_18_n_0 })); LUT3 #( .INIT(8'hBA)) \genblk8[0].match_flag_pb[7]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_154_out), .I2(right_gain_pb), .O(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); LUT6 #( .INIT(64'h0002000000000000)) \genblk8[0].match_flag_pb[7]_i_2 (.I0(num_samples_done_r), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(Q[4]), .I5(Q[0]), .O(p_154_out)); FDSE \genblk8[0].match_flag_pb_reg[0] (.C(CLK), .CE(p_154_out), .D(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .Q(match_flag_pb[0]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[1] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[0]), .Q(match_flag_pb[1]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[2] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[1]), .Q(match_flag_pb[2]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[3] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[2]), .Q(match_flag_pb[3]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[4] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[3]), .Q(match_flag_pb[4]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[5] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[4]), .Q(match_flag_pb[5]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[6] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[5]), .Q(match_flag_pb[6]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[0].match_flag_pb_reg[7] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[6]), .Q(match_flag_pb[7]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[0].right_edge_found_pb_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk8[0].right_edge_found_pb_reg[0]_0 ), .Q(\genblk8[0].right_edge_pb_reg[0]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT2 #( .INIT(4'h9)) \genblk8[0].right_edge_pb[1]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\genblk8[0].right_edge_pb[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'hA9)) \genblk8[0].right_edge_pb[2]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\genblk8[0].right_edge_pb[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'hAAA9)) \genblk8[0].right_edge_pb[3]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[0].right_edge_pb[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT5 #( .INIT(32'hAAAAAAA9)) \genblk8[0].right_edge_pb[4]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\genblk8[0].right_edge_pb[4]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[0].right_edge_pb[5]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(\genblk8[0].left_loss_pb_reg[0]_1 ), .I2(p_154_out), .I3(\genblk8[0].right_edge_pb_reg[0]_1 ), .I4(\genblk8[0].right_edge_pb_reg[0]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[0].right_edge_pb[5]_i_2 (.I0(p_154_out), .I1(\genblk8[0].right_edge_pb_reg[0]_1 ), .I2(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(\genblk8[0].right_edge_pb[5]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \genblk8[0].right_edge_pb[5]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\genblk8[0].right_edge_pb[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[0].right_edge_pb[5]_i_4 (.I0(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ), .I1(\genblk8[0].left_edge_pb[5]_i_5_n_0 ), .I2(match_flag_pb[7]), .I3(match_flag_pb[6]), .I4(match_flag_pb[4]), .I5(match_flag_pb[5]), .O(\genblk8[0].right_edge_pb_reg[0]_1 )); LUT6 #( .INIT(64'h8000000000000000)) \genblk8[0].right_edge_pb[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\genblk8[7].right_edge_pb_reg[42]_1 )); FDSE \genblk8[0].right_edge_pb_reg[0] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[0].right_edge_pb_reg[1] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[0].right_edge_pb_reg[2] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[0].right_edge_pb_reg[3] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[0].right_edge_pb_reg[4] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[0].right_edge_pb_reg[5] (.C(CLK), .CE(\genblk8[0].right_edge_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .S(\genblk8[0].right_edge_pb[5]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[0]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ), .O(\genblk8[0].right_gain_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[1]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ), .O(\genblk8[0].right_gain_pb[1]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[2]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ), .O(\genblk8[0].right_gain_pb[2]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[3]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ), .I3(\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ), .O(\genblk8[0].right_gain_pb[3]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\genblk8[0].right_gain_pb[3]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\genblk8[0].right_gain_pb[3]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\genblk8[0].right_gain_pb[3]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\genblk8[0].right_gain_pb[3]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\genblk8[0].right_gain_pb[3]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\genblk8[0].right_gain_pb[3]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\genblk8[0].right_gain_pb[3]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[3]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\genblk8[0].right_gain_pb[3]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[4]_i_1 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ), .O(\genblk8[0].right_gain_pb[4]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[0].right_gain_pb[5]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[0].left_loss_pb_reg[0]_1 ), .I4(\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_11 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_12 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_13 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_14 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_15 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_15_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_16 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\genblk8[0].right_gain_pb[5]_i_16_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_17 (.I0(right_edge_ref[5]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_17_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[0].right_gain_pb[5]_i_18 (.I0(right_edge_ref[4]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\genblk8[0].right_gain_pb[5]_i_18_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[0].right_gain_pb[5]_i_19 (.I0(\genblk8[0].right_gain_pb[5]_i_27_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I2(right_edge_ref[3]), .I3(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .I4(right_edge_ref[4]), .O(\genblk8[0].right_gain_pb[5]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[0].right_gain_pb[5]_i_2 (.I0(p_154_out), .I1(\genblk8[0].right_edge_pb_reg[0]_1 ), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[0].right_edge_pb_reg[0]_0 ), .I4(\genblk8[0].left_loss_pb_reg[0]_1 ), .O(\genblk8[0].right_gain_pb[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[0].right_gain_pb[5]_i_20 (.I0(\genblk8[0].right_gain_pb[5]_i_28_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I3(right_edge_ref[4]), .I4(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\genblk8[0].right_gain_pb[5]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_23 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_23_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_26_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[0].right_gain_pb[5]_i_27 (.I0(right_edge_ref[0]), .I1(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I2(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I3(right_edge_ref[1]), .I4(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .I5(right_edge_ref[2]), .O(\genblk8[0].right_gain_pb[5]_i_27_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[0].right_gain_pb[5]_i_28 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I4(right_edge_ref[2]), .I5(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\genblk8[0].right_gain_pb[5]_i_28_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[0].right_gain_pb[5]_i_3 (.I0(\genblk8[0].right_edge_pb_reg[0]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ), .O(\genblk8[0].right_gain_pb[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_32_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_33 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_35 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_36_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_37 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_37_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_38 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_38_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_40 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_40_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_41 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_41_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_42 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_42_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_43 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_43_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[0].right_gain_pb[5]_i_44 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(right_edge_ref[4]), .I2(right_edge_ref[5]), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_44_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[0].right_gain_pb[5]_i_45 (.I0(right_edge_ref[2]), .I1(right_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_45_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[0].right_gain_pb[5]_i_46 (.I0(right_edge_ref[0]), .I1(right_edge_ref[1]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_46_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_47 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_47_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[0].right_gain_pb[5]_i_48 (.I0(right_edge_ref[4]), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(right_edge_ref[5]), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_48_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[0].right_gain_pb[5]_i_49 (.I0(right_edge_ref[2]), .I1(right_edge_ref[3]), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_49_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[0].right_gain_pb[5]_i_50 (.I0(right_edge_ref[0]), .I1(right_edge_ref[1]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_50_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_52 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_52_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_53 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_53_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_54 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_54_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_55 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_55_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[0].right_gain_pb[5]_i_56 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .I2(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_56_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[0].right_gain_pb[5]_i_57 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_57_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[0].right_gain_pb[5]_i_58 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_58_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[0].right_gain_pb[5]_i_59 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[0].right_gain_pb[5]_i_59_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[0].right_gain_pb[5]_i_60 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_60_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[0].right_gain_pb[5]_i_61 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_61_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[0].right_gain_pb[5]_i_62 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .I1(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_62_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[0].right_gain_pb[5]_i_8 (.I0(\genblk8[0].right_edge_pb_reg[0]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I4(\genblk8[0].right_gain_pb[5]_i_19_n_0 ), .O(\genblk8[0].right_gain_pb[5]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[0].right_gain_pb[5]_i_9 (.I0(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .I1(right_edge_ref[5]), .I2(\genblk8[0].right_gain_pb[5]_i_20_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ), .I5(\genblk8[0].right_edge_pb_reg[0]_0 ), .O(\genblk8[0].right_gain_pb[5]_i_9_n_0 )); FDRE \genblk8[0].right_gain_pb_reg[0] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[0]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg_n_0_[0] ), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE \genblk8[0].right_gain_pb_reg[1] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[1]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg_n_0_[1] ), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE \genblk8[0].right_gain_pb_reg[2] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[2]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [2]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE \genblk8[0].right_gain_pb_reg[3] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[3]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [3]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].right_gain_pb_reg[3]_i_2 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ,\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 }), .S({\genblk8[0].right_gain_pb[3]_i_4_n_0 ,\genblk8[0].right_gain_pb[3]_i_5_n_0 ,\genblk8[0].right_gain_pb[3]_i_6_n_0 ,\genblk8[0].right_gain_pb[3]_i_7_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[3]_i_3 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ,\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 }), .S({\genblk8[0].right_gain_pb[3]_i_8_n_0 ,\genblk8[0].right_gain_pb[3]_i_9_n_0 ,\genblk8[0].right_gain_pb[3]_i_10_n_0 ,\genblk8[0].right_gain_pb[3]_i_11_n_0 })); FDRE \genblk8[0].right_gain_pb_reg[4] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[4]_i_1_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [4]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); FDRE \genblk8[0].right_gain_pb_reg[5] (.C(CLK), .CE(\genblk8[0].right_gain_pb[5]_i_2_n_0 ), .D(\genblk8[0].right_gain_pb[5]_i_3_n_0 ), .Q(\genblk8[0].right_gain_pb_reg__0 [5]), .R(\genblk8[0].right_gain_pb[5]_i_1_n_0 )); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_10 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_10_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_23_n_0 ,\genblk8[0].right_gain_pb[5]_i_24_n_0 ,\genblk8[0].right_gain_pb[5]_i_25_n_0 ,\genblk8[0].right_gain_pb[5]_i_26_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_21 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_21_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_30_n_0 ,\genblk8[0].right_gain_pb[5]_i_31_n_0 ,\genblk8[0].right_gain_pb[5]_i_32_n_0 ,\genblk8[0].right_gain_pb[5]_i_33_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_22 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_22_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_35_n_0 ,\genblk8[0].right_gain_pb[5]_i_36_n_0 ,\genblk8[0].right_gain_pb[5]_i_37_n_0 ,\genblk8[0].right_gain_pb[5]_i_38_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_29 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_29_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_40_n_0 ,\genblk8[0].right_gain_pb[5]_i_41_n_0 ,\genblk8[0].right_gain_pb[5]_i_42_n_0 ,\genblk8[0].right_gain_pb[5]_i_43_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_34 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_34_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[0].right_gain_pb[5]_i_44_n_0 ,\genblk8[0].right_gain_pb[5]_i_45_n_0 ,\genblk8[0].right_gain_pb[5]_i_46_n_0 }), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_47_n_0 ,\genblk8[0].right_gain_pb[5]_i_48_n_0 ,\genblk8[0].right_gain_pb[5]_i_49_n_0 ,\genblk8[0].right_gain_pb[5]_i_50_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_39 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_39_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_52_n_0 ,\genblk8[0].right_gain_pb[5]_i_53_n_0 ,\genblk8[0].right_gain_pb[5]_i_54_n_0 ,\genblk8[0].right_gain_pb[5]_i_55_n_0 })); MUXF7 \genblk8[0].right_gain_pb_reg[5]_i_4 (.I0(\genblk8[0].right_gain_pb[5]_i_8_n_0 ), .I1(\genblk8[0].right_gain_pb[5]_i_9_n_0 ), .O(\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ), .S(\genblk8[0].right_edge_pb_reg[0]_1 )); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_5 (.CI(\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ), .CO({\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_11_n_0 ,\genblk8[0].right_gain_pb[5]_i_12_n_0 ,\genblk8[0].right_gain_pb[5]_i_13_n_0 ,\genblk8[0].right_gain_pb[5]_i_14_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_51 (.CI(1'b0), .CO({\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ,\genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ,\genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ,\genblk8[0].right_gain_pb_reg[5]_i_51_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[0].right_gain_pb[5]_i_56_n_0 ,\genblk8[0].right_gain_pb[5]_i_57_n_0 ,\genblk8[0].right_gain_pb[5]_i_58_n_0 }), .O(\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED [3:0]), .S({\genblk8[0].right_gain_pb[5]_i_59_n_0 ,\genblk8[0].right_gain_pb[5]_i_60_n_0 ,\genblk8[0].right_gain_pb[5]_i_61_n_0 ,\genblk8[0].right_gain_pb[5]_i_62_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_6 (.CI(\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ), .CO({\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED [3:1],\genblk8[0].right_gain_pb_reg[5]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED [3:2],\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ,\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[0].right_gain_pb[5]_i_15_n_0 ,\genblk8[0].right_gain_pb[5]_i_16_n_0 })); CARRY4 \genblk8[0].right_gain_pb_reg[5]_i_7 (.CI(\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ), .CO({\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED [3:1],\genblk8[0].right_gain_pb_reg[5]_i_7_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED [3:2],\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ,\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 }), .S({1'b0,1'b0,\genblk8[0].right_gain_pb[5]_i_17_n_0 ,\genblk8[0].right_gain_pb[5]_i_18_n_0 })); FDRE \genblk8[1].left_edge_found_pb_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk8[1].left_edge_found_pb_reg[1]_0 ), .Q(\genblk8[1].left_loss_pb_reg[6]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[1].left_edge_pb[11]_i_1 (.I0(p_154_out), .I1(p_146_out), .O(\genblk8[1].left_edge_pb[11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[1].left_edge_pb[11]_i_2 (.I0(match_flag_pb[15]), .I1(\genblk8[1].left_edge_pb[11]_i_3_n_0 ), .I2(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .I3(match_flag_pb[14]), .I4(match_flag_pb[12]), .I5(match_flag_pb[13]), .O(p_146_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[1].left_edge_pb[11]_i_3 (.I0(match_flag_pb[10]), .I1(match_flag_pb[11]), .I2(match_flag_pb[8]), .I3(match_flag_pb[9]), .O(\genblk8[1].left_edge_pb[11]_i_3_n_0 )); FDRE \genblk8[1].left_edge_pb_reg[10] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[10] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_edge_pb_reg[11] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[11] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_edge_pb_reg[6] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[6] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_edge_pb_reg[7] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[7] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_edge_pb_reg[8] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[8] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_edge_pb_reg[9] (.C(CLK), .CE(\genblk8[1].left_edge_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[1].left_edge_pb_reg_n_0_[9] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_edge_updated_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk8[1].left_edge_updated_reg[1]_0 ), .Q(D[1]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[1].left_loss_pb[11]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[1].left_loss_pb_reg[6]_0 ), .I4(p_146_out), .O(\genblk8[1].left_loss_pb[11]_i_1_n_0 )); FDRE \genblk8[1].left_loss_pb_reg[10] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_loss_pb_reg[11] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_loss_pb_reg[6] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg_n_0_[6] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_loss_pb_reg[7] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg_n_0_[7] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_loss_pb_reg[8] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[1].left_loss_pb_reg[9] (.C(CLK), .CE(\genblk8[1].left_loss_pb[11]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[1].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[10] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[9]), .Q(match_flag_pb[10]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[11] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[10]), .Q(match_flag_pb[11]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[12] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[11]), .Q(match_flag_pb[12]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[13] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[12]), .Q(match_flag_pb[13]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[14] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[13]), .Q(match_flag_pb[14]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[15] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[14]), .Q(match_flag_pb[15]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[8] (.C(CLK), .CE(p_154_out), .D(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .Q(match_flag_pb[8]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[1].match_flag_pb_reg[9] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[8]), .Q(match_flag_pb[9]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[1].right_edge_found_pb_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk8[1].right_edge_found_pb_reg[1]_0 ), .Q(\genblk8[1].right_edge_pb_reg[6]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[1].right_edge_pb[11]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_146_out), .I2(p_154_out), .I3(p_143_out), .I4(\genblk8[1].right_edge_pb_reg[6]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[1].right_edge_pb[11]_i_2 (.I0(p_154_out), .I1(p_143_out), .I2(p_146_out), .O(\genblk8[1].right_edge_pb[11]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[1].right_edge_pb[11]_i_3 (.I0(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ), .I1(\genblk8[1].left_edge_pb[11]_i_3_n_0 ), .I2(match_flag_pb[15]), .I3(match_flag_pb[14]), .I4(match_flag_pb[12]), .I5(match_flag_pb[13]), .O(p_143_out)); FDSE \genblk8[1].right_edge_pb_reg[10] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE \genblk8[1].right_edge_pb_reg[11] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE \genblk8[1].right_edge_pb_reg[6] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE \genblk8[1].right_edge_pb_reg[7] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE \genblk8[1].right_edge_pb_reg[8] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); FDSE \genblk8[1].right_edge_pb_reg[9] (.C(CLK), .CE(\genblk8[1].right_edge_pb[11]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .S(\genblk8[1].right_edge_pb[11]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[10]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ), .I3(\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ), .O(\genblk8[1].right_gain_pb[10]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[1].right_gain_pb[11]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_146_out), .I4(\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\genblk8[1].right_gain_pb[11]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\genblk8[1].right_gain_pb[11]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\genblk8[1].right_gain_pb[11]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[1].right_gain_pb[11]_i_13 (.I0(\genblk8[1].right_gain_pb[11]_i_16_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I2(right_edge_ref[3]), .I3(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .I4(right_edge_ref[4]), .O(\genblk8[1].right_gain_pb[11]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[1].right_gain_pb[11]_i_14 (.I0(\genblk8[1].right_gain_pb[11]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I3(right_edge_ref[4]), .I4(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\genblk8[1].right_gain_pb[11]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[1].right_gain_pb[11]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I2(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I3(right_edge_ref[1]), .I4(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .I5(right_edge_ref[2]), .O(\genblk8[1].right_gain_pb[11]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[1].right_gain_pb[11]_i_17 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I4(right_edge_ref[2]), .I5(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\genblk8[1].right_gain_pb[11]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[1].right_gain_pb[11]_i_2 (.I0(p_154_out), .I1(p_143_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[1].right_edge_pb_reg[6]_0 ), .I4(p_146_out), .O(\genblk8[1].right_gain_pb[11]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[11]_i_3 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ), .I3(\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ), .O(\genblk8[1].right_gain_pb[11]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[1].right_gain_pb[11]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .I2(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[1].right_gain_pb[11]_i_34 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[1].right_gain_pb[11]_i_35 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[1].right_gain_pb[11]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[1].right_gain_pb[11]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[1].right_gain_pb[11]_i_37 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[1].right_gain_pb[11]_i_38 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[1].right_gain_pb[11]_i_39 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[1].right_gain_pb[11]_i_7 (.I0(\genblk8[1].right_edge_pb_reg[6]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I4(\genblk8[1].right_gain_pb[11]_i_13_n_0 ), .O(\genblk8[1].right_gain_pb[11]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[1].right_gain_pb[11]_i_8 (.I0(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .I1(right_edge_ref[5]), .I2(\genblk8[1].right_gain_pb[11]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ), .I5(\genblk8[1].right_edge_pb_reg[6]_0 ), .O(\genblk8[1].right_gain_pb[11]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[11]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\genblk8[1].right_gain_pb[11]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[6]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ), .O(\genblk8[1].right_gain_pb[6]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[7]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ), .O(\genblk8[1].right_gain_pb[7]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[8]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ), .O(\genblk8[1].right_gain_pb[8]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[1].right_gain_pb[9]_i_1 (.I0(p_143_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ), .I3(\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ), .O(\genblk8[1].right_gain_pb[9]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\genblk8[1].right_gain_pb[9]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\genblk8[1].right_gain_pb[9]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\genblk8[1].right_gain_pb[9]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\genblk8[1].right_gain_pb[9]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\genblk8[1].right_gain_pb[9]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\genblk8[1].right_gain_pb[9]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\genblk8[1].right_gain_pb[9]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[1].right_gain_pb[9]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\genblk8[1].right_gain_pb[9]_i_9_n_0 )); FDRE \genblk8[1].right_gain_pb_reg[10] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[10]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [4]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE \genblk8[1].right_gain_pb_reg[11] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[11]_i_3_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [5]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_15 (.CI(\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ), .CO({\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_19_n_0 ,\genblk8[1].right_gain_pb[11]_i_20_n_0 ,\genblk8[1].right_gain_pb[11]_i_21_n_0 ,\genblk8[1].right_gain_pb[11]_i_22_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_18 (.CI(\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ), .CO({\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_24_n_0 ,\genblk8[1].right_gain_pb[11]_i_25_n_0 ,\genblk8[1].right_gain_pb[11]_i_26_n_0 ,\genblk8[1].right_gain_pb[11]_i_27_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_23 (.CI(\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ), .CO({\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_29_n_0 ,\genblk8[1].right_gain_pb[11]_i_30_n_0 ,\genblk8[1].right_gain_pb[11]_i_31_n_0 ,\genblk8[1].right_gain_pb[11]_i_32_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_28 (.CI(1'b0), .CO({\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ,\genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ,\genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ,\genblk8[1].right_gain_pb_reg[11]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[1].right_gain_pb[11]_i_33_n_0 ,\genblk8[1].right_gain_pb[11]_i_34_n_0 ,\genblk8[1].right_gain_pb[11]_i_35_n_0 }), .O(\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[1].right_gain_pb[11]_i_36_n_0 ,\genblk8[1].right_gain_pb[11]_i_37_n_0 ,\genblk8[1].right_gain_pb[11]_i_38_n_0 ,\genblk8[1].right_gain_pb[11]_i_39_n_0 })); MUXF7 \genblk8[1].right_gain_pb_reg[11]_i_4 (.I0(\genblk8[1].right_gain_pb[11]_i_7_n_0 ), .I1(\genblk8[1].right_gain_pb[11]_i_8_n_0 ), .O(\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ), .S(p_143_out)); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_5 (.CI(\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ), .CO({\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED [3:1],\genblk8[1].right_gain_pb_reg[11]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED [3:2],\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ,\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[1].right_gain_pb[11]_i_9_n_0 ,\genblk8[1].right_gain_pb[11]_i_10_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[11]_i_6 (.CI(\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ), .CO({\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED [3:1],\genblk8[1].right_gain_pb_reg[11]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED [3:2],\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ,\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[1].right_gain_pb[11]_i_11_n_0 ,\genblk8[1].right_gain_pb[11]_i_12_n_0 })); FDRE \genblk8[1].right_gain_pb_reg[6] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[6]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg_n_0_[6] ), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE \genblk8[1].right_gain_pb_reg[7] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[7]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg_n_0_[7] ), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE \genblk8[1].right_gain_pb_reg[8] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[8]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [2]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); FDRE \genblk8[1].right_gain_pb_reg[9] (.C(CLK), .CE(\genblk8[1].right_gain_pb[11]_i_2_n_0 ), .D(\genblk8[1].right_gain_pb[9]_i_1_n_0 ), .Q(\genblk8[1].right_gain_pb_reg__0 [3]), .R(\genblk8[1].right_gain_pb[11]_i_1_n_0 )); CARRY4 \genblk8[1].right_gain_pb_reg[9]_i_2 (.CI(1'b0), .CO({\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ,\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 }), .S({\genblk8[1].right_gain_pb[9]_i_4_n_0 ,\genblk8[1].right_gain_pb[9]_i_5_n_0 ,\genblk8[1].right_gain_pb[9]_i_6_n_0 ,\genblk8[1].right_gain_pb[9]_i_7_n_0 })); CARRY4 \genblk8[1].right_gain_pb_reg[9]_i_3 (.CI(1'b0), .CO({\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ,\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 }), .S({\genblk8[1].right_gain_pb[9]_i_8_n_0 ,\genblk8[1].right_gain_pb[9]_i_9_n_0 ,\genblk8[1].right_gain_pb[9]_i_10_n_0 ,\genblk8[1].right_gain_pb[9]_i_11_n_0 })); FDRE \genblk8[2].left_edge_found_pb_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk8[2].left_edge_found_pb_reg[2]_0 ), .Q(\genblk8[2].left_loss_pb_reg[12]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[2].left_edge_pb[17]_i_1 (.I0(p_154_out), .I1(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].left_edge_pb[17]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[2].left_edge_pb[17]_i_2 (.I0(match_flag_pb[23]), .I1(\genblk8[2].left_edge_pb[17]_i_3_n_0 ), .I2(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .I3(match_flag_pb[22]), .I4(match_flag_pb[20]), .I5(match_flag_pb[21]), .O(\genblk8[2].right_edge_pb_reg[12]_2 )); LUT4 #( .INIT(16'hFFFE)) \genblk8[2].left_edge_pb[17]_i_3 (.I0(match_flag_pb[18]), .I1(match_flag_pb[19]), .I2(match_flag_pb[16]), .I3(match_flag_pb[17]), .O(\genblk8[2].left_edge_pb[17]_i_3_n_0 )); FDRE \genblk8[2].left_edge_pb_reg[12] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[12] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_edge_pb_reg[13] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[13] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_edge_pb_reg[14] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[14] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_edge_pb_reg[15] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[15] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_edge_pb_reg[16] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[16] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_edge_pb_reg[17] (.C(CLK), .CE(\genblk8[2].left_edge_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[2].left_edge_pb_reg_n_0_[17] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_edge_updated_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk8[2].left_edge_updated_reg[2]_0 ), .Q(D[2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[2].left_loss_pb[17]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[2].left_loss_pb_reg[12]_0 ), .I4(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].left_loss_pb[17]_i_1_n_0 )); FDRE \genblk8[2].left_loss_pb_reg[12] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg_n_0_[12] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_loss_pb_reg[13] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg_n_0_[13] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_loss_pb_reg[14] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_loss_pb_reg[15] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_loss_pb_reg[16] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[2].left_loss_pb_reg[17] (.C(CLK), .CE(\genblk8[2].left_loss_pb[17]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[2].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[16] (.C(CLK), .CE(p_154_out), .D(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .Q(match_flag_pb[16]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[17] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[16]), .Q(match_flag_pb[17]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[18] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[17]), .Q(match_flag_pb[18]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[19] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[18]), .Q(match_flag_pb[19]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[20] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[19]), .Q(match_flag_pb[20]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[21] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[20]), .Q(match_flag_pb[21]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[22] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[21]), .Q(match_flag_pb[22]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[2].match_flag_pb_reg[23] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[22]), .Q(match_flag_pb[23]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[2].right_edge_found_pb_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk8[2].right_edge_found_pb_reg[2]_0 ), .Q(\genblk8[2].right_edge_pb_reg[12]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[2].right_edge_pb[17]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(\genblk8[2].right_edge_pb_reg[12]_2 ), .I2(p_154_out), .I3(\genblk8[2].right_edge_pb_reg[12]_1 ), .I4(\genblk8[2].right_edge_pb_reg[12]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[2].right_edge_pb[17]_i_2 (.I0(p_154_out), .I1(\genblk8[2].right_edge_pb_reg[12]_1 ), .I2(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].right_edge_pb[17]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[2].right_edge_pb[17]_i_3 (.I0(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ), .I1(\genblk8[2].left_edge_pb[17]_i_3_n_0 ), .I2(match_flag_pb[23]), .I3(match_flag_pb[22]), .I4(match_flag_pb[20]), .I5(match_flag_pb[21]), .O(\genblk8[2].right_edge_pb_reg[12]_1 )); FDSE \genblk8[2].right_edge_pb_reg[12] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE \genblk8[2].right_edge_pb_reg[13] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE \genblk8[2].right_edge_pb_reg[14] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE \genblk8[2].right_edge_pb_reg[15] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE \genblk8[2].right_edge_pb_reg[16] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); FDSE \genblk8[2].right_edge_pb_reg[17] (.C(CLK), .CE(\genblk8[2].right_edge_pb[17]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .S(\genblk8[2].right_edge_pb[17]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[12]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ), .O(\genblk8[2].right_gain_pb[12]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[13]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ), .O(\genblk8[2].right_gain_pb[13]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[14]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ), .O(\genblk8[2].right_gain_pb[14]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[15]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ), .I3(\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ), .O(\genblk8[2].right_gain_pb[15]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\genblk8[2].right_gain_pb[15]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\genblk8[2].right_gain_pb[15]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\genblk8[2].right_gain_pb[15]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\genblk8[2].right_gain_pb[15]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\genblk8[2].right_gain_pb[15]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\genblk8[2].right_gain_pb[15]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\genblk8[2].right_gain_pb[15]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[15]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\genblk8[2].right_gain_pb[15]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[16]_i_1 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ), .I3(\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ), .O(\genblk8[2].right_gain_pb[16]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[2].right_gain_pb[17]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[2].right_edge_pb_reg[12]_2 ), .I4(\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .O(\genblk8[2].right_gain_pb[17]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .O(\genblk8[2].right_gain_pb[17]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .O(\genblk8[2].right_gain_pb[17]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[2].right_gain_pb[17]_i_13 (.I0(\genblk8[2].right_gain_pb[17]_i_16_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I2(right_edge_ref[3]), .I3(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I4(right_edge_ref[4]), .O(\genblk8[2].right_gain_pb[17]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[2].right_gain_pb[17]_i_14 (.I0(\genblk8[2].right_gain_pb[17]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I3(right_edge_ref[4]), .I4(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .O(\genblk8[2].right_gain_pb[17]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[2].right_gain_pb[17]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I2(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I3(right_edge_ref[1]), .I4(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .I5(right_edge_ref[2]), .O(\genblk8[2].right_gain_pb[17]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[2].right_gain_pb[17]_i_17 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I4(right_edge_ref[2]), .I5(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\genblk8[2].right_gain_pb[17]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[2].right_gain_pb[17]_i_2 (.I0(p_154_out), .I1(\genblk8[2].right_edge_pb_reg[12]_1 ), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[2].right_edge_pb_reg[12]_0 ), .I4(\genblk8[2].right_edge_pb_reg[12]_2 ), .O(\genblk8[2].right_gain_pb[17]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[2].right_gain_pb[17]_i_3 (.I0(\genblk8[2].right_edge_pb_reg[12]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ), .I3(\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ), .O(\genblk8[2].right_gain_pb[17]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[2].right_gain_pb[17]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I2(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[2].right_gain_pb[17]_i_34 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[2].right_gain_pb[17]_i_35 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[2].right_gain_pb[17]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[2].right_gain_pb[17]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[2].right_gain_pb[17]_i_37 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[2].right_gain_pb[17]_i_38 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[2].right_gain_pb[17]_i_39 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[2].right_gain_pb[17]_i_7 (.I0(\genblk8[2].right_edge_pb_reg[12]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I4(\genblk8[2].right_gain_pb[17]_i_13_n_0 ), .O(\genblk8[2].right_gain_pb[17]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[2].right_gain_pb[17]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(right_edge_ref[5]), .I2(\genblk8[2].right_gain_pb[17]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ), .I5(\genblk8[2].right_edge_pb_reg[12]_0 ), .O(\genblk8[2].right_gain_pb[17]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[2].right_gain_pb[17]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .O(\genblk8[2].right_gain_pb[17]_i_9_n_0 )); FDRE \genblk8[2].right_gain_pb_reg[12] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[12]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg_n_0_[12] ), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE \genblk8[2].right_gain_pb_reg[13] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[13]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg_n_0_[13] ), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE \genblk8[2].right_gain_pb_reg[14] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[14]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [2]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE \genblk8[2].right_gain_pb_reg[15] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[15]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [3]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); CARRY4 \genblk8[2].right_gain_pb_reg[15]_i_2 (.CI(1'b0), .CO({\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ,\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 }), .S({\genblk8[2].right_gain_pb[15]_i_4_n_0 ,\genblk8[2].right_gain_pb[15]_i_5_n_0 ,\genblk8[2].right_gain_pb[15]_i_6_n_0 ,\genblk8[2].right_gain_pb[15]_i_7_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[15]_i_3 (.CI(1'b0), .CO({\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ,\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 }), .S({\genblk8[2].right_gain_pb[15]_i_8_n_0 ,\genblk8[2].right_gain_pb[15]_i_9_n_0 ,\genblk8[2].right_gain_pb[15]_i_10_n_0 ,\genblk8[2].right_gain_pb[15]_i_11_n_0 })); FDRE \genblk8[2].right_gain_pb_reg[16] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[16]_i_1_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [4]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); FDRE \genblk8[2].right_gain_pb_reg[17] (.C(CLK), .CE(\genblk8[2].right_gain_pb[17]_i_2_n_0 ), .D(\genblk8[2].right_gain_pb[17]_i_3_n_0 ), .Q(\genblk8[2].right_gain_pb_reg__0 [5]), .R(\genblk8[2].right_gain_pb[17]_i_1_n_0 )); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_15 (.CI(\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ), .CO({\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_19_n_0 ,\genblk8[2].right_gain_pb[17]_i_20_n_0 ,\genblk8[2].right_gain_pb[17]_i_21_n_0 ,\genblk8[2].right_gain_pb[17]_i_22_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_18 (.CI(\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ), .CO({\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_24_n_0 ,\genblk8[2].right_gain_pb[17]_i_25_n_0 ,\genblk8[2].right_gain_pb[17]_i_26_n_0 ,\genblk8[2].right_gain_pb[17]_i_27_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_23 (.CI(\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ), .CO({\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_29_n_0 ,\genblk8[2].right_gain_pb[17]_i_30_n_0 ,\genblk8[2].right_gain_pb[17]_i_31_n_0 ,\genblk8[2].right_gain_pb[17]_i_32_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_28 (.CI(1'b0), .CO({\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ,\genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ,\genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ,\genblk8[2].right_gain_pb_reg[17]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[2].right_gain_pb[17]_i_33_n_0 ,\genblk8[2].right_gain_pb[17]_i_34_n_0 ,\genblk8[2].right_gain_pb[17]_i_35_n_0 }), .O(\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[2].right_gain_pb[17]_i_36_n_0 ,\genblk8[2].right_gain_pb[17]_i_37_n_0 ,\genblk8[2].right_gain_pb[17]_i_38_n_0 ,\genblk8[2].right_gain_pb[17]_i_39_n_0 })); MUXF7 \genblk8[2].right_gain_pb_reg[17]_i_4 (.I0(\genblk8[2].right_gain_pb[17]_i_7_n_0 ), .I1(\genblk8[2].right_gain_pb[17]_i_8_n_0 ), .O(\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ), .S(\genblk8[2].right_edge_pb_reg[12]_1 )); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_5 (.CI(\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ), .CO({\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED [3:1],\genblk8[2].right_gain_pb_reg[17]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED [3:2],\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ,\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[2].right_gain_pb[17]_i_9_n_0 ,\genblk8[2].right_gain_pb[17]_i_10_n_0 })); CARRY4 \genblk8[2].right_gain_pb_reg[17]_i_6 (.CI(\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ), .CO({\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED [3:1],\genblk8[2].right_gain_pb_reg[17]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED [3:2],\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ,\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[2].right_gain_pb[17]_i_11_n_0 ,\genblk8[2].right_gain_pb[17]_i_12_n_0 })); FDRE \genblk8[3].left_edge_found_pb_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk8[3].left_edge_found_pb_reg[3]_0 ), .Q(\genblk8[3].left_loss_pb_reg[18]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[3].left_edge_pb[23]_i_1 (.I0(p_154_out), .I1(p_130_out), .O(\genblk8[3].left_edge_pb[23]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[3].left_edge_pb[23]_i_2 (.I0(match_flag_pb[31]), .I1(\genblk8[3].left_edge_pb[23]_i_3_n_0 ), .I2(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .I3(match_flag_pb[30]), .I4(match_flag_pb[28]), .I5(match_flag_pb[29]), .O(p_130_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[3].left_edge_pb[23]_i_3 (.I0(match_flag_pb[26]), .I1(match_flag_pb[27]), .I2(match_flag_pb[24]), .I3(match_flag_pb[25]), .O(\genblk8[3].left_edge_pb[23]_i_3_n_0 )); FDRE \genblk8[3].left_edge_pb_reg[18] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[18] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_edge_pb_reg[19] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[19] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_edge_pb_reg[20] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[20] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_edge_pb_reg[21] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[21] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_edge_pb_reg[22] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[22] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_edge_pb_reg[23] (.C(CLK), .CE(\genblk8[3].left_edge_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[3].left_edge_pb_reg_n_0_[23] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_edge_updated_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk8[3].left_edge_updated_reg[3]_0 ), .Q(D[3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[3].left_loss_pb[23]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[3].left_loss_pb_reg[18]_0 ), .I4(p_130_out), .O(\genblk8[3].left_loss_pb[23]_i_1_n_0 )); FDRE \genblk8[3].left_loss_pb_reg[18] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg_n_0_[18] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_loss_pb_reg[19] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg_n_0_[19] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_loss_pb_reg[20] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_loss_pb_reg[21] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_loss_pb_reg[22] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[3].left_loss_pb_reg[23] (.C(CLK), .CE(\genblk8[3].left_loss_pb[23]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[3].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[24] (.C(CLK), .CE(p_154_out), .D(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .Q(match_flag_pb[24]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[25] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[24]), .Q(match_flag_pb[25]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[26] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[25]), .Q(match_flag_pb[26]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[27] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[26]), .Q(match_flag_pb[27]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[28] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[27]), .Q(match_flag_pb[28]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[29] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[28]), .Q(match_flag_pb[29]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[30] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[29]), .Q(match_flag_pb[30]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[3].match_flag_pb_reg[31] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[30]), .Q(match_flag_pb[31]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[3].right_edge_found_pb_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk8[3].right_edge_found_pb_reg[3]_0 ), .Q(\genblk8[3].right_edge_pb_reg[18]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[3].right_edge_pb[23]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_130_out), .I2(p_154_out), .I3(p_127_out), .I4(\genblk8[3].right_edge_pb_reg[18]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[3].right_edge_pb[23]_i_2 (.I0(p_154_out), .I1(p_127_out), .I2(p_130_out), .O(\genblk8[3].right_edge_pb[23]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[3].right_edge_pb[23]_i_3 (.I0(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ), .I1(\genblk8[3].left_edge_pb[23]_i_3_n_0 ), .I2(match_flag_pb[31]), .I3(match_flag_pb[30]), .I4(match_flag_pb[28]), .I5(match_flag_pb[29]), .O(p_127_out)); FDSE \genblk8[3].right_edge_pb_reg[18] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE \genblk8[3].right_edge_pb_reg[19] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE \genblk8[3].right_edge_pb_reg[20] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE \genblk8[3].right_edge_pb_reg[21] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE \genblk8[3].right_edge_pb_reg[22] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); FDSE \genblk8[3].right_edge_pb_reg[23] (.C(CLK), .CE(\genblk8[3].right_edge_pb[23]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .S(\genblk8[3].right_edge_pb[23]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[18]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ), .O(\genblk8[3].right_gain_pb[18]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[19]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ), .O(\genblk8[3].right_gain_pb[19]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[20]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ), .O(\genblk8[3].right_gain_pb[20]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[21]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ), .I3(\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ), .O(\genblk8[3].right_gain_pb[21]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .O(\genblk8[3].right_gain_pb[21]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .O(\genblk8[3].right_gain_pb[21]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .O(\genblk8[3].right_gain_pb[21]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .O(\genblk8[3].right_gain_pb[21]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .O(\genblk8[3].right_gain_pb[21]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .O(\genblk8[3].right_gain_pb[21]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .O(\genblk8[3].right_gain_pb[21]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[21]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .O(\genblk8[3].right_gain_pb[21]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[22]_i_1 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ), .I3(\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ), .O(\genblk8[3].right_gain_pb[22]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[3].right_gain_pb[23]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_130_out), .I4(\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .O(\genblk8[3].right_gain_pb[23]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .O(\genblk8[3].right_gain_pb[23]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .O(\genblk8[3].right_gain_pb[23]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[3].right_gain_pb[23]_i_13 (.I0(\genblk8[3].right_gain_pb[23]_i_16_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I2(right_edge_ref[3]), .I3(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I4(right_edge_ref[4]), .O(\genblk8[3].right_gain_pb[23]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[3].right_gain_pb[23]_i_14 (.I0(\genblk8[3].right_gain_pb[23]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I3(right_edge_ref[4]), .I4(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .O(\genblk8[3].right_gain_pb[23]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[3].right_gain_pb[23]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I2(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I3(right_edge_ref[1]), .I4(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I5(right_edge_ref[2]), .O(\genblk8[3].right_gain_pb[23]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[3].right_gain_pb[23]_i_17 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I4(right_edge_ref[2]), .I5(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .O(\genblk8[3].right_gain_pb[23]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[3].right_gain_pb[23]_i_2 (.I0(p_154_out), .I1(p_127_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[3].right_edge_pb_reg[18]_0 ), .I4(p_130_out), .O(\genblk8[3].right_gain_pb[23]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[3].right_gain_pb[23]_i_3 (.I0(p_127_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ), .I3(\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ), .O(\genblk8[3].right_gain_pb[23]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[3].right_gain_pb[23]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I2(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[3].right_gain_pb[23]_i_34 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[3].right_gain_pb[23]_i_35 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[3].right_gain_pb[23]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[3].right_gain_pb[23]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[3].right_gain_pb[23]_i_37 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[3].right_gain_pb[23]_i_38 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[3].right_gain_pb[23]_i_39 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[3].right_gain_pb[23]_i_7 (.I0(\genblk8[3].right_edge_pb_reg[18]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I4(\genblk8[3].right_gain_pb[23]_i_13_n_0 ), .O(\genblk8[3].right_gain_pb[23]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[3].right_gain_pb[23]_i_8 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I1(right_edge_ref[5]), .I2(\genblk8[3].right_gain_pb[23]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ), .I5(\genblk8[3].right_edge_pb_reg[18]_0 ), .O(\genblk8[3].right_gain_pb[23]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[3].right_gain_pb[23]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .O(\genblk8[3].right_gain_pb[23]_i_9_n_0 )); FDRE \genblk8[3].right_gain_pb_reg[18] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[18]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg_n_0_[18] ), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE \genblk8[3].right_gain_pb_reg[19] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[19]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg_n_0_[19] ), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE \genblk8[3].right_gain_pb_reg[20] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[20]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [2]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE \genblk8[3].right_gain_pb_reg[21] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[21]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [3]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); CARRY4 \genblk8[3].right_gain_pb_reg[21]_i_2 (.CI(1'b0), .CO({\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ,\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 }), .S({\genblk8[3].right_gain_pb[21]_i_4_n_0 ,\genblk8[3].right_gain_pb[21]_i_5_n_0 ,\genblk8[3].right_gain_pb[21]_i_6_n_0 ,\genblk8[3].right_gain_pb[21]_i_7_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[21]_i_3 (.CI(1'b0), .CO({\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ,\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 }), .S({\genblk8[3].right_gain_pb[21]_i_8_n_0 ,\genblk8[3].right_gain_pb[21]_i_9_n_0 ,\genblk8[3].right_gain_pb[21]_i_10_n_0 ,\genblk8[3].right_gain_pb[21]_i_11_n_0 })); FDRE \genblk8[3].right_gain_pb_reg[22] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[22]_i_1_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [4]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); FDRE \genblk8[3].right_gain_pb_reg[23] (.C(CLK), .CE(\genblk8[3].right_gain_pb[23]_i_2_n_0 ), .D(\genblk8[3].right_gain_pb[23]_i_3_n_0 ), .Q(\genblk8[3].right_gain_pb_reg__0 [5]), .R(\genblk8[3].right_gain_pb[23]_i_1_n_0 )); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_15 (.CI(\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ), .CO({\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_19_n_0 ,\genblk8[3].right_gain_pb[23]_i_20_n_0 ,\genblk8[3].right_gain_pb[23]_i_21_n_0 ,\genblk8[3].right_gain_pb[23]_i_22_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_18 (.CI(\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ), .CO({\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_24_n_0 ,\genblk8[3].right_gain_pb[23]_i_25_n_0 ,\genblk8[3].right_gain_pb[23]_i_26_n_0 ,\genblk8[3].right_gain_pb[23]_i_27_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_23 (.CI(\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ), .CO({\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_29_n_0 ,\genblk8[3].right_gain_pb[23]_i_30_n_0 ,\genblk8[3].right_gain_pb[23]_i_31_n_0 ,\genblk8[3].right_gain_pb[23]_i_32_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_28 (.CI(1'b0), .CO({\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ,\genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ,\genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ,\genblk8[3].right_gain_pb_reg[23]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[3].right_gain_pb[23]_i_33_n_0 ,\genblk8[3].right_gain_pb[23]_i_34_n_0 ,\genblk8[3].right_gain_pb[23]_i_35_n_0 }), .O(\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[3].right_gain_pb[23]_i_36_n_0 ,\genblk8[3].right_gain_pb[23]_i_37_n_0 ,\genblk8[3].right_gain_pb[23]_i_38_n_0 ,\genblk8[3].right_gain_pb[23]_i_39_n_0 })); MUXF7 \genblk8[3].right_gain_pb_reg[23]_i_4 (.I0(\genblk8[3].right_gain_pb[23]_i_7_n_0 ), .I1(\genblk8[3].right_gain_pb[23]_i_8_n_0 ), .O(\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ), .S(p_127_out)); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_5 (.CI(\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ), .CO({\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED [3:1],\genblk8[3].right_gain_pb_reg[23]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED [3:2],\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ,\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[3].right_gain_pb[23]_i_9_n_0 ,\genblk8[3].right_gain_pb[23]_i_10_n_0 })); CARRY4 \genblk8[3].right_gain_pb_reg[23]_i_6 (.CI(\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ), .CO({\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED [3:1],\genblk8[3].right_gain_pb_reg[23]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED [3:2],\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ,\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[3].right_gain_pb[23]_i_11_n_0 ,\genblk8[3].right_gain_pb[23]_i_12_n_0 })); FDRE \genblk8[4].left_edge_found_pb_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk8[4].left_edge_found_pb_reg[4]_0 ), .Q(\genblk8[4].left_loss_pb_reg[24]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[4].left_edge_pb[29]_i_1 (.I0(p_154_out), .I1(p_122_out), .O(\genblk8[4].left_edge_pb[29]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[4].left_edge_pb[29]_i_2 (.I0(match_flag_pb[39]), .I1(\genblk8[4].left_edge_pb[29]_i_3_n_0 ), .I2(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .I3(match_flag_pb[38]), .I4(match_flag_pb[36]), .I5(match_flag_pb[37]), .O(p_122_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[4].left_edge_pb[29]_i_3 (.I0(match_flag_pb[34]), .I1(match_flag_pb[35]), .I2(match_flag_pb[32]), .I3(match_flag_pb[33]), .O(\genblk8[4].left_edge_pb[29]_i_3_n_0 )); FDRE \genblk8[4].left_edge_pb_reg[24] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[24] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_edge_pb_reg[25] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[25] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_edge_pb_reg[26] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[26] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_edge_pb_reg[27] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[27] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_edge_pb_reg[28] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[28] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_edge_pb_reg[29] (.C(CLK), .CE(\genblk8[4].left_edge_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[4].left_edge_pb_reg_n_0_[29] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_edge_updated_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk8[4].left_edge_updated_reg[4]_0 ), .Q(D[4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[4].left_loss_pb[29]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[4].left_loss_pb_reg[24]_0 ), .I4(p_122_out), .O(\genblk8[4].left_loss_pb[29]_i_1_n_0 )); FDRE \genblk8[4].left_loss_pb_reg[24] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg_n_0_[24] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_loss_pb_reg[25] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg_n_0_[25] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_loss_pb_reg[26] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_loss_pb_reg[27] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_loss_pb_reg[28] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[4].left_loss_pb_reg[29] (.C(CLK), .CE(\genblk8[4].left_loss_pb[29]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[4].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[32] (.C(CLK), .CE(p_154_out), .D(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .Q(match_flag_pb[32]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[33] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[32]), .Q(match_flag_pb[33]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[34] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[33]), .Q(match_flag_pb[34]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[35] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[34]), .Q(match_flag_pb[35]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[36] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[35]), .Q(match_flag_pb[36]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[37] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[36]), .Q(match_flag_pb[37]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[38] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[37]), .Q(match_flag_pb[38]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[4].match_flag_pb_reg[39] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[38]), .Q(match_flag_pb[39]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[4].right_edge_found_pb_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk8[4].right_edge_found_pb_reg[4]_0 ), .Q(\genblk8[4].right_edge_pb_reg[24]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[4].right_edge_pb[29]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_122_out), .I2(p_154_out), .I3(p_119_out), .I4(\genblk8[4].right_edge_pb_reg[24]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[4].right_edge_pb[29]_i_2 (.I0(p_154_out), .I1(p_119_out), .I2(p_122_out), .O(\genblk8[4].right_edge_pb[29]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[4].right_edge_pb[29]_i_3 (.I0(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ), .I1(\genblk8[4].left_edge_pb[29]_i_3_n_0 ), .I2(match_flag_pb[39]), .I3(match_flag_pb[38]), .I4(match_flag_pb[36]), .I5(match_flag_pb[37]), .O(p_119_out)); FDSE \genblk8[4].right_edge_pb_reg[24] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE \genblk8[4].right_edge_pb_reg[25] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE \genblk8[4].right_edge_pb_reg[26] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE \genblk8[4].right_edge_pb_reg[27] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE \genblk8[4].right_edge_pb_reg[28] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); FDSE \genblk8[4].right_edge_pb_reg[29] (.C(CLK), .CE(\genblk8[4].right_edge_pb[29]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .S(\genblk8[4].right_edge_pb[29]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[24]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ), .O(\genblk8[4].right_gain_pb[24]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[25]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ), .O(\genblk8[4].right_gain_pb[25]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[26]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ), .O(\genblk8[4].right_gain_pb[26]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[27]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ), .I3(\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ), .O(\genblk8[4].right_gain_pb[27]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .O(\genblk8[4].right_gain_pb[27]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .O(\genblk8[4].right_gain_pb[27]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .O(\genblk8[4].right_gain_pb[27]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .O(\genblk8[4].right_gain_pb[27]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .O(\genblk8[4].right_gain_pb[27]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .O(\genblk8[4].right_gain_pb[27]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .O(\genblk8[4].right_gain_pb[27]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[27]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .O(\genblk8[4].right_gain_pb[27]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[28]_i_1 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ), .I3(\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ), .O(\genblk8[4].right_gain_pb[28]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[4].right_gain_pb[29]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_122_out), .I4(\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .O(\genblk8[4].right_gain_pb[29]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .O(\genblk8[4].right_gain_pb[29]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .O(\genblk8[4].right_gain_pb[29]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[4].right_gain_pb[29]_i_13 (.I0(\genblk8[4].right_gain_pb[29]_i_16_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I2(right_edge_ref[3]), .I3(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I4(right_edge_ref[4]), .O(\genblk8[4].right_gain_pb[29]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[4].right_gain_pb[29]_i_14 (.I0(\genblk8[4].right_gain_pb[29]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I3(right_edge_ref[4]), .I4(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .O(\genblk8[4].right_gain_pb[29]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[4].right_gain_pb[29]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I2(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I3(right_edge_ref[1]), .I4(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I5(right_edge_ref[2]), .O(\genblk8[4].right_gain_pb[29]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[4].right_gain_pb[29]_i_17 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I4(right_edge_ref[2]), .I5(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .O(\genblk8[4].right_gain_pb[29]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[4].right_gain_pb[29]_i_2 (.I0(p_154_out), .I1(p_119_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[4].right_edge_pb_reg[24]_0 ), .I4(p_122_out), .O(\genblk8[4].right_gain_pb[29]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[4].right_gain_pb[29]_i_3 (.I0(p_119_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ), .I3(\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ), .O(\genblk8[4].right_gain_pb[29]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[4].right_gain_pb[29]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I2(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[4].right_gain_pb[29]_i_34 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[4].right_gain_pb[29]_i_35 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[4].right_gain_pb[29]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[4].right_gain_pb[29]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[4].right_gain_pb[29]_i_37 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[4].right_gain_pb[29]_i_38 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[4].right_gain_pb[29]_i_39 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[4].right_gain_pb[29]_i_7 (.I0(\genblk8[4].right_edge_pb_reg[24]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I4(\genblk8[4].right_gain_pb[29]_i_13_n_0 ), .O(\genblk8[4].right_gain_pb[29]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[4].right_gain_pb[29]_i_8 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I1(right_edge_ref[5]), .I2(\genblk8[4].right_gain_pb[29]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ), .I5(\genblk8[4].right_edge_pb_reg[24]_0 ), .O(\genblk8[4].right_gain_pb[29]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[4].right_gain_pb[29]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .O(\genblk8[4].right_gain_pb[29]_i_9_n_0 )); FDRE \genblk8[4].right_gain_pb_reg[24] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[24]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg_n_0_[24] ), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE \genblk8[4].right_gain_pb_reg[25] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[25]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg_n_0_[25] ), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE \genblk8[4].right_gain_pb_reg[26] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[26]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [2]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE \genblk8[4].right_gain_pb_reg[27] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[27]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [3]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); CARRY4 \genblk8[4].right_gain_pb_reg[27]_i_2 (.CI(1'b0), .CO({\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ,\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 }), .S({\genblk8[4].right_gain_pb[27]_i_4_n_0 ,\genblk8[4].right_gain_pb[27]_i_5_n_0 ,\genblk8[4].right_gain_pb[27]_i_6_n_0 ,\genblk8[4].right_gain_pb[27]_i_7_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[27]_i_3 (.CI(1'b0), .CO({\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ,\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 }), .S({\genblk8[4].right_gain_pb[27]_i_8_n_0 ,\genblk8[4].right_gain_pb[27]_i_9_n_0 ,\genblk8[4].right_gain_pb[27]_i_10_n_0 ,\genblk8[4].right_gain_pb[27]_i_11_n_0 })); FDRE \genblk8[4].right_gain_pb_reg[28] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[28]_i_1_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [4]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); FDRE \genblk8[4].right_gain_pb_reg[29] (.C(CLK), .CE(\genblk8[4].right_gain_pb[29]_i_2_n_0 ), .D(\genblk8[4].right_gain_pb[29]_i_3_n_0 ), .Q(\genblk8[4].right_gain_pb_reg__0 [5]), .R(\genblk8[4].right_gain_pb[29]_i_1_n_0 )); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_15 (.CI(\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ), .CO({\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_19_n_0 ,\genblk8[4].right_gain_pb[29]_i_20_n_0 ,\genblk8[4].right_gain_pb[29]_i_21_n_0 ,\genblk8[4].right_gain_pb[29]_i_22_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_18 (.CI(\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ), .CO({\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_24_n_0 ,\genblk8[4].right_gain_pb[29]_i_25_n_0 ,\genblk8[4].right_gain_pb[29]_i_26_n_0 ,\genblk8[4].right_gain_pb[29]_i_27_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_23 (.CI(\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ), .CO({\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_29_n_0 ,\genblk8[4].right_gain_pb[29]_i_30_n_0 ,\genblk8[4].right_gain_pb[29]_i_31_n_0 ,\genblk8[4].right_gain_pb[29]_i_32_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_28 (.CI(1'b0), .CO({\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ,\genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ,\genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ,\genblk8[4].right_gain_pb_reg[29]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[4].right_gain_pb[29]_i_33_n_0 ,\genblk8[4].right_gain_pb[29]_i_34_n_0 ,\genblk8[4].right_gain_pb[29]_i_35_n_0 }), .O(\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[4].right_gain_pb[29]_i_36_n_0 ,\genblk8[4].right_gain_pb[29]_i_37_n_0 ,\genblk8[4].right_gain_pb[29]_i_38_n_0 ,\genblk8[4].right_gain_pb[29]_i_39_n_0 })); MUXF7 \genblk8[4].right_gain_pb_reg[29]_i_4 (.I0(\genblk8[4].right_gain_pb[29]_i_7_n_0 ), .I1(\genblk8[4].right_gain_pb[29]_i_8_n_0 ), .O(\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ), .S(p_119_out)); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_5 (.CI(\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ), .CO({\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED [3:1],\genblk8[4].right_gain_pb_reg[29]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED [3:2],\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ,\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[4].right_gain_pb[29]_i_9_n_0 ,\genblk8[4].right_gain_pb[29]_i_10_n_0 })); CARRY4 \genblk8[4].right_gain_pb_reg[29]_i_6 (.CI(\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ), .CO({\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED [3:1],\genblk8[4].right_gain_pb_reg[29]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED [3:2],\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ,\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[4].right_gain_pb[29]_i_11_n_0 ,\genblk8[4].right_gain_pb[29]_i_12_n_0 })); FDRE \genblk8[5].left_edge_found_pb_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk8[5].left_edge_found_pb_reg[5]_0 ), .Q(\genblk8[5].left_loss_pb_reg[30]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[5].left_edge_pb[35]_i_1 (.I0(p_154_out), .I1(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].left_edge_pb[35]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[5].left_edge_pb[35]_i_2 (.I0(match_flag_pb[47]), .I1(\genblk8[5].left_edge_pb[35]_i_3_n_0 ), .I2(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .I3(match_flag_pb[46]), .I4(match_flag_pb[44]), .I5(match_flag_pb[45]), .O(\genblk8[5].right_gain_pb_reg[30]_0 )); LUT4 #( .INIT(16'hFFFE)) \genblk8[5].left_edge_pb[35]_i_3 (.I0(match_flag_pb[42]), .I1(match_flag_pb[43]), .I2(match_flag_pb[40]), .I3(match_flag_pb[41]), .O(\genblk8[5].left_edge_pb[35]_i_3_n_0 )); FDRE \genblk8[5].left_edge_pb_reg[30] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[30] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_edge_pb_reg[31] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[31] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_edge_pb_reg[32] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[32] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_edge_pb_reg[33] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[33] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_edge_pb_reg[34] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[34] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_edge_pb_reg[35] (.C(CLK), .CE(\genblk8[5].left_edge_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[5].left_edge_pb_reg_n_0_[35] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_edge_updated_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk8[5].left_edge_updated_reg[5]_0 ), .Q(D[5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[5].left_loss_pb[35]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[5].left_loss_pb_reg[30]_0 ), .I4(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].left_loss_pb[35]_i_1_n_0 )); FDRE \genblk8[5].left_loss_pb_reg[30] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg_n_0_[30] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_loss_pb_reg[31] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg_n_0_[31] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_loss_pb_reg[32] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_loss_pb_reg[33] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_loss_pb_reg[34] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[5].left_loss_pb_reg[35] (.C(CLK), .CE(\genblk8[5].left_loss_pb[35]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[5].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[40] (.C(CLK), .CE(p_154_out), .D(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .Q(match_flag_pb[40]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[41] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[40]), .Q(match_flag_pb[41]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[42] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[41]), .Q(match_flag_pb[42]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[43] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[42]), .Q(match_flag_pb[43]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[44] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[43]), .Q(match_flag_pb[44]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[45] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[44]), .Q(match_flag_pb[45]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[46] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[45]), .Q(match_flag_pb[46]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[5].match_flag_pb_reg[47] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[46]), .Q(match_flag_pb[47]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[5].right_edge_found_pb_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk8[5].right_edge_found_pb_reg[5]_0 ), .Q(\genblk8[5].right_edge_pb_reg[30]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[5].right_edge_pb[35]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(\genblk8[5].right_gain_pb_reg[30]_0 ), .I2(p_154_out), .I3(\genblk8[5].right_edge_pb_reg[30]_1 ), .I4(\genblk8[5].right_edge_pb_reg[30]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[5].right_edge_pb[35]_i_2 (.I0(p_154_out), .I1(\genblk8[5].right_edge_pb_reg[30]_1 ), .I2(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].right_edge_pb[35]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[5].right_edge_pb[35]_i_3 (.I0(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ), .I1(\genblk8[5].left_edge_pb[35]_i_3_n_0 ), .I2(match_flag_pb[47]), .I3(match_flag_pb[46]), .I4(match_flag_pb[44]), .I5(match_flag_pb[45]), .O(\genblk8[5].right_edge_pb_reg[30]_1 )); FDSE \genblk8[5].right_edge_pb_reg[30] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE \genblk8[5].right_edge_pb_reg[31] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE \genblk8[5].right_edge_pb_reg[32] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE \genblk8[5].right_edge_pb_reg[33] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE \genblk8[5].right_edge_pb_reg[34] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); FDSE \genblk8[5].right_edge_pb_reg[35] (.C(CLK), .CE(\genblk8[5].right_edge_pb[35]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .S(\genblk8[5].right_edge_pb[35]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[30]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ), .O(\genblk8[5].right_gain_pb[30]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[31]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ), .O(\genblk8[5].right_gain_pb[31]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[32]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ), .O(\genblk8[5].right_gain_pb[32]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[33]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ), .I3(\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ), .O(\genblk8[5].right_gain_pb[33]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .O(\genblk8[5].right_gain_pb[33]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .O(\genblk8[5].right_gain_pb[33]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .O(\genblk8[5].right_gain_pb[33]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .O(\genblk8[5].right_gain_pb[33]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .O(\genblk8[5].right_gain_pb[33]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .O(\genblk8[5].right_gain_pb[33]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .O(\genblk8[5].right_gain_pb[33]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[33]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .O(\genblk8[5].right_gain_pb[33]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[34]_i_1 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ), .I3(\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ), .O(\genblk8[5].right_gain_pb[34]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[5].right_gain_pb[35]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[5].right_gain_pb_reg[30]_0 ), .I4(\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .O(\genblk8[5].right_gain_pb[35]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .O(\genblk8[5].right_gain_pb[35]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .O(\genblk8[5].right_gain_pb[35]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[5].right_gain_pb[35]_i_13 (.I0(\genblk8[5].right_gain_pb[35]_i_16_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I2(right_edge_ref[3]), .I3(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I4(right_edge_ref[4]), .O(\genblk8[5].right_gain_pb[35]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[5].right_gain_pb[35]_i_14 (.I0(\genblk8[5].right_gain_pb[35]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(right_edge_ref[4]), .I4(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .O(\genblk8[5].right_gain_pb[35]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[5].right_gain_pb[35]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I3(right_edge_ref[1]), .I4(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I5(right_edge_ref[2]), .O(\genblk8[5].right_gain_pb[35]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[5].right_gain_pb[35]_i_17 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I4(right_edge_ref[2]), .I5(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .O(\genblk8[5].right_gain_pb[35]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[5].right_gain_pb[35]_i_2 (.I0(p_154_out), .I1(\genblk8[5].right_edge_pb_reg[30]_1 ), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[5].right_edge_pb_reg[30]_0 ), .I4(\genblk8[5].right_gain_pb_reg[30]_0 ), .O(\genblk8[5].right_gain_pb[35]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[5].right_gain_pb[35]_i_3 (.I0(\genblk8[5].right_edge_pb_reg[30]_1 ), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ), .I3(\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ), .O(\genblk8[5].right_gain_pb[35]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[5].right_gain_pb[35]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[5].right_gain_pb[35]_i_34 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[5].right_gain_pb[35]_i_35 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[5].right_gain_pb[35]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[5].right_gain_pb[35]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[5].right_gain_pb[35]_i_37 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[5].right_gain_pb[35]_i_38 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[5].right_gain_pb[35]_i_39 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[5].right_gain_pb[35]_i_7 (.I0(\genblk8[5].right_edge_pb_reg[30]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I4(\genblk8[5].right_gain_pb[35]_i_13_n_0 ), .O(\genblk8[5].right_gain_pb[35]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[5].right_gain_pb[35]_i_8 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I1(right_edge_ref[5]), .I2(\genblk8[5].right_gain_pb[35]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ), .I5(\genblk8[5].right_edge_pb_reg[30]_0 ), .O(\genblk8[5].right_gain_pb[35]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[5].right_gain_pb[35]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .O(\genblk8[5].right_gain_pb[35]_i_9_n_0 )); FDRE \genblk8[5].right_gain_pb_reg[30] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[30]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg_n_0_[30] ), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE \genblk8[5].right_gain_pb_reg[31] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[31]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg_n_0_[31] ), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE \genblk8[5].right_gain_pb_reg[32] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[32]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [2]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE \genblk8[5].right_gain_pb_reg[33] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[33]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [3]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); CARRY4 \genblk8[5].right_gain_pb_reg[33]_i_2 (.CI(1'b0), .CO({\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ,\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 }), .S({\genblk8[5].right_gain_pb[33]_i_4_n_0 ,\genblk8[5].right_gain_pb[33]_i_5_n_0 ,\genblk8[5].right_gain_pb[33]_i_6_n_0 ,\genblk8[5].right_gain_pb[33]_i_7_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[33]_i_3 (.CI(1'b0), .CO({\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ,\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 }), .S({\genblk8[5].right_gain_pb[33]_i_8_n_0 ,\genblk8[5].right_gain_pb[33]_i_9_n_0 ,\genblk8[5].right_gain_pb[33]_i_10_n_0 ,\genblk8[5].right_gain_pb[33]_i_11_n_0 })); FDRE \genblk8[5].right_gain_pb_reg[34] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[34]_i_1_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [4]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); FDRE \genblk8[5].right_gain_pb_reg[35] (.C(CLK), .CE(\genblk8[5].right_gain_pb[35]_i_2_n_0 ), .D(\genblk8[5].right_gain_pb[35]_i_3_n_0 ), .Q(\genblk8[5].right_gain_pb_reg__0 [5]), .R(\genblk8[5].right_gain_pb[35]_i_1_n_0 )); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_15 (.CI(\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ), .CO({\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_19_n_0 ,\genblk8[5].right_gain_pb[35]_i_20_n_0 ,\genblk8[5].right_gain_pb[35]_i_21_n_0 ,\genblk8[5].right_gain_pb[35]_i_22_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_18 (.CI(\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ), .CO({\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_24_n_0 ,\genblk8[5].right_gain_pb[35]_i_25_n_0 ,\genblk8[5].right_gain_pb[35]_i_26_n_0 ,\genblk8[5].right_gain_pb[35]_i_27_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_23 (.CI(\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ), .CO({\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_29_n_0 ,\genblk8[5].right_gain_pb[35]_i_30_n_0 ,\genblk8[5].right_gain_pb[35]_i_31_n_0 ,\genblk8[5].right_gain_pb[35]_i_32_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_28 (.CI(1'b0), .CO({\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ,\genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ,\genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ,\genblk8[5].right_gain_pb_reg[35]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[5].right_gain_pb[35]_i_33_n_0 ,\genblk8[5].right_gain_pb[35]_i_34_n_0 ,\genblk8[5].right_gain_pb[35]_i_35_n_0 }), .O(\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[5].right_gain_pb[35]_i_36_n_0 ,\genblk8[5].right_gain_pb[35]_i_37_n_0 ,\genblk8[5].right_gain_pb[35]_i_38_n_0 ,\genblk8[5].right_gain_pb[35]_i_39_n_0 })); MUXF7 \genblk8[5].right_gain_pb_reg[35]_i_4 (.I0(\genblk8[5].right_gain_pb[35]_i_7_n_0 ), .I1(\genblk8[5].right_gain_pb[35]_i_8_n_0 ), .O(\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ), .S(\genblk8[5].right_edge_pb_reg[30]_1 )); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_5 (.CI(\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ), .CO({\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED [3:1],\genblk8[5].right_gain_pb_reg[35]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED [3:2],\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ,\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[5].right_gain_pb[35]_i_9_n_0 ,\genblk8[5].right_gain_pb[35]_i_10_n_0 })); CARRY4 \genblk8[5].right_gain_pb_reg[35]_i_6 (.CI(\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ), .CO({\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED [3:1],\genblk8[5].right_gain_pb_reg[35]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED [3:2],\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ,\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[5].right_gain_pb[35]_i_11_n_0 ,\genblk8[5].right_gain_pb[35]_i_12_n_0 })); FDRE \genblk8[6].left_edge_found_pb_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk8[6].left_edge_found_pb_reg[6]_0 ), .Q(\genblk8[6].left_loss_pb_reg[36]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[6].left_edge_pb[41]_i_1 (.I0(p_154_out), .I1(p_106_out), .O(\genblk8[6].left_edge_pb[41]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[6].left_edge_pb[41]_i_2 (.I0(match_flag_pb[55]), .I1(\genblk8[6].left_edge_pb[41]_i_3_n_0 ), .I2(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .I3(match_flag_pb[54]), .I4(match_flag_pb[52]), .I5(match_flag_pb[53]), .O(p_106_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[6].left_edge_pb[41]_i_3 (.I0(match_flag_pb[50]), .I1(match_flag_pb[51]), .I2(match_flag_pb[48]), .I3(match_flag_pb[49]), .O(\genblk8[6].left_edge_pb[41]_i_3_n_0 )); FDRE \genblk8[6].left_edge_pb_reg[36] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[36] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_edge_pb_reg[37] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[37] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_edge_pb_reg[38] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[38] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_edge_pb_reg[39] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[39] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_edge_pb_reg[40] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[40] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_edge_pb_reg[41] (.C(CLK), .CE(\genblk8[6].left_edge_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[6].left_edge_pb_reg_n_0_[41] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_edge_updated_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk8[6].left_edge_updated_reg[6]_0 ), .Q(D[6]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[6].left_loss_pb[41]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[6].left_loss_pb_reg[36]_0 ), .I4(p_106_out), .O(\genblk8[6].left_loss_pb[41]_i_1_n_0 )); FDRE \genblk8[6].left_loss_pb_reg[36] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg_n_0_[36] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_loss_pb_reg[37] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg_n_0_[37] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_loss_pb_reg[38] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_loss_pb_reg[39] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_loss_pb_reg[40] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[6].left_loss_pb_reg[41] (.C(CLK), .CE(\genblk8[6].left_loss_pb[41]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[6].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[48] (.C(CLK), .CE(p_154_out), .D(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .Q(match_flag_pb[48]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[49] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[48]), .Q(match_flag_pb[49]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[50] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[49]), .Q(match_flag_pb[50]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[51] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[50]), .Q(match_flag_pb[51]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[52] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[51]), .Q(match_flag_pb[52]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[53] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[52]), .Q(match_flag_pb[53]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[54] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[53]), .Q(match_flag_pb[54]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[6].match_flag_pb_reg[55] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[54]), .Q(match_flag_pb[55]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[6].right_edge_found_pb_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk8[6].right_edge_found_pb_reg[6]_0 ), .Q(\genblk8[6].right_edge_pb_reg[36]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[6].right_edge_pb[41]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_106_out), .I2(p_154_out), .I3(p_103_out), .I4(\genblk8[6].right_edge_pb_reg[36]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[6].right_edge_pb[41]_i_2 (.I0(p_154_out), .I1(p_103_out), .I2(p_106_out), .O(\genblk8[6].right_edge_pb[41]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[6].right_edge_pb[41]_i_3 (.I0(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ), .I1(\genblk8[6].left_edge_pb[41]_i_3_n_0 ), .I2(match_flag_pb[55]), .I3(match_flag_pb[54]), .I4(match_flag_pb[52]), .I5(match_flag_pb[53]), .O(p_103_out)); FDSE \genblk8[6].right_edge_pb_reg[36] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE \genblk8[6].right_edge_pb_reg[37] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE \genblk8[6].right_edge_pb_reg[38] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE \genblk8[6].right_edge_pb_reg[39] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE \genblk8[6].right_edge_pb_reg[40] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); FDSE \genblk8[6].right_edge_pb_reg[41] (.C(CLK), .CE(\genblk8[6].right_edge_pb[41]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .S(\genblk8[6].right_edge_pb[41]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[36]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ), .O(\genblk8[6].right_gain_pb[36]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[37]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ), .O(\genblk8[6].right_gain_pb[37]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[38]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ), .O(\genblk8[6].right_gain_pb[38]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[39]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ), .I3(\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ), .O(\genblk8[6].right_gain_pb[39]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .O(\genblk8[6].right_gain_pb[39]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .O(\genblk8[6].right_gain_pb[39]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .O(\genblk8[6].right_gain_pb[39]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .O(\genblk8[6].right_gain_pb[39]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .O(\genblk8[6].right_gain_pb[39]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .O(\genblk8[6].right_gain_pb[39]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .O(\genblk8[6].right_gain_pb[39]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[39]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .O(\genblk8[6].right_gain_pb[39]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[40]_i_1 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ), .I3(\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ), .O(\genblk8[6].right_gain_pb[40]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[6].right_gain_pb[41]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_106_out), .I4(\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .O(\genblk8[6].right_gain_pb[41]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .O(\genblk8[6].right_gain_pb[41]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .O(\genblk8[6].right_gain_pb[41]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[6].right_gain_pb[41]_i_13 (.I0(\genblk8[6].right_gain_pb[41]_i_16_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I2(right_edge_ref[3]), .I3(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I4(right_edge_ref[4]), .O(\genblk8[6].right_gain_pb[41]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[6].right_gain_pb[41]_i_14 (.I0(\genblk8[6].right_gain_pb[41]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I3(right_edge_ref[4]), .I4(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .O(\genblk8[6].right_gain_pb[41]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[6].right_gain_pb[41]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I3(right_edge_ref[1]), .I4(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I5(right_edge_ref[2]), .O(\genblk8[6].right_gain_pb[41]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[6].right_gain_pb[41]_i_17 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I4(right_edge_ref[2]), .I5(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .O(\genblk8[6].right_gain_pb[41]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[6].right_gain_pb[41]_i_2 (.I0(p_154_out), .I1(p_103_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[6].right_edge_pb_reg[36]_0 ), .I4(p_106_out), .O(\genblk8[6].right_gain_pb[41]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[6].right_gain_pb[41]_i_3 (.I0(p_103_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ), .I3(\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ), .O(\genblk8[6].right_gain_pb[41]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[6].right_gain_pb[41]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[6].right_gain_pb[41]_i_34 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[6].right_gain_pb[41]_i_35 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[6].right_gain_pb[41]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[6].right_gain_pb[41]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[6].right_gain_pb[41]_i_37 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[6].right_gain_pb[41]_i_38 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[6].right_gain_pb[41]_i_39 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[6].right_gain_pb[41]_i_7 (.I0(\genblk8[6].right_edge_pb_reg[36]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I4(\genblk8[6].right_gain_pb[41]_i_13_n_0 ), .O(\genblk8[6].right_gain_pb[41]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[6].right_gain_pb[41]_i_8 (.I0(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I1(right_edge_ref[5]), .I2(\genblk8[6].right_gain_pb[41]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ), .I5(\genblk8[6].right_edge_pb_reg[36]_0 ), .O(\genblk8[6].right_gain_pb[41]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[6].right_gain_pb[41]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .O(\genblk8[6].right_gain_pb[41]_i_9_n_0 )); FDRE \genblk8[6].right_gain_pb_reg[36] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[36]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg_n_0_[36] ), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE \genblk8[6].right_gain_pb_reg[37] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[37]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg_n_0_[37] ), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE \genblk8[6].right_gain_pb_reg[38] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[38]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [2]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE \genblk8[6].right_gain_pb_reg[39] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[39]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [3]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); CARRY4 \genblk8[6].right_gain_pb_reg[39]_i_2 (.CI(1'b0), .CO({\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ,\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 }), .S({\genblk8[6].right_gain_pb[39]_i_4_n_0 ,\genblk8[6].right_gain_pb[39]_i_5_n_0 ,\genblk8[6].right_gain_pb[39]_i_6_n_0 ,\genblk8[6].right_gain_pb[39]_i_7_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[39]_i_3 (.CI(1'b0), .CO({\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ,\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 }), .S({\genblk8[6].right_gain_pb[39]_i_8_n_0 ,\genblk8[6].right_gain_pb[39]_i_9_n_0 ,\genblk8[6].right_gain_pb[39]_i_10_n_0 ,\genblk8[6].right_gain_pb[39]_i_11_n_0 })); FDRE \genblk8[6].right_gain_pb_reg[40] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[40]_i_1_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [4]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); FDRE \genblk8[6].right_gain_pb_reg[41] (.C(CLK), .CE(\genblk8[6].right_gain_pb[41]_i_2_n_0 ), .D(\genblk8[6].right_gain_pb[41]_i_3_n_0 ), .Q(\genblk8[6].right_gain_pb_reg__0 [5]), .R(\genblk8[6].right_gain_pb[41]_i_1_n_0 )); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_15 (.CI(\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ), .CO({\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_19_n_0 ,\genblk8[6].right_gain_pb[41]_i_20_n_0 ,\genblk8[6].right_gain_pb[41]_i_21_n_0 ,\genblk8[6].right_gain_pb[41]_i_22_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_18 (.CI(\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ), .CO({\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_24_n_0 ,\genblk8[6].right_gain_pb[41]_i_25_n_0 ,\genblk8[6].right_gain_pb[41]_i_26_n_0 ,\genblk8[6].right_gain_pb[41]_i_27_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_23 (.CI(\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ), .CO({\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_29_n_0 ,\genblk8[6].right_gain_pb[41]_i_30_n_0 ,\genblk8[6].right_gain_pb[41]_i_31_n_0 ,\genblk8[6].right_gain_pb[41]_i_32_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_28 (.CI(1'b0), .CO({\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ,\genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ,\genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ,\genblk8[6].right_gain_pb_reg[41]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[6].right_gain_pb[41]_i_33_n_0 ,\genblk8[6].right_gain_pb[41]_i_34_n_0 ,\genblk8[6].right_gain_pb[41]_i_35_n_0 }), .O(\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[6].right_gain_pb[41]_i_36_n_0 ,\genblk8[6].right_gain_pb[41]_i_37_n_0 ,\genblk8[6].right_gain_pb[41]_i_38_n_0 ,\genblk8[6].right_gain_pb[41]_i_39_n_0 })); MUXF7 \genblk8[6].right_gain_pb_reg[41]_i_4 (.I0(\genblk8[6].right_gain_pb[41]_i_7_n_0 ), .I1(\genblk8[6].right_gain_pb[41]_i_8_n_0 ), .O(\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ), .S(p_103_out)); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_5 (.CI(\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ), .CO({\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED [3:1],\genblk8[6].right_gain_pb_reg[41]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED [3:2],\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ,\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[6].right_gain_pb[41]_i_9_n_0 ,\genblk8[6].right_gain_pb[41]_i_10_n_0 })); CARRY4 \genblk8[6].right_gain_pb_reg[41]_i_6 (.CI(\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ), .CO({\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED [3:1],\genblk8[6].right_gain_pb_reg[41]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED [3:2],\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ,\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[6].right_gain_pb[41]_i_11_n_0 ,\genblk8[6].right_gain_pb[41]_i_12_n_0 })); FDRE \genblk8[7].left_edge_found_pb_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk8[7].left_edge_found_pb_reg[7]_0 ), .Q(\genblk8[7].left_loss_pb_reg[42]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \genblk8[7].left_edge_pb[47]_i_1 (.I0(p_154_out), .I1(p_98_out), .O(\genblk8[7].left_edge_pb[47]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[7].left_edge_pb[47]_i_2 (.I0(match_flag_pb[63]), .I1(\genblk8[7].left_edge_pb[47]_i_3_n_0 ), .I2(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .I3(match_flag_pb[62]), .I4(match_flag_pb[60]), .I5(match_flag_pb[61]), .O(p_98_out)); LUT4 #( .INIT(16'hFFFE)) \genblk8[7].left_edge_pb[47]_i_3 (.I0(match_flag_pb[58]), .I1(match_flag_pb[59]), .I2(match_flag_pb[56]), .I3(match_flag_pb[57]), .O(\genblk8[7].left_edge_pb[47]_i_3_n_0 )); FDRE \genblk8[7].left_edge_pb_reg[42] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[42] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_edge_pb_reg[43] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[43] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_edge_pb_reg[44] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[44] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_edge_pb_reg[45] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[45] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_edge_pb_reg[46] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[46] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_edge_pb_reg[47] (.C(CLK), .CE(\genblk8[7].left_edge_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[7].left_edge_pb_reg_n_0_[47] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_edge_updated_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk8[7].left_edge_updated_reg[7]_1 ), .Q(D[7]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[7].left_loss_pb[47]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(\genblk8[7].left_loss_pb_reg[42]_0 ), .I4(p_98_out), .O(\genblk8[7].left_loss_pb[47]_i_1_n_0 )); FDRE \genblk8[7].left_loss_pb_reg[42] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[0]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg_n_0_[42] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_loss_pb_reg[43] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[1]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg_n_0_[43] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_loss_pb_reg[44] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[2]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [2]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_loss_pb_reg[45] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[3]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_loss_pb_reg[46] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[4]_i_1_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \genblk8[7].left_loss_pb_reg[47] (.C(CLK), .CE(\genblk8[7].left_loss_pb[47]_i_1_n_0 ), .D(\genblk8[0].left_loss_pb[5]_i_2_n_0 ), .Q(\genblk8[7].left_loss_pb_reg__0 [5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[56] (.C(CLK), .CE(p_154_out), .D(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .Q(match_flag_pb[56]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[57] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[56]), .Q(match_flag_pb[57]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[58] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[57]), .Q(match_flag_pb[58]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[59] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[58]), .Q(match_flag_pb[59]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[60] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[59]), .Q(match_flag_pb[60]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[61] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[60]), .Q(match_flag_pb[61]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[62] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[61]), .Q(match_flag_pb[62]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDSE \genblk8[7].match_flag_pb_reg[63] (.C(CLK), .CE(p_154_out), .D(match_flag_pb[62]), .Q(match_flag_pb[63]), .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 )); FDRE \genblk8[7].right_edge_found_pb_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk8[7].right_edge_found_pb_reg[7]_0 ), .Q(\genblk8[7].right_edge_pb_reg[42]_0 ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAABAAAAAAAAA)) \genblk8[7].right_edge_pb[47]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(p_98_out), .I2(p_154_out), .I3(p_95_out), .I4(\genblk8[7].right_edge_pb_reg[42]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_1 ), .O(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); LUT3 #( .INIT(8'h08)) \genblk8[7].right_edge_pb[47]_i_2 (.I0(p_154_out), .I1(p_95_out), .I2(p_98_out), .O(\genblk8[7].right_edge_pb[47]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \genblk8[7].right_edge_pb[47]_i_3 (.I0(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ), .I1(\genblk8[7].left_edge_pb[47]_i_3_n_0 ), .I2(match_flag_pb[63]), .I3(match_flag_pb[62]), .I4(match_flag_pb[60]), .I5(match_flag_pb[61]), .O(p_95_out)); FDSE \genblk8[7].right_edge_pb_reg[42] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].left_edge_pb[0]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE \genblk8[7].right_edge_pb_reg[43] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[1]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE \genblk8[7].right_edge_pb_reg[44] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[2]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE \genblk8[7].right_edge_pb_reg[45] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[3]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE \genblk8[7].right_edge_pb_reg[46] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[4]_i_1_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); FDSE \genblk8[7].right_edge_pb_reg[47] (.C(CLK), .CE(\genblk8[7].right_edge_pb[47]_i_2_n_0 ), .D(\genblk8[0].right_edge_pb[5]_i_3_n_0 ), .Q(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .S(\genblk8[7].right_edge_pb[47]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[42]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ), .O(\genblk8[7].right_gain_pb[42]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[43]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ), .O(\genblk8[7].right_gain_pb[43]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[44]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ), .O(\genblk8[7].right_gain_pb[44]_i_1_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[45]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ), .I3(\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ), .O(\genblk8[7].right_gain_pb[45]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_10 (.I0(right_edge_ref[1]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .O(\genblk8[7].right_gain_pb[45]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_11 (.I0(right_edge_ref[0]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .O(\genblk8[7].right_gain_pb[45]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .O(\genblk8[7].right_gain_pb[45]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .O(\genblk8[7].right_gain_pb[45]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .O(\genblk8[7].right_gain_pb[45]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .O(\genblk8[7].right_gain_pb[45]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_8 (.I0(right_edge_ref[3]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .O(\genblk8[7].right_gain_pb[45]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[45]_i_9 (.I0(right_edge_ref[2]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .O(\genblk8[7].right_gain_pb[45]_i_9_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[46]_i_1 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ), .I3(\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ), .O(\genblk8[7].right_gain_pb[46]_i_1_n_0 )); LUT5 #( .INIT(32'hAEFEAEAE)) \genblk8[7].right_gain_pb[47]_i_1 (.I0(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .I1(right_gain_pb), .I2(p_154_out), .I3(p_98_out), .I4(\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_10 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .O(\genblk8[7].right_gain_pb[47]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_11 (.I0(right_edge_ref[5]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .O(\genblk8[7].right_gain_pb[47]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_12 (.I0(right_edge_ref[4]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .O(\genblk8[7].right_gain_pb[47]_i_12_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[7].right_gain_pb[47]_i_13 (.I0(\genblk8[7].right_gain_pb[47]_i_16_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I2(right_edge_ref[3]), .I3(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I4(right_edge_ref[4]), .O(\genblk8[7].right_gain_pb[47]_i_13_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk8[7].right_gain_pb[47]_i_14 (.I0(\genblk8[7].right_gain_pb[47]_i_17_n_0 ), .I1(right_edge_ref[3]), .I2(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I3(right_edge_ref[4]), .I4(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .O(\genblk8[7].right_gain_pb[47]_i_14_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[7].right_gain_pb[47]_i_16 (.I0(right_edge_ref[0]), .I1(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I3(right_edge_ref[1]), .I4(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I5(right_edge_ref[2]), .O(\genblk8[7].right_gain_pb[47]_i_16_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk8[7].right_gain_pb[47]_i_17 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I1(right_edge_ref[0]), .I2(right_edge_ref[1]), .I3(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I4(right_edge_ref[2]), .I5(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .O(\genblk8[7].right_gain_pb[47]_i_17_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_19 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_19_n_0 )); LUT5 #( .INIT(32'h000000A8)) \genblk8[7].right_gain_pb[47]_i_2 (.I0(p_154_out), .I1(p_95_out), .I2(\genblk8[7].right_edge_pb_reg[42]_1 ), .I3(\genblk8[7].right_edge_pb_reg[42]_0 ), .I4(p_98_out), .O(\genblk8[7].right_gain_pb[47]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_20 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_21 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_22 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_22_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_24 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_25 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_26 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_26_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_27 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_29 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_29_n_0 )); LUT4 #( .INIT(16'hF780)) \genblk8[7].right_gain_pb[47]_i_3 (.I0(p_95_out), .I1(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I2(\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ), .I3(\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ), .O(\genblk8[7].right_gain_pb[47]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_30 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_31 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_32 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_32_n_0 )); LUT4 #( .INIT(16'hF880)) \genblk8[7].right_gain_pb[47]_i_33 (.I0(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_33_n_0 )); LUT6 #( .INIT(64'h0808088CCECECEE0)) \genblk8[7].right_gain_pb[47]_i_34 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_34_n_0 )); LUT4 #( .INIT(16'h8CE0)) \genblk8[7].right_gain_pb[47]_i_35 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \genblk8[7].right_gain_pb[47]_i_36 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\genblk8[7].right_gain_pb[47]_i_36_n_0 )); LUT4 #( .INIT(16'h0660)) \genblk8[7].right_gain_pb[47]_i_37 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I1(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_37_n_0 )); LUT6 #( .INIT(64'h8484844221212118)) \genblk8[7].right_gain_pb[47]_i_38 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_38_n_0 )); LUT4 #( .INIT(16'h4218)) \genblk8[7].right_gain_pb[47]_i_39 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_39_n_0 )); LUT5 #( .INIT(32'h04004404)) \genblk8[7].right_gain_pb[47]_i_7 (.I0(\genblk8[7].right_edge_pb_reg[42]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_1 ), .I2(right_edge_ref[5]), .I3(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I4(\genblk8[7].right_gain_pb[47]_i_13_n_0 ), .O(\genblk8[7].right_gain_pb[47]_i_7_n_0 )); LUT6 #( .INIT(64'h00000000FFB200B2)) \genblk8[7].right_gain_pb[47]_i_8 (.I0(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I1(right_edge_ref[5]), .I2(\genblk8[7].right_gain_pb[47]_i_14_n_0 ), .I3(\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ), .I4(\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_0 ), .O(\genblk8[7].right_gain_pb[47]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \genblk8[7].right_gain_pb[47]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .O(\genblk8[7].right_gain_pb[47]_i_9_n_0 )); FDRE \genblk8[7].right_gain_pb_reg[42] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[42]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg_n_0_[42] ), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE \genblk8[7].right_gain_pb_reg[43] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[43]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg_n_0_[43] ), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE \genblk8[7].right_gain_pb_reg[44] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[44]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [2]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE \genblk8[7].right_gain_pb_reg[45] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[45]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [3]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); CARRY4 \genblk8[7].right_gain_pb_reg[45]_i_2 (.CI(1'b0), .CO({\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_3 }), .CYINIT(1'b0), .DI({\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }), .O({\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ,\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 }), .S({\genblk8[7].right_gain_pb[45]_i_4_n_0 ,\genblk8[7].right_gain_pb[45]_i_5_n_0 ,\genblk8[7].right_gain_pb[45]_i_6_n_0 ,\genblk8[7].right_gain_pb[45]_i_7_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[45]_i_3 (.CI(1'b0), .CO({\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_3 }), .CYINIT(1'b1), .DI(right_edge_ref[3:0]), .O({\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ,\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 }), .S({\genblk8[7].right_gain_pb[45]_i_8_n_0 ,\genblk8[7].right_gain_pb[45]_i_9_n_0 ,\genblk8[7].right_gain_pb[45]_i_10_n_0 ,\genblk8[7].right_gain_pb[45]_i_11_n_0 })); FDRE \genblk8[7].right_gain_pb_reg[46] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[46]_i_1_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [4]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); FDRE \genblk8[7].right_gain_pb_reg[47] (.C(CLK), .CE(\genblk8[7].right_gain_pb[47]_i_2_n_0 ), .D(\genblk8[7].right_gain_pb[47]_i_3_n_0 ), .Q(\genblk8[7].right_gain_pb_reg__0 [5]), .R(\genblk8[7].right_gain_pb[47]_i_1_n_0 )); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_15 (.CI(\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ), .CO({\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_15_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_19_n_0 ,\genblk8[7].right_gain_pb[47]_i_20_n_0 ,\genblk8[7].right_gain_pb[47]_i_21_n_0 ,\genblk8[7].right_gain_pb[47]_i_22_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_18 (.CI(\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ), .CO({\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_18_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_24_n_0 ,\genblk8[7].right_gain_pb[47]_i_25_n_0 ,\genblk8[7].right_gain_pb[47]_i_26_n_0 ,\genblk8[7].right_gain_pb[47]_i_27_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_23 (.CI(\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ), .CO({\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_23_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_29_n_0 ,\genblk8[7].right_gain_pb[47]_i_30_n_0 ,\genblk8[7].right_gain_pb[47]_i_31_n_0 ,\genblk8[7].right_gain_pb[47]_i_32_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_28 (.CI(1'b0), .CO({\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ,\genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ,\genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ,\genblk8[7].right_gain_pb_reg[47]_i_28_n_3 }), .CYINIT(1'b0), .DI({1'b0,\genblk8[7].right_gain_pb[47]_i_33_n_0 ,\genblk8[7].right_gain_pb[47]_i_34_n_0 ,\genblk8[7].right_gain_pb[47]_i_35_n_0 }), .O(\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED [3:0]), .S({\genblk8[7].right_gain_pb[47]_i_36_n_0 ,\genblk8[7].right_gain_pb[47]_i_37_n_0 ,\genblk8[7].right_gain_pb[47]_i_38_n_0 ,\genblk8[7].right_gain_pb[47]_i_39_n_0 })); MUXF7 \genblk8[7].right_gain_pb_reg[47]_i_4 (.I0(\genblk8[7].right_gain_pb[47]_i_7_n_0 ), .I1(\genblk8[7].right_gain_pb[47]_i_8_n_0 ), .O(\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ), .S(p_95_out)); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_5 (.CI(\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ), .CO({\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED [3:1],\genblk8[7].right_gain_pb_reg[47]_i_5_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }), .O({\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED [3:2],\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ,\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 }), .S({1'b0,1'b0,\genblk8[7].right_gain_pb[47]_i_9_n_0 ,\genblk8[7].right_gain_pb[47]_i_10_n_0 })); CARRY4 \genblk8[7].right_gain_pb_reg[47]_i_6 (.CI(\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ), .CO({\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED [3:1],\genblk8[7].right_gain_pb_reg[47]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}), .O({\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED [3:2],\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ,\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 }), .S({1'b0,1'b0,\genblk8[7].right_gain_pb[47]_i_11_n_0 ,\genblk8[7].right_gain_pb[47]_i_12_n_0 })); LUT6 #( .INIT(64'h00000000AAAAAAA2)) \genblk9[0].fine_delay_incdec_pb[0]_i_1 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ), .I1(bit_cnt), .I2(\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ), .I3(\stage_cnt_reg_n_0_[0] ), .I4(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 )); LUT4 #( .INIT(16'hFFFE)) \genblk9[0].fine_delay_incdec_pb[0]_i_10 (.I0(ref_bit[6]), .I1(ref_bit[7]), .I2(ref_bit[4]), .I3(ref_bit[5]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[0].fine_delay_incdec_pb[0]_i_11 (.I0(\genblk8[0].right_gain_pb_reg_n_0_[0] ), .I1(\genblk8[0].left_loss_pb_reg_n_0_[0] ), .I2(\genblk8[0].left_loss_pb_reg_n_0_[1] ), .I3(\genblk8[0].right_gain_pb_reg_n_0_[1] ), .I4(\genblk8[0].left_loss_pb_reg__0 [2]), .I5(\genblk8[0].right_gain_pb_reg__0 [2]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[0].fine_delay_incdec_pb[0]_i_2 (.I0(\genblk8[0].right_gain_pb_reg__0 [5]), .I1(\genblk8[0].left_loss_pb_reg__0 [5]), .I2(\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\fine_delay_mod_reg[26] ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \genblk9[0].fine_delay_incdec_pb[0]_i_3 (.I0(bit_cnt_reg__0[3]), .I1(bit_cnt_reg__0[0]), .I2(bit_cnt_reg__0[4]), .I3(p_1_in159_in), .I4(bit_cnt_reg__0[2]), .I5(\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ), .O(bit_cnt)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'hFFFFFFFE)) \genblk9[0].fine_delay_incdec_pb[0]_i_4 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[0].fine_delay_incdec_pb[0]_i_5 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ), .I1(\genblk8[0].left_loss_pb_reg__0 [3]), .I2(\genblk8[0].right_gain_pb_reg__0 [3]), .I3(\genblk8[0].left_loss_pb_reg__0 [4]), .I4(\genblk8[0].right_gain_pb_reg__0 [4]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT3 #( .INIT(8'h02)) \genblk9[0].fine_delay_incdec_pb[0]_i_6 (.I0(bit_cnt), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT5 #( .INIT(32'h04000000)) \genblk9[0].fine_delay_incdec_pb[0]_i_8 (.I0(Q[3]), .I1(Q[4]), .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), .O(p_1_in159_in)); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT4 #( .INIT(16'hFFFE)) \genblk9[0].fine_delay_incdec_pb[0]_i_9 (.I0(bit_cnt_reg__0[1]), .I1(bit_cnt_reg__0[7]), .I2(bit_cnt_reg__0[5]), .I3(bit_cnt_reg__0[6]), .O(\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 )); FDRE \genblk9[0].fine_delay_incdec_pb_reg[0] (.C(CLK), .CE(1'b1), .D(\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ), .Q(\fine_delay_mod_reg[26] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[1].fine_delay_incdec_pb[1]_i_1 (.I0(\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ), .I1(\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[1].fine_delay_incdec_pb[1]_i_2 (.I0(\genblk8[1].right_gain_pb_reg__0 [5]), .I1(\genblk8[1].left_loss_pb_reg__0 [5]), .I2(\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT5 #( .INIT(32'hFFFFFFEF)) \genblk9[1].fine_delay_incdec_pb[1]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[1].fine_delay_incdec_pb[1]_i_4 (.I0(\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ), .I1(\genblk8[1].left_loss_pb_reg__0 [3]), .I2(\genblk8[1].right_gain_pb_reg__0 [3]), .I3(\genblk8[1].left_loss_pb_reg__0 [4]), .I4(\genblk8[1].right_gain_pb_reg__0 [4]), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[1].fine_delay_incdec_pb[1]_i_5 (.I0(\genblk8[1].right_gain_pb_reg_n_0_[6] ), .I1(\genblk8[1].left_loss_pb_reg_n_0_[6] ), .I2(\genblk8[1].left_loss_pb_reg_n_0_[7] ), .I3(\genblk8[1].right_gain_pb_reg_n_0_[7] ), .I4(\genblk8[1].left_loss_pb_reg__0 [2]), .I5(\genblk8[1].right_gain_pb_reg__0 [2]), .O(\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 )); FDRE \genblk9[1].fine_delay_incdec_pb_reg[1] (.C(CLK), .CE(1'b1), .D(\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ), .Q(\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[2].fine_delay_incdec_pb[2]_i_1 (.I0(\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ), .I1(\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[2].fine_delay_incdec_pb[2]_i_2 (.I0(\genblk8[2].right_gain_pb_reg__0 [5]), .I1(\genblk8[2].left_loss_pb_reg__0 [5]), .I2(\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'hFFFFFFEF)) \genblk9[2].fine_delay_incdec_pb[2]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[0] ), .I2(\ref_bit_reg_n_0_[1] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[2].fine_delay_incdec_pb[2]_i_4 (.I0(\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ), .I1(\genblk8[2].left_loss_pb_reg__0 [3]), .I2(\genblk8[2].right_gain_pb_reg__0 [3]), .I3(\genblk8[2].left_loss_pb_reg__0 [4]), .I4(\genblk8[2].right_gain_pb_reg__0 [4]), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[2].fine_delay_incdec_pb[2]_i_5 (.I0(\genblk8[2].right_gain_pb_reg_n_0_[12] ), .I1(\genblk8[2].left_loss_pb_reg_n_0_[12] ), .I2(\genblk8[2].left_loss_pb_reg_n_0_[13] ), .I3(\genblk8[2].right_gain_pb_reg_n_0_[13] ), .I4(\genblk8[2].left_loss_pb_reg__0 [2]), .I5(\genblk8[2].right_gain_pb_reg__0 [2]), .O(\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 )); FDRE \genblk9[2].fine_delay_incdec_pb_reg[2] (.C(CLK), .CE(1'b1), .D(\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ), .Q(\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[3].fine_delay_incdec_pb[3]_i_1 (.I0(\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ), .I1(\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[3].fine_delay_incdec_pb[3]_i_2 (.I0(\genblk8[3].right_gain_pb_reg__0 [5]), .I1(\genblk8[3].left_loss_pb_reg__0 [5]), .I2(\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT5 #( .INIT(32'hFFFFFFBF)) \genblk9[3].fine_delay_incdec_pb[3]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[3].fine_delay_incdec_pb[3]_i_4 (.I0(\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ), .I1(\genblk8[3].left_loss_pb_reg__0 [3]), .I2(\genblk8[3].right_gain_pb_reg__0 [3]), .I3(\genblk8[3].left_loss_pb_reg__0 [4]), .I4(\genblk8[3].right_gain_pb_reg__0 [4]), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[3].fine_delay_incdec_pb[3]_i_5 (.I0(\genblk8[3].right_gain_pb_reg_n_0_[18] ), .I1(\genblk8[3].left_loss_pb_reg_n_0_[18] ), .I2(\genblk8[3].left_loss_pb_reg_n_0_[19] ), .I3(\genblk8[3].right_gain_pb_reg_n_0_[19] ), .I4(\genblk8[3].left_loss_pb_reg__0 [2]), .I5(\genblk8[3].right_gain_pb_reg__0 [2]), .O(\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 )); FDRE \genblk9[3].fine_delay_incdec_pb_reg[3] (.C(CLK), .CE(1'b1), .D(\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ), .Q(\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[4].fine_delay_incdec_pb[4]_i_1 (.I0(\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ), .I1(\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[4].fine_delay_incdec_pb[4]_i_2 (.I0(\genblk8[4].right_gain_pb_reg__0 [5]), .I1(\genblk8[4].left_loss_pb_reg__0 [5]), .I2(\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\fine_delay_mod_reg[20] ), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT5 #( .INIT(32'hFFFFFFEF)) \genblk9[4].fine_delay_incdec_pb[4]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[2] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[0] ), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[4].fine_delay_incdec_pb[4]_i_4 (.I0(\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ), .I1(\genblk8[4].left_loss_pb_reg__0 [3]), .I2(\genblk8[4].right_gain_pb_reg__0 [3]), .I3(\genblk8[4].left_loss_pb_reg__0 [4]), .I4(\genblk8[4].right_gain_pb_reg__0 [4]), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[4].fine_delay_incdec_pb[4]_i_5 (.I0(\genblk8[4].right_gain_pb_reg_n_0_[24] ), .I1(\genblk8[4].left_loss_pb_reg_n_0_[24] ), .I2(\genblk8[4].left_loss_pb_reg_n_0_[25] ), .I3(\genblk8[4].right_gain_pb_reg_n_0_[25] ), .I4(\genblk8[4].left_loss_pb_reg__0 [2]), .I5(\genblk8[4].right_gain_pb_reg__0 [2]), .O(\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 )); FDRE \genblk9[4].fine_delay_incdec_pb_reg[4] (.C(CLK), .CE(1'b1), .D(\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ), .Q(\fine_delay_mod_reg[20] ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[5].fine_delay_incdec_pb[5]_i_1 (.I0(\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ), .I1(\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[5].fine_delay_incdec_pb[5]_i_2 (.I0(\genblk8[5].right_gain_pb_reg__0 [5]), .I1(\genblk8[5].left_loss_pb_reg__0 [5]), .I2(\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT5 #( .INIT(32'hFFFFFFBF)) \genblk9[5].fine_delay_incdec_pb[5]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[2] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[1] ), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[5].fine_delay_incdec_pb[5]_i_4 (.I0(\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ), .I1(\genblk8[5].left_loss_pb_reg__0 [3]), .I2(\genblk8[5].right_gain_pb_reg__0 [3]), .I3(\genblk8[5].left_loss_pb_reg__0 [4]), .I4(\genblk8[5].right_gain_pb_reg__0 [4]), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[5].fine_delay_incdec_pb[5]_i_5 (.I0(\genblk8[5].right_gain_pb_reg_n_0_[30] ), .I1(\genblk8[5].left_loss_pb_reg_n_0_[30] ), .I2(\genblk8[5].left_loss_pb_reg_n_0_[31] ), .I3(\genblk8[5].right_gain_pb_reg_n_0_[31] ), .I4(\genblk8[5].left_loss_pb_reg__0 [2]), .I5(\genblk8[5].right_gain_pb_reg__0 [2]), .O(\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 )); FDRE \genblk9[5].fine_delay_incdec_pb_reg[5] (.C(CLK), .CE(1'b1), .D(\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ), .Q(\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAAAAAA2)) \genblk9[6].fine_delay_incdec_pb[6]_i_1 (.I0(\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ), .I1(bit_cnt), .I2(\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ), .I3(\stage_cnt_reg_n_0_[0] ), .I4(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[6].fine_delay_incdec_pb[6]_i_2 (.I0(\genblk8[6].right_gain_pb_reg__0 [5]), .I1(\genblk8[6].left_loss_pb_reg__0 [5]), .I2(\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT5 #( .INIT(32'hFFFFFFBF)) \genblk9[6].fine_delay_incdec_pb[6]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[2] ), .I2(\ref_bit_reg_n_0_[1] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[0] ), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[6].fine_delay_incdec_pb[6]_i_4 (.I0(\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ), .I1(\genblk8[6].left_loss_pb_reg__0 [3]), .I2(\genblk8[6].right_gain_pb_reg__0 [3]), .I3(\genblk8[6].left_loss_pb_reg__0 [4]), .I4(\genblk8[6].right_gain_pb_reg__0 [4]), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[6].fine_delay_incdec_pb[6]_i_5 (.I0(\genblk8[6].right_gain_pb_reg_n_0_[36] ), .I1(\genblk8[6].left_loss_pb_reg_n_0_[36] ), .I2(\genblk8[6].left_loss_pb_reg_n_0_[37] ), .I3(\genblk8[6].right_gain_pb_reg_n_0_[37] ), .I4(\genblk8[6].left_loss_pb_reg__0 [2]), .I5(\genblk8[6].right_gain_pb_reg__0 [2]), .O(\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 )); FDRE \genblk9[6].fine_delay_incdec_pb_reg[6] (.C(CLK), .CE(1'b1), .D(\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ), .Q(\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAA8AAAA)) \genblk9[7].fine_delay_incdec_pb[7]_i_1 (.I0(\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ), .I1(\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .I4(bit_cnt), .I5(\genblk8[0].left_edge_pb[5]_i_1_n_0 ), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFFB2FFFFFFB20000)) \genblk9[7].fine_delay_incdec_pb[7]_i_2 (.I0(\genblk8[7].right_gain_pb_reg__0 [5]), .I1(\genblk8[7].left_loss_pb_reg__0 [5]), .I2(\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ), .I4(\stage_cnt_reg[1]_0 ), .I5(\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT5 #( .INIT(32'hFFBFFFFF)) \genblk9[7].fine_delay_incdec_pb[7]_i_3 (.I0(\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ), .I1(\ref_bit_reg_n_0_[1] ), .I2(\ref_bit_reg_n_0_[0] ), .I3(ref_bit[3]), .I4(\ref_bit_reg_n_0_[2] ), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 )); LUT5 #( .INIT(32'hB2FF00B2)) \genblk9[7].fine_delay_incdec_pb[7]_i_4 (.I0(\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ), .I1(\genblk8[7].left_loss_pb_reg__0 [3]), .I2(\genblk8[7].right_gain_pb_reg__0 [3]), .I3(\genblk8[7].left_loss_pb_reg__0 [4]), .I4(\genblk8[7].right_gain_pb_reg__0 [4]), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 )); LUT6 #( .INIT(64'h2F02FFFF00002F02)) \genblk9[7].fine_delay_incdec_pb[7]_i_5 (.I0(\genblk8[7].right_gain_pb_reg_n_0_[42] ), .I1(\genblk8[7].left_loss_pb_reg_n_0_[42] ), .I2(\genblk8[7].left_loss_pb_reg_n_0_[43] ), .I3(\genblk8[7].right_gain_pb_reg_n_0_[43] ), .I4(\genblk8[7].left_loss_pb_reg__0 [2]), .I5(\genblk8[7].right_gain_pb_reg__0 [2]), .O(\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 )); FDRE \genblk9[7].fine_delay_incdec_pb_reg[7] (.C(CLK), .CE(1'b1), .D(\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ), .Q(\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h7)) \init_state_r[0]_i_32 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(rdlvl_stg1_done_int_reg), .O(\init_state_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT5 #( .INIT(32'h000074FF)) \init_state_r[0]_i_35 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(rdlvl_stg1_done_int_reg), .I2(wrcal_done_reg), .I3(dqs_found_done_r_reg), .I4(\num_refresh_reg[1] ), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h3F332F233F332020)) \init_state_r[1]_i_32 (.I0(prbs_last_byte_done), .I1(complex_oclkdelay_calib_done_r1_reg), .I2(rdlvl_stg1_done_int_reg), .I3(rdlvl_stg1_start_int), .I4(rdlvl_last_byte_done), .I5(\one_rank.stg1_wr_done_reg ), .O(\init_state_r_reg[1]_0 )); LUT6 #( .INIT(64'hF0FF808080808080)) \init_state_r[1]_i_45 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(oclkdelay_center_calib_done_r_reg), .I2(rdlvl_stg1_done_int_reg), .I3(wrcal_done_reg), .I4(dqs_found_done_r_reg), .I5(wrlvl_final_mux), .O(\init_state_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT2 #( .INIT(4'h2)) \largest_left_edge[0]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\largest_left_edge[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'h28)) \largest_left_edge[1]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\largest_left_edge[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'h2888)) \largest_left_edge[2]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\largest_left_edge[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'h82222222)) \largest_left_edge[3]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\largest_left_edge[3]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888882222222)) \largest_left_edge[4]_i_1 (.I0(Q[2]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\largest_left_edge[4]_i_1_n_0 )); LUT6 #( .INIT(64'h00002F0000000000)) \largest_left_edge[5]_i_1 (.I0(ref_bit_per_bit0), .I1(\largest_left_edge_reg[0]_0 ), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .I5(\largest_left_edge[5]_i_4_n_0 ), .O(\largest_left_edge[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h2)) \largest_left_edge[5]_i_2 (.I0(Q[2]), .I1(\largest_left_edge[5]_i_5_n_0 ), .O(\largest_left_edge[5]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \largest_left_edge[5]_i_3 (.I0(D[0]), .I1(D[1]), .I2(D[2]), .I3(D[3]), .I4(\largest_left_edge[5]_i_6_n_0 ), .O(ref_bit_per_bit0)); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h81)) \largest_left_edge[5]_i_4 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .O(\largest_left_edge[5]_i_4_n_0 )); LUT6 #( .INIT(64'h00001555FFFFEAAA)) \largest_left_edge[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\largest_left_edge[5]_i_5_n_0 )); LUT4 #( .INIT(16'h0001)) \largest_left_edge[5]_i_6 (.I0(D[6]), .I1(D[7]), .I2(D[5]), .I3(D[4]), .O(\largest_left_edge[5]_i_6_n_0 )); FDRE \largest_left_edge_reg[0] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[0]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \largest_left_edge_reg[1] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[1]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \largest_left_edge_reg[2] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[2]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \largest_left_edge_reg[3] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[3]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \largest_left_edge_reg[4] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[4]_i_1_n_0 ), .Q(\largest_left_edge_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \largest_left_edge_reg[5] (.C(CLK), .CE(\largest_left_edge[5]_i_1_n_0 ), .D(\largest_left_edge[5]_i_2_n_0 ), .Q(\largest_left_edge_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); LUT3 #( .INIT(8'hB8)) \left_edge_ref[0]_i_1 (.I0(\left_edge_ref[2]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[0]_i_2_n_0 ), .O(\left_edge_ref[0]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[0]_i_2 (.I0(\left_edge_ref_reg[4]_i_10_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[0]_i_3_n_0 ), .O(\left_edge_ref[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[0]_i_3 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[0] ), .O(\left_edge_ref[0]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \left_edge_ref[1]_i_1 (.I0(\left_edge_ref[3]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[1]_i_2_n_0 ), .O(\left_edge_ref[1]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[1]_i_2 (.I0(\left_edge_ref_reg[5]_i_16_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[5]_i_15_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[1]_i_3_n_0 ), .O(\left_edge_ref[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[1]_i_3 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[1] ), .O(\left_edge_ref[1]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \left_edge_ref[2]_i_1 (.I0(\left_edge_ref[4]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[2]_i_2_n_0 ), .O(\left_edge_ref[2]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[2]_i_2 (.I0(\left_edge_ref_reg[4]_i_3_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[4]_i_5_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[2]_i_3_n_0 ), .O(\left_edge_ref[2]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[2]_i_3 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[2] ), .O(\left_edge_ref[2]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \left_edge_ref[3]_i_1 (.I0(\left_edge_ref[5]_i_5_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\left_edge_ref[3]_i_2_n_0 ), .O(\left_edge_ref[3]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \left_edge_ref[3]_i_2 (.I0(\left_edge_ref_reg[5]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref[5]_i_7_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\left_edge_ref[3]_i_3_n_0 ), .O(\left_edge_ref[3]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[3]_i_3 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[3] ), .O(\left_edge_ref[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[4]_i_1 (.I0(\left_edge_ref[4]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref_reg[4]_i_3_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\left_edge_ref[4]_i_4_n_0 ), .O(\left_edge_ref[4]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_11 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[20] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[36] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[4] ), .O(\left_edge_ref[4]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_12 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[28] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[44] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[12] ), .O(\left_edge_ref[4]_i_12_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \left_edge_ref[4]_i_2 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\left_edge_ref[4]_i_5_n_0 ), .O(\left_edge_ref[4]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[4]_i_4 (.I0(\left_edge_ref[4]_i_8_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\left_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\left_edge_ref_reg[4]_i_10_n_0 ), .O(\left_edge_ref[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_5 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[26] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[42] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[10] ), .O(\left_edge_ref[4]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_6 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[22] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[38] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[6] ), .O(\left_edge_ref[4]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_7 (.I0(\genblk8[5].left_edge_pb_reg_n_0_[30] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[46] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[14] ), .O(\left_edge_ref[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT4 #( .INIT(16'h00E2)) \left_edge_ref[4]_i_8 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\left_edge_ref[4]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[4]_i_9 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[24] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[40] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[8] ), .O(\left_edge_ref[4]_i_9_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[5]_i_1 (.I0(\left_edge_ref[5]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\left_edge_ref_reg[5]_i_4_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\left_edge_ref[5]_i_5_n_0 ), .O(\left_edge_ref[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \left_edge_ref[5]_i_10 (.I0(\ref_bit_reg_n_0_[1] ), .O(\left_edge_ref[5]_i_10_n_0 )); LUT1 #( .INIT(2'h2)) \left_edge_ref[5]_i_11 (.I0(\ref_bit_reg_n_0_[0] ), .O(\left_edge_ref[5]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_12 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[23] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[39] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[7] ), .O(\left_edge_ref[5]_i_12_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_13 (.I0(\genblk8[5].left_edge_pb_reg_n_0_[31] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[47] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[15] ), .O(\left_edge_ref[5]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT4 #( .INIT(16'h00E2)) \left_edge_ref[5]_i_14 (.I0(\genblk8[2].left_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\left_edge_ref[5]_i_14_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_15 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[25] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[41] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[9] ), .O(\left_edge_ref[5]_i_15_n_0 )); LUT2 #( .INIT(4'h9)) \left_edge_ref[5]_i_17 (.I0(\ref_bit_reg_n_0_[2] ), .I1(ref_bit[4]), .O(\left_edge_ref[5]_i_17_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_18 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[21] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].left_edge_pb_reg_n_0_[37] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].left_edge_pb_reg_n_0_[5] ), .O(\left_edge_ref[5]_i_18_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_19 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[29] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[45] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].left_edge_pb_reg_n_0_[13] ), .O(\left_edge_ref[5]_i_19_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \left_edge_ref[5]_i_2 (.I0(\genblk8[3].left_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].left_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\left_edge_ref[5]_i_7_n_0 ), .O(\left_edge_ref[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \left_edge_ref[5]_i_5 (.I0(\left_edge_ref[5]_i_14_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\left_edge_ref[5]_i_15_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\left_edge_ref_reg[5]_i_16_n_0 ), .O(\left_edge_ref[5]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \left_edge_ref[5]_i_7 (.I0(\genblk8[4].left_edge_pb_reg_n_0_[27] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].left_edge_pb_reg_n_0_[43] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].left_edge_pb_reg_n_0_[11] ), .O(\left_edge_ref[5]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \left_edge_ref[5]_i_8 (.I0(\ref_bit_reg_n_0_[1] ), .I1(ref_bit[3]), .O(\left_edge_ref[5]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \left_edge_ref[5]_i_9 (.I0(\ref_bit_reg_n_0_[0] ), .I1(\ref_bit_reg_n_0_[2] ), .O(\left_edge_ref[5]_i_9_n_0 )); FDRE \left_edge_ref_reg[0] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[0]_i_1_n_0 ), .Q(left_edge_ref[0]), .R(1'b0)); FDRE \left_edge_ref_reg[1] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[1]_i_1_n_0 ), .Q(left_edge_ref[1]), .R(1'b0)); FDRE \left_edge_ref_reg[2] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[2]_i_1_n_0 ), .Q(left_edge_ref[2]), .R(1'b0)); FDRE \left_edge_ref_reg[3] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[3]_i_1_n_0 ), .Q(left_edge_ref[3]), .R(1'b0)); FDRE \left_edge_ref_reg[4] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[4]_i_1_n_0 ), .Q(left_edge_ref[4]), .R(1'b0)); MUXF7 \left_edge_ref_reg[4]_i_10 (.I0(\left_edge_ref[4]_i_11_n_0 ), .I1(\left_edge_ref[4]_i_12_n_0 ), .O(\left_edge_ref_reg[4]_i_10_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); MUXF7 \left_edge_ref_reg[4]_i_3 (.I0(\left_edge_ref[4]_i_6_n_0 ), .I1(\left_edge_ref[4]_i_7_n_0 ), .O(\left_edge_ref_reg[4]_i_3_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); FDRE \left_edge_ref_reg[5] (.C(CLK), .CE(1'b1), .D(\left_edge_ref[5]_i_1_n_0 ), .Q(left_edge_ref[5]), .R(1'b0)); MUXF7 \left_edge_ref_reg[5]_i_16 (.I0(\left_edge_ref[5]_i_18_n_0 ), .I1(\left_edge_ref[5]_i_19_n_0 ), .O(\left_edge_ref_reg[5]_i_16_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); CARRY4 \left_edge_ref_reg[5]_i_3 (.CI(1'b0), .CO({\left_edge_ref_reg[5]_i_3_n_0 ,\left_edge_ref_reg[5]_i_3_n_1 ,\left_edge_ref_reg[5]_i_3_n_2 ,\left_edge_ref_reg[5]_i_3_n_3 }), .CYINIT(1'b0), .DI({\ref_bit_reg_n_0_[1] ,\ref_bit_reg_n_0_[0] ,1'b0,1'b1}), .O({\left_edge_ref_reg[5]_i_3_n_4 ,\left_edge_ref_reg[5]_i_3_n_5 ,\left_edge_ref_reg[5]_i_3_n_6 ,\left_edge_ref_reg[5]_i_3_n_7 }), .S({\left_edge_ref[5]_i_8_n_0 ,\left_edge_ref[5]_i_9_n_0 ,\left_edge_ref[5]_i_10_n_0 ,\left_edge_ref[5]_i_11_n_0 })); MUXF7 \left_edge_ref_reg[5]_i_4 (.I0(\left_edge_ref[5]_i_12_n_0 ), .I1(\left_edge_ref[5]_i_13_n_0 ), .O(\left_edge_ref_reg[5]_i_4_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); CARRY4 \left_edge_ref_reg[5]_i_6 (.CI(\left_edge_ref_reg[5]_i_3_n_0 ), .CO(\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED [3:1],\left_edge_ref_reg[5]_i_6_n_7 }), .S({1'b0,1'b0,1'b0,\left_edge_ref[5]_i_17_n_0 })); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[0]_i_1 (.I0(compare_err_pb_and_reg_n_0), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[0]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[1]_i_1 (.I0(\match_flag_and_reg_n_0_[0] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[1]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[2]_i_1 (.I0(\match_flag_and_reg_n_0_[1] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[2]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[3]_i_1 (.I0(\match_flag_and_reg_n_0_[2] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[3]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[4]_i_1 (.I0(\match_flag_and_reg_n_0_[3] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[4]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[5]_i_1 (.I0(\match_flag_and_reg_n_0_[4] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[5]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[6]_i_1 (.I0(\match_flag_and_reg_n_0_[5] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[6]_i_1_n_0 )); LUT6 #( .INIT(64'h00A2FFFF00A20000)) \match_flag_and[7]_i_1 (.I0(\match_flag_and[7]_i_3_n_0 ), .I1(Q[4]), .I2(num_samples_done_r), .I3(Q[2]), .I4(Q[0]), .I5(no_err_win_detected_reg_0), .O(match_flag_and)); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_and[7]_i_2 (.I0(\match_flag_and_reg_n_0_[6] ), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_and[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h1)) \match_flag_and[7]_i_3 (.I0(Q[1]), .I1(Q[3]), .O(\match_flag_and[7]_i_3_n_0 )); LUT6 #( .INIT(64'h0000444000000000)) \match_flag_and[7]_i_4 (.I0(Q[3]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[2]), .I5(Q[4]), .O(no_err_win_detected_reg_0)); FDSE \match_flag_and_reg[0] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[0]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[0] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[1] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[1]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[1] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[2] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[2]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[2] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[3] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[3]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[3] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[4] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[4]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[4] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[5] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[5]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[5] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[6] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[6]_i_1_n_0 ), .Q(\match_flag_and_reg_n_0_[6] ), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_and_reg[7] (.C(CLK), .CE(match_flag_and), .D(\match_flag_and[7]_i_2_n_0 ), .Q(\match_flag_and_reg_n_0_[7] ), .S(rstdiv0_sync_r1_reg_rep__9)); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[0]_i_1 (.I0(sel0[0]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[0]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[1]_i_1 (.I0(sel0[1]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[1]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[2]_i_1 (.I0(sel0[2]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[2]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[3]_i_1 (.I0(sel0[3]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[3]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[4]_i_1 (.I0(sel0[4]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[4]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[5]_i_1 (.I0(sel0[5]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[5]_i_1_n_0 )); LUT5 #( .INIT(32'hEEE2FFFF)) \match_flag_or[6]_i_1 (.I0(sel0[6]), .I1(Q[1]), .I2(num_samples_done_r), .I3(\match_flag_or_reg[0]_0 ), .I4(Q[4]), .O(\match_flag_or[6]_i_1_n_0 )); FDSE \match_flag_or_reg[0] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[0]_i_1_n_0 ), .Q(sel0[1]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_or_reg[1] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[1]_i_1_n_0 ), .Q(sel0[2]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_or_reg[2] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[2]_i_1_n_0 ), .Q(sel0[3]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_or_reg[3] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[3]_i_1_n_0 ), .Q(sel0[4]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_or_reg[4] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[4]_i_1_n_0 ), .Q(sel0[5]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_or_reg[5] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[5]_i_1_n_0 ), .Q(sel0[6]), .S(rstdiv0_sync_r1_reg_rep__9)); FDSE \match_flag_or_reg[6] (.C(CLK), .CE(match_flag_and), .D(\match_flag_or[6]_i_1_n_0 ), .Q(sel0[7]), .S(rstdiv0_sync_r1_reg_rep__9)); FDRE mux_rd_valid_r_reg (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .Q(mux_rd_valid_r), .R(1'b0)); LUT5 #( .INIT(32'h88888B88)) new_cnt_dqs_r_i_2 (.I0(prech_done), .I1(Q[3]), .I2(prbs_rdlvl_start_r), .I3(prbs_rdlvl_start_reg), .I4(Q[0]), .O(new_cnt_dqs_r)); LUT6 #( .INIT(64'h0030BBBB00308888)) new_cnt_dqs_r_i_3 (.I0(cnt_wait_state), .I1(Q[0]), .I2(prech_done), .I3(prbs_last_byte_done_reg_0), .I4(Q[3]), .I5(prbs_rdlvl_start_reg_0), .O(new_cnt_dqs_r_reg_0)); FDRE new_cnt_dqs_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_0 ), .Q(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .R(rstdiv0_sync_r1_reg_rep__7)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT4 #( .INIT(16'h0100)) no_err_win_detected_i_1 (.I0(Q[1]), .I1(no_err_win_detected_i_2_n_0), .I2(no_err_win_detected_i_3_n_0), .I3(Q[4]), .O(no_err_win_detected_i_1_n_0)); LUT4 #( .INIT(16'hFFFE)) no_err_win_detected_i_2 (.I0(sel0[7]), .I1(sel0[6]), .I2(sel0[4]), .I3(sel0[5]), .O(no_err_win_detected_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) no_err_win_detected_i_3 (.I0(sel0[2]), .I1(sel0[3]), .I2(sel0[0]), .I3(sel0[1]), .O(no_err_win_detected_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT5 #( .INIT(32'h20000003)) no_err_win_detected_latch_i_2 (.I0(no_err_win_detected_latch_reg_0), .I1(Q[4]), .I2(Q[2]), .I3(Q[3]), .I4(Q[1]), .O(no_err_win_detected_latch_reg_1)); FDRE no_err_win_detected_latch_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[3]_1 ), .Q(\largest_left_edge_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE no_err_win_detected_reg (.C(CLK), .CE(match_flag_and), .D(no_err_win_detected_i_1_n_0), .Q(no_err_win_detected_latch_reg_0), .R(rstdiv0_sync_r1_reg_rep__2)); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT2 #( .INIT(4'hE)) num_samples_done_ind_i_2 (.I0(Q[2]), .I1(Q[3]), .O(num_samples_done_ind_reg_0)); FDRE num_samples_done_ind_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_1 ), .Q(\match_flag_or_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__2)); LUT4 #( .INIT(16'hFFFE)) \oclkdelay_ref_cnt[0]_i_3 (.I0(\stg1_wr_rd_cnt_reg[3] ), .I1(rstdiv0_sync_r1_reg_rep__24), .I2(oclkdelay_center_calib_done_r_reg), .I3(ocal_last_byte_done), .O(\oclkdelay_ref_cnt_reg[0] )); FDRE pi_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing), .Q(prbs_pi_stg2_f_en), .R(1'b0)); FDRE pi_en_stg2_f_timing_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing_reg_0), .Q(pi_en_stg2_f_timing), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE pi_stg2_f_incdec_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_f_incdec_timing), .Q(prbs_pi_stg2_f_incdec), .R(1'b0)); FDRE pi_stg2_f_incdec_timing_reg (.C(CLK), .CE(1'b1), .D(prbs_tap_inc_r_reg_0), .Q(pi_stg2_f_incdec_timing), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT3 #( .INIT(8'h47)) \prbs_dec_tap_cnt[0]_i_1 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(Q[2]), .I2(prbs_dec_tap_cnt[0]), .O(\prbs_dec_tap_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'h1AFF1A001A001AFF)) \prbs_dec_tap_cnt[1]_i_1 (.I0(dec_cnt_reg[1]), .I1(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I2(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I3(Q[2]), .I4(prbs_dec_tap_cnt[0]), .I5(prbs_dec_tap_cnt[1]), .O(\prbs_dec_tap_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h060006FF06FF0600)) \prbs_dec_tap_cnt[2]_i_1 (.I0(dec_cnt_reg[2]), .I1(\prbs_dec_tap_cnt[2]_i_2_n_0 ), .I2(\prbs_dec_tap_cnt[2]_i_3_n_0 ), .I3(Q[2]), .I4(\prbs_dec_tap_cnt[2]_i_4_n_0 ), .I5(prbs_dec_tap_cnt[2]), .O(\prbs_dec_tap_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT2 #( .INIT(4'h8)) \prbs_dec_tap_cnt[2]_i_2 (.I0(dec_cnt_reg[1]), .I1(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\prbs_dec_tap_cnt[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT2 #( .INIT(4'h8)) \prbs_dec_tap_cnt[2]_i_3 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I1(\prbs_dec_tap_cnt_reg[1]_0 [1]), .O(\prbs_dec_tap_cnt[2]_i_3_n_0 )); LUT2 #( .INIT(4'h1)) \prbs_dec_tap_cnt[2]_i_4 (.I0(prbs_dec_tap_cnt[0]), .I1(prbs_dec_tap_cnt[1]), .O(\prbs_dec_tap_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'hBBBBBBB88888888B)) \prbs_dec_tap_cnt[3]_i_1 (.I0(\prbs_dec_tap_cnt[3]_i_2_n_0 ), .I1(Q[2]), .I2(prbs_dec_tap_cnt[0]), .I3(prbs_dec_tap_cnt[1]), .I4(prbs_dec_tap_cnt[2]), .I5(prbs_dec_tap_cnt[3]), .O(\prbs_dec_tap_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT5 #( .INIT(32'h006AAAAA)) \prbs_dec_tap_cnt[3]_i_2 (.I0(dec_cnt_reg[3]), .I1(dec_cnt_reg[2]), .I2(dec_cnt_reg[1]), .I3(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I4(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\prbs_dec_tap_cnt[3]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFE0001)) \prbs_dec_tap_cnt[4]_i_2 (.I0(prbs_dec_tap_cnt[3]), .I1(prbs_dec_tap_cnt[2]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[0]), .I4(prbs_dec_tap_cnt[4]), .O(\prbs_dec_tap_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'h00006AAAAAAAAAAA)) \prbs_dec_tap_cnt[4]_i_3 (.I0(dec_cnt_reg[4]), .I1(dec_cnt_reg[3]), .I2(dec_cnt_reg[1]), .I3(dec_cnt_reg[2]), .I4(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I5(\prbs_dec_tap_cnt_reg[1]_0 [0]), .O(\prbs_dec_tap_cnt[4]_i_3_n_0 )); LUT6 #( .INIT(64'h1010100000000000)) \prbs_dec_tap_cnt[5]_i_1 (.I0(Q[4]), .I1(Q[3]), .I2(Q[1]), .I3(p_3_in), .I4(Q[2]), .I5(Q[0]), .O(\prbs_dec_tap_cnt[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \prbs_dec_tap_cnt[5]_i_3 (.I0(prbs_dec_tap_cnt[2]), .I1(prbs_dec_tap_cnt[0]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[4]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[5]), .O(p_3_in)); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \prbs_dec_tap_cnt[5]_i_4 (.I0(prbs_dec_tap_cnt[4]), .I1(prbs_dec_tap_cnt[0]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[2]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[5]), .O(\prbs_dec_tap_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hEAAAAAAAAAAAAAAA)) \prbs_dec_tap_cnt[5]_i_5 (.I0(\prbs_dec_tap_cnt_reg[1]_0 [1]), .I1(dec_cnt_reg[4]), .I2(dec_cnt_reg[2]), .I3(\prbs_dec_tap_cnt_reg[1]_0 [0]), .I4(dec_cnt_reg[1]), .I5(dec_cnt_reg[3]), .O(\prbs_dec_tap_cnt[5]_i_5_n_0 )); FDRE \prbs_dec_tap_cnt_reg[0] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[0]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \prbs_dec_tap_cnt_reg[1] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[1]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \prbs_dec_tap_cnt_reg[2] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[2]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \prbs_dec_tap_cnt_reg[3] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt[3]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \prbs_dec_tap_cnt_reg[4] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ), .Q(prbs_dec_tap_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__9)); MUXF7 \prbs_dec_tap_cnt_reg[4]_i_1 (.I0(\prbs_dec_tap_cnt[4]_i_2_n_0 ), .I1(\prbs_dec_tap_cnt[4]_i_3_n_0 ), .O(\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ), .S(Q[2])); FDRE \prbs_dec_tap_cnt_reg[5] (.C(CLK), .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ), .D(\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ), .Q(prbs_dec_tap_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__9)); MUXF7 \prbs_dec_tap_cnt_reg[5]_i_2 (.I0(\prbs_dec_tap_cnt[5]_i_4_n_0 ), .I1(\prbs_dec_tap_cnt[5]_i_5_n_0 ), .O(\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ), .S(Q[2])); LUT6 #( .INIT(64'h0000000000000800)) \prbs_dqs_cnt_r[1]_i_2 (.I0(prbs_rdlvl_done_reg_1), .I1(Q[3]), .I2(prbs_last_byte_done_reg_0), .I3(prech_done), .I4(Q[1]), .I5(Q[2]), .O(\prbs_dqs_cnt_r_reg[1]_0 )); FDRE \prbs_dqs_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\prbs_dqs_cnt_r_reg[0]_1 ), .Q(\A[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \prbs_dqs_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\prbs_dqs_cnt_r_reg[0]_0 ), .Q(\A[1]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \prbs_dqs_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\prbs_dqs_cnt_r_reg[0]_2 ), .Q(\prbs_dqs_cnt_r_reg[2]_0 ), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT4 #( .INIT(16'h404F)) \prbs_dqs_tap_cnt_r[0]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .O(\prbs_dqs_tap_cnt_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h404F)) \prbs_dqs_tap_cnt_r[0]_rep__0_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .O(\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 )); LUT4 #( .INIT(16'h404F)) \prbs_dqs_tap_cnt_r[0]_rep_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .O(\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 )); LUT6 #( .INIT(64'h0F0066660F009999)) \prbs_dqs_tap_cnt_r[1]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\calib_sel_reg[3] ), .I3(\pi_counter_read_val_reg[5] [1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I5(prbs_tap_inc_r), .O(\prbs_dqs_tap_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0F0066660F009999)) \prbs_dqs_tap_cnt_r[1]_rep__0_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\calib_sel_reg[3] ), .I3(\pi_counter_read_val_reg[5] [1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I5(prbs_tap_inc_r), .O(\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 )); LUT6 #( .INIT(64'h0F0066660F009999)) \prbs_dqs_tap_cnt_r[1]_rep_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .I2(\calib_sel_reg[3] ), .I3(\pi_counter_read_val_reg[5] [1]), .I4(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I5(prbs_tap_inc_r), .O(\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 )); LUT6 #( .INIT(64'h8BB8BB88BB88B88B)) \prbs_dqs_tap_cnt_r[2]_i_1 (.I0(\calib_sel_reg[3]_1 ), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(prbs_tap_inc_r), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_dqs_tap_cnt_r[2]_i_1_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[3]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h7F80)) \prbs_dqs_tap_cnt_r[3]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'h01FE)) \prbs_dqs_tap_cnt_r[3]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[3]_rep__0_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[3]_rep_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 )); LUT6 #( .INIT(64'h8BB888888BB8BBBB)) \prbs_dqs_tap_cnt_r[4]_i_1 (.I0(\calib_sel_reg[3]_2 ), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I4(prbs_tap_inc_r), .I5(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ), .O(\prbs_dqs_tap_cnt_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \prbs_dqs_tap_cnt_r[4]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\prbs_dqs_tap_cnt_r[4]_i_2_n_0 )); LUT5 #( .INIT(32'h0001FFFE)) \prbs_dqs_tap_cnt_r[4]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(\prbs_dqs_tap_cnt_r[4]_i_3_n_0 )); LUT4 #( .INIT(16'hFEAA)) \prbs_dqs_tap_cnt_r[5]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I1(prbs_tap_inc_r), .I2(\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ), .I3(pi_en_stg2_f_timing_reg_0), .O(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 )); LUT5 #( .INIT(32'hB888B8BB)) \prbs_dqs_tap_cnt_r[5]_i_2 (.I0(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]), .I1(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .I2(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ), .I3(prbs_tap_inc_r), .I4(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\prbs_dqs_tap_cnt_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \prbs_dqs_tap_cnt_r[5]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\prbs_dqs_tap_cnt_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \prbs_dqs_tap_cnt_r[5]_i_4 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'h00000001FFFFFFFE)) \prbs_dqs_tap_cnt_r[5]_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 )); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[0]" *) FDRE \prbs_dqs_tap_cnt_r_reg[0] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[0]" *) FDRE \prbs_dqs_tap_cnt_r_reg[0]_rep (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[0]" *) FDRE \prbs_dqs_tap_cnt_r_reg[0]_rep__0 (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[1]" *) FDRE \prbs_dqs_tap_cnt_r_reg[1] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[1]" *) FDRE \prbs_dqs_tap_cnt_r_reg[1]_rep (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[1]" *) FDRE \prbs_dqs_tap_cnt_r_reg[1]_rep__0 (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); FDRE \prbs_dqs_tap_cnt_r_reg[2] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[3]" *) FDRE \prbs_dqs_tap_cnt_r_reg[3] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[3]" *) FDRE \prbs_dqs_tap_cnt_r_reg[3]_rep (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* ORIG_CELL_NAME = "prbs_dqs_tap_cnt_r_reg[3]" *) FDRE \prbs_dqs_tap_cnt_r_reg[3]_rep__0 (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); FDRE \prbs_dqs_tap_cnt_r_reg[4] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \prbs_dqs_tap_cnt_r_reg[5] (.C(CLK), .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ), .D(\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ), .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE prbs_dqs_tap_limit_r_reg (.C(CLK), .CE(1'b1), .D(new_cnt_dqs_r_reg_1), .Q(prbs_dqs_tap_limit_r), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) prbs_found_1st_edge_r_i_2 (.I0(compare_err_latch_reg_n_0), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .I5(prbs_found_1st_edge_r_i_5_n_0), .O(prbs_state_r178_out)); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT2 #( .INIT(4'h1)) prbs_found_1st_edge_r_i_3 (.I0(Q[2]), .I1(Q[4]), .O(complex_pi_incdec_done_reg_1)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h00FF2000)) prbs_found_1st_edge_r_i_4 (.I0(prbs_state_r178_out), .I1(prbs_dqs_tap_limit_r), .I2(num_samples_done_r), .I3(Q[1]), .I4(Q[3]), .O(prbs_found_1st_edge_r_reg_1)); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT2 #( .INIT(4'hE)) prbs_found_1st_edge_r_i_5 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .O(prbs_found_1st_edge_r_i_5_n_0)); FDRE prbs_found_1st_edge_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[3]_0 ), .Q(prbs_found_1st_edge_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__7)); LUT4 #( .INIT(16'h06F6)) \prbs_inc_tap_cnt[0]_i_1 (.I0(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I1(rdlvl_cpt_tap_cnt[0]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[0] ), .O(\prbs_inc_tap_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAA3055CFAACF5530)) \prbs_inc_tap_cnt[1]_i_1 (.I0(\prbs_inc_tap_cnt_reg_n_0_[0] ), .I1(rdlvl_cpt_tap_cnt[0]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(Q[2]), .I4(\prbs_inc_tap_cnt[1]_i_2_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT3 #( .INIT(8'hB8)) \prbs_inc_tap_cnt[1]_i_2 (.I0(\prbs_inc_tap_cnt_reg_n_0_[1] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[1]), .O(\prbs_inc_tap_cnt[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT5 #( .INIT(32'h99699966)) \prbs_inc_tap_cnt[2]_i_1 (.I0(\prbs_inc_tap_cnt[2]_i_2_n_0 ), .I1(\prbs_inc_tap_cnt[2]_i_3_n_0 ), .I2(rdlvl_cpt_tap_cnt[1]), .I3(Q[2]), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFCFAAFFFFFFAACF)) \prbs_inc_tap_cnt[2]_i_2 (.I0(\prbs_inc_tap_cnt_reg_n_0_[0] ), .I1(rdlvl_cpt_tap_cnt[0]), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ), .I3(Q[2]), .I4(\prbs_inc_tap_cnt[1]_i_2_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[2]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(rdlvl_cpt_tap_cnt[2]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[2] ), .O(\prbs_inc_tap_cnt[2]_i_3_n_0 )); LUT6 #( .INIT(64'h6666669699996696)) \prbs_inc_tap_cnt[3]_i_1 (.I0(\prbs_inc_tap_cnt[3]_i_2_n_0 ), .I1(\prbs_inc_tap_cnt[3]_i_3_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(rdlvl_cpt_tap_cnt[2]), .I4(Q[2]), .I5(\prbs_inc_tap_cnt_reg_n_0_[2] ), .O(\prbs_inc_tap_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF477447740000)) \prbs_inc_tap_cnt[3]_i_2 (.I0(\prbs_inc_tap_cnt_reg_n_0_[2] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[2]), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I4(\prbs_inc_tap_cnt[3]_i_4_n_0 ), .I5(\prbs_inc_tap_cnt[2]_i_2_n_0 ), .O(\prbs_inc_tap_cnt[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[3]_i_3 (.I0(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I1(rdlvl_cpt_tap_cnt[3]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[3] ), .O(\prbs_inc_tap_cnt[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT3 #( .INIT(8'h23)) \prbs_inc_tap_cnt[3]_i_4 (.I0(rdlvl_cpt_tap_cnt[1]), .I1(Q[2]), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ), .O(\prbs_inc_tap_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'h6666669699996696)) \prbs_inc_tap_cnt[4]_i_1 (.I0(\prbs_inc_tap_cnt[5]_i_5_n_0 ), .I1(\prbs_inc_tap_cnt[4]_i_2_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I3(rdlvl_cpt_tap_cnt[3]), .I4(Q[2]), .I5(\prbs_inc_tap_cnt_reg_n_0_[3] ), .O(\prbs_inc_tap_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[4]_i_2 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I1(rdlvl_cpt_tap_cnt[4]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[4] ), .O(\prbs_inc_tap_cnt[4]_i_2_n_0 )); LUT5 #( .INIT(32'h00004540)) \prbs_inc_tap_cnt[5]_i_1 (.I0(Q[3]), .I1(\prbs_inc_tap_cnt[5]_i_3_n_0 ), .I2(Q[2]), .I3(\prbs_inc_tap_cnt[5]_i_4_n_0 ), .I4(Q[4]), .O(\prbs_inc_tap_cnt[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7878781EE1E1E178)) \prbs_inc_tap_cnt[5]_i_2 (.I0(\prbs_inc_tap_cnt[5]_i_5_n_0 ), .I1(\prbs_inc_tap_cnt[5]_i_6_n_0 ), .I2(\prbs_inc_tap_cnt[5]_i_7_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I4(Q[2]), .I5(\prbs_inc_tap_cnt[5]_i_8_n_0 ), .O(\prbs_inc_tap_cnt[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'h08)) \prbs_inc_tap_cnt[5]_i_3 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[0]), .I2(Q[1]), .O(\prbs_inc_tap_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000200000)) \prbs_inc_tap_cnt[5]_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(prbs_state_r178_out), .I3(prbs_found_1st_edge_r_reg_0), .I4(num_samples_done_r), .I5(prbs_dqs_tap_limit_r), .O(\prbs_inc_tap_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFF477447740000)) \prbs_inc_tap_cnt[5]_i_5 (.I0(\prbs_inc_tap_cnt_reg_n_0_[3] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[3]), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I4(\prbs_inc_tap_cnt[5]_i_9_n_0 ), .I5(\prbs_inc_tap_cnt[3]_i_2_n_0 ), .O(\prbs_inc_tap_cnt[5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'hFD0D)) \prbs_inc_tap_cnt[5]_i_6 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ), .I1(rdlvl_cpt_tap_cnt[3]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[3] ), .O(\prbs_inc_tap_cnt[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT4 #( .INIT(16'hF909)) \prbs_inc_tap_cnt[5]_i_7 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I1(rdlvl_cpt_tap_cnt[5]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[5] ), .O(\prbs_inc_tap_cnt[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \prbs_inc_tap_cnt[5]_i_8 (.I0(\prbs_inc_tap_cnt_reg_n_0_[4] ), .I1(Q[2]), .I2(rdlvl_cpt_tap_cnt[4]), .O(\prbs_inc_tap_cnt[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'hFD0D)) \prbs_inc_tap_cnt[5]_i_9 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(rdlvl_cpt_tap_cnt[2]), .I2(Q[2]), .I3(\prbs_inc_tap_cnt_reg_n_0_[2] ), .O(\prbs_inc_tap_cnt[5]_i_9_n_0 )); FDRE \prbs_inc_tap_cnt_reg[0] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[0]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \prbs_inc_tap_cnt_reg[1] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[1]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \prbs_inc_tap_cnt_reg[2] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[2]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \prbs_inc_tap_cnt_reg[3] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[3]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \prbs_inc_tap_cnt_reg[4] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[4]_i_1_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \prbs_inc_tap_cnt_reg[5] (.C(CLK), .CE(\prbs_inc_tap_cnt[5]_i_1_n_0 ), .D(\prbs_inc_tap_cnt[5]_i_2_n_0 ), .Q(\prbs_inc_tap_cnt_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT3 #( .INIT(8'hEA)) prbs_last_byte_done_i_2 (.I0(\prbs_dqs_cnt_r_reg[2]_0 ), .I1(\A[0]_0 ), .I2(\A[1]_0 ), .O(prbs_last_byte_done_reg_0)); FDRE prbs_last_byte_done_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_3 ), .Q(prbs_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE prbs_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(prech_done_reg), .Q(prbs_prech_req_r), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT2 #( .INIT(4'h1)) prbs_rdlvl_done_i_2 (.I0(Q[4]), .I1(Q[0]), .O(prbs_rdlvl_done_reg_1)); LUT2 #( .INIT(4'h2)) prbs_rdlvl_done_pulse_i_1 (.I0(complex_oclkdelay_calib_done_r1_reg), .I1(prbs_rdlvl_done_r1), .O(prbs_rdlvl_done_pulse0)); (* MAX_FANOUT = "100" *) (* ORIG_CELL_NAME = "prbs_rdlvl_done_reg" *) FDRE prbs_rdlvl_done_reg (.C(CLK), .CE(1'b1), .D(fine_dly_error_reg_1), .Q(\stg1_wr_rd_cnt_reg[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* IS_FANOUT_CONSTRAINED = "1" *) (* MAX_FANOUT = "100" *) (* ORIG_CELL_NAME = "prbs_rdlvl_done_reg" *) FDRE prbs_rdlvl_done_reg_rep (.C(CLK), .CE(1'b1), .D(fine_dly_error_reg_1), .Q(complex_oclkdelay_calib_done_r1_reg), .R(rstdiv0_sync_r1_reg_rep)); FDRE prbs_rdlvl_prech_req_reg (.C(CLK), .CE(1'b1), .D(prbs_prech_req_r), .Q(prech_req_r_reg), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE prbs_rdlvl_start_r_reg (.C(CLK), .CE(1'b1), .D(prbs_rdlvl_start_reg), .Q(prbs_rdlvl_start_r), .R(1'b0)); LUT6 #( .INIT(64'hFFF0DFDFFFF0D0D0)) \prbs_state_r[0]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(\prbs_state_r[0]_i_2_n_0 ), .I4(\prbs_state_r[0]_i_3_n_0 ), .I5(\prbs_state_r[0]_i_4_n_0 ), .O(\prbs_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h1C1C1C1C1C1D1D1D)) \prbs_state_r[0]_i_2 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(\A[1]_0 ), .I4(\A[0]_0 ), .I5(\prbs_dqs_cnt_r_reg[2]_0 ), .O(\prbs_state_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'hB8)) \prbs_state_r[0]_i_3 (.I0(Q[2]), .I1(Q[4]), .I2(Q[3]), .O(\prbs_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hCCB8FFFFCCB80000)) \prbs_state_r[0]_i_4 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[1]), .I2(p_3_in), .I3(Q[0]), .I4(Q[2]), .I5(\prbs_state_r[0]_i_5_n_0 ), .O(\prbs_state_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'h5445FFFF)) \prbs_state_r[0]_i_5 (.I0(Q[0]), .I1(prbs_dqs_tap_limit_r), .I2(prbs_state_r178_out), .I3(prbs_found_1st_edge_r_reg_0), .I4(Q[1]), .O(\prbs_state_r[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT5 #( .INIT(32'hB8BBB888)) \prbs_state_r[1]_i_1 (.I0(\prbs_state_r[1]_i_2_n_0 ), .I1(Q[4]), .I2(\prbs_state_r[1]_i_3_n_0 ), .I3(Q[3]), .I4(\prbs_state_r[1]_i_4_n_0 ), .O(\prbs_state_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0047FFB80000FFB8)) \prbs_state_r[1]_i_2 (.I0(Q[2]), .I1(Q[4]), .I2(Q[3]), .I3(Q[1]), .I4(Q[0]), .I5(prbs_state_r1), .O(\prbs_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0F000F001F0F1F00)) \prbs_state_r[1]_i_3 (.I0(prbs_tap_en_r_reg_0), .I1(fine_inc_stage_reg_n_0), .I2(Q[1]), .I3(Q[2]), .I4(prbs_last_byte_done_reg_0), .I5(Q[0]), .O(\prbs_state_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT5 #( .INIT(32'h0C0C4C7C)) \prbs_state_r[1]_i_4 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[2]), .I2(Q[1]), .I3(\prbs_state_r[1]_i_6_n_0 ), .I4(Q[0]), .O(\prbs_state_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \prbs_state_r[1]_i_5 (.I0(\prbs_inc_tap_cnt_reg_n_0_[2] ), .I1(\prbs_inc_tap_cnt_reg_n_0_[0] ), .I2(\prbs_inc_tap_cnt_reg_n_0_[1] ), .I3(\prbs_inc_tap_cnt_reg_n_0_[4] ), .I4(\prbs_inc_tap_cnt_reg_n_0_[3] ), .I5(\prbs_inc_tap_cnt_reg_n_0_[5] ), .O(\prbs_state_r[1]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'h15)) \prbs_state_r[1]_i_6 (.I0(prbs_dqs_tap_limit_r), .I1(prbs_state_r178_out), .I2(prbs_found_1st_edge_r_reg_0), .O(\prbs_state_r[1]_i_6_n_0 )); LUT4 #( .INIT(16'h7FFF)) \prbs_state_r[2]_i_10 (.I0(\genblk8[1].right_edge_pb_reg[6]_0 ), .I1(\genblk8[0].right_edge_pb_reg[0]_0 ), .I2(\genblk8[3].right_edge_pb_reg[18]_0 ), .I3(\genblk8[2].right_edge_pb_reg[12]_0 ), .O(\prbs_state_r[2]_i_10_n_0 )); LUT4 #( .INIT(16'hFFFE)) \prbs_state_r[2]_i_11 (.I0(\match_flag_and_reg_n_0_[2] ), .I1(\match_flag_and_reg_n_0_[3] ), .I2(\match_flag_and_reg_n_0_[0] ), .I3(\match_flag_and_reg_n_0_[1] ), .O(\prbs_state_r[2]_i_11_n_0 )); LUT6 #( .INIT(64'h4F00FFFF4F000000)) \prbs_state_r[2]_i_2 (.I0(Q[0]), .I1(prbs_tap_en_r_reg_0), .I2(Q[1]), .I3(Q[2]), .I4(\prbs_state_r[0]_i_3_n_0 ), .I5(\prbs_state_r[2]_i_4_n_0 ), .O(\prbs_state_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFE2E2E2FFE2E2)) \prbs_state_r[2]_i_3 (.I0(Q[3]), .I1(Q[4]), .I2(Q[2]), .I3(prbs_state_r1), .I4(Q[0]), .I5(Q[1]), .O(\prbs_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hFCFCFFFFBB880000)) \prbs_state_r[2]_i_4 (.I0(\prbs_state_r[1]_i_5_n_0 ), .I1(Q[2]), .I2(\prbs_state_r[2]_i_6_n_0 ), .I3(\prbs_state_r[1]_i_6_n_0 ), .I4(Q[1]), .I5(Q[0]), .O(\prbs_state_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'hEAEAEAEAEAEAEAAA)) \prbs_state_r[2]_i_5 (.I0(\prbs_state_r[2]_i_7_n_0 ), .I1(\prbs_state_r[2]_i_8_n_0 ), .I2(\prbs_state_r[2]_i_9_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .O(prbs_state_r1)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \prbs_state_r[2]_i_6 (.I0(prbs_dec_tap_cnt[0]), .I1(prbs_dec_tap_cnt[4]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[5]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[2]), .O(\prbs_state_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'hBAAAAAAAAAAAAAAA)) \prbs_state_r[2]_i_7 (.I0(prbs_dqs_tap_limit_r), .I1(\prbs_state_r[2]_i_10_n_0 ), .I2(\genblk8[5].right_edge_pb_reg[30]_0 ), .I3(\genblk8[4].right_edge_pb_reg[24]_0 ), .I4(\genblk8[6].right_edge_pb_reg[36]_0 ), .I5(\genblk8[7].right_edge_pb_reg[42]_0 ), .O(\prbs_state_r[2]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT5 #( .INIT(32'hFFFFFFFE)) \prbs_state_r[2]_i_8 (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\prbs_state_r[2]_i_8_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \prbs_state_r[2]_i_9 (.I0(compare_err_pb_and_reg_n_0), .I1(\prbs_state_r[2]_i_11_n_0 ), .I2(\match_flag_and_reg_n_0_[6] ), .I3(\match_flag_and_reg_n_0_[7] ), .I4(\match_flag_and_reg_n_0_[4] ), .I5(\match_flag_and_reg_n_0_[5] ), .O(\prbs_state_r[2]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'hE4A5E4A0)) \prbs_state_r[3]_i_1 (.I0(Q[4]), .I1(\prbs_state_r[3]_i_2_n_0 ), .I2(Q[2]), .I3(Q[3]), .I4(\prbs_state_r[3]_i_3_n_0 ), .O(\prbs_state_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( .INIT(32'h0FF0B0FF)) \prbs_state_r[3]_i_2 (.I0(prbs_tap_en_r_reg_0), .I1(fine_inc_stage_reg_n_0), .I2(Q[1]), .I3(Q[2]), .I4(Q[0]), .O(\prbs_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAFFFFFFC00000)) \prbs_state_r[3]_i_3 (.I0(\prbs_state_r[3]_i_4_n_0 ), .I1(prbs_found_1st_edge_r_reg_0), .I2(prbs_state_r178_out), .I3(prbs_dqs_tap_limit_r), .I4(Q[1]), .I5(Q[0]), .O(\prbs_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000100)) \prbs_state_r[3]_i_4 (.I0(prbs_dec_tap_cnt[5]), .I1(prbs_dec_tap_cnt[4]), .I2(prbs_dec_tap_cnt[1]), .I3(prbs_dec_tap_cnt[0]), .I4(prbs_dec_tap_cnt[3]), .I5(prbs_dec_tap_cnt[2]), .O(\prbs_state_r[3]_i_4_n_0 )); LUT5 #( .INIT(32'h00000001)) \prbs_state_r[4]_i_11 (.I0(bit_cnt_reg__0[5]), .I1(bit_cnt_reg__0[4]), .I2(bit_cnt_reg__0[6]), .I3(bit_cnt_reg__0[7]), .I4(fine_delay_sel_i_4_n_0), .O(\prbs_state_r[4]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \prbs_state_r[4]_i_2 (.I0(\prbs_state_r[4]_i_4_n_0 ), .I1(Q[4]), .I2(\prbs_state_r[4]_i_5_n_0 ), .I3(Q[3]), .I4(\prbs_state_r[4]_i_6_n_0 ), .O(\prbs_state_r[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT5 #( .INIT(32'h4E5F4E0A)) \prbs_state_r[4]_i_3 (.I0(Q[4]), .I1(\prbs_state_r[4]_i_7_n_0 ), .I2(Q[2]), .I3(Q[3]), .I4(\prbs_state_r[4]_i_8_n_0 ), .O(\prbs_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'h0A3A3A3A0A0A0A0A)) \prbs_state_r[4]_i_4 (.I0(\prbs_state_r[4]_i_9_n_0 ), .I1(Q[1]), .I2(Q[2]), .I3(prbs_rdlvl_done_reg_0), .I4(Q[0]), .I5(complex_act_start), .O(\prbs_state_r[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT5 #( .INIT(32'hFFF2FC32)) \prbs_state_r[4]_i_5 (.I0(prech_done), .I1(Q[1]), .I2(Q[2]), .I3(Q[0]), .I4(cnt_wait_state), .O(\prbs_state_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFAEF45FFFAEA40)) \prbs_state_r[4]_i_6 (.I0(Q[2]), .I1(num_samples_done_r), .I2(Q[1]), .I3(cnt_wait_state), .I4(Q[0]), .I5(prbs_rdlvl_start_reg_0), .O(\prbs_state_r[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( .INIT(32'hAA080000)) \prbs_state_r[4]_i_7 (.I0(Q[1]), .I1(fine_inc_stage_reg_n_0), .I2(prbs_tap_en_r_reg_0), .I3(Q[0]), .I4(Q[2]), .O(\prbs_state_r[4]_i_7_n_0 )); LUT6 #( .INIT(64'h8080808480848084)) \prbs_state_r[4]_i_8 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(prbs_dqs_tap_limit_r), .I4(prbs_state_r178_out), .I5(prbs_found_1st_edge_r_reg_0), .O(\prbs_state_r[4]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0FFCFAFA0F0C0)) \prbs_state_r[4]_i_9 (.I0(\prbs_state_r[4]_i_11_n_0 ), .I1(\match_flag_or_reg[0]_0 ), .I2(Q[1]), .I3(num_samples_done_r), .I4(Q[0]), .I5(cnt_wait_state), .O(\prbs_state_r[4]_i_9_n_0 )); FDRE \prbs_state_r_reg[0] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[0]_i_1_n_0 ), .Q(Q[0]), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \prbs_state_r_reg[1] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[1]_i_1_n_0 ), .Q(Q[1]), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \prbs_state_r_reg[2] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r_reg[2]_i_1_n_0 ), .Q(Q[2]), .R(rstdiv0_sync_r1_reg_rep__8)); MUXF7 \prbs_state_r_reg[2]_i_1 (.I0(\prbs_state_r[2]_i_2_n_0 ), .I1(\prbs_state_r[2]_i_3_n_0 ), .O(\prbs_state_r_reg[2]_i_1_n_0 ), .S(Q[4])); FDRE \prbs_state_r_reg[3] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[3]_i_1_n_0 ), .Q(Q[3]), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \prbs_state_r_reg[4] (.C(CLK), .CE(\prbs_state_r[4]_i_2_n_0 ), .D(\prbs_state_r[4]_i_3_n_0 ), .Q(Q[4]), .R(rstdiv0_sync_r1_reg_rep__8)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) prbs_tap_en_r_i_2 (.I0(\fine_pi_dec_cnt_reg_n_0_[2] ), .I1(\fine_pi_dec_cnt_reg_n_0_[0] ), .I2(\fine_pi_dec_cnt_reg_n_0_[1] ), .I3(\fine_pi_dec_cnt_reg_n_0_[4] ), .I4(\fine_pi_dec_cnt_reg_n_0_[3] ), .I5(\fine_pi_dec_cnt_reg_n_0_[5] ), .O(prbs_tap_en_r_reg_0)); FDRE prbs_tap_en_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_2 ), .Q(pi_en_stg2_f_timing_reg_0), .R(rstdiv0_sync_r1_reg_rep__8)); LUT6 #( .INIT(64'h888888B8888B8B88)) prbs_tap_inc_r_i_2 (.I0(prbs_tap_inc_r_i_3_n_0), .I1(Q[2]), .I2(Q[0]), .I3(Q[4]), .I4(Q[3]), .I5(Q[1]), .O(prbs_tap_en_r)); LUT6 #( .INIT(64'h1454051504440515)) prbs_tap_inc_r_i_3 (.I0(Q[4]), .I1(Q[1]), .I2(Q[0]), .I3(prbs_dqs_tap_limit_r), .I4(Q[3]), .I5(prbs_tap_en_r_reg_0), .O(prbs_tap_inc_r_i_3_n_0)); FDRE prbs_tap_inc_r_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[0]_1 ), .Q(prbs_tap_inc_r), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE rd_valid_r1_reg (.C(CLK), .CE(1'b1), .D(mux_rd_valid_r), .Q(rd_valid_r1), .R(1'b0)); FDRE rd_valid_r2_reg (.C(CLK), .CE(1'b1), .D(rd_valid_r1), .Q(rd_valid_r2_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'h000000000000E5A5)) \rd_victim_sel[0]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(\rd_victim_sel_reg[2]_1 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_3 ), .I4(num_samples_done_r), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\rd_victim_sel[0]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000DC9C)) \rd_victim_sel[1]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(\rd_victim_sel_reg[2]_1 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_3 ), .I4(num_samples_done_r), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\rd_victim_sel[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000FF40)) \rd_victim_sel[2]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(\rd_victim_sel_reg[2]_1 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_3 ), .I4(num_samples_done_r), .I5(rstdiv0_sync_r1_reg_rep__24), .O(\rd_victim_sel[2]_i_1_n_0 )); FDRE \rd_victim_sel_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel[0]_i_1_n_0 ), .Q(\rd_victim_sel_reg[2]_2 ), .R(1'b0)); FDRE \rd_victim_sel_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel[1]_i_1_n_0 ), .Q(\rd_victim_sel_reg[2]_1 ), .R(1'b0)); FDRE \rd_victim_sel_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_victim_sel[2]_i_1_n_0 ), .Q(\rd_victim_sel_reg[2]_3 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[0]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [0]), .O(\rdlvl_cpt_tap_cnt_reg[5]_1 [0])); LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[3]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [2]), .O(\rdlvl_cpt_tap_cnt_reg[5]_1 [1])); LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[5]_i_1 (.I0(\calib_sel_reg[3] ), .I1(\pi_counter_read_val_reg[5] [3]), .O(\rdlvl_cpt_tap_cnt_reg[5]_1 [2])); FDRE \rdlvl_cpt_tap_cnt_reg[0] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\rdlvl_cpt_tap_cnt_reg[5]_1 [0]), .Q(rdlvl_cpt_tap_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \rdlvl_cpt_tap_cnt_reg[1] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\calib_sel_reg[3]_0 ), .Q(rdlvl_cpt_tap_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \rdlvl_cpt_tap_cnt_reg[2] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\calib_sel_reg[3]_1 ), .Q(rdlvl_cpt_tap_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \rdlvl_cpt_tap_cnt_reg[3] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]), .Q(rdlvl_cpt_tap_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \rdlvl_cpt_tap_cnt_reg[4] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\calib_sel_reg[3]_2 ), .Q(rdlvl_cpt_tap_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__9)); FDRE \rdlvl_cpt_tap_cnt_reg[5] (.C(CLK), .CE(\rdlvl_cpt_tap_cnt_reg[5]_0 ), .D(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]), .Q(rdlvl_cpt_tap_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__9)); LUT5 #( .INIT(32'h80880080)) \ref_bit[7]_i_1 (.I0(bit_cnt0), .I1(ref_right_edge125_in), .I2(\ref_bit[7]_i_3_n_0 ), .I3(\ref_right_edge[5]_i_1_n_0 ), .I4(\ref_right_edge_reg_n_0_[5] ), .O(ref_right_edge)); LUT5 #( .INIT(32'hB2FF00B2)) \ref_bit[7]_i_3 (.I0(\ref_bit[7]_i_6_n_0 ), .I1(\ref_right_edge[3]_i_1_n_0 ), .I2(\ref_right_edge_reg_n_0_[3] ), .I3(\ref_right_edge[4]_i_1_n_0 ), .I4(\ref_right_edge_reg_n_0_[4] ), .O(\ref_bit[7]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_bit[7]_i_4 (.I0(\ref_bit_per_bit_reg_n_0_[3] ), .I1(\ref_bit_per_bit_reg_n_0_[2] ), .I2(bit_cnt_reg__0[1]), .I3(\ref_bit_per_bit_reg_n_0_[1] ), .I4(bit_cnt_reg__0[0]), .I5(\ref_bit_per_bit_reg_n_0_[0] ), .O(\ref_bit[7]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_bit[7]_i_5 (.I0(\ref_bit_per_bit_reg_n_0_[7] ), .I1(\ref_bit_per_bit_reg_n_0_[6] ), .I2(bit_cnt_reg__0[1]), .I3(\ref_bit_per_bit_reg_n_0_[5] ), .I4(bit_cnt_reg__0[0]), .I5(\ref_bit_per_bit_reg_n_0_[4] ), .O(\ref_bit[7]_i_5_n_0 )); LUT6 #( .INIT(64'hDF0DFFFF0000DF0D)) \ref_bit[7]_i_6 (.I0(\ref_right_edge[0]_i_1_n_0 ), .I1(\ref_right_edge_reg_n_0_[0] ), .I2(\ref_right_edge[1]_i_1_n_0 ), .I3(\ref_right_edge_reg_n_0_[1] ), .I4(\ref_right_edge[2]_i_1_n_0 ), .I5(\ref_right_edge_reg_n_0_[2] ), .O(\ref_bit[7]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000200000)) \ref_bit_per_bit[7]_i_1 (.I0(ref_bit_per_bit0), .I1(\ref_bit_per_bit[7]_i_2_n_0 ), .I2(Q[0]), .I3(\ref_bit_per_bit[7]_i_3_n_0 ), .I4(Q[1]), .I5(Q[4]), .O(ref_bit_per_bit)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT2 #( .INIT(4'hE)) \ref_bit_per_bit[7]_i_2 (.I0(\stage_cnt_reg_n_0_[0] ), .I1(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .O(\ref_bit_per_bit[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h7)) \ref_bit_per_bit[7]_i_3 (.I0(Q[2]), .I1(Q[3]), .O(\ref_bit_per_bit[7]_i_3_n_0 )); FDRE \ref_bit_per_bit_reg[0] (.C(CLK), .CE(ref_bit_per_bit), .D(D[0]), .Q(\ref_bit_per_bit_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[1] (.C(CLK), .CE(ref_bit_per_bit), .D(D[1]), .Q(\ref_bit_per_bit_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[2] (.C(CLK), .CE(ref_bit_per_bit), .D(D[2]), .Q(\ref_bit_per_bit_reg_n_0_[2] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[3] (.C(CLK), .CE(ref_bit_per_bit), .D(D[3]), .Q(\ref_bit_per_bit_reg_n_0_[3] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[4] (.C(CLK), .CE(ref_bit_per_bit), .D(D[4]), .Q(\ref_bit_per_bit_reg_n_0_[4] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[5] (.C(CLK), .CE(ref_bit_per_bit), .D(D[5]), .Q(\ref_bit_per_bit_reg_n_0_[5] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[6] (.C(CLK), .CE(ref_bit_per_bit), .D(D[6]), .Q(\ref_bit_per_bit_reg_n_0_[6] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_per_bit_reg[7] (.C(CLK), .CE(ref_bit_per_bit), .D(D[7]), .Q(\ref_bit_per_bit_reg_n_0_[7] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[0] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[0]), .Q(\ref_bit_reg_n_0_[0] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[1] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[1]), .Q(\ref_bit_reg_n_0_[1] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[2] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[2]), .Q(\ref_bit_reg_n_0_[2] ), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[3] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[3]), .Q(ref_bit[3]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[4] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[4]), .Q(ref_bit[4]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[5] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[5]), .Q(ref_bit[5]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[6] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[6]), .Q(ref_bit[6]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDRE \ref_bit_reg[7] (.C(CLK), .CE(ref_right_edge), .D(bit_cnt_reg__0[7]), .Q(ref_bit[7]), .R(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_bit_reg[7]_i_2 (.I0(\ref_bit[7]_i_4_n_0 ), .I1(\ref_bit[7]_i_5_n_0 ), .O(ref_right_edge125_in), .S(bit_cnt_reg__0[2])); LUT5 #( .INIT(32'hB8BBB888)) \ref_right_edge[0]_i_1 (.I0(\ref_right_edge[2]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge_reg[0]_i_2_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_6 ), .I4(\ref_right_edge[0]_i_3_n_0 ), .O(\ref_right_edge[0]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[0]_i_3 (.I0(\ref_right_edge[4]_i_9_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_5 ), .I2(\ref_right_edge[0]_i_4_n_0 ), .O(\ref_right_edge[0]_i_3_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[0]_i_4 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\ref_right_edge[0]_i_4_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \ref_right_edge[1]_i_1 (.I0(\ref_right_edge[3]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge_reg[1]_i_2_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_6 ), .I4(\ref_right_edge[1]_i_3_n_0 ), .O(\ref_right_edge[1]_i_1_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[1]_i_3 (.I0(\ref_right_edge[5]_i_15_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_5 ), .I2(\ref_right_edge[1]_i_6_n_0 ), .O(\ref_right_edge[1]_i_3_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[1]_i_4 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\ref_right_edge[1]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[1]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\ref_right_edge[1]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[1]_i_6 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\ref_right_edge[1]_i_6_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[2]_i_1 (.I0(\ref_right_edge[4]_i_4_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge[2]_i_2_n_0 ), .O(\ref_right_edge[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_right_edge[2]_i_2 (.I0(\ref_right_edge[4]_i_7_n_0 ), .I1(\ref_right_edge[4]_i_6_n_0 ), .I2(\ref_right_edge_reg[5]_i_3_n_6 ), .I3(\ref_right_edge[4]_i_5_n_0 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[2]_i_3_n_0 ), .O(\ref_right_edge[2]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[2]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\ref_right_edge[2]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \ref_right_edge[3]_i_1 (.I0(\ref_right_edge[5]_i_5_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_7 ), .I2(\ref_right_edge[3]_i_2_n_0 ), .O(\ref_right_edge[3]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_right_edge[3]_i_2 (.I0(\ref_right_edge[5]_i_13_n_0 ), .I1(\ref_right_edge[5]_i_12_n_0 ), .I2(\ref_right_edge_reg[5]_i_3_n_6 ), .I3(\ref_right_edge[5]_i_7_n_0 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[3]_i_3_n_0 ), .O(\ref_right_edge[3]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[3]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\ref_right_edge[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \ref_right_edge[4]_i_1 (.I0(\ref_right_edge[4]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_6 ), .I2(\ref_right_edge_reg[4]_i_3_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_7 ), .I4(\ref_right_edge[4]_i_4_n_0 ), .O(\ref_right_edge[4]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_10 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\ref_right_edge[4]_i_10_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_11 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\ref_right_edge[4]_i_11_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \ref_right_edge[4]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[4]_i_5_n_0 ), .O(\ref_right_edge[4]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \ref_right_edge[4]_i_4 (.I0(\ref_right_edge[4]_i_8_n_0 ), .I1(\ref_right_edge[4]_i_9_n_0 ), .I2(\ref_right_edge_reg[5]_i_3_n_6 ), .I3(\ref_right_edge[4]_i_10_n_0 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[4]_i_11_n_0 ), .O(\ref_right_edge[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\ref_right_edge[4]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_6 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\ref_right_edge[4]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_7 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\ref_right_edge[4]_i_7_n_0 )); LUT4 #( .INIT(16'h00E2)) \ref_right_edge[4]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .O(\ref_right_edge[4]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[4]_i_9 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\ref_right_edge[4]_i_9_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \ref_right_edge[5]_i_1 (.I0(\ref_right_edge[5]_i_2_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_6 ), .I2(\ref_right_edge_reg[5]_i_4_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_7 ), .I4(\ref_right_edge[5]_i_5_n_0 ), .O(\ref_right_edge[5]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \ref_right_edge[5]_i_10 (.I0(bit_cnt_reg__0[1]), .O(\ref_right_edge[5]_i_10_n_0 )); LUT1 #( .INIT(2'h2)) \ref_right_edge[5]_i_11 (.I0(bit_cnt_reg__0[0]), .O(\ref_right_edge[5]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_12 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\ref_right_edge[5]_i_12_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_13 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\ref_right_edge[5]_i_13_n_0 )); LUT4 #( .INIT(16'h00E2)) \ref_right_edge[5]_i_14 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .O(\ref_right_edge[5]_i_14_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_15 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\ref_right_edge[5]_i_15_n_0 )); LUT2 #( .INIT(4'h9)) \ref_right_edge[5]_i_16 (.I0(bit_cnt_reg__0[2]), .I1(bit_cnt_reg__0[4]), .O(\ref_right_edge[5]_i_16_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \ref_right_edge[5]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\ref_right_edge_reg[5]_i_3_n_5 ), .I5(\ref_right_edge[5]_i_7_n_0 ), .O(\ref_right_edge[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \ref_right_edge[5]_i_5 (.I0(\ref_right_edge[5]_i_14_n_0 ), .I1(\ref_right_edge_reg[5]_i_3_n_5 ), .I2(\ref_right_edge[5]_i_15_n_0 ), .I3(\ref_right_edge_reg[5]_i_3_n_6 ), .I4(\ref_right_edge_reg[1]_i_2_n_0 ), .O(\ref_right_edge[5]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \ref_right_edge[5]_i_7 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I1(\ref_right_edge_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I3(\ref_right_edge_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\ref_right_edge[5]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \ref_right_edge[5]_i_8 (.I0(bit_cnt_reg__0[1]), .I1(bit_cnt_reg__0[3]), .O(\ref_right_edge[5]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \ref_right_edge[5]_i_9 (.I0(bit_cnt_reg__0[0]), .I1(bit_cnt_reg__0[2]), .O(\ref_right_edge[5]_i_9_n_0 )); FDSE \ref_right_edge_reg[0] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[0]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[0] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_right_edge_reg[0]_i_2 (.I0(\ref_right_edge[4]_i_11_n_0 ), .I1(\ref_right_edge[4]_i_10_n_0 ), .O(\ref_right_edge_reg[0]_i_2_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); FDSE \ref_right_edge_reg[1] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[1]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[1] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_right_edge_reg[1]_i_2 (.I0(\ref_right_edge[1]_i_4_n_0 ), .I1(\ref_right_edge[1]_i_5_n_0 ), .O(\ref_right_edge_reg[1]_i_2_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); FDSE \ref_right_edge_reg[2] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[2]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[2] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \ref_right_edge_reg[3] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[3]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[3] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); FDSE \ref_right_edge_reg[4] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[4]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[4] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); MUXF7 \ref_right_edge_reg[4]_i_3 (.I0(\ref_right_edge[4]_i_6_n_0 ), .I1(\ref_right_edge[4]_i_7_n_0 ), .O(\ref_right_edge_reg[4]_i_3_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); FDSE \ref_right_edge_reg[5] (.C(CLK), .CE(ref_right_edge), .D(\ref_right_edge[5]_i_1_n_0 ), .Q(\ref_right_edge_reg_n_0_[5] ), .S(\genblk8[0].left_edge_pb[5]_i_1_n_0 )); CARRY4 \ref_right_edge_reg[5]_i_3 (.CI(1'b0), .CO({\ref_right_edge_reg[5]_i_3_n_0 ,\ref_right_edge_reg[5]_i_3_n_1 ,\ref_right_edge_reg[5]_i_3_n_2 ,\ref_right_edge_reg[5]_i_3_n_3 }), .CYINIT(1'b0), .DI({bit_cnt_reg__0[1:0],1'b0,1'b1}), .O({\ref_right_edge_reg[5]_i_3_n_4 ,\ref_right_edge_reg[5]_i_3_n_5 ,\ref_right_edge_reg[5]_i_3_n_6 ,\ref_right_edge_reg[5]_i_3_n_7 }), .S({\ref_right_edge[5]_i_8_n_0 ,\ref_right_edge[5]_i_9_n_0 ,\ref_right_edge[5]_i_10_n_0 ,\ref_right_edge[5]_i_11_n_0 })); MUXF7 \ref_right_edge_reg[5]_i_4 (.I0(\ref_right_edge[5]_i_12_n_0 ), .I1(\ref_right_edge[5]_i_13_n_0 ), .O(\ref_right_edge_reg[5]_i_4_n_0 ), .S(\ref_right_edge_reg[5]_i_3_n_5 )); CARRY4 \ref_right_edge_reg[5]_i_6 (.CI(\ref_right_edge_reg[5]_i_3_n_0 ), .CO(\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED [3:1],\ref_right_edge_reg[5]_i_6_n_7 }), .S({1'b0,1'b0,1'b0,\ref_right_edge[5]_i_16_n_0 })); LUT2 #( .INIT(4'hE)) reset_rd_addr_r1_i_1 (.I0(reset_rd_addr), .I1(complex_ocal_reset_rd_addr), .O(reset_rd_addr0)); FDRE reset_rd_addr_reg (.C(CLK), .CE(1'b1), .D(\prbs_state_r_reg[4]_2 ), .Q(reset_rd_addr), .R(rstdiv0_sync_r1_reg_rep__9)); LUT6 #( .INIT(64'h00000000FFFFFFFD)) right_edge_found_i_2 (.I0(right_edge_found_i_4_n_0), .I1(\genblk8[3].right_edge_pb_reg[18]_0 ), .I2(\genblk8[2].right_edge_pb_reg[12]_0 ), .I3(\genblk8[1].right_edge_pb_reg[6]_0 ), .I4(\genblk8[0].right_edge_pb_reg[0]_0 ), .I5(right_edge_found_reg_0), .O(right_edge_found_reg_1)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'h80000008)) right_edge_found_i_3 (.I0(Q[1]), .I1(right_edge_found_i_5_n_0), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .O(right_edge_found)); LUT4 #( .INIT(16'h0001)) right_edge_found_i_4 (.I0(\genblk8[6].right_edge_pb_reg[36]_0 ), .I1(\genblk8[7].right_edge_pb_reg[42]_0 ), .I2(\genblk8[5].right_edge_pb_reg[30]_0 ), .I3(\genblk8[4].right_edge_pb_reg[24]_0 ), .O(right_edge_found_i_4_n_0)); LUT6 #( .INIT(64'h0FE00FE00FE000E0)) right_edge_found_i_5 (.I0(right_edge_found_reg_1), .I1(no_err_win_detected_latch_reg_0), .I2(Q[3]), .I3(Q[4]), .I4(num_samples_done_r), .I5(\match_flag_or_reg[0]_0 ), .O(right_edge_found_i_5_n_0)); FDRE right_edge_found_reg (.C(CLK), .CE(1'b1), .D(no_err_win_detected_reg_1), .Q(right_edge_found_reg_0), .R(rstdiv0_sync_r1_reg_rep__7)); LUT3 #( .INIT(8'hB8)) \right_edge_ref[0]_i_1 (.I0(\right_edge_ref[2]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[0]_i_2_n_0 ), .O(\right_edge_ref[0]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[0]_i_2 (.I0(\right_edge_ref_reg[4]_i_10_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[0]_i_3_n_0 ), .O(\right_edge_ref[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[0]_i_3 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[0] ), .O(\right_edge_ref[0]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \right_edge_ref[1]_i_1 (.I0(\right_edge_ref[3]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[1]_i_2_n_0 ), .O(\right_edge_ref[1]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[1]_i_2 (.I0(\right_edge_ref_reg[5]_i_10_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[5]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[1]_i_3_n_0 ), .O(\right_edge_ref[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[1]_i_3 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[1] ), .O(\right_edge_ref[1]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \right_edge_ref[2]_i_1 (.I0(\right_edge_ref[4]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[2]_i_2_n_0 ), .O(\right_edge_ref[2]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[2]_i_2 (.I0(\right_edge_ref_reg[4]_i_3_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[4]_i_5_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[2]_i_3_n_0 ), .O(\right_edge_ref[2]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[2]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[2] ), .O(\right_edge_ref[2]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \right_edge_ref[3]_i_1 (.I0(\right_edge_ref[5]_i_4_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_7 ), .I2(\right_edge_ref[3]_i_2_n_0 ), .O(\right_edge_ref[3]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \right_edge_ref[3]_i_2 (.I0(\right_edge_ref_reg[5]_i_3_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref[5]_i_5_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_5 ), .I4(\right_edge_ref[3]_i_3_n_0 ), .O(\right_edge_ref[3]_i_2_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[3]_i_3 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[3] ), .O(\right_edge_ref[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[4]_i_1 (.I0(\right_edge_ref[4]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref_reg[4]_i_3_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\right_edge_ref[4]_i_4_n_0 ), .O(\right_edge_ref[4]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_11 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[20] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[36] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[4] ), .O(\right_edge_ref[4]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_12 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[28] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[44] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[12] ), .O(\right_edge_ref[4]_i_12_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \right_edge_ref[4]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[18] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[34] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\right_edge_ref[4]_i_5_n_0 ), .O(\right_edge_ref[4]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[4]_i_4 (.I0(\right_edge_ref[4]_i_8_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\right_edge_ref[4]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\right_edge_ref_reg[4]_i_10_n_0 ), .O(\right_edge_ref[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[26] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[42] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[10] ), .O(\right_edge_ref[4]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_6 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[22] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[38] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[6] ), .O(\right_edge_ref[4]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_7 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[30] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[46] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[14] ), .O(\right_edge_ref[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT4 #( .INIT(16'h00E2)) \right_edge_ref[4]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[16] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[32] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\right_edge_ref[4]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[4]_i_9 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[24] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[40] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[8] ), .O(\right_edge_ref[4]_i_9_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[5]_i_1 (.I0(\right_edge_ref[5]_i_2_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_6 ), .I2(\right_edge_ref_reg[5]_i_3_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_7 ), .I4(\right_edge_ref[5]_i_4_n_0 ), .O(\right_edge_ref[5]_i_1_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_11 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[21] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[37] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[0].right_edge_pb_reg_n_0_[5] ), .O(\right_edge_ref[5]_i_11_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_12 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[29] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[45] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[13] ), .O(\right_edge_ref[5]_i_12_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \right_edge_ref[5]_i_2 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[19] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[35] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\left_edge_ref_reg[5]_i_3_n_5 ), .I5(\right_edge_ref[5]_i_5_n_0 ), .O(\right_edge_ref[5]_i_2_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \right_edge_ref[5]_i_4 (.I0(\right_edge_ref[5]_i_8_n_0 ), .I1(\left_edge_ref_reg[5]_i_3_n_5 ), .I2(\right_edge_ref[5]_i_9_n_0 ), .I3(\left_edge_ref_reg[5]_i_3_n_6 ), .I4(\right_edge_ref_reg[5]_i_10_n_0 ), .O(\right_edge_ref[5]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_5 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[27] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[43] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[11] ), .O(\right_edge_ref[5]_i_5_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_6 (.I0(\genblk8[3].right_edge_pb_reg_n_0_[23] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[39] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[7] ), .O(\right_edge_ref[5]_i_6_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_7 (.I0(\genblk8[5].right_edge_pb_reg_n_0_[31] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[7].right_edge_pb_reg_n_0_[47] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[2].right_edge_pb_reg_n_0_[15] ), .O(\right_edge_ref[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT4 #( .INIT(16'h00E2)) \right_edge_ref[5]_i_8 (.I0(\genblk8[2].right_edge_pb_reg_n_0_[17] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[5].right_edge_pb_reg_n_0_[33] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .O(\right_edge_ref[5]_i_8_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \right_edge_ref[5]_i_9 (.I0(\genblk8[4].right_edge_pb_reg_n_0_[25] ), .I1(\left_edge_ref_reg[5]_i_3_n_4 ), .I2(\genblk8[6].right_edge_pb_reg_n_0_[41] ), .I3(\left_edge_ref_reg[5]_i_6_n_7 ), .I4(\genblk8[1].right_edge_pb_reg_n_0_[9] ), .O(\right_edge_ref[5]_i_9_n_0 )); FDRE \right_edge_ref_reg[0] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[0]_i_1_n_0 ), .Q(right_edge_ref[0]), .R(1'b0)); FDRE \right_edge_ref_reg[1] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[1]_i_1_n_0 ), .Q(right_edge_ref[1]), .R(1'b0)); FDRE \right_edge_ref_reg[2] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[2]_i_1_n_0 ), .Q(right_edge_ref[2]), .R(1'b0)); FDRE \right_edge_ref_reg[3] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[3]_i_1_n_0 ), .Q(right_edge_ref[3]), .R(1'b0)); FDRE \right_edge_ref_reg[4] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[4]_i_1_n_0 ), .Q(right_edge_ref[4]), .R(1'b0)); MUXF7 \right_edge_ref_reg[4]_i_10 (.I0(\right_edge_ref[4]_i_11_n_0 ), .I1(\right_edge_ref[4]_i_12_n_0 ), .O(\right_edge_ref_reg[4]_i_10_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); MUXF7 \right_edge_ref_reg[4]_i_3 (.I0(\right_edge_ref[4]_i_6_n_0 ), .I1(\right_edge_ref[4]_i_7_n_0 ), .O(\right_edge_ref_reg[4]_i_3_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); FDRE \right_edge_ref_reg[5] (.C(CLK), .CE(1'b1), .D(\right_edge_ref[5]_i_1_n_0 ), .Q(right_edge_ref[5]), .R(1'b0)); MUXF7 \right_edge_ref_reg[5]_i_10 (.I0(\right_edge_ref[5]_i_11_n_0 ), .I1(\right_edge_ref[5]_i_12_n_0 ), .O(\right_edge_ref_reg[5]_i_10_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); MUXF7 \right_edge_ref_reg[5]_i_3 (.I0(\right_edge_ref[5]_i_6_n_0 ), .I1(\right_edge_ref[5]_i_7_n_0 ), .O(\right_edge_ref_reg[5]_i_3_n_0 ), .S(\left_edge_ref_reg[5]_i_3_n_5 )); LUT6 #( .INIT(64'h00000000FFFFFFFE)) \samples_cnt_r[0]_i_1 (.I0(\samples_cnt_r_reg_n_0_[11] ), .I1(\samples_cnt_r_reg_n_0_[10] ), .I2(\samples_cnt_r_reg_n_0_[1] ), .I3(\samples_cnt_r[0]_i_2_n_0 ), .I4(\samples_cnt_r[0]_i_3_n_0 ), .I5(\samples_cnt_r_reg_n_0_[0] ), .O(\samples_cnt_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'hFFFE)) \samples_cnt_r[0]_i_2 (.I0(\samples_cnt_r_reg_n_0_[7] ), .I1(\samples_cnt_r_reg_n_0_[6] ), .I2(\samples_cnt_r_reg_n_0_[9] ), .I3(\samples_cnt_r_reg_n_0_[8] ), .O(\samples_cnt_r[0]_i_2_n_0 )); LUT4 #( .INIT(16'hFFF7)) \samples_cnt_r[0]_i_3 (.I0(\samples_cnt_r_reg_n_0_[3] ), .I1(\samples_cnt_r_reg_n_0_[2] ), .I2(\samples_cnt_r_reg_n_0_[5] ), .I3(\samples_cnt_r_reg_n_0_[4] ), .O(\samples_cnt_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[10]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[10]), .O(\samples_cnt_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[11]_i_2 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[11]), .O(\samples_cnt_r[11]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \samples_cnt_r[11]_i_3 (.I0(\samples_cnt_r_reg_n_0_[11] ), .I1(\samples_cnt_r_reg_n_0_[10] ), .I2(\samples_cnt_r_reg_n_0_[1] ), .I3(\samples_cnt_r[0]_i_2_n_0 ), .I4(\samples_cnt_r[0]_i_3_n_0 ), .I5(\samples_cnt_r_reg_n_0_[0] ), .O(\rd_victim_sel_reg[2]_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[11]_i_5 (.I0(\samples_cnt_r_reg_n_0_[11] ), .O(\samples_cnt_r[11]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[11]_i_6 (.I0(\samples_cnt_r_reg_n_0_[10] ), .O(\samples_cnt_r[11]_i_6_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[11]_i_7 (.I0(\samples_cnt_r_reg_n_0_[9] ), .O(\samples_cnt_r[11]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[1]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[1]), .O(\samples_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[2]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[2]), .O(\samples_cnt_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[3]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[3]), .O(\samples_cnt_r[3]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \samples_cnt_r[4]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[4]), .O(\samples_cnt_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_3 (.I0(\samples_cnt_r_reg_n_0_[4] ), .O(\samples_cnt_r[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_4 (.I0(\samples_cnt_r_reg_n_0_[3] ), .O(\samples_cnt_r[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_5 (.I0(\samples_cnt_r_reg_n_0_[2] ), .O(\samples_cnt_r[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[4]_i_6 (.I0(\samples_cnt_r_reg_n_0_[1] ), .O(\samples_cnt_r[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[5]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[5]), .O(\samples_cnt_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[6]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[6]), .O(\samples_cnt_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[7]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[7]), .O(\samples_cnt_r[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[8]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[8]), .O(\samples_cnt_r[8]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_3 (.I0(\samples_cnt_r_reg_n_0_[8] ), .O(\samples_cnt_r[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_4 (.I0(\samples_cnt_r_reg_n_0_[7] ), .O(\samples_cnt_r[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_5 (.I0(\samples_cnt_r_reg_n_0_[6] ), .O(\samples_cnt_r[8]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samples_cnt_r[8]_i_6 (.I0(\samples_cnt_r_reg_n_0_[5] ), .O(\samples_cnt_r[8]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'h8)) \samples_cnt_r[9]_i_1 (.I0(\rd_victim_sel_reg[2]_0 ), .I1(data0[9]), .O(\samples_cnt_r[9]_i_1_n_0 )); FDRE \samples_cnt_r_reg[0] (.C(CLK), .CE(E), .D(\samples_cnt_r[0]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[10] (.C(CLK), .CE(E), .D(\samples_cnt_r[10]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[10] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[11] (.C(CLK), .CE(E), .D(\samples_cnt_r[11]_i_2_n_0 ), .Q(\samples_cnt_r_reg_n_0_[11] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \samples_cnt_r_reg[11]_i_4 (.CI(\samples_cnt_r_reg[8]_i_2_n_0 ), .CO({\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED [3:2],\samples_cnt_r_reg[11]_i_4_n_2 ,\samples_cnt_r_reg[11]_i_4_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}), .S({1'b0,\samples_cnt_r[11]_i_5_n_0 ,\samples_cnt_r[11]_i_6_n_0 ,\samples_cnt_r[11]_i_7_n_0 })); FDRE \samples_cnt_r_reg[1] (.C(CLK), .CE(E), .D(\samples_cnt_r[1]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[2] (.C(CLK), .CE(E), .D(\samples_cnt_r[2]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[3] (.C(CLK), .CE(E), .D(\samples_cnt_r[3]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[4] (.C(CLK), .CE(E), .D(\samples_cnt_r[4]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \samples_cnt_r_reg[4]_i_2 (.CI(1'b0), .CO({\samples_cnt_r_reg[4]_i_2_n_0 ,\samples_cnt_r_reg[4]_i_2_n_1 ,\samples_cnt_r_reg[4]_i_2_n_2 ,\samples_cnt_r_reg[4]_i_2_n_3 }), .CYINIT(\samples_cnt_r_reg_n_0_[0] ), .DI({1'b0,1'b0,1'b0,1'b0}), .O(data0[4:1]), .S({\samples_cnt_r[4]_i_3_n_0 ,\samples_cnt_r[4]_i_4_n_0 ,\samples_cnt_r[4]_i_5_n_0 ,\samples_cnt_r[4]_i_6_n_0 })); FDRE \samples_cnt_r_reg[5] (.C(CLK), .CE(E), .D(\samples_cnt_r[5]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[6] (.C(CLK), .CE(E), .D(\samples_cnt_r[6]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[7] (.C(CLK), .CE(E), .D(\samples_cnt_r[7]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__8)); FDRE \samples_cnt_r_reg[8] (.C(CLK), .CE(E), .D(\samples_cnt_r[8]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__8)); CARRY4 \samples_cnt_r_reg[8]_i_2 (.CI(\samples_cnt_r_reg[4]_i_2_n_0 ), .CO({\samples_cnt_r_reg[8]_i_2_n_0 ,\samples_cnt_r_reg[8]_i_2_n_1 ,\samples_cnt_r_reg[8]_i_2_n_2 ,\samples_cnt_r_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(data0[8:5]), .S({\samples_cnt_r[8]_i_3_n_0 ,\samples_cnt_r[8]_i_4_n_0 ,\samples_cnt_r[8]_i_5_n_0 ,\samples_cnt_r[8]_i_6_n_0 })); FDRE \samples_cnt_r_reg[9] (.C(CLK), .CE(E), .D(\samples_cnt_r[9]_i_1_n_0 ), .Q(\samples_cnt_r_reg_n_0_[9] ), .R(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'h7)) \smallest_right_edge[0]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\smallest_right_edge[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'hD7)) \smallest_right_edge[1]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .O(\smallest_right_edge[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT4 #( .INIT(16'hDDD7)) \smallest_right_edge[2]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I2(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .O(\smallest_right_edge[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT5 #( .INIT(32'hDDDDDDD7)) \smallest_right_edge[3]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .I2(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .O(\smallest_right_edge[3]_i_1_n_0 )); LUT6 #( .INIT(64'hDDDDDDDDDDDDDDD7)) \smallest_right_edge[4]_i_1 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ), .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ), .I3(\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ), .I4(\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ), .I5(\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ), .O(\smallest_right_edge[4]_i_1_n_0 )); LUT6 #( .INIT(64'h8000800000080308)) \smallest_right_edge[5]_i_1 (.I0(\smallest_right_edge[5]_i_3_n_0 ), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .I5(Q[1]), .O(smallest_right_edge)); LUT2 #( .INIT(4'h7)) \smallest_right_edge[5]_i_2 (.I0(Q[0]), .I1(\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ), .O(\smallest_right_edge[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0F40004000400040)) \smallest_right_edge[5]_i_3 (.I0(no_err_win_detected_latch_reg_0), .I1(right_edge_found_reg_1), .I2(Q[3]), .I3(Q[4]), .I4(\smallest_right_edge[5]_i_4_n_0 ), .I5(prbs_state_r1), .O(\smallest_right_edge[5]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \smallest_right_edge[5]_i_4 (.I0(num_samples_done_r), .I1(right_edge_found_reg_0), .O(\smallest_right_edge[5]_i_4_n_0 )); FDSE \smallest_right_edge_reg[0] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[0]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[0] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE \smallest_right_edge_reg[1] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[1]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[1] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE \smallest_right_edge_reg[2] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[2]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[2] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE \smallest_right_edge_reg[3] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[3]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[3] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE \smallest_right_edge_reg[4] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[4]_i_1_n_0 ), .Q(\smallest_right_edge_reg_n_0_[4] ), .S(rstdiv0_sync_r1_reg_rep__8)); FDSE \smallest_right_edge_reg[5] (.C(CLK), .CE(smallest_right_edge), .D(\smallest_right_edge[5]_i_2_n_0 ), .Q(\smallest_right_edge_reg_n_0_[5] ), .S(rstdiv0_sync_r1_reg_rep__8)); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'h38)) \stage_cnt[0]_i_1 (.I0(Q[4]), .I1(\stage_cnt[1]_i_2_n_0 ), .I2(\stage_cnt_reg_n_0_[0] ), .O(\stage_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h2F80)) \stage_cnt[1]_i_1 (.I0(Q[4]), .I1(\stage_cnt_reg_n_0_[0] ), .I2(\stage_cnt[1]_i_2_n_0 ), .I3(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .O(\stage_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000202020002)) \stage_cnt[1]_i_2 (.I0(Q[0]), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(Q[1]), .I5(fine_delay_sel_reg_0), .O(\stage_cnt[1]_i_2_n_0 )); FDRE \stage_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\stage_cnt[0]_i_1_n_0 ), .Q(\stage_cnt_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \stage_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\stage_cnt[1]_i_1_n_0 ), .Q(\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__7)); LUT6 #( .INIT(64'h00000000AAAAEAAA)) \victim_not_fixed.num_samples_done_r_i_1 (.I0(num_samples_done_r), .I1(\rd_victim_sel_reg[2]_3 ), .I2(\rd_victim_sel_reg[2]_2 ), .I3(\rd_victim_sel_reg[2]_1 ), .I4(\rd_victim_sel_reg[2]_0 ), .I5(\victim_not_fixed.num_samples_done_r_i_2_n_0 ), .O(\victim_not_fixed.num_samples_done_r_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAEBEEAAAAAAAA)) \victim_not_fixed.num_samples_done_r_i_2 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(Q[2]), .I2(Q[3]), .I3(Q[1]), .I4(Q[4]), .I5(Q[0]), .O(\victim_not_fixed.num_samples_done_r_i_2_n_0 )); FDRE \victim_not_fixed.num_samples_done_r_reg (.C(CLK), .CE(1'b1), .D(\victim_not_fixed.num_samples_done_r_i_1_n_0 ), .Q(num_samples_done_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( .INIT(32'h00050A12)) wait_state_cnt_en_r_i_1 (.I0(Q[2]), .I1(Q[3]), .I2(Q[4]), .I3(Q[1]), .I4(Q[0]), .O(wait_state_cnt_en_r0)); FDRE wait_state_cnt_en_r_reg (.C(CLK), .CE(1'b1), .D(wait_state_cnt_en_r0), .Q(wait_state_cnt_en_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT1 #( .INIT(2'h1)) \wait_state_cnt_r[0]_i_1 (.I0(wait_state_cnt_r_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h6)) \wait_state_cnt_r[1]_i_1 (.I0(wait_state_cnt_r_reg__0[0]), .I1(wait_state_cnt_r_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'h78)) \wait_state_cnt_r[2]_i_1 (.I0(wait_state_cnt_r_reg__0[1]), .I1(wait_state_cnt_r_reg__0[0]), .I2(wait_state_cnt_r_reg__0[2]), .O(\wait_state_cnt_r[2]_i_1_n_0 )); LUT5 #( .INIT(32'hD5555555)) \wait_state_cnt_r[3]_i_1 (.I0(wait_state_cnt_en_r), .I1(wait_state_cnt_r_reg__0[3]), .I2(wait_state_cnt_r_reg__0[2]), .I3(wait_state_cnt_r_reg__0[0]), .I4(wait_state_cnt_r_reg__0[1]), .O(\wait_state_cnt_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT4 #( .INIT(16'h7F80)) \wait_state_cnt_r[3]_i_2 (.I0(wait_state_cnt_r_reg__0[0]), .I1(wait_state_cnt_r_reg__0[1]), .I2(wait_state_cnt_r_reg__0[2]), .I3(wait_state_cnt_r_reg__0[3]), .O(p_0_in[3])); FDRE \wait_state_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in[0]), .Q(wait_state_cnt_r_reg__0[0]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); FDRE \wait_state_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in[1]), .Q(wait_state_cnt_r_reg__0[1]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); FDRE \wait_state_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wait_state_cnt_r[2]_i_1_n_0 ), .Q(wait_state_cnt_r_reg__0[2]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); FDRE \wait_state_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in[3]), .Q(wait_state_cnt_r_reg__0[3]), .R(\wait_state_cnt_r[3]_i_1_n_0 )); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_rdlvl (mpr_rdlvl_done_r1_reg_0, store_sr_r_reg_0, sr_valid_r1_reg_0, found_stable_eye_last_r_reg_0, found_first_edge_r_reg_0, mpr_rdlvl_start_r, mpr_valid_r1_reg_0, detect_edge_done_r, samp_edge_cnt0_en_r, \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 , p_0_in102_in, p_0_in99_in, p_0_in96_in, p_0_in93_in, p_0_in90_in, p_0_in87_in, p_0_in84_in, idelay_ce_int, idelay_inc_int, dqs_po_dec_done_r2, rdlvl_prech_req, pi_fine_dly_dec_done, pb_detect_edge_done_r, \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 , \gen_track_left_edge[0].pb_found_stable_eye_r_reg , \gen_track_left_edge[1].pb_found_stable_eye_r_reg , \gen_track_left_edge[2].pb_found_stable_eye_r_reg , \gen_track_left_edge[3].pb_found_stable_eye_r_reg , \gen_track_left_edge[4].pb_found_stable_eye_r_reg , \gen_track_left_edge[5].pb_found_stable_eye_r_reg , \gen_track_left_edge[6].pb_found_stable_eye_r_reg , \gen_track_left_edge[7].pb_found_stable_eye_r_reg , \gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 , found_edge_r_reg_0, found_edge_r_reg_1, found_edge_r_reg_2, \gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 , found_edge_r_reg_3, \gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 , \gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 , \right_edge_taps_r_reg[0]_0 , cal1_wait_r, found_stable_eye_last_r, mpr_rd_rise0_prev_r_reg_0, mpr_dec_cpt_r_reg_0, idel_adj_inc_reg_0, pi_en_stg2_f_timing_reg_0, mpr_last_byte_done, mpr_rnk_done, rdlvl_stg1_done_r1_reg, rdlvl_stg1_rank_done, rdlvl_last_byte_done, rdlvl_pi_incdec, \cnt_idel_dec_cpt_r_reg[0]_0 , \pi_dqs_found_lanes_r1_reg[3] , \pi_dqs_found_lanes_r1_reg[3]_0 , \pi_dqs_found_lanes_r1_reg[3]_1 , \pi_dqs_found_lanes_r1_reg[2] , \pi_dqs_found_lanes_r1_reg[2]_0 , \pi_dqs_found_lanes_r1_reg[2]_1 , \pi_dqs_found_lanes_r1_reg[1] , \pi_dqs_found_lanes_r1_reg[1]_0 , \pi_dqs_found_lanes_r1_reg[1]_1 , COUNTERLOADVAL, \pi_dqs_found_lanes_r1_reg[0] , \pi_dqs_found_lanes_r1_reg[0]_0 , \pi_dqs_found_lanes_r1_reg[0]_1 , \stg1_wr_rd_cnt_reg[3] , \init_state_r_reg[0] , \init_state_r_reg[0]_0 , \init_state_r_reg[0]_1 , out, idel_adj_inc_reg_1, \wait_cnt_r_reg[0]_0 , \right_edge_taps_r_reg[0]_1 , store_sr_req_r_reg_0, \rdlvl_cpt_tap_cnt_reg[4] , \rdlvl_cpt_tap_cnt_reg[1] , \rdlvl_cpt_tap_cnt_reg[2] , \pi_rdval_cnt_reg[1]_0 , \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 , \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 , \pi_stg2_reg_l_timing_reg[0]_0 , \regl_dqs_cnt_r_reg[2]_0 , \regl_dqs_cnt_reg[0]_0 , mpr_rd_rise0_prev_r_reg_1, \rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 , cal1_cnt_cpt_r1, mpr_valid_r_reg_0, \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 , \gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 , p_0_in16_in, \gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 , p_0_in13_in, \gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 , p_0_in10_in, \gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 , p_0_in7_in, \gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 , p_0_in4_in, \gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 , p_0_in1_in, \gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 , p_0_in, \gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 , pb_found_stable_eye_r76_out, \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 , pb_found_stable_eye_r72_out, \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 , pb_found_stable_eye_r68_out, \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 , pb_found_stable_eye_r64_out, \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 , pb_found_stable_eye_r60_out, \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 , pb_found_stable_eye_r56_out, \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 , pb_found_stable_eye_r52_out, \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 , \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 , \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 , \right_edge_taps_r_reg[0]_2 , idel_adj_inc_reg_2, pi_cnt_dec_reg_0, \init_state_r_reg[1] , prech_req, \init_state_r_reg[2] , \init_state_r_reg[2]_0 , \init_state_r_reg[2]_1 , \init_state_r_reg[5] , \init_state_r_reg[0]_2 , \init_state_r_reg[3] , \init_state_r_reg[0]_3 , \init_state_r_reg[4] , \init_state_r_reg[0]_4 , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] , \init_state_r_reg[2]_2 , D, \gen_byte_sel_div1.calib_in_common_reg , \gen_byte_sel_div1.byte_sel_cnt_reg[2] , \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 , cmd_delay_start0, \second_edge_taps_r_reg[5]_0 , \pi_dqs_found_lanes_r1_reg[1]_2 , \pi_dqs_found_lanes_r1_reg[2]_2 , \pi_dqs_found_lanes_r1_reg[3]_2 , rdlvl_pi_incdec_reg_0, pi_stg2_rdlvl_cnt, mpr_last_byte_done_reg_0, mpr_rank_done_r_reg_0, rdlvl_pi_incdec_reg_1, \idel_dec_cnt_reg[0]_0 , rdlvl_stg1_done_int, rdlvl_rank_done_r_reg_0, mpr_rank_done_r_reg_1, mpr_dec_cpt_r_reg_1, CLK, rstdiv0_sync_r1_reg_rep__14, sr_valid_r108_out, \rd_mux_sel_r_reg[1]_0 , \rd_mux_sel_r_reg[1]_1 , \rd_mux_sel_r_reg[1]_2 , \rd_mux_sel_r_reg[1]_3 , \rd_mux_sel_r_reg[1]_4 , \rd_mux_sel_r_reg[1]_5 , \rd_mux_sel_r_reg[1]_6 , \rd_mux_sel_r_reg[1]_7 , \rd_mux_sel_r_reg[1]_8 , \rd_mux_sel_r_reg[1]_9 , \rd_mux_sel_r_reg[1]_10 , \rd_mux_sel_r_reg[1]_11 , \rd_mux_sel_r_reg[1]_12 , \rd_mux_sel_r_reg[1]_13 , \rd_mux_sel_r_reg[1]_14 , \rd_mux_sel_r_reg[1]_15 , \rd_mux_sel_r_reg[1]_16 , \rd_mux_sel_r_reg[1]_17 , \rd_mux_sel_r_reg[1]_18 , \rd_mux_sel_r_reg[1]_19 , \rd_mux_sel_r_reg[1]_20 , \rd_mux_sel_r_reg[1]_21 , \rd_mux_sel_r_reg[1]_22 , \rd_mux_sel_r_reg[1]_23 , \rd_mux_sel_r_reg[1]_24 , \rd_mux_sel_r_reg[1]_25 , \rd_mux_sel_r_reg[1]_26 , \rd_mux_sel_r_reg[1]_27 , \rd_mux_sel_r_reg[1]_28 , \rd_mux_sel_r_reg[1]_29 , \rd_mux_sel_r_reg[1]_30 , \rd_mux_sel_r_reg[1]_31 , \rd_mux_sel_r_reg[1]_32 , \rd_mux_sel_r_reg[1]_33 , \rd_mux_sel_r_reg[1]_34 , \rd_mux_sel_r_reg[1]_35 , \rd_mux_sel_r_reg[1]_36 , \rd_mux_sel_r_reg[1]_37 , \rd_mux_sel_r_reg[1]_38 , \rd_mux_sel_r_reg[1]_39 , \rd_mux_sel_r_reg[1]_40 , \rd_mux_sel_r_reg[1]_41 , \rd_mux_sel_r_reg[1]_42 , \rd_mux_sel_r_reg[1]_43 , \rd_mux_sel_r_reg[1]_44 , \rd_mux_sel_r_reg[1]_45 , \rd_mux_sel_r_reg[1]_46 , \rd_mux_sel_r_reg[1]_47 , \rd_mux_sel_r_reg[1]_48 , \rd_mux_sel_r_reg[1]_49 , \rd_mux_sel_r_reg[1]_50 , \rd_mux_sel_r_reg[1]_51 , \rd_mux_sel_r_reg[1]_52 , \rd_mux_sel_r_reg[1]_53 , \rd_mux_sel_r_reg[1]_54 , \rd_mux_sel_r_reg[1]_55 , \rd_mux_sel_r_reg[1]_56 , \rd_mux_sel_r_reg[1]_57 , \rd_mux_sel_r_reg[1]_58 , \rd_mux_sel_r_reg[1]_59 , \rd_mux_sel_r_reg[1]_60 , \rd_mux_sel_r_reg[1]_61 , \rd_mux_sel_r_reg[1]_62 , \rd_mux_sel_r_reg[1]_63 , mpr_rdlvl_start_reg, rdlvl_stg1_start_reg, phy_rddata_en_1, dqs_po_dec_done, rstdiv0_sync_r1_reg_rep__13, samp_cnt_done_r_reg_0, samp_cnt_done_r_reg_1, samp_cnt_done_r_reg_2, samp_cnt_done_r_reg_3, samp_cnt_done_r_reg_4, samp_cnt_done_r_reg_5, samp_cnt_done_r_reg_6, \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 , mpr_rdlvl_done_r_reg_0, store_sr_req_r_reg_1, \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 , \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 , \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 , \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 , \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 , \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 , \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 , \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 , \gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 , \gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 , \gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 , \gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 , \gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 , \gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 , \gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 , \gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 , found_edge_r_reg_4, found_stable_eye_r_reg_0, \FSM_sequential_cal1_state_r_reg[4]_0 , \FSM_sequential_cal1_state_r_reg[3]_0 , \FSM_sequential_cal1_state_r_reg[2]_0 , \wait_cnt_r_reg[0]_1 , \FSM_sequential_cal1_state_r_reg[4]_1 , \FSM_sequential_cal1_state_r_reg[4]_2 , mpr_rdlvl_done_r_reg_1, \FSM_sequential_cal1_state_r_reg[4]_3 , \FSM_sequential_cal1_state_r_reg[4]_4 , \regl_dqs_cnt_reg[2]_0 , \FSM_sequential_cal1_state_r_reg[1]_0 , SR, found_stable_eye_last_r_reg_1, \gen_byte_sel_div1.calib_in_common_reg_0 , prbs_pi_stg2_f_incdec, tempmon_pi_f_inc_r, Q, prbs_pi_stg2_f_en, tempmon_pi_f_en_r, calib_in_common, \calib_sel_reg[3] , \gen_byte_sel_div1.calib_in_common_reg_1 , \gen_byte_sel_div1.calib_in_common_reg_2 , \gen_byte_sel_div1.calib_in_common_reg_3 , rstdiv0_sync_r1_reg_rep__24, stg1_wr_done, wrcal_done_reg, dqs_found_done_r_reg, \init_state_r_reg[1]_0 , oclkdelay_calib_done_r_reg, \one_rank.stg1_wr_done_reg , cal1_state_r1535_out, rstdiv0_sync_r1_reg_rep__23, \calib_sel_reg[3]_0 , \po_stg2_wrcal_cnt_reg[0] , \po_stg2_wrcal_cnt_reg[1] , cal1_dq_idel_ce_reg_0, prech_done, \pi_counter_read_val_reg[5] , rstdiv0_sync_r1_reg_rep__20, \init_state_r_reg[3]_0 , wrcal_prech_req, complex_ocal_ref_req, prbs_rdlvl_prech_req_reg, dqs_found_prech_req, \init_state_r_reg[5]_0 , wrlvl_done_r1_reg, wrlvl_done_r1_reg_0, cnt_init_af_done_r, dqs_found_done_r_reg_0, prbs_rdlvl_done_reg_rep, wrlvl_byte_redo, wrlvl_final_mux, mem_init_done_r, prbs_rdlvl_done_reg_rep_0, \num_refresh_reg[1] , prbs_last_byte_done_r, wrlvl_final_mux_reg, prbs_rdlvl_done_reg_rep_1, oclkdelay_center_calib_done_r_reg, wrlvl_done_r1, wrlvl_byte_redo_reg, \dout_o_reg[6] , first_wrcal_pat_r, \dout_o_reg[6]_0 , prbs_rdlvl_done_reg, wr_level_done_reg, \prbs_dqs_cnt_r_reg[2] , \po_stg2_wrcal_cnt_reg[2] , rdlvl_stg1_start_reg_0, E, samp_edge_cnt0_en_r_reg_0, pi_cnt_dec_reg_1, rstdiv0_sync_r1_reg_rep__2); output mpr_rdlvl_done_r1_reg_0; output store_sr_r_reg_0; output sr_valid_r1_reg_0; output found_stable_eye_last_r_reg_0; output found_first_edge_r_reg_0; output mpr_rdlvl_start_r; output mpr_valid_r1_reg_0; output detect_edge_done_r; output samp_edge_cnt0_en_r; output \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ; output p_0_in102_in; output p_0_in99_in; output p_0_in96_in; output p_0_in93_in; output p_0_in90_in; output p_0_in87_in; output p_0_in84_in; output idelay_ce_int; output idelay_inc_int; output dqs_po_dec_done_r2; output rdlvl_prech_req; output pi_fine_dly_dec_done; output [7:0]pb_detect_edge_done_r; output \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ; output \gen_track_left_edge[0].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[1].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[2].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[3].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[4].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[5].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[6].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[7].pb_found_stable_eye_r_reg ; output \gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ; output found_edge_r_reg_0; output found_edge_r_reg_1; output found_edge_r_reg_2; output \gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ; output found_edge_r_reg_3; output \gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ; output \gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ; output \right_edge_taps_r_reg[0]_0 ; output cal1_wait_r; output found_stable_eye_last_r; output mpr_rd_rise0_prev_r_reg_0; output mpr_dec_cpt_r_reg_0; output idel_adj_inc_reg_0; output pi_en_stg2_f_timing_reg_0; output mpr_last_byte_done; output mpr_rnk_done; output rdlvl_stg1_done_r1_reg; output rdlvl_stg1_rank_done; output rdlvl_last_byte_done; output rdlvl_pi_incdec; output \cnt_idel_dec_cpt_r_reg[0]_0 ; output \pi_dqs_found_lanes_r1_reg[3] ; output \pi_dqs_found_lanes_r1_reg[3]_0 ; output \pi_dqs_found_lanes_r1_reg[3]_1 ; output \pi_dqs_found_lanes_r1_reg[2] ; output \pi_dqs_found_lanes_r1_reg[2]_0 ; output \pi_dqs_found_lanes_r1_reg[2]_1 ; output \pi_dqs_found_lanes_r1_reg[1] ; output \pi_dqs_found_lanes_r1_reg[1]_0 ; output \pi_dqs_found_lanes_r1_reg[1]_1 ; output [5:0]COUNTERLOADVAL; output \pi_dqs_found_lanes_r1_reg[0] ; output \pi_dqs_found_lanes_r1_reg[0]_0 ; output \pi_dqs_found_lanes_r1_reg[0]_1 ; output \stg1_wr_rd_cnt_reg[3] ; output \init_state_r_reg[0] ; output \init_state_r_reg[0]_0 ; output \init_state_r_reg[0]_1 ; output [4:0]out; output idel_adj_inc_reg_1; output [1:0]\wait_cnt_r_reg[0]_0 ; output \right_edge_taps_r_reg[0]_1 ; output store_sr_req_r_reg_0; output \rdlvl_cpt_tap_cnt_reg[4] ; output \rdlvl_cpt_tap_cnt_reg[1] ; output \rdlvl_cpt_tap_cnt_reg[2] ; output \pi_rdval_cnt_reg[1]_0 ; output \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ; output \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ; output \pi_stg2_reg_l_timing_reg[0]_0 ; output [0:0]\regl_dqs_cnt_r_reg[2]_0 ; output \regl_dqs_cnt_reg[0]_0 ; output mpr_rd_rise0_prev_r_reg_1; output [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ; output cal1_cnt_cpt_r1; output mpr_valid_r_reg_0; output \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ; output \gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ; output p_0_in16_in; output \gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ; output p_0_in13_in; output \gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ; output p_0_in10_in; output \gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ; output p_0_in7_in; output \gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ; output p_0_in4_in; output \gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ; output p_0_in1_in; output \gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ; output p_0_in; output \gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ; output pb_found_stable_eye_r76_out; output \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ; output pb_found_stable_eye_r72_out; output \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ; output pb_found_stable_eye_r68_out; output \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ; output pb_found_stable_eye_r64_out; output \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ; output pb_found_stable_eye_r60_out; output \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ; output pb_found_stable_eye_r56_out; output \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ; output pb_found_stable_eye_r52_out; output \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ; output \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ; output \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ; output \right_edge_taps_r_reg[0]_2 ; output idel_adj_inc_reg_2; output pi_cnt_dec_reg_0; output \init_state_r_reg[1] ; output prech_req; output \init_state_r_reg[2] ; output \init_state_r_reg[2]_0 ; output \init_state_r_reg[2]_1 ; output \init_state_r_reg[5] ; output \init_state_r_reg[0]_2 ; output \init_state_r_reg[3] ; output \init_state_r_reg[0]_3 ; output \init_state_r_reg[4] ; output \init_state_r_reg[0]_4 ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ; output \init_state_r_reg[2]_2 ; output [1:0]D; output \gen_byte_sel_div1.calib_in_common_reg ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; output cmd_delay_start0; output \second_edge_taps_r_reg[5]_0 ; output [5:0]\pi_dqs_found_lanes_r1_reg[1]_2 ; output [5:0]\pi_dqs_found_lanes_r1_reg[2]_2 ; output [5:0]\pi_dqs_found_lanes_r1_reg[3]_2 ; output rdlvl_pi_incdec_reg_0; output [1:0]pi_stg2_rdlvl_cnt; output mpr_last_byte_done_reg_0; output mpr_rank_done_r_reg_0; output rdlvl_pi_incdec_reg_1; output \idel_dec_cnt_reg[0]_0 ; output rdlvl_stg1_done_int; output rdlvl_rank_done_r_reg_0; output mpr_rank_done_r_reg_1; output mpr_dec_cpt_r_reg_1; input CLK; input [1:0]rstdiv0_sync_r1_reg_rep__14; input sr_valid_r108_out; input \rd_mux_sel_r_reg[1]_0 ; input \rd_mux_sel_r_reg[1]_1 ; input \rd_mux_sel_r_reg[1]_2 ; input \rd_mux_sel_r_reg[1]_3 ; input \rd_mux_sel_r_reg[1]_4 ; input \rd_mux_sel_r_reg[1]_5 ; input \rd_mux_sel_r_reg[1]_6 ; input \rd_mux_sel_r_reg[1]_7 ; input \rd_mux_sel_r_reg[1]_8 ; input \rd_mux_sel_r_reg[1]_9 ; input \rd_mux_sel_r_reg[1]_10 ; input \rd_mux_sel_r_reg[1]_11 ; input \rd_mux_sel_r_reg[1]_12 ; input \rd_mux_sel_r_reg[1]_13 ; input \rd_mux_sel_r_reg[1]_14 ; input \rd_mux_sel_r_reg[1]_15 ; input \rd_mux_sel_r_reg[1]_16 ; input \rd_mux_sel_r_reg[1]_17 ; input \rd_mux_sel_r_reg[1]_18 ; input \rd_mux_sel_r_reg[1]_19 ; input \rd_mux_sel_r_reg[1]_20 ; input \rd_mux_sel_r_reg[1]_21 ; input \rd_mux_sel_r_reg[1]_22 ; input \rd_mux_sel_r_reg[1]_23 ; input \rd_mux_sel_r_reg[1]_24 ; input \rd_mux_sel_r_reg[1]_25 ; input \rd_mux_sel_r_reg[1]_26 ; input \rd_mux_sel_r_reg[1]_27 ; input \rd_mux_sel_r_reg[1]_28 ; input \rd_mux_sel_r_reg[1]_29 ; input \rd_mux_sel_r_reg[1]_30 ; input \rd_mux_sel_r_reg[1]_31 ; input \rd_mux_sel_r_reg[1]_32 ; input \rd_mux_sel_r_reg[1]_33 ; input \rd_mux_sel_r_reg[1]_34 ; input \rd_mux_sel_r_reg[1]_35 ; input \rd_mux_sel_r_reg[1]_36 ; input \rd_mux_sel_r_reg[1]_37 ; input \rd_mux_sel_r_reg[1]_38 ; input \rd_mux_sel_r_reg[1]_39 ; input \rd_mux_sel_r_reg[1]_40 ; input \rd_mux_sel_r_reg[1]_41 ; input \rd_mux_sel_r_reg[1]_42 ; input \rd_mux_sel_r_reg[1]_43 ; input \rd_mux_sel_r_reg[1]_44 ; input \rd_mux_sel_r_reg[1]_45 ; input \rd_mux_sel_r_reg[1]_46 ; input \rd_mux_sel_r_reg[1]_47 ; input \rd_mux_sel_r_reg[1]_48 ; input \rd_mux_sel_r_reg[1]_49 ; input \rd_mux_sel_r_reg[1]_50 ; input \rd_mux_sel_r_reg[1]_51 ; input \rd_mux_sel_r_reg[1]_52 ; input \rd_mux_sel_r_reg[1]_53 ; input \rd_mux_sel_r_reg[1]_54 ; input \rd_mux_sel_r_reg[1]_55 ; input \rd_mux_sel_r_reg[1]_56 ; input \rd_mux_sel_r_reg[1]_57 ; input \rd_mux_sel_r_reg[1]_58 ; input \rd_mux_sel_r_reg[1]_59 ; input \rd_mux_sel_r_reg[1]_60 ; input \rd_mux_sel_r_reg[1]_61 ; input \rd_mux_sel_r_reg[1]_62 ; input \rd_mux_sel_r_reg[1]_63 ; input mpr_rdlvl_start_reg; input rdlvl_stg1_start_reg; input phy_rddata_en_1; input dqs_po_dec_done; input rstdiv0_sync_r1_reg_rep__13; input samp_cnt_done_r_reg_0; input samp_cnt_done_r_reg_1; input samp_cnt_done_r_reg_2; input samp_cnt_done_r_reg_3; input samp_cnt_done_r_reg_4; input samp_cnt_done_r_reg_5; input samp_cnt_done_r_reg_6; input \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ; input mpr_rdlvl_done_r_reg_0; input store_sr_req_r_reg_1; input \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ; input \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ; input \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ; input \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ; input \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ; input \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ; input \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ; input \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ; input \gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ; input \gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ; input \gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ; input \gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ; input \gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ; input \gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ; input \gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ; input \gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ; input found_edge_r_reg_4; input found_stable_eye_r_reg_0; input \FSM_sequential_cal1_state_r_reg[4]_0 ; input \FSM_sequential_cal1_state_r_reg[3]_0 ; input \FSM_sequential_cal1_state_r_reg[2]_0 ; input \wait_cnt_r_reg[0]_1 ; input \FSM_sequential_cal1_state_r_reg[4]_1 ; input \FSM_sequential_cal1_state_r_reg[4]_2 ; input mpr_rdlvl_done_r_reg_1; input \FSM_sequential_cal1_state_r_reg[4]_3 ; input \FSM_sequential_cal1_state_r_reg[4]_4 ; input \regl_dqs_cnt_reg[2]_0 ; input \FSM_sequential_cal1_state_r_reg[1]_0 ; input [0:0]SR; input found_stable_eye_last_r_reg_1; input \gen_byte_sel_div1.calib_in_common_reg_0 ; input prbs_pi_stg2_f_incdec; input tempmon_pi_f_inc_r; input [0:0]Q; input prbs_pi_stg2_f_en; input tempmon_pi_f_en_r; input calib_in_common; input [2:0]\calib_sel_reg[3] ; input \gen_byte_sel_div1.calib_in_common_reg_1 ; input \gen_byte_sel_div1.calib_in_common_reg_2 ; input \gen_byte_sel_div1.calib_in_common_reg_3 ; input rstdiv0_sync_r1_reg_rep__24; input stg1_wr_done; input wrcal_done_reg; input dqs_found_done_r_reg; input [1:0]\init_state_r_reg[1]_0 ; input oclkdelay_calib_done_r_reg; input \one_rank.stg1_wr_done_reg ; input cal1_state_r1535_out; input rstdiv0_sync_r1_reg_rep__23; input [2:0]\calib_sel_reg[3]_0 ; input \po_stg2_wrcal_cnt_reg[0] ; input [0:0]\po_stg2_wrcal_cnt_reg[1] ; input cal1_dq_idel_ce_reg_0; input prech_done; input [4:0]\pi_counter_read_val_reg[5] ; input rstdiv0_sync_r1_reg_rep__20; input \init_state_r_reg[3]_0 ; input wrcal_prech_req; input complex_ocal_ref_req; input prbs_rdlvl_prech_req_reg; input dqs_found_prech_req; input \init_state_r_reg[5]_0 ; input wrlvl_done_r1_reg; input wrlvl_done_r1_reg_0; input cnt_init_af_done_r; input dqs_found_done_r_reg_0; input prbs_rdlvl_done_reg_rep; input wrlvl_byte_redo; input wrlvl_final_mux; input mem_init_done_r; input prbs_rdlvl_done_reg_rep_0; input \num_refresh_reg[1] ; input prbs_last_byte_done_r; input wrlvl_final_mux_reg; input prbs_rdlvl_done_reg_rep_1; input oclkdelay_center_calib_done_r_reg; input wrlvl_done_r1; input wrlvl_byte_redo_reg; input \dout_o_reg[6] ; input first_wrcal_pat_r; input \dout_o_reg[6]_0 ; input prbs_rdlvl_done_reg; input wr_level_done_reg; input \prbs_dqs_cnt_r_reg[2] ; input \po_stg2_wrcal_cnt_reg[2] ; input [0:0]rdlvl_stg1_start_reg_0; input [0:0]E; input samp_edge_cnt0_en_r_reg_0; input [0:0]pi_cnt_dec_reg_1; input rstdiv0_sync_r1_reg_rep__2; wire CLK; wire [5:0]COUNTERLOADVAL; wire [1:0]D; wire [0:0]E; wire \FSM_sequential_cal1_state_r[0]_i_11_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_12_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_14_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_8_n_0 ; wire \FSM_sequential_cal1_state_r[0]_i_9_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_10_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_11_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_12_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_13_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_8_n_0 ; wire \FSM_sequential_cal1_state_r[1]_i_9_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[2]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[3]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[3]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[3]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[4]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_11_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_1_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_3_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_4_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_6_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_7_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_8_n_0 ; wire \FSM_sequential_cal1_state_r[5]_i_9_n_0 ; wire \FSM_sequential_cal1_state_r_reg[1]_0 ; wire \FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ; wire \FSM_sequential_cal1_state_r_reg[2]_0 ; wire \FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ; wire \FSM_sequential_cal1_state_r_reg[3]_0 ; wire \FSM_sequential_cal1_state_r_reg[4]_0 ; wire \FSM_sequential_cal1_state_r_reg[4]_1 ; wire \FSM_sequential_cal1_state_r_reg[4]_2 ; wire \FSM_sequential_cal1_state_r_reg[4]_3 ; wire \FSM_sequential_cal1_state_r_reg[4]_4 ; wire [0:0]Q; wire [0:0]SR; wire cal1_cnt_cpt_r1; wire \cal1_cnt_cpt_r[0]_i_1_n_0 ; wire \cal1_cnt_cpt_r[1]_i_2_n_0 ; wire \cal1_cnt_cpt_r[1]_i_3_n_0 ; wire \cal1_cnt_cpt_r[1]_i_4_n_0 ; wire \cal1_cnt_cpt_r[1]_i_5_n_0 ; wire \cal1_cnt_cpt_r_reg_n_0_[0] ; wire \cal1_cnt_cpt_r_reg_n_0_[1] ; wire cal1_dlyce_cpt_r; wire cal1_dlyce_cpt_r_i_2_n_0; wire cal1_dlyce_cpt_r_reg_n_0; wire cal1_dlyinc_cpt_r; wire cal1_dlyinc_cpt_r_i_2_n_0; wire cal1_dlyinc_cpt_r_reg_n_0; wire cal1_dq_idel_ce; wire cal1_dq_idel_ce_reg_0; wire cal1_dq_idel_inc; wire cal1_prech_req_r; wire cal1_prech_req_r_reg_n_0; (* RTL_KEEP = "yes" *) wire [5:5]cal1_state_r; wire cal1_state_r1; wire cal1_state_r1533_out; wire cal1_state_r1535_out; wire \cal1_state_r1[0]_i_1_n_0 ; wire \cal1_state_r1[1]_i_1_n_0 ; wire \cal1_state_r1[2]_i_1_n_0 ; wire \cal1_state_r1[3]_i_1_n_0 ; wire \cal1_state_r1[4]_i_1_n_0 ; wire \cal1_state_r1[5]_i_1_n_0 ; wire \cal1_state_r1_reg_n_0_[0] ; wire \cal1_state_r1_reg_n_0_[1] ; wire \cal1_state_r1_reg_n_0_[2] ; wire \cal1_state_r1_reg_n_0_[3] ; wire \cal1_state_r1_reg_n_0_[4] ; wire \cal1_state_r1_reg_n_0_[5] ; wire cal1_state_r2; wire cal1_wait_cnt_en_r; wire cal1_wait_cnt_en_r0; wire \cal1_wait_cnt_r[4]_i_1_n_0 ; wire [4:0]cal1_wait_cnt_r_reg__0; wire cal1_wait_r; wire cal1_wait_r_i_1_n_0; wire calib_in_common; wire [2:0]\calib_sel_reg[3] ; wire [2:0]\calib_sel_reg[3]_0 ; wire cmd_delay_start0; wire [5:0]cnt_idel_dec_cpt_r; wire [5:1]cnt_idel_dec_cpt_r2; wire \cnt_idel_dec_cpt_r[0]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r[0]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_10_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_11_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_12_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_13_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_14_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_6_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_7_n_0 ; wire \cnt_idel_dec_cpt_r[1]_i_8_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[2]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[3]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_4_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_7_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_8_n_0 ; wire \cnt_idel_dec_cpt_r[4]_i_9_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_10_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_11_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_12_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_13_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_1_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_3_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_5_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_6_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_7_n_0 ; wire \cnt_idel_dec_cpt_r[5]_i_8_n_0 ; wire \cnt_idel_dec_cpt_r_reg[0]_0 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ; wire \cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ; wire \cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ; wire \cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ; wire \cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 ; wire \cnt_idel_dec_cpt_r_reg_n_0_[0] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[1] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[2] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[3] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[4] ; wire \cnt_idel_dec_cpt_r_reg_n_0_[5] ; wire cnt_init_af_done_r; wire [3:0]cnt_shift_r_reg__0; wire complex_ocal_ref_req; wire detect_edge_done_r; wire detect_edge_done_r_i_1_n_0; wire detect_edge_done_r_i_2_n_0; wire [3:0]done_cnt; wire done_cnt1; wire \done_cnt[0]_i_1_n_0 ; wire \done_cnt[1]_i_1_n_0 ; wire \done_cnt[2]_i_1_n_0 ; wire \done_cnt[3]_i_1_n_0 ; wire \done_cnt[3]_i_3_n_0 ; wire \done_cnt[3]_i_4_n_0 ; wire \dout_o_reg[6] ; wire \dout_o_reg[6]_0 ; wire dqs_found_done_r_reg; wire dqs_found_done_r_reg_0; wire dqs_found_prech_req; wire dqs_po_dec_done; wire dqs_po_dec_done_r1; wire dqs_po_dec_done_r2; wire fine_dly_dec_done_r1; wire fine_dly_dec_done_r1_i_1_n_0; wire fine_dly_dec_done_r1_i_2_n_0; wire fine_dly_dec_done_r1_i_3_n_0; wire fine_dly_dec_done_r2; wire \first_edge_taps_r[5]_i_1_n_0 ; wire \first_edge_taps_r[5]_i_2_n_0 ; wire \first_edge_taps_r_reg_n_0_[0] ; wire \first_edge_taps_r_reg_n_0_[1] ; wire \first_edge_taps_r_reg_n_0_[2] ; wire \first_edge_taps_r_reg_n_0_[3] ; wire \first_edge_taps_r_reg_n_0_[4] ; wire \first_edge_taps_r_reg_n_0_[5] ; wire first_wrcal_pat_r; wire found_edge_r_i_1_n_0; wire found_edge_r_i_2_n_0; wire found_edge_r_reg_0; wire found_edge_r_reg_1; wire found_edge_r_reg_2; wire found_edge_r_reg_3; wire found_edge_r_reg_4; wire found_first_edge_r_reg_0; wire found_stable_eye_last_r; wire found_stable_eye_last_r_reg_0; wire found_stable_eye_last_r_reg_1; wire found_stable_eye_r_i_1_n_0; wire found_stable_eye_r_i_2_n_0; wire found_stable_eye_r_reg_0; wire \gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ; wire \gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire \gen_byte_sel_div1.calib_in_common_reg_0 ; wire \gen_byte_sel_div1.calib_in_common_reg_1 ; wire \gen_byte_sel_div1.calib_in_common_reg_2 ; wire \gen_byte_sel_div1.calib_in_common_reg_3 ; wire \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ; wire \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ; wire \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ; wire \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ; wire \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ; wire \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ; wire \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ; wire \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ; wire \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ; wire \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ; wire \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ; wire \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ; wire \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ; wire \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ; wire \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ; wire \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ; wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ; wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ; wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ; wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ; wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ; wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ; wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ; wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ; wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ; wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ; wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ; wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ; wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ; wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ; wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ; wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ; wire \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ; wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ; wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ; wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 ; wire \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ; wire \gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ; wire \gen_track_left_edge[0].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ; wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ; wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ; wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 ; wire \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ; wire \gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ; wire \gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ; wire \gen_track_left_edge[1].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ; wire \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ; wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 ; wire \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ; wire \gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ; wire \gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ; wire \gen_track_left_edge[2].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ; wire \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ; wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 ; wire \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ; wire \gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ; wire \gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ; wire \gen_track_left_edge[3].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ; wire \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ; wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 ; wire \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ; wire \gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ; wire \gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ; wire \gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ; wire \gen_track_left_edge[4].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ; wire \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ; wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 ; wire \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ; wire \gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ; wire \gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ; wire \gen_track_left_edge[5].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ; wire \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ; wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 ; wire \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ; wire \gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ; wire \gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ; wire \gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ; wire \gen_track_left_edge[6].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ; wire \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ; wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ; wire [4:0]\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 ; wire \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ; wire \gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ; wire \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ; wire \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ; wire \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ; wire idel_adj_inc_reg_0; wire idel_adj_inc_reg_1; wire idel_adj_inc_reg_2; wire [0:0]idel_dec_cnt; wire \idel_dec_cnt[0]_i_2_n_0 ; wire \idel_dec_cnt[1]_i_1_n_0 ; wire \idel_dec_cnt[2]_i_1_n_0 ; wire \idel_dec_cnt[3]_i_1_n_0 ; wire \idel_dec_cnt[3]_i_2_n_0 ; wire \idel_dec_cnt[4]_i_1_n_0 ; wire \idel_dec_cnt[4]_i_2_n_0 ; wire \idel_dec_cnt[4]_i_4_n_0 ; wire \idel_dec_cnt[4]_i_5_n_0 ; wire \idel_dec_cnt[4]_i_7_n_0 ; wire \idel_dec_cnt[4]_i_8_n_0 ; wire \idel_dec_cnt[4]_i_9_n_0 ; wire [4:0]idel_dec_cnt__0; wire \idel_dec_cnt_reg[0]_0 ; wire idel_mpr_pat_detect_r; wire idel_pat0_data_match_r0__0; wire idel_pat0_match_fall0_and_r; wire idel_pat0_match_fall1_and_r; wire idel_pat0_match_fall2_and_r; wire idel_pat0_match_fall3_and_r; wire idel_pat0_match_rise0_and_r; wire idel_pat0_match_rise1_and_r; wire idel_pat0_match_rise2_and_r; wire idel_pat0_match_rise3_and_r; wire idel_pat1_data_match_r0__0; wire idel_pat1_match_fall0_and_r; wire idel_pat1_match_fall1_and_r; wire idel_pat1_match_fall2_and_r; wire idel_pat1_match_fall3_and_r; wire idel_pat1_match_rise0_and_r; wire idel_pat1_match_rise1_and_r; wire idel_pat1_match_rise2_and_r; wire idel_pat1_match_rise3_and_r; wire idelay_ce_int; wire idelay_inc_int; wire [4:0]idelay_tap_cnt_r; wire \idelay_tap_cnt_r[0][0][0]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][1]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][2]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][3]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][3]_i_2_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_2_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_4_n_0 ; wire \idelay_tap_cnt_r[0][0][4]_i_5_n_0 ; wire \idelay_tap_cnt_r[0][1][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][2][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][3][4]_i_1_n_0 ; wire \idelay_tap_cnt_r[0][3][4]_i_2_n_0 ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][0][4] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][1][4] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][2][4] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][0] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][1] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][2] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][3] ; wire \idelay_tap_cnt_r_reg_n_0_[0][3][4] ; wire [4:0]idelay_tap_cnt_slice_r; wire idelay_tap_limit_r_i_1_n_0; wire idelay_tap_limit_r_i_2_n_0; wire idelay_tap_limit_r_reg_n_0; wire inhibit_edge_detect_r; wire inhibit_edge_detect_r0; wire \init_state_r[0]_i_48_n_0 ; wire \init_state_r[0]_i_49_n_0 ; wire \init_state_r[0]_i_53_n_0 ; wire \init_state_r[0]_i_54_n_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[0]_2 ; wire \init_state_r_reg[0]_3 ; wire \init_state_r_reg[0]_4 ; wire \init_state_r_reg[1] ; wire [1:0]\init_state_r_reg[1]_0 ; wire \init_state_r_reg[2] ; wire \init_state_r_reg[2]_0 ; wire \init_state_r_reg[2]_1 ; wire \init_state_r_reg[2]_2 ; wire \init_state_r_reg[3] ; wire \init_state_r_reg[3]_0 ; wire \init_state_r_reg[4] ; wire \init_state_r_reg[5] ; wire \init_state_r_reg[5]_0 ; wire mem_init_done_r; wire \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ; wire \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ; wire \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ; wire \mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ; wire \mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ; wire \mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ; wire \mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ; wire \mpr_4to1.stable_idel_cnt_reg_n_0_[0] ; wire \mpr_4to1.stable_idel_cnt_reg_n_0_[1] ; wire \mpr_4to1.stable_idel_cnt_reg_n_0_[2] ; wire mpr_dec_cpt_r_reg_0; wire mpr_dec_cpt_r_reg_1; wire mpr_last_byte_done; wire mpr_last_byte_done_reg_0; wire mpr_rank_done_r_reg_0; wire mpr_rank_done_r_reg_1; wire mpr_rd_fall0_prev_r; wire mpr_rd_fall1_prev_r; wire mpr_rd_fall2_prev_r; wire mpr_rd_fall3_prev_r; wire mpr_rd_rise0_prev_r; wire mpr_rd_rise0_prev_r0; wire mpr_rd_rise0_prev_r_reg_0; wire mpr_rd_rise0_prev_r_reg_1; wire mpr_rd_rise1_prev_r; wire mpr_rd_rise2_prev_r; wire mpr_rd_rise3_prev_r; wire mpr_rdlvl_done_r1; wire mpr_rdlvl_done_r1_reg_0; wire mpr_rdlvl_done_r2; wire mpr_rdlvl_done_r_reg_0; wire mpr_rdlvl_done_r_reg_1; wire mpr_rdlvl_start_r; wire mpr_rdlvl_start_reg; wire mpr_rnk_done; wire mpr_valid_r; wire mpr_valid_r1; wire mpr_valid_r1_reg_0; wire mpr_valid_r2; wire mpr_valid_r_reg_0; wire new_cnt_cpt_r; wire new_cnt_cpt_r82_out; wire new_cnt_cpt_r_i_2_n_0; wire new_cnt_cpt_r_reg_n_0; wire \num_refresh_reg[1] ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_center_calib_done_r_reg; wire \one_rank.stg1_wr_done_reg ; (* RTL_KEEP = "yes" *) wire [4:0]out; wire p_0_in; wire p_0_in102_in; wire p_0_in10_in; wire p_0_in134_in; wire p_0_in13_in; wire p_0_in155_in; wire p_0_in16_in; wire p_0_in180_in; wire p_0_in1_in; wire p_0_in205_in; wire p_0_in230_in; wire p_0_in255_in; wire p_0_in280_in; wire p_0_in305_in; wire p_0_in330_in; wire p_0_in355_in; wire p_0_in380_in; wire p_0_in405_in; wire p_0_in430_in; wire p_0_in455_in; wire p_0_in4_in; wire p_0_in539_in; wire p_0_in7_in; wire p_0_in84_in; wire p_0_in87_in; wire p_0_in90_in; wire p_0_in93_in; wire p_0_in96_in; wire p_0_in99_in; wire [5:2]p_0_in__0; wire [4:0]p_0_in__0__0; wire [3:0]p_0_in__1; wire [4:0]p_0_in__2; wire [4:0]p_0_in__3; wire [4:0]p_0_in__4; wire [4:0]p_0_in__5; wire [4:0]p_0_in__6; wire [4:0]p_0_in__7; wire [4:0]p_0_in__8; wire [4:0]p_0_in__9; wire p_137_out__0; wire p_163_out__0; wire p_188_out__0; wire p_1_in11_in; wire p_1_in14_in; wire p_1_in162_in; wire p_1_in17_in; wire p_1_in187_in; wire p_1_in212_in; wire p_1_in237_in; wire p_1_in262_in; wire p_1_in26_in; wire p_1_in287_in; wire p_1_in2_in; wire p_1_in312_in; wire p_1_in337_in; wire p_1_in362_in; wire p_1_in387_in; wire p_1_in412_in; wire p_1_in437_in; wire p_1_in462_in; wire p_1_in5_in; wire p_1_in8_in; wire p_213_out__0; wire p_238_out__0; wire p_263_out__0; wire p_288_out__0; wire p_2_in156_in; wire p_2_in181_in; wire p_2_in206_in; wire p_2_in231_in; wire p_2_in256_in; wire p_2_in281_in; wire p_2_in306_in; wire p_2_in331_in; wire p_2_in356_in; wire p_2_in381_in; wire p_2_in406_in; wire p_2_in431_in; wire p_2_in456_in; wire p_313_out__0; wire p_338_out__0; wire p_363_out__0; wire p_388_out__0; wire p_3_in135_in; wire p_3_in157_in; wire p_3_in182_in; wire p_3_in207_in; wire p_3_in232_in; wire p_3_in257_in; wire p_3_in282_in; wire p_3_in307_in; wire p_3_in332_in; wire p_3_in357_in; wire p_3_in382_in; wire p_3_in407_in; wire p_3_in432_in; wire p_3_in457_in; wire p_413_out__0; wire p_438_out__0; wire p_463_out__0; wire p_488_out__0; wire p_4_in158_in; wire p_4_in183_in; wire p_4_in208_in; wire p_4_in233_in; wire p_4_in258_in; wire p_4_in283_in; wire p_4_in308_in; wire p_4_in333_in; wire p_4_in358_in; wire p_4_in383_in; wire p_4_in408_in; wire p_4_in433_in; wire p_4_in458_in; wire p_513_out__0; wire p_5_in136_in; wire p_5_in159_in; wire p_5_in184_in; wire p_5_in209_in; wire p_5_in234_in; wire p_5_in259_in; wire p_5_in284_in; wire p_5_in309_in; wire p_5_in334_in; wire p_5_in359_in; wire p_5_in384_in; wire p_5_in409_in; wire p_5_in434_in; wire p_5_in459_in; wire p_6_in160_in; wire p_6_in185_in; wire p_6_in210_in; wire p_6_in235_in; wire p_6_in260_in; wire p_6_in285_in; wire p_6_in310_in; wire p_6_in335_in; wire p_6_in360_in; wire p_6_in385_in; wire p_6_in410_in; wire p_6_in435_in; wire p_6_in460_in; wire p_7_in; wire p_7_in161_in; wire p_7_in186_in; wire p_7_in211_in; wire p_7_in236_in; wire p_7_in261_in; wire p_7_in286_in; wire p_7_in311_in; wire p_7_in336_in; wire p_7_in361_in; wire p_7_in386_in; wire p_7_in411_in; wire p_7_in436_in; wire p_7_in461_in; wire pat0_data_match_r0__0; wire pat0_match_fall0_and_r; wire pat0_match_fall1_and_r; wire pat0_match_fall2_and_r; wire pat0_match_fall3_and_r; wire pat0_match_rise0_and_r; wire pat0_match_rise1_and_r; wire pat0_match_rise2_and_r; wire pat0_match_rise3_and_r; wire pat1_data_match_r0__0; wire pat1_match_fall0_and_r; wire pat1_match_fall1_and_r; wire pat1_match_fall2_and_r; wire pat1_match_fall3_and_r; wire pat1_match_rise0_and_r; wire pat1_match_rise1_and_r; wire pat1_match_rise2_and_r; wire pat1_match_rise3_and_r; wire pb_cnt_eye_size_r; wire pb_detect_edge; wire [7:0]pb_detect_edge_done_r; wire pb_detect_edge_setup; wire pb_found_stable_eye_r52_out; wire pb_found_stable_eye_r56_out; wire pb_found_stable_eye_r60_out; wire pb_found_stable_eye_r64_out; wire pb_found_stable_eye_r68_out; wire pb_found_stable_eye_r72_out; wire pb_found_stable_eye_r76_out; wire phy_rddata_en_1; wire pi_cnt_dec_reg_0; wire [0:0]pi_cnt_dec_reg_1; wire pi_counter_load_en; wire [5:0]pi_counter_load_val; wire [4:0]\pi_counter_read_val_reg[5] ; wire \pi_dqs_found_lanes_r1_reg[0] ; wire \pi_dqs_found_lanes_r1_reg[0]_0 ; wire \pi_dqs_found_lanes_r1_reg[0]_1 ; wire \pi_dqs_found_lanes_r1_reg[1] ; wire \pi_dqs_found_lanes_r1_reg[1]_0 ; wire \pi_dqs_found_lanes_r1_reg[1]_1 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_2 ; wire \pi_dqs_found_lanes_r1_reg[2] ; wire \pi_dqs_found_lanes_r1_reg[2]_0 ; wire \pi_dqs_found_lanes_r1_reg[2]_1 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_2 ; wire \pi_dqs_found_lanes_r1_reg[3] ; wire \pi_dqs_found_lanes_r1_reg[3]_0 ; wire \pi_dqs_found_lanes_r1_reg[3]_1 ; wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_2 ; wire pi_en_stg2_f_timing; wire pi_en_stg2_f_timing_i_1_n_0; wire pi_en_stg2_f_timing_reg_0; wire pi_fine_dly_dec_done; wire [5:0]pi_rdval_cnt; wire \pi_rdval_cnt[0]_i_1_n_0 ; wire \pi_rdval_cnt[1]_i_1_n_0 ; wire \pi_rdval_cnt[2]_i_1_n_0 ; wire \pi_rdval_cnt[3]_i_1_n_0 ; wire \pi_rdval_cnt[3]_i_2_n_0 ; wire \pi_rdval_cnt[4]_i_1_n_0 ; wire \pi_rdval_cnt[4]_i_2_n_0 ; wire \pi_rdval_cnt[5]_i_1_n_0 ; wire \pi_rdval_cnt[5]_i_2_n_0 ; wire \pi_rdval_cnt[5]_i_4_n_0 ; wire \pi_rdval_cnt[5]_i_5_n_0 ; wire \pi_rdval_cnt_reg[1]_0 ; wire pi_stg2_f_incdec_timing; wire pi_stg2_f_incdec_timing0; wire pi_stg2_load_timing; wire [1:0]pi_stg2_rdlvl_cnt; wire [5:0]pi_stg2_reg_l_timing; wire \pi_stg2_reg_l_timing[0]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[1]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[2]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[3]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[4]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[5]_i_1_n_0 ; wire \pi_stg2_reg_l_timing[5]_i_2_n_0 ; wire \pi_stg2_reg_l_timing_reg[0]_0 ; wire \po_stg2_wrcal_cnt_reg[0] ; wire [0:0]\po_stg2_wrcal_cnt_reg[1] ; wire \po_stg2_wrcal_cnt_reg[2] ; wire \prbs_dqs_cnt_r_reg[2] ; wire prbs_last_byte_done_r; wire prbs_pi_stg2_f_en; wire prbs_pi_stg2_f_incdec; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prbs_rdlvl_done_reg_rep_0; wire prbs_rdlvl_done_reg_rep_1; wire prbs_rdlvl_prech_req_reg; wire prech_done; wire prech_req; wire \rd_mux_sel_r_reg[1]_0 ; wire \rd_mux_sel_r_reg[1]_1 ; wire \rd_mux_sel_r_reg[1]_10 ; wire \rd_mux_sel_r_reg[1]_11 ; wire \rd_mux_sel_r_reg[1]_12 ; wire \rd_mux_sel_r_reg[1]_13 ; wire \rd_mux_sel_r_reg[1]_14 ; wire \rd_mux_sel_r_reg[1]_15 ; wire \rd_mux_sel_r_reg[1]_16 ; wire \rd_mux_sel_r_reg[1]_17 ; wire \rd_mux_sel_r_reg[1]_18 ; wire \rd_mux_sel_r_reg[1]_19 ; wire \rd_mux_sel_r_reg[1]_2 ; wire \rd_mux_sel_r_reg[1]_20 ; wire \rd_mux_sel_r_reg[1]_21 ; wire \rd_mux_sel_r_reg[1]_22 ; wire \rd_mux_sel_r_reg[1]_23 ; wire \rd_mux_sel_r_reg[1]_24 ; wire \rd_mux_sel_r_reg[1]_25 ; wire \rd_mux_sel_r_reg[1]_26 ; wire \rd_mux_sel_r_reg[1]_27 ; wire \rd_mux_sel_r_reg[1]_28 ; wire \rd_mux_sel_r_reg[1]_29 ; wire \rd_mux_sel_r_reg[1]_3 ; wire \rd_mux_sel_r_reg[1]_30 ; wire \rd_mux_sel_r_reg[1]_31 ; wire \rd_mux_sel_r_reg[1]_32 ; wire \rd_mux_sel_r_reg[1]_33 ; wire \rd_mux_sel_r_reg[1]_34 ; wire \rd_mux_sel_r_reg[1]_35 ; wire \rd_mux_sel_r_reg[1]_36 ; wire \rd_mux_sel_r_reg[1]_37 ; wire \rd_mux_sel_r_reg[1]_38 ; wire \rd_mux_sel_r_reg[1]_39 ; wire \rd_mux_sel_r_reg[1]_4 ; wire \rd_mux_sel_r_reg[1]_40 ; wire \rd_mux_sel_r_reg[1]_41 ; wire \rd_mux_sel_r_reg[1]_42 ; wire \rd_mux_sel_r_reg[1]_43 ; wire \rd_mux_sel_r_reg[1]_44 ; wire \rd_mux_sel_r_reg[1]_45 ; wire \rd_mux_sel_r_reg[1]_46 ; wire \rd_mux_sel_r_reg[1]_47 ; wire \rd_mux_sel_r_reg[1]_48 ; wire \rd_mux_sel_r_reg[1]_49 ; wire \rd_mux_sel_r_reg[1]_5 ; wire \rd_mux_sel_r_reg[1]_50 ; wire \rd_mux_sel_r_reg[1]_51 ; wire \rd_mux_sel_r_reg[1]_52 ; wire \rd_mux_sel_r_reg[1]_53 ; wire \rd_mux_sel_r_reg[1]_54 ; wire \rd_mux_sel_r_reg[1]_55 ; wire \rd_mux_sel_r_reg[1]_56 ; wire \rd_mux_sel_r_reg[1]_57 ; wire \rd_mux_sel_r_reg[1]_58 ; wire \rd_mux_sel_r_reg[1]_59 ; wire \rd_mux_sel_r_reg[1]_6 ; wire \rd_mux_sel_r_reg[1]_60 ; wire \rd_mux_sel_r_reg[1]_61 ; wire \rd_mux_sel_r_reg[1]_62 ; wire \rd_mux_sel_r_reg[1]_63 ; wire \rd_mux_sel_r_reg[1]_7 ; wire \rd_mux_sel_r_reg[1]_8 ; wire \rd_mux_sel_r_reg[1]_9 ; wire \rdlvl_cpt_tap_cnt_reg[1] ; wire \rdlvl_cpt_tap_cnt_reg[2] ; wire \rdlvl_cpt_tap_cnt_reg[4] ; wire rdlvl_dqs_tap_cnt_r; wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ; wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ; wire \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ; wire \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ; wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ; wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ; wire rdlvl_last_byte_done; wire rdlvl_pi_incdec; wire rdlvl_pi_incdec_i_4_n_0; wire rdlvl_pi_incdec_i_5_n_0; wire rdlvl_pi_incdec_i_6_n_0; wire rdlvl_pi_incdec_reg_0; wire rdlvl_pi_incdec_reg_1; wire rdlvl_pi_stg2_f_en; wire rdlvl_pi_stg2_f_incdec; wire rdlvl_prech_req; wire rdlvl_rank_done_r_reg_0; wire rdlvl_stg1_done_int; wire rdlvl_stg1_done_r1_reg; wire rdlvl_stg1_rank_done; wire rdlvl_stg1_start_r; wire rdlvl_stg1_start_reg; wire [0:0]rdlvl_stg1_start_reg_0; wire [1:0]regl_dqs_cnt; wire \regl_dqs_cnt[0]_i_1_n_0 ; wire \regl_dqs_cnt[1]_i_1_n_0 ; wire \regl_dqs_cnt[1]_i_2_n_0 ; wire \regl_dqs_cnt[2]_i_1_n_0 ; wire [2:0]regl_dqs_cnt_r; wire [0:0]\regl_dqs_cnt_r_reg[2]_0 ; wire \regl_dqs_cnt_reg[0]_0 ; wire \regl_dqs_cnt_reg[2]_0 ; wire [1:0]regl_rank_cnt; wire \regl_rank_cnt[0]_i_1_n_0 ; wire \regl_rank_cnt[1]_i_1_n_0 ; wire \right_edge_taps_r[0]_i_1_n_0 ; wire \right_edge_taps_r[1]_i_1_n_0 ; wire \right_edge_taps_r[2]_i_1_n_0 ; wire \right_edge_taps_r[3]_i_1_n_0 ; wire \right_edge_taps_r[4]_i_1_n_0 ; wire \right_edge_taps_r[5]_i_1_n_0 ; wire \right_edge_taps_r[5]_i_2_n_0 ; wire [5:0]right_edge_taps_r__0; wire \right_edge_taps_r_reg[0]_0 ; wire \right_edge_taps_r_reg[0]_1 ; wire \right_edge_taps_r_reg[0]_2 ; wire \rnk_cnt_r[0]_i_1__0_n_0 ; wire \rnk_cnt_r[1]_i_1__0_n_0 ; wire \rnk_cnt_r[1]_i_2_n_0 ; wire \rnk_cnt_r[1]_i_3_n_0 ; wire \rnk_cnt_r_reg_n_0_[0] ; wire \rnk_cnt_r_reg_n_0_[1] ; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire samp_cnt_done_r_i_1_n_0; wire samp_cnt_done_r_i_2_n_0; wire samp_cnt_done_r_i_3_n_0; wire samp_cnt_done_r_i_4_n_0; wire samp_cnt_done_r_reg_0; wire samp_cnt_done_r_reg_1; wire samp_cnt_done_r_reg_2; wire samp_cnt_done_r_reg_3; wire samp_cnt_done_r_reg_4; wire samp_cnt_done_r_reg_5; wire samp_cnt_done_r_reg_6; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg_0; wire samp_edge_cnt0_r0; wire \samp_edge_cnt0_r[0]_i_4_n_0 ; wire \samp_edge_cnt0_r[0]_i_5_n_0 ; wire \samp_edge_cnt0_r[0]_i_6_n_0 ; wire \samp_edge_cnt0_r[0]_i_7_n_0 ; wire \samp_edge_cnt0_r[4]_i_2_n_0 ; wire \samp_edge_cnt0_r[4]_i_3_n_0 ; wire \samp_edge_cnt0_r[4]_i_4_n_0 ; wire \samp_edge_cnt0_r[4]_i_5_n_0 ; wire \samp_edge_cnt0_r[8]_i_2_n_0 ; wire \samp_edge_cnt0_r[8]_i_3_n_0 ; wire \samp_edge_cnt0_r[8]_i_4_n_0 ; wire \samp_edge_cnt0_r[8]_i_5_n_0 ; wire [11:0]samp_edge_cnt0_r_reg; wire \samp_edge_cnt0_r_reg[0]_i_3_n_0 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_1 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_2 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_3 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_4 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_5 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_6 ; wire \samp_edge_cnt0_r_reg[0]_i_3_n_7 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_0 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_1 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_2 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_3 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_4 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_5 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_6 ; wire \samp_edge_cnt0_r_reg[4]_i_1_n_7 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_1 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_2 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_3 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_4 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_5 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_6 ; wire \samp_edge_cnt0_r_reg[8]_i_1_n_7 ; wire samp_edge_cnt1_en_r; wire samp_edge_cnt1_en_r0; wire samp_edge_cnt1_en_r_i_2_n_0; wire samp_edge_cnt1_en_r_i_3_n_0; wire \samp_edge_cnt1_r[0]_i_2_n_0 ; wire \samp_edge_cnt1_r[0]_i_3_n_0 ; wire \samp_edge_cnt1_r[0]_i_4_n_0 ; wire \samp_edge_cnt1_r[0]_i_5_n_0 ; wire \samp_edge_cnt1_r[4]_i_2_n_0 ; wire \samp_edge_cnt1_r[4]_i_3_n_0 ; wire \samp_edge_cnt1_r[4]_i_4_n_0 ; wire \samp_edge_cnt1_r[4]_i_5_n_0 ; wire \samp_edge_cnt1_r[8]_i_2_n_0 ; wire \samp_edge_cnt1_r[8]_i_3_n_0 ; wire \samp_edge_cnt1_r[8]_i_4_n_0 ; wire \samp_edge_cnt1_r[8]_i_5_n_0 ; wire [11:0]samp_edge_cnt1_r_reg; wire \samp_edge_cnt1_r_reg[0]_i_1_n_0 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_1 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_2 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_3 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_4 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_5 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_6 ; wire \samp_edge_cnt1_r_reg[0]_i_1_n_7 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_0 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_1 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_2 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_3 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_4 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_5 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_6 ; wire \samp_edge_cnt1_r_reg[4]_i_1_n_7 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_1 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_2 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_3 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_4 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_5 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_6 ; wire \samp_edge_cnt1_r_reg[8]_i_1_n_7 ; wire \second_edge_taps_r[0]_i_1_n_0 ; wire \second_edge_taps_r[1]_i_1_n_0 ; wire \second_edge_taps_r[2]_i_1_n_0 ; wire \second_edge_taps_r[3]_i_1_n_0 ; wire \second_edge_taps_r[4]_i_1_n_0 ; wire \second_edge_taps_r[5]_i_1_n_0 ; wire \second_edge_taps_r[5]_i_3_n_0 ; wire \second_edge_taps_r_reg[5]_0 ; wire \second_edge_taps_r_reg_n_0_[0] ; wire \second_edge_taps_r_reg_n_0_[1] ; wire \second_edge_taps_r_reg_n_0_[2] ; wire \second_edge_taps_r_reg_n_0_[3] ; wire \second_edge_taps_r_reg_n_0_[4] ; wire \second_edge_taps_r_reg_n_0_[5] ; wire sr_valid_r1; wire sr_valid_r108_out; wire sr_valid_r1_reg_0; wire sr_valid_r2; wire stable_idel_cnt; wire stable_idel_cnt0; wire stable_idel_cnt22_in; wire stg1_wr_done; wire \stg1_wr_rd_cnt_reg[3] ; wire store_sr_r0; wire store_sr_r1; wire store_sr_r_reg_0; wire store_sr_req_pulsed_r; wire store_sr_req_pulsed_r_reg_n_0; wire store_sr_req_r; wire store_sr_req_r_i_2_n_0; wire store_sr_req_r_reg_0; wire store_sr_req_r_reg_1; wire tap_cnt_cpt_r; wire tap_cnt_cpt_r0; wire \tap_cnt_cpt_r[1]_i_1_n_0 ; wire \tap_cnt_cpt_r[5]_i_4_n_0 ; wire \tap_cnt_cpt_r_reg_n_0_[0] ; wire \tap_cnt_cpt_r_reg_n_0_[1] ; wire \tap_cnt_cpt_r_reg_n_0_[2] ; wire \tap_cnt_cpt_r_reg_n_0_[3] ; wire \tap_cnt_cpt_r_reg_n_0_[4] ; wire \tap_cnt_cpt_r_reg_n_0_[5] ; wire tap_limit_cpt_r; wire tap_limit_cpt_r_i_1_n_0; wire tap_limit_cpt_r_i_2_n_0; wire tap_limit_cpt_r_i_3_n_0; wire tempmon_pi_f_en_r; wire tempmon_pi_f_inc_r; wire wait_cnt_r0; wire [3:0]wait_cnt_r0__0; wire \wait_cnt_r[1]_i_1__1_n_0 ; wire [1:0]\wait_cnt_r_reg[0]_0 ; wire \wait_cnt_r_reg[0]_1 ; wire [3:2]wait_cnt_r_reg__0; wire wr_level_done_reg; wire wrcal_done_reg; wire wrcal_prech_req; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ; wire wrlvl_byte_redo; wire wrlvl_byte_redo_reg; wire wrlvl_done_r1; wire wrlvl_done_r1_reg; wire wrlvl_done_r1_reg_0; wire wrlvl_final_mux; wire wrlvl_final_mux_reg; wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED ; wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED ; wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED ; wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED ; wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED ; wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED ; wire [3:3]\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED ; LUT6 #( .INIT(64'hFFFFFEAEAAAAFEAE)) \FSM_sequential_cal1_state_r[0]_i_1 (.I0(\FSM_sequential_cal1_state_r[0]_i_2_n_0 ), .I1(\FSM_sequential_cal1_state_r[0]_i_3_n_0 ), .I2(out[0]), .I3(\FSM_sequential_cal1_state_r[0]_i_4_n_0 ), .I4(out[1]), .I5(\FSM_sequential_cal1_state_r[0]_i_5_n_0 ), .O(\FSM_sequential_cal1_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000002000000)) \FSM_sequential_cal1_state_r[0]_i_10 (.I0(\done_cnt[3]_i_3_n_0 ), .I1(regl_rank_cnt[1]), .I2(regl_rank_cnt[0]), .I3(regl_dqs_cnt[0]), .I4(regl_dqs_cnt[1]), .I5(\regl_dqs_cnt_r_reg[2]_0 ), .O(cal1_state_r1)); LUT5 #( .INIT(32'hBFFFFF00)) \FSM_sequential_cal1_state_r[0]_i_11 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(out[0]), .I4(out[2]), .O(\FSM_sequential_cal1_state_r[0]_i_11_n_0 )); LUT6 #( .INIT(64'h0000150000000000)) \FSM_sequential_cal1_state_r[0]_i_12 (.I0(\FSM_sequential_cal1_state_r[0]_i_14_n_0 ), .I1(mpr_dec_cpt_r_reg_0), .I2(stable_idel_cnt22_in), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I5(out[2]), .O(\FSM_sequential_cal1_state_r[0]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_cal1_state_r[0]_i_13 (.I0(\right_edge_taps_r_reg[0]_0 ), .I1(found_stable_eye_last_r), .O(cal1_state_r1533_out)); (* SOFT_HLUTNM = "soft_lutpair205" *) LUT4 #( .INIT(16'hFFFE)) \FSM_sequential_cal1_state_r[0]_i_14 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .O(\FSM_sequential_cal1_state_r[0]_i_14_n_0 )); LUT6 #( .INIT(64'hBBBB88B888B8BBB8)) \FSM_sequential_cal1_state_r[0]_i_2 (.I0(\FSM_sequential_cal1_state_r[0]_i_6_n_0 ), .I1(\idel_dec_cnt_reg[0]_0 ), .I2(\FSM_sequential_cal1_state_r[0]_i_7_n_0 ), .I3(out[4]), .I4(out[2]), .I5(out[0]), .O(\FSM_sequential_cal1_state_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'h8988898889998988)) \FSM_sequential_cal1_state_r[0]_i_3 (.I0(out[2]), .I1(out[4]), .I2(mpr_rdlvl_done_r1_reg_0), .I3(cal1_state_r), .I4(mpr_rdlvl_start_reg), .I5(mpr_rdlvl_start_r), .O(\FSM_sequential_cal1_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'h1110101011111111)) \FSM_sequential_cal1_state_r[0]_i_4 (.I0(out[2]), .I1(cal1_state_r), .I2(out[3]), .I3(idelay_tap_limit_r_reg_n_0), .I4(\FSM_sequential_cal1_state_r[0]_i_8_n_0 ), .I5(out[4]), .O(\FSM_sequential_cal1_state_r[0]_i_4_n_0 )); LUT6 #( .INIT(64'hEEAFEEAAEEAFEEAF)) \FSM_sequential_cal1_state_r[0]_i_5 (.I0(\FSM_sequential_cal1_state_r[0]_i_9_n_0 ), .I1(cal1_state_r1), .I2(\FSM_sequential_cal1_state_r[0]_i_11_n_0 ), .I3(cal1_state_r), .I4(out[3]), .I5(store_sr_req_r_reg_0), .O(\FSM_sequential_cal1_state_r[0]_i_5_n_0 )); LUT5 #( .INIT(32'h11040004)) \FSM_sequential_cal1_state_r[0]_i_6 (.I0(out[2]), .I1(out[3]), .I2(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I3(out[0]), .I4(mpr_rdlvl_done_r1_reg_0), .O(\FSM_sequential_cal1_state_r[0]_i_6_n_0 )); LUT5 #( .INIT(32'hFFFFA800)) \FSM_sequential_cal1_state_r[0]_i_7 (.I0(mpr_rd_rise0_prev_r_reg_0), .I1(idelay_tap_limit_r_reg_n_0), .I2(idel_mpr_pat_detect_r), .I3(out[0]), .I4(\FSM_sequential_cal1_state_r[0]_i_12_n_0 ), .O(\FSM_sequential_cal1_state_r[0]_i_7_n_0 )); LUT2 #( .INIT(4'h1)) \FSM_sequential_cal1_state_r[0]_i_8 (.I0(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .O(\FSM_sequential_cal1_state_r[0]_i_8_n_0 )); LUT6 #( .INIT(64'h2220202000000000)) \FSM_sequential_cal1_state_r[0]_i_9 (.I0(out[0]), .I1(out[3]), .I2(tap_limit_cpt_r), .I3(found_first_edge_r_reg_0), .I4(cal1_state_r1533_out), .I5(out[4]), .O(\FSM_sequential_cal1_state_r[0]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF2EEE2222)) \FSM_sequential_cal1_state_r[1]_i_1 (.I0(\FSM_sequential_cal1_state_r[1]_i_2_n_0 ), .I1(out[0]), .I2(out[4]), .I3(\FSM_sequential_cal1_state_r[1]_i_3_n_0 ), .I4(\FSM_sequential_cal1_state_r[1]_i_4_n_0 ), .I5(\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ), .O(\FSM_sequential_cal1_state_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT4 #( .INIT(16'hFEFF)) \FSM_sequential_cal1_state_r[1]_i_10 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I3(mpr_dec_cpt_r_reg_0), .O(\FSM_sequential_cal1_state_r[1]_i_10_n_0 )); LUT4 #( .INIT(16'h4474)) \FSM_sequential_cal1_state_r[1]_i_11 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(cal1_state_r), .I2(mpr_rdlvl_start_reg), .I3(mpr_rdlvl_start_r), .O(\FSM_sequential_cal1_state_r[1]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT3 #( .INIT(8'h7F)) \FSM_sequential_cal1_state_r[1]_i_12 (.I0(found_stable_eye_last_r), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(found_first_edge_r_reg_0), .O(\FSM_sequential_cal1_state_r[1]_i_12_n_0 )); LUT2 #( .INIT(4'hE)) \FSM_sequential_cal1_state_r[1]_i_13 (.I0(out[3]), .I1(out[2]), .O(\FSM_sequential_cal1_state_r[1]_i_13_n_0 )); LUT6 #( .INIT(64'h0C0C0C0C88888088)) \FSM_sequential_cal1_state_r[1]_i_2 (.I0(out[4]), .I1(\FSM_sequential_cal1_state_r[1]_i_6_n_0 ), .I2(out[1]), .I3(mpr_dec_cpt_r_reg_0), .I4(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I5(out[2]), .O(\FSM_sequential_cal1_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hEF00FF00EFFFFF00)) \FSM_sequential_cal1_state_r[1]_i_3 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(cal1_cnt_cpt_r1), .I3(out[3]), .I4(mpr_rdlvl_done_r1_reg_0), .I5(idel_adj_inc_reg_0), .O(\FSM_sequential_cal1_state_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'h5500000055510055)) \FSM_sequential_cal1_state_r[1]_i_4 (.I0(cal1_state_r), .I1(mpr_rd_rise0_prev_r_reg_0), .I2(idel_mpr_pat_detect_r), .I3(out[2]), .I4(out[1]), .I5(out[4]), .O(\FSM_sequential_cal1_state_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \FSM_sequential_cal1_state_r[1]_i_6 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I1(out[4]), .I2(stable_idel_cnt22_in), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I5(\FSM_sequential_cal1_state_r[1]_i_10_n_0 ), .O(\FSM_sequential_cal1_state_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_cal1_state_r[1]_i_7 (.I0(\pi_rdval_cnt_reg[1]_0 ), .I1(idel_dec_cnt__0[2]), .I2(idel_dec_cnt__0[1]), .I3(idel_dec_cnt__0[0]), .I4(idel_dec_cnt__0[3]), .I5(idel_dec_cnt__0[4]), .O(\FSM_sequential_cal1_state_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'h0101010151515101)) \FSM_sequential_cal1_state_r[1]_i_8 (.I0(out[2]), .I1(\FSM_sequential_cal1_state_r[1]_i_11_n_0 ), .I2(out[4]), .I3(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .I4(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .I5(out[3]), .O(\FSM_sequential_cal1_state_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'h000000004040FF40)) \FSM_sequential_cal1_state_r[1]_i_9 (.I0(tap_limit_cpt_r), .I1(\FSM_sequential_cal1_state_r[1]_i_12_n_0 ), .I2(out[4]), .I3(cal1_state_r), .I4(cal1_state_r1), .I5(\FSM_sequential_cal1_state_r[1]_i_13_n_0 ), .O(\FSM_sequential_cal1_state_r[1]_i_9_n_0 )); LUT5 #( .INIT(32'hFFFF3404)) \FSM_sequential_cal1_state_r[2]_i_1 (.I0(out[4]), .I1(out[2]), .I2(out[0]), .I3(out[3]), .I4(\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ), .O(\FSM_sequential_cal1_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h8888AAA8AAAAAAAA)) \FSM_sequential_cal1_state_r[2]_i_3 (.I0(out[4]), .I1(out[0]), .I2(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I3(mpr_dec_cpt_r_reg_0), .I4(out[2]), .I5(out[3]), .O(\FSM_sequential_cal1_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'h00AB00AB03AB00AB)) \FSM_sequential_cal1_state_r[2]_i_4 (.I0(\FSM_sequential_cal1_state_r[2]_i_5_n_0 ), .I1(out[4]), .I2(cal1_state_r), .I3(out[0]), .I4(mpr_rd_rise0_prev_r_reg_0), .I5(idel_mpr_pat_detect_r), .O(\FSM_sequential_cal1_state_r[2]_i_4_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_sequential_cal1_state_r[2]_i_5 (.I0(out[2]), .I1(out[3]), .O(\FSM_sequential_cal1_state_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'h303030003008CC08)) \FSM_sequential_cal1_state_r[3]_i_1 (.I0(\FSM_sequential_cal1_state_r[3]_i_2_n_0 ), .I1(out[2]), .I2(out[4]), .I3(out[1]), .I4(out[3]), .I5(out[0]), .O(\FSM_sequential_cal1_state_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \FSM_sequential_cal1_state_r[3]_i_2 (.I0(mpr_dec_cpt_r_reg_0), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I5(\FSM_sequential_cal1_state_r[3]_i_3_n_0 ), .O(\FSM_sequential_cal1_state_r[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_cal1_state_r[3]_i_3 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\FSM_sequential_cal1_state_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'h0C0C0C8C)) \FSM_sequential_cal1_state_r[4]_i_1 (.I0(out[2]), .I1(\FSM_sequential_cal1_state_r[4]_i_2_n_0 ), .I2(\FSM_sequential_cal1_state_r[4]_i_3_n_0 ), .I3(\FSM_sequential_cal1_state_r[4]_i_4_n_0 ), .I4(out[0]), .O(\FSM_sequential_cal1_state_r[4]_i_1_n_0 )); LUT5 #( .INIT(32'hEFFFFFFF)) \FSM_sequential_cal1_state_r[4]_i_2 (.I0(idel_adj_inc_reg_0), .I1(mpr_rdlvl_done_r1_reg_0), .I2(out[0]), .I3(out[2]), .I4(out[1]), .O(\FSM_sequential_cal1_state_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h000000000000AFEF)) \FSM_sequential_cal1_state_r[4]_i_3 (.I0(out[3]), .I1(mpr_dec_cpt_r_reg_0), .I2(out[2]), .I3(out[0]), .I4(\FSM_sequential_cal1_state_r[4]_i_5_n_0 ), .I5(\FSM_sequential_cal1_state_r[4]_i_6_n_0 ), .O(\FSM_sequential_cal1_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'hA0A0A0A0A0A0A0A1)) \FSM_sequential_cal1_state_r[4]_i_4 (.I0(out[1]), .I1(\FSM_sequential_cal1_state_r[4]_i_7_n_0 ), .I2(out[3]), .I3(stable_idel_cnt22_in), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\FSM_sequential_cal1_state_r[4]_i_4_n_0 )); LUT6 #( .INIT(64'h1000101010101010)) \FSM_sequential_cal1_state_r[4]_i_5 (.I0(out[0]), .I1(out[1]), .I2(out[4]), .I3(\FSM_sequential_cal1_state_r[1]_i_7_n_0 ), .I4(out[3]), .I5(mpr_dec_cpt_r_reg_0), .O(\FSM_sequential_cal1_state_r[4]_i_5_n_0 )); LUT5 #( .INIT(32'h55404440)) \FSM_sequential_cal1_state_r[4]_i_6 (.I0(out[2]), .I1(out[1]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .O(\FSM_sequential_cal1_state_r[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair205" *) LUT4 #( .INIT(16'hFFFD)) \FSM_sequential_cal1_state_r[4]_i_7 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .O(\FSM_sequential_cal1_state_r[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'hFFFEFFFF)) \FSM_sequential_cal1_state_r[4]_i_8 (.I0(idelay_tap_cnt_r[4]), .I1(idelay_tap_cnt_r[3]), .I2(idelay_tap_cnt_r[2]), .I3(idelay_tap_cnt_r[1]), .I4(\idel_dec_cnt[0]_i_2_n_0 ), .O(stable_idel_cnt22_in)); LUT6 #( .INIT(64'h101F101F101F1010)) \FSM_sequential_cal1_state_r[5]_i_1 (.I0(cal1_state_r), .I1(\FSM_sequential_cal1_state_r[5]_i_3_n_0 ), .I2(out[4]), .I3(out[3]), .I4(\FSM_sequential_cal1_state_r[5]_i_4_n_0 ), .I5(\FSM_sequential_cal1_state_r[5]_i_5_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h0FF00FF050005FC0)) \FSM_sequential_cal1_state_r[5]_i_11 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_valid_r1_reg_0), .I2(out[0]), .I3(cal1_state_r), .I4(cal1_wait_r), .I5(out[1]), .O(\FSM_sequential_cal1_state_r[5]_i_11_n_0 )); LUT6 #( .INIT(64'h00005400FC00FC00)) \FSM_sequential_cal1_state_r[5]_i_2 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(out[3]), .I2(cal1_state_r), .I3(\FSM_sequential_cal1_state_r[5]_i_6_n_0 ), .I4(\rnk_cnt_r_reg_n_0_[1] ), .I5(\FSM_sequential_cal1_state_r[5]_i_7_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0000B0B1FBF5B0B1)) \FSM_sequential_cal1_state_r[5]_i_3 (.I0(out[3]), .I1(out[2]), .I2(cal1_wait_r), .I3(out[1]), .I4(out[0]), .I5(\FSM_sequential_cal1_state_r[5]_i_8_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0007FFFF00070000)) \FSM_sequential_cal1_state_r[5]_i_4 (.I0(cal1_wait_r), .I1(out[0]), .I2(cal1_state_r), .I3(out[1]), .I4(out[2]), .I5(\FSM_sequential_cal1_state_r[5]_i_9_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000010111010)) \FSM_sequential_cal1_state_r[5]_i_5 (.I0(out[0]), .I1(cal1_state_r), .I2(cal1_state_r1535_out), .I3(rdlvl_stg1_start_r), .I4(rdlvl_stg1_start_reg), .I5(out[1]), .O(\FSM_sequential_cal1_state_r[5]_i_5_n_0 )); LUT5 #( .INIT(32'hC0FE00CC)) \FSM_sequential_cal1_state_r[5]_i_6 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(out[1]), .I2(out[2]), .I3(out[4]), .I4(out[0]), .O(\FSM_sequential_cal1_state_r[5]_i_6_n_0 )); LUT5 #( .INIT(32'h80000000)) \FSM_sequential_cal1_state_r[5]_i_7 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(out[1]), .I4(out[0]), .O(\FSM_sequential_cal1_state_r[5]_i_7_n_0 )); LUT5 #( .INIT(32'hC000EEEE)) \FSM_sequential_cal1_state_r[5]_i_8 (.I0(detect_edge_done_r), .I1(out[3]), .I2(out[1]), .I3(prech_done), .I4(out[2]), .O(\FSM_sequential_cal1_state_r[5]_i_8_n_0 )); LUT5 #( .INIT(32'hFFFF00D0)) \FSM_sequential_cal1_state_r[5]_i_9 (.I0(cal1_wait_r), .I1(store_sr_req_r_reg_0), .I2(out[1]), .I3(cal1_state_r), .I4(\FSM_sequential_cal1_state_r[5]_i_11_n_0 ), .O(\FSM_sequential_cal1_state_r[5]_i_9_n_0 )); (* KEEP = "yes" *) FDRE \FSM_sequential_cal1_state_r_reg[0] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[0]_i_1_n_0 ), .Q(out[0]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE \FSM_sequential_cal1_state_r_reg[1] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[1]_i_1_n_0 ), .Q(out[1]), .R(rstdiv0_sync_r1_reg_rep__2)); MUXF7 \FSM_sequential_cal1_state_r_reg[1]_i_5 (.I0(\FSM_sequential_cal1_state_r[1]_i_8_n_0 ), .I1(\FSM_sequential_cal1_state_r[1]_i_9_n_0 ), .O(\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ), .S(out[1])); (* KEEP = "yes" *) FDRE \FSM_sequential_cal1_state_r_reg[2] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[2]_i_1_n_0 ), .Q(out[2]), .R(rstdiv0_sync_r1_reg_rep__2)); MUXF7 \FSM_sequential_cal1_state_r_reg[2]_i_2 (.I0(\FSM_sequential_cal1_state_r[2]_i_3_n_0 ), .I1(\FSM_sequential_cal1_state_r[2]_i_4_n_0 ), .O(\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ), .S(out[1])); (* KEEP = "yes" *) FDRE \FSM_sequential_cal1_state_r_reg[3] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[3]_i_1_n_0 ), .Q(out[3]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE \FSM_sequential_cal1_state_r_reg[4] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[4]_i_1_n_0 ), .Q(out[4]), .R(rstdiv0_sync_r1_reg_rep__2)); (* KEEP = "yes" *) FDRE \FSM_sequential_cal1_state_r_reg[5] (.C(CLK), .CE(\FSM_sequential_cal1_state_r[5]_i_1_n_0 ), .D(\FSM_sequential_cal1_state_r[5]_i_2_n_0 ), .Q(cal1_state_r), .R(rstdiv0_sync_r1_reg_rep__2)); LUT3 #( .INIT(8'h34)) \cal1_cnt_cpt_r[0]_i_1 (.I0(cal1_state_r), .I1(\cal1_cnt_cpt_r[1]_i_3_n_0 ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .O(\cal1_cnt_cpt_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h1F20)) \cal1_cnt_cpt_r[1]_i_2 (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I1(cal1_state_r), .I2(\cal1_cnt_cpt_r[1]_i_3_n_0 ), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .O(\cal1_cnt_cpt_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00800A0000000000)) \cal1_cnt_cpt_r[1]_i_3 (.I0(out[1]), .I1(\cal1_cnt_cpt_r[1]_i_4_n_0 ), .I2(out[3]), .I3(cal1_state_r), .I4(out[4]), .I5(\cal1_cnt_cpt_r[1]_i_5_n_0 ), .O(\cal1_cnt_cpt_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAA2AAAAAAAAA)) \cal1_cnt_cpt_r[1]_i_4 (.I0(prech_done), .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .I4(\rnk_cnt_r_reg_n_0_[1] ), .I5(mpr_rdlvl_done_r1_reg_0), .O(\cal1_cnt_cpt_r[1]_i_4_n_0 )); LUT3 #( .INIT(8'h81)) \cal1_cnt_cpt_r[1]_i_5 (.I0(out[0]), .I1(out[2]), .I2(out[3]), .O(\cal1_cnt_cpt_r[1]_i_5_n_0 )); FDRE \cal1_cnt_cpt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r[0]_i_1_n_0 ), .Q(\cal1_cnt_cpt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \cal1_cnt_cpt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r[1]_i_2_n_0 ), .Q(\cal1_cnt_cpt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0010000000003000)) cal1_dlyce_cpt_r_i_1 (.I0(tap_limit_cpt_r), .I1(cal1_state_r), .I2(cal1_dlyce_cpt_r_i_2_n_0), .I3(out[2]), .I4(out[4]), .I5(out[3]), .O(cal1_dlyce_cpt_r)); LUT3 #( .INIT(8'h24)) cal1_dlyce_cpt_r_i_2 (.I0(out[0]), .I1(out[2]), .I2(out[1]), .O(cal1_dlyce_cpt_r_i_2_n_0)); FDRE cal1_dlyce_cpt_r_reg (.C(CLK), .CE(1'b1), .D(cal1_dlyce_cpt_r), .Q(cal1_dlyce_cpt_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000000001000000)) cal1_dlyinc_cpt_r_i_1 (.I0(out[2]), .I1(tap_limit_cpt_r), .I2(cal1_state_r), .I3(out[1]), .I4(out[0]), .I5(cal1_dlyinc_cpt_r_i_2_n_0), .O(cal1_dlyinc_cpt_r)); LUT2 #( .INIT(4'h7)) cal1_dlyinc_cpt_r_i_2 (.I0(out[3]), .I1(out[4]), .O(cal1_dlyinc_cpt_r_i_2_n_0)); FDRE cal1_dlyinc_cpt_r_reg (.C(CLK), .CE(1'b1), .D(cal1_dlyinc_cpt_r), .Q(cal1_dlyinc_cpt_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT5 #( .INIT(32'h00000020)) cal1_dq_idel_ce_i_1 (.I0(out[2]), .I1(out[3]), .I2(out[4]), .I3(out[0]), .I4(cal1_state_r), .O(cal1_dq_idel_ce)); FDRE cal1_dq_idel_ce_reg (.C(CLK), .CE(1'b1), .D(cal1_dq_idel_ce), .Q(idelay_ce_int), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000000000001000)) cal1_dq_idel_inc_i_1 (.I0(cal1_state_r), .I1(out[1]), .I2(out[4]), .I3(out[2]), .I4(out[3]), .I5(out[0]), .O(cal1_dq_idel_inc)); FDRE cal1_dq_idel_inc_reg (.C(CLK), .CE(1'b1), .D(cal1_dq_idel_inc), .Q(idelay_inc_int), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h2000000000000000)) cal1_prech_req_r_i_1 (.I0(out[4]), .I1(cal1_state_r), .I2(out[2]), .I3(out[3]), .I4(out[1]), .I5(out[0]), .O(cal1_prech_req_r)); FDRE cal1_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(cal1_prech_req_r), .Q(cal1_prech_req_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'h00404000501F500C)) \cal1_state_r1[0]_i_1 (.I0(cal1_state_r), .I1(out[1]), .I2(out[4]), .I3(out[3]), .I4(out[0]), .I5(out[2]), .O(\cal1_state_r1[0]_i_1_n_0 )); LUT6 #( .INIT(64'h090A010E00045440)) \cal1_state_r1[1]_i_1 (.I0(out[3]), .I1(out[0]), .I2(cal1_state_r), .I3(out[1]), .I4(out[2]), .I5(out[4]), .O(\cal1_state_r1[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000CA0F1102C)) \cal1_state_r1[2]_i_1 (.I0(out[1]), .I1(out[0]), .I2(out[4]), .I3(out[3]), .I4(out[2]), .I5(cal1_state_r), .O(\cal1_state_r1[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0101C54901008482)) \cal1_state_r1[3]_i_1 (.I0(out[2]), .I1(out[4]), .I2(out[3]), .I3(out[1]), .I4(cal1_state_r), .I5(out[0]), .O(\cal1_state_r1[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0100004500000440)) \cal1_state_r1[4]_i_1 (.I0(out[3]), .I1(out[1]), .I2(cal1_state_r), .I3(out[4]), .I4(out[2]), .I5(out[0]), .O(\cal1_state_r1[4]_i_1_n_0 )); LUT6 #( .INIT(64'h1000000800004002)) \cal1_state_r1[5]_i_1 (.I0(cal1_state_r), .I1(out[1]), .I2(out[4]), .I3(out[3]), .I4(out[2]), .I5(out[0]), .O(\cal1_state_r1[5]_i_1_n_0 )); FDRE \cal1_state_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[0]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[0] ), .R(1'b0)); FDRE \cal1_state_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[1]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[1] ), .R(1'b0)); FDRE \cal1_state_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[2]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[2] ), .R(1'b0)); FDRE \cal1_state_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[3]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[3] ), .R(1'b0)); FDRE \cal1_state_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[4]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[4] ), .R(1'b0)); FDRE \cal1_state_r1_reg[5] (.C(CLK), .CE(1'b1), .D(\cal1_state_r1[5]_i_1_n_0 ), .Q(\cal1_state_r1_reg_n_0_[5] ), .R(1'b0)); LUT6 #( .INIT(64'h06090C0600090F12)) cal1_wait_cnt_en_r_i_1 (.I0(out[1]), .I1(out[3]), .I2(cal1_state_r), .I3(out[4]), .I4(out[0]), .I5(out[2]), .O(cal1_wait_cnt_en_r0)); FDRE cal1_wait_cnt_en_r_reg (.C(CLK), .CE(1'b1), .D(cal1_wait_cnt_en_r0), .Q(cal1_wait_cnt_en_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \cal1_wait_cnt_r[0]_i_1 (.I0(cal1_wait_cnt_r_reg__0[0]), .O(p_0_in__0__0[0])); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h6)) \cal1_wait_cnt_r[1]_i_1 (.I0(cal1_wait_cnt_r_reg__0[1]), .I1(cal1_wait_cnt_r_reg__0[0]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT3 #( .INIT(8'h6A)) \cal1_wait_cnt_r[2]_i_1 (.I0(cal1_wait_cnt_r_reg__0[2]), .I1(cal1_wait_cnt_r_reg__0[0]), .I2(cal1_wait_cnt_r_reg__0[1]), .O(p_0_in__0__0[2])); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT4 #( .INIT(16'h6AAA)) \cal1_wait_cnt_r[3]_i_1 (.I0(cal1_wait_cnt_r_reg__0[3]), .I1(cal1_wait_cnt_r_reg__0[1]), .I2(cal1_wait_cnt_r_reg__0[0]), .I3(cal1_wait_cnt_r_reg__0[2]), .O(p_0_in__0__0[3])); LUT6 #( .INIT(64'h40000000FFFFFFFF)) \cal1_wait_cnt_r[4]_i_1 (.I0(cal1_wait_cnt_r_reg__0[4]), .I1(cal1_wait_cnt_r_reg__0[3]), .I2(cal1_wait_cnt_r_reg__0[1]), .I3(cal1_wait_cnt_r_reg__0[0]), .I4(cal1_wait_cnt_r_reg__0[2]), .I5(cal1_wait_cnt_en_r), .O(\cal1_wait_cnt_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT5 #( .INIT(32'h6AAAAAAA)) \cal1_wait_cnt_r[4]_i_2 (.I0(cal1_wait_cnt_r_reg__0[4]), .I1(cal1_wait_cnt_r_reg__0[2]), .I2(cal1_wait_cnt_r_reg__0[0]), .I3(cal1_wait_cnt_r_reg__0[1]), .I4(cal1_wait_cnt_r_reg__0[3]), .O(p_0_in__0__0[4])); FDRE \cal1_wait_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[0]), .Q(cal1_wait_cnt_r_reg__0[0]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE \cal1_wait_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[1]), .Q(cal1_wait_cnt_r_reg__0[1]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE \cal1_wait_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[2]), .Q(cal1_wait_cnt_r_reg__0[2]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE \cal1_wait_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[3]), .Q(cal1_wait_cnt_r_reg__0[3]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); FDRE \cal1_wait_cnt_r_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[4]), .Q(cal1_wait_cnt_r_reg__0[4]), .R(\cal1_wait_cnt_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hBFFFFFFFFFFFFFFF)) cal1_wait_r_i_1 (.I0(cal1_wait_cnt_r_reg__0[4]), .I1(cal1_wait_cnt_r_reg__0[3]), .I2(cal1_wait_cnt_r_reg__0[1]), .I3(cal1_wait_cnt_r_reg__0[0]), .I4(cal1_wait_cnt_r_reg__0[2]), .I5(cal1_wait_cnt_en_r), .O(cal1_wait_r_i_1_n_0)); FDRE cal1_wait_r_reg (.C(CLK), .CE(1'b1), .D(cal1_wait_r_i_1_n_0), .Q(cal1_wait_r), .R(1'b0)); LUT5 #( .INIT(32'h74FF7400)) \cnt_idel_dec_cpt_r[0]_i_1 (.I0(cnt_idel_dec_cpt_r2[1]), .I1(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I2(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ), .I3(out[0]), .I4(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[0])); LUT6 #( .INIT(64'hB800B8FFB8FFB800)) \cnt_idel_dec_cpt_r[0]_i_2 (.I0(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[1] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\tap_cnt_cpt_r_reg_n_0_[0] ), .I5(right_edge_taps_r__0[1]), .O(\cnt_idel_dec_cpt_r[0]_i_2_n_0 )); LUT4 #( .INIT(16'h404F)) \cnt_idel_dec_cpt_r[0]_i_3 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [0]), .I2(out[1]), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'h6F60FFFF6F600000)) \cnt_idel_dec_cpt_r[1]_i_1 (.I0(cnt_idel_dec_cpt_r2[2]), .I1(cnt_idel_dec_cpt_r2[1]), .I2(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I3(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ), .I4(out[0]), .I5(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ), .O(cnt_idel_dec_cpt_r[1])); (* SOFT_HLUTNM = "soft_lutpair208" *) LUT4 #( .INIT(16'h4BB4)) \cnt_idel_dec_cpt_r[1]_i_10 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(right_edge_taps_r__0[1]), .I2(right_edge_taps_r__0[2]), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_11 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\first_edge_taps_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[1]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_12 (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ), .I1(\first_edge_taps_r_reg_n_0_[2] ), .O(\cnt_idel_dec_cpt_r[1]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_13 (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ), .I1(\first_edge_taps_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_14 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(\first_edge_taps_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[1]_i_14_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[1]_i_3 (.I0(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[1]_i_10_n_0 ), .O(\cnt_idel_dec_cpt_r[1]_i_3_n_0 )); LUT5 #( .INIT(32'h4F40404F)) \cnt_idel_dec_cpt_r[1]_i_4 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [1]), .I2(out[1]), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_5 (.I0(\second_edge_taps_r_reg_n_0_[3] ), .I1(\first_edge_taps_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[1]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_6 (.I0(\second_edge_taps_r_reg_n_0_[2] ), .I1(\first_edge_taps_r_reg_n_0_[2] ), .O(\cnt_idel_dec_cpt_r[1]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_7 (.I0(\second_edge_taps_r_reg_n_0_[1] ), .I1(\first_edge_taps_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[1]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[1]_i_8 (.I0(\second_edge_taps_r_reg_n_0_[0] ), .I1(\first_edge_taps_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[1]_i_8_n_0 )); LUT5 #( .INIT(32'hB8B8B88B)) \cnt_idel_dec_cpt_r[2]_i_2 (.I0(\rdlvl_cpt_tap_cnt_reg[2] ), .I1(out[1]), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .O(\cnt_idel_dec_cpt_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'h6AFF6A00)) \cnt_idel_dec_cpt_r[2]_i_3 (.I0(cnt_idel_dec_cpt_r2[3]), .I1(cnt_idel_dec_cpt_r2[1]), .I2(cnt_idel_dec_cpt_r2[2]), .I3(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I4(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ), .O(\cnt_idel_dec_cpt_r[2]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[2]_i_4 (.I0(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ), .O(\cnt_idel_dec_cpt_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'h40F4BF0BBF0B40F4)) \cnt_idel_dec_cpt_r[2]_i_5 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(right_edge_taps_r__0[1]), .I2(right_edge_taps_r__0[2]), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .I4(right_edge_taps_r__0[3]), .I5(\tap_cnt_cpt_r_reg_n_0_[2] ), .O(\cnt_idel_dec_cpt_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'hB8B8B8B8B8B8B88B)) \cnt_idel_dec_cpt_r[3]_i_2 (.I0(\calib_sel_reg[3]_0 [1]), .I1(out[1]), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6AAAFFFF6AAA0000)) \cnt_idel_dec_cpt_r[3]_i_3 (.I0(cnt_idel_dec_cpt_r2[4]), .I1(cnt_idel_dec_cpt_r2[2]), .I2(cnt_idel_dec_cpt_r2[1]), .I3(cnt_idel_dec_cpt_r2[3]), .I4(\cnt_idel_dec_cpt_r_reg[0]_0 ), .I5(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ), .O(\cnt_idel_dec_cpt_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[3]_i_4 (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[4] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ), .O(\cnt_idel_dec_cpt_r[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT3 #( .INIT(8'h96)) \cnt_idel_dec_cpt_r[3]_i_5 (.I0(\cnt_idel_dec_cpt_r[5]_i_11_n_0 ), .I1(right_edge_taps_r__0[4]), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[3]_i_5_n_0 )); LUT6 #( .INIT(64'hB888B8BBB8BBB888)) \cnt_idel_dec_cpt_r[4]_i_1 (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ), .I1(out[0]), .I2(\rdlvl_cpt_tap_cnt_reg[4] ), .I3(out[1]), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I5(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[4])); (* SOFT_HLUTNM = "soft_lutpair206" *) LUT4 #( .INIT(16'h0001)) \cnt_idel_dec_cpt_r[4]_i_3 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .O(\cnt_idel_dec_cpt_r[4]_i_3_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \cnt_idel_dec_cpt_r[4]_i_4 (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ), .I1(\right_edge_taps_r_reg[0]_0 ), .I2(\tap_cnt_cpt_r_reg_n_0_[5] ), .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I4(\cnt_idel_dec_cpt_r[4]_i_7_n_0 ), .O(\cnt_idel_dec_cpt_r[4]_i_4_n_0 )); LUT5 #( .INIT(32'h6AAAAAAA)) \cnt_idel_dec_cpt_r[4]_i_5 (.I0(cnt_idel_dec_cpt_r2[5]), .I1(cnt_idel_dec_cpt_r2[3]), .I2(cnt_idel_dec_cpt_r2[1]), .I3(cnt_idel_dec_cpt_r2[2]), .I4(cnt_idel_dec_cpt_r2[4]), .O(\cnt_idel_dec_cpt_r[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT5 #( .INIT(32'hB24D4DB2)) \cnt_idel_dec_cpt_r[4]_i_7 (.I0(\cnt_idel_dec_cpt_r[5]_i_11_n_0 ), .I1(\tap_cnt_cpt_r_reg_n_0_[3] ), .I2(right_edge_taps_r__0[4]), .I3(right_edge_taps_r__0[5]), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .O(\cnt_idel_dec_cpt_r[4]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[4]_i_8 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(\first_edge_taps_r_reg_n_0_[5] ), .O(\cnt_idel_dec_cpt_r[4]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[4]_i_9 (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ), .I1(\first_edge_taps_r_reg_n_0_[4] ), .O(\cnt_idel_dec_cpt_r[4]_i_9_n_0 )); LUT6 #( .INIT(64'h0000008800222000)) \cnt_idel_dec_cpt_r[5]_i_1 (.I0(\cnt_idel_dec_cpt_r[5]_i_3_n_0 ), .I1(out[3]), .I2(store_sr_req_r_reg_0), .I3(out[1]), .I4(out[2]), .I5(out[0]), .O(\cnt_idel_dec_cpt_r[5]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \cnt_idel_dec_cpt_r[5]_i_10 (.I0(cnt_idel_dec_cpt_r2[4]), .I1(cnt_idel_dec_cpt_r2[2]), .I2(cnt_idel_dec_cpt_r2[1]), .I3(cnt_idel_dec_cpt_r2[3]), .O(\cnt_idel_dec_cpt_r[5]_i_10_n_0 )); LUT6 #( .INIT(64'h2B222222BBBB2B22)) \cnt_idel_dec_cpt_r[5]_i_11 (.I0(right_edge_taps_r__0[3]), .I1(\tap_cnt_cpt_r_reg_n_0_[2] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(right_edge_taps_r__0[1]), .I4(right_edge_taps_r__0[2]), .I5(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(\cnt_idel_dec_cpt_r[5]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[5]_i_12 (.I0(\second_edge_taps_r_reg_n_0_[5] ), .I1(\first_edge_taps_r_reg_n_0_[5] ), .O(\cnt_idel_dec_cpt_r[5]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \cnt_idel_dec_cpt_r[5]_i_13 (.I0(\second_edge_taps_r_reg_n_0_[4] ), .I1(\first_edge_taps_r_reg_n_0_[4] ), .O(\cnt_idel_dec_cpt_r[5]_i_13_n_0 )); LUT3 #( .INIT(8'h41)) \cnt_idel_dec_cpt_r[5]_i_3 (.I0(cal1_state_r), .I1(out[4]), .I2(out[3]), .O(\cnt_idel_dec_cpt_r[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \cnt_idel_dec_cpt_r[5]_i_4 (.I0(\rdlvl_cpt_tap_cnt_reg[4] ), .I1(\rdlvl_cpt_tap_cnt_reg[1] ), .I2(\rdlvl_cpt_tap_cnt_reg[2] ), .I3(\calib_sel_reg[3]_0 [1]), .I4(\calib_sel_reg[3]_0 [0]), .I5(\calib_sel_reg[3]_0 [2]), .O(store_sr_req_r_reg_0)); LUT5 #( .INIT(32'hB88BB8B8)) \cnt_idel_dec_cpt_r[5]_i_5 (.I0(\calib_sel_reg[3]_0 [2]), .I1(out[1]), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I4(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ), .O(\cnt_idel_dec_cpt_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'hF00F0F0F11111111)) \cnt_idel_dec_cpt_r[5]_i_6 (.I0(\cnt_idel_dec_cpt_r[5]_i_7_n_0 ), .I1(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ), .I2(\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ), .I3(\cnt_idel_dec_cpt_r[5]_i_10_n_0 ), .I4(cnt_idel_dec_cpt_r2[5]), .I5(\cnt_idel_dec_cpt_r_reg[0]_0 ), .O(\cnt_idel_dec_cpt_r[5]_i_6_n_0 )); LUT6 #( .INIT(64'h9A59AAAA55559A59)) \cnt_idel_dec_cpt_r[5]_i_7 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(right_edge_taps_r__0[4]), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .I3(\cnt_idel_dec_cpt_r[5]_i_11_n_0 ), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .I5(right_edge_taps_r__0[5]), .O(\cnt_idel_dec_cpt_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \cnt_idel_dec_cpt_r[5]_i_8 (.I0(right_edge_taps_r__0[2]), .I1(right_edge_taps_r__0[3]), .I2(right_edge_taps_r__0[1]), .I3(right_edge_taps_r__0[0]), .I4(right_edge_taps_r__0[5]), .I5(right_edge_taps_r__0[4]), .O(\cnt_idel_dec_cpt_r[5]_i_8_n_0 )); FDRE \cnt_idel_dec_cpt_r_reg[0] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[0]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .R(1'b0)); FDRE \cnt_idel_dec_cpt_r_reg[1] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[1]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .R(1'b0)); CARRY4 \cnt_idel_dec_cpt_r_reg[1]_i_2 (.CI(1'b0), .CO({\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ,\cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ,\cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ,\cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 }), .CYINIT(1'b1), .DI({\second_edge_taps_r_reg_n_0_[3] ,\second_edge_taps_r_reg_n_0_[2] ,\second_edge_taps_r_reg_n_0_[1] ,\second_edge_taps_r_reg_n_0_[0] }), .O({cnt_idel_dec_cpt_r2[3:1],\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED [0]}), .S({\cnt_idel_dec_cpt_r[1]_i_5_n_0 ,\cnt_idel_dec_cpt_r[1]_i_6_n_0 ,\cnt_idel_dec_cpt_r[1]_i_7_n_0 ,\cnt_idel_dec_cpt_r[1]_i_8_n_0 })); CARRY4 \cnt_idel_dec_cpt_r_reg[1]_i_9 (.CI(1'b0), .CO({\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 }), .CYINIT(1'b1), .DI({\tap_cnt_cpt_r_reg_n_0_[3] ,\tap_cnt_cpt_r_reg_n_0_[2] ,\tap_cnt_cpt_r_reg_n_0_[1] ,\tap_cnt_cpt_r_reg_n_0_[0] }), .O({\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ,\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ,\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED [0]}), .S({\cnt_idel_dec_cpt_r[1]_i_11_n_0 ,\cnt_idel_dec_cpt_r[1]_i_12_n_0 ,\cnt_idel_dec_cpt_r[1]_i_13_n_0 ,\cnt_idel_dec_cpt_r[1]_i_14_n_0 })); FDRE \cnt_idel_dec_cpt_r_reg[2] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[2]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[2]_i_1 (.I0(\cnt_idel_dec_cpt_r[2]_i_2_n_0 ), .I1(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[2]), .S(out[0])); FDRE \cnt_idel_dec_cpt_r_reg[3] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[3]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[3]_i_1 (.I0(\cnt_idel_dec_cpt_r[3]_i_2_n_0 ), .I1(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ), .O(cnt_idel_dec_cpt_r[3]), .S(out[0])); FDRE \cnt_idel_dec_cpt_r_reg[4] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[4]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[4]_i_2 (.I0(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ), .I1(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ), .O(\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ), .S(\cnt_idel_dec_cpt_r_reg[0]_0 )); CARRY4 \cnt_idel_dec_cpt_r_reg[4]_i_6 (.CI(\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ), .CO({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED [3:1],\cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\tap_cnt_cpt_r_reg_n_0_[4] }), .O({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED [3:2],\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ,\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 }), .S({1'b0,1'b0,\cnt_idel_dec_cpt_r[4]_i_8_n_0 ,\cnt_idel_dec_cpt_r[4]_i_9_n_0 })); FDRE \cnt_idel_dec_cpt_r_reg[5] (.C(CLK), .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ), .D(cnt_idel_dec_cpt_r[5]), .Q(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .R(1'b0)); MUXF7 \cnt_idel_dec_cpt_r_reg[5]_i_2 (.I0(\cnt_idel_dec_cpt_r[5]_i_5_n_0 ), .I1(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ), .O(cnt_idel_dec_cpt_r[5]), .S(out[0])); CARRY4 \cnt_idel_dec_cpt_r_reg[5]_i_9 (.CI(\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ), .CO({\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [3],\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ,\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [1],\cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,\second_edge_taps_r_reg_n_0_[5] ,\second_edge_taps_r_reg_n_0_[4] }), .O({\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED [3:2],cnt_idel_dec_cpt_r2[5:4]}), .S({1'b0,1'b1,\cnt_idel_dec_cpt_r[5]_i_12_n_0 ,\cnt_idel_dec_cpt_r[5]_i_13_n_0 })); LUT6 #( .INIT(64'h00000000FFFFFFF7)) \cnt_shift_r[0]_i_1 (.I0(rdlvl_stg1_start_reg), .I1(phy_rddata_en_1), .I2(cnt_shift_r_reg__0[1]), .I3(cnt_shift_r_reg__0[3]), .I4(cnt_shift_r_reg__0[2]), .I5(cnt_shift_r_reg__0[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT2 #( .INIT(4'h6)) \cnt_shift_r[1]_i_1 (.I0(cnt_shift_r_reg__0[1]), .I1(cnt_shift_r_reg__0[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT3 #( .INIT(8'h6A)) \cnt_shift_r[2]_i_1 (.I0(cnt_shift_r_reg__0[2]), .I1(cnt_shift_r_reg__0[0]), .I2(cnt_shift_r_reg__0[1]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT4 #( .INIT(16'h6AAA)) \cnt_shift_r[3]_i_3 (.I0(cnt_shift_r_reg__0[3]), .I1(cnt_shift_r_reg__0[1]), .I2(cnt_shift_r_reg__0[0]), .I3(cnt_shift_r_reg__0[2]), .O(p_0_in__1[3])); FDSE \cnt_shift_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in__1[0]), .Q(cnt_shift_r_reg__0[0]), .S(rdlvl_stg1_start_reg_0)); FDRE \cnt_shift_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in__1[1]), .Q(cnt_shift_r_reg__0[1]), .R(rdlvl_stg1_start_reg_0)); FDRE \cnt_shift_r_reg[2] (.C(CLK), .CE(E), .D(p_0_in__1[2]), .Q(cnt_shift_r_reg__0[2]), .R(rdlvl_stg1_start_reg_0)); FDRE \cnt_shift_r_reg[3] (.C(CLK), .CE(E), .D(p_0_in__1[3]), .Q(cnt_shift_r_reg__0[3]), .R(rdlvl_stg1_start_reg_0)); LUT2 #( .INIT(4'h8)) \ctl_lane_cnt[1]_i_2 (.I0(pi_fine_dly_dec_done), .I1(dqs_po_dec_done), .O(cmd_delay_start0)); LUT5 #( .INIT(32'h00008000)) detect_edge_done_r_i_1 (.I0(pb_detect_edge_done_r[6]), .I1(pb_detect_edge_done_r[7]), .I2(pb_detect_edge_done_r[4]), .I3(pb_detect_edge_done_r[5]), .I4(detect_edge_done_r_i_2_n_0), .O(detect_edge_done_r_i_1_n_0)); LUT4 #( .INIT(16'h7FFF)) detect_edge_done_r_i_2 (.I0(pb_detect_edge_done_r[1]), .I1(pb_detect_edge_done_r[0]), .I2(pb_detect_edge_done_r[3]), .I3(pb_detect_edge_done_r[2]), .O(detect_edge_done_r_i_2_n_0)); FDRE detect_edge_done_r_reg (.C(CLK), .CE(1'b1), .D(detect_edge_done_r_i_1_n_0), .Q(detect_edge_done_r), .R(1'b0)); LUT6 #( .INIT(64'h0000000000005554)) \done_cnt[0]_i_1 (.I0(done_cnt[0]), .I1(done_cnt[1]), .I2(done_cnt[3]), .I3(done_cnt[2]), .I4(done_cnt1), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\done_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'hFFAAAAFE)) \done_cnt[1]_i_1 (.I0(done_cnt1), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[1]), .I4(done_cnt[0]), .O(\done_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000EE10)) \done_cnt[2]_i_1 (.I0(done_cnt[0]), .I1(done_cnt[1]), .I2(done_cnt[3]), .I3(done_cnt[2]), .I4(done_cnt1), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\done_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'hFAFAFAEA)) \done_cnt[3]_i_1 (.I0(done_cnt1), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[1]), .I4(done_cnt[0]), .O(\done_cnt[3]_i_1_n_0 )); LUT4 #( .INIT(16'h8F88)) \done_cnt[3]_i_2 (.I0(\done_cnt[3]_i_3_n_0 ), .I1(\done_cnt[3]_i_4_n_0 ), .I2(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I3(p_0_in539_in), .O(done_cnt1)); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT4 #( .INIT(16'h0004)) \done_cnt[3]_i_3 (.I0(done_cnt[1]), .I1(done_cnt[0]), .I2(done_cnt[3]), .I3(done_cnt[2]), .O(\done_cnt[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF7)) \done_cnt[3]_i_4 (.I0(cal1_state_r), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(out[4]), .I5(out[2]), .O(\done_cnt[3]_i_4_n_0 )); FDRE \done_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\done_cnt[0]_i_1_n_0 ), .Q(done_cnt[0]), .R(1'b0)); FDRE \done_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\done_cnt[1]_i_1_n_0 ), .Q(done_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \done_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\done_cnt[2]_i_1_n_0 ), .Q(done_cnt[2]), .R(1'b0)); FDRE \done_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\done_cnt[3]_i_1_n_0 ), .Q(done_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE dqs_po_dec_done_r1_reg (.C(CLK), .CE(1'b1), .D(dqs_po_dec_done), .Q(dqs_po_dec_done_r1), .R(1'b0)); FDRE dqs_po_dec_done_r2_reg (.C(CLK), .CE(1'b1), .D(dqs_po_dec_done_r1), .Q(dqs_po_dec_done_r2), .R(1'b0)); LUT5 #( .INIT(32'hFFFF22F2)) fine_dly_dec_done_r1_i_1 (.I0(fine_dly_dec_done_r1_i_2_n_0), .I1(fine_dly_dec_done_r1_i_3_n_0), .I2(dqs_po_dec_done_r2), .I3(\pi_rdval_cnt_reg[1]_0 ), .I4(fine_dly_dec_done_r1), .O(fine_dly_dec_done_r1_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT4 #( .INIT(16'h0010)) fine_dly_dec_done_r1_i_2 (.I0(pi_rdval_cnt[1]), .I1(pi_rdval_cnt[2]), .I2(pi_rdval_cnt[0]), .I3(pi_rdval_cnt[4]), .O(fine_dly_dec_done_r1_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT3 #( .INIT(8'hFB)) fine_dly_dec_done_r1_i_3 (.I0(pi_rdval_cnt[5]), .I1(pi_en_stg2_f_timing_reg_0), .I2(pi_rdval_cnt[3]), .O(fine_dly_dec_done_r1_i_3_n_0)); FDRE fine_dly_dec_done_r1_reg (.C(CLK), .CE(1'b1), .D(fine_dly_dec_done_r1_i_1_n_0), .Q(fine_dly_dec_done_r1), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE fine_dly_dec_done_r2_reg (.C(CLK), .CE(1'b1), .D(fine_dly_dec_done_r1), .Q(fine_dly_dec_done_r2), .R(1'b0)); LUT3 #( .INIT(8'h80)) \first_edge_taps_r[5]_i_1 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(out[2]), .O(\first_edge_taps_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888800202020)) \first_edge_taps_r[5]_i_2 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(\right_edge_taps_r_reg[0]_2 ), .I3(found_stable_eye_last_r), .I4(\right_edge_taps_r_reg[0]_0 ), .I5(out[2]), .O(\first_edge_taps_r[5]_i_2_n_0 )); LUT4 #( .INIT(16'h2000)) \first_edge_taps_r[5]_i_3 (.I0(out[4]), .I1(cal1_state_r), .I2(out[0]), .I3(out[1]), .O(\right_edge_taps_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair223" *) LUT3 #( .INIT(8'h08)) \first_edge_taps_r[5]_i_4 (.I0(detect_edge_done_r), .I1(found_first_edge_r_reg_0), .I2(tap_limit_cpt_r), .O(\right_edge_taps_r_reg[0]_2 )); FDRE \first_edge_taps_r_reg[0] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\first_edge_taps_r_reg_n_0_[0] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE \first_edge_taps_r_reg[1] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\first_edge_taps_r_reg_n_0_[1] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE \first_edge_taps_r_reg[2] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\first_edge_taps_r_reg_n_0_[2] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE \first_edge_taps_r_reg[3] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\first_edge_taps_r_reg_n_0_[3] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE \first_edge_taps_r_reg[4] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\first_edge_taps_r_reg_n_0_[4] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); FDRE \first_edge_taps_r_reg[5] (.C(CLK), .CE(\first_edge_taps_r[5]_i_2_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\first_edge_taps_r_reg_n_0_[5] ), .R(\first_edge_taps_r[5]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) found_edge_r_i_1 (.I0(found_edge_r_reg_1), .I1(found_edge_r_reg_2), .I2(found_edge_r_reg_0), .I3(found_edge_r_reg_3), .I4(found_edge_r_i_2_n_0), .O(found_edge_r_i_1_n_0)); LUT4 #( .INIT(16'hFFFE)) found_edge_r_i_2 (.I0(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .I1(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .I2(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .I3(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .O(found_edge_r_i_2_n_0)); FDRE found_edge_r_reg (.C(CLK), .CE(1'b1), .D(found_edge_r_i_1_n_0), .Q(found_first_edge_r_reg_0), .R(1'b0)); FDRE found_first_edge_r_reg (.C(CLK), .CE(1'b1), .D(found_edge_r_reg_4), .Q(\right_edge_taps_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE found_second_edge_r_reg (.C(CLK), .CE(1'b1), .D(found_stable_eye_last_r_reg_1), .Q(\cnt_idel_dec_cpt_r_reg[0]_0 ), .R(SR)); FDRE found_stable_eye_last_r_reg (.C(CLK), .CE(1'b1), .D(found_stable_eye_r_reg_0), .Q(found_stable_eye_last_r), .R(pb_detect_edge_setup)); LUT5 #( .INIT(32'h00008000)) found_stable_eye_r_i_1 (.I0(\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .I1(\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .I2(\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .I3(\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .I4(found_stable_eye_r_i_2_n_0), .O(found_stable_eye_r_i_1_n_0)); LUT4 #( .INIT(16'h7FFF)) found_stable_eye_r_i_2 (.I0(\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .I1(\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .I2(\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .I3(\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .O(found_stable_eye_r_i_2_n_0)); FDRE found_stable_eye_r_reg (.C(CLK), .CE(1'b1), .D(found_stable_eye_r_i_1_n_0), .Q(found_stable_eye_last_r_reg_0), .R(1'b0)); LUT3 #( .INIT(8'hB8)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_4 (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I1(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ), .I2(regl_dqs_cnt_r[0]), .O(pi_stg2_rdlvl_cnt[0])); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT3 #( .INIT(8'hB8)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_4 (.I0(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I1(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ), .I2(regl_dqs_cnt_r[1]), .O(pi_stg2_rdlvl_cnt[1])); LUT6 #( .INIT(64'hF0F4F0F4FFF4F0F4)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_3 (.I0(\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ), .I1(\prbs_dqs_cnt_r_reg[2] ), .I2(\po_stg2_wrcal_cnt_reg[2] ), .I3(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ), .I4(regl_dqs_cnt_r[2]), .I5(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT4 #( .INIT(16'hDFFF)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_5 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg), .I2(wrcal_done_reg), .I3(oclkdelay_calib_done_r_reg), .O(\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair207" *) LUT4 #( .INIT(16'h08FF)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_7 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(rdlvl_stg1_done_r1_reg), .I3(mpr_rdlvl_done_r1_reg_0), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF7)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_8 (.I0(cal1_state_r), .I1(out[1]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .I5(out[2]), .O(\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \gen_byte_sel_div1.calib_in_common_i_3 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(prbs_rdlvl_done_reg), .I3(rdlvl_stg1_done_r1_reg), .I4(wr_level_done_reg), .I5(mpr_rdlvl_done_r1_reg_0), .O(\gen_byte_sel_div1.calib_in_common_reg )); FDRE \gen_mux_rd[0].mux_rd_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_8 ), .Q(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_24 ), .Q(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_40 ), .Q(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_56 ), .Q(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_0 ), .Q(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_16 ), .Q(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_32 ), .Q(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[0].mux_rd_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_48 ), .Q(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_9 ), .Q(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_25 ), .Q(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_41 ), .Q(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_57 ), .Q(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_1 ), .Q(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_17 ), .Q(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_33 ), .Q(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[1].mux_rd_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_49 ), .Q(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_10 ), .Q(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_26 ), .Q(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_42 ), .Q(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_58 ), .Q(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_2 ), .Q(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_18 ), .Q(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_34 ), .Q(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[2].mux_rd_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_50 ), .Q(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_11 ), .Q(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_27 ), .Q(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_43 ), .Q(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_59 ), .Q(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_3 ), .Q(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_19 ), .Q(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_35 ), .Q(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[3].mux_rd_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_51 ), .Q(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_12 ), .Q(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_28 ), .Q(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_44 ), .Q(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_60 ), .Q(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_4 ), .Q(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_20 ), .Q(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_36 ), .Q(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[4].mux_rd_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_52 ), .Q(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_13 ), .Q(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_29 ), .Q(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_45 ), .Q(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_61 ), .Q(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_5 ), .Q(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_21 ), .Q(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_37 ), .Q(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[5].mux_rd_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_53 ), .Q(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_14 ), .Q(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_30 ), .Q(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_46 ), .Q(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_62 ), .Q(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_6 ), .Q(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_22 ), .Q(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_38 ), .Q(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[6].mux_rd_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_54 ), .Q(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_15 ), .Q(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_31 ), .Q(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_47 ), .Q(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_63 ), .Q(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_7 ), .Q(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_23 ), .Q(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_39 ), .Q(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd[7].mux_rd_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\rd_mux_sel_r_reg[1]_55 ), .Q(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ), .R(1'b0)); LUT3 #( .INIT(8'hA8)) \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r[0][0]_i_1 (.I0(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ), .I1(sr_valid_r1_reg_0), .I2(mpr_valid_r1_reg_0), .O(store_sr_r0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ), .R(1'b0)); LUT2 #( .INIT(4'hE)) \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r[0][0]_i_1 (.I0(sr_valid_r1_reg_0), .I1(mpr_valid_r1_reg_0), .O(store_sr_r1)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] (.C(CLK), .CE(store_sr_r0), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ), .R(1'b0)); FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] (.C(CLK), .CE(store_sr_r1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .O(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair161" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .O(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair162" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .O(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair163" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .O(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair164" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .O(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT1 #( .INIT(2'h1)) \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .O(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 )); FDRE \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.idel_pat0_data_match_r_i_1 (.I0(idel_pat0_match_rise2_and_r), .I1(idel_pat0_match_fall2_and_r), .I2(idel_pat0_match_fall3_and_r), .I3(idel_pat0_match_rise0_and_r), .I4(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ), .O(idel_pat0_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.idel_pat0_data_match_r_i_2 (.I0(idel_pat0_match_fall0_and_r), .I1(idel_pat0_match_fall1_and_r), .I2(idel_pat0_match_rise3_and_r), .I3(idel_pat0_match_rise1_and_r), .O(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_data_match_r_reg (.C(CLK), .CE(1'b1), .D(idel_pat0_data_match_r0__0), .Q(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall0_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ), .I4(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ), .Q(idel_pat0_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair220" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ), .I1(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ), .O(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ), .Q(idel_pat0_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.idel_pat1_data_match_r_i_1 (.I0(idel_pat1_match_rise2_and_r), .I1(idel_pat1_match_fall2_and_r), .I2(idel_pat1_match_fall3_and_r), .I3(idel_pat1_match_rise0_and_r), .I4(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ), .O(idel_pat1_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.idel_pat1_data_match_r_i_2 (.I0(idel_pat1_match_rise1_and_r), .I1(idel_pat1_match_fall1_and_r), .I2(idel_pat1_match_rise3_and_r), .I3(idel_pat1_match_fall0_and_r), .O(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_data_match_r_reg (.C(CLK), .CE(1'b1), .D(idel_pat1_data_match_r0__0), .Q(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair224" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ), .I1(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall0_and_r), .R(1'b0)); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ), .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ), .Q(idel_pat1_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise1_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .O(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ), .Q(idel_pat1_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat0_data_match_r_i_1 (.I0(pat0_match_fall2_and_r), .I1(pat0_match_rise2_and_r), .I2(pat0_match_fall3_and_r), .I3(pat0_match_rise0_and_r), .I4(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ), .O(pat0_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat0_data_match_r_i_2 (.I0(pat0_match_rise1_and_r), .I1(pat0_match_fall1_and_r), .I2(pat0_match_rise3_and_r), .I3(pat0_match_fall0_and_r), .O(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_data_match_r_reg (.C(CLK), .CE(1'b1), .D(pat0_data_match_r0__0), .Q(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair224" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat0_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat0_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ), .Q(pat0_match_fall0_and_r), .R(1'b0)); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat0_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ), .I1(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat0_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ), .Q(pat0_match_fall1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ), .I4(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ), .Q(pat0_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ), .Q(pat0_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ), .Q(pat0_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ), .Q(pat0_match_rise1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair220" *) LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat0_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ), .I1(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat0_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ), .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ), .Q(pat0_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat0_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ), .I4(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat0_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ), .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat0_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ), .Q(pat0_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat1_data_match_r_i_1 (.I0(pat1_match_rise2_and_r), .I1(pat1_match_fall1_and_r), .I2(pat1_match_fall3_and_r), .I3(pat1_match_rise0_and_r), .I4(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ), .O(pat1_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat1_data_match_r_i_2 (.I0(pat1_match_fall0_and_r), .I1(pat1_match_rise1_and_r), .I2(pat1_match_rise3_and_r), .I3(pat1_match_fall2_and_r), .O(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_data_match_r_reg (.C(CLK), .CE(1'b1), .D(pat1_data_match_r0__0), .Q(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat1_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat1_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ), .Q(pat1_match_fall0_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat1_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat1_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ), .Q(pat1_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat1_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ), .I4(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat1_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ), .Q(pat1_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat1_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ), .I4(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat1_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ), .Q(pat1_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat1_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat1_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ), .Q(pat1_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat1_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat1_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ), .Q(pat1_match_rise1_and_r), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pat_match_div4.pat1_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ), .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_pat_match_div4.pat1_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ), .Q(pat1_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat1_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ), .I4(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.pat1_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ), .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat1_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ), .Q(pat1_match_rise3_and_r), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] (.C(CLK), .CE(phy_rddata_en_1), .D(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ), .I4(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ), .O(p_488_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv (.C(CLK), .CE(1'b1), .D(p_488_out__0), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ), .R(1'b0)); LUT2 #( .INIT(4'h1)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 (.I0(mpr_valid_r2), .I1(sr_valid_r2), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ), .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ), .O(p_513_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ), .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ), .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv (.C(CLK), .CE(1'b1), .D(p_513_out__0), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 )); LUT3 #( .INIT(8'hFB)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2 (.I0(mpr_valid_r1), .I1(mpr_rdlvl_start_reg), .I2(mpr_rdlvl_done_r1_reg_0), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 )); LUT3 #( .INIT(8'hFE)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3 (.I0(mpr_valid_r1), .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ), .I2(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ), .I2(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ), .Q(p_1_in17_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 (.I0(p_2_in431_in), .I1(p_4_in433_in), .I2(p_0_in430_in), .I3(p_3_in432_in), .I4(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ), .O(p_438_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 (.I0(p_7_in436_in), .I1(p_5_in434_in), .I2(p_6_in435_in), .I3(p_1_in437_in), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv (.C(CLK), .CE(1'b1), .D(p_438_out__0), .Q(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in430_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ), .Q(p_0_in430_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in432_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ), .Q(p_3_in432_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in434_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ), .Q(p_5_in434_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in436_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ), .Q(p_7_in436_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in437_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ), .Q(p_1_in437_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in431_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ), .Q(p_2_in431_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in433_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ), .Q(p_4_in433_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in435_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ), .Q(p_6_in435_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ), .Q(p_0_in102_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 (.I0(p_2_in456_in), .I1(p_4_in458_in), .I2(p_0_in455_in), .I3(p_3_in457_in), .I4(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ), .O(p_463_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 (.I0(p_7_in461_in), .I1(p_6_in460_in), .I2(p_5_in459_in), .I3(p_1_in462_in), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv (.C(CLK), .CE(1'b1), .D(p_463_out__0), .Q(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in455_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ), .Q(p_0_in455_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in457_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ), .Q(p_3_in457_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in459_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ), .Q(p_5_in459_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in461_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ), .Q(p_7_in461_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in462_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ), .Q(p_1_in462_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in456_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ), .Q(p_2_in456_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in458_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ), .Q(p_4_in458_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in460_in), .I2(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ), .Q(p_6_in460_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ), .Q(p_1_in14_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 (.I0(p_3_in382_in), .I1(p_4_in383_in), .I2(p_2_in381_in), .I3(p_0_in380_in), .I4(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ), .O(p_388_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 (.I0(p_7_in386_in), .I1(p_5_in384_in), .I2(p_6_in385_in), .I3(p_1_in387_in), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv (.C(CLK), .CE(1'b1), .D(p_388_out__0), .Q(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in380_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ), .Q(p_0_in380_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in382_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ), .Q(p_3_in382_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in384_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ), .Q(p_5_in384_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in386_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ), .Q(p_7_in386_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in387_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ), .Q(p_1_in387_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in381_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ), .Q(p_2_in381_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in383_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ), .Q(p_4_in383_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in385_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ), .Q(p_6_in385_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ), .Q(p_0_in99_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 (.I0(p_2_in406_in), .I1(p_4_in408_in), .I2(p_0_in405_in), .I3(p_3_in407_in), .I4(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ), .O(p_413_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 (.I0(p_7_in411_in), .I1(p_5_in409_in), .I2(p_6_in410_in), .I3(p_1_in412_in), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv (.C(CLK), .CE(1'b1), .D(p_413_out__0), .Q(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in405_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ), .Q(p_0_in405_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in407_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ), .Q(p_3_in407_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in409_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ), .Q(p_5_in409_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in411_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ), .Q(p_7_in411_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in412_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ), .Q(p_1_in412_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in406_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ), .Q(p_2_in406_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in408_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ), .Q(p_4_in408_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair161" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in410_in), .I2(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ), .Q(p_6_in410_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ), .Q(p_1_in11_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 (.I0(p_3_in332_in), .I1(p_4_in333_in), .I2(p_2_in331_in), .I3(p_0_in330_in), .I4(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ), .O(p_338_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 (.I0(p_6_in335_in), .I1(p_5_in334_in), .I2(p_7_in336_in), .I3(p_1_in337_in), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv (.C(CLK), .CE(1'b1), .D(p_338_out__0), .Q(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in330_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ), .Q(p_0_in330_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in332_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ), .Q(p_3_in332_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in334_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ), .Q(p_5_in334_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in336_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ), .Q(p_7_in336_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in337_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ), .Q(p_1_in337_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in331_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ), .Q(p_2_in331_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in333_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ), .Q(p_4_in333_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in335_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ), .Q(p_6_in335_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ), .Q(p_0_in96_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 (.I0(p_4_in358_in), .I1(p_5_in359_in), .I2(p_3_in357_in), .I3(p_0_in355_in), .I4(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ), .O(p_363_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 (.I0(p_7_in361_in), .I1(p_6_in360_in), .I2(p_2_in356_in), .I3(p_1_in362_in), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv (.C(CLK), .CE(1'b1), .D(p_363_out__0), .Q(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in355_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ), .Q(p_0_in355_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in357_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ), .Q(p_3_in357_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in359_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ), .Q(p_5_in359_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in361_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ), .Q(p_7_in361_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in362_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ), .Q(p_1_in362_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in356_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ), .Q(p_2_in356_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in358_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ), .Q(p_4_in358_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair162" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in360_in), .I2(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ), .Q(p_6_in360_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ), .Q(p_1_in8_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 (.I0(p_4_in283_in), .I1(p_5_in284_in), .I2(p_3_in282_in), .I3(p_2_in281_in), .I4(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ), .O(p_288_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 (.I0(p_7_in286_in), .I1(p_6_in285_in), .I2(p_0_in280_in), .I3(p_1_in287_in), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv (.C(CLK), .CE(1'b1), .D(p_288_out__0), .Q(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in280_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ), .Q(p_0_in280_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in282_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ), .Q(p_3_in282_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in284_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ), .Q(p_5_in284_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in286_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ), .Q(p_7_in286_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in287_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ), .Q(p_1_in287_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in281_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ), .Q(p_2_in281_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in283_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ), .Q(p_4_in283_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in285_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ), .Q(p_6_in285_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ), .Q(p_0_in93_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 (.I0(p_4_in308_in), .I1(p_5_in309_in), .I2(p_3_in307_in), .I3(p_2_in306_in), .I4(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ), .O(p_313_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 (.I0(p_7_in311_in), .I1(p_6_in310_in), .I2(p_0_in305_in), .I3(p_1_in312_in), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv (.C(CLK), .CE(1'b1), .D(p_313_out__0), .Q(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in305_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ), .Q(p_0_in305_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in307_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ), .Q(p_3_in307_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in309_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ), .Q(p_5_in309_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in311_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ), .Q(p_7_in311_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in312_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ), .Q(p_1_in312_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in306_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ), .Q(p_2_in306_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in308_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ), .Q(p_4_in308_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair163" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in310_in), .I2(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ), .Q(p_6_in310_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ), .Q(p_1_in5_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 (.I0(p_4_in233_in), .I1(p_5_in234_in), .I2(p_3_in232_in), .I3(p_2_in231_in), .I4(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ), .O(p_238_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 (.I0(p_7_in236_in), .I1(p_6_in235_in), .I2(p_0_in230_in), .I3(p_1_in237_in), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv (.C(CLK), .CE(1'b1), .D(p_238_out__0), .Q(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in230_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ), .Q(p_0_in230_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in232_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ), .Q(p_3_in232_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in234_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ), .Q(p_5_in234_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in236_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ), .Q(p_7_in236_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in237_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ), .Q(p_1_in237_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in231_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ), .Q(p_2_in231_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in233_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ), .Q(p_4_in233_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in235_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ), .Q(p_6_in235_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ), .Q(p_0_in90_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 (.I0(p_4_in258_in), .I1(p_5_in259_in), .I2(p_3_in257_in), .I3(p_2_in256_in), .I4(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ), .O(p_263_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 (.I0(p_7_in261_in), .I1(p_6_in260_in), .I2(p_0_in255_in), .I3(p_1_in262_in), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv (.C(CLK), .CE(1'b1), .D(p_263_out__0), .Q(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in255_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ), .Q(p_0_in255_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in257_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ), .Q(p_3_in257_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in259_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ), .Q(p_5_in259_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in261_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ), .Q(p_7_in261_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in262_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ), .Q(p_1_in262_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in256_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ), .Q(p_2_in256_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in258_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ), .Q(p_4_in258_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair164" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in260_in), .I2(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ), .Q(p_6_in260_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ), .Q(p_1_in2_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 (.I0(p_4_in183_in), .I1(p_5_in184_in), .I2(p_3_in182_in), .I3(p_2_in181_in), .I4(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ), .O(p_188_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 (.I0(p_7_in186_in), .I1(p_6_in185_in), .I2(p_0_in180_in), .I3(p_1_in187_in), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv (.C(CLK), .CE(1'b1), .D(p_188_out__0), .Q(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in180_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ), .Q(p_0_in180_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in182_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ), .Q(p_3_in182_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in184_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ), .Q(p_5_in184_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in186_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ), .Q(p_7_in186_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in187_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ), .Q(p_1_in187_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in181_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ), .Q(p_2_in181_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in183_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ), .Q(p_4_in183_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in185_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ), .Q(p_6_in185_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ), .Q(p_0_in87_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 (.I0(p_4_in208_in), .I1(p_5_in209_in), .I2(p_3_in207_in), .I3(p_2_in206_in), .I4(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ), .O(p_213_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 (.I0(p_7_in211_in), .I1(p_6_in210_in), .I2(p_0_in205_in), .I3(p_1_in212_in), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv (.C(CLK), .CE(1'b1), .D(p_213_out__0), .Q(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in205_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ), .Q(p_0_in205_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in207_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ), .Q(p_3_in207_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in209_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ), .Q(p_5_in209_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in211_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ), .Q(p_7_in211_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in212_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ), .Q(p_1_in212_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in206_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ), .Q(p_2_in206_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in208_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ), .Q(p_4_in208_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in210_in), .I2(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ), .Q(p_6_in210_in), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ), .I1(p_5_in136_in), .I2(p_3_in135_in), .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ), .I4(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ), .O(p_137_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 (.I0(p_7_in), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ), .I2(p_0_in134_in), .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv (.C(CLK), .CE(1'b1), .D(p_137_out__0), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in134_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ), .Q(p_0_in134_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in135_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ), .Q(p_3_in135_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in136_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ), .Q(p_5_in136_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ), .Q(p_7_in), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ), .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ), .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ), .Q(p_0_in84_in), .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF7FFF)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 (.I0(p_4_in158_in), .I1(p_5_in159_in), .I2(p_3_in157_in), .I3(p_2_in156_in), .I4(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ), .O(p_163_out__0)); LUT4 #( .INIT(16'h7FFF)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 (.I0(p_7_in161_in), .I1(p_6_in160_in), .I2(p_0_in155_in), .I3(p_1_in162_in), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 )); FDRE #( .INIT(1'b1)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv (.C(CLK), .CE(1'b1), .D(p_163_out__0), .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_0_in155_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ), .Q(p_0_in155_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_3_in157_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ), .Q(p_3_in157_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_5_in159_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ), .Q(p_5_in159_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_7_in161_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ), .Q(p_7_in161_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_1_in162_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ), .Q(p_1_in162_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_2_in156_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ), .Q(p_2_in156_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_4_in158_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ), .Q(p_4_in158_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT5 #( .INIT(32'hF44F4444)) \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ), .I1(p_6_in160_in), .I2(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ), .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ), .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ), .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 )); FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ), .Q(p_6_in160_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair216" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair216" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .O(p_0_in__2[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[0]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I5(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .O(pb_cnt_eye_size_r)); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .O(p_0_in__2[4])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ), .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .I2(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[0]), .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 )); FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[0]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[1]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[2]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[3]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] (.C(CLK), .CE(pb_cnt_eye_size_r), .D(p_0_in__2[4]), .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 )); FDRE \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ), .Q(pb_detect_edge_done_r[0]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[0].pb_found_edge_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ), .Q(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ), .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .O(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3 (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]), .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]), .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]), .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]), .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]), .O(\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4 (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ), .O(pb_found_stable_eye_r76_out)); FDRE \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ), .Q(\gen_track_left_edge[0].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[0]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFEFBFFFFFEF7F)) \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2 (.I0(out[3]), .I1(out[2]), .I2(out[0]), .I3(out[4]), .I4(cal1_state_r), .I5(out[1]), .O(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 )); FDRE \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ), .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .O(p_0_in__3[0])); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .O(p_0_in__3[1])); (* SOFT_HLUTNM = "soft_lutpair213" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .O(p_0_in__3[2])); (* SOFT_HLUTNM = "soft_lutpair213" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .O(p_0_in__3[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[1]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I5(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .O(p_0_in__3[4])); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 (.I0(p_1_in17_in), .I1(p_0_in102_in), .I2(found_edge_r_reg_0), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in16_in), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[1]), .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 )); FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[0]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[1]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[2]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[3]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] (.C(CLK), .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ), .D(p_0_in__3[4]), .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 )); FDRE \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_6), .Q(pb_detect_edge_done_r[1]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[1].pb_found_edge_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ), .Q(found_edge_r_reg_0), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2 (.I0(p_0_in102_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in17_in), .I3(p_0_in16_in), .O(\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3 (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]), .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]), .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]), .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]), .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]), .O(\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4 (.I0(p_0_in16_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_0), .O(pb_found_stable_eye_r72_out)); FDRE \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ), .Q(\gen_track_left_edge[1].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 (.I0(p_0_in16_in), .I1(p_0_in102_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[1]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 )); FDRE \gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ), .Q(p_0_in16_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .O(p_0_in__4[0])); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .O(p_0_in__4[1])); (* SOFT_HLUTNM = "soft_lutpair210" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .O(p_0_in__4[2])); (* SOFT_HLUTNM = "soft_lutpair210" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .O(p_0_in__4[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[2]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I5(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .O(p_0_in__4[4])); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 (.I0(p_1_in14_in), .I1(p_0_in99_in), .I2(found_edge_r_reg_1), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in13_in), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[2]), .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 )); FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[0]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[1]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[2]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[3]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] (.C(CLK), .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ), .D(p_0_in__4[4]), .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 )); FDRE \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_5), .Q(pb_detect_edge_done_r[2]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[2].pb_found_edge_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ), .Q(found_edge_r_reg_1), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2 (.I0(p_0_in99_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in14_in), .I3(p_0_in13_in), .O(\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3 (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]), .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]), .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]), .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]), .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]), .O(\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4 (.I0(p_0_in13_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_1), .O(pb_found_stable_eye_r68_out)); FDRE \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ), .Q(\gen_track_left_edge[2].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 (.I0(p_0_in13_in), .I1(p_0_in99_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[2]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 )); FDRE \gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ), .Q(p_0_in13_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .O(p_0_in__5[0])); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .O(p_0_in__5[1])); (* SOFT_HLUTNM = "soft_lutpair212" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .O(p_0_in__5[2])); (* SOFT_HLUTNM = "soft_lutpair212" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .O(p_0_in__5[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[3]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I5(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .O(p_0_in__5[4])); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 (.I0(p_1_in11_in), .I1(p_0_in96_in), .I2(found_edge_r_reg_2), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in10_in), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[3]), .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 )); FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[0]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[1]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[2]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[3]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] (.C(CLK), .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ), .D(p_0_in__5[4]), .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 )); FDRE \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_4), .Q(pb_detect_edge_done_r[3]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[3].pb_found_edge_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ), .Q(found_edge_r_reg_2), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2 (.I0(p_0_in96_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in11_in), .I3(p_0_in10_in), .O(\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3 (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]), .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]), .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]), .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]), .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]), .O(\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4 (.I0(p_0_in10_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_2), .O(pb_found_stable_eye_r64_out)); FDRE \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ), .Q(\gen_track_left_edge[3].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 (.I0(p_0_in10_in), .I1(p_0_in96_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[3]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 )); FDRE \gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ), .Q(p_0_in10_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .O(p_0_in__6[0])); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .O(p_0_in__6[1])); (* SOFT_HLUTNM = "soft_lutpair217" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .O(p_0_in__6[2])); (* SOFT_HLUTNM = "soft_lutpair217" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .O(p_0_in__6[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[4]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I5(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .O(p_0_in__6[4])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 (.I0(p_1_in8_in), .I1(p_0_in93_in), .I2(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in7_in), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[4]), .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 )); FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[0]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[1]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[2]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[3]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] (.C(CLK), .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ), .D(p_0_in__6[4]), .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 )); FDRE \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_3), .Q(pb_detect_edge_done_r[4]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[4].pb_found_edge_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ), .Q(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2 (.I0(p_0_in93_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in8_in), .I3(p_0_in7_in), .O(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3 (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]), .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]), .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]), .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]), .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]), .O(\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4 (.I0(p_0_in7_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ), .O(pb_found_stable_eye_r60_out)); FDRE \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ), .Q(\gen_track_left_edge[4].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 (.I0(p_0_in7_in), .I1(p_0_in93_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[4]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 )); FDRE \gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ), .Q(p_0_in7_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .O(p_0_in__7[0])); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .O(p_0_in__7[1])); (* SOFT_HLUTNM = "soft_lutpair215" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .O(p_0_in__7[2])); (* SOFT_HLUTNM = "soft_lutpair215" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .O(p_0_in__7[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[5]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I5(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .O(p_0_in__7[4])); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 (.I0(p_1_in5_in), .I1(p_0_in90_in), .I2(found_edge_r_reg_3), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in4_in), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair222" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[5]), .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 )); FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[0]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[1]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[2]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[3]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] (.C(CLK), .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ), .D(p_0_in__7[4]), .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 )); FDRE \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_2), .Q(pb_detect_edge_done_r[5]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[5].pb_found_edge_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ), .Q(found_edge_r_reg_3), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2 (.I0(p_0_in90_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in5_in), .I3(p_0_in4_in), .O(\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3 (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]), .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]), .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]), .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]), .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]), .O(\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair219" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4 (.I0(p_0_in4_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(found_edge_r_reg_3), .O(pb_found_stable_eye_r56_out)); FDRE \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ), .Q(\gen_track_left_edge[5].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 (.I0(p_0_in4_in), .I1(p_0_in90_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[5]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 )); FDRE \gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ), .Q(p_0_in4_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .O(p_0_in__8[0])); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .O(p_0_in__8[1])); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .O(p_0_in__8[2])); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .O(p_0_in__8[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[6]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I5(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .O(p_0_in__8[4])); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 (.I0(p_1_in2_in), .I1(p_0_in87_in), .I2(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in1_in), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair219" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[6]), .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 )); FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[0]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[1]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[2]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[3]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] (.C(CLK), .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ), .D(p_0_in__8[4]), .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 )); FDRE \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_1), .Q(pb_detect_edge_done_r[6]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[6].pb_found_edge_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ), .Q(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2 (.I0(p_0_in87_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(p_1_in2_in), .I3(p_0_in1_in), .O(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 )); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3 (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]), .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]), .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]), .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]), .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]), .O(\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 )); (* SOFT_HLUTNM = "soft_lutpair222" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4 (.I0(p_0_in1_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ), .O(pb_found_stable_eye_r52_out)); FDRE \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ), .Q(\gen_track_left_edge[6].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 (.I0(p_0_in1_in), .I1(p_0_in87_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[6]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 )); FDRE \gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ), .Q(p_0_in1_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT1 #( .INIT(2'h1)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .O(p_0_in__9[0])); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT2 #( .INIT(4'h6)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .O(p_0_in__9[1])); (* SOFT_HLUTNM = "soft_lutpair204" *) LUT3 #( .INIT(8'h6A)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .O(p_0_in__9[2])); (* SOFT_HLUTNM = "soft_lutpair204" *) LUT4 #( .INIT(16'h6AAA)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .O(p_0_in__9[3])); LUT4 #( .INIT(16'hAAAB)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 (.I0(pb_detect_edge_setup), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ), .I2(pb_detect_edge_done_r[7]), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); LUT6 #( .INIT(64'h8AAAAAAAAAAAAAAA)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I5(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h6AAAAAAA)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .O(p_0_in__9[4])); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT5 #( .INIT(32'h00000F11)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ), .I1(p_0_in84_in), .I2(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I4(p_0_in), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair218" *) LUT3 #( .INIT(8'h02)) \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I2(pb_detect_edge_done_r[7]), .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 )); FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[0]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[1]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[2]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[3]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] (.C(CLK), .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ), .D(p_0_in__9[4]), .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000400040008)) \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 (.I0(out[3]), .I1(out[2]), .I2(cal1_state_r), .I3(out[4]), .I4(out[0]), .I5(out[1]), .O(pb_detect_edge_setup)); FDRE \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_reg_0), .Q(pb_detect_edge_done_r[7]), .R(pb_detect_edge_setup)); FDRE \gen_track_left_edge[7].pb_found_edge_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ), .Q(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .R(pb_detect_edge_setup)); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'h0001)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2 (.I0(p_0_in84_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ), .I3(p_0_in), .O(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h00008000)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3 (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]), .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]), .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]), .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]), .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]), .O(\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 )); (* SOFT_HLUTNM = "soft_lutpair218" *) LUT3 #( .INIT(8'h04)) \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4 (.I0(p_0_in), .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I2(\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ), .O(\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 )); FDRE \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ), .Q(\gen_track_left_edge[7].pb_found_stable_eye_r_reg ), .R(pb_detect_edge_setup)); LUT6 #( .INIT(64'h00000000AAAAAA0E)) \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 (.I0(p_0_in), .I1(p_0_in84_in), .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ), .I4(pb_detect_edge_done_r[7]), .I5(pb_detect_edge_setup), .O(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 )); FDRE \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ), .Q(p_0_in), .R(1'b0)); LUT4 #( .INIT(16'h0008)) idel_adj_inc_i_2 (.I0(out[4]), .I1(out[0]), .I2(cal1_state_r), .I3(out[3]), .O(idel_adj_inc_reg_1)); (* SOFT_HLUTNM = "soft_lutpair223" *) LUT3 #( .INIT(8'hA8)) idel_adj_inc_i_3 (.I0(detect_edge_done_r), .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .O(idel_adj_inc_reg_2)); FDRE idel_adj_inc_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[2]_0 ), .Q(idel_adj_inc_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT4 #( .INIT(16'h4373)) \idel_dec_cnt[0]_i_1 (.I0(idel_dec_cnt__0[0]), .I1(out[1]), .I2(out[2]), .I3(\idel_dec_cnt[0]_i_2_n_0 ), .O(idel_dec_cnt)); LUT6 #( .INIT(64'h505F3030505F3F3F)) \idel_dec_cnt[0]_i_2 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ), .O(\idel_dec_cnt[0]_i_2_n_0 )); LUT5 #( .INIT(32'h0000E22E)) \idel_dec_cnt[1]_i_1 (.I0(idelay_tap_cnt_r[1]), .I1(out[4]), .I2(idel_dec_cnt__0[0]), .I3(idel_dec_cnt__0[1]), .I4(out[0]), .O(\idel_dec_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000EEE2222E)) \idel_dec_cnt[2]_i_1 (.I0(idelay_tap_cnt_r[2]), .I1(out[4]), .I2(idel_dec_cnt__0[1]), .I3(idel_dec_cnt__0[0]), .I4(idel_dec_cnt__0[2]), .I5(out[0]), .O(\idel_dec_cnt[2]_i_1_n_0 )); LUT5 #( .INIT(32'h00002EE2)) \idel_dec_cnt[3]_i_1 (.I0(idelay_tap_cnt_r[3]), .I1(out[4]), .I2(\idel_dec_cnt[3]_i_2_n_0 ), .I3(idel_dec_cnt__0[3]), .I4(out[0]), .O(\idel_dec_cnt[3]_i_1_n_0 )); LUT3 #( .INIT(8'h01)) \idel_dec_cnt[3]_i_2 (.I0(idel_dec_cnt__0[0]), .I1(idel_dec_cnt__0[1]), .I2(idel_dec_cnt__0[2]), .O(\idel_dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h1000001000404000)) \idel_dec_cnt[4]_i_1 (.I0(\idel_dec_cnt_reg[0]_0 ), .I1(out[0]), .I2(\idel_dec_cnt[4]_i_4_n_0 ), .I3(out[1]), .I4(out[4]), .I5(out[2]), .O(\idel_dec_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'h00002EE2)) \idel_dec_cnt[4]_i_2 (.I0(idelay_tap_cnt_r[4]), .I1(out[4]), .I2(\idel_dec_cnt[4]_i_5_n_0 ), .I3(idel_dec_cnt__0[4]), .I4(out[0]), .O(\idel_dec_cnt[4]_i_2_n_0 )); LUT2 #( .INIT(4'hE)) \idel_dec_cnt[4]_i_3 (.I0(out[3]), .I1(cal1_state_r), .O(\idel_dec_cnt_reg[0]_0 )); LUT6 #( .INIT(64'hB888FFFFB8880000)) \idel_dec_cnt[4]_i_4 (.I0(cal1_state_r2), .I1(out[4]), .I2(mpr_rd_rise0_prev_r_reg_0), .I3(idel_mpr_pat_detect_r), .I4(out[1]), .I5(\idel_dec_cnt[4]_i_7_n_0 ), .O(\idel_dec_cnt[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT4 #( .INIT(16'h0001)) \idel_dec_cnt[4]_i_5 (.I0(idel_dec_cnt__0[2]), .I1(idel_dec_cnt__0[1]), .I2(idel_dec_cnt__0[0]), .I3(idel_dec_cnt__0[3]), .O(\idel_dec_cnt[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT5 #( .INIT(32'hFFFFFFFE)) \idel_dec_cnt[4]_i_6 (.I0(idel_dec_cnt__0[4]), .I1(idel_dec_cnt__0[3]), .I2(idel_dec_cnt__0[0]), .I3(idel_dec_cnt__0[1]), .I4(idel_dec_cnt__0[2]), .O(cal1_state_r2)); LUT6 #( .INIT(64'hA800A800A8FFA800)) \idel_dec_cnt[4]_i_7 (.I0(detect_edge_done_r), .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ), .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ), .I3(out[4]), .I4(stable_idel_cnt22_in), .I5(\idel_dec_cnt[4]_i_8_n_0 ), .O(\idel_dec_cnt[4]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFB)) \idel_dec_cnt[4]_i_8 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[5] ), .I1(mpr_dec_cpt_r_reg_0), .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ), .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ), .I4(\cnt_idel_dec_cpt_r_reg_n_0_[4] ), .I5(\idel_dec_cnt[4]_i_9_n_0 ), .O(\idel_dec_cnt[4]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair206" *) LUT2 #( .INIT(4'hB)) \idel_dec_cnt[4]_i_9 (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[1] ), .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ), .O(\idel_dec_cnt[4]_i_9_n_0 )); FDRE \idel_dec_cnt_reg[0] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(idel_dec_cnt), .Q(idel_dec_cnt__0[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idel_dec_cnt_reg[1] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[1]_i_1_n_0 ), .Q(idel_dec_cnt__0[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idel_dec_cnt_reg[2] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[2]_i_1_n_0 ), .Q(idel_dec_cnt__0[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idel_dec_cnt_reg[3] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[3]_i_1_n_0 ), .Q(idel_dec_cnt__0[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idel_dec_cnt_reg[4] (.C(CLK), .CE(\idel_dec_cnt[4]_i_1_n_0 ), .D(\idel_dec_cnt[4]_i_2_n_0 ), .Q(idel_dec_cnt__0[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE idel_pat_detect_valid_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_0 ), .Q(mpr_rd_rise0_prev_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'h04)) \idelay_tap_cnt_r[0][0][0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(idelay_ce_int), .I2(idelay_tap_cnt_slice_r[0]), .O(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT5 #( .INIT(32'h04404004)) \idelay_tap_cnt_r[0][0][1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(idelay_ce_int), .I2(idelay_tap_cnt_slice_r[0]), .I3(idelay_tap_cnt_slice_r[1]), .I4(idelay_inc_int), .O(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h0444400044400004)) \idelay_tap_cnt_r[0][0][2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(idelay_ce_int), .I2(idelay_inc_int), .I3(idelay_tap_cnt_slice_r[0]), .I4(idelay_tap_cnt_slice_r[2]), .I5(idelay_tap_cnt_slice_r[1]), .O(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h28A0A0A0A0A0A082)) \idelay_tap_cnt_r[0][0][3]_i_1 (.I0(\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ), .I1(idelay_tap_cnt_slice_r[2]), .I2(idelay_tap_cnt_slice_r[3]), .I3(idelay_tap_cnt_slice_r[0]), .I4(idelay_inc_int), .I5(idelay_tap_cnt_slice_r[1]), .O(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT2 #( .INIT(4'h2)) \idelay_tap_cnt_r[0][0][3]_i_2 (.I0(idelay_ce_int), .I1(rstdiv0_sync_r1_reg_rep__23), .O(\idelay_tap_cnt_r[0][0][3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF111111F1)) \idelay_tap_cnt_r[0][0][4]_i_1 (.I0(\po_stg2_wrcal_cnt_reg[0] ), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ), .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT3 #( .INIT(8'h04)) \idelay_tap_cnt_r[0][0][4]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(idelay_ce_int), .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ), .O(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair221" *) LUT3 #( .INIT(8'h10)) \idelay_tap_cnt_r[0][0][4]_i_4 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(idelay_ce_int), .O(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 )); LUT6 #( .INIT(64'h9555555555555556)) \idelay_tap_cnt_r[0][0][4]_i_5 (.I0(idelay_tap_cnt_slice_r[4]), .I1(idelay_tap_cnt_slice_r[0]), .I2(idelay_inc_int), .I3(idelay_tap_cnt_slice_r[1]), .I4(idelay_tap_cnt_slice_r[3]), .I5(idelay_tap_cnt_slice_r[2]), .O(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF1111F111)) \idelay_tap_cnt_r[0][1][4]_i_1 (.I0(cal1_dq_idel_ce_reg_0), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ), .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF4F444444)) \idelay_tap_cnt_r[0][2][4]_i_1 (.I0(\po_stg2_wrcal_cnt_reg[0] ), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF4444444)) \idelay_tap_cnt_r[0][3][4]_i_1 (.I0(cal1_dq_idel_ce_reg_0), .I1(\po_stg2_wrcal_cnt_reg[1] ), .I2(idelay_ce_int), .I3(\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ), .I4(cal1_cnt_cpt_r1), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair221" *) LUT2 #( .INIT(4'h1)) \idelay_tap_cnt_r[0][3][4]_i_2 (.I0(\rnk_cnt_r_reg_n_0_[1] ), .I1(\rnk_cnt_r_reg_n_0_[0] ), .O(\idelay_tap_cnt_r[0][3][4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT2 #( .INIT(4'h8)) \idelay_tap_cnt_r[0][3][4]_i_3 (.I0(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ), .O(cal1_cnt_cpt_r1)); FDRE \idelay_tap_cnt_r_reg[0][0][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][0][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][0][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][0][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][0][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][1][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][1][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][1][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][1][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][1][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][2][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][2][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][2][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][2][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][2][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][3][0] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][3][1] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][3][2] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][3][3] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ), .R(1'b0)); FDRE \idelay_tap_cnt_r_reg[0][3][4] (.C(CLK), .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ), .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ), .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ), .R(1'b0)); LUT6 #( .INIT(64'hFFE2CCE233E200E2)) \idelay_tap_cnt_slice_r[0]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ), .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I2(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ), .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I4(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ), .O(idelay_tap_cnt_r[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[1]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ), .O(idelay_tap_cnt_r[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[2]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ), .O(idelay_tap_cnt_r[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[3]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ), .O(idelay_tap_cnt_r[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \idelay_tap_cnt_slice_r[4]_i_1 (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ), .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ), .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I3(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ), .O(idelay_tap_cnt_r[4])); FDRE \idelay_tap_cnt_slice_r_reg[0] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[0]), .Q(idelay_tap_cnt_slice_r[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idelay_tap_cnt_slice_r_reg[1] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[1]), .Q(idelay_tap_cnt_slice_r[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idelay_tap_cnt_slice_r_reg[2] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[2]), .Q(idelay_tap_cnt_slice_r[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idelay_tap_cnt_slice_r_reg[3] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[3]), .Q(idelay_tap_cnt_slice_r[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \idelay_tap_cnt_slice_r_reg[4] (.C(CLK), .CE(1'b1), .D(idelay_tap_cnt_r[4]), .Q(idelay_tap_cnt_slice_r[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT3 #( .INIT(8'h02)) idelay_tap_limit_r_i_1 (.I0(idelay_tap_limit_r_i_2_n_0), .I1(new_cnt_cpt_r_reg_n_0), .I2(rstdiv0_sync_r1_reg_rep__23), .O(idelay_tap_limit_r_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40000000)) idelay_tap_limit_r_i_2 (.I0(\idel_dec_cnt[0]_i_2_n_0 ), .I1(idelay_tap_cnt_r[3]), .I2(idelay_tap_cnt_r[4]), .I3(idelay_tap_cnt_r[2]), .I4(idelay_tap_cnt_r[1]), .I5(idelay_tap_limit_r_reg_n_0), .O(idelay_tap_limit_r_i_2_n_0)); FDRE idelay_tap_limit_r_reg (.C(CLK), .CE(1'b1), .D(idelay_tap_limit_r_i_1_n_0), .Q(idelay_tap_limit_r_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair207" *) LUT3 #( .INIT(8'h54)) \init_state_r[0]_i_37 (.I0(oclkdelay_calib_done_r_reg), .I1(mpr_last_byte_done), .I2(mpr_rdlvl_done_r1_reg_0), .O(\init_state_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000AAFE0000)) \init_state_r[0]_i_38 (.I0(\init_state_r[0]_i_48_n_0 ), .I1(wrlvl_byte_redo), .I2(wrlvl_final_mux), .I3(\init_state_r[0]_i_49_n_0 ), .I4(mem_init_done_r), .I5(prbs_rdlvl_done_reg_rep_0), .O(\init_state_r_reg[0]_2 )); LUT5 #( .INIT(32'h00010000)) \init_state_r[0]_i_44 (.I0(\init_state_r_reg[1]_0 [1]), .I1(mpr_rdlvl_done_r1_reg_0), .I2(mpr_rnk_done), .I3(rdlvl_prech_req), .I4(\init_state_r_reg[1]_0 [0]), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h55FF55FF51FF51F1)) \init_state_r[0]_i_47 (.I0(\init_state_r[0]_i_53_n_0 ), .I1(oclkdelay_calib_done_r_reg), .I2(\init_state_r[0]_i_54_n_0 ), .I3(prbs_rdlvl_done_reg_rep), .I4(rdlvl_stg1_done_r1_reg), .I5(\init_state_r_reg[5] ), .O(\init_state_r_reg[0]_3 )); LUT6 #( .INIT(64'hFFFFFFFF001F0000)) \init_state_r[0]_i_48 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_last_byte_done), .I2(oclkdelay_calib_done_r_reg), .I3(\init_state_r[0]_i_53_n_0 ), .I4(wrlvl_final_mux_reg), .I5(prbs_rdlvl_done_reg_rep_1), .O(\init_state_r[0]_i_48_n_0 )); LUT6 #( .INIT(64'hFF00FF000000FF54)) \init_state_r[0]_i_49 (.I0(prbs_last_byte_done_r), .I1(mpr_last_byte_done), .I2(mpr_rdlvl_done_r1_reg_0), .I3(prbs_rdlvl_done_reg_rep), .I4(wrcal_done_reg), .I5(rdlvl_stg1_done_r1_reg), .O(\init_state_r[0]_i_49_n_0 )); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT3 #( .INIT(8'h01)) \init_state_r[0]_i_52 (.I0(rdlvl_stg1_done_r1_reg), .I1(rdlvl_last_byte_done), .I2(\one_rank.stg1_wr_done_reg ), .O(\init_state_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair214" *) LUT3 #( .INIT(8'h08)) \init_state_r[0]_i_53 (.I0(rdlvl_stg1_done_r1_reg), .I1(oclkdelay_center_calib_done_r_reg), .I2(wrlvl_done_r1), .O(\init_state_r[0]_i_53_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT3 #( .INIT(8'h4F)) \init_state_r[0]_i_54 (.I0(rdlvl_stg1_done_r1_reg), .I1(wrcal_done_reg), .I2(dqs_found_done_r_reg), .O(\init_state_r[0]_i_54_n_0 )); (* SOFT_HLUTNM = "soft_lutpair214" *) LUT4 #( .INIT(16'h0080)) \init_state_r[0]_i_57 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(oclkdelay_center_calib_done_r_reg), .I3(wrlvl_done_r1), .O(\init_state_r_reg[0]_4 )); LUT6 #( .INIT(64'h00FFFE0000000000)) \init_state_r[1]_i_38 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_rnk_done), .I2(rdlvl_prech_req), .I3(\init_state_r_reg[1]_0 [0]), .I4(\init_state_r_reg[1]_0 [1]), .I5(\init_state_r_reg[3]_0 ), .O(\init_state_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT5 #( .INIT(32'h7FFFFFFF)) \init_state_r[2]_i_13 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(wrlvl_done_r1), .I3(dqs_found_done_r_reg), .I4(wrcal_done_reg), .O(\init_state_r_reg[2]_2 )); LUT6 #( .INIT(64'hD0FFD0FFD0FFD0D0)) \init_state_r[2]_i_15 (.I0(wrlvl_done_r1_reg), .I1(\init_state_r_reg[2]_0 ), .I2(\init_state_r_reg[2]_1 ), .I3(wrlvl_done_r1_reg_0), .I4(cnt_init_af_done_r), .I5(dqs_found_done_r_reg_0), .O(\init_state_r_reg[2] )); LUT6 #( .INIT(64'hFFFFFFFF74FFFFFF)) \init_state_r[2]_i_28 (.I0(prbs_rdlvl_done_reg_rep), .I1(rdlvl_stg1_done_r1_reg), .I2(wrcal_done_reg), .I3(dqs_found_done_r_reg), .I4(oclkdelay_calib_done_r_reg), .I5(\init_state_r_reg[5] ), .O(\init_state_r_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair211" *) LUT4 #( .INIT(16'hAAFE)) \init_state_r[3]_i_8 (.I0(wrlvl_byte_redo_reg), .I1(mpr_rdlvl_done_r1_reg_0), .I2(mpr_last_byte_done), .I3(oclkdelay_calib_done_r_reg), .O(\init_state_r_reg[2]_1 )); LUT6 #( .INIT(64'h4040004000000040)) \init_state_r[3]_i_9 (.I0(\num_refresh_reg[1] ), .I1(\init_state_r_reg[5] ), .I2(dqs_found_done_r_reg), .I3(wrcal_done_reg), .I4(rdlvl_stg1_done_r1_reg), .I5(prbs_rdlvl_done_reg_rep), .O(\init_state_r_reg[3] )); LUT6 #( .INIT(64'hB010B010B0100000)) \init_state_r[4]_i_25 (.I0(rdlvl_stg1_done_r1_reg), .I1(wrcal_done_reg), .I2(dqs_found_done_r_reg), .I3(prbs_rdlvl_done_reg_rep), .I4(mpr_last_byte_done), .I5(mpr_rdlvl_done_r1_reg_0), .O(\init_state_r_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair211" *) LUT2 #( .INIT(4'h1)) \init_state_r[5]_i_30 (.I0(mpr_rdlvl_done_r1_reg_0), .I1(mpr_last_byte_done), .O(\init_state_r_reg[5] )); LUT5 #( .INIT(32'h00000002)) \mpr_4to1.idel_mpr_pat_detect_r_i_1 (.I0(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ), .I1(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ), .I2(inhibit_edge_detect_r), .I3(p_1_in26_in), .I4(inhibit_edge_detect_r0), .O(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00100000)) \mpr_4to1.idel_mpr_pat_detect_r_i_2 (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ), .I1(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .I4(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ), .I5(idel_mpr_pat_detect_r), .O(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 )); LUT4 #( .INIT(16'h0008)) \mpr_4to1.idel_mpr_pat_detect_r_i_3 (.I0(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ), .I1(mpr_rd_rise0_prev_r_reg_0), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .O(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000100)) \mpr_4to1.idel_mpr_pat_detect_r_i_4 (.I0(out[3]), .I1(cal1_state_r), .I2(out[4]), .I3(out[0]), .I4(out[2]), .I5(out[1]), .O(p_1_in26_in)); FDRE \mpr_4to1.idel_mpr_pat_detect_r_reg (.C(CLK), .CE(1'b1), .D(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ), .Q(idel_mpr_pat_detect_r), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFB00)) \mpr_4to1.inhibit_edge_detect_r_i_1 (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ), .I1(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ), .I2(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ), .I3(inhibit_edge_detect_r), .I4(inhibit_edge_detect_r0), .O(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \mpr_4to1.inhibit_edge_detect_r_i_2 (.I0(mpr_rd_rise2_prev_r), .I1(mpr_rd_rise1_prev_r), .I2(mpr_rd_rise3_prev_r), .I3(mpr_rd_fall1_prev_r), .I4(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ), .O(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000020000)) \mpr_4to1.inhibit_edge_detect_r_i_3 (.I0(out[1]), .I1(out[3]), .I2(cal1_state_r), .I3(out[4]), .I4(out[0]), .I5(out[2]), .O(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT4 #( .INIT(16'h0001)) \mpr_4to1.inhibit_edge_detect_r_i_4 (.I0(idelay_tap_cnt_r[1]), .I1(idelay_tap_cnt_r[2]), .I2(idelay_tap_cnt_r[3]), .I3(idelay_tap_cnt_r[4]), .O(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAABAAAAAA)) \mpr_4to1.inhibit_edge_detect_r_i_5 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ), .I2(mpr_rd_fall2_prev_r), .I3(mpr_rd_rise2_prev_r), .I4(mpr_rd_rise1_prev_r), .I5(mpr_rd_fall0_prev_r), .O(inhibit_edge_detect_r0)); LUT4 #( .INIT(16'hFF7F)) \mpr_4to1.inhibit_edge_detect_r_i_6 (.I0(mpr_rd_fall2_prev_r), .I1(mpr_rd_fall0_prev_r), .I2(mpr_rd_fall3_prev_r), .I3(mpr_rd_rise0_prev_r), .O(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 )); LUT4 #( .INIT(16'hFFDF)) \mpr_4to1.inhibit_edge_detect_r_i_7 (.I0(mpr_rd_rise0_prev_r), .I1(mpr_rd_fall1_prev_r), .I2(mpr_rd_rise3_prev_r), .I3(mpr_rd_fall3_prev_r), .O(\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 )); FDRE \mpr_4to1.inhibit_edge_detect_r_reg (.C(CLK), .CE(1'b1), .D(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ), .Q(inhibit_edge_detect_r), .R(1'b0)); LUT3 #( .INIT(8'h06)) \mpr_4to1.stable_idel_cnt[0]_i_1 (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I1(stable_idel_cnt), .I2(stable_idel_cnt0), .O(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h006A)) \mpr_4to1.stable_idel_cnt[1]_i_1 (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I1(stable_idel_cnt), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I3(stable_idel_cnt0), .O(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT5 #( .INIT(32'h00006AAA)) \mpr_4to1.stable_idel_cnt[2]_i_1 (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .I1(stable_idel_cnt), .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .I4(stable_idel_cnt0), .O(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000080)) \mpr_4to1.stable_idel_cnt[2]_i_2 (.I0(stable_idel_cnt22_in), .I1(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ), .I2(mpr_rd_rise0_prev_r_reg_0), .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .I4(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .I5(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ), .O(stable_idel_cnt)); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT3 #( .INIT(8'hFE)) \mpr_4to1.stable_idel_cnt[2]_i_3 (.I0(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ), .I1(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ), .I2(rstdiv0_sync_r1_reg_rep__23), .O(stable_idel_cnt0)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) \mpr_4to1.stable_idel_cnt[2]_i_4 (.I0(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ), .I1(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .I2(mpr_rd_fall0_prev_r), .I3(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .I4(mpr_rd_rise2_prev_r), .I5(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ), .O(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \mpr_4to1.stable_idel_cnt[2]_i_5 (.I0(out[3]), .I1(cal1_state_r), .I2(out[2]), .I3(out[0]), .I4(out[4]), .I5(out[1]), .O(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 )); LUT4 #( .INIT(16'h6FF6)) \mpr_4to1.stable_idel_cnt[2]_i_6 (.I0(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .I1(mpr_rd_fall2_prev_r), .I2(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .I3(mpr_rd_rise1_prev_r), .O(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 )); LUT5 #( .INIT(32'hFFFF6FF6)) \mpr_4to1.stable_idel_cnt[2]_i_7 (.I0(mpr_rd_rise0_prev_r), .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .I2(mpr_rd_fall3_prev_r), .I3(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .I4(\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ), .O(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 )); LUT4 #( .INIT(16'h6FF6)) \mpr_4to1.stable_idel_cnt[2]_i_8 (.I0(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .I1(mpr_rd_fall1_prev_r), .I2(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .I3(mpr_rd_rise3_prev_r), .O(\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 )); FDRE \mpr_4to1.stable_idel_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ), .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ), .R(1'b0)); FDRE \mpr_4to1.stable_idel_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ), .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ), .R(1'b0)); FDRE \mpr_4to1.stable_idel_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ), .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ), .R(1'b0)); LUT3 #( .INIT(8'h24)) mpr_dec_cpt_r_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .O(mpr_dec_cpt_r_reg_1)); FDRE mpr_dec_cpt_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[3]_0 ), .Q(mpr_dec_cpt_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0300000000002323)) mpr_last_byte_done_i_2 (.I0(cal1_state_r1), .I1(mpr_rank_done_r_reg_0), .I2(cal1_state_r), .I3(cal1_cnt_cpt_r1), .I4(out[3]), .I5(out[4]), .O(mpr_last_byte_done_reg_0)); FDRE mpr_last_byte_done_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_1 ), .Q(mpr_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'hFBFFFFFFFFFFFFFF)) mpr_rank_done_r_i_2 (.I0(cal1_state_r), .I1(out[4]), .I2(mpr_rdlvl_done_r1_reg_0), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I5(prech_done), .O(mpr_rank_done_r_reg_1)); LUT5 #( .INIT(32'h7E7EFFFE)) mpr_rank_done_r_i_3 (.I0(out[0]), .I1(out[2]), .I2(out[3]), .I3(cal1_state_r), .I4(out[1]), .O(mpr_rank_done_r_reg_0)); FDRE mpr_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_2 ), .Q(mpr_rnk_done), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE mpr_rd_fall0_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .Q(mpr_rd_fall0_prev_r), .R(1'b0)); FDRE mpr_rd_fall1_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .Q(mpr_rd_fall1_prev_r), .R(1'b0)); FDRE mpr_rd_fall2_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .Q(mpr_rd_fall2_prev_r), .R(1'b0)); FDRE mpr_rd_fall3_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .Q(mpr_rd_fall3_prev_r), .R(1'b0)); FDRE mpr_rd_rise0_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .Q(mpr_rd_rise0_prev_r), .R(1'b0)); LUT6 #( .INIT(64'h0000300000001000)) mpr_rd_rise1_prev_r_i_1 (.I0(out[1]), .I1(out[3]), .I2(mpr_rd_rise0_prev_r_reg_1), .I3(out[0]), .I4(out[2]), .I5(mpr_rd_rise0_prev_r_reg_0), .O(mpr_rd_rise0_prev_r0)); LUT2 #( .INIT(4'h1)) mpr_rd_rise1_prev_r_i_2 (.I0(cal1_state_r), .I1(out[4]), .O(mpr_rd_rise0_prev_r_reg_1)); FDRE mpr_rd_rise1_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .Q(mpr_rd_rise1_prev_r), .R(1'b0)); FDRE mpr_rd_rise2_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ), .Q(mpr_rd_rise2_prev_r), .R(1'b0)); FDRE mpr_rd_rise3_prev_r_reg (.C(CLK), .CE(mpr_rd_rise0_prev_r0), .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .Q(mpr_rd_rise3_prev_r), .R(1'b0)); FDRE mpr_rdlvl_done_r1_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r1_reg_0), .Q(mpr_rdlvl_done_r1), .R(1'b0)); FDRE mpr_rdlvl_done_r2_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r1), .Q(mpr_rdlvl_done_r2), .R(1'b0)); LUT6 #( .INIT(64'h0000000000001000)) mpr_rdlvl_done_r_i_2 (.I0(out[1]), .I1(out[4]), .I2(cal1_state_r), .I3(out[0]), .I4(out[3]), .I5(out[2]), .O(rdlvl_stg1_done_int)); FDRE mpr_rdlvl_done_r_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r_reg_0), .Q(mpr_rdlvl_done_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE mpr_rdlvl_start_r_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_start_reg), .Q(mpr_rdlvl_start_r), .R(1'b0)); FDRE mpr_valid_r1_reg (.C(CLK), .CE(1'b1), .D(mpr_valid_r1_reg_0), .Q(mpr_valid_r1), .R(1'b0)); FDRE mpr_valid_r2_reg (.C(CLK), .CE(1'b1), .D(mpr_valid_r1), .Q(mpr_valid_r2), .R(1'b0)); LUT5 #( .INIT(32'h00000008)) mpr_valid_r_i_1 (.I0(mpr_rdlvl_start_reg), .I1(phy_rddata_en_1), .I2(rstdiv0_sync_r1_reg_rep__20), .I3(mpr_rdlvl_done_r1_reg_0), .I4(mpr_valid_r_reg_0), .O(mpr_valid_r)); FDRE mpr_valid_r_reg (.C(CLK), .CE(1'b1), .D(mpr_valid_r), .Q(mpr_valid_r1_reg_0), .R(1'b0)); LUT6 #( .INIT(64'h4000000000000001)) new_cnt_cpt_r_i_1 (.I0(new_cnt_cpt_r_i_2_n_0), .I1(out[2]), .I2(out[3]), .I3(out[4]), .I4(out[0]), .I5(out[1]), .O(new_cnt_cpt_r)); LUT6 #( .INIT(64'hAAAAFFEFFFFFFFEF)) new_cnt_cpt_r_i_2 (.I0(cal1_state_r), .I1(cal1_state_r1535_out), .I2(rdlvl_stg1_start_reg), .I3(rdlvl_stg1_start_r), .I4(out[4]), .I5(new_cnt_cpt_r82_out), .O(new_cnt_cpt_r_i_2_n_0)); LUT6 #( .INIT(64'h8880AAAAAAAAAAAA)) new_cnt_cpt_r_i_3 (.I0(prech_done), .I1(mpr_rdlvl_done_r1_reg_0), .I2(\rnk_cnt_r_reg_n_0_[0] ), .I3(\rnk_cnt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I5(\cal1_cnt_cpt_r_reg_n_0_[0] ), .O(new_cnt_cpt_r82_out)); FDRE new_cnt_cpt_r_reg (.C(CLK), .CE(1'b1), .D(new_cnt_cpt_r), .Q(new_cnt_cpt_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT5 #( .INIT(32'h0000EA00)) \phaser_in_gen.phaser_in_i_1 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [1]), .I2(\calib_sel_reg[3] [0]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[3]_1 )); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_10 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_10__0 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_10__1 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_10__2 (.I0(Q), .I1(pi_counter_load_val[1]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[1])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_11 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_11__0 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_11__1 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_11__2 (.I0(Q), .I1(pi_counter_load_val[0]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[0])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_1__0 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [0]), .I2(\calib_sel_reg[3] [1]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[2]_1 )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT5 #( .INIT(32'h0000BA00)) \phaser_in_gen.phaser_in_i_1__1 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [1]), .I2(\calib_sel_reg[3] [0]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'h0000AB00)) \phaser_in_gen.phaser_in_i_1__2 (.I0(calib_in_common), .I1(\calib_sel_reg[3] [1]), .I2(\calib_sel_reg[3] [0]), .I3(pi_counter_load_en), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[0]_1 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[3]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3__0 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[2]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3__1 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[1]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_3__2 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(rdlvl_pi_stg2_f_en), .I2(prbs_pi_stg2_f_en), .I3(tempmon_pi_f_en_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[0]_0 )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4 (.I0(\gen_byte_sel_div1.calib_in_common_reg_0 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[3] )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4__0 (.I0(\gen_byte_sel_div1.calib_in_common_reg_1 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[2] )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4__1 (.I0(\gen_byte_sel_div1.calib_in_common_reg_2 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[1] )); LUT5 #( .INIT(32'h0000AAA8)) \phaser_in_gen.phaser_in_i_4__2 (.I0(\gen_byte_sel_div1.calib_in_common_reg_3 ), .I1(rdlvl_pi_stg2_f_incdec), .I2(prbs_pi_stg2_f_incdec), .I3(tempmon_pi_f_inc_r), .I4(Q), .O(\pi_dqs_found_lanes_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_6 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [5])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_6__0 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [5])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_6__1 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [5])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_6__2 (.I0(Q), .I1(pi_counter_load_val[5]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[5])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_7 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [4])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_7__0 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [4])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_7__1 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [4])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_7__2 (.I0(Q), .I1(pi_counter_load_val[4]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[4])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_8 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [3])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_8__0 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [3])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_8__1 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [3])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_8__2 (.I0(Q), .I1(pi_counter_load_val[3]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[3])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_9 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[1]_2 [2])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT5 #( .INIT(32'h44440040)) \phaser_in_gen.phaser_in_i_9__0 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [1]), .I3(\calib_sel_reg[3] [0]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[2]_2 [2])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT5 #( .INIT(32'h44444000)) \phaser_in_gen.phaser_in_i_9__1 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(\pi_dqs_found_lanes_r1_reg[3]_2 [2])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT5 #( .INIT(32'h44440004)) \phaser_in_gen.phaser_in_i_9__2 (.I0(Q), .I1(pi_counter_load_val[2]), .I2(\calib_sel_reg[3] [0]), .I3(\calib_sel_reg[3] [1]), .I4(calib_in_common), .O(COUNTERLOADVAL[2])); (* SOFT_HLUTNM = "soft_lutpair209" *) LUT2 #( .INIT(4'hE)) pi_cnt_dec_i_2 (.I0(wait_cnt_r_reg__0[2]), .I1(wait_cnt_r_reg__0[3]), .O(pi_cnt_dec_reg_0)); FDRE pi_cnt_dec_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_r_reg[0]_1 ), .Q(pi_en_stg2_f_timing_reg_0), .R(1'b0)); FDRE pi_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing), .Q(rdlvl_pi_stg2_f_en), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT2 #( .INIT(4'hE)) pi_en_stg2_f_timing_i_1 (.I0(cal1_dlyce_cpt_r_reg_n_0), .I1(pi_en_stg2_f_timing_reg_0), .O(pi_en_stg2_f_timing_i_1_n_0)); FDRE pi_en_stg2_f_timing_reg (.C(CLK), .CE(1'b1), .D(pi_en_stg2_f_timing_i_1_n_0), .Q(pi_en_stg2_f_timing), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE pi_fine_dly_dec_done_reg (.C(CLK), .CE(1'b1), .D(fine_dly_dec_done_r2), .Q(pi_fine_dly_dec_done), .R(1'b0)); LUT5 #( .INIT(32'h40404F40)) \pi_rdval_cnt[0]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [0]), .I2(\pi_rdval_cnt[5]_i_4_n_0 ), .I3(\pi_rdval_cnt_reg[1]_0 ), .I4(pi_rdval_cnt[0]), .O(\pi_rdval_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFB0808FBFB08FB08)) \pi_rdval_cnt[1]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[1] ), .I1(dqs_po_dec_done_r1), .I2(dqs_po_dec_done_r2), .I3(pi_rdval_cnt[1]), .I4(pi_rdval_cnt[0]), .I5(\pi_rdval_cnt_reg[1]_0 ), .O(\pi_rdval_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hB8B8B888888888B8)) \pi_rdval_cnt[2]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[2] ), .I1(\pi_rdval_cnt[5]_i_4_n_0 ), .I2(\pi_rdval_cnt_reg[1]_0 ), .I3(pi_rdval_cnt[1]), .I4(pi_rdval_cnt[0]), .I5(pi_rdval_cnt[2]), .O(\pi_rdval_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0808FB08FB080808)) \pi_rdval_cnt[3]_i_1 (.I0(\calib_sel_reg[3]_0 [1]), .I1(dqs_po_dec_done_r1), .I2(dqs_po_dec_done_r2), .I3(\pi_rdval_cnt_reg[1]_0 ), .I4(\pi_rdval_cnt[3]_i_2_n_0 ), .I5(pi_rdval_cnt[3]), .O(\pi_rdval_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT3 #( .INIT(8'h01)) \pi_rdval_cnt[3]_i_2 (.I0(pi_rdval_cnt[0]), .I1(pi_rdval_cnt[1]), .I2(pi_rdval_cnt[2]), .O(\pi_rdval_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h0808FBFBFB080808)) \pi_rdval_cnt[4]_i_1 (.I0(\rdlvl_cpt_tap_cnt_reg[4] ), .I1(dqs_po_dec_done_r1), .I2(dqs_po_dec_done_r2), .I3(pi_rdval_cnt[5]), .I4(\pi_rdval_cnt[4]_i_2_n_0 ), .I5(pi_rdval_cnt[4]), .O(\pi_rdval_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT4 #( .INIT(16'h0001)) \pi_rdval_cnt[4]_i_2 (.I0(pi_rdval_cnt[2]), .I1(pi_rdval_cnt[1]), .I2(pi_rdval_cnt[0]), .I3(pi_rdval_cnt[3]), .O(\pi_rdval_cnt[4]_i_2_n_0 )); LUT4 #( .INIT(16'hBBFB)) \pi_rdval_cnt[5]_i_1 (.I0(pi_en_stg2_f_timing_reg_0), .I1(\pi_rdval_cnt_reg[1]_0 ), .I2(dqs_po_dec_done_r1), .I3(dqs_po_dec_done_r2), .O(\pi_rdval_cnt[5]_i_1_n_0 )); LUT5 #( .INIT(32'h40404F40)) \pi_rdval_cnt[5]_i_2 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [4]), .I2(\pi_rdval_cnt[5]_i_4_n_0 ), .I3(pi_rdval_cnt[5]), .I4(\pi_rdval_cnt[5]_i_5_n_0 ), .O(\pi_rdval_cnt[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \pi_rdval_cnt[5]_i_3 (.I0(pi_rdval_cnt[5]), .I1(pi_rdval_cnt[4]), .I2(pi_rdval_cnt[2]), .I3(pi_rdval_cnt[1]), .I4(pi_rdval_cnt[0]), .I5(pi_rdval_cnt[3]), .O(\pi_rdval_cnt_reg[1]_0 )); LUT2 #( .INIT(4'h2)) \pi_rdval_cnt[5]_i_4 (.I0(dqs_po_dec_done_r1), .I1(dqs_po_dec_done_r2), .O(\pi_rdval_cnt[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT5 #( .INIT(32'h00000001)) \pi_rdval_cnt[5]_i_5 (.I0(pi_rdval_cnt[3]), .I1(pi_rdval_cnt[0]), .I2(pi_rdval_cnt[1]), .I3(pi_rdval_cnt[2]), .I4(pi_rdval_cnt[4]), .O(\pi_rdval_cnt[5]_i_5_n_0 )); FDRE \pi_rdval_cnt_reg[0] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[0]_i_1_n_0 ), .Q(pi_rdval_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \pi_rdval_cnt_reg[1] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[1]_i_1_n_0 ), .Q(pi_rdval_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \pi_rdval_cnt_reg[2] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[2]_i_1_n_0 ), .Q(pi_rdval_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \pi_rdval_cnt_reg[3] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[3]_i_1_n_0 ), .Q(pi_rdval_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \pi_rdval_cnt_reg[4] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[4]_i_1_n_0 ), .Q(pi_rdval_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \pi_rdval_cnt_reg[5] (.C(CLK), .CE(\pi_rdval_cnt[5]_i_1_n_0 ), .D(\pi_rdval_cnt[5]_i_2_n_0 ), .Q(pi_rdval_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE pi_stg2_f_incdec_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_f_incdec_timing), .Q(rdlvl_pi_stg2_f_incdec), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT4 #( .INIT(16'h0008)) pi_stg2_f_incdec_timing_i_1__0 (.I0(cal1_dlyce_cpt_r_reg_n_0), .I1(cal1_dlyinc_cpt_r_reg_n_0), .I2(pi_en_stg2_f_timing_reg_0), .I3(rstdiv0_sync_r1_reg_rep__23), .O(pi_stg2_f_incdec_timing0)); FDRE pi_stg2_f_incdec_timing_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_f_incdec_timing0), .Q(pi_stg2_f_incdec_timing), .R(1'b0)); FDRE pi_stg2_load_reg (.C(CLK), .CE(1'b1), .D(pi_stg2_load_timing), .Q(pi_counter_load_en), .R(1'b0)); FDRE pi_stg2_load_timing_reg (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt_reg[2]_0 ), .Q(pi_stg2_load_timing), .R(1'b0)); FDRE \pi_stg2_reg_l_reg[0] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[0]), .Q(pi_counter_load_val[0]), .R(1'b0)); FDRE \pi_stg2_reg_l_reg[1] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[1]), .Q(pi_counter_load_val[1]), .R(1'b0)); FDRE \pi_stg2_reg_l_reg[2] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[2]), .Q(pi_counter_load_val[2]), .R(1'b0)); FDRE \pi_stg2_reg_l_reg[3] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[3]), .Q(pi_counter_load_val[3]), .R(1'b0)); FDRE \pi_stg2_reg_l_reg[4] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[4]), .Q(pi_counter_load_val[4]), .R(1'b0)); FDRE \pi_stg2_reg_l_reg[5] (.C(CLK), .CE(1'b1), .D(pi_stg2_reg_l_timing[5]), .Q(pi_counter_load_val[5]), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[0]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ), .O(\pi_stg2_reg_l_timing[0]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[1]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ), .O(\pi_stg2_reg_l_timing[1]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[2]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ), .O(\pi_stg2_reg_l_timing[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[3]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ), .O(\pi_stg2_reg_l_timing[3]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[4]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ), .O(\pi_stg2_reg_l_timing[4]_i_1_n_0 )); LUT3 #( .INIT(8'hEF)) \pi_stg2_reg_l_timing[5]_i_1 (.I0(\pi_stg2_reg_l_timing_reg[0]_0 ), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(\regl_dqs_cnt_reg[0]_0 ), .O(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \pi_stg2_reg_l_timing[5]_i_2 (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ), .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ), .I2(regl_dqs_cnt[0]), .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ), .I4(regl_dqs_cnt[1]), .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ), .O(\pi_stg2_reg_l_timing[5]_i_2_n_0 )); FDRE \pi_stg2_reg_l_timing_reg[0] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[0]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[0]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE \pi_stg2_reg_l_timing_reg[1] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[1]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[1]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE \pi_stg2_reg_l_timing_reg[2] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[2]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[2]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE \pi_stg2_reg_l_timing_reg[3] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[3]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[3]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE \pi_stg2_reg_l_timing_reg[4] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[4]_i_1_n_0 ), .Q(pi_stg2_reg_l_timing[4]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); FDRE \pi_stg2_reg_l_timing_reg[5] (.C(CLK), .CE(1'b1), .D(\pi_stg2_reg_l_timing[5]_i_2_n_0 ), .Q(pi_stg2_reg_l_timing[5]), .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFEFFFEFFFFFFFE)) prech_req_r_i_1 (.I0(rdlvl_prech_req), .I1(wrcal_prech_req), .I2(complex_ocal_ref_req), .I3(prbs_rdlvl_prech_req_reg), .I4(dqs_found_prech_req), .I5(\init_state_r_reg[5]_0 ), .O(prech_req)); FDRE \rd_mux_sel_r_reg[0] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .R(1'b0)); FDRE \rd_mux_sel_r_reg[1] (.C(CLK), .CE(1'b1), .D(\cal1_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[1]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [1]), .O(\rdlvl_cpt_tap_cnt_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[2]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [2]), .O(\rdlvl_cpt_tap_cnt_reg[2] )); LUT2 #( .INIT(4'h4)) \rdlvl_cpt_tap_cnt[4]_i_1 (.I0(\calib_sel_reg[3] [2]), .I1(\pi_counter_read_val_reg[5] [3]), .O(\rdlvl_cpt_tap_cnt_reg[4] )); LUT5 #( .INIT(32'h00000001)) \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I1(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFEFFFFFFFFFFFFF)) \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 (.I0(\cal1_state_r1_reg_n_0_[5] ), .I1(\cal1_state_r1_reg_n_0_[4] ), .I2(\cal1_state_r1_reg_n_0_[2] ), .I3(\cal1_state_r1_reg_n_0_[0] ), .I4(\cal1_state_r1_reg_n_0_[3] ), .I5(\cal1_state_r1_reg_n_0_[1] ), .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 )); LUT5 #( .INIT(32'h00000004)) \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I1(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .I2(\rnk_cnt_r_reg_n_0_[1] ), .I3(\rnk_cnt_r_reg_n_0_[0] ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .O(rdlvl_dqs_tap_cnt_r)); LUT5 #( .INIT(32'h00000002)) \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(\rnk_cnt_r_reg_n_0_[0] ), .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .O(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 )); LUT5 #( .INIT(32'h00020000)) \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1 (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]), .I1(\rnk_cnt_r_reg_n_0_[1] ), .I2(\rnk_cnt_r_reg_n_0_[0] ), .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ), .I4(\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]), .O(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 )); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][0] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][1] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][2] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][3] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][4] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][5] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][0] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][1] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][2] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][3] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][4] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][5] (.C(CLK), .CE(rdlvl_dqs_tap_cnt_r), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][0] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][1] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][2] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][3] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][4] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][5] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ), .R(rstdiv0_sync_r1_reg_rep__14[0])); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][0] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[0] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][1] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[1] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][2] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[2] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][3] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[3] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][4] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[4] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][5] (.C(CLK), .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ), .D(\tap_cnt_cpt_r_reg_n_0_[5] ), .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ), .R(rstdiv0_sync_r1_reg_rep__13)); FDRE rdlvl_last_byte_done_int_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_4 ), .Q(rdlvl_last_byte_done), .R(rstdiv0_sync_r1_reg_rep__13)); LUT6 #( .INIT(64'hFFFFFFFFCC88FEAA)) rdlvl_pi_incdec_i_2 (.I0(out[3]), .I1(cal1_wait_r), .I2(store_sr_req_r_reg_0), .I3(out[1]), .I4(out[2]), .I5(rdlvl_pi_incdec_i_4_n_0), .O(rdlvl_pi_incdec_reg_0)); LUT6 #( .INIT(64'h000000000000FD0D)) rdlvl_pi_incdec_i_4 (.I0(mpr_rdlvl_start_reg), .I1(mpr_rdlvl_start_r), .I2(cal1_state_r), .I3(cal1_wait_r), .I4(out[1]), .I5(out[4]), .O(rdlvl_pi_incdec_i_4_n_0)); LUT6 #( .INIT(64'h0000000105A5AA05)) rdlvl_pi_incdec_i_5 (.I0(out[4]), .I1(cal1_wait_r), .I2(out[3]), .I3(out[0]), .I4(out[1]), .I5(cal1_state_r), .O(rdlvl_pi_incdec_i_5_n_0)); LUT6 #( .INIT(64'h0000000000001000)) rdlvl_pi_incdec_i_6 (.I0(out[1]), .I1(cal1_state_r), .I2(out[3]), .I3(out[4]), .I4(out[0]), .I5(cal1_wait_r), .O(rdlvl_pi_incdec_i_6_n_0)); FDRE rdlvl_pi_incdec_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[1]_0 ), .Q(rdlvl_pi_incdec), .R(rstdiv0_sync_r1_reg_rep__14[0])); MUXF7 rdlvl_pi_incdec_reg_i_3 (.I0(rdlvl_pi_incdec_i_5_n_0), .I1(rdlvl_pi_incdec_i_6_n_0), .O(rdlvl_pi_incdec_reg_1), .S(out[2])); FDRE rdlvl_prech_req_reg (.C(CLK), .CE(1'b1), .D(cal1_prech_req_r_reg_n_0), .Q(rdlvl_prech_req), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'hBFFFFFFFFFFFFFFF)) rdlvl_rank_done_r_i_2 (.I0(cal1_state_r), .I1(out[4]), .I2(mpr_rdlvl_done_r1_reg_0), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I5(prech_done), .O(rdlvl_rank_done_r_reg_0)); FDRE rdlvl_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_cal1_state_r_reg[4]_3 ), .Q(rdlvl_stg1_rank_done), .R(rstdiv0_sync_r1_reg_rep__13)); (* syn_maxfan = "30" *) FDRE rdlvl_stg1_done_int_reg (.C(CLK), .CE(1'b1), .D(mpr_rdlvl_done_r_reg_1), .Q(rdlvl_stg1_done_r1_reg), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE rdlvl_stg1_start_r_reg (.C(CLK), .CE(1'b1), .D(rdlvl_stg1_start_reg), .Q(rdlvl_stg1_start_r), .R(1'b0)); LUT6 #( .INIT(64'h0004FFFFFFFF0000)) \regl_dqs_cnt[0]_i_1 (.I0(\regl_dqs_cnt_r_reg[2]_0 ), .I1(regl_dqs_cnt[1]), .I2(regl_rank_cnt[0]), .I3(regl_rank_cnt[1]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_dqs_cnt[0]), .O(\regl_dqs_cnt[0]_i_1_n_0 )); LUT3 #( .INIT(8'hBA)) \regl_dqs_cnt[1]_i_1 (.I0(\pi_stg2_reg_l_timing_reg[0]_0 ), .I1(mpr_rdlvl_done_r2), .I2(mpr_rdlvl_done_r1), .O(\regl_dqs_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'h3337FFFFCCCC0000)) \regl_dqs_cnt[1]_i_2 (.I0(\regl_dqs_cnt_r_reg[2]_0 ), .I1(regl_dqs_cnt[0]), .I2(regl_rank_cnt[0]), .I3(regl_rank_cnt[1]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_dqs_cnt[1]), .O(\regl_dqs_cnt[1]_i_2_n_0 )); LUT5 #( .INIT(32'hAAAAAAAB)) \regl_dqs_cnt[1]_i_3 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[1]), .I4(done_cnt[0]), .O(\pi_stg2_reg_l_timing_reg[0]_0 )); LUT5 #( .INIT(32'h04444444)) \regl_dqs_cnt[2]_i_1 (.I0(\regl_dqs_cnt[1]_i_1_n_0 ), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(regl_dqs_cnt[1]), .I3(regl_dqs_cnt[0]), .I4(\regl_dqs_cnt_reg[0]_0 ), .O(\regl_dqs_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT5 #( .INIT(32'h00000200)) \regl_dqs_cnt[2]_i_2 (.I0(p_0_in539_in), .I1(done_cnt[2]), .I2(done_cnt[3]), .I3(done_cnt[0]), .I4(done_cnt[1]), .O(\regl_dqs_cnt_reg[0]_0 )); LUT6 #( .INIT(64'h0000000000020000)) \regl_dqs_cnt[2]_i_3 (.I0(out[1]), .I1(out[0]), .I2(out[4]), .I3(out[3]), .I4(cal1_state_r), .I5(out[2]), .O(p_0_in539_in)); FDRE \regl_dqs_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(regl_dqs_cnt[0]), .Q(regl_dqs_cnt_r[0]), .R(1'b0)); FDRE \regl_dqs_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(regl_dqs_cnt[1]), .Q(regl_dqs_cnt_r[1]), .R(1'b0)); FDRE \regl_dqs_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt_r_reg[2]_0 ), .Q(regl_dqs_cnt_r[2]), .R(1'b0)); FDRE \regl_dqs_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt[0]_i_1_n_0 ), .Q(regl_dqs_cnt[0]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); FDRE \regl_dqs_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt[1]_i_2_n_0 ), .Q(regl_dqs_cnt[1]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); FDRE \regl_dqs_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\regl_dqs_cnt[2]_i_1_n_0 ), .Q(\regl_dqs_cnt_r_reg[2]_0 ), .R(1'b0)); LUT6 #( .INIT(64'hCFFFFFFF20000000)) \regl_rank_cnt[0]_i_1 (.I0(regl_rank_cnt[1]), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(regl_dqs_cnt[1]), .I3(regl_dqs_cnt[0]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_rank_cnt[0]), .O(\regl_rank_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hDFFFFFFF20000000)) \regl_rank_cnt[1]_i_1 (.I0(regl_rank_cnt[0]), .I1(\regl_dqs_cnt_r_reg[2]_0 ), .I2(regl_dqs_cnt[1]), .I3(regl_dqs_cnt[0]), .I4(\regl_dqs_cnt_reg[0]_0 ), .I5(regl_rank_cnt[1]), .O(\regl_rank_cnt[1]_i_1_n_0 )); FDRE \regl_rank_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\regl_rank_cnt[0]_i_1_n_0 ), .Q(regl_rank_cnt[0]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); FDRE \regl_rank_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\regl_rank_cnt[1]_i_1_n_0 ), .Q(regl_rank_cnt[1]), .R(\regl_dqs_cnt[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[0]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .I1(out[3]), .O(\right_edge_taps_r[0]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[1]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ), .I1(out[3]), .O(\right_edge_taps_r[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[2]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ), .I1(out[3]), .O(\right_edge_taps_r[2]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[3]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(out[3]), .O(\right_edge_taps_r[3]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[4]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ), .I1(out[3]), .O(\right_edge_taps_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888800002000)) \right_edge_taps_r[5]_i_1 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(\right_edge_taps_r_reg[0]_2 ), .I3(found_stable_eye_last_r), .I4(\right_edge_taps_r_reg[0]_0 ), .I5(out[2]), .O(\right_edge_taps_r[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \right_edge_taps_r[5]_i_2 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(out[3]), .O(\right_edge_taps_r[5]_i_2_n_0 )); FDRE \right_edge_taps_r_reg[0] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[0]_i_1_n_0 ), .Q(right_edge_taps_r__0[0]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \right_edge_taps_r_reg[1] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[1]_i_1_n_0 ), .Q(right_edge_taps_r__0[1]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \right_edge_taps_r_reg[2] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[2]_i_1_n_0 ), .Q(right_edge_taps_r__0[2]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \right_edge_taps_r_reg[3] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[3]_i_1_n_0 ), .Q(right_edge_taps_r__0[3]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \right_edge_taps_r_reg[4] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[4]_i_1_n_0 ), .Q(right_edge_taps_r__0[4]), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \right_edge_taps_r_reg[5] (.C(CLK), .CE(\right_edge_taps_r[5]_i_1_n_0 ), .D(\right_edge_taps_r[5]_i_2_n_0 ), .Q(right_edge_taps_r__0[5]), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT3 #( .INIT(8'h34)) \rnk_cnt_r[0]_i_1__0 (.I0(cal1_state_r), .I1(\rnk_cnt_r[1]_i_2_n_0 ), .I2(\rnk_cnt_r_reg_n_0_[0] ), .O(\rnk_cnt_r[0]_i_1__0_n_0 )); LUT4 #( .INIT(16'h1F20)) \rnk_cnt_r[1]_i_1__0 (.I0(\rnk_cnt_r_reg_n_0_[0] ), .I1(cal1_state_r), .I2(\rnk_cnt_r[1]_i_2_n_0 ), .I3(\rnk_cnt_r_reg_n_0_[1] ), .O(\rnk_cnt_r[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h00800A0000000000)) \rnk_cnt_r[1]_i_2 (.I0(out[1]), .I1(\rnk_cnt_r[1]_i_3_n_0 ), .I2(out[3]), .I3(cal1_state_r), .I4(out[4]), .I5(\cal1_cnt_cpt_r[1]_i_5_n_0 ), .O(\rnk_cnt_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'hE000000000000000)) \rnk_cnt_r[1]_i_3 (.I0(\rnk_cnt_r_reg_n_0_[1] ), .I1(\rnk_cnt_r_reg_n_0_[0] ), .I2(mpr_rdlvl_done_r1_reg_0), .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ), .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ), .I5(prech_done), .O(\rnk_cnt_r[1]_i_3_n_0 )); FDRE \rnk_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[0]_i_1__0_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); FDRE \rnk_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rnk_cnt_r[1]_i_1__0_n_0 ), .Q(\rnk_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h00000000AAAE0000)) samp_cnt_done_r_i_1 (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .I1(samp_cnt_done_r_i_2_n_0), .I2(samp_cnt_done_r_i_3_n_0), .I3(samp_cnt_done_r_i_4_n_0), .I4(samp_edge_cnt0_en_r), .I5(rstdiv0_sync_r1_reg_rep__23), .O(samp_cnt_done_r_i_1_n_0)); LUT4 #( .INIT(16'h0010)) samp_cnt_done_r_i_2 (.I0(samp_edge_cnt1_r_reg[11]), .I1(samp_edge_cnt1_r_reg[7]), .I2(samp_edge_cnt1_r_reg[0]), .I3(samp_edge_cnt1_r_reg[6]), .O(samp_cnt_done_r_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) samp_cnt_done_r_i_3 (.I0(samp_edge_cnt1_r_reg[8]), .I1(samp_edge_cnt1_r_reg[3]), .I2(samp_edge_cnt1_r_reg[1]), .I3(samp_edge_cnt1_r_reg[10]), .O(samp_cnt_done_r_i_3_n_0)); LUT4 #( .INIT(16'hFFFE)) samp_cnt_done_r_i_4 (.I0(samp_edge_cnt1_r_reg[4]), .I1(samp_edge_cnt1_r_reg[9]), .I2(samp_edge_cnt1_r_reg[2]), .I3(samp_edge_cnt1_r_reg[5]), .O(samp_cnt_done_r_i_4_n_0)); FDRE samp_cnt_done_r_reg (.C(CLK), .CE(1'b1), .D(samp_cnt_done_r_i_1_n_0), .Q(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h0100000002003000)) samp_edge_cnt0_en_r_i_1 (.I0(out[1]), .I1(cal1_state_r), .I2(out[4]), .I3(out[0]), .I4(out[2]), .I5(out[3]), .O(pb_detect_edge)); FDRE samp_edge_cnt0_en_r_reg (.C(CLK), .CE(1'b1), .D(pb_detect_edge), .Q(samp_edge_cnt0_en_r), .R(1'b0)); LUT2 #( .INIT(4'hE)) \samp_edge_cnt0_r[0]_i_2 (.I0(sr_valid_r2), .I1(mpr_valid_r2), .O(samp_edge_cnt0_r0)); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[0]_i_4 (.I0(samp_edge_cnt0_r_reg[3]), .O(\samp_edge_cnt0_r[0]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[0]_i_5 (.I0(samp_edge_cnt0_r_reg[2]), .O(\samp_edge_cnt0_r[0]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[0]_i_6 (.I0(samp_edge_cnt0_r_reg[1]), .O(\samp_edge_cnt0_r[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \samp_edge_cnt0_r[0]_i_7 (.I0(samp_edge_cnt0_r_reg[0]), .O(\samp_edge_cnt0_r[0]_i_7_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_2 (.I0(samp_edge_cnt0_r_reg[7]), .O(\samp_edge_cnt0_r[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_3 (.I0(samp_edge_cnt0_r_reg[6]), .O(\samp_edge_cnt0_r[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_4 (.I0(samp_edge_cnt0_r_reg[5]), .O(\samp_edge_cnt0_r[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[4]_i_5 (.I0(samp_edge_cnt0_r_reg[4]), .O(\samp_edge_cnt0_r[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_2 (.I0(samp_edge_cnt0_r_reg[11]), .O(\samp_edge_cnt0_r[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_3 (.I0(samp_edge_cnt0_r_reg[10]), .O(\samp_edge_cnt0_r[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_4 (.I0(samp_edge_cnt0_r_reg[9]), .O(\samp_edge_cnt0_r[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt0_r[8]_i_5 (.I0(samp_edge_cnt0_r_reg[8]), .O(\samp_edge_cnt0_r[8]_i_5_n_0 )); FDRE \samp_edge_cnt0_r_reg[0] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_7 ), .Q(samp_edge_cnt0_r_reg[0]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt0_r_reg[0]_i_3 (.CI(1'b0), .CO({\samp_edge_cnt0_r_reg[0]_i_3_n_0 ,\samp_edge_cnt0_r_reg[0]_i_3_n_1 ,\samp_edge_cnt0_r_reg[0]_i_3_n_2 ,\samp_edge_cnt0_r_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\samp_edge_cnt0_r_reg[0]_i_3_n_4 ,\samp_edge_cnt0_r_reg[0]_i_3_n_5 ,\samp_edge_cnt0_r_reg[0]_i_3_n_6 ,\samp_edge_cnt0_r_reg[0]_i_3_n_7 }), .S({\samp_edge_cnt0_r[0]_i_4_n_0 ,\samp_edge_cnt0_r[0]_i_5_n_0 ,\samp_edge_cnt0_r[0]_i_6_n_0 ,\samp_edge_cnt0_r[0]_i_7_n_0 })); FDRE \samp_edge_cnt0_r_reg[10] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_5 ), .Q(samp_edge_cnt0_r_reg[10]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[11] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_4 ), .Q(samp_edge_cnt0_r_reg[11]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[1] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_6 ), .Q(samp_edge_cnt0_r_reg[1]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[2] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_5 ), .Q(samp_edge_cnt0_r_reg[2]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[3] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[0]_i_3_n_4 ), .Q(samp_edge_cnt0_r_reg[3]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[4] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_7 ), .Q(samp_edge_cnt0_r_reg[4]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt0_r_reg[4]_i_1 (.CI(\samp_edge_cnt0_r_reg[0]_i_3_n_0 ), .CO({\samp_edge_cnt0_r_reg[4]_i_1_n_0 ,\samp_edge_cnt0_r_reg[4]_i_1_n_1 ,\samp_edge_cnt0_r_reg[4]_i_1_n_2 ,\samp_edge_cnt0_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt0_r_reg[4]_i_1_n_4 ,\samp_edge_cnt0_r_reg[4]_i_1_n_5 ,\samp_edge_cnt0_r_reg[4]_i_1_n_6 ,\samp_edge_cnt0_r_reg[4]_i_1_n_7 }), .S({\samp_edge_cnt0_r[4]_i_2_n_0 ,\samp_edge_cnt0_r[4]_i_3_n_0 ,\samp_edge_cnt0_r[4]_i_4_n_0 ,\samp_edge_cnt0_r[4]_i_5_n_0 })); FDRE \samp_edge_cnt0_r_reg[5] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_6 ), .Q(samp_edge_cnt0_r_reg[5]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[6] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_5 ), .Q(samp_edge_cnt0_r_reg[6]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[7] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[4]_i_1_n_4 ), .Q(samp_edge_cnt0_r_reg[7]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt0_r_reg[8] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_7 ), .Q(samp_edge_cnt0_r_reg[8]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt0_r_reg[8]_i_1 (.CI(\samp_edge_cnt0_r_reg[4]_i_1_n_0 ), .CO({\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt0_r_reg[8]_i_1_n_1 ,\samp_edge_cnt0_r_reg[8]_i_1_n_2 ,\samp_edge_cnt0_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt0_r_reg[8]_i_1_n_4 ,\samp_edge_cnt0_r_reg[8]_i_1_n_5 ,\samp_edge_cnt0_r_reg[8]_i_1_n_6 ,\samp_edge_cnt0_r_reg[8]_i_1_n_7 }), .S({\samp_edge_cnt0_r[8]_i_2_n_0 ,\samp_edge_cnt0_r[8]_i_3_n_0 ,\samp_edge_cnt0_r[8]_i_4_n_0 ,\samp_edge_cnt0_r[8]_i_5_n_0 })); FDRE \samp_edge_cnt0_r_reg[9] (.C(CLK), .CE(samp_edge_cnt0_r0), .D(\samp_edge_cnt0_r_reg[8]_i_1_n_6 ), .Q(samp_edge_cnt0_r_reg[9]), .R(samp_edge_cnt0_en_r_reg_0)); LUT6 #( .INIT(64'h0000000000000002)) samp_edge_cnt1_en_r_i_1 (.I0(samp_edge_cnt1_en_r_i_2_n_0), .I1(samp_edge_cnt1_en_r_i_3_n_0), .I2(samp_edge_cnt0_r_reg[8]), .I3(samp_edge_cnt0_r_reg[7]), .I4(samp_edge_cnt0_r_reg[6]), .I5(samp_edge_cnt0_r_reg[2]), .O(samp_edge_cnt1_en_r0)); LUT6 #( .INIT(64'h0000000000000E00)) samp_edge_cnt1_en_r_i_2 (.I0(sr_valid_r2), .I1(mpr_valid_r2), .I2(samp_edge_cnt0_r_reg[3]), .I3(samp_edge_cnt0_r_reg[0]), .I4(samp_edge_cnt0_r_reg[5]), .I5(samp_edge_cnt0_r_reg[1]), .O(samp_edge_cnt1_en_r_i_2_n_0)); LUT4 #( .INIT(16'hFFFE)) samp_edge_cnt1_en_r_i_3 (.I0(samp_edge_cnt0_r_reg[11]), .I1(samp_edge_cnt0_r_reg[4]), .I2(samp_edge_cnt0_r_reg[10]), .I3(samp_edge_cnt0_r_reg[9]), .O(samp_edge_cnt1_en_r_i_3_n_0)); FDRE samp_edge_cnt1_en_r_reg (.C(CLK), .CE(1'b1), .D(samp_edge_cnt1_en_r0), .Q(samp_edge_cnt1_en_r), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[0]_i_2 (.I0(samp_edge_cnt1_r_reg[3]), .O(\samp_edge_cnt1_r[0]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[0]_i_3 (.I0(samp_edge_cnt1_r_reg[2]), .O(\samp_edge_cnt1_r[0]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[0]_i_4 (.I0(samp_edge_cnt1_r_reg[1]), .O(\samp_edge_cnt1_r[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \samp_edge_cnt1_r[0]_i_5 (.I0(samp_edge_cnt1_r_reg[0]), .O(\samp_edge_cnt1_r[0]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_2 (.I0(samp_edge_cnt1_r_reg[7]), .O(\samp_edge_cnt1_r[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_3 (.I0(samp_edge_cnt1_r_reg[6]), .O(\samp_edge_cnt1_r[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_4 (.I0(samp_edge_cnt1_r_reg[5]), .O(\samp_edge_cnt1_r[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[4]_i_5 (.I0(samp_edge_cnt1_r_reg[4]), .O(\samp_edge_cnt1_r[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_2 (.I0(samp_edge_cnt1_r_reg[11]), .O(\samp_edge_cnt1_r[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_3 (.I0(samp_edge_cnt1_r_reg[10]), .O(\samp_edge_cnt1_r[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_4 (.I0(samp_edge_cnt1_r_reg[9]), .O(\samp_edge_cnt1_r[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \samp_edge_cnt1_r[8]_i_5 (.I0(samp_edge_cnt1_r_reg[8]), .O(\samp_edge_cnt1_r[8]_i_5_n_0 )); FDRE \samp_edge_cnt1_r_reg[0] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_7 ), .Q(samp_edge_cnt1_r_reg[0]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt1_r_reg[0]_i_1 (.CI(1'b0), .CO({\samp_edge_cnt1_r_reg[0]_i_1_n_0 ,\samp_edge_cnt1_r_reg[0]_i_1_n_1 ,\samp_edge_cnt1_r_reg[0]_i_1_n_2 ,\samp_edge_cnt1_r_reg[0]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\samp_edge_cnt1_r_reg[0]_i_1_n_4 ,\samp_edge_cnt1_r_reg[0]_i_1_n_5 ,\samp_edge_cnt1_r_reg[0]_i_1_n_6 ,\samp_edge_cnt1_r_reg[0]_i_1_n_7 }), .S({\samp_edge_cnt1_r[0]_i_2_n_0 ,\samp_edge_cnt1_r[0]_i_3_n_0 ,\samp_edge_cnt1_r[0]_i_4_n_0 ,\samp_edge_cnt1_r[0]_i_5_n_0 })); FDRE \samp_edge_cnt1_r_reg[10] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_5 ), .Q(samp_edge_cnt1_r_reg[10]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[11] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_4 ), .Q(samp_edge_cnt1_r_reg[11]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[1] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_6 ), .Q(samp_edge_cnt1_r_reg[1]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[2] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_5 ), .Q(samp_edge_cnt1_r_reg[2]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[3] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[0]_i_1_n_4 ), .Q(samp_edge_cnt1_r_reg[3]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[4] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_7 ), .Q(samp_edge_cnt1_r_reg[4]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt1_r_reg[4]_i_1 (.CI(\samp_edge_cnt1_r_reg[0]_i_1_n_0 ), .CO({\samp_edge_cnt1_r_reg[4]_i_1_n_0 ,\samp_edge_cnt1_r_reg[4]_i_1_n_1 ,\samp_edge_cnt1_r_reg[4]_i_1_n_2 ,\samp_edge_cnt1_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt1_r_reg[4]_i_1_n_4 ,\samp_edge_cnt1_r_reg[4]_i_1_n_5 ,\samp_edge_cnt1_r_reg[4]_i_1_n_6 ,\samp_edge_cnt1_r_reg[4]_i_1_n_7 }), .S({\samp_edge_cnt1_r[4]_i_2_n_0 ,\samp_edge_cnt1_r[4]_i_3_n_0 ,\samp_edge_cnt1_r[4]_i_4_n_0 ,\samp_edge_cnt1_r[4]_i_5_n_0 })); FDRE \samp_edge_cnt1_r_reg[5] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_6 ), .Q(samp_edge_cnt1_r_reg[5]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[6] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_5 ), .Q(samp_edge_cnt1_r_reg[6]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[7] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[4]_i_1_n_4 ), .Q(samp_edge_cnt1_r_reg[7]), .R(samp_edge_cnt0_en_r_reg_0)); FDRE \samp_edge_cnt1_r_reg[8] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_7 ), .Q(samp_edge_cnt1_r_reg[8]), .R(samp_edge_cnt0_en_r_reg_0)); CARRY4 \samp_edge_cnt1_r_reg[8]_i_1 (.CI(\samp_edge_cnt1_r_reg[4]_i_1_n_0 ), .CO({\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt1_r_reg[8]_i_1_n_1 ,\samp_edge_cnt1_r_reg[8]_i_1_n_2 ,\samp_edge_cnt1_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\samp_edge_cnt1_r_reg[8]_i_1_n_4 ,\samp_edge_cnt1_r_reg[8]_i_1_n_5 ,\samp_edge_cnt1_r_reg[8]_i_1_n_6 ,\samp_edge_cnt1_r_reg[8]_i_1_n_7 }), .S({\samp_edge_cnt1_r[8]_i_2_n_0 ,\samp_edge_cnt1_r[8]_i_3_n_0 ,\samp_edge_cnt1_r[8]_i_4_n_0 ,\samp_edge_cnt1_r[8]_i_5_n_0 })); FDRE \samp_edge_cnt1_r_reg[9] (.C(CLK), .CE(samp_edge_cnt1_en_r), .D(\samp_edge_cnt1_r_reg[8]_i_1_n_6 ), .Q(samp_edge_cnt1_r_reg[9]), .R(samp_edge_cnt0_en_r_reg_0)); LUT1 #( .INIT(2'h1)) \second_edge_taps_r[0]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\second_edge_taps_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT2 #( .INIT(4'h9)) \second_edge_taps_r[1]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ), .I1(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\second_edge_taps_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT3 #( .INIT(8'hA9)) \second_edge_taps_r[2]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\second_edge_taps_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT4 #( .INIT(16'hAAA9)) \second_edge_taps_r[3]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\tap_cnt_cpt_r_reg_n_0_[2] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(\second_edge_taps_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT5 #( .INIT(32'hAAAAAAA9)) \second_edge_taps_r[4]_i_1 (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ), .I1(\tap_cnt_cpt_r_reg_n_0_[3] ), .I2(\tap_cnt_cpt_r_reg_n_0_[1] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .I4(\tap_cnt_cpt_r_reg_n_0_[2] ), .O(\second_edge_taps_r[4]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \second_edge_taps_r[5]_i_1 (.I0(out[3]), .I1(\second_edge_taps_r_reg[5]_0 ), .O(\second_edge_taps_r[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8888888820000000)) \second_edge_taps_r[5]_i_2 (.I0(\right_edge_taps_r_reg[0]_1 ), .I1(out[3]), .I2(\right_edge_taps_r_reg[0]_2 ), .I3(found_stable_eye_last_r), .I4(\right_edge_taps_r_reg[0]_0 ), .I5(out[2]), .O(\second_edge_taps_r_reg[5]_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \second_edge_taps_r[5]_i_3 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(\tap_cnt_cpt_r_reg_n_0_[4] ), .I2(\tap_cnt_cpt_r_reg_n_0_[2] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .I4(\tap_cnt_cpt_r_reg_n_0_[1] ), .I5(\tap_cnt_cpt_r_reg_n_0_[3] ), .O(\second_edge_taps_r[5]_i_3_n_0 )); FDRE \second_edge_taps_r_reg[0] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[0]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[0] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE \second_edge_taps_r_reg[1] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[1]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[1] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE \second_edge_taps_r_reg[2] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[2]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[2] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE \second_edge_taps_r_reg[3] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[3]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[3] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE \second_edge_taps_r_reg[4] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[4]_i_1_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[4] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE \second_edge_taps_r_reg[5] (.C(CLK), .CE(\second_edge_taps_r_reg[5]_0 ), .D(\second_edge_taps_r[5]_i_3_n_0 ), .Q(\second_edge_taps_r_reg_n_0_[5] ), .R(\second_edge_taps_r[5]_i_1_n_0 )); FDRE sr_valid_r1_reg (.C(CLK), .CE(1'b1), .D(sr_valid_r1_reg_0), .Q(sr_valid_r1), .R(1'b0)); FDRE sr_valid_r2_reg (.C(CLK), .CE(1'b1), .D(sr_valid_r1), .Q(sr_valid_r2), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT4 #( .INIT(16'hFFFE)) sr_valid_r_i_2 (.I0(cnt_shift_r_reg__0[0]), .I1(cnt_shift_r_reg__0[1]), .I2(cnt_shift_r_reg__0[3]), .I3(cnt_shift_r_reg__0[2]), .O(mpr_valid_r_reg_0)); FDRE sr_valid_r_reg (.C(CLK), .CE(1'b1), .D(sr_valid_r108_out), .Q(sr_valid_r1_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT3 #( .INIT(8'h45)) \stg1_wr_rd_cnt[4]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__24), .I1(rdlvl_stg1_done_r1_reg), .I2(stg1_wr_done), .O(\stg1_wr_rd_cnt_reg[3] )); FDRE store_sr_r_reg (.C(CLK), .CE(1'b1), .D(store_sr_req_r_reg_1), .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000100000000000)) store_sr_req_pulsed_r_i_1 (.I0(cal1_state_r), .I1(out[2]), .I2(out[1]), .I3(out[0]), .I4(out[3]), .I5(out[4]), .O(store_sr_req_pulsed_r)); FDRE store_sr_req_pulsed_r_reg (.C(CLK), .CE(1'b1), .D(store_sr_req_pulsed_r), .Q(store_sr_req_pulsed_r_reg_n_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); LUT6 #( .INIT(64'h0000000288880002)) store_sr_req_r_i_1 (.I0(store_sr_req_r_i_2_n_0), .I1(out[4]), .I2(cal1_wait_r), .I3(store_sr_req_r_reg_0), .I4(out[0]), .I5(store_sr_req_pulsed_r_reg_n_0), .O(store_sr_req_r)); LUT4 #( .INIT(16'h0010)) store_sr_req_r_i_2 (.I0(cal1_state_r), .I1(out[3]), .I2(out[1]), .I3(out[2]), .O(store_sr_req_r_i_2_n_0)); FDRE store_sr_req_r_reg (.C(CLK), .CE(1'b1), .D(store_sr_req_r), .Q(store_sr_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__14[1])); (* SOFT_HLUTNM = "soft_lutpair208" *) LUT3 #( .INIT(8'h69)) \tap_cnt_cpt_r[1]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(\tap_cnt_cpt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT4 #( .INIT(16'h6CC9)) \tap_cnt_cpt_r[2]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[2] ), .I2(\tap_cnt_cpt_r_reg_n_0_[1] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT5 #( .INIT(32'h6CCCCCC9)) \tap_cnt_cpt_r[3]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[3] ), .I2(\tap_cnt_cpt_r_reg_n_0_[2] ), .I3(\tap_cnt_cpt_r_reg_n_0_[0] ), .I4(\tap_cnt_cpt_r_reg_n_0_[1] ), .O(p_0_in__0[3])); LUT6 #( .INIT(64'h6CCCCCCCCCCCCCC9)) \tap_cnt_cpt_r[4]_i_1 (.I0(cal1_dlyinc_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[4] ), .I2(\tap_cnt_cpt_r_reg_n_0_[3] ), .I3(\tap_cnt_cpt_r_reg_n_0_[1] ), .I4(\tap_cnt_cpt_r_reg_n_0_[0] ), .I5(\tap_cnt_cpt_r_reg_n_0_[2] ), .O(p_0_in__0[4])); LUT4 #( .INIT(16'hFFF4)) \tap_cnt_cpt_r[5]_i_1 (.I0(mpr_rdlvl_done_r2), .I1(mpr_rdlvl_done_r1), .I2(new_cnt_cpt_r_reg_n_0), .I3(rstdiv0_sync_r1_reg_rep__23), .O(tap_cnt_cpt_r0)); LUT4 #( .INIT(16'hAA8A)) \tap_cnt_cpt_r[5]_i_2 (.I0(cal1_dlyce_cpt_r_reg_n_0), .I1(\tap_cnt_cpt_r_reg_n_0_[5] ), .I2(\tap_cnt_cpt_r[5]_i_4_n_0 ), .I3(cal1_dlyinc_cpt_r_reg_n_0), .O(tap_cnt_cpt_r)); LUT4 #( .INIT(16'h6F60)) \tap_cnt_cpt_r[5]_i_3 (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ), .I1(tap_limit_cpt_r_i_2_n_0), .I2(cal1_dlyinc_cpt_r_reg_n_0), .I3(\second_edge_taps_r[5]_i_3_n_0 ), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT5 #( .INIT(32'h00000001)) \tap_cnt_cpt_r[5]_i_4 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(\tap_cnt_cpt_r_reg_n_0_[2] ), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .O(\tap_cnt_cpt_r[5]_i_4_n_0 )); FDRE \tap_cnt_cpt_r_reg[0] (.C(CLK), .CE(tap_cnt_cpt_r), .D(\second_edge_taps_r[0]_i_1_n_0 ), .Q(\tap_cnt_cpt_r_reg_n_0_[0] ), .R(tap_cnt_cpt_r0)); FDRE \tap_cnt_cpt_r_reg[1] (.C(CLK), .CE(tap_cnt_cpt_r), .D(\tap_cnt_cpt_r[1]_i_1_n_0 ), .Q(\tap_cnt_cpt_r_reg_n_0_[1] ), .R(tap_cnt_cpt_r0)); FDRE \tap_cnt_cpt_r_reg[2] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[2]), .Q(\tap_cnt_cpt_r_reg_n_0_[2] ), .R(tap_cnt_cpt_r0)); FDRE \tap_cnt_cpt_r_reg[3] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[3]), .Q(\tap_cnt_cpt_r_reg_n_0_[3] ), .R(tap_cnt_cpt_r0)); FDRE \tap_cnt_cpt_r_reg[4] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[4]), .Q(\tap_cnt_cpt_r_reg_n_0_[4] ), .R(tap_cnt_cpt_r0)); FDRE \tap_cnt_cpt_r_reg[5] (.C(CLK), .CE(tap_cnt_cpt_r), .D(p_0_in__0[5]), .Q(\tap_cnt_cpt_r_reg_n_0_[5] ), .R(tap_cnt_cpt_r0)); LUT5 #( .INIT(32'h000000EA)) tap_limit_cpt_r_i_1 (.I0(tap_limit_cpt_r), .I1(tap_limit_cpt_r_i_2_n_0), .I2(\tap_cnt_cpt_r_reg_n_0_[5] ), .I3(tap_limit_cpt_r_i_3_n_0), .I4(tap_cnt_cpt_r0), .O(tap_limit_cpt_r_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT5 #( .INIT(32'h80000000)) tap_limit_cpt_r_i_2 (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ), .I1(\tap_cnt_cpt_r_reg_n_0_[1] ), .I2(\tap_cnt_cpt_r_reg_n_0_[0] ), .I3(\tap_cnt_cpt_r_reg_n_0_[2] ), .I4(\tap_cnt_cpt_r_reg_n_0_[4] ), .O(tap_limit_cpt_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000010)) tap_limit_cpt_r_i_3 (.I0(\cal1_state_r1_reg_n_0_[5] ), .I1(\cal1_state_r1_reg_n_0_[4] ), .I2(\cal1_state_r1_reg_n_0_[2] ), .I3(\cal1_state_r1_reg_n_0_[0] ), .I4(\cal1_state_r1_reg_n_0_[3] ), .I5(\cal1_state_r1_reg_n_0_[1] ), .O(tap_limit_cpt_r_i_3_n_0)); FDRE tap_limit_cpt_r_reg (.C(CLK), .CE(1'b1), .D(tap_limit_cpt_r_i_1_n_0), .Q(tap_limit_cpt_r), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wait_cnt_r[0]_i_1__1 (.I0(\wait_cnt_r_reg[0]_0 [0]), .O(wait_cnt_r0__0[0])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT2 #( .INIT(4'h9)) \wait_cnt_r[1]_i_1__1 (.I0(\wait_cnt_r_reg[0]_0 [1]), .I1(\wait_cnt_r_reg[0]_0 [0]), .O(\wait_cnt_r[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT3 #( .INIT(8'hA9)) \wait_cnt_r[2]_i_1__0 (.I0(wait_cnt_r_reg__0[2]), .I1(\wait_cnt_r_reg[0]_0 [0]), .I2(\wait_cnt_r_reg[0]_0 [1]), .O(wait_cnt_r0__0[2])); LUT5 #( .INIT(32'hAAAAAAA8)) \wait_cnt_r[3]_i_2__1 (.I0(dqs_po_dec_done_r2), .I1(wait_cnt_r_reg__0[2]), .I2(wait_cnt_r_reg__0[3]), .I3(\wait_cnt_r_reg[0]_0 [1]), .I4(\wait_cnt_r_reg[0]_0 [0]), .O(wait_cnt_r0)); (* SOFT_HLUTNM = "soft_lutpair209" *) LUT4 #( .INIT(16'hAAA9)) \wait_cnt_r[3]_i_3 (.I0(wait_cnt_r_reg__0[3]), .I1(wait_cnt_r_reg__0[2]), .I2(\wait_cnt_r_reg[0]_0 [1]), .I3(\wait_cnt_r_reg[0]_0 [0]), .O(wait_cnt_r0__0[3])); FDRE \wait_cnt_r_reg[0] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0[0]), .Q(\wait_cnt_r_reg[0]_0 [0]), .R(pi_cnt_dec_reg_1)); FDRE \wait_cnt_r_reg[1] (.C(CLK), .CE(wait_cnt_r0), .D(\wait_cnt_r[1]_i_1__1_n_0 ), .Q(\wait_cnt_r_reg[0]_0 [1]), .R(pi_cnt_dec_reg_1)); FDRE \wait_cnt_r_reg[2] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0[2]), .Q(wait_cnt_r_reg__0[2]), .R(pi_cnt_dec_reg_1)); FDSE \wait_cnt_r_reg[3] (.C(CLK), .CE(wait_cnt_r0), .D(wait_cnt_r0__0[3]), .Q(wait_cnt_r_reg__0[3]), .S(pi_cnt_dec_reg_1)); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT4 #( .INIT(16'h7FFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_1 (.I0(rdlvl_stg1_done_r1_reg), .I1(prbs_rdlvl_done_reg_rep), .I2(oclkdelay_calib_done_r_reg), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] )); LUT5 #( .INIT(32'hDFDF0FFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[56]_i_1 (.I0(rdlvl_stg1_done_r1_reg), .I1(\dout_o_reg[6]_0 ), .I2(oclkdelay_calib_done_r_reg), .I3(first_wrcal_pat_r), .I4(wrcal_done_reg), .O(D[0])); LUT5 #( .INIT(32'hDFDF0FFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[60]_i_1 (.I0(rdlvl_stg1_done_r1_reg), .I1(\dout_o_reg[6] ), .I2(oclkdelay_calib_done_r_reg), .I3(first_wrcal_pat_r), .I4(wrcal_done_reg), .O(D[1])); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_tempmon (tempmon_pi_f_inc, tempmon_sel_pi_incdec, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , D, \calib_zero_inputs_reg[1] , \calib_zero_inputs_reg[1]_0 , \gen_byte_sel_div1.calib_in_common_reg , CLK, SS, tempmon_sample_en, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__7, oclkdelay_calib_done_r_reg, ck_addr_cmd_delay_done, ctl_lane_sel, rstdiv0_sync_r1_reg_rep__25, calib_complete, cmd_delay_start0, delay_done_r4_reg, calib_in_common, fine_adjust_done_r_reg, rd_data_offset_cal_done, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__6); output tempmon_pi_f_inc; output tempmon_sel_pi_incdec; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output [0:0]D; output [0:0]\calib_zero_inputs_reg[1] ; output \calib_zero_inputs_reg[1]_0 ; output \gen_byte_sel_div1.calib_in_common_reg ; input CLK; input [0:0]SS; input tempmon_sample_en; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__7; input oclkdelay_calib_done_r_reg; input ck_addr_cmd_delay_done; input ctl_lane_sel; input rstdiv0_sync_r1_reg_rep__25; input calib_complete; input cmd_delay_start0; input delay_done_r4_reg; input calib_in_common; input fine_adjust_done_r_reg; input rd_data_offset_cal_done; input [0:0]rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__6; wire CLK; wire [0:0]D; wire [0:0]SS; wire calib_complete; wire calib_in_common; wire [0:0]\calib_zero_inputs_reg[1] ; wire \calib_zero_inputs_reg[1]_0 ; wire ck_addr_cmd_delay_done; wire cmd_delay_start0; wire ctl_lane_sel; wire delay_done_r4_reg; wire [11:0]device_temp_101; wire [11:0]device_temp_init; wire \device_temp_init[11]_i_2_n_0 ; wire \device_temp_init[11]_i_3_n_0 ; wire [11:0]\device_temp_r_reg[11] ; wire fine_adjust_done_r_reg; wire [11:0]four_dec_min_limit; wire \four_dec_min_limit[11]_i_2_n_0 ; wire \four_dec_min_limit[11]_i_3_n_0 ; wire \four_dec_min_limit[5]_i_2_n_0 ; wire \four_dec_min_limit[5]_i_3_n_0 ; wire \four_dec_min_limit[5]_i_4_n_0 ; wire \four_dec_min_limit[5]_i_5_n_0 ; wire \four_dec_min_limit[9]_i_2_n_0 ; wire \four_dec_min_limit[9]_i_3_n_0 ; wire \four_dec_min_limit[9]_i_4_n_0 ; wire \four_dec_min_limit[9]_i_5_n_0 ; wire [11:2]four_dec_min_limit_nxt; wire \four_dec_min_limit_reg[11]_i_1_n_3 ; wire \four_dec_min_limit_reg[5]_i_1_n_0 ; wire \four_dec_min_limit_reg[5]_i_1_n_1 ; wire \four_dec_min_limit_reg[5]_i_1_n_2 ; wire \four_dec_min_limit_reg[5]_i_1_n_3 ; wire \four_dec_min_limit_reg[9]_i_1_n_0 ; wire \four_dec_min_limit_reg[9]_i_1_n_1 ; wire \four_dec_min_limit_reg[9]_i_1_n_2 ; wire \four_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]four_inc_max_limit; wire \four_inc_max_limit[11]_i_2_n_0 ; wire \four_inc_max_limit[11]_i_3_n_0 ; wire \four_inc_max_limit[11]_i_4_n_0 ; wire \four_inc_max_limit[1]_i_2_n_0 ; wire \four_inc_max_limit[4]_i_2_n_0 ; wire \four_inc_max_limit[4]_i_3_n_0 ; wire \four_inc_max_limit[4]_i_4_n_0 ; wire \four_inc_max_limit[4]_i_5_n_0 ; wire \four_inc_max_limit[8]_i_2_n_0 ; wire \four_inc_max_limit[8]_i_3_n_0 ; wire \four_inc_max_limit[8]_i_4_n_0 ; wire \four_inc_max_limit[8]_i_5_n_0 ; wire [11:1]four_inc_max_limit_nxt; wire \four_inc_max_limit_reg[11]_i_1_n_2 ; wire \four_inc_max_limit_reg[11]_i_1_n_3 ; wire \four_inc_max_limit_reg[4]_i_1_n_0 ; wire \four_inc_max_limit_reg[4]_i_1_n_1 ; wire \four_inc_max_limit_reg[4]_i_1_n_2 ; wire \four_inc_max_limit_reg[4]_i_1_n_3 ; wire \four_inc_max_limit_reg[8]_i_1_n_0 ; wire \four_inc_max_limit_reg[8]_i_1_n_1 ; wire \four_inc_max_limit_reg[8]_i_1_n_2 ; wire \four_inc_max_limit_reg[8]_i_1_n_3 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.calib_in_common_reg ; wire [11:1]neutral_max_limit; wire \neutral_max_limit[11]_i_2_n_0 ; wire \neutral_max_limit[11]_i_3_n_0 ; wire \neutral_max_limit[11]_i_4_n_0 ; wire \neutral_max_limit[4]_i_2_n_0 ; wire \neutral_max_limit[4]_i_3_n_0 ; wire \neutral_max_limit[4]_i_4_n_0 ; wire \neutral_max_limit[4]_i_5_n_0 ; wire \neutral_max_limit[8]_i_2_n_0 ; wire \neutral_max_limit[8]_i_3_n_0 ; wire \neutral_max_limit[8]_i_4_n_0 ; wire \neutral_max_limit[8]_i_5_n_0 ; wire [11:1]neutral_max_limit_nxt; wire \neutral_max_limit_reg[11]_i_1_n_2 ; wire \neutral_max_limit_reg[11]_i_1_n_3 ; wire \neutral_max_limit_reg[4]_i_1_n_0 ; wire \neutral_max_limit_reg[4]_i_1_n_1 ; wire \neutral_max_limit_reg[4]_i_1_n_2 ; wire \neutral_max_limit_reg[4]_i_1_n_3 ; wire \neutral_max_limit_reg[8]_i_1_n_0 ; wire \neutral_max_limit_reg[8]_i_1_n_1 ; wire \neutral_max_limit_reg[8]_i_1_n_2 ; wire \neutral_max_limit_reg[8]_i_1_n_3 ; wire [11:1]neutral_min_limit; wire \neutral_min_limit[11]_i_2_n_0 ; wire \neutral_min_limit[11]_i_3_n_0 ; wire \neutral_min_limit[5]_i_2_n_0 ; wire \neutral_min_limit[5]_i_3_n_0 ; wire \neutral_min_limit[5]_i_4_n_0 ; wire \neutral_min_limit[5]_i_5_n_0 ; wire \neutral_min_limit[9]_i_2_n_0 ; wire \neutral_min_limit[9]_i_3_n_0 ; wire \neutral_min_limit[9]_i_4_n_0 ; wire \neutral_min_limit[9]_i_5_n_0 ; wire [11:2]neutral_min_limit_nxt; wire \neutral_min_limit_reg[11]_i_1_n_3 ; wire \neutral_min_limit_reg[5]_i_1_n_0 ; wire \neutral_min_limit_reg[5]_i_1_n_1 ; wire \neutral_min_limit_reg[5]_i_1_n_2 ; wire \neutral_min_limit_reg[5]_i_1_n_3 ; wire \neutral_min_limit_reg[9]_i_1_n_0 ; wire \neutral_min_limit_reg[9]_i_1_n_1 ; wire \neutral_min_limit_reg[9]_i_1_n_2 ; wire \neutral_min_limit_reg[9]_i_1_n_3 ; wire oclkdelay_calib_done_r_reg; wire [11:1]one_dec_max_limit; wire \one_dec_max_limit[11]_i_2_n_0 ; wire \one_dec_max_limit[11]_i_3_n_0 ; wire \one_dec_max_limit[11]_i_4_n_0 ; wire \one_dec_max_limit[4]_i_2_n_0 ; wire \one_dec_max_limit[4]_i_3_n_0 ; wire \one_dec_max_limit[4]_i_4_n_0 ; wire \one_dec_max_limit[4]_i_5_n_0 ; wire \one_dec_max_limit[8]_i_2_n_0 ; wire \one_dec_max_limit[8]_i_3_n_0 ; wire \one_dec_max_limit[8]_i_4_n_0 ; wire \one_dec_max_limit[8]_i_5_n_0 ; wire [11:1]one_dec_max_limit_nxt; wire \one_dec_max_limit_reg[11]_i_1_n_2 ; wire \one_dec_max_limit_reg[11]_i_1_n_3 ; wire \one_dec_max_limit_reg[4]_i_1_n_0 ; wire \one_dec_max_limit_reg[4]_i_1_n_1 ; wire \one_dec_max_limit_reg[4]_i_1_n_2 ; wire \one_dec_max_limit_reg[4]_i_1_n_3 ; wire \one_dec_max_limit_reg[8]_i_1_n_0 ; wire \one_dec_max_limit_reg[8]_i_1_n_1 ; wire \one_dec_max_limit_reg[8]_i_1_n_2 ; wire \one_dec_max_limit_reg[8]_i_1_n_3 ; wire [11:1]one_dec_min_limit; wire \one_dec_min_limit[11]_i_2_n_0 ; wire \one_dec_min_limit[11]_i_3_n_0 ; wire \one_dec_min_limit[5]_i_2_n_0 ; wire \one_dec_min_limit[5]_i_3_n_0 ; wire \one_dec_min_limit[5]_i_4_n_0 ; wire \one_dec_min_limit[5]_i_5_n_0 ; wire \one_dec_min_limit[9]_i_2_n_0 ; wire \one_dec_min_limit[9]_i_3_n_0 ; wire \one_dec_min_limit[9]_i_4_n_0 ; wire \one_dec_min_limit[9]_i_5_n_0 ; wire [11:2]one_dec_min_limit_nxt; wire \one_dec_min_limit_reg[11]_i_1_n_3 ; wire \one_dec_min_limit_reg[5]_i_1_n_0 ; wire \one_dec_min_limit_reg[5]_i_1_n_1 ; wire \one_dec_min_limit_reg[5]_i_1_n_2 ; wire \one_dec_min_limit_reg[5]_i_1_n_3 ; wire \one_dec_min_limit_reg[9]_i_1_n_0 ; wire \one_dec_min_limit_reg[9]_i_1_n_1 ; wire \one_dec_min_limit_reg[9]_i_1_n_2 ; wire \one_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]one_inc_max_limit; wire \one_inc_max_limit[11]_i_2_n_0 ; wire \one_inc_max_limit[11]_i_3_n_0 ; wire \one_inc_max_limit[11]_i_4_n_0 ; wire \one_inc_max_limit[4]_i_2_n_0 ; wire \one_inc_max_limit[4]_i_3_n_0 ; wire \one_inc_max_limit[4]_i_4_n_0 ; wire \one_inc_max_limit[4]_i_5_n_0 ; wire \one_inc_max_limit[8]_i_2_n_0 ; wire \one_inc_max_limit[8]_i_3_n_0 ; wire \one_inc_max_limit[8]_i_4_n_0 ; wire \one_inc_max_limit[8]_i_5_n_0 ; wire [11:1]one_inc_max_limit_nxt; wire \one_inc_max_limit_reg[11]_i_1_n_2 ; wire \one_inc_max_limit_reg[11]_i_1_n_3 ; wire \one_inc_max_limit_reg[4]_i_1_n_0 ; wire \one_inc_max_limit_reg[4]_i_1_n_1 ; wire \one_inc_max_limit_reg[4]_i_1_n_2 ; wire \one_inc_max_limit_reg[4]_i_1_n_3 ; wire \one_inc_max_limit_reg[8]_i_1_n_0 ; wire \one_inc_max_limit_reg[8]_i_1_n_1 ; wire \one_inc_max_limit_reg[8]_i_1_n_2 ; wire \one_inc_max_limit_reg[8]_i_1_n_3 ; wire [11:1]one_inc_min_limit; wire \one_inc_min_limit[11]_i_2_n_0 ; wire \one_inc_min_limit[11]_i_3_n_0 ; wire \one_inc_min_limit[5]_i_2_n_0 ; wire \one_inc_min_limit[5]_i_3_n_0 ; wire \one_inc_min_limit[5]_i_4_n_0 ; wire \one_inc_min_limit[5]_i_5_n_0 ; wire \one_inc_min_limit[9]_i_2_n_0 ; wire \one_inc_min_limit[9]_i_3_n_0 ; wire \one_inc_min_limit[9]_i_4_n_0 ; wire \one_inc_min_limit[9]_i_5_n_0 ; wire [11:2]one_inc_min_limit_nxt; wire \one_inc_min_limit_reg[11]_i_1_n_3 ; wire \one_inc_min_limit_reg[5]_i_1_n_0 ; wire \one_inc_min_limit_reg[5]_i_1_n_1 ; wire \one_inc_min_limit_reg[5]_i_1_n_2 ; wire \one_inc_min_limit_reg[5]_i_1_n_3 ; wire \one_inc_min_limit_reg[9]_i_1_n_0 ; wire \one_inc_min_limit_reg[9]_i_1_n_1 ; wire \one_inc_min_limit_reg[9]_i_1_n_2 ; wire \one_inc_min_limit_reg[9]_i_1_n_3 ; wire p_0_in; wire pi_f_dec_i_2_n_0; wire pi_f_dec_nxt; wire pi_f_inc_i_10_n_0; wire pi_f_inc_i_2_n_0; wire pi_f_inc_i_3_n_0; wire pi_f_inc_i_5_n_0; wire pi_f_inc_i_6_n_0; wire pi_f_inc_i_7_n_0; wire pi_f_inc_i_8_n_0; wire pi_f_inc_i_9_n_0; wire pi_f_inc_nxt; wire rd_data_offset_cal_done; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__4; wire [0:0]rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire rstdiv0_sync_r1_reg_rep__7; wire temp_cmp_four_dec_min_101; wire temp_cmp_four_dec_min_102; wire temp_cmp_four_dec_min_102_i_10_n_0; wire temp_cmp_four_dec_min_102_i_11_n_0; wire temp_cmp_four_dec_min_102_i_12_n_0; wire temp_cmp_four_dec_min_102_i_13_n_0; wire temp_cmp_four_dec_min_102_i_14_n_0; wire temp_cmp_four_dec_min_102_i_3_n_0; wire temp_cmp_four_dec_min_102_i_4_n_0; wire temp_cmp_four_dec_min_102_i_5_n_0; wire temp_cmp_four_dec_min_102_i_6_n_0; wire temp_cmp_four_dec_min_102_i_7_n_0; wire temp_cmp_four_dec_min_102_i_8_n_0; wire temp_cmp_four_dec_min_102_i_9_n_0; wire temp_cmp_four_dec_min_102_reg_i_1_n_3; wire temp_cmp_four_dec_min_102_reg_i_2_n_0; wire temp_cmp_four_dec_min_102_reg_i_2_n_1; wire temp_cmp_four_dec_min_102_reg_i_2_n_2; wire temp_cmp_four_dec_min_102_reg_i_2_n_3; wire temp_cmp_four_inc_max_101; wire temp_cmp_four_inc_max_102; wire temp_cmp_four_inc_max_102_i_10_n_0; wire temp_cmp_four_inc_max_102_i_11_n_0; wire temp_cmp_four_inc_max_102_i_12_n_0; wire temp_cmp_four_inc_max_102_i_13_n_0; wire temp_cmp_four_inc_max_102_i_14_n_0; wire temp_cmp_four_inc_max_102_i_3_n_0; wire temp_cmp_four_inc_max_102_i_4_n_0; wire temp_cmp_four_inc_max_102_i_5_n_0; wire temp_cmp_four_inc_max_102_i_6_n_0; wire temp_cmp_four_inc_max_102_i_7_n_0; wire temp_cmp_four_inc_max_102_i_8_n_0; wire temp_cmp_four_inc_max_102_i_9_n_0; wire temp_cmp_four_inc_max_102_reg_i_1_n_3; wire temp_cmp_four_inc_max_102_reg_i_2_n_0; wire temp_cmp_four_inc_max_102_reg_i_2_n_1; wire temp_cmp_four_inc_max_102_reg_i_2_n_2; wire temp_cmp_four_inc_max_102_reg_i_2_n_3; wire temp_cmp_neutral_max_101; wire temp_cmp_neutral_max_102; wire temp_cmp_neutral_max_102_i_10_n_0; wire temp_cmp_neutral_max_102_i_11_n_0; wire temp_cmp_neutral_max_102_i_12_n_0; wire temp_cmp_neutral_max_102_i_13_n_0; wire temp_cmp_neutral_max_102_i_14_n_0; wire temp_cmp_neutral_max_102_i_3_n_0; wire temp_cmp_neutral_max_102_i_4_n_0; wire temp_cmp_neutral_max_102_i_5_n_0; wire temp_cmp_neutral_max_102_i_6_n_0; wire temp_cmp_neutral_max_102_i_7_n_0; wire temp_cmp_neutral_max_102_i_8_n_0; wire temp_cmp_neutral_max_102_i_9_n_0; wire temp_cmp_neutral_max_102_reg_i_1_n_3; wire temp_cmp_neutral_max_102_reg_i_2_n_0; wire temp_cmp_neutral_max_102_reg_i_2_n_1; wire temp_cmp_neutral_max_102_reg_i_2_n_2; wire temp_cmp_neutral_max_102_reg_i_2_n_3; wire temp_cmp_neutral_min_101; wire temp_cmp_neutral_min_102; wire temp_cmp_neutral_min_102_i_10_n_0; wire temp_cmp_neutral_min_102_i_11_n_0; wire temp_cmp_neutral_min_102_i_12_n_0; wire temp_cmp_neutral_min_102_i_13_n_0; wire temp_cmp_neutral_min_102_i_14_n_0; wire temp_cmp_neutral_min_102_i_3_n_0; wire temp_cmp_neutral_min_102_i_4_n_0; wire temp_cmp_neutral_min_102_i_5_n_0; wire temp_cmp_neutral_min_102_i_6_n_0; wire temp_cmp_neutral_min_102_i_7_n_0; wire temp_cmp_neutral_min_102_i_8_n_0; wire temp_cmp_neutral_min_102_i_9_n_0; wire temp_cmp_neutral_min_102_reg_i_1_n_3; wire temp_cmp_neutral_min_102_reg_i_2_n_0; wire temp_cmp_neutral_min_102_reg_i_2_n_1; wire temp_cmp_neutral_min_102_reg_i_2_n_2; wire temp_cmp_neutral_min_102_reg_i_2_n_3; wire temp_cmp_one_dec_max_101; wire temp_cmp_one_dec_max_102; wire temp_cmp_one_dec_max_102_i_10_n_0; wire temp_cmp_one_dec_max_102_i_11_n_0; wire temp_cmp_one_dec_max_102_i_12_n_0; wire temp_cmp_one_dec_max_102_i_13_n_0; wire temp_cmp_one_dec_max_102_i_14_n_0; wire temp_cmp_one_dec_max_102_i_3_n_0; wire temp_cmp_one_dec_max_102_i_4_n_0; wire temp_cmp_one_dec_max_102_i_5_n_0; wire temp_cmp_one_dec_max_102_i_6_n_0; wire temp_cmp_one_dec_max_102_i_7_n_0; wire temp_cmp_one_dec_max_102_i_8_n_0; wire temp_cmp_one_dec_max_102_i_9_n_0; wire temp_cmp_one_dec_max_102_reg_i_1_n_3; wire temp_cmp_one_dec_max_102_reg_i_2_n_0; wire temp_cmp_one_dec_max_102_reg_i_2_n_1; wire temp_cmp_one_dec_max_102_reg_i_2_n_2; wire temp_cmp_one_dec_max_102_reg_i_2_n_3; wire temp_cmp_one_dec_min_101; wire temp_cmp_one_dec_min_102; wire temp_cmp_one_dec_min_102_i_10_n_0; wire temp_cmp_one_dec_min_102_i_11_n_0; wire temp_cmp_one_dec_min_102_i_12_n_0; wire temp_cmp_one_dec_min_102_i_13_n_0; wire temp_cmp_one_dec_min_102_i_14_n_0; wire temp_cmp_one_dec_min_102_i_3_n_0; wire temp_cmp_one_dec_min_102_i_4_n_0; wire temp_cmp_one_dec_min_102_i_5_n_0; wire temp_cmp_one_dec_min_102_i_6_n_0; wire temp_cmp_one_dec_min_102_i_7_n_0; wire temp_cmp_one_dec_min_102_i_8_n_0; wire temp_cmp_one_dec_min_102_i_9_n_0; wire temp_cmp_one_dec_min_102_reg_i_1_n_3; wire temp_cmp_one_dec_min_102_reg_i_2_n_0; wire temp_cmp_one_dec_min_102_reg_i_2_n_1; wire temp_cmp_one_dec_min_102_reg_i_2_n_2; wire temp_cmp_one_dec_min_102_reg_i_2_n_3; wire temp_cmp_one_inc_max_101; wire temp_cmp_one_inc_max_102; wire temp_cmp_one_inc_max_102_i_10_n_0; wire temp_cmp_one_inc_max_102_i_11_n_0; wire temp_cmp_one_inc_max_102_i_12_n_0; wire temp_cmp_one_inc_max_102_i_13_n_0; wire temp_cmp_one_inc_max_102_i_14_n_0; wire temp_cmp_one_inc_max_102_i_3_n_0; wire temp_cmp_one_inc_max_102_i_4_n_0; wire temp_cmp_one_inc_max_102_i_5_n_0; wire temp_cmp_one_inc_max_102_i_6_n_0; wire temp_cmp_one_inc_max_102_i_7_n_0; wire temp_cmp_one_inc_max_102_i_8_n_0; wire temp_cmp_one_inc_max_102_i_9_n_0; wire temp_cmp_one_inc_max_102_reg_i_1_n_3; wire temp_cmp_one_inc_max_102_reg_i_2_n_0; wire temp_cmp_one_inc_max_102_reg_i_2_n_1; wire temp_cmp_one_inc_max_102_reg_i_2_n_2; wire temp_cmp_one_inc_max_102_reg_i_2_n_3; wire temp_cmp_one_inc_min_101; wire temp_cmp_one_inc_min_102; wire temp_cmp_one_inc_min_102_i_10_n_0; wire temp_cmp_one_inc_min_102_i_11_n_0; wire temp_cmp_one_inc_min_102_i_12_n_0; wire temp_cmp_one_inc_min_102_i_13_n_0; wire temp_cmp_one_inc_min_102_i_14_n_0; wire temp_cmp_one_inc_min_102_i_3_n_0; wire temp_cmp_one_inc_min_102_i_4_n_0; wire temp_cmp_one_inc_min_102_i_5_n_0; wire temp_cmp_one_inc_min_102_i_6_n_0; wire temp_cmp_one_inc_min_102_i_7_n_0; wire temp_cmp_one_inc_min_102_i_8_n_0; wire temp_cmp_one_inc_min_102_i_9_n_0; wire temp_cmp_one_inc_min_102_reg_i_1_n_3; wire temp_cmp_one_inc_min_102_reg_i_2_n_0; wire temp_cmp_one_inc_min_102_reg_i_2_n_1; wire temp_cmp_one_inc_min_102_reg_i_2_n_2; wire temp_cmp_one_inc_min_102_reg_i_2_n_3; wire temp_cmp_three_dec_max_101; wire temp_cmp_three_dec_max_102; wire temp_cmp_three_dec_max_102_i_10_n_0; wire temp_cmp_three_dec_max_102_i_11_n_0; wire temp_cmp_three_dec_max_102_i_12_n_0; wire temp_cmp_three_dec_max_102_i_13_n_0; wire temp_cmp_three_dec_max_102_i_14_n_0; wire temp_cmp_three_dec_max_102_i_3_n_0; wire temp_cmp_three_dec_max_102_i_4_n_0; wire temp_cmp_three_dec_max_102_i_5_n_0; wire temp_cmp_three_dec_max_102_i_6_n_0; wire temp_cmp_three_dec_max_102_i_7_n_0; wire temp_cmp_three_dec_max_102_i_8_n_0; wire temp_cmp_three_dec_max_102_i_9_n_0; wire temp_cmp_three_dec_max_102_reg_i_1_n_3; wire temp_cmp_three_dec_max_102_reg_i_2_n_0; wire temp_cmp_three_dec_max_102_reg_i_2_n_1; wire temp_cmp_three_dec_max_102_reg_i_2_n_2; wire temp_cmp_three_dec_max_102_reg_i_2_n_3; wire temp_cmp_three_dec_min_101; wire temp_cmp_three_dec_min_102; wire temp_cmp_three_dec_min_102_i_10_n_0; wire temp_cmp_three_dec_min_102_i_11_n_0; wire temp_cmp_three_dec_min_102_i_12_n_0; wire temp_cmp_three_dec_min_102_i_13_n_0; wire temp_cmp_three_dec_min_102_i_14_n_0; wire temp_cmp_three_dec_min_102_i_3_n_0; wire temp_cmp_three_dec_min_102_i_4_n_0; wire temp_cmp_three_dec_min_102_i_5_n_0; wire temp_cmp_three_dec_min_102_i_6_n_0; wire temp_cmp_three_dec_min_102_i_7_n_0; wire temp_cmp_three_dec_min_102_i_8_n_0; wire temp_cmp_three_dec_min_102_i_9_n_0; wire temp_cmp_three_dec_min_102_reg_i_1_n_3; wire temp_cmp_three_dec_min_102_reg_i_2_n_0; wire temp_cmp_three_dec_min_102_reg_i_2_n_1; wire temp_cmp_three_dec_min_102_reg_i_2_n_2; wire temp_cmp_three_dec_min_102_reg_i_2_n_3; wire temp_cmp_three_inc_max_101; wire temp_cmp_three_inc_max_102; wire temp_cmp_three_inc_max_102_i_10_n_0; wire temp_cmp_three_inc_max_102_i_11_n_0; wire temp_cmp_three_inc_max_102_i_12_n_0; wire temp_cmp_three_inc_max_102_i_13_n_0; wire temp_cmp_three_inc_max_102_i_14_n_0; wire temp_cmp_three_inc_max_102_i_3_n_0; wire temp_cmp_three_inc_max_102_i_4_n_0; wire temp_cmp_three_inc_max_102_i_5_n_0; wire temp_cmp_three_inc_max_102_i_6_n_0; wire temp_cmp_three_inc_max_102_i_7_n_0; wire temp_cmp_three_inc_max_102_i_8_n_0; wire temp_cmp_three_inc_max_102_i_9_n_0; wire temp_cmp_three_inc_max_102_reg_i_1_n_3; wire temp_cmp_three_inc_max_102_reg_i_2_n_0; wire temp_cmp_three_inc_max_102_reg_i_2_n_1; wire temp_cmp_three_inc_max_102_reg_i_2_n_2; wire temp_cmp_three_inc_max_102_reg_i_2_n_3; wire temp_cmp_three_inc_min_101; wire temp_cmp_three_inc_min_102; wire temp_cmp_three_inc_min_102_i_10_n_0; wire temp_cmp_three_inc_min_102_i_11_n_0; wire temp_cmp_three_inc_min_102_i_12_n_0; wire temp_cmp_three_inc_min_102_i_13_n_0; wire temp_cmp_three_inc_min_102_i_14_n_0; wire temp_cmp_three_inc_min_102_i_3_n_0; wire temp_cmp_three_inc_min_102_i_4_n_0; wire temp_cmp_three_inc_min_102_i_5_n_0; wire temp_cmp_three_inc_min_102_i_6_n_0; wire temp_cmp_three_inc_min_102_i_7_n_0; wire temp_cmp_three_inc_min_102_i_8_n_0; wire temp_cmp_three_inc_min_102_i_9_n_0; wire temp_cmp_three_inc_min_102_reg_i_1_n_3; wire temp_cmp_three_inc_min_102_reg_i_2_n_0; wire temp_cmp_three_inc_min_102_reg_i_2_n_1; wire temp_cmp_three_inc_min_102_reg_i_2_n_2; wire temp_cmp_three_inc_min_102_reg_i_2_n_3; wire temp_cmp_two_dec_max_101; wire temp_cmp_two_dec_max_102; wire temp_cmp_two_dec_max_102_i_10_n_0; wire temp_cmp_two_dec_max_102_i_11_n_0; wire temp_cmp_two_dec_max_102_i_12_n_0; wire temp_cmp_two_dec_max_102_i_13_n_0; wire temp_cmp_two_dec_max_102_i_14_n_0; wire temp_cmp_two_dec_max_102_i_3_n_0; wire temp_cmp_two_dec_max_102_i_4_n_0; wire temp_cmp_two_dec_max_102_i_5_n_0; wire temp_cmp_two_dec_max_102_i_6_n_0; wire temp_cmp_two_dec_max_102_i_7_n_0; wire temp_cmp_two_dec_max_102_i_8_n_0; wire temp_cmp_two_dec_max_102_i_9_n_0; wire temp_cmp_two_dec_max_102_reg_i_1_n_3; wire temp_cmp_two_dec_max_102_reg_i_2_n_0; wire temp_cmp_two_dec_max_102_reg_i_2_n_1; wire temp_cmp_two_dec_max_102_reg_i_2_n_2; wire temp_cmp_two_dec_max_102_reg_i_2_n_3; wire temp_cmp_two_dec_min_101; wire temp_cmp_two_dec_min_102; wire temp_cmp_two_dec_min_102_i_10_n_0; wire temp_cmp_two_dec_min_102_i_11_n_0; wire temp_cmp_two_dec_min_102_i_12_n_0; wire temp_cmp_two_dec_min_102_i_13_n_0; wire temp_cmp_two_dec_min_102_i_14_n_0; wire temp_cmp_two_dec_min_102_i_3_n_0; wire temp_cmp_two_dec_min_102_i_4_n_0; wire temp_cmp_two_dec_min_102_i_5_n_0; wire temp_cmp_two_dec_min_102_i_6_n_0; wire temp_cmp_two_dec_min_102_i_7_n_0; wire temp_cmp_two_dec_min_102_i_8_n_0; wire temp_cmp_two_dec_min_102_i_9_n_0; wire temp_cmp_two_dec_min_102_reg_i_1_n_3; wire temp_cmp_two_dec_min_102_reg_i_2_n_0; wire temp_cmp_two_dec_min_102_reg_i_2_n_1; wire temp_cmp_two_dec_min_102_reg_i_2_n_2; wire temp_cmp_two_dec_min_102_reg_i_2_n_3; wire temp_cmp_two_inc_max_101; wire temp_cmp_two_inc_max_102; wire temp_cmp_two_inc_max_102_i_10_n_0; wire temp_cmp_two_inc_max_102_i_11_n_0; wire temp_cmp_two_inc_max_102_i_12_n_0; wire temp_cmp_two_inc_max_102_i_13_n_0; wire temp_cmp_two_inc_max_102_i_14_n_0; wire temp_cmp_two_inc_max_102_i_3_n_0; wire temp_cmp_two_inc_max_102_i_4_n_0; wire temp_cmp_two_inc_max_102_i_5_n_0; wire temp_cmp_two_inc_max_102_i_6_n_0; wire temp_cmp_two_inc_max_102_i_7_n_0; wire temp_cmp_two_inc_max_102_i_8_n_0; wire temp_cmp_two_inc_max_102_i_9_n_0; wire temp_cmp_two_inc_max_102_reg_i_1_n_3; wire temp_cmp_two_inc_max_102_reg_i_2_n_0; wire temp_cmp_two_inc_max_102_reg_i_2_n_1; wire temp_cmp_two_inc_max_102_reg_i_2_n_2; wire temp_cmp_two_inc_max_102_reg_i_2_n_3; wire temp_cmp_two_inc_min_101; wire temp_cmp_two_inc_min_102; wire temp_cmp_two_inc_min_102_i_10_n_0; wire temp_cmp_two_inc_min_102_i_11_n_0; wire temp_cmp_two_inc_min_102_i_12_n_0; wire temp_cmp_two_inc_min_102_i_13_n_0; wire temp_cmp_two_inc_min_102_i_14_n_0; wire temp_cmp_two_inc_min_102_i_3_n_0; wire temp_cmp_two_inc_min_102_i_4_n_0; wire temp_cmp_two_inc_min_102_i_5_n_0; wire temp_cmp_two_inc_min_102_i_6_n_0; wire temp_cmp_two_inc_min_102_i_7_n_0; wire temp_cmp_two_inc_min_102_i_8_n_0; wire temp_cmp_two_inc_min_102_i_9_n_0; wire temp_cmp_two_inc_min_102_reg_i_1_n_3; wire temp_cmp_two_inc_min_102_reg_i_2_n_0; wire temp_cmp_two_inc_min_102_reg_i_2_n_1; wire temp_cmp_two_inc_min_102_reg_i_2_n_2; wire temp_cmp_two_inc_min_102_reg_i_2_n_3; wire temp_gte_three_dec_max; wire tempmon_init_complete; wire tempmon_pi_f_dec; wire tempmon_pi_f_inc; wire tempmon_sample_en; wire tempmon_sample_en_101; wire tempmon_sample_en_102; wire tempmon_sel_pi_incdec; wire [10:0]tempmon_state; wire \tempmon_state[0]_i_2_n_0 ; wire \tempmon_state[10]_i_10_n_0 ; wire \tempmon_state[10]_i_11_n_0 ; wire \tempmon_state[10]_i_12_n_0 ; wire \tempmon_state[10]_i_13_n_0 ; wire \tempmon_state[10]_i_14_n_0 ; wire \tempmon_state[10]_i_15_n_0 ; wire \tempmon_state[10]_i_16_n_0 ; wire \tempmon_state[10]_i_2_n_0 ; wire \tempmon_state[10]_i_3_n_0 ; wire \tempmon_state[10]_i_4_n_0 ; wire \tempmon_state[10]_i_5_n_0 ; wire \tempmon_state[10]_i_6_n_0 ; wire \tempmon_state[10]_i_7_n_0 ; wire \tempmon_state[10]_i_8_n_0 ; wire \tempmon_state[10]_i_9_n_0 ; wire \tempmon_state[1]_i_1_n_0 ; wire \tempmon_state[2]_i_1_n_0 ; wire \tempmon_state[3]_i_1_n_0 ; wire \tempmon_state[4]_i_1_n_0 ; wire \tempmon_state[5]_i_1_n_0 ; wire \tempmon_state[6]_i_1_n_0 ; wire \tempmon_state[6]_i_2_n_0 ; wire \tempmon_state[7]_i_1_n_0 ; wire \tempmon_state[8]_i_1_n_0 ; wire \tempmon_state[9]_i_1_n_0 ; wire tempmon_state_init; wire tempmon_state_nxt; wire [11:0]three_dec_max_limit; wire \three_dec_max_limit[0]_i_1_n_0 ; wire \three_dec_max_limit[10]_i_1_n_0 ; wire \three_dec_max_limit[11]_i_1_n_0 ; wire \three_dec_max_limit[11]_i_3_n_0 ; wire \three_dec_max_limit[11]_i_4_n_0 ; wire \three_dec_max_limit[11]_i_5_n_0 ; wire \three_dec_max_limit[1]_i_1_n_0 ; wire \three_dec_max_limit[2]_i_1_n_0 ; wire \three_dec_max_limit[3]_i_1_n_0 ; wire \three_dec_max_limit[4]_i_1_n_0 ; wire \three_dec_max_limit[4]_i_3_n_0 ; wire \three_dec_max_limit[4]_i_4_n_0 ; wire \three_dec_max_limit[4]_i_5_n_0 ; wire \three_dec_max_limit[4]_i_6_n_0 ; wire \three_dec_max_limit[5]_i_1_n_0 ; wire \three_dec_max_limit[6]_i_1_n_0 ; wire \three_dec_max_limit[7]_i_1_n_0 ; wire \three_dec_max_limit[8]_i_1_n_0 ; wire \three_dec_max_limit[8]_i_3_n_0 ; wire \three_dec_max_limit[8]_i_4_n_0 ; wire \three_dec_max_limit[8]_i_5_n_0 ; wire \three_dec_max_limit[8]_i_6_n_0 ; wire \three_dec_max_limit[9]_i_1_n_0 ; wire \three_dec_max_limit_reg[11]_i_2_n_2 ; wire \three_dec_max_limit_reg[11]_i_2_n_3 ; wire \three_dec_max_limit_reg[11]_i_2_n_5 ; wire \three_dec_max_limit_reg[11]_i_2_n_6 ; wire \three_dec_max_limit_reg[11]_i_2_n_7 ; wire \three_dec_max_limit_reg[1]_i_2_n_0 ; wire \three_dec_max_limit_reg[4]_i_2_n_0 ; wire \three_dec_max_limit_reg[4]_i_2_n_1 ; wire \three_dec_max_limit_reg[4]_i_2_n_2 ; wire \three_dec_max_limit_reg[4]_i_2_n_3 ; wire \three_dec_max_limit_reg[4]_i_2_n_4 ; wire \three_dec_max_limit_reg[4]_i_2_n_5 ; wire \three_dec_max_limit_reg[4]_i_2_n_6 ; wire \three_dec_max_limit_reg[8]_i_2_n_0 ; wire \three_dec_max_limit_reg[8]_i_2_n_1 ; wire \three_dec_max_limit_reg[8]_i_2_n_2 ; wire \three_dec_max_limit_reg[8]_i_2_n_3 ; wire \three_dec_max_limit_reg[8]_i_2_n_4 ; wire \three_dec_max_limit_reg[8]_i_2_n_5 ; wire \three_dec_max_limit_reg[8]_i_2_n_6 ; wire \three_dec_max_limit_reg[8]_i_2_n_7 ; wire [11:0]three_dec_min_limit; wire \three_dec_min_limit[11]_i_2_n_0 ; wire \three_dec_min_limit[11]_i_3_n_0 ; wire \three_dec_min_limit[5]_i_2_n_0 ; wire \three_dec_min_limit[5]_i_3_n_0 ; wire \three_dec_min_limit[5]_i_4_n_0 ; wire \three_dec_min_limit[5]_i_5_n_0 ; wire \three_dec_min_limit[9]_i_2_n_0 ; wire \three_dec_min_limit[9]_i_3_n_0 ; wire \three_dec_min_limit[9]_i_4_n_0 ; wire \three_dec_min_limit[9]_i_5_n_0 ; wire [11:2]three_dec_min_limit_nxt; wire \three_dec_min_limit_reg[11]_i_1_n_3 ; wire \three_dec_min_limit_reg[5]_i_1_n_0 ; wire \three_dec_min_limit_reg[5]_i_1_n_1 ; wire \three_dec_min_limit_reg[5]_i_1_n_2 ; wire \three_dec_min_limit_reg[5]_i_1_n_3 ; wire \three_dec_min_limit_reg[9]_i_1_n_0 ; wire \three_dec_min_limit_reg[9]_i_1_n_1 ; wire \three_dec_min_limit_reg[9]_i_1_n_2 ; wire \three_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]three_inc_max_limit; wire \three_inc_max_limit[11]_i_2_n_0 ; wire \three_inc_max_limit[11]_i_3_n_0 ; wire \three_inc_max_limit[11]_i_4_n_0 ; wire \three_inc_max_limit[4]_i_2_n_0 ; wire \three_inc_max_limit[4]_i_3_n_0 ; wire \three_inc_max_limit[4]_i_4_n_0 ; wire \three_inc_max_limit[4]_i_5_n_0 ; wire \three_inc_max_limit[8]_i_2_n_0 ; wire \three_inc_max_limit[8]_i_3_n_0 ; wire \three_inc_max_limit[8]_i_4_n_0 ; wire \three_inc_max_limit[8]_i_5_n_0 ; wire [11:1]three_inc_max_limit_nxt; wire \three_inc_max_limit_reg[11]_i_1_n_2 ; wire \three_inc_max_limit_reg[11]_i_1_n_3 ; wire \three_inc_max_limit_reg[4]_i_1_n_0 ; wire \three_inc_max_limit_reg[4]_i_1_n_1 ; wire \three_inc_max_limit_reg[4]_i_1_n_2 ; wire \three_inc_max_limit_reg[4]_i_1_n_3 ; wire \three_inc_max_limit_reg[8]_i_1_n_0 ; wire \three_inc_max_limit_reg[8]_i_1_n_1 ; wire \three_inc_max_limit_reg[8]_i_1_n_2 ; wire \three_inc_max_limit_reg[8]_i_1_n_3 ; wire [11:1]three_inc_min_limit; wire \three_inc_min_limit[11]_i_2_n_0 ; wire \three_inc_min_limit[11]_i_3_n_0 ; wire \three_inc_min_limit[5]_i_2_n_0 ; wire \three_inc_min_limit[5]_i_3_n_0 ; wire \three_inc_min_limit[5]_i_4_n_0 ; wire \three_inc_min_limit[5]_i_5_n_0 ; wire \three_inc_min_limit[9]_i_2_n_0 ; wire \three_inc_min_limit[9]_i_3_n_0 ; wire \three_inc_min_limit[9]_i_4_n_0 ; wire \three_inc_min_limit[9]_i_5_n_0 ; wire [11:2]three_inc_min_limit_nxt; wire \three_inc_min_limit_reg[11]_i_1_n_3 ; wire \three_inc_min_limit_reg[5]_i_1_n_0 ; wire \three_inc_min_limit_reg[5]_i_1_n_1 ; wire \three_inc_min_limit_reg[5]_i_1_n_2 ; wire \three_inc_min_limit_reg[5]_i_1_n_3 ; wire \three_inc_min_limit_reg[9]_i_1_n_0 ; wire \three_inc_min_limit_reg[9]_i_1_n_1 ; wire \three_inc_min_limit_reg[9]_i_1_n_2 ; wire \three_inc_min_limit_reg[9]_i_1_n_3 ; wire [11:0]two_dec_max_limit; wire \two_dec_max_limit[0]_i_1_n_0 ; wire \two_dec_max_limit[11]_i_2_n_0 ; wire \two_dec_max_limit[11]_i_3_n_0 ; wire \two_dec_max_limit[11]_i_4_n_0 ; wire \two_dec_max_limit[4]_i_2_n_0 ; wire \two_dec_max_limit[4]_i_3_n_0 ; wire \two_dec_max_limit[4]_i_4_n_0 ; wire \two_dec_max_limit[4]_i_5_n_0 ; wire \two_dec_max_limit[8]_i_2_n_0 ; wire \two_dec_max_limit[8]_i_3_n_0 ; wire \two_dec_max_limit[8]_i_4_n_0 ; wire \two_dec_max_limit[8]_i_5_n_0 ; wire [11:1]two_dec_max_limit_nxt; wire \two_dec_max_limit_reg[11]_i_1_n_2 ; wire \two_dec_max_limit_reg[11]_i_1_n_3 ; wire \two_dec_max_limit_reg[4]_i_1_n_0 ; wire \two_dec_max_limit_reg[4]_i_1_n_1 ; wire \two_dec_max_limit_reg[4]_i_1_n_2 ; wire \two_dec_max_limit_reg[4]_i_1_n_3 ; wire \two_dec_max_limit_reg[8]_i_1_n_0 ; wire \two_dec_max_limit_reg[8]_i_1_n_1 ; wire \two_dec_max_limit_reg[8]_i_1_n_2 ; wire \two_dec_max_limit_reg[8]_i_1_n_3 ; wire [11:1]two_dec_min_limit; wire \two_dec_min_limit[11]_i_2_n_0 ; wire \two_dec_min_limit[11]_i_3_n_0 ; wire \two_dec_min_limit[5]_i_2_n_0 ; wire \two_dec_min_limit[5]_i_3_n_0 ; wire \two_dec_min_limit[5]_i_4_n_0 ; wire \two_dec_min_limit[5]_i_5_n_0 ; wire \two_dec_min_limit[9]_i_2_n_0 ; wire \two_dec_min_limit[9]_i_3_n_0 ; wire \two_dec_min_limit[9]_i_4_n_0 ; wire \two_dec_min_limit[9]_i_5_n_0 ; wire [11:2]two_dec_min_limit_nxt; wire \two_dec_min_limit_reg[11]_i_1_n_3 ; wire \two_dec_min_limit_reg[5]_i_1_n_0 ; wire \two_dec_min_limit_reg[5]_i_1_n_1 ; wire \two_dec_min_limit_reg[5]_i_1_n_2 ; wire \two_dec_min_limit_reg[5]_i_1_n_3 ; wire \two_dec_min_limit_reg[9]_i_1_n_0 ; wire \two_dec_min_limit_reg[9]_i_1_n_1 ; wire \two_dec_min_limit_reg[9]_i_1_n_2 ; wire \two_dec_min_limit_reg[9]_i_1_n_3 ; wire [11:1]two_inc_max_limit; wire \two_inc_max_limit[11]_i_2_n_0 ; wire \two_inc_max_limit[11]_i_3_n_0 ; wire \two_inc_max_limit[11]_i_4_n_0 ; wire \two_inc_max_limit[4]_i_2_n_0 ; wire \two_inc_max_limit[4]_i_3_n_0 ; wire \two_inc_max_limit[4]_i_4_n_0 ; wire \two_inc_max_limit[4]_i_5_n_0 ; wire \two_inc_max_limit[8]_i_2_n_0 ; wire \two_inc_max_limit[8]_i_3_n_0 ; wire \two_inc_max_limit[8]_i_4_n_0 ; wire \two_inc_max_limit[8]_i_5_n_0 ; wire [11:1]two_inc_max_limit_nxt; wire \two_inc_max_limit_reg[11]_i_1_n_2 ; wire \two_inc_max_limit_reg[11]_i_1_n_3 ; wire \two_inc_max_limit_reg[4]_i_1_n_0 ; wire \two_inc_max_limit_reg[4]_i_1_n_1 ; wire \two_inc_max_limit_reg[4]_i_1_n_2 ; wire \two_inc_max_limit_reg[4]_i_1_n_3 ; wire \two_inc_max_limit_reg[8]_i_1_n_0 ; wire \two_inc_max_limit_reg[8]_i_1_n_1 ; wire \two_inc_max_limit_reg[8]_i_1_n_2 ; wire \two_inc_max_limit_reg[8]_i_1_n_3 ; wire [11:1]two_inc_min_limit; wire \two_inc_min_limit[11]_i_2_n_0 ; wire \two_inc_min_limit[11]_i_3_n_0 ; wire \two_inc_min_limit[5]_i_2_n_0 ; wire \two_inc_min_limit[5]_i_3_n_0 ; wire \two_inc_min_limit[5]_i_4_n_0 ; wire \two_inc_min_limit[5]_i_5_n_0 ; wire \two_inc_min_limit[9]_i_2_n_0 ; wire \two_inc_min_limit[9]_i_3_n_0 ; wire \two_inc_min_limit[9]_i_4_n_0 ; wire \two_inc_min_limit[9]_i_5_n_0 ; wire [11:2]two_inc_min_limit_nxt; wire \two_inc_min_limit_reg[11]_i_1_n_3 ; wire \two_inc_min_limit_reg[5]_i_1_n_0 ; wire \two_inc_min_limit_reg[5]_i_1_n_1 ; wire \two_inc_min_limit_reg[5]_i_1_n_2 ; wire \two_inc_min_limit_reg[5]_i_1_n_3 ; wire \two_inc_min_limit_reg[9]_i_1_n_0 ; wire \two_inc_min_limit_reg[9]_i_1_n_1 ; wire \two_inc_min_limit_reg[9]_i_1_n_2 ; wire \two_inc_min_limit_reg[9]_i_1_n_3 ; wire update_temp_101__0; wire update_temp_102; wire [3:1]\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [3:2]\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED; wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED; wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED; wire [2:2]\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED ; wire [3:3]\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED ; wire [3:0]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED ; wire [3:1]\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ; wire [3:0]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ; wire [3:1]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ; wire [0:0]\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ; wire [3:2]\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ; wire [0:0]\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ; wire [3:1]\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair248" *) LUT4 #( .INIT(16'h3331)) \calib_sel[1]_i_2 (.I0(calib_complete), .I1(rstdiv0_sync_r1_reg_rep__25), .I2(tempmon_pi_f_inc), .I3(tempmon_pi_f_dec), .O(\calib_zero_inputs_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT5 #( .INIT(32'h00A800AA)) \calib_sel[3]_i_1 (.I0(ctl_lane_sel), .I1(tempmon_pi_f_dec), .I2(tempmon_pi_f_inc), .I3(rstdiv0_sync_r1_reg_rep__25), .I4(calib_complete), .O(D)); LUT6 #( .INIT(64'h00000200FFFFFFFF)) \calib_zero_inputs[1]_i_1 (.I0(cmd_delay_start0), .I1(tempmon_pi_f_inc), .I2(tempmon_pi_f_dec), .I3(delay_done_r4_reg), .I4(calib_in_common), .I5(\calib_zero_inputs_reg[1]_0 ), .O(\calib_zero_inputs_reg[1] )); FDRE \device_temp_101_reg[0] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [0]), .Q(device_temp_101[0]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[10] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [10]), .Q(device_temp_101[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[11] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [11]), .Q(device_temp_101[11]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[1] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [1]), .Q(device_temp_101[1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[2] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [2]), .Q(device_temp_101[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[3] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [3]), .Q(device_temp_101[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[4] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [4]), .Q(device_temp_101[4]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[5] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [5]), .Q(device_temp_101[5]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[6] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [6]), .Q(device_temp_101[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[7] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [7]), .Q(device_temp_101[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[8] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [8]), .Q(device_temp_101[8]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \device_temp_101_reg[9] (.C(CLK), .CE(1'b1), .D(\device_temp_r_reg[11] [9]), .Q(device_temp_101[9]), .R(rstdiv0_sync_r1_reg_rep__5)); LUT5 #( .INIT(32'h00000800)) \device_temp_init[11]_i_1 (.I0(\device_temp_init[11]_i_2_n_0 ), .I1(\device_temp_init[11]_i_3_n_0 ), .I2(tempmon_state[0]), .I3(tempmon_state[1]), .I4(tempmon_state[2]), .O(tempmon_state_init)); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT4 #( .INIT(16'h0001)) \device_temp_init[11]_i_2 (.I0(tempmon_state[6]), .I1(tempmon_state[5]), .I2(tempmon_state[4]), .I3(tempmon_state[3]), .O(\device_temp_init[11]_i_2_n_0 )); LUT4 #( .INIT(16'h0001)) \device_temp_init[11]_i_3 (.I0(tempmon_state[10]), .I1(tempmon_state[9]), .I2(tempmon_state[8]), .I3(tempmon_state[7]), .O(\device_temp_init[11]_i_3_n_0 )); FDRE \device_temp_init_reg[0] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[0]), .Q(device_temp_init[0]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[10] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[10]), .Q(device_temp_init[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[11] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[11]), .Q(device_temp_init[11]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[1] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[1]), .Q(device_temp_init[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[2] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[2]), .Q(device_temp_init[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[3] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[3]), .Q(device_temp_init[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[4] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[4]), .Q(device_temp_init[4]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[5] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[5]), .Q(device_temp_init[5]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[6] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[6]), .Q(device_temp_init[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[7] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[7]), .Q(device_temp_init[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[8] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[8]), .Q(device_temp_init[8]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \device_temp_init_reg[9] (.C(CLK), .CE(tempmon_state_init), .D(device_temp_101[9]), .Q(device_temp_init[9]), .R(rstdiv0_sync_r1_reg_rep__4)); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[11]_i_2 (.I0(three_dec_max_limit[11]), .O(\four_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[11]_i_3 (.I0(three_dec_max_limit[10]), .O(\four_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[5]_i_2 (.I0(three_dec_max_limit[5]), .O(\four_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[5]_i_3 (.I0(three_dec_max_limit[4]), .O(\four_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[5]_i_4 (.I0(three_dec_max_limit[3]), .O(\four_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \four_dec_min_limit[5]_i_5 (.I0(three_dec_max_limit[2]), .O(\four_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_2 (.I0(three_dec_max_limit[9]), .O(\four_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_3 (.I0(three_dec_max_limit[8]), .O(\four_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_4 (.I0(three_dec_max_limit[7]), .O(\four_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_dec_min_limit[9]_i_5 (.I0(three_dec_max_limit[6]), .O(\four_dec_min_limit[9]_i_5_n_0 )); FDRE \four_dec_min_limit_reg[0] (.C(CLK), .CE(1'b1), .D(three_dec_max_limit[0]), .Q(four_dec_min_limit[0]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[10]), .Q(four_dec_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[11]), .Q(four_dec_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \four_dec_min_limit_reg[11]_i_1 (.CI(\four_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\four_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}), .O({\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\four_dec_min_limit[11]_i_2_n_0 ,\four_dec_min_limit[11]_i_3_n_0 })); FDRE \four_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(three_dec_max_limit[1]), .Q(four_dec_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[2]), .Q(four_dec_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[3]), .Q(four_dec_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[4]), .Q(four_dec_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[5]), .Q(four_dec_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \four_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\four_dec_min_limit_reg[5]_i_1_n_0 ,\four_dec_min_limit_reg[5]_i_1_n_1 ,\four_dec_min_limit_reg[5]_i_1_n_2 ,\four_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({three_dec_max_limit[5:3],1'b0}), .O(four_dec_min_limit_nxt[5:2]), .S({\four_dec_min_limit[5]_i_2_n_0 ,\four_dec_min_limit[5]_i_3_n_0 ,\four_dec_min_limit[5]_i_4_n_0 ,\four_dec_min_limit[5]_i_5_n_0 })); FDRE \four_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[6]), .Q(four_dec_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[7]), .Q(four_dec_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[8]), .Q(four_dec_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \four_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(four_dec_min_limit_nxt[9]), .Q(four_dec_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \four_dec_min_limit_reg[9]_i_1 (.CI(\four_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\four_dec_min_limit_reg[9]_i_1_n_0 ,\four_dec_min_limit_reg[9]_i_1_n_1 ,\four_dec_min_limit_reg[9]_i_1_n_2 ,\four_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(three_dec_max_limit[9:6]), .O(four_dec_min_limit_nxt[9:6]), .S({\four_dec_min_limit[9]_i_2_n_0 ,\four_dec_min_limit[9]_i_3_n_0 ,\four_dec_min_limit[9]_i_4_n_0 ,\four_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\four_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\four_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \four_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\four_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[1]_i_2 (.I0(device_temp_init[1]), .O(\four_inc_max_limit[1]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\four_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\four_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\four_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\four_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \four_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\four_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\four_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \four_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\four_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \four_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\four_inc_max_limit[8]_i_5_n_0 )); FDRE \four_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[10]), .Q(four_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \four_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[11]), .Q(four_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \four_inc_max_limit_reg[11]_i_1 (.CI(\four_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\four_inc_max_limit_reg[11]_i_1_n_2 ,\four_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10],1'b0}), .O({\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],four_inc_max_limit_nxt[11:9]}), .S({1'b0,\four_inc_max_limit[11]_i_2_n_0 ,\four_inc_max_limit[11]_i_3_n_0 ,\four_inc_max_limit[11]_i_4_n_0 })); FDRE \four_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[1]), .Q(four_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__5)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \four_inc_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],four_inc_max_limit_nxt[1]}), .S({\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\four_inc_max_limit[1]_i_2_n_0 })); FDRE \four_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[2]), .Q(four_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \four_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[3]), .Q(four_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \four_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[4]), .Q(four_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \four_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\four_inc_max_limit_reg[4]_i_1_n_0 ,\four_inc_max_limit_reg[4]_i_1_n_1 ,\four_inc_max_limit_reg[4]_i_1_n_2 ,\four_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI(device_temp_init[4:1]), .O({four_inc_max_limit_nxt[4:2],two_inc_max_limit_nxt[1]}), .S({\four_inc_max_limit[4]_i_2_n_0 ,\four_inc_max_limit[4]_i_3_n_0 ,\four_inc_max_limit[4]_i_4_n_0 ,\four_inc_max_limit[4]_i_5_n_0 })); FDRE \four_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[5]), .Q(four_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \four_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[6]), .Q(four_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \four_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[7]), .Q(four_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \four_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[8]), .Q(four_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \four_inc_max_limit_reg[8]_i_1 (.CI(\four_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\four_inc_max_limit_reg[8]_i_1_n_0 ,\four_inc_max_limit_reg[8]_i_1_n_1 ,\four_inc_max_limit_reg[8]_i_1_n_2 ,\four_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,device_temp_init[7],1'b0,device_temp_init[5]}), .O(four_inc_max_limit_nxt[8:5]), .S({\four_inc_max_limit[8]_i_2_n_0 ,\four_inc_max_limit[8]_i_3_n_0 ,\four_inc_max_limit[8]_i_4_n_0 ,\four_inc_max_limit[8]_i_5_n_0 })); FDRE \four_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit_nxt[9]), .Q(four_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__5)); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'hFE00)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_2 (.I0(tempmon_pi_f_inc), .I1(tempmon_pi_f_dec), .I2(oclkdelay_calib_done_r_reg), .I3(ck_addr_cmd_delay_done), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'hFDFFFDFDFFFFFFFF)) \gen_byte_sel_div1.calib_in_common_i_4 (.I0(cmd_delay_start0), .I1(tempmon_pi_f_inc), .I2(tempmon_pi_f_dec), .I3(fine_adjust_done_r_reg), .I4(rd_data_offset_cal_done), .I5(ck_addr_cmd_delay_done), .O(\gen_byte_sel_div1.calib_in_common_reg )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\neutral_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\neutral_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\neutral_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\neutral_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\neutral_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\neutral_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\neutral_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\neutral_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\neutral_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\neutral_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\neutral_max_limit[8]_i_5_n_0 )); FDRE \neutral_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[10]), .Q(neutral_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \neutral_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[11]), .Q(neutral_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \neutral_max_limit_reg[11]_i_1 (.CI(\neutral_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\neutral_max_limit_reg[11]_i_1_n_2 ,\neutral_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED [3],neutral_max_limit_nxt[11:9]}), .S({1'b0,\neutral_max_limit[11]_i_2_n_0 ,\neutral_max_limit[11]_i_3_n_0 ,\neutral_max_limit[11]_i_4_n_0 })); FDRE \neutral_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[1]), .Q(neutral_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \neutral_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],neutral_max_limit_nxt[1]}), .S({\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\four_inc_max_limit[1]_i_2_n_0 })); FDRE \neutral_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[2]), .Q(neutral_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \neutral_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[3]), .Q(neutral_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \neutral_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[4]), .Q(neutral_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \neutral_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\neutral_max_limit_reg[4]_i_1_n_0 ,\neutral_max_limit_reg[4]_i_1_n_1 ,\neutral_max_limit_reg[4]_i_1_n_2 ,\neutral_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({device_temp_init[4],1'b0,device_temp_init[2:1]}), .O({neutral_max_limit_nxt[4:2],\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\neutral_max_limit[4]_i_2_n_0 ,\neutral_max_limit[4]_i_3_n_0 ,\neutral_max_limit[4]_i_4_n_0 ,\neutral_max_limit[4]_i_5_n_0 })); FDRE \neutral_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[5]), .Q(neutral_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \neutral_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[6]), .Q(neutral_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \neutral_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[7]), .Q(neutral_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \neutral_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[8]), .Q(neutral_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \neutral_max_limit_reg[8]_i_1 (.CI(\neutral_max_limit_reg[4]_i_1_n_0 ), .CO({\neutral_max_limit_reg[8]_i_1_n_0 ,\neutral_max_limit_reg[8]_i_1_n_1 ,\neutral_max_limit_reg[8]_i_1_n_2 ,\neutral_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[6:5]}), .O(neutral_max_limit_nxt[8:5]), .S({\neutral_max_limit[8]_i_2_n_0 ,\neutral_max_limit[8]_i_3_n_0 ,\neutral_max_limit[8]_i_4_n_0 ,\neutral_max_limit[8]_i_5_n_0 })); FDRE \neutral_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(neutral_max_limit_nxt[9]), .Q(neutral_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \neutral_min_limit[11]_i_2 (.I0(one_inc_max_limit[11]), .O(\neutral_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[11]_i_3 (.I0(one_inc_max_limit[10]), .O(\neutral_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[5]_i_2 (.I0(one_inc_max_limit[5]), .O(\neutral_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[5]_i_3 (.I0(one_inc_max_limit[4]), .O(\neutral_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[5]_i_4 (.I0(one_inc_max_limit[3]), .O(\neutral_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \neutral_min_limit[5]_i_5 (.I0(one_inc_max_limit[2]), .O(\neutral_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_2 (.I0(one_inc_max_limit[9]), .O(\neutral_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_3 (.I0(one_inc_max_limit[8]), .O(\neutral_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_4 (.I0(one_inc_max_limit[7]), .O(\neutral_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \neutral_min_limit[9]_i_5 (.I0(one_inc_max_limit[6]), .O(\neutral_min_limit[9]_i_5_n_0 )); FDRE \neutral_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[10]), .Q(neutral_min_limit[10]), .R(SS)); FDRE \neutral_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[11]), .Q(neutral_min_limit[11]), .R(SS)); CARRY4 \neutral_min_limit_reg[11]_i_1 (.CI(\neutral_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\neutral_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}), .O({\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\neutral_min_limit[11]_i_2_n_0 ,\neutral_min_limit[11]_i_3_n_0 })); FDRE \neutral_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit[1]), .Q(neutral_min_limit[1]), .R(SS)); FDRE \neutral_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[2]), .Q(neutral_min_limit[2]), .R(SS)); FDRE \neutral_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[3]), .Q(neutral_min_limit[3]), .R(SS)); FDRE \neutral_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[4]), .Q(neutral_min_limit[4]), .R(SS)); FDRE \neutral_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[5]), .Q(neutral_min_limit[5]), .R(SS)); CARRY4 \neutral_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\neutral_min_limit_reg[5]_i_1_n_0 ,\neutral_min_limit_reg[5]_i_1_n_1 ,\neutral_min_limit_reg[5]_i_1_n_2 ,\neutral_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({one_inc_max_limit[5:3],1'b0}), .O(neutral_min_limit_nxt[5:2]), .S({\neutral_min_limit[5]_i_2_n_0 ,\neutral_min_limit[5]_i_3_n_0 ,\neutral_min_limit[5]_i_4_n_0 ,\neutral_min_limit[5]_i_5_n_0 })); FDRE \neutral_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[6]), .Q(neutral_min_limit[6]), .R(SS)); FDRE \neutral_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[7]), .Q(neutral_min_limit[7]), .R(SS)); FDRE \neutral_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[8]), .Q(neutral_min_limit[8]), .R(SS)); FDRE \neutral_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(neutral_min_limit_nxt[9]), .Q(neutral_min_limit[9]), .R(SS)); CARRY4 \neutral_min_limit_reg[9]_i_1 (.CI(\neutral_min_limit_reg[5]_i_1_n_0 ), .CO({\neutral_min_limit_reg[9]_i_1_n_0 ,\neutral_min_limit_reg[9]_i_1_n_1 ,\neutral_min_limit_reg[9]_i_1_n_2 ,\neutral_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(one_inc_max_limit[9:6]), .O(neutral_min_limit_nxt[9:6]), .S({\neutral_min_limit[9]_i_2_n_0 ,\neutral_min_limit[9]_i_3_n_0 ,\neutral_min_limit[9]_i_4_n_0 ,\neutral_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\one_dec_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\one_dec_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\one_dec_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\one_dec_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\one_dec_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\one_dec_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\one_dec_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\one_dec_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\one_dec_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\one_dec_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\one_dec_max_limit[8]_i_5_n_0 )); FDRE \one_dec_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[10]), .Q(one_dec_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_dec_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[11]), .Q(one_dec_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_dec_max_limit_reg[11]_i_1 (.CI(\one_dec_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_dec_max_limit_reg[11]_i_1_n_2 ,\one_dec_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_dec_max_limit_nxt[11:9]}), .S({1'b0,\one_dec_max_limit[11]_i_2_n_0 ,\one_dec_max_limit[11]_i_3_n_0 ,\one_dec_max_limit[11]_i_4_n_0 })); FDRE \one_dec_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[1]), .Q(one_dec_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \one_dec_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_dec_max_limit_nxt[1]}), .S({\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]})); FDRE \one_dec_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[2]), .Q(one_dec_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_dec_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[3]), .Q(one_dec_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_dec_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[4]), .Q(one_dec_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_dec_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\one_dec_max_limit_reg[4]_i_1_n_0 ,\one_dec_max_limit_reg[4]_i_1_n_1 ,\one_dec_max_limit_reg[4]_i_1_n_2 ,\one_dec_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,1'b0,device_temp_init[2],1'b0}), .O({one_dec_max_limit_nxt[4:2],\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\one_dec_max_limit[4]_i_2_n_0 ,\one_dec_max_limit[4]_i_3_n_0 ,\one_dec_max_limit[4]_i_4_n_0 ,\one_dec_max_limit[4]_i_5_n_0 })); FDRE \one_dec_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[5]), .Q(one_dec_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_dec_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[6]), .Q(one_dec_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_dec_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[7]), .Q(one_dec_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_dec_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[8]), .Q(one_dec_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_dec_max_limit_reg[8]_i_1 (.CI(\one_dec_max_limit_reg[4]_i_1_n_0 ), .CO({\one_dec_max_limit_reg[8]_i_1_n_0 ,\one_dec_max_limit_reg[8]_i_1_n_1 ,\one_dec_max_limit_reg[8]_i_1_n_2 ,\one_dec_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8],1'b0,device_temp_init[6:5]}), .O(one_dec_max_limit_nxt[8:5]), .S({\one_dec_max_limit[8]_i_2_n_0 ,\one_dec_max_limit[8]_i_3_n_0 ,\one_dec_max_limit[8]_i_4_n_0 ,\one_dec_max_limit[8]_i_5_n_0 })); FDRE \one_dec_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit_nxt[9]), .Q(one_dec_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[11]_i_2 (.I0(neutral_max_limit[11]), .O(\one_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[11]_i_3 (.I0(neutral_max_limit[10]), .O(\one_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[5]_i_2 (.I0(neutral_max_limit[5]), .O(\one_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[5]_i_3 (.I0(neutral_max_limit[4]), .O(\one_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[5]_i_4 (.I0(neutral_max_limit[3]), .O(\one_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_dec_min_limit[5]_i_5 (.I0(neutral_max_limit[2]), .O(\one_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_2 (.I0(neutral_max_limit[9]), .O(\one_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_3 (.I0(neutral_max_limit[8]), .O(\one_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_4 (.I0(neutral_max_limit[7]), .O(\one_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \one_dec_min_limit[9]_i_5 (.I0(neutral_max_limit[6]), .O(\one_dec_min_limit[9]_i_5_n_0 )); FDRE \one_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[10]), .Q(one_dec_min_limit[10]), .R(SS)); FDRE \one_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[11]), .Q(one_dec_min_limit[11]), .R(SS)); CARRY4 \one_dec_min_limit_reg[11]_i_1 (.CI(\one_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}), .O({\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\one_dec_min_limit[11]_i_2_n_0 ,\one_dec_min_limit[11]_i_3_n_0 })); FDRE \one_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(neutral_max_limit[1]), .Q(one_dec_min_limit[1]), .R(SS)); FDRE \one_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[2]), .Q(one_dec_min_limit[2]), .R(SS)); FDRE \one_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[3]), .Q(one_dec_min_limit[3]), .R(SS)); FDRE \one_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[4]), .Q(one_dec_min_limit[4]), .R(SS)); FDRE \one_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[5]), .Q(one_dec_min_limit[5]), .R(SS)); CARRY4 \one_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\one_dec_min_limit_reg[5]_i_1_n_0 ,\one_dec_min_limit_reg[5]_i_1_n_1 ,\one_dec_min_limit_reg[5]_i_1_n_2 ,\one_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({neutral_max_limit[5:3],1'b0}), .O(one_dec_min_limit_nxt[5:2]), .S({\one_dec_min_limit[5]_i_2_n_0 ,\one_dec_min_limit[5]_i_3_n_0 ,\one_dec_min_limit[5]_i_4_n_0 ,\one_dec_min_limit[5]_i_5_n_0 })); FDRE \one_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[6]), .Q(one_dec_min_limit[6]), .R(SS)); FDRE \one_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[7]), .Q(one_dec_min_limit[7]), .R(SS)); FDRE \one_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[8]), .Q(one_dec_min_limit[8]), .R(SS)); FDRE \one_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_dec_min_limit_nxt[9]), .Q(one_dec_min_limit[9]), .R(SS)); CARRY4 \one_dec_min_limit_reg[9]_i_1 (.CI(\one_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\one_dec_min_limit_reg[9]_i_1_n_0 ,\one_dec_min_limit_reg[9]_i_1_n_1 ,\one_dec_min_limit_reg[9]_i_1_n_2 ,\one_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(neutral_max_limit[9:6]), .O(one_dec_min_limit_nxt[9:6]), .S({\one_dec_min_limit[9]_i_2_n_0 ,\one_dec_min_limit[9]_i_3_n_0 ,\one_dec_min_limit[9]_i_4_n_0 ,\one_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\one_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\one_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\one_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\one_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\one_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\one_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\one_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\one_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\one_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\one_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\one_inc_max_limit[8]_i_5_n_0 )); FDRE \one_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[10]), .Q(one_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[11]), .Q(one_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_inc_max_limit_reg[11]_i_1 (.CI(\one_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_inc_max_limit_reg[11]_i_1_n_2 ,\one_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10:9]}), .O({\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_inc_max_limit_nxt[11:9]}), .S({1'b0,\one_inc_max_limit[11]_i_2_n_0 ,\one_inc_max_limit[11]_i_3_n_0 ,\one_inc_max_limit[11]_i_4_n_0 })); FDRE \one_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[1]), .Q(one_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \one_inc_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_inc_max_limit_nxt[1]}), .S({\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]})); FDRE \one_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[2]), .Q(one_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[3]), .Q(one_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[4]), .Q(one_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\one_inc_max_limit_reg[4]_i_1_n_0 ,\one_inc_max_limit_reg[4]_i_1_n_1 ,\one_inc_max_limit_reg[4]_i_1_n_2 ,\one_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,device_temp_init[3],1'b0,1'b0}), .O({one_inc_max_limit_nxt[4:2],\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\one_inc_max_limit[4]_i_2_n_0 ,\one_inc_max_limit[4]_i_3_n_0 ,\one_inc_max_limit[4]_i_4_n_0 ,\one_inc_max_limit[4]_i_5_n_0 })); FDRE \one_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[5]), .Q(one_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[6]), .Q(one_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[7]), .Q(one_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \one_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[8]), .Q(one_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \one_inc_max_limit_reg[8]_i_1 (.CI(\one_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\one_inc_max_limit_reg[8]_i_1_n_0 ,\one_inc_max_limit_reg[8]_i_1_n_1 ,\one_inc_max_limit_reg[8]_i_1_n_2 ,\one_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8:7],1'b0,1'b0}), .O(one_inc_max_limit_nxt[8:5]), .S({\one_inc_max_limit[8]_i_2_n_0 ,\one_inc_max_limit[8]_i_3_n_0 ,\one_inc_max_limit[8]_i_4_n_0 ,\one_inc_max_limit[8]_i_5_n_0 })); FDRE \one_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_inc_max_limit_nxt[9]), .Q(one_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[11]_i_2 (.I0(two_inc_max_limit[11]), .O(\one_inc_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[11]_i_3 (.I0(two_inc_max_limit[10]), .O(\one_inc_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[5]_i_2 (.I0(two_inc_max_limit[5]), .O(\one_inc_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[5]_i_3 (.I0(two_inc_max_limit[4]), .O(\one_inc_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[5]_i_4 (.I0(two_inc_max_limit[3]), .O(\one_inc_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \one_inc_min_limit[5]_i_5 (.I0(two_inc_max_limit[2]), .O(\one_inc_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_2 (.I0(two_inc_max_limit[9]), .O(\one_inc_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_3 (.I0(two_inc_max_limit[8]), .O(\one_inc_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_4 (.I0(two_inc_max_limit[7]), .O(\one_inc_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \one_inc_min_limit[9]_i_5 (.I0(two_inc_max_limit[6]), .O(\one_inc_min_limit[9]_i_5_n_0 )); FDRE \one_inc_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[10]), .Q(one_inc_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[11]), .Q(one_inc_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \one_inc_min_limit_reg[11]_i_1 (.CI(\one_inc_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_inc_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}), .O({\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\one_inc_min_limit[11]_i_2_n_0 ,\one_inc_min_limit[11]_i_3_n_0 })); FDRE \one_inc_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit[1]), .Q(one_inc_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[2]), .Q(one_inc_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[3]), .Q(one_inc_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[4]), .Q(one_inc_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[5]), .Q(one_inc_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \one_inc_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\one_inc_min_limit_reg[5]_i_1_n_0 ,\one_inc_min_limit_reg[5]_i_1_n_1 ,\one_inc_min_limit_reg[5]_i_1_n_2 ,\one_inc_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({two_inc_max_limit[5:3],1'b0}), .O(one_inc_min_limit_nxt[5:2]), .S({\one_inc_min_limit[5]_i_2_n_0 ,\one_inc_min_limit[5]_i_3_n_0 ,\one_inc_min_limit[5]_i_4_n_0 ,\one_inc_min_limit[5]_i_5_n_0 })); FDRE \one_inc_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[6]), .Q(one_inc_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[7]), .Q(one_inc_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[8]), .Q(one_inc_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \one_inc_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(one_inc_min_limit_nxt[9]), .Q(one_inc_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \one_inc_min_limit_reg[9]_i_1 (.CI(\one_inc_min_limit_reg[5]_i_1_n_0 ), .CO({\one_inc_min_limit_reg[9]_i_1_n_0 ,\one_inc_min_limit_reg[9]_i_1_n_1 ,\one_inc_min_limit_reg[9]_i_1_n_2 ,\one_inc_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(two_inc_max_limit[9:6]), .O(one_inc_min_limit_nxt[9:6]), .S({\one_inc_min_limit[9]_i_2_n_0 ,\one_inc_min_limit[9]_i_3_n_0 ,\one_inc_min_limit[9]_i_4_n_0 ,\one_inc_min_limit[9]_i_5_n_0 })); LUT4 #( .INIT(16'hF080)) pi_f_dec_i_1 (.I0(update_temp_102), .I1(pi_f_dec_i_2_n_0), .I2(\tempmon_state[10]_i_7_n_0 ), .I3(\tempmon_state[10]_i_3_n_0 ), .O(pi_f_dec_nxt)); LUT6 #( .INIT(64'hFFFFF888F888F888)) pi_f_dec_i_2 (.I0(temp_cmp_three_inc_max_102), .I1(tempmon_state[3]), .I2(tempmon_state[5]), .I3(temp_cmp_one_inc_max_102), .I4(tempmon_state[4]), .I5(temp_cmp_two_inc_max_102), .O(pi_f_dec_i_2_n_0)); FDRE pi_f_dec_reg (.C(CLK), .CE(1'b1), .D(pi_f_dec_nxt), .Q(tempmon_pi_f_dec), .R(SS)); LUT6 #( .INIT(64'hEFEEEEEEEEEEEEEE)) pi_f_inc_i_1 (.I0(pi_f_inc_i_2_n_0), .I1(pi_f_inc_i_3_n_0), .I2(temp_gte_three_dec_max), .I3(tempmon_state[9]), .I4(temp_cmp_three_dec_min_102), .I5(pi_f_inc_i_5_n_0), .O(pi_f_inc_nxt)); LUT4 #( .INIT(16'h0800)) pi_f_inc_i_10 (.I0(tempmon_state[5]), .I1(update_temp_102), .I2(temp_cmp_one_inc_max_102), .I3(temp_cmp_one_inc_min_102), .O(pi_f_inc_i_10_n_0)); LUT6 #( .INIT(64'hFAEAEAEAEAEAEAEA)) pi_f_inc_i_2 (.I0(pi_f_inc_i_6_n_0), .I1(pi_f_inc_i_7_n_0), .I2(\tempmon_state[10]_i_7_n_0 ), .I3(tempmon_state[10]), .I4(temp_cmp_four_dec_min_102), .I5(update_temp_102), .O(pi_f_inc_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT5 #( .INIT(32'h40000000)) pi_f_inc_i_3 (.I0(temp_cmp_two_dec_max_102), .I1(tempmon_state[8]), .I2(temp_cmp_two_dec_min_102), .I3(update_temp_102), .I4(\tempmon_state[10]_i_7_n_0 ), .O(pi_f_inc_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT2 #( .INIT(4'h8)) pi_f_inc_i_4 (.I0(update_temp_102), .I1(temp_cmp_three_dec_max_102), .O(temp_gte_three_dec_max)); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT2 #( .INIT(4'h8)) pi_f_inc_i_5 (.I0(\tempmon_state[10]_i_7_n_0 ), .I1(update_temp_102), .O(pi_f_inc_i_5_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00008000)) pi_f_inc_i_6 (.I0(\tempmon_state[10]_i_7_n_0 ), .I1(update_temp_102), .I2(temp_cmp_one_dec_min_102), .I3(tempmon_state[7]), .I4(temp_cmp_one_dec_max_102), .I5(pi_f_inc_i_8_n_0), .O(pi_f_inc_i_6_n_0)); LUT6 #( .INIT(64'hFFFFFFFFAAEAAAAA)) pi_f_inc_i_7 (.I0(pi_f_inc_i_9_n_0), .I1(tempmon_state[4]), .I2(update_temp_102), .I3(temp_cmp_two_inc_max_102), .I4(temp_cmp_two_inc_min_102), .I5(pi_f_inc_i_10_n_0), .O(pi_f_inc_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT5 #( .INIT(32'h40000000)) pi_f_inc_i_8 (.I0(temp_cmp_neutral_max_102), .I1(tempmon_state[6]), .I2(temp_cmp_neutral_min_102), .I3(update_temp_102), .I4(\tempmon_state[10]_i_7_n_0 ), .O(pi_f_inc_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT4 #( .INIT(16'h0800)) pi_f_inc_i_9 (.I0(tempmon_state[3]), .I1(update_temp_102), .I2(temp_cmp_three_inc_max_102), .I3(temp_cmp_three_inc_min_102), .O(pi_f_inc_i_9_n_0)); FDRE pi_f_inc_reg (.C(CLK), .CE(1'b1), .D(pi_f_inc_nxt), .Q(tempmon_pi_f_inc), .R(rstdiv0_sync_r1_reg_rep__2)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_10 (.I0(four_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(four_dec_min_limit[1]), .O(temp_cmp_four_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_11 (.I0(four_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(four_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_four_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_12 (.I0(four_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(four_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_four_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_13 (.I0(four_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(four_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_four_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_14 (.I0(four_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(four_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_four_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_3 (.I0(four_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(four_dec_min_limit[11]), .O(temp_cmp_four_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_4 (.I0(four_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(four_dec_min_limit[9]), .O(temp_cmp_four_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_5 (.I0(four_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(four_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_four_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_dec_min_102_i_6 (.I0(four_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(four_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_four_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_7 (.I0(four_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(four_dec_min_limit[7]), .O(temp_cmp_four_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_8 (.I0(four_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(four_dec_min_limit[5]), .O(temp_cmp_four_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_dec_min_102_i_9 (.I0(four_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(four_dec_min_limit[3]), .O(temp_cmp_four_dec_min_102_i_9_n_0)); FDRE temp_cmp_four_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_four_dec_min_101), .Q(temp_cmp_four_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_four_dec_min_102_reg_i_1 (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_four_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(four_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_four_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(four_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(four_inc_max_limit[7]), .O(temp_cmp_four_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(four_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(four_inc_max_limit[5]), .O(temp_cmp_four_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(four_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(four_inc_max_limit[3]), .O(temp_cmp_four_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(four_inc_max_limit[1]), .O(temp_cmp_four_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(four_inc_max_limit[10]), .I2(four_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_four_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(four_inc_max_limit[8]), .I2(four_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_four_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(four_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(four_inc_max_limit[11]), .O(temp_cmp_four_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_four_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(four_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(four_inc_max_limit[9]), .O(temp_cmp_four_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(four_inc_max_limit[6]), .I2(four_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_four_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(four_inc_max_limit[4]), .I2(four_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_four_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_four_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(four_inc_max_limit[2]), .I2(four_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_four_inc_max_102_i_9_n_0)); FDRE temp_cmp_four_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_four_inc_max_101), .Q(temp_cmp_four_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_four_inc_max_102_reg_i_1 (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_four_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(neutral_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_neutral_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_11 (.I0(device_temp_101[6]), .I1(neutral_max_limit[6]), .I2(device_temp_101[7]), .I3(neutral_max_limit[7]), .O(temp_cmp_neutral_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_12 (.I0(device_temp_101[4]), .I1(neutral_max_limit[4]), .I2(device_temp_101[5]), .I3(neutral_max_limit[5]), .O(temp_cmp_neutral_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_13 (.I0(device_temp_101[2]), .I1(neutral_max_limit[2]), .I2(device_temp_101[3]), .I3(neutral_max_limit[3]), .O(temp_cmp_neutral_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(neutral_max_limit[1]), .O(temp_cmp_neutral_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_3 (.I0(device_temp_101[10]), .I1(neutral_max_limit[10]), .I2(neutral_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_neutral_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_4 (.I0(device_temp_101[8]), .I1(neutral_max_limit[8]), .I2(neutral_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_neutral_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_5 (.I0(device_temp_101[10]), .I1(neutral_max_limit[10]), .I2(device_temp_101[11]), .I3(neutral_max_limit[11]), .O(temp_cmp_neutral_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_max_102_i_6 (.I0(device_temp_101[8]), .I1(neutral_max_limit[8]), .I2(device_temp_101[9]), .I3(neutral_max_limit[9]), .O(temp_cmp_neutral_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_7 (.I0(device_temp_101[6]), .I1(neutral_max_limit[6]), .I2(neutral_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_neutral_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_8 (.I0(device_temp_101[4]), .I1(neutral_max_limit[4]), .I2(neutral_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_neutral_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_max_102_i_9 (.I0(device_temp_101[2]), .I1(neutral_max_limit[2]), .I2(neutral_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_neutral_max_102_i_9_n_0)); FDRE temp_cmp_neutral_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_neutral_max_101), .Q(temp_cmp_neutral_max_102), .R(1'b0)); CARRY4 temp_cmp_neutral_max_102_reg_i_1 (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}), .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0})); CARRY4 temp_cmp_neutral_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}), .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(neutral_min_limit[1]), .O(temp_cmp_neutral_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_11 (.I0(neutral_min_limit[6]), .I1(device_temp_101[6]), .I2(neutral_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_neutral_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_12 (.I0(neutral_min_limit[4]), .I1(device_temp_101[4]), .I2(neutral_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_neutral_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_13 (.I0(neutral_min_limit[2]), .I1(device_temp_101[2]), .I2(neutral_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_neutral_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(neutral_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_neutral_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_3 (.I0(neutral_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(neutral_min_limit[11]), .O(temp_cmp_neutral_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_4 (.I0(neutral_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(neutral_min_limit[9]), .O(temp_cmp_neutral_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_5 (.I0(neutral_min_limit[10]), .I1(device_temp_101[10]), .I2(neutral_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_neutral_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_neutral_min_102_i_6 (.I0(neutral_min_limit[8]), .I1(device_temp_101[8]), .I2(neutral_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_neutral_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_7 (.I0(neutral_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(neutral_min_limit[7]), .O(temp_cmp_neutral_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_8 (.I0(neutral_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(neutral_min_limit[5]), .O(temp_cmp_neutral_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_neutral_min_102_i_9 (.I0(neutral_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(neutral_min_limit[3]), .O(temp_cmp_neutral_min_102_i_9_n_0)); FDRE temp_cmp_neutral_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_neutral_min_101), .Q(temp_cmp_neutral_min_102), .R(1'b0)); CARRY4 temp_cmp_neutral_min_102_reg_i_1 (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}), .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0})); CARRY4 temp_cmp_neutral_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}), .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(one_dec_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_dec_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_11 (.I0(device_temp_101[6]), .I1(one_dec_max_limit[6]), .I2(device_temp_101[7]), .I3(one_dec_max_limit[7]), .O(temp_cmp_one_dec_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_12 (.I0(device_temp_101[4]), .I1(one_dec_max_limit[4]), .I2(device_temp_101[5]), .I3(one_dec_max_limit[5]), .O(temp_cmp_one_dec_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_13 (.I0(device_temp_101[2]), .I1(one_dec_max_limit[2]), .I2(device_temp_101[3]), .I3(one_dec_max_limit[3]), .O(temp_cmp_one_dec_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(one_dec_max_limit[1]), .O(temp_cmp_one_dec_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_3 (.I0(device_temp_101[10]), .I1(one_dec_max_limit[10]), .I2(one_dec_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_dec_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_4 (.I0(device_temp_101[8]), .I1(one_dec_max_limit[8]), .I2(one_dec_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_dec_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_5 (.I0(device_temp_101[10]), .I1(one_dec_max_limit[10]), .I2(device_temp_101[11]), .I3(one_dec_max_limit[11]), .O(temp_cmp_one_dec_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_max_102_i_6 (.I0(device_temp_101[8]), .I1(one_dec_max_limit[8]), .I2(device_temp_101[9]), .I3(one_dec_max_limit[9]), .O(temp_cmp_one_dec_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_7 (.I0(device_temp_101[6]), .I1(one_dec_max_limit[6]), .I2(one_dec_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_dec_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_8 (.I0(device_temp_101[4]), .I1(one_dec_max_limit[4]), .I2(one_dec_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_dec_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_max_102_i_9 (.I0(device_temp_101[2]), .I1(one_dec_max_limit[2]), .I2(one_dec_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_dec_max_102_i_9_n_0)); FDRE temp_cmp_one_dec_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_dec_max_101), .Q(temp_cmp_one_dec_max_102), .R(1'b0)); CARRY4 temp_cmp_one_dec_max_102_reg_i_1 (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}), .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0})); CARRY4 temp_cmp_one_dec_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}), .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(one_dec_min_limit[1]), .O(temp_cmp_one_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_11 (.I0(one_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(one_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_12 (.I0(one_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(one_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_13 (.I0(one_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(one_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(one_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_3 (.I0(one_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(one_dec_min_limit[11]), .O(temp_cmp_one_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_4 (.I0(one_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(one_dec_min_limit[9]), .O(temp_cmp_one_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_5 (.I0(one_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(one_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_dec_min_102_i_6 (.I0(one_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(one_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_7 (.I0(one_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(one_dec_min_limit[7]), .O(temp_cmp_one_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_8 (.I0(one_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(one_dec_min_limit[5]), .O(temp_cmp_one_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_dec_min_102_i_9 (.I0(one_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(one_dec_min_limit[3]), .O(temp_cmp_one_dec_min_102_i_9_n_0)); FDRE temp_cmp_one_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_dec_min_101), .Q(temp_cmp_one_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_one_dec_min_102_reg_i_1 (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_one_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(one_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(one_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(one_inc_max_limit[7]), .O(temp_cmp_one_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(one_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(one_inc_max_limit[5]), .O(temp_cmp_one_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(one_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(one_inc_max_limit[3]), .O(temp_cmp_one_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(one_inc_max_limit[1]), .O(temp_cmp_one_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(one_inc_max_limit[10]), .I2(one_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(one_inc_max_limit[8]), .I2(one_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(one_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(one_inc_max_limit[11]), .O(temp_cmp_one_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(one_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(one_inc_max_limit[9]), .O(temp_cmp_one_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(one_inc_max_limit[6]), .I2(one_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(one_inc_max_limit[4]), .I2(one_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(one_inc_max_limit[2]), .I2(one_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_inc_max_102_i_9_n_0)); FDRE temp_cmp_one_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_inc_max_101), .Q(temp_cmp_one_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_one_inc_max_102_reg_i_1 (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_one_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(one_inc_min_limit[1]), .O(temp_cmp_one_inc_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_11 (.I0(one_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(one_inc_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_one_inc_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_12 (.I0(one_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(one_inc_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_one_inc_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_13 (.I0(one_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(one_inc_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_one_inc_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(one_inc_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_one_inc_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_3 (.I0(one_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(one_inc_min_limit[11]), .O(temp_cmp_one_inc_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_4 (.I0(one_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(one_inc_min_limit[9]), .O(temp_cmp_one_inc_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_5 (.I0(one_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(one_inc_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_one_inc_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_one_inc_min_102_i_6 (.I0(one_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(one_inc_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_one_inc_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_7 (.I0(one_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(one_inc_min_limit[7]), .O(temp_cmp_one_inc_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_8 (.I0(one_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(one_inc_min_limit[5]), .O(temp_cmp_one_inc_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_one_inc_min_102_i_9 (.I0(one_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(one_inc_min_limit[3]), .O(temp_cmp_one_inc_min_102_i_9_n_0)); FDRE temp_cmp_one_inc_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_one_inc_min_101), .Q(temp_cmp_one_inc_min_102), .R(1'b0)); CARRY4 temp_cmp_one_inc_min_102_reg_i_1 (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}), .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0})); CARRY4 temp_cmp_one_inc_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}), .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_10 (.I0(device_temp_101[0]), .I1(three_dec_max_limit[0]), .I2(three_dec_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_dec_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_11 (.I0(device_temp_101[6]), .I1(three_dec_max_limit[6]), .I2(device_temp_101[7]), .I3(three_dec_max_limit[7]), .O(temp_cmp_three_dec_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_12 (.I0(device_temp_101[4]), .I1(three_dec_max_limit[4]), .I2(device_temp_101[5]), .I3(three_dec_max_limit[5]), .O(temp_cmp_three_dec_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_13 (.I0(device_temp_101[2]), .I1(three_dec_max_limit[2]), .I2(device_temp_101[3]), .I3(three_dec_max_limit[3]), .O(temp_cmp_three_dec_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_14 (.I0(device_temp_101[0]), .I1(three_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(three_dec_max_limit[1]), .O(temp_cmp_three_dec_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_3 (.I0(device_temp_101[10]), .I1(three_dec_max_limit[10]), .I2(three_dec_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_dec_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_4 (.I0(device_temp_101[8]), .I1(three_dec_max_limit[8]), .I2(three_dec_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_dec_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_5 (.I0(device_temp_101[10]), .I1(three_dec_max_limit[10]), .I2(device_temp_101[11]), .I3(three_dec_max_limit[11]), .O(temp_cmp_three_dec_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_max_102_i_6 (.I0(device_temp_101[8]), .I1(three_dec_max_limit[8]), .I2(device_temp_101[9]), .I3(three_dec_max_limit[9]), .O(temp_cmp_three_dec_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_7 (.I0(device_temp_101[6]), .I1(three_dec_max_limit[6]), .I2(three_dec_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_dec_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_8 (.I0(device_temp_101[4]), .I1(three_dec_max_limit[4]), .I2(three_dec_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_dec_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_max_102_i_9 (.I0(device_temp_101[2]), .I1(three_dec_max_limit[2]), .I2(three_dec_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_dec_max_102_i_9_n_0)); FDRE temp_cmp_three_dec_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_dec_max_101), .Q(temp_cmp_three_dec_max_102), .R(1'b0)); CARRY4 temp_cmp_three_dec_max_102_reg_i_1 (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}), .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0})); CARRY4 temp_cmp_three_dec_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}), .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(three_dec_min_limit[1]), .O(temp_cmp_three_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_11 (.I0(three_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(three_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_12 (.I0(three_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(three_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_13 (.I0(three_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(three_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(three_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_3 (.I0(three_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(three_dec_min_limit[11]), .O(temp_cmp_three_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_4 (.I0(three_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(three_dec_min_limit[9]), .O(temp_cmp_three_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_5 (.I0(three_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(three_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_dec_min_102_i_6 (.I0(three_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(three_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_7 (.I0(three_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(three_dec_min_limit[7]), .O(temp_cmp_three_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_8 (.I0(three_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(three_dec_min_limit[5]), .O(temp_cmp_three_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_dec_min_102_i_9 (.I0(three_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(three_dec_min_limit[3]), .O(temp_cmp_three_dec_min_102_i_9_n_0)); FDRE temp_cmp_three_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_dec_min_101), .Q(temp_cmp_three_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_three_dec_min_102_reg_i_1 (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_three_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(three_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(three_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(three_inc_max_limit[7]), .O(temp_cmp_three_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(three_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(three_inc_max_limit[5]), .O(temp_cmp_three_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(three_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(three_inc_max_limit[3]), .O(temp_cmp_three_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(three_inc_max_limit[1]), .O(temp_cmp_three_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(three_inc_max_limit[10]), .I2(three_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(three_inc_max_limit[8]), .I2(three_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(three_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(three_inc_max_limit[11]), .O(temp_cmp_three_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(three_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(three_inc_max_limit[9]), .O(temp_cmp_three_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(three_inc_max_limit[6]), .I2(three_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(three_inc_max_limit[4]), .I2(three_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(three_inc_max_limit[2]), .I2(three_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_inc_max_102_i_9_n_0)); FDRE temp_cmp_three_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_inc_max_101), .Q(temp_cmp_three_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_three_inc_max_102_reg_i_1 (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_three_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(three_inc_min_limit[1]), .O(temp_cmp_three_inc_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_11 (.I0(three_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(three_inc_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_three_inc_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_12 (.I0(three_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(three_inc_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_three_inc_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_13 (.I0(three_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(three_inc_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_three_inc_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(three_inc_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_three_inc_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_3 (.I0(three_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(three_inc_min_limit[11]), .O(temp_cmp_three_inc_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_4 (.I0(three_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(three_inc_min_limit[9]), .O(temp_cmp_three_inc_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_5 (.I0(three_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(three_inc_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_three_inc_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_three_inc_min_102_i_6 (.I0(three_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(three_inc_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_three_inc_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_7 (.I0(three_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(three_inc_min_limit[7]), .O(temp_cmp_three_inc_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_8 (.I0(three_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(three_inc_min_limit[5]), .O(temp_cmp_three_inc_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_three_inc_min_102_i_9 (.I0(three_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(three_inc_min_limit[3]), .O(temp_cmp_three_inc_min_102_i_9_n_0)); FDRE temp_cmp_three_inc_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_three_inc_min_101), .Q(temp_cmp_three_inc_min_102), .R(1'b0)); CARRY4 temp_cmp_three_inc_min_102_reg_i_1 (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}), .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0})); CARRY4 temp_cmp_three_inc_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}), .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(two_dec_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_dec_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_11 (.I0(device_temp_101[6]), .I1(two_dec_max_limit[6]), .I2(device_temp_101[7]), .I3(two_dec_max_limit[7]), .O(temp_cmp_two_dec_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_12 (.I0(device_temp_101[4]), .I1(two_dec_max_limit[4]), .I2(device_temp_101[5]), .I3(two_dec_max_limit[5]), .O(temp_cmp_two_dec_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_13 (.I0(device_temp_101[2]), .I1(two_dec_max_limit[2]), .I2(device_temp_101[3]), .I3(two_dec_max_limit[3]), .O(temp_cmp_two_dec_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(two_dec_max_limit[1]), .O(temp_cmp_two_dec_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_3 (.I0(device_temp_101[10]), .I1(two_dec_max_limit[10]), .I2(two_dec_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_dec_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_4 (.I0(device_temp_101[8]), .I1(two_dec_max_limit[8]), .I2(two_dec_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_dec_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_5 (.I0(device_temp_101[10]), .I1(two_dec_max_limit[10]), .I2(device_temp_101[11]), .I3(two_dec_max_limit[11]), .O(temp_cmp_two_dec_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_max_102_i_6 (.I0(device_temp_101[8]), .I1(two_dec_max_limit[8]), .I2(device_temp_101[9]), .I3(two_dec_max_limit[9]), .O(temp_cmp_two_dec_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_7 (.I0(device_temp_101[6]), .I1(two_dec_max_limit[6]), .I2(two_dec_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_dec_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_8 (.I0(device_temp_101[4]), .I1(two_dec_max_limit[4]), .I2(two_dec_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_dec_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_max_102_i_9 (.I0(device_temp_101[2]), .I1(two_dec_max_limit[2]), .I2(two_dec_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_dec_max_102_i_9_n_0)); FDRE temp_cmp_two_dec_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_dec_max_101), .Q(temp_cmp_two_dec_max_102), .R(1'b0)); CARRY4 temp_cmp_two_dec_max_102_reg_i_1 (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}), .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0})); CARRY4 temp_cmp_two_dec_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}), .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(two_dec_min_limit[1]), .O(temp_cmp_two_dec_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_11 (.I0(two_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(two_dec_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_dec_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_12 (.I0(two_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(two_dec_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_dec_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_13 (.I0(two_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(two_dec_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_dec_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(two_dec_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_dec_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_3 (.I0(two_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(two_dec_min_limit[11]), .O(temp_cmp_two_dec_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_4 (.I0(two_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(two_dec_min_limit[9]), .O(temp_cmp_two_dec_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_5 (.I0(two_dec_min_limit[10]), .I1(device_temp_101[10]), .I2(two_dec_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_dec_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_dec_min_102_i_6 (.I0(two_dec_min_limit[8]), .I1(device_temp_101[8]), .I2(two_dec_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_dec_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_7 (.I0(two_dec_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(two_dec_min_limit[7]), .O(temp_cmp_two_dec_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_8 (.I0(two_dec_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(two_dec_min_limit[5]), .O(temp_cmp_two_dec_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_dec_min_102_i_9 (.I0(two_dec_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(two_dec_min_limit[3]), .O(temp_cmp_two_dec_min_102_i_9_n_0)); FDRE temp_cmp_two_dec_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_dec_min_101), .Q(temp_cmp_two_dec_min_102), .R(1'b0)); CARRY4 temp_cmp_two_dec_min_102_reg_i_1 (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}), .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0})); CARRY4 temp_cmp_two_dec_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}), .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_10 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(two_inc_max_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_inc_max_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_11 (.I0(device_temp_101[6]), .I1(two_inc_max_limit[6]), .I2(device_temp_101[7]), .I3(two_inc_max_limit[7]), .O(temp_cmp_two_inc_max_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_12 (.I0(device_temp_101[4]), .I1(two_inc_max_limit[4]), .I2(device_temp_101[5]), .I3(two_inc_max_limit[5]), .O(temp_cmp_two_inc_max_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_13 (.I0(device_temp_101[2]), .I1(two_inc_max_limit[2]), .I2(device_temp_101[3]), .I3(two_inc_max_limit[3]), .O(temp_cmp_two_inc_max_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_14 (.I0(device_temp_101[0]), .I1(two_dec_max_limit[0]), .I2(device_temp_101[1]), .I3(two_inc_max_limit[1]), .O(temp_cmp_two_inc_max_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_3 (.I0(device_temp_101[10]), .I1(two_inc_max_limit[10]), .I2(two_inc_max_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_inc_max_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_4 (.I0(device_temp_101[8]), .I1(two_inc_max_limit[8]), .I2(two_inc_max_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_inc_max_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_5 (.I0(device_temp_101[10]), .I1(two_inc_max_limit[10]), .I2(device_temp_101[11]), .I3(two_inc_max_limit[11]), .O(temp_cmp_two_inc_max_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_max_102_i_6 (.I0(device_temp_101[8]), .I1(two_inc_max_limit[8]), .I2(device_temp_101[9]), .I3(two_inc_max_limit[9]), .O(temp_cmp_two_inc_max_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_7 (.I0(device_temp_101[6]), .I1(two_inc_max_limit[6]), .I2(two_inc_max_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_inc_max_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_8 (.I0(device_temp_101[4]), .I1(two_inc_max_limit[4]), .I2(two_inc_max_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_inc_max_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_max_102_i_9 (.I0(device_temp_101[2]), .I1(two_inc_max_limit[2]), .I2(two_inc_max_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_inc_max_102_i_9_n_0)); FDRE temp_cmp_two_inc_max_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_inc_max_101), .Q(temp_cmp_two_inc_max_102), .R(1'b0)); CARRY4 temp_cmp_two_inc_max_102_reg_i_1 (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}), .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0})); CARRY4 temp_cmp_two_inc_max_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}), .CYINIT(1'b1), .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}), .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0})); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_10 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(device_temp_101[1]), .I3(two_inc_min_limit[1]), .O(temp_cmp_two_inc_min_102_i_10_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_11 (.I0(two_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(two_inc_min_limit[7]), .I3(device_temp_101[7]), .O(temp_cmp_two_inc_min_102_i_11_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_12 (.I0(two_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(two_inc_min_limit[5]), .I3(device_temp_101[5]), .O(temp_cmp_two_inc_min_102_i_12_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_13 (.I0(two_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(two_inc_min_limit[3]), .I3(device_temp_101[3]), .O(temp_cmp_two_inc_min_102_i_13_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_14 (.I0(three_dec_min_limit[0]), .I1(device_temp_101[0]), .I2(two_inc_min_limit[1]), .I3(device_temp_101[1]), .O(temp_cmp_two_inc_min_102_i_14_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_3 (.I0(two_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(device_temp_101[11]), .I3(two_inc_min_limit[11]), .O(temp_cmp_two_inc_min_102_i_3_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_4 (.I0(two_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(device_temp_101[9]), .I3(two_inc_min_limit[9]), .O(temp_cmp_two_inc_min_102_i_4_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_5 (.I0(two_inc_min_limit[10]), .I1(device_temp_101[10]), .I2(two_inc_min_limit[11]), .I3(device_temp_101[11]), .O(temp_cmp_two_inc_min_102_i_5_n_0)); LUT4 #( .INIT(16'h9009)) temp_cmp_two_inc_min_102_i_6 (.I0(two_inc_min_limit[8]), .I1(device_temp_101[8]), .I2(two_inc_min_limit[9]), .I3(device_temp_101[9]), .O(temp_cmp_two_inc_min_102_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_7 (.I0(two_inc_min_limit[6]), .I1(device_temp_101[6]), .I2(device_temp_101[7]), .I3(two_inc_min_limit[7]), .O(temp_cmp_two_inc_min_102_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_8 (.I0(two_inc_min_limit[4]), .I1(device_temp_101[4]), .I2(device_temp_101[5]), .I3(two_inc_min_limit[5]), .O(temp_cmp_two_inc_min_102_i_8_n_0)); LUT4 #( .INIT(16'h2F02)) temp_cmp_two_inc_min_102_i_9 (.I0(two_inc_min_limit[2]), .I1(device_temp_101[2]), .I2(device_temp_101[3]), .I3(two_inc_min_limit[3]), .O(temp_cmp_two_inc_min_102_i_9_n_0)); FDRE temp_cmp_two_inc_min_102_reg (.C(CLK), .CE(1'b1), .D(temp_cmp_two_inc_min_101), .Q(temp_cmp_two_inc_min_102), .R(1'b0)); CARRY4 temp_cmp_two_inc_min_102_reg_i_1 (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0), .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}), .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0})); CARRY4 temp_cmp_two_inc_min_102_reg_i_2 (.CI(1'b0), .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}), .CYINIT(1'b0), .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}), .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]), .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0})); FDRE tempmon_init_complete_reg (.C(CLK), .CE(tempmon_state_init), .D(tempmon_state_init), .Q(tempmon_init_complete), .R(SS)); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT2 #( .INIT(4'hE)) tempmon_pi_f_en_r_i_1 (.I0(tempmon_pi_f_inc), .I1(tempmon_pi_f_dec), .O(tempmon_sel_pi_incdec)); FDRE tempmon_sample_en_101_reg (.C(CLK), .CE(1'b1), .D(tempmon_sample_en), .Q(tempmon_sample_en_101), .R(SS)); FDRE tempmon_sample_en_102_reg (.C(CLK), .CE(1'b1), .D(tempmon_sample_en_101), .Q(tempmon_sample_en_102), .R(SS)); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT1 #( .INIT(2'h1)) \tempmon_state[0]_i_2 (.I0(\tempmon_state[10]_i_7_n_0 ), .O(\tempmon_state[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFEAFFFFFFFF)) \tempmon_state[10]_i_1 (.I0(\tempmon_state[10]_i_3_n_0 ), .I1(\tempmon_state[10]_i_4_n_0 ), .I2(update_temp_102), .I3(\tempmon_state[10]_i_5_n_0 ), .I4(\tempmon_state[10]_i_6_n_0 ), .I5(\tempmon_state[10]_i_7_n_0 ), .O(tempmon_state_nxt)); LUT3 #( .INIT(8'h80)) \tempmon_state[10]_i_10 (.I0(update_temp_102), .I1(temp_cmp_four_dec_min_102), .I2(tempmon_state[10]), .O(\tempmon_state[10]_i_10_n_0 )); LUT5 #( .INIT(32'hF0808080)) \tempmon_state[10]_i_11 (.I0(tempmon_state[5]), .I1(temp_cmp_one_inc_min_102), .I2(update_temp_102), .I3(tempmon_state[4]), .I4(temp_cmp_two_inc_min_102), .O(\tempmon_state[10]_i_11_n_0 )); LUT6 #( .INIT(64'hFFEAEAEAEAEAEAEA)) \tempmon_state[10]_i_12 (.I0(tempmon_state[1]), .I1(calib_complete), .I2(tempmon_state[0]), .I3(update_temp_102), .I4(tempmon_state[9]), .I5(temp_cmp_three_dec_min_102), .O(\tempmon_state[10]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT5 #( .INIT(32'h00010116)) \tempmon_state[10]_i_13 (.I0(tempmon_state[0]), .I1(tempmon_state[1]), .I2(tempmon_state[2]), .I3(tempmon_state[3]), .I4(tempmon_state[4]), .O(\tempmon_state[10]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT5 #( .INIT(32'hFFFEFEE8)) \tempmon_state[10]_i_14 (.I0(tempmon_state[0]), .I1(tempmon_state[1]), .I2(tempmon_state[2]), .I3(tempmon_state[3]), .I4(tempmon_state[4]), .O(\tempmon_state[10]_i_14_n_0 )); LUT6 #( .INIT(64'h0000000100010116)) \tempmon_state[10]_i_15 (.I0(tempmon_state[5]), .I1(tempmon_state[6]), .I2(tempmon_state[7]), .I3(tempmon_state[8]), .I4(tempmon_state[9]), .I5(tempmon_state[10]), .O(\tempmon_state[10]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFEFEE8)) \tempmon_state[10]_i_16 (.I0(tempmon_state[5]), .I1(tempmon_state[6]), .I2(tempmon_state[7]), .I3(tempmon_state[8]), .I4(tempmon_state[9]), .I5(tempmon_state[10]), .O(\tempmon_state[10]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT4 #( .INIT(16'h8000)) \tempmon_state[10]_i_2 (.I0(tempmon_state[9]), .I1(\tempmon_state[10]_i_7_n_0 ), .I2(temp_cmp_three_dec_max_102), .I3(update_temp_102), .O(\tempmon_state[10]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFF80)) \tempmon_state[10]_i_3 (.I0(temp_cmp_four_inc_max_102), .I1(update_temp_102), .I2(tempmon_state[2]), .I3(\tempmon_state[10]_i_8_n_0 ), .I4(\tempmon_state[10]_i_9_n_0 ), .O(\tempmon_state[10]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT2 #( .INIT(4'h8)) \tempmon_state[10]_i_4 (.I0(tempmon_state[6]), .I1(temp_cmp_neutral_min_102), .O(\tempmon_state[10]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFAAEAAA)) \tempmon_state[10]_i_5 (.I0(\tempmon_state[10]_i_10_n_0 ), .I1(tempmon_state[3]), .I2(temp_cmp_three_inc_min_102), .I3(update_temp_102), .I4(pi_f_dec_i_2_n_0), .I5(\tempmon_state[10]_i_11_n_0 ), .O(\tempmon_state[10]_i_5_n_0 )); LUT6 #( .INIT(64'hFFAAEAAAEAAAEAAA)) \tempmon_state[10]_i_6 (.I0(\tempmon_state[10]_i_12_n_0 ), .I1(temp_cmp_one_dec_min_102), .I2(tempmon_state[7]), .I3(update_temp_102), .I4(temp_cmp_two_dec_min_102), .I5(tempmon_state[8]), .O(\tempmon_state[10]_i_6_n_0 )); LUT4 #( .INIT(16'h0012)) \tempmon_state[10]_i_7 (.I0(\tempmon_state[10]_i_13_n_0 ), .I1(\tempmon_state[10]_i_14_n_0 ), .I2(\tempmon_state[10]_i_15_n_0 ), .I3(\tempmon_state[10]_i_16_n_0 ), .O(\tempmon_state[10]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT5 #( .INIT(32'hF0808080)) \tempmon_state[10]_i_8 (.I0(temp_cmp_two_dec_max_102), .I1(tempmon_state[8]), .I2(update_temp_102), .I3(temp_cmp_three_dec_max_102), .I4(tempmon_state[9]), .O(\tempmon_state[10]_i_8_n_0 )); LUT5 #( .INIT(32'hF0808080)) \tempmon_state[10]_i_9 (.I0(temp_cmp_neutral_max_102), .I1(tempmon_state[6]), .I2(update_temp_102), .I3(temp_cmp_one_dec_max_102), .I4(tempmon_state[7]), .O(\tempmon_state[10]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT2 #( .INIT(4'h8)) \tempmon_state[1]_i_1 (.I0(\tempmon_state[10]_i_7_n_0 ), .I1(tempmon_state[0]), .O(\tempmon_state[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT4 #( .INIT(16'h0888)) \tempmon_state[2]_i_1 (.I0(tempmon_state[3]), .I1(\tempmon_state[10]_i_7_n_0 ), .I2(update_temp_102), .I3(temp_cmp_three_inc_max_102), .O(\tempmon_state[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT5 #( .INIT(32'hFF007000)) \tempmon_state[3]_i_1 (.I0(temp_cmp_two_inc_max_102), .I1(update_temp_102), .I2(tempmon_state[4]), .I3(\tempmon_state[10]_i_7_n_0 ), .I4(tempmon_state[2]), .O(\tempmon_state[3]_i_1_n_0 )); LUT6 #( .INIT(64'h8FFF000088000000)) \tempmon_state[4]_i_1 (.I0(tempmon_state[3]), .I1(temp_cmp_three_inc_max_102), .I2(temp_cmp_one_inc_max_102), .I3(update_temp_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[5]), .O(\tempmon_state[4]_i_1_n_0 )); LUT6 #( .INIT(64'h8FFF000080800000)) \tempmon_state[5]_i_1 (.I0(tempmon_state[4]), .I1(temp_cmp_two_inc_max_102), .I2(update_temp_102), .I3(temp_cmp_neutral_max_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[6]), .O(\tempmon_state[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFF00EE00AE00EE00)) \tempmon_state[6]_i_1 (.I0(tempmon_state[1]), .I1(tempmon_state[7]), .I2(temp_cmp_one_dec_max_102), .I3(\tempmon_state[10]_i_7_n_0 ), .I4(update_temp_102), .I5(\tempmon_state[6]_i_2_n_0 ), .O(\tempmon_state[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT2 #( .INIT(4'h8)) \tempmon_state[6]_i_2 (.I0(tempmon_state[5]), .I1(temp_cmp_one_inc_max_102), .O(\tempmon_state[6]_i_2_n_0 )); LUT6 #( .INIT(64'hFC4C00004C4C0000)) \tempmon_state[7]_i_1 (.I0(temp_cmp_two_dec_max_102), .I1(tempmon_state[8]), .I2(update_temp_102), .I3(temp_cmp_neutral_max_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[6]), .O(\tempmon_state[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFC4C00004C4C0000)) \tempmon_state[8]_i_1 (.I0(temp_cmp_three_dec_max_102), .I1(tempmon_state[9]), .I2(update_temp_102), .I3(temp_cmp_one_dec_max_102), .I4(\tempmon_state[10]_i_7_n_0 ), .I5(tempmon_state[7]), .O(\tempmon_state[8]_i_1_n_0 )); LUT5 #( .INIT(32'hFF800000)) \tempmon_state[9]_i_1 (.I0(update_temp_102), .I1(temp_cmp_two_dec_max_102), .I2(tempmon_state[8]), .I3(tempmon_state[10]), .I4(\tempmon_state[10]_i_7_n_0 ), .O(\tempmon_state[9]_i_1_n_0 )); FDSE \tempmon_state_reg[0] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[0]_i_2_n_0 ), .Q(tempmon_state[0]), .S(SS)); FDRE \tempmon_state_reg[10] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[10]_i_2_n_0 ), .Q(tempmon_state[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[1] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[1]_i_1_n_0 ), .Q(tempmon_state[1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[2] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[2]_i_1_n_0 ), .Q(tempmon_state[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[3] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[3]_i_1_n_0 ), .Q(tempmon_state[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[4] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[4]_i_1_n_0 ), .Q(tempmon_state[4]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[5] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[5]_i_1_n_0 ), .Q(tempmon_state[5]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[6] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[6]_i_1_n_0 ), .Q(tempmon_state[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[7] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[7]_i_1_n_0 ), .Q(tempmon_state[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[8] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[8]_i_1_n_0 ), .Q(tempmon_state[8]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \tempmon_state_reg[9] (.C(CLK), .CE(tempmon_state_nxt), .D(\tempmon_state[9]_i_1_n_0 ), .Q(tempmon_state[9]), .R(rstdiv0_sync_r1_reg_rep__5)); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT2 #( .INIT(4'hB)) \three_dec_max_limit[0]_i_1 (.I0(p_0_in), .I1(device_temp_init[0]), .O(\three_dec_max_limit[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[10]_i_1 (.I0(\three_dec_max_limit_reg[11]_i_2_n_6 ), .I1(p_0_in), .O(\three_dec_max_limit[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[11]_i_1 (.I0(\three_dec_max_limit_reg[11]_i_2_n_5 ), .I1(p_0_in), .O(\three_dec_max_limit[11]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[11]_i_3 (.I0(device_temp_init[11]), .O(\three_dec_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[11]_i_4 (.I0(device_temp_init[10]), .O(\three_dec_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_max_limit[11]_i_5 (.I0(device_temp_init[9]), .O(\three_dec_max_limit[11]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[1]_i_1 (.I0(\three_dec_max_limit_reg[1]_i_2_n_0 ), .I1(p_0_in), .O(\three_dec_max_limit[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[2]_i_1 (.I0(\three_dec_max_limit_reg[4]_i_2_n_6 ), .I1(p_0_in), .O(\three_dec_max_limit[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[3]_i_1 (.I0(\three_dec_max_limit_reg[4]_i_2_n_5 ), .I1(p_0_in), .O(\three_dec_max_limit[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[4]_i_1 (.I0(\three_dec_max_limit_reg[4]_i_2_n_4 ), .I1(p_0_in), .O(\three_dec_max_limit[4]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_3 (.I0(device_temp_init[4]), .O(\three_dec_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_4 (.I0(device_temp_init[3]), .O(\three_dec_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_5 (.I0(device_temp_init[2]), .O(\three_dec_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[4]_i_6 (.I0(device_temp_init[1]), .O(\three_dec_max_limit[4]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[5]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_7 ), .I1(p_0_in), .O(\three_dec_max_limit[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[6]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_6 ), .I1(p_0_in), .O(\three_dec_max_limit[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[7]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_5 ), .I1(p_0_in), .O(\three_dec_max_limit[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[8]_i_1 (.I0(\three_dec_max_limit_reg[8]_i_2_n_4 ), .I1(p_0_in), .O(\three_dec_max_limit[8]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_max_limit[8]_i_3 (.I0(device_temp_init[8]), .O(\three_dec_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[8]_i_4 (.I0(device_temp_init[7]), .O(\three_dec_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_max_limit[8]_i_5 (.I0(device_temp_init[6]), .O(\three_dec_max_limit[8]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_max_limit[8]_i_6 (.I0(device_temp_init[5]), .O(\three_dec_max_limit[8]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'hE)) \three_dec_max_limit[9]_i_1 (.I0(\three_dec_max_limit_reg[11]_i_2_n_7 ), .I1(p_0_in), .O(\three_dec_max_limit[9]_i_1_n_0 )); FDRE \three_dec_max_limit_reg[0] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[0]_i_1_n_0 ), .Q(three_dec_max_limit[0]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[10]_i_1_n_0 ), .Q(three_dec_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[11]_i_1_n_0 ), .Q(three_dec_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \three_dec_max_limit_reg[11]_i_2 (.CI(\three_dec_max_limit_reg[8]_i_2_n_0 ), .CO({p_0_in,\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED [2],\three_dec_max_limit_reg[11]_i_2_n_2 ,\three_dec_max_limit_reg[11]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,device_temp_init[9]}), .O({\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED [3],\three_dec_max_limit_reg[11]_i_2_n_5 ,\three_dec_max_limit_reg[11]_i_2_n_6 ,\three_dec_max_limit_reg[11]_i_2_n_7 }), .S({1'b1,\three_dec_max_limit[11]_i_3_n_0 ,\three_dec_max_limit[11]_i_4_n_0 ,\three_dec_max_limit[11]_i_5_n_0 })); FDRE \three_dec_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[1]_i_1_n_0 ), .Q(three_dec_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__7)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \three_dec_max_limit_reg[1]_i_2_CARRY4 (.CI(1'b0), .CO(\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED [3:1],\three_dec_max_limit_reg[1]_i_2_n_0 }), .S({\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]})); FDRE \three_dec_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[2]_i_1_n_0 ), .Q(three_dec_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[3]_i_1_n_0 ), .Q(three_dec_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[4]_i_1_n_0 ), .Q(three_dec_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \three_dec_max_limit_reg[4]_i_2 (.CI(1'b0), .CO({\three_dec_max_limit_reg[4]_i_2_n_0 ,\three_dec_max_limit_reg[4]_i_2_n_1 ,\three_dec_max_limit_reg[4]_i_2_n_2 ,\three_dec_max_limit_reg[4]_i_2_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\three_dec_max_limit_reg[4]_i_2_n_4 ,\three_dec_max_limit_reg[4]_i_2_n_5 ,\three_dec_max_limit_reg[4]_i_2_n_6 ,\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED [0]}), .S({\three_dec_max_limit[4]_i_3_n_0 ,\three_dec_max_limit[4]_i_4_n_0 ,\three_dec_max_limit[4]_i_5_n_0 ,\three_dec_max_limit[4]_i_6_n_0 })); FDRE \three_dec_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[5]_i_1_n_0 ), .Q(three_dec_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[6]_i_1_n_0 ), .Q(three_dec_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[7]_i_1_n_0 ), .Q(three_dec_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \three_dec_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[8]_i_1_n_0 ), .Q(three_dec_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \three_dec_max_limit_reg[8]_i_2 (.CI(\three_dec_max_limit_reg[4]_i_2_n_0 ), .CO({\three_dec_max_limit_reg[8]_i_2_n_0 ,\three_dec_max_limit_reg[8]_i_2_n_1 ,\three_dec_max_limit_reg[8]_i_2_n_2 ,\three_dec_max_limit_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8],1'b0,device_temp_init[6],1'b0}), .O({\three_dec_max_limit_reg[8]_i_2_n_4 ,\three_dec_max_limit_reg[8]_i_2_n_5 ,\three_dec_max_limit_reg[8]_i_2_n_6 ,\three_dec_max_limit_reg[8]_i_2_n_7 }), .S({\three_dec_max_limit[8]_i_3_n_0 ,\three_dec_max_limit[8]_i_4_n_0 ,\three_dec_max_limit[8]_i_5_n_0 ,\three_dec_max_limit[8]_i_6_n_0 })); FDRE \three_dec_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(\three_dec_max_limit[9]_i_1_n_0 ), .Q(three_dec_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__7)); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[11]_i_2 (.I0(two_dec_max_limit[11]), .O(\three_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[11]_i_3 (.I0(two_dec_max_limit[10]), .O(\three_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[5]_i_2 (.I0(two_dec_max_limit[5]), .O(\three_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[5]_i_3 (.I0(two_dec_max_limit[4]), .O(\three_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[5]_i_4 (.I0(two_dec_max_limit[3]), .O(\three_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_dec_min_limit[5]_i_5 (.I0(two_dec_max_limit[2]), .O(\three_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_2 (.I0(two_dec_max_limit[9]), .O(\three_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_3 (.I0(two_dec_max_limit[8]), .O(\three_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_4 (.I0(two_dec_max_limit[7]), .O(\three_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_dec_min_limit[9]_i_5 (.I0(two_dec_max_limit[6]), .O(\three_dec_min_limit[9]_i_5_n_0 )); FDRE \three_dec_min_limit_reg[0] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit[0]), .Q(three_dec_min_limit[0]), .R(SS)); FDRE \three_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[10]), .Q(three_dec_min_limit[10]), .R(SS)); FDRE \three_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[11]), .Q(three_dec_min_limit[11]), .R(SS)); CARRY4 \three_dec_min_limit_reg[11]_i_1 (.CI(\three_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}), .O({\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\three_dec_min_limit[11]_i_2_n_0 ,\three_dec_min_limit[11]_i_3_n_0 })); FDRE \three_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit[1]), .Q(three_dec_min_limit[1]), .R(SS)); FDRE \three_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[2]), .Q(three_dec_min_limit[2]), .R(SS)); FDRE \three_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[3]), .Q(three_dec_min_limit[3]), .R(SS)); FDRE \three_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[4]), .Q(three_dec_min_limit[4]), .R(SS)); FDRE \three_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[5]), .Q(three_dec_min_limit[5]), .R(SS)); CARRY4 \three_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\three_dec_min_limit_reg[5]_i_1_n_0 ,\three_dec_min_limit_reg[5]_i_1_n_1 ,\three_dec_min_limit_reg[5]_i_1_n_2 ,\three_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({two_dec_max_limit[5:3],1'b0}), .O(three_dec_min_limit_nxt[5:2]), .S({\three_dec_min_limit[5]_i_2_n_0 ,\three_dec_min_limit[5]_i_3_n_0 ,\three_dec_min_limit[5]_i_4_n_0 ,\three_dec_min_limit[5]_i_5_n_0 })); FDRE \three_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[6]), .Q(three_dec_min_limit[6]), .R(SS)); FDRE \three_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[7]), .Q(three_dec_min_limit[7]), .R(SS)); FDRE \three_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[8]), .Q(three_dec_min_limit[8]), .R(SS)); FDRE \three_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(three_dec_min_limit_nxt[9]), .Q(three_dec_min_limit[9]), .R(SS)); CARRY4 \three_dec_min_limit_reg[9]_i_1 (.CI(\three_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\three_dec_min_limit_reg[9]_i_1_n_0 ,\three_dec_min_limit_reg[9]_i_1_n_1 ,\three_dec_min_limit_reg[9]_i_1_n_2 ,\three_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(two_dec_max_limit[9:6]), .O(three_dec_min_limit_nxt[9:6]), .S({\three_dec_min_limit[9]_i_2_n_0 ,\three_dec_min_limit[9]_i_3_n_0 ,\three_dec_min_limit[9]_i_4_n_0 ,\three_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\three_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\three_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\three_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\three_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\three_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\three_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\three_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\three_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\three_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\three_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\three_inc_max_limit[8]_i_5_n_0 )); FDRE \three_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[10]), .Q(three_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[11]), .Q(three_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \three_inc_max_limit_reg[11]_i_1 (.CI(\three_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\three_inc_max_limit_reg[11]_i_1_n_2 ,\three_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10],1'b0}), .O({\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],three_inc_max_limit_nxt[11:9]}), .S({1'b0,\three_inc_max_limit[11]_i_2_n_0 ,\three_inc_max_limit[11]_i_3_n_0 ,\three_inc_max_limit[11]_i_4_n_0 })); FDRE \three_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[1]), .Q(three_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[2]), .Q(three_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[3]), .Q(three_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[4]), .Q(three_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \three_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\three_inc_max_limit_reg[4]_i_1_n_0 ,\three_inc_max_limit_reg[4]_i_1_n_1 ,\three_inc_max_limit_reg[4]_i_1_n_2 ,\three_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({1'b0,device_temp_init[3:2],1'b0}), .O(three_inc_max_limit_nxt[4:1]), .S({\three_inc_max_limit[4]_i_2_n_0 ,\three_inc_max_limit[4]_i_3_n_0 ,\three_inc_max_limit[4]_i_4_n_0 ,\three_inc_max_limit[4]_i_5_n_0 })); FDRE \three_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[5]), .Q(three_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[6]), .Q(three_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[7]), .Q(three_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE \three_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[8]), .Q(three_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__6)); CARRY4 \three_inc_max_limit_reg[8]_i_1 (.CI(\three_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\three_inc_max_limit_reg[8]_i_1_n_0 ,\three_inc_max_limit_reg[8]_i_1_n_1 ,\three_inc_max_limit_reg[8]_i_1_n_2 ,\three_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({device_temp_init[8:7],1'b0,device_temp_init[5]}), .O(three_inc_max_limit_nxt[8:5]), .S({\three_inc_max_limit[8]_i_2_n_0 ,\three_inc_max_limit[8]_i_3_n_0 ,\three_inc_max_limit[8]_i_4_n_0 ,\three_inc_max_limit[8]_i_5_n_0 })); FDRE \three_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit_nxt[9]), .Q(three_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__6)); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[11]_i_2 (.I0(four_inc_max_limit[11]), .O(\three_inc_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[11]_i_3 (.I0(four_inc_max_limit[10]), .O(\three_inc_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[5]_i_2 (.I0(four_inc_max_limit[5]), .O(\three_inc_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[5]_i_3 (.I0(four_inc_max_limit[4]), .O(\three_inc_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[5]_i_4 (.I0(four_inc_max_limit[3]), .O(\three_inc_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \three_inc_min_limit[5]_i_5 (.I0(four_inc_max_limit[2]), .O(\three_inc_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_2 (.I0(four_inc_max_limit[9]), .O(\three_inc_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_3 (.I0(four_inc_max_limit[8]), .O(\three_inc_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_4 (.I0(four_inc_max_limit[7]), .O(\three_inc_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \three_inc_min_limit[9]_i_5 (.I0(four_inc_max_limit[6]), .O(\three_inc_min_limit[9]_i_5_n_0 )); FDRE \three_inc_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[10]), .Q(three_inc_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[11]), .Q(three_inc_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_min_limit_reg[11]_i_1 (.CI(\three_inc_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_inc_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}), .O({\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\three_inc_min_limit[11]_i_2_n_0 ,\three_inc_min_limit[11]_i_3_n_0 })); FDRE \three_inc_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(four_inc_max_limit[1]), .Q(three_inc_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[2]), .Q(three_inc_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[3]), .Q(three_inc_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[4]), .Q(three_inc_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[5]), .Q(three_inc_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\three_inc_min_limit_reg[5]_i_1_n_0 ,\three_inc_min_limit_reg[5]_i_1_n_1 ,\three_inc_min_limit_reg[5]_i_1_n_2 ,\three_inc_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({four_inc_max_limit[5:3],1'b0}), .O(three_inc_min_limit_nxt[5:2]), .S({\three_inc_min_limit[5]_i_2_n_0 ,\three_inc_min_limit[5]_i_3_n_0 ,\three_inc_min_limit[5]_i_4_n_0 ,\three_inc_min_limit[5]_i_5_n_0 })); FDRE \three_inc_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[6]), .Q(three_inc_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[7]), .Q(three_inc_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[8]), .Q(three_inc_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \three_inc_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(three_inc_min_limit_nxt[9]), .Q(three_inc_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__5)); CARRY4 \three_inc_min_limit_reg[9]_i_1 (.CI(\three_inc_min_limit_reg[5]_i_1_n_0 ), .CO({\three_inc_min_limit_reg[9]_i_1_n_0 ,\three_inc_min_limit_reg[9]_i_1_n_1 ,\three_inc_min_limit_reg[9]_i_1_n_2 ,\three_inc_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(four_inc_max_limit[9:6]), .O(three_inc_min_limit_nxt[9:6]), .S({\three_inc_min_limit[9]_i_2_n_0 ,\three_inc_min_limit[9]_i_3_n_0 ,\three_inc_min_limit[9]_i_4_n_0 ,\three_inc_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[0]_i_1 (.I0(device_temp_init[0]), .O(\two_dec_max_limit[0]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\two_dec_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\two_dec_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\two_dec_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\two_dec_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\two_dec_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\two_dec_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\two_dec_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\two_dec_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\two_dec_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\two_dec_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\two_dec_max_limit[8]_i_5_n_0 )); FDRE \two_dec_max_limit_reg[0] (.C(CLK), .CE(1'b1), .D(\two_dec_max_limit[0]_i_1_n_0 ), .Q(two_dec_max_limit[0]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[10]), .Q(two_dec_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[11]), .Q(two_dec_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \two_dec_max_limit_reg[11]_i_1 (.CI(\two_dec_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_dec_max_limit_reg[11]_i_1_n_2 ,\two_dec_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,device_temp_init[9]}), .O({\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_dec_max_limit_nxt[11:9]}), .S({1'b0,\two_dec_max_limit[11]_i_2_n_0 ,\two_dec_max_limit[11]_i_3_n_0 ,\two_dec_max_limit[11]_i_4_n_0 })); FDRE \two_dec_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[1]), .Q(two_dec_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__7)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) CARRY4 \two_dec_max_limit_reg[1]_i_1_CARRY4 (.CI(1'b0), .CO(\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]), .CYINIT(device_temp_init[0]), .DI(\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]), .O({\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],two_dec_max_limit_nxt[1]}), .S({\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\four_inc_max_limit[1]_i_2_n_0 })); FDRE \two_dec_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[2]), .Q(two_dec_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[3]), .Q(two_dec_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[4]), .Q(two_dec_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \two_dec_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\two_dec_max_limit_reg[4]_i_1_n_0 ,\two_dec_max_limit_reg[4]_i_1_n_1 ,\two_dec_max_limit_reg[4]_i_1_n_2 ,\two_dec_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({device_temp_init[4],1'b0,1'b0,device_temp_init[1]}), .O({two_dec_max_limit_nxt[4:2],\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\two_dec_max_limit[4]_i_2_n_0 ,\two_dec_max_limit[4]_i_3_n_0 ,\two_dec_max_limit[4]_i_4_n_0 ,\two_dec_max_limit[4]_i_5_n_0 })); FDRE \two_dec_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[5]), .Q(two_dec_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[6]), .Q(two_dec_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[7]), .Q(two_dec_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__7)); FDRE \two_dec_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[8]), .Q(two_dec_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__7)); CARRY4 \two_dec_max_limit_reg[8]_i_1 (.CI(\two_dec_max_limit_reg[4]_i_1_n_0 ), .CO({\two_dec_max_limit_reg[8]_i_1_n_0 ,\two_dec_max_limit_reg[8]_i_1_n_1 ,\two_dec_max_limit_reg[8]_i_1_n_2 ,\two_dec_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[6],1'b0}), .O(two_dec_max_limit_nxt[8:5]), .S({\two_dec_max_limit[8]_i_2_n_0 ,\two_dec_max_limit[8]_i_3_n_0 ,\two_dec_max_limit[8]_i_4_n_0 ,\two_dec_max_limit[8]_i_5_n_0 })); FDRE \two_dec_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_dec_max_limit_nxt[9]), .Q(two_dec_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__7)); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[11]_i_2 (.I0(one_dec_max_limit[11]), .O(\two_dec_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[11]_i_3 (.I0(one_dec_max_limit[10]), .O(\two_dec_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[5]_i_2 (.I0(one_dec_max_limit[5]), .O(\two_dec_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[5]_i_3 (.I0(one_dec_max_limit[4]), .O(\two_dec_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[5]_i_4 (.I0(one_dec_max_limit[3]), .O(\two_dec_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_dec_min_limit[5]_i_5 (.I0(one_dec_max_limit[2]), .O(\two_dec_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_2 (.I0(one_dec_max_limit[9]), .O(\two_dec_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_3 (.I0(one_dec_max_limit[8]), .O(\two_dec_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_4 (.I0(one_dec_max_limit[7]), .O(\two_dec_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_dec_min_limit[9]_i_5 (.I0(one_dec_max_limit[6]), .O(\two_dec_min_limit[9]_i_5_n_0 )); FDRE \two_dec_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[10]), .Q(two_dec_min_limit[10]), .R(SS)); FDRE \two_dec_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[11]), .Q(two_dec_min_limit[11]), .R(SS)); CARRY4 \two_dec_min_limit_reg[11]_i_1 (.CI(\two_dec_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_dec_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}), .O({\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\two_dec_min_limit[11]_i_2_n_0 ,\two_dec_min_limit[11]_i_3_n_0 })); FDRE \two_dec_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(one_dec_max_limit[1]), .Q(two_dec_min_limit[1]), .R(SS)); FDRE \two_dec_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[2]), .Q(two_dec_min_limit[2]), .R(SS)); FDRE \two_dec_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[3]), .Q(two_dec_min_limit[3]), .R(SS)); FDRE \two_dec_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[4]), .Q(two_dec_min_limit[4]), .R(SS)); FDRE \two_dec_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[5]), .Q(two_dec_min_limit[5]), .R(SS)); CARRY4 \two_dec_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\two_dec_min_limit_reg[5]_i_1_n_0 ,\two_dec_min_limit_reg[5]_i_1_n_1 ,\two_dec_min_limit_reg[5]_i_1_n_2 ,\two_dec_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({one_dec_max_limit[5:3],1'b0}), .O(two_dec_min_limit_nxt[5:2]), .S({\two_dec_min_limit[5]_i_2_n_0 ,\two_dec_min_limit[5]_i_3_n_0 ,\two_dec_min_limit[5]_i_4_n_0 ,\two_dec_min_limit[5]_i_5_n_0 })); FDRE \two_dec_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[6]), .Q(two_dec_min_limit[6]), .R(SS)); FDRE \two_dec_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[7]), .Q(two_dec_min_limit[7]), .R(SS)); FDRE \two_dec_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[8]), .Q(two_dec_min_limit[8]), .R(SS)); FDRE \two_dec_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_dec_min_limit_nxt[9]), .Q(two_dec_min_limit[9]), .R(SS)); CARRY4 \two_dec_min_limit_reg[9]_i_1 (.CI(\two_dec_min_limit_reg[5]_i_1_n_0 ), .CO({\two_dec_min_limit_reg[9]_i_1_n_0 ,\two_dec_min_limit_reg[9]_i_1_n_1 ,\two_dec_min_limit_reg[9]_i_1_n_2 ,\two_dec_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(one_dec_max_limit[9:6]), .O(two_dec_min_limit_nxt[9:6]), .S({\two_dec_min_limit[9]_i_2_n_0 ,\two_dec_min_limit[9]_i_3_n_0 ,\two_dec_min_limit[9]_i_4_n_0 ,\two_dec_min_limit[9]_i_5_n_0 })); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[11]_i_2 (.I0(device_temp_init[11]), .O(\two_inc_max_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[11]_i_3 (.I0(device_temp_init[10]), .O(\two_inc_max_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[11]_i_4 (.I0(device_temp_init[9]), .O(\two_inc_max_limit[11]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[4]_i_2 (.I0(device_temp_init[4]), .O(\two_inc_max_limit[4]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[4]_i_3 (.I0(device_temp_init[3]), .O(\two_inc_max_limit[4]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[4]_i_4 (.I0(device_temp_init[2]), .O(\two_inc_max_limit[4]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[4]_i_5 (.I0(device_temp_init[1]), .O(\two_inc_max_limit[4]_i_5_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[8]_i_2 (.I0(device_temp_init[8]), .O(\two_inc_max_limit[8]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_max_limit[8]_i_3 (.I0(device_temp_init[7]), .O(\two_inc_max_limit[8]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[8]_i_4 (.I0(device_temp_init[6]), .O(\two_inc_max_limit[8]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_max_limit[8]_i_5 (.I0(device_temp_init[5]), .O(\two_inc_max_limit[8]_i_5_n_0 )); FDRE \two_inc_max_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[10]), .Q(two_inc_max_limit[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[11]), .Q(two_inc_max_limit[11]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_max_limit_reg[11]_i_1 (.CI(\two_inc_max_limit_reg[8]_i_1_n_0 ), .CO({\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_inc_max_limit_reg[11]_i_1_n_2 ,\two_inc_max_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,device_temp_init[10:9]}), .O({\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_inc_max_limit_nxt[11:9]}), .S({1'b0,\two_inc_max_limit[11]_i_2_n_0 ,\two_inc_max_limit[11]_i_3_n_0 ,\two_inc_max_limit[11]_i_4_n_0 })); FDRE \two_inc_max_limit_reg[1] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[1]), .Q(two_inc_max_limit[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[2]), .Q(two_inc_max_limit[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[3]), .Q(two_inc_max_limit[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[4]), .Q(two_inc_max_limit[4]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_max_limit_reg[4]_i_1 (.CI(1'b0), .CO({\two_inc_max_limit_reg[4]_i_1_n_0 ,\two_inc_max_limit_reg[4]_i_1_n_1 ,\two_inc_max_limit_reg[4]_i_1_n_2 ,\two_inc_max_limit_reg[4]_i_1_n_3 }), .CYINIT(device_temp_init[0]), .DI({device_temp_init[4:3],1'b0,device_temp_init[1]}), .O({two_inc_max_limit_nxt[4:2],\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\two_inc_max_limit[4]_i_2_n_0 ,\two_inc_max_limit[4]_i_3_n_0 ,\two_inc_max_limit[4]_i_4_n_0 ,\two_inc_max_limit[4]_i_5_n_0 })); FDRE \two_inc_max_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[5]), .Q(two_inc_max_limit[5]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[6]), .Q(two_inc_max_limit[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[7]), .Q(two_inc_max_limit[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_max_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[8]), .Q(two_inc_max_limit[8]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_max_limit_reg[8]_i_1 (.CI(\two_inc_max_limit_reg[4]_i_1_n_0 ), .CO({\two_inc_max_limit_reg[8]_i_1_n_0 ,\two_inc_max_limit_reg[8]_i_1_n_1 ,\two_inc_max_limit_reg[8]_i_1_n_2 ,\two_inc_max_limit_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,device_temp_init[7],1'b0,1'b0}), .O(two_inc_max_limit_nxt[8:5]), .S({\two_inc_max_limit[8]_i_2_n_0 ,\two_inc_max_limit[8]_i_3_n_0 ,\two_inc_max_limit[8]_i_4_n_0 ,\two_inc_max_limit[8]_i_5_n_0 })); FDRE \two_inc_max_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_inc_max_limit_nxt[9]), .Q(two_inc_max_limit[9]), .R(rstdiv0_sync_r1_reg_rep__4)); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[11]_i_2 (.I0(three_inc_max_limit[11]), .O(\two_inc_min_limit[11]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[11]_i_3 (.I0(three_inc_max_limit[10]), .O(\two_inc_min_limit[11]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[5]_i_2 (.I0(three_inc_max_limit[5]), .O(\two_inc_min_limit[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[5]_i_3 (.I0(three_inc_max_limit[4]), .O(\two_inc_min_limit[5]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[5]_i_4 (.I0(three_inc_max_limit[3]), .O(\two_inc_min_limit[5]_i_4_n_0 )); LUT1 #( .INIT(2'h2)) \two_inc_min_limit[5]_i_5 (.I0(three_inc_max_limit[2]), .O(\two_inc_min_limit[5]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_2 (.I0(three_inc_max_limit[9]), .O(\two_inc_min_limit[9]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_3 (.I0(three_inc_max_limit[8]), .O(\two_inc_min_limit[9]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_4 (.I0(three_inc_max_limit[7]), .O(\two_inc_min_limit[9]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \two_inc_min_limit[9]_i_5 (.I0(three_inc_max_limit[6]), .O(\two_inc_min_limit[9]_i_5_n_0 )); FDRE \two_inc_min_limit_reg[10] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[10]), .Q(two_inc_min_limit[10]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[11] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[11]), .Q(two_inc_min_limit[11]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_min_limit_reg[11]_i_1 (.CI(\two_inc_min_limit_reg[9]_i_1_n_0 ), .CO({\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_inc_min_limit_reg[11]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}), .O({\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}), .S({1'b0,1'b0,\two_inc_min_limit[11]_i_2_n_0 ,\two_inc_min_limit[11]_i_3_n_0 })); FDRE \two_inc_min_limit_reg[1] (.C(CLK), .CE(1'b1), .D(three_inc_max_limit[1]), .Q(two_inc_min_limit[1]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[2] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[2]), .Q(two_inc_min_limit[2]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[3] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[3]), .Q(two_inc_min_limit[3]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[4] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[4]), .Q(two_inc_min_limit[4]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[5] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[5]), .Q(two_inc_min_limit[5]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_min_limit_reg[5]_i_1 (.CI(1'b0), .CO({\two_inc_min_limit_reg[5]_i_1_n_0 ,\two_inc_min_limit_reg[5]_i_1_n_1 ,\two_inc_min_limit_reg[5]_i_1_n_2 ,\two_inc_min_limit_reg[5]_i_1_n_3 }), .CYINIT(1'b0), .DI({three_inc_max_limit[5:3],1'b0}), .O(two_inc_min_limit_nxt[5:2]), .S({\two_inc_min_limit[5]_i_2_n_0 ,\two_inc_min_limit[5]_i_3_n_0 ,\two_inc_min_limit[5]_i_4_n_0 ,\two_inc_min_limit[5]_i_5_n_0 })); FDRE \two_inc_min_limit_reg[6] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[6]), .Q(two_inc_min_limit[6]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[7] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[7]), .Q(two_inc_min_limit[7]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[8] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[8]), .Q(two_inc_min_limit[8]), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE \two_inc_min_limit_reg[9] (.C(CLK), .CE(1'b1), .D(two_inc_min_limit_nxt[9]), .Q(two_inc_min_limit[9]), .R(rstdiv0_sync_r1_reg_rep__4)); CARRY4 \two_inc_min_limit_reg[9]_i_1 (.CI(\two_inc_min_limit_reg[5]_i_1_n_0 ), .CO({\two_inc_min_limit_reg[9]_i_1_n_0 ,\two_inc_min_limit_reg[9]_i_1_n_1 ,\two_inc_min_limit_reg[9]_i_1_n_2 ,\two_inc_min_limit_reg[9]_i_1_n_3 }), .CYINIT(1'b0), .DI(three_inc_max_limit[9:6]), .O(two_inc_min_limit_nxt[9:6]), .S({\two_inc_min_limit[9]_i_2_n_0 ,\two_inc_min_limit[9]_i_3_n_0 ,\two_inc_min_limit[9]_i_4_n_0 ,\two_inc_min_limit[9]_i_5_n_0 })); LUT3 #( .INIT(8'h40)) update_temp_101 (.I0(tempmon_sample_en_102), .I1(tempmon_init_complete), .I2(tempmon_sample_en_101), .O(update_temp_101__0)); FDRE update_temp_102_reg (.C(CLK), .CE(1'b1), .D(update_temp_101__0), .Q(update_temp_102), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_top (ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , phy_dout, \samps_r_reg[9] , app_zq_r_reg, \my_empty_reg[7] , init_calib_complete_r_reg, \calib_seq_reg[0] , \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_en_stg2_f_timing_reg, dqs_po_en_stg2_f_reg, \rd_ptr_timing_reg[0] , \resume_wait_r_reg[5] , phy_mc_ctl_full, stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, rd_buf_we, \not_strict_mode.status_ram.rd_buf_we_r1_reg , rst_sync_r1_reg, \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , D, \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[228] , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , maint_prescaler_r1, \cmd_pipe_plus.mc_data_offset_reg[3] , \cmd_pipe_plus.mc_data_offset_reg[5] , \cmd_pipe_plus.mc_data_offset_reg[4] , \cmd_pipe_plus.mc_data_offset_reg[2] , \cmd_pipe_plus.mc_data_offset_reg[1] , \cmd_pipe_plus.mc_data_offset_1_reg[3] , \cmd_pipe_plus.mc_data_offset_1_reg[5] , \cmd_pipe_plus.mc_data_offset_1_reg[4] , \cmd_pipe_plus.mc_data_offset_1_reg[2] , \cmd_pipe_plus.mc_data_offset_1_reg[1] , \read_fifo.tail_r_reg[0] , \cmd_pipe_plus.mc_data_offset_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0] , \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , \not_strict_mode.app_rd_data_reg[255]_0 , ofs_rdy_r_reg, ofs_rdy_r_reg_0, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[0]_0 , wr_en, wr_en_5, wr_en_6, of_ctl_full_v, ddr_ck_out, \qcntr_r_reg[0] , ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, idle, mmcm_ps_clk, rst_sync_r1, CLK, rstdiv0_sync_r1_reg_rep__20, poc_sample_pd, freq_refclk, mem_refclk, sync_pulse, pll_locked, in0, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__24, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, rstdiv0_sync_r1_reg_rep__23, SR, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__18, rstdiv0_sync_r1_reg_rep__16, SS, tempmon_sample_en, rstdiv0_sync_r1_reg_rep__7, \cmd_pipe_plus.mc_address_reg[43] , Q, mem_out, \rd_ptr_reg[3] , rstdiv0_sync_r1_reg_rep__26, rstdiv0_sync_r1_reg_rep__26_0, rstdiv0_sync_r1_reg_rep__25, \sm_r_reg[0]_0 , \rd_ptr_reg[3]_0 , \read_fifo.fifo_out_data_r_reg[6] , ram_init_done_r, mc_cas_n, mc_ras_n, mc_odt, mc_cke, mc_we_n, \cmd_pipe_plus.mc_address_reg[44] , \cmd_pipe_plus.mc_bank_reg[8] , mc_cs_n, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, rstdiv0_sync_r1_reg_rep__26_1, rstdiv0_sync_r1_reg_rep__26_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , sent_col, tail_r, \read_fifo.fifo_out_data_r_reg[6]_0 , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , psdone, rstdiv0_sync_r1_reg_rep__0, rstdiv0_sync_r1_reg_rep__19, fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__24_0, p_81_in, rstdiv0_sync_r1_reg_rep__24_1, rstdiv0_sync_r1_reg_rep__17, po_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__6, mc_wrdata_en, \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 , mc_cmd, \cmd_pipe_plus.mc_data_offset_reg[0]_0 , \cmd_pipe_plus.mc_data_offset_reg[1]_0 , \cmd_pipe_plus.mc_data_offset_reg[2]_0 , \cmd_pipe_plus.mc_data_offset_reg[3]_0 , \cmd_pipe_plus.mc_data_offset_reg[4]_0 , \cmd_pipe_plus.mc_data_offset_reg[5]_0 , \stg3_r_reg[0] , rstdiv0_sync_r1_reg_rep__8); output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [3:0]phy_dout; output \samps_r_reg[9] ; output app_zq_r_reg; output \my_empty_reg[7] ; output init_calib_complete_r_reg; output \calib_seq_reg[0] ; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_en_stg2_f_timing_reg; output dqs_po_en_stg2_f_reg; output [33:0]\rd_ptr_timing_reg[0] ; output \resume_wait_r_reg[5] ; output phy_mc_ctl_full; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output rd_buf_we; output \not_strict_mode.status_ram.rd_buf_we_r1_reg ; output rst_sync_r1_reg; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]D; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[228] ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output maint_prescaler_r1; output \cmd_pipe_plus.mc_data_offset_reg[3] ; output [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; output \cmd_pipe_plus.mc_data_offset_reg[4] ; output \cmd_pipe_plus.mc_data_offset_reg[2] ; output \cmd_pipe_plus.mc_data_offset_reg[1] ; output \cmd_pipe_plus.mc_data_offset_1_reg[3] ; output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; output \cmd_pipe_plus.mc_data_offset_1_reg[4] ; output \cmd_pipe_plus.mc_data_offset_1_reg[2] ; output \cmd_pipe_plus.mc_data_offset_1_reg[1] ; output \read_fifo.tail_r_reg[0] ; output \cmd_pipe_plus.mc_data_offset_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output ofs_rdy_r_reg; output ofs_rdy_r_reg_0; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output [1:0]\rd_ptr_timing_reg[0]_0 ; output wr_en; output wr_en_5; output wr_en_6; output [0:0]of_ctl_full_v; output [1:0]ddr_ck_out; output [0:0]\qcntr_r_reg[0] ; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input idle; input mmcm_ps_clk; input rst_sync_r1; input CLK; input rstdiv0_sync_r1_reg_rep__20; input poc_sample_pd; input freq_refclk; input mem_refclk; input sync_pulse; input pll_locked; input in0; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__24; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input rstdiv0_sync_r1_reg_rep__23; input [0:0]SR; input [0:0]rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [0:0]rstdiv0_sync_r1_reg_rep__18; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input tempmon_sample_en; input rstdiv0_sync_r1_reg_rep__7; input [1:0]\cmd_pipe_plus.mc_address_reg[43] ; input [287:0]Q; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input rstdiv0_sync_r1_reg_rep__26; input rstdiv0_sync_r1_reg_rep__26_0; input rstdiv0_sync_r1_reg_rep__25; input [0:0]\sm_r_reg[0]_0 ; input [29:0]\rd_ptr_reg[3]_0 ; input [0:0]\read_fifo.fifo_out_data_r_reg[6] ; input ram_init_done_r; input [2:0]mc_cas_n; input [2:0]mc_ras_n; input [0:0]mc_odt; input [0:0]mc_cke; input [2:0]mc_we_n; input [37:0]\cmd_pipe_plus.mc_address_reg[44] ; input [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; input [0:0]mc_cs_n; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input rstdiv0_sync_r1_reg_rep__26_1; input rstdiv0_sync_r1_reg_rep__26_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input sent_col; input [0:0]tail_r; input \read_fifo.fifo_out_data_r_reg[6]_0 ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input psdone; input rstdiv0_sync_r1_reg_rep__0; input [0:0]rstdiv0_sync_r1_reg_rep__19; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__24_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__24_1; input [0:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]po_cnt_dec_reg; input [0:0]rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__6; input mc_wrdata_en; input \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; input [1:0]mc_cmd; input \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[2]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[3]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; input \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; input \stg3_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__8; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [287:0]Q; wire RST0; wire [0:0]SR; wire [0:0]SS; wire app_zq_r_reg; wire [1:0]byte_sel_cnt; wire [1:0]calib_sel; wire [3:3]calib_sel__0; wire [1:0]calib_seq; wire \calib_seq_reg[0] ; wire [1:0]\cmd_pipe_plus.mc_address_reg[43] ; wire [37:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[1] ; wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[2] ; wire \cmd_pipe_plus.mc_data_offset_reg[2]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[3] ; wire \cmd_pipe_plus.mc_data_offset_reg[3]_0 ; wire \cmd_pipe_plus.mc_data_offset_reg[4] ; wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ; wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ; wire cnt_pwron_reset_done_r0; wire \complex_row_cnt_ocal_reg[0] ; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire [1:0]\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ; wire [11:0]\device_temp_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire dqs_po_en_stg2_f_reg; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire fine_adjust_reg; wire [26:2]fine_delay_mod; wire fine_delay_sel_r; wire freq_refclk; wire idelay_inc; wire idle; wire in0; wire init_calib_complete_r_reg; wire maint_prescaler_r1; wire [2:0]mc_cas_n; wire [0:0]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_we_n; wire mc_wrdata_en; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [57:5]mux_address; wire mux_cmd_wren; wire [5:0]mux_data_offset_1; wire mux_reset_n; wire [255:0]mux_wrdata; wire mux_wrdata_en; wire [31:0]mux_wrdata_mask; wire \my_empty_reg[7] ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire \not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [55:0]\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns ; wire [7:0]\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ; wire [0:0]of_ctl_full_v; wire ofs_rdy_r_reg; wire ofs_rdy_r_reg_0; wire [22:0]p_1_out; wire p_81_in; wire pd_out; wire [3:0]phy_dout; wire phy_if_reset; wire phy_mc_ctl_full; wire phy_rddata_en; wire phy_read_calib; wire phy_write_calib; wire [0:0]pi_cnt_dec_reg; wire pi_en_stg2_f_timing_reg; wire \pi_rst_stg1_cal_r_reg[0] ; wire pll_locked; wire [0:0]po_cnt_dec_reg; wire [1:0]po_stg2_wrcal_cnt; wire poc_sample_pd; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire ram_init_done_r; wire rd_buf_we; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [33:0]\rd_ptr_timing_reg[0] ; wire [1:0]\rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [0:0]\read_fifo.fifo_out_data_r_reg[6] ; wire \read_fifo.fifo_out_data_r_reg[6]_0 ; wire \read_fifo.tail_r_reg[0] ; wire \resume_wait_r_reg[5] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [0:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__24_0; wire rstdiv0_sync_r1_reg_rep__24_1; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__26_1; wire rstdiv0_sync_r1_reg_rep__26_2; wire rstdiv0_sync_r1_reg_rep__4; wire [0:0]rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire \samps_r_reg[9] ; wire sent_col; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire tempmon_sample_en; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_37; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_38; wire u_ddr_calib_top_n_385; wire u_ddr_calib_top_n_386; wire u_ddr_calib_top_n_387; wire u_ddr_calib_top_n_388; wire u_ddr_calib_top_n_389; wire u_ddr_calib_top_n_390; wire u_ddr_calib_top_n_391; wire u_ddr_calib_top_n_392; wire u_ddr_calib_top_n_393; wire u_ddr_calib_top_n_394; wire u_ddr_calib_top_n_395; wire u_ddr_calib_top_n_396; wire u_ddr_calib_top_n_397; wire u_ddr_calib_top_n_399; wire u_ddr_calib_top_n_400; wire u_ddr_calib_top_n_401; wire u_ddr_calib_top_n_402; wire u_ddr_calib_top_n_403; wire u_ddr_calib_top_n_404; wire u_ddr_calib_top_n_405; wire u_ddr_calib_top_n_406; wire u_ddr_calib_top_n_407; wire u_ddr_calib_top_n_408; wire u_ddr_calib_top_n_409; wire u_ddr_calib_top_n_410; wire u_ddr_calib_top_n_411; wire u_ddr_calib_top_n_412; wire u_ddr_calib_top_n_413; wire u_ddr_calib_top_n_414; wire u_ddr_calib_top_n_415; wire u_ddr_calib_top_n_416; wire u_ddr_calib_top_n_417; wire u_ddr_calib_top_n_418; wire u_ddr_calib_top_n_419; wire u_ddr_calib_top_n_420; wire u_ddr_calib_top_n_421; wire u_ddr_calib_top_n_422; wire u_ddr_calib_top_n_423; wire u_ddr_calib_top_n_424; wire u_ddr_calib_top_n_425; wire u_ddr_calib_top_n_426; wire u_ddr_calib_top_n_427; wire u_ddr_calib_top_n_428; wire u_ddr_calib_top_n_429; wire u_ddr_calib_top_n_430; wire u_ddr_calib_top_n_431; wire u_ddr_calib_top_n_432; wire u_ddr_calib_top_n_433; wire u_ddr_calib_top_n_434; wire u_ddr_calib_top_n_435; wire u_ddr_calib_top_n_436; wire u_ddr_calib_top_n_437; wire u_ddr_calib_top_n_438; wire u_ddr_calib_top_n_439; wire u_ddr_calib_top_n_441; wire u_ddr_calib_top_n_442; wire u_ddr_calib_top_n_443; wire u_ddr_calib_top_n_444; wire u_ddr_calib_top_n_445; wire u_ddr_calib_top_n_446; wire u_ddr_calib_top_n_447; wire u_ddr_calib_top_n_448; wire u_ddr_calib_top_n_449; wire u_ddr_calib_top_n_45; wire u_ddr_calib_top_n_450; wire u_ddr_calib_top_n_451; wire u_ddr_calib_top_n_452; wire u_ddr_calib_top_n_453; wire u_ddr_calib_top_n_454; wire u_ddr_calib_top_n_455; wire u_ddr_calib_top_n_456; wire u_ddr_calib_top_n_457; wire u_ddr_calib_top_n_458; wire u_ddr_calib_top_n_461; wire u_ddr_calib_top_n_464; wire u_ddr_calib_top_n_47; wire u_ddr_calib_top_n_50; wire u_ddr_calib_top_n_809; wire u_ddr_calib_top_n_810; wire u_ddr_calib_top_n_837; wire u_ddr_calib_top_n_838; wire u_ddr_calib_top_n_844; wire u_ddr_calib_top_n_845; wire u_ddr_calib_top_n_859; wire u_ddr_calib_top_n_860; wire u_ddr_calib_top_n_861; wire u_ddr_calib_top_n_862; wire u_ddr_calib_top_n_863; wire u_ddr_calib_top_n_864; wire u_ddr_calib_top_n_865; wire u_ddr_calib_top_n_879; wire u_ddr_calib_top_n_880; wire u_ddr_calib_top_n_881; wire u_ddr_calib_top_n_882; wire u_ddr_calib_top_n_883; wire u_ddr_calib_top_n_884; wire u_ddr_calib_top_n_885; wire u_ddr_calib_top_n_886; wire [2:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay ; wire [26:5]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay ; wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ; wire [26:5]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay ; wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ; wire [26:5]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay ; wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [0:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ; wire [0:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ; wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ; wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ; wire [8:8]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ; wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ; wire [7:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ; wire [7:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ; wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ; wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ; wire [67:8]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ; wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ; wire [5:0]\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ; wire [8:0]\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ; wire [8:0]\u_ddr_mc_phy/po_counter_read_val_w[1]_2 ; wire u_ddr_mc_phy_wrapper_n_1000; wire u_ddr_mc_phy_wrapper_n_1001; wire u_ddr_mc_phy_wrapper_n_1002; wire u_ddr_mc_phy_wrapper_n_1003; wire u_ddr_mc_phy_wrapper_n_1004; wire u_ddr_mc_phy_wrapper_n_1005; wire u_ddr_mc_phy_wrapper_n_1006; wire u_ddr_mc_phy_wrapper_n_1007; wire u_ddr_mc_phy_wrapper_n_1008; wire u_ddr_mc_phy_wrapper_n_1009; wire u_ddr_mc_phy_wrapper_n_1010; wire u_ddr_mc_phy_wrapper_n_1011; wire u_ddr_mc_phy_wrapper_n_1012; wire u_ddr_mc_phy_wrapper_n_1013; wire u_ddr_mc_phy_wrapper_n_1014; wire u_ddr_mc_phy_wrapper_n_1015; wire u_ddr_mc_phy_wrapper_n_1016; wire u_ddr_mc_phy_wrapper_n_1017; wire u_ddr_mc_phy_wrapper_n_1018; wire u_ddr_mc_phy_wrapper_n_1019; wire u_ddr_mc_phy_wrapper_n_102; wire u_ddr_mc_phy_wrapper_n_1020; wire u_ddr_mc_phy_wrapper_n_1021; wire u_ddr_mc_phy_wrapper_n_1022; wire u_ddr_mc_phy_wrapper_n_1023; wire u_ddr_mc_phy_wrapper_n_1024; wire u_ddr_mc_phy_wrapper_n_1025; wire u_ddr_mc_phy_wrapper_n_1026; wire u_ddr_mc_phy_wrapper_n_1027; wire u_ddr_mc_phy_wrapper_n_1028; wire u_ddr_mc_phy_wrapper_n_1029; wire u_ddr_mc_phy_wrapper_n_1030; wire u_ddr_mc_phy_wrapper_n_1033; wire u_ddr_mc_phy_wrapper_n_1034; wire u_ddr_mc_phy_wrapper_n_1035; wire u_ddr_mc_phy_wrapper_n_1036; wire u_ddr_mc_phy_wrapper_n_1037; wire u_ddr_mc_phy_wrapper_n_1038; wire u_ddr_mc_phy_wrapper_n_1039; wire u_ddr_mc_phy_wrapper_n_104; wire u_ddr_mc_phy_wrapper_n_1040; wire u_ddr_mc_phy_wrapper_n_1041; wire u_ddr_mc_phy_wrapper_n_1042; wire u_ddr_mc_phy_wrapper_n_1043; wire u_ddr_mc_phy_wrapper_n_1044; wire u_ddr_mc_phy_wrapper_n_1045; wire u_ddr_mc_phy_wrapper_n_1046; wire u_ddr_mc_phy_wrapper_n_1047; wire u_ddr_mc_phy_wrapper_n_1048; wire u_ddr_mc_phy_wrapper_n_1049; wire u_ddr_mc_phy_wrapper_n_1050; wire u_ddr_mc_phy_wrapper_n_1051; wire u_ddr_mc_phy_wrapper_n_1052; wire u_ddr_mc_phy_wrapper_n_1053; wire u_ddr_mc_phy_wrapper_n_1054; wire u_ddr_mc_phy_wrapper_n_1055; wire u_ddr_mc_phy_wrapper_n_1056; wire u_ddr_mc_phy_wrapper_n_1057; wire u_ddr_mc_phy_wrapper_n_1058; wire u_ddr_mc_phy_wrapper_n_1059; wire u_ddr_mc_phy_wrapper_n_106; wire u_ddr_mc_phy_wrapper_n_1060; wire u_ddr_mc_phy_wrapper_n_1061; wire u_ddr_mc_phy_wrapper_n_1062; wire u_ddr_mc_phy_wrapper_n_1063; wire u_ddr_mc_phy_wrapper_n_1064; wire u_ddr_mc_phy_wrapper_n_1065; wire u_ddr_mc_phy_wrapper_n_1066; wire u_ddr_mc_phy_wrapper_n_1067; wire u_ddr_mc_phy_wrapper_n_1068; wire u_ddr_mc_phy_wrapper_n_1069; wire u_ddr_mc_phy_wrapper_n_107; wire u_ddr_mc_phy_wrapper_n_1070; wire u_ddr_mc_phy_wrapper_n_1071; wire u_ddr_mc_phy_wrapper_n_1072; wire u_ddr_mc_phy_wrapper_n_1073; wire u_ddr_mc_phy_wrapper_n_1074; wire u_ddr_mc_phy_wrapper_n_1075; wire u_ddr_mc_phy_wrapper_n_1076; wire u_ddr_mc_phy_wrapper_n_1077; wire u_ddr_mc_phy_wrapper_n_1078; wire u_ddr_mc_phy_wrapper_n_1079; wire u_ddr_mc_phy_wrapper_n_108; wire u_ddr_mc_phy_wrapper_n_1080; wire u_ddr_mc_phy_wrapper_n_1081; wire u_ddr_mc_phy_wrapper_n_1082; wire u_ddr_mc_phy_wrapper_n_1083; wire u_ddr_mc_phy_wrapper_n_1084; wire u_ddr_mc_phy_wrapper_n_1085; wire u_ddr_mc_phy_wrapper_n_1086; wire u_ddr_mc_phy_wrapper_n_1087; wire u_ddr_mc_phy_wrapper_n_1088; wire u_ddr_mc_phy_wrapper_n_1089; wire u_ddr_mc_phy_wrapper_n_109; wire u_ddr_mc_phy_wrapper_n_1090; wire u_ddr_mc_phy_wrapper_n_1091; wire u_ddr_mc_phy_wrapper_n_1092; wire u_ddr_mc_phy_wrapper_n_1093; wire u_ddr_mc_phy_wrapper_n_1094; wire u_ddr_mc_phy_wrapper_n_1095; wire u_ddr_mc_phy_wrapper_n_1096; wire u_ddr_mc_phy_wrapper_n_110; wire u_ddr_mc_phy_wrapper_n_111; wire u_ddr_mc_phy_wrapper_n_112; wire u_ddr_mc_phy_wrapper_n_1127; wire u_ddr_mc_phy_wrapper_n_1129; wire u_ddr_mc_phy_wrapper_n_1130; wire u_ddr_mc_phy_wrapper_n_1131; wire u_ddr_mc_phy_wrapper_n_1132; wire u_ddr_mc_phy_wrapper_n_1133; wire u_ddr_mc_phy_wrapper_n_1134; wire u_ddr_mc_phy_wrapper_n_1135; wire u_ddr_mc_phy_wrapper_n_1136; wire u_ddr_mc_phy_wrapper_n_1137; wire u_ddr_mc_phy_wrapper_n_1138; wire u_ddr_mc_phy_wrapper_n_1139; wire u_ddr_mc_phy_wrapper_n_1140; wire u_ddr_mc_phy_wrapper_n_1141; wire u_ddr_mc_phy_wrapper_n_1142; wire u_ddr_mc_phy_wrapper_n_1143; wire u_ddr_mc_phy_wrapper_n_1144; wire u_ddr_mc_phy_wrapper_n_1145; wire u_ddr_mc_phy_wrapper_n_1146; wire u_ddr_mc_phy_wrapper_n_1147; wire u_ddr_mc_phy_wrapper_n_1148; wire u_ddr_mc_phy_wrapper_n_1149; wire u_ddr_mc_phy_wrapper_n_1150; wire u_ddr_mc_phy_wrapper_n_1151; wire u_ddr_mc_phy_wrapper_n_1152; wire u_ddr_mc_phy_wrapper_n_1153; wire u_ddr_mc_phy_wrapper_n_1154; wire u_ddr_mc_phy_wrapper_n_1155; wire u_ddr_mc_phy_wrapper_n_1156; wire u_ddr_mc_phy_wrapper_n_1157; wire u_ddr_mc_phy_wrapper_n_1158; wire u_ddr_mc_phy_wrapper_n_1159; wire u_ddr_mc_phy_wrapper_n_1160; wire u_ddr_mc_phy_wrapper_n_1161; wire u_ddr_mc_phy_wrapper_n_1162; wire u_ddr_mc_phy_wrapper_n_1163; wire u_ddr_mc_phy_wrapper_n_1164; wire u_ddr_mc_phy_wrapper_n_1165; wire u_ddr_mc_phy_wrapper_n_1166; wire u_ddr_mc_phy_wrapper_n_1167; wire u_ddr_mc_phy_wrapper_n_1168; wire u_ddr_mc_phy_wrapper_n_1169; wire u_ddr_mc_phy_wrapper_n_1170; wire u_ddr_mc_phy_wrapper_n_1171; wire u_ddr_mc_phy_wrapper_n_1172; wire u_ddr_mc_phy_wrapper_n_1173; wire u_ddr_mc_phy_wrapper_n_1174; wire u_ddr_mc_phy_wrapper_n_1175; wire u_ddr_mc_phy_wrapper_n_1176; wire u_ddr_mc_phy_wrapper_n_1177; wire u_ddr_mc_phy_wrapper_n_1178; wire u_ddr_mc_phy_wrapper_n_1179; wire u_ddr_mc_phy_wrapper_n_1180; wire u_ddr_mc_phy_wrapper_n_1181; wire u_ddr_mc_phy_wrapper_n_1182; wire u_ddr_mc_phy_wrapper_n_1183; wire u_ddr_mc_phy_wrapper_n_1184; wire u_ddr_mc_phy_wrapper_n_1185; wire u_ddr_mc_phy_wrapper_n_1186; wire u_ddr_mc_phy_wrapper_n_1187; wire u_ddr_mc_phy_wrapper_n_1188; wire u_ddr_mc_phy_wrapper_n_1189; wire u_ddr_mc_phy_wrapper_n_1190; wire u_ddr_mc_phy_wrapper_n_1191; wire u_ddr_mc_phy_wrapper_n_30; wire u_ddr_mc_phy_wrapper_n_43; wire u_ddr_mc_phy_wrapper_n_434; wire u_ddr_mc_phy_wrapper_n_435; wire u_ddr_mc_phy_wrapper_n_436; wire u_ddr_mc_phy_wrapper_n_437; wire u_ddr_mc_phy_wrapper_n_438; wire u_ddr_mc_phy_wrapper_n_439; wire u_ddr_mc_phy_wrapper_n_44; wire u_ddr_mc_phy_wrapper_n_440; wire u_ddr_mc_phy_wrapper_n_441; wire u_ddr_mc_phy_wrapper_n_442; wire u_ddr_mc_phy_wrapper_n_443; wire u_ddr_mc_phy_wrapper_n_444; wire u_ddr_mc_phy_wrapper_n_445; wire u_ddr_mc_phy_wrapper_n_446; wire u_ddr_mc_phy_wrapper_n_447; wire u_ddr_mc_phy_wrapper_n_448; wire u_ddr_mc_phy_wrapper_n_449; wire u_ddr_mc_phy_wrapper_n_45; wire u_ddr_mc_phy_wrapper_n_450; wire u_ddr_mc_phy_wrapper_n_451; wire u_ddr_mc_phy_wrapper_n_452; wire u_ddr_mc_phy_wrapper_n_453; wire u_ddr_mc_phy_wrapper_n_454; wire u_ddr_mc_phy_wrapper_n_455; wire u_ddr_mc_phy_wrapper_n_456; wire u_ddr_mc_phy_wrapper_n_457; wire u_ddr_mc_phy_wrapper_n_458; wire u_ddr_mc_phy_wrapper_n_459; wire u_ddr_mc_phy_wrapper_n_46; wire u_ddr_mc_phy_wrapper_n_460; wire u_ddr_mc_phy_wrapper_n_461; wire u_ddr_mc_phy_wrapper_n_462; wire u_ddr_mc_phy_wrapper_n_463; wire u_ddr_mc_phy_wrapper_n_464; wire u_ddr_mc_phy_wrapper_n_465; wire u_ddr_mc_phy_wrapper_n_466; wire u_ddr_mc_phy_wrapper_n_467; wire u_ddr_mc_phy_wrapper_n_468; wire u_ddr_mc_phy_wrapper_n_469; wire u_ddr_mc_phy_wrapper_n_470; wire u_ddr_mc_phy_wrapper_n_471; wire u_ddr_mc_phy_wrapper_n_472; wire u_ddr_mc_phy_wrapper_n_473; wire u_ddr_mc_phy_wrapper_n_474; wire u_ddr_mc_phy_wrapper_n_475; wire u_ddr_mc_phy_wrapper_n_476; wire u_ddr_mc_phy_wrapper_n_477; wire u_ddr_mc_phy_wrapper_n_478; wire u_ddr_mc_phy_wrapper_n_479; wire u_ddr_mc_phy_wrapper_n_480; wire u_ddr_mc_phy_wrapper_n_481; wire u_ddr_mc_phy_wrapper_n_482; wire u_ddr_mc_phy_wrapper_n_483; wire u_ddr_mc_phy_wrapper_n_484; wire u_ddr_mc_phy_wrapper_n_485; wire u_ddr_mc_phy_wrapper_n_486; wire u_ddr_mc_phy_wrapper_n_487; wire u_ddr_mc_phy_wrapper_n_488; wire u_ddr_mc_phy_wrapper_n_489; wire u_ddr_mc_phy_wrapper_n_490; wire u_ddr_mc_phy_wrapper_n_491; wire u_ddr_mc_phy_wrapper_n_492; wire u_ddr_mc_phy_wrapper_n_493; wire u_ddr_mc_phy_wrapper_n_494; wire u_ddr_mc_phy_wrapper_n_495; wire u_ddr_mc_phy_wrapper_n_496; wire u_ddr_mc_phy_wrapper_n_497; wire u_ddr_mc_phy_wrapper_n_60; wire u_ddr_mc_phy_wrapper_n_61; wire u_ddr_mc_phy_wrapper_n_63; wire u_ddr_mc_phy_wrapper_n_64; wire u_ddr_mc_phy_wrapper_n_65; wire u_ddr_mc_phy_wrapper_n_66; wire u_ddr_mc_phy_wrapper_n_67; wire u_ddr_mc_phy_wrapper_n_756; wire u_ddr_mc_phy_wrapper_n_757; wire u_ddr_mc_phy_wrapper_n_758; wire u_ddr_mc_phy_wrapper_n_759; wire u_ddr_mc_phy_wrapper_n_760; wire u_ddr_mc_phy_wrapper_n_761; wire u_ddr_mc_phy_wrapper_n_762; wire u_ddr_mc_phy_wrapper_n_763; wire u_ddr_mc_phy_wrapper_n_764; wire u_ddr_mc_phy_wrapper_n_765; wire u_ddr_mc_phy_wrapper_n_766; wire u_ddr_mc_phy_wrapper_n_767; wire u_ddr_mc_phy_wrapper_n_768; wire u_ddr_mc_phy_wrapper_n_769; wire u_ddr_mc_phy_wrapper_n_770; wire u_ddr_mc_phy_wrapper_n_771; wire u_ddr_mc_phy_wrapper_n_772; wire u_ddr_mc_phy_wrapper_n_773; wire u_ddr_mc_phy_wrapper_n_774; wire u_ddr_mc_phy_wrapper_n_775; wire u_ddr_mc_phy_wrapper_n_776; wire u_ddr_mc_phy_wrapper_n_777; wire u_ddr_mc_phy_wrapper_n_778; wire u_ddr_mc_phy_wrapper_n_779; wire u_ddr_mc_phy_wrapper_n_780; wire u_ddr_mc_phy_wrapper_n_781; wire u_ddr_mc_phy_wrapper_n_782; wire u_ddr_mc_phy_wrapper_n_783; wire u_ddr_mc_phy_wrapper_n_784; wire u_ddr_mc_phy_wrapper_n_785; wire u_ddr_mc_phy_wrapper_n_786; wire u_ddr_mc_phy_wrapper_n_787; wire u_ddr_mc_phy_wrapper_n_788; wire u_ddr_mc_phy_wrapper_n_789; wire u_ddr_mc_phy_wrapper_n_790; wire u_ddr_mc_phy_wrapper_n_791; wire u_ddr_mc_phy_wrapper_n_792; wire u_ddr_mc_phy_wrapper_n_793; wire u_ddr_mc_phy_wrapper_n_794; wire u_ddr_mc_phy_wrapper_n_795; wire u_ddr_mc_phy_wrapper_n_796; wire u_ddr_mc_phy_wrapper_n_797; wire u_ddr_mc_phy_wrapper_n_798; wire u_ddr_mc_phy_wrapper_n_799; wire u_ddr_mc_phy_wrapper_n_800; wire u_ddr_mc_phy_wrapper_n_801; wire u_ddr_mc_phy_wrapper_n_802; wire u_ddr_mc_phy_wrapper_n_803; wire u_ddr_mc_phy_wrapper_n_804; wire u_ddr_mc_phy_wrapper_n_805; wire u_ddr_mc_phy_wrapper_n_806; wire u_ddr_mc_phy_wrapper_n_807; wire u_ddr_mc_phy_wrapper_n_808; wire u_ddr_mc_phy_wrapper_n_809; wire u_ddr_mc_phy_wrapper_n_810; wire u_ddr_mc_phy_wrapper_n_811; wire u_ddr_mc_phy_wrapper_n_812; wire u_ddr_mc_phy_wrapper_n_813; wire u_ddr_mc_phy_wrapper_n_814; wire u_ddr_mc_phy_wrapper_n_815; wire u_ddr_mc_phy_wrapper_n_816; wire u_ddr_mc_phy_wrapper_n_817; wire u_ddr_mc_phy_wrapper_n_818; wire u_ddr_mc_phy_wrapper_n_819; wire u_ddr_mc_phy_wrapper_n_820; wire u_ddr_mc_phy_wrapper_n_835; wire u_ddr_mc_phy_wrapper_n_836; wire u_ddr_mc_phy_wrapper_n_837; wire u_ddr_mc_phy_wrapper_n_838; wire u_ddr_mc_phy_wrapper_n_839; wire u_ddr_mc_phy_wrapper_n_840; wire u_ddr_mc_phy_wrapper_n_841; wire u_ddr_mc_phy_wrapper_n_842; wire u_ddr_mc_phy_wrapper_n_843; wire u_ddr_mc_phy_wrapper_n_844; wire u_ddr_mc_phy_wrapper_n_845; wire u_ddr_mc_phy_wrapper_n_846; wire u_ddr_mc_phy_wrapper_n_847; wire u_ddr_mc_phy_wrapper_n_848; wire u_ddr_mc_phy_wrapper_n_849; wire u_ddr_mc_phy_wrapper_n_850; wire u_ddr_mc_phy_wrapper_n_851; wire u_ddr_mc_phy_wrapper_n_852; wire u_ddr_mc_phy_wrapper_n_853; wire u_ddr_mc_phy_wrapper_n_854; wire u_ddr_mc_phy_wrapper_n_855; wire u_ddr_mc_phy_wrapper_n_856; wire u_ddr_mc_phy_wrapper_n_857; wire u_ddr_mc_phy_wrapper_n_858; wire u_ddr_mc_phy_wrapper_n_859; wire u_ddr_mc_phy_wrapper_n_860; wire u_ddr_mc_phy_wrapper_n_861; wire u_ddr_mc_phy_wrapper_n_862; wire u_ddr_mc_phy_wrapper_n_863; wire u_ddr_mc_phy_wrapper_n_864; wire u_ddr_mc_phy_wrapper_n_865; wire u_ddr_mc_phy_wrapper_n_866; wire u_ddr_mc_phy_wrapper_n_867; wire u_ddr_mc_phy_wrapper_n_868; wire u_ddr_mc_phy_wrapper_n_869; wire u_ddr_mc_phy_wrapper_n_870; wire u_ddr_mc_phy_wrapper_n_871; wire u_ddr_mc_phy_wrapper_n_872; wire u_ddr_mc_phy_wrapper_n_873; wire u_ddr_mc_phy_wrapper_n_874; wire u_ddr_mc_phy_wrapper_n_875; wire u_ddr_mc_phy_wrapper_n_876; wire u_ddr_mc_phy_wrapper_n_877; wire u_ddr_mc_phy_wrapper_n_878; wire u_ddr_mc_phy_wrapper_n_879; wire u_ddr_mc_phy_wrapper_n_880; wire u_ddr_mc_phy_wrapper_n_881; wire u_ddr_mc_phy_wrapper_n_882; wire u_ddr_mc_phy_wrapper_n_883; wire u_ddr_mc_phy_wrapper_n_884; wire u_ddr_mc_phy_wrapper_n_885; wire u_ddr_mc_phy_wrapper_n_886; wire u_ddr_mc_phy_wrapper_n_887; wire u_ddr_mc_phy_wrapper_n_888; wire u_ddr_mc_phy_wrapper_n_889; wire u_ddr_mc_phy_wrapper_n_890; wire u_ddr_mc_phy_wrapper_n_891; wire u_ddr_mc_phy_wrapper_n_892; wire u_ddr_mc_phy_wrapper_n_893; wire u_ddr_mc_phy_wrapper_n_894; wire u_ddr_mc_phy_wrapper_n_895; wire u_ddr_mc_phy_wrapper_n_896; wire u_ddr_mc_phy_wrapper_n_897; wire u_ddr_mc_phy_wrapper_n_898; wire u_ddr_mc_phy_wrapper_n_901; wire u_ddr_mc_phy_wrapper_n_902; wire u_ddr_mc_phy_wrapper_n_903; wire u_ddr_mc_phy_wrapper_n_904; wire u_ddr_mc_phy_wrapper_n_905; wire u_ddr_mc_phy_wrapper_n_906; wire u_ddr_mc_phy_wrapper_n_907; wire u_ddr_mc_phy_wrapper_n_908; wire u_ddr_mc_phy_wrapper_n_909; wire u_ddr_mc_phy_wrapper_n_910; wire u_ddr_mc_phy_wrapper_n_911; wire u_ddr_mc_phy_wrapper_n_912; wire u_ddr_mc_phy_wrapper_n_913; wire u_ddr_mc_phy_wrapper_n_914; wire u_ddr_mc_phy_wrapper_n_915; wire u_ddr_mc_phy_wrapper_n_916; wire u_ddr_mc_phy_wrapper_n_917; wire u_ddr_mc_phy_wrapper_n_918; wire u_ddr_mc_phy_wrapper_n_919; wire u_ddr_mc_phy_wrapper_n_920; wire u_ddr_mc_phy_wrapper_n_921; wire u_ddr_mc_phy_wrapper_n_922; wire u_ddr_mc_phy_wrapper_n_923; wire u_ddr_mc_phy_wrapper_n_924; wire u_ddr_mc_phy_wrapper_n_925; wire u_ddr_mc_phy_wrapper_n_926; wire u_ddr_mc_phy_wrapper_n_927; wire u_ddr_mc_phy_wrapper_n_928; wire u_ddr_mc_phy_wrapper_n_929; wire u_ddr_mc_phy_wrapper_n_930; wire u_ddr_mc_phy_wrapper_n_931; wire u_ddr_mc_phy_wrapper_n_932; wire u_ddr_mc_phy_wrapper_n_933; wire u_ddr_mc_phy_wrapper_n_934; wire u_ddr_mc_phy_wrapper_n_935; wire u_ddr_mc_phy_wrapper_n_936; wire u_ddr_mc_phy_wrapper_n_937; wire u_ddr_mc_phy_wrapper_n_938; wire u_ddr_mc_phy_wrapper_n_939; wire u_ddr_mc_phy_wrapper_n_940; wire u_ddr_mc_phy_wrapper_n_941; wire u_ddr_mc_phy_wrapper_n_942; wire u_ddr_mc_phy_wrapper_n_943; wire u_ddr_mc_phy_wrapper_n_944; wire u_ddr_mc_phy_wrapper_n_945; wire u_ddr_mc_phy_wrapper_n_946; wire u_ddr_mc_phy_wrapper_n_947; wire u_ddr_mc_phy_wrapper_n_948; wire u_ddr_mc_phy_wrapper_n_949; wire u_ddr_mc_phy_wrapper_n_950; wire u_ddr_mc_phy_wrapper_n_951; wire u_ddr_mc_phy_wrapper_n_952; wire u_ddr_mc_phy_wrapper_n_953; wire u_ddr_mc_phy_wrapper_n_954; wire u_ddr_mc_phy_wrapper_n_955; wire u_ddr_mc_phy_wrapper_n_956; wire u_ddr_mc_phy_wrapper_n_957; wire u_ddr_mc_phy_wrapper_n_958; wire u_ddr_mc_phy_wrapper_n_959; wire u_ddr_mc_phy_wrapper_n_960; wire u_ddr_mc_phy_wrapper_n_961; wire u_ddr_mc_phy_wrapper_n_962; wire u_ddr_mc_phy_wrapper_n_963; wire u_ddr_mc_phy_wrapper_n_964; wire u_ddr_mc_phy_wrapper_n_967; wire u_ddr_mc_phy_wrapper_n_968; wire u_ddr_mc_phy_wrapper_n_969; wire u_ddr_mc_phy_wrapper_n_970; wire u_ddr_mc_phy_wrapper_n_971; wire u_ddr_mc_phy_wrapper_n_972; wire u_ddr_mc_phy_wrapper_n_973; wire u_ddr_mc_phy_wrapper_n_974; wire u_ddr_mc_phy_wrapper_n_975; wire u_ddr_mc_phy_wrapper_n_976; wire u_ddr_mc_phy_wrapper_n_977; wire u_ddr_mc_phy_wrapper_n_978; wire u_ddr_mc_phy_wrapper_n_979; wire u_ddr_mc_phy_wrapper_n_980; wire u_ddr_mc_phy_wrapper_n_981; wire u_ddr_mc_phy_wrapper_n_982; wire u_ddr_mc_phy_wrapper_n_983; wire u_ddr_mc_phy_wrapper_n_984; wire u_ddr_mc_phy_wrapper_n_985; wire u_ddr_mc_phy_wrapper_n_986; wire u_ddr_mc_phy_wrapper_n_987; wire u_ddr_mc_phy_wrapper_n_988; wire u_ddr_mc_phy_wrapper_n_989; wire u_ddr_mc_phy_wrapper_n_990; wire u_ddr_mc_phy_wrapper_n_991; wire u_ddr_mc_phy_wrapper_n_992; wire u_ddr_mc_phy_wrapper_n_993; wire u_ddr_mc_phy_wrapper_n_994; wire u_ddr_mc_phy_wrapper_n_995; wire u_ddr_mc_phy_wrapper_n_996; wire u_ddr_mc_phy_wrapper_n_997; wire u_ddr_mc_phy_wrapper_n_998; wire u_ddr_mc_phy_wrapper_n_999; wire \u_ddr_phy_wrcal/p_0_out ; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; ddr3_if_mig_7series_v4_0_ddr_calib_top u_ddr_calib_top (.A(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ), .\A[0]__0 (u_ddr_calib_top_n_881), .\A[0]__4 (u_ddr_calib_top_n_880), .\A[1]_0 (u_ddr_mc_phy_wrapper_n_813), .\A[1]_1 (u_ddr_mc_phy_wrapper_n_805), .\A[1]_10 (u_ddr_mc_phy_wrapper_n_798), .\A[1]_11 (u_ddr_mc_phy_wrapper_n_790), .\A[1]_12 (u_ddr_mc_phy_wrapper_n_782), .\A[1]_13 (u_ddr_mc_phy_wrapper_n_774), .\A[1]_14 (u_ddr_mc_phy_wrapper_n_766), .\A[1]_15 (u_ddr_mc_phy_wrapper_n_758), .\A[1]_16 (u_ddr_mc_phy_wrapper_n_815), .\A[1]_17 (u_ddr_mc_phy_wrapper_n_807), .\A[1]_18 (u_ddr_mc_phy_wrapper_n_799), .\A[1]_19 (u_ddr_mc_phy_wrapper_n_791), .\A[1]_2 (u_ddr_mc_phy_wrapper_n_797), .\A[1]_20 (u_ddr_mc_phy_wrapper_n_783), .\A[1]_21 (u_ddr_mc_phy_wrapper_n_775), .\A[1]_22 (u_ddr_mc_phy_wrapper_n_767), .\A[1]_23 (u_ddr_mc_phy_wrapper_n_759), .\A[1]_24 (u_ddr_mc_phy_wrapper_n_816), .\A[1]_25 (u_ddr_mc_phy_wrapper_n_808), .\A[1]_26 (u_ddr_mc_phy_wrapper_n_800), .\A[1]_27 (u_ddr_mc_phy_wrapper_n_792), .\A[1]_28 (u_ddr_mc_phy_wrapper_n_784), .\A[1]_29 (u_ddr_mc_phy_wrapper_n_776), .\A[1]_3 (u_ddr_mc_phy_wrapper_n_789), .\A[1]_30 (u_ddr_mc_phy_wrapper_n_768), .\A[1]_31 (u_ddr_mc_phy_wrapper_n_760), .\A[1]_32 (u_ddr_mc_phy_wrapper_n_817), .\A[1]_33 (u_ddr_mc_phy_wrapper_n_809), .\A[1]_34 (u_ddr_mc_phy_wrapper_n_801), .\A[1]_35 (u_ddr_mc_phy_wrapper_n_793), .\A[1]_36 (u_ddr_mc_phy_wrapper_n_785), .\A[1]_37 (u_ddr_mc_phy_wrapper_n_777), .\A[1]_38 (u_ddr_mc_phy_wrapper_n_769), .\A[1]_39 (u_ddr_mc_phy_wrapper_n_761), .\A[1]_4 (u_ddr_mc_phy_wrapper_n_781), .\A[1]_40 (u_ddr_mc_phy_wrapper_n_818), .\A[1]_41 (u_ddr_mc_phy_wrapper_n_810), .\A[1]_42 (u_ddr_mc_phy_wrapper_n_802), .\A[1]_43 (u_ddr_mc_phy_wrapper_n_794), .\A[1]_44 (u_ddr_mc_phy_wrapper_n_786), .\A[1]_45 (u_ddr_mc_phy_wrapper_n_778), .\A[1]_46 (u_ddr_mc_phy_wrapper_n_770), .\A[1]_47 (u_ddr_mc_phy_wrapper_n_762), .\A[1]_48 (u_ddr_mc_phy_wrapper_n_819), .\A[1]_49 (u_ddr_mc_phy_wrapper_n_811), .\A[1]_5 (u_ddr_mc_phy_wrapper_n_773), .\A[1]_50 (u_ddr_mc_phy_wrapper_n_803), .\A[1]_51 (u_ddr_mc_phy_wrapper_n_795), .\A[1]_52 (u_ddr_mc_phy_wrapper_n_787), .\A[1]_53 (u_ddr_mc_phy_wrapper_n_779), .\A[1]_54 (u_ddr_mc_phy_wrapper_n_771), .\A[1]_55 (u_ddr_mc_phy_wrapper_n_763), .\A[1]_56 (u_ddr_mc_phy_wrapper_n_820), .\A[1]_57 (u_ddr_mc_phy_wrapper_n_812), .\A[1]_58 (u_ddr_mc_phy_wrapper_n_804), .\A[1]_59 (u_ddr_mc_phy_wrapper_n_796), .\A[1]_6 (u_ddr_mc_phy_wrapper_n_765), .\A[1]_60 (u_ddr_mc_phy_wrapper_n_788), .\A[1]_61 (u_ddr_mc_phy_wrapper_n_780), .\A[1]_62 (u_ddr_mc_phy_wrapper_n_772), .\A[1]_63 (u_ddr_mc_phy_wrapper_n_764), .\A[1]_7 (u_ddr_mc_phy_wrapper_n_757), .\A[1]_8 (u_ddr_mc_phy_wrapper_n_814), .\A[1]_9 (u_ddr_mc_phy_wrapper_n_806), .\A[1]__0 (u_ddr_calib_top_n_883), .\A[1]__3 (u_ddr_calib_top_n_885), .\A[1]__4 (u_ddr_calib_top_n_464), .\A[1]__4_0 (u_ddr_calib_top_n_884), .\A[2]__1 (u_ddr_calib_top_n_886), .\A[2]__2 (u_ddr_calib_top_n_882), .\A[2]__2_0 (u_ddr_mc_phy_wrapper_n_30), .A_1__s_port_(u_ddr_calib_top_n_461), .A_rst_primitives_reg(u_ddr_mc_phy_wrapper_n_756), .CLK(CLK), .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}), .D({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }), .D0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ), .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .D2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ), .D_po_coarse_enable110_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ), .D_po_counter_read_en122_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ), .D_po_fine_enable107_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ), .D_po_fine_inc113_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ), .D_po_sel_fine_oclk_delay125_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ), .E(\resume_wait_r_reg[5] ), .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ), .LD0_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ), .LD0_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ), .LD0_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ), .Q(Q), .SR(SR), .SS(SS), .app_zq_r_reg(app_zq_r_reg), .\byte_r_reg[0] (u_ddr_calib_top_n_809), .\byte_r_reg[0]_0 ({\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }), .\byte_r_reg[1] (u_ddr_calib_top_n_810), .\byte_sel_data_map_reg[1] (u_ddr_calib_top_n_879), .\cmd_pipe_plus.mc_address_reg[44] ({\cmd_pipe_plus.mc_address_reg[44] [37],\cmd_pipe_plus.mc_address_reg[44] [35:14],\cmd_pipe_plus.mc_address_reg[44] [12:0]}), .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1] ), .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2] ), .\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ), .\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4] ), .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ), .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0] ), .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_reg[0]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1] ), .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_reg[1]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2] ), .\cmd_pipe_plus.mc_data_offset_reg[2]_0 (\cmd_pipe_plus.mc_data_offset_reg[2]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3] ), .\cmd_pipe_plus.mc_data_offset_reg[3]_0 (\cmd_pipe_plus.mc_data_offset_reg[3]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4] ), .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_reg[4]_0 ), .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ), .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_reg[5]_0 ), .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0), .\complex_row_cnt_ocal_reg[0] (\complex_row_cnt_ocal_reg[0] ), .\data_offset_1_i1_reg[5] (mux_data_offset_1), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (u_ddr_calib_top_n_405), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (u_ddr_calib_top_n_415), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (u_ddr_calib_top_n_425), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (u_ddr_calib_top_n_449), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_1127), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (u_ddr_mc_phy_wrapper_n_104), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\not_strict_mode.app_rd_data_reg[6] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\not_strict_mode.app_rd_data_reg[14] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\not_strict_mode.app_rd_data_reg[22] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\not_strict_mode.app_rd_data_reg[29] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\not_strict_mode.app_rd_data_reg[5] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\not_strict_mode.app_rd_data_reg[13] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\not_strict_mode.app_rd_data_reg[21] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\not_strict_mode.app_rd_data_reg[28] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\not_strict_mode.app_rd_data_reg[4] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\not_strict_mode.app_rd_data_reg[12] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\not_strict_mode.app_rd_data_reg[20] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\not_strict_mode.app_rd_data_reg[27] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\not_strict_mode.app_rd_data_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\not_strict_mode.app_rd_data_reg[11] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\not_strict_mode.app_rd_data_reg[19] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\not_strict_mode.app_rd_data_reg[26] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\not_strict_mode.app_rd_data_reg[2] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\not_strict_mode.app_rd_data_reg[10] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\not_strict_mode.app_rd_data_reg[18] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\not_strict_mode.app_rd_data_reg[25] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\not_strict_mode.app_rd_data_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\not_strict_mode.app_rd_data_reg[9] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\not_strict_mode.app_rd_data_reg[17] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\not_strict_mode.app_rd_data_reg[24] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\not_strict_mode.app_rd_data_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\not_strict_mode.app_rd_data_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\not_strict_mode.app_rd_data_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\not_strict_mode.app_rd_data_reg[30] ), .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .fine_adjust_reg(fine_adjust_reg), .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}), .\fine_delay_mod_reg[20] (u_ddr_calib_top_n_845), .\fine_delay_mod_reg[26] (u_ddr_calib_top_n_859), .\fine_delay_mod_reg[5] (u_ddr_calib_top_n_844), .\fine_delay_r_reg[26] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}), .\fine_delay_r_reg[26]_0 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}), .\fine_delay_r_reg[26]_1 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}), .\fine_delay_r_reg[2] (u_ddr_calib_top_n_448), .\fine_delay_r_reg[5] (u_ddr_calib_top_n_404), .\fine_delay_r_reg[5]_0 (u_ddr_calib_top_n_414), .\fine_delay_r_reg[5]_1 (u_ddr_calib_top_n_424), .fine_delay_sel_r(fine_delay_sel_r), .fine_delay_sel_r_reg(u_ddr_calib_top_n_50), .\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (byte_sel_cnt), .\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_860), .\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_861), .\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_862), .\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_863), .\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_864), .\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_865), .idelay_inc(idelay_inc), .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_5(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ), .\idelay_tap_cnt_r_reg[0][3][0] (po_stg2_wrcal_cnt), .ififo_rst_reg(u_ddr_calib_top_n_409), .ififo_rst_reg_0(u_ddr_calib_top_n_419), .ififo_rst_reg_1(u_ddr_calib_top_n_429), .ififo_rst_reg_2(u_ddr_calib_top_n_453), .in0({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}), .init_calib_complete_r_reg(init_calib_complete_r_reg), .maint_prescaler_r1(maint_prescaler_r1), .\mcGo_r_reg[15] (\calib_seq_reg[0] ), .mc_cas_n(mc_cas_n), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_cs_n(mc_cs_n), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n), .mc_we_n(mc_we_n), .mc_wrdata_en(mc_wrdata_en), .mem_out({mem_out[10:8],mem_out[2:0]}), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mux_cmd_wren(mux_cmd_wren), .mux_reset_n(mux_reset_n), .mux_wrdata_en(mux_wrdata_en), .my_empty(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .my_empty_6(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .my_empty_7(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .my_empty_8(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ), .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_61), .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_60), .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63), .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_102), .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_67), .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66), .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_65), .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_64), .\my_empty_reg[7] (u_ddr_calib_top_n_37), .\my_empty_reg[7]_0 (\my_empty_reg[7] ), .\my_empty_reg[7]_1 ({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}), .\my_empty_reg[7]_10 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\my_empty_reg[7]_11 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\my_empty_reg[7]_12 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\my_empty_reg[7]_13 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\my_empty_reg[7]_14 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\my_empty_reg[7]_15 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\my_empty_reg[7]_16 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .\my_empty_reg[7]_17 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\my_empty_reg[7]_18 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\my_empty_reg[7]_19 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\my_empty_reg[7]_2 ({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}), .\my_empty_reg[7]_20 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .\my_empty_reg[7]_21 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .\my_empty_reg[7]_22 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\my_empty_reg[7]_23 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\my_empty_reg[7]_24 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\my_empty_reg[7]_25 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .\my_empty_reg[7]_26 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .\my_empty_reg[7]_27 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ), .\my_empty_reg[7]_28 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ), .\my_empty_reg[7]_29 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ), .\my_empty_reg[7]_3 ({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}), .\my_empty_reg[7]_30 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .\my_empty_reg[7]_31 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .\my_empty_reg[7]_32 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .\my_empty_reg[7]_33 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ), .\my_empty_reg[7]_34 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ), .\my_empty_reg[7]_35 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ), .\my_empty_reg[7]_36 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ), .\my_empty_reg[7]_37 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ), .\my_empty_reg[7]_38 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ), .\my_empty_reg[7]_39 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ), .\my_empty_reg[7]_4 ({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}), .\my_empty_reg[7]_40 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ), .\my_empty_reg[7]_41 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ), .\my_empty_reg[7]_42 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .\my_empty_reg[7]_43 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ), .\my_empty_reg[7]_5 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\my_empty_reg[7]_6 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\my_empty_reg[7]_7 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\my_empty_reg[7]_8 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\my_empty_reg[7]_9 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\my_full_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .\my_full_reg[3]_0 (phy_dout[3:2]), .out(u_ddr_calib_top_n_45), .p_0_out(\u_ddr_phy_wrcal/p_0_out ), .p_81_in(p_81_in), .pd_out(pd_out), .\phy_ctl_wd_i1_reg[24] ({calib_seq,p_1_out[22:17],p_1_out[2:0]}), .phy_dout({phy_dout[1:0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}), .phy_if_reset(phy_if_reset), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .pi_cnt_dec_reg(pi_cnt_dec_reg), .\pi_counter_read_val_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ), .\pi_dqs_found_lanes_r1_reg[0] (u_ddr_calib_top_n_447), .\pi_dqs_found_lanes_r1_reg[0]_0 (u_ddr_calib_top_n_454), .\pi_dqs_found_lanes_r1_reg[0]_1 (u_ddr_calib_top_n_455), .\pi_dqs_found_lanes_r1_reg[0]_2 (u_ddr_calib_top_n_456), .\pi_dqs_found_lanes_r1_reg[1] (u_ddr_calib_top_n_423), .\pi_dqs_found_lanes_r1_reg[1]_0 (u_ddr_calib_top_n_430), .\pi_dqs_found_lanes_r1_reg[1]_1 (u_ddr_calib_top_n_431), .\pi_dqs_found_lanes_r1_reg[1]_2 (u_ddr_calib_top_n_432), .\pi_dqs_found_lanes_r1_reg[1]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ), .\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_413), .\pi_dqs_found_lanes_r1_reg[2]_0 (u_ddr_calib_top_n_420), .\pi_dqs_found_lanes_r1_reg[2]_1 (u_ddr_calib_top_n_421), .\pi_dqs_found_lanes_r1_reg[2]_2 (u_ddr_calib_top_n_422), .\pi_dqs_found_lanes_r1_reg[2]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ), .\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_403), .\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_calib_top_n_410), .\pi_dqs_found_lanes_r1_reg[3]_1 (u_ddr_calib_top_n_411), .\pi_dqs_found_lanes_r1_reg[3]_2 (u_ddr_calib_top_n_412), .\pi_dqs_found_lanes_r1_reg[3]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ), .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg), .\pi_rst_stg1_cal_r_reg[0] (\pi_rst_stg1_cal_r_reg[0] ), .po_cnt_dec_reg(po_cnt_dec_reg), .\po_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_106), .\po_counter_read_val_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}), .\po_counter_read_val_reg[8] (u_ddr_calib_top_n_385), .\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_386), .\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_387), .\po_counter_read_val_reg[8]_10 (u_ddr_calib_top_n_396), .\po_counter_read_val_reg[8]_11 (u_ddr_calib_top_n_397), .\po_counter_read_val_reg[8]_12 (u_ddr_calib_top_n_399), .\po_counter_read_val_reg[8]_13 (u_ddr_calib_top_n_400), .\po_counter_read_val_reg[8]_14 (u_ddr_calib_top_n_401), .\po_counter_read_val_reg[8]_15 (u_ddr_calib_top_n_402), .\po_counter_read_val_reg[8]_16 (u_ddr_calib_top_n_406), .\po_counter_read_val_reg[8]_17 (u_ddr_calib_top_n_407), .\po_counter_read_val_reg[8]_18 (u_ddr_calib_top_n_408), .\po_counter_read_val_reg[8]_19 (u_ddr_calib_top_n_416), .\po_counter_read_val_reg[8]_2 (u_ddr_calib_top_n_388), .\po_counter_read_val_reg[8]_20 (u_ddr_calib_top_n_417), .\po_counter_read_val_reg[8]_21 (u_ddr_calib_top_n_418), .\po_counter_read_val_reg[8]_22 (u_ddr_calib_top_n_426), .\po_counter_read_val_reg[8]_23 (u_ddr_calib_top_n_427), .\po_counter_read_val_reg[8]_24 (u_ddr_calib_top_n_428), .\po_counter_read_val_reg[8]_25 (u_ddr_calib_top_n_450), .\po_counter_read_val_reg[8]_26 (u_ddr_calib_top_n_451), .\po_counter_read_val_reg[8]_27 (u_ddr_calib_top_n_452), .\po_counter_read_val_reg[8]_28 (u_ddr_calib_top_n_457), .\po_counter_read_val_reg[8]_29 (u_ddr_calib_top_n_458), .\po_counter_read_val_reg[8]_3 (u_ddr_calib_top_n_389), .\po_counter_read_val_reg[8]_30 ({\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}), .\po_counter_read_val_reg[8]_31 ({\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}), .\po_counter_read_val_reg[8]_4 (u_ddr_calib_top_n_390), .\po_counter_read_val_reg[8]_5 (u_ddr_calib_top_n_391), .\po_counter_read_val_reg[8]_6 (u_ddr_calib_top_n_392), .\po_counter_read_val_reg[8]_7 (u_ddr_calib_top_n_393), .\po_counter_read_val_reg[8]_8 (u_ddr_calib_top_n_394), .\po_counter_read_val_reg[8]_9 (u_ddr_calib_top_n_395), .\po_rdval_cnt_reg[8] ({calib_sel__0,calib_sel}), .\po_stg2_wrcal_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_1152), .\po_stg2_wrcal_cnt_reg[1]_0 (u_ddr_mc_phy_wrapper_n_1156), .\po_stg2_wrcal_cnt_reg[1]_1 (u_ddr_mc_phy_wrapper_n_1171), .\po_stg2_wrcal_cnt_reg[1]_10 (u_ddr_mc_phy_wrapper_n_1136), .\po_stg2_wrcal_cnt_reg[1]_11 (u_ddr_mc_phy_wrapper_n_1137), .\po_stg2_wrcal_cnt_reg[1]_12 (u_ddr_mc_phy_wrapper_n_1138), .\po_stg2_wrcal_cnt_reg[1]_13 (u_ddr_mc_phy_wrapper_n_1139), .\po_stg2_wrcal_cnt_reg[1]_14 (u_ddr_mc_phy_wrapper_n_1140), .\po_stg2_wrcal_cnt_reg[1]_15 (u_ddr_mc_phy_wrapper_n_1141), .\po_stg2_wrcal_cnt_reg[1]_16 (u_ddr_mc_phy_wrapper_n_1142), .\po_stg2_wrcal_cnt_reg[1]_17 (u_ddr_mc_phy_wrapper_n_1143), .\po_stg2_wrcal_cnt_reg[1]_18 (u_ddr_mc_phy_wrapper_n_1144), .\po_stg2_wrcal_cnt_reg[1]_19 (u_ddr_mc_phy_wrapper_n_1145), .\po_stg2_wrcal_cnt_reg[1]_2 (u_ddr_mc_phy_wrapper_n_1175), .\po_stg2_wrcal_cnt_reg[1]_20 (u_ddr_mc_phy_wrapper_n_1146), .\po_stg2_wrcal_cnt_reg[1]_21 (u_ddr_mc_phy_wrapper_n_1147), .\po_stg2_wrcal_cnt_reg[1]_22 (u_ddr_mc_phy_wrapper_n_1148), .\po_stg2_wrcal_cnt_reg[1]_23 (u_ddr_mc_phy_wrapper_n_1149), .\po_stg2_wrcal_cnt_reg[1]_24 (u_ddr_mc_phy_wrapper_n_1150), .\po_stg2_wrcal_cnt_reg[1]_25 (u_ddr_mc_phy_wrapper_n_1151), .\po_stg2_wrcal_cnt_reg[1]_26 (u_ddr_mc_phy_wrapper_n_1153), .\po_stg2_wrcal_cnt_reg[1]_27 (u_ddr_mc_phy_wrapper_n_1154), .\po_stg2_wrcal_cnt_reg[1]_28 (u_ddr_mc_phy_wrapper_n_1155), .\po_stg2_wrcal_cnt_reg[1]_29 (u_ddr_mc_phy_wrapper_n_1157), .\po_stg2_wrcal_cnt_reg[1]_3 (u_ddr_mc_phy_wrapper_n_1129), .\po_stg2_wrcal_cnt_reg[1]_30 (u_ddr_mc_phy_wrapper_n_1158), .\po_stg2_wrcal_cnt_reg[1]_31 (u_ddr_mc_phy_wrapper_n_1159), .\po_stg2_wrcal_cnt_reg[1]_32 (u_ddr_mc_phy_wrapper_n_1160), .\po_stg2_wrcal_cnt_reg[1]_33 (u_ddr_mc_phy_wrapper_n_1161), .\po_stg2_wrcal_cnt_reg[1]_34 (u_ddr_mc_phy_wrapper_n_1162), .\po_stg2_wrcal_cnt_reg[1]_35 (u_ddr_mc_phy_wrapper_n_1163), .\po_stg2_wrcal_cnt_reg[1]_36 (u_ddr_mc_phy_wrapper_n_1164), .\po_stg2_wrcal_cnt_reg[1]_37 (u_ddr_mc_phy_wrapper_n_1165), .\po_stg2_wrcal_cnt_reg[1]_38 (u_ddr_mc_phy_wrapper_n_1166), .\po_stg2_wrcal_cnt_reg[1]_39 (u_ddr_mc_phy_wrapper_n_1167), .\po_stg2_wrcal_cnt_reg[1]_4 (u_ddr_mc_phy_wrapper_n_1130), .\po_stg2_wrcal_cnt_reg[1]_40 (u_ddr_mc_phy_wrapper_n_1168), .\po_stg2_wrcal_cnt_reg[1]_41 (u_ddr_mc_phy_wrapper_n_1169), .\po_stg2_wrcal_cnt_reg[1]_42 (u_ddr_mc_phy_wrapper_n_1170), .\po_stg2_wrcal_cnt_reg[1]_43 (u_ddr_mc_phy_wrapper_n_1172), .\po_stg2_wrcal_cnt_reg[1]_44 (u_ddr_mc_phy_wrapper_n_1173), .\po_stg2_wrcal_cnt_reg[1]_45 (u_ddr_mc_phy_wrapper_n_1174), .\po_stg2_wrcal_cnt_reg[1]_46 (u_ddr_mc_phy_wrapper_n_1176), .\po_stg2_wrcal_cnt_reg[1]_47 (u_ddr_mc_phy_wrapper_n_1177), .\po_stg2_wrcal_cnt_reg[1]_48 (u_ddr_mc_phy_wrapper_n_1178), .\po_stg2_wrcal_cnt_reg[1]_49 (u_ddr_mc_phy_wrapper_n_1179), .\po_stg2_wrcal_cnt_reg[1]_5 (u_ddr_mc_phy_wrapper_n_1131), .\po_stg2_wrcal_cnt_reg[1]_50 (u_ddr_mc_phy_wrapper_n_1180), .\po_stg2_wrcal_cnt_reg[1]_51 (u_ddr_mc_phy_wrapper_n_1181), .\po_stg2_wrcal_cnt_reg[1]_52 (u_ddr_mc_phy_wrapper_n_1182), .\po_stg2_wrcal_cnt_reg[1]_53 (u_ddr_mc_phy_wrapper_n_1183), .\po_stg2_wrcal_cnt_reg[1]_54 (u_ddr_mc_phy_wrapper_n_1184), .\po_stg2_wrcal_cnt_reg[1]_55 (u_ddr_mc_phy_wrapper_n_1185), .\po_stg2_wrcal_cnt_reg[1]_56 (u_ddr_mc_phy_wrapper_n_1186), .\po_stg2_wrcal_cnt_reg[1]_57 (u_ddr_mc_phy_wrapper_n_1187), .\po_stg2_wrcal_cnt_reg[1]_58 (u_ddr_mc_phy_wrapper_n_1188), .\po_stg2_wrcal_cnt_reg[1]_59 (u_ddr_mc_phy_wrapper_n_1189), .\po_stg2_wrcal_cnt_reg[1]_6 (u_ddr_mc_phy_wrapper_n_1132), .\po_stg2_wrcal_cnt_reg[1]_60 (u_ddr_mc_phy_wrapper_n_1190), .\po_stg2_wrcal_cnt_reg[1]_61 (u_ddr_mc_phy_wrapper_n_1191), .\po_stg2_wrcal_cnt_reg[1]_7 (u_ddr_mc_phy_wrapper_n_1133), .\po_stg2_wrcal_cnt_reg[1]_8 (u_ddr_mc_phy_wrapper_n_1134), .\po_stg2_wrcal_cnt_reg[1]_9 (u_ddr_mc_phy_wrapper_n_1135), .poc_sample_pd(poc_sample_pd), .prbs_rdlvl_start_r_reg(u_ddr_calib_top_n_47), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .\rd_mux_sel_r_reg[1] (u_ddr_mc_phy_wrapper_n_490), .\rd_mux_sel_r_reg[1]_0 (u_ddr_mc_phy_wrapper_n_482), .\rd_mux_sel_r_reg[1]_1 (u_ddr_mc_phy_wrapper_n_474), .\rd_mux_sel_r_reg[1]_10 (u_ddr_mc_phy_wrapper_n_467), .\rd_mux_sel_r_reg[1]_11 (u_ddr_mc_phy_wrapper_n_459), .\rd_mux_sel_r_reg[1]_12 (u_ddr_mc_phy_wrapper_n_451), .\rd_mux_sel_r_reg[1]_13 (u_ddr_mc_phy_wrapper_n_443), .\rd_mux_sel_r_reg[1]_14 (u_ddr_mc_phy_wrapper_n_435), .\rd_mux_sel_r_reg[1]_15 (u_ddr_mc_phy_wrapper_n_492), .\rd_mux_sel_r_reg[1]_16 (u_ddr_mc_phy_wrapper_n_484), .\rd_mux_sel_r_reg[1]_17 (u_ddr_mc_phy_wrapper_n_476), .\rd_mux_sel_r_reg[1]_18 (u_ddr_mc_phy_wrapper_n_468), .\rd_mux_sel_r_reg[1]_19 (u_ddr_mc_phy_wrapper_n_460), .\rd_mux_sel_r_reg[1]_2 (u_ddr_mc_phy_wrapper_n_466), .\rd_mux_sel_r_reg[1]_20 (u_ddr_mc_phy_wrapper_n_452), .\rd_mux_sel_r_reg[1]_21 (u_ddr_mc_phy_wrapper_n_444), .\rd_mux_sel_r_reg[1]_22 (u_ddr_mc_phy_wrapper_n_436), .\rd_mux_sel_r_reg[1]_23 (u_ddr_mc_phy_wrapper_n_493), .\rd_mux_sel_r_reg[1]_24 (u_ddr_mc_phy_wrapper_n_485), .\rd_mux_sel_r_reg[1]_25 (u_ddr_mc_phy_wrapper_n_477), .\rd_mux_sel_r_reg[1]_26 (u_ddr_mc_phy_wrapper_n_469), .\rd_mux_sel_r_reg[1]_27 (u_ddr_mc_phy_wrapper_n_461), .\rd_mux_sel_r_reg[1]_28 (u_ddr_mc_phy_wrapper_n_453), .\rd_mux_sel_r_reg[1]_29 (u_ddr_mc_phy_wrapper_n_445), .\rd_mux_sel_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_458), .\rd_mux_sel_r_reg[1]_30 (u_ddr_mc_phy_wrapper_n_437), .\rd_mux_sel_r_reg[1]_31 (u_ddr_mc_phy_wrapper_n_494), .\rd_mux_sel_r_reg[1]_32 (u_ddr_mc_phy_wrapper_n_486), .\rd_mux_sel_r_reg[1]_33 (u_ddr_mc_phy_wrapper_n_478), .\rd_mux_sel_r_reg[1]_34 (u_ddr_mc_phy_wrapper_n_470), .\rd_mux_sel_r_reg[1]_35 (u_ddr_mc_phy_wrapper_n_462), .\rd_mux_sel_r_reg[1]_36 (u_ddr_mc_phy_wrapper_n_454), .\rd_mux_sel_r_reg[1]_37 (u_ddr_mc_phy_wrapper_n_446), .\rd_mux_sel_r_reg[1]_38 (u_ddr_mc_phy_wrapper_n_438), .\rd_mux_sel_r_reg[1]_39 (u_ddr_mc_phy_wrapper_n_495), .\rd_mux_sel_r_reg[1]_4 (u_ddr_mc_phy_wrapper_n_450), .\rd_mux_sel_r_reg[1]_40 (u_ddr_mc_phy_wrapper_n_487), .\rd_mux_sel_r_reg[1]_41 (u_ddr_mc_phy_wrapper_n_479), .\rd_mux_sel_r_reg[1]_42 (u_ddr_mc_phy_wrapper_n_471), .\rd_mux_sel_r_reg[1]_43 (u_ddr_mc_phy_wrapper_n_463), .\rd_mux_sel_r_reg[1]_44 (u_ddr_mc_phy_wrapper_n_455), .\rd_mux_sel_r_reg[1]_45 (u_ddr_mc_phy_wrapper_n_447), .\rd_mux_sel_r_reg[1]_46 (u_ddr_mc_phy_wrapper_n_439), .\rd_mux_sel_r_reg[1]_47 (u_ddr_mc_phy_wrapper_n_496), .\rd_mux_sel_r_reg[1]_48 (u_ddr_mc_phy_wrapper_n_488), .\rd_mux_sel_r_reg[1]_49 (u_ddr_mc_phy_wrapper_n_480), .\rd_mux_sel_r_reg[1]_5 (u_ddr_mc_phy_wrapper_n_442), .\rd_mux_sel_r_reg[1]_50 (u_ddr_mc_phy_wrapper_n_472), .\rd_mux_sel_r_reg[1]_51 (u_ddr_mc_phy_wrapper_n_464), .\rd_mux_sel_r_reg[1]_52 (u_ddr_mc_phy_wrapper_n_456), .\rd_mux_sel_r_reg[1]_53 (u_ddr_mc_phy_wrapper_n_448), .\rd_mux_sel_r_reg[1]_54 (u_ddr_mc_phy_wrapper_n_440), .\rd_mux_sel_r_reg[1]_55 (u_ddr_mc_phy_wrapper_n_497), .\rd_mux_sel_r_reg[1]_56 (u_ddr_mc_phy_wrapper_n_489), .\rd_mux_sel_r_reg[1]_57 (u_ddr_mc_phy_wrapper_n_481), .\rd_mux_sel_r_reg[1]_58 (u_ddr_mc_phy_wrapper_n_473), .\rd_mux_sel_r_reg[1]_59 (u_ddr_mc_phy_wrapper_n_465), .\rd_mux_sel_r_reg[1]_6 (u_ddr_mc_phy_wrapper_n_434), .\rd_mux_sel_r_reg[1]_60 (u_ddr_mc_phy_wrapper_n_457), .\rd_mux_sel_r_reg[1]_61 (u_ddr_mc_phy_wrapper_n_449), .\rd_mux_sel_r_reg[1]_62 (u_ddr_mc_phy_wrapper_n_441), .\rd_mux_sel_r_reg[1]_7 (u_ddr_mc_phy_wrapper_n_491), .\rd_mux_sel_r_reg[1]_8 (u_ddr_mc_phy_wrapper_n_483), .\rd_mux_sel_r_reg[1]_9 (u_ddr_mc_phy_wrapper_n_475), .\rd_ptr_reg[3] ({\rd_ptr_reg[3] [69:66],\rd_ptr_reg[3] [61:58],\rd_ptr_reg[3] [53:34],\rd_ptr_reg[3] [29:26],\rd_ptr_reg[3] [20:18],\rd_ptr_reg[3] [12:10]}), .\rd_ptr_reg[3]_0 ({\rd_ptr_reg[3]_0 [25:22],\rd_ptr_reg[3]_0 [17:14],\rd_ptr_reg[3]_0 [11:8]}), .\rd_ptr_reg[3]_1 ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}), .\rd_ptr_reg[3]_2 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}), .\rd_ptr_reg[3]_3 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}), .\rd_ptr_reg[3]_4 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}), .\rd_ptr_reg[3]_5 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}), .\rd_ptr_timing_reg[0] (u_ddr_calib_top_n_38), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0] ), .\rd_ptr_timing_reg[0]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\rd_ptr_timing_reg[0]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\rd_ptr_timing_reg[0]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\rd_ptr_timing_reg[0]_4 (\rd_ptr_timing_reg[0]_0 ), .\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ({u_ddr_calib_top_n_837,u_ddr_calib_top_n_838}), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .rstdiv0_sync_r1_reg_rep(in0), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0), .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0), .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1), .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg), .\samps_r_reg[9] (\samps_r_reg[9] ), .sent_col(sent_col), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .tempmon_sample_en(tempmon_sample_en), .\zero2fuzz_r_reg[0] (D)); ddr3_if_mig_7series_v4_0_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper (.A(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ), .CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}), .D({calib_seq,p_1_out[22:17],p_1_out[2:0]}), .D0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ), .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .D2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ), .DOA(DOA), .DOB(DOB), .DOC(DOC), .D_po_coarse_enable110_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ), .D_po_counter_read_en122_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ), .D_po_fine_enable107_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ), .D_po_fine_inc113_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ), .D_po_sel_fine_oclk_delay125_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ), .E(u_ddr_calib_top_n_448), .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ), .LD0_3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ), .LD0_4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ), .LD0_5(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ), .Q(Q[287:256]), .RST0(RST0), .SR(SR), .\byte_r_reg[0] (u_ddr_mc_phy_wrapper_n_106), .\byte_r_reg[0]_0 (u_ddr_calib_top_n_809), .\byte_r_reg[1] (u_ddr_calib_top_n_810), .\calib_sel_reg[0] (u_ddr_calib_top_n_390), .\calib_sel_reg[0]_0 (u_ddr_calib_top_n_395), .\calib_sel_reg[0]_1 (u_ddr_calib_top_n_396), .\calib_sel_reg[0]_2 (u_ddr_calib_top_n_397), .\calib_sel_reg[0]_3 (u_ddr_calib_top_n_447), .\calib_sel_reg[0]_4 (u_ddr_calib_top_n_423), .\calib_sel_reg[0]_5 (u_ddr_calib_top_n_403), .\calib_sel_reg[0]_6 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}), .\calib_sel_reg[0]_7 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}), .\calib_sel_reg[1] (u_ddr_calib_top_n_386), .\calib_sel_reg[1]_0 (u_ddr_calib_top_n_387), .\calib_sel_reg[1]_1 (u_ddr_calib_top_n_388), .\calib_sel_reg[1]_2 (u_ddr_calib_top_n_389), .\calib_sel_reg[1]_3 (u_ddr_calib_top_n_391), .\calib_sel_reg[1]_4 (u_ddr_calib_top_n_392), .\calib_sel_reg[1]_5 (u_ddr_calib_top_n_393), .\calib_sel_reg[1]_6 (u_ddr_calib_top_n_394), .\calib_sel_reg[1]_7 (u_ddr_calib_top_n_413), .\calib_sel_reg[1]_8 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}), .\calib_sel_reg[3] ({calib_sel__0,calib_sel}), .\calib_seq_reg[0] (\calib_seq_reg[0] ), .\calib_zero_inputs_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ), .\calib_zero_inputs_reg[0]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ), .\calib_zero_inputs_reg[0]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ), .ck_po_stg2_f_en_reg(u_ddr_calib_top_n_451), .ck_po_stg2_f_en_reg_0(u_ddr_calib_top_n_427), .ck_po_stg2_f_en_reg_1(u_ddr_calib_top_n_417), .ck_po_stg2_f_en_reg_2(u_ddr_calib_top_n_407), .ck_po_stg2_f_indec_reg(u_ddr_calib_top_n_450), .ck_po_stg2_f_indec_reg_0(u_ddr_calib_top_n_426), .ck_po_stg2_f_indec_reg_1(u_ddr_calib_top_n_416), .ck_po_stg2_f_indec_reg_2(u_ddr_calib_top_n_406), .\cmd_pipe_plus.mc_address_reg[43] ({\cmd_pipe_plus.mc_address_reg[44] [36],\cmd_pipe_plus.mc_address_reg[44] [13]}), .\cmd_pipe_plus.mc_data_offset_1_reg[5] (mux_data_offset_1), .\data_bytes_r_reg[63] ({\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .delay_done_r4_reg(u_ddr_calib_top_n_400), .delay_done_r4_reg_0(u_ddr_calib_top_n_401), .delay_done_r4_reg_1(u_ddr_calib_top_n_399), .delay_done_r4_reg_2(u_ddr_calib_top_n_402), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}), .\fine_delay_mod_reg[23]_0 ({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }), .\fine_delay_mod_reg[26]_0 (u_ddr_mc_phy_wrapper_n_30), .fine_delay_sel_r(fine_delay_sel_r), .fine_delay_sel_reg(u_ddr_calib_top_n_50), .freq_refclk(freq_refclk), .\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_calib_top_n_882), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (u_ddr_calib_top_n_881), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 (u_ddr_calib_top_n_880), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 (u_ddr_calib_top_n_883), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 (u_ddr_calib_top_n_885), .\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 (u_ddr_calib_top_n_884), .\gen_byte_sel_div1.byte_sel_cnt_reg[1] (byte_sel_cnt), .\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_calib_top_n_464), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (u_ddr_calib_top_n_461), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 (u_ddr_calib_top_n_886), .\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 (u_ddr_calib_top_n_879), .\gen_byte_sel_div1.calib_in_common_reg (u_ddr_calib_top_n_457), .\gen_byte_sel_div1.calib_in_common_reg_0 (u_ddr_calib_top_n_385), .\gen_byte_sel_div1.calib_in_common_reg_1 (u_ddr_calib_top_n_458), .\gen_byte_sel_div1.calib_in_common_reg_10 (u_ddr_calib_top_n_422), .\gen_byte_sel_div1.calib_in_common_reg_11 (u_ddr_calib_top_n_419), .\gen_byte_sel_div1.calib_in_common_reg_12 (u_ddr_calib_top_n_418), .\gen_byte_sel_div1.calib_in_common_reg_13 (u_ddr_calib_top_n_415), .\gen_byte_sel_div1.calib_in_common_reg_14 (u_ddr_calib_top_n_412), .\gen_byte_sel_div1.calib_in_common_reg_15 (u_ddr_calib_top_n_409), .\gen_byte_sel_div1.calib_in_common_reg_16 (u_ddr_calib_top_n_408), .\gen_byte_sel_div1.calib_in_common_reg_17 (u_ddr_calib_top_n_405), .\gen_byte_sel_div1.calib_in_common_reg_18 (u_ddr_calib_top_n_424), .\gen_byte_sel_div1.calib_in_common_reg_19 (u_ddr_calib_top_n_414), .\gen_byte_sel_div1.calib_in_common_reg_2 (u_ddr_calib_top_n_456), .\gen_byte_sel_div1.calib_in_common_reg_20 (u_ddr_calib_top_n_404), .\gen_byte_sel_div1.calib_in_common_reg_3 (u_ddr_calib_top_n_453), .\gen_byte_sel_div1.calib_in_common_reg_4 (u_ddr_calib_top_n_452), .\gen_byte_sel_div1.calib_in_common_reg_5 (u_ddr_calib_top_n_449), .\gen_byte_sel_div1.calib_in_common_reg_6 (u_ddr_calib_top_n_432), .\gen_byte_sel_div1.calib_in_common_reg_7 (u_ddr_calib_top_n_429), .\gen_byte_sel_div1.calib_in_common_reg_8 (u_ddr_calib_top_n_428), .\gen_byte_sel_div1.calib_in_common_reg_9 (u_ddr_calib_top_n_425), .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_814), .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_491), .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_816), .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_493), .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_818), .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_495), .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_820), .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_497), .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_813), .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_490), .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_815), .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (u_ddr_mc_phy_wrapper_n_492), .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_817), .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_494), .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_819), .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_496), .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_806), .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_483), .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_808), .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_485), .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_810), .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_487), .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_812), .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_489), .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_805), .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_482), .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_807), .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_484), .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_809), .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_486), .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_811), .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_488), .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_798), .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_475), .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_800), .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_477), .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_802), .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_479), .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_804), .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_481), .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_797), .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_474), .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_799), .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_476), .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_801), .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_478), .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_803), .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_480), .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_790), .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_467), .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_792), .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_469), .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_794), .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_471), .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_796), .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_473), .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_789), .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_466), .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_791), .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_468), .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_793), .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_470), .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_795), .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_472), .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_782), .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_459), .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_784), .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_461), .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_786), .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_463), .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_788), .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_465), .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_781), .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_458), .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_783), .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_460), .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_785), .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_462), .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_787), .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_464), .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_774), .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_451), .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_776), .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_453), .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_778), .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_455), .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_780), .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_457), .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_773), .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_450), .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_775), .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_452), .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_777), .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_454), .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_779), .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_456), .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_766), .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_443), .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_768), .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_445), .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_770), .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_447), .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_772), .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_449), .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_765), .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_442), .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_767), .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_444), .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_769), .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_446), .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_771), .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_448), .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_758), .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_435), .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_760), .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_437), .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_762), .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_439), .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_764), .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_441), .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_757), .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_434), .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_759), .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_436), .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_761), .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_438), .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_763), .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_440), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1144), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_1184), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1160), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1136), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1176), .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1168), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1145), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1185), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1161), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1137), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1177), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1129), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1153), .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1169), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1146), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1186), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1162), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1138), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1178), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1130), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1154), .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1170), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1147), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1187), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1163), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1139), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1179), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1131), .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1155), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1148), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1188), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1164), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1140), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1180), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1132), .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1172), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1149), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1189), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1165), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1141), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1181), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1133), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1157), .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1173), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1150), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1190), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1166), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1142), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1182), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1134), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1158), .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1174), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1151), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1191), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1167), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1143), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1183), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1135), .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1159), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1152), .\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1171), .\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1156), .\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1175), .\genblk9[0].fine_delay_incdec_pb_reg[0] (u_ddr_calib_top_n_859), .\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_860), .\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_861), .\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_862), .\genblk9[4].fine_delay_incdec_pb_reg[4] (u_ddr_calib_top_n_844), .\genblk9[4].fine_delay_incdec_pb_reg[4]_0 (u_ddr_calib_top_n_845), .\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_863), .\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_864), .\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_865), .idelay_inc(idelay_inc), .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ), .idelay_ld_rst_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ), .idle(idle), .in0(in0), .init_calib_complete_reg_rep(u_ddr_calib_top_n_37), .init_calib_complete_reg_rep__5(u_ddr_calib_top_n_38), .init_calib_complete_reg_rep__6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .init_calib_complete_reg_rep__6_0(app_zq_r_reg), .mc_cas_n(mc_cas_n[1]), .mem_out({mem_out[17:11],mem_out[7:3]}), .mem_refclk(mem_refclk), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .mux_cmd_wren(mux_cmd_wren), .mux_rd_valid_r_reg(u_ddr_mc_phy_wrapper_n_104), .mux_reset_n(mux_reset_n), .mux_wrdata(mux_wrdata), .mux_wrdata_en(mux_wrdata_en), .mux_wrdata_mask(mux_wrdata_mask), .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_60), .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_61), .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63), .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_64), .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_65), .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66), .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_67), .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_102), .\my_empty_reg[7] ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}), .\my_empty_reg[7]_0 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}), .\my_empty_reg[7]_1 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}), .\my_empty_reg[7]_2 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}), .\my_empty_reg[7]_3 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ), .\not_strict_mode.app_rd_data_reg[15]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), 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.\not_strict_mode.app_rd_data_reg[7]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .of_ctl_full_v(of_ctl_full_v), .ofs_rdy_r_reg(ofs_rdy_r_reg), .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0), .out(u_ddr_calib_top_n_45), .p_0_out(\u_ddr_phy_wrcal/p_0_out ), .pd_out(pd_out), .phy_dout({phy_dout[1],\cmd_pipe_plus.mc_address_reg[43] [1],phy_dout[0],\cmd_pipe_plus.mc_address_reg[43] [0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}), .phy_if_empty_r_reg(u_ddr_mc_phy_wrapper_n_1127), .phy_if_reset(phy_if_reset), .phy_mc_ctl_full(phy_mc_ctl_full), .phy_rddata_en(phy_rddata_en), .phy_read_calib(phy_read_calib), .phy_write_calib(phy_write_calib), .\pi_dqs_found_lanes_r1_reg[3] ({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}), .pi_en_stg2_f_reg(u_ddr_calib_top_n_455), .pi_en_stg2_f_reg_0(u_ddr_calib_top_n_431), .pi_en_stg2_f_reg_1(u_ddr_calib_top_n_421), .pi_en_stg2_f_reg_2(u_ddr_calib_top_n_411), .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_756), .\pi_rdval_cnt_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ), .pi_stg2_f_incdec_reg(u_ddr_calib_top_n_454), .pi_stg2_f_incdec_reg_0(u_ddr_calib_top_n_430), .pi_stg2_f_incdec_reg_1(u_ddr_calib_top_n_420), .pi_stg2_f_incdec_reg_2(u_ddr_calib_top_n_410), .pll_locked(pll_locked), .\po_counter_read_val_r_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}), .\po_rdval_cnt_reg[8] ({\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}), .\po_rdval_cnt_reg[8]_0 ({\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}), .\po_stg2_wrcal_cnt_reg[1] (po_stg2_wrcal_cnt), .prbs_rdlvl_start_reg(u_ddr_calib_top_n_47), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_mux_sel_r_reg[1] ({u_ddr_calib_top_n_837,u_ddr_calib_top_n_838}), .\rd_ptr_reg[3] ({\rd_ptr_reg[3] [71:70],\rd_ptr_reg[3] [65:62],\rd_ptr_reg[3] [57:54],\rd_ptr_reg[3] [33:30],\rd_ptr_reg[3] [25:21],\rd_ptr_reg[3] [17:13],\rd_ptr_reg[3] [9:0]}), .\rd_ptr_reg[3]_0 ({\rd_ptr_reg[3]_0 [29:26],\rd_ptr_reg[3]_0 [21:18],\rd_ptr_reg[3]_0 [13:12],\rd_ptr_reg[3]_0 [7:0]}), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ), .\read_fifo.fifo_out_data_r_reg[6]_0 (\read_fifo.fifo_out_data_r_reg[6]_0 ), .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_1 ), .\write_buffer.wr_buf_out_data_reg[224] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ), .\write_buffer.wr_buf_out_data_reg[225] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ), .\write_buffer.wr_buf_out_data_reg[226] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ), .\write_buffer.wr_buf_out_data_reg[227] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ), .\write_buffer.wr_buf_out_data_reg[228] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ), .\write_buffer.wr_buf_out_data_reg[229] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ), .\write_buffer.wr_buf_out_data_reg[230] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ), .\write_buffer.wr_buf_out_data_reg[231] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ), .\write_buffer.wr_buf_out_data_reg[232] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ), .\write_buffer.wr_buf_out_data_reg[233] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ), .\write_buffer.wr_buf_out_data_reg[234] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ), .\write_buffer.wr_buf_out_data_reg[235] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ), .\write_buffer.wr_buf_out_data_reg[236] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ), .\write_buffer.wr_buf_out_data_reg[237] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ), .\write_buffer.wr_buf_out_data_reg[238] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ), .\write_buffer.wr_buf_out_data_reg[239] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ), .\write_buffer.wr_buf_out_data_reg[240] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ), .\write_buffer.wr_buf_out_data_reg[241] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ), .\write_buffer.wr_buf_out_data_reg[242] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ), .\write_buffer.wr_buf_out_data_reg[243] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ), .\write_buffer.wr_buf_out_data_reg[244] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ), .\write_buffer.wr_buf_out_data_reg[245] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ), .\write_buffer.wr_buf_out_data_reg[246] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ), .\write_buffer.wr_buf_out_data_reg[247] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ), .\write_buffer.wr_buf_out_data_reg[248] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ), .\write_buffer.wr_buf_out_data_reg[249] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ), .\write_buffer.wr_buf_out_data_reg[250] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ), .\write_buffer.wr_buf_out_data_reg[251] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ), .\write_buffer.wr_buf_out_data_reg[252] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ), .\write_buffer.wr_buf_out_data_reg[253] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ), .\write_buffer.wr_buf_out_data_reg[254] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ), .\write_buffer.wr_buf_out_data_reg[255] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 )); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_wrcal (rd_active_r1, rd_active_r2, wrcal_pat_resume_r, wrcal_resume_w, idelay_ld_reg_0, wrcal_done_reg_0, \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 , \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 , \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 , \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 , \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 , \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 , \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 , \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 , \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 , \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 , \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 , \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 , \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 , \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 , \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 , \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 , \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 , \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 , \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 , \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 , \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 , \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 , \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 , \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 , \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 , \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 , \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 , \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 , \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 , \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 , \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 , \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 , \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 , \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 , \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 , \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 , \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 , \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 , \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 , \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 , \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 , \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 , \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 , \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 , \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 , \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 , \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 , \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 , \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 , \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 , \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 , \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 , \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 , \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 , \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 , \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 , \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 , \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 , \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 , \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 , early2_data_reg_0, early1_data_reg_0, wrcal_prech_req, wrcal_pat_resume_r_reg_0, cal2_done_r, wrcal_sanity_chk_done_reg_0, wrlvl_byte_redo, early1_data_reg_1, early2_data_reg_1, idelay_ld, phy_if_reset_w, LD0, LD0_0, LD0_1, LD0_2, \init_state_r_reg[3] , wrcal_done_reg_1, \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] , \idelay_tap_cnt_r_reg[0][2][0] , \idelay_tap_cnt_r_reg[0][2][0]_0 , \idelay_tap_cnt_r_reg[0][1][0] , \init_state_r_reg[0] , \init_state_r_reg[2] , \init_state_r_reg[4] , \init_state_r_reg[0]_0 , \init_state_r_reg[0]_1 , \init_state_r_reg[5] , \init_state_r_reg[0]_2 , \corse_cnt_reg[1][2] , \corse_cnt_reg[2][2] , done_dqs_dec239_out, \corse_cnt_reg[0][2] , \wrlvl_redo_corse_inc_reg[2] , \FSM_sequential_wl_state_r_reg[0] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] , \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \gen_byte_sel_div1.byte_sel_cnt_reg[2] , \not_empty_wait_cnt_reg[0]_0 , wrcal_pat_resume_r_reg_1, idelay_ld_done_reg_0, cal2_if_reset_reg_0, cal2_if_reset_reg_1, idelay_ld_reg_1, cal2_done_r_reg_0, wrlvl_byte_redo_reg_0, early1_data_reg_2, cal2_if_reset_reg_2, phy_rddata_en_1, CLK, \po_stg2_wrcal_cnt_reg[1]_0 , \po_stg2_wrcal_cnt_reg[1]_1 , \po_stg2_wrcal_cnt_reg[1]_2 , \po_stg2_wrcal_cnt_reg[1]_3 , wrcal_sanity_chk, p_0_out, \po_stg2_wrcal_cnt_reg[1]_4 , \po_stg2_wrcal_cnt_reg[1]_5 , \po_stg2_wrcal_cnt_reg[1]_6 , \po_stg2_wrcal_cnt_reg[1]_7 , \po_stg2_wrcal_cnt_reg[1]_8 , \po_stg2_wrcal_cnt_reg[1]_9 , \po_stg2_wrcal_cnt_reg[1]_10 , \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 , \po_stg2_wrcal_cnt_reg[1]_11 , \po_stg2_wrcal_cnt_reg[1]_12 , \po_stg2_wrcal_cnt_reg[1]_13 , \po_stg2_wrcal_cnt_reg[1]_14 , \po_stg2_wrcal_cnt_reg[1]_15 , \po_stg2_wrcal_cnt_reg[1]_16 , \po_stg2_wrcal_cnt_reg[1]_17 , \po_stg2_wrcal_cnt_reg[1]_18 , \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 , \po_stg2_wrcal_cnt_reg[1]_19 , \po_stg2_wrcal_cnt_reg[1]_20 , \po_stg2_wrcal_cnt_reg[1]_21 , \po_stg2_wrcal_cnt_reg[1]_22 , \po_stg2_wrcal_cnt_reg[1]_23 , \po_stg2_wrcal_cnt_reg[1]_24 , \po_stg2_wrcal_cnt_reg[1]_25 , \po_stg2_wrcal_cnt_reg[1]_26 , \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 , \po_stg2_wrcal_cnt_reg[1]_27 , \po_stg2_wrcal_cnt_reg[1]_28 , \po_stg2_wrcal_cnt_reg[1]_29 , \po_stg2_wrcal_cnt_reg[1]_30 , \po_stg2_wrcal_cnt_reg[1]_31 , \po_stg2_wrcal_cnt_reg[1]_32 , \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 , \po_stg2_wrcal_cnt_reg[1]_33 , \po_stg2_wrcal_cnt_reg[1]_34 , \po_stg2_wrcal_cnt_reg[1]_35 , \po_stg2_wrcal_cnt_reg[1]_36 , \po_stg2_wrcal_cnt_reg[1]_37 , \po_stg2_wrcal_cnt_reg[1]_38 , \po_stg2_wrcal_cnt_reg[1]_39 , \po_stg2_wrcal_cnt_reg[1]_40 , \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 , \po_stg2_wrcal_cnt_reg[1]_41 , \po_stg2_wrcal_cnt_reg[1]_42 , \po_stg2_wrcal_cnt_reg[1]_43 , \po_stg2_wrcal_cnt_reg[1]_44 , \po_stg2_wrcal_cnt_reg[1]_45 , \po_stg2_wrcal_cnt_reg[1]_46 , \po_stg2_wrcal_cnt_reg[1]_47 , \po_stg2_wrcal_cnt_reg[1]_48 , \po_stg2_wrcal_cnt_reg[1]_49 , \po_stg2_wrcal_cnt_reg[1]_50 , \po_stg2_wrcal_cnt_reg[1]_51 , \po_stg2_wrcal_cnt_reg[1]_52 , \po_stg2_wrcal_cnt_reg[1]_53 , \po_stg2_wrcal_cnt_reg[1]_54 , \po_stg2_wrcal_cnt_reg[1]_55 , \po_stg2_wrcal_cnt_reg[1]_56 , \po_stg2_wrcal_cnt_reg[1]_57 , \po_stg2_wrcal_cnt_reg[1]_58 , \po_stg2_wrcal_cnt_reg[1]_59 , \po_stg2_wrcal_cnt_reg[1]_60 , \po_stg2_wrcal_cnt_reg[1]_61 , \po_stg2_wrcal_cnt_reg[1]_62 , \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__6, wrlvl_byte_done, rstdiv0_sync_r1_reg_rep__5, \cal2_state_r_reg[0]_0 , \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 , \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 , \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 , \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 , \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 , \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 , \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 , \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 , \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 , wrcal_sanity_chk_r_reg_0, \cal2_state_r_reg[3]_0 , \gen_pat_match_div4.early2_data_match_r_reg_0 , \gen_pat_match_div4.early1_data_match_r_reg_0 , \gen_pat_match_div4.early1_data_match_r_reg_1 , \gen_pat_match_div4.pat_data_match_valid_r_reg_0 , rstdiv0_sync_r1_reg_rep__2, \cal2_state_r_reg[2]_0 , \cal2_state_r_reg[0]_1 , Q, \calib_sel_reg[1] , calib_in_common, idelay_ld_rst, idelay_ld_rst_3, idelay_ld_rst_4, idelay_ld_rst_5, dqs_found_done_r_reg, rdlvl_stg1_start_int_reg, rdlvl_stg1_done_int_reg, oclkdelay_calib_done_r_reg, first_wrcal_pat_r, idelay_ce_int, oclkdelay_calib_done_r_reg_0, wrlvl_final_mux, mem_init_done_r, dqs_found_done_r_reg_0, mpr_rdlvl_done_r_reg, mpr_last_byte_done, prbs_rdlvl_done_reg_rep, prech_req_posedge_r_reg, wrcal_resume_r, wrlvl_done_r1, rdlvl_stg1_done_int_reg_0, oclkdelay_center_calib_done_r_reg, prbs_rdlvl_done_reg_rep_0, ddr3_lm_done_r, wrlvl_byte_redo_r, \final_coarse_tap_reg[3][2] , wl_sm_start, prbs_rdlvl_done_reg, \prbs_dqs_cnt_r_reg[0] , \prbs_dqs_cnt_r_reg[1] , rstdiv0_sync_r1_reg_rep__23, wrcal_rd_wait, wrcal_start_reg, prech_done, wrcal_sanity_chk_reg, phy_rddata_en_r1_reg); output rd_active_r1; output rd_active_r2; output wrcal_pat_resume_r; output wrcal_resume_w; output idelay_ld_reg_0; output wrcal_done_reg_0; output \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ; output \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ; output \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ; output \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ; output \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ; output \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ; output \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ; output \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ; output \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ; output \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ; output \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ; output \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ; output \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ; output \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ; output \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ; output \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ; output \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ; output \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ; output \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ; output \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ; output \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ; output \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ; output \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ; output \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ; output \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ; output \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ; output \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ; output \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ; output \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ; output \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ; output \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ; output \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ; output \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ; output \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ; output \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ; output \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ; output \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ; output \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ; output \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ; output \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ; output \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ; output \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ; output \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ; output \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ; output \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ; output \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ; output \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ; output \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ; output \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ; output \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ; output \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ; output \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ; output \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ; output \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ; output \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ; output \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ; output \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ; output \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ; output \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ; output \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ; output early2_data_reg_0; output early1_data_reg_0; output wrcal_prech_req; output wrcal_pat_resume_r_reg_0; output cal2_done_r; output wrcal_sanity_chk_done_reg_0; output wrlvl_byte_redo; output early1_data_reg_1; output early2_data_reg_1; output idelay_ld; output phy_if_reset_w; output LD0; output LD0_0; output LD0_1; output LD0_2; output \init_state_r_reg[3] ; output wrcal_done_reg_1; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; output \idelay_tap_cnt_r_reg[0][2][0] ; output [2:0]\idelay_tap_cnt_r_reg[0][2][0]_0 ; output \idelay_tap_cnt_r_reg[0][1][0] ; output \init_state_r_reg[0] ; output \init_state_r_reg[2] ; output \init_state_r_reg[4] ; output \init_state_r_reg[0]_0 ; output \init_state_r_reg[0]_1 ; output \init_state_r_reg[5] ; output \init_state_r_reg[0]_2 ; output \corse_cnt_reg[1][2] ; output \corse_cnt_reg[2][2] ; output done_dqs_dec239_out; output \corse_cnt_reg[0][2] ; output \wrlvl_redo_corse_inc_reg[2] ; output \FSM_sequential_wl_state_r_reg[0] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; output [3:0]\not_empty_wait_cnt_reg[0]_0 ; output wrcal_pat_resume_r_reg_1; output idelay_ld_done_reg_0; output cal2_if_reset_reg_0; output cal2_if_reset_reg_1; output idelay_ld_reg_1; output cal2_done_r_reg_0; output wrlvl_byte_redo_reg_0; output early1_data_reg_2; output cal2_if_reset_reg_2; input phy_rddata_en_1; input CLK; input \po_stg2_wrcal_cnt_reg[1]_0 ; input \po_stg2_wrcal_cnt_reg[1]_1 ; input \po_stg2_wrcal_cnt_reg[1]_2 ; input \po_stg2_wrcal_cnt_reg[1]_3 ; input wrcal_sanity_chk; input p_0_out; input \po_stg2_wrcal_cnt_reg[1]_4 ; input \po_stg2_wrcal_cnt_reg[1]_5 ; input \po_stg2_wrcal_cnt_reg[1]_6 ; input \po_stg2_wrcal_cnt_reg[1]_7 ; input \po_stg2_wrcal_cnt_reg[1]_8 ; input \po_stg2_wrcal_cnt_reg[1]_9 ; input \po_stg2_wrcal_cnt_reg[1]_10 ; input \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_11 ; input \po_stg2_wrcal_cnt_reg[1]_12 ; input \po_stg2_wrcal_cnt_reg[1]_13 ; input \po_stg2_wrcal_cnt_reg[1]_14 ; input \po_stg2_wrcal_cnt_reg[1]_15 ; input \po_stg2_wrcal_cnt_reg[1]_16 ; input \po_stg2_wrcal_cnt_reg[1]_17 ; input \po_stg2_wrcal_cnt_reg[1]_18 ; input \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_19 ; input \po_stg2_wrcal_cnt_reg[1]_20 ; input \po_stg2_wrcal_cnt_reg[1]_21 ; input \po_stg2_wrcal_cnt_reg[1]_22 ; input \po_stg2_wrcal_cnt_reg[1]_23 ; input \po_stg2_wrcal_cnt_reg[1]_24 ; input \po_stg2_wrcal_cnt_reg[1]_25 ; input \po_stg2_wrcal_cnt_reg[1]_26 ; input \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_27 ; input \po_stg2_wrcal_cnt_reg[1]_28 ; input \po_stg2_wrcal_cnt_reg[1]_29 ; input \po_stg2_wrcal_cnt_reg[1]_30 ; input \po_stg2_wrcal_cnt_reg[1]_31 ; input \po_stg2_wrcal_cnt_reg[1]_32 ; input \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_33 ; input \po_stg2_wrcal_cnt_reg[1]_34 ; input \po_stg2_wrcal_cnt_reg[1]_35 ; input \po_stg2_wrcal_cnt_reg[1]_36 ; input \po_stg2_wrcal_cnt_reg[1]_37 ; input \po_stg2_wrcal_cnt_reg[1]_38 ; input \po_stg2_wrcal_cnt_reg[1]_39 ; input \po_stg2_wrcal_cnt_reg[1]_40 ; input \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ; input \po_stg2_wrcal_cnt_reg[1]_41 ; input \po_stg2_wrcal_cnt_reg[1]_42 ; input \po_stg2_wrcal_cnt_reg[1]_43 ; input \po_stg2_wrcal_cnt_reg[1]_44 ; input \po_stg2_wrcal_cnt_reg[1]_45 ; input \po_stg2_wrcal_cnt_reg[1]_46 ; input \po_stg2_wrcal_cnt_reg[1]_47 ; input \po_stg2_wrcal_cnt_reg[1]_48 ; input \po_stg2_wrcal_cnt_reg[1]_49 ; input \po_stg2_wrcal_cnt_reg[1]_50 ; input \po_stg2_wrcal_cnt_reg[1]_51 ; input \po_stg2_wrcal_cnt_reg[1]_52 ; input \po_stg2_wrcal_cnt_reg[1]_53 ; input \po_stg2_wrcal_cnt_reg[1]_54 ; input \po_stg2_wrcal_cnt_reg[1]_55 ; input \po_stg2_wrcal_cnt_reg[1]_56 ; input \po_stg2_wrcal_cnt_reg[1]_57 ; input \po_stg2_wrcal_cnt_reg[1]_58 ; input \po_stg2_wrcal_cnt_reg[1]_59 ; input \po_stg2_wrcal_cnt_reg[1]_60 ; input \po_stg2_wrcal_cnt_reg[1]_61 ; input \po_stg2_wrcal_cnt_reg[1]_62 ; input \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ; input rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__6; input wrlvl_byte_done; input [0:0]rstdiv0_sync_r1_reg_rep__5; input \cal2_state_r_reg[0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ; input \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ; input \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ; input \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ; input \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ; input \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ; input \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ; input wrcal_sanity_chk_r_reg_0; input \cal2_state_r_reg[3]_0 ; input \gen_pat_match_div4.early2_data_match_r_reg_0 ; input \gen_pat_match_div4.early1_data_match_r_reg_0 ; input \gen_pat_match_div4.early1_data_match_r_reg_1 ; input \gen_pat_match_div4.pat_data_match_valid_r_reg_0 ; input rstdiv0_sync_r1_reg_rep__2; input \cal2_state_r_reg[2]_0 ; input \cal2_state_r_reg[0]_1 ; input [0:0]Q; input [1:0]\calib_sel_reg[1] ; input calib_in_common; input idelay_ld_rst; input idelay_ld_rst_3; input idelay_ld_rst_4; input idelay_ld_rst_5; input dqs_found_done_r_reg; input rdlvl_stg1_start_int_reg; input rdlvl_stg1_done_int_reg; input oclkdelay_calib_done_r_reg; input first_wrcal_pat_r; input idelay_ce_int; input oclkdelay_calib_done_r_reg_0; input wrlvl_final_mux; input mem_init_done_r; input dqs_found_done_r_reg_0; input mpr_rdlvl_done_r_reg; input mpr_last_byte_done; input prbs_rdlvl_done_reg_rep; input prech_req_posedge_r_reg; input wrcal_resume_r; input wrlvl_done_r1; input rdlvl_stg1_done_int_reg_0; input oclkdelay_center_calib_done_r_reg; input prbs_rdlvl_done_reg_rep_0; input ddr3_lm_done_r; input wrlvl_byte_redo_r; input [1:0]\final_coarse_tap_reg[3][2] ; input wl_sm_start; input prbs_rdlvl_done_reg; input \prbs_dqs_cnt_r_reg[0] ; input \prbs_dqs_cnt_r_reg[1] ; input rstdiv0_sync_r1_reg_rep__23; input wrcal_rd_wait; input wrcal_start_reg; input prech_done; input wrcal_sanity_chk_reg; input phy_rddata_en_r1_reg; wire CLK; wire \FSM_sequential_wl_state_r_reg[0] ; wire LD0; wire LD0_0; wire LD0_1; wire LD0_2; wire [0:0]Q; wire cal2_done_r; wire cal2_done_r_reg_0; wire cal2_if_reset_i_5_n_0; wire cal2_if_reset_reg_0; wire cal2_if_reset_reg_1; wire cal2_if_reset_reg_2; wire cal2_prech_req_r; wire cal2_prech_req_r_i_2_n_0; wire cal2_prech_req_r_i_3_n_0; wire cal2_state_r; wire \cal2_state_r[0]_i_1_n_0 ; wire \cal2_state_r[0]_i_2_n_0 ; wire \cal2_state_r[0]_i_3_n_0 ; wire \cal2_state_r[0]_i_4_n_0 ; wire \cal2_state_r[0]_i_5_n_0 ; wire \cal2_state_r[1]_i_1_n_0 ; wire \cal2_state_r[1]_i_2_n_0 ; wire \cal2_state_r[1]_i_3_n_0 ; wire \cal2_state_r[2]_i_1_n_0 ; wire \cal2_state_r[2]_i_2_n_0 ; wire \cal2_state_r[2]_i_3_n_0 ; wire \cal2_state_r[3]_i_11_n_0 ; wire \cal2_state_r[3]_i_3_n_0 ; wire \cal2_state_r[3]_i_4_n_0 ; wire \cal2_state_r[3]_i_5_n_0 ; wire \cal2_state_r[3]_i_6_n_0 ; wire \cal2_state_r[3]_i_7_n_0 ; wire \cal2_state_r[3]_i_8_n_0 ; wire \cal2_state_r[3]_i_9_n_0 ; wire \cal2_state_r_reg[0]_0 ; wire \cal2_state_r_reg[0]_1 ; wire \cal2_state_r_reg[2]_0 ; wire \cal2_state_r_reg[3]_0 ; wire calib_in_common; wire [1:0]\calib_sel_reg[1] ; wire \corse_cnt_reg[0][2] ; wire \corse_cnt_reg[1][2] ; wire \corse_cnt_reg[2][2] ; wire ddr3_lm_done_r; wire done_dqs_dec239_out; wire dqs_found_done_r_reg; wire dqs_found_done_r_reg_0; wire early1_data_i_3_n_0; wire early1_data_match_r0__0; wire early1_data_reg_0; wire early1_data_reg_1; wire early1_data_reg_2; wire early1_match_fall0_and_r; wire early1_match_fall1_and_r; wire early1_match_fall2_and_r; wire early1_match_fall3_and_r; wire early1_match_rise0_and_r; wire early1_match_rise1_and_r; wire early1_match_rise2_and_r; wire early1_match_rise3_and_r; wire early2_data_match_r0__0; wire early2_data_reg_0; wire early2_data_reg_1; wire early2_match_fall0_and_r; wire early2_match_fall1_and_r; wire early2_match_fall2_and_r; wire early2_match_fall3_and_r; wire early2_match_rise0_and_r; wire early2_match_rise1_and_r; wire early2_match_rise2_and_r; wire early2_match_rise3_and_r; wire [1:0]\final_coarse_tap_reg[3][2] ; wire first_wrcal_pat_r; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ; wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ; wire \gen_pat_match_div4.early1_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_data_match_r_reg_0 ; wire \gen_pat_match_div4.early1_data_match_r_reg_1 ; wire \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_data_match_r_reg_0 ; wire \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ; wire \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ; wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ; wire \gen_pat_match_div4.pat_data_match_r_i_2_n_0 ; wire \gen_pat_match_div4.pat_data_match_r_reg_n_0 ; wire \gen_pat_match_div4.pat_data_match_valid_r_reg_0 ; wire \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ; wire \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ; wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ; wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ; wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ; wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ; wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ; wire \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ; wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ; wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ; wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ; wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ; wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ; wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ; wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ; wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ; wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ; wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ; wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ; wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ; wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ; wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ; wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ; wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ; wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ; wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ; wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ; wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ; wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ; wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ; wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ; wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ; wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ; wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ; wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ; wire \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ; wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ; wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ; wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ; wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ; wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ; wire \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ; wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ; wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ; wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ; wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ; wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ; wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ; wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ; wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ; wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ; wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ; wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ; wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ; wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ; wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ; wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ; wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ; wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ; wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ; wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ; wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ; wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ; wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ; wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ; wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ; wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ; wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ; wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ; wire \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ; wire idelay_ce_int; wire idelay_ld; wire idelay_ld_done_reg_0; wire idelay_ld_reg_0; wire idelay_ld_reg_1; wire idelay_ld_rst; wire idelay_ld_rst_3; wire idelay_ld_rst_4; wire idelay_ld_rst_5; wire \idelay_tap_cnt_r_reg[0][1][0] ; wire \idelay_tap_cnt_r_reg[0][2][0] ; wire [2:0]\idelay_tap_cnt_r_reg[0][2][0]_0 ; wire \init_state_r[0]_i_56_n_0 ; wire \init_state_r[4]_i_34_n_0 ; wire \init_state_r_reg[0] ; wire \init_state_r_reg[0]_0 ; wire \init_state_r_reg[0]_1 ; wire \init_state_r_reg[0]_2 ; wire \init_state_r_reg[2] ; wire \init_state_r_reg[3] ; wire \init_state_r_reg[4] ; wire \init_state_r_reg[5] ; wire mem_init_done_r; wire mpr_last_byte_done; wire mpr_rdlvl_done_r_reg; wire \not_empty_wait_cnt[4]_i_1_n_0 ; wire [3:0]\not_empty_wait_cnt_reg[0]_0 ; wire \not_empty_wait_cnt_reg_n_0_[0] ; wire \not_empty_wait_cnt_reg_n_0_[1] ; wire \not_empty_wait_cnt_reg_n_0_[2] ; wire \not_empty_wait_cnt_reg_n_0_[3] ; wire \not_empty_wait_cnt_reg_n_0_[4] ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_center_calib_done_r_reg; wire [4:0]p_0_in; wire [3:0]p_0_in__0; wire p_0_out; wire pat_data_match_r0__0; wire pat_match_fall0_and_r; wire pat_match_fall1_and_r; wire pat_match_fall2_and_r; wire pat_match_fall3_and_r; wire pat_match_rise0_and_r; wire pat_match_rise1_and_r; wire pat_match_rise2_and_r; wire pat_match_rise3_and_r; wire phy_if_reset_w; wire phy_rddata_en_1; wire phy_rddata_en_r1_reg; wire \po_stg2_wrcal_cnt_reg[1]_0 ; wire \po_stg2_wrcal_cnt_reg[1]_1 ; wire \po_stg2_wrcal_cnt_reg[1]_10 ; wire \po_stg2_wrcal_cnt_reg[1]_11 ; wire \po_stg2_wrcal_cnt_reg[1]_12 ; wire \po_stg2_wrcal_cnt_reg[1]_13 ; wire \po_stg2_wrcal_cnt_reg[1]_14 ; wire \po_stg2_wrcal_cnt_reg[1]_15 ; wire \po_stg2_wrcal_cnt_reg[1]_16 ; wire \po_stg2_wrcal_cnt_reg[1]_17 ; wire \po_stg2_wrcal_cnt_reg[1]_18 ; wire \po_stg2_wrcal_cnt_reg[1]_19 ; wire \po_stg2_wrcal_cnt_reg[1]_2 ; wire \po_stg2_wrcal_cnt_reg[1]_20 ; wire \po_stg2_wrcal_cnt_reg[1]_21 ; wire \po_stg2_wrcal_cnt_reg[1]_22 ; wire \po_stg2_wrcal_cnt_reg[1]_23 ; wire \po_stg2_wrcal_cnt_reg[1]_24 ; wire \po_stg2_wrcal_cnt_reg[1]_25 ; wire \po_stg2_wrcal_cnt_reg[1]_26 ; wire \po_stg2_wrcal_cnt_reg[1]_27 ; wire \po_stg2_wrcal_cnt_reg[1]_28 ; wire \po_stg2_wrcal_cnt_reg[1]_29 ; wire \po_stg2_wrcal_cnt_reg[1]_3 ; wire \po_stg2_wrcal_cnt_reg[1]_30 ; wire \po_stg2_wrcal_cnt_reg[1]_31 ; wire \po_stg2_wrcal_cnt_reg[1]_32 ; wire \po_stg2_wrcal_cnt_reg[1]_33 ; wire \po_stg2_wrcal_cnt_reg[1]_34 ; wire \po_stg2_wrcal_cnt_reg[1]_35 ; wire \po_stg2_wrcal_cnt_reg[1]_36 ; wire \po_stg2_wrcal_cnt_reg[1]_37 ; wire \po_stg2_wrcal_cnt_reg[1]_38 ; wire \po_stg2_wrcal_cnt_reg[1]_39 ; wire \po_stg2_wrcal_cnt_reg[1]_4 ; wire \po_stg2_wrcal_cnt_reg[1]_40 ; wire \po_stg2_wrcal_cnt_reg[1]_41 ; wire \po_stg2_wrcal_cnt_reg[1]_42 ; wire \po_stg2_wrcal_cnt_reg[1]_43 ; wire \po_stg2_wrcal_cnt_reg[1]_44 ; wire \po_stg2_wrcal_cnt_reg[1]_45 ; wire \po_stg2_wrcal_cnt_reg[1]_46 ; wire \po_stg2_wrcal_cnt_reg[1]_47 ; wire \po_stg2_wrcal_cnt_reg[1]_48 ; wire \po_stg2_wrcal_cnt_reg[1]_49 ; wire \po_stg2_wrcal_cnt_reg[1]_5 ; wire \po_stg2_wrcal_cnt_reg[1]_50 ; wire \po_stg2_wrcal_cnt_reg[1]_51 ; wire \po_stg2_wrcal_cnt_reg[1]_52 ; wire \po_stg2_wrcal_cnt_reg[1]_53 ; wire \po_stg2_wrcal_cnt_reg[1]_54 ; wire \po_stg2_wrcal_cnt_reg[1]_55 ; wire \po_stg2_wrcal_cnt_reg[1]_56 ; wire \po_stg2_wrcal_cnt_reg[1]_57 ; wire \po_stg2_wrcal_cnt_reg[1]_58 ; wire \po_stg2_wrcal_cnt_reg[1]_59 ; wire \po_stg2_wrcal_cnt_reg[1]_6 ; wire \po_stg2_wrcal_cnt_reg[1]_60 ; wire \po_stg2_wrcal_cnt_reg[1]_61 ; wire \po_stg2_wrcal_cnt_reg[1]_62 ; wire \po_stg2_wrcal_cnt_reg[1]_7 ; wire \po_stg2_wrcal_cnt_reg[1]_8 ; wire \po_stg2_wrcal_cnt_reg[1]_9 ; wire \prbs_dqs_cnt_r_reg[0] ; wire \prbs_dqs_cnt_r_reg[1] ; wire prbs_rdlvl_done_reg; wire prbs_rdlvl_done_reg_rep; wire prbs_rdlvl_done_reg_rep_0; wire prech_done; wire prech_req_posedge_r_reg; wire rd_active_r1; wire rd_active_r2; wire rd_active_r3; wire rdlvl_stg1_done_int_reg; wire rdlvl_stg1_done_int_reg_0; wire rdlvl_stg1_start_int_reg; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__4; wire [0:0]rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire \tap_inc_wait_cnt[3]_i_1_n_0 ; wire [3:0]tap_inc_wait_cnt_reg__0; wire wl_sm_start; wire wrcal_done_i_1_n_0; wire wrcal_done_reg_0; wire wrcal_done_reg_1; wire [2:2]wrcal_dqs_cnt_r; wire \wrcal_dqs_cnt_r[0]_i_1_n_0 ; wire \wrcal_dqs_cnt_r[1]_i_1_n_0 ; wire \wrcal_dqs_cnt_r[2]_i_2_n_0 ; wire \wrcal_dqs_cnt_r[2]_i_3_n_0 ; wire \wrcal_dqs_cnt_r[2]_i_4_n_0 ; wire \wrcal_dqs_cnt_r_reg_n_0_[0] ; wire \wrcal_dqs_cnt_r_reg_n_0_[1] ; wire wrcal_pat_resume_r; wire wrcal_pat_resume_r2_reg_srl2_n_0; wire wrcal_pat_resume_r_i_3_n_0; wire wrcal_pat_resume_r_reg_0; wire wrcal_pat_resume_r_reg_1; wire wrcal_prech_req; wire wrcal_rd_wait; wire wrcal_resume_r; wire wrcal_resume_w; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done_reg_0; wire wrcal_sanity_chk_r_reg_0; wire wrcal_sanity_chk_reg; wire wrcal_start_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; wire wrlvl_byte_done; wire wrlvl_byte_done_r; wire wrlvl_byte_redo; wire wrlvl_byte_redo_i_3_n_0; wire wrlvl_byte_redo_r; wire wrlvl_byte_redo_reg_0; wire wrlvl_done_r1; wire wrlvl_final_mux; wire \wrlvl_redo_corse_inc_reg[2] ; (* SOFT_HLUTNM = "soft_lutpair635" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_wl_state_r[4]_i_13 (.I0(wrlvl_byte_redo), .I1(wl_sm_start), .O(\FSM_sequential_wl_state_r_reg[0] )); LUT4 #( .INIT(16'hDD45)) \FSM_sequential_wl_state_r[4]_i_6 (.I0(early1_data_reg_1), .I1(\final_coarse_tap_reg[3][2] [0]), .I2(early2_data_reg_1), .I3(\final_coarse_tap_reg[3][2] [1]), .O(\wrlvl_redo_corse_inc_reg[2] )); LUT4 #( .INIT(16'h0040)) cal2_done_r_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(\not_empty_wait_cnt_reg[0]_0 [0]), .O(cal2_done_r_reg_0)); FDRE cal2_done_r_reg (.C(CLK), .CE(1'b1), .D(wrcal_sanity_chk_r_reg_0), .Q(cal2_done_r), .R(rstdiv0_sync_r1_reg_rep__5)); LUT6 #( .INIT(64'h004F0040F000F000)) cal2_if_reset_i_2 (.I0(phy_rddata_en_1), .I1(rd_active_r1), .I2(\not_empty_wait_cnt_reg[0]_0 [0]), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(wrcal_done_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [1]), .O(cal2_if_reset_reg_2)); LUT6 #( .INIT(64'h00FF000008FF08FF)) cal2_if_reset_i_3 (.I0(wrlvl_byte_done), .I1(rd_active_r1), .I2(phy_rddata_en_1), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(idelay_ld_done_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [2]), .O(cal2_if_reset_reg_1)); LUT6 #( .INIT(64'hFF80FFFFFF800000)) cal2_if_reset_i_4 (.I0(prech_done), .I1(cal2_prech_req_r_i_3_n_0), .I2(wrcal_done_reg_0), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(cal2_if_reset_i_5_n_0), .O(cal2_if_reset_reg_0)); LUT6 #( .INIT(64'h8000FFFF80000000)) cal2_if_reset_i_5 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(tap_inc_wait_cnt_reg__0[3]), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .I5(wrcal_start_reg), .O(cal2_if_reset_i_5_n_0)); FDRE cal2_if_reset_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[0]_1 ), .Q(phy_if_reset_w), .R(rstdiv0_sync_r1_reg_rep__4)); LUT6 #( .INIT(64'h0000000010110000)) cal2_prech_req_r_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(cal2_prech_req_r_i_3_n_0), .I3(wrcal_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(\not_empty_wait_cnt_reg[0]_0 [0]), .O(cal2_prech_req_r_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair634" *) LUT3 #( .INIT(8'h08)) cal2_prech_req_r_i_3 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I2(wrcal_dqs_cnt_r), .O(cal2_prech_req_r_i_3_n_0)); FDRE cal2_prech_req_r_reg (.C(CLK), .CE(1'b1), .D(cal2_prech_req_r_i_2_n_0), .Q(cal2_prech_req_r), .R(rstdiv0_sync_r1_reg_rep__4)); LUT6 #( .INIT(64'h00000000E2FFE200)) \cal2_state_r[0]_i_1 (.I0(\cal2_state_r[0]_i_2_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\not_empty_wait_cnt_reg[0]_0 [0]), .I4(\cal2_state_r[0]_i_3_n_0 ), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(\cal2_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hBBB8BBBB88888888)) \cal2_state_r[0]_i_2 (.I0(tap_inc_wait_cnt_reg__0[0]), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(early2_data_reg_0), .I3(early1_data_reg_0), .I4(wrcal_pat_resume_r_reg_0), .I5(\cal2_state_r[0]_i_4_n_0 ), .O(\cal2_state_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'h000F0000DFDFDFDF)) \cal2_state_r[0]_i_3 (.I0(prech_done), .I1(\cal2_state_r[0]_i_5_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrcal_done_reg_0), .I4(wrcal_pat_resume_r_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [2]), .O(\cal2_state_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair618" *) LUT3 #( .INIT(8'h04)) \cal2_state_r[0]_i_4 (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I1(idelay_ld_reg_0), .I2(wrcal_done_reg_0), .O(\cal2_state_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair617" *) LUT3 #( .INIT(8'hF7)) \cal2_state_r[0]_i_5 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I2(wrcal_dqs_cnt_r), .O(\cal2_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \cal2_state_r[1]_i_1 (.I0(\cal2_state_r[1]_i_2_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(\cal2_state_r[1]_i_3_n_0 ), .O(\cal2_state_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair618" *) LUT5 #( .INIT(32'hFF003200)) \cal2_state_r[1]_i_2 (.I0(early2_data_reg_0), .I1(wrcal_done_reg_0), .I2(early1_data_reg_0), .I3(idelay_ld_reg_0), .I4(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .O(\cal2_state_r[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair619" *) LUT5 #( .INIT(32'h0F0050D0)) \cal2_state_r[1]_i_3 (.I0(prech_done), .I1(cal2_prech_req_r_i_3_n_0), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrcal_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .O(\cal2_state_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'h4F4AFFFF4F4A0000)) \cal2_state_r[2]_i_1 (.I0(\not_empty_wait_cnt_reg[0]_0 [1]), .I1(tap_inc_wait_cnt_reg__0[2]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\cal2_state_r[2]_i_2_n_0 ), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(\cal2_state_r[2]_i_3_n_0 ), .O(\cal2_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000010)) \cal2_state_r[2]_i_2 (.I0(early2_data_reg_0), .I1(wrcal_done_reg_0), .I2(idelay_ld_reg_0), .I3(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I4(early1_data_reg_0), .I5(wrcal_pat_resume_r_reg_0), .O(\cal2_state_r[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair619" *) LUT5 #( .INIT(32'h0F00D0D0)) \cal2_state_r[2]_i_3 (.I0(prech_done), .I1(cal2_prech_req_r_i_3_n_0), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrcal_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .O(\cal2_state_r[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair615" *) LUT4 #( .INIT(16'h8000)) \cal2_state_r[3]_i_11 (.I0(\not_empty_wait_cnt_reg_n_0_[2] ), .I1(\not_empty_wait_cnt_reg_n_0_[1] ), .I2(\not_empty_wait_cnt_reg_n_0_[0] ), .I3(\not_empty_wait_cnt_reg_n_0_[3] ), .O(\cal2_state_r[3]_i_11_n_0 )); LUT6 #( .INIT(64'h00E2FFFF00E20000)) \cal2_state_r[3]_i_3 (.I0(\cal2_state_r[3]_i_6_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(tap_inc_wait_cnt_reg__0[3]), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(\cal2_state_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h45404F4F45404A4A)) \cal2_state_r[3]_i_4 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\cal2_state_r[3]_i_7_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(\cal2_state_r[3]_i_8_n_0 ), .I4(\not_empty_wait_cnt_reg[0]_0 [2]), .I5(wrcal_start_reg), .O(\cal2_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000EEE222E2)) \cal2_state_r[3]_i_5 (.I0(\cal2_state_r[3]_i_9_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(phy_rddata_en_r1_reg), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(\cal2_state_r[3]_i_8_n_0 ), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(\cal2_state_r[3]_i_5_n_0 )); LUT6 #( .INIT(64'h00FF0010FFFFFFFF)) \cal2_state_r[3]_i_6 (.I0(early2_data_reg_0), .I1(early1_data_reg_0), .I2(wrcal_pat_resume_r_reg_0), .I3(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I4(wrcal_done_reg_0), .I5(idelay_ld_reg_0), .O(\cal2_state_r[3]_i_6_n_0 )); LUT5 #( .INIT(32'h3B3B3808)) \cal2_state_r[3]_i_7 (.I0(wrcal_sanity_chk), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(wrcal_done_reg_0), .I3(\cal2_state_r[0]_i_5_n_0 ), .I4(prech_done), .O(\cal2_state_r[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair630" *) LUT4 #( .INIT(16'h8000)) \cal2_state_r[3]_i_8 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(tap_inc_wait_cnt_reg__0[3]), .O(\cal2_state_r[3]_i_8_n_0 )); LUT5 #( .INIT(32'hBBBBB888)) \cal2_state_r[3]_i_9 (.I0(idelay_ld_done_reg_0), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(\cal2_state_r[3]_i_11_n_0 ), .I3(\not_empty_wait_cnt_reg_n_0_[4] ), .I4(idelay_ld_reg_0), .O(\cal2_state_r[3]_i_9_n_0 )); FDRE \cal2_state_r_reg[0] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[0]_i_1_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [0]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \cal2_state_r_reg[1] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[1]_i_1_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [1]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \cal2_state_r_reg[2] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[2]_i_1_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [2]), .R(rstdiv0_sync_r1_reg_rep__5)); FDRE \cal2_state_r_reg[3] (.C(CLK), .CE(cal2_state_r), .D(\cal2_state_r[3]_i_3_n_0 ), .Q(\not_empty_wait_cnt_reg[0]_0 [3]), .R(rstdiv0_sync_r1_reg_rep__5)); MUXF7 \cal2_state_r_reg[3]_i_2 (.I0(\cal2_state_r[3]_i_4_n_0 ), .I1(\cal2_state_r[3]_i_5_n_0 ), .O(cal2_state_r), .S(\not_empty_wait_cnt_reg[0]_0 [0])); LUT2 #( .INIT(4'h1)) \corse_cnt[0][2]_i_11 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .I1(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .O(\corse_cnt_reg[0][2] )); (* SOFT_HLUTNM = "soft_lutpair625" *) LUT4 #( .INIT(16'hFBFF)) \corse_cnt[1][2]_i_5 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .I1(wrlvl_byte_redo), .I2(wrlvl_byte_redo_r), .I3(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .O(\corse_cnt_reg[1][2] )); (* SOFT_HLUTNM = "soft_lutpair635" *) LUT3 #( .INIT(8'hDF)) \corse_cnt[2][2]_i_5 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [1]), .I1(wrlvl_byte_redo_r), .I2(wrlvl_byte_redo), .O(\corse_cnt_reg[2][2] )); LUT5 #( .INIT(32'h45400000)) early1_data_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(early1_data_i_3_n_0), .I2(\not_empty_wait_cnt_reg[0]_0 [1]), .I3(wrlvl_byte_redo_i_3_n_0), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .O(early1_data_reg_2)); LUT4 #( .INIT(16'h0008)) early1_data_i_3 (.I0(wrlvl_byte_done), .I1(rd_active_r1), .I2(phy_rddata_en_1), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .O(early1_data_i_3_n_0)); FDRE early1_data_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_data_match_r_reg_0 ), .Q(early1_data_reg_1), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE early2_data_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_data_match_r_reg_1 ), .Q(early2_data_reg_1), .R(rstdiv0_sync_r1_reg_rep__6)); LUT6 #( .INIT(64'h0CAA000000AA0000)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_3 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg), .I3(wrcal_done_reg_1), .I4(oclkdelay_calib_done_r_reg), .I5(\prbs_dqs_cnt_r_reg[0] ), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'h0CAA000000AA0000)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_3 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [1]), .I1(rdlvl_stg1_done_int_reg), .I2(prbs_rdlvl_done_reg), .I3(wrcal_done_reg_1), .I4(oclkdelay_calib_done_r_reg), .I5(\prbs_dqs_cnt_r_reg[1] ), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair632" *) LUT4 #( .INIT(16'h0800)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_6 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .I1(mpr_rdlvl_done_r_reg), .I2(wrcal_done_reg_1), .I3(oclkdelay_calib_done_r_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_19 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_55 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_33 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_11 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_47 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_out), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_41 ), .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_20 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_56 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_34 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_12 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_48 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_4 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_27 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_42 ), .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_21 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_57 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_35 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_13 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_49 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_5 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_28 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_43 ), .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_22 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_58 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_36 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_14 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_50 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_6 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_29 ), .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_23 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_59 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_37 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_15 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_51 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_7 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_44 ), .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_24 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_60 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_38 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_16 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_52 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_8 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_30 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_45 ), .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_25 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_61 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_39 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_17 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_53 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_9 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_31 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_46 ), .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_26 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_62 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_40 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_18 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_54 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_10 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .R(1'b0)); FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\po_stg2_wrcal_cnt_reg[1]_32 ), .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early1_data_match_r_i_1 (.I0(early1_match_rise2_and_r), .I1(early1_match_rise3_and_r), .I2(early1_match_fall1_and_r), .I3(early1_match_rise1_and_r), .I4(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ), .O(early1_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early1_data_match_r_i_2 (.I0(early1_match_rise0_and_r), .I1(early1_match_fall3_and_r), .I2(early1_match_fall0_and_r), .I3(early1_match_fall2_and_r), .O(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_data_match_r_reg (.C(CLK), .CE(1'b1), .D(early1_data_match_r0__0), .Q(early1_data_reg_0), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early1_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ), .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early1_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ), .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ), .Q(early1_match_fall0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ), .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair616" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ), .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ), .Q(early1_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ), .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ), .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ), .Q(early1_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ), .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair622" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ), .Q(early1_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early1_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ), .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early1_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ), .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ), .Q(early1_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ), .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair624" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ), .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ), .Q(early1_match_rise1_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair620" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ), .I4(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ), .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ), .Q(early1_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early1_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ), .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early1_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ), .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early1_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ), .Q(early1_match_rise3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early2_data_match_r_i_1 (.I0(early2_match_fall0_and_r), .I1(early2_match_rise2_and_r), .I2(early2_match_fall3_and_r), .I3(early2_match_rise1_and_r), .I4(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ), .O(early2_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early2_data_match_r_i_2 (.I0(early2_match_rise3_and_r), .I1(early2_match_fall2_and_r), .I2(early2_match_fall1_and_r), .I3(early2_match_rise0_and_r), .O(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_data_match_r_reg (.C(CLK), .CE(1'b1), .D(early2_data_match_r0__0), .Q(early2_data_reg_0), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ), .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair621" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_fall0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ), .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ), .Q(early2_match_fall0_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair616" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ), .I4(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_fall1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ), .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ), .Q(early2_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early2_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ), .I4(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early2_match_fall2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ), .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ), .Q(early2_match_fall2_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair622" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ), .I4(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_fall3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ), .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ), .Q(early2_match_fall3_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ), .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair614" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_rise0_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ), .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ), .Q(early2_match_rise0_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair624" *) LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ), .I4(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_rise1_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ), .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ), .Q(early2_match_rise1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.early2_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ), .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair620" *) LUT4 #( .INIT(16'h8000)) \gen_pat_match_div4.early2_match_rise2_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ), .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ), .Q(early2_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.early2_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ), .I4(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 )); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.early2_match_rise3_and_r_i_2 (.I0(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ), .I1(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ), .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 )); FDRE \gen_pat_match_div4.early2_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ), .Q(early2_match_rise3_and_r), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .Q(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .Q(\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .Q(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .Q(\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ), .R(1'b0)); FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (.C(CLK), .CE(1'b1), .D(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ), .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ), .R(1'b0)); LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat_data_match_r_i_1 (.I0(pat_match_rise0_and_r), .I1(pat_match_rise3_and_r), .I2(pat_match_fall2_and_r), .I3(pat_match_fall3_and_r), .I4(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ), .O(pat_data_match_r0__0)); LUT4 #( .INIT(16'h7FFF)) \gen_pat_match_div4.pat_data_match_r_i_2 (.I0(pat_match_fall0_and_r), .I1(pat_match_rise2_and_r), .I2(pat_match_rise1_and_r), .I3(pat_match_fall1_and_r), .O(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 )); FDRE \gen_pat_match_div4.pat_data_match_r_reg (.C(CLK), .CE(1'b1), .D(pat_data_match_r0__0), .Q(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .R(1'b0)); FDRE \gen_pat_match_div4.pat_data_match_valid_r_reg (.C(CLK), .CE(1'b1), .D(rd_active_r3), .Q(idelay_ld_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair621" *) LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat_match_fall0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ), .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_fall0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ), .Q(pat_match_fall0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_fall1_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ), .O(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_fall1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ), .Q(pat_match_fall1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_fall2_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ), .O(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_fall2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ), .Q(pat_match_fall2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_fall3_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ), .O(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_fall3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ), .Q(pat_match_fall3_and_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair614" *) LUT5 #( .INIT(32'h00008000)) \gen_pat_match_div4.pat_match_rise0_and_r_i_1 (.I0(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ), .I1(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ), .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ), .O(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_rise0_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ), .Q(pat_match_rise0_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_rise1_and_r_i_1 (.I0(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ), .O(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_rise1_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ), .Q(pat_match_rise1_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_rise2_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ), .I2(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ), .I3(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ), .I4(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ), .O(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_rise2_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ), .Q(pat_match_rise2_and_r), .R(1'b0)); LUT5 #( .INIT(32'h80000000)) \gen_pat_match_div4.pat_match_rise3_and_r_i_1 (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ), .I1(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ), .I2(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ), .I3(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ), .I4(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ), .O(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 )); FDRE \gen_pat_match_div4.pat_match_rise3_and_r_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ), .Q(pat_match_rise3_and_r), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 " *) SRL16E \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_0 ), .Q(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 )); FDRE \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ), .Q(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ), .Q(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ), .Q(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ), .Q(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 " *) SRL16E \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_2 ), .Q(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 )); FDRE \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 " *) SRL16E \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_1 ), .Q(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 )); FDRE \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ), .Q(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ), .Q(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ), .Q(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ), .R(1'b0)); FDRE \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] (.C(CLK), .CE(1'b1), .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ), .Q(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ), .R(1'b0)); (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 " *) SRL16E \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\po_stg2_wrcal_cnt_reg[1]_3 ), .Q(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair628" *) LUT4 #( .INIT(16'h0002)) idelay_ld_done_i_2 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .I3(tap_inc_wait_cnt_reg__0[3]), .O(idelay_ld_done_reg_0)); FDRE idelay_ld_done_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[0]_0 ), .Q(wrcal_pat_resume_r_reg_0), .R(rstdiv0_sync_r1_reg_rep__5)); LUT6 #( .INIT(64'h0000540400000000)) idelay_ld_i_2 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\cal2_state_r[2]_i_2_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(idelay_ld_done_reg_0), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(\not_empty_wait_cnt_reg[0]_0 [0]), .O(idelay_ld_reg_1)); FDRE idelay_ld_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ), .Q(idelay_ld), .R(rstdiv0_sync_r1_reg_rep__4)); (* SOFT_HLUTNM = "soft_lutpair627" *) LUT4 #( .INIT(16'hFFEF)) \idelay_tap_cnt_r[0][0][4]_i_3 (.I0(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .I1(idelay_ce_int), .I2(idelay_ld), .I3(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .O(\idelay_tap_cnt_r_reg[0][2][0] )); (* SOFT_HLUTNM = "soft_lutpair627" *) LUT4 #( .INIT(16'hFBFF)) \idelay_tap_cnt_r[0][1][4]_i_2 (.I0(idelay_ce_int), .I1(idelay_ld), .I2(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .I3(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .O(\idelay_tap_cnt_r_reg[0][1][0] )); LUT6 #( .INIT(64'h5555555545555555)) \init_state_r[0]_i_12 (.I0(wrcal_sanity_chk_done_reg_0), .I1(prbs_rdlvl_done_reg_rep_0), .I2(wrlvl_done_r1), .I3(dqs_found_done_r_reg), .I4(wrcal_done_reg_1), .I5(ddr3_lm_done_r), .O(\init_state_r_reg[0]_2 )); LUT6 #( .INIT(64'h5700575757575757)) \init_state_r[0]_i_36 (.I0(oclkdelay_calib_done_r_reg_0), .I1(wrlvl_final_mux), .I2(wrlvl_byte_redo), .I3(mem_init_done_r), .I4(\init_state_r_reg[2] ), .I5(dqs_found_done_r_reg_0), .O(\init_state_r_reg[0] )); LUT6 #( .INIT(64'h00D000D000D0FFFF)) \init_state_r[0]_i_55 (.I0(prbs_rdlvl_done_reg_rep), .I1(\init_state_r[0]_i_56_n_0 ), .I2(wrlvl_done_r1), .I3(wrlvl_byte_redo), .I4(rdlvl_stg1_done_int_reg_0), .I5(dqs_found_done_r_reg), .O(\init_state_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair626" *) LUT2 #( .INIT(4'h7)) \init_state_r[0]_i_56 (.I0(wrcal_done_reg_1), .I1(rdlvl_stg1_done_int_reg), .O(\init_state_r[0]_i_56_n_0 )); (* SOFT_HLUTNM = "soft_lutpair629" *) LUT4 #( .INIT(16'h0001)) \init_state_r[2]_i_23 (.I0(wrcal_done_reg_1), .I1(prech_req_posedge_r_reg), .I2(wrlvl_byte_redo), .I3(wrcal_resume_r), .O(\init_state_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair626" *) LUT4 #( .INIT(16'hB0BB)) \init_state_r[2]_i_29 (.I0(wrlvl_done_r1), .I1(wrlvl_final_mux), .I2(wrcal_done_reg_1), .I3(wrlvl_byte_redo), .O(\init_state_r_reg[2] )); LUT3 #( .INIT(8'h08)) \init_state_r[3]_i_12 (.I0(wrcal_done_reg_1), .I1(dqs_found_done_r_reg), .I2(rdlvl_stg1_start_int_reg), .O(\init_state_r_reg[3] )); LUT6 #( .INIT(64'h2FAF2FAF2FAF0000)) \init_state_r[4]_i_23 (.I0(\init_state_r[4]_i_34_n_0 ), .I1(mem_init_done_r), .I2(oclkdelay_calib_done_r_reg), .I3(wrcal_done_reg_1), .I4(mpr_rdlvl_done_r_reg), .I5(mpr_last_byte_done), .O(\init_state_r_reg[4] )); LUT6 #( .INIT(64'hB010000000000000)) \init_state_r[4]_i_34 (.I0(rdlvl_stg1_done_int_reg), .I1(wrcal_done_reg_1), .I2(dqs_found_done_r_reg), .I3(prbs_rdlvl_done_reg_rep), .I4(\init_state_r_reg[2] ), .I5(dqs_found_done_r_reg_0), .O(\init_state_r[4]_i_34_n_0 )); LUT6 #( .INIT(64'hFFFBFFFBFF00FFFB)) \init_state_r[5]_i_28 (.I0(wrlvl_byte_redo), .I1(dqs_found_done_r_reg), .I2(wrlvl_final_mux), .I3(wrlvl_done_r1), .I4(oclkdelay_center_calib_done_r_reg), .I5(prbs_rdlvl_done_reg_rep_0), .O(\init_state_r_reg[5] )); LUT6 #( .INIT(64'hFFFFFFFF44440004)) \input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [0]), .I3(\calib_sel_reg[1] [1]), .I4(calib_in_common), .I5(idelay_ld_rst), .O(LD0)); LUT6 #( .INIT(64'hFFFFFFFF44440040)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [0]), .I3(\calib_sel_reg[1] [1]), .I4(calib_in_common), .I5(idelay_ld_rst_3), .O(LD0_0)); LUT6 #( .INIT(64'hFFFFFFFF44440040)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__0 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [1]), .I3(\calib_sel_reg[1] [0]), .I4(calib_in_common), .I5(idelay_ld_rst_4), .O(LD0_1)); LUT6 #( .INIT(64'hFFFFFFFF44444000)) \input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__1 (.I0(Q), .I1(idelay_ld), .I2(\calib_sel_reg[1] [0]), .I3(\calib_sel_reg[1] [1]), .I4(calib_in_common), .I5(idelay_ld_rst_5), .O(LD0_2)); (* SOFT_HLUTNM = "soft_lutpair636" *) LUT1 #( .INIT(2'h1)) \not_empty_wait_cnt[0]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[0] ), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair636" *) LUT2 #( .INIT(4'h6)) \not_empty_wait_cnt[1]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[0] ), .I1(\not_empty_wait_cnt_reg_n_0_[1] ), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair631" *) LUT3 #( .INIT(8'h6A)) \not_empty_wait_cnt[2]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[2] ), .I1(\not_empty_wait_cnt_reg_n_0_[1] ), .I2(\not_empty_wait_cnt_reg_n_0_[0] ), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair631" *) LUT4 #( .INIT(16'h6AAA)) \not_empty_wait_cnt[3]_i_1 (.I0(\not_empty_wait_cnt_reg_n_0_[3] ), .I1(\not_empty_wait_cnt_reg_n_0_[0] ), .I2(\not_empty_wait_cnt_reg_n_0_[1] ), .I3(\not_empty_wait_cnt_reg_n_0_[2] ), .O(p_0_in[3])); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) \not_empty_wait_cnt[4]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\not_empty_wait_cnt_reg[0]_0 [3]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\not_empty_wait_cnt_reg[0]_0 [1]), .I4(\not_empty_wait_cnt_reg[0]_0 [0]), .I5(wrcal_rd_wait), .O(\not_empty_wait_cnt[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair615" *) LUT5 #( .INIT(32'h6AAAAAAA)) \not_empty_wait_cnt[4]_i_2 (.I0(\not_empty_wait_cnt_reg_n_0_[4] ), .I1(\not_empty_wait_cnt_reg_n_0_[2] ), .I2(\not_empty_wait_cnt_reg_n_0_[1] ), .I3(\not_empty_wait_cnt_reg_n_0_[0] ), .I4(\not_empty_wait_cnt_reg_n_0_[3] ), .O(p_0_in[4])); FDRE \not_empty_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in[0]), .Q(\not_empty_wait_cnt_reg_n_0_[0] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE \not_empty_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in[1]), .Q(\not_empty_wait_cnt_reg_n_0_[1] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE \not_empty_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in[2]), .Q(\not_empty_wait_cnt_reg_n_0_[2] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE \not_empty_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in[3]), .Q(\not_empty_wait_cnt_reg_n_0_[3] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE \not_empty_wait_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(p_0_in[4]), .Q(\not_empty_wait_cnt_reg_n_0_[4] ), .R(\not_empty_wait_cnt[4]_i_1_n_0 )); FDRE \po_stg2_wrcal_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .Q(\idelay_tap_cnt_r_reg[0][2][0]_0 [0]), .R(1'b0)); FDRE \po_stg2_wrcal_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .Q(\idelay_tap_cnt_r_reg[0][2][0]_0 [1]), .R(1'b0)); FDRE \po_stg2_wrcal_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(wrcal_dqs_cnt_r), .Q(\idelay_tap_cnt_r_reg[0][2][0]_0 [2]), .R(1'b0)); FDRE rd_active_r1_reg (.C(CLK), .CE(1'b1), .D(phy_rddata_en_1), .Q(rd_active_r1), .R(1'b0)); FDRE rd_active_r2_reg (.C(CLK), .CE(1'b1), .D(rd_active_r1), .Q(rd_active_r2), .R(1'b0)); FDRE rd_active_r3_reg (.C(CLK), .CE(1'b1), .D(rd_active_r2), .Q(rd_active_r3), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair637" *) LUT1 #( .INIT(2'h1)) \tap_inc_wait_cnt[0]_i_1 (.I0(tap_inc_wait_cnt_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair637" *) LUT2 #( .INIT(4'h6)) \tap_inc_wait_cnt[1]_i_1 (.I0(tap_inc_wait_cnt_reg__0[1]), .I1(tap_inc_wait_cnt_reg__0[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair630" *) LUT3 #( .INIT(8'h6A)) \tap_inc_wait_cnt[2]_i_1 (.I0(tap_inc_wait_cnt_reg__0[2]), .I1(tap_inc_wait_cnt_reg__0[0]), .I2(tap_inc_wait_cnt_reg__0[1]), .O(p_0_in__0[2])); LUT5 #( .INIT(32'hFFFFAFEF)) \tap_inc_wait_cnt[3]_i_1 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\not_empty_wait_cnt_reg[0]_0 [0]), .I4(rstdiv0_sync_r1_reg_rep__23), .O(\tap_inc_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair628" *) LUT4 #( .INIT(16'h6AAA)) \tap_inc_wait_cnt[3]_i_2 (.I0(tap_inc_wait_cnt_reg__0[3]), .I1(tap_inc_wait_cnt_reg__0[1]), .I2(tap_inc_wait_cnt_reg__0[0]), .I3(tap_inc_wait_cnt_reg__0[2]), .O(p_0_in__0[3])); FDRE \tap_inc_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0[0]), .Q(tap_inc_wait_cnt_reg__0[0]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); FDRE \tap_inc_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0[1]), .Q(tap_inc_wait_cnt_reg__0[1]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); FDRE \tap_inc_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0[2]), .Q(tap_inc_wait_cnt_reg__0[2]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); FDRE \tap_inc_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0[3]), .Q(tap_inc_wait_cnt_reg__0[3]), .R(\tap_inc_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair625" *) LUT2 #( .INIT(4'h2)) \wl_tap_count_r[5]_i_3 (.I0(wrlvl_byte_redo), .I1(wrlvl_byte_redo_r), .O(done_dqs_dec239_out)); LUT5 #( .INIT(32'h0E0E000E)) wrcal_done_i_1 (.I0(wrcal_done_reg_1), .I1(cal2_done_r), .I2(rstdiv0_sync_r1_reg_rep__23), .I3(wrcal_sanity_chk), .I4(wrcal_done_reg_0), .O(wrcal_done_i_1_n_0)); FDRE wrcal_done_reg (.C(CLK), .CE(1'b1), .D(wrcal_done_i_1_n_0), .Q(wrcal_done_reg_1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair634" *) LUT3 #( .INIT(8'h34)) \wrcal_dqs_cnt_r[0]_i_1 (.I0(\not_empty_wait_cnt_reg[0]_0 [2]), .I1(\wrcal_dqs_cnt_r[2]_i_3_n_0 ), .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .O(\wrcal_dqs_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair623" *) LUT4 #( .INIT(16'h1F20)) \wrcal_dqs_cnt_r[1]_i_1 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I1(\not_empty_wait_cnt_reg[0]_0 [2]), .I2(\wrcal_dqs_cnt_r[2]_i_3_n_0 ), .I3(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .O(\wrcal_dqs_cnt_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair623" *) LUT5 #( .INIT(32'h07FF0800)) \wrcal_dqs_cnt_r[2]_i_2 (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(\wrcal_dqs_cnt_r[2]_i_3_n_0 ), .I4(wrcal_dqs_cnt_r), .O(\wrcal_dqs_cnt_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000054040000)) \wrcal_dqs_cnt_r[2]_i_3 (.I0(\not_empty_wait_cnt_reg[0]_0 [3]), .I1(\wrcal_dqs_cnt_r[2]_i_4_n_0 ), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(wrcal_sanity_chk_reg), .I4(\not_empty_wait_cnt_reg[0]_0 [1]), .I5(\not_empty_wait_cnt_reg[0]_0 [0]), .O(\wrcal_dqs_cnt_r[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair617" *) LUT5 #( .INIT(32'hCFFF8AAA)) \wrcal_dqs_cnt_r[2]_i_4 (.I0(prech_done), .I1(wrcal_dqs_cnt_r), .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .I3(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .I4(wrcal_done_reg_0), .O(\wrcal_dqs_cnt_r[2]_i_4_n_0 )); (* syn_maxfan = "10" *) FDRE \wrcal_dqs_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r[0]_i_1_n_0 ), .Q(\wrcal_dqs_cnt_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__6)); (* syn_maxfan = "10" *) FDRE \wrcal_dqs_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r[1]_i_1_n_0 ), .Q(\wrcal_dqs_cnt_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__6)); (* syn_maxfan = "10" *) FDRE \wrcal_dqs_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wrcal_dqs_cnt_r[2]_i_2_n_0 ), .Q(wrcal_dqs_cnt_r), .R(rstdiv0_sync_r1_reg_rep__6)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 " *) SRL16E wrcal_pat_resume_r2_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(wrcal_pat_resume_r), .Q(wrcal_pat_resume_r2_reg_srl2_n_0)); LUT6 #( .INIT(64'h08000800033C003C)) wrcal_pat_resume_r_i_2 (.I0(\cal2_state_r[3]_i_8_n_0 ), .I1(\not_empty_wait_cnt_reg[0]_0 [0]), .I2(\not_empty_wait_cnt_reg[0]_0 [3]), .I3(\not_empty_wait_cnt_reg[0]_0 [2]), .I4(wrcal_pat_resume_r_i_3_n_0), .I5(\not_empty_wait_cnt_reg[0]_0 [1]), .O(wrcal_pat_resume_r_reg_1)); LUT6 #( .INIT(64'h0000800000000000)) wrcal_pat_resume_r_i_3 (.I0(wrcal_pat_resume_r_reg_0), .I1(tap_inc_wait_cnt_reg__0[2]), .I2(tap_inc_wait_cnt_reg__0[0]), .I3(tap_inc_wait_cnt_reg__0[1]), .I4(wrcal_done_reg_0), .I5(tap_inc_wait_cnt_reg__0[3]), .O(wrcal_pat_resume_r_i_3_n_0)); FDRE wrcal_pat_resume_r_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[2]_0 ), .Q(wrcal_pat_resume_r), .R(rstdiv0_sync_r1_reg_rep__2)); FDRE wrcal_pat_resume_reg (.C(CLK), .CE(1'b1), .D(wrcal_pat_resume_r2_reg_srl2_n_0), .Q(wrcal_resume_w), .R(1'b0)); FDRE wrcal_prech_req_reg (.C(CLK), .CE(1'b1), .D(cal2_prech_req_r), .Q(wrcal_prech_req), .R(rstdiv0_sync_r1_reg_rep__6)); FDRE wrcal_sanity_chk_done_reg (.C(CLK), .CE(1'b1), .D(\cal2_state_r_reg[3]_0 ), .Q(wrcal_sanity_chk_done_reg_0), .R(rstdiv0_sync_r1_reg_rep__4)); FDRE wrcal_sanity_chk_r_reg (.C(CLK), .CE(1'b1), .D(wrcal_sanity_chk), .Q(wrcal_done_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair633" *) LUT3 #( .INIT(8'h1F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_1 (.I0(wrcal_done_reg_1), .I1(first_wrcal_pat_r), .I2(oclkdelay_calib_done_r_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] )); (* SOFT_HLUTNM = "soft_lutpair633" *) LUT3 #( .INIT(8'h7F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1 (.I0(wrcal_done_reg_1), .I1(oclkdelay_calib_done_r_reg), .I2(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] )); (* SOFT_HLUTNM = "soft_lutpair629" *) LUT2 #( .INIT(4'h7)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_1 (.I0(wrcal_done_reg_1), .I1(oclkdelay_calib_done_r_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] )); (* SOFT_HLUTNM = "soft_lutpair632" *) LUT3 #( .INIT(8'h2F)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_1 (.I0(wrcal_done_reg_1), .I1(rdlvl_stg1_done_int_reg), .I2(oclkdelay_calib_done_r_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] )); FDRE wrlvl_byte_done_r_reg (.C(CLK), .CE(1'b1), .D(wrlvl_byte_done), .Q(wrlvl_byte_done_r), .R(1'b0)); LUT6 #( .INIT(64'h0000000022222E22)) wrlvl_byte_redo_i_2 (.I0(wrlvl_byte_redo_i_3_n_0), .I1(\not_empty_wait_cnt_reg[0]_0 [1]), .I2(\not_empty_wait_cnt_reg[0]_0 [2]), .I3(wrlvl_byte_done), .I4(wrlvl_byte_done_r), .I5(\not_empty_wait_cnt_reg[0]_0 [3]), .O(wrlvl_byte_redo_reg_0)); LUT6 #( .INIT(64'h0000000000300020)) wrlvl_byte_redo_i_3 (.I0(early1_data_reg_0), .I1(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ), .I2(idelay_ld_reg_0), .I3(wrcal_done_reg_0), .I4(early2_data_reg_0), .I5(\not_empty_wait_cnt_reg[0]_0 [2]), .O(wrlvl_byte_redo_i_3_n_0)); FDRE wrlvl_byte_redo_reg (.C(CLK), .CE(1'b1), .D(\gen_pat_match_div4.early2_data_match_r_reg_0 ), .Q(wrlvl_byte_redo), .R(rstdiv0_sync_r1_reg_rep__6)); endmodule module ddr3_if_mig_7series_v4_0_ddr_phy_wrlvl (wr_level_done_r1_reg_0, wrlvl_byte_redo_r, wrlvl_final_r, dqs_po_dec_done, dqs_po_stg2_f_incdec, dqs_po_en_stg2_f, dqs_wl_po_stg2_c_incdec, \rd_data_edge_detect_r_reg[0]_0 , \FSM_sequential_wl_state_r_reg[0]_0 , p_0_in, \rd_data_edge_detect_r_reg[0]_1 , dqs_po_en_stg2_f_reg_0, wrlvl_done_r_reg, wrlvl_rank_done, D, \stg2_target_r_reg[4] , \stg2_r_reg[4] , \stg3_dec_val_reg[2] , \stg2_r_reg[5] , out, stable_cnt227_in, \stg3_dec_val_reg[2]_0 , \lim_state_reg[12] , \stg2_r_reg[0] , \po_rdval_cnt_reg[0]_0 , flag_ck_negedge09_out, \stable_cnt_reg[3]_0 , \rank_cnt_r_reg[0]_0 , \rank_cnt_r_reg[0]_1 , stable_cnt1, \wrlvl_redo_corse_inc_reg[2]_0 , po_cnt_dec_reg_0, flag_ck_negedge_reg_0, \gen_byte_sel_div1.byte_sel_cnt_reg[0] , \gen_byte_sel_div1.byte_sel_cnt_reg[1] , \gen_byte_sel_div1.byte_sel_cnt_reg[2] , p_1_in, wrlvl_byte_done, done_dqs_tap_inc, wr_level_done_r_reg_0, wrlvl_rank_done_r_reg_0, dq_cnt_inc_reg_0, inhibit_edge_detect_r, inhibit_edge_detect_r_reg_0, \mcGo_r_reg[15] , CLK, wrlvl_byte_redo, wrlvl_final_mux, wr_lvl_start_reg, rstdiv0_sync_r1_reg_rep__18, rstdiv0_sync_r1_reg_rep__15, flag_ck_negedge_reg_1, rstdiv0_sync_r1_reg_rep__16, \FSM_sequential_wl_state_r_reg[2]_0 , \FSM_sequential_wl_state_r_reg[0]_1 , \FSM_sequential_wl_state_r_reg[1]_0 , inhibit_edge_detect_r_reg_1, \wait_cnt_reg[0]_0 , \single_rank.done_dqs_dec_reg_0 , \FSM_sequential_wl_state_r_reg[2]_1 , S, \stg3_r_reg[5] , O, wl_sm_start, \byte_r_reg[0] , \byte_r_reg[1] , Q, \stg2_tap_cnt_reg[2] , \po_counter_read_val_reg[8] , \po_counter_read_val_reg[8]_0 , \calib_sel_reg[3] , \po_counter_read_val_reg[5] , rstdiv0_sync_r1_reg_rep__23, oclkdelay_calib_done_r_reg, \po_stg2_wrcal_cnt_reg[2] , early1_data_reg, early1_data_reg_0, rstdiv0_sync_r1_reg_rep__20, \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 , pi_f_inc_reg, oclkdelay_calib_done_r_reg_0, delay_done_r4_reg, \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 , oclkdelay_calib_done_r_reg_1, byte_sel_cnt, \prbs_dqs_cnt_r_reg[2] , rstdiv0_sync_r1_reg_rep__25, pi_fine_dly_dec_done, rstdiv0_sync_r1_reg_rep__17, rstdiv0_sync_r1_reg_rep, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , my_empty, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 , my_empty_6, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 , my_empty_7, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , my_empty_8, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 , po_cnt_dec_reg_1, rstdiv0_sync_r1_reg_rep__19, done_dqs_dec239_out, \po_stg2_wrcal_cnt_reg[0] , \po_stg2_wrcal_cnt_reg[2]_0 , \po_stg2_wrcal_cnt_reg[1] , wrlvl_byte_redo_reg); output wr_level_done_r1_reg_0; output wrlvl_byte_redo_r; output wrlvl_final_r; output dqs_po_dec_done; output dqs_po_stg2_f_incdec; output dqs_po_en_stg2_f; output dqs_wl_po_stg2_c_incdec; output \rd_data_edge_detect_r_reg[0]_0 ; output \FSM_sequential_wl_state_r_reg[0]_0 ; output p_0_in; output \rd_data_edge_detect_r_reg[0]_1 ; output dqs_po_en_stg2_f_reg_0; output wrlvl_done_r_reg; output wrlvl_rank_done; output [7:0]D; output [1:0]\stg2_target_r_reg[4] ; output \stg2_r_reg[4] ; output \stg3_dec_val_reg[2] ; output \stg2_r_reg[5] ; output [4:0]out; output stable_cnt227_in; output [2:0]\stg3_dec_val_reg[2]_0 ; output \lim_state_reg[12] ; output \stg2_r_reg[0] ; output \po_rdval_cnt_reg[0]_0 ; output flag_ck_negedge09_out; output [0:0]\stable_cnt_reg[3]_0 ; output \rank_cnt_r_reg[0]_0 ; output \rank_cnt_r_reg[0]_1 ; output stable_cnt1; output [1:0]\wrlvl_redo_corse_inc_reg[2]_0 ; output po_cnt_dec_reg_0; output flag_ck_negedge_reg_0; output \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; output \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; output p_1_in; output wrlvl_byte_done; output done_dqs_tap_inc; output wr_level_done_r_reg_0; output wrlvl_rank_done_r_reg_0; output dq_cnt_inc_reg_0; output inhibit_edge_detect_r; output inhibit_edge_detect_r_reg_0; input \mcGo_r_reg[15] ; input CLK; input wrlvl_byte_redo; input wrlvl_final_mux; input wr_lvl_start_reg; input [0:0]rstdiv0_sync_r1_reg_rep__18; input [0:0]rstdiv0_sync_r1_reg_rep__15; input flag_ck_negedge_reg_1; input [0:0]rstdiv0_sync_r1_reg_rep__16; input \FSM_sequential_wl_state_r_reg[2]_0 ; input \FSM_sequential_wl_state_r_reg[0]_1 ; input \FSM_sequential_wl_state_r_reg[1]_0 ; input inhibit_edge_detect_r_reg_1; input \wait_cnt_reg[0]_0 ; input \single_rank.done_dqs_dec_reg_0 ; input \FSM_sequential_wl_state_r_reg[2]_1 ; input [0:0]S; input [2:0]\stg3_r_reg[5] ; input [3:0]O; input wl_sm_start; input \byte_r_reg[0] ; input \byte_r_reg[1] ; input [2:0]Q; input [2:0]\stg2_tap_cnt_reg[2] ; input [4:0]\po_counter_read_val_reg[8] ; input [4:0]\po_counter_read_val_reg[8]_0 ; input [0:0]\calib_sel_reg[3] ; input [3:0]\po_counter_read_val_reg[5] ; input rstdiv0_sync_r1_reg_rep__23; input oclkdelay_calib_done_r_reg; input [2:0]\po_stg2_wrcal_cnt_reg[2] ; input early1_data_reg; input early1_data_reg_0; input rstdiv0_sync_r1_reg_rep__20; input \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; input pi_f_inc_reg; input oclkdelay_calib_done_r_reg_0; input delay_done_r4_reg; input \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; input oclkdelay_calib_done_r_reg_1; input [0:0]byte_sel_cnt; input \prbs_dqs_cnt_r_reg[2] ; input rstdiv0_sync_r1_reg_rep__25; input pi_fine_dly_dec_done; input [0:0]rstdiv0_sync_r1_reg_rep__17; input rstdiv0_sync_r1_reg_rep; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [0:0]my_empty; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; input [0:0]my_empty_6; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; input [0:0]my_empty_7; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [0:0]my_empty_8; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; input [0:0]po_cnt_dec_reg_1; input [0:0]rstdiv0_sync_r1_reg_rep__19; input done_dqs_dec239_out; input \po_stg2_wrcal_cnt_reg[0] ; input \po_stg2_wrcal_cnt_reg[2]_0 ; input \po_stg2_wrcal_cnt_reg[1] ; input wrlvl_byte_redo_reg; wire CLK; wire [7:0]D; wire \FSM_sequential_wl_state_r[0]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_13_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_14_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_15_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_16_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_4_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[0]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_4_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[1]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_12_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_13_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_14_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_15_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[2]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_4_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_6_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[3]_i_9_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_10_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_11_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_12_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_1_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_2_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_3_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_5_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_7_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_8_n_0 ; wire \FSM_sequential_wl_state_r[4]_i_9_n_0 ; wire \FSM_sequential_wl_state_r_reg[0]_0 ; wire \FSM_sequential_wl_state_r_reg[0]_1 ; wire \FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ; wire \FSM_sequential_wl_state_r_reg[1]_0 ; wire \FSM_sequential_wl_state_r_reg[2]_0 ; wire \FSM_sequential_wl_state_r_reg[2]_1 ; wire \FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ; wire \FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ; wire [3:0]O; wire [2:0]Q; wire [0:0]S; wire \byte_r_reg[0] ; wire \byte_r_reg[1] ; wire [0:0]byte_sel_cnt; wire [0:0]\calib_sel_reg[3] ; wire [2:0]corse_cnt; wire \corse_cnt[0][0]_i_1_n_0 ; wire \corse_cnt[0][0]_i_3_n_0 ; wire \corse_cnt[0][0]_i_4_n_0 ; wire \corse_cnt[0][1]_i_1_n_0 ; wire \corse_cnt[0][1]_i_3_n_0 ; wire \corse_cnt[0][1]_i_4_n_0 ; wire \corse_cnt[0][1]_i_5_n_0 ; wire \corse_cnt[0][2]_i_10_n_0 ; wire \corse_cnt[0][2]_i_1_n_0 ; wire \corse_cnt[0][2]_i_3_n_0 ; wire \corse_cnt[0][2]_i_4_n_0 ; wire \corse_cnt[0][2]_i_5_n_0 ; wire \corse_cnt[0][2]_i_6_n_0 ; wire \corse_cnt[0][2]_i_7_n_0 ; wire \corse_cnt[0][2]_i_8_n_0 ; wire \corse_cnt[0][2]_i_9_n_0 ; wire \corse_cnt[1][0]_i_1_n_0 ; wire \corse_cnt[1][1]_i_1_n_0 ; wire \corse_cnt[1][2]_i_1_n_0 ; wire \corse_cnt[1][2]_i_2_n_0 ; wire \corse_cnt[1][2]_i_3_n_0 ; wire \corse_cnt[1][2]_i_4_n_0 ; wire \corse_cnt[2][0]_i_1_n_0 ; wire \corse_cnt[2][1]_i_1_n_0 ; wire \corse_cnt[2][2]_i_1_n_0 ; wire \corse_cnt[2][2]_i_2_n_0 ; wire \corse_cnt[2][2]_i_3_n_0 ; wire \corse_cnt[2][2]_i_4_n_0 ; wire \corse_cnt[3][0]_i_1_n_0 ; wire \corse_cnt[3][1]_i_1_n_0 ; wire \corse_cnt[3][2]_i_1_n_0 ; wire \corse_cnt[3][2]_i_2_n_0 ; wire \corse_cnt[3][2]_i_3_n_0 ; wire \corse_cnt[3][2]_i_4_n_0 ; wire \corse_cnt_reg_n_0_[0][0] ; wire \corse_cnt_reg_n_0_[0][1] ; wire \corse_cnt_reg_n_0_[0][2] ; wire \corse_cnt_reg_n_0_[1][0] ; wire \corse_cnt_reg_n_0_[1][1] ; wire \corse_cnt_reg_n_0_[1][2] ; wire \corse_cnt_reg_n_0_[2][0] ; wire \corse_cnt_reg_n_0_[2][1] ; wire \corse_cnt_reg_n_0_[2][2] ; wire \corse_cnt_reg_n_0_[3][0] ; wire \corse_cnt_reg_n_0_[3][1] ; wire \corse_cnt_reg_n_0_[3][2] ; wire \corse_dec[0][0]_i_1_n_0 ; wire \corse_dec[0][1]_i_1_n_0 ; wire \corse_dec[0][2]_i_1_n_0 ; wire \corse_dec[0][2]_i_2_n_0 ; wire \corse_dec[1][0]_i_1_n_0 ; wire \corse_dec[1][1]_i_1_n_0 ; wire \corse_dec[1][2]_i_1_n_0 ; wire \corse_dec[1][2]_i_2_n_0 ; wire \corse_dec[2][0]_i_1_n_0 ; wire \corse_dec[2][1]_i_1_n_0 ; wire \corse_dec[2][2]_i_1_n_0 ; wire \corse_dec[2][2]_i_2_n_0 ; wire \corse_dec[3][0]_i_1_n_0 ; wire \corse_dec[3][1]_i_1_n_0 ; wire \corse_dec[3][2]_i_1_n_0 ; wire \corse_dec[3][2]_i_2_n_0 ; wire \corse_dec[3][2]_i_3_n_0 ; wire \corse_dec[3][2]_i_4_n_0 ; wire \corse_dec[3][2]_i_5_n_0 ; wire \corse_dec_reg_n_0_[0][0] ; wire \corse_dec_reg_n_0_[0][1] ; wire \corse_dec_reg_n_0_[0][2] ; wire \corse_dec_reg_n_0_[1][0] ; wire \corse_dec_reg_n_0_[1][1] ; wire \corse_dec_reg_n_0_[1][2] ; wire \corse_dec_reg_n_0_[2][0] ; wire \corse_dec_reg_n_0_[2][1] ; wire \corse_dec_reg_n_0_[2][2] ; wire \corse_dec_reg_n_0_[3][0] ; wire \corse_dec_reg_n_0_[3][1] ; wire \corse_dec_reg_n_0_[3][2] ; wire \corse_inc[0][0]_i_1_n_0 ; wire \corse_inc[0][1]_i_1_n_0 ; wire \corse_inc[0][2]_i_1_n_0 ; wire \corse_inc[0][2]_i_2_n_0 ; wire \corse_inc[0][2]_i_3_n_0 ; wire \corse_inc[1][0]_i_1_n_0 ; wire \corse_inc[1][1]_i_1_n_0 ; wire \corse_inc[1][2]_i_1_n_0 ; wire \corse_inc[1][2]_i_2_n_0 ; wire \corse_inc[1][2]_i_3_n_0 ; wire \corse_inc[2][0]_i_1_n_0 ; wire \corse_inc[2][1]_i_1_n_0 ; wire \corse_inc[2][2]_i_1_n_0 ; wire \corse_inc[2][2]_i_2_n_0 ; wire \corse_inc[2][2]_i_3_n_0 ; wire \corse_inc[3][0]_i_1_n_0 ; wire \corse_inc[3][0]_i_2_n_0 ; wire \corse_inc[3][1]_i_1_n_0 ; wire \corse_inc[3][1]_i_2_n_0 ; wire \corse_inc[3][2]_i_1_n_0 ; wire \corse_inc[3][2]_i_2_n_0 ; wire \corse_inc[3][2]_i_3_n_0 ; wire \corse_inc[3][2]_i_4_n_0 ; wire \corse_inc[3][2]_i_5_n_0 ; wire \corse_inc[3][2]_i_6_n_0 ; wire \corse_inc[3][2]_i_7_n_0 ; wire \corse_inc_reg_n_0_[0][0] ; wire \corse_inc_reg_n_0_[0][1] ; wire \corse_inc_reg_n_0_[0][2] ; wire \corse_inc_reg_n_0_[1][0] ; wire \corse_inc_reg_n_0_[1][1] ; wire \corse_inc_reg_n_0_[1][2] ; wire \corse_inc_reg_n_0_[2][0] ; wire \corse_inc_reg_n_0_[2][1] ; wire \corse_inc_reg_n_0_[2][2] ; wire \corse_inc_reg_n_0_[3][0] ; wire \corse_inc_reg_n_0_[3][1] ; wire \corse_inc_reg_n_0_[3][2] ; wire delay_done_r4_reg; wire done_dqs_dec; wire done_dqs_dec239_out; wire done_dqs_tap_inc; wire dq_cnt_inc_reg_0; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ; wire [2:0]dqs_count_r; wire dqs_count_r140_out; wire \dqs_count_r[0]_i_1_n_0 ; wire \dqs_count_r[0]_i_4_n_0 ; wire \dqs_count_r[0]_i_5_n_0 ; wire \dqs_count_r[0]_i_6_n_0 ; wire \dqs_count_r[0]_i_7_n_0 ; wire \dqs_count_r[0]_i_8_n_0 ; wire \dqs_count_r[1]_i_1_n_0 ; wire \dqs_count_r[1]_i_4_n_0 ; wire \dqs_count_r[1]_i_5_n_0 ; wire \dqs_count_r[1]_i_6_n_0 ; wire \dqs_count_r[1]_i_7_n_0 ; wire \dqs_count_r[1]_i_8_n_0 ; wire \dqs_count_r[2]_i_10_n_0 ; wire \dqs_count_r[2]_i_11_n_0 ; wire \dqs_count_r[2]_i_2_n_0 ; wire \dqs_count_r[2]_i_5_n_0 ; wire \dqs_count_r[2]_i_6_n_0 ; wire \dqs_count_r[2]_i_7_n_0 ; wire \dqs_count_r[2]_i_8_n_0 ; wire \dqs_count_r[2]_i_9_n_0 ; wire \dqs_count_r_reg[0]_i_2_n_0 ; wire \dqs_count_r_reg[0]_i_3_n_0 ; wire \dqs_count_r_reg[0]_rep_n_0 ; wire \dqs_count_r_reg[1]_i_2_n_0 ; wire \dqs_count_r_reg[1]_i_3_n_0 ; wire \dqs_count_r_reg[1]_rep_n_0 ; wire \dqs_count_r_reg[2]_i_3_n_0 ; wire \dqs_count_r_reg[2]_i_4_n_0 ; wire dqs_po_dec_done; wire dqs_po_en_stg2_f; wire dqs_po_en_stg2_f_i_1_n_0; wire dqs_po_en_stg2_f_reg_0; wire dqs_po_stg2_f_incdec; wire dqs_po_stg2_f_incdec0; wire dqs_po_stg2_f_incdec_i_2_n_0; wire dqs_po_stg2_f_incdec_i_3_n_0; wire dqs_wl_po_stg2_c_incdec; wire dqs_wl_po_stg2_c_incdec_i_1_n_0; wire early1_data_reg; wire early1_data_reg_0; wire [0:0]final_coarse_tap; wire \final_coarse_tap_reg_n_0_[0][0] ; wire \final_coarse_tap_reg_n_0_[0][1] ; wire \final_coarse_tap_reg_n_0_[0][2] ; wire \final_coarse_tap_reg_n_0_[1][0] ; wire \final_coarse_tap_reg_n_0_[1][1] ; wire \final_coarse_tap_reg_n_0_[1][2] ; wire \final_coarse_tap_reg_n_0_[2][0] ; wire \final_coarse_tap_reg_n_0_[2][1] ; wire \final_coarse_tap_reg_n_0_[2][2] ; wire \final_coarse_tap_reg_n_0_[3][0] ; wire \final_coarse_tap_reg_n_0_[3][1] ; wire \final_coarse_tap_reg_n_0_[3][2] ; wire [5:0]fine_dec_cnt; wire \fine_dec_cnt[1]_i_2_n_0 ; wire \fine_dec_cnt[2]_i_2_n_0 ; wire \fine_dec_cnt[3]_i_2_n_0 ; wire \fine_dec_cnt[4]_i_2_n_0 ; wire \fine_dec_cnt[5]_i_3_n_0 ; wire \fine_dec_cnt[5]_i_4_n_0 ; wire \fine_dec_cnt[5]_i_5_n_0 ; wire \fine_dec_cnt[5]_i_6_n_0 ; wire \fine_dec_cnt[5]_i_7_n_0 ; wire \fine_dec_cnt[5]_i_8_n_0 ; wire [5:0]fine_dec_cnt__0; wire \fine_dec_cnt_reg[5]_i_1_n_0 ; wire [5:0]fine_inc; wire \fine_inc[0][5]_i_1_n_0 ; wire \fine_inc[0][5]_i_3_n_0 ; wire \fine_inc[1][0]_i_1_n_0 ; wire \fine_inc[1][1]_i_1_n_0 ; wire \fine_inc[1][2]_i_1_n_0 ; wire \fine_inc[1][3]_i_1_n_0 ; wire \fine_inc[1][4]_i_1_n_0 ; wire \fine_inc[1][5]_i_1_n_0 ; wire \fine_inc[1][5]_i_2_n_0 ; wire \fine_inc[1][5]_i_3_n_0 ; wire \fine_inc[2][0]_i_1_n_0 ; wire \fine_inc[2][1]_i_1_n_0 ; wire \fine_inc[2][2]_i_1_n_0 ; wire \fine_inc[2][3]_i_1_n_0 ; wire \fine_inc[2][4]_i_1_n_0 ; wire \fine_inc[2][5]_i_1_n_0 ; wire \fine_inc[2][5]_i_2_n_0 ; wire \fine_inc[2][5]_i_3_n_0 ; wire \fine_inc[3][0]_i_1_n_0 ; wire \fine_inc[3][1]_i_1_n_0 ; wire \fine_inc[3][2]_i_1_n_0 ; wire \fine_inc[3][2]_i_2_n_0 ; wire \fine_inc[3][2]_i_3_n_0 ; wire \fine_inc[3][2]_i_4_n_0 ; wire \fine_inc[3][3]_i_1_n_0 ; wire \fine_inc[3][4]_i_1_n_0 ; wire \fine_inc[3][4]_i_2_n_0 ; wire \fine_inc[3][4]_i_3_n_0 ; wire \fine_inc[3][4]_i_4_n_0 ; wire \fine_inc[3][5]_i_1_n_0 ; wire \fine_inc[3][5]_i_2_n_0 ; wire \fine_inc[3][5]_i_3_n_0 ; wire \fine_inc[3][5]_i_5_n_0 ; wire \fine_inc[3][5]_i_6_n_0 ; wire \fine_inc[3][5]_i_7_n_0 ; wire \fine_inc[3][5]_i_8_n_0 ; wire \fine_inc_reg_n_0_[0][0] ; wire \fine_inc_reg_n_0_[0][1] ; wire \fine_inc_reg_n_0_[0][2] ; wire \fine_inc_reg_n_0_[0][3] ; wire \fine_inc_reg_n_0_[0][4] ; wire \fine_inc_reg_n_0_[0][5] ; wire \fine_inc_reg_n_0_[1][0] ; wire \fine_inc_reg_n_0_[1][1] ; wire \fine_inc_reg_n_0_[1][2] ; wire \fine_inc_reg_n_0_[1][3] ; wire \fine_inc_reg_n_0_[1][4] ; wire \fine_inc_reg_n_0_[1][5] ; wire \fine_inc_reg_n_0_[2][0] ; wire \fine_inc_reg_n_0_[2][1] ; wire \fine_inc_reg_n_0_[2][2] ; wire \fine_inc_reg_n_0_[2][3] ; wire \fine_inc_reg_n_0_[2][4] ; wire \fine_inc_reg_n_0_[2][5] ; wire \fine_inc_reg_n_0_[3][0] ; wire \fine_inc_reg_n_0_[3][1] ; wire \fine_inc_reg_n_0_[3][2] ; wire \fine_inc_reg_n_0_[3][3] ; wire \fine_inc_reg_n_0_[3][4] ; wire \fine_inc_reg_n_0_[3][5] ; wire flag_ck_negedge09_out; wire flag_ck_negedge_i_10_n_0; wire flag_ck_negedge_i_6_n_0; wire flag_ck_negedge_i_7_n_0; wire flag_ck_negedge_i_8_n_0; wire flag_ck_negedge_reg_0; wire flag_ck_negedge_reg_1; wire flag_init; wire flag_init_i_1_n_0; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ; wire \gen_byte_sel_div1.byte_sel_cnt_reg[2] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][0] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][1] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][2] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][3] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][4] ; wire \gen_final_tap[0].final_val_reg_n_0_[0][5] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][0] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][1] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][2] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][3] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][4] ; wire \gen_final_tap[1].final_val_reg_n_0_[1][5] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][0] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][1] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][2] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][3] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][4] ; wire \gen_final_tap[2].final_val_reg_n_0_[2][5] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][0] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][1] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][2] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][3] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][4] ; wire \gen_final_tap[3].final_val_reg_n_0_[3][5] ; wire \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ; wire \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ; wire \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ; wire \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ; wire \incdec_wait_cnt[3]_i_1_n_0 ; wire [3:0]incdec_wait_cnt_reg__0; wire inhibit_edge_detect_r; wire inhibit_edge_detect_r_i_4_n_0; wire inhibit_edge_detect_r_reg_0; wire inhibit_edge_detect_r_reg_1; wire [5:0]largest; wire \lim_state_reg[12] ; wire \mcGo_r_reg[15] ; wire [0:0]my_empty; wire [0:0]my_empty_6; wire [0:0]my_empty_7; wire [0:0]my_empty_8; wire [5:3]\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 ; wire oclkdelay_calib_done_r_reg; wire oclkdelay_calib_done_r_reg_0; wire oclkdelay_calib_done_r_reg_1; (* RTL_KEEP = "yes" *) wire [4:0]out; wire p_0_in; wire p_0_in32_in; wire [3:0]p_0_in__0; wire [3:0]p_0_in__0__0; wire \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ; wire \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ; wire \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ; wire \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ; wire \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ; wire \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ; wire \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ; wire \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ; wire p_1_in; wire p_1_in1_in; wire p_1_in28_in; wire p_1_in_0; wire p_21_out; wire phy_ctl_ready_r4_reg_srl4_n_0; wire phy_ctl_ready_r5; wire phy_ctl_ready_r6_reg_n_0; wire pi_f_inc_reg; wire pi_fine_dly_dec_done; wire po_cnt_dec_reg_0; wire [0:0]po_cnt_dec_reg_1; wire [3:0]\po_counter_read_val_reg[5] ; wire [4:0]\po_counter_read_val_reg[8] ; wire [4:0]\po_counter_read_val_reg[8]_0 ; wire po_dec_done; wire po_dec_done_i_1_n_0; wire po_dec_done_i_2_n_0; wire po_dec_done_i_3_n_0; wire [8:0]po_rdval_cnt; wire \po_rdval_cnt[0]_i_1_n_0 ; wire \po_rdval_cnt[1]_i_1_n_0 ; wire \po_rdval_cnt[2]_i_1_n_0 ; wire \po_rdval_cnt[3]_i_1_n_0 ; wire \po_rdval_cnt[4]_i_1_n_0 ; wire \po_rdval_cnt[4]_i_2_n_0 ; wire \po_rdval_cnt[5]_i_1_n_0 ; wire \po_rdval_cnt[5]_i_2_n_0 ; wire \po_rdval_cnt[6]_i_1_n_0 ; wire \po_rdval_cnt[6]_i_2_n_0 ; wire \po_rdval_cnt[7]_i_1_n_0 ; wire \po_rdval_cnt[7]_i_2_n_0 ; wire \po_rdval_cnt[8]_i_1_n_0 ; wire \po_rdval_cnt[8]_i_2_n_0 ; wire \po_rdval_cnt[8]_i_4_n_0 ; wire \po_rdval_cnt[8]_i_5_n_0 ; wire \po_rdval_cnt[8]_i_6_n_0 ; wire \po_rdval_cnt[8]_i_7_n_0 ; wire \po_rdval_cnt_reg[0]_0 ; wire \po_stg2_wrcal_cnt_reg[0] ; wire \po_stg2_wrcal_cnt_reg[1] ; wire [2:0]\po_stg2_wrcal_cnt_reg[2] ; wire \po_stg2_wrcal_cnt_reg[2]_0 ; wire \prbs_dqs_cnt_r_reg[2] ; wire rank_cnt_r; wire \rank_cnt_r[0]_i_1_n_0 ; wire \rank_cnt_r[1]_i_1_n_0 ; wire \rank_cnt_r_reg[0]_0 ; wire \rank_cnt_r_reg[0]_1 ; wire rd_data_edge_detect_r0; wire \rd_data_edge_detect_r[0]_i_1_n_0 ; wire \rd_data_edge_detect_r[1]_i_1_n_0 ; wire \rd_data_edge_detect_r[2]_i_1_n_0 ; wire \rd_data_edge_detect_r[3]_i_2_n_0 ; wire \rd_data_edge_detect_r[3]_i_3_n_0 ; wire \rd_data_edge_detect_r[3]_i_4_n_0 ; wire \rd_data_edge_detect_r[3]_i_5_n_0 ; wire \rd_data_edge_detect_r[3]_i_6_n_0 ; wire \rd_data_edge_detect_r_reg[0]_0 ; wire \rd_data_edge_detect_r_reg[0]_1 ; wire \rd_data_edge_detect_r_reg_n_0_[0] ; wire \rd_data_edge_detect_r_reg_n_0_[1] ; wire \rd_data_edge_detect_r_reg_n_0_[2] ; wire \rd_data_edge_detect_r_reg_n_0_[3] ; wire rd_data_previous_r0; wire \rd_data_previous_r[3]_i_2_n_0 ; wire \rd_data_previous_r[3]_i_3_n_0 ; wire \rd_data_previous_r[3]_i_4_n_0 ; wire \rd_data_previous_r_reg_n_0_[0] ; wire \rd_data_previous_r_reg_n_0_[1] ; wire \rd_data_previous_r_reg_n_0_[2] ; wire \rd_data_previous_r_reg_n_0_[3] ; wire rstdiv0_sync_r1_reg_rep; wire [0:0]rstdiv0_sync_r1_reg_rep__15; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [0:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__25; wire \single_rank.done_dqs_dec_i_1_n_0 ; wire \single_rank.done_dqs_dec_reg_0 ; wire \smallest[0][0]_i_2_n_0 ; wire \smallest[0][1]_i_2_n_0 ; wire \smallest[0][2]_i_2_n_0 ; wire \smallest[0][3]_i_2_n_0 ; wire \smallest[0][4]_i_2_n_0 ; wire \smallest[0][5]_i_2_n_0 ; wire \smallest[0][5]_i_4_n_0 ; wire \smallest[0][5]_i_5_n_0 ; wire \smallest[1][0]_i_1_n_0 ; wire \smallest[1][1]_i_1_n_0 ; wire \smallest[1][2]_i_1_n_0 ; wire \smallest[1][3]_i_1_n_0 ; wire \smallest[1][4]_i_1_n_0 ; wire \smallest[1][5]_i_1_n_0 ; wire \smallest[1][5]_i_2_n_0 ; wire \smallest[2][0]_i_1_n_0 ; wire \smallest[2][1]_i_1_n_0 ; wire \smallest[2][2]_i_1_n_0 ; wire \smallest[2][3]_i_1_n_0 ; wire \smallest[2][4]_i_1_n_0 ; wire \smallest[2][5]_i_1_n_0 ; wire \smallest[2][5]_i_2_n_0 ; wire \smallest[3][0]_i_1_n_0 ; wire \smallest[3][1]_i_1_n_0 ; wire \smallest[3][2]_i_1_n_0 ; wire \smallest[3][3]_i_1_n_0 ; wire \smallest[3][4]_i_1_n_0 ; wire \smallest[3][5]_i_1_n_0 ; wire \smallest[3][5]_i_2_n_0 ; wire [5:0]\smallest_reg[0]__0 ; wire [5:0]\smallest_reg[1]__0 ; wire [5:0]\smallest_reg[2]__0 ; wire [5:0]\smallest_reg[3]__0 ; wire stable_cnt; wire stable_cnt0; wire stable_cnt1; wire stable_cnt227_in; wire \stable_cnt[3]_i_4_n_0 ; wire \stable_cnt[3]_i_6_n_0 ; wire \stable_cnt[3]_i_7_n_0 ; wire [0:0]\stable_cnt_reg[3]_0 ; wire \stable_cnt_reg_n_0_[1] ; wire \stable_cnt_reg_n_0_[2] ; wire \stable_cnt_reg_n_0_[3] ; wire \stg2_r_reg[0] ; wire \stg2_r_reg[4] ; wire \stg2_r_reg[5] ; wire \stg2_tap_cnt[3]_i_4_n_0 ; wire [2:0]\stg2_tap_cnt_reg[2] ; wire \stg2_target_r[4]_i_4_n_0 ; wire \stg2_target_r[4]_i_5_n_0 ; wire \stg2_target_r[8]_i_6_n_0 ; wire [1:0]\stg2_target_r_reg[4] ; wire \stg2_target_r_reg[4]_i_1_n_0 ; wire \stg2_target_r_reg[4]_i_1_n_1 ; wire \stg2_target_r_reg[4]_i_1_n_2 ; wire \stg2_target_r_reg[4]_i_1_n_3 ; wire \stg2_target_r_reg[8]_i_1_n_1 ; wire \stg2_target_r_reg[8]_i_1_n_2 ; wire \stg2_target_r_reg[8]_i_1_n_3 ; wire \stg3_dec_val_reg[2] ; wire [2:0]\stg3_dec_val_reg[2]_0 ; wire [2:0]\stg3_r_reg[5] ; wire \u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ; wire wait_cnt0; wire [3:0]wait_cnt0__0; wire \wait_cnt[1]_i_1_n_0 ; wire \wait_cnt_reg[0]_0 ; wire [3:0]wait_cnt_reg__0; wire wl_corse_cnt; wire \wl_corse_cnt[0][0][0]_i_1_n_0 ; wire \wl_corse_cnt[0][0][1]_i_1_n_0 ; wire \wl_corse_cnt[0][0][2]_i_2_n_0 ; wire \wl_corse_cnt[0][0][2]_i_3_n_0 ; wire \wl_corse_cnt[0][0][2]_i_4_n_0 ; wire \wl_corse_cnt[0][1][2]_i_1_n_0 ; wire \wl_corse_cnt[0][2][2]_i_1_n_0 ; wire \wl_corse_cnt[0][3][2]_i_1_n_0 ; wire [2:0]\wl_corse_cnt_reg[0][0]__0 ; wire [2:0]\wl_corse_cnt_reg[0][1]__0 ; wire [2:0]\wl_corse_cnt_reg[0][2]__0 ; wire [2:0]\wl_corse_cnt_reg[0][3]__0 ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][0][5] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][1][5] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][2][5] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][0] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][1] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][2] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][3] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][4] ; wire \wl_dqs_tap_count_r_reg_n_0_[0][3][5] ; wire [23:0]wl_po_fine_cnt; wire wl_sm_start; wire wl_state_r1; wire \wl_state_r1[0]_i_1_n_0 ; wire \wl_state_r1[1]_i_1_n_0 ; wire \wl_state_r1[2]_i_1_n_0 ; wire \wl_state_r1[3]_i_1_n_0 ; wire \wl_state_r1[4]_i_1_n_0 ; wire \wl_state_r1_reg_n_0_[0] ; wire \wl_state_r1_reg_n_0_[1] ; wire \wl_state_r1_reg_n_0_[2] ; wire \wl_state_r1_reg_n_0_[3] ; wire \wl_state_r1_reg_n_0_[4] ; wire [5:0]wl_tap_count_r; wire \wl_tap_count_r[0]_i_2_n_0 ; wire \wl_tap_count_r[0]_i_3_n_0 ; wire \wl_tap_count_r[1]_i_2_n_0 ; wire \wl_tap_count_r[1]_i_3_n_0 ; wire \wl_tap_count_r[1]_i_4_n_0 ; wire \wl_tap_count_r[2]_i_2_n_0 ; wire \wl_tap_count_r[2]_i_3_n_0 ; wire \wl_tap_count_r[2]_i_4_n_0 ; wire \wl_tap_count_r[3]_i_2_n_0 ; wire \wl_tap_count_r[3]_i_3_n_0 ; wire \wl_tap_count_r[3]_i_4_n_0 ; wire \wl_tap_count_r[4]_i_2_n_0 ; wire \wl_tap_count_r[4]_i_3_n_0 ; wire \wl_tap_count_r[4]_i_4_n_0 ; wire \wl_tap_count_r[5]_i_1_n_0 ; wire \wl_tap_count_r[5]_i_4_n_0 ; wire \wl_tap_count_r[5]_i_5_n_0 ; wire \wl_tap_count_r[5]_i_6_n_0 ; wire \wl_tap_count_r_reg_n_0_[0] ; wire \wl_tap_count_r_reg_n_0_[1] ; wire \wl_tap_count_r_reg_n_0_[2] ; wire \wl_tap_count_r_reg_n_0_[3] ; wire \wl_tap_count_r_reg_n_0_[4] ; wire \wl_tap_count_r_reg_n_0_[5] ; wire wr_level_done0; wire wr_level_done_r1; wire wr_level_done_r1_reg_0; wire wr_level_done_r2; wire wr_level_done_r3; wire wr_level_done_r4; wire wr_level_done_r5; wire wr_level_done_r_reg_0; wire wr_level_start_r; wire wr_lvl_start_reg; wire wrlvl_byte_done; wire wrlvl_byte_done_i_1_n_0; wire wrlvl_byte_redo; wire wrlvl_byte_redo_r; wire wrlvl_byte_redo_reg; wire wrlvl_done_r_reg; wire wrlvl_final_mux; wire wrlvl_final_r; wire wrlvl_rank_done; wire wrlvl_rank_done_r_reg_0; wire \wrlvl_redo_corse_inc[0]_i_1_n_0 ; wire \wrlvl_redo_corse_inc[1]_i_1_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_1_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_2_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_3_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_4_n_0 ; wire \wrlvl_redo_corse_inc[2]_i_7_n_0 ; wire [2:0]wrlvl_redo_corse_inc__0; wire [1:0]\wrlvl_redo_corse_inc_reg[2]_0 ; wire [0:0]\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED ; wire [3:3]\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED ; LUT6 #( .INIT(64'hFFFFFFBF00000000)) \FSM_sequential_wl_state_r[0]_i_1 (.I0(\FSM_sequential_wl_state_r[0]_i_2_n_0 ), .I1(out[4]), .I2(\FSM_sequential_wl_state_r_reg[0]_0 ), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[0]_i_3_n_0 ), .I5(\FSM_sequential_wl_state_r[0]_i_4_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hEEAEEEAEEEAEEFAF)) \FSM_sequential_wl_state_r[0]_i_10 (.I0(out[4]), .I1(out[3]), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I4(stable_cnt227_in), .I5(stable_cnt1), .O(\FSM_sequential_wl_state_r[0]_i_10_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_sequential_wl_state_r[0]_i_11 (.I0(out[3]), .I1(out[0]), .O(\FSM_sequential_wl_state_r[0]_i_11_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_sequential_wl_state_r[0]_i_13 (.I0(p_0_in), .I1(out[3]), .O(\FSM_sequential_wl_state_r[0]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair347" *) LUT3 #( .INIT(8'hF4)) \FSM_sequential_wl_state_r[0]_i_14 (.I0(wr_level_done_r5), .I1(wl_sm_start), .I2(wrlvl_byte_redo), .O(\FSM_sequential_wl_state_r[0]_i_14_n_0 )); LUT5 #( .INIT(32'hFC7FFC7C)) \FSM_sequential_wl_state_r[0]_i_15 (.I0(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I1(out[1]), .I2(out[3]), .I3(out[4]), .I4(wl_state_r1), .O(\FSM_sequential_wl_state_r[0]_i_15_n_0 )); LUT6 #( .INIT(64'h3434343430333030)) \FSM_sequential_wl_state_r[0]_i_16 (.I0(wr_level_done_r5), .I1(out[1]), .I2(out[4]), .I3(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I4(wrlvl_byte_redo), .I5(out[3]), .O(\FSM_sequential_wl_state_r[0]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair347" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_wl_state_r[0]_i_17 (.I0(wr_level_start_r), .I1(wl_sm_start), .I2(wr_level_done_r1_reg_0), .O(wl_state_r1)); LUT4 #( .INIT(16'hFFFE)) \FSM_sequential_wl_state_r[0]_i_2 (.I0(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I1(out[0]), .I2(\FSM_sequential_wl_state_r[0]_i_5_n_0 ), .I3(out[2]), .O(\FSM_sequential_wl_state_r[0]_i_2_n_0 )); LUT3 #( .INIT(8'h7F)) \FSM_sequential_wl_state_r[0]_i_3 (.I0(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .I1(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I2(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAEAAAAAA)) \FSM_sequential_wl_state_r[0]_i_4 (.I0(\FSM_sequential_wl_state_r[0]_i_6_n_0 ), .I1(out[2]), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[3]_i_7_n_0 ), .I4(out[3]), .I5(\FSM_sequential_wl_state_r[0]_i_7_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair313" *) LUT3 #( .INIT(8'h7F)) \FSM_sequential_wl_state_r[0]_i_5 (.I0(\wl_tap_count_r_reg_n_0_[5] ), .I1(\wl_tap_count_r_reg_n_0_[4] ), .I2(\wl_tap_count_r_reg_n_0_[3] ), .O(\FSM_sequential_wl_state_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'hEA00000000000000)) \FSM_sequential_wl_state_r[0]_i_6 (.I0(out[2]), .I1(out[3]), .I2(p_0_in), .I3(out[4]), .I4(\FSM_sequential_wl_state_r[0]_i_8_n_0 ), .I5(\FSM_sequential_wl_state_r[0]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_6_n_0 )); LUT6 #( .INIT(64'hB888FFFFB8880000)) \FSM_sequential_wl_state_r[0]_i_7 (.I0(\FSM_sequential_wl_state_r[0]_i_10_n_0 ), .I1(out[1]), .I2(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I3(\FSM_sequential_wl_state_r[0]_i_11_n_0 ), .I4(out[2]), .I5(\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ), .O(\FSM_sequential_wl_state_r[0]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFF7FFFFFFFF)) \FSM_sequential_wl_state_r[0]_i_8 (.I0(out[0]), .I1(dqs_count_r[0]), .I2(dqs_count_r[2]), .I3(\FSM_sequential_wl_state_r[0]_i_13_n_0 ), .I4(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I5(dqs_count_r[1]), .O(\FSM_sequential_wl_state_r[0]_i_8_n_0 )); LUT5 #( .INIT(32'hFF5D5D5D)) \FSM_sequential_wl_state_r[0]_i_9 (.I0(out[0]), .I1(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I2(\FSM_sequential_wl_state_r[0]_i_14_n_0 ), .I3(p_0_in), .I4(out[3]), .O(\FSM_sequential_wl_state_r[0]_i_9_n_0 )); LUT6 #( .INIT(64'hA888A88888A88888)) \FSM_sequential_wl_state_r[1]_i_1 (.I0(\FSM_sequential_wl_state_r[1]_i_2_n_0 ), .I1(\FSM_sequential_wl_state_r[1]_i_3_n_0 ), .I2(\FSM_sequential_wl_state_r[1]_i_4_n_0 ), .I3(out[1]), .I4(out[4]), .I5(out[2]), .O(\FSM_sequential_wl_state_r[1]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFA200)) \FSM_sequential_wl_state_r[1]_i_10 (.I0(out[2]), .I1(out[4]), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I4(\FSM_sequential_wl_state_r[1]_i_11_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_10_n_0 )); LUT6 #( .INIT(64'h00BB00BBFF0BFFBB)) \FSM_sequential_wl_state_r[1]_i_11 (.I0(\FSM_sequential_wl_state_r[0]_i_14_n_0 ), .I1(out[4]), .I2(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I3(out[3]), .I4(wrlvl_byte_redo), .I5(out[2]), .O(\FSM_sequential_wl_state_r[1]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFDFFF)) \FSM_sequential_wl_state_r[1]_i_2 (.I0(out[3]), .I1(\FSM_sequential_wl_state_r[0]_i_3_n_0 ), .I2(\FSM_sequential_wl_state_r_reg[0]_0 ), .I3(\FSM_sequential_wl_state_r[1]_i_5_n_0 ), .I4(out[0]), .I5(out[1]), .O(\FSM_sequential_wl_state_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h8F8F8F8F8F808080)) \FSM_sequential_wl_state_r[1]_i_3 (.I0(\FSM_sequential_wl_state_r[1]_i_6_n_0 ), .I1(\FSM_sequential_wl_state_r[1]_i_7_n_0 ), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[1]_i_8_n_0 ), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[1]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_3_n_0 )); LUT5 #( .INIT(32'h3FAAFF00)) \FSM_sequential_wl_state_r[1]_i_4 (.I0(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I1(\FSM_sequential_wl_state_r_reg[0]_0 ), .I2(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I3(out[4]), .I4(out[3]), .O(\FSM_sequential_wl_state_r[1]_i_4_n_0 )); LUT4 #( .INIT(16'h4000)) \FSM_sequential_wl_state_r[1]_i_5 (.I0(out[2]), .I1(\wl_tap_count_r_reg_n_0_[3] ), .I2(\wl_tap_count_r_reg_n_0_[4] ), .I3(\wl_tap_count_r_reg_n_0_[5] ), .O(\FSM_sequential_wl_state_r[1]_i_5_n_0 )); LUT6 #( .INIT(64'h7F7F7F7F7F7F7FFF)) \FSM_sequential_wl_state_r[1]_i_6 (.I0(out[4]), .I1(wrlvl_byte_redo), .I2(out[2]), .I3(wrlvl_redo_corse_inc__0[1]), .I4(wrlvl_redo_corse_inc__0[0]), .I5(wrlvl_redo_corse_inc__0[2]), .O(\FSM_sequential_wl_state_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'h0007FFFF00070000)) \FSM_sequential_wl_state_r[1]_i_7 (.I0(out[3]), .I1(wr_level_done_r5), .I2(out[4]), .I3(out[2]), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[1]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'hAAA8FFFFAAA8AAA8)) \FSM_sequential_wl_state_r[1]_i_8 (.I0(out[4]), .I1(\corse_dec[3][2]_i_2_n_0 ), .I2(\corse_dec[3][2]_i_3_n_0 ), .I3(\corse_dec[3][2]_i_4_n_0 ), .I4(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I5(out[3]), .O(\FSM_sequential_wl_state_r[1]_i_8_n_0 )); LUT6 #( .INIT(64'hAAA2A0A0AAA20000)) \FSM_sequential_wl_state_r[1]_i_9 (.I0(out[2]), .I1(stable_cnt227_in), .I2(out[3]), .I3(stable_cnt1), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[1]_i_9_n_0 )); LUT5 #( .INIT(32'hAAA8A8A8)) \FSM_sequential_wl_state_r[2]_i_1 (.I0(\FSM_sequential_wl_state_r[2]_i_2_n_0 ), .I1(\FSM_sequential_wl_state_r[2]_i_3_n_0 ), .I2(\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ), .I3(\FSM_sequential_wl_state_r[2]_i_5_n_0 ), .I4(out[2]), .O(\FSM_sequential_wl_state_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_wl_state_r[2]_i_10 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(\fine_inc[3][5]_i_8_n_0 ), .I4(\fine_inc[3][4]_i_3_n_0 ), .I5(\fine_inc[3][4]_i_4_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_10_n_0 )); LUT6 #( .INIT(64'h1000100010001010)) \FSM_sequential_wl_state_r[2]_i_11 (.I0(out[3]), .I1(out[0]), .I2(out[2]), .I3(out[4]), .I4(stable_cnt227_in), .I5(stable_cnt1), .O(\FSM_sequential_wl_state_r[2]_i_11_n_0 )); LUT5 #( .INIT(32'h00200000)) \FSM_sequential_wl_state_r[2]_i_12 (.I0(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I1(out[1]), .I2(out[0]), .I3(out[4]), .I4(wrlvl_byte_redo), .O(\FSM_sequential_wl_state_r[2]_i_12_n_0 )); LUT5 #( .INIT(32'h10101F10)) \FSM_sequential_wl_state_r[2]_i_13 (.I0(\FSM_sequential_wl_state_r_reg[0]_0 ), .I1(out[0]), .I2(out[4]), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_13_n_0 )); LUT6 #( .INIT(64'h0B3B0B0B3B3B3B3B)) \FSM_sequential_wl_state_r[2]_i_14 (.I0(out[0]), .I1(out[3]), .I2(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I3(wr_level_done_r5), .I4(wl_sm_start), .I5(out[4]), .O(\FSM_sequential_wl_state_r[2]_i_14_n_0 )); LUT6 #( .INIT(64'h011F077F077F077F)) \FSM_sequential_wl_state_r[2]_i_15 (.I0(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .I1(wrlvl_redo_corse_inc__0[1]), .I2(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .I3(wrlvl_redo_corse_inc__0[2]), .I4(wrlvl_redo_corse_inc__0[0]), .I5(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFF7FFF00000000)) \FSM_sequential_wl_state_r[2]_i_2 (.I0(\FSM_sequential_wl_state_r[2]_i_6_n_0 ), .I1(out[4]), .I2(out[0]), .I3(wrlvl_byte_redo), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[2]_i_7_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAAE)) \FSM_sequential_wl_state_r[2]_i_3 (.I0(\FSM_sequential_wl_state_r[2]_i_8_n_0 ), .I1(out[2]), .I2(\FSM_sequential_wl_state_r[2]_i_9_n_0 ), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I5(\FSM_sequential_wl_state_r[2]_i_11_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'hBFAFBFAFB0AFB0A0)) \FSM_sequential_wl_state_r[2]_i_5 (.I0(out[4]), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(wrlvl_byte_redo), .I5(\FSM_sequential_wl_state_r[2]_i_14_n_0 ), .O(\FSM_sequential_wl_state_r[2]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair336" *) LUT3 #( .INIT(8'h01)) \FSM_sequential_wl_state_r[2]_i_6 (.I0(wrlvl_redo_corse_inc__0[1]), .I1(wrlvl_redo_corse_inc__0[0]), .I2(wrlvl_redo_corse_inc__0[2]), .O(\FSM_sequential_wl_state_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFDFFDFFFFFFFF)) \FSM_sequential_wl_state_r[2]_i_7 (.I0(out[0]), .I1(\FSM_sequential_wl_state_r[2]_i_15_n_0 ), .I2(out[2]), .I3(out[1]), .I4(out[4]), .I5(wrlvl_byte_redo), .O(\FSM_sequential_wl_state_r[2]_i_7_n_0 )); LUT6 #( .INIT(64'h0500000035330000)) \FSM_sequential_wl_state_r[2]_i_8 (.I0(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I1(out[4]), .I2(out[0]), .I3(out[3]), .I4(out[1]), .I5(out[2]), .O(\FSM_sequential_wl_state_r[2]_i_8_n_0 )); LUT5 #( .INIT(32'h8888F888)) \FSM_sequential_wl_state_r[2]_i_9 (.I0(out[0]), .I1(out[3]), .I2(dqs_count_r[1]), .I3(dqs_count_r[0]), .I4(dqs_count_r[2]), .O(\FSM_sequential_wl_state_r[2]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFEFEAEFEAEFEA)) \FSM_sequential_wl_state_r[3]_i_1 (.I0(\FSM_sequential_wl_state_r[3]_i_2_n_0 ), .I1(\FSM_sequential_wl_state_r[3]_i_3_n_0 ), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[3]_i_4_n_0 ), .I4(out[3]), .I5(\FSM_sequential_wl_state_r[3]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_wl_state_r[3]_i_10 (.I0(fine_dec_cnt__0[5]), .I1(fine_dec_cnt__0[3]), .I2(fine_dec_cnt__0[1]), .I3(fine_dec_cnt__0[0]), .I4(fine_dec_cnt__0[2]), .I5(fine_dec_cnt__0[4]), .O(\FSM_sequential_wl_state_r[3]_i_10_n_0 )); LUT6 #( .INIT(64'h0100010005AA0500)) \FSM_sequential_wl_state_r[3]_i_2 (.I0(out[1]), .I1(\FSM_sequential_wl_state_r[3]_i_6_n_0 ), .I2(out[2]), .I3(out[3]), .I4(out[0]), .I5(out[4]), .O(\FSM_sequential_wl_state_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6200000062626262)) \FSM_sequential_wl_state_r[3]_i_3 (.I0(out[4]), .I1(out[1]), .I2(wr_level_done_r5), .I3(\FSM_sequential_wl_state_r[3]_i_7_n_0 ), .I4(\FSM_sequential_wl_state_r[3]_i_8_n_0 ), .I5(out[2]), .O(\FSM_sequential_wl_state_r[3]_i_3_n_0 )); LUT5 #( .INIT(32'h00400000)) \FSM_sequential_wl_state_r[3]_i_4 (.I0(stable_cnt1), .I1(out[1]), .I2(out[2]), .I3(out[4]), .I4(stable_cnt227_in), .O(\FSM_sequential_wl_state_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'h33BB338830883088)) \FSM_sequential_wl_state_r[3]_i_5 (.I0(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I1(out[0]), .I2(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .I3(out[1]), .I4(\FSM_sequential_wl_state_r[3]_i_7_n_0 ), .I5(out[2]), .O(\FSM_sequential_wl_state_r[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair313" *) LUT5 #( .INIT(32'h5555D555)) \FSM_sequential_wl_state_r[3]_i_6 (.I0(\FSM_sequential_wl_state_r_reg[0]_0 ), .I1(\wl_tap_count_r_reg_n_0_[5] ), .I2(\wl_tap_count_r_reg_n_0_[4] ), .I3(\wl_tap_count_r_reg_n_0_[3] ), .I4(\rd_data_edge_detect_r[3]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair318" *) LUT4 #( .INIT(16'hFFF7)) \FSM_sequential_wl_state_r[3]_i_7 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(dqs_count_r[2]), .O(\FSM_sequential_wl_state_r[3]_i_7_n_0 )); LUT5 #( .INIT(32'h00005100)) \FSM_sequential_wl_state_r[3]_i_8 (.I0(wrlvl_byte_redo), .I1(wl_sm_start), .I2(wr_level_done_r5), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I4(out[1]), .O(\FSM_sequential_wl_state_r[3]_i_8_n_0 )); LUT3 #( .INIT(8'h01)) \FSM_sequential_wl_state_r[3]_i_9 (.I0(\corse_inc[3][0]_i_2_n_0 ), .I1(\corse_inc[3][2]_i_4_n_0 ), .I2(\corse_inc[3][2]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[3]_i_9_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF03031D1C)) \FSM_sequential_wl_state_r[4]_i_1 (.I0(out[0]), .I1(out[4]), .I2(out[2]), .I3(\FSM_sequential_wl_state_r[4]_i_3_n_0 ), .I4(out[1]), .I5(\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hE0FFFF00E000FF00)) \FSM_sequential_wl_state_r[4]_i_10 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo_reg), .I2(out[4]), .I3(out[0]), .I4(out[2]), .I5(\FSM_sequential_wl_state_r[4]_i_12_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_10_n_0 )); LUT4 #( .INIT(16'hF8FA)) \FSM_sequential_wl_state_r[4]_i_11 (.I0(wr_level_done_r5), .I1(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I2(out[1]), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair321" *) LUT4 #( .INIT(16'h0010)) \FSM_sequential_wl_state_r[4]_i_12 (.I0(incdec_wait_cnt_reg__0[1]), .I1(incdec_wait_cnt_reg__0[0]), .I2(incdec_wait_cnt_reg__0[3]), .I3(incdec_wait_cnt_reg__0[2]), .O(\FSM_sequential_wl_state_r[4]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFF080403070804)) \FSM_sequential_wl_state_r[4]_i_2 (.I0(out[0]), .I1(out[2]), .I2(out[3]), .I3(out[1]), .I4(out[4]), .I5(\FSM_sequential_wl_state_r[4]_i_5_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h08FF080808080808)) \FSM_sequential_wl_state_r[4]_i_3 (.I0(early1_data_reg), .I1(wrlvl_byte_redo), .I2(wrlvl_byte_redo_r), .I3(wr_level_done_r1_reg_0), .I4(wl_sm_start), .I5(wr_level_start_r), .O(\FSM_sequential_wl_state_r[4]_i_3_n_0 )); LUT6 #( .INIT(64'h000000000F0FBBB0)) \FSM_sequential_wl_state_r[4]_i_5 (.I0(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I1(out[3]), .I2(out[1]), .I3(\FSM_sequential_wl_state_r_reg[0]_0 ), .I4(out[0]), .I5(\FSM_sequential_wl_state_r[4]_i_9_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hF0F0FFFCF0F02020)) \FSM_sequential_wl_state_r[4]_i_7 (.I0(out[2]), .I1(out[4]), .I2(wl_sm_start), .I3(wrlvl_byte_redo), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[4]_i_10_n_0 ), .O(\FSM_sequential_wl_state_r[4]_i_7_n_0 )); LUT6 #( .INIT(64'h22222020FFF000FF)) \FSM_sequential_wl_state_r[4]_i_8 (.I0(\FSM_sequential_wl_state_r[4]_i_11_n_0 ), .I1(out[4]), .I2(\FSM_sequential_wl_state_r[4]_i_12_n_0 ), .I3(out[1]), .I4(out[0]), .I5(out[2]), .O(\FSM_sequential_wl_state_r[4]_i_8_n_0 )); LUT5 #( .INIT(32'h00005545)) \FSM_sequential_wl_state_r[4]_i_9 (.I0(out[3]), .I1(wr_level_done_r5), .I2(wl_sm_start), .I3(wrlvl_byte_redo), .I4(out[1]), .O(\FSM_sequential_wl_state_r[4]_i_9_n_0 )); (* KEEP = "yes" *) FDRE \FSM_sequential_wl_state_r_reg[0] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[0]_i_1_n_0 ), .Q(out[0]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_wl_state_r_reg[0]_i_12 (.I0(\FSM_sequential_wl_state_r[0]_i_15_n_0 ), .I1(\FSM_sequential_wl_state_r[0]_i_16_n_0 ), .O(\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ), .S(out[0])); (* KEEP = "yes" *) FDRE \FSM_sequential_wl_state_r_reg[1] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[1]_i_1_n_0 ), .Q(out[1]), .R(rstdiv0_sync_r1_reg_rep__19)); (* KEEP = "yes" *) FDRE \FSM_sequential_wl_state_r_reg[2] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[2]_i_1_n_0 ), .Q(out[2]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_wl_state_r_reg[2]_i_4 (.I0(\FSM_sequential_wl_state_r[2]_i_12_n_0 ), .I1(\FSM_sequential_wl_state_r[2]_i_13_n_0 ), .O(\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ), .S(out[3])); (* KEEP = "yes" *) FDRE \FSM_sequential_wl_state_r_reg[3] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[3]_i_1_n_0 ), .Q(out[3]), .R(rstdiv0_sync_r1_reg_rep__19)); (* KEEP = "yes" *) FDRE \FSM_sequential_wl_state_r_reg[4] (.C(CLK), .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ), .D(\FSM_sequential_wl_state_r[4]_i_2_n_0 ), .Q(out[4]), .R(rstdiv0_sync_r1_reg_rep__19)); MUXF7 \FSM_sequential_wl_state_r_reg[4]_i_4 (.I0(\FSM_sequential_wl_state_r[4]_i_7_n_0 ), .I1(\FSM_sequential_wl_state_r[4]_i_8_n_0 ), .O(\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ), .S(out[3])); (* SOFT_HLUTNM = "soft_lutpair348" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[0][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[0][2]_i_3_n_0 ), .I2(\corse_cnt_reg_n_0_[0][0] ), .O(\corse_cnt[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00F000F088F8FFF8)) \corse_cnt[0][0]_i_2 (.I0(\corse_cnt[0][0]_i_3_n_0 ), .I1(out[0]), .I2(\corse_cnt[0][0]_i_4_n_0 ), .I3(out[2]), .I4(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I5(out[3]), .O(corse_cnt[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][0]_i_3 (.I0(\final_coarse_tap_reg_n_0_[3][0] ), .I1(\final_coarse_tap_reg_n_0_[1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\final_coarse_tap_reg_n_0_[2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\final_coarse_tap_reg_n_0_[0][0] ), .O(\corse_cnt[0][0]_i_3_n_0 )); LUT4 #( .INIT(16'h8830)) \corse_cnt[0][0]_i_4 (.I0(p_0_in), .I1(out[0]), .I2(final_coarse_tap), .I3(out[1]), .O(\corse_cnt[0][0]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][0]_i_5 (.I0(\final_coarse_tap_reg_n_0_[3][0] ), .I1(\final_coarse_tap_reg_n_0_[1][0] ), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\final_coarse_tap_reg_n_0_[2][0] ), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\final_coarse_tap_reg_n_0_[0][0] ), .O(final_coarse_tap)); (* SOFT_HLUTNM = "soft_lutpair337" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[0][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[0][2]_i_3_n_0 ), .I2(\corse_cnt_reg_n_0_[0][1] ), .O(\corse_cnt[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFF080808FF08)) \corse_cnt[0][1]_i_2 (.I0(\corse_cnt[0][1]_i_3_n_0 ), .I1(out[0]), .I2(out[3]), .I3(\corse_cnt[0][1]_i_4_n_0 ), .I4(out[2]), .I5(\corse_cnt[0][1]_i_5_n_0 ), .O(corse_cnt[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][1]_i_3 (.I0(\final_coarse_tap_reg_n_0_[3][1] ), .I1(\final_coarse_tap_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\final_coarse_tap_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\final_coarse_tap_reg_n_0_[0][1] ), .O(\corse_cnt[0][1]_i_3_n_0 )); LUT4 #( .INIT(16'h8830)) \corse_cnt[0][1]_i_4 (.I0(p_0_in), .I1(out[0]), .I2(\wrlvl_redo_corse_inc_reg[2]_0 [0]), .I3(out[1]), .O(\corse_cnt[0][1]_i_4_n_0 )); LUT3 #( .INIT(8'h06)) \corse_cnt[0][1]_i_5 (.I0(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I1(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .I2(out[3]), .O(\corse_cnt[0][1]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair338" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[0][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[0][2]_i_3_n_0 ), .I2(\corse_cnt_reg_n_0_[0][2] ), .O(\corse_cnt[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00010000)) \corse_cnt[0][2]_i_10 (.I0(out[1]), .I1(dqs_count_r[2]), .I2(dqs_count_r[1]), .I3(dqs_count_r[0]), .I4(wrlvl_final_mux), .I5(out[3]), .O(\corse_cnt[0][2]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFF080808FF08)) \corse_cnt[0][2]_i_2 (.I0(\corse_cnt[0][2]_i_4_n_0 ), .I1(out[0]), .I2(out[3]), .I3(\corse_cnt[0][2]_i_5_n_0 ), .I4(out[2]), .I5(\corse_cnt[0][2]_i_6_n_0 ), .O(corse_cnt[2])); LUT6 #( .INIT(64'h0040004055400040)) \corse_cnt[0][2]_i_3 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[0][2]_i_8_n_0 ), .I2(\corse_cnt[0][2]_i_9_n_0 ), .I3(out[0]), .I4(\corse_cnt[0][2]_i_10_n_0 ), .I5(out[2]), .O(\corse_cnt[0][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_cnt[0][2]_i_4 (.I0(\final_coarse_tap_reg_n_0_[3][2] ), .I1(\final_coarse_tap_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\final_coarse_tap_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\final_coarse_tap_reg_n_0_[0][2] ), .O(\corse_cnt[0][2]_i_4_n_0 )); LUT4 #( .INIT(16'h8830)) \corse_cnt[0][2]_i_5 (.I0(p_0_in), .I1(out[0]), .I2(\wrlvl_redo_corse_inc_reg[2]_0 [1]), .I3(out[1]), .O(\corse_cnt[0][2]_i_5_n_0 )); LUT4 #( .INIT(16'h0078)) \corse_cnt[0][2]_i_6 (.I0(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .I1(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .I2(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .I3(out[3]), .O(\corse_cnt[0][2]_i_6_n_0 )); LUT3 #( .INIT(8'hBC)) \corse_cnt[0][2]_i_7 (.I0(p_0_in), .I1(out[3]), .I2(out[4]), .O(\corse_cnt[0][2]_i_7_n_0 )); LUT6 #( .INIT(64'h202020202F202020)) \corse_cnt[0][2]_i_8 (.I0(\fine_inc[0][5]_i_3_n_0 ), .I1(\dqs_count_r[0]_i_8_n_0 ), .I2(out[2]), .I3(\po_stg2_wrcal_cnt_reg[0] ), .I4(done_dqs_dec239_out), .I5(\po_stg2_wrcal_cnt_reg[2] [1]), .O(\corse_cnt[0][2]_i_8_n_0 )); LUT2 #( .INIT(4'h1)) \corse_cnt[0][2]_i_9 (.I0(out[3]), .I1(out[1]), .O(\corse_cnt[0][2]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair335" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[1][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[1][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[1][0] ), .O(\corse_cnt[1][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair339" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[1][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[1][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[1][1] ), .O(\corse_cnt[1][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair340" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[1][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[1][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[1][2] ), .O(\corse_cnt[1][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0040004055400040)) \corse_cnt[1][2]_i_2 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[1][2]_i_3_n_0 ), .I2(\corse_cnt[0][2]_i_9_n_0 ), .I3(out[0]), .I4(\corse_cnt[1][2]_i_4_n_0 ), .I5(out[2]), .O(\corse_cnt[1][2]_i_2_n_0 )); LUT6 #( .INIT(64'h8A008A008A008AFF)) \corse_cnt[1][2]_i_3 (.I0(\fine_inc[1][5]_i_3_n_0 ), .I1(wrlvl_byte_redo), .I2(wr_level_done_r5), .I3(out[2]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\po_stg2_wrcal_cnt_reg[2]_0 ), .O(\corse_cnt[1][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00100000)) \corse_cnt[1][2]_i_4 (.I0(out[1]), .I1(dqs_count_r[2]), .I2(dqs_count_r[0]), .I3(dqs_count_r[1]), .I4(wrlvl_final_mux), .I5(out[3]), .O(\corse_cnt[1][2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair348" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[2][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[2][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[2][0] ), .O(\corse_cnt[2][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair339" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[2][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[2][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[2][1] ), .O(\corse_cnt[2][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair338" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[2][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[2][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[2][2] ), .O(\corse_cnt[2][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0040004055400040)) \corse_cnt[2][2]_i_2 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[2][2]_i_3_n_0 ), .I2(\corse_cnt[0][2]_i_9_n_0 ), .I3(out[0]), .I4(\corse_cnt[2][2]_i_4_n_0 ), .I5(out[2]), .O(\corse_cnt[2][2]_i_2_n_0 )); LUT6 #( .INIT(64'h202020202020202F)) \corse_cnt[2][2]_i_3 (.I0(\fine_inc[2][5]_i_3_n_0 ), .I1(\dqs_count_r[0]_i_8_n_0 ), .I2(out[2]), .I3(\po_stg2_wrcal_cnt_reg[2] [2]), .I4(\po_stg2_wrcal_cnt_reg[2] [0]), .I5(\po_stg2_wrcal_cnt_reg[1] ), .O(\corse_cnt[2][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA00100000)) \corse_cnt[2][2]_i_4 (.I0(out[1]), .I1(dqs_count_r[2]), .I2(dqs_count_r[1]), .I3(dqs_count_r[0]), .I4(wrlvl_final_mux), .I5(out[3]), .O(\corse_cnt[2][2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair335" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[3][0]_i_1 (.I0(corse_cnt[0]), .I1(\corse_cnt[3][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[3][0] ), .O(\corse_cnt[3][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair337" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[3][1]_i_1 (.I0(corse_cnt[1]), .I1(\corse_cnt[3][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[3][1] ), .O(\corse_cnt[3][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair340" *) LUT3 #( .INIT(8'hB8)) \corse_cnt[3][2]_i_1 (.I0(corse_cnt[2]), .I1(\corse_cnt[3][2]_i_2_n_0 ), .I2(\corse_cnt_reg_n_0_[3][2] ), .O(\corse_cnt[3][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000455550004)) \corse_cnt[3][2]_i_2 (.I0(\corse_cnt[0][2]_i_7_n_0 ), .I1(\corse_cnt[3][2]_i_3_n_0 ), .I2(out[3]), .I3(out[1]), .I4(out[0]), .I5(\corse_cnt[3][2]_i_4_n_0 ), .O(\corse_cnt[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'h8A008A008AFF8A00)) \corse_cnt[3][2]_i_3 (.I0(\fine_inc[3][5]_i_5_n_0 ), .I1(wrlvl_byte_redo), .I2(wr_level_done_r5), .I3(out[2]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\po_stg2_wrcal_cnt_reg[2]_0 ), .O(\corse_cnt[3][2]_i_3_n_0 )); LUT5 #( .INIT(32'hBBBBEFFF)) \corse_cnt[3][2]_i_4 (.I0(out[2]), .I1(out[3]), .I2(wrlvl_final_mux), .I3(\fine_inc[3][5]_i_5_n_0 ), .I4(out[1]), .O(\corse_cnt[3][2]_i_4_n_0 )); FDRE \corse_cnt_reg[0][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[0][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[0][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[0][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[0][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[0][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[1][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[1][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[1][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[1][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[1][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[1][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[2][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[2][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[2][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[2][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[2][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[2][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[3][0] (.C(CLK), .CE(1'b1), .D(\corse_cnt[3][0]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[3][1] (.C(CLK), .CE(1'b1), .D(\corse_cnt[3][1]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \corse_cnt_reg[3][2] (.C(CLK), .CE(1'b1), .D(\corse_cnt[3][2]_i_1_n_0 ), .Q(\corse_cnt_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[0][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[0][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[0][0] ), .O(\corse_dec[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[0][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[0][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[0][1] ), .O(\corse_dec[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[0][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[0][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[0][2] ), .O(\corse_dec[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[0][2]_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[0][5]_i_3_n_0 ), .O(\corse_dec[0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[1][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[1][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[1][0] ), .O(\corse_dec[1][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[1][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[1][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[1][1] ), .O(\corse_dec[1][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[1][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[1][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[1][2] ), .O(\corse_dec[1][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[1][2]_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[1][5]_i_3_n_0 ), .O(\corse_dec[1][2]_i_2_n_0 )); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[2][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[2][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[2][0] ), .O(\corse_dec[2][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[2][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[2][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[2][1] ), .O(\corse_dec[2][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[2][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[2][2]_i_2_n_0 ), .I5(\corse_dec_reg_n_0_[2][2] ), .O(\corse_dec[2][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[2][2]_i_2 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[2][5]_i_3_n_0 ), .O(\corse_dec[2][2]_i_2_n_0 )); LUT6 #( .INIT(64'h000EFFFF000E0000)) \corse_dec[3][0]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[3][2]_i_5_n_0 ), .I5(\corse_dec_reg_n_0_[3][0] ), .O(\corse_dec[3][0]_i_1_n_0 )); LUT6 #( .INIT(64'h00C2FFFF00C20000)) \corse_dec[3][1]_i_1 (.I0(\corse_dec[3][2]_i_3_n_0 ), .I1(\corse_dec[3][2]_i_4_n_0 ), .I2(\corse_dec[3][2]_i_2_n_0 ), .I3(out[3]), .I4(\corse_dec[3][2]_i_5_n_0 ), .I5(\corse_dec_reg_n_0_[3][1] ), .O(\corse_dec[3][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00C8FFFF00C80000)) \corse_dec[3][2]_i_1 (.I0(\corse_dec[3][2]_i_2_n_0 ), .I1(\corse_dec[3][2]_i_3_n_0 ), .I2(\corse_dec[3][2]_i_4_n_0 ), .I3(out[3]), .I4(\corse_dec[3][2]_i_5_n_0 ), .I5(\corse_dec_reg_n_0_[3][2] ), .O(\corse_dec[3][2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_dec[3][2]_i_2 (.I0(\corse_dec_reg_n_0_[3][0] ), .I1(\corse_dec_reg_n_0_[1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_dec_reg_n_0_[2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_dec_reg_n_0_[0][0] ), .O(\corse_dec[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_dec[3][2]_i_3 (.I0(\corse_dec_reg_n_0_[3][2] ), .I1(\corse_dec_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_dec_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_dec_reg_n_0_[0][2] ), .O(\corse_dec[3][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_dec[3][2]_i_4 (.I0(\corse_dec_reg_n_0_[3][1] ), .I1(\corse_dec_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_dec_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_dec_reg_n_0_[0][1] ), .O(\corse_dec[3][2]_i_4_n_0 )); LUT6 #( .INIT(64'h0001000000000000)) \corse_dec[3][2]_i_5 (.I0(out[0]), .I1(out[1]), .I2(out[2]), .I3(out[3]), .I4(out[4]), .I5(\fine_inc[3][5]_i_5_n_0 ), .O(\corse_dec[3][2]_i_5_n_0 )); FDRE \corse_dec_reg[0][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[0][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[0][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[0][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[0][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[0][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[1][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[1][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[1][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[1][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[1][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[1][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[2][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[2][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[2][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[2][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[2][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[2][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[3][0] (.C(CLK), .CE(1'b1), .D(\corse_dec[3][0]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[3][1] (.C(CLK), .CE(1'b1), .D(\corse_dec[3][1]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_dec_reg[3][2] (.C(CLK), .CE(1'b1), .D(\corse_dec[3][2]_i_1_n_0 ), .Q(\corse_dec_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[0][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[0][0] ), .I3(out[0]), .I4(\corse_inc[0][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[0][0] ), .O(\corse_inc[0][0]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[0][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[0][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[0][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[0][1] ), .O(\corse_inc[0][1]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[0][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[0][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[0][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[0][2] ), .O(\corse_inc[0][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[0][2]_i_2 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[0][2]_i_3_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000002)) \corse_inc[0][2]_i_3 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[0][2]_i_3_n_0 )); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[1][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[1][0] ), .I3(out[0]), .I4(\corse_inc[1][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[1][0] ), .O(\corse_inc[1][0]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[1][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[1][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[1][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[1][1] ), .O(\corse_inc[1][1]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[1][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[1][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[1][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[1][2] ), .O(\corse_inc[1][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[1][2]_i_2 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[1][2]_i_3_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[1][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \corse_inc[1][2]_i_3 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[0]), .I4(dqs_count_r[1]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[1][2]_i_3_n_0 )); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[2][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[2][0] ), .I3(out[0]), .I4(\corse_inc[2][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[2][0] ), .O(\corse_inc[2][0]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[2][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[2][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[2][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[2][1] ), .O(\corse_inc[2][1]_i_1_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[2][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[2][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[2][2]_i_2_n_0 ), .I5(\corse_inc_reg_n_0_[2][2] ), .O(\corse_inc[2][2]_i_1_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[2][2]_i_2 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[2][2]_i_3_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[2][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \corse_inc[2][2]_i_3 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[2][2]_i_3_n_0 )); LUT6 #( .INIT(64'h5011FFFF50110000)) \corse_inc[3][0]_i_1 (.I0(out[4]), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\final_coarse_tap_reg_n_0_[3][0] ), .I3(out[0]), .I4(\corse_inc[3][2]_i_3_n_0 ), .I5(\corse_inc_reg_n_0_[3][0] ), .O(\corse_inc[3][0]_i_1_n_0 )); LUT6 #( .INIT(64'hF0FFF000AACCAACC)) \corse_inc[3][0]_i_2 (.I0(\corse_inc_reg_n_0_[2][0] ), .I1(\corse_inc_reg_n_0_[0][0] ), .I2(\corse_inc_reg_n_0_[3][0] ), .I3(\dqs_count_r_reg[1]_rep_n_0 ), .I4(\corse_inc_reg_n_0_[1][0] ), .I5(\dqs_count_r_reg[0]_rep_n_0 ), .O(\corse_inc[3][0]_i_2_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[3][1]_i_1 (.I0(\final_coarse_tap_reg_n_0_[3][1] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][1]_i_2_n_0 ), .I4(\corse_inc[3][2]_i_3_n_0 ), .I5(\corse_inc_reg_n_0_[3][1] ), .O(\corse_inc[3][1]_i_1_n_0 )); LUT3 #( .INIT(8'h09)) \corse_inc[3][1]_i_2 (.I0(\corse_inc[3][0]_i_2_n_0 ), .I1(\corse_inc[3][2]_i_4_n_0 ), .I2(out[4]), .O(\corse_inc[3][1]_i_2_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \corse_inc[3][2]_i_1 (.I0(\final_coarse_tap_reg_n_0_[3][2] ), .I1(out[4]), .I2(out[0]), .I3(\corse_inc[3][2]_i_2_n_0 ), .I4(\corse_inc[3][2]_i_3_n_0 ), .I5(\corse_inc_reg_n_0_[3][2] ), .O(\corse_inc[3][2]_i_1_n_0 )); LUT4 #( .INIT(16'h00E1)) \corse_inc[3][2]_i_2 (.I0(\corse_inc[3][2]_i_4_n_0 ), .I1(\corse_inc[3][0]_i_2_n_0 ), .I2(\corse_inc[3][2]_i_5_n_0 ), .I3(out[4]), .O(\corse_inc[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0020002088200020)) \corse_inc[3][2]_i_3 (.I0(\corse_inc[3][2]_i_6_n_0 ), .I1(out[3]), .I2(\corse_inc[3][2]_i_7_n_0 ), .I3(out[0]), .I4(wr_level_done_r4), .I5(wr_level_done_r5), .O(\corse_inc[3][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_inc[3][2]_i_4 (.I0(\corse_inc_reg_n_0_[3][1] ), .I1(\corse_inc_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_inc_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_inc_reg_n_0_[0][1] ), .O(\corse_inc[3][2]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \corse_inc[3][2]_i_5 (.I0(\corse_inc_reg_n_0_[3][2] ), .I1(\corse_inc_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_inc_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_inc_reg_n_0_[0][2] ), .O(\corse_inc[3][2]_i_5_n_0 )); LUT3 #( .INIT(8'h02)) \corse_inc[3][2]_i_6 (.I0(out[2]), .I1(out[4]), .I2(out[1]), .O(\corse_inc[3][2]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000002000000)) \corse_inc[3][2]_i_7 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\corse_inc[3][2]_i_7_n_0 )); FDRE \corse_inc_reg[0][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[0][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[0][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[0][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[0][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[0][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[1][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[1][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[1][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[1][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[1][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[1][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[2][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[2][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[2][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[2][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[2][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[2][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[3][0] (.C(CLK), .CE(1'b1), .D(\corse_inc[3][0]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[3][1] (.C(CLK), .CE(1'b1), .D(\corse_inc[3][1]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \corse_inc_reg[3][2] (.C(CLK), .CE(1'b1), .D(\corse_inc[3][2]_i_1_n_0 ), .Q(\corse_inc_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__15)); LUT3 #( .INIT(8'hBF)) \ctl_lane_cnt[2]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__25), .I1(dqs_po_dec_done), .I2(pi_fine_dly_dec_done), .O(p_1_in)); LUT5 #( .INIT(32'h77770777)) dq_cnt_inc_i_2 (.I0(wrlvl_byte_redo), .I1(out[3]), .I2(dqs_count_r[0]), .I3(dqs_count_r[1]), .I4(dqs_count_r[2]), .O(dq_cnt_inc_reg_0)); FDSE dq_cnt_inc_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[1]_0 ), .Q(p_0_in), .S(rstdiv0_sync_r1_reg_rep__15)); LUT6 #( .INIT(64'hF444FFFFF4440000)) \dqs_count_r[0]_i_1 (.I0(out[4]), .I1(\dqs_count_r_reg[0]_i_2_n_0 ), .I2(\dqs_count_r_reg[0]_i_3_n_0 ), .I3(out[0]), .I4(\dqs_count_r[2]_i_5_n_0 ), .I5(\dqs_count_r_reg[0]_rep_n_0 ), .O(\dqs_count_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'hCACC0A00CACCCACC)) \dqs_count_r[0]_i_4 (.I0(\po_stg2_wrcal_cnt_reg[2] [0]), .I1(\dqs_count_r_reg[0]_rep_n_0 ), .I2(wrlvl_byte_redo_r), .I3(wrlvl_byte_redo), .I4(wrlvl_final_r), .I5(wrlvl_final_mux), .O(\dqs_count_r[0]_i_4_n_0 )); LUT6 #( .INIT(64'hBFBFBFB0000F000F)) \dqs_count_r[0]_i_5 (.I0(wr_level_done_r5), .I1(wr_level_done_r4), .I2(out[0]), .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I4(\fine_inc[3][5]_i_5_n_0 ), .I5(dqs_count_r[0]), .O(\dqs_count_r[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFBFFF80000FF03FF)) \dqs_count_r[0]_i_6 (.I0(p_0_in), .I1(out[1]), .I2(wrlvl_byte_redo), .I3(out[3]), .I4(\fine_inc[3][5]_i_5_n_0 ), .I5(dqs_count_r[0]), .O(\dqs_count_r[0]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000ADAAAAAA)) \dqs_count_r[0]_i_7 (.I0(dqs_count_r[0]), .I1(\fine_inc[3][5]_i_5_n_0 ), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .I4(\dqs_count_r[0]_i_8_n_0 ), .I5(out[3]), .O(\dqs_count_r[0]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair322" *) LUT2 #( .INIT(4'h2)) \dqs_count_r[0]_i_8 (.I0(wr_level_done_r5), .I1(wrlvl_byte_redo), .O(\dqs_count_r[0]_i_8_n_0 )); LUT6 #( .INIT(64'hF444FFFFF4440000)) \dqs_count_r[1]_i_1 (.I0(out[4]), .I1(\dqs_count_r_reg[1]_i_2_n_0 ), .I2(\dqs_count_r_reg[1]_i_3_n_0 ), .I3(out[0]), .I4(\dqs_count_r[2]_i_5_n_0 ), .I5(\dqs_count_r_reg[1]_rep_n_0 ), .O(\dqs_count_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hCACC0A00CACCCACC)) \dqs_count_r[1]_i_4 (.I0(\po_stg2_wrcal_cnt_reg[2] [1]), .I1(dqs_count_r[1]), .I2(wrlvl_byte_redo_r), .I3(wrlvl_byte_redo), .I4(wrlvl_final_r), .I5(wrlvl_final_mux), .O(\dqs_count_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'h7477030377770000)) \dqs_count_r[1]_i_5 (.I0(dqs_count_r140_out), .I1(out[0]), .I2(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I3(dqs_count_r[2]), .I4(dqs_count_r[1]), .I5(dqs_count_r[0]), .O(\dqs_count_r[1]_i_5_n_0 )); LUT5 #( .INIT(32'h8BBBBB88)) \dqs_count_r[1]_i_6 (.I0(\dqs_count_r[1]_i_8_n_0 ), .I1(out[3]), .I2(dqs_count_r[2]), .I3(dqs_count_r[1]), .I4(dqs_count_r[0]), .O(\dqs_count_r[1]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000CCCCCC6E)) \dqs_count_r[1]_i_7 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .I2(dqs_count_r[2]), .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I4(\dqs_count_r[2]_i_11_n_0 ), .I5(out[3]), .O(\dqs_count_r[1]_i_7_n_0 )); LUT6 #( .INIT(64'hF8FB0300FBFB0300)) \dqs_count_r[1]_i_8 (.I0(p_0_in), .I1(out[1]), .I2(wrlvl_byte_redo), .I3(dqs_count_r[0]), .I4(dqs_count_r[1]), .I5(dqs_count_r[2]), .O(\dqs_count_r[1]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair342" *) LUT2 #( .INIT(4'h7)) \dqs_count_r[2]_i_10 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .O(\dqs_count_r[2]_i_10_n_0 )); LUT3 #( .INIT(8'hBF)) \dqs_count_r[2]_i_11 (.I0(wrlvl_byte_redo), .I1(wr_level_done_r5), .I2(\FSM_sequential_wl_state_r[3]_i_9_n_0 ), .O(\dqs_count_r[2]_i_11_n_0 )); LUT6 #( .INIT(64'hF444FFFFF4440000)) \dqs_count_r[2]_i_2 (.I0(out[4]), .I1(\dqs_count_r_reg[2]_i_3_n_0 ), .I2(\dqs_count_r_reg[2]_i_4_n_0 ), .I3(out[0]), .I4(\dqs_count_r[2]_i_5_n_0 ), .I5(dqs_count_r[2]), .O(\dqs_count_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'h00805889)) \dqs_count_r[2]_i_5 (.I0(out[4]), .I1(out[0]), .I2(out[3]), .I3(out[2]), .I4(out[1]), .O(\dqs_count_r[2]_i_5_n_0 )); LUT6 #( .INIT(64'hFB080808FB08FB08)) \dqs_count_r[2]_i_6 (.I0(\po_stg2_wrcal_cnt_reg[2] [2]), .I1(wrlvl_byte_redo), .I2(wrlvl_byte_redo_r), .I3(dqs_count_r[2]), .I4(wrlvl_final_r), .I5(wrlvl_final_mux), .O(\dqs_count_r[2]_i_6_n_0 )); LUT6 #( .INIT(64'h7040707070707070)) \dqs_count_r[2]_i_7 (.I0(dqs_count_r140_out), .I1(out[0]), .I2(dqs_count_r[2]), .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I4(dqs_count_r[0]), .I5(dqs_count_r[1]), .O(\dqs_count_r[2]_i_7_n_0 )); LUT6 #( .INIT(64'hFBFFF80000000000)) \dqs_count_r[2]_i_8 (.I0(p_0_in), .I1(out[1]), .I2(wrlvl_byte_redo), .I3(out[3]), .I4(\dqs_count_r[2]_i_10_n_0 ), .I5(dqs_count_r[2]), .O(\dqs_count_r[2]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000FFBF0000)) \dqs_count_r[2]_i_9 (.I0(\FSM_sequential_wl_state_r[2]_i_10_n_0 ), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .I3(\dqs_count_r[2]_i_11_n_0 ), .I4(dqs_count_r[2]), .I5(out[3]), .O(\dqs_count_r[2]_i_9_n_0 )); (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) FDRE \dqs_count_r_reg[0] (.C(CLK), .CE(1'b1), .D(\dqs_count_r[0]_i_1_n_0 ), .Q(dqs_count_r[0]), .R(rstdiv0_sync_r1_reg_rep__17)); MUXF7 \dqs_count_r_reg[0]_i_2 (.I0(\dqs_count_r[0]_i_4_n_0 ), .I1(\dqs_count_r[0]_i_5_n_0 ), .O(\dqs_count_r_reg[0]_i_2_n_0 ), .S(out[3])); MUXF7 \dqs_count_r_reg[0]_i_3 (.I0(\dqs_count_r[0]_i_6_n_0 ), .I1(\dqs_count_r[0]_i_7_n_0 ), .O(\dqs_count_r_reg[0]_i_3_n_0 ), .S(out[2])); (* IS_FANOUT_CONSTRAINED = "1" *) (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) FDRE \dqs_count_r_reg[0]_rep (.C(CLK), .CE(1'b1), .D(\dqs_count_r[0]_i_1_n_0 ), .Q(\dqs_count_r_reg[0]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) FDRE \dqs_count_r_reg[1] (.C(CLK), .CE(1'b1), .D(\dqs_count_r[1]_i_1_n_0 ), .Q(dqs_count_r[1]), .R(rstdiv0_sync_r1_reg_rep__17)); MUXF7 \dqs_count_r_reg[1]_i_2 (.I0(\dqs_count_r[1]_i_4_n_0 ), .I1(\dqs_count_r[1]_i_5_n_0 ), .O(\dqs_count_r_reg[1]_i_2_n_0 ), .S(out[3])); MUXF7 \dqs_count_r_reg[1]_i_3 (.I0(\dqs_count_r[1]_i_6_n_0 ), .I1(\dqs_count_r[1]_i_7_n_0 ), .O(\dqs_count_r_reg[1]_i_3_n_0 ), .S(out[2])); (* IS_FANOUT_CONSTRAINED = "1" *) (* MAX_FANOUT = "50" *) (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) FDRE \dqs_count_r_reg[1]_rep (.C(CLK), .CE(1'b1), .D(\dqs_count_r[1]_i_1_n_0 ), .Q(\dqs_count_r_reg[1]_rep_n_0 ), .R(rstdiv0_sync_r1_reg_rep)); (* MAX_FANOUT = "50" *) FDRE \dqs_count_r_reg[2] (.C(CLK), .CE(1'b1), .D(\dqs_count_r[2]_i_2_n_0 ), .Q(dqs_count_r[2]), .R(rstdiv0_sync_r1_reg_rep__17)); MUXF7 \dqs_count_r_reg[2]_i_3 (.I0(\dqs_count_r[2]_i_6_n_0 ), .I1(\dqs_count_r[2]_i_7_n_0 ), .O(\dqs_count_r_reg[2]_i_3_n_0 ), .S(out[3])); MUXF7 \dqs_count_r_reg[2]_i_4 (.I0(\dqs_count_r[2]_i_8_n_0 ), .I1(\dqs_count_r[2]_i_9_n_0 ), .O(\dqs_count_r_reg[2]_i_4_n_0 ), .S(out[2])); (* syn_maxfan = "2" *) FDRE dqs_po_dec_done_reg (.C(CLK), .CE(1'b1), .D(po_dec_done), .Q(dqs_po_dec_done), .R(1'b0)); LUT6 #( .INIT(64'hAAAABBABAAAAAABA)) dqs_po_en_stg2_f_i_1 (.I0(dqs_po_en_stg2_f_reg_0), .I1(out[2]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .I5(out[1]), .O(dqs_po_en_stg2_f_i_1_n_0)); FDRE dqs_po_en_stg2_f_reg (.C(CLK), .CE(1'b1), .D(dqs_po_en_stg2_f_i_1_n_0), .Q(dqs_po_en_stg2_f), .R(rstdiv0_sync_r1_reg_rep__18)); LUT3 #( .INIT(8'h02)) dqs_po_stg2_f_incdec_i_1 (.I0(dqs_po_stg2_f_incdec_i_2_n_0), .I1(dqs_po_stg2_f_incdec_i_3_n_0), .I2(rstdiv0_sync_r1_reg_rep__23), .O(dqs_po_stg2_f_incdec0)); LUT6 #( .INIT(64'h00000000FFFFFEDF)) dqs_po_stg2_f_incdec_i_2 (.I0(out[1]), .I1(out[4]), .I2(out[0]), .I3(out[3]), .I4(out[2]), .I5(dqs_po_en_stg2_f_reg_0), .O(dqs_po_stg2_f_incdec_i_2_n_0)); LUT5 #( .INIT(32'hFBFEFFFF)) dqs_po_stg2_f_incdec_i_3 (.I0(out[2]), .I1(out[0]), .I2(out[4]), .I3(out[3]), .I4(out[1]), .O(dqs_po_stg2_f_incdec_i_3_n_0)); FDRE dqs_po_stg2_f_incdec_reg (.C(CLK), .CE(1'b1), .D(dqs_po_stg2_f_incdec0), .Q(dqs_po_stg2_f_incdec), .R(1'b0)); LUT5 #( .INIT(32'h00000002)) dqs_wl_po_stg2_c_incdec_i_1 (.I0(out[2]), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(out[4]), .O(dqs_wl_po_stg2_c_incdec_i_1_n_0)); FDRE dqs_wl_po_stg2_c_incdec_reg (.C(CLK), .CE(1'b1), .D(dqs_wl_po_stg2_c_incdec_i_1_n_0), .Q(dqs_wl_po_stg2_c_incdec), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \final_coarse_tap_reg[0][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][0]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[0][0] ), .R(1'b0)); FDRE \final_coarse_tap_reg[0][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][0]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[0][1] ), .R(1'b0)); FDRE \final_coarse_tap_reg[0][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][0]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[0][2] ), .R(1'b0)); FDRE \final_coarse_tap_reg[1][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][1]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[1][0] ), .R(1'b0)); FDRE \final_coarse_tap_reg[1][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][1]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[1][1] ), .R(1'b0)); FDRE \final_coarse_tap_reg[1][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][1]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[1][2] ), .R(1'b0)); FDRE \final_coarse_tap_reg[2][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][2]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[2][0] ), .R(1'b0)); FDRE \final_coarse_tap_reg[2][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][2]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[2][1] ), .R(1'b0)); FDRE \final_coarse_tap_reg[2][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][2]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[2][2] ), .R(1'b0)); FDRE \final_coarse_tap_reg[3][0] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][3]__0 [0]), .Q(\final_coarse_tap_reg_n_0_[3][0] ), .R(1'b0)); FDRE \final_coarse_tap_reg[3][1] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][3]__0 [1]), .Q(\final_coarse_tap_reg_n_0_[3][1] ), .R(1'b0)); FDRE \final_coarse_tap_reg[3][2] (.C(CLK), .CE(1'b1), .D(\wl_corse_cnt_reg[0][3]__0 [2]), .Q(\final_coarse_tap_reg_n_0_[3][2] ), .R(1'b0)); LUT6 #( .INIT(64'h303F000035370504)) \fine_dec_cnt[0]_i_1 (.I0(fine_dec_cnt__0[0]), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[0] ), .I5(out[4]), .O(fine_dec_cnt[0])); LUT6 #( .INIT(64'hBABFAAAABABBAAAA)) \fine_dec_cnt[1]_i_1 (.I0(\fine_dec_cnt[1]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[1] ), .I5(out[4]), .O(fine_dec_cnt[1])); LUT6 #( .INIT(64'h1001100110010000)) \fine_dec_cnt[1]_i_2 (.I0(out[4]), .I1(out[2]), .I2(fine_dec_cnt__0[1]), .I3(fine_dec_cnt__0[0]), .I4(out[1]), .I5(out[3]), .O(\fine_dec_cnt[1]_i_2_n_0 )); LUT6 #( .INIT(64'h303F000035370505)) \fine_dec_cnt[2]_i_1 (.I0(\fine_dec_cnt[2]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[2] ), .I5(out[4]), .O(fine_dec_cnt[2])); LUT5 #( .INIT(32'h1F1F1FF1)) \fine_dec_cnt[2]_i_2 (.I0(out[3]), .I1(out[1]), .I2(fine_dec_cnt__0[2]), .I3(fine_dec_cnt__0[0]), .I4(fine_dec_cnt__0[1]), .O(\fine_dec_cnt[2]_i_2_n_0 )); LUT6 #( .INIT(64'h303F000035370505)) \fine_dec_cnt[3]_i_1 (.I0(\fine_dec_cnt[3]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[3] ), .I5(out[4]), .O(fine_dec_cnt[3])); LUT6 #( .INIT(64'h1F1F1F1F1F1F1FF1)) \fine_dec_cnt[3]_i_2 (.I0(out[3]), .I1(out[1]), .I2(fine_dec_cnt__0[3]), .I3(fine_dec_cnt__0[1]), .I4(fine_dec_cnt__0[0]), .I5(fine_dec_cnt__0[2]), .O(\fine_dec_cnt[3]_i_2_n_0 )); LUT6 #( .INIT(64'h303F00003A3B0A08)) \fine_dec_cnt[4]_i_1 (.I0(\fine_dec_cnt[4]_i_2_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[4] ), .I5(out[4]), .O(fine_dec_cnt[4])); LUT5 #( .INIT(32'hFFFE0001)) \fine_dec_cnt[4]_i_2 (.I0(fine_dec_cnt__0[3]), .I1(fine_dec_cnt__0[1]), .I2(fine_dec_cnt__0[0]), .I3(fine_dec_cnt__0[2]), .I4(fine_dec_cnt__0[4]), .O(\fine_dec_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'h303F00003A3B0A08)) \fine_dec_cnt[5]_i_2 (.I0(\fine_dec_cnt[5]_i_5_n_0 ), .I1(out[3]), .I2(out[2]), .I3(out[1]), .I4(\wl_tap_count_r_reg_n_0_[5] ), .I5(out[4]), .O(fine_dec_cnt[5])); LUT5 #( .INIT(32'h11800080)) \fine_dec_cnt[5]_i_3 (.I0(out[2]), .I1(out[1]), .I2(\fine_dec_cnt[5]_i_6_n_0 ), .I3(out[3]), .I4(\fine_dec_cnt[5]_i_7_n_0 ), .O(\fine_dec_cnt[5]_i_3_n_0 )); LUT6 #( .INIT(64'h4444040000000400)) \fine_dec_cnt[5]_i_4 (.I0(out[3]), .I1(\fine_dec_cnt[5]_i_8_n_0 ), .I2(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I3(wrlvl_byte_redo), .I4(out[1]), .I5(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(\fine_dec_cnt[5]_i_4_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \fine_dec_cnt[5]_i_5 (.I0(fine_dec_cnt__0[5]), .I1(fine_dec_cnt__0[3]), .I2(fine_dec_cnt__0[1]), .I3(fine_dec_cnt__0[0]), .I4(fine_dec_cnt__0[2]), .I5(fine_dec_cnt__0[4]), .O(\fine_dec_cnt[5]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000080000000)) \fine_dec_cnt[5]_i_6 (.I0(\stable_cnt_reg_n_0_[1] ), .I1(\stable_cnt_reg_n_0_[2] ), .I2(\stable_cnt_reg_n_0_[3] ), .I3(wl_sm_start), .I4(stable_cnt227_in), .I5(out[4]), .O(\fine_dec_cnt[5]_i_6_n_0 )); LUT6 #( .INIT(64'h0020FFFF00200000)) \fine_dec_cnt[5]_i_7 (.I0(\FSM_sequential_wl_state_r[0]_i_3_n_0 ), .I1(\FSM_sequential_wl_state_r[0]_i_5_n_0 ), .I2(\FSM_sequential_wl_state_r_reg[0]_0 ), .I3(\rd_data_edge_detect_r[3]_i_5_n_0 ), .I4(out[4]), .I5(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(\fine_dec_cnt[5]_i_7_n_0 )); LUT2 #( .INIT(4'h1)) \fine_dec_cnt[5]_i_8 (.I0(out[2]), .I1(out[4]), .O(\fine_dec_cnt[5]_i_8_n_0 )); FDRE \fine_dec_cnt_reg[0] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[0]), .Q(fine_dec_cnt__0[0]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \fine_dec_cnt_reg[1] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[1]), .Q(fine_dec_cnt__0[1]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \fine_dec_cnt_reg[2] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[2]), .Q(fine_dec_cnt__0[2]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \fine_dec_cnt_reg[3] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[3]), .Q(fine_dec_cnt__0[3]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \fine_dec_cnt_reg[4] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[4]), .Q(fine_dec_cnt__0[4]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \fine_dec_cnt_reg[5] (.C(CLK), .CE(\fine_dec_cnt_reg[5]_i_1_n_0 ), .D(fine_dec_cnt[5]), .Q(fine_dec_cnt__0[5]), .R(rstdiv0_sync_r1_reg_rep__18)); MUXF7 \fine_dec_cnt_reg[5]_i_1 (.I0(\fine_dec_cnt[5]_i_3_n_0 ), .I1(\fine_dec_cnt[5]_i_4_n_0 ), .O(\fine_dec_cnt_reg[5]_i_1_n_0 ), .S(out[0])); LUT4 #( .INIT(16'h0074)) \fine_inc[0][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[0].final_val_reg_n_0_[0][0] ), .I3(out[4]), .O(fine_inc[0])); LUT5 #( .INIT(32'h090F0900)) \fine_inc[0][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[0].final_val_reg_n_0_[0][1] ), .O(fine_inc[1])); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[0][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[0].final_val_reg_n_0_[0][2] ), .O(fine_inc[2])); LUT5 #( .INIT(32'h060F0600)) \fine_inc[0][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[0].final_val_reg_n_0_[0][3] ), .O(fine_inc[3])); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[0][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[0].final_val_reg_n_0_[0][4] ), .O(fine_inc[4])); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[0][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[0][5]_i_3_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[0][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[0][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[0].final_val_reg_n_0_[0][5] ), .I3(out[4]), .O(fine_inc[5])); (* SOFT_HLUTNM = "soft_lutpair341" *) LUT3 #( .INIT(8'h01)) \fine_inc[0][5]_i_3 (.I0(dqs_count_r[2]), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .O(\fine_inc[0][5]_i_3_n_0 )); LUT4 #( .INIT(16'h0074)) \fine_inc[1][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[1].final_val_reg_n_0_[1][0] ), .I3(out[4]), .O(\fine_inc[1][0]_i_1_n_0 )); LUT5 #( .INIT(32'h090F0900)) \fine_inc[1][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[1].final_val_reg_n_0_[1][1] ), .O(\fine_inc[1][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[1][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[1].final_val_reg_n_0_[1][2] ), .O(\fine_inc[1][2]_i_1_n_0 )); LUT5 #( .INIT(32'h060F0600)) \fine_inc[1][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[1].final_val_reg_n_0_[1][3] ), .O(\fine_inc[1][3]_i_1_n_0 )); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[1][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[1].final_val_reg_n_0_[1][4] ), .O(\fine_inc[1][4]_i_1_n_0 )); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[1][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[1][5]_i_3_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[1][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[1][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[1].final_val_reg_n_0_[1][5] ), .I3(out[4]), .O(\fine_inc[1][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair341" *) LUT3 #( .INIT(8'h04)) \fine_inc[1][5]_i_3 (.I0(dqs_count_r[2]), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .O(\fine_inc[1][5]_i_3_n_0 )); LUT4 #( .INIT(16'h0074)) \fine_inc[2][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[2].final_val_reg_n_0_[2][0] ), .I3(out[4]), .O(\fine_inc[2][0]_i_1_n_0 )); LUT5 #( .INIT(32'h090F0900)) \fine_inc[2][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[2].final_val_reg_n_0_[2][1] ), .O(\fine_inc[2][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[2][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[2].final_val_reg_n_0_[2][2] ), .O(\fine_inc[2][2]_i_1_n_0 )); LUT5 #( .INIT(32'h060F0600)) \fine_inc[2][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[2].final_val_reg_n_0_[2][3] ), .O(\fine_inc[2][3]_i_1_n_0 )); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[2][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[2].final_val_reg_n_0_[2][4] ), .O(\fine_inc[2][4]_i_1_n_0 )); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[2][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[2][5]_i_3_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[2][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[2][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[2].final_val_reg_n_0_[2][5] ), .I3(out[4]), .O(\fine_inc[2][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair342" *) LUT3 #( .INIT(8'h04)) \fine_inc[2][5]_i_3 (.I0(dqs_count_r[2]), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .O(\fine_inc[2][5]_i_3_n_0 )); LUT4 #( .INIT(16'h0074)) \fine_inc[3][0]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(out[1]), .I2(\gen_final_tap[3].final_val_reg_n_0_[3][0] ), .I3(out[4]), .O(\fine_inc[3][0]_i_1_n_0 )); LUT5 #( .INIT(32'h090F0900)) \fine_inc[3][1]_i_1 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[3].final_val_reg_n_0_[3][1] ), .O(\fine_inc[3][1]_i_1_n_0 )); LUT6 #( .INIT(64'h00E100FF00E10000)) \fine_inc[3][2]_i_1 (.I0(\fine_inc[3][2]_i_2_n_0 ), .I1(\fine_inc[3][2]_i_3_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[3].final_val_reg_n_0_[3][2] ), .O(\fine_inc[3][2]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][2]_i_2 (.I0(\fine_inc_reg_n_0_[3][1] ), .I1(\fine_inc_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][1] ), .O(\fine_inc[3][2]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][2]_i_3 (.I0(\fine_inc_reg_n_0_[3][0] ), .I1(\fine_inc_reg_n_0_[1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][0] ), .O(\fine_inc[3][2]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][2]_i_4 (.I0(\fine_inc_reg_n_0_[3][2] ), .I1(\fine_inc_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][2] ), .O(\fine_inc[3][2]_i_4_n_0 )); LUT5 #( .INIT(32'h060F0600)) \fine_inc[3][3]_i_1 (.I0(\fine_inc[3][4]_i_3_n_0 ), .I1(\fine_inc[3][4]_i_2_n_0 ), .I2(out[4]), .I3(out[1]), .I4(\gen_final_tap[3].final_val_reg_n_0_[3][3] ), .O(\fine_inc[3][3]_i_1_n_0 )); LUT6 #( .INIT(64'h00D200FF00D20000)) \fine_inc[3][4]_i_1 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(out[4]), .I4(out[1]), .I5(\gen_final_tap[3].final_val_reg_n_0_[3][4] ), .O(\fine_inc[3][4]_i_1_n_0 )); LUT3 #( .INIT(8'h01)) \fine_inc[3][4]_i_2 (.I0(\fine_inc[3][2]_i_3_n_0 ), .I1(\fine_inc[3][2]_i_2_n_0 ), .I2(\fine_inc[3][2]_i_4_n_0 ), .O(\fine_inc[3][4]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][4]_i_3 (.I0(\fine_inc_reg_n_0_[3][3] ), .I1(\fine_inc_reg_n_0_[1][3] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][3] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][3] ), .O(\fine_inc[3][4]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][4]_i_4 (.I0(\fine_inc_reg_n_0_[3][4] ), .I1(\fine_inc_reg_n_0_[1][4] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][4] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][4] ), .O(\fine_inc[3][4]_i_4_n_0 )); LUT6 #( .INIT(64'h008000800A800080)) \fine_inc[3][5]_i_1 (.I0(\fine_inc[3][5]_i_3_n_0 ), .I1(dqs_count_r140_out), .I2(out[2]), .I3(out[1]), .I4(\fine_inc[3][5]_i_5_n_0 ), .I5(\fine_inc[3][5]_i_6_n_0 ), .O(\fine_inc[3][5]_i_1_n_0 )); LUT4 #( .INIT(16'h88B8)) \fine_inc[3][5]_i_2 (.I0(\fine_inc[3][5]_i_7_n_0 ), .I1(out[1]), .I2(\gen_final_tap[3].final_val_reg_n_0_[3][5] ), .I3(out[4]), .O(\fine_inc[3][5]_i_2_n_0 )); LUT3 #( .INIT(8'h08)) \fine_inc[3][5]_i_3 (.I0(out[0]), .I1(out[3]), .I2(out[4]), .O(\fine_inc[3][5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair345" *) LUT2 #( .INIT(4'h2)) \fine_inc[3][5]_i_4 (.I0(wr_level_done_r4), .I1(wr_level_done_r5), .O(dqs_count_r140_out)); (* SOFT_HLUTNM = "soft_lutpair318" *) LUT3 #( .INIT(8'h40)) \fine_inc[3][5]_i_5 (.I0(dqs_count_r[2]), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .O(\fine_inc[3][5]_i_5_n_0 )); LUT5 #( .INIT(32'h0100FFFF)) \fine_inc[3][5]_i_6 (.I0(\fine_inc[3][5]_i_8_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(\fine_inc[3][4]_i_2_n_0 ), .I4(wr_level_done_r5), .O(\fine_inc[3][5]_i_6_n_0 )); LUT5 #( .INIT(32'h0000FD02)) \fine_inc[3][5]_i_7 (.I0(\fine_inc[3][4]_i_2_n_0 ), .I1(\fine_inc[3][4]_i_3_n_0 ), .I2(\fine_inc[3][4]_i_4_n_0 ), .I3(\fine_inc[3][5]_i_8_n_0 ), .I4(out[4]), .O(\fine_inc[3][5]_i_7_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \fine_inc[3][5]_i_8 (.I0(\fine_inc_reg_n_0_[3][5] ), .I1(\fine_inc_reg_n_0_[1][5] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\fine_inc_reg_n_0_[2][5] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\fine_inc_reg_n_0_[0][5] ), .O(\fine_inc[3][5]_i_8_n_0 )); FDRE \fine_inc_reg[0][0] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[0]), .Q(\fine_inc_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[0][1] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[1]), .Q(\fine_inc_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[0][2] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[2]), .Q(\fine_inc_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[0][3] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[3]), .Q(\fine_inc_reg_n_0_[0][3] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[0][4] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[4]), .Q(\fine_inc_reg_n_0_[0][4] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[0][5] (.C(CLK), .CE(\fine_inc[0][5]_i_1_n_0 ), .D(fine_inc[5]), .Q(\fine_inc_reg_n_0_[0][5] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[1][0] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][0]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[1][1] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][1]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[1][2] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][2]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[1][3] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][3]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][3] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[1][4] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][4]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[1][4] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[1][5] (.C(CLK), .CE(\fine_inc[1][5]_i_1_n_0 ), .D(\fine_inc[1][5]_i_2_n_0 ), .Q(\fine_inc_reg_n_0_[1][5] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[2][0] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][0]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[2][1] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][1]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[2][2] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][2]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[2][3] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][3]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][3] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[2][4] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][4]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[2][4] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[2][5] (.C(CLK), .CE(\fine_inc[2][5]_i_1_n_0 ), .D(\fine_inc[2][5]_i_2_n_0 ), .Q(\fine_inc_reg_n_0_[2][5] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[3][0] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][0]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[3][1] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][1]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[3][2] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][2]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[3][3] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][3]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][3] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[3][4] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][4]_i_1_n_0 ), .Q(\fine_inc_reg_n_0_[3][4] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \fine_inc_reg[3][5] (.C(CLK), .CE(\fine_inc[3][5]_i_1_n_0 ), .D(\fine_inc[3][5]_i_2_n_0 ), .Q(\fine_inc_reg_n_0_[3][5] ), .R(rstdiv0_sync_r1_reg_rep__17)); LUT5 #( .INIT(32'h00820000)) flag_ck_negedge_i_10 (.I0(out[1]), .I1(out[2]), .I2(out[3]), .I3(out[4]), .I4(out[0]), .O(flag_ck_negedge_i_10_n_0)); (* SOFT_HLUTNM = "soft_lutpair314" *) LUT3 #( .INIT(8'h7F)) flag_ck_negedge_i_2 (.I0(\stable_cnt_reg_n_0_[3] ), .I1(\stable_cnt_reg_n_0_[2] ), .I2(\stable_cnt_reg_n_0_[1] ), .O(stable_cnt1)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) flag_ck_negedge_i_3 (.I0(\rd_data_previous_r_reg_n_0_[3] ), .I1(\rd_data_previous_r_reg_n_0_[2] ), .I2(\dqs_count_r_reg[1]_rep_n_0 ), .I3(\rd_data_previous_r_reg_n_0_[1] ), .I4(\dqs_count_r_reg[0]_rep_n_0 ), .I5(\rd_data_previous_r_reg_n_0_[0] ), .O(stable_cnt227_in)); LUT6 #( .INIT(64'h0040FFFF00400040)) flag_ck_negedge_i_4 (.I0(out[1]), .I1(out[2]), .I2(flag_ck_negedge_i_6_n_0), .I3(out[3]), .I4(flag_ck_negedge_i_7_n_0), .I5(stable_cnt227_in), .O(flag_ck_negedge09_out)); LUT4 #( .INIT(16'hFFFE)) flag_ck_negedge_i_5 (.I0(\stable_cnt[3]_i_6_n_0 ), .I1(wr_level_done_r1_reg_0), .I2(flag_ck_negedge_i_8_n_0), .I3(rstdiv0_sync_r1_reg_rep__20), .O(flag_ck_negedge_reg_0)); LUT2 #( .INIT(4'h1)) flag_ck_negedge_i_6 (.I0(out[4]), .I1(out[0]), .O(flag_ck_negedge_i_6_n_0)); LUT6 #( .INIT(64'h0000000000000001)) flag_ck_negedge_i_7 (.I0(\stable_cnt_reg_n_0_[2] ), .I1(\stable_cnt_reg_n_0_[3] ), .I2(p_1_in_0), .I3(flag_ck_negedge_i_10_n_0), .I4(\stable_cnt_reg[3]_0 ), .I5(\stable_cnt_reg_n_0_[1] ), .O(flag_ck_negedge_i_7_n_0)); LUT4 #( .INIT(16'h4000)) flag_ck_negedge_i_8 (.I0(out[2]), .I1(out[3]), .I2(out[0]), .I3(out[4]), .O(flag_ck_negedge_i_8_n_0)); LUT5 #( .INIT(32'h10000000)) flag_ck_negedge_i_9 (.I0(out[4]), .I1(out[0]), .I2(out[3]), .I3(out[2]), .I4(out[1]), .O(p_1_in_0)); FDRE flag_ck_negedge_reg (.C(CLK), .CE(1'b1), .D(flag_ck_negedge_reg_1), .Q(\rd_data_edge_detect_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAAAAAA8AAAAA)) flag_init_i_1 (.I0(flag_init), .I1(\wl_state_r1_reg_n_0_[0] ), .I2(p_1_in28_in), .I3(\wl_state_r1_reg_n_0_[4] ), .I4(\wl_state_r1_reg_n_0_[2] ), .I5(\wl_state_r1_reg_n_0_[3] ), .O(flag_init_i_1_n_0)); LUT5 #( .INIT(32'h04000000)) flag_init_i_2 (.I0(out[3]), .I1(out[0]), .I2(out[4]), .I3(out[2]), .I4(out[1]), .O(p_1_in28_in)); FDSE flag_init_reg (.C(CLK), .CE(1'b1), .D(flag_init_i_1_n_0), .Q(flag_init), .S(rstdiv0_sync_r1_reg_rep__18)); LUT6 #( .INIT(64'h00000000EEEE22E2)) \gen_byte_sel_div1.byte_sel_cnt[0]_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ), .I1(pi_f_inc_reg), .I2(dqs_count_r[0]), .I3(wrlvl_done_r_reg), .I4(oclkdelay_calib_done_r_reg_0), .I5(delay_done_r4_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[0] )); LUT6 #( .INIT(64'h00000000EEEE22E2)) \gen_byte_sel_div1.byte_sel_cnt[1]_i_1 (.I0(\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ), .I1(pi_f_inc_reg), .I2(dqs_count_r[1]), .I3(wrlvl_done_r_reg), .I4(oclkdelay_calib_done_r_reg_1), .I5(delay_done_r4_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[1] )); LUT6 #( .INIT(64'h00000000EEE222E2)) \gen_byte_sel_div1.byte_sel_cnt[2]_i_1 (.I0(byte_sel_cnt), .I1(pi_f_inc_reg), .I2(dqs_count_r[2]), .I3(wrlvl_done_r_reg), .I4(\prbs_dqs_cnt_r_reg[2] ), .I5(delay_done_r4_reg), .O(\gen_byte_sel_div1.byte_sel_cnt_reg[2] )); LUT2 #( .INIT(4'h2)) \gen_final_tap[0].final_val[0][5]_i_1 (.I0(wr_level_done_r2), .I1(wr_level_done_r3), .O(p_21_out)); FDRE \gen_final_tap[0].final_val_reg[0][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [0]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][0] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[0].final_val_reg[0][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [1]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][1] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[0].final_val_reg[0][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [2]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][2] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[0].final_val_reg[0][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [3]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][3] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[0].final_val_reg[0][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [4]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][4] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[0].final_val_reg[0][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[0]__0 [5]), .Q(\gen_final_tap[0].final_val_reg_n_0_[0][5] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[1].final_val_reg[1][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [0]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][0] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[1].final_val_reg[1][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [1]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][1] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[1].final_val_reg[1][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [2]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][2] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[1].final_val_reg[1][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [3]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][3] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[1].final_val_reg[1][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [4]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][4] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[1].final_val_reg[1][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[1]__0 [5]), .Q(\gen_final_tap[1].final_val_reg_n_0_[1][5] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[2].final_val_reg[2][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [0]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][0] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \gen_final_tap[2].final_val_reg[2][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [1]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][1] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \gen_final_tap[2].final_val_reg[2][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [2]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][2] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \gen_final_tap[2].final_val_reg[2][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [3]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][3] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \gen_final_tap[2].final_val_reg[2][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [4]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][4] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \gen_final_tap[2].final_val_reg[2][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[2]__0 [5]), .Q(\gen_final_tap[2].final_val_reg_n_0_[2][5] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \gen_final_tap[3].final_val_reg[3][0] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [0]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][0] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[3].final_val_reg[3][1] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [1]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][1] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[3].final_val_reg[3][2] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [2]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][2] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[3].final_val_reg[3][3] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [3]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][3] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[3].final_val_reg[3][4] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [4]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][4] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_final_tap[3].final_val_reg[3][5] (.C(CLK), .CE(p_21_out), .D(\smallest_reg[3]__0 [5]), .Q(\gen_final_tap[3].final_val_reg_n_0_[3][5] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \gen_rd[0].rd_data_rise_wl_r_reg[0] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ), .Q(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .R(1'b0)); FDRE \gen_rd[1].rd_data_rise_wl_r_reg[1] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ), .Q(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .R(1'b0)); FDRE \gen_rd[2].rd_data_rise_wl_r_reg[2] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ), .Q(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .R(1'b0)); FDRE \gen_rd[3].rd_data_rise_wl_r_reg[3] (.C(CLK), .CE(1'b1), .D(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ), .Q(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .R(1'b0)); LUT1 #( .INIT(2'h1)) \incdec_wait_cnt[0]_i_1 (.I0(incdec_wait_cnt_reg__0[0]), .O(p_0_in__0__0[0])); (* SOFT_HLUTNM = "soft_lutpair350" *) LUT2 #( .INIT(4'h6)) \incdec_wait_cnt[1]_i_1 (.I0(incdec_wait_cnt_reg__0[0]), .I1(incdec_wait_cnt_reg__0[1]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair350" *) LUT3 #( .INIT(8'h6A)) \incdec_wait_cnt[2]_i_1 (.I0(incdec_wait_cnt_reg__0[2]), .I1(incdec_wait_cnt_reg__0[1]), .I2(incdec_wait_cnt_reg__0[0]), .O(p_0_in__0__0[2])); LUT6 #( .INIT(64'hFFFBFFEFFEFFFFFF)) \incdec_wait_cnt[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(out[1]), .I2(out[0]), .I3(out[4]), .I4(out[2]), .I5(out[3]), .O(\incdec_wait_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair321" *) LUT4 #( .INIT(16'h6AAA)) \incdec_wait_cnt[3]_i_2 (.I0(incdec_wait_cnt_reg__0[3]), .I1(incdec_wait_cnt_reg__0[0]), .I2(incdec_wait_cnt_reg__0[1]), .I3(incdec_wait_cnt_reg__0[2]), .O(p_0_in__0__0[3])); FDRE \incdec_wait_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[0]), .Q(incdec_wait_cnt_reg__0[0]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); FDRE \incdec_wait_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[1]), .Q(incdec_wait_cnt_reg__0[1]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); FDRE \incdec_wait_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[2]), .Q(incdec_wait_cnt_reg__0[2]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); FDRE \incdec_wait_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(p_0_in__0__0[3]), .Q(incdec_wait_cnt_reg__0[3]), .R(\incdec_wait_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'h2F203F3F2F203333)) inhibit_edge_detect_r_i_2 (.I0(wrlvl_byte_redo), .I1(out[3]), .I2(out[4]), .I3(stable_cnt227_in), .I4(out[2]), .I5(\FSM_sequential_wl_state_r[3]_i_10_n_0 ), .O(inhibit_edge_detect_r)); LUT6 #( .INIT(64'h0000008303080003)) inhibit_edge_detect_r_i_3 (.I0(inhibit_edge_detect_r_i_4_n_0), .I1(out[2]), .I2(out[4]), .I3(out[3]), .I4(out[1]), .I5(out[0]), .O(inhibit_edge_detect_r_reg_0)); LUT6 #( .INIT(64'h8080808080808F80)) inhibit_edge_detect_r_i_4 (.I0(wrlvl_byte_redo), .I1(\FSM_sequential_wl_state_r[2]_i_6_n_0 ), .I2(out[4]), .I3(wl_sm_start), .I4(stable_cnt1), .I5(stable_cnt227_in), .O(inhibit_edge_detect_r_i_4_n_0)); FDSE inhibit_edge_detect_r_reg (.C(CLK), .CE(1'b1), .D(inhibit_edge_detect_r_reg_1), .Q(\rd_data_edge_detect_r_reg[0]_1 ), .S(rstdiv0_sync_r1_reg_rep__15)); LUT6 #( .INIT(64'h222222F2F2F2F2FF)) \lim_state[12]_i_6 (.I0(\stg2_target_r_reg[4] [1]), .I1(\stg2_tap_cnt_reg[2] [2]), .I2(\stg2_target_r_reg[4] [0]), .I3(\stg2_r_reg[0] ), .I4(\stg2_tap_cnt_reg[2] [0]), .I5(\stg2_tap_cnt_reg[2] [1]), .O(\lim_state_reg[12] )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .I4(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ), .O(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .I3(my_empty), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .O(\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .I4(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ), .O(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ), .I3(my_empty_6), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ), .O(\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ), .I4(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ), .O(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ), .I3(my_empty_7), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ), .O(\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ), .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ), .I4(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ), .O(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000001105)) \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2 (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ), .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .I3(my_empty_8), .I4(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ), .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ), .O(\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 )); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 " *) SRL16E phy_ctl_ready_r4_reg_srl4 (.A0(1'b1), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(\mcGo_r_reg[15] ), .Q(phy_ctl_ready_r4_reg_srl4_n_0)); FDRE phy_ctl_ready_r5_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_ready_r4_reg_srl4_n_0), .Q(phy_ctl_ready_r5), .R(1'b0)); FDRE phy_ctl_ready_r6_reg (.C(CLK), .CE(1'b1), .D(phy_ctl_ready_r5), .Q(phy_ctl_ready_r6_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair316" *) LUT5 #( .INIT(32'hFFFFFDFF)) po_cnt_dec_i_2 (.I0(wait_cnt_reg__0[0]), .I1(wait_cnt_reg__0[1]), .I2(wait_cnt_reg__0[3]), .I3(phy_ctl_ready_r6_reg_n_0), .I4(wait_cnt_reg__0[2]), .O(po_cnt_dec_reg_0)); FDRE po_cnt_dec_reg (.C(CLK), .CE(1'b1), .D(\wait_cnt_reg[0]_0 ), .Q(dqs_po_en_stg2_f_reg_0), .R(1'b0)); LUT3 #( .INIT(8'hF4)) po_dec_done_i_1 (.I0(po_dec_done_i_2_n_0), .I1(po_dec_done_i_3_n_0), .I2(po_dec_done), .O(po_dec_done_i_1_n_0)); LUT5 #( .INIT(32'hEEEFFFEF)) po_dec_done_i_2 (.I0(po_rdval_cnt[2]), .I1(po_rdval_cnt[1]), .I2(phy_ctl_ready_r6_reg_n_0), .I3(po_rdval_cnt[0]), .I4(dqs_po_en_stg2_f_reg_0), .O(po_dec_done_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000001)) po_dec_done_i_3 (.I0(po_rdval_cnt[7]), .I1(po_rdval_cnt[3]), .I2(po_rdval_cnt[4]), .I3(po_rdval_cnt[5]), .I4(po_rdval_cnt[6]), .I5(po_rdval_cnt[8]), .O(po_dec_done_i_3_n_0)); FDRE po_dec_done_reg (.C(CLK), .CE(1'b1), .D(po_dec_done_i_1_n_0), .Q(po_dec_done), .R(rstdiv0_sync_r1_reg_rep__18)); LUT6 #( .INIT(64'hAC00AC00ACFFAC00)) \po_rdval_cnt[0]_i_1 (.I0(\po_counter_read_val_reg[8] [0]), .I1(\po_counter_read_val_reg[8]_0 [0]), .I2(\calib_sel_reg[3] ), .I3(\po_rdval_cnt[8]_i_4_n_0 ), .I4(\po_rdval_cnt_reg[0]_0 ), .I5(po_rdval_cnt[0]), .O(\po_rdval_cnt[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFB0808080808FB08)) \po_rdval_cnt[1]_i_1 (.I0(\po_counter_read_val_reg[5] [0]), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(\po_rdval_cnt_reg[0]_0 ), .I4(po_rdval_cnt[0]), .I5(po_rdval_cnt[1]), .O(\po_rdval_cnt[1]_i_1_n_0 )); LUT6 #( .INIT(64'hB8B8B888888888B8)) \po_rdval_cnt[2]_i_1 (.I0(\po_counter_read_val_reg[5] [1]), .I1(\po_rdval_cnt[8]_i_4_n_0 ), .I2(\po_rdval_cnt_reg[0]_0 ), .I3(po_rdval_cnt[1]), .I4(po_rdval_cnt[0]), .I5(po_rdval_cnt[2]), .O(\po_rdval_cnt[2]_i_1_n_0 )); LUT6 #( .INIT(64'hAC00ACFFACFFAC00)) \po_rdval_cnt[3]_i_1 (.I0(\po_counter_read_val_reg[8] [1]), .I1(\po_counter_read_val_reg[8]_0 [1]), .I2(\calib_sel_reg[3] ), .I3(\po_rdval_cnt[8]_i_4_n_0 ), .I4(po_rdval_cnt[3]), .I5(\po_rdval_cnt[4]_i_2_n_0 ), .O(\po_rdval_cnt[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFB0808FBFB08FB08)) \po_rdval_cnt[4]_i_1 (.I0(\po_counter_read_val_reg[5] [2]), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(po_rdval_cnt[4]), .I4(po_rdval_cnt[3]), .I5(\po_rdval_cnt[4]_i_2_n_0 ), .O(\po_rdval_cnt[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0001)) \po_rdval_cnt[4]_i_2 (.I0(po_rdval_cnt[1]), .I1(po_rdval_cnt[0]), .I2(po_rdval_cnt[2]), .I3(po_dec_done_i_3_n_0), .O(\po_rdval_cnt[4]_i_2_n_0 )); LUT6 #( .INIT(64'hFB0808080808FB08)) \po_rdval_cnt[5]_i_1 (.I0(\po_counter_read_val_reg[5] [3]), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(\po_rdval_cnt_reg[0]_0 ), .I4(\po_rdval_cnt[5]_i_2_n_0 ), .I5(po_rdval_cnt[5]), .O(\po_rdval_cnt[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair315" *) LUT5 #( .INIT(32'hFFFFFFFE)) \po_rdval_cnt[5]_i_2 (.I0(po_rdval_cnt[3]), .I1(po_rdval_cnt[4]), .I2(po_rdval_cnt[1]), .I3(po_rdval_cnt[0]), .I4(po_rdval_cnt[2]), .O(\po_rdval_cnt[5]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFACFF0000AC00)) \po_rdval_cnt[6]_i_1 (.I0(\po_counter_read_val_reg[8] [2]), .I1(\po_counter_read_val_reg[8]_0 [2]), .I2(\calib_sel_reg[3] ), .I3(phy_ctl_ready_r5), .I4(phy_ctl_ready_r6_reg_n_0), .I5(\po_rdval_cnt[6]_i_2_n_0 ), .O(\po_rdval_cnt[6]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAA8A00000020)) \po_rdval_cnt[6]_i_2 (.I0(\po_rdval_cnt_reg[0]_0 ), .I1(po_rdval_cnt[5]), .I2(\po_rdval_cnt[8]_i_7_n_0 ), .I3(po_rdval_cnt[4]), .I4(po_rdval_cnt[3]), .I5(po_rdval_cnt[6]), .O(\po_rdval_cnt[6]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFACFF0000AC00)) \po_rdval_cnt[7]_i_1 (.I0(\po_counter_read_val_reg[8] [3]), .I1(\po_counter_read_val_reg[8]_0 [3]), .I2(\calib_sel_reg[3] ), .I3(phy_ctl_ready_r5), .I4(phy_ctl_ready_r6_reg_n_0), .I5(\po_rdval_cnt[7]_i_2_n_0 ), .O(\po_rdval_cnt[7]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFC00000002)) \po_rdval_cnt[7]_i_2 (.I0(po_rdval_cnt[8]), .I1(po_rdval_cnt[1]), .I2(po_rdval_cnt[0]), .I3(po_rdval_cnt[2]), .I4(\po_rdval_cnt[8]_i_6_n_0 ), .I5(po_rdval_cnt[7]), .O(\po_rdval_cnt[7]_i_2_n_0 )); LUT4 #( .INIT(16'hAEFF)) \po_rdval_cnt[8]_i_1 (.I0(dqs_po_en_stg2_f_reg_0), .I1(phy_ctl_ready_r5), .I2(phy_ctl_ready_r6_reg_n_0), .I3(\po_rdval_cnt_reg[0]_0 ), .O(\po_rdval_cnt[8]_i_1_n_0 )); LUT6 #( .INIT(64'hACFFAC00AC00AC00)) \po_rdval_cnt[8]_i_2 (.I0(\po_counter_read_val_reg[8] [4]), .I1(\po_counter_read_val_reg[8]_0 [4]), .I2(\calib_sel_reg[3] ), .I3(\po_rdval_cnt[8]_i_4_n_0 ), .I4(po_rdval_cnt[8]), .I5(\po_rdval_cnt[8]_i_5_n_0 ), .O(\po_rdval_cnt[8]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \po_rdval_cnt[8]_i_3 (.I0(po_rdval_cnt[8]), .I1(po_rdval_cnt[1]), .I2(po_rdval_cnt[0]), .I3(po_rdval_cnt[2]), .I4(\po_rdval_cnt[8]_i_6_n_0 ), .I5(po_rdval_cnt[7]), .O(\po_rdval_cnt_reg[0]_0 )); LUT2 #( .INIT(4'h2)) \po_rdval_cnt[8]_i_4 (.I0(phy_ctl_ready_r5), .I1(phy_ctl_ready_r6_reg_n_0), .O(\po_rdval_cnt[8]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \po_rdval_cnt[8]_i_5 (.I0(po_rdval_cnt[7]), .I1(po_rdval_cnt[3]), .I2(po_rdval_cnt[4]), .I3(po_rdval_cnt[5]), .I4(po_rdval_cnt[6]), .I5(\po_rdval_cnt[8]_i_7_n_0 ), .O(\po_rdval_cnt[8]_i_5_n_0 )); LUT4 #( .INIT(16'hFFFE)) \po_rdval_cnt[8]_i_6 (.I0(po_rdval_cnt[3]), .I1(po_rdval_cnt[4]), .I2(po_rdval_cnt[5]), .I3(po_rdval_cnt[6]), .O(\po_rdval_cnt[8]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair315" *) LUT3 #( .INIT(8'h01)) \po_rdval_cnt[8]_i_7 (.I0(po_rdval_cnt[2]), .I1(po_rdval_cnt[0]), .I2(po_rdval_cnt[1]), .O(\po_rdval_cnt[8]_i_7_n_0 )); FDRE \po_rdval_cnt_reg[0] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[0]_i_1_n_0 ), .Q(po_rdval_cnt[0]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[1] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[1]_i_1_n_0 ), .Q(po_rdval_cnt[1]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[2] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[2]_i_1_n_0 ), .Q(po_rdval_cnt[2]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[3] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[3]_i_1_n_0 ), .Q(po_rdval_cnt[3]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[4] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[4]_i_1_n_0 ), .Q(po_rdval_cnt[4]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[5] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[5]_i_1_n_0 ), .Q(po_rdval_cnt[5]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[6] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[6]_i_1_n_0 ), .Q(po_rdval_cnt[6]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[7] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[7]_i_1_n_0 ), .Q(po_rdval_cnt[7]), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \po_rdval_cnt_reg[8] (.C(CLK), .CE(\po_rdval_cnt[8]_i_1_n_0 ), .D(\po_rdval_cnt[8]_i_2_n_0 ), .Q(po_rdval_cnt[8]), .R(rstdiv0_sync_r1_reg_rep__15)); (* SOFT_HLUTNM = "soft_lutpair349" *) LUT3 #( .INIT(8'h38)) \rank_cnt_r[0]_i_1 (.I0(\rank_cnt_r_reg[0]_0 ), .I1(rank_cnt_r), .I2(\rank_cnt_r_reg[0]_1 ), .O(\rank_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair349" *) LUT3 #( .INIT(8'h78)) \rank_cnt_r[1]_i_1 (.I0(\rank_cnt_r_reg[0]_1 ), .I1(rank_cnt_r), .I2(\rank_cnt_r_reg[0]_0 ), .O(\rank_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \rank_cnt_r[1]_i_2 (.I0(out[4]), .I1(out[2]), .I2(out[1]), .I3(out[0]), .I4(p_0_in), .I5(out[3]), .O(rank_cnt_r)); FDRE \rank_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rank_cnt_r[0]_i_1_n_0 ), .Q(\rank_cnt_r_reg[0]_1 ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \rank_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rank_cnt_r[1]_i_1_n_0 ), .Q(\rank_cnt_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__17)); (* SOFT_HLUTNM = "soft_lutpair344" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[0]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .I2(\rd_data_previous_r_reg_n_0_[0] ), .O(\rd_data_edge_detect_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair344" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[1]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .I2(\rd_data_previous_r_reg_n_0_[1] ), .O(\rd_data_edge_detect_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair346" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[2]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .I2(\rd_data_previous_r_reg_n_0_[2] ), .O(\rd_data_edge_detect_r[2]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \rd_data_edge_detect_r[3]_i_1 (.I0(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I1(\rd_data_edge_detect_r_reg[0]_1 ), .I2(flag_init), .I3(rstdiv0_sync_r1_reg_rep__23), .I4(\rd_data_edge_detect_r_reg[0]_0 ), .O(rd_data_edge_detect_r0)); LUT6 #( .INIT(64'h49484044FFFFFFFF)) \rd_data_edge_detect_r[3]_i_2 (.I0(out[3]), .I1(out[2]), .I2(out[4]), .I3(out[0]), .I4(out[1]), .I5(\rd_data_edge_detect_r[3]_i_5_n_0 ), .O(\rd_data_edge_detect_r[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair346" *) LUT3 #( .INIT(8'h08)) \rd_data_edge_detect_r[3]_i_3 (.I0(\rd_data_edge_detect_r[3]_i_6_n_0 ), .I1(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .I2(\rd_data_previous_r_reg_n_0_[3] ), .O(\rd_data_edge_detect_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \rd_data_edge_detect_r[3]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[0] ), .I1(\wl_tap_count_r_reg_n_0_[1] ), .I2(\wl_tap_count_r_reg_n_0_[2] ), .I3(\wl_tap_count_r_reg_n_0_[3] ), .I4(\wl_tap_count_r_reg_n_0_[5] ), .I5(\wl_tap_count_r_reg_n_0_[4] ), .O(\rd_data_edge_detect_r[3]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \rd_data_edge_detect_r[3]_i_5 (.I0(\rd_data_edge_detect_r_reg_n_0_[3] ), .I1(\rd_data_edge_detect_r_reg_n_0_[2] ), .I2(\dqs_count_r_reg[1]_rep_n_0 ), .I3(\rd_data_edge_detect_r_reg_n_0_[1] ), .I4(\dqs_count_r_reg[0]_rep_n_0 ), .I5(\rd_data_edge_detect_r_reg_n_0_[0] ), .O(\rd_data_edge_detect_r[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair314" *) LUT5 #( .INIT(32'h000080FF)) \rd_data_edge_detect_r[3]_i_6 (.I0(\stable_cnt_reg_n_0_[3] ), .I1(\stable_cnt_reg_n_0_[2] ), .I2(\stable_cnt_reg_n_0_[1] ), .I3(stable_cnt227_in), .I4(\rd_data_edge_detect_r[3]_i_5_n_0 ), .O(\rd_data_edge_detect_r[3]_i_6_n_0 )); FDRE \rd_data_edge_detect_r_reg[0] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[0]_i_1_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[0] ), .R(rd_data_edge_detect_r0)); FDRE \rd_data_edge_detect_r_reg[1] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[1]_i_1_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[1] ), .R(rd_data_edge_detect_r0)); FDRE \rd_data_edge_detect_r_reg[2] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[2]_i_1_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[2] ), .R(rd_data_edge_detect_r0)); FDRE \rd_data_edge_detect_r_reg[3] (.C(CLK), .CE(\rd_data_edge_detect_r[3]_i_2_n_0 ), .D(\rd_data_edge_detect_r[3]_i_3_n_0 ), .Q(\rd_data_edge_detect_r_reg_n_0_[3] ), .R(rd_data_edge_detect_r0)); LUT6 #( .INIT(64'hAAEEAAAAFFABAAFA)) \rd_data_previous_r[3]_i_1 (.I0(\rd_data_previous_r[3]_i_2_n_0 ), .I1(out[1]), .I2(out[0]), .I3(out[4]), .I4(out[2]), .I5(out[3]), .O(rd_data_previous_r0)); LUT6 #( .INIT(64'hFFFFFFFF00000020)) \rd_data_previous_r[3]_i_2 (.I0(\FSM_sequential_wl_state_r_reg[0]_0 ), .I1(\rd_data_previous_r[3]_i_3_n_0 ), .I2(out[3]), .I3(out[2]), .I4(out[1]), .I5(\rd_data_previous_r[3]_i_4_n_0 ), .O(\rd_data_previous_r[3]_i_2_n_0 )); LUT2 #( .INIT(4'hB)) \rd_data_previous_r[3]_i_3 (.I0(out[0]), .I1(out[4]), .O(\rd_data_previous_r[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000400)) \rd_data_previous_r[3]_i_4 (.I0(\wl_state_r1_reg_n_0_[0] ), .I1(p_0_in32_in), .I2(\wl_state_r1_reg_n_0_[4] ), .I3(\wl_state_r1_reg_n_0_[2] ), .I4(\wl_state_r1_reg_n_0_[3] ), .I5(\wl_state_r1_reg_n_0_[1] ), .O(\rd_data_previous_r[3]_i_4_n_0 )); LUT5 #( .INIT(32'h00000100)) \rd_data_previous_r[3]_i_5 (.I0(out[3]), .I1(out[4]), .I2(out[0]), .I3(out[1]), .I4(out[2]), .O(p_0_in32_in)); FDRE \rd_data_previous_r_reg[0] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .Q(\rd_data_previous_r_reg_n_0_[0] ), .R(1'b0)); FDRE \rd_data_previous_r_reg[1] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .Q(\rd_data_previous_r_reg_n_0_[1] ), .R(1'b0)); FDRE \rd_data_previous_r_reg[2] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .Q(\rd_data_previous_r_reg_n_0_[2] ), .R(1'b0)); FDRE \rd_data_previous_r_reg[3] (.C(CLK), .CE(rd_data_previous_r0), .D(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .Q(\rd_data_previous_r_reg_n_0_[3] ), .R(1'b0)); LUT6 #( .INIT(64'h000000000000FBF8)) \single_rank.done_dqs_dec_i_1 (.I0(done_dqs_tap_inc), .I1(oclkdelay_calib_done_r_reg), .I2(done_dqs_dec), .I3(wr_level_done_r1_reg_0), .I4(wr_level_done0), .I5(rstdiv0_sync_r1_reg_rep__23), .O(\single_rank.done_dqs_dec_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair345" *) LUT3 #( .INIT(8'h08)) \single_rank.done_dqs_dec_i_2 (.I0(oclkdelay_calib_done_r_reg), .I1(wr_level_done_r3), .I2(wr_level_done_r4), .O(done_dqs_dec)); (* SOFT_HLUTNM = "soft_lutpair322" *) LUT4 #( .INIT(16'h4F44)) \single_rank.done_dqs_dec_i_3 (.I0(wrlvl_byte_redo_r), .I1(wrlvl_byte_redo), .I2(wrlvl_final_r), .I3(wrlvl_final_mux), .O(wr_level_done0)); FDRE \single_rank.done_dqs_dec_reg (.C(CLK), .CE(1'b1), .D(\single_rank.done_dqs_dec_i_1_n_0 ), .Q(done_dqs_tap_inc), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair332" *) LUT3 #( .INIT(8'hB8)) \smallest[0][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(largest[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][0]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ), .O(\smallest[0][0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair333" *) LUT3 #( .INIT(8'hB8)) \smallest[0][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(largest[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][1]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ), .O(\smallest[0][1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair332" *) LUT3 #( .INIT(8'hB8)) \smallest[0][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(largest[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][2]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ), .O(\smallest[0][2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair334" *) LUT3 #( .INIT(8'hB8)) \smallest[0][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(largest[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][3]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ), .O(\smallest[0][3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair333" *) LUT3 #( .INIT(8'hB8)) \smallest[0][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(largest[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][4]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ), .O(\smallest[0][4]_i_2_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[0][5]_i_2 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[0][5]_i_3_n_0 ), .O(\smallest[0][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair334" *) LUT3 #( .INIT(8'hB8)) \smallest[0][5]_i_3 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(largest[5])); LUT5 #( .INIT(32'hFDFFF7FF)) \smallest[0][5]_i_4 (.I0(out[4]), .I1(out[0]), .I2(out[2]), .I3(out[3]), .I4(out[1]), .O(\smallest[0][5]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \smallest[0][5]_i_5 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ), .I1(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ), .O(\smallest[0][5]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair327" *) LUT3 #( .INIT(8'hB8)) \smallest[1][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(\smallest[1][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair327" *) LUT3 #( .INIT(8'hB8)) \smallest[1][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(\smallest[1][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair330" *) LUT3 #( .INIT(8'hB8)) \smallest[1][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(\smallest[1][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair330" *) LUT3 #( .INIT(8'hB8)) \smallest[1][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(\smallest[1][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair331" *) LUT3 #( .INIT(8'hB8)) \smallest[1][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(\smallest[1][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[1][5]_i_1 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[1][5]_i_3_n_0 ), .O(\smallest[1][5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair331" *) LUT3 #( .INIT(8'hB8)) \smallest[1][5]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(\smallest[1][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair324" *) LUT3 #( .INIT(8'hB8)) \smallest[2][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(\smallest[2][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair324" *) LUT3 #( .INIT(8'hB8)) \smallest[2][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(\smallest[2][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair325" *) LUT3 #( .INIT(8'hB8)) \smallest[2][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(\smallest[2][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair325" *) LUT3 #( .INIT(8'hB8)) \smallest[2][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(\smallest[2][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair329" *) LUT3 #( .INIT(8'hB8)) \smallest[2][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(\smallest[2][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[2][5]_i_1 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[2][5]_i_3_n_0 ), .O(\smallest[2][5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair329" *) LUT3 #( .INIT(8'hB8)) \smallest[2][5]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(\smallest[2][5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair323" *) LUT3 #( .INIT(8'hB8)) \smallest[3][0]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][0]_i_2_n_0 ), .O(\smallest[3][0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair326" *) LUT3 #( .INIT(8'hB8)) \smallest[3][1]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][1]_i_2_n_0 ), .O(\smallest[3][1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair328" *) LUT3 #( .INIT(8'hB8)) \smallest[3][2]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][2]_i_2_n_0 ), .O(\smallest[3][2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair328" *) LUT3 #( .INIT(8'hB8)) \smallest[3][3]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][3]_i_2_n_0 ), .O(\smallest[3][3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair326" *) LUT3 #( .INIT(8'hB8)) \smallest[3][4]_i_1 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][4]_i_2_n_0 ), .O(\smallest[3][4]_i_1_n_0 )); LUT6 #( .INIT(64'h0010FFFF00100000)) \smallest[3][5]_i_1 (.I0(wr_level_done_r2), .I1(oclkdelay_calib_done_r_reg), .I2(wr_level_done_r1), .I3(wrlvl_byte_redo), .I4(\smallest[0][5]_i_4_n_0 ), .I5(\fine_inc[3][5]_i_5_n_0 ), .O(\smallest[3][5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair323" *) LUT3 #( .INIT(8'hB8)) \smallest[3][5]_i_2 (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(\smallest[0][5]_i_5_n_0 ), .O(\smallest[3][5]_i_2_n_0 )); FDRE \smallest_reg[0][0] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[0]), .Q(\smallest_reg[0]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[0][1] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[1]), .Q(\smallest_reg[0]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[0][2] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[2]), .Q(\smallest_reg[0]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[0][3] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[3]), .Q(\smallest_reg[0]__0 [3]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[0][4] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[4]), .Q(\smallest_reg[0]__0 [4]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[0][5] (.C(CLK), .CE(\smallest[0][5]_i_2_n_0 ), .D(largest[5]), .Q(\smallest_reg[0]__0 [5]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[1][0] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][0]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[1][1] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][1]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[1][2] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][2]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[1][3] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][3]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [3]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[1][4] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][4]_i_1_n_0 ), .Q(\smallest_reg[1]__0 [4]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[1][5] (.C(CLK), .CE(\smallest[1][5]_i_1_n_0 ), .D(\smallest[1][5]_i_2_n_0 ), .Q(\smallest_reg[1]__0 [5]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[2][0] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][0]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[2][1] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][1]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[2][2] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][2]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[2][3] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][3]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [3]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[2][4] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][4]_i_1_n_0 ), .Q(\smallest_reg[2]__0 [4]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[2][5] (.C(CLK), .CE(\smallest[2][5]_i_1_n_0 ), .D(\smallest[2][5]_i_2_n_0 ), .Q(\smallest_reg[2]__0 [5]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[3][0] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][0]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[3][1] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][1]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[3][2] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][2]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[3][3] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][3]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [3]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[3][4] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][4]_i_1_n_0 ), .Q(\smallest_reg[3]__0 [4]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \smallest_reg[3][5] (.C(CLK), .CE(\smallest[3][5]_i_1_n_0 ), .D(\smallest[3][5]_i_2_n_0 ), .Q(\smallest_reg[3]__0 [5]), .R(rstdiv0_sync_r1_reg_rep__16)); (* SOFT_HLUTNM = "soft_lutpair352" *) LUT1 #( .INIT(2'h1)) \stable_cnt[0]_i_1 (.I0(\stable_cnt_reg[3]_0 ), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair352" *) LUT2 #( .INIT(4'h6)) \stable_cnt[1]_i_1 (.I0(\stable_cnt_reg[3]_0 ), .I1(\stable_cnt_reg_n_0_[1] ), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair320" *) LUT3 #( .INIT(8'h6A)) \stable_cnt[2]_i_1 (.I0(\stable_cnt_reg_n_0_[2] ), .I1(\stable_cnt_reg_n_0_[1] ), .I2(\stable_cnt_reg[3]_0 ), .O(p_0_in__0[2])); LUT5 #( .INIT(32'hFFFFFFFB)) \stable_cnt[3]_i_1 (.I0(\stable_cnt[3]_i_4_n_0 ), .I1(\smallest[0][5]_i_4_n_0 ), .I2(p_1_in1_in), .I3(rstdiv0_sync_r1_reg_rep__23), .I4(\stable_cnt[3]_i_6_n_0 ), .O(stable_cnt0)); LUT6 #( .INIT(64'h0000000015550000)) \stable_cnt[3]_i_2 (.I0(\rd_data_edge_detect_r[3]_i_4_n_0 ), .I1(\stable_cnt_reg_n_0_[1] ), .I2(\stable_cnt_reg_n_0_[2] ), .I3(\stable_cnt_reg_n_0_[3] ), .I4(\rd_data_previous_r[3]_i_2_n_0 ), .I5(\stable_cnt[3]_i_4_n_0 ), .O(stable_cnt)); (* SOFT_HLUTNM = "soft_lutpair320" *) LUT4 #( .INIT(16'h6AAA)) \stable_cnt[3]_i_3 (.I0(\stable_cnt_reg_n_0_[3] ), .I1(\stable_cnt_reg[3]_0 ), .I2(\stable_cnt_reg_n_0_[1] ), .I3(\stable_cnt_reg_n_0_[2] ), .O(p_0_in__0[3])); LUT2 #( .INIT(4'h6)) \stable_cnt[3]_i_4 (.I0(stable_cnt227_in), .I1(\stable_cnt[3]_i_7_n_0 ), .O(\stable_cnt[3]_i_4_n_0 )); LUT5 #( .INIT(32'h00000020)) \stable_cnt[3]_i_5 (.I0(out[1]), .I1(out[4]), .I2(out[0]), .I3(out[3]), .I4(out[2]), .O(p_1_in1_in)); LUT5 #( .INIT(32'h00000020)) \stable_cnt[3]_i_6 (.I0(\wl_state_r1_reg_n_0_[0] ), .I1(\wl_state_r1_reg_n_0_[4] ), .I2(\wl_state_r1_reg_n_0_[2] ), .I3(\wl_state_r1_reg_n_0_[3] ), .I4(\wl_state_r1_reg_n_0_[1] ), .O(\stable_cnt[3]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \stable_cnt[3]_i_7 (.I0(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ), .I1(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ), .I2(\dqs_count_r_reg[1]_rep_n_0 ), .I3(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ), .I4(\dqs_count_r_reg[0]_rep_n_0 ), .I5(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ), .O(\stable_cnt[3]_i_7_n_0 )); FDRE \stable_cnt_reg[0] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[0]), .Q(\stable_cnt_reg[3]_0 ), .R(stable_cnt0)); FDRE \stable_cnt_reg[1] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[1]), .Q(\stable_cnt_reg_n_0_[1] ), .R(stable_cnt0)); FDRE \stable_cnt_reg[2] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[2]), .Q(\stable_cnt_reg_n_0_[2] ), .R(stable_cnt0)); FDRE \stable_cnt_reg[3] (.C(CLK), .CE(stable_cnt), .D(p_0_in__0[3]), .Q(\stable_cnt_reg_n_0_[3] ), .R(stable_cnt0)); LUT6 #( .INIT(64'h55330F0055330FFF)) \stg2_tap_cnt[0]_i_2 (.I0(wl_po_fine_cnt[18]), .I1(wl_po_fine_cnt[12]), .I2(wl_po_fine_cnt[6]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[0]), .O(\stg2_r_reg[0] )); LUT6 #( .INIT(64'h55FFDDF05500DDF0)) \stg2_tap_cnt[1]_i_2 (.I0(\stg2_tap_cnt[3]_i_4_n_0 ), .I1(wl_po_fine_cnt[7]), .I2(wl_po_fine_cnt[1]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[13]), .O(\stg2_target_r_reg[4] [0])); LUT6 #( .INIT(64'hFFAAF0CC00AAF0CC)) \stg2_tap_cnt[2]_i_2 (.I0(wl_po_fine_cnt[14]), .I1(wl_po_fine_cnt[2]), .I2(wl_po_fine_cnt[8]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[20]), .O(\stg2_target_r_reg[4] [1])); LUT6 #( .INIT(64'h00AA0F22FFAA0F22)) \stg2_tap_cnt[3]_i_2 (.I0(\stg2_tap_cnt[3]_i_4_n_0 ), .I1(wl_po_fine_cnt[3]), .I2(wl_po_fine_cnt[9]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[21]), .O(\stg3_dec_val_reg[2] )); LUT4 #( .INIT(16'h4F7F)) \stg2_tap_cnt[3]_i_4 (.I0(wl_po_fine_cnt[19]), .I1(\byte_r_reg[0] ), .I2(\byte_r_reg[1] ), .I3(wl_po_fine_cnt[15]), .O(\stg2_tap_cnt[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0511AF1105BBAFBB)) \stg2_tap_cnt[4]_i_2 (.I0(\byte_r_reg[0] ), .I1(wl_po_fine_cnt[4]), .I2(wl_po_fine_cnt[16]), .I3(\byte_r_reg[1] ), .I4(wl_po_fine_cnt[22]), .I5(wl_po_fine_cnt[10]), .O(\stg2_r_reg[4] )); LUT6 #( .INIT(64'h00550F33FF550F33)) \stg2_tap_cnt[5]_i_5 (.I0(wl_po_fine_cnt[17]), .I1(wl_po_fine_cnt[5]), .I2(wl_po_fine_cnt[11]), .I3(\byte_r_reg[0] ), .I4(\byte_r_reg[1] ), .I5(wl_po_fine_cnt[23]), .O(\stg2_r_reg[5] )); LUT6 #( .INIT(64'hFECEF2C23E0E3202)) \stg2_target_r[0]_i_1 (.I0(wl_po_fine_cnt[0]), .I1(\byte_r_reg[1] ), .I2(\byte_r_reg[0] ), .I3(wl_po_fine_cnt[6]), .I4(wl_po_fine_cnt[12]), .I5(wl_po_fine_cnt[18]), .O(D[0])); LUT1 #( .INIT(2'h1)) \stg2_target_r[4]_i_2 (.I0(\stg2_r_reg[4] ), .O(\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4])); LUT1 #( .INIT(2'h1)) \stg2_target_r[4]_i_3 (.I0(\stg3_dec_val_reg[2] ), .O(\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [3])); LUT2 #( .INIT(4'h9)) \stg2_target_r[4]_i_4 (.I0(\stg2_r_reg[4] ), .I1(O[2]), .O(\stg2_target_r[4]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \stg2_target_r[4]_i_5 (.I0(\stg3_dec_val_reg[2] ), .I1(O[1]), .O(\stg2_target_r[4]_i_5_n_0 )); LUT6 #( .INIT(64'hBF8FBC8CB383B080)) \stg2_target_r[8]_i_2 (.I0(wl_po_fine_cnt[23]), .I1(\byte_r_reg[1] ), .I2(\byte_r_reg[0] ), .I3(wl_po_fine_cnt[11]), .I4(wl_po_fine_cnt[5]), .I5(wl_po_fine_cnt[17]), .O(\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5])); LUT2 #( .INIT(4'h9)) \stg2_target_r[8]_i_6 (.I0(\stg2_r_reg[5] ), .I1(O[3]), .O(\stg2_target_r[8]_i_6_n_0 )); CARRY4 \stg2_target_r_reg[4]_i_1 (.CI(1'b0), .CO({\stg2_target_r_reg[4]_i_1_n_0 ,\stg2_target_r_reg[4]_i_1_n_1 ,\stg2_target_r_reg[4]_i_1_n_2 ,\stg2_target_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4:3],\stg2_target_r_reg[4] }), .O({D[3:1],\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED [0]}), .S({\stg2_target_r[4]_i_4_n_0 ,\stg2_target_r[4]_i_5_n_0 ,\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ,S})); CARRY4 \stg2_target_r_reg[8]_i_1 (.CI(\stg2_target_r_reg[4]_i_1_n_0 ), .CO({\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED [3],\stg2_target_r_reg[8]_i_1_n_1 ,\stg2_target_r_reg[8]_i_1_n_2 ,\stg2_target_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5]}), .O(D[7:4]), .S({\stg3_r_reg[5] ,\stg2_target_r[8]_i_6_n_0 })); (* SOFT_HLUTNM = "soft_lutpair319" *) LUT2 #( .INIT(4'h9)) \stg3_dec_val[0]_i_1 (.I0(\stg2_target_r_reg[4] [0]), .I1(Q[0]), .O(\stg3_dec_val_reg[2]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair319" *) LUT4 #( .INIT(16'hE11E)) \stg3_dec_val[1]_i_1 (.I0(\stg2_target_r_reg[4] [0]), .I1(Q[0]), .I2(\stg2_target_r_reg[4] [1]), .I3(Q[1]), .O(\stg3_dec_val_reg[2]_0 [1])); LUT6 #( .INIT(64'h1117EEE8EEE81117)) \stg3_dec_val[2]_i_1 (.I0(\stg2_target_r_reg[4] [1]), .I1(Q[1]), .I2(\stg2_target_r_reg[4] [0]), .I3(Q[0]), .I4(\stg3_dec_val_reg[2] ), .I5(Q[2]), .O(\stg3_dec_val_reg[2]_0 [2])); LUT2 #( .INIT(4'h6)) \u_ocd_po_cntlr/stg2_target_r[4]_i_6 (.I0(\stg2_target_r_reg[4] [1]), .I1(O[0]), .O(\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \wait_cnt[0]_i_1 (.I0(wait_cnt_reg__0[0]), .O(wait_cnt0__0[0])); (* SOFT_HLUTNM = "soft_lutpair351" *) LUT2 #( .INIT(4'h9)) \wait_cnt[1]_i_1 (.I0(wait_cnt_reg__0[0]), .I1(wait_cnt_reg__0[1]), .O(\wait_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair351" *) LUT3 #( .INIT(8'hA9)) \wait_cnt[2]_i_1 (.I0(wait_cnt_reg__0[2]), .I1(wait_cnt_reg__0[1]), .I2(wait_cnt_reg__0[0]), .O(wait_cnt0__0[2])); LUT5 #( .INIT(32'hAAAAAAA8)) \wait_cnt[3]_i_2 (.I0(phy_ctl_ready_r6_reg_n_0), .I1(wait_cnt_reg__0[3]), .I2(wait_cnt_reg__0[1]), .I3(wait_cnt_reg__0[0]), .I4(wait_cnt_reg__0[2]), .O(wait_cnt0)); (* SOFT_HLUTNM = "soft_lutpair316" *) LUT4 #( .INIT(16'hAAA9)) \wait_cnt[3]_i_3 (.I0(wait_cnt_reg__0[3]), .I1(wait_cnt_reg__0[2]), .I2(wait_cnt_reg__0[0]), .I3(wait_cnt_reg__0[1]), .O(wait_cnt0__0[3])); FDRE \wait_cnt_reg[0] (.C(CLK), .CE(wait_cnt0), .D(wait_cnt0__0[0]), .Q(wait_cnt_reg__0[0]), .R(po_cnt_dec_reg_1)); FDRE \wait_cnt_reg[1] (.C(CLK), .CE(wait_cnt0), .D(\wait_cnt[1]_i_1_n_0 ), .Q(wait_cnt_reg__0[1]), .R(po_cnt_dec_reg_1)); FDRE \wait_cnt_reg[2] (.C(CLK), .CE(wait_cnt0), .D(wait_cnt0__0[2]), .Q(wait_cnt_reg__0[2]), .R(po_cnt_dec_reg_1)); FDSE \wait_cnt_reg[3] (.C(CLK), .CE(wait_cnt0), .D(wait_cnt0__0[3]), .Q(wait_cnt_reg__0[3]), .S(po_cnt_dec_reg_1)); LUT6 #( .INIT(64'hF0FFF000AACCAACC)) \wl_corse_cnt[0][0][0]_i_1 (.I0(\corse_cnt_reg_n_0_[2][0] ), .I1(\corse_cnt_reg_n_0_[0][0] ), .I2(\corse_cnt_reg_n_0_[3][0] ), .I3(\dqs_count_r_reg[1]_rep_n_0 ), .I4(\corse_cnt_reg_n_0_[1][0] ), .I5(\dqs_count_r_reg[0]_rep_n_0 ), .O(\wl_corse_cnt[0][0][0]_i_1_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_corse_cnt[0][0][1]_i_1 (.I0(\corse_cnt_reg_n_0_[3][1] ), .I1(\corse_cnt_reg_n_0_[1][1] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_cnt_reg_n_0_[2][1] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_cnt_reg_n_0_[0][1] ), .O(\wl_corse_cnt[0][0][1]_i_1_n_0 )); LUT4 #( .INIT(16'h0100)) \wl_corse_cnt[0][0][2]_i_1 (.I0(dqs_count_r[0]), .I1(dqs_count_r[1]), .I2(dqs_count_r[2]), .I3(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .O(wl_corse_cnt)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_corse_cnt[0][0][2]_i_2 (.I0(\corse_cnt_reg_n_0_[3][2] ), .I1(\corse_cnt_reg_n_0_[1][2] ), .I2(\dqs_count_r_reg[0]_rep_n_0 ), .I3(\corse_cnt_reg_n_0_[2][2] ), .I4(\dqs_count_r_reg[1]_rep_n_0 ), .I5(\corse_cnt_reg_n_0_[0][2] ), .O(\wl_corse_cnt[0][0][2]_i_2_n_0 )); LUT6 #( .INIT(64'h0200088000800000)) \wl_corse_cnt[0][0][2]_i_3 (.I0(\wl_corse_cnt[0][0][2]_i_4_n_0 ), .I1(out[1]), .I2(out[2]), .I3(out[4]), .I4(out[0]), .I5(out[3]), .O(\wl_corse_cnt[0][0][2]_i_3_n_0 )); LUT2 #( .INIT(4'h1)) \wl_corse_cnt[0][0][2]_i_4 (.I0(\rank_cnt_r_reg[0]_0 ), .I1(\rank_cnt_r_reg[0]_1 ), .O(\wl_corse_cnt[0][0][2]_i_4_n_0 )); LUT4 #( .INIT(16'h0020)) \wl_corse_cnt[0][1][2]_i_1 (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .I1(dqs_count_r[1]), .I2(dqs_count_r[0]), .I3(dqs_count_r[2]), .O(\wl_corse_cnt[0][1][2]_i_1_n_0 )); LUT4 #( .INIT(16'h0020)) \wl_corse_cnt[0][2][2]_i_1 (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .I3(dqs_count_r[2]), .O(\wl_corse_cnt[0][2][2]_i_1_n_0 )); LUT4 #( .INIT(16'h0080)) \wl_corse_cnt[0][3][2]_i_1 (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ), .I1(dqs_count_r[0]), .I2(dqs_count_r[1]), .I3(dqs_count_r[2]), .O(\wl_corse_cnt[0][3][2]_i_1_n_0 )); FDRE \wl_corse_cnt_reg[0][0][0] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][0]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_corse_cnt_reg[0][0][1] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][0]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_corse_cnt_reg[0][0][2] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][0]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_corse_cnt_reg[0][1][0] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][1]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_corse_cnt_reg[0][1][1] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][1]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_corse_cnt_reg[0][1][2] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][1]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_corse_cnt_reg[0][2][0] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][2]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_corse_cnt_reg[0][2][1] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][2]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_corse_cnt_reg[0][2][2] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][2]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_corse_cnt_reg[0][3][0] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][3]__0 [0]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_corse_cnt_reg[0][3][1] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ), .Q(\wl_corse_cnt_reg[0][3]__0 [1]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_corse_cnt_reg[0][3][2] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_corse_cnt[0][0][2]_i_2_n_0 ), .Q(\wl_corse_cnt_reg[0][3]__0 [2]), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][0][0] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][0][1] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][0][2] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][0][3] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][0][4] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][0][5] (.C(CLK), .CE(wl_corse_cnt), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][1][0] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][1][1] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][1][2] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][1][3] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][1][4] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][1][5] (.C(CLK), .CE(\wl_corse_cnt[0][1][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][2][0] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][2][1] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][2][2] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][2][3] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][2][4] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][2][5] (.C(CLK), .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wl_dqs_tap_count_r_reg[0][3][0] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[0] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][3][1] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[1] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][3][2] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[2] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][3][3] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[3] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][3][4] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[4] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_dqs_tap_count_r_reg[0][3][5] (.C(CLK), .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ), .D(\wl_tap_count_r_reg_n_0_[5] ), .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE wl_edge_detect_valid_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[2]_0 ), .Q(\FSM_sequential_wl_state_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__16)); FDRE \wl_po_fine_cnt_reg[0] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [0]), .Q(wl_po_fine_cnt[0]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[10] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [4]), .Q(wl_po_fine_cnt[10]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[11] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [5]), .Q(wl_po_fine_cnt[11]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[12] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [0]), .Q(wl_po_fine_cnt[12]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[13] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [1]), .Q(wl_po_fine_cnt[13]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[14] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [2]), .Q(wl_po_fine_cnt[14]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[15] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [3]), .Q(wl_po_fine_cnt[15]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[16] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [4]), .Q(wl_po_fine_cnt[16]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[17] (.C(CLK), .CE(1'b1), .D(\smallest_reg[2]__0 [5]), .Q(wl_po_fine_cnt[17]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[18] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [0]), .Q(wl_po_fine_cnt[18]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[19] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [1]), .Q(wl_po_fine_cnt[19]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[1] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [1]), .Q(wl_po_fine_cnt[1]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[20] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [2]), .Q(wl_po_fine_cnt[20]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[21] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [3]), .Q(wl_po_fine_cnt[21]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[22] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [4]), .Q(wl_po_fine_cnt[22]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[23] (.C(CLK), .CE(1'b1), .D(\smallest_reg[3]__0 [5]), .Q(wl_po_fine_cnt[23]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[2] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [2]), .Q(wl_po_fine_cnt[2]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[3] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [3]), .Q(wl_po_fine_cnt[3]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[4] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [4]), .Q(wl_po_fine_cnt[4]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[5] (.C(CLK), .CE(1'b1), .D(\smallest_reg[0]__0 [5]), .Q(wl_po_fine_cnt[5]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[6] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [0]), .Q(wl_po_fine_cnt[6]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[7] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [1]), .Q(wl_po_fine_cnt[7]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[8] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [2]), .Q(wl_po_fine_cnt[8]), .R(1'b0)); FDRE \wl_po_fine_cnt_reg[9] (.C(CLK), .CE(1'b1), .D(\smallest_reg[1]__0 [3]), .Q(wl_po_fine_cnt[9]), .R(1'b0)); LUT5 #( .INIT(32'h1B15D560)) \wl_state_r1[0]_i_1 (.I0(out[1]), .I1(out[2]), .I2(out[4]), .I3(out[0]), .I4(out[3]), .O(\wl_state_r1[0]_i_1_n_0 )); LUT5 #( .INIT(32'h293CEA22)) \wl_state_r1[1]_i_1 (.I0(out[1]), .I1(out[4]), .I2(out[3]), .I3(out[0]), .I4(out[2]), .O(\wl_state_r1[1]_i_1_n_0 )); LUT5 #( .INIT(32'h0505C478)) \wl_state_r1[2]_i_1 (.I0(out[2]), .I1(out[1]), .I2(out[3]), .I3(out[0]), .I4(out[4]), .O(\wl_state_r1[2]_i_1_n_0 )); LUT5 #( .INIT(32'h67425208)) \wl_state_r1[3]_i_1 (.I0(out[4]), .I1(out[2]), .I2(out[1]), .I3(out[0]), .I4(out[3]), .O(\wl_state_r1[3]_i_1_n_0 )); LUT5 #( .INIT(32'h55512B08)) \wl_state_r1[4]_i_1 (.I0(out[3]), .I1(out[0]), .I2(out[1]), .I3(out[2]), .I4(out[4]), .O(\wl_state_r1[4]_i_1_n_0 )); FDRE \wl_state_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[0]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \wl_state_r1_reg[1] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[1]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \wl_state_r1_reg[2] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[2]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \wl_state_r1_reg[3] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[3]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__15)); FDRE \wl_state_r1_reg[4] (.C(CLK), .CE(1'b1), .D(\wl_state_r1[4]_i_1_n_0 ), .Q(\wl_state_r1_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__15)); LUT4 #( .INIT(16'hFF10)) \wl_tap_count_r[0]_i_1 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r[0]_i_2_n_0 ), .I3(\wl_tap_count_r[0]_i_3_n_0 ), .O(wl_tap_count_r[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[0]_i_2 (.I0(\smallest_reg[3]__0 [0]), .I1(\smallest_reg[1]__0 [0]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [0]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [0]), .O(\wl_tap_count_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'h0003000005050000)) \wl_tap_count_r[0]_i_3 (.I0(out[0]), .I1(out[4]), .I2(\wl_tap_count_r_reg_n_0_[0] ), .I3(wr_level_done_r5), .I4(out[1]), .I5(out[3]), .O(\wl_tap_count_r[0]_i_3_n_0 )); LUT6 #( .INIT(64'hCCCFCCEECCCCCCEE)) \wl_tap_count_r[1]_i_1 (.I0(\wl_tap_count_r[1]_i_2_n_0 ), .I1(\wl_tap_count_r[1]_i_3_n_0 ), .I2(out[0]), .I3(out[3]), .I4(out[1]), .I5(\wl_tap_count_r[1]_i_4_n_0 ), .O(wl_tap_count_r[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[1]_i_2 (.I0(\smallest_reg[3]__0 [1]), .I1(\smallest_reg[1]__0 [1]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [1]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [1]), .O(\wl_tap_count_r[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000880)) \wl_tap_count_r[1]_i_3 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r_reg_n_0_[0] ), .I3(\wl_tap_count_r_reg_n_0_[1] ), .I4(wr_level_done_r5), .I5(out[4]), .O(\wl_tap_count_r[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair343" *) LUT2 #( .INIT(4'h6)) \wl_tap_count_r[1]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[1] ), .I1(\wl_tap_count_r_reg_n_0_[0] ), .O(\wl_tap_count_r[1]_i_4_n_0 )); LUT6 #( .INIT(64'h02C232F202C202C2)) \wl_tap_count_r[2]_i_1 (.I0(\wl_tap_count_r[2]_i_2_n_0 ), .I1(out[3]), .I2(out[1]), .I3(\wl_tap_count_r[2]_i_3_n_0 ), .I4(out[0]), .I5(\wl_tap_count_r[2]_i_4_n_0 ), .O(wl_tap_count_r[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[2]_i_2 (.I0(\smallest_reg[3]__0 [2]), .I1(\smallest_reg[1]__0 [2]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [2]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [2]), .O(\wl_tap_count_r[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFEEFEFEF)) \wl_tap_count_r[2]_i_3 (.I0(out[4]), .I1(wr_level_done_r5), .I2(\wl_tap_count_r_reg_n_0_[2] ), .I3(\wl_tap_count_r_reg_n_0_[0] ), .I4(\wl_tap_count_r_reg_n_0_[1] ), .O(\wl_tap_count_r[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair343" *) LUT3 #( .INIT(8'h6A)) \wl_tap_count_r[2]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[2] ), .I1(\wl_tap_count_r_reg_n_0_[0] ), .I2(\wl_tap_count_r_reg_n_0_[1] ), .O(\wl_tap_count_r[2]_i_4_n_0 )); LUT6 #( .INIT(64'h02C202C202C232F2)) \wl_tap_count_r[3]_i_1 (.I0(\wl_tap_count_r[3]_i_2_n_0 ), .I1(out[3]), .I2(out[1]), .I3(\wl_tap_count_r[3]_i_3_n_0 ), .I4(out[0]), .I5(\wl_tap_count_r[3]_i_4_n_0 ), .O(wl_tap_count_r[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[3]_i_2 (.I0(\smallest_reg[3]__0 [3]), .I1(\smallest_reg[1]__0 [3]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [3]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [3]), .O(\wl_tap_count_r[3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEBBBBBBB)) \wl_tap_count_r[3]_i_3 (.I0(out[4]), .I1(\wl_tap_count_r_reg_n_0_[3] ), .I2(\wl_tap_count_r_reg_n_0_[2] ), .I3(\wl_tap_count_r_reg_n_0_[1] ), .I4(\wl_tap_count_r_reg_n_0_[0] ), .I5(wr_level_done_r5), .O(\wl_tap_count_r[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair317" *) LUT4 #( .INIT(16'h9555)) \wl_tap_count_r[3]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[3] ), .I1(\wl_tap_count_r_reg_n_0_[2] ), .I2(\wl_tap_count_r_reg_n_0_[1] ), .I3(\wl_tap_count_r_reg_n_0_[0] ), .O(\wl_tap_count_r[3]_i_4_n_0 )); LUT4 #( .INIT(16'hFF10)) \wl_tap_count_r[4]_i_1 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r[4]_i_2_n_0 ), .I3(\wl_tap_count_r[4]_i_3_n_0 ), .O(wl_tap_count_r[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[4]_i_2 (.I0(\smallest_reg[3]__0 [4]), .I1(\smallest_reg[1]__0 [4]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [4]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [4]), .O(\wl_tap_count_r[4]_i_2_n_0 )); LUT6 #( .INIT(64'h0003000005050000)) \wl_tap_count_r[4]_i_3 (.I0(out[0]), .I1(out[4]), .I2(\wl_tap_count_r[4]_i_4_n_0 ), .I3(wr_level_done_r5), .I4(out[1]), .I5(out[3]), .O(\wl_tap_count_r[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair317" *) LUT5 #( .INIT(32'h95555555)) \wl_tap_count_r[4]_i_4 (.I0(\wl_tap_count_r_reg_n_0_[4] ), .I1(\wl_tap_count_r_reg_n_0_[0] ), .I2(\wl_tap_count_r_reg_n_0_[1] ), .I3(\wl_tap_count_r_reg_n_0_[2] ), .I4(\wl_tap_count_r_reg_n_0_[3] ), .O(\wl_tap_count_r[4]_i_4_n_0 )); LUT6 #( .INIT(64'h4400000044551110)) \wl_tap_count_r[5]_i_1 (.I0(out[2]), .I1(out[0]), .I2(done_dqs_dec239_out), .I3(out[3]), .I4(out[1]), .I5(out[4]), .O(\wl_tap_count_r[5]_i_1_n_0 )); LUT4 #( .INIT(16'hFF10)) \wl_tap_count_r[5]_i_2 (.I0(out[3]), .I1(out[1]), .I2(\wl_tap_count_r[5]_i_4_n_0 ), .I3(\wl_tap_count_r[5]_i_5_n_0 ), .O(wl_tap_count_r[5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wl_tap_count_r[5]_i_4 (.I0(\smallest_reg[3]__0 [5]), .I1(\smallest_reg[1]__0 [5]), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\smallest_reg[2]__0 [5]), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\smallest_reg[0]__0 [5]), .O(\wl_tap_count_r[5]_i_4_n_0 )); LUT6 #( .INIT(64'h0300000055000000)) \wl_tap_count_r[5]_i_5 (.I0(out[0]), .I1(out[4]), .I2(wr_level_done_r5), .I3(\wl_tap_count_r[5]_i_6_n_0 ), .I4(out[1]), .I5(out[3]), .O(\wl_tap_count_r[5]_i_5_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \wl_tap_count_r[5]_i_6 (.I0(\wl_tap_count_r_reg_n_0_[5] ), .I1(\wl_tap_count_r_reg_n_0_[4] ), .I2(\wl_tap_count_r_reg_n_0_[3] ), .I3(\wl_tap_count_r_reg_n_0_[2] ), .I4(\wl_tap_count_r_reg_n_0_[1] ), .I5(\wl_tap_count_r_reg_n_0_[0] ), .O(\wl_tap_count_r[5]_i_6_n_0 )); FDRE \wl_tap_count_r_reg[0] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[0]), .Q(\wl_tap_count_r_reg_n_0_[0] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_tap_count_r_reg[1] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[1]), .Q(\wl_tap_count_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_tap_count_r_reg[2] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[2]), .Q(\wl_tap_count_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_tap_count_r_reg[3] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[3]), .Q(\wl_tap_count_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_tap_count_r_reg[4] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[4]), .Q(\wl_tap_count_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE \wl_tap_count_r_reg[5] (.C(CLK), .CE(\wl_tap_count_r[5]_i_1_n_0 ), .D(wl_tap_count_r[5]), .Q(\wl_tap_count_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__17)); FDRE wr_level_done_r1_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r1_reg_0), .Q(wr_level_done_r1), .R(1'b0)); FDRE wr_level_done_r2_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r1), .Q(wr_level_done_r2), .R(1'b0)); FDRE wr_level_done_r3_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r2), .Q(wr_level_done_r3), .R(1'b0)); FDRE wr_level_done_r4_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r3), .Q(wr_level_done_r4), .R(1'b0)); FDRE wr_level_done_r5_reg (.C(CLK), .CE(1'b1), .D(wr_level_done_r4), .Q(wr_level_done_r5), .R(1'b0)); LUT6 #( .INIT(64'hF5FFFFFFFFFFFFBB)) wr_level_done_r_i_2 (.I0(out[4]), .I1(wr_level_done0), .I2(p_0_in), .I3(out[3]), .I4(out[1]), .I5(out[0]), .O(wr_level_done_r_reg_0)); FDRE wr_level_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[0]_1 ), .Q(wr_level_done_r1_reg_0), .R(rstdiv0_sync_r1_reg_rep__16)); (* syn_maxfan = "2" *) FDRE wr_level_done_reg (.C(CLK), .CE(1'b1), .D(\single_rank.done_dqs_dec_reg_0 ), .Q(wrlvl_done_r_reg), .R(1'b0)); FDRE wr_level_start_r_reg (.C(CLK), .CE(1'b1), .D(wr_lvl_start_reg), .Q(wr_level_start_r), .R(1'b0)); LUT6 #( .INIT(64'h00000000AEAA00AA)) wrlvl_byte_done_i_1 (.I0(wrlvl_byte_done), .I1(wr_level_done_r3), .I2(wr_level_done_r4), .I3(wrlvl_byte_redo), .I4(wrlvl_byte_redo_r), .I5(rstdiv0_sync_r1_reg_rep__23), .O(wrlvl_byte_done_i_1_n_0)); FDRE wrlvl_byte_done_reg (.C(CLK), .CE(1'b1), .D(wrlvl_byte_done_i_1_n_0), .Q(wrlvl_byte_done), .R(1'b0)); FDRE wrlvl_byte_redo_r_reg (.C(CLK), .CE(1'b1), .D(wrlvl_byte_redo), .Q(wrlvl_byte_redo_r), .R(1'b0)); FDRE wrlvl_final_r_reg (.C(CLK), .CE(1'b1), .D(wrlvl_final_mux), .Q(wrlvl_final_r), .R(1'b0)); LUT6 #( .INIT(64'h0000400000050005)) wrlvl_rank_done_r_i_2 (.I0(out[2]), .I1(out[0]), .I2(out[1]), .I3(out[3]), .I4(p_0_in), .I5(out[4]), .O(wrlvl_rank_done_r_reg_0)); FDRE wrlvl_rank_done_r_reg (.C(CLK), .CE(1'b1), .D(\FSM_sequential_wl_state_r_reg[2]_1 ), .Q(wrlvl_rank_done), .R(rstdiv0_sync_r1_reg_rep__15)); LUT4 #( .INIT(16'h0F40)) \wrlvl_redo_corse_inc[0]_i_1 (.I0(out[4]), .I1(out[2]), .I2(\wrlvl_redo_corse_inc[2]_i_4_n_0 ), .I3(wrlvl_redo_corse_inc__0[0]), .O(\wrlvl_redo_corse_inc[0]_i_1_n_0 )); LUT5 #( .INIT(32'h45FF1500)) \wrlvl_redo_corse_inc[1]_i_1 (.I0(out[4]), .I1(wrlvl_redo_corse_inc__0[0]), .I2(out[2]), .I3(\wrlvl_redo_corse_inc[2]_i_4_n_0 ), .I4(wrlvl_redo_corse_inc__0[1]), .O(\wrlvl_redo_corse_inc[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0074FFFF00B80000)) \wrlvl_redo_corse_inc[2]_i_1 (.I0(\wrlvl_redo_corse_inc[2]_i_2_n_0 ), .I1(out[2]), .I2(\wrlvl_redo_corse_inc[2]_i_3_n_0 ), .I3(out[4]), .I4(\wrlvl_redo_corse_inc[2]_i_4_n_0 ), .I5(wrlvl_redo_corse_inc__0[2]), .O(\wrlvl_redo_corse_inc[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair336" *) LUT2 #( .INIT(4'h1)) \wrlvl_redo_corse_inc[2]_i_2 (.I0(wrlvl_redo_corse_inc__0[0]), .I1(wrlvl_redo_corse_inc__0[1]), .O(\wrlvl_redo_corse_inc[2]_i_2_n_0 )); LUT3 #( .INIT(8'hD5)) \wrlvl_redo_corse_inc[2]_i_3 (.I0(early1_data_reg_0), .I1(\wrlvl_redo_corse_inc_reg[2]_0 [0]), .I2(\wrlvl_redo_corse_inc_reg[2]_0 [1]), .O(\wrlvl_redo_corse_inc[2]_i_3_n_0 )); LUT6 #( .INIT(64'h00000020A0A00020)) \wrlvl_redo_corse_inc[2]_i_4 (.I0(\wrlvl_redo_corse_inc[2]_i_7_n_0 ), .I1(early1_data_reg), .I2(wrlvl_byte_redo), .I3(wrlvl_byte_redo_r), .I4(out[2]), .I5(\FSM_sequential_wl_state_r[2]_i_6_n_0 ), .O(\wrlvl_redo_corse_inc[2]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wrlvl_redo_corse_inc[2]_i_5 (.I0(\final_coarse_tap_reg_n_0_[3][1] ), .I1(\final_coarse_tap_reg_n_0_[1][1] ), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\final_coarse_tap_reg_n_0_[2][1] ), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\final_coarse_tap_reg_n_0_[0][1] ), .O(\wrlvl_redo_corse_inc_reg[2]_0 [0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wrlvl_redo_corse_inc[2]_i_6 (.I0(\final_coarse_tap_reg_n_0_[3][2] ), .I1(\final_coarse_tap_reg_n_0_[1][2] ), .I2(\po_stg2_wrcal_cnt_reg[2] [0]), .I3(\final_coarse_tap_reg_n_0_[2][2] ), .I4(\po_stg2_wrcal_cnt_reg[2] [1]), .I5(\final_coarse_tap_reg_n_0_[0][2] ), .O(\wrlvl_redo_corse_inc_reg[2]_0 [1])); LUT4 #( .INIT(16'h0001)) \wrlvl_redo_corse_inc[2]_i_7 (.I0(out[4]), .I1(out[3]), .I2(out[0]), .I3(out[1]), .O(\wrlvl_redo_corse_inc[2]_i_7_n_0 )); FDRE \wrlvl_redo_corse_inc_reg[0] (.C(CLK), .CE(1'b1), .D(\wrlvl_redo_corse_inc[0]_i_1_n_0 ), .Q(wrlvl_redo_corse_inc__0[0]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wrlvl_redo_corse_inc_reg[1] (.C(CLK), .CE(1'b1), .D(\wrlvl_redo_corse_inc[1]_i_1_n_0 ), .Q(wrlvl_redo_corse_inc__0[1]), .R(rstdiv0_sync_r1_reg_rep__18)); FDRE \wrlvl_redo_corse_inc_reg[2] (.C(CLK), .CE(1'b1), .D(\wrlvl_redo_corse_inc[2]_i_1_n_0 ), .Q(wrlvl_redo_corse_inc__0[2]), .R(rstdiv0_sync_r1_reg_rep__18)); endmodule module ddr3_if_mig_7series_v4_0_ddr_prbs_gen (\rd_addr_reg[0]_0 , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] , Q, \gen_mux_rd[0].compare_data_rise0_r1_reg[0] , \gen_mux_rd[1].compare_data_rise0_r1_reg[1] , \gen_mux_rd[2].compare_data_rise0_r1_reg[2] , \gen_mux_rd[3].compare_data_rise0_r1_reg[3] , \gen_mux_rd[4].compare_data_rise0_r1_reg[4] , \gen_mux_rd[5].compare_data_rise0_r1_reg[5] , \gen_mux_rd[6].compare_data_rise0_r1_reg[6] , \gen_mux_rd[7].compare_data_rise0_r1_reg[7] , \gen_mux_rd[0].compare_data_fall0_r1_reg[0] , \gen_mux_rd[1].compare_data_fall0_r1_reg[1] , \gen_mux_rd[2].compare_data_fall0_r1_reg[2] , \gen_mux_rd[3].compare_data_fall0_r1_reg[3] , \gen_mux_rd[4].compare_data_fall0_r1_reg[4] , \gen_mux_rd[5].compare_data_fall0_r1_reg[5] , \gen_mux_rd[6].compare_data_fall0_r1_reg[6] , \gen_mux_rd[7].compare_data_fall0_r1_reg[7] , \gen_mux_rd[0].compare_data_rise1_r1_reg[0] , \gen_mux_rd[1].compare_data_rise1_r1_reg[1] , \gen_mux_rd[2].compare_data_rise1_r1_reg[2] , \gen_mux_rd[3].compare_data_rise1_r1_reg[3] , \gen_mux_rd[4].compare_data_rise1_r1_reg[4] , \gen_mux_rd[5].compare_data_rise1_r1_reg[5] , \gen_mux_rd[6].compare_data_rise1_r1_reg[6] , \gen_mux_rd[7].compare_data_rise1_r1_reg[7] , \gen_mux_rd[0].compare_data_fall1_r1_reg[0] , \gen_mux_rd[1].compare_data_fall1_r1_reg[1] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] , \gen_mux_rd[3].compare_data_fall1_r1_reg[3] , \gen_mux_rd[4].compare_data_fall1_r1_reg[4] , \gen_mux_rd[5].compare_data_fall1_r1_reg[5] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] , \gen_mux_rd[7].compare_data_fall1_r1_reg[7] , \gen_mux_rd[0].compare_data_rise2_r1_reg[0] , \gen_mux_rd[1].compare_data_rise2_r1_reg[1] , \gen_mux_rd[2].compare_data_rise2_r1_reg[2] , \gen_mux_rd[3].compare_data_rise2_r1_reg[3] , \gen_mux_rd[4].compare_data_rise2_r1_reg[4] , \gen_mux_rd[5].compare_data_rise2_r1_reg[5] , \gen_mux_rd[6].compare_data_rise2_r1_reg[6] , \gen_mux_rd[7].compare_data_rise2_r1_reg[7] , \gen_mux_rd[0].compare_data_fall2_r1_reg[0] , \gen_mux_rd[1].compare_data_fall2_r1_reg[1] , \gen_mux_rd[2].compare_data_fall2_r1_reg[2] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] , \gen_mux_rd[4].compare_data_fall2_r1_reg[4] , \gen_mux_rd[5].compare_data_fall2_r1_reg[5] , \gen_mux_rd[6].compare_data_fall2_r1_reg[6] , \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] , \gen_mux_rd[0].compare_data_rise3_r1_reg[0] , \gen_mux_rd[1].compare_data_rise3_r1_reg[1] , \gen_mux_rd[2].compare_data_rise3_r1_reg[2] , \gen_mux_rd[3].compare_data_rise3_r1_reg[3] , \gen_mux_rd[4].compare_data_rise3_r1_reg[4] , \gen_mux_rd[5].compare_data_rise3_r1_reg[5] , \gen_mux_rd[6].compare_data_rise3_r1_reg[6] , \gen_mux_rd[7].compare_data_rise3_r1_reg[7] , \gen_mux_rd[0].compare_data_fall3_r1_reg[0] , \gen_mux_rd[1].compare_data_fall3_r1_reg[1] , \gen_mux_rd[2].compare_data_fall3_r1_reg[2] , \gen_mux_rd[3].compare_data_fall3_r1_reg[3] , \gen_mux_rd[4].compare_data_fall3_r1_reg[4] , \gen_mux_rd[5].compare_data_fall3_r1_reg[5] , \gen_mux_rd[6].compare_data_fall3_r1_reg[6] , \gen_mux_rd[7].compare_data_fall3_r1_reg[7] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , CLK, rdlvl_stg1_done_int_reg, wrcal_done_reg, first_rdlvl_pat_r, oclkdelay_calib_done_r_reg, \rd_addr_reg[3]_0 , rstdiv0_sync_r1_reg_rep__19, D, SR, E); output \rd_addr_reg[0]_0 ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ; output [0:0]Q; output \gen_mux_rd[0].compare_data_rise0_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise0_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise0_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise0_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise0_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise0_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise0_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise0_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall0_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall0_r1_reg[1] ; output \gen_mux_rd[2].compare_data_fall0_r1_reg[2] ; output \gen_mux_rd[3].compare_data_fall0_r1_reg[3] ; output \gen_mux_rd[4].compare_data_fall0_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall0_r1_reg[5] ; output \gen_mux_rd[6].compare_data_fall0_r1_reg[6] ; output \gen_mux_rd[7].compare_data_fall0_r1_reg[7] ; output \gen_mux_rd[0].compare_data_rise1_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise1_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise1_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise1_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise1_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise1_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise1_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise1_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall1_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall1_r1_reg[1] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ; output \gen_mux_rd[3].compare_data_fall1_r1_reg[3] ; output \gen_mux_rd[4].compare_data_fall1_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall1_r1_reg[5] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ; output \gen_mux_rd[7].compare_data_fall1_r1_reg[7] ; output \gen_mux_rd[0].compare_data_rise2_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise2_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise2_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise2_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise2_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise2_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise2_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise2_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall2_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall2_r1_reg[1] ; output \gen_mux_rd[2].compare_data_fall2_r1_reg[2] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ; output \gen_mux_rd[4].compare_data_fall2_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall2_r1_reg[5] ; output \gen_mux_rd[6].compare_data_fall2_r1_reg[6] ; output \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; output \gen_mux_rd[0].compare_data_rise3_r1_reg[0] ; output \gen_mux_rd[1].compare_data_rise3_r1_reg[1] ; output \gen_mux_rd[2].compare_data_rise3_r1_reg[2] ; output \gen_mux_rd[3].compare_data_rise3_r1_reg[3] ; output \gen_mux_rd[4].compare_data_rise3_r1_reg[4] ; output \gen_mux_rd[5].compare_data_rise3_r1_reg[5] ; output \gen_mux_rd[6].compare_data_rise3_r1_reg[6] ; output \gen_mux_rd[7].compare_data_rise3_r1_reg[7] ; output \gen_mux_rd[0].compare_data_fall3_r1_reg[0] ; output \gen_mux_rd[1].compare_data_fall3_r1_reg[1] ; output \gen_mux_rd[2].compare_data_fall3_r1_reg[2] ; output \gen_mux_rd[3].compare_data_fall3_r1_reg[3] ; output \gen_mux_rd[4].compare_data_fall3_r1_reg[4] ; output \gen_mux_rd[5].compare_data_fall3_r1_reg[5] ; output \gen_mux_rd[6].compare_data_fall3_r1_reg[6] ; output \gen_mux_rd[7].compare_data_fall3_r1_reg[7] ; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input CLK; input rdlvl_stg1_done_int_reg; input wrcal_done_reg; input first_rdlvl_pat_r; input oclkdelay_calib_done_r_reg; input \rd_addr_reg[3]_0 ; input [0:0]rstdiv0_sync_r1_reg_rep__19; input [7:0]D; input [0:0]SR; input [0:0]E; wire CLK; wire [7:0]D; wire [0:0]E; wire [0:0]Q; wire [0:0]SR; wire \dout_o[0]_i_1_n_0 ; wire \dout_o[0]_i_2_n_0 ; wire \dout_o[0]_i_3_n_0 ; wire \dout_o[0]_i_4_n_0 ; wire \dout_o[10]_i_1_n_0 ; wire \dout_o[10]_i_2_n_0 ; wire \dout_o[10]_i_3_n_0 ; wire \dout_o[11]_i_1_n_0 ; wire \dout_o[11]_i_2_n_0 ; wire \dout_o[11]_i_3_n_0 ; wire \dout_o[11]_i_4_n_0 ; wire \dout_o[12]_i_1_n_0 ; wire \dout_o[12]_i_2_n_0 ; wire \dout_o[12]_i_3_n_0 ; wire \dout_o[12]_i_4_n_0 ; wire \dout_o[13]_i_1_n_0 ; wire \dout_o[13]_i_2_n_0 ; wire \dout_o[13]_i_3_n_0 ; wire \dout_o[13]_i_4_n_0 ; wire \dout_o[14]_i_1_n_0 ; wire \dout_o[14]_i_2_n_0 ; wire \dout_o[14]_i_3_n_0 ; wire \dout_o[14]_i_4_n_0 ; wire \dout_o[15]_i_1_n_0 ; wire \dout_o[15]_i_2_n_0 ; wire \dout_o[15]_i_3_n_0 ; wire \dout_o[15]_i_4_n_0 ; wire \dout_o[1]_i_1_n_0 ; wire \dout_o[1]_i_2_n_0 ; wire \dout_o[1]_i_3_n_0 ; wire \dout_o[1]_i_4_n_0 ; wire \dout_o[2]_i_1_n_0 ; wire \dout_o[2]_i_2_n_0 ; wire \dout_o[2]_i_3_n_0 ; wire \dout_o[2]_i_4_n_0 ; wire \dout_o[3]_i_1_n_0 ; wire \dout_o[3]_i_2_n_0 ; wire \dout_o[3]_i_3_n_0 ; wire \dout_o[3]_i_4_n_0 ; wire \dout_o[4]_i_1_n_0 ; wire \dout_o[4]_i_2_n_0 ; wire \dout_o[4]_i_3_n_0 ; wire \dout_o[4]_i_4_n_0 ; wire \dout_o[5]_i_1_n_0 ; wire \dout_o[5]_i_2_n_0 ; wire \dout_o[5]_i_3_n_0 ; wire \dout_o[5]_i_4_n_0 ; wire \dout_o[6]_i_1_n_0 ; wire \dout_o[6]_i_2_n_0 ; wire \dout_o[6]_i_3_n_0 ; wire \dout_o[6]_i_4_n_0 ; wire \dout_o[7]_i_1_n_0 ; wire \dout_o[7]_i_2_n_0 ; wire \dout_o[7]_i_3_n_0 ; wire \dout_o[7]_i_4_n_0 ; wire \dout_o[8]_i_1_n_0 ; wire \dout_o[8]_i_2_n_0 ; wire \dout_o[8]_i_3_n_0 ; wire \dout_o[8]_i_4_n_0 ; wire \dout_o[9]_i_1_n_0 ; wire \dout_o[9]_i_2_n_0 ; wire \dout_o[9]_i_3_n_0 ; wire \dout_o[9]_i_4_n_0 ; wire \dout_o_reg_n_0_[0] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire first_rdlvl_pat_r; wire \gen_mux_rd[0].compare_data_fall0_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_fall1_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_fall2_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_fall3_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise0_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise1_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise2_r1_reg[0] ; wire \gen_mux_rd[0].compare_data_rise3_r1_reg[0] ; wire \gen_mux_rd[1].compare_data_fall0_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_fall1_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_fall2_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_fall3_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise0_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise1_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise2_r1_reg[1] ; wire \gen_mux_rd[1].compare_data_rise3_r1_reg[1] ; wire \gen_mux_rd[2].compare_data_fall0_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_fall2_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_fall3_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise0_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise1_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise2_r1_reg[2] ; wire \gen_mux_rd[2].compare_data_rise3_r1_reg[2] ; wire \gen_mux_rd[3].compare_data_fall0_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_fall1_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_fall3_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise0_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise1_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise2_r1_reg[3] ; wire \gen_mux_rd[3].compare_data_rise3_r1_reg[3] ; wire \gen_mux_rd[4].compare_data_fall0_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_fall1_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_fall2_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_fall3_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise0_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise1_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise2_r1_reg[4] ; wire \gen_mux_rd[4].compare_data_rise3_r1_reg[4] ; wire \gen_mux_rd[5].compare_data_fall0_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_fall1_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_fall2_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_fall3_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise0_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise1_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise2_r1_reg[5] ; wire \gen_mux_rd[5].compare_data_rise3_r1_reg[5] ; wire \gen_mux_rd[6].compare_data_fall0_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_fall2_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_fall3_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise0_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise1_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise2_r1_reg[6] ; wire \gen_mux_rd[6].compare_data_rise3_r1_reg[6] ; wire \gen_mux_rd[7].compare_data_fall0_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_fall1_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_fall3_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise0_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise1_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise2_r1_reg[7] ; wire \gen_mux_rd[7].compare_data_rise3_r1_reg[7] ; wire oclkdelay_calib_done_r_reg; wire p_0_in102_in; wire p_0_in106_in; wire p_0_in110_in; wire p_0_in114_in; wire p_0_in118_in; wire p_0_in122_in; wire p_0_in94_in; wire p_0_in98_in; wire p_1_in; wire p_1_in124_in; wire p_1_in190_in; wire p_1_in256_in; wire p_1_in322_in; wire p_1_in388_in; wire p_1_in454_in; wire p_1_in520_in; wire [7:0]p_1_in__0; wire p_2_in; wire p_2_in126_in; wire p_2_in192_in; wire p_2_in258_in; wire p_2_in324_in; wire p_2_in390_in; wire p_2_in456_in; wire \rd_addr[7]_i_4_n_0 ; wire \rd_addr[7]_i_5_n_0 ; wire \rd_addr[7]_i_6_n_0 ; wire \rd_addr_reg[0]_0 ; wire \rd_addr_reg[3]_0 ; wire \rd_addr_reg_n_0_[0] ; wire \rd_addr_reg_n_0_[1] ; wire \rd_addr_reg_n_0_[2] ; wire \rd_addr_reg_n_0_[4] ; wire \rd_addr_reg_n_0_[5] ; wire \rd_addr_reg_n_0_[6] ; wire \rd_addr_reg_n_0_[7] ; wire \rd_addr_reg_rep_n_0_[0] ; wire \rd_addr_reg_rep_n_0_[1] ; wire \rd_addr_reg_rep_n_0_[2] ; wire \rd_addr_reg_rep_n_0_[3] ; wire \rd_addr_reg_rep_n_0_[4] ; wire \rd_addr_reg_rep_n_0_[5] ; wire \rd_addr_reg_rep_n_0_[6] ; wire \rd_addr_reg_rep_n_0_[7] ; wire rdlvl_stg1_done_int_reg; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire wrcal_done_reg; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ; wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ; LUT5 #( .INIT(32'hFCBBFC88)) \dout_o[0]_i_1 (.I0(\dout_o[0]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[0]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[0]_i_4_n_0 ), .O(\dout_o[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFBA702DC40FD7BA7)) \dout_o[0]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF941DDE1)) \dout_o[0]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[0]_i_3_n_0 )); LUT6 #( .INIT(64'h5F74ABA8D4EB4862)) \dout_o[0]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[0]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[10]_i_1 (.I0(\dout_o[12]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[10]_i_2_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[10]_i_3_n_0 ), .O(\dout_o[10]_i_1_n_0 )); LUT6 #( .INIT(64'h000000004599CD27)) \dout_o[10]_i_2 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[10]_i_2_n_0 )); LUT6 #( .INIT(64'h139126016C0923FA)) \dout_o[10]_i_3 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[10]_i_3_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[11]_i_1 (.I0(\dout_o[11]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[11]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[11]_i_4_n_0 ), .O(\dout_o[11]_i_1_n_0 )); LUT6 #( .INIT(64'h713DD3CC4AE43A65)) \dout_o[11]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[11]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000322002AD)) \dout_o[11]_i_3 (.I0(\rd_addr_reg_rep_n_0_[1] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[11]_i_3_n_0 )); LUT6 #( .INIT(64'h7BB6E4333589857B)) \dout_o[11]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[1] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[11]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[12]_i_1 (.I0(\dout_o[12]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[12]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[12]_i_4_n_0 ), .O(\dout_o[12]_i_1_n_0 )); LUT6 #( .INIT(64'h9100E82800132190)) \dout_o[12]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[12]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000031C1E208)) \dout_o[12]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[12]_i_3_n_0 )); LUT6 #( .INIT(64'h447C4014C71C60A6)) \dout_o[12]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[12]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[13]_i_1 (.I0(\dout_o[13]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[13]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[13]_i_4_n_0 ), .O(\dout_o[13]_i_1_n_0 )); LUT6 #( .INIT(64'h5D37E7F8E29A3F4D)) \dout_o[13]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[2] ), .I2(\rd_addr_reg_rep_n_0_[3] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[13]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000040055161)) \dout_o[13]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[13]_i_3_n_0 )); LUT6 #( .INIT(64'h6EEDFF5CF2C694A7)) \dout_o[13]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[13]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[14]_i_1 (.I0(\dout_o[14]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[14]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[14]_i_4_n_0 ), .O(\dout_o[14]_i_1_n_0 )); LUT6 #( .INIT(64'h9100682100130190)) \dout_o[14]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[14]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000118A8B19)) \dout_o[14]_i_3 (.I0(\rd_addr_reg_rep_n_0_[1] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[14]_i_3_n_0 )); LUT6 #( .INIT(64'hD473D375410D7424)) \dout_o[14]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[14]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[15]_i_1 (.I0(\dout_o[15]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[15]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[15]_i_4_n_0 ), .O(\dout_o[15]_i_1_n_0 )); LUT6 #( .INIT(64'h5D27F5EADA9A3F4D)) \dout_o[15]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[2] ), .I2(\rd_addr_reg_rep_n_0_[3] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[15]_i_2_n_0 )); LUT6 #( .INIT(64'h000000004115533E)) \dout_o[15]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[15]_i_3_n_0 )); LUT6 #( .INIT(64'h5EF9FF567BFFCDB5)) \dout_o[15]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[15]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[1]_i_1 (.I0(\dout_o[1]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[1]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[1]_i_4_n_0 ), .O(\dout_o[1]_i_1_n_0 )); LUT6 #( .INIT(64'hE7E55AE75A58865A)) \dout_o[1]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000051880521)) \dout_o[1]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[1]_i_3_n_0 )); LUT6 #( .INIT(64'h7ADF52E8C4A8E711)) \dout_o[1]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[1]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[2]_i_1 (.I0(\dout_o[2]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[2]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[2]_i_4_n_0 ), .O(\dout_o[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFB02235842E57B02)) \dout_o[2]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[2]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000020DCBD5)) \dout_o[2]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[2]_i_3_n_0 )); LUT6 #( .INIT(64'hCF45D0CFCE2B8950)) \dout_o[2]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[2]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[3]_i_1 (.I0(\dout_o[3]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[3]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[3]_i_4_n_0 ), .O(\dout_o[3]_i_1_n_0 )); LUT6 #( .INIT(64'h46E55AC658188658)) \dout_o[3]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[3]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000019C0421)) \dout_o[3]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[3]_i_3_n_0 )); LUT6 #( .INIT(64'h2DCA4E194B652751)) \dout_o[3]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[1] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[3]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[4]_i_1 (.I0(\dout_o[4]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[4]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[4]_i_4_n_0 ), .O(\dout_o[4]_i_1_n_0 )); LUT6 #( .INIT(64'hD87BBD58DE86587B)) \dout_o[4]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[4]_i_2_n_0 )); LUT6 #( .INIT(64'h000000000455F0E2)) \dout_o[4]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[0] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[4]_i_3_n_0 )); LUT6 #( .INIT(64'h1A563E3E1BBEA40C)) \dout_o[4]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[4]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[5]_i_1 (.I0(\dout_o[5]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[5]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[5]_i_4_n_0 ), .O(\dout_o[5]_i_1_n_0 )); LUT6 #( .INIT(64'h42588642FDA55AFD)) \dout_o[5]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[0] ), .O(\dout_o[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000013A810A9)) \dout_o[5]_i_3 (.I0(\rd_addr_reg_rep_n_0_[1] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[5]_i_3_n_0 )); LUT6 #( .INIT(64'h183B5DF6A40A3E0D)) \dout_o[5]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[5]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[6]_i_1 (.I0(\dout_o[6]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[6]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[6]_i_4_n_0 ), .O(\dout_o[6]_i_1_n_0 )); LUT6 #( .INIT(64'hA35A585A84A7235A)) \dout_o[6]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[6]_i_2_n_0 )); LUT6 #( .INIT(64'h000000004441C9B1)) \dout_o[6]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[6]_i_3_n_0 )); LUT6 #( .INIT(64'h00D98F5FB527B08E)) \dout_o[6]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[6]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[7]_i_1 (.I0(\dout_o[7]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[7]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[7]_i_4_n_0 ), .O(\dout_o[7]_i_1_n_0 )); LUT6 #( .INIT(64'h5C00BF1AFFA5DC00)) \dout_o[7]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[7]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000016D00494)) \dout_o[7]_i_3 (.I0(\rd_addr_reg_rep_n_0_[4] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[0] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[7]_i_3_n_0 )); LUT6 #( .INIT(64'hAA852B305155E79F)) \dout_o[7]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[1] ), .I5(\rd_addr_reg_rep_n_0_[4] ), .O(\dout_o[7]_i_4_n_0 )); LUT5 #( .INIT(32'hFCBBFC88)) \dout_o[8]_i_1 (.I0(\dout_o[8]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[8]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[8]_i_4_n_0 ), .O(\dout_o[8]_i_1_n_0 )); LUT6 #( .INIT(64'h91C9002800211311)) \dout_o[8]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[8]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFD8D3F245)) \dout_o[8]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[4] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[8]_i_3_n_0 )); LUT6 #( .INIT(64'h0A06800432120528)) \dout_o[8]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[1] ), .I3(\rd_addr_reg_rep_n_0_[4] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[2] ), .O(\dout_o[8]_i_4_n_0 )); LUT5 #( .INIT(32'h30BB3088)) \dout_o[9]_i_1 (.I0(\dout_o[9]_i_2_n_0 ), .I1(\rd_addr_reg_rep_n_0_[6] ), .I2(\dout_o[9]_i_3_n_0 ), .I3(\rd_addr_reg_rep_n_0_[7] ), .I4(\dout_o[9]_i_4_n_0 ), .O(\dout_o[9]_i_1_n_0 )); LUT6 #( .INIT(64'hF3F5C3DC0AE47A65)) \dout_o[9]_i_2 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[2] ), .I3(\rd_addr_reg_rep_n_0_[0] ), .I4(\rd_addr_reg_rep_n_0_[4] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[9]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000040E06D5)) \dout_o[9]_i_3 (.I0(\rd_addr_reg_rep_n_0_[0] ), .I1(\rd_addr_reg_rep_n_0_[1] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[3] ), .I5(\rd_addr_reg_rep_n_0_[5] ), .O(\dout_o[9]_i_3_n_0 )); LUT6 #( .INIT(64'h20350802BEE285FB)) \dout_o[9]_i_4 (.I0(\rd_addr_reg_rep_n_0_[5] ), .I1(\rd_addr_reg_rep_n_0_[3] ), .I2(\rd_addr_reg_rep_n_0_[4] ), .I3(\rd_addr_reg_rep_n_0_[2] ), .I4(\rd_addr_reg_rep_n_0_[0] ), .I5(\rd_addr_reg_rep_n_0_[1] ), .O(\dout_o[9]_i_4_n_0 )); FDRE \dout_o_reg[0] (.C(CLK), .CE(1'b1), .D(\dout_o[0]_i_1_n_0 ), .Q(\dout_o_reg_n_0_[0] ), .R(1'b0)); FDRE \dout_o_reg[10] (.C(CLK), .CE(1'b1), .D(\dout_o[10]_i_1_n_0 ), .Q(p_1_in388_in), .R(1'b0)); FDRE \dout_o_reg[11] (.C(CLK), .CE(1'b1), .D(\dout_o[11]_i_1_n_0 ), .Q(p_1_in322_in), .R(1'b0)); FDRE \dout_o_reg[12] (.C(CLK), .CE(1'b1), .D(\dout_o[12]_i_1_n_0 ), .Q(p_1_in256_in), .R(1'b0)); FDRE \dout_o_reg[13] (.C(CLK), .CE(1'b1), .D(\dout_o[13]_i_1_n_0 ), .Q(p_1_in190_in), .R(1'b0)); FDRE \dout_o_reg[14] (.C(CLK), .CE(1'b1), .D(\dout_o[14]_i_1_n_0 ), .Q(p_1_in124_in), .R(1'b0)); FDRE \dout_o_reg[15] (.C(CLK), .CE(1'b1), .D(\dout_o[15]_i_1_n_0 ), .Q(p_1_in), .R(1'b0)); FDRE \dout_o_reg[1] (.C(CLK), .CE(1'b1), .D(\dout_o[1]_i_1_n_0 ), .Q(p_2_in456_in), .R(1'b0)); FDRE \dout_o_reg[2] (.C(CLK), .CE(1'b1), .D(\dout_o[2]_i_1_n_0 ), .Q(p_2_in390_in), .R(1'b0)); FDRE \dout_o_reg[3] (.C(CLK), .CE(1'b1), .D(\dout_o[3]_i_1_n_0 ), .Q(p_2_in324_in), .R(1'b0)); FDRE \dout_o_reg[4] (.C(CLK), .CE(1'b1), .D(\dout_o[4]_i_1_n_0 ), .Q(p_2_in258_in), .R(1'b0)); FDRE \dout_o_reg[5] (.C(CLK), .CE(1'b1), .D(\dout_o[5]_i_1_n_0 ), .Q(p_2_in192_in), .R(1'b0)); FDRE \dout_o_reg[6] (.C(CLK), .CE(1'b1), .D(\dout_o[6]_i_1_n_0 ), .Q(p_2_in126_in), .R(1'b0)); FDRE \dout_o_reg[7] (.C(CLK), .CE(1'b1), .D(\dout_o[7]_i_1_n_0 ), .Q(p_2_in), .R(1'b0)); FDRE \dout_o_reg[8] (.C(CLK), .CE(1'b1), .D(\dout_o[8]_i_1_n_0 ), .Q(p_1_in520_in), .R(1'b0)); FDRE \dout_o_reg[9] (.C(CLK), .CE(1'b1), .D(\dout_o[9]_i_1_n_0 ), .Q(p_1_in454_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair686" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall0_r1[0]_i_1 (.I0(p_2_in126_in), .I1(p_0_in94_in), .I2(p_1_in124_in), .O(\gen_mux_rd[0].compare_data_fall0_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair639" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall1_r1[0]_i_1 (.I0(p_2_in258_in), .I1(p_0_in94_in), .I2(p_1_in256_in), .O(\gen_mux_rd[0].compare_data_fall1_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair693" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall2_r1[0]_i_1 (.I0(p_2_in390_in), .I1(p_0_in94_in), .I2(p_1_in388_in), .O(\gen_mux_rd[0].compare_data_fall2_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair662" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_fall3_r1[0]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in94_in), .I2(p_1_in520_in), .O(\gen_mux_rd[0].compare_data_fall3_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair647" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise0_r1[0]_i_1 (.I0(p_2_in), .I1(p_0_in94_in), .I2(p_1_in), .O(\gen_mux_rd[0].compare_data_rise0_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair682" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise1_r1[0]_i_1 (.I0(p_2_in192_in), .I1(p_0_in94_in), .I2(p_1_in190_in), .O(\gen_mux_rd[0].compare_data_rise1_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair638" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise2_r1[0]_i_1 (.I0(p_2_in324_in), .I1(p_0_in94_in), .I2(p_1_in322_in), .O(\gen_mux_rd[0].compare_data_rise2_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair675" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[0].compare_data_rise3_r1[0]_i_1 (.I0(p_2_in456_in), .I1(p_0_in94_in), .I2(p_1_in454_in), .O(\gen_mux_rd[0].compare_data_rise3_r1_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair691" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall0_r1[1]_i_1 (.I0(p_2_in126_in), .I1(p_0_in98_in), .I2(p_1_in124_in), .O(\gen_mux_rd[1].compare_data_fall0_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair688" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall1_r1[1]_i_1 (.I0(p_2_in258_in), .I1(p_0_in98_in), .I2(p_1_in256_in), .O(\gen_mux_rd[1].compare_data_fall1_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair695" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall2_r1[1]_i_1 (.I0(p_2_in390_in), .I1(p_0_in98_in), .I2(p_1_in388_in), .O(\gen_mux_rd[1].compare_data_fall2_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair641" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_fall3_r1[1]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in98_in), .I2(p_1_in520_in), .O(\gen_mux_rd[1].compare_data_fall3_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair690" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise0_r1[1]_i_1 (.I0(p_2_in), .I1(p_0_in98_in), .I2(p_1_in), .O(\gen_mux_rd[1].compare_data_rise0_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair651" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise1_r1[1]_i_1 (.I0(p_2_in192_in), .I1(p_0_in98_in), .I2(p_1_in190_in), .O(\gen_mux_rd[1].compare_data_rise1_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair694" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise2_r1[1]_i_1 (.I0(p_2_in324_in), .I1(p_0_in98_in), .I2(p_1_in322_in), .O(\gen_mux_rd[1].compare_data_rise2_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair680" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[1].compare_data_rise3_r1[1]_i_1 (.I0(p_2_in456_in), .I1(p_0_in98_in), .I2(p_1_in454_in), .O(\gen_mux_rd[1].compare_data_rise3_r1_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair665" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_fall0_r1[2]_i_1 (.I0(p_2_in126_in), .I1(p_0_in102_in), .I2(p_1_in124_in), .O(\gen_mux_rd[2].compare_data_fall0_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair643" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_fall2_r1[2]_i_1 (.I0(p_2_in390_in), .I1(p_0_in102_in), .I2(p_1_in388_in), .O(\gen_mux_rd[2].compare_data_fall2_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair687" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_fall3_r1[2]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in102_in), .I2(p_1_in520_in), .O(\gen_mux_rd[2].compare_data_fall3_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair664" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise0_r1[2]_i_1 (.I0(p_2_in), .I1(p_0_in102_in), .I2(p_1_in), .O(\gen_mux_rd[2].compare_data_rise0_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair655" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise1_r1[2]_i_1 (.I0(p_2_in192_in), .I1(p_0_in102_in), .I2(p_1_in190_in), .O(\gen_mux_rd[2].compare_data_rise1_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair653" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise2_r1[2]_i_1 (.I0(p_2_in324_in), .I1(p_0_in102_in), .I2(p_1_in322_in), .O(\gen_mux_rd[2].compare_data_rise2_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair658" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[2].compare_data_rise3_r1[2]_i_1 (.I0(p_2_in456_in), .I1(p_0_in102_in), .I2(p_1_in454_in), .O(\gen_mux_rd[2].compare_data_rise3_r1_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair667" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_fall0_r1[3]_i_1 (.I0(p_2_in126_in), .I1(p_0_in106_in), .I2(p_1_in124_in), .O(\gen_mux_rd[3].compare_data_fall0_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair692" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_fall1_r1[3]_i_1 (.I0(p_2_in258_in), .I1(p_0_in106_in), .I2(p_1_in256_in), .O(\gen_mux_rd[3].compare_data_fall1_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair645" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_fall3_r1[3]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in106_in), .I2(p_1_in520_in), .O(\gen_mux_rd[3].compare_data_fall3_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair648" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise0_r1[3]_i_1 (.I0(p_2_in), .I1(p_0_in106_in), .I2(p_1_in), .O(\gen_mux_rd[3].compare_data_rise0_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair679" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise1_r1[3]_i_1 (.I0(p_2_in192_in), .I1(p_0_in106_in), .I2(p_1_in190_in), .O(\gen_mux_rd[3].compare_data_rise1_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair685" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise2_r1[3]_i_1 (.I0(p_2_in324_in), .I1(p_0_in106_in), .I2(p_1_in322_in), .O(\gen_mux_rd[3].compare_data_rise2_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair678" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[3].compare_data_rise3_r1[3]_i_1 (.I0(p_2_in456_in), .I1(p_0_in106_in), .I2(p_1_in454_in), .O(\gen_mux_rd[3].compare_data_rise3_r1_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair686" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall0_r1[4]_i_1 (.I0(p_2_in126_in), .I1(p_0_in110_in), .I2(p_1_in124_in), .O(\gen_mux_rd[4].compare_data_fall0_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair640" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall1_r1[4]_i_1 (.I0(p_2_in258_in), .I1(p_0_in110_in), .I2(p_1_in256_in), .O(\gen_mux_rd[4].compare_data_fall1_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair696" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall2_r1[4]_i_1 (.I0(p_2_in390_in), .I1(p_0_in110_in), .I2(p_1_in388_in), .O(\gen_mux_rd[4].compare_data_fall2_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair661" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_fall3_r1[4]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in110_in), .I2(p_1_in520_in), .O(\gen_mux_rd[4].compare_data_fall3_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair649" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise0_r1[4]_i_1 (.I0(p_2_in), .I1(p_0_in110_in), .I2(p_1_in), .O(\gen_mux_rd[4].compare_data_rise0_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair684" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise1_r1[4]_i_1 (.I0(p_2_in192_in), .I1(p_0_in110_in), .I2(p_1_in190_in), .O(\gen_mux_rd[4].compare_data_rise1_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair659" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise2_r1[4]_i_1 (.I0(p_2_in324_in), .I1(p_0_in110_in), .I2(p_1_in322_in), .O(\gen_mux_rd[4].compare_data_rise2_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair672" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[4].compare_data_rise3_r1[4]_i_1 (.I0(p_2_in456_in), .I1(p_0_in110_in), .I2(p_1_in454_in), .O(\gen_mux_rd[4].compare_data_rise3_r1_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair691" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall0_r1[5]_i_1 (.I0(p_2_in126_in), .I1(p_0_in114_in), .I2(p_1_in124_in), .O(\gen_mux_rd[5].compare_data_fall0_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair692" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall1_r1[5]_i_1 (.I0(p_2_in258_in), .I1(p_0_in114_in), .I2(p_1_in256_in), .O(\gen_mux_rd[5].compare_data_fall1_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair693" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall2_r1[5]_i_1 (.I0(p_2_in390_in), .I1(p_0_in114_in), .I2(p_1_in388_in), .O(\gen_mux_rd[5].compare_data_fall2_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair642" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_fall3_r1[5]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in114_in), .I2(p_1_in520_in), .O(\gen_mux_rd[5].compare_data_fall3_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair690" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise0_r1[5]_i_1 (.I0(p_2_in), .I1(p_0_in114_in), .I2(p_1_in), .O(\gen_mux_rd[5].compare_data_rise0_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair652" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise1_r1[5]_i_1 (.I0(p_2_in192_in), .I1(p_0_in114_in), .I2(p_1_in190_in), .O(\gen_mux_rd[5].compare_data_rise1_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair694" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise2_r1[5]_i_1 (.I0(p_2_in324_in), .I1(p_0_in114_in), .I2(p_1_in322_in), .O(\gen_mux_rd[5].compare_data_rise2_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair683" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[5].compare_data_rise3_r1[5]_i_1 (.I0(p_2_in456_in), .I1(p_0_in114_in), .I2(p_1_in454_in), .O(\gen_mux_rd[5].compare_data_rise3_r1_reg[5] )); (* SOFT_HLUTNM = "soft_lutpair668" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_fall0_r1[6]_i_1 (.I0(p_2_in126_in), .I1(p_0_in118_in), .I2(p_1_in124_in), .O(\gen_mux_rd[6].compare_data_fall0_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair644" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_fall2_r1[6]_i_1 (.I0(p_2_in390_in), .I1(p_0_in118_in), .I2(p_1_in388_in), .O(\gen_mux_rd[6].compare_data_fall2_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair687" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_fall3_r1[6]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in118_in), .I2(p_1_in520_in), .O(\gen_mux_rd[6].compare_data_fall3_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair663" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise0_r1[6]_i_1 (.I0(p_2_in), .I1(p_0_in118_in), .I2(p_1_in), .O(\gen_mux_rd[6].compare_data_rise0_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair656" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise1_r1[6]_i_1 (.I0(p_2_in192_in), .I1(p_0_in118_in), .I2(p_1_in190_in), .O(\gen_mux_rd[6].compare_data_rise1_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair654" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise2_r1[6]_i_1 (.I0(p_2_in324_in), .I1(p_0_in118_in), .I2(p_1_in322_in), .O(\gen_mux_rd[6].compare_data_rise2_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair657" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[6].compare_data_rise3_r1[6]_i_1 (.I0(p_2_in456_in), .I1(p_0_in118_in), .I2(p_1_in454_in), .O(\gen_mux_rd[6].compare_data_rise3_r1_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair666" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_fall0_r1[7]_i_1 (.I0(p_2_in126_in), .I1(p_0_in122_in), .I2(p_1_in124_in), .O(\gen_mux_rd[7].compare_data_fall0_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair688" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_fall1_r1[7]_i_1 (.I0(p_2_in258_in), .I1(p_0_in122_in), .I2(p_1_in256_in), .O(\gen_mux_rd[7].compare_data_fall1_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair646" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_fall3_r1[7]_i_1 (.I0(\dout_o_reg_n_0_[0] ), .I1(p_0_in122_in), .I2(p_1_in520_in), .O(\gen_mux_rd[7].compare_data_fall3_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair650" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise0_r1[7]_i_1 (.I0(p_2_in), .I1(p_0_in122_in), .I2(p_1_in), .O(\gen_mux_rd[7].compare_data_rise0_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair674" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise1_r1[7]_i_1 (.I0(p_2_in192_in), .I1(p_0_in122_in), .I2(p_1_in190_in), .O(\gen_mux_rd[7].compare_data_rise1_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair681" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise2_r1[7]_i_1 (.I0(p_2_in324_in), .I1(p_0_in122_in), .I2(p_1_in322_in), .O(\gen_mux_rd[7].compare_data_rise2_r1_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair673" *) LUT3 #( .INIT(8'hB8)) \gen_mux_rd[7].compare_data_rise3_r1[7]_i_1 (.I0(p_2_in456_in), .I1(p_0_in122_in), .I2(p_1_in454_in), .O(\gen_mux_rd[7].compare_data_rise3_r1_reg[7] )); FDRE phy_if_empty_r_reg (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .Q(\rd_addr_reg[0]_0 ), .R(1'b0)); LUT2 #( .INIT(4'h1)) \rd_addr[0]_i_1 (.I0(\rd_addr_reg_n_0_[0] ), .I1(\rd_addr[7]_i_5_n_0 ), .O(p_1_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair676" *) LUT2 #( .INIT(4'h6)) \rd_addr[1]_i_1 (.I0(\rd_addr_reg_n_0_[0] ), .I1(\rd_addr_reg_n_0_[1] ), .O(p_1_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair660" *) LUT4 #( .INIT(16'h1540)) \rd_addr[2]_i_1 (.I0(\rd_addr[7]_i_5_n_0 ), .I1(\rd_addr_reg_n_0_[0] ), .I2(\rd_addr_reg_n_0_[1] ), .I3(\rd_addr_reg_n_0_[2] ), .O(p_1_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair660" *) LUT5 #( .INIT(32'h15554000)) \rd_addr[3]_i_1 (.I0(\rd_addr[7]_i_5_n_0 ), .I1(\rd_addr_reg_n_0_[1] ), .I2(\rd_addr_reg_n_0_[0] ), .I3(\rd_addr_reg_n_0_[2] ), .I4(Q), .O(p_1_in__0[3])); LUT6 #( .INIT(64'h1555555540000000)) \rd_addr[4]_i_1 (.I0(\rd_addr[7]_i_5_n_0 ), .I1(\rd_addr_reg_n_0_[2] ), .I2(\rd_addr_reg_n_0_[0] ), .I3(\rd_addr_reg_n_0_[1] ), .I4(Q), .I5(\rd_addr_reg_n_0_[4] ), .O(p_1_in__0[4])); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \rd_addr[5]_i_1 (.I0(\rd_addr_reg_n_0_[5] ), .I1(Q), .I2(\rd_addr_reg_n_0_[1] ), .I3(\rd_addr_reg_n_0_[0] ), .I4(\rd_addr_reg_n_0_[2] ), .I5(\rd_addr_reg_n_0_[4] ), .O(p_1_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair677" *) LUT2 #( .INIT(4'h6)) \rd_addr[6]_i_1 (.I0(\rd_addr_reg_n_0_[6] ), .I1(\rd_addr[7]_i_4_n_0 ), .O(p_1_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair677" *) LUT4 #( .INIT(16'h006A)) \rd_addr[7]_i_3 (.I0(\rd_addr_reg_n_0_[7] ), .I1(\rd_addr[7]_i_4_n_0 ), .I2(\rd_addr_reg_n_0_[6] ), .I3(\rd_addr[7]_i_5_n_0 ), .O(p_1_in__0[7])); LUT6 #( .INIT(64'h8000000000000000)) \rd_addr[7]_i_4 (.I0(\rd_addr_reg_n_0_[5] ), .I1(\rd_addr_reg_n_0_[4] ), .I2(\rd_addr_reg_n_0_[2] ), .I3(\rd_addr_reg_n_0_[0] ), .I4(\rd_addr_reg_n_0_[1] ), .I5(Q), .O(\rd_addr[7]_i_4_n_0 )); LUT5 #( .INIT(32'h00000010)) \rd_addr[7]_i_5 (.I0(\rd_addr[7]_i_6_n_0 ), .I1(\rd_addr_reg_n_0_[5] ), .I2(\rd_addr_reg_n_0_[7] ), .I3(\rd_addr_reg_n_0_[6] ), .I4(\rd_addr_reg[3]_0 ), .O(\rd_addr[7]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair676" *) LUT4 #( .INIT(16'hEFFF)) \rd_addr[7]_i_6 (.I0(\rd_addr_reg_n_0_[1] ), .I1(\rd_addr_reg_n_0_[0] ), .I2(\rd_addr_reg_n_0_[4] ), .I3(\rd_addr_reg_n_0_[2] ), .O(\rd_addr[7]_i_6_n_0 )); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[0] (.C(CLK), .CE(E), .D(p_1_in__0[0]), .Q(\rd_addr_reg_n_0_[0] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[1] (.C(CLK), .CE(E), .D(p_1_in__0[1]), .Q(\rd_addr_reg_n_0_[1] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[2] (.C(CLK), .CE(E), .D(p_1_in__0[2]), .Q(\rd_addr_reg_n_0_[2] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[3] (.C(CLK), .CE(E), .D(p_1_in__0[3]), .Q(Q), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[4] (.C(CLK), .CE(E), .D(p_1_in__0[4]), .Q(\rd_addr_reg_n_0_[4] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[5] (.C(CLK), .CE(E), .D(p_1_in__0[5]), .Q(\rd_addr_reg_n_0_[5] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[6] (.C(CLK), .CE(E), .D(p_1_in__0[6]), .Q(\rd_addr_reg_n_0_[6] ), .R(SR)); (* RAM_STYLE = "distributed" *) FDRE \rd_addr_reg[7] (.C(CLK), .CE(E), .D(p_1_in__0[7]), .Q(\rd_addr_reg_n_0_[7] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[0] (.C(CLK), .CE(E), .D(p_1_in__0[0]), .Q(\rd_addr_reg_rep_n_0_[0] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[1] (.C(CLK), .CE(E), .D(p_1_in__0[1]), .Q(\rd_addr_reg_rep_n_0_[1] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[2] (.C(CLK), .CE(E), .D(p_1_in__0[2]), .Q(\rd_addr_reg_rep_n_0_[2] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[3] (.C(CLK), .CE(E), .D(p_1_in__0[3]), .Q(\rd_addr_reg_rep_n_0_[3] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[4] (.C(CLK), .CE(E), .D(p_1_in__0[4]), .Q(\rd_addr_reg_rep_n_0_[4] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[5] (.C(CLK), .CE(E), .D(p_1_in__0[5]), .Q(\rd_addr_reg_rep_n_0_[5] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[6] (.C(CLK), .CE(E), .D(p_1_in__0[6]), .Q(\rd_addr_reg_rep_n_0_[6] ), .R(SR)); (* equivalent_register_removal = "no" *) FDRE \rd_addr_reg_rep[7] (.C(CLK), .CE(E), .D(p_1_in__0[7]), .Q(\rd_addr_reg_rep_n_0_[7] ), .R(SR)); FDRE \victim_sel_rotate.sel_reg[24] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(p_0_in94_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[25] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(p_0_in98_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[26] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(p_0_in102_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[27] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(p_0_in106_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[28] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(p_0_in110_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[29] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(p_0_in114_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[30] (.C(CLK), .CE(1'b1), .D(D[6]), .Q(p_0_in118_in), .R(rstdiv0_sync_r1_reg_rep__19)); FDRE \victim_sel_rotate.sel_reg[31] (.C(CLK), .CE(1'b1), .D(D[7]), .Q(p_0_in122_in), .R(rstdiv0_sync_r1_reg_rep__19)); (* SOFT_HLUTNM = "soft_lutpair639" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1 (.I0(p_1_in256_in), .I1(p_0_in94_in), .I2(p_2_in258_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] )); (* SOFT_HLUTNM = "soft_lutpair669" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[121]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in98_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] )); (* SOFT_HLUTNM = "soft_lutpair689" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[122]_i_1 (.I0(p_2_in258_in), .I1(p_0_in102_in), .I2(p_1_in256_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] )); (* SOFT_HLUTNM = "soft_lutpair669" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[123]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in106_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] )); (* SOFT_HLUTNM = "soft_lutpair640" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1 (.I0(p_1_in256_in), .I1(p_0_in110_in), .I2(p_2_in258_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] )); (* SOFT_HLUTNM = "soft_lutpair670" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[125]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in114_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] )); (* SOFT_HLUTNM = "soft_lutpair689" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[126]_i_1 (.I0(p_2_in258_in), .I1(p_0_in118_in), .I2(p_1_in256_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] )); (* SOFT_HLUTNM = "soft_lutpair670" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[127]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in256_in), .I2(p_0_in122_in), .I3(p_2_in258_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] )); (* SOFT_HLUTNM = "soft_lutpair638" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[152]_i_1 (.I0(p_2_in324_in), .I1(p_0_in94_in), .I2(p_1_in322_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] )); LUT6 #( .INIT(64'hE200000000000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[153]_i_1 (.I0(p_1_in322_in), .I1(p_0_in98_in), .I2(p_2_in324_in), .I3(oclkdelay_calib_done_r_reg), .I4(wrcal_done_reg), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] )); (* SOFT_HLUTNM = "soft_lutpair653" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[154]_i_1 (.I0(p_1_in322_in), .I1(p_0_in102_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] )); (* SOFT_HLUTNM = "soft_lutpair685" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[155]_i_1 (.I0(p_1_in322_in), .I1(p_0_in106_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] )); (* SOFT_HLUTNM = "soft_lutpair659" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_2 (.I0(p_2_in324_in), .I1(p_0_in110_in), .I2(p_1_in322_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] )); LUT6 #( .INIT(64'hE200000000000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[157]_i_1 (.I0(p_1_in322_in), .I1(p_0_in114_in), .I2(p_2_in324_in), .I3(oclkdelay_calib_done_r_reg), .I4(wrcal_done_reg), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] )); (* SOFT_HLUTNM = "soft_lutpair654" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_2 (.I0(p_1_in322_in), .I1(p_0_in118_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] )); (* SOFT_HLUTNM = "soft_lutpair681" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[159]_i_1 (.I0(p_1_in322_in), .I1(p_0_in122_in), .I2(p_2_in324_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] )); (* SOFT_HLUTNM = "soft_lutpair671" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in388_in), .I2(p_0_in94_in), .I3(p_2_in390_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] )); LUT6 #( .INIT(64'hF7FFF77777777777)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[185]_i_1 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(p_2_in390_in), .I3(p_0_in98_in), .I4(p_1_in388_in), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] )); (* SOFT_HLUTNM = "soft_lutpair643" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1 (.I0(p_1_in388_in), .I1(p_0_in102_in), .I2(p_2_in390_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] )); (* SOFT_HLUTNM = "soft_lutpair695" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1 (.I0(p_2_in390_in), .I1(p_0_in106_in), .I2(p_1_in388_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] )); (* SOFT_HLUTNM = "soft_lutpair671" *) LUT4 #( .INIT(16'hA808)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1 (.I0(wrcal_done_reg), .I1(p_1_in388_in), .I2(p_0_in110_in), .I3(p_2_in390_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] )); LUT6 #( .INIT(64'hF7FFF77777777777)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[189]_i_1 (.I0(oclkdelay_calib_done_r_reg), .I1(wrcal_done_reg), .I2(p_2_in390_in), .I3(p_0_in114_in), .I4(p_1_in388_in), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] )); (* SOFT_HLUTNM = "soft_lutpair644" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1 (.I0(p_1_in388_in), .I1(p_0_in118_in), .I2(p_2_in390_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] )); (* SOFT_HLUTNM = "soft_lutpair696" *) LUT3 #( .INIT(8'hB8)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_2 (.I0(p_2_in390_in), .I1(p_0_in122_in), .I2(p_1_in388_in), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] )); (* SOFT_HLUTNM = "soft_lutpair675" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[216]_i_1 (.I0(p_1_in454_in), .I1(p_0_in94_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] )); (* SOFT_HLUTNM = "soft_lutpair680" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[217]_i_1 (.I0(p_1_in454_in), .I1(p_0_in98_in), .I2(p_2_in456_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] )); (* SOFT_HLUTNM = "soft_lutpair658" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[218]_i_1 (.I0(p_2_in456_in), .I1(p_0_in102_in), .I2(p_1_in454_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] )); (* SOFT_HLUTNM = "soft_lutpair678" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[219]_i_1 (.I0(p_1_in454_in), .I1(p_0_in106_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] )); (* SOFT_HLUTNM = "soft_lutpair672" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[220]_i_1 (.I0(p_1_in454_in), .I1(p_0_in110_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] )); (* SOFT_HLUTNM = "soft_lutpair683" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_2 (.I0(p_1_in454_in), .I1(p_0_in114_in), .I2(p_2_in456_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] )); (* SOFT_HLUTNM = "soft_lutpair657" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_2 (.I0(p_2_in456_in), .I1(p_0_in118_in), .I2(p_1_in454_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] )); (* SOFT_HLUTNM = "soft_lutpair673" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_2 (.I0(p_1_in454_in), .I1(p_0_in122_in), .I2(p_2_in456_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] )); (* SOFT_HLUTNM = "soft_lutpair662" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1 (.I0(p_1_in520_in), .I1(p_0_in94_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] )); (* SOFT_HLUTNM = "soft_lutpair641" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1 (.I0(p_1_in520_in), .I1(p_0_in98_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] )); (* SOFT_HLUTNM = "soft_lutpair647" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[24]_i_1 (.I0(p_1_in), .I1(p_0_in94_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] )); (* SOFT_HLUTNM = "soft_lutpair645" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1 (.I0(p_1_in520_in), .I1(p_0_in106_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] )); (* SOFT_HLUTNM = "soft_lutpair661" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1 (.I0(p_1_in520_in), .I1(p_0_in110_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] )); (* SOFT_HLUTNM = "soft_lutpair642" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1 (.I0(p_1_in520_in), .I1(p_0_in114_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] )); (* SOFT_HLUTNM = "soft_lutpair646" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1 (.I0(p_1_in520_in), .I1(p_0_in122_in), .I2(\dout_o_reg_n_0_[0] ), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] )); LUT6 #( .INIT(64'hB800B8FFFFFFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[25]_i_1 (.I0(p_2_in), .I1(p_0_in98_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(first_rdlvl_pat_r), .I5(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] )); (* SOFT_HLUTNM = "soft_lutpair664" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[26]_i_1 (.I0(p_2_in), .I1(p_0_in102_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] )); (* SOFT_HLUTNM = "soft_lutpair648" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[27]_i_1 (.I0(p_1_in), .I1(p_0_in106_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] )); (* SOFT_HLUTNM = "soft_lutpair649" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[28]_i_1 (.I0(p_1_in), .I1(p_0_in110_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] )); LUT6 #( .INIT(64'hB800B8FFFFFFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[29]_i_1 (.I0(p_2_in), .I1(p_0_in114_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(first_rdlvl_pat_r), .I5(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] )); (* SOFT_HLUTNM = "soft_lutpair663" *) LUT5 #( .INIT(32'hB800FFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[30]_i_1 (.I0(p_2_in), .I1(p_0_in118_in), .I2(p_1_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] )); (* SOFT_HLUTNM = "soft_lutpair650" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[31]_i_1 (.I0(p_1_in), .I1(p_0_in122_in), .I2(p_2_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] )); LUT6 #( .INIT(64'hC0CCC00088888888)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[57]_i_1 (.I0(first_rdlvl_pat_r), .I1(wrcal_done_reg), .I2(p_2_in126_in), .I3(p_0_in98_in), .I4(p_1_in124_in), .I5(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] )); (* SOFT_HLUTNM = "soft_lutpair665" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1 (.I0(p_1_in124_in), .I1(p_0_in102_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] )); (* SOFT_HLUTNM = "soft_lutpair667" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[59]_i_1 (.I0(p_1_in124_in), .I1(p_0_in106_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] )); LUT6 #( .INIT(64'hB8FFB80000000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[61]_i_1 (.I0(p_2_in126_in), .I1(p_0_in114_in), .I2(p_1_in124_in), .I3(rdlvl_stg1_done_int_reg), .I4(first_rdlvl_pat_r), .I5(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] )); (* SOFT_HLUTNM = "soft_lutpair668" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1 (.I0(p_1_in124_in), .I1(p_0_in118_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] )); (* SOFT_HLUTNM = "soft_lutpair666" *) LUT5 #( .INIT(32'hE2000000)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[63]_i_1 (.I0(p_1_in124_in), .I1(p_0_in122_in), .I2(p_2_in126_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] )); (* SOFT_HLUTNM = "soft_lutpair682" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[88]_i_1 (.I0(p_1_in190_in), .I1(p_0_in94_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] )); (* SOFT_HLUTNM = "soft_lutpair651" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[89]_i_1 (.I0(p_1_in190_in), .I1(p_0_in98_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] )); (* SOFT_HLUTNM = "soft_lutpair655" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[90]_i_1 (.I0(p_1_in190_in), .I1(p_0_in102_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] )); (* SOFT_HLUTNM = "soft_lutpair679" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[91]_i_1 (.I0(p_1_in190_in), .I1(p_0_in106_in), .I2(p_2_in192_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] )); (* SOFT_HLUTNM = "soft_lutpair684" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[92]_i_1 (.I0(p_1_in190_in), .I1(p_0_in110_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] )); (* SOFT_HLUTNM = "soft_lutpair652" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[93]_i_1 (.I0(p_1_in190_in), .I1(p_0_in114_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] )); (* SOFT_HLUTNM = "soft_lutpair656" *) LUT5 #( .INIT(32'hE2FFFFFF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[94]_i_1 (.I0(p_1_in190_in), .I1(p_0_in118_in), .I2(p_2_in192_in), .I3(rdlvl_stg1_done_int_reg), .I4(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] )); (* SOFT_HLUTNM = "soft_lutpair674" *) LUT4 #( .INIT(16'hE2FF)) \wrdq_div1_4to1_wrcal_first.phy_wrdata[95]_i_1 (.I0(p_1_in190_in), .I1(p_0_in122_in), .I2(p_2_in192_in), .I3(wrcal_done_reg), .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] )); endmodule module ddr3_if_mig_7series_v4_0_infrastructure (mmcm_locked, psdone, CLK, mmcm_ps_clk, freq_refclk, mem_refclk, sync_pulse, poc_sample_pd, rst_sync_r1, \stg3_tap_cnt_reg[0] , reset_reg, \simp_stg3_final_r_reg[17] , in0, \read_fifo.head_r_reg[0] , SR, \rd_ptr_timing_reg[2] , SS, cal2_if_reset_reg, cal2_done_r_reg, \wrcal_dqs_cnt_r_reg[2] , \two_dec_max_limit_reg[11] , \fine_pi_dec_cnt_reg[0] , rst_out_reg, \en_cnt_div4.enable_wrlvl_cnt_reg[2] , \complex_address_reg[0] , complex_sample_cnt_inc_reg, \dec_cnt_reg[0] , mpr_rank_done_r_reg, \gen_final_tap[2].final_val_reg[2][0] , \wl_tap_count_r_reg[0] , \complex_num_reads_dec_reg[0] , \victim_sel_rotate.sel_reg[31] , \rtp_timer_r_reg[0] , \last_master_r_reg[2] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , \wait_cnt_reg[3] , \wrcal_reads_reg[0] , \oneeighty_r_reg[0] , RST0, \stg3_r_reg[1] , \oneeighty_r_reg[0]_0 , pll_locked, rtp_timer_ns1, pre_wait_r_reg, rtp_timer_ns1_0, rtp_timer_ns1_1, ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, ras_timer_zero_r_reg_1, ras_timer_zero_r_reg_2, \pi_rst_stg1_cal_r_reg[1] , \samp_edge_cnt0_r_reg[11] , \wait_cnt_r_reg[3] , \en_cnt_div4.enable_wrlvl_cnt_reg[4] , p_81_in, \wr_victim_sel_ocal_reg[2] , cnt_pwron_reset_done_r0, \wait_cnt_reg[3]_0 , E, mmcm_clk, AS, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , \lim_state_reg[0] , poc_backup_r_reg, \resume_wait_r_reg[10] , sm_r, pass_open_bank_r, pass_open_bank_r_2, pass_open_bank_r_3, pass_open_bank_r_4, bm_end_r1, bm_end_r1_5, bm_end_r1_6, bm_end_r1_7, fine_adjust_reg, samp_edge_cnt0_en_r, pi_cnt_dec, \en_cnt_div4.wrlvl_odt_reg , \row_cnt_victim_rotate.complex_row_cnt_reg[7] , wr_victim_inc_reg, phy_mc_go, po_cnt_dec); output mmcm_locked; output psdone; output CLK; output mmcm_ps_clk; output freq_refclk; output mem_refclk; output sync_pulse; output poc_sample_pd; output rst_sync_r1; output \stg3_tap_cnt_reg[0] ; output reset_reg; output \simp_stg3_final_r_reg[17] ; output in0; output \read_fifo.head_r_reg[0] ; output [0:0]SR; output \rd_ptr_timing_reg[2] ; output [0:0]SS; output cal2_if_reset_reg; output [0:0]cal2_done_r_reg; output \wrcal_dqs_cnt_r_reg[2] ; output \two_dec_max_limit_reg[11] ; output \fine_pi_dec_cnt_reg[0] ; output rst_out_reg; output \en_cnt_div4.enable_wrlvl_cnt_reg[2] ; output [0:0]\complex_address_reg[0] ; output complex_sample_cnt_inc_reg; output \dec_cnt_reg[0] ; output [1:0]mpr_rank_done_r_reg; output [0:0]\gen_final_tap[2].final_val_reg[2][0] ; output [0:0]\wl_tap_count_r_reg[0] ; output [0:0]\complex_num_reads_dec_reg[0] ; output [0:0]\victim_sel_rotate.sel_reg[31] ; output \rtp_timer_r_reg[0] ; output \last_master_r_reg[2] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output \wait_cnt_reg[3] ; output \wrcal_reads_reg[0] ; output \oneeighty_r_reg[0] ; output RST0; output \stg3_r_reg[1] ; output [0:0]\oneeighty_r_reg[0]_0 ; output pll_locked; output rtp_timer_ns1; output pre_wait_r_reg; output rtp_timer_ns1_0; output rtp_timer_ns1_1; output ras_timer_zero_r_reg; output ras_timer_zero_r_reg_0; output ras_timer_zero_r_reg_1; output ras_timer_zero_r_reg_2; output \pi_rst_stg1_cal_r_reg[1] ; output \samp_edge_cnt0_r_reg[11] ; output [0:0]\wait_cnt_r_reg[3] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[4] ; output p_81_in; output \wr_victim_sel_ocal_reg[2] ; output cnt_pwron_reset_done_r0; output [0:0]\wait_cnt_reg[3]_0 ; input [0:0]E; input mmcm_clk; input [0:0]AS; input \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input \lim_state_reg[0] ; input poc_backup_r_reg; input \resume_wait_r_reg[10] ; input sm_r; input pass_open_bank_r; input pass_open_bank_r_2; input pass_open_bank_r_3; input pass_open_bank_r_4; input bm_end_r1; input bm_end_r1_5; input bm_end_r1_6; input bm_end_r1_7; input fine_adjust_reg; input samp_edge_cnt0_en_r; input pi_cnt_dec; input \en_cnt_div4.wrlvl_odt_reg ; input \row_cnt_victim_rotate.complex_row_cnt_reg[7] ; input wr_victim_inc_reg; input phy_mc_go; input po_cnt_dec; wire [0:0]AS; wire CLK; wire [0:0]E; wire RST0; wire RST0_0; wire [0:0]SR; wire [0:0]SS; wire bm_end_r1; wire bm_end_r1_5; wire bm_end_r1_6; wire bm_end_r1_7; wire [0:0]cal2_done_r_reg; wire cal2_if_reset_reg; wire clk_div2_bufg_in; wire clk_pll_i; wire cnt_pwron_reset_done_r0; wire [0:0]\complex_address_reg[0] ; wire [0:0]\complex_num_reads_dec_reg[0] ; wire complex_sample_cnt_inc_reg; wire \dec_cnt_reg[0] ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ; wire \en_cnt_div4.wrlvl_odt_reg ; wire fine_adjust_reg; wire \fine_pi_dec_cnt_reg[0] ; wire first_rising_ps_clk_ns; wire first_rising_ps_clk_r; wire freq_refclk; wire [0:0]\gen_final_tap[2].final_val_reg[2][0] ; wire \gen_mmcm.u_bufg_clk_div2_n_0 ; wire in0; wire inv_poc_sample_ns0_out; wire inv_poc_sample_r; wire inv_poc_sample_r_i_2_n_0; wire \last_master_r_reg[2] ; wire \lim_state_reg[0] ; wire mem_refclk; wire mmcm_clk; wire mmcm_hi0_r; wire mmcm_hi0_r_i_1_n_0; wire mmcm_locked; wire mmcm_ps_clk; wire mmcm_ps_clk_bufg_in; wire [1:0]mpr_rank_done_r_reg; wire \oneeighty_r_reg[0] ; wire [0:0]\oneeighty_r_reg[0]_0 ; wire [7:0]p_0_in__2; wire p_81_in; wire pass_open_bank_r; wire pass_open_bank_r_2; wire pass_open_bank_r_3; wire pass_open_bank_r_4; wire phy_mc_go; wire pi_cnt_dec; wire \pi_rst_stg1_cal_r_reg[1] ; wire pll_clk3; wire pll_clk3_out; wire pll_clkfbout; wire pll_locked; wire pll_locked_i; wire po_cnt_dec; wire poc_backup_r_reg; wire poc_sample_pd; wire poc_sample_pd_ns; wire poc_sample_pd_r_i_2_n_0; wire pre_wait_r_reg; wire psdone; wire qcntr_ns; wire \qcntr_r[2]_i_1_n_0 ; wire \qcntr_r[3]_i_1_n_0 ; wire \qcntr_r[4]_i_1_n_0 ; wire \qcntr_r[5]_i_1_n_0 ; wire \qcntr_r[7]_i_3_n_0 ; wire [7:0]qcntr_r_reg__0; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire ras_timer_zero_r_reg_1; wire ras_timer_zero_r_reg_2; wire \rd_ptr_timing_reg[2] ; wire \read_fifo.head_r_reg[0] ; wire reset_reg; wire \resume_wait_r_reg[10] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[7] ; wire rst_out_reg; wire \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire [11:0]rst_sync_r; wire rst_sync_r1; wire [11:0]rstdiv0_sync_r; wire rstdiv0_sync_r1_reg_rep__0_n_0; wire rstdiv0_sync_r1_reg_rep__10_n_0; wire rstdiv0_sync_r1_reg_rep__11_n_0; wire rstdiv0_sync_r1_reg_rep__12_n_0; wire rstdiv0_sync_r1_reg_rep__13_n_0; wire rstdiv0_sync_r1_reg_rep__14_n_0; wire rstdiv0_sync_r1_reg_rep__15_n_0; wire rstdiv0_sync_r1_reg_rep__16_n_0; wire rstdiv0_sync_r1_reg_rep__17_n_0; wire rstdiv0_sync_r1_reg_rep__18_n_0; wire rstdiv0_sync_r1_reg_rep__19_n_0; wire rstdiv0_sync_r1_reg_rep__1_n_0; wire rstdiv0_sync_r1_reg_rep__20_n_0; wire rstdiv0_sync_r1_reg_rep__21_n_0; wire rstdiv0_sync_r1_reg_rep__22_n_0; wire rstdiv0_sync_r1_reg_rep__23_n_0; wire rstdiv0_sync_r1_reg_rep__24_n_0; wire rstdiv0_sync_r1_reg_rep__25_n_0; wire rstdiv0_sync_r1_reg_rep__26_n_0; wire rstdiv0_sync_r1_reg_rep__2_n_0; wire rstdiv0_sync_r1_reg_rep__3_n_0; wire rstdiv0_sync_r1_reg_rep__4_n_0; wire rstdiv0_sync_r1_reg_rep__5_n_0; wire rstdiv0_sync_r1_reg_rep__6_n_0; wire rstdiv0_sync_r1_reg_rep__7_n_0; wire rstdiv0_sync_r1_reg_rep__8_n_0; wire rstdiv0_sync_r1_reg_rep__9_n_0; wire rstdiv0_sync_r1_reg_rep_n_0; wire [11:0]rstdiv2_sync_r; (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rstdiv2_sync_r1; wire rtp_timer_ns1; wire rtp_timer_ns1_0; wire rtp_timer_ns1_1; wire \rtp_timer_r_reg[0] ; wire samp_edge_cnt0_en_r; wire \samp_edge_cnt0_r_reg[11] ; wire \simp_stg3_final_r_reg[17] ; wire sm_r; wire \stg3_r_reg[1] ; wire \stg3_tap_cnt_reg[0] ; wire sync_pulse; wire \two_dec_max_limit_reg[11] ; wire [0:0]\victim_sel_rotate.sel_reg[31] ; wire [0:0]\wait_cnt_r_reg[3] ; wire \wait_cnt_reg[3] ; wire [0:0]\wait_cnt_reg[3]_0 ; wire [0:0]\wl_tap_count_r_reg[0] ; wire wr_victim_inc_reg; wire \wr_victim_sel_ocal_reg[2] ; wire \wrcal_dqs_cnt_r_reg[2] ; wire \wrcal_reads_reg[0] ; wire \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ; wire \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ; wire [15:0]\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ; wire NLW_plle2_i_CLKOUT4_UNCONNECTED; wire NLW_plle2_i_CLKOUT5_UNCONNECTED; wire NLW_plle2_i_DRDY_UNCONNECTED; wire [15:0]NLW_plle2_i_DO_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'hE)) act_wait_r_lcl_i_3 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(bm_end_r1), .O(ras_timer_zero_r_reg)); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT2 #( .INIT(4'hE)) act_wait_r_lcl_i_3__0 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(bm_end_r1_5), .O(ras_timer_zero_r_reg_0)); LUT2 #( .INIT(4'hE)) act_wait_r_lcl_i_3__1 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(bm_end_r1_6), .O(ras_timer_zero_r_reg_1)); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'hE)) act_wait_r_lcl_i_3__2 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(bm_end_r1_7), .O(ras_timer_zero_r_reg_2)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \cal1_cnt_cpt_r[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__14_n_0), .O(mpr_rank_done_r_reg[1])); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) cal2_prech_req_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__4_n_0), .O(cal2_if_reset_reg)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \cal2_state_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__5_n_0), .O(cal2_done_r_reg)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) cke_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__0_n_0), .O(\read_fifo.head_r_reg[0] )); LUT2 #( .INIT(4'hB)) cnt_pwron_cke_done_r_i_3 (.I0(\wrcal_reads_reg[0] ), .I1(phy_mc_go), .O(cnt_pwron_reset_done_r0)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \complex_num_reads_dec[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__18_n_0), .O(\complex_num_reads_dec_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) complex_victim_inc_i_1 (.I0(rstdiv0_sync_r1_reg_rep__7_n_0), .O(\two_dec_max_limit_reg[11] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \dqs_count_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__17_n_0), .O(\wl_tap_count_r_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \en_cnt_div4.enable_wrlvl_cnt[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__10_n_0), .O(\en_cnt_div4.enable_wrlvl_cnt_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'hE)) \en_cnt_div4.enable_wrlvl_cnt[4]_i_2 (.I0(\wrcal_reads_reg[0] ), .I1(\en_cnt_div4.wrlvl_odt_reg ), .O(\en_cnt_div4.enable_wrlvl_cnt_reg[4] )); LUT1 #( .INIT(2'h1)) first_rising_ps_clk_r_i_1 (.I0(reset_reg), .O(first_rising_ps_clk_ns)); FDRE first_rising_ps_clk_r_reg (.C(mmcm_ps_clk), .CE(1'b1), .D(first_rising_ps_clk_ns), .Q(first_rising_ps_clk_r), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("HIGH"), .CLKFBOUT_MULT_F(4.000000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(4.448000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(8.000000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("TRUE"), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.000000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) \gen_mmcm.mmcm_i (.CLKFBIN(CLK), .CLKFBOUT(clk_pll_i), .CLKFBOUTB(\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ), .CLKFBSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ), .CLKIN1(pll_clk3), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ), .CLKOUT0(mmcm_ps_clk_bufg_in), .CLKOUT0B(\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ), .CLKOUT1(clk_div2_bufg_in), .CLKOUT1B(\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ), .CLKOUT2(\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ), .CLKOUT2B(\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ), .CLKOUT3(\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ), .CLKOUT3B(\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ), .CLKOUT4(\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ), .CLKOUT5(\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ), .CLKOUT6(\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]), .DRDY(\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ), .DWE(1'b0), .LOCKED(mmcm_locked), .PSCLK(CLK), .PSDONE(psdone), .PSEN(E), .PSINCDEC(1'b1), .PWRDWN(1'b0), .RST(RST0_0)); LUT1 #( .INIT(2'h1)) \gen_mmcm.mmcm_i_i_2 (.I0(pll_locked_i), .O(RST0_0)); (* BOX_TYPE = "PRIMITIVE" *) BUFG \gen_mmcm.u_bufg_clk_div2 (.I(clk_div2_bufg_in), .O(\gen_mmcm.u_bufg_clk_div2_n_0 )); (* BOX_TYPE = "PRIMITIVE" *) BUFG \gen_mmcm.u_bufg_mmcm_ps_clk (.I(mmcm_ps_clk_bufg_in), .O(mmcm_ps_clk)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___114_i_1 (.I0(rstdiv0_sync_r1_reg_rep__23_n_0), .O(\wait_cnt_reg[3] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___3_i_1 (.I0(rstdiv0_sync_r1_reg_rep__20_n_0), .O(\rtp_timer_r_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___4_i_1 (.I0(rstdiv0_sync_r1_reg_rep__21_n_0), .O(\last_master_r_reg[2] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) i___77_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22_n_0), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] )); LUT6 #( .INIT(64'h000000007FFF8000)) inv_poc_sample_r_i_1 (.I0(qcntr_r_reg__0[7]), .I1(qcntr_r_reg__0[6]), .I2(inv_poc_sample_r_i_2_n_0), .I3(E), .I4(inv_poc_sample_r), .I5(reset_reg), .O(inv_poc_sample_ns0_out)); LUT6 #( .INIT(64'hEAAAAAAAAAAAAAAA)) inv_poc_sample_r_i_2 (.I0(qcntr_r_reg__0[5]), .I1(qcntr_r_reg__0[4]), .I2(qcntr_r_reg__0[2]), .I3(qcntr_r_reg__0[0]), .I4(qcntr_r_reg__0[1]), .I5(qcntr_r_reg__0[3]), .O(inv_poc_sample_r_i_2_n_0)); FDRE inv_poc_sample_r_reg (.C(CLK), .CE(1'b1), .D(inv_poc_sample_ns0_out), .Q(inv_poc_sample_r), .R(1'b0)); LUT2 #( .INIT(4'h7)) mmcm_hi0_r_i_1 (.I0(mmcm_hi0_r), .I1(first_rising_ps_clk_r), .O(mmcm_hi0_r_i_1_n_0)); FDRE mmcm_hi0_r_reg (.C(CLK), .CE(1'b1), .D(mmcm_hi0_r_i_1_n_0), .Q(mmcm_hi0_r), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) ocal_last_byte_done_i_1 (.I0(rstdiv0_sync_r1_reg_rep__11_n_0), .O(\complex_address_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) ofs_rdy_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__1_n_0), .O(SR)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h7)) phaser_ref_i_i_1 (.I0(pll_locked_i), .I1(mmcm_locked), .O(RST0)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h8)) phy_control_i_i_1 (.I0(pll_locked_i), .I1(mmcm_locked), .O(pll_locked)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \pi_dqs_found_all_bank[1]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__13_n_0), .O(\dec_cnt_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h1)) \pi_rst_stg1_cal_r[1]_i_3 (.I0(\wrcal_reads_reg[0] ), .I1(fine_adjust_reg), .O(\pi_rst_stg1_cal_r_reg[1] )); (* BOX_TYPE = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(9), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.004000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(2), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(337.500000), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(32), .CLKOUT2_DUTY_CYCLE(0.062500), .CLKOUT2_PHASE(9.843750), .CLKOUT3_DIVIDE(8), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(4), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(168.750000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("INTERNAL"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_i (.CLKFBIN(pll_clkfbout), .CLKFBOUT(pll_clkfbout), .CLKIN1(mmcm_clk), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(freq_refclk), .CLKOUT1(mem_refclk), .CLKOUT2(sync_pulse), .CLKOUT3(pll_clk3_out), .CLKOUT4(NLW_plle2_i_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_i_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(pll_locked_i), .PWRDWN(1'b0), .RST(AS)); LUT6 #( .INIT(64'hBBBBEBBB44441444)) poc_sample_pd_r_i_1 (.I0(reset_reg), .I1(inv_poc_sample_r), .I2(E), .I3(inv_poc_sample_r_i_2_n_0), .I4(poc_sample_pd_r_i_2_n_0), .I5(mmcm_hi0_r), .O(poc_sample_pd_ns)); LUT2 #( .INIT(4'h7)) poc_sample_pd_r_i_2 (.I0(qcntr_r_reg__0[6]), .I1(qcntr_r_reg__0[7]), .O(poc_sample_pd_r_i_2_n_0)); FDRE poc_sample_pd_r_reg (.C(CLK), .CE(1'b1), .D(poc_sample_pd_ns), .Q(poc_sample_pd), .R(1'b0)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \prbs_state_r[4]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__8_n_0), .O(\fine_pi_dec_cnt_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT2 #( .INIT(4'h1)) pre_wait_r_i_2__0 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(pass_open_bank_r_2), .O(pre_wait_r_reg)); LUT2 #( .INIT(4'hE)) pre_wait_r_i_3 (.I0(\last_master_r_reg[2] ), .I1(pass_open_bank_r), .O(rtp_timer_ns1)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT2 #( .INIT(4'hE)) pre_wait_r_i_3__1 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(pass_open_bank_r_3), .O(rtp_timer_ns1_0)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT2 #( .INIT(4'hE)) pre_wait_r_i_3__2 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .I1(pass_open_bank_r_4), .O(rtp_timer_ns1_1)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) pwron_ce_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__12_n_0), .O(complex_sample_cnt_inc_reg)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT1 #( .INIT(2'h1)) \qcntr_r[0]_i_1 (.I0(qcntr_r_reg__0[0]), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h6)) \qcntr_r[1]_i_1 (.I0(qcntr_r_reg__0[0]), .I1(qcntr_r_reg__0[1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'h78)) \qcntr_r[2]_i_1 (.I0(qcntr_r_reg__0[1]), .I1(qcntr_r_reg__0[0]), .I2(qcntr_r_reg__0[2]), .O(\qcntr_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h7F80)) \qcntr_r[3]_i_1 (.I0(qcntr_r_reg__0[2]), .I1(qcntr_r_reg__0[0]), .I2(qcntr_r_reg__0[1]), .I3(qcntr_r_reg__0[3]), .O(\qcntr_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h7FFF8000)) \qcntr_r[4]_i_1 (.I0(qcntr_r_reg__0[3]), .I1(qcntr_r_reg__0[1]), .I2(qcntr_r_reg__0[0]), .I3(qcntr_r_reg__0[2]), .I4(qcntr_r_reg__0[4]), .O(\qcntr_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \qcntr_r[5]_i_1 (.I0(qcntr_r_reg__0[4]), .I1(qcntr_r_reg__0[2]), .I2(qcntr_r_reg__0[0]), .I3(qcntr_r_reg__0[1]), .I4(qcntr_r_reg__0[3]), .I5(qcntr_r_reg__0[5]), .O(\qcntr_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB4)) \qcntr_r[6]_i_1 (.I0(\qcntr_r[7]_i_3_n_0 ), .I1(qcntr_r_reg__0[5]), .I2(qcntr_r_reg__0[6]), .O(p_0_in__2[6])); LUT6 #( .INIT(64'hFFFFFFFFB0000000)) \qcntr_r[7]_i_1 (.I0(qcntr_r_reg__0[5]), .I1(\qcntr_r[7]_i_3_n_0 ), .I2(E), .I3(qcntr_r_reg__0[7]), .I4(qcntr_r_reg__0[6]), .I5(reset_reg), .O(qcntr_ns)); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'hBF40)) \qcntr_r[7]_i_2 (.I0(\qcntr_r[7]_i_3_n_0 ), .I1(qcntr_r_reg__0[5]), .I2(qcntr_r_reg__0[6]), .I3(qcntr_r_reg__0[7]), .O(p_0_in__2[7])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h7FFFFFFF)) \qcntr_r[7]_i_3 (.I0(qcntr_r_reg__0[3]), .I1(qcntr_r_reg__0[1]), .I2(qcntr_r_reg__0[0]), .I3(qcntr_r_reg__0[2]), .I4(qcntr_r_reg__0[4]), .O(\qcntr_r[7]_i_3_n_0 )); FDRE \qcntr_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in__2[0]), .Q(qcntr_r_reg__0[0]), .R(qcntr_ns)); FDRE \qcntr_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in__2[1]), .Q(qcntr_r_reg__0[1]), .R(qcntr_ns)); FDRE \qcntr_r_reg[2] (.C(CLK), .CE(E), .D(\qcntr_r[2]_i_1_n_0 ), .Q(qcntr_r_reg__0[2]), .R(qcntr_ns)); FDRE \qcntr_r_reg[3] (.C(CLK), .CE(E), .D(\qcntr_r[3]_i_1_n_0 ), .Q(qcntr_r_reg__0[3]), .R(qcntr_ns)); FDRE \qcntr_r_reg[4] (.C(CLK), .CE(E), .D(\qcntr_r[4]_i_1_n_0 ), .Q(qcntr_r_reg__0[4]), .R(qcntr_ns)); FDRE \qcntr_r_reg[5] (.C(CLK), .CE(E), .D(\qcntr_r[5]_i_1_n_0 ), .Q(qcntr_r_reg__0[5]), .R(qcntr_ns)); FDRE \qcntr_r_reg[6] (.C(CLK), .CE(E), .D(p_0_in__2[6]), .Q(qcntr_r_reg__0[6]), .R(qcntr_ns)); FDRE \qcntr_r_reg[7] (.C(CLK), .CE(E), .D(p_0_in__2[7]), .Q(qcntr_r_reg__0[7]), .R(qcntr_ns)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \rd_ptr_timing[2]_i_1__4 (.I0(rstdiv0_sync_r1_reg_rep__2_n_0), .O(\rd_ptr_timing_reg[2] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \rdlvl_dqs_tap_cnt_r[0][0][0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__15_n_0), .O(mpr_rank_done_r_reg[0])); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) reset_i_1 (.I0(rstdiv0_sync_r1_reg_rep__26_n_0), .O(reset_reg)); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) rst_out_i_2 (.I0(rstdiv0_sync_r1_reg_rep__9_n_0), .O(rst_out_reg)); FDPE rst_sync_r1_reg (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r1)); FDPE \rst_sync_r_reg[0] (.C(mmcm_ps_clk), .CE(1'b1), .D(1'b0), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[0])); FDPE \rst_sync_r_reg[10] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[9]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[10])); FDPE \rst_sync_r_reg[11] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[10]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[11])); FDPE \rst_sync_r_reg[1] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[0]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[1])); FDPE \rst_sync_r_reg[2] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[1]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[2])); FDPE \rst_sync_r_reg[3] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[2]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[3])); FDPE \rst_sync_r_reg[4] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[3]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[4])); FDPE \rst_sync_r_reg[5] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[4]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[5])); FDPE \rst_sync_r_reg[6] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[5]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[6])); FDPE \rst_sync_r_reg[7] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[6]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[7])); FDPE \rst_sync_r_reg[8] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[7]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[8])); FDPE \rst_sync_r_reg[9] (.C(mmcm_ps_clk), .CE(1'b1), .D(rst_sync_r[8]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rst_sync_r[9])); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__0 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__0_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__1 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__1_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__10 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__10_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__11 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__11_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__12 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__12_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__13 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__13_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__14 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__14_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__15 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__15_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__16 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__16_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__17 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__17_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__18 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__18_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__19 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__19_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__2 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__2_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__20 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__20_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__21 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__21_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__22 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__22_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__23 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__23_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__24 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__24_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__25 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__25_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__26 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__26_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__3 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__3_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__4 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__4_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__5 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__5_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__6 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__6_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__7 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__7_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__8 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__8_n_0)); (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) FDPE rstdiv0_sync_r1_reg_rep__9 (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r1_reg_rep__9_n_0)); FDPE \rstdiv0_sync_r_reg[0] (.C(CLK), .CE(1'b1), .D(1'b0), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[0])); FDPE \rstdiv0_sync_r_reg[10] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[9]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[10])); FDPE \rstdiv0_sync_r_reg[11] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[10]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[11])); FDPE \rstdiv0_sync_r_reg[1] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[0]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[1])); FDPE \rstdiv0_sync_r_reg[2] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[1]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[2])); FDPE \rstdiv0_sync_r_reg[3] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[2]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[3])); FDPE \rstdiv0_sync_r_reg[4] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[3]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[4])); FDPE \rstdiv0_sync_r_reg[5] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[4]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[5])); FDPE \rstdiv0_sync_r_reg[6] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[5]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[6])); FDPE \rstdiv0_sync_r_reg[7] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[6]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[7])); FDPE \rstdiv0_sync_r_reg[8] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[7]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[8])); FDPE \rstdiv0_sync_r_reg[9] (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r[8]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv0_sync_r[9])); (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) FDPE rstdiv2_sync_r1_reg (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[11]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r1)); FDPE \rstdiv2_sync_r_reg[0] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(1'b0), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[0])); FDPE \rstdiv2_sync_r_reg[10] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[9]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[10])); FDPE \rstdiv2_sync_r_reg[11] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[10]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[11])); FDPE \rstdiv2_sync_r_reg[1] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[0]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[1])); FDPE \rstdiv2_sync_r_reg[2] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[1]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[2])); FDPE \rstdiv2_sync_r_reg[3] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[2]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[3])); FDPE \rstdiv2_sync_r_reg[4] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[3]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[4])); FDPE \rstdiv2_sync_r_reg[5] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[4]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[5])); FDPE \rstdiv2_sync_r_reg[6] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[5]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[6])); FDPE \rstdiv2_sync_r_reg[7] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[6]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[7])); FDPE \rstdiv2_sync_r_reg[8] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[7]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[8])); FDPE \rstdiv2_sync_r_reg[9] (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ), .CE(1'b1), .D(rstdiv2_sync_r[8]), .PRE(\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .Q(rstdiv2_sync_r[9])); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'hB)) \samp_edge_cnt0_r[0]_i_1 (.I0(\wait_cnt_reg[3] ), .I1(samp_edge_cnt0_en_r), .O(\samp_edge_cnt0_r_reg[11] )); LUT2 #( .INIT(4'h1)) \simp_stg3_final_r[23]_i_2 (.I0(reset_reg), .I1(poc_backup_r_reg), .O(\simp_stg3_final_r_reg[17] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \smallest[0][5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__16_n_0), .O(\gen_final_tap[2].final_val_reg[2][0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \stg2_tap_cnt[5]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__19_n_0), .O(\victim_sel_rotate.sel_reg[31] )); LUT2 #( .INIT(4'hE)) \stg3_r[5]_i_13 (.I0(reset_reg), .I1(\resume_wait_r_reg[10] ), .O(\stg3_r_reg[1] )); LUT2 #( .INIT(4'h1)) \stg3_tap_cnt[5]_i_3 (.I0(reset_reg), .I1(\lim_state_reg[0] ), .O(\stg3_tap_cnt_reg[0] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \tempmon_state[0]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__3_n_0), .O(SS)); (* BOX_TYPE = "PRIMITIVE" *) BUFG u_bufg_clkdiv0 (.I(clk_pll_i), .O(CLK)); (* BOX_TYPE = "PRIMITIVE" *) BUFH u_bufh_pll_clk3 (.I(pll_clk3_out), .O(pll_clk3)); LUT1 #( .INIT(2'h2)) ui_clk_sync_rst_INST_0 (.I0(rstdiv0_sync_r1_reg_rep_n_0), .O(in0)); LUT2 #( .INIT(4'hE)) \wait_cnt[3]_i_1 (.I0(\wait_cnt_reg[3] ), .I1(po_cnt_dec), .O(\wait_cnt_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'hE)) \wait_cnt_r[3]_i_1__1 (.I0(\wait_cnt_reg[3] ), .I1(pi_cnt_dec), .O(\wait_cnt_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'hE)) \wr_victim_sel[2]_i_2 (.I0(\wrcal_reads_reg[0] ), .I1(\row_cnt_victim_rotate.complex_row_cnt_reg[7] ), .O(p_81_in)); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'hE)) \wr_victim_sel_ocal[2]_i_2 (.I0(\wrcal_reads_reg[0] ), .I1(wr_victim_inc_reg), .O(\wr_victim_sel_ocal_reg[2] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \wrcal_dqs_cnt_r[2]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__6_n_0), .O(\wrcal_dqs_cnt_r_reg[2] )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \wrcal_reads[7]_i_4 (.I0(rstdiv0_sync_r1_reg_rep__24_n_0), .O(\wrcal_reads_reg[0] )); LUT2 #( .INIT(4'h1)) \zero_r[9]_i_1 (.I0(\oneeighty_r_reg[0] ), .I1(sm_r), .O(\oneeighty_r_reg[0]_0 )); (* IS_FANOUT_CONSTRAINED = "1" *) LUT1 #( .INIT(2'h2)) \zero_r[9]_i_4 (.I0(rstdiv0_sync_r1_reg_rep__25_n_0), .O(\oneeighty_r_reg[0] )); endmodule module ddr3_if_mig_7series_v4_0_iodelay_ctrl (AS, rst_sync_r1_reg, mmcm_clk, sys_rst); output [0:0]AS; output [0:0]rst_sync_r1_reg; input mmcm_clk; input sys_rst; wire [0:0]AS; wire \clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ; wire clk_ref_mmcm_400; wire [0:0]iodelay_ctrl_rdy; wire mmcm_clk; wire mmcm_clkfbout; wire rst_ref_0; wire rst_ref_1; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ; wire \rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ; wire \rst_ref_sync_r_reg_n_0_[0][0] ; wire \rst_ref_sync_r_reg_n_0_[0][10] ; wire \rst_ref_sync_r_reg_n_0_[0][11] ; wire \rst_ref_sync_r_reg_n_0_[0][12] ; wire \rst_ref_sync_r_reg_n_0_[0][13] ; wire \rst_ref_sync_r_reg_n_0_[0][1] ; wire \rst_ref_sync_r_reg_n_0_[0][2] ; wire \rst_ref_sync_r_reg_n_0_[0][3] ; wire \rst_ref_sync_r_reg_n_0_[0][4] ; wire \rst_ref_sync_r_reg_n_0_[0][5] ; wire \rst_ref_sync_r_reg_n_0_[0][6] ; wire \rst_ref_sync_r_reg_n_0_[0][7] ; wire \rst_ref_sync_r_reg_n_0_[0][8] ; wire \rst_ref_sync_r_reg_n_0_[0][9] ; wire [0:0]rst_sync_r1_reg; wire sys_rst; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ; wire \NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ; wire [15:0]\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED ; (* BOX_TYPE = "PRIMITIVE" *) BUFG \clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400 (.I(clk_ref_mmcm_400), .O(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 )); (* BOX_TYPE = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("HIGH"), .CLKFBOUT_MULT_F(6.000000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(4.000000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), .CLKOUT1_DIVIDE(3), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("INTERNAL"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.000000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) \clk_ref_mmcm_gen.mmcm_i (.CLKFBIN(mmcm_clkfbout), .CLKFBOUT(mmcm_clkfbout), .CLKFBOUTB(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ), .CLKFBSTOPPED(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ), .CLKIN1(mmcm_clk), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ), .CLKOUT0(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ), .CLKOUT0B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ), .CLKOUT1(clk_ref_mmcm_400), .CLKOUT1B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ), .CLKOUT2(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ), .CLKOUT2B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ), .CLKOUT3(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ), .CLKOUT3B(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ), .CLKOUT4(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ), .CLKOUT5(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ), .CLKOUT6(\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED [15:0]), .DRDY(\NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ), .DWE(1'b0), .LOCKED(\NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ), .PSCLK(1'b0), .PSDONE(\NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ), .PSEN(1'b0), .PSINCDEC(1'b0), .PWRDWN(1'b0), .RST(AS)); LUT1 #( .INIT(2'h1)) \clk_ref_mmcm_gen.mmcm_i_i_1 (.I0(sys_rst), .O(AS)); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG1" *) IDELAYCTRL #( .SIM_DEVICE("7SERIES")) \idelayctrl_gen_1.u_idelayctrl_300_400 (.RDY(rst_sync_r1_reg), .REFCLK(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .RST(rst_ref_1)); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][0] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(1'b0), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][10] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][11] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][12] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][13] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ), .PRE(AS), .Q(rst_ref_1)); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][1] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][2] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][3] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][4] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][5] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][6] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][7] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][8] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] )); (* syn_maxfan = "10" *) FDPE \rst_ref_gen_1.rst_ref_sync_r_reg[1][9] (.C(\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ), .CE(1'b1), .D(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ), .PRE(AS), .Q(\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][0] (.C(mmcm_clk), .CE(1'b1), .D(1'b0), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][0] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][10] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][9] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][10] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][11] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][10] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][11] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][12] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][11] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][12] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][13] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][12] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][13] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][14] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][13] ), .PRE(AS), .Q(rst_ref_0)); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][1] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][0] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][1] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][2] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][1] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][2] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][3] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][2] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][3] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][4] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][3] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][4] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][5] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][4] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][5] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][6] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][5] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][6] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][7] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][6] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][7] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][8] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][7] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][8] )); (* syn_maxfan = "10" *) FDPE \rst_ref_sync_r_reg[0][9] (.C(mmcm_clk), .CE(1'b1), .D(\rst_ref_sync_r_reg_n_0_[0][8] ), .PRE(AS), .Q(\rst_ref_sync_r_reg_n_0_[0][9] )); (* BOX_TYPE = "PRIMITIVE" *) (* IODELAY_GROUP = "DDR3_IF_IODELAY_MIG0" *) IDELAYCTRL #( .SIM_DEVICE("7SERIES")) u_idelayctrl_200 (.RDY(iodelay_ctrl_rdy), .REFCLK(mmcm_clk), .RST(rst_ref_0)); endmodule module ddr3_if_mig_7series_v4_0_mc (accept_ns, sent_col, bm_end_r1, act_wait_r_lcl_reg, bm_end_r1_0, act_wait_r_lcl_reg_0, \ras_timer_r_reg[2] , act_wait_r_lcl_reg_1, bm_end_r1_4, act_wait_r_lcl_reg_2, app_ref_ack, app_zq_ack, mc_cmd, E, tempmon_sample_en, mc_ras_n, mc_cs_n, mc_cke, mc_wrdata_en, mc_cas_n, idle, mc_odt, app_sr_active, Q, \cmd_pipe_plus.mc_bank_reg[2]_0 , \read_fifo.tail_r_reg[1] , \rd_ptr_timing_reg[0] , mc_we_n, \rd_ptr_timing_reg[0]_0 , phy_dout, \my_full_reg[3] , \my_empty_reg[7] , bypass__0, \not_strict_mode.app_rd_data_end_reg , \cmd_pipe_plus.mc_bank_reg[8]_0 , \cmd_pipe_plus.mc_bank_reg[8]_1 , pointer_we, app_rd_data_end_ns, \write_buffer.wr_buf_out_data_reg[287] , \rd_ptr_timing_reg[0]_1 , \phy_ctl_wd_i1_reg[22] , \phy_ctl_wd_i1_reg[21] , \phy_ctl_wd_i1_reg[18] , \phy_ctl_wd_i1_reg[17] , \phy_ctl_wd_i1_reg[20] , \phy_ctl_wd_i1_reg[19] , \data_offset_1_i1_reg[5] , \data_offset_1_i1_reg[4] , \data_offset_1_i1_reg[1] , \data_offset_1_i1_reg[0] , \data_offset_1_i1_reg[3] , \data_offset_1_i1_reg[2] , CLK, rstdiv0_sync_r1_reg_rep__0, hi_priority, SR, of_ctl_full_v, phy_mc_ctl_full, maint_prescaler_r1, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, init_calib_complete_reg_rep__6, app_ref_req, app_zq_req, app_hi_pri_r2, use_addr, \app_cmd_r1_reg[0] , app_sr_req, rstdiv0_sync_r1_reg_rep__22, \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] , rstdiv0_sync_r1_reg_rep__23, \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , in0, init_calib_complete_reg_rep__7, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[0]_0 , \rd_buf_indx.rd_buf_indx_r_reg[4] , \entry_cnt_reg[2] , \entry_cnt_reg[2]_0 , bm_end_r1_reg, bm_end_r1_reg_0, bm_end_r1_reg_1, pass_open_bank_r_lcl_reg, \app_cmd_r2_reg[1] , bm_end_r1_reg_2, rtp_timer_ns1, rtp_timer_ns1_6, rtp_timer_ns1_7, \app_addr_r1_reg[27] , ram_init_done_r, \not_strict_mode.status_ram.rd_buf_we_r1_reg , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , \read_fifo.tail_r_reg[0] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] , \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 , granted_col_r_reg, granted_col_r_reg_0, \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] , \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 , granted_col_r_reg_1, granted_col_r_reg_2); output accept_ns; output sent_col; output bm_end_r1; output act_wait_r_lcl_reg; output bm_end_r1_0; output act_wait_r_lcl_reg_0; output \ras_timer_r_reg[2] ; output act_wait_r_lcl_reg_1; output bm_end_r1_4; output act_wait_r_lcl_reg_2; output app_ref_ack; output app_zq_ack; output [1:0]mc_cmd; output [0:0]E; output tempmon_sample_en; output [2:0]mc_ras_n; output [0:0]mc_cs_n; output [0:0]mc_cke; output mc_wrdata_en; output [2:0]mc_cas_n; output idle; output [0:0]mc_odt; output app_sr_active; output [2:0]Q; output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; output [0:0]\read_fifo.tail_r_reg[1] ; output [2:0]\rd_ptr_timing_reg[0] ; output [2:0]mc_we_n; output [3:0]\rd_ptr_timing_reg[0]_0 ; output [1:0]phy_dout; output [37:0]\my_full_reg[3] ; output [1:0]\my_empty_reg[7] ; output bypass__0; output [7:0]\not_strict_mode.app_rd_data_end_reg ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ; output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ; output pointer_we; output app_rd_data_end_ns; output [3:0]\write_buffer.wr_buf_out_data_reg[287] ; output [8:0]\rd_ptr_timing_reg[0]_1 ; output \phy_ctl_wd_i1_reg[22] ; output \phy_ctl_wd_i1_reg[21] ; output \phy_ctl_wd_i1_reg[18] ; output \phy_ctl_wd_i1_reg[17] ; output \phy_ctl_wd_i1_reg[20] ; output \phy_ctl_wd_i1_reg[19] ; output \data_offset_1_i1_reg[5] ; output \data_offset_1_i1_reg[4] ; output \data_offset_1_i1_reg[1] ; output \data_offset_1_i1_reg[0] ; output \data_offset_1_i1_reg[3] ; output \data_offset_1_i1_reg[2] ; input CLK; input rstdiv0_sync_r1_reg_rep__0; input hi_priority; input [0:0]SR; input [0:0]of_ctl_full_v; input phy_mc_ctl_full; input maint_prescaler_r1; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input init_calib_complete_reg_rep__6; input app_ref_req; input app_zq_req; input app_hi_pri_r2; input use_addr; input \app_cmd_r1_reg[0] ; input app_sr_req; input rstdiv0_sync_r1_reg_rep__22; input [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ; input [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ; input rstdiv0_sync_r1_reg_rep__23; input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; input in0; input init_calib_complete_reg_rep__7; input \req_bank_r_lcl_reg[2] ; input \req_bank_r_lcl_reg[2]_0 ; input \req_bank_r_lcl_reg[0] ; input \req_bank_r_lcl_reg[0]_0 ; input [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; input \entry_cnt_reg[2] ; input \entry_cnt_reg[2]_0 ; input bm_end_r1_reg; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input pass_open_bank_r_lcl_reg; input [0:0]\app_cmd_r2_reg[1] ; input bm_end_r1_reg_2; input rtp_timer_ns1; input rtp_timer_ns1_6; input rtp_timer_ns1_7; input [14:0]\app_addr_r1_reg[27] ; input ram_init_done_r; input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input \read_fifo.tail_r_reg[0] ; input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ; input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ; input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ; input granted_col_r_reg; input granted_col_r_reg_0; input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ; input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ; input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ; input granted_col_r_reg_1; input granted_col_r_reg_2; wire CLK; wire [0:0]E; wire [2:0]Q; wire [0:0]SR; wire accept_internal_r; wire accept_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire act_wait_r_lcl_reg_2; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire app_hi_pri_r2; wire app_rd_data_end_ns; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire [3:3]\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ; wire [3:3]\arb_mux0/arb_row_col0/row_arb0/last_master_r ; wire \arb_mux0/arb_select0/cke_r ; wire \arb_mux0/cs_en2 ; wire \bank_cntrl[0].bank0/auto_pre_r ; wire \bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ; wire \bank_cntrl[0].bank0/bank_state0/col_wait_r ; wire \bank_cntrl[0].bank0/bank_state0/demand_priority_r ; wire \bank_cntrl[0].bank0/bank_state0/demanded_prior_r ; wire \bank_cntrl[0].bank0/bank_state0/ras_timer_zero_r ; wire \bank_cntrl[0].bank0/q_has_priority ; wire \bank_cntrl[0].bank0/q_has_rd ; wire [1:1]\bank_cntrl[0].bank0/rb_hit_busies_r ; wire \bank_cntrl[0].bank0/row_hit_r ; wire \bank_cntrl[0].bank0/tail_r ; wire \bank_cntrl[0].bank0/wait_for_maint_r ; wire \bank_cntrl[1].bank0/auto_pre_r ; wire \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ; wire \bank_cntrl[1].bank0/bank_state0/col_wait_r ; wire \bank_cntrl[1].bank0/bank_state0/demand_priority_r ; wire [1:0]\bank_cntrl[1].bank0/bank_state0/rtp_timer_r ; wire \bank_cntrl[1].bank0/q_has_priority ; wire \bank_cntrl[1].bank0/q_has_rd ; wire [3:3]\bank_cntrl[1].bank0/rb_hit_busies_r ; wire \bank_cntrl[1].bank0/row_hit_r ; wire \bank_cntrl[1].bank0/tail_r ; wire \bank_cntrl[1].bank0/wait_for_maint_r ; wire \bank_cntrl[2].bank0/auto_pre_r ; wire \bank_cntrl[2].bank0/bank_queue0/pre_bm_end_r ; wire \bank_cntrl[2].bank0/bank_state0/col_wait_r ; wire \bank_cntrl[2].bank0/bank_state0/demand_priority_r ; wire \bank_cntrl[2].bank0/bank_state0/demanded_prior_r ; wire \bank_cntrl[2].bank0/bank_state0/override_demand_r ; wire \bank_cntrl[2].bank0/bank_state0/ras_timer_zero_r ; wire [1:0]\bank_cntrl[2].bank0/q_entry_r ; wire \bank_cntrl[2].bank0/q_has_priority ; wire \bank_cntrl[2].bank0/q_has_rd ; wire [5:5]\bank_cntrl[2].bank0/rb_hit_busies_r ; wire \bank_cntrl[2].bank0/row_hit_r ; wire \bank_cntrl[2].bank0/tail_r ; wire \bank_cntrl[2].bank0/wait_for_maint_r ; wire \bank_cntrl[3].bank0/auto_pre_r ; wire \bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ; wire \bank_cntrl[3].bank0/bank_state0/col_wait_r ; wire \bank_cntrl[3].bank0/bank_state0/demand_priority_r ; wire \bank_cntrl[3].bank0/bank_state0/demanded_prior_r ; wire [1:0]\bank_cntrl[3].bank0/q_entry_r ; wire \bank_cntrl[3].bank0/q_has_priority ; wire \bank_cntrl[3].bank0/q_has_rd ; wire [5:5]\bank_cntrl[3].bank0/rb_hit_busies_r ; wire \bank_cntrl[3].bank0/row_hit_r ; wire \bank_cntrl[3].bank0/tail_r ; wire \bank_cntrl[3].bank0/wait_for_maint_r ; wire [3:0]\bank_common0/maint_hit_busies_r ; wire \bank_common0/periodic_rd_cntr_r ; wire [0:0]\bank_common0/rfc_zq_xsdll_timer_ns ; wire [4:0]\bank_common0/rfc_zq_xsdll_timer_r ; wire bank_mach0_n_100; wire bank_mach0_n_105; wire bank_mach0_n_106; wire bank_mach0_n_108; wire bank_mach0_n_109; wire bank_mach0_n_111; wire bank_mach0_n_113; wire bank_mach0_n_115; wire bank_mach0_n_116; wire bank_mach0_n_118; wire bank_mach0_n_121; wire bank_mach0_n_122; wire bank_mach0_n_126; wire bank_mach0_n_127; wire bank_mach0_n_128; wire bank_mach0_n_129; wire bank_mach0_n_130; wire bank_mach0_n_131; wire bank_mach0_n_132; wire bank_mach0_n_135; wire bank_mach0_n_136; wire bank_mach0_n_137; wire bank_mach0_n_138; wire bank_mach0_n_141; wire bank_mach0_n_144; wire bank_mach0_n_145; wire bank_mach0_n_146; wire bank_mach0_n_147; wire bank_mach0_n_148; wire bank_mach0_n_149; wire bank_mach0_n_150; wire bank_mach0_n_151; wire bank_mach0_n_152; wire bank_mach0_n_153; wire bank_mach0_n_154; wire bank_mach0_n_155; wire bank_mach0_n_156; wire bank_mach0_n_157; wire bank_mach0_n_158; wire bank_mach0_n_159; wire bank_mach0_n_160; wire bank_mach0_n_161; wire bank_mach0_n_162; wire bank_mach0_n_2; wire bank_mach0_n_259; wire bank_mach0_n_265; wire bank_mach0_n_266; wire bank_mach0_n_267; wire bank_mach0_n_268; wire bank_mach0_n_269; wire bank_mach0_n_275; wire bank_mach0_n_276; wire bank_mach0_n_278; wire bank_mach0_n_279; wire bank_mach0_n_280; wire bank_mach0_n_281; wire bank_mach0_n_282; wire bank_mach0_n_283; wire bank_mach0_n_284; wire bank_mach0_n_98; wire bank_mach0_n_99; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_4; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bypass__0; wire clear_periodic_rd_request; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ; wire \cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ; wire [4:0]col_data_buf_addr; wire col_mach0_n_16; wire col_mach0_n_21; wire col_periodic_rd; wire col_rd_wr; wire col_rd_wr_r1; wire col_rd_wr_r2; wire [3:0]col_wr_data_buf_addr_r; wire \data_offset_1_i1_reg[0] ; wire \data_offset_1_i1_reg[1] ; wire \data_offset_1_i1_reg[2] ; wire \data_offset_1_i1_reg[3] ; wire \data_offset_1_i1_reg[4] ; wire \data_offset_1_i1_reg[5] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \entry_cnt_reg[2] ; wire \entry_cnt_reg[2]_0 ; wire [2:0]faw_cnt_r; wire granted_col_r_reg; wire granted_col_r_reg_0; wire granted_col_r_reg_1; wire granted_col_r_reg_2; wire [3:0]head_r; wire hi_priority; wire i___0_n_0; wire i___100_n_0; wire i___101_n_0; wire i___102_n_0; wire i___103_n_0; wire i___104_n_0; wire i___105_n_0; wire i___106_n_0; wire i___107_n_0; wire i___108_n_0; wire i___109_n_0; wire i___10_n_0; wire i___110_n_0; wire i___111_n_0; wire i___112_n_0; wire i___113_n_0; wire i___114_n_0; wire i___115_n_0; wire i___116_n_0; wire i___117_n_0; wire i___118_n_0; wire i___119_n_0; wire i___11_n_0; wire i___120_n_0; wire i___12_n_0; wire i___13_n_0; wire i___14_n_0; wire i___15_n_0; wire i___16_n_0; wire i___17_n_0; wire i___18_n_0; wire i___19_n_0; wire i___1_n_0; wire i___20_n_0; wire i___21_n_0; wire i___22_n_0; wire i___23_n_0; wire i___24_n_0; wire i___25_n_0; wire i___26_n_0; wire i___27_n_0; wire i___28_n_0; wire i___29_n_0; wire i___2_n_0; wire i___30_n_0; wire i___31_n_0; wire i___32_n_0; wire i___33_n_0; wire i___34_n_0; wire i___35_n_0; wire i___36_n_0; wire i___37_n_0; wire i___38_n_0; wire i___39_n_0; wire i___3_n_0; wire i___40_n_0; wire i___41_n_0; wire i___42_n_0; wire i___43_n_0; wire i___44_n_0; wire i___45_n_0; wire i___46_n_0; wire i___47_n_0; wire i___48_n_0; wire i___49_n_0; wire i___4_n_0; wire i___50_n_0; wire i___51_n_0; wire i___52_n_0; wire i___53_n_0; wire i___54_n_0; wire i___55_n_0; wire i___56_n_0; wire i___57_n_0; wire i___58_n_0; wire i___59_n_0; wire i___5_n_0; wire i___60_n_0; wire i___61_n_0; wire i___62_n_0; wire i___63_n_0; wire i___64_n_0; wire i___65_n_0; wire i___66_n_0; wire i___67_n_0; wire i___68_n_0; wire i___69_n_0; wire i___6_n_0; wire i___70_n_0; wire i___71_n_0; wire i___72_n_0; wire i___73_n_0; wire i___74_n_0; wire i___75_n_0; wire i___76_n_0; wire i___77_n_0; wire i___78_n_0; wire i___79_n_0; wire i___7_n_0; wire i___80_n_0; wire i___81_n_0; wire i___82_n_0; wire i___83_n_0; wire i___84_n_0; wire i___85_n_0; wire i___86_n_0; wire i___87_n_0; wire i___88_n_0; wire i___89_n_0; wire i___8_n_0; wire i___90_n_0; wire i___91_n_0; wire i___92_n_0; wire i___93_n_0; wire i___94_n_0; wire i___95_n_0; wire i___96_n_0; wire i___97_n_0; wire i___98_n_0; wire i___99_n_0; wire i___9_n_0; wire idle; wire [3:0]idle_r; wire in0; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__7; wire insert_maint_r; wire insert_maint_r1; wire maint_prescaler_r1; wire maint_ref_zq_wip; wire maint_req_r; wire maint_sre_r; wire maint_srx_r; wire maint_wip_r; wire maint_zq_r; wire [44:0]mc_address_ns; wire [8:0]mc_bank_ns; wire [2:0]mc_cas_n; wire [1:0]mc_cas_n_ns; wire [0:0]mc_cke; wire [1:1]mc_cke_ns; wire [1:0]mc_cmd; wire [1:1]mc_cmd_ns; wire [0:0]mc_cs_n; wire [0:0]mc_cs_n_ns; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_ras_n_ns; wire mc_ref_zq_wip_ns; wire [2:0]mc_we_n; wire [2:0]mc_we_n_ns; wire mc_wrdata_en; wire [1:0]\my_empty_reg[7] ; wire [37:0]\my_full_reg[3] ; wire [7:0]\not_strict_mode.app_rd_data_end_reg ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire [0:0]of_ctl_full_v; wire [3:0]ordered_r; wire pass_open_bank_r_lcl_reg; wire periodic_rd_ack_r; wire periodic_rd_r; wire \phy_ctl_wd_i1_reg[17] ; wire \phy_ctl_wd_i1_reg[18] ; wire \phy_ctl_wd_i1_reg[19] ; wire \phy_ctl_wd_i1_reg[20] ; wire \phy_ctl_wd_i1_reg[21] ; wire \phy_ctl_wd_i1_reg[22] ; wire [1:0]phy_dout; wire phy_mc_ctl_full; wire pointer_we; wire ram_init_done_r; wire \rank_cntrl[0].rank_cntrl0/act_delayed ; wire \rank_cntrl[0].rank_cntrl0/act_this_rank ; wire \rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ; wire \rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ; wire \rank_cntrl[0].rank_cntrl0/read_this_rank ; wire \rank_cntrl[0].rank_cntrl0/read_this_rank_r ; wire \rank_cntrl[0].rank_cntrl0/refresh_bank_r ; wire \rank_common0/app_ref_r ; wire \rank_common0/app_zq_r ; wire [2:0]\rank_common0/maint_grant_r ; wire [1:0]\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ; wire \rank_common0/maint_prescaler_tick_ns ; wire [2:0]\rank_common0/maintenance_request.maint_arb0/last_master_r ; wire \rank_common0/new_maint_rank_r ; wire \rank_common0/periodic_rd_grant_r ; wire \rank_common0/periodic_rd_r_cnt ; wire [1:0]\rank_common0/refresh_timer.refresh_timer_r_reg__0 ; wire \rank_common0/sre_request_r ; wire \rank_common0/upd_last_master_r ; wire \rank_common0/zq_request_r ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ; wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ; wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ; wire [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ; wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ; wire rank_mach0_n_27; wire rank_mach0_n_30; wire rank_mach0_n_34; wire rank_mach0_n_40; wire rank_mach0_n_42; wire rank_mach0_n_43; wire rank_mach0_n_44; wire rank_mach0_n_45; wire rank_mach0_n_46; wire rank_mach0_n_47; wire rank_mach0_n_48; wire rank_mach0_n_49; wire rank_mach0_n_5; wire rank_mach0_n_50; wire rank_mach0_n_51; wire rank_mach0_n_52; wire rank_mach0_n_53; wire rank_mach0_n_54; wire rank_mach0_n_55; wire rank_mach0_n_56; wire rank_mach0_n_57; wire rank_mach0_n_58; wire rank_mach0_n_59; wire rank_mach0_n_60; wire rank_mach0_n_61; wire rank_mach0_n_62; wire rank_mach0_n_63; wire rank_mach0_n_64; wire rank_mach0_n_71; wire \ras_timer_r_reg[2] ; wire [3:0]rb_hit_busy_r; wire [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; wire [2:0]\rd_ptr_timing_reg[0] ; wire [3:0]\rd_ptr_timing_reg[0]_0 ; wire [8:0]\rd_ptr_timing_reg[0]_1 ; wire [3:0]rd_wr_r; wire \read_fifo.tail_r_reg[0] ; wire [0:0]\read_fifo.tail_r_reg[1] ; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[0]_0 ; wire \req_bank_r_lcl_reg[2] ; wire \req_bank_r_lcl_reg[2]_0 ; wire [55:0]req_row_r; wire [3:0]req_wr_r; wire rnk_config_valid_r; wire [3:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rtp_timer_ns1; wire rtp_timer_ns1_6; wire rtp_timer_ns1_7; wire [1:1]rtw_cnt_r; wire [3:0]sending_col; wire [3:0]sending_pre; wire [3:1]sending_row; wire sent_col; wire sent_col_r2; wire sent_row; wire [2:1]tail_r; wire tempmon_sample_en; wire use_addr; wire was_wr; wire [3:0]\write_buffer.wr_buf_out_data_reg[287] ; wire [2:0]wtr_cnt_r; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ; wire [3:3]\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ; ddr3_if_mig_7series_v4_0_bank_mach bank_mach0 (.CLK(CLK), .D({i___53_n_0,i___50_n_0,i___40_n_0,i___55_n_0}), .DIC(col_periodic_rd), .E(mc_cmd_ns), .Q(sending_col), .SR(SR), .accept_internal_r(accept_internal_r), .accept_internal_r_reg(bank_mach0_n_106), .accept_ns(accept_ns), .accept_r_reg(i___75_n_0), .accept_r_reg_0(i___76_n_0), .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ), .\act_this_rank_r_reg[0] ({row_cmd_wr[3:2],row_cmd_wr[0]}), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0), .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1), .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2), .act_wait_r_lcl_reg_3(i___113_n_0), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .auto_pre_r(\bank_cntrl[0].bank0/auto_pre_r ), .auto_pre_r_25(\bank_cntrl[1].bank0/auto_pre_r ), .auto_pre_r_27(\bank_cntrl[2].bank0/auto_pre_r ), .auto_pre_r_29(\bank_cntrl[3].bank0/auto_pre_r ), .auto_pre_r_lcl_reg(bank_mach0_n_265), .auto_pre_r_lcl_reg_0(bank_mach0_n_266), .auto_pre_r_lcl_reg_1(bank_mach0_n_268), .auto_pre_r_lcl_reg_2(bank_mach0_n_269), .auto_pre_r_lcl_reg_3(i___2_n_0), .auto_pre_r_lcl_reg_4(i___7_n_0), .auto_pre_r_lcl_reg_5(i___11_n_0), .auto_pre_r_lcl_reg_6(i___15_n_0), .bm_end_r1(bm_end_r1), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_4(bm_end_r1_4), .bm_end_r1_reg(bm_end_r1_reg), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .cke_r(\arb_mux0/arb_select0/cke_r ), .clear_periodic_rd_request(clear_periodic_rd_request), .\cmd_pipe_plus.mc_address_reg[10] ({req_row_r[55],req_row_r[29:26],req_row_r[24:11],req_row_r[9:0]}), .\cmd_pipe_plus.mc_address_reg[44] ({mc_address_ns[44:30],mc_address_ns[25:18],mc_address_ns[14:0]}), .\cmd_pipe_plus.mc_bank_reg[2] (Q), .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ), .\cmd_pipe_plus.mc_bank_reg[7] (sending_pre), .\cmd_pipe_plus.mc_bank_reg[8] (mc_bank_ns), .\cmd_pipe_plus.mc_bank_reg[8]_0 (\cmd_pipe_plus.mc_bank_reg[8]_0 ), .\cmd_pipe_plus.mc_bank_reg[8]_1 (\cmd_pipe_plus.mc_bank_reg[8]_1 ), .\cmd_pipe_plus.mc_cmd_reg[0] (sent_col), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (bank_mach0_n_98), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (bank_mach0_n_99), .\cmd_pipe_plus.mc_we_n_reg[1] (bank_mach0_n_284), .col_data_buf_addr(col_data_buf_addr), .col_rd_wr(col_rd_wr), .col_wait_r(\bank_cntrl[0].bank0/bank_state0/col_wait_r ), .col_wait_r_21(\bank_cntrl[1].bank0/bank_state0/col_wait_r ), .col_wait_r_22(\bank_cntrl[2].bank0/bank_state0/col_wait_r ), .col_wait_r_23(\bank_cntrl[3].bank0/bank_state0/col_wait_r ), .col_wait_r_reg(i___38_n_0), .col_wait_r_reg_0(i___56_n_0), .col_wait_r_reg_1(i___36_n_0), .col_wait_r_reg_2(i___37_n_0), .\compute_tail.tail_r_lcl_reg (bank_mach0_n_157), .cs_en2(\arb_mux0/cs_en2 ), .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (col_wr_data_buf_addr_r), .demand_priority_r(\bank_cntrl[0].bank0/bank_state0/demand_priority_r ), .demand_priority_r_1(\bank_cntrl[1].bank0/bank_state0/demand_priority_r ), .demand_priority_r_13(\bank_cntrl[3].bank0/bank_state0/demand_priority_r ), .demand_priority_r_7(\bank_cntrl[2].bank0/bank_state0/demand_priority_r ), .demanded_prior_r(\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ), .demanded_prior_r_14(\bank_cntrl[3].bank0/bank_state0/demanded_prior_r ), .demanded_prior_r_8(\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ), .demanded_prior_r_reg(bank_mach0_n_276), .demanded_prior_r_reg_0(bank_mach0_n_283), .\entry_cnt_reg[2] (\entry_cnt_reg[2] ), .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2]_0 ), .\generate_maint_cmds.insert_maint_r_lcl_reg (rank_mach0_n_40), .\grant_r_reg[0] (i___111_n_0), .\grant_r_reg[0]_0 (i___110_n_0), .\grant_r_reg[0]_1 (i___109_n_0), .\grant_r_reg[0]_10 (i___100_n_0), .\grant_r_reg[0]_11 (i___99_n_0), .\grant_r_reg[0]_12 (i___98_n_0), .\grant_r_reg[0]_2 (i___108_n_0), .\grant_r_reg[0]_3 (i___107_n_0), .\grant_r_reg[0]_4 (i___106_n_0), .\grant_r_reg[0]_5 (i___105_n_0), .\grant_r_reg[0]_6 (i___104_n_0), .\grant_r_reg[0]_7 (i___103_n_0), .\grant_r_reg[0]_8 (i___102_n_0), .\grant_r_reg[0]_9 (i___101_n_0), .\grant_r_reg[1] (bank_mach0_n_158), .\grant_r_reg[1]_0 (bank_mach0_n_160), .\grant_r_reg[1]_1 (bank_mach0_n_275), .\grant_r_reg[2] (bank_mach0_n_154), .\grant_r_reg[3] (bank_mach0_n_161), .\grant_r_reg[3]_0 (bank_mach0_n_259), .granted_row_r_reg(i___71_n_0), .granted_row_r_reg_0(i___70_n_0), .head_r(head_r), .head_r_lcl_reg(bank_mach0_n_135), .head_r_lcl_reg_0(bank_mach0_n_144), .head_r_lcl_reg_1(bank_mach0_n_148), .head_r_lcl_reg_2(bank_mach0_n_149), .head_r_lcl_reg_3(bank_mach0_n_152), .head_r_lcl_reg_4(bank_mach0_n_153), .head_r_lcl_reg_5(bank_mach0_n_267), .head_r_lcl_reg_6(i___1_n_0), .head_r_lcl_reg_7(i___6_n_0), .head_r_lcl_reg_8(i___10_n_0), .head_r_lcl_reg_9(i___14_n_0), .hi_priority(hi_priority), .idle_r(idle_r), .idle_r_lcl_reg(i___0_n_0), .idle_r_lcl_reg_0(i___5_n_0), .idle_r_lcl_reg_1(i___9_n_0), .idle_r_lcl_reg_2(i___13_n_0), .idle_r_lcl_reg_3(i___92_n_0), .idle_r_lcl_reg_4(i___91_n_0), .idle_r_lcl_reg_5(i___57_n_0), .idle_r_lcl_reg_6(i___39_n_0), .idle_r_lcl_reg_7(i___52_n_0), .\inhbt_act_faw.inhbt_act_faw_r_reg (bank_mach0_n_278), .inhbt_act_faw_r(inhbt_act_faw_r), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .insert_maint_r(insert_maint_r), .insert_maint_r1(insert_maint_r1), .\last_master_r_reg[3] (sending_row), .\last_master_r_reg[3]_0 (\arb_mux0/arb_row_col0/row_arb0/last_master_r ), .\last_master_r_reg[3]_1 (\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ), .\last_master_r_reg[3]_2 (i___78_n_0), .\last_master_r_reg[3]_3 (i___79_n_0), .\maint_controller.maint_hit_busies_r_reg[3] (\bank_common0/maint_hit_busies_r ), .\maint_controller.maint_rdy_r1_reg (bank_mach0_n_141), .maint_req_r(maint_req_r), .maint_srx_r(maint_srx_r), .maint_wip_r(maint_wip_r), .maint_zq_r(maint_zq_r), .\maintenance_request.maint_req_r_lcl_reg (i___77_n_0), .\maintenance_request.maint_zq_r_lcl_reg (rank_mach0_n_42), .mc_cas_n_ns(mc_cas_n_ns), .mc_cke_ns(mc_cke_ns), .mc_cs_n_ns(mc_cs_n_ns), .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}), .mc_we_n_ns({mc_we_n_ns[2],mc_we_n_ns[0]}), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .of_ctl_full_v(of_ctl_full_v), .ordered_r(ordered_r), .ordered_r_lcl_reg(bank_mach0_n_132), .ordered_r_lcl_reg_0(bank_mach0_n_138), .ordered_r_lcl_reg_1(bank_mach0_n_147), .ordered_r_lcl_reg_2(i___3_n_0), .ordered_r_lcl_reg_3(i___8_n_0), .ordered_r_lcl_reg_4(i___12_n_0), .ordered_r_lcl_reg_5(i___16_n_0), .override_demand_r(\bank_cntrl[2].bank0/bank_state0/override_demand_r ), .override_demand_r_reg(i___90_n_0), .override_demand_r_reg_0(i___89_n_0), .override_demand_r_reg_1(i___88_n_0), .pass_open_bank_r_lcl_reg(bank_mach0_n_159), .pass_open_bank_r_lcl_reg_0(bank_mach0_n_162), .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg), .pass_open_bank_r_lcl_reg_2(i___4_n_0), .periodic_rd_ack_r(periodic_rd_ack_r), .periodic_rd_ack_r_lcl_reg(i___69_n_0), .periodic_rd_cntr_r(\bank_common0/periodic_rd_cntr_r ), .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (bank_mach0_n_118), .periodic_rd_grant_r(\rank_common0/periodic_rd_grant_r ), .periodic_rd_r(periodic_rd_r), .\periodic_read_request.periodic_rd_r_lcl_reg (i___68_n_0), .phy_mc_ctl_full(phy_mc_ctl_full), .pre_bm_end_r(\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ), .pre_bm_end_r_15(\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ), .pre_bm_end_r_2(\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ), .pre_bm_end_r_9(\bank_cntrl[2].bank0/bank_queue0/pre_bm_end_r ), .q_entry_r(\bank_cntrl[2].bank0/q_entry_r ), .q_entry_r_30(\bank_cntrl[3].bank0/q_entry_r ), .\q_entry_r_reg[0] (bank_mach0_n_108), .\q_entry_r_reg[0]_0 (bank_mach0_n_116), .\q_entry_r_reg[0]_1 (bank_mach0_n_151), .\q_entry_r_reg[1] (bank_mach0_n_2), .\q_entry_r_reg[1]_0 (bank_mach0_n_113), .\q_entry_r_reg[1]_1 (bank_mach0_n_115), .\q_entry_r_reg[1]_2 (bank_mach0_n_136), .\q_entry_r_reg[1]_3 (bank_mach0_n_137), .\q_entry_r_reg[1]_4 (bank_mach0_n_145), .\q_entry_r_reg[1]_5 (bank_mach0_n_146), .\q_entry_r_reg[1]_6 (bank_mach0_n_150), .q_has_priority(\bank_cntrl[0].bank0/q_has_priority ), .q_has_priority_11(\bank_cntrl[2].bank0/q_has_priority ), .q_has_priority_17(\bank_cntrl[3].bank0/q_has_priority ), .q_has_priority_4(\bank_cntrl[1].bank0/q_has_priority ), .q_has_priority_r_reg(i___59_n_0), .q_has_priority_r_reg_0(i___42_n_0), .q_has_priority_r_reg_1(i___65_n_0), .q_has_priority_r_reg_2(i___62_n_0), .q_has_rd(\bank_cntrl[0].bank0/q_has_rd ), .q_has_rd_10(\bank_cntrl[2].bank0/q_has_rd ), .q_has_rd_16(\bank_cntrl[3].bank0/q_has_rd ), .q_has_rd_3(\bank_cntrl[1].bank0/q_has_rd ), .q_has_rd_r_reg(i___58_n_0), .q_has_rd_r_reg_0(i___41_n_0), .q_has_rd_r_reg_1(i___64_n_0), .q_has_rd_r_reg_2(i___61_n_0), .\ras_timer_r_reg[0] (bank_mach0_n_126), .\ras_timer_r_reg[0]_0 (bank_mach0_n_127), .\ras_timer_r_reg[0]_1 (bank_mach0_n_128), .\ras_timer_r_reg[0]_2 (bank_mach0_n_129), .\ras_timer_r_reg[0]_3 (bank_mach0_n_130), .\ras_timer_r_reg[0]_4 (bank_mach0_n_131), .\ras_timer_r_reg[0]_5 (bank_mach0_n_155), .\ras_timer_r_reg[0]_6 (bank_mach0_n_156), .\ras_timer_r_reg[2] (\ras_timer_r_reg[2] ), .ras_timer_zero_r(\bank_cntrl[0].bank0/bank_state0/ras_timer_zero_r ), .ras_timer_zero_r_6(\bank_cntrl[2].bank0/bank_state0/ras_timer_zero_r ), .ras_timer_zero_r_reg(i___74_n_0), .ras_timer_zero_r_reg_0(i___73_n_0), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\bank_cntrl[0].bank0/rb_hit_busies_r ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\bank_cntrl[1].bank0/rb_hit_busies_r ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\bank_cntrl[2].bank0/rb_hit_busies_r ), .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\bank_cntrl[3].bank0/rb_hit_busies_r ), .rb_hit_busy_r(rb_hit_busy_r), .rb_hit_busy_r_reg(bank_mach0_n_105), .rb_hit_busy_r_reg_0(bank_mach0_n_109), .rb_hit_busy_r_reg_1(bank_mach0_n_111), .rb_hit_busy_r_reg_2(i___44_n_0), .rd_wr_r(rd_wr_r), .rd_wr_r_lcl_reg(i___33_n_0), .read_this_rank(\rank_cntrl[0].rank_cntrl0/read_this_rank ), .read_this_rank_r(\rank_cntrl[0].rank_cntrl0/read_this_rank_r ), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .\req_bank_r_lcl_reg[0]_0 (\req_bank_r_lcl_reg[0]_0 ), .\req_bank_r_lcl_reg[0]_1 (i___97_n_0), .\req_bank_r_lcl_reg[1] (i___96_n_0), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .\req_bank_r_lcl_reg[2]_1 (i___95_n_0), .req_wr_r(req_wr_r), .req_wr_r_lcl_reg(i___43_n_0), .req_wr_r_lcl_reg_0(i___66_n_0), .req_wr_r_lcl_reg_1(i___63_n_0), .req_wr_r_lcl_reg_2(i___60_n_0), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (bank_mach0_n_282), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (i___87_n_0), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ({i___25_n_0,i___24_n_0,\bank_common0/rfc_zq_xsdll_timer_ns }), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] (\bank_common0/rfc_zq_xsdll_timer_r ), .\rnk_config_strobe_r_reg[0] (bank_mach0_n_121), .rnk_config_valid_r(rnk_config_valid_r), .rnk_config_valid_r_lcl_reg(bank_mach0_n_122), .rnk_config_valid_r_lcl_reg_0(i___34_n_0), .row_hit_r(\bank_cntrl[0].bank0/row_hit_r ), .row_hit_r_0(\bank_cntrl[1].bank0/row_hit_r ), .row_hit_r_12(\bank_cntrl[3].bank0/row_hit_r ), .row_hit_r_5(\bank_cntrl[2].bank0/row_hit_r ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rtp_timer_ns1(rtp_timer_ns1), .rtp_timer_ns1_6(rtp_timer_ns1_6), .rtp_timer_ns1_7(rtp_timer_ns1_7), .rtp_timer_r(\bank_cntrl[1].bank0/bank_state0/rtp_timer_r ), .\rtw_timer.rtw_cnt_r_reg[1] (bank_mach0_n_100), .\rtw_timer.rtw_cnt_r_reg[1]_0 (rtw_cnt_r), .sent_row(sent_row), .tail_r(\bank_cntrl[0].bank0/tail_r ), .tail_r_24(\bank_cntrl[1].bank0/tail_r ), .tail_r_26(\bank_cntrl[2].bank0/tail_r ), .tail_r_28(\bank_cntrl[3].bank0/tail_r ), .use_addr(use_addr), .wait_for_maint_r(\bank_cntrl[0].bank0/wait_for_maint_r ), .wait_for_maint_r_18(\bank_cntrl[1].bank0/wait_for_maint_r ), .wait_for_maint_r_19(\bank_cntrl[2].bank0/wait_for_maint_r ), .wait_for_maint_r_20(\bank_cntrl[3].bank0/wait_for_maint_r ), .wait_for_maint_r_lcl_reg(i___54_n_0), .wait_for_maint_r_lcl_reg_0(i___48_n_0), .wait_for_maint_r_lcl_reg_1(i___49_n_0), .wait_for_maint_r_lcl_reg_2(i___51_n_0), .was_wr(was_wr), .\wtr_timer.wtr_cnt_r_reg[0] (bank_mach0_n_279), .\wtr_timer.wtr_cnt_r_reg[1] (bank_mach0_n_280), .\wtr_timer.wtr_cnt_r_reg[1]_0 (bank_mach0_n_281), .\wtr_timer.wtr_cnt_r_reg[1]_1 (rank_mach0_n_71)); FDRE \cmd_pipe_plus.mc_address_reg[0] (.C(CLK), .CE(1'b1), .D(mc_address_ns[0]), .Q(\my_full_reg[3] [0]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[10] (.C(CLK), .CE(1'b1), .D(mc_address_ns[10]), .Q(\my_full_reg[3] [10]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[11] (.C(CLK), .CE(1'b1), .D(mc_address_ns[11]), .Q(\my_full_reg[3] [11]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[12] (.C(CLK), .CE(1'b1), .D(mc_address_ns[12]), .Q(\my_full_reg[3] [12]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[13] (.C(CLK), .CE(1'b1), .D(mc_address_ns[13]), .Q(\my_full_reg[3] [13]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[14] (.C(CLK), .CE(1'b1), .D(mc_address_ns[14]), .Q(\my_full_reg[3] [14]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[18] (.C(CLK), .CE(1'b1), .D(mc_address_ns[18]), .Q(\my_full_reg[3] [15]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[19] (.C(CLK), .CE(1'b1), .D(mc_address_ns[19]), .Q(\my_full_reg[3] [16]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[1] (.C(CLK), .CE(1'b1), .D(mc_address_ns[1]), .Q(\my_full_reg[3] [1]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[20] (.C(CLK), .CE(1'b1), .D(mc_address_ns[20]), .Q(\my_full_reg[3] [17]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[21] (.C(CLK), .CE(1'b1), .D(mc_address_ns[21]), .Q(\my_full_reg[3] [18]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[22] (.C(CLK), .CE(1'b1), .D(mc_address_ns[22]), .Q(\my_full_reg[3] [19]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[23] (.C(CLK), .CE(1'b1), .D(mc_address_ns[23]), .Q(\my_full_reg[3] [20]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[24] (.C(CLK), .CE(1'b1), .D(mc_address_ns[24]), .Q(\my_full_reg[3] [21]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[25] (.C(CLK), .CE(1'b1), .D(mc_address_ns[25]), .Q(\my_full_reg[3] [22]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[2] (.C(CLK), .CE(1'b1), .D(mc_address_ns[2]), .Q(\my_full_reg[3] [2]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[30] (.C(CLK), .CE(1'b1), .D(mc_address_ns[30]), .Q(\my_full_reg[3] [23]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[31] (.C(CLK), .CE(1'b1), .D(mc_address_ns[31]), .Q(\my_full_reg[3] [24]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[32] (.C(CLK), .CE(1'b1), .D(mc_address_ns[32]), .Q(\my_full_reg[3] [25]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[33] (.C(CLK), .CE(1'b1), .D(mc_address_ns[33]), .Q(\my_full_reg[3] [26]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[34] (.C(CLK), .CE(1'b1), .D(mc_address_ns[34]), .Q(\my_full_reg[3] [27]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[35] (.C(CLK), .CE(1'b1), .D(mc_address_ns[35]), .Q(\my_full_reg[3] [28]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[36] (.C(CLK), .CE(1'b1), .D(mc_address_ns[36]), .Q(\my_full_reg[3] [29]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[37] (.C(CLK), .CE(1'b1), .D(mc_address_ns[37]), .Q(\my_full_reg[3] [30]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[38] (.C(CLK), .CE(1'b1), .D(mc_address_ns[38]), .Q(\my_full_reg[3] [31]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[39] (.C(CLK), .CE(1'b1), .D(mc_address_ns[39]), .Q(\my_full_reg[3] [32]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[3] (.C(CLK), .CE(1'b1), .D(mc_address_ns[3]), .Q(\my_full_reg[3] [3]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[40] (.C(CLK), .CE(1'b1), .D(mc_address_ns[40]), .Q(\my_full_reg[3] [33]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[41] (.C(CLK), .CE(1'b1), .D(mc_address_ns[41]), .Q(\my_full_reg[3] [34]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[42] (.C(CLK), .CE(1'b1), .D(mc_address_ns[42]), .Q(\my_full_reg[3] [35]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[43] (.C(CLK), .CE(1'b1), .D(mc_address_ns[43]), .Q(\my_full_reg[3] [36]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[44] (.C(CLK), .CE(1'b1), .D(mc_address_ns[44]), .Q(\my_full_reg[3] [37]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[4] (.C(CLK), .CE(1'b1), .D(mc_address_ns[4]), .Q(\my_full_reg[3] [4]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[5] (.C(CLK), .CE(1'b1), .D(mc_address_ns[5]), .Q(\my_full_reg[3] [5]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[6] (.C(CLK), .CE(1'b1), .D(mc_address_ns[6]), .Q(\my_full_reg[3] [6]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[7] (.C(CLK), .CE(1'b1), .D(mc_address_ns[7]), .Q(\my_full_reg[3] [7]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[8] (.C(CLK), .CE(1'b1), .D(mc_address_ns[8]), .Q(\my_full_reg[3] [8]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_address_reg[9] (.C(CLK), .CE(1'b1), .D(mc_address_ns[9]), .Q(\my_full_reg[3] [9]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[0] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[0]), .Q(\rd_ptr_timing_reg[0]_1 [0]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[1] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[1]), .Q(\rd_ptr_timing_reg[0]_1 [1]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[2] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[2]), .Q(\rd_ptr_timing_reg[0]_1 [2]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[3] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[3]), .Q(\rd_ptr_timing_reg[0]_1 [3]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[4] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[4]), .Q(\rd_ptr_timing_reg[0]_1 [4]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[5] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[5]), .Q(\rd_ptr_timing_reg[0]_1 [5]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[6] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[6]), .Q(\rd_ptr_timing_reg[0]_1 [6]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[7] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[7]), .Q(\rd_ptr_timing_reg[0]_1 [7]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_bank_reg[8] (.C(CLK), .CE(1'b1), .D(mc_bank_ns[8]), .Q(\rd_ptr_timing_reg[0]_1 [8]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cas_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_cas_n_ns[0]), .Q(mc_cas_n[0]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cas_n_reg[1] (.C(CLK), .CE(1'b1), .D(mc_cas_n_ns[1]), .Q(mc_cas_n[1]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cas_n_reg[2] (.C(CLK), .CE(1'b1), .D(i___112_n_0), .Q(mc_cas_n[2]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cke_reg[3] (.C(CLK), .CE(1'b1), .D(mc_cke_ns), .Q(mc_cke), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cmd_reg[0] (.C(CLK), .CE(1'b1), .D(sent_col), .Q(mc_cmd[0]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cmd_reg[1] (.C(CLK), .CE(1'b1), .D(mc_cmd_ns), .Q(mc_cmd[1]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_cs_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_cs_n_ns), .Q(mc_cs_n), .R(1'b0)); FDRE \cmd_pipe_plus.mc_data_offset_1_reg[0] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ), .Q(\data_offset_1_i1_reg[0] ), .R(bank_mach0_n_98)); FDRE \cmd_pipe_plus.mc_data_offset_1_reg[1] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ), .Q(\data_offset_1_i1_reg[1] ), .R(bank_mach0_n_98)); FDSE \cmd_pipe_plus.mc_data_offset_1_reg[2] (.C(CLK), .CE(1'b1), .D(granted_col_r_reg_2), .Q(\data_offset_1_i1_reg[2] ), .S(i___32_n_0)); FDSE \cmd_pipe_plus.mc_data_offset_1_reg[3] (.C(CLK), .CE(1'b1), .D(granted_col_r_reg_1), .Q(\data_offset_1_i1_reg[3] ), .S(i___32_n_0)); FDRE \cmd_pipe_plus.mc_data_offset_1_reg[4] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ), .Q(\data_offset_1_i1_reg[4] ), .R(bank_mach0_n_98)); FDRE \cmd_pipe_plus.mc_data_offset_1_reg[5] (.C(CLK), .CE(1'b1), .D(i___94_n_0), .Q(\data_offset_1_i1_reg[5] ), .R(bank_mach0_n_98)); FDRE \cmd_pipe_plus.mc_data_offset_2_reg[3] (.C(CLK), .CE(1'b1), .D(i___32_n_0), .Q(\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ), .R(1'b0)); FDRE \cmd_pipe_plus.mc_data_offset_reg[0] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ), .Q(\phy_ctl_wd_i1_reg[17] ), .R(bank_mach0_n_98)); FDRE \cmd_pipe_plus.mc_data_offset_reg[1] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ), .Q(\phy_ctl_wd_i1_reg[18] ), .R(bank_mach0_n_98)); FDSE \cmd_pipe_plus.mc_data_offset_reg[2] (.C(CLK), .CE(1'b1), .D(granted_col_r_reg_0), .Q(\phy_ctl_wd_i1_reg[19] ), .S(i___32_n_0)); FDSE \cmd_pipe_plus.mc_data_offset_reg[3] (.C(CLK), .CE(1'b1), .D(granted_col_r_reg), .Q(\phy_ctl_wd_i1_reg[20] ), .S(i___32_n_0)); FDRE \cmd_pipe_plus.mc_data_offset_reg[4] (.C(CLK), .CE(1'b1), .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ), .Q(\phy_ctl_wd_i1_reg[21] ), .R(bank_mach0_n_98)); FDRE \cmd_pipe_plus.mc_data_offset_reg[5] (.C(CLK), .CE(1'b1), .D(i___93_n_0), .Q(\phy_ctl_wd_i1_reg[22] ), .R(bank_mach0_n_98)); FDSE \cmd_pipe_plus.mc_odt_reg[0] (.C(CLK), .CE(1'b1), .D(\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ), .Q(mc_odt), .S(i___32_n_0)); FDRE \cmd_pipe_plus.mc_ras_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_ras_n_ns[0]), .Q(mc_ras_n[0]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_ras_n_reg[1] (.C(CLK), .CE(1'b1), .D(i___35_n_0), .Q(mc_ras_n[1]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_ras_n_reg[2] (.C(CLK), .CE(1'b1), .D(mc_ras_n_ns[2]), .Q(mc_ras_n[2]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_we_n_reg[0] (.C(CLK), .CE(1'b1), .D(mc_we_n_ns[0]), .Q(mc_we_n[0]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_we_n_reg[1] (.C(CLK), .CE(1'b1), .D(bank_mach0_n_284), .Q(mc_we_n[1]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_we_n_reg[2] (.C(CLK), .CE(1'b1), .D(mc_we_n_ns[2]), .Q(mc_we_n[2]), .R(1'b0)); FDRE \cmd_pipe_plus.mc_wrdata_en_reg (.C(CLK), .CE(1'b1), .D(i___117_n_0), .Q(mc_wrdata_en), .R(1'b0)); (* syn_maxfan = "30" *) FDRE \cmd_pipe_plus.wr_data_addr_reg[0] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[0]), .Q(\write_buffer.wr_buf_out_data_reg[287] [0]), .R(1'b0)); (* syn_maxfan = "30" *) FDRE \cmd_pipe_plus.wr_data_addr_reg[1] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[1]), .Q(\write_buffer.wr_buf_out_data_reg[287] [1]), .R(1'b0)); (* syn_maxfan = "30" *) FDRE \cmd_pipe_plus.wr_data_addr_reg[2] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[2]), .Q(\write_buffer.wr_buf_out_data_reg[287] [2]), .R(1'b0)); (* syn_maxfan = "30" *) FDRE \cmd_pipe_plus.wr_data_addr_reg[3] (.C(CLK), .CE(1'b1), .D(col_wr_data_buf_addr_r[3]), .Q(\write_buffer.wr_buf_out_data_reg[287] [3]), .R(1'b0)); FDRE \cmd_pipe_plus.wr_data_en_reg (.C(CLK), .CE(1'b1), .D(i___118_n_0), .Q(E), .R(1'b0)); ddr3_if_mig_7series_v4_0_col_mach col_mach0 (.ADDRA({i___115_n_0,i___114_n_0,i___116_n_0}), .CLK(CLK), .D(col_wr_data_buf_addr_r), .DIC(col_periodic_rd), .E(mc_cmd_ns), .SR(SR), .app_rd_data_end_ns(app_rd_data_end_ns), .bypass__0(bypass__0), .col_data_buf_addr(col_data_buf_addr), .col_rd_wr(col_rd_wr), .col_rd_wr_r1(col_rd_wr_r1), .col_rd_wr_r2(col_rd_wr_r2), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .maint_ref_zq_wip(maint_ref_zq_wip), .mc_cmd(mc_cmd[0]), .mc_read_idle_r_reg(col_mach0_n_16), .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns), .\not_strict_mode.app_rd_data_end_reg (\not_strict_mode.app_rd_data_end_reg ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .\rd_buf_indx.rd_buf_indx_r_reg[4] (\rd_buf_indx.rd_buf_indx_r_reg[4] ), .\read_fifo.fifo_out_data_r_reg[7]_0 (col_mach0_n_21), .\read_fifo.tail_r_reg[0]_0 (\read_fifo.tail_r_reg[0] ), .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1] ), .\read_fifo.tail_r_reg[2]_0 (tail_r), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .sent_col_r2(sent_col_r2)); LUT6 #( .INIT(64'hDDCCFFCFDDCCDDCC)) i___0 (.I0(bank_mach0_n_116), .I1(bank_mach0_n_151), .I2(idle_r[0]), .I3(i___47_n_0), .I4(i___76_n_0), .I5(\bank_cntrl[0].bank0/tail_r ), .O(i___0_n_0)); LUT5 #( .INIT(32'hB8FFB800)) i___1 (.I0(bank_mach0_n_148), .I1(bank_mach0_n_116), .I2(bank_mach0_n_267), .I3(bank_mach0_n_150), .I4(head_r[0]), .O(i___1_n_0)); LUT6 #( .INIT(64'hB888FFFFB8880000)) i___10 (.I0(bank_mach0_n_135), .I1(bank_mach0_n_113), .I2(bank_mach0_n_267), .I3(bank_mach0_n_152), .I4(bank_mach0_n_137), .I5(head_r[2]), .O(i___10_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___100 (.I0(sending_pre[0]), .I1(req_row_r[12]), .I2(sending_pre[1]), .I3(req_row_r[27]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___100_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___101 (.I0(sending_pre[0]), .I1(req_row_r[11]), .I2(sending_pre[1]), .I3(req_row_r[26]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___101_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___102 (.I0(sending_pre[0]), .I1(req_row_r[9]), .I2(sending_pre[1]), .I3(req_row_r[24]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___102_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___103 (.I0(sending_pre[0]), .I1(req_row_r[8]), .I2(sending_pre[1]), .I3(req_row_r[23]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___103_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___104 (.I0(sending_pre[0]), .I1(req_row_r[7]), .I2(sending_pre[1]), .I3(req_row_r[22]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___104_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___105 (.I0(sending_pre[0]), .I1(req_row_r[6]), .I2(sending_pre[1]), .I3(req_row_r[21]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___105_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___106 (.I0(sending_pre[0]), .I1(req_row_r[5]), .I2(sending_pre[1]), .I3(req_row_r[20]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___106_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___107 (.I0(sending_pre[0]), .I1(req_row_r[4]), .I2(sending_pre[1]), .I3(req_row_r[19]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___107_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___108 (.I0(sending_pre[0]), .I1(req_row_r[3]), .I2(sending_pre[1]), .I3(req_row_r[18]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___108_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___109 (.I0(sending_pre[0]), .I1(req_row_r[2]), .I2(sending_pre[1]), .I3(req_row_r[17]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___109_n_0)); LUT6 #( .INIT(64'h00000000AEAAEEEE)) i___11 (.I0(\bank_cntrl[2].bank0/auto_pre_r ), .I1(bank_mach0_n_269), .I2(\bank_cntrl[2].bank0/wait_for_maint_r ), .I3(bank_mach0_n_141), .I4(\bank_cntrl[2].bank0/row_hit_r ), .I5(i___66_n_0), .O(i___11_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___110 (.I0(sending_pre[0]), .I1(req_row_r[1]), .I2(sending_pre[1]), .I3(req_row_r[16]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___110_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___111 (.I0(sending_pre[0]), .I1(req_row_r[0]), .I2(sending_pre[1]), .I3(req_row_r[15]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___111_n_0)); LUT5 #( .INIT(32'hFFFFFFFB)) i___112 (.I0(sending_pre[1]), .I1(\arb_mux0/cs_en2 ), .I2(sending_pre[0]), .I3(sending_pre[3]), .I4(sending_pre[2]), .O(i___112_n_0)); LUT4 #( .INIT(16'h80FF)) i___113 (.I0(row_cmd_wr[3]), .I1(sending_pre[3]), .I2(req_row_r[55]), .I3(\arb_mux0/cs_en2 ), .O(i___113_n_0)); LUT5 #( .INIT(32'h15554000)) i___114 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\read_fifo.tail_r_reg[1] ), .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I3(tail_r[1]), .I4(tail_r[2]), .O(i___114_n_0)); LUT2 #( .INIT(4'h1)) i___115 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(col_mach0_n_21), .O(i___115_n_0)); LUT4 #( .INIT(16'h1540)) i___116 (.I0(rstdiv0_sync_r1_reg_rep__23), .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .I2(\read_fifo.tail_r_reg[1] ), .I3(tail_r[1]), .O(i___116_n_0)); LUT2 #( .INIT(4'h2)) i___117 (.I0(sent_col_r2), .I1(col_rd_wr_r2), .O(i___117_n_0)); LUT2 #( .INIT(4'h2)) i___118 (.I0(mc_cmd[0]), .I1(col_rd_wr_r1), .O(i___118_n_0)); LUT2 #( .INIT(4'h9)) i___119 (.I0(\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [0]), .I1(\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [1]), .O(i___119_n_0)); LUT6 #( .INIT(64'h00000000EAEA0AEA)) i___12 (.I0(ordered_r[2]), .I1(bank_mach0_n_132), .I2(req_wr_r[2]), .I3(sending_col[2]), .I4(rd_wr_r[2]), .I5(rstdiv0_sync_r1_reg_rep__21), .O(i___12_n_0)); LUT2 #( .INIT(4'h9)) i___120 (.I0(\rank_common0/refresh_timer.refresh_timer_r_reg__0 [0]), .I1(\rank_common0/refresh_timer.refresh_timer_r_reg__0 [1]), .O(i___120_n_0)); LUT6 #( .INIT(64'hDDCCFFCFDDCCDDCC)) i___13 (.I0(bank_mach0_n_115), .I1(bank_mach0_n_138), .I2(idle_r[3]), .I3(i___46_n_0), .I4(bank_mach0_n_159), .I5(\bank_cntrl[3].bank0/tail_r ), .O(i___13_n_0)); LUT6 #( .INIT(64'hB888FFFFB8880000)) i___14 (.I0(bank_mach0_n_144), .I1(bank_mach0_n_115), .I2(i___46_n_0), .I3(bank_mach0_n_267), .I4(bank_mach0_n_145), .I5(head_r[3]), .O(i___14_n_0)); LUT6 #( .INIT(64'h00000000AEAAEEEE)) i___15 (.I0(\bank_cntrl[3].bank0/auto_pre_r ), .I1(bank_mach0_n_268), .I2(\bank_cntrl[3].bank0/wait_for_maint_r ), .I3(bank_mach0_n_141), .I4(\bank_cntrl[3].bank0/row_hit_r ), .I5(i___63_n_0), .O(i___15_n_0)); LUT6 #( .INIT(64'h00000000EE0EAAAA)) i___16 (.I0(ordered_r[3]), .I1(bank_mach0_n_138), .I2(sending_col[3]), .I3(rd_wr_r[3]), .I4(req_wr_r[3]), .I5(rstdiv0_sync_r1_reg_rep__21), .O(i___16_n_0)); LUT5 #( .INIT(32'hFFFF0008)) i___17 (.I0(\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ), .I1(init_calib_complete_reg_rep__6), .I2(rank_mach0_n_5), .I3(periodic_rd_r), .I4(\rank_common0/periodic_rd_grant_r ), .O(i___17_n_0)); LUT4 #( .INIT(16'h2F20)) i___18 (.I0(maint_sre_r), .I1(maint_srx_r), .I2(insert_maint_r1), .I3(app_sr_active), .O(i___18_n_0)); LUT6 #( .INIT(64'hFFFFC400C400C400)) i___19 (.I0(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .I1(init_calib_complete_reg_rep__6), .I2(\rank_common0/zq_request_r ), .I3(insert_maint_r1), .I4(maint_wip_r), .I5(maint_ref_zq_wip), .O(i___19_n_0)); LUT6 #( .INIT(64'h00000000AEAAEEEE)) i___2 (.I0(\bank_cntrl[0].bank0/auto_pre_r ), .I1(bank_mach0_n_266), .I2(\bank_cntrl[0].bank0/wait_for_maint_r ), .I3(bank_mach0_n_141), .I4(\bank_cntrl[0].bank0/row_hit_r ), .I5(i___60_n_0), .O(i___2_n_0)); LUT2 #( .INIT(4'hB)) i___20 (.I0(\rank_common0/maint_prescaler_tick_ns ), .I1(init_calib_complete_reg_rep__6), .O(i___20_n_0)); (* SOFT_HLUTNM = "soft_lutpair1113" *) LUT5 #( .INIT(32'h88820008)) i___21 (.I0(init_calib_complete_reg_rep__6), .I1(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .I2(app_ref_req), .I3(rank_mach0_n_27), .I4(rank_mach0_n_43), .O(i___21_n_0)); (* SOFT_HLUTNM = "soft_lutpair1113" *) LUT2 #( .INIT(4'hB)) i___22 (.I0(rank_mach0_n_27), .I1(init_calib_complete_reg_rep__6), .O(i___22_n_0)); LUT5 #( .INIT(32'hFF2AFFFF)) i___23 (.I0(\rank_common0/zq_request_r ), .I1(insert_maint_r1), .I2(maint_zq_r), .I3(app_zq_req), .I4(rank_mach0_n_30), .O(i___23_n_0)); LUT5 #( .INIT(32'h00415541)) i___24 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(\bank_common0/rfc_zq_xsdll_timer_r [1]), .I2(\bank_common0/rfc_zq_xsdll_timer_r [0]), .I3(insert_maint_r), .I4(rank_mach0_n_34), .O(i___24_n_0)); LUT5 #( .INIT(32'h00415541)) i___25 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(i___87_n_0), .I2(\bank_common0/rfc_zq_xsdll_timer_r [4]), .I3(insert_maint_r), .I4(rank_mach0_n_34), .O(i___25_n_0)); LUT5 #( .INIT(32'h45444044)) i___26 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [0]), .I2(\rank_common0/new_maint_rank_r ), .I3(\rank_common0/upd_last_master_r ), .I4(\rank_common0/maint_grant_r [0]), .O(i___26_n_0)); LUT5 #( .INIT(32'h45444044)) i___27 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [1]), .I2(\rank_common0/new_maint_rank_r ), .I3(\rank_common0/upd_last_master_r ), .I4(\rank_common0/maint_grant_r [1]), .O(i___27_n_0)); LUT5 #( .INIT(32'h10111511)) i___28 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [2]), .I2(\rank_common0/new_maint_rank_r ), .I3(\rank_common0/upd_last_master_r ), .I4(\rank_common0/maint_grant_r [2]), .O(i___28_n_0)); LUT5 #( .INIT(32'h54005500)) i___29 (.I0(maint_wip_r), .I1(\rank_common0/zq_request_r ), .I2(\rank_common0/sre_request_r ), .I3(init_calib_complete_reg_rep__6), .I4(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .O(i___29_n_0)); LUT6 #( .INIT(64'h00000000EAEA0AEA)) i___3 (.I0(ordered_r[0]), .I1(bank_mach0_n_151), .I2(req_wr_r[0]), .I3(sending_col[0]), .I4(rd_wr_r[0]), .I5(rstdiv0_sync_r1_reg_rep__20), .O(i___3_n_0)); LUT6 #( .INIT(64'h00545454FFFFFFFF)) i___30 (.I0(bank_mach0_n_118), .I1(rank_mach0_n_64), .I2(\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ), .I3(clear_periodic_rd_request), .I4(\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ), .I5(init_calib_complete_reg_rep__6), .O(i___30_n_0)); LUT3 #( .INIT(8'h78)) i___31 (.I0(\rank_common0/periodic_rd_grant_r ), .I1(periodic_rd_ack_r), .I2(\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ), .O(i___31_n_0)); LUT2 #( .INIT(4'h8)) i___32 (.I0(bank_mach0_n_99), .I1(sent_col), .O(i___32_n_0)); LUT4 #( .INIT(16'h04F4)) i___33 (.I0(rd_wr_r[2]), .I1(sending_col[2]), .I2(sending_col[3]), .I3(rd_wr_r[3]), .O(i___33_n_0)); LUT3 #( .INIT(8'hFB)) i___34 (.I0(rnk_config_valid_r), .I1(bank_mach0_n_121), .I2(bank_mach0_n_122), .O(i___34_n_0)); LUT5 #( .INIT(32'hFFFEFFFF)) i___35 (.I0(sending_col[1]), .I1(sending_col[0]), .I2(sending_col[3]), .I3(sending_col[2]), .I4(sent_col), .O(i___35_n_0)); LUT6 #( .INIT(64'h4444444444445455)) i___36 (.I0(\bank_cntrl[2].bank0/bank_state0/col_wait_r ), .I1(i___92_n_0), .I2(bank_mach0_n_127), .I3(\bank_cntrl[2].bank0/rb_hit_busies_r ), .I4(bank_mach0_n_126), .I5(bank_mach0_n_154), .O(i___36_n_0)); LUT6 #( .INIT(64'h4444444444445455)) i___37 (.I0(\bank_cntrl[0].bank0/bank_state0/col_wait_r ), .I1(bank_mach0_n_130), .I2(bank_mach0_n_127), .I3(\bank_cntrl[0].bank0/rb_hit_busies_r ), .I4(bank_mach0_n_129), .I5(bank_mach0_n_158), .O(i___37_n_0)); LUT6 #( .INIT(64'h4444444444445455)) i___38 (.I0(\bank_cntrl[3].bank0/bank_state0/col_wait_r ), .I1(i___91_n_0), .I2(bank_mach0_n_127), .I3(\bank_cntrl[3].bank0/rb_hit_busies_r ), .I4(bank_mach0_n_131), .I5(bank_mach0_n_161), .O(i___38_n_0)); LUT6 #( .INIT(64'h6996966996696996)) i___39 (.I0(bank_mach0_n_108), .I1(idle_r[0]), .I2(idle_r[1]), .I3(idle_r[2]), .I4(idle_r[3]), .I5(bank_mach0_n_116), .O(i___39_n_0)); LUT5 #( .INIT(32'h11000010)) i___4 (.I0(act_wait_r_lcl_reg_0), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(sending_col[1]), .I3(\bank_cntrl[1].bank0/bank_state0/rtp_timer_r [1]), .I4(\bank_cntrl[1].bank0/bank_state0/rtp_timer_r [0]), .O(i___4_n_0)); LUT6 #( .INIT(64'h4444554544444444)) i___40 (.I0(i___43_n_0), .I1(\bank_common0/maint_hit_busies_r [1]), .I2(maint_req_r), .I3(\bank_common0/periodic_rd_cntr_r ), .I4(maint_wip_r), .I5(bank_mach0_n_105), .O(i___40_n_0)); LUT6 #( .INIT(64'h4454555544544454)) i___41 (.I0(i___43_n_0), .I1(\bank_cntrl[1].bank0/q_has_rd ), .I2(maint_req_r), .I3(idle_r[1]), .I4(was_wr), .I5(i___75_n_0), .O(i___41_n_0)); LUT6 #( .INIT(64'h2220202020202020)) i___42 (.I0(bank_mach0_n_108), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\bank_cntrl[1].bank0/q_has_priority ), .I3(app_hi_pri_r2), .I4(rb_hit_busy_r[1]), .I5(bank_mach0_n_136), .O(i___42_n_0)); LUT6 #( .INIT(64'hFFFFFFFFBFAAAAAA)) i___43 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(req_wr_r[1]), .I2(rd_wr_r[1]), .I3(act_wait_r_lcl_reg_0), .I4(sending_col[1]), .I5(\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ), .O(i___43_n_0)); LUT5 #( .INIT(32'h69969669)) i___44 (.I0(bank_mach0_n_149), .I1(rb_hit_busy_r[3]), .I2(rb_hit_busy_r[2]), .I3(rb_hit_busy_r[1]), .I4(rb_hit_busy_r[0]), .O(i___44_n_0)); LUT3 #( .INIT(8'h80)) i___45 (.I0(bank_mach0_n_108), .I1(bank_mach0_n_116), .I2(bank_mach0_n_115), .O(i___45_n_0)); (* SOFT_HLUTNM = "soft_lutpair1118" *) LUT3 #( .INIT(8'h80)) i___46 (.I0(bank_mach0_n_108), .I1(bank_mach0_n_113), .I2(bank_mach0_n_116), .O(i___46_n_0)); (* SOFT_HLUTNM = "soft_lutpair1118" *) LUT3 #( .INIT(8'h80)) i___47 (.I0(bank_mach0_n_108), .I1(bank_mach0_n_113), .I2(bank_mach0_n_115), .O(i___47_n_0)); LUT6 #( .INIT(64'hEAAAEAAAEAAAAAAA)) i___48 (.I0(\bank_cntrl[1].bank0/wait_for_maint_r ), .I1(idle_r[1]), .I2(head_r[1]), .I3(accept_internal_r), .I4(use_addr), .I5(periodic_rd_ack_r), .O(i___48_n_0)); LUT6 #( .INIT(64'hEAAAEAAAEAAAAAAA)) i___49 (.I0(\bank_cntrl[2].bank0/wait_for_maint_r ), .I1(idle_r[2]), .I2(head_r[2]), .I3(accept_internal_r), .I4(use_addr), .I5(periodic_rd_ack_r), .O(i___49_n_0)); LUT6 #( .INIT(64'hDDCCFFCFDDCCDDCC)) i___5 (.I0(bank_mach0_n_108), .I1(bank_mach0_n_147), .I2(idle_r[1]), .I3(bank_mach0_n_157), .I4(i___75_n_0), .I5(\bank_cntrl[1].bank0/tail_r ), .O(i___5_n_0)); LUT6 #( .INIT(64'h4444554544444444)) i___50 (.I0(i___66_n_0), .I1(\bank_common0/maint_hit_busies_r [2]), .I2(maint_req_r), .I3(\bank_common0/periodic_rd_cntr_r ), .I4(maint_wip_r), .I5(bank_mach0_n_109), .O(i___50_n_0)); LUT6 #( .INIT(64'hEAAAEAAAEAAAAAAA)) i___51 (.I0(\bank_cntrl[3].bank0/wait_for_maint_r ), .I1(idle_r[3]), .I2(head_r[3]), .I3(accept_internal_r), .I4(use_addr), .I5(periodic_rd_ack_r), .O(i___51_n_0)); LUT6 #( .INIT(64'h8080800000000000)) i___52 (.I0(idle_r[3]), .I1(head_r[3]), .I2(accept_internal_r), .I3(use_addr), .I4(periodic_rd_ack_r), .I5(req_wr_r[3]), .O(i___52_n_0)); LUT6 #( .INIT(64'h4444554544444444)) i___53 (.I0(i___63_n_0), .I1(\bank_common0/maint_hit_busies_r [3]), .I2(maint_req_r), .I3(\bank_common0/periodic_rd_cntr_r ), .I4(maint_wip_r), .I5(bank_mach0_n_111), .O(i___53_n_0)); LUT6 #( .INIT(64'hEAAAEAAAEAAAAAAA)) i___54 (.I0(\bank_cntrl[0].bank0/wait_for_maint_r ), .I1(idle_r[0]), .I2(head_r[0]), .I3(accept_internal_r), .I4(use_addr), .I5(periodic_rd_ack_r), .O(i___54_n_0)); LUT6 #( .INIT(64'h4444554544444444)) i___55 (.I0(i___60_n_0), .I1(\bank_common0/maint_hit_busies_r [0]), .I2(maint_req_r), .I3(\bank_common0/periodic_rd_cntr_r ), .I4(maint_wip_r), .I5(bank_mach0_n_106), .O(i___55_n_0)); LUT6 #( .INIT(64'h4444444444445455)) i___56 (.I0(\bank_cntrl[1].bank0/bank_state0/col_wait_r ), .I1(bank_mach0_n_156), .I2(bank_mach0_n_128), .I3(\bank_cntrl[1].bank0/rb_hit_busies_r ), .I4(bank_mach0_n_155), .I5(bank_mach0_n_160), .O(i___56_n_0)); LUT5 #( .INIT(32'h69969669)) i___57 (.I0(bank_mach0_n_116), .I1(idle_r[3]), .I2(idle_r[2]), .I3(idle_r[1]), .I4(idle_r[0]), .O(i___57_n_0)); LUT6 #( .INIT(64'h4454555544544454)) i___58 (.I0(i___60_n_0), .I1(\bank_cntrl[0].bank0/q_has_rd ), .I2(maint_req_r), .I3(idle_r[0]), .I4(was_wr), .I5(i___76_n_0), .O(i___58_n_0)); LUT6 #( .INIT(64'h2220202020202020)) i___59 (.I0(bank_mach0_n_116), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\bank_cntrl[0].bank0/q_has_priority ), .I3(app_hi_pri_r2), .I4(rb_hit_busy_r[0]), .I5(bank_mach0_n_136), .O(i___59_n_0)); LUT6 #( .INIT(64'hB888FFFFB8880000)) i___6 (.I0(bank_mach0_n_153), .I1(bank_mach0_n_108), .I2(bank_mach0_n_267), .I3(bank_mach0_n_116), .I4(bank_mach0_n_146), .I5(head_r[1]), .O(i___6_n_0)); LUT6 #( .INIT(64'hFFFFFFFFBFAAAAAA)) i___60 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(req_wr_r[0]), .I2(rd_wr_r[0]), .I3(act_wait_r_lcl_reg), .I4(sending_col[0]), .I5(\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ), .O(i___60_n_0)); LUT6 #( .INIT(64'h4454555544544454)) i___61 (.I0(i___63_n_0), .I1(\bank_cntrl[3].bank0/q_has_rd ), .I2(maint_req_r), .I3(idle_r[3]), .I4(was_wr), .I5(bank_mach0_n_159), .O(i___61_n_0)); LUT6 #( .INIT(64'h2220202020202020)) i___62 (.I0(bank_mach0_n_115), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\bank_cntrl[3].bank0/q_has_priority ), .I3(app_hi_pri_r2), .I4(bank_mach0_n_136), .I5(rb_hit_busy_r[3]), .O(i___62_n_0)); LUT6 #( .INIT(64'hFFFFFFFFBFAAAAAA)) i___63 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(req_wr_r[3]), .I2(rd_wr_r[3]), .I3(act_wait_r_lcl_reg_2), .I4(sending_col[3]), .I5(\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ), .O(i___63_n_0)); LUT6 #( .INIT(64'h4454555544544454)) i___64 (.I0(i___66_n_0), .I1(\bank_cntrl[2].bank0/q_has_rd ), .I2(maint_req_r), .I3(idle_r[2]), .I4(was_wr), .I5(bank_mach0_n_162), .O(i___64_n_0)); LUT6 #( .INIT(64'h2220202020202020)) i___65 (.I0(bank_mach0_n_113), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(\bank_cntrl[2].bank0/q_has_priority ), .I3(app_hi_pri_r2), .I4(bank_mach0_n_136), .I5(rb_hit_busy_r[2]), .O(i___65_n_0)); LUT6 #( .INIT(64'hFFFFFFFFBFAAAAAA)) i___66 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(req_wr_r[2]), .I2(rd_wr_r[2]), .I3(act_wait_r_lcl_reg_1), .I4(sending_col[2]), .I5(\bank_cntrl[2].bank0/bank_queue0/pre_bm_end_r ), .O(i___66_n_0)); (* SOFT_HLUTNM = "soft_lutpair1117" *) LUT3 #( .INIT(8'h78)) i___67 (.I0(periodic_rd_r), .I1(periodic_rd_ack_r), .I2(\rank_common0/periodic_rd_r_cnt ), .O(i___67_n_0)); (* SOFT_HLUTNM = "soft_lutpair1116" *) LUT3 #( .INIT(8'h78)) i___68 (.I0(periodic_rd_r), .I1(periodic_rd_ack_r), .I2(\bank_common0/periodic_rd_cntr_r ), .O(i___68_n_0)); (* SOFT_HLUTNM = "soft_lutpair1116" *) LUT4 #( .INIT(16'hBFAA)) i___69 (.I0(\app_cmd_r1_reg[0] ), .I1(periodic_rd_ack_r), .I2(\bank_common0/periodic_rd_cntr_r ), .I3(periodic_rd_r), .O(i___69_n_0)); LUT6 #( .INIT(64'h00000000AEAAEEEE)) i___7 (.I0(\bank_cntrl[1].bank0/auto_pre_r ), .I1(bank_mach0_n_265), .I2(\bank_cntrl[1].bank0/wait_for_maint_r ), .I3(bank_mach0_n_141), .I4(\bank_cntrl[1].bank0/row_hit_r ), .I5(i___43_n_0), .O(i___7_n_0)); (* SOFT_HLUTNM = "soft_lutpair1112" *) LUT5 #( .INIT(32'hEEEEEEE0)) i___70 (.I0(sent_row), .I1(insert_maint_r1), .I2(sending_row[1]), .I3(sending_row[2]), .I4(sending_row[3]), .O(i___70_n_0)); (* SOFT_HLUTNM = "soft_lutpair1112" *) LUT5 #( .INIT(32'hFFFFFFF1)) i___71 (.I0(sent_row), .I1(insert_maint_r1), .I2(sending_row[1]), .I3(sending_row[2]), .I4(sending_row[3]), .O(i___71_n_0)); LUT5 #( .INIT(32'h00F0F8F8)) i___72 (.I0(app_sr_req), .I1(init_calib_complete_reg_rep__6), .I2(\rank_common0/sre_request_r ), .I3(insert_maint_r1), .I4(maint_sre_r), .O(i___72_n_0)); LUT6 #( .INIT(64'h0000040000000000)) i___73 (.I0(bank_mach0_n_259), .I1(\bank_cntrl[2].bank0/bank_state0/ras_timer_zero_r ), .I2(idle_r[2]), .I3(row_cmd_wr[2]), .I4(\bank_cntrl[2].bank0/wait_for_maint_r ), .I5(head_r[2]), .O(i___73_n_0)); LUT6 #( .INIT(64'h0000040000000000)) i___74 (.I0(bank_mach0_n_275), .I1(\bank_cntrl[0].bank0/bank_state0/ras_timer_zero_r ), .I2(idle_r[0]), .I3(row_cmd_wr[0]), .I4(\bank_cntrl[0].bank0/wait_for_maint_r ), .I5(head_r[0]), .O(i___74_n_0)); (* SOFT_HLUTNM = "soft_lutpair1115" *) LUT4 #( .INIT(16'hF800)) i___75 (.I0(use_addr), .I1(bank_mach0_n_2), .I2(periodic_rd_ack_r), .I3(rb_hit_busy_r[1]), .O(i___75_n_0)); (* SOFT_HLUTNM = "soft_lutpair1115" *) LUT4 #( .INIT(16'hF800)) i___76 (.I0(use_addr), .I1(bank_mach0_n_2), .I2(periodic_rd_ack_r), .I3(rb_hit_busy_r[0]), .O(i___76_n_0)); LUT4 #( .INIT(16'hAAFB)) i___77 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(maint_req_r), .I2(\bank_common0/periodic_rd_cntr_r ), .I3(maint_wip_r), .O(i___77_n_0)); LUT4 #( .INIT(16'h0151)) i___78 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\arb_mux0/arb_row_col0/row_arb0/last_master_r ), .I2(sent_row), .I3(sending_row[3]), .O(i___78_n_0)); LUT4 #( .INIT(16'h0151)) i___79 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ), .I2(\arb_mux0/cs_en2 ), .I3(sending_pre[3]), .O(i___79_n_0)); LUT6 #( .INIT(64'h00000000EAEA0AEA)) i___8 (.I0(ordered_r[1]), .I1(bank_mach0_n_147), .I2(req_wr_r[1]), .I3(sending_col[1]), .I4(rd_wr_r[1]), .I5(rstdiv0_sync_r1_reg_rep__21), .O(i___8_n_0)); (* SOFT_HLUTNM = "soft_lutpair1117" *) LUT4 #( .INIT(16'hFF4C)) i___80 (.I0(periodic_rd_ack_r), .I1(periodic_rd_r), .I2(\rank_common0/periodic_rd_r_cnt ), .I3(rank_mach0_n_5), .O(i___80_n_0)); LUT3 #( .INIT(8'hBA)) i___81 (.I0(app_ref_req), .I1(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .I2(\rank_common0/app_ref_r ), .O(i___81_n_0)); LUT3 #( .INIT(8'hEA)) i___82 (.I0(app_zq_req), .I1(\rank_common0/app_zq_r ), .I2(\rank_common0/zq_request_r ), .O(i___82_n_0)); (* SOFT_HLUTNM = "soft_lutpair1114" *) LUT4 #( .INIT(16'h1441)) i___83 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\rank_cntrl[0].rank_cntrl0/act_delayed ), .I2(bank_mach0_n_278), .I3(faw_cnt_r[0]), .O(i___83_n_0)); (* SOFT_HLUTNM = "soft_lutpair1114" *) LUT5 #( .INIT(32'h44411444)) i___84 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(faw_cnt_r[1]), .I2(bank_mach0_n_278), .I3(\rank_cntrl[0].rank_cntrl0/act_delayed ), .I4(faw_cnt_r[0]), .O(i___84_n_0)); LUT6 #( .INIT(64'h5050501441505050)) i___85 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(faw_cnt_r[1]), .I2(faw_cnt_r[2]), .I3(\rank_cntrl[0].rank_cntrl0/act_delayed ), .I4(bank_mach0_n_278), .I5(faw_cnt_r[0]), .O(i___85_n_0)); LUT6 #( .INIT(64'h5554555455545454)) i___86 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(bank_mach0_n_281), .I2(bank_mach0_n_280), .I3(wtr_cnt_r[2]), .I4(wtr_cnt_r[1]), .I5(wtr_cnt_r[0]), .O(i___86_n_0)); LUT4 #( .INIT(16'hFFFE)) i___87 (.I0(\bank_common0/rfc_zq_xsdll_timer_r [3]), .I1(\bank_common0/rfc_zq_xsdll_timer_r [2]), .I2(\bank_common0/rfc_zq_xsdll_timer_r [0]), .I3(\bank_common0/rfc_zq_xsdll_timer_r [1]), .O(i___87_n_0)); LUT6 #( .INIT(64'h0000000044444544)) i___88 (.I0(\bank_cntrl[2].bank0/bank_state0/override_demand_r ), .I1(bank_mach0_n_283), .I2(\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ), .I3(\bank_cntrl[2].bank0/bank_state0/demand_priority_r ), .I4(sending_col[2]), .I5(\bank_cntrl[0].bank0/bank_state0/demand_priority_r ), .O(i___88_n_0)); LUT6 #( .INIT(64'h0000000055550010)) i___89 (.I0(\bank_cntrl[2].bank0/bank_state0/override_demand_r ), .I1(\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ), .I2(\bank_cntrl[0].bank0/bank_state0/demand_priority_r ), .I3(sending_col[0]), .I4(bank_mach0_n_283), .I5(\bank_cntrl[2].bank0/bank_state0/demand_priority_r ), .O(i___89_n_0)); LUT6 #( .INIT(64'hDDCCFFCFDDCCDDCC)) i___9 (.I0(bank_mach0_n_113), .I1(bank_mach0_n_132), .I2(idle_r[2]), .I3(i___45_n_0), .I4(bank_mach0_n_162), .I5(\bank_cntrl[2].bank0/tail_r ), .O(i___9_n_0)); LUT6 #( .INIT(64'h0000000055550010)) i___90 (.I0(\bank_cntrl[2].bank0/bank_state0/override_demand_r ), .I1(\bank_cntrl[3].bank0/bank_state0/demanded_prior_r ), .I2(\bank_cntrl[3].bank0/bank_state0/demand_priority_r ), .I3(sending_col[3]), .I4(bank_mach0_n_276), .I5(\bank_cntrl[1].bank0/bank_state0/demand_priority_r ), .O(i___90_n_0)); LUT3 #( .INIT(8'hEF)) i___91 (.I0(idle_r[3]), .I1(\bank_cntrl[3].bank0/q_entry_r [1]), .I2(\bank_cntrl[3].bank0/q_entry_r [0]), .O(i___91_n_0)); LUT3 #( .INIT(8'hEF)) i___92 (.I0(idle_r[2]), .I1(\bank_cntrl[2].bank0/q_entry_r [1]), .I2(\bank_cntrl[2].bank0/q_entry_r [0]), .O(i___92_n_0)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) i___93 (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [5]), .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]), .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]), .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]), .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]), .I5(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [4]), .O(i___93_n_0)); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) i___94 (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [5]), .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]), .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]), .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]), .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]), .I5(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [4]), .O(i___94_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___95 (.I0(Q[2]), .I1(sending_pre[0]), .I2(sending_pre[1]), .I3(\cmd_pipe_plus.mc_bank_reg[2]_0 [2]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___95_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___96 (.I0(Q[1]), .I1(sending_pre[0]), .I2(sending_pre[1]), .I3(\cmd_pipe_plus.mc_bank_reg[2]_0 [1]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___96_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___97 (.I0(Q[0]), .I1(sending_pre[0]), .I2(sending_pre[1]), .I3(\cmd_pipe_plus.mc_bank_reg[2]_0 [0]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___97_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___98 (.I0(sending_pre[0]), .I1(req_row_r[14]), .I2(sending_pre[1]), .I3(req_row_r[29]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___98_n_0)); LUT6 #( .INIT(64'h000000000000F808)) i___99 (.I0(sending_pre[0]), .I1(req_row_r[13]), .I2(sending_pre[1]), .I3(req_row_r[28]), .I4(sending_pre[3]), .I5(sending_pre[2]), .O(i___99_n_0)); FDRE mc_read_idle_r_reg (.C(CLK), .CE(1'b1), .D(col_mach0_n_16), .Q(idle), .R(maint_prescaler_r1)); FDRE mc_ref_zq_wip_r_reg (.C(CLK), .CE(1'b1), .D(mc_ref_zq_wip_ns), .Q(tempmon_sample_en), .R(1'b0)); LUT2 #( .INIT(4'hB)) mem_reg_0_15_0_5_i_2__0 (.I0(mc_cs_n), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0] [0])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_0_5_i_3__0 (.I0(mc_ras_n[2]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [3])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_12_17_i_2__4 (.I0(mc_cas_n[0]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [0])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_18_23_i_1__4 (.I0(mc_cas_n[2]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [1])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_24_29_i_2__4 (.I0(mc_ras_n[0]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0]_0 [2])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_30_35_i_1__5 (.I0(\my_full_reg[3] [14]), .I1(init_calib_complete_reg_rep__7), .O(phy_dout[0])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_30_35_i_2__5 (.I0(\my_full_reg[3] [37]), .I1(init_calib_complete_reg_rep__7), .O(phy_dout[1])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_6_11_i_2__4 (.I0(mc_we_n[0]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0] [1])); LUT2 #( .INIT(4'hB)) mem_reg_0_15_6_11_i_3__4 (.I0(mc_we_n[2]), .I1(init_calib_complete_reg_rep__7), .O(\rd_ptr_timing_reg[0] [2])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_2__0 (.I0(\my_full_reg[3] [13]), .I1(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7] [0])); LUT2 #( .INIT(4'h8)) mem_reg_0_15_72_77_i_3__0 (.I0(\my_full_reg[3] [36]), .I1(init_calib_complete_reg_rep__7), .O(\my_empty_reg[7] [1])); LUT2 #( .INIT(4'hB)) \pointer_ram.rams[0].RAM32M0_i_1 (.I0(E), .I1(ram_init_done_r), .O(pointer_we)); ddr3_if_mig_7series_v4_0_rank_mach rank_mach0 (.CLK(CLK), .D({i___27_n_0,i___26_n_0}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }), .Q(\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ), .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}), .SR(SR), .SS(i___20_n_0), .act_delayed(\rank_cntrl[0].rank_cntrl0/act_delayed ), .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ), .app_ref_ack(app_ref_ack), .app_ref_r(\rank_common0/app_ref_r ), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_r(\rank_common0/app_zq_r ), .app_zq_r_reg(i___82_n_0), .cke_r(\arb_mux0/arb_select0/cke_r ), .\grant_r_reg[0] (bank_mach0_n_100), .\grant_r_reg[2] (bank_mach0_n_278), .\grant_r_reg[3] (rank_mach0_n_71), .in0(in0), .\inhbt_act_faw.faw_cnt_r_reg[1] ({i___85_n_0,i___84_n_0,i___83_n_0}), .\inhbt_act_faw.inhbt_act_faw_r_reg (faw_cnt_r), .inhbt_act_faw_r(inhbt_act_faw_r), .init_calib_complete_reg_rep__6(i___72_n_0), .init_calib_complete_reg_rep__6_0(i___21_n_0), .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_2(i___22_n_0), .insert_maint_r(insert_maint_r), .insert_maint_r1(insert_maint_r1), .\last_master_r_reg[2] (\rank_common0/maintenance_request.maint_arb0/last_master_r ), .\last_master_r_reg[2]_0 (i___28_n_0), .\maint_controller.maint_wip_r_lcl_reg (i___29_n_0), .\maint_prescaler.maint_prescaler_r_reg[0] (i___119_n_0), .maint_prescaler_r1(maint_prescaler_r1), .maint_prescaler_tick_ns(\rank_common0/maint_prescaler_tick_ns ), .maint_ref_zq_wip(maint_ref_zq_wip), .maint_req_r(maint_req_r), .maint_sre_r(maint_sre_r), .maint_srx_r(maint_srx_r), .maint_zq_r(maint_zq_r), .\maintenance_request.maint_sre_r_lcl_reg (\rank_common0/maint_grant_r ), .\maintenance_request.maint_sre_r_lcl_reg_0 (i___18_n_0), .mc_cke_ns(mc_cke_ns), .new_maint_rank_r(\rank_common0/new_maint_rank_r ), .periodic_rd_ack_r_lcl_reg(i___80_n_0), .periodic_rd_cntr1_r(\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ), .\periodic_rd_generation.periodic_rd_request_r_reg (rank_mach0_n_64), .\periodic_rd_generation.periodic_rd_request_r_reg_0 (i___30_n_0), .\periodic_rd_generation.periodic_rd_request_r_reg_1 (i___17_n_0), .\periodic_rd_generation.read_this_rank_r_reg (bank_mach0_n_118), .periodic_rd_grant_r(\rank_common0/periodic_rd_grant_r ), .periodic_rd_r(periodic_rd_r), .periodic_rd_r_cnt(\rank_common0/periodic_rd_r_cnt ), .periodic_rd_request_r(\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ), .\periodic_read_request.periodic_rd_grant_r_reg[0] (i___31_n_0), .\periodic_read_request.periodic_rd_r_lcl_reg (i___67_n_0), .\periodic_read_request.upd_last_master_r_reg (rank_mach0_n_5), .read_this_rank(\rank_cntrl[0].rank_cntrl0/read_this_rank ), .read_this_rank_r(\rank_cntrl[0].rank_cntrl0/read_this_rank_r ), .refresh_bank_r(\rank_cntrl[0].rank_cntrl0/refresh_bank_r ), .\refresh_generation.refresh_bank_r_reg[0] (rank_mach0_n_43), .\refresh_generation.refresh_bank_r_reg[0]_0 (i___81_n_0), .\refresh_generation.refresh_bank_r_reg[0]_1 (i___19_n_0), .\refresh_timer.refresh_timer_r_reg[0] (i___120_n_0), .\refresh_timer.refresh_timer_r_reg[4] (\rank_common0/refresh_timer.refresh_timer_r_reg__0 ), .\refresh_timer.refresh_timer_r_reg[5] (rank_mach0_n_27), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\bank_common0/rfc_zq_xsdll_timer_ns ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\bank_common0/rfc_zq_xsdll_timer_r [0]), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (bank_mach0_n_282), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (rank_mach0_n_34), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (rank_mach0_n_42), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (rank_mach0_n_40), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\rtw_timer.rtw_cnt_r_reg[1] (rtw_cnt_r), .sre_request_r(\rank_common0/sre_request_r ), .upd_last_master_r(\rank_common0/upd_last_master_r ), .\wr_this_rank_r_reg[0] (bank_mach0_n_279), .\wr_this_rank_r_reg[0]_0 (bank_mach0_n_281), .\wr_this_rank_r_reg[0]_1 (bank_mach0_n_280), .\wtr_timer.wtr_cnt_r_reg[1] (wtr_cnt_r), .\wtr_timer.wtr_cnt_r_reg[2] (i___86_n_0), .\zq_cntrl.zq_request_logic.zq_request_r_reg (i___23_n_0), .\zq_cntrl.zq_timer.zq_timer_r_reg[0] (rank_mach0_n_30), .\zq_cntrl.zq_timer.zq_timer_r_reg[11] ({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}), .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }), .\zq_cntrl.zq_timer.zq_timer_r_reg[15] ({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}), .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }), .\zq_cntrl.zq_timer.zq_timer_r_reg[19] ({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63}), .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }), .\zq_cntrl.zq_timer.zq_timer_r_reg[7] ({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}), .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }), .zq_request_r(\rank_common0/zq_request_r )); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 (.CI(1'b0), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }), .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }), .S({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ), .CO({\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }), .S({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }), .S({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51})); CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ), .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }), .S({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55})); endmodule module ddr3_if_mig_7series_v4_0_mem_intfc (accept_ns, bm_end_r1, act_wait_r_lcl_reg, bm_end_r1_0, act_wait_r_lcl_reg_0, \ras_timer_r_reg[2] , act_wait_r_lcl_reg_1, bm_end_r1_4, act_wait_r_lcl_reg_2, app_ref_ack, app_zq_ack, E, app_sr_active, req_bank_r, ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , phy_dout, \samps_r_reg[9] , init_calib_complete_r_reg, \calib_seq_reg[0] , \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_en_stg2_f_timing_reg, dqs_po_en_stg2_f_reg, \rd_ptr_timing_reg[0] , \rd_ptr_timing_reg[0]_0 , \resume_wait_r_reg[5] , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, bypass__0, \not_strict_mode.app_rd_data_end_reg , rd_buf_we, rst_sync_r1_reg, \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , D, \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[254] , \not_strict_mode.app_rd_data_reg[238] , \not_strict_mode.app_rd_data_reg[246] , \not_strict_mode.app_rd_data_reg[230] , \not_strict_mode.app_rd_data_reg[253] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[252] , \not_strict_mode.app_rd_data_reg[236] , \not_strict_mode.app_rd_data_reg[244] , \not_strict_mode.app_rd_data_reg[228] , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[250] , \not_strict_mode.app_rd_data_reg[234] , \not_strict_mode.app_rd_data_reg[242] , \not_strict_mode.app_rd_data_reg[226] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[248] , \not_strict_mode.app_rd_data_reg[232] , \not_strict_mode.app_rd_data_reg[240] , \not_strict_mode.app_rd_data_reg[224] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[222] , \not_strict_mode.app_rd_data_reg[206] , \not_strict_mode.app_rd_data_reg[214] , \not_strict_mode.app_rd_data_reg[198] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[220] , \not_strict_mode.app_rd_data_reg[204] , \not_strict_mode.app_rd_data_reg[212] , \not_strict_mode.app_rd_data_reg[196] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[218] , \not_strict_mode.app_rd_data_reg[202] , \not_strict_mode.app_rd_data_reg[210] , \not_strict_mode.app_rd_data_reg[194] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[216] , \not_strict_mode.app_rd_data_reg[200] , \not_strict_mode.app_rd_data_reg[208] , \not_strict_mode.app_rd_data_reg[192] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[190] , \not_strict_mode.app_rd_data_reg[174] , \not_strict_mode.app_rd_data_reg[182] , \not_strict_mode.app_rd_data_reg[166] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[188] , \not_strict_mode.app_rd_data_reg[172] , \not_strict_mode.app_rd_data_reg[180] , \not_strict_mode.app_rd_data_reg[164] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[186] , \not_strict_mode.app_rd_data_reg[170] , \not_strict_mode.app_rd_data_reg[178] , \not_strict_mode.app_rd_data_reg[162] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[184] , \not_strict_mode.app_rd_data_reg[168] , \not_strict_mode.app_rd_data_reg[176] , \not_strict_mode.app_rd_data_reg[160] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[158] , \not_strict_mode.app_rd_data_reg[142] , \not_strict_mode.app_rd_data_reg[150] , \not_strict_mode.app_rd_data_reg[134] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[156] , \not_strict_mode.app_rd_data_reg[140] , \not_strict_mode.app_rd_data_reg[148] , \not_strict_mode.app_rd_data_reg[132] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[154] , \not_strict_mode.app_rd_data_reg[138] , \not_strict_mode.app_rd_data_reg[146] , \not_strict_mode.app_rd_data_reg[130] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[152] , \not_strict_mode.app_rd_data_reg[136] , \not_strict_mode.app_rd_data_reg[144] , \not_strict_mode.app_rd_data_reg[128] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[126] , \not_strict_mode.app_rd_data_reg[110] , \not_strict_mode.app_rd_data_reg[118] , \not_strict_mode.app_rd_data_reg[102] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[124] , \not_strict_mode.app_rd_data_reg[108] , \not_strict_mode.app_rd_data_reg[116] , \not_strict_mode.app_rd_data_reg[100] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[122] , \not_strict_mode.app_rd_data_reg[106] , \not_strict_mode.app_rd_data_reg[114] , \not_strict_mode.app_rd_data_reg[98] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[120] , \not_strict_mode.app_rd_data_reg[104] , \not_strict_mode.app_rd_data_reg[112] , \not_strict_mode.app_rd_data_reg[96] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[94] , \not_strict_mode.app_rd_data_reg[78] , \not_strict_mode.app_rd_data_reg[86] , \not_strict_mode.app_rd_data_reg[70] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[92] , \not_strict_mode.app_rd_data_reg[76] , \not_strict_mode.app_rd_data_reg[84] , \not_strict_mode.app_rd_data_reg[68] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[90] , \not_strict_mode.app_rd_data_reg[74] , \not_strict_mode.app_rd_data_reg[82] , \not_strict_mode.app_rd_data_reg[66] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[88] , \not_strict_mode.app_rd_data_reg[72] , \not_strict_mode.app_rd_data_reg[80] , \not_strict_mode.app_rd_data_reg[64] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[62] , \not_strict_mode.app_rd_data_reg[46] , \not_strict_mode.app_rd_data_reg[54] , \not_strict_mode.app_rd_data_reg[38] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[60] , \not_strict_mode.app_rd_data_reg[44] , \not_strict_mode.app_rd_data_reg[52] , \not_strict_mode.app_rd_data_reg[36] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[58] , \not_strict_mode.app_rd_data_reg[42] , \not_strict_mode.app_rd_data_reg[50] , \not_strict_mode.app_rd_data_reg[34] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[56] , \not_strict_mode.app_rd_data_reg[40] , \not_strict_mode.app_rd_data_reg[48] , \not_strict_mode.app_rd_data_reg[32] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[30] , \not_strict_mode.app_rd_data_reg[14] , \not_strict_mode.app_rd_data_reg[22] , \not_strict_mode.app_rd_data_reg[6] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[5] , \not_strict_mode.app_rd_data_reg[28] , \not_strict_mode.app_rd_data_reg[12] , \not_strict_mode.app_rd_data_reg[20] , \not_strict_mode.app_rd_data_reg[4] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[3] , \not_strict_mode.app_rd_data_reg[26] , \not_strict_mode.app_rd_data_reg[10] , \not_strict_mode.app_rd_data_reg[18] , \not_strict_mode.app_rd_data_reg[2] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[1] , \not_strict_mode.app_rd_data_reg[24] , \not_strict_mode.app_rd_data_reg[8] , \not_strict_mode.app_rd_data_reg[16] , \not_strict_mode.app_rd_data_reg[0] , \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , pointer_we, \not_strict_mode.app_rd_data_reg[255]_0 , app_rd_data_end_ns, \write_buffer.wr_buf_out_data_reg[287] , \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , \wr_ptr_timing_reg[2]_1 , wr_en, wr_en_5, wr_en_6, ddr_ck_out, \qcntr_r_reg[0] , ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, CLK, rstdiv0_sync_r1_reg_rep__0, hi_priority, SR, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, app_ref_req, app_zq_req, app_hi_pri_r2, use_addr, \app_cmd_r1_reg[0] , app_sr_req, rstdiv0_sync_r1_reg_rep__22, rstdiv0_sync_r1_reg_rep__23, mmcm_ps_clk, rst_sync_r1, poc_sample_pd, freq_refclk, mem_refclk, sync_pulse, pll_locked, in0, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__24, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__18, rstdiv0_sync_r1_reg_rep__16, SS, rstdiv0_sync_r1_reg_rep__7, Q, mem_out, \rd_ptr_reg[3] , rstdiv0_sync_r1_reg_rep__26, rstdiv0_sync_r1_reg_rep__26_0, rstdiv0_sync_r1_reg_rep__25, \sm_r_reg[0]_0 , \rd_ptr_reg[3]_0 , \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[0]_0 , \rd_buf_indx.rd_buf_indx_r_reg[4] , ram_init_done_r, sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, rstdiv0_sync_r1_reg_rep__26_1, rstdiv0_sync_r1_reg_rep__26_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , bm_end_r1_reg, bm_end_r1_reg_0, bm_end_r1_reg_1, pass_open_bank_r_lcl_reg, \app_cmd_r2_reg[1] , bm_end_r1_reg_2, rtp_timer_ns1, rtp_timer_ns1_6, rtp_timer_ns1_7, \app_addr_r1_reg[27] , DOC, DOB, DOA, \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 , \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 , \not_strict_mode.status_ram.rd_buf_we_r1_reg , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , \app_addr_r1_reg[12] , \app_addr_r1_reg[9] , psdone, rstdiv0_sync_r1_reg_rep__19, fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__24_0, p_81_in, rstdiv0_sync_r1_reg_rep__24_1, rstdiv0_sync_r1_reg_rep__17, po_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__6, \stg3_r_reg[0] , rstdiv0_sync_r1_reg_rep__8); output accept_ns; output bm_end_r1; output act_wait_r_lcl_reg; output bm_end_r1_0; output act_wait_r_lcl_reg_0; output \ras_timer_r_reg[2] ; output act_wait_r_lcl_reg_1; output bm_end_r1_4; output act_wait_r_lcl_reg_2; output app_ref_ack; output app_zq_ack; output [0:0]E; output app_sr_active; output [11:0]req_bank_r; output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [5:0]phy_dout; output \samps_r_reg[9] ; output init_calib_complete_r_reg; output \calib_seq_reg[0] ; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_en_stg2_f_timing_reg; output dqs_po_en_stg2_f_reg; output [37:0]\rd_ptr_timing_reg[0] ; output [4:0]\rd_ptr_timing_reg[0]_0 ; output [0:0]\resume_wait_r_reg[5] ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output bypass__0; output [6:0]\not_strict_mode.app_rd_data_end_reg ; output rd_buf_we; output rst_sync_r1_reg; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]D; output \not_strict_mode.app_rd_data_reg[255] ; output \not_strict_mode.app_rd_data_reg[239] ; output \not_strict_mode.app_rd_data_reg[247] ; output \not_strict_mode.app_rd_data_reg[231] ; output \not_strict_mode.app_rd_data_reg[254] ; output \not_strict_mode.app_rd_data_reg[238] ; output \not_strict_mode.app_rd_data_reg[246] ; output \not_strict_mode.app_rd_data_reg[230] ; output \not_strict_mode.app_rd_data_reg[253] ; output \not_strict_mode.app_rd_data_reg[237] ; output \not_strict_mode.app_rd_data_reg[245] ; output \not_strict_mode.app_rd_data_reg[229] ; output \not_strict_mode.app_rd_data_reg[252] ; output \not_strict_mode.app_rd_data_reg[236] ; output \not_strict_mode.app_rd_data_reg[244] ; output \not_strict_mode.app_rd_data_reg[228] ; output \not_strict_mode.app_rd_data_reg[251] ; output \not_strict_mode.app_rd_data_reg[235] ; output \not_strict_mode.app_rd_data_reg[243] ; output \not_strict_mode.app_rd_data_reg[227] ; output \not_strict_mode.app_rd_data_reg[250] ; output \not_strict_mode.app_rd_data_reg[234] ; output \not_strict_mode.app_rd_data_reg[242] ; output \not_strict_mode.app_rd_data_reg[226] ; output \not_strict_mode.app_rd_data_reg[249] ; output \not_strict_mode.app_rd_data_reg[233] ; output \not_strict_mode.app_rd_data_reg[241] ; output \not_strict_mode.app_rd_data_reg[225] ; output \not_strict_mode.app_rd_data_reg[248] ; output \not_strict_mode.app_rd_data_reg[232] ; output \not_strict_mode.app_rd_data_reg[240] ; output \not_strict_mode.app_rd_data_reg[224] ; output \not_strict_mode.app_rd_data_reg[223] ; output \not_strict_mode.app_rd_data_reg[207] ; output \not_strict_mode.app_rd_data_reg[215] ; output \not_strict_mode.app_rd_data_reg[199] ; output \not_strict_mode.app_rd_data_reg[222] ; output \not_strict_mode.app_rd_data_reg[206] ; output \not_strict_mode.app_rd_data_reg[214] ; output \not_strict_mode.app_rd_data_reg[198] ; output \not_strict_mode.app_rd_data_reg[221] ; output \not_strict_mode.app_rd_data_reg[205] ; output \not_strict_mode.app_rd_data_reg[213] ; output \not_strict_mode.app_rd_data_reg[197] ; output \not_strict_mode.app_rd_data_reg[220] ; output \not_strict_mode.app_rd_data_reg[204] ; output \not_strict_mode.app_rd_data_reg[212] ; output \not_strict_mode.app_rd_data_reg[196] ; output \not_strict_mode.app_rd_data_reg[219] ; output \not_strict_mode.app_rd_data_reg[203] ; output \not_strict_mode.app_rd_data_reg[211] ; output \not_strict_mode.app_rd_data_reg[195] ; output \not_strict_mode.app_rd_data_reg[218] ; output \not_strict_mode.app_rd_data_reg[202] ; output \not_strict_mode.app_rd_data_reg[210] ; output \not_strict_mode.app_rd_data_reg[194] ; output \not_strict_mode.app_rd_data_reg[217] ; output \not_strict_mode.app_rd_data_reg[201] ; output \not_strict_mode.app_rd_data_reg[209] ; output \not_strict_mode.app_rd_data_reg[193] ; output \not_strict_mode.app_rd_data_reg[216] ; output \not_strict_mode.app_rd_data_reg[200] ; output \not_strict_mode.app_rd_data_reg[208] ; output \not_strict_mode.app_rd_data_reg[192] ; output \not_strict_mode.app_rd_data_reg[191] ; output \not_strict_mode.app_rd_data_reg[175] ; output \not_strict_mode.app_rd_data_reg[183] ; output \not_strict_mode.app_rd_data_reg[167] ; output \not_strict_mode.app_rd_data_reg[190] ; output \not_strict_mode.app_rd_data_reg[174] ; output \not_strict_mode.app_rd_data_reg[182] ; output \not_strict_mode.app_rd_data_reg[166] ; output \not_strict_mode.app_rd_data_reg[189] ; output \not_strict_mode.app_rd_data_reg[173] ; output \not_strict_mode.app_rd_data_reg[181] ; output \not_strict_mode.app_rd_data_reg[165] ; output \not_strict_mode.app_rd_data_reg[188] ; output \not_strict_mode.app_rd_data_reg[172] ; output \not_strict_mode.app_rd_data_reg[180] ; output \not_strict_mode.app_rd_data_reg[164] ; output \not_strict_mode.app_rd_data_reg[187] ; output \not_strict_mode.app_rd_data_reg[171] ; output \not_strict_mode.app_rd_data_reg[179] ; output \not_strict_mode.app_rd_data_reg[163] ; output \not_strict_mode.app_rd_data_reg[186] ; output \not_strict_mode.app_rd_data_reg[170] ; output \not_strict_mode.app_rd_data_reg[178] ; output \not_strict_mode.app_rd_data_reg[162] ; output \not_strict_mode.app_rd_data_reg[185] ; output \not_strict_mode.app_rd_data_reg[169] ; output \not_strict_mode.app_rd_data_reg[177] ; output \not_strict_mode.app_rd_data_reg[161] ; output \not_strict_mode.app_rd_data_reg[184] ; output \not_strict_mode.app_rd_data_reg[168] ; output \not_strict_mode.app_rd_data_reg[176] ; output \not_strict_mode.app_rd_data_reg[160] ; output \not_strict_mode.app_rd_data_reg[159] ; output \not_strict_mode.app_rd_data_reg[143] ; output \not_strict_mode.app_rd_data_reg[151] ; output \not_strict_mode.app_rd_data_reg[135] ; output \not_strict_mode.app_rd_data_reg[158] ; output \not_strict_mode.app_rd_data_reg[142] ; output \not_strict_mode.app_rd_data_reg[150] ; output \not_strict_mode.app_rd_data_reg[134] ; output \not_strict_mode.app_rd_data_reg[157] ; output \not_strict_mode.app_rd_data_reg[141] ; output \not_strict_mode.app_rd_data_reg[149] ; output \not_strict_mode.app_rd_data_reg[133] ; output \not_strict_mode.app_rd_data_reg[156] ; output \not_strict_mode.app_rd_data_reg[140] ; output \not_strict_mode.app_rd_data_reg[148] ; output \not_strict_mode.app_rd_data_reg[132] ; output \not_strict_mode.app_rd_data_reg[155] ; output \not_strict_mode.app_rd_data_reg[139] ; output \not_strict_mode.app_rd_data_reg[147] ; output \not_strict_mode.app_rd_data_reg[131] ; output \not_strict_mode.app_rd_data_reg[154] ; output \not_strict_mode.app_rd_data_reg[138] ; output \not_strict_mode.app_rd_data_reg[146] ; output \not_strict_mode.app_rd_data_reg[130] ; output \not_strict_mode.app_rd_data_reg[153] ; output \not_strict_mode.app_rd_data_reg[137] ; output \not_strict_mode.app_rd_data_reg[145] ; output \not_strict_mode.app_rd_data_reg[129] ; output \not_strict_mode.app_rd_data_reg[152] ; output \not_strict_mode.app_rd_data_reg[136] ; output \not_strict_mode.app_rd_data_reg[144] ; output \not_strict_mode.app_rd_data_reg[128] ; output \not_strict_mode.app_rd_data_reg[127] ; output \not_strict_mode.app_rd_data_reg[111] ; output \not_strict_mode.app_rd_data_reg[119] ; output \not_strict_mode.app_rd_data_reg[103] ; output \not_strict_mode.app_rd_data_reg[126] ; output \not_strict_mode.app_rd_data_reg[110] ; output \not_strict_mode.app_rd_data_reg[118] ; output \not_strict_mode.app_rd_data_reg[102] ; output \not_strict_mode.app_rd_data_reg[125] ; output \not_strict_mode.app_rd_data_reg[109] ; output \not_strict_mode.app_rd_data_reg[117] ; output \not_strict_mode.app_rd_data_reg[101] ; output \not_strict_mode.app_rd_data_reg[124] ; output \not_strict_mode.app_rd_data_reg[108] ; output \not_strict_mode.app_rd_data_reg[116] ; output \not_strict_mode.app_rd_data_reg[100] ; output \not_strict_mode.app_rd_data_reg[123] ; output \not_strict_mode.app_rd_data_reg[107] ; output \not_strict_mode.app_rd_data_reg[115] ; output \not_strict_mode.app_rd_data_reg[99] ; output \not_strict_mode.app_rd_data_reg[122] ; output \not_strict_mode.app_rd_data_reg[106] ; output \not_strict_mode.app_rd_data_reg[114] ; output \not_strict_mode.app_rd_data_reg[98] ; output \not_strict_mode.app_rd_data_reg[121] ; output \not_strict_mode.app_rd_data_reg[105] ; output \not_strict_mode.app_rd_data_reg[113] ; output \not_strict_mode.app_rd_data_reg[97] ; output \not_strict_mode.app_rd_data_reg[120] ; output \not_strict_mode.app_rd_data_reg[104] ; output \not_strict_mode.app_rd_data_reg[112] ; output \not_strict_mode.app_rd_data_reg[96] ; output \not_strict_mode.app_rd_data_reg[95] ; output \not_strict_mode.app_rd_data_reg[79] ; output \not_strict_mode.app_rd_data_reg[87] ; output \not_strict_mode.app_rd_data_reg[71] ; output \not_strict_mode.app_rd_data_reg[94] ; output \not_strict_mode.app_rd_data_reg[78] ; output \not_strict_mode.app_rd_data_reg[86] ; output \not_strict_mode.app_rd_data_reg[70] ; output \not_strict_mode.app_rd_data_reg[93] ; output \not_strict_mode.app_rd_data_reg[77] ; output \not_strict_mode.app_rd_data_reg[85] ; output \not_strict_mode.app_rd_data_reg[69] ; output \not_strict_mode.app_rd_data_reg[92] ; output \not_strict_mode.app_rd_data_reg[76] ; output \not_strict_mode.app_rd_data_reg[84] ; output \not_strict_mode.app_rd_data_reg[68] ; output \not_strict_mode.app_rd_data_reg[91] ; output \not_strict_mode.app_rd_data_reg[75] ; output \not_strict_mode.app_rd_data_reg[83] ; output \not_strict_mode.app_rd_data_reg[67] ; output \not_strict_mode.app_rd_data_reg[90] ; output \not_strict_mode.app_rd_data_reg[74] ; output \not_strict_mode.app_rd_data_reg[82] ; output \not_strict_mode.app_rd_data_reg[66] ; output \not_strict_mode.app_rd_data_reg[89] ; output \not_strict_mode.app_rd_data_reg[73] ; output \not_strict_mode.app_rd_data_reg[81] ; output \not_strict_mode.app_rd_data_reg[65] ; output \not_strict_mode.app_rd_data_reg[88] ; output \not_strict_mode.app_rd_data_reg[72] ; output \not_strict_mode.app_rd_data_reg[80] ; output \not_strict_mode.app_rd_data_reg[64] ; output \not_strict_mode.app_rd_data_reg[63] ; output \not_strict_mode.app_rd_data_reg[47] ; output \not_strict_mode.app_rd_data_reg[55] ; output \not_strict_mode.app_rd_data_reg[39] ; output \not_strict_mode.app_rd_data_reg[62] ; output \not_strict_mode.app_rd_data_reg[46] ; output \not_strict_mode.app_rd_data_reg[54] ; output \not_strict_mode.app_rd_data_reg[38] ; output \not_strict_mode.app_rd_data_reg[61] ; output \not_strict_mode.app_rd_data_reg[45] ; output \not_strict_mode.app_rd_data_reg[53] ; output \not_strict_mode.app_rd_data_reg[37] ; output \not_strict_mode.app_rd_data_reg[60] ; output \not_strict_mode.app_rd_data_reg[44] ; output \not_strict_mode.app_rd_data_reg[52] ; output \not_strict_mode.app_rd_data_reg[36] ; output \not_strict_mode.app_rd_data_reg[59] ; output \not_strict_mode.app_rd_data_reg[43] ; output \not_strict_mode.app_rd_data_reg[51] ; output \not_strict_mode.app_rd_data_reg[35] ; output \not_strict_mode.app_rd_data_reg[58] ; output \not_strict_mode.app_rd_data_reg[42] ; output \not_strict_mode.app_rd_data_reg[50] ; output \not_strict_mode.app_rd_data_reg[34] ; output \not_strict_mode.app_rd_data_reg[57] ; output \not_strict_mode.app_rd_data_reg[41] ; output \not_strict_mode.app_rd_data_reg[49] ; output \not_strict_mode.app_rd_data_reg[33] ; output \not_strict_mode.app_rd_data_reg[56] ; output \not_strict_mode.app_rd_data_reg[40] ; output \not_strict_mode.app_rd_data_reg[48] ; output \not_strict_mode.app_rd_data_reg[32] ; output \not_strict_mode.app_rd_data_reg[31] ; output \not_strict_mode.app_rd_data_reg[15] ; output \not_strict_mode.app_rd_data_reg[23] ; output \not_strict_mode.app_rd_data_reg[7] ; output \not_strict_mode.app_rd_data_reg[30] ; output \not_strict_mode.app_rd_data_reg[14] ; output \not_strict_mode.app_rd_data_reg[22] ; output \not_strict_mode.app_rd_data_reg[6] ; output \not_strict_mode.app_rd_data_reg[29] ; output \not_strict_mode.app_rd_data_reg[13] ; output \not_strict_mode.app_rd_data_reg[21] ; output \not_strict_mode.app_rd_data_reg[5] ; output \not_strict_mode.app_rd_data_reg[28] ; output \not_strict_mode.app_rd_data_reg[12] ; output \not_strict_mode.app_rd_data_reg[20] ; output \not_strict_mode.app_rd_data_reg[4] ; output \not_strict_mode.app_rd_data_reg[27] ; output \not_strict_mode.app_rd_data_reg[11] ; output \not_strict_mode.app_rd_data_reg[19] ; output \not_strict_mode.app_rd_data_reg[3] ; output \not_strict_mode.app_rd_data_reg[26] ; output \not_strict_mode.app_rd_data_reg[10] ; output \not_strict_mode.app_rd_data_reg[18] ; output \not_strict_mode.app_rd_data_reg[2] ; output \not_strict_mode.app_rd_data_reg[25] ; output \not_strict_mode.app_rd_data_reg[9] ; output \not_strict_mode.app_rd_data_reg[17] ; output \not_strict_mode.app_rd_data_reg[1] ; output \not_strict_mode.app_rd_data_reg[24] ; output \not_strict_mode.app_rd_data_reg[8] ; output \not_strict_mode.app_rd_data_reg[16] ; output \not_strict_mode.app_rd_data_reg[0] ; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output pointer_we; output [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output app_rd_data_end_ns; output [3:0]\write_buffer.wr_buf_out_data_reg[287] ; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output [3:0]\wr_ptr_timing_reg[2]_1 ; output wr_en; output wr_en_5; output wr_en_6; output [1:0]ddr_ck_out; output [0:0]\qcntr_r_reg[0] ; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input CLK; input rstdiv0_sync_r1_reg_rep__0; input hi_priority; input [0:0]SR; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input app_ref_req; input app_zq_req; input app_hi_pri_r2; input use_addr; input \app_cmd_r1_reg[0] ; input app_sr_req; input rstdiv0_sync_r1_reg_rep__22; input rstdiv0_sync_r1_reg_rep__23; input mmcm_ps_clk; input rst_sync_r1; input poc_sample_pd; input freq_refclk; input mem_refclk; input sync_pulse; input pll_locked; input in0; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__24; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input [0:0]rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [0:0]rstdiv0_sync_r1_reg_rep__18; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input rstdiv0_sync_r1_reg_rep__7; input [287:0]Q; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input rstdiv0_sync_r1_reg_rep__26; input rstdiv0_sync_r1_reg_rep__26_0; input rstdiv0_sync_r1_reg_rep__25; input [0:0]\sm_r_reg[0]_0 ; input [29:0]\rd_ptr_reg[3]_0 ; input \req_bank_r_lcl_reg[2] ; input \req_bank_r_lcl_reg[2]_0 ; input \req_bank_r_lcl_reg[0] ; input \req_bank_r_lcl_reg[0]_0 ; input [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; input ram_init_done_r; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input rstdiv0_sync_r1_reg_rep__26_1; input rstdiv0_sync_r1_reg_rep__26_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input bm_end_r1_reg; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input pass_open_bank_r_lcl_reg; input [0:0]\app_cmd_r2_reg[1] ; input bm_end_r1_reg_2; input rtp_timer_ns1; input rtp_timer_ns1_6; input rtp_timer_ns1_7; input [14:0]\app_addr_r1_reg[27] ; input [1:0]DOC; input [1:0]DOB; input [1:0]DOA; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [2:0]\app_addr_r1_reg[12] ; input [6:0]\app_addr_r1_reg[9] ; input psdone; input [0:0]rstdiv0_sync_r1_reg_rep__19; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__24_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__24_1; input [0:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]po_cnt_dec_reg; input [0:0]rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__6; input \stg3_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__8; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [0:0]E; wire [287:0]Q; wire RST0; wire [0:0]SR; wire [0:0]SS; wire accept_ns; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire act_wait_r_lcl_reg_2; wire [2:0]\app_addr_r1_reg[12] ; wire [14:0]\app_addr_r1_reg[27] ; wire [6:0]\app_addr_r1_reg[9] ; wire \app_cmd_r1_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire app_hi_pri_r2; wire app_rd_data_end_ns; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_req; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_4; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire bypass__0; wire \calib_seq_reg[0] ; wire cnt_pwron_reset_done_r0; wire \col_mach0/p_0_in ; wire \complex_row_cnt_ocal_reg[0] ; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire ddr_phy_top0_n_359; wire ddr_phy_top0_n_360; wire ddr_phy_top0_n_361; wire ddr_phy_top0_n_362; wire ddr_phy_top0_n_363; wire ddr_phy_top0_n_364; wire ddr_phy_top0_n_365; wire ddr_phy_top0_n_366; wire ddr_phy_top0_n_367; wire ddr_phy_top0_n_368; wire ddr_phy_top0_n_369; wire ddr_phy_top0_n_370; wire ddr_phy_top0_n_371; wire ddr_phy_top0_n_372; wire ddr_phy_top0_n_373; wire ddr_phy_top0_n_374; wire ddr_phy_top0_n_375; wire ddr_phy_top0_n_376; wire ddr_phy_top0_n_377; wire ddr_phy_top0_n_378; wire ddr_phy_top0_n_379; wire ddr_phy_top0_n_380; wire ddr_phy_top0_n_381; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_50; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_51; wire ddr_phy_top0_n_641; wire ddr_phy_top0_n_642; wire ddr_phy_top0_n_97; wire [11:0]\device_temp_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire dqs_po_en_stg2_f_reg; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire fine_adjust_reg; wire freq_refclk; wire hi_priority; wire idle; wire in0; wire init_calib_complete_r_reg; wire mc0_n_117; wire mc0_n_118; wire mc0_n_119; wire mc0_n_120; wire mc0_n_121; wire mc0_n_122; wire mc0_n_123; wire mc0_n_124; wire mc0_n_125; wire mc0_n_126; wire mc0_n_127; wire mc0_n_128; wire [44:0]mc_address; wire [8:0]mc_bank; wire [2:0]mc_cas_n; wire [3:3]mc_cke; wire [1:0]mc_cmd; wire [0:0]mc_cs_n; wire [0:0]mc_odt; wire [2:0]mc_ras_n; wire [2:0]mc_we_n; wire mc_wrdata_en; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [43:13]mux_address; wire [6:0]\not_strict_mode.app_rd_data_end_reg ; wire \not_strict_mode.app_rd_data_reg[0] ; wire \not_strict_mode.app_rd_data_reg[100] ; wire \not_strict_mode.app_rd_data_reg[101] ; wire \not_strict_mode.app_rd_data_reg[102] ; wire \not_strict_mode.app_rd_data_reg[103] ; wire \not_strict_mode.app_rd_data_reg[104] ; wire \not_strict_mode.app_rd_data_reg[105] ; wire \not_strict_mode.app_rd_data_reg[106] ; wire \not_strict_mode.app_rd_data_reg[107] ; wire \not_strict_mode.app_rd_data_reg[108] ; wire \not_strict_mode.app_rd_data_reg[109] ; wire \not_strict_mode.app_rd_data_reg[10] ; wire \not_strict_mode.app_rd_data_reg[110] ; wire \not_strict_mode.app_rd_data_reg[111] ; wire \not_strict_mode.app_rd_data_reg[112] ; wire \not_strict_mode.app_rd_data_reg[113] ; wire \not_strict_mode.app_rd_data_reg[114] ; wire \not_strict_mode.app_rd_data_reg[115] ; wire \not_strict_mode.app_rd_data_reg[116] ; wire \not_strict_mode.app_rd_data_reg[117] ; wire \not_strict_mode.app_rd_data_reg[118] ; wire \not_strict_mode.app_rd_data_reg[119] ; wire \not_strict_mode.app_rd_data_reg[11] ; wire \not_strict_mode.app_rd_data_reg[120] ; wire \not_strict_mode.app_rd_data_reg[121] ; wire \not_strict_mode.app_rd_data_reg[122] ; wire \not_strict_mode.app_rd_data_reg[123] ; wire \not_strict_mode.app_rd_data_reg[124] ; wire \not_strict_mode.app_rd_data_reg[125] ; wire \not_strict_mode.app_rd_data_reg[126] ; wire \not_strict_mode.app_rd_data_reg[127] ; wire \not_strict_mode.app_rd_data_reg[128] ; wire \not_strict_mode.app_rd_data_reg[129] ; wire \not_strict_mode.app_rd_data_reg[12] ; wire \not_strict_mode.app_rd_data_reg[130] ; wire \not_strict_mode.app_rd_data_reg[131] ; wire \not_strict_mode.app_rd_data_reg[132] ; wire \not_strict_mode.app_rd_data_reg[133] ; wire \not_strict_mode.app_rd_data_reg[134] ; wire \not_strict_mode.app_rd_data_reg[135] ; wire \not_strict_mode.app_rd_data_reg[136] ; wire \not_strict_mode.app_rd_data_reg[137] ; wire \not_strict_mode.app_rd_data_reg[138] ; wire \not_strict_mode.app_rd_data_reg[139] ; wire \not_strict_mode.app_rd_data_reg[13] ; wire \not_strict_mode.app_rd_data_reg[140] ; wire \not_strict_mode.app_rd_data_reg[141] ; wire \not_strict_mode.app_rd_data_reg[142] ; wire \not_strict_mode.app_rd_data_reg[143] ; wire \not_strict_mode.app_rd_data_reg[144] ; wire \not_strict_mode.app_rd_data_reg[145] ; wire \not_strict_mode.app_rd_data_reg[146] ; wire \not_strict_mode.app_rd_data_reg[147] ; wire \not_strict_mode.app_rd_data_reg[148] ; wire \not_strict_mode.app_rd_data_reg[149] ; wire \not_strict_mode.app_rd_data_reg[14] ; wire \not_strict_mode.app_rd_data_reg[150] ; wire \not_strict_mode.app_rd_data_reg[151] ; wire \not_strict_mode.app_rd_data_reg[152] ; wire \not_strict_mode.app_rd_data_reg[153] ; wire \not_strict_mode.app_rd_data_reg[154] ; wire \not_strict_mode.app_rd_data_reg[155] ; wire \not_strict_mode.app_rd_data_reg[156] ; wire \not_strict_mode.app_rd_data_reg[157] ; wire \not_strict_mode.app_rd_data_reg[158] ; wire \not_strict_mode.app_rd_data_reg[159] ; wire \not_strict_mode.app_rd_data_reg[15] ; wire \not_strict_mode.app_rd_data_reg[160] ; wire \not_strict_mode.app_rd_data_reg[161] ; wire \not_strict_mode.app_rd_data_reg[162] ; wire \not_strict_mode.app_rd_data_reg[163] ; wire \not_strict_mode.app_rd_data_reg[164] ; wire \not_strict_mode.app_rd_data_reg[165] ; wire \not_strict_mode.app_rd_data_reg[166] ; wire \not_strict_mode.app_rd_data_reg[167] ; wire \not_strict_mode.app_rd_data_reg[168] ; wire \not_strict_mode.app_rd_data_reg[169] ; wire \not_strict_mode.app_rd_data_reg[16] ; wire \not_strict_mode.app_rd_data_reg[170] ; wire \not_strict_mode.app_rd_data_reg[171] ; wire \not_strict_mode.app_rd_data_reg[172] ; wire \not_strict_mode.app_rd_data_reg[173] ; wire \not_strict_mode.app_rd_data_reg[174] ; wire \not_strict_mode.app_rd_data_reg[175] ; wire \not_strict_mode.app_rd_data_reg[176] ; wire \not_strict_mode.app_rd_data_reg[177] ; wire \not_strict_mode.app_rd_data_reg[178] ; wire \not_strict_mode.app_rd_data_reg[179] ; wire \not_strict_mode.app_rd_data_reg[17] ; wire \not_strict_mode.app_rd_data_reg[180] ; wire \not_strict_mode.app_rd_data_reg[181] ; wire \not_strict_mode.app_rd_data_reg[182] ; wire \not_strict_mode.app_rd_data_reg[183] ; wire \not_strict_mode.app_rd_data_reg[184] ; wire \not_strict_mode.app_rd_data_reg[185] ; wire \not_strict_mode.app_rd_data_reg[186] ; wire \not_strict_mode.app_rd_data_reg[187] ; wire \not_strict_mode.app_rd_data_reg[188] ; wire \not_strict_mode.app_rd_data_reg[189] ; wire \not_strict_mode.app_rd_data_reg[18] ; wire \not_strict_mode.app_rd_data_reg[190] ; wire \not_strict_mode.app_rd_data_reg[191] ; wire \not_strict_mode.app_rd_data_reg[192] ; wire \not_strict_mode.app_rd_data_reg[193] ; wire \not_strict_mode.app_rd_data_reg[194] ; wire \not_strict_mode.app_rd_data_reg[195] ; wire \not_strict_mode.app_rd_data_reg[196] ; wire \not_strict_mode.app_rd_data_reg[197] ; wire \not_strict_mode.app_rd_data_reg[198] ; wire \not_strict_mode.app_rd_data_reg[199] ; wire \not_strict_mode.app_rd_data_reg[19] ; wire \not_strict_mode.app_rd_data_reg[1] ; wire \not_strict_mode.app_rd_data_reg[200] ; wire \not_strict_mode.app_rd_data_reg[201] ; wire \not_strict_mode.app_rd_data_reg[202] ; wire \not_strict_mode.app_rd_data_reg[203] ; wire \not_strict_mode.app_rd_data_reg[204] ; wire \not_strict_mode.app_rd_data_reg[205] ; wire \not_strict_mode.app_rd_data_reg[206] ; wire \not_strict_mode.app_rd_data_reg[207] ; wire \not_strict_mode.app_rd_data_reg[208] ; wire \not_strict_mode.app_rd_data_reg[209] ; wire \not_strict_mode.app_rd_data_reg[20] ; wire \not_strict_mode.app_rd_data_reg[210] ; wire \not_strict_mode.app_rd_data_reg[211] ; wire \not_strict_mode.app_rd_data_reg[212] ; wire \not_strict_mode.app_rd_data_reg[213] ; wire \not_strict_mode.app_rd_data_reg[214] ; wire \not_strict_mode.app_rd_data_reg[215] ; wire \not_strict_mode.app_rd_data_reg[216] ; wire \not_strict_mode.app_rd_data_reg[217] ; wire \not_strict_mode.app_rd_data_reg[218] ; wire \not_strict_mode.app_rd_data_reg[219] ; wire \not_strict_mode.app_rd_data_reg[21] ; wire \not_strict_mode.app_rd_data_reg[220] ; wire \not_strict_mode.app_rd_data_reg[221] ; wire \not_strict_mode.app_rd_data_reg[222] ; wire \not_strict_mode.app_rd_data_reg[223] ; wire \not_strict_mode.app_rd_data_reg[224] ; wire \not_strict_mode.app_rd_data_reg[225] ; wire \not_strict_mode.app_rd_data_reg[226] ; wire \not_strict_mode.app_rd_data_reg[227] ; wire \not_strict_mode.app_rd_data_reg[228] ; wire \not_strict_mode.app_rd_data_reg[229] ; wire \not_strict_mode.app_rd_data_reg[22] ; wire \not_strict_mode.app_rd_data_reg[230] ; wire \not_strict_mode.app_rd_data_reg[231] ; wire \not_strict_mode.app_rd_data_reg[232] ; wire \not_strict_mode.app_rd_data_reg[233] ; wire \not_strict_mode.app_rd_data_reg[234] ; wire \not_strict_mode.app_rd_data_reg[235] ; wire \not_strict_mode.app_rd_data_reg[236] ; wire \not_strict_mode.app_rd_data_reg[237] ; wire \not_strict_mode.app_rd_data_reg[238] ; wire \not_strict_mode.app_rd_data_reg[239] ; wire \not_strict_mode.app_rd_data_reg[23] ; wire \not_strict_mode.app_rd_data_reg[240] ; wire \not_strict_mode.app_rd_data_reg[241] ; wire \not_strict_mode.app_rd_data_reg[242] ; wire \not_strict_mode.app_rd_data_reg[243] ; wire \not_strict_mode.app_rd_data_reg[244] ; wire \not_strict_mode.app_rd_data_reg[245] ; wire \not_strict_mode.app_rd_data_reg[246] ; wire \not_strict_mode.app_rd_data_reg[247] ; wire \not_strict_mode.app_rd_data_reg[248] ; wire \not_strict_mode.app_rd_data_reg[249] ; wire \not_strict_mode.app_rd_data_reg[24] ; wire \not_strict_mode.app_rd_data_reg[250] ; wire \not_strict_mode.app_rd_data_reg[251] ; wire \not_strict_mode.app_rd_data_reg[252] ; wire \not_strict_mode.app_rd_data_reg[253] ; wire \not_strict_mode.app_rd_data_reg[254] ; wire \not_strict_mode.app_rd_data_reg[255] ; wire [255:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire \not_strict_mode.app_rd_data_reg[25] ; wire \not_strict_mode.app_rd_data_reg[26] ; wire \not_strict_mode.app_rd_data_reg[27] ; wire \not_strict_mode.app_rd_data_reg[28] ; wire \not_strict_mode.app_rd_data_reg[29] ; wire \not_strict_mode.app_rd_data_reg[2] ; wire \not_strict_mode.app_rd_data_reg[30] ; wire \not_strict_mode.app_rd_data_reg[31] ; wire \not_strict_mode.app_rd_data_reg[32] ; wire \not_strict_mode.app_rd_data_reg[33] ; wire \not_strict_mode.app_rd_data_reg[34] ; wire \not_strict_mode.app_rd_data_reg[35] ; wire \not_strict_mode.app_rd_data_reg[36] ; wire \not_strict_mode.app_rd_data_reg[37] ; wire \not_strict_mode.app_rd_data_reg[38] ; wire \not_strict_mode.app_rd_data_reg[39] ; wire \not_strict_mode.app_rd_data_reg[3] ; wire \not_strict_mode.app_rd_data_reg[40] ; wire \not_strict_mode.app_rd_data_reg[41] ; wire \not_strict_mode.app_rd_data_reg[42] ; wire \not_strict_mode.app_rd_data_reg[43] ; wire \not_strict_mode.app_rd_data_reg[44] ; wire \not_strict_mode.app_rd_data_reg[45] ; wire \not_strict_mode.app_rd_data_reg[46] ; wire \not_strict_mode.app_rd_data_reg[47] ; wire \not_strict_mode.app_rd_data_reg[48] ; wire \not_strict_mode.app_rd_data_reg[49] ; wire \not_strict_mode.app_rd_data_reg[4] ; wire \not_strict_mode.app_rd_data_reg[50] ; wire \not_strict_mode.app_rd_data_reg[51] ; wire \not_strict_mode.app_rd_data_reg[52] ; wire \not_strict_mode.app_rd_data_reg[53] ; wire \not_strict_mode.app_rd_data_reg[54] ; wire \not_strict_mode.app_rd_data_reg[55] ; wire \not_strict_mode.app_rd_data_reg[56] ; wire \not_strict_mode.app_rd_data_reg[57] ; wire \not_strict_mode.app_rd_data_reg[58] ; wire \not_strict_mode.app_rd_data_reg[59] ; wire \not_strict_mode.app_rd_data_reg[5] ; wire \not_strict_mode.app_rd_data_reg[60] ; wire \not_strict_mode.app_rd_data_reg[61] ; wire \not_strict_mode.app_rd_data_reg[62] ; wire \not_strict_mode.app_rd_data_reg[63] ; wire \not_strict_mode.app_rd_data_reg[64] ; wire \not_strict_mode.app_rd_data_reg[65] ; wire \not_strict_mode.app_rd_data_reg[66] ; wire \not_strict_mode.app_rd_data_reg[67] ; wire \not_strict_mode.app_rd_data_reg[68] ; wire \not_strict_mode.app_rd_data_reg[69] ; wire \not_strict_mode.app_rd_data_reg[6] ; wire \not_strict_mode.app_rd_data_reg[70] ; wire \not_strict_mode.app_rd_data_reg[71] ; wire \not_strict_mode.app_rd_data_reg[72] ; wire \not_strict_mode.app_rd_data_reg[73] ; wire \not_strict_mode.app_rd_data_reg[74] ; wire \not_strict_mode.app_rd_data_reg[75] ; wire \not_strict_mode.app_rd_data_reg[76] ; wire \not_strict_mode.app_rd_data_reg[77] ; wire \not_strict_mode.app_rd_data_reg[78] ; wire \not_strict_mode.app_rd_data_reg[79] ; wire \not_strict_mode.app_rd_data_reg[7] ; wire \not_strict_mode.app_rd_data_reg[80] ; wire \not_strict_mode.app_rd_data_reg[81] ; wire \not_strict_mode.app_rd_data_reg[82] ; wire \not_strict_mode.app_rd_data_reg[83] ; wire \not_strict_mode.app_rd_data_reg[84] ; wire \not_strict_mode.app_rd_data_reg[85] ; wire \not_strict_mode.app_rd_data_reg[86] ; wire \not_strict_mode.app_rd_data_reg[87] ; wire \not_strict_mode.app_rd_data_reg[88] ; wire \not_strict_mode.app_rd_data_reg[89] ; wire \not_strict_mode.app_rd_data_reg[8] ; wire \not_strict_mode.app_rd_data_reg[90] ; wire \not_strict_mode.app_rd_data_reg[91] ; wire \not_strict_mode.app_rd_data_reg[92] ; wire \not_strict_mode.app_rd_data_reg[93] ; wire \not_strict_mode.app_rd_data_reg[94] ; wire \not_strict_mode.app_rd_data_reg[95] ; wire \not_strict_mode.app_rd_data_reg[96] ; wire \not_strict_mode.app_rd_data_reg[97] ; wire \not_strict_mode.app_rd_data_reg[98] ; wire \not_strict_mode.app_rd_data_reg[99] ; wire \not_strict_mode.app_rd_data_reg[9] ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ; wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ; wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ; wire p_81_in; wire pass_open_bank_r_lcl_reg; wire [5:0]phy_dout; wire phy_mc_ctl_full; wire [0:0]pi_cnt_dec_reg; wire pi_en_stg2_f_timing_reg; wire \pi_rst_stg1_cal_r_reg[0] ; wire pll_locked; wire [0:0]po_cnt_dec_reg; wire poc_sample_pd; wire pointer_we; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire ram_init_done_r; wire \rank_mach0/rank_common0/maint_prescaler_r1 ; wire \ras_timer_r_reg[2] ; wire [4:0]\rd_buf_indx.rd_buf_indx_r_reg[4] ; wire rd_buf_we; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [37:0]\rd_ptr_timing_reg[0] ; wire [4:0]\rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire [11:0]req_bank_r; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[0]_0 ; wire \req_bank_r_lcl_reg[2] ; wire \req_bank_r_lcl_reg[2]_0 ; wire [0:0]\resume_wait_r_reg[5] ; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [0:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__24_0; wire rstdiv0_sync_r1_reg_rep__24_1; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__26_1; wire rstdiv0_sync_r1_reg_rep__26_2; wire rstdiv0_sync_r1_reg_rep__4; wire [0:0]rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire rtp_timer_ns1; wire rtp_timer_ns1_6; wire rtp_timer_ns1_7; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire \samps_r_reg[9] ; wire sent_col; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_rst; wire [0:0]tail_r; wire tempmon_sample_en; wire [1:1]\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ; wire use_addr; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; wire [3:0]\wr_ptr_timing_reg[2]_1 ; wire [3:0]\write_buffer.wr_buf_out_data_reg[287] ; ddr3_if_mig_7series_v4_0_ddr_phy_top ddr_phy_top0 (.CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .D(D), .DOA(DOA), .DOB(DOB), .DOC(DOC), .Q(Q), .RST0(RST0), .SR(SR), .SS(SS), .app_zq_r_reg(ddr_phy_top0_n_50), .\calib_seq_reg[0] (\calib_seq_reg[0] ), .\cmd_pipe_plus.mc_address_reg[43] ({mux_address[43],mux_address[13]}), .\cmd_pipe_plus.mc_address_reg[44] ({mc_address[44:30],mc_address[25:18],mc_address[14:0]}), .\cmd_pipe_plus.mc_bank_reg[8] (mc_bank), .\cmd_pipe_plus.mc_data_offset_1_reg[0] (ddr_phy_top0_n_381), .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (mc0_n_126), .\cmd_pipe_plus.mc_data_offset_1_reg[1] (ddr_phy_top0_n_378), .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (mc0_n_125), .\cmd_pipe_plus.mc_data_offset_1_reg[2] (ddr_phy_top0_n_377), .\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (mc0_n_128), .\cmd_pipe_plus.mc_data_offset_1_reg[3] (ddr_phy_top0_n_369), .\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (mc0_n_127), .\cmd_pipe_plus.mc_data_offset_1_reg[4] (ddr_phy_top0_n_376), .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (mc0_n_124), .\cmd_pipe_plus.mc_data_offset_1_reg[5] ({ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373,ddr_phy_top0_n_374,ddr_phy_top0_n_375}), .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (mc0_n_123), .\cmd_pipe_plus.mc_data_offset_reg[0] (ddr_phy_top0_n_380), .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_120), .\cmd_pipe_plus.mc_data_offset_reg[1] (ddr_phy_top0_n_368), .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_119), .\cmd_pipe_plus.mc_data_offset_reg[2] (ddr_phy_top0_n_367), .\cmd_pipe_plus.mc_data_offset_reg[2]_0 (mc0_n_122), .\cmd_pipe_plus.mc_data_offset_reg[3] (ddr_phy_top0_n_359), .\cmd_pipe_plus.mc_data_offset_reg[3]_0 (mc0_n_121), .\cmd_pipe_plus.mc_data_offset_reg[4] (ddr_phy_top0_n_366), .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_118), .\cmd_pipe_plus.mc_data_offset_reg[5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}), .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_117), .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0), .\complex_row_cnt_ocal_reg[0] (\complex_row_cnt_ocal_reg[0] ), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .fine_adjust_reg(fine_adjust_reg), .freq_refclk(freq_refclk), .idle(idle), .in0(in0), .init_calib_complete_r_reg(init_calib_complete_r_reg), .maint_prescaler_r1(\rank_mach0/rank_common0/maint_prescaler_r1 ), .mc_cas_n(mc_cas_n), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_cs_n(mc_cs_n), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n), .mc_we_n(mc_we_n), .mc_wrdata_en(mc_wrdata_en), .mem_out(mem_out), .mem_refclk(mem_refclk), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .\my_empty_reg[7] (ddr_phy_top0_n_51), .\not_strict_mode.app_rd_data_reg[0] (\not_strict_mode.app_rd_data_reg[0] ), .\not_strict_mode.app_rd_data_reg[100] (\not_strict_mode.app_rd_data_reg[100] ), .\not_strict_mode.app_rd_data_reg[101] (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[102] (\not_strict_mode.app_rd_data_reg[102] ), .\not_strict_mode.app_rd_data_reg[103] (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[104] (\not_strict_mode.app_rd_data_reg[104] ), .\not_strict_mode.app_rd_data_reg[105] (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[106] (\not_strict_mode.app_rd_data_reg[106] ), .\not_strict_mode.app_rd_data_reg[107] (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[108] (\not_strict_mode.app_rd_data_reg[108] ), .\not_strict_mode.app_rd_data_reg[109] (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[10] (\not_strict_mode.app_rd_data_reg[10] ), .\not_strict_mode.app_rd_data_reg[110] (\not_strict_mode.app_rd_data_reg[110] ), .\not_strict_mode.app_rd_data_reg[111] (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[112] (\not_strict_mode.app_rd_data_reg[112] ), .\not_strict_mode.app_rd_data_reg[113] (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[114] (\not_strict_mode.app_rd_data_reg[114] ), .\not_strict_mode.app_rd_data_reg[115] (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[116] (\not_strict_mode.app_rd_data_reg[116] ), .\not_strict_mode.app_rd_data_reg[117] (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[118] (\not_strict_mode.app_rd_data_reg[118] ), .\not_strict_mode.app_rd_data_reg[119] (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11] (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[120] (\not_strict_mode.app_rd_data_reg[120] ), .\not_strict_mode.app_rd_data_reg[121] (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[122] (\not_strict_mode.app_rd_data_reg[122] ), .\not_strict_mode.app_rd_data_reg[123] (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[124] (\not_strict_mode.app_rd_data_reg[124] ), .\not_strict_mode.app_rd_data_reg[125] (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[126] (\not_strict_mode.app_rd_data_reg[126] ), .\not_strict_mode.app_rd_data_reg[127] (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[128] (\not_strict_mode.app_rd_data_reg[128] ), .\not_strict_mode.app_rd_data_reg[129] (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[12] (\not_strict_mode.app_rd_data_reg[12] ), .\not_strict_mode.app_rd_data_reg[130] (\not_strict_mode.app_rd_data_reg[130] ), .\not_strict_mode.app_rd_data_reg[131] (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[132] (\not_strict_mode.app_rd_data_reg[132] ), .\not_strict_mode.app_rd_data_reg[133] (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[134] (\not_strict_mode.app_rd_data_reg[134] ), .\not_strict_mode.app_rd_data_reg[135] (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[136] (\not_strict_mode.app_rd_data_reg[136] ), .\not_strict_mode.app_rd_data_reg[137] (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[138] (\not_strict_mode.app_rd_data_reg[138] ), .\not_strict_mode.app_rd_data_reg[139] (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13] (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[140] (\not_strict_mode.app_rd_data_reg[140] ), .\not_strict_mode.app_rd_data_reg[141] (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[142] (\not_strict_mode.app_rd_data_reg[142] ), .\not_strict_mode.app_rd_data_reg[143] (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[144] (\not_strict_mode.app_rd_data_reg[144] ), .\not_strict_mode.app_rd_data_reg[145] (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[146] (\not_strict_mode.app_rd_data_reg[146] ), .\not_strict_mode.app_rd_data_reg[147] (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[148] (\not_strict_mode.app_rd_data_reg[148] ), .\not_strict_mode.app_rd_data_reg[149] (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[14] (\not_strict_mode.app_rd_data_reg[14] ), .\not_strict_mode.app_rd_data_reg[150] (\not_strict_mode.app_rd_data_reg[150] ), .\not_strict_mode.app_rd_data_reg[151] (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[152] (\not_strict_mode.app_rd_data_reg[152] ), .\not_strict_mode.app_rd_data_reg[153] (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[154] (\not_strict_mode.app_rd_data_reg[154] ), .\not_strict_mode.app_rd_data_reg[155] (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[156] (\not_strict_mode.app_rd_data_reg[156] ), .\not_strict_mode.app_rd_data_reg[157] (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[158] (\not_strict_mode.app_rd_data_reg[158] ), .\not_strict_mode.app_rd_data_reg[159] (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15] (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[160] (\not_strict_mode.app_rd_data_reg[160] ), .\not_strict_mode.app_rd_data_reg[161] (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[162] (\not_strict_mode.app_rd_data_reg[162] ), .\not_strict_mode.app_rd_data_reg[163] (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[164] (\not_strict_mode.app_rd_data_reg[164] ), .\not_strict_mode.app_rd_data_reg[165] (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[166] (\not_strict_mode.app_rd_data_reg[166] ), .\not_strict_mode.app_rd_data_reg[167] (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[168] (\not_strict_mode.app_rd_data_reg[168] ), .\not_strict_mode.app_rd_data_reg[169] (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[16] (\not_strict_mode.app_rd_data_reg[16] ), .\not_strict_mode.app_rd_data_reg[170] (\not_strict_mode.app_rd_data_reg[170] ), .\not_strict_mode.app_rd_data_reg[171] (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[172] (\not_strict_mode.app_rd_data_reg[172] ), .\not_strict_mode.app_rd_data_reg[173] (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[174] (\not_strict_mode.app_rd_data_reg[174] ), .\not_strict_mode.app_rd_data_reg[175] (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[176] (\not_strict_mode.app_rd_data_reg[176] ), .\not_strict_mode.app_rd_data_reg[177] (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[178] (\not_strict_mode.app_rd_data_reg[178] ), .\not_strict_mode.app_rd_data_reg[179] (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17] (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[180] (\not_strict_mode.app_rd_data_reg[180] ), .\not_strict_mode.app_rd_data_reg[181] (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[182] (\not_strict_mode.app_rd_data_reg[182] ), .\not_strict_mode.app_rd_data_reg[183] (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[184] (\not_strict_mode.app_rd_data_reg[184] ), .\not_strict_mode.app_rd_data_reg[185] (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[186] (\not_strict_mode.app_rd_data_reg[186] ), .\not_strict_mode.app_rd_data_reg[187] (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[188] (\not_strict_mode.app_rd_data_reg[188] ), .\not_strict_mode.app_rd_data_reg[189] (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[18] (\not_strict_mode.app_rd_data_reg[18] ), .\not_strict_mode.app_rd_data_reg[190] (\not_strict_mode.app_rd_data_reg[190] ), .\not_strict_mode.app_rd_data_reg[191] (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[192] (\not_strict_mode.app_rd_data_reg[192] ), .\not_strict_mode.app_rd_data_reg[193] (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[194] (\not_strict_mode.app_rd_data_reg[194] ), .\not_strict_mode.app_rd_data_reg[195] (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[196] (\not_strict_mode.app_rd_data_reg[196] ), .\not_strict_mode.app_rd_data_reg[197] (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[198] (\not_strict_mode.app_rd_data_reg[198] ), .\not_strict_mode.app_rd_data_reg[199] (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[19] (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[1] (\not_strict_mode.app_rd_data_reg[1] ), .\not_strict_mode.app_rd_data_reg[200] (\not_strict_mode.app_rd_data_reg[200] ), .\not_strict_mode.app_rd_data_reg[201] (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[202] (\not_strict_mode.app_rd_data_reg[202] ), .\not_strict_mode.app_rd_data_reg[203] (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[204] (\not_strict_mode.app_rd_data_reg[204] ), .\not_strict_mode.app_rd_data_reg[205] (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[206] (\not_strict_mode.app_rd_data_reg[206] ), .\not_strict_mode.app_rd_data_reg[207] (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[208] (\not_strict_mode.app_rd_data_reg[208] ), .\not_strict_mode.app_rd_data_reg[209] (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[20] (\not_strict_mode.app_rd_data_reg[20] ), .\not_strict_mode.app_rd_data_reg[210] (\not_strict_mode.app_rd_data_reg[210] ), .\not_strict_mode.app_rd_data_reg[211] (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[212] (\not_strict_mode.app_rd_data_reg[212] ), .\not_strict_mode.app_rd_data_reg[213] (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[214] (\not_strict_mode.app_rd_data_reg[214] ), .\not_strict_mode.app_rd_data_reg[215] (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[216] (\not_strict_mode.app_rd_data_reg[216] ), .\not_strict_mode.app_rd_data_reg[217] (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[218] (\not_strict_mode.app_rd_data_reg[218] ), .\not_strict_mode.app_rd_data_reg[219] (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[21] (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[220] (\not_strict_mode.app_rd_data_reg[220] ), .\not_strict_mode.app_rd_data_reg[221] (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[222] (\not_strict_mode.app_rd_data_reg[222] ), .\not_strict_mode.app_rd_data_reg[223] (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[224] (\not_strict_mode.app_rd_data_reg[224] ), .\not_strict_mode.app_rd_data_reg[225] (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[226] (\not_strict_mode.app_rd_data_reg[226] ), .\not_strict_mode.app_rd_data_reg[227] (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[228] (\not_strict_mode.app_rd_data_reg[228] ), .\not_strict_mode.app_rd_data_reg[229] (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[22] (\not_strict_mode.app_rd_data_reg[22] ), .\not_strict_mode.app_rd_data_reg[230] (\not_strict_mode.app_rd_data_reg[230] ), .\not_strict_mode.app_rd_data_reg[231] (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ), .\not_strict_mode.app_rd_data_reg[233] (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[234] (\not_strict_mode.app_rd_data_reg[234] ), .\not_strict_mode.app_rd_data_reg[235] (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[236] (\not_strict_mode.app_rd_data_reg[236] ), .\not_strict_mode.app_rd_data_reg[237] (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[238] (\not_strict_mode.app_rd_data_reg[238] ), .\not_strict_mode.app_rd_data_reg[239] (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[23] (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[240] (\not_strict_mode.app_rd_data_reg[240] ), .\not_strict_mode.app_rd_data_reg[241] (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[242] (\not_strict_mode.app_rd_data_reg[242] ), .\not_strict_mode.app_rd_data_reg[243] (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[244] (\not_strict_mode.app_rd_data_reg[244] ), .\not_strict_mode.app_rd_data_reg[245] (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[246] (\not_strict_mode.app_rd_data_reg[246] ), .\not_strict_mode.app_rd_data_reg[247] (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[248] (\not_strict_mode.app_rd_data_reg[248] ), .\not_strict_mode.app_rd_data_reg[249] (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ), .\not_strict_mode.app_rd_data_reg[250] (\not_strict_mode.app_rd_data_reg[250] ), .\not_strict_mode.app_rd_data_reg[251] (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[252] (\not_strict_mode.app_rd_data_reg[252] ), .\not_strict_mode.app_rd_data_reg[253] (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[254] (\not_strict_mode.app_rd_data_reg[254] ), .\not_strict_mode.app_rd_data_reg[255] (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255]_0 ), .\not_strict_mode.app_rd_data_reg[25] (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[26] (\not_strict_mode.app_rd_data_reg[26] ), .\not_strict_mode.app_rd_data_reg[27] (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[28] (\not_strict_mode.app_rd_data_reg[28] ), .\not_strict_mode.app_rd_data_reg[29] (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[2] (\not_strict_mode.app_rd_data_reg[2] ), .\not_strict_mode.app_rd_data_reg[30] (\not_strict_mode.app_rd_data_reg[30] ), .\not_strict_mode.app_rd_data_reg[31] (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[32] (\not_strict_mode.app_rd_data_reg[32] ), .\not_strict_mode.app_rd_data_reg[33] (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[34] (\not_strict_mode.app_rd_data_reg[34] ), .\not_strict_mode.app_rd_data_reg[35] (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[36] (\not_strict_mode.app_rd_data_reg[36] ), .\not_strict_mode.app_rd_data_reg[37] (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[38] (\not_strict_mode.app_rd_data_reg[38] ), .\not_strict_mode.app_rd_data_reg[39] (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[3] (\not_strict_mode.app_rd_data_reg[3] ), .\not_strict_mode.app_rd_data_reg[40] (\not_strict_mode.app_rd_data_reg[40] ), .\not_strict_mode.app_rd_data_reg[41] (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[42] (\not_strict_mode.app_rd_data_reg[42] ), .\not_strict_mode.app_rd_data_reg[43] (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[44] (\not_strict_mode.app_rd_data_reg[44] ), .\not_strict_mode.app_rd_data_reg[45] (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[46] (\not_strict_mode.app_rd_data_reg[46] ), .\not_strict_mode.app_rd_data_reg[47] (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[48] (\not_strict_mode.app_rd_data_reg[48] ), .\not_strict_mode.app_rd_data_reg[49] (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[4] (\not_strict_mode.app_rd_data_reg[4] ), .\not_strict_mode.app_rd_data_reg[50] (\not_strict_mode.app_rd_data_reg[50] ), .\not_strict_mode.app_rd_data_reg[51] (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[52] (\not_strict_mode.app_rd_data_reg[52] ), .\not_strict_mode.app_rd_data_reg[53] (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[54] (\not_strict_mode.app_rd_data_reg[54] ), .\not_strict_mode.app_rd_data_reg[55] (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[56] (\not_strict_mode.app_rd_data_reg[56] ), .\not_strict_mode.app_rd_data_reg[57] (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[58] (\not_strict_mode.app_rd_data_reg[58] ), .\not_strict_mode.app_rd_data_reg[59] (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[5] (\not_strict_mode.app_rd_data_reg[5] ), .\not_strict_mode.app_rd_data_reg[60] (\not_strict_mode.app_rd_data_reg[60] ), .\not_strict_mode.app_rd_data_reg[61] (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[62] (\not_strict_mode.app_rd_data_reg[62] ), .\not_strict_mode.app_rd_data_reg[63] (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[64] (\not_strict_mode.app_rd_data_reg[64] ), .\not_strict_mode.app_rd_data_reg[65] (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[66] (\not_strict_mode.app_rd_data_reg[66] ), .\not_strict_mode.app_rd_data_reg[67] (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[68] (\not_strict_mode.app_rd_data_reg[68] ), .\not_strict_mode.app_rd_data_reg[69] (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[6] (\not_strict_mode.app_rd_data_reg[6] ), .\not_strict_mode.app_rd_data_reg[70] (\not_strict_mode.app_rd_data_reg[70] ), .\not_strict_mode.app_rd_data_reg[71] (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[72] (\not_strict_mode.app_rd_data_reg[72] ), .\not_strict_mode.app_rd_data_reg[73] (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[74] (\not_strict_mode.app_rd_data_reg[74] ), .\not_strict_mode.app_rd_data_reg[75] (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[76] (\not_strict_mode.app_rd_data_reg[76] ), .\not_strict_mode.app_rd_data_reg[77] (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[78] (\not_strict_mode.app_rd_data_reg[78] ), .\not_strict_mode.app_rd_data_reg[79] (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[7] (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[80] (\not_strict_mode.app_rd_data_reg[80] ), .\not_strict_mode.app_rd_data_reg[81] (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[82] (\not_strict_mode.app_rd_data_reg[82] ), .\not_strict_mode.app_rd_data_reg[83] (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[84] (\not_strict_mode.app_rd_data_reg[84] ), .\not_strict_mode.app_rd_data_reg[85] (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[86] (\not_strict_mode.app_rd_data_reg[86] ), .\not_strict_mode.app_rd_data_reg[87] (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.app_rd_data_reg[88] (\not_strict_mode.app_rd_data_reg[88] ), .\not_strict_mode.app_rd_data_reg[89] (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[8] (\not_strict_mode.app_rd_data_reg[8] ), .\not_strict_mode.app_rd_data_reg[90] (\not_strict_mode.app_rd_data_reg[90] ), .\not_strict_mode.app_rd_data_reg[91] (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[92] (\not_strict_mode.app_rd_data_reg[92] ), .\not_strict_mode.app_rd_data_reg[93] (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[94] (\not_strict_mode.app_rd_data_reg[94] ), .\not_strict_mode.app_rd_data_reg[95] (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[96] (\not_strict_mode.app_rd_data_reg[96] ), .\not_strict_mode.app_rd_data_reg[97] (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[98] (\not_strict_mode.app_rd_data_reg[98] ), .\not_strict_mode.app_rd_data_reg[99] (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9] (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ), 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.\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (ddr_phy_top0_n_97), .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ), .ofs_rdy_r_reg(ddr_phy_top0_n_641), .ofs_rdy_r_reg_0(ddr_phy_top0_n_642), .p_81_in(p_81_in), .phy_dout({phy_dout[5:3],phy_dout[1]}), .phy_mc_ctl_full(phy_mc_ctl_full), .pi_cnt_dec_reg(pi_cnt_dec_reg), .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg), .\pi_rst_stg1_cal_r_reg[0] (\pi_rst_stg1_cal_r_reg[0] ), .pll_locked(pll_locked), .po_cnt_dec_reg(po_cnt_dec_reg), .poc_sample_pd(poc_sample_pd), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .ram_init_done_r(ram_init_done_r), .rd_buf_we(rd_buf_we), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[0] ({\rd_ptr_timing_reg[0] [37:6],\rd_ptr_timing_reg[0] [4],\rd_ptr_timing_reg[0] [1]}), .\rd_ptr_timing_reg[0]_0 ({\rd_ptr_timing_reg[0]_0 [3],\rd_ptr_timing_reg[0]_0 [1]}), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .\read_fifo.fifo_out_data_r_reg[6] (\col_mach0/p_0_in ), .\read_fifo.fifo_out_data_r_reg[6]_0 (bypass__0), .\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_379), .\resume_wait_r_reg[5] (\resume_wait_r_reg[5] ), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0), .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0), .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1), .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg), .\samps_r_reg[9] (\samps_r_reg[9] ), .sent_col(sent_col), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .tail_r(tail_r), .tempmon_sample_en(tempmon_sample_en), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2]_0 ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_1 )); ddr3_if_mig_7series_v4_0_mc mc0 (.CLK(CLK), .E(E), .Q(req_bank_r[2:0]), .SR(SR), .accept_ns(accept_ns), .act_wait_r_lcl_reg(act_wait_r_lcl_reg), .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0), .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1), .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2), .\app_addr_r1_reg[12] (\app_addr_r1_reg[12] ), .\app_addr_r1_reg[27] (\app_addr_r1_reg[27] ), .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ), .\app_cmd_r1_reg[0] (\app_cmd_r1_reg[0] ), .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ), .app_hi_pri_r2(app_hi_pri_r2), .app_rd_data_end_ns(app_rd_data_end_ns), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .bm_end_r1(bm_end_r1), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_4(bm_end_r1_4), .bm_end_r1_reg(bm_end_r1_reg), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bypass__0(bypass__0), .\cmd_pipe_plus.mc_bank_reg[2]_0 (req_bank_r[5:3]), .\cmd_pipe_plus.mc_bank_reg[8]_0 (req_bank_r[8:6]), .\cmd_pipe_plus.mc_bank_reg[8]_1 (req_bank_r[11:9]), .\data_offset_1_i1_reg[0] (mc0_n_126), .\data_offset_1_i1_reg[1] (mc0_n_125), .\data_offset_1_i1_reg[2] (mc0_n_128), .\data_offset_1_i1_reg[3] (mc0_n_127), .\data_offset_1_i1_reg[4] (mc0_n_124), .\data_offset_1_i1_reg[5] (mc0_n_123), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (ddr_phy_top0_n_97), .\entry_cnt_reg[2] (ddr_phy_top0_n_642), .\entry_cnt_reg[2]_0 (ddr_phy_top0_n_641), .granted_col_r_reg(ddr_phy_top0_n_359), .granted_col_r_reg_0(ddr_phy_top0_n_367), .granted_col_r_reg_1(ddr_phy_top0_n_369), .granted_col_r_reg_2(ddr_phy_top0_n_377), .hi_priority(hi_priority), .idle(idle), .in0(in0), .init_calib_complete_reg_rep__6(ddr_phy_top0_n_50), .init_calib_complete_reg_rep__7(ddr_phy_top0_n_51), .maint_prescaler_r1(\rank_mach0/rank_common0/maint_prescaler_r1 ), .mc_cas_n(mc_cas_n), .mc_cke(mc_cke), .mc_cmd(mc_cmd), .mc_cs_n(mc_cs_n), .mc_odt(mc_odt), .mc_ras_n(mc_ras_n), .mc_we_n(mc_we_n), .mc_wrdata_en(mc_wrdata_en), .\my_empty_reg[7] ({mux_address[43],mux_address[13]}), .\my_full_reg[3] ({mc_address[44:30],mc_address[25:18],mc_address[14:0]}), .\not_strict_mode.app_rd_data_end_reg ({\not_strict_mode.app_rd_data_end_reg [6],\col_mach0/p_0_in ,\not_strict_mode.app_rd_data_end_reg [5:0]}), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ), .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .\phy_ctl_wd_i1_reg[17] (mc0_n_120), .\phy_ctl_wd_i1_reg[18] (mc0_n_119), .\phy_ctl_wd_i1_reg[19] (mc0_n_122), .\phy_ctl_wd_i1_reg[20] (mc0_n_121), .\phy_ctl_wd_i1_reg[21] (mc0_n_118), .\phy_ctl_wd_i1_reg[22] (mc0_n_117), .phy_dout({phy_dout[2],phy_dout[0]}), .phy_mc_ctl_full(phy_mc_ctl_full), .pointer_we(pointer_we), .ram_init_done_r(ram_init_done_r), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_368), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (ddr_phy_top0_n_380), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (ddr_phy_top0_n_366), .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (ddr_phy_top0_n_376), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ({ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373,ddr_phy_top0_n_374,ddr_phy_top0_n_375}), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (ddr_phy_top0_n_378), .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 (ddr_phy_top0_n_381), .\ras_timer_r_reg[2] (\ras_timer_r_reg[2] ), .\rd_buf_indx.rd_buf_indx_r_reg[4] (\rd_buf_indx.rd_buf_indx_r_reg[4] ), .\rd_ptr_timing_reg[0] ({\rd_ptr_timing_reg[0]_0 [4],\rd_ptr_timing_reg[0]_0 [2],\rd_ptr_timing_reg[0]_0 [0]}), .\rd_ptr_timing_reg[0]_0 ({\rd_ptr_timing_reg[0] [5],\rd_ptr_timing_reg[0] [3:2],\rd_ptr_timing_reg[0] [0]}), .\rd_ptr_timing_reg[0]_1 (mc_bank), .\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_379), .\read_fifo.tail_r_reg[1] (tail_r), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ), .\req_bank_r_lcl_reg[0]_0 (\req_bank_r_lcl_reg[0]_0 ), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ), .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rtp_timer_ns1(rtp_timer_ns1), .rtp_timer_ns1_6(rtp_timer_ns1_6), .rtp_timer_ns1_7(rtp_timer_ns1_7), .sent_col(sent_col), .tempmon_sample_en(tempmon_sample_en), .use_addr(use_addr), .\write_buffer.wr_buf_out_data_reg[287] (\write_buffer.wr_buf_out_data_reg[287] )); endmodule module ddr3_if_mig_7series_v4_0_memc_ui_top_axi (bm_end_r1, pass_open_bank_r, bm_end_r1_0, pass_open_bank_r_1, bm_end_r1_2, pass_open_bank_r_3, bm_end_r1_4, pass_open_bank_r_5, app_ref_ack, app_zq_ack, app_sr_active, ddr3_reset_n, ddr3_cas_n, ddr3_ras_n, ddr3_we_n, ddr3_addr, ddr3_ba, ddr3_cs_n, ddr3_odt, ddr3_cke, ddr3_dm, \rd_ptr_timing_reg[2] , \rd_ptr_timing_reg[2]_0 , \rd_ptr_timing_reg[2]_1 , \rd_ptr_timing_reg[2]_2 , \rd_ptr_timing_reg[2]_3 , \rd_ptr_timing_reg[2]_4 , \rd_ptr_timing_reg[2]_5 , \rd_ptr_timing_reg[2]_6 , \rd_ptr_timing_reg[2]_7 , \rd_ptr_timing_reg[2]_8 , \rd_ptr_timing_reg[2]_9 , \rd_ptr_timing_reg[2]_10 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 , \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 , phy_dout, sm_r, phy_mc_go, \pi_rst_stg1_cal_r_reg[0] , samp_edge_cnt0_en_r, pi_cnt_dec, po_cnt_dec, \rd_ptr_timing_reg[0] , \rd_ptr_timing_reg[0]_0 , \resume_wait_r_reg[5] , stg3_dec2init_val_r_reg, stg3_inc2init_val_r_reg, rst_sync_r1_reg, s_axi_arready, \stg2_tap_cnt_reg[0] , \sm_r_reg[0] , D, \en_cnt_div4.enable_wrlvl_cnt_reg[3] , \complex_row_cnt_ocal_reg[0] , \row_cnt_victim_rotate.complex_row_cnt_reg[4] , Q, \wr_ptr_timing_reg[2] , \wr_ptr_timing_reg[2]_0 , wr_en, wr_en_5, wr_en_6, ddr_ck_out, E, s_axi_awready, s_axi_wready, out, s_axi_rid, s_axi_bid, s_axi_bvalid, s_axi_rvalid, s_axi_rlast, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n, CLK, rstdiv0_sync_r1_reg_rep__0, SR, rstdiv0_sync_r1_reg_rep__20, rstdiv0_sync_r1_reg_rep__21, app_ref_req, app_zq_req, app_sr_req, rstdiv0_sync_r1_reg_rep__22, rstdiv0_sync_r1_reg_rep__23, mmcm_ps_clk, rst_sync_r1, poc_sample_pd, freq_refclk, mem_refclk, sync_pulse, pll_locked, in0, CLKB0, CLKB0_7, CLKB0_8, CLKB0_9, RST0, rstdiv0_sync_r1_reg_rep__9, rstdiv0_sync_r1_reg_rep__10, rstdiv0_sync_r1_reg_rep__26, rstdiv0_sync_r1_reg_rep__12, rstdiv0_sync_r1_reg_rep__2, rstdiv0_sync_r1_reg_rep__24, rstdiv0_sync_r1_reg_rep__13, rstdiv0_sync_r1_reg_rep__14, rstdiv0_sync_r1_reg_rep__11, cnt_pwron_reset_done_r0, rstdiv0_sync_r1_reg_rep__18, rstdiv0_sync_r1_reg_rep__16, SS, rstdiv0_sync_r1_reg_rep__7, mem_out, \rd_ptr_reg[3] , rstdiv0_sync_r1_reg_rep__26_0, rstdiv0_sync_r1_reg_rep__25, \sm_r_reg[0]_0 , \rd_ptr_reg[3]_0 , sys_rst, \rst_ref_gen_1.rst_ref_sync_r_reg[1][14] , mmcm_locked, s_axi_arvalid, rstdiv0_sync_r1_reg_rep__26_1, rstdiv0_sync_r1_reg_rep__26_2, \mmcm_init_trail_reg[0] , \mmcm_current_reg[0] , bm_end_r1_reg, bm_end_r1_reg_0, bm_end_r1_reg_1, pass_open_bank_r_lcl_reg, bm_end_r1_reg_2, rtp_timer_ns1, rtp_timer_ns1_6, rtp_timer_ns1_7, psdone, rstdiv0_sync_r1_reg_rep__19, fine_adjust_reg, samp_edge_cnt0_en_r_reg, pi_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__24_0, p_81_in, rstdiv0_sync_r1_reg_rep__24_1, rstdiv0_sync_r1_reg_rep__17, po_cnt_dec_reg, rstdiv0_sync_r1_reg_rep__5, \device_temp_r_reg[11] , rstdiv0_sync_r1_reg_rep__4, rstdiv0_sync_r1_reg_rep__6, \stg3_r_reg[0] , rstdiv0_sync_r1_reg_rep__8, s_axi_awlen, s_axi_bready, s_axi_awvalid, s_axi_awaddr, s_axi_awburst, s_axi_wvalid, s_axi_awid, s_axi_arlen, s_axi_araddr, s_axi_arburst, s_axi_rready, s_axi_wstrb, s_axi_wdata, aresetn, s_axi_arid); output bm_end_r1; output pass_open_bank_r; output bm_end_r1_0; output pass_open_bank_r_1; output bm_end_r1_2; output pass_open_bank_r_3; output bm_end_r1_4; output pass_open_bank_r_5; output app_ref_ack; output app_zq_ack; output app_sr_active; output ddr3_reset_n; output ddr3_cas_n; output ddr3_ras_n; output ddr3_we_n; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output [0:0]ddr3_cs_n; output [0:0]ddr3_odt; output [0:0]ddr3_cke; output [3:0]ddr3_dm; output \rd_ptr_timing_reg[2] ; output \rd_ptr_timing_reg[2]_0 ; output \rd_ptr_timing_reg[2]_1 ; output \rd_ptr_timing_reg[2]_2 ; output \rd_ptr_timing_reg[2]_3 ; output \rd_ptr_timing_reg[2]_4 ; output \rd_ptr_timing_reg[2]_5 ; output \rd_ptr_timing_reg[2]_6 ; output \rd_ptr_timing_reg[2]_7 ; output \rd_ptr_timing_reg[2]_8 ; output \rd_ptr_timing_reg[2]_9 ; output \rd_ptr_timing_reg[2]_10 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; output [5:0]phy_dout; output sm_r; output phy_mc_go; output \pi_rst_stg1_cal_r_reg[0] ; output samp_edge_cnt0_en_r; output pi_cnt_dec; output po_cnt_dec; output [37:0]\rd_ptr_timing_reg[0] ; output [4:0]\rd_ptr_timing_reg[0]_0 ; output \resume_wait_r_reg[5] ; output stg3_dec2init_val_r_reg; output stg3_inc2init_val_r_reg; output rst_sync_r1_reg; output s_axi_arready; output \stg2_tap_cnt_reg[0] ; output \sm_r_reg[0] ; output [0:0]D; output \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; output \complex_row_cnt_ocal_reg[0] ; output \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; output [3:0]Q; output [3:0]\wr_ptr_timing_reg[2] ; output [3:0]\wr_ptr_timing_reg[2]_0 ; output wr_en; output wr_en_5; output wr_en_6; output [1:0]ddr_ck_out; output [0:0]E; output s_axi_awready; output s_axi_wready; output [256:0]out; output [0:0]s_axi_rid; output [0:0]s_axi_bid; output s_axi_bvalid; output s_axi_rvalid; output s_axi_rlast; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_p; inout [3:0]ddr3_dqs_n; input CLK; input rstdiv0_sync_r1_reg_rep__0; input [0:0]SR; input rstdiv0_sync_r1_reg_rep__20; input rstdiv0_sync_r1_reg_rep__21; input app_ref_req; input app_zq_req; input app_sr_req; input rstdiv0_sync_r1_reg_rep__22; input rstdiv0_sync_r1_reg_rep__23; input mmcm_ps_clk; input rst_sync_r1; input poc_sample_pd; input freq_refclk; input mem_refclk; input sync_pulse; input pll_locked; input in0; input CLKB0; input CLKB0_7; input CLKB0_8; input CLKB0_9; input RST0; input rstdiv0_sync_r1_reg_rep__9; input rstdiv0_sync_r1_reg_rep__10; input rstdiv0_sync_r1_reg_rep__26; input rstdiv0_sync_r1_reg_rep__12; input rstdiv0_sync_r1_reg_rep__2; input rstdiv0_sync_r1_reg_rep__24; input rstdiv0_sync_r1_reg_rep__13; input [1:0]rstdiv0_sync_r1_reg_rep__14; input [0:0]rstdiv0_sync_r1_reg_rep__11; input cnt_pwron_reset_done_r0; input [0:0]rstdiv0_sync_r1_reg_rep__18; input [0:0]rstdiv0_sync_r1_reg_rep__16; input [0:0]SS; input rstdiv0_sync_r1_reg_rep__7; input [17:0]mem_out; input [71:0]\rd_ptr_reg[3] ; input rstdiv0_sync_r1_reg_rep__26_0; input rstdiv0_sync_r1_reg_rep__25; input [0:0]\sm_r_reg[0]_0 ; input [29:0]\rd_ptr_reg[3]_0 ; input sys_rst; input [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; input mmcm_locked; input s_axi_arvalid; input rstdiv0_sync_r1_reg_rep__26_1; input rstdiv0_sync_r1_reg_rep__26_2; input \mmcm_init_trail_reg[0] ; input \mmcm_current_reg[0] ; input bm_end_r1_reg; input bm_end_r1_reg_0; input bm_end_r1_reg_1; input pass_open_bank_r_lcl_reg; input bm_end_r1_reg_2; input rtp_timer_ns1; input rtp_timer_ns1_6; input rtp_timer_ns1_7; input psdone; input [0:0]rstdiv0_sync_r1_reg_rep__19; input fine_adjust_reg; input samp_edge_cnt0_en_r_reg; input [0:0]pi_cnt_dec_reg; input rstdiv0_sync_r1_reg_rep__24_0; input p_81_in; input rstdiv0_sync_r1_reg_rep__24_1; input [0:0]rstdiv0_sync_r1_reg_rep__17; input [0:0]po_cnt_dec_reg; input [0:0]rstdiv0_sync_r1_reg_rep__5; input [11:0]\device_temp_r_reg[11] ; input rstdiv0_sync_r1_reg_rep__4; input rstdiv0_sync_r1_reg_rep__6; input \stg3_r_reg[0] ; input rstdiv0_sync_r1_reg_rep__8; input [7:0]s_axi_awlen; input s_axi_bready; input s_axi_awvalid; input [29:0]s_axi_awaddr; input [0:0]s_axi_awburst; input s_axi_wvalid; input [0:0]s_axi_awid; input [7:0]s_axi_arlen; input [29:0]s_axi_araddr; input [0:0]s_axi_arburst; input s_axi_rready; input [31:0]s_axi_wstrb; input [255:0]s_axi_wdata; input aresetn; input [0:0]s_axi_arid; wire CLK; wire CLKB0; wire CLKB0_7; wire CLKB0_8; wire CLKB0_9; wire [0:0]D; wire [0:0]E; wire [3:0]Q; wire RST0; wire [0:0]SR; wire [0:0]SS; wire accept_ns; wire [27:3]app_addr; wire [0:0]app_cmd; wire [255:0]app_rd_data; wire [255:0]app_rd_data_ns; wire app_rd_data_valid; wire app_rdy; wire app_ref_ack; wire app_ref_req; wire app_sr_active; wire app_sr_req; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire app_zq_ack; wire app_zq_req; wire aresetn; wire [255:0]\axi_mc_w_channel_0/mc_app_wdf_data_reg ; wire [31:0]\axi_mc_w_channel_0/mc_app_wdf_mask_reg ; wire \axi_mc_w_channel_0/mc_app_wdf_wren_reg ; wire [255:0]\axi_mc_w_channel_0/next_wdf_data ; wire [31:0]\axi_mc_w_channel_0/next_wdf_mask ; wire [2:0]bank; wire bm_end_r1; wire bm_end_r1_0; wire bm_end_r1_2; wire bm_end_r1_4; wire bm_end_r1_reg; wire bm_end_r1_reg_0; wire bm_end_r1_reg_1; wire bm_end_r1_reg_2; wire [1:1]cmd; wire cnt_pwron_reset_done_r0; wire [9:3]col; wire \complex_row_cnt_ocal_reg[0] ; wire [4:0]data_buf_addr; wire [14:0]ddr3_addr; wire [2:0]ddr3_ba; wire ddr3_cas_n; wire [0:0]ddr3_cke; wire [0:0]ddr3_cs_n; wire [3:0]ddr3_dm; wire [31:0]ddr3_dq; wire [3:0]ddr3_dqs_n; wire [3:0]ddr3_dqs_p; wire [0:0]ddr3_odt; wire ddr3_ras_n; wire ddr3_reset_n; wire ddr3_we_n; wire [1:0]ddr_ck_out; wire [11:0]\device_temp_r_reg[11] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ; wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ; wire \en_cnt_div4.enable_wrlvl_cnt_reg[3] ; wire fine_adjust_reg; wire freq_refclk; wire hi_priority; wire in0; wire init_calib_complete_r; wire [11:0]\mc0/bank_mach0/req_bank_r ; wire mem_intfc0_n_142; wire mem_intfc0_n_143; wire mem_intfc0_n_144; wire mem_intfc0_n_145; wire mem_intfc0_n_146; wire mem_intfc0_n_147; wire mem_intfc0_n_148; wire mem_intfc0_n_149; wire mem_intfc0_n_150; wire mem_intfc0_n_151; wire mem_intfc0_n_152; wire mem_intfc0_n_153; wire mem_intfc0_n_154; wire mem_intfc0_n_155; wire mem_intfc0_n_156; wire mem_intfc0_n_157; wire mem_intfc0_n_158; wire mem_intfc0_n_159; wire mem_intfc0_n_160; wire mem_intfc0_n_161; wire mem_intfc0_n_162; wire mem_intfc0_n_163; wire mem_intfc0_n_164; wire mem_intfc0_n_165; wire mem_intfc0_n_166; wire mem_intfc0_n_167; wire mem_intfc0_n_168; wire mem_intfc0_n_169; wire mem_intfc0_n_170; wire mem_intfc0_n_171; wire mem_intfc0_n_172; wire mem_intfc0_n_173; wire mem_intfc0_n_174; wire mem_intfc0_n_175; wire mem_intfc0_n_176; wire mem_intfc0_n_177; wire mem_intfc0_n_178; wire mem_intfc0_n_179; wire mem_intfc0_n_180; wire mem_intfc0_n_181; wire mem_intfc0_n_182; wire mem_intfc0_n_183; wire mem_intfc0_n_184; wire mem_intfc0_n_185; wire mem_intfc0_n_186; wire mem_intfc0_n_187; wire mem_intfc0_n_188; wire mem_intfc0_n_189; wire mem_intfc0_n_190; wire mem_intfc0_n_191; wire mem_intfc0_n_192; wire mem_intfc0_n_193; wire mem_intfc0_n_194; wire mem_intfc0_n_195; wire mem_intfc0_n_196; wire mem_intfc0_n_197; wire mem_intfc0_n_198; wire mem_intfc0_n_199; wire mem_intfc0_n_200; wire mem_intfc0_n_201; wire mem_intfc0_n_202; wire mem_intfc0_n_203; wire mem_intfc0_n_204; wire mem_intfc0_n_205; wire mem_intfc0_n_206; wire mem_intfc0_n_207; wire mem_intfc0_n_208; wire mem_intfc0_n_209; wire mem_intfc0_n_210; wire mem_intfc0_n_211; wire mem_intfc0_n_212; wire mem_intfc0_n_213; wire mem_intfc0_n_214; wire mem_intfc0_n_215; wire mem_intfc0_n_216; wire mem_intfc0_n_217; wire mem_intfc0_n_218; wire mem_intfc0_n_219; wire mem_intfc0_n_220; wire mem_intfc0_n_221; wire mem_intfc0_n_222; wire mem_intfc0_n_223; wire mem_intfc0_n_224; wire mem_intfc0_n_225; wire mem_intfc0_n_226; wire mem_intfc0_n_227; wire mem_intfc0_n_228; wire mem_intfc0_n_229; wire mem_intfc0_n_230; wire mem_intfc0_n_231; wire mem_intfc0_n_232; wire mem_intfc0_n_233; wire mem_intfc0_n_234; wire mem_intfc0_n_235; wire mem_intfc0_n_236; wire mem_intfc0_n_237; wire mem_intfc0_n_238; wire mem_intfc0_n_239; wire mem_intfc0_n_240; wire mem_intfc0_n_241; wire mem_intfc0_n_242; wire mem_intfc0_n_243; wire mem_intfc0_n_244; wire mem_intfc0_n_245; wire mem_intfc0_n_246; wire mem_intfc0_n_247; wire mem_intfc0_n_248; wire mem_intfc0_n_249; wire mem_intfc0_n_250; wire mem_intfc0_n_251; wire mem_intfc0_n_252; wire mem_intfc0_n_253; wire mem_intfc0_n_254; wire mem_intfc0_n_255; wire mem_intfc0_n_256; wire mem_intfc0_n_257; wire mem_intfc0_n_258; wire mem_intfc0_n_259; wire mem_intfc0_n_260; wire mem_intfc0_n_261; wire mem_intfc0_n_262; wire mem_intfc0_n_263; wire mem_intfc0_n_264; wire mem_intfc0_n_265; wire mem_intfc0_n_266; wire mem_intfc0_n_267; wire mem_intfc0_n_268; wire mem_intfc0_n_269; wire mem_intfc0_n_270; wire mem_intfc0_n_271; wire mem_intfc0_n_272; wire mem_intfc0_n_273; wire mem_intfc0_n_274; wire mem_intfc0_n_275; wire mem_intfc0_n_276; wire mem_intfc0_n_277; wire mem_intfc0_n_278; wire mem_intfc0_n_279; wire mem_intfc0_n_280; wire mem_intfc0_n_281; wire mem_intfc0_n_282; wire mem_intfc0_n_283; wire mem_intfc0_n_284; wire mem_intfc0_n_285; wire mem_intfc0_n_286; wire mem_intfc0_n_287; wire mem_intfc0_n_288; wire mem_intfc0_n_289; wire mem_intfc0_n_290; wire mem_intfc0_n_291; wire mem_intfc0_n_292; wire mem_intfc0_n_293; wire mem_intfc0_n_294; wire mem_intfc0_n_295; wire mem_intfc0_n_296; wire mem_intfc0_n_297; wire mem_intfc0_n_298; wire mem_intfc0_n_299; wire mem_intfc0_n_300; wire mem_intfc0_n_301; wire mem_intfc0_n_302; wire mem_intfc0_n_303; wire mem_intfc0_n_304; wire mem_intfc0_n_305; wire mem_intfc0_n_306; wire mem_intfc0_n_307; wire mem_intfc0_n_308; wire mem_intfc0_n_309; wire mem_intfc0_n_310; wire mem_intfc0_n_311; wire mem_intfc0_n_312; wire mem_intfc0_n_313; wire mem_intfc0_n_314; wire mem_intfc0_n_315; wire mem_intfc0_n_316; wire mem_intfc0_n_317; wire mem_intfc0_n_318; wire mem_intfc0_n_319; wire mem_intfc0_n_320; wire mem_intfc0_n_321; wire mem_intfc0_n_322; wire mem_intfc0_n_323; wire mem_intfc0_n_324; wire mem_intfc0_n_325; wire mem_intfc0_n_326; wire mem_intfc0_n_327; wire mem_intfc0_n_328; wire mem_intfc0_n_329; wire mem_intfc0_n_330; wire mem_intfc0_n_331; wire mem_intfc0_n_332; wire mem_intfc0_n_333; wire mem_intfc0_n_334; wire mem_intfc0_n_335; wire mem_intfc0_n_336; wire mem_intfc0_n_337; wire mem_intfc0_n_338; wire mem_intfc0_n_339; wire mem_intfc0_n_340; wire mem_intfc0_n_341; wire mem_intfc0_n_342; wire mem_intfc0_n_343; wire mem_intfc0_n_344; wire mem_intfc0_n_345; wire mem_intfc0_n_346; wire mem_intfc0_n_347; wire mem_intfc0_n_348; wire mem_intfc0_n_349; wire mem_intfc0_n_350; wire mem_intfc0_n_351; wire mem_intfc0_n_352; wire mem_intfc0_n_353; wire mem_intfc0_n_354; wire mem_intfc0_n_355; wire mem_intfc0_n_356; wire mem_intfc0_n_357; wire mem_intfc0_n_358; wire mem_intfc0_n_359; wire mem_intfc0_n_360; wire mem_intfc0_n_361; wire mem_intfc0_n_362; wire mem_intfc0_n_363; wire mem_intfc0_n_364; wire mem_intfc0_n_365; wire mem_intfc0_n_366; wire mem_intfc0_n_367; wire mem_intfc0_n_368; wire mem_intfc0_n_369; wire mem_intfc0_n_370; wire mem_intfc0_n_371; wire mem_intfc0_n_372; wire mem_intfc0_n_373; wire mem_intfc0_n_374; wire mem_intfc0_n_375; wire mem_intfc0_n_376; wire mem_intfc0_n_377; wire mem_intfc0_n_378; wire mem_intfc0_n_379; wire mem_intfc0_n_380; wire mem_intfc0_n_381; wire mem_intfc0_n_382; wire mem_intfc0_n_383; wire mem_intfc0_n_384; wire mem_intfc0_n_385; wire mem_intfc0_n_386; wire mem_intfc0_n_387; wire mem_intfc0_n_388; wire mem_intfc0_n_389; wire mem_intfc0_n_390; wire mem_intfc0_n_391; wire mem_intfc0_n_392; wire mem_intfc0_n_393; wire mem_intfc0_n_394; wire mem_intfc0_n_395; wire mem_intfc0_n_396; wire mem_intfc0_n_397; (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire mem_intfc0_n_77; wire [17:0]mem_out; wire mem_refclk; wire \mmcm_current_reg[0] ; wire \mmcm_init_trail_reg[0] ; wire mmcm_locked; wire mmcm_ps_clk; wire [256:0]out; wire p_81_in; wire pass_open_bank_r; wire pass_open_bank_r_1; wire pass_open_bank_r_3; wire pass_open_bank_r_5; wire pass_open_bank_r_lcl_reg; wire [5:0]phy_dout; wire phy_mc_go; wire pi_cnt_dec; wire [0:0]pi_cnt_dec_reg; wire \pi_rst_stg1_cal_r_reg[0] ; wire pll_locked; wire po_cnt_dec; wire [0:0]po_cnt_dec_reg; wire poc_sample_pd; wire psdone; wire [3:0]ram_init_addr; wire ram_init_done_r; wire [4:0]rd_data_addr; wire rd_data_end; wire rd_data_offset; wire [71:0]\rd_ptr_reg[3] ; wire [29:0]\rd_ptr_reg[3]_0 ; wire [37:0]\rd_ptr_timing_reg[0] ; wire [4:0]\rd_ptr_timing_reg[0]_0 ; wire \rd_ptr_timing_reg[2] ; wire \rd_ptr_timing_reg[2]_0 ; wire \rd_ptr_timing_reg[2]_1 ; wire \rd_ptr_timing_reg[2]_10 ; wire \rd_ptr_timing_reg[2]_2 ; wire \rd_ptr_timing_reg[2]_3 ; wire \rd_ptr_timing_reg[2]_4 ; wire \rd_ptr_timing_reg[2]_5 ; wire \rd_ptr_timing_reg[2]_6 ; wire \rd_ptr_timing_reg[2]_7 ; wire \rd_ptr_timing_reg[2]_8 ; wire \rd_ptr_timing_reg[2]_9 ; wire reset_reg_n_0; wire \resume_wait_r_reg[5] ; wire [14:0]row; wire \row_cnt_victim_rotate.complex_row_cnt_reg[4] ; wire [0:0]\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ; wire rst_sync_r1; wire rst_sync_r1_reg; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__10; wire [0:0]rstdiv0_sync_r1_reg_rep__11; wire rstdiv0_sync_r1_reg_rep__12; wire rstdiv0_sync_r1_reg_rep__13; wire [1:0]rstdiv0_sync_r1_reg_rep__14; wire [0:0]rstdiv0_sync_r1_reg_rep__16; wire [0:0]rstdiv0_sync_r1_reg_rep__17; wire [0:0]rstdiv0_sync_r1_reg_rep__18; wire [0:0]rstdiv0_sync_r1_reg_rep__19; wire rstdiv0_sync_r1_reg_rep__2; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire rstdiv0_sync_r1_reg_rep__23; wire rstdiv0_sync_r1_reg_rep__24; wire rstdiv0_sync_r1_reg_rep__24_0; wire rstdiv0_sync_r1_reg_rep__24_1; wire rstdiv0_sync_r1_reg_rep__25; wire rstdiv0_sync_r1_reg_rep__26; wire rstdiv0_sync_r1_reg_rep__26_0; wire rstdiv0_sync_r1_reg_rep__26_1; wire rstdiv0_sync_r1_reg_rep__26_2; wire rstdiv0_sync_r1_reg_rep__4; wire [0:0]rstdiv0_sync_r1_reg_rep__5; wire rstdiv0_sync_r1_reg_rep__6; wire rstdiv0_sync_r1_reg_rep__7; wire rstdiv0_sync_r1_reg_rep__8; wire rstdiv0_sync_r1_reg_rep__9; wire rtp_timer_ns1; wire rtp_timer_ns1_6; wire rtp_timer_ns1_7; wire [29:0]s_axi_araddr; wire [0:0]s_axi_arburst; wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire s_axi_arready; wire s_axi_arvalid; wire [29:0]s_axi_awaddr; wire [0:0]s_axi_awburst; wire [0:0]s_axi_awid; wire [7:0]s_axi_awlen; wire s_axi_awready; wire s_axi_awvalid; wire [0:0]s_axi_bid; wire s_axi_bready; wire s_axi_bvalid; wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; wire [255:0]s_axi_wdata; wire s_axi_wready; wire [31:0]s_axi_wstrb; wire s_axi_wvalid; wire samp_edge_cnt0_en_r; wire samp_edge_cnt0_en_r_reg; wire sm_r; wire \sm_r_reg[0] ; wire [0:0]\sm_r_reg[0]_0 ; wire \stg2_tap_cnt_reg[0] ; wire stg3_dec2init_val_r_reg; wire stg3_inc2init_val_r_reg; wire \stg3_r_reg[0] ; wire sync_pulse; wire sys_rst; wire u_ui_top_n_1; wire u_ui_top_n_260; wire u_ui_top_n_261; wire u_ui_top_n_269; wire u_ui_top_n_270; wire u_ui_top_n_274; wire u_ui_top_n_275; wire u_ui_top_n_276; wire \ui_cmd0/app_addr_r10 ; wire \ui_cmd0/app_en_ns1 ; wire \ui_cmd0/app_en_r1 ; wire \ui_cmd0/app_hi_pri_r2 ; wire \ui_rd_data0/app_rd_data_end_ns ; wire \ui_rd_data0/bypass__0 ; wire [1:0]\ui_rd_data0/p_100_out ; wire [1:0]\ui_rd_data0/p_101_out ; wire [1:0]\ui_rd_data0/p_102_out ; wire [1:0]\ui_rd_data0/p_103_out ; wire [1:0]\ui_rd_data0/p_104_out ; wire [1:0]\ui_rd_data0/p_105_out ; wire [1:0]\ui_rd_data0/p_106_out ; wire [1:0]\ui_rd_data0/p_107_out ; wire [1:0]\ui_rd_data0/p_108_out ; wire [1:0]\ui_rd_data0/p_109_out ; wire [1:0]\ui_rd_data0/p_10_out ; wire [1:0]\ui_rd_data0/p_110_out ; wire [1:0]\ui_rd_data0/p_111_out ; wire [1:0]\ui_rd_data0/p_112_out ; wire [1:0]\ui_rd_data0/p_113_out ; wire [1:0]\ui_rd_data0/p_114_out ; wire [1:0]\ui_rd_data0/p_115_out ; wire [1:0]\ui_rd_data0/p_116_out ; wire [1:0]\ui_rd_data0/p_117_out ; wire [1:0]\ui_rd_data0/p_118_out ; wire [1:0]\ui_rd_data0/p_119_out ; wire [1:0]\ui_rd_data0/p_11_out ; wire [1:0]\ui_rd_data0/p_120_out ; wire [1:0]\ui_rd_data0/p_121_out ; wire [1:0]\ui_rd_data0/p_122_out ; wire [1:0]\ui_rd_data0/p_123_out ; wire [1:0]\ui_rd_data0/p_124_out ; wire [1:0]\ui_rd_data0/p_125_out ; wire [1:0]\ui_rd_data0/p_127_out ; wire [1:0]\ui_rd_data0/p_128_out ; wire [1:0]\ui_rd_data0/p_129_out ; wire [1:0]\ui_rd_data0/p_12_out ; wire [1:0]\ui_rd_data0/p_13_out ; wire [1:0]\ui_rd_data0/p_14_out ; wire [1:0]\ui_rd_data0/p_15_out ; wire [1:0]\ui_rd_data0/p_16_out ; wire [1:0]\ui_rd_data0/p_17_out ; wire [1:0]\ui_rd_data0/p_18_out ; wire [1:0]\ui_rd_data0/p_19_out ; wire [1:0]\ui_rd_data0/p_1_out ; wire [1:0]\ui_rd_data0/p_20_out ; wire [1:0]\ui_rd_data0/p_21_out ; wire [1:0]\ui_rd_data0/p_22_out ; wire [1:0]\ui_rd_data0/p_23_out ; wire [1:0]\ui_rd_data0/p_24_out ; wire [1:0]\ui_rd_data0/p_25_out ; wire [1:0]\ui_rd_data0/p_26_out ; wire [1:0]\ui_rd_data0/p_27_out ; wire [1:0]\ui_rd_data0/p_28_out ; wire [1:0]\ui_rd_data0/p_29_out ; wire [1:0]\ui_rd_data0/p_30_out ; wire [1:0]\ui_rd_data0/p_31_out ; wire [1:0]\ui_rd_data0/p_32_out ; wire [1:0]\ui_rd_data0/p_33_out ; wire [1:0]\ui_rd_data0/p_34_out ; wire [1:0]\ui_rd_data0/p_35_out ; wire [1:0]\ui_rd_data0/p_36_out ; wire [1:0]\ui_rd_data0/p_37_out ; wire [1:0]\ui_rd_data0/p_38_out ; wire [1:0]\ui_rd_data0/p_39_out ; wire [1:0]\ui_rd_data0/p_3_out ; wire [1:0]\ui_rd_data0/p_40_out ; wire [1:0]\ui_rd_data0/p_41_out ; wire [1:0]\ui_rd_data0/p_42_out ; wire [1:0]\ui_rd_data0/p_43_out ; wire [1:0]\ui_rd_data0/p_44_out ; wire [1:0]\ui_rd_data0/p_45_out ; wire [1:0]\ui_rd_data0/p_46_out ; wire [1:0]\ui_rd_data0/p_47_out ; wire [1:0]\ui_rd_data0/p_48_out ; wire [1:0]\ui_rd_data0/p_49_out ; wire [1:0]\ui_rd_data0/p_4_out ; wire [1:0]\ui_rd_data0/p_50_out ; wire [1:0]\ui_rd_data0/p_51_out ; wire [1:0]\ui_rd_data0/p_52_out ; wire [1:0]\ui_rd_data0/p_53_out ; wire [1:0]\ui_rd_data0/p_54_out ; wire [1:0]\ui_rd_data0/p_55_out ; wire [1:0]\ui_rd_data0/p_56_out ; wire [1:0]\ui_rd_data0/p_57_out ; wire [1:0]\ui_rd_data0/p_58_out ; wire [1:0]\ui_rd_data0/p_59_out ; wire [1:0]\ui_rd_data0/p_5_out ; wire [1:0]\ui_rd_data0/p_60_out ; wire [1:0]\ui_rd_data0/p_61_out ; wire [1:0]\ui_rd_data0/p_62_out ; wire [1:0]\ui_rd_data0/p_63_out ; wire [1:0]\ui_rd_data0/p_64_out ; wire [1:0]\ui_rd_data0/p_65_out ; wire [1:0]\ui_rd_data0/p_66_out ; wire [1:0]\ui_rd_data0/p_67_out ; wire [1:0]\ui_rd_data0/p_68_out ; wire [1:0]\ui_rd_data0/p_69_out ; wire [1:0]\ui_rd_data0/p_6_out ; wire [1:0]\ui_rd_data0/p_70_out ; wire [1:0]\ui_rd_data0/p_71_out ; wire [1:0]\ui_rd_data0/p_72_out ; wire [1:0]\ui_rd_data0/p_73_out ; wire [1:0]\ui_rd_data0/p_74_out ; wire [1:0]\ui_rd_data0/p_75_out ; wire [1:0]\ui_rd_data0/p_76_out ; wire [1:0]\ui_rd_data0/p_77_out ; wire [1:0]\ui_rd_data0/p_78_out ; wire [1:0]\ui_rd_data0/p_79_out ; wire [1:0]\ui_rd_data0/p_7_out ; wire [1:0]\ui_rd_data0/p_80_out ; wire [1:0]\ui_rd_data0/p_81_out ; wire [1:0]\ui_rd_data0/p_82_out ; wire [1:0]\ui_rd_data0/p_83_out ; wire [1:0]\ui_rd_data0/p_84_out ; wire [1:0]\ui_rd_data0/p_85_out ; wire [1:0]\ui_rd_data0/p_86_out ; wire [1:0]\ui_rd_data0/p_87_out ; wire [1:0]\ui_rd_data0/p_88_out ; wire [1:0]\ui_rd_data0/p_89_out ; wire [1:0]\ui_rd_data0/p_8_out ; wire [1:0]\ui_rd_data0/p_90_out ; wire [1:0]\ui_rd_data0/p_91_out ; wire [1:0]\ui_rd_data0/p_92_out ; wire [1:0]\ui_rd_data0/p_93_out ; wire [1:0]\ui_rd_data0/p_94_out ; wire [1:0]\ui_rd_data0/p_95_out ; wire [1:0]\ui_rd_data0/p_96_out ; wire [1:0]\ui_rd_data0/p_97_out ; wire [1:0]\ui_rd_data0/p_98_out ; wire [1:0]\ui_rd_data0/p_99_out ; wire [1:0]\ui_rd_data0/p_9_out ; wire \ui_rd_data0/rd_buf_we ; wire [1:1]\ui_rd_data0/rd_status ; wire \ui_wr_data0/pointer_we ; wire use_addr; wire w_cmd_rdy; wire [255:0]wr_data; wire [3:0]wr_data_addr; wire wr_data_en; wire [31:0]wr_data_mask; wire wr_en; wire wr_en_5; wire wr_en_6; wire [3:0]\wr_ptr_timing_reg[2] ; wire [3:0]\wr_ptr_timing_reg[2]_0 ; FDRE init_calib_complete_r_reg (.C(CLK), .CE(1'b1), .D(mem_intfc0_n_77), .Q(init_calib_complete_r), .R(1'b0)); ddr3_if_mig_7series_v4_0_mem_intfc mem_intfc0 (.CLK(CLK), .CLKB0(CLKB0), .CLKB0_7(CLKB0_7), .CLKB0_8(CLKB0_8), .CLKB0_9(CLKB0_9), .D(D), .DOA(\ui_rd_data0/p_129_out ), .DOB(\ui_rd_data0/p_128_out ), .DOC(\ui_rd_data0/p_127_out ), .E(wr_data_en), .Q({wr_data_mask,wr_data}), .RST0(RST0), .SR(SR), .SS(SS), .accept_ns(accept_ns), .act_wait_r_lcl_reg(pass_open_bank_r), .act_wait_r_lcl_reg_0(pass_open_bank_r_1), .act_wait_r_lcl_reg_1(pass_open_bank_r_3), .act_wait_r_lcl_reg_2(pass_open_bank_r_5), .\app_addr_r1_reg[12] (bank), .\app_addr_r1_reg[27] (row), .\app_addr_r1_reg[9] (col), .\app_cmd_r1_reg[0] (u_ui_top_n_269), .\app_cmd_r2_reg[1] (cmd), .app_hi_pri_r2(\ui_cmd0/app_hi_pri_r2 ), .app_rd_data_end_ns(\ui_rd_data0/app_rd_data_end_ns ), .app_ref_ack(app_ref_ack), .app_ref_req(app_ref_req), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_req(app_zq_req), .bm_end_r1(bm_end_r1), .bm_end_r1_0(bm_end_r1_0), .bm_end_r1_4(bm_end_r1_4), .bm_end_r1_reg(bm_end_r1_reg), .bm_end_r1_reg_0(bm_end_r1_reg_0), .bm_end_r1_reg_1(bm_end_r1_reg_1), .bm_end_r1_reg_2(bm_end_r1_reg_2), .bypass__0(\ui_rd_data0/bypass__0 ), .\calib_seq_reg[0] (phy_mc_go), .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0), .\complex_row_cnt_ocal_reg[0] (\complex_row_cnt_ocal_reg[0] ), .ddr3_addr(ddr3_addr), .ddr3_ba(ddr3_ba), .ddr3_cas_n(ddr3_cas_n), .ddr3_cke(ddr3_cke), .ddr3_cs_n(ddr3_cs_n), .ddr3_dm(ddr3_dm), .ddr3_dq(ddr3_dq), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_odt(ddr3_odt), .ddr3_ras_n(ddr3_ras_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_we_n(ddr3_we_n), .ddr_ck_out(ddr_ck_out), .\device_temp_r_reg[11] (\device_temp_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ), .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ), .dqs_po_en_stg2_f_reg(po_cnt_dec), .\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\en_cnt_div4.enable_wrlvl_cnt_reg[3] ), .fine_adjust_reg(fine_adjust_reg), .freq_refclk(freq_refclk), .hi_priority(hi_priority), .in0(in0), .init_calib_complete_r_reg(mem_intfc0_n_77), .mem_out(mem_out), .mem_refclk(mem_refclk), .\mmcm_current_reg[0] (\mmcm_current_reg[0] ), .\mmcm_init_trail_reg[0] (\mmcm_init_trail_reg[0] ), .mmcm_locked(mmcm_locked), .mmcm_ps_clk(mmcm_ps_clk), .\not_strict_mode.app_rd_data_end_reg ({rd_data_end,rd_data_addr,rd_data_offset}), .\not_strict_mode.app_rd_data_reg[0] (mem_intfc0_n_397), .\not_strict_mode.app_rd_data_reg[100] (mem_intfc0_n_285), .\not_strict_mode.app_rd_data_reg[101] (mem_intfc0_n_281), .\not_strict_mode.app_rd_data_reg[102] (mem_intfc0_n_277), .\not_strict_mode.app_rd_data_reg[103] (mem_intfc0_n_273), .\not_strict_mode.app_rd_data_reg[104] (mem_intfc0_n_299), .\not_strict_mode.app_rd_data_reg[105] (mem_intfc0_n_295), .\not_strict_mode.app_rd_data_reg[106] (mem_intfc0_n_291), .\not_strict_mode.app_rd_data_reg[107] (mem_intfc0_n_287), .\not_strict_mode.app_rd_data_reg[108] (mem_intfc0_n_283), .\not_strict_mode.app_rd_data_reg[109] (mem_intfc0_n_279), .\not_strict_mode.app_rd_data_reg[10] (mem_intfc0_n_387), .\not_strict_mode.app_rd_data_reg[110] (mem_intfc0_n_275), .\not_strict_mode.app_rd_data_reg[111] (mem_intfc0_n_271), .\not_strict_mode.app_rd_data_reg[112] (mem_intfc0_n_300), .\not_strict_mode.app_rd_data_reg[113] (mem_intfc0_n_296), .\not_strict_mode.app_rd_data_reg[114] (mem_intfc0_n_292), .\not_strict_mode.app_rd_data_reg[115] (mem_intfc0_n_288), .\not_strict_mode.app_rd_data_reg[116] (mem_intfc0_n_284), .\not_strict_mode.app_rd_data_reg[117] (mem_intfc0_n_280), .\not_strict_mode.app_rd_data_reg[118] (mem_intfc0_n_276), .\not_strict_mode.app_rd_data_reg[119] (mem_intfc0_n_272), .\not_strict_mode.app_rd_data_reg[11] (mem_intfc0_n_383), .\not_strict_mode.app_rd_data_reg[120] (mem_intfc0_n_298), .\not_strict_mode.app_rd_data_reg[121] (mem_intfc0_n_294), .\not_strict_mode.app_rd_data_reg[122] (mem_intfc0_n_290), .\not_strict_mode.app_rd_data_reg[123] (mem_intfc0_n_286), .\not_strict_mode.app_rd_data_reg[124] (mem_intfc0_n_282), .\not_strict_mode.app_rd_data_reg[125] (mem_intfc0_n_278), .\not_strict_mode.app_rd_data_reg[126] (mem_intfc0_n_274), .\not_strict_mode.app_rd_data_reg[127] (mem_intfc0_n_270), .\not_strict_mode.app_rd_data_reg[128] (mem_intfc0_n_269), .\not_strict_mode.app_rd_data_reg[129] (mem_intfc0_n_265), .\not_strict_mode.app_rd_data_reg[12] (mem_intfc0_n_379), .\not_strict_mode.app_rd_data_reg[130] (mem_intfc0_n_261), .\not_strict_mode.app_rd_data_reg[131] (mem_intfc0_n_257), .\not_strict_mode.app_rd_data_reg[132] (mem_intfc0_n_253), .\not_strict_mode.app_rd_data_reg[133] (mem_intfc0_n_249), .\not_strict_mode.app_rd_data_reg[134] (mem_intfc0_n_245), .\not_strict_mode.app_rd_data_reg[135] (mem_intfc0_n_241), .\not_strict_mode.app_rd_data_reg[136] (mem_intfc0_n_267), .\not_strict_mode.app_rd_data_reg[137] (mem_intfc0_n_263), .\not_strict_mode.app_rd_data_reg[138] (mem_intfc0_n_259), .\not_strict_mode.app_rd_data_reg[139] (mem_intfc0_n_255), .\not_strict_mode.app_rd_data_reg[13] (mem_intfc0_n_375), .\not_strict_mode.app_rd_data_reg[140] (mem_intfc0_n_251), .\not_strict_mode.app_rd_data_reg[141] (mem_intfc0_n_247), .\not_strict_mode.app_rd_data_reg[142] (mem_intfc0_n_243), .\not_strict_mode.app_rd_data_reg[143] (mem_intfc0_n_239), .\not_strict_mode.app_rd_data_reg[144] (mem_intfc0_n_268), .\not_strict_mode.app_rd_data_reg[145] (mem_intfc0_n_264), .\not_strict_mode.app_rd_data_reg[146] (mem_intfc0_n_260), .\not_strict_mode.app_rd_data_reg[147] (mem_intfc0_n_256), .\not_strict_mode.app_rd_data_reg[148] (mem_intfc0_n_252), .\not_strict_mode.app_rd_data_reg[149] (mem_intfc0_n_248), .\not_strict_mode.app_rd_data_reg[14] (mem_intfc0_n_371), .\not_strict_mode.app_rd_data_reg[150] (mem_intfc0_n_244), .\not_strict_mode.app_rd_data_reg[151] (mem_intfc0_n_240), .\not_strict_mode.app_rd_data_reg[152] (mem_intfc0_n_266), .\not_strict_mode.app_rd_data_reg[153] (mem_intfc0_n_262), .\not_strict_mode.app_rd_data_reg[154] (mem_intfc0_n_258), .\not_strict_mode.app_rd_data_reg[155] (mem_intfc0_n_254), .\not_strict_mode.app_rd_data_reg[156] (mem_intfc0_n_250), .\not_strict_mode.app_rd_data_reg[157] (mem_intfc0_n_246), .\not_strict_mode.app_rd_data_reg[158] (mem_intfc0_n_242), .\not_strict_mode.app_rd_data_reg[159] (mem_intfc0_n_238), .\not_strict_mode.app_rd_data_reg[15] (mem_intfc0_n_367), .\not_strict_mode.app_rd_data_reg[160] (mem_intfc0_n_237), .\not_strict_mode.app_rd_data_reg[161] (mem_intfc0_n_233), .\not_strict_mode.app_rd_data_reg[162] (mem_intfc0_n_229), .\not_strict_mode.app_rd_data_reg[163] (mem_intfc0_n_225), .\not_strict_mode.app_rd_data_reg[164] (mem_intfc0_n_221), .\not_strict_mode.app_rd_data_reg[165] (mem_intfc0_n_217), .\not_strict_mode.app_rd_data_reg[166] (mem_intfc0_n_213), .\not_strict_mode.app_rd_data_reg[167] (mem_intfc0_n_209), .\not_strict_mode.app_rd_data_reg[168] (mem_intfc0_n_235), .\not_strict_mode.app_rd_data_reg[169] (mem_intfc0_n_231), .\not_strict_mode.app_rd_data_reg[16] (mem_intfc0_n_396), .\not_strict_mode.app_rd_data_reg[170] (mem_intfc0_n_227), .\not_strict_mode.app_rd_data_reg[171] (mem_intfc0_n_223), .\not_strict_mode.app_rd_data_reg[172] (mem_intfc0_n_219), .\not_strict_mode.app_rd_data_reg[173] (mem_intfc0_n_215), .\not_strict_mode.app_rd_data_reg[174] (mem_intfc0_n_211), .\not_strict_mode.app_rd_data_reg[175] (mem_intfc0_n_207), .\not_strict_mode.app_rd_data_reg[176] (mem_intfc0_n_236), .\not_strict_mode.app_rd_data_reg[177] (mem_intfc0_n_232), .\not_strict_mode.app_rd_data_reg[178] (mem_intfc0_n_228), .\not_strict_mode.app_rd_data_reg[179] (mem_intfc0_n_224), .\not_strict_mode.app_rd_data_reg[17] (mem_intfc0_n_392), .\not_strict_mode.app_rd_data_reg[180] (mem_intfc0_n_220), .\not_strict_mode.app_rd_data_reg[181] (mem_intfc0_n_216), .\not_strict_mode.app_rd_data_reg[182] (mem_intfc0_n_212), .\not_strict_mode.app_rd_data_reg[183] (mem_intfc0_n_208), .\not_strict_mode.app_rd_data_reg[184] (mem_intfc0_n_234), .\not_strict_mode.app_rd_data_reg[185] (mem_intfc0_n_230), .\not_strict_mode.app_rd_data_reg[186] (mem_intfc0_n_226), .\not_strict_mode.app_rd_data_reg[187] (mem_intfc0_n_222), .\not_strict_mode.app_rd_data_reg[188] (mem_intfc0_n_218), .\not_strict_mode.app_rd_data_reg[189] (mem_intfc0_n_214), .\not_strict_mode.app_rd_data_reg[18] (mem_intfc0_n_388), .\not_strict_mode.app_rd_data_reg[190] (mem_intfc0_n_210), .\not_strict_mode.app_rd_data_reg[191] (mem_intfc0_n_206), .\not_strict_mode.app_rd_data_reg[192] (mem_intfc0_n_205), .\not_strict_mode.app_rd_data_reg[193] (mem_intfc0_n_201), .\not_strict_mode.app_rd_data_reg[194] (mem_intfc0_n_197), .\not_strict_mode.app_rd_data_reg[195] (mem_intfc0_n_193), .\not_strict_mode.app_rd_data_reg[196] (mem_intfc0_n_189), .\not_strict_mode.app_rd_data_reg[197] (mem_intfc0_n_185), .\not_strict_mode.app_rd_data_reg[198] (mem_intfc0_n_181), .\not_strict_mode.app_rd_data_reg[199] (mem_intfc0_n_177), .\not_strict_mode.app_rd_data_reg[19] (mem_intfc0_n_384), .\not_strict_mode.app_rd_data_reg[1] (mem_intfc0_n_393), .\not_strict_mode.app_rd_data_reg[200] (mem_intfc0_n_203), .\not_strict_mode.app_rd_data_reg[201] (mem_intfc0_n_199), .\not_strict_mode.app_rd_data_reg[202] (mem_intfc0_n_195), .\not_strict_mode.app_rd_data_reg[203] (mem_intfc0_n_191), .\not_strict_mode.app_rd_data_reg[204] (mem_intfc0_n_187), .\not_strict_mode.app_rd_data_reg[205] (mem_intfc0_n_183), .\not_strict_mode.app_rd_data_reg[206] (mem_intfc0_n_179), .\not_strict_mode.app_rd_data_reg[207] (mem_intfc0_n_175), .\not_strict_mode.app_rd_data_reg[208] (mem_intfc0_n_204), .\not_strict_mode.app_rd_data_reg[209] (mem_intfc0_n_200), .\not_strict_mode.app_rd_data_reg[20] (mem_intfc0_n_380), .\not_strict_mode.app_rd_data_reg[210] (mem_intfc0_n_196), .\not_strict_mode.app_rd_data_reg[211] (mem_intfc0_n_192), .\not_strict_mode.app_rd_data_reg[212] (mem_intfc0_n_188), .\not_strict_mode.app_rd_data_reg[213] (mem_intfc0_n_184), .\not_strict_mode.app_rd_data_reg[214] (mem_intfc0_n_180), .\not_strict_mode.app_rd_data_reg[215] (mem_intfc0_n_176), .\not_strict_mode.app_rd_data_reg[216] (mem_intfc0_n_202), .\not_strict_mode.app_rd_data_reg[217] (mem_intfc0_n_198), .\not_strict_mode.app_rd_data_reg[218] (mem_intfc0_n_194), .\not_strict_mode.app_rd_data_reg[219] (mem_intfc0_n_190), .\not_strict_mode.app_rd_data_reg[21] (mem_intfc0_n_376), .\not_strict_mode.app_rd_data_reg[220] (mem_intfc0_n_186), .\not_strict_mode.app_rd_data_reg[221] (mem_intfc0_n_182), .\not_strict_mode.app_rd_data_reg[222] (mem_intfc0_n_178), .\not_strict_mode.app_rd_data_reg[223] (mem_intfc0_n_174), .\not_strict_mode.app_rd_data_reg[224] (mem_intfc0_n_173), .\not_strict_mode.app_rd_data_reg[225] (mem_intfc0_n_169), .\not_strict_mode.app_rd_data_reg[226] (mem_intfc0_n_165), .\not_strict_mode.app_rd_data_reg[227] (mem_intfc0_n_161), .\not_strict_mode.app_rd_data_reg[228] (mem_intfc0_n_157), .\not_strict_mode.app_rd_data_reg[229] (mem_intfc0_n_153), .\not_strict_mode.app_rd_data_reg[22] (mem_intfc0_n_372), .\not_strict_mode.app_rd_data_reg[230] (mem_intfc0_n_149), .\not_strict_mode.app_rd_data_reg[231] (mem_intfc0_n_145), .\not_strict_mode.app_rd_data_reg[232] (mem_intfc0_n_171), .\not_strict_mode.app_rd_data_reg[233] (mem_intfc0_n_167), .\not_strict_mode.app_rd_data_reg[234] (mem_intfc0_n_163), .\not_strict_mode.app_rd_data_reg[235] (mem_intfc0_n_159), .\not_strict_mode.app_rd_data_reg[236] (mem_intfc0_n_155), .\not_strict_mode.app_rd_data_reg[237] (mem_intfc0_n_151), .\not_strict_mode.app_rd_data_reg[238] (mem_intfc0_n_147), .\not_strict_mode.app_rd_data_reg[239] (mem_intfc0_n_143), .\not_strict_mode.app_rd_data_reg[23] (mem_intfc0_n_368), .\not_strict_mode.app_rd_data_reg[240] (mem_intfc0_n_172), .\not_strict_mode.app_rd_data_reg[241] (mem_intfc0_n_168), .\not_strict_mode.app_rd_data_reg[242] (mem_intfc0_n_164), .\not_strict_mode.app_rd_data_reg[243] (mem_intfc0_n_160), .\not_strict_mode.app_rd_data_reg[244] (mem_intfc0_n_156), .\not_strict_mode.app_rd_data_reg[245] (mem_intfc0_n_152), .\not_strict_mode.app_rd_data_reg[246] (mem_intfc0_n_148), .\not_strict_mode.app_rd_data_reg[247] (mem_intfc0_n_144), .\not_strict_mode.app_rd_data_reg[248] (mem_intfc0_n_170), .\not_strict_mode.app_rd_data_reg[249] (mem_intfc0_n_166), .\not_strict_mode.app_rd_data_reg[24] (mem_intfc0_n_394), .\not_strict_mode.app_rd_data_reg[250] (mem_intfc0_n_162), .\not_strict_mode.app_rd_data_reg[251] (mem_intfc0_n_158), .\not_strict_mode.app_rd_data_reg[252] (mem_intfc0_n_154), .\not_strict_mode.app_rd_data_reg[253] (mem_intfc0_n_150), .\not_strict_mode.app_rd_data_reg[254] (mem_intfc0_n_146), .\not_strict_mode.app_rd_data_reg[255] (mem_intfc0_n_142), .\not_strict_mode.app_rd_data_reg[255]_0 (app_rd_data_ns), .\not_strict_mode.app_rd_data_reg[25] (mem_intfc0_n_390), .\not_strict_mode.app_rd_data_reg[26] (mem_intfc0_n_386), .\not_strict_mode.app_rd_data_reg[27] (mem_intfc0_n_382), .\not_strict_mode.app_rd_data_reg[28] (mem_intfc0_n_378), .\not_strict_mode.app_rd_data_reg[29] (mem_intfc0_n_374), .\not_strict_mode.app_rd_data_reg[2] (mem_intfc0_n_389), .\not_strict_mode.app_rd_data_reg[30] (mem_intfc0_n_370), .\not_strict_mode.app_rd_data_reg[31] (mem_intfc0_n_366), .\not_strict_mode.app_rd_data_reg[32] (mem_intfc0_n_365), .\not_strict_mode.app_rd_data_reg[33] (mem_intfc0_n_361), .\not_strict_mode.app_rd_data_reg[34] (mem_intfc0_n_357), .\not_strict_mode.app_rd_data_reg[35] (mem_intfc0_n_353), .\not_strict_mode.app_rd_data_reg[36] (mem_intfc0_n_349), .\not_strict_mode.app_rd_data_reg[37] (mem_intfc0_n_345), .\not_strict_mode.app_rd_data_reg[38] (mem_intfc0_n_341), .\not_strict_mode.app_rd_data_reg[39] (mem_intfc0_n_337), .\not_strict_mode.app_rd_data_reg[3] (mem_intfc0_n_385), .\not_strict_mode.app_rd_data_reg[40] (mem_intfc0_n_363), .\not_strict_mode.app_rd_data_reg[41] (mem_intfc0_n_359), .\not_strict_mode.app_rd_data_reg[42] (mem_intfc0_n_355), .\not_strict_mode.app_rd_data_reg[43] (mem_intfc0_n_351), .\not_strict_mode.app_rd_data_reg[44] (mem_intfc0_n_347), .\not_strict_mode.app_rd_data_reg[45] (mem_intfc0_n_343), .\not_strict_mode.app_rd_data_reg[46] (mem_intfc0_n_339), .\not_strict_mode.app_rd_data_reg[47] (mem_intfc0_n_335), .\not_strict_mode.app_rd_data_reg[48] (mem_intfc0_n_364), .\not_strict_mode.app_rd_data_reg[49] (mem_intfc0_n_360), .\not_strict_mode.app_rd_data_reg[4] (mem_intfc0_n_381), .\not_strict_mode.app_rd_data_reg[50] (mem_intfc0_n_356), .\not_strict_mode.app_rd_data_reg[51] (mem_intfc0_n_352), .\not_strict_mode.app_rd_data_reg[52] (mem_intfc0_n_348), .\not_strict_mode.app_rd_data_reg[53] (mem_intfc0_n_344), .\not_strict_mode.app_rd_data_reg[54] (mem_intfc0_n_340), .\not_strict_mode.app_rd_data_reg[55] (mem_intfc0_n_336), .\not_strict_mode.app_rd_data_reg[56] (mem_intfc0_n_362), .\not_strict_mode.app_rd_data_reg[57] (mem_intfc0_n_358), .\not_strict_mode.app_rd_data_reg[58] (mem_intfc0_n_354), .\not_strict_mode.app_rd_data_reg[59] (mem_intfc0_n_350), .\not_strict_mode.app_rd_data_reg[5] (mem_intfc0_n_377), .\not_strict_mode.app_rd_data_reg[60] (mem_intfc0_n_346), .\not_strict_mode.app_rd_data_reg[61] (mem_intfc0_n_342), .\not_strict_mode.app_rd_data_reg[62] (mem_intfc0_n_338), .\not_strict_mode.app_rd_data_reg[63] (mem_intfc0_n_334), .\not_strict_mode.app_rd_data_reg[64] (mem_intfc0_n_333), .\not_strict_mode.app_rd_data_reg[65] (mem_intfc0_n_329), .\not_strict_mode.app_rd_data_reg[66] (mem_intfc0_n_325), .\not_strict_mode.app_rd_data_reg[67] (mem_intfc0_n_321), .\not_strict_mode.app_rd_data_reg[68] (mem_intfc0_n_317), .\not_strict_mode.app_rd_data_reg[69] (mem_intfc0_n_313), .\not_strict_mode.app_rd_data_reg[6] (mem_intfc0_n_373), .\not_strict_mode.app_rd_data_reg[70] (mem_intfc0_n_309), .\not_strict_mode.app_rd_data_reg[71] (mem_intfc0_n_305), .\not_strict_mode.app_rd_data_reg[72] (mem_intfc0_n_331), .\not_strict_mode.app_rd_data_reg[73] (mem_intfc0_n_327), .\not_strict_mode.app_rd_data_reg[74] (mem_intfc0_n_323), .\not_strict_mode.app_rd_data_reg[75] (mem_intfc0_n_319), .\not_strict_mode.app_rd_data_reg[76] (mem_intfc0_n_315), .\not_strict_mode.app_rd_data_reg[77] (mem_intfc0_n_311), .\not_strict_mode.app_rd_data_reg[78] (mem_intfc0_n_307), .\not_strict_mode.app_rd_data_reg[79] (mem_intfc0_n_303), .\not_strict_mode.app_rd_data_reg[7] (mem_intfc0_n_369), .\not_strict_mode.app_rd_data_reg[80] (mem_intfc0_n_332), .\not_strict_mode.app_rd_data_reg[81] (mem_intfc0_n_328), .\not_strict_mode.app_rd_data_reg[82] (mem_intfc0_n_324), .\not_strict_mode.app_rd_data_reg[83] (mem_intfc0_n_320), .\not_strict_mode.app_rd_data_reg[84] (mem_intfc0_n_316), .\not_strict_mode.app_rd_data_reg[85] (mem_intfc0_n_312), .\not_strict_mode.app_rd_data_reg[86] (mem_intfc0_n_308), .\not_strict_mode.app_rd_data_reg[87] (mem_intfc0_n_304), .\not_strict_mode.app_rd_data_reg[88] (mem_intfc0_n_330), .\not_strict_mode.app_rd_data_reg[89] (mem_intfc0_n_326), .\not_strict_mode.app_rd_data_reg[8] (mem_intfc0_n_395), .\not_strict_mode.app_rd_data_reg[90] (mem_intfc0_n_322), .\not_strict_mode.app_rd_data_reg[91] (mem_intfc0_n_318), .\not_strict_mode.app_rd_data_reg[92] (mem_intfc0_n_314), .\not_strict_mode.app_rd_data_reg[93] (mem_intfc0_n_310), .\not_strict_mode.app_rd_data_reg[94] (mem_intfc0_n_306), .\not_strict_mode.app_rd_data_reg[95] (mem_intfc0_n_302), .\not_strict_mode.app_rd_data_reg[96] (mem_intfc0_n_301), .\not_strict_mode.app_rd_data_reg[97] (mem_intfc0_n_297), .\not_strict_mode.app_rd_data_reg[98] (mem_intfc0_n_293), .\not_strict_mode.app_rd_data_reg[99] (mem_intfc0_n_289), .\not_strict_mode.app_rd_data_reg[9] (mem_intfc0_n_391), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (data_buf_addr), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\ui_rd_data0/p_123_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\ui_rd_data0/p_124_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\ui_rd_data0/p_125_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\ui_rd_data0/p_116_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\ui_rd_data0/p_26_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\ui_rd_data0/p_21_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\ui_rd_data0/p_22_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\ui_rd_data0/p_23_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\ui_rd_data0/p_18_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\ui_rd_data0/p_19_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\ui_rd_data0/p_20_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\ui_rd_data0/p_15_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\ui_rd_data0/p_16_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\ui_rd_data0/p_17_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\ui_rd_data0/p_111_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\ui_rd_data0/p_12_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\ui_rd_data0/p_13_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\ui_rd_data0/p_14_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\ui_rd_data0/p_9_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\ui_rd_data0/p_10_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\ui_rd_data0/p_11_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\ui_rd_data0/p_6_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\ui_rd_data0/p_7_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\ui_rd_data0/p_8_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\ui_rd_data0/p_3_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\ui_rd_data0/p_112_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\ui_rd_data0/p_4_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\ui_rd_data0/p_5_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ({u_ui_top_n_260,u_ui_top_n_261}), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\ui_rd_data0/p_1_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\ui_rd_data0/p_113_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\ui_rd_data0/p_108_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\ui_rd_data0/p_109_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\ui_rd_data0/p_110_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\ui_rd_data0/p_105_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\ui_rd_data0/p_106_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\ui_rd_data0/p_107_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\ui_rd_data0/p_120_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\ui_rd_data0/p_102_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\ui_rd_data0/p_103_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\ui_rd_data0/p_104_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\ui_rd_data0/p_99_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\ui_rd_data0/p_100_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\ui_rd_data0/p_101_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\ui_rd_data0/p_96_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\ui_rd_data0/p_97_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\ui_rd_data0/p_98_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\ui_rd_data0/p_93_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\ui_rd_data0/p_121_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\ui_rd_data0/p_94_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\ui_rd_data0/p_95_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\ui_rd_data0/p_90_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\ui_rd_data0/p_91_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\ui_rd_data0/p_92_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\ui_rd_data0/p_87_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\ui_rd_data0/p_88_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\ui_rd_data0/p_89_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\ui_rd_data0/p_84_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\ui_rd_data0/p_85_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\ui_rd_data0/p_122_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\ui_rd_data0/p_86_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\ui_rd_data0/p_81_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\ui_rd_data0/p_82_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\ui_rd_data0/p_83_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\ui_rd_data0/p_78_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\ui_rd_data0/p_79_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\ui_rd_data0/p_80_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\ui_rd_data0/p_75_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\ui_rd_data0/p_76_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\ui_rd_data0/p_77_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\ui_rd_data0/p_117_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\ui_rd_data0/p_72_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\ui_rd_data0/p_73_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\ui_rd_data0/p_74_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\ui_rd_data0/p_69_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\ui_rd_data0/p_70_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\ui_rd_data0/p_71_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\ui_rd_data0/p_66_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\ui_rd_data0/p_67_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\ui_rd_data0/p_68_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\ui_rd_data0/p_63_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\ui_rd_data0/p_118_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\ui_rd_data0/p_64_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\ui_rd_data0/p_65_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\ui_rd_data0/p_60_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\ui_rd_data0/p_61_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\ui_rd_data0/p_62_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\ui_rd_data0/p_57_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\ui_rd_data0/p_58_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\ui_rd_data0/p_59_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\ui_rd_data0/p_54_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\ui_rd_data0/p_55_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\ui_rd_data0/p_119_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\ui_rd_data0/p_56_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\ui_rd_data0/p_51_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\ui_rd_data0/p_52_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\ui_rd_data0/p_53_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\ui_rd_data0/p_48_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\ui_rd_data0/p_49_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\ui_rd_data0/p_50_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\ui_rd_data0/p_45_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\ui_rd_data0/p_46_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\ui_rd_data0/p_47_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\ui_rd_data0/p_114_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\ui_rd_data0/p_42_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\ui_rd_data0/p_43_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\ui_rd_data0/p_44_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\ui_rd_data0/p_39_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\ui_rd_data0/p_40_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\ui_rd_data0/p_41_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\ui_rd_data0/p_36_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\ui_rd_data0/p_37_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\ui_rd_data0/p_38_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\ui_rd_data0/p_33_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\ui_rd_data0/p_115_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\ui_rd_data0/p_34_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\ui_rd_data0/p_35_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\ui_rd_data0/p_30_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\ui_rd_data0/p_31_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\ui_rd_data0/p_32_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\ui_rd_data0/p_27_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\ui_rd_data0/p_28_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\ui_rd_data0/p_29_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\ui_rd_data0/p_24_out ), .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\ui_rd_data0/p_25_out ), .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\ui_rd_data0/rd_status ), .p_81_in(p_81_in), .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg), .phy_dout(phy_dout), .pi_cnt_dec_reg(pi_cnt_dec_reg), .pi_en_stg2_f_timing_reg(pi_cnt_dec), .\pi_rst_stg1_cal_r_reg[0] (\pi_rst_stg1_cal_r_reg[0] ), .pll_locked(pll_locked), .po_cnt_dec_reg(po_cnt_dec_reg), .poc_sample_pd(poc_sample_pd), .pointer_we(\ui_wr_data0/pointer_we ), .psdone(psdone), .\qcntr_r_reg[0] (E), .ram_init_done_r(ram_init_done_r), .\ras_timer_r_reg[2] (bm_end_r1_2), .\rd_buf_indx.rd_buf_indx_r_reg[4] ({u_ui_top_n_1,ram_init_addr}), .rd_buf_we(\ui_rd_data0/rd_buf_we ), .\rd_ptr_reg[3] (\rd_ptr_reg[3] ), .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ), .\rd_ptr_timing_reg[0] (\rd_ptr_timing_reg[0] ), .\rd_ptr_timing_reg[0]_0 (\rd_ptr_timing_reg[0]_0 ), .\rd_ptr_timing_reg[2] (\rd_ptr_timing_reg[2] ), .\rd_ptr_timing_reg[2]_0 (\rd_ptr_timing_reg[2]_0 ), .\rd_ptr_timing_reg[2]_1 (\rd_ptr_timing_reg[2]_1 ), .\rd_ptr_timing_reg[2]_10 (\rd_ptr_timing_reg[2]_10 ), .\rd_ptr_timing_reg[2]_2 (\rd_ptr_timing_reg[2]_2 ), .\rd_ptr_timing_reg[2]_3 (\rd_ptr_timing_reg[2]_3 ), .\rd_ptr_timing_reg[2]_4 (\rd_ptr_timing_reg[2]_4 ), .\rd_ptr_timing_reg[2]_5 (\rd_ptr_timing_reg[2]_5 ), .\rd_ptr_timing_reg[2]_6 (\rd_ptr_timing_reg[2]_6 ), .\rd_ptr_timing_reg[2]_7 (\rd_ptr_timing_reg[2]_7 ), .\rd_ptr_timing_reg[2]_8 (\rd_ptr_timing_reg[2]_8 ), .\rd_ptr_timing_reg[2]_9 (\rd_ptr_timing_reg[2]_9 ), .req_bank_r(\mc0/bank_mach0/req_bank_r ), .\req_bank_r_lcl_reg[0] (u_ui_top_n_276), .\req_bank_r_lcl_reg[0]_0 (u_ui_top_n_270), .\req_bank_r_lcl_reg[2] (u_ui_top_n_274), .\req_bank_r_lcl_reg[2]_0 (u_ui_top_n_275), .\resume_wait_r_reg[5] (\resume_wait_r_reg[5] ), .\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\row_cnt_victim_rotate.complex_row_cnt_reg[4] ), .\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ), .rst_sync_r1(rst_sync_r1), .rst_sync_r1_reg(rst_sync_r1_reg), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10), .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11), .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12), .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13), .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14), .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16), .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17), .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18), .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19), .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23), .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24), .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0), .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1), .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25), .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26), .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0), .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1), .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2), .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4), .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5), .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6), .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7), .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8), .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9), .rtp_timer_ns1(rtp_timer_ns1), .rtp_timer_ns1_6(rtp_timer_ns1_6), .rtp_timer_ns1_7(rtp_timer_ns1_7), .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r), .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg), .\samps_r_reg[9] (sm_r), .\sm_r_reg[0] (\sm_r_reg[0] ), .\sm_r_reg[0]_0 (\sm_r_reg[0]_0 ), .\stg2_tap_cnt_reg[0] (\stg2_tap_cnt_reg[0] ), .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg), .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg), .\stg3_r_reg[0] (\stg3_r_reg[0] ), .sync_pulse(sync_pulse), .sys_rst(sys_rst), .use_addr(use_addr), .wr_en(wr_en), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .\wr_ptr_timing_reg[2] (Q), .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2] ), .\wr_ptr_timing_reg[2]_1 (\wr_ptr_timing_reg[2]_0 ), .\write_buffer.wr_buf_out_data_reg[287] (wr_data_addr)); (* syn_maxfan = "10" *) FDRE reset_reg (.C(CLK), .CE(1'b1), .D(rstdiv0_sync_r1_reg_rep__26), .Q(reset_reg_n_0), .R(1'b0)); ddr3_if_mig_7series_v4_0_axi_mc u_axi_mc (.CLK(CLK), .D(\axi_mc_w_channel_0/next_wdf_mask ), .E(\ui_cmd0/app_addr_r10 ), .Q(app_rd_data), .\app_addr_r1_reg[27] (app_addr), .app_en_ns1(\ui_cmd0/app_en_ns1 ), .app_en_r1(\ui_cmd0/app_en_r1 ), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .app_wdf_rdy(app_wdf_rdy), .aresetn(aresetn), .mc_app_cmd(app_cmd), .mc_app_wdf_data_reg(\axi_mc_w_channel_0/mc_app_wdf_data_reg ), .\mc_app_wdf_data_reg_reg[255] (\axi_mc_w_channel_0/next_wdf_data ), .mc_app_wdf_mask_reg(\axi_mc_w_channel_0/mc_app_wdf_mask_reg ), .mc_app_wdf_wren_reg(\axi_mc_w_channel_0/mc_app_wdf_wren_reg ), .mc_init_complete(init_calib_complete_r), .out(out), .reset_reg(reset_reg_n_0), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), .s_axi_awaddr(s_axi_awaddr), .s_axi_awburst(s_axi_awburst), .s_axi_awid(s_axi_awid), .s_axi_awlen(s_axi_awlen), .s_axi_awready(s_axi_awready), .s_axi_awvalid(s_axi_awvalid), .s_axi_bid(s_axi_bid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), .s_axi_wstrb(s_axi_wstrb), .s_axi_wvalid(s_axi_wvalid), .w_cmd_rdy(w_cmd_rdy)); ddr3_if_mig_7series_v4_0_ui_top u_ui_top (.CLK(CLK), .D(\axi_mc_w_channel_0/next_wdf_mask ), .DIA({mem_intfc0_n_377,mem_intfc0_n_381}), .DIB({mem_intfc0_n_385,mem_intfc0_n_389}), .DIC({mem_intfc0_n_393,mem_intfc0_n_397}), .DOA(\ui_rd_data0/p_129_out ), .DOB(\ui_rd_data0/p_128_out ), .DOC(\ui_rd_data0/p_127_out ), .E(wr_data_en), .Q({u_ui_top_n_1,ram_init_addr}), .accept_ns(accept_ns), .\app_cmd_r2_reg[0] (u_ui_top_n_269), .\app_cmd_r2_reg[1] (cmd), .app_en_ns1(\ui_cmd0/app_en_ns1 ), .app_en_r1(\ui_cmd0/app_en_r1 ), .app_hi_pri_r2(\ui_cmd0/app_hi_pri_r2 ), .app_rd_data_end_ns(\ui_rd_data0/app_rd_data_end_ns ), .app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .app_rdy_r_reg(\ui_cmd0/app_addr_r10 ), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .app_wdf_rdy(app_wdf_rdy), .\axaddr_incr_reg[29] (app_addr), .bypass__0(\ui_rd_data0/bypass__0 ), .\cmd_pipe_plus.wr_data_addr_reg[3] (wr_data_addr), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ({mem_intfc0_n_366,mem_intfc0_n_370}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ({mem_intfc0_n_305,mem_intfc0_n_309}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ({mem_intfc0_n_303,mem_intfc0_n_307}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ({mem_intfc0_n_304,mem_intfc0_n_308}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ({mem_intfc0_n_273,mem_intfc0_n_277}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ({mem_intfc0_n_271,mem_intfc0_n_275}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ({mem_intfc0_n_272,mem_intfc0_n_276}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ({mem_intfc0_n_241,mem_intfc0_n_245}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ({mem_intfc0_n_239,mem_intfc0_n_243}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ({mem_intfc0_n_240,mem_intfc0_n_244}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ({mem_intfc0_n_209,mem_intfc0_n_213}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ({mem_intfc0_n_207,mem_intfc0_n_211}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ({mem_intfc0_n_208,mem_intfc0_n_212}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ({mem_intfc0_n_177,mem_intfc0_n_181}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ({mem_intfc0_n_175,mem_intfc0_n_179}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ({mem_intfc0_n_176,mem_intfc0_n_180}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ({mem_intfc0_n_145,mem_intfc0_n_149}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ({mem_intfc0_n_143,mem_intfc0_n_147}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ({mem_intfc0_n_144,mem_intfc0_n_148}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ({mem_intfc0_n_374,mem_intfc0_n_378}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ({mem_intfc0_n_342,mem_intfc0_n_346}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ({mem_intfc0_n_310,mem_intfc0_n_314}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ({mem_intfc0_n_278,mem_intfc0_n_282}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ({mem_intfc0_n_334,mem_intfc0_n_338}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ({mem_intfc0_n_246,mem_intfc0_n_250}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ({mem_intfc0_n_214,mem_intfc0_n_218}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ({mem_intfc0_n_182,mem_intfc0_n_186}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ({mem_intfc0_n_150,mem_intfc0_n_154}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ({mem_intfc0_n_375,mem_intfc0_n_379}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ({mem_intfc0_n_376,mem_intfc0_n_380}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ({mem_intfc0_n_345,mem_intfc0_n_349}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ({mem_intfc0_n_343,mem_intfc0_n_347}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ({mem_intfc0_n_344,mem_intfc0_n_348}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ({mem_intfc0_n_313,mem_intfc0_n_317}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ({mem_intfc0_n_311,mem_intfc0_n_315}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ({mem_intfc0_n_312,mem_intfc0_n_316}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ({mem_intfc0_n_281,mem_intfc0_n_285}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ({mem_intfc0_n_279,mem_intfc0_n_283}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ({mem_intfc0_n_280,mem_intfc0_n_284}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ({mem_intfc0_n_249,mem_intfc0_n_253}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ({mem_intfc0_n_247,mem_intfc0_n_251}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ({mem_intfc0_n_248,mem_intfc0_n_252}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ({mem_intfc0_n_217,mem_intfc0_n_221}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ({mem_intfc0_n_215,mem_intfc0_n_219}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ({mem_intfc0_n_216,mem_intfc0_n_220}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ({mem_intfc0_n_302,mem_intfc0_n_306}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ({mem_intfc0_n_185,mem_intfc0_n_189}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ({mem_intfc0_n_183,mem_intfc0_n_187}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ({mem_intfc0_n_184,mem_intfc0_n_188}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ({mem_intfc0_n_153,mem_intfc0_n_157}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ({mem_intfc0_n_151,mem_intfc0_n_155}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ({mem_intfc0_n_152,mem_intfc0_n_156}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ({mem_intfc0_n_382,mem_intfc0_n_386}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ({mem_intfc0_n_350,mem_intfc0_n_354}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ({mem_intfc0_n_318,mem_intfc0_n_322}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ({mem_intfc0_n_286,mem_intfc0_n_290}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ({mem_intfc0_n_254,mem_intfc0_n_258}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ({mem_intfc0_n_222,mem_intfc0_n_226}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ({mem_intfc0_n_190,mem_intfc0_n_194}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ({mem_intfc0_n_158,mem_intfc0_n_162}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ({mem_intfc0_n_270,mem_intfc0_n_274}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ({mem_intfc0_n_383,mem_intfc0_n_387}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ({mem_intfc0_n_384,mem_intfc0_n_388}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ({mem_intfc0_n_353,mem_intfc0_n_357}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ({mem_intfc0_n_351,mem_intfc0_n_355}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ({mem_intfc0_n_352,mem_intfc0_n_356}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ({mem_intfc0_n_321,mem_intfc0_n_325}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ({mem_intfc0_n_319,mem_intfc0_n_323}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ({mem_intfc0_n_320,mem_intfc0_n_324}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ({mem_intfc0_n_289,mem_intfc0_n_293}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ({mem_intfc0_n_287,mem_intfc0_n_291}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ({mem_intfc0_n_288,mem_intfc0_n_292}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ({mem_intfc0_n_257,mem_intfc0_n_261}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ({mem_intfc0_n_255,mem_intfc0_n_259}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ({mem_intfc0_n_256,mem_intfc0_n_260}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ({mem_intfc0_n_225,mem_intfc0_n_229}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ({mem_intfc0_n_223,mem_intfc0_n_227}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ({mem_intfc0_n_224,mem_intfc0_n_228}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ({mem_intfc0_n_193,mem_intfc0_n_197}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ({mem_intfc0_n_191,mem_intfc0_n_195}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ({mem_intfc0_n_192,mem_intfc0_n_196}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ({mem_intfc0_n_161,mem_intfc0_n_165}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ({mem_intfc0_n_159,mem_intfc0_n_163}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ({mem_intfc0_n_160,mem_intfc0_n_164}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ({mem_intfc0_n_390,mem_intfc0_n_394}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ({mem_intfc0_n_358,mem_intfc0_n_362}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ({mem_intfc0_n_238,mem_intfc0_n_242}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ({mem_intfc0_n_326,mem_intfc0_n_330}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ({mem_intfc0_n_294,mem_intfc0_n_298}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ({mem_intfc0_n_262,mem_intfc0_n_266}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ({mem_intfc0_n_230,mem_intfc0_n_234}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ({mem_intfc0_n_198,mem_intfc0_n_202}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ({mem_intfc0_n_166,mem_intfc0_n_170}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ({mem_intfc0_n_391,mem_intfc0_n_395}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ({mem_intfc0_n_392,mem_intfc0_n_396}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ({mem_intfc0_n_361,mem_intfc0_n_365}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ({mem_intfc0_n_359,mem_intfc0_n_363}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ({mem_intfc0_n_360,mem_intfc0_n_364}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ({mem_intfc0_n_329,mem_intfc0_n_333}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ({mem_intfc0_n_327,mem_intfc0_n_331}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ({mem_intfc0_n_328,mem_intfc0_n_332}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ({mem_intfc0_n_297,mem_intfc0_n_301}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ({mem_intfc0_n_295,mem_intfc0_n_299}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ({mem_intfc0_n_296,mem_intfc0_n_300}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ({mem_intfc0_n_206,mem_intfc0_n_210}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ({mem_intfc0_n_265,mem_intfc0_n_269}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ({mem_intfc0_n_263,mem_intfc0_n_267}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ({mem_intfc0_n_264,mem_intfc0_n_268}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ({mem_intfc0_n_233,mem_intfc0_n_237}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ({mem_intfc0_n_231,mem_intfc0_n_235}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ({mem_intfc0_n_232,mem_intfc0_n_236}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ({mem_intfc0_n_201,mem_intfc0_n_205}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ({mem_intfc0_n_199,mem_intfc0_n_203}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ({mem_intfc0_n_200,mem_intfc0_n_204}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ({mem_intfc0_n_169,mem_intfc0_n_173}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ({mem_intfc0_n_167,mem_intfc0_n_171}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ({mem_intfc0_n_168,mem_intfc0_n_172}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ({mem_intfc0_n_174,mem_intfc0_n_178}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ({mem_intfc0_n_142,mem_intfc0_n_146}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (app_rd_data_ns), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ({mem_intfc0_n_369,mem_intfc0_n_373}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ({mem_intfc0_n_367,mem_intfc0_n_371}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ({mem_intfc0_n_368,mem_intfc0_n_372}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ({mem_intfc0_n_337,mem_intfc0_n_341}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ({mem_intfc0_n_335,mem_intfc0_n_339}), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ({mem_intfc0_n_336,mem_intfc0_n_340}), .hi_priority(hi_priority), .mc_app_cmd(app_cmd), .mc_app_wdf_data_reg(\axi_mc_w_channel_0/mc_app_wdf_data_reg ), .mc_app_wdf_mask_reg(\axi_mc_w_channel_0/mc_app_wdf_mask_reg ), .mc_app_wdf_wren_reg(\axi_mc_w_channel_0/mc_app_wdf_wren_reg ), .\my_empty_reg[7] ({wr_data_mask,wr_data}), .\not_strict_mode.app_rd_data_end_reg (\ui_rd_data0/rd_status ), .\not_strict_mode.app_rd_data_reg[101] (\ui_rd_data0/p_80_out ), .\not_strict_mode.app_rd_data_reg[103] (\ui_rd_data0/p_75_out ), .\not_strict_mode.app_rd_data_reg[105] (\ui_rd_data0/p_76_out ), .\not_strict_mode.app_rd_data_reg[107] (\ui_rd_data0/p_77_out ), .\not_strict_mode.app_rd_data_reg[109] (\ui_rd_data0/p_72_out ), .\not_strict_mode.app_rd_data_reg[111] (\ui_rd_data0/p_73_out ), .\not_strict_mode.app_rd_data_reg[113] (\ui_rd_data0/p_74_out ), .\not_strict_mode.app_rd_data_reg[115] (\ui_rd_data0/p_69_out ), .\not_strict_mode.app_rd_data_reg[117] (\ui_rd_data0/p_70_out ), .\not_strict_mode.app_rd_data_reg[119] (\ui_rd_data0/p_71_out ), .\not_strict_mode.app_rd_data_reg[11] (\ui_rd_data0/p_125_out ), .\not_strict_mode.app_rd_data_reg[121] (\ui_rd_data0/p_66_out ), .\not_strict_mode.app_rd_data_reg[123] (\ui_rd_data0/p_67_out ), .\not_strict_mode.app_rd_data_reg[125] (\ui_rd_data0/p_68_out ), .\not_strict_mode.app_rd_data_reg[127] (\ui_rd_data0/p_63_out ), .\not_strict_mode.app_rd_data_reg[129] (\ui_rd_data0/p_64_out ), .\not_strict_mode.app_rd_data_reg[131] (\ui_rd_data0/p_65_out ), .\not_strict_mode.app_rd_data_reg[133] (\ui_rd_data0/p_60_out ), .\not_strict_mode.app_rd_data_reg[135] (\ui_rd_data0/p_61_out ), .\not_strict_mode.app_rd_data_reg[137] (\ui_rd_data0/p_62_out ), .\not_strict_mode.app_rd_data_reg[139] (\ui_rd_data0/p_57_out ), .\not_strict_mode.app_rd_data_reg[13] (\ui_rd_data0/p_120_out ), .\not_strict_mode.app_rd_data_reg[141] (\ui_rd_data0/p_58_out ), .\not_strict_mode.app_rd_data_reg[143] (\ui_rd_data0/p_59_out ), .\not_strict_mode.app_rd_data_reg[145] (\ui_rd_data0/p_54_out ), .\not_strict_mode.app_rd_data_reg[147] (\ui_rd_data0/p_55_out ), .\not_strict_mode.app_rd_data_reg[149] (\ui_rd_data0/p_56_out ), .\not_strict_mode.app_rd_data_reg[151] (\ui_rd_data0/p_51_out ), .\not_strict_mode.app_rd_data_reg[153] (\ui_rd_data0/p_52_out ), .\not_strict_mode.app_rd_data_reg[155] (\ui_rd_data0/p_53_out ), .\not_strict_mode.app_rd_data_reg[157] (\ui_rd_data0/p_48_out ), .\not_strict_mode.app_rd_data_reg[159] (\ui_rd_data0/p_49_out ), .\not_strict_mode.app_rd_data_reg[15] (\ui_rd_data0/p_121_out ), .\not_strict_mode.app_rd_data_reg[161] (\ui_rd_data0/p_50_out ), .\not_strict_mode.app_rd_data_reg[163] (\ui_rd_data0/p_45_out ), .\not_strict_mode.app_rd_data_reg[165] (\ui_rd_data0/p_46_out ), .\not_strict_mode.app_rd_data_reg[167] (\ui_rd_data0/p_47_out ), .\not_strict_mode.app_rd_data_reg[169] (\ui_rd_data0/p_42_out ), .\not_strict_mode.app_rd_data_reg[171] (\ui_rd_data0/p_43_out ), .\not_strict_mode.app_rd_data_reg[173] (\ui_rd_data0/p_44_out ), .\not_strict_mode.app_rd_data_reg[175] (\ui_rd_data0/p_39_out ), .\not_strict_mode.app_rd_data_reg[177] (\ui_rd_data0/p_40_out ), .\not_strict_mode.app_rd_data_reg[179] (\ui_rd_data0/p_41_out ), .\not_strict_mode.app_rd_data_reg[17] (\ui_rd_data0/p_122_out ), .\not_strict_mode.app_rd_data_reg[181] (\ui_rd_data0/p_36_out ), .\not_strict_mode.app_rd_data_reg[183] (\ui_rd_data0/p_37_out ), .\not_strict_mode.app_rd_data_reg[185] (\ui_rd_data0/p_38_out ), .\not_strict_mode.app_rd_data_reg[187] (\ui_rd_data0/p_33_out ), .\not_strict_mode.app_rd_data_reg[189] (\ui_rd_data0/p_34_out ), .\not_strict_mode.app_rd_data_reg[191] (\ui_rd_data0/p_35_out ), .\not_strict_mode.app_rd_data_reg[193] (\ui_rd_data0/p_30_out ), .\not_strict_mode.app_rd_data_reg[195] (\ui_rd_data0/p_31_out ), .\not_strict_mode.app_rd_data_reg[197] (\ui_rd_data0/p_32_out ), .\not_strict_mode.app_rd_data_reg[199] (\ui_rd_data0/p_27_out ), .\not_strict_mode.app_rd_data_reg[19] (\ui_rd_data0/p_117_out ), .\not_strict_mode.app_rd_data_reg[201] (\ui_rd_data0/p_28_out ), .\not_strict_mode.app_rd_data_reg[203] (\ui_rd_data0/p_29_out ), .\not_strict_mode.app_rd_data_reg[205] (\ui_rd_data0/p_24_out ), .\not_strict_mode.app_rd_data_reg[207] (\ui_rd_data0/p_25_out ), .\not_strict_mode.app_rd_data_reg[209] (\ui_rd_data0/p_26_out ), .\not_strict_mode.app_rd_data_reg[211] (\ui_rd_data0/p_21_out ), .\not_strict_mode.app_rd_data_reg[213] (\ui_rd_data0/p_22_out ), .\not_strict_mode.app_rd_data_reg[215] (\ui_rd_data0/p_23_out ), .\not_strict_mode.app_rd_data_reg[217] (\ui_rd_data0/p_18_out ), .\not_strict_mode.app_rd_data_reg[219] (\ui_rd_data0/p_19_out ), .\not_strict_mode.app_rd_data_reg[21] (\ui_rd_data0/p_118_out ), .\not_strict_mode.app_rd_data_reg[221] (\ui_rd_data0/p_20_out ), .\not_strict_mode.app_rd_data_reg[223] (\ui_rd_data0/p_15_out ), .\not_strict_mode.app_rd_data_reg[225] (\ui_rd_data0/p_16_out ), .\not_strict_mode.app_rd_data_reg[227] (\ui_rd_data0/p_17_out ), .\not_strict_mode.app_rd_data_reg[229] (\ui_rd_data0/p_12_out ), .\not_strict_mode.app_rd_data_reg[231] (\ui_rd_data0/p_13_out ), .\not_strict_mode.app_rd_data_reg[233] (\ui_rd_data0/p_14_out ), .\not_strict_mode.app_rd_data_reg[235] (\ui_rd_data0/p_9_out ), .\not_strict_mode.app_rd_data_reg[237] (\ui_rd_data0/p_10_out ), .\not_strict_mode.app_rd_data_reg[239] (\ui_rd_data0/p_11_out ), .\not_strict_mode.app_rd_data_reg[23] (\ui_rd_data0/p_119_out ), .\not_strict_mode.app_rd_data_reg[241] (\ui_rd_data0/p_6_out ), .\not_strict_mode.app_rd_data_reg[243] (\ui_rd_data0/p_7_out ), .\not_strict_mode.app_rd_data_reg[245] (\ui_rd_data0/p_8_out ), .\not_strict_mode.app_rd_data_reg[247] (\ui_rd_data0/p_3_out ), .\not_strict_mode.app_rd_data_reg[249] (\ui_rd_data0/p_4_out ), .\not_strict_mode.app_rd_data_reg[251] (\ui_rd_data0/p_5_out ), .\not_strict_mode.app_rd_data_reg[253] ({u_ui_top_n_260,u_ui_top_n_261}), .\not_strict_mode.app_rd_data_reg[255] (\ui_rd_data0/p_1_out ), .\not_strict_mode.app_rd_data_reg[25] (\ui_rd_data0/p_114_out ), .\not_strict_mode.app_rd_data_reg[27] (\ui_rd_data0/p_115_out ), .\not_strict_mode.app_rd_data_reg[29] (\ui_rd_data0/p_116_out ), .\not_strict_mode.app_rd_data_reg[31] (\ui_rd_data0/p_111_out ), .\not_strict_mode.app_rd_data_reg[33] (\ui_rd_data0/p_112_out ), .\not_strict_mode.app_rd_data_reg[35] (\ui_rd_data0/p_113_out ), .\not_strict_mode.app_rd_data_reg[37] (\ui_rd_data0/p_108_out ), .\not_strict_mode.app_rd_data_reg[39] (\ui_rd_data0/p_109_out ), .\not_strict_mode.app_rd_data_reg[41] (\ui_rd_data0/p_110_out ), .\not_strict_mode.app_rd_data_reg[43] (\ui_rd_data0/p_105_out ), .\not_strict_mode.app_rd_data_reg[45] (\ui_rd_data0/p_106_out ), .\not_strict_mode.app_rd_data_reg[47] (\ui_rd_data0/p_107_out ), .\not_strict_mode.app_rd_data_reg[49] (\ui_rd_data0/p_102_out ), .\not_strict_mode.app_rd_data_reg[51] (\ui_rd_data0/p_103_out ), .\not_strict_mode.app_rd_data_reg[53] (\ui_rd_data0/p_104_out ), .\not_strict_mode.app_rd_data_reg[55] (\ui_rd_data0/p_99_out ), .\not_strict_mode.app_rd_data_reg[57] (\ui_rd_data0/p_100_out ), .\not_strict_mode.app_rd_data_reg[59] (\ui_rd_data0/p_101_out ), .\not_strict_mode.app_rd_data_reg[61] (\ui_rd_data0/p_96_out ), .\not_strict_mode.app_rd_data_reg[63] (\ui_rd_data0/p_97_out ), .\not_strict_mode.app_rd_data_reg[65] (\ui_rd_data0/p_98_out ), .\not_strict_mode.app_rd_data_reg[67] (\ui_rd_data0/p_93_out ), .\not_strict_mode.app_rd_data_reg[69] (\ui_rd_data0/p_94_out ), .\not_strict_mode.app_rd_data_reg[71] (\ui_rd_data0/p_95_out ), .\not_strict_mode.app_rd_data_reg[73] (\ui_rd_data0/p_90_out ), .\not_strict_mode.app_rd_data_reg[75] (\ui_rd_data0/p_91_out ), .\not_strict_mode.app_rd_data_reg[77] (\ui_rd_data0/p_92_out ), .\not_strict_mode.app_rd_data_reg[79] (\ui_rd_data0/p_87_out ), .\not_strict_mode.app_rd_data_reg[7] (\ui_rd_data0/p_123_out ), .\not_strict_mode.app_rd_data_reg[81] (\ui_rd_data0/p_88_out ), .\not_strict_mode.app_rd_data_reg[83] (\ui_rd_data0/p_89_out ), .\not_strict_mode.app_rd_data_reg[85] (\ui_rd_data0/p_84_out ), .\not_strict_mode.app_rd_data_reg[87] (\ui_rd_data0/p_85_out ), .\not_strict_mode.app_rd_data_reg[89] (\ui_rd_data0/p_86_out ), .\not_strict_mode.app_rd_data_reg[91] (\ui_rd_data0/p_81_out ), .\not_strict_mode.app_rd_data_reg[93] (\ui_rd_data0/p_82_out ), .\not_strict_mode.app_rd_data_reg[95] (\ui_rd_data0/p_83_out ), .\not_strict_mode.app_rd_data_reg[97] (\ui_rd_data0/p_78_out ), .\not_strict_mode.app_rd_data_reg[99] (\ui_rd_data0/p_79_out ), .\not_strict_mode.app_rd_data_reg[9] (\ui_rd_data0/p_124_out ), .pointer_we(\ui_wr_data0/pointer_we ), .ram_init_done_r(ram_init_done_r), .rb_hit_busy_r_reg(u_ui_top_n_270), .rb_hit_busy_r_reg_0(u_ui_top_n_274), .rb_hit_busy_r_reg_1(u_ui_top_n_275), .rb_hit_busy_r_reg_2(u_ui_top_n_276), .rd_buf_we(\ui_rd_data0/rd_buf_we ), .\read_fifo.fifo_out_data_r_reg[7] ({rd_data_end,rd_data_addr,rd_data_offset}), .req_bank_r(\mc0/bank_mach0/req_bank_r ), .\req_bank_r_lcl_reg[2] (bank), .\req_col_r_reg[9] (col), .\req_data_buf_addr_r_reg[4] (data_buf_addr), .\req_row_r_lcl_reg[14] (row), .reset_reg(reset_reg_n_0), .\s_axi_rdata[255] (app_rd_data), .use_addr(use_addr), .w_cmd_rdy(w_cmd_rdy), .wready_reg_rep__1(\axi_mc_w_channel_0/next_wdf_data )); endmodule module ddr3_if_mig_7series_v4_0_poc_edge_store (Q, \rise_trail_center_offset_r_reg[3] , E, \tap_r_reg[5] , CLK, run_polarity_r_reg, D); output [5:0]Q; output [5:0]\rise_trail_center_offset_r_reg[3] ; input [0:0]E; input [5:0]\tap_r_reg[5] ; input CLK; input [0:0]run_polarity_r_reg; input [5:0]D; wire CLK; wire [5:0]D; wire [0:0]E; wire [5:0]Q; wire [5:0]\rise_trail_center_offset_r_reg[3] ; wire [0:0]run_polarity_r_reg; wire [5:0]\tap_r_reg[5] ; FDRE \rise_lead_r_reg[0] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [0]), .Q(Q[0]), .R(1'b0)); FDRE \rise_lead_r_reg[1] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [1]), .Q(Q[1]), .R(1'b0)); FDRE \rise_lead_r_reg[2] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [2]), .Q(Q[2]), .R(1'b0)); FDRE \rise_lead_r_reg[3] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [3]), .Q(Q[3]), .R(1'b0)); FDRE \rise_lead_r_reg[4] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [4]), .Q(Q[4]), .R(1'b0)); FDRE \rise_lead_r_reg[5] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [5]), .Q(Q[5]), .R(1'b0)); FDRE \rise_trail_r_reg[0] (.C(CLK), .CE(run_polarity_r_reg), .D(D[0]), .Q(\rise_trail_center_offset_r_reg[3] [0]), .R(1'b0)); FDRE \rise_trail_r_reg[1] (.C(CLK), .CE(run_polarity_r_reg), .D(D[1]), .Q(\rise_trail_center_offset_r_reg[3] [1]), .R(1'b0)); FDRE \rise_trail_r_reg[2] (.C(CLK), .CE(run_polarity_r_reg), .D(D[2]), .Q(\rise_trail_center_offset_r_reg[3] [2]), .R(1'b0)); FDRE \rise_trail_r_reg[3] (.C(CLK), .CE(run_polarity_r_reg), .D(D[3]), .Q(\rise_trail_center_offset_r_reg[3] [3]), .R(1'b0)); FDRE \rise_trail_r_reg[4] (.C(CLK), .CE(run_polarity_r_reg), .D(D[4]), .Q(\rise_trail_center_offset_r_reg[3] [4]), .R(1'b0)); FDRE \rise_trail_r_reg[5] (.C(CLK), .CE(run_polarity_r_reg), .D(D[5]), .Q(\rise_trail_center_offset_r_reg[3] [5]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_edge_store" *) module ddr3_if_mig_7series_v4_0_poc_edge_store_10 (trailing_edge00_in, D, \center_diff_r_reg[1] , \mmcm_init_trail_reg[5] , \mmcm_init_lead_reg[5] , \center_diff_r_reg[5] , \center_diff_r_reg[3] , \center_diff_r_reg[0] , \center_diff_r_reg[0]_0 , \center_diff_r_reg[3]_0 , \center_diff_r_reg[5]_0 , Q, \tap_r_reg[5] , S, DI, \tap_r_reg[5]_0 , O, \rise_trail_r_reg[5]_0 , \rise_lead_r_reg[1]_0 , \rise_lead_r_reg[4]_0 , \rise_trail_r_reg[3]_0 , \rise_lead_r_reg[3]_0 , use_noise_window, \rise_lead_r_reg[4]_1 , \rise_lead_r_reg[5]_0 , \rise_trail_r_reg[5]_1 , E, CLK, samps_zero_r_reg, \tap_r_reg[4] ); output [4:0]trailing_edge00_in; output [2:0]D; output \center_diff_r_reg[1] ; output [5:0]\mmcm_init_trail_reg[5] ; output [5:0]\mmcm_init_lead_reg[5] ; output [0:0]\center_diff_r_reg[5] ; output [3:0]\center_diff_r_reg[3] ; output \center_diff_r_reg[0] ; output \center_diff_r_reg[0]_0 ; output [2:0]\center_diff_r_reg[3]_0 ; output [0:0]\center_diff_r_reg[5]_0 ; input [0:0]Q; input [5:0]\tap_r_reg[5] ; input [3:0]S; input [0:0]DI; input [1:0]\tap_r_reg[5]_0 ; input [2:0]O; input \rise_trail_r_reg[5]_0 ; input \rise_lead_r_reg[1]_0 ; input \rise_lead_r_reg[4]_0 ; input [2:0]\rise_trail_r_reg[3]_0 ; input [0:0]\rise_lead_r_reg[3]_0 ; input use_noise_window; input \rise_lead_r_reg[4]_1 ; input [0:0]\rise_lead_r_reg[5]_0 ; input [0:0]\rise_trail_r_reg[5]_1 ; input [0:0]E; input CLK; input [0:0]samps_zero_r_reg; input [5:0]\tap_r_reg[4] ; wire CLK; wire [2:0]D; wire [0:0]DI; wire [0:0]E; wire [2:0]O; wire [0:0]Q; wire [3:0]S; wire \center_diff_r[5]_i_13_n_0 ; wire \center_diff_r_reg[0] ; wire \center_diff_r_reg[0]_0 ; wire \center_diff_r_reg[1] ; wire [3:0]\center_diff_r_reg[3] ; wire [2:0]\center_diff_r_reg[3]_0 ; wire [0:0]\center_diff_r_reg[5] ; wire [0:0]\center_diff_r_reg[5]_0 ; wire [5:0]\mmcm_init_lead_reg[5] ; wire [5:0]\mmcm_init_trail_reg[5] ; wire \rise_lead_r_reg[1]_0 ; wire [0:0]\rise_lead_r_reg[3]_0 ; wire \rise_lead_r_reg[4]_0 ; wire \rise_lead_r_reg[4]_1 ; wire [0:0]\rise_lead_r_reg[5]_0 ; wire [2:0]\rise_trail_r_reg[3]_0 ; wire \rise_trail_r_reg[5]_0 ; wire [0:0]\rise_trail_r_reg[5]_1 ; wire [0:0]samps_zero_r_reg; wire [5:0]\tap_r_reg[4] ; wire [5:0]\tap_r_reg[5] ; wire [1:0]\tap_r_reg[5]_0 ; wire [4:0]trailing_edge00_in; wire \trailing_edge0_inferred__0/i__carry__0_n_3 ; wire \trailing_edge0_inferred__0/i__carry_n_0 ; wire \trailing_edge0_inferred__0/i__carry_n_1 ; wire \trailing_edge0_inferred__0/i__carry_n_2 ; wire \trailing_edge0_inferred__0/i__carry_n_3 ; wire use_noise_window; wire [0:0]\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED ; wire [3:1]\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:2]\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED ; LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[1]_i_1 (.I0(O[0]), .I1(\rise_trail_r_reg[5]_0 ), .I2(\rise_lead_r_reg[1]_0 ), .I3(\center_diff_r_reg[1] ), .I4(\rise_lead_r_reg[4]_0 ), .I5(\rise_trail_r_reg[3]_0 [0]), .O(D[0])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[2]_i_1 (.I0(O[1]), .I1(\rise_trail_r_reg[5]_0 ), .I2(\rise_lead_r_reg[1]_0 ), .I3(\center_diff_r_reg[1] ), .I4(\rise_lead_r_reg[4]_0 ), .I5(\rise_trail_r_reg[3]_0 [1]), .O(D[1])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[3]_i_1 (.I0(O[2]), .I1(\rise_trail_r_reg[5]_0 ), .I2(\rise_lead_r_reg[1]_0 ), .I3(\center_diff_r_reg[1] ), .I4(\rise_lead_r_reg[4]_0 ), .I5(\rise_trail_r_reg[3]_0 [2]), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair443" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_10 (.I0(\mmcm_init_trail_reg[5] [2]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [2]), .O(\center_diff_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair443" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_13 (.I0(\mmcm_init_trail_reg[5] [4]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [4]), .O(\center_diff_r[5]_i_13_n_0 )); LUT6 #( .INIT(64'h4540FFFF45404540)) \center_diff_r[5]_i_4 (.I0(\rise_lead_r_reg[3]_0 ), .I1(\mmcm_init_trail_reg[5] [3]), .I2(use_noise_window), .I3(\mmcm_init_lead_reg[5] [3]), .I4(\rise_lead_r_reg[4]_1 ), .I5(\center_diff_r[5]_i_13_n_0 ), .O(\center_diff_r_reg[1] )); LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_7 (.I0(\mmcm_init_trail_reg[5] [1]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [1]), .O(\center_diff_r_reg[0]_0 )); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry__0_i_1 (.I0(\mmcm_init_trail_reg[5] [4]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [4]), .O(\center_diff_r_reg[5]_0 )); LUT5 #( .INIT(32'hB8748B47)) mod_sub1_return0__0_carry__0_i_2 (.I0(\mmcm_init_trail_reg[5] [5]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [5]), .I3(\rise_lead_r_reg[5]_0 ), .I4(\rise_trail_r_reg[5]_1 ), .O(\center_diff_r_reg[5] )); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_1 (.I0(\mmcm_init_trail_reg[5] [3]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [3]), .O(\center_diff_r_reg[3] [3])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_2 (.I0(\mmcm_init_trail_reg[5] [2]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [2]), .O(\center_diff_r_reg[3] [2])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_3 (.I0(\mmcm_init_trail_reg[5] [1]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [1]), .O(\center_diff_r_reg[3] [1])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0__0_carry_i_4 (.I0(\mmcm_init_trail_reg[5] [0]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [0]), .O(\center_diff_r_reg[3] [0])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_2 (.I0(\mmcm_init_trail_reg[5] [2]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [2]), .O(\center_diff_r_reg[3]_0 [2])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_3 (.I0(\mmcm_init_trail_reg[5] [1]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [1]), .O(\center_diff_r_reg[3]_0 [1])); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_4 (.I0(\mmcm_init_trail_reg[5] [0]), .I1(use_noise_window), .I2(\mmcm_init_lead_reg[5] [0]), .O(\center_diff_r_reg[3]_0 [0])); FDRE \rise_lead_r_reg[0] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [0]), .Q(\mmcm_init_lead_reg[5] [0]), .R(1'b0)); FDRE \rise_lead_r_reg[1] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [1]), .Q(\mmcm_init_lead_reg[5] [1]), .R(1'b0)); FDRE \rise_lead_r_reg[2] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [2]), .Q(\mmcm_init_lead_reg[5] [2]), .R(1'b0)); FDRE \rise_lead_r_reg[3] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [3]), .Q(\mmcm_init_lead_reg[5] [3]), .R(1'b0)); FDRE \rise_lead_r_reg[4] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [4]), .Q(\mmcm_init_lead_reg[5] [4]), .R(1'b0)); FDRE \rise_lead_r_reg[5] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [5]), .Q(\mmcm_init_lead_reg[5] [5]), .R(1'b0)); FDRE \rise_trail_r_reg[0] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [0]), .Q(\mmcm_init_trail_reg[5] [0]), .R(1'b0)); FDRE \rise_trail_r_reg[1] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [1]), .Q(\mmcm_init_trail_reg[5] [1]), .R(1'b0)); FDRE \rise_trail_r_reg[2] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [2]), .Q(\mmcm_init_trail_reg[5] [2]), .R(1'b0)); FDRE \rise_trail_r_reg[3] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [3]), .Q(\mmcm_init_trail_reg[5] [3]), .R(1'b0)); FDRE \rise_trail_r_reg[4] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [4]), .Q(\mmcm_init_trail_reg[5] [4]), .R(1'b0)); FDRE \rise_trail_r_reg[5] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [5]), .Q(\mmcm_init_trail_reg[5] [5]), .R(1'b0)); CARRY4 \trailing_edge0_inferred__0/i__carry (.CI(1'b0), .CO({\trailing_edge0_inferred__0/i__carry_n_0 ,\trailing_edge0_inferred__0/i__carry_n_1 ,\trailing_edge0_inferred__0/i__carry_n_2 ,\trailing_edge0_inferred__0/i__carry_n_3 }), .CYINIT(1'b1), .DI({Q,\tap_r_reg[5] [2:0]}), .O({trailing_edge00_in[2:0],\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED [0]}), .S(S)); CARRY4 \trailing_edge0_inferred__0/i__carry__0 (.CI(\trailing_edge0_inferred__0/i__carry_n_0 ), .CO({\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],\trailing_edge0_inferred__0/i__carry__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,DI}), .O({\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED [3:2],trailing_edge00_in[4:3]}), .S({1'b0,1'b0,\tap_r_reg[5]_0 })); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_edge_store" *) module ddr3_if_mig_7series_v4_0_poc_edge_store_9 (DI, \center_diff_r_reg[5] , \window_center_r_reg[6] , \window_center_r_reg[6]_0 , S, D, \center_diff_r_reg[0] , \center_diff_r_reg[0]_0 , \center_diff_r_reg[0]_1 , \center_diff_r_reg[5]_0 , \center_diff_r_reg[1] , \window_center_r_reg[6]_1 , \window_center_r_reg[3] , \window_center_r_reg[0] , \window_center_r_reg[6]_2 , \center_diff_r_reg[3] , \center_diff_r_reg[3]_0 , Q, center0_return3, use_noise_window, \rise_trail_r_reg[5]_0 , \rise_lead_r_reg[5]_0 , O, \rise_trail_r_reg[3]_0 , \rise_lead_r_reg[0]_0 , \rise_lead_r_reg[4]_0 , \rise_trail_r_reg[4]_0 , \rise_trail_r_reg[1]_0 , \rise_trail_r_reg[2]_0 , E, \tap_r_reg[5] , CLK, samps_zero_r_reg, \tap_r_reg[4] ); output [1:0]DI; output [0:0]\center_diff_r_reg[5] ; output [5:0]\window_center_r_reg[6] ; output [5:0]\window_center_r_reg[6]_0 ; output [0:0]S; output [2:0]D; output \center_diff_r_reg[0] ; output \center_diff_r_reg[0]_0 ; output \center_diff_r_reg[0]_1 ; output [0:0]\center_diff_r_reg[5]_0 ; output \center_diff_r_reg[1] ; output [0:0]\window_center_r_reg[6]_1 ; output [2:0]\window_center_r_reg[3] ; output [2:0]\window_center_r_reg[0] ; output [1:0]\window_center_r_reg[6]_2 ; output [0:0]\center_diff_r_reg[3] ; output [0:0]\center_diff_r_reg[3]_0 ; input [1:0]Q; input [3:0]center0_return3; input use_noise_window; input [3:0]\rise_trail_r_reg[5]_0 ; input [3:0]\rise_lead_r_reg[5]_0 ; input [0:0]O; input \rise_trail_r_reg[3]_0 ; input \rise_lead_r_reg[0]_0 ; input [1:0]\rise_lead_r_reg[4]_0 ; input [1:0]\rise_trail_r_reg[4]_0 ; input \rise_trail_r_reg[1]_0 ; input \rise_trail_r_reg[2]_0 ; input [0:0]E; input [5:0]\tap_r_reg[5] ; input CLK; input [0:0]samps_zero_r_reg; input [5:0]\tap_r_reg[4] ; wire CLK; wire [2:0]D; wire [1:0]DI; wire [0:0]E; wire [0:0]O; wire [1:0]Q; wire [0:0]S; wire [3:0]center0_return3; wire \center_diff_r[5]_i_11_n_0 ; wire \center_diff_r[5]_i_6_n_0 ; wire \center_diff_r[5]_i_8_n_0 ; wire \center_diff_r[5]_i_9_n_0 ; wire \center_diff_r_reg[0] ; wire \center_diff_r_reg[0]_0 ; wire \center_diff_r_reg[0]_1 ; wire \center_diff_r_reg[1] ; wire [0:0]\center_diff_r_reg[3] ; wire [0:0]\center_diff_r_reg[3]_0 ; wire [0:0]\center_diff_r_reg[5] ; wire [0:0]\center_diff_r_reg[5]_0 ; wire mod_sub1_return0_carry__0_i_3_n_0; wire \rise_lead_r_reg[0]_0 ; wire [1:0]\rise_lead_r_reg[4]_0 ; wire [3:0]\rise_lead_r_reg[5]_0 ; wire \rise_trail_r_reg[1]_0 ; wire \rise_trail_r_reg[2]_0 ; wire \rise_trail_r_reg[3]_0 ; wire [1:0]\rise_trail_r_reg[4]_0 ; wire [3:0]\rise_trail_r_reg[5]_0 ; wire [0:0]samps_zero_r_reg; wire [5:0]\tap_r_reg[4] ; wire [5:0]\tap_r_reg[5] ; wire use_noise_window; wire [2:0]\window_center_r_reg[0] ; wire [2:0]\window_center_r_reg[3] ; wire [5:0]\window_center_r_reg[6] ; wire [5:0]\window_center_r_reg[6]_0 ; wire [0:0]\window_center_r_reg[6]_1 ; wire [1:0]\window_center_r_reg[6]_2 ; LUT5 #( .INIT(32'hAAAA8000)) center0_return1__0_carry__0_i_1 (.I0(Q[0]), .I1(center0_return3[2]), .I2(center0_return3[1]), .I3(center0_return3[0]), .I4(center0_return3[3]), .O(DI[1])); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry__0_i_2 (.I0(\window_center_r_reg[6] [3]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [3]), .O(DI[0])); LUT6 #( .INIT(64'h5F5F3FC0A0A03FC0)) center0_return1__0_carry__0_i_3 (.I0(\window_center_r_reg[6] [4]), .I1(\window_center_r_reg[6]_0 [4]), .I2(Q[1]), .I3(\window_center_r_reg[6]_0 [5]), .I4(use_noise_window), .I5(\window_center_r_reg[6] [5]), .O(S)); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry_i_1 (.I0(\window_center_r_reg[6] [2]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [2]), .O(\window_center_r_reg[3] [2])); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry_i_2 (.I0(\window_center_r_reg[6] [1]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [1]), .O(\window_center_r_reg[3] [1])); LUT3 #( .INIT(8'hB8)) center0_return1__0_carry_i_3 (.I0(\window_center_r_reg[6] [0]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [0]), .O(\window_center_r_reg[3] [0])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry__0_i_1 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .O(\window_center_r_reg[6]_2 [1])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry__0_i_2 (.I0(\window_center_r_reg[6] [3]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [3]), .O(\window_center_r_reg[6]_2 [0])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry__0_i_3 (.I0(\window_center_r_reg[6] [5]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [5]), .O(\window_center_r_reg[6]_1 )); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry_i_1 (.I0(\window_center_r_reg[6] [2]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [2]), .O(\window_center_r_reg[0] [2])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry_i_2 (.I0(\window_center_r_reg[6] [1]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [1]), .O(\window_center_r_reg[0] [1])); LUT3 #( .INIT(8'hB8)) center0_return1__1_carry_i_3 (.I0(\window_center_r_reg[6] [0]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [0]), .O(\window_center_r_reg[0] [0])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[0]_i_1 (.I0(O), .I1(\center_diff_r_reg[0] ), .I2(\center_diff_r_reg[0]_0 ), .I3(\rise_trail_r_reg[3]_0 ), .I4(\center_diff_r_reg[0]_1 ), .I5(\rise_lead_r_reg[0]_0 ), .O(D[0])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[4]_i_1 (.I0(\rise_lead_r_reg[4]_0 [0]), .I1(\center_diff_r_reg[0] ), .I2(\center_diff_r_reg[0]_0 ), .I3(\rise_trail_r_reg[3]_0 ), .I4(\center_diff_r_reg[0]_1 ), .I5(\rise_trail_r_reg[4]_0 [0]), .O(D[1])); LUT6 #( .INIT(64'hFFBFBBBB00808888)) \center_diff_r[5]_i_1 (.I0(\rise_lead_r_reg[4]_0 [1]), .I1(\center_diff_r_reg[0] ), .I2(\center_diff_r_reg[0]_0 ), .I3(\rise_trail_r_reg[3]_0 ), .I4(\center_diff_r_reg[0]_1 ), .I5(\rise_trail_r_reg[4]_0 [1]), .O(D[2])); LUT5 #( .INIT(32'h335ACC5A)) \center_diff_r[5]_i_11 (.I0(\window_center_r_reg[6]_0 [3]), .I1(\window_center_r_reg[6] [3]), .I2(\rise_lead_r_reg[5]_0 [1]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [1]), .O(\center_diff_r[5]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair442" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_12 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .O(\center_diff_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair441" *) LUT5 #( .INIT(32'hCCAFFFAF)) \center_diff_r[5]_i_2 (.I0(\window_center_r_reg[6]_0 [5]), .I1(\window_center_r_reg[6] [5]), .I2(\rise_lead_r_reg[5]_0 [3]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [3]), .O(\center_diff_r_reg[0] )); LUT6 #( .INIT(64'hFFFFFFFFB200FFB2)) \center_diff_r[5]_i_3 (.I0(\center_diff_r[5]_i_6_n_0 ), .I1(\rise_trail_r_reg[1]_0 ), .I2(\center_diff_r[5]_i_8_n_0 ), .I3(\center_diff_r[5]_i_9_n_0 ), .I4(\rise_trail_r_reg[2]_0 ), .I5(\center_diff_r[5]_i_11_n_0 ), .O(\center_diff_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000FF77CF47)) \center_diff_r[5]_i_5 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .I3(\rise_trail_r_reg[5]_0 [2]), .I4(\rise_lead_r_reg[5]_0 [2]), .I5(mod_sub1_return0_carry__0_i_3_n_0), .O(\center_diff_r_reg[0]_1 )); LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_6 (.I0(\window_center_r_reg[6] [1]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [1]), .O(\center_diff_r[5]_i_6_n_0 )); LUT5 #( .INIT(32'h000ACC0A)) \center_diff_r[5]_i_8 (.I0(\window_center_r_reg[6]_0 [0]), .I1(\window_center_r_reg[6] [0]), .I2(\rise_lead_r_reg[5]_0 [0]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [0]), .O(\center_diff_r[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair442" *) LUT3 #( .INIT(8'hB8)) \center_diff_r[5]_i_9 (.I0(\window_center_r_reg[6] [2]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [2]), .O(\center_diff_r[5]_i_9_n_0 )); LUT5 #( .INIT(32'h478B74B8)) mod_sub1_return0_carry__0_i_1 (.I0(\window_center_r_reg[6] [4]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [4]), .I3(\rise_trail_r_reg[5]_0 [2]), .I4(\rise_lead_r_reg[5]_0 [2]), .O(\center_diff_r_reg[5] )); LUT6 #( .INIT(64'h555595955A559A95)) mod_sub1_return0_carry__0_i_2 (.I0(mod_sub1_return0_carry__0_i_3_n_0), .I1(\window_center_r_reg[6] [4]), .I2(use_noise_window), .I3(\window_center_r_reg[6]_0 [4]), .I4(\rise_trail_r_reg[5]_0 [2]), .I5(\rise_lead_r_reg[5]_0 [2]), .O(\center_diff_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair441" *) LUT5 #( .INIT(32'h335ACC5A)) mod_sub1_return0_carry__0_i_3 (.I0(\window_center_r_reg[6]_0 [5]), .I1(\window_center_r_reg[6] [5]), .I2(\rise_lead_r_reg[5]_0 [3]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [3]), .O(mod_sub1_return0_carry__0_i_3_n_0)); LUT3 #( .INIT(8'hB8)) mod_sub1_return0_carry_i_1 (.I0(\window_center_r_reg[6] [3]), .I1(use_noise_window), .I2(\window_center_r_reg[6]_0 [3]), .O(\center_diff_r_reg[3]_0 )); LUT5 #( .INIT(32'h335ACC5A)) mod_sub1_return0_carry_i_5 (.I0(\window_center_r_reg[6]_0 [3]), .I1(\window_center_r_reg[6] [3]), .I2(\rise_lead_r_reg[5]_0 [1]), .I3(use_noise_window), .I4(\rise_trail_r_reg[5]_0 [1]), .O(\center_diff_r_reg[3] )); FDRE \rise_lead_r_reg[0] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [0]), .Q(\window_center_r_reg[6] [0]), .R(1'b0)); FDRE \rise_lead_r_reg[1] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [1]), .Q(\window_center_r_reg[6] [1]), .R(1'b0)); FDRE \rise_lead_r_reg[2] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [2]), .Q(\window_center_r_reg[6] [2]), .R(1'b0)); FDRE \rise_lead_r_reg[3] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [3]), .Q(\window_center_r_reg[6] [3]), .R(1'b0)); FDRE \rise_lead_r_reg[4] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [4]), .Q(\window_center_r_reg[6] [4]), .R(1'b0)); FDRE \rise_lead_r_reg[5] (.C(CLK), .CE(E), .D(\tap_r_reg[5] [5]), .Q(\window_center_r_reg[6] [5]), .R(1'b0)); FDRE \rise_trail_r_reg[0] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [0]), .Q(\window_center_r_reg[6]_0 [0]), .R(1'b0)); FDRE \rise_trail_r_reg[1] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [1]), .Q(\window_center_r_reg[6]_0 [1]), .R(1'b0)); FDRE \rise_trail_r_reg[2] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [2]), .Q(\window_center_r_reg[6]_0 [2]), .R(1'b0)); FDRE \rise_trail_r_reg[3] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [3]), .Q(\window_center_r_reg[6]_0 [3]), .R(1'b0)); FDRE \rise_trail_r_reg[4] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [4]), .Q(\window_center_r_reg[6]_0 [4]), .R(1'b0)); FDRE \rise_trail_r_reg[5] (.C(CLK), .CE(samps_zero_r_reg), .D(\tap_r_reg[4] [5]), .Q(\window_center_r_reg[6]_0 [5]), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_poc_meta (detect_done_r_reg, \sm_r_reg[1] , poc_backup_r_reg_0, run_polarity_held_r, Q, center_return3, \edge_diff_r_reg[0]_0 , center0_return3, O, \center_diff_r_reg[5]_0 , \center_diff_r_reg[3]_0 , \center_diff_r_reg[5]_1 , \diff_r_reg[7]_0 , \diff_r_reg[7]_1 , \edge_center_r_reg[6]_0 , \prev_r_reg[0]_0 , \prev_r_reg[0]_1 , \prev_r_reg[2]_0 , \window_center_r_reg[6]_0 , CLK, samps_zero_r_reg, samps_zero_r_reg_0, S, \rise_lead_center_offset_r_reg[4]_0 , \rise_lead_center_offset_r_reg[2]_0 , DI, \edge_diff_r_reg[4]_0 , \rise_trail_center_offset_r_reg[2]_0 , \rise_lead_center_offset_r_reg[4]_1 , \rise_trail_center_offset_r_reg[3]_0 , \rise_trail_center_offset_r_reg[5]_0 , \rise_lead_r_reg[2] , \rise_trail_r_reg[2] , \rise_lead_r_reg[4] , \rise_lead_r_reg[5] , \rise_lead_r_reg[2]_0 , \rise_trail_r_reg[2]_0 , \center_diff_r_reg[4]_0 , \rise_lead_r_reg[4]_0 , \rise_lead_r_reg[3] , \rise_trail_r_reg[3] , \rise_lead_r_reg[4]_1 , \rise_lead_r_reg[4]_2 , \rise_trail_r_reg[3]_0 , \rise_lead_r_reg[3]_0 , \rise_trail_r_reg[4] , \rise_trail_r_reg[5] , \edge_center_r_reg[6]_1 , \window_center_r_reg[6]_1 , \edge_center_r_reg[3]_0 , \edge_center_r_reg[5]_0 , \window_center_r_reg[6]_2 , \edge_center_r_reg[0]_0 , \edge_center_r_reg[3]_1 , \edge_center_r_reg[6]_2 , ocd_ktap_right_r_reg, ocd_ktap_left_r_reg, \run_ends_r_reg[1]_0 , rstdiv0_sync_r1_reg_rep__20, ocd_ktap_left_r_reg_0, ocd_edge_detect_rdy_r_reg, \diff_r_reg[2]_0 , run_too_small_r_reg, D, \rise_lead_r_reg[3]_1 , \rise_trail_r_reg[3]_1 , \rise_trail_center_offset_r_reg[0]_0 ); output detect_done_r_reg; output \sm_r_reg[1] ; output poc_backup_r_reg_0; output run_polarity_held_r; output [5:0]Q; output [3:0]center_return3; output [5:0]\edge_diff_r_reg[0]_0 ; output [3:0]center0_return3; output [3:0]O; output [1:0]\center_diff_r_reg[5]_0 ; output [2:0]\center_diff_r_reg[3]_0 ; output [1:0]\center_diff_r_reg[5]_1 ; output [6:0]\diff_r_reg[7]_0 ; output [6:0]\diff_r_reg[7]_1 ; output [4:0]\edge_center_r_reg[6]_0 ; output \prev_r_reg[0]_0 ; output \prev_r_reg[0]_1 ; output [2:0]\prev_r_reg[2]_0 ; output [4:0]\window_center_r_reg[6]_0 ; input CLK; input samps_zero_r_reg; input samps_zero_r_reg_0; input [2:0]S; input [1:0]\rise_lead_center_offset_r_reg[4]_0 ; input [2:0]\rise_lead_center_offset_r_reg[2]_0 ; input [0:0]DI; input [1:0]\edge_diff_r_reg[4]_0 ; input [2:0]\rise_trail_center_offset_r_reg[2]_0 ; input [1:0]\rise_lead_center_offset_r_reg[4]_1 ; input [3:0]\rise_trail_center_offset_r_reg[3]_0 ; input [1:0]\rise_trail_center_offset_r_reg[5]_0 ; input [2:0]\rise_lead_r_reg[2] ; input [2:0]\rise_trail_r_reg[2] ; input [1:0]\rise_lead_r_reg[4] ; input [2:0]\rise_lead_r_reg[5] ; input [2:0]\rise_lead_r_reg[2]_0 ; input [2:0]\rise_trail_r_reg[2]_0 ; input [1:0]\center_diff_r_reg[4]_0 ; input [2:0]\rise_lead_r_reg[4]_0 ; input [3:0]\rise_lead_r_reg[3] ; input [3:0]\rise_trail_r_reg[3] ; input [0:0]\rise_lead_r_reg[4]_1 ; input [1:0]\rise_lead_r_reg[4]_2 ; input [3:0]\rise_trail_r_reg[3]_0 ; input [3:0]\rise_lead_r_reg[3]_0 ; input [0:0]\rise_trail_r_reg[4] ; input [1:0]\rise_trail_r_reg[5] ; input [3:0]\edge_center_r_reg[6]_1 ; input [3:0]\window_center_r_reg[6]_1 ; input [3:0]\edge_center_r_reg[3]_0 ; input [1:0]\edge_center_r_reg[5]_0 ; input [3:0]\window_center_r_reg[6]_2 ; input [0:0]\edge_center_r_reg[0]_0 ; input [3:0]\edge_center_r_reg[3]_1 ; input [2:0]\edge_center_r_reg[6]_2 ; input ocd_ktap_right_r_reg; input ocd_ktap_left_r_reg; input \run_ends_r_reg[1]_0 ; input rstdiv0_sync_r1_reg_rep__20; input ocd_ktap_left_r_reg_0; input ocd_edge_detect_rdy_r_reg; input \diff_r_reg[2]_0 ; input run_too_small_r_reg; input [5:0]D; input [5:0]\rise_lead_r_reg[3]_1 ; input [5:0]\rise_trail_r_reg[3]_1 ; input \rise_trail_center_offset_r_reg[0]_0 ; wire CLK; wire [5:0]D; wire [0:0]DI; wire [3:0]O; wire [5:0]Q; wire [2:0]S; wire [6:0]center0_return0; wire center0_return1__0_carry__0_n_2; wire center0_return1__0_carry__0_n_3; wire center0_return1__0_carry_i_7_n_0; wire center0_return1__0_carry_n_0; wire center0_return1__0_carry_n_1; wire center0_return1__0_carry_n_2; wire center0_return1__0_carry_n_3; wire center0_return1__1_carry__0_n_2; wire center0_return1__1_carry__0_n_3; wire center0_return1__1_carry_i_7_n_0; wire center0_return1__1_carry_n_0; wire center0_return1__1_carry_n_1; wire center0_return1__1_carry_n_2; wire center0_return1__1_carry_n_3; wire [3:0]center0_return3; wire [2:0]\center_diff_r_reg[3]_0 ; wire [1:0]\center_diff_r_reg[4]_0 ; wire [1:0]\center_diff_r_reg[5]_0 ; wire [1:0]\center_diff_r_reg[5]_1 ; wire \center_diff_r_reg_n_0_[0] ; wire [6:0]center_return0; wire center_return1__0_carry__0_i_1_n_0; wire center_return1__0_carry__0_n_2; wire center_return1__0_carry__0_n_3; wire center_return1__0_carry_i_4_n_0; wire center_return1__0_carry_n_0; wire center_return1__0_carry_n_1; wire center_return1__0_carry_n_2; wire center_return1__0_carry_n_3; wire center_return1__1_carry__0_i_1_n_0; wire center_return1__1_carry__0_n_2; wire center_return1__1_carry__0_n_3; wire center_return1__1_carry_i_4_n_0; wire center_return1__1_carry_n_0; wire center_return1__1_carry_n_1; wire center_return1__1_carry_n_2; wire center_return1__1_carry_n_3; wire [3:0]center_return3; wire detect_done_r_reg; wire [0:0]diff; wire [7:0]diff_ns; wire [7:0]diff_ns0; wire [6:1]diff_ns00_in; wire diff_ns0_carry__0_n_1; wire diff_ns0_carry__0_n_2; wire diff_ns0_carry__0_n_3; wire diff_ns0_carry_n_0; wire diff_ns0_carry_n_1; wire diff_ns0_carry_n_2; wire diff_ns0_carry_n_3; wire \diff_ns0_inferred__0/i__carry__0_n_0 ; wire \diff_ns0_inferred__0/i__carry__0_n_2 ; wire \diff_ns0_inferred__0/i__carry__0_n_3 ; wire \diff_ns0_inferred__0/i__carry_n_0 ; wire \diff_ns0_inferred__0/i__carry_n_1 ; wire \diff_ns0_inferred__0/i__carry_n_2 ; wire \diff_ns0_inferred__0/i__carry_n_3 ; wire diff_ns1; wire diff_ns1_carry_n_1; wire diff_ns1_carry_n_2; wire diff_ns1_carry_n_3; wire \diff_r_reg[2]_0 ; wire [6:0]\diff_r_reg[7]_0 ; wire [6:0]\diff_r_reg[7]_1 ; wire \diff_r_reg_n_0_[3] ; wire \diff_r_reg_n_0_[4] ; wire \diff_r_reg_n_0_[5] ; wire \diff_r_reg_n_0_[6] ; wire \diff_r_reg_n_0_[7] ; wire diffs_eq_ns; wire diffs_eq_r; wire done_ns; wire edge_aligned_ns; wire edge_aligned_r_i_2_n_0; wire edge_aligned_r_i_3_n_0; wire [0:0]\edge_center_r_reg[0]_0 ; wire [3:0]\edge_center_r_reg[3]_0 ; wire [3:0]\edge_center_r_reg[3]_1 ; wire [1:0]\edge_center_r_reg[5]_0 ; wire [4:0]\edge_center_r_reg[6]_0 ; wire [3:0]\edge_center_r_reg[6]_1 ; wire [2:0]\edge_center_r_reg[6]_2 ; wire \edge_diff_r[5]_i_2_n_0 ; wire \edge_diff_r[5]_i_3_n_0 ; wire [5:0]\edge_diff_r_reg[0]_0 ; wire [1:0]\edge_diff_r_reg[4]_0 ; wire mod_sub1_return0__0_carry__0_n_3; wire mod_sub1_return0__0_carry_n_0; wire mod_sub1_return0__0_carry_n_1; wire mod_sub1_return0__0_carry_n_2; wire mod_sub1_return0__0_carry_n_3; wire mod_sub1_return0_carry__0_n_3; wire mod_sub1_return0_carry_n_0; wire mod_sub1_return0_carry_n_1; wire mod_sub1_return0_carry_n_2; wire mod_sub1_return0_carry_n_3; wire [5:0]mod_sub_return; wire mod_sub_return0__0_carry__0_n_3; wire mod_sub_return0__0_carry__0_n_6; wire mod_sub_return0__0_carry__0_n_7; wire mod_sub_return0__0_carry_n_0; wire mod_sub_return0__0_carry_n_1; wire mod_sub_return0__0_carry_n_2; wire mod_sub_return0__0_carry_n_3; wire mod_sub_return0__0_carry_n_4; wire mod_sub_return0__0_carry_n_5; wire mod_sub_return0__0_carry_n_6; wire mod_sub_return0_carry__0_i_1_n_0; wire mod_sub_return0_carry__0_n_3; wire mod_sub_return0_carry__0_n_6; wire mod_sub_return0_carry__0_n_7; wire mod_sub_return0_carry_i_1_n_0; wire mod_sub_return0_carry_n_0; wire mod_sub_return0_carry_n_1; wire mod_sub_return0_carry_n_2; wire mod_sub_return0_carry_n_3; wire mod_sub_return0_carry_n_4; wire mod_sub_return0_carry_n_5; wire mod_sub_return0_carry_n_6; wire mod_sub_return0_carry_n_7; wire ocd_edge_detect_rdy_r_reg; wire ocd_ktap_left_r_reg; wire ocd_ktap_left_r_reg_0; wire ocd_ktap_right_r_reg; wire poc_backup_ns; wire poc_backup_ns0; wire poc_backup_ns0_carry_i_10_n_0; wire poc_backup_ns0_carry_i_11_n_0; wire poc_backup_ns0_carry_i_12_n_0; wire poc_backup_ns0_carry_i_13_n_0; wire poc_backup_ns0_carry_i_14_n_0; wire poc_backup_ns0_carry_i_15_n_0; wire poc_backup_ns0_carry_i_16_n_0; wire poc_backup_ns0_carry_i_1_n_0; wire poc_backup_ns0_carry_i_2_n_0; wire poc_backup_ns0_carry_i_3_n_0; wire poc_backup_ns0_carry_i_4_n_0; wire poc_backup_ns0_carry_i_5_n_0; wire poc_backup_ns0_carry_i_6_n_0; wire poc_backup_ns0_carry_i_7_n_0; wire poc_backup_ns0_carry_i_8_n_0; wire poc_backup_ns0_carry_i_9_n_0; wire poc_backup_ns0_carry_n_1; wire poc_backup_ns0_carry_n_2; wire poc_backup_ns0_carry_n_3; wire poc_backup_r_reg_0; wire [7:0]prev_r; wire \prev_r_reg[0]_0 ; wire \prev_r_reg[0]_1 ; wire [2:0]\prev_r_reg[2]_0 ; wire reset_run_ends; wire [2:0]\rise_lead_center_offset_r_reg[2]_0 ; wire [1:0]\rise_lead_center_offset_r_reg[4]_0 ; wire [1:0]\rise_lead_center_offset_r_reg[4]_1 ; wire [2:0]\rise_lead_r_reg[2] ; wire [2:0]\rise_lead_r_reg[2]_0 ; wire [3:0]\rise_lead_r_reg[3] ; wire [3:0]\rise_lead_r_reg[3]_0 ; wire [5:0]\rise_lead_r_reg[3]_1 ; wire [1:0]\rise_lead_r_reg[4] ; wire [2:0]\rise_lead_r_reg[4]_0 ; wire [0:0]\rise_lead_r_reg[4]_1 ; wire [1:0]\rise_lead_r_reg[4]_2 ; wire [2:0]\rise_lead_r_reg[5] ; wire \rise_trail_center_offset_r_reg[0]_0 ; wire [2:0]\rise_trail_center_offset_r_reg[2]_0 ; wire [3:0]\rise_trail_center_offset_r_reg[3]_0 ; wire [1:0]\rise_trail_center_offset_r_reg[5]_0 ; wire [2:0]\rise_trail_r_reg[2] ; wire [2:0]\rise_trail_r_reg[2]_0 ; wire [3:0]\rise_trail_r_reg[3] ; wire [3:0]\rise_trail_r_reg[3]_0 ; wire [5:0]\rise_trail_r_reg[3]_1 ; wire [0:0]\rise_trail_r_reg[4] ; wire [1:0]\rise_trail_r_reg[5] ; wire rstdiv0_sync_r1_reg_rep__20; wire run_end_r2_reg_srl3_n_0; wire run_end_r3; wire \run_ends_r[0]_i_1_n_0 ; wire \run_ends_r[1]_i_1_n_0 ; wire \run_ends_r_reg[1]_0 ; wire run_polarity_held_r; wire run_too_small_r10; wire run_too_small_r2_reg_srl2_n_0; wire run_too_small_r3; wire run_too_small_r_reg; wire samps_zero_r_reg; wire samps_zero_r_reg_0; wire \sm_r_reg[1] ; wire [4:0]\window_center_r_reg[6]_0 ; wire [3:0]\window_center_r_reg[6]_1 ; wire [3:0]\window_center_r_reg[6]_2 ; wire [0:0]NLW_center0_return1__0_carry_O_UNCONNECTED; wire [3:2]NLW_center0_return1__0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center0_return1__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_center0_return1__1_carry_O_UNCONNECTED; wire [2:2]NLW_center0_return1__1_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center0_return1__1_carry__0_O_UNCONNECTED; wire [0:0]NLW_center_return1__0_carry_O_UNCONNECTED; wire [3:2]NLW_center_return1__0_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center_return1__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_center_return1__1_carry_O_UNCONNECTED; wire [2:2]NLW_center_return1__1_carry__0_CO_UNCONNECTED; wire [3:3]NLW_center_return1__1_carry__0_O_UNCONNECTED; wire [3:3]NLW_diff_ns0_carry__0_CO_UNCONNECTED; wire [0:0]\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED ; wire [2:2]\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:3]\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED ; wire [3:0]NLW_diff_ns1_carry_O_UNCONNECTED; wire [0:0]NLW_mod_sub1_return0__0_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub1_return0_carry__0_O_UNCONNECTED; wire [0:0]NLW_mod_sub_return0__0_carry_O_UNCONNECTED; wire [3:1]NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED; wire [3:1]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED; wire [3:2]NLW_mod_sub_return0_carry__0_O_UNCONNECTED; wire [3:0]NLW_poc_backup_ns0_carry_O_UNCONNECTED; CARRY4 center0_return1__0_carry (.CI(1'b0), .CO({center0_return1__0_carry_n_0,center0_return1__0_carry_n_1,center0_return1__0_carry_n_2,center0_return1__0_carry_n_3}), .CYINIT(1'b0), .DI({\rise_lead_r_reg[2]_0 ,1'b0}), .O({center0_return0[3:1],NLW_center0_return1__0_carry_O_UNCONNECTED[0]}), .S({\rise_trail_r_reg[2]_0 ,center0_return1__0_carry_i_7_n_0})); CARRY4 center0_return1__0_carry__0 (.CI(center0_return1__0_carry_n_0), .CO({NLW_center0_return1__0_carry__0_CO_UNCONNECTED[3:2],center0_return1__0_carry__0_n_2,center0_return1__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\center_diff_r_reg[4]_0 }), .O({NLW_center0_return1__0_carry__0_O_UNCONNECTED[3],center0_return0[6:4]}), .S({1'b0,\rise_lead_r_reg[4]_0 })); LUT1 #( .INIT(2'h2)) center0_return1__0_carry_i_7 (.I0(\center_diff_r_reg_n_0_[0] ), .O(center0_return1__0_carry_i_7_n_0)); CARRY4 center0_return1__1_carry (.CI(1'b0), .CO({center0_return1__1_carry_n_0,center0_return1__1_carry_n_1,center0_return1__1_carry_n_2,center0_return1__1_carry_n_3}), .CYINIT(1'b0), .DI({\rise_lead_r_reg[2] ,1'b0}), .O({NLW_center0_return1__1_carry_O_UNCONNECTED[3:1],center0_return0[0]}), .S({\rise_trail_r_reg[2] ,center0_return1__1_carry_i_7_n_0})); CARRY4 center0_return1__1_carry__0 (.CI(center0_return1__1_carry_n_0), .CO({center0_return3[3],NLW_center0_return1__1_carry__0_CO_UNCONNECTED[2],center0_return1__1_carry__0_n_2,center0_return1__1_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,\rise_lead_r_reg[4] }), .O({NLW_center0_return1__1_carry__0_O_UNCONNECTED[3],center0_return3[2:0]}), .S({1'b1,\rise_lead_r_reg[5] })); LUT1 #( .INIT(2'h2)) center0_return1__1_carry_i_7 (.I0(\center_diff_r_reg_n_0_[0] ), .O(center0_return1__1_carry_i_7_n_0)); FDRE \center_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\center_diff_r_reg_n_0_[0] ), .R(1'b0)); FDRE \center_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(\window_center_r_reg[6]_0 [0]), .R(1'b0)); FDRE \center_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[2]), .Q(\window_center_r_reg[6]_0 [1]), .R(1'b0)); FDRE \center_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(D[3]), .Q(\window_center_r_reg[6]_0 [2]), .R(1'b0)); FDRE \center_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(D[4]), .Q(\window_center_r_reg[6]_0 [3]), .R(1'b0)); FDRE \center_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(D[5]), .Q(\window_center_r_reg[6]_0 [4]), .R(1'b0)); CARRY4 center_return1__0_carry (.CI(1'b0), .CO({center_return1__0_carry_n_0,center_return1__0_carry_n_1,center_return1__0_carry_n_2,center_return1__0_carry_n_3}), .CYINIT(1'b0), .DI({Q[2:0],1'b0}), .O({center_return0[3:1],NLW_center_return1__0_carry_O_UNCONNECTED[0]}), .S({\rise_lead_center_offset_r_reg[2]_0 ,center_return1__0_carry_i_4_n_0})); CARRY4 center_return1__0_carry__0 (.CI(center_return1__0_carry_n_0), .CO({NLW_center_return1__0_carry__0_CO_UNCONNECTED[3:2],center_return1__0_carry__0_n_2,center_return1__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,DI,Q[3]}), .O({NLW_center_return1__0_carry__0_O_UNCONNECTED[3],center_return0[6:4]}), .S({1'b0,center_return1__0_carry__0_i_1_n_0,\edge_diff_r_reg[4]_0 })); LUT3 #( .INIT(8'h78)) center_return1__0_carry__0_i_1 (.I0(Q[4]), .I1(\edge_center_r_reg[6]_0 [4]), .I2(Q[5]), .O(center_return1__0_carry__0_i_1_n_0)); LUT1 #( .INIT(2'h2)) center_return1__0_carry_i_4 (.I0(diff), .O(center_return1__0_carry_i_4_n_0)); CARRY4 center_return1__1_carry (.CI(1'b0), .CO({center_return1__1_carry_n_0,center_return1__1_carry_n_1,center_return1__1_carry_n_2,center_return1__1_carry_n_3}), .CYINIT(1'b0), .DI({Q[2:0],1'b0}), .O({NLW_center_return1__1_carry_O_UNCONNECTED[3:1],center_return0[0]}), .S({S,center_return1__1_carry_i_4_n_0})); CARRY4 center_return1__1_carry__0 (.CI(center_return1__1_carry_n_0), .CO({center_return3[3],NLW_center_return1__1_carry__0_CO_UNCONNECTED[2],center_return1__1_carry__0_n_2,center_return1__1_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,Q[4:3]}), .O({NLW_center_return1__1_carry__0_O_UNCONNECTED[3],center_return3[2:0]}), .S({1'b1,center_return1__1_carry__0_i_1_n_0,\rise_lead_center_offset_r_reg[4]_0 })); LUT1 #( .INIT(2'h2)) center_return1__1_carry__0_i_1 (.I0(Q[5]), .O(center_return1__1_carry__0_i_1_n_0)); LUT1 #( .INIT(2'h2)) center_return1__1_carry_i_4 (.I0(diff), .O(center_return1__1_carry_i_4_n_0)); CARRY4 diff_ns0_carry (.CI(1'b0), .CO({diff_ns0_carry_n_0,diff_ns0_carry_n_1,diff_ns0_carry_n_2,diff_ns0_carry_n_3}), .CYINIT(1'b1), .DI(\diff_r_reg[7]_0 [3:0]), .O(diff_ns0[3:0]), .S(\edge_center_r_reg[3]_0 )); CARRY4 diff_ns0_carry__0 (.CI(diff_ns0_carry_n_0), .CO({NLW_diff_ns0_carry__0_CO_UNCONNECTED[3],diff_ns0_carry__0_n_1,diff_ns0_carry__0_n_2,diff_ns0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,\edge_center_r_reg[5]_0 ,\diff_r_reg[7]_1 [4]}), .O(diff_ns0[7:4]), .S(\window_center_r_reg[6]_2 )); CARRY4 \diff_ns0_inferred__0/i__carry (.CI(1'b0), .CO({\diff_ns0_inferred__0/i__carry_n_0 ,\diff_ns0_inferred__0/i__carry_n_1 ,\diff_ns0_inferred__0/i__carry_n_2 ,\diff_ns0_inferred__0/i__carry_n_3 }), .CYINIT(1'b1), .DI(\diff_r_reg[7]_0 [3:0]), .O({diff_ns00_in[3:1],\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED [0]}), .S(\edge_center_r_reg[3]_1 )); CARRY4 \diff_ns0_inferred__0/i__carry__0 (.CI(\diff_ns0_inferred__0/i__carry_n_0 ), .CO({\diff_ns0_inferred__0/i__carry__0_n_0 ,\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED [2],\diff_ns0_inferred__0/i__carry__0_n_2 ,\diff_ns0_inferred__0/i__carry__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,\diff_r_reg[7]_0 [6:4]}), .O({\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED [3],diff_ns00_in[6:4]}), .S({1'b1,\edge_center_r_reg[6]_2 })); CARRY4 diff_ns1_carry (.CI(1'b0), .CO({diff_ns1,diff_ns1_carry_n_1,diff_ns1_carry_n_2,diff_ns1_carry_n_3}), .CYINIT(1'b1), .DI(\edge_center_r_reg[6]_1 ), .O(NLW_diff_ns1_carry_O_UNCONNECTED[3:0]), .S(\window_center_r_reg[6]_1 )); (* SOFT_HLUTNM = "soft_lutpair447" *) LUT3 #( .INIT(8'hAC)) \diff_r[0]_i_1 (.I0(\edge_center_r_reg[0]_0 ), .I1(diff_ns0[0]), .I2(diff_ns1), .O(diff_ns[0])); (* SOFT_HLUTNM = "soft_lutpair448" *) LUT3 #( .INIT(8'hAC)) \diff_r[1]_i_1 (.I0(diff_ns00_in[1]), .I1(diff_ns0[1]), .I2(diff_ns1), .O(diff_ns[1])); (* SOFT_HLUTNM = "soft_lutpair446" *) LUT3 #( .INIT(8'hAC)) \diff_r[2]_i_1 (.I0(diff_ns00_in[2]), .I1(diff_ns0[2]), .I2(diff_ns1), .O(diff_ns[2])); (* SOFT_HLUTNM = "soft_lutpair449" *) LUT3 #( .INIT(8'hAC)) \diff_r[3]_i_1 (.I0(diff_ns00_in[3]), .I1(diff_ns0[3]), .I2(diff_ns1), .O(diff_ns[3])); (* SOFT_HLUTNM = "soft_lutpair449" *) LUT3 #( .INIT(8'hAC)) \diff_r[4]_i_1 (.I0(diff_ns00_in[4]), .I1(diff_ns0[4]), .I2(diff_ns1), .O(diff_ns[4])); (* SOFT_HLUTNM = "soft_lutpair446" *) LUT3 #( .INIT(8'hAC)) \diff_r[5]_i_1 (.I0(diff_ns00_in[5]), .I1(diff_ns0[5]), .I2(diff_ns1), .O(diff_ns[5])); (* SOFT_HLUTNM = "soft_lutpair448" *) LUT3 #( .INIT(8'hAC)) \diff_r[6]_i_1 (.I0(diff_ns00_in[6]), .I1(diff_ns0[6]), .I2(diff_ns1), .O(diff_ns[6])); (* SOFT_HLUTNM = "soft_lutpair447" *) LUT3 #( .INIT(8'h5C)) \diff_r[7]_i_1 (.I0(\diff_ns0_inferred__0/i__carry__0_n_0 ), .I1(diff_ns0[7]), .I2(diff_ns1), .O(diff_ns[7])); FDRE \diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(diff_ns[0]), .Q(\prev_r_reg[2]_0 [0]), .R(1'b0)); FDRE \diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(diff_ns[1]), .Q(\prev_r_reg[2]_0 [1]), .R(1'b0)); FDRE \diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(diff_ns[2]), .Q(\prev_r_reg[2]_0 [2]), .R(1'b0)); FDRE \diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(diff_ns[3]), .Q(\diff_r_reg_n_0_[3] ), .R(1'b0)); FDRE \diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(diff_ns[4]), .Q(\diff_r_reg_n_0_[4] ), .R(1'b0)); FDRE \diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(diff_ns[5]), .Q(\diff_r_reg_n_0_[5] ), .R(1'b0)); FDRE \diff_r_reg[6] (.C(CLK), .CE(1'b1), .D(diff_ns[6]), .Q(\diff_r_reg_n_0_[6] ), .R(1'b0)); FDRE \diff_r_reg[7] (.C(CLK), .CE(1'b1), .D(diff_ns[7]), .Q(\diff_r_reg_n_0_[7] ), .R(1'b0)); LUT6 #( .INIT(64'h000000000000BF80)) diffs_eq_r_i_1 (.I0(edge_aligned_r_i_2_n_0), .I1(done_ns), .I2(detect_done_r_reg), .I3(diffs_eq_r), .I4(ocd_ktap_right_r_reg), .I5(ocd_ktap_left_r_reg), .O(diffs_eq_ns)); FDRE diffs_eq_r_reg (.C(CLK), .CE(1'b1), .D(diffs_eq_ns), .Q(diffs_eq_r), .R(1'b0)); LUT3 #( .INIT(8'h80)) done_r_i_1 (.I0(ocd_edge_detect_rdy_r_reg), .I1(\prev_r_reg[0]_0 ), .I2(\prev_r_reg[0]_1 ), .O(done_ns)); FDRE done_r_reg (.C(CLK), .CE(1'b1), .D(done_ns), .Q(detect_done_r_reg), .R(1'b0)); LUT6 #( .INIT(64'h000000F400000000)) edge_aligned_r_i_1 (.I0(edge_aligned_r_i_2_n_0), .I1(diffs_eq_r), .I2(edge_aligned_r_i_3_n_0), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_left_r_reg_0), .I5(done_ns), .O(edge_aligned_ns)); LUT6 #( .INIT(64'h4000000055551555)) edge_aligned_r_i_2 (.I0(\diff_r_reg_n_0_[6] ), .I1(\diff_r_reg_n_0_[5] ), .I2(\diff_r_reg_n_0_[4] ), .I3(\diff_r_reg_n_0_[3] ), .I4(\diff_r_reg[2]_0 ), .I5(\diff_r_reg_n_0_[7] ), .O(edge_aligned_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000004)) edge_aligned_r_i_3 (.I0(\diff_r_reg_n_0_[3] ), .I1(\diff_r_reg[2]_0 ), .I2(\diff_r_reg_n_0_[4] ), .I3(\diff_r_reg_n_0_[5] ), .I4(\diff_r_reg_n_0_[6] ), .I5(\diff_r_reg_n_0_[7] ), .O(edge_aligned_r_i_3_n_0)); FDRE edge_aligned_r_reg (.C(CLK), .CE(1'b1), .D(edge_aligned_ns), .Q(\sm_r_reg[1] ), .R(1'b0)); FDRE \edge_center_r_reg[0] (.C(CLK), .CE(1'b1), .D(center_return0[0]), .Q(\diff_r_reg[7]_0 [0]), .R(1'b0)); FDRE \edge_center_r_reg[1] (.C(CLK), .CE(1'b1), .D(center_return0[1]), .Q(\diff_r_reg[7]_0 [1]), .R(1'b0)); FDRE \edge_center_r_reg[2] (.C(CLK), .CE(1'b1), .D(center_return0[2]), .Q(\diff_r_reg[7]_0 [2]), .R(1'b0)); FDRE \edge_center_r_reg[3] (.C(CLK), .CE(1'b1), .D(center_return0[3]), .Q(\diff_r_reg[7]_0 [3]), .R(1'b0)); FDRE \edge_center_r_reg[4] (.C(CLK), .CE(1'b1), .D(center_return0[4]), .Q(\diff_r_reg[7]_0 [4]), .R(1'b0)); FDRE \edge_center_r_reg[5] (.C(CLK), .CE(1'b1), .D(center_return0[5]), .Q(\diff_r_reg[7]_0 [5]), .R(1'b0)); FDRE \edge_center_r_reg[6] (.C(CLK), .CE(1'b1), .D(center_return0[6]), .Q(\diff_r_reg[7]_0 [6]), .R(1'b0)); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[0]_i_1 (.I0(\rise_trail_center_offset_r_reg[0]_0 ), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_7), .O(mod_sub_return[0])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[1]_i_1 (.I0(mod_sub_return0__0_carry_n_6), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_6), .O(mod_sub_return[1])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[2]_i_1 (.I0(mod_sub_return0__0_carry_n_5), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_5), .O(mod_sub_return[2])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[3]_i_1 (.I0(mod_sub_return0__0_carry_n_4), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry_n_4), .O(mod_sub_return[3])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[4]_i_1 (.I0(mod_sub_return0__0_carry__0_n_7), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry__0_n_7), .O(mod_sub_return[4])); LUT5 #( .INIT(32'hBAFB8A08)) \edge_diff_r[5]_i_1 (.I0(mod_sub_return0__0_carry__0_n_6), .I1(\edge_diff_r[5]_i_2_n_0 ), .I2(Q[5]), .I3(\edge_diff_r_reg[0]_0 [5]), .I4(mod_sub_return0_carry__0_n_6), .O(mod_sub_return[5])); LUT5 #( .INIT(32'hB2FF00B2)) \edge_diff_r[5]_i_2 (.I0(\edge_diff_r[5]_i_3_n_0 ), .I1(Q[3]), .I2(\edge_diff_r_reg[0]_0 [3]), .I3(Q[4]), .I4(\edge_diff_r_reg[0]_0 [4]), .O(\edge_diff_r[5]_i_2_n_0 )); LUT6 #( .INIT(64'hDF0DFFFF0000DF0D)) \edge_diff_r[5]_i_3 (.I0(Q[0]), .I1(\edge_diff_r_reg[0]_0 [0]), .I2(Q[1]), .I3(\edge_diff_r_reg[0]_0 [1]), .I4(Q[2]), .I5(\edge_diff_r_reg[0]_0 [2]), .O(\edge_diff_r[5]_i_3_n_0 )); FDRE \edge_diff_r_reg[0] (.C(CLK), .CE(1'b1), .D(mod_sub_return[0]), .Q(diff), .R(1'b0)); FDRE \edge_diff_r_reg[1] (.C(CLK), .CE(1'b1), .D(mod_sub_return[1]), .Q(\edge_center_r_reg[6]_0 [0]), .R(1'b0)); FDRE \edge_diff_r_reg[2] (.C(CLK), .CE(1'b1), .D(mod_sub_return[2]), .Q(\edge_center_r_reg[6]_0 [1]), .R(1'b0)); FDRE \edge_diff_r_reg[3] (.C(CLK), .CE(1'b1), .D(mod_sub_return[3]), .Q(\edge_center_r_reg[6]_0 [2]), .R(1'b0)); FDRE \edge_diff_r_reg[4] (.C(CLK), .CE(1'b1), .D(mod_sub_return[4]), .Q(\edge_center_r_reg[6]_0 [3]), .R(1'b0)); FDRE \edge_diff_r_reg[5] (.C(CLK), .CE(1'b1), .D(mod_sub_return[5]), .Q(\edge_center_r_reg[6]_0 [4]), .R(1'b0)); CARRY4 mod_sub1_return0__0_carry (.CI(1'b0), .CO({mod_sub1_return0__0_carry_n_0,mod_sub1_return0__0_carry_n_1,mod_sub1_return0__0_carry_n_2,mod_sub1_return0__0_carry_n_3}), .CYINIT(1'b1), .DI(\rise_trail_r_reg[3]_0 ), .O({\center_diff_r_reg[3]_0 ,NLW_mod_sub1_return0__0_carry_O_UNCONNECTED[0]}), .S(\rise_lead_r_reg[3]_0 )); CARRY4 mod_sub1_return0__0_carry__0 (.CI(mod_sub1_return0__0_carry_n_0), .CO({NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\rise_trail_r_reg[4] }), .O({NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED[3:2],\center_diff_r_reg[5]_1 }), .S({1'b0,1'b0,\rise_trail_r_reg[5] })); CARRY4 mod_sub1_return0_carry (.CI(1'b0), .CO({mod_sub1_return0_carry_n_0,mod_sub1_return0_carry_n_1,mod_sub1_return0_carry_n_2,mod_sub1_return0_carry_n_3}), .CYINIT(1'b1), .DI(\rise_lead_r_reg[3] ), .O(O), .S(\rise_trail_r_reg[3] )); CARRY4 mod_sub1_return0_carry__0 (.CI(mod_sub1_return0_carry_n_0), .CO({NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\rise_lead_r_reg[4]_1 }), .O({NLW_mod_sub1_return0_carry__0_O_UNCONNECTED[3:2],\center_diff_r_reg[5]_0 }), .S({1'b0,1'b0,\rise_lead_r_reg[4]_2 })); CARRY4 mod_sub_return0__0_carry (.CI(1'b0), .CO({mod_sub_return0__0_carry_n_0,mod_sub_return0__0_carry_n_1,mod_sub_return0__0_carry_n_2,mod_sub_return0__0_carry_n_3}), .CYINIT(1'b1), .DI(\edge_diff_r_reg[0]_0 [3:0]), .O({mod_sub_return0__0_carry_n_4,mod_sub_return0__0_carry_n_5,mod_sub_return0__0_carry_n_6,NLW_mod_sub_return0__0_carry_O_UNCONNECTED[0]}), .S(\rise_trail_center_offset_r_reg[3]_0 )); CARRY4 mod_sub_return0__0_carry__0 (.CI(mod_sub_return0__0_carry_n_0), .CO({NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0__0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\edge_diff_r_reg[0]_0 [4]}), .O({NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__0_carry__0_n_6,mod_sub_return0__0_carry__0_n_7}), .S({1'b0,1'b0,\rise_trail_center_offset_r_reg[5]_0 })); CARRY4 mod_sub_return0_carry (.CI(1'b0), .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}), .CYINIT(1'b1), .DI({Q[3],\edge_diff_r_reg[0]_0 [2:0]}), .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}), .S({mod_sub_return0_carry_i_1_n_0,\rise_trail_center_offset_r_reg[2]_0 })); CARRY4 mod_sub_return0_carry__0 (.CI(mod_sub_return0_carry_n_0), .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,mod_sub_return0_carry__0_i_1_n_0}), .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}), .S({1'b0,1'b0,\rise_lead_center_offset_r_reg[4]_1 })); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry__0_i_1 (.I0(Q[4]), .I1(\edge_diff_r_reg[0]_0 [4]), .O(mod_sub_return0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h6)) mod_sub_return0_carry_i_1 (.I0(\edge_diff_r_reg[0]_0 [3]), .I1(Q[3]), .O(mod_sub_return0_carry_i_1_n_0)); CARRY4 poc_backup_ns0_carry (.CI(1'b0), .CO({poc_backup_ns0,poc_backup_ns0_carry_n_1,poc_backup_ns0_carry_n_2,poc_backup_ns0_carry_n_3}), .CYINIT(1'b0), .DI({poc_backup_ns0_carry_i_1_n_0,poc_backup_ns0_carry_i_2_n_0,poc_backup_ns0_carry_i_3_n_0,poc_backup_ns0_carry_i_4_n_0}), .O(NLW_poc_backup_ns0_carry_O_UNCONNECTED[3:0]), .S({poc_backup_ns0_carry_i_5_n_0,poc_backup_ns0_carry_i_6_n_0,poc_backup_ns0_carry_i_7_n_0,poc_backup_ns0_carry_i_8_n_0})); LUT6 #( .INIT(64'h154015407FD51540)) poc_backup_ns0_carry_i_1 (.I0(prev_r[7]), .I1(\diff_r_reg_n_0_[6] ), .I2(poc_backup_ns0_carry_i_9_n_0), .I3(\diff_r_reg_n_0_[7] ), .I4(poc_backup_ns0_carry_i_10_n_0), .I5(prev_r[6]), .O(poc_backup_ns0_carry_i_1_n_0)); LUT6 #( .INIT(64'hF00C0C0C580C0C0C)) poc_backup_ns0_carry_i_10 (.I0(\diff_r_reg[2]_0 ), .I1(\diff_r_reg_n_0_[7] ), .I2(\diff_r_reg_n_0_[6] ), .I3(\diff_r_reg_n_0_[4] ), .I4(\diff_r_reg_n_0_[5] ), .I5(\diff_r_reg_n_0_[3] ), .O(poc_backup_ns0_carry_i_10_n_0)); (* SOFT_HLUTNM = "soft_lutpair444" *) LUT2 #( .INIT(4'h1)) poc_backup_ns0_carry_i_11 (.I0(\diff_r_reg_n_0_[6] ), .I1(\diff_r_reg_n_0_[7] ), .O(poc_backup_ns0_carry_i_11_n_0)); (* SOFT_HLUTNM = "soft_lutpair445" *) LUT4 #( .INIT(16'h0001)) poc_backup_ns0_carry_i_12 (.I0(\prev_r_reg[2]_0 [1]), .I1(\prev_r_reg[2]_0 [0]), .I2(\prev_r_reg[2]_0 [2]), .I3(\diff_r_reg_n_0_[3] ), .O(poc_backup_ns0_carry_i_12_n_0)); LUT6 #( .INIT(64'h0FF00FF00FF00F8F)) poc_backup_ns0_carry_i_13 (.I0(\diff_r_reg_n_0_[4] ), .I1(\diff_r_reg_n_0_[5] ), .I2(\diff_r_reg_n_0_[3] ), .I3(\diff_r_reg[2]_0 ), .I4(\diff_r_reg_n_0_[6] ), .I5(\diff_r_reg_n_0_[7] ), .O(poc_backup_ns0_carry_i_13_n_0)); (* SOFT_HLUTNM = "soft_lutpair445" *) LUT4 #( .INIT(16'h6663)) poc_backup_ns0_carry_i_14 (.I0(poc_backup_ns0_carry_i_15_n_0), .I1(\prev_r_reg[2]_0 [2]), .I2(\prev_r_reg[2]_0 [0]), .I3(\prev_r_reg[2]_0 [1]), .O(poc_backup_ns0_carry_i_14_n_0)); (* SOFT_HLUTNM = "soft_lutpair444" *) LUT5 #( .INIT(32'h01111111)) poc_backup_ns0_carry_i_15 (.I0(\diff_r_reg_n_0_[7] ), .I1(\diff_r_reg_n_0_[6] ), .I2(\diff_r_reg_n_0_[4] ), .I3(\diff_r_reg_n_0_[5] ), .I4(\diff_r_reg_n_0_[3] ), .O(poc_backup_ns0_carry_i_15_n_0)); LUT6 #( .INIT(64'hA556A956A956A956)) poc_backup_ns0_carry_i_16 (.I0(prev_r[3]), .I1(poc_backup_ns0_carry_i_11_n_0), .I2(\diff_r_reg[2]_0 ), .I3(\diff_r_reg_n_0_[3] ), .I4(\diff_r_reg_n_0_[5] ), .I5(\diff_r_reg_n_0_[4] ), .O(poc_backup_ns0_carry_i_16_n_0)); LUT6 #( .INIT(64'h44541101C5F45351)) poc_backup_ns0_carry_i_2 (.I0(prev_r[5]), .I1(poc_backup_ns0_carry_i_11_n_0), .I2(\diff_r_reg_n_0_[4] ), .I3(poc_backup_ns0_carry_i_12_n_0), .I4(\diff_r_reg_n_0_[5] ), .I5(prev_r[4]), .O(poc_backup_ns0_carry_i_2_n_0)); LUT4 #( .INIT(16'h1117)) poc_backup_ns0_carry_i_3 (.I0(prev_r[3]), .I1(poc_backup_ns0_carry_i_13_n_0), .I2(prev_r[2]), .I3(poc_backup_ns0_carry_i_14_n_0), .O(poc_backup_ns0_carry_i_3_n_0)); LUT5 #( .INIT(32'h5014D45C)) poc_backup_ns0_carry_i_4 (.I0(prev_r[1]), .I1(\prev_r_reg[2]_0 [0]), .I2(\prev_r_reg[2]_0 [1]), .I3(poc_backup_ns0_carry_i_15_n_0), .I4(prev_r[0]), .O(poc_backup_ns0_carry_i_4_n_0)); LUT6 #( .INIT(64'h6A95000000006A95)) poc_backup_ns0_carry_i_5 (.I0(\diff_r_reg_n_0_[7] ), .I1(poc_backup_ns0_carry_i_9_n_0), .I2(\diff_r_reg_n_0_[6] ), .I3(prev_r[7]), .I4(poc_backup_ns0_carry_i_10_n_0), .I5(prev_r[6]), .O(poc_backup_ns0_carry_i_5_n_0)); LUT6 #( .INIT(64'h9006990006900096)) poc_backup_ns0_carry_i_6 (.I0(\diff_r_reg_n_0_[5] ), .I1(prev_r[5]), .I2(poc_backup_ns0_carry_i_11_n_0), .I3(\diff_r_reg_n_0_[4] ), .I4(poc_backup_ns0_carry_i_12_n_0), .I5(prev_r[4]), .O(poc_backup_ns0_carry_i_6_n_0)); LUT6 #( .INIT(64'h828282A02828280A)) poc_backup_ns0_carry_i_7 (.I0(poc_backup_ns0_carry_i_16_n_0), .I1(poc_backup_ns0_carry_i_15_n_0), .I2(\prev_r_reg[2]_0 [2]), .I3(\prev_r_reg[2]_0 [0]), .I4(\prev_r_reg[2]_0 [1]), .I5(prev_r[2]), .O(poc_backup_ns0_carry_i_7_n_0)); LUT5 #( .INIT(32'h960000C3)) poc_backup_ns0_carry_i_8 (.I0(poc_backup_ns0_carry_i_15_n_0), .I1(\prev_r_reg[2]_0 [1]), .I2(prev_r[1]), .I3(\prev_r_reg[2]_0 [0]), .I4(prev_r[0]), .O(poc_backup_ns0_carry_i_8_n_0)); LUT6 #( .INIT(64'h8888888888888880)) poc_backup_ns0_carry_i_9 (.I0(\diff_r_reg_n_0_[5] ), .I1(\diff_r_reg_n_0_[4] ), .I2(\diff_r_reg_n_0_[3] ), .I3(\prev_r_reg[2]_0 [2]), .I4(\prev_r_reg[2]_0 [0]), .I5(\prev_r_reg[2]_0 [1]), .O(poc_backup_ns0_carry_i_9_n_0)); LUT5 #( .INIT(32'h20202220)) poc_backup_r_i_1 (.I0(poc_backup_ns0), .I1(\run_ends_r_reg[1]_0 ), .I2(edge_aligned_r_i_3_n_0), .I3(diffs_eq_r), .I4(edge_aligned_r_i_2_n_0), .O(poc_backup_ns)); FDRE poc_backup_r_reg (.C(CLK), .CE(1'b1), .D(poc_backup_ns), .Q(poc_backup_r_reg_0), .R(1'b0)); FDRE \prev_r_reg[0] (.C(CLK), .CE(done_ns), .D(\prev_r_reg[2]_0 [0]), .Q(prev_r[0]), .R(1'b0)); FDRE \prev_r_reg[1] (.C(CLK), .CE(done_ns), .D(\prev_r_reg[2]_0 [1]), .Q(prev_r[1]), .R(1'b0)); FDRE \prev_r_reg[2] (.C(CLK), .CE(done_ns), .D(\prev_r_reg[2]_0 [2]), .Q(prev_r[2]), .R(1'b0)); FDRE \prev_r_reg[3] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[3] ), .Q(prev_r[3]), .R(1'b0)); FDRE \prev_r_reg[4] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[4] ), .Q(prev_r[4]), .R(1'b0)); FDRE \prev_r_reg[5] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[5] ), .Q(prev_r[5]), .R(1'b0)); FDRE \prev_r_reg[6] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[6] ), .Q(prev_r[6]), .R(1'b0)); FDRE \prev_r_reg[7] (.C(CLK), .CE(done_ns), .D(\diff_r_reg_n_0_[7] ), .Q(prev_r[7]), .R(1'b0)); FDRE \rise_lead_center_offset_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [0]), .Q(Q[0]), .R(1'b0)); FDRE \rise_lead_center_offset_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [1]), .Q(Q[1]), .R(1'b0)); FDRE \rise_lead_center_offset_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [2]), .Q(Q[2]), .R(1'b0)); FDRE \rise_lead_center_offset_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [3]), .Q(Q[3]), .R(1'b0)); FDRE \rise_lead_center_offset_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [4]), .Q(Q[4]), .R(1'b0)); FDRE \rise_lead_center_offset_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rise_lead_r_reg[3]_1 [5]), .Q(Q[5]), .R(1'b0)); FDRE \rise_trail_center_offset_r_reg[0] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [0]), .Q(\edge_diff_r_reg[0]_0 [0]), .R(1'b0)); FDRE \rise_trail_center_offset_r_reg[1] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [1]), .Q(\edge_diff_r_reg[0]_0 [1]), .R(1'b0)); FDRE \rise_trail_center_offset_r_reg[2] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [2]), .Q(\edge_diff_r_reg[0]_0 [2]), .R(1'b0)); FDRE \rise_trail_center_offset_r_reg[3] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [3]), .Q(\edge_diff_r_reg[0]_0 [3]), .R(1'b0)); FDRE \rise_trail_center_offset_r_reg[4] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [4]), .Q(\edge_diff_r_reg[0]_0 [4]), .R(1'b0)); FDRE \rise_trail_center_offset_r_reg[5] (.C(CLK), .CE(1'b1), .D(\rise_trail_r_reg[3]_1 [5]), .Q(\edge_diff_r_reg[0]_0 [5]), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r2_reg_srl3 " *) SRL16E run_end_r2_reg_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(samps_zero_r_reg_0), .Q(run_end_r2_reg_srl3_n_0)); FDRE run_end_r3_reg (.C(CLK), .CE(1'b1), .D(run_end_r2_reg_srl3_n_0), .Q(run_end_r3), .R(1'b0)); LUT5 #( .INIT(32'h0000DACA)) \run_ends_r[0]_i_1 (.I0(\prev_r_reg[0]_0 ), .I1(\prev_r_reg[0]_1 ), .I2(run_end_r3), .I3(run_polarity_held_r), .I4(reset_run_ends), .O(\run_ends_r[0]_i_1_n_0 )); LUT3 #( .INIT(8'hFB)) \run_ends_r[0]_i_2 (.I0(run_too_small_r3), .I1(ocd_edge_detect_rdy_r_reg), .I2(rstdiv0_sync_r1_reg_rep__20), .O(reset_run_ends)); LUT6 #( .INIT(64'h0000000000EC0000)) \run_ends_r[1]_i_1 (.I0(\prev_r_reg[0]_0 ), .I1(\prev_r_reg[0]_1 ), .I2(run_end_r3), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_edge_detect_rdy_r_reg), .I5(run_too_small_r3), .O(\run_ends_r[1]_i_1_n_0 )); FDRE \run_ends_r_reg[0] (.C(CLK), .CE(1'b1), .D(\run_ends_r[0]_i_1_n_0 ), .Q(\prev_r_reg[0]_0 ), .R(1'b0)); FDRE \run_ends_r_reg[1] (.C(CLK), .CE(1'b1), .D(\run_ends_r[1]_i_1_n_0 ), .Q(\prev_r_reg[0]_1 ), .R(1'b0)); FDRE run_polarity_held_r_reg (.C(CLK), .CE(1'b1), .D(samps_zero_r_reg), .Q(run_polarity_held_r), .R(1'b0)); (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r2_reg_srl2 " *) SRL16E run_too_small_r2_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(run_too_small_r10), .Q(run_too_small_r2_reg_srl2_n_0)); LUT3 #( .INIT(8'h08)) run_too_small_r2_reg_srl2_i_1 (.I0(run_too_small_r_reg), .I1(\prev_r_reg[0]_0 ), .I2(\prev_r_reg[0]_1 ), .O(run_too_small_r10)); FDRE run_too_small_r3_reg (.C(CLK), .CE(1'b1), .D(run_too_small_r2_reg_srl2_n_0), .Q(run_too_small_r3), .R(1'b0)); FDRE \window_center_r_reg[0] (.C(CLK), .CE(1'b1), .D(center0_return0[0]), .Q(\diff_r_reg[7]_1 [0]), .R(1'b0)); FDRE \window_center_r_reg[1] (.C(CLK), .CE(1'b1), .D(center0_return0[1]), .Q(\diff_r_reg[7]_1 [1]), .R(1'b0)); FDRE \window_center_r_reg[2] (.C(CLK), .CE(1'b1), .D(center0_return0[2]), .Q(\diff_r_reg[7]_1 [2]), .R(1'b0)); FDRE \window_center_r_reg[3] (.C(CLK), .CE(1'b1), .D(center0_return0[3]), .Q(\diff_r_reg[7]_1 [3]), .R(1'b0)); FDRE \window_center_r_reg[4] (.C(CLK), .CE(1'b1), .D(center0_return0[4]), .Q(\diff_r_reg[7]_1 [4]), .R(1'b0)); FDRE \window_center_r_reg[5] (.C(CLK), .CE(1'b1), .D(center0_return0[5]), .Q(\diff_r_reg[7]_1 [5]), .R(1'b0)); FDRE \window_center_r_reg[6] (.C(CLK), .CE(1'b1), .D(center0_return0[6]), .Q(\diff_r_reg[7]_1 [6]), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_poc_pd (pd_out_pre, mmcm_ps_clk, in_dqs_lpbk_to_iddr_0, rst_sync_r1, CLK); output [0:0]pd_out_pre; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_0; input rst_sync_r1; input CLK; wire CLK; wire in_dqs_lpbk_to_iddr_0; wire mmcm_ps_clk; wire [0:0]pd_out_pre; wire pos_edge_samp; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(pos_edge_samp), .R(1'b0)); FDRE pd_out_r_reg (.C(CLK), .CE(1'b1), .D(pos_edge_samp), .Q(pd_out_pre), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_0), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_if_mig_7series_v4_0_poc_pd_3 (pd_out_pre, mmcm_ps_clk, in_dqs_lpbk_to_iddr_1, rst_sync_r1, CLK); output [0:0]pd_out_pre; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_1; input rst_sync_r1; input CLK; wire CLK; wire in_dqs_lpbk_to_iddr_1; wire mmcm_ps_clk; wire \no_eXes.pos_edge_samp_reg_n_0 ; wire [0:0]pd_out_pre; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(\no_eXes.pos_edge_samp_reg_n_0 ), .R(1'b0)); FDRE pd_out_r_reg (.C(CLK), .CE(1'b1), .D(\no_eXes.pos_edge_samp_reg_n_0 ), .Q(pd_out_pre), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_1), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_if_mig_7series_v4_0_poc_pd_4 (pd_out_pre, mmcm_ps_clk, in_dqs_lpbk_to_iddr_2, rst_sync_r1, CLK); output [0:0]pd_out_pre; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_2; input rst_sync_r1; input CLK; wire CLK; wire in_dqs_lpbk_to_iddr_2; wire mmcm_ps_clk; wire \no_eXes.pos_edge_samp_reg_n_0 ; wire [0:0]pd_out_pre; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(\no_eXes.pos_edge_samp_reg_n_0 ), .R(1'b0)); FDRE pd_out_r_reg (.C(CLK), .CE(1'b1), .D(\no_eXes.pos_edge_samp_reg_n_0 ), .Q(pd_out_pre), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_2), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_poc_pd" *) module ddr3_if_mig_7series_v4_0_poc_pd_5 (pd_out, mmcm_ps_clk, in_dqs_lpbk_to_iddr_3, rst_sync_r1, CLK, pd_out_r_reg_0, \gen_byte_sel_div1.byte_sel_cnt_reg[1] ); output pd_out; input mmcm_ps_clk; input in_dqs_lpbk_to_iddr_3; input rst_sync_r1; input CLK; input [2:0]pd_out_r_reg_0; input [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire CLK; wire [1:0]\gen_byte_sel_div1.byte_sel_cnt_reg[1] ; wire in_dqs_lpbk_to_iddr_3; wire mmcm_ps_clk; wire \no_eXes.pos_edge_samp_reg_n_0 ; wire pd_out; wire [3:3]pd_out_pre; wire [2:0]pd_out_r_reg_0; wire q1; wire rst_sync_r1; wire NLW_u_phase_detector_Q2_UNCONNECTED; FDRE \no_eXes.pos_edge_samp_reg (.C(CLK), .CE(1'b1), .D(q1), .Q(\no_eXes.pos_edge_samp_reg_n_0 ), .R(1'b0)); FDRE pd_out_r_reg (.C(CLK), .CE(1'b1), .D(\no_eXes.pos_edge_samp_reg_n_0 ), .Q(pd_out_pre), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \samps_hi_r[3]_i_7 (.I0(pd_out_pre), .I1(pd_out_r_reg_0[2]), .I2(\gen_byte_sel_div1.byte_sel_cnt_reg[1] [1]), .I3(pd_out_r_reg_0[1]), .I4(\gen_byte_sel_div1.byte_sel_cnt_reg[1] [0]), .I5(pd_out_r_reg_0[0]), .O(pd_out)); (* BOX_TYPE = "PRIMITIVE" *) (* __SRVAL = "FALSE" *) IDDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT_Q1(1'b0), .INIT_Q2(1'b0), .IS_C_INVERTED(1'b0), .IS_D_INVERTED(1'b0), .SRTYPE("SYNC")) u_phase_detector (.C(mmcm_ps_clk), .CE(1'b1), .D(in_dqs_lpbk_to_iddr_3), .Q1(q1), .Q2(NLW_u_phase_detector_Q2_UNCONNECTED), .R(rst_sync_r1), .S(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_poc_tap_base (\run_r_reg[0]_0 , run_too_small_r3_reg, \run_r_reg[0]_1 , \run_r_reg[0]_2 , Q, S, \samp_cntr_r_reg[8]_0 , \samp_cntr_r_reg[12]_0 , \samp_cntr_r_reg[16]_0 , \samps_hi_r_reg[3]_0 , \samps_hi_r_reg[7]_0 , \samps_hi_r_reg[11]_0 , \samps_hi_r_reg[15]_0 , \samps_hi_r_reg[17]_0 , samps_zero_r_reg_0, \tap_r_reg[0]_0 , \run_r_reg[4]_0 , run_too_small_r_reg_0, \rise_trail_r_reg[0] , \sm_r_reg[0]_0 , \sm_r_reg[0]_1 , \qcntr_r_reg[0] , \rise_lead_r_reg[5] , DI, samps_zero_r_reg_1, samps_zero_r_reg_2, samps_zero_r_reg_3, samps_zero_r_reg_4, samps_zero_r_reg_5, \samp_cntr_r_reg[0]_0 , \rise_trail_r_reg[5] , \rise_trail_r_reg[5]_0 , \rise_trail_r_reg[5]_1 , \rise_trail_r_reg[3] , \samp_wait_r_reg[6]_0 , \samp_wait_r_reg[7]_0 , \rise_trail_r_reg[5]_2 , \rise_trail_r_reg[5]_3 , CLK, samps_lo, rstdiv0_sync_r1_reg_rep__20, \run_r_reg[2]_0 , ocd_ktap_left_r_reg, ocd_ktap_right_r_reg, trailing_edge0, trailing_edge00_in, poc_sample_pd, \samp_wait_r_reg[4]_0 , samp_cntr_ns0, samps_hi_ns0, psdone, rstdiv0_sync_r1_reg_rep, D, rstdiv0_sync_r1_reg_rep__0, E); output \run_r_reg[0]_0 ; output run_too_small_r3_reg; output \run_r_reg[0]_1 ; output \run_r_reg[0]_2 ; output [4:0]Q; output [3:0]S; output [3:0]\samp_cntr_r_reg[8]_0 ; output [3:0]\samp_cntr_r_reg[12]_0 ; output [3:0]\samp_cntr_r_reg[16]_0 ; output [2:0]\samps_hi_r_reg[3]_0 ; output [3:0]\samps_hi_r_reg[7]_0 ; output [3:0]\samps_hi_r_reg[11]_0 ; output [3:0]\samps_hi_r_reg[15]_0 ; output [1:0]\samps_hi_r_reg[17]_0 ; output [3:0]samps_zero_r_reg_0; output \tap_r_reg[0]_0 ; output [4:0]\run_r_reg[4]_0 ; output run_too_small_r_reg_0; output [0:0]\rise_trail_r_reg[0] ; output \sm_r_reg[0]_0 ; output \sm_r_reg[0]_1 ; output [0:0]\qcntr_r_reg[0] ; output [5:0]\rise_lead_r_reg[5] ; output [0:0]DI; output [3:0]samps_zero_r_reg_1; output [2:0]samps_zero_r_reg_2; output [2:0]samps_zero_r_reg_3; output [0:0]samps_zero_r_reg_4; output [0:0]samps_zero_r_reg_5; output [0:0]\samp_cntr_r_reg[0]_0 ; output [5:0]\rise_trail_r_reg[5] ; output [0:0]\rise_trail_r_reg[5]_0 ; output [0:0]\rise_trail_r_reg[5]_1 ; output [0:0]\rise_trail_r_reg[3] ; output \samp_wait_r_reg[6]_0 ; output [6:0]\samp_wait_r_reg[7]_0 ; output [0:0]\rise_trail_r_reg[5]_2 ; output [0:0]\rise_trail_r_reg[5]_3 ; input CLK; input [14:0]samps_lo; input rstdiv0_sync_r1_reg_rep__20; input \run_r_reg[2]_0 ; input ocd_ktap_left_r_reg; input ocd_ktap_right_r_reg; input [5:0]trailing_edge0; input [5:0]trailing_edge00_in; input poc_sample_pd; input \samp_wait_r_reg[4]_0 ; input [15:0]samp_cntr_ns0; input [17:0]samps_hi_ns0; input psdone; input rstdiv0_sync_r1_reg_rep; input [1:0]D; input rstdiv0_sync_r1_reg_rep__0; input [0:0]E; wire CLK; wire [1:0]D; wire [0:0]DI; wire [0:0]E; wire [4:0]Q; wire [3:0]S; wire ocd_ktap_left_r_reg; wire ocd_ktap_right_r_reg; wire [5:0]p_0_in; wire [5:0]p_0_in__0; wire [7:0]p_1_in; wire poc_sample_pd; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire [5:0]\rise_lead_r_reg[5] ; wire \rise_trail_r[5]_i_4_n_0 ; wire \rise_trail_r[5]_i_6_n_0 ; wire \rise_trail_r[5]_i_7_n_0 ; wire \rise_trail_r[5]_i_8_n_0 ; wire \rise_trail_r[5]_i_9_n_0 ; wire [0:0]\rise_trail_r_reg[0] ; wire [0:0]\rise_trail_r_reg[3] ; wire [5:0]\rise_trail_r_reg[5] ; wire [0:0]\rise_trail_r_reg[5]_0 ; wire [0:0]\rise_trail_r_reg[5]_1 ; wire [0:0]\rise_trail_r_reg[5]_2 ; wire [0:0]\rise_trail_r_reg[5]_3 ; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire run_polarity_ns2_out; wire \run_r[5]_i_2_n_0 ; wire \run_r_reg[0]_0 ; wire \run_r_reg[0]_1 ; wire \run_r_reg[0]_2 ; wire \run_r_reg[2]_0 ; wire [4:0]\run_r_reg[4]_0 ; wire \run_r_reg_n_0_[5] ; wire run_too_small_ns; wire run_too_small_r3_reg; wire run_too_small_r_reg_0; wire [16:16]samp_cntr; wire [15:0]samp_cntr_ns0; wire \samp_cntr_r[0]_i_1_n_0 ; wire \samp_cntr_r[10]_i_1_n_0 ; wire \samp_cntr_r[11]_i_1_n_0 ; wire \samp_cntr_r[12]_i_1_n_0 ; wire \samp_cntr_r[13]_i_1_n_0 ; wire \samp_cntr_r[14]_i_1_n_0 ; wire \samp_cntr_r[15]_i_1_n_0 ; wire \samp_cntr_r[16]_i_1_n_0 ; wire \samp_cntr_r[1]_i_1_n_0 ; wire \samp_cntr_r[2]_i_1_n_0 ; wire \samp_cntr_r[3]_i_1_n_0 ; wire \samp_cntr_r[4]_i_1_n_0 ; wire \samp_cntr_r[5]_i_1_n_0 ; wire \samp_cntr_r[6]_i_1_n_0 ; wire \samp_cntr_r[7]_i_1_n_0 ; wire \samp_cntr_r[8]_i_1_n_0 ; wire \samp_cntr_r[9]_i_1_n_0 ; wire [0:0]\samp_cntr_r_reg[0]_0 ; wire [3:0]\samp_cntr_r_reg[12]_0 ; wire [3:0]\samp_cntr_r_reg[16]_0 ; wire [3:0]\samp_cntr_r_reg[8]_0 ; wire \samp_cntr_r_reg_n_0_[10] ; wire \samp_cntr_r_reg_n_0_[11] ; wire \samp_cntr_r_reg_n_0_[12] ; wire \samp_cntr_r_reg_n_0_[13] ; wire \samp_cntr_r_reg_n_0_[14] ; wire \samp_cntr_r_reg_n_0_[15] ; wire \samp_cntr_r_reg_n_0_[1] ; wire \samp_cntr_r_reg_n_0_[2] ; wire \samp_cntr_r_reg_n_0_[3] ; wire \samp_cntr_r_reg_n_0_[4] ; wire \samp_cntr_r_reg_n_0_[5] ; wire \samp_cntr_r_reg_n_0_[6] ; wire \samp_cntr_r_reg_n_0_[7] ; wire \samp_cntr_r_reg_n_0_[8] ; wire \samp_cntr_r_reg_n_0_[9] ; wire [5:5]samp_wait_r; wire \samp_wait_r[4]_i_2_n_0 ; wire \samp_wait_r[7]_i_1_n_0 ; wire \samp_wait_r_reg[4]_0 ; wire \samp_wait_r_reg[6]_0 ; wire [6:0]\samp_wait_r_reg[7]_0 ; wire [17:17]samps_hi; wire [17:0]samps_hi_ns0; wire \samps_hi_r[0]_i_1_n_0 ; wire \samps_hi_r[10]_i_1_n_0 ; wire \samps_hi_r[11]_i_1_n_0 ; wire \samps_hi_r[12]_i_1_n_0 ; wire \samps_hi_r[13]_i_1_n_0 ; wire \samps_hi_r[14]_i_1_n_0 ; wire \samps_hi_r[15]_i_1_n_0 ; wire \samps_hi_r[16]_i_1_n_0 ; wire \samps_hi_r[17]_i_1_n_0 ; wire \samps_hi_r[1]_i_1_n_0 ; wire \samps_hi_r[2]_i_1_n_0 ; wire \samps_hi_r[3]_i_1_n_0 ; wire \samps_hi_r[4]_i_1_n_0 ; wire \samps_hi_r[5]_i_1_n_0 ; wire \samps_hi_r[6]_i_1_n_0 ; wire \samps_hi_r[7]_i_1_n_0 ; wire \samps_hi_r[8]_i_1_n_0 ; wire \samps_hi_r[9]_i_1_n_0 ; wire [3:0]\samps_hi_r_reg[11]_0 ; wire [3:0]\samps_hi_r_reg[15]_0 ; wire [1:0]\samps_hi_r_reg[17]_0 ; wire [2:0]\samps_hi_r_reg[3]_0 ; wire [3:0]\samps_hi_r_reg[7]_0 ; wire \samps_hi_r_reg_n_0_[11] ; wire \samps_hi_r_reg_n_0_[12] ; wire \samps_hi_r_reg_n_0_[13] ; wire \samps_hi_r_reg_n_0_[14] ; wire \samps_hi_r_reg_n_0_[15] ; wire \samps_hi_r_reg_n_0_[16] ; wire \samps_hi_r_reg_n_0_[3] ; wire \samps_hi_r_reg_n_0_[4] ; wire \samps_hi_r_reg_n_0_[5] ; wire \samps_hi_r_reg_n_0_[6] ; wire \samps_hi_r_reg_n_0_[7] ; wire \samps_hi_r_reg_n_0_[8] ; wire [14:0]samps_lo; wire samps_one_ns; wire samps_one_r0_carry__0_i_1_n_0; wire samps_one_r0_carry__0_i_2_n_0; wire samps_one_r0_carry__0_i_3_n_0; wire samps_one_r0_carry__0_i_4_n_0; wire samps_one_r0_carry__0_i_5_n_0; wire samps_one_r0_carry__0_i_6_n_0; wire samps_one_r0_carry__0_i_7_n_0; wire samps_one_r0_carry__0_n_0; wire samps_one_r0_carry__0_n_1; wire samps_one_r0_carry__0_n_2; wire samps_one_r0_carry__0_n_3; wire samps_one_r0_carry__1_i_1_n_0; wire samps_one_r0_carry__1_i_2_n_0; wire samps_one_r0_carry_i_1_n_0; wire samps_one_r0_carry_i_2_n_0; wire samps_one_r0_carry_i_3_n_0; wire samps_one_r0_carry_i_4_n_0; wire samps_one_r0_carry_i_5_n_0; wire samps_one_r0_carry_i_6_n_0; wire samps_one_r0_carry_i_7_n_0; wire samps_one_r0_carry_n_0; wire samps_one_r0_carry_n_1; wire samps_one_r0_carry_n_2; wire samps_one_r0_carry_n_3; wire samps_zero_ns; wire samps_zero_r0_carry__0_i_1_n_0; wire samps_zero_r0_carry__0_i_2_n_0; wire samps_zero_r0_carry__0_i_3_n_0; wire samps_zero_r0_carry__0_i_5_n_0; wire samps_zero_r0_carry__0_i_6_n_0; wire samps_zero_r0_carry__0_i_7_n_0; wire samps_zero_r0_carry__0_i_8_n_0; wire samps_zero_r0_carry__0_n_0; wire samps_zero_r0_carry__0_n_1; wire samps_zero_r0_carry__0_n_2; wire samps_zero_r0_carry__0_n_3; wire samps_zero_r0_carry__1_i_1_n_0; wire samps_zero_r0_carry__1_i_2_n_0; wire samps_zero_r0_carry_i_1_n_0; wire samps_zero_r0_carry_i_3_n_0; wire samps_zero_r0_carry_i_4_n_0; wire samps_zero_r0_carry_i_5_n_0; wire samps_zero_r0_carry_i_6_n_0; wire samps_zero_r0_carry_i_7_n_0; wire samps_zero_r0_carry_i_8_n_0; wire samps_zero_r0_carry_n_0; wire samps_zero_r0_carry_n_1; wire samps_zero_r0_carry_n_2; wire samps_zero_r0_carry_n_3; wire [3:0]samps_zero_r_reg_0; wire [3:0]samps_zero_r_reg_1; wire [2:0]samps_zero_r_reg_2; wire [2:0]samps_zero_r_reg_3; wire [0:0]samps_zero_r_reg_4; wire [0:0]samps_zero_r_reg_5; wire sm_ns0_carry__0_i_1_n_0; wire sm_ns0_carry__0_i_2_n_0; wire sm_ns0_carry__0_n_2; wire sm_ns0_carry__0_n_3; wire sm_ns0_carry_i_1_n_0; wire sm_ns0_carry_i_2_n_0; wire sm_ns0_carry_i_3_n_0; wire sm_ns0_carry_i_4_n_0; wire sm_ns0_carry_n_0; wire sm_ns0_carry_n_1; wire sm_ns0_carry_n_2; wire sm_ns0_carry_n_3; wire \sm_r[0]_i_1_n_0 ; wire \sm_r[0]_i_2_n_0 ; wire \sm_r[1]_i_1_n_0 ; wire \sm_r_reg[0]_0 ; wire \sm_r_reg[0]_1 ; wire \tap_r_reg[0]_0 ; wire [5:0]trailing_edge0; wire [5:0]trailing_edge00_in; wire [3:0]NLW_samps_one_r0_carry_O_UNCONNECTED; wire [3:0]NLW_samps_one_r0_carry__0_O_UNCONNECTED; wire [3:1]NLW_samps_one_r0_carry__1_CO_UNCONNECTED; wire [3:0]NLW_samps_one_r0_carry__1_O_UNCONNECTED; wire [3:0]NLW_samps_zero_r0_carry_O_UNCONNECTED; wire [3:0]NLW_samps_zero_r0_carry__0_O_UNCONNECTED; wire [3:1]NLW_samps_zero_r0_carry__1_CO_UNCONNECTED; wire [3:0]NLW_samps_zero_r0_carry__1_O_UNCONNECTED; wire [3:0]NLW_sm_ns0_carry_O_UNCONNECTED; wire [3:2]NLW_sm_ns0_carry__0_CO_UNCONNECTED; wire [3:0]NLW_sm_ns0_carry__0_O_UNCONNECTED; (* SOFT_HLUTNM = "soft_lutpair453" *) LUT3 #( .INIT(8'h04)) \gen_mmcm.mmcm_i_i_1 (.I0(\sm_r_reg[0]_0 ), .I1(\sm_r_reg[0]_1 ), .I2(rstdiv0_sync_r1_reg_rep__20), .O(\qcntr_r_reg[0] )); LUT6 #( .INIT(64'h0000000000000001)) i___12_i_1 (.I0(\samp_wait_r_reg[7]_0 [3]), .I1(\samp_wait_r_reg[7]_0 [0]), .I2(\samp_wait_r_reg[7]_0 [1]), .I3(\samp_wait_r_reg[7]_0 [2]), .I4(\samp_wait_r_reg[7]_0 [4]), .I5(samp_wait_r), .O(\samp_wait_r_reg[6]_0 )); LUT6 #( .INIT(64'h0000000000B80000)) i___7_i_1__0 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\run_r_reg[0]_2 ), .I3(\sm_r_reg[0]_0 ), .I4(\sm_r_reg[0]_1 ), .I5(rstdiv0_sync_r1_reg_rep__20), .O(run_too_small_r_reg_0)); LUT1 #( .INIT(2'h1)) i__carry__0_i_1 (.I0(\run_r_reg[4]_0 [3]), .O(DI)); LUT4 #( .INIT(16'h9699)) i__carry__0_i_2 (.I0(\rise_lead_r_reg[5] [5]), .I1(\run_r_reg_n_0_[5] ), .I2(\rise_lead_r_reg[5] [4]), .I3(\run_r_reg[4]_0 [4]), .O(\rise_trail_r_reg[5]_0 )); LUT2 #( .INIT(4'h6)) i__carry_i_1 (.I0(\rise_lead_r_reg[5] [3]), .I1(\run_r_reg[4]_0 [3]), .O(\rise_trail_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair460" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[0]_i_1 (.I0(trailing_edge0[0]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[0]), .O(\rise_trail_r_reg[5] [0])); (* SOFT_HLUTNM = "soft_lutpair460" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[1]_i_1 (.I0(trailing_edge0[1]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[1]), .O(\rise_trail_r_reg[5] [1])); (* SOFT_HLUTNM = "soft_lutpair459" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[2]_i_1 (.I0(trailing_edge0[2]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[2]), .O(\rise_trail_r_reg[5] [2])); (* SOFT_HLUTNM = "soft_lutpair459" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[3]_i_1 (.I0(trailing_edge0[3]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[3]), .O(\rise_trail_r_reg[5] [3])); (* SOFT_HLUTNM = "soft_lutpair458" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[4]_i_1 (.I0(trailing_edge0[4]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[4]), .O(\rise_trail_r_reg[5] [4])); LUT4 #( .INIT(16'h0008)) \rise_trail_r[5]_i_1 (.I0(\run_r_reg[0]_0 ), .I1(run_too_small_r_reg_0), .I2(ocd_ktap_left_r_reg), .I3(ocd_ktap_right_r_reg), .O(\rise_trail_r_reg[0] )); LUT5 #( .INIT(32'h00800000)) \rise_trail_r[5]_i_1__0 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\tap_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_right_r_reg), .O(\rise_trail_r_reg[5]_2 )); LUT5 #( .INIT(32'h00800000)) \rise_trail_r[5]_i_1__1 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\tap_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_left_r_reg), .O(\rise_trail_r_reg[5]_3 )); (* SOFT_HLUTNM = "soft_lutpair458" *) LUT3 #( .INIT(8'hB8)) \rise_trail_r[5]_i_2 (.I0(trailing_edge0[5]), .I1(\rise_trail_r[5]_i_4_n_0 ), .I2(trailing_edge00_in[5]), .O(\rise_trail_r_reg[5] [5])); LUT6 #( .INIT(64'h88888888A8AA88A8)) \rise_trail_r[5]_i_4 (.I0(\rise_trail_r[5]_i_6_n_0 ), .I1(\rise_trail_r[5]_i_7_n_0 ), .I2(\rise_trail_r[5]_i_8_n_0 ), .I3(\run_r_reg[4]_0 [3]), .I4(\rise_lead_r_reg[5] [3]), .I5(\rise_trail_r[5]_i_9_n_0 ), .O(\rise_trail_r[5]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \rise_trail_r[5]_i_5 (.I0(\run_r_reg_n_0_[5] ), .I1(\rise_lead_r_reg[5] [5]), .O(\rise_trail_r_reg[5]_1 )); (* SOFT_HLUTNM = "soft_lutpair454" *) LUT2 #( .INIT(4'hB)) \rise_trail_r[5]_i_6 (.I0(\rise_lead_r_reg[5] [5]), .I1(\run_r_reg_n_0_[5] ), .O(\rise_trail_r[5]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair454" *) LUT4 #( .INIT(16'h4F44)) \rise_trail_r[5]_i_7 (.I0(\run_r_reg_n_0_[5] ), .I1(\rise_lead_r_reg[5] [5]), .I2(\run_r_reg[4]_0 [4]), .I3(\rise_lead_r_reg[5] [4]), .O(\rise_trail_r[5]_i_7_n_0 )); LUT6 #( .INIT(64'hDF0D4F04DF0DDF0D)) \rise_trail_r[5]_i_8 (.I0(\run_r_reg[4]_0 [1]), .I1(\rise_lead_r_reg[5] [1]), .I2(\run_r_reg[4]_0 [2]), .I3(\rise_lead_r_reg[5] [2]), .I4(\rise_lead_r_reg[5] [0]), .I5(\run_r_reg[4]_0 [0]), .O(\rise_trail_r[5]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair457" *) LUT2 #( .INIT(4'h2)) \rise_trail_r[5]_i_9 (.I0(\run_r_reg[4]_0 [4]), .I1(\rise_lead_r_reg[5] [4]), .O(\rise_trail_r[5]_i_9_n_0 )); LUT6 #( .INIT(64'h5151040055550400)) run_polarity_r_i_1 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\sm_r_reg[0]_1 ), .I2(\sm_r_reg[0]_0 ), .I3(\run_r_reg[0]_2 ), .I4(\run_r_reg[0]_0 ), .I5(\run_r_reg[0]_1 ), .O(run_polarity_ns2_out)); FDRE run_polarity_r_reg (.C(CLK), .CE(1'b1), .D(run_polarity_ns2_out), .Q(\run_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h00000000333347FF)) \run_r[0]_i_1 (.I0(\run_r_reg[0]_1 ), .I1(\run_r_reg[0]_0 ), .I2(\run_r_reg[0]_2 ), .I3(\tap_r_reg[0]_0 ), .I4(rstdiv0_sync_r1_reg_rep__20), .I5(\run_r_reg[4]_0 [0]), .O(p_0_in__0[0])); LUT3 #( .INIT(8'h28)) \run_r[1]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [0]), .I2(\run_r_reg[4]_0 [1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair451" *) LUT4 #( .INIT(16'h2A80)) \run_r[2]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [1]), .I2(\run_r_reg[4]_0 [0]), .I3(\run_r_reg[4]_0 [2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair451" *) LUT5 #( .INIT(32'h2AAA8000)) \run_r[3]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [0]), .I2(\run_r_reg[4]_0 [1]), .I3(\run_r_reg[4]_0 [2]), .I4(\run_r_reg[4]_0 [3]), .O(p_0_in__0[3])); LUT6 #( .INIT(64'h2AAAAAAA80000000)) \run_r[4]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[4]_0 [2]), .I2(\run_r_reg[4]_0 [1]), .I3(\run_r_reg[4]_0 [0]), .I4(\run_r_reg[4]_0 [3]), .I5(\run_r_reg[4]_0 [4]), .O(p_0_in__0[4])); (* SOFT_HLUTNM = "soft_lutpair457" *) LUT4 #( .INIT(16'h8A20)) \run_r[5]_i_1 (.I0(\run_r[5]_i_2_n_0 ), .I1(\run_r_reg[2]_0 ), .I2(\run_r_reg[4]_0 [4]), .I3(\run_r_reg_n_0_[5] ), .O(p_0_in__0[5])); LUT6 #( .INIT(64'h5151FBFF5555FBFF)) \run_r[5]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__20), .I1(\sm_r_reg[0]_1 ), .I2(\sm_r_reg[0]_0 ), .I3(\run_r_reg[0]_2 ), .I4(\run_r_reg[0]_0 ), .I5(\run_r_reg[0]_1 ), .O(\run_r[5]_i_2_n_0 )); FDRE \run_r_reg[0] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[0]), .Q(\run_r_reg[4]_0 [0]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \run_r_reg[1] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[1]), .Q(\run_r_reg[4]_0 [1]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \run_r_reg[2] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[2]), .Q(\run_r_reg[4]_0 [2]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \run_r_reg[3] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[3]), .Q(\run_r_reg[4]_0 [3]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \run_r_reg[4] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[4]), .Q(\run_r_reg[4]_0 [4]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \run_r_reg[5] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in__0[5]), .Q(\run_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep)); LUT6 #( .INIT(64'h0002020202020202)) run_too_small_r_i_1 (.I0(run_too_small_r_reg_0), .I1(\run_r_reg[4]_0 [4]), .I2(\run_r_reg_n_0_[5] ), .I3(\run_r_reg[4]_0 [3]), .I4(\run_r_reg[4]_0 [2]), .I5(\run_r_reg[4]_0 [1]), .O(run_too_small_ns)); FDRE run_too_small_r_reg (.C(CLK), .CE(1'b1), .D(run_too_small_ns), .Q(run_too_small_r3_reg), .R(1'b0)); LUT2 #( .INIT(4'h1)) \samp_cntr_r[0]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\samp_cntr_r_reg[0]_0 ), .O(\samp_cntr_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair477" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[10]_i_1 (.I0(samp_cntr_ns0[9]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair469" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[11]_i_1 (.I0(samp_cntr_ns0[10]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair472" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[12]_i_1 (.I0(samp_cntr_ns0[11]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[12]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_3 (.I0(\samp_cntr_r_reg_n_0_[12] ), .O(\samp_cntr_r_reg[12]_0 [3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_4 (.I0(\samp_cntr_r_reg_n_0_[11] ), .O(\samp_cntr_r_reg[12]_0 [2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_5 (.I0(\samp_cntr_r_reg_n_0_[10] ), .O(\samp_cntr_r_reg[12]_0 [1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[12]_i_6 (.I0(\samp_cntr_r_reg_n_0_[9] ), .O(\samp_cntr_r_reg[12]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair473" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[13]_i_1 (.I0(samp_cntr_ns0[12]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair473" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[14]_i_1 (.I0(samp_cntr_ns0[13]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair476" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[15]_i_1 (.I0(samp_cntr_ns0[14]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair474" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[16]_i_1 (.I0(samp_cntr_ns0[15]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[16]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_3 (.I0(samp_cntr), .O(\samp_cntr_r_reg[16]_0 [3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_4 (.I0(\samp_cntr_r_reg_n_0_[15] ), .O(\samp_cntr_r_reg[16]_0 [2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_5 (.I0(\samp_cntr_r_reg_n_0_[14] ), .O(\samp_cntr_r_reg[16]_0 [1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[16]_i_6 (.I0(\samp_cntr_r_reg_n_0_[13] ), .O(\samp_cntr_r_reg[16]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair466" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[1]_i_1 (.I0(samp_cntr_ns0[0]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair464" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[2]_i_1 (.I0(samp_cntr_ns0[1]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair468" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[3]_i_1 (.I0(samp_cntr_ns0[2]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair477" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[4]_i_1 (.I0(samp_cntr_ns0[3]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[4]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_3 (.I0(\samp_cntr_r_reg_n_0_[4] ), .O(S[3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_4 (.I0(\samp_cntr_r_reg_n_0_[3] ), .O(S[2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_5 (.I0(\samp_cntr_r_reg_n_0_[2] ), .O(S[1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[4]_i_6 (.I0(\samp_cntr_r_reg_n_0_[1] ), .O(S[0])); (* SOFT_HLUTNM = "soft_lutpair467" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[5]_i_1 (.I0(samp_cntr_ns0[4]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair471" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[6]_i_1 (.I0(samp_cntr_ns0[5]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair475" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[7]_i_1 (.I0(samp_cntr_ns0[6]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair462" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[8]_i_1 (.I0(samp_cntr_ns0[7]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[8]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_3 (.I0(\samp_cntr_r_reg_n_0_[8] ), .O(\samp_cntr_r_reg[8]_0 [3])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_4 (.I0(\samp_cntr_r_reg_n_0_[7] ), .O(\samp_cntr_r_reg[8]_0 [2])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_5 (.I0(\samp_cntr_r_reg_n_0_[6] ), .O(\samp_cntr_r_reg[8]_0 [1])); LUT1 #( .INIT(2'h2)) \samp_cntr_r[8]_i_6 (.I0(\samp_cntr_r_reg_n_0_[5] ), .O(\samp_cntr_r_reg[8]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair465" *) LUT2 #( .INIT(4'h2)) \samp_cntr_r[9]_i_1 (.I0(samp_cntr_ns0[8]), .I1(\sm_r_reg[0]_1 ), .O(\samp_cntr_r[9]_i_1_n_0 )); FDRE \samp_cntr_r_reg[0] (.C(CLK), .CE(E), .D(\samp_cntr_r[0]_i_1_n_0 ), .Q(\samp_cntr_r_reg[0]_0 ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[10] (.C(CLK), .CE(E), .D(\samp_cntr_r[10]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[10] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[11] (.C(CLK), .CE(E), .D(\samp_cntr_r[11]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[11] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[12] (.C(CLK), .CE(E), .D(\samp_cntr_r[12]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[12] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[13] (.C(CLK), .CE(E), .D(\samp_cntr_r[13]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[13] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[14] (.C(CLK), .CE(E), .D(\samp_cntr_r[14]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[14] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[15] (.C(CLK), .CE(E), .D(\samp_cntr_r[15]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[15] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[16] (.C(CLK), .CE(E), .D(\samp_cntr_r[16]_i_1_n_0 ), .Q(samp_cntr), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[1] (.C(CLK), .CE(E), .D(\samp_cntr_r[1]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[1] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[2] (.C(CLK), .CE(E), .D(\samp_cntr_r[2]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[2] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[3] (.C(CLK), .CE(E), .D(\samp_cntr_r[3]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[4] (.C(CLK), .CE(E), .D(\samp_cntr_r[4]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[5] (.C(CLK), .CE(E), .D(\samp_cntr_r[5]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[6] (.C(CLK), .CE(E), .D(\samp_cntr_r[6]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[7] (.C(CLK), .CE(E), .D(\samp_cntr_r[7]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[8] (.C(CLK), .CE(E), .D(\samp_cntr_r[8]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samp_cntr_r_reg[9] (.C(CLK), .CE(E), .D(\samp_cntr_r[9]_i_1_n_0 ), .Q(\samp_cntr_r_reg_n_0_[9] ), .R(rstdiv0_sync_r1_reg_rep__0)); (* SOFT_HLUTNM = "soft_lutpair456" *) LUT3 #( .INIT(8'h8F)) \samp_wait_r[0]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[7]_0 [0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair456" *) LUT4 #( .INIT(16'hF88F)) \samp_wait_r[1]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[7]_0 [1]), .I3(\samp_wait_r_reg[7]_0 [0]), .O(p_1_in[1])); LUT6 #( .INIT(64'hFFFFFFFEAAAAAAAB)) \samp_wait_r[4]_i_1 (.I0(\samp_wait_r[4]_i_2_n_0 ), .I1(\samp_wait_r_reg[7]_0 [3]), .I2(\samp_wait_r_reg[7]_0 [0]), .I3(\samp_wait_r_reg[7]_0 [1]), .I4(\samp_wait_r_reg[7]_0 [2]), .I5(\samp_wait_r_reg[7]_0 [4]), .O(p_1_in[4])); (* SOFT_HLUTNM = "soft_lutpair455" *) LUT2 #( .INIT(4'h8)) \samp_wait_r[4]_i_2 (.I0(\sm_r_reg[0]_0 ), .I1(\sm_r_reg[0]_1 ), .O(\samp_wait_r[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair455" *) LUT4 #( .INIT(16'h8FF8)) \samp_wait_r[5]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[4]_0 ), .I3(samp_wait_r), .O(p_1_in[5])); (* SOFT_HLUTNM = "soft_lutpair450" *) LUT4 #( .INIT(16'h8FF8)) \samp_wait_r[6]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[6]_0 ), .I3(\samp_wait_r_reg[7]_0 [5]), .O(p_1_in[6])); LUT5 #( .INIT(32'hFFFFFF8F)) \samp_wait_r[7]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[6]_0 ), .I3(\samp_wait_r_reg[7]_0 [5]), .I4(\samp_wait_r_reg[7]_0 [6]), .O(\samp_wait_r[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair450" *) LUT5 #( .INIT(32'hFF8F88F8)) \samp_wait_r[7]_i_2 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .I2(\samp_wait_r_reg[6]_0 ), .I3(\samp_wait_r_reg[7]_0 [5]), .I4(\samp_wait_r_reg[7]_0 [6]), .O(p_1_in[7])); FDRE \samp_wait_r_reg[0] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[0]), .Q(\samp_wait_r_reg[7]_0 [0]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[1] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[1]), .Q(\samp_wait_r_reg[7]_0 [1]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[2] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(D[0]), .Q(\samp_wait_r_reg[7]_0 [2]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[3] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(D[1]), .Q(\samp_wait_r_reg[7]_0 [3]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[4] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[4]), .Q(\samp_wait_r_reg[7]_0 [4]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[5] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[5]), .Q(samp_wait_r), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[6] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[6]), .Q(\samp_wait_r_reg[7]_0 [5]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \samp_wait_r_reg[7] (.C(CLK), .CE(\samp_wait_r[7]_i_1_n_0 ), .D(p_1_in[7]), .Q(\samp_wait_r_reg[7]_0 [6]), .R(rstdiv0_sync_r1_reg_rep)); (* SOFT_HLUTNM = "soft_lutpair474" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[0]_i_1 (.I0(samps_hi_ns0[0]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair470" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[10]_i_1 (.I0(samps_hi_ns0[10]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair468" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[11]_i_1 (.I0(samps_hi_ns0[11]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[11]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_3 (.I0(\samps_hi_r_reg_n_0_[11] ), .O(\samps_hi_r_reg[11]_0 [3])); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_4 (.I0(Q[4]), .O(\samps_hi_r_reg[11]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_5 (.I0(Q[3]), .O(\samps_hi_r_reg[11]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[11]_i_6 (.I0(\samps_hi_r_reg_n_0_[8] ), .O(\samps_hi_r_reg[11]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair467" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[12]_i_1 (.I0(samps_hi_ns0[12]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair462" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[13]_i_1 (.I0(samps_hi_ns0[13]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair466" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[14]_i_1 (.I0(samps_hi_ns0[14]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair464" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[15]_i_1 (.I0(samps_hi_ns0[15]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[15]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_3 (.I0(\samps_hi_r_reg_n_0_[15] ), .O(\samps_hi_r_reg[15]_0 [3])); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_4 (.I0(\samps_hi_r_reg_n_0_[14] ), .O(\samps_hi_r_reg[15]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_5 (.I0(\samps_hi_r_reg_n_0_[13] ), .O(\samps_hi_r_reg[15]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[15]_i_6 (.I0(\samps_hi_r_reg_n_0_[12] ), .O(\samps_hi_r_reg[15]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair463" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[16]_i_1 (.I0(samps_hi_ns0[16]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[16]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair461" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[17]_i_1 (.I0(samps_hi_ns0[17]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[17]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[17]_i_3 (.I0(samps_hi), .O(\samps_hi_r_reg[17]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[17]_i_4 (.I0(\samps_hi_r_reg_n_0_[16] ), .O(\samps_hi_r_reg[17]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair463" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[1]_i_1 (.I0(samps_hi_ns0[1]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair461" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[2]_i_1 (.I0(samps_hi_ns0[2]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair470" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[3]_i_1 (.I0(samps_hi_ns0[3]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[3]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[3]_i_3 (.I0(\samps_hi_r_reg_n_0_[3] ), .O(\samps_hi_r_reg[3]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[3]_i_4 (.I0(Q[2]), .O(\samps_hi_r_reg[3]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[3]_i_5 (.I0(Q[1]), .O(\samps_hi_r_reg[3]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair476" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[4]_i_1 (.I0(samps_hi_ns0[4]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair469" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[5]_i_1 (.I0(samps_hi_ns0[5]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair475" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[6]_i_1 (.I0(samps_hi_ns0[6]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair472" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[7]_i_1 (.I0(samps_hi_ns0[7]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[7]_i_1_n_0 )); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_3 (.I0(\samps_hi_r_reg_n_0_[7] ), .O(\samps_hi_r_reg[7]_0 [3])); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_4 (.I0(\samps_hi_r_reg_n_0_[6] ), .O(\samps_hi_r_reg[7]_0 [2])); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_5 (.I0(\samps_hi_r_reg_n_0_[5] ), .O(\samps_hi_r_reg[7]_0 [1])); LUT1 #( .INIT(2'h2)) \samps_hi_r[7]_i_6 (.I0(\samps_hi_r_reg_n_0_[4] ), .O(\samps_hi_r_reg[7]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair471" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[8]_i_1 (.I0(samps_hi_ns0[8]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair465" *) LUT2 #( .INIT(4'h2)) \samps_hi_r[9]_i_1 (.I0(samps_hi_ns0[9]), .I1(\sm_r_reg[0]_1 ), .O(\samps_hi_r[9]_i_1_n_0 )); FDRE \samps_hi_r_reg[0] (.C(CLK), .CE(E), .D(\samps_hi_r[0]_i_1_n_0 ), .Q(Q[0]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[10] (.C(CLK), .CE(E), .D(\samps_hi_r[10]_i_1_n_0 ), .Q(Q[4]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[11] (.C(CLK), .CE(E), .D(\samps_hi_r[11]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[11] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[12] (.C(CLK), .CE(E), .D(\samps_hi_r[12]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[12] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[13] (.C(CLK), .CE(E), .D(\samps_hi_r[13]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[13] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[14] (.C(CLK), .CE(E), .D(\samps_hi_r[14]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[14] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[15] (.C(CLK), .CE(E), .D(\samps_hi_r[15]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[15] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[16] (.C(CLK), .CE(E), .D(\samps_hi_r[16]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[16] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[17] (.C(CLK), .CE(E), .D(\samps_hi_r[17]_i_1_n_0 ), .Q(samps_hi), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[1] (.C(CLK), .CE(E), .D(\samps_hi_r[1]_i_1_n_0 ), .Q(Q[1]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[2] (.C(CLK), .CE(E), .D(\samps_hi_r[2]_i_1_n_0 ), .Q(Q[2]), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[3] (.C(CLK), .CE(E), .D(\samps_hi_r[3]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[3] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[4] (.C(CLK), .CE(E), .D(\samps_hi_r[4]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[4] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[5] (.C(CLK), .CE(E), .D(\samps_hi_r[5]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[5] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[6] (.C(CLK), .CE(E), .D(\samps_hi_r[6]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[6] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[7] (.C(CLK), .CE(E), .D(\samps_hi_r[7]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[7] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[8] (.C(CLK), .CE(E), .D(\samps_hi_r[8]_i_1_n_0 ), .Q(\samps_hi_r_reg_n_0_[8] ), .R(rstdiv0_sync_r1_reg_rep__0)); FDRE \samps_hi_r_reg[9] (.C(CLK), .CE(E), .D(\samps_hi_r[9]_i_1_n_0 ), .Q(Q[3]), .R(rstdiv0_sync_r1_reg_rep__0)); CARRY4 samps_one_r0_carry (.CI(1'b0), .CO({samps_one_r0_carry_n_0,samps_one_r0_carry_n_1,samps_one_r0_carry_n_2,samps_one_r0_carry_n_3}), .CYINIT(1'b1), .DI({samps_one_r0_carry_i_1_n_0,\samps_hi_r_reg_n_0_[5] ,samps_one_r0_carry_i_2_n_0,samps_one_r0_carry_i_3_n_0}), .O(NLW_samps_one_r0_carry_O_UNCONNECTED[3:0]), .S({samps_one_r0_carry_i_4_n_0,samps_one_r0_carry_i_5_n_0,samps_one_r0_carry_i_6_n_0,samps_one_r0_carry_i_7_n_0})); CARRY4 samps_one_r0_carry__0 (.CI(samps_one_r0_carry_n_0), .CO({samps_one_r0_carry__0_n_0,samps_one_r0_carry__0_n_1,samps_one_r0_carry__0_n_2,samps_one_r0_carry__0_n_3}), .CYINIT(1'b0), .DI({samps_one_r0_carry__0_i_1_n_0,samps_one_r0_carry__0_i_2_n_0,samps_one_r0_carry__0_i_3_n_0,Q[3]}), .O(NLW_samps_one_r0_carry__0_O_UNCONNECTED[3:0]), .S({samps_one_r0_carry__0_i_4_n_0,samps_one_r0_carry__0_i_5_n_0,samps_one_r0_carry__0_i_6_n_0,samps_one_r0_carry__0_i_7_n_0})); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__0_i_1 (.I0(\samps_hi_r_reg_n_0_[15] ), .I1(\samps_hi_r_reg_n_0_[14] ), .O(samps_one_r0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__0_i_2 (.I0(\samps_hi_r_reg_n_0_[13] ), .I1(\samps_hi_r_reg_n_0_[12] ), .O(samps_one_r0_carry__0_i_2_n_0)); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__0_i_3 (.I0(\samps_hi_r_reg_n_0_[11] ), .I1(Q[4]), .O(samps_one_r0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__0_i_4 (.I0(\samps_hi_r_reg_n_0_[14] ), .I1(\samps_hi_r_reg_n_0_[15] ), .O(samps_one_r0_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__0_i_5 (.I0(\samps_hi_r_reg_n_0_[12] ), .I1(\samps_hi_r_reg_n_0_[13] ), .O(samps_one_r0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__0_i_6 (.I0(Q[4]), .I1(\samps_hi_r_reg_n_0_[11] ), .O(samps_one_r0_carry__0_i_6_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry__0_i_7 (.I0(\samps_hi_r_reg_n_0_[8] ), .I1(Q[3]), .O(samps_one_r0_carry__0_i_7_n_0)); CARRY4 samps_one_r0_carry__1 (.CI(samps_one_r0_carry__0_n_0), .CO({NLW_samps_one_r0_carry__1_CO_UNCONNECTED[3:1],samps_one_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_1_n_0}), .O(NLW_samps_one_r0_carry__1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_2_n_0})); LUT2 #( .INIT(4'hE)) samps_one_r0_carry__1_i_1 (.I0(samps_hi), .I1(\samps_hi_r_reg_n_0_[16] ), .O(samps_one_r0_carry__1_i_1_n_0)); LUT2 #( .INIT(4'h1)) samps_one_r0_carry__1_i_2 (.I0(\samps_hi_r_reg_n_0_[16] ), .I1(samps_hi), .O(samps_one_r0_carry__1_i_2_n_0)); LUT2 #( .INIT(4'h8)) samps_one_r0_carry_i_1 (.I0(\samps_hi_r_reg_n_0_[7] ), .I1(\samps_hi_r_reg_n_0_[6] ), .O(samps_one_r0_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) samps_one_r0_carry_i_2 (.I0(\samps_hi_r_reg_n_0_[3] ), .I1(Q[2]), .O(samps_one_r0_carry_i_2_n_0)); LUT2 #( .INIT(4'h8)) samps_one_r0_carry_i_3 (.I0(Q[0]), .I1(Q[1]), .O(samps_one_r0_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_4 (.I0(\samps_hi_r_reg_n_0_[7] ), .I1(\samps_hi_r_reg_n_0_[6] ), .O(samps_one_r0_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_5 (.I0(\samps_hi_r_reg_n_0_[4] ), .I1(\samps_hi_r_reg_n_0_[5] ), .O(samps_one_r0_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_6 (.I0(\samps_hi_r_reg_n_0_[3] ), .I1(Q[2]), .O(samps_one_r0_carry_i_6_n_0)); LUT2 #( .INIT(4'h2)) samps_one_r0_carry_i_7 (.I0(Q[1]), .I1(Q[0]), .O(samps_one_r0_carry_i_7_n_0)); FDRE samps_one_r_reg (.C(CLK), .CE(1'b1), .D(samps_one_ns), .Q(\run_r_reg[0]_2 ), .R(1'b0)); CARRY4 samps_zero_r0_carry (.CI(1'b0), .CO({samps_zero_r0_carry_n_0,samps_zero_r0_carry_n_1,samps_zero_r0_carry_n_2,samps_zero_r0_carry_n_3}), .CYINIT(1'b1), .DI({samps_zero_r0_carry_i_1_n_0,samps_lo[2],samps_zero_r0_carry_i_3_n_0,samps_zero_r0_carry_i_4_n_0}), .O(NLW_samps_zero_r0_carry_O_UNCONNECTED[3:0]), .S({samps_zero_r0_carry_i_5_n_0,samps_zero_r0_carry_i_6_n_0,samps_zero_r0_carry_i_7_n_0,samps_zero_r0_carry_i_8_n_0})); CARRY4 samps_zero_r0_carry__0 (.CI(samps_zero_r0_carry_n_0), .CO({samps_zero_r0_carry__0_n_0,samps_zero_r0_carry__0_n_1,samps_zero_r0_carry__0_n_2,samps_zero_r0_carry__0_n_3}), .CYINIT(1'b0), .DI({samps_zero_r0_carry__0_i_1_n_0,samps_zero_r0_carry__0_i_2_n_0,samps_zero_r0_carry__0_i_3_n_0,samps_lo[6]}), .O(NLW_samps_zero_r0_carry__0_O_UNCONNECTED[3:0]), .S({samps_zero_r0_carry__0_i_5_n_0,samps_zero_r0_carry__0_i_6_n_0,samps_zero_r0_carry__0_i_7_n_0,samps_zero_r0_carry__0_i_8_n_0})); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__0_i_1 (.I0(samps_lo[12]), .I1(samps_lo[11]), .O(samps_zero_r0_carry__0_i_1_n_0)); LUT1 #( .INIT(2'h2)) samps_zero_r0_carry__0_i_11 (.I0(Q[3]), .O(samps_zero_r_reg_0[3])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_12 (.I0(\samps_hi_r_reg_n_0_[8] ), .O(samps_zero_r_reg_0[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_13 (.I0(\samps_hi_r_reg_n_0_[7] ), .O(samps_zero_r_reg_0[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_14 (.I0(\samps_hi_r_reg_n_0_[6] ), .O(samps_zero_r_reg_0[0])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_15 (.I0(samps_hi), .O(samps_zero_r_reg_1[3])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_16 (.I0(\samps_hi_r_reg_n_0_[16] ), .O(samps_zero_r_reg_1[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_17 (.I0(\samps_hi_r_reg_n_0_[15] ), .O(samps_zero_r_reg_1[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_18 (.I0(\samps_hi_r_reg_n_0_[14] ), .O(samps_zero_r_reg_1[0])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_19 (.I0(Q[3]), .O(samps_zero_r_reg_5)); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__0_i_2 (.I0(samps_lo[10]), .I1(samps_lo[9]), .O(samps_zero_r0_carry__0_i_2_n_0)); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_20 (.I0(\samps_hi_r_reg_n_0_[13] ), .O(samps_zero_r_reg_2[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_21 (.I0(\samps_hi_r_reg_n_0_[12] ), .O(samps_zero_r_reg_2[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry__0_i_22 (.I0(\samps_hi_r_reg_n_0_[11] ), .O(samps_zero_r_reg_2[0])); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__0_i_3 (.I0(samps_lo[8]), .I1(samps_lo[7]), .O(samps_zero_r0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__0_i_5 (.I0(samps_lo[11]), .I1(samps_lo[12]), .O(samps_zero_r0_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__0_i_6 (.I0(samps_lo[9]), .I1(samps_lo[10]), .O(samps_zero_r0_carry__0_i_6_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__0_i_7 (.I0(samps_lo[7]), .I1(samps_lo[8]), .O(samps_zero_r0_carry__0_i_7_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry__0_i_8 (.I0(samps_lo[5]), .I1(samps_lo[6]), .O(samps_zero_r0_carry__0_i_8_n_0)); CARRY4 samps_zero_r0_carry__1 (.CI(samps_zero_r0_carry__0_n_0), .CO({NLW_samps_zero_r0_carry__1_CO_UNCONNECTED[3:1],samps_zero_ns}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_1_n_0}), .O(NLW_samps_zero_r0_carry__1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_2_n_0})); LUT2 #( .INIT(4'hE)) samps_zero_r0_carry__1_i_1 (.I0(samps_lo[14]), .I1(samps_lo[13]), .O(samps_zero_r0_carry__1_i_1_n_0)); LUT2 #( .INIT(4'h1)) samps_zero_r0_carry__1_i_2 (.I0(samps_lo[13]), .I1(samps_lo[14]), .O(samps_zero_r0_carry__1_i_2_n_0)); LUT2 #( .INIT(4'h8)) samps_zero_r0_carry_i_1 (.I0(samps_lo[4]), .I1(samps_lo[3]), .O(samps_zero_r0_carry_i_1_n_0)); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_10 (.I0(\samps_hi_r_reg_n_0_[5] ), .O(samps_zero_r_reg_3[2])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_11 (.I0(\samps_hi_r_reg_n_0_[4] ), .O(samps_zero_r_reg_3[1])); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_12 (.I0(\samps_hi_r_reg_n_0_[3] ), .O(samps_zero_r_reg_3[0])); LUT3 #( .INIT(8'h28)) samps_zero_r0_carry_i_3 (.I0(samps_lo[0]), .I1(Q[2]), .I2(Q[1]), .O(samps_zero_r0_carry_i_3_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry_i_4 (.I0(Q[1]), .I1(Q[0]), .O(samps_zero_r0_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry_i_5 (.I0(samps_lo[4]), .I1(samps_lo[3]), .O(samps_zero_r0_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) samps_zero_r0_carry_i_6 (.I0(samps_lo[1]), .I1(samps_lo[2]), .O(samps_zero_r0_carry_i_6_n_0)); LUT3 #( .INIT(8'h82)) samps_zero_r0_carry_i_7 (.I0(samps_lo[0]), .I1(Q[2]), .I2(Q[1]), .O(samps_zero_r0_carry_i_7_n_0)); LUT2 #( .INIT(4'h8)) samps_zero_r0_carry_i_8 (.I0(Q[0]), .I1(Q[1]), .O(samps_zero_r0_carry_i_8_n_0)); LUT1 #( .INIT(2'h1)) samps_zero_r0_carry_i_9 (.I0(Q[1]), .O(samps_zero_r_reg_4)); FDRE samps_zero_r_reg (.C(CLK), .CE(1'b1), .D(samps_zero_ns), .Q(\run_r_reg[0]_1 ), .R(1'b0)); CARRY4 sm_ns0_carry (.CI(1'b0), .CO({sm_ns0_carry_n_0,sm_ns0_carry_n_1,sm_ns0_carry_n_2,sm_ns0_carry_n_3}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_sm_ns0_carry_O_UNCONNECTED[3:0]), .S({sm_ns0_carry_i_1_n_0,sm_ns0_carry_i_2_n_0,sm_ns0_carry_i_3_n_0,sm_ns0_carry_i_4_n_0})); CARRY4 sm_ns0_carry__0 (.CI(sm_ns0_carry_n_0), .CO({NLW_sm_ns0_carry__0_CO_UNCONNECTED[3:2],sm_ns0_carry__0_n_2,sm_ns0_carry__0_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_sm_ns0_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,sm_ns0_carry__0_i_1_n_0,sm_ns0_carry__0_i_2_n_0})); LUT2 #( .INIT(4'h1)) sm_ns0_carry__0_i_1 (.I0(samp_cntr), .I1(\samp_cntr_r_reg_n_0_[15] ), .O(sm_ns0_carry__0_i_1_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry__0_i_2 (.I0(\samp_cntr_r_reg_n_0_[13] ), .I1(\samp_cntr_r_reg_n_0_[14] ), .I2(\samp_cntr_r_reg_n_0_[12] ), .O(sm_ns0_carry__0_i_2_n_0)); LUT3 #( .INIT(8'h04)) sm_ns0_carry_i_1 (.I0(\samp_cntr_r_reg_n_0_[11] ), .I1(\samp_cntr_r_reg_n_0_[9] ), .I2(\samp_cntr_r_reg_n_0_[10] ), .O(sm_ns0_carry_i_1_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry_i_2 (.I0(\samp_cntr_r_reg_n_0_[7] ), .I1(\samp_cntr_r_reg_n_0_[8] ), .I2(\samp_cntr_r_reg_n_0_[6] ), .O(sm_ns0_carry_i_2_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry_i_3 (.I0(\samp_cntr_r_reg_n_0_[4] ), .I1(\samp_cntr_r_reg_n_0_[5] ), .I2(\samp_cntr_r_reg_n_0_[3] ), .O(sm_ns0_carry_i_3_n_0)); LUT3 #( .INIT(8'h01)) sm_ns0_carry_i_4 (.I0(\samp_cntr_r_reg_n_0_[1] ), .I1(\samp_cntr_r_reg_n_0_[2] ), .I2(\samp_cntr_r_reg[0]_0 ), .O(sm_ns0_carry_i_4_n_0)); LUT6 #( .INIT(64'h000000002F2A2A2A)) \sm_r[0]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(psdone), .I2(\sm_r_reg[0]_0 ), .I3(\sm_r[0]_i_2_n_0 ), .I4(sm_ns0_carry__0_n_2), .I5(rstdiv0_sync_r1_reg_rep__20), .O(\sm_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h0008)) \sm_r[0]_i_2 (.I0(poc_sample_pd), .I1(\samp_wait_r_reg[6]_0 ), .I2(\samp_wait_r_reg[7]_0 [5]), .I3(\samp_wait_r_reg[7]_0 [6]), .O(\sm_r[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair453" *) LUT4 #( .INIT(16'h007A)) \sm_r[1]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(psdone), .I2(\sm_r_reg[0]_0 ), .I3(rstdiv0_sync_r1_reg_rep__20), .O(\sm_r[1]_i_1_n_0 )); FDRE \sm_r_reg[0] (.C(CLK), .CE(1'b1), .D(\sm_r[0]_i_1_n_0 ), .Q(\sm_r_reg[0]_0 ), .R(1'b0)); FDRE \sm_r_reg[1] (.C(CLK), .CE(1'b1), .D(\sm_r[1]_i_1_n_0 ), .Q(\sm_r_reg[0]_1 ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair452" *) LUT4 #( .INIT(16'h070F)) \tap_r[0]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [0]), .I3(\rise_lead_r_reg[5] [3]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair452" *) LUT5 #( .INIT(32'h07700FF0)) \tap_r[1]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [1]), .I3(\rise_lead_r_reg[5] [0]), .I4(\rise_lead_r_reg[5] [3]), .O(p_0_in[1])); LUT6 #( .INIT(64'h077070700FF0F0F0)) \tap_r[2]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [2]), .I3(\rise_lead_r_reg[5] [1]), .I4(\rise_lead_r_reg[5] [0]), .I5(\rise_lead_r_reg[5] [3]), .O(p_0_in[2])); LUT6 #( .INIT(64'h0770707070707070)) \tap_r[3]_i_1 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [3]), .I3(\rise_lead_r_reg[5] [0]), .I4(\rise_lead_r_reg[5] [1]), .I5(\rise_lead_r_reg[5] [2]), .O(p_0_in[3])); LUT6 #( .INIT(64'h15557FFFC0000000)) \tap_r[4]_i_1 (.I0(\rise_lead_r_reg[5] [5]), .I1(\rise_lead_r_reg[5] [2]), .I2(\rise_lead_r_reg[5] [1]), .I3(\rise_lead_r_reg[5] [0]), .I4(\rise_lead_r_reg[5] [3]), .I5(\rise_lead_r_reg[5] [4]), .O(p_0_in[4])); LUT2 #( .INIT(4'h2)) \tap_r[5]_i_1 (.I0(\sm_r_reg[0]_1 ), .I1(\sm_r_reg[0]_0 ), .O(\tap_r_reg[0]_0 )); LUT6 #( .INIT(64'h644444444CCCCCCC)) \tap_r[5]_i_2 (.I0(\rise_lead_r_reg[5] [4]), .I1(\rise_lead_r_reg[5] [5]), .I2(\rise_lead_r_reg[5] [2]), .I3(\rise_lead_r_reg[5] [1]), .I4(\rise_lead_r_reg[5] [0]), .I5(\rise_lead_r_reg[5] [3]), .O(p_0_in[5])); FDRE \tap_r_reg[0] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[0]), .Q(\rise_lead_r_reg[5] [0]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \tap_r_reg[1] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[1]), .Q(\rise_lead_r_reg[5] [1]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \tap_r_reg[2] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[2]), .Q(\rise_lead_r_reg[5] [2]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \tap_r_reg[3] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[3]), .Q(\rise_lead_r_reg[5] [3]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \tap_r_reg[4] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[4]), .Q(\rise_lead_r_reg[5] [4]), .R(rstdiv0_sync_r1_reg_rep)); FDRE \tap_r_reg[5] (.C(CLK), .CE(\tap_r_reg[0]_0 ), .D(p_0_in[5]), .Q(\rise_lead_r_reg[5] [5]), .R(rstdiv0_sync_r1_reg_rep)); endmodule module ddr3_if_mig_7series_v4_0_poc_top (detect_done_r_reg, \sm_r_reg[1] , poc_backup_r_reg, Q, \mmcm_init_lead_reg[5] , \qcntr_r_reg[0] , \prev_r_reg[0] , \prev_r_reg[0]_0 , CLK, rstdiv0_sync_r1_reg_rep__20, ocd_ktap_left_r_reg, ocd_ktap_right_r_reg, poc_sample_pd, use_noise_window, pd_out, \run_ends_r_reg[1] , ocd_ktap_left_r_reg_0, ocd_edge_detect_rdy_r_reg, psdone, rstdiv0_sync_r1_reg_rep, rstdiv0_sync_r1_reg_rep__0, ninety_offsets); output detect_done_r_reg; output \sm_r_reg[1] ; output poc_backup_r_reg; output [5:0]Q; output [5:0]\mmcm_init_lead_reg[5] ; output [0:0]\qcntr_r_reg[0] ; output \prev_r_reg[0] ; output \prev_r_reg[0]_0 ; input CLK; input rstdiv0_sync_r1_reg_rep__20; input ocd_ktap_left_r_reg; input ocd_ktap_right_r_reg; input poc_sample_pd; input use_noise_window; input pd_out; input \run_ends_r_reg[1] ; input ocd_ktap_left_r_reg_0; input ocd_edge_detect_rdy_r_reg; input psdone; input rstdiv0_sync_r1_reg_rep; input rstdiv0_sync_r1_reg_rep__0; input [1:0]ninety_offsets; wire CLK; wire [5:0]Q; wire center0_return1__0_carry__0_i_4_n_0; wire center0_return1__0_carry__0_i_5_n_0; wire center0_return1__0_carry__0_i_6_n_0; wire center0_return1__0_carry_i_4_n_0; wire center0_return1__0_carry_i_5_n_0; wire center0_return1__0_carry_i_6_n_0; wire center0_return1__1_carry__0_i_4_n_0; wire center0_return1__1_carry__0_i_5_n_0; wire center0_return1__1_carry_i_4_n_0; wire center0_return1__1_carry_i_5_n_0; wire center0_return1__1_carry_i_6_n_0; wire [7:4]center0_return3; wire \center_diff_r_reg[0]_i_2_n_0 ; wire center_return1__0_carry__0_i_2_n_0; wire center_return1__0_carry__0_i_3_n_0; wire center_return1__0_carry__0_i_4_n_0; wire center_return1__0_carry_i_1_n_0; wire center_return1__0_carry_i_2_n_0; wire center_return1__0_carry_i_3_n_0; wire center_return1__1_carry__0_i_2_n_0; wire center_return1__1_carry__0_i_3_n_0; wire center_return1__1_carry_i_1_n_0; wire center_return1__1_carry_i_2_n_0; wire center_return1__1_carry_i_3_n_0; wire [7:4]center_return3; wire detect_done_r_reg; wire [5:1]diff; wire [0:0]diff_ns00_in; wire diff_ns0_carry__0_i_1_n_0; wire diff_ns0_carry__0_i_2_n_0; wire diff_ns1_carry_i_1_n_0; wire diff_ns1_carry_i_2_n_0; wire diff_ns1_carry_i_3_n_0; wire diff_ns1_carry_i_4_n_0; wire diff_ns1_carry_i_5_n_0; wire diff_ns1_carry_i_6_n_0; wire diff_ns1_carry_i_7_n_0; wire [6:0]edge_center; wire \edge_diff_r_reg[0]_i_2_n_0 ; wire fall_lead_r0; wire i___10_n_0; wire i___11_n_0; wire i___12_n_0; wire i___13_n_0; wire i___14_n_0; wire i___15_n_0; wire i___16_n_0; wire i___17_n_0; wire i___18_n_0; wire i___18_rep_n_0; wire i___19_n_0; wire i___19_rep_n_0; wire i___20_n_0; wire i___20_rep__0_n_0; wire i___20_rep_n_0; wire i___21_n_0; wire i___21_rep_n_0; wire i___22_n_0; wire i___23_n_0; wire i___24_n_0; wire i___25_n_0; wire i___25_rep_n_0; wire i___26_n_0; wire i___26_rep__0_n_0; wire i___26_rep_n_0; wire i___27_n_0; wire i___28_n_0; wire i___29_n_0; wire i___30_n_0; wire i___31_n_0; wire i___32_n_0; wire i___33_n_0; wire i___34_n_0; wire i___34_rep_n_0; wire i___35_n_0; wire i___35_rep_n_0; wire i___36_n_0; wire i___36_rep__0_n_0; wire i___36_rep_n_0; wire i___37_n_0; wire i___38_n_0; wire i___38_rep_n_0; wire i___39_n_0; wire i___39_rep_n_0; wire i___40_n_0; wire i___41_n_0; wire i___42_n_0; wire i___43_n_0; wire i___44_n_0; wire i___45_n_0; wire i___46_n_0; wire i___47_n_0; wire i___47_rep_n_0; wire i___48_n_0; wire i___48_rep__0_n_0; wire i___48_rep_n_0; wire i___4_n_0; wire i___5_n_0; wire i___6_n_0; wire i___7_n_0; wire i___8_n_0; wire i___9_n_0; wire [5:0]\mmcm_init_lead_reg[5] ; wire [5:0]mod_sub1_return; wire [1:0]ninety_offsets; wire ocd_edge_detect_rdy_r_reg; wire ocd_ktap_left_r_reg; wire ocd_ktap_left_r_reg_0; wire ocd_ktap_right_r_reg; wire [5:1]offset0_return0; wire [5:1]offset_return0; wire [6:1]p_0_in1_in; wire pd_out; wire poc_backup_r_reg; wire poc_sample_pd; wire \prev_r_reg[0] ; wire \prev_r_reg[0]_0 ; wire psdone; wire [0:0]\qcntr_r_reg[0] ; wire [5:0]rise_lead_center_0; wire \rise_lead_center_offset_r[5]_i_2_n_0 ; wire [5:0]rise_lead_left_0; wire [5:0]rise_trail_center_0; wire \rise_trail_center_offset_r[5]_i_2_n_0 ; wire [5:0]rise_trail_left_0; wire \rise_trail_r_reg[3]_i_2_n_0 ; wire \rise_trail_r_reg[3]_i_2_n_1 ; wire \rise_trail_r_reg[3]_i_2_n_2 ; wire \rise_trail_r_reg[3]_i_2_n_3 ; wire \rise_trail_r_reg[5]_i_3_n_3 ; wire rstdiv0_sync_r1_reg_rep; wire rstdiv0_sync_r1_reg_rep__0; wire rstdiv0_sync_r1_reg_rep__20; wire \run_ends_r_reg[1] ; wire run_polarity_held_r; wire [16:1]samp_cntr_ns0; wire \samp_cntr_r_reg[12]_i_2_n_0 ; wire \samp_cntr_r_reg[12]_i_2_n_1 ; wire \samp_cntr_r_reg[12]_i_2_n_2 ; wire \samp_cntr_r_reg[12]_i_2_n_3 ; wire \samp_cntr_r_reg[16]_i_2_n_1 ; wire \samp_cntr_r_reg[16]_i_2_n_2 ; wire \samp_cntr_r_reg[16]_i_2_n_3 ; wire \samp_cntr_r_reg[4]_i_2_n_0 ; wire \samp_cntr_r_reg[4]_i_2_n_1 ; wire \samp_cntr_r_reg[4]_i_2_n_2 ; wire \samp_cntr_r_reg[4]_i_2_n_3 ; wire \samp_cntr_r_reg[8]_i_2_n_0 ; wire \samp_cntr_r_reg[8]_i_2_n_1 ; wire \samp_cntr_r_reg[8]_i_2_n_2 ; wire \samp_cntr_r_reg[8]_i_2_n_3 ; wire [7:0]samp_wait_r; wire [17:0]samps_hi_ns0; wire \samps_hi_r[3]_i_6_n_0 ; wire \samps_hi_r_reg[11]_i_2_n_0 ; wire \samps_hi_r_reg[11]_i_2_n_1 ; wire \samps_hi_r_reg[11]_i_2_n_2 ; wire \samps_hi_r_reg[11]_i_2_n_3 ; wire \samps_hi_r_reg[15]_i_2_n_0 ; wire \samps_hi_r_reg[15]_i_2_n_1 ; wire \samps_hi_r_reg[15]_i_2_n_2 ; wire \samps_hi_r_reg[15]_i_2_n_3 ; wire \samps_hi_r_reg[17]_i_2_n_3 ; wire \samps_hi_r_reg[3]_i_2_n_0 ; wire \samps_hi_r_reg[3]_i_2_n_1 ; wire \samps_hi_r_reg[3]_i_2_n_2 ; wire \samps_hi_r_reg[3]_i_2_n_3 ; wire \samps_hi_r_reg[7]_i_2_n_0 ; wire \samps_hi_r_reg[7]_i_2_n_1 ; wire \samps_hi_r_reg[7]_i_2_n_2 ; wire \samps_hi_r_reg[7]_i_2_n_3 ; wire [17:3]samps_lo; wire samps_zero_r0_carry__0_i_10_n_0; wire samps_zero_r0_carry__0_i_10_n_1; wire samps_zero_r0_carry__0_i_10_n_2; wire samps_zero_r0_carry__0_i_10_n_3; wire samps_zero_r0_carry__0_i_4_n_0; wire samps_zero_r0_carry__0_i_4_n_1; wire samps_zero_r0_carry__0_i_4_n_2; wire samps_zero_r0_carry__0_i_4_n_3; wire samps_zero_r0_carry__0_i_9_n_1; wire samps_zero_r0_carry__0_i_9_n_2; wire samps_zero_r0_carry__0_i_9_n_3; wire samps_zero_r0_carry_i_2_n_0; wire samps_zero_r0_carry_i_2_n_1; wire samps_zero_r0_carry_i_2_n_2; wire samps_zero_r0_carry_i_2_n_3; wire \sm_r_reg[1] ; wire [5:0]trailing_edge; wire [5:0]trailing_edge0; wire [5:0]trailing_edge00_in; wire u_edge_left_n_0; wire u_edge_left_n_1; wire u_edge_left_n_15; wire u_edge_left_n_19; wire u_edge_left_n_2; wire u_edge_left_n_20; wire u_edge_left_n_21; wire u_edge_left_n_22; wire u_edge_left_n_23; wire u_edge_left_n_24; wire u_edge_left_n_25; wire u_edge_left_n_26; wire u_edge_left_n_27; wire u_edge_left_n_28; wire u_edge_left_n_29; wire u_edge_left_n_30; wire u_edge_left_n_31; wire u_edge_left_n_32; wire u_edge_left_n_33; wire u_edge_left_n_34; wire u_edge_right_n_21; wire u_edge_right_n_22; wire u_edge_right_n_23; wire u_edge_right_n_24; wire u_edge_right_n_25; wire u_edge_right_n_26; wire u_edge_right_n_27; wire u_edge_right_n_28; wire u_edge_right_n_29; wire u_edge_right_n_30; wire u_edge_right_n_31; wire u_edge_right_n_8; wire u_poc_meta_n_14; wire u_poc_meta_n_15; wire u_poc_meta_n_16; wire u_poc_meta_n_17; wire u_poc_meta_n_18; wire u_poc_meta_n_19; wire u_poc_meta_n_24; wire u_poc_meta_n_25; wire u_poc_meta_n_26; wire u_poc_meta_n_27; wire u_poc_meta_n_28; wire u_poc_meta_n_29; wire u_poc_meta_n_30; wire u_poc_meta_n_31; wire u_poc_meta_n_32; wire u_poc_meta_n_33; wire u_poc_meta_n_34; wire u_poc_meta_n_56; wire u_poc_meta_n_57; wire u_poc_meta_n_58; wire u_poc_meta_n_59; wire u_poc_meta_n_60; wire u_poc_meta_n_61; wire u_poc_meta_n_62; wire u_poc_meta_n_63; wire u_poc_tap_base_n_0; wire u_poc_tap_base_n_1; wire u_poc_tap_base_n_10; wire u_poc_tap_base_n_11; wire u_poc_tap_base_n_12; wire u_poc_tap_base_n_13; wire u_poc_tap_base_n_14; wire u_poc_tap_base_n_15; wire u_poc_tap_base_n_16; wire u_poc_tap_base_n_17; wire u_poc_tap_base_n_18; wire u_poc_tap_base_n_19; wire u_poc_tap_base_n_2; wire u_poc_tap_base_n_20; wire u_poc_tap_base_n_21; wire u_poc_tap_base_n_22; wire u_poc_tap_base_n_23; wire u_poc_tap_base_n_24; wire u_poc_tap_base_n_25; wire u_poc_tap_base_n_26; wire u_poc_tap_base_n_27; wire u_poc_tap_base_n_28; wire u_poc_tap_base_n_29; wire u_poc_tap_base_n_3; wire u_poc_tap_base_n_30; wire u_poc_tap_base_n_31; wire u_poc_tap_base_n_32; wire u_poc_tap_base_n_33; wire u_poc_tap_base_n_34; wire u_poc_tap_base_n_35; wire u_poc_tap_base_n_36; wire u_poc_tap_base_n_37; wire u_poc_tap_base_n_38; wire u_poc_tap_base_n_39; wire u_poc_tap_base_n_4; wire u_poc_tap_base_n_40; wire u_poc_tap_base_n_41; wire u_poc_tap_base_n_42; wire u_poc_tap_base_n_43; wire u_poc_tap_base_n_44; wire u_poc_tap_base_n_45; wire u_poc_tap_base_n_46; wire u_poc_tap_base_n_47; wire u_poc_tap_base_n_48; wire u_poc_tap_base_n_49; wire u_poc_tap_base_n_5; wire u_poc_tap_base_n_50; wire u_poc_tap_base_n_51; wire u_poc_tap_base_n_52; wire u_poc_tap_base_n_53; wire u_poc_tap_base_n_54; wire u_poc_tap_base_n_55; wire u_poc_tap_base_n_57; wire u_poc_tap_base_n_58; wire u_poc_tap_base_n_59; wire u_poc_tap_base_n_6; wire u_poc_tap_base_n_60; wire u_poc_tap_base_n_61; wire u_poc_tap_base_n_62; wire u_poc_tap_base_n_63; wire u_poc_tap_base_n_64; wire u_poc_tap_base_n_65; wire u_poc_tap_base_n_66; wire u_poc_tap_base_n_67; wire u_poc_tap_base_n_68; wire u_poc_tap_base_n_69; wire u_poc_tap_base_n_7; wire u_poc_tap_base_n_70; wire u_poc_tap_base_n_71; wire u_poc_tap_base_n_72; wire u_poc_tap_base_n_73; wire u_poc_tap_base_n_74; wire u_poc_tap_base_n_75; wire u_poc_tap_base_n_76; wire u_poc_tap_base_n_8; wire u_poc_tap_base_n_83; wire u_poc_tap_base_n_84; wire u_poc_tap_base_n_85; wire u_poc_tap_base_n_86; wire u_poc_tap_base_n_9; wire u_poc_tap_base_n_95; wire use_noise_window; wire [6:0]window_center; wire [3:1]\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED ; wire [3:2]\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED ; wire [3:3]\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED ; wire [3:1]\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED ; wire [3:2]\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED ; wire [3:3]NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED; wire [0:0]NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED; LUT6 #( .INIT(64'h1555FFFFEAAA0000)) center0_return1__0_carry__0_i_4 (.I0(center0_return3[7]), .I1(center0_return3[4]), .I2(center0_return3[5]), .I3(center0_return3[6]), .I4(u_poc_meta_n_60), .I5(center0_return1__0_carry__0_i_6_n_0), .O(center0_return1__0_carry__0_i_4_n_0)); LUT6 #( .INIT(64'hA999999956666666)) center0_return1__0_carry__0_i_5 (.I0(u_poc_meta_n_60), .I1(center0_return3[7]), .I2(center0_return3[4]), .I3(center0_return3[5]), .I4(center0_return3[6]), .I5(u_edge_left_n_1), .O(center0_return1__0_carry__0_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry__0_i_6 (.I0(rise_trail_left_0[4]), .I1(use_noise_window), .I2(rise_lead_left_0[4]), .I3(u_poc_meta_n_59), .O(center0_return1__0_carry__0_i_6_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry_i_4 (.I0(rise_trail_left_0[2]), .I1(use_noise_window), .I2(rise_lead_left_0[2]), .I3(u_poc_meta_n_61), .O(center0_return1__0_carry_i_4_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry_i_5 (.I0(rise_trail_left_0[1]), .I1(use_noise_window), .I2(rise_lead_left_0[1]), .I3(u_poc_meta_n_62), .O(center0_return1__0_carry_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__0_carry_i_6 (.I0(rise_trail_left_0[0]), .I1(use_noise_window), .I2(rise_lead_left_0[0]), .I3(u_poc_meta_n_63), .O(center0_return1__0_carry_i_6_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry__0_i_4 (.I0(rise_trail_left_0[4]), .I1(use_noise_window), .I2(rise_lead_left_0[4]), .I3(u_poc_meta_n_59), .O(center0_return1__1_carry__0_i_4_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry__0_i_5 (.I0(rise_trail_left_0[3]), .I1(use_noise_window), .I2(rise_lead_left_0[3]), .I3(u_poc_meta_n_60), .O(center0_return1__1_carry__0_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry_i_4 (.I0(rise_trail_left_0[2]), .I1(use_noise_window), .I2(rise_lead_left_0[2]), .I3(u_poc_meta_n_61), .O(center0_return1__1_carry_i_4_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry_i_5 (.I0(rise_trail_left_0[1]), .I1(use_noise_window), .I2(rise_lead_left_0[1]), .I3(u_poc_meta_n_62), .O(center0_return1__1_carry_i_5_n_0)); LUT4 #( .INIT(16'h1DE2)) center0_return1__1_carry_i_6 (.I0(rise_trail_left_0[0]), .I1(use_noise_window), .I2(rise_lead_left_0[0]), .I3(u_poc_meta_n_63), .O(center0_return1__1_carry_i_6_n_0)); LUT1 #( .INIT(2'h1)) \center_diff_r_reg[0]_i_2 (.I0(i___20_n_0), .O(\center_diff_r_reg[0]_i_2_n_0 )); LUT6 #( .INIT(64'h007FFFFFFF800000)) center_return1__0_carry__0_i_2 (.I0(center_return3[5]), .I1(center_return3[4]), .I2(center_return3[6]), .I3(center_return3[7]), .I4(diff[4]), .I5(center_return1__0_carry__0_i_4_n_0), .O(center_return1__0_carry__0_i_2_n_0)); LUT6 #( .INIT(64'hAAAA955555556AAA)) center_return1__0_carry__0_i_3 (.I0(diff[4]), .I1(center_return3[5]), .I2(center_return3[4]), .I3(center_return3[6]), .I4(center_return3[7]), .I5(p_0_in1_in[4]), .O(center_return1__0_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry__0_i_4 (.I0(p_0_in1_in[5]), .I1(diff[5]), .O(center_return1__0_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry_i_1 (.I0(p_0_in1_in[3]), .I1(diff[3]), .O(center_return1__0_carry_i_1_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry_i_2 (.I0(p_0_in1_in[2]), .I1(diff[2]), .O(center_return1__0_carry_i_2_n_0)); LUT2 #( .INIT(4'h6)) center_return1__0_carry_i_3 (.I0(p_0_in1_in[1]), .I1(diff[1]), .O(center_return1__0_carry_i_3_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry__0_i_2 (.I0(p_0_in1_in[5]), .I1(diff[5]), .O(center_return1__1_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry__0_i_3 (.I0(p_0_in1_in[4]), .I1(diff[4]), .O(center_return1__1_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry_i_1 (.I0(p_0_in1_in[3]), .I1(diff[3]), .O(center_return1__1_carry_i_1_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry_i_2 (.I0(p_0_in1_in[2]), .I1(diff[2]), .O(center_return1__1_carry_i_2_n_0)); LUT2 #( .INIT(4'h6)) center_return1__1_carry_i_3 (.I0(p_0_in1_in[1]), .I1(diff[1]), .O(center_return1__1_carry_i_3_n_0)); LUT2 #( .INIT(4'h6)) diff_ns0_carry__0_i_1 (.I0(window_center[5]), .I1(edge_center[5]), .O(diff_ns0_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h6)) diff_ns0_carry__0_i_2 (.I0(edge_center[4]), .I1(window_center[4]), .O(diff_ns0_carry__0_i_2_n_0)); LUT4 #( .INIT(16'h2F02)) diff_ns1_carry_i_1 (.I0(edge_center[4]), .I1(window_center[4]), .I2(window_center[5]), .I3(edge_center[5]), .O(diff_ns1_carry_i_1_n_0)); LUT4 #( .INIT(16'h2F02)) diff_ns1_carry_i_2 (.I0(edge_center[2]), .I1(window_center[2]), .I2(window_center[3]), .I3(edge_center[3]), .O(diff_ns1_carry_i_2_n_0)); LUT4 #( .INIT(16'h2F02)) diff_ns1_carry_i_3 (.I0(edge_center[0]), .I1(window_center[0]), .I2(window_center[1]), .I3(edge_center[1]), .O(diff_ns1_carry_i_3_n_0)); LUT2 #( .INIT(4'h9)) diff_ns1_carry_i_4 (.I0(window_center[6]), .I1(edge_center[6]), .O(diff_ns1_carry_i_4_n_0)); LUT4 #( .INIT(16'h9009)) diff_ns1_carry_i_5 (.I0(edge_center[4]), .I1(window_center[4]), .I2(edge_center[5]), .I3(window_center[5]), .O(diff_ns1_carry_i_5_n_0)); LUT4 #( .INIT(16'h9009)) diff_ns1_carry_i_6 (.I0(edge_center[2]), .I1(window_center[2]), .I2(edge_center[3]), .I3(window_center[3]), .O(diff_ns1_carry_i_6_n_0)); LUT4 #( .INIT(16'h9009)) diff_ns1_carry_i_7 (.I0(edge_center[0]), .I1(window_center[0]), .I2(edge_center[1]), .I3(window_center[1]), .O(diff_ns1_carry_i_7_n_0)); LUT1 #( .INIT(2'h1)) \diff_r_reg[0]_i_2 (.I0(i___48_n_0), .O(diff_ns00_in)); LUT1 #( .INIT(2'h1)) \edge_diff_r_reg[0]_i_2 (.I0(i___36_n_0), .O(\edge_diff_r_reg[0]_i_2_n_0 )); LUT5 #( .INIT(32'hFFF8888F)) i___10 (.I0(u_poc_tap_base_n_55), .I1(u_poc_tap_base_n_54), .I2(samp_wait_r[0]), .I3(samp_wait_r[1]), .I4(samp_wait_r[2]), .O(i___10_n_0)); LUT6 #( .INIT(64'hFFFFFFF88888888F)) i___11 (.I0(u_poc_tap_base_n_55), .I1(u_poc_tap_base_n_54), .I2(samp_wait_r[2]), .I3(samp_wait_r[1]), .I4(samp_wait_r[0]), .I5(samp_wait_r[3]), .O(i___11_n_0)); LUT6 #( .INIT(64'h5555555500000040)) i___12 (.I0(u_poc_tap_base_n_54), .I1(poc_sample_pd), .I2(u_poc_tap_base_n_86), .I3(samp_wait_r[6]), .I4(samp_wait_r[7]), .I5(u_poc_tap_base_n_55), .O(i___12_n_0)); LUT5 #( .INIT(32'h00000001)) i___13 (.I0(samp_wait_r[4]), .I1(samp_wait_r[2]), .I2(samp_wait_r[1]), .I3(samp_wait_r[0]), .I4(samp_wait_r[3]), .O(i___13_n_0)); LUT5 #( .INIT(32'hA8888888)) i___14 (.I0(diff[4]), .I1(center_return3[7]), .I2(center_return3[6]), .I3(center_return3[4]), .I4(center_return3[5]), .O(i___14_n_0)); LUT6 #( .INIT(64'h478B74B8B8748B47)) i___15 (.I0(rise_lead_left_0[4]), .I1(use_noise_window), .I2(rise_trail_left_0[4]), .I3(Q[4]), .I4(\mmcm_init_lead_reg[5] [4]), .I5(u_edge_left_n_1), .O(i___15_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___16 (.I0(\mmcm_init_lead_reg[5] [4]), .I1(Q[4]), .I2(rise_trail_left_0[4]), .I3(use_noise_window), .I4(rise_lead_left_0[4]), .O(i___16_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___17 (.I0(\mmcm_init_lead_reg[5] [3]), .I1(Q[3]), .I2(rise_trail_left_0[3]), .I3(use_noise_window), .I4(rise_lead_left_0[3]), .O(i___17_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___18 (.I0(\mmcm_init_lead_reg[5] [2]), .I1(Q[2]), .I2(rise_trail_left_0[2]), .I3(use_noise_window), .I4(rise_lead_left_0[2]), .O(i___18_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___18_rep (.I0(\mmcm_init_lead_reg[5] [2]), .I1(Q[2]), .I2(rise_trail_left_0[2]), .I3(use_noise_window), .I4(rise_lead_left_0[2]), .O(i___18_rep_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___19 (.I0(\mmcm_init_lead_reg[5] [1]), .I1(Q[1]), .I2(rise_trail_left_0[1]), .I3(use_noise_window), .I4(rise_lead_left_0[1]), .O(i___19_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___19_rep (.I0(\mmcm_init_lead_reg[5] [1]), .I1(Q[1]), .I2(rise_trail_left_0[1]), .I3(use_noise_window), .I4(rise_lead_left_0[1]), .O(i___19_rep_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___20 (.I0(\mmcm_init_lead_reg[5] [0]), .I1(Q[0]), .I2(rise_trail_left_0[0]), .I3(use_noise_window), .I4(rise_lead_left_0[0]), .O(i___20_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___20_rep (.I0(\mmcm_init_lead_reg[5] [0]), .I1(Q[0]), .I2(rise_trail_left_0[0]), .I3(use_noise_window), .I4(rise_lead_left_0[0]), .O(i___20_rep_n_0)); LUT5 #( .INIT(32'hCCA533A5)) i___20_rep__0 (.I0(\mmcm_init_lead_reg[5] [0]), .I1(Q[0]), .I2(rise_trail_left_0[0]), .I3(use_noise_window), .I4(rise_lead_left_0[0]), .O(i___20_rep__0_n_0)); LUT2 #( .INIT(4'h9)) i___21 (.I0(u_poc_tap_base_n_60), .I1(u_poc_tap_base_n_49), .O(i___21_n_0)); LUT2 #( .INIT(4'h9)) i___21_rep (.I0(u_poc_tap_base_n_60), .I1(u_poc_tap_base_n_49), .O(i___21_rep_n_0)); LUT2 #( .INIT(4'h9)) i___22 (.I0(u_poc_tap_base_n_59), .I1(u_poc_tap_base_n_48), .O(i___22_n_0)); LUT3 #( .INIT(8'h69)) i___23 (.I0(u_poc_tap_base_n_47), .I1(u_poc_tap_base_n_58), .I2(u_poc_tap_base_n_48), .O(i___23_n_0)); LUT2 #( .INIT(4'h9)) i___24 (.I0(u_poc_tap_base_n_58), .I1(u_poc_tap_base_n_47), .O(i___24_n_0)); LUT2 #( .INIT(4'h9)) i___25 (.I0(u_poc_tap_base_n_61), .I1(u_poc_tap_base_n_50), .O(i___25_n_0)); LUT2 #( .INIT(4'h9)) i___25_rep (.I0(u_poc_tap_base_n_61), .I1(u_poc_tap_base_n_50), .O(i___25_rep_n_0)); (* SOFT_HLUTNM = "soft_lutpair478" *) LUT2 #( .INIT(4'h9)) i___26 (.I0(u_poc_tap_base_n_62), .I1(u_poc_tap_base_n_51), .O(i___26_n_0)); LUT2 #( .INIT(4'h9)) i___26_rep (.I0(u_poc_tap_base_n_62), .I1(u_poc_tap_base_n_51), .O(i___26_rep_n_0)); LUT2 #( .INIT(4'h9)) i___26_rep__0 (.I0(u_poc_tap_base_n_62), .I1(u_poc_tap_base_n_51), .O(i___26_rep__0_n_0)); LUT2 #( .INIT(4'h6)) i___27 (.I0(u_poc_tap_base_n_7), .I1(u_poc_tap_base_n_6), .O(i___27_n_0)); LUT2 #( .INIT(4'h6)) i___28 (.I0(u_poc_tap_base_n_5), .I1(u_poc_tap_base_n_4), .O(i___28_n_0)); LUT4 #( .INIT(16'hD22D)) i___29 (.I0(p_0_in1_in[5]), .I1(u_poc_meta_n_15), .I2(p_0_in1_in[6]), .I3(u_poc_meta_n_14), .O(i___29_n_0)); LUT2 #( .INIT(4'h9)) i___30 (.I0(u_poc_meta_n_14), .I1(p_0_in1_in[6]), .O(i___30_n_0)); LUT3 #( .INIT(8'h69)) i___31 (.I0(p_0_in1_in[5]), .I1(u_poc_meta_n_15), .I2(p_0_in1_in[4]), .O(i___31_n_0)); LUT2 #( .INIT(4'h9)) i___32 (.I0(u_poc_meta_n_15), .I1(p_0_in1_in[5]), .O(i___32_n_0)); LUT2 #( .INIT(4'h9)) i___33 (.I0(u_poc_meta_n_16), .I1(p_0_in1_in[4]), .O(i___33_n_0)); LUT2 #( .INIT(4'h9)) i___34 (.I0(u_poc_meta_n_17), .I1(p_0_in1_in[3]), .O(i___34_n_0)); LUT2 #( .INIT(4'h9)) i___34_rep (.I0(u_poc_meta_n_17), .I1(p_0_in1_in[3]), .O(i___34_rep_n_0)); LUT2 #( .INIT(4'h9)) i___35 (.I0(u_poc_meta_n_18), .I1(p_0_in1_in[2]), .O(i___35_n_0)); LUT2 #( .INIT(4'h9)) i___35_rep (.I0(u_poc_meta_n_18), .I1(p_0_in1_in[2]), .O(i___35_rep_n_0)); LUT2 #( .INIT(4'h9)) i___36 (.I0(u_poc_meta_n_19), .I1(p_0_in1_in[1]), .O(i___36_n_0)); LUT2 #( .INIT(4'h9)) i___36_rep (.I0(u_poc_meta_n_19), .I1(p_0_in1_in[1]), .O(i___36_rep_n_0)); LUT2 #( .INIT(4'h9)) i___36_rep__0 (.I0(u_poc_meta_n_19), .I1(p_0_in1_in[1]), .O(i___36_rep__0_n_0)); LUT4 #( .INIT(16'hD22D)) i___37 (.I0(window_center[5]), .I1(edge_center[5]), .I2(window_center[6]), .I3(edge_center[6]), .O(i___37_n_0)); LUT2 #( .INIT(4'h9)) i___38 (.I0(edge_center[2]), .I1(window_center[2]), .O(i___38_n_0)); LUT2 #( .INIT(4'h9)) i___38_rep (.I0(edge_center[2]), .I1(window_center[2]), .O(i___38_rep_n_0)); LUT2 #( .INIT(4'h9)) i___39 (.I0(edge_center[1]), .I1(window_center[1]), .O(i___39_n_0)); LUT2 #( .INIT(4'h9)) i___39_rep (.I0(edge_center[1]), .I1(window_center[1]), .O(i___39_rep_n_0)); LUT6 #( .INIT(64'hFFFFCFFF00008800)) i___4 (.I0(u_poc_tap_base_n_2), .I1(u_poc_tap_base_n_0), .I2(u_poc_tap_base_n_3), .I3(u_poc_tap_base_n_46), .I4(rstdiv0_sync_r1_reg_rep__20), .I5(run_polarity_held_r), .O(i___4_n_0)); LUT2 #( .INIT(4'h2)) i___40 (.I0(window_center[6]), .I1(edge_center[6]), .O(i___40_n_0)); LUT2 #( .INIT(4'h9)) i___41 (.I0(edge_center[6]), .I1(window_center[6]), .O(i___41_n_0)); LUT2 #( .INIT(4'h2)) i___42 (.I0(edge_center[6]), .I1(window_center[6]), .O(i___42_n_0)); LUT3 #( .INIT(8'h69)) i___43 (.I0(window_center[5]), .I1(edge_center[5]), .I2(window_center[4]), .O(i___43_n_0)); LUT2 #( .INIT(4'h9)) i___44 (.I0(edge_center[5]), .I1(window_center[5]), .O(i___44_n_0)); LUT2 #( .INIT(4'hB)) i___45 (.I0(edge_center[5]), .I1(window_center[5]), .O(i___45_n_0)); LUT2 #( .INIT(4'h9)) i___46 (.I0(edge_center[4]), .I1(window_center[4]), .O(i___46_n_0)); LUT2 #( .INIT(4'h9)) i___47 (.I0(edge_center[3]), .I1(window_center[3]), .O(i___47_n_0)); LUT2 #( .INIT(4'h9)) i___47_rep (.I0(edge_center[3]), .I1(window_center[3]), .O(i___47_rep_n_0)); LUT2 #( .INIT(4'h9)) i___48 (.I0(edge_center[0]), .I1(window_center[0]), .O(i___48_n_0)); LUT2 #( .INIT(4'h9)) i___48_rep (.I0(edge_center[0]), .I1(window_center[0]), .O(i___48_rep_n_0)); LUT2 #( .INIT(4'h9)) i___48_rep__0 (.I0(edge_center[0]), .I1(window_center[0]), .O(i___48_rep__0_n_0)); LUT5 #( .INIT(32'h00400000)) i___5 (.I0(u_poc_tap_base_n_0), .I1(u_poc_tap_base_n_3), .I2(u_poc_tap_base_n_46), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_right_r_reg), .O(i___5_n_0)); LUT5 #( .INIT(32'h00400000)) i___6 (.I0(u_poc_tap_base_n_0), .I1(u_poc_tap_base_n_3), .I2(u_poc_tap_base_n_46), .I3(rstdiv0_sync_r1_reg_rep__20), .I4(ocd_ktap_left_r_reg), .O(i___6_n_0)); LUT4 #( .INIT(16'h0004)) i___7 (.I0(u_poc_tap_base_n_0), .I1(u_poc_tap_base_n_52), .I2(ocd_ktap_left_r_reg), .I3(ocd_ktap_right_r_reg), .O(i___7_n_0)); LUT3 #( .INIT(8'h01)) i___8 (.I0(u_poc_meta_n_56), .I1(u_poc_meta_n_58), .I2(u_poc_meta_n_57), .O(i___8_n_0)); (* SOFT_HLUTNM = "soft_lutpair478" *) LUT4 #( .INIT(16'h7FFF)) i___9 (.I0(u_poc_tap_base_n_49), .I1(u_poc_tap_base_n_50), .I2(u_poc_tap_base_n_51), .I3(u_poc_tap_base_n_48), .O(i___9_n_0)); (* SOFT_HLUTNM = "soft_lutpair481" *) LUT2 #( .INIT(4'h6)) \rise_lead_center_offset_r[1]_i_1 (.I0(rise_lead_center_0[1]), .I1(ninety_offsets[0]), .O(offset_return0[1])); (* SOFT_HLUTNM = "soft_lutpair479" *) LUT4 #( .INIT(16'h4BB4)) \rise_lead_center_offset_r[2]_i_1 (.I0(rise_lead_center_0[1]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_lead_center_0[2]), .O(offset_return0[2])); LUT6 #( .INIT(64'h5A4969254969925A)) \rise_lead_center_offset_r[3]_i_1 (.I0(rise_lead_center_0[3]), .I1(rise_lead_center_0[5]), .I2(\rise_lead_center_offset_r[5]_i_2_n_0 ), .I3(rise_lead_center_0[4]), .I4(ninety_offsets[1]), .I5(ninety_offsets[0]), .O(offset_return0[3])); LUT6 #( .INIT(64'h998564666466621A)) \rise_lead_center_offset_r[4]_i_1 (.I0(rise_lead_center_0[4]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_lead_center_0[5]), .I4(rise_lead_center_0[3]), .I5(\rise_lead_center_offset_r[5]_i_2_n_0 ), .O(offset_return0[4])); LUT6 #( .INIT(64'hF00E871887700EF0)) \rise_lead_center_offset_r[5]_i_1 (.I0(rise_lead_center_0[3]), .I1(\rise_lead_center_offset_r[5]_i_2_n_0 ), .I2(rise_lead_center_0[5]), .I3(ninety_offsets[1]), .I4(ninety_offsets[0]), .I5(rise_lead_center_0[4]), .O(offset_return0[5])); (* SOFT_HLUTNM = "soft_lutpair479" *) LUT4 #( .INIT(16'hE460)) \rise_lead_center_offset_r[5]_i_2 (.I0(ninety_offsets[1]), .I1(ninety_offsets[0]), .I2(rise_lead_center_0[2]), .I3(rise_lead_center_0[1]), .O(\rise_lead_center_offset_r[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair481" *) LUT2 #( .INIT(4'h6)) \rise_trail_center_offset_r[1]_i_1 (.I0(rise_trail_center_0[1]), .I1(ninety_offsets[0]), .O(offset0_return0[1])); (* SOFT_HLUTNM = "soft_lutpair480" *) LUT4 #( .INIT(16'h4BB4)) \rise_trail_center_offset_r[2]_i_1 (.I0(rise_trail_center_0[1]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_trail_center_0[2]), .O(offset0_return0[2])); LUT6 #( .INIT(64'h5A4969254969925A)) \rise_trail_center_offset_r[3]_i_1 (.I0(rise_trail_center_0[3]), .I1(rise_trail_center_0[5]), .I2(\rise_trail_center_offset_r[5]_i_2_n_0 ), .I3(rise_trail_center_0[4]), .I4(ninety_offsets[1]), .I5(ninety_offsets[0]), .O(offset0_return0[3])); LUT6 #( .INIT(64'h998564666466621A)) \rise_trail_center_offset_r[4]_i_1 (.I0(rise_trail_center_0[4]), .I1(ninety_offsets[0]), .I2(ninety_offsets[1]), .I3(rise_trail_center_0[5]), .I4(rise_trail_center_0[3]), .I5(\rise_trail_center_offset_r[5]_i_2_n_0 ), .O(offset0_return0[4])); LUT6 #( .INIT(64'hF00E871887700EF0)) \rise_trail_center_offset_r[5]_i_1 (.I0(rise_trail_center_0[3]), .I1(\rise_trail_center_offset_r[5]_i_2_n_0 ), .I2(rise_trail_center_0[5]), .I3(ninety_offsets[1]), .I4(ninety_offsets[0]), .I5(rise_trail_center_0[4]), .O(offset0_return0[5])); (* SOFT_HLUTNM = "soft_lutpair480" *) LUT4 #( .INIT(16'hE460)) \rise_trail_center_offset_r[5]_i_2 (.I0(ninety_offsets[1]), .I1(ninety_offsets[0]), .I2(rise_trail_center_0[2]), .I3(rise_trail_center_0[1]), .O(\rise_trail_center_offset_r[5]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \rise_trail_r_reg[0]_i_2 (.I0(i___26_n_0), .O(trailing_edge00_in[0])); CARRY4 \rise_trail_r_reg[3]_i_2 (.CI(1'b0), .CO({\rise_trail_r_reg[3]_i_2_n_0 ,\rise_trail_r_reg[3]_i_2_n_1 ,\rise_trail_r_reg[3]_i_2_n_2 ,\rise_trail_r_reg[3]_i_2_n_3 }), .CYINIT(1'b1), .DI({u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .O(trailing_edge0[3:0]), .S({i___22_n_0,i___21_rep_n_0,i___25_rep_n_0,i___26_rep_n_0})); CARRY4 \rise_trail_r_reg[5]_i_3 (.CI(\rise_trail_r_reg[3]_i_2_n_0 ), .CO({\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED [3:1],\rise_trail_r_reg[5]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_58}), .O({\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED [3:2],trailing_edge0[5:4]}), .S({1'b0,1'b0,u_poc_tap_base_n_84,i___24_n_0})); CARRY4 \samp_cntr_r_reg[12]_i_2 (.CI(\samp_cntr_r_reg[8]_i_2_n_0 ), .CO({\samp_cntr_r_reg[12]_i_2_n_0 ,\samp_cntr_r_reg[12]_i_2_n_1 ,\samp_cntr_r_reg[12]_i_2_n_2 ,\samp_cntr_r_reg[12]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[12:9]), .S({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20})); CARRY4 \samp_cntr_r_reg[16]_i_2 (.CI(\samp_cntr_r_reg[12]_i_2_n_0 ), .CO({\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED [3],\samp_cntr_r_reg[16]_i_2_n_1 ,\samp_cntr_r_reg[16]_i_2_n_2 ,\samp_cntr_r_reg[16]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[16:13]), .S({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24})); CARRY4 \samp_cntr_r_reg[4]_i_2 (.CI(1'b0), .CO({\samp_cntr_r_reg[4]_i_2_n_0 ,\samp_cntr_r_reg[4]_i_2_n_1 ,\samp_cntr_r_reg[4]_i_2_n_2 ,\samp_cntr_r_reg[4]_i_2_n_3 }), .CYINIT(u_poc_tap_base_n_76), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[4:1]), .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12})); CARRY4 \samp_cntr_r_reg[8]_i_2 (.CI(\samp_cntr_r_reg[4]_i_2_n_0 ), .CO({\samp_cntr_r_reg[8]_i_2_n_0 ,\samp_cntr_r_reg[8]_i_2_n_1 ,\samp_cntr_r_reg[8]_i_2_n_2 ,\samp_cntr_r_reg[8]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samp_cntr_ns0[8:5]), .S({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16})); LUT2 #( .INIT(4'h6)) \samps_hi_r[3]_i_6 (.I0(u_poc_tap_base_n_8), .I1(pd_out), .O(\samps_hi_r[3]_i_6_n_0 )); CARRY4 \samps_hi_r_reg[11]_i_2 (.CI(\samps_hi_r_reg[7]_i_2_n_0 ), .CO({\samps_hi_r_reg[11]_i_2_n_0 ,\samps_hi_r_reg[11]_i_2_n_1 ,\samps_hi_r_reg[11]_i_2_n_2 ,\samps_hi_r_reg[11]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_hi_ns0[11:8]), .S({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35})); CARRY4 \samps_hi_r_reg[15]_i_2 (.CI(\samps_hi_r_reg[11]_i_2_n_0 ), .CO({\samps_hi_r_reg[15]_i_2_n_0 ,\samps_hi_r_reg[15]_i_2_n_1 ,\samps_hi_r_reg[15]_i_2_n_2 ,\samps_hi_r_reg[15]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_hi_ns0[15:12]), .S({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39})); CARRY4 \samps_hi_r_reg[17]_i_2 (.CI(\samps_hi_r_reg[15]_i_2_n_0 ), .CO({\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED [3:1],\samps_hi_r_reg[17]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED [3:2],samps_hi_ns0[17:16]}), .S({1'b0,1'b0,u_poc_tap_base_n_40,u_poc_tap_base_n_41})); CARRY4 \samps_hi_r_reg[3]_i_2 (.CI(1'b0), .CO({\samps_hi_r_reg[3]_i_2_n_0 ,\samps_hi_r_reg[3]_i_2_n_1 ,\samps_hi_r_reg[3]_i_2_n_2 ,\samps_hi_r_reg[3]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_8}), .O(samps_hi_ns0[3:0]), .S({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27,\samps_hi_r[3]_i_6_n_0 })); CARRY4 \samps_hi_r_reg[7]_i_2 (.CI(\samps_hi_r_reg[3]_i_2_n_0 ), .CO({\samps_hi_r_reg[7]_i_2_n_0 ,\samps_hi_r_reg[7]_i_2_n_1 ,\samps_hi_r_reg[7]_i_2_n_2 ,\samps_hi_r_reg[7]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_hi_ns0[7:4]), .S({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31})); CARRY4 samps_zero_r0_carry__0_i_10 (.CI(samps_zero_r0_carry__0_i_4_n_0), .CO({samps_zero_r0_carry__0_i_10_n_0,samps_zero_r0_carry__0_i_10_n_1,samps_zero_r0_carry__0_i_10_n_2,samps_zero_r0_carry__0_i_10_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_75}), .O(samps_lo[13:10]), .S({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70,i___28_n_0})); CARRY4 samps_zero_r0_carry__0_i_4 (.CI(samps_zero_r0_carry_i_2_n_0), .CO({samps_zero_r0_carry__0_i_4_n_0,samps_zero_r0_carry__0_i_4_n_1,samps_zero_r0_carry__0_i_4_n_2,samps_zero_r0_carry__0_i_4_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_lo[9:6]), .S({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45})); CARRY4 samps_zero_r0_carry__0_i_9 (.CI(samps_zero_r0_carry__0_i_10_n_0), .CO({NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED[3],samps_zero_r0_carry__0_i_9_n_1,samps_zero_r0_carry__0_i_9_n_2,samps_zero_r0_carry__0_i_9_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(samps_lo[17:14]), .S({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67})); CARRY4 samps_zero_r0_carry_i_2 (.CI(1'b0), .CO({samps_zero_r0_carry_i_2_n_0,samps_zero_r0_carry_i_2_n_1,samps_zero_r0_carry_i_2_n_2,samps_zero_r0_carry_i_2_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_74}), .O({samps_lo[5:3],NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED[0]}), .S({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73,i___27_n_0})); ddr3_if_mig_7series_v4_0_poc_edge_store u_edge_center (.CLK(CLK), .D(trailing_edge), .E(i___7_n_0), .Q(rise_lead_center_0), .\rise_trail_center_offset_r_reg[3] (rise_trail_center_0), .run_polarity_r_reg(u_poc_tap_base_n_53), .\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62})); ddr3_if_mig_7series_v4_0_poc_edge_store_9 u_edge_left (.CLK(CLK), .D({mod_sub1_return[5:4],mod_sub1_return[0]}), .DI({u_edge_left_n_0,u_edge_left_n_1}), .E(i___6_n_0), .O(u_poc_meta_n_27), .Q({u_poc_meta_n_59,u_poc_meta_n_60}), .S(u_edge_left_n_15), .center0_return3(center0_return3), .\center_diff_r_reg[0] (u_edge_left_n_19), .\center_diff_r_reg[0]_0 (u_edge_left_n_20), .\center_diff_r_reg[0]_1 (u_edge_left_n_21), .\center_diff_r_reg[1] (u_edge_left_n_23), .\center_diff_r_reg[3] (u_edge_left_n_33), .\center_diff_r_reg[3]_0 (u_edge_left_n_34), .\center_diff_r_reg[5] (u_edge_left_n_2), .\center_diff_r_reg[5]_0 (u_edge_left_n_22), .\rise_lead_r_reg[0]_0 (\center_diff_r_reg[0]_i_2_n_0 ), .\rise_lead_r_reg[4]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}), .\rise_lead_r_reg[5]_0 ({\mmcm_init_lead_reg[5] [5:3],\mmcm_init_lead_reg[5] [0]}), .\rise_trail_r_reg[1]_0 (u_edge_right_n_27), .\rise_trail_r_reg[2]_0 (u_edge_right_n_26), .\rise_trail_r_reg[3]_0 (u_edge_right_n_8), .\rise_trail_r_reg[4]_0 ({u_poc_meta_n_33,u_poc_meta_n_34}), .\rise_trail_r_reg[5]_0 ({Q[5:3],Q[0]}), .samps_zero_r_reg(u_poc_tap_base_n_95), .\tap_r_reg[4] (trailing_edge), .\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .use_noise_window(use_noise_window), .\window_center_r_reg[0] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}), .\window_center_r_reg[3] ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}), .\window_center_r_reg[6] (rise_lead_left_0), .\window_center_r_reg[6]_0 (rise_trail_left_0), .\window_center_r_reg[6]_1 (u_edge_left_n_24), .\window_center_r_reg[6]_2 ({u_edge_left_n_31,u_edge_left_n_32})); ddr3_if_mig_7series_v4_0_poc_edge_store_10 u_edge_right (.CLK(CLK), .D(mod_sub1_return[3:1]), .DI(u_poc_tap_base_n_63), .E(i___5_n_0), .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26}), .Q(u_poc_tap_base_n_48), .S({u_poc_tap_base_n_85,i___21_n_0,i___25_n_0,i___26_rep__0_n_0}), .\center_diff_r_reg[0] (u_edge_right_n_26), .\center_diff_r_reg[0]_0 (u_edge_right_n_27), .\center_diff_r_reg[1] (u_edge_right_n_8), .\center_diff_r_reg[3] ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}), .\center_diff_r_reg[3]_0 ({u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}), .\center_diff_r_reg[5] (u_edge_right_n_21), .\center_diff_r_reg[5]_0 (u_edge_right_n_31), .\mmcm_init_lead_reg[5] (\mmcm_init_lead_reg[5] ), .\mmcm_init_trail_reg[5] (Q), .\rise_lead_r_reg[1]_0 (u_edge_left_n_20), .\rise_lead_r_reg[3]_0 (u_edge_left_n_1), .\rise_lead_r_reg[4]_0 (u_edge_left_n_21), .\rise_lead_r_reg[4]_1 (u_edge_left_n_23), .\rise_lead_r_reg[5]_0 (rise_lead_left_0[5]), .\rise_trail_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}), .\rise_trail_r_reg[5]_0 (u_edge_left_n_19), .\rise_trail_r_reg[5]_1 (rise_trail_left_0[5]), .samps_zero_r_reg(fall_lead_r0), .\tap_r_reg[4] (trailing_edge), .\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .\tap_r_reg[5]_0 ({u_poc_tap_base_n_83,i___23_n_0}), .trailing_edge00_in(trailing_edge00_in[5:1]), .use_noise_window(use_noise_window)); ddr3_if_mig_7series_v4_0_poc_meta u_poc_meta (.CLK(CLK), .D(mod_sub1_return), .DI(i___14_n_0), .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26,u_poc_meta_n_27}), .Q(p_0_in1_in), .S({center_return1__1_carry_i_1_n_0,center_return1__1_carry_i_2_n_0,center_return1__1_carry_i_3_n_0}), .center0_return3(center0_return3), .\center_diff_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}), .\center_diff_r_reg[4]_0 ({u_edge_left_n_0,u_edge_left_n_1}), .\center_diff_r_reg[5]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}), .\center_diff_r_reg[5]_1 ({u_poc_meta_n_33,u_poc_meta_n_34}), .center_return3(center_return3), .detect_done_r_reg(detect_done_r_reg), .\diff_r_reg[2]_0 (i___8_n_0), .\diff_r_reg[7]_0 (edge_center), .\diff_r_reg[7]_1 (window_center), .\edge_center_r_reg[0]_0 (diff_ns00_in), .\edge_center_r_reg[3]_0 ({i___47_rep_n_0,i___38_rep_n_0,i___39_rep_n_0,i___48_rep_n_0}), .\edge_center_r_reg[3]_1 ({i___47_n_0,i___38_n_0,i___39_n_0,i___48_rep__0_n_0}), .\edge_center_r_reg[5]_0 ({i___45_n_0,diff_ns0_carry__0_i_1_n_0}), .\edge_center_r_reg[6]_0 (diff), .\edge_center_r_reg[6]_1 ({i___42_n_0,diff_ns1_carry_i_1_n_0,diff_ns1_carry_i_2_n_0,diff_ns1_carry_i_3_n_0}), .\edge_center_r_reg[6]_2 ({i___41_n_0,i___44_n_0,i___46_n_0}), .\edge_diff_r_reg[0]_0 ({u_poc_meta_n_14,u_poc_meta_n_15,u_poc_meta_n_16,u_poc_meta_n_17,u_poc_meta_n_18,u_poc_meta_n_19}), .\edge_diff_r_reg[4]_0 ({center_return1__0_carry__0_i_2_n_0,center_return1__0_carry__0_i_3_n_0}), .ocd_edge_detect_rdy_r_reg(ocd_edge_detect_rdy_r_reg), .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg), .ocd_ktap_left_r_reg_0(ocd_ktap_left_r_reg_0), .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg), .poc_backup_r_reg_0(poc_backup_r_reg), .\prev_r_reg[0]_0 (\prev_r_reg[0] ), .\prev_r_reg[0]_1 (\prev_r_reg[0]_0 ), .\prev_r_reg[2]_0 ({u_poc_meta_n_56,u_poc_meta_n_57,u_poc_meta_n_58}), .\rise_lead_center_offset_r_reg[2]_0 ({center_return1__0_carry_i_1_n_0,center_return1__0_carry_i_2_n_0,center_return1__0_carry_i_3_n_0}), .\rise_lead_center_offset_r_reg[4]_0 ({center_return1__1_carry__0_i_2_n_0,center_return1__1_carry__0_i_3_n_0}), .\rise_lead_center_offset_r_reg[4]_1 ({i___29_n_0,i___31_n_0}), .\rise_lead_r_reg[2] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}), .\rise_lead_r_reg[2]_0 ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}), .\rise_lead_r_reg[3] ({u_edge_left_n_34,u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}), .\rise_lead_r_reg[3]_0 ({i___17_n_0,i___18_n_0,i___19_n_0,i___20_rep__0_n_0}), .\rise_lead_r_reg[3]_1 ({offset_return0,rise_lead_center_0[0]}), .\rise_lead_r_reg[4] ({u_edge_left_n_31,u_edge_left_n_32}), .\rise_lead_r_reg[4]_0 ({u_edge_left_n_15,center0_return1__0_carry__0_i_4_n_0,center0_return1__0_carry__0_i_5_n_0}), .\rise_lead_r_reg[4]_1 (u_edge_left_n_2), .\rise_lead_r_reg[4]_2 ({u_edge_left_n_22,i___15_n_0}), .\rise_lead_r_reg[5] ({u_edge_left_n_24,center0_return1__1_carry__0_i_4_n_0,center0_return1__1_carry__0_i_5_n_0}), .\rise_trail_center_offset_r_reg[0]_0 (\edge_diff_r_reg[0]_i_2_n_0 ), .\rise_trail_center_offset_r_reg[2]_0 ({i___34_rep_n_0,i___35_rep_n_0,i___36_rep_n_0}), .\rise_trail_center_offset_r_reg[3]_0 ({i___33_n_0,i___34_n_0,i___35_n_0,i___36_rep__0_n_0}), .\rise_trail_center_offset_r_reg[5]_0 ({i___30_n_0,i___32_n_0}), .\rise_trail_r_reg[2] ({center0_return1__1_carry_i_4_n_0,center0_return1__1_carry_i_5_n_0,center0_return1__1_carry_i_6_n_0}), .\rise_trail_r_reg[2]_0 ({center0_return1__0_carry_i_4_n_0,center0_return1__0_carry_i_5_n_0,center0_return1__0_carry_i_6_n_0}), .\rise_trail_r_reg[3] ({u_edge_left_n_33,i___18_rep_n_0,i___19_rep_n_0,i___20_rep_n_0}), .\rise_trail_r_reg[3]_0 ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}), .\rise_trail_r_reg[3]_1 ({offset0_return0,rise_trail_center_0[0]}), .\rise_trail_r_reg[4] (u_edge_right_n_31), .\rise_trail_r_reg[5] ({u_edge_right_n_21,i___16_n_0}), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\run_ends_r_reg[1]_0 (\run_ends_r_reg[1] ), .run_polarity_held_r(run_polarity_held_r), .run_too_small_r_reg(u_poc_tap_base_n_1), .samps_zero_r_reg(i___4_n_0), .samps_zero_r_reg_0(u_poc_tap_base_n_52), .\sm_r_reg[1] (\sm_r_reg[1] ), .\window_center_r_reg[6]_0 ({u_poc_meta_n_59,u_poc_meta_n_60,u_poc_meta_n_61,u_poc_meta_n_62,u_poc_meta_n_63}), .\window_center_r_reg[6]_1 ({diff_ns1_carry_i_4_n_0,diff_ns1_carry_i_5_n_0,diff_ns1_carry_i_6_n_0,diff_ns1_carry_i_7_n_0}), .\window_center_r_reg[6]_2 ({i___40_n_0,i___37_n_0,i___43_n_0,diff_ns0_carry__0_i_2_n_0})); ddr3_if_mig_7series_v4_0_poc_tap_base u_poc_tap_base (.CLK(CLK), .D({i___11_n_0,i___10_n_0}), .DI(u_poc_tap_base_n_63), .E(i___12_n_0), .Q({u_poc_tap_base_n_4,u_poc_tap_base_n_5,u_poc_tap_base_n_6,u_poc_tap_base_n_7,u_poc_tap_base_n_8}), .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12}), .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg), .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg), .poc_sample_pd(poc_sample_pd), .psdone(psdone), .\qcntr_r_reg[0] (\qcntr_r_reg[0] ), .\rise_lead_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}), .\rise_trail_r_reg[0] (u_poc_tap_base_n_53), .\rise_trail_r_reg[3] (u_poc_tap_base_n_85), .\rise_trail_r_reg[5] (trailing_edge), .\rise_trail_r_reg[5]_0 (u_poc_tap_base_n_83), .\rise_trail_r_reg[5]_1 (u_poc_tap_base_n_84), .\rise_trail_r_reg[5]_2 (fall_lead_r0), .\rise_trail_r_reg[5]_3 (u_poc_tap_base_n_95), .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep), .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .\run_r_reg[0]_0 (u_poc_tap_base_n_0), .\run_r_reg[0]_1 (u_poc_tap_base_n_2), .\run_r_reg[0]_2 (u_poc_tap_base_n_3), .\run_r_reg[2]_0 (i___9_n_0), .\run_r_reg[4]_0 ({u_poc_tap_base_n_47,u_poc_tap_base_n_48,u_poc_tap_base_n_49,u_poc_tap_base_n_50,u_poc_tap_base_n_51}), .run_too_small_r3_reg(u_poc_tap_base_n_1), .run_too_small_r_reg_0(u_poc_tap_base_n_52), .samp_cntr_ns0(samp_cntr_ns0), .\samp_cntr_r_reg[0]_0 (u_poc_tap_base_n_76), .\samp_cntr_r_reg[12]_0 ({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20}), .\samp_cntr_r_reg[16]_0 ({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24}), .\samp_cntr_r_reg[8]_0 ({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16}), .\samp_wait_r_reg[4]_0 (i___13_n_0), .\samp_wait_r_reg[6]_0 (u_poc_tap_base_n_86), .\samp_wait_r_reg[7]_0 ({samp_wait_r[7:6],samp_wait_r[4:0]}), .samps_hi_ns0(samps_hi_ns0), .\samps_hi_r_reg[11]_0 ({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35}), .\samps_hi_r_reg[15]_0 ({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39}), .\samps_hi_r_reg[17]_0 ({u_poc_tap_base_n_40,u_poc_tap_base_n_41}), .\samps_hi_r_reg[3]_0 ({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27}), .\samps_hi_r_reg[7]_0 ({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31}), .samps_lo(samps_lo), .samps_zero_r_reg_0({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45}), .samps_zero_r_reg_1({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67}), .samps_zero_r_reg_2({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70}), .samps_zero_r_reg_3({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73}), .samps_zero_r_reg_4(u_poc_tap_base_n_74), .samps_zero_r_reg_5(u_poc_tap_base_n_75), .\sm_r_reg[0]_0 (u_poc_tap_base_n_54), .\sm_r_reg[0]_1 (u_poc_tap_base_n_55), .\tap_r_reg[0]_0 (u_poc_tap_base_n_46), .trailing_edge0(trailing_edge0), .trailing_edge00_in(trailing_edge00_in)); endmodule module ddr3_if_mig_7series_v4_0_rank_cntrl (act_delayed, read_this_rank_r, inhbt_act_faw_r, periodic_rd_request_r, periodic_rd_cntr1_r, \grant_r_reg[0] , \rtw_timer.rtw_cnt_r_reg[1]_0 , \periodic_rd_generation.periodic_rd_request_r_reg_0 , \inhbt_act_faw.inhbt_act_faw_r_reg_0 , \wtr_timer.wtr_cnt_r_reg[1]_0 , \grant_r_reg[3] , act_this_rank, CLK, read_this_rank, SR, \periodic_rd_generation.periodic_rd_request_r_reg_1 , \periodic_read_request.periodic_rd_grant_r_reg[0] , init_calib_complete_reg_rep__6, \periodic_rd_generation.read_this_rank_r_reg_0 , init_calib_complete_reg_rep__6_0, maint_prescaler_tick_r, \grant_r_reg[0]_0 , rstdiv0_sync_r1_reg_rep__21, rstdiv0_sync_r1_reg_rep__22, \grant_r_reg[2] , \wr_this_rank_r_reg[0] , \wr_this_rank_r_reg[0]_0 , \wr_this_rank_r_reg[0]_1 , rstdiv0_sync_r1_reg_rep__20, \inhbt_act_faw.faw_cnt_r_reg[1]_0 , \wtr_timer.wtr_cnt_r_reg[2]_0 ); output act_delayed; output read_this_rank_r; output inhbt_act_faw_r; output periodic_rd_request_r; output periodic_rd_cntr1_r; output \grant_r_reg[0] ; output [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; output \periodic_rd_generation.periodic_rd_request_r_reg_0 ; output [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg_0 ; output [2:0]\wtr_timer.wtr_cnt_r_reg[1]_0 ; output \grant_r_reg[3] ; input act_this_rank; input CLK; input read_this_rank; input [0:0]SR; input \periodic_rd_generation.periodic_rd_request_r_reg_1 ; input \periodic_read_request.periodic_rd_grant_r_reg[0] ; input init_calib_complete_reg_rep__6; input \periodic_rd_generation.read_this_rank_r_reg_0 ; input init_calib_complete_reg_rep__6_0; input maint_prescaler_tick_r; input \grant_r_reg[0]_0 ; input rstdiv0_sync_r1_reg_rep__21; input rstdiv0_sync_r1_reg_rep__22; input \grant_r_reg[2] ; input \wr_this_rank_r_reg[0] ; input \wr_this_rank_r_reg[0]_0 ; input \wr_this_rank_r_reg[0]_1 ; input rstdiv0_sync_r1_reg_rep__20; input [2:0]\inhbt_act_faw.faw_cnt_r_reg[1]_0 ; input [0:0]\wtr_timer.wtr_cnt_r_reg[2]_0 ; wire CLK; wire [0:0]SR; wire act_delayed; wire act_this_rank; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[2] ; wire \grant_r_reg[3] ; wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[1]_0 ; wire \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ; wire [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg_0 ; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire maint_prescaler_tick_r; wire periodic_rd_cntr1_r; wire \periodic_rd_generation.periodic_rd_request_r_reg_0 ; wire \periodic_rd_generation.periodic_rd_request_r_reg_1 ; wire \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ; wire \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ; wire \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ; wire \periodic_rd_generation.read_this_rank_r_reg_0 ; wire periodic_rd_request_r; wire [2:0]periodic_rd_timer_r; wire \periodic_read_request.periodic_rd_grant_r_reg[0] ; wire read_this_rank; wire read_this_rank_r; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire [1:0]rtw_cnt_ns; wire [0:0]rtw_cnt_r; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire \wr_this_rank_r_reg[0] ; wire \wr_this_rank_r_reg[0]_0 ; wire \wr_this_rank_r_reg[0]_1 ; wire [1:0]wtr_cnt_ns; wire [2:0]\wtr_timer.wtr_cnt_r_reg[1]_0 ; wire [0:0]\wtr_timer.wtr_cnt_r_reg[2]_0 ; LUT5 #( .INIT(32'hFFFF0001)) \grant_r[3]_i_8 (.I0(\wtr_timer.wtr_cnt_r_reg[1]_0 [1]), .I1(\wtr_timer.wtr_cnt_r_reg[1]_0 [2]), .I2(\wr_this_rank_r_reg[0]_0 ), .I3(\wr_this_rank_r_reg[0]_1 ), .I4(rstdiv0_sync_r1_reg_rep__20), .O(\grant_r_reg[3] )); LUT4 #( .INIT(16'h0040)) i___30_i_2 (.I0(periodic_rd_timer_r[1]), .I1(periodic_rd_timer_r[0]), .I2(maint_prescaler_tick_r), .I3(periodic_rd_timer_r[2]), .O(\periodic_rd_generation.periodic_rd_request_r_reg_0 )); (* BOX_TYPE = "PRIMITIVE" *) (* XILINX_LEGACY_PRIM = "SRLC32E" *) (* srl_bus_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl " *) (* srl_name = "\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 " *) SRL16E #( .INIT(16'h0000), .IS_CLK_INVERTED(1'b0)) \inhbt_act_faw.SRLC32E0 (.A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(CLK), .D(act_this_rank), .Q(act_delayed)); FDRE \inhbt_act_faw.faw_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.faw_cnt_r_reg[1]_0 [0]), .Q(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]), .R(1'b0)); FDRE \inhbt_act_faw.faw_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.faw_cnt_r_reg[1]_0 [1]), .Q(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]), .R(1'b0)); FDRE \inhbt_act_faw.faw_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.faw_cnt_r_reg[1]_0 [2]), .Q(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]), .R(1'b0)); LUT6 #( .INIT(64'h0001000020000220)) \inhbt_act_faw.inhbt_act_faw_r_i_1 (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]), .I1(rstdiv0_sync_r1_reg_rep__22), .I2(act_delayed), .I3(\grant_r_reg[2] ), .I4(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]), .I5(\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]), .O(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 )); FDRE \inhbt_act_faw.inhbt_act_faw_r_reg (.C(CLK), .CE(1'b1), .D(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ), .Q(inhbt_act_faw_r), .R(1'b0)); FDRE \periodic_rd_generation.periodic_rd_cntr1_r_reg (.C(CLK), .CE(1'b1), .D(\periodic_read_request.periodic_rd_grant_r_reg[0] ), .Q(periodic_rd_cntr1_r), .R(SR)); FDRE \periodic_rd_generation.periodic_rd_request_r_reg (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_request_r_reg_1 ), .Q(periodic_rd_request_r), .R(SR)); LUT6 #( .INIT(64'hBBFFFFBBBFFBFFBB)) \periodic_rd_generation.periodic_rd_timer_r[0]_i_1 (.I0(\periodic_rd_generation.read_this_rank_r_reg_0 ), .I1(init_calib_complete_reg_rep__6_0), .I2(periodic_rd_timer_r[1]), .I3(periodic_rd_timer_r[0]), .I4(maint_prescaler_tick_r), .I5(periodic_rd_timer_r[2]), .O(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h4004404040004040)) \periodic_rd_generation.periodic_rd_timer_r[1]_i_1 (.I0(\periodic_rd_generation.read_this_rank_r_reg_0 ), .I1(init_calib_complete_reg_rep__6_0), .I2(periodic_rd_timer_r[1]), .I3(periodic_rd_timer_r[0]), .I4(maint_prescaler_tick_r), .I5(periodic_rd_timer_r[2]), .O(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFBFBBBBBB)) \periodic_rd_generation.periodic_rd_timer_r[2]_i_1 (.I0(\periodic_rd_generation.read_this_rank_r_reg_0 ), .I1(init_calib_complete_reg_rep__6_0), .I2(periodic_rd_timer_r[1]), .I3(periodic_rd_timer_r[0]), .I4(maint_prescaler_tick_r), .I5(periodic_rd_timer_r[2]), .O(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 )); FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ), .Q(periodic_rd_timer_r[0]), .R(1'b0)); FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ), .Q(periodic_rd_timer_r[1]), .R(1'b0)); FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[2] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ), .Q(periodic_rd_timer_r[2]), .R(1'b0)); FDRE \periodic_rd_generation.read_this_rank_r_reg (.C(CLK), .CE(1'b1), .D(read_this_rank), .Q(read_this_rank_r), .R(1'b0)); FDRE \refresh_generation.refresh_bank_r_reg[0] (.C(CLK), .CE(1'b1), .D(init_calib_complete_reg_rep__6), .Q(\grant_r_reg[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1103" *) LUT4 #( .INIT(16'h0008)) \rtw_timer.rtw_cnt_r[0]_i_1 (.I0(\grant_r_reg[0]_0 ), .I1(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(rtw_cnt_r), .O(rtw_cnt_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1103" *) LUT4 #( .INIT(16'h0D05)) \rtw_timer.rtw_cnt_r[1]_i_1 (.I0(\grant_r_reg[0]_0 ), .I1(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(rtw_cnt_r), .O(rtw_cnt_ns[1])); FDRE \rtw_timer.rtw_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(rtw_cnt_ns[0]), .Q(rtw_cnt_r), .R(1'b0)); FDRE \rtw_timer.rtw_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(rtw_cnt_ns[1]), .Q(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .R(1'b0)); LUT4 #( .INIT(16'h0054)) \wtr_timer.wtr_cnt_r[0]_i_1 (.I0(\wtr_timer.wtr_cnt_r_reg[1]_0 [0]), .I1(\wtr_timer.wtr_cnt_r_reg[1]_0 [1]), .I2(\wtr_timer.wtr_cnt_r_reg[1]_0 [2]), .I3(\wr_this_rank_r_reg[0] ), .O(wtr_cnt_ns[0])); LUT6 #( .INIT(64'h0000000000000098)) \wtr_timer.wtr_cnt_r[1]_i_1 (.I0(\wtr_timer.wtr_cnt_r_reg[1]_0 [0]), .I1(\wtr_timer.wtr_cnt_r_reg[1]_0 [1]), .I2(\wtr_timer.wtr_cnt_r_reg[1]_0 [2]), .I3(\wr_this_rank_r_reg[0]_0 ), .I4(\wr_this_rank_r_reg[0]_1 ), .I5(rstdiv0_sync_r1_reg_rep__22), .O(wtr_cnt_ns[1])); FDRE \wtr_timer.wtr_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(wtr_cnt_ns[0]), .Q(\wtr_timer.wtr_cnt_r_reg[1]_0 [0]), .R(1'b0)); FDRE \wtr_timer.wtr_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(wtr_cnt_ns[1]), .Q(\wtr_timer.wtr_cnt_r_reg[1]_0 [1]), .R(1'b0)); FDRE \wtr_timer.wtr_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wtr_timer.wtr_cnt_r_reg[2]_0 ), .Q(\wtr_timer.wtr_cnt_r_reg[1]_0 [2]), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_rank_common (maint_prescaler_tick_r, maint_prescaler_tick_ns, \maintenance_request.new_maint_rank_r_reg_0 , \maintenance_request.maint_req_r_lcl_reg_0 , maint_req_r, \periodic_read_request.upd_last_master_r_reg_0 , app_ref_ack, app_zq_ack, \maint_controller.maint_srx_r1_reg , \maintenance_request.maint_sre_r_lcl_reg_0 , \grant_r_reg[0] , \grant_r_reg[0]_0 , \maintenance_request.maint_zq_r_lcl_reg_0 , periodic_rd_r, app_ref_r, app_zq_r, periodic_rd_r_cnt, periodic_rd_grant_r, app_sr_active, maint_ref_zq_wip, Q, \refresh_timer.refresh_timer_r_reg[5]_0 , \refresh_timer.refresh_timer_r_reg[4]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 , \maintenance_request.maint_sre_r_lcl_reg_1 , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] , \last_master_r_reg[2] , mc_cke_ns, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] , \refresh_generation.refresh_bank_r_reg[0] , S, \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 , CLK, \maint_controller.maint_wip_r_lcl_reg , SR, \zq_cntrl.zq_request_logic.zq_request_r_reg_0 , init_calib_complete_reg_rep__6, maint_prescaler_r1, periodic_rd_ack_r_lcl_reg, \refresh_generation.refresh_bank_r_reg[0]_0 , app_zq_r_reg_0, \periodic_read_request.periodic_rd_r_lcl_reg_0 , \periodic_rd_generation.periodic_rd_request_r_reg , \maintenance_request.maint_sre_r_lcl_reg_2 , in0, \refresh_generation.refresh_bank_r_reg[0]_1 , O, \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 , \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 , \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 , \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 , init_calib_complete_reg_rep__6_0, app_sr_req, D, \refresh_generation.refresh_bank_r_reg[0]_2 , \last_master_r_reg[2]_0 , rstdiv0_sync_r1_reg_rep__21, periodic_rd_request_r, cke_r, insert_maint_r1, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] , insert_maint_r, rstdiv0_sync_r1_reg_rep__22, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 , SS, \maint_prescaler.maint_prescaler_r_reg[0]_0 , init_calib_complete_reg_rep__6_1, \refresh_timer.refresh_timer_r_reg[0]_0 ); output maint_prescaler_tick_r; output maint_prescaler_tick_ns; output \maintenance_request.new_maint_rank_r_reg_0 ; output \maintenance_request.maint_req_r_lcl_reg_0 ; output maint_req_r; output \periodic_read_request.upd_last_master_r_reg_0 ; output app_ref_ack; output app_zq_ack; output \maint_controller.maint_srx_r1_reg ; output \maintenance_request.maint_sre_r_lcl_reg_0 ; output \grant_r_reg[0] ; output \grant_r_reg[0]_0 ; output \maintenance_request.maint_zq_r_lcl_reg_0 ; output periodic_rd_r; output app_ref_r; output app_zq_r; output periodic_rd_r_cnt; output periodic_rd_grant_r; output app_sr_active; output maint_ref_zq_wip; output [1:0]Q; output \refresh_timer.refresh_timer_r_reg[5]_0 ; output [1:0]\refresh_timer.refresh_timer_r_reg[4]_0 ; output \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ; output [2:0]\maintenance_request.maint_sre_r_lcl_reg_1 ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; output [2:0]\last_master_r_reg[2] ; output [0:0]mc_cke_ns; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; output \refresh_generation.refresh_bank_r_reg[0] ; output [3:0]S; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; input CLK; input \maint_controller.maint_wip_r_lcl_reg ; input [0:0]SR; input \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ; input init_calib_complete_reg_rep__6; input maint_prescaler_r1; input periodic_rd_ack_r_lcl_reg; input \refresh_generation.refresh_bank_r_reg[0]_0 ; input app_zq_r_reg_0; input \periodic_read_request.periodic_rd_r_lcl_reg_0 ; input \periodic_rd_generation.periodic_rd_request_r_reg ; input \maintenance_request.maint_sre_r_lcl_reg_2 ; input in0; input \refresh_generation.refresh_bank_r_reg[0]_1 ; input [3:0]O; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ; input init_calib_complete_reg_rep__6_0; input app_sr_req; input [1:0]D; input \refresh_generation.refresh_bank_r_reg[0]_2 ; input \last_master_r_reg[2]_0 ; input rstdiv0_sync_r1_reg_rep__21; input periodic_rd_request_r; input cke_r; input insert_maint_r1; input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ; input insert_maint_r; input rstdiv0_sync_r1_reg_rep__22; input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; input [0:0]SS; input [0:0]\maint_prescaler.maint_prescaler_r_reg[0]_0 ; input [0:0]init_calib_complete_reg_rep__6_1; input [0:0]\refresh_timer.refresh_timer_r_reg[0]_0 ; wire CLK; wire [1:0]D; wire [3:0]O; wire [1:0]Q; wire [3:0]S; wire [0:0]SR; wire [0:0]SS; wire app_ref_ack; wire app_ref_ack_ns; wire app_ref_r; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_ack_ns; wire app_zq_r; wire app_zq_r_reg_0; wire cke_r; wire [1:0]ckesr_timer_r; wire \grant_r_reg[0] ; wire \grant_r_reg[0]_0 ; wire i___21_i_3_n_0; wire in0; wire inhbt_srx; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire [0:0]init_calib_complete_reg_rep__6_1; wire insert_maint_r; wire insert_maint_r1; wire [2:0]\last_master_r_reg[2] ; wire \last_master_r_reg[2]_0 ; wire \maint_controller.maint_srx_r1_reg ; wire \maint_controller.maint_wip_r_lcl_reg ; wire [0:0]\maint_prescaler.maint_prescaler_r_reg[0]_0 ; wire [5:2]\maint_prescaler.maint_prescaler_r_reg__0 ; wire [5:0]maint_prescaler_r0; wire maint_prescaler_r1; wire maint_prescaler_tick_ns; wire maint_prescaler_tick_r; wire maint_ref_zq_wip; wire maint_req_r; wire \maintenance_request.maint_arb0_n_0 ; wire \maintenance_request.maint_arb0_n_4 ; wire \maintenance_request.maint_arb0_n_8 ; wire \maintenance_request.maint_req_r_lcl_reg_0 ; wire \maintenance_request.maint_sre_r_lcl_reg_0 ; wire [2:0]\maintenance_request.maint_sre_r_lcl_reg_1 ; wire \maintenance_request.maint_sre_r_lcl_reg_2 ; wire \maintenance_request.maint_srx_r_lcl_i_2_n_0 ; wire \maintenance_request.maint_zq_r_lcl_reg_0 ; wire \maintenance_request.new_maint_rank_r_reg_0 ; wire [0:0]mc_cke_ns; wire periodic_rd_ack_r_lcl_reg; wire \periodic_rd_generation.periodic_rd_request_r_reg ; wire periodic_rd_grant_r; wire periodic_rd_r; wire periodic_rd_r_cnt; wire periodic_rd_request_r; wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ; wire \periodic_read_request.upd_last_master_r_reg_0 ; wire \refresh_generation.refresh_bank_r_reg[0] ; wire \refresh_generation.refresh_bank_r_reg[0]_0 ; wire \refresh_generation.refresh_bank_r_reg[0]_1 ; wire \refresh_generation.refresh_bank_r_reg[0]_2 ; wire \refresh_timer.refresh_timer_r[5]_i_3_n_0 ; wire [0:0]\refresh_timer.refresh_timer_r_reg[0]_0 ; wire [1:0]\refresh_timer.refresh_timer_r_reg[4]_0 ; wire \refresh_timer.refresh_timer_r_reg[5]_0 ; wire [5:2]\refresh_timer.refresh_timer_r_reg__0 ; wire [5:0]refresh_timer_r0; wire refresh_timer_r0_0; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire sel; wire \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ; wire \sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ; wire upd_last_master_ns; wire \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ; wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ; wire [19:0]\zq_cntrl.zq_timer.zq_timer_r_reg ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ; wire zq_timer_r0; (* SOFT_HLUTNM = "soft_lutpair1110" *) LUT3 #( .INIT(8'h8A)) app_ref_ack_r_i_1 (.I0(app_ref_r), .I1(\refresh_generation.refresh_bank_r_reg[0]_2 ), .I2(init_calib_complete_reg_rep__6_0), .O(app_ref_ack_ns)); FDRE #( .INIT(1'b0)) app_ref_ack_r_reg (.C(CLK), .CE(1'b1), .D(app_ref_ack_ns), .Q(app_ref_ack), .R(1'b0)); FDRE #( .INIT(1'b0)) app_ref_r_reg (.C(CLK), .CE(1'b1), .D(\refresh_generation.refresh_bank_r_reg[0]_0 ), .Q(app_ref_r), .R(maint_prescaler_r1)); FDRE app_sr_active_r_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_sre_r_lcl_reg_2 ), .Q(app_sr_active), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1110" *) LUT3 #( .INIT(8'h2A)) app_zq_ack_r_i_1 (.I0(app_zq_r), .I1(init_calib_complete_reg_rep__6_0), .I2(\grant_r_reg[0] ), .O(app_zq_ack_ns)); FDRE #( .INIT(1'b0)) app_zq_ack_r_reg (.C(CLK), .CE(1'b1), .D(app_zq_ack_ns), .Q(app_zq_ack), .R(1'b0)); FDRE #( .INIT(1'b0)) app_zq_r_reg (.C(CLK), .CE(1'b1), .D(app_zq_r_reg_0), .Q(app_zq_r), .R(maint_prescaler_r1)); (* SOFT_HLUTNM = "soft_lutpair1107" *) LUT4 #( .INIT(16'h0ECC)) cke_r_i_2 (.I0(\maint_controller.maint_srx_r1_reg ), .I1(cke_r), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(insert_maint_r1), .O(mc_cke_ns)); LUT6 #( .INIT(64'h0000000000100000)) i___21_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [2]), .I1(\refresh_timer.refresh_timer_r_reg__0 [5]), .I2(maint_prescaler_tick_r), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I4(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I5(i___21_i_3_n_0), .O(\refresh_timer.refresh_timer_r_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair1107" *) LUT4 #( .INIT(16'h0100)) i___21_i_2 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I2(\maint_controller.maint_srx_r1_reg ), .I3(insert_maint_r1), .O(\refresh_generation.refresh_bank_r_reg[0] )); LUT2 #( .INIT(4'hE)) i___21_i_3 (.I0(\refresh_timer.refresh_timer_r_reg__0 [3]), .I1(\refresh_timer.refresh_timer_r_reg__0 [4]), .O(i___21_i_3_n_0)); LUT6 #( .INIT(64'hAAAA8AAAAAAAAAAA)) i___23_i_1 (.I0(init_calib_complete_reg_rep__6_0), .I1(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ), .I2(maint_prescaler_tick_r), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ), .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair1104" *) LUT3 #( .INIT(8'h54)) i___24_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maint_controller.maint_srx_r1_reg ), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair1106" *) LUT1 #( .INIT(2'h1)) \maint_prescaler.maint_prescaler_r[0]_i_1 (.I0(Q[0]), .O(maint_prescaler_r0[0])); (* SOFT_HLUTNM = "soft_lutpair1109" *) LUT3 #( .INIT(8'hA9)) \maint_prescaler.maint_prescaler_r[2]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I1(Q[1]), .I2(Q[0]), .O(maint_prescaler_r0[2])); (* SOFT_HLUTNM = "soft_lutpair1109" *) LUT4 #( .INIT(16'hAAA9)) \maint_prescaler.maint_prescaler_r[3]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I2(Q[0]), .I3(Q[1]), .O(maint_prescaler_r0[3])); (* SOFT_HLUTNM = "soft_lutpair1106" *) LUT5 #( .INIT(32'hAAAAAAA9)) \maint_prescaler.maint_prescaler_r[4]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I2(Q[1]), .I3(Q[0]), .I4(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .O(maint_prescaler_r0[4])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \maint_prescaler.maint_prescaler_r[5]_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I2(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .I3(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I4(Q[0]), .I5(Q[1]), .O(sel)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \maint_prescaler.maint_prescaler_r[5]_i_2 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .I1(Q[1]), .I2(Q[0]), .I3(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .I4(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I5(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .O(maint_prescaler_r0[5])); FDRE \maint_prescaler.maint_prescaler_r_reg[0] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[0]), .Q(Q[0]), .R(SS)); FDRE \maint_prescaler.maint_prescaler_r_reg[1] (.C(CLK), .CE(sel), .D(\maint_prescaler.maint_prescaler_r_reg[0]_0 ), .Q(Q[1]), .R(SS)); FDSE \maint_prescaler.maint_prescaler_r_reg[2] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[2]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .S(SS)); FDSE \maint_prescaler.maint_prescaler_r_reg[3] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[3]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .S(SS)); FDRE \maint_prescaler.maint_prescaler_r_reg[4] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[4]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .R(SS)); FDSE \maint_prescaler.maint_prescaler_r_reg[5] (.C(CLK), .CE(sel), .D(maint_prescaler_r0[5]), .Q(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .S(SS)); LUT6 #( .INIT(64'h0000000000010000)) \maint_prescaler.maint_prescaler_tick_r_lcl_i_1 (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [5]), .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]), .I2(\maint_prescaler.maint_prescaler_r_reg__0 [4]), .I3(Q[1]), .I4(Q[0]), .I5(\maint_prescaler.maint_prescaler_r_reg__0 [2]), .O(maint_prescaler_tick_ns)); FDRE \maint_prescaler.maint_prescaler_tick_r_lcl_reg (.C(CLK), .CE(1'b1), .D(maint_prescaler_tick_ns), .Q(maint_prescaler_tick_r), .R(1'b0)); FDRE #( .INIT(1'b0)) maint_ref_zq_wip_r_reg (.C(CLK), .CE(1'b1), .D(\refresh_generation.refresh_bank_r_reg[0]_1 ), .Q(maint_ref_zq_wip), .R(in0)); ddr3_if_mig_7series_v4_0_round_robin_arb \maintenance_request.maint_arb0 (.CLK(CLK), .D(D), .Q(\maintenance_request.maint_sre_r_lcl_reg_1 ), .app_sr_req(app_sr_req), .ckesr_timer_r(ckesr_timer_r), .inhbt_srx(inhbt_srx), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0), .\last_master_r_reg[2]_0 (\last_master_r_reg[2] ), .\last_master_r_reg[2]_1 (\last_master_r_reg[2]_0 ), .\maintenance_request.maint_sre_r_lcl_reg (\maintenance_request.maint_arb0_n_0 ), .\maintenance_request.maint_sre_r_lcl_reg_0 (\maintenance_request.maint_sre_r_lcl_reg_0 ), .\maintenance_request.maint_srx_r_lcl_reg (\maintenance_request.maint_arb0_n_4 ), .\maintenance_request.maint_srx_r_lcl_reg_0 (\maint_controller.maint_srx_r1_reg ), .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_arb0_n_8 ), .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ), .\maintenance_request.new_maint_rank_r_reg (\maintenance_request.maint_req_r_lcl_reg_0 ), .\maintenance_request.upd_last_master_r_reg (\maintenance_request.maint_srx_r_lcl_i_2_n_0 ), .\maintenance_request.upd_last_master_r_reg_0 (\maintenance_request.new_maint_rank_r_reg_0 ), .\refresh_generation.refresh_bank_r_reg[0] (\refresh_generation.refresh_bank_r_reg[0]_2 ), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .\sr_cntrl.sre_request_logic.sre_request_r_reg (\grant_r_reg[0]_0 ), .\zq_cntrl.zq_request_logic.zq_request_r_reg (\grant_r_reg[0] )); FDRE \maintenance_request.maint_req_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_req_r_lcl_reg_0 ), .Q(maint_req_r), .R(1'b0)); FDRE \maintenance_request.maint_sre_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_arb0_n_0 ), .Q(\maintenance_request.maint_sre_r_lcl_reg_0 ), .R(SR)); LUT2 #( .INIT(4'h2)) \maintenance_request.maint_srx_r_lcl_i_2 (.I0(\maintenance_request.new_maint_rank_r_reg_0 ), .I1(\maintenance_request.maint_req_r_lcl_reg_0 ), .O(\maintenance_request.maint_srx_r_lcl_i_2_n_0 )); LUT2 #( .INIT(4'hE)) \maintenance_request.maint_srx_r_lcl_i_3 (.I0(ckesr_timer_r[0]), .I1(ckesr_timer_r[1]), .O(inhbt_srx)); FDRE \maintenance_request.maint_srx_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_arb0_n_4 ), .Q(\maint_controller.maint_srx_r1_reg ), .R(SR)); FDRE \maintenance_request.maint_zq_r_lcl_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.maint_arb0_n_8 ), .Q(\maintenance_request.maint_zq_r_lcl_reg_0 ), .R(SR)); FDRE \maintenance_request.new_maint_rank_r_reg (.C(CLK), .CE(1'b1), .D(\maintenance_request.new_maint_rank_r_reg_0 ), .Q(\maintenance_request.maint_req_r_lcl_reg_0 ), .R(1'b0)); FDRE \maintenance_request.upd_last_master_r_reg (.C(CLK), .CE(1'b1), .D(\maint_controller.maint_wip_r_lcl_reg ), .Q(\maintenance_request.new_maint_rank_r_reg_0 ), .R(1'b0)); FDRE \periodic_read_request.periodic_rd_grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\periodic_rd_generation.periodic_rd_request_r_reg ), .Q(periodic_rd_grant_r), .R(1'b0)); FDRE \periodic_read_request.periodic_rd_r_cnt_reg (.C(CLK), .CE(1'b1), .D(\periodic_read_request.periodic_rd_r_lcl_reg_0 ), .Q(periodic_rd_r_cnt), .R(SR)); FDRE \periodic_read_request.periodic_rd_r_lcl_reg (.C(CLK), .CE(1'b1), .D(periodic_rd_ack_r_lcl_reg), .Q(periodic_rd_r), .R(maint_prescaler_r1)); LUT4 #( .INIT(16'h0008)) \periodic_read_request.upd_last_master_r_i_1 (.I0(periodic_rd_request_r), .I1(init_calib_complete_reg_rep__6_0), .I2(\periodic_read_request.upd_last_master_r_reg_0 ), .I3(periodic_rd_r), .O(upd_last_master_ns)); FDRE \periodic_read_request.upd_last_master_r_reg (.C(CLK), .CE(1'b1), .D(upd_last_master_ns), .Q(\periodic_read_request.upd_last_master_r_reg_0 ), .R(1'b0)); LUT1 #( .INIT(2'h1)) \refresh_timer.refresh_timer_r[0]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .O(refresh_timer_r0[0])); (* SOFT_HLUTNM = "soft_lutpair1111" *) LUT3 #( .INIT(8'hA9)) \refresh_timer.refresh_timer_r[2]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [2]), .I1(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I2(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .O(refresh_timer_r0[2])); (* SOFT_HLUTNM = "soft_lutpair1105" *) LUT4 #( .INIT(16'hAAA9)) \refresh_timer.refresh_timer_r[3]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [3]), .I1(\refresh_timer.refresh_timer_r_reg__0 [2]), .I2(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .O(refresh_timer_r0[3])); (* SOFT_HLUTNM = "soft_lutpair1105" *) LUT5 #( .INIT(32'hAAAAAAA9)) \refresh_timer.refresh_timer_r[4]_i_1 (.I0(\refresh_timer.refresh_timer_r_reg__0 [4]), .I1(\refresh_timer.refresh_timer_r_reg__0 [3]), .I2(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I4(\refresh_timer.refresh_timer_r_reg__0 [2]), .O(refresh_timer_r0[4])); LUT5 #( .INIT(32'hAAAAAA8A)) \refresh_timer.refresh_timer_r[5]_i_1 (.I0(maint_prescaler_tick_r), .I1(\refresh_timer.refresh_timer_r_reg__0 [5]), .I2(\refresh_timer.refresh_timer_r[5]_i_3_n_0 ), .I3(\refresh_timer.refresh_timer_r_reg__0 [4]), .I4(\refresh_timer.refresh_timer_r_reg__0 [3]), .O(refresh_timer_r0_0)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \refresh_timer.refresh_timer_r[5]_i_2 (.I0(\refresh_timer.refresh_timer_r_reg__0 [5]), .I1(\refresh_timer.refresh_timer_r_reg__0 [3]), .I2(\refresh_timer.refresh_timer_r_reg__0 [4]), .I3(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I4(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I5(\refresh_timer.refresh_timer_r_reg__0 [2]), .O(refresh_timer_r0[5])); (* SOFT_HLUTNM = "soft_lutpair1111" *) LUT3 #( .INIT(8'h01)) \refresh_timer.refresh_timer_r[5]_i_3 (.I0(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .I1(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .I2(\refresh_timer.refresh_timer_r_reg__0 [2]), .O(\refresh_timer.refresh_timer_r[5]_i_3_n_0 )); FDRE \refresh_timer.refresh_timer_r_reg[0] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[0]), .Q(\refresh_timer.refresh_timer_r_reg[4]_0 [0]), .R(init_calib_complete_reg_rep__6_1)); FDSE \refresh_timer.refresh_timer_r_reg[1] (.C(CLK), .CE(refresh_timer_r0_0), .D(\refresh_timer.refresh_timer_r_reg[0]_0 ), .Q(\refresh_timer.refresh_timer_r_reg[4]_0 [1]), .S(init_calib_complete_reg_rep__6_1)); FDSE \refresh_timer.refresh_timer_r_reg[2] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[2]), .Q(\refresh_timer.refresh_timer_r_reg__0 [2]), .S(init_calib_complete_reg_rep__6_1)); FDRE \refresh_timer.refresh_timer_r_reg[3] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[3]), .Q(\refresh_timer.refresh_timer_r_reg__0 [3]), .R(init_calib_complete_reg_rep__6_1)); FDRE \refresh_timer.refresh_timer_r_reg[4] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[4]), .Q(\refresh_timer.refresh_timer_r_reg__0 [4]), .R(init_calib_complete_reg_rep__6_1)); FDSE \refresh_timer.refresh_timer_r_reg[5] (.C(CLK), .CE(refresh_timer_r0_0), .D(refresh_timer_r0[5]), .Q(\refresh_timer.refresh_timer_r_reg__0 [5]), .S(init_calib_complete_reg_rep__6_1)); LUT6 #( .INIT(64'h00000000010100FF)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 (.I0(\maint_controller.maint_srx_r1_reg ), .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .I4(insert_maint_r), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1104" *) LUT5 #( .INIT(32'h00000100)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_2 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I2(\maint_controller.maint_srx_r1_reg ), .I3(insert_maint_r), .I4(rstdiv0_sync_r1_reg_rep__22), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] )); LUT6 #( .INIT(64'h5555555555555D55)) \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_5 (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ), .I1(insert_maint_r), .I2(rstdiv0_sync_r1_reg_rep__22), .I3(\maint_controller.maint_srx_r1_reg ), .I4(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I5(\maintenance_request.maint_sre_r_lcl_reg_0 ), .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] )); (* SOFT_HLUTNM = "soft_lutpair1108" *) LUT4 #( .INIT(16'h0222)) \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 (.I0(ckesr_timer_r[1]), .I1(ckesr_timer_r[0]), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(insert_maint_r1), .O(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1108" *) LUT4 #( .INIT(16'hF888)) \sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1 (.I0(ckesr_timer_r[1]), .I1(ckesr_timer_r[0]), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(insert_maint_r1), .O(\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] (.C(CLK), .CE(1'b1), .D(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ), .Q(ckesr_timer_r[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[1] (.C(CLK), .CE(1'b1), .D(\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ), .Q(ckesr_timer_r[1]), .R(1'b0)); FDRE \sr_cntrl.sre_request_logic.sre_request_r_reg (.C(CLK), .CE(1'b1), .D(init_calib_complete_reg_rep__6), .Q(\grant_r_reg[0]_0 ), .R(SR)); FDRE \zq_cntrl.zq_request_logic.zq_request_r_reg (.C(CLK), .CE(1'b1), .D(\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ), .Q(\grant_r_reg[0] ), .R(SR)); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_1 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ), .O(zq_timer_r0)); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_10 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .O(S[0])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_11 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [5]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [4]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [7]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [17]), .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [3]), .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [18]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 )); LUT5 #( .INIT(32'hAAA8AAAA)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_2 (.I0(maint_prescaler_tick_r), .I1(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ), .I2(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [10]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [11]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [12]), .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [14]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 )); LUT4 #( .INIT(16'hFFFE)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [1]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [16]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [15]), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 )); LUT5 #( .INIT(32'h00000001)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_6 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]), .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [8]), .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ), .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_7 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [3]), .O(S[3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_8 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .O(S[2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[0]_i_9 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [1]), .O(S[1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [15]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[12]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [12]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [0])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[16]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [16]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [0])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [5]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[4]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [4]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [0])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_2 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [11]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [3])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_3 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [10]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [2])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_4 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [1])); LUT1 #( .INIT(2'h1)) \zq_cntrl.zq_timer.zq_timer_r[8]_i_5 (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [8]), .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [0])); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[0] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [0]), .R(zq_timer_r0)); FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[10] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [10]), .S(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[11] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [11]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[12] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [12]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[13] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [13]), .R(zq_timer_r0)); FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[14] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [14]), .S(zq_timer_r0)); FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[15] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [15]), .S(zq_timer_r0)); FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[16] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [16]), .S(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[17] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [17]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[18] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [18]), .R(zq_timer_r0)); FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[19] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [19]), .S(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[1] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [1]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[2] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [2]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[3] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(O[3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [3]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[4] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [4]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[5] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [5]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[6] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [2]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [6]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[7] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [3]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [7]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[8] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [0]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [8]), .R(zq_timer_r0)); FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[9] (.C(CLK), .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ), .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [1]), .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [9]), .R(zq_timer_r0)); endmodule module ddr3_if_mig_7series_v4_0_rank_mach (act_delayed, maint_prescaler_tick_ns, upd_last_master_r, new_maint_rank_r, maint_req_r, \periodic_read_request.upd_last_master_r_reg , app_ref_ack, app_zq_ack, read_this_rank_r, inhbt_act_faw_r, maint_srx_r, maint_sre_r, zq_request_r, sre_request_r, maint_zq_r, periodic_rd_request_r, periodic_rd_r, app_ref_r, app_zq_r, periodic_rd_r_cnt, periodic_rd_grant_r, app_sr_active, maint_ref_zq_wip, periodic_rd_cntr1_r, refresh_bank_r, Q, \refresh_timer.refresh_timer_r_reg[5] , \refresh_timer.refresh_timer_r_reg[4] , \zq_cntrl.zq_timer.zq_timer_r_reg[0] , \maintenance_request.maint_sre_r_lcl_reg , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] , \last_master_r_reg[2] , \rtw_timer.rtw_cnt_r_reg[1] , mc_cke_ns, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] , \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] , \refresh_generation.refresh_bank_r_reg[0] , S, \zq_cntrl.zq_timer.zq_timer_r_reg[7] , \zq_cntrl.zq_timer.zq_timer_r_reg[11] , \zq_cntrl.zq_timer.zq_timer_r_reg[15] , \zq_cntrl.zq_timer.zq_timer_r_reg[19] , \periodic_rd_generation.periodic_rd_request_r_reg , \inhbt_act_faw.inhbt_act_faw_r_reg , \wtr_timer.wtr_cnt_r_reg[1] , \grant_r_reg[3] , act_this_rank, CLK, \maint_controller.maint_wip_r_lcl_reg , read_this_rank, SR, \zq_cntrl.zq_request_logic.zq_request_r_reg , init_calib_complete_reg_rep__6, \periodic_rd_generation.periodic_rd_request_r_reg_0 , maint_prescaler_r1, periodic_rd_ack_r_lcl_reg, \refresh_generation.refresh_bank_r_reg[0]_0 , app_zq_r_reg, \periodic_read_request.periodic_rd_r_lcl_reg , \periodic_rd_generation.periodic_rd_request_r_reg_1 , \maintenance_request.maint_sre_r_lcl_reg_0 , in0, \refresh_generation.refresh_bank_r_reg[0]_1 , \periodic_read_request.periodic_rd_grant_r_reg[0] , init_calib_complete_reg_rep__6_0, O, \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 , \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 , \periodic_rd_generation.read_this_rank_r_reg , init_calib_complete_reg_rep__6_1, app_sr_req, D, \last_master_r_reg[2]_0 , rstdiv0_sync_r1_reg_rep__21, \grant_r_reg[0] , cke_r, insert_maint_r1, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] , insert_maint_r, rstdiv0_sync_r1_reg_rep__22, \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 , \grant_r_reg[2] , \wr_this_rank_r_reg[0] , \wr_this_rank_r_reg[0]_0 , \wr_this_rank_r_reg[0]_1 , rstdiv0_sync_r1_reg_rep__20, \inhbt_act_faw.faw_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[2] , SS, \maint_prescaler.maint_prescaler_r_reg[0] , init_calib_complete_reg_rep__6_2, \refresh_timer.refresh_timer_r_reg[0] ); output act_delayed; output maint_prescaler_tick_ns; output upd_last_master_r; output new_maint_rank_r; output maint_req_r; output \periodic_read_request.upd_last_master_r_reg ; output app_ref_ack; output app_zq_ack; output read_this_rank_r; output inhbt_act_faw_r; output maint_srx_r; output maint_sre_r; output zq_request_r; output sre_request_r; output maint_zq_r; output periodic_rd_request_r; output periodic_rd_r; output app_ref_r; output app_zq_r; output periodic_rd_r_cnt; output periodic_rd_grant_r; output app_sr_active; output maint_ref_zq_wip; output periodic_rd_cntr1_r; output refresh_bank_r; output [1:0]Q; output \refresh_timer.refresh_timer_r_reg[5] ; output [1:0]\refresh_timer.refresh_timer_r_reg[4] ; output \zq_cntrl.zq_timer.zq_timer_r_reg[0] ; output [2:0]\maintenance_request.maint_sre_r_lcl_reg ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; output [2:0]\last_master_r_reg[2] ; output [0:0]\rtw_timer.rtw_cnt_r_reg[1] ; output [0:0]mc_cke_ns; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; output [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; output \refresh_generation.refresh_bank_r_reg[0] ; output [3:0]S; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ; output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ; output \periodic_rd_generation.periodic_rd_request_r_reg ; output [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg ; output [2:0]\wtr_timer.wtr_cnt_r_reg[1] ; output \grant_r_reg[3] ; input act_this_rank; input CLK; input \maint_controller.maint_wip_r_lcl_reg ; input read_this_rank; input [0:0]SR; input \zq_cntrl.zq_request_logic.zq_request_r_reg ; input init_calib_complete_reg_rep__6; input \periodic_rd_generation.periodic_rd_request_r_reg_0 ; input maint_prescaler_r1; input periodic_rd_ack_r_lcl_reg; input \refresh_generation.refresh_bank_r_reg[0]_0 ; input app_zq_r_reg; input \periodic_read_request.periodic_rd_r_lcl_reg ; input \periodic_rd_generation.periodic_rd_request_r_reg_1 ; input \maintenance_request.maint_sre_r_lcl_reg_0 ; input in0; input \refresh_generation.refresh_bank_r_reg[0]_1 ; input \periodic_read_request.periodic_rd_grant_r_reg[0] ; input init_calib_complete_reg_rep__6_0; input [3:0]O; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; input \periodic_rd_generation.read_this_rank_r_reg ; input init_calib_complete_reg_rep__6_1; input app_sr_req; input [1:0]D; input \last_master_r_reg[2]_0 ; input rstdiv0_sync_r1_reg_rep__21; input \grant_r_reg[0] ; input cke_r; input insert_maint_r1; input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ; input insert_maint_r; input rstdiv0_sync_r1_reg_rep__22; input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; input \grant_r_reg[2] ; input \wr_this_rank_r_reg[0] ; input \wr_this_rank_r_reg[0]_0 ; input \wr_this_rank_r_reg[0]_1 ; input rstdiv0_sync_r1_reg_rep__20; input [2:0]\inhbt_act_faw.faw_cnt_r_reg[1] ; input [0:0]\wtr_timer.wtr_cnt_r_reg[2] ; input [0:0]SS; input [0:0]\maint_prescaler.maint_prescaler_r_reg[0] ; input [0:0]init_calib_complete_reg_rep__6_2; input [0:0]\refresh_timer.refresh_timer_r_reg[0] ; wire CLK; wire [1:0]D; wire [3:0]O; wire [1:0]Q; wire [3:0]S; wire [0:0]SR; wire [0:0]SS; wire act_delayed; wire act_this_rank; wire app_ref_ack; wire app_ref_r; wire app_sr_active; wire app_sr_req; wire app_zq_ack; wire app_zq_r; wire app_zq_r_reg; wire cke_r; wire \grant_r_reg[0] ; wire \grant_r_reg[2] ; wire \grant_r_reg[3] ; wire in0; wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[1] ; wire [2:0]\inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire init_calib_complete_reg_rep__6; wire init_calib_complete_reg_rep__6_0; wire init_calib_complete_reg_rep__6_1; wire [0:0]init_calib_complete_reg_rep__6_2; wire insert_maint_r; wire insert_maint_r1; wire [2:0]\last_master_r_reg[2] ; wire \last_master_r_reg[2]_0 ; wire \maint_controller.maint_wip_r_lcl_reg ; wire [0:0]\maint_prescaler.maint_prescaler_r_reg[0] ; wire maint_prescaler_r1; wire maint_prescaler_tick_ns; wire maint_prescaler_tick_r; wire maint_ref_zq_wip; wire maint_req_r; wire maint_sre_r; wire maint_srx_r; wire maint_zq_r; wire [2:0]\maintenance_request.maint_sre_r_lcl_reg ; wire \maintenance_request.maint_sre_r_lcl_reg_0 ; wire [0:0]mc_cke_ns; wire new_maint_rank_r; wire periodic_rd_ack_r_lcl_reg; wire periodic_rd_cntr1_r; wire \periodic_rd_generation.periodic_rd_request_r_reg ; wire \periodic_rd_generation.periodic_rd_request_r_reg_0 ; wire \periodic_rd_generation.periodic_rd_request_r_reg_1 ; wire \periodic_rd_generation.read_this_rank_r_reg ; wire periodic_rd_grant_r; wire periodic_rd_r; wire periodic_rd_r_cnt; wire periodic_rd_request_r; wire \periodic_read_request.periodic_rd_grant_r_reg[0] ; wire \periodic_read_request.periodic_rd_r_lcl_reg ; wire \periodic_read_request.upd_last_master_r_reg ; wire read_this_rank; wire read_this_rank_r; wire refresh_bank_r; wire \refresh_generation.refresh_bank_r_reg[0] ; wire \refresh_generation.refresh_bank_r_reg[0]_0 ; wire \refresh_generation.refresh_bank_r_reg[0]_1 ; wire [0:0]\refresh_timer.refresh_timer_r_reg[0] ; wire [1:0]\refresh_timer.refresh_timer_r_reg[4] ; wire \refresh_timer.refresh_timer_r_reg[5] ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ; wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ; wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ; wire rstdiv0_sync_r1_reg_rep__20; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1] ; wire sre_request_r; wire upd_last_master_r; wire \wr_this_rank_r_reg[0] ; wire \wr_this_rank_r_reg[0]_0 ; wire \wr_this_rank_r_reg[0]_1 ; wire [2:0]\wtr_timer.wtr_cnt_r_reg[1] ; wire [0:0]\wtr_timer.wtr_cnt_r_reg[2] ; wire \zq_cntrl.zq_request_logic.zq_request_r_reg ; wire \zq_cntrl.zq_timer.zq_timer_r_reg[0] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ; wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ; wire zq_request_r; ddr3_if_mig_7series_v4_0_rank_cntrl \rank_cntrl[0].rank_cntrl0 (.CLK(CLK), .SR(SR), .act_delayed(act_delayed), .act_this_rank(act_this_rank), .\grant_r_reg[0] (refresh_bank_r), .\grant_r_reg[0]_0 (\grant_r_reg[0] ), .\grant_r_reg[2] (\grant_r_reg[2] ), .\grant_r_reg[3] (\grant_r_reg[3] ), .\inhbt_act_faw.faw_cnt_r_reg[1]_0 (\inhbt_act_faw.faw_cnt_r_reg[1] ), .\inhbt_act_faw.inhbt_act_faw_r_reg_0 (\inhbt_act_faw.inhbt_act_faw_r_reg ), .inhbt_act_faw_r(inhbt_act_faw_r), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1), .maint_prescaler_tick_r(maint_prescaler_tick_r), .periodic_rd_cntr1_r(periodic_rd_cntr1_r), .\periodic_rd_generation.periodic_rd_request_r_reg_0 (\periodic_rd_generation.periodic_rd_request_r_reg ), .\periodic_rd_generation.periodic_rd_request_r_reg_1 (\periodic_rd_generation.periodic_rd_request_r_reg_0 ), .\periodic_rd_generation.read_this_rank_r_reg_0 (\periodic_rd_generation.read_this_rank_r_reg ), .periodic_rd_request_r(periodic_rd_request_r), .\periodic_read_request.periodic_rd_grant_r_reg[0] (\periodic_read_request.periodic_rd_grant_r_reg[0] ), .read_this_rank(read_this_rank), .read_this_rank_r(read_this_rank_r), .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1] ), .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ), .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ), .\wr_this_rank_r_reg[0]_1 (\wr_this_rank_r_reg[0]_1 ), .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1] ), .\wtr_timer.wtr_cnt_r_reg[2]_0 (\wtr_timer.wtr_cnt_r_reg[2] )); ddr3_if_mig_7series_v4_0_rank_common rank_common0 (.CLK(CLK), .D(D), .O(O), .Q(Q), .S(S), .SR(SR), .SS(SS), .app_ref_ack(app_ref_ack), .app_ref_r(app_ref_r), .app_sr_active(app_sr_active), .app_sr_req(app_sr_req), .app_zq_ack(app_zq_ack), .app_zq_r(app_zq_r), .app_zq_r_reg_0(app_zq_r_reg), .cke_r(cke_r), .\grant_r_reg[0] (zq_request_r), .\grant_r_reg[0]_0 (sre_request_r), .in0(in0), .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6), .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1), .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6_2), .insert_maint_r(insert_maint_r), .insert_maint_r1(insert_maint_r1), .\last_master_r_reg[2] (\last_master_r_reg[2] ), .\last_master_r_reg[2]_0 (\last_master_r_reg[2]_0 ), .\maint_controller.maint_srx_r1_reg (maint_srx_r), .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ), .\maint_prescaler.maint_prescaler_r_reg[0]_0 (\maint_prescaler.maint_prescaler_r_reg[0] ), .maint_prescaler_r1(maint_prescaler_r1), .maint_prescaler_tick_ns(maint_prescaler_tick_ns), .maint_prescaler_tick_r(maint_prescaler_tick_r), .maint_ref_zq_wip(maint_ref_zq_wip), .maint_req_r(maint_req_r), .\maintenance_request.maint_req_r_lcl_reg_0 (new_maint_rank_r), .\maintenance_request.maint_sre_r_lcl_reg_0 (maint_sre_r), .\maintenance_request.maint_sre_r_lcl_reg_1 (\maintenance_request.maint_sre_r_lcl_reg ), .\maintenance_request.maint_sre_r_lcl_reg_2 (\maintenance_request.maint_sre_r_lcl_reg_0 ), .\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r), .\maintenance_request.new_maint_rank_r_reg_0 (upd_last_master_r), .mc_cke_ns(mc_cke_ns), .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg), .\periodic_rd_generation.periodic_rd_request_r_reg (\periodic_rd_generation.periodic_rd_request_r_reg_1 ), .periodic_rd_grant_r(periodic_rd_grant_r), .periodic_rd_r(periodic_rd_r), .periodic_rd_r_cnt(periodic_rd_r_cnt), .periodic_rd_request_r(periodic_rd_request_r), .\periodic_read_request.periodic_rd_r_lcl_reg_0 (\periodic_read_request.periodic_rd_r_lcl_reg ), .\periodic_read_request.upd_last_master_r_reg_0 (\periodic_read_request.upd_last_master_r_reg ), .\refresh_generation.refresh_bank_r_reg[0] (\refresh_generation.refresh_bank_r_reg[0] ), .\refresh_generation.refresh_bank_r_reg[0]_0 (\refresh_generation.refresh_bank_r_reg[0]_0 ), .\refresh_generation.refresh_bank_r_reg[0]_1 (\refresh_generation.refresh_bank_r_reg[0]_1 ), .\refresh_generation.refresh_bank_r_reg[0]_2 (refresh_bank_r), .\refresh_timer.refresh_timer_r_reg[0]_0 (\refresh_timer.refresh_timer_r_reg[0] ), .\refresh_timer.refresh_timer_r_reg[4]_0 (\refresh_timer.refresh_timer_r_reg[4] ), .\refresh_timer.refresh_timer_r_reg[5]_0 (\refresh_timer.refresh_timer_r_reg[5] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ), .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ), .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21), .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22), .\zq_cntrl.zq_request_logic.zq_request_r_reg_0 (\zq_cntrl.zq_request_logic.zq_request_r_reg ), .\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[0] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[11] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ), .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[15] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ), .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[19] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ), .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[7] ), .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 )); endmodule module ddr3_if_mig_7series_v4_0_round_robin_arb (\maintenance_request.maint_sre_r_lcl_reg , Q, \maintenance_request.maint_srx_r_lcl_reg , \last_master_r_reg[2]_0 , \maintenance_request.maint_zq_r_lcl_reg , \maintenance_request.upd_last_master_r_reg , \maintenance_request.maint_sre_r_lcl_reg_0 , ckesr_timer_r, app_sr_req, \maintenance_request.maint_srx_r_lcl_reg_0 , inhbt_srx, D, init_calib_complete_reg_rep__6, \refresh_generation.refresh_bank_r_reg[0] , \sr_cntrl.sre_request_logic.sre_request_r_reg , \zq_cntrl.zq_request_logic.zq_request_r_reg , \last_master_r_reg[2]_1 , \maintenance_request.upd_last_master_r_reg_0 , \maintenance_request.new_maint_rank_r_reg , rstdiv0_sync_r1_reg_rep__21, \maintenance_request.maint_zq_r_lcl_reg_0 , CLK); output \maintenance_request.maint_sre_r_lcl_reg ; output [2:0]Q; output \maintenance_request.maint_srx_r_lcl_reg ; output [2:0]\last_master_r_reg[2]_0 ; output \maintenance_request.maint_zq_r_lcl_reg ; input \maintenance_request.upd_last_master_r_reg ; input \maintenance_request.maint_sre_r_lcl_reg_0 ; input [1:0]ckesr_timer_r; input app_sr_req; input \maintenance_request.maint_srx_r_lcl_reg_0 ; input inhbt_srx; input [1:0]D; input init_calib_complete_reg_rep__6; input \refresh_generation.refresh_bank_r_reg[0] ; input \sr_cntrl.sre_request_logic.sre_request_r_reg ; input \zq_cntrl.zq_request_logic.zq_request_r_reg ; input \last_master_r_reg[2]_1 ; input \maintenance_request.upd_last_master_r_reg_0 ; input \maintenance_request.new_maint_rank_r_reg ; input rstdiv0_sync_r1_reg_rep__21; input \maintenance_request.maint_zq_r_lcl_reg_0 ; input CLK; wire CLK; wire [1:0]D; wire [2:0]Q; wire app_sr_req; wire [1:0]ckesr_timer_r; wire \grant_r[0]_i_1_n_0 ; wire \grant_r[1]_i_1_n_0 ; wire \grant_r[2]_i_1_n_0 ; wire inhbt_srx; wire init_calib_complete_reg_rep__6; wire \last_master_r[2]_i_1_n_0 ; wire [2:0]\last_master_r_reg[2]_0 ; wire \last_master_r_reg[2]_1 ; wire \maintenance_request.maint_sre_r_lcl_reg ; wire \maintenance_request.maint_sre_r_lcl_reg_0 ; wire \maintenance_request.maint_srx_r_lcl_reg ; wire \maintenance_request.maint_srx_r_lcl_reg_0 ; wire \maintenance_request.maint_zq_r_lcl_reg ; wire \maintenance_request.maint_zq_r_lcl_reg_0 ; wire \maintenance_request.new_maint_rank_r_reg ; wire \maintenance_request.upd_last_master_r_reg ; wire \maintenance_request.upd_last_master_r_reg_0 ; wire \refresh_generation.refresh_bank_r_reg[0] ; wire rstdiv0_sync_r1_reg_rep__21; wire \sr_cntrl.sre_request_logic.sre_request_r_reg ; wire \zq_cntrl.zq_request_logic.zq_request_r_reg ; LUT6 #( .INIT(64'h0000000C040C040C)) \grant_r[0]_i_1 (.I0(D[1]), .I1(init_calib_complete_reg_rep__6), .I2(\refresh_generation.refresh_bank_r_reg[0] ), .I3(\sr_cntrl.sre_request_logic.sre_request_r_reg ), .I4(\zq_cntrl.zq_request_logic.zq_request_r_reg ), .I5(D[0]), .O(\grant_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000A0808080A080)) \grant_r[1]_i_1 (.I0(\zq_cntrl.zq_request_logic.zq_request_r_reg ), .I1(\refresh_generation.refresh_bank_r_reg[0] ), .I2(init_calib_complete_reg_rep__6), .I3(\last_master_r_reg[2]_1 ), .I4(D[1]), .I5(\sr_cntrl.sre_request_logic.sre_request_r_reg ), .O(\grant_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0EAE000000000000)) \grant_r[2]_i_1 (.I0(\last_master_r_reg[2]_1 ), .I1(\refresh_generation.refresh_bank_r_reg[0] ), .I2(\zq_cntrl.zq_request_logic.zq_request_r_reg ), .I3(D[0]), .I4(init_calib_complete_reg_rep__6), .I5(\sr_cntrl.sre_request_logic.sre_request_r_reg ), .O(\grant_r[2]_i_1_n_0 )); FDRE \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1_n_0 ), .Q(Q[1]), .R(1'b0)); FDRE \grant_r_reg[2] (.C(CLK), .CE(1'b1), .D(\grant_r[2]_i_1_n_0 ), .Q(Q[2]), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFB08)) \last_master_r[2]_i_1 (.I0(Q[2]), .I1(\maintenance_request.upd_last_master_r_reg_0 ), .I2(\maintenance_request.new_maint_rank_r_reg ), .I3(\last_master_r_reg[2]_0 [2]), .I4(rstdiv0_sync_r1_reg_rep__21), .O(\last_master_r[2]_i_1_n_0 )); FDRE \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(\last_master_r_reg[2]_0 [0]), .R(1'b0)); FDRE \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(\last_master_r_reg[2]_0 [1]), .R(1'b0)); FDRE \last_master_r_reg[2] (.C(CLK), .CE(1'b1), .D(\last_master_r[2]_i_1_n_0 ), .Q(\last_master_r_reg[2]_0 [2]), .R(1'b0)); LUT6 #( .INIT(64'hB8B8B8B8B8B8B888)) \maintenance_request.maint_sre_r_lcl_i_1 (.I0(Q[2]), .I1(\maintenance_request.upd_last_master_r_reg ), .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ), .I3(ckesr_timer_r[0]), .I4(ckesr_timer_r[1]), .I5(app_sr_req), .O(\maintenance_request.maint_sre_r_lcl_reg )); LUT6 #( .INIT(64'h000000FFA2A2A2A2)) \maintenance_request.maint_srx_r_lcl_i_1 (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ), .I1(\maintenance_request.upd_last_master_r_reg ), .I2(Q[2]), .I3(app_sr_req), .I4(inhbt_srx), .I5(\maintenance_request.maint_sre_r_lcl_reg_0 ), .O(\maintenance_request.maint_srx_r_lcl_reg )); LUT4 #( .INIT(16'hBA8A)) \maintenance_request.maint_zq_r_lcl_i_1 (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ), .I1(\maintenance_request.new_maint_rank_r_reg ), .I2(\maintenance_request.upd_last_master_r_reg_0 ), .I3(Q[1]), .O(\maintenance_request.maint_zq_r_lcl_reg )); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized1 (D, \last_master_r_reg[3]_0 , Q, mc_we_n_ns, \cmd_pipe_plus.mc_bank_reg[8] , \cmd_pipe_plus.mc_address_reg[44] , \last_master_r_reg[3]_1 , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, ras_timer_zero_r_reg_1, auto_pre_r_lcl_reg_1, ras_timer_zero_r_reg_2, auto_pre_r_lcl_reg_2, rstdiv0_sync_r1_reg_rep__21, \pre_4_1_1T_arb.granted_pre_r_reg , act_wait_r_lcl_reg, act_wait_r_lcl_reg_0, act_wait_r_lcl_reg_1, row_cmd_wr, rstdiv0_sync_r1_reg_rep__22, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , \grant_r_reg[0]_0 , req_row_r, \grant_r_reg[0]_1 , \grant_r_reg[0]_2 , \grant_r_reg[0]_3 , \grant_r_reg[0]_4 , \grant_r_reg[0]_5 , \grant_r_reg[0]_6 , \grant_r_reg[0]_7 , \grant_r_reg[0]_8 , \grant_r_reg[0]_9 , \grant_r_reg[0]_10 , \grant_r_reg[0]_11 , \grant_r_reg[0]_12 , \grant_r_reg[0]_13 , \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[1] , CLK); output [1:0]D; output [0:0]\last_master_r_reg[3]_0 ; output [3:0]Q; output [0:0]mc_we_n_ns; output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; output [13:0]\cmd_pipe_plus.mc_address_reg[44] ; input \last_master_r_reg[3]_1 ; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input ras_timer_zero_r_reg; input ras_timer_zero_r_reg_0; input ras_timer_zero_r_reg_1; input auto_pre_r_lcl_reg_1; input ras_timer_zero_r_reg_2; input auto_pre_r_lcl_reg_2; input rstdiv0_sync_r1_reg_rep__21; input \pre_4_1_1T_arb.granted_pre_r_reg ; input act_wait_r_lcl_reg; input act_wait_r_lcl_reg_0; input act_wait_r_lcl_reg_1; input [0:0]row_cmd_wr; input rstdiv0_sync_r1_reg_rep__22; input \req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input \grant_r_reg[0]_0 ; input [27:0]req_row_r; input \grant_r_reg[0]_1 ; input \grant_r_reg[0]_2 ; input \grant_r_reg[0]_3 ; input \grant_r_reg[0]_4 ; input \grant_r_reg[0]_5 ; input \grant_r_reg[0]_6 ; input \grant_r_reg[0]_7 ; input \grant_r_reg[0]_8 ; input \grant_r_reg[0]_9 ; input \grant_r_reg[0]_10 ; input \grant_r_reg[0]_11 ; input \grant_r_reg[0]_12 ; input \grant_r_reg[0]_13 ; input \req_bank_r_lcl_reg[0] ; input \req_bank_r_lcl_reg[1] ; input CLK; wire CLK; wire [1:0]D; wire [3:0]Q; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire [13:0]\cmd_pipe_plus.mc_address_reg[44] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ; wire \cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ; wire \grant_r[0]_i_1__2_n_0 ; wire \grant_r[1]_i_1__2_n_0 ; wire \grant_r[1]_i_2__1_n_0 ; wire \grant_r[2]_i_1__2_n_0 ; wire \grant_r[3]_i_1__1_n_0 ; wire \grant_r[3]_i_2__1_n_0 ; wire \grant_r_reg[0]_0 ; wire \grant_r_reg[0]_1 ; wire \grant_r_reg[0]_10 ; wire \grant_r_reg[0]_11 ; wire \grant_r_reg[0]_12 ; wire \grant_r_reg[0]_13 ; wire \grant_r_reg[0]_2 ; wire \grant_r_reg[0]_3 ; wire \grant_r_reg[0]_4 ; wire \grant_r_reg[0]_5 ; wire \grant_r_reg[0]_6 ; wire \grant_r_reg[0]_7 ; wire \grant_r_reg[0]_8 ; wire \grant_r_reg[0]_9 ; wire [2:0]last_master_r; wire \last_master_r[1]_i_1__1_n_0 ; wire \last_master_r[3]_i_1__1_n_0 ; wire [0:0]\last_master_r_reg[3]_0 ; wire \last_master_r_reg[3]_1 ; wire [0:0]mc_we_n_ns; wire \pre_4_1_1T_arb.granted_pre_r_reg ; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire ras_timer_zero_r_reg_1; wire ras_timer_zero_r_reg_2; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[1] ; wire \req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [27:0]req_row_r; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[30]_i_1 (.I0(\grant_r_reg[0]_0 ), .I1(Q[3]), .I2(req_row_r[14]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[0]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [0])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[31]_i_1 (.I0(\grant_r_reg[0]_1 ), .I1(Q[3]), .I2(req_row_r[15]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[1]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [1])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[32]_i_1 (.I0(\grant_r_reg[0]_2 ), .I1(Q[3]), .I2(req_row_r[16]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[2]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [2])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[33]_i_1 (.I0(\grant_r_reg[0]_3 ), .I1(Q[3]), .I2(req_row_r[17]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[3]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [3])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[34]_i_1 (.I0(\grant_r_reg[0]_4 ), .I1(Q[3]), .I2(req_row_r[18]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[4]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [4])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[35]_i_1 (.I0(\grant_r_reg[0]_5 ), .I1(Q[3]), .I2(req_row_r[19]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[5]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [5])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[36]_i_1 (.I0(\grant_r_reg[0]_6 ), .I1(Q[3]), .I2(req_row_r[20]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[6]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [6])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[37]_i_1 (.I0(\grant_r_reg[0]_7 ), .I1(Q[3]), .I2(req_row_r[21]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[7]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [7])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[38]_i_1 (.I0(\grant_r_reg[0]_8 ), .I1(Q[3]), .I2(req_row_r[22]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[8]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [8])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[39]_i_1 (.I0(\grant_r_reg[0]_9 ), .I1(Q[3]), .I2(req_row_r[23]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[9]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [9])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[41]_i_1 (.I0(\grant_r_reg[0]_10 ), .I1(Q[3]), .I2(req_row_r[24]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[10]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [10])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[42]_i_1 (.I0(\grant_r_reg[0]_11 ), .I1(Q[3]), .I2(req_row_r[25]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[11]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [11])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[43]_i_1 (.I0(\grant_r_reg[0]_12 ), .I1(Q[3]), .I2(req_row_r[26]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[12]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [12])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_address[44]_i_1 (.I0(\grant_r_reg[0]_13 ), .I1(Q[3]), .I2(req_row_r[27]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(req_row_r[13]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_address_reg[44] [13])); LUT6 #( .INIT(64'hEFFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_bank[6]_i_1 (.I0(\req_bank_r_lcl_reg[0] ), .I1(\req_bank_r_lcl_reg[2]_0 [0]), .I2(Q[3]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(\req_bank_r_lcl_reg[2]_1 [0]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_bank_reg[8] [0])); LUT6 #( .INIT(64'hEFFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_bank[7]_i_1 (.I0(\req_bank_r_lcl_reg[1] ), .I1(\req_bank_r_lcl_reg[2]_0 [1]), .I2(Q[3]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(\req_bank_r_lcl_reg[2]_1 [1]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_bank_reg[8] [1])); LUT6 #( .INIT(64'hEFFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_bank[8]_i_1 (.I0(\req_bank_r_lcl_reg[2] ), .I1(\req_bank_r_lcl_reg[2]_0 [2]), .I2(Q[3]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(\req_bank_r_lcl_reg[2]_1 [2]), .I5(Q[2]), .O(\cmd_pipe_plus.mc_bank_reg[8] [2])); LUT6 #( .INIT(64'hFBFFEAFFEAFFEAFF)) \cmd_pipe_plus.mc_we_n[2]_i_1 (.I0(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ), .I1(Q[3]), .I2(act_wait_r_lcl_reg), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(act_wait_r_lcl_reg_0), .I5(Q[2]), .O(mc_we_n_ns)); LUT6 #( .INIT(64'h1111100000001000)) \cmd_pipe_plus.mc_we_n[2]_i_2 (.I0(Q[3]), .I1(Q[2]), .I2(Q[0]), .I3(act_wait_r_lcl_reg_1), .I4(Q[1]), .I5(row_cmd_wr), .O(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 )); LUT6 #( .INIT(64'h00F10000F0F10000)) \grant_r[0]_i_1__2 (.I0(\last_master_r[1]_i_1__1_n_0 ), .I1(ras_timer_zero_r_reg), .I2(ras_timer_zero_r_reg_0), .I3(D[0]), .I4(auto_pre_r_lcl_reg), .I5(auto_pre_r_lcl_reg_0), .O(\grant_r[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0020AAAA00000000)) \grant_r[1]_i_1__2 (.I0(\grant_r[1]_i_2__1_n_0 ), .I1(D[1]), .I2(\last_master_r_reg[3]_1 ), .I3(\last_master_r[1]_i_1__1_n_0 ), .I4(auto_pre_r_lcl_reg), .I5(auto_pre_r_lcl_reg_0), .O(\grant_r[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hBBBBBBBBAAABBBAB)) \grant_r[1]_i_2__1 (.I0(ras_timer_zero_r_reg_0), .I1(ras_timer_zero_r_reg), .I2(last_master_r[1]), .I3(\pre_4_1_1T_arb.granted_pre_r_reg ), .I4(Q[1]), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\grant_r[1]_i_2__1_n_0 )); LUT6 #( .INIT(64'h00F00020F0F00020)) \grant_r[2]_i_1__2 (.I0(\last_master_r_reg[3]_1 ), .I1(ras_timer_zero_r_reg_1), .I2(auto_pre_r_lcl_reg_1), .I3(D[1]), .I4(ras_timer_zero_r_reg_2), .I5(auto_pre_r_lcl_reg_2), .O(\grant_r[2]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0020AAAA00000000)) \grant_r[3]_i_1__1 (.I0(\grant_r[3]_i_2__1_n_0 ), .I1(D[0]), .I2(\last_master_r_reg[3]_1 ), .I3(\last_master_r[1]_i_1__1_n_0 ), .I4(auto_pre_r_lcl_reg_1), .I5(auto_pre_r_lcl_reg_2), .O(\grant_r[3]_i_1__1_n_0 )); LUT6 #( .INIT(64'hAAAAAAABABABAAAB)) \grant_r[3]_i_2__1 (.I0(ras_timer_zero_r_reg_2), .I1(ras_timer_zero_r_reg_1), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(\last_master_r_reg[3]_0 ), .I4(\pre_4_1_1T_arb.granted_pre_r_reg ), .I5(Q[3]), .O(\grant_r[3]_i_2__1_n_0 )); FDRE \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1__2_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1__2_n_0 ), .Q(Q[1]), .R(1'b0)); FDRE \grant_r_reg[2] (.C(CLK), .CE(1'b1), .D(\grant_r[2]_i_1__2_n_0 ), .Q(Q[2]), .R(1'b0)); FDRE \grant_r_reg[3] (.C(CLK), .CE(1'b1), .D(\grant_r[3]_i_1__1_n_0 ), .Q(Q[3]), .R(1'b0)); LUT4 #( .INIT(16'h00E2)) \last_master_r[0]_i_1__1 (.I0(last_master_r[0]), .I1(\pre_4_1_1T_arb.granted_pre_r_reg ), .I2(Q[0]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(D[0])); LUT4 #( .INIT(16'h00E2)) \last_master_r[1]_i_1__1 (.I0(last_master_r[1]), .I1(\pre_4_1_1T_arb.granted_pre_r_reg ), .I2(Q[1]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[1]_i_1__1_n_0 )); LUT4 #( .INIT(16'h00E2)) \last_master_r[2]_i_1__2 (.I0(last_master_r[2]), .I1(\pre_4_1_1T_arb.granted_pre_r_reg ), .I2(Q[2]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(D[1])); LUT4 #( .INIT(16'hFFB8)) \last_master_r[3]_i_1__1 (.I0(Q[3]), .I1(\pre_4_1_1T_arb.granted_pre_r_reg ), .I2(\last_master_r_reg[3]_0 ), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[3]_i_1__1_n_0 )); FDRE \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(D[0]), .Q(last_master_r[0]), .R(1'b0)); FDRE \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(\last_master_r[1]_i_1__1_n_0 ), .Q(last_master_r[1]), .R(1'b0)); FDRE \last_master_r_reg[2] (.C(CLK), .CE(1'b1), .D(D[1]), .Q(last_master_r[2]), .R(1'b0)); FDRE \last_master_r_reg[3] (.C(CLK), .CE(1'b1), .D(\last_master_r[3]_i_1__1_n_0 ), .Q(\last_master_r_reg[3]_0 ), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized2 (mc_we_n_ns, Q, mc_cas_n_ns, mc_ras_n_ns, \cmd_pipe_plus.mc_bank_reg[2] , \cmd_pipe_plus.mc_bank_reg[1] , \cmd_pipe_plus.mc_address_reg[14] , \grant_r_reg[2]_0 , \grant_r_reg[3]_0 , \grant_r_reg[3]_1 , \grant_r_reg[1]_0 , \last_master_r_reg[3]_0 , act_this_rank, \inhbt_act_faw.inhbt_act_faw_r_reg , row_cmd_wr, insert_maint_r1_lcl_reg, rstdiv0_sync_r1_reg_rep__21, maint_zq_r, act_wait_r_lcl_reg, granted_row_r_reg, maint_srx_r, granted_row_r_reg_0, \req_bank_r_lcl_reg[2] , granted_row_r_reg_1, \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , \req_bank_r_lcl_reg[2]_2 , \req_row_r_lcl_reg[14] , req_row_r, act_wait_r_lcl_reg_0, act_wait_r_lcl_reg_1, act_wait_r_lcl_reg_2, ras_timer_zero_r_reg, ras_timer_zero_r_reg_0, ras_timer_zero_r_reg_1, \last_master_r_reg[3]_1 , ras_timer_zero_r_reg_2, ras_timer_zero_r_reg_3, \generate_maint_cmds.insert_maint_r_lcl_reg , inhbt_act_faw_r, rstdiv0_sync_r1_reg_rep__22, act_this_rank_r, CLK); output [0:0]mc_we_n_ns; output [3:0]Q; output [0:0]mc_cas_n_ns; output [0:0]mc_ras_n_ns; output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; output \cmd_pipe_plus.mc_bank_reg[1] ; output [14:0]\cmd_pipe_plus.mc_address_reg[14] ; output \grant_r_reg[2]_0 ; output \grant_r_reg[3]_0 ; output \grant_r_reg[3]_1 ; output \grant_r_reg[1]_0 ; output [0:0]\last_master_r_reg[3]_0 ; output act_this_rank; output \inhbt_act_faw.inhbt_act_faw_r_reg ; input [0:0]row_cmd_wr; input insert_maint_r1_lcl_reg; input rstdiv0_sync_r1_reg_rep__21; input maint_zq_r; input act_wait_r_lcl_reg; input granted_row_r_reg; input maint_srx_r; input granted_row_r_reg_0; input [2:0]\req_bank_r_lcl_reg[2] ; input granted_row_r_reg_1; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input [2:0]\req_bank_r_lcl_reg[2]_2 ; input [27:0]\req_row_r_lcl_reg[14] ; input [29:0]req_row_r; input act_wait_r_lcl_reg_0; input act_wait_r_lcl_reg_1; input act_wait_r_lcl_reg_2; input ras_timer_zero_r_reg; input ras_timer_zero_r_reg_0; input ras_timer_zero_r_reg_1; input \last_master_r_reg[3]_1 ; input ras_timer_zero_r_reg_2; input ras_timer_zero_r_reg_3; input \generate_maint_cmds.insert_maint_r_lcl_reg ; input inhbt_act_faw_r; input rstdiv0_sync_r1_reg_rep__22; input [3:0]act_this_rank_r; input CLK; wire CLK; wire [3:0]Q; wire act_this_rank; wire [3:0]act_this_rank_r; wire act_wait_r_lcl_reg; wire act_wait_r_lcl_reg_0; wire act_wait_r_lcl_reg_1; wire act_wait_r_lcl_reg_2; wire \cmd_pipe_plus.mc_address[0]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[10]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[11]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[12]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[13]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[14]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[1]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[2]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[3]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[4]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[5]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[6]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[7]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[8]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[9]_i_2_n_0 ; wire [14:0]\cmd_pipe_plus.mc_address_reg[14] ; wire \cmd_pipe_plus.mc_bank[0]_i_2_n_0 ; wire \cmd_pipe_plus.mc_bank[1]_i_2_n_0 ; wire \cmd_pipe_plus.mc_bank[2]_i_2_n_0 ; wire \cmd_pipe_plus.mc_bank_reg[1] ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ; wire \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ; wire \cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ; wire \cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ; wire \generate_maint_cmds.insert_maint_r_lcl_reg ; wire \grant_r[0]_i_1__1_n_0 ; wire \grant_r[1]_i_1__1_n_0 ; wire \grant_r[1]_i_3__0_n_0 ; wire \grant_r[2]_i_1__1_n_0 ; wire \grant_r[2]_i_2__1_n_0 ; wire \grant_r[2]_i_3_n_0 ; wire \grant_r[3]_i_1__0_n_0 ; wire \grant_r[3]_i_4__1_n_0 ; wire \grant_r[3]_i_5__0_n_0 ; wire \grant_r[3]_i_6__0_n_0 ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[2]_0 ; wire \grant_r_reg[3]_0 ; wire \grant_r_reg[3]_1 ; wire granted_row_r_reg; wire granted_row_r_reg_0; wire granted_row_r_reg_1; wire i___73_i_2_n_0; wire i___74_i_2_n_0; wire i___83_i_2_n_0; wire \inhbt_act_faw.inhbt_act_faw_r_reg ; wire inhbt_act_faw_r; wire insert_maint_r1_lcl_reg; wire [2:0]last_master_r; wire \last_master_r[0]_i_1__0_n_0 ; wire \last_master_r[1]_i_1__0_n_0 ; wire \last_master_r[2]_i_1__1_n_0 ; wire \last_master_r[3]_i_1__0_n_0 ; wire [0:0]\last_master_r_reg[3]_0 ; wire \last_master_r_reg[3]_1 ; wire maint_srx_r; wire maint_zq_r; wire [0:0]mc_cas_n_ns; wire [0:0]mc_ras_n_ns; wire [0:0]mc_we_n_ns; wire ras_timer_zero_r_reg; wire ras_timer_zero_r_reg_0; wire ras_timer_zero_r_reg_1; wire ras_timer_zero_r_reg_2; wire ras_timer_zero_r_reg_3; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [2:0]\req_bank_r_lcl_reg[2]_2 ; wire [29:0]req_row_r; wire [27:0]\req_row_r_lcl_reg[14] ; wire [0:0]row_cmd_wr; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[0]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [0]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [0])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[0]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [14]), .I2(req_row_r[1]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[16]), .O(\cmd_pipe_plus.mc_address[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFF800000FF80FF80)) \cmd_pipe_plus.mc_address[10]_i_1 (.I0(req_row_r[0]), .I1(Q[0]), .I2(act_wait_r_lcl_reg), .I3(granted_row_r_reg), .I4(\cmd_pipe_plus.mc_address[10]_i_2_n_0 ), .I5(act_wait_r_lcl_reg_0), .O(\cmd_pipe_plus.mc_address_reg[14] [10])); LUT5 #( .INIT(32'h0800FFFF)) \cmd_pipe_plus.mc_address[10]_i_2 (.I0(act_wait_r_lcl_reg_1), .I1(Q[2]), .I2(Q[3]), .I3(req_row_r[11]), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address[10]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[11]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [10]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [11])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[11]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [24]), .I2(req_row_r[12]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[26]), .O(\cmd_pipe_plus.mc_address[11]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[12]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [11]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [12])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[12]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [25]), .I2(req_row_r[13]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[27]), .O(\cmd_pipe_plus.mc_address[12]_i_2_n_0 )); LUT6 #( .INIT(64'hF800F8F8F800F800)) \cmd_pipe_plus.mc_address[13]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [12]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ), .I4(\cmd_pipe_plus.mc_bank_reg[1] ), .I5(\req_row_r_lcl_reg[14] [26]), .O(\cmd_pipe_plus.mc_address_reg[14] [13])); LUT5 #( .INIT(32'hF808FFFF)) \cmd_pipe_plus.mc_address[13]_i_2 (.I0(req_row_r[14]), .I1(Q[2]), .I2(Q[3]), .I3(req_row_r[28]), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address[13]_i_2_n_0 )); LUT6 #( .INIT(64'hF800F8F8F800F800)) \cmd_pipe_plus.mc_address[14]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [13]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ), .I4(\cmd_pipe_plus.mc_bank_reg[1] ), .I5(\req_row_r_lcl_reg[14] [27]), .O(\cmd_pipe_plus.mc_address_reg[14] [14])); LUT5 #( .INIT(32'hF808FFFF)) \cmd_pipe_plus.mc_address[14]_i_2 (.I0(req_row_r[15]), .I1(Q[2]), .I2(Q[3]), .I3(req_row_r[29]), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address[14]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1048" *) LUT3 #( .INIT(8'hFB)) \cmd_pipe_plus.mc_address[14]_i_3 (.I0(Q[3]), .I1(Q[1]), .I2(Q[2]), .O(\cmd_pipe_plus.mc_bank_reg[1] )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[1]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [1]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [1])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[1]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [15]), .I2(req_row_r[2]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[17]), .O(\cmd_pipe_plus.mc_address[1]_i_2_n_0 )); LUT6 #( .INIT(64'hF800F8F8F800F800)) \cmd_pipe_plus.mc_address[2]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [2]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ), .I4(\cmd_pipe_plus.mc_bank_reg[1] ), .I5(\req_row_r_lcl_reg[14] [16]), .O(\cmd_pipe_plus.mc_address_reg[14] [2])); LUT5 #( .INIT(32'hF808FFFF)) \cmd_pipe_plus.mc_address[2]_i_2 (.I0(req_row_r[3]), .I1(Q[2]), .I2(Q[3]), .I3(req_row_r[18]), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address[2]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[3]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [3]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [3])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[3]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [17]), .I2(req_row_r[4]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[19]), .O(\cmd_pipe_plus.mc_address[3]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[4]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [4]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [4])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[4]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [18]), .I2(req_row_r[5]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[20]), .O(\cmd_pipe_plus.mc_address[4]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[5]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [5]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [5])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[5]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [19]), .I2(req_row_r[6]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[21]), .O(\cmd_pipe_plus.mc_address[5]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[6]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [6]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [6])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[6]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [20]), .I2(req_row_r[7]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[22]), .O(\cmd_pipe_plus.mc_address[6]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[7]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [7]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [7])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[7]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [21]), .I2(req_row_r[8]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[23]), .O(\cmd_pipe_plus.mc_address[7]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[8]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [8]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [8])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[8]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [22]), .I2(req_row_r[9]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[24]), .O(\cmd_pipe_plus.mc_address[8]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_address[9]_i_1 (.I0(Q[0]), .I1(\req_row_r_lcl_reg[14] [9]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_address_reg[14] [9])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_address[9]_i_2 (.I0(Q[1]), .I1(\req_row_r_lcl_reg[14] [23]), .I2(req_row_r[10]), .I3(Q[2]), .I4(Q[3]), .I5(req_row_r[25]), .O(\cmd_pipe_plus.mc_address[9]_i_2_n_0 )); LUT5 #( .INIT(32'hF800F8F8)) \cmd_pipe_plus.mc_bank[0]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [0]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_bank_reg[2] [0])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_bank[0]_i_2 (.I0(Q[1]), .I1(\req_bank_r_lcl_reg[2]_0 [0]), .I2(\req_bank_r_lcl_reg[2]_1 [0]), .I3(Q[2]), .I4(Q[3]), .I5(\req_bank_r_lcl_reg[2]_2 [0]), .O(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 )); LUT6 #( .INIT(64'hF800F8F8F800F800)) \cmd_pipe_plus.mc_bank[1]_i_1 (.I0(Q[0]), .I1(\req_bank_r_lcl_reg[2] [1]), .I2(granted_row_r_reg), .I3(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ), .I4(\cmd_pipe_plus.mc_bank_reg[1] ), .I5(\req_bank_r_lcl_reg[2]_0 [1]), .O(\cmd_pipe_plus.mc_bank_reg[2] [1])); LUT5 #( .INIT(32'hF808FFFF)) \cmd_pipe_plus.mc_bank[1]_i_2 (.I0(\req_bank_r_lcl_reg[2]_1 [1]), .I1(Q[2]), .I2(Q[3]), .I3(\req_bank_r_lcl_reg[2]_2 [1]), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 )); LUT5 #( .INIT(32'hEA00EAEA)) \cmd_pipe_plus.mc_bank[2]_i_1 (.I0(granted_row_r_reg), .I1(Q[0]), .I2(\req_bank_r_lcl_reg[2] [2]), .I3(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ), .I4(granted_row_r_reg_1), .O(\cmd_pipe_plus.mc_bank_reg[2] [2])); LUT6 #( .INIT(64'hFFFFF0880000F088)) \cmd_pipe_plus.mc_bank[2]_i_2 (.I0(Q[1]), .I1(\req_bank_r_lcl_reg[2]_0 [2]), .I2(\req_bank_r_lcl_reg[2]_1 [2]), .I3(Q[2]), .I4(Q[3]), .I5(\req_bank_r_lcl_reg[2]_2 [2]), .O(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 )); LUT6 #( .INIT(64'hEFEFEEEEEFEEEEEE)) \cmd_pipe_plus.mc_cas_n[0]_i_1 (.I0(granted_row_r_reg), .I1(Q[0]), .I2(rstdiv0_sync_r1_reg_rep__21), .I3(maint_zq_r), .I4(insert_maint_r1_lcl_reg), .I5(maint_srx_r), .O(mc_cas_n_ns)); LUT6 #( .INIT(64'h000200020002FFFF)) \cmd_pipe_plus.mc_ras_n[0]_i_1 (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(insert_maint_r1_lcl_reg), .I5(granted_row_r_reg_0), .O(mc_ras_n_ns)); LUT5 #( .INIT(32'h11001000)) \cmd_pipe_plus.mc_ras_n[0]_i_2 (.I0(Q[0]), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(maint_zq_r), .I3(insert_maint_r1_lcl_reg), .I4(maint_srx_r), .O(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 )); LUT6 #( .INIT(64'hCCCCCCCCCCFCCCDD)) \cmd_pipe_plus.mc_we_n[0]_i_1 (.I0(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ), .I1(\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ), .I2(row_cmd_wr), .I3(Q[2]), .I4(Q[1]), .I5(Q[3]), .O(mc_we_n_ns)); LUT5 #( .INIT(32'h00FDFFFD)) \cmd_pipe_plus.mc_we_n[0]_i_2 (.I0(insert_maint_r1_lcl_reg), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(maint_zq_r), .I3(Q[0]), .I4(act_wait_r_lcl_reg), .O(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 )); LUT6 #( .INIT(64'hF088F088F088FFFF)) \cmd_pipe_plus.mc_we_n[0]_i_3 (.I0(Q[2]), .I1(act_wait_r_lcl_reg_1), .I2(act_wait_r_lcl_reg_2), .I3(Q[3]), .I4(insert_maint_r1_lcl_reg), .I5(granted_row_r_reg_0), .O(\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 )); LUT5 #( .INIT(32'h0000F100)) \grant_r[0]_i_1__1 (.I0(\grant_r[3]_i_5__0_n_0 ), .I1(ras_timer_zero_r_reg), .I2(\grant_r[3]_i_4__1_n_0 ), .I3(ras_timer_zero_r_reg_0), .I4(\grant_r[2]_i_3_n_0 ), .O(\grant_r[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000003000707)) \grant_r[1]_i_1__1 (.I0(ras_timer_zero_r_reg), .I1(\last_master_r[1]_i_1__0_n_0 ), .I2(\grant_r[1]_i_3__0_n_0 ), .I3(\grant_r[2]_i_2__1_n_0 ), .I4(ras_timer_zero_r_reg_0), .I5(\grant_r[2]_i_3_n_0 ), .O(\grant_r[1]_i_1__1_n_0 )); LUT5 #( .INIT(32'hFFFFFEEE)) \grant_r[1]_i_3__0 (.I0(ras_timer_zero_r_reg_2), .I1(Q[1]), .I2(Q[3]), .I3(act_wait_r_lcl_reg_2), .I4(\grant_r[3]_i_6__0_n_0 ), .O(\grant_r[1]_i_3__0_n_0 )); LUT5 #( .INIT(32'h40444040)) \grant_r[2]_i_1__1 (.I0(\grant_r[3]_i_5__0_n_0 ), .I1(ras_timer_zero_r_reg_1), .I2(\grant_r[2]_i_2__1_n_0 ), .I3(\grant_r[2]_i_3_n_0 ), .I4(\grant_r_reg[2]_0 ), .O(\grant_r[2]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0005000000050303)) \grant_r[2]_i_2__1 (.I0(Q[3]), .I1(\last_master_r_reg[3]_0 ), .I2(rstdiv0_sync_r1_reg_rep__22), .I3(Q[2]), .I4(granted_row_r_reg_0), .I5(last_master_r[2]), .O(\grant_r[2]_i_2__1_n_0 )); LUT5 #( .INIT(32'h00004540)) \grant_r[2]_i_3 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(Q[2]), .I2(granted_row_r_reg_0), .I3(last_master_r[2]), .I4(\grant_r_reg[3]_0 ), .O(\grant_r[2]_i_3_n_0 )); LUT6 #( .INIT(64'h000000000C000E0E)) \grant_r[3]_i_1__0 (.I0(\grant_r_reg[2]_0 ), .I1(\last_master_r_reg[3]_1 ), .I2(\grant_r_reg[3]_0 ), .I3(\grant_r[3]_i_4__1_n_0 ), .I4(ras_timer_zero_r_reg_1), .I5(\grant_r[3]_i_5__0_n_0 ), .O(\grant_r[3]_i_1__0_n_0 )); LUT2 #( .INIT(4'h2)) \grant_r[3]_i_2__0 (.I0(\grant_r[1]_i_3__0_n_0 ), .I1(ras_timer_zero_r_reg_0), .O(\grant_r_reg[2]_0 )); LUT5 #( .INIT(32'hFFFFFEEE)) \grant_r[3]_i_3__0 (.I0(\grant_r[3]_i_6__0_n_0 ), .I1(Q[3]), .I2(Q[1]), .I3(row_cmd_wr), .I4(ras_timer_zero_r_reg_3), .O(\grant_r_reg[3]_0 )); LUT6 #( .INIT(64'hF0F5F0F0F0F5F3F3)) \grant_r[3]_i_4__1 (.I0(Q[1]), .I1(last_master_r[1]), .I2(rstdiv0_sync_r1_reg_rep__22), .I3(Q[0]), .I4(granted_row_r_reg_0), .I5(last_master_r[0]), .O(\grant_r[3]_i_4__1_n_0 )); LUT5 #( .INIT(32'h00004540)) \grant_r[3]_i_5__0 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(Q[0]), .I2(granted_row_r_reg_0), .I3(last_master_r[0]), .I4(\grant_r[1]_i_3__0_n_0 ), .O(\grant_r[3]_i_5__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFF8FFF8FFF8)) \grant_r[3]_i_6__0 (.I0(Q[2]), .I1(act_wait_r_lcl_reg_1), .I2(\generate_maint_cmds.insert_maint_r_lcl_reg ), .I3(inhbt_act_faw_r), .I4(act_wait_r_lcl_reg), .I5(Q[0]), .O(\grant_r[3]_i_6__0_n_0 )); FDRE \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1__1_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1__1_n_0 ), .Q(Q[1]), .R(1'b0)); FDRE \grant_r_reg[2] (.C(CLK), .CE(1'b1), .D(\grant_r[2]_i_1__1_n_0 ), .Q(Q[2]), .R(1'b0)); FDRE \grant_r_reg[3] (.C(CLK), .CE(1'b1), .D(\grant_r[3]_i_1__0_n_0 ), .Q(Q[3]), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFF888)) i___73_i_1 (.I0(act_wait_r_lcl_reg_2), .I1(Q[3]), .I2(row_cmd_wr), .I3(Q[1]), .I4(i___73_i_2_n_0), .I5(Q[2]), .O(\grant_r_reg[3]_1 )); LUT4 #( .INIT(16'hFFF8)) i___73_i_2 (.I0(Q[0]), .I1(act_wait_r_lcl_reg), .I2(inhbt_act_faw_r), .I3(\generate_maint_cmds.insert_maint_r_lcl_reg ), .O(i___73_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEEE)) i___74_i_1 (.I0(i___74_i_2_n_0), .I1(Q[0]), .I2(Q[2]), .I3(act_wait_r_lcl_reg_1), .I4(\generate_maint_cmds.insert_maint_r_lcl_reg ), .I5(inhbt_act_faw_r), .O(\grant_r_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair1048" *) LUT4 #( .INIT(16'hF888)) i___74_i_2 (.I0(Q[1]), .I1(row_cmd_wr), .I2(Q[3]), .I3(act_wait_r_lcl_reg_2), .O(i___74_i_2_n_0)); LUT5 #( .INIT(32'h00000777)) i___83_i_1 (.I0(Q[2]), .I1(act_this_rank_r[2]), .I2(Q[1]), .I3(act_this_rank_r[1]), .I4(i___83_i_2_n_0), .O(\inhbt_act_faw.inhbt_act_faw_r_reg )); LUT4 #( .INIT(16'hF888)) i___83_i_2 (.I0(act_this_rank_r[0]), .I1(Q[0]), .I2(act_this_rank_r[3]), .I3(Q[3]), .O(i___83_i_2_n_0)); LUT1 #( .INIT(2'h1)) \inhbt_act_faw.SRLC32E0_i_1 (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ), .O(act_this_rank)); LUT4 #( .INIT(16'h00E2)) \last_master_r[0]_i_1__0 (.I0(last_master_r[0]), .I1(granted_row_r_reg_0), .I2(Q[0]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[0]_i_1__0_n_0 )); LUT4 #( .INIT(16'h00E2)) \last_master_r[1]_i_1__0 (.I0(last_master_r[1]), .I1(granted_row_r_reg_0), .I2(Q[1]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[1]_i_1__0_n_0 )); LUT4 #( .INIT(16'h00E2)) \last_master_r[2]_i_1__1 (.I0(last_master_r[2]), .I1(granted_row_r_reg_0), .I2(Q[2]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[2]_i_1__1_n_0 )); LUT4 #( .INIT(16'hFFB8)) \last_master_r[3]_i_1__0 (.I0(Q[3]), .I1(granted_row_r_reg_0), .I2(\last_master_r_reg[3]_0 ), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[3]_i_1__0_n_0 )); FDRE \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(\last_master_r[0]_i_1__0_n_0 ), .Q(last_master_r[0]), .R(1'b0)); FDRE \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(\last_master_r[1]_i_1__0_n_0 ), .Q(last_master_r[1]), .R(1'b0)); FDRE \last_master_r_reg[2] (.C(CLK), .CE(1'b1), .D(\last_master_r[2]_i_1__1_n_0 ), .Q(last_master_r[2]), .R(1'b0)); FDRE \last_master_r_reg[3] (.C(CLK), .CE(1'b1), .D(\last_master_r[3]_i_1__0_n_0 ), .Q(\last_master_r_reg[3]_0 ), .R(1'b0)); endmodule (* ORIG_REF_NAME = "mig_7series_v4_0_round_robin_arb" *) module ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized4 (\cmd_pipe_plus.mc_data_offset_1_reg[0] , \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 , \rtw_timer.rtw_cnt_r_reg[1] , Q, \periodic_rd_generation.periodic_rd_timer_r_reg[2] , read_this_rank, \grant_r_reg[3]_0 , E, col_rd_wr, DIC, \grant_r_reg[3]_1 , \grant_r_reg[1]_0 , \grant_r_reg[1]_1 , \grant_r_reg[2]_0 , col_data_buf_addr, \wtr_timer.wtr_cnt_r_reg[0] , \wtr_timer.wtr_cnt_r_reg[1] , \wtr_timer.wtr_cnt_r_reg[1]_0 , \cmd_pipe_plus.mc_address_reg[25] , \cmd_pipe_plus.mc_bank_reg[5] , demand_priority_r_reg, \cmd_pipe_plus.mc_we_n_reg[1] , granted_col_r_reg, rd_wr_r_lcl_reg, read_this_rank_r, rd_this_rank_r, rd_wr_r_lcl_reg_0, rd_wr_r_lcl_reg_1, rd_wr_r_lcl_reg_2, rd_wr_r_lcl_reg_3, rd_wr_r_lcl_reg_4, rstdiv0_sync_r1_reg_rep__21, rd_wr_r_lcl_reg_5, \rtw_timer.rtw_cnt_r_reg[1]_0 , rd_wr_r_lcl_reg_6, rd_wr_r_lcl_reg_7, req_periodic_rd_r, col_periodic_rd_r, col_rd_wr_r, rnk_config_valid_r_lcl_reg, ofs_rdy_r, \genblk3[1].rnk_config_strobe_r_reg , \genblk3[2].rnk_config_strobe_r_reg , rnk_config_strobe, ofs_rdy_r_3, ofs_rdy_r_4, ofs_rdy_r_5, rstdiv0_sync_r1_reg_rep__22, req_data_buf_addr_r, col_data_buf_addr_r, \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] , wr_this_rank_r, \req_col_r_reg[9] , \req_col_r_reg[9]_0 , \req_col_r_reg[9]_1 , \req_col_r_reg[9]_2 , auto_pre_r_lcl_reg, auto_pre_r_lcl_reg_0, auto_pre_r_lcl_reg_1, auto_pre_r_lcl_reg_2, \req_bank_r_lcl_reg[2] , \req_bank_r_lcl_reg[2]_0 , \req_bank_r_lcl_reg[2]_1 , \req_bank_r_lcl_reg[2]_2 , req_bank_rdy_r, CLK); output \cmd_pipe_plus.mc_data_offset_1_reg[0] ; output \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; output \rtw_timer.rtw_cnt_r_reg[1] ; output [3:0]Q; output \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; output read_this_rank; output \grant_r_reg[3]_0 ; output [0:0]E; output col_rd_wr; output [0:0]DIC; output \grant_r_reg[3]_1 ; output \grant_r_reg[1]_0 ; output \grant_r_reg[1]_1 ; output \grant_r_reg[2]_0 ; output [4:0]col_data_buf_addr; output \wtr_timer.wtr_cnt_r_reg[0] ; output \wtr_timer.wtr_cnt_r_reg[1] ; output \wtr_timer.wtr_cnt_r_reg[1]_0 ; output [7:0]\cmd_pipe_plus.mc_address_reg[25] ; output [2:0]\cmd_pipe_plus.mc_bank_reg[5] ; output demand_priority_r_reg; output \cmd_pipe_plus.mc_we_n_reg[1] ; input granted_col_r_reg; input rd_wr_r_lcl_reg; input read_this_rank_r; input [3:0]rd_this_rank_r; input rd_wr_r_lcl_reg_0; input rd_wr_r_lcl_reg_1; input rd_wr_r_lcl_reg_2; input rd_wr_r_lcl_reg_3; input rd_wr_r_lcl_reg_4; input rstdiv0_sync_r1_reg_rep__21; input rd_wr_r_lcl_reg_5; input [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; input rd_wr_r_lcl_reg_6; input rd_wr_r_lcl_reg_7; input [3:0]req_periodic_rd_r; input col_periodic_rd_r; input col_rd_wr_r; input rnk_config_valid_r_lcl_reg; input ofs_rdy_r; input \genblk3[1].rnk_config_strobe_r_reg ; input \genblk3[2].rnk_config_strobe_r_reg ; input rnk_config_strobe; input ofs_rdy_r_3; input ofs_rdy_r_4; input ofs_rdy_r_5; input rstdiv0_sync_r1_reg_rep__22; input [19:0]req_data_buf_addr_r; input [0:0]col_data_buf_addr_r; input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; input [3:0]wr_this_rank_r; input [6:0]\req_col_r_reg[9] ; input [6:0]\req_col_r_reg[9]_0 ; input [6:0]\req_col_r_reg[9]_1 ; input [6:0]\req_col_r_reg[9]_2 ; input auto_pre_r_lcl_reg; input auto_pre_r_lcl_reg_0; input auto_pre_r_lcl_reg_1; input auto_pre_r_lcl_reg_2; input [2:0]\req_bank_r_lcl_reg[2] ; input [2:0]\req_bank_r_lcl_reg[2]_0 ; input [2:0]\req_bank_r_lcl_reg[2]_1 ; input [2:0]\req_bank_r_lcl_reg[2]_2 ; input req_bank_rdy_r; input CLK; wire CLK; wire [0:0]DIC; wire [0:0]E; wire [3:0]Q; wire auto_pre_r_lcl_reg; wire auto_pre_r_lcl_reg_0; wire auto_pre_r_lcl_reg_1; wire auto_pre_r_lcl_reg_2; wire \cmd_pipe_plus.mc_address[18]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[19]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[20]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[21]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[22]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[23]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[24]_i_2_n_0 ; wire \cmd_pipe_plus.mc_address[25]_i_2_n_0 ; wire [7:0]\cmd_pipe_plus.mc_address_reg[25] ; wire \cmd_pipe_plus.mc_bank[3]_i_2_n_0 ; wire \cmd_pipe_plus.mc_bank[4]_i_2_n_0 ; wire \cmd_pipe_plus.mc_bank[5]_i_2_n_0 ; wire [2:0]\cmd_pipe_plus.mc_bank_reg[5] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ; wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ; wire \cmd_pipe_plus.mc_we_n_reg[1] ; wire [4:0]col_data_buf_addr; wire [0:0]col_data_buf_addr_r; wire \col_mux.col_data_buf_addr_r[4]_i_2_n_0 ; wire \col_mux.col_periodic_rd_r_i_2_n_0 ; wire col_periodic_rd_r; wire col_rd_wr; wire col_rd_wr_r; wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ; wire demand_priority_r_reg; wire \genblk3[1].rnk_config_strobe_r_reg ; wire \genblk3[2].rnk_config_strobe_r_reg ; wire \grant_r[0]_i_1__0_n_0 ; wire \grant_r[1]_i_1__0_n_0 ; wire \grant_r[2]_i_1__0_n_0 ; wire \grant_r[2]_i_2_n_0 ; wire \grant_r[2]_i_3__1_n_0 ; wire \grant_r[3]_i_12_n_0 ; wire \grant_r[3]_i_1_n_0 ; wire \grant_r[3]_i_4__0_n_0 ; wire \grant_r[3]_i_6_n_0 ; wire \grant_r_reg[1]_0 ; wire \grant_r_reg[1]_1 ; wire \grant_r_reg[2]_0 ; wire \grant_r_reg[3]_0 ; wire \grant_r_reg[3]_1 ; wire granted_col_r_reg; wire i___32_i_2_n_0; wire [3:0]last_master_r; wire \last_master_r[0]_i_1_n_0 ; wire \last_master_r[1]_i_1_n_0 ; wire \last_master_r[2]_i_1__0_n_0 ; wire \last_master_r[3]_i_1_n_0 ; wire ofs_rdy_r; wire ofs_rdy_r_3; wire ofs_rdy_r_4; wire ofs_rdy_r_5; wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ; wire \periodic_rd_generation.read_this_rank_r_i_2_n_0 ; wire [3:0]rd_this_rank_r; wire rd_wr_r_lcl_reg; wire rd_wr_r_lcl_reg_0; wire rd_wr_r_lcl_reg_1; wire rd_wr_r_lcl_reg_2; wire rd_wr_r_lcl_reg_3; wire rd_wr_r_lcl_reg_4; wire rd_wr_r_lcl_reg_5; wire rd_wr_r_lcl_reg_6; wire rd_wr_r_lcl_reg_7; wire \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0 ; wire \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0 ; wire \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0 ; wire \read_fifo.fifo_ram[0].RAM32M0_i_9_n_0 ; wire read_this_rank; wire read_this_rank_r; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [2:0]\req_bank_r_lcl_reg[2]_0 ; wire [2:0]\req_bank_r_lcl_reg[2]_1 ; wire [2:0]\req_bank_r_lcl_reg[2]_2 ; wire req_bank_rdy_r; wire [6:0]\req_col_r_reg[9] ; wire [6:0]\req_col_r_reg[9]_0 ; wire [6:0]\req_col_r_reg[9]_1 ; wire [6:0]\req_col_r_reg[9]_2 ; wire [19:0]req_data_buf_addr_r; wire [3:0]req_periodic_rd_r; wire rnk_config_strobe; wire rnk_config_valid_r_lcl_reg; wire rstdiv0_sync_r1_reg_rep__21; wire rstdiv0_sync_r1_reg_rep__22; wire \rtw_timer.rtw_cnt_r[1]_i_3_n_0 ; wire \rtw_timer.rtw_cnt_r_reg[1] ; wire [0:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ; wire [3:0]wr_this_rank_r; wire \wtr_timer.wtr_cnt_r_reg[0] ; wire \wtr_timer.wtr_cnt_r_reg[1] ; wire \wtr_timer.wtr_cnt_r_reg[1]_0 ; (* SOFT_HLUTNM = "soft_lutpair1046" *) LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[18]_i_1 (.I0(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [0]), .O(\cmd_pipe_plus.mc_address_reg[25] [0])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[18]_i_2 (.I0(\req_col_r_reg[9]_0 [0]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [0]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [0]), .O(\cmd_pipe_plus.mc_address[18]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1047" *) LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[19]_i_1 (.I0(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [1]), .O(\cmd_pipe_plus.mc_address_reg[25] [1])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[19]_i_2 (.I0(\req_col_r_reg[9]_0 [1]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [1]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [1]), .O(\cmd_pipe_plus.mc_address[19]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[20]_i_1 (.I0(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [2]), .O(\cmd_pipe_plus.mc_address_reg[25] [2])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[20]_i_2 (.I0(\req_col_r_reg[9]_0 [2]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [2]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [2]), .O(\cmd_pipe_plus.mc_address[20]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[21]_i_1 (.I0(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [3]), .O(\cmd_pipe_plus.mc_address_reg[25] [3])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[21]_i_2 (.I0(\req_col_r_reg[9]_0 [3]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [3]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [3]), .O(\cmd_pipe_plus.mc_address[21]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[22]_i_1 (.I0(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [4]), .O(\cmd_pipe_plus.mc_address_reg[25] [4])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[22]_i_2 (.I0(\req_col_r_reg[9]_0 [4]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [4]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [4]), .O(\cmd_pipe_plus.mc_address[22]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[23]_i_1 (.I0(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [5]), .O(\cmd_pipe_plus.mc_address_reg[25] [5])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[23]_i_2 (.I0(\req_col_r_reg[9]_0 [5]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [5]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [5]), .O(\cmd_pipe_plus.mc_address[23]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[24]_i_1 (.I0(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_col_r_reg[9] [6]), .O(\cmd_pipe_plus.mc_address_reg[25] [6])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[24]_i_2 (.I0(\req_col_r_reg[9]_0 [6]), .I1(Q[0]), .I2(\req_col_r_reg[9]_1 [6]), .I3(Q[1]), .I4(Q[2]), .I5(\req_col_r_reg[9]_2 [6]), .O(\cmd_pipe_plus.mc_address[24]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_address[25]_i_1 (.I0(\cmd_pipe_plus.mc_address[25]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(auto_pre_r_lcl_reg), .O(\cmd_pipe_plus.mc_address_reg[25] [7])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_address[25]_i_2 (.I0(auto_pre_r_lcl_reg_0), .I1(Q[0]), .I2(auto_pre_r_lcl_reg_1), .I3(Q[1]), .I4(Q[2]), .I5(auto_pre_r_lcl_reg_2), .O(\cmd_pipe_plus.mc_address[25]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_bank[3]_i_1 (.I0(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_bank_r_lcl_reg[2] [0]), .O(\cmd_pipe_plus.mc_bank_reg[5] [0])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_bank[3]_i_2 (.I0(\req_bank_r_lcl_reg[2]_0 [0]), .I1(Q[0]), .I2(\req_bank_r_lcl_reg[2]_1 [0]), .I3(Q[1]), .I4(Q[2]), .I5(\req_bank_r_lcl_reg[2]_2 [0]), .O(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_bank[4]_i_1 (.I0(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_bank_r_lcl_reg[2] [1]), .O(\cmd_pipe_plus.mc_bank_reg[5] [1])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_bank[4]_i_2 (.I0(\req_bank_r_lcl_reg[2]_0 [1]), .I1(Q[0]), .I2(\req_bank_r_lcl_reg[2]_1 [1]), .I3(Q[1]), .I4(Q[2]), .I5(\req_bank_r_lcl_reg[2]_2 [1]), .O(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 )); LUT4 #( .INIT(16'hF737)) \cmd_pipe_plus.mc_bank[5]_i_1 (.I0(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ), .I1(granted_col_r_reg), .I2(Q[3]), .I3(\req_bank_r_lcl_reg[2] [2]), .O(\cmd_pipe_plus.mc_bank_reg[5] [2])); LUT6 #( .INIT(64'h00000F77FFFF0F77)) \cmd_pipe_plus.mc_bank[5]_i_2 (.I0(\req_bank_r_lcl_reg[2]_0 [2]), .I1(Q[0]), .I2(\req_bank_r_lcl_reg[2]_1 [2]), .I3(Q[1]), .I4(Q[2]), .I5(\req_bank_r_lcl_reg[2]_2 [2]), .O(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1045" *) LUT2 #( .INIT(4'h2)) \cmd_pipe_plus.mc_cmd[1]_i_1 (.I0(granted_col_r_reg), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .O(E)); (* SOFT_HLUTNM = "soft_lutpair1047" *) LUT2 #( .INIT(4'hD)) \cmd_pipe_plus.mc_data_offset[5]_i_1 (.I0(granted_col_r_reg), .I1(\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .O(\cmd_pipe_plus.mc_data_offset_1_reg[0] )); LUT6 #( .INIT(64'h55555554FFFFFFFF)) \cmd_pipe_plus.mc_we_n[1]_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[0]), .I4(Q[1]), .I5(granted_col_r_reg), .O(\cmd_pipe_plus.mc_we_n_reg[1] )); LUT5 #( .INIT(32'hB8BBB888)) \col_mux.col_data_buf_addr_r[4]_i_1 (.I0(req_data_buf_addr_r[19]), .I1(Q[3]), .I2(req_data_buf_addr_r[14]), .I3(Q[2]), .I4(\col_mux.col_data_buf_addr_r[4]_i_2_n_0 ), .O(col_data_buf_addr[4])); LUT5 #( .INIT(32'hB8BBB888)) \col_mux.col_data_buf_addr_r[4]_i_2 (.I0(req_data_buf_addr_r[9]), .I1(Q[1]), .I2(req_data_buf_addr_r[4]), .I3(Q[0]), .I4(col_data_buf_addr_r), .O(\col_mux.col_data_buf_addr_r[4]_i_2_n_0 )); LUT5 #( .INIT(32'hFFCA00CA)) \col_mux.col_periodic_rd_r_i_1 (.I0(\col_mux.col_periodic_rd_r_i_2_n_0 ), .I1(req_periodic_rd_r[2]), .I2(Q[2]), .I3(Q[3]), .I4(req_periodic_rd_r[3]), .O(DIC)); LUT6 #( .INIT(64'hAAAAFF00AAAA3030)) \col_mux.col_periodic_rd_r_i_2 (.I0(req_periodic_rd_r[1]), .I1(rstdiv0_sync_r1_reg_rep__21), .I2(col_periodic_rd_r), .I3(req_periodic_rd_r[0]), .I4(Q[1]), .I5(Q[0]), .O(\col_mux.col_periodic_rd_r_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \col_mux.col_rd_wr_r_i_1 (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ), .O(col_rd_wr)); (* SOFT_HLUTNM = "soft_lutpair1046" *) LUT3 #( .INIT(8'hDF)) demand_priority_r_i_5__2 (.I0(req_bank_rdy_r), .I1(Q[3]), .I2(granted_col_r_reg), .O(demand_priority_r_reg)); LUT5 #( .INIT(32'h00000E00)) \grant_r[0]_i_1__0 (.I0(rd_wr_r_lcl_reg_0), .I1(\grant_r[3]_i_4__0_n_0 ), .I2(\grant_r[2]_i_2_n_0 ), .I3(rd_wr_r_lcl_reg_2), .I4(\grant_r[3]_i_6_n_0 ), .O(\grant_r[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000032323)) \grant_r[1]_i_1__0 (.I0(rd_wr_r_lcl_reg_0), .I1(rd_wr_r_lcl_reg_1), .I2(\last_master_r[1]_i_1_n_0 ), .I3(\grant_r[2]_i_3__1_n_0 ), .I4(rd_wr_r_lcl_reg_2), .I5(\grant_r[2]_i_2_n_0 ), .O(\grant_r[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \grant_r[1]_i_7 (.I0(rnk_config_valid_r_lcl_reg), .I1(Q[1]), .I2(ofs_rdy_r_3), .I3(\genblk3[1].rnk_config_strobe_r_reg ), .I4(\genblk3[2].rnk_config_strobe_r_reg ), .I5(rnk_config_strobe), .O(\grant_r_reg[1]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \grant_r[1]_i_8 (.I0(rnk_config_valid_r_lcl_reg), .I1(Q[0]), .I2(ofs_rdy_r_4), .I3(\genblk3[1].rnk_config_strobe_r_reg ), .I4(\genblk3[2].rnk_config_strobe_r_reg ), .I5(rnk_config_strobe), .O(\grant_r_reg[1]_1 )); LUT5 #( .INIT(32'h00044444)) \grant_r[2]_i_1__0 (.I0(\grant_r[3]_i_6_n_0 ), .I1(rd_wr_r_lcl_reg_3), .I2(rd_wr_r_lcl_reg_4), .I3(\grant_r[2]_i_2_n_0 ), .I4(\grant_r[2]_i_3__1_n_0 ), .O(\grant_r[2]_i_1__0_n_0 )); LUT5 #( .INIT(32'h00004540)) \grant_r[2]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(Q[2]), .I2(granted_col_r_reg), .I3(last_master_r[2]), .I4(rd_wr_r_lcl_reg_5), .O(\grant_r[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFAFFFACC)) \grant_r[2]_i_3__1 (.I0(Q[2]), .I1(last_master_r[2]), .I2(Q[3]), .I3(granted_col_r_reg), .I4(last_master_r[3]), .I5(rstdiv0_sync_r1_reg_rep__22), .O(\grant_r[2]_i_3__1_n_0 )); LUT6 #( .INIT(64'h0000000000001F15)) \grant_r[3]_i_1 (.I0(rd_wr_r_lcl_reg_3), .I1(rd_wr_r_lcl_reg_4), .I2(\last_master_r[3]_i_1_n_0 ), .I3(\grant_r[3]_i_4__0_n_0 ), .I4(rd_wr_r_lcl_reg_5), .I5(\grant_r[3]_i_6_n_0 ), .O(\grant_r[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1044" *) LUT4 #( .INIT(16'h0001)) \grant_r[3]_i_12 (.I0(Q[1]), .I1(Q[0]), .I2(Q[3]), .I3(Q[2]), .O(\grant_r[3]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \grant_r[3]_i_14 (.I0(rnk_config_valid_r_lcl_reg), .I1(Q[2]), .I2(ofs_rdy_r_5), .I3(\genblk3[1].rnk_config_strobe_r_reg ), .I4(\genblk3[2].rnk_config_strobe_r_reg ), .I5(rnk_config_strobe), .O(\grant_r_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \grant_r[3]_i_16 (.I0(rnk_config_valid_r_lcl_reg), .I1(Q[3]), .I2(ofs_rdy_r), .I3(\genblk3[1].rnk_config_strobe_r_reg ), .I4(\genblk3[2].rnk_config_strobe_r_reg ), .I5(rnk_config_strobe), .O(\grant_r_reg[3]_1 )); LUT6 #( .INIT(64'hF0F5F0F0F0F5F3F3)) \grant_r[3]_i_4__0 (.I0(Q[0]), .I1(last_master_r[0]), .I2(rstdiv0_sync_r1_reg_rep__22), .I3(Q[1]), .I4(granted_col_r_reg), .I5(last_master_r[1]), .O(\grant_r[3]_i_4__0_n_0 )); LUT5 #( .INIT(32'h00004540)) \grant_r[3]_i_6 (.I0(rstdiv0_sync_r1_reg_rep__21), .I1(Q[0]), .I2(granted_col_r_reg), .I3(last_master_r[0]), .I4(rd_wr_r_lcl_reg_1), .O(\grant_r[3]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFF0000FFFFFFAB)) \grant_r[3]_i_7 (.I0(rd_wr_r_lcl_reg), .I1(\rtw_timer.rtw_cnt_r[1]_i_3_n_0 ), .I2(i___32_i_2_n_0), .I3(\grant_r[3]_i_12_n_0 ), .I4(rstdiv0_sync_r1_reg_rep__21), .I5(\rtw_timer.rtw_cnt_r_reg[1]_0 ), .O(\grant_r_reg[3]_0 )); FDRE \grant_r_reg[0] (.C(CLK), .CE(1'b1), .D(\grant_r[0]_i_1__0_n_0 ), .Q(Q[0]), .R(1'b0)); FDRE \grant_r_reg[1] (.C(CLK), .CE(1'b1), .D(\grant_r[1]_i_1__0_n_0 ), .Q(Q[1]), .R(1'b0)); FDRE \grant_r_reg[2] (.C(CLK), .CE(1'b1), .D(\grant_r[2]_i_1__0_n_0 ), .Q(Q[2]), .R(1'b0)); FDRE \grant_r_reg[3] (.C(CLK), .CE(1'b1), .D(\grant_r[3]_i_1_n_0 ), .Q(Q[3]), .R(1'b0)); LUT6 #( .INIT(64'hAAAAA888A888A888)) i___30_i_1 (.I0(read_this_rank_r), .I1(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ), .I2(rd_this_rank_r[1]), .I3(Q[1]), .I4(rd_this_rank_r[2]), .I5(Q[2]), .O(\periodic_rd_generation.periodic_rd_timer_r_reg[2] )); LUT6 #( .INIT(64'hFFFFFFFF00155515)) i___32_i_1 (.I0(i___32_i_2_n_0), .I1(Q[0]), .I2(rd_wr_r_lcl_reg_6), .I3(Q[1]), .I4(rd_wr_r_lcl_reg_7), .I5(rd_wr_r_lcl_reg), .O(\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair1044" *) LUT5 #( .INIT(32'hEEEFEEEE)) i___32_i_2 (.I0(Q[3]), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(col_rd_wr_r), .O(i___32_i_2_n_0)); LUT4 #( .INIT(16'hF888)) i___86_i_1 (.I0(wr_this_rank_r[3]), .I1(Q[3]), .I2(wr_this_rank_r[1]), .I3(Q[1]), .O(\wtr_timer.wtr_cnt_r_reg[1]_0 )); LUT4 #( .INIT(16'hF888)) i___86_i_2 (.I0(wr_this_rank_r[0]), .I1(Q[0]), .I2(wr_this_rank_r[2]), .I3(Q[2]), .O(\wtr_timer.wtr_cnt_r_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1045" *) LUT4 #( .INIT(16'h00E2)) \last_master_r[0]_i_1 (.I0(last_master_r[0]), .I1(granted_col_r_reg), .I2(Q[0]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[0]_i_1_n_0 )); LUT4 #( .INIT(16'h00E2)) \last_master_r[1]_i_1 (.I0(last_master_r[1]), .I1(granted_col_r_reg), .I2(Q[1]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[1]_i_1_n_0 )); LUT4 #( .INIT(16'h00E2)) \last_master_r[2]_i_1__0 (.I0(last_master_r[2]), .I1(granted_col_r_reg), .I2(Q[2]), .I3(rstdiv0_sync_r1_reg_rep__22), .O(\last_master_r[2]_i_1__0_n_0 )); LUT4 #( .INIT(16'hFEAE)) \last_master_r[3]_i_1 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(last_master_r[3]), .I2(granted_col_r_reg), .I3(Q[3]), .O(\last_master_r[3]_i_1_n_0 )); FDRE \last_master_r_reg[0] (.C(CLK), .CE(1'b1), .D(\last_master_r[0]_i_1_n_0 ), .Q(last_master_r[0]), .R(1'b0)); FDRE \last_master_r_reg[1] (.C(CLK), .CE(1'b1), .D(\last_master_r[1]_i_1_n_0 ), .Q(last_master_r[1]), .R(1'b0)); FDRE \last_master_r_reg[2] (.C(CLK), .CE(1'b1), .D(\last_master_r[2]_i_1__0_n_0 ), .Q(last_master_r[2]), .R(1'b0)); FDRE \last_master_r_reg[3] (.C(CLK), .CE(1'b1), .D(\last_master_r[3]_i_1_n_0 ), .Q(last_master_r[3]), .R(1'b0)); LUT5 #( .INIT(32'hFFEAEAEA)) \periodic_rd_generation.read_this_rank_r_i_1 (.I0(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ), .I1(rd_this_rank_r[1]), .I2(Q[1]), .I3(rd_this_rank_r[2]), .I4(Q[2]), .O(read_this_rank)); LUT4 #( .INIT(16'hF888)) \periodic_rd_generation.read_this_rank_r_i_2 (.I0(rd_this_rank_r[0]), .I1(Q[0]), .I2(rd_this_rank_r[3]), .I3(Q[3]), .O(\periodic_rd_generation.read_this_rank_r_i_2_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_1 (.I0(req_data_buf_addr_r[18]), .I1(Q[3]), .I2(req_data_buf_addr_r[13]), .I3(Q[2]), .I4(\read_fifo.fifo_ram[0].RAM32M0_i_7_n_0 ), .O(col_data_buf_addr[3])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_10 (.I0(req_data_buf_addr_r[5]), .I1(Q[1]), .I2(req_data_buf_addr_r[0]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [0]), .O(\read_fifo.fifo_ram[0].RAM32M0_i_10_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_2 (.I0(req_data_buf_addr_r[17]), .I1(Q[3]), .I2(req_data_buf_addr_r[12]), .I3(Q[2]), .I4(\read_fifo.fifo_ram[0].RAM32M0_i_8_n_0 ), .O(col_data_buf_addr[2])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_3 (.I0(req_data_buf_addr_r[16]), .I1(Q[3]), .I2(req_data_buf_addr_r[11]), .I3(Q[2]), .I4(\read_fifo.fifo_ram[0].RAM32M0_i_9_n_0 ), .O(col_data_buf_addr[1])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_4 (.I0(req_data_buf_addr_r[15]), .I1(Q[3]), .I2(req_data_buf_addr_r[10]), .I3(Q[2]), .I4(\read_fifo.fifo_ram[0].RAM32M0_i_10_n_0 ), .O(col_data_buf_addr[0])); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_7 (.I0(req_data_buf_addr_r[8]), .I1(Q[1]), .I2(req_data_buf_addr_r[3]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [3]), .O(\read_fifo.fifo_ram[0].RAM32M0_i_7_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_8 (.I0(req_data_buf_addr_r[7]), .I1(Q[1]), .I2(req_data_buf_addr_r[2]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [2]), .O(\read_fifo.fifo_ram[0].RAM32M0_i_8_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \read_fifo.fifo_ram[0].RAM32M0_i_9 (.I0(req_data_buf_addr_r[6]), .I1(Q[1]), .I2(req_data_buf_addr_r[1]), .I3(Q[0]), .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [1]), .O(\read_fifo.fifo_ram[0].RAM32M0_i_9_n_0 )); LUT6 #( .INIT(64'hF0F0F0F0F0F0F1FF)) \rtw_timer.rtw_cnt_r[1]_i_2 (.I0(Q[0]), .I1(Q[1]), .I2(rd_wr_r_lcl_reg), .I3(\rtw_timer.rtw_cnt_r[1]_i_3_n_0 ), .I4(Q[2]), .I5(Q[3]), .O(\rtw_timer.rtw_cnt_r_reg[1] )); LUT4 #( .INIT(16'hF808)) \rtw_timer.rtw_cnt_r[1]_i_3 (.I0(Q[0]), .I1(rd_wr_r_lcl_reg_6), .I2(Q[1]), .I3(rd_wr_r_lcl_reg_7), .O(\rtw_timer.rtw_cnt_r[1]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFEEEFEEEFEEE)) \wtr_timer.wtr_cnt_r[0]_i_2 (.I0(rstdiv0_sync_r1_reg_rep__22), .I1(\wtr_timer.wtr_cnt_r_reg[1] ), .I2(wr_this_rank_r[3]), .I3(Q[3]), .I4(wr_this_rank_r[1]), .I5(Q[1]), .O(\wtr_timer.wtr_cnt_r_reg[0] )); endmodule module ddr3_if_mig_7series_v4_0_tempmon (out, D, mmcm_clk, in0, CLK); output [11:0]out; output [11:0]D; input mmcm_clk; input in0; input CLK; wire CLK; wire [11:0]D; wire \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ; wire \device_temp_101[11]_i_4_n_0 ; wire \device_temp_101[11]_i_5_n_0 ; wire \device_temp_101[11]_i_6_n_0 ; wire \device_temp_101[11]_i_7_n_0 ; wire \device_temp_101[11]_i_8_n_0 ; wire [11:0]device_temp_lcl; (* async_reg = "true" *) wire [11:0]device_temp_r; wire \device_temp_r[11]_i_1_n_0 ; (* async_reg = "true" *) wire [11:0]device_temp_sync_r1; (* async_reg = "true" *) wire [11:0]device_temp_sync_r2; (* async_reg = "true" *) (* syn_srlstyle = "registers" *) wire [11:0]device_temp_sync_r3; (* async_reg = "true" *) wire [11:0]device_temp_sync_r4; wire device_temp_sync_r4_neq_r3; wire device_temp_sync_r4_neq_r3_i_2_n_0; wire device_temp_sync_r4_neq_r3_i_3_n_0; wire device_temp_sync_r4_neq_r3_i_4_n_0; wire device_temp_sync_r4_neq_r3_i_5_n_0; wire device_temp_sync_r4_neq_r3_reg_i_1_n_0; wire device_temp_sync_r4_neq_r3_reg_i_1_n_1; wire device_temp_sync_r4_neq_r3_reg_i_1_n_2; wire device_temp_sync_r4_neq_r3_reg_i_1_n_3; (* async_reg = "true" *) wire [11:0]device_temp_sync_r5; wire in0; wire mmcm_clk; wire [11:0]p_0_in; wire [10:1]p_0_in__0; wire [1:0]p_0_in__1; (* async_reg = "true" *) wire rst_r1; (* async_reg = "true" *) wire rst_r2; wire sample_en; wire sample_en0; wire sample_timer0; wire sample_timer_en; wire sync_cntr0; wire \sync_cntr[2]_i_1_n_0 ; wire \sync_cntr[3]_i_2_n_0 ; wire \sync_cntr[3]_i_3_n_0 ; wire [3:0]sync_cntr_reg__0; (* RTL_KEEP = "yes" *) wire temperature; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ; wire \u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ; wire xadc_den; wire [15:0]xadc_do; wire xadc_drdy; wire xadc_drdy_r; wire \xadc_supplied_temperature.sample_en_i_2_n_0 ; wire \xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ; wire \xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ; wire \xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ; wire \xadc_supplied_temperature.sample_timer_en_i_1_n_0 ; wire [10:0]\xadc_supplied_temperature.sample_timer_reg__0 ; wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED; wire \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ; wire \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ; wire [7:0]\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ; wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ; wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ; assign out[11:0] = device_temp_r; LUT6 #( .INIT(64'hFFFFFEEEFEEEFEEE)) \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1 (.I0(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .I1(temperature), .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .I3(sample_en), .I4(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .I5(xadc_drdy_r), .O(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 )); (* KEEP = "yes" *) FDSE #( .INIT(1'b1)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(temperature), .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .S(rst_r2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .R(rst_r2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .R(rst_r2)); (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3] (.C(mmcm_clk), .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ), .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .Q(temperature), .R(rst_r2)); LUT3 #( .INIT(8'h10)) \device_temp_101[0]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[0]), .O(D[0])); LUT3 #( .INIT(8'hBA)) \device_temp_101[10]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[10]), .O(D[10])); LUT3 #( .INIT(8'hFE)) \device_temp_101[11]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[11]), .O(D[11])); LUT6 #( .INIT(64'h0000000011111115)) \device_temp_101[11]_i_2 (.I0(\device_temp_101[11]_i_4_n_0 ), .I1(device_temp_r[11]), .I2(device_temp_r[8]), .I3(device_temp_r[10]), .I4(device_temp_r[9]), .I5(\device_temp_101[11]_i_5_n_0 ), .O(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low )); LUT5 #( .INIT(32'h0000FD55)) \device_temp_101[11]_i_3 (.I0(\device_temp_101[11]_i_6_n_0 ), .I1(device_temp_r[1]), .I2(device_temp_r[0]), .I3(device_temp_r[2]), .I4(\device_temp_101[11]_i_7_n_0 ), .O(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high )); LUT4 #( .INIT(16'h8000)) \device_temp_101[11]_i_4 (.I0(device_temp_r[4]), .I1(device_temp_r[11]), .I2(device_temp_r[7]), .I3(device_temp_r[5]), .O(\device_temp_101[11]_i_4_n_0 )); LUT6 #( .INIT(64'hE000A000A000A000)) \device_temp_101[11]_i_5 (.I0(device_temp_r[6]), .I1(device_temp_r[5]), .I2(device_temp_r[7]), .I3(device_temp_r[11]), .I4(device_temp_r[2]), .I5(device_temp_r[3]), .O(\device_temp_101[11]_i_5_n_0 )); LUT5 #( .INIT(32'h00000001)) \device_temp_101[11]_i_6 (.I0(device_temp_r[6]), .I1(device_temp_r[9]), .I2(device_temp_r[8]), .I3(device_temp_r[4]), .I4(device_temp_r[3]), .O(\device_temp_101[11]_i_6_n_0 )); LUT6 #( .INIT(64'h7F777F777F77FF77)) \device_temp_101[11]_i_7 (.I0(device_temp_r[11]), .I1(device_temp_r[10]), .I2(device_temp_r[7]), .I3(\device_temp_101[11]_i_8_n_0 ), .I4(device_temp_r[6]), .I5(device_temp_r[5]), .O(\device_temp_101[11]_i_7_n_0 )); LUT2 #( .INIT(4'h1)) \device_temp_101[11]_i_8 (.I0(device_temp_r[9]), .I1(device_temp_r[8]), .O(\device_temp_101[11]_i_8_n_0 )); LUT3 #( .INIT(8'h10)) \device_temp_101[1]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[1]), .O(D[1])); LUT3 #( .INIT(8'hFE)) \device_temp_101[2]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[2]), .O(D[2])); LUT3 #( .INIT(8'hDC)) \device_temp_101[3]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[3]), .O(D[3])); LUT3 #( .INIT(8'h10)) \device_temp_101[4]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[4]), .O(D[4])); LUT3 #( .INIT(8'hFE)) \device_temp_101[5]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[5]), .O(D[5])); LUT3 #( .INIT(8'h10)) \device_temp_101[6]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[6]), .O(D[6])); LUT3 #( .INIT(8'hFE)) \device_temp_101[7]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I2(device_temp_r[7]), .O(D[7])); LUT3 #( .INIT(8'h10)) \device_temp_101[8]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[8]), .O(D[8])); LUT3 #( .INIT(8'h10)) \device_temp_101[9]_i_1 (.I0(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ), .I1(\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ), .I2(device_temp_r[9]), .O(D[9])); LUT4 #( .INIT(16'h8000)) \device_temp_r[11]_i_1 (.I0(sync_cntr_reg__0[3]), .I1(sync_cntr_reg__0[2]), .I2(sync_cntr_reg__0[0]), .I3(sync_cntr_reg__0[1]), .O(\device_temp_r[11]_i_1_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[0] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[0]), .Q(device_temp_r[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[10] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[10]), .Q(device_temp_r[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[11] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[11]), .Q(device_temp_r[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[1] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[1]), .Q(device_temp_r[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[2] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[2]), .Q(device_temp_r[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[3] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[3]), .Q(device_temp_r[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[4] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[4]), .Q(device_temp_r[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[5] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[5]), .Q(device_temp_r[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[6] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[6]), .Q(device_temp_r[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[7] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[7]), .Q(device_temp_r[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[8] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[8]), .Q(device_temp_r[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_r_reg[9] (.C(CLK), .CE(\device_temp_r[11]_i_1_n_0 ), .D(device_temp_sync_r5[9]), .Q(device_temp_r[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[0]), .Q(device_temp_sync_r1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[10]), .Q(device_temp_sync_r1[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[11]), .Q(device_temp_sync_r1[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[1]), .Q(device_temp_sync_r1[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[2]), .Q(device_temp_sync_r1[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[3]), .Q(device_temp_sync_r1[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[4]), .Q(device_temp_sync_r1[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[5]), .Q(device_temp_sync_r1[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[6]), .Q(device_temp_sync_r1[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[7]), .Q(device_temp_sync_r1[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[8]), .Q(device_temp_sync_r1[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r1_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_lcl[9]), .Q(device_temp_sync_r1[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[0]), .Q(device_temp_sync_r2[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[10]), .Q(device_temp_sync_r2[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[11]), .Q(device_temp_sync_r2[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[1]), .Q(device_temp_sync_r2[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[2]), .Q(device_temp_sync_r2[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[3]), .Q(device_temp_sync_r2[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[4]), .Q(device_temp_sync_r2[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[5]), .Q(device_temp_sync_r2[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[6]), .Q(device_temp_sync_r2[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[7]), .Q(device_temp_sync_r2[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[8]), .Q(device_temp_sync_r2[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r2_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r1[9]), .Q(device_temp_sync_r2[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[0]), .Q(device_temp_sync_r3[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[10]), .Q(device_temp_sync_r3[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[11]), .Q(device_temp_sync_r3[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[1]), .Q(device_temp_sync_r3[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[2]), .Q(device_temp_sync_r3[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[3]), .Q(device_temp_sync_r3[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[4]), .Q(device_temp_sync_r3[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[5]), .Q(device_temp_sync_r3[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[6]), .Q(device_temp_sync_r3[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[7]), .Q(device_temp_sync_r3[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[8]), .Q(device_temp_sync_r3[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* syn_srlstyle = "registers" *) FDRE \device_temp_sync_r3_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r2[9]), .Q(device_temp_sync_r3[9]), .R(1'b0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_2 (.I0(device_temp_sync_r4[9]), .I1(device_temp_sync_r3[9]), .I2(device_temp_sync_r3[11]), .I3(device_temp_sync_r4[11]), .I4(device_temp_sync_r3[10]), .I5(device_temp_sync_r4[10]), .O(device_temp_sync_r4_neq_r3_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_3 (.I0(device_temp_sync_r4[6]), .I1(device_temp_sync_r3[6]), .I2(device_temp_sync_r3[8]), .I3(device_temp_sync_r4[8]), .I4(device_temp_sync_r3[7]), .I5(device_temp_sync_r4[7]), .O(device_temp_sync_r4_neq_r3_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_4 (.I0(device_temp_sync_r4[3]), .I1(device_temp_sync_r3[3]), .I2(device_temp_sync_r3[5]), .I3(device_temp_sync_r4[5]), .I4(device_temp_sync_r3[4]), .I5(device_temp_sync_r4[4]), .O(device_temp_sync_r4_neq_r3_i_4_n_0)); LUT6 #( .INIT(64'h9009000000009009)) device_temp_sync_r4_neq_r3_i_5 (.I0(device_temp_sync_r4[0]), .I1(device_temp_sync_r3[0]), .I2(device_temp_sync_r3[2]), .I3(device_temp_sync_r4[2]), .I4(device_temp_sync_r3[1]), .I5(device_temp_sync_r4[1]), .O(device_temp_sync_r4_neq_r3_i_5_n_0)); FDRE device_temp_sync_r4_neq_r3_reg (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0), .Q(device_temp_sync_r4_neq_r3), .R(1'b0)); CARRY4 device_temp_sync_r4_neq_r3_reg_i_1 (.CI(1'b0), .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]), .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0})); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[0]), .Q(device_temp_sync_r4[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[10]), .Q(device_temp_sync_r4[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[11]), .Q(device_temp_sync_r4[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[1]), .Q(device_temp_sync_r4[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[2]), .Q(device_temp_sync_r4[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[3]), .Q(device_temp_sync_r4[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[4]), .Q(device_temp_sync_r4[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[5]), .Q(device_temp_sync_r4[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[6]), .Q(device_temp_sync_r4[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[7]), .Q(device_temp_sync_r4[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[8]), .Q(device_temp_sync_r4[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r4_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r3[9]), .Q(device_temp_sync_r4[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[0] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[0]), .Q(device_temp_sync_r5[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[10] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[10]), .Q(device_temp_sync_r5[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[11] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[11]), .Q(device_temp_sync_r5[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[1] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[1]), .Q(device_temp_sync_r5[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[2] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[2]), .Q(device_temp_sync_r5[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[3] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[3]), .Q(device_temp_sync_r5[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[4] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[4]), .Q(device_temp_sync_r5[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[5] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[5]), .Q(device_temp_sync_r5[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[6] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[6]), .Q(device_temp_sync_r5[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[7] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[7]), .Q(device_temp_sync_r5[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[8] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[8]), .Q(device_temp_sync_r5[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \device_temp_sync_r5_reg[9] (.C(CLK), .CE(1'b1), .D(device_temp_sync_r4[9]), .Q(device_temp_sync_r5[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT1 #( .INIT(2'h1)) \sync_cntr[0]_i_1 (.I0(sync_cntr_reg__0[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h6)) \sync_cntr[1]_i_1 (.I0(sync_cntr_reg__0[0]), .I1(sync_cntr_reg__0[1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'h78)) \sync_cntr[2]_i_1 (.I0(sync_cntr_reg__0[1]), .I1(sync_cntr_reg__0[0]), .I2(sync_cntr_reg__0[2]), .O(\sync_cntr[2]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \sync_cntr[3]_i_1 (.I0(in0), .I1(device_temp_sync_r4_neq_r3), .O(sync_cntr0)); LUT4 #( .INIT(16'h7FFF)) \sync_cntr[3]_i_2 (.I0(sync_cntr_reg__0[1]), .I1(sync_cntr_reg__0[0]), .I2(sync_cntr_reg__0[2]), .I3(sync_cntr_reg__0[3]), .O(\sync_cntr[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h7F80)) \sync_cntr[3]_i_3 (.I0(sync_cntr_reg__0[2]), .I1(sync_cntr_reg__0[0]), .I2(sync_cntr_reg__0[1]), .I3(sync_cntr_reg__0[3]), .O(\sync_cntr[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \sync_cntr_reg[0] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(p_0_in__1[0]), .Q(sync_cntr_reg__0[0]), .R(sync_cntr0)); FDRE #( .INIT(1'b0)) \sync_cntr_reg[1] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(p_0_in__1[1]), .Q(sync_cntr_reg__0[1]), .R(sync_cntr0)); FDRE #( .INIT(1'b0)) \sync_cntr_reg[2] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(\sync_cntr[2]_i_1_n_0 ), .Q(sync_cntr_reg__0[2]), .R(sync_cntr0)); FDRE #( .INIT(1'b0)) \sync_cntr_reg[3] (.C(CLK), .CE(\sync_cntr[3]_i_2_n_0 ), .D(\sync_cntr[3]_i_3_n_0 ), .Q(sync_cntr_reg__0[3]), .R(sync_cntr0)); (* BOX_TYPE = "PRIMITIVE" *) XADC #( .INIT_40(16'h1000), .INIT_41(16'h2FFF), .INIT_42(16'h0800), .INIT_43(16'h0000), .INIT_44(16'h0000), .INIT_45(16'h0000), .INIT_46(16'h0000), .INIT_47(16'h0000), .INIT_48(16'h0101), .INIT_49(16'h0000), .INIT_4A(16'h0100), .INIT_4B(16'h0000), .INIT_4C(16'h0000), .INIT_4D(16'h0000), .INIT_4E(16'h0000), .INIT_4F(16'h0000), .INIT_50(16'hB5ED), .INIT_51(16'h57E4), .INIT_52(16'hA147), .INIT_53(16'hCA33), .INIT_54(16'hA93A), .INIT_55(16'h52C6), .INIT_56(16'h9555), .INIT_57(16'hAE4E), .INIT_58(16'h5999), .INIT_59(16'h0000), .INIT_5A(16'h0000), .INIT_5B(16'h0000), .INIT_5C(16'h5111), .INIT_5D(16'h0000), .INIT_5E(16'h0000), .INIT_5F(16'h0000), .IS_CONVSTCLK_INVERTED(1'b0), .IS_DCLK_INVERTED(1'b0), .SIM_DEVICE("7SERIES"), .SIM_MONITOR_FILE("design.txt")) \xadc_supplied_temperature.XADC_inst (.ALM(\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]), .BUSY(\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ), .CHANNEL(\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]), .CONVST(1'b0), .CONVSTCLK(1'b0), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(mmcm_clk), .DEN(xadc_den), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(xadc_do), .DRDY(xadc_drdy), .DWE(1'b0), .EOC(\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ), .EOS(\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ), .JTAGBUSY(\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ), .JTAGLOCKED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ), .JTAGMODIFIED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ), .MUXADDR(\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]), .OT(\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ), .RESET(1'b0), .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .VN(1'b0), .VP(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \xadc_supplied_temperature.rst_r1_reg (.C(mmcm_clk), .CE(1'b1), .D(in0), .Q(rst_r1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE \xadc_supplied_temperature.rst_r2_reg (.C(mmcm_clk), .CE(1'b1), .D(rst_r1), .Q(rst_r2), .R(1'b0)); LUT6 #( .INIT(64'h0000020000000000)) \xadc_supplied_temperature.sample_en_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I5(\xadc_supplied_temperature.sample_en_i_2_n_0 ), .O(sample_en0)); LUT6 #( .INIT(64'h0080000000000000)) \xadc_supplied_temperature.sample_en_i_2 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [10]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .O(\xadc_supplied_temperature.sample_en_i_2_n_0 )); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_en_reg (.C(mmcm_clk), .CE(1'b1), .D(sample_en0), .Q(sample_en), .R(1'b0)); LUT1 #( .INIT(2'h1)) \xadc_supplied_temperature.sample_timer[0]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .O(\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \xadc_supplied_temperature.sample_timer[10]_i_1 (.I0(rst_r2), .I1(xadc_den), .O(sample_timer0)); LUT6 #( .INIT(64'hF7FFFFFF08000000)) \xadc_supplied_temperature.sample_timer[10]_i_2 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [10]), .O(p_0_in__0[10])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \xadc_supplied_temperature.sample_timer[10]_i_3 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .O(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \xadc_supplied_temperature.sample_timer[1]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h78)) \xadc_supplied_temperature.sample_timer[2]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h7F80)) \xadc_supplied_temperature.sample_timer[3]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'h7FFF8000)) \xadc_supplied_temperature.sample_timer[4]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \xadc_supplied_temperature.sample_timer[5]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .I5(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h9)) \xadc_supplied_temperature.sample_timer[6]_i_1 (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( .INIT(8'hD2)) \xadc_supplied_temperature.sample_timer[7]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'hDF20)) \xadc_supplied_temperature.sample_timer[8]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I2(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .O(p_0_in__0[8])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'hF7FF0800)) \xadc_supplied_temperature.sample_timer[9]_i_1 (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ), .I3(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .I4(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .O(p_0_in__0[9])); LUT4 #( .INIT(16'h000E)) \xadc_supplied_temperature.sample_timer_clr_i_1 (.I0(xadc_den), .I1(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ), .I3(rst_r2), .O(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 )); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_clr_reg (.C(mmcm_clk), .CE(1'b1), .D(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ), .Q(xadc_den), .R(1'b0)); LUT5 #( .INIT(32'h000000FE)) \xadc_supplied_temperature.sample_timer_en_i_1 (.I0(sample_timer_en), .I1(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ), .I2(temperature), .I3(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ), .I4(rst_r2), .O(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 )); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_en_reg (.C(mmcm_clk), .CE(1'b1), .D(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ), .Q(sample_timer_en), .R(1'b0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[0] (.C(mmcm_clk), .CE(sample_timer_en), .D(\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [0]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[10] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[10]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [10]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[1] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[1]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [1]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[2] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[2]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [2]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[3] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[3]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [3]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[4] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[4]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [4]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[5] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[5]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [5]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[6] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[6]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [6]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[7] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[7]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [7]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[8] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[8]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [8]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.sample_timer_reg[9] (.C(mmcm_clk), .CE(sample_timer_en), .D(p_0_in__0[9]), .Q(\xadc_supplied_temperature.sample_timer_reg__0 [9]), .R(sample_timer0)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[0] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[0]), .Q(device_temp_lcl[0]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[10] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[10]), .Q(device_temp_lcl[10]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[11] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[11]), .Q(device_temp_lcl[11]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[1] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[1]), .Q(device_temp_lcl[1]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[2] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[2]), .Q(device_temp_lcl[2]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[3] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[3]), .Q(device_temp_lcl[3]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[4] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[4]), .Q(device_temp_lcl[4]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[5] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[5]), .Q(device_temp_lcl[5]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[6] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[6]), .Q(device_temp_lcl[6]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[7] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[7]), .Q(device_temp_lcl[7]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[8] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[8]), .Q(device_temp_lcl[8]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.temperature_reg[9] (.C(mmcm_clk), .CE(temperature), .D(p_0_in[9]), .Q(device_temp_lcl[9]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[10] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[10]), .Q(p_0_in[6]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[11] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[11]), .Q(p_0_in[7]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[12] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[12]), .Q(p_0_in[8]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[13] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[13]), .Q(p_0_in[9]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[14] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[14]), .Q(p_0_in[10]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[15] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[15]), .Q(p_0_in[11]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[4] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[4]), .Q(p_0_in[0]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[5] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[5]), .Q(p_0_in[1]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[6] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[6]), .Q(p_0_in[2]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[7] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[7]), .Q(p_0_in[3]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[8] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[8]), .Q(p_0_in[4]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_do_r_reg[9] (.C(mmcm_clk), .CE(1'b1), .D(xadc_do[9]), .Q(p_0_in[5]), .R(rst_r2)); FDRE #( .INIT(1'b0)) \xadc_supplied_temperature.xadc_drdy_r_reg (.C(mmcm_clk), .CE(1'b1), .D(xadc_drdy), .Q(xadc_drdy_r), .R(rst_r2)); endmodule module ddr3_if_mig_7series_v4_0_ui_cmd (E, app_en_r1, app_hi_pri_r2, hi_priority, \app_cmd_r2_reg[0]_0 , rb_hit_busy_r_reg, \req_bank_r_lcl_reg[0] , \req_bank_r_lcl_reg[1] , \req_bank_r_lcl_reg[2] , rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, rb_hit_busy_r_reg_2, \wr_req_counter.wr_req_cnt_r_reg[4] , \wr_req_counter.wr_req_cnt_r_reg[3] , wr_accepted, \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] , rd_accepted, use_addr, \req_data_buf_addr_r_reg[4] , \app_cmd_r2_reg[1]_0 , \req_row_r_lcl_reg[14] , \req_col_r_reg[9] , app_rdy_ns, CLK, app_en_ns1, mc_app_cmd, req_bank_r, reset_reg, p_0_in, wr_req_cnt_r, Q, wr_data_buf_addr, \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] , app_rdy_r_reg_0, \axaddr_incr_reg[29] ); output [0:0]E; output app_en_r1; output app_hi_pri_r2; output hi_priority; output \app_cmd_r2_reg[0]_0 ; output rb_hit_busy_r_reg; output \req_bank_r_lcl_reg[0] ; output \req_bank_r_lcl_reg[1] ; output \req_bank_r_lcl_reg[2] ; output rb_hit_busy_r_reg_0; output rb_hit_busy_r_reg_1; output rb_hit_busy_r_reg_2; output \wr_req_counter.wr_req_cnt_r_reg[4] ; output \wr_req_counter.wr_req_cnt_r_reg[3] ; output wr_accepted; output \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ; output rd_accepted; output use_addr; output [4:0]\req_data_buf_addr_r_reg[4] ; output [0:0]\app_cmd_r2_reg[1]_0 ; output [14:0]\req_row_r_lcl_reg[14] ; output [6:0]\req_col_r_reg[9] ; input app_rdy_ns; input CLK; input app_en_ns1; input [0:0]mc_app_cmd; input [11:0]req_bank_r; input reset_reg; input [0:0]p_0_in; input [1:0]wr_req_cnt_r; input [1:0]Q; input [3:0]wr_data_buf_addr; input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; input [0:0]app_rdy_r_reg_0; input [24:0]\axaddr_incr_reg[29] ; wire CLK; wire [0:0]E; wire [1:0]Q; wire \app_addr_r1_reg_n_0_[13] ; wire \app_addr_r1_reg_n_0_[14] ; wire \app_addr_r1_reg_n_0_[15] ; wire \app_addr_r1_reg_n_0_[16] ; wire \app_addr_r1_reg_n_0_[17] ; wire \app_addr_r1_reg_n_0_[18] ; wire \app_addr_r1_reg_n_0_[19] ; wire \app_addr_r1_reg_n_0_[20] ; wire \app_addr_r1_reg_n_0_[21] ; wire \app_addr_r1_reg_n_0_[22] ; wire \app_addr_r1_reg_n_0_[23] ; wire \app_addr_r1_reg_n_0_[24] ; wire \app_addr_r1_reg_n_0_[25] ; wire \app_addr_r1_reg_n_0_[26] ; wire \app_addr_r1_reg_n_0_[27] ; wire \app_addr_r1_reg_n_0_[3] ; wire \app_addr_r1_reg_n_0_[4] ; wire \app_addr_r1_reg_n_0_[5] ; wire \app_addr_r1_reg_n_0_[6] ; wire \app_addr_r1_reg_n_0_[7] ; wire \app_addr_r1_reg_n_0_[8] ; wire \app_addr_r1_reg_n_0_[9] ; wire \app_addr_r2_reg_n_0_[13] ; wire \app_addr_r2_reg_n_0_[14] ; wire \app_addr_r2_reg_n_0_[15] ; wire \app_addr_r2_reg_n_0_[16] ; wire \app_addr_r2_reg_n_0_[17] ; wire \app_addr_r2_reg_n_0_[18] ; wire \app_addr_r2_reg_n_0_[19] ; wire \app_addr_r2_reg_n_0_[20] ; wire \app_addr_r2_reg_n_0_[21] ; wire \app_addr_r2_reg_n_0_[22] ; wire \app_addr_r2_reg_n_0_[23] ; wire \app_addr_r2_reg_n_0_[24] ; wire \app_addr_r2_reg_n_0_[25] ; wire \app_addr_r2_reg_n_0_[26] ; wire \app_addr_r2_reg_n_0_[27] ; wire \app_addr_r2_reg_n_0_[3] ; wire \app_addr_r2_reg_n_0_[4] ; wire \app_addr_r2_reg_n_0_[5] ; wire \app_addr_r2_reg_n_0_[6] ; wire \app_addr_r2_reg_n_0_[7] ; wire \app_addr_r2_reg_n_0_[8] ; wire \app_addr_r2_reg_n_0_[9] ; wire [0:0]app_cmd_r1; wire \app_cmd_r1[0]_i_1_n_0 ; wire [1:0]app_cmd_r2; wire \app_cmd_r2_reg[0]_0 ; wire [0:0]\app_cmd_r2_reg[1]_0 ; wire app_en_ns1; wire app_en_ns2; wire app_en_r1; wire app_en_r2; wire app_hi_pri_r2; wire app_rdy_ns; wire [0:0]app_rdy_r_reg_0; wire [24:0]\axaddr_incr_reg[29] ; wire hi_priority; wire [0:0]mc_app_cmd; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ; wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ; wire [0:0]p_0_in; wire [2:0]p_0_in_0; wire [2:0]p_1_in; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire rd_accepted; wire [11:0]req_bank_r; wire \req_bank_r_lcl_reg[0] ; wire \req_bank_r_lcl_reg[1] ; wire \req_bank_r_lcl_reg[2] ; wire [6:0]\req_col_r_reg[9] ; wire [4:0]\req_data_buf_addr_r_reg[4] ; wire [14:0]\req_row_r_lcl_reg[14] ; wire reset_reg; wire use_addr; wire wr_accepted; wire [3:0]wr_data_buf_addr; wire [1:0]wr_req_cnt_r; wire \wr_req_counter.wr_req_cnt_r_reg[3] ; wire \wr_req_counter.wr_req_cnt_r_reg[4] ; FDRE #( .INIT(1'b0)) \app_addr_r1_reg[10] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [7]), .Q(p_1_in[0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[11] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [8]), .Q(p_1_in[1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[12] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [9]), .Q(p_1_in[2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[13] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [10]), .Q(\app_addr_r1_reg_n_0_[13] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[14] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [11]), .Q(\app_addr_r1_reg_n_0_[14] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[15] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [12]), .Q(\app_addr_r1_reg_n_0_[15] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[16] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [13]), .Q(\app_addr_r1_reg_n_0_[16] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[17] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [14]), .Q(\app_addr_r1_reg_n_0_[17] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[18] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [15]), .Q(\app_addr_r1_reg_n_0_[18] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[19] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [16]), .Q(\app_addr_r1_reg_n_0_[19] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[20] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [17]), .Q(\app_addr_r1_reg_n_0_[20] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[21] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [18]), .Q(\app_addr_r1_reg_n_0_[21] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[22] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [19]), .Q(\app_addr_r1_reg_n_0_[22] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[23] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [20]), .Q(\app_addr_r1_reg_n_0_[23] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[24] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [21]), .Q(\app_addr_r1_reg_n_0_[24] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[25] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [22]), .Q(\app_addr_r1_reg_n_0_[25] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[26] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [23]), .Q(\app_addr_r1_reg_n_0_[26] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[27] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [24]), .Q(\app_addr_r1_reg_n_0_[27] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[3] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [0]), .Q(\app_addr_r1_reg_n_0_[3] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[4] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [1]), .Q(\app_addr_r1_reg_n_0_[4] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[5] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [2]), .Q(\app_addr_r1_reg_n_0_[5] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[6] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [3]), .Q(\app_addr_r1_reg_n_0_[6] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[7] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [4]), .Q(\app_addr_r1_reg_n_0_[7] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[8] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [5]), .Q(\app_addr_r1_reg_n_0_[8] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r1_reg[9] (.C(CLK), .CE(app_rdy_r_reg_0), .D(\axaddr_incr_reg[29] [6]), .Q(\app_addr_r1_reg_n_0_[9] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[10] (.C(CLK), .CE(E), .D(p_1_in[0]), .Q(p_0_in_0[0]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[11] (.C(CLK), .CE(E), .D(p_1_in[1]), .Q(p_0_in_0[1]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[12] (.C(CLK), .CE(E), .D(p_1_in[2]), .Q(p_0_in_0[2]), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[13] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[13] ), .Q(\app_addr_r2_reg_n_0_[13] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[14] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[14] ), .Q(\app_addr_r2_reg_n_0_[14] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[15] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[15] ), .Q(\app_addr_r2_reg_n_0_[15] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[16] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[16] ), .Q(\app_addr_r2_reg_n_0_[16] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[17] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[17] ), .Q(\app_addr_r2_reg_n_0_[17] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[18] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[18] ), .Q(\app_addr_r2_reg_n_0_[18] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[19] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[19] ), .Q(\app_addr_r2_reg_n_0_[19] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[20] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[20] ), .Q(\app_addr_r2_reg_n_0_[20] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[21] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[21] ), .Q(\app_addr_r2_reg_n_0_[21] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[22] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[22] ), .Q(\app_addr_r2_reg_n_0_[22] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[23] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[23] ), .Q(\app_addr_r2_reg_n_0_[23] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[24] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[24] ), .Q(\app_addr_r2_reg_n_0_[24] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[25] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[25] ), .Q(\app_addr_r2_reg_n_0_[25] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[26] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[26] ), .Q(\app_addr_r2_reg_n_0_[26] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[27] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[27] ), .Q(\app_addr_r2_reg_n_0_[27] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[3] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[3] ), .Q(\app_addr_r2_reg_n_0_[3] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[4] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[4] ), .Q(\app_addr_r2_reg_n_0_[4] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[5] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[5] ), .Q(\app_addr_r2_reg_n_0_[5] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[6] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[6] ), .Q(\app_addr_r2_reg_n_0_[6] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[7] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[7] ), .Q(\app_addr_r2_reg_n_0_[7] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[8] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[8] ), .Q(\app_addr_r2_reg_n_0_[8] ), .R(reset_reg)); FDRE #( .INIT(1'b0)) \app_addr_r2_reg[9] (.C(CLK), .CE(E), .D(\app_addr_r1_reg_n_0_[9] ), .Q(\app_addr_r2_reg_n_0_[9] ), .R(reset_reg)); (* SOFT_HLUTNM = "soft_lutpair1498" *) LUT3 #( .INIT(8'hB8)) \app_cmd_r1[0]_i_1 (.I0(mc_app_cmd), .I1(E), .I2(app_cmd_r1), .O(\app_cmd_r1[0]_i_1_n_0 )); FDRE \app_cmd_r1_reg[0] (.C(CLK), .CE(1'b1), .D(\app_cmd_r1[0]_i_1_n_0 ), .Q(app_cmd_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1489" *) LUT2 #( .INIT(4'h2)) \app_cmd_r2[1]_i_1 (.I0(app_cmd_r2[1]), .I1(E), .O(\app_cmd_r2_reg[1]_0 )); FDRE \app_cmd_r2_reg[0] (.C(CLK), .CE(1'b1), .D(\app_cmd_r2_reg[0]_0 ), .Q(app_cmd_r2[0]), .R(1'b0)); FDRE \app_cmd_r2_reg[1] (.C(CLK), .CE(1'b1), .D(\app_cmd_r2_reg[1]_0 ), .Q(app_cmd_r2[1]), .R(1'b0)); FDRE app_en_r1_reg (.C(CLK), .CE(1'b1), .D(app_en_ns1), .Q(app_en_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1490" *) LUT4 #( .INIT(16'h2230)) app_en_r2_i_1 (.I0(app_en_r1), .I1(reset_reg), .I2(app_en_r2), .I3(E), .O(app_en_ns2)); FDRE app_en_r2_reg (.C(CLK), .CE(1'b1), .D(app_en_ns2), .Q(app_en_r2), .R(1'b0)); FDRE app_hi_pri_r2_reg (.C(CLK), .CE(1'b1), .D(hi_priority), .Q(app_hi_pri_r2), .R(1'b0)); (* syn_maxfan = "10" *) FDRE #( .INIT(1'b0)) app_rdy_r_reg (.C(CLK), .CE(1'b1), .D(app_rdy_ns), .Q(E), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1487" *) LUT4 #( .INIT(16'h8008)) \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 (.I0(E), .I1(app_en_r2), .I2(app_cmd_r2[0]), .I3(app_cmd_r2[1]), .O(wr_accepted)); (* SOFT_HLUTNM = "soft_lutpair1487" *) LUT2 #( .INIT(4'h8)) i___48_i_1 (.I0(app_en_r2), .I1(E), .O(use_addr)); (* SOFT_HLUTNM = "soft_lutpair1498" *) LUT3 #( .INIT(8'hB8)) i___69_i_1 (.I0(app_cmd_r1), .I1(E), .I2(app_cmd_r2[0]), .O(\app_cmd_r2_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair1486" *) LUT4 #( .INIT(16'h4000)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_1 (.I0(app_cmd_r2[1]), .I1(app_cmd_r2[0]), .I2(E), .I3(app_en_r2), .O(rd_accepted)); LUT6 #( .INIT(64'h7555555510000000)) \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2 (.I0(Q[1]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(E), .I4(app_en_r2), .I5(Q[0]), .O(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2 (.I0(\req_bank_r_lcl_reg[2] ), .I1(req_bank_r[5]), .I2(req_bank_r[4]), .I3(\req_bank_r_lcl_reg[1] ), .I4(req_bank_r[3]), .I5(\req_bank_r_lcl_reg[0] ), .O(rb_hit_busy_r_reg_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2 (.I0(\req_bank_r_lcl_reg[2] ), .I1(req_bank_r[8]), .I2(req_bank_r[7]), .I3(\req_bank_r_lcl_reg[1] ), .I4(req_bank_r[6]), .I5(\req_bank_r_lcl_reg[0] ), .O(rb_hit_busy_r_reg_1)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2 (.I0(\req_bank_r_lcl_reg[0] ), .I1(req_bank_r[9]), .I2(req_bank_r[10]), .I3(\req_bank_r_lcl_reg[1] ), .I4(req_bank_r[11]), .I5(\req_bank_r_lcl_reg[2] ), .O(rb_hit_busy_r_reg_2)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) rb_hit_busy_r_i_2 (.I0(\req_bank_r_lcl_reg[0] ), .I1(req_bank_r[0]), .I2(req_bank_r[1]), .I3(\req_bank_r_lcl_reg[1] ), .I4(req_bank_r[2]), .I5(\req_bank_r_lcl_reg[2] ), .O(rb_hit_busy_r_reg)); (* SOFT_HLUTNM = "soft_lutpair1500" *) LUT3 #( .INIT(8'hB8)) \req_bank_r_lcl[0]_i_1 (.I0(p_1_in[0]), .I1(E), .I2(p_0_in_0[0]), .O(\req_bank_r_lcl_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair1500" *) LUT3 #( .INIT(8'hB8)) \req_bank_r_lcl[1]_i_1 (.I0(p_1_in[1]), .I1(E), .I2(p_0_in_0[1]), .O(\req_bank_r_lcl_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair1499" *) LUT3 #( .INIT(8'hB8)) \req_bank_r_lcl[2]_i_1 (.I0(p_1_in[2]), .I1(E), .I2(p_0_in_0[2]), .O(\req_bank_r_lcl_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair1501" *) LUT3 #( .INIT(8'hB8)) \req_col_r[3]_i_1 (.I0(\app_addr_r1_reg_n_0_[3] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[3] ), .O(\req_col_r_reg[9] [0])); LUT3 #( .INIT(8'hB8)) \req_col_r[4]_i_1 (.I0(\app_addr_r1_reg_n_0_[4] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[4] ), .O(\req_col_r_reg[9] [1])); (* SOFT_HLUTNM = "soft_lutpair1503" *) LUT3 #( .INIT(8'hB8)) \req_col_r[5]_i_1 (.I0(\app_addr_r1_reg_n_0_[5] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[5] ), .O(\req_col_r_reg[9] [2])); (* SOFT_HLUTNM = "soft_lutpair1503" *) LUT3 #( .INIT(8'hB8)) \req_col_r[6]_i_1 (.I0(\app_addr_r1_reg_n_0_[6] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[6] ), .O(\req_col_r_reg[9] [3])); (* SOFT_HLUTNM = "soft_lutpair1502" *) LUT3 #( .INIT(8'hB8)) \req_col_r[7]_i_1 (.I0(\app_addr_r1_reg_n_0_[7] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[7] ), .O(\req_col_r_reg[9] [4])); (* SOFT_HLUTNM = "soft_lutpair1502" *) LUT3 #( .INIT(8'hB8)) \req_col_r[8]_i_1 (.I0(\app_addr_r1_reg_n_0_[8] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[8] ), .O(\req_col_r_reg[9] [5])); (* SOFT_HLUTNM = "soft_lutpair1501" *) LUT3 #( .INIT(8'hB8)) \req_col_r[9]_i_1 (.I0(\app_addr_r1_reg_n_0_[9] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[9] ), .O(\req_col_r_reg[9] [6])); LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[0]_i_1 (.I0(wr_data_buf_addr[0]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]), .O(\req_data_buf_addr_r_reg[4] [0])); (* SOFT_HLUTNM = "soft_lutpair1488" *) LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[1]_i_1 (.I0(wr_data_buf_addr[1]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]), .O(\req_data_buf_addr_r_reg[4] [1])); (* SOFT_HLUTNM = "soft_lutpair1489" *) LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[2]_i_1 (.I0(wr_data_buf_addr[2]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]), .O(\req_data_buf_addr_r_reg[4] [2])); LUT4 #( .INIT(16'hBE82)) \req_data_buf_addr_r[3]_i_1 (.I0(wr_data_buf_addr[3]), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]), .O(\req_data_buf_addr_r_reg[4] [3])); (* SOFT_HLUTNM = "soft_lutpair1488" *) LUT3 #( .INIT(8'h28)) \req_data_buf_addr_r[4]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]), .I1(app_cmd_r2[0]), .I2(app_cmd_r2[1]), .O(\req_data_buf_addr_r_reg[4] [4])); (* SOFT_HLUTNM = "soft_lutpair1490" *) LUT2 #( .INIT(4'h2)) req_priority_r_i_1 (.I0(app_hi_pri_r2), .I1(E), .O(hi_priority)); (* SOFT_HLUTNM = "soft_lutpair1496" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[0]_i_1 (.I0(\app_addr_r1_reg_n_0_[13] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[13] ), .O(\req_row_r_lcl_reg[14] [0])); (* SOFT_HLUTNM = "soft_lutpair1491" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[10]_i_1 (.I0(\app_addr_r1_reg_n_0_[23] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[23] ), .O(\req_row_r_lcl_reg[14] [10])); (* SOFT_HLUTNM = "soft_lutpair1499" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[11]_i_1 (.I0(\app_addr_r1_reg_n_0_[24] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[24] ), .O(\req_row_r_lcl_reg[14] [11])); (* SOFT_HLUTNM = "soft_lutpair1497" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[12]_i_1 (.I0(\app_addr_r1_reg_n_0_[25] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[25] ), .O(\req_row_r_lcl_reg[14] [12])); (* SOFT_HLUTNM = "soft_lutpair1495" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[13]_i_1 (.I0(\app_addr_r1_reg_n_0_[26] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[26] ), .O(\req_row_r_lcl_reg[14] [13])); (* SOFT_HLUTNM = "soft_lutpair1493" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[14]_i_1 (.I0(\app_addr_r1_reg_n_0_[27] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[27] ), .O(\req_row_r_lcl_reg[14] [14])); (* SOFT_HLUTNM = "soft_lutpair1495" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[1]_i_1 (.I0(\app_addr_r1_reg_n_0_[14] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[14] ), .O(\req_row_r_lcl_reg[14] [1])); (* SOFT_HLUTNM = "soft_lutpair1494" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[2]_i_1 (.I0(\app_addr_r1_reg_n_0_[15] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[15] ), .O(\req_row_r_lcl_reg[14] [2])); (* SOFT_HLUTNM = "soft_lutpair1493" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[3]_i_1 (.I0(\app_addr_r1_reg_n_0_[16] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[16] ), .O(\req_row_r_lcl_reg[14] [3])); (* SOFT_HLUTNM = "soft_lutpair1492" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[4]_i_1 (.I0(\app_addr_r1_reg_n_0_[17] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[17] ), .O(\req_row_r_lcl_reg[14] [4])); (* SOFT_HLUTNM = "soft_lutpair1491" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[5]_i_1 (.I0(\app_addr_r1_reg_n_0_[18] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[18] ), .O(\req_row_r_lcl_reg[14] [5])); (* SOFT_HLUTNM = "soft_lutpair1497" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[6]_i_1 (.I0(\app_addr_r1_reg_n_0_[19] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[19] ), .O(\req_row_r_lcl_reg[14] [6])); (* SOFT_HLUTNM = "soft_lutpair1496" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[7]_i_1 (.I0(\app_addr_r1_reg_n_0_[20] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[20] ), .O(\req_row_r_lcl_reg[14] [7])); (* SOFT_HLUTNM = "soft_lutpair1494" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[8]_i_1 (.I0(\app_addr_r1_reg_n_0_[21] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[21] ), .O(\req_row_r_lcl_reg[14] [8])); (* SOFT_HLUTNM = "soft_lutpair1492" *) LUT3 #( .INIT(8'hB8)) \req_row_r_lcl[9]_i_1 (.I0(\app_addr_r1_reg_n_0_[22] ), .I1(E), .I2(\app_addr_r2_reg_n_0_[22] ), .O(\req_row_r_lcl_reg[14] [9])); LUT6 #( .INIT(64'hD55555D540000040)) \wr_req_counter.wr_req_cnt_r[3]_i_2 (.I0(wr_req_cnt_r[1]), .I1(E), .I2(app_en_r2), .I3(app_cmd_r2[0]), .I4(app_cmd_r2[1]), .I5(wr_req_cnt_r[0]), .O(\wr_req_counter.wr_req_cnt_r_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair1486" *) LUT5 #( .INIT(32'h96555555)) \wr_req_counter.wr_req_cnt_r[3]_i_3 (.I0(p_0_in), .I1(app_cmd_r2[1]), .I2(app_cmd_r2[0]), .I3(app_en_r2), .I4(E), .O(\wr_req_counter.wr_req_cnt_r_reg[4] )); endmodule module ddr3_if_mig_7series_v4_0_ui_rd_data (\not_strict_mode.app_rd_data_end_reg_0 , Q, DOA, DOB, DOC, \not_strict_mode.app_rd_data_reg[11]_0 , \not_strict_mode.app_rd_data_reg[9]_0 , \not_strict_mode.app_rd_data_reg[7]_0 , \not_strict_mode.app_rd_data_reg[17]_0 , \not_strict_mode.app_rd_data_reg[15]_0 , \not_strict_mode.app_rd_data_reg[13]_0 , \not_strict_mode.app_rd_data_reg[23]_0 , \not_strict_mode.app_rd_data_reg[21]_0 , \not_strict_mode.app_rd_data_reg[19]_0 , \not_strict_mode.app_rd_data_reg[29]_0 , \not_strict_mode.app_rd_data_reg[27]_0 , \not_strict_mode.app_rd_data_reg[25]_0 , \not_strict_mode.app_rd_data_reg[35]_0 , \not_strict_mode.app_rd_data_reg[33]_0 , \not_strict_mode.app_rd_data_reg[31]_0 , \not_strict_mode.app_rd_data_reg[41]_0 , \not_strict_mode.app_rd_data_reg[39]_0 , \not_strict_mode.app_rd_data_reg[37]_0 , \not_strict_mode.app_rd_data_reg[47]_0 , \not_strict_mode.app_rd_data_reg[45]_0 , \not_strict_mode.app_rd_data_reg[43]_0 , \not_strict_mode.app_rd_data_reg[53]_0 , \not_strict_mode.app_rd_data_reg[51]_0 , \not_strict_mode.app_rd_data_reg[49]_0 , \not_strict_mode.app_rd_data_reg[59]_0 , \not_strict_mode.app_rd_data_reg[57]_0 , \not_strict_mode.app_rd_data_reg[55]_0 , \not_strict_mode.app_rd_data_reg[65]_0 , \not_strict_mode.app_rd_data_reg[63]_0 , \not_strict_mode.app_rd_data_reg[61]_0 , \not_strict_mode.app_rd_data_reg[71]_0 , \not_strict_mode.app_rd_data_reg[69]_0 , \not_strict_mode.app_rd_data_reg[67]_0 , \not_strict_mode.app_rd_data_reg[77]_0 , \not_strict_mode.app_rd_data_reg[75]_0 , \not_strict_mode.app_rd_data_reg[73]_0 , \not_strict_mode.app_rd_data_reg[83]_0 , \not_strict_mode.app_rd_data_reg[81]_0 , \not_strict_mode.app_rd_data_reg[79]_0 , \not_strict_mode.app_rd_data_reg[89]_0 , \not_strict_mode.app_rd_data_reg[87]_0 , \not_strict_mode.app_rd_data_reg[85]_0 , \not_strict_mode.app_rd_data_reg[95]_0 , \not_strict_mode.app_rd_data_reg[93]_0 , \not_strict_mode.app_rd_data_reg[91]_0 , \not_strict_mode.app_rd_data_reg[101]_0 , \not_strict_mode.app_rd_data_reg[99]_0 , \not_strict_mode.app_rd_data_reg[97]_0 , \not_strict_mode.app_rd_data_reg[107]_0 , \not_strict_mode.app_rd_data_reg[105]_0 , \not_strict_mode.app_rd_data_reg[103]_0 , \not_strict_mode.app_rd_data_reg[113]_0 , \not_strict_mode.app_rd_data_reg[111]_0 , \not_strict_mode.app_rd_data_reg[109]_0 , \not_strict_mode.app_rd_data_reg[119]_0 , \not_strict_mode.app_rd_data_reg[117]_0 , \not_strict_mode.app_rd_data_reg[115]_0 , \not_strict_mode.app_rd_data_reg[125]_0 , \not_strict_mode.app_rd_data_reg[123]_0 , \not_strict_mode.app_rd_data_reg[121]_0 , \not_strict_mode.app_rd_data_reg[131]_0 , \not_strict_mode.app_rd_data_reg[129]_0 , \not_strict_mode.app_rd_data_reg[127]_0 , \not_strict_mode.app_rd_data_reg[137]_0 , \not_strict_mode.app_rd_data_reg[135]_0 , \not_strict_mode.app_rd_data_reg[133]_0 , \not_strict_mode.app_rd_data_reg[143]_0 , \not_strict_mode.app_rd_data_reg[141]_0 , \not_strict_mode.app_rd_data_reg[139]_0 , \not_strict_mode.app_rd_data_reg[149]_0 , \not_strict_mode.app_rd_data_reg[147]_0 , \not_strict_mode.app_rd_data_reg[145]_0 , \not_strict_mode.app_rd_data_reg[155]_0 , \not_strict_mode.app_rd_data_reg[153]_0 , \not_strict_mode.app_rd_data_reg[151]_0 , \not_strict_mode.app_rd_data_reg[161]_0 , \not_strict_mode.app_rd_data_reg[159]_0 , \not_strict_mode.app_rd_data_reg[157]_0 , \not_strict_mode.app_rd_data_reg[167]_0 , \not_strict_mode.app_rd_data_reg[165]_0 , \not_strict_mode.app_rd_data_reg[163]_0 , \not_strict_mode.app_rd_data_reg[173]_0 , \not_strict_mode.app_rd_data_reg[171]_0 , \not_strict_mode.app_rd_data_reg[169]_0 , \not_strict_mode.app_rd_data_reg[179]_0 , \not_strict_mode.app_rd_data_reg[177]_0 , \not_strict_mode.app_rd_data_reg[175]_0 , \not_strict_mode.app_rd_data_reg[185]_0 , \not_strict_mode.app_rd_data_reg[183]_0 , \not_strict_mode.app_rd_data_reg[181]_0 , \not_strict_mode.app_rd_data_reg[191]_0 , \not_strict_mode.app_rd_data_reg[189]_0 , \not_strict_mode.app_rd_data_reg[187]_0 , \not_strict_mode.app_rd_data_reg[197]_0 , \not_strict_mode.app_rd_data_reg[195]_0 , \not_strict_mode.app_rd_data_reg[193]_0 , \not_strict_mode.app_rd_data_reg[203]_0 , \not_strict_mode.app_rd_data_reg[201]_0 , \not_strict_mode.app_rd_data_reg[199]_0 , \not_strict_mode.app_rd_data_reg[209]_0 , \not_strict_mode.app_rd_data_reg[207]_0 , \not_strict_mode.app_rd_data_reg[205]_0 , \not_strict_mode.app_rd_data_reg[215]_0 , \not_strict_mode.app_rd_data_reg[213]_0 , \not_strict_mode.app_rd_data_reg[211]_0 , \not_strict_mode.app_rd_data_reg[221]_0 , \not_strict_mode.app_rd_data_reg[219]_0 , \not_strict_mode.app_rd_data_reg[217]_0 , \not_strict_mode.app_rd_data_reg[227]_0 , \not_strict_mode.app_rd_data_reg[225]_0 , \not_strict_mode.app_rd_data_reg[223]_0 , \not_strict_mode.app_rd_data_reg[233]_0 , \not_strict_mode.app_rd_data_reg[231]_0 , \not_strict_mode.app_rd_data_reg[229]_0 , \not_strict_mode.app_rd_data_reg[239]_0 , \not_strict_mode.app_rd_data_reg[237]_0 , \not_strict_mode.app_rd_data_reg[235]_0 , \not_strict_mode.app_rd_data_reg[245]_0 , \not_strict_mode.app_rd_data_reg[243]_0 , \not_strict_mode.app_rd_data_reg[241]_0 , \not_strict_mode.app_rd_data_reg[251]_0 , \not_strict_mode.app_rd_data_reg[249]_0 , \not_strict_mode.app_rd_data_reg[247]_0 , \not_strict_mode.app_rd_data_reg[255]_0 , \not_strict_mode.app_rd_data_reg[253]_0 , \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 , app_rd_data_valid, D, \not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 , \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 , \rd_buf_indx.ram_init_done_r_lcl_reg_0 , ADDRD, pointer_wr_data, \s_axi_rdata[255] , CLK, rd_buf_we, DIA, DIB, DIC, \read_fifo.fifo_out_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] , app_rd_data_end_ns, rd_accepted, reset_reg, \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 , bypass__0, \read_data_indx.rd_data_indx_r_reg[3] , \cmd_pipe_plus.wr_data_addr_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ); output [0:0]\not_strict_mode.app_rd_data_end_reg_0 ; output [4:0]Q; output [1:0]DOA; output [1:0]DOB; output [1:0]DOC; output [1:0]\not_strict_mode.app_rd_data_reg[11]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[9]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[7]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[17]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[15]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[13]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[23]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[21]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[19]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[29]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[27]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[25]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[35]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[33]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[31]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[41]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[39]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[37]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[47]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[45]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[43]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[53]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[51]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[49]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[59]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[57]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[55]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[65]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[63]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[61]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[71]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[69]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[67]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[77]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[75]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[73]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[83]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[81]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[79]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[89]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[87]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[85]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[95]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[93]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[91]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[101]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[99]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[97]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[107]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[105]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[103]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[113]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[111]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[109]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[119]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[117]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[115]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[125]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[123]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[121]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[131]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[129]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[127]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[137]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[135]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[133]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[143]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[141]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[139]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[149]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[147]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[145]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[155]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[153]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[151]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[161]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[159]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[157]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[167]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[165]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[163]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[173]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[171]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[169]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[179]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[177]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[175]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[185]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[183]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[181]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[191]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[189]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[187]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[197]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[195]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[193]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[203]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[201]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[199]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[209]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[207]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[205]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[215]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[213]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[211]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[221]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[219]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[217]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[227]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[225]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[223]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[233]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[231]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[229]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[239]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[237]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[235]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[245]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[243]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[241]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[251]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[249]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[247]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[255]_0 ; output [1:0]\not_strict_mode.app_rd_data_reg[253]_0 ; output \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ; output app_rd_data_valid; output [0:0]D; output [1:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ; output [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ; output \rd_buf_indx.ram_init_done_r_lcl_reg_0 ; output [3:0]ADDRD; output [3:0]pointer_wr_data; output [255:0]\s_axi_rdata[255] ; input CLK; input rd_buf_we; input [1:0]DIA; input [1:0]DIB; input [1:0]DIC; input [6:0]\read_fifo.fifo_out_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; input app_rd_data_end_ns; input rd_accepted; input reset_reg; input \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ; input bypass__0; input [3:0]\read_data_indx.rd_data_indx_r_reg[3] ; input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; input [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [3:0]ADDRD; wire CLK; wire [0:0]D; wire [1:0]DIA; wire [1:0]DIB; wire [1:0]DIC; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [4:0]Q; wire app_rd_data_end; wire app_rd_data_end_ns; wire app_rd_data_valid; wire app_rd_data_valid_copy; wire app_rd_data_valid_ns; wire bypass__0; wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire [0:0]\not_strict_mode.app_rd_data_end_reg_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[101]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[103]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[105]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[107]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[109]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[111]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[113]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[115]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[117]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[119]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[11]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[121]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[123]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[125]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[127]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[129]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[131]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[133]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[135]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[137]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[139]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[13]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[141]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[143]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[145]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[147]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[149]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[151]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[153]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[155]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[157]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[159]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[15]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[161]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[163]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[165]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[167]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[169]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[171]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[173]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[175]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[177]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[179]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[17]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[181]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[183]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[185]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[187]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[189]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[191]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[193]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[195]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[197]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[199]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[19]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[201]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[203]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[205]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[207]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[209]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[211]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[213]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[215]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[217]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[219]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[21]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[221]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[223]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[225]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[227]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[229]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[231]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[233]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[235]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[237]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[239]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[23]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[241]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[243]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[245]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[247]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[249]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[251]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[253]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[255]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[25]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[27]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[29]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[31]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[33]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[35]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[37]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[39]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[41]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[43]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[45]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[47]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[49]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[51]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[53]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[55]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[57]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[59]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[61]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[63]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[65]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[67]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[69]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[71]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[73]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[75]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[77]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[79]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[7]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[81]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[83]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[85]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[87]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[89]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[91]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[93]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[95]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[97]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[99]_0 ; wire [1:0]\not_strict_mode.app_rd_data_reg[9]_0 ; wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ; wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ; wire [1:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ; wire \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ; wire [5:2]occ_cnt_r; wire [4:0]p_0_in__2; wire [3:0]pointer_wr_data; wire ram_init_done_ns; wire rd_accepted; wire \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ; wire \rd_buf_indx.ram_init_done_r_lcl_reg_0 ; wire \rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ; wire \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ; wire \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ; (* RTL_KEEP = "true" *) (* syn_keep = "true" *) wire [4:0]rd_buf_indx_copy_r; wire [5:0]rd_buf_indx_ns; wire rd_buf_we; wire rd_buf_we_r1; wire [0:0]rd_status; wire [3:0]\read_data_indx.rd_data_indx_r_reg[3] ; wire [6:0]\read_fifo.fifo_out_data_r_reg[7] ; wire reset_reg; wire [255:0]\s_axi_rdata[255] ; wire [4:0]status_ram_wr_addr_ns; wire [4:0]status_ram_wr_addr_r; wire [1:0]status_ram_wr_data_ns; wire [1:0]status_ram_wr_data_r; wire wr_status; wire wr_status_r1; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED ; wire [1:1]\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED ; wire [1:0]\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED ; FDRE \not_strict_mode.app_rd_data_end_reg (.C(CLK), .CE(1'b1), .D(app_rd_data_end_ns), .Q(app_rd_data_end), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[0] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [0]), .Q(\s_axi_rdata[255] [0]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[100] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [100]), .Q(\s_axi_rdata[255] [100]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[101] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [101]), .Q(\s_axi_rdata[255] [101]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[102] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [102]), .Q(\s_axi_rdata[255] [102]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[103] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [103]), .Q(\s_axi_rdata[255] [103]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[104] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [104]), .Q(\s_axi_rdata[255] [104]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[105] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [105]), .Q(\s_axi_rdata[255] [105]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[106] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [106]), .Q(\s_axi_rdata[255] [106]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[107] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [107]), .Q(\s_axi_rdata[255] [107]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[108] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [108]), .Q(\s_axi_rdata[255] [108]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[109] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [109]), .Q(\s_axi_rdata[255] [109]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[10] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [10]), .Q(\s_axi_rdata[255] [10]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[110] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [110]), .Q(\s_axi_rdata[255] [110]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[111] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [111]), .Q(\s_axi_rdata[255] [111]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[112] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [112]), .Q(\s_axi_rdata[255] [112]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[113] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [113]), .Q(\s_axi_rdata[255] [113]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[114] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [114]), .Q(\s_axi_rdata[255] [114]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[115] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [115]), .Q(\s_axi_rdata[255] [115]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[116] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [116]), .Q(\s_axi_rdata[255] [116]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[117] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [117]), .Q(\s_axi_rdata[255] [117]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[118] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [118]), .Q(\s_axi_rdata[255] [118]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[119] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [119]), .Q(\s_axi_rdata[255] [119]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[11] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [11]), .Q(\s_axi_rdata[255] [11]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[120] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [120]), .Q(\s_axi_rdata[255] [120]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[121] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [121]), .Q(\s_axi_rdata[255] [121]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[122] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [122]), .Q(\s_axi_rdata[255] [122]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[123] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [123]), .Q(\s_axi_rdata[255] [123]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[124] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [124]), .Q(\s_axi_rdata[255] [124]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[125] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [125]), .Q(\s_axi_rdata[255] [125]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[126] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [126]), .Q(\s_axi_rdata[255] [126]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[127] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [127]), .Q(\s_axi_rdata[255] [127]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[128] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [128]), .Q(\s_axi_rdata[255] [128]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[129] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [129]), .Q(\s_axi_rdata[255] [129]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[12] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [12]), .Q(\s_axi_rdata[255] [12]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[130] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [130]), .Q(\s_axi_rdata[255] [130]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[131] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [131]), .Q(\s_axi_rdata[255] [131]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[132] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [132]), .Q(\s_axi_rdata[255] [132]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[133] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [133]), .Q(\s_axi_rdata[255] [133]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[134] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [134]), .Q(\s_axi_rdata[255] [134]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[135] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [135]), .Q(\s_axi_rdata[255] [135]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[136] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [136]), .Q(\s_axi_rdata[255] [136]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[137] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [137]), .Q(\s_axi_rdata[255] [137]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[138] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [138]), .Q(\s_axi_rdata[255] [138]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[139] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [139]), .Q(\s_axi_rdata[255] [139]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[13] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [13]), .Q(\s_axi_rdata[255] [13]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[140] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [140]), .Q(\s_axi_rdata[255] [140]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[141] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [141]), .Q(\s_axi_rdata[255] [141]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[142] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [142]), .Q(\s_axi_rdata[255] [142]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[143] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [143]), .Q(\s_axi_rdata[255] [143]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[144] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [144]), .Q(\s_axi_rdata[255] [144]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[145] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [145]), .Q(\s_axi_rdata[255] [145]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[146] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [146]), .Q(\s_axi_rdata[255] [146]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[147] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [147]), .Q(\s_axi_rdata[255] [147]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[148] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [148]), .Q(\s_axi_rdata[255] [148]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[149] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [149]), .Q(\s_axi_rdata[255] [149]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[14] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [14]), .Q(\s_axi_rdata[255] [14]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[150] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [150]), .Q(\s_axi_rdata[255] [150]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[151] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [151]), .Q(\s_axi_rdata[255] [151]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[152] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [152]), .Q(\s_axi_rdata[255] [152]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[153] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [153]), .Q(\s_axi_rdata[255] [153]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[154] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [154]), .Q(\s_axi_rdata[255] [154]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[155] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [155]), .Q(\s_axi_rdata[255] [155]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[156] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [156]), .Q(\s_axi_rdata[255] [156]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[157] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [157]), .Q(\s_axi_rdata[255] [157]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[158] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [158]), .Q(\s_axi_rdata[255] [158]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[159] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [159]), .Q(\s_axi_rdata[255] [159]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[15] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [15]), .Q(\s_axi_rdata[255] [15]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[160] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [160]), .Q(\s_axi_rdata[255] [160]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[161] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [161]), .Q(\s_axi_rdata[255] [161]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[162] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [162]), .Q(\s_axi_rdata[255] [162]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[163] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [163]), .Q(\s_axi_rdata[255] [163]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[164] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [164]), .Q(\s_axi_rdata[255] [164]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[165] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [165]), .Q(\s_axi_rdata[255] [165]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[166] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [166]), .Q(\s_axi_rdata[255] [166]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[167] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [167]), .Q(\s_axi_rdata[255] [167]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[168] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [168]), .Q(\s_axi_rdata[255] [168]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[169] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [169]), .Q(\s_axi_rdata[255] [169]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[16] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [16]), .Q(\s_axi_rdata[255] [16]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[170] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [170]), .Q(\s_axi_rdata[255] [170]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[171] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [171]), .Q(\s_axi_rdata[255] [171]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[172] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [172]), .Q(\s_axi_rdata[255] [172]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[173] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [173]), .Q(\s_axi_rdata[255] [173]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[174] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [174]), .Q(\s_axi_rdata[255] [174]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[175] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [175]), .Q(\s_axi_rdata[255] [175]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[176] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [176]), .Q(\s_axi_rdata[255] [176]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[177] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [177]), .Q(\s_axi_rdata[255] [177]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[178] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [178]), .Q(\s_axi_rdata[255] [178]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[179] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [179]), .Q(\s_axi_rdata[255] [179]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[17] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [17]), .Q(\s_axi_rdata[255] [17]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[180] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [180]), .Q(\s_axi_rdata[255] [180]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[181] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [181]), .Q(\s_axi_rdata[255] [181]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[182] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [182]), .Q(\s_axi_rdata[255] [182]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[183] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [183]), .Q(\s_axi_rdata[255] [183]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[184] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [184]), .Q(\s_axi_rdata[255] [184]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[185] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [185]), .Q(\s_axi_rdata[255] [185]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[186] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [186]), .Q(\s_axi_rdata[255] [186]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[187] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [187]), .Q(\s_axi_rdata[255] [187]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[188] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [188]), .Q(\s_axi_rdata[255] [188]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[189] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [189]), .Q(\s_axi_rdata[255] [189]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[18] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [18]), .Q(\s_axi_rdata[255] [18]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[190] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [190]), .Q(\s_axi_rdata[255] [190]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[191] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [191]), .Q(\s_axi_rdata[255] [191]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[192] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [192]), .Q(\s_axi_rdata[255] [192]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[193] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [193]), .Q(\s_axi_rdata[255] [193]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[194] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [194]), .Q(\s_axi_rdata[255] [194]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[195] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [195]), .Q(\s_axi_rdata[255] [195]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[196] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [196]), .Q(\s_axi_rdata[255] [196]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[197] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [197]), .Q(\s_axi_rdata[255] [197]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[198] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [198]), .Q(\s_axi_rdata[255] [198]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[199] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [199]), .Q(\s_axi_rdata[255] [199]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[19] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [19]), .Q(\s_axi_rdata[255] [19]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[1] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [1]), .Q(\s_axi_rdata[255] [1]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[200] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [200]), .Q(\s_axi_rdata[255] [200]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[201] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [201]), .Q(\s_axi_rdata[255] [201]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[202] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [202]), .Q(\s_axi_rdata[255] [202]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[203] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [203]), .Q(\s_axi_rdata[255] [203]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[204] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [204]), .Q(\s_axi_rdata[255] [204]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[205] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [205]), .Q(\s_axi_rdata[255] [205]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[206] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [206]), .Q(\s_axi_rdata[255] [206]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[207] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [207]), .Q(\s_axi_rdata[255] [207]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[208] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [208]), .Q(\s_axi_rdata[255] [208]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[209] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [209]), .Q(\s_axi_rdata[255] [209]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[20] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [20]), .Q(\s_axi_rdata[255] [20]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[210] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [210]), .Q(\s_axi_rdata[255] [210]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[211] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [211]), .Q(\s_axi_rdata[255] [211]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[212] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [212]), .Q(\s_axi_rdata[255] [212]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[213] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [213]), .Q(\s_axi_rdata[255] [213]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[214] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [214]), .Q(\s_axi_rdata[255] [214]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[215] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [215]), .Q(\s_axi_rdata[255] [215]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[216] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [216]), .Q(\s_axi_rdata[255] [216]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[217] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [217]), .Q(\s_axi_rdata[255] [217]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[218] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [218]), .Q(\s_axi_rdata[255] [218]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[219] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [219]), .Q(\s_axi_rdata[255] [219]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[21] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [21]), .Q(\s_axi_rdata[255] [21]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[220] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [220]), .Q(\s_axi_rdata[255] [220]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[221] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [221]), .Q(\s_axi_rdata[255] [221]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[222] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [222]), .Q(\s_axi_rdata[255] [222]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[223] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [223]), .Q(\s_axi_rdata[255] [223]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[224] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [224]), .Q(\s_axi_rdata[255] [224]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[225] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [225]), .Q(\s_axi_rdata[255] [225]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[226] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [226]), .Q(\s_axi_rdata[255] [226]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[227] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [227]), .Q(\s_axi_rdata[255] [227]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[228] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [228]), .Q(\s_axi_rdata[255] [228]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[229] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [229]), .Q(\s_axi_rdata[255] [229]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[22] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [22]), .Q(\s_axi_rdata[255] [22]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[230] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [230]), .Q(\s_axi_rdata[255] [230]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[231] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [231]), .Q(\s_axi_rdata[255] [231]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[232] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [232]), .Q(\s_axi_rdata[255] [232]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[233] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [233]), .Q(\s_axi_rdata[255] [233]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[234] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [234]), .Q(\s_axi_rdata[255] [234]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[235] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [235]), .Q(\s_axi_rdata[255] [235]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[236] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [236]), .Q(\s_axi_rdata[255] [236]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[237] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [237]), .Q(\s_axi_rdata[255] [237]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[238] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [238]), .Q(\s_axi_rdata[255] [238]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[239] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [239]), .Q(\s_axi_rdata[255] [239]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[23] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [23]), .Q(\s_axi_rdata[255] [23]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[240] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [240]), .Q(\s_axi_rdata[255] [240]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[241] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [241]), .Q(\s_axi_rdata[255] [241]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[242] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [242]), .Q(\s_axi_rdata[255] [242]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[243] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [243]), .Q(\s_axi_rdata[255] [243]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[244] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [244]), .Q(\s_axi_rdata[255] [244]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[245] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [245]), .Q(\s_axi_rdata[255] [245]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[246] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [246]), .Q(\s_axi_rdata[255] [246]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[247] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [247]), .Q(\s_axi_rdata[255] [247]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[248] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [248]), .Q(\s_axi_rdata[255] [248]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[249] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [249]), .Q(\s_axi_rdata[255] [249]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[24] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [24]), .Q(\s_axi_rdata[255] [24]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[250] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [250]), .Q(\s_axi_rdata[255] [250]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[251] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [251]), .Q(\s_axi_rdata[255] [251]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[252] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [252]), .Q(\s_axi_rdata[255] [252]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[253] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [253]), .Q(\s_axi_rdata[255] [253]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[254] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [254]), .Q(\s_axi_rdata[255] [254]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[255] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [255]), .Q(\s_axi_rdata[255] [255]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[25] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [25]), .Q(\s_axi_rdata[255] [25]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[26] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [26]), .Q(\s_axi_rdata[255] [26]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[27] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [27]), .Q(\s_axi_rdata[255] [27]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[28] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [28]), .Q(\s_axi_rdata[255] [28]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[29] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [29]), .Q(\s_axi_rdata[255] [29]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[2] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [2]), .Q(\s_axi_rdata[255] [2]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[30] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [30]), .Q(\s_axi_rdata[255] [30]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[31] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [31]), .Q(\s_axi_rdata[255] [31]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[32] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [32]), .Q(\s_axi_rdata[255] [32]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[33] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [33]), .Q(\s_axi_rdata[255] [33]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[34] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [34]), .Q(\s_axi_rdata[255] [34]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[35] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [35]), .Q(\s_axi_rdata[255] [35]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[36] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [36]), .Q(\s_axi_rdata[255] [36]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[37] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [37]), .Q(\s_axi_rdata[255] [37]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[38] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [38]), .Q(\s_axi_rdata[255] [38]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[39] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [39]), .Q(\s_axi_rdata[255] [39]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[3] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [3]), .Q(\s_axi_rdata[255] [3]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[40] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [40]), .Q(\s_axi_rdata[255] [40]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[41] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [41]), .Q(\s_axi_rdata[255] [41]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[42] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [42]), .Q(\s_axi_rdata[255] [42]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[43] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [43]), .Q(\s_axi_rdata[255] [43]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[44] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [44]), .Q(\s_axi_rdata[255] [44]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[45] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [45]), .Q(\s_axi_rdata[255] [45]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[46] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [46]), .Q(\s_axi_rdata[255] [46]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[47] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [47]), .Q(\s_axi_rdata[255] [47]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[48] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [48]), .Q(\s_axi_rdata[255] [48]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[49] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [49]), .Q(\s_axi_rdata[255] [49]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[4] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [4]), .Q(\s_axi_rdata[255] [4]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[50] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [50]), .Q(\s_axi_rdata[255] [50]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[51] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [51]), .Q(\s_axi_rdata[255] [51]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[52] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [52]), .Q(\s_axi_rdata[255] [52]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[53] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [53]), .Q(\s_axi_rdata[255] [53]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[54] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [54]), .Q(\s_axi_rdata[255] [54]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[55] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [55]), .Q(\s_axi_rdata[255] [55]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[56] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [56]), .Q(\s_axi_rdata[255] [56]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[57] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [57]), .Q(\s_axi_rdata[255] [57]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[58] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [58]), .Q(\s_axi_rdata[255] [58]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[59] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [59]), .Q(\s_axi_rdata[255] [59]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[5] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [5]), .Q(\s_axi_rdata[255] [5]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[60] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [60]), .Q(\s_axi_rdata[255] [60]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[61] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [61]), .Q(\s_axi_rdata[255] [61]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[62] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [62]), .Q(\s_axi_rdata[255] [62]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[63] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [63]), .Q(\s_axi_rdata[255] [63]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[64] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [64]), .Q(\s_axi_rdata[255] [64]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[65] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [65]), .Q(\s_axi_rdata[255] [65]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[66] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [66]), .Q(\s_axi_rdata[255] [66]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[67] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [67]), .Q(\s_axi_rdata[255] [67]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[68] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [68]), .Q(\s_axi_rdata[255] [68]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[69] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [69]), .Q(\s_axi_rdata[255] [69]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[6] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [6]), .Q(\s_axi_rdata[255] [6]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[70] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [70]), .Q(\s_axi_rdata[255] [70]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[71] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [71]), .Q(\s_axi_rdata[255] [71]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[72] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [72]), .Q(\s_axi_rdata[255] [72]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[73] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [73]), .Q(\s_axi_rdata[255] [73]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[74] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [74]), .Q(\s_axi_rdata[255] [74]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[75] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [75]), .Q(\s_axi_rdata[255] [75]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[76] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [76]), .Q(\s_axi_rdata[255] [76]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[77] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [77]), .Q(\s_axi_rdata[255] [77]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[78] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [78]), .Q(\s_axi_rdata[255] [78]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[79] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [79]), .Q(\s_axi_rdata[255] [79]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[7] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [7]), .Q(\s_axi_rdata[255] [7]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[80] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [80]), .Q(\s_axi_rdata[255] [80]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[81] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [81]), .Q(\s_axi_rdata[255] [81]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[82] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [82]), .Q(\s_axi_rdata[255] [82]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[83] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [83]), .Q(\s_axi_rdata[255] [83]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[84] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [84]), .Q(\s_axi_rdata[255] [84]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[85] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [85]), .Q(\s_axi_rdata[255] [85]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[86] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [86]), .Q(\s_axi_rdata[255] [86]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[87] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [87]), .Q(\s_axi_rdata[255] [87]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[88] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [88]), .Q(\s_axi_rdata[255] [88]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[89] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [89]), .Q(\s_axi_rdata[255] [89]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[8] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [8]), .Q(\s_axi_rdata[255] [8]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[90] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [90]), .Q(\s_axi_rdata[255] [90]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[91] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [91]), .Q(\s_axi_rdata[255] [91]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[92] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [92]), .Q(\s_axi_rdata[255] [92]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[93] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [93]), .Q(\s_axi_rdata[255] [93]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[94] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [94]), .Q(\s_axi_rdata[255] [94]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[95] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [95]), .Q(\s_axi_rdata[255] [95]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[96] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [96]), .Q(\s_axi_rdata[255] [96]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[97] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [97]), .Q(\s_axi_rdata[255] [97]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[98] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [98]), .Q(\s_axi_rdata[255] [98]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[99] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [99]), .Q(\s_axi_rdata[255] [99]), .R(1'b0)); FDRE \not_strict_mode.app_rd_data_reg[9] (.C(CLK), .CE(1'b1), .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [9]), .Q(\s_axi_rdata[255] [9]), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE \not_strict_mode.app_rd_data_valid_copy_reg (.C(CLK), .CE(1'b1), .D(app_rd_data_valid_ns), .Q(app_rd_data_valid_copy), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1505" *) LUT4 #( .INIT(16'hEB00)) \not_strict_mode.app_rd_data_valid_i_1 (.I0(bypass__0), .I1(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I2(rd_status), .I3(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .O(app_rd_data_valid_ns)); (* syn_maxfan = "10" *) FDRE \not_strict_mode.app_rd_data_valid_reg (.C(CLK), .CE(1'b1), .D(app_rd_data_valid_ns), .Q(app_rd_data_valid), .R(1'b0)); LUT1 #( .INIT(2'h1)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[0]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair1511" *) LUT2 #( .INIT(4'h6)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[1]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair1511" *) LUT3 #( .INIT(8'h78)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[2]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair1506" *) LUT4 #( .INIT(16'h7F80)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[3]_i_1 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]), .O(p_0_in__2[3])); (* SOFT_HLUTNM = "soft_lutpair1506" *) LUT5 #( .INIT(32'h7FFF8000)) \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_2 (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]), .I4(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]), .O(p_0_in__2[4])); FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[0] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[0]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]), .R(reset_reg)); FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[1] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[1]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]), .R(reset_reg)); FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[2] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[2]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]), .R(reset_reg)); FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[3] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[3]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]), .R(reset_reg)); FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (.C(CLK), .CE(rd_accepted), .D(p_0_in__2[4]), .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]), .R(reset_reg)); (* SOFT_HLUTNM = "soft_lutpair1507" *) LUT5 #( .INIT(32'h00009666)) \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I1(rd_accepted), .I2(app_rd_data_valid_copy), .I3(app_rd_data_end), .I4(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000C96C6C6C)) \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I2(rd_accepted), .I3(app_rd_data_valid_copy), .I4(app_rd_data_end), .I5(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF81007E008100)) \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I1(rd_accepted), .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I4(occ_cnt_r[2]), .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF81007E008100)) \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1 (.I0(occ_cnt_r[2]), .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ), .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I4(occ_cnt_r[3]), .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFF906090)) \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1 (.I0(occ_cnt_r[3]), .I1(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ), .I2(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I3(occ_cnt_r[4]), .I4(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFF81007E008100)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_1 (.I0(occ_cnt_r[4]), .I1(occ_cnt_r[3]), .I2(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ), .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ), .I4(occ_cnt_r[5]), .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ), .O(D)); LUT5 #( .INIT(32'h8000FFFE)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .I1(rd_accepted), .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .I3(occ_cnt_r[2]), .I4(occ_cnt_r[3]), .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1507" *) LUT4 #( .INIT(16'h006A)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3 (.I0(rd_accepted), .I1(app_rd_data_valid_copy), .I2(app_rd_data_end), .I3(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1508" *) LUT4 #( .INIT(16'h0095)) \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4 (.I0(rd_accepted), .I1(app_rd_data_valid_copy), .I2(app_rd_data_end), .I3(reset_reg), .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 )); FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ), .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]), .R(1'b0)); FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ), .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]), .R(1'b0)); FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ), .Q(occ_cnt_r[2]), .R(1'b0)); FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ), .Q(occ_cnt_r[3]), .R(1'b0)); FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[4] (.C(CLK), .CE(1'b1), .D(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ), .Q(occ_cnt_r[4]), .R(1'b0)); FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[5] (.C(CLK), .CE(1'b1), .D(D), .Q(occ_cnt_r[5]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[0]), .Q(rd_buf_indx_copy_r[0]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[1]), .Q(rd_buf_indx_copy_r[1]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[2]), .Q(rd_buf_indx_copy_r[2]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[3]), .Q(rd_buf_indx_copy_r[3]), .R(1'b0)); (* KEEP = "yes" *) (* syn_keep = "true" *) FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[4]), .Q(rd_buf_indx_copy_r[4]), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID({1'b0,1'b0}), .DOA(DOA), .DOB(DOB), .DOC(DOC), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[65]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[63]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[61]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[71]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[69]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[67]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[77]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[75]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[73]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[83]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[81]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[79]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[89]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[87]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[85]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[95]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[93]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[91]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[101]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[99]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[97]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[107]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[105]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[103]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[113]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[111]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[109]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[119]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[117]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[115]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[11]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[9]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[7]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[125]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[123]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[121]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[131]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[129]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[127]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[137]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[135]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[133]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[143]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[141]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[139]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[149]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[147]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[145]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[155]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[153]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[151]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[161]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[159]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[157]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[167]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[165]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[163]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[173]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[171]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[169]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[179]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[177]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[175]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[17]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[15]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[13]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[185]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[183]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[181]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[191]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[189]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[187]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[197]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[195]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[193]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[203]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[201]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[199]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[209]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[207]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[205]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[215]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[213]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[211]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[221]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[219]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[217]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[227]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[225]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[223]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[233]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[231]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[229]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[239]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[237]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[235]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[23]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[21]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[19]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[245]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[243]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[241]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[251]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[249]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[247]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA({1'b0,1'b0}), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .DID({1'b0,1'b0}), .DOA(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(\not_strict_mode.app_rd_data_reg[255]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[253]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[29]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[27]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[25]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[35]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[33]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[31]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[41]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[39]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[37]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[47]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[45]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[43]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[53]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[51]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[49]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 (.ADDRA(rd_buf_indx_copy_r), .ADDRB(rd_buf_indx_copy_r), .ADDRC(rd_buf_indx_copy_r), .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]), .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .DID({1'b0,1'b0}), .DOA(\not_strict_mode.app_rd_data_reg[59]_0 ), .DOB(\not_strict_mode.app_rd_data_reg[57]_0 ), .DOC(\not_strict_mode.app_rd_data_reg[55]_0 ), .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \not_strict_mode.status_ram.RAM32M0 (.ADDRA(Q), .ADDRB({1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRC(status_ram_wr_addr_ns), .ADDRD(status_ram_wr_addr_r), .DIA(status_ram_wr_data_r), .DIB({1'b0,1'b0}), .DIC(status_ram_wr_data_r), .DID(status_ram_wr_data_r), .DOA({\not_strict_mode.app_rd_data_end_reg_0 ,rd_status}), .DOB(\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED [1:0]), .DOC({\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED [1],wr_status}), .DOD(\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(rd_buf_we_r1)); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_1 (.I0(\read_fifo.fifo_out_data_r_reg[7] [5]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[4]), .O(status_ram_wr_addr_ns[4])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_2 (.I0(\read_fifo.fifo_out_data_r_reg[7] [4]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[3]), .O(status_ram_wr_addr_ns[3])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_3 (.I0(\read_fifo.fifo_out_data_r_reg[7] [3]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[2]), .O(status_ram_wr_addr_ns[2])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_4 (.I0(\read_fifo.fifo_out_data_r_reg[7] [2]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[1]), .O(status_ram_wr_addr_ns[1])); LUT3 #( .INIT(8'hB8)) \not_strict_mode.status_ram.RAM32M0_i_5 (.I0(\read_fifo.fifo_out_data_r_reg[7] [1]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[0]), .O(status_ram_wr_addr_ns[0])); FDRE \not_strict_mode.status_ram.rd_buf_we_r1_reg (.C(CLK), .CE(1'b1), .D(rd_buf_we), .Q(rd_buf_we_r1), .R(1'b0)); FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[0]), .Q(status_ram_wr_addr_r[0]), .R(1'b0)); FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[1]), .Q(status_ram_wr_addr_r[1]), .R(1'b0)); FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[2]), .Q(status_ram_wr_addr_r[2]), .R(1'b0)); FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[3]), .Q(status_ram_wr_addr_r[3]), .R(1'b0)); FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4] (.C(CLK), .CE(1'b1), .D(status_ram_wr_addr_ns[4]), .Q(status_ram_wr_addr_r[4]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1509" *) LUT4 #( .INIT(16'h404C)) \not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1 (.I0(wr_status_r1), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(\read_fifo.fifo_out_data_r_reg[7] [0]), .I3(wr_status), .O(status_ram_wr_data_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1509" *) LUT2 #( .INIT(4'h8)) \not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1 (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I1(\read_fifo.fifo_out_data_r_reg[7] [6]), .O(status_ram_wr_data_ns[1])); FDRE \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0] (.C(CLK), .CE(1'b1), .D(status_ram_wr_data_ns[0]), .Q(status_ram_wr_data_r[0]), .R(1'b0)); FDRE \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1] (.C(CLK), .CE(1'b1), .D(status_ram_wr_data_ns[1]), .Q(status_ram_wr_data_r[1]), .R(1'b0)); FDRE \not_strict_mode.status_ram.wr_status_r1_reg (.C(CLK), .CE(1'b1), .D(wr_status), .Q(wr_status_r1), .R(1'b0)); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_2 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [1]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[1]), .O(pointer_wr_data[1])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_3 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [0]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[0]), .O(pointer_wr_data[0])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_4 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [3]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[3]), .O(ADDRD[3])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_5 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [2]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[2]), .O(ADDRD[2])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_6 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [1]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[1]), .O(ADDRD[1])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[0].RAM32M0_i_7 (.I0(\read_data_indx.rd_data_indx_r_reg[3] [0]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[0]), .O(ADDRD[0])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[1].RAM32M0_i_1 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [3]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[3]), .O(pointer_wr_data[3])); LUT3 #( .INIT(8'hB8)) \pointer_ram.rams[1].RAM32M0_i_2 (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [2]), .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I2(Q[2]), .O(pointer_wr_data[2])); LUT6 #( .INIT(64'hFFFFFFFF80000000)) \rd_buf_indx.ram_init_done_r_lcl_i_1 (.I0(Q[3]), .I1(Q[4]), .I2(\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ), .I3(Q[2]), .I4(Q[1]), .I5(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ), .O(ram_init_done_ns)); LUT2 #( .INIT(4'h2)) \rd_buf_indx.ram_init_done_r_lcl_i_2 (.I0(Q[0]), .I1(reset_reg), .O(\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1508" *) LUT2 #( .INIT(4'h2)) \rd_buf_indx.ram_init_done_r_lcl_i_3 (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I1(reset_reg), .O(\rd_buf_indx.ram_init_done_r_lcl_reg_0 )); (* syn_maxfan = "10" *) FDRE \rd_buf_indx.ram_init_done_r_lcl_reg (.C(CLK), .CE(1'b1), .D(ram_init_done_ns), .Q(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .R(1'b0)); LUT6 #( .INIT(64'h000000001400EBFF)) \rd_buf_indx.rd_buf_indx_r[0]_i_1 (.I0(bypass__0), .I1(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I2(rd_status), .I3(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I4(Q[0]), .I5(reset_reg), .O(rd_buf_indx_ns[0])); (* SOFT_HLUTNM = "soft_lutpair1510" *) LUT3 #( .INIT(8'h09)) \rd_buf_indx.rd_buf_indx_r[1]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ), .I1(Q[1]), .I2(reset_reg), .O(rd_buf_indx_ns[1])); (* SOFT_HLUTNM = "soft_lutpair1505" *) LUT5 #( .INIT(32'h0028FFFF)) \rd_buf_indx.rd_buf_indx_r[1]_i_2 (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .I1(rd_status), .I2(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I3(bypass__0), .I4(Q[0]), .O(\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1510" *) LUT3 #( .INIT(8'h06)) \rd_buf_indx.rd_buf_indx_r[2]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I1(Q[2]), .I2(reset_reg), .O(rd_buf_indx_ns[2])); (* SOFT_HLUTNM = "soft_lutpair1504" *) LUT4 #( .INIT(16'h0078)) \rd_buf_indx.rd_buf_indx_r[3]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(reset_reg), .O(rd_buf_indx_ns[3])); (* SOFT_HLUTNM = "soft_lutpair1504" *) LUT5 #( .INIT(32'h00007F80)) \rd_buf_indx.rd_buf_indx_r[4]_i_1 (.I0(Q[3]), .I1(Q[2]), .I2(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I3(Q[4]), .I4(reset_reg), .O(rd_buf_indx_ns[4])); LUT6 #( .INIT(64'h000000007FFF8000)) \rd_buf_indx.rd_buf_indx_r[5]_i_1 (.I0(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I5(reset_reg), .O(rd_buf_indx_ns[5])); LUT6 #( .INIT(64'h8880808888888888)) \rd_buf_indx.rd_buf_indx_r[5]_i_2 (.I0(Q[1]), .I1(Q[0]), .I2(bypass__0), .I3(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .I4(rd_status), .I5(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ), .O(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 )); FDRE \rd_buf_indx.rd_buf_indx_r_reg[0] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[0]), .Q(Q[0]), .R(1'b0)); FDRE \rd_buf_indx.rd_buf_indx_r_reg[1] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[1]), .Q(Q[1]), .R(1'b0)); FDRE \rd_buf_indx.rd_buf_indx_r_reg[2] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[2]), .Q(Q[2]), .R(1'b0)); FDRE \rd_buf_indx.rd_buf_indx_r_reg[3] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[3]), .Q(Q[3]), .R(1'b0)); FDRE \rd_buf_indx.rd_buf_indx_r_reg[4] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[4]), .Q(Q[4]), .R(1'b0)); FDRE \rd_buf_indx.rd_buf_indx_r_reg[5] (.C(CLK), .CE(1'b1), .D(rd_buf_indx_ns[5]), .Q(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ), .R(1'b0)); endmodule module ddr3_if_mig_7series_v4_0_ui_top (\not_strict_mode.app_rd_data_end_reg , Q, DOA, DOB, DOC, \not_strict_mode.app_rd_data_reg[11] , \not_strict_mode.app_rd_data_reg[9] , \not_strict_mode.app_rd_data_reg[7] , \not_strict_mode.app_rd_data_reg[17] , \not_strict_mode.app_rd_data_reg[15] , \not_strict_mode.app_rd_data_reg[13] , \not_strict_mode.app_rd_data_reg[23] , \not_strict_mode.app_rd_data_reg[21] , \not_strict_mode.app_rd_data_reg[19] , \not_strict_mode.app_rd_data_reg[29] , \not_strict_mode.app_rd_data_reg[27] , \not_strict_mode.app_rd_data_reg[25] , \not_strict_mode.app_rd_data_reg[35] , \not_strict_mode.app_rd_data_reg[33] , \not_strict_mode.app_rd_data_reg[31] , \not_strict_mode.app_rd_data_reg[41] , \not_strict_mode.app_rd_data_reg[39] , \not_strict_mode.app_rd_data_reg[37] , \not_strict_mode.app_rd_data_reg[47] , \not_strict_mode.app_rd_data_reg[45] , \not_strict_mode.app_rd_data_reg[43] , \not_strict_mode.app_rd_data_reg[53] , \not_strict_mode.app_rd_data_reg[51] , \not_strict_mode.app_rd_data_reg[49] , \not_strict_mode.app_rd_data_reg[59] , \not_strict_mode.app_rd_data_reg[57] , \not_strict_mode.app_rd_data_reg[55] , \not_strict_mode.app_rd_data_reg[65] , \not_strict_mode.app_rd_data_reg[63] , \not_strict_mode.app_rd_data_reg[61] , \not_strict_mode.app_rd_data_reg[71] , \not_strict_mode.app_rd_data_reg[69] , \not_strict_mode.app_rd_data_reg[67] , \not_strict_mode.app_rd_data_reg[77] , \not_strict_mode.app_rd_data_reg[75] , \not_strict_mode.app_rd_data_reg[73] , \not_strict_mode.app_rd_data_reg[83] , \not_strict_mode.app_rd_data_reg[81] , \not_strict_mode.app_rd_data_reg[79] , \not_strict_mode.app_rd_data_reg[89] , \not_strict_mode.app_rd_data_reg[87] , \not_strict_mode.app_rd_data_reg[85] , \not_strict_mode.app_rd_data_reg[95] , \not_strict_mode.app_rd_data_reg[93] , \not_strict_mode.app_rd_data_reg[91] , \not_strict_mode.app_rd_data_reg[101] , \not_strict_mode.app_rd_data_reg[99] , \not_strict_mode.app_rd_data_reg[97] , \not_strict_mode.app_rd_data_reg[107] , \not_strict_mode.app_rd_data_reg[105] , \not_strict_mode.app_rd_data_reg[103] , \not_strict_mode.app_rd_data_reg[113] , \not_strict_mode.app_rd_data_reg[111] , \not_strict_mode.app_rd_data_reg[109] , \not_strict_mode.app_rd_data_reg[119] , \not_strict_mode.app_rd_data_reg[117] , \not_strict_mode.app_rd_data_reg[115] , \not_strict_mode.app_rd_data_reg[125] , \not_strict_mode.app_rd_data_reg[123] , \not_strict_mode.app_rd_data_reg[121] , \not_strict_mode.app_rd_data_reg[131] , \not_strict_mode.app_rd_data_reg[129] , \not_strict_mode.app_rd_data_reg[127] , \not_strict_mode.app_rd_data_reg[137] , \not_strict_mode.app_rd_data_reg[135] , \not_strict_mode.app_rd_data_reg[133] , \not_strict_mode.app_rd_data_reg[143] , \not_strict_mode.app_rd_data_reg[141] , \not_strict_mode.app_rd_data_reg[139] , \not_strict_mode.app_rd_data_reg[149] , \not_strict_mode.app_rd_data_reg[147] , \not_strict_mode.app_rd_data_reg[145] , \not_strict_mode.app_rd_data_reg[155] , \not_strict_mode.app_rd_data_reg[153] , \not_strict_mode.app_rd_data_reg[151] , \not_strict_mode.app_rd_data_reg[161] , \not_strict_mode.app_rd_data_reg[159] , \not_strict_mode.app_rd_data_reg[157] , \not_strict_mode.app_rd_data_reg[167] , \not_strict_mode.app_rd_data_reg[165] , \not_strict_mode.app_rd_data_reg[163] , \not_strict_mode.app_rd_data_reg[173] , \not_strict_mode.app_rd_data_reg[171] , \not_strict_mode.app_rd_data_reg[169] , \not_strict_mode.app_rd_data_reg[179] , \not_strict_mode.app_rd_data_reg[177] , \not_strict_mode.app_rd_data_reg[175] , \not_strict_mode.app_rd_data_reg[185] , \not_strict_mode.app_rd_data_reg[183] , \not_strict_mode.app_rd_data_reg[181] , \not_strict_mode.app_rd_data_reg[191] , \not_strict_mode.app_rd_data_reg[189] , \not_strict_mode.app_rd_data_reg[187] , \not_strict_mode.app_rd_data_reg[197] , \not_strict_mode.app_rd_data_reg[195] , \not_strict_mode.app_rd_data_reg[193] , \not_strict_mode.app_rd_data_reg[203] , \not_strict_mode.app_rd_data_reg[201] , \not_strict_mode.app_rd_data_reg[199] , \not_strict_mode.app_rd_data_reg[209] , \not_strict_mode.app_rd_data_reg[207] , \not_strict_mode.app_rd_data_reg[205] , \not_strict_mode.app_rd_data_reg[215] , \not_strict_mode.app_rd_data_reg[213] , \not_strict_mode.app_rd_data_reg[211] , \not_strict_mode.app_rd_data_reg[221] , \not_strict_mode.app_rd_data_reg[219] , \not_strict_mode.app_rd_data_reg[217] , \not_strict_mode.app_rd_data_reg[227] , \not_strict_mode.app_rd_data_reg[225] , \not_strict_mode.app_rd_data_reg[223] , \not_strict_mode.app_rd_data_reg[233] , \not_strict_mode.app_rd_data_reg[231] , \not_strict_mode.app_rd_data_reg[229] , \not_strict_mode.app_rd_data_reg[239] , \not_strict_mode.app_rd_data_reg[237] , \not_strict_mode.app_rd_data_reg[235] , \not_strict_mode.app_rd_data_reg[245] , \not_strict_mode.app_rd_data_reg[243] , \not_strict_mode.app_rd_data_reg[241] , \not_strict_mode.app_rd_data_reg[251] , \not_strict_mode.app_rd_data_reg[249] , \not_strict_mode.app_rd_data_reg[247] , \not_strict_mode.app_rd_data_reg[255] , \not_strict_mode.app_rd_data_reg[253] , app_rdy, app_en_r1, app_hi_pri_r2, hi_priority, ram_init_done_r, app_wdf_rdy, app_rd_data_valid, \app_cmd_r2_reg[0] , rb_hit_busy_r_reg, \req_bank_r_lcl_reg[2] , rb_hit_busy_r_reg_0, rb_hit_busy_r_reg_1, rb_hit_busy_r_reg_2, use_addr, \req_data_buf_addr_r_reg[4] , \app_cmd_r2_reg[1] , \req_row_r_lcl_reg[14] , \req_col_r_reg[9] , \my_empty_reg[7] , \s_axi_rdata[255] , CLK, pointer_we, \cmd_pipe_plus.wr_data_addr_reg[3] , rd_buf_we, DIA, DIB, DIC, \read_fifo.fifo_out_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] , \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] , app_en_ns1, E, app_rd_data_end_ns, reset_reg, mc_app_cmd, req_bank_r, mc_app_wdf_wren_reg, w_cmd_rdy, D, mc_app_wdf_mask_reg, wready_reg_rep__1, mc_app_wdf_data_reg, accept_ns, bypass__0, app_rdy_r_reg, \axaddr_incr_reg[29] , app_wdf_data, app_wdf_mask, \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ); output [0:0]\not_strict_mode.app_rd_data_end_reg ; output [4:0]Q; output [1:0]DOA; output [1:0]DOB; output [1:0]DOC; output [1:0]\not_strict_mode.app_rd_data_reg[11] ; output [1:0]\not_strict_mode.app_rd_data_reg[9] ; output [1:0]\not_strict_mode.app_rd_data_reg[7] ; output [1:0]\not_strict_mode.app_rd_data_reg[17] ; output [1:0]\not_strict_mode.app_rd_data_reg[15] ; output [1:0]\not_strict_mode.app_rd_data_reg[13] ; output [1:0]\not_strict_mode.app_rd_data_reg[23] ; output [1:0]\not_strict_mode.app_rd_data_reg[21] ; output [1:0]\not_strict_mode.app_rd_data_reg[19] ; output [1:0]\not_strict_mode.app_rd_data_reg[29] ; output [1:0]\not_strict_mode.app_rd_data_reg[27] ; output [1:0]\not_strict_mode.app_rd_data_reg[25] ; output [1:0]\not_strict_mode.app_rd_data_reg[35] ; output [1:0]\not_strict_mode.app_rd_data_reg[33] ; output [1:0]\not_strict_mode.app_rd_data_reg[31] ; output [1:0]\not_strict_mode.app_rd_data_reg[41] ; output [1:0]\not_strict_mode.app_rd_data_reg[39] ; output [1:0]\not_strict_mode.app_rd_data_reg[37] ; output [1:0]\not_strict_mode.app_rd_data_reg[47] ; output [1:0]\not_strict_mode.app_rd_data_reg[45] ; output [1:0]\not_strict_mode.app_rd_data_reg[43] ; output [1:0]\not_strict_mode.app_rd_data_reg[53] ; output [1:0]\not_strict_mode.app_rd_data_reg[51] ; output [1:0]\not_strict_mode.app_rd_data_reg[49] ; output [1:0]\not_strict_mode.app_rd_data_reg[59] ; output [1:0]\not_strict_mode.app_rd_data_reg[57] ; output [1:0]\not_strict_mode.app_rd_data_reg[55] ; output [1:0]\not_strict_mode.app_rd_data_reg[65] ; output [1:0]\not_strict_mode.app_rd_data_reg[63] ; output [1:0]\not_strict_mode.app_rd_data_reg[61] ; output [1:0]\not_strict_mode.app_rd_data_reg[71] ; output [1:0]\not_strict_mode.app_rd_data_reg[69] ; output [1:0]\not_strict_mode.app_rd_data_reg[67] ; output [1:0]\not_strict_mode.app_rd_data_reg[77] ; output [1:0]\not_strict_mode.app_rd_data_reg[75] ; output [1:0]\not_strict_mode.app_rd_data_reg[73] ; output [1:0]\not_strict_mode.app_rd_data_reg[83] ; output [1:0]\not_strict_mode.app_rd_data_reg[81] ; output [1:0]\not_strict_mode.app_rd_data_reg[79] ; output [1:0]\not_strict_mode.app_rd_data_reg[89] ; output [1:0]\not_strict_mode.app_rd_data_reg[87] ; output [1:0]\not_strict_mode.app_rd_data_reg[85] ; output [1:0]\not_strict_mode.app_rd_data_reg[95] ; output [1:0]\not_strict_mode.app_rd_data_reg[93] ; output [1:0]\not_strict_mode.app_rd_data_reg[91] ; output [1:0]\not_strict_mode.app_rd_data_reg[101] ; output [1:0]\not_strict_mode.app_rd_data_reg[99] ; output [1:0]\not_strict_mode.app_rd_data_reg[97] ; output [1:0]\not_strict_mode.app_rd_data_reg[107] ; output [1:0]\not_strict_mode.app_rd_data_reg[105] ; output [1:0]\not_strict_mode.app_rd_data_reg[103] ; output [1:0]\not_strict_mode.app_rd_data_reg[113] ; output [1:0]\not_strict_mode.app_rd_data_reg[111] ; output [1:0]\not_strict_mode.app_rd_data_reg[109] ; output [1:0]\not_strict_mode.app_rd_data_reg[119] ; output [1:0]\not_strict_mode.app_rd_data_reg[117] ; output [1:0]\not_strict_mode.app_rd_data_reg[115] ; output [1:0]\not_strict_mode.app_rd_data_reg[125] ; output [1:0]\not_strict_mode.app_rd_data_reg[123] ; output [1:0]\not_strict_mode.app_rd_data_reg[121] ; output [1:0]\not_strict_mode.app_rd_data_reg[131] ; output [1:0]\not_strict_mode.app_rd_data_reg[129] ; output [1:0]\not_strict_mode.app_rd_data_reg[127] ; output [1:0]\not_strict_mode.app_rd_data_reg[137] ; output [1:0]\not_strict_mode.app_rd_data_reg[135] ; output [1:0]\not_strict_mode.app_rd_data_reg[133] ; output [1:0]\not_strict_mode.app_rd_data_reg[143] ; output [1:0]\not_strict_mode.app_rd_data_reg[141] ; output [1:0]\not_strict_mode.app_rd_data_reg[139] ; output [1:0]\not_strict_mode.app_rd_data_reg[149] ; output [1:0]\not_strict_mode.app_rd_data_reg[147] ; output [1:0]\not_strict_mode.app_rd_data_reg[145] ; output [1:0]\not_strict_mode.app_rd_data_reg[155] ; output [1:0]\not_strict_mode.app_rd_data_reg[153] ; output [1:0]\not_strict_mode.app_rd_data_reg[151] ; output [1:0]\not_strict_mode.app_rd_data_reg[161] ; output [1:0]\not_strict_mode.app_rd_data_reg[159] ; output [1:0]\not_strict_mode.app_rd_data_reg[157] ; output [1:0]\not_strict_mode.app_rd_data_reg[167] ; output [1:0]\not_strict_mode.app_rd_data_reg[165] ; output [1:0]\not_strict_mode.app_rd_data_reg[163] ; output [1:0]\not_strict_mode.app_rd_data_reg[173] ; output [1:0]\not_strict_mode.app_rd_data_reg[171] ; output [1:0]\not_strict_mode.app_rd_data_reg[169] ; output [1:0]\not_strict_mode.app_rd_data_reg[179] ; output [1:0]\not_strict_mode.app_rd_data_reg[177] ; output [1:0]\not_strict_mode.app_rd_data_reg[175] ; output [1:0]\not_strict_mode.app_rd_data_reg[185] ; output [1:0]\not_strict_mode.app_rd_data_reg[183] ; output [1:0]\not_strict_mode.app_rd_data_reg[181] ; output [1:0]\not_strict_mode.app_rd_data_reg[191] ; output [1:0]\not_strict_mode.app_rd_data_reg[189] ; output [1:0]\not_strict_mode.app_rd_data_reg[187] ; output [1:0]\not_strict_mode.app_rd_data_reg[197] ; output [1:0]\not_strict_mode.app_rd_data_reg[195] ; output [1:0]\not_strict_mode.app_rd_data_reg[193] ; output [1:0]\not_strict_mode.app_rd_data_reg[203] ; output [1:0]\not_strict_mode.app_rd_data_reg[201] ; output [1:0]\not_strict_mode.app_rd_data_reg[199] ; output [1:0]\not_strict_mode.app_rd_data_reg[209] ; output [1:0]\not_strict_mode.app_rd_data_reg[207] ; output [1:0]\not_strict_mode.app_rd_data_reg[205] ; output [1:0]\not_strict_mode.app_rd_data_reg[215] ; output [1:0]\not_strict_mode.app_rd_data_reg[213] ; output [1:0]\not_strict_mode.app_rd_data_reg[211] ; output [1:0]\not_strict_mode.app_rd_data_reg[221] ; output [1:0]\not_strict_mode.app_rd_data_reg[219] ; output [1:0]\not_strict_mode.app_rd_data_reg[217] ; output [1:0]\not_strict_mode.app_rd_data_reg[227] ; output [1:0]\not_strict_mode.app_rd_data_reg[225] ; output [1:0]\not_strict_mode.app_rd_data_reg[223] ; output [1:0]\not_strict_mode.app_rd_data_reg[233] ; output [1:0]\not_strict_mode.app_rd_data_reg[231] ; output [1:0]\not_strict_mode.app_rd_data_reg[229] ; output [1:0]\not_strict_mode.app_rd_data_reg[239] ; output [1:0]\not_strict_mode.app_rd_data_reg[237] ; output [1:0]\not_strict_mode.app_rd_data_reg[235] ; output [1:0]\not_strict_mode.app_rd_data_reg[245] ; output [1:0]\not_strict_mode.app_rd_data_reg[243] ; output [1:0]\not_strict_mode.app_rd_data_reg[241] ; output [1:0]\not_strict_mode.app_rd_data_reg[251] ; output [1:0]\not_strict_mode.app_rd_data_reg[249] ; output [1:0]\not_strict_mode.app_rd_data_reg[247] ; output [1:0]\not_strict_mode.app_rd_data_reg[255] ; output [1:0]\not_strict_mode.app_rd_data_reg[253] ; output app_rdy; output app_en_r1; output app_hi_pri_r2; output hi_priority; output ram_init_done_r; output app_wdf_rdy; output app_rd_data_valid; output \app_cmd_r2_reg[0] ; output rb_hit_busy_r_reg; output [2:0]\req_bank_r_lcl_reg[2] ; output rb_hit_busy_r_reg_0; output rb_hit_busy_r_reg_1; output rb_hit_busy_r_reg_2; output use_addr; output [4:0]\req_data_buf_addr_r_reg[4] ; output [0:0]\app_cmd_r2_reg[1] ; output [14:0]\req_row_r_lcl_reg[14] ; output [6:0]\req_col_r_reg[9] ; output [287:0]\my_empty_reg[7] ; output [255:0]\s_axi_rdata[255] ; input CLK; input pointer_we; input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; input rd_buf_we; input [1:0]DIA; input [1:0]DIB; input [1:0]DIC; input [6:0]\read_fifo.fifo_out_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; input app_en_ns1; input [0:0]E; input app_rd_data_end_ns; input reset_reg; input [0:0]mc_app_cmd; input [11:0]req_bank_r; input mc_app_wdf_wren_reg; input w_cmd_rdy; input [31:0]D; input [31:0]mc_app_wdf_mask_reg; input [255:0]wready_reg_rep__1; input [255:0]mc_app_wdf_data_reg; input accept_ns; input bypass__0; input [0:0]app_rdy_r_reg; input [24:0]\axaddr_incr_reg[29] ; input [255:0]app_wdf_data; input [31:0]app_wdf_mask; input [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire CLK; wire [31:0]D; wire [1:0]DIA; wire [1:0]DIB; wire [1:0]DIC; wire [1:0]DOA; wire [1:0]DOB; wire [1:0]DOC; wire [0:0]E; wire [4:0]Q; wire accept_ns; wire \app_cmd_r2_reg[0] ; wire [0:0]\app_cmd_r2_reg[1] ; wire app_en_ns1; wire app_en_r1; wire app_hi_pri_r2; wire app_rd_data_end_ns; wire app_rd_data_valid; wire app_rdy; wire app_rdy_ns; wire [0:0]app_rdy_r_reg; wire [255:0]app_wdf_data; wire [31:0]app_wdf_mask; wire app_wdf_rdy; wire [24:0]\axaddr_incr_reg[29] ; wire bypass__0; wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ; wire [255:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ; wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ; wire hi_priority; wire [0:0]mc_app_cmd; wire [255:0]mc_app_wdf_data_reg; wire [31:0]mc_app_wdf_mask_reg; wire mc_app_wdf_wren_reg; wire [287:0]\my_empty_reg[7] ; wire [0:0]\not_strict_mode.app_rd_data_end_reg ; wire [1:0]\not_strict_mode.app_rd_data_reg[101] ; wire [1:0]\not_strict_mode.app_rd_data_reg[103] ; wire [1:0]\not_strict_mode.app_rd_data_reg[105] ; wire [1:0]\not_strict_mode.app_rd_data_reg[107] ; wire [1:0]\not_strict_mode.app_rd_data_reg[109] ; wire [1:0]\not_strict_mode.app_rd_data_reg[111] ; wire [1:0]\not_strict_mode.app_rd_data_reg[113] ; wire [1:0]\not_strict_mode.app_rd_data_reg[115] ; wire [1:0]\not_strict_mode.app_rd_data_reg[117] ; wire [1:0]\not_strict_mode.app_rd_data_reg[119] ; wire [1:0]\not_strict_mode.app_rd_data_reg[11] ; wire [1:0]\not_strict_mode.app_rd_data_reg[121] ; wire [1:0]\not_strict_mode.app_rd_data_reg[123] ; wire [1:0]\not_strict_mode.app_rd_data_reg[125] ; wire [1:0]\not_strict_mode.app_rd_data_reg[127] ; wire [1:0]\not_strict_mode.app_rd_data_reg[129] ; wire [1:0]\not_strict_mode.app_rd_data_reg[131] ; wire [1:0]\not_strict_mode.app_rd_data_reg[133] ; wire [1:0]\not_strict_mode.app_rd_data_reg[135] ; wire [1:0]\not_strict_mode.app_rd_data_reg[137] ; wire [1:0]\not_strict_mode.app_rd_data_reg[139] ; wire [1:0]\not_strict_mode.app_rd_data_reg[13] ; wire [1:0]\not_strict_mode.app_rd_data_reg[141] ; wire [1:0]\not_strict_mode.app_rd_data_reg[143] ; wire [1:0]\not_strict_mode.app_rd_data_reg[145] ; wire [1:0]\not_strict_mode.app_rd_data_reg[147] ; wire [1:0]\not_strict_mode.app_rd_data_reg[149] ; wire [1:0]\not_strict_mode.app_rd_data_reg[151] ; wire [1:0]\not_strict_mode.app_rd_data_reg[153] ; wire [1:0]\not_strict_mode.app_rd_data_reg[155] ; wire [1:0]\not_strict_mode.app_rd_data_reg[157] ; wire [1:0]\not_strict_mode.app_rd_data_reg[159] ; wire [1:0]\not_strict_mode.app_rd_data_reg[15] ; wire [1:0]\not_strict_mode.app_rd_data_reg[161] ; wire [1:0]\not_strict_mode.app_rd_data_reg[163] ; wire [1:0]\not_strict_mode.app_rd_data_reg[165] ; wire [1:0]\not_strict_mode.app_rd_data_reg[167] ; wire [1:0]\not_strict_mode.app_rd_data_reg[169] ; wire [1:0]\not_strict_mode.app_rd_data_reg[171] ; wire [1:0]\not_strict_mode.app_rd_data_reg[173] ; wire [1:0]\not_strict_mode.app_rd_data_reg[175] ; wire [1:0]\not_strict_mode.app_rd_data_reg[177] ; wire [1:0]\not_strict_mode.app_rd_data_reg[179] ; wire [1:0]\not_strict_mode.app_rd_data_reg[17] ; wire [1:0]\not_strict_mode.app_rd_data_reg[181] ; wire [1:0]\not_strict_mode.app_rd_data_reg[183] ; wire [1:0]\not_strict_mode.app_rd_data_reg[185] ; wire [1:0]\not_strict_mode.app_rd_data_reg[187] ; wire [1:0]\not_strict_mode.app_rd_data_reg[189] ; wire [1:0]\not_strict_mode.app_rd_data_reg[191] ; wire [1:0]\not_strict_mode.app_rd_data_reg[193] ; wire [1:0]\not_strict_mode.app_rd_data_reg[195] ; wire [1:0]\not_strict_mode.app_rd_data_reg[197] ; wire [1:0]\not_strict_mode.app_rd_data_reg[199] ; wire [1:0]\not_strict_mode.app_rd_data_reg[19] ; wire [1:0]\not_strict_mode.app_rd_data_reg[201] ; wire [1:0]\not_strict_mode.app_rd_data_reg[203] ; wire [1:0]\not_strict_mode.app_rd_data_reg[205] ; wire [1:0]\not_strict_mode.app_rd_data_reg[207] ; wire [1:0]\not_strict_mode.app_rd_data_reg[209] ; wire [1:0]\not_strict_mode.app_rd_data_reg[211] ; wire [1:0]\not_strict_mode.app_rd_data_reg[213] ; wire [1:0]\not_strict_mode.app_rd_data_reg[215] ; wire [1:0]\not_strict_mode.app_rd_data_reg[217] ; wire [1:0]\not_strict_mode.app_rd_data_reg[219] ; wire [1:0]\not_strict_mode.app_rd_data_reg[21] ; wire [1:0]\not_strict_mode.app_rd_data_reg[221] ; wire [1:0]\not_strict_mode.app_rd_data_reg[223] ; wire [1:0]\not_strict_mode.app_rd_data_reg[225] ; wire [1:0]\not_strict_mode.app_rd_data_reg[227] ; wire [1:0]\not_strict_mode.app_rd_data_reg[229] ; wire [1:0]\not_strict_mode.app_rd_data_reg[231] ; wire [1:0]\not_strict_mode.app_rd_data_reg[233] ; wire [1:0]\not_strict_mode.app_rd_data_reg[235] ; wire [1:0]\not_strict_mode.app_rd_data_reg[237] ; wire [1:0]\not_strict_mode.app_rd_data_reg[239] ; wire [1:0]\not_strict_mode.app_rd_data_reg[23] ; wire [1:0]\not_strict_mode.app_rd_data_reg[241] ; wire [1:0]\not_strict_mode.app_rd_data_reg[243] ; wire [1:0]\not_strict_mode.app_rd_data_reg[245] ; wire [1:0]\not_strict_mode.app_rd_data_reg[247] ; wire [1:0]\not_strict_mode.app_rd_data_reg[249] ; wire [1:0]\not_strict_mode.app_rd_data_reg[251] ; wire [1:0]\not_strict_mode.app_rd_data_reg[253] ; wire [1:0]\not_strict_mode.app_rd_data_reg[255] ; wire [1:0]\not_strict_mode.app_rd_data_reg[25] ; wire [1:0]\not_strict_mode.app_rd_data_reg[27] ; wire [1:0]\not_strict_mode.app_rd_data_reg[29] ; wire [1:0]\not_strict_mode.app_rd_data_reg[31] ; wire [1:0]\not_strict_mode.app_rd_data_reg[33] ; wire [1:0]\not_strict_mode.app_rd_data_reg[35] ; wire [1:0]\not_strict_mode.app_rd_data_reg[37] ; wire [1:0]\not_strict_mode.app_rd_data_reg[39] ; wire [1:0]\not_strict_mode.app_rd_data_reg[41] ; wire [1:0]\not_strict_mode.app_rd_data_reg[43] ; wire [1:0]\not_strict_mode.app_rd_data_reg[45] ; wire [1:0]\not_strict_mode.app_rd_data_reg[47] ; wire [1:0]\not_strict_mode.app_rd_data_reg[49] ; wire [1:0]\not_strict_mode.app_rd_data_reg[51] ; wire [1:0]\not_strict_mode.app_rd_data_reg[53] ; wire [1:0]\not_strict_mode.app_rd_data_reg[55] ; wire [1:0]\not_strict_mode.app_rd_data_reg[57] ; wire [1:0]\not_strict_mode.app_rd_data_reg[59] ; wire [1:0]\not_strict_mode.app_rd_data_reg[61] ; wire [1:0]\not_strict_mode.app_rd_data_reg[63] ; wire [1:0]\not_strict_mode.app_rd_data_reg[65] ; wire [1:0]\not_strict_mode.app_rd_data_reg[67] ; wire [1:0]\not_strict_mode.app_rd_data_reg[69] ; wire [1:0]\not_strict_mode.app_rd_data_reg[71] ; wire [1:0]\not_strict_mode.app_rd_data_reg[73] ; wire [1:0]\not_strict_mode.app_rd_data_reg[75] ; wire [1:0]\not_strict_mode.app_rd_data_reg[77] ; wire [1:0]\not_strict_mode.app_rd_data_reg[79] ; wire [1:0]\not_strict_mode.app_rd_data_reg[7] ; wire [1:0]\not_strict_mode.app_rd_data_reg[81] ; wire [1:0]\not_strict_mode.app_rd_data_reg[83] ; wire [1:0]\not_strict_mode.app_rd_data_reg[85] ; wire [1:0]\not_strict_mode.app_rd_data_reg[87] ; wire [1:0]\not_strict_mode.app_rd_data_reg[89] ; wire [1:0]\not_strict_mode.app_rd_data_reg[91] ; wire [1:0]\not_strict_mode.app_rd_data_reg[93] ; wire [1:0]\not_strict_mode.app_rd_data_reg[95] ; wire [1:0]\not_strict_mode.app_rd_data_reg[97] ; wire [1:0]\not_strict_mode.app_rd_data_reg[99] ; wire [1:0]\not_strict_mode.app_rd_data_reg[9] ; wire [1:0]occ_cnt_r; wire [0:0]p_0_in; wire pointer_we; wire [3:0]pointer_wr_addr; wire [3:0]pointer_wr_data; wire ram_init_done_r; wire rb_hit_busy_r_reg; wire rb_hit_busy_r_reg_0; wire rb_hit_busy_r_reg_1; wire rb_hit_busy_r_reg_2; wire rd_accepted; wire rd_buf_we; wire [4:0]rd_data_buf_addr_r; wire [3:0]\read_data_indx.rd_data_indx_r_reg__0 ; wire [6:0]\read_fifo.fifo_out_data_r_reg[7] ; wire [11:0]req_bank_r; wire [2:0]\req_bank_r_lcl_reg[2] ; wire [6:0]\req_col_r_reg[9] ; wire [4:0]\req_data_buf_addr_r_reg[4] ; wire [14:0]\req_row_r_lcl_reg[14] ; wire reset_reg; wire [255:0]\s_axi_rdata[255] ; wire ui_cmd0_n_12; wire ui_cmd0_n_13; wire ui_cmd0_n_15; wire ui_rd_data0_n_264; wire ui_rd_data0_n_272; wire use_addr; wire w_cmd_rdy; wire wr_accepted; wire [3:0]wr_data_buf_addr; wire [1:0]wr_req_cnt_r; wire [255:0]wready_reg_rep__1; ddr3_if_mig_7series_v4_0_ui_cmd ui_cmd0 (.CLK(CLK), .E(app_rdy), .Q(occ_cnt_r), .\app_cmd_r2_reg[0]_0 (\app_cmd_r2_reg[0] ), .\app_cmd_r2_reg[1]_0 (\app_cmd_r2_reg[1] ), .app_en_ns1(app_en_ns1), .app_en_r1(app_en_r1), .app_hi_pri_r2(app_hi_pri_r2), .app_rdy_ns(app_rdy_ns), .app_rdy_r_reg_0(app_rdy_r_reg), .\axaddr_incr_reg[29] (\axaddr_incr_reg[29] ), .hi_priority(hi_priority), .mc_app_cmd(mc_app_cmd), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (rd_data_buf_addr_r), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] (ui_cmd0_n_15), .p_0_in(p_0_in), .rb_hit_busy_r_reg(rb_hit_busy_r_reg), .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0), .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1), .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2), .rd_accepted(rd_accepted), .req_bank_r(req_bank_r), .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[2] [0]), .\req_bank_r_lcl_reg[1] (\req_bank_r_lcl_reg[2] [1]), .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] [2]), .\req_col_r_reg[9] (\req_col_r_reg[9] ), .\req_data_buf_addr_r_reg[4] (\req_data_buf_addr_r_reg[4] ), .\req_row_r_lcl_reg[14] (\req_row_r_lcl_reg[14] ), .reset_reg(reset_reg), .use_addr(use_addr), .wr_accepted(wr_accepted), .wr_data_buf_addr(wr_data_buf_addr), .wr_req_cnt_r(wr_req_cnt_r), .\wr_req_counter.wr_req_cnt_r_reg[3] (ui_cmd0_n_13), .\wr_req_counter.wr_req_cnt_r_reg[4] (ui_cmd0_n_12)); ddr3_if_mig_7series_v4_0_ui_rd_data ui_rd_data0 (.ADDRD(pointer_wr_addr), .CLK(CLK), .D(ui_rd_data0_n_264), .DIA(DIA), .DIB(DIB), .DIC(DIC), .DOA(DOA), .DOB(DOB), .DOC(DOC), .Q(Q), .app_rd_data_end_ns(app_rd_data_end_ns), .app_rd_data_valid(app_rd_data_valid), .bypass__0(bypass__0), .\cmd_pipe_plus.wr_data_addr_reg[3] (\cmd_pipe_plus.wr_data_addr_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ), .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ), .\not_strict_mode.app_rd_data_end_reg_0 (\not_strict_mode.app_rd_data_end_reg ), .\not_strict_mode.app_rd_data_reg[101]_0 (\not_strict_mode.app_rd_data_reg[101] ), .\not_strict_mode.app_rd_data_reg[103]_0 (\not_strict_mode.app_rd_data_reg[103] ), .\not_strict_mode.app_rd_data_reg[105]_0 (\not_strict_mode.app_rd_data_reg[105] ), .\not_strict_mode.app_rd_data_reg[107]_0 (\not_strict_mode.app_rd_data_reg[107] ), .\not_strict_mode.app_rd_data_reg[109]_0 (\not_strict_mode.app_rd_data_reg[109] ), .\not_strict_mode.app_rd_data_reg[111]_0 (\not_strict_mode.app_rd_data_reg[111] ), .\not_strict_mode.app_rd_data_reg[113]_0 (\not_strict_mode.app_rd_data_reg[113] ), .\not_strict_mode.app_rd_data_reg[115]_0 (\not_strict_mode.app_rd_data_reg[115] ), .\not_strict_mode.app_rd_data_reg[117]_0 (\not_strict_mode.app_rd_data_reg[117] ), .\not_strict_mode.app_rd_data_reg[119]_0 (\not_strict_mode.app_rd_data_reg[119] ), .\not_strict_mode.app_rd_data_reg[11]_0 (\not_strict_mode.app_rd_data_reg[11] ), .\not_strict_mode.app_rd_data_reg[121]_0 (\not_strict_mode.app_rd_data_reg[121] ), .\not_strict_mode.app_rd_data_reg[123]_0 (\not_strict_mode.app_rd_data_reg[123] ), .\not_strict_mode.app_rd_data_reg[125]_0 (\not_strict_mode.app_rd_data_reg[125] ), .\not_strict_mode.app_rd_data_reg[127]_0 (\not_strict_mode.app_rd_data_reg[127] ), .\not_strict_mode.app_rd_data_reg[129]_0 (\not_strict_mode.app_rd_data_reg[129] ), .\not_strict_mode.app_rd_data_reg[131]_0 (\not_strict_mode.app_rd_data_reg[131] ), .\not_strict_mode.app_rd_data_reg[133]_0 (\not_strict_mode.app_rd_data_reg[133] ), .\not_strict_mode.app_rd_data_reg[135]_0 (\not_strict_mode.app_rd_data_reg[135] ), .\not_strict_mode.app_rd_data_reg[137]_0 (\not_strict_mode.app_rd_data_reg[137] ), .\not_strict_mode.app_rd_data_reg[139]_0 (\not_strict_mode.app_rd_data_reg[139] ), .\not_strict_mode.app_rd_data_reg[13]_0 (\not_strict_mode.app_rd_data_reg[13] ), .\not_strict_mode.app_rd_data_reg[141]_0 (\not_strict_mode.app_rd_data_reg[141] ), .\not_strict_mode.app_rd_data_reg[143]_0 (\not_strict_mode.app_rd_data_reg[143] ), .\not_strict_mode.app_rd_data_reg[145]_0 (\not_strict_mode.app_rd_data_reg[145] ), .\not_strict_mode.app_rd_data_reg[147]_0 (\not_strict_mode.app_rd_data_reg[147] ), .\not_strict_mode.app_rd_data_reg[149]_0 (\not_strict_mode.app_rd_data_reg[149] ), .\not_strict_mode.app_rd_data_reg[151]_0 (\not_strict_mode.app_rd_data_reg[151] ), .\not_strict_mode.app_rd_data_reg[153]_0 (\not_strict_mode.app_rd_data_reg[153] ), .\not_strict_mode.app_rd_data_reg[155]_0 (\not_strict_mode.app_rd_data_reg[155] ), .\not_strict_mode.app_rd_data_reg[157]_0 (\not_strict_mode.app_rd_data_reg[157] ), .\not_strict_mode.app_rd_data_reg[159]_0 (\not_strict_mode.app_rd_data_reg[159] ), .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15] ), .\not_strict_mode.app_rd_data_reg[161]_0 (\not_strict_mode.app_rd_data_reg[161] ), .\not_strict_mode.app_rd_data_reg[163]_0 (\not_strict_mode.app_rd_data_reg[163] ), .\not_strict_mode.app_rd_data_reg[165]_0 (\not_strict_mode.app_rd_data_reg[165] ), .\not_strict_mode.app_rd_data_reg[167]_0 (\not_strict_mode.app_rd_data_reg[167] ), .\not_strict_mode.app_rd_data_reg[169]_0 (\not_strict_mode.app_rd_data_reg[169] ), .\not_strict_mode.app_rd_data_reg[171]_0 (\not_strict_mode.app_rd_data_reg[171] ), .\not_strict_mode.app_rd_data_reg[173]_0 (\not_strict_mode.app_rd_data_reg[173] ), .\not_strict_mode.app_rd_data_reg[175]_0 (\not_strict_mode.app_rd_data_reg[175] ), .\not_strict_mode.app_rd_data_reg[177]_0 (\not_strict_mode.app_rd_data_reg[177] ), .\not_strict_mode.app_rd_data_reg[179]_0 (\not_strict_mode.app_rd_data_reg[179] ), .\not_strict_mode.app_rd_data_reg[17]_0 (\not_strict_mode.app_rd_data_reg[17] ), .\not_strict_mode.app_rd_data_reg[181]_0 (\not_strict_mode.app_rd_data_reg[181] ), .\not_strict_mode.app_rd_data_reg[183]_0 (\not_strict_mode.app_rd_data_reg[183] ), .\not_strict_mode.app_rd_data_reg[185]_0 (\not_strict_mode.app_rd_data_reg[185] ), .\not_strict_mode.app_rd_data_reg[187]_0 (\not_strict_mode.app_rd_data_reg[187] ), .\not_strict_mode.app_rd_data_reg[189]_0 (\not_strict_mode.app_rd_data_reg[189] ), .\not_strict_mode.app_rd_data_reg[191]_0 (\not_strict_mode.app_rd_data_reg[191] ), .\not_strict_mode.app_rd_data_reg[193]_0 (\not_strict_mode.app_rd_data_reg[193] ), .\not_strict_mode.app_rd_data_reg[195]_0 (\not_strict_mode.app_rd_data_reg[195] ), .\not_strict_mode.app_rd_data_reg[197]_0 (\not_strict_mode.app_rd_data_reg[197] ), .\not_strict_mode.app_rd_data_reg[199]_0 (\not_strict_mode.app_rd_data_reg[199] ), .\not_strict_mode.app_rd_data_reg[19]_0 (\not_strict_mode.app_rd_data_reg[19] ), .\not_strict_mode.app_rd_data_reg[201]_0 (\not_strict_mode.app_rd_data_reg[201] ), .\not_strict_mode.app_rd_data_reg[203]_0 (\not_strict_mode.app_rd_data_reg[203] ), .\not_strict_mode.app_rd_data_reg[205]_0 (\not_strict_mode.app_rd_data_reg[205] ), .\not_strict_mode.app_rd_data_reg[207]_0 (\not_strict_mode.app_rd_data_reg[207] ), .\not_strict_mode.app_rd_data_reg[209]_0 (\not_strict_mode.app_rd_data_reg[209] ), .\not_strict_mode.app_rd_data_reg[211]_0 (\not_strict_mode.app_rd_data_reg[211] ), .\not_strict_mode.app_rd_data_reg[213]_0 (\not_strict_mode.app_rd_data_reg[213] ), .\not_strict_mode.app_rd_data_reg[215]_0 (\not_strict_mode.app_rd_data_reg[215] ), .\not_strict_mode.app_rd_data_reg[217]_0 (\not_strict_mode.app_rd_data_reg[217] ), .\not_strict_mode.app_rd_data_reg[219]_0 (\not_strict_mode.app_rd_data_reg[219] ), .\not_strict_mode.app_rd_data_reg[21]_0 (\not_strict_mode.app_rd_data_reg[21] ), .\not_strict_mode.app_rd_data_reg[221]_0 (\not_strict_mode.app_rd_data_reg[221] ), .\not_strict_mode.app_rd_data_reg[223]_0 (\not_strict_mode.app_rd_data_reg[223] ), .\not_strict_mode.app_rd_data_reg[225]_0 (\not_strict_mode.app_rd_data_reg[225] ), .\not_strict_mode.app_rd_data_reg[227]_0 (\not_strict_mode.app_rd_data_reg[227] ), .\not_strict_mode.app_rd_data_reg[229]_0 (\not_strict_mode.app_rd_data_reg[229] ), .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231] ), .\not_strict_mode.app_rd_data_reg[233]_0 (\not_strict_mode.app_rd_data_reg[233] ), .\not_strict_mode.app_rd_data_reg[235]_0 (\not_strict_mode.app_rd_data_reg[235] ), .\not_strict_mode.app_rd_data_reg[237]_0 (\not_strict_mode.app_rd_data_reg[237] ), .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239] ), .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23] ), .\not_strict_mode.app_rd_data_reg[241]_0 (\not_strict_mode.app_rd_data_reg[241] ), .\not_strict_mode.app_rd_data_reg[243]_0 (\not_strict_mode.app_rd_data_reg[243] ), .\not_strict_mode.app_rd_data_reg[245]_0 (\not_strict_mode.app_rd_data_reg[245] ), .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247] ), .\not_strict_mode.app_rd_data_reg[249]_0 (\not_strict_mode.app_rd_data_reg[249] ), .\not_strict_mode.app_rd_data_reg[251]_0 (\not_strict_mode.app_rd_data_reg[251] ), .\not_strict_mode.app_rd_data_reg[253]_0 (\not_strict_mode.app_rd_data_reg[253] ), .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255] ), .\not_strict_mode.app_rd_data_reg[25]_0 (\not_strict_mode.app_rd_data_reg[25] ), .\not_strict_mode.app_rd_data_reg[27]_0 (\not_strict_mode.app_rd_data_reg[27] ), .\not_strict_mode.app_rd_data_reg[29]_0 (\not_strict_mode.app_rd_data_reg[29] ), .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31] ), .\not_strict_mode.app_rd_data_reg[33]_0 (\not_strict_mode.app_rd_data_reg[33] ), .\not_strict_mode.app_rd_data_reg[35]_0 (\not_strict_mode.app_rd_data_reg[35] ), .\not_strict_mode.app_rd_data_reg[37]_0 (\not_strict_mode.app_rd_data_reg[37] ), .\not_strict_mode.app_rd_data_reg[39]_0 (\not_strict_mode.app_rd_data_reg[39] ), .\not_strict_mode.app_rd_data_reg[41]_0 (\not_strict_mode.app_rd_data_reg[41] ), .\not_strict_mode.app_rd_data_reg[43]_0 (\not_strict_mode.app_rd_data_reg[43] ), .\not_strict_mode.app_rd_data_reg[45]_0 (\not_strict_mode.app_rd_data_reg[45] ), .\not_strict_mode.app_rd_data_reg[47]_0 (\not_strict_mode.app_rd_data_reg[47] ), .\not_strict_mode.app_rd_data_reg[49]_0 (\not_strict_mode.app_rd_data_reg[49] ), .\not_strict_mode.app_rd_data_reg[51]_0 (\not_strict_mode.app_rd_data_reg[51] ), .\not_strict_mode.app_rd_data_reg[53]_0 (\not_strict_mode.app_rd_data_reg[53] ), .\not_strict_mode.app_rd_data_reg[55]_0 (\not_strict_mode.app_rd_data_reg[55] ), .\not_strict_mode.app_rd_data_reg[57]_0 (\not_strict_mode.app_rd_data_reg[57] ), .\not_strict_mode.app_rd_data_reg[59]_0 (\not_strict_mode.app_rd_data_reg[59] ), .\not_strict_mode.app_rd_data_reg[61]_0 (\not_strict_mode.app_rd_data_reg[61] ), .\not_strict_mode.app_rd_data_reg[63]_0 (\not_strict_mode.app_rd_data_reg[63] ), .\not_strict_mode.app_rd_data_reg[65]_0 (\not_strict_mode.app_rd_data_reg[65] ), .\not_strict_mode.app_rd_data_reg[67]_0 (\not_strict_mode.app_rd_data_reg[67] ), .\not_strict_mode.app_rd_data_reg[69]_0 (\not_strict_mode.app_rd_data_reg[69] ), .\not_strict_mode.app_rd_data_reg[71]_0 (\not_strict_mode.app_rd_data_reg[71] ), .\not_strict_mode.app_rd_data_reg[73]_0 (\not_strict_mode.app_rd_data_reg[73] ), .\not_strict_mode.app_rd_data_reg[75]_0 (\not_strict_mode.app_rd_data_reg[75] ), .\not_strict_mode.app_rd_data_reg[77]_0 (\not_strict_mode.app_rd_data_reg[77] ), .\not_strict_mode.app_rd_data_reg[79]_0 (\not_strict_mode.app_rd_data_reg[79] ), .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7] ), .\not_strict_mode.app_rd_data_reg[81]_0 (\not_strict_mode.app_rd_data_reg[81] ), .\not_strict_mode.app_rd_data_reg[83]_0 (\not_strict_mode.app_rd_data_reg[83] ), .\not_strict_mode.app_rd_data_reg[85]_0 (\not_strict_mode.app_rd_data_reg[85] ), .\not_strict_mode.app_rd_data_reg[87]_0 (\not_strict_mode.app_rd_data_reg[87] ), .\not_strict_mode.app_rd_data_reg[89]_0 (\not_strict_mode.app_rd_data_reg[89] ), .\not_strict_mode.app_rd_data_reg[91]_0 (\not_strict_mode.app_rd_data_reg[91] ), .\not_strict_mode.app_rd_data_reg[93]_0 (\not_strict_mode.app_rd_data_reg[93] ), .\not_strict_mode.app_rd_data_reg[95]_0 (\not_strict_mode.app_rd_data_reg[95] ), .\not_strict_mode.app_rd_data_reg[97]_0 (\not_strict_mode.app_rd_data_reg[97] ), .\not_strict_mode.app_rd_data_reg[99]_0 (\not_strict_mode.app_rd_data_reg[99] ), .\not_strict_mode.app_rd_data_reg[9]_0 (\not_strict_mode.app_rd_data_reg[9] ), .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 (rd_data_buf_addr_r), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 (ui_cmd0_n_15), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 (occ_cnt_r), .\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 (ram_init_done_r), .pointer_wr_data(pointer_wr_data), .rd_accepted(rd_accepted), .\rd_buf_indx.ram_init_done_r_lcl_reg_0 (ui_rd_data0_n_272), .rd_buf_we(rd_buf_we), .\read_data_indx.rd_data_indx_r_reg[3] (\read_data_indx.rd_data_indx_r_reg__0 ), .\read_fifo.fifo_out_data_r_reg[7] (\read_fifo.fifo_out_data_r_reg[7] ), .reset_reg(reset_reg), .\s_axi_rdata[255] (\s_axi_rdata[255] )); ddr3_if_mig_7series_v4_0_ui_wr_data ui_wr_data0 (.ADDRD(pointer_wr_addr), .CLK(CLK), .D(D), .E(E), .Q(\read_data_indx.rd_data_indx_r_reg__0 ), .accept_ns(accept_ns), .app_rdy_ns(app_rdy_ns), .app_wdf_data(app_wdf_data), .app_wdf_mask(app_wdf_mask), .\cmd_pipe_plus.wr_data_addr_reg[3] (\cmd_pipe_plus.wr_data_addr_reg[3] ), .mc_app_wdf_data_reg(mc_app_wdf_data_reg), .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg), .\mc_app_wdf_mask_reg_reg[0] (app_wdf_rdy), .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg), .\my_empty_reg[7] (\my_empty_reg[7] ), .\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] (ui_rd_data0_n_264), .p_0_in(p_0_in), .pointer_we(pointer_we), .pointer_wr_data(pointer_wr_data), .ram_init_done_r(ram_init_done_r), .\rd_buf_indx.ram_init_done_r_lcl_reg (ui_rd_data0_n_272), .\read_data_indx.rd_data_upd_indx_r_reg_0 (ui_cmd0_n_12), .reset_reg(reset_reg), .w_cmd_rdy(w_cmd_rdy), .wr_accepted(wr_accepted), .wr_data_buf_addr(wr_data_buf_addr), .\wr_req_counter.wr_req_cnt_r_reg[1]_0 (wr_req_cnt_r), .\wr_req_counter.wr_req_cnt_r_reg[1]_1 (ui_cmd0_n_13), .wready_reg_rep__1(wready_reg_rep__1)); endmodule module ddr3_if_mig_7series_v4_0_ui_wr_data (wr_data_buf_addr, p_0_in, \mc_app_wdf_mask_reg_reg[0] , app_rdy_ns, \wr_req_counter.wr_req_cnt_r_reg[1]_0 , Q, \my_empty_reg[7] , CLK, pointer_we, pointer_wr_data, ADDRD, \cmd_pipe_plus.wr_data_addr_reg[3] , E, mc_app_wdf_wren_reg, w_cmd_rdy, reset_reg, D, mc_app_wdf_mask_reg, wready_reg_rep__1, mc_app_wdf_data_reg, \not_strict_mode.occupied_counter.occ_cnt_r_reg[4] , accept_ns, wr_accepted, \wr_req_counter.wr_req_cnt_r_reg[1]_1 , \read_data_indx.rd_data_upd_indx_r_reg_0 , \rd_buf_indx.ram_init_done_r_lcl_reg , ram_init_done_r, app_wdf_data, app_wdf_mask); output [3:0]wr_data_buf_addr; output [0:0]p_0_in; output \mc_app_wdf_mask_reg_reg[0] ; output app_rdy_ns; output [1:0]\wr_req_counter.wr_req_cnt_r_reg[1]_0 ; output [3:0]Q; output [287:0]\my_empty_reg[7] ; input CLK; input pointer_we; input [3:0]pointer_wr_data; input [3:0]ADDRD; input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; input [0:0]E; input mc_app_wdf_wren_reg; input w_cmd_rdy; input reset_reg; input [31:0]D; input [31:0]mc_app_wdf_mask_reg; input [255:0]wready_reg_rep__1; input [255:0]mc_app_wdf_data_reg; input [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ; input accept_ns; input wr_accepted; input \wr_req_counter.wr_req_cnt_r_reg[1]_1 ; input \read_data_indx.rd_data_upd_indx_r_reg_0 ; input \rd_buf_indx.ram_init_done_r_lcl_reg ; input ram_init_done_r; input [255:0]app_wdf_data; input [31:0]app_wdf_mask; wire [3:0]ADDRD; wire CLK; wire [31:0]D; wire [0:0]E; wire [3:0]Q; wire accept_ns; wire app_rdy_ns; wire app_rdy_r_i_2_n_0; wire app_rdy_r_i_3_n_0; wire [255:0]app_wdf_data; wire [255:0]app_wdf_data_r1; wire app_wdf_end_ns1; wire app_wdf_end_r1; wire [31:0]app_wdf_mask; wire [31:0]app_wdf_mask_r1; wire app_wdf_rdy_r_copy1; wire app_wdf_rdy_r_copy2; wire app_wdf_rdy_r_copy3; wire app_wdf_wren_ns1; wire app_wdf_wren_r1; wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ; wire [3:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 ; wire [255:0]mc_app_wdf_data_reg; wire [31:0]mc_app_wdf_mask_reg; wire \mc_app_wdf_mask_reg_reg[0] ; wire mc_app_wdf_wren_reg; wire [287:0]\my_empty_reg[7] ; wire [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ; wire \occupied_counter.occ_cnt[0]_i_1_n_0 ; wire \occupied_counter.occ_cnt[10]_i_1_n_0 ; wire \occupied_counter.occ_cnt[11]_i_1_n_0 ; wire \occupied_counter.occ_cnt[12]_i_1_n_0 ; wire \occupied_counter.occ_cnt[13]_i_1_n_0 ; wire \occupied_counter.occ_cnt[14]_i_1_n_0 ; wire \occupied_counter.occ_cnt[15]_i_1_n_0 ; wire \occupied_counter.occ_cnt[15]_i_2_n_0 ; wire \occupied_counter.occ_cnt[1]_i_1_n_0 ; wire \occupied_counter.occ_cnt[2]_i_1_n_0 ; wire \occupied_counter.occ_cnt[3]_i_1_n_0 ; wire \occupied_counter.occ_cnt[4]_i_1_n_0 ; wire \occupied_counter.occ_cnt[5]_i_1_n_0 ; wire \occupied_counter.occ_cnt[6]_i_1_n_0 ; wire \occupied_counter.occ_cnt[7]_i_1_n_0 ; wire \occupied_counter.occ_cnt[8]_i_1_n_0 ; wire \occupied_counter.occ_cnt[9]_i_1_n_0 ; wire \occupied_counter.occ_cnt_reg_n_0_[0] ; wire \occupied_counter.occ_cnt_reg_n_0_[10] ; wire \occupied_counter.occ_cnt_reg_n_0_[11] ; wire \occupied_counter.occ_cnt_reg_n_0_[12] ; wire \occupied_counter.occ_cnt_reg_n_0_[13] ; wire \occupied_counter.occ_cnt_reg_n_0_[15] ; wire \occupied_counter.occ_cnt_reg_n_0_[1] ; wire \occupied_counter.occ_cnt_reg_n_0_[2] ; wire \occupied_counter.occ_cnt_reg_n_0_[3] ; wire \occupied_counter.occ_cnt_reg_n_0_[4] ; wire \occupied_counter.occ_cnt_reg_n_0_[5] ; wire \occupied_counter.occ_cnt_reg_n_0_[6] ; wire \occupied_counter.occ_cnt_reg_n_0_[7] ; wire \occupied_counter.occ_cnt_reg_n_0_[8] ; wire \occupied_counter.occ_cnt_reg_n_0_[9] ; wire [0:0]p_0_in; wire [3:0]p_0_in__0; wire [1:1]p_0_in__0_0; wire [3:0]p_0_in__0__0; wire [3:0]p_0_in__1; wire p_4_in; wire pointer_we; wire [3:0]pointer_wr_data; wire ram_init_done_r; wire \rd_buf_indx.ram_init_done_r_lcl_reg ; wire \read_data_indx.rd_data_upd_indx_r_reg_0 ; wire reset_reg; wire w_cmd_rdy; wire wb_wr_data_addr0_ns; wire wb_wr_data_addr0_r; wire [4:1]wb_wr_data_addr_r; wire [4:1]wb_wr_data_addr_w; wire wdf_rdy_ns; wire wr_accepted; wire [287:0]wr_buf_in_data; wire [287:0]wr_buf_out_data_w; wire wr_data_addr_le; wire [3:0]wr_data_buf_addr; wire [3:0]wr_data_pntr; wire [4:2]wr_req_cnt_r; wire \wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ; wire \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ; wire [1:0]\wr_req_counter.wr_req_cnt_r_reg[1]_0 ; wire \wr_req_counter.wr_req_cnt_r_reg[1]_1 ; wire [255:0]wready_reg_rep__1; wire [3:0]\write_data_control.wr_data_indx_r_reg__0 ; wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ; wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ; wire [1:0]\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ; LUT5 #( .INIT(32'h44440444)) app_rdy_r_i_1 (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ), .I1(accept_ns), .I2(app_rdy_r_i_2_n_0), .I3(app_rdy_r_i_3_n_0), .I4(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ), .O(app_rdy_ns)); LUT6 #( .INIT(64'hFFFF00007FFE8001)) app_rdy_r_i_2 (.I0(wr_req_cnt_r[3]), .I1(wr_req_cnt_r[2]), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I3(\wr_req_counter.wr_req_cnt_r_reg[1]_1 ), .I4(wr_req_cnt_r[4]), .I5(\read_data_indx.rd_data_upd_indx_r_reg_0 ), .O(app_rdy_r_i_2_n_0)); LUT6 #( .INIT(64'h0040010000001001)) app_rdy_r_i_3 (.I0(reset_reg), .I1(wr_req_cnt_r[2]), .I2(wr_accepted), .I3(p_0_in), .I4(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I5(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .O(app_rdy_r_i_3_n_0)); FDRE \app_wdf_data_r1_reg[0] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[0]), .Q(app_wdf_data_r1[0]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[100] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[100]), .Q(app_wdf_data_r1[100]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[101] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[101]), .Q(app_wdf_data_r1[101]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[102] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[102]), .Q(app_wdf_data_r1[102]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[103] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[103]), .Q(app_wdf_data_r1[103]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[104] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[104]), .Q(app_wdf_data_r1[104]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[105] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[105]), .Q(app_wdf_data_r1[105]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[106] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[106]), .Q(app_wdf_data_r1[106]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[107] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[107]), .Q(app_wdf_data_r1[107]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[108] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[108]), .Q(app_wdf_data_r1[108]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[109] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[109]), .Q(app_wdf_data_r1[109]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[10] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[10]), .Q(app_wdf_data_r1[10]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[110] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[110]), .Q(app_wdf_data_r1[110]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[111] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[111]), .Q(app_wdf_data_r1[111]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[112] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[112]), .Q(app_wdf_data_r1[112]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[113] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[113]), .Q(app_wdf_data_r1[113]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[114] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[114]), .Q(app_wdf_data_r1[114]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[115] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[115]), .Q(app_wdf_data_r1[115]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[116] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[116]), .Q(app_wdf_data_r1[116]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[117] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[117]), .Q(app_wdf_data_r1[117]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[118] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[118]), .Q(app_wdf_data_r1[118]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[119] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[119]), .Q(app_wdf_data_r1[119]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[11] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[11]), .Q(app_wdf_data_r1[11]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[120] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[120]), .Q(app_wdf_data_r1[120]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[121] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[121]), .Q(app_wdf_data_r1[121]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[122] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[122]), .Q(app_wdf_data_r1[122]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[123] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[123]), .Q(app_wdf_data_r1[123]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[124] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[124]), .Q(app_wdf_data_r1[124]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[125] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[125]), .Q(app_wdf_data_r1[125]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[126] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[126]), .Q(app_wdf_data_r1[126]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[127] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[127]), .Q(app_wdf_data_r1[127]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[128] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[128]), .Q(app_wdf_data_r1[128]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[129] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[129]), .Q(app_wdf_data_r1[129]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[12] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[12]), .Q(app_wdf_data_r1[12]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[130] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[130]), .Q(app_wdf_data_r1[130]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[131] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[131]), .Q(app_wdf_data_r1[131]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[132] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[132]), .Q(app_wdf_data_r1[132]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[133] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[133]), .Q(app_wdf_data_r1[133]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[134] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[134]), .Q(app_wdf_data_r1[134]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[135] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[135]), .Q(app_wdf_data_r1[135]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[136] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[136]), .Q(app_wdf_data_r1[136]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[137] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[137]), .Q(app_wdf_data_r1[137]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[138] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[138]), .Q(app_wdf_data_r1[138]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[139] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[139]), .Q(app_wdf_data_r1[139]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[13] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[13]), .Q(app_wdf_data_r1[13]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[140] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[140]), .Q(app_wdf_data_r1[140]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[141] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[141]), .Q(app_wdf_data_r1[141]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[142] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[142]), .Q(app_wdf_data_r1[142]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[143] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[143]), .Q(app_wdf_data_r1[143]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[144] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[144]), .Q(app_wdf_data_r1[144]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[145] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[145]), .Q(app_wdf_data_r1[145]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[146] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[146]), .Q(app_wdf_data_r1[146]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[147] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[147]), .Q(app_wdf_data_r1[147]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[148] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[148]), .Q(app_wdf_data_r1[148]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[149] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[149]), .Q(app_wdf_data_r1[149]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[14] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[14]), .Q(app_wdf_data_r1[14]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[150] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[150]), .Q(app_wdf_data_r1[150]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[151] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[151]), .Q(app_wdf_data_r1[151]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[152] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[152]), .Q(app_wdf_data_r1[152]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[153] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[153]), .Q(app_wdf_data_r1[153]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[154] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[154]), .Q(app_wdf_data_r1[154]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[155] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[155]), .Q(app_wdf_data_r1[155]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[156] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[156]), .Q(app_wdf_data_r1[156]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[157] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[157]), .Q(app_wdf_data_r1[157]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[158] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[158]), .Q(app_wdf_data_r1[158]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[159] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[159]), .Q(app_wdf_data_r1[159]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[15] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[15]), .Q(app_wdf_data_r1[15]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[160] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[160]), .Q(app_wdf_data_r1[160]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[161] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[161]), .Q(app_wdf_data_r1[161]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[162] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[162]), .Q(app_wdf_data_r1[162]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[163] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[163]), .Q(app_wdf_data_r1[163]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[164] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[164]), .Q(app_wdf_data_r1[164]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[165] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[165]), .Q(app_wdf_data_r1[165]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[166] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[166]), .Q(app_wdf_data_r1[166]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[167] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[167]), .Q(app_wdf_data_r1[167]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[168] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[168]), .Q(app_wdf_data_r1[168]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[169] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[169]), .Q(app_wdf_data_r1[169]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[16] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[16]), .Q(app_wdf_data_r1[16]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[170] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[170]), .Q(app_wdf_data_r1[170]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[171] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[171]), .Q(app_wdf_data_r1[171]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[172] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[172]), .Q(app_wdf_data_r1[172]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[173] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[173]), .Q(app_wdf_data_r1[173]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[174] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[174]), .Q(app_wdf_data_r1[174]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[175] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[175]), .Q(app_wdf_data_r1[175]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[176] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[176]), .Q(app_wdf_data_r1[176]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[177] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[177]), .Q(app_wdf_data_r1[177]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[178] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[178]), .Q(app_wdf_data_r1[178]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[179] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[179]), .Q(app_wdf_data_r1[179]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[17] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[17]), .Q(app_wdf_data_r1[17]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[180] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[180]), .Q(app_wdf_data_r1[180]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[181] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[181]), .Q(app_wdf_data_r1[181]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[182] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[182]), .Q(app_wdf_data_r1[182]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[183] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[183]), .Q(app_wdf_data_r1[183]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[184] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[184]), .Q(app_wdf_data_r1[184]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[185] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[185]), .Q(app_wdf_data_r1[185]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[186] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[186]), .Q(app_wdf_data_r1[186]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[187] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[187]), .Q(app_wdf_data_r1[187]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[188] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[188]), .Q(app_wdf_data_r1[188]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[189] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[189]), .Q(app_wdf_data_r1[189]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[18] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[18]), .Q(app_wdf_data_r1[18]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[190] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[190]), .Q(app_wdf_data_r1[190]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[191] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[191]), .Q(app_wdf_data_r1[191]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[192] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[192]), .Q(app_wdf_data_r1[192]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[193] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[193]), .Q(app_wdf_data_r1[193]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[194] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[194]), .Q(app_wdf_data_r1[194]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[195] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[195]), .Q(app_wdf_data_r1[195]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[196] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[196]), .Q(app_wdf_data_r1[196]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[197] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[197]), .Q(app_wdf_data_r1[197]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[198] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[198]), .Q(app_wdf_data_r1[198]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[199] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[199]), .Q(app_wdf_data_r1[199]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[19] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[19]), .Q(app_wdf_data_r1[19]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[1] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[1]), .Q(app_wdf_data_r1[1]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[200] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[200]), .Q(app_wdf_data_r1[200]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[201] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[201]), .Q(app_wdf_data_r1[201]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[202] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[202]), .Q(app_wdf_data_r1[202]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[203] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[203]), .Q(app_wdf_data_r1[203]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[204] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[204]), .Q(app_wdf_data_r1[204]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[205] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[205]), .Q(app_wdf_data_r1[205]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[206] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[206]), .Q(app_wdf_data_r1[206]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[207] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[207]), .Q(app_wdf_data_r1[207]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[208] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[208]), .Q(app_wdf_data_r1[208]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[209] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[209]), .Q(app_wdf_data_r1[209]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[20] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[20]), .Q(app_wdf_data_r1[20]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[210] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[210]), .Q(app_wdf_data_r1[210]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[211] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[211]), .Q(app_wdf_data_r1[211]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[212] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[212]), .Q(app_wdf_data_r1[212]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[213] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[213]), .Q(app_wdf_data_r1[213]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[214] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[214]), .Q(app_wdf_data_r1[214]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[215] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[215]), .Q(app_wdf_data_r1[215]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[216] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[216]), .Q(app_wdf_data_r1[216]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[217] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[217]), .Q(app_wdf_data_r1[217]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[218] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[218]), .Q(app_wdf_data_r1[218]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[219] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[219]), .Q(app_wdf_data_r1[219]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[21] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[21]), .Q(app_wdf_data_r1[21]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[220] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[220]), .Q(app_wdf_data_r1[220]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[221] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[221]), .Q(app_wdf_data_r1[221]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[222] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[222]), .Q(app_wdf_data_r1[222]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[223] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[223]), .Q(app_wdf_data_r1[223]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[224] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[224]), .Q(app_wdf_data_r1[224]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[225] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[225]), .Q(app_wdf_data_r1[225]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[226] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[226]), .Q(app_wdf_data_r1[226]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[227] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[227]), .Q(app_wdf_data_r1[227]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[228] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[228]), .Q(app_wdf_data_r1[228]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[229] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[229]), .Q(app_wdf_data_r1[229]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[22] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[22]), .Q(app_wdf_data_r1[22]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[230] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[230]), .Q(app_wdf_data_r1[230]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[231] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[231]), .Q(app_wdf_data_r1[231]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[232] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[232]), .Q(app_wdf_data_r1[232]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[233] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[233]), .Q(app_wdf_data_r1[233]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[234] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[234]), .Q(app_wdf_data_r1[234]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[235] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[235]), .Q(app_wdf_data_r1[235]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[236] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[236]), .Q(app_wdf_data_r1[236]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[237] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[237]), .Q(app_wdf_data_r1[237]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[238] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[238]), .Q(app_wdf_data_r1[238]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[239] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[239]), .Q(app_wdf_data_r1[239]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[23] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[23]), .Q(app_wdf_data_r1[23]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[240] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[240]), .Q(app_wdf_data_r1[240]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[241] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[241]), .Q(app_wdf_data_r1[241]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[242] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[242]), .Q(app_wdf_data_r1[242]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[243] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[243]), .Q(app_wdf_data_r1[243]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[244] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[244]), .Q(app_wdf_data_r1[244]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[245] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[245]), .Q(app_wdf_data_r1[245]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[246] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[246]), .Q(app_wdf_data_r1[246]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[247] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[247]), .Q(app_wdf_data_r1[247]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[248] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[248]), .Q(app_wdf_data_r1[248]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[249] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[249]), .Q(app_wdf_data_r1[249]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[24] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[24]), .Q(app_wdf_data_r1[24]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[250] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[250]), .Q(app_wdf_data_r1[250]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[251] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[251]), .Q(app_wdf_data_r1[251]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[252] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[252]), .Q(app_wdf_data_r1[252]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[253] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[253]), .Q(app_wdf_data_r1[253]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[254] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[254]), .Q(app_wdf_data_r1[254]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[255] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[255]), .Q(app_wdf_data_r1[255]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[25] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[25]), .Q(app_wdf_data_r1[25]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[26] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[26]), .Q(app_wdf_data_r1[26]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[27] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[27]), .Q(app_wdf_data_r1[27]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[28] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[28]), .Q(app_wdf_data_r1[28]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[29] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[29]), .Q(app_wdf_data_r1[29]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[2] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[2]), .Q(app_wdf_data_r1[2]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[30] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[30]), .Q(app_wdf_data_r1[30]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[31] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[31]), .Q(app_wdf_data_r1[31]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[32] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[32]), .Q(app_wdf_data_r1[32]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[33] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[33]), .Q(app_wdf_data_r1[33]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[34] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[34]), .Q(app_wdf_data_r1[34]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[35] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[35]), .Q(app_wdf_data_r1[35]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[36] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[36]), .Q(app_wdf_data_r1[36]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[37] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[37]), .Q(app_wdf_data_r1[37]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[38] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[38]), .Q(app_wdf_data_r1[38]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[39] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[39]), .Q(app_wdf_data_r1[39]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[3] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[3]), .Q(app_wdf_data_r1[3]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[40] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[40]), .Q(app_wdf_data_r1[40]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[41] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[41]), .Q(app_wdf_data_r1[41]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[42] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[42]), .Q(app_wdf_data_r1[42]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[43] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[43]), .Q(app_wdf_data_r1[43]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[44] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[44]), .Q(app_wdf_data_r1[44]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[45] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[45]), .Q(app_wdf_data_r1[45]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[46] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[46]), .Q(app_wdf_data_r1[46]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[47] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[47]), .Q(app_wdf_data_r1[47]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[48] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[48]), .Q(app_wdf_data_r1[48]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[49] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[49]), .Q(app_wdf_data_r1[49]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[4] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[4]), .Q(app_wdf_data_r1[4]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[50] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[50]), .Q(app_wdf_data_r1[50]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[51] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[51]), .Q(app_wdf_data_r1[51]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[52] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[52]), .Q(app_wdf_data_r1[52]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[53] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[53]), .Q(app_wdf_data_r1[53]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[54] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[54]), .Q(app_wdf_data_r1[54]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[55] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[55]), .Q(app_wdf_data_r1[55]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[56] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[56]), .Q(app_wdf_data_r1[56]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[57] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[57]), .Q(app_wdf_data_r1[57]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[58] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[58]), .Q(app_wdf_data_r1[58]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[59] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[59]), .Q(app_wdf_data_r1[59]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[5] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[5]), .Q(app_wdf_data_r1[5]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[60] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[60]), .Q(app_wdf_data_r1[60]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[61] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[61]), .Q(app_wdf_data_r1[61]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[62] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[62]), .Q(app_wdf_data_r1[62]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[63] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[63]), .Q(app_wdf_data_r1[63]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[64] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[64]), .Q(app_wdf_data_r1[64]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[65] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[65]), .Q(app_wdf_data_r1[65]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[66] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[66]), .Q(app_wdf_data_r1[66]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[67] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[67]), .Q(app_wdf_data_r1[67]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[68] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[68]), .Q(app_wdf_data_r1[68]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[69] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[69]), .Q(app_wdf_data_r1[69]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[6] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[6]), .Q(app_wdf_data_r1[6]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[70] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[70]), .Q(app_wdf_data_r1[70]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[71] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[71]), .Q(app_wdf_data_r1[71]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[72] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[72]), .Q(app_wdf_data_r1[72]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[73] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[73]), .Q(app_wdf_data_r1[73]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[74] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[74]), .Q(app_wdf_data_r1[74]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[75] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[75]), .Q(app_wdf_data_r1[75]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[76] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[76]), .Q(app_wdf_data_r1[76]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[77] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[77]), .Q(app_wdf_data_r1[77]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[78] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[78]), .Q(app_wdf_data_r1[78]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[79] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[79]), .Q(app_wdf_data_r1[79]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[7] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[7]), .Q(app_wdf_data_r1[7]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[80] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[80]), .Q(app_wdf_data_r1[80]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[81] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[81]), .Q(app_wdf_data_r1[81]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[82] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[82]), .Q(app_wdf_data_r1[82]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[83] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[83]), .Q(app_wdf_data_r1[83]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[84] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[84]), .Q(app_wdf_data_r1[84]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[85] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[85]), .Q(app_wdf_data_r1[85]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[86] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[86]), .Q(app_wdf_data_r1[86]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[87] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[87]), .Q(app_wdf_data_r1[87]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[88] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[88]), .Q(app_wdf_data_r1[88]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[89] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[89]), .Q(app_wdf_data_r1[89]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[8] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[8]), .Q(app_wdf_data_r1[8]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[90] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[90]), .Q(app_wdf_data_r1[90]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[91] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[91]), .Q(app_wdf_data_r1[91]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[92] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[92]), .Q(app_wdf_data_r1[92]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[93] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[93]), .Q(app_wdf_data_r1[93]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[94] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[94]), .Q(app_wdf_data_r1[94]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[95] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[95]), .Q(app_wdf_data_r1[95]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[96] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[96]), .Q(app_wdf_data_r1[96]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[97] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[97]), .Q(app_wdf_data_r1[97]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[98] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[98]), .Q(app_wdf_data_r1[98]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[99] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[99]), .Q(app_wdf_data_r1[99]), .R(1'b0)); FDRE \app_wdf_data_r1_reg[9] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_data[9]), .Q(app_wdf_data_r1[9]), .R(1'b0)); LUT6 #( .INIT(64'h00E200E200FF0000)) app_wdf_end_r1_i_1 (.I0(mc_app_wdf_wren_reg), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(w_cmd_rdy), .I3(reset_reg), .I4(app_wdf_end_r1), .I5(app_wdf_rdy_r_copy2), .O(app_wdf_end_ns1)); FDRE app_wdf_end_r1_reg (.C(CLK), .CE(1'b1), .D(app_wdf_end_ns1), .Q(app_wdf_end_r1), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[0] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[0]), .Q(app_wdf_mask_r1[0]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[10] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[10]), .Q(app_wdf_mask_r1[10]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[11] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[11]), .Q(app_wdf_mask_r1[11]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[12] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[12]), .Q(app_wdf_mask_r1[12]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[13] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[13]), .Q(app_wdf_mask_r1[13]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[14] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[14]), .Q(app_wdf_mask_r1[14]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[15] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[15]), .Q(app_wdf_mask_r1[15]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[16] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[16]), .Q(app_wdf_mask_r1[16]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[17] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[17]), .Q(app_wdf_mask_r1[17]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[18] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[18]), .Q(app_wdf_mask_r1[18]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[19] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[19]), .Q(app_wdf_mask_r1[19]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[1] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[1]), .Q(app_wdf_mask_r1[1]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[20] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[20]), .Q(app_wdf_mask_r1[20]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[21] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[21]), .Q(app_wdf_mask_r1[21]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[22] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[22]), .Q(app_wdf_mask_r1[22]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[23] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[23]), .Q(app_wdf_mask_r1[23]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[24] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[24]), .Q(app_wdf_mask_r1[24]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[25] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[25]), .Q(app_wdf_mask_r1[25]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[26] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[26]), .Q(app_wdf_mask_r1[26]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[27] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[27]), .Q(app_wdf_mask_r1[27]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[28] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[28]), .Q(app_wdf_mask_r1[28]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[29] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[29]), .Q(app_wdf_mask_r1[29]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[2] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[2]), .Q(app_wdf_mask_r1[2]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[30] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[30]), .Q(app_wdf_mask_r1[30]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[31] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[31]), .Q(app_wdf_mask_r1[31]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[3] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[3]), .Q(app_wdf_mask_r1[3]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[4] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[4]), .Q(app_wdf_mask_r1[4]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[5] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[5]), .Q(app_wdf_mask_r1[5]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[6] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[6]), .Q(app_wdf_mask_r1[6]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[7] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[7]), .Q(app_wdf_mask_r1[7]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[8] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[8]), .Q(app_wdf_mask_r1[8]), .R(1'b0)); FDRE \app_wdf_mask_r1_reg[9] (.C(CLK), .CE(app_wdf_rdy_r_copy2), .D(app_wdf_mask[9]), .Q(app_wdf_mask_r1[9]), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE app_wdf_rdy_r_copy1_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(app_wdf_rdy_r_copy1), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE app_wdf_rdy_r_copy2_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(app_wdf_rdy_r_copy2), .R(1'b0)); (* equivalent_register_removal = "no" *) FDRE app_wdf_rdy_r_copy3_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(app_wdf_rdy_r_copy3), .R(1'b0)); LUT6 #( .INIT(64'h00E200E200FF0000)) app_wdf_wren_r1_i_1 (.I0(mc_app_wdf_wren_reg), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(w_cmd_rdy), .I3(reset_reg), .I4(app_wdf_wren_r1), .I5(app_wdf_rdy_r_copy2), .O(app_wdf_wren_ns1)); FDRE app_wdf_wren_r1_reg (.C(CLK), .CE(1'b1), .D(app_wdf_wren_ns1), .Q(app_wdf_wren_r1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1519" *) LUT1 #( .INIT(2'h1)) \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair1519" *) LUT2 #( .INIT(4'h6)) \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair1518" *) LUT3 #( .INIT(8'h78)) \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair1518" *) LUT4 #( .INIT(16'h7F80)) \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]), .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]), .O(p_0_in__0[3])); FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[0] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[0]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]), .R(reset_reg)); FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[1] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[1]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]), .R(reset_reg)); FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[2] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[2]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]), .R(reset_reg)); FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[3] (.C(CLK), .CE(wr_accepted), .D(p_0_in__0[3]), .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]), .R(reset_reg)); (* equivalent_register_removal = "no" *) FDRE \occupied_counter.app_wdf_rdy_r_reg (.C(CLK), .CE(1'b1), .D(wdf_rdy_ns), .Q(\mc_app_wdf_mask_reg_reg[0] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1515" *) LUT4 #( .INIT(16'hEAAA)) \occupied_counter.occ_cnt[0]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ), .I1(app_wdf_rdy_r_copy1), .I2(app_wdf_end_r1), .I3(app_wdf_wren_r1), .O(\occupied_counter.occ_cnt[0]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[10]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[9] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[11] ), .O(\occupied_counter.occ_cnt[10]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[11]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[10] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[12] ), .O(\occupied_counter.occ_cnt[11]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[12]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[11] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[13] ), .O(\occupied_counter.occ_cnt[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1514" *) LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[13]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[12] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(p_4_in), .O(\occupied_counter.occ_cnt[13]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[14]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[13] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[15] ), .O(\occupied_counter.occ_cnt[14]_i_1_n_0 )); LUT4 #( .INIT(16'h6AAA)) \occupied_counter.occ_cnt[15]_i_1 (.I0(p_0_in), .I1(app_wdf_rdy_r_copy1), .I2(app_wdf_end_r1), .I3(app_wdf_wren_r1), .O(\occupied_counter.occ_cnt[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1514" *) LUT4 #( .INIT(16'h8000)) \occupied_counter.occ_cnt[15]_i_2 (.I0(app_wdf_wren_r1), .I1(app_wdf_end_r1), .I2(app_wdf_rdy_r_copy1), .I3(p_4_in), .O(\occupied_counter.occ_cnt[15]_i_2_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[1]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[0] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[2] ), .O(\occupied_counter.occ_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1515" *) LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[2]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[3] ), .O(\occupied_counter.occ_cnt[2]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[3]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[2] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[4] ), .O(\occupied_counter.occ_cnt[3]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[4]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[3] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[5] ), .O(\occupied_counter.occ_cnt[4]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[5]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[4] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[6] ), .O(\occupied_counter.occ_cnt[5]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[6]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[5] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[7] ), .O(\occupied_counter.occ_cnt[6]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[7]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[6] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[8] ), .O(\occupied_counter.occ_cnt[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1512" *) LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[8]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[7] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[9] ), .O(\occupied_counter.occ_cnt[8]_i_1_n_0 )); LUT5 #( .INIT(32'hBFFF8000)) \occupied_counter.occ_cnt[9]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[8] ), .I1(app_wdf_wren_r1), .I2(app_wdf_end_r1), .I3(app_wdf_rdy_r_copy1), .I4(\occupied_counter.occ_cnt_reg_n_0_[10] ), .O(\occupied_counter.occ_cnt[9]_i_1_n_0 )); FDRE \occupied_counter.occ_cnt_reg[0] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[0]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[0] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[10] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[10]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[10] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[11] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[11]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[11] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[12] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[12]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[12] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[13] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[13]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[13] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[14] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[14]_i_1_n_0 ), .Q(p_4_in), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[15] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[15]_i_2_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[15] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[1] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[1]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[1] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[2] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[2]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[2] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[3] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[3]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[3] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[4] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[4]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[4] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[5] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[5]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[5] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[6] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[6]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[6] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[7] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[7]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[7] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[8] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[8]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[8] ), .R(reset_reg)); FDRE \occupied_counter.occ_cnt_reg[9] (.C(CLK), .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ), .D(\occupied_counter.occ_cnt[9]_i_1_n_0 ), .Q(\occupied_counter.occ_cnt_reg_n_0_[9] ), .R(reset_reg)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \pointer_ram.rams[0].RAM32M0 (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }), .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg__0 }), .ADDRD({1'b0,ADDRD}), .DIA({1'b0,1'b0}), .DIB(pointer_wr_data[1:0]), .DIC(pointer_wr_data[1:0]), .DID({1'b0,1'b0}), .DOA(\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(wr_data_buf_addr[1:0]), .DOC(wr_data_pntr[1:0]), .DOD(\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(pointer_we)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \pointer_ram.rams[1].RAM32M0 (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }), .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg__0 }), .ADDRD({1'b0,ADDRD}), .DIA({1'b0,1'b0}), .DIB(pointer_wr_data[3:2]), .DIC(pointer_wr_data[3:2]), .DID({1'b0,1'b0}), .DOA(\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]), .DOB(wr_data_buf_addr[3:2]), .DOC(wr_data_pntr[3:2]), .DOD(\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(pointer_we)); (* SOFT_HLUTNM = "soft_lutpair1520" *) LUT1 #( .INIT(2'h1)) \read_data_indx.rd_data_indx_r[0]_i_1 (.I0(Q[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair1520" *) LUT2 #( .INIT(4'h6)) \read_data_indx.rd_data_indx_r[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair1517" *) LUT3 #( .INIT(8'h78)) \read_data_indx.rd_data_indx_r[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair1517" *) LUT4 #( .INIT(16'h7F80)) \read_data_indx.rd_data_indx_r[3]_i_1 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(p_0_in__1[3])); FDRE \read_data_indx.rd_data_indx_r_reg[0] (.C(CLK), .CE(E), .D(p_0_in__1[0]), .Q(Q[0]), .R(reset_reg)); FDRE \read_data_indx.rd_data_indx_r_reg[1] (.C(CLK), .CE(E), .D(p_0_in__1[1]), .Q(Q[1]), .R(reset_reg)); FDRE \read_data_indx.rd_data_indx_r_reg[2] (.C(CLK), .CE(E), .D(p_0_in__1[2]), .Q(Q[2]), .R(reset_reg)); FDRE \read_data_indx.rd_data_indx_r_reg[3] (.C(CLK), .CE(E), .D(p_0_in__1[3]), .Q(Q[3]), .R(reset_reg)); FDRE \read_data_indx.rd_data_upd_indx_r_reg (.C(CLK), .CE(1'b1), .D(E), .Q(p_0_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1513" *) LUT4 #( .INIT(16'h0096)) \wr_req_counter.wr_req_cnt_r[0]_i_1 (.I0(p_0_in), .I1(wr_accepted), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I3(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1513" *) LUT5 #( .INIT(32'h0000D2B4)) \wr_req_counter.wr_req_cnt_r[1]_i_1 (.I0(wr_accepted), .I1(p_0_in), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I3(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I4(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000F7EF0810)) \wr_req_counter.wr_req_cnt_r[2]_i_1 (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I2(p_0_in), .I3(wr_accepted), .I4(wr_req_cnt_r[2]), .I5(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FF7E0081)) \wr_req_counter.wr_req_cnt_r[3]_i_1 (.I0(wr_req_cnt_r[2]), .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_1 ), .I3(\read_data_indx.rd_data_upd_indx_r_reg_0 ), .I4(wr_req_cnt_r[3]), .I5(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h000000009CCCCCC9)) \wr_req_counter.wr_req_cnt_r[4]_i_1 (.I0(\read_data_indx.rd_data_upd_indx_r_reg_0 ), .I1(wr_req_cnt_r[4]), .I2(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ), .I3(wr_req_cnt_r[2]), .I4(wr_req_cnt_r[3]), .I5(reset_reg), .O(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 )); LUT4 #( .INIT(16'h80FE)) \wr_req_counter.wr_req_cnt_r[4]_i_2 (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .I1(wr_accepted), .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .I3(wr_req_cnt_r[2]), .O(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 )); FDRE \wr_req_counter.wr_req_cnt_r_reg[0] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ), .Q(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]), .R(1'b0)); FDRE \wr_req_counter.wr_req_cnt_r_reg[1] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ), .Q(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]), .R(1'b0)); FDRE \wr_req_counter.wr_req_cnt_r_reg[2] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ), .Q(wr_req_cnt_r[2]), .R(1'b0)); FDRE \wr_req_counter.wr_req_cnt_r_reg[3] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ), .Q(wr_req_cnt_r[3]), .R(1'b0)); FDRE \wr_req_counter.wr_req_cnt_r_reg[4] (.C(CLK), .CE(1'b1), .D(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ), .Q(wr_req_cnt_r[4]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[0] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[0]), .Q(\my_empty_reg[7] [0]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[100] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[100]), .Q(\my_empty_reg[7] [100]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[101] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[101]), .Q(\my_empty_reg[7] [101]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[102] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[102]), .Q(\my_empty_reg[7] [102]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[103] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[103]), .Q(\my_empty_reg[7] [103]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[104] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[104]), .Q(\my_empty_reg[7] [104]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[105] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[105]), .Q(\my_empty_reg[7] [105]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[106] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[106]), .Q(\my_empty_reg[7] [106]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[107] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[107]), .Q(\my_empty_reg[7] [107]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[108] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[108]), .Q(\my_empty_reg[7] [108]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[109] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[109]), .Q(\my_empty_reg[7] [109]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[10] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[10]), .Q(\my_empty_reg[7] [10]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[110] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[110]), .Q(\my_empty_reg[7] [110]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[111] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[111]), .Q(\my_empty_reg[7] [111]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[112] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[112]), .Q(\my_empty_reg[7] [112]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[113] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[113]), .Q(\my_empty_reg[7] [113]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[114] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[114]), .Q(\my_empty_reg[7] [114]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[115] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[115]), .Q(\my_empty_reg[7] [115]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[116] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[116]), .Q(\my_empty_reg[7] [116]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[117] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[117]), .Q(\my_empty_reg[7] [117]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[118] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[118]), .Q(\my_empty_reg[7] [118]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[119] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[119]), .Q(\my_empty_reg[7] [119]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[11] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[11]), .Q(\my_empty_reg[7] [11]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[120] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[120]), .Q(\my_empty_reg[7] [120]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[121] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[121]), .Q(\my_empty_reg[7] [121]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[122] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[122]), .Q(\my_empty_reg[7] [122]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[123] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[123]), .Q(\my_empty_reg[7] [123]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[124] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[124]), .Q(\my_empty_reg[7] [124]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[125] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[125]), .Q(\my_empty_reg[7] [125]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[126] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[126]), .Q(\my_empty_reg[7] [126]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[127] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[127]), .Q(\my_empty_reg[7] [127]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[128] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[128]), .Q(\my_empty_reg[7] [128]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[129] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[129]), .Q(\my_empty_reg[7] [129]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[12] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[12]), .Q(\my_empty_reg[7] [12]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[130] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[130]), .Q(\my_empty_reg[7] [130]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[131] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[131]), .Q(\my_empty_reg[7] [131]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[132] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[132]), .Q(\my_empty_reg[7] [132]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[133] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[133]), .Q(\my_empty_reg[7] [133]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[134] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[134]), .Q(\my_empty_reg[7] [134]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[135] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[135]), .Q(\my_empty_reg[7] [135]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[136] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[136]), .Q(\my_empty_reg[7] [136]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[137] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[137]), .Q(\my_empty_reg[7] [137]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[138] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[138]), .Q(\my_empty_reg[7] [138]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[139] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[139]), .Q(\my_empty_reg[7] [139]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[13] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[13]), .Q(\my_empty_reg[7] [13]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[140] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[140]), .Q(\my_empty_reg[7] [140]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[141] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[141]), .Q(\my_empty_reg[7] [141]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[142] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[142]), .Q(\my_empty_reg[7] [142]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[143] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[143]), .Q(\my_empty_reg[7] [143]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[144] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[144]), .Q(\my_empty_reg[7] [144]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[145] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[145]), .Q(\my_empty_reg[7] [145]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[146] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[146]), .Q(\my_empty_reg[7] [146]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[147] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[147]), .Q(\my_empty_reg[7] [147]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[148] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[148]), .Q(\my_empty_reg[7] [148]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[149] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[149]), .Q(\my_empty_reg[7] [149]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[14] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[14]), .Q(\my_empty_reg[7] [14]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[150] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[150]), .Q(\my_empty_reg[7] [150]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[151] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[151]), .Q(\my_empty_reg[7] [151]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[152] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[152]), .Q(\my_empty_reg[7] [152]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[153] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[153]), .Q(\my_empty_reg[7] [153]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[154] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[154]), .Q(\my_empty_reg[7] [154]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[155] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[155]), .Q(\my_empty_reg[7] [155]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[156] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[156]), .Q(\my_empty_reg[7] [156]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[157] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[157]), .Q(\my_empty_reg[7] [157]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[158] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[158]), .Q(\my_empty_reg[7] [158]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[159] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[159]), .Q(\my_empty_reg[7] [159]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[15] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[15]), .Q(\my_empty_reg[7] [15]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[160] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[160]), .Q(\my_empty_reg[7] [160]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[161] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[161]), .Q(\my_empty_reg[7] [161]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[162] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[162]), .Q(\my_empty_reg[7] [162]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[163] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[163]), .Q(\my_empty_reg[7] [163]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[164] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[164]), .Q(\my_empty_reg[7] [164]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[165] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[165]), .Q(\my_empty_reg[7] [165]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[166] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[166]), .Q(\my_empty_reg[7] [166]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[167] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[167]), .Q(\my_empty_reg[7] [167]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[168] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[168]), .Q(\my_empty_reg[7] [168]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[169] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[169]), .Q(\my_empty_reg[7] [169]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[16] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[16]), .Q(\my_empty_reg[7] [16]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[170] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[170]), .Q(\my_empty_reg[7] [170]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[171] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[171]), .Q(\my_empty_reg[7] [171]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[172] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[172]), .Q(\my_empty_reg[7] [172]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[173] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[173]), .Q(\my_empty_reg[7] [173]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[174] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[174]), .Q(\my_empty_reg[7] [174]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[175] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[175]), .Q(\my_empty_reg[7] [175]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[176] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[176]), .Q(\my_empty_reg[7] [176]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[177] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[177]), .Q(\my_empty_reg[7] [177]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[178] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[178]), .Q(\my_empty_reg[7] [178]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[179] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[179]), .Q(\my_empty_reg[7] [179]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[17] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[17]), .Q(\my_empty_reg[7] [17]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[180] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[180]), .Q(\my_empty_reg[7] [180]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[181] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[181]), .Q(\my_empty_reg[7] [181]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[182] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[182]), .Q(\my_empty_reg[7] [182]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[183] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[183]), .Q(\my_empty_reg[7] [183]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[184] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[184]), .Q(\my_empty_reg[7] [184]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[185] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[185]), .Q(\my_empty_reg[7] [185]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[186] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[186]), .Q(\my_empty_reg[7] [186]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[187] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[187]), .Q(\my_empty_reg[7] [187]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[188] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[188]), .Q(\my_empty_reg[7] [188]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[189] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[189]), .Q(\my_empty_reg[7] [189]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[18] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[18]), .Q(\my_empty_reg[7] [18]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[190] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[190]), .Q(\my_empty_reg[7] [190]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[191] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[191]), .Q(\my_empty_reg[7] [191]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[192] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[192]), .Q(\my_empty_reg[7] [192]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[193] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[193]), .Q(\my_empty_reg[7] [193]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[194] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[194]), .Q(\my_empty_reg[7] [194]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[195] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[195]), .Q(\my_empty_reg[7] [195]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[196] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[196]), .Q(\my_empty_reg[7] [196]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[197] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[197]), .Q(\my_empty_reg[7] [197]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[198] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[198]), .Q(\my_empty_reg[7] [198]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[199] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[199]), .Q(\my_empty_reg[7] [199]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[19] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[19]), .Q(\my_empty_reg[7] [19]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[1] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[1]), .Q(\my_empty_reg[7] [1]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[200] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[200]), .Q(\my_empty_reg[7] [200]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[201] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[201]), .Q(\my_empty_reg[7] [201]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[202] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[202]), .Q(\my_empty_reg[7] [202]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[203] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[203]), .Q(\my_empty_reg[7] [203]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[204] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[204]), .Q(\my_empty_reg[7] [204]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[205] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[205]), .Q(\my_empty_reg[7] [205]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[206] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[206]), .Q(\my_empty_reg[7] [206]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[207] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[207]), .Q(\my_empty_reg[7] [207]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[208] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[208]), .Q(\my_empty_reg[7] [208]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[209] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[209]), .Q(\my_empty_reg[7] [209]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[20] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[20]), .Q(\my_empty_reg[7] [20]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[210] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[210]), .Q(\my_empty_reg[7] [210]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[211] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[211]), .Q(\my_empty_reg[7] [211]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[212] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[212]), .Q(\my_empty_reg[7] [212]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[213] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[213]), .Q(\my_empty_reg[7] [213]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[214] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[214]), .Q(\my_empty_reg[7] [214]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[215] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[215]), .Q(\my_empty_reg[7] [215]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[216] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[216]), .Q(\my_empty_reg[7] [216]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[217] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[217]), .Q(\my_empty_reg[7] [217]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[218] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[218]), .Q(\my_empty_reg[7] [218]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[219] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[219]), .Q(\my_empty_reg[7] [219]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[21] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[21]), .Q(\my_empty_reg[7] [21]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[220] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[220]), .Q(\my_empty_reg[7] [220]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[221] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[221]), .Q(\my_empty_reg[7] [221]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[222] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[222]), .Q(\my_empty_reg[7] [222]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[223] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[223]), .Q(\my_empty_reg[7] [223]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[224] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[224]), .Q(\my_empty_reg[7] [224]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[225] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[225]), .Q(\my_empty_reg[7] [225]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[226] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[226]), .Q(\my_empty_reg[7] [226]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[227] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[227]), .Q(\my_empty_reg[7] [227]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[228] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[228]), .Q(\my_empty_reg[7] [228]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[229] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[229]), .Q(\my_empty_reg[7] [229]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[22] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[22]), .Q(\my_empty_reg[7] [22]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[230] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[230]), .Q(\my_empty_reg[7] [230]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[231] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[231]), .Q(\my_empty_reg[7] [231]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[232] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[232]), .Q(\my_empty_reg[7] [232]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[233] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[233]), .Q(\my_empty_reg[7] [233]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[234] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[234]), .Q(\my_empty_reg[7] [234]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[235] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[235]), .Q(\my_empty_reg[7] [235]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[236] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[236]), .Q(\my_empty_reg[7] [236]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[237] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[237]), .Q(\my_empty_reg[7] [237]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[238] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[238]), .Q(\my_empty_reg[7] [238]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[239] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[239]), .Q(\my_empty_reg[7] [239]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[23] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[23]), .Q(\my_empty_reg[7] [23]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[240] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[240]), .Q(\my_empty_reg[7] [240]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[241] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[241]), .Q(\my_empty_reg[7] [241]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[242] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[242]), .Q(\my_empty_reg[7] [242]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[243] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[243]), .Q(\my_empty_reg[7] [243]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[244] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[244]), .Q(\my_empty_reg[7] [244]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[245] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[245]), .Q(\my_empty_reg[7] [245]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[246] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[246]), .Q(\my_empty_reg[7] [246]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[247] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[247]), .Q(\my_empty_reg[7] [247]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[248] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[248]), .Q(\my_empty_reg[7] [248]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[249] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[249]), .Q(\my_empty_reg[7] [249]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[24] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[24]), .Q(\my_empty_reg[7] [24]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[250] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[250]), .Q(\my_empty_reg[7] [250]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[251] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[251]), .Q(\my_empty_reg[7] [251]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[252] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[252]), .Q(\my_empty_reg[7] [252]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[253] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[253]), .Q(\my_empty_reg[7] [253]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[254] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[254]), .Q(\my_empty_reg[7] [254]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[255] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[255]), .Q(\my_empty_reg[7] [255]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[256] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[256]), .Q(\my_empty_reg[7] [256]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[257] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[257]), .Q(\my_empty_reg[7] [257]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[258] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[258]), .Q(\my_empty_reg[7] [258]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[259] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[259]), .Q(\my_empty_reg[7] [259]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[25] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[25]), .Q(\my_empty_reg[7] [25]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[260] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[260]), .Q(\my_empty_reg[7] [260]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[261] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[261]), .Q(\my_empty_reg[7] [261]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[262] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[262]), .Q(\my_empty_reg[7] [262]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[263] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[263]), .Q(\my_empty_reg[7] [263]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[264] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[264]), .Q(\my_empty_reg[7] [264]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[265] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[265]), .Q(\my_empty_reg[7] [265]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[266] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[266]), .Q(\my_empty_reg[7] [266]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[267] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[267]), .Q(\my_empty_reg[7] [267]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[268] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[268]), .Q(\my_empty_reg[7] [268]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[269] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[269]), .Q(\my_empty_reg[7] [269]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[26] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[26]), .Q(\my_empty_reg[7] [26]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[270] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[270]), .Q(\my_empty_reg[7] [270]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[271] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[271]), .Q(\my_empty_reg[7] [271]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[272] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[272]), .Q(\my_empty_reg[7] [272]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[273] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[273]), .Q(\my_empty_reg[7] [273]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[274] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[274]), .Q(\my_empty_reg[7] [274]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[275] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[275]), .Q(\my_empty_reg[7] [275]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[276] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[276]), .Q(\my_empty_reg[7] [276]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[277] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[277]), .Q(\my_empty_reg[7] [277]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[278] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[278]), .Q(\my_empty_reg[7] [278]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[279] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[279]), .Q(\my_empty_reg[7] [279]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[27] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[27]), .Q(\my_empty_reg[7] [27]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[280] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[280]), .Q(\my_empty_reg[7] [280]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[281] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[281]), .Q(\my_empty_reg[7] [281]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[282] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[282]), .Q(\my_empty_reg[7] [282]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[283] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[283]), .Q(\my_empty_reg[7] [283]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[284] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[284]), .Q(\my_empty_reg[7] [284]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[285] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[285]), .Q(\my_empty_reg[7] [285]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[286] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[286]), .Q(\my_empty_reg[7] [286]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[287] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[287]), .Q(\my_empty_reg[7] [287]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[28] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[28]), .Q(\my_empty_reg[7] [28]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[29] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[29]), .Q(\my_empty_reg[7] [29]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[2] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[2]), .Q(\my_empty_reg[7] [2]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[30] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[30]), .Q(\my_empty_reg[7] [30]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[31] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[31]), .Q(\my_empty_reg[7] [31]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[32] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[32]), .Q(\my_empty_reg[7] [32]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[33] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[33]), .Q(\my_empty_reg[7] [33]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[34] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[34]), .Q(\my_empty_reg[7] [34]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[35] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[35]), .Q(\my_empty_reg[7] [35]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[36] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[36]), .Q(\my_empty_reg[7] [36]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[37] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[37]), .Q(\my_empty_reg[7] [37]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[38] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[38]), .Q(\my_empty_reg[7] [38]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[39] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[39]), .Q(\my_empty_reg[7] [39]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[3] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[3]), .Q(\my_empty_reg[7] [3]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[40] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[40]), .Q(\my_empty_reg[7] [40]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[41] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[41]), .Q(\my_empty_reg[7] [41]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[42] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[42]), .Q(\my_empty_reg[7] [42]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[43] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[43]), .Q(\my_empty_reg[7] [43]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[44] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[44]), .Q(\my_empty_reg[7] [44]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[45] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[45]), .Q(\my_empty_reg[7] [45]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[46] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[46]), .Q(\my_empty_reg[7] [46]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[47] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[47]), .Q(\my_empty_reg[7] [47]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[48] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[48]), .Q(\my_empty_reg[7] [48]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[49] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[49]), .Q(\my_empty_reg[7] [49]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[4] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[4]), .Q(\my_empty_reg[7] [4]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[50] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[50]), .Q(\my_empty_reg[7] [50]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[51] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[51]), .Q(\my_empty_reg[7] [51]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[52] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[52]), .Q(\my_empty_reg[7] [52]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[53] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[53]), .Q(\my_empty_reg[7] [53]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[54] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[54]), .Q(\my_empty_reg[7] [54]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[55] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[55]), .Q(\my_empty_reg[7] [55]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[56] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[56]), .Q(\my_empty_reg[7] [56]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[57] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[57]), .Q(\my_empty_reg[7] [57]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[58] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[58]), .Q(\my_empty_reg[7] [58]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[59] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[59]), .Q(\my_empty_reg[7] [59]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[5] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[5]), .Q(\my_empty_reg[7] [5]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[60] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[60]), .Q(\my_empty_reg[7] [60]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[61] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[61]), .Q(\my_empty_reg[7] [61]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[62] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[62]), .Q(\my_empty_reg[7] [62]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[63] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[63]), .Q(\my_empty_reg[7] [63]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[64] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[64]), .Q(\my_empty_reg[7] [64]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[65] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[65]), .Q(\my_empty_reg[7] [65]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[66] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[66]), .Q(\my_empty_reg[7] [66]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[67] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[67]), .Q(\my_empty_reg[7] [67]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[68] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[68]), .Q(\my_empty_reg[7] [68]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[69] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[69]), .Q(\my_empty_reg[7] [69]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[6] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[6]), .Q(\my_empty_reg[7] [6]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[70] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[70]), .Q(\my_empty_reg[7] [70]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[71] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[71]), .Q(\my_empty_reg[7] [71]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[72] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[72]), .Q(\my_empty_reg[7] [72]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[73] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[73]), .Q(\my_empty_reg[7] [73]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[74] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[74]), .Q(\my_empty_reg[7] [74]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[75] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[75]), .Q(\my_empty_reg[7] [75]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[76] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[76]), .Q(\my_empty_reg[7] [76]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[77] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[77]), .Q(\my_empty_reg[7] [77]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[78] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[78]), .Q(\my_empty_reg[7] [78]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[79] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[79]), .Q(\my_empty_reg[7] [79]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[7] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[7]), .Q(\my_empty_reg[7] [7]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[80] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[80]), .Q(\my_empty_reg[7] [80]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[81] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[81]), .Q(\my_empty_reg[7] [81]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[82] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[82]), .Q(\my_empty_reg[7] [82]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[83] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[83]), .Q(\my_empty_reg[7] [83]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[84] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[84]), .Q(\my_empty_reg[7] [84]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[85] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[85]), .Q(\my_empty_reg[7] [85]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[86] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[86]), .Q(\my_empty_reg[7] [86]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[87] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[87]), .Q(\my_empty_reg[7] [87]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[88] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[88]), .Q(\my_empty_reg[7] [88]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[89] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[89]), .Q(\my_empty_reg[7] [89]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[8] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[8]), .Q(\my_empty_reg[7] [8]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[90] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[90]), .Q(\my_empty_reg[7] [90]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[91] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[91]), .Q(\my_empty_reg[7] [91]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[92] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[92]), .Q(\my_empty_reg[7] [92]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[93] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[93]), .Q(\my_empty_reg[7] [93]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[94] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[94]), .Q(\my_empty_reg[7] [94]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[95] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[95]), .Q(\my_empty_reg[7] [95]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[96] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[96]), .Q(\my_empty_reg[7] [96]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[97] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[97]), .Q(\my_empty_reg[7] [97]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[98] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[98]), .Q(\my_empty_reg[7] [98]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[99] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[99]), .Q(\my_empty_reg[7] [99]), .R(1'b0)); FDRE \write_buffer.wr_buf_out_data_reg[9] (.C(CLK), .CE(1'b1), .D(wr_buf_out_data_w[9]), .Q(\my_empty_reg[7] [9]), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[0].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[5:4]), .DIB(wr_buf_in_data[3:2]), .DIC(wr_buf_in_data[1:0]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[5:4]), .DOB(wr_buf_out_data_w[3:2]), .DOC(wr_buf_out_data_w[1:0]), .DOD(\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT6 #( .INIT(64'h4040404040444444)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_1 (.I0(reset_reg), .I1(ram_init_done_r), .I2(p_0_in), .I3(p_0_in__0_0), .I4(p_4_in), .I5(\occupied_counter.occ_cnt_reg_n_0_[15] ), .O(wdf_rdy_ns)); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_10 (.I0(wr_data_pntr[1]), .I1(wb_wr_data_addr_r[2]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[2])); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_11 (.I0(wr_data_pntr[0]), .I1(wb_wr_data_addr_r[1]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[1])); LUT5 #( .INIT(32'h02020F00)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_12 (.I0(app_wdf_rdy_r_copy3), .I1(app_wdf_end_r1), .I2(reset_reg), .I3(wb_wr_data_addr0_r), .I4(app_wdf_wren_r1), .O(wb_wr_data_addr0_ns)); (* SOFT_HLUTNM = "soft_lutpair1512" *) LUT3 #( .INIT(8'h80)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_13 (.I0(app_wdf_wren_r1), .I1(app_wdf_end_r1), .I2(app_wdf_rdy_r_copy1), .O(p_0_in__0_0)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_2 (.I0(wready_reg_rep__1[5]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[5]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[5]), .O(wr_buf_in_data[5])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_3 (.I0(wready_reg_rep__1[4]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[4]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[4]), .O(wr_buf_in_data[4])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_4 (.I0(wready_reg_rep__1[3]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[3]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[3]), .O(wr_buf_in_data[3])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_5 (.I0(wready_reg_rep__1[2]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[2]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[2]), .O(wr_buf_in_data[2])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_6 (.I0(wready_reg_rep__1[1]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[1]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[1]), .O(wr_buf_in_data[1])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_7 (.I0(wready_reg_rep__1[0]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[0]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[0]), .O(wr_buf_in_data[0])); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_8 (.I0(wr_data_pntr[3]), .I1(wb_wr_data_addr_r[4]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[4])); LUT4 #( .INIT(16'h00AC)) \write_buffer.wr_buffer_ram[0].RAM32M0_i_9 (.I0(wr_data_pntr[2]), .I1(wb_wr_data_addr_r[3]), .I2(wr_data_addr_le), .I3(reset_reg), .O(wb_wr_data_addr_w[3])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[10].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[65:64]), .DIB(wr_buf_in_data[63:62]), .DIC(wr_buf_in_data[61:60]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[65:64]), .DOB(wr_buf_out_data_w[63:62]), .DOC(wr_buf_out_data_w[61:60]), .DOD(\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_1 (.I0(wready_reg_rep__1[65]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[65]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[65]), .O(wr_buf_in_data[65])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_2 (.I0(wready_reg_rep__1[64]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[64]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[64]), .O(wr_buf_in_data[64])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_3 (.I0(wready_reg_rep__1[63]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[63]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[63]), .O(wr_buf_in_data[63])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_4 (.I0(wready_reg_rep__1[62]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[62]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[62]), .O(wr_buf_in_data[62])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_5 (.I0(wready_reg_rep__1[61]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[61]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[61]), .O(wr_buf_in_data[61])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[10].RAM32M0_i_6 (.I0(wready_reg_rep__1[60]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[60]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[60]), .O(wr_buf_in_data[60])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[11].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[71:70]), .DIB(wr_buf_in_data[69:68]), .DIC(wr_buf_in_data[67:66]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[71:70]), .DOB(wr_buf_out_data_w[69:68]), .DOC(wr_buf_out_data_w[67:66]), .DOD(\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_1 (.I0(wready_reg_rep__1[71]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[71]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[71]), .O(wr_buf_in_data[71])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_2 (.I0(wready_reg_rep__1[70]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[70]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[70]), .O(wr_buf_in_data[70])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_3 (.I0(wready_reg_rep__1[69]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[69]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[69]), .O(wr_buf_in_data[69])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_4 (.I0(wready_reg_rep__1[68]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[68]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[68]), .O(wr_buf_in_data[68])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_5 (.I0(wready_reg_rep__1[67]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[67]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[67]), .O(wr_buf_in_data[67])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[11].RAM32M0_i_6 (.I0(wready_reg_rep__1[66]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[66]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[66]), .O(wr_buf_in_data[66])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[12].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[77:76]), .DIB(wr_buf_in_data[75:74]), .DIC(wr_buf_in_data[73:72]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[77:76]), .DOB(wr_buf_out_data_w[75:74]), .DOC(wr_buf_out_data_w[73:72]), .DOD(\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_1 (.I0(wready_reg_rep__1[77]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[77]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[77]), .O(wr_buf_in_data[77])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_2 (.I0(wready_reg_rep__1[76]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[76]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[76]), .O(wr_buf_in_data[76])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_3 (.I0(wready_reg_rep__1[75]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[75]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[75]), .O(wr_buf_in_data[75])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_4 (.I0(wready_reg_rep__1[74]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[74]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[74]), .O(wr_buf_in_data[74])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_5 (.I0(wready_reg_rep__1[73]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[73]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[73]), .O(wr_buf_in_data[73])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[12].RAM32M0_i_6 (.I0(wready_reg_rep__1[72]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[72]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[72]), .O(wr_buf_in_data[72])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[13].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[83:82]), .DIB(wr_buf_in_data[81:80]), .DIC(wr_buf_in_data[79:78]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[83:82]), .DOB(wr_buf_out_data_w[81:80]), .DOC(wr_buf_out_data_w[79:78]), .DOD(\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_1 (.I0(wready_reg_rep__1[83]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[83]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[83]), .O(wr_buf_in_data[83])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_2 (.I0(wready_reg_rep__1[82]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[82]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[82]), .O(wr_buf_in_data[82])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_3 (.I0(wready_reg_rep__1[81]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[81]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[81]), .O(wr_buf_in_data[81])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_4 (.I0(wready_reg_rep__1[80]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[80]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[80]), .O(wr_buf_in_data[80])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_5 (.I0(wready_reg_rep__1[79]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[79]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[79]), .O(wr_buf_in_data[79])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[13].RAM32M0_i_6 (.I0(wready_reg_rep__1[78]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[78]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[78]), .O(wr_buf_in_data[78])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[14].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[89:88]), .DIB(wr_buf_in_data[87:86]), .DIC(wr_buf_in_data[85:84]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[89:88]), .DOB(wr_buf_out_data_w[87:86]), .DOC(wr_buf_out_data_w[85:84]), .DOD(\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_1 (.I0(wready_reg_rep__1[89]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[89]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[89]), .O(wr_buf_in_data[89])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_2 (.I0(wready_reg_rep__1[88]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[88]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[88]), .O(wr_buf_in_data[88])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_3 (.I0(wready_reg_rep__1[87]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[87]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[87]), .O(wr_buf_in_data[87])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_4 (.I0(wready_reg_rep__1[86]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[86]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[86]), .O(wr_buf_in_data[86])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_5 (.I0(wready_reg_rep__1[85]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[85]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[85]), .O(wr_buf_in_data[85])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[14].RAM32M0_i_6 (.I0(wready_reg_rep__1[84]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[84]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[84]), .O(wr_buf_in_data[84])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[15].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[95:94]), .DIB(wr_buf_in_data[93:92]), .DIC(wr_buf_in_data[91:90]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[95:94]), .DOB(wr_buf_out_data_w[93:92]), .DOC(wr_buf_out_data_w[91:90]), .DOD(\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_1 (.I0(wready_reg_rep__1[95]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[95]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[95]), .O(wr_buf_in_data[95])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_2 (.I0(wready_reg_rep__1[94]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[94]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[94]), .O(wr_buf_in_data[94])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_3 (.I0(wready_reg_rep__1[93]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[93]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[93]), .O(wr_buf_in_data[93])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_4 (.I0(wready_reg_rep__1[92]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[92]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[92]), .O(wr_buf_in_data[92])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_5 (.I0(wready_reg_rep__1[91]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[91]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[91]), .O(wr_buf_in_data[91])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[15].RAM32M0_i_6 (.I0(wready_reg_rep__1[90]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[90]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[90]), .O(wr_buf_in_data[90])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[16].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[101:100]), .DIB(wr_buf_in_data[99:98]), .DIC(wr_buf_in_data[97:96]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[101:100]), .DOB(wr_buf_out_data_w[99:98]), .DOC(wr_buf_out_data_w[97:96]), .DOD(\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_1 (.I0(wready_reg_rep__1[101]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[101]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[101]), .O(wr_buf_in_data[101])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_2 (.I0(wready_reg_rep__1[100]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[100]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[100]), .O(wr_buf_in_data[100])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_3 (.I0(wready_reg_rep__1[99]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[99]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[99]), .O(wr_buf_in_data[99])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_4 (.I0(wready_reg_rep__1[98]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[98]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[98]), .O(wr_buf_in_data[98])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_5 (.I0(wready_reg_rep__1[97]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[97]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[97]), .O(wr_buf_in_data[97])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[16].RAM32M0_i_6 (.I0(wready_reg_rep__1[96]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[96]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[96]), .O(wr_buf_in_data[96])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[17].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[107:106]), .DIB(wr_buf_in_data[105:104]), .DIC(wr_buf_in_data[103:102]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[107:106]), .DOB(wr_buf_out_data_w[105:104]), .DOC(wr_buf_out_data_w[103:102]), .DOD(\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_1 (.I0(wready_reg_rep__1[107]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[107]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[107]), .O(wr_buf_in_data[107])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_2 (.I0(wready_reg_rep__1[106]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[106]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[106]), .O(wr_buf_in_data[106])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_3 (.I0(wready_reg_rep__1[105]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[105]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[105]), .O(wr_buf_in_data[105])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_4 (.I0(wready_reg_rep__1[104]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[104]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[104]), .O(wr_buf_in_data[104])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_5 (.I0(wready_reg_rep__1[103]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[103]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[103]), .O(wr_buf_in_data[103])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[17].RAM32M0_i_6 (.I0(wready_reg_rep__1[102]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[102]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[102]), .O(wr_buf_in_data[102])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[18].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[113:112]), .DIB(wr_buf_in_data[111:110]), .DIC(wr_buf_in_data[109:108]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[113:112]), .DOB(wr_buf_out_data_w[111:110]), .DOC(wr_buf_out_data_w[109:108]), .DOD(\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_1 (.I0(wready_reg_rep__1[113]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[113]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[113]), .O(wr_buf_in_data[113])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_2 (.I0(wready_reg_rep__1[112]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[112]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[112]), .O(wr_buf_in_data[112])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_3 (.I0(wready_reg_rep__1[111]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[111]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[111]), .O(wr_buf_in_data[111])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_4 (.I0(wready_reg_rep__1[110]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[110]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[110]), .O(wr_buf_in_data[110])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_5 (.I0(wready_reg_rep__1[109]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[109]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[109]), .O(wr_buf_in_data[109])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[18].RAM32M0_i_6 (.I0(wready_reg_rep__1[108]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[108]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[108]), .O(wr_buf_in_data[108])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[19].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[119:118]), .DIB(wr_buf_in_data[117:116]), .DIC(wr_buf_in_data[115:114]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[119:118]), .DOB(wr_buf_out_data_w[117:116]), .DOC(wr_buf_out_data_w[115:114]), .DOD(\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_1 (.I0(wready_reg_rep__1[119]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[119]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[119]), .O(wr_buf_in_data[119])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_2 (.I0(wready_reg_rep__1[118]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[118]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[118]), .O(wr_buf_in_data[118])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_3 (.I0(wready_reg_rep__1[117]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[117]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[117]), .O(wr_buf_in_data[117])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_4 (.I0(wready_reg_rep__1[116]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[116]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[116]), .O(wr_buf_in_data[116])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_5 (.I0(wready_reg_rep__1[115]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[115]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[115]), .O(wr_buf_in_data[115])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[19].RAM32M0_i_6 (.I0(wready_reg_rep__1[114]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[114]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[114]), .O(wr_buf_in_data[114])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[1].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[11:10]), .DIB(wr_buf_in_data[9:8]), .DIC(wr_buf_in_data[7:6]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[11:10]), .DOB(wr_buf_out_data_w[9:8]), .DOC(wr_buf_out_data_w[7:6]), .DOD(\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_1 (.I0(wready_reg_rep__1[11]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[11]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[11]), .O(wr_buf_in_data[11])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_2 (.I0(wready_reg_rep__1[10]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[10]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[10]), .O(wr_buf_in_data[10])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_3 (.I0(wready_reg_rep__1[9]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[9]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[9]), .O(wr_buf_in_data[9])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_4 (.I0(wready_reg_rep__1[8]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[8]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[8]), .O(wr_buf_in_data[8])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_5 (.I0(wready_reg_rep__1[7]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[7]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[7]), .O(wr_buf_in_data[7])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[1].RAM32M0_i_6 (.I0(wready_reg_rep__1[6]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[6]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[6]), .O(wr_buf_in_data[6])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[20].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[125:124]), .DIB(wr_buf_in_data[123:122]), .DIC(wr_buf_in_data[121:120]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[125:124]), .DOB(wr_buf_out_data_w[123:122]), .DOC(wr_buf_out_data_w[121:120]), .DOD(\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_1 (.I0(wready_reg_rep__1[125]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[125]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[125]), .O(wr_buf_in_data[125])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_2 (.I0(wready_reg_rep__1[124]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[124]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[124]), .O(wr_buf_in_data[124])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_3 (.I0(wready_reg_rep__1[123]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[123]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[123]), .O(wr_buf_in_data[123])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_4 (.I0(wready_reg_rep__1[122]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[122]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[122]), .O(wr_buf_in_data[122])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_5 (.I0(wready_reg_rep__1[121]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[121]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[121]), .O(wr_buf_in_data[121])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[20].RAM32M0_i_6 (.I0(wready_reg_rep__1[120]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[120]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[120]), .O(wr_buf_in_data[120])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[21].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[131:130]), .DIB(wr_buf_in_data[129:128]), .DIC(wr_buf_in_data[127:126]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[131:130]), .DOB(wr_buf_out_data_w[129:128]), .DOC(wr_buf_out_data_w[127:126]), .DOD(\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_1 (.I0(wready_reg_rep__1[131]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[131]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[131]), .O(wr_buf_in_data[131])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_2 (.I0(wready_reg_rep__1[130]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[130]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[130]), .O(wr_buf_in_data[130])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_3 (.I0(wready_reg_rep__1[129]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[129]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[129]), .O(wr_buf_in_data[129])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_4 (.I0(wready_reg_rep__1[128]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[128]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[128]), .O(wr_buf_in_data[128])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_5 (.I0(wready_reg_rep__1[127]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[127]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[127]), .O(wr_buf_in_data[127])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[21].RAM32M0_i_6 (.I0(wready_reg_rep__1[126]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[126]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[126]), .O(wr_buf_in_data[126])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[22].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[137:136]), .DIB(wr_buf_in_data[135:134]), .DIC(wr_buf_in_data[133:132]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[137:136]), .DOB(wr_buf_out_data_w[135:134]), .DOC(wr_buf_out_data_w[133:132]), .DOD(\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_1 (.I0(wready_reg_rep__1[137]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[137]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[137]), .O(wr_buf_in_data[137])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_2 (.I0(wready_reg_rep__1[136]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[136]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[136]), .O(wr_buf_in_data[136])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_3 (.I0(wready_reg_rep__1[135]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[135]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[135]), .O(wr_buf_in_data[135])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_4 (.I0(wready_reg_rep__1[134]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[134]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[134]), .O(wr_buf_in_data[134])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_5 (.I0(wready_reg_rep__1[133]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[133]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[133]), .O(wr_buf_in_data[133])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[22].RAM32M0_i_6 (.I0(wready_reg_rep__1[132]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[132]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[132]), .O(wr_buf_in_data[132])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[23].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[143:142]), .DIB(wr_buf_in_data[141:140]), .DIC(wr_buf_in_data[139:138]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[143:142]), .DOB(wr_buf_out_data_w[141:140]), .DOC(wr_buf_out_data_w[139:138]), .DOD(\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_1 (.I0(wready_reg_rep__1[143]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[143]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[143]), .O(wr_buf_in_data[143])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_2 (.I0(wready_reg_rep__1[142]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[142]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[142]), .O(wr_buf_in_data[142])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_3 (.I0(wready_reg_rep__1[141]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[141]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[141]), .O(wr_buf_in_data[141])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_4 (.I0(wready_reg_rep__1[140]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[140]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[140]), .O(wr_buf_in_data[140])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_5 (.I0(wready_reg_rep__1[139]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[139]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[139]), .O(wr_buf_in_data[139])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[23].RAM32M0_i_6 (.I0(wready_reg_rep__1[138]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[138]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[138]), .O(wr_buf_in_data[138])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[24].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[149:148]), .DIB(wr_buf_in_data[147:146]), .DIC(wr_buf_in_data[145:144]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[149:148]), .DOB(wr_buf_out_data_w[147:146]), .DOC(wr_buf_out_data_w[145:144]), .DOD(\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_1 (.I0(wready_reg_rep__1[149]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[149]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[149]), .O(wr_buf_in_data[149])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_2 (.I0(wready_reg_rep__1[148]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[148]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[148]), .O(wr_buf_in_data[148])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_3 (.I0(wready_reg_rep__1[147]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[147]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[147]), .O(wr_buf_in_data[147])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_4 (.I0(wready_reg_rep__1[146]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[146]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[146]), .O(wr_buf_in_data[146])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_5 (.I0(wready_reg_rep__1[145]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[145]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[145]), .O(wr_buf_in_data[145])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[24].RAM32M0_i_6 (.I0(wready_reg_rep__1[144]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[144]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[144]), .O(wr_buf_in_data[144])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[25].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[155:154]), .DIB(wr_buf_in_data[153:152]), .DIC(wr_buf_in_data[151:150]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[155:154]), .DOB(wr_buf_out_data_w[153:152]), .DOC(wr_buf_out_data_w[151:150]), .DOD(\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_1 (.I0(wready_reg_rep__1[155]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[155]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[155]), .O(wr_buf_in_data[155])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_2 (.I0(wready_reg_rep__1[154]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[154]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[154]), .O(wr_buf_in_data[154])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_3 (.I0(wready_reg_rep__1[153]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[153]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[153]), .O(wr_buf_in_data[153])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_4 (.I0(wready_reg_rep__1[152]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[152]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[152]), .O(wr_buf_in_data[152])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_5 (.I0(wready_reg_rep__1[151]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[151]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[151]), .O(wr_buf_in_data[151])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[25].RAM32M0_i_6 (.I0(wready_reg_rep__1[150]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[150]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[150]), .O(wr_buf_in_data[150])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[26].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[161:160]), .DIB(wr_buf_in_data[159:158]), .DIC(wr_buf_in_data[157:156]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[161:160]), .DOB(wr_buf_out_data_w[159:158]), .DOC(wr_buf_out_data_w[157:156]), .DOD(\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_1 (.I0(wready_reg_rep__1[161]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[161]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[161]), .O(wr_buf_in_data[161])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_2 (.I0(wready_reg_rep__1[160]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[160]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[160]), .O(wr_buf_in_data[160])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_3 (.I0(wready_reg_rep__1[159]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[159]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[159]), .O(wr_buf_in_data[159])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_4 (.I0(wready_reg_rep__1[158]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[158]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[158]), .O(wr_buf_in_data[158])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_5 (.I0(wready_reg_rep__1[157]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[157]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[157]), .O(wr_buf_in_data[157])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[26].RAM32M0_i_6 (.I0(wready_reg_rep__1[156]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[156]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[156]), .O(wr_buf_in_data[156])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[27].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[167:166]), .DIB(wr_buf_in_data[165:164]), .DIC(wr_buf_in_data[163:162]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[167:166]), .DOB(wr_buf_out_data_w[165:164]), .DOC(wr_buf_out_data_w[163:162]), .DOD(\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_1 (.I0(wready_reg_rep__1[167]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[167]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[167]), .O(wr_buf_in_data[167])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_2 (.I0(wready_reg_rep__1[166]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[166]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[166]), .O(wr_buf_in_data[166])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_3 (.I0(wready_reg_rep__1[165]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[165]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[165]), .O(wr_buf_in_data[165])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_4 (.I0(wready_reg_rep__1[164]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[164]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[164]), .O(wr_buf_in_data[164])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_5 (.I0(wready_reg_rep__1[163]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[163]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[163]), .O(wr_buf_in_data[163])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[27].RAM32M0_i_6 (.I0(wready_reg_rep__1[162]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[162]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[162]), .O(wr_buf_in_data[162])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[28].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[173:172]), .DIB(wr_buf_in_data[171:170]), .DIC(wr_buf_in_data[169:168]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[173:172]), .DOB(wr_buf_out_data_w[171:170]), .DOC(wr_buf_out_data_w[169:168]), .DOD(\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_1 (.I0(wready_reg_rep__1[173]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[173]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[173]), .O(wr_buf_in_data[173])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_2 (.I0(wready_reg_rep__1[172]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[172]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[172]), .O(wr_buf_in_data[172])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_3 (.I0(wready_reg_rep__1[171]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[171]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[171]), .O(wr_buf_in_data[171])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_4 (.I0(wready_reg_rep__1[170]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[170]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[170]), .O(wr_buf_in_data[170])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_5 (.I0(wready_reg_rep__1[169]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[169]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[169]), .O(wr_buf_in_data[169])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[28].RAM32M0_i_6 (.I0(wready_reg_rep__1[168]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[168]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[168]), .O(wr_buf_in_data[168])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[29].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[179:178]), .DIB(wr_buf_in_data[177:176]), .DIC(wr_buf_in_data[175:174]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[179:178]), .DOB(wr_buf_out_data_w[177:176]), .DOC(wr_buf_out_data_w[175:174]), .DOD(\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_1 (.I0(wready_reg_rep__1[179]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[179]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[179]), .O(wr_buf_in_data[179])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_2 (.I0(wready_reg_rep__1[178]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[178]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[178]), .O(wr_buf_in_data[178])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_3 (.I0(wready_reg_rep__1[177]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[177]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[177]), .O(wr_buf_in_data[177])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_4 (.I0(wready_reg_rep__1[176]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[176]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[176]), .O(wr_buf_in_data[176])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_5 (.I0(wready_reg_rep__1[175]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[175]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[175]), .O(wr_buf_in_data[175])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[29].RAM32M0_i_6 (.I0(wready_reg_rep__1[174]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[174]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[174]), .O(wr_buf_in_data[174])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[2].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[17:16]), .DIB(wr_buf_in_data[15:14]), .DIC(wr_buf_in_data[13:12]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[17:16]), .DOB(wr_buf_out_data_w[15:14]), .DOC(wr_buf_out_data_w[13:12]), .DOD(\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_1 (.I0(wready_reg_rep__1[17]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[17]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[17]), .O(wr_buf_in_data[17])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_2 (.I0(wready_reg_rep__1[16]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[16]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[16]), .O(wr_buf_in_data[16])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_3 (.I0(wready_reg_rep__1[15]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[15]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[15]), .O(wr_buf_in_data[15])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_4 (.I0(wready_reg_rep__1[14]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[14]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[14]), .O(wr_buf_in_data[14])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_5 (.I0(wready_reg_rep__1[13]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[13]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[13]), .O(wr_buf_in_data[13])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[2].RAM32M0_i_6 (.I0(wready_reg_rep__1[12]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[12]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[12]), .O(wr_buf_in_data[12])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[30].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[185:184]), .DIB(wr_buf_in_data[183:182]), .DIC(wr_buf_in_data[181:180]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[185:184]), .DOB(wr_buf_out_data_w[183:182]), .DOC(wr_buf_out_data_w[181:180]), .DOD(\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_1 (.I0(wready_reg_rep__1[185]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[185]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[185]), .O(wr_buf_in_data[185])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_2 (.I0(wready_reg_rep__1[184]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[184]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[184]), .O(wr_buf_in_data[184])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_3 (.I0(wready_reg_rep__1[183]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[183]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[183]), .O(wr_buf_in_data[183])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_4 (.I0(wready_reg_rep__1[182]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[182]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[182]), .O(wr_buf_in_data[182])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_5 (.I0(wready_reg_rep__1[181]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[181]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[181]), .O(wr_buf_in_data[181])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[30].RAM32M0_i_6 (.I0(wready_reg_rep__1[180]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[180]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[180]), .O(wr_buf_in_data[180])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[31].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[191:190]), .DIB(wr_buf_in_data[189:188]), .DIC(wr_buf_in_data[187:186]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[191:190]), .DOB(wr_buf_out_data_w[189:188]), .DOC(wr_buf_out_data_w[187:186]), .DOD(\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_1 (.I0(wready_reg_rep__1[191]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[191]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[191]), .O(wr_buf_in_data[191])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_2 (.I0(wready_reg_rep__1[190]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[190]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[190]), .O(wr_buf_in_data[190])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_3 (.I0(wready_reg_rep__1[189]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[189]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[189]), .O(wr_buf_in_data[189])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_4 (.I0(wready_reg_rep__1[188]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[188]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[188]), .O(wr_buf_in_data[188])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_5 (.I0(wready_reg_rep__1[187]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[187]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[187]), .O(wr_buf_in_data[187])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[31].RAM32M0_i_6 (.I0(wready_reg_rep__1[186]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[186]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[186]), .O(wr_buf_in_data[186])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[32].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[197:196]), .DIB(wr_buf_in_data[195:194]), .DIC(wr_buf_in_data[193:192]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[197:196]), .DOB(wr_buf_out_data_w[195:194]), .DOC(wr_buf_out_data_w[193:192]), .DOD(\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_1 (.I0(wready_reg_rep__1[197]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[197]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[197]), .O(wr_buf_in_data[197])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_2 (.I0(wready_reg_rep__1[196]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[196]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[196]), .O(wr_buf_in_data[196])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_3 (.I0(wready_reg_rep__1[195]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[195]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[195]), .O(wr_buf_in_data[195])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_4 (.I0(wready_reg_rep__1[194]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[194]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[194]), .O(wr_buf_in_data[194])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_5 (.I0(wready_reg_rep__1[193]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[193]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[193]), .O(wr_buf_in_data[193])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[32].RAM32M0_i_6 (.I0(wready_reg_rep__1[192]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[192]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[192]), .O(wr_buf_in_data[192])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[33].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[203:202]), .DIB(wr_buf_in_data[201:200]), .DIC(wr_buf_in_data[199:198]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[203:202]), .DOB(wr_buf_out_data_w[201:200]), .DOC(wr_buf_out_data_w[199:198]), .DOD(\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_1 (.I0(wready_reg_rep__1[203]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[203]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[203]), .O(wr_buf_in_data[203])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_2 (.I0(wready_reg_rep__1[202]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[202]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[202]), .O(wr_buf_in_data[202])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_3 (.I0(wready_reg_rep__1[201]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[201]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[201]), .O(wr_buf_in_data[201])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_4 (.I0(wready_reg_rep__1[200]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[200]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[200]), .O(wr_buf_in_data[200])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_5 (.I0(wready_reg_rep__1[199]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[199]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[199]), .O(wr_buf_in_data[199])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[33].RAM32M0_i_6 (.I0(wready_reg_rep__1[198]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[198]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[198]), .O(wr_buf_in_data[198])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[34].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[209:208]), .DIB(wr_buf_in_data[207:206]), .DIC(wr_buf_in_data[205:204]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[209:208]), .DOB(wr_buf_out_data_w[207:206]), .DOC(wr_buf_out_data_w[205:204]), .DOD(\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_1 (.I0(wready_reg_rep__1[209]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[209]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[209]), .O(wr_buf_in_data[209])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_2 (.I0(wready_reg_rep__1[208]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[208]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[208]), .O(wr_buf_in_data[208])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_3 (.I0(wready_reg_rep__1[207]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[207]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[207]), .O(wr_buf_in_data[207])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_4 (.I0(wready_reg_rep__1[206]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[206]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[206]), .O(wr_buf_in_data[206])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_5 (.I0(wready_reg_rep__1[205]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[205]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[205]), .O(wr_buf_in_data[205])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[34].RAM32M0_i_6 (.I0(wready_reg_rep__1[204]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[204]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[204]), .O(wr_buf_in_data[204])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[35].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[215:214]), .DIB(wr_buf_in_data[213:212]), .DIC(wr_buf_in_data[211:210]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[215:214]), .DOB(wr_buf_out_data_w[213:212]), .DOC(wr_buf_out_data_w[211:210]), .DOD(\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_1 (.I0(wready_reg_rep__1[215]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[215]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[215]), .O(wr_buf_in_data[215])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_2 (.I0(wready_reg_rep__1[214]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[214]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[214]), .O(wr_buf_in_data[214])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_3 (.I0(wready_reg_rep__1[213]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[213]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[213]), .O(wr_buf_in_data[213])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_4 (.I0(wready_reg_rep__1[212]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[212]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[212]), .O(wr_buf_in_data[212])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_5 (.I0(wready_reg_rep__1[211]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[211]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[211]), .O(wr_buf_in_data[211])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[35].RAM32M0_i_6 (.I0(wready_reg_rep__1[210]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[210]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[210]), .O(wr_buf_in_data[210])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[36].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[221:220]), .DIB(wr_buf_in_data[219:218]), .DIC(wr_buf_in_data[217:216]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[221:220]), .DOB(wr_buf_out_data_w[219:218]), .DOC(wr_buf_out_data_w[217:216]), .DOD(\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_1 (.I0(wready_reg_rep__1[221]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[221]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[221]), .O(wr_buf_in_data[221])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_2 (.I0(wready_reg_rep__1[220]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[220]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[220]), .O(wr_buf_in_data[220])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_3 (.I0(wready_reg_rep__1[219]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[219]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[219]), .O(wr_buf_in_data[219])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_4 (.I0(wready_reg_rep__1[218]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[218]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[218]), .O(wr_buf_in_data[218])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_5 (.I0(wready_reg_rep__1[217]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[217]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[217]), .O(wr_buf_in_data[217])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[36].RAM32M0_i_6 (.I0(wready_reg_rep__1[216]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[216]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[216]), .O(wr_buf_in_data[216])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[37].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[227:226]), .DIB(wr_buf_in_data[225:224]), .DIC(wr_buf_in_data[223:222]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[227:226]), .DOB(wr_buf_out_data_w[225:224]), .DOC(wr_buf_out_data_w[223:222]), .DOD(\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_1 (.I0(wready_reg_rep__1[227]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[227]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[227]), .O(wr_buf_in_data[227])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_2 (.I0(wready_reg_rep__1[226]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[226]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[226]), .O(wr_buf_in_data[226])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_3 (.I0(wready_reg_rep__1[225]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[225]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[225]), .O(wr_buf_in_data[225])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_4 (.I0(wready_reg_rep__1[224]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[224]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[224]), .O(wr_buf_in_data[224])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_5 (.I0(wready_reg_rep__1[223]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[223]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[223]), .O(wr_buf_in_data[223])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[37].RAM32M0_i_6 (.I0(wready_reg_rep__1[222]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[222]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[222]), .O(wr_buf_in_data[222])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[38].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[233:232]), .DIB(wr_buf_in_data[231:230]), .DIC(wr_buf_in_data[229:228]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[233:232]), .DOB(wr_buf_out_data_w[231:230]), .DOC(wr_buf_out_data_w[229:228]), .DOD(\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_1 (.I0(wready_reg_rep__1[233]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[233]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[233]), .O(wr_buf_in_data[233])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_2 (.I0(wready_reg_rep__1[232]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[232]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[232]), .O(wr_buf_in_data[232])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_3 (.I0(wready_reg_rep__1[231]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[231]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[231]), .O(wr_buf_in_data[231])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_4 (.I0(wready_reg_rep__1[230]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[230]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[230]), .O(wr_buf_in_data[230])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_5 (.I0(wready_reg_rep__1[229]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[229]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[229]), .O(wr_buf_in_data[229])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[38].RAM32M0_i_6 (.I0(wready_reg_rep__1[228]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[228]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[228]), .O(wr_buf_in_data[228])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[39].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[239:238]), .DIB(wr_buf_in_data[237:236]), .DIC(wr_buf_in_data[235:234]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[239:238]), .DOB(wr_buf_out_data_w[237:236]), .DOC(wr_buf_out_data_w[235:234]), .DOD(\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_1 (.I0(wready_reg_rep__1[239]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[239]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[239]), .O(wr_buf_in_data[239])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_2 (.I0(wready_reg_rep__1[238]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[238]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[238]), .O(wr_buf_in_data[238])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_3 (.I0(wready_reg_rep__1[237]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[237]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[237]), .O(wr_buf_in_data[237])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_4 (.I0(wready_reg_rep__1[236]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[236]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[236]), .O(wr_buf_in_data[236])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_5 (.I0(wready_reg_rep__1[235]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[235]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[235]), .O(wr_buf_in_data[235])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[39].RAM32M0_i_6 (.I0(wready_reg_rep__1[234]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[234]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[234]), .O(wr_buf_in_data[234])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[3].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[23:22]), .DIB(wr_buf_in_data[21:20]), .DIC(wr_buf_in_data[19:18]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[23:22]), .DOB(wr_buf_out_data_w[21:20]), .DOC(wr_buf_out_data_w[19:18]), .DOD(\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_1 (.I0(wready_reg_rep__1[23]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[23]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[23]), .O(wr_buf_in_data[23])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_2 (.I0(wready_reg_rep__1[22]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[22]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[22]), .O(wr_buf_in_data[22])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_3 (.I0(wready_reg_rep__1[21]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[21]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[21]), .O(wr_buf_in_data[21])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_4 (.I0(wready_reg_rep__1[20]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[20]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[20]), .O(wr_buf_in_data[20])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_5 (.I0(wready_reg_rep__1[19]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[19]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[19]), .O(wr_buf_in_data[19])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[3].RAM32M0_i_6 (.I0(wready_reg_rep__1[18]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[18]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[18]), .O(wr_buf_in_data[18])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[40].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[245:244]), .DIB(wr_buf_in_data[243:242]), .DIC(wr_buf_in_data[241:240]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[245:244]), .DOB(wr_buf_out_data_w[243:242]), .DOC(wr_buf_out_data_w[241:240]), .DOD(\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_1 (.I0(wready_reg_rep__1[245]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[245]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[245]), .O(wr_buf_in_data[245])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_2 (.I0(wready_reg_rep__1[244]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[244]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[244]), .O(wr_buf_in_data[244])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_3 (.I0(wready_reg_rep__1[243]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[243]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[243]), .O(wr_buf_in_data[243])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_4 (.I0(wready_reg_rep__1[242]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[242]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[242]), .O(wr_buf_in_data[242])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_5 (.I0(wready_reg_rep__1[241]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[241]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[241]), .O(wr_buf_in_data[241])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[40].RAM32M0_i_6 (.I0(wready_reg_rep__1[240]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[240]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[240]), .O(wr_buf_in_data[240])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[41].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[251:250]), .DIB(wr_buf_in_data[249:248]), .DIC(wr_buf_in_data[247:246]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[251:250]), .DOB(wr_buf_out_data_w[249:248]), .DOC(wr_buf_out_data_w[247:246]), .DOD(\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_1 (.I0(wready_reg_rep__1[251]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[251]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[251]), .O(wr_buf_in_data[251])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_2 (.I0(wready_reg_rep__1[250]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[250]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[250]), .O(wr_buf_in_data[250])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_3 (.I0(wready_reg_rep__1[249]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[249]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[249]), .O(wr_buf_in_data[249])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_4 (.I0(wready_reg_rep__1[248]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[248]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[248]), .O(wr_buf_in_data[248])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_5 (.I0(wready_reg_rep__1[247]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[247]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[247]), .O(wr_buf_in_data[247])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[41].RAM32M0_i_6 (.I0(wready_reg_rep__1[246]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[246]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[246]), .O(wr_buf_in_data[246])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[42].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[257:256]), .DIB(wr_buf_in_data[255:254]), .DIC(wr_buf_in_data[253:252]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[257:256]), .DOB(wr_buf_out_data_w[255:254]), .DOC(wr_buf_out_data_w[253:252]), .DOD(\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_1 (.I0(D[1]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[1]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[1]), .O(wr_buf_in_data[257])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_2 (.I0(D[0]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[0]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[0]), .O(wr_buf_in_data[256])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_3 (.I0(wready_reg_rep__1[255]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[255]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[255]), .O(wr_buf_in_data[255])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_4 (.I0(wready_reg_rep__1[254]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[254]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[254]), .O(wr_buf_in_data[254])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_5 (.I0(wready_reg_rep__1[253]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[253]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[253]), .O(wr_buf_in_data[253])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[42].RAM32M0_i_6 (.I0(wready_reg_rep__1[252]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[252]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[252]), .O(wr_buf_in_data[252])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[43].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[263:262]), .DIB(wr_buf_in_data[261:260]), .DIC(wr_buf_in_data[259:258]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[263:262]), .DOB(wr_buf_out_data_w[261:260]), .DOC(wr_buf_out_data_w[259:258]), .DOD(\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_1 (.I0(D[7]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[7]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[7]), .O(wr_buf_in_data[263])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_2 (.I0(D[6]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[6]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[6]), .O(wr_buf_in_data[262])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_3 (.I0(D[5]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[5]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[5]), .O(wr_buf_in_data[261])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_4 (.I0(D[4]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[4]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[4]), .O(wr_buf_in_data[260])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_5 (.I0(D[3]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[3]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[3]), .O(wr_buf_in_data[259])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[43].RAM32M0_i_6 (.I0(D[2]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[2]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[2]), .O(wr_buf_in_data[258])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[44].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[269:268]), .DIB(wr_buf_in_data[267:266]), .DIC(wr_buf_in_data[265:264]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[269:268]), .DOB(wr_buf_out_data_w[267:266]), .DOC(wr_buf_out_data_w[265:264]), .DOD(\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_1 (.I0(D[13]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[13]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[13]), .O(wr_buf_in_data[269])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_2 (.I0(D[12]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[12]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[12]), .O(wr_buf_in_data[268])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_3 (.I0(D[11]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[11]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[11]), .O(wr_buf_in_data[267])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_4 (.I0(D[10]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[10]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[10]), .O(wr_buf_in_data[266])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_5 (.I0(D[9]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[9]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[9]), .O(wr_buf_in_data[265])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[44].RAM32M0_i_6 (.I0(D[8]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[8]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[8]), .O(wr_buf_in_data[264])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[45].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[275:274]), .DIB(wr_buf_in_data[273:272]), .DIC(wr_buf_in_data[271:270]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[275:274]), .DOB(wr_buf_out_data_w[273:272]), .DOC(wr_buf_out_data_w[271:270]), .DOD(\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_1 (.I0(D[19]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[19]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[19]), .O(wr_buf_in_data[275])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_2 (.I0(D[18]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[18]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[18]), .O(wr_buf_in_data[274])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_3 (.I0(D[17]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[17]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[17]), .O(wr_buf_in_data[273])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_4 (.I0(D[16]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[16]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[16]), .O(wr_buf_in_data[272])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_5 (.I0(D[15]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[15]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[15]), .O(wr_buf_in_data[271])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[45].RAM32M0_i_6 (.I0(D[14]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[14]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[14]), .O(wr_buf_in_data[270])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[46].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[281:280]), .DIB(wr_buf_in_data[279:278]), .DIC(wr_buf_in_data[277:276]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[281:280]), .DOB(wr_buf_out_data_w[279:278]), .DOC(wr_buf_out_data_w[277:276]), .DOD(\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_1 (.I0(D[25]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[25]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[25]), .O(wr_buf_in_data[281])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_2 (.I0(D[24]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[24]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[24]), .O(wr_buf_in_data[280])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_3 (.I0(D[23]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[23]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[23]), .O(wr_buf_in_data[279])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_4 (.I0(D[22]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[22]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[22]), .O(wr_buf_in_data[278])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_5 (.I0(D[21]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[21]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[21]), .O(wr_buf_in_data[277])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[46].RAM32M0_i_6 (.I0(D[20]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[20]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[20]), .O(wr_buf_in_data[276])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[47].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[287:286]), .DIB(wr_buf_in_data[285:284]), .DIC(wr_buf_in_data[283:282]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[287:286]), .DOB(wr_buf_out_data_w[285:284]), .DOC(wr_buf_out_data_w[283:282]), .DOD(\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_1 (.I0(D[31]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[31]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[31]), .O(wr_buf_in_data[287])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_2 (.I0(D[30]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[30]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[30]), .O(wr_buf_in_data[286])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_3 (.I0(D[29]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[29]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[29]), .O(wr_buf_in_data[285])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_4 (.I0(D[28]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[28]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[28]), .O(wr_buf_in_data[284])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_5 (.I0(D[27]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[27]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[27]), .O(wr_buf_in_data[283])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[47].RAM32M0_i_6 (.I0(D[26]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_mask_reg[26]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_mask_r1[26]), .O(wr_buf_in_data[282])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[4].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[29:28]), .DIB(wr_buf_in_data[27:26]), .DIC(wr_buf_in_data[25:24]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[29:28]), .DOB(wr_buf_out_data_w[27:26]), .DOC(wr_buf_out_data_w[25:24]), .DOD(\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_1 (.I0(wready_reg_rep__1[29]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[29]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[29]), .O(wr_buf_in_data[29])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_2 (.I0(wready_reg_rep__1[28]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[28]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[28]), .O(wr_buf_in_data[28])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_3 (.I0(wready_reg_rep__1[27]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[27]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[27]), .O(wr_buf_in_data[27])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_4 (.I0(wready_reg_rep__1[26]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[26]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[26]), .O(wr_buf_in_data[26])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_5 (.I0(wready_reg_rep__1[25]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[25]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[25]), .O(wr_buf_in_data[25])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[4].RAM32M0_i_6 (.I0(wready_reg_rep__1[24]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[24]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[24]), .O(wr_buf_in_data[24])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[5].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[35:34]), .DIB(wr_buf_in_data[33:32]), .DIC(wr_buf_in_data[31:30]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[35:34]), .DOB(wr_buf_out_data_w[33:32]), .DOC(wr_buf_out_data_w[31:30]), .DOD(\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_1 (.I0(wready_reg_rep__1[35]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[35]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[35]), .O(wr_buf_in_data[35])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_2 (.I0(wready_reg_rep__1[34]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[34]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[34]), .O(wr_buf_in_data[34])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_3 (.I0(wready_reg_rep__1[33]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[33]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[33]), .O(wr_buf_in_data[33])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_4 (.I0(wready_reg_rep__1[32]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[32]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[32]), .O(wr_buf_in_data[32])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_5 (.I0(wready_reg_rep__1[31]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[31]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[31]), .O(wr_buf_in_data[31])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[5].RAM32M0_i_6 (.I0(wready_reg_rep__1[30]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[30]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[30]), .O(wr_buf_in_data[30])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[6].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[41:40]), .DIB(wr_buf_in_data[39:38]), .DIC(wr_buf_in_data[37:36]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[41:40]), .DOB(wr_buf_out_data_w[39:38]), .DOC(wr_buf_out_data_w[37:36]), .DOD(\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_1 (.I0(wready_reg_rep__1[41]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[41]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[41]), .O(wr_buf_in_data[41])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_2 (.I0(wready_reg_rep__1[40]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[40]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[40]), .O(wr_buf_in_data[40])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_3 (.I0(wready_reg_rep__1[39]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[39]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[39]), .O(wr_buf_in_data[39])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_4 (.I0(wready_reg_rep__1[38]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[38]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[38]), .O(wr_buf_in_data[38])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_5 (.I0(wready_reg_rep__1[37]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[37]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[37]), .O(wr_buf_in_data[37])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[6].RAM32M0_i_6 (.I0(wready_reg_rep__1[36]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[36]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[36]), .O(wr_buf_in_data[36])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[7].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[47:46]), .DIB(wr_buf_in_data[45:44]), .DIC(wr_buf_in_data[43:42]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[47:46]), .DOB(wr_buf_out_data_w[45:44]), .DOC(wr_buf_out_data_w[43:42]), .DOD(\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_1 (.I0(wready_reg_rep__1[47]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[47]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[47]), .O(wr_buf_in_data[47])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_2 (.I0(wready_reg_rep__1[46]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[46]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[46]), .O(wr_buf_in_data[46])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_3 (.I0(wready_reg_rep__1[45]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[45]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[45]), .O(wr_buf_in_data[45])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_4 (.I0(wready_reg_rep__1[44]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[44]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[44]), .O(wr_buf_in_data[44])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_5 (.I0(wready_reg_rep__1[43]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[43]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[43]), .O(wr_buf_in_data[43])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[7].RAM32M0_i_6 (.I0(wready_reg_rep__1[42]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[42]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[42]), .O(wr_buf_in_data[42])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[8].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[53:52]), .DIB(wr_buf_in_data[51:50]), .DIC(wr_buf_in_data[49:48]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[53:52]), .DOB(wr_buf_out_data_w[51:50]), .DOC(wr_buf_out_data_w[49:48]), .DOD(\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_1 (.I0(wready_reg_rep__1[53]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[53]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[53]), .O(wr_buf_in_data[53])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_2 (.I0(wready_reg_rep__1[52]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[52]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[52]), .O(wr_buf_in_data[52])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_3 (.I0(wready_reg_rep__1[51]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[51]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[51]), .O(wr_buf_in_data[51])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_4 (.I0(wready_reg_rep__1[50]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[50]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[50]), .O(wr_buf_in_data[50])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_5 (.I0(wready_reg_rep__1[49]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[49]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[49]), .O(wr_buf_in_data[49])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[8].RAM32M0_i_6 (.I0(wready_reg_rep__1[48]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[48]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[48]), .O(wr_buf_in_data[48])); (* BOX_TYPE = "PRIMITIVE" *) RAM32M #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .IS_WCLK_INVERTED(1'b0)) \write_buffer.wr_buffer_ram[9].RAM32M0 (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}), .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}), .DIA(wr_buf_in_data[59:58]), .DIB(wr_buf_in_data[57:56]), .DIC(wr_buf_in_data[55:54]), .DID({1'b0,1'b0}), .DOA(wr_buf_out_data_w[59:58]), .DOB(wr_buf_out_data_w[57:56]), .DOC(wr_buf_out_data_w[55:54]), .DOD(\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]), .WCLK(CLK), .WE(wdf_rdy_ns)); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_1 (.I0(wready_reg_rep__1[59]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[59]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[59]), .O(wr_buf_in_data[59])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_2 (.I0(wready_reg_rep__1[58]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[58]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[58]), .O(wr_buf_in_data[58])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_3 (.I0(wready_reg_rep__1[57]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[57]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[57]), .O(wr_buf_in_data[57])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_4 (.I0(wready_reg_rep__1[56]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[56]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[56]), .O(wr_buf_in_data[56])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_5 (.I0(wready_reg_rep__1[55]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[55]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[55]), .O(wr_buf_in_data[55])); LUT5 #( .INIT(32'hB8FFB800)) \write_buffer.wr_buffer_ram[9].RAM32M0_i_6 (.I0(wready_reg_rep__1[54]), .I1(\mc_app_wdf_mask_reg_reg[0] ), .I2(mc_app_wdf_data_reg[54]), .I3(app_wdf_rdy_r_copy2), .I4(app_wdf_data_r1[54]), .O(wr_buf_in_data[54])); FDRE \write_data_control.wb_wr_data_addr0_r_reg (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr0_ns), .Q(wb_wr_data_addr0_r), .R(1'b0)); FDRE \write_data_control.wb_wr_data_addr_r_reg[1] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[1]), .Q(wb_wr_data_addr_r[1]), .R(1'b0)); FDRE \write_data_control.wb_wr_data_addr_r_reg[2] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[2]), .Q(wb_wr_data_addr_r[2]), .R(1'b0)); FDRE \write_data_control.wb_wr_data_addr_r_reg[3] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[3]), .Q(wb_wr_data_addr_r[3]), .R(1'b0)); FDRE \write_data_control.wb_wr_data_addr_r_reg[4] (.C(CLK), .CE(1'b1), .D(wb_wr_data_addr_w[4]), .Q(wb_wr_data_addr_r[4]), .R(1'b0)); LUT1 #( .INIT(2'h1)) \write_data_control.wr_data_indx_r[0]_i_1 (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]), .O(p_0_in__0__0[0])); LUT2 #( .INIT(4'h6)) \write_data_control.wr_data_indx_r[1]_i_1 (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]), .I1(\write_data_control.wr_data_indx_r_reg__0 [1]), .O(p_0_in__0__0[1])); (* SOFT_HLUTNM = "soft_lutpair1516" *) LUT3 #( .INIT(8'h78)) \write_data_control.wr_data_indx_r[2]_i_1 (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]), .I1(\write_data_control.wr_data_indx_r_reg__0 [1]), .I2(\write_data_control.wr_data_indx_r_reg__0 [2]), .O(p_0_in__0__0[2])); LUT6 #( .INIT(64'hF000FFFF10001000)) \write_data_control.wr_data_indx_r[3]_i_1 (.I0(\occupied_counter.occ_cnt_reg_n_0_[15] ), .I1(p_4_in), .I2(p_0_in__0_0), .I3(\rd_buf_indx.ram_init_done_r_lcl_reg ), .I4(app_wdf_rdy_r_copy1), .I5(p_0_in), .O(wr_data_addr_le)); (* SOFT_HLUTNM = "soft_lutpair1516" *) LUT4 #( .INIT(16'h7F80)) \write_data_control.wr_data_indx_r[3]_i_2 (.I0(\write_data_control.wr_data_indx_r_reg__0 [2]), .I1(\write_data_control.wr_data_indx_r_reg__0 [1]), .I2(\write_data_control.wr_data_indx_r_reg__0 [0]), .I3(\write_data_control.wr_data_indx_r_reg__0 [3]), .O(p_0_in__0__0[3])); FDSE \write_data_control.wr_data_indx_r_reg[0] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[0]), .Q(\write_data_control.wr_data_indx_r_reg__0 [0]), .S(reset_reg)); FDRE \write_data_control.wr_data_indx_r_reg[1] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[1]), .Q(\write_data_control.wr_data_indx_r_reg__0 [1]), .R(reset_reg)); FDRE \write_data_control.wr_data_indx_r_reg[2] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[2]), .Q(\write_data_control.wr_data_indx_r_reg__0 [2]), .R(reset_reg)); FDRE \write_data_control.wr_data_indx_r_reg[3] (.C(CLK), .CE(wr_data_addr_le), .D(p_0_in__0__0[3]), .Q(\write_data_control.wr_data_indx_r_reg__0 [3]), .R(reset_reg)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:09:09 2016 // Host : david-xilinx-vm running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top ddr3_if -prefix // ddr3_if_ ddr3_if_stub.v // Design : ddr3_if // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module ddr3_if(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, init_calib_complete, device_temp, sys_rst) /* synthesis syn_black_box black_box_pad_pin="ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */; inout [31:0]ddr3_dq; inout [3:0]ddr3_dqs_n; inout [3:0]ddr3_dqs_p; output [14:0]ddr3_addr; output [2:0]ddr3_ba; output ddr3_ras_n; output ddr3_cas_n; output ddr3_we_n; output ddr3_reset_n; output [0:0]ddr3_ck_p; output [0:0]ddr3_ck_n; output [0:0]ddr3_cke; output [0:0]ddr3_cs_n; output [3:0]ddr3_dm; output [0:0]ddr3_odt; input sys_clk_i; output ui_clk; output ui_clk_sync_rst; output mmcm_locked; input aresetn; input app_sr_req; input app_ref_req; input app_zq_req; output app_sr_active; output app_ref_ack; output app_zq_ack; input [0:0]s_axi_awid; input [29:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input s_axi_awvalid; output s_axi_awready; input [255:0]s_axi_wdata; input [31:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; input s_axi_bready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input [0:0]s_axi_arid; input [29:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input s_axi_arvalid; output s_axi_arready; input s_axi_rready; output [0:0]s_axi_rid; output [255:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; output init_calib_complete; output [11:0]device_temp; input sys_rst; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/mig_a.prj ================================================ ddr3_if 1 1 OFF 1024 ON Enabled xc7k325t-ffg900/-2 4.0 No Buffer Use System Clock ACTIVE LOW FALSE 0 OFF 0 DDR3_SDRAM/Components/MT41J256m16XX-107 1112 2.0V 4:1 199.84 0 899 1.000 1 1 1 1 32 1 1 Disabled Normal 4 FALSE 15 10 3 1.5V ROW_BANK_COLUMN 8 - Fixed Sequential 13 Normal No Slow Exit Enable RZQ/7 Disable Enable RZQ/6 0 Disabled Enabled Output Buffer Enabled Full Array 9 Enabled Normal Dynamic ODT off AXI RD_PRI_REG_STARVE_LIMIT 30 256 1 0 ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.v ================================================ // file: dvi_pll.v // // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //---------------------------------------------------------------------------- // User entered comments //---------------------------------------------------------------------------- // None // //---------------------------------------------------------------------------- // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // pixel_clock___148.000______0.000______50.0______111.449____139.507 // dvi_bit_clock___740.000______0.000______50.0_______87.091____139.507 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) //---------------------------------------------------------------------------- // __primary_____________200____________0.010 `timescale 1ps/1ps (* CORE_GENERATION_INFO = "dvi_pll,clk_wiz_v5_3_2_0,{component_name=dvi_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) module dvi_pll ( // Clock out ports output pixel_clock, output dvi_bit_clock, // Clock in ports input sysclk ); dvi_pll_clk_wiz inst ( // Clock out ports .pixel_clock(pixel_clock), .dvi_bit_clock(dvi_bit_clock), // Clock in ports .sysclk(sysclk) ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci ================================================ xilinx.com xci unknown 1.0 dvi_pll MMCM cddcdone cddcreq 0000 0080 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 100.0 1145 0000 148.000 1041 0000 740.000 BUFG 50.0 false 148.000 0.000 50.000 148 0.000 1 1041 00c0 100.000 BUFG 50.0 false 740.000 0.000 50.000 740 0.000 1 1 1041 00c0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 1041 00c0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 1041 00c0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 1041 00c0 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO clk_in_sel pixel_clock dvi_bit_clock clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0083 1 0.2 1.48 1.48 1.48 1.48 1.48 dout drdy dwe 0 0 0 0 0 0 0 0 FDBK_AUTO 0800 1890 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_____________200____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 00fa 7c01 7fe9 false false false false false false false false OPTIMIZED 37.000 0.000 FALSE 5.0 10.0 10.000 0.500 0.000 FALSE 2 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE ZHOLD 5 None 0.010 0.010 FALSE 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) pixel_clock___148.000______0.000______50.0______111.449____139.507 dvi_bit_clock___740.000______0.000______50.0_______87.091____139.507 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 0 0 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down FFFF 1 sysclk PLL AUTO 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 dvi_pll MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 50.0 0.010 100.0 0.010 BUFG 111.449 false 139.507 50.000 148 0.000 1 true BUFG 87.091 false 139.507 50.000 740 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel pixel_clock false dvi_bit_clock false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto dvi_pll daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 37 0.000 false 5.0 10.0 10 0.500 0.000 false 2 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 5 None 0.010 0.010 false 2 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 sysclk PLL mmcm_adv 200 0.010 10.000 Global_buffer psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false false false false false true false false false false false kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 2 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xdc ================================================ # file: dvi_pll.xdc # # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and # international copyright and other intellectual property # laws. # # DISCLAIMER # This disclaimer is not a license and does not grant any # rights to the materials distributed herewith. Except as # otherwise provided in a valid license issued to you by # Xilinx, and to the maximum extent permitted by applicable # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and # (2) Xilinx shall not be liable (whether in contract or tort, # including negligence, or under any other theory of # liability) for any loss or damage of any kind or nature # related to, arising under or in connection with these # materials, including for any direct, or any indirect, # special, incidental, or consequential loss or damage # (including loss of data, profits, goodwill, or any type of # loss or damage suffered as a result of any action brought # by a third party) even if such damage or loss was # reasonably foreseeable or Xilinx had been advised of the # possibility of the same. # # CRITICAL APPLICATIONS # Xilinx products are not designed or intended to be fail- # safe, or for use in any application requiring fail-safe # performance, such as life-support or safety devices or # systems, Class III medical devices, nuclear facilities, # applications related to the deployment of airbags, or any # other applications that could lead to death, personal # injury, or severe property or environmental damage # (individually and collectively, "Critical # Applications"). Customer assumes the sole risk and # liability of any use of Xilinx products in Critical # Applications, subject only to applicable laws and # regulations governing limitations on product liability. # # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS # PART OF THIS FILE AT ALL TIMES. # # Input clock periods. These duplicate the values entered for the # input clocks. You can use these to time your system. If required # commented constraints can be used in the top level xdc #---------------------------------------------------------------- #create_clock -period 5.0 [get_ports sysclk] #set_input_jitter [get_clocks -of_objects [get_ports sysclk]] 0.05 set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_board.xdc ================================================ #--------------------Physical Constraints----------------- ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_clk_wiz.v ================================================ // file: dvi_pll.v // // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //---------------------------------------------------------------------------- // User entered comments //---------------------------------------------------------------------------- // None // //---------------------------------------------------------------------------- // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // pixel_clock___148.000______0.000______50.0______111.449____139.507 // dvi_bit_clock___740.000______0.000______50.0_______87.091____139.507 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) //---------------------------------------------------------------------------- // __primary_____________200____________0.010 `timescale 1ps/1ps module dvi_pll_clk_wiz (// Clock in ports // Clock out ports output pixel_clock, output dvi_bit_clock, input sysclk ); // Input buffering //------------------------------------ wire sysclk_dvi_pll; wire clk_in2_dvi_pll; BUFG clkin1_bufg (.O (sysclk_dvi_pll), .I (sysclk)); // Clocking PRIMITIVE //------------------------------------ // Instantiation of the MMCM PRIMITIVE // * Unused inputs are tied off // * Unused outputs are labeled unused wire pixel_clock_dvi_pll; wire dvi_bit_clock_dvi_pll; wire clk_out3_dvi_pll; wire clk_out4_dvi_pll; wire clk_out5_dvi_pll; wire clk_out6_dvi_pll; wire clk_out7_dvi_pll; wire [15:0] do_unused; wire drdy_unused; wire psdone_unused; wire locked_int; wire clkfbout_dvi_pll; wire clkfbout_buf_dvi_pll; wire clkfboutb_unused; wire clkout2_unused; wire clkout3_unused; wire clkout4_unused; wire clkout5_unused; wire clkout6_unused; wire clkfbstopped_unused; wire clkinstopped_unused; PLLE2_ADV #(.BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("ZHOLD"), .DIVCLK_DIVIDE (5), .CLKFBOUT_MULT (37), .CLKFBOUT_PHASE (0.000), .CLKOUT0_DIVIDE (10), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT1_DIVIDE (2), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKIN1_PERIOD (5.0)) plle2_adv_inst // Output clocks ( .CLKFBOUT (clkfbout_dvi_pll), .CLKOUT0 (pixel_clock_dvi_pll), .CLKOUT1 (dvi_bit_clock_dvi_pll), .CLKOUT2 (clkout2_unused), .CLKOUT3 (clkout3_unused), .CLKOUT4 (clkout4_unused), .CLKOUT5 (clkout5_unused), // Input clock control .CLKFBIN (clkfbout_buf_dvi_pll), .CLKIN1 (sysclk_dvi_pll), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (do_unused), .DRDY (drdy_unused), .DWE (1'b0), // Other control and status signals .LOCKED (locked_int), .PWRDWN (1'b0), .RST (1'b0)); // Clock Monitor clock assigning //-------------------------------------- // Output buffering //----------------------------------- BUFG clkf_buf (.O (clkfbout_buf_dvi_pll), .I (clkfbout_dvi_pll)); BUFG clkout1_buf (.O (pixel_clock), .I (pixel_clock_dvi_pll)); BUFG clkout2_buf (.O (dvi_bit_clock), .I (dvi_bit_clock_dvi_pll)); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_ooc.xdc ================================================ # file: dvi_pll_ooc.xdc # # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and # international copyright and other intellectual property # laws. # # DISCLAIMER # This disclaimer is not a license and does not grant any # rights to the materials distributed herewith. Except as # otherwise provided in a valid license issued to you by # Xilinx, and to the maximum extent permitted by applicable # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and # (2) Xilinx shall not be liable (whether in contract or tort, # including negligence, or under any other theory of # liability) for any loss or damage of any kind or nature # related to, arising under or in connection with these # materials, including for any direct, or any indirect, # special, incidental, or consequential loss or damage # (including loss of data, profits, goodwill, or any type of # loss or damage suffered as a result of any action brought # by a third party) even if such damage or loss was # reasonably foreseeable or Xilinx had been advised of the # possibility of the same. # # CRITICAL APPLICATIONS # Xilinx products are not designed or intended to be fail- # safe, or for use in any application requiring fail-safe # performance, such as life-support or safety devices or # systems, Class III medical devices, nuclear facilities, # applications related to the deployment of airbags, or any # other applications that could lead to death, personal # injury, or severe property or environmental damage # (individually and collectively, "Critical # Applications"). Customer assumes the sole risk and # liability of any use of Xilinx products in Critical # Applications, subject only to applicable laws and # regulations governing limitations on product liability. # # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS # PART OF THIS FILE AT ALL TIMES. # ################# #DEFAULT CLOCK CONSTRAINTS ############################################################ # Clock Period Constraints # ############################################################ create_clock -period 5.0 [get_ports sysclk] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 17:05:27 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim // /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v // Design : dvi_pll // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module dvi_pll (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire dvi_bit_clock; wire pixel_clock; wire sysclk; dvi_pll_dvi_pll_clk_wiz inst (.dvi_bit_clock(dvi_bit_clock), .pixel_clock(pixel_clock), .sysclk(sysclk)); endmodule (* ORIG_REF_NAME = "dvi_pll_clk_wiz" *) module dvi_pll_dvi_pll_clk_wiz (pixel_clock, dvi_bit_clock, sysclk); output pixel_clock; output dvi_bit_clock; input sysclk; wire clkfbout_buf_dvi_pll; wire clkfbout_dvi_pll; wire dvi_bit_clock; wire dvi_bit_clock_dvi_pll; wire pixel_clock; wire pixel_clock_dvi_pll; wire sysclk; wire sysclk_dvi_pll; wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED; wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_dvi_pll), .O(clkfbout_buf_dvi_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkin1_bufg (.I(sysclk), .O(sysclk_dvi_pll)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout1_buf (.I(pixel_clock_dvi_pll), .O(pixel_clock)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout2_buf (.I(dvi_bit_clock_dvi_pll), .O(dvi_bit_clock)); (* BOX_TYPE = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(37), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(10), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(2), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(5), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_adv_inst (.CLKFBIN(clkfbout_buf_dvi_pll), .CLKFBOUT(clkfbout_dvi_pll), .CLKIN1(sysclk_dvi_pll), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(pixel_clock_dvi_pll), .CLKOUT1(dvi_bit_clock_dvi_pll), .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED), .PWRDWN(1'b0), .RST(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 17:05:27 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v // Design : dvi_pll // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module dvi_pll(pixel_clock, dvi_bit_clock, sysclk) /* synthesis syn_black_box black_box_pad_pin="pixel_clock,dvi_bit_clock,sysclk" */; output pixel_clock; output dvi_bit_clock; input sysclk; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd ================================================ [File too large to display: 14.2 MB] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci ================================================ xilinx.com xci unknown 1.0 input_line_buffer 4096 12 10 1 4 0 1 9 0 1 7 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 36.714252 mW kintex7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 input_line_buffer.mem no_coe_file_loaded 0 0 1 0 1 4096 1024 64 256 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 4096 1024 NO_CHANGE WRITE_FIRST 64 256 kintex7 4 Memory_Slave AXI4_Full false Minimum_Area false 9 NONE no_coe_file_loaded ALL input_line_buffer false false false false false false false false false Use_ENA_Pin Always_Enabled Single_Bit_Error_Injection false Native false no_mem_loaded Simple_Dual_Port_RAM NO_CHANGE WRITE_FIRST 0 0 BRAM 0 100 100 50 100 100 0 8kx2 false false 64 256 false false false false 0 false false CE CE SYNC false false false false false false false 4096 64 256 No_ECC false false false Stand_Alone kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 4 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_ooc.xdc ================================================ ################################################################################ # # (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and # international copyright and other intellectual property # laws. # # DISCLAIMER # This disclaimer is not a license and does not grant any # rights to the materials distributed herewith. Except as # otherwise provided in a valid license issued to you by # Xilinx, and to the maximum extent permitted by applicable # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and # (2) Xilinx shall not be liable (whether in contract or tort, # including negligence, or under any other theory of # liability) for any loss or damage of any kind or nature # related to, arising under or in connection with these # materials, including for any direct, or any indirect, # special, incidental, or consequential loss or damage # (including loss of data, profits, goodwill, or any type of # loss or damage suffered as a result of any action brought # by a third party) even if such damage or loss was # reasonably foreseeable or Xilinx had been advised of the # possibility of the same. # # CRITICAL APPLICATIONS # Xilinx products are not designed or intended to be fail- # safe, or for use in any application requiring fail-safe # performance, such as life-support or safety devices or # systems, Class III medical devices, nuclear facilities, # applications related to the deployment of airbags, or any # other applications that could lead to death, personal # injury, or severe property or environmental damage # (individually and collectively, "Critical # Applications"). Customer assumes the sole risk and # liability of any use of Xilinx products in Critical # Applications, subject only to applicable laws and # regulations governing limitations on product liability. # # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS # PART OF THIS FILE AT ALL TIMES. # ################################################################################ # Core Period Constraint. This constraint can be modified, and is # valid as long as it is met after place and route. create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ] set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ] create_clock -name "TS_CLKB" -period 20.0 [ get_ports clkb ] set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ] ################################################################################ ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:41:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v // Design : input_line_buffer // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "input_line_buffer,blk_mem_gen_v8_3_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) (* NotValidForBitStream *) module input_line_buffer (clka, ena, wea, addra, dina, clkb, addrb, doutb); (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [63:0]dina; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [9:0]addrb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [255:0]doutb; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_rsta_busy_UNCONNECTED; wire NLW_U0_rstb_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_dbiterr_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_sbiterr_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire [63:0]NLW_U0_douta_UNCONNECTED; wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED; wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; wire [255:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; (* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 36.714252 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "input_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "4096" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "64" *) (* C_READ_WIDTH_B = "256" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "4096" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "64" *) (* C_WRITE_WIDTH_B = "256" *) (* C_XDEVICEFAMILY = "kintex7" *) (* downgradeipidentifiedwarnings = "yes" *) input_line_buffer_blk_mem_gen_v8_3_4 U0 (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .deepsleep(1'b0), .dina(dina), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(NLW_U0_douta_UNCONNECTED[63:0]), .doutb(doutb), .eccpipece(1'b0), .ena(ena), .enb(1'b0), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]), .regcea(1'b0), .regceb(1'b0), .rsta(1'b0), .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), .rstb(1'b0), .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), .s_aclk(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), .s_axi_injectdbiterr(1'b0), .s_axi_injectsbiterr(1'b0), .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[255:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb(1'b0), .s_axi_wvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .shutdown(1'b0), .sleep(1'b0), .wea(wea), .web(1'b0)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module input_line_buffer_blk_mem_gen_generic_cstr (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [255:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [63:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_width \ramloop[0].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[3:0]), .doutb({doutb[195:192],doutb[131:128],doutb[67:64],doutb[3:0]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[12:4]), .doutb({doutb[204:196],doutb[140:132],doutb[76:68],doutb[12:4]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[21:13]), .doutb({doutb[213:205],doutb[149:141],doutb[85:77],doutb[21:13]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[30:22]), .doutb({doutb[222:214],doutb[158:150],doutb[94:86],doutb[30:22]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[39:31]), .doutb({doutb[231:223],doutb[167:159],doutb[103:95],doutb[39:31]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[48:40]), .doutb({doutb[240:232],doutb[176:168],doutb[112:104],doutb[48:40]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[57:49]), .doutb({doutb[249:241],doutb[185:177],doutb[121:113],doutb[57:49]}), .ena(ena), .wea(wea)); input_line_buffer_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina[63:58]), .doutb({doutb[255:250],doutb[191:186],doutb[127:122],doutb[63:58]}), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [15:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [3:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [3:0]dina; wire [15:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module input_line_buffer_blk_mem_gen_prim_width__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [23:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [5:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [5:0]dina; wire [23:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [15:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [3:0]dina; input [0:0]wea; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 ; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [3:0]dina; wire [15:0]doutb; wire ena; wire [0:0]wea; wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(18), .READ_WIDTH_B(18), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(4), .WRITE_WIDTH_B(4)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (.ADDRARDADDR({addra,1'b0,1'b0}), .ADDRBWRADDR({addrb,1'b0,1'b0,1'b0,1'b0}), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), .DOBDO(doutb), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 }), .ENARDEN(ena), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [35:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [8:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [8:0]dina; wire [35:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module input_line_buffer_blk_mem_gen_prim_wrapper__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [23:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [5:0]dina; input [0:0]wea; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [5:0]dina; wire [23:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ,doutb[23:18],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ,doutb[17:12],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,doutb[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb[5:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module input_line_buffer_blk_mem_gen_top (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [255:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [63:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_generic_cstr \valid.cstr (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 36.714252 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "input_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "4096" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "64" *) (* C_READ_WIDTH_B = "256" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "4096" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "64" *) (* C_WRITE_WIDTH_B = "256" *) (* C_XDEVICEFAMILY = "kintex7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *) (* downgradeipidentifiedwarnings = "yes" *) module input_line_buffer_blk_mem_gen_v8_3_4 (clka, rsta, ena, regcea, wea, addra, dina, douta, clkb, rstb, enb, regceb, web, addrb, dinb, doutb, injectsbiterr, injectdbiterr, eccpipece, sbiterr, dbiterr, rdaddrecc, sleep, deepsleep, shutdown, rsta_busy, rstb_busy, s_aclk, s_aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, s_axi_injectsbiterr, s_axi_injectdbiterr, s_axi_sbiterr, s_axi_dbiterr, s_axi_rdaddrecc); input clka; input rsta; input ena; input regcea; input [0:0]wea; input [11:0]addra; input [63:0]dina; output [63:0]douta; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [9:0]addrb; input [255:0]dinb; output [255:0]doutb; input injectsbiterr; input injectdbiterr; input eccpipece; output sbiterr; output dbiterr; output [9:0]rdaddrecc; input sleep; input deepsleep; input shutdown; output rsta_busy; output rstb_busy; input s_aclk; input s_aresetn; input [3:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input s_axi_awvalid; output s_axi_awready; input [63:0]s_axi_wdata; input [0:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; output [3:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input s_axi_bready; input [3:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input s_axi_arvalid; output s_axi_arready; output [3:0]s_axi_rid; output [255:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; input s_axi_rready; input s_axi_injectsbiterr; input s_axi_injectdbiterr; output s_axi_sbiterr; output s_axi_dbiterr; output [9:0]s_axi_rdaddrecc; wire \ ; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; assign dbiterr = \ ; assign douta[63] = \ ; assign douta[62] = \ ; assign douta[61] = \ ; assign douta[60] = \ ; assign douta[59] = \ ; assign douta[58] = \ ; assign douta[57] = \ ; assign douta[56] = \ ; assign douta[55] = \ ; assign douta[54] = \ ; assign douta[53] = \ ; assign douta[52] = \ ; assign douta[51] = \ ; assign douta[50] = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign rdaddrecc[9] = \ ; assign rdaddrecc[8] = \ ; assign rdaddrecc[7] = \ ; assign rdaddrecc[6] = \ ; assign rdaddrecc[5] = \ ; assign rdaddrecc[4] = \ ; assign rdaddrecc[3] = \ ; assign rdaddrecc[2] = \ ; assign rdaddrecc[1] = \ ; assign rdaddrecc[0] = \ ; assign rsta_busy = \ ; assign rstb_busy = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[3] = \ ; assign s_axi_bid[2] = \ ; assign s_axi_bid[1] = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_dbiterr = \ ; assign s_axi_rdaddrecc[9] = \ ; assign s_axi_rdaddrecc[8] = \ ; assign s_axi_rdaddrecc[7] = \ ; assign s_axi_rdaddrecc[6] = \ ; assign s_axi_rdaddrecc[5] = \ ; assign s_axi_rdaddrecc[4] = \ ; assign s_axi_rdaddrecc[3] = \ ; assign s_axi_rdaddrecc[2] = \ ; assign s_axi_rdaddrecc[1] = \ ; assign s_axi_rdaddrecc[0] = \ ; assign s_axi_rdata[255] = \ ; assign s_axi_rdata[254] = \ ; assign s_axi_rdata[253] = \ ; assign s_axi_rdata[252] = \ ; assign s_axi_rdata[251] = \ ; assign s_axi_rdata[250] = \ ; assign s_axi_rdata[249] = \ ; assign s_axi_rdata[248] = \ ; assign s_axi_rdata[247] = \ ; assign s_axi_rdata[246] = \ ; assign s_axi_rdata[245] = \ ; assign s_axi_rdata[244] = \ ; assign s_axi_rdata[243] = \ ; assign s_axi_rdata[242] = \ ; assign s_axi_rdata[241] = \ ; assign s_axi_rdata[240] = \ ; assign s_axi_rdata[239] = \ ; assign s_axi_rdata[238] = \ ; assign s_axi_rdata[237] = \ ; assign s_axi_rdata[236] = \ ; assign s_axi_rdata[235] = \ ; assign s_axi_rdata[234] = \ ; assign s_axi_rdata[233] = \ ; assign s_axi_rdata[232] = \ ; assign s_axi_rdata[231] = \ ; assign s_axi_rdata[230] = \ ; assign s_axi_rdata[229] = \ ; assign s_axi_rdata[228] = \ ; assign s_axi_rdata[227] = \ ; assign s_axi_rdata[226] = \ ; assign s_axi_rdata[225] = \ ; assign s_axi_rdata[224] = \ ; assign s_axi_rdata[223] = \ ; assign s_axi_rdata[222] = \ ; assign s_axi_rdata[221] = \ ; assign s_axi_rdata[220] = \ ; assign s_axi_rdata[219] = \ ; assign s_axi_rdata[218] = \ ; assign s_axi_rdata[217] = \ ; assign s_axi_rdata[216] = \ ; assign s_axi_rdata[215] = \ ; assign s_axi_rdata[214] = \ ; assign s_axi_rdata[213] = \ ; assign s_axi_rdata[212] = \ ; assign s_axi_rdata[211] = \ ; assign s_axi_rdata[210] = \ ; assign s_axi_rdata[209] = \ ; assign s_axi_rdata[208] = \ ; assign s_axi_rdata[207] = \ ; assign s_axi_rdata[206] = \ ; assign s_axi_rdata[205] = \ ; assign s_axi_rdata[204] = \ ; assign s_axi_rdata[203] = \ ; assign s_axi_rdata[202] = \ ; assign s_axi_rdata[201] = \ ; assign s_axi_rdata[200] = \ ; assign s_axi_rdata[199] = \ ; assign s_axi_rdata[198] = \ ; assign s_axi_rdata[197] = \ ; assign s_axi_rdata[196] = \ ; assign s_axi_rdata[195] = \ ; assign s_axi_rdata[194] = \ ; assign s_axi_rdata[193] = \ ; assign s_axi_rdata[192] = \ ; assign s_axi_rdata[191] = \ ; assign s_axi_rdata[190] = \ ; assign s_axi_rdata[189] = \ ; assign s_axi_rdata[188] = \ ; assign s_axi_rdata[187] = \ ; assign s_axi_rdata[186] = \ ; assign s_axi_rdata[185] = \ ; assign s_axi_rdata[184] = \ ; assign s_axi_rdata[183] = \ ; assign s_axi_rdata[182] = \ ; assign s_axi_rdata[181] = \ ; assign s_axi_rdata[180] = \ ; assign s_axi_rdata[179] = \ ; assign s_axi_rdata[178] = \ ; assign s_axi_rdata[177] = \ ; assign s_axi_rdata[176] = \ ; assign s_axi_rdata[175] = \ ; assign s_axi_rdata[174] = \ ; assign s_axi_rdata[173] = \ ; assign s_axi_rdata[172] = \ ; assign s_axi_rdata[171] = \ ; assign s_axi_rdata[170] = \ ; assign s_axi_rdata[169] = \ ; assign s_axi_rdata[168] = \ ; assign s_axi_rdata[167] = \ ; assign s_axi_rdata[166] = \ ; assign s_axi_rdata[165] = \ ; assign s_axi_rdata[164] = \ ; assign s_axi_rdata[163] = \ ; assign s_axi_rdata[162] = \ ; assign s_axi_rdata[161] = \ ; assign s_axi_rdata[160] = \ ; assign s_axi_rdata[159] = \ ; assign s_axi_rdata[158] = \ ; assign s_axi_rdata[157] = \ ; assign s_axi_rdata[156] = \ ; assign s_axi_rdata[155] = \ ; assign s_axi_rdata[154] = \ ; assign s_axi_rdata[153] = \ ; assign s_axi_rdata[152] = \ ; assign s_axi_rdata[151] = \ ; assign s_axi_rdata[150] = \ ; assign s_axi_rdata[149] = \ ; assign s_axi_rdata[148] = \ ; assign s_axi_rdata[147] = \ ; assign s_axi_rdata[146] = \ ; assign s_axi_rdata[145] = \ ; assign s_axi_rdata[144] = \ ; assign s_axi_rdata[143] = \ ; assign s_axi_rdata[142] = \ ; assign s_axi_rdata[141] = \ ; assign s_axi_rdata[140] = \ ; assign s_axi_rdata[139] = \ ; assign s_axi_rdata[138] = \ ; assign s_axi_rdata[137] = \ ; assign s_axi_rdata[136] = \ ; assign s_axi_rdata[135] = \ ; assign s_axi_rdata[134] = \ ; assign s_axi_rdata[133] = \ ; assign s_axi_rdata[132] = \ ; assign s_axi_rdata[131] = \ ; assign s_axi_rdata[130] = \ ; assign s_axi_rdata[129] = \ ; assign s_axi_rdata[128] = \ ; assign s_axi_rdata[127] = \ ; assign s_axi_rdata[126] = \ ; assign s_axi_rdata[125] = \ ; assign s_axi_rdata[124] = \ ; assign s_axi_rdata[123] = \ ; assign s_axi_rdata[122] = \ ; assign s_axi_rdata[121] = \ ; assign s_axi_rdata[120] = \ ; assign s_axi_rdata[119] = \ ; assign s_axi_rdata[118] = \ ; assign s_axi_rdata[117] = \ ; assign s_axi_rdata[116] = \ ; assign s_axi_rdata[115] = \ ; assign s_axi_rdata[114] = \ ; assign s_axi_rdata[113] = \ ; assign s_axi_rdata[112] = \ ; assign s_axi_rdata[111] = \ ; assign s_axi_rdata[110] = \ ; assign s_axi_rdata[109] = \ ; assign s_axi_rdata[108] = \ ; assign s_axi_rdata[107] = \ ; assign s_axi_rdata[106] = \ ; assign s_axi_rdata[105] = \ ; assign s_axi_rdata[104] = \ ; assign s_axi_rdata[103] = \ ; assign s_axi_rdata[102] = \ ; assign s_axi_rdata[101] = \ ; assign s_axi_rdata[100] = \ ; assign s_axi_rdata[99] = \ ; assign s_axi_rdata[98] = \ ; assign s_axi_rdata[97] = \ ; assign s_axi_rdata[96] = \ ; assign s_axi_rdata[95] = \ ; assign s_axi_rdata[94] = \ ; assign s_axi_rdata[93] = \ ; assign s_axi_rdata[92] = \ ; assign s_axi_rdata[91] = \ ; assign s_axi_rdata[90] = \ ; assign s_axi_rdata[89] = \ ; assign s_axi_rdata[88] = \ ; assign s_axi_rdata[87] = \ ; assign s_axi_rdata[86] = \ ; assign s_axi_rdata[85] = \ ; assign s_axi_rdata[84] = \ ; assign s_axi_rdata[83] = \ ; assign s_axi_rdata[82] = \ ; assign s_axi_rdata[81] = \ ; assign s_axi_rdata[80] = \ ; assign s_axi_rdata[79] = \ ; assign s_axi_rdata[78] = \ ; assign s_axi_rdata[77] = \ ; assign s_axi_rdata[76] = \ ; assign s_axi_rdata[75] = \ ; assign s_axi_rdata[74] = \ ; assign s_axi_rdata[73] = \ ; assign s_axi_rdata[72] = \ ; assign s_axi_rdata[71] = \ ; assign s_axi_rdata[70] = \ ; assign s_axi_rdata[69] = \ ; assign s_axi_rdata[68] = \ ; assign s_axi_rdata[67] = \ ; assign s_axi_rdata[66] = \ ; assign s_axi_rdata[65] = \ ; assign s_axi_rdata[64] = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[3] = \ ; assign s_axi_rid[2] = \ ; assign s_axi_rid[1] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_sbiterr = \ ; assign s_axi_wready = \ ; assign sbiterr = \ ; GND GND (.G(\ )); input_line_buffer_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *) module input_line_buffer_blk_mem_gen_v8_3_4_synth (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [255:0]doutb; input clka; input clkb; input ena; input [11:0]addra; input [9:0]addrb; input [63:0]dina; input [0:0]wea; wire [11:0]addra; wire [9:0]addrb; wire clka; wire clkb; wire [63:0]dina; wire [255:0]doutb; wire ena; wire [0:0]wea; input_line_buffer_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:41:00 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v // Design : input_line_buffer // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) module input_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb) /* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[63:0],clkb,addrb[9:0],doutb[255:0]" */; input clka; input ena; input [0:0]wea; input [11:0]addra; input [63:0]dina; input clkb; input [9:0]addrb; output [255:0]doutb; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/misc/blk_mem_gen_v8_3.vhd ================================================ library ieee; use ieee.std_logic_1164.all; entity blk_mem_gen_v8_3_4 is generic ( C_FAMILY : string := "virtex7"; C_XDEVICEFAMILY : string := "virtex7"; C_ELABORATION_DIR : string := ""; C_INTERFACE_TYPE : integer := 0; C_AXI_TYPE : integer := 1; C_AXI_SLAVE_TYPE : integer := 0; C_USE_BRAM_BLOCK : integer := 0; C_ENABLE_32BIT_ADDRESS : integer := 0; C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7"; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; C_MEM_TYPE : integer := 2; C_BYTE_SIZE : integer := 9; C_ALGORITHM : integer := 0; C_PRIM_TYPE : integer := 3; C_LOAD_INIT_FILE : integer := 0; C_INIT_FILE_NAME : string := "no_coe_file_loaded"; C_INIT_FILE : string := "no_mem_file_loaded"; C_USE_DEFAULT_DATA : integer := 0; C_DEFAULT_DATA : string := "0"; C_HAS_RSTA : integer := 0; C_RST_PRIORITY_A : string := "ce"; C_RSTRAM_A : integer := 0; C_INITA_VAL : string := "0"; C_HAS_ENA : integer := 1; C_HAS_REGCEA : integer := 0; C_USE_BYTE_WEA : integer := 0; C_WEA_WIDTH : integer := 1; C_WRITE_MODE_A : string := "WRITE_FIRST"; C_WRITE_WIDTH_A : integer := 9; C_READ_WIDTH_A : integer := 9; C_WRITE_DEPTH_A : integer := 2048; C_READ_DEPTH_A : integer := 2048; C_ADDRA_WIDTH : integer := 11; C_HAS_RSTB : integer := 0; C_RST_PRIORITY_B : string := "ce"; C_RSTRAM_B : integer := 0; C_INITB_VAL : string := "0"; C_HAS_ENB : integer := 1; C_HAS_REGCEB : integer := 0; C_USE_BYTE_WEB : integer := 0; C_WEB_WIDTH : integer := 1; C_WRITE_MODE_B : string := "WRITE_FIRST"; C_WRITE_WIDTH_B : integer := 9; C_READ_WIDTH_B : integer := 9; C_WRITE_DEPTH_B : integer := 2048; C_READ_DEPTH_B : integer := 2048; C_ADDRB_WIDTH : integer := 11; C_HAS_MEM_OUTPUT_REGS_A : integer := 0; C_HAS_MEM_OUTPUT_REGS_B : integer := 0; C_HAS_MUX_OUTPUT_REGS_A : integer := 0; C_HAS_MUX_OUTPUT_REGS_B : integer := 0; C_MUX_PIPELINE_STAGES : integer := 0; C_HAS_SOFTECC_INPUT_REGS_A : integer := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0; C_USE_SOFTECC : integer := 0; C_USE_ECC : integer := 0; C_EN_ECC_PIPE : integer := 0; C_HAS_INJECTERR : integer := 0; C_SIM_COLLISION_CHECK : string := "none"; C_COMMON_CLK : integer := 0; C_DISABLE_WARN_BHV_COLL : integer := 0; C_EN_SLEEP_PIN : integer := 0; C_USE_URAM : integer := 0; C_EN_RDADDRA_CHG : integer := 0; C_EN_RDADDRB_CHG : integer := 0; C_EN_DEEPSLEEP_PIN : integer := 0; C_EN_SHUTDOWN_PIN : integer := 0; C_EN_SAFETY_CKT : integer := 0; C_DISABLE_WARN_BHV_RANGE : integer := 0; C_COUNT_36K_BRAM : string := ""; C_COUNT_18K_BRAM : string := ""; C_EST_POWER_SUMMARY : string := "" ); port ( clka : in std_logic := '0'; rsta : in std_logic := '0'; ena : in std_logic := '0'; regcea : in std_logic := '0'; wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0'); addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0'); dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0'); douta : out std_logic_vector(c_read_width_a - 1 downto 0); clkb : in std_logic := '0'; rstb : in std_logic := '0'; enb : in std_logic := '0'; regceb : in std_logic := '0'; web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0'); addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0'); dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0'); doutb : out std_logic_vector(c_read_width_b - 1 downto 0); injectsbiterr : in std_logic := '0'; injectdbiterr : in std_logic := '0'; eccpipece : in std_logic := '0'; sbiterr : out std_logic; dbiterr : out std_logic; rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0); sleep : in std_logic := '0'; deepsleep : in std_logic := '0'; shutdown : in std_logic := '0'; rsta_busy : out std_logic; rstb_busy : out std_logic; s_aclk : in std_logic := '0'; s_aresetn : in std_logic := '0'; s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0'); s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0'); s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0'); s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0'); s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0'); s_axi_awvalid : in std_logic := '0'; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0'); s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0'); s_axi_wlast : in std_logic := '0'; s_axi_wvalid : in std_logic := '0'; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic := '0'; s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0'); s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0'); s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0'); s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0'); s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0'); s_axi_arvalid : in std_logic := '0'; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0); s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0); s_axi_rresp : out std_logic_vector(2 - 1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic := '0'; s_axi_injectsbiterr : in std_logic := '0'; s_axi_injectdbiterr : in std_logic := '0'; s_axi_sbiterr : out std_logic; s_axi_dbiterr : out std_logic; s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0) ); end entity blk_mem_gen_v8_3_4; architecture xilinx of blk_mem_gen_v8_3_4 is begin end architecture xilinx; ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/sim/input_line_buffer.v ================================================ // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 // IP Revision: 4 `timescale 1ns/1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module input_line_buffer ( clka, ena, wea, addra, dina, clkb, addrb, doutb ); (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input wire clka; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input wire ena; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input wire [0 : 0] wea; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input wire [11 : 0] addra; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input wire [63 : 0] dina; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input wire clkb; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input wire [9 : 0] addrb; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output wire [255 : 0] doutb; blk_mem_gen_v8_3_4 #( .C_FAMILY("kintex7"), .C_XDEVICEFAMILY("kintex7"), .C_ELABORATION_DIR("./"), .C_INTERFACE_TYPE(0), .C_AXI_TYPE(1), .C_AXI_SLAVE_TYPE(0), .C_USE_BRAM_BLOCK(0), .C_ENABLE_32BIT_ADDRESS(0), .C_CTRL_ECC_ALGO("NONE"), .C_HAS_AXI_ID(0), .C_AXI_ID_WIDTH(4), .C_MEM_TYPE(1), .C_BYTE_SIZE(9), .C_ALGORITHM(1), .C_PRIM_TYPE(1), .C_LOAD_INIT_FILE(0), .C_INIT_FILE_NAME("no_coe_file_loaded"), .C_INIT_FILE("input_line_buffer.mem"), .C_USE_DEFAULT_DATA(0), .C_DEFAULT_DATA("0"), .C_HAS_RSTA(0), .C_RST_PRIORITY_A("CE"), .C_RSTRAM_A(0), .C_INITA_VAL("0"), .C_HAS_ENA(1), .C_HAS_REGCEA(0), .C_USE_BYTE_WEA(0), .C_WEA_WIDTH(1), .C_WRITE_MODE_A("NO_CHANGE"), .C_WRITE_WIDTH_A(64), .C_READ_WIDTH_A(64), .C_WRITE_DEPTH_A(4096), .C_READ_DEPTH_A(4096), .C_ADDRA_WIDTH(12), .C_HAS_RSTB(0), .C_RST_PRIORITY_B("CE"), .C_RSTRAM_B(0), .C_INITB_VAL("0"), .C_HAS_ENB(0), .C_HAS_REGCEB(0), .C_USE_BYTE_WEB(0), .C_WEB_WIDTH(1), .C_WRITE_MODE_B("WRITE_FIRST"), .C_WRITE_WIDTH_B(256), .C_READ_WIDTH_B(256), .C_WRITE_DEPTH_B(1024), .C_READ_DEPTH_B(1024), .C_ADDRB_WIDTH(10), .C_HAS_MEM_OUTPUT_REGS_A(0), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_MUX_PIPELINE_STAGES(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_USE_SOFTECC(0), .C_USE_ECC(0), .C_EN_ECC_PIPE(0), .C_HAS_INJECTERR(0), .C_SIM_COLLISION_CHECK("ALL"), .C_COMMON_CLK(0), .C_DISABLE_WARN_BHV_COLL(0), .C_EN_SLEEP_PIN(0), .C_USE_URAM(0), .C_EN_RDADDRA_CHG(0), .C_EN_RDADDRB_CHG(0), .C_EN_DEEPSLEEP_PIN(0), .C_EN_SHUTDOWN_PIN(0), .C_EN_SAFETY_CKT(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_COUNT_36K_BRAM("7"), .C_COUNT_18K_BRAM("1"), .C_EST_POWER_SUMMARY("Estimated Power for IP : 36.714252 mW") ) inst ( .clka(clka), .rsta(1'D0), .ena(ena), .regcea(1'D0), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clkb), .rstb(1'D0), .enb(1'D0), .regceb(1'D0), .web(1'B0), .addrb(addrb), .dinb(256'B0), .doutb(doutb), .injectsbiterr(1'D0), .injectdbiterr(1'D0), .eccpipece(1'D0), .sbiterr(), .dbiterr(), .rdaddrecc(), .sleep(1'D0), .deepsleep(1'D0), .shutdown(1'D0), .rsta_busy(), .rstb_busy(), .s_aclk(1'H0), .s_aresetn(1'D0), .s_axi_awid(4'B0), .s_axi_awaddr(32'B0), .s_axi_awlen(8'B0), .s_axi_awsize(3'B0), .s_axi_awburst(2'B0), .s_axi_awvalid(1'D0), .s_axi_awready(), .s_axi_wdata(64'B0), .s_axi_wstrb(1'B0), .s_axi_wlast(1'D0), .s_axi_wvalid(1'D0), .s_axi_wready(), .s_axi_bid(), .s_axi_bresp(), .s_axi_bvalid(), .s_axi_bready(1'D0), .s_axi_arid(4'B0), .s_axi_araddr(32'B0), .s_axi_arlen(8'B0), .s_axi_arsize(3'B0), .s_axi_arburst(2'B0), .s_axi_arvalid(1'D0), .s_axi_arready(), .s_axi_rid(), .s_axi_rdata(), .s_axi_rresp(), .s_axi_rlast(), .s_axi_rvalid(), .s_axi_rready(1'D0), .s_axi_injectsbiterr(1'D0), .s_axi_injectdbiterr(1'D0), .s_axi_sbiterr(), .s_axi_dbiterr(), .s_axi_rdaddrecc() ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/simulation/blk_mem_gen_v8_3.v ================================================ /****************************************************************************** -- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ***************************************************************************** * * Filename: blk_mem_gen_v8_3_4.v * * Description: * This file is the Verilog behvarial model for the * Block Memory Generator Core. * ***************************************************************************** * Author: Xilinx * * History: Jan 11, 2006 Initial revision * Jun 11, 2007 Added independent register stages for * Port A and Port B (IP1_Jm/v2.5) * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) * Mar 13, 2008 Behavioral model optimizations * April 07, 2009 : Added support for Spartan-6 and Virtex-6 * features, including the following: * (i) error injection, detection and/or correction * (ii) reset priority * (iii) special reset behavior * *****************************************************************************/ `timescale 1ps/1ps module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5); parameter INIT = 64'h0000000000000000; input I0, I1, I2, I3, I4, I5; output O; reg O; reg tmp; always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; if ( tmp == 0 || tmp == 1) O = INIT[{I5, I4, I3, I2, I1, I0}]; end endmodule module beh_vlog_muxf7_v8_3 (O, I0, I1, S); output O; reg O; input I0, I1, S; always @(I0 or I1 or S) if (S) O = I1; else O = I0; endmodule module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q<= 1'b0; else Q<= #FLOP_DELAY D; endmodule module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, D, PRE; reg Q; initial Q= 1'b0; always @(posedge C ) if (PRE) Q <= 1'b1; else Q <= #FLOP_DELAY D; endmodule module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CE, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q <= 1'b0; else if (CE) Q <= #FLOP_DELAY D; endmodule module write_netlist_v8_3 #( parameter C_AXI_TYPE = 0 ) ( S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c ); input S_ACLK; input S_ARESETN; input S_AXI_AWVALID; input S_AXI_WVALID; input S_AXI_BREADY; input w_last_c; input bready_timeout_c; output aw_ready_r; output S_AXI_WREADY; output S_AXI_BVALID; output S_AXI_WR_EN; output addr_en_c; output incr_addr_c; output bvalid_c; //------------------------------------------------------------------------- //AXI LITE //------------------------------------------------------------------------- generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm wire w_ready_r_7; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSignal_bvalid_c; wire NlwRenamedSignal_incr_addr_c; wire present_state_FSM_FFd3_13; wire present_state_FSM_FFd2_14; wire present_state_FSM_FFd1_15; wire present_state_FSM_FFd4_16; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd4_In1_21; wire [0:0] Mmux_aw_ready_c ; begin assign S_AXI_WREADY = w_ready_r_7, S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, incr_addr_c = NlwRenamedSignal_incr_addr_c, bvalid_c = NlwRenamedSignal_bvalid_c; assign NlwRenamedSignal_incr_addr_c = 1'b0; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_7) ); beh_vlog_ff_pre_v8_3 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_16) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_13) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_15) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000055554440)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000088880800)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( S_AXI_WVALID), .I2 ( bready_timeout_c), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000AAAA2000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_WVALID), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( addr_en_c) ); STATE_LOGIC_v8_3 #( .INIT (64'hF5F07570F5F05500)) Mmux_w_ready_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( w_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd3_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd1_15), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_14), .I2 ( present_state_FSM_FFd3_13), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSignal_bvalid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h2F0F27072F0F2200)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( present_state_FSM_FFd4_In1_21) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_In1_21), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h7535753575305500)) Mmux_aw_ready_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_WVALID), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 ( present_state_FSM_FFd2_14), .O ( Mmux_aw_ready_c[0]) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000F8)) Mmux_aw_ready_c_0_2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( Mmux_aw_ready_c[0]), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( aw_ready_c) ); end end endgenerate //--------------------------------------------------------------------- // AXI FULL //--------------------------------------------------------------------- generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm wire w_ready_r_8; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSig_OI_bvalid_c; wire present_state_FSM_FFd1_16; wire present_state_FSM_FFd4_17; wire present_state_FSM_FFd3_18; wire present_state_FSM_FFd2_19; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd2_In1_24; wire present_state_FSM_FFd4_In1_25; wire N2; wire N4; begin assign S_AXI_WREADY = w_ready_r_8, bvalid_c = NlwRenamedSig_OI_bvalid_c, S_AXI_BVALID = 1'b0; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_8) ); beh_vlog_ff_pre_v8_3 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_17) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_18) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_19) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_16) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000005540)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd4_17), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_3 #( .INIT (64'hBF3FBB33AF0FAA00)) Mmux_aw_ready_c_0_2 ( .I0 ( S_AXI_BREADY), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd1_16), .I4 ( present_state_FSM_FFd4_17), .I5 ( NlwRenamedSig_OI_bvalid_c), .O ( aw_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'hAAAAAAAA20000000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( S_AXI_WVALID), .I4 ( w_last_c), .I5 ( present_state_FSM_FFd4_17), .O ( addr_en_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_19), .I2 ( present_state_FSM_FFd3_18), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( S_AXI_WR_EN) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000002220)) Mmux_incr_addr_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( incr_addr_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000008880)) Mmux_aw_ready_c_0_11 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSig_OI_bvalid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000000000D5C0)) present_state_FSM_FFd2_In1 ( .I0 ( w_last_c), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd4_17), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd2_In1_24) ); STATE_LOGIC_v8_3 #( .INIT (64'hFFFFAAAA08AAAAAA)) present_state_FSM_FFd2_In2 ( .I0 ( present_state_FSM_FFd2_19), .I1 ( S_AXI_AWVALID), .I2 ( bready_timeout_c), .I3 ( w_last_c), .I4 ( S_AXI_WVALID), .I5 ( present_state_FSM_FFd2_In1_24), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00C0004000C00000)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( w_last_c), .I2 ( S_AXI_WVALID), .I3 ( bready_timeout_c), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( present_state_FSM_FFd4_In1_25) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000FFFF88F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_16), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_17), .I3 ( S_AXI_AWVALID), .I4 ( present_state_FSM_FFd4_In1_25), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000007)) Mmux_w_ready_c_0_SW0 ( .I0 ( w_last_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N2) ); STATE_LOGIC_v8_3 #( .INIT (64'hFABAFABAFAAAF000)) Mmux_w_ready_c_0_Q ( .I0 ( N2), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd4_17), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( w_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000008)) Mmux_aw_ready_c_0_11_SW0 ( .I0 ( bready_timeout_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N4) ); STATE_LOGIC_v8_3 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( w_last_c), .I1 ( N4), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 ( present_state_FSM_FFd1_16), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); end end endgenerate endmodule module read_netlist_v8_3 #( parameter C_AXI_TYPE = 1, parameter C_ADDRB_WIDTH = 12 ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); input S_AXI_R_LAST_INT; input S_ACLK; input S_ARESETN; input S_AXI_ARVALID; input S_AXI_RREADY; output S_AXI_INCR_ADDR; output S_AXI_ADDR_EN; output S_AXI_SINGLE_TRANS; output S_AXI_MUX_SEL; output S_AXI_R_LAST; output S_AXI_ARREADY; output S_AXI_RLAST; output S_AXI_RVALID; output S_AXI_RD_EN; input [7:0] S_AXI_ARLEN; wire present_state_FSM_FFd1_13 ; wire present_state_FSM_FFd2_14 ; wire gaxi_full_sm_outstanding_read_r_15 ; wire gaxi_full_sm_ar_ready_r_16 ; wire gaxi_full_sm_r_last_r_17 ; wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; wire gaxi_full_sm_r_valid_c ; wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; wire gaxi_full_sm_ar_ready_c ; wire gaxi_full_sm_outstanding_read_c ; wire NlwRenamedSig_OI_S_AXI_R_LAST ; wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; wire present_state_FSM_FFd2_In ; wire present_state_FSM_FFd1_In ; wire Mmux_S_AXI_R_LAST13 ; wire N01 ; wire N2 ; wire Mmux_gaxi_full_sm_ar_ready_c11 ; wire N4 ; wire N8 ; wire N9 ; wire N10 ; wire N11 ; wire N12 ; wire N13 ; assign S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, S_AXI_RLAST = gaxi_full_sm_r_last_r_17, S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_outstanding_read_r ( .C (S_ACLK), .CLR(S_ARESETN), .D(gaxi_full_sm_outstanding_read_c), .Q(gaxi_full_sm_outstanding_read_r_15) ); beh_vlog_ff_ce_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_r_valid_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (gaxi_full_sm_r_valid_c), .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_ar_ready_r ( .C (S_ACLK), .CLR (S_ARESETN), .D (gaxi_full_sm_ar_ready_c), .Q (gaxi_full_sm_ar_ready_r_16) ); beh_vlog_ff_ce_clr_v8_3 #( .INIT(1'b0)) gaxi_full_sm_r_last_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (NlwRenamedSig_OI_S_AXI_R_LAST), .Q (gaxi_full_sm_r_last_r_17) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C (S_ACLK), .CLR (S_ARESETN), .D (present_state_FSM_FFd1_In), .Q (present_state_FSM_FFd1_13) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000000000000B)) S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( .I0 ( S_AXI_RREADY), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000008)) Mmux_S_AXI_SINGLE_TRANS11 ( .I0 (S_AXI_ARVALID), .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_SINGLE_TRANS) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000004)) Mmux_S_AXI_ADDR_EN11 ( .I0 (present_state_FSM_FFd1_13), .I1 (S_AXI_ARVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_ADDR_EN) ); STATE_LOGIC_v8_3 #( .INIT (64'hECEE2022EEEE2022)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_ARVALID), .I1 ( present_state_FSM_FFd1_13), .I2 ( S_AXI_RREADY), .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I4 ( present_state_FSM_FFd2_14), .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000044440444)) Mmux_S_AXI_R_LAST131 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_RREADY), .I5 (1'b0), .O ( Mmux_S_AXI_R_LAST13) ); STATE_LOGIC_v8_3 #( .INIT (64'h4000FFFF40004000)) Mmux_S_AXI_INCR_ADDR11 ( .I0 ( S_AXI_R_LAST_INT), .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( Mmux_S_AXI_R_LAST13), .O ( S_AXI_INCR_ADDR) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000FE)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( .I0 ( S_AXI_ARLEN[2]), .I1 ( S_AXI_ARLEN[1]), .I2 ( S_AXI_ARLEN[0]), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N01) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000001)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( .I0 ( S_AXI_ARLEN[7]), .I1 ( S_AXI_ARLEN[6]), .I2 ( S_AXI_ARLEN[5]), .I3 ( S_AXI_ARLEN[4]), .I4 ( S_AXI_ARLEN[3]), .I5 ( N01), .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000007)) Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 ( 1'b0), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N2) ); STATE_LOGIC_v8_3 #( .INIT (64'h0020000002200200)) Mmux_gaxi_full_sm_outstanding_read_c1 ( .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd1_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( gaxi_full_sm_outstanding_read_r_15), .I5 ( N2), .O ( gaxi_full_sm_outstanding_read_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000004555)) Mmux_gaxi_full_sm_ar_ready_c12 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( 1'b0), .I5 ( 1'b0), .O ( Mmux_gaxi_full_sm_ar_ready_c11) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000EF)) Mmux_S_AXI_R_LAST11_SW0 ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N4) ); STATE_LOGIC_v8_3 #( .INIT (64'hFCAAFC0A00AA000A)) Mmux_S_AXI_R_LAST11 ( .I0 ( S_AXI_ARVALID), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( N4), .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .O ( gaxi_full_sm_r_valid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000AAAAAA08)) S_AXI_MUX_SEL1 ( .I0 (present_state_FSM_FFd1_13), .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (S_AXI_RREADY), .I3 (present_state_FSM_FFd2_14), .I4 (gaxi_full_sm_outstanding_read_r_15), .I5 (1'b0), .O (S_AXI_MUX_SEL) ); STATE_LOGIC_v8_3 #( .INIT (64'hF3F3F755A2A2A200)) Mmux_S_AXI_RD_EN11 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 ( S_AXI_RREADY), .I3 ( gaxi_full_sm_outstanding_read_r_15), .I4 ( present_state_FSM_FFd2_14), .I5 ( S_AXI_ARVALID), .O ( S_AXI_RD_EN) ); beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 ( .I0 ( N8), .I1 ( N9), .S ( present_state_FSM_FFd1_13), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000005410F4F0)) present_state_FSM_FFd1_In3_F ( .I0 ( S_AXI_RREADY), .I1 ( present_state_FSM_FFd2_14), .I2 ( S_AXI_ARVALID), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( 1'b0), .O ( N8) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000072FF7272)) present_state_FSM_FFd1_In3_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N9) ); beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 ( .I0 ( N10), .I1 ( N11), .S ( present_state_FSM_FFd1_13), .O ( gaxi_full_sm_ar_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000FFFF88A8)) Mmux_gaxi_full_sm_ar_ready_c14_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), .I5 ( 1'b0), .O ( N10) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000008D008D8D)) Mmux_gaxi_full_sm_ar_ready_c14_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N11) ); beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 ( .I0 ( N12), .I1 ( N13), .S ( present_state_FSM_FFd1_13), .O ( NlwRenamedSig_OI_S_AXI_R_LAST) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000088088888)) Mmux_S_AXI_R_LAST1_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N12) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000E400E4E4)) Mmux_S_AXI_R_LAST1_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( S_AXI_R_LAST_INT), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N13) ); endmodule module blk_mem_axi_write_wrapper_beh_v8_3 # ( // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; parameter C_WRITE_DEPTH_A = 0, parameter C_AXI_AWADDR_WIDTH = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_WDATA_WIDTH = 32, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, // AXI OUTSTANDING WRITES parameter C_AXI_OS_WR = 2 ) ( // AXI Global Signals input S_ACLK, input S_ARESETN, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, input [8-1:0] S_AXI_AWLEN, input [2:0] S_AXI_AWSIZE, input [1:0] S_AXI_AWBURST, input S_AXI_AWVALID, output S_AXI_AWREADY, input S_AXI_WVALID, output S_AXI_WREADY, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, output S_AXI_BVALID, input S_AXI_BREADY, // Signals for BMG interface output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, output S_AXI_WR_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: ((C_AXI_WDATA_WIDTH==16)?1: ((C_AXI_WDATA_WIDTH==32)?2: ((C_AXI_WDATA_WIDTH==64)?3: ((C_AXI_WDATA_WIDTH==128)?4: ((C_AXI_WDATA_WIDTH==256)?5:0)))))); wire bvalid_c ; reg bready_timeout_c = 0; wire [1:0] bvalid_rd_cnt_c; reg bvalid_r = 0; reg [2:0] bvalid_count_r = 0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; reg [1:0] bvalid_wr_cnt_r = 0; reg [1:0] bvalid_rd_cnt_r = 0; wire w_last_c ; wire addr_en_c ; wire incr_addr_c ; wire aw_ready_r ; wire dec_alen_c ; reg bvalid_d1_c = 0; reg [7:0] awlen_cntr_r = 0; reg [7:0] awlen_int = 0; reg [1:0] awburst_int = 0; integer total_bytes = 0; integer wrap_boundary = 0; integer wrap_base_addr = 0; integer num_of_bytes_c = 0; integer num_of_bytes_r = 0; // Array to store BIDs reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; wire S_AXI_BVALID_axi_wr_fsm; //------------------------------------- //AXI WRITE FSM COMPONENT INSTANTIATION //------------------------------------- write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm ( .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), .S_AXI_AWVALID(S_AXI_AWVALID), .aw_ready_r(aw_ready_r), .S_AXI_WVALID(S_AXI_WVALID), .S_AXI_WREADY(S_AXI_WREADY), .S_AXI_BREADY(S_AXI_BREADY), .S_AXI_WR_EN(S_AXI_WR_EN), .w_last_c(w_last_c), .bready_timeout_c(bready_timeout_c), .addr_en_c(addr_en_c), .incr_addr_c(incr_addr_c), .bvalid_c(bvalid_c), .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) ); //Wrap Address boundary calculation always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); total_bytes = (num_of_bytes_r)*(awlen_int+1); wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); wrap_boundary = wrap_base_addr+total_bytes; end //------------------------------------------------------------------------- // BMG address generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awaddr_reg <= 0; num_of_bytes_r <= 0; awburst_int <= 0; end else begin if (addr_en_c == 1'b1) begin awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; num_of_bytes_r <= num_of_bytes_c; awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); end else if (incr_addr_c == 1'b1) begin if (awburst_int == 2'b10) begin if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin awaddr_reg <= wrap_base_addr; end else begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end end end assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); //------------------------------------------------------------------------- // AXI wlast generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awlen_cntr_r <= 0; awlen_int <= 0; end else begin if (addr_en_c == 1'b1) begin awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; end else if (dec_alen_c == 1'b1) begin awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; end end end assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; assign dec_alen_c = (incr_addr_c | w_last_c); //------------------------------------------------------------------------- // Generation of bvalid counter for outstanding transactions //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_count_r <= 0; end else begin // bvalid_count_r generation if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; end else if (bvalid_c == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; end end end //------------------------------------------------------------------------- // Generation of bvalid when BID is used //------------------------------------------------------------------------- generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; bvalid_d1_c <= 0; end else begin // Delay the generation o bvalid_r for generation for BID bvalid_d1_c <= bvalid_c; //external bvalid signal generation if (bvalid_d1_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of bvalid when BID is not used //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; end else begin //external bvalid signal generation if (bvalid_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of Bready timeout //------------------------------------------------------------------------- always @(bvalid_count_r) begin // bready_timeout_c generation if(bvalid_count_r == C_AXI_OS_WR-1) begin bready_timeout_c <= 1'b1; end else begin bready_timeout_c <= 1'b0; end end //------------------------------------------------------------------------- // Generation of BID //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_wr_cnt_r <= 0; bvalid_rd_cnt_r <= 0; end else begin // STORE AWID IN AN ARRAY if(bvalid_c == 1'b1) begin bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; end // generate BID FROM AWID ARRAY bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; end end assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; //------------------------------------------------------------------------- // Storing AWID for generation of BID //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if(S_ARESETN == 1'b1) begin axi_bid_array[0] = 0; axi_bid_array[1] = 0; axi_bid_array[2] = 0; axi_bid_array[3] = 0; end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; end end end endgenerate assign S_AXI_BVALID = bvalid_r; assign S_AXI_AWREADY = aw_ready_r; endmodule module blk_mem_axi_read_wrapper_beh_v8_3 # ( //// AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_MEMORY_TYPE = 0, parameter C_WRITE_WIDTH_A = 4, parameter C_WRITE_DEPTH_A = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_PIPELINE_STAGES = 0, parameter C_AXI_ARADDR_WIDTH = 12, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_ADDRB_WIDTH = 12 ) ( //// AXI Global Signals input S_ACLK, input S_ARESETN, //// AXI Full/Lite Slave Read (Read side) input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, input [7:0] S_AXI_ARLEN, input [2:0] S_AXI_ARSIZE, input [1:0] S_AXI_ARBURST, input S_AXI_ARVALID, output S_AXI_ARREADY, output S_AXI_RLAST, output S_AXI_RVALID, input S_AXI_RREADY, input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, //// AXI Full/Lite Read Address Signals to BRAM output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, output S_AXI_RD_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: ((C_WRITE_WIDTH_A==16)?1: ((C_WRITE_WIDTH_A==32)?2: ((C_WRITE_WIDTH_A==64)?3: ((C_WRITE_WIDTH_A==128)?4: ((C_WRITE_WIDTH_A==256)?5:0)))))); reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; wire addr_en_c; wire rd_en_c; wire incr_addr_c; wire single_trans_c; wire dec_alen_c; wire mux_sel_c; wire r_last_c; wire r_last_int_c; wire [C_ADDRB_WIDTH-1 : 0] araddr_out; reg [7:0] arlen_int_r=0; reg [7:0] arlen_cntr=8'h01; reg [1:0] arburst_int_c=0; reg [1:0] arburst_int_r=0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; integer num_of_bytes_c = 0; integer total_bytes = 0; integer num_of_bytes_r = 0; integer wrap_base_addr_r = 0; integer wrap_boundary_r = 0; reg [7:0] arlen_int_c=0; integer total_bytes_c = 0; integer wrap_base_addr_c = 0; integer wrap_boundary_c = 0; assign dec_alen_c = incr_addr_c | r_last_int_c; read_netlist_v8_3 #(.C_AXI_TYPE (1), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_read_fsm ( .S_AXI_INCR_ADDR(incr_addr_c), .S_AXI_ADDR_EN(addr_en_c), .S_AXI_SINGLE_TRANS(single_trans_c), .S_AXI_MUX_SEL(mux_sel_c), .S_AXI_R_LAST(r_last_c), .S_AXI_R_LAST_INT(r_last_int_c), //// AXI Global Signals .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), //// AXI Full/Lite Slave Read (Read side) .S_AXI_ARLEN(S_AXI_ARLEN), .S_AXI_ARVALID(S_AXI_ARVALID), .S_AXI_ARREADY(S_AXI_ARREADY), .S_AXI_RLAST(S_AXI_RLAST), .S_AXI_RVALID(S_AXI_RVALID), .S_AXI_RREADY(S_AXI_RREADY), //// AXI Full/Lite Read Address Signals to BRAM .S_AXI_RD_EN(rd_en_c) ); always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); total_bytes = (num_of_bytes_r)*(arlen_int_r+1); wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); wrap_boundary_r = wrap_base_addr_r+total_bytes; //////// combinatorial from interface arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); wrap_boundary_c = wrap_base_addr_c+total_bytes_c; arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); end ////------------------------------------------------------------------------- //// BMG address generation ////------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin araddr_reg <= 0; arburst_int_r <= 0; num_of_bytes_r <= 0; end else begin if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin arburst_int_r <= arburst_int_c; num_of_bytes_r <= num_of_bytes_c; if (arburst_int_c == 2'b10) begin if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin araddr_reg <= wrap_base_addr_c; end else begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (addr_en_c == 1'b1) begin araddr_reg <= S_AXI_ARADDR; num_of_bytes_r <= num_of_bytes_c; arburst_int_r <= arburst_int_c; end else if (incr_addr_c == 1'b1) begin if (arburst_int_r == 2'b10) begin if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin araddr_reg <= wrap_base_addr_r; end else begin araddr_reg <= araddr_reg + num_of_bytes_r; end end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin araddr_reg <= araddr_reg + num_of_bytes_r; end end end end assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); ////----------------------------------------------------------------------- //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM ////----------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin arlen_cntr <= 8'h01; arlen_int_r <= 0; end else begin if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= S_AXI_ARLEN - 1'b1; end else if (addr_en_c == 1'b1) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; end else if (dec_alen_c == 1'b1) begin arlen_cntr <= arlen_cntr - 1'b1 ; end else begin arlen_cntr <= arlen_cntr; end end end assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; ////------------------------------------------------------------------------ //// AXI FULL FSM //// Mux Selection of ARADDR //// ARADDR is driven out from the read fsm based on the mux_sel_c //// Based on mux_sel either ARADDR is given out or the latched ARADDR is //// given out to BRAM ////------------------------------------------------------------------------ assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; ////------------------------------------------------------------------------ //// Assign output signals - AXI FULL FSM ////------------------------------------------------------------------------ assign S_AXI_RD_EN = rd_en_c; generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin S_AXI_RID <= 0; ar_id_r <= 0; end else begin if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin S_AXI_RID <= S_AXI_ARID; ar_id_r <= S_AXI_ARID; end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin ar_id_r <= S_AXI_ARID; end else if (rd_en_c == 1'b1) begin S_AXI_RID <= ar_id_r; end end end end endgenerate endmodule module blk_mem_axi_regs_fwd_v8_3 #(parameter C_DATA_WIDTH = 8 )( input ACLK, input ARESET, input S_VALID, output S_READY, input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, output M_VALID, input M_READY, output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA ); reg [C_DATA_WIDTH-1:0] STORAGE_DATA; wire S_READY_I; reg M_VALID_I; reg [1:0] ARESET_D; //assign local signal to its output signal assign S_READY = S_READY_I; assign M_VALID = M_VALID_I; always @(posedge ACLK) begin ARESET_D <= {ARESET_D[0], ARESET}; end //Save payload data whenever we have a transaction on the slave side always @(posedge ACLK or ARESET) begin if (ARESET == 1'b1) begin STORAGE_DATA <= 0; end else begin if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin STORAGE_DATA <= S_PAYLOAD_DATA; end end end always @(posedge ACLK) begin M_PAYLOAD_DATA = STORAGE_DATA; end //M_Valid set to high when we have a completed transfer on slave side //Is removed on a M_READY except if we have a new transfer on the slave side always @(posedge ACLK or ARESET_D) begin if (ARESET_D != 2'b00) begin M_VALID_I <= 1'b0; end else begin if (S_VALID == 1'b1) begin //Always set M_VALID_I when slave side is valid M_VALID_I <= 1'b1; end else if (M_READY == 1'b1 ) begin //Clear (or keep) when no slave side is valid but master side is ready M_VALID_I <= 1'b0; end end end //Slave Ready is either when Master side drives M_READY or we have space in our storage data assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); endmodule //***************************************************************************** // Output Register Stage module // // This module builds the output register stages of the memory. This module is // instantiated in the main memory module (blk_mem_gen_v8_3_4) which is // declared/implemented further down in this file. //***************************************************************************** module blk_mem_gen_v8_3_4_output_stage #(parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RST = 0, parameter C_RSTRAM = 0, parameter C_RST_PRIORITY = "CE", parameter C_INIT_VAL = "0", parameter C_HAS_EN = 0, parameter C_HAS_REGCE = 0, parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_MEM_OUTPUT_REGS = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter NUM_STAGES = 1, parameter C_EN_ECC_PIPE = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input RST, input EN, input REGCE, input [C_DATA_WIDTH-1:0] DIN_I, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN_I, input DBITERR_IN_I, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, input ECCPIPECE, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RST : Determines the presence of the RST port // C_RSTRAM : Determines if special reset behavior is used // C_RST_PRIORITY : Determines the priority between CE and SR // C_INIT_VAL : Initialization value // C_HAS_EN : Determines the presence of the EN port // C_HAS_REGCE : Determines the presence of the REGCE port // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // NUM_STAGES : Determines the number of output stages // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // RST : Reset input to reset memory outputs to a user-defined // reset state // EN : Enable all read and write operations // REGCE : Register Clock Enable to control each pipeline output // register stages // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// // Fix for CR-509792 localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; // Declare the pipeline registers // (includes mem output reg, mux pipeline stages, and mux output reg) reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; reg [REG_STAGES-1:0] sbiterr_regs; reg [REG_STAGES-1:0] dbiterr_regs; reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; reg [C_DATA_WIDTH-1:0] init_val ; //********************************************* // Wire off optional inputs based on parameters //********************************************* wire en_i; wire regce_i; wire rst_i; // Internal signals reg [C_DATA_WIDTH-1:0] DIN; reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; reg SBITERR_IN; reg DBITERR_IN; // Internal enable for output registers is tied to user EN or '1' depending // on parameters assign en_i = (C_HAS_EN==0 || EN); // Internal register enable for output registers is tied to user REGCE, EN or // '1' depending on parameters // For V4 ECC, REGCE is always 1 // Virtex-4 ECC Not Yet Supported assign regce_i = ((C_HAS_REGCE==1) && REGCE) || ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); //Internal SRR is tied to user RST or '0' depending on parameters assign rst_i = (C_HAS_RST==1) && RST; //**************************************************** // Power on: load up the output registers and latches //**************************************************** initial begin if (!($sscanf(init_str, "%h", init_val))) begin init_val = 0; end DOUT = init_val; RDADDRECC = 0; SBITERR = 1'b0; DBITERR = 1'b0; DIN = {(C_DATA_WIDTH){1'b0}}; RDADDRECC_IN = 0; SBITERR_IN = 0; DBITERR_IN = 0; // This will be one wider than need, but 0 is an error out_regs = {(REG_STAGES+1){init_val}}; rdaddrecc_regs = 0; sbiterr_regs = {(REG_STAGES+1){1'b0}}; dbiterr_regs = {(REG_STAGES+1){1'b0}}; end //*********************************************** // NUM_STAGES = 0 (No output registers. RAM only) //*********************************************** generate if (NUM_STAGES == 0) begin : zero_stages always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg always @* begin DIN = DIN_I; SBITERR_IN = SBITERR_IN_I; DBITERR_IN = DBITERR_IN_I; RDADDRECC_IN = RDADDRECC_IN_I; end end endgenerate generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg always @(posedge CLK) begin if(ECCPIPECE == 1) begin DIN <= #FLOP_DELAY DIN_I; SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; end end end endgenerate //*********************************************** // NUM_STAGES = 1 // (Mem Output Reg only or Mux Output Reg only) //*********************************************** // Possible valid combinations: // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) // +-----------------------------------------+ // | C_RSTRAM_* | Reset Behavior | // +----------------+------------------------+ // | 0 | Normal Behavior | // +----------------+------------------------+ // | 1 | Special Behavior | // +----------------+------------------------+ // // Normal = REGCE gates reset, as in the case of all families except S3ADSP. // Special = EN gates reset, as in the case of S3ADSP. generate if (NUM_STAGES == 1 && (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) begin : one_stages_norm always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end //end Priority conditions end //end RST Type conditions end //end one_stages_norm generate statement endgenerate // Special Reset Behavior for S3ADSP generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) begin : one_stage_splbhv always @(posedge CLK) begin if (en_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; end else if (regce_i && !rst_i) begin DOUT <= #FLOP_DELAY DIN; end //Output signal assignments end //end CLK end //end one_stage_splbhv generate statement endgenerate //************************************************************ // NUM_STAGES > 1 // Mem Output Reg + Mux Output Reg // or // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg // or // Mux Pipeline Stages (>0) + Mux Output Reg //************************************************************* generate if (NUM_STAGES > 1) begin : multi_stage //Asynchronous Reset always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end //end Priority conditions // Shift the data through the output stages if (en_i) begin out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; end end //end CLK end //end multi_stage generate statement endgenerate endmodule module blk_mem_gen_v8_3_4_softecc_output_reg_stage #(parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_USE_SOFTECC = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input [C_DATA_WIDTH-1:0] DIN, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN, input DBITERR_IN, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// reg [C_DATA_WIDTH-1:0] dout_i = 0; reg sbiterr_i = 0; reg dbiterr_i = 0; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; //*********************************************** // NO OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate //*********************************************** // WITH OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage always @(posedge CLK) begin dout_i <= #FLOP_DELAY DIN; rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; sbiterr_i <= #FLOP_DELAY SBITERR_IN; dbiterr_i <= #FLOP_DELAY DBITERR_IN; end always @* begin DOUT = dout_i; RDADDRECC = rdaddrecc_i; SBITERR = sbiterr_i; DBITERR = dbiterr_i; end //end always end //end in_or_out_stage generate statement endgenerate endmodule //***************************************************************************** // Main Memory module // // This module is the top-level behavioral model and this implements the RAM //***************************************************************************** module blk_mem_gen_v8_3_4_mem_module #(parameter C_CORENAME = "blk_mem_gen_v8_3_4", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_USE_BRAM_BLOCK = 0, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter FLOP_DELAY = 100, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_ECC_PIPE = 0, parameter C_DISABLE_WARN_BHV_RANGE = 0 ) (input CLKA, input RSTA, input ENA, input REGCEA, input [C_WEA_WIDTH-1:0] WEA, input [C_ADDRA_WIDTH-1:0] ADDRA, input [C_WRITE_WIDTH_A-1:0] DINA, output [C_READ_WIDTH_A-1:0] DOUTA, input CLKB, input RSTB, input ENB, input REGCEB, input [C_WEB_WIDTH-1:0] WEB, input [C_ADDRB_WIDTH-1:0] ADDRB, input [C_WRITE_WIDTH_B-1:0] DINB, output [C_READ_WIDTH_B-1:0] DOUTB, input INJECTSBITERR, input INJECTDBITERR, input ECCPIPECE, input SLEEP, output SBITERR, output DBITERR, output [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// // Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_4" and it is // only used by this module to print warning messages. It is neither passed // down from blk_mem_gen_v8_3_4_xst.v nor present in the instantiation template // coregen generates //*************************************************************************** // constants for the core behavior //*************************************************************************** // file handles for logging //-------------------------------------------------- localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range localparam COLLFILE = 32'h8000_0001; //stdout for coll detection localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors // other constants //-------------------------------------------------- localparam COLL_DELAY = 100; // 100 ps // locally derived parameters to determine memory shape //----------------------------------------------------- localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? C_WRITE_WIDTH_A : C_READ_WIDTH_A; localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? C_WRITE_WIDTH_B : C_READ_WIDTH_B; localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? MIN_WIDTH_A : MIN_WIDTH_B; localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? C_WRITE_DEPTH_A : C_READ_DEPTH_A; localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? C_WRITE_DEPTH_B : C_READ_DEPTH_B; localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? MAX_DEPTH_A : MAX_DEPTH_B; // locally derived parameters to assist memory access //---------------------------------------------------- // Calculate the width ratios of each port with respect to the narrowest // port localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; // To modify the LSBs of the 'wider' data to the actual // address value //---------------------------------------------------- localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; // If byte writes aren't being used, make sure BYTE_SIZE is not // wider than the memory elements to avoid compilation warnings localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; // The memory reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1]; reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; // ECC error arrays reg sbiterr_arr [0:MAX_DEPTH-1]; reg dbiterr_arr [0:MAX_DEPTH-1]; reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; // Memory output 'latches' reg [C_READ_WIDTH_A-1:0] memory_out_a; reg [C_READ_WIDTH_B-1:0] memory_out_b; // ECC error inputs and outputs from output_stage module: reg sbiterr_in; wire sbiterr_sdp; reg dbiterr_in; wire dbiterr_sdp; wire [C_READ_WIDTH_B-1:0] dout_i; wire dbiterr_i; wire sbiterr_i; wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; // Reset values reg [C_READ_WIDTH_A-1:0] inita_val; reg [C_READ_WIDTH_B-1:0] initb_val; // Collision detect reg is_collision; reg is_collision_a, is_collision_delay_a; reg is_collision_b, is_collision_delay_b; // Temporary variables for initialization //--------------------------------------- integer status; integer initfile; integer meminitfile; // data input buffer reg [C_WRITE_WIDTH_A-1:0] mif_data; reg [C_WRITE_WIDTH_A-1:0] mem_data; // string values in hex reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; // initialization filename reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE; //Constants used to calculate the effective address widths for each of the //four ports. integer cnt = 1; integer write_addr_a_width, read_addr_a_width; integer write_addr_b_width, read_addr_b_width; localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))))))); // Internal configuration parameters //--------------------------------------------- localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); localparam HAS_A_WRITE = (!IS_ROM); localparam HAS_B_WRITE = (C_MEM_TYPE==2); localparam HAS_A_READ = (C_MEM_TYPE!=1); localparam HAS_B_READ = (!SINGLE_PORT); localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); // Calculate the mux pipeline register stages for Port A and Port B //------------------------------------------------------------------ localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? C_MUX_PIPELINE_STAGES : 0; localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? C_MUX_PIPELINE_STAGES : 0; // Calculate total number of register stages in the core // ----------------------------------------------------- localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); wire ena_i; wire enb_i; wire reseta_i; wire resetb_i; wire [C_WEA_WIDTH-1:0] wea_i; wire [C_WEB_WIDTH-1:0] web_i; wire rea_i; wire reb_i; wire rsta_outp_stage; wire rstb_outp_stage; // ECC SBITERR/DBITERR Outputs // The ECC Behavior is modeled by the behavioral models only for Virtex-6. // For Virtex-5, these outputs will be tied to 0. assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; // This effectively wires off optional inputs assign ena_i = (C_HAS_ENA==0) || ENA; assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; //assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; // To Fix CR855535 assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0; assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; assign rea_i = (HAS_A_READ) ? ena_i : 'b0; assign reb_i = (HAS_B_READ) ? enb_i : 'b0; // These signals reset the memory latches assign reseta_i = ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); assign resetb_i = ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); // Tasks to access the memory //--------------------------- //************** // write_a //************** task write_a (input reg [C_ADDRA_WIDTH-1:0] addr, input reg [C_WEA_WIDTH-1:0] byte_en, input reg [C_WRITE_WIDTH_A-1:0] data, input inj_sbiterr, input inj_dbiterr); reg [C_WRITE_WIDTH_A-1:0] current_contents; reg [C_ADDRA_WIDTH-1:0] address; integer i; begin // Shift the address by the ratio address = (addr/WRITE_ADDR_A_DIV); if (address >= C_WRITE_DEPTH_A) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for A Write", C_CORENAME, addr); end // valid address end else begin // Combine w/ byte writes if (C_USE_BYTE_WEA) begin // Get the current memory contents if (WRITE_WIDTH_RATIO_A == 1) begin // Workaround for IUS 5.5 part-select issue current_contents = memory[address]; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin current_contents[MIN_WIDTH*i+:MIN_WIDTH] = memory[address*WRITE_WIDTH_RATIO_A + i]; end end // Apply incoming bytes if (C_WEA_WIDTH == 1) begin // Workaround for IUS 5.5 part-select issue if (byte_en[0]) begin current_contents = data; end end else begin for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin if (byte_en[i]) begin current_contents[BYTE_SIZE*i+:BYTE_SIZE] = data[BYTE_SIZE*i+:BYTE_SIZE]; end end end // No byte-writes, overwrite the whole word end else begin current_contents = data; end // Insert double bit errors: if (C_USE_ECC == 1) begin if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin // Modified for Implementing CR_859399 current_contents[0] = !(current_contents[30]); current_contents[1] = !(current_contents[62]); /*current_contents[0] = !(current_contents[0]); current_contents[1] = !(current_contents[1]);*/ end end // Insert softecc double bit errors: if (C_USE_SOFTECC == 1) begin if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; end end // Write data to memory if (WRITE_WIDTH_RATIO_A == 1) begin // Workaround for IUS 5.5 part-select issue memory[address*WRITE_WIDTH_RATIO_A] = current_contents; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin memory[address*WRITE_WIDTH_RATIO_A + i] = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; end end // Store the address at which error is injected: if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) begin sbiterr_arr[addr] = 1; end else begin sbiterr_arr[addr] = 0; end if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin dbiterr_arr[addr] = 1; end else begin dbiterr_arr[addr] = 0; end end // Store the address at which softecc error is injected: if (C_USE_SOFTECC == 1) begin if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) begin softecc_sbiterr_arr[addr] = 1; end else begin softecc_sbiterr_arr[addr] = 0; end if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin softecc_dbiterr_arr[addr] = 1; end else begin softecc_dbiterr_arr[addr] = 0; end end end end endtask //************** // write_b //************** task write_b (input reg [C_ADDRB_WIDTH-1:0] addr, input reg [C_WEB_WIDTH-1:0] byte_en, input reg [C_WRITE_WIDTH_B-1:0] data); reg [C_WRITE_WIDTH_B-1:0] current_contents; reg [C_ADDRB_WIDTH-1:0] address; integer i; begin // Shift the address by the ratio address = (addr/WRITE_ADDR_B_DIV); if (address >= C_WRITE_DEPTH_B) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for B Write", C_CORENAME, addr); end // valid address end else begin // Combine w/ byte writes if (C_USE_BYTE_WEB) begin // Get the current memory contents if (WRITE_WIDTH_RATIO_B == 1) begin // Workaround for IUS 5.5 part-select issue current_contents = memory[address]; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin current_contents[MIN_WIDTH*i+:MIN_WIDTH] = memory[address*WRITE_WIDTH_RATIO_B + i]; end end // Apply incoming bytes if (C_WEB_WIDTH == 1) begin // Workaround for IUS 5.5 part-select issue if (byte_en[0]) begin current_contents = data; end end else begin for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin if (byte_en[i]) begin current_contents[BYTE_SIZE*i+:BYTE_SIZE] = data[BYTE_SIZE*i+:BYTE_SIZE]; end end end // No byte-writes, overwrite the whole word end else begin current_contents = data; end // Write data to memory if (WRITE_WIDTH_RATIO_B == 1) begin // Workaround for IUS 5.5 part-select issue memory[address*WRITE_WIDTH_RATIO_B] = current_contents; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin memory[address*WRITE_WIDTH_RATIO_B + i] = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; end end end end endtask //************** // read_a //************** task read_a (input reg [C_ADDRA_WIDTH-1:0] addr, input reg reset); reg [C_ADDRA_WIDTH-1:0] address; integer i; begin if (reset) begin memory_out_a <= #FLOP_DELAY inita_val; end else begin // Shift the address by the ratio address = (addr/READ_ADDR_A_DIV); if (address >= C_READ_DEPTH_A) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for A Read", C_CORENAME, addr); end memory_out_a <= #FLOP_DELAY 'bX; // valid address end else begin if (READ_WIDTH_RATIO_A==1) begin memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; end else begin // Increment through the 'partial' words in the memory for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; end end //end READ_WIDTH_RATIO_A==1 loop end //end valid address loop end //end reset-data assignment loops end endtask //************** // read_b //************** task read_b (input reg [C_ADDRB_WIDTH-1:0] addr, input reg reset); reg [C_ADDRB_WIDTH-1:0] address; integer i; begin if (reset) begin memory_out_b <= #FLOP_DELAY initb_val; sbiterr_in <= #FLOP_DELAY 1'b0; dbiterr_in <= #FLOP_DELAY 1'b0; rdaddrecc_in <= #FLOP_DELAY 0; end else begin // Shift the address address = (addr/READ_ADDR_B_DIV); if (address >= C_READ_DEPTH_B) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for B Read", C_CORENAME, addr); end memory_out_b <= #FLOP_DELAY 'bX; sbiterr_in <= #FLOP_DELAY 1'bX; dbiterr_in <= #FLOP_DELAY 1'bX; rdaddrecc_in <= #FLOP_DELAY 'bX; // valid address end else begin if (READ_WIDTH_RATIO_B==1) begin memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; end else begin // Increment through the 'partial' words in the memory for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; end end if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin rdaddrecc_in <= #FLOP_DELAY addr; if (sbiterr_arr[addr] == 1) begin sbiterr_in <= #FLOP_DELAY 1'b1; end else begin sbiterr_in <= #FLOP_DELAY 1'b0; end if (dbiterr_arr[addr] == 1) begin dbiterr_in <= #FLOP_DELAY 1'b1; end else begin dbiterr_in <= #FLOP_DELAY 1'b0; end end else if (C_USE_SOFTECC == 1) begin rdaddrecc_in <= #FLOP_DELAY addr; if (softecc_sbiterr_arr[addr] == 1) begin sbiterr_in <= #FLOP_DELAY 1'b1; end else begin sbiterr_in <= #FLOP_DELAY 1'b0; end if (softecc_dbiterr_arr[addr] == 1) begin dbiterr_in <= #FLOP_DELAY 1'b1; end else begin dbiterr_in <= #FLOP_DELAY 1'b0; end end else begin rdaddrecc_in <= #FLOP_DELAY 0; dbiterr_in <= #FLOP_DELAY 1'b0; sbiterr_in <= #FLOP_DELAY 1'b0; end //end SOFTECC Loop end //end Valid address loop end //end reset-data assignment loops end endtask //************** // reset_a //************** task reset_a (input reg reset); begin if (reset) memory_out_a <= #FLOP_DELAY inita_val; end endtask //************** // reset_b //************** task reset_b (input reg reset); begin if (reset) memory_out_b <= #FLOP_DELAY initb_val; end endtask //************** // init_memory //************** task init_memory; integer i, j, addr_step; integer status; reg [C_WRITE_WIDTH_A-1:0] default_data; begin default_data = 0; //Display output message indicating that the behavioral model is being //initialized if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data..."); // Convert the default to hex if (C_USE_DEFAULT_DATA) begin if (default_data_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); $finish; end else begin status = $sscanf(default_data_str, "%h", default_data); if (status == 0) begin $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", "from C_DEFAULT_DATA: %0s"}, C_CORENAME, C_DEFAULT_DATA); $finish; end end end // Step by WRITE_ADDR_A_DIV through the memory via the // Port A write interface to hit every location once addr_step = WRITE_ADDR_A_DIV; // 'write' to every location with default (or 0) for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); end // Get specialized data from the MIF file if (C_LOAD_INIT_FILE) begin if (init_file_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", C_CORENAME); $finish; end else begin initfile = $fopen(init_file_str, "r"); if (initfile == 0) begin $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", "C_INIT_FILE_NAME: %0s!"}, C_CORENAME, init_file_str); $finish; end else begin // loop through the mif file, loading in the data for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin status = $fscanf(initfile, "%b", mif_data); if (status > 0) begin write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); end end $fclose(initfile); end //initfile end //init_file_str end //C_LOAD_INIT_FILE if (C_USE_BRAM_BLOCK) begin // Get specialized data from the MIF file if (C_INIT_FILE != "NONE") begin if (mem_init_file_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!", C_CORENAME); $finish; end else begin meminitfile = $fopen(mem_init_file_str, "r"); if (meminitfile == 0) begin $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", "C_INIT_FILE: %0s!"}, C_CORENAME, mem_init_file_str); $finish; end else begin // loop through the mif file, loading in the data $readmemh(mem_init_file_str, memory ); for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin end $fclose(meminitfile); end //meminitfile end //mem_init_file_str end //C_INIT_FILE end //C_USE_BRAM_BLOCK //Display output message indicating that the behavioral model is done //initializing if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator data initialization complete."); end endtask //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //******************* // collision_check //******************* function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, input integer iswrite_a, input reg [C_ADDRB_WIDTH-1:0] addr_b, input integer iswrite_b); reg c_aw_bw, c_aw_br, c_ar_bw; integer scaled_addra_to_waddrb_width; integer scaled_addrb_to_waddrb_width; integer scaled_addra_to_waddra_width; integer scaled_addrb_to_waddra_width; integer scaled_addra_to_raddrb_width; integer scaled_addrb_to_raddrb_width; integer scaled_addra_to_raddra_width; integer scaled_addrb_to_raddra_width; begin c_aw_bw = 0; c_aw_br = 0; c_ar_bw = 0; //If write_addr_b_width is smaller, scale both addresses to that width for //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to write_addr_b_width. Once both are scaled to //write_addr_b_width, compare. scaled_addra_to_waddrb_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-write_addr_b_width)); scaled_addrb_to_waddrb_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-write_addr_b_width)); //If write_addr_a_width is smaller, scale both addresses to that width for //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to write_addr_a_width. Once both are scaled to //write_addr_a_width, compare. scaled_addra_to_waddra_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-write_addr_a_width)); scaled_addrb_to_waddra_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-write_addr_a_width)); //If read_addr_b_width is smaller, scale both addresses to that width for //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to read_addr_b_width. Once both are scaled to //read_addr_b_width, compare. scaled_addra_to_raddrb_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-read_addr_b_width)); scaled_addrb_to_raddrb_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-read_addr_b_width)); //If read_addr_a_width is smaller, scale both addresses to that width for //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to read_addr_a_width. Once both are scaled to //read_addr_a_width, compare. scaled_addra_to_raddra_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-read_addr_a_width)); scaled_addrb_to_raddra_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-read_addr_a_width)); //Look for a write-write collision. In order for a write-write //collision to exist, both ports must have a write transaction. if (iswrite_a && iswrite_b) begin if (write_addr_a_width > write_addr_b_width) begin if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin c_aw_bw = 1; end else begin c_aw_bw = 0; end end else begin if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin c_aw_bw = 1; end else begin c_aw_bw = 0; end end //width end //iswrite_a and iswrite_b //If the B port is reading (which means it is enabled - so could be //a TX_WRITE or TX_READ), then check for a write-read collision). //This could happen whether or not a write-write collision exists due //to asymmetric write/read ports. if (iswrite_a) begin if (write_addr_a_width > read_addr_b_width) begin if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin c_aw_br = 1; end else begin c_aw_br = 0; end end else begin if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin c_aw_br = 1; end else begin c_aw_br = 0; end end //width end //iswrite_a //If the A port is reading (which means it is enabled - so could be // a TX_WRITE or TX_READ), then check for a write-read collision). //This could happen whether or not a write-write collision exists due // to asymmetric write/read ports. if (iswrite_b) begin if (read_addr_a_width > write_addr_b_width) begin if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin c_ar_bw = 1; end else begin c_ar_bw = 0; end end else begin if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin c_ar_bw = 1; end else begin c_ar_bw = 0; end end //width end //iswrite_b collision_check = c_aw_bw | c_aw_br | c_ar_bw; end endfunction //******************************* // power on values //******************************* initial begin // Load up the memory init_memory; // Load up the output registers and latches if ($sscanf(inita_str, "%h", inita_val)) begin memory_out_a = inita_val; end else begin memory_out_a = 0; end if ($sscanf(initb_str, "%h", initb_val)) begin memory_out_b = initb_val; end else begin memory_out_b = 0; end sbiterr_in = 1'b0; dbiterr_in = 1'b0; rdaddrecc_in = 0; // Determine the effective address widths for each of the 4 ports write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); end //*************************************************************************** // These are the main blocks which schedule read and write operations // Note that the reset priority feature at the latch stage is only supported // for Spartan-6. For other families, the default priority at the latch stage // is "CE" //*************************************************************************** // Synchronous clocks: schedule port operations with respect to // both write operating modes generate if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_wf_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_rf_wf always @(posedge CLKA) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_wf_rf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_rf_rf always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_wf_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_rf_nc always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_nc_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_nc_rf always @(posedge CLKA) begin //Read B if (reb_i) read_b(ADDRB, resetb_i); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_nc_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK) begin: com_clk_sched_default always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end endgenerate // Asynchronous clocks: port operation is independent generate if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); end end else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); end end else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); end end endgenerate generate if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf always @(posedge CLKB) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf always @(posedge CLKB) begin //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc always @(posedge CLKB) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); end end endgenerate //*************************************************************** // Instantiate the variable depth output register stage module //*************************************************************** // Port A assign rsta_outp_stage = RSTA & (~SLEEP); blk_mem_gen_v8_3_4_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTA), .C_RSTRAM (C_RSTRAM_A), .C_RST_PRIORITY (C_RST_PRIORITY_A), .C_INIT_VAL (C_INITA_VAL), .C_HAS_EN (C_HAS_ENA), .C_HAS_REGCE (C_HAS_REGCEA), .C_DATA_WIDTH (C_READ_WIDTH_A), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_A), .C_EN_ECC_PIPE (0), .FLOP_DELAY (FLOP_DELAY)) reg_a (.CLK (CLKA), .RST (rsta_outp_stage),//(RSTA), .EN (ENA), .REGCE (REGCEA), .DIN_I (memory_out_a), .DOUT (DOUTA), .SBITERR_IN_I (1'b0), .DBITERR_IN_I (1'b0), .SBITERR (), .DBITERR (), .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), .ECCPIPECE (1'b0), .RDADDRECC () ); assign rstb_outp_stage = RSTB & (~SLEEP); // Port B blk_mem_gen_v8_3_4_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTB), .C_RSTRAM (C_RSTRAM_B), .C_RST_PRIORITY (C_RST_PRIORITY_B), .C_INIT_VAL (C_INITB_VAL), .C_HAS_EN (C_HAS_ENB), .C_HAS_REGCE (C_HAS_REGCEB), .C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_B), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .FLOP_DELAY (FLOP_DELAY)) reg_b (.CLK (CLKB), .RST (rstb_outp_stage),//(RSTB), .EN (ENB), .REGCE (REGCEB), .DIN_I (memory_out_b), .DOUT (dout_i), .SBITERR_IN_I (sbiterr_in), .DBITERR_IN_I (dbiterr_in), .SBITERR (sbiterr_i), .DBITERR (dbiterr_i), .RDADDRECC_IN_I (rdaddrecc_in), .ECCPIPECE (ECCPIPECE), .RDADDRECC (rdaddrecc_i) ); //*************************************************************** // Instantiate the Input and Output register stages //*************************************************************** blk_mem_gen_v8_3_4_softecc_output_reg_stage #(.C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .FLOP_DELAY (FLOP_DELAY)) has_softecc_output_reg_stage (.CLK (CLKB), .DIN (dout_i), .DOUT (DOUTB), .SBITERR_IN (sbiterr_i), .DBITERR_IN (dbiterr_i), .SBITERR (sbiterr_sdp), .DBITERR (dbiterr_sdp), .RDADDRECC_IN (rdaddrecc_i), .RDADDRECC (rdaddrecc_sdp) ); //**************************************************** // Synchronous collision checks //**************************************************** // CR 780544 : To make verilog model's collison warnings in consistant with // vhdl model, the non-blocking assignments are replaced with blocking // assignments. generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision = 0; end end else begin is_collision = 0; end // If the write port is in READ_FIRST mode, there is no collision if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin is_collision = 0; end if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin is_collision = 0; end // Only flag if one of the accesses is a write if (is_collision && (wea_i || web_i)) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", wea_i ? "write" : "read", ADDRA, web_i ? "write" : "read", ADDRB); end end //**************************************************** // Asynchronous collision checks //**************************************************** end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll // Delay A and B addresses in order to mimic setup/hold times wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; wire [0:0] #COLL_DELAY wea_delay = wea_i; wire #COLL_DELAY ena_delay = ena_i; wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; wire [0:0] #COLL_DELAY web_delay = web_i; wire #COLL_DELAY enb_delay = enb_i; // Do the checks w/rt A always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_a = 0; end end else begin is_collision_a = 0; end if (ena_i && enb_delay) begin if(wea_i || web_delay) begin is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, web_delay); end else begin is_collision_delay_a = 0; end end else begin is_collision_delay_a = 0; end // Only flag if B access is a write if (is_collision_a && web_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, ADDRB); end else if (is_collision_delay_a && web_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, addrb_delay); end end // Do the checks w/rt B always @(posedge CLKB) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_b = 0; end end else begin is_collision_b = 0; end if (ena_delay && enb_i) begin if (wea_delay || web_i) begin is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, web_i); end else begin is_collision_delay_b = 0; end end else begin is_collision_delay_b = 0; end // Only flag if A access is a write if (is_collision_b && wea_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", ADDRA, web_i ? "write" : "read", ADDRB); end else if (is_collision_delay_b && wea_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", addra_delay, web_i ? "write" : "read", ADDRB); end end end endgenerate endmodule //***************************************************************************** // Top module wraps Input register and Memory module // // This module is the top-level behavioral model and this implements the memory // module and the input registers //***************************************************************************** module blk_mem_gen_v8_3_4 #(parameter C_CORENAME = "blk_mem_gen_v8_3_4", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_ELABORATION_DIR = "", parameter C_INTERFACE_TYPE = 0, parameter C_USE_BRAM_BLOCK = 0, parameter C_CTRL_ECC_ALGO = "NONE", parameter C_ENABLE_32BIT_ADDRESS = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", //parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_EN_ECC_PIPE = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_SLEEP_PIN = 0, parameter C_USE_URAM = 0, parameter C_EN_RDADDRA_CHG = 0, parameter C_EN_RDADDRB_CHG = 0, parameter C_EN_DEEPSLEEP_PIN = 0, parameter C_EN_SHUTDOWN_PIN = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_COUNT_36K_BRAM = "", parameter C_COUNT_18K_BRAM = "", parameter C_EST_POWER_SUMMARY = "", parameter C_DISABLE_WARN_BHV_RANGE = 0 ) (input clka, input rsta, input ena, input regcea, input [C_WEA_WIDTH-1:0] wea, input [C_ADDRA_WIDTH-1:0] addra, input [C_WRITE_WIDTH_A-1:0] dina, output [C_READ_WIDTH_A-1:0] douta, input clkb, input rstb, input enb, input regceb, input [C_WEB_WIDTH-1:0] web, input [C_ADDRB_WIDTH-1:0] addrb, input [C_WRITE_WIDTH_B-1:0] dinb, output [C_READ_WIDTH_B-1:0] doutb, input injectsbiterr, input injectdbiterr, output sbiterr, output dbiterr, output [C_ADDRB_WIDTH-1:0] rdaddrecc, input eccpipece, input sleep, input deepsleep, input shutdown, output rsta_busy, output rstb_busy, //AXI BMG Input and Output Port Declarations //AXI Global Signals input s_aclk, input s_aresetn, //AXI Full/lite slave write (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [31:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input s_axi_awvalid, output s_axi_awready, input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, input [C_WEA_WIDTH-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, input s_axi_bready, //AXI Full/lite slave read (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [31:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, input s_axi_rready, //AXI Full/lite sideband signals input s_axi_injectsbiterr, input s_axi_injectdbiterr, output s_axi_sbiterr, output s_axi_dbiterr, output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_HAS_SOFTECC_INPUT_REGS_A : // C_HAS_SOFTECC_OUTPUT_REGS_B : // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// wire SBITERR; wire DBITERR; wire S_AXI_AWREADY; wire S_AXI_WREADY; wire S_AXI_BVALID; wire S_AXI_ARREADY; wire S_AXI_RLAST; wire S_AXI_RVALID; wire S_AXI_SBITERR; wire S_AXI_DBITERR; wire [C_WEA_WIDTH-1:0] WEA = wea; wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; wire [C_WRITE_WIDTH_A-1:0] DINA = dina; wire [C_READ_WIDTH_A-1:0] DOUTA; wire [C_WEB_WIDTH-1:0] WEB = web; wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; wire [C_READ_WIDTH_B-1:0] DOUTB; wire [C_ADDRB_WIDTH-1:0] RDADDRECC; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; wire [31:0] S_AXI_AWADDR = s_axi_awaddr; wire [7:0] S_AXI_AWLEN = s_axi_awlen; wire [2:0] S_AXI_AWSIZE = s_axi_awsize; wire [1:0] S_AXI_AWBURST = s_axi_awburst; wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [1:0] S_AXI_BRESP; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; wire [31:0] S_AXI_ARADDR = s_axi_araddr; wire [7:0] S_AXI_ARLEN = s_axi_arlen; wire [2:0] S_AXI_ARSIZE = s_axi_arsize; wire [1:0] S_AXI_ARBURST = s_axi_arburst; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; wire [1:0] S_AXI_RRESP; wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; // Added to fix the simulation warning #CR731605 wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; wire ECCPIPECE; wire SLEEP; reg RSTA_BUSY = 0; reg RSTB_BUSY = 0; // Declaration of internal signals to avoid warnings #927399 wire CLKA; wire RSTA; wire ENA; wire REGCEA; wire CLKB; wire RSTB; wire ENB; wire REGCEB; wire INJECTSBITERR; wire INJECTDBITERR; wire S_ACLK; wire S_ARESETN; wire S_AXI_AWVALID; wire S_AXI_WLAST; wire S_AXI_WVALID; wire S_AXI_BREADY; wire S_AXI_ARVALID; wire S_AXI_RREADY; wire S_AXI_INJECTSBITERR; wire S_AXI_INJECTDBITERR; assign CLKA = clka; assign RSTA = rsta; assign ENA = ena; assign REGCEA = regcea; assign CLKB = clkb; assign RSTB = rstb; assign ENB = enb; assign REGCEB = regceb; assign INJECTSBITERR = injectsbiterr; assign INJECTDBITERR = injectdbiterr; assign ECCPIPECE = eccpipece; assign SLEEP = sleep; assign sbiterr = SBITERR; assign dbiterr = DBITERR; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; assign s_axi_sbiterr = S_AXI_SBITERR; assign s_axi_dbiterr = S_AXI_DBITERR; assign rsta_busy = RSTA_BUSY; assign rstb_busy = RSTB_BUSY; assign doutb = DOUTB; assign douta = DOUTA; assign rdaddrecc = RDADDRECC; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_rdaddrecc = S_AXI_RDADDRECC; localparam FLOP_DELAY = 100; // 100 ps reg injectsbiterr_in; reg injectdbiterr_in; reg rsta_in; reg ena_in; reg regcea_in; reg [C_WEA_WIDTH-1:0] wea_in; reg [C_ADDRA_WIDTH-1:0] addra_in; reg [C_WRITE_WIDTH_A-1:0] dina_in; wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; wire s_axi_wr_en_c; wire s_axi_rd_en_c; wire s_aresetn_a_c; wire [7:0] s_axi_arlen_c ; wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; wire [1:0] s_axi_rresp_c; wire s_axi_rlast_c; wire s_axi_rvalid_c; wire s_axi_rready_c; wire regceb_c; localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; // Safety logic related signals reg [4:0] RSTA_SHFT_REG = 0; reg POR_A = 0; reg [4:0] RSTB_SHFT_REG = 0; reg POR_B = 0; reg ENA_dly = 0; reg ENA_dly_D = 0; reg ENB_dly = 0; reg ENB_dly_D = 0; wire RSTA_I_SAFE; wire RSTB_I_SAFE; wire ENA_I_SAFE; wire ENB_I_SAFE; reg ram_rstram_a_busy = 0; reg ram_rstreg_a_busy = 0; reg ram_rstram_b_busy = 0; reg ram_rstreg_b_busy = 0; reg ENA_dly_reg = 0; reg ENB_dly_reg = 0; reg ENA_dly_reg_D = 0; reg ENB_dly_reg_D = 0; //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //************** // log2int //************** function integer log2int (input integer data_value); integer width; integer cnt; begin width = 0; cnt= data_value; for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin width = width + 1; end //loop log2int = width; end //log2int endfunction //************************************************************************** // FUNCTION : divroundup // Returns the ceiling value of the division // Data_value - the quantity to be divided, dividend // Divisor - the value to divide the data_value by //************************************************************************** function integer divroundup (input integer data_value,input integer divisor); integer div; begin div = data_value/divisor; if ((data_value % divisor) != 0) begin div = div+1; end //if divroundup = div; end //if endfunction localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; //Data Width Number of LSB address bits to be discarded //1 to 16 1 //17 to 32 2 //33 to 64 3 //65 to 128 4 //129 to 256 5 //257 to 512 6 //513 to 1024 7 // The following two constants determine this. localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); localparam C_AXI_OS_WR = 2; //*********************************************** // INPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage always @* begin injectsbiterr_in = INJECTSBITERR; injectdbiterr_in = INJECTDBITERR; rsta_in = RSTA; ena_in = ENA; regcea_in = REGCEA; wea_in = WEA; addra_in = ADDRA; dina_in = DINA; end //end always end //end no_softecc_input_reg_stage endgenerate generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage always @(posedge CLKA) begin injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; rsta_in <= #FLOP_DELAY RSTA; ena_in <= #FLOP_DELAY ENA; regcea_in <= #FLOP_DELAY REGCEA; wea_in <= #FLOP_DELAY WEA; addra_in <= #FLOP_DELAY ADDRA; dina_in <= #FLOP_DELAY DINA; end //end always end //end input_reg_stages generate statement endgenerate //************************************************************************** // NO SAFETY LOGIC //************************************************************************** generate if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN assign ENA_I_SAFE = ena_in; assign ENB_I_SAFE = ENB; assign RSTA_I_SAFE = rsta_in; assign RSTB_I_SAFE = RSTB; end endgenerate //*************************************************************************** // SAFETY LOGIC // Power-ON Reset Generation //*************************************************************************** generate if (C_EN_SAFETY_CKT == 1) begin always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ; always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0]; always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ; always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; assign RSTA_I_SAFE = rsta_in | POR_A; assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B); end endgenerate //----------------------------------------------------------------------------- // -- RSTA/B_BUSY Generation //----------------------------------------------------------------------------- generate if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D; always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D; always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy; end endgenerate generate if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY always @(*) RSTB_BUSY = 1'b0; end endgenerate generate if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D; always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D; always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy; end endgenerate //----------------------------------------------------------------------------- // -- ENA/ENB Generation //----------------------------------------------------------------------------- generate if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG always @(posedge clka) begin ENA_dly <= #FLOP_DELAY RSTA_I_SAFE; ENA_dly_D <= #FLOP_DELAY ENA_dly; end assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in); end endgenerate generate if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG always @(posedge clka) begin ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE; ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg; end assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in); end endgenerate generate if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB assign ENB_I_SAFE = 1'b0; end endgenerate generate if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG always @(posedge clkb) begin : PROC_ENB_GEN ENB_dly <= #FLOP_DELAY RSTB_I_SAFE; ENB_dly_D <= #FLOP_DELAY ENB_dly; end assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG always @(posedge clkb) begin : PROC_ENB_GEN ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE; ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg; end assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB); end endgenerate generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_ALGORITHM (C_ALGORITHM), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (CLKA), .RSTA (RSTA_I_SAFE),//(rsta_in), .ENA (ENA_I_SAFE),//(ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB_I_SAFE),//(RSTB), .ENB (ENB_I_SAFE),//(ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (RDADDRECC) ); end endgenerate generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; // Data Width Number of LSB address bits to be discarded // 1 to 16 1 // 17 to 32 2 // 33 to 64 3 // 65 to 128 4 // 129 to 256 5 // 257 to 512 6 // 513 to 1024 7 // The following two constants determine this. localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; assign msb_zero_i = 0; assign lsb_zero_i = 0; assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (CLKA), .RSTA (RSTA_I_SAFE),//(rsta_in), .ENA (ENA_I_SAFE),//(ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB_I_SAFE),//(RSTB), .ENB (ENB_I_SAFE),//(ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (rdaddrecc_i) ); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RLAST = s_axi_rlast_c; assign S_AXI_RVALID = s_axi_rvalid_c; assign S_AXI_RID = s_axi_rid_c; assign S_AXI_RRESP = s_axi_rresp_c; assign s_axi_rready_c = S_AXI_RREADY; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb assign regceb_c = REGCEB; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd blk_mem_axi_regs_fwd_v8_3 #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) axi_regs_inst ( .ACLK (S_ACLK), .ARESET (s_aresetn_a_c), .S_VALID (s_axi_rvalid_c), .S_READY (s_axi_rready_c), .S_PAYLOAD_DATA (s_axi_payload_c), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY), .M_PAYLOAD_DATA (m_axi_payload_c) ); end endgenerate generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module assign s_aresetn_a_c = !S_ARESETN; assign S_AXI_BRESP = 2'b00; assign s_axi_rresp_c = 2'b00; assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; blk_mem_axi_write_wrapper_beh_v8_3 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), .C_AXI_OS_WR (C_AXI_OS_WR)) axi_wr_fsm ( // AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), // AXI Full/Lite Slave Write interface .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_AWLEN (S_AXI_AWLEN), .S_AXI_AWID (S_AXI_AWID), .S_AXI_AWSIZE (S_AXI_AWSIZE), .S_AXI_AWBURST (S_AXI_AWBURST), .S_AXI_AWVALID (S_AXI_AWVALID), .S_AXI_AWREADY (S_AXI_AWREADY), .S_AXI_WVALID (S_AXI_WVALID), .S_AXI_WREADY (S_AXI_WREADY), .S_AXI_BVALID (S_AXI_BVALID), .S_AXI_BREADY (S_AXI_BREADY), .S_AXI_BID (S_AXI_BID), // Signals for BRAM interfac( .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), .S_AXI_WR_EN (s_axi_wr_en_c) ); blk_mem_axi_read_wrapper_beh_v8_3 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_PIPELINE_STAGES (1), .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_rd_sm( //AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), //AXI Full/Lite Read Side .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_ARLEN (s_axi_arlen_c), .S_AXI_ARSIZE (S_AXI_ARSIZE), .S_AXI_ARBURST (S_AXI_ARBURST), .S_AXI_ARVALID (S_AXI_ARVALID), .S_AXI_ARREADY (S_AXI_ARREADY), .S_AXI_RLAST (s_axi_rlast_c), .S_AXI_RVALID (s_axi_rvalid_c), .S_AXI_RREADY (s_axi_rready_c), .S_AXI_ARID (S_AXI_ARID), .S_AXI_RID (s_axi_rid_c), //AXI Full/Lite Read FSM Outputs .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), .S_AXI_RD_EN (s_axi_rd_en_c) ); blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (1), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (1), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (1), .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_BYTE_WEB (1), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (0), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (0), .C_HAS_MUX_OUTPUT_REGS_B (0), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (0), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (S_ACLK), .RSTA (s_aresetn_a_c), .ENA (s_axi_wr_en_c), .REGCEA (regcea_in), .WEA (S_AXI_WSTRB), .ADDRA (s_axi_awaddr_out_c), .DINA (S_AXI_WDATA), .DOUTA (DOUTA), .CLKB (S_ACLK), .RSTB (s_aresetn_a_c), .ENB (s_axi_rd_en_c), .REGCEB (regceb_c), .WEB (WEB_parameterized), .ADDRB (s_axi_araddr_out_c), .DINB (DINB), .DOUTB (s_axi_rdata_c), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .SBITERR (SBITERR), .DBITERR (DBITERR), .ECCPIPECE (1'b0), .SLEEP (1'b0), .RDADDRECC (RDADDRECC) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/synth/input_line_buffer.vhd ================================================ -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_4; USE blk_mem_gen_v8_3_4.blk_mem_gen_v8_3_4; ENTITY input_line_buffer IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0) ); END input_line_buffer; ARCHITECTURE input_line_buffer_arch OF input_line_buffer IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF input_line_buffer_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_4 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(255 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_4; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF input_line_buffer_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_4,Vivado 2016.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF input_line_buffer_arch : ARCHITECTURE IS "input_line_buffer,blk_mem_gen_v8_3_4,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF input_line_buffer_arch: ARCHITECTURE IS "input_line_buffer,blk_mem_gen_v8_3_4,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME" & "=no_coe_file_loaded,C_INIT_FILE=input_line_buffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=256,C_REA" & "D_WIDTH_B=256,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_E" & "N_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 36.714252 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_3_4 GENERIC MAP ( C_FAMILY => "kintex7", C_XDEVICEFAMILY => "kintex7", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 1, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "input_line_buffer.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "NO_CHANGE", C_WRITE_WIDTH_A => 64, C_READ_WIDTH_A => 64, C_WRITE_DEPTH_A => 4096, C_READ_DEPTH_A => 4096, C_ADDRA_WIDTH => 12, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 256, C_READ_WIDTH_B => 256, C_WRITE_DEPTH_B => 1024, C_READ_DEPTH_B => 1024, C_ADDRB_WIDTH => 10, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "7", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 36.714252 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, clkb => clkb, rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => addrb, dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 256)), doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END input_line_buffer_arch; ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd ================================================ [File too large to display: 14.2 MB] ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/misc/blk_mem_gen_v8_3.vhd ================================================ library ieee; use ieee.std_logic_1164.all; entity blk_mem_gen_v8_3_4 is generic ( C_FAMILY : string := "virtex7"; C_XDEVICEFAMILY : string := "virtex7"; C_ELABORATION_DIR : string := ""; C_INTERFACE_TYPE : integer := 0; C_AXI_TYPE : integer := 1; C_AXI_SLAVE_TYPE : integer := 0; C_USE_BRAM_BLOCK : integer := 0; C_ENABLE_32BIT_ADDRESS : integer := 0; C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7"; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; C_MEM_TYPE : integer := 2; C_BYTE_SIZE : integer := 9; C_ALGORITHM : integer := 0; C_PRIM_TYPE : integer := 3; C_LOAD_INIT_FILE : integer := 0; C_INIT_FILE_NAME : string := "no_coe_file_loaded"; C_INIT_FILE : string := "no_mem_file_loaded"; C_USE_DEFAULT_DATA : integer := 0; C_DEFAULT_DATA : string := "0"; C_HAS_RSTA : integer := 0; C_RST_PRIORITY_A : string := "ce"; C_RSTRAM_A : integer := 0; C_INITA_VAL : string := "0"; C_HAS_ENA : integer := 1; C_HAS_REGCEA : integer := 0; C_USE_BYTE_WEA : integer := 0; C_WEA_WIDTH : integer := 1; C_WRITE_MODE_A : string := "WRITE_FIRST"; C_WRITE_WIDTH_A : integer := 9; C_READ_WIDTH_A : integer := 9; C_WRITE_DEPTH_A : integer := 2048; C_READ_DEPTH_A : integer := 2048; C_ADDRA_WIDTH : integer := 11; C_HAS_RSTB : integer := 0; C_RST_PRIORITY_B : string := "ce"; C_RSTRAM_B : integer := 0; C_INITB_VAL : string := "0"; C_HAS_ENB : integer := 1; C_HAS_REGCEB : integer := 0; C_USE_BYTE_WEB : integer := 0; C_WEB_WIDTH : integer := 1; C_WRITE_MODE_B : string := "WRITE_FIRST"; C_WRITE_WIDTH_B : integer := 9; C_READ_WIDTH_B : integer := 9; C_WRITE_DEPTH_B : integer := 2048; C_READ_DEPTH_B : integer := 2048; C_ADDRB_WIDTH : integer := 11; C_HAS_MEM_OUTPUT_REGS_A : integer := 0; C_HAS_MEM_OUTPUT_REGS_B : integer := 0; C_HAS_MUX_OUTPUT_REGS_A : integer := 0; C_HAS_MUX_OUTPUT_REGS_B : integer := 0; C_MUX_PIPELINE_STAGES : integer := 0; C_HAS_SOFTECC_INPUT_REGS_A : integer := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0; C_USE_SOFTECC : integer := 0; C_USE_ECC : integer := 0; C_EN_ECC_PIPE : integer := 0; C_HAS_INJECTERR : integer := 0; C_SIM_COLLISION_CHECK : string := "none"; C_COMMON_CLK : integer := 0; C_DISABLE_WARN_BHV_COLL : integer := 0; C_EN_SLEEP_PIN : integer := 0; C_USE_URAM : integer := 0; C_EN_RDADDRA_CHG : integer := 0; C_EN_RDADDRB_CHG : integer := 0; C_EN_DEEPSLEEP_PIN : integer := 0; C_EN_SHUTDOWN_PIN : integer := 0; C_EN_SAFETY_CKT : integer := 0; C_DISABLE_WARN_BHV_RANGE : integer := 0; C_COUNT_36K_BRAM : string := ""; C_COUNT_18K_BRAM : string := ""; C_EST_POWER_SUMMARY : string := "" ); port ( clka : in std_logic := '0'; rsta : in std_logic := '0'; ena : in std_logic := '0'; regcea : in std_logic := '0'; wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0'); addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0'); dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0'); douta : out std_logic_vector(c_read_width_a - 1 downto 0); clkb : in std_logic := '0'; rstb : in std_logic := '0'; enb : in std_logic := '0'; regceb : in std_logic := '0'; web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0'); addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0'); dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0'); doutb : out std_logic_vector(c_read_width_b - 1 downto 0); injectsbiterr : in std_logic := '0'; injectdbiterr : in std_logic := '0'; eccpipece : in std_logic := '0'; sbiterr : out std_logic; dbiterr : out std_logic; rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0); sleep : in std_logic := '0'; deepsleep : in std_logic := '0'; shutdown : in std_logic := '0'; rsta_busy : out std_logic; rstb_busy : out std_logic; s_aclk : in std_logic := '0'; s_aresetn : in std_logic := '0'; s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0'); s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0'); s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0'); s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0'); s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0'); s_axi_awvalid : in std_logic := '0'; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0'); s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0'); s_axi_wlast : in std_logic := '0'; s_axi_wvalid : in std_logic := '0'; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic := '0'; s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0'); s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0'); s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0'); s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0'); s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0'); s_axi_arvalid : in std_logic := '0'; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0); s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0); s_axi_rresp : out std_logic_vector(2 - 1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic := '0'; s_axi_injectsbiterr : in std_logic := '0'; s_axi_injectdbiterr : in std_logic := '0'; s_axi_sbiterr : out std_logic; s_axi_dbiterr : out std_logic; s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0) ); end entity blk_mem_gen_v8_3_4; architecture xilinx of blk_mem_gen_v8_3_4 is begin end architecture xilinx; ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci ================================================ xilinx.com xci unknown 1.0 output_line_buffer 4096 10 12 1 4 0 1 9 0 1 7 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 33.580152 mW kintex7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 output_line_buffer.mem no_coe_file_loaded 0 0 1 0 1 1024 4096 256 64 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 1024 4096 NO_CHANGE WRITE_FIRST 256 64 kintex7 4 Memory_Slave AXI4_Full false Minimum_Area false 9 NONE no_coe_file_loaded ALL output_line_buffer false false false false false false false false false Use_ENA_Pin Always_Enabled Single_Bit_Error_Injection false Native false no_mem_loaded Simple_Dual_Port_RAM NO_CHANGE WRITE_FIRST 0 0 BRAM 0 100 100 50 100 100 0 8kx2 false false 256 64 false false false false 0 false false CE CE SYNC false false false false false false false 1024 256 64 No_ECC false false false Stand_Alone kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 4 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_ooc.xdc ================================================ ################################################################################ # # (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and # international copyright and other intellectual property # laws. # # DISCLAIMER # This disclaimer is not a license and does not grant any # rights to the materials distributed herewith. Except as # otherwise provided in a valid license issued to you by # Xilinx, and to the maximum extent permitted by applicable # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and # (2) Xilinx shall not be liable (whether in contract or tort, # including negligence, or under any other theory of # liability) for any loss or damage of any kind or nature # related to, arising under or in connection with these # materials, including for any direct, or any indirect, # special, incidental, or consequential loss or damage # (including loss of data, profits, goodwill, or any type of # loss or damage suffered as a result of any action brought # by a third party) even if such damage or loss was # reasonably foreseeable or Xilinx had been advised of the # possibility of the same. # # CRITICAL APPLICATIONS # Xilinx products are not designed or intended to be fail- # safe, or for use in any application requiring fail-safe # performance, such as life-support or safety devices or # systems, Class III medical devices, nuclear facilities, # applications related to the deployment of airbags, or any # other applications that could lead to death, personal # injury, or severe property or environmental damage # (individually and collectively, "Critical # Applications"). Customer assumes the sole risk and # liability of any use of Xilinx products in Critical # Applications, subject only to applicable laws and # regulations governing limitations on product liability. # # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS # PART OF THIS FILE AT ALL TIMES. # ################################################################################ # Core Period Constraint. This constraint can be modified, and is # valid as long as it is met after place and route. create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ] set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ] create_clock -name "TS_CLKB" -period 20.0 [ get_ports clkb ] set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ] ################################################################################ ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:42:01 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v // Design : output_line_buffer // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "output_line_buffer,blk_mem_gen_v8_3_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) (* NotValidForBitStream *) module output_line_buffer (clka, ena, wea, addra, dina, clkb, addrb, doutb); (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [255:0]dina; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [11:0]addrb; (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [63:0]doutb; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_rsta_busy_UNCONNECTED; wire NLW_U0_rstb_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_dbiterr_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_sbiterr_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire [255:0]NLW_U0_douta_UNCONNECTED; wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED; wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; (* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 33.580152 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "output_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "4096" *) (* C_READ_WIDTH_A = "256" *) (* C_READ_WIDTH_B = "64" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "4096" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "256" *) (* C_WRITE_WIDTH_B = "64" *) (* C_XDEVICEFAMILY = "kintex7" *) (* downgradeipidentifiedwarnings = "yes" *) output_line_buffer_blk_mem_gen_v8_3_4 U0 (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .deepsleep(1'b0), .dina(dina), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(NLW_U0_douta_UNCONNECTED[255:0]), .doutb(doutb), .eccpipece(1'b0), .ena(ena), .enb(1'b0), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]), .regcea(1'b0), .regceb(1'b0), .rsta(1'b0), .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), .rstb(1'b0), .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), .s_aclk(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), .s_axi_injectdbiterr(1'b0), .s_axi_injectsbiterr(1'b0), .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb(1'b0), .s_axi_wvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .shutdown(1'b0), .sleep(1'b0), .wea(wea), .web(1'b0)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module output_line_buffer_blk_mem_gen_generic_cstr (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [63:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [255:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_width \ramloop[0].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[195:192],dina[131:128],dina[67:64],dina[3:0]}), .doutb(doutb[3:0]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[204:196],dina[140:132],dina[76:68],dina[12:4]}), .doutb(doutb[12:4]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[213:205],dina[149:141],dina[85:77],dina[21:13]}), .doutb(doutb[21:13]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[222:214],dina[158:150],dina[94:86],dina[30:22]}), .doutb(doutb[30:22]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[231:223],dina[167:159],dina[103:95],dina[39:31]}), .doutb(doutb[39:31]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[240:232],dina[176:168],dina[112:104],dina[48:40]}), .doutb(doutb[48:40]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[249:241],dina[185:177],dina[121:113],dina[57:49]}), .doutb(doutb[57:49]), .ena(ena), .wea(wea)); output_line_buffer_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina({dina[255:250],dina[191:186],dina[127:122],dina[63:58]}), .doutb(doutb[63:58]), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [3:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [15:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [15:0]dina; wire [3:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module output_line_buffer_blk_mem_gen_prim_width__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [5:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [23:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [23:0]dina; wire [5:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [3:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [15:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [15:0]dina; wire [3:0]doutb; wire ena; wire [0:0]wea; wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(4), .READ_WIDTH_B(4), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(18)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({addrb,1'b0,1'b0}), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DIADI(dina), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],doutb}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(ena), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized0 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized1 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized2 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized3 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized4 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized5 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [8:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [35:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [35:0]dina; wire [8:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({dina[35],dina[26],dina[17],dina[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module output_line_buffer_blk_mem_gen_prim_wrapper__parameterized6 (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [5:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [23:0]dina; input [0:0]wea; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [23:0]dina; wire [5:0]doutb; wire ena; wire [0:0]wea; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(9), .READ_WIDTH_B(9), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), .CLKARDCLK(clka), .CLKBWRCLK(clkb), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), .DIADI({1'b0,1'b0,dina[23:18],1'b0,1'b0,dina[17:12],1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena), .ENBWREN(1'b1), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), .WEA({wea,wea,wea,wea}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module output_line_buffer_blk_mem_gen_top (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [63:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [255:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_generic_cstr \valid.cstr (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) (* C_COUNT_36K_BRAM = "7" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) (* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 33.580152 mW" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "output_line_buffer.mem" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *) (* C_MEM_TYPE = "1" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "4096" *) (* C_READ_WIDTH_A = "256" *) (* C_READ_WIDTH_B = "64" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "4096" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "256" *) (* C_WRITE_WIDTH_B = "64" *) (* C_XDEVICEFAMILY = "kintex7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *) (* downgradeipidentifiedwarnings = "yes" *) module output_line_buffer_blk_mem_gen_v8_3_4 (clka, rsta, ena, regcea, wea, addra, dina, douta, clkb, rstb, enb, regceb, web, addrb, dinb, doutb, injectsbiterr, injectdbiterr, eccpipece, sbiterr, dbiterr, rdaddrecc, sleep, deepsleep, shutdown, rsta_busy, rstb_busy, s_aclk, s_aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, s_axi_injectsbiterr, s_axi_injectdbiterr, s_axi_sbiterr, s_axi_dbiterr, s_axi_rdaddrecc); input clka; input rsta; input ena; input regcea; input [0:0]wea; input [9:0]addra; input [255:0]dina; output [255:0]douta; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [11:0]addrb; input [63:0]dinb; output [63:0]doutb; input injectsbiterr; input injectdbiterr; input eccpipece; output sbiterr; output dbiterr; output [11:0]rdaddrecc; input sleep; input deepsleep; input shutdown; output rsta_busy; output rstb_busy; input s_aclk; input s_aresetn; input [3:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input s_axi_awvalid; output s_axi_awready; input [255:0]s_axi_wdata; input [0:0]s_axi_wstrb; input s_axi_wlast; input s_axi_wvalid; output s_axi_wready; output [3:0]s_axi_bid; output [1:0]s_axi_bresp; output s_axi_bvalid; input s_axi_bready; input [3:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input s_axi_arvalid; output s_axi_arready; output [3:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; input s_axi_rready; input s_axi_injectsbiterr; input s_axi_injectdbiterr; output s_axi_sbiterr; output s_axi_dbiterr; output [11:0]s_axi_rdaddrecc; wire \ ; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; assign dbiterr = \ ; assign douta[255] = \ ; assign douta[254] = \ ; assign douta[253] = \ ; assign douta[252] = \ ; assign douta[251] = \ ; assign douta[250] = \ ; assign douta[249] = \ ; assign douta[248] = \ ; assign douta[247] = \ ; assign douta[246] = \ ; assign douta[245] = \ ; assign douta[244] = \ ; assign douta[243] = \ ; assign douta[242] = \ ; assign douta[241] = \ ; assign douta[240] = \ ; assign douta[239] = \ ; assign douta[238] = \ ; assign douta[237] = \ ; assign douta[236] = \ ; assign douta[235] = \ ; assign douta[234] = \ ; assign douta[233] = \ ; assign douta[232] = \ ; assign douta[231] = \ ; assign douta[230] = \ ; assign douta[229] = \ ; assign douta[228] = \ ; assign douta[227] = \ ; assign douta[226] = \ ; assign douta[225] = \ ; assign douta[224] = \ ; assign douta[223] = \ ; assign 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assign douta[180] = \ ; assign douta[179] = \ ; assign douta[178] = \ ; assign douta[177] = \ ; assign douta[176] = \ ; assign douta[175] = \ ; assign douta[174] = \ ; assign douta[173] = \ ; assign douta[172] = \ ; assign douta[171] = \ ; assign douta[170] = \ ; assign douta[169] = \ ; assign douta[168] = \ ; assign douta[167] = \ ; assign douta[166] = \ ; assign douta[165] = \ ; assign douta[164] = \ ; assign douta[163] = \ ; assign douta[162] = \ ; assign douta[161] = \ ; assign douta[160] = \ ; assign douta[159] = \ ; assign douta[158] = \ ; assign douta[157] = \ ; assign douta[156] = \ ; assign douta[155] = \ ; assign douta[154] = \ ; assign douta[153] = \ ; assign douta[152] = \ ; assign douta[151] = \ ; assign douta[150] = \ ; assign douta[149] = \ ; assign douta[148] = \ ; assign douta[147] = \ ; assign douta[146] = \ ; assign douta[145] = \ ; assign douta[144] = \ ; assign douta[143] = \ ; assign douta[142] = \ ; assign douta[141] = \ ; assign douta[140] = \ ; assign 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assign douta[97] = \ ; assign douta[96] = \ ; assign douta[95] = \ ; assign douta[94] = \ ; assign douta[93] = \ ; assign douta[92] = \ ; assign douta[91] = \ ; assign douta[90] = \ ; assign douta[89] = \ ; assign douta[88] = \ ; assign douta[87] = \ ; assign douta[86] = \ ; assign douta[85] = \ ; assign douta[84] = \ ; assign douta[83] = \ ; assign douta[82] = \ ; assign douta[81] = \ ; assign douta[80] = \ ; assign douta[79] = \ ; assign douta[78] = \ ; assign douta[77] = \ ; assign douta[76] = \ ; assign douta[75] = \ ; assign douta[74] = \ ; assign douta[73] = \ ; assign douta[72] = \ ; assign douta[71] = \ ; assign douta[70] = \ ; assign douta[69] = \ ; assign douta[68] = \ ; assign douta[67] = \ ; assign douta[66] = \ ; assign douta[65] = \ ; assign douta[64] = \ ; assign douta[63] = \ ; assign douta[62] = \ ; assign douta[61] = \ ; assign douta[60] = \ ; assign douta[59] = \ ; assign douta[58] = \ ; assign douta[57] = \ ; assign douta[56] = \ ; assign douta[55] = \ ; assign douta[54] = \ ; assign douta[53] = \ ; assign douta[52] = \ ; assign douta[51] = \ ; assign douta[50] = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign rdaddrecc[11] = \ ; assign rdaddrecc[10] = \ ; assign rdaddrecc[9] = \ ; assign rdaddrecc[8] = \ ; assign rdaddrecc[7] = \ ; assign rdaddrecc[6] = \ ; assign rdaddrecc[5] = \ ; assign rdaddrecc[4] = \ ; assign rdaddrecc[3] = \ ; assign rdaddrecc[2] = \ ; assign rdaddrecc[1] = \ ; assign rdaddrecc[0] = \ ; assign rsta_busy = \ ; assign rstb_busy = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[3] = \ ; assign s_axi_bid[2] = \ ; assign s_axi_bid[1] = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_dbiterr = \ ; assign s_axi_rdaddrecc[11] = \ ; assign s_axi_rdaddrecc[10] = \ ; assign s_axi_rdaddrecc[9] = \ ; assign s_axi_rdaddrecc[8] = \ ; assign s_axi_rdaddrecc[7] = \ ; assign s_axi_rdaddrecc[6] = \ ; assign s_axi_rdaddrecc[5] = \ ; assign s_axi_rdaddrecc[4] = \ ; assign s_axi_rdaddrecc[3] = \ ; assign s_axi_rdaddrecc[2] = \ ; assign s_axi_rdaddrecc[1] = \ ; assign s_axi_rdaddrecc[0] = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[3] = \ ; assign s_axi_rid[2] = \ ; assign s_axi_rid[1] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_sbiterr = \ ; assign s_axi_wready = \ ; assign sbiterr = \ ; GND GND (.G(\ )); output_line_buffer_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *) module output_line_buffer_blk_mem_gen_v8_3_4_synth (doutb, clka, clkb, ena, addra, addrb, dina, wea); output [63:0]doutb; input clka; input clkb; input ena; input [9:0]addra; input [11:0]addrb; input [255:0]dina; input [0:0]wea; wire [9:0]addra; wire [11:0]addrb; wire clka; wire clkb; wire [255:0]dina; wire [63:0]doutb; wire ena; wire [0:0]wea; output_line_buffer_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.addra(addra), .addrb(addrb), .clka(clka), .clkb(clkb), .dina(dina), .doutb(doutb), .ena(ena), .wea(wea)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v ================================================ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 // Date : Tue Nov 15 09:42:01 2016 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v // Design : output_line_buffer // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *) module output_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb) /* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[255:0],clkb,addrb[11:0],doutb[63:0]" */; input clka; input ena; input [0:0]wea; input [9:0]addra; input [255:0]dina; input clkb; input [11:0]addrb; output [63:0]doutb; endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/sim/output_line_buffer.v ================================================ // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 // IP Revision: 4 `timescale 1ns/1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module output_line_buffer ( clka, ena, wea, addra, dina, clkb, addrb, doutb ); (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input wire clka; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input wire ena; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input wire [0 : 0] wea; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input wire [9 : 0] addra; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input wire [255 : 0] dina; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input wire clkb; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input wire [11 : 0] addrb; (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output wire [63 : 0] doutb; blk_mem_gen_v8_3_4 #( .C_FAMILY("kintex7"), .C_XDEVICEFAMILY("kintex7"), .C_ELABORATION_DIR("./"), .C_INTERFACE_TYPE(0), .C_AXI_TYPE(1), .C_AXI_SLAVE_TYPE(0), .C_USE_BRAM_BLOCK(0), .C_ENABLE_32BIT_ADDRESS(0), .C_CTRL_ECC_ALGO("NONE"), .C_HAS_AXI_ID(0), .C_AXI_ID_WIDTH(4), .C_MEM_TYPE(1), .C_BYTE_SIZE(9), .C_ALGORITHM(1), .C_PRIM_TYPE(1), .C_LOAD_INIT_FILE(0), .C_INIT_FILE_NAME("no_coe_file_loaded"), .C_INIT_FILE("output_line_buffer.mem"), .C_USE_DEFAULT_DATA(0), .C_DEFAULT_DATA("0"), .C_HAS_RSTA(0), .C_RST_PRIORITY_A("CE"), .C_RSTRAM_A(0), .C_INITA_VAL("0"), .C_HAS_ENA(1), .C_HAS_REGCEA(0), .C_USE_BYTE_WEA(0), .C_WEA_WIDTH(1), .C_WRITE_MODE_A("NO_CHANGE"), .C_WRITE_WIDTH_A(256), .C_READ_WIDTH_A(256), .C_WRITE_DEPTH_A(1024), .C_READ_DEPTH_A(1024), .C_ADDRA_WIDTH(10), .C_HAS_RSTB(0), .C_RST_PRIORITY_B("CE"), .C_RSTRAM_B(0), .C_INITB_VAL("0"), .C_HAS_ENB(0), .C_HAS_REGCEB(0), .C_USE_BYTE_WEB(0), .C_WEB_WIDTH(1), .C_WRITE_MODE_B("WRITE_FIRST"), .C_WRITE_WIDTH_B(64), .C_READ_WIDTH_B(64), .C_WRITE_DEPTH_B(4096), .C_READ_DEPTH_B(4096), .C_ADDRB_WIDTH(12), .C_HAS_MEM_OUTPUT_REGS_A(0), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_MUX_PIPELINE_STAGES(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_USE_SOFTECC(0), .C_USE_ECC(0), .C_EN_ECC_PIPE(0), .C_HAS_INJECTERR(0), .C_SIM_COLLISION_CHECK("ALL"), .C_COMMON_CLK(0), .C_DISABLE_WARN_BHV_COLL(0), .C_EN_SLEEP_PIN(0), .C_USE_URAM(0), .C_EN_RDADDRA_CHG(0), .C_EN_RDADDRB_CHG(0), .C_EN_DEEPSLEEP_PIN(0), .C_EN_SHUTDOWN_PIN(0), .C_EN_SAFETY_CKT(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_COUNT_36K_BRAM("7"), .C_COUNT_18K_BRAM("1"), .C_EST_POWER_SUMMARY("Estimated Power for IP : 33.580152 mW") ) inst ( .clka(clka), .rsta(1'D0), .ena(ena), .regcea(1'D0), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clkb), .rstb(1'D0), .enb(1'D0), .regceb(1'D0), .web(1'B0), .addrb(addrb), .dinb(64'B0), .doutb(doutb), .injectsbiterr(1'D0), .injectdbiterr(1'D0), .eccpipece(1'D0), .sbiterr(), .dbiterr(), .rdaddrecc(), .sleep(1'D0), .deepsleep(1'D0), .shutdown(1'D0), .rsta_busy(), .rstb_busy(), .s_aclk(1'H0), .s_aresetn(1'D0), .s_axi_awid(4'B0), .s_axi_awaddr(32'B0), .s_axi_awlen(8'B0), .s_axi_awsize(3'B0), .s_axi_awburst(2'B0), .s_axi_awvalid(1'D0), .s_axi_awready(), .s_axi_wdata(256'B0), .s_axi_wstrb(1'B0), .s_axi_wlast(1'D0), .s_axi_wvalid(1'D0), .s_axi_wready(), .s_axi_bid(), .s_axi_bresp(), .s_axi_bvalid(), .s_axi_bready(1'D0), .s_axi_arid(4'B0), .s_axi_araddr(32'B0), .s_axi_arlen(8'B0), .s_axi_arsize(3'B0), .s_axi_arburst(2'B0), .s_axi_arvalid(1'D0), .s_axi_arready(), .s_axi_rid(), .s_axi_rdata(), .s_axi_rresp(), .s_axi_rlast(), .s_axi_rvalid(), .s_axi_rready(1'D0), .s_axi_injectsbiterr(1'D0), .s_axi_injectdbiterr(1'D0), .s_axi_sbiterr(), .s_axi_dbiterr(), .s_axi_rdaddrecc() ); endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/simulation/blk_mem_gen_v8_3.v ================================================ /****************************************************************************** -- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ***************************************************************************** * * Filename: blk_mem_gen_v8_3_4.v * * Description: * This file is the Verilog behvarial model for the * Block Memory Generator Core. * ***************************************************************************** * Author: Xilinx * * History: Jan 11, 2006 Initial revision * Jun 11, 2007 Added independent register stages for * Port A and Port B (IP1_Jm/v2.5) * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) * Mar 13, 2008 Behavioral model optimizations * April 07, 2009 : Added support for Spartan-6 and Virtex-6 * features, including the following: * (i) error injection, detection and/or correction * (ii) reset priority * (iii) special reset behavior * *****************************************************************************/ `timescale 1ps/1ps module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5); parameter INIT = 64'h0000000000000000; input I0, I1, I2, I3, I4, I5; output O; reg O; reg tmp; always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; if ( tmp == 0 || tmp == 1) O = INIT[{I5, I4, I3, I2, I1, I0}]; end endmodule module beh_vlog_muxf7_v8_3 (O, I0, I1, S); output O; reg O; input I0, I1, S; always @(I0 or I1 or S) if (S) O = I1; else O = I0; endmodule module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q<= 1'b0; else Q<= #FLOP_DELAY D; endmodule module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, D, PRE; reg Q; initial Q= 1'b0; always @(posedge C ) if (PRE) Q <= 1'b1; else Q <= #FLOP_DELAY D; endmodule module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CE, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q <= 1'b0; else if (CE) Q <= #FLOP_DELAY D; endmodule module write_netlist_v8_3 #( parameter C_AXI_TYPE = 0 ) ( S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c ); input S_ACLK; input S_ARESETN; input S_AXI_AWVALID; input S_AXI_WVALID; input S_AXI_BREADY; input w_last_c; input bready_timeout_c; output aw_ready_r; output S_AXI_WREADY; output S_AXI_BVALID; output S_AXI_WR_EN; output addr_en_c; output incr_addr_c; output bvalid_c; //------------------------------------------------------------------------- //AXI LITE //------------------------------------------------------------------------- generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm wire w_ready_r_7; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSignal_bvalid_c; wire NlwRenamedSignal_incr_addr_c; wire present_state_FSM_FFd3_13; wire present_state_FSM_FFd2_14; wire present_state_FSM_FFd1_15; wire present_state_FSM_FFd4_16; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd4_In1_21; wire [0:0] Mmux_aw_ready_c ; begin assign S_AXI_WREADY = w_ready_r_7, S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, incr_addr_c = NlwRenamedSignal_incr_addr_c, bvalid_c = NlwRenamedSignal_bvalid_c; assign NlwRenamedSignal_incr_addr_c = 1'b0; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_7) ); beh_vlog_ff_pre_v8_3 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_16) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_13) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_15) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000055554440)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000088880800)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( S_AXI_WVALID), .I2 ( bready_timeout_c), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000AAAA2000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_WVALID), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( addr_en_c) ); STATE_LOGIC_v8_3 #( .INIT (64'hF5F07570F5F05500)) Mmux_w_ready_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( w_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd3_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd1_15), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_14), .I2 ( present_state_FSM_FFd3_13), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSignal_bvalid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h2F0F27072F0F2200)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( present_state_FSM_FFd4_In1_21) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_In1_21), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h7535753575305500)) Mmux_aw_ready_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_WVALID), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 ( present_state_FSM_FFd2_14), .O ( Mmux_aw_ready_c[0]) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000F8)) Mmux_aw_ready_c_0_2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( Mmux_aw_ready_c[0]), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( aw_ready_c) ); end end endgenerate //--------------------------------------------------------------------- // AXI FULL //--------------------------------------------------------------------- generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm wire w_ready_r_8; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSig_OI_bvalid_c; wire present_state_FSM_FFd1_16; wire present_state_FSM_FFd4_17; wire present_state_FSM_FFd3_18; wire present_state_FSM_FFd2_19; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd2_In1_24; wire present_state_FSM_FFd4_In1_25; wire N2; wire N4; begin assign S_AXI_WREADY = w_ready_r_8, bvalid_c = NlwRenamedSig_OI_bvalid_c, S_AXI_BVALID = 1'b0; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_8) ); beh_vlog_ff_pre_v8_3 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_17) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_18) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_19) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_16) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000005540)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd4_17), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_3 #( .INIT (64'hBF3FBB33AF0FAA00)) Mmux_aw_ready_c_0_2 ( .I0 ( S_AXI_BREADY), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd1_16), .I4 ( present_state_FSM_FFd4_17), .I5 ( NlwRenamedSig_OI_bvalid_c), .O ( aw_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'hAAAAAAAA20000000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( S_AXI_WVALID), .I4 ( w_last_c), .I5 ( present_state_FSM_FFd4_17), .O ( addr_en_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_19), .I2 ( present_state_FSM_FFd3_18), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( S_AXI_WR_EN) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000002220)) Mmux_incr_addr_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( incr_addr_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000008880)) Mmux_aw_ready_c_0_11 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSig_OI_bvalid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000000000D5C0)) present_state_FSM_FFd2_In1 ( .I0 ( w_last_c), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd4_17), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd2_In1_24) ); STATE_LOGIC_v8_3 #( .INIT (64'hFFFFAAAA08AAAAAA)) present_state_FSM_FFd2_In2 ( .I0 ( present_state_FSM_FFd2_19), .I1 ( S_AXI_AWVALID), .I2 ( bready_timeout_c), .I3 ( w_last_c), .I4 ( S_AXI_WVALID), .I5 ( present_state_FSM_FFd2_In1_24), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h00C0004000C00000)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( w_last_c), .I2 ( S_AXI_WVALID), .I3 ( bready_timeout_c), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( present_state_FSM_FFd4_In1_25) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000FFFF88F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_16), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_17), .I3 ( S_AXI_AWVALID), .I4 ( present_state_FSM_FFd4_In1_25), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000007)) Mmux_w_ready_c_0_SW0 ( .I0 ( w_last_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N2) ); STATE_LOGIC_v8_3 #( .INIT (64'hFABAFABAFAAAF000)) Mmux_w_ready_c_0_Q ( .I0 ( N2), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd4_17), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( w_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000008)) Mmux_aw_ready_c_0_11_SW0 ( .I0 ( bready_timeout_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N4) ); STATE_LOGIC_v8_3 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( w_last_c), .I1 ( N4), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 ( present_state_FSM_FFd1_16), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); end end endgenerate endmodule module read_netlist_v8_3 #( parameter C_AXI_TYPE = 1, parameter C_ADDRB_WIDTH = 12 ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); input S_AXI_R_LAST_INT; input S_ACLK; input S_ARESETN; input S_AXI_ARVALID; input S_AXI_RREADY; output S_AXI_INCR_ADDR; output S_AXI_ADDR_EN; output S_AXI_SINGLE_TRANS; output S_AXI_MUX_SEL; output S_AXI_R_LAST; output S_AXI_ARREADY; output S_AXI_RLAST; output S_AXI_RVALID; output S_AXI_RD_EN; input [7:0] S_AXI_ARLEN; wire present_state_FSM_FFd1_13 ; wire present_state_FSM_FFd2_14 ; wire gaxi_full_sm_outstanding_read_r_15 ; wire gaxi_full_sm_ar_ready_r_16 ; wire gaxi_full_sm_r_last_r_17 ; wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; wire gaxi_full_sm_r_valid_c ; wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; wire gaxi_full_sm_ar_ready_c ; wire gaxi_full_sm_outstanding_read_c ; wire NlwRenamedSig_OI_S_AXI_R_LAST ; wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; wire present_state_FSM_FFd2_In ; wire present_state_FSM_FFd1_In ; wire Mmux_S_AXI_R_LAST13 ; wire N01 ; wire N2 ; wire Mmux_gaxi_full_sm_ar_ready_c11 ; wire N4 ; wire N8 ; wire N9 ; wire N10 ; wire N11 ; wire N12 ; wire N13 ; assign S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, S_AXI_RLAST = gaxi_full_sm_r_last_r_17, S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_outstanding_read_r ( .C (S_ACLK), .CLR(S_ARESETN), .D(gaxi_full_sm_outstanding_read_c), .Q(gaxi_full_sm_outstanding_read_r_15) ); beh_vlog_ff_ce_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_r_valid_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (gaxi_full_sm_r_valid_c), .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) gaxi_full_sm_ar_ready_r ( .C (S_ACLK), .CLR (S_ARESETN), .D (gaxi_full_sm_ar_ready_c), .Q (gaxi_full_sm_ar_ready_r_16) ); beh_vlog_ff_ce_clr_v8_3 #( .INIT(1'b0)) gaxi_full_sm_r_last_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (NlwRenamedSig_OI_S_AXI_R_LAST), .Q (gaxi_full_sm_r_last_r_17) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_3 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C (S_ACLK), .CLR (S_ARESETN), .D (present_state_FSM_FFd1_In), .Q (present_state_FSM_FFd1_13) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000000000000B)) S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( .I0 ( S_AXI_RREADY), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000008)) Mmux_S_AXI_SINGLE_TRANS11 ( .I0 (S_AXI_ARVALID), .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_SINGLE_TRANS) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000004)) Mmux_S_AXI_ADDR_EN11 ( .I0 (present_state_FSM_FFd1_13), .I1 (S_AXI_ARVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_ADDR_EN) ); STATE_LOGIC_v8_3 #( .INIT (64'hECEE2022EEEE2022)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_ARVALID), .I1 ( present_state_FSM_FFd1_13), .I2 ( S_AXI_RREADY), .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I4 ( present_state_FSM_FFd2_14), .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000044440444)) Mmux_S_AXI_R_LAST131 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_RREADY), .I5 (1'b0), .O ( Mmux_S_AXI_R_LAST13) ); STATE_LOGIC_v8_3 #( .INIT (64'h4000FFFF40004000)) Mmux_S_AXI_INCR_ADDR11 ( .I0 ( S_AXI_R_LAST_INT), .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( Mmux_S_AXI_R_LAST13), .O ( S_AXI_INCR_ADDR) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000FE)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( .I0 ( S_AXI_ARLEN[2]), .I1 ( S_AXI_ARLEN[1]), .I2 ( S_AXI_ARLEN[0]), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N01) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000001)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( .I0 ( S_AXI_ARLEN[7]), .I1 ( S_AXI_ARLEN[6]), .I2 ( S_AXI_ARLEN[5]), .I3 ( S_AXI_ARLEN[4]), .I4 ( S_AXI_ARLEN[3]), .I5 ( N01), .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000000007)) Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 ( 1'b0), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N2) ); STATE_LOGIC_v8_3 #( .INIT (64'h0020000002200200)) Mmux_gaxi_full_sm_outstanding_read_c1 ( .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd1_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( gaxi_full_sm_outstanding_read_r_15), .I5 ( N2), .O ( gaxi_full_sm_outstanding_read_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000000004555)) Mmux_gaxi_full_sm_ar_ready_c12 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( 1'b0), .I5 ( 1'b0), .O ( Mmux_gaxi_full_sm_ar_ready_c11) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000000000EF)) Mmux_S_AXI_R_LAST11_SW0 ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N4) ); STATE_LOGIC_v8_3 #( .INIT (64'hFCAAFC0A00AA000A)) Mmux_S_AXI_R_LAST11 ( .I0 ( S_AXI_ARVALID), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( N4), .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .O ( gaxi_full_sm_r_valid_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000AAAAAA08)) S_AXI_MUX_SEL1 ( .I0 (present_state_FSM_FFd1_13), .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (S_AXI_RREADY), .I3 (present_state_FSM_FFd2_14), .I4 (gaxi_full_sm_outstanding_read_r_15), .I5 (1'b0), .O (S_AXI_MUX_SEL) ); STATE_LOGIC_v8_3 #( .INIT (64'hF3F3F755A2A2A200)) Mmux_S_AXI_RD_EN11 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 ( S_AXI_RREADY), .I3 ( gaxi_full_sm_outstanding_read_r_15), .I4 ( present_state_FSM_FFd2_14), .I5 ( S_AXI_ARVALID), .O ( S_AXI_RD_EN) ); beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 ( .I0 ( N8), .I1 ( N9), .S ( present_state_FSM_FFd1_13), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000005410F4F0)) present_state_FSM_FFd1_In3_F ( .I0 ( S_AXI_RREADY), .I1 ( present_state_FSM_FFd2_14), .I2 ( S_AXI_ARVALID), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( 1'b0), .O ( N8) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000072FF7272)) present_state_FSM_FFd1_In3_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N9) ); beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 ( .I0 ( N10), .I1 ( N11), .S ( present_state_FSM_FFd1_13), .O ( gaxi_full_sm_ar_ready_c) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000FFFF88A8)) Mmux_gaxi_full_sm_ar_ready_c14_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), .I5 ( 1'b0), .O ( N10) ); STATE_LOGIC_v8_3 #( .INIT (64'h000000008D008D8D)) Mmux_gaxi_full_sm_ar_ready_c14_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N11) ); beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 ( .I0 ( N12), .I1 ( N13), .S ( present_state_FSM_FFd1_13), .O ( NlwRenamedSig_OI_S_AXI_R_LAST) ); STATE_LOGIC_v8_3 #( .INIT (64'h0000000088088888)) Mmux_S_AXI_R_LAST1_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N12) ); STATE_LOGIC_v8_3 #( .INIT (64'h00000000E400E4E4)) Mmux_S_AXI_R_LAST1_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( S_AXI_R_LAST_INT), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N13) ); endmodule module blk_mem_axi_write_wrapper_beh_v8_3 # ( // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; parameter C_WRITE_DEPTH_A = 0, parameter C_AXI_AWADDR_WIDTH = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_WDATA_WIDTH = 32, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, // AXI OUTSTANDING WRITES parameter C_AXI_OS_WR = 2 ) ( // AXI Global Signals input S_ACLK, input S_ARESETN, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, input [8-1:0] S_AXI_AWLEN, input [2:0] S_AXI_AWSIZE, input [1:0] S_AXI_AWBURST, input S_AXI_AWVALID, output S_AXI_AWREADY, input S_AXI_WVALID, output S_AXI_WREADY, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, output S_AXI_BVALID, input S_AXI_BREADY, // Signals for BMG interface output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, output S_AXI_WR_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: ((C_AXI_WDATA_WIDTH==16)?1: ((C_AXI_WDATA_WIDTH==32)?2: ((C_AXI_WDATA_WIDTH==64)?3: ((C_AXI_WDATA_WIDTH==128)?4: ((C_AXI_WDATA_WIDTH==256)?5:0)))))); wire bvalid_c ; reg bready_timeout_c = 0; wire [1:0] bvalid_rd_cnt_c; reg bvalid_r = 0; reg [2:0] bvalid_count_r = 0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; reg [1:0] bvalid_wr_cnt_r = 0; reg [1:0] bvalid_rd_cnt_r = 0; wire w_last_c ; wire addr_en_c ; wire incr_addr_c ; wire aw_ready_r ; wire dec_alen_c ; reg bvalid_d1_c = 0; reg [7:0] awlen_cntr_r = 0; reg [7:0] awlen_int = 0; reg [1:0] awburst_int = 0; integer total_bytes = 0; integer wrap_boundary = 0; integer wrap_base_addr = 0; integer num_of_bytes_c = 0; integer num_of_bytes_r = 0; // Array to store BIDs reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; wire S_AXI_BVALID_axi_wr_fsm; //------------------------------------- //AXI WRITE FSM COMPONENT INSTANTIATION //------------------------------------- write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm ( .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), .S_AXI_AWVALID(S_AXI_AWVALID), .aw_ready_r(aw_ready_r), .S_AXI_WVALID(S_AXI_WVALID), .S_AXI_WREADY(S_AXI_WREADY), .S_AXI_BREADY(S_AXI_BREADY), .S_AXI_WR_EN(S_AXI_WR_EN), .w_last_c(w_last_c), .bready_timeout_c(bready_timeout_c), .addr_en_c(addr_en_c), .incr_addr_c(incr_addr_c), .bvalid_c(bvalid_c), .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) ); //Wrap Address boundary calculation always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); total_bytes = (num_of_bytes_r)*(awlen_int+1); wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); wrap_boundary = wrap_base_addr+total_bytes; end //------------------------------------------------------------------------- // BMG address generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awaddr_reg <= 0; num_of_bytes_r <= 0; awburst_int <= 0; end else begin if (addr_en_c == 1'b1) begin awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; num_of_bytes_r <= num_of_bytes_c; awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); end else if (incr_addr_c == 1'b1) begin if (awburst_int == 2'b10) begin if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin awaddr_reg <= wrap_base_addr; end else begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end end end assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); //------------------------------------------------------------------------- // AXI wlast generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awlen_cntr_r <= 0; awlen_int <= 0; end else begin if (addr_en_c == 1'b1) begin awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; end else if (dec_alen_c == 1'b1) begin awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; end end end assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; assign dec_alen_c = (incr_addr_c | w_last_c); //------------------------------------------------------------------------- // Generation of bvalid counter for outstanding transactions //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_count_r <= 0; end else begin // bvalid_count_r generation if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; end else if (bvalid_c == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; end end end //------------------------------------------------------------------------- // Generation of bvalid when BID is used //------------------------------------------------------------------------- generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; bvalid_d1_c <= 0; end else begin // Delay the generation o bvalid_r for generation for BID bvalid_d1_c <= bvalid_c; //external bvalid signal generation if (bvalid_d1_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of bvalid when BID is not used //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; end else begin //external bvalid signal generation if (bvalid_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of Bready timeout //------------------------------------------------------------------------- always @(bvalid_count_r) begin // bready_timeout_c generation if(bvalid_count_r == C_AXI_OS_WR-1) begin bready_timeout_c <= 1'b1; end else begin bready_timeout_c <= 1'b0; end end //------------------------------------------------------------------------- // Generation of BID //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_wr_cnt_r <= 0; bvalid_rd_cnt_r <= 0; end else begin // STORE AWID IN AN ARRAY if(bvalid_c == 1'b1) begin bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; end // generate BID FROM AWID ARRAY bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; end end assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; //------------------------------------------------------------------------- // Storing AWID for generation of BID //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if(S_ARESETN == 1'b1) begin axi_bid_array[0] = 0; axi_bid_array[1] = 0; axi_bid_array[2] = 0; axi_bid_array[3] = 0; end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; end end end endgenerate assign S_AXI_BVALID = bvalid_r; assign S_AXI_AWREADY = aw_ready_r; endmodule module blk_mem_axi_read_wrapper_beh_v8_3 # ( //// AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_MEMORY_TYPE = 0, parameter C_WRITE_WIDTH_A = 4, parameter C_WRITE_DEPTH_A = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_PIPELINE_STAGES = 0, parameter C_AXI_ARADDR_WIDTH = 12, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_ADDRB_WIDTH = 12 ) ( //// AXI Global Signals input S_ACLK, input S_ARESETN, //// AXI Full/Lite Slave Read (Read side) input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, input [7:0] S_AXI_ARLEN, input [2:0] S_AXI_ARSIZE, input [1:0] S_AXI_ARBURST, input S_AXI_ARVALID, output S_AXI_ARREADY, output S_AXI_RLAST, output S_AXI_RVALID, input S_AXI_RREADY, input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, //// AXI Full/Lite Read Address Signals to BRAM output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, output S_AXI_RD_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: ((C_WRITE_WIDTH_A==16)?1: ((C_WRITE_WIDTH_A==32)?2: ((C_WRITE_WIDTH_A==64)?3: ((C_WRITE_WIDTH_A==128)?4: ((C_WRITE_WIDTH_A==256)?5:0)))))); reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; wire addr_en_c; wire rd_en_c; wire incr_addr_c; wire single_trans_c; wire dec_alen_c; wire mux_sel_c; wire r_last_c; wire r_last_int_c; wire [C_ADDRB_WIDTH-1 : 0] araddr_out; reg [7:0] arlen_int_r=0; reg [7:0] arlen_cntr=8'h01; reg [1:0] arburst_int_c=0; reg [1:0] arburst_int_r=0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; integer num_of_bytes_c = 0; integer total_bytes = 0; integer num_of_bytes_r = 0; integer wrap_base_addr_r = 0; integer wrap_boundary_r = 0; reg [7:0] arlen_int_c=0; integer total_bytes_c = 0; integer wrap_base_addr_c = 0; integer wrap_boundary_c = 0; assign dec_alen_c = incr_addr_c | r_last_int_c; read_netlist_v8_3 #(.C_AXI_TYPE (1), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_read_fsm ( .S_AXI_INCR_ADDR(incr_addr_c), .S_AXI_ADDR_EN(addr_en_c), .S_AXI_SINGLE_TRANS(single_trans_c), .S_AXI_MUX_SEL(mux_sel_c), .S_AXI_R_LAST(r_last_c), .S_AXI_R_LAST_INT(r_last_int_c), //// AXI Global Signals .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), //// AXI Full/Lite Slave Read (Read side) .S_AXI_ARLEN(S_AXI_ARLEN), .S_AXI_ARVALID(S_AXI_ARVALID), .S_AXI_ARREADY(S_AXI_ARREADY), .S_AXI_RLAST(S_AXI_RLAST), .S_AXI_RVALID(S_AXI_RVALID), .S_AXI_RREADY(S_AXI_RREADY), //// AXI Full/Lite Read Address Signals to BRAM .S_AXI_RD_EN(rd_en_c) ); always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); total_bytes = (num_of_bytes_r)*(arlen_int_r+1); wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); wrap_boundary_r = wrap_base_addr_r+total_bytes; //////// combinatorial from interface arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); wrap_boundary_c = wrap_base_addr_c+total_bytes_c; arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); end ////------------------------------------------------------------------------- //// BMG address generation ////------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin araddr_reg <= 0; arburst_int_r <= 0; num_of_bytes_r <= 0; end else begin if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin arburst_int_r <= arburst_int_c; num_of_bytes_r <= num_of_bytes_c; if (arburst_int_c == 2'b10) begin if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin araddr_reg <= wrap_base_addr_c; end else begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (addr_en_c == 1'b1) begin araddr_reg <= S_AXI_ARADDR; num_of_bytes_r <= num_of_bytes_c; arburst_int_r <= arburst_int_c; end else if (incr_addr_c == 1'b1) begin if (arburst_int_r == 2'b10) begin if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin araddr_reg <= wrap_base_addr_r; end else begin araddr_reg <= araddr_reg + num_of_bytes_r; end end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin araddr_reg <= araddr_reg + num_of_bytes_r; end end end end assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); ////----------------------------------------------------------------------- //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM ////----------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin arlen_cntr <= 8'h01; arlen_int_r <= 0; end else begin if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= S_AXI_ARLEN - 1'b1; end else if (addr_en_c == 1'b1) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; end else if (dec_alen_c == 1'b1) begin arlen_cntr <= arlen_cntr - 1'b1 ; end else begin arlen_cntr <= arlen_cntr; end end end assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; ////------------------------------------------------------------------------ //// AXI FULL FSM //// Mux Selection of ARADDR //// ARADDR is driven out from the read fsm based on the mux_sel_c //// Based on mux_sel either ARADDR is given out or the latched ARADDR is //// given out to BRAM ////------------------------------------------------------------------------ assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; ////------------------------------------------------------------------------ //// Assign output signals - AXI FULL FSM ////------------------------------------------------------------------------ assign S_AXI_RD_EN = rd_en_c; generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin S_AXI_RID <= 0; ar_id_r <= 0; end else begin if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin S_AXI_RID <= S_AXI_ARID; ar_id_r <= S_AXI_ARID; end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin ar_id_r <= S_AXI_ARID; end else if (rd_en_c == 1'b1) begin S_AXI_RID <= ar_id_r; end end end end endgenerate endmodule module blk_mem_axi_regs_fwd_v8_3 #(parameter C_DATA_WIDTH = 8 )( input ACLK, input ARESET, input S_VALID, output S_READY, input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, output M_VALID, input M_READY, output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA ); reg [C_DATA_WIDTH-1:0] STORAGE_DATA; wire S_READY_I; reg M_VALID_I; reg [1:0] ARESET_D; //assign local signal to its output signal assign S_READY = S_READY_I; assign M_VALID = M_VALID_I; always @(posedge ACLK) begin ARESET_D <= {ARESET_D[0], ARESET}; end //Save payload data whenever we have a transaction on the slave side always @(posedge ACLK or ARESET) begin if (ARESET == 1'b1) begin STORAGE_DATA <= 0; end else begin if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin STORAGE_DATA <= S_PAYLOAD_DATA; end end end always @(posedge ACLK) begin M_PAYLOAD_DATA = STORAGE_DATA; end //M_Valid set to high when we have a completed transfer on slave side //Is removed on a M_READY except if we have a new transfer on the slave side always @(posedge ACLK or ARESET_D) begin if (ARESET_D != 2'b00) begin M_VALID_I <= 1'b0; end else begin if (S_VALID == 1'b1) begin //Always set M_VALID_I when slave side is valid M_VALID_I <= 1'b1; end else if (M_READY == 1'b1 ) begin //Clear (or keep) when no slave side is valid but master side is ready M_VALID_I <= 1'b0; end end end //Slave Ready is either when Master side drives M_READY or we have space in our storage data assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); endmodule //***************************************************************************** // Output Register Stage module // // This module builds the output register stages of the memory. This module is // instantiated in the main memory module (blk_mem_gen_v8_3_4) which is // declared/implemented further down in this file. //***************************************************************************** module blk_mem_gen_v8_3_4_output_stage #(parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RST = 0, parameter C_RSTRAM = 0, parameter C_RST_PRIORITY = "CE", parameter C_INIT_VAL = "0", parameter C_HAS_EN = 0, parameter C_HAS_REGCE = 0, parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_MEM_OUTPUT_REGS = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter NUM_STAGES = 1, parameter C_EN_ECC_PIPE = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input RST, input EN, input REGCE, input [C_DATA_WIDTH-1:0] DIN_I, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN_I, input DBITERR_IN_I, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, input ECCPIPECE, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RST : Determines the presence of the RST port // C_RSTRAM : Determines if special reset behavior is used // C_RST_PRIORITY : Determines the priority between CE and SR // C_INIT_VAL : Initialization value // C_HAS_EN : Determines the presence of the EN port // C_HAS_REGCE : Determines the presence of the REGCE port // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // NUM_STAGES : Determines the number of output stages // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // RST : Reset input to reset memory outputs to a user-defined // reset state // EN : Enable all read and write operations // REGCE : Register Clock Enable to control each pipeline output // register stages // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// // Fix for CR-509792 localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; // Declare the pipeline registers // (includes mem output reg, mux pipeline stages, and mux output reg) reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; reg [REG_STAGES-1:0] sbiterr_regs; reg [REG_STAGES-1:0] dbiterr_regs; reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; reg [C_DATA_WIDTH-1:0] init_val ; //********************************************* // Wire off optional inputs based on parameters //********************************************* wire en_i; wire regce_i; wire rst_i; // Internal signals reg [C_DATA_WIDTH-1:0] DIN; reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; reg SBITERR_IN; reg DBITERR_IN; // Internal enable for output registers is tied to user EN or '1' depending // on parameters assign en_i = (C_HAS_EN==0 || EN); // Internal register enable for output registers is tied to user REGCE, EN or // '1' depending on parameters // For V4 ECC, REGCE is always 1 // Virtex-4 ECC Not Yet Supported assign regce_i = ((C_HAS_REGCE==1) && REGCE) || ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); //Internal SRR is tied to user RST or '0' depending on parameters assign rst_i = (C_HAS_RST==1) && RST; //**************************************************** // Power on: load up the output registers and latches //**************************************************** initial begin if (!($sscanf(init_str, "%h", init_val))) begin init_val = 0; end DOUT = init_val; RDADDRECC = 0; SBITERR = 1'b0; DBITERR = 1'b0; DIN = {(C_DATA_WIDTH){1'b0}}; RDADDRECC_IN = 0; SBITERR_IN = 0; DBITERR_IN = 0; // This will be one wider than need, but 0 is an error out_regs = {(REG_STAGES+1){init_val}}; rdaddrecc_regs = 0; sbiterr_regs = {(REG_STAGES+1){1'b0}}; dbiterr_regs = {(REG_STAGES+1){1'b0}}; end //*********************************************** // NUM_STAGES = 0 (No output registers. RAM only) //*********************************************** generate if (NUM_STAGES == 0) begin : zero_stages always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg always @* begin DIN = DIN_I; SBITERR_IN = SBITERR_IN_I; DBITERR_IN = DBITERR_IN_I; RDADDRECC_IN = RDADDRECC_IN_I; end end endgenerate generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg always @(posedge CLK) begin if(ECCPIPECE == 1) begin DIN <= #FLOP_DELAY DIN_I; SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; end end end endgenerate //*********************************************** // NUM_STAGES = 1 // (Mem Output Reg only or Mux Output Reg only) //*********************************************** // Possible valid combinations: // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) // +-----------------------------------------+ // | C_RSTRAM_* | Reset Behavior | // +----------------+------------------------+ // | 0 | Normal Behavior | // +----------------+------------------------+ // | 1 | Special Behavior | // +----------------+------------------------+ // // Normal = REGCE gates reset, as in the case of all families except S3ADSP. // Special = EN gates reset, as in the case of S3ADSP. generate if (NUM_STAGES == 1 && (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) begin : one_stages_norm always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end //end Priority conditions end //end RST Type conditions end //end one_stages_norm generate statement endgenerate // Special Reset Behavior for S3ADSP generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) begin : one_stage_splbhv always @(posedge CLK) begin if (en_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; end else if (regce_i && !rst_i) begin DOUT <= #FLOP_DELAY DIN; end //Output signal assignments end //end CLK end //end one_stage_splbhv generate statement endgenerate //************************************************************ // NUM_STAGES > 1 // Mem Output Reg + Mux Output Reg // or // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg // or // Mux Pipeline Stages (>0) + Mux Output Reg //************************************************************* generate if (NUM_STAGES > 1) begin : multi_stage //Asynchronous Reset always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end //end Priority conditions // Shift the data through the output stages if (en_i) begin out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; end end //end CLK end //end multi_stage generate statement endgenerate endmodule module blk_mem_gen_v8_3_4_softecc_output_reg_stage #(parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_USE_SOFTECC = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input [C_DATA_WIDTH-1:0] DIN, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN, input DBITERR_IN, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// reg [C_DATA_WIDTH-1:0] dout_i = 0; reg sbiterr_i = 0; reg dbiterr_i = 0; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; //*********************************************** // NO OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate //*********************************************** // WITH OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage always @(posedge CLK) begin dout_i <= #FLOP_DELAY DIN; rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; sbiterr_i <= #FLOP_DELAY SBITERR_IN; dbiterr_i <= #FLOP_DELAY DBITERR_IN; end always @* begin DOUT = dout_i; RDADDRECC = rdaddrecc_i; SBITERR = sbiterr_i; DBITERR = dbiterr_i; end //end always end //end in_or_out_stage generate statement endgenerate endmodule //***************************************************************************** // Main Memory module // // This module is the top-level behavioral model and this implements the RAM //***************************************************************************** module blk_mem_gen_v8_3_4_mem_module #(parameter C_CORENAME = "blk_mem_gen_v8_3_4", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_USE_BRAM_BLOCK = 0, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter FLOP_DELAY = 100, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_ECC_PIPE = 0, parameter C_DISABLE_WARN_BHV_RANGE = 0 ) (input CLKA, input RSTA, input ENA, input REGCEA, input [C_WEA_WIDTH-1:0] WEA, input [C_ADDRA_WIDTH-1:0] ADDRA, input [C_WRITE_WIDTH_A-1:0] DINA, output [C_READ_WIDTH_A-1:0] DOUTA, input CLKB, input RSTB, input ENB, input REGCEB, input [C_WEB_WIDTH-1:0] WEB, input [C_ADDRB_WIDTH-1:0] ADDRB, input [C_WRITE_WIDTH_B-1:0] DINB, output [C_READ_WIDTH_B-1:0] DOUTB, input INJECTSBITERR, input INJECTDBITERR, input ECCPIPECE, input SLEEP, output SBITERR, output DBITERR, output [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// // Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_4" and it is // only used by this module to print warning messages. It is neither passed // down from blk_mem_gen_v8_3_4_xst.v nor present in the instantiation template // coregen generates //*************************************************************************** // constants for the core behavior //*************************************************************************** // file handles for logging //-------------------------------------------------- localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range localparam COLLFILE = 32'h8000_0001; //stdout for coll detection localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors // other constants //-------------------------------------------------- localparam COLL_DELAY = 100; // 100 ps // locally derived parameters to determine memory shape //----------------------------------------------------- localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? C_WRITE_WIDTH_A : C_READ_WIDTH_A; localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? C_WRITE_WIDTH_B : C_READ_WIDTH_B; localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? MIN_WIDTH_A : MIN_WIDTH_B; localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? C_WRITE_DEPTH_A : C_READ_DEPTH_A; localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? C_WRITE_DEPTH_B : C_READ_DEPTH_B; localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? MAX_DEPTH_A : MAX_DEPTH_B; // locally derived parameters to assist memory access //---------------------------------------------------- // Calculate the width ratios of each port with respect to the narrowest // port localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; // To modify the LSBs of the 'wider' data to the actual // address value //---------------------------------------------------- localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; // If byte writes aren't being used, make sure BYTE_SIZE is not // wider than the memory elements to avoid compilation warnings localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; // The memory reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1]; reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; // ECC error arrays reg sbiterr_arr [0:MAX_DEPTH-1]; reg dbiterr_arr [0:MAX_DEPTH-1]; reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; // Memory output 'latches' reg [C_READ_WIDTH_A-1:0] memory_out_a; reg [C_READ_WIDTH_B-1:0] memory_out_b; // ECC error inputs and outputs from output_stage module: reg sbiterr_in; wire sbiterr_sdp; reg dbiterr_in; wire dbiterr_sdp; wire [C_READ_WIDTH_B-1:0] dout_i; wire dbiterr_i; wire sbiterr_i; wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; // Reset values reg [C_READ_WIDTH_A-1:0] inita_val; reg [C_READ_WIDTH_B-1:0] initb_val; // Collision detect reg is_collision; reg is_collision_a, is_collision_delay_a; reg is_collision_b, is_collision_delay_b; // Temporary variables for initialization //--------------------------------------- integer status; integer initfile; integer meminitfile; // data input buffer reg [C_WRITE_WIDTH_A-1:0] mif_data; reg [C_WRITE_WIDTH_A-1:0] mem_data; // string values in hex reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; // initialization filename reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE; //Constants used to calculate the effective address widths for each of the //four ports. integer cnt = 1; integer write_addr_a_width, read_addr_a_width; integer write_addr_b_width, read_addr_b_width; localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))))))); // Internal configuration parameters //--------------------------------------------- localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); localparam HAS_A_WRITE = (!IS_ROM); localparam HAS_B_WRITE = (C_MEM_TYPE==2); localparam HAS_A_READ = (C_MEM_TYPE!=1); localparam HAS_B_READ = (!SINGLE_PORT); localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); // Calculate the mux pipeline register stages for Port A and Port B //------------------------------------------------------------------ localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? C_MUX_PIPELINE_STAGES : 0; localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? C_MUX_PIPELINE_STAGES : 0; // Calculate total number of register stages in the core // ----------------------------------------------------- localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); wire ena_i; wire enb_i; wire reseta_i; wire resetb_i; wire [C_WEA_WIDTH-1:0] wea_i; wire [C_WEB_WIDTH-1:0] web_i; wire rea_i; wire reb_i; wire rsta_outp_stage; wire rstb_outp_stage; // ECC SBITERR/DBITERR Outputs // The ECC Behavior is modeled by the behavioral models only for Virtex-6. // For Virtex-5, these outputs will be tied to 0. assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; // This effectively wires off optional inputs assign ena_i = (C_HAS_ENA==0) || ENA; assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; //assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; // To Fix CR855535 assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0; assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; assign rea_i = (HAS_A_READ) ? ena_i : 'b0; assign reb_i = (HAS_B_READ) ? enb_i : 'b0; // These signals reset the memory latches assign reseta_i = ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); assign resetb_i = ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); // Tasks to access the memory //--------------------------- //************** // write_a //************** task write_a (input reg [C_ADDRA_WIDTH-1:0] addr, input reg [C_WEA_WIDTH-1:0] byte_en, input reg [C_WRITE_WIDTH_A-1:0] data, input inj_sbiterr, input inj_dbiterr); reg [C_WRITE_WIDTH_A-1:0] current_contents; reg [C_ADDRA_WIDTH-1:0] address; integer i; begin // Shift the address by the ratio address = (addr/WRITE_ADDR_A_DIV); if (address >= C_WRITE_DEPTH_A) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for A Write", C_CORENAME, addr); end // valid address end else begin // Combine w/ byte writes if (C_USE_BYTE_WEA) begin // Get the current memory contents if (WRITE_WIDTH_RATIO_A == 1) begin // Workaround for IUS 5.5 part-select issue current_contents = memory[address]; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin current_contents[MIN_WIDTH*i+:MIN_WIDTH] = memory[address*WRITE_WIDTH_RATIO_A + i]; end end // Apply incoming bytes if (C_WEA_WIDTH == 1) begin // Workaround for IUS 5.5 part-select issue if (byte_en[0]) begin current_contents = data; end end else begin for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin if (byte_en[i]) begin current_contents[BYTE_SIZE*i+:BYTE_SIZE] = data[BYTE_SIZE*i+:BYTE_SIZE]; end end end // No byte-writes, overwrite the whole word end else begin current_contents = data; end // Insert double bit errors: if (C_USE_ECC == 1) begin if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin // Modified for Implementing CR_859399 current_contents[0] = !(current_contents[30]); current_contents[1] = !(current_contents[62]); /*current_contents[0] = !(current_contents[0]); current_contents[1] = !(current_contents[1]);*/ end end // Insert softecc double bit errors: if (C_USE_SOFTECC == 1) begin if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; end end // Write data to memory if (WRITE_WIDTH_RATIO_A == 1) begin // Workaround for IUS 5.5 part-select issue memory[address*WRITE_WIDTH_RATIO_A] = current_contents; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin memory[address*WRITE_WIDTH_RATIO_A + i] = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; end end // Store the address at which error is injected: if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) begin sbiterr_arr[addr] = 1; end else begin sbiterr_arr[addr] = 0; end if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin dbiterr_arr[addr] = 1; end else begin dbiterr_arr[addr] = 0; end end // Store the address at which softecc error is injected: if (C_USE_SOFTECC == 1) begin if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) begin softecc_sbiterr_arr[addr] = 1; end else begin softecc_sbiterr_arr[addr] = 0; end if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin softecc_dbiterr_arr[addr] = 1; end else begin softecc_dbiterr_arr[addr] = 0; end end end end endtask //************** // write_b //************** task write_b (input reg [C_ADDRB_WIDTH-1:0] addr, input reg [C_WEB_WIDTH-1:0] byte_en, input reg [C_WRITE_WIDTH_B-1:0] data); reg [C_WRITE_WIDTH_B-1:0] current_contents; reg [C_ADDRB_WIDTH-1:0] address; integer i; begin // Shift the address by the ratio address = (addr/WRITE_ADDR_B_DIV); if (address >= C_WRITE_DEPTH_B) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for B Write", C_CORENAME, addr); end // valid address end else begin // Combine w/ byte writes if (C_USE_BYTE_WEB) begin // Get the current memory contents if (WRITE_WIDTH_RATIO_B == 1) begin // Workaround for IUS 5.5 part-select issue current_contents = memory[address]; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin current_contents[MIN_WIDTH*i+:MIN_WIDTH] = memory[address*WRITE_WIDTH_RATIO_B + i]; end end // Apply incoming bytes if (C_WEB_WIDTH == 1) begin // Workaround for IUS 5.5 part-select issue if (byte_en[0]) begin current_contents = data; end end else begin for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin if (byte_en[i]) begin current_contents[BYTE_SIZE*i+:BYTE_SIZE] = data[BYTE_SIZE*i+:BYTE_SIZE]; end end end // No byte-writes, overwrite the whole word end else begin current_contents = data; end // Write data to memory if (WRITE_WIDTH_RATIO_B == 1) begin // Workaround for IUS 5.5 part-select issue memory[address*WRITE_WIDTH_RATIO_B] = current_contents; end else begin for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin memory[address*WRITE_WIDTH_RATIO_B + i] = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; end end end end endtask //************** // read_a //************** task read_a (input reg [C_ADDRA_WIDTH-1:0] addr, input reg reset); reg [C_ADDRA_WIDTH-1:0] address; integer i; begin if (reset) begin memory_out_a <= #FLOP_DELAY inita_val; end else begin // Shift the address by the ratio address = (addr/READ_ADDR_A_DIV); if (address >= C_READ_DEPTH_A) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for A Read", C_CORENAME, addr); end memory_out_a <= #FLOP_DELAY 'bX; // valid address end else begin if (READ_WIDTH_RATIO_A==1) begin memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; end else begin // Increment through the 'partial' words in the memory for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; end end //end READ_WIDTH_RATIO_A==1 loop end //end valid address loop end //end reset-data assignment loops end endtask //************** // read_b //************** task read_b (input reg [C_ADDRB_WIDTH-1:0] addr, input reg reset); reg [C_ADDRB_WIDTH-1:0] address; integer i; begin if (reset) begin memory_out_b <= #FLOP_DELAY initb_val; sbiterr_in <= #FLOP_DELAY 1'b0; dbiterr_in <= #FLOP_DELAY 1'b0; rdaddrecc_in <= #FLOP_DELAY 0; end else begin // Shift the address address = (addr/READ_ADDR_B_DIV); if (address >= C_READ_DEPTH_B) begin if (!C_DISABLE_WARN_BHV_RANGE) begin $fdisplay(ADDRFILE, "%0s WARNING: Address %0h is outside range for B Read", C_CORENAME, addr); end memory_out_b <= #FLOP_DELAY 'bX; sbiterr_in <= #FLOP_DELAY 1'bX; dbiterr_in <= #FLOP_DELAY 1'bX; rdaddrecc_in <= #FLOP_DELAY 'bX; // valid address end else begin if (READ_WIDTH_RATIO_B==1) begin memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; end else begin // Increment through the 'partial' words in the memory for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; end end if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin rdaddrecc_in <= #FLOP_DELAY addr; if (sbiterr_arr[addr] == 1) begin sbiterr_in <= #FLOP_DELAY 1'b1; end else begin sbiterr_in <= #FLOP_DELAY 1'b0; end if (dbiterr_arr[addr] == 1) begin dbiterr_in <= #FLOP_DELAY 1'b1; end else begin dbiterr_in <= #FLOP_DELAY 1'b0; end end else if (C_USE_SOFTECC == 1) begin rdaddrecc_in <= #FLOP_DELAY addr; if (softecc_sbiterr_arr[addr] == 1) begin sbiterr_in <= #FLOP_DELAY 1'b1; end else begin sbiterr_in <= #FLOP_DELAY 1'b0; end if (softecc_dbiterr_arr[addr] == 1) begin dbiterr_in <= #FLOP_DELAY 1'b1; end else begin dbiterr_in <= #FLOP_DELAY 1'b0; end end else begin rdaddrecc_in <= #FLOP_DELAY 0; dbiterr_in <= #FLOP_DELAY 1'b0; sbiterr_in <= #FLOP_DELAY 1'b0; end //end SOFTECC Loop end //end Valid address loop end //end reset-data assignment loops end endtask //************** // reset_a //************** task reset_a (input reg reset); begin if (reset) memory_out_a <= #FLOP_DELAY inita_val; end endtask //************** // reset_b //************** task reset_b (input reg reset); begin if (reset) memory_out_b <= #FLOP_DELAY initb_val; end endtask //************** // init_memory //************** task init_memory; integer i, j, addr_step; integer status; reg [C_WRITE_WIDTH_A-1:0] default_data; begin default_data = 0; //Display output message indicating that the behavioral model is being //initialized if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data..."); // Convert the default to hex if (C_USE_DEFAULT_DATA) begin if (default_data_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); $finish; end else begin status = $sscanf(default_data_str, "%h", default_data); if (status == 0) begin $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", "from C_DEFAULT_DATA: %0s"}, C_CORENAME, C_DEFAULT_DATA); $finish; end end end // Step by WRITE_ADDR_A_DIV through the memory via the // Port A write interface to hit every location once addr_step = WRITE_ADDR_A_DIV; // 'write' to every location with default (or 0) for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); end // Get specialized data from the MIF file if (C_LOAD_INIT_FILE) begin if (init_file_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", C_CORENAME); $finish; end else begin initfile = $fopen(init_file_str, "r"); if (initfile == 0) begin $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", "C_INIT_FILE_NAME: %0s!"}, C_CORENAME, init_file_str); $finish; end else begin // loop through the mif file, loading in the data for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin status = $fscanf(initfile, "%b", mif_data); if (status > 0) begin write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); end end $fclose(initfile); end //initfile end //init_file_str end //C_LOAD_INIT_FILE if (C_USE_BRAM_BLOCK) begin // Get specialized data from the MIF file if (C_INIT_FILE != "NONE") begin if (mem_init_file_str == "") begin $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!", C_CORENAME); $finish; end else begin meminitfile = $fopen(mem_init_file_str, "r"); if (meminitfile == 0) begin $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", "C_INIT_FILE: %0s!"}, C_CORENAME, mem_init_file_str); $finish; end else begin // loop through the mif file, loading in the data $readmemh(mem_init_file_str, memory ); for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin end $fclose(meminitfile); end //meminitfile end //mem_init_file_str end //C_INIT_FILE end //C_USE_BRAM_BLOCK //Display output message indicating that the behavioral model is done //initializing if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator data initialization complete."); end endtask //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //******************* // collision_check //******************* function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, input integer iswrite_a, input reg [C_ADDRB_WIDTH-1:0] addr_b, input integer iswrite_b); reg c_aw_bw, c_aw_br, c_ar_bw; integer scaled_addra_to_waddrb_width; integer scaled_addrb_to_waddrb_width; integer scaled_addra_to_waddra_width; integer scaled_addrb_to_waddra_width; integer scaled_addra_to_raddrb_width; integer scaled_addrb_to_raddrb_width; integer scaled_addra_to_raddra_width; integer scaled_addrb_to_raddra_width; begin c_aw_bw = 0; c_aw_br = 0; c_ar_bw = 0; //If write_addr_b_width is smaller, scale both addresses to that width for //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to write_addr_b_width. Once both are scaled to //write_addr_b_width, compare. scaled_addra_to_waddrb_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-write_addr_b_width)); scaled_addrb_to_waddrb_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-write_addr_b_width)); //If write_addr_a_width is smaller, scale both addresses to that width for //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to write_addr_a_width. Once both are scaled to //write_addr_a_width, compare. scaled_addra_to_waddra_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-write_addr_a_width)); scaled_addrb_to_waddra_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-write_addr_a_width)); //If read_addr_b_width is smaller, scale both addresses to that width for //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to read_addr_b_width. Once both are scaled to //read_addr_b_width, compare. scaled_addra_to_raddrb_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-read_addr_b_width)); scaled_addrb_to_raddrb_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-read_addr_b_width)); //If read_addr_a_width is smaller, scale both addresses to that width for //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, //scale it down to read_addr_a_width. Once both are scaled to //read_addr_a_width, compare. scaled_addra_to_raddra_width = ((addr_a)/ 2**(C_ADDRA_WIDTH-read_addr_a_width)); scaled_addrb_to_raddra_width = ((addr_b)/ 2**(C_ADDRB_WIDTH-read_addr_a_width)); //Look for a write-write collision. In order for a write-write //collision to exist, both ports must have a write transaction. if (iswrite_a && iswrite_b) begin if (write_addr_a_width > write_addr_b_width) begin if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin c_aw_bw = 1; end else begin c_aw_bw = 0; end end else begin if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin c_aw_bw = 1; end else begin c_aw_bw = 0; end end //width end //iswrite_a and iswrite_b //If the B port is reading (which means it is enabled - so could be //a TX_WRITE or TX_READ), then check for a write-read collision). //This could happen whether or not a write-write collision exists due //to asymmetric write/read ports. if (iswrite_a) begin if (write_addr_a_width > read_addr_b_width) begin if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin c_aw_br = 1; end else begin c_aw_br = 0; end end else begin if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin c_aw_br = 1; end else begin c_aw_br = 0; end end //width end //iswrite_a //If the A port is reading (which means it is enabled - so could be // a TX_WRITE or TX_READ), then check for a write-read collision). //This could happen whether or not a write-write collision exists due // to asymmetric write/read ports. if (iswrite_b) begin if (read_addr_a_width > write_addr_b_width) begin if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin c_ar_bw = 1; end else begin c_ar_bw = 0; end end else begin if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin c_ar_bw = 1; end else begin c_ar_bw = 0; end end //width end //iswrite_b collision_check = c_aw_bw | c_aw_br | c_ar_bw; end endfunction //******************************* // power on values //******************************* initial begin // Load up the memory init_memory; // Load up the output registers and latches if ($sscanf(inita_str, "%h", inita_val)) begin memory_out_a = inita_val; end else begin memory_out_a = 0; end if ($sscanf(initb_str, "%h", initb_val)) begin memory_out_b = initb_val; end else begin memory_out_b = 0; end sbiterr_in = 1'b0; dbiterr_in = 1'b0; rdaddrecc_in = 0; // Determine the effective address widths for each of the 4 ports write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); end //*************************************************************************** // These are the main blocks which schedule read and write operations // Note that the reset priority feature at the latch stage is only supported // for Spartan-6. For other families, the default priority at the latch stage // is "CE" //*************************************************************************** // Synchronous clocks: schedule port operations with respect to // both write operating modes generate if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_wf_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_rf_wf always @(posedge CLKA) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_wf_rf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_rf_rf always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_wf_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_rf_nc always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "WRITE_FIRST")) begin : com_clk_sched_nc_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "READ_FIRST")) begin : com_clk_sched_nc_rf always @(posedge CLKA) begin //Read B if (reb_i) read_b(ADDRB, resetb_i); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == "NO_CHANGE")) begin : com_clk_sched_nc_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); end end else if(C_COMMON_CLK) begin: com_clk_sched_default always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read A if (rea_i) read_a(ADDRA, reseta_i); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end endgenerate // Asynchronous clocks: port operation is independent generate if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i) read_a(ADDRA, reseta_i); end end else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf always @(posedge CLKA) begin //Read A if (rea_i) read_a(ADDRA, reseta_i); //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); end end else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc always @(posedge CLKA) begin //Write A if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); //Read A if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); end end endgenerate generate if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf always @(posedge CLKB) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i) read_b(ADDRB, resetb_i); end end else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf always @(posedge CLKB) begin //Read B if (reb_i) read_b(ADDRB, resetb_i); //Write B if (web_i) write_b(ADDRB, web_i, DINB); end end else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc always @(posedge CLKB) begin //Write B if (web_i) write_b(ADDRB, web_i, DINB); //Read B if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); end end endgenerate //*************************************************************** // Instantiate the variable depth output register stage module //*************************************************************** // Port A assign rsta_outp_stage = RSTA & (~SLEEP); blk_mem_gen_v8_3_4_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTA), .C_RSTRAM (C_RSTRAM_A), .C_RST_PRIORITY (C_RST_PRIORITY_A), .C_INIT_VAL (C_INITA_VAL), .C_HAS_EN (C_HAS_ENA), .C_HAS_REGCE (C_HAS_REGCEA), .C_DATA_WIDTH (C_READ_WIDTH_A), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_A), .C_EN_ECC_PIPE (0), .FLOP_DELAY (FLOP_DELAY)) reg_a (.CLK (CLKA), .RST (rsta_outp_stage),//(RSTA), .EN (ENA), .REGCE (REGCEA), .DIN_I (memory_out_a), .DOUT (DOUTA), .SBITERR_IN_I (1'b0), .DBITERR_IN_I (1'b0), .SBITERR (), .DBITERR (), .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), .ECCPIPECE (1'b0), .RDADDRECC () ); assign rstb_outp_stage = RSTB & (~SLEEP); // Port B blk_mem_gen_v8_3_4_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTB), .C_RSTRAM (C_RSTRAM_B), .C_RST_PRIORITY (C_RST_PRIORITY_B), .C_INIT_VAL (C_INITB_VAL), .C_HAS_EN (C_HAS_ENB), .C_HAS_REGCE (C_HAS_REGCEB), .C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_B), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .FLOP_DELAY (FLOP_DELAY)) reg_b (.CLK (CLKB), .RST (rstb_outp_stage),//(RSTB), .EN (ENB), .REGCE (REGCEB), .DIN_I (memory_out_b), .DOUT (dout_i), .SBITERR_IN_I (sbiterr_in), .DBITERR_IN_I (dbiterr_in), .SBITERR (sbiterr_i), .DBITERR (dbiterr_i), .RDADDRECC_IN_I (rdaddrecc_in), .ECCPIPECE (ECCPIPECE), .RDADDRECC (rdaddrecc_i) ); //*************************************************************** // Instantiate the Input and Output register stages //*************************************************************** blk_mem_gen_v8_3_4_softecc_output_reg_stage #(.C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .FLOP_DELAY (FLOP_DELAY)) has_softecc_output_reg_stage (.CLK (CLKB), .DIN (dout_i), .DOUT (DOUTB), .SBITERR_IN (sbiterr_i), .DBITERR_IN (dbiterr_i), .SBITERR (sbiterr_sdp), .DBITERR (dbiterr_sdp), .RDADDRECC_IN (rdaddrecc_i), .RDADDRECC (rdaddrecc_sdp) ); //**************************************************** // Synchronous collision checks //**************************************************** // CR 780544 : To make verilog model's collison warnings in consistant with // vhdl model, the non-blocking assignments are replaced with blocking // assignments. generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision = 0; end end else begin is_collision = 0; end // If the write port is in READ_FIRST mode, there is no collision if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin is_collision = 0; end if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin is_collision = 0; end // Only flag if one of the accesses is a write if (is_collision && (wea_i || web_i)) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", wea_i ? "write" : "read", ADDRA, web_i ? "write" : "read", ADDRB); end end //**************************************************** // Asynchronous collision checks //**************************************************** end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll // Delay A and B addresses in order to mimic setup/hold times wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; wire [0:0] #COLL_DELAY wea_delay = wea_i; wire #COLL_DELAY ena_delay = ena_i; wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; wire [0:0] #COLL_DELAY web_delay = web_i; wire #COLL_DELAY enb_delay = enb_i; // Do the checks w/rt A always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_a = 0; end end else begin is_collision_a = 0; end if (ena_i && enb_delay) begin if(wea_i || web_delay) begin is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, web_delay); end else begin is_collision_delay_a = 0; end end else begin is_collision_delay_a = 0; end // Only flag if B access is a write if (is_collision_a && web_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, ADDRB); end else if (is_collision_delay_a && web_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, addrb_delay); end end // Do the checks w/rt B always @(posedge CLKB) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_b = 0; end end else begin is_collision_b = 0; end if (ena_delay && enb_i) begin if (wea_delay || web_i) begin is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, web_i); end else begin is_collision_delay_b = 0; end end else begin is_collision_delay_b = 0; end // Only flag if A access is a write if (is_collision_b && wea_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", ADDRA, web_i ? "write" : "read", ADDRB); end else if (is_collision_delay_b && wea_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", addra_delay, web_i ? "write" : "read", ADDRB); end end end endgenerate endmodule //***************************************************************************** // Top module wraps Input register and Memory module // // This module is the top-level behavioral model and this implements the memory // module and the input registers //***************************************************************************** module blk_mem_gen_v8_3_4 #(parameter C_CORENAME = "blk_mem_gen_v8_3_4", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_ELABORATION_DIR = "", parameter C_INTERFACE_TYPE = 0, parameter C_USE_BRAM_BLOCK = 0, parameter C_CTRL_ECC_ALGO = "NONE", parameter C_ENABLE_32BIT_ADDRESS = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", //parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_EN_ECC_PIPE = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_SLEEP_PIN = 0, parameter C_USE_URAM = 0, parameter C_EN_RDADDRA_CHG = 0, parameter C_EN_RDADDRB_CHG = 0, parameter C_EN_DEEPSLEEP_PIN = 0, parameter C_EN_SHUTDOWN_PIN = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_COUNT_36K_BRAM = "", parameter C_COUNT_18K_BRAM = "", parameter C_EST_POWER_SUMMARY = "", parameter C_DISABLE_WARN_BHV_RANGE = 0 ) (input clka, input rsta, input ena, input regcea, input [C_WEA_WIDTH-1:0] wea, input [C_ADDRA_WIDTH-1:0] addra, input [C_WRITE_WIDTH_A-1:0] dina, output [C_READ_WIDTH_A-1:0] douta, input clkb, input rstb, input enb, input regceb, input [C_WEB_WIDTH-1:0] web, input [C_ADDRB_WIDTH-1:0] addrb, input [C_WRITE_WIDTH_B-1:0] dinb, output [C_READ_WIDTH_B-1:0] doutb, input injectsbiterr, input injectdbiterr, output sbiterr, output dbiterr, output [C_ADDRB_WIDTH-1:0] rdaddrecc, input eccpipece, input sleep, input deepsleep, input shutdown, output rsta_busy, output rstb_busy, //AXI BMG Input and Output Port Declarations //AXI Global Signals input s_aclk, input s_aresetn, //AXI Full/lite slave write (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [31:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input s_axi_awvalid, output s_axi_awready, input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, input [C_WEA_WIDTH-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, input s_axi_bready, //AXI Full/lite slave read (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [31:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, input s_axi_rready, //AXI Full/lite sideband signals input s_axi_injectsbiterr, input s_axi_injectdbiterr, output s_axi_sbiterr, output s_axi_dbiterr, output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_HAS_SOFTECC_INPUT_REGS_A : // C_HAS_SOFTECC_OUTPUT_REGS_B : // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// wire SBITERR; wire DBITERR; wire S_AXI_AWREADY; wire S_AXI_WREADY; wire S_AXI_BVALID; wire S_AXI_ARREADY; wire S_AXI_RLAST; wire S_AXI_RVALID; wire S_AXI_SBITERR; wire S_AXI_DBITERR; wire [C_WEA_WIDTH-1:0] WEA = wea; wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; wire [C_WRITE_WIDTH_A-1:0] DINA = dina; wire [C_READ_WIDTH_A-1:0] DOUTA; wire [C_WEB_WIDTH-1:0] WEB = web; wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; wire [C_READ_WIDTH_B-1:0] DOUTB; wire [C_ADDRB_WIDTH-1:0] RDADDRECC; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; wire [31:0] S_AXI_AWADDR = s_axi_awaddr; wire [7:0] S_AXI_AWLEN = s_axi_awlen; wire [2:0] S_AXI_AWSIZE = s_axi_awsize; wire [1:0] S_AXI_AWBURST = s_axi_awburst; wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [1:0] S_AXI_BRESP; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; wire [31:0] S_AXI_ARADDR = s_axi_araddr; wire [7:0] S_AXI_ARLEN = s_axi_arlen; wire [2:0] S_AXI_ARSIZE = s_axi_arsize; wire [1:0] S_AXI_ARBURST = s_axi_arburst; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; wire [1:0] S_AXI_RRESP; wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; // Added to fix the simulation warning #CR731605 wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; wire ECCPIPECE; wire SLEEP; reg RSTA_BUSY = 0; reg RSTB_BUSY = 0; // Declaration of internal signals to avoid warnings #927399 wire CLKA; wire RSTA; wire ENA; wire REGCEA; wire CLKB; wire RSTB; wire ENB; wire REGCEB; wire INJECTSBITERR; wire INJECTDBITERR; wire S_ACLK; wire S_ARESETN; wire S_AXI_AWVALID; wire S_AXI_WLAST; wire S_AXI_WVALID; wire S_AXI_BREADY; wire S_AXI_ARVALID; wire S_AXI_RREADY; wire S_AXI_INJECTSBITERR; wire S_AXI_INJECTDBITERR; assign CLKA = clka; assign RSTA = rsta; assign ENA = ena; assign REGCEA = regcea; assign CLKB = clkb; assign RSTB = rstb; assign ENB = enb; assign REGCEB = regceb; assign INJECTSBITERR = injectsbiterr; assign INJECTDBITERR = injectdbiterr; assign ECCPIPECE = eccpipece; assign SLEEP = sleep; assign sbiterr = SBITERR; assign dbiterr = DBITERR; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; assign s_axi_sbiterr = S_AXI_SBITERR; assign s_axi_dbiterr = S_AXI_DBITERR; assign rsta_busy = RSTA_BUSY; assign rstb_busy = RSTB_BUSY; assign doutb = DOUTB; assign douta = DOUTA; assign rdaddrecc = RDADDRECC; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_rdaddrecc = S_AXI_RDADDRECC; localparam FLOP_DELAY = 100; // 100 ps reg injectsbiterr_in; reg injectdbiterr_in; reg rsta_in; reg ena_in; reg regcea_in; reg [C_WEA_WIDTH-1:0] wea_in; reg [C_ADDRA_WIDTH-1:0] addra_in; reg [C_WRITE_WIDTH_A-1:0] dina_in; wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; wire s_axi_wr_en_c; wire s_axi_rd_en_c; wire s_aresetn_a_c; wire [7:0] s_axi_arlen_c ; wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; wire [1:0] s_axi_rresp_c; wire s_axi_rlast_c; wire s_axi_rvalid_c; wire s_axi_rready_c; wire regceb_c; localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; // Safety logic related signals reg [4:0] RSTA_SHFT_REG = 0; reg POR_A = 0; reg [4:0] RSTB_SHFT_REG = 0; reg POR_B = 0; reg ENA_dly = 0; reg ENA_dly_D = 0; reg ENB_dly = 0; reg ENB_dly_D = 0; wire RSTA_I_SAFE; wire RSTB_I_SAFE; wire ENA_I_SAFE; wire ENB_I_SAFE; reg ram_rstram_a_busy = 0; reg ram_rstreg_a_busy = 0; reg ram_rstram_b_busy = 0; reg ram_rstreg_b_busy = 0; reg ENA_dly_reg = 0; reg ENB_dly_reg = 0; reg ENA_dly_reg_D = 0; reg ENB_dly_reg_D = 0; //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //************** // log2int //************** function integer log2int (input integer data_value); integer width; integer cnt; begin width = 0; cnt= data_value; for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin width = width + 1; end //loop log2int = width; end //log2int endfunction //************************************************************************** // FUNCTION : divroundup // Returns the ceiling value of the division // Data_value - the quantity to be divided, dividend // Divisor - the value to divide the data_value by //************************************************************************** function integer divroundup (input integer data_value,input integer divisor); integer div; begin div = data_value/divisor; if ((data_value % divisor) != 0) begin div = div+1; end //if divroundup = div; end //if endfunction localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; //Data Width Number of LSB address bits to be discarded //1 to 16 1 //17 to 32 2 //33 to 64 3 //65 to 128 4 //129 to 256 5 //257 to 512 6 //513 to 1024 7 // The following two constants determine this. localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); localparam C_AXI_OS_WR = 2; //*********************************************** // INPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage always @* begin injectsbiterr_in = INJECTSBITERR; injectdbiterr_in = INJECTDBITERR; rsta_in = RSTA; ena_in = ENA; regcea_in = REGCEA; wea_in = WEA; addra_in = ADDRA; dina_in = DINA; end //end always end //end no_softecc_input_reg_stage endgenerate generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage always @(posedge CLKA) begin injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; rsta_in <= #FLOP_DELAY RSTA; ena_in <= #FLOP_DELAY ENA; regcea_in <= #FLOP_DELAY REGCEA; wea_in <= #FLOP_DELAY WEA; addra_in <= #FLOP_DELAY ADDRA; dina_in <= #FLOP_DELAY DINA; end //end always end //end input_reg_stages generate statement endgenerate //************************************************************************** // NO SAFETY LOGIC //************************************************************************** generate if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN assign ENA_I_SAFE = ena_in; assign ENB_I_SAFE = ENB; assign RSTA_I_SAFE = rsta_in; assign RSTB_I_SAFE = RSTB; end endgenerate //*************************************************************************** // SAFETY LOGIC // Power-ON Reset Generation //*************************************************************************** generate if (C_EN_SAFETY_CKT == 1) begin always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ; always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0]; always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ; always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; assign RSTA_I_SAFE = rsta_in | POR_A; assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B); end endgenerate //----------------------------------------------------------------------------- // -- RSTA/B_BUSY Generation //----------------------------------------------------------------------------- generate if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D; always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D; always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy; end endgenerate generate if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY always @(*) RSTB_BUSY = 1'b0; end endgenerate generate if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D; always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D; always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy; end endgenerate //----------------------------------------------------------------------------- // -- ENA/ENB Generation //----------------------------------------------------------------------------- generate if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG always @(posedge clka) begin ENA_dly <= #FLOP_DELAY RSTA_I_SAFE; ENA_dly_D <= #FLOP_DELAY ENA_dly; end assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in); end endgenerate generate if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG always @(posedge clka) begin ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE; ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg; end assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in); end endgenerate generate if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB assign ENB_I_SAFE = 1'b0; end endgenerate generate if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG always @(posedge clkb) begin : PROC_ENB_GEN ENB_dly <= #FLOP_DELAY RSTB_I_SAFE; ENB_dly_D <= #FLOP_DELAY ENB_dly; end assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG always @(posedge clkb) begin : PROC_ENB_GEN ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE; ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg; end assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB); end endgenerate generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_ALGORITHM (C_ALGORITHM), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (CLKA), .RSTA (RSTA_I_SAFE),//(rsta_in), .ENA (ENA_I_SAFE),//(ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB_I_SAFE),//(RSTB), .ENB (ENB_I_SAFE),//(ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (RDADDRECC) ); end endgenerate generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; // Data Width Number of LSB address bits to be discarded // 1 to 16 1 // 17 to 32 2 // 33 to 64 3 // 65 to 128 4 // 129 to 256 5 // 257 to 512 6 // 513 to 1024 7 // The following two constants determine this. localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; assign msb_zero_i = 0; assign lsb_zero_i = 0; assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (CLKA), .RSTA (RSTA_I_SAFE),//(rsta_in), .ENA (ENA_I_SAFE),//(ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB_I_SAFE),//(RSTB), .ENB (ENB_I_SAFE),//(ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (rdaddrecc_i) ); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RLAST = s_axi_rlast_c; assign S_AXI_RVALID = s_axi_rvalid_c; assign S_AXI_RID = s_axi_rid_c; assign S_AXI_RRESP = s_axi_rresp_c; assign s_axi_rready_c = S_AXI_RREADY; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb assign regceb_c = REGCEB; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd blk_mem_axi_regs_fwd_v8_3 #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) axi_regs_inst ( .ACLK (S_ACLK), .ARESET (s_aresetn_a_c), .S_VALID (s_axi_rvalid_c), .S_READY (s_axi_rready_c), .S_PAYLOAD_DATA (s_axi_payload_c), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY), .M_PAYLOAD_DATA (m_axi_payload_c) ); end endgenerate generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module assign s_aresetn_a_c = !S_ARESETN; assign S_AXI_BRESP = 2'b00; assign s_axi_rresp_c = 2'b00; assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; blk_mem_axi_write_wrapper_beh_v8_3 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), .C_AXI_OS_WR (C_AXI_OS_WR)) axi_wr_fsm ( // AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), // AXI Full/Lite Slave Write interface .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_AWLEN (S_AXI_AWLEN), .S_AXI_AWID (S_AXI_AWID), .S_AXI_AWSIZE (S_AXI_AWSIZE), .S_AXI_AWBURST (S_AXI_AWBURST), .S_AXI_AWVALID (S_AXI_AWVALID), .S_AXI_AWREADY (S_AXI_AWREADY), .S_AXI_WVALID (S_AXI_WVALID), .S_AXI_WREADY (S_AXI_WREADY), .S_AXI_BVALID (S_AXI_BVALID), .S_AXI_BREADY (S_AXI_BREADY), .S_AXI_BID (S_AXI_BID), // Signals for BRAM interfac( .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), .S_AXI_WR_EN (s_axi_wr_en_c) ); blk_mem_axi_read_wrapper_beh_v8_3 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_PIPELINE_STAGES (1), .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_rd_sm( //AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), //AXI Full/Lite Read Side .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_ARLEN (s_axi_arlen_c), .S_AXI_ARSIZE (S_AXI_ARSIZE), .S_AXI_ARBURST (S_AXI_ARBURST), .S_AXI_ARVALID (S_AXI_ARVALID), .S_AXI_ARREADY (S_AXI_ARREADY), .S_AXI_RLAST (s_axi_rlast_c), .S_AXI_RVALID (s_axi_rvalid_c), .S_AXI_RREADY (s_axi_rready_c), .S_AXI_ARID (S_AXI_ARID), .S_AXI_RID (s_axi_rid_c), //AXI Full/Lite Read FSM Outputs .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), .S_AXI_RD_EN (s_axi_rd_en_c) ); blk_mem_gen_v8_3_4_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (1), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (1), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (1), .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_BYTE_WEB (1), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (0), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (0), .C_HAS_MUX_OUTPUT_REGS_B (0), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (0), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_3_4_inst (.CLKA (S_ACLK), .RSTA (s_aresetn_a_c), .ENA (s_axi_wr_en_c), .REGCEA (regcea_in), .WEA (S_AXI_WSTRB), .ADDRA (s_axi_awaddr_out_c), .DINA (S_AXI_WDATA), .DOUTA (DOUTA), .CLKB (S_ACLK), .RSTB (s_aresetn_a_c), .ENB (s_axi_rd_en_c), .REGCEB (regceb_c), .WEB (WEB_parameterized), .ADDRB (s_axi_araddr_out_c), .DINB (DINB), .DOUTB (s_axi_rdata_c), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .SBITERR (SBITERR), .DBITERR (DBITERR), .ECCPIPECE (1'b0), .SLEEP (1'b0), .RDADDRECC (RDADDRECC) ); end endgenerate endmodule ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/synth/output_line_buffer.vhd ================================================ -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_4; USE blk_mem_gen_v8_3_4.blk_mem_gen_v8_3_4; ENTITY output_line_buffer IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END output_line_buffer; ARCHITECTURE output_line_buffer_arch OF output_line_buffer IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_line_buffer_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_4 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_4; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF output_line_buffer_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_4,Vivado 2016.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF output_line_buffer_arch : ARCHITECTURE IS "output_line_buffer,blk_mem_gen_v8_3_4,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF output_line_buffer_arch: ARCHITECTURE IS "output_line_buffer,blk_mem_gen_v8_3_4,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAM" & "E=no_coe_file_loaded,C_INIT_FILE=output_line_buffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=256,C_READ_WIDTH_A=256,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_" & "READ_WIDTH_B=64,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C" & "_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 33.580152 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_3_4 GENERIC MAP ( C_FAMILY => "kintex7", C_XDEVICEFAMILY => "kintex7", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 1, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "output_line_buffer.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "NO_CHANGE", C_WRITE_WIDTH_A => 256, C_READ_WIDTH_A => 256, C_WRITE_DEPTH_A => 1024, C_READ_DEPTH_A => 1024, C_ADDRA_WIDTH => 10, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 64, C_READ_WIDTH_B => 64, C_WRITE_DEPTH_B => 4096, C_READ_DEPTH_B => 4096, C_ADDRB_WIDTH => 12, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "7", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 33.580152 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, clkb => clkb, rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => addrb, dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 256)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END output_line_buffer_arch; ================================================ FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.xpr ================================================ ================================================ FILE: vhdl_rx/framebuffer-ctrl/framebuffer_ctrl.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Framebuffer Controller for 4k camera demo --Copyright (C) 2016 David Shah --Licensed under the MIT License --This controls a AXI4 compliant framebuffer (implemented in DDR3) for the purposes --of processing the 4k camera stream to display on a 1080p monitor. It supports either --a 1x crop mode or a 0.5x zoom-out mode implemented by skipping lines and pixels --The input port is two pixels wide and the output port one pixel wide. VSYNC and DE inputs in both --cases are active high entity framebuffer_ctrl_crop_scale is generic( burst_len : natural := 16; input_width : natural := 3840; --Pixel size of input video input_height : natural := 2160; output_width : natural := 1920; --Pixel size of output video output_height : natural := 1080; crop_xoffset : natural := 1024; --X/Y offset in crop mode (chosen to avoid bursts crossing a 4k boundary) crop_yoffset : natural := 540; scale_xoffset : natural := 0; --X/Y offset in scale mode (not used, for future purposes only) scale_yoffset : natural := 0 ); port( --Input pixel port input_clock : in std_logic; input_vsync : in std_logic; input_line_start : in std_logic; input_den : in std_logic; input_data_even : in std_logic_vector(23 downto 0); input_data_odd : in std_logic_vector(23 downto 0); --Output pixel port output_clock : in std_logic; output_vsync : in std_logic; output_line_start : in std_logic; output_den : in std_logic; output_data : out std_logic_vector(23 downto 0); --AXI4 master general axi_clock : in std_logic; axi_resetn : in std_logic; --AXI4 write address axi_awid : out std_logic_vector(0 downto 0); axi_awaddr : out std_logic_vector(29 downto 0); axi_awlen : out std_logic_vector(7 downto 0); axi_awsize : out std_logic_vector(2 downto 0); axi_awburst : out std_logic_vector(1 downto 0); axi_awlock : out std_logic_vector(0 downto 0); axi_awcache : out std_logic_vector(3 downto 0); axi_awprot : out std_logic_vector(2 downto 0); axi_awqos : out std_logic_vector(3 downto 0); axi_awvalid : out std_logic; axi_awready : in std_logic; --AXI4 write data axi_wdata : out std_logic_vector(255 downto 0); axi_wstrb : out std_logic_vector(31 downto 0); axi_wlast : out std_logic; axi_wvalid : out std_logic; axi_wready : in std_logic; --AXI4 write response axi_bid : in std_logic_vector(0 downto 0); axi_bresp : in std_logic_vector(1 downto 0); axi_bvalid : in std_logic; axi_bready : out std_logic; --AXI4 read address axi_arid : out std_logic_vector(0 downto 0); axi_araddr : out std_logic_vector(29 downto 0); axi_arlen : out std_logic_vector(7 downto 0); axi_arsize : out std_logic_vector(2 downto 0); axi_arburst : out std_logic_vector(1 downto 0); axi_arlock : out std_logic_vector(0 downto 0); axi_arcache : out std_logic_vector(3 downto 0); axi_arprot : out std_logic_vector(2 downto 0); axi_arqos : out std_logic_vector(3 downto 0); axi_arvalid : out std_logic; axi_arready : in std_logic; --AXI4 read data axi_rid : in std_logic_vector(0 downto 0); axi_rdata : in std_logic_vector(255 downto 0); axi_rresp : in std_logic_vector(1 downto 0); axi_rlast : in std_logic; axi_rvalid : in std_logic; axi_rready : out std_logic; --Misc zoom_mode : in std_logic; --0=scale, 1=crop freeze : in std_logic --assert to disable writing ); end framebuffer_ctrl_crop_scale; architecture Behavioral of framebuffer_ctrl_crop_scale is COMPONENT input_line_buffer PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0) ); END COMPONENT; COMPONENT output_line_buffer PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END COMPONENT; signal global_reset : std_logic; signal write_state : natural range 0 to 4; signal write_count : natural range 0 to burst_len-1; signal read_state : natural range 0 to 3; signal input_linebuf_read_high, input_linebuf_write_high, output_linebuf_read_high, output_linebuf_write_high : std_logic_vector(0 downto 0); signal input_read_x, input_write_x, output_read_x, output_write_x : natural range 0 to 4095; signal input_read_y, input_write_y, output_read_y, output_write_y : natural range 0 to 4095; signal input_write_y_curr, input_write_y_last, output_read_y_curr, output_read_y_last : natural range 0 to 4095; signal input_linebuf_write_addr : std_logic_vector(11 downto 0); signal input_linebuf_read_addr : std_logic_vector(9 downto 0); signal output_linebuf_write_addr : std_logic_vector(9 downto 0); signal output_linebuf_read_addr : std_logic_vector(11 downto 0); signal input_linebuf_din : std_logic_vector(63 downto 0); signal input_linebuf_wren : std_logic_vector(0 downto 0); signal input_linebuf_q : std_logic_vector(255 downto 0); signal output_linebuf_din : std_logic_vector(255 downto 0); signal output_linebuf_wren : std_logic_vector(0 downto 0); signal output_linebuf_q : std_logic_vector(63 downto 0); signal fb_read_address : std_logic_vector(23 downto 0); signal fb_write_address : std_logic_vector(23 downto 0); signal output_write_end_x : natural range 0 to 4095; signal axi_wready_last : std_logic; signal input_linebuf_ready : std_logic; --Average two pixels for downscaling purposes function rgb_average(pixel_1, pixel_2 : std_logic_vector) return std_logic_vector is variable pixel_1_t, pixel_2_t : std_logic_vector(23 downto 0); variable sum : unsigned(8 downto 0); variable result : std_logic_vector(23 downto 0); begin pixel_1_t := pixel_1; pixel_2_t := pixel_2; for i in 0 to 2 loop sum := resize(unsigned(pixel_1_t((8*i+7) downto (8*i))), 9) + resize(unsigned(pixel_2_t((8*i+7) downto (8*i))), 9); result((8*i+7) downto (8*i)) := std_logic_vector(sum(8 downto 1)); end loop; return result; end function; begin global_reset <= not axi_resetn; input_linebuf_write_addr <= input_linebuf_write_high & std_logic_vector(to_unsigned(input_write_x, 12)(11 downto 1)); input_linebuf_read_addr <= input_linebuf_read_high & std_logic_vector(to_unsigned(input_read_x, 12)(11 downto 3)); output_linebuf_write_addr <= output_linebuf_write_high & std_logic_vector(to_unsigned(output_write_x, 12)(11 downto 3)); output_linebuf_read_addr <= output_linebuf_read_high & std_logic_vector(to_unsigned(output_read_x, 12)(11 downto 1)); fb_write_address <= std_logic_vector(to_unsigned((input_read_y * input_width) + input_read_x, 24)); fb_read_address <= std_logic_vector(to_unsigned((output_write_y * input_width * 2) + output_write_x, 24)) when zoom_mode = '0' else std_logic_vector(to_unsigned(((output_write_y + crop_yoffset) * input_width) + output_write_x + crop_xoffset, 24)); output_write_end_x <= (output_width * 2) when zoom_mode = '0' else output_width; process(input_clock) begin if rising_edge(input_clock) then if input_vsync = '1' then input_write_x <= 0; input_write_y <= 4095; input_linebuf_write_high <= "1"; elsif input_line_start = '1' then input_write_x <= 0; input_linebuf_write_high <= not input_linebuf_write_high; if input_write_y = 4095 then input_write_y <= 0; else input_write_y <= input_write_y + 1; end if; elsif input_den = '1' then input_write_x <= input_write_x + 2; --2 pixels per clock end if; end if; end process; process(output_clock) begin if rising_edge(output_clock) then if output_vsync = '1' then output_read_x <= 0; output_read_y <= 4095; output_linebuf_read_high <= "1"; elsif output_line_start = '1' then output_read_x <= 0; output_linebuf_read_high <= not output_linebuf_read_high; if output_read_y = 4095 then output_read_y <= 0; else output_read_y <= output_read_y + 1; end if; elsif output_den = '1' then if zoom_mode = '0' then output_read_x <= output_read_x + 2; --2 pixels per clock for downscaling else output_read_x <= output_read_x + 1; end if; end if; end if; end process; process(axi_clock) begin if rising_edge(axi_clock) then input_write_y_curr <= input_write_y; input_write_y_last <= input_write_y_curr; output_read_y_curr <= output_read_y; output_read_y_last <= output_read_y_curr; --Only make changes not during writes/reads if write_state = 0 then --Has write y (i.e. other side) changed? if input_write_y_curr /= input_write_y_last then input_read_x <= 0; end if; input_read_y <= input_write_y_curr - 1; input_linebuf_read_high <= not input_linebuf_write_high; input_linebuf_ready <= '1'; elsif write_state = 3 then if axi_wready = '1' and input_linebuf_ready = '1' then input_read_x <= input_read_x + 8; input_linebuf_ready <= '0'; else input_linebuf_ready <= '1'; end if; else input_linebuf_ready <= '1'; end if; -- if axi_wready = '1' and axi_wready_last = '0' then -- input_linebuf_ready <= '0'; -- else -- input_linebuf_ready <= '1'; -- end if; if read_state = 0 then if output_read_y_curr /= output_read_y_last then output_write_x <= 0; end if; if output_read_y_curr = 4095 then output_write_y <= 0; else output_write_y <= output_read_y_curr + 1; end if; output_linebuf_write_high <= not output_linebuf_read_high; elsif read_state = 2 then if axi_rvalid = '1' then output_write_x <= output_write_x + 8; end if; end if; end if; end process; process(output_linebuf_q, zoom_mode, output_read_x) begin if zoom_mode = '1' then --crop, alternate between LSW and MSW if output_read_x mod 2 = 0 then output_data <= output_linebuf_q(31 downto 8); else output_data <= output_linebuf_q(63 downto 40); end if; else --zoom, average between both pixels output_data <= rgb_average(output_linebuf_q(63 downto 40), output_linebuf_q(31 downto 8)); end if; end process; input_linebuf_din <= input_data_odd & x"00" & input_data_even & x"00"; input_linebuf_wren <= "" & input_den; axi_awaddr <= "0000" & fb_write_address & "00"; axi_araddr <= "0000" & fb_read_address & "00"; --Write state machine process(axi_clock) begin if rising_edge(axi_clock) then axi_wready_last <= axi_wready; if global_reset = '1' then write_state <= 0; write_count <= 0; else case write_state is when 0 => --wait to be able to start writing if input_read_x < input_width and input_read_y < input_height and freeze = '0' then write_state <= 1; end if; when 1 => --assert awvalid, wait for awready if axi_awready = '1' then write_state <= 2; write_count <= 0; end if; when 2 => --begin write write_state <= 3; when 3 => --write in progress if input_linebuf_ready = '1' and axi_wready = '1' then if write_count = burst_len - 1 then write_state <= 4; else write_count <= write_count + 1; end if; end if; when 4 => write_state <= 0; end case; end if; end if; end process; axi_awvalid <= '1' when write_state = 1 else '0'; axi_wvalid <= input_linebuf_ready when write_state = 3 else '0'; axi_wlast <= '1' when write_state = 3 and write_count = burst_len - 1 else '0'; axi_wdata <= input_linebuf_q; --Read state machine process(axi_clock) begin if rising_edge(axi_clock) then if global_reset = '1' then read_state <= 0; else case read_state is when 0 => --wait to be able to start reading if output_write_x < output_write_end_x and output_write_y < output_height then read_state <= 1; end if; when 1 => --assert arvalid, wait for arready if axi_arready = '1' then read_state <= 2; end if; when 2 => --read in progress if axi_rvalid = '1' and axi_rlast = '1' then read_state <= 3; end if; when 3 => read_state <= 0; end case; end if; end if; end process; axi_arvalid <= '1' when read_state = 1 else '0'; output_linebuf_wren <= "1" when ((read_state = 1) or (read_state = 2)) and (axi_rvalid = '1') else "0"; --Split pixels between the two fifos output_linebuf_din <= axi_rdata; inbuf : input_line_buffer port map( clka => input_clock, ena => '1', wea => input_linebuf_wren, addra => input_linebuf_write_addr, dina => input_linebuf_din, clkb => axi_clock, addrb => input_linebuf_read_addr, doutb => input_linebuf_q ); outbuf : output_line_buffer port map( clka => axi_clock, ena => '1', wea => output_linebuf_wren, addra => output_linebuf_write_addr, dina => output_linebuf_din, clkb => output_clock, addrb => output_linebuf_read_addr, doutb => output_linebuf_q ); --Hardwired AXI4 signals (useful) axi_awlen <= std_logic_vector(to_unsigned(burst_len - 1, 8)); --burst len of 16 transfers (128 32-bit words) axi_arlen <= std_logic_vector(to_unsigned(burst_len - 1, 8)); axi_awsize <= "010"; --not sure about this - AXI4 spec does not consider 256-bit datapath axi_arsize <= "010"; axi_awburst <= "01"; --INCR burst type axi_arburst <= "01"; axi_rready <= '1'; --we're always ready axi_bready <= '1'; axi_wstrb <= (others => '1'); --all data bytes always valid axi_awid <= "0"; axi_arid <= "1"; --Hardwired AXI4 signals (useless) axi_awlock <= "0"; axi_awcache <= "0011"; axi_awprot <= "000"; axi_awqos <= "0000"; axi_arlock <= "0"; axi_arcache <= "0011"; axi_arprot <= "000"; axi_arqos <= "0000"; end Behavioral; ================================================ FILE: vhdl_rx/framebuffer-ctrl/input_line_buffer.xci ================================================ xilinx.com xci unknown 1.0 input_line_buffer 4096 12 10 1 4 0 1 9 0 1 7 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 36.714252 mW kintex7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 input_line_buffer.mem no_coe_file_loaded 0 0 1 0 1 4096 1024 64 256 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 4096 1024 NO_CHANGE WRITE_FIRST 64 256 kintex7 4 Memory_Slave AXI4_Full false Minimum_Area false 9 NONE no_coe_file_loaded ALL input_line_buffer false false false false false false false false false Use_ENA_Pin Always_Enabled Single_Bit_Error_Injection false Native false no_mem_loaded Simple_Dual_Port_RAM NO_CHANGE WRITE_FIRST 0 0 BRAM 0 100 100 50 100 100 0 8kx2 false false 64 256 false false false false 0 false false CE CE SYNC false false false false false false false 4096 64 256 No_ECC false false false Stand_Alone kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 4 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/framebuffer-ctrl/output_line_buffer.xci ================================================ xilinx.com xci unknown 1.0 output_line_buffer 4096 10 12 1 4 0 1 9 0 1 7 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 33.580152 mW kintex7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 output_line_buffer.mem no_coe_file_loaded 0 0 1 0 1 1024 4096 256 64 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 1024 4096 NO_CHANGE WRITE_FIRST 256 64 kintex7 4 Memory_Slave AXI4_Full false Minimum_Area false 9 NONE no_coe_file_loaded ALL output_line_buffer false false false false false false false false false Use_ENA_Pin Always_Enabled Single_Bit_Error_Injection false Native false no_mem_loaded Simple_Dual_Port_RAM NO_CHANGE WRITE_FIRST 0 0 BRAM 0 100 100 50 100 100 0 8kx2 false false 256 64 false false false false 0 false false CE CE SYNC false false false false false false false 1024 256 64 No_ECC false false false Stand_Alone kintex7 xc7k325t ffg900 VERILOG MIXED -2 TRUE TRUE IP_Flow 4 TRUE . . 2016.3 OUT_OF_CONTEXT ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_10bit_unpack.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --MIPI CSI-2 10bit pixel unpacker --Copyright (C) 2016 David Shah --Licensed under the MIT License --This receives 32-bit words from the long video packet payload in; and unpacks them --into 40 bits of output (which is only active - signified with the 'dout_valid' output - --80% of the time). It is intended that the dout_valid signal drives the write enable for a linebuffer --or FIFO. --At the moment only MIPI 10bit RAW format is supported, other formats may be --supported in the future (for 8bit you could simply bypass this entity) entity csi_rx_10bit_unpack is Port ( clock : in STD_LOGIC; --word clock in reset : in STD_LOGIC; --synchronous active high reset enable : in STD_LOGIC; --active high enable data_in : in STD_LOGIC_VECTOR (31 downto 0); --packet payload in din_valid : in STD_LOGIC; --payload in valid data_out : out STD_LOGIC_VECTOR (39 downto 0); --unpacked data out dout_valid : out STD_LOGIC); --data out valid (see above) end csi_rx_10bit_unpack; architecture Behavioral of csi_rx_10bit_unpack is signal dout_int : std_logic_vector(39 downto 0); signal bytes_int : std_logic_vector(31 downto 0); signal byte_count_int : integer range 0 to 4; signal dout_valid_int : std_logic; signal dout_unpacked : std_logic_vector(39 downto 0); signal dout_valid_up : std_logic; --Unpack CSI packed 10-bit to 4 sequential 10-bit pixels function mipi_unpack(packed : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(39 downto 0); begin result(9 downto 0) := packed(7 downto 0) & packed(33 downto 32); result(19 downto 10) := packed(15 downto 8) & packed(35 downto 34); result(29 downto 20) := packed(23 downto 16) & packed(37 downto 36); result(39 downto 30) := packed(31 downto 24) & packed(39 downto 38); return result; end mipi_unpack; begin process(clock, reset) begin if rising_edge(clock) then if reset = '1' then dout_int <= x"0000000000"; byte_count_int <= 0; dout_valid_int <= '0'; elsif enable = '1' then if din_valid = '1' then --Behaviour is based on the number of bytes in the buffer case byte_count_int is when 0 => dout_int <= x"0000000000"; dout_valid_int <= '0'; bytes_int <= data_in; byte_count_int <= 4; when 1 => dout_int <= data_in & bytes_int(7 downto 0); dout_valid_int <= '1'; bytes_int <= x"00000000"; byte_count_int <= 0; when 2 => dout_int <= data_in(23 downto 0) & bytes_int(15 downto 0); dout_valid_int <= '1'; bytes_int <= x"000000" & data_in(31 downto 24); byte_count_int <= 1; when 3 => dout_int <= data_in(15 downto 0) & bytes_int(23 downto 0); dout_valid_int <= '1'; bytes_int <= x"0000" & data_in(31 downto 16); byte_count_int <= 2; when 4 => dout_int <= data_in(7 downto 0) & bytes_int(31 downto 0); dout_valid_int <= '1'; bytes_int <= x"00" & data_in(31 downto 8); byte_count_int <= 3; end case; else byte_count_int <= 0; dout_valid_int <= '0'; end if; dout_unpacked <= mipi_unpack(dout_int); dout_valid_up <= dout_valid_int; data_out <= dout_unpacked; dout_valid <= dout_valid_up; end if; end if; end process; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_4_lane_link.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; --MIPI CSI-2 Rx 4 lane link layer --Copyright (C) 2016 David Shah --Licensed under the MIT License --This combines the clock and data PHYs; byte aligners and word aligner to --form the lower levels of the CSI Rx link layer entity csi_rx_4_lane_link is generic( fpga_series : string := "7SERIES"; dphy_term_en : boolean := true; d0_invert : boolean := false; d1_invert : boolean := false; d2_invert : boolean := false; d3_invert : boolean := false; d0_skew : natural := 0; d1_skew : natural := 0; d2_skew : natural := 0; d3_skew : natural := 0; generate_idelayctrl : boolean := false ); port( dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --clock lane (1 is P, 0 is N) dphy_d0 : in STD_LOGIC_VECTOR (1 downto 0); --data lanes (1 is P, 0 is N) dphy_d1 : in STD_LOGIC_VECTOR (1 downto 0); dphy_d2 : in STD_LOGIC_VECTOR (1 downto 0); dphy_d3 : in STD_LOGIC_VECTOR (1 downto 0); ref_clock : in STD_LOGIC; --reference clock for clock detection and IDELAYCTRLs (nominally ~200MHz) reset : in STD_LOGIC; --active high synchronous reset in enable : in STD_LOGIC; --active high enable out wait_for_sync : in STD_LOGIC; --sync wait signal from packet handler packet_done : in STD_LOGIC; --packet done signal from packet handler reset_out : out STD_LOGIC; --reset output based on clock detection word_clock : out STD_LOGIC; --divided word clock output word_data : out STD_LOGIC_VECTOR (31 downto 0); --aligned word data output word_valid : out STD_LOGIC --whether or not above data is synced and aligned ); end csi_rx_4_lane_link; architecture Behavioral of csi_rx_4_lane_link is signal ddr_bit_clock : std_logic; signal ddr_bit_clock_b : std_logic; signal word_clock_int : std_logic; signal serdes_reset : std_logic; signal deser_data : std_logic_vector(31 downto 0); signal deser_data_rev : std_logic_vector(31 downto 0); signal byte_align_data : std_logic_vector(31 downto 0); signal byte_valid : std_logic_vector(3 downto 0); signal word_align_data : std_logic_vector(31 downto 0); signal byte_packet_done : std_logic; begin clkphy : entity work.csi_rx_hs_clk_phy generic map( series => fpga_series, term_en => dphy_term_en) port map( dphy_clk => dphy_clk, reset => reset, ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int); clkdet : entity work.csi_rx_clock_det port map( ref_clock => ref_clock, ext_clock => word_clock_int, enable => enable, reset_in => reset, reset_out => serdes_reset); d0phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d0_invert, term_en => dphy_term_en, delay => d0_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d0, deser_out => deser_data(7 downto 0)); d1phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d1_invert, term_en => dphy_term_en, delay => d1_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d1, deser_out => deser_data(15 downto 8)); d2phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d2_invert, term_en => dphy_term_en, delay => d2_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d2, deser_out => deser_data(23 downto 16)); d3phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d3_invert, term_en => dphy_term_en, delay => d3_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d3, deser_out => deser_data(31 downto 24)); gen_bytealign : for i in 0 to 3 generate ba : entity work.csi_rx_byte_align port map ( clock => word_clock_int, reset => serdes_reset, enable => enable, deser_in => deser_data((8*i) + 7 downto 8 * i), wait_for_sync => wait_for_sync, packet_done => byte_packet_done, valid_data => byte_valid(i), data_out => byte_align_data((8*i) + 7 downto 8 * i)); end generate; wordalign : entity work.csi_rx_word_align port map ( word_clock => word_clock_int, reset => serdes_reset, enable => enable, packet_done => packet_done, wait_for_sync => wait_for_sync, packet_done_out => byte_packet_done, word_in => byte_align_data, valid_in => byte_valid, word_out => word_align_data, valid_out => word_valid); word_clock <= word_clock_int; word_data <= word_align_data; reset_out <= serdes_reset; gen_idctl : if generate_idelayctrl generate idctrl : entity work.csi_rx_idelayctrl_gen port map( ref_clock => ref_clock, reset => reset); end generate; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_byte_align.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --MIPI CSI-2 byte aligner --Copyright (C) 2016 David Shah --Licensed under the MIT License --This receives raw, unaligned bytes (which could contain part of two actual bytes) --from the SERDES and aligns them by looking for the D-PHY sync pattern --When wait_for_sync is high the entity will wait until it sees the valid header at some alignment, --at which point the found alignment is locked until packet_done is asserted --valid_data is asserted as soon as the sync pattern is found, so the next byte --contains the CSI packet header --In reality to avoid false triggers we must look for a valid sync pattern on all 4 lanes, --if this does not occur the word aligner (a seperate entity) will assert packet_done immediately entity csi_rx_byte_align is port ( clock : in STD_LOGIC; --byte clock in reset : in STD_LOGIC; --synchronous active high reset enable : in STD_LOGIC; --active high enable deser_in : in STD_LOGIC_VECTOR (7 downto 0); --raw data from ISERDES wait_for_sync : in STD_LOGIC; --when high will look for a sync pattern if sync not already found packet_done : in STD_LOGIC; --assert to reset synchronisation status valid_data : out STD_LOGIC; --goes high as soon as sync pattern is found (so data out on next cycle contains header) data_out : out STD_LOGIC_VECTOR (7 downto 0)); --aligned data out, typically delayed by 2 cycles end csi_rx_byte_align; architecture Behavioral of csi_rx_byte_align is signal curr_byte : std_logic_vector(7 downto 0); signal last_byte : std_logic_vector(7 downto 0); signal shifted_byte : std_logic_vector(7 downto 0); signal found_hdr : std_logic; signal valid_data_int : std_logic; signal hdr_offs : unsigned(2 downto 0); signal data_offs : unsigned(2 downto 0); begin process(clock) begin if rising_edge(clock) then if reset = '1' then valid_data_int <= '0'; elsif enable = '1' then last_byte <= curr_byte; curr_byte <= deser_in; data_out <= shifted_byte; if packet_done = '1' then valid_data_int <= found_hdr; elsif wait_for_sync = '1' and found_hdr = '1' and valid_data_int = '0' then valid_data_int <= '1'; data_offs <= hdr_offs; end if; end if; end if; end process; valid_data <= valid_data_int; --This assumes that data is arranged correctly (chronologically last bit in MSB) --and looks for the "10111000" sync sequence process(curr_byte, last_byte) constant sync : std_logic_vector(7 downto 0) := "10111000"; variable was_found : boolean := false; variable offset : integer range 0 to 7; begin offset := 0; was_found := false; for i in 0 to 7 loop if (curr_byte(i downto 0) & last_byte(7 downto i + 1) = sync) and (unsigned(last_byte(i downto 0)) = 0) then was_found := true; offset := i; end if; end loop; if was_found then found_hdr <= '1'; hdr_offs <= to_unsigned(offset, 3); else found_hdr <= '0'; hdr_offs <= "000"; end if; end process; --This aligns the data correctly shifted_byte <= curr_byte when data_offs = 7 else curr_byte(6 downto 0) & last_byte(7 downto 7) when data_offs = 6 else curr_byte(5 downto 0) & last_byte(7 downto 6) when data_offs = 5 else curr_byte(4 downto 0) & last_byte(7 downto 5) when data_offs = 4 else curr_byte(3 downto 0) & last_byte(7 downto 4) when data_offs = 3 else curr_byte(2 downto 0) & last_byte(7 downto 3) when data_offs = 2 else curr_byte(1 downto 0) & last_byte(7 downto 2) when data_offs = 1 else curr_byte(0 downto 0) & last_byte(7 downto 1); end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_clock_det.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Simple Clock Detector for CSI-2 Rx --Copyright (C) 2016 David Shah --Licensed under the MIT License --This is designed to hold the ISERDES in reset until at least 3 byte clock --cycles have been detected; to ensure proper ISERDES behaviour --It will reassert reset once the byte clock has not toggled compared to the reference clock --for at least 200 reference clock cycles entity csi_rx_clock_det is port ( ref_clock : in std_logic; --reference clock in; must not be synchronised to ext_clock ext_clock : in STD_LOGIC; --external byte clock input for detection enable : in STD_LOGIC; --active high enable reset_in : in STD_LOGIC; --active high asynchronous reset in reset_out : out STD_LOGIC); --active high reset out to ISERDESs end csi_rx_clock_det; architecture Behavioral of csi_rx_clock_det is signal count_value : unsigned(3 downto 0); signal clk_fail : std_logic; signal ext_clk_lat : std_logic; signal last_ext_clk : std_logic; signal clk_fail_count : unsigned(7 downto 0); begin process(ext_clock, reset_in, clk_fail) begin if reset_in = '1' or clk_fail = '1' then count_value <= x"0"; elsif rising_edge(ext_clock) then if enable = '1' then if count_value < 3 then count_value <= count_value + 1; end if; end if; end if; end process; --Reset in between frames, by detecting the loss of the high speed clock process(ref_clock) begin if rising_edge(ref_clock) then ext_clk_lat <= ext_clock; last_ext_clk <= ext_clk_lat; if last_ext_clk /= ext_clk_lat then clk_fail_count <= (others => '0'); else if clk_fail_count < 250 then clk_fail_count <= clk_fail_count + 1; end if; end if; end if; end process; clk_fail <= '1' when clk_fail_count >= 200 else '0'; reset_out <= '0' when count_value >= 2 else '1'; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_hdr_ecc.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; --MIPI CSI-2 Header ECC calculation --Copyright (C) 2016 David Shah --Licensed under the MIT License entity csi_rx_hdr_ecc is Port ( data : in STD_LOGIC_VECTOR (23 downto 0); ecc : out STD_LOGIC_VECTOR (7 downto 0)); end csi_rx_hdr_ecc; architecture Behavioral of csi_rx_hdr_ecc is begin ecc(7) <= '0'; ecc(6) <= '0'; ecc(5) <= data(10) xor data(11) xor data(12) xor data(13) xor data(14) xor data(15) xor data(16) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(23); ecc(4) <= data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(9) xor data(16) xor data(17) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23); ecc(3) <= data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(15) xor data(19) xor data(20) xor data(21) xor data(23); ecc(2) <= data(0) xor data(2) xor data(3) xor data(5) xor data(6) xor data(9) xor data(11) xor data(12) xor data(15) xor data(18) xor data(20) xor data(21) xor data(22); ecc(1) <= data(0) xor data(1) xor data(3) xor data(4) xor data(6) xor data(8) xor data(10) xor data(12) xor data(14) xor data(17) xor data(20) xor data(21) xor data(22) xor data(23); ecc(0) <= data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(7) xor data(10) xor data(11) xor data(13) xor data(16) xor data(20) xor data(21) xor data(22) xor data(23); end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_hs_clk_phy.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; --High-Speed D-PHY clock RX PHY for MIPI CSI-2 Rx core --Copyright (C) 2016 David Shah --Licensed under the MIT License -- This receives the input clock and produces both real and complement DDR bit -- clocks and an SDR (i.e. in/4) byte clock for the SERDES and other downstream devices entity csi_rx_hs_clk_phy is generic ( series : string := "7SERIES"; --FPGA series, 7SERIES or VIRTEX6 term_en : boolean := true ); port ( dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --D-PHY clock input; 1 is P, 0 is N reset : in STD_LOGIC; --reset input for BUFR ddr_bit_clock : out STD_LOGIC; --DDR bit clock (i.e. input clock buffered) out ddr_bit_clock_b : out STD_LOGIC; --Inverted DDR bit clock out byte_clock : out STD_LOGIC --SDR byte clock (i.e. input clock / 4) out ); end csi_rx_hs_clk_phy; architecture Behavioral of csi_rx_hs_clk_phy is signal bit_clock_int_pre : std_logic; signal bit_clock_int : std_logic; signal bit_clock_b_int : std_logic; signal byte_clock_int : std_logic; begin iclkdbuf : IBUFDS generic map ( DIFF_TERM => term_en, IBUF_LOW_PWR => FALSE, IOSTANDARD => "DEFAULT" ) port map( O => bit_clock_int_pre, I => dphy_clk(1), IB => dphy_clk(0) ); iclkbufio: BUFIO port map ( O => bit_clock_int, I => bit_clock_int_pre ); bit_clock_b_int <= NOT bit_clock_int; clkdiv : BUFR generic map ( BUFR_DIVIDE => "4", SIM_DEVICE => series ) port map ( O => byte_clock_int, CE => '1', CLR => reset, I => bit_clock_int_pre ); ddr_bit_clock <= bit_clock_int; ddr_bit_clock_b <= bit_clock_b_int; byte_clock <= byte_clock_int; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_hs_lane_phy.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; --High-Speed D-PHY lane RX PHY for MIPI CSI-2 Rx core --Copyright (C) 2016 David Shah --Licensed under the MIT License --This entity handles input skew compensation and deserialisation for the --CSI data input lanes. Output is has arbitrary alignment which must be fixed later on --in the processing chain entity csi_rx_hs_lane_phy is generic( series : string := "7SERIES"; --FPGA series, 7SERIES or VIRTEX6 invert : boolean := false; --Whether or not to invert output (i.e. if pairs are swapped) term_en : boolean := true; --Whether or not to enable internal input termination delay : natural --IDELAY delay value for skew compensation ); port ( ddr_bit_clock : in STD_LOGIC; --true and complement DDR bit clocks, buffered from D-PHY clock ddr_bit_clock_b : in STD_LOGIC; byte_clock : in STD_LOGIC; --byte clock; i.e. input clock /4 enable : in STD_LOGIC; --active high enable for SERDES reset : in STD_LOGIC; --reset, latched internally to byte clock dphy_hs : in STD_LOGIC_VECTOR (1 downto 0); --lane input, 1 is P, 0 is N deser_out : out STD_LOGIC_VECTOR (7 downto 0) --deserialised byte output ); end csi_rx_hs_lane_phy; architecture Behavioral of csi_rx_hs_lane_phy is signal reset_lat : std_logic; --reset synchronised to byte clock signal in_se : std_logic; --input after differential buffer signal in_delayed : std_logic; --input after deskew --for Virtex-6 devices where we cascade two ISERDESs signal shift_1 : std_logic; signal shift_2 : std_logic; signal serdes_out_int : std_logic_vector(7 downto 0); begin process(byte_clock) begin if rising_edge(byte_clock) then reset_lat <= reset; end if; end process; inbuf : IBUFDS generic map( DIFF_TERM => term_en, IBUF_LOW_PWR => FALSE, IOSTANDARD => "DEFAULT") port map( O => in_se, I => dphy_hs(1), IB => dphy_hs(0)); --7 series specific blocks gen_7s : if series = "7SERIES" generate indelay : IDELAYE2 generic map ( CINVCTRL_SEL => "FALSE", DELAY_SRC => "IDATAIN", HIGH_PERFORMANCE_MODE => "TRUE", IDELAY_TYPE => "FIXED", IDELAY_VALUE => delay, REFCLK_FREQUENCY => 200.0, SIGNAL_PATTERN => "DATA", PIPE_SEL => "FALSE" ) port map ( DATAOUT => in_delayed, DATAIN => '0', C => byte_clock, CE => '0', INC => '0', IDATAIN => in_se, CNTVALUEIN => "00000", CNTVALUEOUT => open, CINVCTRL => '0', LD => '0', LDPIPEEN => '0', REGRST => '0' ); ideser : ISERDESE2 generic map ( DATA_RATE => "DDR", DATA_WIDTH => 8, DYN_CLKDIV_INV_EN => "FALSE", DYN_CLK_INV_EN => "FALSE", INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "NETWORKING", IOBDELAY => "IFD", NUM_CE => 1, OFB_USED => "FALSE", SERDES_MODE => "MASTER", SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, --In the ISERDESE2, Q8 is the oldest bit but in the CSI spec --the MSB is the most recent bit. So we mirror the output Q1 => serdes_out_int(7), Q2 => serdes_out_int(6), Q3 => serdes_out_int(5), Q4 => serdes_out_int(4), Q5 => serdes_out_int(3), Q6 => serdes_out_int(2), Q7 => serdes_out_int(1), Q8 => serdes_out_int(0), SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', CE1 => enable, CE2 => '1', CLKDIVP => '0', CLK => ddr_bit_clock, CLKB => ddr_bit_clock_b, CLKDIV => byte_clock, OCLK => '0', DYNCLKDIVSEL => '0', DYNCLKSEL => '0', D => '0', DDLY => in_delayed, OFB => '0', OCLKB => '0', RST => reset_lat, SHIFTIN1 => '0', SHIFTIN2 => '0' ); end generate; --Legacy Virtex-6 specific blocks gen_v6 : if series = "VIRTEX6" generate --Input delay for skew compensation indelay : IODELAYE1 generic map ( CINVCTRL_SEL => FALSE, DELAY_SRC => "I", HIGH_PERFORMANCE_MODE => TRUE, IDELAY_TYPE => "FIXED", IDELAY_VALUE => delay, ODELAY_TYPE => "FIXED", ODELAY_VALUE => 0, REFCLK_FREQUENCY => 200.0, SIGNAL_PATTERN => "DATA" ) port map ( DATAOUT => in_delayed, DATAIN => '0', C => byte_clock, CE => '0', INC => '0', IDATAIN => in_se, ODATAIN => '0', RST => '0', T => '1', CNTVALUEIN => "00000", CNTVALUEOUT => open, CLKIN => '0', CINVCTRL => '0' ); --Input deserialisation ideser1 : ISERDESE1 generic map ( DATA_RATE => "DDR", DATA_WIDTH => 8, DYN_CLKDIV_INV_EN => FALSE, DYN_CLK_INV_EN => FALSE, INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "NETWORKING", IOBDELAY => "IFD", NUM_CE => 2, OFB_USED => FALSE, SERDES_MODE => "MASTER", SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0' ) port map( O => open, Q1 => serdes_out_int(7), Q2 => serdes_out_int(6), Q3 => serdes_out_int(5), Q4 => serdes_out_int(4), Q5 => serdes_out_int(3), Q6 => serdes_out_int(2), SHIFTOUT1 => shift_1, SHIFTOUT2 => shift_2, BITSLIP => '0', CE1 => enable, CE2 => enable, CLK => ddr_bit_clock, CLKB => ddr_bit_clock_b, CLKDIV => byte_clock, D => '0', DDLY => in_delayed, DYNCLKDIVSEL => '0', DYNCLKSEL => '0', OCLK => '0', OFB => '0', RST => reset_lat, SHIFTIN1 => '0', SHIFTIN2 => '0'); ideser2 : ISERDESE1 generic map ( DATA_RATE => "DDR", DATA_WIDTH => 8, DYN_CLKDIV_INV_EN => FALSE, DYN_CLK_INV_EN => FALSE, INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "NETWORKING", IOBDELAY => "IFD", NUM_CE => 2, OFB_USED => FALSE, SERDES_MODE => "SLAVE", SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0' ) port map( O => open, Q1 => open, Q2 => open, Q3 => serdes_out_int(1), Q4 => serdes_out_int(0), Q5 => open, Q6 => open, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', CE1 => enable, CE2 => enable, CLK => ddr_bit_clock, CLKB => ddr_bit_clock_b, CLKDIV => byte_clock, D => '0', DDLY => '0', DYNCLKDIVSEL => '0', DYNCLKSEL => '0', OCLK => '0', OFB => '0', RST => reset_lat, SHIFTIN1 => shift_1, SHIFTIN2 => shift_2); end generate; --Inversion of output based on generic gen_true : if not invert generate deser_out <= serdes_out_int; end generate; gen_inv : if invert generate deser_out <= not serdes_out_int; end generate; end architecture; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_idelayctrl_gen.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; --Core-specific IDELAYCTRL wrapper --Copyright (C) 2016 David Shah --Licensed under the MIT License entity csi_rx_idelayctrl_gen is generic( fpga_series : string := "7SERIES" ); port( ref_clock : in std_logic; --IDELAYCTRL reference clock reset : in std_logic --IDELAYCTRL reset ); end csi_rx_idelayctrl_gen; architecture Behavioral of csi_rx_idelayctrl_gen is begin gen_v6_7s: if fpga_series = "VIRTEX6" or fpga_series = "7SERIES" generate delayctrl : IDELAYCTRL port map ( RDY => open, REFCLK => ref_clock, RST => reset ); end generate; end architecture; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_line_buffer.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --MIPI CSI-2 Rx Line Buffer --Copyright (C) 2016 David Shah --Licensed under the MIT License entity csi_rx_line_buffer is generic( line_width : natural := 3840; --width of a single line pixels_per_clock : natural := 2 --number of pixels output every clock cycle; either 1, 2 or 4 ); port( write_clock : in std_logic; write_addr : in natural range 0 to (line_width / 4) - 1; write_data : in std_logic_vector(39 downto 0); --write port is always 4 pixels wide write_en : in std_logic; read_clock : in std_logic; read_addr : in natural range 0 to (line_width / pixels_per_clock) - 1; read_q : out std_logic_vector((10 * pixels_per_clock) - 1 downto 0) ); end csi_rx_line_buffer; architecture Behavioral of csi_rx_line_buffer is type linebuf_t is array(0 to (line_width / 4) - 1) of std_logic_vector(39 downto 0); signal linebuf : linebuf_t; signal linebuf_read_address : natural range 0 to (line_width / 4) - 1; signal read_address_lat : natural range 0 to (line_width / pixels_per_clock) - 1; signal linebuf_read_q : std_logic_vector(39 downto 0); begin process(write_clock) begin if rising_edge(write_clock) then if write_en = '1' then linebuf(write_addr) <= write_data; end if; end if; end process; process(read_clock) begin if rising_edge(read_clock) then read_address_lat <= read_addr; linebuf_read_q <= linebuf(linebuf_read_address); end if; end process; sppc : if pixels_per_clock = 1 generate linebuf_read_address <= read_addr / 4; read_q <= linebuf_read_q(9 downto 0) when read_address_lat mod 4 = 0 else linebuf_read_q(19 downto 10) when read_address_lat mod 4 = 1 else linebuf_read_q(29 downto 20) when read_address_lat mod 4 = 2 else linebuf_read_q(39 downto 30); end generate; dppc : if pixels_per_clock = 2 generate linebuf_read_address <= read_addr / 2; read_q <= linebuf_read_q(19 downto 0) when read_address_lat mod 2 = 0 else linebuf_read_q(39 downto 20); end generate; qppc : if pixels_per_clock = 4 generate linebuf_read_address <= read_addr; read_q <= linebuf_read_q; end generate; end architecture; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_packet_handler.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --MIPI CSI-2 Rx Packet Handler --Copyright (C) 2016 David Shah --Licensed under the MIT License --This controls the wait_for_sync and packet_done inputs to the byte/word aligners; --receives aligned words and processes them --It keeps track of whether or not we are currently in a video line or frame; --and pulls the video payload out of long packets of the correct type entity csi_rx_packet_handler is Port ( clock : in STD_LOGIC; --word clock in reset : in STD_LOGIC; --asynchronous active high reset enable : in STD_LOGIC; --active high enable data : in STD_LOGIC_VECTOR (31 downto 0); --data in from word aligner data_valid : in STD_LOGIC; --data valid in from word aligner sync_wait : out STD_LOGIC; --drives byte and word aligner wait_for_sync packet_done : out STD_LOGIC; --drives word aligner packet_done payload_out : out STD_LOGIC_VECTOR(31 downto 0); --payload out from long video packets payload_valid : out STD_LOGIC; --whether or not payload output is valid (i.e. currently receiving a long packet) vsync_out : out STD_LOGIC; --vsync output to timing controller in_frame : out STD_LOGIC; --whether or not currently in video frame (i.e. got FS but not FE) in_line : out STD_LOGIC); --whether or not receiving video line end csi_rx_packet_handler; architecture Behavioral of csi_rx_packet_handler is signal is_hdr : std_logic; signal packet_type : std_logic_vector(7 downto 0); signal long_packet : std_logic; signal packet_len : unsigned(15 downto 0); signal packet_len_q : unsigned(15 downto 0) := x"0000"; signal state : std_logic_vector(2 downto 0) := "000"; signal bytes_read : unsigned(15 downto 0); signal in_frame_d : std_logic; signal in_line_d : std_logic; signal valid_packet : std_logic; signal packet_for_ecc : std_logic_vector(23 downto 0); signal expected_ecc : std_logic_vector(7 downto 0); function is_allowed_type(packet_type : std_logic_vector) return std_logic is variable result : std_logic; variable packet_type_temp : std_logic_vector(7 downto 0); begin packet_type_temp := packet_type; --keep GHDL happy case packet_type_temp is when x"00" | x"01" | x"02" | x"03" => --sync result := '1'; when x"10" | x"11" | x"12" => --non image result := '1'; when x"28" | x"29" | x"2A" | x"2B" | x"2C" | x"2D" => --RAW result := '1'; when others => result := '0'; end case; return result; end is_allowed_type; begin --Main state machine process process(reset, clock) begin if rising_edge(clock) then if reset = '1' then state <= "000"; elsif enable = '1' then case state is when "000" => --waiting to init state <= "001"; when "001" => --waiting for start bytes_read <= x"0000"; if data_valid = '1' then packet_len_q <= packet_len; if long_packet = '1' then state <= "010"; else state <= "011"; end if; end if; when "010" => --rx long packet if (bytes_read < (packet_len_q - 4)) and(bytes_read < 8192) then bytes_read <= bytes_read + 4; else state <= "011"; end if; when "011" => --packet done, assert packet_done state <= "100"; when "100" => --wait one cycle and reset state <= "001"; when others => state <= "000"; end case; end if; end if; end process; --At the moment we only calculate the expected ECC and compare it to the received ECC, --rejecting the packet if this fails. In the future it would be better to also correct --single bit errors ecc : entity work.csi_rx_hdr_ecc port map( data => packet_for_ecc, ecc => expected_ecc); packet_type <= "00" & data(5 downto 0); valid_packet <= '1' when (data(31 downto 24) = expected_ecc) and (is_allowed_type(packet_type) = '1') and (data(7 downto 6) = "00") else '0'; is_hdr <= '1' when data_valid = '1' and state = "001" else '0'; long_packet <= '1' when (packet_type > x"0F") and (valid_packet = '1') else '0'; vsync_out <= '1' when is_hdr = '1' and packet_type = x"00" else '0'; packet_for_ecc <= data(23 downto 0); packet_len <= unsigned(data(23 downto 8)); process(reset, clock) begin if rising_edge(clock) then if reset = '1' then in_frame_d <= '0'; in_line_d <= '0'; elsif enable = '1' then if is_hdr = '1' and packet_type = x"00" and valid_packet = '1' then --FS in_frame_d <= '1'; elsif is_hdr = '1' and packet_type = x"01" and valid_packet = '1' then --FE in_frame_d <= '0'; end if; if is_hdr = '1' and (packet_type(7 downto 4) = x"2") and valid_packet = '1' then in_line_d <= '1'; elsif state /= "010" and state /= "001" then in_line_d <= '0'; end if; end if; end if; end process; in_frame <= in_frame_d; in_line <= in_line_d; sync_wait <= '1' when state = "001" else '0'; packet_done <= '1' when state = "011" else '0'; payload_out <= data when state = "010" else x"00000000"; payload_valid <= '1' when state = "010" else '0'; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_top.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --VHDL MIPI CSI-2 Rx designed for Xilinx 7-series FPGAs --Copyright (C) 2016 David Shah --Licensed under the MIT License --This driver is designed for 4 lane links and has been tested with the Omnivison OV13850 --It supports resolutions up to 4k at 30fps (higher has not been tested but may work) with --10-bit Bayer data (support for other output formats is not yet implemented). This is output --in traditional parallel video format with a few tweaks --For improved timing performance up to 4 pixels per clock can be output. For the ease of debayering blocks, --the previous line's data; and whether the current line is even (BGBG) or odd (GRGR) is also output. --At minimum you will need to provide it with suitable clocks from a PLL (the pixel clock input --should in general either be phase locked to the master clock input to the camera or the CSI byte clock) --and configure skew parameters and video port timings for your camera setup --The primary testing platform is a Digilent Genesys 2 (Kintex-7 XC7K325T) with a --custom FMC breakout board to connect two Firefly OV13850 modules. --A previous version has also been tested on a ML605 Virtex-6 development board; --however functioning support is not guaranteed entity csi_rx_4lane is generic ( --FPGA series to control SERDES/buffer generation --either "VIRTEX6" or "7SERIES" fpga_series : string := "7SERIES"; --Low-level PHY parameters dphy_term_en : boolean := true; --Enable internal termination on all pairs --Use these to invert channels if needed on your PCB d0_invert : boolean := false; d1_invert : boolean := false; d2_invert : boolean := false; d3_invert : boolean := false; --These skew values are the delay settings for the IDELAYs on each lane --Adjust these for optimum stability with your PCB layout and cameras d0_skew : natural := 0; d1_skew : natural := 0; d2_skew : natural := 0; d3_skew : natural := 0; --Output port pixel timings (for included OV13850 config at 23.98fps with MCLK 24.399MHz and output clock 145Mz) video_hlength : natural := 4041; --total visible and blanking pixels per line video_vlength : natural := 2992; --total visible and blanking lines per frame video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync video_hsync_len : natural := 48; --horizontal sync length in pixels video_hbp_len : natural := 122; --horizontal back porch length (excluding sync) video_h_visible : natural := 3840; --number of visible pixels per line video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync video_vsync_len : natural := 3; --vertical sync length in lines video_vbp_len : natural := 23; --vertical back porch length (excluding sync) video_v_visible : natural := 2160; --number of visible lines per frame pixels_per_clock : natural := 2; --Number of pixels per clock to output; 1, 2 or 4 --Set this to false if this is not the first CSI rx or other IDELAY using device in the system generate_idelayctrl : boolean := false ); port( ref_clock_in : in std_logic; --IDELAY reference clock (nominally 200MHz) pixel_clock_in : in std_logic; --Output pixel clock from PLL byte_clock_out : out std_logic; --DSI byte clock output enable : in std_logic; --system enable input reset : in std_logic; --synchronous active high reset input video_valid : out std_logic; --goes high when valid frames are being received --DSI signals, signal 1 is P and signal 0 is N dphy_clk : in std_logic_vector(1 downto 0); dphy_d0 : in std_logic_vector(1 downto 0); dphy_d1 : in std_logic_vector(1 downto 0); dphy_d2 : in std_logic_vector(1 downto 0); dphy_d3 : in std_logic_vector(1 downto 0); --Pixel data output video_hsync : out std_logic; video_vsync : out std_logic; video_den : out std_logic; video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use ); end csi_rx_4lane; architecture Behavioral of csi_rx_4lane is signal csi_byte_clock : std_logic; signal link_reset_out : std_logic; signal wait_for_sync : std_logic; signal packet_done : std_logic; signal word_clock : std_logic; signal word_data : std_logic_vector(31 downto 0); signal word_valid : std_logic; signal packet_payload : std_logic_vector(31 downto 0); signal packet_payload_valid : std_logic; signal csi_vsync : std_logic; signal csi_in_frame, csi_in_line : std_logic; signal unpack_data : std_logic_vector(39 downto 0); signal unpack_data_valid : std_logic; begin link : entity work.csi_rx_4_lane_link generic map( fpga_series => fpga_series, dphy_term_en => dphy_term_en, d0_invert => d0_invert, d1_invert => d1_invert, d2_invert => d2_invert, d3_invert => d3_invert, d0_skew => d0_skew, d1_skew => d1_skew, d2_skew => d2_skew, d3_skew => d3_skew, generate_idelayctrl => generate_idelayctrl) port map( dphy_clk => dphy_clk, dphy_d0 => dphy_d0, dphy_d1 => dphy_d1, dphy_d2 => dphy_d2, dphy_d3 => dphy_d3, ref_clock => ref_clock_in, reset => reset, enable => enable, wait_for_sync => wait_for_sync, packet_done => packet_done, reset_out => link_reset_out, word_clock => csi_byte_clock, word_data => word_data, word_valid => word_valid); depacket : entity work.csi_rx_packet_handler port map ( clock => csi_byte_clock, reset => link_reset_out, enable => enable, data => word_data, data_valid => word_valid, sync_wait => wait_for_sync, packet_done => packet_done, payload_out => packet_payload, payload_valid => packet_payload_valid, vsync_out => csi_vsync, in_frame => csi_in_frame, in_line => csi_in_line); unpack10 : entity work.csi_rx_10bit_unpack port map ( clock => csi_byte_clock, reset => link_reset_out, enable => enable, data_in => packet_payload, din_valid => packet_payload_valid, data_out => unpack_data, dout_valid => unpack_data_valid); vout : entity work.csi_rx_video_output generic map ( video_hlength => video_hlength, video_vlength => video_vlength, video_hsync_pol => video_hsync_pol, video_hsync_len => video_hsync_len, video_hbp_len => video_hbp_len, video_h_visible => video_h_visible, video_vsync_pol => video_vsync_pol, video_vsync_len => video_vsync_len, video_vbp_len => video_vbp_len, video_v_visible => video_v_visible, pixels_per_clock => pixels_per_clock) port map ( output_clock => pixel_clock_in, csi_byte_clock => csi_byte_clock, enable => enable, reset => reset, pixel_data_in => unpack_data, pixel_data_valid => unpack_data_valid, csi_in_frame => csi_in_frame, csi_in_line => csi_in_line, csi_vsync => csi_vsync, video_valid => video_valid, video_hsync => video_hsync, video_vsync => video_vsync, video_den => video_den, video_line_start => video_line_start, video_odd_line => video_odd_line, video_data => video_data, video_prev_line_data => video_prev_line_data ); byte_clock_out <= csi_byte_clock; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_video_output.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --MIPI CSI-2 Rx Video Output Controller --Copyright (C) 2016 David Shah --Licensed under the MIT License --This receives unpacked 10bit pixel data from the unpacker and framing signals from the packet handler, --and writes it into a dual-port line buffer to cross it from the byte clock into the pixel clock domain --It also generates all the necessary video output signals entity csi_rx_video_output is generic( video_hlength : natural := 4046; --total visible and blanking pixels per line video_vlength : natural := 2190; --total visible and blanking lines per frame video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync video_hsync_len : natural := 48; --horizontal sync length in pixels video_hbp_len : natural := 122; --horizontal back porch length (excluding sync) video_h_visible : natural := 3840; --number of visible pixels per line video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync video_vsync_len : natural := 3; --vertical sync length in lines video_vbp_len : natural := 23; --vertical back porch length (excluding sync) video_v_visible : natural := 2160; --number of visible lines per frame pixels_per_clock : natural := 2 --Number of pixels per clock to output; 1, 2 or 4 ); port( output_clock : in std_logic; --Output pixel clock csi_byte_clock : in std_logic; --CSI byte clock enable : in std_logic; --system enable input reset : in std_logic; --synchronous active high reset input pixel_data_in : in std_logic_vector(39 downto 0); --Unpacked 10 bit data pixel_data_valid : in std_logic; csi_in_frame : in std_logic; csi_in_line : in std_logic; csi_vsync : in std_logic; video_valid : out std_logic; --goes high when valid frames are being received --Pixel data output video_hsync : out std_logic; video_vsync : out std_logic; video_den : out std_logic; video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use ); end csi_rx_video_output; architecture Behavioral of csi_rx_video_output is signal csi_in_line_last, csi_in_frame_last, csi_odd_line, csi_frame_started : std_logic := '0'; signal video_fsync_pre, video_fsync : std_logic := '0'; signal csi_x_pos : natural range 0 to video_h_visible - 1; constant output_width : natural := video_h_visible / pixels_per_clock; constant output_tmg_hlength : natural := video_hlength / pixels_per_clock; constant output_hvis_begin : natural := (video_hsync_len + video_hbp_len) / pixels_per_clock; signal output_timing_h : natural range 0 to output_tmg_hlength - 1; signal output_pixel_y : natural range 0 to video_v_visible - 1; signal linebuf_write_address : natural range 0 to video_h_visible / 4 - 1; signal linebuf_read_address : natural range 0 to output_width - 1; signal even_linebuf_wren, odd_linebuf_wren : std_logic := '0'; signal even_linebuf_q, odd_linebuf_q : std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); signal output_hsync, output_vsync, output_den, output_line_start, output_odd_line : std_logic; signal output_data, output_prev_line_data : std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); begin process(csi_byte_clock) begin if rising_edge(csi_byte_clock) then if reset = '1' then csi_in_line_last <= '0'; csi_in_frame_last <= '0'; csi_frame_started <= '0'; csi_odd_line <= '1'; elsif enable = '1' then csi_in_frame_last <= csi_in_frame; csi_in_line_last <= csi_in_line; if csi_in_frame_last = '0' and csi_in_frame = '1' then --Start of frame csi_x_pos <= 0; csi_odd_line <= '1'; csi_frame_started <= '0'; elsif csi_in_line_last = '0' and csi_in_line = '1' then --Start of line csi_x_pos <= 0; csi_odd_line <= not csi_odd_line; csi_frame_started <= '1'; elsif pixel_data_valid = '1' then csi_x_pos <= csi_x_pos + 4; end if; end if; end if; end process; linebuf_write_address <= csi_x_pos / 4; even_linebuf_wren <= pixel_data_valid when csi_odd_line = '0' else '0'; odd_linebuf_wren <= pixel_data_valid when csi_odd_line = '1' else '0'; process(output_clock) begin if rising_edge(output_clock) then if reset = '1' then video_fsync_pre <= '0'; video_fsync <= '0'; elsif enable = '1' then video_fsync_pre <= csi_frame_started; video_fsync <= video_fsync_pre; --Register video output video_hsync <= output_hsync; video_vsync <= output_vsync; video_den <= output_den; video_line_start <= output_line_start; video_odd_line <= output_odd_line; video_data <= output_data; video_prev_line_data <= output_prev_line_data; end if; end if; end process; output_odd_line <= '1' when output_pixel_y mod 2 = 1 else '0'; output_data <= odd_linebuf_q when output_odd_line = '1' else even_linebuf_q; output_prev_line_data <= even_linebuf_q when output_odd_line = '1' else odd_linebuf_q; linebuf_read_address <= (output_timing_h - (output_hvis_begin - 1)); -- the -1 accounts for the RAM read latency output_timing : entity work.video_timing_ctrl generic map( video_hlength => output_tmg_hlength, video_vlength => video_vlength, video_hsync_pol => video_hsync_pol, video_hsync_len => video_hsync_len / pixels_per_clock, video_hbp_len => video_hbp_len / pixels_per_clock, video_h_visible => video_h_visible / pixels_per_clock, video_vsync_pol => video_vsync_pol, video_vsync_len => video_vsync_len, video_vbp_len => video_vbp_len, video_v_visible => video_v_visible, sync_v_pos => (video_vbp_len + video_vsync_len - 1), --keep output 1 line behind input sync_h_pos => (output_tmg_hlength - 5) ) port map( pixel_clock => output_clock, reset => reset, ext_sync => video_fsync, timing_h_pos => output_timing_h, timing_v_pos => open, pixel_x => open, pixel_y => output_pixel_y, video_vsync => output_vsync, video_hsync => output_hsync, video_den => output_den, video_line_start => output_line_start ); even_linebuf : entity work.csi_rx_line_buffer generic map( line_width => video_h_visible, pixels_per_clock => pixels_per_clock ) port map( write_clock => csi_byte_clock, write_addr => linebuf_write_address, write_data => pixel_data_in, write_en => even_linebuf_wren, read_clock => output_clock, read_addr => linebuf_read_address, read_q => even_linebuf_q ); odd_linebuf : entity work.csi_rx_line_buffer generic map( line_width => video_h_visible, pixels_per_clock => pixels_per_clock ) port map( write_clock => csi_byte_clock, write_addr => linebuf_write_address, write_data => pixel_data_in, write_en => odd_linebuf_wren, read_clock => output_clock, read_addr => linebuf_read_address, read_q => odd_linebuf_q ); video_valid <= '1'; --not yet implemented end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/csi_rx_word_align.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_MISC.ALL; --MIPI CSI-2 word aligner --Copyright (C) 2016 David Shah --Licensed under the MIT License --This receives aligned bytes and status signals from the 4 byte aligners --and compensates for up to 2 clock cycles of skew between channels. It also --controls the packet_done input to the byte aligner, resetting byte aligners' --sync status if all 4 byte aligners fail to find the sync pattern --Similar to the byte aligner, this locks the alignment once a valid alignment --has been found until packet_done is asserted entity csi_rx_word_align is Port ( word_clock : in STD_LOGIC; --byte/word clock in reset : in STD_LOGIC; --active high synchronous reset enable : in STD_LOGIC; --active high enable packet_done : in STD_LOGIC; --packet done input from packet handler entity wait_for_sync : in STD_LOGIC; --whether or not to be looking for an alignment packet_done_out : out STD_LOGIC; --packet done output to byte aligners word_in : in STD_LOGIC_VECTOR (31 downto 0); --unaligned word from the 4 byte aligners valid_in : in STD_LOGIC_VECTOR (3 downto 0); --valid_out from the byte aligners (MSB is index 3, LSB index 0) word_out : out STD_LOGIC_VECTOR (31 downto 0); --aligned word out to packet handler valid_out : out STD_LOGIC); --goes high once alignment is valid, such that the first word with it high is the CSI packet header end csi_rx_word_align; architecture Behavioral of csi_rx_word_align is signal word_dly_0 : std_logic_vector(31 downto 0); signal word_dly_1 : std_logic_vector(31 downto 0); signal word_dly_2 : std_logic_vector(31 downto 0); signal valid_dly_0 : std_logic_vector (3 downto 0); signal valid_dly_1 : std_logic_vector (3 downto 0); signal valid_dly_2 : std_logic_vector (3 downto 0); type taps_t is array(0 to 3) of std_logic_vector(1 downto 0); signal taps : taps_t; signal next_taps : taps_t; signal valid : std_logic := '0'; signal next_valid : std_logic; signal invalid_start : std_logic := '0'; signal aligned_word : std_logic_vector(31 downto 0); begin process(word_clock) begin if rising_edge(word_clock) then if reset = '1' then valid <= '0'; taps <= ("00", "00", "00", "00"); elsif enable = '1' then word_dly_0 <= word_in; valid_dly_0 <= valid_in; word_dly_1 <= word_dly_0; valid_dly_1 <= valid_dly_0; word_dly_2 <= word_dly_1; valid_dly_2 <= valid_dly_1; valid_out <= valid; word_out <= aligned_word; if next_valid = '1' and valid = '0' and wait_for_sync = '1' then valid <= '1'; taps <= next_taps; elsif packet_done = '1' then valid <= '0'; end if; end if; end if; end process; process(valid_dly_0, valid_dly_1, valid_dly_2) variable next_valid_int : std_logic; variable is_triggered : std_logic := '0'; begin next_valid_int := and_reduce(valid_dly_0); --Reset if all channels fail to sync is_triggered := '0'; for i in 0 to 3 loop if valid_dly_0(i) = '1' and valid_dly_1(i) = '1' and valid_dly_2(i) = '1' then is_triggered := '1'; end if; end loop; invalid_start <= (not next_valid_int) and is_triggered; next_valid <= next_valid_int; for i in 0 to 3 loop if valid_dly_2(i) = '1' then next_taps(i) <= "10"; elsif valid_dly_1(i) = '1' then next_taps(i) <= "01"; else next_taps(i) <= "00"; end if; end loop; end process; packet_done_out <= packet_done or invalid_start; process(word_dly_0, word_dly_1, word_dly_2, taps) begin for i in 0 to 3 loop if taps(i) = "10" then aligned_word((8*i) + 7 downto 8 * i) <= word_dly_2((8*i) + 7 downto 8 * i); elsif taps(i) = "01" then aligned_word((8*i) + 7 downto 8 * i) <= word_dly_1((8*i) + 7 downto 8 * i); else aligned_word((8*i) + 7 downto 8 * i) <= word_dly_0((8*i) + 7 downto 8 * i); end if; end loop; end process; end Behavioral; ================================================ FILE: vhdl_rx/mipi-csi-rx/synth.ys ================================================ read -vhdl csi_rx_hdr_ecc.vhd csi_rx_packet_handler.vhd csi_rx_10bit_unpack.vhd csi_rx_video_output.vhd csi_rx_line_buffer.vhd ================================================ FILE: vhdl_rx/ov-cam-control/manual_focus.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Manual focus controller --Copyright (C) 2016 David Shah --Licensed under the MIT License --This reads two buttons and outputs a current value for the focus voice --coil driver entity manual_focus is Port ( clock : in STD_LOGIC; enable : in STD_LOGIC; reset : in STD_LOGIC; i2c_start : out STD_LOGIC; vcm_value : out STD_LOGIC_VECTOR (9 downto 0); btn_inc : in STD_LOGIC; btn_dec : in STD_LOGIC); end manual_focus; architecture Behavioral of manual_focus is signal int_focus_value : unsigned(22 downto 0); signal last_focus_value : unsigned(9 downto 0); signal out_focus_value : std_logic_vector(9 downto 0); signal i2c_wait_ctr : unsigned(8 downto 0); begin process(reset, clock) begin if reset = '1' then int_focus_value <= (others => '0'); last_focus_value <= (others => '0'); out_focus_value <= (others => '0'); i2c_wait_ctr <= (others => '0'); elsif rising_edge(clock) then if enable = '1' then --User side if btn_inc = '1' then if int_focus_value < 8388607 then int_focus_value <= int_focus_value + 1; end if; elsif btn_dec = '1' then if int_focus_value > 0 then int_focus_value <= int_focus_value - 1; end if; end if; --I2C side if i2c_wait_ctr = 0 then if int_focus_value(22 downto 13) /= last_focus_value then out_focus_value <= std_logic_vector(int_focus_value(22 downto 13)); last_focus_value <= int_focus_value(22 downto 13); i2c_start <= '1'; else i2c_start <= '0'; end if; else i2c_start <= '0'; end if; i2c_wait_ctr <= i2c_wait_ctr + 1; end if; end if; end process; vcm_value <= out_focus_value; end Behavioral; ================================================ FILE: vhdl_rx/ov-cam-control/ov13850_4k_regs.vhd ================================================ library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --OV13850 Camera Configuration --This configuration is for 4k24/4k30, 10-bit, 4-lane with a total horizontal length of 6800 pixels --and a total vertical length of 2992 lines entity ov13850_4k_regs is port (clock : in std_logic; --this allows a blockram to be elaborated address : in std_logic_vector(8 downto 0); --This is the I2C data to be written --2 MSBs are address, 1 MSB is data data : out std_logic_vector(23 downto 0)); end ov13850_4k_regs; architecture behv_cd of ov13850_4k_regs is begin process(clock) begin if rising_edge(clock) then case address(8 downto 0) is when "0" & x"00" => data <= x"010301"; --software reset when "0" & x"01" => data <= x"030a00"; when "0" & x"02" => data <= x"300f11"; --MIPI 10 bit mode when "0" & x"03" => data <= x"301003"; --MIPI PHY when "0" & x"04" => data <= x"301176"; --MIPI PHY when "0" & x"05" => data <= x"301241"; --MIPI 4 lane when "0" & x"06" => data <= x"301312"; when "0" & x"07" => data <= x"301411"; when "0" & x"08" => data <= x"301f03"; when "0" & x"09" => data <= x"310600"; when "0" & x"0a" => data <= x"321047"; when "0" & x"0b" => data <= x"350000"; when "0" & x"0c" => data <= x"3501b0"; when "0" & x"0d" => data <= x"350200"; when "0" & x"0e" => data <= x"350600"; when "0" & x"0f" => data <= x"35070a"; when "0" & x"10" => data <= x"350800"; when "0" & x"11" => data <= x"350910"; when "0" & x"12" => data <= x"350a00"; when "0" & x"13" => data <= x"350ba0"; when "0" & x"14" => data <= x"350e00"; when "0" & x"15" => data <= x"350fa0"; when "0" & x"16" => data <= x"360040"; when "0" & x"17" => data <= x"3601fc"; when "0" & x"18" => data <= x"360202"; when "0" & x"19" => data <= x"360348"; when "0" & x"1a" => data <= x"3604a5"; when "0" & x"1b" => data <= x"36059f"; when "0" & x"1c" => data <= x"360700"; when "0" & x"1d" => data <= x"360a40"; when "0" & x"1e" => data <= x"360b91"; when "0" & x"1f" => data <= x"360c49"; when "0" & x"20" => data <= x"360f8a"; when "0" & x"21" => data <= x"361110"; when "0" & x"22" => data <= x"361311"; --wait when "0" & x"30" => data <= x"361508"; when "0" & x"31" => data <= x"364102"; when "0" & x"32" => data <= x"366082"; when "0" & x"33" => data <= x"366854"; when "0" & x"34" => data <= x"366940"; when "0" & x"35" => data <= x"3667a0"; when "0" & x"36" => data <= x"370240"; when "0" & x"37" => data <= x"370344"; when "0" & x"38" => data <= x"37042c"; when "0" & x"39" => data <= x"370524"; when "0" & x"3a" => data <= x"370650"; when "0" & x"3b" => data <= x"370744"; when "0" & x"3c" => data <= x"37083c"; when "0" & x"3d" => data <= x"37091f"; when "0" & x"3e" => data <= x"370a26"; when "0" & x"3f" => data <= x"370b3c"; when "0" & x"40" => data <= x"372066"; when "0" & x"41" => data <= x"372284"; when "0" & x"42" => data <= x"372840"; when "0" & x"43" => data <= x"372a00"; when "0" & x"44" => data <= x"372f90"; when "0" & x"45" => data <= x"371028"; when "0" & x"46" => data <= x"371603"; when "0" & x"47" => data <= x"371810"; when "0" & x"48" => data <= x"371908"; when "0" & x"49" => data <= x"371cfc"; when "0" & x"4a" => data <= x"376013"; when "0" & x"4b" => data <= x"376134"; when "0" & x"4c" => data <= x"376724"; when "0" & x"4d" => data <= x"376806"; when "0" & x"4e" => data <= x"376945"; when "0" & x"4f" => data <= x"376c23"; when "0" & x"50" => data <= x"3d8400"; when "0" & x"51" => data <= x"3d8517"; when "0" & x"52" => data <= x"3d8c73"; when "0" & x"53" => data <= x"3d8dbf"; when "0" & x"54" => data <= x"380000"; when "0" & x"55" => data <= x"380108"; when "0" & x"56" => data <= x"380200"; when "0" & x"57" => data <= x"380304"; when "0" & x"58" => data <= x"380410"; when "0" & x"59" => data <= x"380597"; when "0" & x"5a" => data <= x"38060c"; when "0" & x"5b" => data <= x"38074b"; when "0" & x"5c" => data <= x"380808"; when "0" & x"5d" => data <= x"380940"; when "0" & x"5e" => data <= x"380a06"; when "0" & x"5f" => data <= x"380b20"; when "0" & x"60" => data <= x"380c25"; when "0" & x"61" => data <= x"380d80"; when "0" & x"62" => data <= x"380e06"; when "0" & x"63" => data <= x"380f80"; when "0" & x"64" => data <= x"381000"; when "0" & x"65" => data <= x"381104"; when "0" & x"66" => data <= x"381200"; when "0" & x"67" => data <= x"381302"; when "0" & x"68" => data <= x"381431"; when "0" & x"69" => data <= x"381531"; when "0" & x"6a" => data <= x"382002"; when "0" & x"6b" => data <= x"382105"; --mirror off when "0" & x"6c" => data <= x"383400"; when "0" & x"6d" => data <= x"38351c"; when "0" & x"6e" => data <= x"383608"; when "0" & x"6f" => data <= x"383702"; when "0" & x"70" => data <= x"4000f1"; when "0" & x"71" => data <= x"400100"; when "0" & x"72" => data <= x"400b0c"; when "0" & x"73" => data <= x"401100"; when "0" & x"74" => data <= x"401a00"; when "0" & x"75" => data <= x"401b00"; when "0" & x"76" => data <= x"401c00"; when "0" & x"77" => data <= x"401d00"; when "0" & x"78" => data <= x"402000"; when "0" & x"79" => data <= x"4021e4"; when "0" & x"7a" => data <= x"402207"; when "0" & x"7b" => data <= x"40235f"; when "0" & x"7c" => data <= x"402408"; when "0" & x"7d" => data <= x"402544"; when "0" & x"7e" => data <= x"402608"; when "0" & x"7f" => data <= x"402747"; when "0" & x"80" => data <= x"402800"; when "0" & x"81" => data <= x"402902"; when "0" & x"82" => data <= x"402a04"; when "0" & x"83" => data <= x"402b08"; when "0" & x"84" => data <= x"402c02"; when "0" & x"85" => data <= x"402d02"; when "0" & x"86" => data <= x"402e0c"; when "0" & x"87" => data <= x"402f08"; when "0" & x"88" => data <= x"403d2c"; when "0" & x"89" => data <= x"403f7f"; when "0" & x"8a" => data <= x"450082"; when "0" & x"8b" => data <= x"450138"; when "0" & x"8c" => data <= x"460104"; when "0" & x"8d" => data <= x"460222"; when "0" & x"8e" => data <= x"460301"; when "0" & x"8f" => data <= x"483719"; when "0" & x"90" => data <= x"480004"; when "0" & x"91" => data <= x"480242"; when "0" & x"92" => data <= x"481a00"; when "0" & x"93" => data <= x"481b1c"; when "0" & x"94" => data <= x"482612"; when "0" & x"95" => data <= x"4d0004"; when "0" & x"96" => data <= x"4d0142"; when "0" & x"97" => data <= x"4d02d1"; when "0" & x"98" => data <= x"4d0390"; when "0" & x"99" => data <= x"4d0466"; when "0" & x"9a" => data <= x"4d0565"; when "0" & x"9b" => data <= x"50000e"; when "0" & x"9c" => data <= x"500103"; when "0" & x"9d" => data <= x"500207"; when "0" & x"9e" => data <= x"501340"; when "0" & x"9f" => data <= x"501c00"; when "0" & x"a0" => data <= x"501d10"; when "0" & x"a1" => data <= x"524200"; when "0" & x"a2" => data <= x"5243b8"; when "0" & x"a3" => data <= x"524400"; when "0" & x"a4" => data <= x"5245f9"; when "0" & x"a5" => data <= x"524600"; when "0" & x"a6" => data <= x"5247f6"; when "0" & x"a7" => data <= x"524800"; when "0" & x"a8" => data <= x"5249a6"; when "0" & x"a9" => data <= x"5300fc"; when "0" & x"aa" => data <= x"5301df"; when "0" & x"ab" => data <= x"53023f"; when "0" & x"ac" => data <= x"530308"; when "0" & x"ad" => data <= x"53040c"; when "0" & x"ae" => data <= x"530510"; when "0" & x"af" => data <= x"530620"; when "0" & x"b0" => data <= x"530740"; when "0" & x"b1" => data <= x"530808"; when "0" & x"b2" => data <= x"530908"; when "0" & x"b3" => data <= x"530a02"; when "0" & x"b4" => data <= x"530b01"; when "0" & x"b5" => data <= x"530c01"; when "0" & x"b6" => data <= x"530d0c"; when "0" & x"b7" => data <= x"530e02"; when "0" & x"b8" => data <= x"530f01"; when "0" & x"b9" => data <= x"531001"; when "0" & x"ba" => data <= x"540000"; when "0" & x"bb" => data <= x"540161"; when "0" & x"bc" => data <= x"540200"; when "0" & x"bd" => data <= x"540300"; when "0" & x"be" => data <= x"540400"; when "0" & x"bf" => data <= x"540540"; when "0" & x"c0" => data <= x"540c05"; when "0" & x"c1" => data <= x"5b0000"; when "0" & x"c2" => data <= x"5b0100"; when "0" & x"c3" => data <= x"5b0201"; when "0" & x"c4" => data <= x"5b03ff"; when "0" & x"c5" => data <= x"5b0402"; when "0" & x"c6" => data <= x"5b056c"; when "0" & x"c7" => data <= x"5b0902"; when "0" & x"c8" => data <= x"5e0000"; --test pattern off when "0" & x"c9" => data <= x"5e101c"; when "0" & x"ca" => data <= x"381304"; when "0" & x"cb" => data <= x"381411"; when "0" & x"cc" => data <= x"381511"; when "0" & x"cd" => data <= x"382004"; when "0" & x"ce" => data <= x"382104"; --mirror off when "0" & x"cf" => data <= x"383604"; when "0" & x"d0" => data <= x"383701"; when "0" & x"d1" => data <= x"48370a"; when "0" & x"d2" => data <= x"482612"; when "0" & x"d3" => data <= x"540171"; when "0" & x"d4" => data <= x"540580"; when "0" & x"d5" => data <= x"361207"; when "0" & x"d6" => data <= x"030000"; when "0" & x"d7" => data <= x"030100"; when "0" & x"d8" => data <= x"030220"; when "0" & x"d9" => data <= x"030300"; when "0" & x"e0" => data <= x"48370d"; when "0" & x"e1" => data <= x"370a24"; when "0" & x"e2" => data <= x"372a04"; when "0" & x"e3" => data <= x"372fa0"; when "0" & x"e4" => data <= x"380001"; when "0" & x"e5" => data <= x"38014c"; when "0" & x"e6" => data <= x"380202"; when "0" & x"e7" => data <= x"38038c"; when "0" & x"e8" => data <= x"380410"; when "0" & x"e9" => data <= x"380553"; when "0" & x"f0" => data <= x"38060b"; when "0" & x"f1" => data <= x"380703"; when "0" & x"f2" => data <= x"38080f"; when "0" & x"f3" => data <= x"380900"; when "0" & x"f4" => data <= x"380a08"; when "0" & x"f5" => data <= x"380b70"; when "0" & x"f6" => data <= x"380c1a"; --HTS MSB when "0" & x"f7" => data <= x"380d90"; --HTS LSB when "0" & x"f8" => data <= x"380e0b"; --VTS MSB when "0" & x"f9" => data <= x"380fb0"; --VTS LSB when "1" & x"00" => data <= x"381000"; when "1" & x"01" => data <= x"381104"; when "1" & x"02" => data <= x"381200"; when "1" & x"03" => data <= x"381304"; when "1" & x"04" => data <= x"383604"; when "1" & x"05" => data <= x"383701"; when "1" & x"06" => data <= x"402000"; when "1" & x"07" => data <= x"4021e6"; when "1" & x"08" => data <= x"40220e"; when "1" & x"09" => data <= x"40231e"; when "1" & x"0a" => data <= x"40240f"; when "1" & x"0b" => data <= x"402500"; when "1" & x"0c" => data <= x"40260f"; when "1" & x"0d" => data <= x"402706"; when "1" & x"0e" => data <= x"010001"; when others => data <= x"000000"; end case; end if; end process; end behv_cd; ================================================ FILE: vhdl_rx/ov-cam-control/ov13850_control_top.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Low speed Omnivision camera reset sequencing and control --Copyright (C) 2016 David Shah --Licensed under the MIT License entity ov13850_control_top is port(reset : in std_logic; clock : in std_logic; --400kHz clock i2c_sda : inout std_logic; i2c_sck : inout std_logic; rst_out : out std_logic; loading_out : out std_logic ); end ov13850_control_top; architecture Behavioral of ov13850_control_top is signal current_cmd : std_logic_vector(23 downto 0); signal statecntr : unsigned(17 downto 0) := (others => '0'); signal cmd_addr : std_logic_vector(8 downto 0); signal i2c_en : std_logic; signal i2c_start : std_logic; signal i2c_done : std_logic; constant state_end : integer := 262000; begin i2c_if : entity work.ov_i2c_control generic map( slave_addr => x"20") port map( clock_in => clock, data_in => current_cmd, enable => i2c_en, start_xfer => i2c_start, xfer_done => i2c_done, i2c_sck => i2c_sck, i2c_sda => i2c_sda); regs : entity work.ov13850_4k_regs port map( clock => clock, address => cmd_addr, data => current_cmd); loading_out <= '1' when statecntr < state_end else '0'; --Keep track of where we are in the setup procedure process(clock, reset) begin if reset = '1' then statecntr <= (others => '0'); elsif rising_edge(clock) then if statecntr < state_end then statecntr <= statecntr + 1; end if; end if; end process; --Power on reset process(statecntr) begin if statecntr < 16384 then rst_out <= '0'; else rst_out <= '1'; end if; end process; --I2C command selection process(statecntr, current_cmd) variable statecntr_sub : unsigned(17 downto 0); begin if statecntr < 32768 then i2c_en <= '0'; i2c_start <= '0'; cmd_addr <= "0" & x"00"; else statecntr_sub := statecntr - 32768; --We output a new command over I2C every 128 cycles cmd_addr <= std_logic_vector(statecntr_sub(17 downto 9)); --All zeroes indicate a dummy command if current_cmd = x"000000" then i2c_en <= '0'; i2c_start <= '0'; else i2c_en <= '1'; --Output a start transaction signal for cycles 1&2 if statecntr_sub(8 downto 2) = 1 or statecntr_sub(8 downto 2) = 2 then i2c_start <= '1'; else i2c_start <= '0'; end if; end if; end if; end process; end Behavioral; ================================================ FILE: vhdl_rx/ov-cam-control/ov16825_1080p120_regs.vhd ================================================ library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --OV16825 Camera Configuration --This configuration is for 1080p, 120fps, 10-bit, 4-lane with a total horizontal length of 4224 pixels --and a total vertical length of 1248 lines entity ov16825_1080p120_regs is port (clock : in std_logic; --this allows a blockram to be elaborated address : in std_logic_vector(8 downto 0); --This is the I2C data to be written --2 MSBs are address, 1 MSB is data data : out std_logic_vector(23 downto 0)); end ov16825_1080p120_regs; architecture behv_cd of ov16825_1080p120_regs is begin process(clock) begin if rising_edge(clock) then case address(8 downto 0) is --Global init when "0" & x"00" => data <= x"010301"; --software reset when "0" & x"10" => --PLL setup data <= x"010000"; when "0" & x"11" => data <= x"030002"; when "0" & x"12" => data <= x"030250"; when "0" & x"13" => data <= x"030501"; when "0" & x"14" => data <= x"030600"; when "0" & x"15" => data <= x"030b02"; when "0" & x"16" => data <= x"030c14"; when "0" & x"17" => data <= x"030e00"; when "0" & x"18" => data <= x"031302"; when "0" & x"19" => data <= x"031414"; when "0" & x"1a" => data <= x"031f00"; when "0" & x"20" => data <= x"302201"; when "0" & x"21" => data <= x"303280"; when "0" & x"22" => data <= x"3601f8"; when "0" & x"23" => data <= x"360200"; when "0" & x"24" => data <= x"360550"; when "0" & x"25" => data <= x"360600"; when "0" & x"26" => data <= x"36072b"; when "0" & x"27" => data <= x"360816"; when "0" & x"28" => data <= x"360900"; when "0" & x"29" => data <= x"360e99"; when "0" & x"2a" => data <= x"360f75"; when "0" & x"2b" => data <= x"361069"; when "0" & x"2c" => data <= x"361159"; when "0" & x"2d" => data <= x"361240"; when "0" & x"2e" => data <= x"361389"; when "0" & x"2f" => data <= x"361544"; when "0" & x"30" => data <= x"361700"; when "0" & x"31" => data <= x"361820"; when "0" & x"32" => data <= x"361900"; when "0" & x"33" => data <= x"361a10"; when "0" & x"34" => data <= x"361c10"; when "0" & x"35" => data <= x"361d00"; when "0" & x"36" => data <= x"361e00"; when "0" & x"37" => data <= x"364015"; when "0" & x"38" => data <= x"364154"; when "0" & x"39" => data <= x"364263"; when "0" & x"3a" => data <= x"364332"; when "0" & x"3b" => data <= x"364403"; when "0" & x"3c" => data <= x"364504"; when "0" & x"3d" => data <= x"364685"; when "0" & x"3e" => data <= x"364a07"; when "0" & x"3f" => data <= x"370708"; when "0" & x"40" => data <= x"371875"; when "0" & x"41" => data <= x"371a55"; when "0" & x"42" => data <= x"371c55"; when "0" & x"43" => data <= x"373380"; when "0" & x"44" => data <= x"376000"; when "0" & x"45" => data <= x"376130"; when "0" & x"46" => data <= x"376200"; when "0" & x"47" => data <= x"3763c0"; when "0" & x"48" => data <= x"376403"; when "0" & x"49" => data <= x"376500"; when "0" & x"50" => data <= x"382308"; when "0" & x"51" => data <= x"382702"; when "0" & x"52" => data <= x"382800"; when "0" & x"53" => data <= x"383200"; when "0" & x"54" => data <= x"383300"; when "0" & x"55" => data <= x"383400"; when "0" & x"56" => data <= x"3d8517"; when "0" & x"57" => data <= x"3d8c70"; when "0" & x"58" => data <= x"3d8da0"; when "0" & x"59" => data <= x"3f0002"; when "0" & x"60" => data <= x"400183"; when "0" & x"61" => data <= x"400e00"; when "0" & x"62" => data <= x"401100"; when "0" & x"63" => data <= x"401200"; when "0" & x"64" => data <= x"420008"; when "0" & x"65" => data <= x"43027f"; when "0" & x"66" => data <= x"4303ff"; when "0" & x"67" => data <= x"430400"; when "0" & x"68" => data <= x"430500"; when "0" & x"69" => data <= x"450130"; when "0" & x"6a" => data <= x"460320"; when "0" & x"6b" => data <= x"4b0022"; when "0" & x"6c" => data <= x"490300"; when "0" & x"6d" => data <= x"50007f"; when "0" & x"6e" => data <= x"500101"; when "0" & x"6f" => data <= x"500400"; when "0" & x"70" => data <= x"501320"; when "0" & x"71" => data <= x"505100"; when "0" & x"72" => data <= x"550001"; when "0" & x"73" => data <= x"550100"; when "0" & x"74" => data <= x"550207"; when "0" & x"75" => data <= x"5503ff"; when "0" & x"76" => data <= x"55056c"; when "0" & x"77" => data <= x"550902"; when "0" & x"78" => data <= x"5780fc"; when "0" & x"79" => data <= x"5781ff"; when "0" & x"7a" => data <= x"578740"; when "0" & x"7b" => data <= x"578808"; when "0" & x"7c" => data <= x"578a02"; when "0" & x"7d" => data <= x"578b01"; when "0" & x"7e" => data <= x"578c01"; when "0" & x"7f" => data <= x"578e02"; when "0" & x"80" => data <= x"578f01"; when "0" & x"81" => data <= x"579001"; when "0" & x"82" => data <= x"579200"; when "0" & x"83" => data <= x"598000"; when "0" & x"84" => data <= x"598121"; when "0" & x"85" => data <= x"598200"; when "0" & x"86" => data <= x"598300"; when "0" & x"87" => data <= x"598400"; when "0" & x"88" => data <= x"598500"; when "0" & x"89" => data <= x"598600"; when "0" & x"8a" => data <= x"598700"; when "0" & x"8b" => data <= x"598800"; when "0" & x"90" => data <= x"320115"; when "0" & x"91" => data <= x"32022a"; --1080p120 specific config when "0" & x"a0" => data <= x"010000"; when "0" & x"b0" => data <= x"320800"; when "0" & x"b1" => data <= x"301afb"; when "0" & x"b2" => data <= x"030264"; when "0" & x"b3" => data <= x"030501"; when "0" & x"b4" => data <= x"030e00"; when "0" & x"b5" => data <= x"30187a"; when "0" & x"b6" => data <= x"30310a"; when "0" & x"b7" => data <= x"360305"; when "0" & x"b8" => data <= x"360402"; when "0" & x"b9" => data <= x"360a02"; when "0" & x"ba" => data <= x"360b02"; when "0" & x"bb" => data <= x"360c12"; when "0" & x"bc" => data <= x"360d04"; when "0" & x"bd" => data <= x"361477"; when "0" & x"be" => data <= x"361631"; when "0" & x"bf" => data <= x"363140"; when "0" & x"c0" => data <= x"370060"; when "0" & x"c1" => data <= x"370110"; when "0" & x"c2" => data <= x"370222"; when "0" & x"c3" => data <= x"370340"; when "0" & x"c4" => data <= x"370410"; when "0" & x"c5" => data <= x"370501"; when "0" & x"c6" => data <= x"370604"; when "0" & x"c7" => data <= x"370840"; when "0" & x"c8" => data <= x"370978"; when "0" & x"c9" => data <= x"370a02"; when "0" & x"ca" => data <= x"370bb2"; when "0" & x"cb" => data <= x"370c06"; when "0" & x"cc" => data <= x"370e40"; when "0" & x"cd" => data <= x"370f0a"; when "0" & x"d0" => data <= x"371030"; when "0" & x"d1" => data <= x"371140"; when "0" & x"d2" => data <= x"371431"; when "0" & x"d3" => data <= x"371925"; when "0" & x"d4" => data <= x"371b05"; when "0" & x"d5" => data <= x"371d05"; when "0" & x"d6" => data <= x"371e11"; when "0" & x"d7" => data <= x"371f2d"; when "0" & x"e0" => data <= x"372015"; when "0" & x"e1" => data <= x"372130"; when "0" & x"e2" => data <= x"372215"; when "0" & x"e3" => data <= x"372330"; when "0" & x"e4" => data <= x"372408"; when "0" & x"e5" => data <= x"372508"; when "0" & x"e6" => data <= x"372604"; when "0" & x"e7" => data <= x"372704"; when "0" & x"e8" => data <= x"372804"; when "0" & x"e9" => data <= x"372904"; when "0" & x"ea" => data <= x"372a29"; when "0" & x"eb" => data <= x"372bc9"; when "0" & x"ec" => data <= x"372ca9"; when "0" & x"ed" => data <= x"372db9"; when "0" & x"ee" => data <= x"372e95"; when "0" & x"ef" => data <= x"372f55"; when "0" & x"f0" => data <= x"373055"; when "0" & x"f1" => data <= x"373155"; when "0" & x"f2" => data <= x"373205"; when "0" & x"f3" => data <= x"373410"; when "0" & x"f4" => data <= x"373905"; when "0" & x"f5" => data <= x"373a40"; when "0" & x"f6" => data <= x"373b18"; when "0" & x"f7" => data <= x"373c38"; when "0" & x"f8" => data <= x"373e15"; when "0" & x"f9" => data <= x"373f80"; when "1" & x"00" => data <= x"380001"; when "1" & x"01" => data <= x"380180"; when "1" & x"02" => data <= x"380202"; when "1" & x"03" => data <= x"380394"; when "1" & x"04" => data <= x"380410"; when "1" & x"05" => data <= x"3805bf"; when "1" & x"06" => data <= x"38060b"; when "1" & x"07" => data <= x"38070f"; when "1" & x"08" => data <= x"380807"; when "1" & x"09" => data <= x"380980"; when "1" & x"0a" => data <= x"380a04"; when "1" & x"0b" => data <= x"380b38"; when "1" & x"0c" => data <= x"380c04"; when "1" & x"0d" => data <= x"380d20"; when "1" & x"0e" => data <= x"380e04"; when "1" & x"0f" => data <= x"380fe0"; when "1" & x"10" => data <= x"381117"; when "1" & x"11" => data <= x"381302"; when "1" & x"12" => data <= x"381403"; when "1" & x"13" => data <= x"381501"; when "1" & x"14" => data <= x"382000"; when "1" & x"15" => data <= x"382107"; when "1" & x"16" => data <= x"382900"; when "1" & x"17" => data <= x"382a03"; when "1" & x"18" => data <= x"382b01"; when "1" & x"19" => data <= x"383008"; when "1" & x"1a" => data <= x"3f0840"; when "1" & x"20" => data <= x"400202"; when "1" & x"21" => data <= x"400304"; when "1" & x"22" => data <= x"483714"; when "1" & x"23" => data <= x"350144"; when "1" & x"24" => data <= x"350808"; when "1" & x"25" => data <= x"3509ff"; when "1" & x"26" => data <= x"363800"; when "1" & x"27" => data <= x"301af0"; when "1" & x"28" => data <= x"320810"; when "1" & x"29" => data <= x"3208a0"; when "1" & x"30" => data <= x"380807"; when "1" & x"31" => data <= x"380980"; when "1" & x"32" => data <= x"380a04"; when "1" & x"33" => data <= x"380b38"; when "1" & x"34" => data <= x"381000"; when "1" & x"35" => data <= x"381117"; when "1" & x"36" => data <= x"381200"; when "1" & x"37" => data <= x"381302"; when "1" & x"38" => data <= x"46032f"; when "1" & x"39" => data <= x"50007f"; when "1" & x"40" => data <= x"010001"; when others => data <= x"000000"; end case; end if; end process; end behv_cd; ================================================ FILE: vhdl_rx/ov-cam-control/ov_i2c_control.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --I2C controller for Omnivision camera control (used in the OV13850 demo) --Ugly but it works :). This is actually from a OV5640 driver I wrote a while ago, --so it's from when I was still learning VHDL... --Copyright (C) 2016 David Shah --Licensed under the MIT License entity ov_i2c_control is generic ( slave_addr : std_logic_vector(7 downto 0) := x"20"); --OV13850 slave address port (clock_in : in std_logic; data_in : in std_logic_vector(23 downto 0); -- 16 bit address followed by 8 bit data enable : in std_logic; start_xfer : in std_logic; --pull high, then low to reset and start xfer xfer_done : out std_logic; --signifies that the transfer is done i2c_sck : inout std_logic; --I2C SCK pin i2c_sda : inout std_logic); --I2C SDA pin end ov_i2c_control; architecture Behavioral of ov_i2c_control is signal sys_en : std_logic; signal sda_int : std_logic; --Internal I2C data, 0=low, 1=tristate signal sck_int : std_logic; --Internal I2C clock, 0=low, 1=tristate signal sck_force : std_logic; --Used to force I2C clock signal state_cntr : unsigned(7 downto 0); --Internal counter for keeping track of state constant state_done : integer := 168; --value of state_cntr when transfer finished begin process(enable, start_xfer, state_cntr) begin if enable = '1' and start_xfer = '0' then if state_cntr >= state_done then sys_en <= '0'; xfer_done <= '1'; else sys_en <= '1'; xfer_done <= '0'; end if; else sys_en <= '0'; xfer_done <= '0'; end if; end process; process(start_xfer, clock_in) begin if start_xfer = '1' then state_cntr <= "00000000"; else if rising_edge(clock_in) then if state_cntr < state_done then state_cntr <= state_cntr + 1; end if; end if; end if; end process; process(sda_int, sck_int, sys_en) begin if sys_en = '1' then if sda_int = '1' then i2c_sda <= 'Z'; else i2c_sda <= '0'; end if; if sck_int = '1' then i2c_sck <= 'Z'; else i2c_sck <= '0'; end if; else i2c_sda <= 'Z'; i2c_sck <= 'Z'; end if; end process; process(state_cntr, clock_in, sck_force) begin if state_cntr(7 downto 2) >= 4 and state_cntr(7 downto 2) <= 39 then sck_int <= sck_force or (state_cntr(1) xor state_cntr(0)); else sck_int <= sck_force; end if; end process; process(start_xfer, clock_in) begin if start_xfer = '1' then sda_int <= '1'; sck_force <= '1'; elsif rising_edge(clock_in) then if state_cntr(1 downto 0) = 3 then case state_cntr(7 downto 2) is --start sequence when "000000" => sda_int <= '1'; sck_force <= '1'; when "000001" => sda_int <= '0'; when "000010" => sck_force <= '0'; --I2C slave address when "000011" => sda_int <= slave_addr(7); when "000100" => sda_int <= slave_addr(6); when "000101" => sda_int <= slave_addr(5); when "000110" => sda_int <= slave_addr(4); when "000111" => sda_int <= slave_addr(3); when "001000" => sda_int <= slave_addr(2); when "001001" => sda_int <= slave_addr(1); when "001010" => sda_int <= '0'; --WRITE transaction when "001011" => sda_int <= '1'; --Register address MSB when "001100" => sda_int <= data_in(23); when "001101" => sda_int <= data_in(22); when "001110" => sda_int <= data_in(21); when "001111" => sda_int <= data_in(20); when "010000" => sda_int <= data_in(19); when "010001" => sda_int <= data_in(18); when "010010" => sda_int <= data_in(17); when "010011" => sda_int <= data_in(16); when "010100" => sda_int <= '1'; --Register address LSB when "010101" => sda_int <= data_in(15); when "010110" => sda_int <= data_in(14); when "010111" => sda_int <= data_in(13); when "011000" => sda_int <= data_in(12); when "011001" => sda_int <= data_in(11); when "011010" => sda_int <= data_in(10); when "011011" => sda_int <= data_in(9); when "011100" => sda_int <= data_in(8); when "011101" => sda_int <= '1'; --Register value when "011110" => sda_int <= data_in(7); when "011111" => sda_int <= data_in(6); when "100000" => sda_int <= data_in(5); when "100001" => sda_int <= data_in(4); when "100010" => sda_int <= data_in(3); when "100011" => sda_int <= data_in(2); when "100100" => sda_int <= data_in(1); when "100101" => sda_int <= data_in(0); when "100110" => sda_int <= '1'; --STOP when "100111" => sda_int <= '0'; sck_force <= '0'; when "101000" => sck_force <= '1'; when "101001" => sda_int <= '1'; when others => end case; end if; end if; end process; end Behavioral; ================================================ FILE: vhdl_rx/ov-cam-control/vcm_i2c_control.vhd ================================================ library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --I2C controller for the VCM driver inside the camera module, responsible for --focusing --Copyright (C) 2016 David Shah --Licensed under the MIT License entity vcm_i2c_control is port (clock_in : in std_logic; data_in : in std_logic_vector(9 downto 0); -- 10 bit VCM setting enable : in std_logic; start_xfer : in std_logic; --pull high, then low to reset and start xfer xfer_done : out std_logic; --signifies that the transfer is done i2c_sck : inout std_logic; --I2C SCK pin i2c_sda : inout std_logic); --I2C SDA pin end vcm_i2c_control; architecture behv_i2c of vcm_i2c_control is signal sys_en : std_logic; signal sda_int : std_logic; --Internal I2C data, 0=low, 1=tristate signal sck_int : std_logic; --Internal I2C clock, 0=low, 1=tristate signal sck_force : std_logic; --Used to force I2C clock signal state_cntr : unsigned(7 downto 0); --Internal counter for keeping track of state constant state_done : integer := 168; --value of state_cntr when transfer finished constant slave_addr : std_logic_vector(7 downto 0) := x"18"; --VCM driver slave address begin process(enable, start_xfer, state_cntr) begin if enable = '1' and start_xfer = '0' then if state_cntr >= state_done then sys_en <= '0'; xfer_done <= '1'; else sys_en <= '1'; xfer_done <= '0'; end if; else sys_en <= '0'; xfer_done <= '0'; end if; end process; process(start_xfer, clock_in) begin if start_xfer = '1' then state_cntr <= "00000000"; else if rising_edge(clock_in) then if state_cntr < state_done then state_cntr <= state_cntr + 1; end if; end if; end if; end process; process(sda_int, sck_int, sys_en) begin if sys_en = '1' then if sda_int = '1' then i2c_sda <= 'Z'; else i2c_sda <= '0'; end if; if sck_int = '1' then i2c_sck <= 'Z'; else i2c_sck <= '0'; end if; else i2c_sda <= 'Z'; i2c_sck <= 'Z'; end if; end process; process(state_cntr, clock_in, sck_force) begin if state_cntr(7 downto 2) >= 13 and state_cntr(7 downto 2) <= 39 then sck_int <= sck_force or (state_cntr(1) xor state_cntr(0)); else sck_int <= sck_force; end if; end process; process(start_xfer, clock_in) begin if start_xfer = '1' then sda_int <= '1'; sck_force <= '1'; elsif rising_edge(clock_in) then if state_cntr(1 downto 0) = 3 then case state_cntr(7 downto 2) is --start sequence when "001001" => sda_int <= '1'; sck_force <= '1'; when "001010" => sda_int <= '0'; when "001011" => sck_force <= '0'; --I2C slave address when "001100" => sda_int <= slave_addr(7); when "001101" => sda_int <= slave_addr(6); when "001110" => sda_int <= slave_addr(5); when "001111" => sda_int <= slave_addr(4); when "010000" => sda_int <= slave_addr(3); when "010001" => sda_int <= slave_addr(2); when "010010" => sda_int <= slave_addr(1); when "010011" => sda_int <= slave_addr(0); when "010100" => sda_int <= '1'; --Register address LSB when "010101" => sda_int <= '0'; when "010110" => sda_int <= '0'; when "010111" => sda_int <= data_in(9); when "011000" => sda_int <= data_in(8); when "011001" => sda_int <= data_in(7); when "011010" => sda_int <= data_in(6); when "011011" => sda_int <= data_in(5); when "011100" => sda_int <= data_in(4); when "011101" => sda_int <= '1'; --Register value when "011110" => sda_int <= data_in(3); when "011111" => sda_int <= data_in(2); when "100000" => sda_int <= data_in(1); when "100001" => sda_int <= data_in(0); when "100010" => sda_int <= '0'; when "100011" => sda_int <= '1'; when "100100" => sda_int <= '1'; when "100101" => sda_int <= '1'; when "100110" => sda_int <= '1'; --STOP when "100111" => sda_int <= '0'; sck_force <= '0'; when "101000" => sck_force <= '1'; when "101001" => sda_int <= '1'; when others => end case; end if; end if; end process; end behv_i2c; ================================================ FILE: vhdl_rx/video-misc/image_gain_wb.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Gain/White Balance for CSI-2 Rx Example --Copyright (C) 2016 David Shah --Licensed under the MIT License --This applies simple gain and white balance adjustments to the image, also converting 10-bit --RGB to 8-bit RGB. Like other processing blocks this operates on two pixels per clock entity image_gain_wb is generic ( --Red, green and blue channel gains in units of 1/8 red_gain : natural := 10; green_gain : natural := 7; blue_gain : natural := 9 ); port( clock : in std_logic; input_vsync : in std_logic; input_hsync : in std_logic; input_den : in std_logic; input_line_start : in std_logic; input_data_even : in std_logic_vector(29 downto 0); input_data_odd : in std_logic_vector(29 downto 0); output_vsync : out std_logic; output_hsync : out std_logic; output_den : out std_logic; output_line_start : out std_logic; output_data_even : out std_logic_vector(23 downto 0); output_data_odd : out std_logic_vector(23 downto 0) ); end image_gain_wb; architecture Behavioral of image_gain_wb is --Multiply a 10-bit number by a 4-bit natural and shift right to a 11-bit result function channel_mul(ch : std_logic_vector; gain : natural) return std_logic_vector is variable chvalue : unsigned(9 downto 0); variable gvalue : unsigned(3 downto 0); variable mul : unsigned(13 downto 0); variable result : std_logic_vector(10 downto 0); begin chvalue := unsigned(ch); gvalue := to_unsigned(gain, 4); mul := chvalue * gvalue; result := std_logic_vector(mul(13 downto 3)); return result; end channel_mul; --Divide an 11-bit number by 4 and clamp it to an 8 bit unsigned value function clamp_to_8bit(inp : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(7 downto 0); variable value : unsigned(10 downto 0); begin value := unsigned(inp); if value > 1023 then result := x"FF"; else result := std_logic_vector(value(9 downto 2)); end if; return result; end clamp_to_8bit; begin process(clock) begin if rising_edge(clock) then output_vsync <= input_vsync; output_hsync <= input_hsync; output_den <= input_den; output_line_start <= input_line_start; output_data_even(7 downto 0) <= clamp_to_8bit(channel_mul(input_data_even(9 downto 0), blue_gain)); output_data_even(15 downto 8) <= clamp_to_8bit(channel_mul(input_data_even(19 downto 10), green_gain)); output_data_even(23 downto 16) <= clamp_to_8bit(channel_mul(input_data_even(29 downto 20), red_gain)); output_data_odd(7 downto 0) <= clamp_to_8bit(channel_mul(input_data_odd(9 downto 0), blue_gain)); output_data_odd(15 downto 8) <= clamp_to_8bit(channel_mul(input_data_odd(19 downto 10), green_gain)); output_data_odd(23 downto 16) <= clamp_to_8bit(channel_mul(input_data_odd(29 downto 20), red_gain)); end if; end process; end Behavioral; ================================================ FILE: vhdl_rx/video-misc/simple_debayer.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Minimal Debayering Block for CSI-2 Rx --Copyright (C) 2016 David Shah --Licensed under the MIT License --This uses the simplest possible method to debayer two pixels per clock, --purely as a proof of concept to demo the CSI-2 Rx core. It is designed to go between --the CSI-2 Rx and the white balance/gain controller, also included in the example entity simple_debayer is port( clock : in std_logic; input_hsync : in std_logic; input_vsync : in std_logic; input_den : in std_logic; input_line_start : in std_logic; input_odd_line : in std_logic; input_data : in std_logic_vector(19 downto 0); input_prev_line_data : in std_logic_vector(19 downto 0); output_hsync : out std_logic; output_vsync : out std_logic; output_den : out std_logic; output_line_start : out std_logic; output_data_even : out std_logic_vector(29 downto 0); --10bit R:G:B output_data_odd : out std_logic_vector(29 downto 0) --10bit R:G:B ); end simple_debayer; architecture Behavioral of simple_debayer is signal last_block_c, last_block_p : std_logic_vector(19 downto 0); signal pre_hsync, pre_vsync, pre_den, pre_line_start : std_logic; signal pre_data_even, pre_data_odd : std_logic_vector(29 downto 0); function channel_average(val_1, val_2 : std_logic_vector) return std_logic_vector is variable sum : unsigned(10 downto 0); variable result : std_logic_vector(9 downto 0); begin sum := resize(unsigned(val_1), 11) + resize(unsigned(val_2), 11); result := std_logic_vector(sum(10 downto 1)); return result; end function; begin process(clock) variable pixel_0_R, pixel_0_G, pixel_0_B : std_logic_vector(9 downto 0); variable pixel_1_R, pixel_1_G, pixel_1_B : std_logic_vector(9 downto 0); begin if rising_edge(clock) then pre_hsync <= input_hsync; pre_vsync <= input_vsync; pre_den <= input_den; pre_line_start <= input_line_start; if input_odd_line = '1' then pixel_0_R := channel_average(input_data(19 downto 10), last_block_c(19 downto 10)); pixel_0_G := input_data(9 downto 0); pixel_0_B := input_prev_line_data(9 downto 0); pixel_1_R := input_data(19 downto 10); pixel_1_G := channel_average(input_data(9 downto 0), last_block_p(19 downto 10)); pixel_1_B := input_prev_line_data(9 downto 0); else pixel_0_R := channel_average(input_prev_line_data(19 downto 10), last_block_p(19 downto 10)); pixel_0_G := channel_average(input_data(19 downto 10), last_block_c(19 downto 10)); pixel_0_B := input_data(9 downto 0); pixel_1_R := input_prev_line_data(19 downto 10); pixel_1_G := input_data(19 downto 10); pixel_1_B := input_data(9 downto 0); end if; pre_data_even <= pixel_0_R & pixel_0_G & pixel_0_B; pre_data_odd <= pixel_1_R & pixel_1_G & pixel_1_B; output_hsync <= pre_hsync; output_vsync <= pre_vsync; output_den <= pre_den; output_line_start <= pre_line_start; output_data_even <= pre_data_even; output_data_odd <= pre_data_odd; if input_den = '1' then last_block_c <= input_data; last_block_p <= input_prev_line_data; end if; end if; end process; end architecture; ================================================ FILE: vhdl_rx/video-misc/test_pattern_gen.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Simple Test Square Generator --Copyright (C) 2016 David Shah --Licensed under the MIT License entity test_pattern_gen is generic( video_hlength : natural := 4046; --total visible and blanking pixels per line video_vlength : natural := 2190; --total visible and blanking lines per frame video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync video_hsync_len : natural := 48; --horizontal sync length in pixels video_hbp_len : natural := 122; --horizontal back porch length (excluding sync) video_h_visible : natural := 3840; --number of visible pixels per line video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync video_vsync_len : natural := 3; --vertical sync length in lines video_vbp_len : natural := 23; --vertical back porch length (excluding sync) video_v_visible : natural := 2160 --number of visible lines per frame ); port( pixel_clock : in std_logic; reset : in std_logic; --active high async reset video_vsync : out std_logic; video_hsync : out std_logic; video_den : out std_logic; video_line_start : out std_logic; --2 pixel per clock output video_pixel_even : out std_logic_vector(23 downto 0); video_pixel_odd : out std_logic_vector(23 downto 0) ); end test_pattern_gen; architecture Behavioral of test_pattern_gen is type pattern_colours_t is array(0 to 15) of std_logic_vector(23 downto 0); constant pattern_colours : pattern_colours_t := (x"FF0000", x"00FF00", x"0000FF", x"FFFFFF", x"AA0000", x"00AA00", x"0000AA", x"AAAAAA", x"550000", x"005500", x"000055", x"555555", x"FFFF00", x"FF00FF", x"00FFFF", x"000000"); signal pattern_index : unsigned(3 downto 0); signal pattern_value : std_logic_vector(23 downto 0); signal den_int : std_logic; signal pixel_x_div : natural range 0 to (video_h_visible / 2) - 1; signal pixel_x : natural range 0 to video_h_visible - 1; signal pixel_y : natural range 0 to video_v_visible - 1; begin pixel_x <= pixel_x_div * 2; pattern_index(1 downto 0) <= to_unsigned(pixel_x, 14)(4 downto 3); pattern_index(3 downto 2) <= to_unsigned(pixel_y, 14)(4 downto 3); pattern_value <= pattern_colours(to_integer(pattern_index)); video_pixel_even <= pattern_value when den_int = '1' else x"000000"; video_pixel_odd <= pattern_value when den_int = '1' else x"000000"; video_den <= den_int; tmg_gen : entity work.video_timing_ctrl generic map ( video_hlength => video_hlength / 2, --divide by two because two pixels per clock video_vlength => video_vlength, video_hsync_pol => video_hsync_pol, video_hsync_len => video_hsync_len / 2, video_hbp_len => video_hbp_len / 2, video_h_visible => video_h_visible / 2, video_vsync_pol => video_vsync_pol, video_vsync_len => video_vsync_len, video_vbp_len => video_vbp_len, video_v_visible => video_v_visible) port map( pixel_clock => pixel_clock, reset => reset, ext_sync => '0', timing_h_pos => open, timing_v_pos => open, pixel_x => pixel_x_div, pixel_y => pixel_y, video_vsync => video_vsync, video_hsync => video_hsync, video_den => den_int, video_line_start => video_line_start); end Behavioral; ================================================ FILE: vhdl_rx/video-misc/video_fb_output.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Framebuffer video output controller --Copyright (C) 2016 David Shah --Licensed under the MIT License entity video_fb_output is generic( video_hlength : natural := 2200; --total visible and blanking pixels per line video_vlength : natural := 1125; --total visible and blanking lines per frame video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync (does not affect framebuffer outputs) video_hsync_len : natural := 44; --horizontal sync length in pixels video_hbp_len : natural := 88; --horizontal back porch length (excluding sync) video_h_visible : natural := 1920; --number of visible pixels per line video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync video_vsync_len : natural := 5; --vertical sync length in lines video_vbp_len : natural := 4; --vertical back porch length (excluding sync) video_v_visible : natural := 1080 --number of visible lines per frame ); port( pixel_clock : in std_logic; reset : in std_logic; --active high async reset --Framebuffer controller interface fbc_vsync : out std_logic; fbc_data : in std_logic_vector(23 downto 0); --Output port timing signals --line_start is like hsync but always active high and only asserted for visible lines and for 1 clock cycle video_vsync : out std_logic; video_hsync : out std_logic; video_den : out std_logic; video_line_start : out std_logic; --Pixel output port video_data : out std_logic_vector(23 downto 0) ); end video_fb_output; architecture Behavioral of video_fb_output is signal timing_v_pos : natural range 0 to video_vlength - 1; signal timing_h_pos : natural range 0 to video_hlength - 1; signal den_int : std_logic; begin fbc_vsync <= '1' when timing_v_pos = 0 else '0'; video_data <= fbc_data when den_int = '1' else x"000000"; video_den <= den_int; tmg_gen : entity work.video_timing_ctrl generic map ( video_hlength => video_hlength, video_vlength => video_vlength, video_hsync_pol => video_hsync_pol, video_hsync_len => video_hsync_len, video_hbp_len => video_hbp_len, video_h_visible => video_h_visible, video_vsync_pol => video_vsync_pol, video_vsync_len => video_vsync_len, video_vbp_len => video_vbp_len, video_v_visible => video_v_visible) port map( pixel_clock => pixel_clock, reset => reset, ext_sync => '0', timing_h_pos => timing_h_pos, timing_v_pos => timing_v_pos, pixel_x => open, pixel_y => open, video_vsync => video_vsync, video_hsync => video_hsync, video_den => den_int, video_line_start => video_line_start); end Behavioral; ================================================ FILE: vhdl_rx/video-misc/video_register.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; --Pipeline register for video systems (supports up to 2 pixels per clock) --Copyright (C) 2016 David Shah --Licensed under the MIT License --Insert this where needed to obtain timing closure for the design entity video_register is port( clock : in std_logic; den_in : in std_logic; vsync_in : in std_logic; hsync_in : in std_logic; line_start_in : in std_logic; pixel_1_in : in std_logic_vector(23 downto 0); pixel_2_in : in std_logic_vector(23 downto 0); den_out : out std_logic; vsync_out : out std_logic; hsync_out : out std_logic; line_start_out : out std_logic; pixel_1_out : out std_logic_vector(23 downto 0); pixel_2_out : out std_logic_vector(23 downto 0) ); end entity; architecture Behavioral of video_register is begin process(clock) begin if rising_edge(clock) then den_out <= den_in; vsync_out <= vsync_in; hsync_out <= hsync_in; line_start_out <= line_start_in; pixel_1_out <= pixel_1_in; pixel_2_out <= pixel_2_in; end if; end process; end Behavioral; ================================================ FILE: vhdl_rx/video-misc/video_timing_ctrl.vhd ================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --Flexible Video Timing Controller --Copyright (C) 2016 David Shah --Licensed under the MIT License entity video_timing_ctrl is generic( video_hlength : natural := 2200; --total visible and blanking pixels per line video_vlength : natural := 1125; --total visible and blanking lines per frame video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync (does not affect framebuffer outputs) video_hsync_len : natural := 44; --horizontal sync length in pixels video_hbp_len : natural := 88; --horizontal back porch length (excluding sync) video_h_visible : natural := 1920; --number of visible pixels per line video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync video_vsync_len : natural := 5; --vertical sync length in lines video_vbp_len : natural := 4; --vertical back porch length (excluding sync) video_v_visible : natural := 1080; --number of visible lines per frame --H and V timing coordinates at rising edge of external sync input sync_v_pos : natural := 132; sync_h_pos : natural := 1079 ); port( pixel_clock : in std_logic; reset : in std_logic; --active high async reset --External sync input ext_sync : in std_logic; --Timing and pixel coordinate outputs timing_h_pos : out natural range 0 to video_hlength - 1; timing_v_pos : out natural range 0 to video_vlength - 1; pixel_x : out natural range 0 to video_h_visible - 1; pixel_y : out natural range 0 to video_v_visible - 1; --Traditional timing signals --line_start is like hsync but always active high and only asserted for visible lines and for 1 clock cycle video_vsync : out std_logic; video_hsync : out std_logic; video_den : out std_logic; video_line_start : out std_logic ); end video_timing_ctrl; architecture Behavioral of video_timing_ctrl is constant t_hsync_end : natural := video_hsync_len - 1; constant t_hvis_begin : natural := video_hsync_len + video_hbp_len; constant t_hvis_end : natural := t_hvis_begin + video_h_visible - 1; constant t_vsync_end : natural := video_vsync_len - 1; constant t_vvis_begin : natural := video_vsync_len + video_vbp_len; constant t_vvis_end : natural := t_vvis_begin + video_v_visible - 1; signal h_pos : natural range 0 to video_hlength - 1; signal v_pos : natural range 0 to video_vlength - 1; signal x_int : natural range 0 to video_h_visible - 1; signal y_int : natural range 0 to video_h_visible - 1; signal h_visible, v_visible : std_logic; signal hsync_pos, vsync_pos : std_logic; signal ext_sync_last : std_logic; signal ext_sync_curr : std_logic; begin --Basic counters process(pixel_clock, reset) begin if reset = '1' then h_pos <= 0; v_pos <= 0; elsif rising_edge(pixel_clock) then if ext_sync_curr = '1' and ext_sync_last = '0' then h_pos <= sync_h_pos; v_pos <= sync_v_pos; else if h_pos = video_hlength - 1 then h_pos <= 0; if v_pos = video_vlength - 1 then v_pos <= 0; else v_pos <= v_pos + 1; end if; else h_pos <= h_pos + 1; end if; end if; ext_sync_curr <= ext_sync; ext_sync_last <= ext_sync_curr; end if; end process; --Visible signals v_visible <= '1' when (v_pos >= t_vvis_begin) and (v_pos <= t_vvis_end) else '0'; h_visible <= '1' when (h_pos >= t_hvis_begin) and (h_pos <= t_hvis_end) else '0'; --Pixel coordinates x_int <= (h_pos - t_hvis_begin) when (h_visible = '1') and (v_visible = '1') else 0; y_int <= (v_pos - t_vvis_begin) when v_visible = '1' else 0; --den and line_start signals video_den <= h_visible and v_visible; video_line_start <= '1' when (v_visible = '1') and (h_pos = 0) else '0'; --Sync signals vsync_pos <= '1' when v_pos <= t_vsync_end else '0'; hsync_pos <= '1' when h_pos <= t_hsync_end else '0'; video_vsync <= vsync_pos when video_vsync_pol else not vsync_pos; video_hsync <= hsync_pos when video_hsync_pol else not hsync_pos; --External outputs timing_h_pos <= h_pos; timing_v_pos <= v_pos; pixel_x <= x_int; pixel_y <= y_int; end Behavioral;